init. 1AQQW051HEADmaster

325 files changed, 181239 insertions, 0 deletions

diff --git a/ReferenceCode/Chipset/SystemAgent/AcpiTables/Dmar/Dmar.act b/ReferenceCode/Chipset/SystemAgent/AcpiTables/Dmar/Dmar.act
new file mode 100644
index 0000000..122a3cc
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/AcpiTables/Dmar/Dmar.act
@@ -0,0 +1,340 @@
+/*++
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement
+--*/
+
+/*++
+
+Copyright (c)  1999 - 2013 Intel Corporation. All rights reserved
+This software and associated documentation (if any) is furnished
+under a license and may only be used or copied in accordance
+with the terms of the license. Except as permitted by such
+license, no part of this software or documentation may be
+reproduced, stored in a retrieval system, or transmitted in any
+form or by any means without the express written consent of
+Intel Corporation.
+
+
+Module Name:
+
+  Dmar.act
+
+Abstract:
+
+  This file describes the contents of the ACPI DMA address Remapping
+
+--*/
+
+#include "Dmar.h"
+
+EFI_ACPI_DMAR_TABLE DmarTable = {
+
+  EFI_ACPI_VTD_DMAR_TABLE_SIGNATURE,
+  sizeof (EFI_ACPI_DMAR_TABLE),
+  EFI_ACPI_DMAR_TABLE_REVISION,
+
+  //
+  // Checksum will be updated at runtime
+  //
+  0x00,
+
+  //
+  // It is expected that these values will be programmed at runtime
+  //
+  'I', 'N', 'T', 'E', 'L', ' ',
+  EFI_ACPI_DMAR_OEM_TABLE_ID,
+  0x1,
+  EFI_ACPI_DMAR_OEM_CREATOR_ID,
+  1,
+
+  //
+  // DMAR table specific entries below:
+  //
+
+  //
+  // 39-bit addressing Host Address Width
+  //
+  38,
+
+  //
+  // Flags
+  //
+  0,
+
+  //
+  // Reserved fields
+  //
+  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+
+  //
+  // First DRHD structure, VT-d Engine #1
+  //
+  {
+    0,                                          // Type = 0 (DRHD)
+    sizeof (EFI_ACPI_DRHD_ENGINE1_STRUCT),      // Length of structure
+    0,                                          // Flag - Do not include all - bugbug - not clear what this means
+    0,                                          // Reserved fields
+    0,                                          // Segment
+    0x00000000,                                 // Base address of DMA-remapping hardware - Updated at boot time
+
+    //
+    // Device Scopes
+    //
+    {
+      1,                                      // Type
+      sizeof (EFI_ACPI_DEV_SCOPE_STRUCTURE),  // Length
+      0,                                      // Segment number
+      0,                                      // Reserved
+      0,                                      // Start bus number
+      {2, 0}                                  // PCI path
+    }
+  },
+
+  //Second DRHD structure VT-d Engine# 2
+  {
+    0,                                         // Type = 0 (DRHD)
+    sizeof(EFI_ACPI_DRHD_ENGINE2_STRUCT),      // Length of strucure.
+    1,                                         // Flag - Include all
+    0,                                         // Reserved
+    0,                                         // Segment Number
+    0x00000000,                                // Base address of DMA-remapping hardware.
+
+    {
+      //
+      // Device Scopes
+      //
+      {
+        3,                                        // Type=IO APIC
+        sizeof (EFI_ACPI_DEV_SCOPE_STRUCTURE),    // Length
+        0,                                        // Reserved
+        2,                                        // Enumeration ID
+        0xF0,                                     // Start bus number
+        {31, 0}                                   // PCI path
+      },
+      //
+      // Device Scopes
+      //
+      {
+        4,                                        // Type=HPET
+        sizeof (EFI_ACPI_DEV_SCOPE_STRUCTURE),    // Length
+        0,                                        // Reserved
+        0,                                        // Enumeration ID
+        0xF0,                                     // Start bus number
+        {15, 0}                                   // PCI path
+      }
+      ,
+      //
+      // Device Scopes - I2C0
+      //
+      {
+        5,                                        // Type=ACPI_NAMESPACE_DEVICE
+        sizeof (EFI_ACPI_DEV_SCOPE_STRUCTURE),    // Length
+        0,                                        // Reserved
+        1,                                        // Enumeration ID
+        0,                                        // Start bus number
+        {21, 1}                                   // PCI path
+      },
+      //
+      // Device Scopes - I2C1
+      //
+      {
+        5,                                        // Type=ACPI_NAMESPACE_DEVICE
+        sizeof (EFI_ACPI_DEV_SCOPE_STRUCTURE),    // Length
+        0,                                        // Reserved
+        2,                                        // Enumeration ID
+        0,                                        // Start bus number
+        {21, 2}                                   // PCI path
+      },
+      //
+      // Device Scopes - SPI0
+      //
+      {
+        5,                                        // Type=ACPI_NAMESPACE_DEVICE
+        sizeof (EFI_ACPI_DEV_SCOPE_STRUCTURE),    // Length
+        0,                                        // Reserved
+        3,                                        // Enumeration ID
+        0,                                        // Start bus number
+        {21, 3}                                   // PCI path
+      },
+      //
+      // Device Scopes - SPI1
+      //
+      {
+        5,                                        // Type=ACPI_NAMESPACE_DEVICE
+        sizeof (EFI_ACPI_DEV_SCOPE_STRUCTURE),    // Length
+        0,                                        // Reserved
+        4,                                        // Enumeration ID
+        0,                                        // Start bus number
+        {21, 4}                                   // PCI path
+      },
+      //
+      // Device Scopes - UART0
+      //
+      {
+        5,                                        // Type=ACPI_NAMESPACE_DEVICE
+        sizeof (EFI_ACPI_DEV_SCOPE_STRUCTURE),    // Length
+        0,                                        // Reserved
+        5,                                        // Enumeration ID
+        0,                                        // Start bus number
+        {21, 5}                                   // PCI path
+      },
+      //
+      // Device Scopes - UART1
+      //
+      {
+        5,                                        // Type=ACPI_NAMESPACE_DEVICE
+        sizeof (EFI_ACPI_DEV_SCOPE_STRUCTURE),    // Length
+        0,                                        // Reserved
+        6,                                        // Enumeration ID
+        0,                                        // Start bus number
+        {21, 6}                                   // PCI path
+      },
+      //
+      // Device Scopes - SDIO
+      //
+      {
+        5,                                        // Type=ACPI_NAMESPACE_DEVICE
+        sizeof (EFI_ACPI_DEV_SCOPE_STRUCTURE),    // Length
+        0,                                        // Reserved
+        7,                                        // Enumeration ID
+        0,                                        // Start bus number
+        {23, 0}                                   // PCI path
+      }
+    }
+  },
+
+  //RMRR structure for USB devices.
+  {
+    0x1,                                       // Type 1 - RMRR structure
+    sizeof(EFI_ACPI_RMRR_USB_STRUC),           // Length
+    0x0000,                                    // Reserved
+    0x0000,                                    // Segment Num
+    0x00000000000E0000,                        // RMRR Base address - Updated in runtime.
+    0x00000000000EFFFF,                        // RMRR Limit address - Updated in runtime.
+    {
+      {
+        1,                                     // Type
+        sizeof(EFI_ACPI_DEV_SCOPE_STRUCTURE),  // Length
+        0,                                     // Reserved
+        0,                                     // Enum ID
+        0,                                     // Start bus number
+        {29, 0}                                // PCI path
+      },
+      {
+        1,                                     // Type
+        sizeof(EFI_ACPI_DEV_SCOPE_STRUCTURE),  // Length
+        0,                                     // Reserved
+        0,                                     // Enum ID
+        0,                                     // Start bus number
+        {26, 0}                                // PCI path
+      },
+      {
+        1,                                     // Type
+        sizeof(EFI_ACPI_DEV_SCOPE_STRUCTURE),  // Length
+        0,                                     // Reserved
+        0,                                     // Enum ID
+        0,                                     // Start bus number
+        {20, 0}                                // PCI path
+      }
+    }
+  },
+
+  //RMRR structure for IGD device.
+  {
+    1,                                        // Type 1 - RMRR structure
+    sizeof(EFI_ACPI_RMRR_IGD_STRUC),          // Length
+    0x0000,                                   // Reserved
+    0x0000,                                   // Segment Num
+    0x0000000000000000,                       // RMRR Base address - Updated in runtime.
+    0x0000000000000000,                       // RMRR Limit address - Updated in runtime.
+    {
+      {
+        1,                                    // Type
+        sizeof(EFI_ACPI_DEV_SCOPE_STRUCTURE), // Length
+        0,                                    // Reserved
+        0,                                    // Enum ID
+        0,                                    // Start bus number
+        {2, 0}                                // PCI path
+      }
+    }
+  }
+  ,
+
+  // ANDD structure.
+  {
+    4,                                        // Type 4 - ANDD structure
+    sizeof(EFI_ACPI_ANDD_STRUC),              // Length
+    0, 0, 0,                                  // Reserved [3]
+    1,
+    "\\_SB.PCI0.I2C0"
+  },
+
+  // ANDD structure.
+  {
+    4,                                        // Type 4 - ANDD structure
+    sizeof(EFI_ACPI_ANDD_STRUC),              // Length
+    0, 0, 0,                                  // Reserved [3]
+    2,
+    "\\_SB.PCI0.I2C1"
+  },
+
+  // ANDD structure.
+  {
+    4,                                        // Type 4 - ANDD structure
+    sizeof(EFI_ACPI_ANDD_STRUC),              // Length
+    0, 0, 0,                                  // Reserved [3]
+    3,
+    "\\_SB.PCI0.SPI0"
+  },
+
+  // ANDD structure.
+  {
+    4,                                        // Type 4 - ANDD structure
+    sizeof(EFI_ACPI_ANDD_STRUC),              // Length
+    0, 0, 0,                                  // Reserved [3]
+    4,
+    "\\_SB.PCI0.SPI1"
+  },
+
+  // ANDD structure.
+  {
+    4,                                        // Type 4 - ANDD structure
+    sizeof(EFI_ACPI_ANDD_STRUC),              // Length
+    0, 0, 0,                                  // Reserved [3]
+    5,
+    "\\_SB.PCI0.UA00"
+  },
+
+  // ANDD structure.
+  {
+    4,                                        // Type 4 - ANDD structure
+    sizeof(EFI_ACPI_ANDD_STRUC),              // Length
+    0, 0, 0,                                  // Reserved [3]
+    6,
+    "\\_SB.PCI0.UA01"
+  },
+
+  // ANDD structure.
+  {
+    4,                                        // Type 4 - ANDD structure
+    sizeof(EFI_ACPI_ANDD_STRUC),              // Length
+    0, 0, 0,                                  // Reserved [3]
+    7,
+    "\\_SB.PCI0.SDHC"
+  }
+};
+
+//
+// Dummy function required for build tools
+//
+int
+main (
+  VOID
+  )
+{
+  return 0;
+}
\ No newline at end of file
diff --git a/ReferenceCode/Chipset/SystemAgent/AcpiTables/Dmar/Dmar.h b/ReferenceCode/Chipset/SystemAgent/AcpiTables/Dmar/Dmar.h
new file mode 100644
index 0000000..0025a02
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/AcpiTables/Dmar/Dmar.h
@@ -0,0 +1,39 @@
+/** @file
+  This file describes the contents of the ACPI DMA address Remapping
+  Some additional ACPI values are defined in Acpi1_0.h and Acpi2_0.h.
+
+@copyright
+  Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement
+**/
+#ifndef _SA_DMAR_H_
+#define _SA_DMAR_H_
+
+///
+/// Include standard ACPI table definitions
+///
+#include "Acpi1_0.h"
+#include "Acpi2_0.h"
+#include "Acpi3_0.h"
+#include "DmaRemappingTable.h"
+
+#pragma pack(1)
+
+#define EFI_ACPI_DMAR_OEM_TABLE_ID    0x20575348  ///< "HSW "
+#define EFI_ACPI_DMAR_OEM_CREATOR_ID  0x4C544E49  ///< "INTL"
+#pragma pack()
+
+#endif
diff --git a/ReferenceCode/Chipset/SystemAgent/AcpiTables/HOST_BUS.ASL b/ReferenceCode/Chipset/SystemAgent/AcpiTables/HOST_BUS.ASL
new file mode 100644
index 0000000..439736e
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/AcpiTables/HOST_BUS.ASL
@@ -0,0 +1,770 @@
+/*++
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement
+--*/
+
+/*++
+
+Copyright (c)  1999 - 2013 Intel Corporation. All rights reserved
+This software and associated documentation (if any) is furnished
+under a license and may only be used or copied in accordance
+with the terms of the license. Except as permitted by such
+license, no part of this software or documentation may be
+reproduced, stored in a retrieval system, or transmitted in any
+form or by any means without the express written consent of
+Intel Corporation.
+
+
+Module Name:
+
+  HOST_BUS.ASL
+
+Abstract:
+
+  SystemAgent PCI configuration space definition.
+
+--*/
+
+
+  //
+  // Define various System Agent (SA) PCI Configuration Space
+  // registers which will be used to dynamically produce all
+  // resources in the Host Bus _CRS.
+  //
+OperationRegion (HBUS, PCI_Config, 0x00, 0x100)
+Field (HBUS, DWordAcc, NoLock, Preserve)
+{
+  Offset(0x40),   // EPBAR (0:0:0:40)
+  EPEN, 1,        // Enable
+      , 11,
+  EPBR, 20,       // EPBAR [31:12]
+
+  Offset(0x48),   // MCHBAR (0:0:0:48)
+  MHEN, 1,        // Enable
+      , 14,
+  MHBR, 17,       // MCHBAR [31:15]
+
+  Offset(0x50),   // GGC (0:0:0:50)
+  GCLK, 1,        // GGCLCK
+
+  Offset(0x54),   // DEVEN (0:0:0:54)
+  D0EN, 1,        // DEV0 Enable
+  D1F2, 1,        // DEV1 FUN2 Enable
+  D1F1, 1,        // DEV1 FUN1 Enable
+  D1F0, 1,        // DEV1 FUN0 Enable
+
+  Offset(0x60),   // PCIEXBAR (0:0:0:60)
+  PXEN, 1,        // Enable
+  PXSZ, 2,        // PCI Express Size
+      , 23,
+  PXBR, 6,        // PCI Express BAR [31:26]
+
+  Offset(0x68),   // DMIBAR (0:0:0:68)
+  DIEN, 1,        // Enable
+      , 11,
+  DIBR, 20,       // DMIBAR [31:12]
+
+  Offset(0x70),   // MESEG_BASE (0:0:0:70)
+      , 20,
+  MEBR, 12,       // MESEG_BASE [31:20]
+
+  Offset(0x80),   // PAM0 Register (0:0:0:80)
+      , 4,
+  PM0H, 2,        // PAM 0, High Nibble
+      , 2,
+
+  Offset(0x81),   // PAM1 Register (0:0:0:81)
+  PM1L, 2,        // PAM1, Low  Nibble
+      , 2,
+  PM1H, 2,        // PAM1, High Nibble
+      , 2,
+
+  Offset(0x82),   // PAM2 Register (0:0:0:82)
+  PM2L, 2,        // PAM2, Low  Nibble
+      , 2,
+  PM2H, 2,        // PAM2, High Nibble
+      , 2,
+
+  Offset(0x83),   // PAM3 Register (0:0:0:83)
+  PM3L, 2,        // PAM3, Low  Nibble
+      , 2,
+  PM3H, 2,        // PAM3, High Nibble
+      , 2,
+
+  Offset(0x84),   // PAM4 Register (0:0:0:84)
+  PM4L, 2,        // PAM4, Low  Nibble
+      , 2,
+  PM4H, 2,        // PAM4, High Nibble
+      , 2,
+
+  Offset(0x85),   // PAM5 Register (0:0:0:85)
+  PM5L, 2,        // PAM5, Low  Nibble
+      , 2,
+  PM5H, 2,        // PAM5, High Nibble
+      , 2,
+
+  Offset(0x86),   // PAM6 Register (0:0:0:86)
+  PM6L, 2,        // PAM6, Low  Nibble
+      , 2,
+  PM6H, 2,        // PAM6, High Nibble
+      , 2,
+
+  Offset(0xA8),   // Top of Upper Usable DRAM Register (0:0:0:A8)
+      , 20,
+  TUUD, 19,       // TOUUD [38:20]
+
+  Offset(0xBC),   // Top of Lower Usable DRAM Register (0:0:0:BC)
+      , 20,
+  TLUD, 12,       // TOLUD [31:20]
+
+  Offset(0xC8),   // ERRSTS register (0:0:0:C8)
+      , 7,
+  HTSE, 1         // Host Thermal Sensor Event for SMI/SCI/SERR
+}
+
+OperationRegion (MCHT, SystemMemory, 0xFED10000, 0x1100)
+
+// Define a buffer that will store all the bus, memory, and IO information
+// relating to the Host Bus.  This buffer will be dynamically altered in
+// the _CRS and passed back to the OS.
+
+Name(BUF0,ResourceTemplate()
+{
+  // Bus Number Allocation: Bus 0 to 0xFF
+
+  WORDBusNumber(ResourceProducer,MinFixed,MaxFixed,PosDecode,0x00,
+    0x0000,0x00FF,0x00,0x0100,,,PB00)
+
+  // I/O Region Allocation 0 ( 0x0000 - 0x0CF7 )
+
+  DWordIo(ResourceProducer,MinFixed,MaxFixed,PosDecode,EntireRange,
+    0x00,0x0000,0x0CF7,0x00,0x0CF8,,,PI00)
+
+  // PCI Configuration Registers ( 0x0CF8 - 0x0CFF )
+
+  Io(Decode16,0x0CF8,0x0CF8,1,0x08)
+
+  // I/O Region Allocation 1 ( 0x0D00 - 0xFFFF )
+
+  DWordIo(ResourceProducer,MinFixed,MaxFixed,PosDecode,EntireRange,
+    0x00,0x0D00,0xFFFF,0x00,0xF300,,,PI01)
+
+  // Video Buffer Area ( 0xA0000 - 0xBFFFF )
+
+  DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable,
+    ReadWrite,0x00,0xA0000,0xBFFFF,0x00,0x20000,,,A000)
+
+  // ISA Add-on BIOS Area ( 0xC0000 - 0xC3FFF )
+
+  DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable,
+    ReadWrite,0x00,0xC0000,0xC3FFF,0x00,0x4000,,,C000)
+
+  // ISA Add-on BIOS Area ( 0xC4000 - 0xC7FFF )
+
+  DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable,
+    ReadWrite,0x00,0xC4000,0xC7FFF,0x00,0x4000,,,C400)
+
+  // ISA Add-on BIOS Area ( 0xC8000 - 0xCBFFF )
+
+  DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable,
+    ReadWrite,0x00,0xC8000,0xCBFFF,0x00,0x4000,,,C800)
+
+  // ISA Add-on BIOS Area ( 0xCC000 - 0xCFFFF )
+
+  DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable,
+    ReadWrite,0x00,0xCC000,0xCFFFF,0x00,0x4000,,,CC00)
+
+  // ISA Add-on BIOS Area ( 0xD0000 - 0xD3FFF )
+
+  DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable,
+    ReadWrite,0x00,0xD0000,0xD3FFF,0x00,0x4000,,,D000)
+
+  // ISA Add-on BIOS Area ( 0xD4000 - 0xD7FFF )
+
+  DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable,
+    ReadWrite,0x00,0xD4000,0xD7FFF,0x00,0x4000,,,D400)
+
+  // ISA Add-on BIOS Area ( 0xD8000 - 0xDBFFF )
+
+  DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable,
+    ReadWrite,0x00,0xD8000,0xDBFFF,0x00,0x4000,,,D800)
+
+  // ISA Add-on BIOS Area ( 0xDC000 - 0xDFFFF )
+
+  DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable,
+    ReadWrite,0x00,0xDC000,0xDFFFF,0x00,0x4000,,,DC00)
+
+  // BIOS Extension Area ( 0xE0000 - 0xE3FFF )
+
+  DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable,
+    ReadWrite,0x00,0xE0000,0xE3FFF,0x00,0x4000,,,E000)
+
+  // BIOS Extension Area ( 0xE4000 - 0xE7FFF )
+
+  DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable,
+    ReadWrite,0x00,0xE4000,0xE7FFF,0x00,0x4000,,,E400)
+
+  // BIOS Extension Area ( 0xE8000 - 0xEBFFF )
+
+  DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable,
+    ReadWrite,0x00,0xE8000,0xEBFFF,0x00,0x4000,,,E800)
+
+  // BIOS Extension Area ( 0xEC000 - 0xEFFFF )
+
+  DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable,
+    ReadWrite,0x00,0xEC000,0xEFFFF,0x00,0x4000,,,EC00)
+
+  // BIOS Area ( 0xF0000 - 0xFFFFF )
+
+  DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable,
+    ReadWrite,0x00,0xF0000,0xFFFFF,0x00,0x10000,,,F000)
+
+//  // Memory Hole Region ( 0xF00000 - 0xFFFFFF )
+//
+//  DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable,
+//    ReadWrite,0x00,0xF00000,0xFFFFFF,0x00,0x100000,,,HOLE)
+
+  // PCI Memory Region ( TOLUD - 0xFEAFFFFF )
+
+  DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable,
+    ReadWrite,0x00,0x00000000,0xFEAFFFFF,0x00,0xFEB00000,,,PM01)
+})
+
+Method(_CRS,0,Serialized)
+{
+  // Fix up Max Bus Number and Length
+  CreateWordField(BUF0, ^PB00._MAX, PBMX)
+  Store(Subtract(ShiftRight(\PELN,20),2), PBMX)
+  CreateWordField(BUF0, ^PB00._LEN, PBLN)
+  Store(Subtract(ShiftRight(\PELN,20),1), PBLN)
+  // Fix up all of the Option ROM areas from 0xC0000-0xFFFFF.
+  //
+
+  If(PM1L)  // \_SB.PCI0
+  {
+      // PAMx != 0.  Set length = 0.
+
+      CreateDwordField(BUF0, ^C000._LEN,C0LN)
+      Store(Zero,C0LN)
+  }
+
+  If(LEqual(PM1L,1))
+  {
+      CreateBitField(BUF0, ^C000._RW,C0RW)
+      Store(Zero,C0RW)
+  }
+
+  If(PM1H)
+  {
+      CreateDwordField(BUF0, ^C400._LEN,C4LN)
+      Store(Zero,C4LN)
+  }
+
+  If(LEqual(PM1H,1))
+  {
+      CreateBitField(BUF0, ^C400._RW,C4RW)
+      Store(Zero,C4RW)
+  }
+
+  If(PM2L)
+  {
+      CreateDwordField(BUF0, ^C800._LEN,C8LN)
+      Store(Zero,C8LN)
+  }
+
+  If(LEqual(PM2L,1))
+  {
+      CreateBitField(BUF0, ^C800._RW,C8RW)
+      Store(Zero,C8RW)
+  }
+
+  If(PM2H)
+  {
+      CreateDwordField(BUF0, ^CC00._LEN,CCLN)
+      Store(Zero,CCLN)
+  }
+
+  If(LEqual(PM2H,1))
+  {
+      CreateBitField(BUF0, ^CC00._RW,CCRW)
+      Store(Zero,CCRW)
+  }
+
+  If(PM3L)
+  {
+      CreateDwordField(BUF0, ^D000._LEN,D0LN)
+      Store(Zero,D0LN)
+  }
+
+  If(LEqual(PM3L,1))
+  {
+      CreateBitField(BUF0, ^D000._RW,D0RW)
+      Store(Zero,D0RW)
+  }
+
+  If(PM3H)
+  {
+      CreateDwordField(BUF0, ^D400._LEN,D4LN)
+      Store(Zero,D4LN)
+  }
+
+  If(LEqual(PM3H,1))
+  {
+      CreateBitField(BUF0, ^D400._RW,D4RW)
+      Store(Zero,D4RW)
+  }
+
+  If(PM4L)
+  {
+      CreateDwordField(BUF0, ^D800._LEN,D8LN)
+      Store(Zero,D8LN)
+  }
+
+  If(LEqual(PM4L,1))
+  {
+      CreateBitField(BUF0, ^D800._RW,D8RW)
+      Store(Zero,D8RW)
+  }
+
+  If(PM4H)
+  {
+      CreateDwordField(BUF0, ^DC00._LEN,DCLN)
+      Store(Zero,DCLN)
+  }
+
+  If(LEqual(PM4H,1))
+  {
+      CreateBitField(BUF0, ^DC00._RW,DCRW)
+      Store(Zero,DCRW)
+  }
+
+  If(PM5L)
+  {
+      CreateDwordField(BUF0, ^E000._LEN,E0LN)
+      Store(Zero,E0LN)
+  }
+
+  If(LEqual(PM5L,1))
+  {
+      CreateBitField(BUF0, ^E000._RW,E0RW)
+      Store(Zero,E0RW)
+  }
+
+  If(PM5H)
+  {
+      CreateDwordField(BUF0, ^E400._LEN,E4LN)
+      Store(Zero,E4LN)
+  }
+
+  If(LEqual(PM5H,1))
+  {
+      CreateBitField(BUF0, ^E400._RW,E4RW)
+      Store(Zero,E4RW)
+  }
+
+  If(PM6L)
+  {
+      CreateDwordField(BUF0, ^E800._LEN,E8LN)
+      Store(Zero,E8LN)
+  }
+
+  If(LEqual(PM6L,1))
+  {
+      CreateBitField(BUF0, ^E800._RW,E8RW)
+      Store(Zero,E8RW)
+  }
+
+  If(PM6H)
+  {
+      CreateDwordField(BUF0, ^EC00._LEN,ECLN)
+      Store(Zero,ECLN)
+  }
+
+  If(LEqual(PM6H,1))
+  {
+      CreateBitField(BUF0, ^EC00._RW,ECRW)
+      Store(Zero,ECRW)
+  }
+
+  If(PM0H)
+  {
+      CreateDwordField(BUF0, ^F000._LEN,F0LN)
+      Store(Zero,F0LN)
+  }
+
+  If(LEqual(PM0H,1))
+  {
+      CreateBitField(BUF0, ^F000._RW,F0RW)
+      Store(Zero,F0RW)
+  }
+
+//  // Enable the 1MB region between 15-16MB if HENA = 1.
+//
+//  If( MCHC.HENA)
+//  {
+//    CreateDwordField(BUF0, HOLE._LEN,H0LN)
+//    Store(0x100000,H0LN)
+//  }
+
+  // Create pointers to Memory Sizing values.
+
+  CreateDwordField(BUF0, ^PM01._MIN,M1MN)
+  CreateDwordField(BUF0, ^PM01._MAX,M1MX)
+  CreateDwordField(BUF0, ^PM01._LEN,M1LN)
+
+  // Set Memory Size Values. TLUD represents bits 31:20 of phyical
+  // TOM, so shift these bits into the correct position and fix up
+  // the Memory Region available to PCI.
+
+  ShiftLeft( TLUD,20,M1MN)
+  Add(Subtract(M1MX,M1MN),1,M1LN)
+
+  Return(BUF0)
+}
+
+//Name(GUID,UUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))
+Name(GUID,Buffer(){0x5b, 0x4d, 0xdb, 0x33,
+          0xf7, 0x1f,
+          0x1c, 0x40,
+          0x96, 0x57,
+          0x74, 0x41, 0xc0, 0x3d, 0xd7, 0x66})
+
+
+Name(SUPP,0)  // PCI _OSC Support Field value
+Name(CTRL,0)  // PCI _OSC Control Field value
+Name(XCNT, 0) // Variable used in _OSC for counting
+
+Method(_OSC,4,Serialized)
+{ // Check for proper UUID
+  // Save the capabilities buffer
+  Store(Arg3,Local0)
+
+  // Create DWord-adressable fields from the Capabilties Buffer
+  CreateDWordField(Local0,0,CDW1)
+  CreateDWordField(Local0,4,CDW2)
+  CreateDWordField(Local0,8,CDW3)
+
+
+  //
+  // This provides a facility for the PCH reference code to expose USB XHCI controllers to the OS.
+  // Refer to Intel PCH reference code for further details.
+  //
+  if (\_SB.PCI0.XHC.CUID(Arg0)) {
+    Return (\_SB.PCI0.XHC.POSC(Arg1, Arg2, Arg3))
+  } else {
+    If (LGreaterEqual(OSYS,2012)) {
+      If(LEqual(XCNT, 0)) {
+        \_SB.PCI0.XHC.XSEL()
+        Increment(XCNT)
+      }
+    }
+  }
+
+  // Check for proper UUID
+#ifdef AMI_ORIGINAL_FOR_FIX_UUID_INVALID
+  If(LAnd(LEqual(Arg0,GUID),NEXP))
+#else // AMI_ORIGINAL_FOR_FIX_UUID_INVALID
+  If(LEqual(Arg0,GUID))
+#endif // AMI_ORIGINAL_FOR_FIX_UUID_INVALID
+  {
+    // Save Capabilities DWord2 & 3
+    Store(CDW2,SUPP)
+    Store(CDW3,CTRL)
+
+    // You can clear bits in CTRL here if you don't want OS to take
+    // control
+
+//    And(CTRL, 0xFFFFFFF8, CTRL)       // disable Native hot plug, PME
+
+#ifdef AMI_ORIGINAL_FOR_FIX_UUID_INVALID
+    If(Not(And(CDW1,1)))  // Query flag clear?
+    { // Disable GPEs for features granted native control.
+      If(And(CTRL,0x01))
+      {
+        NHPG()
+      }
+      If(And(CTRL,0x04))  // PME control granted?
+      {
+        NPME()
+      }
+    }
+#else // AMI_ORIGINAL_FOR_FIX_UUID_INVALID
+    If (LEqual(NEXP,0)) 
+    {
+       And(CTRL, 0xFFFFFFF8, CTRL)       // disable Native hot plug, PME
+    }
+
+    If (NEXP) 
+    {
+       If(Not(And(CDW1,1)))  // Query flag clear?
+       { // Disable GPEs for features granted native control.
+         If(And(CTRL,0x01))
+         {
+           NHPG()
+         }
+         If(And(CTRL,0x04))  // PME control granted?
+         {
+           NPME()
+         }
+       }
+    } 
+
+#endif // AMI_ORIGINAL_FOR_FIX_UUID_INVALID
+
+    If(LNotEqual(Arg1,One))
+    { // Unknown revision
+      Or(CDW1,0x08,CDW1)
+    }
+
+    If(LNotEqual(CDW3,CTRL))
+    { // Capabilities bits were masked
+      Or(CDW1,0x10,CDW1)
+    }
+    // Update DWORD3 in the buffer
+    Store(CTRL,CDW3)
+    Store(CTRL,OSCC)
+    Return(Local0)
+  } Else {
+    Or(CDW1,4,CDW1)   // Unrecognized UUID
+    Return(Local0)
+  }
+} // End _OSC
+
+// Added code for Dual IRQ support. Two set of ACPI IRQ tables were generated.
+// Code has been added to select the appropriate IRQ table by checking the CPUID.
+Scope(\_SB.PCI0)
+{
+	Method(AR00) {
+		Return(\_SB.AR00)
+
+	}
+
+	Method(PR00) {
+		Return(\_SB.PR00)
+	}
+
+#if defined(ASL_PCI_BRIDGE_DISABLE) && (ASL_PCI_BRIDGE_DISABLE == 0)
+	Method(AR01) {
+		Return(\_SB.AR01)
+	}
+
+	Method(PR01) {
+		Return(\_SB.PR01)
+	}
+#endif
+
+#ifdef AMI_ORIGINAL_FOR_DISABLE_PCIE_SLOT
+	Method(AR02) {
+		Return(\_SB.AR02)
+	}
+
+	Method(PR02) {
+		Return(\_SB.PR02)
+	}
+
+	Method(AR04) {
+		Return(\_SB.AR04)
+	}
+
+	Method(PR04) {
+		Return(\_SB.PR04)
+	}
+
+	Method(AR05) {
+		Return(\_SB.AR05)
+	}
+
+	Method(PR05) {
+		Return(\_SB.PR05)
+	}
+
+	Method(AR06) {
+		Return(\_SB.AR06)
+	}
+
+	Method(PR06) {
+		Return(\_SB.PR06)
+	}
+
+	Method(AR07) {
+		Return(\_SB.AR07)
+	}
+
+	Method(PR07) {
+		Return(\_SB.PR07)
+	}
+
+	Method(AR08) {
+		Return(\_SB.AR08)
+	}
+
+	Method(PR08) {
+		Return(\_SB.PR08)
+	}
+
+	Method(AR09) {
+		Return(\_SB.AR09)
+	}
+
+	Method(PR09) {
+		Return(\_SB.PR09)
+	}
+
+	Method(AR0A) {
+		Return(\_SB.AR0A)
+	}
+
+	Method(PR0A) {
+		Return(\_SB.PR0A)
+	}
+
+	Method(AR0B) {
+		Return(\_SB.AR0B)
+	}
+
+	Method(PR0B) {
+		Return(\_SB.PR0B)
+  }
+#else // AMI_ORIGINAL_FOR_DISABLE_PCIE_SLOT
+#if defined(ASL_RC_PEG_0) && (ASL_RC_PEG_0 == 1)
+	Method(AR02) {
+		Return(\_SB.AR02)
+	}
+
+	Method(PR02) {
+		Return(\_SB.PR02)
+	}
+#endif
+
+#if defined (ASL_RC_PORT_0) && (ASL_RC_PORT_0 == 1)
+	Method(AR04) {
+		Return(\_SB.AR04)
+	}
+
+	Method(PR04) {
+		Return(\_SB.PR04)
+	}
+
+#if defined (ASL_RC_PORT_1) && (ASL_RC_PORT_1 == 1)
+	Method(AR05) {
+		Return(\_SB.AR05)
+	}
+
+	Method(PR05) {
+		Return(\_SB.PR05)
+	}
+#endif
+
+#if defined (ASL_RC_PORT_2) && (ASL_RC_PORT_2 == 1)
+	Method(AR06) {
+		Return(\_SB.AR06)
+	}
+
+	Method(PR06) {
+		Return(\_SB.PR06)
+	}
+#endif
+
+#if defined (ASL_RC_PORT_3) && (ASL_RC_PORT_3 == 1)
+	Method(AR07) {
+		Return(\_SB.AR07)
+	}
+
+	Method(PR07) {
+		Return(\_SB.PR07)
+	}
+#endif
+
+#if defined (ASL_RC_PORT_4) && (ASL_RC_PORT_4 == 1)
+	Method(AR08) {
+		Return(\_SB.AR08)
+	}
+
+	Method(PR08) {
+		Return(\_SB.PR08)
+	}
+#endif
+
+#if defined (ASL_RC_PORT_5) && (ASL_RC_PORT_5 == 1)
+	Method(AR09) {
+		Return(\_SB.AR09)
+	}
+
+	Method(PR09) {
+		Return(\_SB.PR09)
+	}
+#endif
+
+#if defined (ASL_RC_PORT_6) && (ASL_RC_PORT_6 == 1)
+	Method(AR0E) {
+		Return(\_SB.AR0E)
+	}
+
+	Method(PR0E) {
+		Return(\_SB.PR0E)
+	}
+#endif
+
+#if defined (ASL_RC_PORT_7) && (ASL_RC_PORT_7 == 1)
+	Method(AR0F) {
+		Return(\_SB.AR0F)
+	}
+
+	Method(PR0F) {
+		Return(\_SB.PR0F)
+	}
+#endif
+#endif
+
+#if defined(ASL_RC_PEG_1) && (ASL_RC_PEG_1 == 1)
+	Method(AR0A) {
+		Return(\_SB.AR0A)
+	}
+
+	Method(PR0A) {
+		Return(\_SB.PR0A)
+	}
+
+#if defined(ASL_RC_PEG_2) && (ASL_RC_PEG_2 == 1)
+	Method(AR0B) {
+		Return(\_SB.AR0B)
+	}
+
+	Method(PR0B) {
+		Return(\_SB.PR0B)
+    }
+#endif
+#endif
+#endif // AMI_ORIGINAL_FOR_DISABLE_PCIE_SLOT
+}
+
+#ifndef AMI_OVERRIDE_FOR_TPM_AREA_REPORT
+Device(TPMX)
+{
+  Name(_HID, EISAID("PNP0C01"))   // Hardware Device ID
+  Name(_UID, 1)
+
+  Name(CRS, ResourceTemplate()
+  {
+    Memory32Fixed(ReadOnly, 0xFED40000, 0x5000, TPMR) //Non-writeable
+  })
+
+  Method (_CRS, 0)
+  {
+      Return(CRS)
+  }
+    // if TPM is active, TPM module will report TPM area to OS.
+  Method (_STA, 0)
+  {
+    If(TPMF)
+    {
+        Return(0x00)
+    }
+     Return(0x0F)
+  }
+}
+#endif // AMI_OVERRIDE_FOR_TPM_AREA_REPORT
diff --git a/ReferenceCode/Chipset/SystemAgent/AcpiTables/SaAcpiTables.cif b/ReferenceCode/Chipset/SystemAgent/AcpiTables/SaAcpiTables.cif
new file mode 100644
index 0000000..3dc05f6
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/AcpiTables/SaAcpiTables.cif
@@ -0,0 +1,18 @@
+<component>
+	name = "SaAcpiTables"
+	category = ModulePart
+	LocalRoot = "ReferenceCode\Chipset\SystemAgent\AcpiTables"
+	RefName = "SaAcpiTables"
+[files]
+"SaAcpiTables.sdl"	
+"SaAcpiTables.mak"	
+"HOST_BUS.ASL"	
+"Dmar\Dmar.act"	
+"Dmar\Dmar.h"	
+"SaAcpiTables.inf"	
+"SaAcpiTables_Edk.inf"	
+[parts]
+"SaSsdtTables"
+"SgAcpiTablesPeg"
+"SgAcpiTablesPch"
+<endComponent>
diff --git a/ReferenceCode/Chipset/SystemAgent/AcpiTables/SaAcpiTables.inf b/ReferenceCode/Chipset/SystemAgent/AcpiTables/SaAcpiTables.inf
new file mode 100644
index 0000000..3439079
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/AcpiTables/SaAcpiTables.inf
@@ -0,0 +1,54 @@
+## @file
+#  Component description file for the ACPI tables
+#
+#@copyright
+#  Copyright (c)  1999 - 2012 Intel Corporation. All rights reserved
+#  This software and associated documentation (if any) is furnished
+#  under a license and may only be used or copied in accordance
+#  with the terms of the license. Except as permitted by such
+#  license, no part of this software or documentation may be
+#  reproduced, stored in a retrieval system, or transmitted in any
+#  form or by any means without the express written consent of
+#  Intel Corporation.
+#
+#  This file contains a 'Sample Driver' and is licensed as such
+#  under the terms of your license agreement with Intel or your
+#  vendor.  This file may be modified by the user, subject to
+#  the additional terms of the license agreement
+#
+
+[defines]
+BASE_NAME            = SaAcpiTables
+FILE_GUID            = 27E569D5-0AFC-4D8F-8C90-783AC4A318AB
+COMPONENT_TYPE       = ACPITABLE
+FFS_EXT              = .ffs
+
+[sources.common]
+  Dmar/Dmar.act
+  Dmar/Dmar.h
+
+[libraries.common]
+
+[includes.common]
+  .
+  $(EFI_SOURCE)
+  $(EFI_SOURCE)/Include
+  $(EFI_SOURCE)/$(PROJECT_SA_ROOT)/Include
+  $(EDK_SOURCE)/Foundation/Efi
+  $(EDK_SOURCE)/Foundation/Include
+  $(EDK_SOURCE)/Foundation/Efi/Include
+  $(EDK_SOURCE)/Foundation/Framework/Include
+  $(EFI_SOURCE)/Include/IndustryStandard
+  $(EDK_SOURCE)/Foundation/Include/IndustryStandard
+  $(EDK_SOURCE)/Foundation/Library/Dxe/Include
+  $(EDK_SOURCE)/Foundation
+  $(EDK_SOURCE)/Foundation/Framework
+
+#
+# Typically the sample code referenced will be available in the code base already
+# So keep this include at the end to defer to the source base definition
+# and only use the sample code definition if source base does not include these files.
+#
+  $(EFI_SOURCE)/$(PROJECT_SA_ROOT)/SampleCode/Include
+
+[nmake.common]
diff --git a/ReferenceCode/Chipset/SystemAgent/AcpiTables/SaAcpiTables.mak b/ReferenceCode/Chipset/SystemAgent/AcpiTables/SaAcpiTables.mak
new file mode 100644
index 0000000..c4cd7e7
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/AcpiTables/SaAcpiTables.mak
@@ -0,0 +1,41 @@
+all : SaAcpiTables
+
+SaAcpiTables : $(BUILD_DIR)\SaAcpiTables.ffS
+
+SaAcpiTables_Includes = \
+	$(EDK_INCLUDES)\
+	$(INTEL_MCH_INCLUDES)\
+
+SaAcpiTables_Defines = \
+    /D"TIANO_RELEASE_VERSION=0x00080006"\
+
+SaAcpiTables_ACPIS = \
+    $(BUILD_DIR)\Dmar.acpi\
+
+$(BUILD_DIR)\SaAcpiTables.asl: $(BUILD_DIR)\token.mak $(SaAcpiTables_DIR)\SaAcpiTables.mak
+	copy << $@
+!IF "$(TCG2Support)" == "0" || "$(TCG2Support)" == ""
+!IF "$(TCG_SUPPORT)" != "1" 
+Name(TPMF, 0x0)
+!ENDIF
+!ENDIF
+<<
+
+$(BUILD_DIR)\Dmar.exe : $(SaAcpiTables_DIR)\Dmar\Dmar.act $(SaAcpiTables_DIR)\Dmar\Dmar.h
+	@CL $(CFLAGS) $(SaAcpiTables_Defines) /Fo$(BUILD_DIR)\ $(SaAcpiTables_Includes) /TC $(SaAcpiTables_DIR)\Dmar\Dmar.act
+	@Link  /OUT:$(BUILD_DIR)\Dmar.exe /NODEFAULTLIB /ENTRY:main $(BUILD_DIR)\Dmar.obj
+
+$(BUILD_DIR)\Dmar.acpi : $(BUILD_DIR)\Dmar.exe
+	$(GENACPITABLE) $(BUILD_DIR)\Dmar.exe $(BUILD_DIR)\Dmar.acpi
+
+$(BUILD_DIR)\SaAcpiTables.sec : $(SaAcpiTables_ACPIS)
+  $(GENSECTION) -I $** -O $@ -S EFI_SECTION_RAW
+
+$(BUILD_DIR)\SaAcpiTables.ffs: $(BUILD_DIR)\SaAcpiTables.sec $(SaAcpiTables_DIR)\SaAcpiTables.mak
+	$(MAKE) /f Core\FFS.mak \
+		BUILD_DIR=$(BUILD_DIR) \
+        GUID=27E569D5-0AFC-4D8F-8C90-783AC4A318AB\
+		TYPE=EFI_FV_FILETYPE_FREEFORM \
+        FFS_CHECKSUM=1\
+		RAWFILE=$(BUILD_DIR)\SaAcpiTables.sec FFSFILE=$(BUILD_DIR)\SaAcpiTables.ffs COMPRESS=0 NAME=SaAcpiTables
+
diff --git a/ReferenceCode/Chipset/SystemAgent/AcpiTables/SaAcpiTables.sdl b/ReferenceCode/Chipset/SystemAgent/AcpiTables/SaAcpiTables.sdl
new file mode 100644
index 0000000..e122ec8
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/AcpiTables/SaAcpiTables.sdl
@@ -0,0 +1,41 @@
+TOKEN
+	Name  = "SaAcpiTables_SUPPORT"
+	Value  = "1"
+	Help  = "Main switch to enable SaAcpiTables support in Project"
+	TokenType = Boolean
+	Master = Yes
+End
+
+PATH
+	Name  = "SaAcpiTables_DIR"
+End
+
+TOKEN
+	Name  = "GENACPITABLE"
+	Value  = "$(INTEL_SYSTEM_AGENT_DIR)\SampleCode\Tools\GenAcpiTable"
+	TokenType = Expression
+	TargetMAK = Yes
+End
+
+MODULE
+	Help  = "Includes SaAcpiTables.mak to Project"
+	File  = "SaAcpiTables.mak"
+End
+
+ELINK
+	Name  = "/I$(SaAcpiTables_DIR)\Dmar"
+	Parent  = "INTEL_MCH_INCLUDES"
+	InvokeOrder = AfterParent
+End
+
+ELINK
+	Name  = "$(BUILD_DIR)\SaAcpiTables.ffs"
+	Parent  = "FV_MAIN"
+	InvokeOrder = AfterParent
+End
+
+ELINK
+	Name  = "$(BUILD_DIR)\SaAcpiTables.asl"
+	Parent  = "GENERIC_ASL"
+	InvokeOrder = AfterParent
+End
diff --git a/ReferenceCode/Chipset/SystemAgent/AcpiTables/SaAcpiTables_Edk.inf b/ReferenceCode/Chipset/SystemAgent/AcpiTables/SaAcpiTables_Edk.inf
new file mode 100644
index 0000000..b47548a
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/AcpiTables/SaAcpiTables_Edk.inf
@@ -0,0 +1,54 @@
+## @file
+#  Component description file for the ACPI tables (for EDK1117)
+#
+#@copyright
+#  Copyright (c)  2012 Intel Corporation. All rights reserved
+#  This software and associated documentation (if any) is furnished
+#  under a license and may only be used or copied in accordance
+#  with the terms of the license. Except as permitted by such
+#  license, no part of this software or documentation may be
+#  reproduced, stored in a retrieval system, or transmitted in any
+#  form or by any means without the express written consent of
+#  Intel Corporation.
+#
+#  This file contains a 'Sample Driver' and is licensed as such
+#  under the terms of your license agreement with Intel or your
+#  vendor.  This file may be modified by the user, subject to
+#  the additional terms of the license agreement
+#
+
+[defines]
+BASE_NAME            = SaAcpiTables
+FILE_GUID            = 27E569D5-0AFC-4D8F-8C90-783AC4A318AB
+COMPONENT_TYPE       = SA_DMAR_ACPITABLE
+FFS_EXT              = .ffs
+
+[sources.common]
+  Dmar/Dmar.act
+  Dmar/Dmar.h
+
+[libraries.common]
+
+[includes.common]
+  .
+  $(EFI_SOURCE)
+  $(EFI_SOURCE)/Include
+  $(EFI_SOURCE)/$(PROJECT_SA_ROOT)/Include
+  $(EDK_SOURCE)/Foundation/Efi
+  $(EDK_SOURCE)/Foundation/Include
+  $(EDK_SOURCE)/Foundation/Efi/Include
+  $(EDK_SOURCE)/Foundation/Framework/Include
+  $(EFI_SOURCE)/Include/IndustryStandard
+  $(EDK_SOURCE)/Foundation/Include/IndustryStandard
+  $(EDK_SOURCE)/Foundation/Library/Dxe/Include
+  $(EDK_SOURCE)/Foundation
+  $(EDK_SOURCE)/Foundation/Framework
+
+#
+# Typically the sample code referenced will be available in the code base already
+# So keep this include at the end to defer to the source base definition
+# and only use the sample code definition if source base does not include these files.
+#
+  $(EFI_SOURCE)/$(PROJECT_SA_ROOT)/SampleCode/Include
+
+[nmake.common]
diff --git a/ReferenceCode/Chipset/SystemAgent/AcpiTables/SaSsdt/INTELGFX.ASL b/ReferenceCode/Chipset/SystemAgent/AcpiTables/SaSsdt/INTELGFX.ASL
new file mode 100644
index 0000000..153afd5
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/AcpiTables/SaSsdt/INTELGFX.ASL
@@ -0,0 +1,1731 @@
+/*++
+  This file contains an 'Intel Peripheral Driver' and uniquely  
+  identified as "Intel Reference Module" and is                 
+  licensed for Intel CPUs and chipsets under the terms of your  
+  license agreement with Intel or your vendor.  This file may   
+  be modified by the user, subject to additional terms of the   
+  license agreement                                             
+--*/
+
+/*++
+
+Copyright (c)  1999 - 2013 Intel Corporation. All rights reserved
+This software and associated documentation (if any) is furnished
+under a license and may only be used or copied in accordance
+with the terms of the license. Except as permitted by such
+license, no part of this software or documentation may be
+reproduced, stored in a retrieval system, or transmitted in any
+form or by any means without the express written consent of
+Intel Corporation.
+
+
+Module Name:
+
+  INTELGFX.ASL
+
+Abstract:
+
+  IGD OpRegion/Software ACPI Reference Code.
+
+--*/
+
+
+ External(\_SB.PCI0.GFX0.IDAB, MethodObj)
+ External(\_SB.PCI0.GFX0.HWID, MethodObj)
+ External(\ECST, MethodObj)
+ External(HDOS, MethodObj)
+#if !defined(ASL_Remove_SaSsdt_Data_To_Dsdt) || (ASL_Remove_SaSsdt_Data_To_Dsdt == 0)
+ External(\ECON, IntObj)
+ External(\PNHM, IntObj)
+#endif // AMI_OVERRIDE
+ External(OSYS, IntObj)
+ External(SCIS)
+ External(\GUAM, MethodObj)
+ External(DSEN)
+ External(BID)
+ External(BHB)
+ External(BFS2)
+ External(BFS3)
+ External(BFS4)
+
+
+ External(S0ID)
+ External(\ADBG, MethodObj)
+ External(\_SB.PEPD, DeviceObj)
+
+  Method(_DEP){
+    ADBG("GFX0 DEP Call")
+    If(LEqual(S0ID, 1)){
+      ADBG("GFX0 DEP")
+      Return(Package() {\_SB.PEPD})
+    }Else{
+      ADBG("GFX0 DEP NULL")
+      Return(Package(){})
+    }
+  }
+
+  // Enable/Disable Output Switching.  In WIN2K/WINXP, _DOS = 0 will
+  // get called during initialization to prepare for an ACPI Display
+  // Switch Event.  During an ACPI Display Switch, the OS will call
+  // _DOS = 2 immediately after a Notify=0x80 to temporarily disable
+  // all Display Switching.  After ACPI Display Switching is complete,
+  // the OS will call _DOS = 0 to re-enable ACPI Display Switching.
+
+  Method(_DOS,1)
+  {
+    // Store Display Switching and LCD brightness BIOS control bit
+    Store(And(Arg0,7),DSEN)
+
+    If(LEqual(And(Arg0,  0x3), 0))     // If _DOS[1:0]=0 
+    {
+      If(CondRefOf(HDOS))
+      {
+        HDOS()
+      }
+    }
+  }
+
+  // Enumerate the Display Environment.  This method will return
+  // valid addresses for all display device encoders present in the
+  // system.  The Miniport Driver will reject the addresses for every
+  // encoder that does not have an attached display device.  After
+  // enumeration is complete, the OS will call the _DGS methods
+  // during a display switch only for the addresses accepted by the
+  // Miniport Driver.  For hot-insertion and removal of display
+  // devices, a re-enumeration notification will be required so the
+  // address of the newly present display device will be accepted by
+  // the Miniport Driver.
+
+  Method(_DOD,0)
+  {
+    
+    If (CondRefOf(IDAB))
+    {
+      IDAB() 
+    }
+    Else
+    {
+      Store(0, NDID)
+
+      If(LNotEqual(DIDL, Zero))
+      {
+        Store(SDDL(DIDL),DID1)
+      }
+      If(LNotEqual(DDL2, Zero))
+      {
+        Store(SDDL(DDL2),DID2)
+      }
+      If(LNotEqual(DDL3, Zero))
+      {
+        Store(SDDL(DDL3),DID3)
+      }
+      If(LNotEqual(DDL4, Zero))
+      {
+        Store(SDDL(DDL4),DID4)
+      }
+      If(LNotEqual(DDL5, Zero))
+      {
+        Store(SDDL(DDL5),DID5)
+      }
+      If(LNotEqual(DDL6, Zero))
+      {
+        Store(SDDL(DDL6),DID6)
+      }
+      If(LNotEqual(DDL7, Zero))
+      {
+        Store(SDDL(DDL7),DID7)
+      }
+      If(LNotEqual(DDL8, Zero))
+      {
+        Store(SDDL(DDL8),DID8)
+      }
+      If(LNotEqual(DDL9, Zero))
+      {
+        Store(SDDL(DDL9),DID9)
+      }
+      If(LNotEqual(DD10, Zero))
+      {
+        Store(SDDL(DD10),DIDA)
+      }
+      If(LNotEqual(DD11, Zero))
+      {
+        Store(SDDL(DD11),DIDB)
+      }
+      If(LNotEqual(DD12, Zero))
+      {
+        Store(SDDL(DD12),DIDC)
+      }
+      If(LNotEqual(DD13, Zero))
+      {
+        Store(SDDL(DD13),DIDD)
+      }
+      If(LNotEqual(DD14, Zero))
+      {
+        Store(SDDL(DD14),DIDE)
+      }
+      If(LNotEqual(DD15, Zero))
+      {
+        Store(SDDL(DD15),DIDF)
+      }
+    }
+
+    // @todo - This level of flexibility is not needed for a true
+    //  OEM design.  Simply determine the greatest number of
+    //  encoders the platform will suppport then remove all
+    //  return packages beyond that value.  Note that for
+    //  current silicon, the maximum number of encoders
+    //  possible is 8.
+
+    If(LEqual(NDID,1))
+    {
+      Name(TMP1,Package() {0xFFFFFFFF})
+      Store(Or(0x10000,DID1),Index(TMP1,0))
+      Return(TMP1)
+    }
+
+    If(LEqual(NDID,2))
+    {
+      Name(TMP2,Package() {0xFFFFFFFF, 
+            0xFFFFFFFF})
+      Store(Or(0x10000,DID1),Index(TMP2,0))
+      Store(Or(0x10000,DID2),Index(TMP2,1))
+      Return(TMP2)
+    }
+
+    If(LEqual(NDID,3))
+    {
+      Name(TMP3,Package() {0xFFFFFFFF,
+            0xFFFFFFFF,
+            0xFFFFFFFF})
+      Store(Or(0x10000,DID1),Index(TMP3,0))
+      Store(Or(0x10000,DID2),Index(TMP3,1))
+      Store(Or(0x10000,DID3),Index(TMP3,2))
+      Return(TMP3)
+    }
+
+    If(LEqual(NDID,4))
+    {
+      Name(TMP4,Package() {0xFFFFFFFF,
+            0xFFFFFFFF,
+            0xFFFFFFFF,
+            0xFFFFFFFF})
+      Store(Or(0x10000,DID1),Index(TMP4,0))
+      Store(Or(0x10000,DID2),Index(TMP4,1))
+      Store(Or(0x10000,DID3),Index(TMP4,2))
+      Store(Or(0x10000,DID4),Index(TMP4,3))
+      Return(TMP4)
+    }
+
+    If(LEqual(NDID,5))
+    {
+      Name(TMP5,Package() {0xFFFFFFFF,
+            0xFFFFFFFF,
+            0xFFFFFFFF,
+            0xFFFFFFFF,
+            0xFFFFFFFF})
+      Store(Or(0x10000,DID1),Index(TMP5,0))
+      Store(Or(0x10000,DID2),Index(TMP5,1))
+      Store(Or(0x10000,DID3),Index(TMP5,2))
+      Store(Or(0x10000,DID4),Index(TMP5,3))
+      Store(Or(0x10000,DID5),Index(TMP5,4))
+      Return(TMP5)
+    }
+
+    If(LEqual(NDID,6))
+    {
+      Name(TMP6,Package() {0xFFFFFFFF,
+            0xFFFFFFFF,
+            0xFFFFFFFF,
+            0xFFFFFFFF,
+            0xFFFFFFFF,
+            0xFFFFFFFF})
+      Store(Or(0x10000,DID1),Index(TMP6,0))
+      Store(Or(0x10000,DID2),Index(TMP6,1))
+      Store(Or(0x10000,DID3),Index(TMP6,2))
+      Store(Or(0x10000,DID4),Index(TMP6,3))
+      Store(Or(0x10000,DID5),Index(TMP6,4))
+      Store(Or(0x10000,DID6),Index(TMP6,5))
+      Return(TMP6)
+    }
+
+    If(LEqual(NDID,7))
+    {
+      Name(TMP7,Package() {0xFFFFFFFF,
+            0xFFFFFFFF,
+            0xFFFFFFFF,
+            0xFFFFFFFF,
+            0xFFFFFFFF,
+            0xFFFFFFFF,
+            0xFFFFFFFF})
+      Store(Or(0x10000,DID1),Index(TMP7,0))
+      Store(Or(0x10000,DID2),Index(TMP7,1))
+      Store(Or(0x10000,DID3),Index(TMP7,2))
+      Store(Or(0x10000,DID4),Index(TMP7,3))
+      Store(Or(0x10000,DID5),Index(TMP7,4))
+      Store(Or(0x10000,DID6),Index(TMP7,5))
+      Store(Or(0x10000,DID7),Index(TMP7,6))
+      Return(TMP7)
+    }
+
+    If(LEqual(NDID,8))
+    {
+      Name(TMP8,Package() {0xFFFFFFFF,
+            0xFFFFFFFF,
+            0xFFFFFFFF,
+            0xFFFFFFFF,
+            0xFFFFFFFF,
+            0xFFFFFFFF,
+            0xFFFFFFFF,
+            0xFFFFFFFF})
+      Store(Or(0x10000,DID1),Index(TMP8,0))
+      Store(Or(0x10000,DID2),Index(TMP8,1))
+      Store(Or(0x10000,DID3),Index(TMP8,2))
+      Store(Or(0x10000,DID4),Index(TMP8,3))
+      Store(Or(0x10000,DID5),Index(TMP8,4))
+      Store(Or(0x10000,DID6),Index(TMP8,5))
+      Store(Or(0x10000,DID7),Index(TMP8,6))
+      Store(Or(0x10000,DID8),Index(TMP8,7))
+      Return(TMP8)
+    }
+
+    If(LEqual(NDID,9))
+    {
+      Name(TMP9,Package() {0xFFFFFFFF,
+            0xFFFFFFFF,
+            0xFFFFFFFF,
+            0xFFFFFFFF,
+            0xFFFFFFFF,
+            0xFFFFFFFF,
+            0xFFFFFFFF,
+            0xFFFFFFFF,
+            0xFFFFFFFF})
+      Store(Or(0x10000,DID1),Index(TMP9,0))
+      Store(Or(0x10000,DID2),Index(TMP9,1))
+      Store(Or(0x10000,DID3),Index(TMP9,2))
+      Store(Or(0x10000,DID4),Index(TMP9,3))
+      Store(Or(0x10000,DID5),Index(TMP9,4))
+      Store(Or(0x10000,DID6),Index(TMP9,5))
+      Store(Or(0x10000,DID7),Index(TMP9,6))
+      Store(Or(0x10000,DID8),Index(TMP9,7))
+                        Store(Or(0x10000,DID9),Index(TMP9,8))
+      Return(TMP9)
+    }
+
+    If(LEqual(NDID,0x0A))
+    {
+      Name(TMPA,Package() {0xFFFFFFFF,
+            0xFFFFFFFF,
+            0xFFFFFFFF,
+            0xFFFFFFFF,
+            0xFFFFFFFF,
+            0xFFFFFFFF,
+            0xFFFFFFFF,
+            0xFFFFFFFF,
+            0xFFFFFFFF,
+            0xFFFFFFFF})
+      Store(Or(0x10000,DID1),Index(TMPA,0))
+      Store(Or(0x10000,DID2),Index(TMPA,1))
+      Store(Or(0x10000,DID3),Index(TMPA,2))
+      Store(Or(0x10000,DID4),Index(TMPA,3))
+      Store(Or(0x10000,DID5),Index(TMPA,4))
+      Store(Or(0x10000,DID6),Index(TMPA,5))
+      Store(Or(0x10000,DID7),Index(TMPA,6))
+      Store(Or(0x10000,DID8),Index(TMPA,7))
+                        Store(Or(0x10000,DID9),Index(TMPA,8))
+                        Store(Or(0x10000,DIDA),Index(TMPA,9))
+      Return(TMPA)
+    }
+
+    If(LEqual(NDID,0x0B))
+    {
+      Name(TMPB,Package() {0xFFFFFFFF,
+            0xFFFFFFFF,
+            0xFFFFFFFF,
+            0xFFFFFFFF,
+            0xFFFFFFFF,
+            0xFFFFFFFF,
+            0xFFFFFFFF,
+            0xFFFFFFFF,
+            0xFFFFFFFF,
+            0xFFFFFFFF,
+            0xFFFFFFFF})
+      Store(Or(0x10000,DID1),Index(TMPB,0))
+      Store(Or(0x10000,DID2),Index(TMPB,1))
+      Store(Or(0x10000,DID3),Index(TMPB,2))
+      Store(Or(0x10000,DID4),Index(TMPB,3))
+      Store(Or(0x10000,DID5),Index(TMPB,4))
+      Store(Or(0x10000,DID6),Index(TMPB,5))
+      Store(Or(0x10000,DID7),Index(TMPB,6))
+      Store(Or(0x10000,DID8),Index(TMPB,7))
+                        Store(Or(0x10000,DID9),Index(TMPB,8))
+                        Store(Or(0x10000,DIDA),Index(TMPB,9))
+                        Store(Or(0x10000,DIDB),Index(TMPB,10))
+      Return(TMPB)
+    }
+
+    If(LEqual(NDID,0x0C))
+    {
+      Name(TMPC,Package() {0xFFFFFFFF,
+            0xFFFFFFFF,
+            0xFFFFFFFF,
+            0xFFFFFFFF,
+            0xFFFFFFFF,
+            0xFFFFFFFF,
+            0xFFFFFFFF,
+            0xFFFFFFFF,
+            0xFFFFFFFF,
+            0xFFFFFFFF,
+            0xFFFFFFFF,
+            0xFFFFFFFF})
+      Store(Or(0x10000,DID1),Index(TMPC,0))
+      Store(Or(0x10000,DID2),Index(TMPC,1))
+      Store(Or(0x10000,DID3),Index(TMPC,2))
+      Store(Or(0x10000,DID4),Index(TMPC,3))
+      Store(Or(0x10000,DID5),Index(TMPC,4))
+      Store(Or(0x10000,DID6),Index(TMPC,5))
+      Store(Or(0x10000,DID7),Index(TMPC,6))
+      Store(Or(0x10000,DID8),Index(TMPC,7))
+      Store(Or(0x10000,DID9),Index(TMPC,8))
+      Store(Or(0x10000,DIDA),Index(TMPC,9))
+      Store(Or(0x10000,DIDB),Index(TMPC,10))
+      Store(Or(0x10000,DIDC),Index(TMPC,11))
+      Return(TMPC)
+    }
+
+    If(LEqual(NDID,0x0D))
+    {
+      Name(TMPD,Package() {0xFFFFFFFF,
+            0xFFFFFFFF,
+            0xFFFFFFFF,
+            0xFFFFFFFF,
+            0xFFFFFFFF,
+            0xFFFFFFFF,
+            0xFFFFFFFF,
+            0xFFFFFFFF,
+            0xFFFFFFFF,
+            0xFFFFFFFF,
+            0xFFFFFFFF,
+            0xFFFFFFFF,
+            0xFFFFFFFF})
+      Store(Or(0x10000,DID1),Index(TMPD,0))
+      Store(Or(0x10000,DID2),Index(TMPD,1))
+      Store(Or(0x10000,DID3),Index(TMPD,2))
+      Store(Or(0x10000,DID4),Index(TMPD,3))
+      Store(Or(0x10000,DID5),Index(TMPD,4))
+      Store(Or(0x10000,DID6),Index(TMPD,5))
+      Store(Or(0x10000,DID7),Index(TMPD,6))
+      Store(Or(0x10000,DID8),Index(TMPD,7))
+      Store(Or(0x10000,DID9),Index(TMPD,8))
+      Store(Or(0x10000,DIDA),Index(TMPD,9))
+      Store(Or(0x10000,DIDB),Index(TMPD,10))
+      Store(Or(0x10000,DIDC),Index(TMPD,11))
+      Store(Or(0x10000,DIDD),Index(TMPD,12))
+      Return(TMPD)
+    }
+
+    If(LEqual(NDID,0x0E))
+    {
+      Name(TMPE,Package() {0xFFFFFFFF,
+            0xFFFFFFFF,
+            0xFFFFFFFF,
+            0xFFFFFFFF,
+            0xFFFFFFFF,
+            0xFFFFFFFF,
+            0xFFFFFFFF,
+            0xFFFFFFFF,
+            0xFFFFFFFF,
+            0xFFFFFFFF,
+            0xFFFFFFFF,
+            0xFFFFFFFF,
+            0xFFFFFFFF,
+            0xFFFFFFFF})
+      Store(Or(0x10000,DID1),Index(TMPE,0))
+      Store(Or(0x10000,DID2),Index(TMPE,1))
+      Store(Or(0x10000,DID3),Index(TMPE,2))
+      Store(Or(0x10000,DID4),Index(TMPE,3))
+      Store(Or(0x10000,DID5),Index(TMPE,4))
+      Store(Or(0x10000,DID6),Index(TMPE,5))
+      Store(Or(0x10000,DID7),Index(TMPE,6))
+      Store(Or(0x10000,DID8),Index(TMPE,7))
+      Store(Or(0x10000,DID9),Index(TMPE,8))
+      Store(Or(0x10000,DIDA),Index(TMPE,9))
+      Store(Or(0x10000,DIDB),Index(TMPE,10))
+      Store(Or(0x10000,DIDC),Index(TMPE,11))
+      Store(Or(0x10000,DIDD),Index(TMPE,12))
+      Store(Or(0x10000,DIDE),Index(TMPE,13))
+      Return(TMPE)
+    }
+
+    If(LEqual(NDID,0x0F))
+    {
+
+      Name(TMPF,Package() {0xFFFFFFFF,
+            0xFFFFFFFF,
+            0xFFFFFFFF,
+            0xFFFFFFFF,
+            0xFFFFFFFF,
+            0xFFFFFFFF,
+            0xFFFFFFFF,
+            0xFFFFFFFF,
+            0xFFFFFFFF,
+            0xFFFFFFFF,
+            0xFFFFFFFF,
+            0xFFFFFFFF,
+            0xFFFFFFFF,
+            0xFFFFFFFF,
+            0xFFFFFFFF})
+      Store(Or(0x10000,DID1),Index(TMPF,0))
+      Store(Or(0x10000,DID2),Index(TMPF,1))
+      Store(Or(0x10000,DID3),Index(TMPF,2))
+      Store(Or(0x10000,DID4),Index(TMPF,3))
+      Store(Or(0x10000,DID5),Index(TMPF,4))
+      Store(Or(0x10000,DID6),Index(TMPF,5))
+      Store(Or(0x10000,DID7),Index(TMPF,6))
+      Store(Or(0x10000,DID8),Index(TMPF,7))
+      Store(Or(0x10000,DID9),Index(TMPF,8))
+      Store(Or(0x10000,DIDA),Index(TMPF,9))
+      Store(Or(0x10000,DIDB),Index(TMPF,10))
+      Store(Or(0x10000,DIDC),Index(TMPF,11))
+      Store(Or(0x10000,DIDD),Index(TMPF,12))
+      Store(Or(0x10000,DIDE),Index(TMPF,13))
+      Store(Or(0x10000,DIDF),Index(TMPF,14))
+      Return(TMPF)
+    }
+
+    // If nothing else, return Unknown LFP.
+    // (Prevents compiler warning.)
+    
+    Return(Package() {0x00000400})
+  }
+  
+  Device(DD01)
+  {
+
+    // Return Unique ID.
+
+    Method(_ADR,0,Serialized)
+    {
+      If(LEqual(And(0x0F00,DID1),0x400))
+      {
+        Store(0x1, EDPV)
+        Store(NXD1, NXDX)
+        Store(DID1, DIDX)
+        Return(1)
+      }
+      If(LEqual(DID1,0))
+      {
+        Return(1)
+      }
+      Else
+      {
+        Return(And(0xFFFF,DID1))
+      }
+    }
+
+    // Return the Current Status.
+
+    Method(_DCS,0)
+    {
+      Return(CDDS(DID1))
+    }
+
+    // Query Graphics State (active or inactive).
+
+    Method(_DGS,0)
+    {
+                        If(LAnd(LEqual(And(SGMD,0x7F),0x01),CondRefOf(SNXD)))
+      {
+        Return (NXD1)
+      }
+      Return(NDDS(DID1))
+    }
+
+    // Device Set State.
+
+    // _DSS Table:
+    //
+    //  BIT31  BIT30  Execution
+    //  0  0  Don't implement.
+    //  0  1  Cache change.  Nothing to Implement.
+    //  1  0  Don't Implement.
+    //  1  1  Display Switch Complete.  Implement.
+
+    Method(_DSS,1)
+    {
+      If(LEqual(And(Arg0,0xC0000000),0xC0000000))
+      {
+
+        // State change was performed by the
+        // Video Drivers.  Simply update the
+        // New State.
+
+        Store(NSTE,CSTE)
+      }
+    }
+  }
+
+  Device(DD02)
+  {
+
+    // Return Unique ID.
+
+    Method(_ADR,0,Serialized)
+    {
+      If(LEqual(And(0x0F00,DID2),0x400))
+      {
+        Store(0x2, EDPV)
+        Store(NXD2, NXDX)
+        Store(DID2, DIDX)
+        Return(2)
+      }
+      If(LEqual(DID2,0))
+      {
+        Return(2)
+      }
+      Else
+      {
+        Return(And(0xFFFF,DID2))
+      }
+    }
+
+    // Return the Current Status.
+
+    Method(_DCS,0)
+    {
+      If(LEqual(LIDS,0))
+      {
+        Return(0x0)
+      }
+      
+      Return(CDDS(DID2))
+    }
+
+    // Query Graphics State (active or inactive).
+
+    Method(_DGS,0)
+    {
+      // Return the Next State.
+      If(LAnd(LEqual(And(SGMD,0x7F),0x01),CondRefOf(SNXD)))
+      {
+        Return (NXD2)
+      }
+      Return(NDDS(DID2))
+    }
+
+    // Device Set State. (See table above.)
+
+    Method(_DSS,1)
+    {
+      If(LEqual(And(Arg0,0xC0000000),0xC0000000))
+      {
+
+        // State change was performed by the
+        // Video Drivers.  Simply update the
+        // New State.
+
+        Store(NSTE,CSTE)
+      }
+    }
+  }
+
+  Device(DD03)
+  {
+
+    // Return Unique ID.
+
+    Method(_ADR,0,Serialized)
+    {
+      If(LEqual(And(0x0F00,DID3),0x400))
+      {
+        Store(0x3, EDPV)
+        Store(NXD3, NXDX)
+        Store(DID3, DIDX)
+        Return(3)
+      }
+      If(LEqual(DID3,0))
+      {
+        Return(3)
+      }
+      Else
+      {
+      Return(And(0xFFFF,DID3))
+      }
+    }
+
+    // Return the Current Status.
+
+    Method(_DCS,0)
+    {
+      If(LEqual(DID3,0))
+      {
+        Return(0x0B)
+      }
+      Else
+      {
+        Return(CDDS(DID3))
+      }
+    }
+
+    // Query Graphics State (active or inactive).
+
+    Method(_DGS,0)
+    {      
+      If(LAnd(LEqual(And(SGMD,0x7F),0x01),CondRefOf(SNXD)))
+      {
+        Return (NXD3)
+      }
+      Return(NDDS(DID3))
+    }
+
+    // Device Set State. (See table above.)
+
+    Method(_DSS,1)
+    {
+      If(LEqual(And(Arg0,0xC0000000),0xC0000000))
+      {
+        // State change was performed by the
+        // Video Drivers.  Simply update the
+        // New State.
+
+        Store(NSTE,CSTE)
+      }
+    }
+  }
+
+  Device(DD04)
+  {
+
+    // Return Unique ID.
+
+    Method(_ADR,0,Serialized)
+    {
+      If(LEqual(And(0x0F00,DID4),0x400))
+      {
+        Store(0x4, EDPV)
+        Store(NXD4, NXDX)
+        Store(DID4, DIDX)
+        Return(4)
+      }
+      If(LEqual(DID4,0))
+      {
+        Return(4)
+      }
+      Else
+      {
+        Return(And(0xFFFF,DID4))
+      }
+    }
+
+    // Return the Current Status.
+
+    Method(_DCS,0)
+    {
+      If(LEqual(DID4,0))
+      {
+        Return(0x0B)
+      }
+      Else
+      {
+        Return(CDDS(DID4))
+      }
+    }
+
+    // Query Graphics State (active or inactive).
+
+    Method(_DGS,0)
+    {
+      If(LAnd(LEqual(And(SGMD,0x7F),0x01),CondRefOf(SNXD)))
+      {
+        Return (NXD4)
+      }
+      Return(NDDS(DID4))
+    }
+
+    // Device Set State. (See table above.)
+
+    Method(_DSS,1)
+    {
+      If(LEqual(And(Arg0,0xC0000000),0xC0000000))
+      {
+
+        // State change was performed by the
+        // Video Drivers.  Simply update the
+        // New State.
+
+        Store(NSTE,CSTE)
+      }
+    }
+  }
+
+
+  Device(DD05)
+  {
+
+    // Return Unique ID.
+
+    Method(_ADR,0,Serialized)
+    {
+      If(LEqual(And(0x0F00,DID5),0x400))
+      {
+        Store(0x5, EDPV)
+        Store(NXD5, NXDX)
+        Store(DID5, DIDX)
+        Return(5)
+      }
+      If(LEqual(DID5,0))
+      {
+        Return(5)
+      }
+      Else
+      {
+        Return(And(0xFFFF,DID5))
+      }
+    }
+
+    // Return the Current Status.
+    
+    Method(_DCS,0)
+    {
+      If(LEqual(DID5,0))
+      {
+        Return(0x0B)
+      }
+      Else
+      {
+        Return(CDDS(DID5))
+      }
+    }
+
+    // Query Graphics State (active or inactive).
+
+    Method(_DGS,0)
+    {
+      If(LAnd(LEqual(And(SGMD,0x7F),0x01),CondRefOf(SNXD)))
+      {
+        Return (NXD5)
+      }
+      Return(NDDS(DID5))
+    }
+
+    // Device Set State. (See table above.)
+
+    Method(_DSS,1)
+    {
+      If(LEqual(And(Arg0,0xC0000000),0xC0000000))
+      {
+        // State change was performed by the
+        // Video Drivers.  Simply update the
+        // New State.
+
+        Store(NSTE,CSTE)
+      }
+    }
+  }
+
+
+  Device(DD06)
+  {
+
+    // Return Unique ID.
+
+    Method(_ADR,0,Serialized)
+    {
+      If(LEqual(And(0x0F00,DID6),0x400))
+      {
+        Store(0x6, EDPV)
+        Store(NXD6, NXDX)
+        Store(DID6, DIDX)
+        Return(6)
+      }
+      If(LEqual(DID6,0))
+      {
+        Return(6)
+      }
+      Else
+      {
+        Return(And(0xFFFF,DID6))
+      }
+    }
+
+    // Return the Current Status.
+
+    Method(_DCS,0)
+    {
+      If(LEqual(DID6,0))
+      {
+        Return(0x0B)
+      }
+      Else
+      {
+        Return(CDDS(DID6))
+      }
+    }
+
+    // Query Graphics State (active or inactive).
+
+    Method(_DGS,0)
+    {
+      If(LAnd(LEqual(And(SGMD,0x7F),0x01),CondRefOf(SNXD)))
+      {
+        Return (NXD6)
+      }
+      Return(NDDS(DID6))
+    }
+
+    // Device Set State. (See table above.)
+
+    Method(_DSS,1)
+    {
+      If(LEqual(And(Arg0,0xC0000000),0xC0000000))
+      {
+        // State change was performed by the
+        // Video Drivers.  Simply update the
+        // New State.
+
+        Store(NSTE,CSTE)
+      }
+    }
+  }
+
+
+  Device(DD07)
+  {
+
+    // Return Unique ID.
+
+    Method(_ADR,0,Serialized)
+    {
+      If(LEqual(And(0x0F00,DID7),0x400))
+      {
+        Store(0x7, EDPV)
+        Store(NXD7, NXDX)
+        Store(DID7, DIDX)
+        Return(7)
+      }
+      If(LEqual(DID7,0))
+      {
+        Return(7)
+      }
+      Else
+      {
+        Return(And(0xFFFF,DID7))
+      }
+    }
+
+    // Return the Current Status.
+    
+    Method(_DCS,0)
+    {
+      If(LEqual(DID7,0))
+      {
+        Return(0x0B)
+      }
+      Else
+      {
+        Return(CDDS(DID7))
+      }
+    }
+
+    // Query Graphics State (active or inactive).
+
+    Method(_DGS,0)
+    {
+      If(LAnd(LEqual(And(SGMD,0x7F),0x01),CondRefOf(SNXD)))
+      {
+        Return (NXD7)
+      }
+      Return(NDDS(DID7))
+    }
+
+    // Device Set State. (See table above.)
+
+    Method(_DSS,1)
+    {
+      If(LEqual(And(Arg0,0xC0000000),0xC0000000))
+      {
+        // State change was performed by the
+        // Video Drivers.  Simply update the
+        // New State.
+
+        Store(NSTE,CSTE)
+      }
+    }
+  }
+
+
+  Device(DD08)
+  {
+
+    // Return Unique ID.
+
+    Method(_ADR,0,Serialized)
+    {
+      If(LEqual(And(0x0F00,DID8),0x400))
+      {
+        Store(0x8, EDPV)
+        Store(NXD8, NXDX)
+        Store(DID8, DIDX)
+        Return(8)
+      }
+      If(LEqual(DID8,0))
+      {
+        Return(8)
+      }
+      Else
+      {
+        Return(And(0xFFFF,DID8))
+      }
+    }
+
+    // Return the Current Status.
+
+    Method(_DCS,0)
+    {
+      If(LEqual(DID8,0))
+      {
+        Return(0x0B)
+      }
+      Else
+      {
+        Return(CDDS(DID8))
+      }
+    }
+
+    // Query Graphics State (active or inactive).
+
+    Method(_DGS,0)
+    {
+      If(LAnd(LEqual(And(SGMD,0x7F),0x01),CondRefOf(SNXD)))
+      {
+        Return (NXD8)
+      }
+      Return(NDDS(DID8))
+    }
+
+    // Device Set State. (See table above.)
+
+    Method(_DSS,1)
+    {
+      If(LEqual(And(Arg0,0xC0000000),0xC0000000))
+      {
+        // State change was performed by the
+        // Video Drivers.  Simply update the
+        // New State.
+
+        Store(NSTE,CSTE)
+      }
+    }
+  }
+
+        Device(DD09)
+  {
+    // Return Unique ID.
+
+    Method(_ADR,0,Serialized)
+    {
+      If(LEqual(And(0x0F00,DID9),0x400))
+      {
+        Store(0x9, EDPV)
+        Store(NXD8, NXDX)
+        Store(DID9, DIDX)
+        Return(9)
+      }
+      If(LEqual(DID9,0))
+      {
+        Return(9)
+      }
+      Else
+      {
+        Return(And(0xFFFF,DID9))
+      }
+    }
+
+    // Return the Current Status.
+
+    Method(_DCS,0)
+    {
+      If(LEqual(DID9,0))
+      {
+        Return(0x0B)
+      }
+      Else
+      {
+        Return(CDDS(DID9))
+      }
+    }
+
+    // Query Graphics State (active or inactive).
+
+    Method(_DGS,0)
+    {
+      If(LAnd(LEqual(And(SGMD,0x7F),0x01),CondRefOf(SNXD)))
+      {
+        Return (NXD8)
+      }
+      Return(NDDS(DID9))
+    }
+
+    // Device Set State. (See table above.)
+
+    Method(_DSS,1)
+    {
+      If(LEqual(And(Arg0,0xC0000000),0xC0000000))
+      {
+        // State change was performed by the
+        // Video Drivers.  Simply update the
+        // New State.
+        Store(NSTE,CSTE)
+      }
+    }
+  }
+
+        Device(DD0A)
+  {
+    // Return Unique ID.
+
+    Method(_ADR,0,Serialized)
+    {
+      If(LEqual(And(0x0F00,DIDA),0x400))
+      {
+        Store(0xA, EDPV)
+        Store(NXD8, NXDX)
+        Store(DIDA, DIDX)
+        Return(0x0A)
+      }
+      If(LEqual(DIDA,0))
+      {
+        Return(0x0A)
+      }
+      Else
+      {
+        Return(And(0xFFFF,DIDA))
+      }
+    }
+
+    // Return the Current Status.
+
+    Method(_DCS,0)
+    {
+      If(LEqual(DIDA,0))
+      {
+        Return(0x0B)
+      }
+      Else
+      {
+        Return(CDDS(DIDA))
+      }
+    }
+
+    // Query Graphics State (active or inactive).
+
+    Method(_DGS,0)
+    {
+      If(LAnd(LEqual(And(SGMD,0x7F),0x01),CondRefOf(SNXD)))
+      {
+        Return (NXD8)
+      }
+      Return(NDDS(DIDA))
+    }
+
+    // Device Set State. (See table above.)
+
+    Method(_DSS,1)
+    {
+      If(LEqual(And(Arg0,0xC0000000),0xC0000000))
+      {
+        // State change was performed by the
+        // Video Drivers.  Simply update the
+        // New State.
+        Store(NSTE,CSTE)
+      }
+    }
+  }
+
+        Device(DD0B)
+  {
+    // Return Unique ID.
+
+    Method(_ADR,0,Serialized)
+    {
+      If(LEqual(And(0x0F00,DIDB),0x400))
+      {
+        Store(0xB, EDPV)
+        Store(NXD8, NXDX)
+        Store(DIDB, DIDX)
+        Return(0X0B)
+      }
+      If(LEqual(DIDB,0))
+      {
+        Return(0x0B)
+      }
+      Else
+      {
+        Return(And(0xFFFF,DIDB))
+      }
+    }
+
+    // Return the Current Status.
+
+    Method(_DCS,0)
+    {
+      If(LEqual(DIDB,0))
+      {
+        Return(0x0B)
+      }
+      Else
+      {
+        Return(CDDS(DIDB))
+      }
+    }
+
+    // Query Graphics State (active or inactive).
+
+    Method(_DGS,0)
+    {
+      If(LAnd(LEqual(And(SGMD,0x7F),0x01),CondRefOf(SNXD)))
+      {
+        Return (NXD8)
+      }
+      Return(NDDS(DIDB))
+    }
+
+    // Device Set State. (See table above.)
+
+    Method(_DSS,1)
+    {
+      If(LEqual(And(Arg0,0xC0000000),0xC0000000))
+      {
+        // State change was performed by the
+        // Video Drivers.  Simply update the
+        // New State.
+        Store(NSTE,CSTE)
+      }
+    }
+  }
+
+  Device(DD0C)
+  {
+    // Return Unique ID.
+
+    Method(_ADR,0,Serialized)
+    {
+      If(LEqual(And(0x0F00,DIDC),0x400))
+      {
+        Store(0xC, EDPV)
+        Store(NXD8, NXDX)
+        Store(DIDC, DIDX)
+        Return(0X0C)
+      }
+      If(LEqual(DIDC,0))
+      {
+        Return(0x0C)
+      }
+      Else
+      {
+        Return(And(0xFFFF,DIDC))
+      }
+    }
+
+    // Return the Current Status.
+
+    Method(_DCS,0)
+    {
+      If(LEqual(DIDC,0))
+      {
+        Return(0x0C)
+      }
+      Else
+      {
+        Return(CDDS(DIDC))
+      }
+    }
+
+    // Query Graphics State (active or inactive).
+
+    Method(_DGS,0)
+    {
+      If(LAnd(LEqual(And(SGMD,0x7F),0x01),CondRefOf(SNXD)))
+      {
+        Return (NXD8)
+      }
+      Return(NDDS(DIDC))
+    }
+
+    // Device Set State. (See table above.)
+
+    Method(_DSS,1)
+    {
+      If(LEqual(And(Arg0,0xC0000000),0xC0000000))
+      {
+        // State change was performed by the
+        // Video Drivers.  Simply update the
+        // New State.
+        Store(NSTE,CSTE)
+      }
+    }
+  }
+	
+  Device(DD0D)
+  {
+    // Return Unique ID.
+
+    Method(_ADR,0,Serialized)
+    {
+      If(LEqual(And(0x0F00,DIDD),0x400))
+      {
+        Store(0xD, EDPV)
+        Store(NXD8, NXDX)
+        Store(DIDD, DIDX)
+        Return(0X0D)
+      }
+      If(LEqual(DIDD,0))
+      {
+        Return(0x0D)
+      }
+      Else
+      {
+        Return(And(0xFFFF,DIDD))
+      }
+    }
+
+    // Return the Current Status.
+
+    Method(_DCS,0)
+    {
+      If(LEqual(DIDD,0))
+      {
+        Return(0x0D)
+      }
+      Else
+      {
+        Return(CDDS(DIDD))
+      }
+    }
+
+    // Query Graphics State (active or inactive).
+
+    Method(_DGS,0)
+    {
+      If(LAnd(LEqual(And(SGMD,0x7F),0x01),CondRefOf(SNXD)))
+      {
+        Return (NXD8)
+      }
+      Return(NDDS(DIDD))
+    }
+
+    // Device Set State. (See table above.)
+
+    Method(_DSS,1)
+    {
+      If(LEqual(And(Arg0,0xC0000000),0xC0000000))
+      {
+        // State change was performed by the
+        // Video Drivers.  Simply update the
+        // New State.
+        Store(NSTE,CSTE)
+      }
+    }
+  }
+ 
+  Device(DD0E)
+  {
+    // Return Unique ID.
+
+    Method(_ADR,0,Serialized)
+    {
+      If(LEqual(And(0x0F00,DIDE),0x400))
+      {
+        Store(0xE, EDPV)
+        Store(NXD8, NXDX)
+        Store(DIDE, DIDX)
+        Return(0X0E)
+      }
+      If(LEqual(DIDE,0))
+      {
+        Return(0x0E)
+      }
+      Else
+      {
+        Return(And(0xFFFF,DIDE))
+      }
+    }
+
+    // Return the Current Status.
+
+    Method(_DCS,0)
+    {
+      If(LEqual(DIDE,0))
+      {
+        Return(0x0E)
+      }
+      Else
+      {
+        Return(CDDS(DIDE))
+      }
+    }
+
+    // Query Graphics State (active or inactive).
+
+    Method(_DGS,0)
+    {
+      If(LAnd(LEqual(And(SGMD,0x7F),0x01),CondRefOf(SNXD)))
+      {
+        Return (NXD8)
+      }
+      Return(NDDS(DIDE))
+    }
+
+    // Device Set State. (See table above.)
+
+    Method(_DSS,1)
+    {
+      If(LEqual(And(Arg0,0xC0000000),0xC0000000))
+      {
+        // State change was performed by the
+        // Video Drivers.  Simply update the
+        // New State.
+        Store(NSTE,CSTE)
+      }
+    }
+  }
+	
+  Device(DD0F)
+  {
+    // Return Unique ID.
+
+    Method(_ADR,0,Serialized)
+    {
+      If(LEqual(And(0x0F00,DIDF),0x400))
+      {
+        Store(0xF, EDPV)
+        Store(NXD8, NXDX)
+        Store(DIDF, DIDX)
+        Return(0X0F)
+      }
+      If(LEqual(DIDF,0))
+      {
+        Return(0x0F)
+      }
+      Else
+      {
+        Return(And(0xFFFF,DIDF))
+      }
+    }
+
+    // Return the Current Status.
+
+    Method(_DCS,0)
+    {
+      If(LEqual(DIDC,0))
+      {
+        Return(0x0F)
+      }
+      Else
+      {
+        Return(CDDS(DIDF))
+      }
+    }
+
+    // Query Graphics State (active or inactive).
+
+    Method(_DGS,0)
+    {
+      If(LAnd(LEqual(And(SGMD,0x7F),0x01),CondRefOf(SNXD)))
+      {
+        Return (NXD8)
+      }
+      Return(NDDS(DIDF))
+    }
+
+    // Device Set State. (See table above.)
+
+    Method(_DSS,1)
+    {
+      If(LEqual(And(Arg0,0xC0000000),0xC0000000))
+      {
+        // State change was performed by the
+        // Video Drivers.  Simply update the
+        // New State.
+        Store(NSTE,CSTE)
+      }
+    }
+  }
+
+//device for eDP
+  Device(DD1F)
+  {
+    // Return Unique ID.
+
+    Method(_ADR,0,Serialized)
+    {
+      If(LEqual(EDPV, 0x0))
+      {
+        Return(0x1F)
+      }
+      Else
+      {
+        Return(And(0xFFFF,DIDX))
+      }
+    }
+
+    // Return the Current Status.
+
+    Method(_DCS,0)
+    {
+      If(LEqual(EDPV, 0x0))
+      {
+        Return(0x00)
+      }
+      Else
+      {
+        Return(CDDS(DIDX))
+      }
+    }
+
+    // Query Graphics State (active or inactive).
+
+    Method(_DGS,0)
+    {
+      If(LAnd(LEqual(And(SGMD,0x7F),0x01),CondRefOf(SNXD)))
+      {
+        Return (NXDX)
+      }
+      Return(NDDS(DIDX))
+    }
+
+    // Device Set State. (See table above.)
+
+    Method(_DSS,1)
+    {
+      If(LEqual(And(Arg0,0xC0000000),0xC0000000))
+      {
+        // State change was performed by the
+        // Video Drivers.  Simply update the
+        // New State.
+        Store(NSTE,CSTE)
+      }
+    }
+    // Query List of Brightness Control Levels Supported.
+
+    Method(_BCL,0)
+    {
+      // List of supported brightness levels in the following sequence.
+
+      // Level when machine has full power.
+      // Level when machine is on batteries.
+      // Other supported levels.
+      Return(Package(){80, 50, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100})
+    }
+
+    // Set the Brightness Level.
+
+    Method (_BCM,1)
+    {
+      // Set the requested level if it is between 0 and 100%.
+
+      If(LAnd(LGreaterEqual(Arg0,0),LLessEqual(Arg0,100)))
+      {
+        \_SB.PCI0.GFX0.AINT(1, Arg0)
+        Store(Arg0,BRTL)  // Store Brightness Level.
+      }
+    }
+
+    // Brightness Query Current level.
+
+    Method (_BQC,0)
+    {
+      Return(BRTL)
+    }
+  }
+  
+  Method(SDDL,1)
+  {
+    Increment(NDID)
+    Store(And(Arg0,0xF0F),Local0)
+    Or(0x80000000,Local0, Local1)
+    If(LEqual(DIDL,Local0))
+    {
+      Return(Local1)
+    }
+    If(LEqual(DDL2,Local0))
+    {
+      Return(Local1)
+    }
+    If(LEqual(DDL3,Local0))
+    {
+      Return(Local1)
+    }
+    If(LEqual(DDL4,Local0))
+    {
+      Return(Local1)
+    }
+    If(LEqual(DDL5,Local0))
+    {
+      Return(Local1)
+    }
+    If(LEqual(DDL6,Local0))
+    {
+      Return(Local1)
+    }
+    If(LEqual(DDL7,Local0))
+    {
+      Return(Local1)
+    }
+    If(LEqual(DDL8,Local0))
+    {
+      Return(Local1)
+    }
+    If(LEqual(DDL9,Local0))
+    {
+      Return(Local1)
+    }
+    If(LEqual(DD10,Local0))
+    {
+      Return(Local1)
+    }
+    If(LEqual(DD11,Local0))
+    {
+      Return(Local1)
+    }
+    If(LEqual(DD12,Local0))
+    {
+      Return(Local1)
+    }
+    If(LEqual(DD13,Local0))
+    {
+      Return(Local1)
+    }
+    If(LEqual(DD14,Local0))
+    {
+      Return(Local1)
+    }
+    If(LEqual(DD15,Local0))
+    {
+      Return(Local1)
+    }
+    Decrement(NDID) // AMI_OVERRIDE
+    Return(0)
+  }
+
+  Method(CDDS,1)
+  {
+    Store(And(Arg0,0xF0F),Local0)
+      
+    If(LEqual(0, Local0))
+    {
+      Return(0x1D)
+    }
+    If(LEqual(CADL, Local0))
+    {
+      Return(0x1F)
+    }
+    If(LEqual(CAL2, Local0))
+    {
+      Return(0x1F)
+    }
+    If(LEqual(CAL3, Local0))
+    {
+      Return(0x1F)
+    }
+    If(LEqual(CAL4, Local0))
+    {
+      Return(0x1F)
+    }
+    If(LEqual(CAL5, Local0))
+    {
+      Return(0x1F)
+    }
+    If(LEqual(CAL6, Local0))
+    {
+      Return(0x1F)
+    }
+    If(LEqual(CAL7, Local0))
+    {
+      Return(0x1F)
+    }
+    If(LEqual(CAL8, Local0))
+    {
+      Return(0x1F)
+    }
+    Return(0x1D)
+  }  
+  
+  Method(NDDS,1)
+  {
+    Store(And(Arg0,0xF0F),Local0)
+      
+    If(LEqual(0, Local0))
+    {
+      Return(0)
+    }
+    If(LEqual(NADL, Local0))
+    {
+      Return(1)
+    }
+    If(LEqual(NDL2, Local0))
+    {
+      Return(1)
+    }
+    If(LEqual(NDL3, Local0))
+    {
+      Return(1)
+    }
+    If(LEqual(NDL4, Local0))
+    {
+      Return(1)
+    }
+    If(LEqual(NDL5, Local0))
+    {
+      Return(1)
+    }
+    If(LEqual(NDL6, Local0))
+    {
+      Return(1)
+    }
+    If(LEqual(NDL7, Local0))
+    {
+      Return(1)
+    }
+    If(LEqual(NDL8, Local0))
+    {
+      Return(1)
+    }
+    Return(0)
+  }  
+
+  // Include IGD OpRegion/Software SCI interrupt handler which is use by
+  // the graphics drivers to request data from system BIOS.
+
+  include ("IgdOpRn.ASL")
+//
+// iGfx WA for HSW. Exclude the memory range 20000000-201FFFFF (2MB) and 0x40004000-0x40004FFF (4KB
+//
+Device(\_SB.MEM2)
+{
+  Name(_HID, EISAID("PNP0C01"))   // Hardware Device ID
+  Name(_UID, 2)
+
+  Name(CRS2, ResourceTemplate()
+  {
+    Memory32Fixed (ReadWrite, 0x20000000, 0x00200000)
+    Memory32Fixed (ReadWrite, 0x40004000, 0x00001000)
+  })
+  
+  Method(_STA,0)
+  {
+    If(IGDS)
+    {
+      If (LEqual(PNHM,0x000306C1))
+      {
+        Return(0xF) // then enabled
+      }
+    } 
+    Return(0) // then disabled
+  }
+
+  Method (_CRS, 0)
+  {
+    Return(CRS2)
+  }
+  
+}
diff --git a/ReferenceCode/Chipset/SystemAgent/AcpiTables/SaSsdt/IgdOGBDA.ASL b/ReferenceCode/Chipset/SystemAgent/AcpiTables/SaSsdt/IgdOGBDA.ASL
new file mode 100644
index 0000000..e28ce5c
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/AcpiTables/SaSsdt/IgdOGBDA.ASL
@@ -0,0 +1,164 @@
+/*++
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement
+--*/
+
+/*++
+
+Copyright (c)  1999 - 2012 Intel Corporation. All rights reserved
+This software and associated documentation (if any) is furnished
+under a license and may only be used or copied in accordance
+with the terms of the license. Except as permitted by such
+license, no part of this software or documentation may be
+reproduced, stored in a retrieval system, or transmitted in any
+form or by any means without the express written consent of
+Intel Corporation.
+
+
+Module Name:
+
+  IgdOGBDA.ASL
+
+Abstract:
+
+  IGD OpRegion/Software SCI Reference Code.
+  This file contains Get BIOS Data Area funciton support for
+  the Integrated Graphics Device (IGD) OpRegion/Software SCI mechanism.
+
+--*/
+
+
+Method (GBDA, 0, Serialized)
+{
+
+  // Supported calls: Sub-function 0
+
+  If (LEqual(GESF, 0))
+  {
+    //<TODO> Update implementation specific supported calls.  Reference
+    // code is set to Intel's validated implementation.
+
+    Store(0x0000659, PARM)
+
+    Store(Zero, GESF)		// Clear the exit parameter
+    Return(SUCC)			// Success
+  }
+
+  // Requested callbacks: Sub-function 1
+
+  If (LEqual(GESF, 1))
+  {
+
+    //<TODO> Update implementation specific system BIOS requested call
+    // back functions.  Call back functions are where the driver calls the
+    // system BIOS at function indicated event.
+
+    Store(0x300482, PARM)
+    If(LEqual(S0ID, One)){
+      Or(PARM, 0x100, PARM) //Request Fn 8 callback in CS systems
+    }
+    Store(Zero, GESF)		// Clear the exit parameter
+    Return(SUCC)			// Success
+  }
+
+  // Get Boot display Preferences: Sub-function 4
+
+  If (LEqual(GESF, 4))
+  {
+
+    //<TODO> Update the implementation specific Get Boot Display
+    // Preferences function.
+
+    And(PARM, 0xEFFF0000, PARM)	// PARM[30:16] = Boot device ports
+    And(PARM, ShiftLeft(DeRefOf(Index(DBTB, IBTT)), 16), PARM)
+    Or(IBTT, PARM, PARM)		// PARM[7:0] = Boot device type
+
+    Store(Zero, GESF)		// Clear the exit parameter
+    Return(SUCC)			// Success
+  }
+
+  // Panel details: Sub-function 5
+
+  If (LEqual(GESF, 5))
+  {
+
+    //<TODO> Update the implementation specific Get Panel Details
+    // function.
+
+    Store(IPSC, PARM)		// Report the scaling setting
+    Or(PARM, ShiftLeft(IPAT, 8), PARM)
+    Add(PARM, 0x100, PARM)		// Adjust panel type, 0 = VBT default
+    Or(PARM, ShiftLeft(LIDS, 16), PARM) // Report the lid state
+    Add(PARM, 0x10000, PARM)	// Adjust the lid state, 0 = Unknown
+    Or(PARM, ShiftLeft(IBIA, 20), PARM) // Report the BIA setting
+    Store(Zero, GESF)
+    Return(SUCC)
+  }
+
+  // Internal graphics: Sub-function 7
+
+  If (LEqual(GESF, 7))
+  {
+    Store(GIVD, PARM)		// PARM[0]      - VGA mode(1=VGA)
+    Xor(PARM, 1, PARM)		// Invert the VGA mode polarity
+    Or(PARM, ShiftLeft(GMFN, 1), PARM) // PARM[1]   - # IGD PCI functions-1
+                                       // PARM[3:2]    - Reserved
+                                       // PARM[4]      - IGD D3 support(0=cold)
+                                       // PARM[10:5]   - Reserved
+    Or(PARM, ShiftLeft(3, 11), PARM) // PARM[12:11] - DVMT mode(11b = 5.0)
+
+    //
+    // Report DVMT 5.0 Total Graphics memory size.
+    //
+    Or(PARM, ShiftLeft(IDMS, 17), PARM)   // Bits 20:17 are for Gfx total memory size
+
+    // If the "Set Internal Graphics" call is supported, the modified
+    // settings flag must be programmed per the specification.  This means
+    // that the flag must be set to indicate that system BIOS requests
+    // these settings.  Once "Set Internal Graphics" is called, the
+    //  modified settings flag must be cleared on all subsequent calls to
+    // this function.
+
+    // Report the graphics frequency based on B0:D2:F0:RF0h[12].  Must
+    // take into account the current VCO.
+
+    Or(ShiftLeft(Derefof(Index(Derefof(Index(CDCT, HVCO)), CDVL)), 21),PARM, PARM)
+
+    Store(1, GESF)			// Set the modified settings flag
+    Return(SUCC)
+  }
+
+  // Spread spectrum clocks: Sub-function 10
+
+  If (LEqual(GESF, 10))
+  {
+
+    Store(0, PARM)			// Assume SSC is disabled
+
+    If(ISSC)
+    {
+      Or(PARM, 3, PARM)	// If SSC enabled, return SSC1+Enabled
+    }
+
+    Store(0, GESF)			// Set the modified settings flag
+    Return(SUCC)			// Success
+  }
+
+
+  If (LEqual(GESF, 11))
+  {
+    Store(KSV0, PARM)		// First four bytes of AKSV
+    Store(KSV1, GESF)		// Fifth byte of AKSV
+
+    Return(SUCC)			// Success
+  }
+
+  // A call to a reserved "Get BIOS data" function was received.
+
+  Store(Zero, GESF)			// Clear the exit parameter
+  Return(CRIT)				// Reserved, "Critical failure"
+}
diff --git a/ReferenceCode/Chipset/SystemAgent/AcpiTables/SaSsdt/IgdOMOBF.ASL b/ReferenceCode/Chipset/SystemAgent/AcpiTables/SaSsdt/IgdOMOBF.ASL
new file mode 100644
index 0000000..07a716b
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/AcpiTables/SaSsdt/IgdOMOBF.ASL
@@ -0,0 +1,560 @@
+/*++
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement
+--*/
+
+/*++
+
+Copyright (c)  1999 - 2013 Intel Corporation. All rights reserved
+This software and associated documentation (if any) is furnished
+under a license and may only be used or copied in accordance
+with the terms of the license. Except as permitted by such
+license, no part of this software or documentation may be
+reproduced, stored in a retrieval system, or transmitted in any
+form or by any means without the express written consent of
+Intel Corporation.
+
+
+Module Name:
+
+  IgdOMOBF.ASL
+
+Abstract:
+
+  IGD OpRegion/Software SCI Reference Code.
+  This file contains ASL code with the purpose of handling events
+  i.e. hotkeys and other system interrupts.
+
+--*/
+
+
+// Notes:
+// 1. The following routines are to be called from the appropriate event
+//    handlers.
+// 2. This code cannot comprehend the exact implementation in the OEM's BIOS.
+//    Therefore, an OEM must call these methods from the existing event
+//    handler infrastructure.  Details on when/why to call each method is
+//    included in the method header under the "usage" section.
+
+
+/************************************************************************;
+;* ACPI Notification Methods
+;************************************************************************/
+
+
+/************************************************************************;
+;*
+;* Name:	PDRD
+;*
+;* Description:	Check if the graphics driver is ready to process
+;*		notifications and video extensions.
+;*
+;* Usage:	This method is to be called prior to performing any
+;*		notifications or handling video extensions.
+;*		Ex: If (PDRD()) {Return (FAIL)}
+;*
+;* Input:	None
+;*
+;* Output:	None
+;*
+;* References:	DRDY (Driver ready status), ASLP (Driver recommended
+;*		sleep timeout value).
+;*
+;************************************************************************/
+
+External(HNOT, MethodObj)
+
+Method(PDRD)
+{
+
+		// Sleep for ASLP milliseconds if the driver is not ready.
+
+
+	// If DRDY is clear, the driver is not ready.  If the return value is
+	// !=0, do not perform any notifications or video extension handling.
+
+	Return(LNot(DRDY))
+}
+
+
+/************************************************************************;
+;*
+;* Name:	PSTS
+;*
+;* Description:	Check if the graphics driver has completed the previous
+;*		"notify" command.
+;*
+;* Usage:	This method is called before every "notify" command.  A
+;*		"notify" should only be set if the driver has completed the
+;*		previous command.  Else, ignore the event and exit the parent
+;*		method.
+;*		Ex: If (PSTS()) {Return (FAIL)}
+;*
+;* Input:	None
+;*
+;* Output:	None
+;*
+;* References:	CSTS (Notification status), ASLP (Driver recommended sleep
+;*		timeout value).
+;*
+;************************************************************************/
+
+Method(PSTS)
+{
+	If(LGreater(CSTS, 2))
+	{
+		// Sleep for ASLP milliseconds if the status is not "success,
+		// failure, or pending"
+		//
+		Sleep(ASLP)
+	}
+
+	Return(LEqual(CSTS, 3))		// Return True if still Dispatched
+}
+
+
+/************************************************************************;
+;*
+;* Name:	GNOT
+;*
+;* Description:	Call the appropriate methods to query the graphics driver
+;*		status.  If all methods return success, do a notification of
+;*		the graphics device.
+;*
+;* Usage:	This method is to be called when a graphics device
+;*		notification is required (display switch hotkey, etc).
+;*
+;* Input:	Arg0 = Current event type:
+;*			1 = display switch
+;*			2 = lid
+;*			3 = dock
+;*		Arg1 = Notification type:
+;*			0 = Re-enumeration
+;*			0x80 = Display switch
+;*
+;* Output:	Returns 0 = success, 1 = failure
+;*
+;* References:	PDRD and PSTS methods.  OSYS (OS version)
+;*
+;************************************************************************/
+
+Method(GNOT, 2)
+{
+	// Check for 1. Driver loaded, 2. Driver ready.
+	// If any of these cases is not met, skip this event and return failure.
+	//
+	If(PDRD())
+	{
+		Return(0x1)		// Return failure if driver not loaded.
+	}
+
+	Store(Arg0, CEVT)		// Set up the current event value
+	Store(3, CSTS)			// CSTS=BIOS dispatched an event
+
+	If(LAnd(LEqual(CHPD, 0), LEqual(Arg1, 0)))	// Do not re-enum if driver supports hotplug
+	{
+		If(LOr(LGreater(OSYS, 2000), LLess(OSYS, 2006)))
+		{
+			//
+			// WINXP requires that the entire PCI Bridge be re-enumerated.
+			//
+			Notify(\_SB.PCI0, Arg1)
+		}
+		Else
+		{
+			//
+			// Re-enumerate the Graphics Device for non-XP operating systems.
+			//
+			Notify(\_SB.PCI0.GFX0, Arg1)
+		}
+	}
+
+	If(CondRefOf(HNOT))
+	{
+		HNOT(Arg0)  //Notification handler for Switchable graphics
+	}
+	Else
+	{
+		Notify(\_SB.PCI0.GFX0,0x80)
+	}
+
+	Return(0x0)			// Return success
+}
+
+
+/************************************************************************;
+;*
+;* Name:	GHDS
+;*
+;* Description:	Handle a hotkey display switching event (performs a
+;*		Notify(GFX0, 0).
+;*
+;* Usage:	This method must be called when a hotkey event occurs and the
+;*		purpose of that hotkey is to do a display switch.
+;*
+;* Input:	Arg0 = Toggle table number.
+;*
+;* Output:	Returns 0 = success, 1 = failure.
+;*		CEVT and TIDX are indirect outputs.
+;*
+;* References:	TIDX, GNOT
+;*
+;************************************************************************/
+
+Method(GHDS, 1)
+{
+	Store(Arg0, TIDX)		// Store the table number
+
+	// Call GNOT for CEVT = 1 = hotkey, notify value = 0
+
+	Return(GNOT(1, 0))		// Return stats from GNOT
+}
+
+
+/************************************************************************;
+;*
+;* Name:	GLID
+;*
+;* Description:	Handle a lid event (performs the Notify(GFX0, 0), but not the
+;*		lid notify).
+;*
+;* Usage:	This method must be called when a lid event occurs.  A
+;*		Notify(LID0, 0x80) must follow the call to this method.
+;*
+;* Input:	Arg0 = Lid state:
+;*			0 = All closed
+;*			1 = internal LFP lid open
+;*			2 = external lid open
+;*			3 = both external and internal open
+;*
+;* Output:	Returns 0=success, 1=failure.
+;*		CLID and CEVT are indirect outputs.
+;*
+;* References:	CLID, GNOT
+;*
+;************************************************************************/
+
+Method(GLID, 1)
+{
+
+        If (LEqual(Arg0,1))
+	{
+           Store(3,CLID)
+        }
+	Else
+	{
+           Store(Arg0, CLID)
+        }
+
+        //Store(Arg0, CLID)		// Store the current lid state
+
+	// Call GNOT for CEVT=2=Lid, notify value = 0
+
+	if (GNOT(2, 0)) {
+	  Or (CLID, 0x80000000, CLID)
+	  Return (1)		// Return Fail
+	}
+
+	Return (0)		// Return Pass
+}
+
+
+/************************************************************************;
+;*
+;* Name:	GDCK
+;*
+;* Description:	Handle a docking event by updating the current docking status
+;*		and doing a notification.
+;*
+;* Usage:	This method must be called when a docking event occurs.
+;*
+;* Input:	Arg0 = Docking state:
+;*			0 = Undocked
+;*			1 = Docked
+;*
+;* Output:	Returns 0=success, 1=failure.
+;*		CDCK and CEVT are indirect outputs.
+;*
+;* References:	CDCK, GNOT
+;*
+;************************************************************************/
+
+Method(GDCK, 1)
+{
+	Store(Arg0, CDCK)		// Store the current dock state
+
+	// Call GNOT for CEVT=4=Dock, notify value = 0
+
+	Return(GNOT(4, 0))		// Return stats from GNOT
+}
+
+
+/************************************************************************;
+;* ASLE Interrupt Methods
+;************************************************************************/
+
+
+/************************************************************************;
+;*
+;* Name:	PARD
+;*
+;* Description:	Check if the driver is ready to handle ASLE interrupts
+;*		generate by the system BIOS.
+;*
+;* Usage:	This method must be called before generating each ASLE
+;*		interrupt.
+;*
+;* Input:	None
+;*
+;* Output:	Returns 0 = success, 1 = failure.
+;*
+;* References:	ARDY (Driver readiness), ASLP (Driver recommended sleep
+;*		timeout value)
+;*
+;************************************************************************/
+
+Method(PARD)
+{
+	If(LNot(ARDY))
+	{
+
+		// Sleep for ASLP milliseconds if the driver is not ready.
+
+		Sleep(ASLP)
+	}
+
+	// If ARDY is clear, the driver is not ready.  If the return value is
+	// !=0, do not generate the ASLE interrupt.
+
+	Return(LNot(ARDY))
+}
+
+//
+// Intel Ultrabook Event Handler.  Arg0 represents the Ultrabook Event Bit # to pass
+// to the Intel Graphics Driver.  Note that this is a serialized method, meaning
+// sumultaneous events are not allowed.
+//
+
+Method(IUEH,1,Serialized)
+{
+  And(IUER,0xC0,IUER)   			// Clear all button events on entry.
+  XOr(IUER,Shiftleft(1,Arg0),IUER)	        // Toggle status.
+
+  If(LLessEqual(Arg0,4))			// Button Event?
+  {
+   	Return(AINT(5,0))			// Generate event and return status.
+
+  }
+  Else						// Indicator Event.
+  {
+        Return(AINT(Arg0,0))			// Generate event and return status.
+  }
+}
+
+/************************************************************************;
+;*
+;* Name:	AINT
+;*
+;* Description:	Call the appropriate methods to generate an ASLE interrupt.
+;*		This process includes ensuring the graphics driver is ready
+;*		to process the interrupt, ensuring the driver supports the
+;*		interrupt of interest, and passing information about the event
+;*		to the graphics driver.
+;*
+;* Usage:	This method must called to generate an ASLE interrupt.
+;*
+;* Input:	Arg0 = ASLE command function code:
+;*			0 = Set ALS illuminance
+;*			1 = Set backlight brightness
+;*			2 = Do Panel Fitting
+;*			4 = Reserved
+;*			5 = Button Indicator Event
+;*			6 = Convertible Indicator Event
+;*			7 = Docking Indicator Event
+;*		Arg1 = If Arg0 = 0, current ALS reading:
+;*			0 = Reading below sensor range
+;*			1-0xFFFE = Current sensor reading
+;*			0xFFFF = Reading above sensor range
+;*		Arg1 = If Arg0 = 1, requested backlight percentage
+;*
+;* Output:	Returns 0 = success, 1 = failure
+;*
+;* References:	PARD method.
+;*
+;************************************************************************/
+
+Method(AINT, 2)
+{
+
+	// Return failure if the requested feature is not supported by the
+	// driver.
+
+	If(LNot(And(TCHE, ShiftLeft(1, Arg0))))
+	{
+		Return(0x1)
+	}
+
+	// Return failure if the driver is not ready to handle an ASLE
+	// interrupt.
+
+	If(PARD())
+	{
+  		Return(0x1)
+	}
+
+	// Handle Intel Ultrabook Events.
+
+	If(LAnd(LGreaterEqual(Arg0,5),LLessEqual(Arg0,7)))
+	{
+		Store(ShiftLeft(1,Arg0), ASLC)				// Set Ultrbook Event [6:4].
+		Store(0x01, ASLE)               			// Generate ASLE interrupt
+
+		Store(0,Local2)						// Use Local2 as a timeout counter.  Intialize to zero.
+
+    		While(LAnd(LLess(Local2,250),LNotEqual(ASLC,0)))	// Wait 1 second or until Driver ACKs a success.
+    		{
+			Sleep(4)					// Delay 4 ms.
+			Increment(Local2)				// Increment Timeout.
+		}
+
+		Return(0)					// Return success
+	}
+
+	// Evaluate the first argument (Panel fitting, backlight brightness, or ALS).
+
+	If(LEqual(Arg0, 2))		// Arg0 = 2, so request a panel fitting mode change.
+	{
+		If(CPFM)					// If current mode field is non-zero use it.
+		{
+			And(CPFM, 0x0F, Local0)			// Create variables without reserved
+			And(EPFM, 0x0F, Local1)			// or valid bits.
+
+			If(LEqual(Local0, 1))			// If current mode is centered,
+			{
+				If(And(Local1, 6))		// and if stretched is enabled,
+				{
+					Store(6, PFIT)		// request stretched.
+				}
+				Else				// Otherwise,
+				{
+					If(And(Local1, 8))	// if aspect ratio is enabled,
+					{
+						Store(8, PFIT)	// request aspect ratio.
+					}
+					Else			// Only centered mode is enabled
+					{
+						Store(1, PFIT)	// so request centered. (No change.)
+					}
+				}
+			}
+			If(LEqual(Local0, 6))			// If current mode is stretched,
+			{
+				If(And(Local1, 8))		// and if aspect ratio is enabled,
+				{
+					Store(8, PFIT)		// request aspect ratio.
+				}
+				Else				// Otherwise,
+				{
+					If(And(Local1, 1))	// if centered is enabled,
+					{
+						Store(1, PFIT)	// request centered.
+					}
+					Else			// Only stretched mode is enabled
+					{
+						Store(6, PFIT)	// so request stretched. (No change.)
+					}
+				}
+			}
+			If(LEqual(Local0, 8))			// If current mode is aspect ratio,
+			{
+				If(And(Local1, 1))		// and if centered is enabled,
+				{
+					Store(1, PFIT)		// request centered.
+				}
+				Else				// Otherwise,
+				{
+					If(And(Local1, 6))	// if stretched is enabled,
+					{
+						Store(6, PFIT)	// request stretched.
+					}
+					Else			// Only aspect ratio mode is enabled
+					{
+						Store(8, PFIT)	// so request aspect ratio. (No change.)
+					}
+				}
+			}
+		}
+
+		// The following code for panel fitting (within the Else condition) is retained for backward compatiblity.
+
+		Else				// If CFPM field is zero use PFIT and toggle the
+		{
+			Xor(PFIT,7,PFIT)	// mode setting between stretched and centered only.
+		}
+
+		Or(PFIT,0x80000000,PFIT) 	// Set the valid bit for all cases.
+
+		Store(4, ASLC)			// Store "Panel fitting event" to ASLC[31:1]
+	}
+	Else
+	{
+		If(LEqual(Arg0, 1))		// Arg0=1, so set the backlight brightness.
+		{
+			Store(Divide(Multiply(Arg1, 255), 100), BCLP) // Convert from percent to 0-255.
+
+			Or(BCLP, 0x80000000, BCLP)	// Set the valid bit.
+
+			Store(2, ASLC)			// Store "Backlight control event" to ASLC[31:1]
+		}
+		Else
+		{
+			If(LEqual(Arg0, 0))		// Arg0=0, so set the ALS illuminace
+			{
+				Store(Arg1, ALSI)
+
+			  	Store(1, ASLC)		// Store "ALS event" to ASLC[31:1]
+			}
+			Else
+			{
+				Return(0x1) // Unsupported function
+			}
+		}
+	}
+
+	Store(0x01, ASLE)               // Generate ASLE interrupt
+	Return(0x0)			// Return success
+}
+
+
+/************************************************************************;
+;*
+;* Name:	SCIP
+;*
+;* Description:	Checks the presence of the OpRegion and SCI
+;*
+;* Usage:	This method is called before other OpRegion methods. The
+;*		former "GSMI True/False is not always valid.  This method
+;*		checks if the OpRegion Version is non-zero and if non-zero,
+;*		(present and readable) then checks the GSMI flag.
+;*
+;* Input:	None
+;*
+;* Output:	Boolean True = SCI present.
+;*
+;* References:	None
+;*
+;************************************************************************/
+
+Method(SCIP)
+{
+	If(LNotEqual(OVER,0))		// If OpRegion Version not 0.
+	{
+		Return(LNot(GSMI))	// Return True if SCI.
+	}
+
+	Return(0)			// Else Return False.
+}
diff --git a/ReferenceCode/Chipset/SystemAgent/AcpiTables/SaSsdt/IgdOSBCB.ASL b/ReferenceCode/Chipset/SystemAgent/AcpiTables/SaSsdt/IgdOSBCB.ASL
new file mode 100644
index 0000000..9cb0db6
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/AcpiTables/SaSsdt/IgdOSBCB.ASL
@@ -0,0 +1,335 @@
+/*++
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement
+--*/
+
+/*++
+
+Copyright (c)  1999 - 2013 Intel Corporation. All rights reserved
+This software and associated documentation (if any) is furnished
+under a license and may only be used or copied in accordance
+with the terms of the license. Except as permitted by such
+license, no part of this software or documentation may be
+reproduced, stored in a retrieval system, or transmitted in any
+form or by any means without the express written consent of
+Intel Corporation.
+
+
+Module Name:
+
+  IgdOSBCB.ASL
+
+Abstract:
+
+  This file contains the system BIOS call back functionality for the
+  OpRegion/Software SCI mechanism.
+
+--*/
+
+
+Method (SBCB, 0, Serialized)
+{
+
+  // Supported Callbacks: Sub-function 0
+
+  If (LEqual(GESF, 0x0))
+  {
+
+	//<TODO> An OEM may support the driver->SBIOS status callbacks, but
+	// the supported callbacks value must be modified.  The code that is
+	// executed upon reception of the callbacks must be also be updated
+	// to perform the desired functionality.
+
+	Store(0x00000000, PARM)		// No callbacks supported
+	//Store(0x000787FD, PARM)	// Used for Intel test implementaion
+
+	// <NOTSAMPLECODE>
+
+	Store(0x000F87DD, PARM)
+
+	// </NOTSAMPLECODE>
+
+	Store(Zero, GESF)		// Clear the exit parameter
+	Return(SUCC)			// "Success"
+  }
+
+  // BIOS POST Completion: Sub-function 1
+
+  If (LEqual(GESF, 1))
+  {
+	Store(Zero, GESF)		// Clear the exit parameter
+	Store(Zero, PARM)
+	Return(SUCC)			// Not supported, but no failure
+  }
+
+  // Pre-Hires Set Mode: Sub-function 3
+
+  If (LEqual(GESF, 3))
+  {
+	Store(Zero, GESF)		// Clear the exit parameter
+	Store(Zero, PARM)
+	Return(SUCC)			// Not supported, but no failure
+  }
+
+  // Post-Hires Set Mode: Sub-function 4
+
+  If (LEqual(GESF, 4))
+  {
+	Store(Zero, GESF)		// Clear the exit parameter
+	Store(Zero, PARM)
+	Return(SUCC)			// Not supported, but no failure
+  }
+
+  // Display Switch: Sub-function 5
+
+  If (LEqual(GESF, 5))
+  {
+	Store(Zero, GESF)		// Clear the exit parameter
+	Store(Zero, PARM)
+	Return(SUCC)			// Not supported, but no failure
+  }
+
+  // Adapter Power State: Sub-function 7
+
+  If (LEqual(GESF, 7))
+  {
+	//
+	// Handle Low Power S0 Idle Capability if enabled
+	//
+	If(LEqual(S0ID, One)){
+		//
+		// Call GUAM to trigger CS Entry
+		//   If Adapter Power State Notification = D1 (PARM[7:0]=0x01)
+		//
+		If (LEqual (And(PARM,0xFF), 0x01)) {
+			// GUAM - Global User Absent Mode Notification Method
+			\GUAM(One) // 0x01 - Power State Standby (CS Entry)
+		}
+	}
+
+  	// Upon notification from driver that the Adapter Power State = D0,
+	// check if previous lid event failed.  If it did, retry the lid
+	// event here.
+	If(LEqual(PARM, 0))
+	{
+		Store(CLID, Local0)
+		If(And(0x80000000,Local0))
+		{
+			And(CLID, 0x0000000F, CLID)
+			GLID(CLID)
+		}
+	}
+	Store(Zero, GESF)		// Clear the exit parameter
+	Store(Zero, PARM)
+	Return(SUCC)			// Not supported, but no failure
+  }
+
+  // Display Power State: Sub-function 8
+
+  If (LEqual(GESF, 8))
+  {
+	//
+	// Handle Low Power S0 Idle Capability if enabled
+	//
+	If(LEqual(S0ID, One)){
+	  // Bits [15:8] - Power State
+	  // 00h = On
+	  // 01h = Standby
+	  // 02h = Suspend
+	  // 04h = Off
+	  // 08h = Reduced On
+	  Store(And(ShiftRight(PARM, 8), 0xFF), Local0)
+  	  //
+	  // Call GUAM
+	  //   If Display Turn ON Notification (PARM [15:8] == 0) for CS Exit
+	  //
+	  If (LEqual (Local0, 0)) {
+	    // GUAM - Global User Absent Mode Notification Method
+	    \GUAM(Zero) // 0x00 - Power State On (CS Exit)
+	  }
+	}
+	Store(Zero, GESF)		// Clear the exit parameter
+	Store(Zero, PARM)
+	Return(SUCC)			// Not supported, but no failure
+  }
+
+  // Set Boot Display: Sub-function 9
+
+  If (LEqual(GESF, 9))
+  {
+
+	//<TODO> An OEM may elect to implement this method.  In that case,
+	// the input values must be saved into non-volatile storage for
+	// parsing during the next boot.  The following Sample code is Intel
+	// validated implementation.
+
+	And(PARM, 0xFF, IBTT)		// Save the boot display to NVS
+	Store(Zero, GESF)		// Clear the exit parameter
+	Store(Zero, PARM)
+	Return(SUCC)			// Reserved, "Critical failure"
+  }
+
+  // Set Panel Details: Sub-function 10 (0Ah)
+
+  If (LEqual(GESF, 10))
+  {
+
+	//<TODO> An OEM may elect to implement this method.  In that case,
+	// the input values must be saved into non-volatile storage for
+	// parsing during the next boot.  The following Sample code is Intel
+	// validated implementation.
+
+	// Set the panel-related NVRAM variables based the input from the driver.
+
+	And(PARM, 0xFF, IPSC)
+
+	// Change panel type if a change is requested by the driver (Change if
+	// panel type input is non-zero).  Zero=No change requested.
+
+	If(And(ShiftRight(PARM, 8), 0xFF))
+	{
+		And(ShiftRight(PARM, 8), 0xFF, IPAT)
+		Decrement(IPAT)		// 0 = no change, so fit to CMOS map
+	}
+	And(ShiftRight(PARM, 20), 0x7, IBIA)
+	Store(Zero, GESF)		// Clear the exit parameter
+	Store(Zero, PARM)
+	Return(SUCC)			// Success
+  }
+
+  // Set Internal Graphics: Sub-function 11 (0Bh)
+
+  If (LEqual(GESF, 11))
+  {
+
+	//<TODO> An OEM may elect to implement this method.  In that case,
+	// the input values must be saved into non-volatile storage for
+	// parsing during the next boot.  The following Sample code is Intel
+	// validated implementation.
+
+	And(ShiftRight(PARM, 1), 1, IF1E) // Program the function 1 option
+
+	If(And(PARM, ShiftLeft(0xF, 13))) // Use fixed memory if fixed size != 0
+	{
+
+		// Fixed memory
+
+		And(ShiftRight(PARM, 13), 0xF, IDMS) // Program fixed memory size
+	}
+	Else
+	{
+
+		// DVMT memory
+
+		And(ShiftRight(PARM, 17), 0xF, IDMS) // Program fixed memory size
+	}
+	Store(Zero, GESF)		// Clear the exit parameter
+	Store(Zero, PARM)
+	Return(SUCC)			// Success
+  }
+
+  // Post-Hires to DOS FS: Sub-function 16 (10h)
+
+  If (LEqual(GESF, 16))
+  {
+	Store(Zero, GESF)		// Clear the exit parameter
+	Store(Zero, PARM)
+	Return(SUCC)			// Not supported, but no failure
+  }
+
+  // APM Complete:  Sub-function 17 (11h)
+
+  If (LEqual(GESF, 17))
+  {
+
+	Store(ShiftLeft(LIDS, 8), PARM)	// Report the lid state
+	Add(PARM, 0x100, PARM)		// Adjust the lid state, 0 = Unknown
+
+	Store(Zero, GESF)		// Clear the exit parameter
+	Return(SUCC)			// Not supported, but no failure
+  }
+
+  // Set Spread Spectrum Clocks: Sub-function 18 (12h)
+
+  If (LEqual(GESF, 18))
+  {
+
+	//<TODO> An OEM may elect to implement this method.  In that case,
+	// the input values must be saved into non-volatile storage for
+	// parsing during the next boot.  The following Sample code is Intel
+	// validated implementation.
+
+	If(And(PARM, 1))
+	{
+		If(LEqual(ShiftRight(PARM, 1), 1))
+		{
+			Store(1, ISSC)	// Enable HW SSC, only for clock 1
+		}
+		Else
+		{
+			Store(Zero, GESF)
+			Return(CRIT)	// Failure, as the SSC clock must be 1
+		}
+	}
+	Else
+	{
+		Store(0, ISSC)		// Disable SSC
+	}
+	Store(Zero, GESF)		// Clear the exit parameter
+	Store(Zero, PARM)
+	Return(SUCC)			// Success
+  }
+
+  // Post VBE/PM Callback: Sub-function 19 (13h)
+
+  If (LEqual(GESF, 19))
+  {
+	Store(Zero, GESF)		// Clear the exit parameter
+	Store(Zero, PARM)
+	Return(SUCC)			// Not supported, but no failure
+  }
+
+  // Set PAVP Data: Sub-function 20 (14h)
+
+  If (LEqual(GESF, 20))
+  {
+	And(PARM, 0xF, PAVP)	// Store PAVP info
+	Store(Zero, GESF)		// Clear the exit parameter
+	Store(Zero, PARM)
+	Return(SUCC)			// Success
+  }
+
+  // Enable/Disable Audio: Sub-function 21 (15h)
+
+  If (LEqual(GESF, 21))
+  {
+    If(LEqual(PARM,1))
+    {
+      OR (\_SB.PCI0.AUDE, 0x20,\_SB.PCI0.AUDE)
+      \_SB.PCI0.B0D3.ABWA (1)
+      \_SB.PCI0.B0D3.ARST ()
+      \_SB.PCI0.B0D3.ASTR ()
+      \_SB.PCI0.B0D3.AINI ()
+      \_SB.PCI0.B0D3.CXDC ()
+      \_SB.PCI0.B0D3.ABWA (0)
+      Notify(\_SB.PCI0,0)
+    }
+    If(LEqual(PARM,0))
+    {
+      AND (\_SB.PCI0.AUDE, 0xDF,\_SB.PCI0.AUDE)
+      Notify(\_SB.PCI0,0)
+    }
+    Store(Zero, GESF)
+    Store(Zero, PARM)
+    Return(SUCC)
+  }
+
+  // A call to a reserved "System BIOS callbacks" function was received
+
+  Store(Zero, GESF)			// Clear the exit parameter
+  Return(SUCC)				// Reserved, "Critical failure"
+}
diff --git a/ReferenceCode/Chipset/SystemAgent/AcpiTables/SaSsdt/IgdOpRn.ASL b/ReferenceCode/Chipset/SystemAgent/AcpiTables/SaSsdt/IgdOpRn.ASL
new file mode 100644
index 0000000..56d3f71
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/AcpiTables/SaSsdt/IgdOpRn.ASL
@@ -0,0 +1,342 @@
+/*++
+  This file contains an 'Intel Peripheral Driver' and uniquely  
+  identified as "Intel Reference Module" and is                 
+  licensed for Intel CPUs and chipsets under the terms of your  
+  license agreement with Intel or your vendor.  This file may   
+  be modified by the user, subject to additional terms of the   
+  license agreement                                             
+--*/
+
+/*++
+
+Copyright (c)  1999 - 2013 Intel Corporation. All rights reserved
+This software and associated documentation (if any) is furnished
+under a license and may only be used or copied in accordance
+with the terms of the license. Except as permitted by such
+license, no part of this software or documentation may be
+reproduced, stored in a retrieval system, or transmitted in any
+form or by any means without the express written consent of
+Intel Corporation.
+
+
+Module Name:
+
+  IgdOpRn.ASL
+
+Abstract:
+
+  IGD OpRegion/Software SCI Reference Code.
+  This file contains the interrupt handler code for the Integrated
+  Graphics Device (IGD) OpRegion/Software SCI mechanism.
+
+--*/
+
+
+//NOTES:
+//
+// (1)	The code contained in this file inherits the scope in which it
+//	was included.  So BIOS developers must be sure to include this
+//	file in the scope associated with the graphics device
+//	(ex. \_SB.PCI0.GFX0).
+// (2)	Create a _L06 method under the GPE scope to handle the event
+//	generated by the graphics driver.  The _L06 method must call
+//	the GSCI method in this file.
+// (3)	The MCHP operation region assumes that _ADR and _BBN names
+//	corresponding to bus 0, device0, function 0 have been declared
+//	under the PCI0 scope.
+// (4)	Before the first execution of the GSCI method, the base address
+//	of the GMCH SCI OpRegion must be programmed where the driver can
+//	access it. A 32bit scratch register at 0xFC in the IGD PCI
+//	configuration space (B0/D2/F0/R0FCh) is used for this purpose.
+
+//  Define an OperationRegion to cover the GMCH PCI configuration space as
+//  described in the IGD OpRegion specificiation.
+
+Scope(\_SB.PCI0)
+{
+	OperationRegion(MCHP, PCI_Config, 0x40, 0xC0)
+	Field(MCHP, AnyAcc, NoLock, Preserve)
+	{
+                Offset(0x14),
+                AUDE,    8,
+
+		Offset(0x60),		// Top of Memory register
+		TASM,	10,		// Total system memory (64MB gran)
+		    ,	6,
+	}
+}
+
+//  Define an OperationRegion to cover the IGD PCI configuration space as
+//  described in the IGD OpRegion specificiation.
+
+OperationRegion(IGDP, PCI_Config, 0x40, 0xC0)
+Field(IGDP, AnyAcc, NoLock, Preserve)
+{
+	Offset(0x12),			// Mirror of gfx control reg
+	    ,	1,
+	GIVD,	1,			// IGD VGA disable bit
+	    ,	2,
+	GUMA,	3,			// Stolen memory size
+	    ,	9,
+	Offset(0x14),
+	    ,	4,
+	GMFN,	1,			// Gfx function 1 enable
+	    ,	27,
+	Offset(0xA4),
+	ASLE,	8,			// Reg 0xE4, ASLE interrupt register
+	    ,	24,			// Only use first byte of ASLE reg
+	Offset(0xA8),			// Reg 0xE8, SWSCI control register
+	GSSE,	1,			// Graphics SCI event (1=event pending)
+	GSSB,	14,			// Graphics SCI scratchpad bits
+	GSES,	1,			// Graphics event select (1=SCI)
+	Offset(0xB0),			// Gfx Clk Frequency and Gating Control
+	    ,	12,
+	CDVL,	1,			// Core display clock value
+	    ,	3,			// Graphics Core Display Clock Select
+	Offset(0xB5),
+	LBPC,	8,			// Legacy brightness control
+	Offset(0xBC),
+	ASLS,	32,			// Reg 0xFC, Address of the IGD OpRegion
+}
+
+//  Define an OperationRegion to cover the IGD OpRegion layout.
+
+OperationRegion(IGDM, SystemMemory, ASLB, 0x2000)
+Field(IGDM, AnyAcc, NoLock, Preserve)
+{
+
+	// OpRegion Header
+
+	SIGN,	128,			// Signature-"IntelGraphicsMem"
+	SIZE,	32,			// OpRegion Size
+	OVER,	32,			// OpRegion Version
+	SVER,	256,			// System BIOS Version
+	VVER,	128,			// VBIOS Version
+	GVER,	128,			// Driver version
+	MBOX,	32,			// Mailboxes supported
+	DMOD,	32,			// Driver Model
+	PCON,	32,			// Platform Configuration
+	DVER,	64,			// GOP Version
+	// OpRegion Mailbox 1 (Public ACPI Methods)
+	// Note: Mailbox 1 is normally reserved for desktop platforms.
+
+	Offset(0x100),
+	DRDY,	32,			// Driver readiness (ACPI notification)
+	CSTS,	32,			// Notification status
+	CEVT,	32,			// Current event
+	Offset(0x120),	
+	DIDL,	32,			// Supported display device ID list
+	DDL2,	32,			// Allows for 8 devices
+	DDL3,	32,
+	DDL4,	32,
+	DDL5,	32,
+	DDL6,	32,
+	DDL7,	32,
+	DDL8,	32,
+	CPDL,	32,			// Currently present display list
+	CPL2,	32,			// Allows for 8 devices
+	CPL3,	32,
+	CPL4,	32,
+	CPL5,	32,
+	CPL6,	32,
+	CPL7,	32,
+	CPL8,	32,
+	CADL,	32,			// Currently active display list
+	CAL2,	32,			// Allows for 8 devices
+	CAL3,	32,
+	CAL4,	32,
+	CAL5,	32,
+	CAL6,	32,
+	CAL7,	32,
+	CAL8,	32,
+	NADL,	32,			// Next active display list
+	NDL2,	32,			// Allows for 8 devices
+	NDL3,	32,
+	NDL4,	32,
+	NDL5,	32,
+	NDL6,	32,
+	NDL7,	32,
+	NDL8,	32,
+	ASLP,	32,			// ASL sleep timeout
+	TIDX,	32,			// Toggle table index
+	CHPD,	32,			// Current hot plug enable indicator
+	CLID,	32,			// Current lid state indicator
+	CDCK,	32,			// Current docking state indicator
+	SXSW,	32,			// Display switch notify on resume
+	EVTS,	32,			// Events supported by ASL (diag only)
+	CNOT,	32,			// Current OS notifications (diag only) 
+	NRDY,	32,	
+        //  Extended DIDL list
+        DDL9,   32,     
+        DD10,   32,
+        DD11,   32,
+        DD12,   32,
+        DD13,   32,
+        DD14,   32,
+        DD15,   32,
+        //Extended Currently attached Display Device List  CPD2
+        CPL9,   32,
+        CP10,   32,
+        CP11,   32,
+        CP12,   32,
+        CP13,   32,
+        CP14,   32,
+        CP15,   32,
+        // OpRegion Mailbox 2 (Software SCI Interface)
+
+	Offset(0x200),			// SCIC
+	SCIE,	1,			// SCI entry bit (1=call unserviced)
+	GEFC,	4,			// Entry function code
+	GXFC,	3,			// Exit result
+	GESF,	8,			// Entry/exit sub-function/parameter
+	    ,	16,			// SCIC[31:16] reserved
+	Offset(0x204),			// PARM
+	PARM,	32,			// PARM register (extra parameters)
+	DSLP,	32,			// Driver sleep time out
+
+	// OpRegion Mailbox 3 (BIOS to Driver Notification)
+	// Note: Mailbox 3 is normally reserved for desktop platforms.
+	
+	Offset(0x300),
+	ARDY,	32,			// Driver readiness (power conservation)
+	ASLC,	32,			// ASLE interrupt command/status
+	TCHE,	32,			// Technology enabled indicator
+	ALSI,	32,			// Current ALS illuminance reading
+	BCLP,	32,			// Backlight brightness
+	PFIT,	32,			// Panel fitting state or request
+	CBLV,	32,			// Current brightness level
+	BCLM,	320,			// Backlight brightness level duty cycle mapping table
+	CPFM,	32,			// Current panel fitting mode
+	EPFM,	32,			// Enabled panel fitting modes
+	PLUT,	592,			// Optional. 74-byte Panel LUT Table
+	PFMB,	32,			// Optional. PWM Frequency and Minimum Brightness
+	CCDV,	32,			// Optional. Gamma, Brightness, Contrast values.
+	PCFT,	32,			// Optional. Power Conservation Features
+	SROT,	32,			// Supported rotation angle.
+	IUER,	32,			// Optional. Intel Ultrabook Event Register.
+	FDSP,	64,			// Optional. FFS Display Physical address
+	FDSS,	32,			// Optional. FFS Display Size
+	STAT,	32,			// State Indicator
+
+	// OpRegion Mailbox 4 (VBT)
+
+	Offset(0x400),
+	GVD1,   0xC000,			// 6K bytes maximum VBT image
+
+	// OpRegion Mailbox 5 (BIOS to Driver Notification Extension)
+
+	Offset(0x1C00),
+	PHED,   32,			// Panel Header
+	BDDC,   2048,			// Panel EDID (Max 256 bytes)      
+
+}
+
+//  Define an OperationRegion to cover the ICH TCO I/O space region for use in
+//  clearing the MCH SCI status bit.
+
+/* Defined already by main ASL code, but shown below for reference.
+
+OperationRegion(TCOI,SystemIO,0x1060,0x8)
+Field(TCOI,WordAcc, NoLock, Preserve)
+{
+	Offset(0x04),			// TCO status register
+	    ,	9,
+	SCIS,	1,			// TCO DMI SCI status
+	    ,	6,
+}*/
+
+// Convert boot display type into a port mask.
+
+Name (DBTB, Package()
+{
+	0x0000,				// Automatic
+	0x0007,				// Port-0 : Integrated CRT
+	0x0038,				// Port-1 : DVO-A, or Integrated LVDS
+	0x01C0,				// Port-2 : SDVO-B, or SDVO-B/C
+	0x0E00,				// Port-3 : SDVO-C
+	0x003F,				// [CRT + DVO-A / Integrated LVDS]
+	0x01C7,				// [CRT + SDVO-B] or [CRT + SDVO-B/C]
+	0x0E07,				// [CRT + SDVO-C]
+	0x01F8,				// [DVO-A / Integrated LVDS + SDVO-B]
+	0x0E38,				// [DVO-A / Integrated LVDS + SDVO-C]
+	0x0FC0,				// [SDVO-B + SDVO-C]
+	0x0000,				// Reserved
+	0x0000,				// Reserved
+	0x0000,				// Reserved
+	0x0000,				// Reserved
+	0x0000,				// Reserved
+	0x7000,				// Port-4: Integrated TV
+	0x7007,				// [Integrated TV + CRT]
+	0x7038,				// [Integrated TV + LVDS]
+	0x71C0,				// [Integrated TV + DVOB]
+	0x7E00				// [Integrated TV + DVOC]
+})
+
+// Core display clock value table.
+
+Name (CDCT, Package()
+{
+	Package() {228, 320},
+	Package() {222, 333},
+	Package() {222, 333},
+	Package() {  0,   0},
+	Package() {222, 333},
+})
+
+// Defined exit result values:
+
+Name (SUCC, 1)				// Exit result: Success
+Name (NVLD, 2)				// Exit result: Invalid parameter
+Name (CRIT, 4)				// Exit result: Critical failure
+Name (NCRT, 6)				// Exit result: Non-critical failure
+
+
+/************************************************************************;
+;*
+;* Name: GSCI
+;*
+;* Description:	Handles an SCI generated by the graphics driver.  The
+;*		PARM and SCIC input fields are parsed to determine the
+;*		functionality requested by the driver.  GBDA or SBCB
+;*		is called based on the input data in SCIC.
+;*
+;* Usage:	The method must be called in response to a GPE 06 event
+;*		which will be generated by the graphics driver.
+;*		Ex: Method(\_GPE._L06) {Return(\_SB.PCI0.GFX0.GSCI())}
+;*
+;* Input:	PARM and SCIC are indirect inputs
+;*
+;* Output:	PARM and SIC are indirect outputs
+;*
+;* References:	GBDA (Get BIOS Data method), SBCB (System BIOS Callback
+;*		method)
+;*
+;************************************************************************/
+
+Method (GSCI, 0, Serialized)
+{
+	Include("IgdOGbda.asl")	// "Get BIOS Data" Functions
+	Include("IgdOSbcb.asl")	// "System BIOS CallBacks"
+
+	If (LEqual(GEFC, 4))
+	{
+		Store(GBDA(), GXFC)	// Process Get BIOS Data functions
+	}
+
+	If (LEqual(GEFC, 6))
+	{
+		Store(SBCB(), GXFC)	// Process BIOS Callback functions
+	}
+
+	Store(0, GEFC)			// Wipe out the entry function code
+	Store(1, SCIS)			// Clear the MCH SCI status bit in ICH TCO I/O space.
+	Store(0, GSSE)			// Clear the SCI generation bit in PCI space.
+	Store(0, SCIE)			// Clr SCI serviced bit to signal completion
+	
+	Return(Zero)
+}
+
+// Include MOBLFEAT.ASL for mobile systems only.  Remove for desktop.
+
+Include("IgdOMobF.asl")		// IGD SCI mobile features
+
diff --git a/ReferenceCode/Chipset/SystemAgent/AcpiTables/SaSsdt/Sa.asl b/ReferenceCode/Chipset/SystemAgent/AcpiTables/SaSsdt/Sa.asl
new file mode 100644
index 0000000..a8f4ee0
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/AcpiTables/SaSsdt/Sa.asl
@@ -0,0 +1,495 @@
+/*++
+  This file contains an 'Intel Peripheral Driver' and uniquely  
+  identified as "Intel Reference Module" and is                 
+  licensed for Intel CPUs and chipsets under the terms of your  
+  license agreement with Intel or your vendor.  This file may   
+  be modified by the user, subject to additional terms of the   
+  license agreement                                             
+--*/
+
+/*++
+
+Copyright (c)  1999 - 2013 Intel Corporation. All rights reserved
+This software and associated documentation (if any) is furnished
+under a license and may only be used or copied in accordance
+with the terms of the license. Except as permitted by such
+license, no part of this software or documentation may be
+reproduced, stored in a retrieval system, or transmitted in any
+form or by any means without the express written consent of
+Intel Corporation.
+
+
+Module Name:
+
+  Sa.ASL
+
+Abstract:
+
+  Devices definition of SystemAgent ACPI reference code.
+
+--*/
+//AMI_OVERRIDE -->>
+#if !defined(ASL_Remove_SaSsdt_Data_To_Dsdt) || (ASL_Remove_SaSsdt_Data_To_Dsdt == 0)
+#if defined(ASL_RC_PEG_0) && (ASL_RC_PEG_0 == 1)
+External(AR02)
+External(PR02)
+#endif
+#if defined(ASL_RC_PEG_1) && (ASL_RC_PEG_1 == 1)
+External(AR0A)
+External(PR0A)
+#endif
+#if defined(ASL_RC_PEG_2) && (ASL_RC_PEG_2 == 1)
+External(AR0B)
+External(PR0B)
+#endif
+External(PICM)
+External(\GPRW, MethodObj)
+External(\_SB.PCI0, DeviceObj)
+#endif
+//AMI_OVERRIDE --<<
+
+Scope (\_SB.PCI0) {
+    Name(LTRS, 0)
+    Name(OBFS, 0)
+//AMI_OVERRIDE -->>
+#if defined(ASL_RC_PEG_0) && (ASL_RC_PEG_0 == 1)
+    Device(PEG0) { // P.E.G. Root Port D1F0
+      Name(_ADR, 0x00010000)
+      OperationRegion(PEGR,PCI_Config,0xC0,0x30)
+      Field(PEGR,DWordAcc,NoLock,Preserve)
+      {
+        ,16,
+        PSTS, 1,     // PME Status
+        offset (44),
+        GENG, 1,     // General Message GPE Enable
+        ,1,          // Reserved
+        PMEG, 1,     // PME GPE Enable
+      }
+      Method(_PRW, 0) { Return(GPRW(0x09, 4)) } // can wakeup from S4 state
+
+      Method(_PSW,1)
+      {
+        If(Arg0)
+        {
+          Store(1,GENG)
+          Store(1,PMEG)
+        }
+        Else
+        {
+          Store(0,GENG)
+          Store(0,PMEG)
+        }
+      }
+      Method(HPME,0,Serialized)
+      {
+        //
+        // Clear PME status bit
+        //
+        Store(1,PSTS)
+      }
+      Method(_PRT,0) {
+        If(PICM) { Return(AR02) }// APIC mode
+        Return (PR02) // PIC Mode
+      } // end _PRT
+      //
+      // Pass LTRx to LTRS so SaPcieDsm.asl can be reused for PEGs.
+      //
+      Method(_INI)
+      {
+        Store (LTRA, LTRS)
+        Store (OBFA, OBFS)
+      }
+      include("SaPcieDsm.ASL")
+
+      Device(PEGP) { // P.E.G. Port Slot x16
+        Name(_ADR, 0x00000000)
+        Method(_PRW, 0) { Return(GPRW(0x09, 4)) } // can wakeup from S4 state
+      } // end "P.E.G. Port Slot x16"
+
+    } // end "P.E.G. Root Port D1F0"
+#endif
+#if defined(ASL_RC_PEG_1) && (ASL_RC_PEG_1 == 1)
+    Device(PEG1) { // P.E.G. Root Port D1F1
+      Name(_ADR, 0x00010001)
+      OperationRegion(PEGR,PCI_Config,0xC0,0x30)
+      Field(PEGR,DWordAcc,NoLock,Preserve)
+      {
+        ,16,
+        PSTS, 1,     // PME Status
+        offset (44),
+        GENG, 1,     // General Message GPE Enable
+        ,1,          // Reserved
+        PMEG, 1,     // PME GPE Enable
+      }
+      Method(_PRW, 0) { Return(GPRW(0x09, 4)) } // can wakeup from S4 state
+
+      Method(_PSW,1)
+      {
+        If(Arg0)
+        {
+          Store(1,GENG)
+          Store(1,PMEG)
+        }
+        Else
+        {
+          Store(0,GENG)
+          Store(0,PMEG)
+        }
+      }
+      Method(HPME,0,Serialized)
+      {
+        //
+        // Clear PME status bit
+        //
+        Store(1,PSTS)
+      }
+      Method(_PRT,0) {
+        If(PICM) { Return(AR0A) }// APIC mode
+        Return (PR0A) // PIC Mode
+      } // end _PRT
+
+      Method(_INI)
+      {
+        Store (LTRB, LTRS)
+        Store (OBFB, OBFS)
+      }
+      include("SaPcieDsm.ASL")
+    } // end "P.E.G. Root Port D1F1"
+#endif
+#if defined(ASL_RC_PEG_2) && (ASL_RC_PEG_2 == 1)
+    Device(PEG2) { // P.E.G. Root Port D1F2
+      Name(_ADR, 0x00010002)
+      OperationRegion(PEGR,PCI_Config,0xC0,0x30)
+      Field(PEGR,DWordAcc,NoLock,Preserve)
+      {
+        ,16,
+        PSTS, 1,     // PME Status
+        offset (44),
+        GENG, 1,     // General Message GPE Enable
+        ,1,          // Reserved
+        PMEG, 1,     // PME GPE Enable
+      }
+      Method(_PRW, 0) { Return(GPRW(0x09, 4)) } // can wakeup from S4 state
+
+      Method(_PSW,1)
+      {
+        If(Arg0)
+        {
+          Store(1,GENG)
+          Store(1,PMEG)
+        }
+        Else
+        {
+          Store(0,GENG)
+          Store(0,PMEG)
+        }
+      }
+      Method(HPME,0,Serialized)
+      {
+        //
+        // Clear PME status bit
+        //
+        Store(1,PSTS)
+      }
+      Method(_PRT,0) {
+        If(PICM) { Return(AR0B) }// APIC mode
+        Return (PR0B) // PIC Mode
+      } // end _PRT
+
+      Method(_INI)
+      {
+        Store (LTRC, LTRS)
+        Store (OBFC, OBFS)
+      }
+      include("SaPcieDsm.ASL")
+    } // end "P.E.G. Root Port D1F2"
+#endif
+//AMI_OVERRIDE --<<
+    Device(B0D3) { // SA Audio Device
+      Name(_ADR, 0x00030000)
+      Name (BARA, 0x80000000)
+      Name (TBAR, 0x0)
+      Name (TCMD, 0x0)
+      Name (MODB, 0x0)
+      Name (MODC, 0x0)
+
+      Method(_STA,0)
+      {
+        If(LNotEqual(AUVD, 0xFFFF))
+        {
+          Return(0xF) // then enabled
+        }
+        Return(0) // then disabled
+      }
+      
+      Method(_INI) {
+        //
+        // Save a valid Audio BAR for the ABWA W/A
+        //
+        If (LAnd (LNotEqual (And(ABAR, 0xFFFFC004), 0xFFFFC004), LNotEqual (And (ABAR, 0xFFFFC000), 0))) {
+          Store (ABAR, BARA)
+        }
+      }
+
+      OperationRegion(RPCS,SystemMemory,\XBAS,0x18040)
+      Field(RPCS,AnyAcc,NoLock,Preserve)
+      {
+          Offset (0x18004),
+          ACMD, 8,
+          Offset (0x18010),
+          ABAR,   32,
+      }
+      
+      OperationRegion(RPCZ,PCI_Config,0x00,0x40)
+      Field(RPCZ,DWordAcc,Lock,Preserve)
+      {
+          AUVD,   16,
+      }
+      
+      ///
+      /// Restore Audio WAs
+      ///     
+      Method (ASTR, 0, Serialized) {
+      
+        If (LAnd (LNotEqual (And(ABAR, 0xFFFFC004), 0xFFFFC004), LNotEqual (And (ABAR, 0xFFFFC000), 0))) { 
+          And (ABAR, 0xFFFFFFF0, BBAR)
+          Add (BBAR, 0x1000, BBAR)
+          OperationRegion(RPCY,SystemMemory,BBAR, 0x25)
+          Field(RPCY,DWordAcc,NoLock,Preserve)
+          {
+             Offset(0xC),
+             EM4W,  32,
+             Offset(0x10),
+             EMWA,  32,
+             Offset(0x1C),
+             ADWA,   32,
+          }
+ 
+          Store(AUDA, EMWA)
+          Store(AUDB, ADWA)
+          Store(AUDC, EM4W)
+        }
+ 
+     }
+	 
+     ///
+     /// Send the command to the codec via the Immediate Command
+     ///					
+     Method (VSTR, 1, Serialized) {
+      
+       Name (CONT, 1000)
+       Name (ADDR, 0x80000000)
+    
+       Store (Arg0, ADDR)
+       OperationRegion(CCDC,SystemMemory,ADDR,4)
+        Field(CCDC,ByteAcc,NoLock,Preserve)
+        {
+          Offset(0x0),
+          CDEC,  32,
+        }
+           
+        If (LAnd (LNotEqual (And(ABAR, 0xFFFFC004), 0xFFFFC004), LNotEqual (And (ABAR, 0xFFFFC000), 0))) {
+          If (LNotEqual (CDEC, 0)) { 
+            And (ABAR, 0xFFFFFFF0, BBAR)
+
+            OperationRegion(IPCV,SystemMemory,BBAR,0x70)
+            Field(IPCV,DWordAcc,NoLock,Preserve)
+            {
+              Offset(0x60),
+              AVIC,  32,
+              Offset(0x68),
+              AIRS,  16,
+            }
+          
+            Store (1000, CONT)
+            While (LAnd (LEqual(And(AIRS, 0x1), 1), LNotEqual(CONT,0))) 
+            { 
+              Stall(1)
+              Decrement(CONT)
+            }
+            Or (AIRS, 2, AIRS)
+            Store (CDEC, AVIC)
+            Or (AIRS, 1, AIRS)
+         
+            Store (1000, CONT)
+            While (LAnd (LEqual(And(AIRS, 0x1), 1), LNotEqual(CONT,0))) 
+            { 
+              Stall(1)
+              Decrement(CONT)
+            }
+          }
+        }
+      }
+      
+      ///
+      /// Restore Verb Table
+      ///
+      Method (CXDC, 0, Serialized)
+      {
+        Name(IDDX, 0x80000000)
+//AMI_OVERRIDE --- Change name from CADR to CCSA to fix that the system has BsOD issue. It is due to the name(CADR) is conflict with AMI Aptio definition name. >>
+       If (LAnd (LNotEqual (CCSA, 0), LNotEqual (CCNT, 0))) {            
+          Store (CCSA, IDDX)
+          While (LLess (IDDX, Add (CCSA, Multiply (CCNT, 4)))) 
+//     If (LAnd (LNotEqual (CADR, 0), LNotEqual (CCNT, 0))) {            
+//        Store (CADR, IDDX)
+//        While (LLess (IDDX, Add (CADR, Multiply (CCNT, 4)))) 
+//AMI_OVERRIDE --- <<
+          {
+            VSTR (IDDX)
+            Add (IDDX, 4, IDDX)
+          }
+        }
+      }
+      
+      ///
+      /// Reset Audio Controller
+      ///
+      Method (ARST, 0, Serialized)
+      {
+        If (LAnd (LNotEqual (And(ABAR, 0xFFFFC004), 0xFFFFC004), LNotEqual (And (ABAR, 0xFFFFC000), 0))) { 
+          And (ABAR, 0xFFFFFFF0, BBAR)
+          OperationRegion(IPCV,SystemMemory,BBAR,0xBF)
+          Field(IPCV,AnyAcc,NoLock,Preserve)
+          {
+              Offset(0x08),
+              CRST, 32,
+              Offset(0x4C),
+              CORB, 32,
+              Offset(0x5C),
+              RIRB, 32,
+              Offset(0x80),
+              OSD1, 32,
+              Offset(0xA0),
+              OSD2, 32,
+          }
+          AND (CORB, 0xFFFFFFFD, CORB)
+          AND (RIRB, 0xFFFFFFFD, RIRB)
+          AND (OSD1, 0xFFFFFFFD, OSD1)
+          AND (OSD2, 0xFFFFFFFD, OSD2)
+          AND (CRST, 0xFFFFFFFE, CRST)
+        }
+      }
+
+      ///
+      /// Codec Initialization Programming Sequence
+      ///
+      Method (AINI, 0, Serialized)
+      {
+        Name (CONT, 1000)
+           
+        If (LAnd (LNotEqual (And(ABAR, 0xFFFFC004), 0xFFFFC004), LNotEqual (And (ABAR, 0xFFFFC000), 0))) { 
+          And (ABAR, 0xFFFFFFF0, BBAR)
+
+          OperationRegion(IPCV,SystemMemory,BBAR,0x70)
+          Field(IPCV,DWordAcc,NoLock,Preserve)
+          {
+              Offset(0x0),
+              GCAP, 16,
+              Offset(0x08),
+              GCTL,  32,
+              Offset(0x0E),
+              SSTS,  8,
+              Offset(0x60),
+              AVIC,  32,
+              Offset(0x68),
+              AIRS,  16,
+          }
+
+          ///
+          /// Step1/2:Reset Controller and wait for reset complete
+          ///
+          Or (GCTL, 1, GCTL)
+          Store (1000, CONT)
+          While (LAnd (LEqual (And (GCTL , 1), 0), LNotEqual (CONT, 0))) 
+          { 
+              Stall (1)
+              Decrement (CONT)
+          }
+          
+          ///
+          /// Step3: 
+          /// Read GCAP and write the same value back to
+          /// the register once after Controller Reset# bit is set
+          ///
+          And (GCAP, 0xFFFF, GCAP)
+			
+          ///
+          /// Step4:
+          /// Clear the "State Change Status Register" STATESTS bits for
+          /// each of the "SDIN Stat Change Status Flag"
+          ///
+          Or (SSTS, 0xF, SSTS)
+
+          ///
+          /// Step5:
+          /// Turn off the link and poll RESET# bit until it reads back 
+          /// as 0 to get hardware reset report
+          ///
+          And (GCTL, 0xFFFFFFFE, GCTL)
+
+          Store (1000, CONT)
+          While (LAnd (LEqual(And(GCTL,1), 1), LNotEqual(CONT,0))) 
+          { 
+              Stall (1)
+              Decrement (CONT)
+          }
+
+          ///
+          /// Step6:
+          /// Turn on the link and poll RESET# bit until it reads back as 1
+          ///
+          Or (GCTL, 1, GCTL)
+          Store (1000, CONT)
+          While (LAnd (LEqual(And(GCTL,1), 0), LNotEqual(CONT,0))) 
+          { 
+              Stall (1)
+              Decrement (CONT)
+          }
+        }
+      }
+      ///
+      /// W/A for Audio CdClk restore issue with HDMI hotplug after S3/S4 resume
+      /// Store ABAR temporarily and restore it at the end of Call Back SF 21h
+      ///
+      Method (ABWA, 1, Serialized)
+      {
+        If (Arg0) {
+          If (LOr (LEqual (And(ABAR, 0xFFFFC004), 0xFFFFC004), LEqual (And (ABAR, 0xFFFFC000), 0))) {
+            ///
+            /// if Audio BAR does not have a valid value
+            ///
+            If (LNotEqual (BARA, 0x80000000)) {       // but a vaid value has been saved by the _INI or _WAK earlier
+              Store (ABAR, TBAR)                      // temporarily assign Audio Bar to restore mmio registers
+              Store (ACMD, TCMD)
+              Store (BARA, ABAR)
+              Store (0x06, ACMD)
+              Store (0x01, MODB)
+            }
+          } Else {                                    // Audio BAR has a valid value
+            If (LNotEqual (And (ACMD, 0x06), 0x06)) { // but CMD register is not set to allow writes to mmio registers
+              Store (ACMD, TCMD)                      // temporarily set CMD register to allow mmio writes
+              Store (0x06, ACMD)
+              Store (0x01, MODC)
+            }
+          }
+        } Else {                                      // Restore the original Audio Bar and Cmd Register
+          If (MODB) {
+            If(LEqual(ABAR, BARA)) {
+              Store (TBAR, ABAR)
+              Store (TCMD, ACMD)
+            }
+          }
+          If (MODC) {                                 // Restore only the Cmd Register
+            Store (TCMD, ACMD)
+          }
+        }
+      }
+    } // end "SA Audio Device"
+
+    Device(GFX0) { // I.G.D
+      Name(_ADR, 0x00020000)
+      include("IntelGfx.ASL")
+    } // end I.G.D
+
+}
diff --git a/ReferenceCode/Chipset/SystemAgent/AcpiTables/SaSsdt/SaPcieDsm.asl b/ReferenceCode/Chipset/SystemAgent/AcpiTables/SaSsdt/SaPcieDsm.asl
new file mode 100644
index 0000000..613138c
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/AcpiTables/SaSsdt/SaPcieDsm.asl
@@ -0,0 +1,119 @@
+/**************************************************************************;
+;*                                                                        *;
+;*    Intel Confidential                                                  *;
+;*                                                                        *;
+;*    Intel Corporation - ACPI Reference Code for the Haswell             *;
+;*    Family of Customer Reference Boards.                                *;
+;*                                                                        *;
+;*                                                                        *;
+;*    Copyright (c)  1999 - 2012 Intel Corporation. All rights reserved   *;
+;*    This software and associated documentation (if any) is furnished    *;
+;*    under a license and may only be used or copied in accordance        *;
+;*    with the terms of the license. Except as permitted by such          *;
+;*    license, no part of this software or documentation may be           *;
+;*    reproduced, stored in a retrieval system, or transmitted in any     *;
+;*    form or by any means without the express written consent of         *;
+;*    Intel Corporation.                                                  *;
+;*                                                                        *;
+;*                                                                        *;
+;**************************************************************************/
+/*++
+  This file contains an 'Intel Peripheral Driver' and is
+  licensed for Intel CPUs and chipsets under the terms of your  
+  license agreement with Intel or your vendor.  This file may   
+  be modified by the user, subject to additional terms of the   
+  license agreement                                             
+--*/   
+
+  Name(LTRV, Package(){0,0,0,0})
+  Name(OPTS, 0) // SA SETUP options for LTR and OBFF
+
+  //
+  // _DSM Device Specific Method
+  //
+  // Arg0: UUID Unique function identifier
+  // Arg1: Integer Revision Level
+  // Arg2: Integer Function Index (0 = Return Supported Functions)
+  // Arg3: Package Parameters
+  Method(_DSM, 4, Serialized) {
+    //
+    // Switch based on which unique function identifier was passed in
+    //
+    Switch(ToInteger(Arg0)) {
+      //
+      // _DSM Definitions for Latency Tolerance Reporting
+      //
+      // Arguments:
+      // Arg0: UUID: E5C937D0-3553-4d7a-9117-EA4D19C3434D
+      // Arg1: Revision ID: 2
+      // Arg2: Function Index: 6
+      // Arg3: Empty Package
+      //
+      // Return:
+      // A Package of four integers corresponding with the LTR encoding defined
+      // in the PCI Express Base Specification, as follows:
+      // Integer 0: Maximum Snoop Latency Scale
+      // Integer 1: Maximum Snoop Latency Value
+      // Integer 2: Maximum No-Snoop Latency Scale
+      // Integer 3: Maximum No-Snoop Latency Value
+      // These values correspond directly to the LTR Extended Capability Structure
+      // fields described in the PCI Express Base Specification.
+      //
+      Case(ToUUID("E5C937D0-3553-4d7a-9117-EA4D19C3434D")) {
+        //
+        // Switch by function index
+        //
+        Switch(ToInteger(Arg2)) {
+          //
+          // Function Index:0
+          // Standard query - A bitmask of functions supported
+          //
+          Case (0)
+          {
+            if (LEqual(Arg1, 2)){ // test Arg1 for Revision ID: 2
+              Store(1, OPTS) // function 0
+              if (LTRS){
+                Or(OPTS,0x40,OPTS) // function 6
+              }
+              if (OBFS){
+                Or(OPTS,0x10,OPTS) // function 4
+              }
+              Return (OPTS) // bitmask of supported functions: 6, 4, 0.
+            } else {
+              Return (0)
+            }
+          }
+          //
+          // Function Index: 4
+          //
+          Case(4) {
+            if (LEqual(Arg1, 2)){ // test Arg1 for Revision ID: 2
+              if (OBFS){
+                Return (Buffer () {0,0,0,0,0,0,0,0,0,0,0,8,0,0,0,0}) // OBFF capable, offset 4[08h]
+              } else {
+                Return (Buffer () {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0})
+              }
+            }
+          }
+          //
+          // Function Index: 6
+          // LTR Extended Capability Structure
+          //
+          Case(6) {
+            if (LEqual(Arg1, 2)){ // test Arg1 for Revision ID: 2
+              if (LTRS){
+                Store(And(ShiftRight(SMSL,10),7), Index(LTRV, 0))
+                Store(And(SMSL,0x3FF), Index(LTRV, 1))
+                Store(And(ShiftRight(SNSL,10),7), Index(LTRV, 2))
+                Store(And(SNSL,0x3FF), Index(LTRV, 3))
+                return (LTRV)
+              } else {
+                Return (0)
+              }
+            }
+          }
+        } // End of switch(Arg2)
+      } // End of case(ToUUID("E5C937D0-3553-4d7a-9117-EA4D19C3434D"))
+    } // End of switch(Arg0)
+    return (Buffer() {0x00})
+  } // End of _DSM
diff --git a/ReferenceCode/Chipset/SystemAgent/AcpiTables/SaSsdt/SaSsdt.asl b/ReferenceCode/Chipset/SystemAgent/AcpiTables/SaSsdt/SaSsdt.asl
new file mode 100644
index 0000000..0650178
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/AcpiTables/SaSsdt/SaSsdt.asl
@@ -0,0 +1,172 @@
+/*++
+  This file contains an 'Intel Peripheral Driver' and uniquely  
+  identified as "Intel Reference Module" and is                 
+  licensed for Intel CPUs and chipsets under the terms of your  
+  license agreement with Intel or your vendor.  This file may   
+  be modified by the user, subject to additional terms of the   
+  license agreement                                             
+--*/
+
+/*++
+
+Copyright (c)  2012 - 2013 Intel Corporation. All rights reserved
+This software and associated documentation (if any) is furnished
+under a license and may only be used or copied in accordance
+with the terms of the license. Except as permitted by such
+license, no part of this software or documentation may be
+reproduced, stored in a retrieval system, or transmitted in any
+form or by any means without the express written consent of
+Intel Corporation.
+
+Module Name:
+
+  SaSsdt.asl
+
+Abstract:
+
+  SA SSDT Table ASL code
+
+--*/
+
+
+DefinitionBlock (
+  "SaSsdt.aml",
+  "SSDT",
+  0x01,
+  "SaSsdt",
+  "SaSsdt ",
+  0x3000
+  )
+{
+
+  OperationRegion(SANV,SystemMemory,0xFFFF0000,0xAA55)
+  Field(SANV,AnyAcc,Lock,Preserve)
+  {
+  SARV, 32,     /// (000) SA RC Revision
+  ASLB, 32,     /// (004) IGD OpRegion base address
+  IMON, 8,      /// (008) IMON Current Value
+  IGDS, 8,      /// (009) IGD State (Primary Display = 1)
+  CADL, 8,      /// (010) Current Attached Device List
+  PADL, 8,      /// (011) Previous Attached Device List
+  CSTE, 16,     /// (012) Current Display State
+  NSTE, 16,     /// (014) Next Display State
+  DID9, 32,     /// (016) Device Id 9
+  DIDA, 32,     /// (020) Device Id 10
+  DIDB, 32,     /// (024) Device Id 11
+  IBTT, 8,      /// (028) IGD Boot Display Device
+  IPAT, 8,      /// (029) IGD Panel Type CMOs option
+  IPSC, 8,      /// (030) IGD Panel Scaling
+  IBLC, 8,      /// (031) IGD BLC Configuration
+  IBIA, 8,      /// (032) IGD BIA Configuration
+  ISSC, 8,      /// (033) IGD SSC Configuration
+  IPCF, 8,      /// (034) IGD Power Conservation Feature Flag
+  IDMS, 8,      /// (035) IGD DVMT Memory Size
+  IF1E, 8,      /// (036) IGD Function 1 Enable
+  HVCO, 8,      /// (037) HPLL VCO
+  NXD1, 32,     /// (038) Next state DID1 for _DGS
+  NXD2, 32,     /// (042) Next state DID2 for _DGS
+  NXD3, 32,     /// (046) Next state DID3 for _DGS
+  NXD4, 32,     /// (050) Next state DID4 for _DGS
+  NXD5, 32,     /// (054) Next state DID5 for _DGS
+  NXD6, 32,     /// (058) Next state DID6 for _DGS
+  NXD7, 32,     /// (062) Next state DID7 for _DGS
+  NXD8, 32,     /// (066) Next state DID8 for _DGS
+  GSMI, 8,      /// (070) GMCH SMI/SCI mode (0=SCI)
+  PAVP, 8,      /// (071) IGD PAVP data
+  LIDS, 8,      /// (072) Lid State (Lid Open = 1)
+  KSV0, 32,     /// (073) First four bytes of AKSV (mannufacturing mode)
+  KSV1, 8,      /// (077) Fifth byte of AKSV (mannufacturing mode)
+  BBAR, 32,     /// (078) IGFX Audio (D3F0) MMIO BAR Address
+  BLCS, 8,      /// (082) Backlight Control Support
+  BRTL, 8,      /// (083) Brightness Level Percentage
+  ALSE, 8,      /// (084) ALS Enable
+  ALAF, 8,      /// (085) Ambient Light Adjusment Factor
+  LLOW, 8,      /// (086) LUX Low Value
+  LHIH, 8,      /// (087) LUX High Value
+  ALFP, 8,      /// (088) Active LFP
+  AUDA, 32,     /// (089) Audio MMIO WA 1
+  AUDB, 32,     /// (093) Audio MMIO WA 2
+  AUDC, 32,     /// (097) Audio MMIO WA 3 
+  DIDC, 32,	/// (101) Device Id 12
+  DIDD, 32,	/// (105) Device Id 13
+  DIDE, 32,	/// (109) Device Id 14
+  DIDF, 32,	/// (113) Device Id 15
+//AMI_OVERRIDE --- Change name from CADR to CCSA to fix that the system has BsOD issue. It is due to the name(CADR) is conflict with AMI Aptio definition name. >>
+  CCSA, 32,     /// (117) Codec Save Address 
+  CCNT, 32,     /// (121) Codec Save Count 
+//CADR, 32,     /// (117) Codec Save Address 
+//CCNT, 8,      /// (121) Codec Save Count 
+//AMI_OVERRIDE --- <<
+  ///
+  /// Switchable Graphics Info
+  ///
+  Offset(200),
+  SGMD, 8,      /// (200) SG Mode (0=Disabled, 1=SG Muxed, 2=SG Muxless, 3=DGPU Only)
+  SGFL, 8,      /// (201) SG Feature List
+  PWOK, 8,      /// (202) dGPU PWROK GPIO assigned
+  HLRS, 8,      /// (203) dGPU HLD RST GPIO assigned
+  PWEN, 8,      /// (204) dGPU PWR Enable GPIO assigned
+  PRST, 8,      /// (205) dGPU Present Detect GPIO assigned
+  CPSP, 32,     /// (206) PEG Endpoint Capability Structure Presence (Bit 0: Virtual Channel Capability)
+  EECP, 8,      /// (210) PEG Endpoint PCIe Capability Structure Offset
+  EVCP, 16,     /// (211) PEG Endpoint Virtual Channel Capability Structure Offset
+  XBAS, 32,     /// (213) Any Device's PCIe Config Space Base Address
+  GBAS, 16,     /// (217) GPIO Base Address
+  SGGP, 8,      /// (219) SG GPIO Support
+  NVGA, 32,     /// (220) NVIG opregion address
+  NVHA, 32,     /// (224) NVHM opregion address
+  AMDA, 32,     /// (228) AMDA opregion address
+  NDID, 8,      /// (232) Number of Valid Device IDs
+  DID1, 32,     /// (233) Device ID 1
+  DID2, 32,     /// (237) Device ID 2
+  DID3, 32,     /// (241) Device ID 3
+  DID4, 32,     /// (245) Device ID 4
+  DID5, 32,     /// (249) Device ID 5
+  DID6, 32,     /// (253) Device ID 6
+  DID7, 32,     /// (257) Device ID 7
+  DID8, 32,     /// (261) Device ID 8
+  OBS1, 32,     /// (265) Occupied Buses - from 0 to 31
+  OBS2, 32,     /// (269) Occupied Buses - from 32 to 63
+  OBS3, 32,     /// (273) Occupied Buses - from 64 to 95
+  OBS4, 32,     /// (277) Occupied Buses - from 96 to 127
+  OBS5, 32,     /// (281) Occupied Buses - from 128 to 159
+  OBS6, 32,     /// (285) Occupied Buses - from 160 to 191
+  OBS7, 32,     /// (289) Occupied Buses - from 192 to 223
+  OBS8, 32,     /// (293) Occupied Buses - from 224 to 255
+  LTRA, 8,      /// (297) Latency Tolerance Reporting Enable
+  OBFA, 8,      /// (298) Optimized Buffer Flush and Fill
+  LTRB, 8,      /// (299) Latency Tolerance Reporting Enable
+  OBFB, 8,      /// (300) Optimized Buffer Flush and Fill
+  LTRC, 8,      /// (301) Latency Tolerance Reporting Enable
+  OBFC, 8,      /// (302) Optimized Buffer Flush and Fill
+  SMSL, 16,     /// (303) SA Peg Latency Tolerance Reporting Max Snoop Latency
+  SNSL, 16,     /// (305) SA Peg Latency Tolerance Reporting Max No Snoop Latency
+  P0UB, 8,      /// (307) Peg0 Unused Bundle Control
+  P1UB, 8,      /// (308) Peg1 Unused Bundle Control
+  P2UB, 8,      /// (309) Peg2 Unused Bundle Control
+  EDPV, 8,      /// (310) Check for eDP display device
+  NXDX, 32,     /// (311) Next state DID for eDP
+  DIDX, 32,     /// (315) Device ID for eDP device
+  PCSL, 8,      /// (319) The lowest C-state for the package
+  SC7A, 8,      /// (316) Run-time C7 Allowed feature (0=Disabled, 1=Enabled)
+// AMI_OVERRIDE...
+  DSEL, 8,      /// (319) dGPU Display Select GPIO assigned
+  ESEL, 8,      /// (320) dGPU EDID Select GPIO assigned
+  PSEL, 8,      /// (321) dGPU PWM Select GPIO assigned
+  MXD1, 32,     /// (322) DID1 Mux Setting
+  MXD2, 32,     /// (326) DID2 Mux Setting
+  MXD3, 32,     /// (330) DID3 Mux Setting
+  MXD4, 32,     /// (334) DID4 Mux Setting
+  MXD5, 32,     /// (338) DID5 Mux Setting
+  MXD6, 32,     /// (342) DID6 Mux Setting
+  MXD7, 32,     /// (346) DID7 Mux Setting
+  MXD8, 32,     /// (350) DID8 Mux Setting
+  PXFD, 8,      /// (354) ATI 5.0 Fixed/Dynamic ATI 5.0 Fixed/Dynamic
+  EBAS, 32,     /// (355) Endpoint PCIe Base Address
+  HYSS, 32,     /// (359) dGPU SSID for MSHyBrid restore
+// AMI_OVERRIDE...end.
+  }
+#if !defined(ASL_Remove_SaSsdt_Data_To_Dsdt) || (ASL_Remove_SaSsdt_Data_To_Dsdt == 0)
+  include ("Sa.asl")
+#endif // AMI_OVERRIDE
+}
\ No newline at end of file
diff --git a/ReferenceCode/Chipset/SystemAgent/AcpiTables/SaSsdt/SaSsdt.inf b/ReferenceCode/Chipset/SystemAgent/AcpiTables/SaSsdt/SaSsdt.inf
new file mode 100644
index 0000000..e97e019
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/AcpiTables/SaSsdt/SaSsdt.inf
@@ -0,0 +1,69 @@
+## @file
+#  Component description file for the ACPI tables
+#
+#@copyright
+#  Copyright (c)  2012 Intel Corporation. All rights reserved
+#  This software and associated documentation (if any) is furnished
+#  under a license and may only be used or copied in accordance
+#  with the terms of the license. Except as permitted by such
+#  license, no part of this software or documentation may be
+#  reproduced, stored in a retrieval system, or transmitted in any
+#  form or by any means without the express written consent of
+#  Intel Corporation.
+#
+#  This file contains an 'Intel Peripheral Driver' and uniquely
+#  identified as "Intel Reference Module" and is
+#  licensed for Intel CPUs and chipsets under the terms of your
+#  license agreement with Intel or your vendor.  This file may
+#  be modified by the user, subject to additional terms of the
+#  license agreement
+#
+
+
+[defines]
+BASE_NAME            = SaSsdt
+FILE_GUID            = AAA99A23-13B6-4C31-BB8B-299E8EC04FA4
+COMPONENT_TYPE       = ACPITABLE
+FFS_EXT              = .ffs
+
+[sources.common]
+  SaSsdt.ASL
+
+[libraries.common]
+
+[includes.common]
+  .
+  $(EFI_SOURCE)
+  $(EFI_SOURCE)/Include
+  $(EFI_SOURCE)/$(PROJECT_SA_ROOT)/Include
+  $(EDK_SOURCE)/Foundation/Efi
+  $(EDK_SOURCE)/Foundation/Include
+  $(EDK_SOURCE)/Foundation/Efi/Include
+  $(EDK_SOURCE)/Foundation/Framework/Include
+  $(EFI_SOURCE)/Include/IndustryStandard
+  $(EDK_SOURCE)/Foundation/Include/IndustryStandard
+  $(EDK_SOURCE)/Foundation/Library/Dxe/Include
+  $(EDK_SOURCE)/Foundation
+  $(EDK_SOURCE)/Foundation/Framework
+#
+# Typically the sample code referenced will be available in the code base already
+# So keep this include at the end to defer to the source base definition
+# and only use the sample code definition if source base does not include these files.
+#
+# $(EFI_SOURCE)/$(PROJECT_SA_ROOT)/SampleCode/Include
+
+#
+# Edk II Glue Library, some hearder are included by R9 header so have to include
+#
+
+ $(EFI_SOURCE)
+ $(EFI_SOURCE)/Framework
+ $(EDK_SOURCE)/Foundation
+ $(EDK_SOURCE)/Foundation/Framework
+ $(EDK_SOURCE)/Foundation/Include/IndustryStandard
+ $(EDK_SOURCE)/Foundation/Core/Dxe
+ $(EDK_SOURCE)/Foundation/Include/Pei
+ $(EDK_SOURCE)/Foundation/Library/Dxe/Include
+ $(EDK_SOURCE)/Foundation/Library/EdkIIGlueLib/Include
+
+[nmake.common]
diff --git a/ReferenceCode/Chipset/SystemAgent/AcpiTables/SaSsdt/SaSsdtTables.cif b/ReferenceCode/Chipset/SystemAgent/AcpiTables/SaSsdt/SaSsdtTables.cif
new file mode 100644
index 0000000..ef4ae0c
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/AcpiTables/SaSsdt/SaSsdtTables.cif
@@ -0,0 +1,19 @@
+<component>
+	name = "SaSsdtTables"
+	category = ModulePart
+	LocalRoot = "ReferenceCode\Chipset\SystemAgent\AcpiTables\SaSsdt\"
+	RefName = "SaSsdtTables"
+[files]
+"IgdOGBDA.ASL"	
+"IgdOMOBF.ASL"	
+"IgdOpRn.ASL"	
+"IgdOSBCB.ASL"	
+"INTELGFX.ASL"	
+"Sa.asl"	
+"SaPcieDsm.asl"	
+"SaSsdt.asl"	
+"SaSsdt.inf"	
+"SaSsdt_Edk.inf"	
+"SaSsdtTables.mak"	
+"SaSsdtTables.sdl"	
+<endComponent>
diff --git a/ReferenceCode/Chipset/SystemAgent/AcpiTables/SaSsdt/SaSsdtTables.mak b/ReferenceCode/Chipset/SystemAgent/AcpiTables/SaSsdt/SaSsdtTables.mak
new file mode 100644
index 0000000..e44f223
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/AcpiTables/SaSsdt/SaSsdtTables.mak
@@ -0,0 +1,57 @@
+#*************************************************************************
+#*************************************************************************
+#**                                                                     **
+#**        (C)Copyright 1985-2011, American Megatrends, Inc.            **
+#**                                                                     **
+#**                       All Rights Reserved.                          **
+#**                                                                     **
+#**      5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093           **
+#**                                                                     **
+#**                       Phone: (770)-246-8600                         **
+#**                                                                     **
+#*************************************************************************
+#*************************************************************************
+
+#*************************************************************************
+#<AMI_FHDR_START>
+#
+# Name: SgAcpiTables.mak
+#
+# Description: MAK file for the ModulePart:SgAcpiTables
+# 
+#
+#<AMI_FHDR_END>
+#*************************************************************************
+all : BuildSaSsdt
+
+BuildSaSsdt : $(BUILD_DIR)\SaSsdt.ffs
+
+#-----------------------------------------------------------------------
+# ASL compiler definition
+#-----------------------------------------------------------------------
+IASL = $(SILENT)iasl4.exe 
+#-----------------------------------------------------------------------
+$(BUILD_DIR)\SaSsdt.aml : $(INTEL_SASSDT_ASL_FILE) 
+  $(CP) /FI$(BUILD_DIR)\tokenasl.h $(INTEL_IgdOGBDA_ASL_FILE) > $(BUILD_DIR)\IgdOGBDA.asl
+  $(CP) /FI$(BUILD_DIR)\tokenasl.h $(INTEL_IgdOMOBF_ASL_FILE) > $(BUILD_DIR)\IgdOMOBF.asl
+  $(CP) /FI$(BUILD_DIR)\tokenasl.h $(INTEL_IgdOPRN_ASL_FILE) > $(BUILD_DIR)\IgdOPRN.asl
+  $(CP) /FI$(BUILD_DIR)\tokenasl.h $(INTEL_IgdOSBCB_ASL_FILE) > $(BUILD_DIR)\IgdOSBCB.asl
+  $(CP) /FI$(BUILD_DIR)\tokenasl.h $(INTEL_INTELGFX_ASL_FILE) > $(BUILD_DIR)\INTELGFX.asl
+  $(CP) /FI$(BUILD_DIR)\tokenasl.h $(INTEL_SA_ASL_FILE) > $(BUILD_DIR)\SA.asl
+  $(CP) /FI$(BUILD_DIR)\tokenasl.h $(INTEL_SAPCIEDSM_ASL_FILE) > $(BUILD_DIR)\SAPCIEDSM.asl
+  $(CP) /FI$(BUILD_DIR)\tokenasl.h $(INTEL_SASSDT_ASL_FILE) > $(BUILD_DIR)\SASSDT.asl
+  $(ASLEXPANDER) $(BUILD_DIR)\SASSDT.asl $(BUILD_DIR)\SASSDT_BUILD.asl $(BUILD_DIR) 
+  $(IASL) -p $(BUILD_DIR)\SaSsdt.aml $(BUILD_DIR)\SASSDT_BUILD.asl
+
+
+$(BUILD_DIR)\SaSsdt.sec: $(BUILD_DIR)\SaSsdt.aml
+  $(GENSECTION) -I $*.aml -O $@ -S EFI_SECTION_RAW
+
+$(BUILD_DIR)\SaSsdt.ffs: $(BUILD_DIR)\SaSsdt.sec $(SaSsdtTables_DIR)\SaSsdtTables.mak
+	$(MAKE) /f Core\FFS.mak \
+		BUILD_DIR=$(BUILD_DIR) \
+        GUID=AAA99A23-13B6-4C31-BB8B-299E8EC04FA4\
+		TYPE=EFI_FV_FILETYPE_FREEFORM \
+        FFS_CHECKSUM=1\
+		RAWFILE=$(BUILD_DIR)\SaSsdt.sec FFSFILE=$(BUILD_DIR)\SaSsdt.ffs COMPRESS=0 NAME=SaSsdt
+
diff --git a/ReferenceCode/Chipset/SystemAgent/AcpiTables/SaSsdt/SaSsdtTables.sdl b/ReferenceCode/Chipset/SystemAgent/AcpiTables/SaSsdt/SaSsdtTables.sdl
new file mode 100644
index 0000000..6e0c223
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/AcpiTables/SaSsdt/SaSsdtTables.sdl
@@ -0,0 +1,104 @@
+TOKEN
+	Name  = "SaSsdtTables_SUPPORT"
+	Value  = "1"
+	TokenType = Boolean
+	TargetEQU = Yes
+	TargetMAK = Yes
+	Master = Yes
+	Help  = "Main switch to enable SaSsdtTables support in Project"
+End
+
+TOKEN
+	Name  = "Remove_SaSsdt_Data_To_Dsdt"
+	Value  = "0"
+	TokenType = Boolean
+	TargetEQU = Yes
+	TargetMAK = Yes
+        TargetH = Yes
+	Help  = "Remove related SaSsdt acpi data to DSDT"
+End
+
+ELINK
+	Name  = "/D Remove_SaSsdt_Data_To_Dsdt"
+	Parent  = "INTEL_SA_RC_FLAGS"
+	Token = "Remove_SaSsdt_Data_To_Dsdt" "=" "1"
+	InvokeOrder = AfterParent
+End
+
+MODULE
+	Help  = "Includes SgAcpiTables.mak to Project"
+	File  = "SaSsdtTables.mak"
+End
+
+PATH
+	Name  = "SaSsdtTables_DIR"
+End
+
+ELINK
+	Name  = "$(SaSsdtTables_DIR)\Sa.asl"
+	Parent  = "INTEL_GENERIC_ASL"
+	Token = "Remove_SaSsdt_Data_To_Dsdt" "=" "1"
+	InvokeOrder = AfterParent
+End
+
+TOKEN
+	Name  = "INTEL_IgdOGBDA_ASL_FILE"
+	Value  = "$(SaSsdtTables_DIR)\IgdOGBDA.asl"
+	TokenType = Expression
+	TargetMAK = Yes
+End
+
+TOKEN
+	Name  = "INTEL_IgdOMOBF_ASL_FILE"
+	Value  = "$(SaSsdtTables_DIR)\IgdOMOBF.asl"
+	TokenType = Expression
+	TargetMAK = Yes
+End
+
+TOKEN
+	Name  = "INTEL_IgdOPRN_ASL_FILE"
+	Value  = "$(SaSsdtTables_DIR)\IgdOPRN.asl"
+	TokenType = Expression
+	TargetMAK = Yes
+End
+
+TOKEN
+	Name  = "INTEL_IgdOSBCB_ASL_FILE"
+	Value  = "$(SaSsdtTables_DIR)\IgdOSBCB.asl"
+	TokenType = Expression
+	TargetMAK = Yes
+End
+
+TOKEN
+	Name  = "INTEL_INTELGFX_ASL_FILE"
+	Value  = "$(SaSsdtTables_DIR)\INTELGFX.asl"
+	TokenType = Expression
+	TargetMAK = Yes
+End
+
+TOKEN
+	Name  = "INTEL_SA_ASL_FILE"
+	Value  = "$(SaSsdtTables_DIR)\SA.asl"
+	TokenType = Expression
+	TargetMAK = Yes
+End
+
+TOKEN
+	Name  = "INTEL_SAPCIEDSM_ASL_FILE"
+	Value  = "$(SaSsdtTables_DIR)\SAPCIEDSM.asl"
+	TokenType = Expression
+	TargetMAK = Yes
+End
+
+TOKEN
+	Name  = "INTEL_SASSDT_ASL_FILE"
+	Value  = "$(SaSsdtTables_DIR)\SASSDT.asl"
+	TokenType = Expression
+	TargetMAK = Yes
+End
+
+ELINK
+	Name  = "$(BUILD_DIR)\SaSsdt.ffs"
+	Parent  = "FV_MAIN"
+	InvokeOrder = AfterParent
+End
diff --git a/ReferenceCode/Chipset/SystemAgent/AcpiTables/SaSsdt/SaSsdt_Edk.inf b/ReferenceCode/Chipset/SystemAgent/AcpiTables/SaSsdt/SaSsdt_Edk.inf
new file mode 100644
index 0000000..4ef6ff6
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/AcpiTables/SaSsdt/SaSsdt_Edk.inf
@@ -0,0 +1,76 @@
+## @file
+#  Component description file for the ACPI tables (for EDK1117)
+#
+#@copyright
+#  Copyright (c)  2012 Intel Corporation. All rights reserved
+#  This software and associated documentation (if any) is furnished
+#  under a license and may only be used or copied in accordance
+#  with the terms of the license. Except as permitted by such
+#  license, no part of this software or documentation may be
+#  reproduced, stored in a retrieval system, or transmitted in any
+#  form or by any means without the express written consent of
+#  Intel Corporation.
+#
+#  This file contains an 'Intel Peripheral Driver' and uniquely
+#  identified as "Intel Reference Module" and is
+#  licensed for Intel CPUs and chipsets under the terms of your
+#  license agreement with Intel or your vendor.  This file may
+#  be modified by the user, subject to additional terms of the
+#  license agreement
+#
+
+
+[defines]
+BASE_NAME            = SaSsdt
+FILE_GUID            = AAA99A23-13B6-4C31-BB8B-299E8EC04FA4
+COMPONENT_TYPE       = SA_SSDT_ACPITABLE
+FFS_EXT              = .ffs
+
+[sources.common]
+  SaSsdt.ASL
+  Sa.asl
+  IntelGfx.asl
+  IgdOpRn.asl
+  IgdOGBDA.asl
+  IgdOMOBF.asl
+  IgdOSBCB.asl
+  SaPcieDsm.asl
+  
+[libraries.common]
+
+[includes.common]
+  .
+  $(EFI_SOURCE)
+  $(EFI_SOURCE)/Include
+  $(EFI_SOURCE)/$(PROJECT_SA_ROOT)/Include
+  $(EDK_SOURCE)/Foundation/Efi
+  $(EDK_SOURCE)/Foundation/Include
+  $(EDK_SOURCE)/Foundation/Efi/Include
+  $(EDK_SOURCE)/Foundation/Framework/Include
+  $(EFI_SOURCE)/Include/IndustryStandard
+  $(EDK_SOURCE)/Foundation/Include/IndustryStandard
+  $(EDK_SOURCE)/Foundation/Library/Dxe/Include
+  $(EDK_SOURCE)/Foundation
+  $(EDK_SOURCE)/Foundation/Framework
+#
+# Typically the sample code referenced will be available in the code base already
+# So keep this include at the end to defer to the source base definition
+# and only use the sample code definition if source base does not include these files.
+#
+# $(EFI_SOURCE)/$(PROJECT_SA_ROOT)/SampleCode/Include
+
+#
+# Edk II Glue Library, some hearder are included by R9 header so have to include
+#
+
+ $(EFI_SOURCE)
+ $(EFI_SOURCE)/Framework
+ $(EDK_SOURCE)/Foundation
+ $(EDK_SOURCE)/Foundation/Framework
+ $(EDK_SOURCE)/Foundation/Include/IndustryStandard
+ $(EDK_SOURCE)/Foundation/Core/Dxe
+ $(EDK_SOURCE)/Foundation/Include/Pei
+ $(EDK_SOURCE)/Foundation/Library/Dxe/Include
+ $(EDK_SOURCE)/Foundation/Library/EdkIIGlueLib/Include
+
+[nmake.common]
diff --git a/ReferenceCode/Chipset/SystemAgent/AcpiTables/SwitchableGraphics/Pch/SgAcpiTablesPch.cif b/ReferenceCode/Chipset/SystemAgent/AcpiTables/SwitchableGraphics/Pch/SgAcpiTablesPch.cif
new file mode 100644
index 0000000..55ed596
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/AcpiTables/SwitchableGraphics/Pch/SgAcpiTablesPch.cif
@@ -0,0 +1,12 @@
+<component>
+	name = "SgAcpiTablesPch"
+	category = ModulePart
+	LocalRoot = "ReferenceCode\Chipset\SystemAgent\AcpiTables\SwitchableGraphics\Pch\"
+	RefName = "SgAcpiTablesPch"
+[files]
+"SgAcpiTablesPch.sdl"	
+"SgAcpiTablesPch.mak"	
+"SgAcpiTablesPch.inf"
+"SgDgpuPch.asl"
+"SgSsdtPch.asl"	
+<endComponent>
diff --git a/ReferenceCode/Chipset/SystemAgent/AcpiTables/SwitchableGraphics/Pch/SgAcpiTablesPch.inf b/ReferenceCode/Chipset/SystemAgent/AcpiTables/SwitchableGraphics/Pch/SgAcpiTablesPch.inf
new file mode 100644
index 0000000..5fdc0ea
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/AcpiTables/SwitchableGraphics/Pch/SgAcpiTablesPch.inf
@@ -0,0 +1,69 @@
+## @file
+#  Component description file for the ACPI tables
+#
+#@copyright
+#  Copyright (c)  2010 - 2012 Intel Corporation. All rights reserved
+#  This software and associated documentation (if any) is furnished
+#  under a license and may only be used or copied in accordance
+#  with the terms of the license. Except as permitted by such
+#  license, no part of this software or documentation may be
+#  reproduced, stored in a retrieval system, or transmitted in any
+#  form or by any means without the express written consent of
+#  Intel Corporation.
+#
+#  This file contains an 'Intel Peripheral Driver' and uniquely
+#  identified as "Intel Reference Module" and is
+#  licensed for Intel CPUs and chipsets under the terms of your
+#  license agreement with Intel or your vendor.  This file may
+#  be modified by the user, subject to additional terms of the
+#  license agreement
+#
+
+
+[defines]
+BASE_NAME            = SgAcpiTablesPch
+FILE_GUID            = CBCB3817-81E6-497e-87FF-C8FA8F24EC28
+COMPONENT_TYPE       = ACPITABLE
+FFS_EXT              = .ffs
+
+[sources.common]
+  SgSsdtPch.ASL
+
+[libraries.common]
+
+[includes.common]
+  .
+  $(EFI_SOURCE)
+  $(EFI_SOURCE)/Include
+  $(EFI_SOURCE)/$(PROJECT_SA_ROOT)/Include
+  $(EDK_SOURCE)/Foundation/Efi
+  $(EDK_SOURCE)/Foundation/Include
+  $(EDK_SOURCE)/Foundation/Efi/Include
+  $(EDK_SOURCE)/Foundation/Framework/Include
+  $(EFI_SOURCE)/Include/IndustryStandard
+  $(EDK_SOURCE)/Foundation/Include/IndustryStandard
+  $(EDK_SOURCE)/Foundation/Library/Dxe/Include
+  $(EDK_SOURCE)/Foundation
+  $(EDK_SOURCE)/Foundation/Framework
+#
+# Typically the sample code referenced will be available in the code base already
+# So keep this include at the end to defer to the source base definition
+# and only use the sample code definition if source base does not include these files.
+#
+  $(EFI_SOURCE)/$(PROJECT_SA_ROOT)/SampleCode/Include
+
+#
+# Edk II Glue Library, some hearder are included by R9 header so have to include
+#
+
+ $(EFI_SOURCE)
+ $(EFI_SOURCE)/Framework
+ $(EDK_SOURCE)/Foundation
+ $(EDK_SOURCE)/Foundation/Framework
+ $(EDK_SOURCE)/Foundation/Include/IndustryStandard
+ $(EDK_SOURCE)/Foundation/Core/Dxe
+ $(EDK_SOURCE)/Foundation/Include/Pei
+ $(EDK_SOURCE)/Foundation/Library/Dxe/Include
+ $(EDK_SOURCE)/Foundation/Library/EdkIIGlueLib/Include
+
+[nmake.common]
diff --git a/ReferenceCode/Chipset/SystemAgent/AcpiTables/SwitchableGraphics/Pch/SgAcpiTablesPch.mak b/ReferenceCode/Chipset/SystemAgent/AcpiTables/SwitchableGraphics/Pch/SgAcpiTablesPch.mak
new file mode 100644
index 0000000..4f84b21
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/AcpiTables/SwitchableGraphics/Pch/SgAcpiTablesPch.mak
@@ -0,0 +1,62 @@
+#*************************************************************************
+#*************************************************************************
+#**                                                                     **
+#**        (C)Copyright 1985-2011, American Megatrends, Inc.            **
+#**                                                                     **
+#**                       All Rights Reserved.                          **
+#**                                                                     **
+#**      5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093           **
+#**                                                                     **
+#**                       Phone: (770)-246-8600                         **
+#**                                                                     **
+#*************************************************************************
+#*************************************************************************
+
+#*************************************************************************
+#<AMI_FHDR_START>
+#
+# Name: SgAcpiTablesPch.mak
+#
+# Description: MAK file for the ModulePart:SgAcpiTablesPch
+# 
+#
+#<AMI_FHDR_END>
+#*************************************************************************
+EDK: SGPCHASL
+
+SGPCHASL: $(BUILD_DIR)\SGACPIPCH.ffs
+
+ALLSGPCHSEC = $(BUILD_DIR)\SGACPIPCH.sec
+
+!IFNDEF IASL
+IASL = iasl4.exe 	# Intel ASL compiler. Supports extended ACPI 2.0 asl objects
+!ENDIF
+
+#-----------------------------------------------------------------------#
+#		Process SGPCH asl files
+#-----------------------------------------------------------------------#
+
+$(BUILD_DIR)\SgSsdtPch.asl : $(SGACPIPCH_DIR)\SgSsdtPch.ASL \
+                             $(SGACPIPCH_DIR)\SgDgpuPch.ASL
+    $(CP) /I$(SGACPIPCH_DIR) /FItoken.h /C $(SGACPIPCH_DIR)\$(@F) > $@
+# include the token.h if needed to check for SDL flags
+#  /FItoken.h
+
+SgAcpiTablesPch_Includes = \
+	$(SGACPIPCH_DIR)\
+
+$(BUILD_DIR)\SgSsdtPch.aml: $(BUILD_DIR)\SgSsdtPch.asl
+	$(SILENT)$(IASL) -I $(SgAcpiTablesPch_Includes) -p $@  $**
+
+$(ALLSGPCHSEC): $(BUILD_DIR)\SgSsdtPch.aml
+  $(GENSECTION) -I $** -O $@ -S EFI_SECTION_RAW
+
+$(BUILD_DIR)\SGACPIPCH.ffs: $(ALLSGPCHSEC) $(SGACPIPCH_DIR)\SgAcpiTablesPch.mak
+	$(MAKE) /f Core\FFS.mak \
+		BUILD_DIR=$(BUILD_DIR) \
+        GUID=CBCB3817-81E6-497e-87FF-C8FA8F24EC28\
+		TYPE=EFI_FV_FILETYPE_FREEFORM \
+        FFS_CHECKSUM=1\
+		RAWFILE=$(ALLSGPCHSEC) FFSFILE=$(BUILD_DIR)\SGACPIPCH.ffs COMPRESS=0 NAME=SGACPIPCH
+
+
diff --git a/ReferenceCode/Chipset/SystemAgent/AcpiTables/SwitchableGraphics/Pch/SgAcpiTablesPch.sdl b/ReferenceCode/Chipset/SystemAgent/AcpiTables/SwitchableGraphics/Pch/SgAcpiTablesPch.sdl
new file mode 100644
index 0000000..94ec922
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/AcpiTables/SwitchableGraphics/Pch/SgAcpiTablesPch.sdl
@@ -0,0 +1,113 @@
+TOKEN
+	Name  = SgAcpiTablesPch_SUPPORT
+	Value  = 1
+	TokenType = Boolean
+	TargetEQU = Yes
+	TargetMAK = Yes
+	Master = Yes
+	Help  = "Main switch to enable SgAcpiTablesPch support in Project"
+    Token = "SwitchableGraphics_SUPPORT" "=" "1"
+End
+
+TOKEN
+	Name  = "SG_ULT_RPNum"
+	Value  = "1"
+	TokenType = Expression
+        TargetMak = Yes
+	TargetH = Yes
+        Token = "SG_ULT_PORT_FUNC" "=" "0"
+	Lock = Yes
+End
+
+TOKEN
+	Name  = "SG_ULT_RPNum"
+	Value  = "2"
+	TokenType = Expression
+        TargetMak = Yes
+	TargetH = Yes
+        Token = "SG_ULT_PORT_FUNC" "=" "1"
+	Lock = Yes
+End
+
+TOKEN
+	Name  = "SG_ULT_RPNum"
+	Value  = "3"
+	TokenType = Expression
+        TargetMak = Yes
+	TargetH = Yes
+        Token = "SG_ULT_PORT_FUNC" "=" "2"
+	Lock = Yes
+End
+
+TOKEN
+	Name  = "SG_ULT_RPNum"
+	Value  = "4"
+	TokenType = Expression
+        TargetMak = Yes
+	TargetH = Yes
+        Token = "SG_ULT_PORT_FUNC" "=" "3"
+	Lock = Yes
+End
+
+TOKEN
+	Name  = "SG_ULT_RPNum"
+	Value  = "5"
+	TokenType = Expression
+        TargetMak = Yes
+	TargetH = Yes
+        Token = "SG_ULT_PORT_FUNC" "=" "4"
+	Lock = Yes
+End
+
+TOKEN
+	Name  = "SG_ULT_RPNum"
+	Value  = "6"
+	TokenType = Expression
+        TargetMak = Yes
+	TargetH = Yes
+        Token = "SG_ULT_PORT_FUNC" "=" "5"
+	Lock = Yes
+End
+
+TOKEN
+	Name  = "SG_ULT_RPNum"
+	Value  = "7"
+	TokenType = Expression
+        TargetMak = Yes
+	TargetH = Yes
+        Token = "SG_ULT_PORT_FUNC" "=" "6"
+	Lock = Yes
+End
+
+TOKEN
+	Name  = "SG_ULT_RPNum"
+	Value  = "8"
+	TokenType = Expression
+        TargetMak = Yes
+	TargetH = Yes
+        Token = "SG_ULT_PORT_FUNC" "=" "7"
+	Lock =Yes
+End
+
+TOKEN
+	Name  = "SG_ULT_RP_NUM"
+	Value  = "\_SB.PCI0.RP0$(SG_ULT_RPNum)"
+	TokenType = Expression
+	TargetH = Yes
+	Lock = Yes
+End
+
+MODULE
+	Help  = "Includes SgAcpiTablesPch.mak to Project"
+	File  = "SgAcpiTablesPch.mak"
+End
+
+PATH
+	Name  = "SGACPIPCH_DIR"
+End
+
+ELINK
+	Name  = "$(BUILD_DIR)\SGACPIPCH.ffs"
+	Parent  = "FV_MAIN"
+	InvokeOrder = AfterParent
+End
diff --git a/ReferenceCode/Chipset/SystemAgent/AcpiTables/SwitchableGraphics/Pch/SgDgpuPch.asl b/ReferenceCode/Chipset/SystemAgent/AcpiTables/SwitchableGraphics/Pch/SgDgpuPch.asl
new file mode 100644
index 0000000..76a9a0e
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/AcpiTables/SwitchableGraphics/Pch/SgDgpuPch.asl
@@ -0,0 +1,847 @@
+/**************************************************************************;
+;*                                                                        *;
+;*    Intel Confidential                                                  *;
+;*                                                                        *;
+;*    Intel Corporation - SG Reference Code                               *;
+;*    Family of Customer Reference Boards.                                *;
+;*                                                                        *;
+;*                                                                        *;
+;*    Copyright (c) 2010 - 2013 Intel Corporation. All rights reserved    *;
+;*    This software and associated documentation (if any) is furnished    *;
+;*    under a license and may only be used or copied in accordance        *;
+;*    with the terms of the license. Except as permitted by such          *;
+;*    license, no part of this software or documentation may be           *;
+;*    reproduced, stored in a retrieval system, or transmitted in any     *;
+;*    form or by any means without the express written consent of         *;
+;*    Intel Corporation.                                                  *;
+;*                                                                        *;
+;*                                                                        *;
+;**************************************************************************/
+/*++
+  This file contains an 'Intel Peripheral Driver' and is
+  licensed for Intel CPUs and chipsets under the terms of your  
+  license agreement with Intel or your vendor.  This file may   
+  be modified by the user, subject to additional terms of the   
+  license agreement                                             
+--*/
+
+External(\_SB.PCI0.GFX0._DOD, MethodObj)
+External(\_SB.PCI0.GFX0.DD01._ADR, MethodObj)
+External(\_SB.PCI0.GFX0.DD02._ADR, MethodObj)
+External(\_SB.PCI0.GFX0.DD03._ADR, MethodObj)
+External(\_SB.PCI0.GFX0.DD04._ADR, MethodObj)
+External(\_SB.PCI0.GFX0.DD05._ADR, MethodObj)
+External(\_SB.PCI0.GFX0.DD06._ADR, MethodObj)
+External(\_SB.PCI0.GFX0.DD07._ADR, MethodObj)
+External(\_SB.PCI0.GFX0.DD08._ADR, MethodObj)
+
+External(\_SB.PCI0.GFX0.DD01._DGS, MethodObj)
+External(\_SB.PCI0.GFX0.DD02._DGS, MethodObj)
+External(\_SB.PCI0.GFX0.DD03._DGS, MethodObj)
+External(\_SB.PCI0.GFX0.DD04._DGS, MethodObj)
+External(\_SB.PCI0.GFX0.DD05._DGS, MethodObj)
+External(\_SB.PCI0.GFX0.DD06._DGS, MethodObj)
+External(\_SB.PCI0.GFX0.DD07._DGS, MethodObj)
+External(\_SB.PCI0.GFX0.DD08._DGS, MethodObj)
+
+External(\_SB.PCI0.GFX0.DD02._DCS, MethodObj)
+
+External(\_SB.PCI0.GFX0.DD02._BCL, MethodObj)
+External(\_SB.PCI0.GFX0.DD02._BQC, MethodObj)
+External(\_SB.PCI0.GFX0.DD02._BCM, MethodObj)
+//AMI override begin
+External(SG_ULT_RP_NUM, DeviceObj)
+//External(\_SB.PCI0.RP05, DeviceObj)
+//AMI override end
+External(\RPA4)
+External(\EECP)
+External(\XBAS)
+External(\GBAS)
+External(\HLRS)
+External(\PWEN)
+External(\SGMD)
+External(\SGGP)
+//AMI override begin
+External(\EBAS)
+External(\HYSS)
+//AMI override end
+//AMI override begin
+Scope(SG_ULT_RP_NUM)
+//Scope(\_SB.PCI0.RP05)
+//AMI override end
+{
+    OperationRegion (MSID, SystemMemory, EBAS, 0x50)
+    Field(MSID, DWordAcc, Lock, Preserve)
+    {
+        VEID, 16,
+	Offset(0x40),
+        NVID, 32,
+        offset(0x4c),
+        ATID, 32,
+    }
+    // Define a Memory Region that will allow access to the PCH root port
+    // Register Block.
+    //
+//    OperationRegion(RPCI,PCI_Config,0x00,0xF0)
+//    Field(RPCI,DWordAcc,Lock,Preserve)
+//    {
+//    }
+
+    OperationRegion(RPCX,SystemMemory,Add(Add(\XBAS,0xE0000), ShiftLeft(And(\RPA4,0xF),12)),0x1000)
+    Field(RPCX,DWordAcc,NoLock,Preserve)
+    {
+        Offset(0),
+        PVID,   16,
+        PDID,   16,
+// AMI_OVERRIDE >>>
+	Offset(0x4),
+	CMDR, 8,
+// AMI_OVERRIDE >>>	
+        Offset(0x50),                   // LCTL - Link Control Register of (PCI Express* -> B00:D28:F04)
+        ASPM,   2,                      // 1:0, ASPM //Not referenced in code
+        ,       2,
+        LNKD,   1,                      // Link Disable
+ // AMI_OVERRIDE >>>
+	Offset(0xA4),
+	D0ST, 2,
+// AMI_OVERRIDE >>>
+        Offset(0x328), //PCIESTS1 - PCI Express Status 1
+        ,       19,
+        LNKS,   4,     //Link Status (LNKSTAT) {22:19}
+    }
+
+    //-----------------------------------------
+    // Runtime Device Power Management - Begin
+    //-----------------------------------------
+    // Note:
+    //      Runtime Device Power Management can be achieved by using _PRx or _PSx or both
+
+    //
+    // Name: PC05
+    // Description: Declare a PowerResource object for RP05 slot device
+    //
+    PowerResource(PC05, 0, 0)
+    {
+      Name(_STA, One)
+
+      Method(_ON, 0, Serialized)
+      {
+
+// AMI_OVERRIDE >>>
+//        \_SB.PCI0.RP05.PEGP.HGON()
+        \_SB.PCI0.RP05.PEGP.SGON()
+        Store(0x07, CMDR)
+        Store(0, D0ST)
+
+        If(LEqual(VEID,0x10DE))
+        {
+          Store(HYSS, NVID)
+        }
+        If(LEqual(VEID,0x1002))
+        {
+          Store(HYSS, ATID)
+        }
+// AMI_OVERRIDE <<<
+        Store(One, _STA)
+      }
+
+      Method(_OFF, 0, Serialized)
+      {
+
+// AMI_OVERRIDE >>>
+//        \_SB.PCI0.RP05.PEGP.HGOF()
+        \_SB.PCI0.RP05.PEGP.SGOF()
+// AMI_OVERRIDE <<<
+        Store(Zero, _STA)
+      }
+    } //End of PowerResource(PC05, 0, 0)
+
+    Name(_PR0,Package(){PC05})
+    Name(_PR2,Package(){PC05})
+    Name(_PR3,Package(){PC05})
+
+//    //
+//    // Name: _PS0
+//    // Description: D0 Method for RP05 slot device
+//    // Input: Nothing
+//    // Return: Nothing
+//    //
+//    Method(_PS0, 0, Serialized)
+//    {
+//
+//      \_SB.PCI0.RP05.PEGP.HGON()
+//    }
+//
+//    //
+//    // Name: _PS3
+//    // Description: D3 Method for RP05 slot device
+//    // Input: Nothing
+//    // Return: Nothing
+//    //
+//    Method(_PS3, 0, Serialized)
+//    {
+//
+//      \_SB.PCI0.RP05.PEGP.HGOF()
+//    }
+
+    Method(_S0W, 0)
+    {
+      Return(4) //D3cold is supported
+    }
+
+    //-----------------------------------------
+    // Runtime Device Power Management - End
+    //-----------------------------------------
+
+    Device(PEGP) { // (PCI Express* -> B00:D28:F04) Slot Device D0F0
+      Name(_ADR, 0x00000000)
+      Method(_PRW, 0) { Return(GPRW(0x09, 4)) } // can wakeup from S4 state
+    } // (PCI Express* -> B00:D28:F04) Slot Device D0F0
+
+    Device(PEGA) { // (PCI Express* -> B00:D28:F04) Slot Device D0F1
+      Name(_ADR, 0x00000001)
+
+      OperationRegion(ACAP, PCI_Config, \EECP,0x14)
+      Field(ACAP,DWordAcc, NoLock,Preserve)
+      {
+        Offset(0x10),
+        LCT1,   16,  // Link Control register
+      }
+      Method(_PRW, 0) { Return(GPRW(0x09, 4)) } // can wakeup from S4 state
+    } // (PCI Express* -> B00:D28:F04) Slot Device D0F1
+}
+//AMI override begin
+Scope(SG_ULT_RP_NUM.PEGP)
+//Scope(\_SB.PCI0.RP05.PEGP)
+//AMI override end
+{       
+    Name (ONOF, 0x1) //Endpoint On-Off flag status. Assume Endpoint is ON by default {1-ON, 0-OFF}
+    Name (IVID, 0xFFFF) //Invalid Vendor ID
+    Name (ELCT, 0x00000000)
+    Name (HVID, 0x0000)
+    Name (HDID, 0x0000)
+
+    OperationRegion (PCIS, PCI_Config, 0x00, 0xF0)
+    Field(PCIS, AnyAcc, Lock, Preserve)
+    {
+        Offset(0x0),
+        DVID, 16,
+        Offset(0xB),
+        CBCC, 8,
+        Offset(0x2C),
+        SVID, 16,
+        SDID, 16,
+        Offset(0x4C),
+        WVID, 16,
+        WDID, 16,
+    }
+
+    OperationRegion(PCAP, PCI_Config, \EECP,0x14)
+    Field(PCAP,DWordAcc, NoLock,Preserve)
+    {
+        Offset(0x10),
+        LCTL,   16,                      // Link Control register
+    }
+
+    Method (_INI)
+    {
+    //AMI override begin
+        Store (0x0, SG_ULT_RP_NUM.PEGP._ADR)
+	//Store (0x0, \_SB.PCI0.RP05.PEGP._ADR)
+    //AMI override end
+    }
+
+// AMI CHANGE BEGIN. 
+    Method(SGON,0,Serialized)
+//    Method(HGON,0,Serialized)
+// AMI CHANGE END. 
+    {
+
+	//AMI override begin
+        Store("SG_ULT_RP_NUM.PEGP._ON", Debug)
+        //Store("\_SB.PCI0.RP05.PEGP._ON", Debug)
+        //AMI override end
+        If (LEqual(CCHK(1), 0))
+        {
+          Return ()
+        }
+
+        Store(1, ONOF) //Indicate Endpoint is in ON state
+
+        //ACTION TODO:
+        //........................................................................................
+        //While powering up the slot again, the only requirement is that the Reset# should be 
+        //de-asserted 100ms after the power to slot is up (Standard requirement as per PCIe spec).
+
+        //Note:
+        //Before power enable, and for 100ms after power enable, the reset should be in hold condition.
+        //The 100 ms time is given for power rails and clocks to become stable.
+        //So during this period, reset must not be released.
+        //........................................................................................
+
+        //Power on the dGPU card
+        SGPO(HLRS, 1)                  //Assert dGPU_HOLD_RST# {Hold the dGPU Reset}
+        SGPO(PWEN, 1)                  //Assert dGPU_PWR_EN# {Power on the dGPU}
+
+        Sleep(300)                     // Wait for 300ms if dGPU_PWROK has h/w issues
+        
+        SGPO(HLRS, 0)                  //Deassert dGPU_HOLD_RST# {Release the dGPU Reset}
+        Sleep(100)                     // Wait for 100ms
+        
+        //Enable x4 Link
+        //This bit should already be set to 0 in the _Off method. But do it anyway.
+        Store(0,LNKD)
+
+        //wait until link has trained to x4. Verify        
+        While(LLess(LNKS,7))
+        {
+                Sleep(1)
+        }
+
+        // Re-store the DGPU SSID
+        Store(HVID,WVID)
+        Store(HDID,WDID)
+
+        // Re-store the Link Control register - Common Clock Control and ASPM
+        Or(And(ELCT,0x0043),And(LCTL,0xFFBC),LCTL)
+//AMI override begin
+        Or(And(ELCT,0x0043),And(SG_ULT_RP_NUM.PEGA.LCT1,0xFFBC),SG_ULT_RP_NUM.PEGA.LCT1)
+	//Or(And(ELCT,0x0043),And(\_SB.PCI0.RP05.PEGA.LCT1,0xFFBC),\_SB.PCI0.RP05.PEGA.LCT1)
+
+//        Return ()
+//    }
+
+//    Method(_ON,0,Serialized)
+//    {
+
+//        HGON()
+//AMI override end
+        //Ask OS to do a PnP rescan
+// AMI CHANGE BEGIN. 
+//        Notify(SG_ULT_RP_NUM,0)
+// AMI CHANGE END. 
+
+// AMI CHANGE BEGIN.
+        Return (1)                      
+// AMI CHANGE END.
+    }
+
+// AMI CHANGE BEGIN. 
+//    Method(HGOF,0,Serialized)
+    Method(SGOF,0,Serialized)
+// AMI CHANGE END. 
+    {
+
+        If (LEqual(CCHK(0), 0))
+        {
+          Return ()
+        }
+
+        Store(0, ONOF) //Indicate Endpoint is in OFF state
+
+        //ACTION TODO:
+        //........................................................................................
+        //To turn off the power to the slot, all you would need to do is assert the RESET# 
+        //and then take off the power using the power enable GPIO.
+        //Once the power goes off, the clock request from the slot to the PCH is also turned off, 
+        //so no clocks will be going to the PCIe slot anymore.
+        //........................................................................................
+        
+        // Save the Link Control register
+        Store(LCTL,ELCT)
+
+        // Save the DGPU SSID
+        Store(SVID,HVID)
+        Store(SDID,HDID)
+
+        //Force disable the x4 link
+        Store(1, LNKD)
+
+        //Wait till link is actually in disabled state
+        While(LNotEqual(LNKS,0))
+        {
+            Sleep(1)
+        }
+
+        //Power-off the dGPU card
+        SGPO(HLRS, 1)                   // Assert dGPU_HOLD_RST# (PERST#) {Hold the dGPU Reset}
+        SGPO(PWEN, 0)                   // Deassert dGPU_PWR_EN#  {Power off the dGPU}
+// AMI CHANGE BEGIN.
+//        Return ()
+//    }
+//       
+//    Method(_OFF,0,Serialized)
+//    {
+//
+//        HGOF()
+// AMI CHANGE END.
+        //Ask OS to do a PnP rescan
+// AMI CHANGE BEGIN. 
+//        Notify(SG_ULT_RP_NUM,0)
+// AMI CHANGE END. 
+
+// AMI CHANGE BEGIN.
+        Return (0)
+// AMI CHANGE END.
+    }
+
+    Method(EPON, 0, Serialized)
+    {
+      Store(1, ONOF) //Indicate Endpoint is in ON state
+
+      Return ()
+    }
+        
+// AMI CHANGE BEGIN. 
+//    Method(_STA,0,Serialized)
+    Method(SGST,0,Serialized)
+// AMI CHANGE END. 
+    {
+      //
+      // Check SGMode and dGPU Present Detect GPIO for SG system
+      //
+      If(And(SGMD,0x0F))
+      {
+        If(LNotEqual(SGGP,0x01))
+        {
+           Return(0x0F)
+        }
+
+        // To detect dGPU: Check Device is present and which belongs to display controllers type also.
+        If(LNotEqual(DVID,0xFFFF))
+        {
+            If(LEqual(CBCC,0x3)) // Base Class Code 03h which is referring all types of display controllers
+            {
+               Return(0x0F)
+            }
+        }
+	  
+        Return(0x00)
+      }
+
+      //
+      // For non-SG system check for valid Vendor Id
+      //
+      If(LNotEqual(DVID,0xFFFF))
+      {
+          Return(0x0F)
+      }
+      Return(0x00)
+    }
+
+
+    Method(_DOD,0)
+    {
+        Return (\_SB.PCI0.GFX0._DOD())
+    }
+
+
+    Device(DD01)
+    {
+            Method(_ADR,0,Serialized)
+            {
+                    Return(\_SB.PCI0.GFX0.DD01._ADR())
+            }
+
+            // Device Current State.
+            Method(_DCS,0)
+            {
+
+            }
+
+            // Device Get State.
+
+            Method(_DGS,0)
+            {
+                    // Return the Next State.
+                    Return(\_SB.PCI0.GFX0.DD01._DGS())
+            }
+
+            // Device Set State.
+
+            // _DSS Table:
+            //
+            //  BIT31   BIT30   Execution
+            //  0       0       Don't implement.
+            //  0       1       Cache change.  Nothing to Implement.
+            //  1       0       Don't Implement.
+            //  1       1       Display Switch Complete.  Implement.
+
+            Method(_DSS,1)
+            {
+                    // Do nothing here in the OpRegion model.  OEMs may choose to
+                    // update internal state if necessary.
+            }
+    }
+
+    Device(DD02)
+    {
+            Method(_ADR,0,Serialized)
+            {
+                    Return(\_SB.PCI0.GFX0.DD02._ADR())
+            }
+
+            // Device Current State.
+
+            Method(_DCS,0)
+            {
+                    // Get the Current Display State.
+                    Return(\_SB.PCI0.GFX0.DD02._DCS())
+            }
+
+            // Device Get State.
+
+            Method(_DGS,0)
+            {
+                    // Return the Next State.
+                    Return(\_SB.PCI0.GFX0.DD02._DGS())
+            }
+
+            // Device Set State.
+
+            Method(_DSS,1)
+            {
+                    // Do nothing here in the OpRegion model.  OEMs may choose to
+                    // update internal state if necessary.
+            }
+
+/*
+            Method(_DDC,1)
+            {
+                    If(Lor(LEqual(\_SB.PCI0.GFX0.PHED,1),LEqual(\_SB.PCI0.GFX0.PHED,2)))
+                    {
+                        Name(DDC2,Buffer (256) {0x0})
+                        Store(\_SB.PCI0.GFX0.BDDC,DDC2)
+                        Return(DDC2)
+                    }
+                    Return(Buffer(256){0x0})
+            }
+*/
+            Method(_BCL,0)
+            {
+                    Return(\_SB.PCI0.GFX0.DD02._BCL())
+            }
+
+            Method(_BQC,0)
+            {
+                    Return(\_SB.PCI0.GFX0.DD02._BQC())
+            }
+            
+            Method(_BCM,1)
+            {
+                    Return(\_SB.PCI0.GFX0.DD02._BCM(Arg0))
+            }
+
+    }
+
+    Device(DD03)
+    {
+            Method(_ADR,0,Serialized)
+            {
+                    Return(\_SB.PCI0.GFX0.DD03._ADR())
+            }
+
+            // Device Current State.
+
+            Method(_DCS,0)
+            {
+                    // Get the Current Display State.
+            }
+
+            // Device Get State.
+
+            Method(_DGS,0)
+            {
+                    // Return the Next State.
+                    Return(\_SB.PCI0.GFX0.DD03._DGS())
+            }
+
+            // Device Set State.
+
+            Method(_DSS,1)
+            {
+                    // Do nothing here in the OpRegion model.  OEMs may choose to
+                    // update internal state if necessary.
+            }
+    }
+
+    Device(DD04)
+    {
+            Method(_ADR,0,Serialized)
+            {
+                    Return(\_SB.PCI0.GFX0.DD04._ADR())
+            }
+
+            // Device Current State.
+
+            Method(_DCS,0)
+            {
+                    // Get the Current Display State.
+            }
+
+            // Device Get State.
+
+            Method(_DGS,0)
+            {
+                    // Return the Next State.
+                    Return(\_SB.PCI0.GFX0.DD04._DGS())
+            }
+
+            // Device Set State.
+
+            Method(_DSS,1)
+            {
+                    // Do nothing here in the OpRegion model.  OEMs may choose to
+                    // update internal state if necessary.
+            }
+            
+    }
+
+    Device(DD05)
+    {
+            Method(_ADR,0,Serialized)
+            {
+                    Return(\_SB.PCI0.GFX0.DD05._ADR())
+            }
+
+            // Device Current State.
+
+            Method(_DCS,0)
+            {
+                    // Get the Current Display State.
+            }
+
+            // Device Get State.
+
+            Method(_DGS,0)
+            {
+                    // Return the Next State.
+                    Return(\_SB.PCI0.GFX0.DD05._DGS())
+            }
+
+            // Device Set State.
+
+            Method(_DSS,1)
+            {
+                    // Do nothing here in the OpRegion model.  OEMs may choose to
+                    // update internal state if necessary.
+            }
+    }
+
+    Device(DD06)
+    {
+            Method(_ADR,0,Serialized)
+            {
+                    Return(\_SB.PCI0.GFX0.DD06._ADR())
+            }
+
+            // Device Current State.
+
+            Method(_DCS,0)
+            {
+                    // Get the Current Display State.
+            }
+
+            // Device Get State.
+
+            Method(_DGS,0)
+            {
+                    // Return the Next State.
+                    Return(\_SB.PCI0.GFX0.DD06._DGS())
+            }
+
+            // Device Set State.
+
+            Method(_DSS,1)
+            {
+                    // Do nothing here in the OpRegion model.  OEMs may choose to
+                    // update internal state if necessary.
+            }
+    }
+    
+    Device(DD07)
+    {
+            Method(_ADR,0,Serialized)
+            {
+                    Return(\_SB.PCI0.GFX0.DD07._ADR())
+            }
+
+            // Device Current State.
+
+            Method(_DCS,0)
+            {
+                    // Get the Current Display State.
+            }
+
+            // Device Get State.
+
+            Method(_DGS,0)
+            {
+                    // Return the Next State.
+                    Return(\_SB.PCI0.GFX0.DD07._DGS())
+            }
+
+            // Device Set State.
+
+            Method(_DSS,1)
+            {
+                    // Do nothing here in the OpRegion model.  OEMs may choose to
+                    // update internal state if necessary.
+            }
+    }
+
+    Device(DD08)
+    {
+            Method(_ADR,0,Serialized)
+            {
+                    Return(\_SB.PCI0.GFX0.DD08._ADR())
+            }
+
+            // Device Current State.
+
+            Method(_DCS,0)
+            {
+                    // Get the Current Display State.
+            }
+
+            // Device Get State.
+
+            Method(_DGS,0)
+            {
+                    // Return the Next State.
+                    Return(\_SB.PCI0.GFX0.DD08._DGS())
+            }
+
+            // Device Set State.
+
+            Method(_DSS,1)
+            {
+                    // Do nothing here in the OpRegion model.  OEMs may choose to
+                    // update internal state if necessary.
+            }
+    }
+
+  
+  // GPIO Read
+  // Arg0 = GPIO No + GPIO active info. {BIT7 => (1:Active, 0: Not active), BIT6:0 => GPIO No}
+  Method (SGPI,1,Serialized)
+  {
+    If(And(SGMD,0x0F))
+    {
+      If(LEqual(SGGP,0x01))
+      {
+        ShiftRight (Arg0, 7, Local1) //GPIO active info
+        And(Arg0, 0x7F, Arg0) //GPIO No
+
+        // Read the GPIO [GPI_LVL]
+        // Arg0 - GPIO Pin number to read
+        If(LLessEqual(Arg0, 94)){
+          Store( Add(Add(\GBAS,0x100) , Multiply(Arg0,0x08)),Local0 )
+          OperationRegion(LGPI, SystemIo, Local0, 8)
+          Field(LGPI, ByteAcc, NoLock, Preserve) {
+          Offset(0x0),
+          , 30,
+          TEMP, 1
+          }
+      
+          Store(TEMP, Local2)
+        }
+ 
+        // 
+        // Check if Active Low
+        //
+        If (LEqual(Local1,0))
+        {
+          Not(Local2, Local2)
+        }
+
+        Return(And(Local2,0x01))
+      }
+    }
+	
+    Return(0)
+  }
+  
+
+  // GPIO Write
+  // Arg0 = GPIO No + GPIO active info. {BIT7 => (1:Active, 0: Not active), BIT6:0 => GPIO No}
+  // Arg1 = Value (0/1)
+  Method (SGPO,2,Serialized)
+  {
+    If(And(SGMD,0x0F))
+    {
+      If(LEqual(SGGP,0x01))
+      {
+        ShiftRight (Arg0, 7, Local1) //GPIO active info
+        And(Arg0, 0x7F, Arg0) //GPIO No
+
+        // 
+        // Check if Active Low
+        //
+        If (LEqual(Local1,0))
+        {
+          Not(Arg1, Arg1)
+        }
+
+        And (Arg1, 0x01, Arg1)
+	
+        // Program the GPIO [GPO_LVL]
+        // Arg0 - GPIO Pin number to write
+        // Arg1 - Value to be written
+        If(LLessEqual(Arg0, 94)){
+          Store( Add(Add(\GBAS,0x100) , Multiply(Arg0,0x08)),Local0 )
+          OperationRegion(LGPI, SystemIo, Local0, 8)
+          Field(LGPI, ByteAcc, NoLock, Preserve) {
+          Offset(0x0),
+          , 31,
+          TEMP, 1
+          }
+      
+          Store(Arg1,TEMP)
+        }
+      }
+    }
+  }
+
+  //
+  // Name: CCHK
+  // Description: Function to check whether _ON/_OFF sequence is allowed to execute for the given RP05 controller or not
+  // Input: Arg0 -> 0 means _OFF sequence, 1 means _ON sequence
+  // Return: 0 - Don't execute the flow, 1 - Execute the flow
+  //
+  Method(CCHK,1)
+  {
+
+    //Check for RP05 controller presence
+    If(LEqual(PVID, IVID))
+    {
+
+      Return(0)
+    }
+
+    //If Endpoint is not present[already disabled] before executing _OFF then don't call the _OFF method
+    //If Endpoint is present[already enabled] before executing _ON then don't call the _ON method
+    If(LEqual(Arg0, 0))
+    {
+      //_OFF sequence condition check
+      If(LEqual(ONOF, 0))
+      {
+
+        Return(0)
+      }
+    }
+    ElseIf(LEqual(Arg0, 1))
+    {
+      //_ON sequence condition check
+      If(LEqual(ONOF, 1))
+      {
+
+        Return(0)
+      }
+    }
+
+
+    Return(1)
+  } // End of Method(CCHK,1)
+
+}
diff --git a/ReferenceCode/Chipset/SystemAgent/AcpiTables/SwitchableGraphics/Pch/SgSsdtPch.asl b/ReferenceCode/Chipset/SystemAgent/AcpiTables/SwitchableGraphics/Pch/SgSsdtPch.asl
new file mode 100644
index 0000000..e65777c
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/AcpiTables/SwitchableGraphics/Pch/SgSsdtPch.asl
@@ -0,0 +1,43 @@
+/**************************************************************************;
+;*                                                                        *;
+;*    Intel Confidential                                                  *;
+;*                                                                        *;
+;*    Intel Corporation - SG Reference Code                               *;
+;*    Family of Customer Reference Boards.                                *;
+;*                                                                        *;
+;*                                                                        *;
+;*    Copyright (c) 2010 - 2012 Intel Corporation. All rights reserved    *;
+;*    This software and associated documentation (if any) is furnished    *;
+;*    under a license and may only be used or copied in accordance        *;
+;*    with the terms of the license. Except as permitted by such          *;
+;*    license, no part of this software or documentation may be           *;
+;*    reproduced, stored in a retrieval system, or transmitted in any     *;
+;*    form or by any means without the express written consent of         *;
+;*    Intel Corporation.                                                  *;
+;*                                                                        *;
+;*                                                                        *;
+;**************************************************************************/
+/*++
+  This file contains an 'Intel Peripheral Driver' and is
+  licensed for Intel CPUs and chipsets under the terms of your  
+  license agreement with Intel or your vendor.  This file may   
+  be modified by the user, subject to additional terms of the   
+  license agreement                                             
+--*/
+
+DefinitionBlock (
+    "Sg.aml",
+    "SSDT",
+    1,
+    "SgRef",
+    "SgPch",
+    0x1000
+    )
+{
+  External(P8XH, MethodObj) 
+  External(GPRW, MethodObj) 
+  //AMI override begin
+  //Include("SgDgpuPch.ASL")
+  #include <SgDgpuPch.ASL>
+  //AMI override end
+}
diff --git a/ReferenceCode/Chipset/SystemAgent/AcpiTables/SwitchableGraphics/Peg/SgAcpiTables.inf b/ReferenceCode/Chipset/SystemAgent/AcpiTables/SwitchableGraphics/Peg/SgAcpiTables.inf
new file mode 100644
index 0000000..0aaad00
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/AcpiTables/SwitchableGraphics/Peg/SgAcpiTables.inf
@@ -0,0 +1,69 @@
+## @file
+#  Component description file for the ACPI tables
+#
+#@copyright
+#  Copyright (c)  2010 - 2012 Intel Corporation. All rights reserved
+#  This software and associated documentation (if any) is furnished
+#  under a license and may only be used or copied in accordance
+#  with the terms of the license. Except as permitted by such
+#  license, no part of this software or documentation may be
+#  reproduced, stored in a retrieval system, or transmitted in any
+#  form or by any means without the express written consent of
+#  Intel Corporation.
+#
+#  This file contains an 'Intel Peripheral Driver' and uniquely
+#  identified as "Intel Reference Module" and is
+#  licensed for Intel CPUs and chipsets under the terms of your
+#  license agreement with Intel or your vendor.  This file may
+#  be modified by the user, subject to additional terms of the
+#  license agreement
+#
+
+
+[defines]
+BASE_NAME            = SgAcpiTables
+FILE_GUID            = CACB3817-81E6-497e-87FF-C8FA8F24EC28
+COMPONENT_TYPE       = ACPITABLE
+FFS_EXT              = .ffs
+
+[sources.common]
+  SgSsdt.ASL
+
+[libraries.common]
+
+[includes.common]
+  .
+  $(EFI_SOURCE)
+  $(EFI_SOURCE)/Include
+  $(EFI_SOURCE)/$(PROJECT_SA_ROOT)/Include
+  $(EDK_SOURCE)/Foundation/Efi
+  $(EDK_SOURCE)/Foundation/Include
+  $(EDK_SOURCE)/Foundation/Efi/Include
+  $(EDK_SOURCE)/Foundation/Framework/Include
+  $(EFI_SOURCE)/Include/IndustryStandard
+  $(EDK_SOURCE)/Foundation/Include/IndustryStandard
+  $(EDK_SOURCE)/Foundation/Library/Dxe/Include
+  $(EDK_SOURCE)/Foundation
+  $(EDK_SOURCE)/Foundation/Framework
+#
+# Typically the sample code referenced will be available in the code base already
+# So keep this include at the end to defer to the source base definition
+# and only use the sample code definition if source base does not include these files.
+#
+  $(EFI_SOURCE)/$(PROJECT_SA_ROOT)/SampleCode/Include
+
+#
+# Edk II Glue Library, some hearder are included by R9 header so have to include
+#
+
+ $(EFI_SOURCE)
+ $(EFI_SOURCE)/Framework
+ $(EDK_SOURCE)/Foundation
+ $(EDK_SOURCE)/Foundation/Framework
+ $(EDK_SOURCE)/Foundation/Include/IndustryStandard
+ $(EDK_SOURCE)/Foundation/Core/Dxe
+ $(EDK_SOURCE)/Foundation/Include/Pei
+ $(EDK_SOURCE)/Foundation/Library/Dxe/Include
+ $(EDK_SOURCE)/Foundation/Library/EdkIIGlueLib/Include
+
+[nmake.common]
diff --git a/ReferenceCode/Chipset/SystemAgent/AcpiTables/SwitchableGraphics/Peg/SgAcpiTablesPeg.cif b/ReferenceCode/Chipset/SystemAgent/AcpiTables/SwitchableGraphics/Peg/SgAcpiTablesPeg.cif
new file mode 100644
index 0000000..85524cd
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/AcpiTables/SwitchableGraphics/Peg/SgAcpiTablesPeg.cif
@@ -0,0 +1,12 @@
+<component>
+	name = "SgAcpiTablesPeg"
+	category = ModulePart
+	LocalRoot = "ReferenceCode\Chipset\SystemAgent\AcpiTables\SwitchableGraphics\Peg\"
+	RefName = "SgAcpiTablesPeg"
+[files]
+"SgAcpiTablesPeg.sdl"	
+"SgAcpiTablesPeg.mak"	
+"SgAcpiTables.inf"
+"SgDgpu.asl"
+"SgSsdt.asl"
+<endComponent>
diff --git a/ReferenceCode/Chipset/SystemAgent/AcpiTables/SwitchableGraphics/Peg/SgAcpiTablesPeg.mak b/ReferenceCode/Chipset/SystemAgent/AcpiTables/SwitchableGraphics/Peg/SgAcpiTablesPeg.mak
new file mode 100644
index 0000000..e67f4a0
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/AcpiTables/SwitchableGraphics/Peg/SgAcpiTablesPeg.mak
@@ -0,0 +1,63 @@
+#*************************************************************************
+#*************************************************************************
+#**                                                                     **
+#**        (C)Copyright 1985-2011, American Megatrends, Inc.            **
+#**                                                                     **
+#**                       All Rights Reserved.                          **
+#**                                                                     **
+#**      5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093           **
+#**                                                                     **
+#**                       Phone: (770)-246-8600                         **
+#**                                                                     **
+#*************************************************************************
+#*************************************************************************
+
+#*************************************************************************
+#<AMI_FHDR_START>
+#
+# Name: SgAcpiTables.mak
+#
+# Description: MAK file for the ModulePart:SgAcpiTables
+# 
+#
+#<AMI_FHDR_END>
+#*************************************************************************
+EDK: SGPEGASL
+
+SGPEGASL: $(BUILD_DIR)\SGACPIPEG.ffs
+
+ALLSGPEGSEC = $(BUILD_DIR)\SGACPIPEG.sec
+
+!IF "$(ACPIPLATFORM_ASL_COMPILER)"==""
+!ERROR It is an invalid path, please check your ASL compiler path.
+!ENDIF
+
+IASL = $(ACPIPLATFORM_ASL_COMPILER)  
+
+#-----------------------------------------------------------------------#
+#		Process SG asl files
+#-----------------------------------------------------------------------#
+
+$(BUILD_DIR)\SgSsdt.asl :  $(SGACPIPEG_DIR)\SgSsdt.ASL \
+                            $(SGACPIPEG_DIR)\SgDgpu.ASL
+    $(CP) /I$(SGACPIPEG_DIR) /C $(SGACPIPEG_DIR)\$(@F) > $@
+# include the token.h if needed to check for SDL flags
+#  /FItoken.h
+
+SGAcpiTablesPeg_Includes = \
+	$(SGACPIPEG_DIR)\
+
+$(BUILD_DIR)\SgSsdt.aml: $(BUILD_DIR)\SgSsdt.asl
+	$(SILENT)$(IASL) -I $(SGAcpiTablesPeg_Includes) -p $@  $**
+
+$(ALLSGPEGSEC): $(BUILD_DIR)\SgSsdt.aml
+  $(GENSECTION) -I $** -O $@ -S EFI_SECTION_RAW
+
+$(BUILD_DIR)\SGACPIPEG.ffs: $(ALLSGPEGSEC) $(SGACPIPEG_DIR)\SgAcpiTablesPeg.mak
+	$(MAKE) /f Core\FFS.mak \
+		BUILD_DIR=$(BUILD_DIR) \
+        GUID=CACB3817-81E6-497e-87FF-C8FA8F24EC28\
+		TYPE=EFI_FV_FILETYPE_FREEFORM \
+        FFS_CHECKSUM=1\
+		RAWFILE=$(ALLSGPEGSEC) FFSFILE=$(BUILD_DIR)\SGACPIPEG.ffs COMPRESS=0 NAME=SGACPIPEG
+
diff --git a/ReferenceCode/Chipset/SystemAgent/AcpiTables/SwitchableGraphics/Peg/SgAcpiTablesPeg.sdl b/ReferenceCode/Chipset/SystemAgent/AcpiTables/SwitchableGraphics/Peg/SgAcpiTablesPeg.sdl
new file mode 100644
index 0000000..1f2c571
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/AcpiTables/SwitchableGraphics/Peg/SgAcpiTablesPeg.sdl
@@ -0,0 +1,25 @@
+TOKEN
+	Name  = "SgAcpiTablesPeg_SUPPORT"
+	Value  = "1"
+	TokenType = Boolean
+	TargetEQU = Yes
+	TargetMAK = Yes
+	Master = Yes
+	Help  = "Main switch to enable SgAcpiTablesPeg support in Project"
+    Token = "SwitchableGraphics_SUPPORT" "=" "1"
+End
+
+MODULE
+	Help  = "Includes SgAcpiTablesPeg.mak to Project"
+	File  = "SgAcpiTablesPeg.mak"
+End
+
+PATH
+	Name  = "SGACPIPEG_DIR"
+End
+
+ELINK
+	Name  = "$(BUILD_DIR)\SGACPIPEG.ffs"
+	Parent  = "FV_MAIN"
+	InvokeOrder = AfterParent
+End
diff --git a/ReferenceCode/Chipset/SystemAgent/AcpiTables/SwitchableGraphics/Peg/SgDgpu.asl b/ReferenceCode/Chipset/SystemAgent/AcpiTables/SwitchableGraphics/Peg/SgDgpu.asl
new file mode 100644
index 0000000..1e63dc4
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/AcpiTables/SwitchableGraphics/Peg/SgDgpu.asl
@@ -0,0 +1,1693 @@
+/**************************************************************************;
+;*                                                                        *;
+;*    Intel Confidential                                                  *;
+;*                                                                        *;
+;*    Intel Corporation - SG Reference Code                               *;
+;*    Family of Customer Reference Boards.                                *;
+;*                                                                        *;
+;*                                                                        *;
+;*    Copyright (c) 2010 - 2013 Intel Corporation. All rights reserved    *;
+;*    This software and associated documentation (if any) is furnished    *;
+;*    under a license and may only be used or copied in accordance        *;
+;*    with the terms of the license. Except as permitted by such          *;
+;*    license, no part of this software or documentation may be           *;
+;*    reproduced, stored in a retrieval system, or transmitted in any     *;
+;*    form or by any means without the express written consent of         *;
+;*    Intel Corporation.                                                  *;
+;*                                                                        *;
+;*                                                                        *;
+;**************************************************************************/
+/*++
+  This file contains an 'Intel Peripheral Driver' and is
+  licensed for Intel CPUs and chipsets under the terms of your  
+  license agreement with Intel or your vendor.  This file may   
+  be modified by the user, subject to additional terms of the   
+  license agreement                                             
+--*/
+
+External(\_SB.PCI0.GFX0._DOD, MethodObj)
+External(\_SB.PCI0.GFX0.DD01._ADR, MethodObj)
+External(\_SB.PCI0.GFX0.DD02._ADR, MethodObj)
+External(\_SB.PCI0.GFX0.DD03._ADR, MethodObj)
+External(\_SB.PCI0.GFX0.DD04._ADR, MethodObj)
+External(\_SB.PCI0.GFX0.DD05._ADR, MethodObj)
+External(\_SB.PCI0.GFX0.DD06._ADR, MethodObj)
+External(\_SB.PCI0.GFX0.DD07._ADR, MethodObj)
+External(\_SB.PCI0.GFX0.DD08._ADR, MethodObj)
+
+External(\_SB.PCI0.GFX0.DD01._DGS, MethodObj)
+External(\_SB.PCI0.GFX0.DD02._DGS, MethodObj)
+External(\_SB.PCI0.GFX0.DD03._DGS, MethodObj)
+External(\_SB.PCI0.GFX0.DD04._DGS, MethodObj)
+External(\_SB.PCI0.GFX0.DD05._DGS, MethodObj)
+External(\_SB.PCI0.GFX0.DD06._DGS, MethodObj)
+External(\_SB.PCI0.GFX0.DD07._DGS, MethodObj)
+External(\_SB.PCI0.GFX0.DD08._DGS, MethodObj)
+
+External(\_SB.PCI0.GFX0.DD02._DCS, MethodObj)
+
+External(\_SB.PCI0.GFX0.DD02._BCL, MethodObj)
+External(\_SB.PCI0.GFX0.DD02._BQC, MethodObj)
+External(\_SB.PCI0.GFX0.DD02._BCM, MethodObj)
+External(\_SB.PCI0.PEG0, DeviceObj)
+External(\_SB.PCI0.PEG0.PEGP, DeviceObj)
+External(\_SB.PCI0.PEG0.PEGP._ADR)
+External(\EECP)
+External(\XBAS)
+External(\GBAS)
+External(\HLRS)
+External(\PWEN)
+External(\PWOK)
+External(\SGMD)
+External(\SGGP)
+External(PNHM, IntObj)
+External(P0UB, IntObj)
+External(PCSL, IntObj)
+External(SC7A, IntObj)
+//AMI override begin
+
+External(\EBAS)
+External(\HYSS)
+//AMI override begin end
+Scope(\_SB.PCI0.PEG0)
+//AMI override begin
+{
+    OperationRegion (MSID, SystemMemory, EBAS, 0x50)
+    Field(MSID, DWordAcc, Lock, Preserve)
+    {
+        VEID, 16,
+	Offset(0x40),
+        NVID, 32,
+        offset(0x4c),
+        ATID, 32,
+    }
+//AMI override begin end
+    // Define a Memory Region that will allow access to the PEG root port
+    // Register Block.
+    //
+    //OperationRegion(RPCI,PCI_Config,0x00,0xF0)
+    //Field(RPCI,DWordAcc,Lock,Preserve)
+    //{
+    //}
+
+    OperationRegion(RPCX,SystemMemory,Add(\XBAS,0x8000),0x1000)
+    Field(RPCX,ByteAcc,NoLock,Preserve)
+    {
+        Offset(0),
+        PVID,   16,
+        PDID,   16,
+// AMI_OVERRIDE >>>
+	Offset(0x4),
+	CMDR, 8,
+	Offset(0x84),
+	D0ST, 2,
+// AMI_OVERRIDE >>>
+        Offset(0xAC),                   // LCAP - Link Capabilities Register
+        ,       4,
+        CMLW,   6,                      // 9:4, Max Link Width
+        Offset(0xB0),                   // LCTL - Link Control Register
+        ASPM,   2,                      // 1:0, ASPM //Not referenced in code
+        ,       2,
+        LNKD,   1,                      // Link Disable
+        Offset(0x11A),
+        ,       1,
+        VCNP,   1,  //VC0RSTS.VC0NP
+        Offset(0x214),
+        ,       16,
+        LNKS,   4,  //PEGSTS.LKS
+        Offset(0x504),
+        ,       16,
+        PCFG,   2,  //FUSESCMN.PEG1CFGSEL
+        Offset(0x508),
+        TREN,   1,  //TRNEN.TREN
+        Offset(0x91C),
+        ,       31,
+        BSP1,   1,
+        Offset(0x93C),
+        ,       31,
+        BSP2,   1,
+        Offset(0x95C),
+        ,       31,
+        BSP3,   1,
+        Offset(0x97C),
+        ,       31,
+        BSP4,   1,
+        Offset(0x99C),
+        ,       31,
+        BSP5,   1,
+        Offset(0x9BC),
+        ,       31,
+        BSP6,   1,
+        Offset(0x9DC),
+        ,       31,
+        BSP7,   1,
+        Offset(0x9FC),
+        ,       31,
+        BSP8,   1,
+        Offset(0xC20),
+        ,       4,
+        AFES,   2,  //AFEOVR.RXSQDETOVR
+        Offset(0xD0C),
+        ,       20,
+        LREV,   1,  //PEGTST.LANEREVSTS
+    }
+
+    Method(RBP0,1) // ReadBytePEG0
+    {
+      // Function to read pcie byte of Peg0 [0x00/0x01/0x00]
+      //
+      // Arg0 : The offset of pcie config space to be read
+      //
+      Store( Add(Add(\XBAS,0x8000), Arg0) ,Local7)
+      OperationRegion(PCI0, SystemMemory, Local7, 1) 
+      Field(PCI0, ByteAcc,NoLock,Preserve)
+      {
+        TEMP, 8
+      }
+      Return(TEMP)
+    } // End of Method(RBP0,1)
+
+    Method(WBP0,2) // WriteBytePEG0
+    {
+      // Function to write pcie byte of Peg0 [0x00/0x01/0x00]
+      //
+      // Arg0 : The offset of pcie config space to be written
+      // Arg1 : Value to be written
+      //
+      Store( Add(Add(\XBAS,0x8000), Arg0) ,Local7)
+      OperationRegion(PCI0, SystemMemory, Local7, 1) 
+      Field(PCI0, ByteAcc,NoLock,Preserve)
+      {
+        TEMP, 8
+      }
+      Store(Arg1,TEMP)
+      Return(TEMP)
+    } // End of Method(WBP0,2)
+
+//    Method(BSPR,2)
+//    {
+      // Function to set/reset powerdown the bundles
+      //
+      // Arg0 : The zero based bundle number
+      // Arg1 : Value to be written
+      //
+//      Store( Add(Add(Add(\XBAS,0x8000), 0x91C) , Multiply(Arg0,0x20)),Local7)
+//      OperationRegion(PCI0, SystemMemory, Local7, 4) 
+//      Field(PCI0, DWordAcc,NoLock,Preserve)
+//      {
+//        Offset(0x0),
+//        ,31,
+//        TEMP, 1
+//      }
+//        Store(Arg1,TEMP)
+//    } // End of Method(BSPR,2)
+
+    Method(C7OK,1)
+    {
+      // Function to set/reset C7 Allowed
+      //
+      // Arg0 : Value to be written
+      //
+
+      //
+      // Memory window to the Host Bus registers 
+      //
+      OperationRegion(MWHB,SystemMemory,\XBAS,0x1000)
+      Field(MWHB,DWordAcc,NoLock,Preserve)
+      {
+          Offset(0x48),   // MCHBAR (0:0:0:48)
+          MHEN, 1,        // Enable
+              , 14,
+          MHBR, 17,       // MCHBAR [31:15]
+      }
+
+      //
+      // Memory window to the registers starting at MCHBAR+5000h. 
+      //
+      OperationRegion (MBAR, SystemMemory, Add(ShiftLeft(MHBR,15),0x5000), 0x1000)
+      Field (MBAR, ByteAcc, NoLock, Preserve)
+      {
+          Offset (0xDA8), // BIOS_RESET_CPL (MCHBAR+0x5da8)
+          ,      2,       //
+          C7AD,  1,       // C7 Allowed [2:2]
+      }
+
+      Store(Arg0,C7AD)
+    } // End of Method(C7OK,1)
+
+    //-----------------------------------------
+    // Runtime Device Power Management - Begin
+    //-----------------------------------------
+    // Note:
+    //      Runtime Device Power Management can be achieved by using _PRx or _PSx or both
+
+    //
+    // Name: PG00
+    // Description: Declare a PowerResource object for PEG0 slot device
+    //
+    PowerResource(PG00, 0, 0)
+    {
+      Name(_STA, One)
+
+      Method(_ON, 0, Serialized)
+      {
+        //
+        // SA:InternalOnlyBegin
+        // 
+        Store("\_SB.PCI0.PEG0.PG00._ON", Debug)
+        //
+        // SA:InternalOnlyEnd
+        //
+
+// AMI_OVERRIDE >>>
+//        \_SB.PCI0.PEG0.PEGP._ON()
+        \_SB.PCI0.PEG0.PEGP.SGON()
+        Store(0x07, CMDR)
+        Store(0, D0ST)
+
+        If(LEqual(VEID,0x10DE))
+        {
+          Store(HYSS, NVID)
+        }
+        If(LEqual(VEID,0x1002))
+        {
+          Store(HYSS, ATID)
+        }
+// AMI_OVERRIDE >>>
+        Store(One, _STA)
+      }
+
+      Method(_OFF, 0, Serialized)
+      {
+        //
+        // SA:InternalOnlyBegin
+        // 
+        Store("\_SB.PCI0.PEG0.PG00._OFF", Debug)
+        //
+        // SA:InternalOnlyEnd
+        //
+// AMI_OVERRIDE >>>
+//        \_SB.PCI0.PEG0.PEGP.HGOF()
+        \_SB.PCI0.PEG0.PEGP.SGOF()
+// AMI_OVERRIDE >>>
+        Store(Zero, _STA)
+      }
+    } //End of PowerResource(PG00, 0, 0)
+
+    Name(_PR0,Package(){PG00})
+    Name(_PR2,Package(){PG00})
+    Name(_PR3,Package(){PG00})
+
+//    //
+//    // Name: _PS0
+//    // Description: D0 Method for PEG0 slot device
+//    // Input: Nothing
+//    // Return: Nothing
+//    //
+//    Method(_PS0, 0, Serialized)
+//    {
+//      //
+//      // SA:InternalOnlyBegin
+//      // 
+//      Store("\_SB.PCI0.PEG0._PS0", Debug)
+//      //
+//      // SA:InternalOnlyEnd
+//      //
+//
+//      \_SB.PCI0.PEG0.PEGP.HGON()
+//    }
+//
+//    //
+//    // Name: _PS3
+//    // Description: D3 Method for PEG0 slot device
+//    // Input: Nothing
+//    // Return: Nothing
+//    //
+//    Method(_PS3, 0, Serialized)
+//    {
+//      //
+//      // SA:InternalOnlyBegin
+//      // 
+//      Store("\_SB.PCI0.PEG0._PS3", Debug)
+//      //
+//      // SA:InternalOnlyEnd
+//      //
+//
+//      \_SB.PCI0.PEG0.PEGP.HGOF()
+//    }
+
+    Method(_S0W, 0)
+    {
+      Return(4) //D3cold is supported
+    }
+
+    //-----------------------------------------
+    // Runtime Device Power Management - End
+    //-----------------------------------------
+
+    Device(PEGA) { // P.E.G. Device D0F1
+      Name(_ADR, 0x00000001)
+
+      OperationRegion(ACAP, PCI_Config, \EECP,0x14)
+      Field(ACAP,DWordAcc, NoLock,Preserve)
+      {
+        Offset(0x10),
+        LCT1,   16,  // Link Control register
+      }
+      Method(_PRW, 0) { Return(GPRW(0x09, 4)) } // can wakeup from S4 state
+    } // end "P.E.G. Device D0F1"
+}
+
+Scope(\_SB.PCI0.PEG0.PEGP)
+{
+    Name (ONOF, 0x1) //Endpoint On-Off flag status. Assume Endpoint is ON by default {1-ON, 0-OFF}
+    Name (IVID, 0xFFFF) //Invalid Vendor ID
+    Name (TCNT, 0)
+    Name (LDLY, 100) //100 ms
+    Name (ELCT, 0x00000000)
+    Name (HVID, 0x0000)
+    Name (HDID, 0x0000)
+    Name (FBDL, 0x0) //BndlPwrdnFirst
+    Name (MBDL, 0x0) //MaxBndlPwrdnCount
+    Name (CBDL, 0x0) //BndlPwrdnCount
+    Name (HSTR, 0x0) //HwStrap
+    Name (UULN, 0x0) //UnusedLanes
+    Name (INDX, 0x0)
+    Name (POFF, 0x0)
+    Name (PLEN, 0x0)
+    Name (PDAT, 0x0)
+    Name (WLSB, 0x0)
+    Name (WMSB, 0x0)
+    Name (DMLW, 0x0)
+    Name (DAT0, Buffer() {
+    //Offset    Length    Data
+	
+    //Save-Restore Any Controller fields
+    0xD8,0x0D,    0x4,    0x00,0x00,0x00,0x00,
+    0x00,0x09,    0x4,    0x00,0x00,0x00,0x00,
+    0x04,0x09,    0x4,    0x00,0x00,0x00,0x00,
+    0x08,0x09,    0x4,    0x00,0x00,0x00,0x00,
+    0x0C,0x09,    0x4,    0x00,0x00,0x00,0x00,
+    0x10,0x09,    0x4,    0x00,0x00,0x00,0x00,
+    0x0C,0x08,    0x4,    0x00,0x00,0x00,0x00,
+    0x20,0x09,    0x4,    0x00,0x00,0x00,0x00,
+    0x24,0x09,    0x4,    0x00,0x00,0x00,0x00,
+    0x28,0x09,    0x4,    0x00,0x00,0x00,0x00,
+    0x2C,0x09,    0x4,    0x00,0x00,0x00,0x00,
+    0x30,0x09,    0x4,    0x00,0x00,0x00,0x00,
+    0x2C,0x08,    0x4,    0x00,0x00,0x00,0x00,
+    0x40,0x09,    0x4,    0x00,0x00,0x00,0x00,
+    0x44,0x09,    0x4,    0x00,0x00,0x00,0x00,
+    0x48,0x09,    0x4,    0x00,0x00,0x00,0x00,
+    0x4C,0x09,    0x4,    0x00,0x00,0x00,0x00,
+    0x50,0x09,    0x4,    0x00,0x00,0x00,0x00,
+    0x4C,0x08,    0x4,    0x00,0x00,0x00,0x00,
+    0x60,0x09,    0x4,    0x00,0x00,0x00,0x00,
+    0x64,0x09,    0x4,    0x00,0x00,0x00,0x00,
+    0x68,0x09,    0x4,    0x00,0x00,0x00,0x00,
+    0x6C,0x09,    0x4,    0x00,0x00,0x00,0x00,
+    0x70,0x09,    0x4,    0x00,0x00,0x00,0x00,
+    0x6C,0x08,    0x4,    0x00,0x00,0x00,0x00,
+    0x80,0x09,    0x4,    0x00,0x00,0x00,0x00,
+    0x84,0x09,    0x4,    0x00,0x00,0x00,0x00,
+    0x88,0x09,    0x4,    0x00,0x00,0x00,0x00,
+    0x8C,0x09,    0x4,    0x00,0x00,0x00,0x00,
+    0x90,0x09,    0x4,    0x00,0x00,0x00,0x00,
+    0x8C,0x08,    0x4,    0x00,0x00,0x00,0x00,
+    0xA0,0x09,    0x4,    0x00,0x00,0x00,0x00,
+    0xA4,0x09,    0x4,    0x00,0x00,0x00,0x00,
+    0xA8,0x09,    0x4,    0x00,0x00,0x00,0x00,
+    0xAC,0x09,    0x4,    0x00,0x00,0x00,0x00,
+    0xB0,0x09,    0x4,    0x00,0x00,0x00,0x00,
+    0xAC,0x08,    0x4,    0x00,0x00,0x00,0x00,
+    0xC0,0x09,    0x4,    0x00,0x00,0x00,0x00,
+    0xC4,0x09,    0x4,    0x00,0x00,0x00,0x00,
+    0xC8,0x09,    0x4,    0x00,0x00,0x00,0x00,
+    0xCC,0x09,    0x4,    0x00,0x00,0x00,0x00,
+    0xD0,0x09,    0x4,    0x00,0x00,0x00,0x00,
+    0xCC,0x08,    0x4,    0x00,0x00,0x00,0x00,
+    0xE0,0x09,    0x4,    0x00,0x00,0x00,0x00,
+    0xE4,0x09,    0x4,    0x00,0x00,0x00,0x00,
+    0xE8,0x09,    0x4,    0x00,0x00,0x00,0x00,
+    0xEC,0x09,    0x4,    0x00,0x00,0x00,0x00,
+    0xF0,0x09,    0x4,    0x00,0x00,0x00,0x00,
+    0xEC,0x08,    0x4,    0x00,0x00,0x00,0x00,
+    0x30,0x0C,    0x4,    0x00,0x00,0x00,0x00,
+    0x00,0x0A,    0x4,    0x00,0x00,0x00,0x00,
+    0x04,0x0A,    0x4,    0x00,0x00,0x00,0x00,
+    0x08,0x0A,    0x4,    0x00,0x00,0x00,0x00,
+    0x0C,0x0A,    0x4,    0x00,0x00,0x00,0x00,
+    0xA0,0x0A,    0x4,    0x00,0x00,0x00,0x00,
+    0xA4,0x0A,    0x4,    0x00,0x00,0x00,0x00,
+    0xA8,0x0A,    0x4,    0x00,0x00,0x00,0x00,
+    0xAC,0x0A,    0x4,    0x00,0x00,0x00,0x00,
+    0xB0,0x0A,    0x4,    0x00,0x00,0x00,0x00,
+    0xB4,0x0A,    0x4,    0x00,0x00,0x00,0x00,
+    0xB8,0x0A,    0x4,    0x00,0x00,0x00,0x00,
+    0xBC,0x0A,    0x4,    0x00,0x00,0x00,0x00,
+    0xC0,0x0A,    0x4,    0x00,0x00,0x00,0x00,
+    0xC4,0x0A,    0x4,    0x00,0x00,0x00,0x00,
+    0xC8,0x0A,    0x4,    0x00,0x00,0x00,0x00,
+    0xCC,0x0A,    0x4,    0x00,0x00,0x00,0x00,
+    0xD0,0x0A,    0x4,    0x00,0x00,0x00,0x00,
+    0xD4,0x0A,    0x4,    0x00,0x00,0x00,0x00,
+    0xD8,0x0A,    0x4,    0x00,0x00,0x00,0x00,
+    0xDC,0x0A,    0x4,    0x00,0x00,0x00,0x00,
+    0xE0,0x0A,    0x4,    0x00,0x00,0x00,0x00,
+    0xE4,0x0A,    0x4,    0x00,0x00,0x00,0x00,
+    0xE8,0x0A,    0x4,    0x00,0x00,0x00,0x00,
+    0xEC,0x0A,    0x4,    0x00,0x00,0x00,0x00,
+    0xF0,0x0A,    0x4,    0x00,0x00,0x00,0x00,
+    0xF4,0x0A,    0x4,    0x00,0x00,0x00,0x00,
+    0xF8,0x0A,    0x4,    0x00,0x00,0x00,0x00,
+    0xFC,0x0A,    0x4,    0x00,0x00,0x00,0x00,
+    0x10,0x0A,    0x4,    0x00,0x00,0x00,0x00,
+    0x14,0x0A,    0x4,    0x00,0x00,0x00,0x00,
+    0x18,0x0A,    0x4,    0x00,0x00,0x00,0x00,
+    0x1C,0x0A,    0x4,    0x00,0x00,0x00,0x00,
+    0x20,0x0A,    0x4,    0x00,0x00,0x00,0x00,
+    0x24,0x0A,    0x4,    0x00,0x00,0x00,0x00,
+    0x28,0x0A,    0x4,    0x00,0x00,0x00,0x00,
+    0x2C,0x0A,    0x4,    0x00,0x00,0x00,0x00,
+    0x30,0x0A,    0x4,    0x00,0x00,0x00,0x00,
+    0x34,0x0A,    0x4,    0x00,0x00,0x00,0x00,
+    0x38,0x0A,    0x4,    0x00,0x00,0x00,0x00,
+    0x3C,0x0A,    0x4,    0x00,0x00,0x00,0x00,
+    0x40,0x0A,    0x4,    0x00,0x00,0x00,0x00,
+    0x44,0x0A,    0x4,    0x00,0x00,0x00,0x00,
+    0x48,0x0A,    0x4,    0x00,0x00,0x00,0x00,
+    0x4C,0x0A,    0x4,    0x00,0x00,0x00,0x00,
+    0x50,0x0A,    0x4,    0x00,0x00,0x00,0x00,
+    0x54,0x0A,    0x4,    0x00,0x00,0x00,0x00,
+    0x58,0x0A,    0x4,    0x00,0x00,0x00,0x00,
+    0x5C,0x0A,    0x4,    0x00,0x00,0x00,0x00,
+    0x60,0x0A,    0x4,    0x00,0x00,0x00,0x00,
+    0x64,0x0A,    0x4,    0x00,0x00,0x00,0x00,
+    0x68,0x0A,    0x4,    0x00,0x00,0x00,0x00,
+    0x6C,0x0A,    0x4,    0x00,0x00,0x00,0x00,
+    0x70,0x0A,    0x4,    0x00,0x00,0x00,0x00,
+    0x74,0x0A,    0x4,    0x00,0x00,0x00,0x00,
+    0x78,0x0A,    0x4,    0x00,0x00,0x00,0x00,
+    0x7C,0x0A,    0x4,    0x00,0x00,0x00,0x00,
+    0x80,0x0A,    0x4,    0x00,0x00,0x00,0x00,
+    0x84,0x0A,    0x4,    0x00,0x00,0x00,0x00,
+    0x88,0x0A,    0x4,    0x00,0x00,0x00,0x00,
+    0x8C,0x0A,    0x4,    0x00,0x00,0x00,0x00,
+    0x90,0x0A,    0x4,    0x00,0x00,0x00,0x00,
+    0x94,0x0A,    0x4,    0x00,0x00,0x00,0x00,
+    0x98,0x0A,    0x4,    0x00,0x00,0x00,0x00,
+    0x9C,0x0A,    0x4,    0x00,0x00,0x00,0x00,
+    0x18,0x09,    0x4,    0x00,0x00,0x00,0x00,
+    0x38,0x09,    0x4,    0x00,0x00,0x00,0x00,
+    0x58,0x09,    0x4,    0x00,0x00,0x00,0x00,
+    0x78,0x09,    0x4,    0x00,0x00,0x00,0x00,
+    0x98,0x09,    0x4,    0x00,0x00,0x00,0x00,
+    0xB8,0x09,    0x4,    0x00,0x00,0x00,0x00,
+    0xD8,0x09,    0x4,    0x00,0x00,0x00,0x00,
+    0xF8,0x09,    0x4,    0x00,0x00,0x00,0x00,
+
+    //Save-Restore Appropriate Controller fields
+    0x24,0x02,    0x4,    0x00,0x00,0x00,0x00,
+    0xf8,0x01,    0x4,    0x00,0x00,0x00,0x00,
+    0x60,0x02,    0x4,    0x00,0x00,0x00,0x00,
+    0x28,0x0C,    0x4,    0x00,0x00,0x00,0x00,
+    0x38,0x0C,    0x4,    0x00,0x00,0x00,0x00,
+    0x14,0x0D,    0x4,    0x00,0x00,0x00,0x00,
+    0x0C,0x00,    0x1,    0x00,
+    0x19,0x00,    0x1,    0x00,
+    0x1A,0x00,    0x1,    0x00,
+    0x1C,0x00,    0x1,    0x00,
+    0x1D,0x00,    0x1,    0x00,
+    0x20,0x00,    0x2,    0x00,0x00,
+    0x22,0x00,    0x2,    0x00,0x00,
+    0x24,0x00,    0x2,    0x00,0x00,
+    0x26,0x00,    0x2,    0x00,0x00,
+    0x28,0x00,    0x4,    0x00,0x00,0x00,0x00,
+    0x2C,0x00,    0x4,    0x00,0x00,0x00,0x00,
+    0x3C,0x00,    0x1,    0x00,
+    0x3D,0x00,    0x1,    0x00,
+    0x3E,0x00,    0x2,    0x00,0x00,
+    0x84,0x00,    0x4,    0x00,0x00,0x00,0x00,
+    0x8C,0x00,    0x4,    0x00,0x00,0x00,0x00,
+    0x92,0x00,    0x2,    0x00,0x00,
+    0x94,0x00,    0x4,    0x00,0x00,0x00,0x00,
+    0x98,0x00,    0x2,    0x00,0x00,
+    0xA2,0x00,    0x2,    0x00,0x00,
+    0xA8,0x00,    0x2,    0x00,0x00,
+    0xAC,0x00,    0x4,    0x00,0x00,0x00,0x00,
+    0xB0,0x00,    0x2,    0x00,0x00,
+    0xB4,0x00,    0x4,    0x00,0x00,0x00,0x00,
+    0xBC,0x00,    0x2,    0x00,0x00,
+    0xC8,0x00,    0x2,    0x00,0x00,
+    0xD0,0x00,    0x2,    0x00,0x00,
+    0xEC,0x00,    0x4,    0x00,0x00,0x00,0x00,
+    0x14,0x01,    0x4,    0x00,0x00,0x00,0x00,
+    0x44,0x01,    0x4,    0x00,0x00,0x00,0x00,
+    0x50,0x01,    0x4,    0x00,0x00,0x00,0x00,
+    0x58,0x01,    0x4,    0x00,0x00,0x00,0x00,
+    0x5C,0x01,    0x4,    0x00,0x00,0x00,0x00,
+    0xFC,0x01,    0x4,    0x00,0x00,0x00,0x00,
+    0x00,0x02,    0x4,    0x00,0x00,0x00,0x00,
+    0x04,0x02,    0x4,    0x00,0x00,0x00,0x00,
+    0x08,0x02,    0x4,    0x00,0x00,0x00,0x00,
+    0x28,0x02,    0x4,    0x00,0x00,0x00,0x00,
+    0x2C,0x02,    0x4,    0x00,0x00,0x00,0x00,
+    0x38,0x02,    0x4,    0x00,0x00,0x00,0x00,
+    0x40,0x02,    0x4,    0x00,0x00,0x00,0x00,
+    0x44,0x02,    0x4,    0x00,0x00,0x00,0x00,
+    0x50,0x02,    0x4,    0x00,0x00,0x00,0x00,
+    0x58,0x02,    0x4,    0x00,0x00,0x00,0x00,
+    0x5C,0x02,    0x4,    0x00,0x00,0x00,0x00,
+    0xD0,0x0C,    0x4,    0x00,0x00,0x00,0x00,
+    0x34,0x0D,    0x4,    0x00,0x00,0x00,0x00,
+    0xF4,0x00,    0x4,    0x00,0x00,0x00,0x00,
+    0xA0,0x0D,    0x4,    0x00,0x00,0x00,0x00,
+    0xA4,0x0D,    0x4,    0x00,0x00,0x00,0x00,
+    0xA8,0x0D,    0x4,    0x00,0x00,0x00,0x00,
+    0xAC,0x0D,    0x4,    0x00,0x00,0x00,0x00,
+    0xB0,0x0D,    0x4,    0x00,0x00,0x00,0x00,
+    0xB4,0x0D,    0x4,    0x00,0x00,0x00,0x00,
+    0xB8,0x0D,    0x4,    0x00,0x00,0x00,0x00,
+    0xBC,0x0D,    0x4,    0x00,0x00,0x00,0x00,
+    0xCC,0x01,    0x4,    0x00,0x00,0x00,0x00,
+    0x04,0x00,    0x2,    0x00,0x00,
+
+    //Final field
+    0xFF,0xFF,    0x4,    0xFF,0xFF,0xFF,0xFF  //Last data
+    })
+
+    Name (DAT1, Buffer() {
+    //Offset    Length    Data
+	
+    //Save-Restore Any Controller fields
+    0x06,0x00,    0x2,    0xFF,0xFF,
+    0x1E,0x00,    0x2,    0xFF,0xFF,
+    0xAA,0x00,    0x2,    0xFF,0xFF,
+    0xC0,0x00,    0x4,    0xFF,0xFF,0xFF,0xFF,
+    0xD2,0x00,    0x2,    0xFF,0xFF,
+    0xC4,0x01,    0x4,    0xFF,0xFF,0xFF,0xFF,
+    0xD0,0x01,    0x4,    0xFF,0xFF,0xFF,0xFF,
+    0xF0,0x01,    0x4,    0xFF,0xFF,0xFF,0xFF,
+    0x9C,0x0D,    0x4,    0xFF,0xFF,0xFF,0xFF,
+    0xB2,0x00,    0x2,    0xFF,0xFF,
+
+    //Final field
+    0xFF,0xFF,    0x4,    0xFF,0xFF,0xFF,0xFF  //Last data
+    })
+
+    OperationRegion (PCIS, PCI_Config, 0x00, 0xF0)
+    Field(PCIS, DWordAcc, Lock, Preserve)
+    {
+        Offset(0x0),
+        DVID, 16,
+        Offset(0x2C),
+        SVID, 16,
+        SDID, 16,
+        Offset(0x4C),
+        WVID, 16,
+        WDID, 16,
+    }        
+
+    OperationRegion( GPR, SystemIO, \GBAS, 0x60 )
+    Field( GPR, ByteAcc, Lock, Preserve )
+    {
+        Offset(0x0C),   // GPIO, Level, Bank 0
+        LVL0,   32,
+        Offset(0x38),   // GPIO, Level, Bank 1
+        LVL1,   32,
+        Offset(0x48),   // GPIO, Level, Bank 2
+        LVL2,   32,
+    }
+
+    OperationRegion(PCAP, PCI_Config, \EECP,0x14)
+    Field(PCAP,DWordAcc, NoLock,Preserve)
+    {
+        Offset(0x0C),                    // Link Capabilities Register
+        ,       4,
+        EMLW,   6,                       // 9:4, Max Link Width
+        Offset(0x10),                    
+        LCTL,   16,                      // Link Control register
+    }
+
+    Method (_INI)
+    {
+        Store (0x0, \_SB.PCI0.PEG0.PEGP._ADR)
+    }
+
+    //GetMaxBundles
+    Method(GMXB,0)
+    {
+        Store (PCFG, HSTR) //HwStrap
+        If (LEqual(HSTR, 3)) //SA_PEG_x16_x0_x0
+        {
+          Store (8, Local0)
+        }
+        Else 
+        {
+          Store (4, Local0)
+        }
+
+        Return(Local0)
+    }
+
+    //PowerUpAllBundles
+    Method(PUAB,0)
+    {
+        Store (0, FBDL) //BndlPwrdnFirst
+        Store (0, CBDL) //BndlPwrdnCount
+        Store (PCFG, HSTR) //HwStrap
+        If (LEqual(HSTR, 3)) //SA_PEG_x16_x0_x0
+        {
+          Store (0, FBDL)
+          Store (8, CBDL)
+        }
+        Else
+        {
+          If(LEqual(LREV,0))
+          {
+            Store (0, FBDL)
+            Store (4, CBDL)
+          }
+          Else
+          {
+            Store (4, FBDL)
+            Store (4, CBDL)
+          }
+        }
+
+        Store (1, INDX)
+        If (LNotEqual(CBDL,0))
+        {
+          While(LLessEqual(INDX, CBDL))
+          {
+            If(LEqual(FBDL,0))
+            {
+              Store (0, BSP1)
+            }
+            If(LEqual(FBDL,1))
+            {
+              Store (0, BSP2)
+            }
+            If(LEqual(FBDL,2))
+            {
+              Store (0, BSP3)
+            }
+            If(LEqual(FBDL,3))
+            {
+              Store (0, BSP4)
+            }
+            If(LEqual(FBDL,4))
+            {
+              Store (0, BSP5)
+            }
+            If(LEqual(FBDL,5))
+            {
+              Store (0, BSP6)
+            }
+            If(LEqual(FBDL,6))
+            {
+              Store (0, BSP7)
+            }
+            If(LEqual(FBDL,7))
+            {
+              Store (0, BSP8)
+            }
+            Increment (FBDL)
+            Increment (INDX)
+          }
+        }
+    } // End of Method(PUAB,0)
+
+    // PowerDownUnusedBundles
+    // Arg0 = BndlPwrdnCount
+    Method(PDUB,1)
+    {
+        Store (0, FBDL) //BndlPwrdnFirst
+        Store (Arg0, CBDL) //BndlPwrdnCount
+        If (LEqual(CBDL,0))
+        {
+          // All lanes are used. Do nothing
+          Return
+        }
+
+        If (LEqual(HSTR, 3)) //SA_PEG_x16_x0_x0
+        {
+          If(LEqual(LREV,0))
+          {
+            Store (Subtract(8, CBDL), FBDL) //8 - (UnusedLanes / 2)
+          }
+          Else
+          {
+            Store (0, FBDL)
+          }
+        }
+        Else
+        {
+          If(LEqual(LREV,0))
+          {
+            Store (Subtract(4, CBDL), FBDL) //4 - (UnusedLanes / 2)
+          }
+          Else
+          {
+            Store (4, FBDL)
+          }
+        }
+
+        Store (1, INDX)
+        While(LLessEqual(INDX, CBDL)) //< Check that bundles need to be powered down
+        {
+          If(LEqual(FBDL,0))
+          {
+            Store (1, BSP1)
+          }
+          If(LEqual(FBDL,1))
+          {
+            Store (1, BSP2)
+          }
+          If(LEqual(FBDL,2))
+          {
+            Store (1, BSP3)
+          }
+          If(LEqual(FBDL,3))
+          {
+            Store (1, BSP4)
+          }
+          If(LEqual(FBDL,4))
+          {
+            Store (1, BSP5)
+          }
+          If(LEqual(FBDL,5))
+          {
+            Store (1, BSP6)
+          }
+          If(LEqual(FBDL,6))
+          {
+            Store (1, BSP7)
+          }
+          If(LEqual(FBDL,7))
+          {
+            Store (1, BSP8)
+          }
+          Increment (FBDL)
+          Increment (INDX)
+        }
+    } // End of Method(PDUB,0)
+
+    Method(SPP0,0)
+    {
+        Store (0, INDX)
+        While (1)
+        {
+            Store (DerefOf (Index(DAT0, INDX)), WLSB)
+            Increment (INDX) //Offset is 2 bytes long <First byte-LSB>
+            Store (DerefOf (Index(DAT0, INDX)), WMSB)
+            Increment (INDX) //Offset is 2 bytes long <Second byte-MSB>
+            Store (Or (ShiftLeft (WMSB, 8), WLSB), POFF)
+            Store (DerefOf (Index(DAT0, INDX)), PLEN)
+            Increment (INDX) //Length is 1 byte long
+
+            If(LEqual(POFF,0xFFFF))
+            {
+               Break
+            }
+
+            While (LGreater(PLEN, 0))
+            {
+               Store(RBP0(POFF), Index(DAT0, INDX))
+               Increment (INDX)
+               Increment (POFF)
+               Decrement (PLEN)
+            }
+        }
+    } // End of Method(SPP0,0)
+
+    Method(RPP0,0)
+    {
+        Store (0, INDX)
+        While (1)
+        {
+            Store (DerefOf (Index(DAT0, INDX)), WLSB)
+            Increment (INDX) //Offset is 2 bytes long <First byte-LSB>
+            Store (DerefOf (Index(DAT0, INDX)), WMSB)
+            Increment (INDX) //Offset is 2 bytes long <Second byte-MSB>
+            Store (Or (ShiftLeft (WMSB, 8), WLSB), POFF)
+            Store (DerefOf (Index(DAT0, INDX)), PLEN)
+            Increment (INDX) //Length is 1 byte long
+
+            If(LEqual(POFF,0xFFFF))
+            {
+               Break
+            }
+
+            While (LGreater(PLEN, 0))
+            {
+               WBP0(POFF, DerefOf (Index(DAT0, INDX)))
+               Increment (INDX)
+               Increment (POFF)
+               Decrement (PLEN)
+            }
+        }
+    } // End of Method(RPP0,0)
+
+    Method(CLP0,0)
+    {
+        Store (0, INDX)
+        While (1)
+        {
+            Store (DerefOf (Index(DAT1, INDX)), WLSB)
+            Increment (INDX) //Offset is 2 bytes long <First byte-LSB>
+            Store (DerefOf (Index(DAT1, INDX)), WMSB)
+            Increment (INDX) //Offset is 2 bytes long <Second byte-MSB>
+            Store (Or (ShiftLeft (WMSB, 8), WLSB), POFF)
+            Store (DerefOf (Index(DAT1, INDX)), PLEN)
+            Increment (INDX) //Length is 1 byte long
+
+            If(LEqual(POFF,0xFFFF))
+            {
+               Break
+            }
+
+            While (LGreater(PLEN, 0))
+            {
+               WBP0(POFF, DerefOf (Index(DAT1, INDX)))
+               Increment (INDX)
+               Increment (POFF)
+               Decrement (PLEN)
+            }
+        }
+    } // End of Method(CLP0,0)
+
+// AMI CHANGE BEGIN. 
+    Method(SGON,0,Serialized)
+//    Method(HGON,0,Serialized)
+// AMI CHANGE END. 
+    {
+        //
+        // SA:InternalOnlyBegin
+        // 
+        P8XH(0,0xD6)
+        P8XH(1,0x00)
+        Store("\_SB.PCI0.PEG0.PEGP.HGON", Debug)
+        //
+        // SA:InternalOnlyEnd
+        //
+
+        If (LEqual(CCHK(1), 0))
+        {
+          //
+          // SA:InternalOnlyBegin
+          // 
+          P8XH(0,0xD6)
+          P8XH(1,0xC0)
+          Store("\_SB.PCI0.PEG0.PEGP.HGON is not allowed to execute ", Debug)
+          //
+          // SA:InternalOnlyEnd
+          // 
+          Return ()
+        }
+
+        Store(1, ONOF) //Indicate Endpoint is in ON state
+
+        //Power on the dGPU card
+        SGPO(HLRS, 1)                  //Assert dGPU_HOLD_RST#
+        SGPO(PWEN, 1)                  //Assert dGPU_PWR_EN#
+
+//        While(LNotEqual(SGPI(PWOK),1)) //Wait until dGPU_PWROK=1
+//        {
+//                Sleep(1)                
+//        }
+
+        Sleep(300)                     // Wait for 300ms if dGPU_PWROK has h/w issues
+        
+        SGPO(HLRS, 0)                  //Deassert dGPU_HOLD_RST#
+        Sleep(100)                     // Wait for 100ms
+        
+        // Software clears BIOS_RESET_CPL.C7_ALLOWED
+        If (LGreaterEqual(PCSL, 4)) //C7 or above
+        {
+          If (LEqual(SC7A, 0x01)) //Run-time C7 Allowed feature setup value = Enabled
+          {
+            C7OK(0)
+
+            // Restore the PEG0 PCIE registers
+            RPP0()
+
+            // Clear the PEG0 errors
+            CLP0()
+          }
+        }
+
+        //Program AFEOVR.RXSQDETOVR
+        //PCIe link disable for Switchable GFx
+        //Additional Power savings: Set 0:1:0 0xc20 BIT4 = 0 & BIT5 = 0
+        Store(0, AFES)
+
+        //Program BND*SPARE.BNDL_PWRDN
+        //PowerOff unused bundles for PEGs
+        //SA:RestrictedContent Ref: HSW_PCIe_HAS_1.0.docx [Table 15 - Bifurcation and reversal port and pin mappings]
+        If (LGreaterEqual(And(PNHM, 0xF), 0x3)) //(CpuSteppingId >= EnumHswC0)
+        {
+          If (LNotEqual(P0UB, 0x00))
+          {
+            //PowerUpAllBundles
+            PUAB()
+
+            //Get BndlPwrdnCount
+            If (LEqual (P0UB, 0xFF)) //AUTO
+            {
+               If (LGreater(CMLW, DMLW))
+               {
+                 Subtract (CMLW, DMLW, UULN) //UnusedLanes
+               } 
+               Else 
+               {
+                 Store (0, UULN) //UnusedLanes
+               }
+               Store (Divide(UULN,2), CBDL) //BndlPwrdnCount
+            } 
+            ElseIf (LNotEqual (P0UB, 0x00)) //1...8 bundles
+            { 
+               Store (P0UB, CBDL) //BndlPwrdnCount
+            }
+
+            //Get MaxBndlPwrdnCount
+            Store(GMXB(), MBDL)
+
+            If (LGreater(CBDL, MBDL))
+            {
+               Store(MBDL, CBDL)
+            }
+
+            //PowerDownUnusedBundles
+            PDUB(CBDL)
+          }
+        }
+
+// AMI CHANGE BEGIN. 
+        // Enable controller initial training
+        Store(1, TREN)
+// AMI CHANGE END. 
+        //Enable x16 Link
+        //This bit should already be set to 0 in the _Off method. But do it anyway.
+        Store(0,LNKD)
+//AMI_OVERRIDE -->>  When runnign a long run test (S3,S4,or _on/_off) with SG on two chips platform, it may happen to BSOD 0x9F. It got different fail rate on different platform.
+        //wait until link has trained to x16. Verify        
+        While(LLess(LNKS,7))
+        {
+                Sleep(1)
+        }
+//AMI_OVERRIDE --<< When runnign a long run test (S3,S4,or _on/_off) with SG on two chips platform, it may happen to BSOD 0x9F. It got different fail rate on different platform.
+
+// AMI CHANGE BEGIN. 
+        // Enable controller initial training
+        //Store(1, TREN)
+// AMI CHANGE END. 
+//AMI_OVERRIDE -->>  When runnign a long run test (S3,S4,or _on/_off) with SG on two chips platform, it may happen to BSOD 0x9F. It got different fail rate on different platform.
+//        // Wait until the VC negotiation is complete     
+//        Store(0, TCNT)
+//        While(LLess(TCNT, LDLY))
+//        {
+//          If(LEqual(VCNP,0))
+//          {
+//             Break
+//          }
+//
+//         Sleep(16) //In some OS one tick is equal to 1/64 second (15.625ms)
+//          Add(TCNT, 16, TCNT)
+//        }  
+//AMI_OVERRIDE --<<  When runnign a long run test (S3,S4,or _on/_off) with SG on two chips platform, it may happen to BSOD 0x9F. It got different fail rate on different platform.
+
+        // Re-store the DGPU SSID
+        Store(HVID,WVID)
+        Store(HDID,WDID)
+
+        // Re-store the Link Control register - Common Clock Control and ASPM
+        Or(And(ELCT,0x0043),And(LCTL,0xFFBC),LCTL)
+        Or(And(ELCT,0x0043),And(\_SB.PCI0.PEG0.PEGA.LCT1,0xFFBC),\_SB.PCI0.PEG0.PEGA.LCT1)
+// AMI CHANGE BEGIN. 
+//        Return ()
+//    }
+//
+//    Method(_ON,0,Serialized)
+//    {
+        //
+        // SA:InternalOnlyBegin
+        // 
+        Store("\_SB.PCI0.PEG0.PEGP._ON", Debug)
+        //
+        // SA:InternalOnlyEnd
+        //
+
+//        HGON()
+// AMI CHANGE END
+        //Ask OS to do a PnP rescan
+// AMI CHANGE BEGIN. 
+//        Notify(\_SB.PCI0.PEG0,0)
+// AMI CHANGE END. 
+
+// AMI CHANGE BEGIN.
+        Return (1)                      
+// AMI CHANGE END.
+    }
+
+// AMI CHANGE BEGIN. 
+//    Method(HGOF,0,Serialized)
+    Method(SGOF,0,Serialized)
+// AMI CHANGE END. 
+    {
+        //
+        // SA:InternalOnlyBegin
+        // 
+        P8XH(0,0xD6)
+        P8XH(1,0x0F)
+        Store("\_SB.PCI0.PEG0.PEGP.HGOF", Debug)
+        //
+        // SA:InternalOnlyEnd
+        //
+
+        If (LEqual(CCHK(0), 0))
+        {
+          //
+          // SA:InternalOnlyBegin
+          // 
+          P8XH(0,0xD6)
+          P8XH(1,0xCF)
+          Store("\_SB.PCI0.PEG0.PEGP.HGOF is not allowed to execute ", Debug)
+          //
+          // SA:InternalOnlyEnd
+          // 
+          Return ()
+        }
+
+        Store(0, ONOF) //Indicate Endpoint is in OFF state
+
+        // Save the Link Control register
+        Store(LCTL,ELCT)
+
+        // Save the DGPU SSID
+        Store(SVID,HVID)
+        Store(SDID,HDID)
+
+        // Save the Endpoint Max Link Width
+        Store(EMLW,DMLW)
+
+        // Software sets BIOS_RESET_CPL.C7_ALLOWED
+        If (LGreaterEqual(PCSL, 4)) //C7 or above
+        {
+          If (LEqual(SC7A, 0x01)) //Run-time C7 Allowed feature setup value = Enabled
+          {
+            // Save the PEG0 PCIE registers
+            SPP0()
+          }
+        }
+
+        //Force disable the x16 link
+        Store(1, LNKD)
+
+        //Wait till link is actually in disabled state
+        Store(0, TCNT)
+        While(LLess(TCNT, LDLY))
+        {
+          If(LEqual(LNKS,0))
+          {
+             Break
+          }
+
+          Sleep(16) //In some OS one tick is equal to 1/64 second (15.625ms)
+          Add(TCNT, 16, TCNT)
+        }
+//AMI_OVERRIDE -->>  When runnign a long run test (S3,S4,or _on/_off) with SG on two chips platform, it may happen to BSOD 0x9F. It got different fail rate on different platform.
+        While(LNotEqual(LNKS,0))
+        {
+            Sleep(1)
+        }
+//AMI_OVERRIDE --<<  When runnign a long run test (S3,S4,or _on/_off) with SG on two chips platform, it may happen to BSOD 0x9F. It got different fail rate on different platform.
+
+        //Program AFEOVR.RXSQDETOVR
+        //PCIe link disable for Switchable GFx
+        //Additional Power savings: Set 0:1:0 0xc20 BIT4 = 0 & BIT5 = 1
+        Store(2, AFES)
+
+        // PowerOff all bundles for PEGs
+        // Program BND*SPARE.BNDL_PWRDN
+        // SA:RestrictedContent Ref: HSW_PCIe_HAS_1.0.docx [Table 15 - Bifurcation and reversal port and pin mappings]
+        If (LGreaterEqual(And(PNHM, 0xF), 0x3)) //(CpuSteppingId >= EnumHswC0)
+        {
+          If (LNotEqual(P0UB, 0x00))
+          {
+            //Get MaxBndlPwrdnCount
+            Store(GMXB(), MBDL)
+
+            //PowerDownUnusedBundles
+            PDUB(MBDL)
+          }
+        }
+
+        // Software sets BIOS_RESET_CPL.C7_ALLOWED
+        If (LGreaterEqual(PCSL, 4)) //C7 or above
+        {
+          If (LEqual(SC7A, 0x01)) //Run-time C7 Allowed feature setup value = Enabled
+          {
+            C7OK(1)
+          }
+        }
+
+        //Power-off the dGPU card
+        SGPO(HLRS, 1)                   // Assert dGPU_HOLD_RST# (PERST#)
+        SGPO(PWEN, 0)                   // Deassert dGPU_PWR_EN#                
+// AMI CHANGE BEGIN. 
+//        Return ()
+//    }
+//       
+//    Method(_OFF,0,Serialized)
+//    {
+        //
+        // SA:InternalOnlyBegin
+        // 
+        Store("\_SB.PCI0.PEG0.PEGP._OFF", Debug)
+        //
+        // SA:InternalOnlyEnd
+        //
+
+//        HGOF()
+//
+// AMI CHANGE BEGIN. 
+        //Ask OS to do a PnP rescan
+// AMI CHANGE BEGIN. 
+//        Notify(\_SB.PCI0.PEG0,0)
+// AMI CHANGE END. 
+
+// AMI CHANGE BEGIN
+        Return (0)
+// AMI CHANGE END.
+    }
+
+    Method(EPON, 0, Serialized)
+    {
+      Store(1, ONOF) //Indicate Endpoint is in ON state
+
+      Return ()
+    }
+            
+// AMI CHANGE BEGIN. 
+//    Method(_STA,0,Serialized)
+    Method(SGST,0,Serialized)
+// AMI CHANGE END. 
+    {
+      //
+      // Check SGMode and dGPU Present Detect GPIO for SG system
+      //
+      If(And(SGMD,0x0F))
+      {
+        If(LNotEqual(SGGP,0x01))
+        {
+           Return(0x0F)
+        }
+        // Check dGPU_PWROK to detect dGPU.
+        If(LEqual(SGPI(PWOK),1))  
+        {
+          Return(0x0F)
+        }
+        Return(0x00)
+      }
+
+      //
+      // For non-SG system check for valid Vendor Id
+      //
+      If(LNotEqual(DVID,0xFFFF))
+      {
+          Return(0x0F)
+      }
+      Return(0x00)
+    }
+
+
+    Method(_DOD,0)
+    {
+        Return (\_SB.PCI0.GFX0._DOD())
+    }
+
+
+    Device(DD01)
+    {
+            Method(_ADR,0,Serialized)
+            {
+                    Return(\_SB.PCI0.GFX0.DD01._ADR())
+            }
+
+            // Device Current State.
+            Method(_DCS,0)
+            {
+
+            }
+
+            // Device Get State.
+
+            Method(_DGS,0)
+            {
+                    // Return the Next State.
+                    Return(\_SB.PCI0.GFX0.DD01._DGS())
+            }
+
+            // Device Set State.
+
+            // _DSS Table:
+            //
+            //  BIT31   BIT30   Execution
+            //  0       0       Don't implement.
+            //  0       1       Cache change.  Nothing to Implement.
+            //  1       0       Don't Implement.
+            //  1       1       Display Switch Complete.  Implement.
+
+            Method(_DSS,1)
+            {
+                    // Do nothing here in the OpRegion model.  OEMs may choose to
+                    // update internal state if necessary.
+            }
+    }
+
+    Device(DD02)
+    {
+            Method(_ADR,0,Serialized)
+            {
+                    Return(\_SB.PCI0.GFX0.DD02._ADR())
+            }
+
+            // Device Current State.
+
+            Method(_DCS,0)
+            {
+                    // Get the Current Display State.
+                    Return(\_SB.PCI0.GFX0.DD02._DCS())
+            }
+
+            // Device Get State.
+
+            Method(_DGS,0)
+            {
+                    // Return the Next State.
+                    Return(\_SB.PCI0.GFX0.DD02._DGS())
+            }
+
+            // Device Set State.
+
+            Method(_DSS,1)
+            {
+                    // Do nothing here in the OpRegion model.  OEMs may choose to
+                    // update internal state if necessary.
+            }
+
+/*
+            Method(_DDC,1)
+            {
+                    If(Lor(LEqual(\_SB.PCI0.GFX0.PHED,1),LEqual(\_SB.PCI0.GFX0.PHED,2)))
+                    {
+                        Name(DDC2,Buffer (256) {0x0})
+                        Store(\_SB.PCI0.GFX0.BDDC,DDC2)
+                        Return(DDC2)
+                    }
+                    Return(Buffer(256){0x0})
+            }
+*/
+            Method(_BCL,0)
+            {
+                    Return(\_SB.PCI0.GFX0.DD02._BCL())               
+            }
+
+            Method(_BQC,0)
+            {
+                    Return(\_SB.PCI0.GFX0.DD02._BQC())
+            }
+            
+            Method(_BCM,1)
+            {
+                    Return(\_SB.PCI0.GFX0.DD02._BCM(Arg0))
+            }
+
+    }
+
+    Device(DD03)
+    {
+            Method(_ADR,0,Serialized)
+            {
+                    Return(\_SB.PCI0.GFX0.DD03._ADR())
+            }
+
+            // Device Current State.
+
+            Method(_DCS,0)
+            {
+                    // Get the Current Display State.
+            }
+
+            // Device Get State.
+
+            Method(_DGS,0)
+            {
+                    // Return the Next State.
+                    Return(\_SB.PCI0.GFX0.DD03._DGS())
+            }
+
+            // Device Set State.
+
+            Method(_DSS,1)
+            {
+                    // Do nothing here in the OpRegion model.  OEMs may choose to
+                    // update internal state if necessary.
+            }
+    }
+
+    Device(DD04)
+    {
+            Method(_ADR,0,Serialized)
+            {
+                    Return(\_SB.PCI0.GFX0.DD04._ADR())
+            }
+
+            // Device Current State.
+
+            Method(_DCS,0)
+            {
+                    // Get the Current Display State.
+            }
+
+            // Device Get State.
+
+            Method(_DGS,0)
+            {
+                    // Return the Next State.
+                    Return(\_SB.PCI0.GFX0.DD04._DGS())
+            }
+
+            // Device Set State.
+
+            Method(_DSS,1)
+            {
+                    // Do nothing here in the OpRegion model.  OEMs may choose to
+                    // update internal state if necessary.
+            }
+            
+    }
+
+    Device(DD05)
+    {
+            Method(_ADR,0,Serialized)
+            {
+                    Return(\_SB.PCI0.GFX0.DD05._ADR())
+            }
+
+            // Device Current State.
+
+            Method(_DCS,0)
+            {
+                    // Get the Current Display State.
+            }
+
+            // Device Get State.
+
+            Method(_DGS,0)
+            {
+                    // Return the Next State.
+                    Return(\_SB.PCI0.GFX0.DD05._DGS())
+            }
+
+            // Device Set State.
+
+            Method(_DSS,1)
+            {
+                    // Do nothing here in the OpRegion model.  OEMs may choose to
+                    // update internal state if necessary.
+            }
+    }
+
+    Device(DD06)
+    {
+            Method(_ADR,0,Serialized)
+            {
+                    Return(\_SB.PCI0.GFX0.DD06._ADR())
+            }
+
+            // Device Current State.
+
+            Method(_DCS,0)
+            {
+                    // Get the Current Display State.
+            }
+
+            // Device Get State.
+
+            Method(_DGS,0)
+            {
+                    // Return the Next State.
+                    Return(\_SB.PCI0.GFX0.DD06._DGS())
+            }
+
+            // Device Set State.
+
+            Method(_DSS,1)
+            {
+                    // Do nothing here in the OpRegion model.  OEMs may choose to
+                    // update internal state if necessary.
+            }
+    }
+    
+    Device(DD07)
+    {
+            Method(_ADR,0,Serialized)
+            {
+                    Return(\_SB.PCI0.GFX0.DD07._ADR())
+            }
+
+            // Device Current State.
+
+            Method(_DCS,0)
+            {
+                    // Get the Current Display State.
+            }
+
+            // Device Get State.
+
+            Method(_DGS,0)
+            {
+                    // Return the Next State.
+                    Return(\_SB.PCI0.GFX0.DD07._DGS())
+            }
+
+            // Device Set State.
+
+            Method(_DSS,1)
+            {
+                    // Do nothing here in the OpRegion model.  OEMs may choose to
+                    // update internal state if necessary.
+            }
+    }
+
+    Device(DD08)
+    {
+            Method(_ADR,0,Serialized)
+            {
+                    Return(\_SB.PCI0.GFX0.DD08._ADR())
+            }
+
+            // Device Current State.
+
+            Method(_DCS,0)
+            {
+                    // Get the Current Display State.
+            }
+
+            // Device Get State.
+
+            Method(_DGS,0)
+            {
+                    // Return the Next State.
+                    Return(\_SB.PCI0.GFX0.DD08._DGS())
+            }
+
+            // Device Set State.
+
+            Method(_DSS,1)
+            {
+                    // Do nothing here in the OpRegion model.  OEMs may choose to
+                    // update internal state if necessary.
+            }
+    }
+  // GPIO Read
+  // Arg0 = GPIO No.
+  Method (SGPI,1,Serialized)
+  {
+    If(And(SGMD,0x0F))
+    {
+      If(LEqual(SGGP,0x01))
+      {
+        ShiftRight (Arg0, 7, Local1)
+        And(Arg0, 0x7F, Arg0)   
+
+        If (LLess(Arg0,0x20))
+        {
+          Store(\_SB.PCI0.PEG0.PEGP.LVL0, Local0)
+          ShiftRight(Local0, Arg0, Local0)
+        }
+        ElseIf (LLess(Arg0,0x40))
+        {
+          Store(\_SB.PCI0.PEG0.PEGP.LVL1, Local0)
+          ShiftRight(Local0, Subtract(Arg0,0x20), Local0)
+        }
+        Else
+        {
+          Store(\_SB.PCI0.PEG0.PEGP.LVL2, Local0)
+          ShiftRight(Local0, Subtract(Arg0,0x40), Local0)
+        }
+
+        // 
+        // Check if Active Low
+        //
+        If (LEqual(Local1,0))
+        {
+          Not(Local0, Local0)
+        }
+
+        Return(And(Local0,0x01))
+      }
+    }
+	
+    Return(0)
+  }
+
+  // GPIO Write
+  // Arg0 = GPIO No.
+  // Arg1 = Value (0/1)
+  Method (SGPO,2,Serialized)
+  {
+    If(And(SGMD,0x0F))
+    {
+      If(LEqual(SGGP,0x01))
+      {
+        ShiftRight (Arg0, 7, Local3)
+        And(Arg0, 0x7F, Arg0)   
+
+        // 
+        // Check if Active Low
+        //
+        If (LEqual(Local3,0))
+        {
+          Not (Arg1, Local3)
+          And (Local3, 0x01, Local3)
+        }
+        Else 
+        {
+          And (Arg1, 0x01, Local3)
+        }
+        If (LLess(Arg0,0x20))
+        {
+          ShiftLeft(Local3, Arg0, Local0)
+          ShiftLeft(0x00000001, Arg0, Local1)
+          And(\_SB.PCI0.PEG0.PEGP.LVL0, Not(Local1), Local2)
+          Or(Local2, Local0, \_SB.PCI0.PEG0.PEGP.LVL0)
+        }
+        ElseIf (LLess(Arg0,0x40))
+        {
+          ShiftLeft(Local3, Subtract(Arg0,0x20), Local0)
+          ShiftLeft(0x00000001, Subtract(Arg0,0x20), Local1)
+          And(\_SB.PCI0.PEG0.PEGP.LVL1, Not(Local1), Local2)
+          Or(Local2, Local0, \_SB.PCI0.PEG0.PEGP.LVL1)
+        }
+        Else
+        {
+          ShiftLeft(Local3, Subtract(Arg0,0x40), Local0)
+          ShiftLeft(0x00000001, Subtract(Arg0,0x40), Local1)
+          And(\_SB.PCI0.PEG0.PEGP.LVL2, Not(Local1), Local2)
+          Or(Local2, Local0, \_SB.PCI0.PEG0.PEGP.LVL2)
+        }
+        Return(1)
+      }
+    }
+	
+    Return(1)
+  }
+
+  //
+  // Name: CCHK
+  // Description: Function to check whether _ON/_OFF sequence is allowed to execute for the given PEG0 controller or not
+  // Input: Arg0 -> 0 means _OFF sequence, 1 means _ON sequence
+  // Return: 0 - Don't execute the flow, 1 - Execute the flow
+  //
+  Method(CCHK,1)
+  {
+    //
+    // SA:InternalOnlyBegin
+    //
+    Store("CCHK : ", Debug)
+    If(LEqual(Arg0, 0))
+    {
+      Store("_OFF sequence condition check : ", Debug)
+    }
+    ElseIf(LEqual(Arg0, 1))
+    {
+      Store("_ON sequence condition check : ", Debug)
+    }
+    //
+    // SA:InternalOnlyEnd
+    //
+
+    //Check for PEG0 controller presence
+    If(LEqual(PVID, IVID))
+    {
+      //
+      // SA:InternalOnlyBegin
+      //
+      Store("Don't execut the flow. Failed criteria: PEG0 controller is not present", Debug)
+      //
+      // SA:InternalOnlyEnd
+      //
+
+      Return(0)
+    }
+
+    //If Endpoint is not present[already disabled] before executing _OFF then don't call the _OFF method
+    //If Endpoint is present[already enabled] before executing _ON then don't call the _ON method
+    If(LEqual(Arg0, 0))
+    {
+      //_OFF sequence condition check
+      If(LEqual(ONOF, 0))
+      {
+        //
+        // SA:InternalOnlyBegin
+        //
+        Store("Don't execut the flow. Failed criteria: Endpoint is not present[already disabled]", Debug)
+        //
+        // SA:InternalOnlyEnd
+        //
+
+        Return(0)
+      }
+    }
+    ElseIf(LEqual(Arg0, 1))
+    {
+      //_ON sequence condition check
+      If(LEqual(ONOF, 1))
+      {
+        //
+        // SA:InternalOnlyBegin
+        //
+        Store("Don't execut the flow. Failed criteria: Endpoint is present[already enabled]", Debug)
+        //
+        // SA:InternalOnlyEnd
+        //
+
+        Return(0)
+      }
+    }
+
+    //
+    // SA:InternalOnlyBegin
+    //
+    Store("Execute the flow", Debug)
+    //
+    // SA:InternalOnlyEnd
+    //
+
+    Return(1)
+  } // End of Method(CCHK,1)
+
+}
diff --git a/ReferenceCode/Chipset/SystemAgent/AcpiTables/SwitchableGraphics/Peg/SgSsdt.asl b/ReferenceCode/Chipset/SystemAgent/AcpiTables/SwitchableGraphics/Peg/SgSsdt.asl
new file mode 100644
index 0000000..9d4e1d1
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/AcpiTables/SwitchableGraphics/Peg/SgSsdt.asl
@@ -0,0 +1,45 @@
+/**************************************************************************;
+;*                                                                        *;
+;*    Intel Confidential                                                  *;
+;*                                                                        *;
+;*    Intel Corporation - SG Reference Code                               *;
+;*    Family of Customer Reference Boards.                                *;
+;*                                                                        *;
+;*                                                                        *;
+;*    Copyright (c) 2010 - 2012 Intel Corporation. All rights reserved    *;
+;*    This software and associated documentation (if any) is furnished    *;
+;*    under a license and may only be used or copied in accordance        *;
+;*    with the terms of the license. Except as permitted by such          *;
+;*    license, no part of this software or documentation may be           *;
+;*    reproduced, stored in a retrieval system, or transmitted in any     *;
+;*    form or by any means without the express written consent of         *;
+;*    Intel Corporation.                                                  *;
+;*                                                                        *;
+;*                                                                        *;
+;**************************************************************************/
+/*++
+  This file contains an 'Intel Peripheral Driver' and is
+  licensed for Intel CPUs and chipsets under the terms of your  
+  license agreement with Intel or your vendor.  This file may   
+  be modified by the user, subject to additional terms of the   
+  license agreement                                             
+--*/
+
+DefinitionBlock (
+    "Sg.aml",
+    "SSDT",
+    1,
+    "SgRef",
+    "SgPeg",
+    0x1000
+    )
+{
+  External(P8XH, MethodObj) 
+  External(GPRW, MethodObj) 
+
+// AMI MODIFY BEGIN
+//  Include("SgIgpu.ASL")
+//  Include("SgDgpu.ASL")
+#include <SgDgpu.ASL>
+// AMI MODIFY END
+}
diff --git a/ReferenceCode/Chipset/SystemAgent/BdatAccessHandler/Dxe/BdatAccessHandler.c b/ReferenceCode/Chipset/SystemAgent/BdatAccessHandler/Dxe/BdatAccessHandler.c
new file mode 100644
index 0000000..4894c8f
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/BdatAccessHandler/Dxe/BdatAccessHandler.c
@@ -0,0 +1,75 @@
+/** @file
+  This code makes the BIOS Data structure available via standard ACPI mechanisms.
+
+@copyright
+  Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement
+**/
+
+#include "BdatAccessHandler.h"
+
+STATIC EFI_ACPI_TABLE_PROTOCOL  *AcpiTable;
+
+/**
+  Entry point of the Bdat Access Handler.
+
+  @param[in] ImageHandle   EFI_HANDLE: A handle for the image that is initializing this driver
+  @param[in] SystemTable   EFI_SYSTEM_TABLE: A pointer to the EFI system table
+
+  @retval EFI_SUCCESS:              Driver initialized successfully
+  @exception EFI_UNSUPPORTED:          A needed driver was not located
+  @retval EFI_OUT_OF_RESOURCES:     Could not allocate needed resources
+**/
+EFI_STATUS
+BdatAccessHandler (
+  IN EFI_HANDLE           ImageHandle,
+  IN EFI_SYSTEM_TABLE     *SystemTable
+  )
+{
+  EFI_STATUS                      Status;
+  VOID                            *HobList;
+  DXE_PLATFORM_SA_POLICY_PROTOCOL *DxePlatformSaPolicy;
+
+  ///
+  /// Check if the BDAT ACPI table support is enabled in Setup, if not then exit.
+  /// Get the platform setup policy.
+  ///
+  Status = gBS->LocateProtocol (&gDxePlatformSaPolicyGuid, NULL, (VOID **) &DxePlatformSaPolicy);
+  ASSERT_EFI_ERROR (Status);
+
+  ///
+  /// Get the start of the HOBs.
+  ///
+  Status = EfiGetSystemConfigurationTable (&gEfiHobListGuid, &HobList);
+  ASSERT_EFI_ERROR (Status);
+  if (EFI_ERROR (Status)) {
+    return EFI_UNSUPPORTED;
+  }
+  ///
+  /// Locate ACPI table protocol
+  ///
+  Status = gBS->LocateProtocol (&gEfiAcpiTableProtocolGuid, NULL, (VOID **) &AcpiTable);
+  ASSERT_EFI_ERROR (Status);
+  ASSERT (AcpiTable != NULL);
+  if (EFI_ERROR (Status)) {
+    return EFI_OUT_OF_RESOURCES;
+  }
+  BdatRmtHandler (DxePlatformSaPolicy, HobList, AcpiTable);
+  ///
+  /// ASSERT_EFI_ERROR (Status);
+  ///
+  return Status;
+}
diff --git a/ReferenceCode/Chipset/SystemAgent/BdatAccessHandler/Dxe/BdatAccessHandler.cif b/ReferenceCode/Chipset/SystemAgent/BdatAccessHandler/Dxe/BdatAccessHandler.cif
new file mode 100644
index 0000000..db14005
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/BdatAccessHandler/Dxe/BdatAccessHandler.cif
@@ -0,0 +1,15 @@
+<component>
+	name = "BdatAccessHandler"
+	category = ModulePart
+	LocalRoot = "ReferenceCode\Chipset\SystemAgent\BdatAccessHandler\Dxe\"
+	RefName = "BdatAccessHandler"
+[files]
+"BdatAccessHandler.sdl"	
+"BdatAccessHandler.mak"	
+"BdatAccessHandler.c"	
+"BdatAccessHandler.h"	
+"BdatAccessHandler.dxs"	
+"BdatAccessHandler.inf"	
+"BdatRmtHandler.c"
+"BdatRmtHandler.h"
+<endComponent>
diff --git a/ReferenceCode/Chipset/SystemAgent/BdatAccessHandler/Dxe/BdatAccessHandler.dxs b/ReferenceCode/Chipset/SystemAgent/BdatAccessHandler/Dxe/BdatAccessHandler.dxs
new file mode 100644
index 0000000..44b88d0
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/BdatAccessHandler/Dxe/BdatAccessHandler.dxs
@@ -0,0 +1,37 @@
+/**
+
+Copyright (c)  1999 - 2011 Intel Corporation. All rights reserved
+This software and associated documentation (if any) is furnished
+under a license and may only be used or copied in accordance
+with the terms of the license. Except as permitted by such
+license, no part of this software or documentation may be
+reproduced, stored in a retrieval system, or transmitted in any
+form or by any means without the express written consent of
+Intel Corporation.
+
+
+Module Name:
+
+  BdatAccessHandler.dxs
+
+Abstract:
+
+  Dependency expression source file.
+  
+**/
+  
+#include "AutoGen.h"
+#include "DxeDepex.h"
+#if defined (BUILD_WITH_GLUELIB) || defined (BUILD_WITH_EDKII_GLUE_LIB)
+#include "EfiDepex.h"
+
+#include EFI_PROTOCOL_DEPENDENCY      (SaPlatformPolicy)
+#include EFI_PROTOCOL_DEPENDENCY      (AcpiTable)
+#include EFI_PROTOCOL_DEPENDENCY      (SaInfo)
+#endif
+
+DEPENDENCY_START
+  DXE_PLATFORM_SA_POLICY_GUID          AND
+  EFI_ACPI_TABLE_PROTOCOL_GUID         AND
+  EFI_SA_INFO_PROTOCOL_GUID
+DEPENDENCY_END
diff --git a/ReferenceCode/Chipset/SystemAgent/BdatAccessHandler/Dxe/BdatAccessHandler.h b/ReferenceCode/Chipset/SystemAgent/BdatAccessHandler/Dxe/BdatAccessHandler.h
new file mode 100644
index 0000000..21e236f
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/BdatAccessHandler/Dxe/BdatAccessHandler.h
@@ -0,0 +1,80 @@
+/** @file
+  This code makes the BIOS Data structure available via standard ACPI mechanisms.
+
+@copyright
+  Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved.
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement
+**/
+
+#ifndef _BDAT_ACCESS_HANDLER_H_
+#define _BDAT_ACCESS_HANDLER_H_
+///
+/// External include files do NOT need to be explicitly specified in real EDKII environment.
+///
+#if !defined(EDK_RELEASE_VERSION) || (EDK_RELEASE_VERSION < 0x00020000)
+#include "EdkIIGlueDxe.h"
+#include "Acpi3_0.h"
+#include "Acpi.h"
+#include "BdatRmtHandler.h"
+#include EFI_GUID_DEFINITION (Hob)
+
+///
+/// Consumed protocols
+///
+#include EFI_PROTOCOL_CONSUMER (AcpiTable)
+#include EFI_PROTOCOL_PRODUCER (BdatAccess)
+#include EFI_PROTOCOL_DEFINITION (SaPlatformPolicy)
+#endif
+///
+/// Ensure proper structure formats
+///
+#pragma pack(push, 1)
+///
+/// BIOS Data ACPI structure
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER             Header;
+  EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE  BdatGas;
+} EFI_BDAT_ACPI_DESCRIPTION_TABLE;
+
+
+/**
+  Entry point of the Bdat RMT Access Handler.
+
+  @param[in] DxePlatformSaPolicy   : A pointer to Dxe platform policy
+  @param[in] HobList               : A pointer to the HOB list
+  @param[in] AcpiTable             : A pointer to ACPI table
+
+  @retval EFI_SUCCESS:              Driver initialized successfully
+  @exception EFI_UNSUPPORTED:       A needed driver was not located
+  @retval EFI_OUT_OF_RESOURCES:     Could not allocate needed resources
+**/
+EFI_STATUS
+BdatRmtHandler (
+  IN DXE_PLATFORM_SA_POLICY_PROTOCOL *DxePlatformSaPolicy,
+  IN VOID                            *HobList,
+  IN EFI_ACPI_TABLE_PROTOCOL         *AcpiTable
+  )
+;
+///
+/// This is copied from Include\Acpi.h
+///
+#define CREATOR_ID_INTEL  0x4C544E49  /// "LTNI""INTL"(Intel)
+#define CREATOR_REV_INTEL 0x20090903
+
+#pragma pack(pop)
+
+#endif /// _BDAT_ACCESS_HANDLER_H_
diff --git a/ReferenceCode/Chipset/SystemAgent/BdatAccessHandler/Dxe/BdatAccessHandler.inf b/ReferenceCode/Chipset/SystemAgent/BdatAccessHandler/Dxe/BdatAccessHandler.inf
new file mode 100644
index 0000000..c83318a
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/BdatAccessHandler/Dxe/BdatAccessHandler.inf
@@ -0,0 +1,99 @@
+#/*++
+#
+#  Copyright (c)  1999 - 2012 Intel Corporation. All rights reserved
+#  This software and associated documentation (if any) is furnished
+#  under a license and may only be used or copied in accordance
+#  with the terms of the license. Except as permitted by such
+#  license, no part of this software or documentation may be
+#  reproduced, stored in a retrieval system, or transmitted in any
+#  form or by any means without the express written consent of
+#  Intel Corporation.
+#
+#
+#  Module Name:
+#
+#   BdatAccessHandler.inf
+#
+#  Abstract:
+#
+#    Component description file for the BdatAccessHandler module.
+#
+#--*/
+
+[defines]
+BASE_NAME            = BdatAccessHandler
+FILE_GUID            = 6DB9486F-6AF6-4090-984D-238482CE3EA4
+COMPONENT_TYPE       = BS_DRIVER
+
+[sources.common]
+  BdatAccessHandler.c
+  BdatAccessHandler.h
+  BdatRmtHandler.c
+  BdatRmtHandler.h
+#
+# Edk II Glue Driver Entry Point
+#
+  EdkIIGlueDxeDriverEntryPoint.c
+
+[includes.common]
+  .
+  $(EFI_SOURCE)
+  $(EDK_SOURCE)/Foundation/Library/EdkIIGlueLib/Include
+  $(EDK_SOURCE)/Foundation/Library/EdkIIGlueLib/Include/Library
+  $(EDK_SOURCE)/Foundation/Library/EdkIIGlueLib/Include/Common
+  $(EDK_SOURCE)/Foundation/Efi
+  $(EDK_SOURCE)/Foundation
+  $(EDK_SOURCE)/Foundation/Framework
+  $(EDK_SOURCE)/Foundation/Framework/Guid
+  $(EDK_SOURCE)/Foundation/Include
+  $(EDK_SOURCE)/Foundation/Efi/Include
+  $(EDK_SOURCE)/Foundation/Framework/Include
+  $(EDK_SOURCE)/Foundation/Include/IndustryStandard
+  $(EDK_SOURCE)/Foundation/Core/Dxe
+  $(EDK_SOURCE)/Foundation/Library/Dxe/Include
+  $(EFI_SOURCE)/$(PROJECT_SA_ROOT)/Include
+  $(EFI_SOURCE)/$(PROJECT_SA_ROOT)/SaInit/Pei
+  $(EFI_SOURCE)/$(PROJECT_SA_ROOT)/$(PROJECT_SA_MRC)/Pei
+  $(EFI_SOURCE)/$(PROJECT_SA_ROOT)/$(PROJECT_SA_MRC)/Pei/Source/Api
+  $(EFI_SOURCE)/$(PROJECT_SA_ROOT)/$(PROJECT_SA_MRC)/Pei/Source/Include
+  $(EFI_SOURCE)/$(PROJECT_SA_ROOT)/$(PROJECT_SA_MRC)/Pei/Source/Include/MrcRegisters
+  $(EFI_SOURCE)/$(PROJECT_SA_ROOT)
+  $(EDK_SOURCE)/Foundation/Cpu/Pentium/Include
+  $(EFI_SOURCE)/$(PROJECT_CPU_ROOT)
+  $(EFI_SOURCE)/$(PROJECT_CPU_ROOT)/Include
+  $(EFI_SOURCE)/$(PROJECT_CPU_ROOT)/Include/Library
+
+[libraries.common]
+  EdkFrameworkProtocolLib
+  EdkFrameworkGuidLib
+  EfiGuidLib
+  EdkProtocolLib
+  EdkIIGlueBaseLib
+  EdkIIGlueBaseIoLibIntrinsic
+  EdkIIGlueBaseMemoryLib
+  EdkIIGlueDxeReportStatusCodeLib
+  EdkIIGlueDxeDebugLibReportStatusCode
+  EdkIIGlueUefiBootServicesTableLib
+  EdkIIGlueUefiRuntimeServicesTableLib
+  EdkIIGlueDxeServicesTableLib
+  EdkIIGlueDxeHobLib
+  IntelSaProtocolLib
+  CpuPlatformLib
+
+[nmake.common]
+  IMAGE_ENTRY_POINT = _ModuleEntryPoint
+  DPX_SOURCE        = BdatAccessHandler.dxs
+
+#
+# Module Entry Point
+#
+  C_FLAGS = $(C_FLAGS) -D __EDKII_GLUE_MODULE_ENTRY_POINT__=BdatAccessHandler
+  C_FLAGS = $(C_FLAGS) -D __EDKII_GLUE_BASE_IO_LIB_INTRINSIC__ \
+                       -D __EDKII_GLUE_BASE_LIB__ \
+                       -D __EDKII_GLUE_DXE_REPORT_STATUS_CODE_LIB__ \
+                       -D __EDKII_GLUE_DXE_DEBUG_LIB_REPORT_STATUS_CODE__ \
+                       -D __EDKII_GLUE_UEFI_BOOT_SERVICES_TABLE_LIB__ \
+                       -D __EDKII_GLUE_UEFI_RUNTIME_SERVICES_TABLE_LIB__ \
+                       -D __EDKII_GLUE_DXE_SERVICES_TABLE_LIB__ \
+                       -D __EDKII_GLUE_DXE_MEMORY_ALLOCATION_LIB__
+
diff --git a/ReferenceCode/Chipset/SystemAgent/BdatAccessHandler/Dxe/BdatAccessHandler.mak b/ReferenceCode/Chipset/SystemAgent/BdatAccessHandler/Dxe/BdatAccessHandler.mak
new file mode 100644
index 0000000..c30f7a4
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/BdatAccessHandler/Dxe/BdatAccessHandler.mak
@@ -0,0 +1,58 @@
+#---------------------------------------------------------------------------
+#		Create PCI Host Bridge DXE Component
+#---------------------------------------------------------------------------
+EDK : BdatAccessHandler
+
+BdatAccessHandler : $(BUILD_DIR)\BdatAccessHandler.mak BdatAccessHandlerBin
+
+$(BUILD_DIR)\BdatAccessHandler.mak : $(BdatAccessHandler_DIR)\BdatAccessHandler.cif $(BUILD_RULES)
+	$(CIF2MAK) $(BdatAccessHandler_DIR)\BdatAccessHandler.cif $(CIF2MAK_DEFAULTS)
+
+BdatAccessHandler_INCLUDES=\
+  $(EdkIIGlueLib_INCLUDES)\
+  $(EDK_INCLUDES)\
+  $(INTEL_MCH_INCLUDES)\
+  $(INTEL_PCH_INCLUDES)
+
+BdatAccessHandler_DEFINES =$(MY_DEFINES)\
+  /D "__EDKII_GLUE_MODULE_ENTRY_POINT__=BdatAccessHandler" \
+  /D __EDKII_GLUE_BASE_LIB__ \
+  /D __EDKII_GLUE_BASE_IO_LIB_INTRINSIC__ \
+  /D __EDKII_GLUE_DXE_REPORT_STATUS_CODE_LIB__ \
+  /D __EDKII_GLUE_DXE_SERVICES_TABLE_LIB__ \
+  /D __EDKII_GLUE_DXE_DEBUG_LIB_REPORT_STATUS_CODE__ \
+  /D __EDKII_GLUE_UEFI_BOOT_SERVICES_TABLE_LIB__\
+  /D __EDKII_GLUE_DXE_MEMORY_ALLOCATION_LIB__ \
+
+BdatAccessHandler_LIB_LINKS =\
+    $(EDKFRAMEWORKPROTOCOLLIB)\
+    $(EdkIIGlueBaseLib_LIB)\
+    $(EDKPROTOCOLLIB)\
+!IF "$(x64_BUILD)"=="1"
+    $(EdkIIGlueBaseLibX64_LIB)\
+!ELSE
+    $(EdkIIGlueBaseLibIA32_LIB)\
+!ENDIF
+    $(EdkIIGlueBaseIoLibIntrinsic_LIB)\
+    $(EdkIIGlueBaseMemoryLib_LIB)\
+    $(EdkIIGlueDxeReportStatusCodeLib_LIB)\
+    $(EdkIIGlueDxeDebugLibReportStatusCode_LIB)\
+    $(EdkIIGlueUefiBootServicesTableLib_LIB)\
+    $(EdkIIGlueUefiRuntimeServicesTableLib_LIB)\
+    $(EdkIIGlueDxeServicesTableLib_LIB)\
+    $(EdkIIGlueDxeHobLib_LIB)\
+    $(INTEL_SA_PROTOCOL_LIB)\
+    $(CpuPlatformLib_LIB)\
+
+BdatAccessHandlerBin :  $(BdatAccessHandler_LIB_LINKS)
+                        $(MAKE) /$(MAKEFLAGS) $(EDKIIGLUE_DEFAULTS)\
+                        /f $(BUILD_DIR)\BdatAccessHandler.mak all\
+                        GUID=6DB9486F-6AF6-4090-984D-238482CE3EA4 \
+                        ENTRY_POINT=_ModuleEntryPoint \
+                        "MY_DEFINES=$(BdatAccessHandler_DEFINES)"\
+                        "MY_INCLUDES=$(BdatAccessHandler_INCLUDES)"\
+                        TYPE=BS_DRIVER \
+                        EDKIIModule=DXEDRIVER\
+                        DEPEX1=$(BdatAccessHandler_DIR)\BdatAccessHandler.dxs\
+                        DEPEX1_TYPE=EFI_SECTION_DXE_DEPEX\
+                        COMPRESS=1
\ No newline at end of file
diff --git a/ReferenceCode/Chipset/SystemAgent/BdatAccessHandler/Dxe/BdatAccessHandler.sdl b/ReferenceCode/Chipset/SystemAgent/BdatAccessHandler/Dxe/BdatAccessHandler.sdl
new file mode 100644
index 0000000..4efce7e
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/BdatAccessHandler/Dxe/BdatAccessHandler.sdl
@@ -0,0 +1,26 @@
+TOKEN
+	Name  = "BdatAccessHandler_SUPPORT"
+	Value  = "1"
+	TokenType = Boolean
+	TargetEQU = Yes
+	TargetMAK = Yes
+	TargetH = Yes
+	Master = Yes
+	Help  = "Main switch to enable BdatAccessHandler support in Project"
+	Token = "MRC_BDAT_SUPPORT" "=" "1"
+End
+
+MODULE
+	Help  = "Includes BdatAccessHandler.mak to Project"
+	File  = "BdatAccessHandler.mak"
+End
+
+PATH
+	Name  = "BdatAccessHandler_DIR"
+End
+
+ELINK
+	Name  = "$(BUILD_DIR)\BdatAccessHandler.ffs"
+	Parent  = "FV_MAIN"
+	InvokeOrder = AfterParent
+End
diff --git a/ReferenceCode/Chipset/SystemAgent/BdatAccessHandler/Dxe/BdatRmtHandler.c b/ReferenceCode/Chipset/SystemAgent/BdatAccessHandler/Dxe/BdatRmtHandler.c
new file mode 100644
index 0000000..8fbe3d2
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/BdatAccessHandler/Dxe/BdatRmtHandler.c
@@ -0,0 +1,152 @@
+/** @file
+  Copies the memory related timing and configuration information into the
+  Compatible BIOS data (BDAT) table.
+
+@copyright
+  Copyright (c) 2010 - 2012 Intel Corporation. All rights reserved.
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement.
+**/
+
+#include "BdatAccessHandler.h"
+#include "McMain.h"
+
+#ifdef BDAT_SUPPORT
+///
+/// Data definitions & structures
+///
+EFI_GUID                                gMemoryInitHobGuid = EFI_MEMORY_RESTORE_DATA_GUID;
+
+///
+/// Bdat Access Handler instance data structure
+///
+STATIC EFI_BDAT_ACPI_DESCRIPTION_TABLE  mRmtAcpiTable = {
+  EFI_BDAT_TABLE_SIGNATURE,                 ///< Signature
+  sizeof (EFI_BDAT_ACPI_DESCRIPTION_TABLE), ///< Length
+  0x01,                                     ///< Revision [01]
+  0,                                        ///< Checksum
+  ' ',                                      ///< OEM ID
+  ' ',                                      ///< .
+  ' ',                                      ///< .
+  ' ',                                      ///< .
+  ' ',                                      ///< .
+  ' ',                                      ///< .
+  0,                                        ///< OEM Table ID
+  0,                                        ///< OEM Revision [0x00000000]
+  0,                                        ///< Creator ID
+  0,                                        ///< Creator Revision
+  0,                                        ///< System Memory Address Space ID
+  0,
+  0,
+  0,
+  EFI_BDAT_ACPI_POINTER,
+};
+#endif
+
+/**
+  Entry point of the Bdat RMT Access Handler.
+
+  @param[in] DxePlatformSaPolicy   : A pointer to Dxe platform policy
+  @param[in] HobList               : A pointer to the HOB list
+  @param[in] AcpiTable             : A pointer to ACPI table
+
+  @retval EFI_SUCCESS:              Driver initialized successfully
+  @exception EFI_UNSUPPORTED:       A needed driver was not located
+  @retval EFI_OUT_OF_RESOURCES:     Could not allocate needed resources
+**/
+EFI_STATUS
+BdatRmtHandler (
+  IN DXE_PLATFORM_SA_POLICY_PROTOCOL *DxePlatformSaPolicy,
+  IN VOID                            *HobList,
+  IN EFI_ACPI_TABLE_PROTOCOL         *AcpiTable
+  )
+{
+#ifdef BDAT_SUPPORT
+  EFI_STATUS            Status;
+  VOID                  *Buffer;
+  RmtData               *rmtBdat;
+  HOB_SAVE_MEMORY_DATA  *RmtHobData;
+  UINTN                 AcpiTableKey;
+  UINT64                TempBuffer;
+  UINT16                BufferSize;
+  UINT32                *ScratchPad;
+
+  Buffer      = NULL;
+  rmtBdat     = NULL;
+  BufferSize  = 0;
+  Status      = EFI_SUCCESS;
+  if (!DxePlatformSaPolicy->MemoryConfig->RmtBdatEnable) {
+    return EFI_UNSUPPORTED;
+  }
+  ///
+  /// Get the Compatible BIOS structure PMT BDAT from the HOB.
+  ///
+  RmtHobData = GetNextGuidHob (&gMemoryInitHobGuid, HobList);
+  if (RmtHobData == NULL) {
+    return EFI_UNSUPPORTED;
+  }
+  ///
+  /// Allocate and clear memory, in 4kb pages
+  ///
+  BufferSize = sizeof (RmtData);
+
+  Status = (gBS->AllocatePages) (AllocateAnyPages, EfiReservedMemoryType, EFI_SIZE_TO_PAGES (BufferSize), (EFI_PHYSICAL_ADDRESS *) &Buffer);
+  if (EFI_ERROR (Status)) {
+    return EFI_OUT_OF_RESOURCES;
+  }
+
+  ZeroMem (Buffer, BufferSize);
+  ///
+  /// Copy BDAT structure to Reserved memory
+  ///
+  CopyMem (Buffer, &RmtHobData->MrcData.Rmt, BufferSize);
+
+  TempBuffer = EFI_SIGNATURE_64 ('I', 'N', 'T', 'E', 'L', 0, 0, 0);
+  ///
+  /// RMT ACPI table
+  ///
+  DEBUG ((EFI_D_INFO, "In RMT ACPI table\n"));
+  CopyMem (&mRmtAcpiTable.Header.OemId, &TempBuffer, sizeof (mRmtAcpiTable.Header.OemId));
+  mRmtAcpiTable.Header.OemTableId       = EFI_SIGNATURE_64 ('H', 'S', 'W', '-', 'L', 'P', 'T', 0);
+  mRmtAcpiTable.Header.CreatorId        = CREATOR_ID_INTEL;
+  mRmtAcpiTable.Header.CreatorRevision  = CREATOR_REV_INTEL;
+  mRmtAcpiTable.Header.OemRevision      = ACPI_BDAT_OEM_REV;
+  ///
+  /// Copy pointer to RMT ACPI BDAT structure and protocol.
+  ///
+  mRmtAcpiTable.BdatGas.Address = (EFI_PHYSICAL_ADDRESS) Buffer;
+  ///
+  /// Install RMT BDAT into RMT ACPI table
+  ///
+  AcpiTableKey = 0;
+  Status = AcpiTable->InstallAcpiTable (
+                        AcpiTable,
+                        &mRmtAcpiTable,
+                        sizeof (EFI_BDAT_ACPI_DESCRIPTION_TABLE),
+                        &AcpiTableKey
+                        );
+  ASSERT_EFI_ERROR (Status);
+
+  ///
+  /// Write scratchpad register in MCHBAR space with address of the RMT ACPI BDAT structure.
+  ///
+  ScratchPad  = (UINT32 *) ((UINT64) (RmtHobData->MrcData.SysIn.Inputs.MchBarBaseAddress) + NCDECS_CR_SCRATCHPAD_NCU_2_REG);
+  *ScratchPad = (UINT32) ((UINT64) Buffer);
+
+  return Status;
+#else
+  return EFI_UNSUPPORTED;
+#endif
+}
diff --git a/ReferenceCode/Chipset/SystemAgent/BdatAccessHandler/Dxe/BdatRmtHandler.h b/ReferenceCode/Chipset/SystemAgent/BdatAccessHandler/Dxe/BdatRmtHandler.h
new file mode 100644
index 0000000..ce24bff
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/BdatAccessHandler/Dxe/BdatRmtHandler.h
@@ -0,0 +1,33 @@
+/** @file
+  Copies the memory related timing and configuration information into the
+  Compatible BIOS data (BDAT) table.
+
+@copyright
+  Copyright (c) 2010 - 2012 Intel Corporation. All rights reserved.
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement.
+**/
+#ifndef _BdatRmtHandler_h_
+#define _BdatRmtHandler_h_
+#ifndef BDAT_SUPPORT
+#define BDAT_SUPPORT
+#endif
+#include "MemInfoHob.h"
+
+#define EFI_BDAT_TABLE_SIGNATURE  EFI_SIGNATURE_32 ('B', 'D', 'A', 'T')
+#define ACPI_BDAT_OEM_REV         0x00001000
+#define EFI_BDAT_ACPI_POINTER     0x0
+
+#endif /// _BdatRmtHandler_h_
diff --git a/ReferenceCode/Chipset/SystemAgent/Guid/AcpiVariable/AcpiVariable.h b/ReferenceCode/Chipset/SystemAgent/Guid/AcpiVariable/AcpiVariable.h
new file mode 100644
index 0000000..6560e70
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/Guid/AcpiVariable/AcpiVariable.h
@@ -0,0 +1,80 @@
+/** @file
+  GUIDs used for ACPI variables.
+
+@copyright
+  Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement
+**/
+#ifndef _ACPI_VARIABLE_H_
+#define _ACPI_VARIABLE_H_
+
+///
+/// RC Override: sync from R8HswClientPkg\Guid\AcpiVariable\AcpiVariable.h
+///
+#define EFI_ACPI_VARIABLE_GUID \
+  { \
+    0xc020489e, 0x6db2, 0x4ef2, 0x9a, 0xa5, 0xca, 0x6, 0xfc, 0x11, 0xd3, 0x6a \
+  }
+
+#define ACPI_GLOBAL_VARIABLE  L"AcpiGlobalVariable"
+
+///
+/// The following structure combine all ACPI related variables into one in order
+/// to boost performance
+///
+#pragma pack(1)
+typedef struct {
+  UINT16  Limit;
+  UINTN   Base;
+} PSEUDO_DESCRIPTOR;
+#pragma pack()
+
+typedef struct {
+  BOOLEAN               APState;
+  BOOLEAN               S3BootPath;
+  EFI_PHYSICAL_ADDRESS  WakeUpBuffer;
+  EFI_PHYSICAL_ADDRESS  GdtrProfile;
+  EFI_PHYSICAL_ADDRESS  IdtrProfile;
+  EFI_PHYSICAL_ADDRESS  CpuPrivateData;
+  EFI_PHYSICAL_ADDRESS  StackAddress;
+  EFI_PHYSICAL_ADDRESS  MicrocodePointerBuffer;
+  EFI_PHYSICAL_ADDRESS  SmramBase;
+  EFI_PHYSICAL_ADDRESS  SmmStartImageBase;
+  UINT32                SmmStartImageSize;
+  UINT32                NumberOfCpus;
+} ACPI_CPU_DATA;
+
+///
+/// Acpi Related variables
+///
+typedef struct {
+  EFI_PHYSICAL_ADDRESS  AcpiReservedMemoryBase;
+  UINT32                AcpiReservedMemorySize;
+  EFI_PHYSICAL_ADDRESS  S3ReservedLowMemoryBase;
+  EFI_PHYSICAL_ADDRESS  AcpiBootScriptTable;
+  EFI_PHYSICAL_ADDRESS  RuntimeScriptTableBase;
+  EFI_PHYSICAL_ADDRESS  AcpiFacsTable;
+  UINT64                SystemMemoryLength;
+  ACPI_CPU_DATA         AcpiCpuData;
+  EFI_PHYSICAL_ADDRESS  VideoOpromAddress; ///< VGA OPROM to support Video Re-POST for Linux S3
+  UINT32                VideoOpromSize;    ///< VGA OPROM to support Video Re-POST for Linux S3
+  EFI_PHYSICAL_ADDRESS  S3DebugBufferAddress;   ///< S3 Debug extension
+  EFI_PHYSICAL_ADDRESS  S3ResumeNvsEntryPoint;  ///< S3 Debug extension
+} ACPI_VARIABLE_SET;
+
+extern EFI_GUID gEfiAcpiVariableGuid;
+
+#endif
diff --git a/ReferenceCode/Chipset/SystemAgent/Guid/SaAcpiTableStorage/SaAcpiTableStorage.c b/ReferenceCode/Chipset/SystemAgent/Guid/SaAcpiTableStorage/SaAcpiTableStorage.c
new file mode 100644
index 0000000..a7ebeac
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/Guid/SaAcpiTableStorage/SaAcpiTableStorage.c
@@ -0,0 +1,27 @@
+/** @file
+  The GUID definition for SA ACPI table storage file name
+
+@copyright
+  Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement
+**/
+#include "Tiano.h"
+#include "SaAcpiTableStorage.h"
+
+EFI_GUID  gSaAcpiTableStorageGuid = SA_ACPI_TABLE_STORAGE_GUID;
+
+EFI_GUID_STRING
+  (&gIntelSaAcpiTableStorageGuid, "SA ACPI Table Storage File Name", "SA ACPI Table Storage file name GUID");
diff --git a/ReferenceCode/Chipset/SystemAgent/Guid/SaAcpiTableStorage/SaAcpiTableStorage.h b/ReferenceCode/Chipset/SystemAgent/Guid/SaAcpiTableStorage/SaAcpiTableStorage.h
new file mode 100644
index 0000000..cc599a1
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/Guid/SaAcpiTableStorage/SaAcpiTableStorage.h
@@ -0,0 +1,31 @@
+/** @file
+  GUID definition for the SA ACPI table storage file name
+
+@copyright
+  Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement
+**/
+#ifndef _SA_ACPI_TABLE_STORAGE_H_
+#define _SA_ACPI_TABLE_STORAGE_H_
+
+#define SA_ACPI_TABLE_STORAGE_GUID \
+  { \
+    0x27E569D5, 0xAFC, 0x4D8F, 0x8C, 0x90, 0x78, 0x3A, 0xC4, 0xA3, 0x18, 0xAB \
+  }
+
+extern EFI_GUID gSaAcpiTableStorageGuid;
+
+#endif
diff --git a/ReferenceCode/Chipset/SystemAgent/Guid/SaDataHob/SaDataHob.c b/ReferenceCode/Chipset/SystemAgent/Guid/SaDataHob/SaDataHob.c
new file mode 100644
index 0000000..067f02b
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/Guid/SaDataHob/SaDataHob.c
@@ -0,0 +1,27 @@
+/** @file
+  The GUID definition for SaDataHob
+
+@copyright
+  Copyright (c) 2012 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement
+**/
+
+#include "Tiano.h"
+#include "SaDataHob.h"
+
+EFI_GUID  gSaDataHobGuid = SA_DATA_HOB_GUID;
+
+EFI_GUID_STRING(&gSaDataHobGuid, "SA Data HOB", "GUID for SA Data HOB");
diff --git a/ReferenceCode/Chipset/SystemAgent/Guid/SaDataHob/SaDataHob.h b/ReferenceCode/Chipset/SystemAgent/Guid/SaDataHob/SaDataHob.h
new file mode 100644
index 0000000..476cb68
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/Guid/SaDataHob/SaDataHob.h
@@ -0,0 +1,122 @@
+/** @file
+  The GUID definition for SaDataHob
+
+@copyright
+  Copyright (c) 2012 - 2013 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement
+**/
+
+#ifndef _SA_DATA_HOB_H_
+#define _SA_DATA_HOB_H_
+
+#define SA_DATA_HOB_GUID \
+  { \
+    0x4c10d934, 0x38e6, 0x45a4, 0x9a, 0x24, 0x2a, 0x79, 0xb9, 0x3d, 0xcb, 0x7f \
+  }
+
+extern EFI_GUID gSaDataHobGuid;
+
+#define GP_ENABLE   1
+#define GP_DISABLE  0
+
+#ifndef _PEI_HOB_H_
+#ifndef __HOB__H__
+typedef struct _EFI_HOB_GENERIC_HEADER {
+  UINT16  HobType;
+  UINT16  HobLength;
+  UINT32  Reserved;
+} EFI_HOB_GENERIC_HEADER;
+
+typedef struct _EFI_HOB_GUID_TYPE {
+  EFI_HOB_GENERIC_HEADER  Header;
+  EFI_GUID                Name;
+  //
+  // Guid specific data goes here
+  //
+} EFI_HOB_GUID_TYPE;
+#endif
+#endif
+
+///
+/// DPR Directory Types
+///
+typedef enum {
+  EnumDprDirectoryTxt   = 0,
+  EnumDprDirectoryPfat
+} DPR_DIRECTORY_ELEMENT;
+
+#define DPR_DIRECTORY_TYPE_TXT     0x01
+#define DPR_DIRECTORY_TYPE_PFAT    0x02
+#define DPR_DIRECTORY_MAX          2
+
+///
+/// DPR directory entry definition
+///
+typedef struct {
+  UINT8   Type;          ///< DPR Directory Type
+  UINT8   Size;          ///< DPR Size in MB
+  UINT32  PhysBase;      ///< Physical address - must be 4K aligned (bits 11..0 must be clear)
+  UINT16  Reserved;      ///< Must be 0
+} DPR_DIRECTORY_ENTRY;
+
+///
+/// PEG data definition
+///
+typedef struct {
+  UINT32  EndPointVendorIdDeviceId[3];  ///< VID/DID for each PEG controller
+  UINT8   BestPreset[16];               ///< Best preset value for each lane
+  UINT8   PegGen3PresetSearch;          ///< Policy value from earlier boot
+  UINT8   PegLinkFailMask;              ///< Mask of PEG controllers to ignore
+} SA_PEG_DATA;
+
+///
+/// SgMode settings
+///
+typedef enum {
+  SgModeDisabled = 0,
+  SgModeMuxed,
+  SgModeMuxless,
+  SgModeDgpu,
+  SgModeMax
+} SG_MODE;
+
+///
+/// SA Info HOB
+///
+typedef struct _SG_INFO_HOB {
+  EFI_HOB_GUID_TYPE EfiHobGuidType;
+  UINT8             RevisionId;     ///< Revision ID
+  SG_MODE           SgMode;
+  BOOLEAN           SgGpioSupport;  ///< 1=Supported; 0=Not Supported
+  UINT8             SgDgpuPwrOK;
+  UINT8             SgDgpuHoldRst;
+  UINT8             SgDgpuPwrEnable;
+  UINT8             SgDgpuPrsnt;
+  UINT8		        PXFixedDynamicMode; // AMI_OVERRIDE_FOR ATI 5.0 Fixed/Dynamic
+} SG_INFO_HOB;
+
+typedef struct {
+  EFI_HOB_GUID_TYPE     EfiHobGuidType;
+  DPR_DIRECTORY_ENTRY   DprDirectory[DPR_DIRECTORY_MAX];
+  BOOLEAN               PegDataValid;                      ///< TRUE, if PegData contains data from a prior boot
+  SA_PEG_DATA           PegData;
+  UINT16                SaIotrapSmiAddress;                ///< Store address for Iotrap SMI
+  BOOLEAN               InitPcieAspmAfterOprom;            ///< Switch for PCIe ASPM initialization after Oprom or before
+  SG_INFO_HOB           SgInfo;
+  BOOLEAN               PegPlatformResetRequired;          ///< if PegPlatformResetRequired=1, platform code should generate a cold/power cycle reset after saving PEG config data into NVRAM
+} SA_DATA_HOB;
+
+#endif
diff --git a/ReferenceCode/Chipset/SystemAgent/Guid/SaGuidLib.cif b/ReferenceCode/Chipset/SystemAgent/Guid/SaGuidLib.cif
new file mode 100644
index 0000000..3298df9
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/Guid/SaGuidLib.cif
@@ -0,0 +1,19 @@
+<component>
+	name = "SaGuidLib"
+	category = ModulePart
+	LocalRoot = "ReferenceCode\Chipset\SystemAgent\Guid\"
+	RefName = "SaGuidLib"
+[files]
+"SaGuidLib.sdl"	
+"SaGuidLib.mak"	
+"SaGuidLib.inf"	
+"AcpiVariable\AcpiVariable.h"	
+"SaAcpiTableStorage\SaAcpiTableStorage.h"	
+"SaAcpiTableStorage\SaAcpiTableStorage.c"	
+"SaDataHob\SaDataHob.h"	
+"SaDataHob\SaDataHob.c"	
+"SgAcpiTableStorage\SgAcpiTableStorage.h"	
+"SgAcpiTableStorage\SgAcpiTableStorage.c"	
+"SaSsdtTableStorage\SaSsdtTableStorage.c"	
+"SaSsdtTableStorage\SaSsdtTableStorage.h"	
+<endComponent>
diff --git a/ReferenceCode/Chipset/SystemAgent/Guid/SaGuidLib.inf b/ReferenceCode/Chipset/SystemAgent/Guid/SaGuidLib.inf
new file mode 100644
index 0000000..9d20582
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/Guid/SaGuidLib.inf
@@ -0,0 +1,49 @@
+## @file
+#  Component description file for the SA GUID library
+#
+#@copyright
+#  Copyright (c)  1999 - 2012 Intel Corporation. All rights reserved
+#  This software and associated documentation (if any) is furnished
+#  under a license and may only be used or copied in accordance
+#  with the terms of the license. Except as permitted by such
+#  license, no part of this software or documentation may be
+#  reproduced, stored in a retrieval system, or transmitted in any
+#  form or by any means without the express written consent of
+#  Intel Corporation.
+#
+#  This file contains a 'Sample Driver' and is licensed as such
+#  under the terms of your license agreement with Intel or your
+#  vendor.  This file may be modified by the user, subject to
+#  the additional terms of the license agreement
+#
+
+[defines]
+BASE_NAME       = SaGuidLib
+COMPONENT_TYPE  = LIBRARY
+
+[sources.common]
+  AcpiVariable/AcpiVariable.h
+  SaAcpiTableStorage/SaAcpiTableStorage.h
+  SaAcpiTableStorage/SaAcpiTableStorage.c
+  SgAcpiTableStorage/SgAcpiTableStorage.h
+  SgAcpiTableStorage/SgAcpiTableStorage.c
+  SaDataHob/SaDataHob.h
+  SaDataHob/SaDataHob.c
+  SaSsdtTableStorage/SaSsdtTableStorage.h
+  SaSsdtTableStorage/SaSsdtTableStorage.c
+
+[includes.common]
+  $(EFI_SOURCE)
+  $(EDK_SOURCE)/Foundation
+  $(EDK_SOURCE)/Foundation/Efi
+  $(EDK_SOURCE)/Foundation/Efi/Include
+  $(EDK_SOURCE)/Foundation/Framework
+  $(EDK_SOURCE)/Foundation/Framework/Include
+  $(EDK_SOURCE)/Foundation/Include
+  $(EDK_SOURCE)/Foundation/Include/IndustryStandard
+  $(EDK_SOURCE)/Foundation/Library/EdkIIGlueLib/Include
+  $(EDK_SOURCE)/Foundation/Core/Dxe
+  $(EDK_SOURCE)/Foundation/Library/Dxe/Include
+
+[nmake.common]
+C_STD_INCLUDE=
diff --git a/ReferenceCode/Chipset/SystemAgent/Guid/SaGuidLib.mak b/ReferenceCode/Chipset/SystemAgent/Guid/SaGuidLib.mak
new file mode 100644
index 0000000..4d3e7a8
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/Guid/SaGuidLib.mak
@@ -0,0 +1,21 @@
+# MAK file for the ModulePart:SaGuidLib
+all : SaGuidLib
+
+$(SaGuidLib_LIB) : SaGuidLib
+
+SaGuidLib : $(BUILD_DIR)\SaGuidLib.mak SaGuidLibBin
+
+$(BUILD_DIR)\SaGuidLib.mak : $(SaGuidLib_DIR)\$(@B).cif $(SaGuidLib_DIR)\$(@B).mak $(BUILD_RULES)
+	$(CIF2MAK) $(SaGuidLib_DIR)\$(@B).cif $(CIF2MAK_DEFAULTS)
+
+SaGuidLibBin : 
+	$(MAKE) /$(MAKEFLAGS) $(EDK_DEFAULTS)\
+		/f $(BUILD_DIR)\SaGuidLib.mak all\
+		"MY_INCLUDES=$(EDK_INCLUDES) $(EdkIIGlueLib_INCLUDES)"  \
+		TYPE=LIBRARY
+!IF "$(x64_BUILD)"=="1" 
+        $(MAKE) /$(MAKEFLAGS) $(EDK_DEFAULTS) BUILD_DIR=$(BUILD_DIR)\IA32\
+                /f $(BUILD_DIR)\SaGuidLib.mak all\
+                "MY_INCLUDES=$(EDK_INCLUDES) $(EdkIIGlueLib_INCLUDES)"  \
+                TYPE=PEI_LIBRARY
+!ENDIF	
diff --git a/ReferenceCode/Chipset/SystemAgent/Guid/SaGuidLib.sdl b/ReferenceCode/Chipset/SystemAgent/Guid/SaGuidLib.sdl
new file mode 100644
index 0000000..55af4bc
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/Guid/SaGuidLib.sdl
@@ -0,0 +1,37 @@
+TOKEN
+	Name  = "SaGuidLib_SUPPORT"
+	Value  = "1"
+	TokenType = Boolean
+	TargetEQU = Yes
+	TargetMAK = Yes
+	Master = Yes
+	Help  = "Main switch to enable SaGuidLib support in Project"
+End
+
+MODULE
+	Help  = "Includes SaGuidLib.mak to Project"
+	File  = "SaGuidLib.mak"
+End
+
+PATH
+	Name  = "SaGuidLib_DIR"
+End
+
+ELINK
+	Name  = "/I$(SaGuidLib_DIR)"
+	Parent  = "INTEL_MCH_INCLUDES"
+	InvokeOrder = AfterParent
+End
+
+ELINK
+	Name  = "/I$(SaGuidLib_DIR)\AcpiVariable"
+	Parent  = "INTEL_MCH_INCLUDES"
+	InvokeOrder = AfterParent
+End
+
+TOKEN
+	Name  = "SaGuidLib_LIB"
+	Value  = "$$(LIB_BUILD_DIR)\SaGuidLib.lib"
+	TokenType = Expression
+	TargetMAK = Yes
+End
diff --git a/ReferenceCode/Chipset/SystemAgent/Guid/SaSsdtTableStorage/SaSsdtTableStorage.c b/ReferenceCode/Chipset/SystemAgent/Guid/SaSsdtTableStorage/SaSsdtTableStorage.c
new file mode 100644
index 0000000..0f0307b
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/Guid/SaSsdtTableStorage/SaSsdtTableStorage.c
@@ -0,0 +1,27 @@
+/** @file
+  The GUID definition for SA ACPI table storage file name
+
+@copyright
+  Copyright (c) 2012 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement
+**/
+#include "Tiano.h"
+#include "SaSsdtTableStorage.h"
+
+EFI_GUID  gSaSsdtAcpiTableStorageGuid = SA_SSDT_ACPI_TABLE_STORAGE_GUID;
+
+EFI_GUID_STRING
+  (&gSaSsdtAcpiTableStorageGuid, "SA SSDT ACPI Table Storage File Name", "SA SSDT ACPI Table Storage file name GUID");
diff --git a/ReferenceCode/Chipset/SystemAgent/Guid/SaSsdtTableStorage/SaSsdtTableStorage.h b/ReferenceCode/Chipset/SystemAgent/Guid/SaSsdtTableStorage/SaSsdtTableStorage.h
new file mode 100644
index 0000000..1e0b9b1
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/Guid/SaSsdtTableStorage/SaSsdtTableStorage.h
@@ -0,0 +1,31 @@
+/** @file
+  GUID definition for the SA SSDT ACPI table storage file name
+
+@copyright
+  Copyright (c) 2012 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement
+**/
+#ifndef _SA_SSDT_TABLE_STORAGE_H_
+#define _SA_SSDT_TABLE_STORAGE_H_
+
+#define SA_SSDT_ACPI_TABLE_STORAGE_GUID \
+  { \
+    0xAAA99A23, 0x13B6, 0x4C31, 0xBB, 0x8B, 0x29, 0x9E, 0x8E, 0xC0, 0x4F, 0xA4 \
+  }
+
+extern EFI_GUID gSaSsdtAcpiTableStorageGuid;
+
+#endif
diff --git a/ReferenceCode/Chipset/SystemAgent/Guid/SgAcpiTableStorage/SgAcpiTableStorage.c b/ReferenceCode/Chipset/SystemAgent/Guid/SgAcpiTableStorage/SgAcpiTableStorage.c
new file mode 100644
index 0000000..5cac632
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/Guid/SgAcpiTableStorage/SgAcpiTableStorage.c
@@ -0,0 +1,45 @@
+/** @file
+  The GUID definition for SG ACPI table storage file name
+
+@copyright
+  Copyright (c) 2010 - 2012 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement
+**/
+#include "EdkIIGlueDxe.h"
+#include "SgAcpiTableStorage.h"
+
+///
+/// Protocol GUID definition for PEG Switchable Graphics
+///
+EFI_GUID  gSgAcpiTableStorageGuid = SG_ACPI_TABLE_STORAGE_GUID;
+
+///
+/// Protocol description for PEG Switchable Graphics
+///
+EFI_GUID_STRING
+  (&gIntelSgAcpiTableStorageGuid, "SG ACPI Table Storage File Name", "SG ACPI Table Storage file name GUID");
+
+
+///
+/// Protocol GUID definition for PCH Switchable Graphics
+///
+EFI_GUID  gSgAcpiTablePchStorageGuid = SG_ACPI_TABLE_PCH_STORAGE_GUID;
+
+///
+/// Protocol description for PCH Switchable Graphics
+///
+EFI_GUID_STRING
+  (&gSgAcpiTablePchStorageGuid, "SG ACPI Table Pch Storage File Name", "SG ACPI Table Pch Storage file name GUID");
diff --git a/ReferenceCode/Chipset/SystemAgent/Guid/SgAcpiTableStorage/SgAcpiTableStorage.h b/ReferenceCode/Chipset/SystemAgent/Guid/SgAcpiTableStorage/SgAcpiTableStorage.h
new file mode 100644
index 0000000..4aa8d54
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/Guid/SgAcpiTableStorage/SgAcpiTableStorage.h
@@ -0,0 +1,50 @@
+/** @file
+  GUID definition for the SG ACPI table storage file name
+
+@copyright
+  Copyright (c) 2010 - 2012 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement
+**/
+#ifndef _SG_ACPI_TABLE_STORAGE_H_
+#define _SG_ACPI_TABLE_STORAGE_H_
+
+///
+/// {CACB3817-81E6-497e-87FF-C8FA8F24EC28}
+///
+#define SG_ACPI_TABLE_STORAGE_GUID \
+  { \
+    0xcacb3817, 0x81e6, 0x497e, 0x87, 0xff, 0xc8, 0xfa, 0x8f, 0x24, 0xec, 0x28 \
+  }
+
+extern EFI_GUID gSgAcpiTableStorageGuid;
+
+#endif
+
+
+#ifndef _SG_ACPI_TABLE_PCH_STORAGE_H_
+#define _SG_ACPI_TABLE_PCH_STORAGE_H_
+
+///
+/// {CBCB3817-81E6-497e-87FF-C8FA8F24EC28}
+///
+#define SG_ACPI_TABLE_PCH_STORAGE_GUID \
+  { \
+    0xcbcb3817, 0x81e6, 0x497e, 0x87, 0xff, 0xc8, 0xfa, 0x8f, 0x24, 0xec, 0x28 \
+  }
+
+extern EFI_GUID gSgAcpiTablePchStorageGuid;
+
+#endif
diff --git a/ReferenceCode/Chipset/SystemAgent/Include/DmaRemappingTable.h b/ReferenceCode/Chipset/SystemAgent/Include/DmaRemappingTable.h
new file mode 100644
index 0000000..380a351
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/Include/DmaRemappingTable.h
@@ -0,0 +1,115 @@
+/** @file
+  This code defines ACPI DMA Remapping table related definitions.
+  See the System Agent BIOS specification for definition of the table.
+
+@copyright
+  Copyright (c) 1999 - 2013 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement
+**/
+#ifndef _DMA_REMAPPING_TABLE_H_
+#define _DMA_REMAPPING_TABLE_H_
+
+#include "Tiano.h"
+#include "Acpi3_0.h"
+
+#pragma pack(1)
+///
+/// DMAR table signature
+///
+#define EFI_ACPI_VTD_DMAR_TABLE_SIGNATURE   0x52414D44  ///< "DMAR"
+#define EFI_ACPI_DMAR_TABLE_REVISION        1
+#define EFI_ACPI_DRHD_ENGINE_HEADER_LENGTH  0x10
+#define EFI_ACPI_RMRR_HEADER_LENGTH         0x18
+#define MAX_PCI_DEPTH                       5
+
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT16  Reserved;
+  UINT8   EnumId;
+  UINT8   StartBusNumber;
+  UINT8   PciPath[2];
+} EFI_ACPI_DEV_SCOPE_STRUCTURE;
+
+typedef struct {
+  UINT16                        Type;
+  UINT16                        Length;
+  UINT8                         Flags;
+  UINT8                         Reserved;
+  UINT16                        SegmentNum;
+  EFI_PHYSICAL_ADDRESS          RegisterBaseAddress;
+  EFI_ACPI_DEV_SCOPE_STRUCTURE  DeviceScope[1];
+} EFI_ACPI_DRHD_ENGINE1_STRUCT;
+
+typedef struct {
+  UINT16                        Type;
+  UINT16                        Length;
+  UINT8                         Flags;
+  UINT8                         Reserved;
+  UINT16                        SegmentNum;
+  EFI_PHYSICAL_ADDRESS          RegisterBaseAddress;
+  EFI_ACPI_DEV_SCOPE_STRUCTURE  DeviceScope[9];
+} EFI_ACPI_DRHD_ENGINE2_STRUCT;
+
+typedef struct {
+  UINT16                        Type;
+  UINT16                        Length;
+  UINT16                        Reserved;
+  UINT16                        SegmentNum;
+  EFI_PHYSICAL_ADDRESS          RmrBaseAddress;
+  EFI_PHYSICAL_ADDRESS          RmrLimitAddress;
+  EFI_ACPI_DEV_SCOPE_STRUCTURE  DeviceScope[3];
+} EFI_ACPI_RMRR_USB_STRUC;
+
+typedef struct {
+  UINT16                        Type;
+  UINT16                        Length;
+  UINT16                        Reserved;
+  UINT16                        SegmentNum;
+  EFI_PHYSICAL_ADDRESS          RmrBaseAddress;
+  EFI_PHYSICAL_ADDRESS          RmrLimitAddress;
+  EFI_ACPI_DEV_SCOPE_STRUCTURE  DeviceScope[1];
+} EFI_ACPI_RMRR_IGD_STRUC;
+
+typedef struct {
+  UINT16                        Type;
+  UINT16                        Length;
+  UINT8                         Reserved[3];
+  UINT8                         AcpiDeviceNumber;
+  UINT8                         AcpiObjectName[20];
+} EFI_ACPI_ANDD_STRUC;
+
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER   Header;
+  UINT8                         HostAddressWidth;
+  UINT8                         Flags;
+  UINT8                         Reserved[10];
+  EFI_ACPI_DRHD_ENGINE1_STRUCT  DrhdEngine1;
+  EFI_ACPI_DRHD_ENGINE2_STRUCT  DrhdEngine2;
+  EFI_ACPI_RMRR_USB_STRUC       RmrrUsb;
+  EFI_ACPI_RMRR_IGD_STRUC       RmrrIgd;
+  EFI_ACPI_ANDD_STRUC           AnddI2C0;
+  EFI_ACPI_ANDD_STRUC           AnddI2C1;
+  EFI_ACPI_ANDD_STRUC           AnddSpi0;
+  EFI_ACPI_ANDD_STRUC           AnddSpi1;
+  EFI_ACPI_ANDD_STRUC           AnddUa00;
+  EFI_ACPI_ANDD_STRUC           AnddUa01;
+  EFI_ACPI_ANDD_STRUC           AnddSdhc;
+} EFI_ACPI_DMAR_TABLE;
+
+#pragma pack()
+
+#endif
diff --git a/ReferenceCode/Chipset/SystemAgent/Include/IntelSaAcpiTables.dsc b/ReferenceCode/Chipset/SystemAgent/Include/IntelSaAcpiTables.dsc
new file mode 100644
index 0000000..fd7a989
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/Include/IntelSaAcpiTables.dsc
@@ -0,0 +1,62 @@
+## @file
+#  Build description file for building the SA ACPI tables
+#
+#@copyright
+#  Copyright (c)  1999 - 2012 Intel Corporation. All rights reserved
+#  This software and associated documentation (if any) is furnished
+#  under a license and may only be used or copied in accordance
+#  with the terms of the license. Except as permitted by such
+#  license, no part of this software or documentation may be
+#  reproduced, stored in a retrieval system, or transmitted in any
+#  form or by any means without the express written consent of
+#  Intel Corporation.
+#
+#  This file contains a 'Sample Driver' and is licensed as such
+#  under the terms of your license agreement with Intel or your
+#  vendor.  This file may be modified by the user, subject to
+#  the additional terms of the license agreement
+#
+
+[=============================================================================]
+#
+# Instructions for building the MCH ACPI table storage file
+#
+[=============================================================================]
+[Build.Ia32.SA_DMAR_ACPITABLE,Build.x64.SA_DMAR_ACPITABLE]
+#
+# Check if we have any source to work with.
+#
+!IFNDEF SECTIONS
+!IFNDEF ASL_FILES
+!ERROR No ASL source files to build were defined in the INF file
+!ENDIF
+!ENDIF
+
+#
+# Define some macros to simplify changes
+#
+TARGET_FFS_FILE   = $(BIN_DIR)\$(FILE_GUID)-$(BASE_NAME).ffs
+    
+#
+# Build FFS file
+#
+$(TARGET_FFS_FILE) : $(SECTIONS) 
+  $(GENFFSFILE) -B $(DEST_DIR) -P1 $(DEST_DIR)\$(BASE_NAME).pkg -V
+
+all : $(TARGET_FFS_FILE)
+
+[=============================================================================]
+[Package.SA_DMAR_ACPITABLE.Default]
+PACKAGE.INF
+\[.]
+BASE_NAME                   = $(BASE_NAME)
+FFS_FILEGUID                = $(FILE_GUID)
+FFS_FILETYPE                = EFI_FV_FILETYPE_FREEFORM
+FFS_ATTRIB_CHECKSUM         = TRUE
+
+IMAGE_SCRIPT =
+{
+  Compress (Dummy) {
+    $(DEST_DIR)\Dmar\Dmar.sec
+  }
+}
diff --git a/ReferenceCode/Chipset/SystemAgent/Include/IntelSaDxe.dsc b/ReferenceCode/Chipset/SystemAgent/Include/IntelSaDxe.dsc
new file mode 100644
index 0000000..06bcb9c
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/Include/IntelSaDxe.dsc
@@ -0,0 +1,35 @@
+## @file
+#  This is the build description file containing the Iio 
+#  DXE, Runtime DXE, SMM, legacy support or other later modules.
+#
+#  This should be included in a [Components] section of the DSC files for a platform build.
+#
+#@copyright
+#  Copyright (c)  1999 - 2012 Intel Corporation. All rights reserved
+#  This software and associated documentation (if any) is furnished
+#  under a license and may only be used or copied in accordance
+#  with the terms of the license. Except as permitted by such
+#  license, no part of this software or documentation may be
+#  reproduced, stored in a retrieval system, or transmitted in any
+#  form or by any means without the express written consent of
+#  Intel Corporation.
+#
+#  This file contains an 'Intel Peripheral Driver' and uniquely
+#  identified as "Intel Reference Module" and is
+#  licensed for Intel CPUs and chipsets under the terms of your
+#  license agreement with Intel or your vendor.  This file may
+#  be modified by the user, subject to additional terms of the
+#  license agreement
+#
+
+$(PROJECT_SA_ROOT)\SmbiosMemory\Dxe\SmbiosMemory.inf   SOURCE_OVERRIDE_PATH = $(EDK_SOURCE)\Foundation\Library\EdkIIGlueLib\EntryPoints
+$(PROJECT_SA_ROOT)\SmmAccess\Dxe\SmmAccess.inf  SOURCE_OVERRIDE_PATH = $(EDK_SOURCE)\Foundation\Library\EdkIIGlueLib\EntryPoints
+$(PROJECT_SA_ROOT)\PciHostBridge\Dxe\PciHostBridge.inf  SOURCE_OVERRIDE_PATH = $(EDK_SOURCE)\Foundation\Library\EdkIIGlueLib\EntryPoints
+$(PROJECT_SA_ROOT)\Acpitables\SaAcpiTables_Edk.inf  SOURCE_OVERRIDE_PATH = $(EDK_SOURCE)\Foundation\Library\EdkIIGlueLib\EntryPoints
+$(PROJECT_SA_ROOT)\Acpitables\SaSsdt\SaSsdt_Edk.inf  SOURCE_OVERRIDE_PATH = $(EDK_SOURCE)\Foundation\Library\EdkIIGlueLib\EntryPoints
+$(PROJECT_SA_ROOT)\SaInit\Dxe\SaInit.inf  SOURCE_OVERRIDE_PATH = $(EDK_SOURCE)\Foundation\Library\EdkIIGlueLib\EntryPoints
+$(PROJECT_SA_ROOT)\BdatAccessHandler\Dxe\BdatAccessHandler.inf  SOURCE_OVERRIDE_PATH = $(EDK_SOURCE)\Foundation\Library\EdkIIGlueLib\EntryPoints
+#
+# Comment out below line if ASPM Init After Oprom was not supported
+#
+$(PROJECT_SA_ROOT)\SaInit\Smm\SaLateInitSmm.inf  SOURCE_OVERRIDE_PATH = $(EDK_SOURCE)\Foundation\Library\EdkIIGlueLib\EntryPoints
diff --git a/ReferenceCode/Chipset/SystemAgent/Include/IntelSaDxeLib.dsc b/ReferenceCode/Chipset/SystemAgent/Include/IntelSaDxeLib.dsc
new file mode 100644
index 0000000..9b7fe1f
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/Include/IntelSaDxeLib.dsc
@@ -0,0 +1,31 @@
+## @file
+#  This is the build description file containing the SA library modules.
+#  This should be included in a [Libraries] section of the DSC files for a platform build.
+#
+#@copyright
+#  Copyright (c)  1999 - 2012 Intel Corporation. All rights reserved
+#  This software and associated documentation (if any) is furnished
+#  under a license and may only be used or copied in accordance
+#  with the terms of the license. Except as permitted by such
+#  license, no part of this software or documentation may be
+#  reproduced, stored in a retrieval system, or transmitted in any
+#  form or by any means without the express written consent of
+#  Intel Corporation.
+#
+#  This file contains a 'Sample Driver' and is licensed as such
+#  under the terms of your license agreement with Intel or your
+#  vendor.  This file may be modified by the user, subject to
+#  the additional terms of the license agreement
+#
+
+$(PROJECT_SA_ROOT)\Protocol\IntelSaProtocolLib.inf
+$(PROJECT_SA_ROOT)\Guid\SaGuidLib.inf
+$(PROJECT_SA_ROOT)\Library\SaPcieLib\Dxe\SaPcieDxeLib.inf
+$(PROJECT_SA_ROOT)\Library\SaPcieLib\Smm\SaPcieSmmLib.inf
+
+#
+# Typically the sample code referenced will be available in the code base already
+# So keep this include at the end to defer to the source base definition
+# and only use the sample code definition if source base does not include these files.
+#
+# $(PROJECT_SA_ROOT)\SampleCode\Protocol\IntelSaSampleCodeProtocolLib.inf
diff --git a/ReferenceCode/Chipset/SystemAgent/Include/IntelSaPei.dsc b/ReferenceCode/Chipset/SystemAgent/Include/IntelSaPei.dsc
new file mode 100644
index 0000000..0b1f05f
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/Include/IntelSaPei.dsc
@@ -0,0 +1,24 @@
+## @file
+#  This is the build description file containing the System Agent PEI modules.
+#
+#  This should be included in a [Components] section of the DSC files for a platform build.
+#
+#@copyright
+#  Copyright (c)  2010 - 2012 Intel Corporation. All rights reserved
+#  This software and associated documentation (if any) is furnished
+#  under a license and may only be used or copied in accordance
+#  with the terms of the license. Except as permitted by such
+#  license, no part of this software or documentation may be
+#  reproduced, stored in a retrieval system, or transmitted in any
+#  form or by any means without the express written consent of
+#  Intel Corporation.
+#
+#  This file contains a 'Sample Driver' and is licensed as such
+#  under the terms of your license agreement with Intel or your
+#  vendor.  This file may be modified by the user, subject to
+#  the additional terms of the license agreement
+#
+
+$(PROJECT_SA_ROOT)\MemoryInit\Pei\MemoryInit.inf SOURCE_OVERRIDE_PATH = $(EDK_SOURCE)\Foundation\Library\EdkIIGlueLib\EntryPoints
+$(PROJECT_SA_ROOT)\SaInit\Pei\SaInitPeim.inf SOURCE_OVERRIDE_PATH = $(EDK_SOURCE)\Foundation\Library\EdkIIGlueLib\EntryPoints
+
diff --git a/ReferenceCode/Chipset/SystemAgent/Include/IntelSaPeiLib.dsc b/ReferenceCode/Chipset/SystemAgent/Include/IntelSaPeiLib.dsc
new file mode 100644
index 0000000..556d529
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/Include/IntelSaPeiLib.dsc
@@ -0,0 +1,29 @@
+## @file
+#  This is the build description file containing the IIO library modules.
+#  This should be included in a [Libraries] section of the DSC files for a platform build.
+#
+#@copyright
+#  Copyright (c)  1999 - 2012 Intel Corporation. All rights reserved
+#  This software and associated documentation (if any) is furnished
+#  under a license and may only be used or copied in accordance
+#  with the terms of the license. Except as permitted by such
+#  license, no part of this software or documentation may be
+#  reproduced, stored in a retrieval system, or transmitted in any
+#  form or by any means without the express written consent of
+#  Intel Corporation.
+#
+#  This file contains a 'Sample Driver' and is licensed as such
+#  under the terms of your license agreement with Intel or your
+#  vendor.  This file may be modified by the user, subject to
+#  the additional terms of the license agreement
+#
+
+$(PROJECT_SA_ROOT)\Guid\SaGuidLib.inf
+$(PROJECT_SA_ROOT)\Ppi\IntelSaPpiLib.inf
+$(PROJECT_SA_ROOT)\SampleCode\Ppi\IntelSaSampleCodePpiLib.inf
+
+#
+# Typically the sample code referenced will be available in the code base already
+# So keep this include at the end to defer to the source base definition
+# and only use the sample code definition if source base does not include these files.
+#
diff --git a/ReferenceCode/Chipset/SystemAgent/Include/IntelSaSsdtAcpiTables.dsc b/ReferenceCode/Chipset/SystemAgent/Include/IntelSaSsdtAcpiTables.dsc
new file mode 100644
index 0000000..8f3ced6
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/Include/IntelSaSsdtAcpiTables.dsc
@@ -0,0 +1,67 @@
+## @file
+#  Build description file for building the SA SSDT ACPI tables
+#
+#@copyright
+#  Copyright (c)  2012 Intel Corporation. All rights reserved
+#  This software and associated documentation (if any) is furnished
+#  under a license and may only be used or copied in accordance
+#  with the terms of the license. Except as permitted by such
+#  license, no part of this software or documentation may be
+#  reproduced, stored in a retrieval system, or transmitted in any
+#  form or by any means without the express written consent of
+#  Intel Corporation.
+#
+#  This file contains a 'Sample Driver' and is licensed as such
+#  under the terms of your license agreement with Intel or your
+#  vendor.  This file may be modified by the user, subject to
+#  the additional terms of the license agreement
+#
+
+[=============================================================================]
+#
+# Instructions for building the SA SSDT ACPI table storage file
+#
+[=============================================================================]
+[Build.Ia32.SA_SSDT_ACPITABLE,Build.x64.SA_SSDT_ACPITABLE]
+#
+# Check if we have any source to work with.
+#
+!IFNDEF SECTIONS
+!IFNDEF ASL_FILES
+!ERROR No ASL source files to build were defined in the INF file
+!ENDIF
+!ENDIF
+
+#
+# Define some macros to simplify changes
+#
+TARGET_FFS_FILE   = $(BIN_DIR)\$(FILE_GUID)-$(BASE_NAME).ffs
+
+$(DEST_DIR)\SaSsdt.sec : $(ASL_SOURCE_FILES) $(ASL_FILES)
+    $(ASL) $(ASL_FLAGS) $(DEST_DIR)\SaSsdt.asl
+    -copy $(DEST_DIR)\SaSsdt.aml $(DEST_DIR)\SaSsdt.acpi
+    $(GENSECTION) -I $(DEST_DIR)\SaSsdt.acpi -O $(DEST_DIR)\SaSsdt.sec -S EFI_SECTION_RAW
+
+#
+# Build FFS file
+#
+$(TARGET_FFS_FILE) : $(SECTIONS) $(DEST_DIR)\SaSsdt.sec
+  $(GENFFSFILE) -B $(DEST_DIR) -P1 $(DEST_DIR)\$(BASE_NAME).pkg -V
+
+all : $(TARGET_FFS_FILE)
+
+[=============================================================================]
+[Package.SA_SSDT_ACPITABLE.Default]
+PACKAGE.INF
+\[.]
+BASE_NAME                   = $(BASE_NAME)
+FFS_FILEGUID                = $(FILE_GUID)
+FFS_FILETYPE                = EFI_FV_FILETYPE_FREEFORM
+FFS_ATTRIB_CHECKSUM         = TRUE
+
+IMAGE_SCRIPT =
+{
+  Compress (Dummy) {
+    $(DEST_DIR)\SaSsdt.sec
+  }
+}
diff --git a/ReferenceCode/Chipset/SystemAgent/Include/SaAccess.h b/ReferenceCode/Chipset/SystemAgent/Include/SaAccess.h
new file mode 100644
index 0000000..ab0490f
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/Include/SaAccess.h
@@ -0,0 +1,290 @@
+/** @file
+  Macros to simplify and abstract the interface to PCI configuration.
+
+@copyright
+  Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement
+**/
+#ifndef _SAACCESS_H_
+#define _SAACCESS_H_
+
+#include "SaRegs.h"
+#include "SaCommonDefinitions.h"
+
+///
+/// SystemAgent Base Address definition
+///
+#ifndef MCH_BASE_ADDRESS
+#define MCH_BASE_ADDRESS  0xfed10000
+#endif
+#ifndef STALL_ONE_MICRO_SECOND
+#define STALL_ONE_MICRO_SECOND  1
+#endif
+#ifndef STALL_ONE_MILLI_SECOND
+#define STALL_ONE_MILLI_SECOND  1000
+#endif
+
+//
+// SA DMI configuration
+//
+#define SA_DMI_MAX_LANE    0x04
+#define SA_DMI_MAX_BUNDLE  0x02
+
+//
+// SA PCI Express* Port configuration
+//
+#define SA_PEG_BUS_NUM     0x00
+#define SA_PEG_DEV_NUM     0x01
+#define SA_PEG10_DEV_NUM   SA_PEG_DEV_NUM
+#define SA_PEG10_FUN_NUM   0x00
+#define SA_PEG11_DEV_NUM   SA_PEG_DEV_NUM
+#define SA_PEG11_FUN_NUM   0x01
+#define SA_PEG12_DEV_NUM   SA_PEG_DEV_NUM
+#define SA_PEG12_FUN_NUM   0x02
+#define SA_PEG_MAX_FUN     0x03
+#define SA_PEG_MAX_LANE    0x10
+#define SA_PEG_MAX_BUNDLE  0x08
+
+#define SA_SWING_HALF     0x1
+#define SA_SWING_FULL     0x2
+
+///
+/// PCI Express* Port configuration Hardware Strapping value
+///
+#define SA_PEG_x8_x4_x4  0x00
+#define SA_PEG_x8_x8_x0  0x02
+#define SA_PEG_x16_x0_x0 0x03
+
+///
+/// System Agent PCI access macros
+///
+///
+/// Device #, Function #
+///
+#define McDevFunPciCfg64(Bus, Dev, Func, Register)              MmPci64 (0, Bus, Dev, Func, Register)
+#define McDevFunPciCfg64Or(Bus, Dev, Func, Register, OrData)    MmPci64Or (0, Bus, Dev, Func, Register, OrData)
+#define McDevFunPciCfg64And(Bus, Dev, Func, Register, AndData)  MmPci64And (0, Bus, Dev, Func, Register, AndData)
+#define McDevFunPciCfg64AndThenOr(Bus, Dev, Func, Register, AndData, OrData) \
+  MmPci64AndThenOr (0, \
+                    Bus, \
+                    Dev, \
+                    Func, \
+                    Register, \
+                    AndData, \
+                    OrData \
+      )
+
+#define McDevFunPciCfg32(Bus, Dev, Func, Register)              MmPci32 (0, Bus, Dev, Func, Register)
+#define McDevFunPciCfg32Or(Bus, Dev, Func, Register, OrData)    MmPci32Or (0, Bus, Dev, Func, Register, OrData)
+#define McDevFunPciCfg32And(Bus, Dev, Func, Register, AndData)  MmPci32And (0, Bus, Dev, Func, Register, AndData)
+#define McDevFunPciCfg32AndThenOr(Bus, Dev, Func, Register, AndData, OrData) \
+  MmPci32AndThenOr (0, \
+                    Bus, \
+                    Dev, \
+                    Func, \
+                    Register, \
+                    AndData, \
+                    OrData \
+      )
+
+#define McDevFunPciCfg16(Bus, Dev, Func, Register)              MmPci16 (0, Bus, Dev, Func, Register)
+#define McDevFunPciCfg16Or(Bus, Dev, Func, Register, OrData)    MmPci16Or (0, Bus, Dev, Func, Register, OrData)
+#define McDevFunPciCfg16And(Bus, Dev, Func, Register, AndData)  MmPci16And (0, Bus, Dev, Func, Register, AndData)
+#define McDevFunPciCfg16AndThenOr(Bus, Dev, Func, Register, AndData, OrData) \
+  MmPci16AndThenOr (0, \
+                    Bus, \
+                    Dev, \
+                    Func, \
+                    Register, \
+                    AndData, \
+                    OrData \
+      )
+
+#define McDevFunPciCfg8(Bus, Dev, Func, Register)             MmPci8 (0, Bus, Dev, Func, Register)
+#define McDevFunPciCfg8Or(Bus, Dev, Func, Register, OrData)   MmPci8Or (0, Bus, Dev, Func, Register, OrData)
+#define McDevFunPciCfg8And(Bus, Dev, Func, Register, AndData) MmPci8And (0, Bus, Dev, Func, Register, AndData)
+#define McDevFunPciCfg8AndThenOr(Bus, Dev, Func, Register, AndData, OrData) \
+  MmPci8AndThenOr (0, \
+                   Bus, \
+                   Dev, \
+                   Func, \
+                   Register, \
+                   AndData, \
+                   OrData \
+      )
+
+///
+/// Device 0, Function 0
+///
+#define McD0PciCfg64(Register)                            MmPci64 (0, SA_MC_BUS, 0, 0, Register)
+#define McD0PciCfg64Or(Register, OrData)                  MmPci64Or (0, SA_MC_BUS, 0, 0, Register, OrData)
+#define McD0PciCfg64And(Register, AndData)                MmPci64And (0, SA_MC_BUS, 0, 0, Register, AndData)
+#define McD0PciCfg64AndThenOr(Register, AndData, OrData)  MmPci64AndThenOr (0, SA_MC_BUS, 0, 0, Register, AndData, OrData)
+
+#define McD0PciCfg32(Register)                            MmPci32 (0, SA_MC_BUS, 0, 0, Register)
+#define McD0PciCfg32Or(Register, OrData)                  MmPci32Or (0, SA_MC_BUS, 0, 0, Register, OrData)
+#define McD0PciCfg32And(Register, AndData)                MmPci32And (0, SA_MC_BUS, 0, 0, Register, AndData)
+#define McD0PciCfg32AndThenOr(Register, AndData, OrData)  MmPci32AndThenOr (0, SA_MC_BUS, 0, 0, Register, AndData, OrData)
+
+#define McD0PciCfg16(Register)                            MmPci16 (0, SA_MC_BUS, 0, 0, Register)
+#define McD0PciCfg16Or(Register, OrData)                  MmPci16Or (0, SA_MC_BUS, 0, 0, Register, OrData)
+#define McD0PciCfg16And(Register, AndData)                MmPci16And (0, SA_MC_BUS, 0, 0, Register, AndData)
+#define McD0PciCfg16AndThenOr(Register, AndData, OrData)  MmPci16AndThenOr (0, SA_MC_BUS, 0, 0, Register, AndData, OrData)
+
+#define McD0PciCfg8(Register)                             MmPci8 (0, SA_MC_BUS, 0, 0, Register)
+#define McD0PciCfg8Or(Register, OrData)                   MmPci8Or (0, SA_MC_BUS, 0, 0, Register, OrData)
+#define McD0PciCfg8And(Register, AndData)                 MmPci8And (0, SA_MC_BUS, 0, 0, Register, AndData)
+#define McD0PciCfg8AndThenOr(Register, AndData, OrData)   MmPci8AndThenOr (0, SA_MC_BUS, 0, 0, Register, AndData, OrData)
+
+///
+/// Device 1, Function 0
+///
+#define McD1PciCfg64(Register)                            MmPci64 (0, SA_MC_BUS, 1, 0, Register)
+#define McD1PciCfg64Or(Register, OrData)                  MmPci64Or (0, SA_MC_BUS, 1, 0, Register, OrData)
+#define McD1PciCfg64And(Register, AndData)                MmPci64And (0, SA_MC_BUS, 1, 0, Register, AndData)
+#define McD1PciCfg64AndThenOr(Register, AndData, OrData)  MmPci64AndThenOr (0, SA_MC_BUS, 1, 0, Register, AndData, OrData)
+
+#define McD1PciCfg32(Register)                            MmPci32 (0, SA_MC_BUS, 1, 0, Register)
+#define McD1PciCfg32Or(Register, OrData)                  MmPci32Or (0, SA_MC_BUS, 1, 0, Register, OrData)
+#define McD1PciCfg32And(Register, AndData)                MmPci32And (0, SA_MC_BUS, 1, 0, Register, AndData)
+#define McD1PciCfg32AndThenOr(Register, AndData, OrData)  MmPci32AndThenOr (0, SA_MC_BUS, 1, 0, Register, AndData, OrData)
+
+#define McD1PciCfg16(Register)                            MmPci16 (0, SA_MC_BUS, 1, 0, Register)
+#define McD1PciCfg16Or(Register, OrData)                  MmPci16Or (0, SA_MC_BUS, 1, 0, Register, OrData)
+#define McD1PciCfg16And(Register, AndData)                MmPci16And (0, SA_MC_BUS, 1, 0, Register, AndData)
+#define McD1PciCfg16AndThenOr(Register, AndData, OrData)  MmPci16AndThenOr (0, SA_MC_BUS, 1, 0, Register, AndData, OrData)
+
+#define McD1PciCfg8(Register)                             MmPci8 (0, SA_MC_BUS, 1, 0, Register)
+#define McD1PciCfg8Or(Register, OrData)                   MmPci8Or (0, SA_MC_BUS, 1, 0, Register, OrData)
+#define McD1PciCfg8And(Register, AndData)                 MmPci8And (0, SA_MC_BUS, 1, 0, Register, AndData)
+#define McD1PciCfg8AndThenOr(Register, AndData, OrData)   MmPci8AndThenOr (0, SA_MC_BUS, 1, 0, Register, AndData, OrData)
+
+///
+/// Device 1, Function 1
+///
+#define McD1F1PciCfg64(Register)                            MmPci64 (0, SA_MC_BUS, 1, 1, Register)
+#define McD1F1PciCfg64Or(Register, OrData)                  MmPci64Or (0, SA_MC_BUS, 1, 1, Register, OrData)
+#define McD1F1PciCfg64And(Register, AndData)                MmPci64And (0, SA_MC_BUS, 1, 1, Register, AndData)
+#define McD1F1PciCfg64AndThenOr(Register, AndData, OrData)  MmPci64AndThenOr (0, SA_MC_BUS, 1, 1, Register, AndData, OrData)
+
+#define McD1F1PciCfg32(Register)                            MmPci32 (0, SA_MC_BUS, 1, 1, Register)
+#define McD1F1PciCfg32Or(Register, OrData)                  MmPci32Or (0, SA_MC_BUS, 1, 1, Register, OrData)
+#define McD1F1PciCfg32And(Register, AndData)                MmPci32And (0, SA_MC_BUS, 1, 1, Register, AndData)
+#define McD1F1PciCfg32AndThenOr(Register, AndData, OrData)  MmPci32AndThenOr (0, SA_MC_BUS, 1, 1, Register, AndData, OrData)
+
+#define McD1F1PciCfg16(Register)                            MmPci16 (0, SA_MC_BUS, 1, 1, Register)
+#define McD1F1PciCfg16Or(Register, OrData)                  MmPci16Or (0, SA_MC_BUS, 1, 1, Register, OrData)
+#define McD1F1PciCfg16And(Register, AndData)                MmPci16And (0, SA_MC_BUS, 1, 1, Register, AndData)
+#define McD1F1PciCfg16AndThenOr(Register, AndData, OrData)  MmPci16AndThenOr (0, SA_MC_BUS, 1, 1, Register, AndData, OrData)
+
+#define McD1F1PciCfg8(Register)                             MmPci8 (0, SA_MC_BUS, 1, 1, Register)
+#define McD1F1PciCfg8Or(Register, OrData)                   MmPci8Or (0, SA_MC_BUS, 1, 1, Register, OrData)
+#define McD1F1PciCfg8And(Register, AndData)                 MmPci8And (0, SA_MC_BUS, 1, 1, Register, AndData)
+#define McD1F1PciCfg8AndThenOr(Register, AndData, OrData)   MmPci8AndThenOr (0, SA_MC_BUS, 1, 1, Register, AndData, OrData)
+
+///
+/// Device 1, Function 2
+///
+#define McD1F2PciCfg64(Register)                            MmPci64 (0, SA_MC_BUS, 1, 2, Register)
+#define McD1F2PciCfg64Or(Register, OrData)                  MmPci64Or (0, SA_MC_BUS, 1, 2, Register, OrData)
+#define McD1F2PciCfg64And(Register, AndData)                MmPci64And (0, SA_MC_BUS, 1, 2, Register, AndData)
+#define McD1F2PciCfg64AndThenOr(Register, AndData, OrData)  MmPci64AndThenOr (0, SA_MC_BUS, 1, 2, Register, AndData, OrData)
+
+#define McD1F2PciCfg32(Register)                            MmPci32 (0, SA_MC_BUS, 1, 2, Register)
+#define McD1F2PciCfg32Or(Register, OrData)                  MmPci32Or (0, SA_MC_BUS, 1, 2, Register, OrData)
+#define McD1F2PciCfg32And(Register, AndData)                MmPci32And (0, SA_MC_BUS, 1, 2, Register, AndData)
+#define McD1F2PciCfg32AndThenOr(Register, AndData, OrData)  MmPci32AndThenOr (0, SA_MC_BUS, 1, 2, Register, AndData, OrData)
+
+#define McD1F2PciCfg16(Register)                            MmPci16 (0, SA_MC_BUS, 1, 2, Register)
+#define McD1F2PciCfg16Or(Register, OrData)                  MmPci16Or (0, SA_MC_BUS, 1, 2, Register, OrData)
+#define McD1F2PciCfg16And(Register, AndData)                MmPci16And (0, SA_MC_BUS, 1, 2, Register, AndData)
+#define McD1F2PciCfg16AndThenOr(Register, AndData, OrData)  MmPci16AndThenOr (0, SA_MC_BUS, 1, 2, Register, AndData, OrData)
+
+#define McD1F2PciCfg8(Register)                             MmPci8 (0, SA_MC_BUS, 1, 2, Register)
+#define McD1F2PciCfg8Or(Register, OrData)                   MmPci8Or (0, SA_MC_BUS, 1, 2, Register, OrData)
+#define McD1F2PciCfg8And(Register, AndData)                 MmPci8And (0, SA_MC_BUS, 1, 2, Register, AndData)
+#define McD1F2PciCfg8AndThenOr(Register, AndData, OrData)   MmPci8AndThenOr (0, SA_MC_BUS, 1, 2, Register, AndData, OrData)
+
+///
+/// Device 2, Function 0
+///
+#define McD2PciCfg64(Register)                            MmPci64 (0, SA_MC_BUS, 2, 0, Register)
+#define McD2PciCfg64Or(Register, OrData)                  MmPci64Or (0, SA_MC_BUS, 2, 0, Register, OrData)
+#define McD2PciCfg64And(Register, AndData)                MmPci64And (0, SA_MC_BUS, 2, 0, Register, AndData)
+#define McD2PciCfg64AndThenOr(Register, AndData, OrData)  MmPci64AndThenOr (0, SA_MC_BUS, 2, 0, Register, AndData, OrData)
+
+#define McD2PciCfg32(Register)                            MmPci32 (0, SA_MC_BUS, 2, 0, Register)
+#define McD2PciCfg32Or(Register, OrData)                  MmPci32Or (0, SA_MC_BUS, 2, 0, Register, OrData)
+#define McD2PciCfg32And(Register, AndData)                MmPci32And (0, SA_MC_BUS, 2, 0, Register, AndData)
+#define McD2PciCfg32AndThenOr(Register, AndData, OrData)  MmPci32AndThenOr (0, SA_MC_BUS, 2, 0, Register, AndData, OrData)
+
+#define McD2PciCfg16(Register)                            MmPci16 (0, SA_MC_BUS, 2, 0, Register)
+#define McD2PciCfg16Or(Register, OrData)                  MmPci16Or (0, SA_MC_BUS, 2, 0, Register, OrData)
+#define McD2PciCfg16And(Register, AndData)                MmPci16And (0, SA_MC_BUS, 2, 0, Register, AndData)
+#define McD2PciCfg16AndThenOr(Register, AndData, OrData)  MmPci16AndThenOr (0, SA_MC_BUS, 2, 0, Register, AndData, OrData)
+
+#define McD2PciCfg8(Register)                             MmPci8 (0, SA_MC_BUS, 2, 0, Register)
+#define McD2PciCfg8Or(Register, OrData)                   MmPci8Or (0, SA_MC_BUS, 2, 0, Register, OrData)
+#define McD2PciCfg8And(Register, AndData)                 MmPci8And (0, SA_MC_BUS, 2, 0, Register, AndData)
+#define McD2PciCfg8AndThenOr(Register, AndData, OrData)   MmPci8AndThenOr (0, SA_MC_BUS, 2, 0, Register, AndData, OrData)
+
+///
+/// Device 22, Function 0
+///
+#define PchD22PciCfg32(Register)                            MmPci32 (0, 0, 22, 0, Register)
+#define PchD22PciCfg32Or(Register, OrData)                  MmPci32Or (0, 0, 22, 0, Register, OrData)
+#define PchD22PciCfg32And(Register, AndData)                MmPci32And (0, 0, 22, 0, Register, AndData)
+#define PchD22PciCfg32AndThenOr(Register, AndData, OrData)  MmPci32AndThenOr (0, 0, 22, 0, Register, AndData, OrData)
+
+///
+/// Memory Controller Hub Memory Mapped IO register access
+///
+#define MCH_REGION_BASE                 (McD0PciCfg64 (R_SA_MCHBAR) &~BIT0)
+#define McMmioAddress(Register)         ((UINTN) MCH_REGION_BASE + (UINTN) (Register))
+
+#define McMmio32Ptr(Register)           ((volatile UINT32 *) McMmioAddress (Register))
+#define McMmio64Ptr(Register)           ((volatile UINT64 *) McMmioAddress (Register))
+
+#define McMmio64(Register)              *McMmio64Ptr (Register)
+#define McMmio64Or(Register, OrData)    (McMmio64 (Register) |= (UINT64) (OrData))
+#define McMmio64And(Register, AndData)  (McMmio64 (Register) &= (UINT64) (AndData))
+#define McMmio64AndThenOr(Register, AndData, OrData) \
+    (McMmio64 (Register) = (McMmio64 (Register) & (UINT64) (AndData)) | (UINT64) (OrData))
+
+#define McMmio32(Register)              *McMmio32Ptr (Register)
+#define McMmio32Or(Register, OrData)    (McMmio32 (Register) |= (UINT32) (OrData))
+#define McMmio32And(Register, AndData)  (McMmio32 (Register) &= (UINT32) (AndData))
+#define McMmio32AndThenOr(Register, AndData, OrData) \
+    (McMmio32 (Register) = (McMmio32 (Register) & (UINT32) (AndData)) | (UINT32) (OrData))
+
+#define McMmio16Ptr(Register)           ((volatile UINT16 *) McMmioAddress (Register))
+#define McMmio16(Register)              *McMmio16Ptr (Register)
+#define McMmio16Or(Register, OrData)    (McMmio16 (Register) |= (UINT16) (OrData))
+#define McMmio16And(Register, AndData)  (McMmio16 (Register) &= (UINT16) (AndData))
+#define McMmio16AndThenOr(Register, AndData, OrData) \
+    (McMmio16 (Register) = (McMmio16 (Register) & (UINT16) (AndData)) | (UINT16) (OrData))
+
+#define McMmio8Ptr(Register)          ((volatile UINT8 *) McMmioAddress (Register))
+#define McMmio8(Register)             *McMmio8Ptr (Register)
+#define McMmio8Or(Register, OrData)   (McMmio8 (Register) |= (UINT8) (OrData))
+#define McMmio8And(Register, AndData) (McMmio8 (Register) &= (UINT8) (AndData))
+#define McMmio8AndThenOr(Register, AndData, OrData) \
+    (McMmio8 (Register) = (McMmio8 (Register) & (UINT8) (AndData)) | (UINT8) (OrData))
+
+#define MmioR32(Address)        (*(volatile UINT32 *) (UINTN) (Address))
+#define MmioW32(Address, Value) (*(volatile UINT32 *) (UINTN) (Address) = (Value))
+
+#endif
diff --git a/ReferenceCode/Chipset/SystemAgent/Include/SaBuildFlags.h b/ReferenceCode/Chipset/SystemAgent/Include/SaBuildFlags.h
new file mode 100644
index 0000000..28ef269
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/Include/SaBuildFlags.h
@@ -0,0 +1,37 @@
+/** @file
+  Defines SA build flags
+
+@copyright
+  Copyright (c) 2012 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement
+**/
+
+#ifndef _SA_BUILD_FLAGS_H_
+#define _SA_BUILD_FLAGS_H_
+
+///
+/// These build flags can be overridden by defining them
+/// in compiling environment variable
+///
+#ifndef SA_PCIE_ASPM_IN_DXE
+#define SA_PCIE_ASPM_IN_DXE 1
+#endif
+
+#ifndef SA_PCIE_ASPM_IN_SMM
+#define SA_PCIE_ASPM_IN_SMM 1
+#endif
+
+#endif
diff --git a/ReferenceCode/Chipset/SystemAgent/Include/SaCommonDefinitions.h b/ReferenceCode/Chipset/SystemAgent/Include/SaCommonDefinitions.h
new file mode 100644
index 0000000..cfcb39f
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/Include/SaCommonDefinitions.h
@@ -0,0 +1,424 @@
+/** @file
+  This header file provides common definitions just for System Agent using to avoid including extra module's file.
+
+@copyright
+  Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement
+**/
+#ifndef _SA_COMMON_DEFINITIONS_H_
+#define _SA_COMMON_DEFINITIONS_H_
+
+#ifndef PCI_VID
+#define PCI_VID             0x0000  ///< Vendor ID Register
+#define PCI_DID             0x0002  ///< Device ID Register
+#define PCI_CMD             0x0004  ///< PCI Command Register
+#define PCI_STS             0x0006  ///< PCI Status Register
+#define PCI_RID             0x0008  ///< Revision ID Register
+#define PCI_IFT             0x0009  ///< Interface Type
+#define PCI_SCC             0x000A  ///< Sub Class Code Register
+#define PCI_BCC             0x000B  ///< Base Class Code Register
+#define PCI_CLS             0x000C  ///< Cache Line Size
+#define PCI_PMLT            0x000D  ///< Primary Master Latency Timer
+#define PCI_HDR             0x000E  ///< Header Type Register
+#define PCI_BIST            0x000F  ///< Built in Self Test Register
+#define PCI_BAR0            0x0010  ///< Base Address Register 0
+#define PCI_BAR1            0x0014  ///< Base Address Register 1
+#define PCI_BAR2            0x0018  ///< Base Address Register 2
+#define PCI_PBUS            0x0018  ///< Primary Bus Number Register
+#define PCI_SBUS            0x0019  ///< Secondary Bus Number Register
+#define PCI_SUBUS           0x001A  ///< Subordinate Bus Number Register
+#define PCI_SMLT            0x001B  ///< Secondary Master Latency Timer
+#define PCI_BAR3            0x001C  ///< Base Address Register 3
+#define PCI_IOBASE          0x001C  ///< I/O base Register
+#define PCI_IOLIMIT         0x001D  ///< I/O Limit Register
+#define PCI_SECSTATUS       0x001E  ///< Secondary Status Register
+#define PCI_BAR4            0x0020  ///< Base Address Register 4
+#define PCI_MEMBASE         0x0020  ///< Memory Base Register
+#define PCI_MEMLIMIT        0x0022  ///< Memory Limit Register
+#define PCI_BAR5            0x0024  ///< Base Address Register 5
+#define PCI_PRE_MEMBASE     0x0024  ///< Prefetchable memory Base register
+#define PCI_PRE_MEMLIMIT    0x0026  ///< Prefetchable memory Limit register
+#define PCI_PRE_MEMBASE_U   0x0028  ///< Prefetchable memory base upper 32 bits
+#define PCI_PRE_MEMLIMIT_U  0x002C  ///< Prefetchable memory limit upper 32 bits
+#define PCI_SVID            0x002C  ///< Subsystem Vendor ID
+#define PCI_SID             0x002E  ///< Subsystem ID
+#define PCI_IOBASE_U        0x0030  ///< I/O base Upper Register
+#define PCI_IOLIMIT_U       0x0032  ///< I/O Limit Upper Register
+#define PCI_CAPP            0x0034  ///< Capabilities Pointer
+#define PCI_EROM            0x0038  ///< Expansion ROM Base Address
+#define PCI_INTLINE         0x003C  ///< Interrupt Line Register
+#define PCI_INTPIN          0x003D  ///< Interrupt Pin Register
+#define PCI_MAXGNT          0x003E  ///< Max Grant Register
+#define PCI_BRIDGE_CNTL     0x003E  ///< Bridge Control Register
+#define PCI_MAXLAT          0x003F  ///< Max Latency Register
+#endif
+
+#ifndef BIT0
+#define BIT0  0x0001
+#define BIT1  0x0002
+#define BIT2  0x0004
+#define BIT3  0x0008
+#define BIT4  0x0010
+#define BIT5  0x0020
+#define BIT6  0x0040
+#define BIT7  0x0080
+#define BIT8  0x0100
+#define BIT9  0x0200
+#ifndef BIT10
+#define BIT10 0x0400
+#define BIT11 0x0800
+#define BIT12 0x1000
+#define BIT13 0x2000
+#define BIT14 0x4000
+#define BIT15 0x8000
+#endif
+#define BIT16 0x00010000
+#define BIT17 0x00020000
+#define BIT18 0x00040000
+#define BIT19 0x00080000
+#define BIT20 0x00100000
+#define BIT21 0x00200000
+#define BIT22 0x00400000
+#define BIT23 0x00800000
+#define BIT24 0x01000000
+#define BIT25 0x02000000
+#define BIT26 0x04000000
+#define BIT27 0x08000000
+#define BIT28 0x10000000
+#define BIT29 0x20000000
+#define BIT30 0x40000000
+#define BIT31 0x80000000
+#endif
+#define ERROR_BY_16     (0xEE15)
+#define ERROR_NOT_BY_16 (0xED15)
+
+#define MAX_PCIE_ASPM_OVERRIDE       500
+#define MAX_PCIE_LTR_OVERRIDE        500
+
+///
+///  Common code version reporting structure
+///
+typedef struct {
+  UINT8 Major;  ///< Major version number
+  UINT8 Minor;  ///< Minor version number
+  UINT8 Rev;    ///< Revision number
+  UINT8 Build;  ///< Build number
+} CodeVersion;
+
+///
+///  Common Memory mapped Io access macros
+///
+#define MmioAddress(BaseAddr, Register) \
+  ((UINTN) BaseAddr + (UINTN) (Register))
+
+///
+/// Macro to point to a 64 bit MMIO Address
+///
+#define Mmio64Ptr(BaseAddr, Register) \
+  ((volatile UINT64 *) MmioAddress (BaseAddr, Register))
+///
+/// Macro to get the value from a 64 bit MMIO Address
+///
+#define Mmio64(BaseAddr, Register) \
+  *Mmio64Ptr (BaseAddr, Register)
+///
+/// Macro to get a value from a 64 bit MMIO Address, perform a logical OR with
+/// the given data and then write it back to the same address
+///
+#define Mmio64Or(BaseAddr, Register, OrData) \
+  Mmio64 (BaseAddr, Register) = (UINT64) \
+    (Mmio64 (BaseAddr, Register) | (UINT64) (OrData))
+///
+/// Macro to get a value from a 64 bit MMIO Address, perform a logical AND with
+/// the given data and then write it back to the same address
+///
+#define Mmio64And(BaseAddr, Register, AndData) \
+  Mmio64 (BaseAddr, Register) = (UINT64) \
+    (Mmio64 (BaseAddr, Register) & (UINT64) (AndData))
+///
+/// Macro to get a value from a 64 bit MMIO Address, perform a logical AND and
+/// then a OR with the given data and then write it back to the same address
+///
+#define Mmio64AndThenOr(BaseAddr, Register, AndData, OrData) \
+  Mmio64 (BaseAddr, Register) = (UINT64) \
+    ((Mmio64 (BaseAddr, Register) & (UINT64) (AndData)) | (UINT64) (OrData))
+
+///
+/// Macro to point to a 32 bit MMIO Address
+///
+#define Mmio32Ptr(BaseAddr, Register) \
+  ((volatile UINT32 *) MmioAddress (BaseAddr, Register))
+///
+/// Macro to get the value from a 32 bit MMIO Address
+///
+#define Mmio32(BaseAddr, Register) \
+  *Mmio32Ptr (BaseAddr, Register)
+///
+/// Macro to get a value from a 32 bit MMIO Address, perform a logical OR with
+/// the given data and then write it back to the same address
+///
+#define Mmio32Or(BaseAddr, Register, OrData) \
+  Mmio32 (BaseAddr, Register) = (UINT32) \
+    (Mmio32 (BaseAddr, Register) | (UINT32) (OrData))
+///
+/// Macro to get a value from a 32 bit MMIO Address, perform a logical AND with
+/// the given data and then write it back to the same address
+///
+#define Mmio32And(BaseAddr, Register, AndData) \
+  Mmio32 (BaseAddr, Register) = (UINT32) \
+    (Mmio32 (BaseAddr, Register) & (UINT32) (AndData))
+///
+/// Macro to get a value from a 32 bit MMIO Address, perform a logical AND and
+/// then a OR with the given data and then write it back to the same address
+///
+#define Mmio32AndThenOr(BaseAddr, Register, AndData, OrData) \
+  Mmio32 (BaseAddr, Register) = (UINT32) \
+    ((Mmio32 (BaseAddr, Register) & (UINT32) (AndData)) | (UINT32) (OrData))
+
+///
+/// Macro to point to a 16 bit MMIO Address
+///
+#define Mmio16Ptr(BaseAddr, Register) \
+  ((volatile UINT16 *) MmioAddress (BaseAddr, Register))
+///
+/// Macro to get the value from a 16 bit MMIO Address
+///
+#define Mmio16(BaseAddr, Register) \
+  *Mmio16Ptr (BaseAddr, Register)
+///
+/// Macro to get a value from a 16 bit MMIO Address, perform a logical OR with
+/// the given data and then write it back to the same address
+///
+#define Mmio16Or(BaseAddr, Register, OrData) \
+  Mmio16 (BaseAddr, Register) = (UINT16) \
+    (Mmio16 (BaseAddr, Register) | (UINT16) (OrData))
+///
+/// Macro to get a value from a 16 bit MMIO Address, perform a logical AND with
+/// the given data and then write it back to the same address
+///
+#define Mmio16And(BaseAddr, Register, AndData) \
+  Mmio16 (BaseAddr, Register) = (UINT16) \
+    (Mmio16 (BaseAddr, Register) & (UINT16) (AndData))
+///
+/// Macro to get a value from a 16 bit MMIO Address, perform a logical AND and
+/// then a OR with the given data and then write it back to the same address
+///
+#define Mmio16AndThenOr(BaseAddr, Register, AndData, OrData) \
+  Mmio16 (BaseAddr, Register) = (UINT16) \
+    ((Mmio16 (BaseAddr, Register) & (UINT16) (AndData)) | (UINT16) (OrData))
+
+///
+///  Macro to point to a 8 bit MMIO Address
+///
+#define Mmio8Ptr(BaseAddr, Register) \
+  ((volatile UINT8 *) MmioAddress (BaseAddr, Register))
+///
+/// Macro to get the value from a 8 bit MMIO Address
+///
+#define Mmio8(BaseAddr, Register) \
+  *Mmio8Ptr (BaseAddr, Register)
+///
+/// Macro to get a value from a 8 bit MMIO Address, perform a logical OR with
+/// the given data and then write it back to the same address
+///
+#define Mmio8Or(BaseAddr, Register, OrData) \
+  Mmio8 (BaseAddr, Register) = (UINT8) \
+    (Mmio8 (BaseAddr, Register) | (UINT8) (OrData))
+///
+/// Macro to get a value from a 8 bit MMIO Address, perform a logical AND with
+/// the given data and then write it back to the same address
+///
+#define Mmio8And(BaseAddr, Register, AndData) \
+  Mmio8 (BaseAddr, Register) = (UINT8) \
+    (Mmio8 (BaseAddr, Register) & (UINT8) (AndData))
+///
+/// Macro to get a value from a 8 bit MMIO Address, perform a logical AND and
+/// then a OR with the given data and then write it back to the same address
+///
+#define Mmio8AndThenOr(BaseAddr, Register, AndData, OrData) \
+  Mmio8 (BaseAddr, Register) = (UINT8) \
+    ((Mmio8 (BaseAddr, Register) & (UINT8) (AndData)) | (UINT8) (OrData))
+
+///
+///  Common Memory mapped Pci access macros
+///
+#ifndef MmPciAddress
+#define MmPciAddress(Segment, Bus, Device, Function, Register) \
+    ((UINTN) (PciRead32 (PCI_LIB_ADDRESS (0,0,0,0x60)) & 0xFC000000) + \
+     (UINTN) (Bus << 20) + (UINTN) (Device << 15) + (UINTN) \
+     (Function << 12) + (UINTN) (Register))
+#endif
+
+///
+/// Macro to point to a 64 bit PCI Configuration Space Address
+///
+#define MmPci64Ptr(Segment, Bus, Device, Function, Register) \
+  ((volatile UINT64 *) MmPciAddress (Segment, Bus, Device, Function, Register))
+///
+/// Macro to get the value from a 64 bit PCI Configuration Space Address
+///
+#define MmPci64(Segment, Bus, Device, Function, Register) \
+  *MmPci64Ptr (Segment, Bus, Device, Function, Register)
+///
+/// Macro to get a value from a 64 bit PCI Configuration Space Address, perform
+/// a logical OR with the given data and then write it back to the same address
+///
+#define MmPci64Or(Segment, Bus, Device, Function, Register, OrData) \
+  MmPci64 (Segment, Bus, Device, Function, Register) = \
+    (UINT64) (MmPci64 (Segment, Bus, Device, Function, Register) | (UINT64) (OrData))
+///
+/// Macro to get a value from a 64 bit PCI Configuration Space Address, perform
+/// a logical AND with the given data and then write it back to the same address
+///
+#define MmPci64And(Segment, Bus, Device, Function, Register, AndData) \
+  MmPci64 (Segment, \
+           Bus, \
+           Device, \
+           Function, \
+           Register \
+      ) = (UINT64) (MmPci64 (Segment, Bus, Device, Function, Register) & (UINT64) (AndData))
+///
+/// Macro to get a value from a 64 bit PCI Configuration Space Address, perform
+/// a logical AND and then a OR with the given data and then write it back to the
+/// same address
+///
+#define MmPci64AndThenOr(Segment, Bus, Device, Function, Register, AndData, OrData) \
+  MmPci64 (Segment, \
+           Bus, \
+           Device, \
+           Function, \
+           Register \
+      ) = (UINT64) ((MmPci64 (Segment, Bus, Device, Function, Register) & (UINT64) (AndData)) | (UINT64) (OrData))
+
+///
+/// Macro to point to a 32 bit PCI Configuration Space Address
+///
+#define MmPci32Ptr(Segment, Bus, Device, Function, Register) \
+   ((volatile UINT32 *) MmPciAddress (Segment, Bus, Device, Function, Register))
+///
+/// Macro to get the value from a 32 bit PCI Configuration Space Address
+///
+#define MmPci32(Segment, Bus, Device, Function, Register) \
+   *MmPci32Ptr (Segment, Bus, Device, Function, Register)
+///
+/// Macro to get a value from a 32 bit PCI Configuration Space Address, perform
+/// a logical OR with the given data and then write it back to the same address
+///
+#define MmPci32Or(Segment, Bus, Device, Function, Register, OrData) \
+  MmPci32 (Segment, Bus, Device, Function, Register) = \
+    (UINT32) (MmPci32 (Segment, Bus, Device, Function, Register) | (UINT32) (OrData))
+///
+/// Macro to get a value from a 32 bit PCI Configuration Space Address, perform
+/// a logical AND with the given data and then write it back to the same address
+///
+#define MmPci32And(Segment, Bus, Device, Function, Register, AndData) \
+  MmPci32 (Segment, \
+           Bus, \
+           Device, \
+           Function, \
+           Register \
+      ) = (UINT32) (MmPci32 (Segment, Bus, Device, Function, Register) & (UINT32) (AndData))
+///
+/// Macro to get a value from a 32 bit PCI Configuration Space Address, perform
+/// a logical AND and then a OR with the given data and then write it back to the
+/// same address
+///
+#define MmPci32AndThenOr(Segment, Bus, Device, Function, Register, AndData, OrData) \
+  MmPci32 (Segment, \
+           Bus, \
+           Device, \
+           Function, \
+           Register \
+      ) = (UINT32) ((MmPci32 (Segment, Bus, Device, Function, Register) & (UINT32) (AndData)) | (UINT32) (OrData))
+
+///
+/// Macro to point to a 16 bit PCI Configuration Space Address
+///
+#define MmPci16Ptr(Segment, Bus, Device, Function, Register) \
+  ((volatile UINT16 *) MmPciAddress (Segment, Bus, Device, Function, Register))
+///
+/// Macro to get the value from a 16 bit PCI Configuration Space Address
+///
+#define MmPci16(Segment, Bus, Device, Function, Register) \
+  *MmPci16Ptr (Segment, Bus, Device, Function, Register)
+///
+/// Macro to get a value from a 16 bit PCI Configuration Space Address, perform
+/// a logical OR with the given data and then write it back to the same address
+///
+#define MmPci16Or(Segment, Bus, Device, Function, Register, OrData) \
+  MmPci16 (Segment, Bus, Device, Function, Register) = \
+    (UINT16) (MmPci16 (Segment, Bus, Device, Function, Register) | (UINT16) (OrData))
+///
+/// Macro to get a value from a 16 bit PCI Configuration Space Address, perform
+/// a logical AND with the given data and then write it back to the same address
+///
+#define MmPci16And(Segment, Bus, Device, Function, Register, AndData) \
+  MmPci16 (Segment, \
+           Bus, \
+           Device, \
+           Function, \
+           Register \
+      ) = (UINT16) (MmPci16 (Segment, Bus, Device, Function, Register) & (UINT16) (AndData))
+///
+/// Macro to get a value from a 16 bit PCI Configuration Space Address, perform
+/// a logical AND and then a OR with the given data and then write it back to the
+/// same address
+///
+#define MmPci16AndThenOr(Segment, Bus, Device, Function, Register, AndData, OrData) \
+  MmPci16 (Segment, \
+           Bus, \
+           Device, \
+           Function, \
+           Register \
+      ) = (UINT16) ((MmPci16 (Segment, Bus, Device, Function, Register) & (UINT16) (AndData)) | (UINT16) (OrData))
+
+///
+/// Macro to point to a 8 bit PCI Configuration Space Address
+///
+#define MmPci8Ptr(Segment, Bus, Device, Function, Register) \
+  ((volatile UINT8 *) MmPciAddress (Segment, Bus, Device, Function, Register))
+///
+/// Macro to get the value from a 8 bit PCI Configuration Space Address
+///
+#define MmPci8(Segment, Bus, Device, Function, Register) \
+  *MmPci8Ptr (Segment, Bus, Device, Function, Register)
+///
+/// Macro to get a value from a 8 bit PCI Configuration Space Address, perform
+/// a logical OR with the given data and then write it back to the same address
+///
+#define MmPci8Or(Segment, Bus, Device, Function, Register, OrData) \
+  MmPci8 (Segment, Bus, Device, Function, Register) = \
+    (UINT8) (MmPci8 (Segment, Bus, Device, Function, Register) | (UINT8) (OrData))
+///
+/// Macro to get a value from a 8 bit PCI Configuration Space Address, perform
+/// a logical AND with the given data and then write it back to the same address
+///
+#define MmPci8And(Segment, Bus, Device, Function, Register, AndData) \
+  MmPci8 (Segment, Bus, Device, Function, Register) = \
+    (UINT8) (MmPci8 (Segment, Bus, Device, Function, Register) & (UINT8) (AndData))
+///
+/// Macro to get a value from a 8 bit PCI Configuration Space Address, perform
+/// a logical AND and then a OR with the given data and then write it back to the
+/// same address
+///
+#define MmPci8AndThenOr(Segment, Bus, Device, Function, Register, AndData, OrData) \
+  MmPci8 (Segment, \
+          Bus, \
+          Device, \
+          Function, \
+          Register \
+      ) = (UINT8) ((MmPci8 (Segment, Bus, Device, Function, Register) & (UINT8) (AndData)) | (UINT8) (OrData))
+#endif
diff --git a/ReferenceCode/Chipset/SystemAgent/Include/SaInclude.cif b/ReferenceCode/Chipset/SystemAgent/Include/SaInclude.cif
new file mode 100644
index 0000000..9506fe6
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/Include/SaInclude.cif
@@ -0,0 +1,21 @@
+<component>
+	name = "SaInclude"
+	category = ModulePart
+	LocalRoot = "ReferenceCode\Chipset\SystemAgent\Include\"
+	RefName = "SaInclude"
+[files]
+"SaInclude.sdl"	
+"SaAccess.h"	
+"SaBuildFlags.h"
+"SaCommonDefinitions.h"	
+"SaRegs.h"	
+"SaPcieVersion.h"
+"DmaRemappingTable.h"	
+"SaPciExpressLib.h"
+"IntelSaPeiLib.dsc"	
+"IntelSaSsdtAcpiTables.dsc"
+"IntelSaAcpiTables.dsc"	
+"IntelSaDxe.dsc"	
+"IntelSaDxeLib.dsc"	
+"IntelSaPei.dsc"	
+<endComponent>
diff --git a/ReferenceCode/Chipset/SystemAgent/Include/SaInclude.sdl b/ReferenceCode/Chipset/SystemAgent/Include/SaInclude.sdl
new file mode 100644
index 0000000..1dabe74
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/Include/SaInclude.sdl
@@ -0,0 +1,15 @@
+TOKEN
+	Name  = "SaInclude_SUPPORT"
+	Value  = "1"
+	TokenType = Boolean
+	TargetEQU = Yes
+	TargetMAK = Yes
+	Master = Yes
+	Help  = "Main switch to enable SaInclude support in Project"
+End
+
+PATH
+	Name  = "INTEL_SA_INCLUDE_DIR"
+End
+
+
diff --git a/ReferenceCode/Chipset/SystemAgent/Include/SaPciExpressLib.h b/ReferenceCode/Chipset/SystemAgent/Include/SaPciExpressLib.h
new file mode 100644
index 0000000..69c7307
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/Include/SaPciExpressLib.h
@@ -0,0 +1,38 @@
+/** @file
+  Header file for the PCI Express library.
+
+@copyright
+  Copyright (c) 2012 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains a 'Sample Driver' and is licensed as such
+  under the terms of your license agreement with Intel or your
+  vendor.  This file may be modified by the user, subject to
+  the additional terms of the license agreement
+**/
+#ifndef _SA_PCI_EXPRESS_LIB_H_
+#define _SA_PCI_EXPRESS_LIB_H_
+
+#if defined (EDK_RELEASE_VERSION) && (EDK_RELEASE_VERSION < 0x00020000)
+#include "EdkIIGlueBase.h"
+#endif
+
+/**
+  Gets the base address of PCI Express.
+
+  This internal functions retrieves PCI Express Base Address.
+
+  @return The base address of PCI Express.
+**/
+VOID*
+GetPciExpressBaseAddress (
+  VOID
+);
+
+#endif
diff --git a/ReferenceCode/Chipset/SystemAgent/Include/SaPcieVersion.h b/ReferenceCode/Chipset/SystemAgent/Include/SaPcieVersion.h
new file mode 100644
index 0000000..ba05a7b
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/Include/SaPcieVersion.h
@@ -0,0 +1,30 @@
+/** @file
+  The System Agent PCIe code version
+
+@copyright
+  Copyright (c) 1999 - 2014 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement
+**/
+
+#ifndef _SA_PCIE_VERSION_H_
+#define _SA_PCIE_VERSION_H_
+///
+///  Major Minor Rev   Build
+///  ----- ----- ----- -----
+///
+1, 9, 0, 0
+
+#endif
diff --git a/ReferenceCode/Chipset/SystemAgent/Include/SaRegs.h b/ReferenceCode/Chipset/SystemAgent/Include/SaRegs.h
new file mode 100644
index 0000000..867766f
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/Include/SaRegs.h
@@ -0,0 +1,1510 @@
+/** @file
+  Register names for System Agent (SA) registers
+  Conventions:
+  - Prefixes:
+  - Definitions beginning with "R_" are registers
+  - Definitions beginning with "B_" are bits within registers
+  - Definitions beginning with "V_" are meaningful values of bits within the registers
+  - Definitions beginning with "S_" are register sizes
+  - Definitions beginning with "N_" are the bit position
+  - In general, SA registers are denoted by "_SA_" in register names
+  - Registers / bits that are different between SA generations are denoted by
+    "_SA_<generation_name>_" in register/bit names. e.g., "_SA_HSW_"
+  - Registers / bits that are different between SKUs are denoted by "_<SKU_name>"
+    at the end of the register/bit names
+  - Registers / bits of new devices introduced in a SA generation will be just named
+    as "_SA_" without <generation_name> inserted.
+@copyright
+  Copyright (c) 1999 - 2013 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement
+**/
+#ifndef _SA_REGS_H_
+#define _SA_REGS_H_
+
+//
+// Equates to convert Device IDs to Platform IDs
+//
+#define PLATFORM_ID_MOBILE    1
+#define PLATFORM_ID_DESKTOP   0
+#define PLATFORM_ID_UP_SERVER 2
+
+//
+// DEVICE 0 (Memory Controller Hub)
+//
+#define SA_MC_BUS          0x00
+#define SA_MC_DEV          0x00
+#define SA_MC_FUN          0x00
+#define V_SA_MC_VID        0x8086
+#define R_SA_MC_DEVICE_ID  0x02
+#define R_SA_MC_CAPID0_B   0xE8
+
+///
+/// Macros that judge which type a device ID belongs to
+///
+
+///
+/// CPU Mobile SA Device IDs B0:D0:F0
+///
+#define V_SA_DEVICE_ID_MB_0        0x0C04   ///< Haswell Mobile SA DID
+#define V_SA_DEVICE_ID_MB_1        0x0A04   ///< Haswell Ult Mobile SA DID
+#define V_SA_DEVICE_ID_MB_2        0x0D04   ///< Crystalwell Mobile SA DID
+#define V_SA_DEVICE_ID_MB_3        0x0A0C   ///< Haswell Ulx Mobile SA DID
+
+///
+/// CPU Desktop SA Device IDs B0:D0:F0
+///
+#define V_SA_DEVICE_ID_DT_0        0x0C00   ///< Haswell Desktop SA DID
+#define V_SA_DEVICE_ID_DT_1        0x0D00   ///< Crystalwell Desktop SA DID
+
+///
+/// CPU Server SA Device IDs B0:D0:F0
+///
+#define V_SA_DEVICE_ID_SVR_0       0x0C08   ///< Haswell Server SA DID
+#define V_SA_DEVICE_ID_SVR_1       0x0D08   ///< Crystalwell Server SA DID
+#ifdef UPSERVER_SUPPORT
+#define V_SA_DEVICE_ID_DT_2        0x0C0C   ///< Haswell Marketing SpareAffect SA DID
+#endif
+
+
+///
+/// Device IDs that are Mobile specific B0:D0:F0
+///
+#define IS_SA_DEVICE_ID_MOBILE(DeviceId) \
+    ( \
+      (DeviceId == V_SA_DEVICE_ID_MB_0) || \
+      (DeviceId == V_SA_DEVICE_ID_MB_1) || \
+      (DeviceId == V_SA_DEVICE_ID_MB_2) || \
+      (DeviceId == V_SA_DEVICE_ID_MB_3) \
+    )
+
+///
+/// Device IDs that are Desktop specific B0:D0:F0
+///
+#ifdef UPSERVER_SUPPORT
+#define IS_SA_DEVICE_ID_DESKTOP(DeviceId) \
+    ( \
+      (DeviceId == V_SA_DEVICE_ID_DT_0) || \
+      (DeviceId == V_SA_DEVICE_ID_DT_1) || \
+      (DeviceId == V_SA_DEVICE_ID_DT_2) \
+    )
+#else
+#define IS_SA_DEVICE_ID_DESKTOP(DeviceId) \
+    ( \
+      (DeviceId == V_SA_DEVICE_ID_DT_0) || \
+      (DeviceId == V_SA_DEVICE_ID_DT_1) \
+    )
+#endif
+
+///
+/// Device IDS that are Server specific B0:D0:F0
+///
+#define IS_SA_DEVICE_ID_SERVER(DeviceId) \
+    ( \
+      (DeviceId == V_SA_DEVICE_ID_SVR_0) || \
+      (DeviceId == V_SA_DEVICE_ID_SVR_1) \
+    )
+
+///
+/// Description:
+///  This is the base address for the PCI Express Egress Port MMIO Configuration space.  There is no physical memory within this 4KB window that can be addressed.  The 4KB reserved by this register does not alias to any PCI 2.3 compliant memory mapped space.  On reset, the EGRESS port MMIO configuration space is disabled and must be enabled by writing a 1 to PXPEPBAREN [Dev 0, offset 40h, bit 0].
+///  All the bits in this register are locked in LT mode.
+///
+#define R_SA_PXPEPBAR  (0x40)
+///
+/// Description of PXPEPBAREN (0:0)
+///  0:  PXPEPBAR is disabled and does not claim any memory
+///  1:  PXPEPBAR memory mapped accesses are claimed and decoded appropriately
+///  This register is locked by LT.
+///
+#define N_SA_PXPEPBAR_PXPEPBAREN_OFFSET  (0x0)
+#define S_SA_PXPEPBAR_PXPEPBAREN_WIDTH   (0x1)
+#define B_SA_PXPEPBAR_PXPEPBAREN_MASK    (0x1)
+#define V_SA_PXPEPBAR_PXPEPBAREN_DEFAULT (0x0)
+///
+/// Description of PXPEPBAR (12:38)
+///  This field corresponds to bits 38 to 12 of the base address PCI Express Egress Port MMIO configuration space.  BIOS will program this register resulting in a base address for a 4KB block of contiguous memory address space.  This register ensures that a naturally aligned 4KB space is allocated within the first 512GB of addressable memory space.  System Software uses this base address to program the PCI Express Egress Port MMIO register set.  All the bits in this register are locked in LT mode.
+///
+#define N_SA_PXPEPBAR_PXPEPBAR_OFFSET  (0xc)
+#define S_SA_PXPEPBAR_PXPEPBAR_WIDTH   (0x1b)
+#define B_SA_PXPEPBAR_PXPEPBAR_MASK    (0x7ffffff000)
+#define V_SA_PXPEPBAR_PXPEPBAR_DEFAULT (0x0)
+
+///
+/// Description:
+///  This is the base address for the Host Memory Mapped Configuration space.  There is no physical memory within this 32KB window that can be addressed.  The 32KB reserved by this register does not alias to any PCI 2.3 compliant memory mapped space.  On reset, the Host MMIO Memory Mapped Configuation space is disabled and must be enabled by writing a 1 to MCHBAREN [Dev 0, offset48h, bit 0].
+///  All the bits in this register are locked in LT mode.
+///  The register space contains memory control, initialization, timing, and buffer strength registers; clocking registers; and power and thermal management registers.
+///
+#define R_SA_MCHBAR  (0x48)
+///
+/// Description of MCHBAREN (0:0)
+///  0: MCHBAR is disabled and does not claim any memory
+///  1: MCHBAR memory mapped accesses are claimed and decoded appropriately
+///  This register is locked by LT.
+///
+#define N_SA_MCHBAR_MCHBAREN_OFFSET  (0x0)
+#define S_SA_MCHBAR_MCHBAREN_WIDTH   (0x1)
+#define B_SA_MCHBAR_MCHBAREN_MASK    (0x1)
+#define V_SA_MCHBAR_MCHBAREN_DEFAULT (0x0)
+///
+/// Description of MCHBAR (15:38)
+///  This field corresponds to bits 38 to 15 of the base address Host Memory Mapped configuration space.  BIOS will program this register resulting in a base address for a 32KB block of contiguous memory address space.  This register ensures that a naturally aligned 32KB space is allocated within the first 512GB of addressable memory space. System Software uses this base address to program the Host Memory Mapped register set. All the bits in this register are locked in LT mode.
+///
+#define N_SA_MCHBAR_MCHBAR_OFFSET  (0xf)
+#define S_SA_MCHBAR_MCHBAR_WIDTH   (0x18)
+#define B_SA_MCHBAR_MCHBAR_MASK    (0x7fffff8000ULL)
+#define V_SA_MCHBAR_MCHBAR_DEFAULT (0x0)
+
+///
+/// Description:
+///  All the bits in this register are LT lockable.
+///
+#define R_SA_GGC (0x50)
+///
+/// Description of GGCLCK (0:0)
+///  When set to 1b, this bit will lock all bits in this register.
+///
+#define N_SA_GGC_GGCLCK_OFFSET   (0x0)
+#define S_SA_GGC_GGCLCK_WIDTH    (0x1)
+#define B_SA_GGC_GGCLCK_MASK     (0x1)
+#define V_SA_GGC_GGCLCK_DEFAULT  (0x0)
+///
+/// Description of IVD (1:1)
+///  0: Enable.  Device 2 (IGD) claims VGA memory and IO cycles, the Sub-Class Code within Device 2 Class Code register is 00.
+///  1: Disable.  Device 2 (IGD) does not claim VGA cycles (Mem and IO), and the Sub- Class Code field within Device 2 function 0 Class Code register is 80.
+///  BIOS Requirement:  BIOS must not set this bit to 0 if the GMS field (bits 7:3 of this register) pre-allocates no memory.
+///  This bit MUST be set to 1 if Device 2 is disabled either via a fuse or fuse override (CAPID0[46] = 1) or via a register (DEVEN[3] = 0).
+///  This register is locked by LT lock.
+///
+#define N_SA_GGC_IVD_OFFSET  (0x1)
+#define S_SA_GGC_IVD_WIDTH   (0x1)
+#define B_SA_GGC_IVD_MASK    (0x2)
+#define V_SA_GGC_IVD_DEFAULT (0x0)
+///
+/// Description of GMS (3:7)
+///  This field is used to select the amount of Main Memory that is pre-allocated to support the Internal Graphics device in VGA (non-linear) and Native (linear) modes.  The BIOS ensures that memory is pre-allocated only when Internal graphics is enabled.
+///  This register is also LT lockable.
+///  00000b:    0MB
+///  00001b:   32MB
+///  00010b:   64MB
+///  00011b:   96MB
+///  00100b:  128MB
+///  00101b:  160MB
+///  00110b:  192MB
+///  00111b:  224MB
+///  01000b:  256MB
+///  01001b:  288MB
+///  01010b:  320MB
+///  01011b:  352MB
+///  01100b:  384MB
+///  01101b:  416MB
+///  01110b:  448MB
+///  01111b:  480MB
+///  10000b:  512MB
+///  All other values are reserved
+///  Hardware does not clear or set any of these bits automatically based on IGD being disabled/enabled.
+///  BIOS Requirement: BIOS must not set this field to 0h if IVD (bit 1 of this register) is 0.
+///
+#define N_SA_GGC_GMS_OFFSET  (0x3)
+#define S_SA_GGC_GMS_WIDTH   (0x5)
+#define B_SA_GGC_GMS_MASK    (0xf8)
+#define V_SA_GGC_GMS_DEFAULT (0x28)
+#define V_SA_GGC_GMS_DIS     0
+#define V_SA_GGC_GMS_32MB    1
+#define V_SA_GGC_GMS_64MB    2
+#define V_SA_GGC_GMS_96MB    3
+#define V_SA_GGC_GMS_128MB   4
+#define V_SA_GGC_GMS_160MB   5
+#define V_SA_GGC_GMS_192MB   6
+#define V_SA_GGC_GMS_224MB   7
+#define V_SA_GGC_GMS_256MB   8
+#define V_SA_GGC_GMS_288MB   9
+#define V_SA_GGC_GMS_320MB   0x0a
+#define V_SA_GGC_GMS_352MB   0x0b
+#define V_SA_GGC_GMS_384MB   0x0c
+#define V_SA_GGC_GMS_416MB   0x0d
+#define V_SA_GGC_GMS_448MB   0x0e
+#define V_SA_GGC_GMS_480MB   0x0f
+#define V_SA_GGC_GMS_512MB   0x10
+
+///
+/// Description of GGMS (8:9)
+///  This field is used to select the amount of Main Memory that is pre-allocated to support the Internal Graphics Translation Table.  The BIOS ensures that memory is pre-allocated only when Internal graphics is enabled.
+///  GSM is assumed to be a contiguous physical DRAM space with DSM, and BIOS needs to allocate a contiguous memory chunk.  Hardware will derive the base of GSM from DSM only using the GSM size programmed in the register.
+///  0h: No memory pre-allocated. GTT cycles (Mem and IO) are not claimed.
+///  1h: 1 MB of memory pre-allocated for GTT.
+///  2h: 2 MB of memory pre-allocated for GTT.
+///  3h: Reserved
+///  Hardware functionality in case of programming this value to Reserved is not guaranteed.
+///
+#define N_SA_GGC_GGMS_OFFSET  (0x8)
+#define S_SA_GGC_GGMS_WIDTH   (0x2)
+#define B_SA_GGC_GGMS_MASK    (0x300)
+#define V_SA_GGC_GGMS_DEFAULT (0x0)
+#define V_SA_GGC_GGMS_DIS     0
+#define V_SA_GGC_GGMS_1MB     1
+#define V_SA_GGC_GGMS_2MB     2
+
+///
+/// Description of VAMEN (14:14)
+///  Enables the use of the iGFX enbines for Versatile Acceleration.
+///  1 - iGFX engines are in Versatile Acceleration Mode.  Device 2 Class Code is 048000h.
+///  0 - iGFX engines are in iGFX Mode.  Device 2 Class Code is 030000h.
+///
+#define N_SA_GGC_VAMEN_OFFSET  (0xe)
+#define S_SA_GGC_VAMEN_WIDTH   (0x1)
+#define B_SA_GGC_VAMEN_MASK    (0x4000)
+#define V_SA_GGC_VAMEN_DEFAULT (0x0)
+
+///
+/// Description:
+///  Allows for enabling/disabling of PCI devices and functions that are within the CPU package. The table below the bit definitions describes the behavior of all combinations of transactions to devices controlled by this register.
+///  All the bits in this register are LT Lockable.
+///
+#define R_SA_DEVEN (0x54)
+///
+/// Description of D0EN (0:0)
+///  Bus 0 Device 0 Function 0 may not be disabled and is therefore hardwired to 1.
+///
+#define N_SA_DEVEN_D0EN_OFFSET   (0x0)
+#define S_SA_DEVEN_D0EN_WIDTH    (0x1)
+#define B_SA_DEVEN_D0EN_MASK     (0x1)
+#define V_SA_DEVEN_D0EN_DEFAULT  (0x1)
+///
+/// Description of D1F2EN (1:1)
+///  0: Bus 0 Device 1 Function 2 is disabled and hidden.
+///  1: Bus 0 Device 1 Function 2 is enabled and visible.
+///  This bit will remain 0 if PEG12 capability is disabled.
+///
+#define N_SA_DEVEN_D1F2EN_OFFSET   (0x1)
+#define S_SA_DEVEN_D1F2EN_WIDTH    (0x1)
+#define B_SA_DEVEN_D1F2EN_MASK     (0x2)
+#define V_SA_DEVEN_D1F2EN_DEFAULT  (0x2)
+///
+/// Description of D1F1EN (2:2)
+///  0: Bus 0 Device 1 Function 1 is disabled and hidden.
+///  1: Bus 0 Device 1 Function 1 is enabled and visible.
+///  This bit will remain 0 if PEG11 capability is disabled.
+///
+#define N_SA_DEVEN_D1F1EN_OFFSET   (0x2)
+#define S_SA_DEVEN_D1F1EN_WIDTH    (0x1)
+#define B_SA_DEVEN_D1F1EN_MASK     (0x4)
+#define V_SA_DEVEN_D1F1EN_DEFAULT  (0x4)
+///
+/// Description of D1F0EN (3:3)
+///  0: Bus 0 Device 1 Function 0 is disabled and hidden.
+///  1: Bus 0 Device 1 Function 0 is enabled and visible.
+///  This bit will remain 0 if PEG10 capability is disabled.
+///
+#define N_SA_DEVEN_D1F0EN_OFFSET   (0x3)
+#define S_SA_DEVEN_D1F0EN_WIDTH    (0x1)
+#define B_SA_DEVEN_D1F0EN_MASK     (0x8)
+#define V_SA_DEVEN_D1F0EN_DEFAULT  (0x8)
+///
+/// Description of D2EN (4:4)
+///  0:  Bus 0 Device 2 is disabled and hidden
+///  1:  Bus 0 Device 2 is enabled and visible
+///  This bit will remain 0 if Device 2 capability is disabled.
+///
+#define N_SA_DEVEN_D2EN_OFFSET   (0x4)
+#define S_SA_DEVEN_D2EN_WIDTH    (0x1)
+#define B_SA_DEVEN_D2EN_MASK     (0x10)
+#define V_SA_DEVEN_D2EN_DEFAULT  (0x10)
+///
+/// Description of D3EN (5:5)
+///  0:  Bus 0 Device 3 is disabled and hidden
+///  1:  Bus 0 Device 3 is enabled and visible
+///  This bit will remain 0 if Device 3 capability is disabled.
+///
+#define N_SA_DEVEN_D3EN_OFFSET   (0x5)
+#define S_SA_DEVEN_D3EN_WIDTH    (0x1)
+#define B_SA_DEVEN_D3EN_MASK     (0x20)
+#define V_SA_DEVEN_D3EN_DEFAULT  (0x20)
+///
+/// Description of D4EN (7:7)
+///  0: Bus 0 Device 4 is disabled and not visible.
+///  1: Bus 0 Device 4 is enabled and visible.
+///  This bit will remain 0 if Device 4 capability is disabled.
+///
+#define N_SA_DEVEN_D4EN_OFFSET   (0x7)
+#define S_SA_DEVEN_D4EN_WIDTH    (0x1)
+#define B_SA_DEVEN_D4EN_MASK     (0x80)
+#define V_SA_DEVEN_D4EN_DEFAULT  (0x80)
+///
+/// Description of D7EN (14:14)
+///  0: Bus 0 Device 7 is disabled and not visible.
+///  1: Bus 0 Device 7 is enabled and visible.
+///  Non-production BIOS code should provide a setup option to enable Bus 0 Device 7.  When enabled, Bus 0 Device 7 must be initialized in accordance to standard PCI device initialization procedures.
+///
+#define N_SA_DEVEN_D7EN_OFFSET   (0xe)
+#define S_SA_DEVEN_D7EN_WIDTH    (0x1)
+#define B_SA_DEVEN_D7EN_MASK     (0x4000)
+#define V_SA_DEVEN_D7EN_DEFAULT  (0x0)
+///
+/// Description of EPBAREN (27:27)
+///  0:  EPBAR is disabled and does not claim any memory.    1:  EPBAR memory mapped accesses are claimed and decoded approprately. This bit is Intel Reserved
+///
+#define N_SA_DEVEN_EPBAREN_OFFSET  (0x1b)
+#define S_SA_DEVEN_EPBAREN_WIDTH   (0x1)
+#define B_SA_DEVEN_EPBAREN_MASK    (0x8000000)
+#define V_SA_DEVEN_EPBAREN_DEFAULT (0x0)
+///
+/// Description of MCHBAREN (28:28)
+///  0:  MCHBAR is disabled and does not claim any memory.    1:  MCHBAR memory mapped accesses are claimed and decoded approprately. This bit is Intel Reserved
+///
+#define N_SA_DEVEN_MCHBAREN_OFFSET   (0x1c)
+#define S_SA_DEVEN_MCHBAREN_WIDTH    (0x1)
+#define B_SA_DEVEN_MCHBAREN_MASK     (0x10000000)
+#define V_SA_DEVEN_MCHBAREN_DEFAULT  (0x0)
+///
+/// Description of DMIBAREN (29:29)
+///  0:  DMIBAR is disabled and does not claim any memory.    1:  DMIBAR memory mapped accesses are claimed and decoded approprately. This bit is Intel Reserved
+///
+#define N_SA_DEVEN_DMIBAREN_OFFSET   (0x1d)
+#define S_SA_DEVEN_DMIBAREN_WIDTH    (0x1)
+#define B_SA_DEVEN_DMIBAREN_MASK     (0x20000000)
+#define V_SA_DEVEN_DMIBAREN_DEFAULT  (0x0)
+///
+/// Description of PCIEXBAREN (31:31)
+///  0:  The PCIEXBAR register is disabled. Memory read and write transactions proceed as if there were no PCIEXBAR register. PCIEXBAR bits 31:28 are R/W with no functionality behind them.    1:  The PCIEXBAR register is enabled. Memory read and write transactions whose address bits 31:28 match PCIEXBAR 31:28 will be translated to configuration reads and writes within the GMCH. These translated cycles are routed as shown in the table above.
+///
+#define N_SA_DEVEN_PCIEXBAREN_OFFSET   (0x1f)
+#define S_SA_DEVEN_PCIEXBAREN_WIDTH    (0x1)
+#define B_SA_DEVEN_PCIEXBAREN_MASK     (0x80000000)
+#define V_SA_DEVEN_PCIEXBAREN_DEFAULT  (0x0)
+///
+/// Description of RSVD (31:31)
+///
+#define N_SA_DEVEN_RSVD_OFFSET   (0x1f)
+#define S_SA_DEVEN_RSVD_WIDTH    (0x1)
+#define B_SA_DEVEN_RSVD_MASK     (0x80000000)
+#define V_SA_DEVEN_RSVD_DEFAULT  (0x0)
+
+///
+/// Description
+/// Protected Audio Video Path Control
+/// All the bits in this register are locked by LT.  When locked the R/W bits are RO.
+///
+#define R_SA_PAVPC (0x58)
+/// Description of PCME (0:0)
+///  This field enables Protected Content Memory within Graphics Stolen Memory.
+///  This register is locked (becomes read-only) when PAVPLCK = 1b.
+///  This register is read-only (stays at 0b) when PAVP fuse is set to "disabled"
+///  0: Protected Content Memory is disabled
+///  1: Protected Content Memory is enabled
+///
+#define N_SA_PAVPC_PCME_OFFSET   (0x0)
+#define S_SA_PAVPC_PCME_WIDTH    (0x1)
+#define B_SA_PAVPC_PCME_MASK     (0x1)
+#define V_SA_PAVPC_PCME_MASK     (0x0)
+///
+/// Description of PAVPE (1:1)
+///  0: PAVP path is disabled
+///  1: PAVP path is enabled
+///  This register is locked (becomes read-only) when PAVPLCK = 1b
+///  This register is read-only (stays at 0b) when PAVP capability is set to "disabled" as defined by CAPID0_B[PAVPE].
+///
+#define N_SA_PAVPC_PAVPE_OFFSET  (0x1)
+#define S_SA_PAVPC_PAVPE_WIDTH   (0x1)
+#define B_SA_PAVPC_PAVPE_MASK    (0x2)
+#define V_SA_PAVPC_PAVPE_DEFAULT (0x0)
+///
+/// Description of PAVPLCK (2:2)
+///  This bit will lock all writeable contents in this register when set (including itself).
+///  This bit will be locked if PAVP is fused off.
+///
+#define N_SA_PAVPC_PAVPLCK_OFFSET  (0x2)
+#define S_SA_PAVPC_PAVPLCK_WIDTH   (0x1)
+#define B_SA_PAVPC_PAVPLCK_MASK    (0x4)
+#define V_SA_PAVPC_PAVPLCK_DEFAULT (0x0)
+///
+/// Description of HVYMODSEL (3:3)
+///  1b   Serpent Mode
+///  0b   Big PCM Mode
+///
+#define N_SA_PAVPC_HVYMODSEL_OFFSET  (0x3)
+#define S_SA_PAVPC_HVYMODSEL_WIDTH   (0x1)
+#define B_SA_PAVPC_HVYMODSEL_MASK    (0x8)
+#define V_SA_PAVPC_HVYMODSEL_DEFAULT (0x0)
+///
+/// Description of WOPCMSZ (4:5)
+///  00b - 1MB (default)
+///  01b - 512KB
+///  10b - 256KB
+///  11b - 128KB
+///
+#define N_SA_PAVPC_WOPCMSZ_OFFSET  (0x4)
+#define S_SA_PAVPC_WOPCMSZ_WIDTH   (0x2)
+#define B_SA_PAVPC_WOPCMSZ_MASK    (0x30)
+#define V_SA_PAVPC_WOPCMSZ_DEFAULT (0x0)
+///
+/// Description of PCMBASE (20:31)
+///  This field is used to set the base of Protected Content Memory.
+///  This corresponds to bits 31:20 of the system memory address range, giving a 1MB granularity. This value MUST be at least 1MB above the base and below the top of stolen memory.
+///  This register is locked (becomes read-only) when PAVPE = 1b.
+///
+#define N_SA_PAVPC_PCMBASE_OFFSET  (0x14)
+#define S_SA_PAVPC_PCMBASE_WIDTH   (0xc)
+#define B_SA_PAVPC_PCMBASE_MASK    (0xfff00000)
+#define V_SA_PAVPC_PCMBASE_DEFAULT (0x0)
+
+///
+/// Description:
+/// DMA protected range register
+///
+#define R_SA_DPR (0x5c)
+///
+/// Description of LOCK (0:0)
+///  This bit will lock all writeable settings in this register, including itself.
+///
+#define N_SA_DPR_LOCK_OFFSET   (0x0)
+#define S_SA_DPR_LOCK_WIDTH    (0x1)
+#define B_SA_DPR_LOCK_MASK     (0x1)
+#define V_SA_DPR_LOCK_DEFAULT  (0x0)
+///
+/// Description of PRS (1:1)
+///  This field indicates the status of DPR.
+///  0: DPR protection disabled
+///  1: DPR protection enabled
+///
+#define N_SA_DPR_PRS_OFFSET   (0x1)
+#define S_SA_DPR_PRS_WIDTH    (0x1)
+#define B_SA_DPR_PRS_MASK     (0x2)
+#define V_SA_DPR_PRS_DEFAULT  (0x0)
+///
+/// Description of EPM (2:2)
+///  This field controls DMA accesses to the DMA Protected Range (DPR) region.
+///  0: DPR is disabled
+///  1: DPR is enabled.  All DMA requests accessing DPR region are blocked.
+///  HW reports the status of DPR enable/disable through the PRS field in this register.
+///
+#define N_SA_DPR_EPM_OFFSET  (0x2)
+#define S_SA_DPR_EPM_WIDTH   (0x1)
+#define B_SA_DPR_EPM_MASK    (0x4)
+#define V_SA_DPR_EPM_DEFAULT (0x0)
+///
+/// Description of DPRSIZE (11:4)
+///  This field is used to specify the size of memory protected from DMA access in MB
+///  The maximum amount of memory that will be protected is 255MB
+///  The Top of protected range is the base of TSEG-1
+///
+#define N_DPR_DPRSIZE_OFFSET  (0x4)
+#define V_DPR_DPRSIZE_WIDTH   (0x8)
+#define V_DPR_DPRSIZE_MASK    (0xFF0)
+#define V_DPR_DPRSIZE_DEFAULT (0x0)
+///
+/// Description of TOPOFDPR (31:20)
+///  This is the Top address 1 of DPR - Base of TSEG
+///
+#define N_SA_DPR_TOPOFDPR_OFFSET  (20)
+#define S_SA_DPR_TOPOFDPR_WIDTH   (0xC)
+#define B_SA_DPR_TOPOFDPR_MASK    (0xFFF00000)
+#define V_SA_DPR_TOPOFDPR_DEFAULT (0x0)
+
+///
+/// Description:
+///  This is the base address for the PCI Express configuration space.  This window of addresses contains the 4KB of configuration space for each PCI Express device that can potentially be part of the PCI Express Hierarchy associated with the Uncore.  There is no actual physical memory within this window of up to 256MB that can be addressed.  The actual size of this range is determined by a field in this register.
+///  Each PCI Express Hierarchy requires a PCI Express BASE register.  The Uncore supports one PCI Express Hierarchy.  The region reserved by this register does not alias to any PCI2.3 compliant memory mapped space.  For example, the range reserved for MCHBAR is outside of PCIEXBAR space.
+///  On reset, this register is disabled and must be enabled by writing a 1 to the enable field in this register.  This base address shall be assigned on a boundary consistent with the number of buses (defined by the length field in this register), above TOLUD and still within 39-bit addressable memory space.
+///  The PCI Express Base Address cannot be less than the maximum address written to the Top of physical memory register (TOLUD).  Software must guarantee that these ranges do not overlap with known ranges located above TOLUD.
+///  Software must ensure that the sum of the length of the enhanced configuration region + TOLUD + any other known ranges reserved above TOLUD is not greater than the 39-bit addessable limit of 512GB.  In general, system implementation and the number of PCI/PCI Express/PCI-X buses supported in the hierarchy will dictate the length of the region.
+///  All the bits in this register are locked in LT mode.
+///
+#define R_SA_PCIEXBAR  (0x60)
+///
+/// Description of PCIEXBAREN (0:0)
+///  0: The PCIEXBAR register is disabled.  Memory read and write transactions proceed s if there were no PCIEXBAR register.  PCIEXBAR bits 38:26 are R/W with no functionality behind them.
+///  1: The PCIEXBAR register is enabled.  Memory read and write transactions whose address bits 38:26 match PCIEXBAR will be translated to configuration reads and writes within the Uncore.  These Translated cycles are routed as shown in the above table.
+///  This register is locked by LT.
+///
+#define N_SA_PCIEXBAR_PCIEXBAREN_OFFSET  (0x0)
+#define S_SA_PCIEXBAR_PCIEXBAREN_WIDTH   (0x1)
+#define B_SA_PCIEXBAR_PCIEXBAREN_MASK    (0x1)
+#define V_SA_PCIEXBAR_PCIEXBAREN_DEFAULT (0x0)
+///
+/// Description of LENGTH (1:2)
+///  This field describes the length of this region.
+///  00: 256MB (buses 0-255).  Bits 38:28 are decoded in the PCI Express Base Address Field.
+///  01: 128MB (buses 0-127).  Bits 38:27 are decoded in the PCI Express Base Address Field.
+///  10: 64MB (buses 0-63).  Bits 38:26 are decoded in the PCI Express Base Address Field.
+///  11: Reserved.
+///  Thsi register is locked by LT.
+///
+#define N_SA_PCIEXBAR_LENGTH_OFFSET  (0x1)
+#define S_SA_PCIEXBAR_LENGTH_WIDTH   (0x2)
+#define B_SA_PCIEXBAR_LENGTH_MASK    (0x6)
+#define V_SA_PCIEXBAR_LENGTH_DEFAULT (0x0)
+///
+/// Description of ADMSK64 (26:26)
+///  This bit is either part of the PCI Express Base Address (R/W) or part of the Address Mask (RO, read 0b), depending on the value of bits [2:1] in this register.
+///
+#define N_SA_PCIEXBAR_ADMSK64_OFFSET   (0x1a)
+#define S_SA_PCIEXBAR_ADMSK64_WIDTH    (0x1)
+#define B_SA_PCIEXBAR_ADMSK64_MASK     (0x4000000)
+#define V_SA_PCIEXBAR_ADMSK64_DEFAULT  (0x0)
+///
+/// Description of ADMSK128 (27:27)
+///  This bit is either part of the PCI Express Base Address (R/W) or part of the Address Mask (RO, read 0b), depending on the value of bits [2:1] in this register.
+///
+#define N_SA_PCIEXBAR_ADMSK128_OFFSET  (0x1b)
+#define S_SA_PCIEXBAR_ADMSK128_WIDTH   (0x1)
+#define B_SA_PCIEXBAR_ADMSK128_MASK    (0x8000000)
+#define V_SA_PCIEXBAR_ADMSK128_DEFAULT (0x0)
+///
+/// Description of PCIEXBAR (28:38)
+///  This field corresponds to bits 38 to 28 of the base address for PCI Express enhanced configuration space.  BIOS will program this register resulting in a base address for a contiguous memory address space.  The size of the range is defined by bits [2:1] of this register.
+///  This Base address shall be assigned on a boundary consistent with the number of buses (defined by the Length field in this register) above TOLUD and still within the 39-bit addressable memory space.  The address bits decoded depend on the length of the region defined by this register.
+///  This register is locked by LT.
+///  The address used to access the PCI Express configuration space for a specific device can be determined as follows:
+///  PCI Express Base Address + Bus Number * 1MB + Device Number * 32KB + Function Number * 4KB
+///  This address is the beginning of the 4KB space that contains both the PCI compatible configuration space and the PCI Express extended configuration space.
+///
+#define N_SA_PCIEXBAR_PCIEXBAR_OFFSET  (0x1c)
+#define S_SA_PCIEXBAR_PCIEXBAR_WIDTH   (0xb)
+#define B_SA_PCIEXBAR_PCIEXBAR_MASK    (0x7ff0000000)
+#define V_SA_PCIEXBAR_PCIEXBAR_DEFAULT (0x0)
+
+///
+/// Description:
+///  This is the base address for the Root Complex configuration space. This window of addresses contains the Root Complex Register set for the PCI Express Hierarchy associated with the Host Bridge. There is no physical memory within this 4KB window that can be addressed. The 4KB reserved by this register does not alias to any PCI 2.3 compliant memory mapped space. On reset, the Root Complex configuration space is disabled and must be enabled by writing a 1 to DMIBAREN [Dev 0, offset 68h, bit 0] All the bits in this register are locked in LT mode.
+///
+#define R_SA_DMIBAR  (0x68)
+///
+/// Description of DMIBAREN (0:0)
+///  0: DMIBAR is disabled and does not claim any memory
+///  1: DMIBAR memory mapped accesses are claimed and decoded appropriately
+///  This register is locked by LT.
+///
+#define N_SA_DMIBAR_DMIBAREN_OFFSET  (0x0)
+#define S_SA_DMIBAR_DMIBAREN_WIDTH   (0x1)
+#define B_SA_DMIBAR_DMIBAREN_MASK    (0x1)
+#define V_SA_DMIBAR_DMIBAREN_DEFAULT (0x0)
+///
+/// Description of DMIBAR (12:38)
+///  This field corresponds to bits 38 to 12 of the base address DMI configuration space. BIOS will program this register resulting in a base address for a 4KB block of contiguous memory address space. This register ensures that a naturally aligned 4KB space is allocated within the first 512GB of addressable memory space. System Software uses this base address to program the DMI register set. All the Bits in this register are locked in LT mode.
+///
+#define N_SA_DMIBAR_DMIBAR_OFFSET  (0xc)
+#define S_SA_DMIBAR_DMIBAR_WIDTH   (0x1b)
+#define B_SA_DMIBAR_DMIBAR_MASK    (0x7ffffff000)
+#define V_SA_DMIBAR_DMIBAR_DEFAULT (0x0)
+
+///
+/// Description:
+///  This register determines the Base Address register of the memory range that is pre-allocated to the Manageability Engine.  Together with the MESEG_MASK register it controls the amount of memory allocated to the ME.
+///  This register must be initialized by the configuration software.  For the purpose of address decode address bits A[19:0] are assumed to be 0. Thus, the bottom of the defined memory address range will be aligned to a 1MB boundary.
+///  This register is locked by LT.
+///
+#define R_SA_MESEG_BASE  (0x70)
+///
+/// Description of MEBASE (20:38)
+///  Corresponds to A[38:20] of the base address memory range that is allocated to the ME.
+///
+#define N_SA_MESEG_BASE_MEBASE_OFFSET  (0x14)
+#define S_SA_MESEG_BASE_MEBASE_WIDTH   (0x13)
+#define B_SA_MESEG_BASE_MEBASE_MASK    (0x7ffff00000)
+#define V_SA_MESEG_BASE_MEBASE_DEFAULT (0xfffff00000)
+
+///
+/// Description:
+///  This register determines the Mask Address register of the memory range that is pre-allocated to the Manageability Engine.  Together with the MESEG_BASE register it controls the amount of memory allocated to the ME.
+///  This register is locked by LT.
+///
+#define R_SA_MESEG_MASK  (0x78)
+///
+/// Description of MELCK (10:10)
+///  This field indicates whether all bits in the MESEG_BASE and MESEG_MASK registers are locked.  When locked, updates to any field for these registers must be dropped.
+///
+#define N_SA_MESEG_MASK_MELCK_OFFSET   (0xa)
+#define S_SA_MESEG_MASK_MELCK_WIDTH    (0x1)
+#define B_SA_MESEG_MASK_MELCK_MASK     (0x400)
+#define V_SA_MESEG_MASK_MELCK_DEFAULT  (0x0)
+///
+/// Description of ME_STLEN_EN (11:11)
+///  Indicates whether the ME stolen  Memory range is enabled or not.
+///
+#define N_SA_MESEG_MASK_ME_STLEN_EN_OFFSET   (0xb)
+#define S_SA_MESEG_MASK_ME_STLEN_EN_WIDTH    (0x1)
+#define B_SA_MESEG_MASK_ME_STLEN_EN_MASK     (0x800)
+#define V_SA_MESEG_MASK_ME_STLEN_EN_DEFAULT  (0x0)
+///
+/// Description of MEMASK (20:38)
+///  This field indicates the bits that must match MEBASE in order to qualify as an ME Memory Range access.
+///  For example, if the field is set to 7FFFFh, then ME Memory is 1MB in size.
+///  Another example is that if the field is set to 7FFFEh, then ME Memory is 2MB in size.
+///  In other words, the size of ME Memory Range is limited to power of 2 times 1MB.
+///
+#define N_SA_MESEG_MASK_MEMASK_OFFSET  (0x14)
+#define S_SA_MESEG_MASK_MEMASK_WIDTH   (0x13)
+#define B_SA_MESEG_MASK_MEMASK_MASK    (0x7ffff00000)
+#define V_SA_MESEG_MASK_MEMASK_DEFAULT (0x0)
+
+///
+/// Description:
+///  This register controls the read, write and shadowing attributes of the BIOS range from F_0000h to F_FFFFh.  The Uncore allows programmable memory attributes on 13 legacy memory segments of various sizes in the 768KB to 1MB address range.  Seven Programmable Attribute Map (PAM) registers are used to support these features.  Cacheability of these areas is controlled via the MTRR register in the core.
+///  Two bits are used to specify memory attributes for each memory segment.  These bits apply to host accesses to the PAM areas.  These attributes are:
+///  RE - Read Enable.  When RE=1, the host read accesses to the corresponding memory segment are claimed by the Uncore and directed to main memory.  Conversely, when RE=0, the host read accesses are directed to DMI.
+///  WE - Write Enable.  When WE=1, the host write accesses to the corresponding memory segment are claimed by the Uncore and directed to main memory.  Conversely, when WE=0, the host read accesses are directed to DMI.
+///  The RE and WE attributes permit a memory segment to be Read Only, Write Only, Read/Write or Disabled.  For example, if a memory segment has RE=1 and WE=0, the segment is Read Only.
+///
+#define R_SA_PAM0  (0x80)
+///
+/// Description of HIENABLE (4:5)
+///  This field controls the steering of read and write cycles that address the BIOS area from 0F_0000h to 0F_FFFFh.
+///  00: DRAM Disabled.  All accesses are directed to DMI.
+///  01: Read Only.  All reads are sent to DRAM, all writes are forwarded to DMI.
+///  10: Write Only.  All writes are sent to DRAM, all reads are serviced by DMI.
+///  11: Normal DRAM Operation.  All reads and writes are serviced by DRAM.
+///  This register is locked by LT.
+///
+#define N_SA_PAM0_HIENABLE_OFFSET  (0x4)
+#define S_SA_PAM0_HIENABLE_WIDTH   (0x2)
+#define B_SA_PAM0_HIENABLE_MASK    (0x30)
+#define V_SA_PAM0_HIENABLE_DEFAULT (0x0)
+
+///
+/// Description:
+///  This register controls the read, write and shadowing attributes of the BIOS range from C_0000h to C_7FFFh.  The Uncore allows programmable memory attributes on 13 legacy memory segments of various sizes in the 768KB to 1MB address range.  Seven Programmable Attribute Map (PAM) registers are used to support these features.  Cacheability of these areas is controlled via the MTRR register in the core.
+///  Two bits are used to specify memory attributes for each memory segment.  These bits apply to host accesses to the PAM areas.  These attributes are:
+///  RE - Read Enable.  When RE=1, the host read accesses to the corresponding memory segment are claimed by the Uncore and directed to main memory.  Conversely, when RE=0, the host read accesses are directed to DMI.
+///  WE - Write Enable.  When WE=1, the host write accesses to the corresponding memory segment are claimed by the Uncore and directed to main memory.  Conversely, when WE=0, the host read accesses are directed to DMI.
+///  The RE and WE attributes permit a memory segment to be Read Only, Write Only, Read/Write or Disabled.  For example, if a memory segment has RE=1 and WE=0, the segment is Read Only.
+///
+#define R_SA_PAM1  (0x81)
+///
+/// Description of LOENABLE (0:1)
+///  This field controls the steering of read and write cycles that address the BIOS area from 0C0000h to 0C3FFFh.
+///  00: DRAM Disabled.  All reads are sent to DRAM.  All writes are forwarded to DMI.
+///  01: Read Only.  All reads are sent to DRAM.  All writes are forwarded to DMI.
+///  10: Write Only.  All writes are sent to DRAM.  All reads are serviced by DMI.
+///  11: Normal DRAM Operation.  All reads and writes are serviced by DRAM.
+///  This register is locked by LT.
+///
+#define N_SA_PAM1_LOENABLE_OFFSET  (0x0)
+#define S_SA_PAM1_LOENABLE_WIDTH   (0x2)
+#define B_SA_PAM1_LOENABLE_MASK    (0x3)
+#define V_SA_PAM1_LOENABLE_DEFAULT (0x0)
+///
+/// Description of HIENABLE (4:5)
+///  This field controls the steering of read and write cycles that address the BIOS area from 0C_4000h to 0C_7FFFh.
+///  00: DRAM Disabled.  All accesses are directed to DMI.
+///  01: Read Only.  All reads are sent to DRAM, all writes are forwarded to DMI.
+///  10: Write Only.  All writes are sent to DRAM, all reads are serviced by DMI.
+///  11: Normal DRAM Operation.  All reads and writes are serviced by DRAM.
+///  This register is locked by LT.
+///
+#define N_SA_PAM1_HIENABLE_OFFSET  (0x4)
+#define S_SA_PAM1_HIENABLE_WIDTH   (0x2)
+#define B_SA_PAM1_HIENABLE_MASK    (0x30)
+#define V_SA_PAM1_HIENABLE_DEFAULT (0x0)
+
+///
+/// Description:
+///  This register controls the read, write and shadowing attributes of the BIOS range from C_8000h to C_FFFFh.  The Uncore allows programmable memory attributes on 13 legacy memory segments of various sizes in the 768KB to 1MB address range.  Seven Programmable Attribute Map (PAM) registers are used to support these features.  Cacheability of these areas is controlled via the MTRR register in the core.
+///  Two bits are used to specify memory attributes for each memory segment.  These bits apply to host accesses to the PAM areas.  These attributes are:
+///  RE - Read Enable.  When RE=1, the host read accesses to the corresponding memory segment are claimed by the Uncore and directed to main memory.  Conversely, when RE=0, the host read accesses are directed to DMI.
+///  WE - Write Enable.  When WE=1, the host write accesses to the corresponding memory segment are claimed by the Uncore and directed to main memory.  Conversely, when WE=0, the host read accesses are directed to DMI.
+///  The RE and WE attributes permit a memory segment to be Read Only, Write Only, Read/Write or Disabled.  For example, if a memory segment has RE=1 and WE=0, the segment is Read Only.
+///
+#define R_SA_PAM2  (0x82)
+///
+/// Description of LOENABLE (0:1)
+///  This field controls the steering of read and write cycles that address the BIOS area from 0C8000h to 0CBFFFh.
+///  00: DRAM Disabled.  All reads are sent to DRAM.  All writes are forwarded to DMI.
+///  01: Read Only.  All reads are sent to DRAM.  All writes are forwarded to DMI.
+///  10: Write Only.  All writes are sent to DRAM.  All reads are serviced by DMI.
+///  11: Normal DRAM Operation.  All reads and writes are serviced by DRAM.
+///  This register is locked by LT.
+///
+#define N_SA_PAM2_LOENABLE_OFFSET  (0x0)
+#define S_SA_PAM2_LOENABLE_WIDTH   (0x2)
+#define B_SA_PAM2_LOENABLE_MASK    (0x3)
+#define V_SA_PAM2_LOENABLE_DEFAULT (0x0)
+///
+/// Description of HIENABLE (4:5)
+///  This field controls the steering of read and write cycles that address the BIOS area from 0CC000h to 0CFFFFh.
+///  00: DRAM Disabled.  All accesses are directed to DMI.
+///  01: Read Only.  All reads are sent to DRAM, all writes are forwarded to DMI.
+///  10: Write Only.  All writes are sent to DRAM, all reads are serviced by DMI.
+///  11: Normal DRAM Operation.  All reads and writes are serviced by DRAM.
+///  This register is locked by LT.
+///
+#define N_SA_PAM2_HIENABLE_OFFSET  (0x4)
+#define S_SA_PAM2_HIENABLE_WIDTH   (0x2)
+#define B_SA_PAM2_HIENABLE_MASK    (0x30)
+#define V_SA_PAM2_HIENABLE_DEFAULT (0x0)
+
+///
+/// Description:
+///  This register controls the read, write and shadowing attributes of the BIOS range from D0000h to D7FFFh.  The Uncore allows programmable memory attributes on 13 legacy memory segments of various sizes in the 768KB to 1MB address range.  Seven Programmable Attribute Map (PAM) registers are used to support these features.  Cacheability of these areas is controlled via the MTRR register in the core.
+///  Two bits are used to specify memory attributes for each memory segment.  These bits apply to host accesses to the PAM areas.  These attributes are:
+///  RE - Read Enable.  When RE=1, the host read accesses to the corresponding memory segment are claimed by the Uncore and directed to main memory.  Conversely, when RE=0, the host read accesses are directed to DMI.
+///  WE - Write Enable.  When WE=1, the host write accesses to the corresponding memory segment are claimed by the Uncore and directed to main memory.  Conversely, when WE=0, the host read accesses are directed to DMI.
+///  The RE and WE attributes permit a memory segment to be Read Only, Write Only, Read/Write or Disabled.  For example, if a memory segment has RE=1 and WE=0, the segment is Read Only.
+///
+#define R_SA_PAM3  (0x83)
+///
+/// Description of LOENABLE (0:1)
+///  This field controls the steering of read and write cycles that address the BIOS area from 0D0000h to 0D3FFFh.
+///  00: DRAM Disabled.  All reads are sent to DRAM.  All writes are forwarded to DMI.
+///  01: Read Only.  All reads are sent to DRAM.  All writes are forwarded to DMI.
+///  10: Write Only.  All writes are sent to DRAM.  All reads are serviced by DMI.
+///  11: Normal DRAM Operation.  All reads and writes are serviced by DRAM.
+///  This register is locked by LT.
+///
+#define N_SA_PAM3_LOENABLE_OFFSET  (0x0)
+#define S_SA_PAM3_LOENABLE_WIDTH   (0x2)
+#define B_SA_PAM3_LOENABLE_MASK    (0x3)
+#define V_SA_PAM3_LOENABLE_DEFAULT (0x0)
+///
+/// Description of HIENABLE (4:5)
+///  This field controls the steering of read and write cycles that address the BIOS area from 0D4000h to 0D7FFFh.
+///  00: DRAM Disabled.  All accesses are directed to DMI.
+///  01: Read Only.  All reads are sent to DRAM, all writes are forwarded to DMI.
+///  10: Write Only.  All writes are sent to DRAM, all reads are serviced by DMI.
+///  11: Normal DRAM Operation.  All reads and writes are serviced by DRAM.
+///  This register is locked by LT.
+///
+#define N_SA_PAM3_HIENABLE_OFFSET  (0x4)
+#define S_SA_PAM3_HIENABLE_WIDTH   (0x2)
+#define B_SA_PAM3_HIENABLE_MASK    (0x30)
+#define V_SA_PAM3_HIENABLE_DEFAULT (0x0)
+
+///
+/// Description:
+///  This register controls the read, write and shadowing attributes of the BIOS range from D8000h to DFFFFh.  The Uncore allows programmable memory attributes on 13 legacy memory segments of various sizes in the 768KB to 1MB address range.  Seven Programmable Attribute Map (PAM) registers are used to support these features.  Cacheability of these areas is controlled via the MTRR register in the core.
+///  Two bits are used to specify memory attributes for each memory segment.  These bits apply to host accesses to the PAM areas.  These attributes are:
+///  RE - Read Enable.  When RE=1, the host read accesses to the corresponding memory segment are claimed by the Uncore and directed to main memory.  Conversely, when RE=0, the host read accesses are directed to DMI.
+///  WE - Write Enable.  When WE=1, the host write accesses to the corresponding memory segment are claimed by the Uncore and directed to main memory.  Conversely, when WE=0, the host read accesses are directed to DMI.
+///  The RE and WE attributes permit a memory segment to be Read Only, Write Only, Read/Write or Disabled.  For example, if a memory segment has RE=1 and WE=0, the segment is Read Only.
+///
+#define R_SA_PAM4  (0x84)
+///
+/// Description of LOENABLE (0:1)
+///  This field controls the steering of read and write cycles that address the BIOS area from 0D8000h to 0DBFFFh.
+///  00: DRAM Disabled.  All reads are sent to DRAM.  All writes are forwarded to DMI.
+///  01: Read Only.  All reads are sent to DRAM.  All writes are forwarded to DMI.
+///  10: Write Only.  All writes are sent to DRAM.  All reads are serviced by DMI.
+///  11: Normal DRAM Operation.  All reads and writes are serviced by DRAM.
+///  This register is locked by LT.
+///
+#define N_SA_PAM4_LOENABLE_OFFSET  (0x0)
+#define S_SA_PAM4_LOENABLE_WIDTH   (0x2)
+#define B_SA_PAM4_LOENABLE_MASK    (0x3)
+#define V_SA_PAM4_LOENABLE_DEFAULT (0x0)
+///
+/// Description of HIENABLE (4:5)
+///  This field controls the steering of read and write cycles that address the BIOS area from 0DC000h to 0DFFFFh.
+///  00: DRAM Disabled.  All accesses are directed to DMI.
+///  01: Read Only.  All reads are sent to DRAM, all writes are forwarded to DMI.
+///  10: Write Only.  All writes are sent to DRAM, all reads are serviced by DMI.
+///  11: Normal DRAM Operation.  All reads and writes are serviced by DRAM.
+///  This register is locked by LT.
+///
+#define N_SA_PAM4_HIENABLE_OFFSET  (0x4)
+#define S_SA_PAM4_HIENABLE_WIDTH   (0x2)
+#define B_SA_PAM4_HIENABLE_MASK    (0x30)
+#define V_SA_PAM4_HIENABLE_DEFAULT (0x0)
+
+///
+/// Description:
+///  This register controls the read, write and shadowing attributes of the BIOS range from E_0000h to E_7FFFh.  The Uncore allows programmable memory attributes on 13 legacy memory segments of various sizes in the 768KB to 1MB address range.  Seven Programmable Attribute Map (PAM) registers are used to support these features.  Cacheability of these areas is controlled via the MTRR register in the core.
+///  Two bits are used to specify memory attributes for each memory segment.  These bits apply to host accesses to the PAM areas.  These attributes are:
+///  RE - Read Enable.  When RE=1, the host read accesses to the corresponding memory segment are claimed by the Uncore and directed to main memory.  Conversely, when RE=0, the host read accesses are directed to DMI.
+///  WE - Write Enable.  When WE=1, the host write accesses to the corresponding memory segment are claimed by the Uncore and directed to main memory.  Conversely, when WE=0, the host read accesses are directed to DMI.
+///  The RE and WE attributes permit a memory segment to be Read Only, Write Only, Read/Write or Disabled.  For example, if a memory segment has RE=1 and WE=0, the segment is Read Only.
+///
+#define R_SA_PAM5  (0x85)
+///
+/// Description of LOENABLE (0:1)
+///  This field controls the steering of read and write cycles that address the BIOS area from 0E0000h to 0E3FFFh.
+///  00: DRAM Disabled.  All reads are sent to DRAM.  All writes are forwarded to DMI.
+///  01: Read Only.  All reads are sent to DRAM.  All writes are forwarded to DMI.
+///  10: Write Only.  All writes are sent to DRAM.  All reads are serviced by DMI.
+///  11: Normal DRAM Operation.  All reads and writes are serviced by DRAM.
+///  This register is locked by LT.
+///
+#define N_SA_PAM5_LOENABLE_OFFSET  (0x0)
+#define S_SA_PAM5_LOENABLE_WIDTH   (0x2)
+#define B_SA_PAM5_LOENABLE_MASK    (0x3)
+#define V_SA_PAM5_LOENABLE_DEFAULT (0x0)
+///
+/// Description of HIENABLE (4:5)
+///  This field controls the steering of read and write cycles that address the BIOS area from 0E4000h to 0E7FFFh.
+///  00: DRAM Disabled.  All accesses are directed to DMI.
+///  01: Read Only.  All reads are sent to DRAM, all writes are forwarded to DMI.
+///  10: Write Only.  All writes are sent to DRAM, all reads are serviced by DMI.
+///  11: Normal DRAM Operation.  All reads and writes are serviced by DRAM.
+///  This register is locked by LT.
+///
+#define N_SA_PAM5_HIENABLE_OFFSET  (0x4)
+#define S_SA_PAM5_HIENABLE_WIDTH   (0x2)
+#define B_SA_PAM5_HIENABLE_MASK    (0x30)
+#define V_SA_PAM5_HIENABLE_DEFAULT (0x0)
+
+///
+/// Description:
+///  This register controls the read, write and shadowing attributes of the BIOS range from E_8000h to E_FFFFh.  The Uncore allows programmable memory attributes on 13 legacy memory segments of various sizes in the 768KB to 1MB address range.  Seven Programmable Attribute Map (PAM) registers are used to support these features.  Cacheability of these areas is controlled via the MTRR register in the core.
+///  Two bits are used to specify memory attributes for each memory segment.  These bits apply to host accesses to the PAM areas.  These attributes are:
+///  RE - Read Enable.  When RE=1, the host read accesses to the corresponding memory segment are claimed by the Uncore and directed to main memory.  Conversely, when RE=0, the host read accesses are directed to DMI.
+///  WE - Write Enable.  When WE=1, the host write accesses to the corresponding memory segment are claimed by the Uncore and directed to main memory.  Conversely, when WE=0, the host read accesses are directed to DMI.
+///  The RE and WE attributes permit a memory segment to be Read Only, Write Only, Read/Write or Disabled.  For example, if a memory segment has RE=1 and WE=0, the segment is Read Only.
+///
+#define R_SA_PAM6  (0x86)
+///
+/// Description of LOENABLE (0:1)
+///  This field controls the steering of read and write cycles that address the BIOS area from 0E8000h to 0EBFFFh.
+///  00: DRAM Disabled.  All reads are sent to DRAM.  All writes are forwarded to DMI.
+///  01: Read Only.  All reads are sent to DRAM.  All writes are forwarded to DMI.
+///  10: Write Only.  All writes are sent to DRAM.  All reads are serviced by DMI.
+///  11: Normal DRAM Operation.  All reads and writes are serviced by DRAM.
+///  This register is locked by LT.
+///
+#define N_SA_PAM6_LOENABLE_OFFSET  (0x0)
+#define S_SA_PAM6_LOENABLE_WIDTH   (0x2)
+#define B_SA_PAM6_LOENABLE_MASK    (0x3)
+#define V_SA_PAM6_LOENABLE_DEFAULT (0x0)
+///
+/// Description of HIENABLE (4:5)
+///  This field controls the steering of read and write cycles that address the BIOS area from 0EC000h to 0EFFFFh.
+///  00: DRAM Disabled.  All accesses are directed to DMI.
+///  01: Read Only.  All reads are sent to DRAM, all writes are forwarded to DMI.
+///  10: Write Only.  All writes are sent to DRAM, all reads are serviced by DMI.
+///  11: Normal DRAM Operation.  All reads and writes are serviced by DRAM.
+///  This register is locked by LT.
+///
+#define N_SA_PAM6_HIENABLE_OFFSET  (0x4)
+#define S_SA_PAM6_HIENABLE_WIDTH   (0x2)
+#define B_SA_PAM6_HIENABLE_MASK    (0x30)
+#define V_SA_PAM6_HIENABLE_DEFAULT (0x0)
+
+#define R_SA_MC_LAC_OFFSET         0x87  ///< Legacy Access Control Register
+#define R_SA_B_HEN                 0x80  ///< RW
+///
+/// Description:
+///  The SMRAMC register controls how accesses to Compatible SMRAM spaces are treated.  The Open, Close and Lock bits function only when G_SMRAME bit is set to 1.  Also, the Open bit must be reset before the Lock bit is set.
+///
+#define R_SA_SMRAMC  (0x88)
+///
+/// Description of C_BASE_SEG (0:2)
+///  This field indicates the location of SMM space.  SMM DRAM is not remapped.  It is simply made visible if the conditions are right to access SMM space, otherwise the access is forwarded to DMI.  Only SMM space bewteen A_0000h and B_FFFFh is supported, so this field is hardwired to 010b.
+///
+#define N_SA_SMRAMC_C_BASE_SEG_OFFSET  (0x0)
+#define S_SA_SMRAMC_C_BASE_SEG_WIDTH   (0x3)
+#define B_SA_SMRAMC_C_BASE_SEG_MASK    (0x7)
+#define V_SA_SMRAMC_C_BASE_SEG_DEFAULT (0x2)
+///
+/// Description of G_SMRAME (3:3)
+///  If set to '1', then Compatible SMRAM functions are enabled, providing 128KB of DRAM accessible at the A_0000h address while in SMM.  To enable Extended SMRAM function this bit has to be set to 1.  Once D_LCK is set, this bit becomes RO.
+///
+#define N_SA_SMRAMC_G_SMRAME_OFFSET  (0x3)
+#define S_SA_SMRAMC_G_SMRAME_WIDTH   (0x1)
+#define B_SA_SMRAMC_G_SMRAME_MASK    (0x8)
+#define V_SA_SMRAMC_G_SMRAME_DEFAULT (0x0)
+///
+/// Description of D_LCK (4:4)
+///  When D_LCK=1, then D_OPEN is reset to 0 and all writeable fields in this register are locked (become RO).  D_LCK can be set to 1 via a normal configuration space write but can only be cleared by a Full Reset.
+///  The combination of D_LCK and D_OPEN provide convenience with security.  The BIOS can use the D_OPEN function to initialize SMM space and then use D_LCK to "lock down" SMM space in the future so that no application software (or even BIOS itself) can violate the integrity of SMM space, even if the program has knowledge of the D_OPEN function.
+///
+#define N_SA_SMRAMC_D_LCK_OFFSET   (0x4)
+#define S_SA_SMRAMC_D_LCK_WIDTH    (0x1)
+#define B_SA_SMRAMC_D_LCK_MASK     (0x10)
+#define V_SA_SMRAMC_D_LCK_DEFAULT  (0x0)
+///
+/// Description of D_CLS (5:5)
+///  When D_CLS = 1, SMM DRAM space is not accessible to data references, even if SMM decode is active.  Code references may still access SMM DRAM space.  This will allow SMM software to reference through SMM space to update the display even when SMM is mapped over the VGA range.  Software should ensure that D_OPEN = 1 and D_CLS = 1 are not set at the same time.
+///
+#define N_SA_SMRAMC_D_CLS_OFFSET   (0x5)
+#define S_SA_SMRAMC_D_CLS_WIDTH    (0x1)
+#define B_SA_SMRAMC_D_CLS_MASK     (0x20)
+#define V_SA_SMRAMC_D_CLS_DEFAULT  (0x0)
+///
+/// Description of D_OPEN (6:6)
+///  When D_OPEN = 1 and D_LCK = 0, the SMM DRAM space is made visible even when SMM decode is not active.  This is intended to help BIOS initialize SMM space.  Software should ensure that D_OPEN = 1 and D_CLS = 1 are not set at the same time.
+///
+#define N_SA_SMRAMC_D_OPEN_OFFSET  (0x6)
+#define S_SA_SMRAMC_D_OPEN_WIDTH   (0x1)
+#define B_SA_SMRAMC_D_OPEN_MASK    (0x40)
+#define V_SA_SMRAMC_D_OPEN_DEFAULT (0x0)
+
+///
+/// Description:
+///
+#define R_SA_REMAPBASE (0x90)
+///
+/// Description of LOCK (0:0)
+///  This bit will lock all writeable settings in this register, including itself.
+///
+#define N_SA_REMAPBASE_LOCK_OFFSET   (0x0)
+#define S_SA_REMAPBASE_LOCK_WIDTH    (0x1)
+#define B_SA_REMAPBASE_LOCK_MASK     (0x1)
+#define V_SA_REMAPBASE_LOCK_DEFAULT  (0x0)
+///
+/// Description of REMAPBASE (20:35)
+///  The value in this register defines the lower boundary of the Remap window. The Remap window is inclusive of this address. In the decoder A[19:0] of the Remap Base Address are assumed to be 0's. Thus the bottom of the defined memory range will be aligned to a 1MB boundary.
+///  When the value in this register is greater than the value programmed into the Remap Limit register, the Remap window is disabled.
+///  These bits are LT lockable.
+///
+#define N_SA_REMAPBASE_REMAPBASE_OFFSET  (0x14)
+#define S_SA_REMAPBASE_REMAPBASE_WIDTH   (0x10)
+#define B_SA_REMAPBASE_REMAPBASE_MASK    (0xffff00000)
+#define V_SA_REMAPBASE_REMAPBASE_DEFAULT (0xffff00000)
+
+///
+/// Description:
+///
+#define R_SA_REMAPLIMIT  (0x98)
+///
+/// Description of LOCK (0:0)
+///  This bit will lock all writeable settings in this register, including itself.
+///
+#define N_SA_REMAPLIMIT_LOCK_OFFSET  (0x0)
+#define S_SA_REMAPLIMIT_LOCK_WIDTH   (0x1)
+#define B_SA_REMAPLIMIT_LOCK_MASK    (0x1)
+#define V_SA_REMAPLIMIT_LOCK_DEFAULT (0x0)
+///
+/// Description of REMAPLMT (20:35)
+///  The value in this register defines the upper boundary of the Remap window. The Remap window is inclusive of this address. In the decoder A[19:0] of the remap limit address are assumed to be F's. Thus the top of the defined range will be one byte less than a 1MB boundary.
+///  When the value in this register is less than the value programmed into the Remap Base register, the Remap window is disabled.
+///  These Bits are LT lockable.
+///
+#define N_SA_REMAPLIMIT_REMAPLMT_OFFSET  (0x14)
+#define S_SA_REMAPLIMIT_REMAPLMT_WIDTH   (0x10)
+#define B_SA_REMAPLIMIT_REMAPLMT_MASK    (0xffff00000)
+#define V_SA_REMAPLIMIT_REMAPLMT_DEFAULT (0x0)
+
+///
+/// Description:
+///  This Register contains the size of physical memory.  BIOS determines the memory size reported to the OS using this Register.
+///
+#define R_SA_TOM (0xa0)
+///
+/// Description of LOCK (0:0)
+///  This bit will lock all writeable settings in this register, including itself.
+///
+#define N_SA_TOM_LOCK_OFFSET   (0x0)
+#define S_SA_TOM_LOCK_WIDTH    (0x1)
+#define B_SA_TOM_LOCK_MASK     (0x1)
+#define V_SA_TOM_LOCK_DEFAULT  (0x0)
+
+///
+/// Description of TOM (20:38)
+///  This register reflects the total amount of populated physical memory. This is NOT necessarily the highest main memory address (holes may exist in main memory address map due to addresses allocated for memory mapped IO). These bits correspond to address bits 38:20 (1MB granularity). Bits 19:0 are assumed to be 0. All the bits in this register are locked in LT mode.
+///
+#define N_SA_TOM_TOM_OFFSET  (0x14)
+#define S_SA_TOM_TOM_WIDTH   (0x13)
+#define B_SA_TOM_TOM_MASK    (0x7ffff00000)
+#define V_SA_TOM_TOM_DEFAULT (0x7ffff00000)
+
+///
+/// Description:
+///  This 64 bit register defines the Top of Upper Usable DRAM.
+///  Configuration software must set this value to TOM minus all EP stolen memory if reclaim is disabled.  If reclaim is enabled, this value must be set to reclaim limit + 1byte, 1MB aligned, since reclaim limit is 1MB aligned. Address bits 19:0 are assumed to be 000_0000h for the purposes of address comparison. The Host interface positively decodes an address towards DRAM if the incoming address is less than the value programmed in this register and greater than or equal to 4GB.
+///  BIOS Restriction: Minimum value for TOUUD is 4GB.
+///  These bits are LT lockable.
+///
+#define R_SA_TOUUD (0xa8)
+///
+/// Description of LOCK (0:0)
+///  This bit will lock all writeable settings in this register, including itself.
+///
+#define N_SA_TOUUD_LOCK_OFFSET   (0x0)
+#define S_SA_TOUUD_LOCK_WIDTH    (0x1)
+#define B_SA_TOUUD_LOCK_MASK     (0x1)
+#define V_SA_TOUUD_LOCK_DEFAULT  (0x0)
+///
+/// Description of TOUUD (20:38)
+///  This register contains bits 38  to 20 of an address one byte above the maximum DRAM memory above 4G that is usable by the operating system. Configuration software must set this value to TOM minus all EP stolen memory if reclaim is disabled. If reclaim is enabled, this value must be set to reclaim limit 1MB aligned since reclaim limit + 1byte is 1MB aligned. Address bits 19:0 are assumed to be 000_0000h for the purposes of address comparison. The Host interface positively decodes an address towards DRAM if the incoming address is less than the value programmed in this register and greater than 4GB.
+///  All the bits in this register are locked in LT mode.
+///
+#define N_SA_TOUUD_TOUUD_OFFSET  (0x14)
+#define S_SA_TOUUD_TOUUD_WIDTH   (0x13)
+#define B_SA_TOUUD_TOUUD_MASK    (0x7ffff00000ULL)
+#define V_SA_TOUUD_TOUUD_DEFAULT (0x0)
+
+///
+/// Description:
+///  This register contains the base address of graphics data stolen DRAM memory. BIOS determines the base of graphics data stolen memory by subtracting the graphics data stolen memory size (PCI Device 0 offset 52 bits 7:4) from TOLUD (PCI Device 0 offset BC bits 31:20).
+///
+#define R_SA_BDSM  (0xb0)
+///
+/// Description of LOCK (0:0)
+///  This bit will lock all writeable settings in this register, including itself.
+///
+#define N_SA_BDSM_LOCK_OFFSET  (0x0)
+#define S_SA_BDSM_LOCK_WIDTH   (0x1)
+#define B_SA_BDSM_LOCK_MASK    (0x1)
+#define V_SA_BDSM_LOCK_DEFAULT (0x0)
+///
+/// Description of BDSM (20:31)
+///  This register contains bits 31 to 20 of the base address of stolen DRAM memory. BIOS determines the base of graphics stolen memory by subtracting the graphics stolen memory size (PCI Device 0 offset 52 bits 6:4) from TOLUD (PCI Device 0 offset BC bits 31:20).
+///
+#define N_SA_BDSM_BDSM_OFFSET  (0x14)
+#define S_SA_BDSM_BDSM_WIDTH   (0xc)
+#define B_SA_BDSM_BDSM_MASK    (0xfff00000)
+#define V_SA_BDSM_BDSM_DEFAULT (0x0)
+
+///
+/// Description:
+///  This register contains the base address of stolen DRAM memory for the GTT. BIOS determines the base of GTT stolen memory by subtracting the GTT graphics stolen memory size (PCI Device 0 offset 52 bits 9:8) from the Graphics Base of  Data Stolen Memory (PCI Device 0 offset B0 bits 31:20).
+///
+#define R_SA_BGSM  (0xb4)
+///
+/// Description of LOCK (0:0)
+///  This bit will lock all writeable settings in this register, including itself.
+///
+#define N_SA_BGSM_LOCK_OFFSET  (0x0)
+#define S_SA_BGSM_LOCK_WIDTH   (0x1)
+#define B_SA_BGSM_LOCK_MASK    (0x1)
+#define V_SA_BGSM_LOCK_DEFAULT (0x0)
+///
+/// Description of BGSM (20:31)
+///  This register contains the base address of stolen DRAM memory for the GTT. BIOS determines the base of GTT stolen memory by subtracting the GTT graphics stolen memory size (PCI Device 0 offset 52 bits 11:8) from the Graphics Base of  Data Stolen Memory (PCI Device 0 offset B0 bits 31:20).
+///
+#define N_SA_BGSM_BGSM_OFFSET  (0x14)
+#define S_SA_BGSM_BGSM_WIDTH   (0xc)
+#define B_SA_BGSM_BGSM_MASK    (0xfff00000)
+#define V_SA_BGSM_BGSM_DEFAULT (0x0)
+
+///
+/// Description:
+///  This register contains the base address of TSEG DRAM memory. BIOS determines the base of TSEG memory which must be at or below Graphics Base of GTT Stolen Memory (PCI Device 0 Offset B4 bits 31:20).
+///
+#define R_SA_TSEGMB  (0xb8)
+///
+/// Description of LOCK (0:0)
+///  This bit will lock all writeable settings in this register, including itself.
+///
+#define N_SA_TSEGMB_LOCK_OFFSET  (0x0)
+#define S_SA_TSEGMB_LOCK_WIDTH   (0x1)
+#define B_SA_TSEGMB_LOCK_MASK    (0x1)
+#define V_SA_TSEGMB_LOCK_DEFAULT (0x0)
+///
+/// Description of TSEGMB (20:31)
+///  This register contains the base address of TSEG DRAM memory. BIOS determines the base of TSEG memory which must be at or below Graphics Base of GTT Stolen Memory (PCI Device 0 Offset B4 bits 31:20).
+///
+#define N_SA_TSEGMB_TSEGMB_OFFSET  (0x14)
+#define S_SA_TSEGMB_TSEGMB_WIDTH   (0xc)
+#define B_SA_TSEGMB_TSEGMB_MASK    (0xfff00000)
+#define V_SA_TSEGMB_TSEGMB_DEFAULT (0x0)
+
+///
+/// Description:
+///  This register contains the Top of low memory address.
+///
+#define R_SA_TOLUD (0xbc)
+///
+/// Description of LOCK (0:0)
+///  This bit will lock all writeable settings in this register, including itself.
+///
+#define N_SA_TOLUD_LOCK_OFFSET   (0x0)
+#define S_SA_TOLUD_LOCK_WIDTH    (0x1)
+#define B_SA_TOLUD_LOCK_MASK     (0x1)
+#define V_SA_TOLUD_LOCK_DEFAULT  (0x0)
+///
+/// Description of TOLUD (20:31)
+///  This register contains bits 31 to 20 of an address one byte above the maximum DRAM memory below 4G that is usable by the operating system. Address bits 31 down to 20 programmed to 01h implies a minimum memory size of 1MB. Configuration software must set this value to the smaller of the following 2 choices: maximum amount memory in the system minus ME stolen memory plus one byte or the minimum address allocated for PCI memory. Address bits 19:0 are assumed to be 0_0000h for the purposes of address comparison. The Host interface positively decodes an address towards DRAM if the incoming address is less than the value programmed in this register.
+///  The Top of Low Usable DRAM is the lowest address above both Graphics Stolen memory and Tseg. BIOS determines the base of Graphics Stolen Memory by subtracting the Graphics Stolen Memory Size from TOLUD and further decrements by Tseg size to determine base of Tseg. All the Bits in this register are locked in LT mode.
+///  This register must be 1MB aligned when reclaim is enabled.
+///
+#define N_SA_TOLUD_TOLUD_OFFSET    (0x14)
+#define S_SA_TOLUD_TOLUD_WIDTH     (0xc)
+#define B_SA_TOLUD_TOLUD_MASK      (0xfff00000)
+#define V_SA_TOLUD_TOLUD_DEFAULT   (0x100000)
+
+#define R_SA_MC_ERRSTS_OFFSET      0xC8    ///< Error Status Register
+#define B_GMSWSMI                  0x1000  ///< Software SMI
+#define R_SA_MC_ERRCMD_OFFSET      0xCA    ///< Error Command Register
+#define R_SA_MC_SKPD_OFFSET        0xDC    ///< Scratch Pad Data
+#define R_SA_MC_CAPID0_OFFSET      0xE0    ///< Capability Identification @bug reserved in EDS
+#define R_SA_MC_CAPID0_A_OFFSET    0xE4
+
+//
+// MCHBAR IO Register Offset Equates
+//
+#define R_SA_MCHBAR_PAVPC_OFFSET                   0x34    ///< PAPVC
+#define R_SA_MCHBAR_PCIE_CODE_VERSION_OFFSET_HSW   0x5434
+#define R_SA_MCHBAR_BIOS_RESET_CPL_OFFSET          0x5DA8
+#define R_SA_MCHBAR_SAPMCTL_OFFSET                 0x5F00
+#define R_SA_MCHBAR_GDXCBAR_OFFSET                 0x5420
+#define R_SA_MCHBAR_EDRAMBAR_OFFSET                0x5408
+#define R_SA_MCHBAR_ILTR_OVRD_OFFSET               0x5D30
+#define R_SA_MCHBAR_CRDTCTL0_OFFSET                0x7400
+#define R_SA_MCHBAR_CRDTCTL1_OFFSET                0x7404
+#define R_SA_MCHBAR_CRDTCTL2_OFFSET                0x7408
+#define R_SA_MCHBAR_CRDTCTL3_OFFSET                0x740C
+#define R_SA_MCHBAR_CRDTCTL4_OFFSET                0x7410
+#define R_SA_MCHBAR_CRDTCTL6_OFFSET                0x7418
+#define R_SA_MCHBAR_CRDTCTL8_OFFSET                0x7454
+
+#define V_SA_LTR_MAX_SNOOP_LATENCY_VALUE           0x0846  ///< Intel recommended maximum value for Snoop Latency (70us)
+#define V_SA_LTR_MAX_NON_SNOOP_LATENCY_VALUE       0x0846  ///< Intel recommended maximum value for Non-Snoop Latency (70us)
+
+//
+// Thermal Management Controls
+//
+//
+// Device 1 Memory Mapped IO Register Offset Equates
+//
+#define V_SA_PEG_VID     0x8086
+#define V_SA_PEG_DID     0x2A41
+
+///
+/// Device 1 Register Equates
+///
+#define R_SA_PEG_VID_OFFSET            0x00  ///< Vendor ID
+#define R_SA_PEG_DID_OFFSET            0x02  ///< Device ID
+#define R_SA_PEG_BCTRL_OFFSET          0x3E  ///< Bridge Control
+#define R_SA_PEG_SSCAPID_OFFSET        0x88  ///< Subsystem ID and Vendor ID Capabilities IS
+#define R_SA_PEG_SS_OFFSET             0x8C  ///< Subsystem ID
+#define R_SA_PEG_MSICAPID_OFFSET       0x90  ///< MSI Capabilities ID
+#define R_SA_PEG_MC_OFFSET             0x92  ///< Message Control
+#define R_SA_PEG_MA_OFFSET             0x94  ///< Message Address
+#define R_SA_PEG_MD_OFFSET             0x98  ///< Message Data
+#define R_SA_PEG_CAPL_OFFSET           0xA0  ///< PEG Capabilities List
+#define R_SA_PEG_CAP_OFFSET            0xA2  ///< PEG Capabilities
+#define R_SA_PEG_DCAP_OFFSET           0xA4  ///< Device Capabilities
+#define R_SA_PEG_DCTL_OFFSET           0xA8  ///< Device Control
+#define R_SA_PEG_DSTS_OFFSET           0xAA  ///< Device Status
+#define R_SA_PEG_LCAP_OFFSET           0xAC  ///< Link Capabilities
+#define R_SA_PEG_LCTL_OFFSET           0xB0  ///< Link Control
+#define R_SA_PEG_LSTS_OFFSET           0xB2  ///< Link Status
+#define R_SA_PEG_SLOTCAP_OFFSET        0xB4  ///< Slot Capabilities
+#define R_SA_PEG_SLOTCTL_OFFSET        0xB8  ///< Slot Control
+#define R_SA_PEG_SLOTSTS_OFFSET        0xBA  ///< Slot Status
+#define R_SA_PEG_RCTL_OFFSET           0xBC  ///< Root Control
+#define R_SA_PEG_RSTS_OFFSET           0xC0  ///< Root Status
+#define R_SA_PEG_DCAP2_OFFSET          0xC4  ///< Device Capability 2
+#define R_SA_PEG_DCTL2_OFFSET          0xC8  ///< Device Control 2
+#define R_SA_PEG_LCTL2_OFFSET          0xD0  ///< Link Control 2
+#define R_SA_PEG_LSTS2_OFFSET          0xD2  ///< Link Status 2
+#define R_SA_PEG_PEGLC_OFFSET          0xEC  ///< PEG Legacy Control
+#define R_SA_PEG_VCECH_OFFSET          0x100 ///< PEG Virtual Channel Enhanced Capability
+#define R_SA_PEG_VCCAP1_OFFSET         0x104 ///< PEG Port VC Capability
+#define R_SA_PEG_VCCAP2_OFFSET         0x108 ///< PEG Port VC Capability 2
+#define R_SA_PEG_VCCTL_OFFSET          0x10C ///< PEG Port VC Control
+#define R_SA_PEG_VC0RCAP_OFFSET        0x110 ///< PEG VC0 Resource Capability
+#define R_SA_PEG_VC0RCTL0_OFFSET       0x114 ///< PEG VC0 Resource Control
+#define R_SA_PEG_VC0RSTS_OFFSET        0x11A ///< PEG VC0 Resource Status
+#define R_SA_PEG_VC1RCAP_OFFSET        0x11C ///< PEG VC1 Resource Capability
+#define R_SA_PEG_VC1RCTL1_OFFSET       0x120 ///< PEG VC1 Resource Control
+#define R_SA_PEG_VC1RSTS_OFFSET        0x126 ///< PEG VC1 Resource Status
+#define R_SA_PEG_RCLDECH_OFFSET        0x140 ///< PEG Root Complex Link Declaration
+#define R_SA_PEG_ESD_OFFSET            0x144 ///< PEG Element Self Description
+#define R_SA_PEG_LE1D_OFFSET           0x150 ///< PEG Link Entry 1 Description
+#define R_SA_PEG_LE1A_OFFSET           0x158 ///< PEG Link Entry 1 Address
+#define R_SA_PEG_PEGUESTS_OFFSET       0x1C4 ///< PEG Error Status
+#define R_SA_PEG_PEGCESTS_OFFSET       0x1D0 ///< PEG Error Status
+#define R_SA_PEG_PEGSTS_OFFSET         0x214 ///< PEG Status
+#define R_SA_PEG_LTSSMC_OFFSET         0x224 ///< PEG LTSSMC Control
+#define R_SA_PEG_L0SLAT_OFFSET         0x22C ///< PEG L0s Control
+#define R_SA_PEG_CFG2_OFFSET           0x250 ///< PEG Config 2
+#define R_SA_PEG_CFG4_OFFSET           0x258 ///< PEG Config 4
+#define R_SA_PEG_CFG5_OFFSET           0x25C ///< PEG Config 5
+#define R_SA_PEG_CFG6_OFFSET           0x260 ///< PEG Config 6
+#define R_SA_PEG_VC0PRCA_OFFSET        0x308 ///< PEG VC0 Posted
+#define R_SA_PEG_VC0NPRCA_OFFSET       0x314 ///< PEG VC0 Non-Posted
+#define R_SA_PEG_VC0CCL_OFFSET         0x31C ///< PEG Completion Credit Limit
+#define R_SA_PEG_VC01CL_OFFSET         0x320 ///< PEG Chaining Limit
+#define R_SA_PEG_VC1PRCA_OFFSET        0x32C ///< PEG VC1 Posted
+#define R_SA_PEG_VC1NPRCA_OFFSET       0x330 ///< PEG VC1 Non-Posted
+#define R_SA_PEG_REUT_PH_CTR1_OFFSET   0x448 ///< PEG PHY Control
+#define R_SA_PEG_REUT_PH1_PIS_OFFSET   0x464 ///< PEG PH1 PIS
+#define R_SA_PEG_REUT_OVR_CTL_OFFSET   0x490 ///< PEG REUT Override
+#define R_SA_PEG_FUSESCMN_OFFSET       0x504 ///< PEG Fuses
+#define R_SA_PEG_AFEBND0CFG5_OFFSET    0x80C ///< PEG AFE Bundle Config 5
+#define R_SA_PEG_EQPH3_OFFSET          0x814 ///< PEG Phase 3
+#define R_SA_PEG_AFEBND0CFG0_OFFSET    0x900 ///< PEG AFE Bundle Config 0
+#define R_SA_PEG_AFEBND0CFG1_OFFSET    0x904 ///< PEG AFE Bundle Config 1
+#define R_SA_PEG_AFEBND0CFG2_OFFSET    0x908 ///< PEG AFE Bundle Config 2
+#define R_SA_PEG_AFEBND0CFG3_OFFSET    0x90C ///< PEG AFE Bundle Config 3
+#define R_SA_PEG_AFEBND0CFG4_OFFSET    0x910 ///< PEG AFE Bundle Config 4
+#define R_SA_PEG_LOADBUSCTL0_OFFSET    0x914 ///< PEG Load Bus Control
+#define R_SA_PEG_G3CTL0_OFFSET         0x918 ///< PEG Gen3 Control
+#define R_SA_PEG_BND0SPARE_OFFSET      0x91C ///< PEG Bundle 0 Spare Register
+#define R_SA_PEG_AFELN0CFG0_OFFSET     0xA00 ///< PEG AFE Lane Config 0
+#define R_SA_PEG_AFELN0CFG1_OFFSET     0xA04 ///< PEG AFE Lane Config 1
+#define R_SA_PEG_AFEOVR_OFFSET         0xC20 ///< PEG AFE Override
+#define R_SA_PEG_AFE_PWRON_OFFSET      0xC24 ///< PEG AFE Power-on
+#define R_SA_PEG_AFE_PM_TMR_OFFSET     0xC28 ///< PEG AFE PM Timer
+#define R_SA_PEG_CMNRXERR_OFFSET       0xC34 ///< PEG Common Error
+#define R_SA_PEG_CMNSPARE_OFFSET       0xC38 ///< PEG Common Spare
+#define R_SA_PEG_PEGTST_OFFSET         0xD0C ///< PEG TEST
+#define R_SA_PEG_DEBUP2_OFFSET         0xD10 ///< PEG Debug
+#define R_SA_PEG_DEBUP3_OFFSET         0xD14 ///< PEG Debug
+#define R_SA_PEG_PEGCOMLCGCTRL_OFFSET  0xD20 ///< PEG Clock Gating Control
+#define R_SA_PEG_FCLKGTTLLL_OFFSET     0xD24 ///< PEG FCLK Clock Gating
+#define R_SA_PEG_LCTL3_OFFSET          0xD98 ///< PEG Link Control 3
+#define R_SA_PEG_LNERRSTAT_OFFSET      0xD9C ///< PEG Lane Error Status
+#define R_SA_PEG_EQCTL0_1_OFFSET       0xDA0 ///< PEG Lane Equalization
+#define R_SA_PEG_EQCFG_OFFSET          0xDD8 ///< PEG Equalization Config
+#define R_SA_PEG_PLUCTLH0_OFFSET       0xE0C ///< PEG Lane Config
+
+///
+/// Device 2 Register Equates
+//
+// The following equates must be reviewed and revised when the specification is ready.
+//
+#define SA_IGD_BUS           0x00
+#define SA_IGD_DEV           0x02
+#define SA_IGD_FUN_0         0x00
+#define SA_IGD_FUN_1         0x01
+#define SA_IGD_DEV_FUN       (SA_IGD_DEV << 3)
+#define SA_IGD_BUS_DEV_FUN   (SA_MC_BUS << 8) + SA_IGD_DEV_FUN
+
+#define V_SA_IGD_VID         0x8086
+#define V_SA_IGD_DID         0x2A42
+#define V_SA_IGD_DID_MB      0x0106
+#define V_SA_IGD_DID_MB_1    0x0116
+#define V_SA_IGD_DID_MB_2    0x0126
+#define V_SA_IGD_DID_DT      0x0102
+#define V_SA_IGD_DID_DT_1    0x0112
+#define V_SA_IGD_DID_DT_2    0x0122
+#define V_SA_IGD_DID_DT_3    0x010A
+
+///
+/// For HSW IGD
+///
+#define V_SA_PCI_DEV_2_HSM_ID      0x00C06 ///< Dev2-HSW GT-L Mobile
+#define V_SA_PCI_DEV_2_GT_HSM_ID   0x00C16 ///< Dev2-HSW GT-M Mobile
+#define V_SA_PCI_DEV_2_GT2P_HSM_ID 0x00C26 ///< Dev2-HSW GT-H Mobile
+#define V_SA_PCI_DEV_2_HSD_ID      0x00C02 ///< Dev2-HSW GT-L Desktop
+#define V_SA_PCI_DEV_2_GT_HSD_ID   0x00C12 ///< Dev2-HSW GT-M Desktop
+#define V_SA_PCI_DEV_2_GT2P_HSD_ID 0x00C22 ///< Dev2-HSW GT-H Desktop
+#define V_SA_PCI_DEV_2_HSS_ID      0x00C0A ///< Dev2-HSW GT-L Server
+#define V_SA_PCI_DEV_2_GT_HSS_ID   0x00C1A ///< Dev2-HSW GT-M Server
+#define V_SA_PCI_DEV_2_GT2P_HSS_ID 0x00C2A ///< Dev2-HSW GT-H Server
+
+#define V_SA_PCI_DEV_2_GT1_HSM_ID  0x00406 ///< Dev2-HSW GT1-H Mobile
+#define V_SA_PCI_DEV_2_GT2_HSM_ID  0x00416 ///< Dev2-HSW GT2-M Mobile
+#define V_SA_PCI_DEV_2_GT3_HSM_ID  0x00426 ///< Dev2-HSW GT3-H Mobile
+#define V_SA_PCI_DEV_2_GT1_HSD_ID  0x00402 ///< Dev2-HSW GT1 Desktop
+#define V_SA_PCI_DEV_2_GT2_HSD_ID  0x00412 ///< Dev2-HSW GT2 Desktop
+#define V_SA_PCI_DEV_2_GT3_HSD_ID  0x00422 ///< Dev2-HSW GT3 Desktop
+#define V_SA_PCI_DEV_2_GT15_HSD_ID 0x0041E ///< Dev2-HSW GT1.5 Desktop
+#define V_SA_PCI_DEV_2_GT1_HSS_ID  0x0040A ///< Dev2-HSW GT1 Server
+#define V_SA_PCI_DEV_2_GT2_HSS_ID  0x0041A ///< Dev2-HSW GT2 Server
+#define V_SA_PCI_DEV_2_GT3_HSS_ID  0x0042A ///< Dev2-HSW GT3 Server
+///
+/// For HSW ULT
+///
+#define V_SA_PCI_DEV_2_GT1_HUM_ID  0x00A06 ///< Dev2-HSW ULT GT1 Mobile
+#define V_SA_PCI_DEV_2_GT2_HUM_ID  0x00A16 ///< Dev2-HSW ULT GT2 Mobile
+#define V_SA_PCI_DEV_2_GT3_HUM_ID  0x00A26 ///< Dev2-HSW ULT GT3 Mobile
+#define V_SA_PCI_DEV_2_GT3_HXM_ID  0x00A2E ///< Dev2-HSW ULT GT3 Mobile
+#define V_SA_PCI_DEV_2_GT1_HUD_ID  0x00A02 ///< Dev2-HSW ULT GT1 Desktop
+#define V_SA_PCI_DEV_2_GT2_HUD_ID  0x00A12 ///< Dev2-HSW ULT GT2 Desktop
+#define V_SA_PCI_DEV_2_GT3_HUD_ID  0x00A22 ///< Dev2-HSW ULT GT3 Desktop
+#define V_SA_PCI_DEV_2_GT1_HUS_ID  0x00A0A ///< Dev2-HSW ULT GT1 Server
+#define V_SA_PCI_DEV_2_GT2_HUS_ID  0x00A1A ///< Dev2-HSW ULT GT2 Server
+#define V_SA_PCI_DEV_2_GT3_HUS_ID  0x00A2A ///< Dev2-HSW ULT GT3 Server
+
+///
+/// For CRW IGD
+///
+#define V_SA_PCI_DEV_2_GT1_HSD_CRW 0x00D12 ///< Dev2-HSW DT-GT1
+#define V_SA_PCI_DEV_2_GT2_HSD_CRW 0x00D22 ///< Dev2-HSW DT-GT2
+#define V_SA_PCI_DEV_2_GT3_HSD_CRW 0x00D32 ///< Dev2-HSW DT-GT3
+#define V_SA_PCI_DEV_2_GT1_HSM_CRW 0x00D16 ///< Dev2-HSW MB-GT1
+#define V_SA_PCI_DEV_2_GT2_HSM_CRW 0x00D26 ///< Dev2-HSW MB-GT2
+#define V_SA_PCI_DEV_2_GT3_HSM_CRW 0x00D36 ///< Dev2-HSW MB-GT3
+
+///
+/// For HSW ULX
+///
+#define V_SA_PCI_DEV_2_GT1_HSW_ULX 0x00A0E ///< Dev2-HSW ULX GT1
+#define V_SA_PCI_DEV_2_GT2_HSW_ULX 0x00A1E ///< Dev2-HSW ULX GT2
+
+#define R_SA_IGD_VID               0x00
+#define R_SA_IGD_CMD               0x04
+#define R_SA_IGD_GTTMMADR          0x10
+#define R_SA_IGD_GMADR             0x18
+#define R_SA_IGD_IOBAR             0x20
+
+#define R_SA_IGD_BSM_OFFSET        0x005C  ///< Base of Stolen Memory
+#define R_SA_IGD_MSAC_OFFSET       0x0062  ///< Multisize Aperture Control
+#define R_SA_IGD_MSICAPID_OFFSET   0x0090  ///< MSI Capabilities ID
+#define R_SA_IGD_MC_OFFSET         0x0092  ///< Message Control
+#define R_SA_IGD_MA_OFFSET         0x0094  ///< Message Address
+#define R_SA_IGD_MD_OFFSET         0x0098  ///< Message Data
+#define R_SA_IGD_SWSCI_OFFSET      0x00E8
+#define R_SA_IGD_ASLS_OFFSET       0x00FC  ///< ASL Storage
+
+//
+// Device 3 Equates
+//
+#define SA_HDA_BUS_NUM    0x00
+#define SA_HDA_DEV_NUM    0x03
+#define SA_HDA_FUN_NUM    0x00
+#define SA_HDA_HDBAR_SIZE (1 << 14)
+#define SA_HDA_HDBARL     0x10
+#define SA_HDA_HDBARU     0x14
+
+///
+/// Maximum number of SDRAM channels supported by the memory controller
+///
+///
+/// Maximum number of SDRAM channels supported by the memory controller
+///
+#define SA_MC_MAX_CHANNELS 2
+///
+/// Maximum number of DIMM sockets supported by each channel
+///
+#define SA_MC_MAX_SLOTS 2
+
+///
+/// Maximum number of sides supported per DIMM
+///
+#define SA_MC_MAX_SIDES 2
+
+///
+/// Maximum number of DIMM sockets supported by the memory controller
+///
+#define SA_MC_MAX_SOCKETS (SA_MC_MAX_CHANNELS * SA_MC_MAX_SLOTS)
+
+///
+/// Maximum number of rows supported by the memory controller
+///
+#define SA_MC_MAX_RANKS (SA_MC_MAX_SOCKETS * SA_MC_MAX_SIDES)
+
+///
+/// Maximum number of rows supported by the memory controller
+///
+#define SA_MC_MAX_ROWS (SA_MC_MAX_SIDES * SA_MC_MAX_SOCKETS)
+
+///
+/// Maximum memory supported by the memory controller
+/// 4 GB in terms of KB
+///
+#define SA_MC_MAX_MEM_CAPACITY (4 * 1024 * 1024)
+
+///
+/// Define the SPD Address for DIMM 0
+///
+#define SA_MC_DIMM0_SPD_ADDRESS 0xA0
+
+///
+/// Internal Graphics Display and Render Clock Freqencies
+///
+#define R_SA_MC_MMIO_GCFGC       0xC8C                           ///< Graphics Clock Frequency and Gating Control
+#define R_SA_IGD_GCFGC_OFFSET    0x00F0                          ///< Graphics Clock Frequency and Gating Control
+#define N_SA_GCFGC_GCRC          BIT9                            ///< Gate Core Display ClockGate Core Display Clock
+#define B_SA_GCFGC_GCSCS_MASK    (BIT19 | BIT18 | BIT17 | BIT16) ///< Graphics Core Sampler Clock Select (GCSCS)
+#define B_SA_GCFGC_GCDCS_MASK    (BIT6 | BIT5 | BIT4)            ///< Graphics Core Display Clock Select (GCDCS)
+#define B_SA_GCFGC_GCRCS_MASK    (BIT3 | BIT2 | BIT1 | BIT0)     ///< Graphics Core Render Clock Select (GCRCS)
+#define R_SA_MC_MMIO_IOCKTRR1    0x0B68                          ///< IO Circuit Reserve Register 1
+#define R_SA_MCHBAR_GFXPLL0      0x2C30                          ///< GFX PLL BIOS
+#define R_SA_MCHBAR_GFXPLL1      0x2C32                          ///< GFX PLL BIOS
+#define R_SA_MCHBAR_GFXPLL9      0x2C44                          ///< GFX PLL Frequency Change Control
+#define R_SA_MCHBAR_RGVSWCTL     0x1170
+#define R_SA_MCHBAR_VIDCTL       0x11C0
+#define R_SA_MCHBAR_PMCFG        0x1210
+
+///
+/// DMIBAR registers
+///
+#define R_SA_DMIBAR_DMIPVCCAP1_OFFSET  0x4       ///< DMI VC Capabilities 1
+#define R_SA_DMIBAR_DMIVC0RCTL_OFFSET  0x14      ///< DMI VC0 Resource Control
+#define R_SA_DMIBAR_DMIVC0RSTS_OFFSET  0x1A      ///< DMI VC0 Status
+#define R_SA_DMIBAR_DMIVC1RCTL_OFFSET  0x20      ///< DMI VC1 Resource Control
+#define R_SA_DMIBAR_DMIVC1RSTS_OFFSET  0x26      ///< DMI VC1 Status
+#define R_SA_DMIBAR_DMIVCPRCTL_OFFSET  0x2C      ///< DMI VCp Resource Control
+#define R_SA_DMIBAR_DMIVCPRSTS_OFFSET  0x32      ///< DMI VCp Status
+#define R_SA_DMIBAR_DMIVCMRCTL_OFFSET  0x38      ///< DMI VCm Resource Control
+#define R_SA_DMIBAR_DMIVCMRSTS_OFFSET  0x3E      ///< DMI VCm Status
+#define R_SA_DMIBAR_LCAP_OFFSET        0x84      ///< DMI Link Capabilities
+#define R_SA_DMIBAR_LCTL_OFFSET        0x88      ///< DMI Link Control
+#define R_SA_DMIBAR_LSTS_OFFSET        0x8A      ///< DMI Link Status
+#define R_SA_DMIBAR_LCTL2_OFFSET       0x98      ///< DMI Link Control 2
+#define R_SA_DMIBAR_DMICC_OFFSET       0x208     ///< DMI Config Control
+#define R_SA_DMIBAR_LTSSMC_OFFSET      0x224     ///< DMI LTSSMC Control
+#define R_SA_DMIBAR_L0SLAT_OFFSET      0x22C     ///< DMI L0s Control
+#define R_SA_DMIBAR_CFG4_OFFSET        0x258     ///< DMI Config 4
+#define R_SA_DMIBAR_CFG6_OFFSET        0x260     ///< DMI Config 6
+#define R_SA_DMIBAR_SCRATCHPAD0_OFFSET 0x71C     ///< DMI Scratchpad 0
+#define R_SA_DMIBAR_SCRATCHPAD1_OFFSET 0x720     ///< DMI Scratchpad 1
+#define R_SA_DMIBAR_AFEBND0CFG1_OFFSET 0x904     ///< DMI AFE Bundle Config 1
+#define R_SA_DMIBAR_AFEBND0CFG2_OFFSET 0x908     ///< DMI AFE Bundle Config 2
+#define R_SA_DMIBAR_AFELN0CFG0_OFFSET  0xA00     ///< DMI AFE Lane Config 0
+#define R_SA_DMIBAR_CMNSPARE_OFFSET    0xC38     ///< DMI Common Spare
+
+#define N_SA_DMIBAR_DMIVCCTL_EN        BIT31
+#define V_SA_DMIBAR_DMIVCCTL_ID        (7 << 24) ///< Bit[26:24]
+#define B_SA_DMIBAR_DMIVCCTL_TVM_MASK  0xFE
+#define N_SA_DMIBAR_DMIVCCTL_ID        24
+#define B_SA_DMIBAR_DMISTS_NP          BIT1
+
+///
+/// Vt-d Engine base address.
+///
+#define R_SA_MCHBAR_VTD1_OFFSET  0x5400  ///< HW UNIT2 for IGD
+#define R_SA_MCHBAR_VTD2_OFFSET  0x5410  ///< HW UNIT3 for all other - PEG, USB, SATA etc
+
+//
+// VCU Mailbox Definitions
+//
+#define R_SA_MCHBAR_VCU_MAILBOX_INTERFACE_OFFSET  0x6C00
+#define R_SA_MCHBAR_VCU_MAILBOX_DATA_OFFSET       0x6C04
+#define B_SA_MCHBAR_VCU_STATUS_RUN_BUSY           BIT31
+#define V_SA_VCU_OPCODE_OPEN_SEQ_REV1             0x1
+#define V_SA_VCU_OPCODE_CLOSE_SEQ_REV1            0x2
+#define V_SA_VCU_OPCODE_READ_VCU_API_VER_ID_REV1  0x5
+#define V_SA_VCU_OPCODE_READ_DATA_REV1            0x6
+#define V_SA_VCU_OPCODE_WRITE_DATA_REV1           0x7
+#define V_SA_VCU_OPCODE_READ_CSR_REV1             0x20
+#define V_SA_VCU_OPCODE_WRITE_CSR_REV1            0x21
+#define V_SA_VCU_OPCODE_READ_MMIO_REV1            0x22
+#define V_SA_VCU_OPCODE_WRITE_MMIO_REV1           0x23
+
+#define V_SA_VCU_OPCODE_OPEN_SEQ_REV2             0x2
+#define V_SA_VCU_OPCODE_CLOSE_SEQ_REV2            0x3
+#define V_SA_VCU_OPCODE_READ_VCU_API_VER_ID_REV2  0x1
+#define V_SA_VCU_OPCODE_READ_DATA_REV2            0x7
+#define V_SA_VCU_OPCODE_WRITE_DATA_REV2           0x8
+#define V_SA_VCU_OPCODE_READ_CSR_REV2             0x13
+#define V_SA_VCU_OPCODE_WRITE_CSR_REV2            0x14
+#define V_SA_VCU_OPCODE_READ_MMIO_REV2            0x15
+#define V_SA_VCU_OPCODE_WRITE_MMIO_REV2           0x16
+
+
+#define V_SA_VCU_SEQID_READ_CSR_REV1    0x6
+#define V_SA_VCU_SEQID_WRITE_CSR_REV1   0x7
+#define V_SA_VCU_SEQID_READ_MMIO_REV1   0x8
+#define V_SA_VCU_SEQID_WRITE_MMIO_REV1  0x9
+
+#define V_SA_VCU_SEQID_READ_CSR_REV2    0x1
+#define V_SA_VCU_SEQID_WRITE_CSR_REV2   0x2
+#define V_SA_VCU_SEQID_READ_MMIO_REV2   0x3
+#define V_SA_VCU_SEQID_WRITE_MMIO_REV2  0x4
+
+#define V_SA_VCU_RESPONSE_SUCCESS            0x40
+#define V_SA_VCU_RESPONSE_BUSY               0x80
+#define V_SA_VCU_RESPONSE_THREADUNAVAILABLE  0x82
+#define V_SA_VCU_RESPONSE_ILLEGAL            0x90
+#define R_SA_VCU_AFECMNCFG0_ADDRESS_REV1  0x0C008018
+#define R_SA_VCU_AFECMNCFG2_ADDRESS_REV1  0x0C088018
+#define R_SA_VCU_AFECMNCFG3_ADDRESS_REV1  0x0C0C8018
+#define R_SA_VCU_AFECMNCFG7_ADDRESS_REV1  0x0C308803
+
+#define R_SA_VCU_AFECMNCFG0_ADDRESS_REV2  0x0C008001
+#define R_SA_VCU_AFECMNCFG2_ADDRESS_REV2  0x0C088001
+#define R_SA_VCU_AFECMNCFG3_ADDRESS_REV2  0x0C0C8001
+#define R_SA_VCU_AFECMNCFG7_ADDRESS_REV2  0x0C308080
+
+///
+/// VCU Miscellaneous Controls
+///
+#define V_SA_VCU_STATUS_BUSY_LIMIT     100
+#define V_SA_VCU_RESPONSE_RETRY_LIMIT  10
+#endif
diff --git a/ReferenceCode/Chipset/SystemAgent/Library/SaPcieLib/Common/SaPcieLib.c b/ReferenceCode/Chipset/SystemAgent/Library/SaPcieLib/Common/SaPcieLib.c
new file mode 100644
index 0000000..0e83b90
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/Library/SaPcieLib/Common/SaPcieLib.c
@@ -0,0 +1,1780 @@
+/** @file
+  SA PCIE Library
+
+@copyright
+  Copyright (c) 2012 - 2013 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement
+
+**/
+
+#if !defined(EDK_RELEASE_VERSION) || (EDK_RELEASE_VERSION < 0x00020000)
+#include "EdkIIGlueBase.h"
+#include "EfiCommon.h"
+#include "SaAccess.h"
+#include "PchAccess.h"
+#include EFI_PROTOCOL_CONSUMER (SaPlatformPolicy)
+#include "SaPcieLib.h"
+#include "CpuRegs.h"
+#include "CpuPlatformLib.h"
+#endif
+
+#define LTR_VALUE_MASK (BIT0 + BIT1 + BIT2 + BIT3 + BIT4 + BIT5 + BIT6 + BIT7 + BIT8 + BIT9)
+#define LTR_SCALE_MASK (BIT10 + BIT11 + BIT12)
+
+///
+/// LTR related macros
+///
+#define LTR_LATENCY_VALUE(x)           (x & LTR_VALUE_MASK)
+#define LTR_MULTIPLIER_INDEX(x)        ((UINT32)(x & LTR_SCALE_MASK) >> 10)
+
+
+typedef struct {
+  UINT64  BaseAddr;
+  UINT32  Offset;
+  UINT32  AndMask;
+  UINT32  OrMask;
+} BOOT_SCRIPT_REGISTER_SETTING;
+
+///
+/// SA PCI Registers to save for S3 resume
+///
+UINTN mSaChipsetPciRegistersTable[] = {
+  R_SA_DEVEN,
+  R_SA_REMAPBASE + 4,
+  R_SA_REMAPBASE,
+  R_SA_REMAPLIMIT + 4,
+  R_SA_REMAPLIMIT
+};
+//
+// Address values for mSaChipsetPciRegistersSaveTable will be initialized at Runtime inside function
+// SaPcieInitPolicy(). The Address uses the Register Offset from table mSaChipsetPciRegistersTable
+//
+BOOT_SCRIPT_PCI_REGISTER_SAVE mSaChipsetPciRegistersSaveTable[] = {
+  0,  EfiBootScriptWidthUint32,  0,  // R_SA_DEVEN
+  0,  EfiBootScriptWidthUint32,  0,  // R_SA_REMAPBASE + 4
+  0,  EfiBootScriptWidthUint32,  0,  // R_SA_REMAPBASE
+  0,  EfiBootScriptWidthUint32,  0,  // R_SA_REMAPLIMIT + 4
+  0,  EfiBootScriptWidthUint32,  0,  // R_SA_REMAPLIMIT
+};
+
+///
+/// SA IGFX PCI Registers to save for S3 resume
+///
+UINTN mSaIgfxPciRegistersTable[] = {
+  R_SA_IGD_SWSCI_OFFSET,
+  R_SA_IGD_ASLS_OFFSET,
+  R_SA_IGD_GTTMMADR + 4,
+  R_SA_IGD_GTTMMADR,
+  R_SA_IGD_GMADR + 4,
+  R_SA_IGD_GMADR,
+  R_SA_IGD_IOBAR,
+  R_SA_IGD_CMD
+};
+//
+// Address values for mSaIgfxPciRegistersSaveTable will be initialized at Runtime inside function
+// SaPcieInitPolicy(). The Address uses the Register Offset from table mSaIgfxPciRegistersTable
+//
+BOOT_SCRIPT_PCI_REGISTER_SAVE mSaIgfxPciRegistersSaveTable[] = {
+  0,  EfiBootScriptWidthUint32,  0,  // R_SA_IGD_SWSCI_OFFSET
+  0,  EfiBootScriptWidthUint32,  0,  // R_SA_IGD_ASLS_OFFSET
+  0,  EfiBootScriptWidthUint32,  0,  // R_SA_IGD_GTTMMADR + 4
+  0,  EfiBootScriptWidthUint32,  0,  // R_SA_IGD_GTTMMADR
+  0,  EfiBootScriptWidthUint32,  0,  // R_SA_IGD_GMADR + 4
+  0,  EfiBootScriptWidthUint32,  0,  // R_SA_IGD_GMADR
+  0,  EfiBootScriptWidthUint32,  0,  // R_SA_IGD_IOBAR
+  0,  EfiBootScriptWidthUint32,  0,  // R_SA_IGD_CMD
+};
+
+/*
+  4th Gen Intel(R) Core Processor (Haswell) System Agent BIOS Spec 0.7.2
+
+  13.1.1 SMRAM Locking
+   Lock down SMRAM Space by setting the B0.D0.F0 register offset 088h[4] = '1b'
+  
+  13.2 System Agent configuration Locking.
+  For reliable operation and security, it is strongly recommended that BIOS should lock critical system agent configuration.
+  When the lock bits are set to 1 then all related registers become read only to the CPU.
+
+    For reliable operation and security, it is strongly recommended that BIOS should set the following bits:
+    .Lock GGC from writes by setting the B0.D0.F0 register offset 050[0] = '1b'. (Duplicate of MRC)
+    .Lock DPR by setting the B0.D0.F0 register offset 05Ch[0] = '1b'.
+    .Lock ME memory range configuration by setting the B0.D0.F0 register offset 078h[10] = '1b'.  (Duplicate of MRC)
+    .Lock remap base and limit by setting the B0.D0.F0 register offset 090h[0] = '1b' and B0.D0.F0 register offset 098h[0] = '1b' (Duplicate of MRC)
+    .Lock TOM by setting the B0.D0.F0 register offset 0A0h[0] = '1b'.  (Duplicate of MRC)
+    .Lock TOUUD by setting the B0.D0.F0 register offset 0A8h[0] = '1b'. (Duplicate of MRC)
+    .Lock BDSM by setting the B0.D0.F0 register offset 0B0h[0] = '1b'. (Duplicate of MRC)
+    .Lock BGSM by setting the B0.D0.F0 register offset 0B4h[0] = '1b'. (Duplicate of MRC)
+    .Lock TSEG Memory Base by setting the B0.D0.F0 register offset 0B8h[0] = '1b'.
+    .Lock TOLUD by setting the B0.D0.F0 register offset 0BCh[0] = '1b'.  (Duplicate of MRC)
+    .Lock Memory controller configuration by setting the MCHBAR Offset 50FCh [7:0] = '8Fh'. (Duplicate of MRC)
+    .Lock DDR power/thermal management settings by setting MCHBAR offset 5880h [5] = '1b'
+    .Lock primary channel arbiter weights by setting the MCHBAR Offset 7000h [31] = '1b',
+       MCHBAR Offset 77FCh [0] = '1b', MCHBAR Offset 7FFCh [0] = '1b' and MCHBAR Offset 6800h [31] = '1b'.
+    .Lock UMA GFX by setting the MCHBAR Offset 6020h [0] = '1b'.
+    .Lock PAVP settings by setting MCHBAR Offset 0x5500h [0] = '1b'.
+    .Lock VTDTRK by setting the MCHBAR Offset 63FCh [0] = '1b'.
+    .Read and write back MCHBAR Offset 6008h [31:0]
+    .Read and write back MCHBAR Offset 6030h [31:0]
+    .Read and write back MCHBAR Offset 6034h [31:0]
+    .Lock processor/chipset BAR registers by setting MSR 0x2E7h [0] = '1b' at the end of POST.
+*/
+//
+// BaseAddr values for mSaSecurityRegisters that uses PciExpressBaseAddress will be initialized at
+// Runtime inside function SaPcieInitPolicy().
+//
+BOOT_SCRIPT_REGISTER_SETTING mSaSecurityRegisters[] = {
+  0,  0x088,  0xFFFFFFFF,  BIT4,
+  0,  0x050,  0xFFFFFFFF,  BIT0,
+  0,  0x05C,  0xFFFFFFFF,  BIT0,
+  0,  0x078,  0xFFFFFFFF,  BIT10,
+  0,  0x090,  0xFFFFFFFF,  BIT0,
+  0,  0x098,  0xFFFFFFFF,  BIT0,
+  0,  0x0A0,  0xFFFFFFFF,  BIT0,
+  0,  0x0A8,  0xFFFFFFFF,  BIT0,
+  0,  0x0B0,  0xFFFFFFFF,  BIT0,
+  0,  0x0B4,  0xFFFFFFFF,  BIT0,
+  0,  0x0B8,  0xFFFFFFFF,  BIT0,
+  0,  0x0BC,  0xFFFFFFFF,  BIT0,
+  MCH_BASE_ADDRESS,  0x50FC,  0xFFFFFFFF,  0x8F,
+  MCH_BASE_ADDRESS,  0x5880,  0xFFFFFFFF,  BIT5,
+  MCH_BASE_ADDRESS,  0x7000,  0xFFFFFFFF,  BIT31,
+  MCH_BASE_ADDRESS,  0x77FC,  0xFFFFFFFF,  BIT0,
+  MCH_BASE_ADDRESS,  0x7FFC,  0xFFFFFFFF,  BIT0,
+  MCH_BASE_ADDRESS,  0x6800,  0xFFFFFFFF,  BIT31,
+  MCH_BASE_ADDRESS,  0x6020,  0xFFFFFFFF,  BIT0,
+  MCH_BASE_ADDRESS,  0x5500,  0xFFFFFFFF,  BIT0,
+  MCH_BASE_ADDRESS,  0x63FC,  0xFFFFFFFF,  BIT0,
+  MCH_BASE_ADDRESS,  0x6008,  0xFFFFFFFF,  0,
+  MCH_BASE_ADDRESS,  0x6030,  0xFFFFFFFF,  0,
+  MCH_BASE_ADDRESS,  0x6034,  0xFFFFFFFF,  0
+};
+
+#ifdef PEG_FLAG
+UINTN                           mDeviceCapMmBaseSave [MAX_SUPPORTED_ROOT_BRIDGE_NUMBER][MAX_SUPPORTED_DEVICE_NUMBER];
+UINT32                          mDeviceExtCapLtrOffsetSave [MAX_SUPPORTED_ROOT_BRIDGE_NUMBER][MAX_SUPPORTED_DEVICE_NUMBER];
+UINT32                          mDeviceExtCapVcOffsetSave [MAX_SUPPORTED_ROOT_BRIDGE_NUMBER][MAX_SUPPORTED_DEVICE_NUMBER];
+UINT32                          mDeviceBusNumberSave [MAX_SUPPORTED_ROOT_BRIDGE_NUMBER][MAX_SUPPORTED_DEVICE_NUMBER];
+UINT8                           mDeviceAspmSave [MAX_SUPPORTED_ROOT_BRIDGE_NUMBER][MAX_SUPPORTED_DEVICE_NUMBER];
+UINT16                          mDeviceLtrObffSave [MAX_SUPPORTED_ROOT_BRIDGE_NUMBER][MAX_SUPPORTED_DEVICE_NUMBER];
+UINT16                          mDeviceMaxSnoopLatencySave [MAX_SUPPORTED_ROOT_BRIDGE_NUMBER][MAX_SUPPORTED_DEVICE_NUMBER];
+UINT16                          mDeviceMaxNoSnoopLatencySave [MAX_SUPPORTED_ROOT_BRIDGE_NUMBER][MAX_SUPPORTED_DEVICE_NUMBER];
+UINT8                           mDeviceTcxVc0MappingSave [MAX_SUPPORTED_ROOT_BRIDGE_NUMBER][MAX_SUPPORTED_DEVICE_NUMBER];
+UINT8                           mCommonClock [MAX_SUPPORTED_ROOT_BRIDGE_NUMBER] = {0, 0, 0};
+UINT16                          mDeviceControlRegisterSave [MAX_SUPPORTED_ROOT_BRIDGE_NUMBER][MAX_SUPPORTED_DEVICE_NUMBER];
+UINT8                           mNumberOfDeviceFound [MAX_SUPPORTED_ROOT_BRIDGE_NUMBER] = {0, 0, 0};
+#endif  // PEG_FLAG
+
+UINT8                           mPAMSave [MAX_PAM_REG_COUNT];
+UINTN                           mSaChipsetPciRegistersSave [sizeof (mSaChipsetPciRegistersSaveTable) / sizeof (BOOT_SCRIPT_PCI_REGISTER_SAVE)];
+UINTN                           mSaIgfxPciRegistersSave [sizeof (mSaIgfxPciRegistersSaveTable) / sizeof (BOOT_SCRIPT_PCI_REGISTER_SAVE)];
+UINT8                           mSteppingId;
+UINT8                           mBridgeId;
+UINT8                           mBridgeSteppingId;
+
+///
+/// Store required policy setting in global variables.
+///
+UINT8                           mDxePlatformSaPolicyRevision;
+SA_PCIE_ASPM_CONFIG             mPegAspmPerPort[MAX_SUPPORTED_ROOT_BRIDGE_NUMBER];
+UINT8                           mPegAspmL0sPerPort[MAX_SUPPORTED_ROOT_BRIDGE_NUMBER];
+BOOLEAN                         mCridEnable;
+BOOLEAN                         mDevice4Enable;
+PCIE_ASPM_DEV_INFO              *mPcieAspmDevsOverride;
+PCIE_LTR_DEV_INFO               *mPcieLtrDevsOverride;
+UINT16                          mSnoopLatencyOvrValue;
+UINT16                          mNonSnoopLatencyOvrValue;
+SA_PCIE_PWR_OPT                 mPegPwrOpt[SA_PEG_MAX_FUN];
+
+#ifdef EFI_DEBUG
+UINT8                           mMaxBusNumberSupported;
+#endif
+EFI_STATUS                      mEnumStatus;
+
+#ifdef PEG_FLAG
+/**
+  Find the Offset to a given Capabilities ID
+  CAPID list:
+    0x01 = PCI Power Management Interface
+    0x04 = Slot Identification
+    0x05 = MSI Capability
+    0x10 = PCI Express Capability
+
+  @param[in] Bus       -   Pci Bus Number
+  @param[in] Device    -   Pci Device Number
+  @param[in] Function  -   Pci Function Number
+  @param[in] CapId     -   CAPID to search for
+
+  @retval 0            - CAPID not found
+  @retval Other        - CAPID found, Offset of desired CAPID
+**/
+UINT32
+LibPcieFindCapId (
+  IN UINT8   Bus,
+  IN UINT8   Device,
+  IN UINT8   Function,
+  IN UINT8   CapId
+  )
+{
+  UINT8 CapHeader;
+
+#ifndef AMI_OVERRIDE_FOR_ULT_FASTBOOT
+  CPU_FAMILY CpuFamilyId;
+  CpuFamilyId = GetCpuFamily();
+  if (CpuFamilyId == EnumCpuHswUlt) return 0;
+#endif // AMI_OVERRIDE_FOR_ULT_FASTBOOT
+  ///
+  /// Always start at Offset 0x34
+  ///
+  CapHeader = MmPci8 (0, Bus, Device, Function, PCI_CAPP);
+  if (CapHeader == 0xFF) {
+    return 0;
+  }
+
+  while (CapHeader != 0) {
+    ///
+    /// Bottom 2 bits of the pointers are reserved per PCI Local Bus Spec 2.2
+    ///
+    CapHeader &= ~(BIT1 + BIT0);
+    ///
+    /// Search for desired CapID
+    ///
+    if (MmPci8 (0, Bus, Device, Function, CapHeader) == CapId) {
+      return CapHeader;
+    }
+
+    CapHeader = MmPci8 (0, Bus, Device, Function, CapHeader + 1);
+  }
+
+  return 0;
+}
+
+/**
+  Search and return the offset of desired Pci Express Capability ID
+  CAPID list:
+    0x0001 = Advanced Error Rreporting Capability
+    0x0002 = Virtual Channel Capability
+    0x0003 = Device Serial Number Capability
+    0x0004 = Power Budgeting Capability
+
+  @param[in] PegBaseAddress - DeviceMmBase which points to PCIe device register space.
+  @param[in] CapId          - Extended CAPID to search for
+
+  @retval 0       - CAPID not found
+  @retval Other   - CAPID found, Offset of desired CAPID
+**/
+UINT32
+LibPcieFindExtendedCapId (
+  IN UINT32  PegBaseAddress,
+  IN UINT16  CapId
+  )
+{
+  UINT16  CapHeaderOffset;
+  UINT16  CapHeaderId;
+#ifndef AMI_OVERRIDE_FOR_ULT_FASTBOOT
+  CPU_FAMILY CpuFamilyId;
+  CpuFamilyId = GetCpuFamily();
+  if (CpuFamilyId == EnumCpuHswUlt) return 0;
+#endif // AMI_OVERRIDE_FOR_ULT_FASTBOOT
+  ///
+  /// Start to search at Offset 0x100
+  /// Get Capability Header
+  ///
+  CapHeaderId     = 0;
+  CapHeaderOffset = 0x100;
+
+  while (CapHeaderOffset != 0 && CapHeaderId != 0xFFFF) {
+    ///
+    /// Search for desired CapID
+    ///
+    CapHeaderId = MmioRead16 (PegBaseAddress + CapHeaderOffset);
+    if (CapHeaderId == CapId) {
+      return CapHeaderOffset;
+    }
+
+    CapHeaderOffset = (MmioRead16 (PegBaseAddress + CapHeaderOffset + 2) >> 4);
+  }
+
+  return 0;
+}
+
+/**
+  Enumerate all end point devices connected to root bridge ports and record their MMIO base address
+
+  @exception EFI_UNSUPPORTED      PCIe capability structure not found
+  @retval    EFI_SUCCESS          All done successfully
+**/
+EFI_STATUS
+EnumerateAllPcieDevices (
+  VOID
+  )
+{
+  UINT32      CapOffset1;
+  UINT32      CapOffset2;
+  UINTN       RootPortMmBase;
+  UINT8       SubBusNum;
+  UINT8       BusNum;
+  UINT8       PegBus;
+  UINT8       PegDev;
+  UINT8       PegFunc;
+  UINT8       Bus;
+  UINT8       Dev;
+  UINT8       Func;
+  UINT8       RootBridgeCompleted;
+  UINT8       RootBridgeDeviceNumber [MAX_SUPPORTED_ROOT_BRIDGE_NUMBER] = {1, 1, 1};
+  UINT8       RootBridgeFunctionNumber [MAX_SUPPORTED_ROOT_BRIDGE_NUMBER] = {0, 1, 2};
+
+#ifdef EFI_DEBUG
+  mMaxBusNumberSupported = 0xFF >> ((MmPci32 (0, SA_MC_BUS, SA_MC_DEV, SA_MC_FUN, R_SA_PCIEXBAR) & B_SA_PCIEXBAR_LENGTH_MASK) >> N_SA_PCIEXBAR_LENGTH_OFFSET);
+#endif
+  PegBus = 0;
+  for (RootBridgeCompleted = 0; RootBridgeCompleted < MAX_SUPPORTED_ROOT_BRIDGE_NUMBER; RootBridgeCompleted++) {
+    PegDev  = RootBridgeDeviceNumber [RootBridgeCompleted];
+    PegFunc = RootBridgeFunctionNumber [RootBridgeCompleted];
+    if (MmPci16 (0, PegBus, PegDev, PegFunc, PCI_VID) == 0xFFFF) {
+      continue;
+    }
+    ///
+    /// Save Bridge Bus number assignment
+    ///
+    mDeviceBusNumberSave [RootBridgeCompleted][0] = MmPci32 (0, PegBus, PegDev, PegFunc, PCI_PBUS);
+    SaScriptMemWrite (
+      EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+      EfiBootScriptWidthUint32,
+      (UINTN) MmPciAddress (0, PegBus, PegDev, PegFunc, PCI_PBUS),
+      1,
+      &mDeviceBusNumberSave [RootBridgeCompleted][0]
+      );
+
+    ///
+    /// Get the pointer to the Port PCI Express Capability Structure.
+    ///
+    CapOffset1  = LibPcieFindCapId (PegBus, PegDev, PegFunc, 0x10);
+    if (CapOffset1 == 0) {
+      DEBUG ((EFI_D_ERROR, "ERROR: Cannot find Root Bridge PCIE capability structure.\n"));
+      return EFI_UNSUPPORTED;
+    }
+
+    ///
+    /// Save root bridge device MM base
+    ///
+    RootPortMmBase = MmPciAddress (0, PegBus, PegDev, PegFunc, 0);
+    mDeviceCapMmBaseSave [RootBridgeCompleted][0] = RootPortMmBase + CapOffset1;
+    DEBUG ((EFI_D_INFO, "Root bridge [B%X|D%X|F%X]:", PegBus, PegDev, PegFunc));
+    DEBUG ((EFI_D_INFO, " mDeviceCapMmBaseSave [%d][0] = 0x%X\n", RootBridgeCompleted, mDeviceCapMmBaseSave [RootBridgeCompleted][0]));
+    mNumberOfDeviceFound [RootBridgeCompleted] ++;
+
+    ///
+    /// Get Secondary bus number and Subordinate bus number for end point device enumeration
+    ///
+    BusNum = MmPci8 (0, PegBus, PegDev, PegFunc, PCI_SBUS);
+    SubBusNum = MmPci8 (0, PegBus, PegDev, PegFunc, PCI_SUBUS);
+    for (Bus = SubBusNum; Bus >= BusNum; Bus--) {
+      for (Dev = 0; Dev < 32; Dev++) {
+        for (Func =0; Func <=7; Func++) {
+          ///
+          /// Read Vendor ID to check if device exists
+          /// if no device exists, then check next device
+          ///
+          if (MmPci16 (0, Bus, Dev, 0, PCI_VID) == 0xFFFF) {
+            ///
+            /// No other functions present if Func0 is not preset
+            ///
+            break;
+          }
+          if (MmPci16 (0, Bus, Dev, Func, PCI_VID) == 0xFFFF) {
+            continue;
+          }
+
+          DEBUG ((EFI_D_INFO, "End point [B%X|D%X|F%X]:", Bus, Dev, Func));
+          CapOffset2 = LibPcieFindCapId (Bus, Dev, Func, 0x10);
+          if (CapOffset2 != 0) {
+            ///
+            /// Save end point device MM base
+            ///
+            if (mNumberOfDeviceFound [RootBridgeCompleted] >= MAX_SUPPORTED_DEVICE_NUMBER) {
+              DEBUG ((EFI_D_ERROR, "ERROR: DeviceMmBaseSave array size not big enough.\n"));
+              return EFI_BUFFER_TOO_SMALL;
+            } else {
+              ///
+              /// Save Downstream Bus number assignment
+              ///
+              mDeviceBusNumberSave [RootBridgeCompleted][mNumberOfDeviceFound [RootBridgeCompleted]] = MmPci32 (0, Bus, Dev, Func, PCI_PBUS);
+              SaScriptMemWrite (
+                EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+                EfiBootScriptWidthUint32,
+                (UINTN) MmPciAddress (0, Bus, Dev, Func, PCI_PBUS),
+                1,
+                &mDeviceBusNumberSave [RootBridgeCompleted][mNumberOfDeviceFound [RootBridgeCompleted]]
+                );
+              mDeviceCapMmBaseSave [RootBridgeCompleted][mNumberOfDeviceFound [RootBridgeCompleted]] = MmPciAddress (0, Bus, Dev, Func, 0) + CapOffset2;
+              DEBUG ((EFI_D_INFO, " mDeviceCapMmBaseSave [%d][%d]", RootBridgeCompleted, mNumberOfDeviceFound [RootBridgeCompleted]));
+              DEBUG ((EFI_D_INFO, " = 0x%X\n", mDeviceCapMmBaseSave [RootBridgeCompleted][mNumberOfDeviceFound [RootBridgeCompleted]]));
+              mNumberOfDeviceFound [RootBridgeCompleted] ++;
+            }
+          }
+        }
+      }
+    }
+    DEBUG ((EFI_D_INFO, "mNumberOfDeviceFound [%d] = %d\n", RootBridgeCompleted, mNumberOfDeviceFound [RootBridgeCompleted]));
+  }
+  return EFI_SUCCESS;
+}
+
+/**
+  Initialize VC0 traffic class
+
+  @param[in] RootBridgeCompleted - The first index (point to root bridge) of the device MMIO Base array to select bridge which currently under working or completed.
+  @param[in] EndpointCompleted   - The second index (point to end point devices) of the device MMIO Base array to select device which currently under working or completed.
+
+  @exception EFI_UNSUPPORTED - VC capability ID not found
+  @retval EFI_SUCCESS     - VC mapping correctly initialized
+**/
+EFI_STATUS
+PcieInitTcxVc0 (
+  IN UINT8   RootBridgeCompleted,
+  IN UINT8   EndpointCompleted
+  )
+{
+  UINT32  Offset;
+  UINT8   Data8And;
+  UINT8   Data8Or;
+  UINT32  PegBaseAddress;
+  UINT8   i;
+  UINT8   CapId[] = {'2','8'};
+
+  Offset         = 0;
+  i              = 0;
+  PegBaseAddress = (UINT32) (mDeviceCapMmBaseSave [RootBridgeCompleted][EndpointCompleted] & (UINTN) ~0xFF);
+  ///
+  /// Set TCx-VC0 value - map all TCs to VC0
+  ///
+  ///
+  /// Fix for ClientSW s5039821: PTC Gen3 BIOS Test : MFVC Capability test failure
+  ///
+  while ((Offset == 0x0) && (i < sizeof(CapId))) {
+    mDeviceExtCapVcOffsetSave [RootBridgeCompleted][EndpointCompleted] |= LibPcieFindExtendedCapId (PegBaseAddress, CapId[i]);
+    Offset = mDeviceExtCapVcOffsetSave [RootBridgeCompleted][EndpointCompleted];
+    i++;
+  }
+
+  DEBUG ((EFI_D_INFO, "PTC SaPcieLib.c - Offset: 0x%x\n", Offset));
+  if (Offset == 0) {
+    DEBUG ((EFI_D_INFO, "VC ExtCap structure not found on device [0x%08X]\n", PegBaseAddress));
+    return EFI_UNSUPPORTED;
+  }
+
+  Data8And        = 0;
+  Data8Or         = BIT0 + BIT1 + BIT2 + BIT3 + BIT4 + BIT5 + BIT6 + BIT7;
+  MmioAndThenOr8 (PegBaseAddress + Offset + 0x014, Data8And, Data8Or);
+  SaScriptMemReadWrite (
+    EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+    EfiBootScriptWidthUint8,
+    (UINTN) (PegBaseAddress + Offset + 0x014),
+    &Data8Or,
+    &Data8And
+    );
+  mDeviceTcxVc0MappingSave [RootBridgeCompleted][EndpointCompleted] = MmioRead8 (PegBaseAddress + Offset + 0x014);
+  return EFI_SUCCESS;
+}
+
+/**
+  Sets Common Clock, TCx-VC0 mapping, and Max Payload for PCIe
+**/
+VOID
+SaPcieConfigBeforeOpRom (
+  VOID
+  )
+{
+  UINT8       RootBridgeCompleted;
+  UINT8       EndpointCompleted;
+  UINT16      EndpointMaxPayload;
+  UINTN       RootPortPcieCapMmBase;
+  UINTN       EndPointPcieCapMmBase;
+  UINT16      Data16And;
+  UINT16      Data16Or;
+  UINT16      MaxPayload [MAX_SUPPORTED_ROOT_BRIDGE_NUMBER];
+
+  for (RootBridgeCompleted = 0; RootBridgeCompleted < MAX_SUPPORTED_ROOT_BRIDGE_NUMBER; RootBridgeCompleted++) {
+    RootPortPcieCapMmBase = mDeviceCapMmBaseSave [RootBridgeCompleted][0];
+    EndPointPcieCapMmBase = mDeviceCapMmBaseSave [RootBridgeCompleted][1];
+
+    if (RootPortPcieCapMmBase == 0) {
+      continue;
+    }
+    ///
+    /// Get the PCIE root Port Max Payload Size support.
+    ///
+    MaxPayload [RootBridgeCompleted] = MmioRead16 (RootPortPcieCapMmBase + 4) & (BIT2 | BIT1 | BIT0);
+    ///
+    /// Check the Port Slot Clock Configuration Bit.
+    ///
+    if ((MmioRead16 (RootPortPcieCapMmBase + 0x012) & BIT12) == 0) {
+      ///
+      /// Indicate CommonClock is not supported on this port
+      ///
+      mCommonClock [RootBridgeCompleted] = 0xFF;
+      DEBUG ((EFI_D_INFO, "CommonClock not supported by root bridge [B%X|D%X|F%X|R%X]\n",
+                             (RootPortPcieCapMmBase >> 20)   & mMaxBusNumberSupported,
+                             (RootPortPcieCapMmBase >> 15)   & 0x1F,
+                             (RootPortPcieCapMmBase >> 12)   & 0x07,
+                             (RootPortPcieCapMmBase + 0x012) & 0xFFF));
+    }
+    for (EndpointCompleted = 1; EndpointCompleted < mNumberOfDeviceFound [RootBridgeCompleted]; EndpointCompleted++) {
+      ///
+      /// Set TCx-VC0 mapping on Endpoint
+      ///
+      PcieInitTcxVc0 (RootBridgeCompleted, EndpointCompleted);
+
+      EndPointPcieCapMmBase = mDeviceCapMmBaseSave [RootBridgeCompleted][EndpointCompleted];
+      ///
+      /// Get the end point function Max Payload Size support
+      ///
+      EndpointMaxPayload = MmioRead16 (EndPointPcieCapMmBase + 4) & (BIT2 | BIT1 | BIT0);
+      DEBUG ((EFI_D_INFO, "CAP_MPS of [%X] = %X\n", EndPointPcieCapMmBase + 4, EndpointMaxPayload));
+      ///
+      /// Obtain the minimum Max Payload Size between the PCIE root Port and the end point functions
+      ///
+      if (MaxPayload [RootBridgeCompleted] > EndpointMaxPayload) {
+        MaxPayload [RootBridgeCompleted] = EndpointMaxPayload;
+      }
+      ///
+      /// Check the Endpoint Slot Clock Configuration Bit.
+      ///
+      if ((MmioRead16 (EndPointPcieCapMmBase + 0x012) & BIT12) != 0) {
+        ///
+        /// Common clock is supported, set common clock bit on root port
+        /// and the endpoint
+        ///
+        if (mCommonClock [RootBridgeCompleted] == 0) {
+          MmioOr8 (RootPortPcieCapMmBase + 0x010, BIT6);
+          Data16Or  = BIT6;
+          Data16And = (UINT16)~BIT6;
+          SaScriptMemReadWrite (
+            EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+            EfiBootScriptWidthUint8,
+            (UINTN) (RootPortPcieCapMmBase + 0x010),
+            &Data16Or,  ///< Data to be ORed
+            &Data16And  ///< Data to be ANDed
+            );
+          mCommonClock [RootBridgeCompleted] = 1;
+          DEBUG ((EFI_D_INFO, "Set CommonClock on Root [B%X|D%X|F%X|R%X]\n",
+                                 (RootPortPcieCapMmBase >> 20)   & mMaxBusNumberSupported,
+                                 (RootPortPcieCapMmBase >> 15)   & 0x1F,
+                                 (RootPortPcieCapMmBase >> 12)   & 0x07,
+                                 (RootPortPcieCapMmBase + 0x010) & 0xFFF));
+        }
+        MmioOr8 (EndPointPcieCapMmBase + 0x010, BIT6);
+        Data16Or  = BIT6;
+        Data16And = (UINT16)~BIT6;
+        SaScriptMemReadWrite (
+          EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+          EfiBootScriptWidthUint8,
+          (UINTN) (EndPointPcieCapMmBase + 0x010),
+          &Data16Or,  ///< Data to be ORed
+          &Data16And  ///< Data to be ANDed
+          );
+        DEBUG ((EFI_D_INFO, "Set CommonClock on Device [B%X|D%X|F%X|R%X]\n",
+                               (EndPointPcieCapMmBase >> 20)   & mMaxBusNumberSupported,
+                               (EndPointPcieCapMmBase >> 15)   & 0x1F,
+                               (EndPointPcieCapMmBase >> 12)   & 0x07,
+                               (EndPointPcieCapMmBase + 0x010) & 0xFFF));
+      }
+    }
+    ///
+    /// If common clock supported on root port and endpoint, retrain link
+    ///
+    if (mCommonClock [RootBridgeCompleted] == 1) {
+      DEBUG ((EFI_D_INFO, "CommonClock supported. Retrain link\n"));
+      ///
+      /// Retrain the Link per PCI Express Specification.
+      ///
+      MmioOr8 (RootPortPcieCapMmBase + 0x010, BIT5);
+      Data16Or = BIT5;
+      Data16And = (UINT8) ~BIT5;
+      SaScriptMemReadWrite (
+        EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+        EfiBootScriptWidthUint8,
+        (UINTN) (RootPortPcieCapMmBase + 0x010),
+        &Data16Or,
+        &Data16And
+        );
+      ///
+      /// Wait until Re-Training has completed.
+      ///
+      while ((MmioRead16 (RootPortPcieCapMmBase + 0x012) & BIT11) != 0) {}
+      ///
+      /// Poll until BIT11 clear. 200 ms as polling timeout
+      ///
+      Data16Or  = BIT11;
+      Data16And = 0;
+      SaScriptMemPoll (
+        EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+        EfiBootScriptWidthUint16,
+        (UINTN) (RootPortPcieCapMmBase + 0x012),
+        &Data16Or,
+        &Data16And,
+        1,
+        200000
+        );
+    }
+
+    ///
+    /// Set Max Payload to all root and end point devices
+    ///
+    MaxPayload [RootBridgeCompleted] <<= 5;
+    EndpointCompleted = 0;
+    while (EndpointCompleted < mNumberOfDeviceFound [RootBridgeCompleted]) {
+      EndPointPcieCapMmBase = mDeviceCapMmBaseSave [RootBridgeCompleted][EndpointCompleted];
+      DEBUG ((EFI_D_INFO, "Set MPS of [%X] to %X\n", EndPointPcieCapMmBase + 0x8, MaxPayload [RootBridgeCompleted]));
+      MmioAndThenOr16 (EndPointPcieCapMmBase + 0x8, (UINT16)~(BIT7 | BIT6 | BIT5), MaxPayload [RootBridgeCompleted]);
+      ///
+      /// S3 Save for Device Control Register on all bridges and devices is done after the OpRom has run in EnableExtendedTag.
+      ///
+      EndpointCompleted ++;
+    }
+  }
+}
+
+/**
+  Calculate ASPM Auto setting value
+
+  @param[in] RootBridgeIndex   - Root Bridge Index to select mDeviceCapMmBaseSave array elements for ASPM capability calculation.
+
+  @retval AspmVal - ASPM settings for RP and all EP
+**/
+UINT16
+PcieCalcAspmSettings (
+  IN  UINT8   RootBridgeIndex
+  )
+{
+  UINT16              RootPortAspm;
+  UINT16              EndPointAspm;
+  UINT32              PcieAspmDev;
+  UINT16              EndPointVendorId;
+  UINT16              EndPointDeviceId;
+  UINT8               EndPointRevId;
+  UINT16              AspmVal;
+  UINT32              PortLxLat;
+  UINT32              EndPointLxLat;
+  UINT32              LxLat;
+  UINT8               EndpointCompleted;
+  UINTN               RootPortPcieCapMmBase;
+  UINT32              RootPortLinkCap;
+  UINTN               EndPointPcieCapMmBase;
+  UINT32              EndPointLinkCap;
+  UINT32              EndPointDevCap;
+
+  RootPortPcieCapMmBase = mDeviceCapMmBaseSave [RootBridgeIndex][0];
+  RootPortLinkCap       = MmioRead32 (RootPortPcieCapMmBase + 0x0C);
+
+  ///
+  /// Obtain initial ASPM settings from respective port capability registers.
+  ///
+  RootPortAspm = (RootPortLinkCap >> 10) & 3;
+  DEBUG ((EFI_D_INFO, "Root [%X] Aspm capability = %X\n", RootPortPcieCapMmBase + 0xC, RootPortAspm));
+  AspmVal = RootPortAspm;
+  EndpointCompleted = 1;
+
+  while (EndpointCompleted < mNumberOfDeviceFound [RootBridgeIndex]) {
+    EndPointPcieCapMmBase = mDeviceCapMmBaseSave [RootBridgeIndex][EndpointCompleted];
+    EndPointDevCap        = MmioRead32 (EndPointPcieCapMmBase + 0x04);
+    EndPointLinkCap       = MmioRead32 (EndPointPcieCapMmBase + 0x0C);
+
+    EndPointAspm = (EndPointLinkCap >> 10) & 3;
+    DEBUG ((EFI_D_INFO, "End point [%X] Aspm capability = %X\n", EndPointPcieCapMmBase + 0xC, EndPointAspm));
+    if (mPcieAspmDevsOverride != NULL) {
+      ///
+      /// Mask APMC with values from lookup table.
+      /// RevID of 0xFF applies to all steppings.
+      ///
+      EndPointVendorId  = MmioRead16 ((EndPointPcieCapMmBase & (UINTN) ~0xFF) + 0x000);
+      EndPointDeviceId  = MmioRead16 ((EndPointPcieCapMmBase & (UINTN) ~0xFF) + 0x002);
+      EndPointRevId     = MmioRead8  ((EndPointPcieCapMmBase & (UINTN) ~0xFF) + 0x008);
+      DEBUG ((EFI_D_INFO, "End point [%X] VendorID:DeviceID = %04X:%04X RevID=%02X\n",
+                EndPointPcieCapMmBase, EndPointVendorId, EndPointDeviceId, EndPointRevId));
+      PcieAspmDev       = 0;
+      while ((mPcieAspmDevsOverride[PcieAspmDev].VendorId != SA_PCIE_DEV_END_OF_TABLE)
+          && (PcieAspmDev < MAX_PCIE_ASPM_OVERRIDE)) {
+        if ((mPcieAspmDevsOverride[PcieAspmDev].VendorId == EndPointVendorId) &&
+           (mPcieAspmDevsOverride[PcieAspmDev].DeviceId == EndPointDeviceId) &&
+           ((mPcieAspmDevsOverride[PcieAspmDev].RevId == 0xFF) ||
+            (mPcieAspmDevsOverride[PcieAspmDev].RevId == EndPointRevId))) {
+          RootPortAspm &= mPcieAspmDevsOverride[PcieAspmDev].RootApmcMask;
+          EndPointAspm &= mPcieAspmDevsOverride[PcieAspmDev].EndpointApmcMask;
+          break;
+        }
+        PcieAspmDev++;
+      }
+    }
+
+    if (AspmVal > EndPointAspm) {
+      AspmVal = EndPointAspm;
+      ///
+      /// In case L0s and L1 both can't be enabled, return the result now.
+      ///
+      if((AspmVal & 0x03) == 0) {
+        return AspmVal;
+      }
+    }
+    ///
+    /// Check if L1 should be enabled based on port and endpoint L1 exit latency.
+    ///
+    if (AspmVal & BIT1) {
+      if (!(EndPointLinkCap & BIT22) && !(AspmVal & BIT0)) {
+        DEBUG ((EFI_D_INFO, "\nDevice [%X] ASPM Optionality Compliance bit not set!", EndPointPcieCapMmBase));
+        DEBUG ((EFI_D_INFO, "ASPM L1-Only setting is not supported!\n"));
+        AspmVal = 0;
+        return AspmVal;
+      }
+      PortLxLat = RootPortLinkCap & (BIT17 + BIT16 + BIT15);
+      EndPointLxLat = EndPointLinkCap & (BIT17 + BIT16 + BIT15);
+      DEBUG ((EFI_D_INFO, "Root [%X] L1 Exit Latency = %X\n", RootPortPcieCapMmBase + 0xC, PortLxLat >> 15));
+      DEBUG ((EFI_D_INFO, "End  [%X] L1 Exit Latency = %X\n", EndPointPcieCapMmBase + 0xC, EndPointLxLat >> 15));
+      LxLat = PortLxLat;
+      if (PortLxLat < EndPointLxLat) {
+        LxLat = EndPointLxLat;
+      }
+      ///
+      /// check if the value is bigger than endpoint L1 acceptable exit latency, if it is
+      /// larger than accepted value, then we should disable L1
+      ///
+      LxLat >>= 6;
+      DEBUG ((EFI_D_INFO, "End [%X] L1 Acceptable Latency = %X\n", EndPointPcieCapMmBase + 0x4,
+        (EndPointDevCap & (BIT11 + BIT10 + BIT9)) >> 9));
+      if (LxLat > (EndPointDevCap & (BIT11 + BIT10 + BIT9))) {
+        AspmVal &= ~BIT1;
+        if((AspmVal & 0x03) == 0) {
+          return AspmVal;
+        }
+      }
+    }
+    ///
+    /// Check if L0s should be enabled based on port and endpoint L0s exit latency.
+    ///
+    if (AspmVal & BIT0) {
+      PortLxLat     = RootPortLinkCap & (BIT14 + BIT13 + BIT12);
+      EndPointLxLat = EndPointLinkCap & (BIT14 + BIT13 + BIT12);
+      DEBUG ((EFI_D_INFO, "Root [%X] L0s Exit Latency = %X\n", RootPortPcieCapMmBase + 0xC, PortLxLat >> 12));
+      DEBUG ((EFI_D_INFO, "End  [%X] L0s Exit Latency = %X\n", EndPointPcieCapMmBase + 0xC, EndPointLxLat >> 12));
+      LxLat = PortLxLat;
+      if (PortLxLat < EndPointLxLat) {
+        LxLat = EndPointLxLat;
+      }
+      ///
+      /// check if the value is bigger than endpoint L0s acceptable exit latency, if it is
+      /// larger than accepted value, then we should disable L0s
+      ///
+      LxLat >>= 6;
+      DEBUG ((EFI_D_INFO, "End [%X] L0s Acceptable Latency = %X\n", EndPointPcieCapMmBase + 0x4,
+                                                            (EndPointDevCap & (BIT8 + BIT7 + BIT6)) >> 6));
+      if (LxLat > (EndPointDevCap & (BIT8 + BIT7 + BIT6))) {
+        AspmVal &= ~BIT0;
+        if((AspmVal & 0x03) ==0) {
+          return AspmVal;
+        }
+      }
+    }
+    EndpointCompleted ++;
+  }
+  return AspmVal;
+}
+
+/**
+  This function compares the actual latency in LatencyValue1
+  with actual latency in LatencyValue2 programs the minimum
+  back to LatencyValue1, in the required format.
+
+  @param[in] LatencyValue1  - Current latency value
+  @param[in] LatencyValue2  - Latency value from the Table
+**/
+VOID
+DetermineLatencyValue (
+  IN UINT16   *LatencyValue1,
+  IN UINT16   *LatencyValue2
+  )
+{
+  UINT8      Scale1;
+  UINT8      Scale2;
+  UINT64     ActualLatency1 = 0;
+  UINT64     ActualLatency2 = 0;
+  UINT32     Multiplier[6] = {
+    1,
+    32,
+    1024,
+    32768,
+    1048576,
+    33554432
+  };
+
+  Scale1 = LTR_MULTIPLIER_INDEX(*LatencyValue1);
+  Scale2 = LTR_MULTIPLIER_INDEX(*LatencyValue2);
+  if ((Scale1 <= 5) && (Scale2 <= 5)) {
+    ActualLatency1 = LTR_LATENCY_VALUE(*LatencyValue1) * Multiplier[Scale1];
+    ActualLatency2 = LTR_LATENCY_VALUE(*LatencyValue2) * Multiplier[Scale2];
+  }
+
+  ///
+  /// Store the lower latency value and corresponding scale bits back to LatencyValue1
+  /// and set the Force bit
+  ///
+  if ((ActualLatency1 == 0) || ActualLatency1 > ActualLatency2) {
+    *LatencyValue1 = *LatencyValue2;
+  }
+}
+
+/**
+  This function will scan the LTR override table and update the default values for snoop and non-snoop latencies.
+
+  @param[in] PegBaseAddress   - DeviceMmBase which points to PCIe device register space.
+**/
+VOID
+ScanLtrOverrideTable (
+  IN  UINT32  PegBaseAddress
+  )
+{
+  UINT8               EndPointRevId;
+  UINT16              EndPointVendorId;
+  UINT16              EndPointDeviceId;
+  UINT32              PcieLtrDev;
+
+  EndPointVendorId  = MmioRead16 (PegBaseAddress + 0x000);
+  EndPointDeviceId  = MmioRead16 (PegBaseAddress + 0x002);
+  EndPointRevId     = MmioRead8  (PegBaseAddress + 0x008);
+  if (mPcieLtrDevsOverride != NULL) {
+    PcieLtrDev = 0;
+    while ((mPcieLtrDevsOverride[PcieLtrDev].VendorId != SA_PCIE_DEV_END_OF_TABLE)
+        && (PcieLtrDev < MAX_PCIE_LTR_OVERRIDE)) {
+      if ((mPcieLtrDevsOverride[PcieLtrDev].VendorId == EndPointVendorId) &&
+         (mPcieLtrDevsOverride[PcieLtrDev].DeviceId == EndPointDeviceId) &&
+         ((mPcieLtrDevsOverride[PcieLtrDev].RevId == 0xFF) ||
+         (mPcieLtrDevsOverride[PcieLtrDev].RevId == EndPointRevId))
+          ) {
+        if (mPcieLtrDevsOverride[PcieLtrDev].SnoopLatency & BIT15) {
+          DetermineLatencyValue(&mSnoopLatencyOvrValue, &mPcieLtrDevsOverride[PcieLtrDev].SnoopLatency);
+        }
+        if (mPcieLtrDevsOverride[PcieLtrDev].NonSnoopLatency & BIT15) {
+          DetermineLatencyValue(&mNonSnoopLatencyOvrValue, &mPcieLtrDevsOverride[PcieLtrDev].NonSnoopLatency);
+        }
+        break;
+      }
+      PcieLtrDev++;
+    }
+  }
+}
+
+/**
+  Configure LTR/OBFF on end point device
+
+  @param[in] RootBridgeIndex   - Root Bridge index number to select mDeviceCapMmBaseSave array element for end point device MmBase.
+  @param[in] EndpointCompleted - End point device index number to select mDeviceCapMmBaseSave array element for end point device MmBase.
+**/
+VOID
+PcieSetEndpointLtrObff (
+  IN UINT8      RootBridgeIndex,
+  IN UINT8      EndpointCompleted
+  )
+{
+
+  UINT16  Data16Or;
+  UINT16  Data16And;
+  UINT32  DeviceCapabilities2;
+  UINT32  PegBaseAddress;
+  UINTN   EndpointCapMmBase;
+  UINT32  ExtendedCapOffset;
+  UINT16  DefaultMaxLatency;
+  UINT8   PegFunc;
+
+  PegFunc = (UINT8) ((mDeviceCapMmBaseSave [RootBridgeIndex][0] >> 12) & 0x07);
+  if (PegFunc >= SA_PEG_MAX_FUN) {
+    DEBUG ((EFI_D_ERROR, "PegFunc out of bound! Exit from PcieSetEndpointLtrObff()!\n"));
+    ASSERT (PegFunc < SA_PEG_MAX_FUN);
+    return;
+  }
+
+  EndpointCapMmBase = mDeviceCapMmBaseSave [RootBridgeIndex][EndpointCompleted];
+  ///
+  /// Scan the LTR override table
+  ///
+  PegBaseAddress = (UINT32) (EndpointCapMmBase & (UINTN) ~0xFF);
+  ScanLtrOverrideTable (PegBaseAddress);
+  DeviceCapabilities2 = MmioRead32 (EndpointCapMmBase + 0x24);
+  Data16And           = (UINT16)~(BIT10 + BIT13 + BIT14);
+  Data16Or            = 0;
+  ///
+  /// If mSnoopLatencyOvrValue and mNonSnoopLatencyOvrValue has a value of 0, then this endpoint is not
+  /// part of the override table If it supports LTR messaging then enable the capability
+  ///
+  if ((mSnoopLatencyOvrValue == 0) &&
+      (mNonSnoopLatencyOvrValue == 0)) {
+    if (DeviceCapabilities2 & BIT11) {
+      // If PegPortLtrEnable set to true
+      //
+      if (mPegPwrOpt[PegFunc].LtrEnable == 1) {
+        Data16Or |= BIT10;
+      }
+    }
+  }
+  ///
+  /// Check if endpoint device is capable of OBFF using WAKE# signaling
+  ///
+  if ((DeviceCapabilities2 & BIT19) != 0) {
+    if (mPegPwrOpt[PegFunc].ObffEnable == 1) {
+      Data16Or |= BIT14 | BIT13; ///< 11b - Enable OBFF using WAKE# signaling
+    }
+  }
+  DEBUG ((EFI_D_INFO, "Configure LTR/OBFF setting to EndPoint: [0x%x] to value 0x%x\n",
+          EndpointCapMmBase + 0x28, Data16Or));
+  MmioAndThenOr16 (EndpointCapMmBase + 0x28, Data16And, Data16Or);
+  SaScriptMemReadWrite (
+    EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+    EfiBootScriptWidthUint16,
+    (UINTN) (EndpointCapMmBase + 0x28),
+    &Data16Or,
+    &Data16And
+    );
+  mDeviceLtrObffSave [RootBridgeIndex][EndpointCompleted] = MmioRead16 (EndpointCapMmBase + 0x28);
+  ///
+  ///
+  /// Program LTR Max Latencies
+  ///
+  if (DeviceCapabilities2 & BIT11) {
+    if (mPegPwrOpt[PegFunc].LtrEnable == 1) {
+      ///
+      /// Get the pointer to the Endpoint PCI Express Extended Capability Structure.
+      ///
+      mDeviceExtCapLtrOffsetSave [RootBridgeIndex][EndpointCompleted] = LibPcieFindExtendedCapId (PegBaseAddress, 0x18);
+      ExtendedCapOffset = mDeviceExtCapLtrOffsetSave [RootBridgeIndex][EndpointCompleted];
+      Data16And         = (UINT16) (~0x1FFF);
+      Data16Or          = mSnoopLatencyOvrValue;
+      DefaultMaxLatency = mPegPwrOpt[PegFunc].LtrMaxSnoopLatency;
+      if (ExtendedCapOffset != 0) {
+        DetermineLatencyValue(&Data16Or, &DefaultMaxLatency);
+        MmioAndThenOr16 (PegBaseAddress + ExtendedCapOffset + 4, Data16And, Data16Or);
+        SaScriptMemReadWrite (
+          EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+          EfiBootScriptWidthUint16,
+          (UINTN) (PegBaseAddress + ExtendedCapOffset + 4),
+          &Data16Or,  ///< Data to be ORed
+          &Data16And  ///< Data to be ANDed
+          );
+        mDeviceMaxSnoopLatencySave [RootBridgeIndex][EndpointCompleted] = MmioRead16 (PegBaseAddress + ExtendedCapOffset + 0x4);
+        Data16Or           = mNonSnoopLatencyOvrValue;
+        DefaultMaxLatency  = mPegPwrOpt[PegFunc].LtrMaxNoSnoopLatency;
+        DetermineLatencyValue(&Data16Or, &DefaultMaxLatency);
+        MmioAndThenOr16 (PegBaseAddress + ExtendedCapOffset + 6, Data16And, Data16Or);
+        SaScriptMemReadWrite (
+          EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+          EfiBootScriptWidthUint16,
+          (UINTN) (PegBaseAddress + ExtendedCapOffset + 6),
+          &Data16Or,  ///< Data to be ORed
+          &Data16And  ///< Data to be ANDed
+          );
+        mDeviceMaxNoSnoopLatencySave [RootBridgeIndex][EndpointCompleted] = MmioRead16 (PegBaseAddress + ExtendedCapOffset + 0x6);
+      } else {
+        DEBUG ((EFI_D_INFO, "LTR ExtCap structure not found on device [0x%08X]\n", PegBaseAddress));
+      }
+    }
+  }
+}
+
+/**
+  This function programs the LTR Override values
+**/
+VOID
+PcieILtrOverride (
+  VOID
+  )
+{
+  UINT64  MchBar;
+  UINT32  Data32And;
+  UINT32  Data32Or;
+
+  MchBar    = McD0PciCfg64 (R_SA_MCHBAR) &~BIT0;
+  Data32And = 0x0;
+
+  ///
+  /// Configure Snoop Latency value
+  ///
+  if (mSnoopLatencyOvrValue != 0) {
+    mSnoopLatencyOvrValue |= BIT14;
+  }
+  Data32Or = ((UINT32) (mSnoopLatencyOvrValue << 16));
+
+
+  ///
+  /// Configure Non-Snoop Latency value
+  ///
+  if (mNonSnoopLatencyOvrValue != 0) {
+    mNonSnoopLatencyOvrValue |= BIT14;
+  }
+  Data32Or |= mNonSnoopLatencyOvrValue;
+
+  ///
+  /// Program ILTR_OVRD with latency values
+  ///
+  Mmio32AndThenOr (MchBar, R_SA_MCHBAR_ILTR_OVRD_OFFSET, Data32And, Data32Or);
+  SaScriptMemReadWrite (
+    EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+    EfiBootScriptWidthUint32,
+    (UINTN) (MchBar + R_SA_MCHBAR_ILTR_OVRD_OFFSET),
+    &Data32Or,  /// Data to be ORed
+    &Data32And  /// Data to be ANDed
+    );
+}
+
+/**
+  This function enumerate devices to apply Peg Aspm settings.
+
+  @param[in] RootBridgeIndex   - Root Bridge Index to select mDeviceCapMmBaseSave array elements for ASPM capability calculation.
+  @param[in] AutoFlag          - ASPM AUTO calculation mode
+  @param[in] RootPortAspm      - ASPM setting for Root port
+  @param[in] EndPointAspm      - ASPM setting for End point
+**/
+VOID
+PcieEnumerateDeviceToApplyASPM (
+  IN UINT8      RootBridgeIndex,
+  IN BOOLEAN    AutoFlag,
+  IN UINT16     RootPortAspm,
+  IN UINT16     EndPointAspm
+  )
+{
+  UINT16  LinkAspmCap;
+  UINT16  LinkAspmVal;
+  UINT8   EndpointCompleted;
+  UINT32  PegBaseAddress;
+  UINT16  Data16Or;
+  UINT16  Data16And;
+  UINT32  DeviceCapabilities2;
+  UINT8   PegFunc;
+
+  PegFunc = (UINT8) ((mDeviceCapMmBaseSave [RootBridgeIndex][0] >> 12) & 0x07);
+  if (PegFunc >= SA_PEG_MAX_FUN) {
+    DEBUG ((EFI_D_ERROR, "PegFunc out of bound! Exit from PcieEnumerateDeviceToApplyASPM()!\n"));
+    ASSERT (PegFunc < SA_PEG_MAX_FUN);
+    return;
+  }
+
+  if(AutoFlag) {
+    LinkAspmVal = PcieCalcAspmSettings(RootBridgeIndex);
+    RootPortAspm = LinkAspmVal & 0xFF;
+    EndPointAspm = LinkAspmVal & 0xFF;
+    DEBUG ((EFI_D_INFO, "PcieCalcAspmSettings return ASPM value as: %x, apply on both RP and EP\n", RootPortAspm));
+  }
+
+  ///
+  /// Apply to root port first
+  ///
+  MmioAndThenOr16 (mDeviceCapMmBaseSave [RootBridgeIndex][0] + 0x010, (UINT16)~3, RootPortAspm);
+  DEBUG ((EFI_D_INFO, "Apply Aspm settings to Root [%X] to Aspm value: 0x%x\n", mDeviceCapMmBaseSave [RootBridgeIndex][0] + 0x010, RootPortAspm));
+  ///
+  /// Save register setting for S3 resume.
+  ///
+  mDeviceAspmSave [RootBridgeIndex][0] = MmioRead8 (mDeviceCapMmBaseSave [RootBridgeIndex][0] + 0x010);
+  SaScriptMemWrite (
+    EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+    EfiBootScriptWidthUint8,
+    (UINTN) (mDeviceCapMmBaseSave [RootBridgeIndex][0] + 0x010),
+    1,
+    &mDeviceAspmSave [RootBridgeIndex][0]
+    );
+  ///
+  /// Apply Power Optimizer settings to PEG RootPoints.
+  /// Read DCAP2 to see if LTR/OBFF is supported, program DCTL2 according to policies.
+  ///
+  PegBaseAddress = (UINT32) (mDeviceCapMmBaseSave [RootBridgeIndex][0] & (UINTN) ~0xFF);
+  DeviceCapabilities2 = MmioRead32 (PegBaseAddress + R_SA_PEG_DCAP2_OFFSET);
+  Data16And           = (UINT16)~(BIT10 + BIT13 + BIT14);
+  Data16Or            = 0;
+
+  if (DeviceCapabilities2 & BIT11) {
+    if (mPegPwrOpt[PegFunc].LtrEnable == 1) {
+    Data16Or |= BIT10;
+    }
+  }
+  ///
+  /// Check if root port support WAKE# signaling
+  ///
+  if ((DeviceCapabilities2 & BIT19) != 0) {
+    if (mPegPwrOpt[PegFunc].ObffEnable == 1) {
+    Data16Or |= BIT14 | BIT13; ///< 11b - Enable OBFF using WAKE#
+    }
+  }
+
+  DEBUG ((EFI_D_INFO, "Configure LTR/OBFF setting to PEG root [0x%x] to value 0x%x\n",
+          PegBaseAddress + R_SA_PEG_DCTL2_OFFSET, Data16Or));
+  MmioAndThenOr16 (PegBaseAddress + R_SA_PEG_DCTL2_OFFSET, Data16And, Data16Or);
+  SaScriptMemReadWrite (
+    EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+    EfiBootScriptWidthUint16,
+    (UINTN) (PegBaseAddress + R_SA_PEG_DCTL2_OFFSET),
+    &Data16Or,
+    &Data16And
+    );
+  mDeviceLtrObffSave [RootBridgeIndex][0] = MmioRead16 (PegBaseAddress + R_SA_PEG_DCTL2_OFFSET);
+
+  ///
+  /// Apply to end point devices
+  ///
+  EndpointCompleted = 1;
+  while (EndpointCompleted < mNumberOfDeviceFound [RootBridgeIndex]) {
+    ///
+    /// Read the Link Capability register's ASPM setting and apply ASPM setting to end point device
+    ///
+    LinkAspmCap = (MmioRead16 (mDeviceCapMmBaseSave [RootBridgeIndex][EndpointCompleted] + 0x00C) >> 10) & 3;
+    MmioAndThenOr16 (mDeviceCapMmBaseSave [RootBridgeIndex][EndpointCompleted] + 0x010, (UINT16)~3, EndPointAspm & LinkAspmCap);
+    DEBUG ((EFI_D_INFO, "Apply Aspm settings to device [%X] to Aspm value: 0x%x and in fact set to 0x%x\n", mDeviceCapMmBaseSave [RootBridgeIndex][EndpointCompleted] + 0x10, EndPointAspm, EndPointAspm & LinkAspmCap));
+    ///
+    /// Save register setting for S3 resume.
+    ///
+    mDeviceAspmSave [RootBridgeIndex][EndpointCompleted] = MmioRead8 (mDeviceCapMmBaseSave [RootBridgeIndex][EndpointCompleted] + 0x010);
+    SaScriptMemWrite (
+      EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+      EfiBootScriptWidthUint8,
+      (UINTN) (mDeviceCapMmBaseSave [RootBridgeIndex][EndpointCompleted] + 0x010),
+      1,
+      &mDeviceAspmSave [RootBridgeIndex][EndpointCompleted]
+      );
+    ///
+    /// Power optimization on end point device
+    ///
+    PcieSetEndpointLtrObff (RootBridgeIndex, EndpointCompleted);
+    EndpointCompleted ++;
+  }
+}
+
+/**
+  This function apply additional settings before ASPM enabling
+
+  @param[in] RootBridgeIndex   - Root Bridge Index to select mDeviceCapMmBaseSave array elements for ASPM capability calculation.
+**/
+VOID
+PcieAdditionalSettingBeforeASPM (
+  IN UINT8      RootBridgeIndex
+  )
+{
+  UINT32 Data32Or;
+  UINT32 Data32And;
+
+  if ((mPegAspmPerPort[RootBridgeIndex] != PcieAspmDisabled) && (mCommonClock [RootBridgeIndex] == 1)) {
+    ///
+    /// Enable support for L0s and L1 by programming the `Active State Link
+    /// PM Support' field of the LCAP register at D.F.R 0ACh [11:10] = `11b'.
+    ///
+    MmioOr32 ((mDeviceCapMmBaseSave[RootBridgeIndex][0] & (UINTN) ~0xFF) + 0x0AC, BIT11 | BIT10);
+    Data32Or  = (BIT11 | BIT10);
+    Data32And = (UINT32)~(BIT11 | BIT10);
+    SaScriptMemReadWrite (
+      EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+      EfiBootScriptWidthUint32,
+      (UINTN) ((mDeviceCapMmBaseSave [RootBridgeIndex][0] & (UINTN) ~0xFF) + 0x0AC),
+      &Data32Or,  ///< Data to be ORed
+      &Data32And  ///< Data to be ANDed
+      );
+
+    ///
+    /// Set D.F.R 0200h [27:26] to `00b'.
+    ///
+    MmioAnd32 ((mDeviceCapMmBaseSave[RootBridgeIndex][0] & (UINTN) ~0xFF) + 0x200, (UINT32) ~(BIT27 | BIT26));
+    Data32Or  = 0;
+    Data32And = (UINT32)~(BIT27 | BIT26);
+    SaScriptMemReadWrite (
+      EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+      EfiBootScriptWidthUint32,
+      (UINTN) ((mDeviceCapMmBaseSave [RootBridgeIndex][0] & (UINTN) ~0xFF) + 0x200),
+      &Data32Or,  ///< Data to be ORed
+      &Data32And  ///< Data to be ANDed
+      );
+
+    ///
+    /// Set D.F.R 0258 [2] to '1b' for PCI Express 2.0 compliance
+    /// Note: Other fields within this register must not be changed
+    /// while writing to D1.F0.R 0258h [2]
+    ///
+    MmioOr16 ((mDeviceCapMmBaseSave [RootBridgeIndex][0] & (UINTN) ~0xFF) + R_SA_PEG_CFG4_OFFSET, BIT2);
+    Data32Or  = BIT2;
+    Data32And = (UINT32)~(BIT2);
+    SaScriptMemReadWrite (
+      EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+      EfiBootScriptWidthUint32,
+      (UINTN) ((mDeviceCapMmBaseSave [RootBridgeIndex][0] & (UINTN) ~0xFF) + R_SA_PEG_CFG4_OFFSET),
+      &Data32Or,  ///< Data to be ORed
+      &Data32And  ///< Data to be ANDed
+      );
+  }
+}
+
+/**
+  This function does all SA ASPM initialization
+**/
+VOID
+SaAspm (
+  VOID
+  )
+{
+  BOOLEAN                         AutoFlag;
+  UINT16                          RootPortAspm;
+  UINT16                          EndPointAspm;
+  UINT8                           PegComplete;
+  SA_PCIE_ASPM_CONFIG             PegAspmSetup;
+  UINT8                           PegAspmL0sSetup;
+
+  ///
+  /// Scan PEG devices and program ASPM
+  ///
+  for (PegComplete = 0; PegComplete < MAX_SUPPORTED_ROOT_BRIDGE_NUMBER; PegComplete++) {
+    if (mDeviceCapMmBaseSave [PegComplete][0] == 0) {
+      continue;
+    }
+    PegAspmSetup      = mPegAspmPerPort[PegComplete];
+    PegAspmL0sSetup   = mPegAspmL0sPerPort[PegComplete];
+    RootPortAspm      = 0;
+    EndPointAspm      = 0;
+    AutoFlag          = FALSE;
+
+    PcieAdditionalSettingBeforeASPM (PegComplete);
+    DEBUG ((EFI_D_INFO, "PegAspmSetup[%x]=%x\n", PegComplete, PegAspmSetup));
+    DEBUG ((EFI_D_INFO, "PegAspmL0sSetup[%x]=%x\n", PegComplete, PegAspmL0sSetup));
+    if ((PegAspmSetup != PcieAspmDisabled) && (mCommonClock [PegComplete] == 1)) {
+      ///
+      /// Select L1/L0 programming based on setup questions
+      ///
+      switch(PegAspmSetup) {
+        case PcieAspmL1:///<2
+        case PcieAspmL0sL1:///<3
+          RootPortAspm = L1_SET;
+          EndPointAspm = L1_SET;
+
+          ///
+          /// If L1's only then break, else also program L0's
+          ///
+          if (PegAspmSetup == PcieAspmL1 ) {
+            break;
+            }
+        case PcieAspmL0s:///<1
+          RootPortAspm |= (PegAspmL0sSetup & L0_SET );
+          EndPointAspm |= ((PegAspmL0sSetup >> 1 ) & L0_SET );
+          break;
+        case PcieAspmAutoConfig: ///<4
+        case PcieAspmMax: ///<5
+          AutoFlag = TRUE;
+          break;
+        case PcieAspmDisabled:
+        default:
+          break;
+      }
+    }
+    DEBUG ((EFI_D_INFO, "RootPortAspm=%x\n", RootPortAspm ));
+    DEBUG ((EFI_D_INFO, "EndPointAspm=%x\n", EndPointAspm ));
+    PcieEnumerateDeviceToApplyASPM(PegComplete, AutoFlag, RootPortAspm, EndPointAspm);
+  }
+  ///
+  /// Program override register with final latency values.
+  ///
+  PcieILtrOverride ();
+  return;
+}
+
+/**
+  This function checks PEG end point device for extended tag capability and enables them if they are.
+**/
+VOID
+EnableExtendedTag (
+  VOID
+  )
+{
+  UINT8       RootBridgeCompleted;
+  UINT8       EndpointCompleted;
+  UINTN       RootPortPcieCapMmBase;
+  UINTN       EndPointPcieCapMmBase;
+  UINTN       PcieCapMmBase;
+
+  ///
+  /// Scan PEG devices
+  ///
+  for (RootBridgeCompleted = 0; RootBridgeCompleted < MAX_SUPPORTED_ROOT_BRIDGE_NUMBER; RootBridgeCompleted++) {
+    RootPortPcieCapMmBase = mDeviceCapMmBaseSave [RootBridgeCompleted][0];
+    if (RootPortPcieCapMmBase == 0) {
+      continue;
+    }
+    for (EndpointCompleted = 0; EndpointCompleted < mNumberOfDeviceFound [RootBridgeCompleted]; EndpointCompleted++) {
+      if (EndpointCompleted != 0) {
+        EndPointPcieCapMmBase = mDeviceCapMmBaseSave [RootBridgeCompleted][EndpointCompleted];
+        DEBUG ((EFI_D_INFO, "Extended tag scan End Point [B%X|D%X|F%X|R%X]\n",
+                               (EndPointPcieCapMmBase >> 20)   & mMaxBusNumberSupported,
+                               (EndPointPcieCapMmBase >> 15)   & 0x1F,
+                               (EndPointPcieCapMmBase >> 12)   & 0x07,
+                               (EndPointPcieCapMmBase + 0x010) & 0xFFF));
+        ///
+        /// If extended tag is supported, enable it.
+        ///
+        if (((MmioRead32 (EndPointPcieCapMmBase + 0x4)) & BIT5) != 0) {
+          MmioOr16 (EndPointPcieCapMmBase + 0x8, BIT8);
+          DEBUG ((EFI_D_INFO, "Extended tag enabled [B%X|D%X|F%X|R%X]\n",
+                                 (EndPointPcieCapMmBase >> 20)   & mMaxBusNumberSupported,
+                                 (EndPointPcieCapMmBase >> 15)   & 0x1F,
+                                 (EndPointPcieCapMmBase >> 12)   & 0x07,
+                                 (EndPointPcieCapMmBase + 0x010) & 0xFFF));
+        }
+      }
+      ///
+      /// Save Device Control Register value on all bridges and devices for S3 resume
+      ///
+      PcieCapMmBase = mDeviceCapMmBaseSave [RootBridgeCompleted][EndpointCompleted];
+      mDeviceControlRegisterSave [RootBridgeCompleted][EndpointCompleted] = MmioRead16 (PcieCapMmBase + 0x8);
+      SaScriptMemWrite (
+        EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+        EfiBootScriptWidthUint16,
+        (UINTN) (PcieCapMmBase + 0x8),
+        1,
+        &mDeviceControlRegisterSave [RootBridgeCompleted][EndpointCompleted]
+        );
+    }
+  }
+  return;
+}
+#endif  // PEG_FLAG
+
+/**
+  This function saves/restores Chipset registers
+
+  @param[in] IsSaving                  - TRUE for saving and FALSE for restoring
+  @param[in] PciRegistersSaveTable[]   - The register table that has to be saved/restored
+  @param[in] PciRegistersSaveTableSize - Size of above table
+  @param[in] PciRegistersSaveBuffer    - A saving/restoring buffer for those register settings.
+**/
+VOID
+SaSaveRestoreChipset (
+  IN     BOOLEAN                       IsSaving,
+  IN     BOOT_SCRIPT_PCI_REGISTER_SAVE PciRegistersSaveTable[],
+  IN     UINTN                         PciRegistersSaveTableSize,
+  IN OUT UINTN                         *PciRegistersSaveBuffer
+)
+{
+  UINT8    Index;
+
+  if (IsSaving == TRUE) {
+    DEBUG ((EFI_D_INFO, "SA Save PCI register settings\n"));
+    ///
+    /// Save SA PCI Registers for S3 resume
+    ///
+    for (Index = 0; Index < PciRegistersSaveTableSize; Index++) {
+      PciRegistersSaveBuffer[Index] = MmioRead32 (PciRegistersSaveTable[Index].Address);
+      SaScriptMemWrite (
+        EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+        EfiBootScriptWidthUint32,
+        (UINTN) PciRegistersSaveTable[Index].Address,
+        1,
+        &PciRegistersSaveBuffer[Index]
+        );
+      DEBUG ((EFI_D_INFO, "SA Register = %X, SaPciRegSave = %08X\n", PciRegistersSaveTable[Index].Address, PciRegistersSaveBuffer[Index]));
+    }
+  } else {
+    DEBUG ((EFI_D_INFO, "SA Restore PCI register settings\n"));
+    ///
+    /// Restore SA PCI Registers for S3 resume
+    ///
+    for (Index = 0; Index < PciRegistersSaveTableSize; Index++) {
+      MmioWrite32 (PciRegistersSaveTable[Index].Address, (UINT32) PciRegistersSaveBuffer[Index]);
+      DEBUG ((EFI_D_INFO, "SA Register = %X, SaPciRegSave = %08X\n", PciRegistersSaveTable[Index].Address, PciRegistersSaveBuffer[Index]));
+    }
+  }
+}
+
+/**
+  This function saves/restores platform relative registers
+
+  @param[in] IsSaving                  - TRUE for saving and FALSE for restoring
+**/
+VOID
+SaSaveRestorePlatform (
+  IN BOOLEAN        IsSaving
+)
+{
+  UINT8    Index;
+  UINT8    Data8;
+
+  ///
+  /// Save (or restore) IGFX registers
+  /// When saving, it has to be done after all BAR/Command registers have been assigned.
+  ///
+  if (MmPci16 (0, SA_IGD_BUS, SA_IGD_DEV, SA_IGD_FUN_0, PCI_VID) != 0xFFFF) {
+    SaSaveRestoreChipset (IsSaving, mSaIgfxPciRegistersSaveTable, sizeof (mSaIgfxPciRegistersSaveTable) / sizeof (BOOT_SCRIPT_PCI_REGISTER_SAVE), mSaIgfxPciRegistersSave);
+  }
+
+  if (IsSaving == TRUE) {
+    DEBUG ((EFI_D_INFO, "SA Save platform register settings\n"));
+    ///
+    /// Save PAM register
+    ///
+    for (Index = 0; Index < MAX_PAM_REG_COUNT; Index++) {
+      mPAMSave[Index] = MmPci8 (0, SA_MC_BUS, SA_MC_DEV, SA_MC_FUN, PAM_REG_BASE + Index);
+      SaScriptMemWrite (
+        EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+        EfiBootScriptWidthUint8,
+        (UINTN) MmPciAddress (0, SA_MC_BUS, SA_MC_DEV, SA_MC_FUN, PAM_REG_BASE + Index),
+        1,
+        &mPAMSave[Index]
+        );
+    }
+  } else {
+    DEBUG ((EFI_D_INFO, "SA Restore platform register settings\n"));
+    ///
+    /// Restore PAM register
+    ///
+    for (Index = 0; Index < MAX_PAM_REG_COUNT; Index++) {
+      MmPci8 (0, SA_MC_BUS, SA_MC_DEV, SA_MC_FUN, PAM_REG_BASE + Index) = mPAMSave [Index];
+    }
+  }
+  ///
+  /// CRID configuration
+  ///
+  if (mCridEnable == TRUE) {
+    Data8 = CRID_DATA;
+  } else {
+    Data8 = CRID_LOCK;
+  }
+  MmPci8 (0, SA_MC_BUS, SA_MC_DEV, SA_MC_FUN, PCI_RID) = Data8;
+  SaScriptMemWrite (
+    EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+    EfiBootScriptWidthUint8,
+    (UINTN) MmPciAddress (0, SA_MC_BUS, SA_MC_DEV, SA_MC_FUN, 0x08),
+    1,
+    &Data8
+    );
+
+}
+
+/**
+  This function does SA security lock
+**/
+VOID
+SaSecurityLock (
+  VOID
+)
+{
+  UINT8           Index;
+  UINT64          BaseAddress;
+  UINT32          RegOffset;
+  UINT32          Data32And;
+  UINT32          Data32Or;
+  CPU_STEPPING    CpuSteppingId;
+  CPU_FAMILY      CpuFamilyId;
+
+  CpuSteppingId = GetCpuStepping();
+  CpuFamilyId   = GetCpuFamily();
+
+  ///
+  /// 17.2 System Agent Security Lock configuration
+  ///
+    DEBUG ((EFI_D_INFO, "SaSecurityLock\n"));
+    for (Index = 0; Index < (sizeof (mSaSecurityRegisters) / sizeof (BOOT_SCRIPT_REGISTER_SETTING)); Index++) {
+      BaseAddress = mSaSecurityRegisters[Index].BaseAddr;
+      RegOffset   = mSaSecurityRegisters[Index].Offset;
+      Data32And   = mSaSecurityRegisters[Index].AndMask;
+      Data32Or    = mSaSecurityRegisters[Index].OrMask;
+
+      if (mDevice4Enable == TRUE) {
+        if (RegOffset ==  0x50FC){
+          Data32Or = 0x87; ///< unlock bit3 if Device (0,4,0) is enabbled.
+        }
+      }
+      MmioAndThenOr32 (BaseAddress + RegOffset, Data32And, Data32Or);
+      SaScriptMemReadWrite (
+        EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+        EfiBootScriptWidthUint32,
+        (UINTN) (BaseAddress + RegOffset),
+        &Data32Or,  ///< Data to be ORed
+        &Data32And  ///< Data to be ANDed
+        );
+    }
+
+    ///
+    /// Lock processor/chipset BAR registers
+    ///
+
+    if (!(((CpuFamilyId == EnumCpuHsw)    && (CpuSteppingId <= EnumHswB0)   ) ||
+          ((CpuFamilyId == EnumCpuHswUlt) && (CpuSteppingId <= EnumHswUltB0)) ||
+          ((CpuFamilyId == EnumCpuCrw)    && (CpuSteppingId <= EnumCrwB0)   ) )) {
+      AsmMsrOr64 (0x2e7, 1);
+    }
+}
+
+#ifdef PEG_FLAG
+/**
+  This function handles SA S3 resume
+**/
+VOID
+SaS3Resume (
+  VOID
+)
+{
+  UINT8                           PegComplete;
+  UINT8                           EndpointCompleted;
+  UINT32                          PegBaseAddress;
+
+#ifndef AMI_OVERRIDE_FOR_ULT_FASTBOOT
+  CPU_FAMILY CpuFamilyId;
+  CpuFamilyId = GetCpuFamily();
+  if (CpuFamilyId == EnumCpuHswUlt) return;
+#endif // AMI_OVERRIDE_FOR_ULT_FASTBOOT
+
+  DEBUG ((EFI_D_INFO, "SA S3 resume\n"));
+  if (mEnumStatus == EFI_SUCCESS) {
+    ///
+    /// Restore Bus number assignment first
+    ///
+    for (PegComplete = 0; PegComplete < MAX_SUPPORTED_ROOT_BRIDGE_NUMBER; PegComplete++) {
+      if (mDeviceCapMmBaseSave [PegComplete][0] == 0) {
+        continue;
+      }
+      EndpointCompleted = 0;
+      while (EndpointCompleted < mNumberOfDeviceFound [PegComplete]) {
+        PegBaseAddress = (mDeviceCapMmBaseSave [PegComplete][EndpointCompleted] & (UINTN) ~0xFF);
+        MmioWrite32 (PegBaseAddress + PCI_PBUS, mDeviceBusNumberSave [PegComplete][EndpointCompleted]);
+        DEBUG ((EFI_D_INFO, " Restore Bus number [%X] = %08X\n", PegBaseAddress + PCI_PBUS, MmioRead32 (PegBaseAddress + PCI_PBUS)));
+        EndpointCompleted ++;
+      }
+    }
+    for (PegComplete = 0; PegComplete < MAX_SUPPORTED_ROOT_BRIDGE_NUMBER; PegComplete++) {
+      if (mDeviceCapMmBaseSave [PegComplete][0] == 0) {
+        continue;
+      }
+      PcieAdditionalSettingBeforeASPM (PegComplete);
+      EndpointCompleted = 0;
+      while (EndpointCompleted < mNumberOfDeviceFound [PegComplete]) {
+        PegBaseAddress = (mDeviceCapMmBaseSave [PegComplete][EndpointCompleted] & (UINTN) ~0xFF);
+        ///
+        /// Restore Max Pay Load and Extended Tag
+        ///
+        MmioWrite16 (mDeviceCapMmBaseSave [PegComplete][EndpointCompleted] + 0x8, mDeviceControlRegisterSave [PegComplete][EndpointCompleted]);
+        DEBUG ((EFI_D_INFO, "[B%X|D%X|F%X|R%X] DCTL=%X\n",
+                               (mDeviceCapMmBaseSave [PegComplete][EndpointCompleted] >> 20)  & mMaxBusNumberSupported,
+                               (mDeviceCapMmBaseSave [PegComplete][EndpointCompleted] >> 15)  & 0x1F,
+                               (mDeviceCapMmBaseSave [PegComplete][EndpointCompleted] >> 12)  & 0x07,
+                               (mDeviceCapMmBaseSave [PegComplete][EndpointCompleted] + 0x08) & 0xFFF,
+                               mDeviceControlRegisterSave [PegComplete][EndpointCompleted]));
+        ///
+        /// Restore ASPM and Common Clock
+        ///
+        MmioWrite8 ((mDeviceCapMmBaseSave [PegComplete][EndpointCompleted] + 0x010), mDeviceAspmSave [PegComplete][EndpointCompleted]);
+        DEBUG ((EFI_D_INFO, "[B%X|D%X|F%X|R%X] ASPM/CommonClock=%X\n",
+                               (mDeviceCapMmBaseSave [PegComplete][EndpointCompleted] >> 20)  & mMaxBusNumberSupported,
+                               (mDeviceCapMmBaseSave [PegComplete][EndpointCompleted] >> 15)  & 0x1F,
+                               (mDeviceCapMmBaseSave [PegComplete][EndpointCompleted] >> 12)  & 0x07,
+                               (mDeviceCapMmBaseSave [PegComplete][EndpointCompleted] + 0x10) & 0xFFF,
+                               mDeviceAspmSave [PegComplete][EndpointCompleted]));
+        ///
+        /// Restore PEG power optimization.
+        ///
+        MmioAndThenOr16 (mDeviceCapMmBaseSave [PegComplete][EndpointCompleted] + 0x28, (UINT16)~(BIT10 + BIT13 + BIT14), mDeviceLtrObffSave [PegComplete][EndpointCompleted]);
+        DEBUG ((EFI_D_INFO, "[B%X|D%X|F%X|R%X] LTR/OBFF=%X\n",
+                               (mDeviceCapMmBaseSave [PegComplete][EndpointCompleted] >> 20)  & mMaxBusNumberSupported,
+                               (mDeviceCapMmBaseSave [PegComplete][EndpointCompleted] >> 15)  & 0x1F,
+                               (mDeviceCapMmBaseSave [PegComplete][EndpointCompleted] >> 12)  & 0x07,
+                               (mDeviceCapMmBaseSave [PegComplete][EndpointCompleted] + 0x28) & 0xFFF,
+                               mDeviceLtrObffSave [PegComplete][EndpointCompleted]));
+
+        if (mDeviceExtCapLtrOffsetSave [PegComplete][EndpointCompleted] != 0) {
+          MmioAndThenOr16 (PegBaseAddress + mDeviceExtCapLtrOffsetSave [PegComplete][EndpointCompleted] + 0x4, (UINT16) (~0x1FFF), mDeviceMaxSnoopLatencySave [PegComplete][EndpointCompleted]);
+          DEBUG ((EFI_D_INFO, "[B%X|D%X|F%X|R%X] Max snoop latency=%X\n",
+                                 ((PegBaseAddress + mDeviceExtCapLtrOffsetSave [PegComplete][EndpointCompleted]) >> 20)  & mMaxBusNumberSupported,
+                                 ((PegBaseAddress + mDeviceExtCapLtrOffsetSave [PegComplete][EndpointCompleted]) >> 15)  & 0x1F,
+                                 ((PegBaseAddress + mDeviceExtCapLtrOffsetSave [PegComplete][EndpointCompleted]) >> 12)  & 0x07,
+                                 (PegBaseAddress + mDeviceExtCapLtrOffsetSave [PegComplete][EndpointCompleted] + 0x4) & 0xFFF,
+                                 mDeviceMaxSnoopLatencySave [PegComplete][EndpointCompleted]));
+
+          MmioAndThenOr16 ((PegBaseAddress + mDeviceExtCapLtrOffsetSave [PegComplete][EndpointCompleted] + 0x6), (UINT16) (~0x1FFF), mDeviceMaxNoSnoopLatencySave [PegComplete][EndpointCompleted]);
+          DEBUG ((EFI_D_INFO, "[B%X|D%X|F%X|R%X] Max No-snoop latency=%X\n",
+                                 ((PegBaseAddress + mDeviceExtCapLtrOffsetSave [PegComplete][EndpointCompleted]) >> 20)  & mMaxBusNumberSupported,
+                                 ((PegBaseAddress + mDeviceExtCapLtrOffsetSave [PegComplete][EndpointCompleted]) >> 15)  & 0x1F,
+                                 ((PegBaseAddress + mDeviceExtCapLtrOffsetSave [PegComplete][EndpointCompleted]) >> 12)  & 0x07,
+                                 (PegBaseAddress + mDeviceExtCapLtrOffsetSave [PegComplete][EndpointCompleted] + 0x6) & 0xFFF,
+                                 mDeviceMaxNoSnoopLatencySave [PegComplete][EndpointCompleted]));
+        }
+        if (mDeviceExtCapVcOffsetSave [PegComplete][EndpointCompleted]) {
+          MmioAndThenOr8 ((mDeviceExtCapVcOffsetSave [PegComplete][EndpointCompleted] + 0x14), 0, mDeviceTcxVc0MappingSave [PegComplete][EndpointCompleted]);
+          DEBUG ((EFI_D_INFO, "[B%X|D%X|F%X|R%X] TCx/VC0 mapping=%X\n",
+                                 ((PegBaseAddress + mDeviceExtCapLtrOffsetSave [PegComplete][EndpointCompleted]) >> 20)  & mMaxBusNumberSupported,
+                                 ((PegBaseAddress + mDeviceExtCapLtrOffsetSave [PegComplete][EndpointCompleted]) >> 15)  & 0x1F,
+                                 ((PegBaseAddress + mDeviceExtCapLtrOffsetSave [PegComplete][EndpointCompleted]) >> 12)  & 0x07,
+                                 (PegBaseAddress + mDeviceExtCapLtrOffsetSave [PegComplete][EndpointCompleted] + 0x14) & 0xFFF,
+                                 mDeviceTcxVc0MappingSave [PegComplete][EndpointCompleted]));
+        }
+        EndpointCompleted ++;
+      }
+      ///
+      /// If common clock supported on root port and endpoint, retrain link
+      ///
+      if (mCommonClock [PegComplete] == 1) {
+        DEBUG ((EFI_D_INFO, "Retrain Link for Common Clock\n"));
+        ///
+        /// Retrain the Link per PCI Express Specification.
+        ///
+        MmioOr8 (mDeviceCapMmBaseSave [PegComplete][0] + 0x010, BIT5);
+
+        ///
+        /// Wait until Re-Training has completed.
+        ///
+        while ((MmioRead16 (mDeviceCapMmBaseSave [PegComplete][0] + 0x012) & BIT11) != 0) {}
+      }
+    }
+  }
+  ///
+  /// Re-do this during S3 resume
+  ///
+  PcieILtrOverride ();
+}
+#endif  // PEG_FLAG
+
+/**
+  Wrapper function for all SA S3 resume tasks which can be a callback function.
+**/
+VOID
+SaS3ResumeCallback (
+  VOID
+)
+{
+#ifdef PEG_FLAG
+    SaS3Resume ();
+#endif  // PEG_FLAG
+    SaSaveRestoreChipset (FALSE, mSaChipsetPciRegistersSaveTable, sizeof (mSaChipsetPciRegistersSaveTable) / sizeof (BOOT_SCRIPT_PCI_REGISTER_SAVE), mSaChipsetPciRegistersSave);
+    SaSaveRestorePlatform (FALSE);
+    SaSecurityLock ();
+}
+
+/**
+  Wrapper function for all SA ASPM tasks and extended tag which can be a callback function.
+**/
+VOID
+SaPcieConfigAfterOpRom (
+  VOID
+)
+{
+
+#ifndef AMI_OVERRIDE_FOR_ULT_FASTBOOT
+  CPU_FAMILY CpuFamilyId;
+  CpuFamilyId = GetCpuFamily();
+  if (CpuFamilyId == EnumCpuHswUlt) return;
+#endif // AMI_OVERRIDE_FOR_ULT_FASTBOOT
+
+#ifdef PEG_FLAG
+    DEBUG ((EFI_D_INFO, "SA ASPM\n"));
+    if (mEnumStatus == EFI_SUCCESS) {
+      SaAspm ();
+      ///
+      /// Device Control Register on all endpoint devices is saved after the OpRom has run in EnableExtendedTag (DXE phase will still use ExitPmAuth)
+      /// This is to prevent duplication of saving this register in different phases.
+      ///
+      EnableExtendedTag ();
+    }
+#endif  // PEG_FLAG
+}
+
+/**
+  Wrapper function for all SA enumeration tasks which can be a callback function.
+**/
+VOID
+SaPcieEnumCallback (
+  VOID
+)
+{
+#ifndef AMI_OVERRIDE_FOR_ULT_FASTBOOT
+  CPU_FAMILY CpuFamilyId;
+  CpuFamilyId = GetCpuFamily();
+  if (CpuFamilyId != EnumCpuHswUlt) {
+#endif // AMI_OVERRIDE_FOR_ULT_FASTBOOT
+    DEBUG ((EFI_D_INFO, "SA PCIe enumeration\n"));
+#ifdef PEG_FLAG
+    ///
+    /// Expected to execute in ExitPmAuth point (before OROM)
+    ///
+    mEnumStatus = EnumerateAllPcieDevices ();
+    if (mEnumStatus == EFI_SUCCESS) {
+      SaPcieConfigBeforeOpRom ();
+    }
+#endif  // PEG_FLAG
+#ifndef AMI_OVERRIDE_FOR_ULT_FASTBOOT
+  }
+#endif
+    ///
+    /// Save Chipset registers
+    ///
+    SaSaveRestoreChipset (TRUE, mSaChipsetPciRegistersSaveTable, sizeof (mSaChipsetPciRegistersSaveTable) / sizeof (BOOT_SCRIPT_PCI_REGISTER_SAVE), mSaChipsetPciRegistersSave);
+}
+
+/**
+  This function will initialize all required platform policy into global veriables so no need to locate policy protocol during runtime.
+**/
+VOID
+SaPcieInitPolicy (
+  IN DXE_PLATFORM_SA_POLICY_PROTOCOL *DxePlatformSaPolicy
+)
+{
+  UINT8  RootPortCount;
+  UINT8  Index;
+
+  ///
+  /// Initialize module global variables - Stepping ID and Platform Policy
+  ///
+  for (Index = 0; Index < (sizeof (mSaChipsetPciRegistersSaveTable) / sizeof (BOOT_SCRIPT_PCI_REGISTER_SAVE)); Index++) {
+    mSaChipsetPciRegistersSaveTable[Index].Address = MmPciAddress (0, SA_MC_BUS, SA_MC_DEV, SA_MC_FUN, mSaChipsetPciRegistersTable[Index]);
+  }
+
+  for (Index = 0; Index < (sizeof (mSaIgfxPciRegistersSaveTable) / sizeof (BOOT_SCRIPT_PCI_REGISTER_SAVE)); Index++) {
+    mSaIgfxPciRegistersSaveTable[Index].Address = MmPciAddress (0, SA_IGD_BUS, SA_IGD_DEV, SA_IGD_FUN_0, mSaIgfxPciRegistersTable[Index]);
+  }
+
+  for (Index = 0; Index < (sizeof (mSaSecurityRegisters) / sizeof (BOOT_SCRIPT_REGISTER_SETTING)); Index++) {
+    if (mSaSecurityRegisters[Index].BaseAddr != MCH_BASE_ADDRESS) {
+      mSaSecurityRegisters[Index].BaseAddr = (UINTN) MmPciAddress (0,0,0,0,0);
+    }
+  }
+
+  for (RootPortCount = 0; RootPortCount < MAX_SUPPORTED_ROOT_BRIDGE_NUMBER; RootPortCount++) {
+    mPegAspmPerPort[RootPortCount] = DxePlatformSaPolicy->PcieConfig->PegAspm[RootPortCount];
+    mPegAspmL0sPerPort[RootPortCount] = DxePlatformSaPolicy->PcieConfig->PegAspmL0s[RootPortCount];
+    if (DxePlatformSaPolicy->Revision >= DXE_SA_PLATFORM_POLICY_PROTOCOL_REVISION_7) {
+      mPegPwrOpt[RootPortCount] = DxePlatformSaPolicy->PcieConfig->PegPwrOpt[RootPortCount];
+    } else {
+      //
+      // This Platform policy protocol field may not have been initialized.
+      // Initialize a default for RC to use
+      //
+      mPegPwrOpt[RootPortCount].LtrEnable            = 1;
+      mPegPwrOpt[RootPortCount].LtrMaxSnoopLatency   = V_SA_LTR_MAX_SNOOP_LATENCY_VALUE;
+      mPegPwrOpt[RootPortCount].LtrMaxNoSnoopLatency = V_SA_LTR_MAX_NON_SNOOP_LATENCY_VALUE;
+      mPegPwrOpt[RootPortCount].ObffEnable           = 1;
+    }
+  }
+
+  if (DxePlatformSaPolicy->Revision >= DXE_SA_PLATFORM_POLICY_PROTOCOL_REVISION_2) {
+    mPcieAspmDevsOverride = DxePlatformSaPolicy->PcieConfig->PcieAspmDevsOverride;
+    mPcieLtrDevsOverride = DxePlatformSaPolicy->PcieConfig->PcieLtrDevsOverride;
+  }
+  mCridEnable = DxePlatformSaPolicy->MiscConfig->CridEnable;
+  mDevice4Enable = DxePlatformSaPolicy->MiscConfig->Device4Enable;
+  mSteppingId = GetCpuStepping ();
+
+  mBridgeId = (UINT8) (McD0PciCfg16 (R_SA_MC_DEVICE_ID) & 0xF0);
+  mBridgeSteppingId = mBridgeId + mSteppingId;
+
+  ///
+  /// Initialize Snoop and Non-Snoop Latencies
+  ///
+  mSnoopLatencyOvrValue        = 0;
+  mNonSnoopLatencyOvrValue     = 0;
+
+}
diff --git a/ReferenceCode/Chipset/SystemAgent/Library/SaPcieLib/Common/SaPcieLib.cif b/ReferenceCode/Chipset/SystemAgent/Library/SaPcieLib/Common/SaPcieLib.cif
new file mode 100644
index 0000000..f966a97
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/Library/SaPcieLib/Common/SaPcieLib.cif
@@ -0,0 +1,11 @@
+<component>
+	name = "SaPcieLib"
+	category = ModulePart
+	LocalRoot = "ReferenceCode\Chipset\SystemAgent\Library\SaPcieLib\Common\"
+	RefName = "SaPcieLib"
+[files]
+"SaPcieLib.sdl"
+"SaPcieLib.mak"
+"SaPcieLib.h"
+"SaPcieLib.c"
+<endComponent>
diff --git a/ReferenceCode/Chipset/SystemAgent/Library/SaPcieLib/Common/SaPcieLib.h b/ReferenceCode/Chipset/SystemAgent/Library/SaPcieLib/Common/SaPcieLib.h
new file mode 100644
index 0000000..99f19d7
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/Library/SaPcieLib/Common/SaPcieLib.h
@@ -0,0 +1,273 @@
+/** @file
+  Defines and prototypes for the library module
+
+@copyright
+  Copyright (c) 2012 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement
+**/
+#ifndef _SA_PCIE_LIB_H_
+#define _SA_PCIE_LIB_H_
+
+#include "EfiScriptLib.h"
+
+#define MAX_SUPPORTED_ROOT_BRIDGE_NUMBER  3
+#define MAX_SUPPORTED_DEVICE_NUMBER       192
+#define L0_SET                            BIT0
+#define L1_SET                            BIT1
+#define MAX_PAM_REG_COUNT                 7
+#define PAM_REG_BASE                      0x80
+#define CRID_DATA                         0x69
+#define CRID_LOCK                         0x17
+
+typedef struct {
+  UINT64                Address;
+  EFI_BOOT_SCRIPT_WIDTH Width;
+  UINT32                Value;
+} BOOT_SCRIPT_PCI_REGISTER_SAVE;
+
+EFI_STATUS
+EnumerateAllPcieDevices (
+  VOID
+  )
+/**
+  Enumerate all end point devices connected to root bridge ports and record their MMIO base address
+
+  @param[in] None
+
+  @exception EFI_UNSUPPORTED      PCIe capability structure not found
+  @retval    EFI_SUCCESS          All done successfully
+**/
+;
+
+VOID
+SaPcieConfigBeforeOpRom (
+  VOID
+  )
+/**
+  Sets Common Clock, TCx-VC0 mapping, and Max Payload for PCIe
+
+  @param[in] None
+
+  @retval None
+**/
+;
+
+VOID
+SaAspm (
+  VOID
+  )
+/**
+  This function does all SA ASPM initialization
+
+  @param[in] None
+
+  @retval None
+**/
+;
+
+VOID
+EnableExtendedTag (
+  VOID
+  )
+/**
+  This function checks PEG end point device for extended tag capability and enables them if they are.
+
+  @param[in] None
+
+  @retval None
+**/
+;
+
+VOID
+SaSaveRestoreChipset (
+  IN     BOOLEAN                       IsSaving,
+  IN     BOOT_SCRIPT_PCI_REGISTER_SAVE PciRegistersSaveTable[],
+  IN     UINTN                         PciRegistersSaveTableSize,
+  IN OUT UINTN                         *PciRegistersSaveBuffer
+)
+/**
+  This function saves/restores Chipset registers
+
+  @param[in] IsSaving                  - TRUE for saving and FALSE for restoring
+  @param[in] PciRegistersSaveTable[]   - The register table that has to be saved/restored
+  @param[in] PciRegistersSaveTableSize - Size of above table
+  @param[in] PciRegistersSaveBuffer    - A saving/restoring buffer for those register settings.
+
+  @retval None
+**/
+;
+
+VOID
+SaSaveRestorePlatform (
+  IN BOOLEAN        IsSaving
+)
+/**
+  This function saves/restores platform relative registers
+
+  @param[in] IsSaving                  - TRUE for saving and FALSE for restoring
+
+  @retval None
+**/
+;
+
+VOID
+SaSecurityLock (
+  VOID
+)
+/**
+  This function does SA security lock
+
+  @param[in] None
+
+  @retval None
+**/
+;
+
+VOID
+SaS3Resume (
+  VOID
+)
+/**
+  This function handles SA S3 resume
+
+  @param[in] None
+
+  @retval None
+**/
+;
+
+VOID
+SaS3ResumeCallback (
+  VOID
+)
+/**
+  Wrapper function for all SA S3 resume tasks which can be a callback function.
+
+  @param[in] None
+
+  @retval None
+**/
+;
+
+VOID
+SaPcieConfigAfterOpRom (
+  VOID
+)
+/**
+  Wrapper function for all SA ASPM tasks and extended tag which can be a callback function.
+
+  @param[in] None
+
+  @retval None
+**/
+;
+
+VOID
+SaPcieEnumCallback (
+  VOID
+)
+/**
+  Wrapper function for all SA enumeration tasks which can be a callback function.
+
+  @param[in] None
+
+  @retval None
+**/
+;
+
+VOID
+SaPcieInitPolicy (
+  IN DXE_PLATFORM_SA_POLICY_PROTOCOL *DxePlatformSaPolicy
+)
+/**
+  This function will initialize all required platform policy into global veriables so no need to locate policy protocol during runtime.
+
+  @param[in] None
+
+  @retval None
+**/
+;
+
+EFI_STATUS
+SaScriptMemWrite (
+  IN  UINT16                            TableName,
+  IN  EFI_BOOT_SCRIPT_WIDTH             Width,
+  IN  UINT64                            Address,
+  IN  UINTN                             Count,
+  IN  VOID                              *Buffer
+)
+/**
+  Wrapper for boot script with opcode EFI_BOOT_SCRIPT_MEM_WRITE_OPCODE
+
+  @param[in] TableName - Desired boot script table
+  @param[in] Width   - The width of the memory operations.
+  @param[in] Address - The base address of the memory operations.
+  @param[in] Count   - The number of memory operations to perform.
+  @param[in] Buffer  - The source buffer from which to write the data.
+
+  @retval EFI_NOT_FOUND - BootScriptSave Protocol not exist.
+  @retval EFI_STATUS - BootScriptSave Protocol exist, always returns EFI_SUCCESS
+**/
+;
+
+EFI_STATUS
+SaScriptMemReadWrite (
+  IN  UINT16                            TableName,
+  IN  EFI_BOOT_SCRIPT_WIDTH             Width,
+  IN  UINT64                            Address,
+  IN  VOID                              *Data,
+  IN  VOID                              *DataMask
+)
+/**
+  Wrapper for boot script with opcode EFI_BOOT_SCRIPT_MEM_READ_WRITE_OPCODE
+
+  @param[in] TableName - Desired boot script table
+  @param[in] Width   - The width of the memory operations.
+  @param[in] Address - The base address of the memory operations.
+  @param[in] Data    - A pointer to the data to be OR-ed.
+  @param[in] DataMask  - A pointer to the data mask to be AND-ed with the data read from the register.
+
+  @retval EFI_NOT_FOUND - BootScriptSave Protocol not exist.
+  @retval EFI_STATUS - BootScriptSave Protocol exist, always returns EFI_SUCCESS
+**/
+;
+
+EFI_STATUS
+SaScriptMemPoll (
+  IN  UINT16                            TableName,
+  IN  EFI_BOOT_SCRIPT_WIDTH             Width,
+  IN  UINT64                            Address,
+  IN  VOID                              *BitMask,
+  IN  VOID                              *BitValue,
+  IN  UINTN                             Duration,
+  IN  UINTN                             LoopTimes
+  )
+/**
+  Wrapper for boot script for Polling one memory mapping register
+
+  @param[in] TableName - Desired boot script table
+  @param[in] Width     - The width of the memory operations.
+  @param[in] Address   - The base address of the memory operations.
+  @param[in] BitMask   - A pointer to the bit mask to be AND-ed with the data read from the register.
+  @param[in] BitValue  - A pointer to the data value after to be Masked.
+  @param[in] Duration  - Duration in microseconds of the stall.
+  @param[in] LoopTimes - The times of the register polling.
+
+  @retval EFI_SUCCESS - The operation was executed successfully
+**/
+;
+
+#endif
diff --git a/ReferenceCode/Chipset/SystemAgent/Library/SaPcieLib/Common/SaPcieLib.mak b/ReferenceCode/Chipset/SystemAgent/Library/SaPcieLib/Common/SaPcieLib.mak
new file mode 100644
index 0000000..1228399
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/Library/SaPcieLib/Common/SaPcieLib.mak
@@ -0,0 +1,54 @@
+#*************************************************************************
+#*************************************************************************
+#**                                                                     **
+#**        (C)Copyright 1985-2011, American Megatrends, Inc.            **
+#**                                                                     **
+#**                       All Rights Reserved.                          **
+#**                                                                     **
+#**      5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093           **
+#**                                                                     **
+#**                       Phone: (770)-246-8600                         **
+#**                                                                     **
+#*************************************************************************
+#*************************************************************************
+
+# MAK file for the ModulePart:SaPcieLib
+EDK : SaPcieLib
+
+SaPcieLib : $(BUILD_DIR)\SaPcieLib.mak SaPcieLibBin
+
+$(BUILD_DIR)\SaPcieLib.mak : $(SaPcieLib_DIR)\$(@B).cif $(SaPcieLib_DIR)\$(@B).mak $(BUILD_RULES)
+	$(CIF2MAK) $(SaPcieLib_DIR)\$(@B).cif $(CIF2MAK_DEFAULTS)
+
+$(SaPcieLib_LIB) : SaPcieLib
+
+SaPcieLib_INCLUDES=\
+            $(EdkIIGlueLib_INCLUDES)\
+            $(PROJECT_CPU_INCLUDES)\
+            $(INTEL_MCH_INCLUDES)\
+            $(INTEL_PCH_INCLUDES)\
+
+SaPcieLib_DEFINES = \
+            $(CFLAGS) \
+    
+SaPcieLibBin: 
+	    $(MAKE) /$(MAKEFLAGS) $(EDK_DEFAULTS) \
+            /f $(BUILD_DIR)\SaPcieLib.mak all \
+            "MY_INCLUDES=$(SaPcieLib_INCLUDES)" \
+            "CFLAGS=$(SaPcieLib_DEFINES)"\
+            TYPE=LIBRARY LIBRARIES= \
+            LIBRARY_NAME=$(SaPcieLib_LIB)
+
+#*************************************************************************
+#*************************************************************************
+#**                                                                     **
+#**        (C)Copyright 1985-2011, American Megatrends, Inc.            **
+#**                                                                     **
+#**                       All Rights Reserved.                          **
+#**                                                                     **
+#**      5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093           **
+#**                                                                     **
+#**                       Phone: (770)-246-8600                         **
+#**                                                                     **
+#*************************************************************************
+#*************************************************************************
diff --git a/ReferenceCode/Chipset/SystemAgent/Library/SaPcieLib/Common/SaPcieLib.sdl b/ReferenceCode/Chipset/SystemAgent/Library/SaPcieLib/Common/SaPcieLib.sdl
new file mode 100644
index 0000000..ae305ab
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/Library/SaPcieLib/Common/SaPcieLib.sdl
@@ -0,0 +1,29 @@
+
+TOKEN
+        Name  = "SaPcieLib_SUPPORT"
+        Value  = "1"
+        Help  = "Main switch to enable SaPcieLib support in Project"
+        TokenType = Boolean
+        TargetMAK = Yes
+        Master = Yes
+End
+
+PATH
+        Name  = "SaPcieLib_DIR"
+End
+
+MODULE
+        Help  = "Includes SaPcieLib.mak to Project"
+        File  = "SaPcieLib.mak"
+End
+
+ELINK
+        Name  = "SaPcieLib_LIB"
+        InvokeOrder = ReplaceParent
+End
+
+ELINK
+        Name  = "$(BUILD_DIR)\SaPcieLib.lib"
+        Parent  = "SaPcieLib_LIB"
+        InvokeOrder = AfterParent
+End
\ No newline at end of file
diff --git a/ReferenceCode/Chipset/SystemAgent/Library/SaPcieLib/Dxe/SaPcieDxeLib.c b/ReferenceCode/Chipset/SystemAgent/Library/SaPcieLib/Dxe/SaPcieDxeLib.c
new file mode 100644
index 0000000..ccf7775
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/Library/SaPcieLib/Dxe/SaPcieDxeLib.c
@@ -0,0 +1,99 @@
+/** @file
+  This is DXE library code used by Intel System Agent PCIe library
+
+@copyright
+  Copyright (c) 2012 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement
+**/
+
+#include "EfiScriptLib.h"
+#include EFI_PROTOCOL_CONSUMER      (BootScriptSave)
+
+/**
+  Wrapper for boot script with opcode EFI_BOOT_SCRIPT_MEM_WRITE_OPCODE
+
+  @param[in] TableName - Desired boot script table
+  @param[in] Width   - The width of the memory operations.
+  @param[in] Address - The base address of the memory operations.
+  @param[in] Count   - The number of memory operations to perform.
+  @param[in] Buffer  - The source buffer from which to write the data.
+
+  @retval EFI_SUCCESS - Always returns EFI_SUCCESS
+**/
+EFI_STATUS
+SaScriptMemWrite (
+  IN  UINT16                            TableName,
+  IN  EFI_BOOT_SCRIPT_WIDTH             Width,
+  IN  UINT64                            Address,
+  IN  UINTN                             Count,
+  IN  VOID                              *Buffer
+)
+{
+  SCRIPT_MEM_WRITE (TableName, Width, Address, Count, Buffer);
+  return EFI_SUCCESS;
+}
+
+/**
+  Wrapper for boot script with opcode EFI_BOOT_SCRIPT_MEM_READ_WRITE_OPCODE
+
+  @param[in] TableName - Desired boot script table
+  @param[in] Width   - The width of the memory operations.
+  @param[in] Address - The base address of the memory operations.
+  @param[in] Data    - A pointer to the data to be OR-ed.
+  @param[in] DataMask  - A pointer to the data mask to be AND-ed with the data read from the register.
+
+  @retval EFI_SUCCESS - Always returns EFI_SUCCESS
+**/
+EFI_STATUS
+SaScriptMemReadWrite (
+  IN  UINT16                            TableName,
+  IN  EFI_BOOT_SCRIPT_WIDTH             Width,
+  IN  UINT64                            Address,
+  IN  VOID                              *Data,
+  IN  VOID                              *DataMask
+)
+{
+  SCRIPT_MEM_READ_WRITE (TableName, Width, Address, Data, DataMask);
+  return EFI_SUCCESS;
+}
+
+/**
+  Wrapper for boot script for Polling one memory mapping register
+
+  @param[in] TableName - Desired boot script table
+  @param[in] Width     - The width of the memory operations.
+  @param[in] Address   - The base address of the memory operations.
+  @param[in] BitMask   - A pointer to the bit mask to be AND-ed with the data read from the register.
+  @param[in] BitValue  - A pointer to the data value after to be Masked.
+  @param[in] Duration  - Duration in microseconds of the stall.
+  @param[in] LoopTimes - The times of the register polling.
+
+  @retval EFI_SUCCESS - Always returns EFI_SUCCESS
+**/
+EFI_STATUS
+SaScriptMemPoll (
+  IN  UINT16                            TableName,
+  IN  EFI_BOOT_SCRIPT_WIDTH             Width,
+  IN  UINT64                            Address,
+  IN  VOID                              *BitMask,
+  IN  VOID                              *BitValue,
+  IN  UINTN                             Duration,
+  IN  UINTN                             LoopTimes
+  )
+{
+  SCRIPT_MEM_POLL (TableName, Width, Address, BitMask, BitValue, Duration, LoopTimes);
+  return EFI_SUCCESS;
+}
diff --git a/ReferenceCode/Chipset/SystemAgent/Library/SaPcieLib/Dxe/SaPcieDxeLib.cif b/ReferenceCode/Chipset/SystemAgent/Library/SaPcieLib/Dxe/SaPcieDxeLib.cif
new file mode 100644
index 0000000..1574d65
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/Library/SaPcieLib/Dxe/SaPcieDxeLib.cif
@@ -0,0 +1,11 @@
+<component>
+	name = "SaPcieDxeLib"
+	category = ModulePart
+	LocalRoot = "ReferenceCode\Chipset\SystemAgent\Library\SaPcieLib\Dxe\"
+	RefName = "SaPcieDxeLib"
+[files]
+"SaPcieDxeLib.sdl"	
+"SaPcieDxeLib.mak"	
+"SaPcieDxeLib.c"
+"SaPcieDxeLib.inf"
+<endComponent>
diff --git a/ReferenceCode/Chipset/SystemAgent/Library/SaPcieLib/Dxe/SaPcieDxeLib.inf b/ReferenceCode/Chipset/SystemAgent/Library/SaPcieLib/Dxe/SaPcieDxeLib.inf
new file mode 100644
index 0000000..5ab9c93
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/Library/SaPcieLib/Dxe/SaPcieDxeLib.inf
@@ -0,0 +1,63 @@
+## @file
+#  Component description file for the SA PCIE library
+#
+#@copyright
+#  Copyright (c)  2012 Intel Corporation. All rights reserved
+#  This software and associated documentation (if any) is furnished
+#  under a license and may only be used or copied in accordance
+#  with the terms of the license. Except as permitted by such
+#  license, no part of this software or documentation may be
+#  reproduced, stored in a retrieval system, or transmitted in any
+#  form or by any means without the express written consent of
+#  Intel Corporation.
+#
+#  This file contains a 'Sample Driver' and is licensed as such
+#  under the terms of your license agreement with Intel or your
+#  vendor.  This file may be modified by the user, subject to
+#  the additional terms of the license agreement
+#
+
+[defines]
+BASE_NAME       =   SaPcieDxeLib
+COMPONENT_TYPE  =   LIBRARY
+
+[sources.common]
+  ../Common/SaPcieLib.h
+  ../Common/SaPcieLib.c
+  SaPcieDxeLib.c
+
+[includes.common]
+  .
+  $(EDK_SOURCE)/Foundation/Library/Pei/Include
+  $(EDK_SOURCE)/Foundation/Efi
+  $(EDK_SOURCE)/Foundation/Include
+  $(EDK_SOURCE)/Foundation/Efi/Include
+  $(EDK_SOURCE)/Foundation/Framework/Include
+  $(EFI_SOURCE)/$(PROJECT_PCH_ROOT)/Include
+  $(EFI_SOURCE)/$(PROJECT_PCH_ROOT)
+  $(EFI_SOURCE)/$(PROJECT_PCH_ROOT)/Include/Library
+  $(EFI_SOURCE)/$(PROJECT_SA_ROOT)/Library/SaPcieLib/Dxe
+  $(EFI_SOURCE)/$(PROJECT_SA_ROOT)/Include
+  $(EFI_SOURCE)/$(PROJECT_SA_ROOT)
+  $(EFI_SOURCE)/$(PROJECT_CPU_ROOT)/Include/Library
+  $(EFI_SOURCE)/$(PROJECT_CPU_ROOT)/Include
+#
+# EDK II Glue Library utilizes some standard headers from EDK
+#
+  $(EFI_SOURCE)
+  $(EDK_SOURCE)/Foundation
+  $(EDK_SOURCE)/Foundation/Framework
+  $(EDK_SOURCE)/Foundation/Include/IndustryStandard
+  $(EDK_SOURCE)/Foundation/Core/Dxe
+  $(EDK_SOURCE)/Foundation/Include/Pei
+  $(EDK_SOURCE)/Foundation/Library/Dxe/Include
+  $(EDK_SOURCE)/Foundation/Library/EdkIIGlueLib/Include
+
+[libraries.common]
+  EdkIIGlueBasePciLibPciExpress
+
+[nmake.common]
+C_FLAGS = $(C_FLAGS)
+C_STD_INCLUDE=
+
+
diff --git a/ReferenceCode/Chipset/SystemAgent/Library/SaPcieLib/Dxe/SaPcieDxeLib.mak b/ReferenceCode/Chipset/SystemAgent/Library/SaPcieLib/Dxe/SaPcieDxeLib.mak
new file mode 100644
index 0000000..fc86ac2
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/Library/SaPcieLib/Dxe/SaPcieDxeLib.mak
@@ -0,0 +1,46 @@
+#*************************************************************************
+#*************************************************************************
+#**                                                                     **
+#**        (C)Copyright 1985-2011, American Megatrends, Inc.            **
+#**                                                                     **
+#**                       All Rights Reserved.                          **
+#**                                                                     **
+#**      5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093           **
+#**                                                                     **
+#**                       Phone: (770)-246-8600                         **
+#**                                                                     **
+#*************************************************************************
+#*************************************************************************
+
+# MAK file for the ModulePart:SaPcieDxeLib
+EDK : SaPcieDxeLib
+
+SaPcieDxeLib : $(BUILD_DIR)\SaPcieDxeLib.mak SaPcieDxeLibBin
+
+$(BUILD_DIR)\SaPcieDxeLib.mak : $(SaPcieDxeLib_DIR)\$(@B).cif $(SaPcieDxeLib_DIR)\$(@B).mak $(BUILD_RULES)
+	$(CIF2MAK) $(SaPcieDxeLib_DIR)\$(@B).cif $(CIF2MAK_DEFAULTS)
+
+$(SaPcieDxeLib_LIB) : SaPcieDxeLib
+
+SaPcieDxeLib_DEFINES = \
+            $(CFLAGS) \
+    
+SaPcieDxeLibBin: $(SaPcieLib_LIB)
+	    $(MAKE) /$(MAKEFLAGS) $(EDK_DEFAULTS) \
+            /f $(BUILD_DIR)\SaPcieDxeLib.mak all \
+            "CFLAGS=$(SaPcieDxeLib_DEFINES)"\
+            TYPE=LIBRARY LIBRARIES= \
+            LIBRARY_NAME=$(SaPcieDxeLib_LIB)
+#*************************************************************************
+#*************************************************************************
+#**                                                                     **
+#**        (C)Copyright 1985-2011, American Megatrends, Inc.            **
+#**                                                                     **
+#**                       All Rights Reserved.                          **
+#**                                                                     **
+#**      5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093           **
+#**                                                                     **
+#**                       Phone: (770)-246-8600                         **
+#**                                                                     **
+#*************************************************************************
+#*************************************************************************
diff --git a/ReferenceCode/Chipset/SystemAgent/Library/SaPcieLib/Dxe/SaPcieDxeLib.sdl b/ReferenceCode/Chipset/SystemAgent/Library/SaPcieLib/Dxe/SaPcieDxeLib.sdl
new file mode 100644
index 0000000..2b306dd
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/Library/SaPcieLib/Dxe/SaPcieDxeLib.sdl
@@ -0,0 +1,33 @@
+TOKEN
+        Name  = "SaPcieDxeLib_SUPPORT"
+        Value  = "1"
+        Help  = "Main switch to enable SaPcieDxeLib support in Project"
+        TokenType = Boolean
+        TargetEQU = Yes
+        TargetMAK = Yes
+        TargetH = Yes
+        Master = Yes
+	    Token = "SaPcieLib_SUPPORT" "=" "1"
+#	    Token = "SA_PCIE_ASPM_IN_DXE" "=" "1"
+End
+
+PATH
+        Name  = "SaPcieDxeLib_DIR"
+	Help  = "SaPcieDxeLib file source directory"
+End
+
+MODULE
+        File  = "SaPcieDxeLib.mak"
+        Help  = "Includes SaPcieDxeLib.mak to Project"
+End
+
+ELINK
+        Name  = "SaPcieDxeLib_LIB"
+        InvokeOrder = ReplaceParent
+End
+
+ELINK
+        Name  = "$(BUILD_DIR)\SaPcieDxeLib.lib"
+        Parent  = "SaPcieDxeLib_LIB"
+        InvokeOrder = AfterParent
+End
\ No newline at end of file
diff --git a/ReferenceCode/Chipset/SystemAgent/Library/SaPcieLib/Smm/SaPcieSmmLib.c b/ReferenceCode/Chipset/SystemAgent/Library/SaPcieLib/Smm/SaPcieSmmLib.c
new file mode 100644
index 0000000..5d44c9c
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/Library/SaPcieLib/Smm/SaPcieSmmLib.c
@@ -0,0 +1,94 @@
+/** @file
+  This is SMM library code used by Intel System Agent PCIe library
+
+@copyright
+  Copyright (c) 2012 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement
+**/
+#include "EfiScriptLib.h"
+
+/**
+  Wrapper for boot script with opcode EFI_BOOT_SCRIPT_MEM_WRITE_OPCODE
+
+  @param[in] TableName - Desired boot script table
+  @param[in] Width     - The width of the memory operations.
+  @param[in] Address   - The base address of the memory operations.
+  @param[in] Count     - The number of memory operations to perform.
+  @param[in] Buffer    - The source buffer from which to write the data.
+
+  @retval EFI_SUCCESS  - The operation was executed successfully
+**/
+EFI_STATUS
+SaScriptMemWrite (
+  IN  UINT16                            TableName,
+  IN  EFI_BOOT_SCRIPT_WIDTH             Width,
+  IN  UINT64                            Address,
+  IN  UINTN                             Count,
+  IN  VOID                              *Buffer
+)
+{
+  return EFI_SUCCESS;
+}
+
+/**
+  Wrapper for boot script with opcode EFI_BOOT_SCRIPT_MEM_READ_WRITE_OPCODE
+
+  @param[in] TableName - Desired boot script table
+  @param[in] Width     - The width of the memory operations.
+  @param[in] Address   - The base address of the memory operations.
+  @param[in] Data      - A pointer to the data to be OR-ed.
+  @param[in] DataMask  - A pointer to the data mask to be AND-ed with the data read from the register.
+
+  @retval EFI_SUCCESS  - The operation was executed successfully
+**/
+EFI_STATUS
+SaScriptMemReadWrite (
+  IN  UINT16                            TableName,
+  IN  EFI_BOOT_SCRIPT_WIDTH             Width,
+  IN  UINT64                            Address,
+  IN  VOID                              *Data,
+  IN  VOID                              *DataMask
+)
+{
+  return EFI_SUCCESS;
+}
+
+/**
+  Wrapper for boot script for Polling one memory mapping register
+
+  @param[in] TableName - Desired boot script table
+  @param[in] Width     - The width of the memory operations.
+  @param[in] Address   - The base address of the memory operations.
+  @param[in] BitMask   - A pointer to the bit mask to be AND-ed with the data read from the register.
+  @param[in] BitValue  - A pointer to the data value after to be Masked.
+  @param[in] Duration  - Duration in microseconds of the stall.
+  @param[in] LoopTimes - The times of the register polling.
+
+  @retval EFI_SUCCESS - The operation was executed successfully
+**/
+EFI_STATUS
+SaScriptMemPoll (
+  IN  UINT16                            TableName,
+  IN  EFI_BOOT_SCRIPT_WIDTH             Width,
+  IN  UINT64                            Address,
+  IN  VOID                              *BitMask,
+  IN  VOID                              *BitValue,
+  IN  UINTN                             Duration,
+  IN  UINTN                             LoopTimes
+  )
+{
+  return EFI_SUCCESS;
+}
\ No newline at end of file
diff --git a/ReferenceCode/Chipset/SystemAgent/Library/SaPcieLib/Smm/SaPcieSmmLib.cif b/ReferenceCode/Chipset/SystemAgent/Library/SaPcieLib/Smm/SaPcieSmmLib.cif
new file mode 100644
index 0000000..9fa9ac2
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/Library/SaPcieLib/Smm/SaPcieSmmLib.cif
@@ -0,0 +1,11 @@
+<component>
+	name = "SaPcieSmmLib"
+	category = ModulePart
+	LocalRoot = "ReferenceCode\Chipset\SystemAgent\Library\SaPcieLib\Smm\"
+	RefName = "SaPcieSmmLib"
+[files]
+"SaPcieSmmLib.sdl"
+"SaPcieSmmLib.mak"
+"SaPcieSmmLib.c"
+"SaPcieSmmLib.inf"
+<endComponent>
diff --git a/ReferenceCode/Chipset/SystemAgent/Library/SaPcieLib/Smm/SaPcieSmmLib.inf b/ReferenceCode/Chipset/SystemAgent/Library/SaPcieLib/Smm/SaPcieSmmLib.inf
new file mode 100644
index 0000000..97c4c12
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/Library/SaPcieLib/Smm/SaPcieSmmLib.inf
@@ -0,0 +1,63 @@
+## @file
+#  Component description file for the SA PCIE library
+#
+#@copyright
+#  Copyright (c)  2012 Intel Corporation. All rights reserved
+#  This software and associated documentation (if any) is furnished
+#  under a license and may only be used or copied in accordance
+#  with the terms of the license. Except as permitted by such
+#  license, no part of this software or documentation may be
+#  reproduced, stored in a retrieval system, or transmitted in any
+#  form or by any means without the express written consent of
+#  Intel Corporation.
+#
+#  This file contains a 'Sample Driver' and is licensed as such
+#  under the terms of your license agreement with Intel or your
+#  vendor.  This file may be modified by the user, subject to
+#  the additional terms of the license agreement
+#
+
+[defines]
+BASE_NAME       =   SaPcieSmmLib
+COMPONENT_TYPE  =   LIBRARY
+
+[sources.common]
+  ../Common/SaPcieLib.h
+  ../Common/SaPcieLib.c
+  SaPcieSmmLib.c
+
+[includes.common]
+  .
+  $(EDK_SOURCE)/Foundation/Library/Pei/Include
+  $(EDK_SOURCE)/Foundation/Efi
+  $(EDK_SOURCE)/Foundation/Include
+  $(EDK_SOURCE)/Foundation/Efi/Include
+  $(EDK_SOURCE)/Foundation/Framework/Include
+  $(EFI_SOURCE)/$(PROJECT_PCH_ROOT)/Include
+  $(EFI_SOURCE)/$(PROJECT_PCH_ROOT)
+  $(EFI_SOURCE)/$(PROJECT_PCH_ROOT)/Include/Library
+  $(EFI_SOURCE)/$(PROJECT_SA_ROOT)/Library/SaPcieLib/Smm
+  $(EFI_SOURCE)/$(PROJECT_SA_ROOT)/Include
+  $(EFI_SOURCE)/$(PROJECT_SA_ROOT)
+  $(EFI_SOURCE)/$(PROJECT_CPU_ROOT)/Include/Library
+  $(EFI_SOURCE)/$(PROJECT_CPU_ROOT)/Include
+#
+# EDK II Glue Library utilizes some standard headers from EDK
+#
+  $(EFI_SOURCE)
+  $(EDK_SOURCE)/Foundation
+  $(EDK_SOURCE)/Foundation/Framework
+  $(EDK_SOURCE)/Foundation/Include/IndustryStandard
+  $(EDK_SOURCE)/Foundation/Core/Dxe
+  $(EDK_SOURCE)/Foundation/Include/Pei
+  $(EDK_SOURCE)/Foundation/Library/Dxe/Include
+  $(EDK_SOURCE)/Foundation/Library/EdkIIGlueLib/Include
+
+[libraries.common]
+  EdkIIGlueBasePciLibPciExpress
+
+[nmake.common]
+C_FLAGS = $(C_FLAGS)
+C_STD_INCLUDE=
+
+
diff --git a/ReferenceCode/Chipset/SystemAgent/Library/SaPcieLib/Smm/SaPcieSmmLib.mak b/ReferenceCode/Chipset/SystemAgent/Library/SaPcieLib/Smm/SaPcieSmmLib.mak
new file mode 100644
index 0000000..4d18c76
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/Library/SaPcieLib/Smm/SaPcieSmmLib.mak
@@ -0,0 +1,50 @@
+#*************************************************************************
+#*************************************************************************
+#**                                                                     **
+#**        (C)Copyright 1985-2011, American Megatrends, Inc.            **
+#**                                                                     **
+#**                       All Rights Reserved.                          **
+#**                                                                     **
+#**      5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093           **
+#**                                                                     **
+#**                       Phone: (770)-246-8600                         **
+#**                                                                     **
+#*************************************************************************
+#*************************************************************************
+
+#---------------------------------------------------------------------------
+#   Create SaPcieSmmLib Driver
+#---------------------------------------------------------------------------
+
+# MAK file for the ModulePart:SaPcieSmmLib
+EDK : SaPcieSmmLib
+
+SaPcieSmmLib : $(BUILD_DIR)\SaPcieSmmLib.mak SaPcieSmmLibBin
+
+$(BUILD_DIR)\SaPcieSmmLib.mak : $(SaPcieSmmLib_DIR)\$(@B).cif $(SaPcieSmmLib_DIR)\$(@B).mak $(BUILD_RULES)
+	$(CIF2MAK) $(SaPcieSmmLib_DIR)\$(@B).cif $(CIF2MAK_DEFAULTS)
+
+$(SaPcieSmmLib_LIB) : SaPcieSmmLib
+
+SaPcieSmmLib_DEFINES = \
+            $(CFLAGS) \
+    
+SaPcieSmmLibBin: $(SaPcieLib_LIB)
+	    $(MAKE) /$(MAKEFLAGS) $(EDK_DEFAULTS) \
+            /f $(BUILD_DIR)\SaPcieSmmLib.mak all \
+            "CFLAGS=$(SaPcieSmmLib_DEFINES)"\
+            TYPE=LIBRARY LIBRARIES= \
+            LIBRARY_NAME=$(SaPcieSmmLib_LIB)
+#*************************************************************************
+#*************************************************************************
+#**                                                                     **
+#**        (C)Copyright 1985-2011, American Megatrends, Inc.            **
+#**                                                                     **
+#**                       All Rights Reserved.                          **
+#**                                                                     **
+#**      5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093           **
+#**                                                                     **
+#**                       Phone: (770)-246-8600                         **
+#**                                                                     **
+#*************************************************************************
+#*************************************************************************
diff --git a/ReferenceCode/Chipset/SystemAgent/Library/SaPcieLib/Smm/SaPcieSmmLib.sdl b/ReferenceCode/Chipset/SystemAgent/Library/SaPcieLib/Smm/SaPcieSmmLib.sdl
new file mode 100644
index 0000000..5641512
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/Library/SaPcieLib/Smm/SaPcieSmmLib.sdl
@@ -0,0 +1,34 @@
+TOKEN
+        Name  = "SaPcieSmmLib_SUPPORT"
+        Value  = "1"
+        Help  = "Main switch to enable SaPcieSmmLib support in Project"
+        TokenType = Boolean
+        TargetEQU = Yes
+        TargetMAK = Yes
+        TargetH = Yes
+        Master = Yes
+	    Token = "SaPcieLib_SUPPORT" "=" "1"
+#	    Token = "SA_PCIE_ASPM_IN_SMM" "=" "1"
+End
+
+
+PATH
+        Name  = "SaPcieSmmLib_DIR"
+	Help  = "SaPcieSmmLib file source directory"
+End
+
+MODULE
+        File  = "SaPcieSmmLib.mak"
+        Help  = "Includes SaPcieSmmLib.mak to Project"
+End
+
+ELINK
+        Name  = "SaPcieSmmLib_LIB"
+        InvokeOrder = ReplaceParent
+End
+
+ELINK
+        Name  = "$(BUILD_DIR)\SaPcieSmmLib_Lib.lib"
+        Parent  = "SaPcieSmmLib_LIB"
+        InvokeOrder = AfterParent
+End
\ No newline at end of file
diff --git a/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/MemInfoHob.h b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/MemInfoHob.h
new file mode 100644
index 0000000..0ce1f90
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/MemInfoHob.h
@@ -0,0 +1,103 @@
+/** @file
+  This file contains definitions required for creation of
+  Memory Info hob.
+
+@copyright
+  Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement.
+**/
+
+///
+/// @todo: Delete #define's and use definitions from SaCommonDefitions.h
+///
+#ifndef _MEM_HOB_H_
+#define _MEM_HOB_H_
+#pragma pack (push, 1)
+
+#include "MrcGlobal.h"
+
+#define EFI_MEMORY_RESTORE_DATA_GUID \
+  {0x87f22dcb,0x7304,0x4105,0xbb,0x7c,0x31,0x71,0x43,0xcc,0xc2,0x3b }
+
+#define MAX_NODE        1
+#define MAX_CH          2
+#define MAX_DIMM        2
+
+#define DDR3_FREQ_AUTO  0
+#define DDR3_FREQ_800   1
+#define DDR3_FREQ_1000  2
+#define DDR3_FREQ_1067  3
+#define DDR3_FREQ_1200  4
+#define DDR3_FREQ_1333  5
+#define DDR3_FREQ_1400  6
+#define DDR3_FREQ_1600  7
+#define DDR3_FREQ_1800  8
+#define DDR3_FREQ_1867  9
+#define DDR3_FREQ_2000  10
+#define DDR3_FREQ_2133  11
+#define DDR3_FREQ_2200  12
+#define DDR3_FREQ_2400  13
+#define DDR3_FREQ_2600  14
+#define DDR3_FREQ_2667  15
+
+///
+/// Host reset states from MRC.
+///
+#define  WARM_BOOT        2
+
+#define MCPciD4F0RegBase  PCIEX_BASE_ADDRESS + (UINT32) (((PCIEX_LENGTH >> 20) - 1) << 20) + (UINT32) (4 << 15) + (UINT32) (0 << 12)
+#define MCPciD5F0RegBase  PCIEX_BASE_ADDRESS + (UINT32) (((PCIEX_LENGTH >> 20) - 1) << 20) + (UINT32) (5 << 15) + (UINT32) (0 << 12)
+
+#define R_MC_CHNL_RANK_PRESENT  0x7C
+#define   B_RANK0_PRS           BIT0
+#define   B_RANK1_PRS           BIT1
+#define   B_RANK2_PRS           BIT4
+#define   B_RANK3_PRS           BIT5
+
+#ifndef _PEI_HOB_H_
+#ifndef __HOB__H__
+typedef struct _EFI_HOB_GENERIC_HEADER {
+  UINT16  HobType;
+  UINT16  HobLength;
+  UINT32  Reserved;
+} EFI_HOB_GENERIC_HEADER;
+
+typedef struct _EFI_HOB_GUID_TYPE {
+  EFI_HOB_GENERIC_HEADER  Header;
+  EFI_GUID                Name;
+  ///
+  /// Guid specific data goes here
+  ///
+} EFI_HOB_GUID_TYPE;
+#endif
+#endif
+///
+/// HOB to save MRC Output data and Memory S3_RestoreData
+///
+#define MRC_HOB_SIZE_TOTAL  (63 * 1024)
+#if ((defined SSA_FLAG) || (defined MRC_DEBUG_PRINT))
+#define MRC_HOB_SIZE_BUFFER (MRC_HOB_SIZE_TOTAL - sizeof (EFI_HOB_GUID_TYPE) - sizeof (MrcParameters))
+#else
+#define MRC_HOB_SIZE_BUFFER (1)
+#endif
+typedef struct {
+  EFI_HOB_GUID_TYPE EfiHobGuidType;
+  MrcParameters     MrcData;
+  UINT8             Buffer[MRC_HOB_SIZE_BUFFER];
+} HOB_SAVE_MEMORY_DATA;
+
+#pragma pack (pop)
+#endif
\ No newline at end of file
diff --git a/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/MemoryInit.c b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/MemoryInit.c
new file mode 100644
index 0000000..2dbc444
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/MemoryInit.c
@@ -0,0 +1,2722 @@
+/** @file
+  Memory Initialization PEIM.
+
+@copyright
+  Copyright (c) 1999 - 2013 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement.
+**/
+
+#include "CpuIA32.h"
+#include "EdkIIGluePeim.h"
+#include "SaAccess.h"
+#include "MemInfoHob.h"
+#include "MemoryInit.h"
+#include "MrcDebugHook.h"
+#include "MrcOemDebugPrint.h"
+#include "MrcOemIo.h"
+#include "MrcOemPlatform.h"
+#include "MrcSaveRestore.h"
+#include "MrcSpdDriver.h"
+#include "McGdxcbar.h"
+#include "CpuRegs.h"
+#include "CpuPlatformLib.h"
+#include "MrcCommon.h"
+#include "TxtLibrary.h"
+#include "PttHciRegs.h"
+
+// The next extern is temporary, including MrcCommon.h causes compile problems.
+extern
+MrcFrequency
+MrcGetCurrentMemoryFrequency (
+  MrcParameters * const MrcData,
+  U32 * const             MemoryClock,
+  MrcClockRatio * const   Ratio,
+  MrcRefClkSelect * const RefClk
+  );
+
+//
+// Driver Dependent PPI Prototypes
+//
+#include EFI_PPI_DEPENDENCY (BaseMemoryTest)
+#include EFI_PPI_DEPENDENCY (Capsule)
+#include EFI_PPI_DEPENDENCY (PlatformMemoryRange)
+#include EFI_PPI_DEPENDENCY (PlatformMemorySize)
+#include EFI_PPI_DEPENDENCY (SaPlatformPolicy)
+#include EFI_PPI_DEPENDENCY (CpuPlatformPolicy)
+#include EFI_GUID_DEFINITION (TxtInfoHob)
+#include EFI_PPI_DEPENDENCY (Stall)
+#include EFI_PPI_DEPENDENCY (Variable)
+#include EFI_PPI_CONSUMER   (Wdt)
+
+//
+// Driver Consumed GUID
+//
+#include EFI_GUID_DEFINITION (AcpiVariable)
+#include EFI_GUID_DEFINITION (MemoryTypeInformation)
+#include EFI_GUID_DEFINITION (SmramMemoryReserve)
+//#ifdef MRC_DEBUG_PRINT
+//#include EFI_GUID_DEFINITION (GlobalVariable)
+//#include EFI_PPI_DEFINITION (DebugMask)
+//#endif // MRC_DEBUG_PRINT
+
+//
+// Driver PPI Definitions
+//
+#ifdef RAPID_START_FLAG
+#include EFI_PPI_DEFINITION (RapidStart)
+#include "RapidStartCommonLib.h"
+#include "RapidStartPeiLib.h"
+#include EFI_PPI_CONSUMER (PchReset)
+#endif // RAPID_START_FLAG
+#include EFI_PPI_DEFINITION (PchInit)
+#include EFI_PPI_DEFINITION (PchMeUma)
+#include "PchMeUma.h"
+#if 0//def MRC_DEBUG_PRINT
+#include "DebugMask.h"
+#endif
+
+#ifndef AMI_OVERRIDE_FOR_NOTIFY_MRC
+#define __HOB__H__
+#include <Ppi\NBPPI.h>
+#endif // AMI_OVERRIDE_FOR_NOTIFY_MRC
+
+//
+// Driver GUID Definitions
+//
+EFI_GUID  gMemRestoreDataGuid   = EFI_MEMORY_RESTORE_DATA_GUID;
+EFI_GUID  gPeiCapsulePpiGuid    = PEI_CAPSULE_PPI_GUID;
+EFI_GUID  gEfiAcpiVariableGuid  = EFI_ACPI_VARIABLE_GUID;
+#if 0//def MRC_DEBUG_PRINT
+EFI_GUID  gEfiGenericVariableGuid = EFI_GENERIC_VARIABLE_GUID;
+#endif
+
+
+#ifdef MRC_DEBUG_PRINT
+const UINT8 BootStringFc[]  = "BOOT_WITH_FULL_CONFIGURATION";
+const UINT8 BootStringMc[]  = "BOOT_WITH_MINIMAL_CONFIGURATION";
+const UINT8 BootStringNc[]  = "BOOT_ASSUMING_NO_CONFIGURATION_CHANGES";
+const UINT8 BootStringFcd[] = "BOOT_WITH_FULL_CONFIGURATION_PLUS_DIAGNOSTICS";
+const UINT8 BootStringDs[]  = "BOOT_WITH_DEFAULT_SETTINGS";
+const UINT8 BootStringS4[]  = "BOOT_ON_S4_RESUME";
+const UINT8 BootStringS5[]  = "BOOT_ON_S5_RESUME";
+const UINT8 BootStringS2[]  = "BOOT_ON_S2_RESUME";
+const UINT8 BootStringS3[]  = "BOOT_ON_S3_RESUME";
+const UINT8 BootStringFu[]  = "BOOT_ON_FLASH_UPDATE";
+const UINT8 BootStringRm[]  = "BOOT_IN_RECOVERY_MODE";
+const UINT8 BootStringRmm[] = "BOOT_IN_RECOVERY_MODE_MASK";
+const UINT8 BootStringSm[]  = "BOOT_SPECIAL_MASK";
+const UINT8 BootStringUnk[] = "BOOT_MODE_UNKNOWN";
+#endif
+
+#ifndef AMI_OVERRIDE_FOR_NOTIFY_MRC
+static EFI_PEI_PPI_DESCRIPTOR mAmiPeiBeforeMrcDesc[] = {
+    { (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST), \
+      &gAmiPeiBeforeMrcGuid, \
+      NULL }
+};
+
+static EFI_PEI_PPI_DESCRIPTOR mAmiPeiCompelteMrcDesc[] = {
+    { (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST), \
+      &gAmiPeiAfterMrcGuid, \
+      NULL }
+};
+
+static EFI_PEI_PPI_DESCRIPTOR mAmiPeiEndOfMrcDesc[] = {
+    { (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST), \
+      &gAmiPeiEndOfMemDetectGuid, \
+      NULL }
+};
+#endif // AMI_OVERRIDE_FOR_NOTIFY_MRC
+
+EFI_PEIM_ENTRY_POINT (PeimMemoryInit);
+
+/**
+  Main starting point for system memory initialization.
+    1. Get SysBootMode and MrcBootMode
+    2. Locate SaPlatformPolicy PPI
+    3. Locate S3DataPtr from SaPlatformPolicy.
+    4. SaveDataValid := TRUE if S3DataPtr is not NULL.
+    5. If SysBootMode is BOOT_ON_S3_RESUME and S3Data is not valid:
+    -> ASSERT.
+    6. If MrcBootMode is Warm boot, but S3 data is not valid :
+    -> change MrcBootMode to Cold boot.
+    7. If MrcBootMode is Cold boot:
+    -> Run MRC code
+    -> Save S3 Restore Data
+    Else
+    -> Run MRC_S3Resume
+    8. Run MRC_Done().
+    9. Install EFI memory HOBs.
+
+  @param[in] FfsHeader        - Not used.
+  @param[in] PeiServices      - General purpose services available to every PEIM.
+
+  @retval EFI_SUCCESS      - Memory initialization completed successfully.
+  @retval EFI_NOT_READY    - Cannot locate SA Platform Policy.
+  @retval EFI_NOT_FOUND    - No S3 data in S3 Boot Mode.
+  @retval EFI_DEVICE_ERROR - MemoryInit failed or IOSAV Memory test failed.
+**/
+EFI_STATUS
+PeimMemoryInit (
+  IN EFI_FFS_FILE_HEADER *FfsHeader,
+  IN EFI_PEI_SERVICES    **PeiServices
+  )
+{
+  PEI_READ_ONLY_VARIABLE_PPI  *VariableServices;
+  SA_PLATFORM_POLICY_PPI      *SaPlatformPolicyPpi;
+  HOB_SAVE_MEMORY_DATA        *Hob;
+  MrcParameters               *MrcData;
+  MrcInput                    *Inputs;
+  MrcOutput                   *Outputs;
+  SysSave                     *SaveSys;
+  MrcSave                     *Save;
+  MrcCpuModel                 CpuModel;
+  MrcCpuStepping              CpuStep;
+  UINT32                      CpuModelStep;
+  BOOLEAN                     CpuDetected;
+  MrcParameters               MrcGlobalData;
+  EFI_STATUS                  Status;
+  EFI_BOOT_MODE               SysBootMode;
+  MrcStatus                   MrcStatus;
+  MrcBootMode                 MrcBootMode;
+  MrcVersion                  Version;
+  BOOLEAN                     SaveDataValid;
+  UINT32                      Crc32;
+  UINT64                      SskpdValue;
+#ifdef MRC_DEBUG_PRINT
+  MrcDebug                    *Debug;
+  const UINT8                 *Str;
+#endif
+  PCH_ME_UMA_PPI              *PchMeUma;
+  UINT8                       InitStat;
+  UINT8                       ForceFullTraining;
+  UINT8                       OrigMrcBootMode;
+#ifdef RAPID_START_FLAG
+  PCH_RESET_PPI               *PchResetPpi;
+  RAPID_START_PPI             *RapidStartPpi;
+#endif
+  UINT8                       TotalDprSizeMB;
+  UINT32                      MemoryClock;
+  MrcClockRatio               Ratio;
+  MrcUpmPwrRetrainLimits      RetrainLimits[MRC_NUMBER_UPM_PWR_RETRAIN_MARGINS];
+
+  MrcData = &MrcGlobalData;
+  Inputs  = &MrcData->SysIn.Inputs;
+  Outputs = &MrcData->SysOut.Outputs;
+  ZeroMem (MrcData, sizeof (MrcParameters));
+  Outputs->UpmPwrRetrainLimits.Pointer = RetrainLimits;
+  MrcOemMemoryCpy (
+    (U8 *) RetrainLimits,
+    (U8 *) InitialLimits,
+    sizeof (MrcUpmPwrRetrainLimits) * MRC_NUMBER_UPM_PWR_RETRAIN_MARGINS
+    );
+
+  //;;## ...AMI_OVERRIDE... Notify BeforeMrc
+  // Install the NB Before Mrc Notify PPI
+  Status = (*PeiServices)->InstallPpi(PeiServices, &mAmiPeiBeforeMrcDesc[0]);
+  ASSERT_EFI_ERROR (Status);
+  //;;## ...AMI_OVERRIDE... Notify BeforeMrc end
+
+  //
+  // Obtain boot mode.
+  //
+  Status = (*PeiServices)->GetBootMode (PeiServices, &SysBootMode);
+  ASSERT_EFI_ERROR (Status);
+
+  if (SysBootMode != BOOT_ON_S3_RESUME) {
+    Status = MrcGetHobForDataStorage (PeiServices, &Hob, sizeof (HOB_SAVE_MEMORY_DATA));
+    ASSERT_EFI_ERROR (Status);
+  } else {
+    Hob = 0;
+  }
+
+#ifdef SSA_FLAG
+  Status = (**PeiServices).LocatePpi (PeiServices, &gSsaBiosCallBacksPpiGuid, 0, NULL, (VOID **) &Inputs->SsaCallbackPpi);
+  if (EFI_SUCCESS != Status) {
+    Inputs->SsaCallbackPpi = 0;
+  }
+  Inputs->Debug.Stream   = (U32) PeiServices;
+  Inputs->SsaHeapBase    = (U32) &Hob->MrcData;
+  Inputs->SsaHeapSize    = MRC_HOB_SIZE_TOTAL - sizeof (EFI_HOB_GUID_TYPE);
+  PEI_DEBUG (((void *) PeiServices, EFI_D_ERROR, "SsaCallbackPpi = %Xh\n", Inputs->SsaCallbackPpi));
+  PEI_DEBUG (((void *) PeiServices, EFI_D_ERROR, "SSA heap. Base = %Xh, Size = %d\n", Inputs->SsaHeapBase, Inputs->SsaHeapSize));
+#endif // SSA_FLAG
+
+  //
+  // Obtain platform policy settings.
+  //
+  Status = (**PeiServices).LocatePpi (PeiServices, &gSaPlatformPolicyPpiGuid, 0, NULL, (VOID **) &SaPlatformPolicyPpi);
+  ASSERT_EFI_ERROR (Status);
+
+  MrcOemDebugHook (MrcData, MRC_INITIALIZATION_START);
+#ifdef MRC_DEBUG_PRINT
+  Debug   = &Inputs->Debug;
+#endif
+
+  MRC_DEBUG_MSG_OPEN (
+    Debug,
+    (SaPlatformPolicyPpi->MemConfig->MrcTimeMeasure > 0) ? MSG_LEVEL_TIME : SaPlatformPolicyPpi->MemConfig->SerialDebug,
+    (U32) PeiServices,
+    (SysBootMode == BOOT_ON_S3_RESUME) ? 0 : (U32) &Hob->MrcData,
+    (SysBootMode == BOOT_ON_S3_RESUME) ? 0 : (MRC_HOB_SIZE_TOTAL - sizeof (EFI_HOB_GUID_TYPE))
+    );
+
+  InitStat = 0;
+  ForceFullTraining = 0;
+
+  MrcStatus = mrcSuccess;
+
+  //
+  // Obtain variable services.
+  //
+  Status = (*PeiServices)->LocatePpi (PeiServices, &gPeiReadOnlyVariablePpiGuid, 0, NULL, (VOID **) &VariableServices);
+  ASSERT_EFI_ERROR (Status);
+
+#ifndef TXT_SUPPORT_FLAG
+  //
+  // Unlock memory if it is necessary.
+  //
+  UnlockMemory (MrcData, PeiServices);
+#endif // TXT_SUPPORT_FLAG
+
+  //
+  // Get MRC BootMode
+  //
+  MrcBootMode = (SysBootMode == BOOT_ON_S3_RESUME) ? bmS3 : MrcGetBootMode ();
+
+#ifdef MRC_DEBUG_PRINT
+  if ((SysBootMode == BOOT_ON_S3_RESUME) && (bmCold == MrcGetBootMode ())) {
+    MRC_DEBUG_MSG (
+      Debug,
+      MSG_LEVEL_NOTE,
+      "SysBootMode = %Xh and MrcBootMode = %d - Check PCH SR bit\n",
+      SysBootMode,
+      MrcBootMode
+      );
+  }
+#endif // MRC_DEBUG_PRINT
+
+#ifdef RAPID_START_FLAG
+  //
+  // Locate RapidStart PPI
+  //
+  Status = (*PeiServices)->LocatePpi (PeiServices, &gRapidStartPpiGuid, 0, NULL, &RapidStartPpi);
+  ASSERT_EFI_ERROR (Status);
+#endif // RAPID_START_FLAG
+
+  MrcVersionGet (&Version);
+  MrcVersionPrint (MrcData, &Version);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\nSystem boot mode = %Xh\n", SysBootMode);
+#ifdef MRC_DEBUG_PRINT
+  switch (SysBootMode) {
+    case BOOT_WITH_FULL_CONFIGURATION:                  Str = BootStringFc;   break;
+    case BOOT_WITH_MINIMAL_CONFIGURATION:               Str = BootStringMc;   break;
+    case BOOT_ASSUMING_NO_CONFIGURATION_CHANGES:        Str = BootStringNc;   break;
+    case BOOT_WITH_FULL_CONFIGURATION_PLUS_DIAGNOSTICS: Str = BootStringFcd;  break;
+    case BOOT_WITH_DEFAULT_SETTINGS:                    Str = BootStringDs;   break;
+    case BOOT_ON_S4_RESUME:                             Str = BootStringS4;   break;
+    case BOOT_ON_S5_RESUME:                             Str = BootStringS5;   break;
+    case BOOT_ON_S2_RESUME:                             Str = BootStringS2;   break;
+    case BOOT_ON_S3_RESUME:                             Str = BootStringS3;   break;
+    case BOOT_ON_FLASH_UPDATE:                          Str = BootStringFu;   break;
+    case BOOT_IN_RECOVERY_MODE:                         Str = BootStringRm;   break;
+    case BOOT_IN_RECOVERY_MODE_MASK:                    Str = BootStringRmm;  break;
+    case BOOT_SPECIAL_MASK:                             Str = BootStringSm;   break;
+    default:                                            Str = BootStringUnk;  break;
+  }
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\nSystem boot mode = %s\n", Str);
+#endif //MRC_DEBUG_PRINT
+
+  //
+  // Locate and determine if memory configuration save data is valid.
+  //
+  SaveDataValid = FALSE;
+  if ((SaPlatformPolicyPpi->S3DataPtr != NULL) && (SysBootMode != BOOT_WITH_DEFAULT_SETTINGS)) {
+    SaveSys = (SysSave *) (SaPlatformPolicyPpi->S3DataPtr);
+    Save    = &SaveSys->Save;
+    Crc32 = MrcCalculateCrc32 ((U8 *) (&Save->Data), sizeof (MrcSaveData));
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Calc. crc = 0x%x, Header crc = 0x%x\n", Crc32, Save->Header.Crc);
+    MRC_DEBUG_MSG (
+      Debug,
+      MSG_LEVEL_NOTE,
+      "S3DataPtr = 0x%x - &MrcData = 0x%x - sizeof (MrcParameters) = 0x%x\n",
+      SaPlatformPolicyPpi->S3DataPtr,
+      &MrcData,
+      sizeof (MrcParameters)
+      );
+
+      if (Crc32 == Save->Header.Crc) {
+      MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Saved memory configuration data is valid\n");
+      ((*PeiServices)->CopyMem) ((VOID *) &MrcData->SysSave, (VOID *) SaveSys, sizeof (SysSave));
+      SaveDataValid = TRUE;
+    }
+  }
+
+  //
+  // We must have memory configuration save data in order to resume from S3.
+  //
+  if ((SysBootMode == BOOT_ON_S3_RESUME) && (!SaveDataValid)) {
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_ERROR, "Unable to resume from S3 without valid saved memory configuration data\n");
+    PEI_ASSERT (PeiServices, FALSE);
+    return EFI_NOT_FOUND;
+  }
+
+  //
+  // Locate PchMeUma PPI.
+  //
+  Status = (*PeiServices)->LocatePpi (PeiServices, &gPchMeUmaPpiGuid, 0, NULL, &PchMeUma);
+  ASSERT_EFI_ERROR (Status);
+
+  if (MrcBootMode != bmS3 && MrcBootMode != bmWarm) {
+    //
+    // Check CPU Replaced Status, if so a system non-power cycle reset will be required.
+    //
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Calling CpuReplacementCheck\n");
+    Status = PchMeUma->CpuReplacementCheck(PeiServices, FfsHeader, &ForceFullTraining);
+
+    if (ForceFullTraining == 0x1) {
+      SaveDataValid = FALSE;
+    }
+  }
+
+  // Keep track of the original MRC Boot mode before an alternate flow is determined below.
+  OrigMrcBootMode = MrcBootMode;
+
+  CpuModel     = GetCpuFamily();
+  CpuStep      = GetCpuStepping();
+  CpuModelStep = CpuModel | CpuStep;
+  CpuDetected  = (MrcSetCpuInformation (MrcData, CpuModel, CpuStep) == mrcSuccess) ? TRUE : FALSE;
+
+  if (!CpuDetected) {
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_ERROR, "ERROR: CPU Family/Model/Step %Xh is not supported:\n", CpuModelStep);
+    ASSERT_EFI_ERROR (EFI_DEVICE_ERROR);
+  }
+
+  //
+  // MrcBootMode can ONLY be bmCold, bmWarm or bmS3 at this point.
+  //
+  switch (MrcBootMode) {
+    case bmCold:
+      // Advance the MRC boot mode to fast boot if the following condition is met.
+      if ((SaveDataValid == TRUE) &&
+        (SaPlatformPolicyPpi->MemConfig->MrcFastBoot > 0) &&
+        (ColdBootRequired (MrcData, SaPlatformPolicyPpi)) == FALSE) {
+          MrcBootMode = bmFast;
+          MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Fast boot is possible, so forcing it\n");
+      }
+      else {
+        MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Cold boot\n");
+        SaveDataValid = FALSE;
+      }
+      break;
+
+    case bmWarm:
+    case bmS3:
+      if (SaveDataValid == FALSE) {
+        MRC_DEBUG_MSG (Debug, MSG_LEVEL_WARNING, "Saved memory configuration data is not valid, forcing a cold boot\n");
+        MrcBootMode = bmCold;
+        break;
+      } else {
+        if (ColdBootRequired (MrcData, SaPlatformPolicyPpi) == TRUE) {
+          MRC_DEBUG_MSG (
+            Debug,
+            MSG_LEVEL_WARNING,
+            "Platform settings or configuration have changed, forcing a cold boot\n"
+            );
+          MrcBootMode = bmCold;
+          SaveDataValid = FALSE;
+          break;
+        }
+        //
+        // Check SSKPD register to determine if Warm Reset occured before MRC was reached during a cold boot.
+        // If so, we need to force the cold boot path.
+        //
+        MrcOemMmioRead64 (PCU_CR_SSKPD_PCU_REG, &SskpdValue, SaPlatformPolicyPpi->PlatformData->MchBar);
+        if ((SskpdValue == 0) && (MrcBootMode == bmWarm)) {
+          MRC_DEBUG_MSG (
+            Debug,
+            MSG_LEVEL_WARNING,
+            "Reset occured in the cold boot path before reaching MRC.  Forcing Cold Boot\n"
+            );
+          MrcBootMode = bmCold;
+          SaveDataValid = FALSE;
+          break;
+        }
+      }
+      MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%s\n", (MrcBootMode == bmS3) ? "Resume from S3" : "Warm reset");
+      break;
+
+    default:
+      MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Cold boot\n");
+      MrcBootMode = bmCold;
+      SaveDataValid = FALSE;
+      break;
+  }
+
+  //
+  // Clear MrcSave if not valid saved data. We don't want to end up with Ghost DIMMs
+  //
+  if (SaveDataValid == FALSE) {
+    ZeroMem (&MrcData->SysSave.Save, sizeof (MrcSave));
+  }
+
+#ifdef MRC_DEBUG_PRINT
+  ((*PeiServices)->CopyMem) ((VOID *) &MrcData->SysIn.Inputs.Debug, Debug, sizeof (MrcDebug));
+  Debug = &Inputs->Debug;
+#endif // MRC_DEBUG_PRINT
+
+  //
+  //Calculate Total DPR Size
+  //
+  CalculateTotalDprMemorySize (PeiServices, &TotalDprSizeMB);
+
+  if(TotalDprSizeMB != 0){
+    Inputs->DprSize = (U32) TotalDprSizeMB;
+  }
+
+  //
+  // Set up the MRC input data structure.
+  //
+  Inputs->BootMode = MrcSetupMrcData (SysBootMode, MrcBootMode, Inputs, PeiServices, SaPlatformPolicyPpi);
+
+  //
+  // Initialize MeStolenSize to 0 before we retrieving from ME FW.
+  //
+  Inputs->MeStolenSize = 0;
+
+#ifdef RAPID_START_FLAG
+  if ((SysBootMode != BOOT_ON_S3_RESUME) && (RapidStartPpi->GetMode (RapidStartPpi) == RapidStartExit)) {
+    //
+    // Need to erase whole memory for Rapid Start Resume
+    //
+    Inputs->OemCleanMemory = TRUE;
+  }
+#endif  // RAPID_START_FLAG
+
+      //
+      // ME Stolen Size in MB units
+      //
+      DEBUG ((EFI_D_ERROR, "Calling MeSendUmaSize\n"));
+      Inputs->MeStolenSize = PchMeUma->MeSendUmaSize (PeiServices, FfsHeader);
+      MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "ME UMA size = %u MB\n", Inputs->MeStolenSize);
+
+  do {
+    if (Inputs->BootMode == bmCold) {
+      //
+      // Clear DRAM Init Bit if we are doing a cold boot, to prevent hang if a warm reset occurs in the training flow
+      // where an old memory config is saved.
+      //
+      MrcResetDISB ();
+    }
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "MRC Start Memory Configuration\n");
+    MrcStatus = MrcStartMemoryConfiguration (MrcData);
+
+    switch (MrcStatus) {
+      case mrcSuccess:
+        break;
+
+      case mrcRetrain:
+        MRC_DEBUG_MSG (Debug, MSG_LEVEL_ERROR, "Rerunning training with higher UPM/PWR limits!\n");
+          ZeroMem (Outputs, sizeof (MrcOutput));
+          Outputs->UpmPwrRetrainLimits.Pointer = RetrainLimits;
+          Inputs->Iteration++;
+        break;
+
+      case mrcFrequencyError:
+        MrcGetCurrentMemoryFrequency (MrcData, &MemoryClock, &Ratio, NULL);
+        if (Ratio >= Outputs->Ratio) {
+          MRC_DEBUG_MSG (Debug, MSG_LEVEL_ERROR, "Memory initialization has failed\n");
+          //
+          // Get lower byte and set the error bit
+          //
+#ifndef AMI_OVERRIDE_FOR_MRC_ERROR_REPORT
+        MrcOemDebugHook (MrcData, MrcOemInPort8 (0x80) | MRC_FAILURE_INDICATION);
+#else
+        MrcOemOutPort8 (0x80, MrcOemInPort8 (0x80) | MRC_FAILURE_INDICATION);
+#endif
+          ASSERT_EFI_ERROR (EFI_DEVICE_ERROR);
+          return EFI_DEVICE_ERROR;
+        } else {
+          // Restart memory configuration, using the lower frequency.
+          MrcStatus = mrcColdBootRequired;
+        }
+        // no break;
+
+      case mrcColdBootRequired:
+        if (Inputs->BootMode == bmFast) {
+          // At this point, input structure has limited data.
+          // We need to initialize the input structure for the cold boot.
+          Inputs->BootMode = MrcSetupMrcData (SysBootMode, bmCold, Inputs, PeiServices, SaPlatformPolicyPpi);
+        } else {
+          Inputs->BootMode = bmCold;
+        }
+        break;
+
+      case mrcDimmNotExist:
+        //
+        // Set memory init status = 0x1 and send DRAM Init Done to ME FW,
+        // indicating that no memory exists in the system.
+        //
+        InitStat = 0x1;
+        Status = PchMeUma->MeConfigDidReg (PeiServices, FfsHeader, MrcBootMode, InitStat, Outputs->MemoryMapData.FtpmStolenBase, Inputs->MeStolenSize);
+        MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "FtpmStolenBase = 0x%08X \n", Outputs->MemoryMapData.FtpmStolenBase);
+        MrcOemDebugHook (MrcData, MRC_NO_MEMORY_DETECTED);
+        MRC_DEBUG_MSG (Debug, MSG_LEVEL_ERROR, "There are no DIMMs present in the system\n");
+        //
+        //Indicate to the caller that memory has not been detected.
+        //
+        (*PeiServices)->PeiReportStatusCode (
+          PeiServices,
+          EFI_ERROR_CODE,
+          EFI_COMPUTING_UNIT_MEMORY | EFI_CU_MEMORY_EC_NONE_DETECTED,
+          0,
+          NULL,
+          NULL
+          );
+        // no break;
+
+      default:
+        MRC_DEBUG_MSG (Debug, MSG_LEVEL_ERROR, "Memory initialization has failed\n");
+        //
+        // Get lower byte and set the error bit
+        //
+#ifndef AMI_OVERRIDE_FOR_MRC_ERROR_REPORT
+        MrcOemDebugHook (MrcData, MrcOemInPort8 (0x80) | MRC_FAILURE_INDICATION);
+#else
+        MrcOemOutPort8 (0x80, MrcOemInPort8 (0x80) | MRC_FAILURE_INDICATION);
+#endif
+        ASSERT_EFI_ERROR (EFI_DEVICE_ERROR);
+        return EFI_DEVICE_ERROR;
+    }
+  } while ((MrcStatus == mrcColdBootRequired) || (MrcStatus == mrcRetrain));
+
+  //
+  // Intel Silicon View Technology (ISVT) IO Reading port 0x84 with AH = 1 for End of MRC
+  //
+#if defined __GNUC__  // GCC compiler
+  __asm__ __volatile__ (
+    "\n\t mov $0x100, %eax"
+    "\n\t in $0x84, %al"
+    );
+#else //MSFT compiler
+  ASM {
+    mov EAX, 100h
+    in  AL, 84h
+  }
+#endif
+
+  //
+  // Configure "ME DRAM Init Done Register"
+  //
+  //
+  // ME UMA Size outside of a 0MB-32MB range is not defined or if BDF 0:22:0 is not present, exit.
+  //
+#ifdef RAPID_START_FLAG
+  //
+  // Check wake conditions to determine if a Rapid Start transition is to be performed
+  // and set the RapidStart flag in DID.
+  //
+  if (RapidStartPpi->GetMode (RapidStartPpi) != RapidStartNone) {
+    InitStat |= 0x80;
+  }
+#endif  // RAPID_START_FLAG
+
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Check for Memory Retrain on warm reset -- MrcBootMode=0x%02X OrigBootMode=0x%02X\n", MrcBootMode, OrigMrcBootMode);
+  // On warm reset if memory coherency was not maintained (forced Cold Reset flow), set the DID message
+  //  to indicate that memory was not preserved across reset, so that ME will reload the FW from NV memory.
+  if (bmWarm == OrigMrcBootMode && bmCold == MrcBootMode) {
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Memory retrain occurred during warm reset.  Force ME FW reload.\n");
+    // Set the flag to tell FW that memory was not maintained InitStat bits 3:0 = (3).
+    InitStat = (InitStat & 0xF0) | 0x3;
+  }
+
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "ME UMA Size requested: %d MB\n", Inputs->MeStolenSize);
+  if ((Inputs->MeStolenSize > 0x20) || (PchD22PciCfg32 (0x10) == 0xffffffff)) {
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_ERROR, "Invalid ME UMA Size requested.\n");
+  } else {
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Calling MeConfigDidReg\n");
+    Status = PchMeUma->MeConfigDidReg (PeiServices, FfsHeader, MrcBootMode, InitStat, Outputs->MemoryMapData.FtpmStolenBase,Inputs->MeStolenSize);
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "MeDramInitDone Complete.\n");
+  }
+
+  //
+  // SATA must be initialized before Rapid Start transition.
+  //
+  //remove for PCH RC updated to V44, the code would be elimated if SA/MRC sync to V44 as well
+  //  Status = PchInitPpi->SataInit (PeiServices);
+  //  ASSERT_PEI_ERROR (PeiServices, Status);
+
+#ifdef RAPID_START_FLAG
+  //
+  // Perform Rapid Start transition if necessary (BootMode mode may change here!)
+  // Rapid Start requires MRC Fast boot to be enabled for best performance.
+  // In Rapid Start Resume flow if MRC boot mode is not bmFast that means memory
+  // configuration has changed and Rapid Start resume should be aborted.
+  //
+  if ((SaPlatformPolicyPpi->MemConfig->MrcFastBoot) && (RapidStartPpi->GetMode (RapidStartPpi) == RapidStartExit) && (Inputs->BootMode != bmFast)) {
+    DEBUG ((EFI_D_ERROR, "Memory Configuration changed! Rapid Start Resume is aborted!\n"));
+    RapidStartAfterTransition (PeiServices, RapidStartExit, EFI_MEDIA_CHANGED, 0);
+    Status = (*PeiServices)->LocatePpi (
+                              PeiServices,
+                              &gPchResetPpiGuid,
+                              0,
+                              NULL,
+                              &PchResetPpi
+                              );
+    ASSERT_EFI_ERROR (Status);
+    PchResetPpi->Reset (PchResetPpi, PowerCycleReset);
+  } else {
+    RapidStartPpi->TransitionEntryPoint (RapidStartPpi, &SysBootMode);
+  }
+#endif // RAPID_START_FLAG
+
+#ifndef AMI_OVERRIDE_FOR_NOTIFY_MRC
+  // Install the NB End of Mrc Notify PPI
+  Status = (*PeiServices)->InstallPpi(PeiServices, &mAmiPeiCompelteMrcDesc[0]);
+  ASSERT_EFI_ERROR (Status);
+  DEBUG ((EFI_D_ERROR, "Install Complete MRC Ppi.\n"));
+#endif // AMI_OVERRIDE_FOR_NOTIFY_MRC
+#ifndef AMI_OVERRIDE_FOR_EIP102852
+  Status = (*PeiServices)->GetBootMode( PeiServices, &SysBootMode );
+#endif // AMI_OVERRIDE_FOR_EIP102852
+
+  //
+  // Install EFI memory HOBs
+  //
+  if (SysBootMode == BOOT_ON_S3_RESUME) {
+    Status = InstallS3Memory (Inputs, PeiServices, VariableServices);
+    ASSERT_EFI_ERROR (Status);
+  } else {
+    if ((MrcBootMode == bmCold) || (MrcBootMode == bmFast)) {
+      //
+      // Perform simple memory test.
+      //
+      if (mrcFail == BasicMemoryTest (Inputs)) {
+        MrcOemDebugHook (MrcData, MRC_MEM_INIT_DONE_WITH_ERRORS);
+        ASSERT_EFI_ERROR (EFI_DEVICE_ERROR);
+        return EFI_DEVICE_ERROR;
+      }
+    }
+    MrcData->SaveSize = sizeof (MrcSave);
+#ifdef MRC_DEBUG_PRINT
+    Debug->Current    = 0;
+#endif // MRC_DEBUG_PRINT
+    ((*PeiServices)->CopyMem) ((VOID *) &Hob->MrcData, MrcData, sizeof (MrcParameters));
+    ZeroMem ((VOID *) &Hob->Buffer, MRC_HOB_SIZE_BUFFER);
+
+    Status = InstallEfiMemory (Inputs, PeiServices, SysBootMode);
+    ASSERT_EFI_ERROR (Status);
+  }
+
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "MemoryInit Complete.\n");
+  MrcOemDebugHook (MrcData, MRC_MEM_INIT_DONE);
+
+#ifndef AMI_OVERRIDE_FOR_NOTIFY_MRC
+  // Install the NB End of Mrc Notify PPI
+  Status = (*PeiServices)->InstallPpi(PeiServices, &mAmiPeiEndOfMrcDesc[0]);
+  ASSERT_EFI_ERROR (Status);
+#endif // AMI_OVERRIDE_FOR_NOTIFY_MRC
+
+  return Status;
+}
+
+/**
+  This function installs memory for all paths except S3 resume.
+
+  @param[in] Inputs      - MRC input structure.
+  @param[in] PeiServices - PEI Services table.
+  @param[in] SysBootMode - The specific boot path that is being followed.
+
+  @retval EFI_SUCCESS          The function completed successfully.
+  @retval EFI_OUT_OF_RESOURCES Out of Resources.
+**/
+EFI_STATUS
+InstallEfiMemory (
+  IN const MrcInput *const Inputs,
+  IN EFI_PEI_SERVICES      **PeiServices,
+  IN EFI_BOOT_MODE         SysBootMode
+  )
+{
+  EFI_STATUS                            Status;
+  UINT8                                 Index;
+  UINT8                                 NumRanges;
+  UINT8                                 SmramIndex;
+  UINT8                                 SmramRanges;
+  UINT64                                PeiMemoryLength;
+  UINT64                                RangeLength;
+  UINTN                                 BufferSize;
+  UINTN                                 CapsuleBufferLength;
+  UINTN                                 PeiMemoryIndex;
+  UINTN                                 RequiredMemSize;
+  VOID                                  *CapsuleBuffer;
+  EFI_PEI_HOB_POINTERS                  Hob;
+  EFI_PHYSICAL_ADDRESS                  PeiMemoryBaseAddress;
+  EFI_PHYSICAL_ADDRESS                  TopUseableMemAddr;
+  EFI_PHYSICAL_ADDRESS                  TopUseableMemSize;
+  EFI_PHYSICAL_ADDRESS                  Tom;
+  PEI_MEMORY_TEST_OP                    MemoryTestOp;
+  PEI_BASE_MEMORY_TEST_PPI              *BaseMemoryTestPpi;
+  PEI_CAPSULE_PPI                       *Capsule;
+  PEI_PLATFORM_MEMORY_SIZE_PPI          *MemSize;
+  EFI_SMRAM_HOB_DESCRIPTOR_BLOCK        *SmramHobDescriptorBlock;
+  EFI_SMRAM_DESCRIPTOR                  *SmramDescriptor;
+  PEI_DUAL_CHANNEL_DDR_MEMORY_MAP_RANGE MemoryMap[MAX_RANGES];
+  EFI_PHYSICAL_ADDRESS                  BadMemoryAddress;
+  EFI_RESOURCE_TYPE                     ResourceType;
+  EFI_RESOURCE_ATTRIBUTE_TYPE           ResourceAttribute;
+  const MrcDebug                        *Debug;
+
+  Debug = &Inputs->Debug;
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Install EFI memory.\n");
+
+  //
+  // Get the Memory Map
+  //
+  NumRanges = MAX_RANGES;
+  ZeroMem (MemoryMap, sizeof (PEI_DUAL_CHANNEL_DDR_MEMORY_MAP_RANGE) * NumRanges);
+  Status = GetMemoryMap (PeiServices, (PEI_DUAL_CHANNEL_DDR_MEMORY_MAP_RANGE *) MemoryMap, &NumRanges);
+  ASSERT_EFI_ERROR (Status);
+
+  //
+  // Find the highest memory range in processor native address space to give to
+  // PEI. Then take the top.
+  // If this algorithm changes, then we need to fix the capsule memory
+  // selection algorithm below.
+  //
+  PeiMemoryBaseAddress = 0;
+
+  //
+  // Query the platform for the minimum memory size.
+  //
+  Status = (*PeiServices)->LocatePpi (PeiServices, &gPeiPlatformMemorySizePpiGuid, 0, NULL, (VOID **) &MemSize);
+  ASSERT_EFI_ERROR (Status);
+
+  Status = MemSize->GetPlatformMemorySize (PeiServices, MemSize, &PeiMemoryLength);
+  ASSERT_EFI_ERROR (Status);
+
+  //
+  // Get required memory size for ACPI use. This helps to put ACPI memory on the top.
+  //
+  RequiredMemSize = 0;
+  RetrieveRequiredMemorySize (PeiServices, &RequiredMemSize);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Required memory size = %Xh (%u) bytes\n", RequiredMemSize, RequiredMemSize);
+
+  PeiMemoryIndex = 0;
+  for (Index = 0; Index < NumRanges; Index++) {
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Found %016Xh bytes at ", MemoryMap[Index].RangeLength);
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%016Xh\n", MemoryMap[Index].PhysicalAddress);
+    if ((MemoryMap[Index].Type == DualChannelDdrMainMemory) &&
+      (MemoryMap[Index].PhysicalAddress + MemoryMap[Index].RangeLength < EFI_MAX_ADDRESS) &&
+      (MemoryMap[Index].PhysicalAddress >= PeiMemoryBaseAddress) &&
+      (MemoryMap[Index].RangeLength >= PeiMemoryLength)) {
+        PeiMemoryBaseAddress = MemoryMap[Index].PhysicalAddress + MemoryMap[Index].RangeLength - PeiMemoryLength;
+        PeiMemoryIndex       = Index;
+    }
+  }
+
+  //
+  // Test only the PEI memory if necessary. Some platforms do not require the
+  // Base Memory PEIM to be present.
+  //
+  Status = (*PeiServices)->LocatePpi (PeiServices, &gPeiBaseMemoryTestPpiGuid, 0, NULL, (VOID **) &BaseMemoryTestPpi);
+
+  switch (SysBootMode) {
+
+  case BOOT_WITH_FULL_CONFIGURATION:
+    MemoryTestOp = Quick;
+    break;
+
+  case BOOT_WITH_FULL_CONFIGURATION_PLUS_DIAGNOSTICS:
+    MemoryTestOp = Extensive;
+    break;
+
+  default:
+    MemoryTestOp = Ignore;
+    break;
+  }
+
+  (*PeiServices)->PeiReportStatusCode (
+    PeiServices,
+    EFI_PROGRESS_CODE,                                  // Type
+    EFI_COMPUTING_UNIT_MEMORY | EFI_CU_MEMORY_PC_TEST,  // Value
+    0,    // Instance
+    NULL, // *CallerId OPTIONAL
+    NULL  // *Data OPTIONAL
+    );
+
+  Status = BaseMemoryTestPpi->BaseMemoryTest (
+    PeiServices,
+    BaseMemoryTestPpi,
+    PeiMemoryBaseAddress,
+    PeiMemoryLength,
+    MemoryTestOp,
+    &BadMemoryAddress
+    );
+  if (EFI_ERROR (Status)) {
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_ERROR, "Memory test failure at %lXh.\n", BadMemoryAddress);
+  }
+
+  ASSERT_EFI_ERROR (Status);
+
+  Capsule             = NULL;
+  CapsuleBuffer       = NULL;
+  CapsuleBufferLength = 0;
+
+  if (SysBootMode == BOOT_ON_FLASH_UPDATE) {
+    Status = (*PeiServices)->LocatePpi (PeiServices, &gPeiCapsulePpiGuid, 0, NULL, (VOID **) &Capsule);
+#ifdef AMI_OVERRIDE_FOR_EIP102852
+    ASSERT_EFI_ERROR (Status);
+#endif // AMI_OVERRIDE_FOR_EIP102852
+
+    if (Status == EFI_SUCCESS) {
+      //
+      // Find the largest memory range excluding that given to PEI.
+      //
+      for (Index = 0; Index < NumRanges; Index++) {
+        if ((MemoryMap[Index].Type == DualChannelDdrMainMemory) &&
+          (MemoryMap[Index].PhysicalAddress + MemoryMap[Index].RangeLength < EFI_MAX_ADDRESS)) {
+          if (Index != PeiMemoryIndex) {
+            if (MemoryMap[Index].RangeLength > CapsuleBufferLength) {
+              CapsuleBuffer       = (VOID *) ((UINTN) MemoryMap[Index].PhysicalAddress);
+              CapsuleBufferLength = (UINTN) MemoryMap[Index].RangeLength;
+            }
+          } else {
+            if ((MemoryMap[Index].RangeLength - PeiMemoryLength) >= CapsuleBufferLength) {
+              CapsuleBuffer       = (VOID *) ((UINTN) MemoryMap[Index].PhysicalAddress);
+              CapsuleBufferLength = (UINTN) (MemoryMap[Index].RangeLength - PeiMemoryLength);
+            }
+          }
+        }
+      }
+      //
+      // Call the Capsule PPI Coalesce function to coalesce the capsule data.
+      //
+      Status = Capsule->Coalesce (PeiServices, &CapsuleBuffer, &CapsuleBufferLength);
+    }
+    //
+    // If it failed, then NULL out our capsule PPI pointer so that the capsule
+    // HOB does not get created below.
+    //
+    if (Status != EFI_SUCCESS) {
+      Capsule = NULL;
+    }
+  }
+  //
+  // Carve out the top memory reserved for ACPI.
+  //
+  Status = (*PeiServices)->InstallPeiMemory (PeiServices, PeiMemoryBaseAddress, PeiMemoryLength - RequiredMemSize);
+  ASSERT_EFI_ERROR (Status);
+
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Building RESOURCE_SYSTEM_MEMORY Hob: \n");
+  DEBUG ((EFI_D_ERROR, "PeiMemoryBaseAddress = %lXh, PeiMemoryLength = %lXh\n", PeiMemoryBaseAddress, PeiMemoryLength));
+
+  BuildResourceDescriptorHob (
+    EFI_RESOURCE_SYSTEM_MEMORY,
+    (
+    EFI_RESOURCE_ATTRIBUTE_PRESENT |
+    EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
+    EFI_RESOURCE_ATTRIBUTE_TESTED |
+    EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
+    EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
+    EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
+    EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE
+    ),
+    PeiMemoryBaseAddress,
+    PeiMemoryLength
+    );
+
+  //
+  // Install physical memory descriptor hobs for each memory range.
+  //
+  SmramRanges = 0;
+  for (Index = 0; Index < NumRanges; Index++) {
+    if (MemoryMap[Index].Type == DualChannelDdrMainMemory) {
+      if (Index == PeiMemoryIndex) {
+        //
+        // This is a partially tested Main Memory range, give it to EFI
+        //
+        RangeLength = MemoryMap[Index].RangeLength - PeiMemoryLength;
+      } else {
+        //
+        // This is an untested Main Memory range, give it to EFI.
+        //
+        RangeLength = MemoryMap[Index].RangeLength;
+      }
+      BuildResourceDescriptorHob (
+        EFI_RESOURCE_SYSTEM_MEMORY,
+        (
+        EFI_RESOURCE_ATTRIBUTE_PRESENT |
+        EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
+        //
+        // RC Override: mark <4G available memory as tested to give DXE enough memory space, so that default
+        // memory allocations won't occupy the bins for specific memory types.
+        //
+        EFI_RESOURCE_ATTRIBUTE_TESTED |
+        EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
+        EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
+        EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
+        EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE
+        ),
+        MemoryMap[Index].PhysicalAddress,
+        RangeLength
+        );
+
+      //
+      // Test this memory range
+      //
+      Status = BaseMemoryTestPpi->BaseMemoryTest (
+        PeiServices,
+        BaseMemoryTestPpi,
+        MemoryMap[Index].PhysicalAddress,
+        RangeLength,
+        MemoryTestOp,
+        &BadMemoryAddress
+        );
+      ASSERT_EFI_ERROR (Status);
+    } else {
+      if ((
+          (MemoryMap[Index].Type == DualChannelDdrSmramCacheable) ||
+          (MemoryMap[Index].Type == DualChannelDdrSmramNonCacheable)
+          ) &&
+          (MemoryMap[Index].PhysicalAddress != MC_ABSEG_HSEG_PHYSICAL_START)) {
+        //
+        // Only count and report TSEG.
+        //
+        SmramRanges++;
+      }
+      //
+      // Make sure non-system memory is marked as reserved.
+      //
+      BuildResourceDescriptorHob (
+        EFI_RESOURCE_MEMORY_RESERVED,     // MemoryType,
+//        0,                                // MemoryAttribute
+        (MemoryMap[Index].Type == DualChannelDdrGraphicsMemoryNonCacheable)? EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE : 0,
+        MemoryMap[Index].PhysicalAddress, // MemoryBegin
+        MemoryMap[Index].RangeLength      // MemoryLength
+        );
+    }
+  }
+
+  BufferSize = sizeof (EFI_SMRAM_HOB_DESCRIPTOR_BLOCK);
+  if (SmramRanges > 0) {
+    BufferSize += ((SmramRanges - 1) * sizeof (EFI_SMRAM_DESCRIPTOR));
+  }
+
+  Hob.Raw = BuildGuidHob (&gEfiSmmPeiSmramMemoryReserve, BufferSize);
+  if (Hob.Raw == NULL) {
+    return EFI_OUT_OF_RESOURCES;
+  }
+
+  SmramHobDescriptorBlock = (void *) (Hob.Raw);
+  SmramHobDescriptorBlock->NumberOfSmmReservedRegions = SmramRanges;
+
+  SmramIndex = 0;
+  for (Index = 0; Index < NumRanges; Index++) {
+    if ((
+        (MemoryMap[Index].Type == DualChannelDdrSmramCacheable) ||
+        (MemoryMap[Index].Type == DualChannelDdrSmramNonCacheable)
+        ) &&
+        (MemoryMap[Index].PhysicalAddress != MC_ABSEG_HSEG_PHYSICAL_START)) {
+      //
+      // This is an SMRAM range (not reporting AB_SEG or H_SEG), create an SMRAM descriptor.
+      //
+      SmramDescriptor = &SmramHobDescriptorBlock->Descriptor[SmramIndex];
+      SmramDescriptor->PhysicalStart = MemoryMap[Index].PhysicalAddress;
+      SmramDescriptor->CpuStart      = MemoryMap[Index].CpuAddress;
+
+      //
+      // RangeLength includes alignment adjustment.
+      //
+      if (SmramDescriptor->PhysicalStart < 0x100000) {
+        SmramDescriptor->PhysicalSize  = MemoryMap[Index].RangeLength;
+      } else {
+        SmramDescriptor->PhysicalSize  = (Inputs->TsegSize - Inputs->IedSize )* 0x100000;
+      }
+      MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "TSeg base is %Xh\n", SmramDescriptor->PhysicalStart);
+      MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "TSeg SMRAM size is %Xh\n", SmramDescriptor->PhysicalSize);
+
+
+      if (MemoryMap[Index].Type == DualChannelDdrSmramCacheable) {
+        SmramDescriptor->RegionState = EFI_SMRAM_CLOSED | EFI_CACHEABLE;
+      } else {
+        SmramDescriptor->RegionState = EFI_SMRAM_CLOSED;
+      }
+      SmramIndex++;
+    }
+  }
+  //
+  // Get the current "Top of Upper Usable Memory" address from TOUUD.
+  // If TOUUD > 4G, it means memory is re-mapped.
+  //
+  TopUseableMemSize = McD0PciCfg64 (R_SA_TOUUD) & B_SA_TOUUD_TOUUD_MASK;
+  TopUseableMemAddr = MEM_EQU_4GB;
+  Tom = McD0PciCfg64 (R_SA_TOM) & B_SA_TOM_TOM_MASK;
+  
+  if (TopUseableMemSize > MEM_EQU_4GB) {
+    //
+    // This is above 4G memory address, give it to EFI.
+    // If memory hob length is above 4G length, cut and separate it.
+    //
+    while ((TopUseableMemSize - MEM_EQU_4GB) > MEM_EQU_4GB) {
+      PEI_DEBUG ((PeiServices, EFI_D_ERROR, "Found 0x100000000 bytes at 0x%016lX\n", TopUseableMemAddr));
+      
+      if (Inputs->MemoryTrace && (TopUseableMemAddr + MEM_EQU_4GB > RShiftU64 (Tom, 1))) {
+        //
+        // Mark memory above 4GB as reserved if it's used for Memory Trace
+        //
+        ResourceType      = EFI_RESOURCE_MEMORY_RESERVED;
+        ResourceAttribute = 0;
+      } else {
+        ResourceType      = EFI_RESOURCE_SYSTEM_MEMORY;
+        ResourceAttribute = EFI_RESOURCE_ATTRIBUTE_PRESENT |
+                            EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
+                            EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
+                            EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
+                            EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
+                            EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE;
+      }
+      BuildResourceDescriptorHob (
+        ResourceType,       // MemoryType,
+        ResourceAttribute,  // MemoryAttribute
+        TopUseableMemAddr,  // MemoryBegin
+        MEM_EQU_4GB         // MemoryLength
+        );
+      TopUseableMemSize = TopUseableMemSize - MEM_EQU_4GB;
+      TopUseableMemAddr = TopUseableMemAddr + MEM_EQU_4GB;
+    }
+    //
+    // Create hob for remaining memory which is above 4G memory address.
+    //
+    if (TopUseableMemSize > MEM_EQU_4GB) {
+      PEI_DEBUG ((PeiServices, EFI_D_ERROR, "Found 0x%016lX bytes at ", TopUseableMemSize - MEM_EQU_4GB));
+      PEI_DEBUG ((PeiServices, EFI_D_ERROR, "0x%016lX\n", TopUseableMemAddr));
+    }
+    if (Inputs->MemoryTrace) {
+      //
+      // Mark memory above 4GB as reserved if it's used for Memory Trace
+      //
+      ResourceType      = EFI_RESOURCE_MEMORY_RESERVED;
+      ResourceAttribute = 0;
+    } else {
+      ResourceType      = EFI_RESOURCE_SYSTEM_MEMORY;
+      ResourceAttribute = EFI_RESOURCE_ATTRIBUTE_PRESENT |
+                          EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
+                          EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
+                          EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
+                          EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
+                          EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE;
+    }
+    BuildResourceDescriptorHob (
+      ResourceType,                     // MemoryType,
+      ResourceAttribute,                // MemoryAttribute
+      TopUseableMemAddr,                // MemoryBegin
+      (TopUseableMemSize - MEM_EQU_4GB) // MemoryLength
+      );
+  }
+  //
+  // If we found the capsule PPI (and we didn't have errors), then
+  // call the capsule PEIM to allocate memory for the capsule.
+  //
+  if (Capsule != NULL) {
+    Status = Capsule->CreateState (PeiServices, CapsuleBuffer, CapsuleBufferLength);
+  }
+
+  return EFI_SUCCESS;
+}
+
+/**
+  This function installs memory for the S3 resume path.
+
+  @param[in] Inputs           - Mrc input data structure
+  @param[in] PeiServices      - PEI services table.
+  @param[in] VariableServices - Pointer to EFI Variable PPI
+
+  @retval EFI_SUCCESS          - The function completed successfully.
+  @retval EFI_OUT_OF_RESOURCES - Out of Resources.
+**/
+EFI_STATUS
+InstallS3Memory (
+  IN const MrcInput *const      Inputs,
+  IN EFI_PEI_SERVICES           **PeiServices,
+  IN PEI_READ_ONLY_VARIABLE_PPI *VariableServices
+)
+{
+  EFI_STATUS                            Status;
+  UINTN                                 VarSize;
+  UINTN                                 VarAttrib;
+  EFI_PHYSICAL_ADDRESS                  TopUseableMemAddr;
+  EFI_PHYSICAL_ADDRESS                  TopUseableMemSize;
+  EFI_PHYSICAL_ADDRESS                  Tom;
+  UINT64                                AcpiVariableSet64;
+  ACPI_VARIABLE_SET                     *AcpiVariableSet;
+  UINTN                                 S3MemoryBase;
+  UINTN                                 S3MemorySize;
+  UINT8                                 NumRanges;
+  PEI_DUAL_CHANNEL_DDR_MEMORY_MAP_RANGE MemoryMap[MAX_RANGES];
+  EFI_PEI_HOB_POINTERS                  Hob;
+  EFI_SMRAM_HOB_DESCRIPTOR_BLOCK        *SmramHobDescriptorBlock;
+  EFI_SMRAM_DESCRIPTOR                  *SmramDescriptor;
+  EFI_RESOURCE_TYPE                     ResourceType;
+  EFI_RESOURCE_ATTRIBUTE_TYPE           ResourceAttribute;
+  UINT8                                 Index;
+  UINT8                                 SmramIndex;
+  UINT8                                 SmramRanges;
+  UINTN                                 BufferSize;
+  const MrcDebug                        *Debug;
+
+  Debug = &Inputs->Debug;
+  
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Install S3 resume memory.\n");
+  NumRanges = MAX_RANGES;
+  ZeroMem (MemoryMap, sizeof (PEI_DUAL_CHANNEL_DDR_MEMORY_MAP_RANGE) * NumRanges);
+  //
+  // Call to GetMemoryMap to initialize TSEG registers.
+  //
+  Status = GetMemoryMap (PeiServices, (PEI_DUAL_CHANNEL_DDR_MEMORY_MAP_RANGE *) MemoryMap, &NumRanges);
+  ASSERT_EFI_ERROR (Status);
+
+  AcpiVariableSet = NULL;
+  VarSize         = sizeof (AcpiVariableSet64);
+  VarAttrib       = EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS | EFI_VARIABLE_NON_VOLATILE;
+
+  Status = VariableServices->PeiGetVariable (
+    PeiServices,
+    ACPI_GLOBAL_VARIABLE,
+    &gEfiAcpiVariableGuid,
+    &VarAttrib,
+    &VarSize,
+    &AcpiVariableSet64
+    );
+  AcpiVariableSet = (ACPI_VARIABLE_SET *) (UINTN) AcpiVariableSet64;
+
+  if (EFI_ERROR (Status) || (AcpiVariableSet == NULL)) {
+    return EFI_OUT_OF_RESOURCES;
+  }
+
+  BuildGuidDataHob (&gEfiAcpiVariableGuid, AcpiVariableSet, sizeof (ACPI_VARIABLE_SET));
+
+  MRC_DEBUG_MSG (
+    Debug,
+    MSG_LEVEL_NOTE,
+    "AcpiVariableSet at = 0x%x. 0x%x\n",
+    AcpiVariableSet,
+    &AcpiVariableSet->AcpiReservedMemoryBase
+    );
+
+  S3MemoryBase = (UINTN) (AcpiVariableSet->AcpiReservedMemoryBase);
+  S3MemorySize = (UINTN) (AcpiVariableSet->AcpiReservedMemorySize);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "S3MemoryBase = 0x%x - S3MemorySize = 0x%x.\n", S3MemoryBase, S3MemorySize);
+  Status       = (*PeiServices)->InstallPeiMemory (PeiServices, S3MemoryBase, S3MemorySize);
+  ASSERT_EFI_ERROR (Status);
+
+  //
+  // Retrieve the system memory length and build memory hob for the system
+  // memory above 1MB, so memory callback can set cache for the system memory
+  // correctly on S3 resume path, just like it does on normal boot path.
+  //
+  PEI_ASSERT (PeiServices, (AcpiVariableSet->SystemMemoryLength - 0x100000) > 0);
+  BuildResourceDescriptorHob (
+    EFI_RESOURCE_SYSTEM_MEMORY,
+    (
+    EFI_RESOURCE_ATTRIBUTE_PRESENT |
+    EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
+    EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
+    EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
+    EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
+    EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE
+    ),
+    0x100000,
+    AcpiVariableSet->SystemMemoryLength - 0x100000
+    );
+
+  //
+  // Get the current "Top of Upper Usable Memory" address from TOUUD.
+  // If TOUUD > 4G, it means memory is re-mapped.
+  //
+  TopUseableMemSize = McD0PciCfg64 (R_SA_TOUUD) & B_SA_TOUUD_TOUUD_MASK;
+  TopUseableMemAddr = MEM_EQU_4GB;
+  Tom = McD0PciCfg64 (R_SA_TOM) & B_SA_TOM_TOM_MASK;
+
+  if (TopUseableMemSize > MEM_EQU_4GB) {
+    //
+    // This is a above 4G memory, give it to EFI
+    // if memory hob length is above 4G length,cut and separate it.
+    //
+    if (Inputs->MemoryTrace && (TopUseableMemAddr + MEM_EQU_4GB > RShiftU64 (Tom, 1))) {
+      if (Inputs->MemoryTrace) {
+        //
+        // Mark memory above 4GB as reserved if it's used for Memory Trace
+        //
+        ResourceType      = EFI_RESOURCE_MEMORY_RESERVED;
+        ResourceAttribute = 0;
+      } else {
+        ResourceType      = EFI_RESOURCE_SYSTEM_MEMORY;
+        ResourceAttribute = EFI_RESOURCE_ATTRIBUTE_PRESENT |
+                            EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
+                            EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
+                            EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
+                            EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
+                            EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE;
+      }
+      BuildResourceDescriptorHob (
+        ResourceType,       // MemoryType,
+        ResourceAttribute,  // MemoryAttribute
+        TopUseableMemAddr,  // MemoryBegin
+        MEM_EQU_4GB         // MemoryLength
+        );
+      TopUseableMemSize = TopUseableMemSize - MEM_EQU_4GB;
+      TopUseableMemAddr = TopUseableMemAddr + MEM_EQU_4GB;
+    }
+    //
+    // Create hob for remaining memory which is above 4G memory address.
+    //
+    if (Inputs->MemoryTrace) {
+      //
+      // Mark memory above 4GB as reserved if it's used for Memory Trace
+      //
+      ResourceType      = EFI_RESOURCE_MEMORY_RESERVED;
+      ResourceAttribute = 0;
+    } else {
+      ResourceType      = EFI_RESOURCE_SYSTEM_MEMORY;
+      ResourceAttribute = EFI_RESOURCE_ATTRIBUTE_PRESENT |
+                          EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
+                          EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
+                          EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
+                          EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
+                          EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE;
+    }
+    BuildResourceDescriptorHob (
+      ResourceType,                     // MemoryType,
+      ResourceAttribute,                // MemoryAttribute
+      TopUseableMemAddr,                // MemoryBegin
+      (TopUseableMemSize - MEM_EQU_4GB) // MemoryLength
+      );
+  }
+
+  //
+  // Report SMRAM ranges
+  //
+
+  SmramRanges = 0;
+  for (Index = 0; Index < NumRanges; Index++) {
+    if ((
+        (MemoryMap[Index].Type == DualChannelDdrSmramCacheable) ||
+        (MemoryMap[Index].Type == DualChannelDdrSmramNonCacheable)
+        ) &&
+        (MemoryMap[Index].PhysicalAddress  != MC_ABSEG_HSEG_PHYSICAL_START)
+        ) {
+      //
+      // Only count TSEG
+      //
+      SmramRanges++;
+    }
+  }
+
+  BufferSize = sizeof (EFI_SMRAM_HOB_DESCRIPTOR_BLOCK);
+  if (SmramRanges > 0) {
+    BufferSize += ((SmramRanges - 1) * sizeof (EFI_SMRAM_DESCRIPTOR));
+  }
+
+  Hob.Raw = BuildGuidHob (&gEfiSmmPeiSmramMemoryReserve, BufferSize);
+
+  SmramHobDescriptorBlock = (void *) (Hob.Raw);
+  SmramHobDescriptorBlock->NumberOfSmmReservedRegions = SmramRanges;
+
+  SmramIndex = 0;
+  for (Index = 0; Index < NumRanges; Index++) {
+    if ((
+        (MemoryMap[Index].Type == DualChannelDdrSmramCacheable) ||
+        (MemoryMap[Index].Type == DualChannelDdrSmramNonCacheable)
+        ) &&
+        (MemoryMap[Index].PhysicalAddress  != MC_ABSEG_HSEG_PHYSICAL_START)) {
+
+        //
+        // This is an SMRAM range (not reporting AB_SEG or H_SEG, create an SMRAM descriptor
+        //
+        SmramDescriptor = &SmramHobDescriptorBlock->Descriptor[SmramIndex];
+        SmramDescriptor->PhysicalStart = MemoryMap[Index].PhysicalAddress;
+        SmramDescriptor->CpuStart      = MemoryMap[Index].CpuAddress;
+        
+        //
+        // RangeLength includes alignment adjustment.
+        //
+        if (SmramDescriptor->PhysicalStart < 0x100000) {
+          SmramDescriptor->PhysicalSize  = MemoryMap[Index].RangeLength;
+        } else {
+          SmramDescriptor->PhysicalSize  = (Inputs->TsegSize - Inputs->IedSize )* 0x100000;
+        }
+        MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "TSeg base is %Xh\n", SmramDescriptor->PhysicalStart);
+        MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "TSeg SMRAM size is %Xh\n", SmramDescriptor->PhysicalSize);
+
+        if (MemoryMap[Index].Type == DualChannelDdrSmramCacheable) {
+          SmramDescriptor->RegionState = EFI_SMRAM_CLOSED | EFI_CACHEABLE;
+        } else {
+          SmramDescriptor->RegionState = EFI_SMRAM_CLOSED;
+        }
+        SmramIndex++;
+    }
+  }
+
+  return EFI_SUCCESS;
+}
+
+/**
+  Determine the memory size desired based on HOB memory information.
+
+  @param[in]      PeiServices - PEI Services table.
+  @param[in, out] Size        - The memory size to return.
+
+  @retval Nothing.
+**/
+void
+RetrieveRequiredMemorySize (
+  IN     EFI_PEI_SERVICES **PeiServices,
+  IN OUT UINTN            *Size
+  )
+{
+  EFI_STATUS                  Status;
+  EFI_PEI_HOB_POINTERS        Hob;
+  EFI_MEMORY_TYPE_INFORMATION *MemoryData;
+  UINT8                       Index;
+  UINTN                       TempPageNum;
+
+  *Size      = 0;
+  MemoryData = NULL;
+  Status     = (*PeiServices)->GetHobList (PeiServices, (VOID **) &Hob.Raw);
+  while (!END_OF_HOB_LIST (Hob)) {
+    if (Hob.Header->HobType == EFI_HOB_TYPE_GUID_EXTENSION &&
+      CompareGuid (&Hob.Guid->Name, &gEfiMemoryTypeInformationGuid)) {
+      MemoryData = (EFI_MEMORY_TYPE_INFORMATION *) (Hob.Raw + sizeof (EFI_HOB_GENERIC_HEADER) + sizeof (EFI_GUID));
+      break;
+    }
+
+    Hob.Raw = GET_NEXT_HOB (Hob);
+  }
+  //
+  // Platform PEIM should supply the information. Generic PEIM doesn't assume any default value.
+  //
+  if (MemoryData == NULL) {
+    return;
+  }
+
+  TempPageNum = 0;
+  for (Index = 0; MemoryData[Index].Type != EfiMaxMemoryType; Index++) {
+    //
+    // Accumulate default memory size requirements
+    //
+    TempPageNum += MemoryData[Index].NumberOfPages;
+  }
+
+  if (TempPageNum == 0) {
+    return;
+  }
+  //
+  // 16 additional pages are used by DXE memory manager.
+  //
+  *Size = (TempPageNum + 16) * EFI_PAGE_SIZE;
+
+  return;
+}
+
+/**
+  Determine the Total DPR memory size needed based on the DPR directory in the SA Data HOB.
+
+  @param[in]      PeiServices - PEI Services table.
+  @param[in, out] Size        - The memory size in MB to return.
+
+  @retval Nothing.
+**/
+void
+CalculateTotalDprMemorySize (
+  IN     EFI_PEI_SERVICES **PeiServices,
+  IN OUT UINT8            *Size
+  )
+{
+  UINT8                DprEntryIndex;
+  SA_DATA_HOB          *SaDataHob;
+  DPR_DIRECTORY_ENTRY  *DirectoryEntry;
+
+  *Size           = 0;
+  DprEntryIndex   = 0;
+  DirectoryEntry  = NULL;
+  SaDataHob       = NULL;
+
+  SaDataHob = GetFirstGuidHob (&gSaDataHobGuid);
+  if (SaDataHob != NULL) {
+    DirectoryEntry = SaDataHob->DprDirectory;
+    while(DprEntryIndex < DPR_DIRECTORY_MAX){
+      *Size += DirectoryEntry->Size;
+      DirectoryEntry++;
+      DprEntryIndex++;
+    }
+  }
+  return;
+}
+
+/**
+  Calculates the bases for each technology consuming the DPR region
+  and updates the SA Data HOB with the appropriate values in the Dpr
+  directory
+
+  @param[in] PeiServices    - PEI Services table.
+  @param[in] Base           - The memory base to return.
+  @param[in] TotalDprSizeMB - The total DPR size in MB
+
+  @retval Nothing.
+**/
+void
+UpdateDprHobInfo (
+  IN EFI_PEI_SERVICES      **PeiServices,
+  IN EFI_PHYSICAL_ADDRESS  Base,
+  IN UINT8                 TotalDprSizeMB
+  )
+{
+  UINT32               TopOfDpr;
+  UINT8                DprEntryIndex;
+  SA_DATA_HOB          *SaDataHob;
+  DPR_DIRECTORY_ENTRY  *DirectoryEntry;
+
+  DprEntryIndex   = 0;
+  DirectoryEntry  = NULL;
+  SaDataHob       = NULL;
+  TopOfDpr        = (UINT32) Base + (UINT32) LShiftU64(TotalDprSizeMB, 20);
+
+  SaDataHob = GetFirstGuidHob (&gSaDataHobGuid);
+  if (SaDataHob != NULL) {
+    DirectoryEntry = SaDataHob->DprDirectory;
+    while(DprEntryIndex < DPR_DIRECTORY_MAX){
+      switch (DirectoryEntry->Type) {
+        case DPR_DIRECTORY_TYPE_TXT:
+          DirectoryEntry->PhysBase = (UINT32) TopOfDpr - (UINT32) LShiftU64(DirectoryEntry->Size, 20);
+          break;
+        case DPR_DIRECTORY_TYPE_PFAT:
+          DirectoryEntry->PhysBase = (UINT32) Base;
+          break;
+        default:
+          break;
+      }
+      DirectoryEntry++;
+      DprEntryIndex++;
+    }
+  }
+  return;
+}
+
+/**
+  Determine the memory size desired by GDXC
+
+  @param[in]      PeiServices - PEI Services table.
+  @param[in, out] MotSize     - The MOT memory size
+  @param[in, out] GdxcSize    - The GDXC memory size
+
+  @retval Nothing.
+**/
+void
+RetrieveGdxcMemorySize (
+  IN  EFI_PEI_SERVICES **PeiServices,
+  OUT UINT64            *MotSize,
+  OUT UINT64            *GdxcSize
+  )
+{
+  UINT32                              MchBar;
+  UINT32                              GdxcBar;
+  UINT32                              TempMotSize;
+  MPCOHTRK_CR_GDXC_MOT_REGION_STRUCT  MotRange;
+  MPCOHTRK_CR_GDXC_OCLA_REGION_STRUCT OclaRange;
+
+  *MotSize  = 0;
+  *GdxcSize = 0;
+
+  //
+  // Get MchBAR
+  //
+  MchBar = McD0PciCfg32 (R_SA_MCHBAR) & B_SA_MCHBAR_MCHBAR_MASK;
+  //
+  // Get GdxcBar
+  //
+  MrcOemMmioRead (NCDECS_CR_GDXCBAR_NCU_REG, (U32 *) &GdxcBar, MchBar);
+  GdxcBar &= NCDECS_CR_GDXCBAR_NCU_MAX;
+  //
+  // Determine Gdxc size: Includes MOT\PSMI\IOT (OCLA)
+  //
+  MrcOemMmioRead(MPCOHTRK_CR_GDXC_MOT_REGION_REG, (U32 *) &MotRange, GdxcBar);
+  TempMotSize = MotRange.Bits.END_ADDRESS - MotRange.Bits.START_ADDRESS;
+  if (TempMotSize > 0) {
+    *GdxcSize = *MotSize = MrcOemMemoryLeftShiftU64 ((UINT64) (TempMotSize + 1), 23);
+  }
+
+  MrcOemMmioRead(MPCOHTRK_CR_GDXC_OCLA_REGION_REG, (U32 *) &OclaRange, GdxcBar);
+  *GdxcSize += MrcOemMemoryLeftShiftU64 ((UINT64) (OclaRange.Bits.END_ADDRESS - OclaRange.Bits.START_ADDRESS), 23);
+
+  // Add 16MB if some allocated to MOT and/or IOT
+  if (*GdxcSize != 0) {
+    *GdxcSize += (16 << 20);
+  }
+
+  return;
+}
+
+/**
+  This function returns the memory ranges to be enabled, along with information
+  describing how the range should be used. The MemoryMap buffer will be filled in and
+  NumRanges will contain the actual number of memory ranges that are to be enabled.
+
+  @param[in]      PeiServices - PEI Services Table.
+  @param[in, out] MemoryMap   - Buffer to record details of the memory ranges to be enabled.
+  @param[in, out] NumRanges   - On input, this contains the maximum number of memory ranges that
+                                can be described in the MemoryMap buffer.
+
+  @retval EFI_SUCCESS          - The function completed successfully.
+  @retval EFI_BUFFER_TOO_SMALL - The specified number of ranges is too large.
+**/
+EFI_STATUS
+GetMemoryMap (
+  IN     EFI_PEI_SERVICES                      **PeiServices,
+  IN OUT PEI_DUAL_CHANNEL_DDR_MEMORY_MAP_RANGE *MemoryMap,
+  IN OUT UINT8                                 *NumRanges
+  )
+{
+  BOOLEAN                          EnableSmram;
+  EFI_PHYSICAL_ADDRESS             MemorySize;
+  EFI_PHYSICAL_ADDRESS             RowLength;
+  EFI_PHYSICAL_ADDRESS             AlignedTsegBase;
+  EFI_PHYSICAL_ADDRESS             AlignedGdxcBase;
+  EFI_STATUS                       Status;
+  PEI_MEMORY_RANGE_GRAPHICS_MEMORY GraphicsMemoryMask;
+  PEI_MEMORY_RANGE_PCI_MEMORY      PciMemoryMask;
+  PEI_MEMORY_RANGE_OPTION_ROM      OptionRomMask;
+  PEI_MEMORY_RANGE_SMRAM           SmramMask;
+  PEI_MEMORY_RANGE_SMRAM           TsegMask;
+  PEI_PLATFORM_MEMORY_RANGE_PPI    *MemoryRangePpi;
+  UINT32                           BlockNum;
+  UINT8                            EsmramcRegister;
+  UINT8                            ExtendedMemoryIndex;
+  UINT8                            Index;
+  UINT8                            TotalDprSizeMB;
+  UINT64                           GdxcRequiredMemSize;
+  UINT64                           GdxcMotMemSize;
+#ifdef PTT_FLAG
+  UINT32                           PttSts;
+#endif
+  if ((*NumRanges) < MAX_RANGES) {
+    return EFI_BUFFER_TOO_SMALL;
+  }
+
+  *NumRanges = 0;
+
+  //
+  // Get platform memory range service
+  //
+  Status = (*PeiServices)->LocatePpi (PeiServices, &gPeiPlatformMemoryRangePpiGuid, 0, NULL, (VOID **) &MemoryRangePpi);
+  ASSERT_EFI_ERROR (Status);
+
+  //
+  // Find out which memory ranges to reserve on this platform
+  //
+  Status = MemoryRangePpi->ChooseRanges (
+    PeiServices,
+    MemoryRangePpi,
+    &OptionRomMask,
+    &SmramMask,
+    &GraphicsMemoryMask,
+    &PciMemoryMask
+    );
+  ASSERT_EFI_ERROR (Status);
+  //
+  // MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "OptionRomMask      = %Xh\n", OptionRomMask);
+  // MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "SmramMask          = %Xh\n", SmramMask);
+  // MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "GraphicsMemoryMask = %Xh\n", GraphicsMemoryMask);
+  // MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "PciMemoryMask      = %Xh\n", PciMemoryMask);
+  //
+  //
+  // Generate memory ranges for the memory map.
+  //
+  EnableSmram     = FALSE;
+  EsmramcRegister = 0;
+  MemorySize      = 0;
+  Index           = 0;
+
+  //
+  // Get the current "max usable memory" address from TOLUD because we will not
+  // support any memory above 4Gig.  Will ignore the memory between 4G and TOUUD.
+  //
+  RowLength = McD0PciCfg32 (R_SA_TOLUD) & B_SA_TOLUD_TOLUD_MASK;
+
+  //
+  // System is very unlikely to work with less than 32MB
+  //
+  PEI_ASSERT (PeiServices, RowLength >= (32 * 1024 * 1024));
+
+  //
+  // Add memory below 640KB to the memory map. Make sure memory between
+  // 640KB and 1MB are reserved, even if not used for SMRAM
+  //
+  MemoryMap[*NumRanges].RowNumber       = Index;
+  MemoryMap[*NumRanges].PhysicalAddress = MemorySize;
+  MemoryMap[*NumRanges].CpuAddress      = MemorySize;
+  MemoryMap[*NumRanges].RangeLength     = 0xA0000;
+  MemoryMap[*NumRanges].Type            = DualChannelDdrMainMemory;
+  (*NumRanges)++;
+
+  //
+  // Reserve ABSEG or HSEG SMRAM if needed
+  //
+  if (SmramMask & (PEI_MR_SMRAM_ABSEG_MASK | PEI_MR_SMRAM_HSEG_MASK)) {
+    EnableSmram = TRUE;
+    MemoryMap[*NumRanges].PhysicalAddress = MC_ABSEG_HSEG_PHYSICAL_START;
+    MemoryMap[*NumRanges].RangeLength     = MC_ABSEG_HSEG_LENGTH;
+    MemoryMap[*NumRanges].CpuAddress      = (SmramMask & PEI_MR_SMRAM_ABSEG_MASK) ?
+      MC_ABSEG_CPU_START :
+      MC_HSEG_CPU_START;
+    //
+    // Chipset only supports cacheable SMRAM.
+    //
+    MemoryMap[*NumRanges].Type = DualChannelDdrSmramNonCacheable;
+  }
+  else {
+    //
+    // Just mark this range reserved.
+    //
+    MemoryMap[*NumRanges].PhysicalAddress = MC_ABSEG_HSEG_PHYSICAL_START;
+    MemoryMap[*NumRanges].CpuAddress      = MC_ABSEG_CPU_START;
+    MemoryMap[*NumRanges].RangeLength     = 0x60000;
+    MemoryMap[*NumRanges].Type            = DualChannelDdrReservedMemory;
+  }
+
+  MemoryMap[*NumRanges].RowNumber = Index;
+  (*NumRanges)++;
+
+  RowLength -= 0x100000;
+  MemorySize = 0x100000;
+
+  //
+  // Add remaining memory to the memory map.
+  //
+  if (RowLength > 0) {
+    MemoryMap[*NumRanges].RowNumber       = Index;
+    MemoryMap[*NumRanges].PhysicalAddress = MemorySize;
+    MemoryMap[*NumRanges].CpuAddress      = MemorySize;
+    MemoryMap[*NumRanges].RangeLength     = RowLength;
+    MemoryMap[*NumRanges].Type            = DualChannelDdrMainMemory;
+    (*NumRanges)++;
+    MemorySize += RowLength;
+  }
+
+  ExtendedMemoryIndex = (UINT8) (*NumRanges - 1);
+
+  //
+  // See if we need to trim Graphics Memory out of the highest memory range.
+  //
+  if (GraphicsMemoryMask != PEI_MR_GRAPHICS_MEMORY_NONE) {
+    //
+    // Create the new range for Graphics Memory from the previous SdrDdrMainMemory range.
+    //
+    MemoryMap[*NumRanges].RangeLength           = ((GraphicsMemoryMask & PEI_MR_GRAPHICS_MEMORY_SIZE_MASK) * 512 * 1024);
+    MemoryMap[*NumRanges].RowNumber             = MemoryMap[ExtendedMemoryIndex].RowNumber;
+    MemorySize                                 -= MemoryMap[*NumRanges].RangeLength;
+    MemoryMap[*NumRanges].PhysicalAddress       = MemorySize;
+    MemoryMap[*NumRanges].CpuAddress            = MemorySize;
+    MemoryMap[ExtendedMemoryIndex].RangeLength -= MemoryMap[*NumRanges].RangeLength;
+    MemoryMap[*NumRanges].Type                  = (GraphicsMemoryMask & PEI_MR_GRAPHICS_MEMORY_CACHEABLE) ?
+      DualChannelDdrGraphicsMemoryCacheable : DualChannelDdrGraphicsMemoryNonCacheable;
+
+    (*NumRanges)++;
+  }
+  //
+  // See if we need to trim TSEG out of the highest memory range.
+  //
+  if (SmramMask & PEI_MR_SMRAM_TSEG_MASK) {
+    //
+    // Create the new range for TSEG and remove that range from the previous SdrDdrMainMemory range.
+    //
+    TsegMask = (SmramMask & PEI_MR_SMRAM_SIZE_MASK);
+
+    BlockNum = 1;
+    while (TsegMask) {
+      TsegMask >>= 1;
+      BlockNum <<= 1;
+    }
+
+    BlockNum >>= 1;
+
+    switch (BlockNum) {
+    case PEI_MR_SMRAM_SIZE_1024K_MASK:
+      break;
+
+    case PEI_MR_SMRAM_SIZE_2048K_MASK:
+      break;
+
+    case PEI_MR_SMRAM_SIZE_8192K_MASK:
+      break;
+
+    case PEI_MR_SMRAM_SIZE_16384K_MASK:
+      break;
+
+    case PEI_MR_SMRAM_SIZE_32768K_MASK:
+      break;
+
+    case PEI_MR_SMRAM_SIZE_65536K_MASK:
+      break;
+
+    default:
+      //
+      // Non supported size. Set to 0.
+      //
+      BlockNum = 0;
+      break;
+    }
+
+    if (BlockNum) {
+      EnableSmram                       = TRUE;
+
+      MemoryMap[*NumRanges].RangeLength = (BlockNum * 128 * 1024);
+      MemoryMap[*NumRanges].RowNumber   = MemoryMap[ExtendedMemoryIndex].RowNumber;
+      MemorySize                       -= MemoryMap[*NumRanges].RangeLength;
+
+      //
+      // MRC aligns TSEG base on 8MB boundary.
+      // Need to adjust memory map accordingly.
+      //
+      AlignedTsegBase                             = MemorySize & ~(MemoryMap[*NumRanges].RangeLength - 1);
+      MemoryMap[*NumRanges].RangeLength          += (MemorySize - AlignedTsegBase);
+      MemorySize                                  = AlignedTsegBase;
+      MemoryMap[*NumRanges].PhysicalAddress       = AlignedTsegBase;
+      MemoryMap[*NumRanges].CpuAddress            = AlignedTsegBase;
+      MemoryMap[ExtendedMemoryIndex].RangeLength -= MemoryMap[*NumRanges].RangeLength;
+    }
+    //
+    // Chipset only supports cacheable SMRAM.
+    //
+    MemoryMap[*NumRanges].Type = DualChannelDdrSmramCacheable;
+
+    (*NumRanges)++;
+  }
+
+//;;## ...AMI_OVERRIDE... Disable compatible SMM space A00000 and B00000 start.
+#ifndef SMM_THUNK_NO_AB_SEG_FLAG
+  //
+  // Turn on SMRAM if required.
+  //
+  if (EnableSmram) {
+    McD0PciCfg8Or (R_SA_SMRAMC, B_SA_SMRAMC_G_SMRAME_MASK);
+  }
+#endif
+//;;## ...AMI_OVERRIDE... Disable compatible SMM space A00000 and B00000 end.
+  //
+  // Reserve DPR based on Total size required by all technologies using DPR
+  //
+  CalculateTotalDprMemorySize (PeiServices, &TotalDprSizeMB);
+
+  if (TotalDprSizeMB != 0) {
+
+    MemoryMap[*NumRanges].RangeLength           = (UINT64) LShiftU64 (TotalDprSizeMB, 20);
+    MemoryMap[*NumRanges].RowNumber             = MemoryMap[ExtendedMemoryIndex].RowNumber;
+    MemorySize                                 -= MemoryMap[*NumRanges].RangeLength;
+    MemoryMap[*NumRanges].PhysicalAddress       = MemorySize;
+    MemoryMap[*NumRanges].CpuAddress            = MemorySize;
+    MemoryMap[ExtendedMemoryIndex].RangeLength -= MemoryMap[*NumRanges].RangeLength;
+    MemoryMap[*NumRanges].Type                  = DualChannelDdrReservedMemory;
+
+    UpdateDprHobInfo (PeiServices, MemorySize, TotalDprSizeMB);
+
+    (*NumRanges)++;
+  }
+
+  //
+  // Reserve GDXC
+  //
+  RetrieveGdxcMemorySize (PeiServices, &GdxcMotMemSize, &GdxcRequiredMemSize);
+
+  if (GdxcRequiredMemSize) {
+    MemoryMap[*NumRanges].RangeLength           = GdxcMotMemSize;
+    MemoryMap[*NumRanges].RowNumber             = MemoryMap[ExtendedMemoryIndex].RowNumber;
+    MemorySize                                 -= MemoryMap[*NumRanges].RangeLength;
+
+    //
+    // MRC aligns Mot base on 16MB boundary.
+    // Need to adjust memory map accordingly.
+    //
+    AlignedGdxcBase                             = MemorySize &~(MRC_BIT24 - 1);
+    //
+    // Now subtract rest of GdxcRequiredMemsize - GdxcMotMemSize
+    //
+    AlignedGdxcBase                            -= GdxcRequiredMemSize - GdxcMotMemSize;
+    MemoryMap[*NumRanges].RangeLength          += (MemorySize - AlignedGdxcBase);
+    MemorySize                                  = AlignedGdxcBase;
+    MemoryMap[*NumRanges].PhysicalAddress       = AlignedGdxcBase;
+    MemoryMap[*NumRanges].CpuAddress            = AlignedGdxcBase;
+    MemoryMap[ExtendedMemoryIndex].RangeLength -= MemoryMap[*NumRanges].RangeLength;
+    MemoryMap[*NumRanges].Type                  = DualChannelDdrReservedMemory;
+
+    (*NumRanges)++;
+  }
+
+#ifdef PTT_FLAG
+  if (GetCpuFamily() == cmHSW_ULT) {
+    MrcOemMmioRead (R_PTT_HCI_STS, (U32 *) &PttSts, R_PTT_HCI_BASE_ADDRESS);
+    if ((PttSts & B_PTT_HCI_STS_ENABLED) == B_PTT_HCI_STS_ENABLED) {
+      MemoryMap[*NumRanges].RangeLength           = 0x1000;
+      MemoryMap[*NumRanges].RowNumber             = MemoryMap[ExtendedMemoryIndex].RowNumber;
+      MemorySize                                 -= MemoryMap[*NumRanges].RangeLength;
+      MemoryMap[*NumRanges].PhysicalAddress       = MemorySize;
+      MemoryMap[*NumRanges].CpuAddress            = MemorySize;
+      MemoryMap[ExtendedMemoryIndex].RangeLength -= MemoryMap[*NumRanges].RangeLength;
+      MemoryMap[*NumRanges].Type                  = DualChannelDdrReservedMemory;
+
+      (*NumRanges)++;
+    }
+  }
+#endif
+
+  return EFI_SUCCESS;
+}
+
+/**
+  This function returns a pointer to the allocated hand off buffer.
+
+  @param[in]      PeiServices - A pointer to the EFI PEI services table
+  @param[in, out] Hob         - A pointer to where to store the pointer to the allocated data buffer.
+  @param[in]      Size        - The size of the buffer to get.
+
+  @retval EFI_SUCCESS - Hob is successfully built.
+  @retval Others      - Error occured while creating the Hob.
+**/
+EFI_STATUS
+MrcGetHobForDataStorage (
+  IN     EFI_PEI_SERVICES       **PeiServices,
+  IN OUT HOB_SAVE_MEMORY_DATA   **Hob,
+  IN     UINT16                 BlockSize
+  )
+{
+  EFI_STATUS     Status;
+
+  Status = (*PeiServices)->CreateHob (PeiServices, EFI_HOB_TYPE_GUID_EXTENSION, BlockSize, (VOID **) Hob);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+  (*Hob)->EfiHobGuidType.Name = gMemRestoreDataGuid;
+  ZeroMem (&((*Hob)->MrcData), sizeof (MrcParameters));
+  return EFI_SUCCESS;
+}
+
+/**
+  A small memory test to quickly point out severe memory issues.
+
+  @param[in] Inputs - Pointer to the MRC Input data structure
+
+  @retval mrcFail on failure, otherwise mrcSuccess.
+**/
+MrcStatus
+BasicMemoryTest (
+  IN const MrcInput * const Inputs
+  )
+{
+  const UINT32    BlockSize = 0x1000;
+  UINT8           *Addr;
+  UINT8           Pattern;
+  UINT8           Value;
+  UINTN           LoopCount;
+  const MrcDebug  *Debug;
+
+  Debug = &Inputs->Debug;
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Normal mode memory test started.\n");
+
+  Addr    = 0;
+  Pattern = 0;
+  while ((UINT32) Addr < BlockSize) {
+    *Addr = Pattern++;
+    Addr++;
+  }
+
+  for (LoopCount = 0; LoopCount < 20; LoopCount++) {
+    Addr    = 0;
+    Pattern = 0;
+    while ((UINT32) Addr < BlockSize) {
+      Value = *Addr;
+      if (Value != Pattern) {
+        MRC_DEBUG_MSG (Debug, MSG_LEVEL_ERROR, "!!! Normal mode memory test FAILED !!!\n");
+        MRC_DEBUG_MSG (
+          Debug,
+          MSG_LEVEL_ERROR,
+          "Address: %Xh, Expected data: %Xh, Actual data: %Xh.\n",
+          Addr,
+          Pattern,
+          Value
+          );
+        return mrcFail;
+      }
+      Addr++;
+      Pattern++;
+    }
+  }
+
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Normal mode memory test passed.\n");
+  return mrcSuccess;
+}
+
+#ifndef TXT_SUPPORT_FLAG
+/**
+  Determines whether or not the platform has executed a TXT launch by
+  examining the TPM Establishment bit.
+
+  @param[in] PeiServices - General purpose services available to every PEIM.
+
+  @retval TRUE        - If the TPM establishment bit is asserted.
+  @retval FALSE       - If the TPM establishment bit is unasserted.
+**/
+BOOLEAN
+IsEstablishmentBitAsserted (
+  IN EFI_PEI_SERVICES **PeiServices
+  )
+{
+  UINT8         Access;
+  UINT16        TimeOutCount;
+  EFI_STATUS    Status;
+  PEI_STALL_PPI *StallPpi;
+  Status = (*PeiServices)->LocatePpi (PeiServices, &gPeiStallPpiGuid, 0, NULL, (VOID **) &StallPpi);
+  ASSERT_EFI_ERROR (Status);
+
+
+  //
+  // Set TPM.ACCESS polling timeout about 750ms.
+  //
+  TimeOutCount = TPM_TIME_OUT;
+  do {
+    //
+    // Read TPM status register
+    //
+
+    Access = (*PeiServices)->CpuIo->MemRead8 (
+      PeiServices,
+      (*PeiServices)->CpuIo,
+      TPM_STATUS_REG_ADDRESS
+      );
+
+    //
+    // if TPM.Access == 0xFF, TPM is not present.
+    //
+    if (Access == 0xFF) {
+      return FALSE;
+    }
+    //
+    // Check tpmRegValidSts bit before checking establishment bit.
+    //
+    if ((Access & 0x80) == 0x80) {
+      //
+      // tpmRegValidSts set, we can check establishment bit now.
+      //
+      break;
+    }
+    else {
+      //
+      // Delay 1ms
+      //
+      StallPpi->Stall (PeiServices, StallPpi, 1000);
+    }
+
+    TimeOutCount--;
+  } while (TimeOutCount != 0);
+
+  //
+  // ValidSts is not set.
+  //
+  if ((Access & 0x80) != 0x80) {
+    return FALSE;
+  }
+  //
+  // The bit we're interested in uses negative logic:
+  // If bit 0 == 1 then return False,
+  // Else return True.
+  //
+  return (BOOLEAN) ((Access & 0x1) ? FALSE : TRUE);
+}
+
+/**
+  Unlock memory when security is set and TxT is not enabled.
+
+  @param[in] MrcData     - Mrc global data.
+  @param[in] PeiServices - PEI Services Table.
+
+  @retval Nothing
+**/
+void
+UnlockMemory (
+  IN const MrcParameters *const MrcData,
+  IN EFI_PEI_SERVICES           **PeiServices
+  )
+{
+  EFI_CPUID_REGISTER Reg;
+  UINT32             Data32;
+  const MrcDebug     *Debug;
+
+  Debug = &MrcData->SysIn.Inputs.Debug;
+
+  Data32 = 0;
+
+  EfiCpuid (1, &Reg);
+  if ((Reg.RegEcx & BIT6)) {
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Processor supports TXT\n");
+
+    Data32 = CheckSmxCapabilities();
+
+    if (Data32 & BIT0) {
+      MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Platform / PCH supports TXT\n");
+      if (!(IsEstablishmentBitAsserted (PeiServices))) {
+        MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Unlock memory\n");
+        EfiWriteMsr (0x2e6, 0);
+      }
+    }
+    else {
+      MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Platform / PCH does not support TxT\n");
+    }
+  }
+  else {
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Processor does not support TxT\n");
+  }
+}
+#endif // TXT_SUPPORT_FLAG
+
+/**
+  Determine whether a cold reset of the platform is required.
+  Note that the memory configuration saved data must be valid.
+
+  @param[in] MrcData             - The MRC "global data" area.
+  @param[in] SaPlatformPolicyPpi - SA Platform Policy structure.
+
+  @retval TRUE if cold reset is required, otherwise returns FALSE.
+**/
+BOOLEAN
+ColdBootRequired (
+  IN const MrcParameters *const MrcData,
+  IN SA_PLATFORM_POLICY_PPI     *SaPlatformPolicyPpi
+  )
+{
+  const MrcDebug       *Debug;
+  const MrcInput       *Inputs;
+  const MrcSaveData    *SaveData;
+  MEMORY_CONFIGURATION *MemConfig;
+  MrcVersion           Version;
+  U32                  CurrentCrc;
+
+  Inputs    = &MrcData->SysIn.Inputs;
+  Debug     = &Inputs->Debug;
+  SaveData  = &MrcData->SysSave.Save.Data;
+  MemConfig = SaPlatformPolicyPpi->MemConfig;
+
+  MrcVersionGet (&Version);
+  CurrentCrc   = MrcCalculateCrc32 ((U8 *) MemConfig, sizeof (MEMORY_CONFIGURATION));
+
+  if ((Version.Major != SaveData->Version.Major) ||
+      (Version.Minor != SaveData->Version.Minor) ||
+      (Version.Rev   != SaveData->Version.Rev)   ||
+      (Version.Build != SaveData->Version.Build)) {
+    MRC_DEBUG_MSG (
+      Debug,
+      MSG_LEVEL_NOTE,
+      "MRC change detected, prev. ver. %u.%u.%u.%u, curr. ver. %u.%u.%u.%u\n",
+      SaveData->Version.Major,
+      SaveData->Version.Minor,
+      SaveData->Version.Rev,
+      SaveData->Version.Build,
+      Version.Major,
+      Version.Minor,
+      Version.Rev,
+      Version.Build
+      );
+    return TRUE;
+  }
+  if ((Inputs->CpuModel != SaveData->CpuModel) || (Inputs->CpuStepping != SaveData->CpuStepping)) {
+    MRC_DEBUG_MSG (
+      Debug,
+      MSG_LEVEL_NOTE,
+      "CPU change detected, prev. CPU %x.%x, curr. CPU %x.%x\n",
+      SaveData->CpuModel,
+      SaveData->CpuStepping,
+      Inputs->CpuModel,
+      Inputs->CpuStepping
+      );
+    return TRUE;
+  }
+  if (CurrentCrc != SaveData->SaMemCfgCrc) {
+    MRC_DEBUG_MSG (
+      Debug,
+      MSG_LEVEL_NOTE,
+      "System Agent input parameter change detected, prev. CRC %xh, curr. CRC %xh.\n",
+      SaveData->SaMemCfgCrc,
+      CurrentCrc
+      );
+
+    return TRUE;
+  }
+  return FALSE;
+}
+
+/**
+  Set up the MRC input data structure.
+
+  @param[in]  SysBootMode         - Boot mode of the system.
+  @param[in]  BootMode            - Boot mode of the Mrc.
+  @param[out] Inputs              - Pointer to the Mrc Input data structure.
+  @param[in]  PeiServices         - PEI Services Table.
+  @param[in]  SaPlatformPolicyPpi - SA Platform Policy structure.
+
+  @retval Always returns mrcSuccess.
+**/
+MrcBootMode
+MrcSetupMrcData (
+  IN  const EFI_BOOT_MODE           SysBootMode,
+  IN  const MrcBootMode             BootMode,
+  OUT MrcInput *const               Inputs,
+  IN  EFI_PEI_SERVICES **const      PeiServices,
+  IN  SA_PLATFORM_POLICY_PPI *const SaPlatformPolicyPpi
+  )
+{
+  const MEMORY_CONFIGURATION  *MemConfig;
+  const MrcDebug              *Debug;
+  MrcControllerIn             *ControllerIn;
+  MrcChannelIn                *ChannelIn;
+  U16                         DeviceId;
+  U8                          Controller;
+  U8                          Channel;
+  U8                          Dimm;
+
+  Debug     = &Inputs->Debug;
+  MemConfig = SaPlatformPolicyPpi->MemConfig;
+
+  Inputs->SaMemCfgAddress = (U32) MemConfig;
+  Inputs->SaMemCfgSize    = sizeof (MEMORY_CONFIGURATION);
+  Inputs->RefClk          = 0;
+  Inputs->Ratio           = 0;
+  Inputs->VddVoltage      = VDD_INVALID;
+
+  // Setup the memory profile (Standard/XMP/Custom)
+  switch (MemConfig->SpdProfileSelected) {
+#if (SUPPORT_XMP == SUPPORT)
+    case XMPProfile1:
+      Inputs->MemoryProfile = (SysBootMode == BOOT_WITH_DEFAULT_SETTINGS) ? STD_PROFILE : XMP_PROFILE1;
+      break;
+    case XMPProfile2:
+      Inputs->MemoryProfile = (SysBootMode == BOOT_WITH_DEFAULT_SETTINGS) ? STD_PROFILE : XMP_PROFILE2;
+      break;
+#endif // SUPPORT_XMP
+    case UserDefined:
+      if (SysBootMode == BOOT_WITH_DEFAULT_SETTINGS) {
+        Inputs->MemoryProfile = STD_PROFILE;
+      } else {
+        Inputs->MemoryProfile = USER_PROFILE;
+        Inputs->RefClk        = MemConfig->RefClk;
+        Inputs->Ratio         = MemConfig->Ratio;
+        Inputs->VddVoltage    = MemConfig->DDR3Voltage;
+      }
+      break;
+    case Default:
+    default:
+      Inputs->MemoryProfile = STD_PROFILE;
+      break;
+  }
+
+  // Setup the base addresses.
+  Inputs->MchBarBaseAddress = SaPlatformPolicyPpi->PlatformData->MchBar;
+  Inputs->PciEBaseAddress   = SaPlatformPolicyPpi->PlatformData->PciExpressBar;
+  Inputs->SmbusBaseAddress  = SaPlatformPolicyPpi->PlatformData->SmbusBar;
+  Inputs->GdxcBaseAddress   = SaPlatformPolicyPpi->PlatformData->GdxcBar;
+  Inputs->HpetBaseAddress   = 0xFED00000;
+
+  //
+  // MMIO size in MB units (below 4GB)
+  //
+  Inputs->MmioSize = SaPlatformPolicyPpi->GtConfig->MmioSize;
+
+  //
+  // DDR maximum frequency
+  //
+  Inputs->FreqMax = MemConfig->DdrFreqLimit;
+
+  //
+  // TSEG Size in MB units
+  //
+  Inputs->TsegSize = (SaPlatformPolicyPpi->PlatformData->TsegSize) >> 20;
+
+  //
+  // Graphics Stolen Size
+  //
+  Inputs->GraphicsGttSize            = SaPlatformPolicyPpi->GtConfig->GttSize;
+  // IgdDvmt50PreAlloc value 17 represents 1024M memory - WA for GMS limitation of 5 bits.
+  if (SaPlatformPolicyPpi->GtConfig->IgdDvmt50PreAlloc == 17) {
+    Inputs->GraphicsStolenSize         = 32 * 32;
+  } else {
+    Inputs->GraphicsStolenSize         = 32 * SaPlatformPolicyPpi->GtConfig->IgdDvmt50PreAlloc;
+  }
+  Inputs->GfxIsVersatileAcceleration = FALSE;
+
+  //
+  //Get RTC time
+  //
+  MrcOemGetRtcTime(&(Inputs->BaseTime.Seconds),&(Inputs->BaseTime.Minutes),
+    &(Inputs->BaseTime.Hours), &(Inputs->BaseTime.DayOfMonth),
+    &(Inputs->BaseTime.Month), &(Inputs->BaseTime.Year) );
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "RTC %u/%u/%u %u:%u:%u\n",
+    Inputs->BaseTime.Month,   Inputs->BaseTime.DayOfMonth,
+    Inputs->BaseTime.Year,    Inputs->BaseTime.Hours,
+    Inputs->BaseTime.Minutes, Inputs->BaseTime.Seconds);
+
+  //
+  // Get BoardType (Mobile - 0; Desktop/UpServer - 1)
+  //
+  Inputs->BoardType      = SaPlatformPolicyPpi->PlatformData->UserBd;
+  DeviceId = McD0PciCfg16 (R_SA_MC_DEVICE_ID);
+  Inputs->MobilePlatform = (IS_SA_DEVICE_ID_MOBILE(DeviceId)) ? TRUE : FALSE;
+
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_ERROR, "BoardType=%d, MobilePlatform=%d\n", Inputs->BoardType, Inputs->MobilePlatform);
+
+  //
+  // Get memory voltages requested value.
+  //
+  Inputs->VddSettleWaitTime = MemConfig->DDR3VoltageWaitTime;
+  Inputs->VccIomV           = 1000;      // Assume 1.0 volts
+
+  Inputs->SetRxDqs32        = FALSE;
+  Inputs->McLock                        = MemConfig->McLock;
+
+  Inputs->Gdxc.GdxcEnable          = MemConfig->GdxcEnable;    // Enable/disable GDXC support
+  Inputs->Gdxc.GdxcIotSize         = MemConfig->GdxcIotSize;   // Value in 8MB
+  Inputs->Gdxc.GdxcMotSize         = MemConfig->GdxcMotSize;   // Value in 8MB
+
+  Inputs->MemoryTrace              = MemConfig->MemoryTrace;   // Memory Trace to second DDR channel using Stacked Mode
+
+  //
+  // Options for training steps
+  //
+  Inputs->TrainingEnables.ECT        = MemConfig->ECT;
+  Inputs->TrainingEnables.SOT        = MemConfig->SOT;
+  Inputs->TrainingEnables.RDMPRT     = MemConfig->RDMPRT;
+  Inputs->TrainingEnables.RCVET      = MemConfig->RCVET;
+  Inputs->TrainingEnables.JWRL       = MemConfig->JWRL;
+  Inputs->TrainingEnables.FWRL       = MemConfig->FWRL;
+  Inputs->TrainingEnables.WRTC1D     = MemConfig->WRTC1D;
+  Inputs->TrainingEnables.RDTC1D     = MemConfig->RDTC1D;
+  Inputs->TrainingEnables.DIMMODTT   = MemConfig->DIMMODTT;
+  Inputs->TrainingEnables.WRDST      = MemConfig->WRDST;
+  Inputs->TrainingEnables.WREQT      = MemConfig->WREQT;
+  Inputs->TrainingEnables.RDODTT     = MemConfig->RDODTT;
+  Inputs->TrainingEnables.RDEQT      = MemConfig->RDEQT;
+  Inputs->TrainingEnables.RDAPT      = MemConfig->RDAPT;
+  Inputs->TrainingEnables.WRTC2D     = MemConfig->WRTC2D;
+  Inputs->TrainingEnables.RDTC2D     = MemConfig->RDTC2D;
+  Inputs->TrainingEnables.WRVC2D     = MemConfig->WRVC2D;
+  Inputs->TrainingEnables.RDVC2D     = MemConfig->RDVC2D;
+  Inputs->TrainingEnables.LCT        = MemConfig->LCT;
+  Inputs->TrainingEnables.RTL        = MemConfig->RTL;
+  Inputs->TrainingEnables.TAT        = MemConfig->TAT;
+  Inputs->TrainingEnables.RMT        = MemConfig->RMT;
+  Inputs->TrainingEnables.MEMTST     = MemConfig->MEMTST;
+
+  if (SaPlatformPolicyPpi->Revision >= SA_PLATFORM_POLICY_PPI_REVISION_2) {
+    Inputs->TrainingEnables.DIMMODTT1D = MemConfig->DIMMODTT1D;
+    Inputs->TrainingEnables.WRSRT      = MemConfig->WRSRT;
+    Inputs->TrainingEnables.DIMMRONT   = MemConfig->DIMMRONT;
+  } else {
+    Inputs->TrainingEnables.DIMMODTT1D = 0;
+    Inputs->TrainingEnables.WRSRT      = 0;
+    Inputs->TrainingEnables.DIMMRONT   = 1;
+  }
+
+  if (SaPlatformPolicyPpi->Revision >= SA_PLATFORM_POLICY_PPI_REVISION_4) {
+    Inputs->TrainingEnables.CMDVC = MemConfig->CMDVC;
+    Inputs->PowerDownMode         = MemConfig->PowerDownMode;
+    Inputs->PwdwnIdleCounter      = MemConfig->PwdwnIdleCounter;
+    Inputs->RankInterleave        = MemConfig->RankInterleave;
+    Inputs->EnhancedInterleave    = MemConfig->EnhancedInterleave;
+    Inputs->WeaklockEn            = MemConfig->WeaklockEn;
+    Inputs->EnCmdRate             = MemConfig->EnCmdRate;
+    Inputs->CmdTriStateDis        = MemConfig->CmdTriStateDis;
+  } else {
+    Inputs->TrainingEnables.CMDVC = 1;
+    Inputs->PowerDownMode         = 0xFF;
+    Inputs->PwdwnIdleCounter      = 0x40;
+    Inputs->RankInterleave        = TRUE;
+    Inputs->EnhancedInterleave    = TRUE;
+    Inputs->WeaklockEn            = FALSE;
+    Inputs->EnCmdRate             = 7;
+    Inputs->CmdTriStateDis        = FALSE;
+  }
+
+  if (SaPlatformPolicyPpi->Revision >= SA_PLATFORM_POLICY_PPI_REVISION_5) {
+    Inputs->BClkFrequency = (MemConfig->BClkFrequency < (BCLK_DEFAULT - (10 * 1000 * 1000))) ?
+      BCLK_DEFAULT : ((MemConfig->BClkFrequency / 1000000) * 1000000);
+  } else {
+    Inputs->BClkFrequency = BCLK_DEFAULT;
+  }
+
+  if (SaPlatformPolicyPpi->Revision >= SA_PLATFORM_POLICY_PPI_REVISION_6) {
+    Inputs->TrainingEnables.ALIASCHK  = MemConfig->ALIASCHK;
+  } else {
+    Inputs->TrainingEnables.ALIASCHK  = 1;
+  }
+
+  if (SaPlatformPolicyPpi->Revision >= SA_PLATFORM_POLICY_PPI_REVISION_9) {
+    Inputs->IedSize             = (SaPlatformPolicyPpi->PlatformData->IedSize) >> 20;
+    Inputs->RefreshRate2x       = MemConfig->RefreshRate2x;       // Tells the MRC to enable 2x Refresh.
+    Inputs->ChHashEnable        = MemConfig->ChHashEnable;        // Enale/disable CH HASH support
+    Inputs->ChHashMask          = MemConfig->ChHashMask;          // Addr bits[19:6] to include in Channel XOR function.
+    Inputs->ChHashInterleaveBit = MemConfig->ChHashInterleaveBit; // Valid values are 0 - 3 for BITS 6 -9
+  } else {
+    Inputs->IedSize             = 0x04;
+    Inputs->RefreshRate2x       = FALSE;
+    Inputs->ChHashEnable        = TRUE;       // Enale CH HASH support
+    Inputs->ChHashMask          = 0x30CE;     // Addr bits[19:6] to include in Channel XOR function.
+    Inputs->ChHashInterleaveBit = 1;          // Valid values are 0 - 3 for BITS 6 -9
+  }
+
+  if (SaPlatformPolicyPpi->Revision >= SA_PLATFORM_POLICY_PPI_REVISION_10) {
+    //
+    // Options for Thermal settings
+    //
+    Inputs->ThermalEnables.EnableExtts         = MemConfig->EnableExtts;
+    Inputs->ThermalEnables.EnableCltm          = MemConfig->EnableCltm;
+    Inputs->ThermalEnables.EnableOltm          = MemConfig->EnableOltm;
+    Inputs->ThermalEnables.EnablePwrDn         = MemConfig->EnablePwrDn;
+#ifdef ULT_FLAG
+    if (Inputs->CpuModel == cmHSW_ULT) {
+      Inputs->ThermalEnables.EnablePwrDnLpddr = MemConfig->EnablePwrDnLpddr;
+    }
+#endif // ULT_FLAG
+    Inputs->ThermalEnables.Refresh2X           = MemConfig->Refresh2X;
+    Inputs->ThermalEnables.LpddrThermalSensor  = MemConfig->LpddrThermalSensor; // LPDDR MR4 temperature reads
+    Inputs->ThermalEnables.LockPTMregs         = MemConfig->LockPTMregs;
+    Inputs->ThermalEnables.UserPowerWeightsEn  = MemConfig->UserPowerWeightsEn;
+    Inputs->ThermalEnables.EnergyScaleFact     = MemConfig->EnergyScaleFact;
+    Inputs->ThermalEnables.RaplPwrFl[1]        = MemConfig->RaplPwrFlCh1;
+    Inputs->ThermalEnables.RaplPwrFl[0]        = MemConfig->RaplPwrFlCh0;
+    Inputs->ThermalEnables.RaplLim2Lock        = MemConfig->RaplLim2Lock;
+    Inputs->ThermalEnables.RaplLim2WindX       = MemConfig->RaplLim2WindX;
+    Inputs->ThermalEnables.RaplLim2WindY       = MemConfig->RaplLim2WindY;
+    Inputs->ThermalEnables.RaplLim2Ena         = MemConfig->RaplLim2Ena;
+    Inputs->ThermalEnables.RaplLim2Pwr         = MemConfig->RaplLim2Pwr;
+    Inputs->ThermalEnables.RaplLim1WindX       = MemConfig->RaplLim1WindX;
+    Inputs->ThermalEnables.RaplLim1WindY       = MemConfig->RaplLim1WindY;
+    Inputs->ThermalEnables.RaplLim1Ena         = MemConfig->RaplLim1Ena;
+    Inputs->ThermalEnables.RaplLim1Pwr         = MemConfig->RaplLim1Pwr;
+    Inputs->ThermalEnables.WarmThreshold[0][0] = MemConfig->WarmThresholdCh0Dimm0;
+    Inputs->ThermalEnables.WarmThreshold[0][1] = MemConfig->WarmThresholdCh0Dimm1;
+    Inputs->ThermalEnables.WarmThreshold[1][0] = MemConfig->WarmThresholdCh1Dimm0;
+    Inputs->ThermalEnables.WarmThreshold[1][1] = MemConfig->WarmThresholdCh1Dimm1;
+    Inputs->ThermalEnables.HotThreshold[0][0]  = MemConfig->HotThresholdCh0Dimm0;
+    Inputs->ThermalEnables.HotThreshold[0][1]  = MemConfig->HotThresholdCh0Dimm1;
+    Inputs->ThermalEnables.HotThreshold[1][0]  = MemConfig->HotThresholdCh1Dimm0;
+    Inputs->ThermalEnables.HotThreshold[1][1]  = MemConfig->HotThresholdCh1Dimm1;
+    Inputs->ThermalEnables.WarmBudget[0][0]    = MemConfig->WarmBudgetCh0Dimm0;
+    Inputs->ThermalEnables.WarmBudget[0][1]    = MemConfig->WarmBudgetCh0Dimm1;
+    Inputs->ThermalEnables.WarmBudget[1][0]    = MemConfig->WarmBudgetCh1Dimm0;
+    Inputs->ThermalEnables.WarmBudget[1][1]    = MemConfig->WarmBudgetCh1Dimm1;
+    Inputs->ThermalEnables.HotBudget[0][0]     = MemConfig->HotBudgetCh0Dimm0;
+    Inputs->ThermalEnables.HotBudget[0][1]     = MemConfig->HotBudgetCh0Dimm1;
+    Inputs->ThermalEnables.HotBudget[1][0]     = MemConfig->HotBudgetCh1Dimm0;
+    Inputs->ThermalEnables.HotBudget[1][1]     = MemConfig->HotBudgetCh1Dimm1;
+    Inputs->ThermalEnables.IdleEnergy[0][1]    = MemConfig->IdleEnergyCh0Dimm1;
+    Inputs->ThermalEnables.IdleEnergy[0][0]    = MemConfig->IdleEnergyCh0Dimm0;
+    Inputs->ThermalEnables.IdleEnergy[1][1]    = MemConfig->IdleEnergyCh1Dimm1;
+    Inputs->ThermalEnables.IdleEnergy[1][0]    = MemConfig->IdleEnergyCh1Dimm0;
+    Inputs->ThermalEnables.PdEnergy[0][1]      = MemConfig->PdEnergyCh0Dimm1;
+    Inputs->ThermalEnables.PdEnergy[0][0]      = MemConfig->PdEnergyCh0Dimm0;
+    Inputs->ThermalEnables.PdEnergy[1][1]      = MemConfig->PdEnergyCh1Dimm1;
+    Inputs->ThermalEnables.PdEnergy[1][0]      = MemConfig->PdEnergyCh1Dimm0;
+    Inputs->ThermalEnables.ActEnergy[0][1]     = MemConfig->ActEnergyCh0Dimm1;
+    Inputs->ThermalEnables.ActEnergy[0][0]     = MemConfig->ActEnergyCh0Dimm0;
+    Inputs->ThermalEnables.ActEnergy[1][1]     = MemConfig->ActEnergyCh1Dimm1;
+    Inputs->ThermalEnables.ActEnergy[1][0]     = MemConfig->ActEnergyCh1Dimm0;
+    Inputs->ThermalEnables.RdEnergy[0][1]      = MemConfig->RdEnergyCh0Dimm1;
+    Inputs->ThermalEnables.RdEnergy[0][0]      = MemConfig->RdEnergyCh0Dimm0;
+    Inputs->ThermalEnables.RdEnergy[1][1]      = MemConfig->RdEnergyCh1Dimm1;
+    Inputs->ThermalEnables.RdEnergy[1][0]      = MemConfig->RdEnergyCh1Dimm0;
+    Inputs->ThermalEnables.WrEnergy[0][1]      = MemConfig->WrEnergyCh0Dimm1;
+    Inputs->ThermalEnables.WrEnergy[0][0]      = MemConfig->WrEnergyCh0Dimm0;
+    Inputs->ThermalEnables.WrEnergy[1][1]      = MemConfig->WrEnergyCh1Dimm1;
+    Inputs->ThermalEnables.WrEnergy[1][0]      = MemConfig->WrEnergyCh1Dimm0;
+    Inputs->ThermalEnables.SrefCfgEna          = MemConfig->SrefCfgEna;
+    Inputs->ThermalEnables.SrefCfgIdleTmr      = MemConfig->SrefCfgIdleTmr;
+    Inputs->ThermalEnables.ThrtCkeMinDefeat    = MemConfig->ThrtCkeMinDefeat;
+    Inputs->ThermalEnables.ThrtCkeMinTmr       = MemConfig->ThrtCkeMinTmr;
+#ifdef ULT_FLAG
+    if (Inputs->CpuModel == cmHSW_ULT) {
+      Inputs->ThermalEnables.ThrtCkeMinDefeatLpddr = MemConfig->ThrtCkeMinDefeatLpddr;
+      Inputs->ThermalEnables.ThrtCkeMinTmrLpddr    = MemConfig->ThrtCkeMinTmrLpddr;
+    }
+#endif // ULT_FLAG
+  } else {
+    Inputs->ThermalEnables.EnableExtts           = 0;
+    Inputs->ThermalEnables.EnableCltm            = 0;
+    Inputs->ThermalEnables.EnableOltm            = 0;
+    Inputs->ThermalEnables.EnablePwrDn           = 1;
+#ifdef ULT_FLAG
+    if (Inputs->CpuModel == cmHSW_ULT) {
+      Inputs->ThermalEnables.EnablePwrDnLpddr    = 0;
+    }
+#endif // ULT_FLAG
+    Inputs->ThermalEnables.Refresh2X             = 0;
+    Inputs->ThermalEnables.LpddrThermalSensor    = 1;        // Enable LPDDR MR4 temperature reads
+    Inputs->ThermalEnables.LockPTMregs           = 0;
+    Inputs->ThermalEnables.EnergyScaleFact       = 3;
+    Inputs->ThermalEnables.RaplLim2Lock          = 0;
+    Inputs->ThermalEnables.RaplLim2WindX         = 0;
+    Inputs->ThermalEnables.RaplLim2WindY         = 0;
+    Inputs->ThermalEnables.RaplLim2Ena           = 0;
+    Inputs->ThermalEnables.RaplLim2Pwr           = 0;
+    Inputs->ThermalEnables.RaplLim1WindX         = 0;
+    Inputs->ThermalEnables.RaplLim1WindY         = 0;
+    Inputs->ThermalEnables.RaplLim1Ena           = 0;
+    Inputs->ThermalEnables.RaplLim1Pwr           = 0;
+    for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+      Inputs->ThermalEnables.RaplPwrFl[Channel] = 0;
+      for (Dimm = 0; Dimm < MAX_DIMMS_IN_CHANNEL; Dimm++) {
+        Inputs->ThermalEnables.WarmThreshold[Channel][Dimm] = 0xFF;
+        Inputs->ThermalEnables.HotThreshold[Channel][Dimm]  = 0xFF;
+        Inputs->ThermalEnables.WarmBudget[Channel][Dimm]    = 0xFF;
+        Inputs->ThermalEnables.HotBudget[Channel][Dimm]     = 0xFF;
+        Inputs->ThermalEnables.IdleEnergy[Channel][Dimm]    = 0;
+        Inputs->ThermalEnables.PdEnergy[Channel][Dimm]      = 0;
+        Inputs->ThermalEnables.ActEnergy[Channel][Dimm]     = 0;
+        Inputs->ThermalEnables.RdEnergy[Channel][Dimm]      = 0;
+        Inputs->ThermalEnables.WrEnergy[Channel][Dimm]      = 0;
+      }
+    }
+    Inputs->ThermalEnables.SrefCfgEna            = 1;
+    Inputs->ThermalEnables.SrefCfgIdleTmr        = 0x200;
+    Inputs->ThermalEnables.ThrtCkeMinDefeat      = 0;
+    Inputs->ThermalEnables.ThrtCkeMinTmr         = 0x30;
+#ifdef ULT_FLAG
+    if (Inputs->CpuModel == cmHSW_ULT) {
+      Inputs->ThermalEnables.ThrtCkeMinDefeatLpddr = 1;
+      Inputs->ThermalEnables.ThrtCkeMinTmrLpddr    = 0x40;
+    }
+#endif //ULT_FLAG
+  }
+
+  if (SaPlatformPolicyPpi->Revision >= SA_PLATFORM_POLICY_PPI_REVISION_11) {
+    Inputs->AutoSelfRefreshSupport         = MemConfig->AutoSelfRefreshSupport;
+    Inputs->ExtTemperatureSupport          = MemConfig->ExtTemperatureSupport;
+    Inputs->MaxRttWr                       = MemConfig->MaxRttWr;
+  } else {
+    Inputs->AutoSelfRefreshSupport = TRUE;
+    Inputs->ExtTemperatureSupport  = TRUE;
+    Inputs->MaxRttWr = 0;
+  }
+
+  if (SaPlatformPolicyPpi->Revision >= SA_PLATFORM_POLICY_PPI_REVISION_12) {
+    Inputs->TrainingEnables.RCVENC1D  = MemConfig->RCVENC1D;
+  } else {
+    Inputs->TrainingEnables.RCVENC1D  = 1;
+  }
+
+  Inputs->TrainingEnables.RMC = (SaPlatformPolicyPpi->Revision >= SA_PLATFORM_POLICY_PPI_REVISION_15) ?
+                                  MemConfig->RMC : 1;
+
+  Inputs->MrcMode     = MrcModeFull;
+  Inputs->Iteration   = 0;
+
+  //
+  // Scrambler Suppport.
+  //
+  Inputs->ScramblerEnable = MemConfig->ScramblerSupport;
+
+  //
+  // Remap above 4G Support
+  //
+  Inputs->RemapEnable = MemConfig->RemapEnable;
+
+  // ECC support.
+  Inputs->EccSupport  = MemConfig->EccSupport;
+
+  // RMT BDAT support.
+  Inputs->RmtBdatEnable = MemConfig->RmtBdatEnable;
+
+
+#ifdef ULT_FLAG
+  if (Inputs->CpuModel == cmHSW_ULT) {
+    //
+    // Interleaving mode of DQ/DQS pins - depends on board routing
+    //
+    Inputs->DqPinsInterleaved = MemConfig->DqPinsInterleaved;
+
+    //
+    // DRAM ODT is not used
+    //
+    Inputs->LpddrDramOdt = 0;
+
+    //
+    // Initialize the board-specific CMD/CTL/CLK and DQ/DQS mapping for LPDDR3
+    //
+    MrcOemLpddrBoardMapping (Inputs, SaPlatformPolicyPpi->PlatformData->BoardId);
+  }
+#endif // ULT_FLAG
+
+  // Decide which channels and DIMMs are enabled.
+  for (Controller = 0; Controller < MAX_CONTROLLERS; Controller++) {
+    ControllerIn = &Inputs->Controller[Controller];
+    ControllerIn->ChannelCount = 0;
+    for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+      ChannelIn = &ControllerIn->Channel[Channel];
+      switch (MemConfig->DisableDimmChannel[Channel]) {
+        case 1:
+          ChannelIn->Dimm[0].Status = DIMM_DISABLED;
+          ChannelIn->Dimm[1].Status = DIMM_ENABLED;
+          ChannelIn->Status         = CHANNEL_PRESENT;
+          ControllerIn->ChannelCount++;
+          ChannelIn->DimmCount      = 1;
+          break;
+        case 2:
+          ChannelIn->Dimm[0].Status = DIMM_ENABLED;
+          ChannelIn->Dimm[1].Status = DIMM_DISABLED;
+          ChannelIn->Status         = CHANNEL_PRESENT;
+          ControllerIn->ChannelCount++;
+          ChannelIn->DimmCount      = 1;
+          break;
+        case 3:
+          ChannelIn->Dimm[0].Status = DIMM_DISABLED;
+          ChannelIn->Dimm[1].Status = DIMM_DISABLED;
+          ChannelIn->Status         = CHANNEL_DISABLED;
+          ChannelIn->DimmCount      = 0;
+          break;
+        default:
+          ChannelIn->Dimm[0].Status = DIMM_ENABLED;
+          ChannelIn->Dimm[1].Status = DIMM_ENABLED;
+          ChannelIn->Status         = CHANNEL_PRESENT;
+          ControllerIn->ChannelCount++;
+          ChannelIn->DimmCount      = 2;
+          break;
+      }
+    }
+  }
+
+  //
+  // Get DIMM SpdBaseAddresses.
+  //
+  for (Controller = 0; Controller < MAX_CONTROLLERS; Controller++) {
+    ControllerIn = &Inputs->Controller[Controller];
+    for (Channel = 0;  Channel < MAX_CHANNEL; Channel++) {
+      ChannelIn = &ControllerIn->Channel[Channel];
+      for (Dimm = 0; Dimm < MAX_DIMMS_IN_CHANNEL; Dimm++) {
+        ChannelIn->Dimm[Dimm].SpdAddress =
+          SaPlatformPolicyPpi->PlatformData->SpdAddressTable[(Channel * MAX_DIMMS_IN_CHANNEL) + Dimm];
+          /// @todo Need code to detect disabling of individual DIMMs.
+      }
+    }
+  }
+
+#if (defined MEMORY_DOWN_SUPPORT && (MEMORY_DOWN_SUPPORT > 0))
+  EnableMemoryDown (Inputs, SaPlatformPolicyPpi->PlatformData->BoardId);
+#endif
+
+  switch (BootMode) {
+  case bmWarm:
+    CheckForTimingOverride (Inputs, SaPlatformPolicyPpi);
+    return bmWarm;
+
+  case bmS3:
+    CheckForTimingOverride (Inputs, SaPlatformPolicyPpi);
+    return bmS3;
+
+  case bmFast:
+    //
+    // Read SPD data.
+    //
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "FAST BOOT GetSpdData\n");
+    MrcGetSpdData (BootMode, Inputs);
+    CheckForTimingOverride (Inputs, SaPlatformPolicyPpi);
+    return bmFast;
+
+  default:
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_ERROR, "ERROR: Invalid flow specified, defaulting to cold flow\n");
+    // No break. Note that the boot mode changes to bmCold.
+
+  case bmCold:
+    //
+    // Read SPD data.
+    //
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "COLD BOOT GetSpdData\n");
+    MrcGetSpdData (BootMode, Inputs);
+    CheckForTimingOverride (Inputs, SaPlatformPolicyPpi);
+    break;
+  }
+
+  return bmCold;
+}
+
+/**
+  Check to see if user defined profile is selected and if it is, then copy the
+  timing settings for this profile to the timing override structure. If user
+  defined profile is not selected, then set the timing override structure to 0.
+
+  Note that even though we set timings on a DIMM by DIMM basis, the controller
+  may force DIMM timings to be the same for all DIMMs in a channel.
+
+  @param[in, out] Inputs              - The MRC Input data structure.
+  @param[in]      SaPlatformPolicyPpi - The Peim to Peim interface of SaPlatformPolicy.
+
+  @retval Nothing
+**/
+void
+CheckForTimingOverride (
+  IN OUT MrcInput *const               Inputs,
+  IN     SA_PLATFORM_POLICY_PPI *const SaPlatformPolicyPpi
+  )
+{
+  const MEMORY_CONFIGURATION  *MemConfig;
+  MrcControllerIn             *ControllerIn;
+  MrcChannelIn                *ChannelIn;
+  MrcDimmIn                   *DimmIn;
+  U8                          Controller;
+  U8                          Channel;
+  U8                          Dimm;
+
+  //
+  // Override DIMM timing settings for customer profile setting.
+  //
+  if (Inputs->MemoryProfile == USER_PROFILE) {
+    MemConfig = SaPlatformPolicyPpi->MemConfig;
+    for (Controller = 0; Controller < MAX_CONTROLLERS; Controller++) {
+      ControllerIn = &Inputs->Controller[Controller];
+      for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+        ChannelIn = &ControllerIn->Channel[Channel];
+        for (Dimm = 0; Dimm < MAX_DIMMS_IN_CHANNEL; Dimm++) {
+          DimmIn = &ChannelIn->Dimm[Dimm];
+          DimmIn->Timing.NMode   = MemConfig->NModeSupport;
+          DimmIn->Timing.tCL     = MemConfig->tCL;
+          DimmIn->Timing.tCWL    = MemConfig->tCWL;
+          DimmIn->Timing.tFAW    = MemConfig->tFAW;
+          DimmIn->Timing.tRAS    = MemConfig->tRAS;
+          DimmIn->Timing.tRC     = MemConfig->tRC;
+          DimmIn->Timing.tRCD    = MemConfig->tRCD;
+          DimmIn->Timing.tREFI   = MemConfig->tREFI;
+          DimmIn->Timing.tRFC    = MemConfig->tRFC;
+          DimmIn->Timing.tRP     = MemConfig->tRP;
+          if (SaPlatformPolicyPpi->Revision >= SA_PLATFORM_POLICY_PPI_REVISION_6) {
+            DimmIn->Timing.tRPab = MemConfig->tRPab;
+          } else {
+            DimmIn->Timing.tRPab = 0;
+          }
+          DimmIn->Timing.tRRD    = MemConfig->tRRD;
+          DimmIn->Timing.tRTP    = MemConfig->tRTP;
+          DimmIn->Timing.tWR     = MemConfig->tWR;
+          DimmIn->Timing.tWTR    = MemConfig->tWTR;
+        }
+      }
+    }
+  }
+
+  return;
+}
+
diff --git a/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/MemoryInit.cif b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/MemoryInit.cif
new file mode 100644
index 0000000..2aee05c
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/MemoryInit.cif
@@ -0,0 +1,102 @@
+<component>
+	name = "MemoryInit"
+	category = ModulePart
+	LocalRoot = "ReferenceCode\Chipset\SystemAgent\MemoryInit\Pei"
+	RefName = "MemoryInit"
+[files]
+"MemoryInit.sdl"	
+"MemoryInit.mak"	
+"MemInfoHob.h"	
+"MemoryInit.c"	
+"MemoryInit.dxs"	
+"MemoryInit.h"	
+"MemoryInit.inf"	
+"MrcDebugHook.h"	
+"MrcOemDebugPrint.c"	
+"MrcOemDebugPrint.h"	
+"MrcOemIo.c"	
+"MrcOemIo.h"	
+"MrcOemMemory.c"	
+"MrcOemMemory.h"	
+"MrcOemMmio.c"	
+"MrcOemMmio.h"	
+"MrcOemPlatform.c"	
+"MrcOemPlatform.h"	
+"MrcOemSmbus.c"	
+"MrcOemSmbus.h"	
+"MrcSpdDriver.c"	
+"MrcSpdDriver.h"	
+"Source\Api\MrcApi.h"	
+"Source\Api\MrcBdat.c"	
+"Source\Api\MrcBdat.h"	
+"Source\Api\MrcGeneral.c"	
+"Source\Api\MrcGeneral.h"	
+"Source\Api\MrcMemoryScrub.c"	
+"Source\Api\MrcMemoryScrub.h"	
+"Source\Api\MrcSaveRestore.c"	
+"Source\Api\MrcSaveRestore.h"	
+"Source\Api\MrcStartMemoryConfiguration.c"	
+"Source\Api\MrcStartMemoryConfiguration.h"	
+"Source\Include\McAddress.h"	
+"Source\Include\MrcCommandTraining.h"	
+"Source\Include\MrcCommon.h"	
+"Source\Include\MrcCrosser.h"	
+"Source\Include\MrcDdr3.h"	
+"Source\Include\MrcDdr3Registers.h"	
+"Source\Include\MrcGlobal.h"	
+"Source\Include\MrcIoControl.h"	
+"Source\Include\MrcMcConfiguration.h"	
+"Source\Include\MrcMemoryMap.h"	
+"Source\Include\MrcOem.h"	
+"Source\Include\MrcReset.h"	
+"Source\Include\MrcRmtData.h"	
+"Source\Include\MrcSpdData.h"	
+"Source\Include\MrcTypes.h"	
+"Source\Include\MrcVersion.h"	
+"Source\Include\MrcRegisters\McGdxcbar.h"	
+"Source\Include\MrcRegisters\McIoCkeCtl.h"	
+"Source\Include\MrcRegisters\McIoClk.h"	
+"Source\Include\MrcRegisters\McIoCmd.h"	
+"Source\Include\MrcRegisters\McIoComp.h"	
+"Source\Include\MrcRegisters\McIoData.h"	
+"Source\Include\MrcRegisters\McMain.h"	
+"Source\Include\MrcRegisters\McScramble.h"	
+"Source\Include\MrcRegisters\Msa.h"	
+"Source\Include\MrcRegisters\Pci000.h"	
+"Source\McConfiguration\MrcAddressDecodeConfiguration.c"	
+"Source\McConfiguration\MrcAddressDecodeConfiguration.h"	
+"Source\McConfiguration\MrcPowerModes.c"	
+"Source\McConfiguration\MrcPowerModes.h"	
+"Source\McConfiguration\MrcRefreshConfiguration.c"	
+"Source\McConfiguration\MrcRefreshConfiguration.h"	
+"Source\McConfiguration\MrcSchedulerParameters.c"	
+"Source\McConfiguration\MrcSchedulerParameters.h"	
+"Source\McConfiguration\MrcTimingConfiguration.c"	
+"Source\McConfiguration\MrcTimingConfiguration.h"	
+"Source\ReadTraining\MrcReadDqDqs.c"	
+"Source\ReadTraining\MrcReadDqDqs.h"	
+"Source\ReadTraining\MrcReadReceiveEnable.c"	
+"Source\ReadTraining\MrcReadReceiveEnable.h"	
+"Source\Services\MrcCommandTraining.c"	
+"Source\Services\MrcCommon.c"	
+"Source\Services\MrcCrosser.c"	
+"Source\Services\MrcDdr3.c"	
+"Source\Services\MrcIoControl.c"	
+"Source\Services\MrcMcConfiguration.c"	
+"Source\Services\MrcMemoryMap.c"	
+"Source\Services\MrcReset.c"	
+"Source\SpdProcessing\MrcSpdProcessing.c"	
+"Source\SpdProcessing\MrcSpdProcessing.h"	
+"Source\WriteTraining\MrcWriteDqDqs.c"	
+"Source\WriteTraining\MrcWriteDqDqs.h"	
+"Source\WriteTraining\MrcWriteLeveling.c"	
+"Source\WriteTraining\MrcWriteLeveling.h"	
+"MrcSsaServices.c"	
+"MrcSsaServices.h"	
+"SsaCallbackPeim.h"	
+"MrcOemAddrDecode.c"	
+"MrcOemAddrDecode.h"	
+"Source\AddrDecode\MrcHswMcAddrDecode.c"	
+"Source\AddrDecode\MrcHswMcAddrDecode.h"	
+"Source\Include\MrcRegisters\PttHciRegs.h"	
+<endComponent>
diff --git a/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/MemoryInit.dxs b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/MemoryInit.dxs
new file mode 100644
index 0000000..7716fdd
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/MemoryInit.dxs
@@ -0,0 +1,78 @@
+/**
+
+Copyright (c)  2005-2013 Intel Corporation. All rights reserved
+This software and associated documentation (if any) is furnished
+under a license and may only be used or copied in accordance
+with the terms of the license. Except as permitted by such
+license, no part of this software or documentation may be
+reproduced, stored in a retrieval system, or transmitted in any
+form or by any means without the express written consent of
+Intel Corporation.
+
+
+Module Name:
+
+  MemInit.dxs
+
+Abstract:
+
+  Dependency expression file for Memory Init PEIM.
+  
+**/  
+
+//
+// Common for R8 and R9 codebase
+//
+#include "AutoGen.h"
+#include "PeimDepex.h"
+
+//
+// BUILD_WITH_GLUELIB and BUILD_WITH_EDKII_GLUE_LIB are both "defined" in R8 codebase;
+// BUILD_WITH_EDKII_GLUE_LIB is defined in Edk-Dev-Snapshot-20070228 and later version
+// BUILD_WITH_GLUELIB and BUILD_WITH_EDKII_GLUE_LIB are "not defined" in R9 codebase.
+//
+#if defined (BUILD_WITH_GLUELIB) || defined (BUILD_WITH_EDKII_GLUE_LIB)
+#include "EfiDepex.h"
+
+#include EFI_PPI_DEPENDENCY (PlatformMemoryRange)
+#include EFI_PPI_DEPENDENCY (BaseMemoryTest)
+#include EFI_PPI_DEPENDENCY (Variable)
+#include EFI_PPI_DEPENDENCY (PlatformMemorySize)
+#include EFI_PPI_DEPENDENCY (Smbus)
+#include EFI_PPI_DEPENDENCY (SaPlatformPolicy)
+#include EFI_PPI_DEPENDENCY (CpuPlatformPolicy)
+#include EFI_PPI_DEPENDENCY (SaPeiInit)
+#include EFI_PPI_CONSUMER   (BootMode)
+#include EFI_PPI_DEPENDENCY (Wdt)
+#include EFI_PPI_DEPENDENCY (PchMeUma)
+
+#ifdef TXT_SUPPORT_FLAG
+#include EFI_PPI_DEFINITION (TxtMemoryUnlocked)
+#include EFI_PPI_DEPENDENCY (Stall)
+// #include "ppi\TcgPeiDone.h"
+#endif // TXT_SUPPORT_FLAG
+#ifdef RAPID_START_FLAG
+#include EFI_PPI_DEPENDENCY (RapidStart)
+#endif
+#endif
+
+DEPENDENCY_START
+#ifdef TXT_SUPPORT_FLAG
+  PEI_TXT_MEMORY_UNLOCKED_PPI_GUID        AND
+  PEI_STALL_PPI_GUID                      AND
+#endif // TXT_SUPPORT_FLAG
+  PEI_PLATFORM_MEMORY_RANGE_PPI_GUID      AND
+  PEI_BASE_MEMORY_TEST_GUID               AND  
+  PEI_MASTER_BOOT_MODE_PEIM_PPI           AND
+  PEI_READ_ONLY_VARIABLE_ACCESS_PPI_GUID  AND
+  PEI_PLATFORM_MEMORY_SIZE_PPI_GUID       AND
+  PEI_SMBUS_PPI_GUID                      AND
+  SA_PLATFORM_POLICY_PPI_GUID             AND
+  PEI_CPU_PLATFORM_POLICY_PPI_GUID        AND
+  WDT_PPI_GUID                            AND
+  PCH_ME_UMA_PPI_GUID                     AND
+#ifdef RAPID_START_FLAG
+  RAPID_START_PPI_GUID                    AND
+#endif
+  SA_PEI_INIT_PPI_GUID
+DEPENDENCY_END
diff --git a/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/MemoryInit.h b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/MemoryInit.h
new file mode 100644
index 0000000..f8071fc
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/MemoryInit.h
@@ -0,0 +1,388 @@
+/** @file
+  Memory Initialization PEIM.
+
+@copyright
+  Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved.
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement
+
+**/
+#ifndef _MemoryInit_h_
+#define _MemoryInit_h_
+
+#include "EdkIIGluePeim.h"
+#include EFI_PPI_DEPENDENCY (SaPlatformPolicy)
+#include "MemInfoHob.h"
+///
+/// These header files are from MRC
+///
+#include "MrcTypes.h"
+#include "MrcApi.h"
+#include "MrcGlobal.h"
+#include "MrcGeneral.h"
+#include "MrcStartMemoryConfiguration.h"
+
+#include EFI_GUID_DEFINITION (SaDataHob)
+#ifdef SSA_FLAG
+#include "SsaCallbackPeim.h"
+#endif // SSA_FLAG
+
+
+///
+/// SMRAM range definitions
+///
+#define MC_ABSEG_HSEG_PHYSICAL_START  0x000A0000
+#define MC_ABSEG_HSEG_LENGTH          0x00020000
+#define MC_ABSEG_CPU_START            0x000A0000
+#define MC_HSEG_CPU_START             0xFEDA0000
+
+///
+/// See NonDistributed\ReferenceCode\Txt\BiosAcm\Txt.h
+///
+#define TXT_PUBLIC_BASE 0xFED30000
+
+///
+/// Maximum number of memory ranges supported by the memory controller
+///
+#define MAX_RANGES  (SA_MC_MAX_ROWS + 8)
+#define MEM_EQU_4GB 0x100000000ULL
+
+///
+/// TPM Status and Time-out
+///
+#define TPM_STATUS_REG_ADDRESS  0xfed40000
+#define TPM_TIME_OUT            750
+
+#define PLATFORM_ID_MOBILE      1
+
+///
+/// Memory range types
+///
+typedef enum {
+  DualChannelDdrMainMemory,
+  DualChannelDdrSmramCacheable,
+  DualChannelDdrSmramNonCacheable,
+  DualChannelDdrGraphicsMemoryCacheable,
+  DualChannelDdrGraphicsMemoryNonCacheable,
+  DualChannelDdrReservedMemory,
+  DualChannelDdrMaxMemoryRangeType
+} PEI_DUAL_CHANNEL_DDR_MEMORY_RANGE_TYPE;
+
+///
+/// Memory map range information
+///
+#pragma pack(push, 1)
+typedef struct {
+  UINT8                                   RowNumber;
+  EFI_PHYSICAL_ADDRESS                    PhysicalAddress;
+  EFI_PHYSICAL_ADDRESS                    CpuAddress;
+  EFI_PHYSICAL_ADDRESS                    RangeLength;
+  PEI_DUAL_CHANNEL_DDR_MEMORY_RANGE_TYPE  Type;
+} PEI_DUAL_CHANNEL_DDR_MEMORY_MAP_RANGE;
+#pragma pack(pop)
+
+/**
+@brief
+  Main starting point for system memory initialization.
+    1. Get SysBootMode and MrcBootMode
+    2. Locate SaPlatformPolicy PPI
+    3. Locate S3DataPtr from SaPlatformPolicy.
+    4. SaveDataValid := TRUE if S3DataPtr is not NULL.
+    5. If SysBootMode is BOOT_ON_S3_RESUME and S3Data is not valid:
+    -> ASSERT.
+    6. If MrcBootMode is Warm boot, but S3 data is not valid :
+    -> change MrcBootMode to Cold boot.
+    7. If MrcBootMode is Cold boot:
+    -> Run MRC code
+    -> Save S3 Restore Data
+    Else
+    -> Run MRC_S3Resume
+    8. Run MRC_Done().
+    9. Install EFI memory HOBs.
+
+  @param[in] FfsHeader        - Not used.
+  @param[in] PeiServices      - General purpose services available to every PEIM.
+
+  @retval EFI_SUCCESS      - Memory initialization completed successfully.
+  @retval EFI_NOT_READY    - Cannot locate SA Platform Policy.
+  @retval EFI_NOT_FOUND    - No S3 data in S3 Boot Mode.
+  @retval EFI_DEVICE_ERROR - MemoryInit failed or IOSAV Memory test failed.
+**/
+extern
+EFI_STATUS
+PeimMemoryInit (
+  IN EFI_FFS_FILE_HEADER *FfsHeader,
+  IN EFI_PEI_SERVICES    **PeiServices
+  );
+
+
+/**
+@brief
+  This function installs memory for all paths except S3 resume.
+
+  @param[in] Inputs      - MRC input structure.
+  @param[in] PeiServices - PEI Services table.
+  @param[in] SysBootMode - The specific boot path that is being followed.
+
+  @retval EFI_SUCCESS          The function completed successfully.
+  @retval EFI_OUT_OF_RESOURCES Out of Resources.
+**/
+extern
+EFI_STATUS
+InstallEfiMemory (
+  IN const MrcInput *const Inputs,
+  IN EFI_PEI_SERVICES      **PeiServices,
+  IN EFI_BOOT_MODE         SysBootMode
+  );
+
+/**
+@brief
+  This function installs memory for the S3 resume path.
+
+  @param[in] Inputs           - Mrc input data structure
+  @param[in] PeiServices      - PEI services table.
+  @param[in] VariableServices - Pointer to EFI Variable PPI
+
+  @retval EFI_SUCCESS          - The function completed successfully.
+  @retval EFI_OUT_OF_RESOURCES - Out of Resources.
+**/
+extern
+EFI_STATUS
+InstallS3Memory (
+  IN const MrcInput *const      Inputs,
+  IN EFI_PEI_SERVICES           **PeiServices,
+  IN PEI_READ_ONLY_VARIABLE_PPI *VariableServices
+);
+
+/**
+@brief
+  Determine the memory size desired based on HOB memory information.
+
+  @param[in]      PeiServices - PEI Services table.
+  @param[in, out] Size        - The memory size to return.
+
+  @retval Nothing.
+**/
+extern
+void
+RetrieveRequiredMemorySize (
+  IN  EFI_PEI_SERVICES **PeiServices,
+  OUT UINTN            *Size
+  );
+
+/**
+@brief
+  Determine the Total DPR memory size needed based on the DPR directory in the SA Data HOB.
+
+  @param[in]      PeiServices - PEI Services table.
+  @param[in, out] Size        - The memory size in MB to return.
+
+  @retval Nothing.
+**/
+extern
+void
+CalculateTotalDprMemorySize (
+  IN     EFI_PEI_SERVICES  **PeiServices,
+  IN OUT UINT8             *Size
+  );
+
+/**
+@brief
+  Calculates the bases for each technology consuming the DPR region
+  and updates the SA Data HOB with the appropriate values in the Dpr
+  directory
+
+  @param[in] PeiServices    - PEI Services table.
+  @param[in] Base           - The memory base to return.
+  @param[in] TotalDprSizeMB - The total DPR size in MB
+
+  @retval Nothing.
+**/
+extern
+VOID
+UpdateDprHobInfo (
+  IN EFI_PEI_SERVICES      **PeiServices,
+  IN EFI_PHYSICAL_ADDRESS  Base,
+  IN UINT8                 TotalDprSizeMB
+  );
+
+/**
+@brief
+  Determine the memory size desired by GDXC
+
+  @param[in]      PeiServices - PEI Services table.
+  @param[in, out] MotSize     - The MOT memory size
+  @param[in, out] GdxcSize    - The GDXC memory size
+
+  @retval Nothing.
+**/
+extern
+void
+RetrieveGdxcMemorySize (
+  IN  EFI_PEI_SERVICES **PeiServices,
+  OUT UINT64            *MotSize,
+  OUT UINT64            *GdxcSize
+  );
+
+/**
+@brief
+  This function returns the memory ranges to be enabled, along with information
+  describing how the range should be used. The MemoryMap buffer will be filled in and
+  NumRanges will contain the actual number of memory ranges that are to be enabled.
+
+  @param[in]      PeiServices - PEI Services Table.
+  @param[in, out] MemoryMap   - Buffer to record details of the memory ranges to be enabled.
+  @param[in, out] NumRanges   - On input, this contains the maximum number of memory ranges that
+                                can be described in the MemoryMap buffer.
+
+  @retval EFI_SUCCESS          - The function completed successfully.
+  @retval EFI_BUFFER_TOO_SMALL - The specified number of ranges is too large.
+**/
+extern
+EFI_STATUS
+GetMemoryMap (
+  IN     EFI_PEI_SERVICES                      **PeiServices,
+  IN OUT PEI_DUAL_CHANNEL_DDR_MEMORY_MAP_RANGE *MemoryMap,
+  IN OUT UINT8                                 *NumRanges
+  );
+
+/**
+@brief
+  This function returns a pointer to the allocated hand off buffer.
+
+  @param[in]      PeiServices - A pointer to the EFI PEI services table
+  @param[in, out] Hob         - A pointer to where to store the pointer to the allocated data buffer.
+  @param[in]      Size        - The size of the buffer to get.
+
+  @retval EFI_SUCCESS - Hob is successfully built.
+  @retval Others      - Error occured while creating the Hob.
+**/
+extern
+EFI_STATUS
+MrcGetHobForDataStorage (
+  IN     EFI_PEI_SERVICES       **PeiServices,
+  IN OUT HOB_SAVE_MEMORY_DATA   **Hob,
+  IN     UINT16                 BlockSize
+  );
+
+/**
+@brief
+  A small memory test to quickly point out severe memory issues.
+
+  @param[in] Inputs - Pointer to the MRC Input data structure
+
+  @retval mrcFail on failure, otherwise mrcSuccess.
+**/
+extern
+MrcStatus
+BasicMemoryTest (
+  IN const MrcInput *const Inputs
+  );
+
+#ifndef TXT_SUPPORT_FLAG
+/**
+@brief
+  Determines whether or not the platform has executed a TXT launch by
+  examining the TPM Establishment bit.
+
+  @param[in] PeiServices - General purpose services available to every PEIM.
+
+  @retval TRUE        - If the TPM establishment bit is asserted.
+  @retval FALSE       - If the TPM establishment bit is unasserted.
+**/
+extern
+BOOLEAN
+IsEstablishmentBitAsserted (
+  IN EFI_PEI_SERVICES **PeiServices
+  );
+
+/**
+@brief
+  Unlock memory when security is set and TxT is not enabled.
+
+  @param[in] MrcData     - Mrc global data.
+  @param[in] PeiServices - PEI Services Table.
+
+  @retval Nothing
+**/
+extern
+void
+UnlockMemory (
+  IN const MrcParameters *const MrcData,
+  IN EFI_PEI_SERVICES           **PeiServices
+  );
+#endif /// TXT_SUPPORT_FLAG
+/**
+@brief
+  Determine whether a cold reset of the platform is required.
+  Note that the memory configuration saved data must be valid.
+
+  @param[in] MrcData             - The MRC "global data" area.
+  @param[in] SaPlatformPolicyPpi - SA Platform Policy structure.
+
+  @retval TRUE if cold reset is required, otherwise returns FALSE.
+**/
+extern
+BOOLEAN
+ColdBootRequired (
+  IN const MrcParameters *const MrcData,
+  IN SA_PLATFORM_POLICY_PPI     *SaPlatformPolicyPpi
+  );
+
+/**
+@brief
+  Set up the MRC input data structure.
+
+  @param[in]  SysBootMode         - Boot mode of the system.
+  @param[in]  BootMode            - Boot mode of the Mrc.
+  @param[out] Inputs              - Pointer to the Mrc Input data structure.
+  @param[in]  PeiServices         - PEI Services Table.
+  @param[in]  SaPlatformPolicyPpi - SA Platform Policy structure.
+
+  @retval Always returns mrcSuccess.
+**/
+extern
+MrcBootMode
+MrcSetupMrcData (
+  IN  const EFI_BOOT_MODE           SysBootMode,
+  IN  const MrcBootMode             BootMode,
+  OUT MrcInput *const               Inputs,
+  IN  EFI_PEI_SERVICES **const      PeiServices,
+  IN  SA_PLATFORM_POLICY_PPI *const SaPlatformPolicyPpi
+  );
+
+/**
+@brief
+  Check to see if user defined profile is selected and if it is, then copy the
+  timing settings for this profile to the timing override structure. If user
+  defined profile is not selected, then set the timing override structure to 0.
+
+  Note that even though we set timings on a DIMM by DIMM basis, the controller
+  may force DIMM timings to be the same for all DIMMs in a channel.
+
+  @param[in, out] Inputs              - The MRC Input data structure.
+  @param[in]      SaPlatformPolicyPpi - The Peim to Peim interface of SaPlatformPolicy.
+
+  @retval Nothing.
+**/
+extern
+void
+CheckForTimingOverride (
+  IN OUT MrcInput *const               Inputs,
+  IN     SA_PLATFORM_POLICY_PPI *const SaPlatformPolicyPpi
+  );
+
+
+#endif
diff --git a/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/MemoryInit.inf b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/MemoryInit.inf
new file mode 100644
index 0000000..3ef88b6
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/MemoryInit.inf
@@ -0,0 +1,234 @@
+## @file
+#  Component description file for MemoryInit
+#
+#@copyright
+#  Copyright (c)  1999 - 2014 Intel Corporation. All rights reserved
+#  This software and associated documentation (if any) is furnished
+#  under a license and may only be used or copied in accordance
+#  with the terms of the license. Except as permitted by such
+#  license, no part of this software or documentation may be
+#  reproduced, stored in a retrieval system, or transmitted in any
+#  form or by any means without the express written consent of
+#  Intel Corporation.
+#
+#  This file contains a 'Sample Driver' and is licensed as such
+#  under the terms of your license agreement with Intel or your
+#  vendor.  This file may be modified by the user, subject to
+#  the additional terms of the license agreement
+#
+
+
+[defines]
+BASE_NAME            = MemoryInit
+FILE_GUID            = 3B42EF57-16D3-44CB-8632-9FDB06B41451
+
+COMPONENT_TYPE       = PE32_PEIM
+
+[sources.common]
+  MrcSsaServices.c
+  MrcSsaServices.h
+  MemInfoHob.h
+  MemoryInit.c
+  MemoryInit.h
+  MrcDebugHook.h
+  MrcOemAddrDecode.c
+  MrcOemAddrDecode.h
+  MrcOemDebugPrint.c
+  MrcOemDebugPrint.h
+  MrcOemIo.c
+  MrcOemIo.h
+  MrcOemMemory.c
+  MrcOemMemory.h
+  MrcOemMmio.c
+  MrcOemMmio.h
+  MrcOemPlatform.c
+  MrcOemPlatform.h
+  MrcOemSmbus.c
+  MrcOemSmbus.h
+  MrcSpdDriver.c
+  MrcSpdDriver.h
+  Source/AddrDecode/MrcHswMcAddrDecode.c
+  Source/AddrDecode/MrcHswMcAddrDecode.h
+  Source/Api/MrcApi.h
+  Source/Api/MrcBdat.c
+  Source/Api/MrcBdat.h
+  Source/Api/MrcGeneral.c
+  Source/Api/MrcGeneral.h
+  Source/Api/MrcMemoryScrub.c
+  Source/Api/MrcMemoryScrub.h
+  Source/Api/MrcSaveRestore.c
+  Source/Api/MrcSaveRestore.h
+  Source/Api/MrcStartMemoryConfiguration.c
+  Source/Api/MrcStartMemoryConfiguration.h
+  Source/Include/McAddress.h
+  Source/Include/MrcCommandTraining.h
+  Source/Include/MrcCommon.h
+  Source/Include/MrcCrosser.h
+  Source/Include/MrcDdr3.h
+  Source/Include/MrcDdr3Registers.h
+  Source/Include/MrcIoControl.h
+  Source/Include/MrcMcConfiguration.h
+  Source/Include/MrcMemoryMap.h
+  Source/Include/MrcOem.h
+  Source/Include/MrcReset.h
+  Source/Include/MrcRmtData.h
+  Source/Include/MrcSpdData.h
+  Source/Include/MrcTypes.h
+  Source/Include/MrcVersion.h
+  Source/Include/MrcRegisters/McGdxcbar.h
+  Source/Include/MrcRegisters/McIoCkeCtl.h
+  Source/Include/MrcRegisters/McIoClk.h
+  Source/Include/MrcRegisters/McIoCmd.h
+  Source/Include/MrcRegisters/McIoComp.h
+  Source/Include/MrcRegisters/McIoData.h
+  Source/Include/MrcRegisters/McMain.h
+  Source/Include/MrcRegisters/McScramble.h
+  Source/Include/MrcRegisters/Pci000.h
+  Source/McConfiguration/MrcAddressDecodeConfiguration.c
+  Source/McConfiguration/MrcAddressDecodeConfiguration.h
+  Source/McConfiguration/MrcPowerModes.c
+  Source/McConfiguration/MrcPowerModes.h
+  Source/McConfiguration/MrcRefreshConfiguration.c
+  Source/McConfiguration/MrcRefreshConfiguration.h
+  Source/McConfiguration/MrcSchedulerParameters.c
+  Source/McConfiguration/MrcSchedulerParameters.h
+  Source/McConfiguration/MrcTimingConfiguration.c
+  Source/McConfiguration/MrcTimingConfiguration.h
+  Source/ReadTraining/MrcReadDqDqs.c
+  Source/ReadTraining/MrcReadDqDqs.h
+  Source/ReadTraining/MrcReadReceiveEnable.c
+  Source/ReadTraining/MrcReadReceiveEnable.h
+  Source/Services/MrcCommandTraining.c
+  Source/Services/MrcCommon.c
+  Source/Services/MrcCrosser.c
+  Source/Services/MrcDdr3.c
+  Source/Services/MrcIoControl.c
+  Source/Services/MrcMcConfiguration.c
+  Source/Services/MrcMemoryMap.c
+  Source/Services/MrcReset.c
+  Source/SpdProcessing/MrcSpdProcessing.c
+  Source/SpdProcessing/MrcSpdProcessing.h
+  Source/WriteTraining/MrcWriteDqDqs.c
+  Source/WriteTraining/MrcWriteDqDqs.h
+  Source/WriteTraining/MrcWriteLeveling.c
+  Source/WriteTraining/MrcWriteLeveling.h
+#
+# Edk II Glue Driver Entry Point
+#
+  EdkIIGluePeimEntryPoint.c
+
+[includes.common]
+  .
+  $(EFI_SOURCE)
+  $(EFI_SOURCE)/Include
+  $(EFI_SOURCE)/$(PROJECT_SA_ROOT)/
+  $(EFI_SOURCE)/$(PROJECT_SA_ROOT)/Include
+  $(EFI_SOURCE)/$(PROJECT_SA_ROOT)/MemoryInit/Pei/Source/AddrDecode
+  $(EFI_SOURCE)/$(PROJECT_SA_ROOT)/MemoryInit/Pei/Source/Api
+  $(EFI_SOURCE)/$(PROJECT_SA_ROOT)/MemoryInit/Pei/Source/Include
+  $(EFI_SOURCE)/$(PROJECT_SA_ROOT)/MemoryInit/Pei/Source/Include/MrcRegisters
+  $(EFI_SOURCE)/$(PROJECT_SA_ROOT)/MemoryInit/Pei/Source/McConfiguration
+  $(EFI_SOURCE)/$(PROJECT_SA_ROOT)/MemoryInit/Pei/Source/ReadTraining
+  $(EFI_SOURCE)/$(PROJECT_SA_ROOT)/MemoryInit/Pei/Source/Services
+  $(EFI_SOURCE)/$(PROJECT_SA_ROOT)/MemoryInit/Pei/Source/SpdProcessing
+  $(EFI_SOURCE)/$(PROJECT_SA_ROOT)/MemoryInit/Pei/Source/WriteTraining
+  $(EFI_SOURCE)/$(PROJECT_SA_ROOT)/Ppi/SsaPeiInit
+  $(EFI_SOURCE)/$(PROJECT_ME_ROOT)
+  $(EFI_SOURCE)/$(PROJECT_ME_ROOT)/PchMeUma
+  $(EFI_SOURCE)/$(PROJECT_PCH_ROOT)
+  $(EFI_SOURCE)/$(PROJECT_PCH_ROOT)/Include
+  $(EFI_SOURCE)/$(PROJECT_PCH_ROOT)/Include/PchRegs
+  $(EFI_SOURCE)/$(PROJECT_CPU_ROOT)
+  $(EFI_SOURCE)/$(PROJECT_CPU_ROOT)/Include
+  $(EFI_SOURCE)/$(PROJECT_CPU_ROOT)/Include/Library
+#
+# Uncomment the following RapidStart include directories if RapidStart is supported
+#
+  $(EFI_SOURCE)/$(PROJECT_RAPID_START_ROOT)
+  $(EFI_SOURCE)/$(PROJECT_RAPID_START_ROOT)/Include
+  $(EDK_SOURCE)/Foundation
+  $(EDK_SOURCE)/Foundation/Cpu/Pentium/Include
+  $(EDK_SOURCE)/Foundation/Framework
+  $(EDK_SOURCE)/Foundation/Efi
+  $(EDK_SOURCE)/Foundation/Include
+  $(EDK_SOURCE)/Foundation/Efi/Include
+  $(EDK_SOURCE)/Foundation/Framework/Include
+  $(EDK_SOURCE)/Foundation/Library/EdkIIGlueLib/Include
+  $(EDK_SOURCE)/Foundation/Library/EdkIIGlueLib/Include/Library
+  $(EDK_SOURCE)/Foundation/Library/EdkIIGlueLib/Include/Common
+  $(EDK_SOURCE)/Foundation/Library/EdkIIGlueLib/Include/Pcd
+  $(EDK_SOURCE)/Foundation/Include/IndustryStandard
+  $(EFI_SOURCE)
+  $(EDK_SOURCE)/Foundation/Include/Pei
+  $(EDK_SOURCE)/Foundation/Library/Pei/Include
+  $(EDK_SOURCE)/Foundation/Library/Dxe/Include
+  $(EDK_SOURCE)/Foundation/Protocol/DebugMask
+
+
+#
+# Typically the sample code referenced will be available in the code base already
+# So keep this include at the end to defer to the source base definition
+# and only use the sample code definition if source base does not include these files.
+#
+  $(EFI_SOURCE)/$(PROJECT_SA_ROOT)/SampleCode/
+  $(EFI_SOURCE)/$(PROJECT_SA_ROOT)/SampleCode/Ppi
+#
+# Uncomment the following RapidStart include directories if RapidStart is supported
+#
+  $(EFI_SOURCE)/$(PROJECT_RAPID_START_ROOT)/Samplecode/Library/RapidStartCommonLib
+  $(EFI_SOURCE)/$(PROJECT_RAPID_START_ROOT)/Samplecode/Library/RapidStartPlatformLib/Pei
+
+
+[libraries.common]
+  EdkFrameworkGuidLib
+  EdkFrameworkPpiLib
+  EdkPpiLib
+  EdkGuidLib
+  SAGuidLib
+  $(PROJECT_SA_FAMILY)PpiLib
+  CpuPpiLib
+  CpuGuidLib
+  PeiLib
+  $(PROJECT_SA_FAMILY)SampleCodePpiLib
+  $(PROJECT_PCH_FAMILY)PpiLib
+  MeLibPpi
+  EfiGuidLib
+  EdkIIGlueBaseLib
+  EdkIIGlueBaseIoLibIntrinsic
+  EdkIIGluePeiDebugLibReportStatusCode
+  EdkIIGluePeiReportStatusCodeLib
+  EdkIIGluePeiServicesLib
+  EdkIIGluePeiMemoryAllocationLib
+  EdkIIGluePeiHobLib
+  EdkIIGluePeiSmbusLib
+  PchPlatformLib
+  EdkIIGlueBasePciLibPciExpress
+  EdkIIGlueBasePrintLib
+#
+# Uncomment the following RapidStart libraries if RapidStart is supported
+#
+#  RapidStartCommonLib
+#  RapidStartPpiLib
+#  RapidStartPeiLib
+  CpuPlatformLib
+  TxtLib
+
+[nmake.common]
+  IMAGE_ENTRY_POINT = _ModuleEntryPoint
+  DPX_SOURCE        = MemoryInit.dxs
+#EcpOverride: add /GL- and macro MDE_CPU_IA32
+  C_FLAGS = $(C_FLAGS) /Oi /Gs65536 /Zi /Gm -DMDE_CPU_IA32
+  C_FLAGS = $(C_FLAGS) -D __EDKII_GLUE_MODULE_ENTRY_POINT__=PeimMemoryInit\
+                       -D __EDKII_GLUE_BASE_LIB__ \
+                       -D __EDKII_GLUE_BASE_IO_LIB_INTRINSIC__ \
+                       -D __EDKII_GLUE_PEI_DEBUG_LIB_REPORT_STATUS_CODE__ \
+                       -D __EDKII_GLUE_PEI_REPORT_STATUS_CODE_LIB__ \
+                       -D __EDKII_GLUE_PEI_SERVICES_LIB__ \
+                       -D __EDKII_GLUE_PEI_MEMORY_ALLOCATION_LIB__ \
+                       -D __EDKII_GLUE_PEI_HOB_LIB__ \
+                       -D __EDKII_GLUE_PEI_SMBUS_LIB__ \
+                       -D __EDKII_GLUE_BASE_PCI_LIB_PCI_EXPRESS__ \
+                       -DMEMORY_DOWN_SUPPORT=1
+# Uncomment the following RapidStart flags if RapidStart is supported
+# C_FLAGS = $(C_FLAGS) -DRAPID_START_FLAG
+# C_FLAGS = $(C_FLAGS) -DRAPID_START_NO_SMRAM_INTEGRITY_CHECK
diff --git a/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/MemoryInit.mak b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/MemoryInit.mak
new file mode 100644
index 0000000..8b79a2a
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/MemoryInit.mak
@@ -0,0 +1,110 @@
+# MAK file for the ModulePart:MemoryInit
+
+all: $(BUILD_DIR)\MemoryInit.mak MemoryInitBin
+
+$(BUILD_DIR)\MemoryInit.mak : $(MemoryInit_DIR)\$(@B).cif $(MemoryInit_DIR)\$(@B).mak $(BUILD_RULES)
+    $(CIF2MAK) $(MemoryInit_DIR)\$(@B).cif $(CIF2MAK_DEFAULTS)
+
+MemoryInitBin_INCLUDES=\
+    $(PROJECT_CPU_INCLUDES) \
+    /I$(NB_BOARD_DIR)\
+    /I$(MemoryInit_DIR) \
+    /I$(MemoryInit_DIR)\Source\Include \
+    /I$(MemoryInit_DIR)\Source\Include\MrcRegisters \
+    /I$(MemoryInit_DIR)\Source\AddrDecode \
+    /I$(MemoryInit_DIR)\Source\Api \
+    /I$(INTEL_SYSTEM_AGENT_DIR)\SampleCode \
+    /I$(MemoryInit_DIR)\Source\ReadTraining \
+    /I$(MemoryInit_DIR)\Source\WriteTraining \
+    /I$(MemoryInit_DIR)\Source\SpdProcessing \
+    /I$(MemoryInit_DIR)\Source\McConfiguration \
+    /I$(MemoryInit_DIR)\Source\AggressiveTraining \
+    /I$(INTEL_SA_PPI_LIB_DIR)\EviPeiInit \
+    /I$(AcpiPlatform_DIR)\Include \
+    /I$(PROJECT_DIR)\Include \
+    $(PchMeUma_INCLUDES) \
+    $(ME_INCLUDES) \
+    $(INTEL_MCH_INCLUDES) \
+    $(INTEL_PCH_INCLUDES) \
+    $(EDK_INCLUDES) \
+    $(TXT_INCLUDES) \
+    $(EdkIIGlueLib_INCLUDES) \
+    $(RAPIDSTART_INCLUDES) \
+    /I$(RapidStartCommonLib_DIR) \
+
+MemoryInitBin_LIBS=\
+    $(AMIPEILIB) \
+    $(CPUIA32LIB) \
+    $(IntelSaSampleCodePpiLib_LIB) \
+    $(EDKPPILIB) \
+    $(EDKGUIDLIB) \
+    $(INTEL_SA_PPI_LIB) \
+    $(MeLibPpi_LIB)\
+    $(EdkIIGlueBaseLib_LIB)\
+    $(EdkIIGlueBaseLibIA32_LIB)\
+    $(EdkIIGlueBaseIoLibIntrinsic_LIB) \
+    $(EdkIIGluePeiDebugLibReportStatusCode_LIB) \
+    $(EdkIIGluePeiReportStatusCodeLib_LIB) \
+    $(EdkIIGluePeiServicesLib_LIB) \
+    $(EdkIIGluePeiMemoryAllocationLib_LIB) \
+    $(EdkIIGluePeiHobLib_LIB) \
+    $(EdkIIGluePeiSmbusLib_LIB) \
+    $(PEILIB)\
+    $(RapidStartPpiLib_LIB)\
+    $(RapidStartPeiLib_LIB)\
+    $(RapidStartCommonPeiLib_LIB)\
+    $(PchPlatformPeiLib_LIB)\
+    $(EdkIIGlueBasePciLibPciExpress_LIB) \
+    $(IntelPchPpiLib_LIB)\
+    $(EdkIIGlueBasePrintLib_LIB) \
+    $(CPU_PPI_LIB) \
+    $(CpuPlatformLib_LIB)\
+    $(SaGuidLib_LIB)\
+    $(TxtLib_LIB)
+
+MemoryInitBin_DEFINES=\
+    /D"__EDKII_GLUE_MODULE_ENTRY_POINT__=PeimMemoryInit"\
+    /D __EDKII_GLUE_BASE_IO_LIB_INTRINSIC__ \
+    /D __EDKII_GLUE_PEI_DEBUG_LIB_REPORT_STATUS_CODE__ \
+    /D __EDKII_GLUE_PEI_REPORT_STATUS_CODE_LIB__ \
+    /D __EDKII_GLUE_PEI_SERVICES_LIB__ \
+    /D __EDKII_GLUE_PEI_MEMORY_ALLOCATION_LIB__ \
+    /D __EDKII_GLUE_PEI_HOB_LIB__ \
+#!IFDEF SOFTSDV_FLAG
+#    /D MRC_FLAG_SKIP_TRAINING\
+#    /D MRC_FLAG_SKIP_JEDEC_RESET\
+#!ENDIF # SOFTSDV_FLAG
+
+#    /DINCLUDE_ME_CODE\
+#    /DSFF_SUPPORT\
+#    /DDDR2_SUPPORT\
+#    /DDDR3_SUPPORT\
+#    /DDDR3LV_SUPPORT\
+#    /DTHERMAL_SUPPORT\
+#    /DPRE_PRODUCTION_WA_SUPPORT\
+#    /DREAD_TRAINING_SUPPORT\
+#    /DWRITE_TRAINING_SUPPORT\
+#    /D"SO_DIMM_SUPPORT=1"
+
+MemoryInitBin: $(MemoryInitBin_LIBS)
+    $(MAKE) /$(MAKEFLAGS) $(EDKIIGLUE_DEFAULTS)\
+    /f $(BUILD_DIR)\MemoryInit.mak all\
+    NAME=MemoryInit\
+    MAKEFILE=$(BUILD_DIR)\MemoryInit.mak \
+    "CFLAGS=$(CFLAGS) /Oi /Gs65536 /Zi /Gm" \
+    "MY_INCLUDES=$(MemoryInitBin_INCLUDES)"\
+    "MY_DEFINES=$(MemoryInitBin_DEFINES)"\
+    GUID=3B42EF57-16D3-44CB-8632-9FDB06B41451\
+    ENTRY_POINT=_ModuleEntryPoint\
+    DEPEX1=$(MemoryInit_DIR)\MemoryInit.dxs\
+    DEPEX1_TYPE=EFI_SECTION_PEI_DEPEX\
+    TYPE=PEIM\
+    EDKIIModule=PEIM\
+    COMPRESS=0
+
+#
+# We use the following Microsoft Visual C++ Compiler options:
+#  /Oi      - Generate intrinsic functions (memset, memcpy etc.)
+#  /Gs32768 - Limit stack checking calls to 32KB (default is 4KB)
+#  /FAsc    - may be used to produce the *.COD files (intermediate assembly)
+#
diff --git a/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/MemoryInit.sdl b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/MemoryInit.sdl
new file mode 100644
index 0000000..a472857
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/MemoryInit.sdl
@@ -0,0 +1,273 @@
+TOKEN
+	Name  = "MemoryInit_SUPPORT"
+	Value  = "1"
+	Help  = "SandyBridge MemoryInit support in Project"
+	TokenType = Boolean
+	TargetEQU = Yes
+	TargetMAK = Yes
+	TargetH = Yes
+	Master = Yes
+End
+
+TOKEN
+	Name  = "MRC_DEBUG_PRINT_SUPPORT"
+	Value  = "0"
+	TokenType = Boolean
+	TargetMAK = Yes
+	TargetH = Yes
+	Token = "DEBUG_MODE" "=" "1"
+End
+
+TOKEN
+	Name  = "CAR_TOTAL_SIZE"
+	Value  = "0x40000"
+	Help  = "Total Cache-as-RAM size available (in bytes)"
+	TokenType = Integer
+	TargetEQU = Yes
+	TargetH = Yes
+End
+
+TOKEN
+	Name  = "ULT_SUPPORT"
+	Value  = "0"
+	TokenType = Boolean
+	TargetMAK = Yes
+	TargetH = Yes
+End
+
+TOKEN
+	Name  = "ULT_SUPPORT"
+	Value  = "1"
+	TokenType = Boolean
+	TargetMAK = Yes
+	TargetH = Yes
+	Token = "PCH_SKU" "=" "1"
+End
+
+TOKEN
+	Name  = "VP_SUPPORT"
+	Value  = "0"
+	TokenType = Boolean
+	TargetMAK = Yes
+End
+
+TOKEN
+	Name  = "CTE_SUPPORT"
+	Value  = "0"
+	TokenType = Boolean
+	TargetMAK = Yes
+End
+
+TOKEN
+	Name  = "SLE_SUPPORT"
+	Value  = "0"
+	TokenType = Boolean
+	TargetMAK = Yes
+End
+
+TOKEN
+	Name  = "SSA_SUPPORT"
+	Value  = "1"
+	TokenType = Boolean
+	TargetMAK = Yes
+End
+
+TOKEN
+	Name  = "EMBEDDED_SUPPORT"
+	Value  = "1"
+	TokenType = Boolean
+	TargetMAK = Yes
+End
+
+TOKEN
+	Name  = " "
+	TokenType = Integer
+End
+
+TOKEN
+	Name  = "=============== NB MRC Memory Down Tokens =============="
+	TokenType = Expression
+End
+
+TOKEN
+	Name  = "MRC_MEMORY_DOWN_SUPPORT"
+	Value  = "1"
+	TokenType = Boolean
+	TargetMAK = Yes
+End
+
+TOKEN
+	Name  = "NB_OEM_DIMM1_STATUS"
+	Value  = "2"
+	Help  = "Memory slot 1 status. 0: Memory Absent, 1: Physical memory slot, 2: Memory down."
+	TokenType = Integer
+	TargetH = Yes
+	Range  = "0, 1, 2"
+	Token = "MRC_MEMORY_DOWN_SUPPORT" "=" "1"
+End
+
+TOKEN
+	Name  = "NB_OEM_DIMM2_STATUS"
+	Value  = "2"
+	Help  = "Memory slot 2 status. 0: Memory Absent, 1: Physical memory slot, 2: Memory down."
+	TokenType = Integer
+	TargetH = Yes
+	Range  = "0, 1, 2"
+	Token = "MRC_MEMORY_DOWN_SUPPORT" "=" "1"
+End
+
+TOKEN
+	Name  = "NB_OEM_DIMM3_STATUS"
+	Value  = "2"
+	Help  = "Memory slot 3 status. 0: Memory Absent, 1: Physical memory slot, 2: Memory down."
+	TokenType = Integer
+	TargetH = Yes
+	Range  = "0, 1, 2"
+	Token = "MRC_MEMORY_DOWN_SUPPORT" "=" "1"
+End
+
+TOKEN
+	Name  = "NB_OEM_DIMM4_STATUS"
+	Value  = "2"
+	Help  = "Memory slot 4 status. 0: Memory Absent, 1: Physical memory slot, 2: Memory down."
+	TokenType = Integer
+	TargetH = Yes
+	Range  = "0, 1, 2"
+	Token = "MRC_MEMORY_DOWN_SUPPORT" "=" "1"
+End
+
+TOKEN
+	Name  = "NB_OEM_DIMM1_SPD_DATA"
+	Value  = "{0x92, 0x10, 0x0B, 0x02, 0x02, 0x11, 0x00, 0x09, 0x03, 0x52, 0x01, 0x08, 0x0A, 0x00, 0xFE, 0x00, 0x69, 0x78, 0x69, 0x30, 0x69, 0x11, 0x18, 0x81, 0x70, 0x03, 0x3C, 0x3C, 0x00, 0xF0, 0x83, 0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x11, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x98, 0x00, 0x11, 0x11, 0x6B, 0x22, 0x9A, 0x82, 0x11, 0x70}"
+	Help  = "SPD data {0-127} = {Offset0, Offset1, Offset2, Offset3, ....}."
+	TokenType = Expression
+	TargetH = Yes
+	Range  = "{0-127}"
+	Token = "NB_OEM_DIMM1_STATUS" "=" "2"
+End
+
+TOKEN
+	Name  = "NB_OEM_DIMM2_SPD_DATA"
+	Value  = "{0x92, 0x10, 0x0B, 0x02, 0x02, 0x11, 0x00, 0x09, 0x03, 0x52, 0x01, 0x08, 0x0A, 0x00, 0xFE, 0x00, 0x69, 0x78, 0x69, 0x30, 0x69, 0x11, 0x18, 0x81, 0x70, 0x03, 0x3C, 0x3C, 0x00, 0xF0, 0x83, 0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x11, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x98, 0x00, 0x11, 0x11, 0x6B, 0x22, 0x9A, 0x82, 0x11, 0x70}"
+	Help  = "SPD data {0-127} = {Offset0, Offset1, Offset2, Offset3, ....}."
+	TokenType = Expression
+	TargetH = Yes
+	Range  = "{0-127}"
+	Token = "NB_OEM_DIMM2_STATUS" "=" "2"
+End
+
+TOKEN
+	Name  = "NB_OEM_DIMM3_SPD_DATA"
+	Value  = "{0x92, 0x10, 0x0B, 0x02, 0x02, 0x11, 0x00, 0x09, 0x03, 0x52, 0x01, 0x08, 0x0A, 0x00, 0xFE, 0x00, 0x69, 0x78, 0x69, 0x30, 0x69, 0x11, 0x18, 0x81, 0x70, 0x03, 0x3C, 0x3C, 0x00, 0xF0, 0x83, 0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x11, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x98, 0x00, 0x11, 0x11, 0x6B, 0x22, 0x9A, 0x82, 0x11, 0x70}"
+	Help  = "SPD data {0-127} = {Offset0, Offset1, Offset2, Offset3, ....}."
+	TokenType = Expression
+	TargetH = Yes
+	Range  = "{0-127}"
+	Token = "NB_OEM_DIMM3_STATUS" "=" "2"
+End
+
+TOKEN
+	Name  = "NB_OEM_DIMM4_SPD_DATA"
+	Value  = "{0x92, 0x10, 0x0B, 0x02, 0x02, 0x11, 0x00, 0x09, 0x03, 0x52, 0x01, 0x08, 0x0A, 0x00, 0xFE, 0x00, 0x69, 0x78, 0x69, 0x30, 0x69, 0x11, 0x18, 0x81, 0x70, 0x03, 0x3C, 0x3C, 0x00, 0xF0, 0x83, 0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x11, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x98, 0x00, 0x11, 0x11, 0x6B, 0x22, 0x9A, 0x82, 0x11, 0x70}"
+	Help  = "SPD data {0-127} = {Offset0, Offset1, Offset2, Offset3, ....}."
+	TokenType = Expression
+	TargetH = Yes
+	Range  = "{0-127}"
+	Token = "NB_OEM_DIMM4_STATUS" "=" "2"
+End
+
+PATH
+	Name  = "MemoryInit_DIR"
+End
+
+MODULE
+	Help  = "Includes MemoryInit.mak to Project"
+	File  = "MemoryInit.mak"
+End
+
+ELINK
+	Name  = "$(BUILD_DIR)\MemoryInit.ffs"
+	Parent  = "MEM_INIT_FV_BB"
+	InvokeOrder = AfterParent
+End
+
+ELINK
+	Name  = "/D DDR3LV_SUPPORT"
+	Parent  = "INTEL_SA_RC_FLAGS"
+	InvokeOrder = AfterParent
+End
+
+ELINK
+	Name  = "/D MEMORY_DOWN_SUPPORT=$(MRC_MEMORY_DOWN_SUPPORT)"
+	Parent  = "INTEL_SA_RC_FLAGS"
+	InvokeOrder = AfterParent
+End
+
+ELINK
+	Name  = "/D TRAD_FLAG"
+	Parent  = "INTEL_SA_RC_FLAGS"
+	InvokeOrder = AfterParent
+End
+
+ELINK
+	Name  = "/D ULT_FLAG"
+	Parent  = "INTEL_SA_RC_FLAGS"
+	InvokeOrder = AfterParent
+End
+
+ELINK
+	Name  = "/D VP_FLAG"
+	Parent  = "INTEL_SA_RC_FLAGS"
+	Token = "VP_SUPPORT" "=" "1"
+	InvokeOrder = AfterParent
+End
+
+ELINK
+	Name  = "/D CTE_FLAG"
+	Parent  = "INTEL_SA_RC_FLAGS"
+	Token = "CTE_SUPPORT" "=" "1"
+	InvokeOrder = AfterParent
+End
+
+ELINK
+	Name  = "/D SLE_FLAG"
+	Parent  = "INTEL_SA_RC_FLAGS"
+	Token = "SLE_SUPPORT" "=" "1"
+	InvokeOrder = AfterParent
+End
+
+ELINK
+	Name  = "/D ME_SUPPORT_FLAG"
+	Parent  = "INTEL_SA_RC_FLAGS"
+	Token = "iME_SUPPORT" "=" "1"
+	InvokeOrder = AfterParent
+End
+
+ELINK
+	Name  = "/D TXT_SUPPORT_FLAG"
+	Parent  = "INTEL_SA_RC_FLAGS"
+	Token = "TxtPei_SUPPORT" "=" "1"
+	InvokeOrder = AfterParent
+End
+
+ELINK
+	Name  = "/D SSA_FLAG"
+	Parent  = "INTEL_SA_RC_FLAGS"
+	Token = "SSA_SUPPORT" "=" "1"
+	InvokeOrder = AfterParent
+End
+
+ELINK
+	Name  = "/D EMBEDDED_FLAG"
+	Parent  = "INTEL_SA_RC_FLAGS"
+	Token = "EMBEDDED_SUPPORT" "=" "1"
+	InvokeOrder = AfterParent
+End
+
+ELINK
+	Name  = "/D SMM_THUNK_NO_AB_SEG_FLAG"
+	Parent  = "INTEL_SA_RC_FLAGS"
+	Token = "SMM_THUNK_IN_CSM" "=" "1"
+	Token = "SMM_THUNK_NO_AB_SEG" "=" "0"
+	InvokeOrder = AfterParent
+End
diff --git a/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/MrcDebugHook.h b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/MrcDebugHook.h
new file mode 100644
index 0000000..e6ff6fc
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/MrcDebugHook.h
@@ -0,0 +1,210 @@
+/** @file
+  This file defines all the MRC debug hooks.
+
+@copyright
+  Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved.
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement
+**/
+#ifndef _MrcDebugHook_h_
+#define _MrcDebugHook_h_
+
+#define MRC_FAILURE_INDICATION          (0x0080)  /// This value is or'ed with below "*_ERROR" codes
+#define MRC_INITIALIZATION_START        (0xDD00)
+
+#define MRC_FAST_BOOT_PERMITTED         (0xDD1B)
+#define MRC_FAST_BOOT_PERMITTED_ERROR   (MRC_FAST_BOOT_PERMITTED | MRC_FAILURE_INDICATION)
+
+#define MRC_RESTORE_NON_TRAINING        (0xDD1C)
+#define MRC_RESTORE_NON_TRAINING_ERROR  (MRC_RESTORE_NON_TRAINING | MRC_FAILURE_INDICATION)
+
+#define MRC_PRINT_INPUT_PARAMS          (0xDD1D)
+#define MRC_PRINT_INPUT_PARAMS_ERROR    (MRC_PRINT_INPUT_PARAMS | MRC_FAILURE_INDICATION)
+
+#define MRC_SET_OVERRIDES_PSPD          (0xDD1E)
+#define MRC_SET_OVERRIDES_PSPD_ERROR    (MRC_SET_OVERRIDES_PSPD | MRC_FAILURE_INDICATION)
+
+#define MRC_MC_CAPABILITY_PSPD          (0xDD1F)
+#define MRC_MC_CAPABILITY_PSPD_ERROR    (MRC_MC_CAPABILITY_PSPD | MRC_FAILURE_INDICATION)
+
+#define MRC_SPD_PROCESSING              (0xDD20)
+#define MRC_SPD_PROCESSING_ERROR        (MRC_SPD_PROCESSING | MRC_FAILURE_INDICATION)
+
+#define MRC_SET_OVERRIDES               (0xDD21)
+#define MRC_SET_OVERRIDES_ERROR         (MRC_SET_OVERRIDES | MRC_FAILURE_INDICATION)
+
+#define MRC_MC_CAPABILITY               (0xDD22)
+#define MRC_MC_CAPABILITY_ERROR         (MRC_MC_CAPABILITY | MRC_FAILURE_INDICATION)
+
+#define MRC_MC_CONFIG                   (0xDD23)
+#define MRC_MC_CONFIG_ERROR             (MRC_MC_CONFIG | MRC_FAILURE_INDICATION)
+
+#define MRC_MC_MEMORY_MAP               (0xDD24)
+#define MRC_MC_MEMORY_MAP_ERROR         (MRC_MC_MEMORY_MAP | MRC_FAILURE_INDICATION)
+
+#define MRC_JEDEC_INIT_LPDDR3           (0xDD25)
+#define MRC_JEDEC_INIT_LPDDR3_ERROR     (MRC_JEDEC_INIT_LPDDR3 | MRC_FAILURE_INDICATION)
+
+#define MRC_RESET_SEQUENCE              (0xDD26)
+#define MRC_RESET_ERROR                 (MRC_RESET_SEQUENCE | MRC_FAILURE_INDICATION)
+
+#define MRC_PRE_TRAINING                (0xDD27)
+#define MRC_PRE_TRAINING_ERROR          (MRC_PRE_TRAINING | MRC_FAILURE_INDICATION)
+
+///
+/// TRAINING STEPS START
+///
+#define MRC_EARLY_COMMAND               (0xDD28)
+#define MRC_EARLY_COMMAND_ERROR         (MRC_EARLY_COMMAND | MRC_FAILURE_INDICATION)
+
+#define MRC_SENSE_AMP_OFFSET            (0xDD29)
+#define MRC_SENSE_AMP_OFFSET_ERROR      (MRC_SENSE_AMP_OFFSET | MRC_FAILURE_INDICATION)
+
+#define MRC_READ_MPR                    (0xDD2A)
+#define MRC_READ_MPR_ERROR              (MRC_READ_MPR | MRC_FAILURE_INDICATION)
+
+#define MRC_RECEIVE_ENABLE              (0xDD2B)
+#define MRC_RECEIVE_ENABLE_ERROR        (MRC_RECEIVE_ENABLE | MRC_FAILURE_INDICATION)
+
+#define MRC_JEDEC_WRITE_LEVELING        (0xDD2C)
+#define MRC_JEDEC_WRITE_LEVELING_ERROR  (MRC_JEDEC_WRITE_LEVELING | MRC_FAILURE_INDICATION)
+
+#define MRC_WRITE_TIMING_1D             (0xDD2E)
+#define MRC_WRITE_TIMING_1D_ERROR       (MRC_WRITE_TIMING_1D | MRC_FAILURE_INDICATION)
+
+#define MRC_READ_TIMING_1D              (0xDD2F)
+#define MRC_READ_TIMING_1D_ERROR        (MRC_READ_TIMING_1D | MRC_FAILURE_INDICATION)
+
+#define MRC_DIMM_ODT                    (0xDD30)
+#define MRC_DIMM_ODT_ERROR              (MRC_DIMM_ODT | MRC_FAILURE_INDICATION)
+
+#define MRC_WRITE_DS                    (0xDD32)
+#define MRC_WRITE_DS_ERROR              (MRC_WRITE_DS | MRC_FAILURE_INDICATION)
+
+#define MRC_WRITE_EQ                    (0xDD33)
+#define MRC_WRITE_EQ_ERROR              (MRC_WRITE_EQ | MRC_FAILURE_INDICATION)
+
+#define MRC_READ_ODT                    (0xDD35)
+#define MRC_READ_ODT_ERROR              (MRC_READ_ODT | MRC_FAILURE_INDICATION)
+
+#define MRC_READ_EQ                     (0xDD36)
+#define MRC_READ_EQ_ERROR               (MRC_READ_EQ | MRC_FAILURE_INDICATION)
+
+#define MRC_READ_AMP_POWER              (0xDD37)
+#define MRC_READ_AMP_POWER_ERROR        (MRC_READ_AMP_POWER | MRC_FAILURE_INDICATION)
+
+#define MRC_WRITE_TIMING_2D             (0xDD38)
+#define MRC_WRITE_TIMING_2D_ERROR       (MRC_WRITE_TIMING_2D | MRC_FAILURE_INDICATION)
+
+#define MRC_READ_TIMING_2D              (0xDD39)
+#define MRC_READ_TIMING_2D_ERROR        (MRC_READ_TIMING_2D | MRC_FAILURE_INDICATION)
+
+#define MRC_CMD_VREF                    (0xDD3A)
+#define MRC_CMD_VREF_ERROR              (MRC_CMD_VREF_2D | MRC_FAILURE_INDICATION)
+
+#define MRC_WRITE_VREF_2D               (0xDD3B)
+#define MRC_WRITE_VREF_2D_ERROR         (MRC_WRITE_VREF_2D | MRC_FAILURE_INDICATION)
+
+#define MRC_READ_VREF_2D                (0xDD3C)
+#define MRC_READ_VREF_2D_ERROR          (MRC_READ_VREF_2D | MRC_FAILURE_INDICATION)
+
+#define MRC_POST_TRAINING               (0xDD3D)
+#define MRC_POST_TRAINING_ERROR         (MRC_POST_TRAINING | MRC_FAILURE_INDICATION)
+
+#define MRC_LATE_COMMAND                (0xDD3E)
+#define MRC_LATE_COMMAND_ERROR          (MRC_LATE_COMMAND | MRC_FAILURE_INDICATION)
+
+#define MRC_ROUND_TRIP_LAT              (0xDD3F)
+#define MRC_ROUND_TRIP_LAT_ERROR        (MRC_ROUND_TRIP_LAT | MRC_FAILURE_INDICATION)
+
+#define MRC_TURN_AROUND                 (0xDD40)
+#define MRC_TURN_AROUND_ERROR           (MRC_TURN_AROUND | MRC_FAILURE_INDICATION)
+
+#define MRC_CMP_OPT                     (0xDD41)
+#define MRC_CMP_OPT_ERROR               (MRC_CMP_OPT | MRC_FAILURE_INDICATION)
+
+#define MRC_SAVE_MC_VALUES              (0xDD42)
+#define MRC_SAVE_MC_VALUES_ERROR        (MRC_SAVE_MC_VALUES | MRC_FAILURE_INDICATION)
+
+#define MRC_RESTORE_TRAINING            (0xDD43)
+#define MRC_RESTORE_TRAINING_ERROR      (MRC_RESTORE_TRAINING | MRC_FAILURE_INDICATION)
+
+#define MRC_RMT_TOOL                    (0xDD44)
+#define MRC_RMT_TOOL_ERROR              (MRC_RMT_TOOL | MRC_FAILURE_INDICATION)
+
+#define MRC_WRITE_SR                    (0xDD45)
+#define MRC_WRITE_SR_ERROR              (MRC_WRITE_SR | MRC_FAILURE_INDICATION)
+
+#define MRC_DIMM_RON                    (0xDD46)
+#define MRC_DIMM_RON_ERROR              (MRC_DIMM_RON | MRC_FAILURE_INDICATION)
+
+#define MRC_RCVEN_TIMING_1D             (0xDD47)
+#define MRC_RCVEN_TIMING_1D_ERROR       (MRC_RCVEN_TIMING_1D | MRC_FAILURE_INDICATION)
+
+#define MRC_PWR_MTR                     (0xDD49)
+#define MRC_PWR_MTR_ERROR               (MRC_PWR_MTR | MRC_FAILURE_INDICATION)
+
+#define MRC_MC_ACTIVATE                 (0xDD50)
+#define MRC_MC_ACTIVATE_ERROR           (MRC_MC_ACTIVATE | MRC_FAILURE_INDICATION)
+
+#define MRC_GET_MRC_DATA                (0xDD52)
+#define MRC_GET_MRC_DATA_ERROR          (MRC_GET_MRC_DATA | MRC_FAILURE_INDICATION)
+
+
+///
+/// To have distinct post codes for debuggin purposes, do not define a training step
+/// value to have the same lower byte value as MRC_MEM_INIT_DONE.  This value is
+/// specific to signal the completion of the module.  This holds higher signifiance
+/// on systems that do not use the high byte.
+///
+/// #define MRC_DO_NOT_USE                (0x__55)
+///
+
+#define MRC_RETRAIN_CHECK               (0xDD58)
+#define MRC_RETRAIN_CHECK_ERROR         (MRC_RETRAIN_CHECK | MRC_FAILURE_INDICATION)
+
+#define MRC_INIT_IO_DEFAULT             (0xDD59)
+#define MRC_INIT_IO_DEFAULT_ERROR       (MRC_INIT_IO_DEFAULT | MRC_FAILURE_INDICATION)
+
+#define MRC_ALIAS_CHECK                 (0xDD5B)
+#define MRC_ALIAS_CHECK_ERROR           (MRC_ALIAS_CHECK | MRC_FAILURE_INDICATION)
+
+#define MRC_ECC_CLEAN_START             (0xDD5C)
+#define MRC_ECC_CLEAN_ERROR             (MRC_ECC_CLEAN_START | MRC_FAILURE_INDICATION)
+
+#define MRC_DONE                        (0xDD5D)
+#define MRC_DONE_WITH_ERROR             (MRC_DONE | MRC_FAILURE_INDICATION)
+
+#define MRC_CPGC_MEMORY_TEST            (0xDD5F)
+#define MRC_CPGC_MEMORY_TEST_ERROR      (MRC_CPGC_MEMORY_TEST | MRC_FAILURE_INDICATION)
+
+#define MRC_MEMORY_TEST                 (0xDD68)
+#define MRC_MEMORY_TEST_ERROR           (MRC_MEMORY_TEST | MRC_FAILURE_INDICATION)
+
+#define MRC_FILL_RMT_STRUCTURE          (0xDD69)
+#define MRC_FILL_RMT_STRUCTURE_ERROR    (MRC_FILL_RMT_STRUCTURE | MRC_FAILURE_INDICATION)
+
+#define MRC_SELF_REFRESH_EXIT           (0xDD70)
+#define MRC_SELF_REFRESH_EXIT_ERROR     (MRC_SELF_REFRESH_EXIT | MRC_FAILURE_INDICATION)
+
+#define MRC_NORMAL_MODE                 (0xDD71)
+#define MRC_MRC_NORMAL_MODE_ERROR       (MRC_NORMAL_MODE | MRC_FAILURE_INDICATION)
+
+#define MRC_NO_MEMORY_DETECTED          (0xDD7E | MRC_FAILURE_INDICATION)
+
+#define MRC_MEM_INIT_DONE               (0x0055)
+#define MRC_MEM_INIT_DONE_WITH_ERRORS   (MRC_MEM_INIT_DONE | MRC_FAILURE_INDICATION)
+
+#endif
diff --git a/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/MrcOemAddrDecode.c b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/MrcOemAddrDecode.c
new file mode 100644
index 0000000..7c94deb
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/MrcOemAddrDecode.c
@@ -0,0 +1,232 @@
+/**
+This file contains an 'Intel Peripheral Driver' and uniquely
+identified as "Intel Reference Module" and is
+licensed for Intel CPUs and chipsets under the terms of your
+license agreement with Intel or your vendor.  This file may
+be modified by the user, subject to additional terms of the
+license agreement
+
+Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved.
+This software and associated documentation (if any) is furnished
+under a license and may only be used or copied in accordance
+with the terms of the license. Except as permitted by such
+license, no part of this software or documentation may be
+reproduced, stored in a retrieval system, or transmitted in any
+form or by any means without the express written consent of
+Intel Corporation.
+
+@file:
+  MrcOemAddrDecode.c
+
+@brief:
+  Wrapper file for AddrDecode files.
+**/
+
+//
+// Include files
+//
+#include "MrcApi.h"
+#include "MrcGlobal.h"
+#include "MrcOemAddrDecode.h"
+#include "MrcOemIo.h"
+#include "MrcOemMmio.h"
+#include "McAddress.h"
+#include "MrcHswMcAddrDecode.h"
+
+/**
+@brief
+  Address decode function
+  Converts system address to DRAM address
+
+  @param[in]      SystemAddress  - The 39-bit system address to convert.
+  @param[out]     DramAddress    - The dram address struct that the system address decodes to.
+
+  @retval Returns 1 if successful, 0 otherwise.
+
+**/
+unsigned char
+MrcMcAddressDecode (
+  IN     unsigned long long SystemAddress,
+  OUT    ADDRESS_DECODE     *DramAddress
+  )
+{
+  unsigned char                        Status;
+  U32                                  MchBarBaseAddress;
+  U32                                  PciEBaseAddress;
+  U32                                  Offset;
+  MRC_PCI_000_TOLUD_STRUCT             Tolud;
+  MRC_PCI_000_REMAPBASE_STRUCT         RemapBase;
+  MRC_PCI_000_REMAPLIMIT_STRUCT        RemapLimit;
+  MCDECS_CR_CHANNEL_HASH_MCMAIN_STRUCT ChannelHash;
+  MCDECS_CR_MAD_ZR_MCMAIN_STRUCT       MadZr;
+  MCDECS_CR_MAD_CHNL_MCMAIN_STRUCT     MadChnl;
+  MCDECS_CR_MAD_DIMM_CH0_MCMAIN_STRUCT DimmCh0McMain;
+  MCDECS_CR_MAD_DIMM_CH1_MCMAIN_STRUCT DimmCh1McMain;
+  U16                                  TempChannel;
+  U16                                  TempDimm;
+  U16                                  TempRank;
+  U16                                  TempBank;
+  U16                                  TempRow;
+  U16                                  TempColumn;
+  BOOL                                 IsTcm;
+
+  Status = 0;
+
+  //
+  // Check that MCHBAR is programmed
+  //
+  MrcOemOutPort32 (MrcOemPciIndex (), MrcOemGetPciDeviceAddress (0, 0, 0, MRC_PCI_000_MCHBAR_REG));
+  MchBarBaseAddress = MrcOemInPort32 (MrcOemPciData ());
+
+  if ((MchBarBaseAddress & MRC_BIT0) == MRC_BIT0) {
+    MchBarBaseAddress &= (~MRC_BIT0);
+  } else {
+    return Status;
+  }
+
+  //
+  // Check that PCIEXBAR is programmed
+  //
+  MrcOemOutPort32 (MrcOemPciIndex(), MrcOemGetPciDeviceAddress (0, 0, 0, MRC_PCI_000_PCIEXBAR_REG));
+  PciEBaseAddress = MrcOemInPort32 (MrcOemPciData ());
+
+  if ((PciEBaseAddress & MRC_BIT0) == MRC_BIT0) {
+    PciEBaseAddress &= ~(MRC_BIT2 | MRC_BIT1 | MRC_BIT0);
+  } else {
+    return Status;
+  }
+
+  Offset = MrcOemGetPcieDeviceAddress (0, 0, 0, MRC_PCI_000_TOLUD_REG);
+  MrcOemMmioRead (Offset, &Tolud.Data, PciEBaseAddress);
+  Offset = MrcOemGetPcieDeviceAddress (0, 0, 0, MRC_PCI_000_REMAPBASE_REG);
+  MrcOemMmioRead64 (Offset, &RemapBase.Data, PciEBaseAddress);
+  Offset = MrcOemGetPcieDeviceAddress (0, 0, 0, MRC_PCI_000_REMAPLIMIT_REG);
+  MrcOemMmioRead64 (Offset, &RemapLimit.Data, PciEBaseAddress);
+  MrcOemMmioRead (MCDECS_CR_CHANNEL_HASH_MCMAIN_REG, &ChannelHash.Data, MchBarBaseAddress);
+  MrcOemMmioRead (MCDECS_CR_MAD_ZR_MCMAIN_REG, &MadZr.Data, MchBarBaseAddress);
+  MrcOemMmioRead (MCDECS_CR_MAD_CHNL_MCMAIN_REG, &MadChnl.Data, MchBarBaseAddress);
+  MrcOemMmioRead (MCDECS_CR_MAD_DIMM_CH0_MCMAIN_REG, &DimmCh0McMain.Data, MchBarBaseAddress);
+  MrcOemMmioRead (MCDECS_CR_MAD_DIMM_CH1_MCMAIN_REG, &DimmCh1McMain.Data, MchBarBaseAddress);
+  IsTcm = FALSE;
+
+  Status = MrcHswDecode (
+             SystemAddress,
+             &IsTcm,
+             Tolud.Data,
+             RemapBase.Data,
+             RemapLimit.Data,
+             ChannelHash.Data,
+             MadZr.Data,
+             MadChnl.Data,
+             DimmCh0McMain.Data,
+             DimmCh1McMain.Data,
+             0,
+             &TempChannel,
+             &TempDimm,
+             &TempRank,
+             &TempBank,
+             &TempRow,
+             &TempColumn
+             );
+  DramAddress->ChannelNumber = (U8) TempChannel;
+  DramAddress->DIMMNumber    = (U8) TempDimm;
+  DramAddress->Rank          = (U8) TempRank;
+  DramAddress->Bank          = (U8) TempBank;
+  DramAddress->RAS           = (U16) TempRow;
+  DramAddress->CAS           = (U16) TempColumn;
+
+  return Status;
+}
+
+/**
+@brief
+  Address encode function (reverse address decode)
+  DRAM address to system address conversion
+
+  @param[in]      DramAddress    - The dram address that is converted.
+  @param[out]     SystemAddress  - The 39-bit system address to convert to.
+
+  @retval Returns 1 if successful, 0 otherwise.
+
+**/
+unsigned char
+MrcMcAddressEncode (
+  IN     ADDRESS_DECODE     *DramAddress,
+  OUT    unsigned long long *SystemAddress
+  )
+{
+  unsigned char                        Status;
+  U32                                  MchBarBaseAddress;
+  U32                                  PciEBaseAddress;
+  U32                                  Offset;
+  MRC_PCI_000_TOLUD_STRUCT             Tolud;
+  MRC_PCI_000_REMAPBASE_STRUCT         RemapBase;
+  MRC_PCI_000_REMAPLIMIT_STRUCT        RemapLimit;
+  MCDECS_CR_CHANNEL_HASH_MCMAIN_STRUCT ChannelHash;
+  MCDECS_CR_MAD_ZR_MCMAIN_STRUCT       MadZr;
+  MCDECS_CR_MAD_CHNL_MCMAIN_STRUCT     MadChnl;
+  MCDECS_CR_MAD_DIMM_CH0_MCMAIN_STRUCT DimmCh0McMain;
+  MCDECS_CR_MAD_DIMM_CH1_MCMAIN_STRUCT DimmCh1McMain;
+  BOOL                                 IsTcm;
+
+  Status = 0;
+
+  //
+  // Check that MCHBAR is programmed
+  //
+  MrcOemOutPort32 (MrcOemPciIndex (), MrcOemGetPciDeviceAddress (0, 0, 0, MRC_PCI_000_MCHBAR_REG));
+  MchBarBaseAddress = MrcOemInPort32 (MrcOemPciData ());
+
+  if ((MchBarBaseAddress & MRC_BIT0) == MRC_BIT0) {
+    MchBarBaseAddress &= (~MRC_BIT0);
+  } else {
+    return Status;
+  }
+
+  //
+  // Check that PCIEXBAR is programmed
+  //
+  MrcOemOutPort32 (MrcOemPciIndex(), MrcOemGetPciDeviceAddress (0, 0, 0, MRC_PCI_000_PCIEXBAR_REG));
+  PciEBaseAddress = MrcOemInPort32 (MrcOemPciData ());
+
+  if ((PciEBaseAddress & MRC_BIT0) == MRC_BIT0) {
+    PciEBaseAddress &= ~(MRC_BIT2 | MRC_BIT1 | MRC_BIT0);
+  } else {
+    return Status;
+  }
+
+  Offset = MrcOemGetPcieDeviceAddress (0, 0, 0, MRC_PCI_000_TOLUD_REG);
+  MrcOemMmioRead (Offset, &Tolud.Data, PciEBaseAddress);
+  Offset = MrcOemGetPcieDeviceAddress (0, 0, 0, MRC_PCI_000_REMAPBASE_REG);
+  MrcOemMmioRead64 (Offset, &RemapBase.Data, PciEBaseAddress);
+  Offset = MrcOemGetPcieDeviceAddress (0, 0, 0, MRC_PCI_000_REMAPLIMIT_REG);
+  MrcOemMmioRead64 (Offset, &RemapLimit.Data, PciEBaseAddress);
+  MrcOemMmioRead (MCDECS_CR_CHANNEL_HASH_MCMAIN_REG, &ChannelHash.Data, MchBarBaseAddress);
+  MrcOemMmioRead (MCDECS_CR_MAD_ZR_MCMAIN_REG, &MadZr.Data, MchBarBaseAddress);
+  MrcOemMmioRead (MCDECS_CR_MAD_CHNL_MCMAIN_REG, &MadChnl.Data, MchBarBaseAddress);
+  MrcOemMmioRead (MCDECS_CR_MAD_DIMM_CH0_MCMAIN_REG, &DimmCh0McMain.Data, MchBarBaseAddress);
+  MrcOemMmioRead (MCDECS_CR_MAD_DIMM_CH1_MCMAIN_REG, &DimmCh1McMain.Data, MchBarBaseAddress);
+  IsTcm = FALSE;
+
+  Status = MrcHswEncode (
+             (U16) DramAddress->ChannelNumber,
+             (U16) DramAddress->DIMMNumber,
+             (U16) DramAddress->Rank,
+             (U16) DramAddress->Bank,
+             (U16) DramAddress->RAS,
+             (U16) DramAddress->CAS,
+             Tolud.Data,
+             RemapBase.Data,
+             RemapLimit.Data,
+             ChannelHash.Data,
+             MadZr.Data,
+             MadChnl.Data,
+             DimmCh0McMain.Data,
+             DimmCh1McMain.Data,
+             0,
+             SystemAddress,
+             &IsTcm
+             );
+
+  return Status;
+}
diff --git a/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/MrcOemAddrDecode.h b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/MrcOemAddrDecode.h
new file mode 100644
index 0000000..7b9f4c9
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/MrcOemAddrDecode.h
@@ -0,0 +1,79 @@
+/**
+This file contains an 'Intel Peripheral Driver' and uniquely
+identified as "Intel Reference Module" and is
+licensed for Intel CPUs and chipsets under the terms of your
+license agreement with Intel or your vendor.  This file may
+be modified by the user, subject to additional terms of the
+license agreement.
+
+Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved.
+This software and associated documentation (if any) is furnished
+under a license and may only be used or copied in accordance
+with the terms of the license. Except as permitted by such
+license, no part of this software or documentation may be
+reproduced, stored in a retrieval system, or transmitted in any
+form or by any means without the express written consent of
+Intel Corporation.
+
+@file:
+  MrcOemAddrDecode.h
+
+@brief:
+  Wrapper file for AddrDecode files.
+
+**/
+#ifndef __MrcOemAddrDecode_h__
+#define __MrcOemAddrDecode_h__
+
+#include "MrcTypes.h"
+
+//
+// Defines used to get code in AddrDecode folder to compile
+//
+#define inline
+
+typedef struct
+{
+  U8  ChannelNumber;
+  U8  DIMMNumber;
+  U8  Rank;
+  U8  Bank;
+  U16 CAS;
+  U16 RAS;
+} ADDRESS_DECODE;
+
+/**
+@brief
+  Address decode function
+  Converts system address to DRAM address
+
+  @param[in]      SystemAddress  - The 39-bit system address to convert.
+  @param[out]     DramAddress    - The dram address struct that the system address decodes to.
+
+  @retval Returns 1 if successful, 0 otherwise.
+
+**/
+unsigned char
+MrcMcAddressDecode (
+  IN     unsigned long long SystemAddress,
+  OUT    ADDRESS_DECODE     *DramAddress
+  );
+
+/**
+@brief
+  Address encode function (reverse address decode)
+  DRAM address to system address conversion
+
+  @param[in]      DramAddress    - The dram address that is converted.
+  @param[out]     SystemAddress  - The 39-bit system address to convert to.
+
+  @retval Returns 1 if successful, 0 otherwise.
+
+**/
+unsigned char
+MrcMcAddressEncode (
+  IN     ADDRESS_DECODE     *DramAddress,
+  OUT    unsigned long long *SystemAddress
+  );
+
+#endif // __MrcOemAddrDecode_h__
diff --git a/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/MrcOemDebugPrint.c b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/MrcOemDebugPrint.c
new file mode 100644
index 0000000..dcae540
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/MrcOemDebugPrint.c
@@ -0,0 +1,470 @@
+/** @file
+  Output debug messages to the debug port.
+
+@copyright
+  Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved.
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement.
+
+**/
+
+#include "MrcTypes.h"
+#ifdef MRC_MINIBIOS_BUILD
+#include "printf.h"
+#else
+#include "EdkIIGluePeim.h"
+#endif // MRC_MINIBIOS_BUILD
+#include "MrcDebugHook.h"
+#include "MrcGlobal.h"
+#include "MrcOemDebugPrint.h"
+#include "MrcOemMemory.h"
+
+#ifdef MRC_DEBUG_PRINT
+#define ASCII_ETX (3)
+
+/**
+@brief
+  Convert an unsigned integer to a string.
+
+  @param[in]  Value           - Value to work on.
+  @param[out] Str             - The return string to print.
+  @param[in]  Width           - The width of string to print
+  @param[in]  Flags           - The flag type to print out, like '-' or '+'.
+  @param[in]  Base            - Number base to work on, as in 10, or 16.
+
+  @retval Number of characters in the resulting string.
+**/
+U32
+OemUintnToStr (
+  IN  const U32 Value,
+  OUT char      *Str,
+  IN  const U32 Width,
+  IN  const U32 Flags,
+  IN  const U32 Base
+  )
+{
+  char  *Ptr;
+  U32   Negative;
+  U32   Int;
+  U32   i;
+  char  Prefix;
+  char  c;
+  const char Hex[] = { '0', '1', '2', '3', '4', '5', '6', '7', '8', '9', 'A', 'B', 'C', 'D', 'E', 'F' };
+
+  Ptr = Str;
+  if ((Value > MRC_INT32_MAX) && (Flags & MRC_INT_SIGNED)) {
+    Int       = ~Value + 1; /* -Value */
+    Negative  = 1;
+  } else {
+    Int       = Value;
+    Negative  = 0;
+  }
+
+  i = 0;
+  do {           /* Generate digits in reverse order */
+    i++;
+    *Ptr++ = Hex[Int % Base];
+    if (Flags & MRC_COMMA_TYPE) {
+      if (Base == 16) {
+        if (i % 4 == 0) {
+          *Ptr++ = ',';
+        }
+      } else if (Base == 10) {
+        if ((i % 3) == 0) {
+          *Ptr++ = ',';
+        }
+      }
+    }
+  } while ((Int /= Base) > 0);
+  if (*(Ptr - 1) == ',') {
+    Ptr--;
+  }
+
+  if (Negative) {
+    *Ptr++ = '-';
+    i++;
+  } else if (Flags & MRC_PREFIX_SIGN) {
+    *Ptr++ = '+';
+    i++;
+  }
+
+  if (Flags & MRC_PREFIX_ZERO) {
+    Prefix = '0';
+  } else if (!(Flags & MRC_LEFT_JUSTIFY)) {
+    Prefix = ' ';
+  } else {
+    Prefix = 0x00;
+  }
+
+  if (Prefix != 0x00) {
+    for (i = (int) (Ptr - Str); i < Width; i++) {
+      *Ptr++ = Prefix;
+    }
+  }
+
+  *Ptr = '\0';
+
+  /* Reverse string */
+  while (Str < --Ptr) {
+    c       = *Str;
+    *Str++  = *Ptr;
+    *Ptr    = c;
+  }
+
+  return i;
+}
+
+/**
+@brief
+  Convert a string to a number.
+
+  @param[in, out] String - String to convert.
+
+  @retval Returns the string in number.
+**/
+U32
+OemStrToNumber (
+  IN OUT char **String
+  )
+{
+  U32   Sum;
+  char  *Str;
+
+  Str = *String;
+  if (*Str == '0') {
+    Str++;
+  }
+
+  Sum = 0;
+  while (MRC_ISDIGIT (*Str)) {
+    Sum = Sum * 10 + (*Str++ -'0');
+  }
+
+  *String = Str;
+  return Sum;
+}
+
+/*++
+@brief
+  Format string using specified format specifier. Limited support for sizes other than
+  unsigned 32-bit to save code space. Type overrides like {h | I | I64 | L}
+  are not supported.
+
+  @param[in] Format     - String containing characters to print and formatting data.
+    %[flags][width]type
+    [flags] '-' left align
+    [flags] '+' prefix with sign (+ or -)
+    [flags] '0' zero pad numbers
+    [flags] ' ' prefix black in front of postive numbers
+    [width] non negative decimal integer that specifies the width to print a value.
+    [width] '*' get the width from a int argument on the stack.
+    type    'd'|'i' signed decimal integer
+    type    'u' unsigned integer
+    type    'x'|'X' hexidecimal using "ABCDEF"
+    type    'c' print character
+    type    'p' print a pointer to void
+    type    's' print a null terminated string
+  @param[in] Marker     - Variable argument marker.
+  @param[in] BufferSize - Size of the buffer, in bytes.
+  @param[in] Buffer     - The buffer.
+
+  @retval Number of characters printed.
+**/
+int
+StringFormatter (
+  IN const char *const      Format,
+  IN MrcVaList              Marker,
+  IN U32                    BufferSize,
+  IN OUT U8                 *Buffer
+  )
+{
+  char     *p;
+  char     *String;
+  U32      Width;
+  U32      Flags;
+  U32      CharCount;
+
+  CharCount = 0;
+  if (Format != NULL) {
+    for (p = (char *) Format; *p && (CharCount < BufferSize); p++) {
+      if (*p != '%') {
+        if (*p == MRC_CHAR_LF) {
+          //
+          // Make LF into CR LF
+          //
+          MRC_PUTCC (Buffer, MRC_CHAR_CR, CharCount);
+        }
+
+        MRC_PUTCC (Buffer, *p, CharCount);
+      } else {
+        p++;
+        //
+        // Check for flags
+        //
+        Flags = 0;
+        if (*p == '-') {
+          Flags |= MRC_LEFT_JUSTIFY;
+        } else if (*p == '+') {
+          Flags |= MRC_PREFIX_SIGN;
+        } else if (*p == ' ') {
+          Flags |= MRC_PREFIX_BLANK;
+        }
+
+        if (Flags != 0) {
+          p++;
+        }
+        //
+        // Check for width
+        //
+        if (MRC_ISDIGIT (*p)) {
+          if (*p == '0') {
+            Flags |= MRC_PREFIX_ZERO;
+          }
+
+          Width = OemStrToNumber (&p);
+        } else if (*p == '*') {
+          Width = VA_ARG (Marker, int);
+          p++;
+        } else {
+          Width = 0;
+        }
+
+        if (*p == ',') {
+          Flags |= MRC_COMMA_TYPE;
+          p++;
+        }
+        //
+        // Get type
+        //
+        switch (*p) {
+          case 'd':
+          case 'i':
+            //
+            // Always print as UINTN. Will need extra code to print different widths.
+            //
+            CharCount = CharCount + OemUintnToStr (
+              (U32) VA_ARG (Marker, U32 *),
+              (char *) &Buffer[CharCount],
+              Width,
+              Flags | MRC_INT_SIGNED,
+              10
+              );
+            break;
+
+          case 'u':
+            //
+            // Always print as UINTN. Will need extra code to print different widths.
+            //
+            CharCount = CharCount + OemUintnToStr ((U32) VA_ARG (Marker, U32 *), (char *) &Buffer[CharCount], Width, Flags, 10);
+            break;
+
+          case 'x':
+          case 'X':
+          case 'p':
+            //
+            // Always print as UINTN. Will need extra code to print different widths.
+            //
+            CharCount = CharCount + OemUintnToStr ((U32) VA_ARG (Marker, U32 *), (char *) &Buffer[CharCount], Width, Flags, 16);
+            break;
+
+          case 'c':
+            MRC_PUTCC (Buffer, VA_ARG (Marker, char), CharCount);
+            Buffer[CharCount] = '\0';
+            break;
+
+          case 's':
+            String = (char *) VA_ARG (Marker, char *);
+            while (*String != '\0') {
+              MRC_PUTCC (Buffer, *String++, CharCount);
+            }
+            break;
+        }
+      }
+    }
+
+    if (CharCount < BufferSize) {
+      MRC_PUTCC (Buffer, '\0', CharCount);
+    } else {
+      Buffer[BufferSize - 1] = '\0';
+    }
+  }
+
+  return CharCount;
+}
+
+/*++
+
+@brief
+  Print to output stream/device. Limited support for sizes other than
+  unsigned 32-bit to save code space. Type overrides like {h | I | I64 | L}
+  are not supported.
+
+  @param[in] Debug  - Location to store debug message print information for future use.
+  @param[in] Level  - The debug level.
+  @param[in] Format - String containing characters to print and formatting data.
+    %[flags][width]type
+    [flags] '-' left align
+    [flags] '+' prefix with sign (+ or -)
+    [flags] '0' zero pad numbers
+    [flags] ' ' prefix black in front of postive numbers
+    [width] non negative decimal integer that specifies the width to print a value.
+    [width] '*' get the width from a int argument on the stack.
+    type    'd'|'i' signed decimal integer
+    type    'u' unsigned integer
+    type    'x'|'X' hexidecimal using "ABCDEF"
+    type    'c' print character
+    type    'p' print a pointer to void
+    type    's' print a null terminated string
+  @param[in] Marker - Variable argument marker
+
+  @retval Number of characters printed.
+**/
+int
+MrcOemPrintfVaList (
+  IN const MrcDebug *const  Debug,
+  IN const MrcDebugMsgLevel Level,
+  IN const char *const      Format,
+  IN MrcVaList              Marker
+  )
+{
+  MrcDebug *Dbg;
+  U8       *String;
+  U32      CharCount;
+  U8       Buffer[MAX_STRING_LENGTH];
+
+  CharCount = 0;
+  if ((Format != NULL) && (Level != MSG_LEVEL_NEVER)) {
+    if (((Debug->Level == MSG_LEVEL_TIME) && (Level == MSG_LEVEL_TIME)) || ((Debug->Level != MSG_LEVEL_TIME) && (Level <= Debug->Level))) {
+      CharCount = StringFormatter (Format, Marker, sizeof (Buffer), Buffer);
+
+      //
+      // Write the string to the serial log buffer.
+      //
+      if (Debug->Current > 0) {
+        Dbg    = (MrcDebug *) Debug;
+        String = Buffer;
+        while (*String != '\0') {
+          if (Dbg->Current >= Dbg->End) {
+            Dbg->Current = Dbg->Start;
+          }
+          *((U8 *) (Dbg->Current)) = *String++;
+          Dbg->Current++;
+        }
+        //
+        // Write a "end of text" marker to the buffer but don't increment the current pointer.
+        //
+        if (Dbg->Current >= Dbg->End) {
+          Dbg->Current = Dbg->Start;
+        }
+        *((U8 *) (Dbg->Current)) = ASCII_ETX;
+      }
+
+      if (Debug->Stream > 0) {
+#ifdef MRC_MINIBIOS_BUILD
+        puts ((char *) Buffer);
+#else
+        PEI_DEBUG (((void *) (Debug->Stream), EFI_D_ERROR, Buffer));
+#endif
+      }
+    }
+  }
+  return CharCount;
+}
+
+/**
+@brief
+  Print to output stream/device.  Gets the start Marker for the variable arguments
+  and calls MrcOemPrintfVaList().
+
+  @param[in] Debug  - Location to store debug message print information for future use.
+  @param[in] Level  - The debug level.
+  @param[in] Format - String containing characters to print and formatting data.
+           %[flags][width]type
+           [flags] '-' left align
+           [flags] '+' prefix with sign (+ or -)
+           [flags] '0' zero pad numbers
+           [flags] ' ' prefix black in front of postive numbers
+           [width] non negative decimal integer that specifies the width to print a value.
+           [width] '*' get the width from a int argument on the stack.
+           type    'd'|'i' signed decimal integer
+           type    'u' unsigned integer
+           type    'x'|'X' hexidecimal using "ABCDEF"
+           type    'c' print character
+           type    'p' print a pointer to void
+           type    's' print a null terminated string
+  @param[in] ...    - Variable number of arguments to print
+
+  @retval Number of characters printed.
+**/
+int
+MrcOemPrintf (
+  IN const MrcDebug *const  Debug,
+  IN const MrcDebugMsgLevel Level,
+  IN const char *const      Format,
+  ...
+  )
+{
+  MrcVaList Marker;
+
+  VA_START (Marker, Format);
+
+  return MrcOemPrintfVaList (Debug, Level, Format, Marker);
+}
+
+/**
+@brief
+  Save the output stream/device. This function must be called prior to debug
+  string output.
+
+  @param[out] Debug  - Location to store debug message print information for future use.
+  @param[in]  Level  - The debug level to set. Messages at or above this level are printed.
+  @param[in]  Stream - Pointer to the stream/device to use.
+  @param[in]  Buffer - Pointer to the buffer that will be used to 'tee' the data to.
+  @param[in]  Size   - Size of the 'tee' buffer.
+
+  @retval Nothing.
+**/
+void
+MrcOemFopen (
+  OUT MrcDebug *const        Debug,
+  IN  const MrcDebugMsgLevel Level,
+  IN  U32                    Stream,
+  IN  U32                    Buffer,
+  IN  U32                    Size
+  )
+{
+  const U8 StringBegin[] = "ISV>";
+  const U8 StringEnd[]   = "<ISV";
+
+  Debug->Level        = Level;
+  Debug->Stream       = Stream;
+  Debug->PostCode[0]  = 0;
+  if ((Buffer > 0) && (Size > (sizeof (StringBegin) + sizeof (StringEnd)))) {
+    Debug->Start   = Buffer + (sizeof (StringBegin) - 1);
+    Debug->End     = Buffer + Size - (sizeof (StringEnd) - 1);
+    Debug->Current = Debug->Start;
+    MrcOemMemorySet ((U8 *) Debug->Start, ' ', Size - (sizeof (StringBegin) + sizeof (StringEnd) - 2));
+    MrcOemMemoryCpy ((U8 *) Buffer, (U8 *) StringBegin, sizeof (StringBegin) - 1);
+    MrcOemMemoryCpy ((U8 *) Debug->End, (U8 *) StringEnd, sizeof (StringEnd) - 1);
+  } else {
+    Debug->Start   = 0;
+    Debug->End     = 0;
+    Debug->Current = 0;
+  }
+
+  return;
+}
+
+#endif // MRC_DEBUG_PRINT
diff --git a/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/MrcOemDebugPrint.h b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/MrcOemDebugPrint.h
new file mode 100644
index 0000000..9f84cc0
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/MrcOemDebugPrint.h
@@ -0,0 +1,261 @@
+/** @file
+  Output debug messages to the debug port.
+
+@copyright
+  Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved.
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement.
+**/
+
+#ifndef _MrcOemDebugPrint_h_
+#define _MrcOemDebugPrint_h_
+#pragma pack (push, 1)
+
+#include "MrcTypes.h"
+
+typedef char  *MrcVaList;
+
+#ifdef EFI_DEBUG
+#define MRC_DEBUG_PRINT (1)
+#endif // EFI_DEBUG
+#define TRANSMIT_HOLDING        (0x00)
+
+#define LINE_STATUS             (0x05)
+#define TRANS_HOLDING_REG_EMPTY (0x20)
+#define DATA_READY              (0x01)
+
+///
+/// com port options
+///
+#define MRC_COM1_BASE (0x3f8)
+#define MRC_COM2_BASE (0x2f8)
+#define MRC_COM3_BASE (0x3e8)
+#define MRC_COM4_BASE (0x2e8)
+
+///
+/// select the platform com port address
+///
+#define GLOBALCOMPORT (MRC_COM1_BASE)                                   ///< 0x3F8-0x3FF
+#ifndef MRC_LEFT_JUSTIFY
+#define MRC_LEFT_JUSTIFY  (0x01)
+#endif
+#ifndef MRC_PREFIX_SIGN
+#define MRC_PREFIX_SIGN (0x02)
+#endif
+#ifndef MRC_PREFIX_BLANK
+#define MRC_PREFIX_BLANK  (0x04)
+#endif
+#ifndef MRC_COMMA_TYPE
+#define MRC_COMMA_TYPE  (0x08)
+#endif
+#ifndef MRC_LONG_TYPE
+#define MRC_LONG_TYPE (0x10)
+#endif
+#ifndef MRC_PREFIX_ZERO
+#define MRC_PREFIX_ZERO (0x20)
+#endif
+#ifndef MRC_INT_SIGNED
+#define MRC_INT_SIGNED  (0x40)
+#endif
+
+#define MRC_CHAR_LF         (0x0A)
+#define MRC_CHAR_CR         (0x0D)
+#define MRC_INT32_MAX       (0x7FFFFFFF)
+#define MAX_STRING_LENGTH   160
+#define MRC_PUTCC(_str, _c, _CharCount) { \
+    _str[_CharCount] = _c; \
+    if (_CharCount < (MAX_STRING_LENGTH - 1)) {_CharCount++;}; \
+  }
+#define MRC_ISDIGIT(_c) (((_c) >= '0') && ((_c) <= '9'))
+
+#ifdef MRC_DEBUG_PRINT
+#define MRC_DEBUG_MSG_OPEN(DEBUG, LEVEL, FILE, BUFFER, SIZE) MrcOemFopen (DEBUG, LEVEL, FILE, BUFFER, SIZE)
+#define MRC_DEBUG_MSG(DEBUG, LEVEL, FORMAT, ...)             MrcOemPrintf (DEBUG, LEVEL, FORMAT, __VA_ARGS__)
+#define MRC_DEBUG_TEXT(arg)                                  (arg)
+#else
+#define MRC_DEBUG_MSG_OPEN(DEBUG, LEVEL, FILE, BUFFER, SIZE)
+#define MRC_DEBUG_MSG(DEBUG, LEVEL, FORMAT, ...)
+#define MRC_DEBUG_TEXT(arg)
+#endif
+
+typedef enum {
+  MSG_LEVEL_NEVER,
+  MSG_LEVEL_ERROR,
+  MSG_LEVEL_WARNING,
+  MSG_LEVEL_NOTE,
+  MSG_LEVEL_EVENT,
+  MSG_LEVEL_TIME,
+  MSG_LEVEL_ALL     = MRC_INT32_MAX
+} MrcDebugMsgLevel;
+
+typedef struct {
+  U32 Stream;
+  U32 Start;
+  U32 End;
+  U32 Current;
+  int Level;
+  U16 PostCode[2];
+} MrcDebug;
+
+/**
+@brief
+  Convert an unsigned integer to a string.
+
+  @param[in]  Value           - Value to work on.
+  @param[out] Str             - The return string to print.
+  @param[in]  Width           - The width of string to print
+  @param[in]  Flags           - The flag type to print out, like '-' or '+'.
+  @param[in]  Base            - Number base to work on, as in 10, or 16.
+
+  @retval Number of characters in the resulting string.
+**/
+extern
+U32
+OemUintnToStr (
+  IN  const U32 Value,
+  OUT char      *Str,
+  IN  const U32 Width,
+  IN  const U32 Flags,
+  IN  const U32 Base
+  );
+
+/**
+@brief
+  Convert a string to a number.
+
+  @param[in, out] String - String to convert.
+
+  @retval Returns the string in number.
+**/
+extern
+U32
+OemStrToNumber (
+  IN OUT char **String
+  );
+
+/*++
+@brief
+  Format string using specified format specifier. Limited support for sizes other than
+  unsigned 32-bit to save code space. Type overrides like {h | I | I64 | L}
+  are not supported.
+
+  @param[in] Format     - String containing characters to print and formatting data.
+    %[flags][width]type
+    [flags] '-' left align
+    [flags] '+' prefix with sign (+ or -)
+    [flags] '0' zero pad numbers
+    [flags] ' ' prefix black in front of postive numbers
+    [width] non negative decimal integer that specifies the width to print a value.
+    [width] '*' get the width from a int argument on the stack.
+    type    'd'|'i' signed decimal integer
+    type    'u' unsigned integer
+    type    'x'|'X' hexidecimal using "ABCDEF"
+    type    'c' print character
+    type    'p' print a pointer to void
+    type    's' print a null terminated string
+  @param[in] Marker     - Variable argument marker.
+  @param[in] BufferSize - Size of the buffer, in bytes.
+  @param[in] Buffer     - The buffer.
+
+  @retval Number of characters printed.
+**/
+
+extern
+int
+StringFormatter (
+  IN const char *const      Format,
+  IN MrcVaList              Marker,
+  IN U32                    BufferSize,
+  IN OUT U8                 *Buffer
+  );
+
+/*++
+
+@brief
+  Print to output stream/device. Limited support for sizes other than
+  unsigned 32-bit to save code space. Type overrides like {h | I | I64 | L}
+  are not supported.
+
+  @param[in] Debug  - Location to store debug message print information for future use.
+  @param[in] Level  - The debug level.
+  @param[in] Format - String containing characters to print and formatting data.
+    %[flags][width]type
+    [flags] '-' left align
+    [flags] '+' prefix with sign (+ or -)
+    [flags] '0' zero pad numbers
+    [flags] ' ' prefix black in front of postive numbers
+    [width] non negative decimal integer that specifies the width to print a value.
+    [width] '*' get the width from a int argument on the stack.
+    type    'd'|'i' signed decimal integer
+    type    'u' unsigned integer
+    type    'x'|'X' hexidecimal using "ABCDEF"
+    type    'c' print character
+    type    'p' print a pointer to void
+    type    's' print a null terminated string
+  @param[in] Marker - Variable argument marker
+
+  @retval Number of characters printed.
+**/
+extern
+int
+MrcOemPrintfVaList (
+  IN const MrcDebug *const  Debug,
+  IN const MrcDebugMsgLevel Level,
+  IN const char *const      Format,
+  IN MrcVaList              Marker
+  );
+
+/**
+@brief
+  put char in the uart device.
+
+  @param[in] c   - char to put in the uart.
+
+  @retval Returns the puted char.
+**/
+extern
+int
+MrcOemPrintf (
+  IN const MrcDebug *const  Debug,
+  IN const MrcDebugMsgLevel Level,
+  IN const char *const      Format,
+  ...
+  );
+
+/**
+@brief
+  Save the output stream/device. This function must be called prior to debug
+  string output.
+
+  @param[out] Debug  - Location to store debug message print information for future use.
+  @param[in]  Level  - The debug level to set. Messages at or above this level are printed.
+  @param[in]  Stream - Pointer to the stream/device to use.
+  @param[in]  Buffer - Pointer to the buffer that will be used to 'tee' the data to.
+  @param[in]  Size   - Size of the 'tee' buffer.
+
+  @retval Nothing.
+**/
+extern
+void
+MrcOemFopen (
+  OUT MrcDebug *const        Debug,
+  IN  const MrcDebugMsgLevel Level,
+  IN  U32                    Stream,
+  IN  U32                    Buffer,
+  IN  U32                    Size
+  );
+
+#pragma pack (pop)
+#endif //_MrcOemDebugPrint_h_
diff --git a/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/MrcOemIo.c b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/MrcOemIo.c
new file mode 100644
index 0000000..3654bef
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/MrcOemIo.c
@@ -0,0 +1,480 @@
+/** @file
+  This file contains the I/O port related functions.
+
+@copyright
+  Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved.
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement.
+
+**/
+
+#ifndef MRC_MINIBIOS_BUILD
+#include <Tiano.h>
+#include <EdkIIGlueIoLib.h>
+#endif // MRC_MINIBIOS_BUILD
+#include "MrcTypes.h"
+#include "MrcOemIo.h"
+#ifdef MRC_MINIBIOS_BUILD
+#include "Io.h"
+#endif // MRC_MINIBIOS_BUILD
+
+/*++
+
+@brief
+  8 bit I/O port read.
+
+  @param[in] IoAddress - The I/O port read address.
+
+  @retval The value read.
+**/
+U8
+MrcOemInPort8 (
+  IN const U16 IoAddress
+  )
+{
+  return IoRead8 (IoAddress);
+}
+
+/**
+@brief
+  8 bit I/O port write.
+
+  @param[in] IoAddress - The I/O port read address.
+  @param[in] Data      - The value to write.
+
+  @retval Nothing.
+**/
+void
+MrcOemOutPort8 (
+  IN const U16 IoAddress,
+  IN const U8  Data
+  )
+{
+  IoWrite8 (IoAddress, Data);
+}
+
+/**
+@brief
+  16 bit I/O port read.
+
+  @param[in] IoAddress - The I/O port read address.
+
+  @retval The value read.
+**/
+U16
+MrcOemInPort16 (
+  IN const U16 IoAddress
+  )
+{
+  return IoRead16 (IoAddress);
+}
+
+/**
+@brief
+  16 bit I/O port write.
+
+  @param[in] IoAddress - The I/O port read address.
+  @param[in] Data      - The value to write.
+
+  @retval Nothing.
+**/
+void
+MrcOemOutPort16 (
+  IN const U16 IoAddress,
+  IN const U16 Data
+  )
+{
+  IoWrite16 (IoAddress, Data);
+}
+
+/**
+@brief
+  32 bit I/O port read.
+
+  @param[in] IoAddress - The I/O port read address.
+
+  @retval The value read.
+**/
+U32
+MrcOemInPort32 (
+  IN const U16 IoAddress
+  )
+{
+  return IoRead32 (IoAddress);
+}
+
+/**
+@brief
+  32 bit I/O port write.
+
+  @param[in] IoAddress - The I/O port read address.
+  @param[in] Data      - The value to write.
+
+  @retval Nothing.
+**/
+void
+MrcOemOutPort32 (
+  IN const U16 IoAddress,
+  IN const U32 Data
+  )
+{
+  IoWrite32 (IoAddress, Data);
+}
+
+/**
+@brief
+  The PCI index address.
+
+  @param[in] None.
+
+  @retval The PCI index address.
+**/
+U16
+MrcOemPciIndex (
+  void
+  )
+{
+  return 0xCF8;
+}
+
+/**
+@brief
+  The PCI data address.
+
+  @param[in] None.
+
+  @retval The PCI data address.
+**/
+U16
+MrcOemPciData (
+  void
+  )
+{
+  return 0xCFC;
+}
+
+/**
+@brief
+  Calculate the PCI device address for the given Bus/Device/Function/Offset.
+
+  @param[in] Bus      - PCI bus
+  @param[in] Device   - PCI device
+  @param[in] Function - PCI function
+  @param[in] Offset   - Offset
+
+  @retval The PCI device address.
+**/
+U32
+MrcOemGetPciDeviceAddress (
+  IN const U8 Bus,
+  IN const U8 Device,
+  IN const U8 Function,
+  IN const U8 Offset
+  )
+{
+  return (
+    ((U32) ((Bus)      & 0xFF) << 16) |
+    ((U32) ((Device)   & 0x1F) << 11) |
+    ((U32) ((Function) & 0x07) << 8)  |
+    ((U32) ((Offset)   & 0xFF) << 0)  |
+    (1UL << 31));
+}
+
+/**
+@brief
+  Calculate the PCIE device address for the given Bus/Device/Function/Offset.
+
+  @param[in] Bus      - PCI bus
+  @param[in] Device   - PCI device
+  @param[in] Function - PCI function
+  @param[in] Offset   - Offset
+
+   The PCIE device address.
+
+  @retval The PCIe device address
+**/
+U32
+MrcOemGetPcieDeviceAddress (
+  IN const U8 Bus,
+  IN const U8 Device,
+  IN const U8 Function,
+  IN const U8 Offset
+  )
+{
+  return ((U32) Bus << 20) + ((U32) Device << 15) + ((U32) Function << 12) + ((U32) Offset << 0);
+}
+
+/**
+@brief
+  Read 32-bit value from the specified bus/device/function/offset.
+
+  @param[in] bus      - PCI bus number.
+  @param[in] device   - PCI device number.
+  @param[in] function - PCI function number.
+  @param[in] offset   - PCI address offset.
+
+  @retval 32-bit PCI value.
+**/
+U32
+MrcOemPciRead32 (
+  IN const U8 bus,
+  IN const U8 device,
+  IN const U8 function,
+  IN const U8 offset
+  )
+{
+  MrcOemOutPort32 (MrcOemPciIndex (), MrcOemGetPciDeviceAddress (bus, device, function, offset));
+  return MrcOemInPort32 (MrcOemPciData ());
+}
+
+/**
+@brief
+  Check if RTC date and time update is in progress and wait util it's finished.
+  We have at least 244us when "update in progress bit" is seen as low to
+  perform an operation on the RTC.
+
+  @param[in] None.
+
+  @retval Zero on timeout or non-zero and RTC is ready for transaction.
+**/
+U32
+CheckUpdateComplete (
+  void
+  )
+{
+  U32 Timeout;
+
+  //
+  // Wait until RTC "update in progress" bit goes low.
+  //
+  Timeout = 0x0FFFFF;
+  do {
+    MrcOemOutPort8 (RTC_INDEX_REGISTER, CMOS_REGA);
+    if ((MrcOemInPort8 (RTC_TARGET_REGISTER) & RTC_UPDATE_IN_PROGRESS) != RTC_UPDATE_IN_PROGRESS) {
+      break;
+    }
+  } while (--Timeout > 0);
+
+  return Timeout;
+}
+
+/**
+@brief
+  Initializes the RTC.
+
+  @param[in] None.
+
+  @retval Nothing.
+**/
+void
+InitRtc (
+  void
+  )
+{
+  MrcOemOutPort8 (RTC_INDEX_REGISTER, CMOS_REGB);
+  MrcOemOutPort8 (RTC_TARGET_REGISTER, RTC_HOLD | RTC_MODE_24HOUR);
+
+  MrcOemOutPort8 (RTC_INDEX_REGISTER, CMOS_REGA);
+  MrcOemOutPort8 (RTC_TARGET_REGISTER, RTC_CLOCK_DIVIDER | RTC_RATE_SELECT);
+
+  MrcOemOutPort8 (RTC_INDEX_REGISTER, CMOS_REGC);
+  MrcOemInPort8 (RTC_TARGET_REGISTER);
+
+  MrcOemOutPort8 (RTC_INDEX_REGISTER, CMOS_REGD);
+  MrcOemInPort8 (RTC_TARGET_REGISTER);
+
+  MrcOemOutPort8 (RTC_INDEX_REGISTER, CMOS_REGB);
+  MrcOemOutPort8 (RTC_TARGET_REGISTER, RTC_MODE_24HOUR);
+
+  return;
+}
+
+/**
+@brief
+  Returns the current time, as determined by reading the Real Time Clock (RTC) on the platform.
+  Since RTC time is stored in BCD, convert each value to binary.
+
+  @param[out] Seconds       - The current second (0-59).
+  @param[out] Minutes       - The current minute (0-59).
+  @param[out] Hours         - The current hour (0-23).
+  @param[out] DayOfMonth    - The current day of the month (1-31).
+  @param[out] Month         - The current month (1-12).
+  @param[out] Year          - The current year (2000-2099).
+
+  @retval Nothing.
+**/
+void
+MrcOemGetRtcTime (
+  OUT U8  *const Seconds,
+  OUT U8  *const Minutes,
+  OUT U8  *const Hours,
+  OUT U8  *const DayOfMonth,
+  OUT U8  *const Month,
+  OUT U16 *const Year
+  )
+{
+  if (0 == CheckUpdateComplete ()) {
+    InitRtc ();
+  }
+  //
+  // Read seconds
+  //
+  MrcOemOutPort8 (RTC_INDEX_REGISTER, RTC_SECONDS);
+  *Seconds = MrcOemInPort8 (RTC_TARGET_REGISTER);
+
+  //
+  // Read minutes
+  //
+  MrcOemOutPort8 (RTC_INDEX_REGISTER, RTC_MINUTES);
+  *Minutes = MrcOemInPort8 (RTC_TARGET_REGISTER);
+
+  //
+  // Read hours
+  //
+  MrcOemOutPort8 (RTC_INDEX_REGISTER, RTC_HOURS);
+  *Hours = MrcOemInPort8 (RTC_TARGET_REGISTER);
+
+  //
+  // Read day of month
+  //
+  MrcOemOutPort8 (RTC_INDEX_REGISTER, RTC_DAY_OF_MONTH);
+  *DayOfMonth = MrcOemInPort8 (RTC_TARGET_REGISTER);
+
+  //
+  // Read month
+  //
+  MrcOemOutPort8 (RTC_INDEX_REGISTER, RTC_MONTH);
+  *Month = MrcOemInPort8 (RTC_TARGET_REGISTER);
+
+  //
+  // Read year and add current century.
+  //
+  MrcOemOutPort8 (RTC_INDEX_REGISTER, RTC_YEAR);
+  *Year = MrcOemInPort8 (RTC_TARGET_REGISTER);
+
+  *Seconds    = BCD2BINARY (*Seconds);
+  *Minutes    = BCD2BINARY (*Minutes);
+  *Hours      = BCD2BINARY (*Hours);
+  *DayOfMonth = BCD2BINARY (*DayOfMonth);
+  *Month      = BCD2BINARY (*Month);
+  *Year       = BCD2BINARY (*Year) + CENTURY_OFFSET;
+}
+
+/**
+@brief
+  Read specific RTC/CMOS RAM
+
+  @param[in] Location        Point to RTC/CMOS RAM offset for read
+
+  @retval The data of specific location in RTC/CMOS RAM.
+**/
+U8
+RtcRead (
+  IN const U8 Location
+  )
+{
+  U8  RtcIndexPort;
+  U8  RtcDataPort;
+
+  //
+  // CMOS access registers (using alternative access not to handle NMI bit)
+  //
+  if (Location < RTC_BANK_SIZE) {
+    //
+    // First bank
+    //
+    RtcIndexPort  = R_PCH_RTC_INDEX_ALT;
+    RtcDataPort   = R_PCH_RTC_TARGET_ALT;
+  } else {
+    //
+    // Second bank
+    //
+    RtcIndexPort  = R_PCH_RTC_EXT_INDEX_ALT;
+    RtcDataPort   = R_PCH_RTC_EXT_TARGET_ALT;
+  }
+
+  MrcOemOutPort8 (RtcIndexPort, Location & RTC_INDEX_MASK);
+  return MrcOemInPort8 (RtcDataPort);
+}
+
+/**
+@brief
+  Write specific RTC/CMOS RAM
+
+  @param[in] Location        Point to RTC/CMOS RAM offset for write
+  @param[in] Value           The data that will be written to RTC/CMOS RAM
+**/
+void
+RtcWrite (
+  IN const U8 Location,
+  IN const U8 Value
+  )
+{
+  U8  RtcIndexPort;
+  U8  RtcDataPort;
+
+  //
+  // CMOS access registers (using alternative access not to handle NMI bit)
+  //
+  if (Location < RTC_BANK_SIZE) {
+    //
+    // First bank
+    //
+    RtcIndexPort  = R_PCH_RTC_INDEX_ALT;
+    RtcDataPort   = R_PCH_RTC_TARGET_ALT;
+  } else {
+    //
+    // Second bank
+    //
+    RtcIndexPort  = R_PCH_RTC_EXT_INDEX_ALT;
+    RtcDataPort   = R_PCH_RTC_EXT_TARGET_ALT;
+  }
+
+  MrcOemOutPort8 (RtcIndexPort, Location & RTC_INDEX_MASK);
+  MrcOemOutPort8 (RtcDataPort, Value);
+}
+
+/**
+@brief
+  Read word from specific RTC/CMOS RAM
+
+  @param[in] Location        Point to RTC/CMOS RAM offset for read
+
+  @retval The data of specific location in RTC/CMOS RAM.
+**/
+U16
+RtcRead16 (
+  IN const U8 Location
+  )
+{
+  return RtcRead (Location) | (RtcRead (Location + 1) << 8);
+}
+
+/**
+@brief
+  Write word to specific RTC/CMOS RAM
+
+  @param[in] Location        Point to RTC/CMOS RAM offset for write
+  @param[in] Value           The data that will be written to RTC/CMOS RAM
+**/
+void
+RtcWrite16 (
+  IN const U8   Location,
+  IN const U16  Value
+  )
+{
+  RtcWrite (Location, (U8) Value);
+  RtcWrite (Location + 1, (U8) (Value >> 8));
+}
diff --git a/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/MrcOemIo.h b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/MrcOemIo.h
new file mode 100644
index 0000000..916077b
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/MrcOemIo.h
@@ -0,0 +1,353 @@
+/** @file
+  This file contains the I/O port related definitions.
+
+@copyright
+  Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved.
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement.
+**/
+
+#ifndef _MrcOemIo_h_
+#define _MrcOemIo_h_
+#pragma pack (push, 1)
+
+#include "MrcTypes.h"
+
+#define RTC_INDEX_REGISTER        (0x70)
+#define RTC_TARGET_REGISTER       (0x71)
+#define R_PCH_RTC_INDEX_ALT       (0x74)
+#define R_PCH_RTC_TARGET_ALT      (0x75)
+#define R_PCH_RTC_EXT_INDEX_ALT   (0x76)
+#define R_PCH_RTC_EXT_TARGET_ALT  (0x77)
+
+#define RTC_INDEX_MASK            (0x7F)
+#define RTC_BANK_SIZE             (0x80)
+
+#define RTC_SECONDS               (0x00)
+#define RTC_MINUTES               (0x02)
+#define RTC_HOURS                 (0x04)
+#define RTC_DAY_OF_MONTH          (0x07)
+#define RTC_MONTH                 (0x08)
+#define RTC_YEAR                  (0x09)
+#define CMOS_REGA                 (0x0A)
+#define CMOS_REGB                 (0x0B)
+#define CMOS_REGC                 (0x0C)
+#define CMOS_REGD                 (0x0D)
+
+#define RTC_UPDATE_IN_PROGRESS    (0x80)
+#define RTC_HOLD                  (0x80)
+#define RTC_MODE_24HOUR           (0x02)
+#define RTC_CLOCK_DIVIDER         (0x20)
+#define RTC_RATE_SELECT           (0x06)
+
+#define BCD2BINARY(A)             (((((A) >> 4) & 0xF) * 10) + ((A) & 0xF))
+#define CENTURY_OFFSET            (2000)
+
+#define MRC_POST_CODE_LOW_BYTE_ADDR   (0x48)
+#define MRC_POST_CODE_HIGH_BYTE_ADDR  (0x49)
+
+/**
+@brief
+  8 bit I/O port read.
+
+  @param[in] IoAddress - The I/O port read address.
+
+  @retval The value read.
+**/
+extern
+U8
+MrcOemInPort8 (
+  IN const U16 IoAddress
+  );
+
+/**
+@brief
+  8 bit I/O port write.
+
+  @param[in] IoAddress - The I/O port read address.
+  @param[in] Data      - The value to write.
+
+  @retval Nothing.
+**/
+extern
+void
+MrcOemOutPort8 (
+  IN const U16 IoAddress,
+  IN const U8  Data
+  );
+
+/**
+@brief
+  16 bit I/O port read.
+
+  @param[in] IoAddress - The I/O port read address.
+
+  @retval The value read.
+**/
+extern
+U16
+MrcOemInPort16 (
+  IN const U16 IoAddress
+  );
+
+/**
+@brief
+  16 bit I/O port write.
+
+  @param[in] IoAddress - The I/O port read address.
+  @param[in] Data      - The value to write.
+
+  @retval Nothing.
+**/
+extern
+void
+MrcOemOutPort16 (
+  IN const U16 IoAddress,
+  IN const U16 Data
+  );
+
+/**
+@brief
+  32 bit I/O port read.
+
+  @param[in] IoAddress - The I/O port read address.
+
+  @retval The value read.
+**/
+extern
+U32
+MrcOemInPort32 (
+  IN const U16 IoAddress
+  );
+
+/**
+@brief
+  32 bit I/O port write.
+
+  @param[in] IoAddress - The I/O port read address.
+  @param[in] Data      - The value to write.
+
+  @retval Nothing.
+**/
+extern
+void
+MrcOemOutPort32 (
+  IN const U16 IoAddress,
+  IN const U32 Data
+  );
+
+/**
+@brief
+  The PCI index address.
+
+  @param[in] None.
+
+  @retval The PCI index address.
+**/
+extern
+U16
+MrcOemPciIndex (
+  void
+  );
+
+/**
+@brief
+  The PCI data address.
+
+  @param[in] None.
+
+  @retval The PCI data address.
+**/
+extern
+U16
+MrcOemPciData (
+  void
+  );
+
+/**
+@brief
+  Calculate the PCI device address for the given Bus/Device/Function/Offset.
+
+  @param[in] Bus      - PCI bus
+  @param[in] Device   - PCI device
+  @param[in] Function - PCI function
+  @param[in] Offset   - Offset
+
+  @retval The PCI device address.
+**/
+extern
+U32
+MrcOemGetPciDeviceAddress (
+  IN const U8 Bus,
+  IN const U8 Device,
+  IN const U8 Function,
+  IN const U8 Offset
+  );
+
+/**
+@brief
+  Calculate the PCIE device address for the given Bus/Device/Function/Offset.
+
+  @param[in] Bus      - PCI bus
+  @param[in] Device   - PCI device
+  @param[in] Function - PCI function
+  @param[in] Offset   - Offset
+
+   The PCIe device address.
+
+  @retval
+**/
+extern
+U32
+MrcOemGetPcieDeviceAddress (
+  IN const U8 Bus,
+  IN const U8 Device,
+  IN const U8 Function,
+  IN const U8 Offset
+  );
+
+/**
+@brief
+  Read 32-bit value from the specified bus/device/function/offset.
+
+  @param[in] bus      - PCI bus number.
+  @param[in] device   - PCI device number.
+  @param[in] function - PCI function number.
+  @param[in] offset   - PCI address offset.
+
+  @retval 32-bit PCI value.
+**/
+extern
+U32
+MrcOemPciRead32 (
+  IN const U8 bus,
+  IN const U8 device,
+  IN const U8 function,
+  IN const U8 offset
+  );
+
+/**
+@brief
+  Check if RTC date and time update is in progress and wait util it's finished.
+  We have at least 244us when "update in progress bit" is seen as low to
+  perform an operation on the RTC.
+
+  @param[in] None.
+
+  @retval Zero on timeout or non-zero and RTC is ready for transaction.
+**/
+extern
+U32
+CheckUpdateComplete (
+  void
+  );
+
+/**
+@brief
+  Initializes the RTC.
+
+  @param[in] None.
+
+  @retval Nothing.
+**/
+extern
+void
+InitRtc (
+  void
+  );
+
+/**
+@brief
+  Returns the current time, as determined by reading the Real Time Clock (RTC) on the platform.
+  Since RTC time is stored in BCD, convert each value to binary.
+
+  @param[out] Seconds       - The current second (0-59).
+  @param[out] Minutes       - The current minute (0-59).
+  @param[out] Hours         - The current hour (0-23).
+  @param[out] DayOfMonth    - The current day of the month (1-31).
+  @param[out] Month         - The current month (1-12).
+  @param[out] Year          - The current year (2000-2099).
+
+  @retval Nothing.
+**/
+extern
+void
+MrcOemGetRtcTime (
+  OUT U8  *const Seconds,
+  OUT U8  *const Minutes,
+  OUT U8  *const Hours,
+  OUT U8  *const DayOfMonth,
+  OUT U8  *const Month,
+  OUT U16 *const Year
+  );
+
+/**
+@brief
+  Read specific RTC/CMOS RAM
+
+  @param[in] Location        Point to RTC/CMOS RAM offset for read
+
+  @retval The data of specific location in RTC/CMOS RAM.
+**/
+extern
+U8
+RtcRead (
+  IN const U8 Location
+  );
+
+/**
+@brief
+  Write specific RTC/CMOS RAM
+
+  @param[in] Location        Point to RTC/CMOS RAM offset for write
+  @param[in] Value           The data that will be written to RTC/CMOS RAM
+**/
+extern
+void
+RtcWrite (
+  IN const U8 Location,
+  IN const U8 Value
+  );
+
+/**
+@brief
+  Read word from specific RTC/CMOS RAM
+
+  @param[in] Location        Point to RTC/CMOS RAM offset for read
+
+  @retval The data of specific location in RTC/CMOS RAM.
+**/
+extern
+U16
+RtcRead16 (
+  IN const U8 Location
+  );
+
+/**
+@brief
+  Write word to specific RTC/CMOS RAM
+
+  @param[in] Location        Point to RTC/CMOS RAM offset for write
+  @param[in] Value           The data that will be written to RTC/CMOS RAM
+**/
+extern
+void
+RtcWrite16 (
+  IN const U8   Location,
+  IN const U16  Value
+  );
+
+#pragma pack(pop)
+#endif // _MrcOemIo_h_
diff --git a/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/MrcOemMemory.c b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/MrcOemMemory.c
new file mode 100644
index 0000000..1d87c42
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/MrcOemMemory.c
@@ -0,0 +1,198 @@
+/** @file
+  This file contains the memory manipulation functions.
+
+@copyright
+  Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved.
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement.
+**/
+
+#ifdef MRC_MINIBIOS_BUILD
+#include "MemoryUtils.h"
+#else
+#include <Tiano.h>
+#include <EdkIIGlueDefinitionChangesBase.h>
+#include <EdkIIGluePeim.h>
+#include <EdkIIGlueBaseMemoryLib.h>
+#endif // MRC_MINIBIOS_BUILD
+#include "MrcTypes.h"
+#include "MrcOemMemory.h"
+
+/**
+@brief
+  Copy the specified number of memory bytes, a byte at a time, from the
+  specified source to the specified destination.
+
+  @param[in, out] Dest            - Destination pointer.
+  @param[in]      Src             - Source pointer.
+  @param[in]      NumBytes        - The number of bytes to copy.
+
+  @retval Nothing.
+**/
+void
+MrcOemMemoryCpy (
+  IN OUT U8 *Dest,
+  IN U8     *Src,
+  IN U32    NumBytes
+  )
+{
+  CopyMem (Dest, Src, NumBytes);
+  return;
+}
+
+/**
+@brief
+  Sets the specified number of memory bytes, a byte at a time, at the
+  specified destination.
+
+  @param[in, out] Dest            - Destination pointer.
+  @param[in]      Value           - The value to set.
+  @param[in]      NumBytes        - The number of bytes to set.
+
+  @retval Nothing.
+**/
+void
+MrcOemMemorySet (
+  IN OUT U8 *Dest,
+  IN U32    Value,
+  IN U32    NumBytes
+  )
+{
+  SetMem ((U8 *) Dest, NumBytes, (U8) Value);
+  return;
+}
+
+/**
+@brief
+  Sets the specified number of memory dwords, a dword at a time, at the
+  specified destination.
+
+  @param[in, out] Dest            - Destination pointer.
+  @param[in]      Value           - The value to set.
+  @param[in]      NumWords        - The number of dwords to set.
+
+  @retval Nothing.
+**/
+void
+MrcOemMemorySetWord (
+  IN OUT U16    *Dest,
+  IN const U16  Value,
+  IN U32        NumWords
+  )
+{
+  while (0 != NumWords--) {
+    *Dest++ = Value;
+  }
+
+  return;
+}
+
+/**
+@brief
+  Sets the specified number of memory dwords, a dword at a time, at the
+  specified destination.
+
+  @param[in, out] Dest            - Destination pointer.
+  @param[in]      Value           - The value to set.
+  @param[in]      NumDwords       - The number of dwords to set.
+
+  @retval Nothing.
+**/
+void
+MrcOemMemorySetDword (
+  IN OUT U32    *Dest,
+  IN const U32  Value,
+  IN U32        NumDwords
+  )
+{
+  while (0 != NumDwords--) {
+    *Dest++ = Value;
+  }
+
+  return;
+}
+
+/**
+@brief
+  Shift the specified data value left by the specified count.
+
+  @param[in] Data            - 64 bit number to shift left.
+  @param[in] Count           - Number of bits to shift (0..63)
+
+  @retval The number of bits shifted left.
+**/
+U64
+MrcOemMemoryLeftShiftU64 (
+  IN const U64 Data,
+  IN const U8  Count
+  )
+{
+  return LShiftU64 (Data, Count);
+}
+
+/**
+@brief
+  Shift the specified data value Right by the specified count..
+
+  @param[in] Data            - U64 number to shift
+  @param[in] Count           - number of bits to shift (0..63)
+
+  @retval Returns the shifted U64 value.
+**/
+U64
+MrcOemMemoryRightShiftU64 (
+  IN const U64 Data,
+  IN const U8  Count
+  )
+{
+  return RShiftU64 (Data, Count);
+}
+
+/**
+@brief
+  this function Multiply U64 with a U32 number. Result is <= 64 bits
+  need to be port for OEM platform requirements.
+
+  @param[in] Multiplicand  - U64 number to be multiplied with
+  @param[in] Multiplier - U32 number to multiply
+
+  @retval N/A
+**/
+U64
+MrcOemMemoryMultiplyU64ByU32 (
+  IN const U64 Multiplicand,
+  IN const U32 Multiplier
+  )
+{
+  return MultU64x32 (Multiplicand, Multiplier);
+}
+
+/**
+@brief
+  Divide U64 with a U64 number. Result is <= 32 bits
+
+  @param[in] Dividend  - U64 number to be multiplied with
+  @param[in] Divisor - U32 number to multiply
+
+  @retval Returns the quotient result of U32 value.
+**/
+U64
+MrcOemMemoryDivideU64ByU64 (
+  IN const U64 Dividend,
+  IN const U64 Divisor
+  )
+{
+  return (DivU64x64Remainder (Dividend, Divisor, NULL));
+}
diff --git a/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/MrcOemMemory.h b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/MrcOemMemory.h
new file mode 100644
index 0000000..08c6747
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/MrcOemMemory.h
@@ -0,0 +1,171 @@
+/** @file
+  This file contains the memory manipulation definitions.
+
+@copyright
+  Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved.
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement.
+**/
+
+#ifndef _MrcOemMemory_h_
+#define _MrcOemMemory_h_
+#pragma pack (push, 1)
+
+#include "MrcTypes.h"
+
+/**
+@brief
+  Copy the specified number of memory bytes, a byte at a time, from the
+  specified source to the specified destination.
+
+  @param[in, out] Dest            - Destination pointer.
+  @param[in]      Src             - Source pointer.
+  @param[in]      NumBytes        - The number of bytes to copy.
+
+  @retval Nothing.
+**/
+extern
+void
+MrcOemMemoryCpy (
+  IN OUT U8 *Dest,
+  IN U8     *Src,
+  IN U32    NumBytes
+  );
+
+/**
+@brief
+  Sets the specified number of memory bytes, a byte at a time, at the
+  specified destination.
+
+  @param[in, out] Dest            - Destination pointer.
+  @param[in]      Value           - The value to set.
+  @param[in]      NumBytes        - The number of bytes to set.
+
+  @retval Nothing.
+**/
+extern
+void
+MrcOemMemorySet (
+  IN OUT U8 *Dest,
+  IN U32    Value,
+  IN U32    NumBytes
+  );
+
+/**
+@brief
+  Sets the specified number of memory dwords, a dword at a time, at the
+  specified destination.
+
+  @param[in, out] Dest            - Destination pointer.
+  @param[in]      Value           - The value to set.
+  @param[in]      NumWords        - The number of dwords to set.
+
+  @retval Nothing.
+**/
+extern
+void
+MrcOemMemorySetWord (
+  IN OUT U16    *Dest,
+  IN const U16  Value,
+  IN U32        NumWords
+  );
+
+/**
+@brief
+  Sets the specified number of memory dwords, a dword at a time, at the
+  specified destination.
+
+  @param[in, out] Dest            - Destination pointer.
+  @param[in]      Value           - The value to set.
+  @param[in]      NumDwords       - The number of dwords to set.
+
+  @retval Nothing.
+**/
+extern
+void
+MrcOemMemorySetDword (
+  IN OUT U32    *Dest,
+  IN const U32  Value,
+  IN U32        NumDwords
+  );
+
+/**
+@brief
+  Shift the specified data value left by the specified count.
+
+  @param[in] Data            - 64 bit number to shift left.
+  @param[in] Count           - Number of bits to shift (0..63)
+
+  @retval The number of bits shifted left.
+**/
+extern
+U64
+MrcOemMemoryLeftShiftU64 (
+  IN const U64 Data,
+  IN const U8  Count
+  );
+
+/**
+@brief
+  Shift the specified data value Right by the specified count..
+
+  @param[in] Data            - U64 number to shift
+  @param[in] Count           - number of bits to shift (0..63)
+
+  @retval Returns the shifted U64 value.
+**/
+extern
+U64
+MrcOemMemoryRightShiftU64 (
+  IN const U64 Data,
+  IN const U8  Count
+  );
+
+/**
+@brief
+  this function Multiply U64 with a U32 number. Result is <= 64 bits
+  need to be port for OEM platform requirements.
+
+  @param[in] Multiplicand  - U64 number to be multiplied with
+  @param[in] Multiplier - U32 number to multiply
+
+  @retval N/A
+**/
+extern
+U64
+MrcOemMemoryMultiplyU64ByU32 (
+  IN const U64 Multiplicand,
+  IN const U32 Multiplier
+  );
+
+/**
+@brief
+  Divide U64 with a U64 number. Result is <= 32 bits
+
+  @param[in] Dividend  - U64 number to be multiplied with
+  @param[in] Divisor - U32 number to multiply
+
+  @retval Returns the quotient result of U32 value.
+**/
+extern
+U64
+MrcOemMemoryDivideU64ByU64 (
+  IN const U64 Dividend,
+  IN const U64 Divisor
+  )
+;
+
+#pragma pack (pop)
+#endif // _MrcOemMemory_h_
diff --git a/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/MrcOemMmio.c b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/MrcOemMmio.c
new file mode 100644
index 0000000..c2d80e6
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/MrcOemMmio.c
@@ -0,0 +1,302 @@
+/** @file
+  This file contains the memory mapped I/O manipulation functions.
+
+@copyright
+  Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved.
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement.
+**/
+
+#include "MrcTypes.h"
+#include "MrcOemMmio.h"
+
+/**
+@brief
+  Read 64 bits from the Memory Mapped I/O space.
+
+  @param[in]  Offset      - Offset from the specified base address.
+  @param[out] Value       - Where to store the read value.
+  @param[in]  BaseAddress - MMIO space base address.
+
+  @retval Nothing.
+**/
+void
+MrcOemMmioRead64 (
+  IN  U32 Offset,
+  OUT U64 *Value,
+  IN  U32 BaseAddress
+  )
+{
+  U64 MmxSave;
+  U64 *MmioOffset;
+
+  MmioOffset = (U64 *) (Offset + BaseAddress);
+
+#if defined __GNUC__  // GCC compiler
+  __asm__ __volatile__ (
+    "\n\t movq %%mm0, %0"
+    "\n\t movq %2, %%mm0"
+    "\n\t movq %%mm0, %1"
+    "\n\t movq %3, %%mm0"
+    "\n\t emms"
+    : "=m" (MmxSave),
+      "=m" (Value[0])
+    : "m" (MmioOffset[0]),
+      "m" (MmxSave)
+    );
+#else // MSFT compiler
+  ASM {
+
+    ; Save mm0
+    movq  MmxSave, mm0
+
+    mov   edi, MmioOffset
+
+    movq  mm0, QWORD PTR DS:[edi]
+
+    mov   edi, Value
+    movq  QWORD PTR DS:[edi], mm0
+
+    ; Restore mm0
+    movq  mm0, MmxSave
+    emms                     ; Exit mmx Instruction
+  }
+#endif
+
+  MmioReadCount ();
+  return;
+}
+
+/**
+@brief
+  Read 32 bits from the Memory Mapped I/O space.
+
+  @param[in]  Offset      - Offset from the specified base address.
+  @param[out] Value       - Where to store the read value.
+  @param[in]  BaseAddress - MMIO space base address.
+
+  @retval Nothing.
+**/
+void
+MrcOemMmioRead (
+  IN  U32 Offset,
+  OUT U32 *Value,
+  IN  U32 BaseAddress
+  )
+{
+  *Value = (*((volatile U32 *) (Offset + BaseAddress)));
+  MmioReadCount ();
+  return;
+}
+
+/**
+@brief
+  Read 16 bits from the Memory Mapped I/O space.
+
+  @param[in]  Offset      - Offset from the specified base address.
+  @param[out] Value       - Where to store the read value.
+  @param[in]  BaseAddress - MMIO space base address.
+
+  @retval Nothing.
+**/
+void
+MrcOemMmioRead16 (
+  IN  U32 Offset,
+  OUT U16 *Value,
+  IN  U32 BaseAddress
+  )
+{
+  *Value = (*((volatile U16 *) (Offset + BaseAddress)));
+  MmioReadCount ();
+  return;
+}
+
+/**
+@brief
+  Read 8 bits from the Memory Mapped I/O space.
+
+  @param[in]  Offset      - Offset from the specified base address.
+  @param[out] Value       - Where to store the read value.
+  @param[in]  BaseAddress - MMIO space base address.
+
+  @retval Nothing.
+**/
+void
+MrcOemMmioRead8 (
+  IN  U32 Offset,
+  OUT U8  *Value,
+  IN  U32 BaseAddress
+  )
+{
+  *Value = (*((volatile U8 *) (Offset + BaseAddress)));
+  MmioReadCount ();
+  return;
+}
+
+/**
+@brief
+  Write 64 bits to the Memory Mapped I/O space.
+
+  @param[in] Offset      - Offset from the specified base address.
+  @param[in] Value       - The value to write.
+  @param[in] BaseAddress - MMIO space base address.
+
+  @retval Nothing.
+**/
+void
+MrcOemMmioWrite64 (
+  IN U32 Offset,
+  IN U64 Value,
+  IN U32 BaseAddress
+  )
+{
+  U64 MmxSave;
+  U64 *MmioOffset;
+
+  MmioOffset = (U64 *) (Offset + BaseAddress);
+
+#if defined __GNUC__  // GCC compiler
+  __asm__ __volatile__ (
+    "\n\t movq %%mm0, %0"
+    "\n\t movq %2, %%mm0"
+    "\n\t movq %%mm0, %1"
+    "\n\t movq %3, %%mm0"
+    "\n\t emms"
+    : "=m" (MmxSave)
+    : "m" (MmioOffset[0]),
+      "m" (Value),
+      "m" (MmxSave)
+    );
+#else //MSFT compiler
+  ASM {
+
+    ; Save mm0
+    movq  MmxSave, mm0
+
+    mov   edi, MmioOffset
+    movq  mm0, Value
+
+    movq  QWORD PTR DS:[edi], mm0
+
+    ; Restore mm0
+    movq  mm0, MmxSave
+    emms                     ; Exit mmx Instruction
+
+  }
+#endif
+
+  MmioWriteCount ();
+  return;
+}
+
+/**
+@brief
+  Write 32 bits to the Memory Mapped I/O space.
+
+  @param[in] Offset      - Offset from the specified base address.
+  @param[in] Value       - The value to write.
+  @param[in] BaseAddress - MMIO space base address.
+
+  @retval Nothing.
+**/
+void
+MrcOemMmioWrite (
+  IN U32 Offset,
+  IN U32 Value,
+  IN U32 BaseAddress
+  )
+{
+  (*((volatile U32 *) (Offset + BaseAddress))) = Value;
+  MmioWriteCount ();
+  return;
+}
+
+/**
+@brief
+  Write 16 bits to the Memory Mapped I/O space.
+
+  @param[in] Offset      - Offset from the specified base address.
+  @param[in] Value       - The value to write.
+  @param[in] BaseAddress - MMIO space base address.
+
+  @retval Nothing.
+**/
+void
+MrcOemMmioWrite16 (
+  IN U32 Offset,
+  IN U16 Value,
+  IN U32 BaseAddress
+  )
+{
+  (*((volatile U16 *) (Offset + BaseAddress))) = Value;
+  MmioWriteCount ();
+  return;
+}
+
+/**
+@brief
+  Write 8 bits to the Memory Mapped I/O space.
+
+  @param[in] Offset      - Offset from the specified base address.
+  @param[in] Value       - The value to write.
+  @param[in] BaseAddress - MMIO space base address.
+
+  @retval Nothing.
+**/
+void
+MrcOemMmioWrite8 (
+  IN U32 Offset,
+  IN U8  Value,
+  IN U32 BaseAddress
+  )
+{
+  (*((volatile U8 *) (Offset + BaseAddress))) = Value;
+  MmioWriteCount ();
+  return;
+}
+#ifndef MRC_MINIBIOS_BUILD
+/*++
+
+@brief
+  This function count the number of access to writes MMIO registers.
+
+  @param[in] Nothing.
+
+  @retval Nothing.
+**/
+void
+MmioWriteCount (
+  void
+  )
+{
+  return;
+}
+
+/**
+@brief
+  This function count the number of access to reads MMIO registers.
+
+  @param[in] Nothing.
+
+  @retval Nothing.
+**/
+void
+MmioReadCount (
+  void
+  )
+{
+  return;
+}
+#endif // MRC_MINIBIOS_BUILD
diff --git a/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/MrcOemMmio.h b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/MrcOemMmio.h
new file mode 100644
index 0000000..f5621cd
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/MrcOemMmio.h
@@ -0,0 +1,192 @@
+/** @file
+
+  This file contains the memory mapped I/O manipulation definitions.
+
+@copyright
+  Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved.
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement.
+**/
+
+#ifndef _MrcOemMmio_h_
+#define _MrcOemMmio_h_
+
+#include "MrcTypes.h"
+
+/**
+@brief
+  Read 64 bits from the Memory Mapped I/O space.
+
+  @param[in]  Offset      - Offset from the specified base address.
+  @param[out] Value       - Where to store the read value.
+  @param[in]  BaseAddress - MMIO space base address.
+
+  @retval Nothing.
+**/
+extern
+void
+MrcOemMmioRead64 (
+  IN  U32 Offset,
+  OUT U64 *Value,
+  IN  U32 BaseAddress
+  );
+
+/**
+@brief
+  Read 32 bits from the Memory Mapped I/O space.
+
+  @param[in]  Offset      - Offset from the specified base address.
+  @param[out] Value       - Where to store the read value.
+  @param[in]  BaseAddress - MMIO space base address.
+
+  @retval Nothing.
+**/
+extern
+void
+MrcOemMmioRead (
+  IN  U32 Offset,
+  OUT U32 *Value,
+  IN  U32 BaseAddress
+  );
+
+/**
+@brief
+  Read 16 bits from the Memory Mapped I/O space.
+
+  @param[in]  Offset      - Offset from the specified base address.
+  @param[out] Value       - Where to store the read value.
+  @param[in]  BaseAddress - MMIO space base address.
+
+  @retval Nothing.
+**/
+extern
+void
+MrcOemMmioRead16 (
+  IN  U32 Offset,
+  OUT U16 *Value,
+  IN  U32 BaseAddress
+  );
+
+/**
+@brief
+  Read 8 bits from the Memory Mapped I/O space.
+
+  @param[in]  Offset      - Offset from the specified base address.
+  @param[out] Value       - Where to store the read value.
+  @param[in]  BaseAddress - MMIO space base address.
+
+  @retval Nothing.
+**/
+extern
+void
+MrcOemMmioRead8 (
+  IN  U32 Offset,
+  OUT U8  *Value,
+  IN  U32 BaseAddress
+  );
+
+/**
+@brief
+  Write 64 bits to the Memory Mapped I/O space.
+
+  @param[in] Offset      - Offset from the specified base address.
+  @param[in] Value       - The value to write.
+  @param[in] BaseAddress - MMIO space base address.
+
+  @retval Nothing
+**/
+extern
+void
+MrcOemMmioWrite64 (
+  IN U32 Offset,
+  IN U64 Value,
+  IN U32 BaseAddress
+  );
+
+/**
+@brief
+  Write 32 bits to the Memory Mapped I/O space.
+
+  @param[in] Offset      - Offset from the specified base address.
+  @param[in] Value       - The value to write.
+  @param[in] BaseAddress - MMIO space base address.
+
+  @retval Nothing.
+**/
+extern
+void
+MrcOemMmioWrite (
+  IN U32 Offset,
+  IN U32 Value,
+  IN U32 BaseAddress
+  );
+
+/**
+@brief
+  Write 16 bits to the Memory Mapped I/O space.
+
+  @param[in] Offset      - Offset from the specified base address.
+  @param[in] Value       - The value to write.
+  @param[in] BaseAddress - MMIO space base address.
+
+  @retval Nothing.
+**/
+extern
+void
+MrcOemMmioWrite16 (
+  IN U32 Offset,
+  IN U16 Value,
+  IN U32 BaseAddress
+  );
+
+/**
+@brief
+  Write 8 bits to the Memory Mapped I/O space.
+
+  @param[in] Offset      - Offset from the specified base address.
+  @param[in] Value       - The value to write.
+  @param[in] BaseAddress - MMIO space base address.
+
+  @retval Nothing.
+**/
+extern
+void
+MrcOemMmioWrite8 (
+  IN U32 Offset,
+  IN U8  Value,
+  IN U32 BaseAddress
+  );
+
+extern
+void
+MmioReadCount (
+  void
+  );
+
+/**
+@brief
+  This function count the number of access to writes MMIO registers.
+
+  @param[in] Nothing
+
+  @retval Nothing
+**/
+extern
+void
+MmioWriteCount (
+  void
+  );
+
+#endif // _MrcOemMmio_h_
diff --git a/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/MrcOemPlatform.c b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/MrcOemPlatform.c
new file mode 100644
index 0000000..d095c51
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/MrcOemPlatform.c
@@ -0,0 +1,2780 @@
+/** @file
+  This file contains platform related functions.
+
+@copyright
+  Copyright (c) 1999 - 2013 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement.
+
+**/
+
+#ifdef MRC_MINIBIOS_BUILD
+#include "MemoryUtils.h"
+#else
+#include <Tiano.h>
+#include <EdkIIGluePeim.h>
+#include <EdkIIGlueBaseLib.h>
+#include "CpuRegs.h"
+#include "CpuPlatformLib.h"
+#ifdef SSA_FLAG
+#include "SsaCallbackPeim.h"
+extern
+VOID
+SsaBiosInitialize (
+  IN MrcParameters       *MrcData
+  );
+#endif // SSA_FLAG
+#endif
+
+//
+// Include files
+//
+#ifndef AMI_OVERRIDE_FOR_MEMORY_DOWN
+#include <Token.h>
+#include "MrcSpdData.h"
+#endif // AMI_OVERRIDE_FOR_MEMORY_DOWN
+#include "MrcTypes.h"
+#include "MrcApi.h"
+#include "McAddress.h"
+#include "MrcCommon.h"
+#include "MrcGlobal.h"
+#include "MrcOem.h"
+#include "MrcOemPlatform.h"
+
+#include "PchRegsLpc.h"
+#include "MrcReset.h"
+
+
+// AMI_OVERRIDE_FOR_UPSERVER_SUPPORT
+#ifdef UPSERVER_SUPPORT
+#include "MrcOemSmbus.h"
+
+const U8 CltmThermalLookUpTable [2][2][2][5] =
+{
+    {// DRAM Density 2Gb
+        {// Frequency 1600
+            // 1 DIMM
+            {6, 6, 6, 6, 6},
+            // 2 DIMMs
+            {7, 7, 7, 6, 6}
+        },
+        {// Frequency 1333
+            // 1 DIMM
+            {5, 5, 5, 5, 5},
+            // 2 DIMMs
+            {6, 6, 6, 6, 5}
+        }
+    },
+    {// DRAM Density 4Gb
+        {// Frequency 1600
+            // 1 DIMM
+            {7, 6, 6, 6, 7},
+            // 2 DIMMs
+            {7, 7, 7, 7, 6}
+        },
+        {// Frequency 1333
+            // 1 DIMM
+            {6, 5, 5, 5, 6},
+            // 2 DIMMs
+            {7, 7, 6, 6, 6}
+        }
+    }
+};
+
+const U16 CltmPowerLookUpTable [2][2][2][8] =
+{
+    {// DRAM Density 2Gb
+        {// Frequency 1600
+            // DIMM Position 1
+            
+            {4, 99, 147, 129, 6, 10, 0x18, 0x0C},
+            // DIMM Position 2
+            {3, 182, 203, 64, 3, 5, 0x1B, 0x09}
+        },
+        {// Frequency 1333 
+            // DIMM Position 1
+            {4, 102, 160, 121, 7, 11, 0x15, 0x08},
+            // DIMM Position 2
+            {3, 210, 236, 60, 3, 5, 0x18, 0x0C}
+        }
+    },
+    {// DRAM Density 4Gb
+        {// Frequency 1600
+            // DIMM Position 1
+            {4, 111, 158, 132, 8, 12, 0x1B, 0x0E},
+            // DIMM Position 2
+            {3, 188, 209, 66, 4, 6, 0x1D, 0x07}
+        },
+        {// Frequency 1333
+            // DIMM Position 1
+            {4, 115, 171, 124, 9, 13, 0x17, 0x0A},
+            // DIMM Position 2
+            {3, 217, 241, 62, 4, 6, 0x1B, 0x09}
+        }
+    }
+};
+
+#endif
+// AMI_OVERRIDE_FOR_UPSERVER_SUPPORT
+
+#ifdef MRC_DEBUG_PRINT
+extern const char CcdString[];
+const char TrainEnString[]  = "TrainingEnables";
+const char GdxcString[]     = "Gdxc";
+const char BaseTimeString[] = "BaseTime";
+const char ThermEnString[]  = "ThermalEnables";
+#endif // MRC_DEBUG_PRINT
+
+#ifdef ULT_FLAG
+
+//
+// The following section contains board-specific CMD/CTL/CLK and DQ/DQS mapping, needed for LPDDR3
+//
+
+//
+// DQByteMap[0] - ClkDQByteMap:
+//   If clock is per rank, program to [0xFF, 0xFF]
+//   If clock is shared by 2 ranks, program to [0xFF, 0] or [0, 0xFF]
+//   If clock is shared by 2 ranks but does not go to all bytes,
+//           Entry[i] defines which DQ bytes Group i services
+// DQByteMap[1] - CmdNDQByteMap: Entry[0] is CmdN/CAA and Entry[1] is CmdN/CAB
+// DQByteMap[2] - CmdSDQByteMap: Entry[0] is CmdS/CAA and Entry[1] is CmdS/CAB
+// DQByteMap[3] - CkeDQByteMap : Entry[0] is CKE /CAA and Entry[1] is CKE /CAB
+//                For DDR, DQByteMap[3:1] = [0xFF, 0]
+// DQByteMap[4] - CtlDQByteMap : Always program to [0xFF, 0] since we have 1 CTL / rank
+//                               Variable only exists to make the code easier to use
+// DQByteMap[5] - CmdVDQByteMap: Always program to [0xFF, 0] since we have 1 CA Vref
+//                               Variable only exists to make the code easier to use
+//
+
+//
+// DQ byte mapping to CMD/CTL/CLK, from the CPU side - for Sawtooth Peak and Harris Beach
+//
+const U8 DqByteMapRvpCh0[6][2] = {
+  { 0x0F, 0xF0 }, // CLK0 goes to package 0 - Bytes[3:0], CLK1 goes to package 1 - Bytes[7:4]
+  { 0x00, 0xF0 }, // CmdN does not have CAA, CAB goes to Bytes[7:4]
+  { 0x0F, 0xF0 }, // CmdS CAA goes to Bytes[3:0], CmdS CAB goes to Byte[7:4]
+  { 0x0F, 0x00 }, // CKE CAA goes to Bytes[3:0], CKE does not have CAB
+  { 0xFF, 0x00 }, // CTL (CS) goes to all bytes
+  { 0xFF, 0x00 }  // CA Vref is one for all bytes
+};
+
+const U8 DqByteMapRvpCh1[6][2] = {
+  { 0x0F, 0xF0 }, // CLK0 goes to package 0 - Bytes[3:0], CLK1 goes to package 1 - Bytes[7:4]
+  { 0x00, 0xF0 }, // CmdN does not have CAA, CAB goes to Bytes[7:4]
+  { 0x0F, 0xF0 }, // CmdS CAA goes to Bytes[3:0], CmdS CAB goes to Byte[7:4]
+  { 0x0F, 0x00 }, // CKE CAA goes to Bytes[3:0], CKE does not have CAB
+  { 0xFF, 0x00 }, // CTL (CS) goes to all bytes
+  { 0xFF, 0x00 }  // CA Vref is one for all bytes
+};
+
+//
+// DQ byte mapping to CMD/CTL/CLK, from the CPU side - for Big Creek
+//
+const U8 DqByteMapSvCh0[6][2] = {
+  { 0x0F, 0xF0 }, // CLK0 goes to package 0 - Bytes[3:0], CLK1 goes to package 1 - Bytes[7:4]
+  { 0x00, 0xF0 }, // CmdN does not have CAA, CAB goes to Bytes[7:4]
+  { 0x0F, 0xF0 }, // CmdS CAA goes to Bytes[3:0], CmdS CAB goes to Byte[7:4]
+  { 0x0F, 0x00 }, // CKE CAA goes to Bytes[3:0], CKE does not have CAB
+  { 0xFF, 0x00 }, // CTL (CS) goes to all bytes
+  { 0xFF, 0x00 }  // CA Vref is one for all bytes
+};
+
+const U8 DqByteMapSvCh1[6][2] = {
+  { 0xE8, 0x17 }, // CLK0 goes to package 0 - Bytes[3:0], CLK1 goes to package 1 - Bytes[7:4]
+  { 0x00, 0x17 }, // CmdN does not have CAA, CAB goes to Bytes[7:4]
+  { 0xE8, 0x17 }, // CmdS CAA goes to Bytes[3:0], CmdS CAB goes to Byte[7:4]
+  { 0xE8, 0x00 }, // CKE CAA goes to Bytes[3:0], CKE does not have CAB
+  { 0xFF, 0x00 }, // CTL (CS) goes to all bytes
+  { 0xFF, 0x00 }  // CA Vref is one for all bytes
+};
+
+//
+// DQS byte swizzling between CPU and DRAM - for Sawtooth Peak and Harris Beach
+//
+const U8 DqsMapCpu2DramRvpCh0[8] = { 2, 0, 1, 3, 6, 4, 7, 5 };
+const U8 DqsMapCpu2DramRvpCh1[8] = { 1, 3, 2, 0, 5, 7, 6, 4 };
+
+//
+// DQS byte swizzling between CPU and DRAM - for Big Creek
+//
+const U8 DqsMapCpu2DramSvCh0[8] = { 0, 1, 2, 3, 5, 6, 7, 4 };
+const U8 DqsMapCpu2DramSvCh1[8] = { 7, 6, 5, 2, 4, 3, 1, 0 };
+
+//
+// DQ bit swizzling between CPU and DRAM - for Sawtooth Peak and Harris Beach
+//
+const U8 DqMapCpu2DramRvpCh0[8][8] = {
+  { 16, 21, 18, 19, 20, 17, 22, 23 },  // Byte 0
+  {  3,  6,  1,  5,  2,  7,  0,  4 },  // Byte 1
+  {  9,  8, 14, 15, 10, 11, 13, 12 },  // Byte 2
+  { 29, 28, 27, 31, 24, 25, 30, 26 },  // Byte 3
+  { 53, 49, 50, 51, 48, 52, 54, 55 },  // Byte 4
+  { 35, 38, 33, 37, 34, 39, 32, 36 },  // Byte 5
+  { 63, 59, 61, 57, 56, 60, 58, 62 },  // Byte 6
+  { 44, 45, 46, 42, 40, 41, 43, 47 }   // Byte 7
+};
+const U8 DqMapCpu2DramRvpCh1[8][8] = {
+  { 15, 11,  8,  9, 10, 14, 12, 13 },  // Byte 0
+  { 24, 29, 30, 26, 28, 25, 27, 31 },  // Byte 1
+  { 16, 20, 22, 23, 17, 21, 19, 18 },  // Byte 2
+  {  6,  3,  1,  5,  2,  7,  4,  0 },  // Byte 3
+  { 47, 42, 40, 41, 43, 46, 44, 45 },  // Byte 4
+  { 57, 56, 62, 58, 61, 60, 59, 63 },  // Byte 5
+  { 51, 49, 54, 53, 48, 50, 55, 52 },  // Byte 6
+  { 38, 35, 36, 32, 34, 39, 33, 37 }   // Byte 7
+};
+
+//
+// DQ bit swizzling between CPU and DRAM - for Big Creek
+//
+const U8 DqMapCpu2DramSvCh0[8][8] = {
+  {  1,  0,  2,  6,  5,  4,  3,  7 },  // Byte 0
+  { 13,  9, 14, 10, 12,  8, 15, 11 },  // Byte 1
+  { 22, 18, 21, 16, 17, 20, 19, 23 },  // Byte 2
+  { 29, 28, 26, 27, 30, 31, 24, 25 },  // Byte 3
+  { 41, 45, 46, 42, 40, 44, 43, 47 },  // Byte 4
+  { 53, 49, 54, 50, 52, 48, 55, 51 },  // Byte 5
+  { 63, 62, 61, 60, 59, 58, 57, 56 },  // Byte 6
+  { 34, 35, 37, 36, 38, 39, 33, 32 }   // Byte 7
+};
+const U8 DqMapCpu2DramSvCh1[8][8] = {
+  { 58, 62, 57, 61, 59, 63, 56, 60 },  // Byte 0
+  { 54, 50, 53, 49, 55, 51, 52, 48 },  // Byte 1
+  { 46, 47, 45, 44, 43, 42, 41, 40 },  // Byte 2
+  { 22, 19, 23, 18, 16, 21, 20, 17 },  // Byte 3
+  { 38, 34, 37, 33, 39, 35, 36, 32 },  // Byte 4
+  { 26, 30, 25, 29, 27, 31, 24, 28 },  // Byte 5
+  { 15, 11,  9, 13, 14, 10, 12,  8 },  // Byte 6
+  {  6,  7,  0,  1,  4,  5,  3,  2 }   // Byte 7
+};
+
+#endif // ULT_FLAG
+
+const MrcVddSelect MemoryVoltageTable[] = {
+  //
+  //                       MB     DT                  MB    DT
+  // Voltage         //  GPIO24/GPIO60   GPIO46     GPIO8/GPIO45
+  //
+  1650,           //    0               0            0
+  1600,           //    0               0            1
+  1550,           //    0               1            0
+  1503,           //    0               1            1
+  1500,           //    1               0            0
+  1450,           //    1               0            1
+  1400,           //    1               1            0
+  1350            //    1               1            1
+};
+
+/**
+  Gets CPU ratio
+
+  @param[in] Nothing
+
+  @retval Cpu ratio.
+**/
+U32
+MrcGetCpuRatio (
+  void
+  )
+{
+  PCU_CR_PLATFORM_INFO_STRUCT Msr;
+
+  Msr.Data = AsmReadMsr64 (PCU_CR_PLATFORM_INFO);
+  return (Msr.Bits.MAX_NON_TURBO_LIM_RATIO);
+}
+
+/**
+  Gets CPU current time.
+
+  @param[in] Nothing
+
+  @retval The current CPU time in milliseconds.
+**/
+U64
+MrcGetCpuTime (
+  void
+  )
+{
+  U32 TimeBase;
+
+  TimeBase = (1000 * MRC_SYSTEM_BCLK) * MrcGetCpuRatio (); //In Millisec
+  return ((TimeBase == 0) ? 0 : MrcOemMemoryDivideU64ByU64 (AsmReadTsc (), TimeBase));
+}
+
+/**
+  Sets CpuModel and CpuStepping in MrcData based on CpuModelStep.
+
+  @param[out] MrcData     - The Mrc Host data structure
+  @param[in]  CpuModel    - The CPU Family Model.
+  @param[in]  CpuStepping - The CPU Stepping.
+
+  @retval - mrcSuccess if the model and stepping is found.  Otherwise mrcFail
+**/
+MrcStatus
+MrcSetCpuInformation (
+  OUT MrcParameters  *MrcData,
+  IN  MrcCpuModel    CpuModel,
+  IN  MrcCpuStepping CpuStepping
+  )
+{
+  MrcInput  *Inputs;
+  MrcDebug  *Debug;
+  MrcStatus Status;
+
+  Inputs = &MrcData->SysIn.Inputs;
+  Debug  = &MrcData->SysIn.Inputs.Debug;
+  Status = mrcFail;
+
+#ifdef ULT_FLAG
+  if (CpuModel == cmHSW_ULT) {
+    Inputs->CpuModel = cmHSW_ULT;
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Haswell ULT:");
+
+    switch (CpuStepping) {
+      case csHswUltB0:
+        Inputs->CpuStepping = csHswUltB0;
+        MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, " Stepping B0\n");
+        break;
+
+      case csHswUltC0:
+        Inputs->CpuStepping = csHswUltC0;
+        MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, " Stepping C0\n");
+        break;
+
+      default:
+        Inputs->CpuStepping = csHswUltB0;   // @todo: Update for C0.
+        MRC_DEBUG_MSG (
+          Debug,
+          MSG_LEVEL_WARNING,
+          "\nWARNING: Unknown CPU stepping, using MRC for last known step. Step = %Xh\n",
+          Inputs->CpuStepping
+          );
+        break;
+    }
+    Status = mrcSuccess;
+  }
+#endif // ULT_FLAG
+
+#ifdef TRAD_FLAG
+  if (CpuModel == cmHSW) {
+    Inputs->CpuModel = cmHSW;
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Haswell:");
+
+    switch (CpuStepping) {
+      case csHswA0:
+        Inputs->CpuStepping = csHswA0;
+        MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, " Stepping A0\n");
+        break;
+
+      case csHswB0:
+        Inputs->CpuStepping = csHswB0;
+        MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, " Stepping B0\n");
+        break;
+
+      case csHswC0:
+        Inputs->CpuStepping = csHswC0;
+        MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, " Stepping C0\n");
+        break;
+
+      default:
+        Inputs->CpuStepping = csHswC0;
+        MRC_DEBUG_MSG (
+          Debug,
+          MSG_LEVEL_WARNING,
+          "\nWARNING: Unknown CPU stepping, using MRC for last known step. Step = %Xh\n",
+          Inputs->CpuStepping
+          );
+        break;
+    }
+    Status = mrcSuccess;
+  }
+
+  if (CpuModel == cmCRW) {
+    Inputs->CpuModel = cmCRW;
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Crystalwell:");
+
+    switch (CpuStepping) {
+      case csCrwB0:
+        Inputs->CpuStepping = csCrwB0;
+        MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, " Stepping B0\n");
+        break;
+
+      case csCrwC0:
+        Inputs->CpuStepping = csCrwC0;
+        MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, " Stepping C0\n");
+        break;
+
+      default:
+        Inputs->CpuStepping = csCrwB0;  // @todo: Update for C0
+        MRC_DEBUG_MSG (
+          Debug,
+          MSG_LEVEL_WARNING,
+          "\nWARNING: Unknown CPU stepping, using MRC for last known step. Step = %Xh\n",
+          Inputs->CpuStepping
+          );
+        break;
+    }
+    Status = mrcSuccess;
+  }
+#endif // TRAD_FLAG
+
+  return Status;
+}
+
+/**
+  Gets a number from the CPU's random number generator.
+
+  @param[in] Nothing
+
+  @retval   Random number or zero if random number is not generated or is invalid.
+**/
+U32
+AsmGetRandomNumber (
+  void
+  )
+{
+  U32 Status;
+  U32 RandomNumber;
+
+  // Assembly instruction to read CPU's random number generator
+  // Instruction is only available 100k cycles after reset
+  // rdrand eax
+  // db 0Fh, 0C7h, 0F0h
+#if defined __GNUC__  // GCC compiler
+  __asm__ __volatile__ (
+    "\n\t .byte 0x0F, 0xC7, 0xF0"
+    "\n\t movl %%eax, %0"
+    "\n\t pushf"
+    "\n\t pop %%eax"
+    "\n\t movl %%eax, %1"
+    : "=m" (RandomNumber),
+      "=m" (Status)
+    );
+#else //MSFT compiler
+  ASM {
+    _emit   0x0F
+    _emit   0xC7
+    _emit   0xF0
+    mov     RandomNumber, eax
+
+    pushfd
+    pop     eax
+    mov     Status, eax
+  }
+#endif
+  // If CF is cleared, return 0
+  return (((Status & 1) == 0) ? 0 : RandomNumber);
+}
+
+/**
+  Gets a random number from the CPU's random number generator.
+
+  @param[in] Nothing
+
+  @retval Random number returned by the CPU instruction or generated from real time clock data.
+**/
+U32
+MrcGetRandomNumber (
+  void
+  )
+{
+  U32 RandomNumber;
+  U32 Retry;
+  U16 Year;
+  U8  Month;
+  U8  DayOfMonth;
+  U8  Hours;
+  U8  Minutes;
+  U8  Seconds;
+
+  RandomNumber = 0;
+  for (Retry = 100000; ((Retry != 0) && (RandomNumber == 0)); --Retry) {
+    RandomNumber = AsmGetRandomNumber ();
+  }
+  if ((Retry == 0) && (RandomNumber == 0)) {
+    MrcOemGetRtcTime (&Seconds, &Minutes, &Hours, &DayOfMonth, &Month, &Year);
+    RandomNumber = Seconds + (Minutes * 60) + (Hours * 60 * 60);
+  }
+
+  return (RandomNumber);
+}
+
+/**
+  This function enables 2x Refresh through the mailbox.
+
+  @param[in]  MrcData - Pointer to the MRC global data structure
+
+  @retval - Nothing.
+**/
+void
+MrcOemEnable2xRefresh (
+  IN MrcParameters *const MrcData
+  )
+{
+#ifndef MRC_MINIBIOS_BUILD
+  MrcDebug            *Debug;
+  MrcMailbox2xRefresh Write2xRefreshData;
+  U32                 MailboxStatus;
+
+  Debug  = &MrcData->SysIn.Inputs.Debug;
+
+  MailboxRead(MAILBOX_TYPE_PCODE, READ_DDR_FORCE_2X_REFRESH, &Write2xRefreshData.Data, &MailboxStatus);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, " Read Write2xRefreshData: 0x%x\n", Write2xRefreshData.Data);
+
+
+  if (!Write2xRefreshData.Bits.Lock_Bit) {
+    Write2xRefreshData.Bits.Lock_Bit          = 1;
+    Write2xRefreshData.Bits.Enable_2x_Refresh = 1;
+#ifdef ULT_FLAG
+    if (MrcData->SysOut.Outputs.DdrType == MRC_DDR_TYPE_LPDDR3) {
+      Write2xRefreshData.Bits.LPDDR_Min_MR4 = RefRate2x; // Matches the JEDEC MR4 Encoding.
+    }
+#endif
+    MailboxWrite(MAILBOX_TYPE_PCODE, WRITE_DDR_FORCE_2X_REFRESH, Write2xRefreshData.Data, &MailboxStatus);
+
+    if (MailboxStatus != PCODE_MAILBOX_CC_SUCCESS) {
+      MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "WRITE_DDR_FORCE_2X_REFRESH failed.  MailboxStatus = 0x%x\n", MailboxStatus);
+    } else {
+      MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Writing 0x%x to WRITE_DDR_FORCE_2X_REFRESH\n", Write2xRefreshData.Data);
+    }
+  }
+#endif
+}
+
+/**
+  This function changes the DIMM Voltage to the closest desired voltage without
+  going higher. Default wait time is the minimum value of 200us, if more time
+  is needed before deassertion of DIMM Reset#, then change the parameter.
+
+  @param[in, out] MrcData            - The MRC "global data" area.
+  @param[in]      VddVoltage         - Selects the DDR voltage to use, in mV.
+  @param[in, out] VddSettleWaitTime  - Time needed for Vdd to settle after the update
+
+  @retval TRUE if a voltage change occurred, otherwise FALSE.
+**/
+BOOL
+MrcOemVDDVoltageCheckAndSwitch (
+  IN OUT MrcParameters      *MrcData,
+  IN     const MrcVddSelect VddVoltage,
+  IN OUT U32 * const        VddSettleWaitTime
+  )
+{
+  MrcInput  *Inputs;
+  MrcOutput *Outputs;
+  BOOL      Status;
+  U32       GPIOBase;
+  U32       GPIO_In_31_0;
+  U32       GPIO_In_63_32;
+  U32       GPIO_Out_31_0;
+  U32       GPIO_Out_63_32;
+  U32       Current;
+  U8        Index;
+
+  Inputs  = &MrcData->SysIn.Inputs;
+  Outputs = &MrcData->SysOut.Outputs;
+  Status  = FALSE;
+
+  if (((Inputs->MobilePlatform == TRUE) && (Inputs->BoardType != btUser4)) || (Inputs->MobilePlatform == FALSE)) {
+    //
+    // Read GPIO base.
+    //
+    MrcOemMmioRead (
+      MrcOemGetPcieDeviceAddress (0, PCI_DEVICE_NUMBER_PCH_LPC, 0, R_PCH_LPC_GPIO_BASE),
+      &GPIOBase,
+      Inputs->PciEBaseAddress
+      );
+    GPIOBase &= ~MRC_BIT0;
+
+#ifdef MRC_MINIBIOS_BUILD
+    if ((Inputs->MobilePlatform == TRUE) && (Inputs->BoardType != btUser4)) {
+      //
+      // Setup GPIOs (8,24,46)
+      //
+      GPIO_In_31_0 = MrcOemInPort32 ((U16) (GPIOBase + R_PCH_GPIO_USE_SEL));
+      if ((GPIO_In_31_0 & (MRC_BIT8 | MRC_BIT24)) != (MRC_BIT8 | MRC_BIT24)) {
+        GPIO_In_31_0 |= (MRC_BIT8 | MRC_BIT24);
+        MrcOemOutPort32 ((U16) (GPIOBase + R_PCH_GPIO_USE_SEL), GPIO_In_31_0);
+      }
+
+      GPIO_In_63_32 = MrcOemInPort32 ((U16) (GPIOBase + R_PCH_GPIO_USE_SEL2));
+      if ((GPIO_In_63_32 & MRC_BIT14) != MRC_BIT14) {
+        GPIO_In_63_32 |= MRC_BIT14;
+        MrcOemOutPort32 ((U16) (GPIOBase + R_PCH_GPIO_USE_SEL2), GPIO_In_63_32);
+      }
+
+      GPIO_In_31_0 = MrcOemInPort32 ((U16) (GPIOBase + R_PCH_GPIO_IO_SEL));
+      if ((GPIO_In_31_0 & (MRC_BIT8 | MRC_BIT24)) != 0) {
+        GPIO_In_31_0 &= ~(MRC_BIT8 | MRC_BIT24);
+        MrcOemOutPort32 ((U16) (GPIOBase + R_PCH_GPIO_IO_SEL), GPIO_In_31_0);
+      }
+
+      GPIO_In_63_32 = MrcOemInPort32 ((U16) (GPIOBase + R_PCH_GPIO_IO_SEL2));
+      if ((GPIO_In_63_32 & MRC_BIT14) != 0) {
+        GPIO_In_63_32 &= ~MRC_BIT14;
+        MrcOemOutPort32 ((U16) (GPIOBase + R_PCH_GPIO_IO_SEL2), GPIO_In_63_32);
+      }
+    } else if ((Inputs->MobilePlatform == FALSE) && (Inputs->BoardType == btCRBDT)) {
+      //
+      // Setup GPIOs (45,46,60)
+      //
+      GPIO_In_63_32 = MrcOemInPort32 ((U16) (GPIOBase + R_PCH_GPIO_USE_SEL2));
+      if ((GPIO_In_63_32 & (MRC_BIT28 | MRC_BIT14 | MRC_BIT13)) != (MRC_BIT28 | MRC_BIT14 | MRC_BIT13)) {
+        GPIO_In_63_32 |= (MRC_BIT28 | MRC_BIT14 | MRC_BIT13);
+        MrcOemOutPort32 ((U16) (GPIOBase + R_PCH_GPIO_USE_SEL2), GPIO_In_63_32);
+      }
+
+      GPIO_In_63_32 = MrcOemInPort32 ((U16) (GPIOBase + R_PCH_GPIO_IO_SEL2));
+      if ((GPIO_In_63_32 & (MRC_BIT28 | MRC_BIT14 | MRC_BIT13)) != 0) {
+        GPIO_In_63_32 &= ~(MRC_BIT28 | MRC_BIT14 | MRC_BIT13);
+        MrcOemOutPort32 ((U16) (GPIOBase + R_PCH_GPIO_IO_SEL2), GPIO_In_63_32);
+      }
+    }
+#endif // MRC_MINIBIOS_BUILD
+
+    GPIO_In_31_0   = MrcOemInPort32 ((U16) (GPIOBase + R_PCH_GPIO_LVL));
+    GPIO_In_63_32  = MrcOemInPort32 ((U16) (GPIOBase + R_PCH_GPIO_LVL2));
+    GPIO_Out_31_0  = GPIO_In_31_0;
+    GPIO_Out_63_32 = GPIO_In_63_32;
+
+    for (Index = 0; Index < (sizeof (MemoryVoltageTable) / sizeof (MemoryVoltageTable[0])); Index++) {
+      if (VddVoltage >= MemoryVoltageTable[Index]) {
+        break;
+      }
+    }
+
+#ifdef EMBEDDED_FLAG
+    if (Inputs->BoardType == btCRBEMB) {
+      //
+      // Set GP24 to the required value.
+      //
+      Current = (((GPIO_Out_31_0 & MRC_BIT24) >> 22) ^ MRC_BIT2) | MRC_BIT1 | MRC_BIT0;
+      (Index & MRC_BIT1) ? (GPIO_Out_31_0  &= (~MRC_BIT24)) : (GPIO_Out_31_0  |= MRC_BIT24);
+    } else
+#endif
+
+    if ((Inputs->MobilePlatform == TRUE) && (Inputs->BoardType != btUser4)) {
+      //
+      // Set GP8, GP24, and GP46 to the required value.
+      //
+      Current = (((GPIO_Out_31_0 & MRC_BIT24) >> 22) | ((GPIO_Out_63_32 & MRC_BIT14) >> 13) | ((GPIO_Out_31_0 & MRC_BIT8) >> 8));
+      (Index & MRC_BIT2) ? (GPIO_Out_31_0  |= MRC_BIT24) : (GPIO_Out_31_0  &= (~MRC_BIT24));
+      (Index & MRC_BIT1) ? (GPIO_Out_63_32 |= MRC_BIT14) : (GPIO_Out_63_32 &= (~MRC_BIT14));
+      (Index & MRC_BIT0) ? (GPIO_Out_31_0  |= MRC_BIT8)  : (GPIO_Out_31_0  &= (~MRC_BIT8));
+    } else if ((Inputs->MobilePlatform == FALSE) && (Inputs->BoardType == btCRBDT)) {
+      //
+      // Set GP45, GP46, and GP60 to the required value.
+      //
+      Current = (((GPIO_Out_63_32 & MRC_BIT28) >> 26) | ((GPIO_Out_63_32 & MRC_BIT14) >> 13) | ((GPIO_Out_63_32 & MRC_BIT13) >> 13));
+      (Index & MRC_BIT2) ? (GPIO_Out_63_32 |= MRC_BIT28) : (GPIO_Out_63_32 &= (~MRC_BIT28));
+      (Index & MRC_BIT1) ? (GPIO_Out_63_32 |= MRC_BIT14) : (GPIO_Out_63_32 &= (~MRC_BIT14));
+      (Index & MRC_BIT0) ? (GPIO_Out_63_32 |= MRC_BIT13) : (GPIO_Out_63_32 &= (~MRC_BIT13));
+    } else {
+      Current = 4;
+    }
+
+    MRC_DEBUG_MSG (&Inputs->Debug, MSG_LEVEL_NOTE, "Current VddVoltage is %u mV\n", MemoryVoltageTable[Current]);
+    if ((GPIO_In_31_0 != GPIO_Out_31_0) || (GPIO_In_63_32 != GPIO_Out_63_32)) {
+        MRC_DEBUG_MSG (&Inputs->Debug, MSG_LEVEL_NOTE, "**** VddVoltage updated to %u mV\n", VddVoltage);
+        MrcOemOutPort32 ((U16) (GPIOBase + R_PCH_GPIO_LVL), GPIO_Out_31_0);
+        MrcOemOutPort32 ((U16) (GPIOBase + R_PCH_GPIO_LVL2), GPIO_Out_63_32);
+        Status = TRUE;
+    }
+
+    //
+    // Increase the VddSettleWaitTime by the amount requested in the Input structure
+    //
+    *VddSettleWaitTime += Inputs->VddSettleWaitTime;
+
+    //
+    // Either update was already done or change is not necessary every time this is called
+    //
+    Outputs->VddVoltageDone = TRUE;
+  }
+
+  return (Status);
+}
+
+/**
+  Hook before normal mode is enabled.
+
+  @param[in, out] MrcData  - The MRC "global data" area.
+
+  @retval Nothing.
+**/
+void
+MrcOemBeforeNormalModeTestMenu (
+  IN OUT MrcParameters *const MrcData
+  )
+{
+
+  return;
+}
+
+/**
+  Hook after normal mode is enabled
+
+  @param[in] MrcData  - The MRC "global data" area.
+
+  @retval Nothing.
+**/
+void
+MrcOemAfterNormalModeTestMenu (
+  IN MrcParameters *MrcData
+  )
+{
+
+  MrcThermalOverwrites (MrcData);
+
+  // @todo: Add lates code  DDR Thermal Management, throttling control. Also UP CLTT code
+  //
+// AMI_OVERRIDE_FOR_UPSERVER_SUPPORT
+#ifdef UPSERVER_SUPPORT
+  MrcCltmInit (MrcData);
+#endif // UPSERVER_SUPPORT
+// AMI_OVERRIDE_FOR_UPSERVER_SUPPORT
+  return;
+}
+
+/**
+  Overwrite Thermal settings
+
+  @param[in] MrcData  - The MRC "global data" area.
+
+  @retval Nothing.
+**/
+void
+MrcThermalOverwrites (
+  IN MrcParameters *MrcData
+  )
+{
+  MrcInput                                        *Inputs;
+  MrcOutput                                       *Outputs;
+  MrcDebug                                        *Debug;
+  MrcDdrType                                      DdrType;
+  ThermalMngmtEn                                  *ThermalEnables;
+  U8                                              Channel;
+  U32                                             Offset;
+  PCU_CR_DDR_PTM_CTL_PCU_STRUCT                   DdrPtmCtl;
+  PCU_CR_DDR_ENERGY_SCALEFACTOR_PCU_STRUCT        DdrEnergyScaleFactor;
+  PCU_CR_DDR_RAPL_CHANNEL_POWER_FLOOR_PCU_STRUCT  DdrRaplChannelPowerFloor;
+  PCU_CR_DDR_RAPL_LIMIT_PCU_STRUCT                DdrRaplLimit;
+  PCU_CR_DDR_WARM_THRESHOLD_CH0_PCU_STRUCT        DdrWarmThresholdCh0;
+  PCU_CR_DDR_WARM_THRESHOLD_CH1_PCU_STRUCT        DdrWarmThresholdCh1;
+  PCU_CR_DDR_HOT_THRESHOLD_CH0_PCU_STRUCT         DdrHotThresholdCh0;
+  PCU_CR_DDR_HOT_THRESHOLD_CH1_PCU_STRUCT         DdrHotThresholdCh1;
+  PCU_CR_DDR_WARM_BUDGET_CH0_PCU_STRUCT           DdrWarmBudgetCh0;
+  PCU_CR_DDR_WARM_BUDGET_CH1_PCU_STRUCT           DdrWarmBudgetCh1;
+  PCU_CR_DDR_HOT_BUDGET_CH0_PCU_STRUCT            DdrHotBudgetCh0;
+  PCU_CR_DDR_HOT_BUDGET_CH1_PCU_STRUCT            DdrHotBudgetCh1;
+  MCHBAR_CH0_CR_PM_DIMM_IDLE_ENERGY_STRUCT        PmDimmIdleEnergy;
+  MCHBAR_CH0_CR_PM_DIMM_PD_ENERGY_STRUCT          PmDimmPdEnergy;
+  MCHBAR_CH0_CR_PM_DIMM_ACT_ENERGY_STRUCT         PmDimmActEnergy;
+  MCHBAR_CH0_CR_PM_DIMM_RD_ENERGY_STRUCT          PmDimmRdEnergy;
+  MCHBAR_CH0_CR_PM_DIMM_WR_ENERGY_STRUCT          PmDimmWrEnergy;
+  MCHBAR_CH0_CR_PM_THRT_CKE_MIN_STRUCT            PmThrtCkeMin;
+  MCDECS_CR_PM_SREF_CONFIG_MCMAIN_STRUCT          PmSrefConfig;
+
+  Inputs          = &MrcData->SysIn.Inputs;
+  Debug           = &Inputs->Debug;
+  ThermalEnables  = &Inputs->ThermalEnables;
+  Outputs         = &MrcData->SysOut.Outputs;
+  DdrType         = Outputs->DdrType;
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "...Thermal Overwrite ...\n");
+
+  if (Inputs->ThermalEnables.UserPowerWeightsEn) {
+    //
+    // ENERGY SCALE FACTOR
+    //
+    DdrEnergyScaleFactor.Data             = 0;
+    DdrEnergyScaleFactor.Bits.SCALEFACTOR = ThermalEnables->EnergyScaleFact;
+    MRC_DEBUG_MSG (
+      Debug,
+      MSG_LEVEL_NOTE,
+      "DDR_ENERGY_SCALEFACTOR %Xh: %Xh \n",
+      PCU_CR_DDR_ENERGY_SCALEFACTOR_PCU_REG,
+      DdrEnergyScaleFactor.Data
+      );
+    MrcWriteCR (MrcData, PCU_CR_DDR_ENERGY_SCALEFACTOR_PCU_REG, DdrEnergyScaleFactor.Data);
+
+    //
+    // RAPL POWER FLOOR
+    //
+    DdrRaplChannelPowerFloor.Data     = 0;
+    DdrRaplChannelPowerFloor.Bits.CH0 = ThermalEnables->RaplPwrFl[0];
+    DdrRaplChannelPowerFloor.Bits.CH1 = ThermalEnables->RaplPwrFl[1];
+    MRC_DEBUG_MSG (
+      Debug,
+      MSG_LEVEL_NOTE,
+      "DDR_RAPL_CHANNEL_POWER_FLOOR %Xh: %Xh \n",
+      PCU_CR_DDR_RAPL_CHANNEL_POWER_FLOOR_PCU_REG,
+      DdrRaplChannelPowerFloor.Data
+      );
+    MrcWriteCR (MrcData, PCU_CR_DDR_RAPL_CHANNEL_POWER_FLOOR_PCU_REG, DdrRaplChannelPowerFloor.Data);
+  }
+
+  //
+  // RAPL LIMIT
+  //
+  DdrRaplLimit.Data                       = 0;
+  DdrRaplLimit.Bits.LIMIT1_TIME_WINDOW_X  = ThermalEnables->RaplLim1WindX;
+  DdrRaplLimit.Bits.LIMIT1_TIME_WINDOW_Y  = ThermalEnables->RaplLim1WindY;
+  DdrRaplLimit.Bits.LIMIT1_ENABLE         = ThermalEnables->RaplLim1Ena;
+  DdrRaplLimit.Bits.LIMIT1_POWER          = ThermalEnables->RaplLim1Pwr;
+  DdrRaplLimit.Bits.LOCKED                = ThermalEnables->RaplLim2Lock;
+  DdrRaplLimit.Bits.LIMIT2_TIME_WINDOW_X  = ThermalEnables->RaplLim2WindX;
+  DdrRaplLimit.Bits.LIMIT2_TIME_WINDOW_Y  = ThermalEnables->RaplLim2WindY;
+  DdrRaplLimit.Bits.LIMIT2_ENABLE         = ThermalEnables->RaplLim2Ena;
+  DdrRaplLimit.Bits.LIMIT2_POWER          = ThermalEnables->RaplLim2Pwr;
+  MRC_DEBUG_MSG (
+    Debug,
+    MSG_LEVEL_NOTE,
+    "DDR_RAPL_LIMIT1 %Xh: %Xh \n",
+    PCU_CR_DDR_RAPL_LIMIT_PCU_REG,
+    DdrRaplLimit.Data32[0]
+    );
+  MRC_DEBUG_MSG (
+    Debug,
+    MSG_LEVEL_NOTE,
+    "DDR_RAPL_LIMIT2 %Xh: %Xh \n",
+    PCU_CR_DDR_RAPL_LIMIT_PCU_REG + 4,
+    DdrRaplLimit.Data32[1]
+    );
+  MrcWriteCR (MrcData, PCU_CR_DDR_RAPL_LIMIT_PCU_REG, DdrRaplLimit.Data32[0]);
+  MrcWriteCR (MrcData, PCU_CR_DDR_RAPL_LIMIT_PCU_REG + 4, DdrRaplLimit.Data32[1]);
+
+  //
+  // DDR WARM AND HOT THRESHOLD
+  //
+  DdrWarmThresholdCh0.Data        = 0;
+  DdrWarmThresholdCh0.Bits.DIMM1  = ThermalEnables->WarmThreshold[0][1];
+  DdrWarmThresholdCh0.Bits.DIMM0  = ThermalEnables->WarmThreshold[0][0];
+  MRC_DEBUG_MSG (
+    Debug,
+    MSG_LEVEL_NOTE,
+    "DDR_WARM_THRESHOLD_CH0 %Xh: %Xh \n",
+    PCU_CR_DDR_WARM_THRESHOLD_CH0_PCU_REG,
+    DdrWarmThresholdCh0.Data
+    );
+  MrcWriteCR (MrcData, PCU_CR_DDR_WARM_THRESHOLD_CH0_PCU_REG, DdrWarmThresholdCh0.Data);
+
+  DdrWarmThresholdCh1.Data        = 0;
+  DdrWarmThresholdCh1.Bits.DIMM1  = ThermalEnables->WarmThreshold[1][1];
+  DdrWarmThresholdCh1.Bits.DIMM0  = ThermalEnables->WarmThreshold[1][0];
+  MRC_DEBUG_MSG (
+    Debug,
+    MSG_LEVEL_NOTE,
+    "DDR_WARM_THRESHOLD_CH1 %Xh: %Xh \n",
+    PCU_CR_DDR_WARM_THRESHOLD_CH1_PCU_REG,
+    DdrWarmThresholdCh1.Data
+    );
+  MrcWriteCR (MrcData, PCU_CR_DDR_WARM_THRESHOLD_CH1_PCU_REG, DdrWarmThresholdCh1.Data);
+
+  DdrHotThresholdCh0.Data       = 0;
+  DdrHotThresholdCh0.Bits.DIMM1 = ThermalEnables->HotThreshold[0][1];
+  DdrHotThresholdCh0.Bits.DIMM0 = ThermalEnables->HotThreshold[0][0];
+  MRC_DEBUG_MSG (
+    Debug,
+    MSG_LEVEL_NOTE,
+    "DDR_HOT_THRESHOLD_CH0 %Xh: %Xh \n",
+    PCU_CR_DDR_HOT_THRESHOLD_CH0_PCU_REG,
+    DdrHotThresholdCh0.Data
+    );
+  MrcWriteCR (MrcData, PCU_CR_DDR_HOT_THRESHOLD_CH0_PCU_REG, DdrHotThresholdCh0.Data);
+
+  DdrHotThresholdCh1.Data       = 0;
+  DdrHotThresholdCh1.Bits.DIMM1 = ThermalEnables->HotThreshold[1][1];
+  DdrHotThresholdCh1.Bits.DIMM0 = ThermalEnables->HotThreshold[1][0];
+  MRC_DEBUG_MSG (
+    Debug,
+    MSG_LEVEL_NOTE,
+    "DDR_HOT_THRESHOLD_CH1 %Xh: %Xh \n",
+    PCU_CR_DDR_HOT_THRESHOLD_CH1_PCU_REG,
+    DdrHotThresholdCh1.Data
+    );
+  MrcWriteCR (MrcData, PCU_CR_DDR_HOT_THRESHOLD_CH1_PCU_REG, DdrHotThresholdCh1.Data);
+
+  //
+  // DDR WARM AND HOT BUDGET
+  //
+  DdrWarmBudgetCh0.Data       = 0;
+  DdrWarmBudgetCh0.Bits.DIMM1 = ThermalEnables->WarmBudget[0][1];
+  DdrWarmBudgetCh0.Bits.DIMM0 = ThermalEnables->WarmBudget[0][0];
+  MRC_DEBUG_MSG (
+    Debug,
+    MSG_LEVEL_NOTE,
+    "DDR_WARM_BUDGET_CH0 %Xh: %Xh \n",
+    PCU_CR_DDR_WARM_BUDGET_CH0_PCU_REG,
+    DdrWarmBudgetCh0.Data
+    );
+  MrcWriteCR (MrcData, PCU_CR_DDR_WARM_BUDGET_CH0_PCU_REG, DdrWarmBudgetCh0.Data);
+
+  DdrWarmBudgetCh1.Data       = 0;
+  DdrWarmBudgetCh1.Bits.DIMM1 = ThermalEnables->WarmBudget[1][1];
+  DdrWarmBudgetCh1.Bits.DIMM0 = ThermalEnables->WarmBudget[1][0];
+  MRC_DEBUG_MSG (
+    Debug,
+    MSG_LEVEL_NOTE,
+    "DDR_WARM_BUDGET_CH1 %Xh: %Xh \n",
+    PCU_CR_DDR_WARM_BUDGET_CH1_PCU_REG,
+    DdrWarmBudgetCh1.Data
+    );
+  MrcWriteCR (MrcData, PCU_CR_DDR_WARM_BUDGET_CH1_PCU_REG, DdrWarmBudgetCh1.Data);
+
+  DdrHotBudgetCh0.Data        = 0;
+  DdrHotBudgetCh0.Bits.DIMM1  = ThermalEnables->HotBudget[0][1];
+  DdrHotBudgetCh0.Bits.DIMM0  = ThermalEnables->HotBudget[0][0];
+  MRC_DEBUG_MSG (
+    Debug,
+    MSG_LEVEL_NOTE,
+    "DDR_HOT_BUDGET_CH0 %Xh: %Xh \n",
+    PCU_CR_DDR_HOT_BUDGET_CH0_PCU_REG,
+    DdrHotBudgetCh0.Data
+    );
+  MrcWriteCR (MrcData, PCU_CR_DDR_HOT_BUDGET_CH0_PCU_REG, DdrHotBudgetCh0.Data);
+
+  DdrHotBudgetCh1.Data        = 0;
+  DdrHotBudgetCh1.Bits.DIMM1  = ThermalEnables->HotBudget[1][1];
+  DdrHotBudgetCh1.Bits.DIMM0  = ThermalEnables->HotBudget[1][0];
+  MRC_DEBUG_MSG (
+    Debug,
+    MSG_LEVEL_NOTE,
+    "DDR_HOT_BUDGET_CH1 %Xh: %Xh \n",
+    PCU_CR_DDR_HOT_BUDGET_CH1_PCU_REG,
+    DdrHotBudgetCh1.Data
+    );
+  MrcWriteCR (MrcData, PCU_CR_DDR_HOT_BUDGET_CH1_PCU_REG, DdrHotBudgetCh1.Data);
+
+  for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+    if (MrcChannelExist (Outputs, Channel)) {
+      if (Inputs->ThermalEnables.UserPowerWeightsEn) {
+        PmDimmIdleEnergy.Data                   = 0;
+        PmDimmIdleEnergy.Bits.DIMM1_IDLE_ENERGY = ThermalEnables->IdleEnergy[Channel][1];
+        PmDimmIdleEnergy.Bits.DIMM0_IDLE_ENERGY = ThermalEnables->IdleEnergy[Channel][0];
+        Offset = MCHBAR_CH0_CR_PM_DIMM_IDLE_ENERGY_REG +
+          (MCHBAR_CH1_CR_PM_DIMM_IDLE_ENERGY_REG - MCHBAR_CH0_CR_PM_DIMM_IDLE_ENERGY_REG) * Channel;
+        MRC_DEBUG_MSG (
+          Debug,
+          MSG_LEVEL_NOTE,
+          "C%u PM_DIMM_IDLE_ENERGY %Xh: %Xh \n",
+          Channel,
+          Offset,
+          PmDimmIdleEnergy.Data
+          );
+        MrcWriteCR (MrcData, Offset, PmDimmIdleEnergy.Data);
+
+        PmDimmPdEnergy.Data                 = 0;
+        PmDimmPdEnergy.Bits.DIMM1_PD_ENERGY = ThermalEnables->PdEnergy[Channel][1];
+        PmDimmPdEnergy.Bits.DIMM0_PD_ENERGY = ThermalEnables->PdEnergy[Channel][0];
+        Offset = MCHBAR_CH0_CR_PM_DIMM_PD_ENERGY_REG +
+          (MCHBAR_CH1_CR_PM_DIMM_PD_ENERGY_REG - MCHBAR_CH0_CR_PM_DIMM_PD_ENERGY_REG) * Channel;
+        MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "C%u PM_DIMM_PD_ENERGY %Xh: %Xh \n", Channel, Offset, PmDimmPdEnergy.Data);
+        MrcWriteCR (MrcData, Offset, PmDimmPdEnergy.Data);
+
+        PmDimmActEnergy.Data                  = 0;
+        PmDimmActEnergy.Bits.DIMM1_ACT_ENERGY = ThermalEnables->ActEnergy[Channel][1];
+        PmDimmActEnergy.Bits.DIMM0_ACT_ENERGY = ThermalEnables->ActEnergy[Channel][0];
+        Offset = MCHBAR_CH0_CR_PM_DIMM_ACT_ENERGY_REG +
+          (MCHBAR_CH1_CR_PM_DIMM_ACT_ENERGY_REG - MCHBAR_CH0_CR_PM_DIMM_ACT_ENERGY_REG) * Channel;
+        MRC_DEBUG_MSG (
+          Debug,
+          MSG_LEVEL_NOTE,
+          "C%u PM_DIMM_ACT_ENERGY %Xh: %Xh \n",
+          Channel,
+          Offset,
+          PmDimmActEnergy.Data
+          );
+        MrcWriteCR (MrcData, Offset, PmDimmActEnergy.Data);
+
+        PmDimmRdEnergy.Data                 = 0;
+        PmDimmRdEnergy.Bits.DIMM1_RD_ENERGY = ThermalEnables->RdEnergy[Channel][1];
+        PmDimmRdEnergy.Bits.DIMM0_RD_ENERGY = ThermalEnables->RdEnergy[Channel][0];
+        Offset = MCHBAR_CH0_CR_PM_DIMM_RD_ENERGY_REG +
+          (MCHBAR_CH1_CR_PM_DIMM_RD_ENERGY_REG - MCHBAR_CH0_CR_PM_DIMM_RD_ENERGY_REG) * Channel;
+        MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "C%u PM_DIMM_RD_ENERGY %Xh: %Xh \n", Channel, Offset, PmDimmRdEnergy.Data);
+        MrcWriteCR (MrcData, Offset, PmDimmRdEnergy.Data);
+
+        PmDimmWrEnergy.Data                 = 0;
+        PmDimmWrEnergy.Bits.DIMM1_WR_ENERGY = ThermalEnables->WrEnergy[Channel][1];
+        PmDimmWrEnergy.Bits.DIMM0_WR_ENERGY = ThermalEnables->WrEnergy[Channel][0];
+        Offset = MCHBAR_CH0_CR_PM_DIMM_WR_ENERGY_REG +
+          (MCHBAR_CH1_CR_PM_DIMM_WR_ENERGY_REG - MCHBAR_CH0_CR_PM_DIMM_WR_ENERGY_REG) * Channel;
+        MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "C%u PM_DIMM_WR_ENERGY %Xh: %Xh \n", Channel, Offset, PmDimmWrEnergy.Data);
+        MrcWriteCR (MrcData, Offset, PmDimmWrEnergy.Data);
+      }
+
+      PmThrtCkeMin.Data                   = 0;
+#ifdef ULT_FLAG
+      if (DdrType == MRC_DDR_TYPE_LPDDR3) {
+        PmThrtCkeMin.Bits.CKE_MIN_DEFEATURE = ThermalEnables->ThrtCkeMinDefeatLpddr;
+        PmThrtCkeMin.Bits.CKE_MIN           = ThermalEnables->ThrtCkeMinTmrLpddr;
+      } else
+#endif // ULT_FLAG
+      {
+        PmThrtCkeMin.Bits.CKE_MIN_DEFEATURE = ThermalEnables->ThrtCkeMinDefeat;
+        PmThrtCkeMin.Bits.CKE_MIN           = ThermalEnables->ThrtCkeMinTmr;
+      }
+      Offset = MCHBAR_CH0_CR_PM_THRT_CKE_MIN_REG +
+        (MCHBAR_CH1_CR_PM_THRT_CKE_MIN_REG - MCHBAR_CH0_CR_PM_THRT_CKE_MIN_REG) * Channel;
+      MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "C%u PM_THRT_CKE_MIN %Xh: %Xh \n", Channel, Offset, PmThrtCkeMin.Data);
+      MrcWriteCR (MrcData, Offset, PmThrtCkeMin.Data);
+    }
+  }
+
+  PmSrefConfig.Data             = 0;
+  PmSrefConfig.Bits.SR_Enable   = ThermalEnables->SrefCfgEna;
+  PmSrefConfig.Bits.Idle_timer  = ThermalEnables->SrefCfgIdleTmr;
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "PM_SREF_CONFIG %Xh: %Xh\n", MCDECS_CR_PM_SREF_CONFIG_MCMAIN_REG, PmSrefConfig.Data);
+  MrcWriteCR (MrcData, MCDECS_CR_PM_SREF_CONFIG_MCMAIN_REG, PmSrefConfig.Data);
+
+  //
+  // POWER THERMAL MANAGEMENT CONTROL
+  //
+  DdrPtmCtl.Data                    = MrcReadCR (MrcData, PCU_CR_DDR_PTM_CTL_PCU_REG);
+  DdrPtmCtl.Bits.OLTM_ENABLE        = ThermalEnables->EnableOltm;
+  DdrPtmCtl.Bits.CLTM_ENABLE        = ThermalEnables->EnableCltm;
+  DdrPtmCtl.Bits.EXTTS_ENABLE       = ThermalEnables->EnableExtts;
+  DdrPtmCtl.Bits.REFRESH_2X_MODE    = ThermalEnables->Refresh2X;
+#ifdef ULT_FLAG
+  if (DdrType == MRC_DDR_TYPE_LPDDR3) {
+    DdrPtmCtl.Bits.PDWN_CONFIG_CTL = ThermalEnables->EnablePwrDnLpddr;
+    //
+    // When enabling 2x Refresh for LPDDR through the Mailbox we must
+    // ensure DDR_PTM_CTL.DISABLE_DRAM_TS = 0.  Thus we ignore LpddrThermalSensor.
+    //
+    if (Inputs->RefreshRate2x == FALSE) {
+      DdrPtmCtl.Bits.DISABLE_DRAM_TS = (ThermalEnables->LpddrThermalSensor == 0) ? 1 : 0;
+    } else {
+       MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Ignoring ThermalEnables->LpddrThermal Sensor as 2x Refresh is enabled\n");
+    }
+  } else
+#endif // ULT_FLAG
+  {
+    DdrPtmCtl.Bits.PDWN_CONFIG_CTL = ThermalEnables->EnablePwrDn;
+  }
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "DDR_PTM_CTL %Xh: %Xh\n", PCU_CR_DDR_PTM_CTL_PCU_REG, DdrPtmCtl.Data);
+  MrcWriteCR (MrcData, PCU_CR_DDR_PTM_CTL_PCU_REG, DdrPtmCtl.Data);
+
+  return;
+}
+
+
+/**
+  this function use by the OEM to do dedicated task during the MRC.
+
+  @param[in] MrcData           - include all the MRC data
+  @param[in] OemStatusCommand  - A command that indicates the task to perform.
+  @param[in] ptr               - general ptr for general use.
+
+  @retval The status of the task.
+**/
+MrcStatus
+MrcOemCheckPoint (
+  IN MrcParameters        *MrcData,
+  IN MRC_OemStatusCommand OemStatusCommand,
+  IN void                 *ptr
+  )
+{
+  MrcInput  *Inputs;
+  MrcOutput *Outputs;
+  MrcStatus Status;
+  MrcDdrType DdrType;
+
+  Status  = mrcSuccess;
+  Inputs  = &MrcData->SysIn.Inputs;
+  Outputs = &MrcData->SysOut.Outputs;
+  DdrType = Outputs->DdrType;
+
+
+  switch (OemStatusCommand) {
+  case OemSpdProcessingRun:
+    break;
+
+  case OemPreTraining:
+    break;
+
+  case OemMcTrainingRun:
+    break;
+
+  case OemEarlyCommandTraining:
+    if (DdrType == MRC_DDR_TYPE_LPDDR3) {
+      Status = mrcSuccess;  // This is required for LPDDR
+    } else if (!Inputs->TrainingEnables.ECT) {
+      Status = mrcFail; // Skip this training step
+    }
+    break;
+
+#ifdef ULT_FLAG
+  case OemJedecInitLpddr3:    // MrcJedecInitLpddr3
+    if (DdrType == MRC_DDR_TYPE_LPDDR3) {
+      Status = mrcSuccess;
+    } else {
+      Status = mrcFail;  // Skip this step for non-LPDDR
+    }
+    break;
+#endif // ULT_FLAG
+
+  case OemSenseAmpTraining:
+    if (!Inputs->TrainingEnables.SOT) {
+        Status = mrcFail; // Skip this training step
+    }
+    break;
+
+  case OemReadMprTraining:
+    if (!Inputs->TrainingEnables.RDMPRT) {
+        Status = mrcFail; // Skip this training step
+    }
+    break;
+
+  case OemReceiveEnable:
+    if (!Inputs->TrainingEnables.RCVET) {
+        Status = mrcFail; // Skip this training step
+    }
+    break;
+
+  case OemJedecWriteLeveling:
+    if (!Inputs->TrainingEnables.JWRL) {
+        Status = mrcFail; // Skip this training step
+    }
+    break;
+
+  case OemWriteLeveling:
+    if (!Inputs->TrainingEnables.FWRL) {
+        Status = mrcFail; // Skip this training step
+    }
+    break;
+
+  case OemWriteDqDqs:
+    if (!Inputs->TrainingEnables.WRTC1D) {
+        Status = mrcFail; // Skip this training step
+    }
+    break;
+
+  case OemReadDqDqs:
+    if (!Inputs->TrainingEnables.RDTC1D) {
+        Status = mrcFail; // Skip this training step
+    }
+    break;
+
+  case OemDimmODTTraining:
+    if (!Inputs->TrainingEnables.DIMMODTT) {
+      Status = mrcFail; // Skip this training step
+    }
+    break;
+
+  case OemDimmRonTraining:
+    if (!Inputs->TrainingEnables.DIMMRONT) {
+      Status = mrcFail; // Skip this training step
+    }
+    break;
+
+  case OemWriteSlewRate:
+    if (!Inputs->TrainingEnables.WRSRT) {
+      Status = mrcFail; // Skip this training step
+    }
+    break;
+
+  case OemDimmODT1dTraining:
+    if (!Inputs->TrainingEnables.DIMMODTT1D) {
+      Status = mrcFail; // Skip this training step
+    }
+    break;
+
+  case OemWriteDriveStrength:
+    if (!Inputs->TrainingEnables.WRDST) {
+        Status = mrcFail; // Skip this training step
+    }
+    break;
+
+  case OemWriteEQTraining:
+    if (!Inputs->TrainingEnables.WREQT) {
+        Status = mrcFail; // Skip this training step
+    }
+    break;
+
+  case OemReadODTTraining:
+    if (!Inputs->TrainingEnables.RDODTT) {
+        Status = mrcFail; // Skip this training step
+    }
+    break;
+
+  case OemReadEQTraining:
+    if (!Inputs->TrainingEnables.RDEQT) {
+        Status = mrcFail; // Skip this training step
+    }
+    break;
+
+  case OemPostTraining:
+    if (DdrType == MRC_DDR_TYPE_LPDDR3) {
+      Status = mrcFail; // Skip this training step
+      break;
+    }
+    break;
+
+  case OemReadAmplifierPower:
+    if (!Inputs->TrainingEnables.RDAPT) {
+        Status = mrcFail; // Skip this training step
+    }
+    break;
+
+  case OemOptimizeComp:
+    break;
+
+  case OemWriteDqDqs2D:
+    if (!Inputs->TrainingEnables.WRTC2D) {
+        Status = mrcFail; // Skip this training step
+    }
+    break;
+
+  case OemReadDqDqs2D:
+    if (!Inputs->TrainingEnables.RDTC2D) {
+        Status = mrcFail; // Skip this training step
+    }
+    break;
+
+  case OemCmdVoltCentering:
+    if (!Inputs->TrainingEnables.CMDVC) {
+        Status = mrcFail; // Skip this training step
+    }
+    break;
+
+  case OemWriteVoltCentering2D:
+    if (!Inputs->TrainingEnables.WRVC2D) {
+        Status = mrcFail; // Skip this training step
+    }
+    break;
+
+  case OemReadVoltCentering2D:
+    if (!Inputs->TrainingEnables.RDVC2D) {
+        Status = mrcFail; // Skip this training step
+    }
+    break;
+
+  case OemLateCommandTraining:
+    if (!Inputs->TrainingEnables.LCT) {
+      Status = mrcFail; // Skip this training step
+    }
+    break;
+
+  case OemRoundTripLatency:
+    if (!Inputs->TrainingEnables.RTL) {
+        Status = mrcFail; // Skip this training step
+    }
+    break;
+
+  case OemTurnAroundTimes:
+    //
+    // @todo: TAT has to be updated for LPDDR3, skip it for now.
+    //
+    if ((!Inputs->TrainingEnables.TAT) || (DdrType == MRC_DDR_TYPE_LPDDR3)) {
+      Status = mrcFail; // Skip this training step
+    }
+    break;
+
+#ifdef ULT_FLAG
+    case OemRcvEnCentering1D:
+      if ((!Inputs->TrainingEnables.RCVENC1D) || (DdrType != MRC_DDR_TYPE_LPDDR3)) {
+        Status = mrcFail;  // Skip this step for non-LPDDR
+      }
+      break;
+#endif // ULT_FLAG
+
+  case OemRetrainMarginCheck:
+    if (!Inputs->TrainingEnables.RMC) {
+        Status = mrcFail; // Skip this training step
+    }
+    break;
+
+
+  case OemRmt:
+    if (!Inputs->TrainingEnables.RMT) {
+        Status = mrcFail; // Skip this training step
+    }
+    break;
+
+  case OemMemTest:
+    if (!Inputs->TrainingEnables.MEMTST) {
+        Status = mrcFail; // Skip this training step
+    }
+    break;
+
+  case OemAliasCheck:
+    if (!Inputs->TrainingEnables.ALIASCHK) {
+      Status = mrcFail; // Skip this training step
+    }
+    break;
+
+  case OemBeforeNormalMode:
+    MrcOemBeforeNormalModeTestMenu (MrcData);
+    break;
+
+  case OemAfterNormalMode:
+    MrcOemAfterNormalModeTestMenu (MrcData);
+    break;
+
+  case OemFrequencySetDone:
+#ifdef SSA_FLAG
+#ifndef MRC_MINIBIOS_BUILD
+    SsaBiosInitialize (MrcData);
+#endif
+#endif // SSA_FLAG
+    break;
+
+  default:
+    break;
+  }
+
+  return Status;
+}
+
+/**
+  This function display on port 80 number.
+  It can be different debug interface.
+  This function can be use for any debug ability according to OEM requirements.
+
+  @param[in] MrcData            - Mrc Global Data
+  @param[in] DisplayDebugNumber - the number to display on port 80.
+
+  @retval Nothing
+**/
+void
+MrcOemDebugHook (
+  IN MrcParameters *MrcData,
+  IN U16           DisplayDebugNumber
+  )
+{
+  MrcInput  *Inputs;
+  U8        temp;
+  U16       BreakCmos;
+
+  Inputs                    = &MrcData->SysIn.Inputs;
+  Inputs->Debug.PostCode[1] = DisplayDebugNumber;
+  MrcOemOutPort16 (0x80, DisplayDebugNumber);
+  MRC_DEBUG_MSG (&Inputs->Debug, MSG_LEVEL_NOTE, "Post Code: 0x%X\n", DisplayDebugNumber);
+
+  //
+  // Check if we should break on this post code.
+  //
+  do {
+    temp = RtcRead (MRC_POST_CODE_LOW_BYTE_ADDR);
+    BreakCmos = (RtcRead (MRC_POST_CODE_HIGH_BYTE_ADDR) << 8) | temp;
+  } while (DisplayDebugNumber == BreakCmos);
+
+#ifdef SSA_FLAG
+#ifndef MRC_MINIBIOS_BUILD
+  if ((void *) (Inputs->SsaCallbackPpi) != NULL) {
+    (((SSA_BIOS_CALLBACKS_PPI *) (Inputs->SsaCallbackPpi))->MrcCheckpoint) ((EFI_PEI_SERVICES **) (Inputs->Debug.Stream), ((SSA_BIOS_CALLBACKS_PPI *)Inputs->SsaCallbackPpi), DisplayDebugNumber, NULL);
+  }
+#endif
+#endif // SSA_FLAG
+
+  return;
+}
+
+#ifdef MRC_DEBUG_PRINT
+/**
+  Print the input parameters to the debug message output port.
+
+  @param[in] MrcData - The MRC global data.
+
+  @retval mrcSuccess
+**/
+MrcStatus
+MrcPrintInputParameters (
+  IN MrcParameters *const MrcData
+  )
+{
+  const MrcDebug                        *Debug;
+  const MrcInput                        *Inputs;
+  const MrcControllerIn                 *ControllerIn;
+  const MrcChannelIn                    *ChannelIn;
+  const MrcDimmIn                       *DimmIn;
+  const TrainingStepsEn                 *TrainingSteps;
+  U8                                    Controller;
+  U8                                    Channel;
+  U8                                    Dimm;
+
+  Inputs = &MrcData->SysIn.Inputs;
+  Debug  = &Inputs->Debug;
+
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "*************************************\n");
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "*****MRC INPUT PARAMS DUMP START*****\n");
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "*************************************\n");
+  //
+  // The following are system level definitions. All memory controllers in the system are set to these values.
+  //
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Debug.Stream : %Xh\n", Inputs->Debug.Stream);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Debug.Level : %Xh\n", Inputs->Debug.Level);
+
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "FreqMax : %u\n", Inputs->FreqMax);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Ratio : %u\n", Inputs->Ratio);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "RefClk : %uMHz\n", (Inputs->RefClk == MRC_REF_CLOCK_100) ? 100 : 133);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "BClk : %uHz\n", Inputs->BClkFrequency);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "BoardType : %Xh\n", Inputs->BoardType);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "CpuStepping : %Xh\n", Inputs->CpuStepping);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "CpuModel : %Xh\n", Inputs->CpuModel);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "GraphicsStolenSize : %Xh\n", Inputs->GraphicsStolenSize);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "GraphicsGttSize : %Xh\n", Inputs->GraphicsGttSize);
+
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%s.Seconds : %u\n", BaseTimeString, Inputs->BaseTime.Seconds);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%s.Minutes : %u\n", BaseTimeString, Inputs->BaseTime.Minutes);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%s.Hours : %u\n", BaseTimeString, Inputs->BaseTime.Hours);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%s.DayOfMonth : %u\n", BaseTimeString, Inputs->BaseTime.DayOfMonth);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%s.Month : %u\n", BaseTimeString, Inputs->BaseTime.Month);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%s.Year : %u\n", BaseTimeString, Inputs->BaseTime.Year);
+
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Iteration : %Xh\n", Inputs->Iteration);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "MrcMode : %Xh\n", Inputs->MrcMode);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "VddVoltage : %u mV\n", Inputs->VddVoltage);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "MemoryProfile : %Xh\n", Inputs->MemoryProfile);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "BootMode : %Xh\n", Inputs->BootMode);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "TxtFlag : %Xh\n", Inputs->TxtFlag);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "MobilePlatform : %Xh\n", Inputs->MobilePlatform);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "EccSupport : %Xh\n", Inputs->EccSupport);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "SetRxDqs32 : %Xh\n", Inputs->SetRxDqs32);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "GfxIsVersatileAcceleration : %Xh\n", Inputs->GfxIsVersatileAcceleration);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "ScramblerEnable : %Xh\n", Inputs->ScramblerEnable);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "McLock : %Xh\n", Inputs->McLock);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "RemapEnable : %Xh\n", Inputs->RemapEnable);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "PowerDownMode : %Xh\n", Inputs->PowerDownMode);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "PwdwnIdleCounter : %Xh\n", Inputs->PwdwnIdleCounter);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "RankInterleave : %Xh\n", Inputs->RankInterleave);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "EnhancedInterleave : %Xh\n", Inputs->EnhancedInterleave);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "WeaklockEn : %Xh\n", Inputs->WeaklockEn);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "EnCmdRate : %Xh\n", Inputs->EnCmdRate);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "CmdTriStateDis : %Xh\n", Inputs->CmdTriStateDis);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "RefreshRate2x : %Xh\n", Inputs->RefreshRate2x);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "BaseAddresses\n");
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "  PciE : %Xh\n", Inputs->PciEBaseAddress);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "  MchBar : %Xh\n", Inputs->MchBarBaseAddress);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "  Smbus : %Xh\n", Inputs->SmbusBaseAddress);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "  Gdxc : %Xh\n", Inputs->GdxcBaseAddress);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "  Hpet : %Xh\n\n", Inputs->HpetBaseAddress);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "MeStolenSize : %Xh\n", Inputs->MeStolenSize);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "MmioSize : %Xh\n", Inputs->MmioSize);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "TsegSize : %Xh\n", Inputs->TsegSize);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "IedSize : %Xh\n", Inputs->IedSize);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "DprSize : %Xh\n", Inputs->DprSize);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "VddSettleWaitTime : %Xh\n", Inputs->VddSettleWaitTime);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "VccIomV : %Xh\n", Inputs->VccIomV);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "AutoSelfRefreshSupport : %u\n", Inputs->AutoSelfRefreshSupport);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "ExtTemperatureSupport : %u\n", Inputs->ExtTemperatureSupport);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "ChHashEnable : %Xh\n", Inputs->ChHashEnable);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "ChHashMask : %Xh\n", Inputs->ChHashMask);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "ChHashInterleaveBit : %Xh\n", Inputs->ChHashInterleaveBit);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%sEnable : %Xh\n", GdxcString, Inputs->Gdxc.GdxcEnable);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%sIotSize : %Xh\n", GdxcString, Inputs->Gdxc.GdxcIotSize);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%sMotSize : %Xh\n", GdxcString, Inputs->Gdxc.GdxcMotSize);
+  
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "MemoryTrace: %u\n", Inputs->MemoryTrace);
+
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "*************************************\n");
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "*****    MRC TRAINING STEPS     *****\n");
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "*************************************\n");
+  TrainingSteps = &Inputs->TrainingEnables;
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%s : %Xh\n", TrainEnString, Inputs->TrainingEnables);
+
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%s.ECT : %u\n", TrainEnString, TrainingSteps->ECT);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%s.SOT : %u\n", TrainEnString, TrainingSteps->SOT);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%s.RDMPRT : %u\n", TrainEnString, TrainingSteps->RDMPRT);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%s.RCVET : %u\n", TrainEnString, TrainingSteps->RCVET);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%s.JWRL : %u\n", TrainEnString, TrainingSteps->JWRL);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%s.FWRL : %u\n", TrainEnString, TrainingSteps->FWRL);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%s.WRTC1D : %u\n", TrainEnString, TrainingSteps->WRTC1D);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%s.RDTC1D : %u\n", TrainEnString, TrainingSteps->RDTC1D);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%s.DIMMODTT : %u\n", TrainEnString, TrainingSteps->DIMMODTT);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%s.WRDST : %u\n", TrainEnString, TrainingSteps->WRDST);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%s.WREQT : %u\n", TrainEnString, TrainingSteps->WREQT);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%s.RDODTT : %u\n", TrainEnString, TrainingSteps->RDODTT);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%s.RDEQT : %u\n", TrainEnString, TrainingSteps->RDEQT);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%s.RDAPT : %u\n", TrainEnString, TrainingSteps->RDAPT);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%s.WRTC2D : %u\n", TrainEnString, TrainingSteps->WRTC2D);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%s.RDTC2D : %u\n", TrainEnString, TrainingSteps->RDTC2D);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%s.WRVC2D : %u\n", TrainEnString, TrainingSteps->WRVC2D);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%s.RDVC2D : %u\n", TrainEnString, TrainingSteps->RDVC2D);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%s.LCT : %u\n", TrainEnString, TrainingSteps->LCT);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%s.RTL : %u\n", TrainEnString, TrainingSteps->RTL);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%s.TAT : %u\n", TrainEnString, TrainingSteps->TAT);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%s.RMT : %u\n", TrainEnString, TrainingSteps->RMT);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%s.MEMTST : %u\n", TrainEnString, TrainingSteps->MEMTST);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%s.DIMMODTT1D : %u\n", TrainEnString, TrainingSteps->DIMMODTT1D);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%s.WRSRT : %u\n", TrainEnString, TrainingSteps->WRSRT);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%s.DIMMRONT : %u\n", TrainEnString, TrainingSteps->DIMMRONT);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%s.ALIASCHK : %u\n", TrainEnString, TrainingSteps->ALIASCHK);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%s.RCVENC1D : %u\n", TrainEnString, TrainingSteps->RCVENC1D);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%s.RMC : %u\n", TrainEnString, TrainingSteps->RMC);
+
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "*************************************\n");
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "*****      MRC TIMING DATA      *****\n");
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "*************************************\n");
+
+  for (Controller = 0; Controller < MAX_CONTROLLERS; Controller++) {
+    ControllerIn = &Inputs->Controller[Controller];
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Controller[%u] ChannelCount : %Xh\n", Controller, ControllerIn->ChannelCount);
+    for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+      ChannelIn = &ControllerIn->Channel[Channel];
+      MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Channel[%u].Status : %Xh\n", Channel, ChannelIn->Status);
+      MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Channel[%u].DimmCount : %Xh\n", Channel, ChannelIn->DimmCount);
+
+      for (Dimm = 0; Dimm < MAX_DIMMS_IN_CHANNEL; Dimm++) {
+        DimmIn = &ChannelIn->Dimm[Dimm];
+        MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%s %u/%u/%u Status : %Xh\n", CcdString, Controller, Channel, Dimm, DimmIn->Status);
+        if (Inputs->MemoryProfile == USER_PROFILE) {
+          MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%s %u/%u/%u tCK    : %u\n", CcdString, Controller, Channel, Dimm, DimmIn->Timing.tCK);
+          MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%s %u/%u/%u NMode  : %u\n", CcdString, Controller, Channel, Dimm, DimmIn->Timing.NMode);
+          MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%s %u/%u/%u tCL    : %u\n", CcdString, Controller, Channel, Dimm, DimmIn->Timing.tCL);
+          MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%s %u/%u/%u tCWL   : %u\n", CcdString, Controller, Channel, Dimm, DimmIn->Timing.tCWL);
+          MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%s %u/%u/%u tFAW   : %u\n", CcdString, Controller, Channel, Dimm, DimmIn->Timing.tFAW);
+          MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%s %u/%u/%u tRAS   : %u\n", CcdString, Controller, Channel, Dimm, DimmIn->Timing.tRAS);
+          MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%s %u/%u/%u tRC    : %u\n", CcdString, Controller, Channel, Dimm, DimmIn->Timing.tRC);
+          MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%s %u/%u/%u tRCD   : %u\n", CcdString, Controller, Channel, Dimm, DimmIn->Timing.tRCD);
+          MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%s %u/%u/%u tREFI  : %u\n", CcdString, Controller, Channel, Dimm, DimmIn->Timing.tREFI);
+          MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%s %u/%u/%u tRFC   : %u\n", CcdString, Controller, Channel, Dimm, DimmIn->Timing.tRFC);
+          MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%s %u/%u/%u tRP    : %u\n", CcdString, Controller, Channel, Dimm, DimmIn->Timing.tRP);
+#ifdef ULT_FLAG
+          MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%s %u/%u/%u tRPab  : %u\n", CcdString, Controller, Channel, Dimm, DimmIn->Timing.tRPab);
+#endif // ULT_FLAG
+          MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%s %u/%u/%u tRRD   : %u\n", CcdString, Controller, Channel, Dimm, DimmIn->Timing.tRRD);
+          MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%s %u/%u/%u tRTP   : %u\n", CcdString, Controller, Channel, Dimm, DimmIn->Timing.tRTP);
+          MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%s %u/%u/%u tWR    : %u\n", CcdString, Controller, Channel, Dimm, DimmIn->Timing.tWR);
+          MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%s %u/%u/%u tWTR   : %u\n", CcdString, Controller, Channel, Dimm, DimmIn->Timing.tWTR);
+        }
+        MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%s %u/%u/%u SpdAddress : %Xh\n", CcdString, Controller, Channel, Dimm, DimmIn->SpdAddress);
+      }
+    }
+  }
+
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "*************************************\n");
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "*****    THERMAL OVERWRITE    *******\n");
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "*************************************\n");
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%s.EnableExtts     : %Xh\n",   ThermEnString, Inputs->ThermalEnables.EnableExtts);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%s.EnableCltm      : %Xh\n",   ThermEnString, Inputs->ThermalEnables.EnableCltm);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%s.EnableOltm      : %Xh\n",   ThermEnString, Inputs->ThermalEnables.EnableOltm);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%s.EnablePwrDn     : %Xh\n",   ThermEnString, Inputs->ThermalEnables.EnablePwrDn);
+#ifdef ULT_FLAG
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%s.EnablePwrDnLpddr: %Xh\n",   ThermEnString, Inputs->ThermalEnables.EnablePwrDnLpddr);
+#endif // ULT_FLAG
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%s.Refresh2X       : %Xh\n",   ThermEnString, Inputs->ThermalEnables.Refresh2X);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%s.LpddrThermalSensor: %Xh\n", ThermEnString, Inputs->ThermalEnables.LpddrThermalSensor);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%s.LockPTMregs     : %Xh\n",   ThermEnString, Inputs->ThermalEnables.LockPTMregs);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%s.UserPowerWeightsEn: %Xh\n", ThermEnString, Inputs->ThermalEnables.UserPowerWeightsEn);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%s.EnergyScaleFact : %Xh\n",   ThermEnString, Inputs->ThermalEnables.EnergyScaleFact);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%s.RaplLim2Lock    : %Xh\n",   ThermEnString, Inputs->ThermalEnables.RaplLim2Lock);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%s.RaplLim2WindX   : %Xh\n",   ThermEnString, Inputs->ThermalEnables.RaplLim2WindX);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%s.RaplLim2WindY   : %Xh\n",   ThermEnString, Inputs->ThermalEnables.RaplLim2WindY);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%s.RaplLim2Ena     : %Xh\n",   ThermEnString, Inputs->ThermalEnables.RaplLim2Ena);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%s.RaplLim2Pwr     : %Xh\n",   ThermEnString, Inputs->ThermalEnables.RaplLim2Pwr);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%s.RaplLim1WindX   : %Xh\n",   ThermEnString, Inputs->ThermalEnables.RaplLim1WindX);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%s.RaplLim1WindY   : %Xh\n",   ThermEnString, Inputs->ThermalEnables.RaplLim1WindY);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%s.RaplLim1Ena     : %Xh\n",   ThermEnString, Inputs->ThermalEnables.RaplLim1Ena);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%s.RaplLim1Pwr     : %Xh\n",   ThermEnString, Inputs->ThermalEnables.RaplLim1Pwr);
+  for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%s.RaplPwrFlCh[%u]  : %Xh\n", ThermEnString, Channel, Inputs->ThermalEnables.RaplPwrFl[Channel]);
+    for (Dimm = 0; Dimm < MAX_DIMMS_IN_CHANNEL; Dimm++) {
+      MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%s.WarmThresholdCh[%u]Dimm[%u] : %Xh\n", ThermEnString, Channel, Dimm, Inputs->ThermalEnables.WarmThreshold[Channel][Dimm]);
+      MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%s.HotThresholdCh[%u]Dimm[%u]  : %Xh\n", ThermEnString, Channel, Dimm, Inputs->ThermalEnables.HotThreshold[Channel][Dimm]);
+      MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%s.WarmBudgetCh[%u]Dimm[%u]    : %Xh\n", ThermEnString, Channel, Dimm, Inputs->ThermalEnables.WarmBudget[Channel][Dimm]);
+      MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%s.HotBudgetCh[%u]Dimm[%u]     : %Xh\n", ThermEnString, Channel, Dimm, Inputs->ThermalEnables.HotBudget[Channel][Dimm]);
+      MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%s.IdleEnergyCh[%u]Dimm[%u]    : %Xh\n", ThermEnString, Channel, Dimm, Inputs->ThermalEnables.IdleEnergy[Channel][Dimm]);
+      MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%s.PdEnergyCh[%u]Dimm[%u]      : %Xh\n", ThermEnString, Channel, Dimm, Inputs->ThermalEnables.PdEnergy[Channel][Dimm]);
+      MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%s.ActEnergyCh[%u]Dimm[%u]     : %Xh\n", ThermEnString, Channel, Dimm, Inputs->ThermalEnables.ActEnergy[Channel][Dimm]);
+      MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%s.RdEnergyCh[%u]Dimm[%u]      : %Xh\n", ThermEnString, Channel, Dimm, Inputs->ThermalEnables.RdEnergy[Channel][Dimm]);
+      MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%s.WrEnergyCh[%u]Dimm[%u]      : %Xh\n", ThermEnString, Channel, Dimm, Inputs->ThermalEnables.WrEnergy[Channel][Dimm]);
+    }
+  }
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%s.SrefCfgEna      : %Xh\n", ThermEnString, Inputs->ThermalEnables.SrefCfgEna);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%s.SrefCfgIdleTmr  : %Xh\n", ThermEnString, Inputs->ThermalEnables.SrefCfgIdleTmr);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%s.ThrtCkeMinDefeat: %Xh\n", ThermEnString, Inputs->ThermalEnables.ThrtCkeMinDefeat);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%s.ThrtCkeMinTmr   : %Xh\n", ThermEnString, Inputs->ThermalEnables.ThrtCkeMinTmr);
+#ifdef ULT_FLAG
+  if (Inputs->CpuModel == cmHSW_ULT) {
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%s.ThrtCkeMinDefeatLpddr: %Xh\n", ThermEnString, Inputs->ThermalEnables.ThrtCkeMinDefeatLpddr);
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%s.ThrtCkeMinTmrLpddr   : %Xh\n", ThermEnString, Inputs->ThermalEnables.ThrtCkeMinTmrLpddr);
+  }
+#endif // ULT_FLAG
+
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "*************************************\n");
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "*****MRC INPUT PARAMS DUMP END*******\n");
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "*************************************\n\n");
+
+  return mrcSuccess;
+}
+
+/**
+  Print the specified memory to the serial message debug port.
+
+  @param[in] Debug - Serial message debug structure.
+  @param[in] Start - The starting address to dump.
+  @param[in] Size  - The amount of data in bytes to dump.
+
+  @retval Nothing.
+**/
+void
+MrcPrintMemory (
+  IN const MrcDebug *const Debug,
+  IN const U8 *const       Start,
+  IN const U32              Size
+  )
+{
+  const U8  *Address;
+  const U8  *End;
+  U32       Line;
+  U32       Offset;
+
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "          ");
+  for (Offset = 0; Offset < 16; Offset++) {
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%02X ", ((U32) Start + Offset) % 16);
+  }
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\n");
+  End = Start + Size;
+  for (Line = 0; Line < ((Size / 16) + 1); Line++) {
+    Address = Start + (Line * 16);
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "% 8X: ", Address);
+    for (Offset = 0; Offset < 16; Offset++) {
+      MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, ((Address + Offset) < End) ? "%02X " : "   ", Address[Offset]);
+    }
+    for (Offset = 0; (Offset < 16) && ((Address + Offset) < End); Offset++) {
+      MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%c", isprint (Address[Offset]) ? Address[Offset] : '.');
+    }
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\n");
+  }
+  return;
+}
+#endif
+
+#if (defined MEMORY_DOWN_SUPPORT && (MEMORY_DOWN_SUPPORT > 0))
+
+/******************************************************************************
+  Memory down configuration code starts here.
+  Add SPD, and channel/slot population settings here.
+
+  Even though this is a memory down configuration, the MRC needs to know how
+  the memory appears to the controller, so indicate here which channels are
+  populated. Also, the MRC needs to know which slots are valid, even though
+  there are technically no physical slots in a memory down configuration.
+  The MRC also needs a valid SPD data for the configuration.
+******************************************************************************/
+typedef enum {
+  MEMORY_ABSENT,    ///< No memory down and no physical memory slot.
+  MEMORY_SLOT_ONLY, ///< No memory down and a physical memory slot.
+  MEMORY_DOWN_ONLY, ///< Memory down and not a physical memory slot.
+} MemorySlotStatus;
+
+#ifndef AMI_OVERRIDE_FOR_MEMORY_DOWN
+#if defined(NB_OEM_DIMM1_STATUS) && (NB_OEM_DIMM1_STATUS == 0x02)
+static const UINT8 Dimm1SpdTbl[] = NB_OEM_DIMM1_SPD_DATA;
+#endif
+#if defined(NB_OEM_DIMM2_STATUS) && (NB_OEM_DIMM2_STATUS == 0x02)
+static const UINT8 Dimm2SpdTbl[] = NB_OEM_DIMM2_SPD_DATA;
+#endif
+#if defined(NB_OEM_DIMM3_STATUS) && (NB_OEM_DIMM3_STATUS == 0x02)
+static const UINT8 Dimm3SpdTbl[] = NB_OEM_DIMM3_SPD_DATA;
+#endif
+#if defined(NB_OEM_DIMM4_STATUS) && (NB_OEM_DIMM4_STATUS == 0x02)
+static const UINT8 Dimm4SpdTbl[] = NB_OEM_DIMM4_SPD_DATA;
+#endif
+#endif // AMI_OVERRIDE_FOR_MEMORY_DOWN
+///
+/// Example board support
+///
+#ifdef AMI_OVERRIDE_FOR_MEMORY_DOWN
+#define EXAMPLE_BOARD_SUPPORT 0
+#else
+#if (defined MEMORY_DOWN_SUPPORT && (MEMORY_DOWN_SUPPORT == 1))
+#define EXAMPLE_BOARD_SUPPORT 1
+#else
+#define EXAMPLE_BOARD_SUPPORT 0
+#endif // MEMORY_DOWN_SUPPORT
+#endif // AMI_OVERRIDE_FOR_MEMORY_DOWN
+#if (defined EXAMPLE_BOARD_SUPPORT && (EXAMPLE_BOARD_SUPPORT > 0))
+///
+/// For this example board, we have a dual channel, single slot configuration
+/// with the same memory configuration in each channel (DDR3).
+///
+const MemorySlotStatus ExampleSlotStatus[MAX_CHANNEL][MAX_DIMMS_IN_CHANNEL] = {
+#ifndef AMI_OVERRIDE_FOR_MEMORY_DOWN
+  NB_OEM_DIMM1_STATUS,    // Channel 0, Slot 0
+  NB_OEM_DIMM2_STATUS,    // Channel 0, Slot 1
+  NB_OEM_DIMM3_STATUS,    // Channel 1, Slot 0
+  NB_OEM_DIMM4_STATUS,    // Channel 1, Slot 1
+#else
+  MEMORY_DOWN_ONLY,                     ///< Channel 0, Slot 0
+  MEMORY_ABSENT,                        ///< Channel 0, Slot 1
+  MEMORY_DOWN_ONLY,                     ///< Channel 1, Slot 0
+  MEMORY_ABSENT,                        ///< Channel 1, Slot 1
+#endif // AMI_OVERRIDE_FOR_MEMORY_DOWN
+};
+
+const U8 ExampleSpd[] = {
+  0x92,                                 ///< 0   Number of Serial PD Bytes Written / SPD Device Size / CRC Coverage 1, 2
+  0x10,                                 ///< 1   SPD Revision
+  0x0B,                                 ///< 2   DRAM Device Type
+  0x03,                                 ///< 3   Module Type
+  0x02,                                 ///< 4   SDRAM Density and Banks
+  0x11,                                 ///< 5   SDRAM Addressing
+  0x00,                                 ///< 6   Module Nominal Voltage
+  0x09,                                 ///< 7   Module Organization
+  0x03,                                 ///< 8   Module Memory Bus Width
+  0x52,                                 ///< 9   Fine Timebase (FTB) Dividend / Divisor
+  0x01,                                 ///< 10  Medium Timebase (MTB) Dividend
+  0x08,                                 ///< 11  Medium Timebase (MTB) Divisor
+  0x0A,                                 ///< 12  SDRAM Minimum Cycle Time (tCKmin)
+  0x00,                                 ///< 13  Reserved0
+  0xFE,                                 ///< 14  CAS Latencies Supported, Least Significant Byte
+  0x00,                                 ///< 15  CAS Latencies Supported, Most Significant Byte
+  0x69,                                 ///< 16  Minimum CAS Latency Time (tAAmin)
+  0x78,                                 ///< 17  Minimum Write Recovery Time (tWRmin)
+  0x69,                                 ///< 18  Minimum RAS# to CAS# Delay Time (tRCDmin)
+  0x30,                                 ///< 19  Minimum Row Active to Row Active Delay Time (tRRDmin)
+  0x69,                                 ///< 20  Minimum Row Precharge Delay Time (tRPmin)
+  0x11,                                 ///< 21  Upper Nibbles for tRAS and tRC
+  0x18,                                 ///< 22  Minimum Active to Precharge Delay Time (tRASmin), Least Significant Byte
+  0x81,                                 ///< 23  Minimum Active to Active/Refresh Delay Time (tRCmin), Least Significant Byte
+  0x70,                                 ///< 24  Minimum Refresh Recovery Delay Time (tRFCmin), Least Significant Byte
+  0x03,                                 ///< 25  Minimum Refresh Recovery Delay Time (tRFCmin), Most Significant Byte
+  0x3C,                                 ///< 26  Minimum Internal Write to Read Command Delay Time (tWTRmin)
+  0x3C,                                 ///< 27  Minimum Internal Read to Precharge Command Delay Time (tRTPmin)
+  0x00,                                 ///< 28  Upper Nibble for tFAW
+  0xF0,                                 ///< 29  Minimum Four Activate Window Delay Time (tFAWmin)
+  0x83,                                 ///< 30  SDRAM Optional Features
+  0x01,                                 ///< 31  SDRAMThermalAndRefreshOptions
+  0x00,                                 ///< 32  ModuleThermalSensor
+  0x00,                                 ///< 33  SDRAM Device Type
+  0x00,                                 ///< 34  Fine Offset for SDRAM Minimum Cycle Time (tCKmin)
+  0x00,                                 ///< 35  Fine Offset for Minimum CAS Latency Time (tAAmin)
+  0x00,                                 ///< 36  Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin)
+  0x00,                                 ///< 37  Fine Offset for Minimum Row Precharge Delay Time (tRPmin)
+  0x00,                                 ///< 38  Fine Offset for Minimum Active to Active/Refresh Delay Time (tRCmin)
+  0x00,                                 ///< 39
+  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,         ///< 40 - 49
+  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,         ///< 50 - 59
+  0, 0,                                 ///< 60 - 61
+  0x45,                                 ///< 62  Reference Raw Card Used
+  0x00,                                 ///< 63  Address Mapping from Edge Connector to DRAM
+  0x00,                                 ///< 64  ThermalHeatSpreaderSolution
+  0, 0, 0, 0, 0,                        ///< 65 - 69
+  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,         ///< 70 - 79
+  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,         ///< 80 - 89
+  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,         ///< 90 - 99
+  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,         ///< 100 - 109
+  0, 0, 0, 0, 0, 0, 0,                  ///< 110 - 116
+  0x80,                                 ///< 117 Module Manufacturer ID Code, Least Significant Byte
+  0xCE,                                 ///< 118 Module Manufacturer ID Code, Most Significant Byte
+  0x01,                                 ///< 119 Module Manufacturing Location
+  0x11,                                 ///< 120 Module Manufacturing Date Year
+  0x02,                                 ///< 121 Module Manufacturing Date creation work week
+  0x44,                                 ///< 122 Module Serial Number A
+  0x0A,                                 ///< 123 Module Serial Number B
+  0x83,                                 ///< 124 Module Serial Number C
+  0x0C,                                 ///< 125 Module Serial Number D
+  0xA5,                                 ///< 126 CRC A
+  0x50                                  ///< 127 CRC B
+};
+#endif // EXAMPLE_BOARD_SUPPORT
+
+
+/**
+  Copies information from the Memory Down SPD structure to the SPD Input structure
+  in the Host structure.
+
+  Setting the SpdBaseAddress to zero means this slot has a memory down configuration.
+  For systems that have both memory down and slots, it is recommended to have the
+  memory down in the slot position farthest from the controller.
+
+  @param[in, out] Inputs  - MRC Host Input structure.
+  @param[in]      SpdIn   - Pointer to the Memory Down SPD structure to copy.
+  @param[in]      Slot    - Pointer to the Memory Down MemorySlotStatus structure.
+  @param[in]      SpdSize - Size of the SPD structure to limit MemoryCpy.
+
+  @retval - Nothing.
+**/
+void
+CopyMemoryDownSpd (
+  IN OUT MrcInput *const         Inputs,
+  IN     const U8                *SpdIn[MAX_CHANNEL][MAX_DIMMS_IN_CHANNEL],
+  IN     const MemorySlotStatus  *Slot,
+  IN     U16                     SpdSize
+  )
+{
+  MrcDimmIn *DimmIn;
+  U8        Channel;
+  U8        Dimm;
+
+  if (SpdIn == NULL || Slot == NULL || SpdSize == 0) {
+    return;
+  }
+
+  for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+    for (Dimm = 0; Dimm < MAX_DIMMS_IN_CHANNEL; Dimm++, Slot++) {
+      DimmIn = &Inputs->Controller[0].Channel[Channel].Dimm[Dimm];
+      switch (*Slot) {
+      case MEMORY_DOWN_ONLY:
+        DimmIn->SpdAddress  = 0;
+        // Check user request to disable DIMM/rank pair.
+        if (DimmIn->Status != DIMM_DISABLED) {
+          DimmIn->Status = DIMM_ENABLED;
+        MrcOemMemoryCpy ((U8 *) &DimmIn->Spd, (U8 *) SpdIn[Channel][Dimm], SpdSize);
+        MRC_DEBUG_MSG (&Inputs->Debug, MSG_LEVEL_NOTE, "Memory down present on channel %u, dimm %u\n", Channel, Dimm);
+        } else {
+          MRC_DEBUG_MSG (&Inputs->Debug, MSG_LEVEL_NOTE, "Memory down absent on channel %u, dimm %u\n", Channel, Dimm);
+        }
+        break;
+
+      case MEMORY_ABSENT:
+        DimmIn->Status      = DIMM_DISABLED;
+        DimmIn->SpdAddress  = 0;
+        MRC_DEBUG_MSG (&Inputs->Debug, MSG_LEVEL_NOTE, "Memory down absent on channel %u, dimm %u\n", Channel, Dimm);
+        break;
+
+      case MEMORY_SLOT_ONLY:
+      default:
+        break;
+      }
+    }
+  }
+
+  return;
+}
+
+/**
+  Enables Memory Down support and sets SPD data for all DIMMs needing support.
+
+  @param[in] Inputs  - MRC Input data structure.
+  @param[in] BoardId - The ID of the board.
+
+  @retval Nothing
+**/
+void
+EnableMemoryDown (
+  IN MrcInput *const Inputs,
+  IN U16             BoardId
+  )
+{
+  const U8                *SpdIn[MAX_CHANNEL][MAX_DIMMS_IN_CHANNEL];
+  const MemorySlotStatus  *Slot;
+  U16                     SpdSize;
+  U8                      Channel;
+  U8                      Dimm;
+#ifndef AMI_OVERRIDE_FOR_MEMORY_DOWN
+  const U8 *DimmSpdTbl = NULL;
+#endif // AMI_OVERRIDE_FOR_MEMORY_DOWN
+
+  Channel = 0;
+  Dimm    = 0;
+  SpdSize = 0;
+
+  switch (BoardId) {
+#if (defined EXAMPLE_BOARD_SUPPORT && (EXAMPLE_BOARD_SUPPORT > 0))
+
+  case 0:
+    //
+    // BoardIdExample:
+    //
+    for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+      for (Dimm = 0; Dimm < MAX_DIMMS_IN_CHANNEL; Dimm++) {
+#ifndef AMI_OVERRIDE_FOR_MEMORY_DOWN
+#if defined(NB_OEM_DIMM1_STATUS) && (NB_OEM_DIMM1_STATUS == 0x02)         
+          if (Channel == 0 && Dimm == 0) {
+             DimmSpdTbl = Dimm1SpdTbl;
+          }
+#endif
+#if defined(NB_OEM_DIMM2_STATUS) && (NB_OEM_DIMM2_STATUS == 0x02)         
+          if (Channel == 0 && Dimm == 1) {
+             DimmSpdTbl = Dimm2SpdTbl;
+          }
+#endif
+#if defined(NB_OEM_DIMM3_STATUS) && (NB_OEM_DIMM3_STATUS == 0x02)         
+          if (Channel == 1 && Dimm == 0) {
+             DimmSpdTbl = Dimm3SpdTbl;
+          }
+#endif     
+#if defined(NB_OEM_DIMM4_STATUS) && (NB_OEM_DIMM4_STATUS == 0x02)         
+          if (Channel == 1 && Dimm == 1) {
+             DimmSpdTbl = Dimm4SpdTbl;
+          }
+#endif
+          SpdIn[Channel][Dimm] = DimmSpdTbl;
+          if (DimmSpdTbl != NULL) {
+             DimmSpdTbl = NULL;
+          }
+#else
+        SpdIn[Channel][Dimm] = ExampleSpd;
+#endif // AMI_OVERRIDE_FOR_MEMORY_DOWN
+      }
+    }
+
+    Slot = (const MemorySlotStatus *) &ExampleSlotStatus[0][0];
+    SpdSize = sizeof(ExampleSpd);
+    break;
+#endif // EXAMPLE_BOARD_SUPPORT
+
+
+  //
+  // Add additional boards that support memory down here.
+  //
+
+  //
+  // The default case means the board ID was not recognized.  Instead
+  // we set Slot = NULL thus forcing us to read from the SPD.
+  //
+  default:
+    Slot  = NULL;
+  }
+
+  CopyMemoryDownSpd (Inputs, SpdIn, Slot, SpdSize);
+
+  return;
+}
+#endif // MEMORY_DOWN_SUPPORT
+
+#ifdef ULT_FLAG
+/**
+  Initialize the board-specific CMD/CTL/CLK and DQ/DQS mapping for LPDDR3.
+
+  @param[in, out] Inputs  - MRC Input data structure.
+  @param[in]      BoardId - The ID of the board.
+
+  @retval none
+**/
+void
+MrcOemLpddrBoardMapping (
+  IN OUT  MrcInput *Inputs,
+  IN      U16      BoardId
+  )
+{
+  MrcControllerIn *ControllerIn;
+  U8              *DqByteMapCh0;
+  U8              *DqByteMapCh1;
+  U8              *DqsMapCpu2DramCh0;
+  U8              *DqsMapCpu2DramCh1;
+  U8              *DqMapCpu2DramCh0;
+  U8              *DqMapCpu2DramCh1;
+  U32             Channel;
+  U32             Byte;
+
+
+  ControllerIn = &Inputs->Controller[0];
+  DqByteMapCh0      = NULL;
+  DqByteMapCh1      = NULL;
+  DqsMapCpu2DramCh0 = NULL;
+  DqsMapCpu2DramCh1 = NULL;
+  DqMapCpu2DramCh0  = NULL;
+  DqMapCpu2DramCh1  = NULL;
+
+  //
+  // CKE to Rank mapping:       CKE  | 0 1 2 3
+  // (same on both channels)    --------------
+  //                            Rank | 0 1 0 1
+  //
+  Inputs->CkeRankMapping = 0xAA;
+
+  //
+  // @todo: pass these via SaPlatformPolicy PPI
+  //
+  DqByteMapCh0      = (U8 *) DqByteMapRvpCh0;
+  DqByteMapCh1      = (U8 *) DqByteMapRvpCh1;
+  DqsMapCpu2DramCh0 = (U8 *) DqsMapCpu2DramRvpCh0;
+  DqsMapCpu2DramCh1 = (U8 *) DqsMapCpu2DramRvpCh1;
+  DqMapCpu2DramCh0  = (U8 *) DqMapCpu2DramRvpCh0;
+  DqMapCpu2DramCh1  = (U8 *) DqMapCpu2DramRvpCh1;
+
+
+  //
+  // DQ byte mapping to CMD/CTL/CLK
+  //
+  MrcOemMemoryCpy ((U8 *) ControllerIn->Channel[0].DQByteMap, DqByteMapCh0, sizeof (DqByteMapRvpCh0));
+  MrcOemMemoryCpy ((U8 *) ControllerIn->Channel[1].DQByteMap, DqByteMapCh1, sizeof (DqByteMapRvpCh1));
+
+  //
+  // DQS byte swizzling between CPU and DRAM
+  //
+  MrcOemMemoryCpy (ControllerIn->Channel[0].DqsMapCpu2Dram, DqsMapCpu2DramCh0, sizeof (DqsMapCpu2DramRvpCh0));
+  MrcOemMemoryCpy (ControllerIn->Channel[1].DqsMapCpu2Dram, DqsMapCpu2DramCh1, sizeof (DqsMapCpu2DramRvpCh1));
+
+  for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+    MRC_DEBUG_MSG (&Inputs->Debug, MSG_LEVEL_ERROR, "Ch %d DqsMapCpu2Dram: ", Channel);
+    for (Byte = 0; Byte < 8; Byte++) {
+      MRC_DEBUG_MSG (&Inputs->Debug, MSG_LEVEL_ERROR, "%d ", ControllerIn->Channel[Channel].DqsMapCpu2Dram[Byte]);
+    }
+    MRC_DEBUG_MSG (&Inputs->Debug, MSG_LEVEL_ERROR, "\n");
+  }
+
+  //
+  // DQ bit swizzling between CPU and DRAM
+  //
+  MrcOemMemoryCpy ((U8 *) ControllerIn->Channel[0].DqMapCpu2Dram, DqMapCpu2DramCh0, sizeof (DqMapCpu2DramRvpCh0));
+  MrcOemMemoryCpy ((U8 *) ControllerIn->Channel[1].DqMapCpu2Dram, DqMapCpu2DramCh1, sizeof (DqMapCpu2DramRvpCh0));
+}
+#endif // ULT_FLAG
+// AMI_OVERRIDE_FOR_UPSERVER_SUPPORT
+#ifdef UPSERVER_SUPPORT
+void
+MrcCltmDisable (
+  MrcParameters          *MrcData
+  )
+/*++
+
+Routine Description:
+
+  Disable CLTM configuration register if Outputs->CLTM_SPD_Conf = PROCESS_FAILED
+
+Arguments:
+
+  MrcData          - include all the MRC data.
+
+Returns:
+ None
+
+--*/
+{
+  MrcDebug                *Debug;
+  PCU_CR_DDR_PTM_CTL_PCU_STRUCT                         DdrPtmCtl;
+  ThermalMngmtEn          *ThermalEnables;
+  MrcInput                *Inputs;
+
+  Inputs          = &MrcData->SysIn.Inputs;
+  Debug           = &Inputs->Debug;
+  ThermalEnables  = &Inputs->ThermalEnables;
+
+    DdrPtmCtl.Data                    = MrcReadCR (MrcData, PCU_CR_DDR_PTM_CTL_PCU_REG);
+    DdrPtmCtl.Bits.OLTM_ENABLE        = ThermalEnables->EnableOltm;//Disable , 0,  Not available for UP Platforms
+    DdrPtmCtl.Bits.CLTM_ENABLE        = CLTM_DISABLE;//0, Disable.
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "CLTM is Disabled - Exiting.\n");
+    MrcWriteCR (MrcData, PCU_CR_DDR_PTM_CTL_PCU_REG, DdrPtmCtl.Data);
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "DDR_PTM_CTL %Xh: %Xh \n", PCU_CR_DDR_PTM_CTL_PCU_REG, MrcReadCR (MrcData, PCU_CR_DDR_PTM_CTL_PCU_REG));
+}
+
+void
+MrcCltmInit (
+  MrcParameters          *MrcData
+  )
+/*++
+
+Routine Description:
+
+  CLTM Initialization
+
+Arguments:
+
+  MrcData          - include all the MRC data.
+
+Returns:
+ None
+
+--*/
+{
+  MrcInput                *Inputs;
+  MrcOutput               *Outputs;
+  MrcDebug                *Debug;
+  ThermalMngmtEn          *ThermalEnables;
+  U8                      Controller;
+  U8                      Channel, Dimm;
+  U8                      OffsetDimm[2];
+  BOOL                    FirstValue;
+  PCU_CR_DDR_PTM_CTL_PCU_STRUCT                         DdrPtmCtl;
+  PCU_CR_DDR_ENERGY_SCALEFACTOR_PCU_STRUCT              DdrEnergyScaleFactor;
+  PCU_CR_DDR_WARM_THRESHOLD_CH0_PCU_STRUCT              DdrWarmThresholdCh0;
+  PCU_CR_DDR_WARM_THRESHOLD_CH1_PCU_STRUCT              DdrWarmThresholdCh1;
+  PCU_CR_DDR_HOT_THRESHOLD_CH0_PCU_STRUCT               DdrHotThresholdCh0;
+  PCU_CR_DDR_HOT_THRESHOLD_CH1_PCU_STRUCT               DdrHotThresholdCh1;
+  PCU_CR_DDR_WARM_BUDGET_CH0_PCU_STRUCT                 DdrWarmBudgetCh0;
+  PCU_CR_DDR_WARM_BUDGET_CH1_PCU_STRUCT                 DdrWarmBudgetCh1;
+  PCU_CR_DDR_HOT_BUDGET_CH0_PCU_STRUCT                  DdrHotBudgetCh0;
+  PCU_CR_DDR_HOT_BUDGET_CH1_PCU_STRUCT                  DdrHotBudgetCh1;
+  MCHBAR_CH0_CR_PM_DIMM_IDLE_ENERGY_STRUCT              PmDimmIdleEnergy;
+  MCHBAR_CH0_CR_PM_DIMM_PD_ENERGY_STRUCT                PmDimmPdEnergy;
+  MCHBAR_CH0_CR_PM_DIMM_ACT_ENERGY_STRUCT               PmDimmActEnergy;
+  MCHBAR_CH0_CR_PM_DIMM_RD_ENERGY_STRUCT                PmDimmRdEnergy;
+  MCHBAR_CH0_CR_PM_DIMM_WR_ENERGY_STRUCT                PmDimmWrEnergy;
+  TSOD_CONF_REGISTER_STRUCT                             TsodConfReg;
+
+  U8             h=0,i = 0, j = 0, k1 =2, k0=2 ; //h=2xRefreshMode i = Density , j = Frequency , k1 = Adjacent DIMM prescence in Channel 1, k0 = Adjacent DIMM prescence in Channel 0 
+  U8             iprev = 2, hotThreshold = 0, warmThreshold=0;
+  U8             ControllerSave = CONTROLLER_NOT_LOADED;
+  const U16      *PwrWeight0 = NULL, *PwrWeight1 = NULL ;
+  U16            MtsData = 0, Thigh = 0, Tcrit = 0, Temp = 0;
+  U16            freq=0, density= 0; 
+  Inputs          = &MrcData->SysIn.Inputs;
+  Debug           = &Inputs->Debug;
+  ThermalEnables  = &Inputs->ThermalEnables;
+  Outputs         = &MrcData->SysOut.Outputs;
+  TsodConfReg.Data =0;
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "MrcCltmInit - Start.\n");
+ 
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "EnableCltm %d EccSupport %d - \n", ThermalEnables->EnableCltm, Outputs->EccSupport);
+  if (ThermalEnables->EnableCltm  && (Outputs->EccSupport == TRUE)) {
+    FirstValue = FALSE;
+    if(Outputs->CLTM_SPD_Conf == PROCESS_NOT_INITIALIZED) {
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE,"CLTM_SPD_Config = %u\n",Outputs->CLTM_SPD_Conf);
+    for (Controller = 0; Controller < MAX_CONTROLLERS; Controller++) {
+    // Check in every DIMM for CLTM capabilities
+    for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+
+      if (Outputs->Controller[Controller].Channel[Channel].Status != CHANNEL_PRESENT) continue;
+
+      for (Dimm = 0; Dimm < MAX_DIMMS_IN_CHANNEL; Dimm++) {
+
+        if (Outputs->Controller[Controller].Channel[Channel].Dimm[Dimm].Status != DIMM_PRESENT) continue;
+
+        MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Channel %d Dimm %d - Check for CLTM Capabilities\n", Channel, Dimm);
+
+        // CHECK CLTM RESTRICTIONS
+
+        // Check ECC support. Do not enable CLTM if not supported.
+        if (Outputs->Controller[Controller].Channel[Channel].Dimm[Dimm].EccSupport == FALSE) {
+          MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "CLTM is Disable - Channel %d Dimm %d is non ECC - Exiting.\n", Channel, Dimm);
+          Outputs->CLTM_SPD_Conf = PROCESS_FAILED;
+          MrcCltmDisable(MrcData);
+          return;
+        }
+
+        // Check thermal sensor presence. Do not enable CLTM if no sensor.
+        if (Inputs->Controller[Controller].Channel[Channel].Dimm[Dimm].Spd.Ddr3.General.ModuleThermalSensor.Bits.ThermalSensorPresence == 0) {
+          MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "CLTM is Disable - Channel %d Dimm %d do not have Thermal Sensor Incorporated - Exiting.\n", Channel, Dimm);
+          Outputs->CLTM_SPD_Conf = PROCESS_FAILED;
+          MrcCltmDisable(MrcData);
+          return;
+        }
+/*All dimms will be taken as Raw Card E
+        // Check Refernce Raw Card = E . Do not enable CLTM if no Raw Card.
+        if (Inputs->Controller[Controller].Channel[Channel].Dimm[Dimm].Spd.Ddr3.Module.Unbuffered.ReferenceRawCardUsed.Bits.Card != rcE) {
+          MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Channel %d Dimm %d RAW Card is not E - CLTM disable.\n", Channel, Dimm);
+          Outputs->CLTM_SPD_Conf = PROCESS_FAILED;
+          MrcCltmDisable(MrcData);
+          return;
+        }
+*/
+         // Check if UDIMM. Do not enable CLTM if not UDIM 
+        if (Inputs->Controller[Controller].Channel[Channel].Dimm[Dimm].Spd.Ddr3.General.ModuleType.Bits.ModuleType != MRC_UDIMM_TYPE_NUMBER) {
+          MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Channel %d Dimm %d Module Type is not UDIMM - CLTM disable.\n", Channel, Dimm);
+          Outputs->CLTM_SPD_Conf = PROCESS_FAILED;
+          MrcCltmDisable(MrcData);
+          return;
+        }
+ /* All dimms will be configure as Dual Rank and x8
+       // Check if Dual Rank. Do not enable CLTM if not Dual Rank 
+        if (Outputs->Controller[Controller].Channel[Channel].Dimm[Dimm].RankInDIMM != 2) {
+          MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Channel %d Dimm %d not Dual Rank - CLTM disable.\n", Channel, Dimm);
+          Outputs->CLTM_SPD_Conf = PROCESS_FAILED;
+          MrcCltmDisable(MrcData);
+          return;
+        }
+
+        // Check if x8. Do not enable CLTM if not x8 
+        if (Outputs->Controller[Controller].Channel[Channel].Dimm[Dimm].SdramWidth != 8) {
+          Outputs->CLTM_SPD_Conf = PROCESS_FAILED;
+          MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Channel %d Dimm %d Width is not x8 - CLTM disable.\n", Channel, Dimm);
+          MrcCltmDisable(MrcData);
+          return;
+        } 
+*/
+           //switch (Outputs->Controller[Controller].Channel[Channel].Dimm[Dimm].DimmCapacity) {
+           switch (Inputs->Controller[Controller].Channel[Channel].Dimm[Dimm].Spd.Ddr3.General.SdramDensityAndBanks.Bits.Density) {
+          //case 2048:
+          case 3:  
+            i = 0;
+            if(FirstValue == FALSE) { iprev = i; }
+            if(iprev != i) {
+                //MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Channel %d Dimm %d Capacity is 2Gb and different from other previous DIMM - CLTM disable\n", Channel, Dimm);
+                MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Channel %d Dimm %d Density is 2Gb and different from other previous DIMM - configure as 4Gb\n", Channel, Dimm);
+                i = 1;
+            }
+            iprev =i;
+            //MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Channel %d Dimm %d Capacity is 2Gb\n", Channel, Dimm);
+            MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Channel %d Dimm %d Density is 2Gb\n", Channel, Dimm);
+            break;
+          //case 4096:
+           case 4:
+            i = 1;
+            if(FirstValue == FALSE) { iprev = i; }
+            if(iprev != i) {
+                //MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Channel %d Dimm %d Capacity is 4Gb and different from other previous DIMM\n", Channel, Dimm);
+                MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Channel %d Dimm %d Density is 4Gb and different from other previous DIMM\n", Channel, Dimm);
+                i = 1; 
+            }
+            iprev =i;
+            //MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Channel %d Dimm %d Capacity is 4Gb\n", Channel, Dimm);
+            MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Channel %d Dimm %d Density is 4Gb\n", Channel, Dimm);
+            break;
+          default:
+            //MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Channel %d Dimm %d Capacity is different than 4Gb and 2GB - CLTM disable \n", Channel, Dimm);
+            MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Channel %d Dimm %d Density is different than 4Gb and 2GB \n", Channel, Dimm);
+            i = 1; 
+            iprev =i;
+            break;
+          }
+         
+          if (Outputs->Controller[Controller].Channel[Channel].DimmCount > 1) {
+            if(Channel == 0) {k0 = 1;}
+            else{k1=1;}
+            MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Adjacent DIMM next to Dimm %d in Channel %d.\n", Dimm, Channel); 
+          } 
+          else {
+            if(Channel == 0) {k0 = 0;}
+            else{k1=0;}
+            MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "No adjacent DIMM next to Dimm %d in Channel %d.\n", Dimm, Channel);
+          }
+
+        // Check if DIMM supports dual refresh
+        if (((Inputs->Controller[Controller].Channel[Channel].Dimm[Dimm].Spd.Ddr3.General.ThermalAndRefreshOptions.Data & (MRC_BIT1 | MRC_BIT0)) == MRC_BIT0)) {
+          MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Channel %d Dimm %d Supports 2x Self Refresh\n", Channel, Dimm);
+        } else {
+          MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Channel %d Dimm %d DO NOT Support 2x Self Refresh\n", Channel, Dimm);
+          ThermalEnables->Refresh2X = DISABLE_REFRESH2X;
+          
+        }
+        h = ThermalEnables->Refresh2X;
+      FirstValue = TRUE;
+      } //for (Dimm = 0; Dimm < MAX_DIMMS_IN_CHANNEL; Dimm++)
+     } //for (Channel = 0; Channel < MAX_CHANNEL; Channel++)
+    }// for Controller
+    
+     //Frequency calculated from Common Memory Controller Frequency
+     switch (Outputs->Frequency) {
+          case f1600:
+            j = 0;
+            break;
+          case f1333:
+            j = 1;
+            break;
+          default:
+            j=0;
+            MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "MC Frequency is other than 1600 and 1333 - CLTM configure as 1600 .\n");
+            break;
+          }
+     MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE,"CLTM_SPD_Config check has finished for first time\n");
+    }
+    
+    if((Outputs->CLTM_SPD_Conf != PROCESS_FAILED) && (Outputs->CLTM_SPD_Conf != PROCESS_NOT_INITIALIZED) ) 
+     {
+         h = (((Outputs->CLTM_SPD_Conf)& (0x0300))>> 8); // mask with 0000 0011 0000 0000 and shift right 8, 2xRefreshMode
+         i = (((Outputs->CLTM_SPD_Conf)& (0x00C0))>> 6); // mask with 0000 0000 1100 0000 and shift right 6, Density index
+         j = (((Outputs->CLTM_SPD_Conf)& (0x0030))>> 4); // mask with 0000 0000 0011 0000 and shift right 4, Frequency
+         k1 = (((Outputs->CLTM_SPD_Conf)& (0x000C))>> 2); //mask 0000 0000 0000 1100 and shift right 2, Adjacent DIMM prescence of channel 1
+         k0 = ((Outputs->CLTM_SPD_Conf)& 0x0003);//mask with 0000 0000 0000 0011,  Adjacent DIMM prescence of channel 0
+         MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE,"DIMM variables: 2xRefresh Support,  frequency , adjacent, density has been initialized. \n "); 
+     }
+     else if (Outputs->CLTM_SPD_Conf == PROCESS_FAILED) 
+     {
+      MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "CLTM_SPD_Config already executed and Failed\n");
+      MrcCltmDisable(MrcData);
+      return; 
+     }
+
+     Outputs->CLTM_SPD_Conf = (h << 8)+ (i << 6) + (j<<4) + (k1<<2) + k0;
+     (i == 0)? (density = 2) : (density = 4);
+     (j == 0)? (freq = 1600) : (freq = 1333);
+
+
+     if ( ((k0==0)||(k0==1)) && ((k1==0)||(k1==1)) ){
+ 
+         MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE,"CLTM_SPD_Config interpret = \n  2xRefresh Support = %d , density = 2GB%d, frequency=%d, \n Channel 1 adjacent DIMM=%d, Channel 0 Adjacent DIMM =%d \n",h,density,freq,k1,k0);
+     }
+     else if (k1==2) {
+         MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE,"CLTM_SPD_Config interpret = \n 2xRefresh Support = %d ,density index=%d, frequency=%d, \n Channel 0 Adjacent DIMM =%d \n",h,density,freq,k0); 
+     }
+     else if (k0==2) {
+         MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE,"CLTM_SPD_Config interpret = \n 2xRefresh Support = %d ,density index=%d, frequency =%d, \n Channel 1 Adjacent DIMM =%d \n",h,density,freq,k1);
+     }
+     else{
+          MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE,"CLTM_SPD_Config interpret incorrectly k1=%d, or k0=%d are incorrect \n",k1,k0);
+         Outputs->CLTM_SPD_Conf = PROCESS_FAILED;
+         MrcCltmDisable(MrcData);
+         return;
+     }
+     
+      
+     MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE,"CLTM_SPD_Config = %u\n",Outputs->CLTM_SPD_Conf);  
+     
+     //Configuration Register of TSOD
+     TsodConfReg.Bits.EVENT_MODE             = ThermalEnables->TSOD_EventMode;//Default 1, Interrupt
+     TsodConfReg.Bits.EVENT_POLARITY         = ThermalEnables->TSOD_EventPolarity;//Default 0, Low
+     TsodConfReg.Bits.CRICAL_EVENT_ONLY      = ThermalEnables->TSOD_CriticalEventOnly;//Default 1, Enable
+     TsodConfReg.Bits.EVENT_OUTPUT_CONTROL   = ThermalEnables->TSOD_EventOutputControl; //Default 1, Enable
+     TsodConfReg.Bits.ALARM_WINDOW_LOCK      = ThermalEnables->TSOD_AlarmwindowLockBit; //Default 0, Unlock
+     TsodConfReg.Bits.CRITICAL_LOCK          = ThermalEnables->TSOD_CriticaltripLockBit; //Default 0, Unlock
+     TsodConfReg.Bits.SHUTDOWNMODE           = ThermalEnables->TSOD_ShutdownMode; // Default 0, TSOD Enable
+     TsodConfReg.Bits.HYST_ENABLE            = HYST_DISABLE; 
+
+     
+     DdrWarmThresholdCh0.Data        = 0;
+     DdrWarmThresholdCh1.Data        = 0;
+     DdrHotThresholdCh0.Data         = 0;
+     DdrHotThresholdCh1.Data         = 0;
+
+       if (!ThermalEnables->UserThresholdEn) {//Configuration of warm and hot threshold depending of single or dual refresh
+         if(h != DISABLE_REFRESH2X ) {
+          warmThreshold = ( WarmThreshold_2X_MAX_TEMP  );
+          hotThreshold = ( HotThreshold_2X_MAX_TEMP  );
+          
+         }
+         else{
+          warmThreshold = ( WarmThreshold_1X_MAX_TEMP  );
+          hotThreshold = ( HotThreshold_1X_MAX_TEMP  );
+          
+         }
+       }
+
+    for (Controller = 0; Controller < MAX_CONTROLLERS; Controller++) {
+    for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+
+      //OffsetChannel[Channel] = 0;
+
+      if (Outputs->Controller[Controller].Channel[Channel].Status != CHANNEL_PRESENT) continue;
+
+      for (Dimm = 0; Dimm < MAX_DIMMS_IN_CHANNEL; Dimm++) {
+
+        OffsetDimm[Dimm] = 0;
+        if (Outputs->Controller[Controller].Channel[Channel].Dimm[Dimm].Status != DIMM_PRESENT) continue;
+               ControllerSave = Controller;
+        MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "CLTM Configuration for Channel %d Dimm %d\n", Channel, Dimm);
+
+        // Get offset temperature
+        (Channel ==0) ? (OffsetDimm[Dimm] = CltmThermalLookUpTable[i][j][k0][ThermalEnables->Altitude]): (OffsetDimm[Dimm] = CltmThermalLookUpTable[i][j][k1][ThermalEnables->Altitude]);
+        
+        MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Offset = %d degreeC\n", OffsetDimm[Dimm]);
+
+        if (ThermalEnables->TSOD_ManEn) {
+          Thigh = ((ThermalEnables->TSOD_ThigMax) << 4);
+          Tcrit = ((ThermalEnables->TSOD_TcritMax) << 4);
+           
+        }
+        else{
+          Tcrit = (( (CRITICAL_TEMP) - OffsetDimm[Dimm]) << 4);
+          if(h != DISABLE_REFRESH2X ) {
+          Thigh = (( (THOT_2X_MAX_TEMP) - OffsetDimm[Dimm]) << 4);
+          }
+          else{
+          Thigh = (( (THOT_1X_MAX_TEMP) - OffsetDimm[Dimm]) << 4);
+          }
+          
+        }
+ 
+        // SPD Thermal sensor registers Configurations Begin
+        //((SpdDeviceAddress & 0x0F) | THERMAL_MODULE_MASK )         
+        //Thermal Sensor Information 
+        //  MFG ID
+        if (MrcOemSmbusRead16 (Inputs->SmbusBaseAddress, ((Inputs->Controller[Controller].Channel[Channel].Dimm[Dimm].SpdAddress & 0x0F) | THERMAL_MODULE_MASK ), MTS_MFGID, &MtsData) == mrcFail) {
+          MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Error - Channel %d Dimm %d Temp Sensor NACK\n", Channel, Dimm);
+        } else {
+          Temp = (((MtsData & 0xFF00) >> 8) | ((MtsData & 0x00FF) << 8));
+          MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Channel %d Dimm %d Temp Sensor Mfg Id = 0x%04X\n", Channel, Dimm, Temp);
+        }
+
+        // SPD thermal sensor DEV ID
+        
+        if (MrcOemSmbusRead16 (Inputs->SmbusBaseAddress, ((Inputs->Controller[Controller].Channel[Channel].Dimm[Dimm].SpdAddress & 0x0F) | THERMAL_MODULE_MASK ) , MTS_DID, &MtsData) == mrcFail) {
+          MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Error - Channel %d Dimm %d Temp Sensor NACK\n", Channel, Dimm);
+        } else {
+          Temp = (((MtsData & 0xFF00) >> 8) | ((MtsData & 0x00FF) << 8));
+          MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Channel %d Dimm %d Temp Sensor Dev/Rev Id = 0x%04X\n", Channel, Dimm, Temp);
+        }
+
+       // Configuration Register // Disabling Configuration Register
+        MtsData = 0;
+        Temp = (((MtsData & 0xFF00) >> 8) | ((MtsData & 0x00FF) << 8));
+       MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Thermal Sensor Configuration value to be programmed into TS2002 is 0x%X\n", Temp);
+        MrcOemSmbusWrite16 (Inputs->SmbusBaseAddress, ((Inputs->Controller[Controller].Channel[Channel].Dimm[Dimm].SpdAddress & 0x0F) | THERMAL_MODULE_MASK ), MTS_CFG, Temp);
+        MrcOemSmbusRead16 (Inputs->SmbusBaseAddress, ((Inputs->Controller[Controller].Channel[Channel].Dimm[Dimm].SpdAddress & 0x0F) | THERMAL_MODULE_MASK ), MTS_CFG, &MtsData);
+        Temp = (((MtsData & 0xFF00) >> 8) | ((MtsData & 0x00FF) << 8));
+        MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Thermal Sensor Configuration value read from TS2002 is 0x%X\n", MtsData);
+        MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Thermal Sensor Configuration value is 0x%X\n", Temp);
+
+        // THigh 0x02
+        
+        Temp = (((Thigh & 0xFF00) >> 8) | ((Thigh & 0x00FF) << 8));
+        MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "High Temp value is 0x%X = %d degreeC\n", Thigh, (Thigh >> 4));
+        MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "High Temp value to be programmed into TS2002 is 0x%X\n", Temp);
+        MrcOemSmbusWrite16 (Inputs->SmbusBaseAddress, ((Inputs->Controller[Controller].Channel[Channel].Dimm[Dimm].SpdAddress & 0x0F) | THERMAL_MODULE_MASK ), MTS_THIGH, Temp);
+        MrcOemSmbusRead16 (Inputs->SmbusBaseAddress, ((Inputs->Controller[Controller].Channel[Channel].Dimm[Dimm].SpdAddress & 0x0F) | THERMAL_MODULE_MASK ), MTS_THIGH, &Thigh);
+        Temp = (((Thigh & 0xFF00) >> 8) | ((Thigh & 0x00FF) << 8));
+        MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "High Temp value read from TS2002 is 0x%X\n", Thigh);
+        MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "High Temp value is 0x%X = %d degreeC\n", Temp, (Temp >> 4));
+        
+
+        // TCrit 0x04
+        Temp = (((Tcrit & 0xFF00) >> 8) | ((Tcrit & 0x00FF) << 8));
+        MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Critical Temp value is 0x%X = %d degreeC\n", Tcrit, (Tcrit >> 4));
+        MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Critical Temp value to be programmed into TS2002 is 0x%X\n", Temp);
+        MrcOemSmbusWrite16 (Inputs->SmbusBaseAddress, ((Inputs->Controller[Controller].Channel[Channel].Dimm[Dimm].SpdAddress & 0x0F) | THERMAL_MODULE_MASK ), MTS_TCRIT, Temp);
+        MrcOemSmbusRead16 (Inputs->SmbusBaseAddress, ((Inputs->Controller[Controller].Channel[Channel].Dimm[Dimm].SpdAddress & 0x0F) | THERMAL_MODULE_MASK ), MTS_TCRIT, &Tcrit);
+        Temp = (((Tcrit & 0xFF00) >> 8) | ((Tcrit & 0x00FF) << 8));
+        MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Critical Temp value read from TS2002 is 0x%X\n", Tcrit);
+        MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Critical Temp value is 0x%X = %d degreeC\n", Temp, (Temp >> 4));
+
+       // Configuration Register
+        MtsData = TsodConfReg.Data;
+        Temp = (((MtsData & 0xFF00) >> 8) | ((MtsData & 0x00FF) << 8));
+        MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Thermal Sensor Configuration value is 0x%X\n", MtsData);
+        MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Thermal Sensor Configuration value to be programmed into TS2002 is 0x%X\n", Temp);
+        MrcOemSmbusWrite16 (Inputs->SmbusBaseAddress, ((Inputs->Controller[Controller].Channel[Channel].Dimm[Dimm].SpdAddress & 0x0F) | THERMAL_MODULE_MASK ), MTS_CFG, Temp);
+        MrcOemSmbusRead16 (Inputs->SmbusBaseAddress, ((Inputs->Controller[Controller].Channel[Channel].Dimm[Dimm].SpdAddress & 0x0F) | THERMAL_MODULE_MASK ), MTS_CFG, &MtsData);
+        Temp = (((MtsData & 0xFF00) >> 8) | ((MtsData & 0x00FF) << 8));
+        MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Thermal Sensor Configuration value read from TS2002 is 0x%X\n", MtsData);
+        MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Thermal Sensor Configuration value is 0x%X\n", Temp);
+       // SPD thermal sensor registers Configurations End
+
+        //Read current temperature of the TSOD 0x05
+        MrcOemSmbusRead16 (Inputs->SmbusBaseAddress, ((Inputs->Controller[Controller].Channel[Channel].Dimm[Dimm].SpdAddress & 0x0F) | THERMAL_MODULE_MASK ), TEMPERATURE_REGISTER, &Thigh);
+        Temp = (((Thigh & 0xFF00) >> 8) | ((Thigh & 0x001F) << 8));//This will get rid of the firt three bits of the register and hold only the themperatur value
+        MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "SMBUS base Address is 0x%X\n", Inputs->SmbusBaseAddress);
+        MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "SPD address offset 0x%X of Channel:%d  DIMM:%d \n", Inputs->Controller[Controller].Channel[Channel].Dimm[Dimm].SpdAddress & 0x0F, Channel, Dimm);
+        MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Module thermal SPD address 0x%X of Channel:%d  DIMM:%d\n", ((Inputs->Controller[Controller].Channel[Channel].Dimm[Dimm].SpdAddress & 0x0F) | THERMAL_MODULE_MASK ), Channel, Dimm);
+        MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Offset to temperature register 0x%X\n", TEMPERATURE_REGISTER );
+        MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Temperature register value read from TS2002 is 0x%X\n", Thigh);
+        MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Current TSOD Temperatur value is 0x%X = %d degreeC\n", Temp, (Temp >> 4));
+        
+        //Warm and hot threshold Configuration begin
+       if(!ThermalEnables->UserThresholdEn) {
+          
+        if((Channel ==0)&& (Dimm == 0) ) {
+          DdrWarmThresholdCh0.Bits.DIMM0  = warmThreshold;
+          DdrHotThresholdCh0.Bits.DIMM0  = hotThreshold;
+        }
+         if((Channel ==0)&& (Dimm == 1) ) {
+          DdrWarmThresholdCh0.Bits.DIMM1  = warmThreshold;
+          DdrHotThresholdCh0.Bits.DIMM1  = hotThreshold;
+        }
+
+         if((Channel ==1)&& (Dimm == 0) ) {
+          DdrWarmThresholdCh1.Bits.DIMM0  = warmThreshold;
+          DdrHotThresholdCh1.Bits.DIMM0  = hotThreshold;
+        }
+
+         if((Channel ==1)&& (Dimm == 1) ) {
+          DdrWarmThresholdCh1.Bits.DIMM1  = warmThreshold;
+          DdrHotThresholdCh1.Bits.DIMM1  = hotThreshold;
+        }
+
+       }//Warm and hot threshold Configuration End
+
+     
+
+      } //for (Dimm = 0; Dimm < MAX_DIMMS_IN_CHANNEL; Dimm++)
+          
+    } //for (Channel = 0; Channel < MAX_CHANNEL; Channel++)
+    } // for Controller
+
+    if(!ThermalEnables->UserThresholdEn) {//Warm and hot threshold Write Registers begin
+              
+        MrcWriteCR (MrcData, PCU_CR_DDR_WARM_THRESHOLD_CH0_PCU_REG, DdrWarmThresholdCh0.Data);
+        MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "DDR_WARM_THRESHOLD_CH0 %Xh: %Xh \n", PCU_CR_DDR_WARM_THRESHOLD_CH0_PCU_REG, MrcReadCR (MrcData, PCU_CR_DDR_WARM_THRESHOLD_CH0_PCU_REG));
+    
+        MrcWriteCR (MrcData, PCU_CR_DDR_HOT_THRESHOLD_CH0_PCU_REG, DdrHotThresholdCh0.Data);
+        MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "DDR_HOT_THRESHOLD_CH0 %Xh: %Xh \n", PCU_CR_DDR_HOT_THRESHOLD_CH0_PCU_REG, MrcReadCR (MrcData, PCU_CR_DDR_HOT_THRESHOLD_CH0_PCU_REG));
+        
+        MrcWriteCR (MrcData, PCU_CR_DDR_WARM_THRESHOLD_CH1_PCU_REG, DdrWarmThresholdCh1.Data);
+        MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "DDR_WARM_THRESHOLD_CH1 %Xh: %Xh \n", PCU_CR_DDR_WARM_THRESHOLD_CH1_PCU_REG, MrcReadCR (MrcData, PCU_CR_DDR_WARM_THRESHOLD_CH1_PCU_REG));
+        
+        MrcWriteCR (MrcData, PCU_CR_DDR_HOT_THRESHOLD_CH1_PCU_REG, DdrHotThresholdCh1.Data);
+        MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "DDR_HOT_THRESHOLD_CH1 %Xh: %Xh \n", PCU_CR_DDR_HOT_THRESHOLD_CH1_PCU_REG, MrcReadCR (MrcData, PCU_CR_DDR_HOT_THRESHOLD_CH1_PCU_REG));
+        
+
+     }//Warm and hot threshold threshold Write Register End
+
+    
+    
+
+    ASSERT (ControllerSave != CONTROLLER_NOT_LOADED ); //If no controller is Save The system asserts
+    
+
+  if(!ThermalEnables->UserPowerWeightsEn) {
+      MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "UP Server overriding Power weight Energy registers...\n");
+      DdrEnergyScaleFactor.Data = 0;
+
+    if((k0==0)||(k0==1)) {
+        PwrWeight0 = &CltmPowerLookUpTable[i][j][k0][0];
+        ASSERT(PwrWeight0 != NULL);//If PwrWeight0 is Null the system asserts.
+        DdrEnergyScaleFactor.Bits.SCALEFACTOR = *PwrWeight0;
+    }
+    if((k1==0)||(k1==1)) {
+        PwrWeight1 = &CltmPowerLookUpTable[i][j][k1][0];
+        ASSERT(PwrWeight1 != NULL);//If PwrWeight1 is Null the system asserts.
+        DdrEnergyScaleFactor.Bits.SCALEFACTOR = *PwrWeight1;
+    }
+    
+    if ( ((k0==0)||(k0==1)) && ((k1==0)||(k1==1))) {
+        (k0 >= k1) ? (DdrEnergyScaleFactor.Bits.SCALEFACTOR = *PwrWeight0) : (DdrEnergyScaleFactor.Bits.SCALEFACTOR = *PwrWeight1);
+    }
+    
+    
+    
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "DDR_ENERGY_SCALEFACTOR %Xh: %Xh \n", PCU_CR_DDR_ENERGY_SCALEFACTOR_PCU_REG, DdrEnergyScaleFactor.Data);
+    MrcWriteCR (MrcData, PCU_CR_DDR_ENERGY_SCALEFACTOR_PCU_REG, DdrEnergyScaleFactor.Data);
+    
+
+    if((k0==0)||(k0==1)) {PwrWeight0++;}
+    if((k1==0)||(k1==1)) {PwrWeight1++;}
+    
+    PmDimmRdEnergy.Data = 0;
+
+    if ((k0==0)||(k0==1)){
+        if (Outputs->Controller[ControllerSave].Channel[0].Dimm[0].Status == DIMM_PRESENT){
+            PmDimmRdEnergy.Bits.DIMM0_RD_ENERGY = *PwrWeight0;
+        }
+        if (Outputs->Controller[ControllerSave].Channel[0].Dimm[1].Status == DIMM_PRESENT){
+            PmDimmRdEnergy.Bits.DIMM1_RD_ENERGY = *PwrWeight0;
+        }
+        
+    }
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "MCHBAR_CH0_CR_PM_DIMM_RD_ENERGY_REG %Xh: %Xh \n", MCHBAR_CH0_CR_PM_DIMM_RD_ENERGY_REG, PmDimmRdEnergy.Data);
+    MrcWriteCR (MrcData, MCHBAR_CH0_CR_PM_DIMM_RD_ENERGY_REG, PmDimmRdEnergy.Data); 
+
+
+    PmDimmRdEnergy.Data = 0;
+
+    if ((k1==0)||(k1==1)){
+        if (Outputs->Controller[ControllerSave].Channel[1].Dimm[0].Status == DIMM_PRESENT){
+            PmDimmRdEnergy.Bits.DIMM0_RD_ENERGY = *PwrWeight1; 
+            
+        }
+        if (Outputs->Controller[ControllerSave].Channel[1].Dimm[1].Status == DIMM_PRESENT){
+            PmDimmRdEnergy.Bits.DIMM1_RD_ENERGY = *PwrWeight1;
+        }
+
+    }
+        MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "MCHBAR_CH1_CR_PM_DIMM_RD_ENERGY_REG %Xh: %Xh \n", MCHBAR_CH1_CR_PM_DIMM_RD_ENERGY_REG, PmDimmRdEnergy.Data);
+        MrcWriteCR (MrcData, MCHBAR_CH1_CR_PM_DIMM_RD_ENERGY_REG, PmDimmRdEnergy.Data);    
+
+    if((k0==0)||(k0==1)) {PwrWeight0++;}
+    if((k1==0)||(k1==1)) {PwrWeight1++;}
+    PmDimmWrEnergy.Data                 = 0;
+
+    if ((k0==0)||(k0==1)){
+        if (Outputs->Controller[ControllerSave].Channel[0].Dimm[0].Status == DIMM_PRESENT){
+            PmDimmWrEnergy.Bits.DIMM0_WR_ENERGY = *PwrWeight0;
+        }
+        if (Outputs->Controller[ControllerSave].Channel[0].Dimm[1].Status == DIMM_PRESENT){
+            PmDimmWrEnergy.Bits.DIMM1_WR_ENERGY = *PwrWeight0;
+        }
+        
+    }
+   
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "MCHBAR_CH0_CR_PM_DIMM_WR_ENERGY_REG %Xh: %Xh \n", MCHBAR_CH0_CR_PM_DIMM_WR_ENERGY_REG, PmDimmWrEnergy.Data);
+    MrcWriteCR (MrcData, MCHBAR_CH0_CR_PM_DIMM_WR_ENERGY_REG, PmDimmWrEnergy.Data);
+
+    PmDimmWrEnergy.Data                 = 0;
+
+    if ((k1==0)||(k1==1)){
+        if (Outputs->Controller[ControllerSave].Channel[1].Dimm[0].Status == DIMM_PRESENT){
+             PmDimmWrEnergy.Bits.DIMM0_WR_ENERGY = *PwrWeight1;
+            
+        }
+        if (Outputs->Controller[ControllerSave].Channel[1].Dimm[1].Status == DIMM_PRESENT){
+            PmDimmWrEnergy.Bits.DIMM1_WR_ENERGY = *PwrWeight1;
+        }
+
+    }
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "MCHBAR_CH1_CR_PM_DIMM_WR_ENERGY_REG %Xh: %Xh \n", MCHBAR_CH1_CR_PM_DIMM_WR_ENERGY_REG, PmDimmWrEnergy.Data);
+    MrcWriteCR (MrcData, MCHBAR_CH1_CR_PM_DIMM_WR_ENERGY_REG, PmDimmWrEnergy.Data);
+
+    if((k0==0)||(k0==1)) {PwrWeight0++;}
+    if((k1==0)||(k1==1)) {PwrWeight1++;}
+    PmDimmActEnergy.Data                  = 0;
+    if ((k0==0)||(k0==1)){
+        if (Outputs->Controller[ControllerSave].Channel[0].Dimm[0].Status == DIMM_PRESENT){
+            PmDimmActEnergy.Bits.DIMM0_ACT_ENERGY = *PwrWeight0;
+        }
+        if (Outputs->Controller[ControllerSave].Channel[0].Dimm[1].Status == DIMM_PRESENT){
+            PmDimmActEnergy.Bits.DIMM1_ACT_ENERGY = *PwrWeight0;
+        }
+        
+    }
+        
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "MCHBAR_CH0_CR_PM_DIMM_ACT_ENERGY_REG %Xh: %Xh \n", MCHBAR_CH0_CR_PM_DIMM_ACT_ENERGY_REG, PmDimmActEnergy.Data);
+    MrcWriteCR (MrcData, MCHBAR_CH0_CR_PM_DIMM_ACT_ENERGY_REG, PmDimmActEnergy.Data);
+
+    PmDimmActEnergy.Data                  = 0;
+    if ((k1==0)||(k1==1)){
+        if (Outputs->Controller[ControllerSave].Channel[1].Dimm[0].Status == DIMM_PRESENT){
+            PmDimmActEnergy.Bits.DIMM0_ACT_ENERGY = *PwrWeight1;
+        }
+        if (Outputs->Controller[ControllerSave].Channel[1].Dimm[1].Status == DIMM_PRESENT){
+            PmDimmActEnergy.Bits.DIMM1_ACT_ENERGY = *PwrWeight1;
+        }
+        
+    }
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "MCHBAR_CH1_CR_PM_DIMM_ACT_ENERGY_REG %Xh: %Xh \n", MCHBAR_CH1_CR_PM_DIMM_ACT_ENERGY_REG, PmDimmActEnergy.Data);
+    MrcWriteCR (MrcData, MCHBAR_CH1_CR_PM_DIMM_ACT_ENERGY_REG, PmDimmActEnergy.Data);
+
+    if((k0==0)||(k0==1)) {PwrWeight0++;}
+    if((k1==0)||(k1==1)) {PwrWeight1++;}
+    PmDimmIdleEnergy.Data                   = 0;
+    if ((k0==0)||(k0==1)){
+        if (Outputs->Controller[ControllerSave].Channel[0].Dimm[0].Status == DIMM_PRESENT){
+            PmDimmIdleEnergy.Bits.DIMM0_IDLE_ENERGY = *PwrWeight0;
+        }
+        if (Outputs->Controller[ControllerSave].Channel[0].Dimm[1].Status == DIMM_PRESENT){
+            PmDimmIdleEnergy.Bits.DIMM1_IDLE_ENERGY = *PwrWeight0;
+        }
+
+    }
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "MCHBAR_CH0_CR_PM_DIMM_IDLE_ENERGY_REG %Xh: %Xh \n", MCHBAR_CH0_CR_PM_DIMM_IDLE_ENERGY_REG, PmDimmIdleEnergy.Data);
+    MrcWriteCR (MrcData, MCHBAR_CH0_CR_PM_DIMM_IDLE_ENERGY_REG, PmDimmIdleEnergy.Data);
+
+    PmDimmIdleEnergy.Data                   = 0;
+    if ((k1==0)||(k1==1)){
+        if (Outputs->Controller[ControllerSave].Channel[1].Dimm[0].Status == DIMM_PRESENT){
+            PmDimmIdleEnergy.Bits.DIMM0_IDLE_ENERGY = *PwrWeight1;
+        }
+        if (Outputs->Controller[ControllerSave].Channel[1].Dimm[1].Status == DIMM_PRESENT){
+            PmDimmIdleEnergy.Bits.DIMM1_IDLE_ENERGY = *PwrWeight1;
+        }
+
+    }
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "MCHBAR_CH1_CR_PM_DIMM_IDLE_ENERGY_REG %Xh: %Xh \n", MCHBAR_CH1_CR_PM_DIMM_IDLE_ENERGY_REG, PmDimmIdleEnergy.Data);
+    MrcWriteCR (MrcData, MCHBAR_CH1_CR_PM_DIMM_IDLE_ENERGY_REG, PmDimmIdleEnergy.Data);
+
+    if((k0==0)||(k0==1)) {PwrWeight0++;}
+    if((k1==0)||(k1==1)) {PwrWeight1++;}
+    PmDimmPdEnergy.Data                 = 0;
+    if ((k0==0)||(k0==1)){
+        if (Outputs->Controller[ControllerSave].Channel[0].Dimm[0].Status == DIMM_PRESENT){
+            PmDimmPdEnergy.Bits.DIMM0_PD_ENERGY = *PwrWeight0;
+        }
+        if (Outputs->Controller[ControllerSave].Channel[0].Dimm[1].Status == DIMM_PRESENT){
+            PmDimmPdEnergy.Bits.DIMM1_PD_ENERGY = *PwrWeight0;
+        }
+
+    }
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "MCHBAR_CH0_CR_PM_DIMM_PD_ENERGY_REG %Xh: %Xh \n", MCHBAR_CH0_CR_PM_DIMM_PD_ENERGY_REG, PmDimmPdEnergy.Data);
+    MrcWriteCR (MrcData, MCHBAR_CH0_CR_PM_DIMM_PD_ENERGY_REG, PmDimmPdEnergy.Data);
+
+    PmDimmPdEnergy.Data                 = 0;
+    if ((k1==0)||(k1==1)){
+        if (Outputs->Controller[ControllerSave].Channel[1].Dimm[0].Status == DIMM_PRESENT){
+            PmDimmPdEnergy.Bits.DIMM0_PD_ENERGY = *PwrWeight1;
+        }
+        if (Outputs->Controller[ControllerSave].Channel[1].Dimm[1].Status == DIMM_PRESENT){
+            PmDimmPdEnergy.Bits.DIMM1_PD_ENERGY = *PwrWeight1;
+        }
+
+    }
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "MCHBAR_CH1_CR_PM_DIMM_PD_ENERGY_REG %Xh: %Xh \n", MCHBAR_CH1_CR_PM_DIMM_PD_ENERGY_REG, PmDimmPdEnergy.Data);
+    MrcWriteCR (MrcData, MCHBAR_CH1_CR_PM_DIMM_PD_ENERGY_REG, PmDimmPdEnergy.Data);
+
+  }
+
+  if(!ThermalEnables->UserBudgetEn) {
+      MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "UP Server Overriding Power budget registers...\n");
+     
+    if((k0==0)||(k0==1)) {
+        PwrWeight0 = &CltmPowerLookUpTable[i][j][k0][0];
+        PwrWeight0 = PwrWeight0 + WARM_BUDGET_POSITION;
+        ASSERT(PwrWeight0 != NULL);//If PwrWeight0 is Null the system asserts.
+        
+    }
+    if((k1==0)||(k1==1)) {
+        PwrWeight1 = &CltmPowerLookUpTable[i][j][k1][0];
+        PwrWeight1 = PwrWeight1 + WARM_BUDGET_POSITION;
+        ASSERT(PwrWeight1 != NULL);//If PwrWeight1 is Null the system asserts.
+        
+    }
+
+    DdrWarmBudgetCh0.Data        = 0;
+    if ((k0==0)||(k0==1)){
+        if (Outputs->Controller[ControllerSave].Channel[0].Dimm[0].Status == DIMM_PRESENT){
+            DdrWarmBudgetCh0.Bits.DIMM0  = *PwrWeight0;
+        }
+        if (Outputs->Controller[ControllerSave].Channel[0].Dimm[1].Status == DIMM_PRESENT){
+            DdrWarmBudgetCh0.Bits.DIMM1  = *PwrWeight0;
+        }
+
+    }
+        
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "DDR_WARM_BUDGET_CH0 %Xh: %Xh \n", PCU_CR_DDR_WARM_BUDGET_CH0_PCU_REG, DdrWarmBudgetCh0.Data);
+    MrcWriteCR (MrcData, PCU_CR_DDR_WARM_BUDGET_CH0_PCU_REG, DdrWarmBudgetCh0.Data);
+
+    DdrWarmBudgetCh1.Data        = 0;
+    if ((k1==0)||(k1==1)){
+        if (Outputs->Controller[ControllerSave].Channel[1].Dimm[0].Status == DIMM_PRESENT){
+            DdrWarmBudgetCh1.Bits.DIMM0  = *PwrWeight1;
+        }
+        if (Outputs->Controller[ControllerSave].Channel[1].Dimm[1].Status == DIMM_PRESENT){
+            DdrWarmBudgetCh1.Bits.DIMM1  = *PwrWeight1;
+        }
+
+    }
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "DDR_WARM_BUDGET_CH1 %Xh: %Xh \n", PCU_CR_DDR_WARM_BUDGET_CH1_PCU_REG, DdrWarmBudgetCh1.Data);
+    MrcWriteCR (MrcData, PCU_CR_DDR_WARM_BUDGET_CH1_PCU_REG, DdrWarmBudgetCh1.Data);
+
+    if((k0==0)||(k0==1)) {PwrWeight0++;}
+    if((k1==0)||(k1==1)) {PwrWeight1++;}
+    DdrHotBudgetCh0.Data        = 0;
+    if ((k0==0)||(k0==1)){
+        if (Outputs->Controller[ControllerSave].Channel[0].Dimm[0].Status == DIMM_PRESENT){
+            DdrHotBudgetCh0.Bits.DIMM0  = *PwrWeight0;
+        }
+        if (Outputs->Controller[ControllerSave].Channel[0].Dimm[1].Status == DIMM_PRESENT){
+            DdrHotBudgetCh0.Bits.DIMM1  = *PwrWeight0;
+        }
+
+    }
+
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "DDR_HOT_BUDGET_CH0 %Xh: %Xh \n", PCU_CR_DDR_HOT_BUDGET_CH0_PCU_REG, DdrHotBudgetCh0.Data);
+    MrcWriteCR (MrcData, PCU_CR_DDR_HOT_BUDGET_CH0_PCU_REG, DdrHotBudgetCh0.Data);
+
+    DdrHotBudgetCh1.Data        = 0;
+
+    if ((k1==0)||(k1==1)){
+        if (Outputs->Controller[ControllerSave].Channel[1].Dimm[0].Status == DIMM_PRESENT){
+            DdrHotBudgetCh1.Bits.DIMM0  = *PwrWeight1;
+        }
+        if (Outputs->Controller[ControllerSave].Channel[1].Dimm[1].Status == DIMM_PRESENT){
+            DdrHotBudgetCh1.Bits.DIMM1  = *PwrWeight1;
+        }
+
+    }
+
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "DDR_HOT_BUDGET_CH1 %Xh: %Xh \n", PCU_CR_DDR_HOT_BUDGET_CH1_PCU_REG, DdrHotBudgetCh1.Data);
+    MrcWriteCR (MrcData, PCU_CR_DDR_HOT_BUDGET_CH1_PCU_REG, DdrHotBudgetCh1.Data);
+
+ }
+
+ 
+    //
+    // POWER THERMAL MANAGEMENT CONTROL
+    //
+    DdrPtmCtl.Data                    = MrcReadCR (MrcData, PCU_CR_DDR_PTM_CTL_PCU_REG);
+    DdrPtmCtl.Bits.OLTM_ENABLE        = ThermalEnables->EnableOltm;//Disable , 0,  Not available for UP Platforms
+    DdrPtmCtl.Bits.CLTM_ENABLE        = ThermalEnables->EnableCltm;//Default 1
+    DdrPtmCtl.Bits.REFRESH_2X_MODE    = ThermalEnables->Refresh2X;//Default 1, REFRESH_2X_WARM_HOT if dimm do not support then equals 0
+    /*
+    DdrPtmCtl.Bits.EXTTS_ENABLE       = ThermalEnables->EnableExtts;//Default 0
+    DdrPtmCtl.Bits.PDWN_CONFIG_CTL    = ThermalEnables->EnablePwrDn;//Default 1, BIOS is in control of powednmodes  
+    
+    //DdrPtmCtl.Bits.DISABLE_DRAM_TS  = !ThermalEnables->LpddrThermalSensor; //If not ULT this is disable or Value 1
+    */
+
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "DDR_PTM_CTL  %Xh to program: %Xh \n", PCU_CR_DDR_PTM_CTL_PCU_REG, DdrPtmCtl.Data);
+    MrcWriteCR (MrcData, PCU_CR_DDR_PTM_CTL_PCU_REG, DdrPtmCtl.Data);
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "DDR_PTM_CTL %Xh: %Xh \n", PCU_CR_DDR_PTM_CTL_PCU_REG, MrcReadCR (MrcData, PCU_CR_DDR_PTM_CTL_PCU_REG));
+     
+
+  } else {
+     //
+    // POWER THERMAL MANAGEMENT CONTROL
+    //
+    Outputs->CLTM_SPD_Conf = PROCESS_FAILED;
+    MrcCltmDisable(MrcData);
+    return;
+
+
+  }
+
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "MrcCltmInit - End.\n");
+ 
+}
+#endif // AMI_OVERRIDE_FOR_UPSERVER_SUPPORT
diff --git a/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/MrcOemPlatform.h b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/MrcOemPlatform.h
new file mode 100644
index 0000000..77006be
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/MrcOemPlatform.h
@@ -0,0 +1,357 @@
+/** @file
+  This file contains platform related functions.
+
+@copyright
+  Copyright (c) 1999 - 2013 Intel Corporation. All rights reserved.
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement
+**/
+#ifndef _MrcOemPlatform_h_
+#define _MrcOemPlatform_h_
+
+#include "MrcTypes.h"
+#include "MrcApi.h"
+#include "MrcOem.h"
+#include "MrcOemIo.h"
+#include "MrcOemMmio.h"
+#include "MrcWriteDqDqs.h"
+
+#ifdef MRC_MINIBIOS_BUILD
+
+#define GPIO_BASE_ADDRESS (0x800)
+
+#define PLATFORM_MB             (0x04)
+#define PLATFORM_SRVER          (0x01)
+#define PLATFORM_DT             (0x01)
+
+#define SB_BUS                  (0)
+#define SB_PCI2ISA_DEVICE       (31)
+#define SB_PCI2ISA_FUNC         (0)
+#define SB_PCI2ISA_BUS_DEV_FUNC ((SB_BUS << 8) + ((SB_PCI2ISA_DEVICE << 3) + SB_PCI2ISA_FUNC))
+#define PCI_LPC_BASE            (0x80000000 + (SB_PCI2ISA_BUS_DEV_FUNC << 8))
+
+///
+/// CPU Mobile SA Device IDs B0:D0:F0
+///
+#define MRC_SA_DEVICE_ID_MB_0        0x0C04   ///< Haswell Mobile SA DID
+#define MRC_SA_DEVICE_ID_MB_1        0x0A04   ///< Haswell Ult Mobile SA DID
+#define MRC_SA_DEVICE_ID_MB_2        0x0D04   ///< Crystalwell Mobile SA DID
+
+///
+/// CPU Desktop SA Device IDs B0:D0:F0
+///
+#define MRC_SA_DEVICE_ID_DT_0        0x0C00   ///< Haswell Desktop SA DID
+#define MRC_SA_DEVICE_ID_DT_1        0x0D00   ///< Crystalwell Desktop SA DID
+#define MRC_SA_DEVICE_ID_DT_2        0x0C0C   ///< Haswell Marketing SpareAffect SA DID
+
+///
+/// CPU Server SA Device IDs B0:D0:F0
+///
+#define MRC_SA_DEVICE_ID_SVR_0       0x0C08   ///< Haswell Server SA DID
+#define MRC_SA_DEVICE_ID_SVR_1       0x0D08   ///< Crystalwell Server SA DID
+
+#endif // MRC_MINIBIOS_BUILD
+#define MRC_EXIT_VALUE       (0xFF)
+#define PCU_CR_PLATFORM_INFO (0xCE)
+#define isprint(a)           (((a) >= ' ') && ((a) <= '~') ? (a) : 0)
+
+typedef enum {
+  RefRateLowTempOOS,  // Not safe
+  RefRateFourth,      // 4x tREFI - Not safe
+  RefRateHalf,        // 2x tREFI
+  RefRate1x,          // tREFI
+  RefRate2x,          // 1/2 tREFI
+  RefRate4x,          // 1/4 tREFI
+  RefRate4xDeRateAc,  // 1/4 tREFI de-rate AC timing - Not safe
+  RefRateHighTempOOS  // Not safe
+} LpddrRefreshRates;
+
+#pragma pack (push, 1)
+typedef union {
+  struct {
+    U32                         : 8;
+    U32 MAX_NON_TURBO_LIM_RATIO : 8;
+    U32                         : 16;
+    U32                         : 32;
+  } Bits;
+  U64 Data;
+  U32 Data32[2];
+  U16 Data16[4];
+  U8  Data8[8];
+} PCU_CR_PLATFORM_INFO_STRUCT;
+
+typedef union {
+  struct {
+    U32 Enable_2x_Refresh                       :  1;  // Bits 0:0
+    U32 LPDDR_Min_MR4                           :  3;  // Bits 1:3
+    U32                                         :  27; // Bits 4:30
+    U32 Lock_Bit                                :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MrcMailbox2xRefresh;
+#pragma pack (pop)
+/**
+  This function directs pCode to force 2x Refresh through the mailbox.
+
+  @param[in]  MrcData - Pointer to the MRC global data structure
+
+  @retval - Nothing.
+**/
+void
+MrcOemEnable2xRefresh (
+  IN MrcParameters *const MrcData
+  );
+
+/**
+  This function changes the DIMM Voltage to the closest desired voltage without
+  going higher. Default wait time is the minimum value of 200us, if more time
+  is needed before deassertion of DIMM Reset#, then change the parameter.
+
+  @param[in, out] MrcData            - The MRC "global data" area.
+  @param[in]      VddVoltage         - Selects the DDR voltage to use, in mV.
+  @param[in, out] VddSettleWaitTime  - Time needed for Vdd to settle after the update
+
+  @retval TRUE if a voltage change occurred, otherwise FALSE.
+**/
+extern
+BOOL
+MrcOemVDDVoltageCheckAndSwitch (
+  IN OUT MrcParameters      *MrcData,
+  IN     const MrcVddSelect VddVoltage,
+  IN OUT U32 * const        VddSettleWaitTime
+  );
+
+/**
+@brief
+  Gets CPU ratio - P-State ratio. for get the real time we need to multiply it in B CLK.
+
+  @param[in] Nothing
+
+  @retval U32 - PERF STATUS.
+**/
+extern
+U32
+MrcGetCpuRatio (
+  void
+  );
+
+/**
+@brief
+  Gets CPU current time - rdtsc value.
+  return the result in millisec.
+
+  @param[in] Nothing
+
+  @retval U64 - rdtsc value.
+**/
+extern
+U64
+MrcGetCpuTime (
+  void
+  );
+
+/**
+@brief
+  Sets CpuModel and CpuStepping in MrcData based on CpuModelStep.
+
+  @param[out] MrcData     - The Mrc Host data structure
+  @param[in]  CpuModel    - The CPU Family Model.
+  @param[in]  CpuStepping - The CPU Stepping.
+
+  @retval - mrcSuccess if the model and stepping is found.  Otherwise mrcFail
+**/
+MrcStatus
+MrcSetCpuInformation (
+  OUT MrcParameters  *MrcData,
+  IN  MrcCpuModel    CpuModel,
+  IN  MrcCpuStepping CpuStepping
+  );
+
+/**
+@brief
+  Gets CPU's random number generator.
+  return the GeneratedSeed result.
+
+  @param[in] Nothing
+
+  @retval U32 -           GeneratedSeed value.
+**/
+extern
+U32
+MrcGetRandomNumber (
+  void
+  );
+
+/**
+@brief
+  Hook before normal mode is enabled.
+
+  @param[in, out] MrcData  - The MRC "global data" area.
+
+  @retval Nothing.
+**/
+extern
+void
+MrcOemBeforeNormalModeTestMenu (
+  IN OUT MrcParameters *const MrcData
+  );
+
+/**
+@brief
+  Hook after normal mode is enabled
+
+  @param[in] MrcData  - The MRC "global data" area.
+
+  @retval Nothing.
+**/
+extern
+void
+MrcOemAfterNormalModeTestMenu (
+  IN MrcParameters *MrcData
+  );
+
+/**
+@brief
+  Overwrite Thermal settings
+
+  @param[in] MrcData  - The MRC "global data" area.
+
+  @retval Nothing.
+**/
+extern
+void
+MrcThermalOverwrites (
+  IN MrcParameters *MrcData
+  );
+
+
+/**
+@brief
+  this function use by the OEM to do dedicated task during the MRC.
+
+  @param[in] MrcData           - include all the MRC data
+  @param[in] OemStatusCommand  - A command that indicates the task to perform.
+  @param[in] ptr               - general ptr for general use.
+
+  @retval The status of the task.
+**/
+extern
+MrcStatus
+MrcOemCheckPoint (
+  IN MrcParameters        *MrcData,
+  IN MRC_OemStatusCommand OemStatusCommand,
+  IN void                 *ptr
+  );
+
+/**
+@brief
+  This function display on port 80 number.
+  It can be different debug interface.
+  This function can be use for any debug ability according to OEM requirements.
+
+  @param[in] MrcData            - Mrc Global Data
+  @param[in] DisplayDebugNumber - the number to display on port 80.
+
+  @retval Nothing
+**/
+extern
+void
+MrcOemDebugHook (
+  IN MrcParameters *MrcData,
+  IN U16           DisplayDebugNumber
+  );
+
+#ifdef UPSERVER_SUPPORT
+void
+MrcCltmInit (
+  MrcParameters *MrcData
+);
+
+void
+MrcCltmDisable (
+  MrcParameters *MrcData
+);
+#endif //UPSERVER_SUPPORT
+
+#ifdef MRC_DEBUG_PRINT
+/**
+@brief
+  Print the input parameters to the debug message output port.
+
+  @param[in] MrcData - The MRC global data.
+
+  @retval mrcSuccess
+**/
+extern
+MrcStatus
+MrcPrintInputParameters (
+  MrcParameters * const MrcData
+  );
+
+/**
+@brief
+  Print the specified memory to the serial message debug port.
+
+  @param[in] Debug - Serial message debug structure.
+  @param[in] Start - The starting address to dump.
+  @param[in] Size  - The amount of data in bytes to dump.
+
+  @retval Nothing.
+**/
+extern
+void
+MrcPrintMemory (
+  IN const MrcDebug *const Debug,
+  IN const U8 *const       Start,
+  IN const U32              Size
+  );
+#endif
+
+#if (defined MEMORY_DOWN_SUPPORT && (MEMORY_DOWN_SUPPORT > 0))
+/**
+@brief
+  Enables Memory Down support and sets SPD data for all DIMMs needing support.
+
+  @param[in, out] Inputs - MRC Input data structure.
+  @param[in]      BoardId - The ID of the board.
+
+  @retval Nothing
+**/
+extern
+void
+EnableMemoryDown (
+  IN OUT MrcInput *const Inputs,
+  IN     U16             BoardId
+  );
+#endif  // MEMORY_DOWN_SUPPORT
+
+/**
+@brief
+  Initialize the board-specific CMD/CTL/CLK and DQ/DQS mapping for LPDDR3.
+
+  @param[in, out] Inputs  - MRC Input data structure.
+  @param[in]      BoardId - The ID of the board.
+
+  @retval none
+**/
+void
+MrcOemLpddrBoardMapping (
+  IN OUT  MrcInput *Inputs,
+  IN      U16      BoardId
+  );
+
+#endif // _MrcOemPlatform_h_
diff --git a/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/MrcOemSmbus.c b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/MrcOemSmbus.c
new file mode 100644
index 0000000..3aee432
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/MrcOemSmbus.c
@@ -0,0 +1,188 @@
+/** @file
+  This file contains SMBus related functions.
+
+@copyright
+  Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved.
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement.
+**/
+
+#include "MrcOemSmbus.h"
+
+#ifdef NOSMBUS_BUILD
+///
+/// DDR3 1600 2GB single rank
+///
+const U8 SPDData[] =
+  {0x92, 0x11, 0x0B, 0x02, 0x03, 0x19, 0x02, 0x01, 0x03, 0x11, 0x01, 0x08, 0x0A, 0x00, 0xFE, 0x00, /// 00-15
+   0x69, 0x78, 0x69, 0x30, 0x69, 0x11, 0x18, 0x81, 0x00, 0x05, 0x3C, 0x3C, 0x00, 0xF0, 0x83, 0x01, /// 16-31
+   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /// 32-47
+   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x11, 0x61, 0x00, /// 48-63
+   0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x00, 0x00, 0x00, 0x80                                      /// 64-73
+};
+#endif
+
+/**
+@brief
+  Perform a byte read from the specified SMBus device address.
+
+  @param[in] SmbusBaseAddress   - The SMBus base address.
+  @param[in] SmBusDeviceAddress - SMBus device address to read from.
+  @param[in] Offset             - Byte offset to read from.
+  @param[out] Value             - Location to store read value.
+
+  @retval: mrcSuccess if the read is successful, otherwise mrcFail and the read data is set to zero.
+**/
+MrcStatus
+MrcOemSmbusRead8 (
+  IN const U32  SmbusBaseAddress,
+  IN const U8   SmBusDeviceAddress,
+  IN const U8   Offset,
+  OUT U8 *const Value
+  )
+{
+  MrcStatus     Status;
+  RETURN_STATUS EfiStatus;
+
+#ifdef NOSMBUS_BUILD
+  if (SmBusDeviceAddress == 0xA0) {
+    //
+    // For CH0 - DIMM0 only
+    //
+    *Value  = SPDData[Offset];
+    Status  = mrcSuccess;
+  } else {
+    Status = mrcFail;
+  }
+
+#else
+  *Value = SmBusReadDataByte (SmBusDeviceAddress | ((U32) Offset << 8), &EfiStatus);
+  if (EfiStatus == RETURN_SUCCESS) {
+    Status = mrcSuccess;
+  } else {
+    Status = mrcFail;
+  }
+#endif // NOSMBUS_BUILD
+
+  if (Status != mrcSuccess) {
+    *Value = 0;
+  }
+
+  return Status;
+}
+
+/**
+@brief
+  Perform a byte write to the specified SMBus device address.
+
+  @param[in] SmbusBaseAddress   - The SMBus base address.
+  @param[in] SmBusDeviceAddress - SMBus device address to write to.
+  @param[in] Offset             - Byte offset to write to.
+  @param[in] Value              - The value to write.
+
+  @retval: mrcSuccess if the write is successful, otherwise mrcFail.
+**/
+MrcStatus
+MrcOemSmbusWrite8 (
+  IN const U32  SmbusBaseAddress,
+  IN const U8   SmBusDeviceAddress,
+  IN const U8   Offset,
+  IN U8         Value
+  )
+{
+
+  MrcStatus     Status;
+  RETURN_STATUS EfiStatus;
+
+  SmBusWriteDataByte (SmBusDeviceAddress | ((U32) Offset << 8), Value, &EfiStatus);
+  Status = (EfiStatus == RETURN_SUCCESS) ? mrcSuccess : mrcFail;
+  return Status;
+}
+
+/**
+@brief
+  Perform a word read from the specified SMBus device address.
+
+  @param[in] SmbusBaseAddress   - The SMBus base address.
+  @param[in] SmBusDeviceAddress - SMBus device address to read from.
+  @param[in] Offset             - Offset to read from.
+  @param[out] Value             - Location to store read value.
+
+  @retval:  mrcSuccess if the read is successful, otherwise mrcFail and the read data is set to zero.
+**/
+MrcStatus
+MrcOemSmbusRead16 (
+  IN const U32   SmbusBaseAddress,
+  IN const U8    SmBusDeviceAddress,
+  IN const U8    Offset,
+  OUT U16 *const Value
+  )
+{
+  MrcStatus     Status;
+  RETURN_STATUS EfiStatus;
+
+#ifdef NOSMBUS_BUILD
+  if (SmBusDeviceAddress == 0xA0) {
+    //
+    // For CH0 - DIMM0 only
+    //
+    *Value  = SPDData[Offset];
+    Status  = mrcSuccess;
+  } else {
+    Status = mrcFail;
+  }
+
+#else
+  *Value = SmBusReadDataWord (SmBusDeviceAddress | ((U32) Offset << 8), &EfiStatus);
+  if (EfiStatus == RETURN_SUCCESS) {
+    Status = mrcSuccess;
+  } else {
+    Status = mrcFail;
+  }
+#endif // NOSMBUS_BUILD
+
+  if (Status != mrcSuccess) {
+    *Value = 0;
+  }
+
+  return Status;
+}
+
+/**
+@brief
+  Perform a word write to the specified SMBus device address.
+
+  @param[in] SmbusBaseAddress   - The SMBus base address.
+  @param[in] SmBusDeviceAddress - SMBus device address to write to.
+  @param[in] Offset             - Offset to write to.
+  @param[in] Value              - The value to write.
+
+  @retval:  mrcSuccess if the write is successful, otherwise mrcFail.
+**/
+MrcStatus
+MrcOemSmbusWrite16 (
+  IN const U32  SmbusBaseAddress,
+  IN const U8   SmBusDeviceAddress,
+  IN const U8   Offset,
+  IN U16        Value
+  )
+{
+  MrcStatus     Status;
+  RETURN_STATUS EfiStatus;
+
+  SmBusWriteDataWord (SmBusDeviceAddress | ((U32) Offset << 8), Value, &EfiStatus);
+  Status = (EfiStatus == RETURN_SUCCESS) ? mrcSuccess : mrcFail;
+  return Status;
+}
diff --git a/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/MrcOemSmbus.h b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/MrcOemSmbus.h
new file mode 100644
index 0000000..c6569bd
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/MrcOemSmbus.h
@@ -0,0 +1,119 @@
+/** @file
+  This file contains SMBus related functions.
+
+@copyright
+  Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved.
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement.
+**/
+#ifndef _MrcOemSmbus_h_
+#define _MrcOemSmbus_h_
+
+#ifndef MRC_MINIBIOS_BUILD
+#include <Tiano.h>
+#include <EdkIIGlueBaseTypes.h>
+#include <EdkIIGlueSmbusLib.h>
+#endif // MRC_MINIBIOS_BUILD
+#pragma pack (push, 1)
+#include "MrcTypes.h"
+#include "MrcApi.h"
+#include "MrcOemDebugPrint.h"
+
+#ifdef MRC_MINIBIOS_BUILD
+#include "smb.h"
+#endif // MRC_MINIBIOS_BUILD
+
+/**
+@brief
+  Perform a byte read from the specified SMBus device address.
+
+  @param[in] SmbusBaseAddress   - The SMBus base address.
+  @param[in] SmBusDeviceAddress - SMBus device address to read from.
+  @param[in] Offset             - Byte offset to read from.
+  @param[out] Value             - Location to store read value.
+
+  @retval: mrcSuccess if the read is successful, otherwise mrcFail and the read data is set to zero.
+**/
+extern
+MrcStatus
+MrcOemSmbusRead8 (
+  IN const U32  SmbusBaseAddress,
+  IN const U8   SmBusDeviceAddress,
+  IN const U8   Offset,
+  OUT U8 *const Value
+  );
+
+/**
+@brief
+  Perform a byte write to the specified SMBus device address.
+
+  @param[in] SmbusBaseAddress   - The SMBus base address.
+  @param[in] SmBusDeviceAddress - SMBus device address to write to.
+  @param[in] Offset             - Byte offset to write to.
+  @param[in] Value              - The value to write.
+
+  @retval: mrcSuccess if the write is successful, otherwise mrcFail.
+**/
+extern
+MrcStatus
+MrcOemSmbusWrite8 (
+  IN const U32  SmbusBaseAddress,
+  IN const U8   SmBusDeviceAddress,
+  IN const U8   Offset,
+  IN U8         Value
+  );
+
+/**
+@brief
+  Perform a word read from the specified SMBus device address.
+
+  @param[in] SmbusBaseAddress   - The SMBus base address.
+  @param[in] SmBusDeviceAddress - SMBus device address to read from.
+  @param[in] Offset             - Offset to read from.
+  @param[out] Value             - Location to store read value.
+
+  @retval:  mrcSuccess if the read is successful, otherwise mrcFail and the read data is set to zero.
+**/
+extern
+MrcStatus
+MrcOemSmbusRead16 (
+  IN const U32   SmbusBaseAddress,
+  IN const U8    SmBusDeviceAddress,
+  IN const U8    Offset,
+  OUT U16 *const Value
+  );
+
+/**
+@brief
+  Perform a word write to the specified SMBus device address.
+
+  @param[in] SmbusBaseAddress   - The SMBus base address.
+  @param[in] SmBusDeviceAddress - SMBus device address to write to.
+  @param[in] Offset             - Offset to write to.
+  @param[in] Value              - The value to write.
+
+  @retval:  mrcSuccess if the write is successful, otherwise mrcFail.
+**/
+extern
+MrcStatus
+MrcOemSmbusWrite16 (
+  IN const U32  SmbusBaseAddress,
+  IN const U8   SmBusDeviceAddress,
+  IN const U8   Offset,
+  IN U16        Value
+  );
+
+#pragma pack(pop)
+#endif // _MrcOemSmbus_h_
diff --git a/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/MrcSpdDriver.c b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/MrcSpdDriver.c
new file mode 100644
index 0000000..fe916cc
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/MrcSpdDriver.c
@@ -0,0 +1,291 @@
+/** @file
+
+  This file contains functions that read the SPD data for each DIMM slot over
+  the SMBus interface.
+
+@copyright
+  Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved.
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement.
+
+**/
+
+#include "MrcSpdDriver.h"
+#include "MrcSpdProcessing.h"
+
+#define MAX_SPD_PAGE_COUNT (1)
+#define MAX_SPD_PAGE_SIZE  (256)
+#define MAX_SPD_SIZE       (MAX_SPD_PAGE_SIZE * MAX_SPD_PAGE_COUNT)
+#define SPD_PAGE_ADDRESS_0 (0x6C)
+#define SPD_PAGE_ADDRESS_1 (0x6E)
+
+/**
+@brief
+  Read the SPD data over the SMBus, at the specified SPD address, starting at
+  the specified starting offset and read the given amount of data.
+
+  @param[in, out] Inputs - Mrc Inputs structure
+  @param[in] SpdAddress  - SPD SMBUS address
+  @param[in, out] Buffer - Buffer to store the data.
+  @param[in] Start       - Starting SPD offset
+  @param[in] Size        - The number of bytes of data to read and also the size of the buffer.
+  @param[in, out] Page   - The final page that is being pointed to.
+
+  @retval mrcSuccess if the read is successful, otherwise mrcDimmNotExist, which
+  @retval indicates that no slots are populated.
+**/
+static
+MrcStatus
+MrcDoSpdRead (
+  IN OUT MrcInput *const Inputs,
+  IN     const U8        SpdAddress,
+  IN OUT U8 *const       Buffer,
+  IN     const U16       Start,
+  IN           U16       Size,
+  IN OUT U8              *Page
+  )
+{
+  MrcDebug  *Debug;
+  MrcStatus Status;
+  BOOL      PageUpdate;
+  U16       Count;
+  U16       Index;
+
+  Debug  = &Inputs->Debug;
+  Status = mrcFail;
+  if ((Buffer != NULL) && (Start < MAX_SPD_SIZE) && ((Start + Size) < MAX_SPD_SIZE)) {
+    Count = 0;
+    PageUpdate = FALSE;
+    while (Size--) {
+      Index = Start + Count;
+      if ((Index / MAX_SPD_PAGE_SIZE) != *Page) {
+        *Page = (U8) (Index / MAX_SPD_PAGE_SIZE);
+        PageUpdate = TRUE;
+      }
+      Index %= MAX_SPD_PAGE_SIZE;
+      if (PageUpdate == TRUE) {
+        PageUpdate = FALSE;
+        MrcOemSmbusWrite8 (Inputs->SmbusBaseAddress, (*Page == 0) ? SPD_PAGE_ADDRESS_0 : SPD_PAGE_ADDRESS_1, 0, 0);
+      }
+      Status = MrcOemSmbusRead8 (Inputs->SmbusBaseAddress, SpdAddress, (U8) Index, &Buffer[Count]);
+      if (mrcSuccess != Status) {
+        break;
+      }
+      Count++;
+    }
+  }
+  return (Status);
+}
+
+/**
+@brief
+  See if there is valid XMP SPD data.
+
+  @param[in] Debug    - Mrc debug structure.
+  @param[in, out] Spd - Mrc SPD structure.
+  @param[in] XmpStart - The current offset in the SPD.
+
+  @retval TRUE if valid, FALSE in not.
+**/
+static
+BOOL
+VerifyXmp (
+  IN MrcDebug          *Debug,
+  IN OUT MrcSpd *const Spd,
+  IN const U16         XmpStart
+  )
+{
+  SPD_EXTREME_MEMORY_PROFILE_HEADER *Header;
+
+  switch (Spd->Ddr3.General.DramDeviceType.Bits.Type) {
+#if ((SUPPORT_DDR3 == SUPPORT) || (SUPPORT_LPDDR3 == SUPPORT))
+#if (SUPPORT_DDR3 == SUPPORT)
+  case MRC_SPD_DDR3_SDRAM_TYPE_NUMBER:
+#endif
+#if (SUPPORT_LPDDR3 == SUPPORT)
+  case MRC_SPD_LPDDR3_SDRAM_TYPE_NUMBER:
+#endif
+    Header = &Spd->Ddr3.Xmp.Header;
+    break;
+#endif
+  default:
+    return (FALSE);
+  }
+  if (XmpStart == ((U32) (Header) - (U32) Spd)) {
+    if ((XMP_ID_STRING == Header->XmpId) && ((Header->XmpRevision.Data & 0xFE) == 0x12)) {
+      return (TRUE);
+    } else {
+      Header->XmpId            = 0;
+      Header->XmpOrgConf.Data  = 0;
+      Header->XmpRevision.Data = 0;
+    }
+  } else {
+    return (TRUE);
+  }
+  return (FALSE);
+}
+
+/**
+@brief
+  Read the SPD data over the SMBus, for all DIMM slots and copy the data to the MrcData structure.
+  The SPD data locations read is controlled by the current boot mode.
+
+  @param[in] BootMode - Mrc Boot Mode
+  @param[in, out] Inputs - Mrc Inputs structure
+
+  @retval mrcSuccess if the read is successful, otherwise mrcDimmNotExist, which
+  @retval indicates that no slots are populated.
+**/
+MrcStatus
+MrcGetSpdData (
+  IN     const MrcBootMode BootMode,
+  IN OUT MrcInput *const   Inputs
+  )
+{
+#pragma pack (push, 1)
+  typedef struct {
+    U16 Start;
+    U16 End;
+    U8  BootMode;
+    U8  Profile;
+  } SpdOffsetTable;
+#pragma pack (pop)
+  const SpdOffsetTable Table3[] = {
+#ifdef ULT_FLAG
+    {   0,              40,           (1 << bmCold),                                   (1 << STD_PROFILE) | (1 << XMP_PROFILE1) | (1 << XMP_PROFILE2) | (1 << USER_PROFILE) },
+#else  // ULT_FLAG
+    {   0,              38,           (1 << bmCold),                                   (1 << STD_PROFILE) | (1 << XMP_PROFILE1) | (1 << XMP_PROFILE2) | (1 << USER_PROFILE) },
+#endif // ULT_FLAG
+    {  60,              63,           (1 << bmCold),                                   (1 << STD_PROFILE) | (1 << XMP_PROFILE1) | (1 << XMP_PROFILE2) | (1 << USER_PROFILE) },
+    { SPD3_MANUF_START, SPD3_MANUF_END, (1 << bmCold) | (1 << bmWarm) | (1 << bmFast), (1 << STD_PROFILE) | (1 << XMP_PROFILE1) | (1 << XMP_PROFILE2) | (1 << USER_PROFILE) },
+    { 128,             145,           (1 << bmCold),                                   (1 << STD_PROFILE) | (1 << XMP_PROFILE1) | (1 << XMP_PROFILE2) | (1 << USER_PROFILE) },
+#if (SUPPORT_SPD_CRC == SUPPORT)
+    {  39,              59,           (1 << bmCold),                                   (1 << STD_PROFILE) | (1 << XMP_PROFILE1) | (1 << XMP_PROFILE2) | (1 << USER_PROFILE) },
+    {  64,             125,           (1 << bmCold),                                   (1 << STD_PROFILE) | (1 << XMP_PROFILE1) | (1 << XMP_PROFILE2) | (1 << USER_PROFILE) },
+#endif
+#if SUPPORT_XMP == SUPPORT
+    { 176,             179,           (1 << bmCold),                                   (1 << STD_PROFILE) | (1 << XMP_PROFILE1) | (1 << XMP_PROFILE2) | (1 << USER_PROFILE) },
+    { 180,             184,           (1 << bmCold),                                   (1 << STD_PROFILE) | (1 << XMP_PROFILE1) | (1 << XMP_PROFILE2) | (1 << USER_PROFILE) },
+    { 185,             215,           (1 << bmCold),                                   (1 << STD_PROFILE) | (1 << XMP_PROFILE1) | (1 << XMP_PROFILE2) | (1 << USER_PROFILE) },
+    { 220,             250,           (1 << bmCold),                                   (1 << STD_PROFILE) | (1 << XMP_PROFILE1) | (1 << XMP_PROFILE2) | (1 << USER_PROFILE) },
+#endif
+  };
+  MrcDebug              *Debug;
+  MrcControllerIn       *ControllerIn;
+  MrcChannelIn          *ChannelIn;
+  MrcDimmIn             *DimmIn;
+  U8                    *Buffer;
+  const SpdOffsetTable  *Tbl;
+  const SpdOffsetTable  *TableSelect;
+  MrcStatus             Status;
+  U16                   Offset;
+#ifdef MRC_DEBUG_PRINT
+  U16                   Line;
+  U16                   Address;
+#endif
+  U8                    Controller;
+  U8                    Channel;
+  U8                    Dimm;
+  U8                    Count;
+  U8                    Index;
+  U8                    Stop;
+  U8                    Page;
+
+  Debug = &Inputs->Debug;
+  Count = 0;
+  Page  = 0;
+  for (Controller = 0; Controller < MAX_CONTROLLERS; Controller++) {
+    ControllerIn = &Inputs->Controller[Controller];
+    for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+      ChannelIn = &ControllerIn->Channel[Channel];
+      if (ChannelIn->Status == CHANNEL_PRESENT) {
+        for (Dimm = 0; Dimm < MAX_DIMMS_IN_CHANNEL; Dimm++) {
+          Status  = mrcSuccess;
+          DimmIn  = &ChannelIn->Dimm[Dimm];
+          if ((DimmIn->Status == DIMM_ENABLED) || (DimmIn->Status == DIMM_DISABLED)) {
+            Buffer = (U8 *) &DimmIn->Spd;
+            if (DimmIn->SpdAddress > 0) {
+                    TableSelect = Table3;
+                    Stop = (sizeof (Table3) / sizeof (SpdOffsetTable));
+              for (Index = 0; (Status == mrcSuccess) && (Index < Stop); Index++) {
+                Tbl = &TableSelect[Index];
+                if (((1 << BootMode) & Tbl->BootMode) && ((1 << Inputs->MemoryProfile) & Tbl->Profile)) {
+                  Status = MrcDoSpdRead (
+                    Inputs,
+                    DimmIn->SpdAddress,
+                    &Buffer[Tbl->Start],
+                    Tbl->Start,
+                    Tbl->End - Tbl->Start + 1,
+                    &Page
+                    );
+                  if (Status == mrcSuccess) {
+                    for (Offset = Tbl->Start; Offset <= Tbl->End; Offset++) {
+                      DimmIn->SpdValid[Offset / CHAR_BITS] |= 1 << (Offset % CHAR_BITS);
+                    }
+#if SUPPORT_XMP == SUPPORT
+                    if (bmCold == BootMode) {
+                      if (FALSE == VerifyXmp (Debug, (MrcSpd *) Buffer, Tbl->Start)) {
+                       MRC_DEBUG_MSG (
+                        Debug,
+                        MSG_LEVEL_NOTE,
+                        "VerifyXmp FALSE\n"
+                        );
+                       break;
+                      }
+                    }
+#endif // SUPPORT_XMP
+                  } else {
+                    MRC_DEBUG_MSG (
+                      Debug,
+                      MSG_LEVEL_WARNING,
+                      "ERROR! Fail to read SMB DimmAddress %Xh Offset %Xh - %Xh\n",
+                      DimmIn->SpdAddress,
+                      Tbl->Start,
+                      Tbl->End
+                      );
+                  } // if (Status...
+                } // if (((1 << BootMode)...
+              }  // for (Index...
+            }  else { // if (DimmIn->SpdAddress > 0), 0 = MemoryDown, see EnableMemoryDown()
+              Status = mrcSuccess;
+            }
+
+            if (Status == mrcSuccess) {
+              Count++;
+#ifdef MRC_DEBUG_PRINT
+              MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\nChannel %d Dimm %d\n", Channel, Dimm);
+              MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "SPD:           00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F\n");
+              for (Line = 0; Line < (sizeof (MrcSpd) / 16); Line++) {
+                Address = Line * 16;
+                MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, " % 4Xh(% 5u): ", Address, Address);
+                for (Offset = 0; Offset < 16; Offset++) {
+                  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%02X ", Buffer[Address + Offset]);
+                }
+                for (Offset = 0; Offset < 16; Offset++) {
+                  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%c", isprint (Buffer[Address + Offset]) ? Buffer[Address + Offset] : '.');
+                }
+                MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\n");
+              }
+#endif
+            } else {
+              MRC_DEBUG_MSG (Debug, MSG_LEVEL_WARNING, "DIMM is not populated on channel %u, slot %u\n", Channel, Dimm);
+            } // if (Status...
+          }  // if (DimmIn->Status == DIMM_ENABLED)
+        }  // for (Dimm...
+      }  // if (ChannelIn->Status...
+    }  // for (Channel...
+  }  // for (Controller...
+  return ((Count > 0) ? mrcSuccess : mrcDimmNotExist);
+}
diff --git a/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/MrcSpdDriver.h b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/MrcSpdDriver.h
new file mode 100644
index 0000000..9031f9c
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/MrcSpdDriver.h
@@ -0,0 +1,50 @@
+/** @file
+  This file contains functions that read the SPD data for each DIMM slot over
+  the SMBus interface.
+
+@Copyright
+  Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved.
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement
+**/
+
+#ifndef _MrcSpdDriver_h_
+#define _MrcSpdDriver_h_
+
+#include "MrcTypes.h"
+#include "MrcApi.h"
+#include "MrcGlobal.h"
+#include "MrcOemDebugPrint.h"
+#include "MrcOemSmbus.h"
+
+/**
+@brief
+  Read the SPD data over the SMBus, for all DIMM slots and copy the data to the MrcData structure.
+  The SPD data locations read is controlled by the current boot mode.
+
+  @param[in] BootMode - Mrc Boot Mode
+  @param[in] Inputs - Mrc Inputs structure
+
+  @retval mrcSuccess if the read is successful, otherwise mrcDimmNotExist, which
+  @retval indicates that no slots are populated.
+**/
+extern
+MrcStatus
+MrcGetSpdData (
+  IN     const MrcBootMode BootMode,
+  IN OUT MrcInput *const   Inputs
+  );
+
+#endif
diff --git a/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/MrcSsaServices.c b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/MrcSsaServices.c
new file mode 100644
index 0000000..2a74103
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/MrcSsaServices.c
@@ -0,0 +1,2338 @@
+/**
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement.
+
+@copyright
+  Copyright (c) 2012 - 2013 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+@file
+  MrcSsaServices.c
+
+@brief
+  This file contains the SSA BIOS services PPI.
+**/
+
+#include "MrcGlobal.h"
+#include "MrcDdr3.h"
+#include "MrcOemDebugPrint.h"
+#include "MrcOemIo.h"
+#include "MrcOemMmio.h"
+#include "MrcOemPlatform.h"
+#include "MrcOemSmbus.h"
+#include "MrcSsaServices.h"
+
+#define MAX_CADB_ENTRIES                (16)
+#define REUT_CPGC_OFFSET                (0x400)
+#define EXTRA_INDEX_OFFSET              (1)
+#define SSA_REVISION_BIOS               (('0' << 24) | ('0' << 16) | ('7' << 8) | '5')
+#define SSA_REVISION_COMMON             (('0' << 24) | ('0' << 16) | ('7' << 8) | '5')
+#define SSA_REVISION_MEMORY             (('0' << 24) | ('0' << 16) | ('7' << 8) | '5')
+#define SPD_SENSOR_BASE_ADDRESS         (0x30)
+#define SPD_SENSOR_TEMPERATURE_OFFSET   (5)
+
+extern EFI_GUID gSsaBiosServicesPpiGuid;
+
+typedef union {
+  struct {
+    UINT32  Low;
+    UINT32  High;
+  } Data32;
+  UINT64 Data;
+} UINT64_STRUCT;
+
+#ifdef SSA_FLAG
+
+/**
+
+@brief
+  Verify that the indicated socket is present and enabled.
+
+  @param[in] MrcData - Pointer to the MRC global data area.
+  @param[in] Socket  - Zero based CPU socket number.
+
+  @retval TRUE if present and enabled, otherwise FALSE.
+
+**/
+static
+BOOLEAN
+IsSocketPresent (
+  const MrcParameters * const MrcData,
+  const UINT8                 Socket
+  )
+{
+  return ((Socket < MAX_CPU_SOCKETS) ? TRUE : FALSE);
+}
+
+/**
+
+@brief
+  Verify that the indicated controller is present and enabled.
+
+  @param[in] MrcData    - Pointer to the MRC global data area.
+  @param[in] Socket     - Zero based CPU socket number.
+  @param[in] Controller - Zero based memory controller number.
+
+  @retval TRUE if present and enabled, otherwise FALSE.
+
+**/
+static
+BOOLEAN
+IsControllerPresent (
+  const MrcParameters * const MrcData,
+  const UINT8                 Socket,
+  const UINT8                 Controller
+  )
+{
+  return (((IsSocketPresent (MrcData, Socket)) &&
+    (Controller < MAX_CONTROLLERS) &&
+    (MrcData->SysOut.Outputs.Controller[Controller].Status == CONTROLLER_PRESENT)) ?
+    TRUE : FALSE);
+}
+
+/**
+
+@brief
+  Verify that the indicated channel is present and enabled.
+
+  @param[in] MrcData    - Pointer to the MRC global data area.
+  @param[in] Socket     - Zero based CPU socket number.
+  @param[in] Controller - Zero based memory controller number.
+  @param[in] Channel    - Zero based memory channel number.
+
+  @retval TRUE if present and enabled, otherwise FALSE.
+
+**/
+static
+BOOLEAN
+IsChannelPresent (
+  const MrcParameters * const MrcData,
+  const UINT8                 Socket,
+  const UINT8                 Controller,
+  const UINT8                 Channel
+  )
+{
+  return (((IsControllerPresent (MrcData, Socket, Controller)) &&
+    (Channel < MAX_CHANNEL) &&
+    (MrcData->SysOut.Outputs.Controller[Controller].Channel[Channel].Status == CHANNEL_PRESENT)) ?
+    TRUE : FALSE);
+}
+
+/**
+
+@brief
+  Verify that the indicated DIMM is present and enabled.
+
+  @param[in] MrcData    - Pointer to the MRC global data area.
+  @param[in] Socket     - Zero based CPU socket number.
+  @param[in] Controller - Zero based memory controller number.
+  @param[in] Channel    - Zero based memory channel number.
+  @param[in] Dimm       - Zero based memory DIMM number.
+
+  @retval TRUE if present and enabled, otherwise FALSE.
+
+**/
+static
+BOOLEAN
+IsDimmPresent (
+  const MrcParameters * const MrcData,
+  const UINT8                 Socket,
+  const UINT8                 Controller,
+  const UINT8                 Channel,
+  const UINT8                 Dimm
+  )
+{
+  return (((IsChannelPresent (MrcData, Socket, Controller, Channel)) &&
+    (Dimm < MAX_DIMMS_IN_CHANNEL) &&
+    (MrcData->SysOut.Outputs.Controller[Controller].Channel[Channel].Dimm[Dimm].Status == DIMM_PRESENT)) ?
+    TRUE : FALSE);
+}
+
+/**
+
+@brief
+  Verify that the indicated rank is present and enabled.
+
+  @param[in] MrcData    - Pointer to the MRC global data area.
+  @param[in] Socket     - Zero based CPU socket number.
+  @param[in] Controller - Zero based memory controller number.
+  @param[in] Channel    - Zero based memory channel number.
+  @param[in] Dimm       - Zero based memory DIMM number.
+  @param[in] Rank       - Zero based memory rank number in the DIMM.
+
+  @retval TRUE if present and enabled, otherwise FALSE.
+
+**/
+static
+BOOLEAN
+IsRankPresent (
+  const MrcParameters * const MrcData,
+  const UINT8                 Socket,
+  const UINT8                 Controller,
+  const UINT8                 Channel,
+  const UINT8                 Dimm,
+  const UINT8                 Rank
+  )
+{
+  return (((IsDimmPresent (MrcData, Socket, Controller, Channel, Dimm)) &&
+    (Rank < MAX_RANK_IN_DIMM) &&
+    ((MrcData->SysOut.Outputs.Controller[Controller].Channel[Channel].Dimm[Dimm].RankInDIMM - 1) >= Rank)) ?
+    TRUE : FALSE);
+}
+
+/**
+
+@brief
+  Initialize the heap so that malloc and free can be used.
+
+  @param[in] MrcData    - Pointer to the MRC global data area.
+
+  @retval TRUE if present and enabled, otherwise FALSE.
+
+**/
+
+static
+BOOLEAN
+InitHeap (
+  const MrcParameters * const MrcData
+  )
+{
+  const MrcInput *Inputs;
+  UINT8          *HeapLimitPtr;
+  HeapBufHeader  *HeapBase;
+  UINT8          *BaseAddr;
+
+  Inputs = &MrcData->SysIn.Inputs;
+
+  //
+  // If heap is provided
+  //
+  if (Inputs->SsaHeapSize) {
+    BaseAddr     = (UINT8 *) Inputs->SsaHeapBase;
+    HeapLimitPtr = BaseAddr + Inputs->SsaHeapSize;
+
+    //
+    // Initialize the start header
+    //
+    HeapBase                 = (HeapBufHeader *) BaseAddr;
+    HeapBase->BufBase        = BaseAddr + sizeof (HeapBufHeader);
+    HeapBase->BufLimit       = Inputs->SsaHeapSize - (2 * sizeof (HeapBufHeader));
+    HeapBase->BufFlags.Data  = 0;
+
+    //
+    // Initialize the end header
+    //
+    HeapBase                        = (HeapBufHeader *) (HeapLimitPtr - sizeof (HeapBufHeader));
+    HeapBase->BufBase               = HeapLimitPtr;
+    HeapBase->BufLimit              = 0;
+    HeapBase->BufFlags.Bits.HeapEnd = 1;
+    return TRUE;
+  }
+  return FALSE;
+}
+
+/**
+
+@brief
+  Reads a variable-sized value from a memory mapped register using an absolute address.
+  This function takes advantage of any caching implemented by BIOS.
+
+  @param[in, out] PeiServices - An indirect pointer to the PEI Services Table published by the PEI Foundation.
+  @param[in, out] This        - Interface pointer that implements the particular SSA_BIOS_SERVICES_PPI instance.
+  @param[in]      Width       - The size of the value to write.
+  @param[in]      Address     - Address of the register to be accessed.
+  @param[out]     Buffer      - Value storage location.
+
+  @retval Nothing.
+
+**/
+static
+VOID
+ReadMem (
+  EFI_PEI_SERVICES      **PeiServices,
+  SSA_BIOS_SERVICES_PPI *This,
+  REG_WIDTH             Width,
+  EFI_PHYSICAL_ADDRESS  Address,
+  VOID                  *Buffer
+  )
+{
+  MMIO_BUFFER *MmioBuffer;
+
+  MmioBuffer = (MMIO_BUFFER *) Buffer;
+  switch (Width) {
+    case RegWidth8:
+      MrcOemMmioRead8 ((U32) Address, &MmioBuffer->Data8, 0);
+      break;
+
+    case RegWidth16:
+      MrcOemMmioRead16 ((U32) Address, &MmioBuffer->Data16, 0);
+      break;
+
+    case RegWidth32:
+      MrcOemMmioRead ((U32) Address, &MmioBuffer->Data32, 0);
+      break;
+
+    case RegWidth64:
+      MrcOemMmioRead64 ((U32) Address, &MmioBuffer->Data64, 0);
+      break;
+
+    default:
+      break;
+  }
+  return;
+}
+
+/**
+
+@brief
+  Writes a variable sized value to a memory mapped register using an absolute address.
+  
+  @param[in, out] PeiServices - An indirect pointer to the PEI Services Table published by the PEI Foundation.
+  @param[in, out] This        - Interface pointer that implements the particular SSA_BIOS_SERVICES_PPI instance.
+  @param[in]      Width       - The size of the value to write.
+  @param[in]      Address     - Address of the register to be accessed.
+  @param[in]      Buffer      - Value to write.
+
+  @retval Nothing.
+
+**/
+static
+VOID
+WriteMem (
+  EFI_PEI_SERVICES      **PeiServices,
+  SSA_BIOS_SERVICES_PPI *This,
+  REG_WIDTH             Width,
+  EFI_PHYSICAL_ADDRESS  Address,
+  VOID                  *Buffer
+  )
+{
+  MMIO_BUFFER         *MmioBuffer;
+
+  MmioBuffer = (MMIO_BUFFER *) Buffer;
+  switch (Width) {
+    case RegWidth8:
+      MrcOemMmioWrite8 ((U32) Address, MmioBuffer->Data8, 0);
+      break;
+
+    case RegWidth16:
+      MrcOemMmioWrite16 ((U32) Address, MmioBuffer->Data16, 0);
+      break;
+
+    case RegWidth32:
+      MrcOemMmioWrite ((U32) Address, MmioBuffer->Data32, 0);
+      break;
+
+    case RegWidth64:
+      MrcOemMmioWrite64 ((U32) Address, MmioBuffer->Data64, 0);
+      break;
+
+    default:
+      break;
+  }
+  return;
+}
+
+/**
+
+@brief
+  Reads a variable sized value from I/O.
+  This function takes advantage of any caching implemented by BIOS.
+
+  @param[in, out] PeiServices - An indirect pointer to the PEI Services Table published by the PEI Foundation.
+  @param[in, out] This        - Interface pointer that implements the particular SSA_BIOS_SERVICES_PPI instance.
+  @param[in]      Width       - The size of the value to write.
+  @param[in]      Address     - Address of the I/O to be accessed.
+  @param[out]     Buffer      - Value storage location.
+
+  @retval Nothing.
+
+**/
+static
+VOID
+ReadIo (
+  EFI_PEI_SERVICES      **PeiServices,
+  SSA_BIOS_SERVICES_PPI *This,
+  REG_WIDTH             Width,
+  UINT32                Address,
+  VOID                  *Buffer
+  )
+{
+  IO_BUFFER           *IoBuffer;
+
+  IoBuffer = (IO_BUFFER *) Buffer;
+  switch (Width) {
+    case RegWidth8:
+      IoBuffer->Data8 = MrcOemInPort8 ((UINT16) Address);
+      break;
+
+    case RegWidth16:
+      IoBuffer->Data16 = MrcOemInPort16 ((UINT16) Address);
+      break;
+
+    case RegWidth32:
+      IoBuffer->Data32 = MrcOemInPort32 ((UINT16) Address);
+      break;
+
+    default:
+      break;
+  }
+  return;
+}
+
+/**
+
+@brief
+  Writes a variable sized value to I/O.
+  
+  @param[in, out] PeiServices - An indirect pointer to the PEI Services Table published by the PEI Foundation.
+  @param[in, out] This        - Interface pointer that implements the particular SSA_BIOS_SERVICES_PPI instance.
+  @param[in]      Width       - The size of the value to write.
+  @param[in]      Address     - Address of the I/O to be accessed.
+  @param[in]      Buffer      - Value to write.
+
+  @retval Nothing.
+
+**/
+static
+VOID
+WriteIo (
+  EFI_PEI_SERVICES      **PeiServices,
+  SSA_BIOS_SERVICES_PPI *This,
+  REG_WIDTH             Width,
+  UINT32                Address,
+  VOID                  *Buffer
+  )
+{
+  IO_BUFFER           *IoBuffer;
+
+  IoBuffer = (IO_BUFFER *) Buffer;
+  switch (Width) {
+    case RegWidth8:
+      MrcOemOutPort8 ((UINT16) Address, IoBuffer->Data8);
+      break;
+
+    case RegWidth16:
+      MrcOemOutPort16 ((UINT16) Address, IoBuffer->Data16);
+      break;
+
+    case RegWidth32:
+      MrcOemOutPort32 ((UINT16) Address, IoBuffer->Data32);
+      break;
+
+    default:
+      break;
+  }
+  return;
+}
+
+/**
+
+@brief
+  Reads a variable sized value from the PCI config space register.
+  This function takes advantage of any caching implemented by BIOS.
+
+  @param[in, out] PeiServices - An indirect pointer to the PEI Services Table published by the PEI Foundation.
+  @param[in, out] This        - Interface pointer that implements the particular SSA_BIOS_SERVICES_PPI instance.
+  @param[in]      Width       - The size of the value to write.
+  @param[in]      Address     - Address of the I/O to be accessed. Must be modulo 'Width'.
+  @param[out]     Buffer      - Value storage location.
+  @param[in]      CachedData  - If set to TRUE, returns the Cached data (if applicable) for performance. If set to FALSE returns the data read from device. 
+
+  @retval Nothing.
+
+**/
+static
+VOID
+ReadPci (
+  EFI_PEI_SERVICES                **PeiServices,
+  SSA_BIOS_SERVICES_PPI           *This,
+  REG_WIDTH                       Width,
+  EFI_PEI_PCI_CFG_PPI_PCI_ADDRESS *Address,
+  VOID                            *Buffer,
+  BOOLEAN                         CachedData
+  )
+{
+  PCI_BUFFER        *PciBuffer;
+  PCI_CONFIG_SPACE  PciAddress;
+  UINT32            Value;
+
+  PciBuffer                 = (PCI_BUFFER *) Buffer;
+  PciAddress.Value          = 0;
+  PciAddress.Bits.Bus       = Address->Bus;
+  PciAddress.Bits.Device    = Address->Device;
+  PciAddress.Bits.Function  = Address->Function;
+  PciAddress.Bits.Offset    = Address->Register;
+  PciAddress.Bits.Enable    = 1;
+  MrcOemOutPort32 (MrcOemPciIndex (), PciAddress.Value);
+  Value = MrcOemInPort32 (MrcOemPciData ());
+
+  switch (Width) {
+    case RegWidth8:
+      PciBuffer->Data8 = (UINT8) Value;
+      break;
+
+    case RegWidth16:
+      PciBuffer->Data16 = (UINT16) Value;
+      break;
+
+    case RegWidth32:
+      PciBuffer->Data32 = Value;
+      break;
+
+    default:
+      break;
+  }
+
+  return;
+}
+
+/**
+
+@brief
+  Writes a variable sized value to the PCI config space register.
+  
+  @param[in, out] PeiServices - An indirect pointer to the PEI Services Table published by the PEI Foundation.
+  @param[in, out] This        - Interface pointer that implements the particular SSA_BIOS_SERVICES_PPI instance.
+  @param[in]      Width       - The size of the value to write.
+  @param[in]      Address     - Address of the I/O to be accessed. Must be modulo 'Width'.
+  @param[in]      Buffer      - Value to write.
+  @param[in]      CachedData  - If set to TRUE, returns the Cached data (if applicable) for performance. If set to FALSE returns the data read from device. 
+
+  @retval Nothing.
+
+**/
+static
+VOID
+WritePci (
+  EFI_PEI_SERVICES                **PeiServices,
+  SSA_BIOS_SERVICES_PPI           *This,
+  REG_WIDTH                       Width,
+  EFI_PEI_PCI_CFG_PPI_PCI_ADDRESS *Address,
+  VOID                            *Buffer,
+  BOOLEAN                         CachedData
+  )
+{
+  PCI_BUFFER        *PciBuffer;
+  PCI_CONFIG_SPACE  PciAddress;
+  BOOLEAN           DoIt;
+  UINT32            Value;
+
+  PciBuffer                 = (PCI_BUFFER *) Buffer;
+  DoIt                      = TRUE;
+  PciAddress.Value          = 0;
+  PciAddress.Bits.Bus       = Address->Bus;
+  PciAddress.Bits.Device    = Address->Device;
+  PciAddress.Bits.Function  = Address->Function;
+  PciAddress.Bits.Offset    = Address->Register;
+  PciAddress.Bits.Enable    = 1;
+  Value                     = 0;
+
+  switch (Width) {
+    case RegWidth8:
+      ReadPci (PeiServices, This, RegWidth32, Address, (PCI_BUFFER *) &Value, FALSE);
+      Value &= ~0xFF;
+      Value |= PciBuffer->Data8;
+      break;
+
+    case RegWidth16:
+      ReadPci (PeiServices, This, RegWidth32, Address, (PCI_BUFFER *) &Value, FALSE);
+      Value &= ~0xFFFF;
+      Value |= PciBuffer->Data16;
+      break;
+
+    case RegWidth32:
+      Value = PciBuffer->Data32;
+      break;
+
+    default:
+      Value = 0;
+      DoIt  = FALSE;
+      break;
+  }
+
+  if (DoIt) {
+    MrcOemOutPort32 (MrcOemPciIndex (), PciAddress.Value);
+    MrcOemOutPort32 (MrcOemPciData (), Value);
+  }
+
+  return;
+}
+
+/**
+
+@brief
+  Gets a base address to be used in the different memory map or MMIO register access functions.
+  
+  @param[in, out] PeiServices     - An indirect pointer to the PEI Services Table published by the PEI Foundation.
+  @param[in, out] This            - Interface pointer that implements the particular SSA_BIOS_SERVICES_PPI instance.
+  @param[in]      Socket          - Zero based CPU socket number.
+  @param[in]      Controller      - Zero based controller number.
+  @param[in]      Index           - Additional index to locate the register.
+  @param[in]      BaseAddressType - Value that indicates the type of base address to be retrieved.
+  @param[in]      BaseAddress     - Where to write the base address
+
+  @retval Success or error code.
+
+**/
+static
+SSA_STATUS
+GetBaseAddress (
+  EFI_PEI_SERVICES      **PeiServices,
+  SSA_BIOS_SERVICES_PPI *This,
+  UINT8                 Socket,
+  UINT8                 Controller,
+  UINT8                 Index,
+  BASE_ADDR_TYPE        BaseAddressType,
+  EFI_PHYSICAL_ADDRESS  *BaseAddress
+  )
+{
+  MrcParameters *MrcData;
+
+  MrcData = (MrcParameters *) This->SsaMemoryConfig.MrcData;
+  switch (BaseAddressType) {
+    case MCH_BAR:
+      *BaseAddress = IsControllerPresent (MrcData, Socket, Controller) ?
+        MrcData->SysIn.Inputs.MchBarBaseAddress : 0;
+      return (Success);
+    default:
+      break;
+  }
+  return (UnsupportedValue);
+}
+
+/**
+
+@brief
+  Function used to dynamically allocate memory.
+
+  @param[in, out] PeiServices - An indirect pointer to the PEI Services Table published by the PEI Foundation.
+  @param[in, out] This        - Interface pointer that implements the particular SSA_BIOS_SERVICES_PPI instance.
+  @param[in]      Size        - Amount of memory in bytes to allocate.
+
+  @retval Returns a pointer to an allocated memory block on success or NULL on failure. 
+
+**/
+static
+VOID *
+Malloc (
+  EFI_PEI_SERVICES      **PeiServices,
+  SSA_BIOS_SERVICES_PPI *This,
+  UINT32                Size
+  )
+{
+  MrcInput       *Inputs;
+  MrcDebug       *Debug;
+  HeapBufHeader  *HeaderPtr;
+  HeapBufHeader  *NextHeaderPtr;
+  MrcParameters  *MrcData;
+
+  MrcData = (MrcParameters *) This->SsaMemoryConfig.MrcData;
+  Inputs  = &MrcData->SysIn.Inputs;
+  Debug   = &Inputs->Debug;
+
+  if ((Size == 0) || (Inputs->SsaHeapSize == 0)) {
+    return NULL;
+  }
+
+  if (Inputs->SsaHeapFlag.Bits.Init == 0) {
+    Inputs->Debug.Current         = 0;
+    Inputs->SsaHeapFlag.Bits.Init = 1;
+    InitHeap (MrcData);
+  }
+
+  //
+  // Round size up to a QWORD integral.
+  //
+  Size += sizeof (UINT64) - (Size % sizeof (UINT64));
+
+  //
+  // Check to see if request exceeds available heap size.
+  //
+  if (Size > (Inputs->SsaHeapSize - (3 * sizeof (HeapBufHeader)))) {
+    return NULL;
+  }
+
+  HeaderPtr = (HeapBufHeader *) Inputs->SsaHeapBase;
+
+  //
+  // Walk the heap looking for an available buffer.
+  //
+  while ((HeaderPtr->BufFlags.Bits.Occupied > 0) || (HeaderPtr->BufLimit < Size)) {
+    HeaderPtr = (HeapBufHeader *) (HeaderPtr->BufBase + HeaderPtr->BufLimit);
+  }
+
+  //
+  // Check for the end of heap space.
+  //
+  if (HeaderPtr->BufFlags.Bits.HeapEnd > 0) {
+    return NULL;
+  }
+
+  //
+  // Lock memory for the buffer.
+  //
+  HeaderPtr->BufFlags.Bits.Occupied = 1;
+
+  //
+  // Initialize the current size and next header if required.
+  //
+  if ((HeaderPtr->BufLimit - Size) > sizeof (HeapBufHeader)) {
+    NextHeaderPtr                = (HeapBufHeader *) (HeaderPtr->BufBase + Size);
+    NextHeaderPtr->BufBase       = (UINT8 *) NextHeaderPtr + sizeof (HeapBufHeader);
+    NextHeaderPtr->BufLimit      = HeaderPtr->BufLimit - Size - sizeof (HeapBufHeader);
+    NextHeaderPtr->BufFlags.Data = 0;
+    HeaderPtr->BufLimit          = Size;
+  }
+
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "SSA malloc. Base = %Xh, Size = %u\n", HeaderPtr->BufBase, Size);
+  //
+  // Return the current base.
+  //
+  return HeaderPtr->BufBase;
+}
+
+/**
+
+@brief
+  Function used to release memory allocated using Malloc.
+
+  @param[in, out] PeiServices - An indirect pointer to the PEI Services Table published by the PEI Foundation.
+  @param[in, out] This        - Interface pointer that implements the particular SSA_BIOS_SERVICES_PPI instance.
+  @param[in]      Buffer      - The buffer to return to the free pool.
+
+  @retval Nothing. 
+
+**/
+static
+VOID
+Free (
+  EFI_PEI_SERVICES      **PeiServices,
+  SSA_BIOS_SERVICES_PPI *This,
+  VOID                  *Buffer
+  )
+{
+  const MrcInput *Inputs;
+  const MrcDebug *Debug;
+  HeapBufHeader  *HeaderPtr;
+  HeapBufHeader  *TempPtr;
+  MrcParameters  *MrcData;
+
+  MrcData = (MrcParameters *) This->SsaMemoryConfig.MrcData;
+  Inputs  = &MrcData->SysIn.Inputs;
+  Debug   = &Inputs->Debug;
+  if (Inputs->SsaHeapSize > 0) {
+    //
+    // Initialize a pointer to the given buffer header.
+    //
+    HeaderPtr = (HeapBufHeader *) ((UINT8 *) Buffer - sizeof (HeapBufHeader));
+
+    //
+    // Validate the given pointer before proceeding.
+    //
+    if (HeaderPtr->BufBase == Buffer) {
+      //
+      // Free the given buffer.
+      //
+      HeaderPtr->BufFlags.Bits.Occupied = 0;
+
+      //
+      // Initialize the root header.
+      //
+      HeaderPtr = (HeapBufHeader *) Inputs->SsaHeapBase;
+
+      //
+      // Walk the heap looking for holes to merge.
+      //
+      do {
+        //
+        // Find the next hole.
+        //
+        while (HeaderPtr->BufFlags.Bits.Occupied > 0) {
+          HeaderPtr = (HeapBufHeader *) (HeaderPtr->BufBase + HeaderPtr->BufLimit);
+        }
+
+        //
+        // Check for the end of heap space.
+        //
+        if (HeaderPtr->BufFlags.Bits.HeapEnd > 0) {
+          break;
+        }
+
+        //
+        // Look for adjacent holes to merge.
+        //
+        TempPtr = (HeapBufHeader *) (HeaderPtr->BufBase + HeaderPtr->BufLimit);
+        while ((TempPtr->BufFlags.Bits.Occupied == 0) && (TempPtr->BufFlags.Bits.HeapEnd == 0)) {
+          //
+          // Add this buffer to the current limit and move to the next buffer.
+          //
+          HeaderPtr->BufLimit += TempPtr->BufLimit + sizeof (HeapBufHeader);
+          TempPtr = (HeapBufHeader *) (TempPtr->BufBase + TempPtr->BufLimit);
+        }
+        //
+        // Move to the next buffer.
+        //
+        HeaderPtr = (HeapBufHeader *) (HeaderPtr->BufBase + HeaderPtr->BufLimit);
+
+      } while (HeaderPtr->BufFlags.Bits.HeapEnd == 0);
+      MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "SSA free. Base = %Xh\n", Buffer);
+    }
+  }
+  return;
+}
+
+/**
+
+@brief
+  Function used to output debug messages to the output logging device.
+
+  @param[in, out] PeiServices  - An indirect pointer to the PEI Services Table published by the PEI Foundation.
+  @param[in, out] This         - Interface pointer that implements the particular SSA_BIOS_SERVICES_PPI instance.
+  @param[in]      PrintLevel   - The severity level of the string.
+  @param[in]      FormatString - The reduced set of printf style format specifiers.
+                  %[flags][width]type
+                  [flags] '-' left align
+                  [flags] '+' prefix with sign (+ or -)
+                  [flags] '0' zero pad numbers
+                  [flags] ' ' prefix black in front of postive numbers
+                  [width] non negative decimal integer that specifies the width to print a value.
+                  [width] '*' get the width from a int argument on the stack.
+                  type    'd'|'i' signed decimal integer
+                  type    'u' unsigned integer
+                  type    'x'|'X' hexidecimal using "ABCDEF"
+                  type    'c' print character
+                  type    'p' print a pointer to void
+                  type    's' print a null terminated string
+  @param[in]      ...          - Variable list of output values.
+
+  @retval Nothing. 
+
+**/
+static
+VOID
+SsaDebugPrint (
+  EFI_PEI_SERVICES      **PeiServices,
+  SSA_BIOS_SERVICES_PPI *This,
+  PRINT_LEVEL           PrintLevel,
+  UINT8                 *FormatString,
+  ...
+  )
+{
+#ifdef MRC_DEBUG_PRINT
+  MrcVaList Marker;
+  char      Buffer[MAX_STRING_LENGTH];
+
+  if (FormatString != NULL) {
+    VA_START (Marker, FormatString);
+    if (StringFormatter (FormatString, Marker, sizeof (Buffer), Buffer) > 0) {
+      DEBUG ((PrintLevel, Buffer));
+    }
+  }
+#endif
+
+  return;
+}
+
+/**
+
+@brief
+  Returns the platform's memory voltage (VDD).
+
+  @param[in, out] PeiServices - An indirect pointer to the PEI Services Table published by the PEI Foundation.
+  @param[in, out] This        - Interface pointer that implements the particular SSA_BIOS_SERVICES_PPI instance.
+  @param[out]     Voltage     - Where the platform's memory voltage (in mV) will be written.
+
+  @retval Success or failure code.
+
+**/
+static
+SSA_STATUS
+GetMemVoltage (
+  EFI_PEI_SERVICES      **PeiServices,
+  SSA_BIOS_SERVICES_PPI *This,
+  UINT32                *Voltage
+  )
+{
+  MrcParameters *MrcData;
+
+  MrcData  = (MrcParameters *) This->SsaMemoryConfig.MrcData;
+  *Voltage = MrcData->SysOut.Outputs.VddVoltage[MrcData->SysIn.Inputs.MemoryProfile];
+  return (Success);
+}
+
+/**
+
+@brief
+  Sets the platform's memory voltage (VDD).
+
+  @param[in, out] PeiServices - An indirect pointer to the PEI Services Table published by the PEI Foundation.
+  @param[in, out] This        - Interface pointer that implements the particular SSA_BIOS_SERVICES_PPI instance.
+  @param[in]      Voltage     - The requested platform's memory voltage (in mV).
+
+  @retval Success or failure code.
+
+**/
+static
+SSA_STATUS
+SetMemVoltage (
+  EFI_PEI_SERVICES      **PeiServices,
+  SSA_BIOS_SERVICES_PPI *This,
+  UINT32                *Voltage
+  )
+{
+  UINT32 VddSettleWaitTime;
+  MrcParameters *MrcData;
+
+  MrcData = (MrcParameters *) This->SsaMemoryConfig.MrcData;
+  VddSettleWaitTime = MIN (MrcData->SysIn.Inputs.VddSettleWaitTime, 200);
+  MrcOemVDDVoltageCheckAndSwitch (MrcData, *Voltage, &VddSettleWaitTime);
+  MrcWait (MrcData, VddSettleWaitTime * HPET_1US);
+  MrcData->SysOut.Outputs.VddVoltage[MrcData->SysIn.Inputs.MemoryProfile] = *Voltage;
+  return (Success);
+}
+
+/**
+
+@brief
+  Returns the temperature of the specified DIMM in whole degree Celsius.
+
+  @param[in, out] PeiServices - An indirect pointer to the PEI Services Table published by the PEI Foundation.
+  @param[in, out] This        - Interface pointer that implements the particular SSA_BIOS_SERVICES_PPI instance.
+  @param[in]      Socket      - Zero based CPU socket number.
+  @param[in]      Controller  - Zero based controller number.
+  @param[in]      Channel     - Zero based channel number.
+  @param[in]      Dimm        - Zero based DIMM number.
+  @param[out]     Temperature - Where the DIMM's temperature in whole degree Celsius will be written.
+
+  @retval Success or failure code.
+
+**/
+static
+SSA_STATUS
+GetMemTemp (
+  EFI_PEI_SERVICES      **PeiServices,
+  SSA_BIOS_SERVICES_PPI *This,
+  UINT8                 Socket,
+  UINT8                 Controller,
+  UINT8                 Channel,
+  UINT8                 Dimm,
+  INT32                 *Temperature
+  )
+{
+  const MrcParameters *MrcData;
+  const MrcInput      *Inputs;
+  UINT16              Value;
+  UINT8               Address;
+  union {
+    struct {
+      UINT16 Fraction : 4;
+      UINT16 Whole    : 8;
+      UINT16 Sign     : 1;
+      UINT16 Low      : 1;
+      UINT16 High     : 1;
+      UINT16 Tcrit    : 1;
+    } Bit;
+    UINT16            Data;
+    UINT8             Data8[2];
+  } TsRegisterSet;
+
+  MrcData = (MrcParameters *) This->SsaMemoryConfig.MrcData;
+  Inputs  = &MrcData->SysIn.Inputs;
+  if (IsDimmPresent (MrcData, Socket, Controller, Channel, Dimm)) {
+    Address = SPD_SENSOR_BASE_ADDRESS | (Inputs->Controller[Controller].Channel[Channel].Dimm[Dimm].SpdAddress & 0xF);
+    if (mrcSuccess == MrcOemSmbusRead16 (Inputs->SmbusBaseAddress, Address, SPD_SENSOR_TEMPERATURE_OFFSET, &Value)) {
+      // Value read is in big endian format, convert it to little endian.
+      TsRegisterSet.Data = ((Value << 8) & 0xFF00) | ((Value >> 8) & 0xFF);
+      *Temperature       = (TsRegisterSet.Bit.Sign) ? ((-1) * TsRegisterSet.Bit.Whole) : TsRegisterSet.Bit.Whole;
+      // SsaDebugPrint (PeiServices, This, SSA_D_INFO, "SSA GetMemTemp %u/%u/%u/%u %04Xh %04Xh %d\n", Socket, Controller, Channel, Dimm, Address, TsRegisterSet.Data, *Temperature);
+      return (Success);
+    }
+  }
+  *Temperature = 0;
+  return (NotAvailable);
+}
+
+/**
+
+@brief
+  Sets the rank's mode register.
+
+  @param[in, out] PeiServices - An indirect pointer to the PEI Services Table published by the PEI Foundation.
+  @param[in, out] This        - Interface pointer that implements the particular SSA_BIOS_SERVICES_PPI instance.
+  @param[in]      Socket      - Zero based CPU socket number.
+  @param[in]      Controller  - Zero based controller number.
+  @param[in]      Channel     - Zero based channel number.
+  @param[in]      Dimm        - Zero based DIMM number.
+  @param[in]      Rank        - Zero based rank number in the DIMM.
+  @param[in]      Address     - Zero based mode register number.
+  @param[in]      Data        - Value to write to the register.
+
+  @retval Success or failure code.
+
+**/
+static
+SSA_STATUS
+WriteMrs (
+  EFI_PEI_SERVICES      **PeiServices,
+  SSA_BIOS_SERVICES_PPI *This,
+  UINT8                 Socket,
+  UINT8                 Controller,
+  UINT8                 Channel,
+  UINT8                 Dimm,
+  UINT8                 Rank,
+  UINT8                 Address,
+  UINT16                Data
+  )
+{
+  MrcParameters *MrcData;
+  U8            LogicalRank;
+
+  MrcData = (MrcParameters *) This->SsaMemoryConfig.MrcData;
+  if (IsRankPresent (MrcData, Socket, Controller, Channel, Dimm, Rank)) {
+    LogicalRank = (Dimm * MAX_RANK_IN_DIMM) + Rank;
+#ifdef ULT_FLAG
+    if (MrcData->SysOut.Outputs.DdrType == MRC_DDR_TYPE_LPDDR3) {
+      MrcIssueMrw (MrcData, Channel, LogicalRank, Address, Data, FALSE, FALSE);
+    } else
+#endif
+    {
+      MrcWriteMRSAll (MrcData, Channel, MRC_BIT0 << LogicalRank, Address, &Data);
+    }
+    return (Success);
+  }
+  return (LogicalRankNotSupported);
+}
+
+/**
+
+@brief
+  Restores the rank's mode register using the default value that the MRC has stored away.
+
+  @param[in, out] PeiServices - An indirect pointer to the PEI Services Table published by the PEI Foundation.
+  @param[in, out] This        - Interface pointer that implements the particular SSA_BIOS_SERVICES_PPI instance.
+  @param[in]      Socket      - Zero based CPU socket number.
+  @param[in]      Controller  - Zero based controller number.
+  @param[in]      Channel     - Zero based channel number.
+  @param[in]      Dimm        - Zero based DIMM number.
+  @param[in]      Rank        - Zero based rank number in the DIMM.
+  @param[in]      Address     - Zero based mode register number.
+
+  @retval Success or failure code.
+
+**/
+static
+SSA_STATUS
+RestoreMrs (
+  EFI_PEI_SERVICES      **PeiServices,
+  SSA_BIOS_SERVICES_PPI *This,
+  UINT8                 Socket,
+  UINT8                 Controller,
+  UINT8                 Channel,
+  UINT8                 Dimm,
+  UINT8                 Rank,
+  UINT8                 Address
+  )
+{
+  MrcParameters *MrcData;
+  UINT16        Data;
+
+  MrcData = (MrcParameters *) This->SsaMemoryConfig.MrcData;
+  Data    = MrcData->SysOut.Outputs.Controller[Controller].Channel[Channel].Dimm[Dimm].Rank[Rank].MR[Address];
+  return (WriteMrs (PeiServices, This, Socket, Controller, Channel, Dimm, Rank, Address, Data));
+}
+
+/**
+
+@brief
+  Get the rank's mode register.
+
+  @param[in, out] PeiServices - An indirect pointer to the PEI Services Table published by the PEI Foundation.
+  @param[in, out] This        - Interface pointer that implements the particular SSA_BIOS_SERVICES_PPI instance.
+  @param[in]      Socket      - Zero based CPU socket number.
+  @param[in]      Controller  - Zero based controller number.
+  @param[in]      Channel     - Zero based channel number.
+  @param[in]      Dimm        - Zero based DIMM number.
+  @param[in]      Rank        - Zero based rank number in the DIMM.
+  @param[in]      Address     - Zero based mode register number.
+  @param[out]     Data        - Value read from the register.
+
+  @retval Success or failure code.
+
+**/
+static
+SSA_STATUS
+ReadMrs (
+  EFI_PEI_SERVICES      **PeiServices,
+  SSA_BIOS_SERVICES_PPI *This,
+  UINT8                 Socket,
+  UINT8                 Controller,
+  UINT8                 Channel,
+  UINT8                 Dimm,
+  UINT8                 Rank,
+  UINT8                 Address,
+  UINT16                *Data
+  )
+{
+  MrcParameters *MrcData;
+  SSA_STATUS    Status;
+
+  MrcData = (MrcParameters *) This->SsaMemoryConfig.MrcData;
+  if (IsRankPresent (MrcData, Socket, Controller, Channel, Dimm, Rank)) {
+    *Data  = MrcData->SysOut.Outputs.Controller[Controller].Channel[Channel].Dimm[Dimm].Rank[Rank].MR[Address];
+    Status = Success;
+  } else {
+    *Data  = 0;
+    Status = LogicalRankNotSupported;
+  }
+  return (Status);
+}
+
+/**
+
+@brief
+  Returns the DIMM number according to the rank number.
+
+  @param[in, out] PeiServices - An indirect pointer to the PEI Services Table published by the PEI Foundation.
+  @param[in, out] This        - Interface pointer that implements the particular SSA_BIOS_SERVICES_PPI instance.
+  @param[in]      Socket      - Zero based CPU socket number.
+  @param[in]      Controller  - Zero based controller number.
+  @param[in]      Channel     - Zero based channel number.
+  @param[in]      Rank        - Zero based rank number in the channel.
+
+  @retval Returns the zero based DIMM index or FFh on error.
+
+**/
+static
+UINT8
+GetDimmFromLogicalRank (
+  EFI_PEI_SERVICES      **PeiServices,
+  SSA_BIOS_SERVICES_PPI *This,
+  UINT8                 Socket,
+  UINT8                 Controller,
+  UINT8                 Channel,
+  UINT8                 Rank
+  )
+{
+  MrcParameters *MrcData;
+
+  MrcData = (MrcParameters *) This->SsaMemoryConfig.MrcData;
+  if (IsChannelPresent (MrcData, Socket, Controller, Channel) && (Rank < MAX_RANK_IN_CHANNEL)) {
+    return (Rank / MAX_RANK_IN_DIMM);
+  }
+  return ((UINT8) ~0);
+}
+
+/**
+
+@brief
+  Gets DIMM information. 
+
+  @param[in, out] PeiServices    - An indirect pointer to the PEI Services Table published by the PEI Foundation.
+  @param[in, out] This           - Interface pointer that implements the particular SSA_BIOS_SERVICES_PPI instance.
+  @param[in]      Socket         - Zero based CPU socket number.
+  @param[in]      Controller     - Zero based controller number.
+  @param[in]      Channel        - Zero based channel number.
+  @param[in]      Dimm           - Zero based DIMM number.
+  @param[in, out] DimmInfoBuffer - Location to store DIMM information.
+
+  @retval Returns DIMM information when a good status code is returned.
+
+**/
+static
+SSA_STATUS
+GetDimmInfo (
+  EFI_PEI_SERVICES      **PeiServices,
+  SSA_BIOS_SERVICES_PPI *This,
+  UINT8                 Socket,
+  UINT8                 Controller,
+  UINT8                 Channel,
+  UINT8                 Dimm,
+  MrcDimmInfo           *DimmInfoBuffer
+  )
+{
+  MrcDimmOut  *DimmOut;
+  MrcParameters *MrcData;
+
+  MrcData = (MrcParameters *) This->SsaMemoryConfig.MrcData;
+  if (IsDimmPresent (MrcData, Socket, Controller, Channel, Dimm)) {
+    DimmOut = &MrcData->SysOut.Outputs.Controller[Controller].Channel[Channel].Dimm[Dimm];
+    DimmInfoBuffer->EccSupport   = MrcData->SysOut.Outputs.EccSupport;
+    DimmInfoBuffer->DimmCapacity = DimmOut->DimmCapacity;
+    DimmInfoBuffer->RowSize      = DimmOut->RowSize;
+    DimmInfoBuffer->ColumnSize   = DimmOut->ColumnSize;
+    CopyMem (&DimmInfoBuffer->SerialNumber,
+      &MrcData->SysIn.Inputs.Controller[Controller].Channel[Channel].Dimm[Dimm].Spd.Ddr3.ModuleId,
+      sizeof (SPD_UNIQUE_MODULE_ID));
+    return (Success);
+  } else {
+    SetMem (DimmInfoBuffer, 0, sizeof (MrcDimmInfo));
+    return (NotAvailable);
+  }
+}
+
+/**
+
+@brief
+  Returns the number of ranks in a specific DIMM on a given socket/controller.
+
+  @param[in, out] PeiServices - An indirect pointer to the PEI Services Table published by the PEI Foundation.
+  @param[in, out] This        - Interface pointer that implements the particular SSA_BIOS_SERVICES_PPI instance.
+  @param[in]      Socket      - Zero based CPU socket number.
+  @param[in]      Controller  - Zero based controller number.
+  @param[in]      Channel     - Zero based channel number.
+  @param[in]      Dimm        - Zero based DIMM number.
+
+  @retval Returns the number of ranks in a specific DIMM on a given socket/controller.
+
+**/
+static
+UINT8
+GetRankInDimm (
+  EFI_PEI_SERVICES      **PeiServices,
+  SSA_BIOS_SERVICES_PPI *This,
+  UINT8                 Socket,
+  UINT8                 Controller,
+  UINT8                 Channel,
+  UINT8                 Dimm
+  )
+{
+  MrcParameters *MrcData;
+
+  MrcData = (MrcParameters *) This->SsaMemoryConfig.MrcData;
+  return ((IsDimmPresent (MrcData, Socket, Controller, Channel, Dimm)) ?
+    MrcData->SysOut.Outputs.Controller[Controller].Channel[Channel].Dimm[Dimm].RankInDIMM : 0);
+}
+
+/**
+
+@brief
+  Returns the bitmask of valid ranks on a given channel.
+
+  @param[in, out] PeiServices - An indirect pointer to the PEI Services Table published by the PEI Foundation.
+  @param[in, out] This        - Interface pointer that implements the particular SSA_BIOS_SERVICES_PPI instance.
+  @param[in]      Socket      - Zero based CPU socket number.
+  @param[in]      Controller  - Zero based controller number.
+  @param[in]      Channel     - Zero based channel number.
+
+  @retval Returns the bitmask of valid ranks on a given channel.
+
+**/
+static
+UINT8
+GetLogicalRankBitMask (
+  EFI_PEI_SERVICES      **PeiServices,
+  SSA_BIOS_SERVICES_PPI *This,
+  UINT8                 Socket,
+  UINT8                 Controller,
+  UINT8                 Channel
+  )
+{
+  MrcParameters *MrcData;
+
+  MrcData = (MrcParameters *) This->SsaMemoryConfig.MrcData;
+  return ((IsChannelPresent (MrcData, Socket, Controller, Channel)) ?
+    MrcData->SysOut.Outputs.Controller[Controller].Channel[Channel].ValidRankBitMask : 0);
+}
+
+/**
+
+@brief
+  Returns the channel bit mask of the populated channels.
+
+  @param[in, out] PeiServices - An indirect pointer to the PEI Services Table published by the PEI Foundation.
+  @param[in, out] This        - Interface pointer that implements the particular SSA_BIOS_SERVICES_PPI instance.
+  @param[in]      Socket      - Zero based CPU socket number.
+  @param[in]      Controller  - Zero based controller number.
+
+  @retval Returns the channel bit mask of the populated channels.
+
+**/
+static
+UINT8
+GetChannelBitMask (
+  EFI_PEI_SERVICES      **PeiServices,
+  SSA_BIOS_SERVICES_PPI *This,
+  UINT8                 Socket,
+  UINT8                 Controller
+  )
+{
+  UINT8 Channel;
+  UINT8 ChannelMask;
+  MrcParameters *MrcData;
+
+  MrcData = (MrcParameters *) This->SsaMemoryConfig.MrcData;
+  ChannelMask = 0;
+  for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+    if (IsChannelPresent (MrcData, Socket, Controller, Channel)) {
+      ChannelMask |= (MRC_BIT0 << Channel);
+    }
+  }
+  return (ChannelMask);
+}
+
+/**
+
+@brief
+  Gets information about the system.
+
+  @param[in, out] PeiServices - An indirect pointer to the PEI Services Table published by the PEI Foundation.
+  @param[in, out] This        - Interface pointer that implements the particular SSA_BIOS_SERVICES_PPI instance.
+  @param[in, out] SystemInfo  - Pointer to buffer to be filled with system information.
+
+  @retval Returns information about the system. 
+
+**/
+static
+SSA_STATUS
+GetSystemInfo (
+  EFI_PEI_SERVICES      **PeiServices,
+  SSA_BIOS_SERVICES_PPI *This,
+  MrcSystemInfo         *SystemInfoBuffer
+  )
+{
+  SystemInfoBuffer->MaxNumberSockets      = MAX_CPU_SOCKETS;
+  SystemInfoBuffer->MaxNumberControllers  = MAX_CONTROLLERS;
+  SystemInfoBuffer->MaxNumberChannels     = MAX_CHANNEL;
+  SystemInfoBuffer->MaxNumberLogicalRanks = MAX_RANK_IN_CHANNEL;
+  SystemInfoBuffer->SocketsBitMask        = ((UINT32) (~0)) >> (32 - MAX_CPU_SOCKETS);
+  return (Success);
+}
+
+/**
+
+@brief
+  Get a bit mask representing the present and enabled memory controllers in a CPU socket.
+
+  @param[in, out] PeiServices - An indirect pointer to the PEI Services Table published by the PEI Foundation.
+  @param[in, out] This        - Interface pointer that implements the particular SSA_BIOS_SERVICES_PPI instance.
+  @param[in]      Socket      - Zero based CPU socket number.
+
+  @retval A bit mask representing the present and enabled memory controllers in a CPU socket.
+
+**/
+static
+UINT8
+GetControllerBitMask (
+  EFI_PEI_SERVICES      **PeiServices,
+  SSA_BIOS_SERVICES_PPI *This,
+  UINT8                 Socket
+  )
+{
+  MrcParameters *MrcData;
+
+  MrcData = (MrcParameters *) This->SsaMemoryConfig.MrcData;
+  return (IsSocketPresent (MrcData, Socket) ? (((UINT8) (~0)) >> (8 - MAX_CONTROLLERS)) : 0);
+}
+
+/**
+
+@brief
+  Function used to reset a DIMM.
+
+  @param[in, out] PeiServices - An indirect pointer to the PEI Services Table published by the PEI Foundation.
+  @param[in, out] This        - Interface pointer that implements the particular SSA_BIOS_SERVICES_PPI instance.
+  @param[in]      Socket      - Zero based CPU socket number.
+  @param[in]      Controller  - Zero based controller number.
+
+  @retval Nothing.
+
+**/
+static
+VOID
+JedecReset (
+  EFI_PEI_SERVICES      **PeiServices,
+  SSA_BIOS_SERVICES_PPI *This,
+  UINT8                 Socket,
+  UINT8                 Controller
+  )
+{
+  MrcParameters *MrcData;
+
+  MrcData = (MrcParameters *) This->SsaMemoryConfig.MrcData;
+  if (IsControllerPresent (MrcData, Socket, Controller)) {
+    MrcResetSequence (MrcData);
+  }
+  return;
+}
+
+/**
+
+@brief
+  Function returns the low side range of a margin parameter.
+
+  @param[in] IoLevel     - Id of the I/O level to access.
+  @param[in] MarginGroup - Id of the margin group. Can be RxDq, TxDq, RxVref or TxVref.
+
+  @retval Function returns the low side range of a margin parameter.
+
+**/
+static
+INT16
+GetMarginParamMin (
+  GSM_LT IoLevel,
+  GSM_GT MarginGroup
+  )
+{
+  INT16 Value;
+
+  switch (MarginGroup) {
+      case RxDqsDelay:
+      case TxDqsDelay:
+        Value = (-31);
+        break;
+
+      case RxVref:
+      case TxVref:
+        Value = (-54);
+        break;
+
+      default:
+        Value = INT16_MIN;
+        break;
+  }
+  return (Value);
+}
+
+/**
+
+@brief
+  Function returns the high side range of a margin parameter.
+
+  @param[in] IoLevel     - Id of the I/O level to access.
+  @param[in] MarginGroup - Id of the margin group. Can be RxDq, TxDq, RxVref or TxVref.
+
+  @retval Function returns the high side range of a margin parameter.
+
+**/
+static
+INT16
+GetMarginParamMax (
+  GSM_LT IoLevel,
+  GSM_GT MarginGroup
+  )
+{
+  INT16 Value;
+
+  switch (MarginGroup) {
+    case RxDqsDelay:
+    case TxDqsDelay:
+      Value = 31;
+      break;
+
+    case RxVref:
+    case TxVref:
+      Value = 54;
+      break;
+      
+    default:
+      Value = INT16_MAX;
+      break;
+  }
+  return (Value);
+}
+
+/**
+
+@brief
+  Function returns the minimum and maximum offsets that can be applied to the margin group
+  and the time delay in micro seconds for the new value to take effect.
+
+  @param[in, out] PeiServices - An indirect pointer to the PEI Services Table published by the PEI Foundation.
+  @param[in, out] This        - Interface pointer that implements the particular SSA_BIOS_SERVICES_PPI instance.
+  @param[in]      Socket      - Zero based CPU socket number.
+  @param[in]      Controller  - Zero based controller number.
+  @param[in]      Channel     - Zero based channel number.
+  @param[in]      LogicRank   - Zero based rank number in the channel.
+  @param[in]      IoLevel     - Id of the I/O level to access.
+  @param[in]      MarginGroup - Id of the margin group.
+  @param[in]      MinOffset   - Minimum offset supported by the given margin group.
+  @param[in]      MaxOffset   - Maximum offset supported by the given margin group.
+  @param[out]     Delay       - Wait time in micro-seconds that is required for the new setting to take effect.
+
+  @retval Success or error code.
+
+**/
+static
+SSA_STATUS
+GetMarginParamLimits (
+  EFI_PEI_SERVICES      **PeiServices,
+  SSA_BIOS_SERVICES_PPI *This,
+  UINT8                 Socket,
+  UINT8                 Controller,
+  UINT8                 Channel,
+  UINT8                 LogicRank,
+  GSM_LT                IoLevel,
+  GSM_GT                MarginGroup,
+  INT16                 *MinOffset,
+  INT16                 *MaxOffset,
+  UINT16                *Delay
+  )
+{
+  MrcParameters *MrcData;
+
+  MrcData = (MrcParameters *) This->SsaMemoryConfig.MrcData;
+  if (IsRankPresent (MrcData, Socket, Controller, Channel, LogicRank % MAX_RANK_IN_DIMM, LogicRank)) {
+    *MinOffset = GetMarginParamMin (IoLevel, MarginGroup);
+    *MaxOffset = GetMarginParamMax (IoLevel, MarginGroup);
+  *Delay = 0;
+  }
+  return (Success);
+}
+
+/**
+
+@brief
+  Function used to adjust a margin parameter.It will add an offset from the training value
+  (if memory has been trained) or from the default value (if memory has not been trained yet).
+
+  @param[in, out] PeiServices - An indirect pointer to the PEI Services Table published by the PEI Foundation.
+  @param[in, out] This        - Interface pointer that implements the particular SSA_BIOS_SERVICES_PPI instance.
+  @param[in]      Socket      - Zero based CPU socket number.
+  @param[in]      Controller  - Zero based controller number.
+  @param[in]      Channel     - Zero based channel number.
+  @param[in]      LogicRank   - Zero based rank number in the channel.
+  @param[in]      IoLevel     - Id of the I/O level to access.
+  @param[in]      MarginGroup - Id of the margin group. Can be RcvEna(0), RdT(1), WrT(2), WrDqsT(3), RdV(4) or WrV(5).
+  @param[in]      Offset      - Offset to be applied to the Margin parameter from the nominal.
+
+  @retval Nothing.
+
+**/
+static
+SSA_STATUS
+OffsetMarginParam (
+  EFI_PEI_SERVICES      **PeiServices,
+  SSA_BIOS_SERVICES_PPI *This,
+  UINT8                 Socket,
+  UINT8                 Controller,
+  UINT8                 Channel,
+  UINT8                 LogicRank,
+  GSM_LT                IoLevel,
+  GSM_GT                MarginGroup,
+  UINT16                Offset
+  )
+{
+  UINT8 Byte;
+  UINT8 ByteEnd;
+  MrcParameters *MrcData;
+
+  MrcData = (MrcParameters *) This->SsaMemoryConfig.MrcData;
+  if (IsRankPresent (MrcData, Socket, Controller, Channel, LogicRank % MAX_RANK_IN_DIMM, LogicRank)) {
+    if (MarginGroup < WrLevel) {
+      ByteEnd = MrcData->SysOut.Outputs.SdramCount;
+      for (Byte = 0; Byte < ByteEnd; Byte++) {
+        if ((MarginGroup != WrV) || (Byte == 0)) {
+          ChangeMargin(
+            MrcData,
+            MarginGroup,          // param
+            (S32) Offset,         // value0
+            0,                    // value1
+            0,                    // EnMultiCast
+            Channel,              // ch
+            LogicRank,            // rank
+            Byte,                 // byte
+            0,                    // bit
+            0,                    // UpdateMrcData
+            1,                    // SkipWait
+            MrcRegFileStart
+            );
+        } // if
+      } // for
+    } else {
+      return (UnsupportedValue);
+    } // if
+  } else {
+    return (LogicalRankNotSupported);
+  } // if
+  return (Success);
+}
+
+/**
+
+@brief
+  Function used to write to the Write Data Buffer (WDB).
+
+  @param[in, out] PeiServices         - An indirect pointer to the PEI Services Table published by the PEI Foundation.
+  @param[in, out] This                - Interface pointer that implements the particular SSA_BIOS_SERVICES_PPI instance.
+  @param[in]      Socket              - Zero based CPU socket number.
+  @param[in]      Controller          - Zero based controller number.
+  @param[in]      Channel             - Zero based channel number.
+  @param[in]      Pattern             - Buffer containing the WDB pattern.
+  @param[in]      CachelineCount      - Size of the buffer pattern in term of the count of cachelines.
+  @param[in]      StartCachelineIndex - Start offset on the WDB.
+
+  @retval Nothing.
+
+**/
+static
+VOID
+SetWdbPattern (
+  EFI_PEI_SERVICES      **PeiServices,
+  SSA_BIOS_SERVICES_PPI *This,
+  UINT8                 Socket,
+  UINT8                 Controller,
+  UINT8                 Channel,
+  UINT64                *Pattern,
+  UINT8                 CachelineCount,
+  UINT8                 StartCachelineIndex
+  )
+{
+  UINT64_STRUCT *Pointer;
+  MCHBAR_CH0_CR_QCLK_LDAT_PDAT_STRUCT CrQclkLdatPdat;
+  MCHBAR_CH0_CR_QCLK_LDAT_SDAT_STRUCT CrQclkLdatSdat;
+  UINT32 CrQclkLdatDatain0Offset;
+  UINT32 CrQclkLdatDatain1Offset;
+  UINT32 CrQclkLdatSdatOffset;
+  UINT32 CrQclkLdatPdatOffset;
+  UINT8 PatternCachelineIdx;
+  UINT8 Chunk;
+  MrcParameters *MrcData;
+
+  MrcData = (MrcParameters *) This->SsaMemoryConfig.MrcData;
+  if (IsChannelPresent (MrcData, Socket, Controller, Channel)) {
+    CrQclkLdatDatain0Offset = MCHBAR_CH0_CR_QCLK_LDAT_DATAIN_0_REG +
+      ((MCHBAR_CH1_CR_QCLK_LDAT_DATAIN_0_REG - MCHBAR_CH0_CR_QCLK_LDAT_DATAIN_0_REG) * Channel);
+    CrQclkLdatDatain1Offset = MCHBAR_CH0_CR_QCLK_LDAT_DATAIN_1_REG +
+      ((MCHBAR_CH1_CR_QCLK_LDAT_DATAIN_1_REG - MCHBAR_CH0_CR_QCLK_LDAT_DATAIN_1_REG) * Channel);
+    CrQclkLdatSdatOffset = MCHBAR_CH0_CR_QCLK_LDAT_SDAT_REG +
+      ((MCHBAR_CH1_CR_QCLK_LDAT_SDAT_REG - MCHBAR_CH0_CR_QCLK_LDAT_SDAT_REG) * Channel);
+    CrQclkLdatPdatOffset = MCHBAR_CH0_CR_QCLK_LDAT_PDAT_REG +
+      ((MCHBAR_CH1_CR_QCLK_LDAT_PDAT_REG - MCHBAR_CH0_CR_QCLK_LDAT_PDAT_REG) * Channel);
+
+    CrQclkLdatSdat.Data = 0;
+    CrQclkLdatSdat.Bits.MODE = 1;
+
+    CrQclkLdatPdat.Data = 0;
+    CrQclkLdatPdat.Bits.CMDB = MRC_BIT3;
+
+    for (PatternCachelineIdx = 0; PatternCachelineIdx < CachelineCount; PatternCachelineIdx++) {
+      Pointer = (UINT64_STRUCT *) &Pattern[PatternCachelineIdx];
+      for (Chunk = 0; Chunk < MAX_CHUNK_SIZE; Chunk++) {
+        WriteMem (PeiServices, This, RegWidth32, CrQclkLdatDatain0Offset, &Pointer[Chunk].Data32.Low);
+        WriteMem (PeiServices, This, RegWidth32, CrQclkLdatDatain1Offset, &Pointer[Chunk].Data32.High);
+
+        // Set rep = 0, don't want to replicate the data.
+        // Set banksel field to the value of the chunk you want to write the 64 bits to.
+        // Set arraysel = 0 (indicating it is the MC WDB) and mode = 'b01 in the SDAT register.
+        CrQclkLdatSdat.Bits.BANKSEL = Chunk;
+        WriteMem (PeiServices, This, RegWidth32, CrQclkLdatSdatOffset, &CrQclkLdatSdat.Data);
+
+        // Finally, write the PDAT register indicating which cacheline of the WDB you want to write to
+        // by setting fastaddr field to one of the 64 cache lines. Also set cmdb in the pdat register to 4'b1000,
+        // indicating that this is a LDAT write.
+        CrQclkLdatPdat.Bits.FASTADDR = StartCachelineIndex + PatternCachelineIdx;
+        WriteMem (PeiServices, This, RegWidth32, CrQclkLdatPdatOffset, &CrQclkLdatPdat.Data);
+      } // Chunk
+
+      // Turn off LDAT mode after writing to WDB is complete.
+      CrQclkLdatSdat.Data = 0;
+      WriteMem (PeiServices, This, RegWidth32, CrQclkLdatSdatOffset, &CrQclkLdatSdat.Data);
+    } // PatternCachelineIdx
+  }
+  return;
+}
+
+/**
+
+@brief
+  Function used to write to the CADB.
+
+  @param[in, out] PeiServices         - An indirect pointer to the PEI Services Table published by the PEI Foundation.
+  @param[in, out] This                - Interface pointer that implements the particular SSA_BIOS_SERVICES_PPI instance.
+  @param[in]      Socket              - Zero based CPU socket number.
+  @param[in]      Controller          - Zero based controller number.
+  @param[in]      Channel             - Zero based channel number.
+  @param[in]      Pattern             - Buffer containing the WDB pattern.
+  @param[in]      CachelineCount      - Size of the buffer pattern in term of the count of cachelines.
+  @param[in]      StartCachelineIndex - Start offset on the WDB.
+
+  @retval Nothing.
+
+**/
+static
+VOID
+SetCadbPattern (
+  EFI_PEI_SERVICES      **PeiServices,
+  SSA_BIOS_SERVICES_PPI *This,
+  UINT8                 Socket,
+  UINT8                 Controller,
+  UINT8                 Channel,
+  UINT64                *Pattern,
+  UINT8                 CachelineCount,
+  UINT8                 StartCachelineIndex
+  )
+{
+  UINT32 Offset;
+  MrcParameters *MrcData;
+
+  MrcData = (MrcParameters *) This->SsaMemoryConfig.MrcData;
+  if (IsChannelPresent (MrcData, Socket, Controller, Channel)) {
+    Offset = MCHBAR_CH0_CR_REUT_CH_PAT_CADB_WRITE_POINTER_REG +
+      ((MCHBAR_CH1_CR_REUT_CH_PAT_CADB_WRITE_POINTER_REG - MCHBAR_CH0_CR_REUT_CH_PAT_CADB_WRITE_POINTER_REG) * Channel);
+    MrcWriteCR (MrcData, Offset, StartCachelineIndex % MAX_CADB_ENTRIES);
+
+    CachelineCount %= MAX_CADB_ENTRIES;
+    Offset = MCHBAR_CH0_CR_REUT_CH_PAT_CADB_PROG_REG +
+      ((MCHBAR_CH1_CR_REUT_CH_PAT_CADB_PROG_REG - MCHBAR_CH0_CR_REUT_CH_PAT_CADB_PROG_REG) * Channel);
+    while (CachelineCount--) {
+      // Write Row. CADB is auto incremented after every write
+      MrcWriteCR64 (MrcData, Offset, *Pattern++);
+    }
+  }
+  return;
+}
+
+/**
+
+@brief
+  Function used to clear the lane error status registers.
+
+  @param[in, out] PeiServices  - An indirect pointer to the PEI Services Table published by the PEI Foundation.
+  @param[in, out] This         - Interface pointer that implements the particular SSA_BIOS_SERVICES_PPI instance.
+  @param[in]      Socket       - Zero based CPU socket number.
+  @param[in]      Controller   - Zero based controller number.
+  @param[in]      ChannelMask  - Each bit represents a channel to be cleared.
+
+  @retval Nothing.
+
+**/
+static
+SSA_STATUS
+ClearErrorStatus (
+  EFI_PEI_SERVICES      **PeiServices,
+  SSA_BIOS_SERVICES_PPI *This,
+  UINT8                 Socket,
+  UINT8                 Controller,
+  UINT8                 ChannelMask
+  )
+{
+  MCHBAR_CH0_CR_REUT_CH_ERR_DATA_STATUS_STRUCT CrReutChErrDataStatus;
+  MrcParameters *MrcData;
+  UINT8         Channel;
+
+  MrcData = (MrcParameters *) This->SsaMemoryConfig.MrcData;
+  if (IsControllerPresent (MrcData, Socket, Controller)) {
+    if (ChannelMask > 0) {
+      Channel = 0;
+      while (ChannelMask) {
+        if ((ChannelMask & 1) && IsChannelPresent (MrcData, Socket, Controller, Channel)) {
+          CrReutChErrDataStatus.Data = 0;
+          WriteMem (
+            PeiServices,
+            This,
+            RegWidth64,
+            MCHBAR_CH0_CR_REUT_CH_ERR_DATA_STATUS_REG +
+            (Channel * (MCHBAR_CH1_CR_REUT_CH_ERR_DATA_STATUS_REG - MCHBAR_CH0_CR_REUT_CH_ERR_DATA_STATUS_REG)),
+            &CrReutChErrDataStatus.Data);
+        }
+        Channel++;
+        ChannelMask >>= 1;
+      }
+    } else {
+      return (UnsupportedValue);
+    }
+  } else {
+    return (ControllerNotSupported);
+  }
+  return (Success);
+}
+
+/**
+
+@brief
+  Function used to clear the error counter register.
+
+  @param[in, out] PeiServices  - An indirect pointer to the PEI Services Table published by the PEI Foundation.
+  @param[in, out] This         - Interface pointer that implements the particular SSA_BIOS_SERVICES_PPI instance.
+  @param[in]      Socket       - Zero based CPU socket number.
+  @param[in]      Controller   - Zero based controller number.
+  @param[in]      Channel      - Zero based channel number.
+  @param[in]      Counter      - Zero based counter number.
+
+  @retval Nothing.
+
+**/
+static
+SSA_STATUS
+ClearErrorCounter (
+  EFI_PEI_SERVICES      **PeiServices,
+  SSA_BIOS_SERVICES_PPI *This,
+  UINT8                 Socket,
+  UINT8                 Controller,
+  UINT8                 Channel,
+  UINT8                 Counter
+  )
+{
+  MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_0_STRUCT CrReutChErrCounterStatus0;
+  UINT32  Offset;
+  UINT8   Byte;
+  MrcParameters *MrcData;
+
+  MrcData = (MrcParameters *) This->SsaMemoryConfig.MrcData;
+  if (IsChannelPresent (MrcData, Socket, Controller, Channel)) {
+    Offset = MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_0_REG +
+      (Channel * (MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_0_REG - MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_0_REG));
+    CrReutChErrCounterStatus0.Data = 0;
+    for (Byte = 0; Byte < MrcData->SysOut.Outputs.SdramCount; Byte++) {
+      WriteMem (PeiServices, This, RegWidth32, Offset, &CrReutChErrCounterStatus0.Data);
+      Offset += MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_1_REG - MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_0_REG;
+    }
+  } else {
+    return (ChannelNotSupported);
+  }
+  return (Success);
+}
+
+/**
+
+@brief
+  Function used to get the DQ lane error status.
+
+  @param[in, out] PeiServices  - An indirect pointer to the PEI Services Table published by the PEI Foundation.
+  @param[in, out] This         - Interface pointer that implements the particular SSA_BIOS_SERVICES_PPI instance.
+  @param[in]      Socket       - Zero based CPU socket number.
+  @param[in]      Controller   - Zero based controller number.
+  @param[in]      Channel      - Zero based channel number.
+
+  @retval The DQ lane error status..
+
+**/
+static
+UINT64
+GetDqErrorStatus (
+  EFI_PEI_SERVICES      **PeiServices,
+  SSA_BIOS_SERVICES_PPI *This,
+  UINT8                 Socket,
+  UINT8                 Controller,
+  UINT8                 Channel
+  )
+{
+  MCHBAR_CH0_CR_REUT_CH_ERR_DATA_STATUS_STRUCT CrReutChErrDataStatus;
+  MrcParameters *MrcData;
+
+  MrcData = (MrcParameters *) This->SsaMemoryConfig.MrcData;
+  CrReutChErrDataStatus.Data = 0;
+  if (IsChannelPresent (MrcData, Socket, Controller, Channel)) {
+    ReadMem (
+      PeiServices,
+      This,
+      RegWidth64,
+      MCHBAR_CH0_CR_REUT_CH_ERR_DATA_STATUS_REG +
+      (Channel * (MCHBAR_CH1_CR_REUT_CH_ERR_DATA_STATUS_REG - MCHBAR_CH0_CR_REUT_CH_ERR_DATA_STATUS_REG)),
+      &CrReutChErrDataStatus.Data);
+  }
+  return (CrReutChErrDataStatus.Data);
+}
+
+/**
+
+@brief
+  Function used to get the ECC lane error status.
+
+  @param[in, out] PeiServices - An indirect pointer to the PEI Services Table published by the PEI Foundation.
+  @param[in, out] This        - Interface pointer that implements the particular SSA_BIOS_SERVICES_PPI instance.
+  @param[in]      Socket      - Zero based CPU socket number.
+  @param[in]      Controller  - Zero based controller number.
+  @param[in]      Channel     - Zero based channel number.
+
+  @retval Nothing.
+
+**/
+static
+UINT8
+GetEccErrorStatus (
+  EFI_PEI_SERVICES      **PeiServices,
+  SSA_BIOS_SERVICES_PPI *This,
+  UINT8                 Socket,
+  UINT8                 Controller,
+  UINT8                 Channel
+  )
+{
+  MCHBAR_CH0_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_STRUCT Status;
+  MrcParameters *MrcData;
+
+  MrcData = (MrcParameters *) This->SsaMemoryConfig.MrcData;
+  Status.Data = 0;
+  if (IsChannelPresent (MrcData, Socket, Controller, Channel)) {
+    ReadMem (
+      PeiServices,
+      This,
+      RegWidth32,
+      MCHBAR_CH0_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_REG +
+      (Channel * (MCHBAR_CH1_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_REG -
+      MCHBAR_CH0_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_REG)),
+      &Status.Data);
+  }
+  return ((UINT8) Status.Bits.ECC_Error_Status);
+}
+
+/**
+
+@brief
+  Function used to get the ECC lane error status.
+
+  @param[in, out] PeiServices - An indirect pointer to the PEI Services Table published by the PEI Foundation.
+  @param[in, out] This        - Interface pointer that implements the particular SSA_BIOS_SERVICES_PPI instance.
+  @param[in]      Socket      - Zero based CPU socket number.
+  @param[in]      Controller  - Zero based controller number.
+  @param[in]      Channel     - Zero based channel number.
+  @param[in]      Counter     - Zero based counter number.
+  @param[in]      CounterMode - Enum that indicates the counter mode to be used. Count on all lanes,
+                                count on a particular lane, count on a byte group, count on a particular chunk.
+  @param[in]      ModeIndex   - Extra index used to provide additional information if needed by the mode selected.
+                                This indicates which lane, byte group or chunk has been selected.
+
+  @retval Nothing.
+
+**/
+static
+SSA_STATUS
+SetErrorCounterMode (
+  EFI_PEI_SERVICES      **PeiServices,
+  SSA_BIOS_SERVICES_PPI *This,
+  UINT8                 Socket,
+  UINT8                 Controller,
+  UINT8                 Channel,
+  UINT8                 Counter,
+  COUNTER_MODE          CounterMode,
+  UINT32                ModeIndex
+  )
+{
+  UINT32                                         Offset;
+  MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_0_STRUCT ReutChErrCounterCtl;
+  MrcParameters *MrcData;
+
+  MrcData = (MrcParameters *) This->SsaMemoryConfig.MrcData;
+  if (IsChannelPresent (MrcData, Socket, Controller, Channel)) {
+    ReutChErrCounterCtl.Data = 0;
+    switch (CounterMode) {
+      case AllLanes:
+        Offset = MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_0_REG +
+          ((MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_0_REG - MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_0_REG) * Channel);
+        break;
+
+      case ParticularLane:
+      case ParticularByteGroup:
+      case ParticularChunk:
+        Offset = MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_0_REG +
+          ((MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_0_REG - MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_0_REG) * Channel) +
+          ((MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_1_REG - MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_0_REG) * Counter);
+        ReutChErrCounterCtl.Bits.Counter_Pointer = ModeIndex;
+        ReutChErrCounterCtl.Bits.Counter_Control = CounterMode;
+        break;
+
+      default:
+        return (UnsupportedValue);
+    }
+    MrcWriteCR (MrcData, Offset, ReutChErrCounterCtl.Data);
+  }
+  return (Success);
+}
+
+/**
+
+@brief
+  Function used to get the error count value for a given channel on a given socket/controller.
+
+  @param[in, out] PeiServices - An indirect pointer to the PEI Services Table published by the PEI Foundation.
+  @param[in, out] This        - Interface pointer that implements the particular SSA_BIOS_SERVICES_PPI instance.
+  @param[in]      Socket      - Zero based CPU socket number.
+  @param[in]      Controller  - Zero based controller number.
+  @param[in]      Channel     - Zero based channel number.
+  @param[in]      Counter     - Zero based counter number.
+
+  @retval Nothing.
+
+**/
+static
+ERROR_COUNT_32BITS
+GetErrorCount (
+  EFI_PEI_SERVICES      **PeiServices,
+  SSA_BIOS_SERVICES_PPI *This,
+  UINT8                 Socket,
+  UINT8                 Controller,
+  UINT8                 Channel,
+  UINT8                 Counter
+  )
+{
+  MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_0_STRUCT CrReutErrCounterStatus0;
+  ERROR_COUNT_32BITS Count;
+  UINT32             Offset;
+  UINT8              Byte;
+  MrcParameters      *MrcData;
+
+  MrcData    = (MrcParameters *) This->SsaMemoryConfig.MrcData;
+  Count.Data = 0;
+  if (IsChannelPresent (MrcData, Socket, Controller, Channel)) {
+    Offset = MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_0_REG +
+      (Channel * (MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_0_REG - MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_0_REG));
+    for (Byte = 0; Byte < MrcData->SysOut.Outputs.SdramCount; Byte++) {
+      ReadMem (PeiServices, This, RegWidth32, Offset, &CrReutErrCounterStatus0.Data);
+      Count.Data += CrReutErrCounterStatus0.Data;
+      Offset += MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_1_REG - MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_0_REG;
+    }
+  }
+  if (Count.Data > 0x7FFFFFFF) {
+    Count.Bits.Count    = 0x7FFFFFFF;
+    Count.Bits.Overflow = 1;
+  }
+
+  return (Count);
+}
+
+/**
+
+@brief
+  Function used to set the lane validation mask for a give channel on a given socket/controller.
+  Only the lanes with the mask bit set will be checked for errors.
+
+  @param[in, out] PeiServices - An indirect pointer to the PEI Services Table published by the PEI Foundation.
+  @param[in, out] This        - Interface pointer that implements the particular SSA_BIOS_SERVICES_PPI instance.
+  @param[in]      Socket      - Zero based CPU socket number.
+  @param[in]      Controller  - Zero based controller number.
+  @param[in]      Channel     - Zero based channel number.
+  @param[in]      DqMask      - DQ lanes bitmask.
+  @param[in]      EccMask     - ECC lanes bitmask.
+
+  @retval Nothing.
+
+**/
+static
+VOID
+SetValidationBitMask (
+  EFI_PEI_SERVICES      **PeiServices,
+  SSA_BIOS_SERVICES_PPI *This,
+  UINT8                 Socket,
+  UINT8                 Controller,
+  UINT8                 Channel,
+  UINT64                DqMask,
+  UINT8                 EccMask
+  )
+{
+  MCHBAR_CH0_CR_REUT_CH_ERR_DATA_MASK_STRUCT CrReutErrDataMask;
+  MCHBAR_CH0_CR_REUT_CH_ERR_ECC_MASK_STRUCT CrReutChErrEccMask;
+  UINT32 Offset;
+  MrcParameters *MrcData;
+
+  MrcData = (MrcParameters *) This->SsaMemoryConfig.MrcData;
+  if (IsChannelPresent (MrcData, Socket, Controller, Channel)) {
+    Offset = MCHBAR_CH0_CR_REUT_CH_ERR_DATA_MASK_REG +
+      ((MCHBAR_CH1_CR_REUT_CH_ERR_DATA_MASK_REG - MCHBAR_CH0_CR_REUT_CH_ERR_DATA_MASK_REG) * Channel);
+    CrReutErrDataMask.Data = ~DqMask;
+    WriteMem (PeiServices, This, RegWidth64, Offset, &CrReutErrDataMask.Data);
+
+    Offset = MCHBAR_CH0_CR_REUT_CH_ERR_ECC_MASK_REG +
+      ((MCHBAR_CH1_CR_REUT_CH_ERR_ECC_MASK_REG - MCHBAR_CH0_CR_REUT_CH_ERR_ECC_MASK_REG) * Channel);
+    CrReutChErrEccMask.Data = ~EccMask;
+    WriteMem (PeiServices, This, RegWidth8, Offset, &CrReutChErrEccMask.Data);
+  }
+  return;
+}
+
+/**
+
+@brief
+  Function used to set the phase mask for a give channel on a given socket/controller.
+  Only the phases with the mask bit set will be checked for errors.
+
+  @param[in, out] PeiServices        - An indirect pointer to the PEI Services Table published by the PEI Foundation.
+  @param[in, out] This               - Interface pointer that implements the particular SSA_BIOS_SERVICES_PPI instance.
+  @param[in]      Socket             - Zero based CPU socket number.
+  @param[in]      Controller         - Zero based controller number.
+  @param[in]      Channel            - Zero based channel number.
+  @param[in]      CachelineMask      - Mask for the cacheline to be enabled.
+  @param[in]      PhaseMask          - Mask for the Phase. One bit for each phase.
+
+  @retval Nothing.
+
+**/
+static
+VOID
+SetValidationPhaseMask (
+  EFI_PEI_SERVICES      **PeiServices,
+  SSA_BIOS_SERVICES_PPI *This,
+  UINT8                 Socket,
+  UINT8                 Controller,
+  UINT8                 Channel,
+  UINT8                 CachelineMask,
+  UINT8                 PhaseMask
+  )
+{
+  MCHBAR_CH0_CR_REUT_CH_ERR_CTL_STRUCT CrReutChErrCtl;
+  UINT32 Offset;
+  MrcParameters *MrcData;
+
+  MrcData = (MrcParameters *) This->SsaMemoryConfig.MrcData;
+  if (IsChannelPresent (MrcData, Socket, Controller, Channel)) {
+    Offset = MCHBAR_CH0_CR_REUT_CH_ERR_CTL_REG +
+      ((MCHBAR_CH1_CR_REUT_CH_ERR_CTL_REG - MCHBAR_CH0_CR_REUT_CH_ERR_CTL_REG) * Channel);
+    CrReutChErrCtl.Data = 0;
+    CrReutChErrCtl.Bits.Selective_Error_Enable_Cacheline = CachelineMask;
+    CrReutChErrCtl.Bits.Selective_Error_Enable_Chunk = PhaseMask;
+    WriteMem (PeiServices, This, RegWidth32, Offset, &CrReutChErrCtl.Data);
+  }
+  return;
+}
+
+/**
+
+@brief
+  Function used to run a point test.
+
+  @param[in, out] PeiServices     - An indirect pointer to the PEI Services Table published by the PEI Foundation.
+  @param[in, out] This            - Interface pointer that implements the particular SSA_BIOS_SERVICES_PPI instance.
+  @param[in]      Socket          - Zero based CPU socket number.
+  @param[in]      Controller      - Zero based controller number.
+  @param[in]      TestParameters  - Architecture-specific test parameters.
+  @param[in]      SkipSetup       - Skip the test setup. It is OK to skip the setup after the first test.
+
+  @retval Nothing.
+
+**/
+static
+VOID
+RunPointTest (
+  EFI_PEI_SERVICES      **PeiServices,
+  SSA_BIOS_SERVICES_PPI *This,
+  UINT8                 Socket,
+  UINT8                 Controller,
+  VOID                  *TestParameters,
+  BOOLEAN               SkipSetup
+  )
+{
+  const MRC_REUTAddress ReutAddress = {
+    {0, 0, 0, 0},    // Start
+    {0, 0, 0, 1023}, // Stop
+    {0, 0, 0, 0},    // Order
+    {0, 0, 0, 0},    // IncRate
+    {0, 0, 0, 1}     // IncValue
+  };
+  //                                  IncRate,  Start, Stop, DQPat
+  const MRC_WDBPattern CWdbPattern = {   16,      0,     1, BasicVA};
+
+  MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_STRUCT CrReutChPatWdbClMuxCfg;
+  MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_STRUCT CrReutChSeqCfgMcMain0;
+  MCDFXS_CR_REUT_GLOBAL_CTL_MCMAIN_STRUCT CrReutGlobalCtl;
+  MCDFXS_CR_REUT_GLOBAL_ERR_MCMAIN_STRUCT CrReutGlobalErr;
+  MRC_WDBPattern WdbPattern;
+  POINT_TEST_PARAMETERS *Params;
+  UINT32 Offset;
+  UINT16 BurstLength;
+  UINT8 DumArr[7];
+  UINT8 Channel;
+  UINT8 Rank;
+  UINT8 TargetRank;
+  UINT8 LoopCount;
+  MrcParameters *MrcData;
+
+  MrcData = (MrcParameters *) This->SsaMemoryConfig.MrcData;
+  if (IsControllerPresent (MrcData, Socket, Controller)) {
+    CopyMem (&WdbPattern, &CWdbPattern, sizeof (MRC_WDBPattern));
+    SetMem (DumArr, 1, sizeof (DumArr));
+    Params = (POINT_TEST_PARAMETERS *) TestParameters;
+
+    // Program the set up the test for each channel.
+    if (!SkipSetup) {
+      for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+        if (IsChannelPresent (MrcData, Socket, Controller, Channel)) {
+          // Update the WDB pattern incRate, start and stop.
+          WdbPattern.IncRate = Params->WdbIncRates[Channel];
+          WdbPattern.Stop    = Params->WdbEnds[Channel];
+
+          // if (aggressor) traffic is WR or RD, need double the burst length to make it overlap with
+          // (victim) loopback traffic.
+          switch (Params->TrafficModes[Channel].Bits.TrafficMode) {
+            case TrafficModeWrite:              // PatWr (Write Only)
+            case TrafficModeRead:               // PatRd (Read Only)
+              BurstLength = Params->BurstLength * 2;
+              LoopCount   = Params->LoopCount + 1;
+              break;
+
+            case TrafficModeWrRd:               // PatWrRd (Standard Write/Read Loopback)
+            default:
+              BurstLength = Params->BurstLength;
+              LoopCount   = Params->LoopCount;
+              break;
+          }
+          SetupIOTest (MrcData,
+            (MRC_BIT0 << Channel),                          // ChbitMask,
+            Params->TrafficModes[Channel].Bits.TrafficMode, // CmdPat,
+            BurstLength,                                    // NumCL,
+            LoopCount,                                      // LC,
+            &ReutAddress,                                   // REUTAddress,
+            Params->StopOnErr,                              // SOE,
+            &WdbPattern,                                    // WDBPattern,
+            Params->EnCadb[Channel],                        // EnCADB,
+            0,                                              // EnCKE,
+            0);                                             // SubSeqWait
+
+          // Set up LFSR or fix pattern modes.
+          if (Params->Modes[Channel].Bits.PatternMode == PatternModeFixed) {
+            // Sequentially walk through the WDB.
+            CrReutChPatWdbClMuxCfg.Data = 0;
+            CrReutChPatWdbClMuxCfg.Bits.Mux2_Control = 1;
+            CrReutChPatWdbClMuxCfg.Bits.Mux1_Control = 1;
+            CrReutChPatWdbClMuxCfg.Bits.Mux0_Control = 1;
+            CrReutChPatWdbClMuxCfg.Bits.ECC_Data_Source_Sel = 1;
+            Offset = MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_REG +
+              ((MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_REG - MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_REG) * Channel);
+            WriteMem (PeiServices, This, RegWidth32, Offset, &CrReutChPatWdbClMuxCfg.Data);
+          }
+
+          // Update the target rank.
+          TargetRank = 0;
+          for (Rank = 0; Rank < MAX_RANK_IN_CHANNEL; Rank++) {
+            // support one rank now
+            if (Params->Ranks[Channel] & (1 << Rank)) {
+              TargetRank = Rank;
+              break;
+            }
+          } // Rank
+          SelectReutRanks (MrcData, Channel, (1 << TargetRank), 0);
+        } // if
+      } // Channel
+
+      // The SetupIOTest() disables channel's global control, we need to enable them.
+      for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+        if (IsChannelPresent (MrcData, Socket, Controller, Channel)) {
+          Offset = MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_REG +
+            ((MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_REG - MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_REG) * Channel);
+          ReadMem (PeiServices, This, RegWidth64, Offset, &CrReutChSeqCfgMcMain0.Data);
+          CrReutChSeqCfgMcMain0.Bits.Global_Control = 1;
+          WriteMem (PeiServices, This, RegWidth64, Offset, &CrReutChSeqCfgMcMain0.Data);
+        } // if
+      } // Channel
+
+      // Run test
+      RunIOTest (MrcData, // MrcParameters *MrcData,
+        3,                // U8 ChbitMask,
+        BasicVA,          // U8 DQPat,
+        DumArr,           // U8 *SeqLCs,
+        0,                // U8 ClearErrors,
+        0);
+    } else {
+      // bypassSetup. Only issue test start bit. The not !bypassSetup needed to be called
+      // first to set up the system.
+      CrReutGlobalCtl.Data = 0;
+      CrReutGlobalCtl.Bits.Global_Start_Test = 1;
+      WriteMem (PeiServices, This, RegWidth32, MCDFXS_CR_REUT_GLOBAL_CTL_MCMAIN_REG, &CrReutGlobalCtl.Data);
+
+      // Wait until channel test done.
+      do {
+        ReadMem (PeiServices, This, RegWidth32, MCDFXS_CR_REUT_GLOBAL_ERR_MCMAIN_REG, &CrReutGlobalErr.Data);
+      }
+      while (!CrReutGlobalErr.Bits.Channel_Test_Done_Status_0 || !CrReutGlobalErr.Bits.Channel_Test_Done_Status_1);
+    }
+  }
+  return;
+}
+
+const SSA_BIOS_SERVICES_PPI SsaBiosServicesConst = {
+  {
+    SSA_REVISION_BIOS,
+    0,                                  // *SsaCommonConfig
+    0,                                  // *SsaMemoryConfig
+  },
+  {
+    SSA_REVISION_COMMON,
+    0,                                  // MrcData
+    ReadMem,
+    WriteMem,
+    ReadIo,
+    WriteIo,
+    ReadPci,
+    WritePci,
+    GetBaseAddress,
+    Malloc,
+    Free,
+    SsaDebugPrint,
+  },
+  {
+    SSA_REVISION_MEMORY,
+    0,                                  // MrcData
+    GetSystemInfo,
+    GetMemVoltage,
+    SetMemVoltage,
+    GetMemTemp,                         // @todo: not implemented yet
+    RestoreMrs,
+    WriteMrs,
+    ReadMrs,
+    GetDimmFromLogicalRank,
+    GetDimmInfo,
+    GetRankInDimm,
+    GetLogicalRankBitMask,
+    GetChannelBitMask,
+    GetControllerBitMask,
+    JedecReset,
+    GetMarginParamLimits,
+    OffsetMarginParam,
+    SetWdbPattern,
+    SetCadbPattern,
+    ClearErrorStatus,
+    ClearErrorCounter,
+    GetDqErrorStatus,
+    GetEccErrorStatus,
+    SetErrorCounterMode,
+    GetErrorCount,
+    SetValidationBitMask,
+    SetValidationPhaseMask,
+    RunPointTest
+  }
+};
+
+/**
+
+@brief
+  Initialize the SsaBiosServices data structure.
+
+  @param[in] MrcData  - The MRC global data area.
+
+  @retval Nothing
+
+**/
+VOID
+SsaBiosInitialize (
+  IN MrcParameters       *MrcData
+  )
+{
+  EFI_PEI_SERVICES       **PeiServices;
+  SSA_BIOS_SERVICES_PPI  *SsaBiosServicesPpi;
+  EFI_PEI_PPI_DESCRIPTOR *SsaBiosServicesPpiDesc;
+  EFI_STATUS             Status;
+
+  SsaBiosServicesPpi = (SSA_BIOS_SERVICES_PPI *) AllocatePool (sizeof (SSA_BIOS_SERVICES_PPI));
+  ASSERT (SsaBiosServicesPpi != NULL);
+  SsaBiosServicesPpiDesc = (EFI_PEI_PPI_DESCRIPTOR *) AllocatePool (sizeof (EFI_PEI_PPI_DESCRIPTOR));
+  ASSERT (SsaBiosServicesPpiDesc != NULL);
+
+  CopyMem (SsaBiosServicesPpi, &SsaBiosServicesConst, sizeof (SSA_BIOS_SERVICES_PPI));
+  SsaBiosServicesPpi->SsaHeader.SsaCommonConfig = &SsaBiosServicesPpi->SsaCommonConfig;
+  SsaBiosServicesPpi->SsaHeader.SsaMemoryConfig = &SsaBiosServicesPpi->SsaMemoryConfig;
+  SsaBiosServicesPpi->SsaCommonConfig.BiosData = MrcData;
+  SsaBiosServicesPpi->SsaMemoryConfig.MrcData  = MrcData;
+
+  EfiCommonLibZeroMem (SsaBiosServicesPpiDesc, sizeof (EFI_PEI_PPI_DESCRIPTOR));
+  SsaBiosServicesPpiDesc->Flags  = EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST;
+  SsaBiosServicesPpiDesc->Guid   = &gSsaBiosServicesPpiGuid;
+  SsaBiosServicesPpiDesc->Ppi    = SsaBiosServicesPpi;
+
+  PeiServices = (EFI_PEI_SERVICES **) MrcData->SysIn.Inputs.Debug.Stream;
+  Status = (**PeiServices).InstallPpi (PeiServices, SsaBiosServicesPpiDesc);
+  ASSERT_EFI_ERROR (Status);
+
+  MRC_DEBUG_MSG (&MrcData->SysIn.Inputs.Debug, MSG_LEVEL_NOTE, "SSA Interface ready\n");
+
+  return;
+}
+
+#endif // SSA_FLAG
diff --git a/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/MrcSsaServices.h b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/MrcSsaServices.h
new file mode 100644
index 0000000..63d70c1
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/MrcSsaServices.h
@@ -0,0 +1,761 @@
+/**
+This file contains an 'Intel Peripheral Driver' and uniquely
+identified as "Intel Reference Module" and is
+licensed for Intel CPUs and chipsets under the terms of your
+license agreement with Intel or your vendor.  This file may
+be modified by the user, subject to additional terms of the
+license agreement
+
+Copyright (c) 2012 - 2013 Intel Corporation. All rights reserved.
+This software and associated documentation (if any) is furnished
+under a license and may only be used or copied in accordance
+with the terms of the license. Except as permitted by such
+license, no part of this software or documentation may be
+reproduced, stored in a retrieval system, or transmitted in any
+form or by any means without the express written consent of
+Intel Corporation.
+
+@file
+  MrcSsaServices.h
+
+@brief
+  This file contains the SSA services PPI.
+**/
+#ifndef _MrcSsaServices_h_
+#define _MrcSsaServices_h_
+
+#include "EdkIIGluePeim.h"
+
+#pragma pack (push, 1)
+
+#define INT32_MIN                       (0x80000000)
+#define INT32_MAX                       (0x7FFFFFFF)
+#define INT16_MIN                       (0x8000)
+#define INT16_MAX                       (0x7FFF)
+#define MAX_CHUNK_SIZE                  (8)
+#ifndef MAX_CHANNEL
+#define MAX_CHANNEL                     (2)
+#endif
+
+typedef enum {
+  Success,                                      ///< The function completed successfully.
+  NotYetAvailable,                              ///< The function is not yet available.
+  NotAvailable,                                 ///< The function is not available or selected DIMM is invalid.
+  UnsupportedValue,                             ///< A function parameter is incorrect.
+  SocketNotSupported,                           ///< The desired CPU is not supported or not available in the system.
+  ControllerNotSupported,                       ///< The desired memory controller is not supported or not available in the CPU.
+  ChannelNotSupported,                          ///< The desired memory channel is not supported or not available on the controller.
+  LogicalRankNotSupported,                      ///< The desired memory rank is not supported or not available in the channel.
+  IoLevelNotSupported,                          ///< The desired I/O level is not supported or not available.
+  MarginGroupNotSupported,                      ///< The desired margin group is not supported or not available.
+  SsaStatusMax                                  ///< SSA_STATUS structure maximum value.
+} SSA_STATUS;
+
+typedef enum {
+  RegWidth8,                                    ///< An 8-bit register width is selected.
+  RegWidth16,                                   ///< A 16-bit register width is selected.
+  RegWidth32,                                   ///< A 32-bit register width is selected.
+  RegWidth64,                                   ///< A 64-bit register width is selected.
+  RegWidthMax                                   ///< REG_WIDTH structure maximum value.
+} REG_WIDTH;
+
+typedef enum {
+  RecEnDelay,                                   ///< Receive enable delay margin group.
+  RxDqsDelay,                                   ///< Receive DQS delay margin group.
+  RxDqBitDelay,                                 ///< Receive DS bit delay margin group.
+  WrLvlDelay,                                   ///< Write leveling delay margin group.
+  TxDqsDelay,                                   ///< Transmit DQS delay margin group.
+  TxDqDelay,                                    ///< Transmit DQ delay margin group.
+  TxDqBitDelay,                                 ///< Transmit DQ bit delay margin group.
+  RxVref,                                       ///< Receive voltage reference margin group.
+  TxVref,                                       ///< Transmit voltage reference margin group.
+  CmdAll,                                       ///< All command margin group.
+  CmdGrp0,                                      ///< Command 0 margin group.
+  CmdGrp1,                                      ///< Command 1 margin group.
+  CmdGrp2,                                      ///< Command 2 margin group.
+  CtlAll,                                       ///< All control margin group.
+  CtlGrp0,                                      ///< Control 1 margin group.
+  CtlGrp1,                                      ///< Control 2 margin group.
+  CtlGrp2,                                      ///< Control 3 margin group.
+  CtlGrp3,                                      ///< Control 4 margin group.
+  CtlGrp4,                                      ///< Control 5 margin group.
+  CtlGrp5,                                      ///< Control 5 margin group.
+  CkAll,                                        ///< All CK margin group.
+  CmdCtlAll,                                    ///< All command/control margin group.
+  CmdVref,                                      ///< Command voltage reference margin group.
+  GsmGtMax                                      ///< GSM_GT structure maximum value.
+} GSM_GT;
+
+typedef enum {
+  VmseLevel,                                    ///< VMSE I/O level.
+  DdrLevel,                                     ///< DDR I/O level.
+  LrbufLevel,                                   ///< LRBUF I/O level.
+  GsmLtMax                                      ///< GSM_LT structure maximum value.
+} GSM_LT;
+
+typedef enum {
+  AllLanes,                                     ///< All lanes counter mode.
+  ParticularLane,                               ///< A particular lane counter mode.
+  ParticularByteGroup,                          ///< A particular byte lane counter mode.
+  ParticularChunk,                              ///< A particular chunk counter mode.
+  CounterModeMax                                ///< COUNTER_MODE structure maximum value.
+} COUNTER_MODE;
+
+typedef enum {
+  PatternModeFixed,                             ///< Fixed pattern mode.
+  PatternModeLsfr,                              ///< LFSR pattern mode.
+  PatternModeMax                                ///< PATTERN_MODE structure maximum value.
+} PATTERN_MODE;
+
+typedef enum {
+  TrafficModeWrRd,                              ///< Write/Read traffic mode.
+  TrafficModeWrite,                             ///< Write traffic mode.
+  TrafficModeRead,                              ///< Read traffic mode.
+  TrafficModeMax                                ///< TRAFFIC_MODE structure maximum value.
+} TRAFFIC_MODE;
+
+typedef enum {
+  MCH_BAR,                                      ///< MCHBAR base address selection.
+  BaseAddrTypeMax                               ///< BASE_ADDR_TYPE structure maximum value.
+} BASE_ADDR_TYPE;
+
+typedef enum {
+  SSA_D_WARN  = EFI_D_WARN,                     ///< Warnings
+  SSA_D_LOAD  = EFI_D_LOAD,                     ///< Load events
+  SSA_D_INFO  = EFI_D_INFO,                     ///< Informational debug messages
+  SSA_D_EVENT = EFI_D_EVENT,                    ///< Event messages
+  SSA_D_ERROR = EFI_D_ERROR,                    ///< Error
+} PRINT_LEVEL;
+
+typedef union {
+  UINT64 Data64;                                ///< 64-bit MMIO buffer.
+  UINT32 Data32;                                ///< 32-bit MMIO buffer.
+  UINT16 Data16;                                ///< 16-bit MMIO buffer.
+  UINT8  Data8;                                 ///< 8-bit MMIO buffer.
+} MMIO_BUFFER;
+
+typedef union {
+  UINT32 Data32;                                ///< 32-bit I/O buffer.
+  UINT16 Data16;                                ///< 16-bit I/O buffer.
+  UINT8  Data8;                                 ///< 8-bit I/O buffer.
+} IO_BUFFER;
+
+typedef union {
+  UINT32 Data32;                                ///< 32-bit PCI buffer.
+  UINT16 Data16;                                ///< 16-bit PCI buffer.
+  UINT8  Data8;                                 ///< 8-bit PCI buffer.
+} PCI_BUFFER;
+
+typedef union {
+  struct {
+    UINT32 Reserved0 : 2;                       ///< PCI address pointer reserved value, range 0 to 3.
+    UINT32 Offset    : 6;                       ///< PCI address pointer offset value, range 0 to 63.
+    UINT32 Function  : 3;                       ///< PCI address pointer function value, range 0 to 7.
+    UINT32 Device    : 5;                       ///< PCI address pointer device value, range 0 to 31.
+    UINT32 Bus       : 8;                       ///< PCI address pointer bus value, range 0 to 255.
+    UINT32 Reserved1 : 7;                       ///< PCI address pointer reserved value, range 0 to 127.
+    UINT32 Enable    : 1;                       ///< PCI address pointer enable flag, 0 = disable, 1 = enable.
+  } Bits;
+  UINT32 Value;
+} PCI_CONFIG_SPACE;
+
+#ifndef _MrcSpdData_h_
+typedef union {
+  struct {
+    UINT16 ContinuationCount  :  7;             ///< Bits 6:0
+    UINT16 ContinuationParity :  1;             ///< Bits 7:7
+    UINT16 LastNonZeroByte    :  8;             ///< Bits 15:8
+  } Bits;
+  UINT16 Data;
+  UINT8  Data8;
+} SPD_MANUFACTURER_ID_CODE;
+
+typedef struct {
+  UINT8 Location;                               ///< Module Manufacturing Location
+} SPD_MANUFACTURING_LOCATION;
+
+typedef struct {
+  UINT8  Year;                                  ///< Year represented in BCD (00h = 2000)
+  UINT8  Week;                                  ///< Year represented in BCD (47h = week 47)
+} SPD_MANUFACTURING_DATE;
+
+typedef union {
+  UINT32 Data;
+  UINT16 SerialNumber16[2];
+  UINT8  SerialNumber8[4];
+} SPD_MANUFACTURER_SERIAL_NUMBER;
+
+typedef struct {
+  SPD_MANUFACTURER_ID_CODE       IdCode;        ///< Module Manufacturer ID Code
+  SPD_MANUFACTURING_LOCATION     Location;      ///< Module Manufacturing Location
+  SPD_MANUFACTURING_DATE         Date;          ///< Module Manufacturing Year, in BCD (range: 2000-2255)
+  SPD_MANUFACTURER_SERIAL_NUMBER SerialNumber;  ///< Module Serial Number
+} SPD_UNIQUE_MODULE_ID;
+#endif //_MrcSpdData_h_
+
+typedef struct {
+  BOOLEAN               EccSupport;             ///< TRUE if the DIMM supports ECC, otherwise FALSE.
+  UINT32                DimmCapacity;           ///< The DIMM's capacity, in megabytes.
+  UINT32                RowSize;                ///< The DIMM's row address size.
+  UINT16                ColumnSize;             ///< The DIMM's column address size.
+  SPD_UNIQUE_MODULE_ID  SerialNumber;           ///< The DIMM's serial number, retrieved from the SPD.
+} MrcDimmInfo;
+
+typedef struct {
+  UINT8                 MaxNumberSockets;       ///< The maximum number of CPU sockets in a system.
+  UINT8                 MaxNumberControllers;   ///< The maximum number of memory controllers in a CPU socket.
+  UINT8                 MaxNumberChannels;      ///< The maximum number of channels in a memory controller.
+  UINT8                 MaxNumberLogicalRanks;  ///< The maximum number of ranks in a memory channel.
+  UINT32                SocketsBitMask;         ///< The bit mask of available CPU sockets.
+} MrcSystemInfo;
+
+typedef union {
+  struct {
+    UINT16 PatternMode : 1;                     ///< Pattern types. 0 = Fixed, 1 = LSFR.
+    UINT16             : 15;                    ///< Reserved.
+  } Bits;
+  UINT16 Data;
+} PATTERN_MODES;
+
+typedef union {
+  struct {
+    UINT8 TrafficMode : 2;                      ///< Traffic modes. 0 = Write/Read, 1 = Write, 2 = Read, 3 = Reserved.
+    UINT8             : 6;                      ///< Reserved.
+  } Bits;
+  UINT8 Data;
+} TRAFFIC_MODES;
+
+typedef union {
+  struct {
+    UINT32 Count    : 31;                       ///< Error count, range is 0 to 2^31 - 1.
+    UINT32 Overflow : 1;                        ///< Error count overflow, 0 = no overflow, 1 = overflow.
+  } Bits;
+  UINT32 Data;
+} ERROR_COUNT_32BITS;
+
+typedef struct {
+  UINT16        Ranks[MAX_CHANNEL];             ///< The bit mask of the ranks in a channel to test.
+  TRAFFIC_MODES TrafficModes[MAX_CHANNEL];      ///< Traffic modes. 0 = write/read, 1 = write only, 2 = read only, all other values reserved.
+  PATTERN_MODES Modes[MAX_CHANNEL];             ///< Pattern types. 0 = Fixed, 1 = LSFR.
+  UINT8         WdbIncRates[MAX_CHANNEL];       ///< WDB increment rates.
+  UINT8         WdbEnds[MAX_CHANNEL];           ///< WDB pattern stop.
+  UINT8         EnCadb[MAX_CHANNEL];            ///< Enable CADB.
+  UINT8         LoopCount;                      ///< Sequence repeat count.
+  UINT16        BurstLength;                    ///< Burst length.
+  UINT8         StopOnErr;                      ///< Stop on error.
+} POINT_TEST_PARAMETERS;
+
+typedef 
+VOID
+(EFIAPI * WRITE_MEM) (
+  EFI_PEI_SERVICES      **PeiServices,
+//  SSA_BIOS_SERVICES_PPI *This,
+  VOID                  *This,
+  REG_WIDTH             Width,
+  EFI_PHYSICAL_ADDRESS  Address,
+  VOID                  *Buffer
+  );
+
+typedef 
+VOID
+(EFIAPI * READ_MEM) (
+  EFI_PEI_SERVICES      **PeiServices,
+//  SSA_BIOS_SERVICES_PPI *This,
+  VOID                  *This,
+  REG_WIDTH             Width,
+  EFI_PHYSICAL_ADDRESS  Address,
+  VOID                  *Buffer
+  );
+
+typedef 
+VOID
+(EFIAPI * WRITE_IO) (
+  EFI_PEI_SERVICES      **PeiServices,
+//  SSA_BIOS_SERVICES_PPI *This,
+  VOID                  *This,
+  REG_WIDTH             Width,
+  UINT32                Address,
+  VOID                  *Buffer
+  );
+
+typedef 
+VOID
+(EFIAPI * READ_IO) (
+  EFI_PEI_SERVICES      **PeiServices,
+//  SSA_BIOS_SERVICES_PPI *This,
+  VOID                  *This,
+  REG_WIDTH             Width,
+  UINT32                Address,
+  VOID                  *Buffer
+  );
+
+typedef 
+VOID
+(EFIAPI * WRITE_PCI) (
+  EFI_PEI_SERVICES                **PeiServices,
+//  SSA_BIOS_SERVICES_PPI           *This,
+  VOID                            *This,
+  REG_WIDTH                       Width,
+  EFI_PEI_PCI_CFG_PPI_PCI_ADDRESS *Address,
+  VOID                            *Buffer,
+  BOOLEAN                         CachedData
+  );
+
+typedef 
+VOID
+(EFIAPI * READ_PCI) (
+  EFI_PEI_SERVICES                **PeiServices,
+//  SSA_BIOS_SERVICES_PPI           *This,
+  VOID                            *This,
+  REG_WIDTH                       Width,
+  EFI_PEI_PCI_CFG_PPI_PCI_ADDRESS *Address,
+  VOID                            *Buffer,
+  BOOLEAN                         CachedData
+  );
+
+typedef 
+SSA_STATUS
+(EFIAPI * GET_BASE_ADDRESS) (
+  EFI_PEI_SERVICES      **PeiServices,
+//  SSA_BIOS_SERVICES_PPI *This,
+  VOID                  *This,
+  UINT8                 Socket,
+  UINT8                 Controller,
+  UINT8                 Index,
+  BASE_ADDR_TYPE        BaseAddressType,
+  EFI_PHYSICAL_ADDRESS  *BaseAddress
+  );
+
+typedef 
+SSA_STATUS
+(EFIAPI * GET_MEM_VOLTAGE) (
+  EFI_PEI_SERVICES      **PeiServices,
+//  SSA_BIOS_SERVICES_PPI *This,
+  VOID                  *This,
+  UINT32                *Voltage
+  );
+
+typedef 
+SSA_STATUS
+(EFIAPI * SET_MEM_VOLTAGE) (
+  EFI_PEI_SERVICES      **PeiServices,
+//  SSA_BIOS_SERVICES_PPI *This,
+  VOID                  *This,
+  UINT32                *Voltage
+  );
+
+typedef 
+SSA_STATUS
+(EFIAPI * GET_MEM_TEMP) (
+  EFI_PEI_SERVICES      **PeiServices,
+//  SSA_BIOS_SERVICES_PPI *This,
+  VOID                  *This,
+  UINT8                 Socket,
+  UINT8                 Controller,
+  UINT8                 Channel,
+  UINT8                 Dimm,
+  INT32                 *Temperature
+  );
+
+typedef 
+VOID
+(EFIAPI * RESTORE_MRS) (
+  EFI_PEI_SERVICES      **PeiServices,
+//  SSA_BIOS_SERVICES_PPI *This,
+  VOID                  *This,
+  UINT8                 Socket,
+  UINT8                 Controller,
+  UINT8                 Channel,
+  UINT8                 Dimm,
+  UINT8                 Rank,
+  UINT8                 Address
+  );
+
+typedef 
+VOID
+(EFIAPI * WRITE_MRS) (
+  EFI_PEI_SERVICES      **PeiServices,
+//  SSA_BIOS_SERVICES_PPI *This,
+  VOID                  *This,
+  UINT8                 Socket,
+  UINT8                 Controller,
+  UINT8                 Channel,
+  UINT8                 Dimm,
+  UINT8                 Rank,
+  UINT8                 Bank,
+  UINT16                Data
+  );
+
+typedef 
+VOID
+(EFIAPI * READ_MRS) (
+  EFI_PEI_SERVICES      **PeiServices,
+//  SSA_BIOS_SERVICES_PPI *This,
+  VOID                  *This,
+  UINT8                 Socket,
+  UINT8                 Controller,
+  UINT8                 Channel,
+  UINT8                 Dimm,
+  UINT8                 Rank,
+  UINT8                 Address,
+  UINT16                *Data
+  );
+
+typedef 
+VOID *
+(EFIAPI * MALLOC) (
+  EFI_PEI_SERVICES      **PeiServices,
+//  SSA_BIOS_SERVICES_PPI *This,
+  VOID                  *This,
+  UINT32                Size
+  );
+
+typedef 
+VOID
+(EFIAPI * FREE) (
+  EFI_PEI_SERVICES      **PeiServices,
+//  SSA_BIOS_SERVICES_PPI *This,
+  VOID                  *This,
+  VOID                  *Buffer
+  );
+
+typedef
+VOID
+(EFIAPI * DEBUG_PRINT) (
+  EFI_PEI_SERVICES      **PeiServices,
+//  SSA_BIOS_SERVICES_PPI *This,
+  VOID                  *This,
+  PRINT_LEVEL           PrintLevel,
+  UINT8                 *FormatString,
+  ...
+  );
+
+typedef 
+UINT8
+(EFIAPI * GET_DIMM_FROM_LOGICAL_RANK) (
+  EFI_PEI_SERVICES      **PeiServices,
+//  SSA_BIOS_SERVICES_PPI *This,
+  VOID                  *This,
+  UINT8                 Socket,
+  UINT8                 Controller,
+  UINT8                 Channel,
+  UINT8                 Rank
+  );
+
+typedef 
+SSA_STATUS
+(EFIAPI * GET_DIMM_INFO) (
+  EFI_PEI_SERVICES      **PeiServices,
+//  SSA_BIOS_SERVICES_PPI *This,
+  VOID                  *This,
+  UINT8                 Socket,
+  UINT8                 Controller,
+  UINT8                 Channel,
+  UINT8                 Dimm,
+  MrcDimmInfo           *DimmInfoBuffer
+  );
+
+typedef 
+UINT8
+(EFIAPI * GET_RANK_IN_DIMM) (
+  EFI_PEI_SERVICES      **PeiServices,
+//  SSA_BIOS_SERVICES_PPI *This,
+  VOID                  *This,
+  UINT8                 Socket,
+  UINT8                 Controller,
+  UINT8                 Channel,
+  UINT8                 Dimm
+  );
+
+typedef 
+UINT8
+(EFIAPI * GET_LOGICAL_RANK_BIT_MASK) (
+  EFI_PEI_SERVICES      **PeiServices,
+//  SSA_BIOS_SERVICES_PPI *This,
+  VOID                  *This,
+  UINT8                 Socket,
+  UINT8                 Controller,
+  UINT8                 Channel
+  );
+
+typedef 
+UINT8
+(EFIAPI * GET_CHANNEL_BIT_MASK) (
+  EFI_PEI_SERVICES      **PeiServices,
+//  SSA_BIOS_SERVICES_PPI *This,
+  VOID                  *This,
+  UINT8                 Socket,
+  UINT8                 Controller
+  );
+
+typedef 
+SSA_STATUS
+(EFIAPI * GET_SYSTEM_INFO) (
+  EFI_PEI_SERVICES      **PeiServices,
+//  SSA_BIOS_SERVICES_PPI *This,
+  VOID                  *This,
+  MrcSystemInfo         *SystemInfoBuffer
+  );
+
+
+typedef 
+UINT8
+(EFIAPI * GET_CONTROLLER_BIT_MASK) (
+  EFI_PEI_SERVICES      **PeiServices,
+//  SSA_BIOS_SERVICES_PPI *This,
+  VOID                  *This,
+  UINT8                 Socket
+  );
+
+typedef 
+VOID
+(EFIAPI * JEDEC_RESET) (
+  EFI_PEI_SERVICES      **PeiServices,
+//  SSA_BIOS_SERVICES_PPI *This,
+  VOID                  *This,
+  UINT8                 Socket,
+  UINT8                 Controller
+  );
+
+typedef 
+SSA_STATUS
+(EFIAPI * GET_MARGIN_PARAM_LIMITS) (
+  EFI_PEI_SERVICES      **PeiServices,
+//  SSA_BIOS_SERVICES_PPI *This,
+  VOID                  *This,
+  UINT8                 Socket,
+  UINT8                 Controller,
+  UINT8                 Channel,
+  UINT8                 LogicRank,
+  GSM_LT                IoLevel,
+  GSM_GT                MarginGroup,
+  INT16                 *MinOffset,
+  INT16                 *MaxOffset,
+  UINT16                *Delay
+  );
+
+typedef 
+VOID
+(EFIAPI * OFFSET_MARGIN_PARAM) (
+  EFI_PEI_SERVICES      **PeiServices,
+//  SSA_BIOS_SERVICES_PPI *This,
+  VOID                  *This,
+  UINT8                 Socket,
+  UINT8                 Controller,
+  UINT8                 Channel,
+  UINT8                 LogicRank,
+  GSM_LT                IoLevel,
+  GSM_GT                MarginGroup,
+  UINT16                Offset
+  );
+
+typedef 
+VOID
+(EFIAPI * SET_WDB_PATTERN) (
+  EFI_PEI_SERVICES      **PeiServices,
+//  SSA_BIOS_SERVICES_PPI *This,
+  VOID                  *This,
+  UINT8                 Socket,
+  UINT8                 Controller,
+  UINT8                 Channel,
+  UINT64                *Pattern,
+  UINT8                 CachelineCount,
+  UINT8                 StartCachelineIndex
+  );
+
+typedef 
+VOID
+(EFIAPI * SET_CADB_PATTERN) (
+  EFI_PEI_SERVICES      **PeiServices,
+//  SSA_BIOS_SERVICES_PPI *This,
+  VOID                  *This,
+  UINT8                 Socket,
+  UINT8                 Controller,
+  UINT8                 Channel,
+  UINT64                *Pattern,
+  UINT8                 CachelineCount,
+  UINT8                 StartCachelineIndex
+  );
+
+typedef 
+VOID
+(EFIAPI * CLEAR_ERROR_STATUS) (
+  EFI_PEI_SERVICES      **PeiServices,
+//  SSA_BIOS_SERVICES_PPI *This,
+  VOID                  *This,
+  UINT8                 Socket,
+  UINT8                 Controller,
+  UINT8                 ChannelMask
+  );
+
+typedef 
+SSA_STATUS
+(EFIAPI * CLEAR_ERROR_COUNTER) (
+  EFI_PEI_SERVICES      **PeiServices,
+//  SSA_BIOS_SERVICES_PPI *This,
+  VOID                  *This,
+  UINT8                 Socket,
+  UINT8                 Controller,
+  UINT8                 Channel,
+  UINT8                 Counter
+  );
+
+typedef 
+UINT64
+(EFIAPI * GET_DQ_ERROR_STATUS) (
+  EFI_PEI_SERVICES      **PeiServices,
+//  SSA_BIOS_SERVICES_PPI *This,
+  VOID                  *This,
+  UINT8                 Socket,
+  UINT8                 Controller,
+  UINT8                 Channel
+  );
+
+typedef 
+UINT8
+(EFIAPI * GET_ECC_ERROR_STATUS) (
+  EFI_PEI_SERVICES      **PeiServices,
+//  SSA_BIOS_SERVICES_PPI *This,
+  VOID                  *This,
+  UINT8                 Socket,
+  UINT8                 Controller,
+  UINT8                 Channel
+  );
+
+typedef 
+SSA_STATUS
+(EFIAPI * SET_ERROR_COUNTER_MODE) (
+  EFI_PEI_SERVICES      **PeiServices,
+//  SSA_BIOS_SERVICES_PPI *This,
+  VOID                  *This,
+  UINT8                 Socket,
+  UINT8                 Controller,
+  UINT8                 Channel,
+  UINT8                 Counter,
+  COUNTER_MODE          CounterMode,
+  UINT32                ModeIndex
+  );
+
+typedef 
+ERROR_COUNT_32BITS
+(EFIAPI * GET_ERROR_COUNT) (
+  EFI_PEI_SERVICES      **PeiServices,
+//  SSA_BIOS_SERVICES_PPI *This,
+  VOID                  *This,
+  UINT8                 Socket,
+  UINT8                 Controller,
+  UINT8                 Channel,
+  UINT8                 Counter
+  );
+
+typedef 
+VOID
+(EFIAPI * SET_VALIDATION_BIT_MASK) (
+  EFI_PEI_SERVICES      **PeiServices,
+//  SSA_BIOS_SERVICES_PPI *This,
+  VOID                  *This,
+  UINT8                 Socket,
+  UINT8                 Controller,
+  UINT8                 Channel,
+  UINT64                DqMask,
+  UINT8                 EccMask
+  );
+
+typedef 
+VOID
+(EFIAPI * SET_VALIDATION_PHASE_MASK) (
+  EFI_PEI_SERVICES      **PeiServices,
+//  SSA_BIOS_SERVICES_PPI *This,
+  VOID                  *This,
+  UINT8                 Socket,
+  UINT8                 Controller,
+  UINT8                 Channel,
+  UINT8                 CachelineMask,
+  UINT8                 PhaseMask
+  );
+
+typedef 
+VOID
+(EFIAPI * RUN_POINT_TEST) (
+  EFI_PEI_SERVICES      **PeiServices,
+//  SSA_BIOS_SERVICES_PPI *This,
+  VOID                  *This,
+  UINT8                 Socket,
+  UINT8                 Controller,
+  VOID                  *TestParameters,
+  BOOLEAN               SkipSetup
+  );
+
+//
+// SSA BIOS Common Configuration
+//
+typedef struct _SSA_COMMON_CONFIG {
+  UINT32                        Revision;               ///< Incremented when a backwards compatible binary change is made to the PPI.
+  VOID                          *BiosData;              ///< Pointer to the BIOS data buffer.
+  READ_MEM                      ReadMem;                ///< Reads a variable-sized value from a memory mapped register using an absolute address. This function takes advantage of any caching implemented by BIOS.
+  WRITE_MEM                     WriteMem;               ///< Writes a variable-sized value to a memory mapped register using an absolute address. This function takes advantage of any caching implemented by BIOS.
+  READ_IO                       ReadIo;                 ///< Reads a variable-sized value from IO. This function takes advantage of any caching implemented by BIOS.
+  WRITE_IO                      WriteIo;                ///< Writes a variable-sized value to IO.
+  READ_PCI                      ReadPci;                ///< Reads a variable-sized value from a PCI config space register. This function takes advantage of any caching implemented by BIOS.
+  WRITE_PCI                     WritePci;               ///< Writes a variable-sized value to a PCI config space register. This function takes advantage of any caching implemented by BIOS.
+  GET_BASE_ADDRESS              GetBaseAddress;         ///< Gets a base address to be used in the different memory map or IO register access functions.
+  MALLOC                        Malloc;                 ///< Function used to dynamically allocate memory.
+  FREE                          Free;                   ///< Function used to release memory allocated using Malloc.
+  DEBUG_PRINT                   DebugPrint;             ///< Function used to output debug messages to the output logging device.
+} SSA_COMMON_CONFIG;
+
+//
+// SSA BIOS Memory Configuration
+//
+typedef struct _SSA_MEMORY_CONFIG {
+  UINT32                        Revision;               ///< Incremented when a backwards compatible binary change is made to the PPI.
+  VOID                          *MrcData;               ///< Pointer to the BIOS data buffer.
+  GET_SYSTEM_INFO               GetSystemInfo;          ///< Returns system information.
+  GET_MEM_VOLTAGE               GetMemVoltage;          ///< Returns the platform's memory voltage.
+  SET_MEM_VOLTAGE               SetMemVoltage;          ///< Sets the platform's memory voltage.
+  GET_MEM_TEMP                  GetMemTemp;             ///< Returns the DIMM's temperature.
+  RESTORE_MRS                   RestoreMrs;             ///< Restore BIOS default DRAM mode register value.
+  WRITE_MRS                     WriteMrs;               ///< Writes DRAM mode register.
+  READ_MRS                      ReadMrs;                ///< Reads DRAM mode register.
+  GET_DIMM_FROM_LOGICAL_RANK    GetDimmFromLogicalRank; ///< Return the DIMM number according to the logical rank number.
+  GET_DIMM_INFO                 GetDimmInfo;            ///< Returns DIMM information.
+  GET_RANK_IN_DIMM        	    GetRankInDimm;          ///< Return the number of ranks in a specific DIMM on a given controller.
+  GET_LOGICAL_RANK_BIT_MASK     GetLogicalRankBitMask;  ///< Return the logical rank bit mask of the channel.
+  GET_CHANNEL_BIT_MASK          GetChannelBitMask;      ///< Return the channel bit mask of the populated channels.
+  GET_CONTROLLER_BIT_MASK       GetControllerBitMask;   ///< Returns bitmask of available controllers on a given socket.
+  JEDEC_RESET                   JedecReset;             ///< Function used to reset a DIMM.
+  GET_MARGIN_PARAM_LIMITS       GetMarginParamLimits;   ///< Function returns the low side, high side range and required delay of a margin parameter.
+  OFFSET_MARGIN_PARAM           OffsetMarginParam;      ///< Function used to adjust a margin parameter.
+  SET_WDB_PATTERN               SetWdbPattern;          ///< Function used to set up WDB pattern.
+  SET_CADB_PATTERN              SetCadbPattern;         ///< Function used to set up CADB pattern.
+  CLEAR_ERROR_STATUS            ClearErrorStatus;       ///< Function used to clear the lane error status registers.
+  CLEAR_ERROR_COUNTER           ClearErrorCounter;      ///< Function used to clear the error counter register.
+  GET_DQ_ERROR_STATUS           GetDqErrorStatus;       ///< Function used to get the DQ lane error status.
+  GET_ECC_ERROR_STATUS          GetEccErrorStatus;      ///< Function used to get the ECC lane error status.
+  SET_ERROR_COUNTER_MODE        SetErrorCounterMode;    ///< Function used to clear the error counter register.
+  GET_ERROR_COUNT               GetErrorCount;          ///< Function used to get the error count value for a give channel and counter on a given controller.
+  SET_VALIDATION_BIT_MASK       SetValidationBitMask;   ///< Function used to set the lane validation mask for a give channel on a given controller. Only the lanes with the mask bit set will be checked for errors.
+  SET_VALIDATION_PHASE_MASK     SetValidationPhaseMask; ///< Function used to set the phase mask for a give channel on a given controller. Only the phases with the mask bit set will be checked for errors.
+  RUN_POINT_TEST                RunPointTest;           ///< Function used to run a point test.
+} SSA_MEMORY_CONFIG;
+
+///
+/// SSA BIOS Services Header
+///
+typedef struct _SSA_BIOS_HEADER {
+  UINT32                        Revision;               ///< Incremented when a backwards compatible binary change is made to the PPI.
+  SSA_COMMON_CONFIG             *SsaCommonConfig;       ///< Pointer to the SSA BIOS common functions.
+  SSA_MEMORY_CONFIG             *SsaMemoryConfig;       ///< Pointer to the SSA BIOS memory related functions.
+} SSA_BIOS_HEADER;
+
+///
+/// SSA BIOS Services PPI
+///
+typedef struct _SSA_BIOS_SERVICES_PPI {
+  SSA_BIOS_HEADER               SsaHeader;              ///< SSA BIOS Services Header.
+  SSA_COMMON_CONFIG             SsaCommonConfig;        ///< SSA BIOS common functions.
+  SSA_MEMORY_CONFIG             SsaMemoryConfig;        ///< SSA BIOS memory related functions.
+} SSA_BIOS_SERVICES_PPI;
+
+#pragma pack (pop)
+#endif // _MrcSsaServices_h_
diff --git a/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/AddrDecode/MrcHswMcAddrDecode.c b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/AddrDecode/MrcHswMcAddrDecode.c
new file mode 100644
index 0000000..57e87fb
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/AddrDecode/MrcHswMcAddrDecode.c
@@ -0,0 +1,1326 @@
+/**
+This file contains an 'Intel Peripheral Driver' and uniquely
+identified as "Intel Reference Module" and is
+licensed for Intel CPUs and chipsets under the terms of your
+license agreement with Intel or your vendor.  This file may
+be modified by the user, subject to additional terms of the
+license agreement.
+
+Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved.
+This software and associated documentation (if any) is furnished
+under a license and may only be used or copied in accordance
+with the terms of the license. Except as permitted by such
+license, no part of this software or documentation may be
+reproduced, stored in a retrieval system, or transmitted in any
+form or by any means without the express written consent of
+Intel Corporation.
+
+@file:
+  MrcHswMcAddrDecode.c
+
+@brief:
+  File to support address decoding and encoding
+
+**/
+/*
+
+This file defines functions that perform address decoding, reverse address
+decoding, configuration checking, and configuration printing:
+
+    hswult_mc_addr_decode_config_check() - Checks the values in the registers used
+        for DRAM address decoding for illegal or inconsistent programming.
+        It would be wise to call this function once before using the other
+        functions.  Once the configuration/register-programming passes the check,
+        the decode and/or encode functions may be called multiple times.
+
+    hswult_mc_addr_decode() - Decodes system addresses into DRAM addresses and is
+        equivalent to the address decoding performed inside the memory
+        controller.
+
+    hswult_mc_addr_encode() - Performs the reverse of hswult_mc_addr_decode().
+        Translates a DRAM address into a system address.
+
+    hswult_mc_addr_decode_config_info() - Prints to a sring information about the
+        configuration that can be determined from the registers involved in
+        address decoding.
+
+"System address" refers to the 39-bit address presented to the memory controller
+at the memory controller's interface to the IMPH.
+
+"DRAM address" refers to the physical memory location inside the DDR3 memory
+hierarchy:
+-Channel
+    |
+    +-DIMM
+        |
+        +-Rank
+            |
+            +-Bank
+                |
+                +-Row
+                    |
+                    +-Column
+
+This code was authored with the intention that it comply with the C99 spec.
+This file should be compiled with the -std=c99 command line option if GCC is
+used to compile.
+The checking, decoding, and encoding functions return the bool "false" if they
+fail and return the bool "true" if they succeed.  They also print an error
+message explaining the failure to a string for which memory must be allocated
+before calling the function.
+
+A reminder about the bit-widths of data types guaranteed by the C99 spec:
+    - unsigned long long - must be at least 64-bits
+    - unsigned long      - must be at least 32-bits
+    - unsigned           - must be at least 16-bits, but is often 32.
+                           The size will be the "natural" size for the platform
+                           architecture.
+
+A reminder about literals:
+    literals are sometimes assumed to be the "natural" size for the platform
+    architecture:
+
+    unsigned long long x = (0x1 << 63);
+
+    result is x = 0, not 0x8000000000000000.
+
+    Solution:
+
+    unsigned long long x = (((unsigned long long) 0x1) << 63);
+
+    Also note that literals that are not the "natural size" must be typed
+    with trailing letters. For example, 0x8000000000000000 must be specified as
+    0x8000000000000000ULL (note the "ULL" at the end for "unsigned long long").
+
+*/
+
+
+
+#include "MrcHswMcAddrDecode.h"
+
+// size of the hash mask field in the channel hash register
+#define HSW_MC_ADDR_CHANNEL_HASH_MASK_SIZE 14
+
+//
+// Bit-Masks used to remove or test register fields
+//
+#define HSW_MC_ADDR_TOLUD_MASK             0xFFF00000
+#define HSW_MC_ADDR_REMAP_MASK             0x0000007FFFF00000ULL
+#define HSW_MC_ADDR_CHAN_HASH_ENABLE_MASK  0x00800000
+
+// Mask used to add 1's to lower bits of REMAP_LIMIT register
+#define HSW_MC_ADDR_REMAP_LIMIT_LOWER_BITS_MASK 0x00000000000FFFFFULL
+
+// Useful number constants
+#define HSW_MC_256MB_AS_CL  (1 << 22)
+#define HSW_MC_512MB_AS_CL  (1 << 23)
+#define HSW_MC_1GB_AS_CL    (1 << 24)
+#define HSW_MC_2GB_AS_CL    (1 << 25)
+#define HSW_MC_4GB_AS_CL    (1 << 26)
+#define HSW_MC_8GB_AS_CL    (1 << 27)
+
+
+// global variable to control debug messages printed to standard out.
+BOOL g_hswult_mc_addr_debug_messages = FALSE;
+
+//
+// Functions to extract fields from the registers
+//
+
+static inline U64
+get_onec_as_cl (
+  U32 MAD_ZR
+  )
+{
+  return MrcOemMemoryLeftShiftU64 ((((U64) MAD_ZR) & 0x000000FFULL), 22); // [ 7: 0]=8-bits
+}
+
+static inline U64
+get_threec_as_cl (
+  U32 MAD_ZR
+  )
+{
+  return MrcOemMemoryLeftShiftU64 ((((U64) MAD_ZR) & 0x0000FF00ULL), 14); // [15: 8]=8-bits
+}
+
+static inline U64
+get_twobandc_as_cl (
+  U32 MAD_ZR
+  )
+{
+  return MrcOemMemoryLeftShiftU64 ((((U64) MAD_ZR) & 0x00FF0000ULL), 6); // [23:16]=8-bits
+}
+
+static inline U64
+get_bandc_as_cl (
+  U32 MAD_ZR
+  )
+{
+  return MrcOemMemoryRightShiftU64 ((((U64) MAD_ZR) & 0xFF000000ULL), 2); // [31:24]=8-bits
+}
+
+static inline U64
+get_dimm_a_size_as_cl (
+  U32 MAD_DIMM
+  )
+{
+  return MrcOemMemoryLeftShiftU64 ((((U64) MAD_DIMM) & 0x00FFULL), 22); // MAD_DIMM[ 7:0]*256MB >>6
+}
+
+static inline U64
+get_dimm_b_size_as_cl (
+  U32 MAD_DIMM
+  )
+{
+  return MrcOemMemoryLeftShiftU64 ((((U64) MAD_DIMM) & 0xFF00ULL), 14); // MAD_DIMM[15:8]*256MB >>6
+}
+
+static inline BOOL
+get_dimm_a_number_of_ranks (
+  U32 MAD_DIMM
+  )
+{
+  return (BOOL) ((MAD_DIMM >> 17) & 1); // TRUE = 2-ranks, FALSE = 1-rank
+}
+
+static inline BOOL
+get_dimm_b_number_of_ranks (
+  U32 MAD_DIMM
+  )
+{
+  return (BOOL) ((MAD_DIMM >> 18) & 1); // TRUE = 2-ranks, FALSE = 1-rank
+}
+
+static inline U64
+get_dimm_a_rank_size_as_cl (
+  U32 MAD_DIMM
+  )
+{
+  return MrcOemMemoryRightShiftU64 (get_dimm_a_size_as_cl(MAD_DIMM), ((U8) get_dimm_a_number_of_ranks(MAD_DIMM)));
+}
+
+static inline U64
+get_dimm_b_rank_size_as_cl (
+  U32 MAD_DIMM
+  )
+{
+  return MrcOemMemoryRightShiftU64 (get_dimm_b_size_as_cl(MAD_DIMM), ((U8) get_dimm_b_number_of_ranks(MAD_DIMM)));
+}
+
+static inline BOOL
+get_dimm_and_rank_intlv (
+  U32 MAD_DIMM
+  )
+{
+  return (BOOL) ((MAD_DIMM >> 21) & 1); // MAD_DIMM[21:21]
+}
+
+static inline BOOL
+get_high_order_intlv_mode (
+  U32 MAD_DIMM
+  )
+{
+  return (BOOL) ((MAD_DIMM >> 26) & 1); // MAD_DIMM[26:26]
+}
+
+static inline U16
+get_hori_addr (
+  U32 MAD_DIMM
+  )
+{
+  return (U16) ((MAD_DIMM >> 27) & 7); // MAD_DIMM[29:27]
+}
+
+static inline BOOL
+get_enhanced_intlv_mode (
+  U32 MAD_DIMM
+  )
+{
+  return (BOOL) ((MAD_DIMM >> 22) & 1); // MAD_DIMM[22:22]
+}
+
+static inline U16
+get_dimm_a_select (
+  U32 MAD_DIMM
+  )
+{
+  return (U16) ((MAD_DIMM >> 16) & 1);
+}
+
+static inline BOOL
+get_lpddr_mode (
+  U32 MAD_CHNL
+  )
+{
+  return (BOOL) (MAD_CHNL >> 10) & 1;
+}
+
+static inline U16
+get_dimm_a_width (
+  U32 MAD_CHNL,
+  U32 MAD_DIMM
+  )
+{
+  BOOL is_x16 = (BOOL) ((MAD_DIMM >> 19) & 1);
+  return is_x16 ? 16 : (get_lpddr_mode(MAD_CHNL) ? 32 : 8);
+}
+
+static inline U16
+get_dimm_b_width (
+  U32 MAD_CHNL,
+  U32 MAD_DIMM
+  )
+{
+  BOOL is_x16 = (BOOL) ((MAD_DIMM >> 20) & 1);
+  return is_x16 ? 16 : (get_lpddr_mode(MAD_CHNL) ? 32 : 8);
+}
+
+static inline U16
+get_dimm_a_num_col_bits (
+  U32 MAD_CHNL,
+  U32 MAD_DIMM
+  )
+{
+  U16 width;
+  U64 dimm_rank_size_as_cl;
+
+  if (!get_lpddr_mode(MAD_CHNL)) {
+    return 10; // Supported DDR3 DRAM organizations all have 10 column bits
+  }
+
+  // If we got past the above line, we are LPDDR
+
+  width                = get_dimm_a_width(MAD_CHNL, MAD_DIMM);
+  dimm_rank_size_as_cl = get_dimm_a_rank_size_as_cl(MAD_DIMM);
+  if (width == 16) {
+    return (dimm_rank_size_as_cl == HSW_MC_1GB_AS_CL) ? 10 : 11; // LPDDR x16 2Gb device has 10 col bits,
+                                                                 // the 4 and 8 Gb LPDDR x16s have 11 col bits.
+  }
+  // width == 32
+  return (dimm_rank_size_as_cl == HSW_MC_512MB_AS_CL) ? 9 : 10; // LPDDR x32 2Gb device has 9 col bits,
+                                                                // the 4 and 8 Gb LPDDR x32s have 10 col bits.
+}
+
+static inline U16
+get_dimm_b_num_col_bits (
+  U32 MAD_CHNL,
+  U32 MAD_DIMM
+  )
+{
+  U16 width;
+  U64 dimm_rank_size_as_cl;
+
+  if (!get_lpddr_mode(MAD_CHNL)) {
+    return 10; // Supported DDR3 DRAM organizations all have 10 column bits
+  }
+
+  // If we got past the above line, we are LPDDR
+
+  width                = get_dimm_b_width(MAD_CHNL, MAD_DIMM);
+  dimm_rank_size_as_cl = get_dimm_b_rank_size_as_cl(MAD_DIMM);
+  if (width == 16) {
+    return (dimm_rank_size_as_cl == HSW_MC_1GB_AS_CL) ? 10 : 11; // LPDDR x16 2Gb device has 10 col bits,
+                                                                 // the 4 and 8 Gb LPDDR x16s have 11 col bits.
+  }
+  // width == 32
+  return (dimm_rank_size_as_cl == HSW_MC_512MB_AS_CL) ? 9 : 10; // LPDDR x32 2Gb device has 9 col bits,
+                                                                // the 4 and 8 Gb LPDDR x32s have 10 col bits.
+}
+
+static inline U16
+get_ch_hash_lsb_mask_bit (
+  U32 CHANNEL_HASH
+  )
+{
+  return (CHANNEL_HASH >> 21) & 3;
+}
+
+static inline U16
+get_ch_hash_mask (
+  U32 CHANNEL_HASH
+  )
+{
+  return CHANNEL_HASH & 0x03FFF;
+}
+
+static inline BOOL
+get_stacked_mode (
+  U32 MAD_CHNL
+  )
+{
+  return (BOOL) ((MAD_CHNL >> 6) & 1);
+}
+
+static inline U16
+get_stacked_encoding (
+  U32 MAD_CHNL
+  )
+{
+  return (U16) (MAD_CHNL >> 7) & 7;
+}
+
+//
+// Functions to aid in common tasks
+//
+
+// convert a cache-line address to a system address
+static inline U64
+cl_to_sys (
+  U64 cache_line
+  )
+{
+  return MrcOemMemoryLeftShiftU64 (cache_line, 6);
+}
+
+// Channel conversion functions. For logical channels: 0=A, 1=B.
+static inline U16
+logical_to_physical_chan (
+  U32 MAD_CHNL,
+  U16 logical_chan
+  )
+{
+  return ((U16) ((MAD_CHNL >> (logical_chan << 1)) & 0x3));
+}
+
+static inline U16
+physical_to_logical_chan (
+  U32 MAD_CHNL,
+  U16 physical_chan
+  )
+{
+  return ((((U16) (MAD_CHNL & 3)) == physical_chan) ? 0 : 1); // 0=A, 1=B
+}
+
+// Function for decode of stacked channel debug feature
+static inline U64
+get_stacked_memory_size (
+  U16 stacked_encoding
+  )
+{
+  return MrcOemMemoryLeftShiftU64 (0x00400000ULL, (U8) stacked_encoding); // 1 << 28 + stacked_encoding - 6 for the cachline align
+}
+
+
+/**
+@brief
+  Address decode function
+  Converts system address to DRAM address
+
+  @param[in]      sys_addr - the 39-bit system address to convert
+  @param[in, out] p_is_tcm - is the transaction to sys_addr "traffic class for the manageability engine"
+  @param[in]      TOLUD - memory register
+  @param[in]      REMAP_BASE - memory register
+  @param[in]      REMAP_LIMIT - memory register
+  @param[in]      CHANNEL_HASH - memory register
+  @param[in]      MAD_ZR - memory register
+  @param[in]      MAD_CHNL - memory register
+  @param[in]      MAD_DIMM_ch0 - memory register
+  @param[in]      MAD_DIMM_ch1 - memory register
+  @param[in]      MAD_DIMM_ch2 - memory register
+  @param[out]     p_chan - channel sys_addr decodes to
+  @param[out]     p_dimm - DIMM sys_addr decodes to
+  @param[out]     p_rank - rank sys_addr decodes to
+  @param[out]     p_bank - bank sys_addr decodes to
+  @param[out]     p_row - row sys_addr decodes to
+  @param[out]     p_col - column sys_addr decodes to.
+
+  @retval True if successful.
+
+**/
+BOOL
+MrcHswDecode (
+  IN     U64  sys_addr,
+  IN OUT BOOL *p_is_tcm,
+  IN     U32  TOLUD,
+  IN     U64  REMAP_BASE,
+  IN     U64  REMAP_LIMIT,
+  IN     U32  CHANNEL_HASH,
+  IN     U32  MAD_ZR,
+  IN     U32  MAD_CHNL,
+  IN     U32  MAD_DIMM_ch0,
+  IN     U32  MAD_DIMM_ch1,
+  IN     U32  MAD_DIMM_ch2,
+  OUT    U16  *p_chan,
+  OUT    U16  *p_dimm,
+  OUT    U16  *p_rank,
+  OUT    U16  *p_bank,
+  OUT    U16  *p_row,
+  OUT    U16  *p_col
+  )
+{
+  // used to hold the address after the remap zone has been applied to the system address
+  U64  remap_addr; // full address
+  U64  remap_line; // cache-line address
+  // used to hold fields from MAD_ZR, adjusted to cache-line address
+  U64  onec;     // 1 * C
+  U64  threec;   // 3 * C       - top of Zone 0
+  U64  twobandc; // (2 * B) + C - top of Zone 1
+  U64  bandc;    // (B + C)
+  // Make a MAD_DIMM array for easy access
+  U32  MAD_DIMM[3];
+  U32  chan_a_mad_dimm; // channel A's MAD_DIMM register
+  U64  gap_limit; // MMIO Gap Limit
+  U64  tom; // Top Of Memory (cache-line address)
+  U16  lsb_mask_bit; // LsbMaskBit field from CHANNEL_HASH register
+  U16  hash_mask; // channel hash mask from CHANNEL_HASH register
+  U16  hash_line; // lower bits of remap_line with hash_mask applied
+  U16  i; // loop counter
+  U64  chan_line; // channel address space (cache-line)
+  U16  chan_select; // 0 = Channel A, 1 = Channel B
+  U32  selected_mad_dimm; // MAD_DIMM for the selected channel
+  BOOL is_lpddr = get_lpddr_mode(MAD_CHNL); // LPDDR or DDR3
+  U16  num_col_bits; // The number of column address bits the DIMM has.
+  U64  dimm_a_size; // sizes of the DIMMs on the channel in cache-lines
+  U64  dimm_b_size;
+  BOOL dimm_and_rank_interleaving; // modes for the selected channel
+  BOOL high_order_rank_interleave;
+  BOOL enhanced_interleave_mode;
+  U16  hori_addr; // bits to use from address for HORI
+  U64  dimm_line; // DIMM address space (cache-line)
+  U16  dimm_select; // 0 = DIMM A, 1 = DIMM B
+  U32  dimm_size; // size of selected DIMM (cache-lines)
+  BOOL dual_rank; // number of ranks on selected DIMM
+  // channel stacking variables
+  BOOL stacked_mode;
+  U64  stacked_size;
+  // temporary values for bit masking and shifting
+  U64  row_mask;
+  U16  rank_bit_shift;
+
+  MAD_DIMM[0] = MAD_DIMM_ch0;
+  MAD_DIMM[1] = MAD_DIMM_ch1;
+  MAD_DIMM[2] = MAD_DIMM_ch2;
+
+  // zero out unused register bits
+  TOLUD       &= HSW_MC_ADDR_TOLUD_MASK;
+  REMAP_BASE  &= HSW_MC_ADDR_REMAP_MASK;
+  REMAP_LIMIT &= HSW_MC_ADDR_REMAP_MASK;
+
+  // Assume lower bits of REMAP_LIMIT are all 1's.
+  REMAP_LIMIT |= HSW_MC_ADDR_REMAP_LIMIT_LOWER_BITS_MASK;
+
+  //
+  // Register field values are in 256MB granularity.
+  // They are stored here adjusted to cache-line granularity.
+  //
+  onec     = get_onec_as_cl (MAD_ZR);
+  threec   = get_threec_as_cl (MAD_ZR);
+  twobandc = get_twobandc_as_cl (MAD_ZR);
+  bandc    = get_bandc_as_cl (MAD_ZR);
+
+  //
+  // TOM is not directly available in a register. It will be computed by
+  // finding the channel index of channel A, then adding the two DIMM
+  // capacities of that channel together. Technically, this is only needed to
+  // check that the system address is not beyond the amount of memory
+  // available.
+  //
+
+  // Overflow check MAD_DIMM
+  if ((MAD_CHNL & 0x3) > 2) {
+    return FALSE;
+  }
+  chan_a_mad_dimm = MAD_DIMM[MAD_CHNL & 0x3];
+  tom  = get_dimm_a_size_as_cl(chan_a_mad_dimm);
+  tom += get_dimm_b_size_as_cl(chan_a_mad_dimm);
+  tom += bandc;
+
+  // remap the address if it is not a TCM transaction and falls inside the remap range
+  remap_addr = sys_addr;
+  if (REMAP_LIMIT > REMAP_BASE) { // check for remap region being enabled
+    gap_limit = ((U64) TOLUD) + REMAP_LIMIT - REMAP_BASE;
+    //
+    // check for address falling in remap region
+    //
+    if ((sys_addr >= REMAP_BASE) && (sys_addr <= REMAP_LIMIT)) { // REMAP_LIMIT is now inclusive
+      if (*p_is_tcm) {
+        if (sys_addr >= cl_to_sys(tom)) {
+          // transaction to sys_addr should not have been TCM.
+          *p_is_tcm = FALSE;
+          return FALSE;
+        }
+      } else {
+        //
+        // The address hit the remap region, so remap the address from the remap
+        // source region (REMAP_BASE to REMAP_LIMIT) to the remap target region
+        // (TOLUD to size-of-gap).
+        //
+        remap_addr -= REMAP_BASE;
+        remap_addr += ((U64) TOLUD);
+      }
+    } else if ((sys_addr >= ((U64) TOLUD)) &&
+                 (sys_addr <= gap_limit                   )) { // check for address falling in MMIO gap created by remap region
+      // transaction to sys_addr should not have been TCM.
+      *p_is_tcm = FALSE;
+      return FALSE;
+    } else {
+      //
+      // transaction to sys_addr should not have been TCM, but the memory
+      // controller will process the request anyway without any problems.
+      //
+      *p_is_tcm = FALSE;
+    }
+  } else {
+    // transaction to sys_addr should not have been TCM, but the memory
+    // controller will process the request anyway without any problems.
+    //
+    *p_is_tcm = FALSE;
+  }
+
+
+  // from now on we will work on cache-line addresses
+  remap_line = MrcOemMemoryRightShiftU64 (remap_addr, 6); // shift off intra-cache-line bits
+
+
+  stacked_mode = get_stacked_mode (MAD_CHNL);
+
+  if (stacked_mode) {
+    //
+    // In stacked mode, check that remapped address is below TOM.
+    //
+    if (remap_line >= tom) {
+      return FALSE;
+    }
+
+    stacked_size = get_stacked_memory_size (get_stacked_encoding(MAD_CHNL));
+
+    chan_select = (remap_line < stacked_size) ? 0 : 1;
+
+    chan_line = remap_line;
+
+
+    chan_select = (remap_line < stacked_size) ? 0 : 1;
+    chan_line = remap_line;
+
+    // If this is channel 1 in stacked mode, then we need to subtract out the channel size (clear
+    // the stacked mode bit)
+    //
+    if (chan_select == 1) {
+      chan_line = chan_line - stacked_size;
+    }
+  } else if (remap_line < threec) { // Zone 0
+    return FALSE;
+  } else if (remap_line < twobandc) { // Zone 1
+    // Determine if the channel hash feature is being used
+    if (CHANNEL_HASH & HSW_MC_ADDR_CHAN_HASH_ENABLE_MASK) { // test enable bit
+      lsb_mask_bit = get_ch_hash_lsb_mask_bit (CHANNEL_HASH);
+      hash_mask = get_ch_hash_mask (CHANNEL_HASH);
+      hash_mask = hash_mask | (1 << lsb_mask_bit); // force the selected lsb_mask_bit to be on
+
+      hash_line = ((U16) remap_line) & hash_mask; // get the bits to XOR for the hash
+      //
+      // Produce chan_select by XORing together all of the bits of hash_line.
+      //
+      // I don't know of a single instruction to do this, so an unrollable
+      // loop will be used.
+      //
+      chan_select = 0;
+      for (i = 0 ; i < HSW_MC_ADDR_CHANNEL_HASH_MASK_SIZE ; i++) {
+        chan_select = chan_select ^ (hash_line >> i);
+      }
+      chan_select = chan_select & 1;
+      //
+      // sys_addr 6 will be shifted off to produce the channel address, so it must
+      // be preserved if it wasn't used in the hash.  This is done by moving it to
+      // the position indicated by lsb_mask_bit.
+      //
+      remap_line = remap_line & (~MrcOemMemoryLeftShiftU64 (0x0000000000000001ULL, (U8) lsb_mask_bit)); // zero out lsb_mask_bit
+      remap_line = remap_line | MrcOemMemoryLeftShiftU64 ((remap_line & 1), (U8) lsb_mask_bit); // OR in bit 6 to lsb_mask_bit position
+    } else {
+      chan_select = (U16) (remap_line & 1); // remap_addr[6:6]
+    }
+    chan_line = MrcOemMemoryRightShiftU64 ((remap_line - onec), 1); // right shift by 1 divides by 2
+  } else if (remap_line < tom) { // Zone 2
+    chan_select = 0; // Channel A
+    chan_line = remap_line - bandc;
+  } else { // address was above memory capacity
+    return FALSE;
+  }
+
+  // obtain the physical channel index
+  *p_chan = logical_to_physical_chan (MAD_CHNL, chan_select);
+
+  // Overflow check *p_chan
+  if (*p_chan > 2) {
+    return FALSE;
+  }
+
+  // get the register for the channel we're using
+  selected_mad_dimm = MAD_DIMM[*p_chan];
+
+  // Find the DIMM sizes on our selected channel. adjust to cache-line granularity
+  dimm_a_size = get_dimm_a_size_as_cl (selected_mad_dimm);
+  dimm_b_size = get_dimm_b_size_as_cl (selected_mad_dimm);
+
+  // determine if we are doing DIMM and Rank interleaving
+  dimm_and_rank_interleaving = get_dimm_and_rank_intlv (selected_mad_dimm);
+
+  // determine if we are doing high order rank interleave
+  high_order_rank_interleave = get_high_order_intlv_mode (selected_mad_dimm);
+
+  // determine if we are doing Enhanced Interleave Mode (EIM) (XOR rank & bank bits)
+  enhanced_interleave_mode   = get_enhanced_intlv_mode (selected_mad_dimm);
+
+  // DIMM address calculation
+
+  // DIMMs are interleaved for both dimm_and_rank_interleaving and high_order_rank_interleave modes.
+  if (dimm_and_rank_interleaving || high_order_rank_interleave) {
+    if (chan_line < MrcOemMemoryLeftShiftU64 (dimm_b_size, 1)) { // Range 0 limit = 2 * dimm_b_size
+      // 2-way DIMM interleave. Channel address [15:15] is used to select DIMM
+      dimm_select = (U16) (MrcOemMemoryRightShiftU64 (chan_line, 9) & 1);
+
+      // DIMM address is channel address with the interleave bit (15) removed
+      dimm_line = (MrcOemMemoryRightShiftU64 (chan_line, 1) & (~((U64) 0x01FFULL))) |
+                  (chan_line & ((U64) 0x01FFULL));
+    } else if (chan_line < (dimm_a_size + dimm_b_size)) { // Range 1 limit
+      // No DIMM interleave. DIMM is the largest DIMM: DIMM A.
+      dimm_select = 0;
+
+      // DIMM address is channel address with DIMM B's contribution removed
+      dimm_line = chan_line - dimm_b_size;
+    } else {
+      return FALSE;
+    }
+  } else { // no DIMM and Rank interleaving
+    dimm_line = chan_line;
+    if (chan_line < dimm_a_size) { // Range 0 limit = dimm_a_size
+      // No DIMM interleave. DIMM is the largest DIMM: DIMM A.
+      dimm_select = 0;
+
+      // DIMM address is channel address
+    } else if (chan_line < (dimm_a_size + dimm_b_size)) { // Range 1 limit
+      // No DIMM interleave. DIMM is the smallest DIMM: DIMM B.
+      dimm_select = 1;
+
+      // DIMM address is channel address with dimm_a_size removed.
+      dimm_line -= dimm_a_size;
+    } else {
+      return FALSE;
+    }
+  }
+
+  // get the physical DIMM index
+  *p_dimm = dimm_select ^ get_dimm_a_select (selected_mad_dimm);
+
+  // get DIMM info
+  dimm_size = (U32) (dimm_select ? dimm_b_size : dimm_a_size);
+  dual_rank =  dimm_select ? get_dimm_b_number_of_ranks (selected_mad_dimm):
+                             get_dimm_a_number_of_ranks (selected_mad_dimm);
+
+  num_col_bits = dimm_select ? get_dimm_b_num_col_bits (MAD_CHNL, selected_mad_dimm) :
+                               get_dimm_a_num_col_bits (MAD_CHNL, selected_mad_dimm);
+
+
+  // DRAM address calculation
+
+  //
+  // Grab the column first (because with HSW-ULT we will shift dimm_line up or
+  // down by 1 based on column size).
+  //
+  // column is DimmAddress[12:3] when 10 column bits are present. [13:3] and
+  // [11:3] for 11 and 9 column bits, respectively.
+  //
+  *p_col = (U16) MrcOemMemoryLeftShiftU64 (dimm_line, 3);
+
+  // The low-order intra-cache-line bits must be added back in.
+  *p_col = *p_col | ((U16) (MrcOemMemoryRightShiftU64 (sys_addr, 3) & 0x7ULL));
+
+  // We picked up extra high-order bits from dimm_line.
+  // Mask off the bits above the column range.
+  //
+  *p_col = *p_col & ((1 << num_col_bits) - 1);
+
+  // Now compute Rank, Bank, and Row
+
+  // The column address bits make up the bottom of the DIMM address space.
+  // With the addition of LPDDR to HSW-ULT, the number column address bits may
+  // change from the standard 10 with DDR3 to 9 or 11 with some of the LPDDR
+  // organizations.  The entire DIMM address space can be shifted up or down
+  // with this change, then the bank, rank, and row bits can be extracted as
+  // with the standard 10 column bits.
+  //
+  if (num_col_bits == 9) {
+    dimm_line = MrcOemMemoryLeftShiftU64 (dimm_line, 1); // Shift up as though there were 10.
+  }
+
+  if (num_col_bits == 11) {
+    dimm_line = MrcOemMemoryRightShiftU64 (dimm_line, 1); // Shift down as though there were 10.
+  }
+
+  // high_order_rank_interleave is mutually exclusive with dimm_and_rank_interleaving
+  if (dual_rank && high_order_rank_interleave) {
+    //
+    // Specify which address bit 20-27 to use as the rank interleave bit
+    //  000 = bit 20, 001 = bit 21, ..., 111 = bit 27
+    //
+    hori_addr = get_hori_addr (selected_mad_dimm);
+
+    // Rank is selected by the HORI address field, which chooses a bit from DimmAddress[27:20]
+    *p_rank = (U16) (MrcOemMemoryRightShiftU64 (dimm_line, (U8) (hori_addr + 20 - 6)) & 1);
+
+    // Bank in HORI mode is just like no-rank-interleave
+
+    // bank = DimmAddress[15:13]
+    *p_bank = (U16) (MrcOemMemoryRightShiftU64 (dimm_line, 7) & 7);
+
+    if (enhanced_interleave_mode) {
+      // bank = DimmAddress[15:13] ^ DimmAddress[18:16]
+      *p_bank = *p_bank ^ ((U16) (MrcOemMemoryRightShiftU64 (dimm_line, 10) & 7));
+    }
+
+    // row[15:11] is always DimmAddress[32:28]
+    // row[3:0] is always DimmAddress[19:16]
+    // row[11:4] must make room for the rank bit, wherever hori_addr puts it.
+
+    // Get all row bits plus the rank bit somewhere in there.
+    *p_row = (U16) MrcOemMemoryRightShiftU64 (dimm_line, 10);
+
+    // Create a mask with 1's in the position of the row bits below the rank bit
+    row_mask = (1 << (hori_addr + 4)) - 1;
+
+    // Shift down the upper bits by one to remove the rank bit and recombine with the lower bits
+    *p_row = ((*p_row >> 1) & ((U16) (~row_mask))) | (*p_row & ((U16) row_mask));
+
+    // Mask away any row bits too large for the size of DIMM (only the number of row bits changes with DIMM size).
+    *p_row = *p_row & ((U16) ((dimm_size >> 10) - 1));
+  } else if (dual_rank && dimm_and_rank_interleaving) {
+    if (enhanced_interleave_mode) {
+      //
+      // rank = DimmAddress[15:15] XOR DimmAddress[19:19]
+      // bank = {DimmAddress[16:16],DimmAddress[14:13]} XOR
+      //        {DimmAddress[20:20],DimmAddress[18:17]}
+      //
+      // We can just modify the bank rank bits in the dimm_line address.
+      // The rest of the bits will not be affected, neither will further
+      // operations involving dimm_line.
+      //
+      dimm_line = dimm_line ^ (MrcOemMemoryRightShiftU64 (dimm_line, 4) & 0x780ULL);
+    }
+
+    // rank = DimmAddress[15:15]
+    *p_rank = (U16) (MrcOemMemoryRightShiftU64 (dimm_line, 9) & 1);
+
+    // bank = {DimmAddress[16:16],DimmAddress[14:13]}
+    *p_bank = (U16) ((MrcOemMemoryRightShiftU64 (dimm_line, 8) & 4) | (MrcOemMemoryRightShiftU64 (dimm_line, 7) & 3));
+
+    // row = DimmAddress[32..28:17] depending on DIMM size.
+    *p_row = (U16) MrcOemMemoryRightShiftU64 (dimm_line, 11);
+
+    // Mask away any row bits too large for the size of DIMM (only the number of row bits changes with DIMM size).
+    *p_row = *p_row & ((U16) ((dimm_size >> 10) - 1));
+  } else { // single rank or no rank interleaving
+    // for single-rank DIMM, bits above row bits should all be zero
+    row_mask = 0xFFFFFFFFFFFFFC00ULL;
+
+    // rank = one of DimmAddress[32..28] depending on DIMM size, or 0 for single rank.
+    *p_rank = 0;
+    if (dual_rank) {
+      //
+      // When using 11 column bits the HSW ULT supports only 4Gb/8Gb x16 LPDDR devices.
+      // Meaning rank size can be 2GB/4GB, hence since we are in dual rank DIMM, DIMM size is 4GB/8GB.
+      // LPDDR only supports 14/15 row address bits, for 2GB/4GB ranks respectively.
+      // But, DDR3 calculation (always 10 col bits) 2GB/4GB ranks (4GB/8GB DIMMs) uses 15/16 row address bits respectively.
+      // So, we change dimm_size as if we calculate DDR3 to avoid getting 16 row bits and shifted rank position.
+      //
+      if (is_lpddr && (num_col_bits == 11)) {
+        switch( dimm_size ) { // remember: dimm_size is in cache-lines
+          case HSW_MC_4GB_AS_CL:
+            dimm_size = HSW_MC_2GB_AS_CL;
+            break;
+          case HSW_MC_8GB_AS_CL:
+            dimm_size = HSW_MC_4GB_AS_CL;
+            break;
+          default:
+            return FALSE;
+        }
+      }
+      //
+      // When using 9column bits the HSW ULT supports only 2Gb x32 LPDDR devices.
+      // Meaning rank size can be 512MGB, hence since we are in dual rank DIMM, DIMM size is 1GB.
+      // LPDDR only supports 14 row address bits, for 512MB ranks.
+      // But, DDR3 calculation (always 10 col bits) 512MB ranks (1GB DIMMs) uses 13 row address bits.
+      // So, we change dimm_size as if we calculate DDR3 to avoid getting 13 row bits and shifted rank position.
+      //
+      if (is_lpddr && (num_col_bits == 9)) {
+        switch( dimm_size ) { // remember: dimm_size is in cache-lines
+          case HSW_MC_1GB_AS_CL:
+            dimm_size = HSW_MC_2GB_AS_CL;
+            break;
+          default:
+            return FALSE;
+        }
+      }
+
+      switch( dimm_size ) // remember: dimm_size is in cache-lines
+      {
+          case HSW_MC_256MB_AS_CL:
+            return FALSE;
+          case HSW_MC_512MB_AS_CL:
+            rank_bit_shift = 22;
+            row_mask = 0x003FFC00ULL;
+            break;
+          case HSW_MC_1GB_AS_CL:
+            rank_bit_shift = 23;
+            row_mask = 0x007FFC00ULL;
+            break;
+          case HSW_MC_2GB_AS_CL:
+            rank_bit_shift = 24;
+            row_mask = 0x00FFFC00ULL;
+            break;
+          case HSW_MC_4GB_AS_CL:
+            rank_bit_shift = 25;
+            row_mask = 0x01FFFC00ULL;
+            break;
+          case HSW_MC_8GB_AS_CL:
+            rank_bit_shift = 26;
+            row_mask = 0x03FFFC00ULL;
+            break;
+          default:
+            return FALSE;
+      }
+      *p_rank = (U16) MrcOemMemoryRightShiftU64 (dimm_line, (U8) rank_bit_shift) & 1;
+    }
+
+    // bank = DimmAddress[15:13]
+    *p_bank = (U16) (MrcOemMemoryRightShiftU64 (dimm_line, 7) & 7);
+
+    if( enhanced_interleave_mode ) {
+      // bank = DimmAddress[15:13] ^ DimmAddress[18:16]
+      *p_bank = *p_bank ^ ((U16) (MrcOemMemoryRightShiftU64 (dimm_line, 10) & 7));
+    }
+
+    // row = DimmAddress[31..27:16] depending on DIMM size. mask already prepared.
+    row_mask = row_mask & dimm_line; // use row_mask to hold row because it is "U64"
+    row_mask = MrcOemMemoryRightShiftU64 (row_mask, 10); // shift off bank and col bits
+    *p_row = (U16) row_mask;
+  }
+
+  return TRUE;
+}
+
+
+/**
+@brief
+  Address encode function (reverse address decode)
+  DRAM address to system address conversion
+
+  @param[in]     p_chan - channel sys_addr to encode
+  @param[in]     p_dimm - DIMM sys_addr to encode
+  @param[in]     p_rank - rank sys_addr to encode
+  @param[in]     p_bank - bank sys_addr to encode
+  @param[in]     p_row - row sys_addr to encode
+  @param[in]     p_col - column sys_addr to encode. Note: The architecture is limited to
+                         half-cache-line granularity for burst order. Therefore the last
+                         two bits of the column are ignored.
+  @param[in]      TOLUD - memory register
+  @param[in]      REMAP_BASE - memory register
+  @param[in]      REMAP_LIMIT - memory register
+  @param[in]      CHANNEL_HASH - memory register
+  @param[in]      MAD_ZR - memory register
+  @param[in]      MAD_CHNL - memory register
+  @param[in]      MAD_DIMM_ch0 - memory register
+  @param[in]      MAD_DIMM_ch1 - memory register
+  @param[in]      MAD_DIMM_ch2 - memory register
+  @param[out]     sys_addr - the 39-bit system address convert to
+  @param[in, out] p_is_tcm - is the transaction to sys_addr "traffic class for the manageability engine"
+
+  @retval True if successful.
+
+**/
+BOOL
+MrcHswEncode (
+  IN  U16     chan,
+  IN  U16     dimm,
+  IN  U16     rank,
+  IN  U16     bank,
+  IN  U16     row,
+  IN  U16     col,
+  IN  U32     TOLUD,
+  IN  U64     REMAP_BASE,
+  IN  U64     REMAP_LIMIT,
+  IN  U32     CHANNEL_HASH,
+  IN  U32     MAD_ZR,
+  IN  U32     MAD_CHNL,
+  IN  U32     MAD_DIMM_ch0,
+  IN  U32     MAD_DIMM_ch1,
+  IN  U32     MAD_DIMM_ch2,
+  OUT U64     *p_sys_addr,
+  IN OUT BOOL *p_is_tcm
+  )
+{
+  U32  MAD_DIMM; // MAD_DIMM register for chosen channel
+  U64  dimm_select; // DIMM A=0, B=1
+  U64  dimm_size; // size of selected DIMM
+  BOOL dual_rank; // number of ranks on selected DIMM
+  U64  bit_above_row; // one-hot bit to mark the size of the row address
+  BOOL dimm_and_rank_interleaving; // modes for the selected channel
+  BOOL high_order_rank_interleave;
+  BOOL enhanced_interleave_mode;
+  U16  hori_addr; // bits to use from address for HORI
+  U16  row_mask; // used to insert rank bit inbetween row bits in HORI mode
+  U64  dimm_line; // DIMM address space (cache-line)
+  U64  chan_line; // Channel address space (cache-line)
+  U16  num_col_bits; // The number of column address bits the DIMM has.
+  // sizes of the DIMMs on the channel (cache-line)
+  U64  dimm_a_size;
+  U64  dimm_b_size;
+  U16  chan_select; // 0 = Channel A, 1 = Channel B
+  // MAD_ZR register fields
+  U64  bandc;    // (B + C)
+  // address before reverse decoding the remap region
+  U64  remap_line; // cache-line
+  U64  remap_addr; // full address
+  // stacked channel variables
+  BOOL stacked_mode;
+  U16  stacked_encoding;
+  U64  stacked_size;
+  U16  lsb_mask_bit; // LsbMaskBit field from CHANNEL_HASH register
+  U16  hash_mask; // channel hash mask from CHANNEL_HASH register
+  U16  hash_line; // lower bits of remap_line with hash_mask applied
+  U16  hash_bit; // bit that gets destroyed in forward decode
+  U16  i; // loop counter
+  U64  top_of_remaped_mem; // used for reverse decode of remap region
+
+  // perform some checks on the inputs
+
+  // illegal channel check
+  if (chan & ~((U16) 1)) {
+    return FALSE;
+  }
+
+  // select our MAD_DIMM register. Ignore channel 2
+  MAD_DIMM = chan ? MAD_DIMM_ch1 : MAD_DIMM_ch0;
+
+  // check for too high of a DIMM index
+  if (dimm & ~((U16) 1)) {
+    return FALSE;
+  }
+
+  // is it DIMM A or B? A=0, B=1
+  dimm_select = (U64) (dimm ^ get_dimm_a_select(MAD_DIMM));
+
+  // get DIMM size
+  dimm_size = dimm_select ? get_dimm_b_size_as_cl (MAD_DIMM) : get_dimm_a_size_as_cl (MAD_DIMM);
+
+  // check if DIMM slot is populated
+  if (dimm_size == 0) {
+    return FALSE;
+  }
+
+  // check for too high of a rank index
+  if (rank & ~((U16) 1)) {
+    return FALSE;
+  }
+
+  // get number of ranks on DIMM
+  dual_rank = dimm_select ? get_dimm_b_number_of_ranks (MAD_DIMM) : get_dimm_a_number_of_ranks (MAD_DIMM);
+
+  // check that rank exists on DIMM
+  if (rank && !dual_rank) {
+    return FALSE;
+  }
+
+  // check for too high of a bank index
+  if (bank & ~((U16) 0x7)) {
+    return FALSE;
+  }
+
+  num_col_bits = dimm_select ? get_dimm_b_num_col_bits (MAD_CHNL, MAD_DIMM) :
+                               get_dimm_a_num_col_bits (MAD_CHNL, MAD_DIMM);
+
+  // Set a bit in a position that is one bit higher than the highest row bit
+  // in the DIMM address space (cacheline address).
+  //
+  //  Most-Significant-Bits of Supported DRAM Chip Organizations (num bits - 1):
+  //
+  //  Type   Config  Device-Size  Row  Col  Bank  Rank-Size
+  //  -----  ------  -----------  ---  ---  ----  ---------
+  //  DDR3   x8      512 Mbit     12   9    2     512 MByte
+  //  DDR3   x8      1 Gbit       13   9    2     1 GByte
+  //  DDR3   x8      2 Gbit       14   9    2     2 GByte
+  //  DDR3   x8      4 Gbit       15   9    2     4 GByte
+  //  DDR3   x16     512 Mbit     11   9    2     256 MByte
+  //  DDR3   x16     1 Gbit       12   9    2     512 MByte
+  //  DDR3   x16     2 Gbit       13   9    2     1 GByte
+  //  DDR3   x16     4 Gbit       14   9    2     2 GByte
+  //  LPDDR  x16     2 Gbit       13   9    2     1 GByte
+  //  LPDDR  x16     4 Gbit       13   10   2     2 GByte
+  //  LPDDR  x16     8 Gbit       14   10   2     4 GByte
+  //  LPDDR  x32     2 Gbit       13   8    2     512 MByte
+  //  LPDDR  x32     4 Gbit       13   9    2     1 GByte
+  //  LPDDR  x32     8 Gbit       14   9    2     2 GByte
+  //
+  // dimm size (GB) | dimm_size (cache-line)
+  // ---------------+-----------------------
+  //        8 GB    |        1<<27
+  //        4 GB    |        1<<26
+  //        2 GB    |        1<<25
+  //        1 GB    |        1<<24
+  //        0.5 GB  |        1<<23
+  //        0.25 GB |        1<<22
+  //
+  bit_above_row = MrcOemMemoryRightShiftU64 (dimm_size, (U8) (num_col_bits + ((U16) dual_rank)));
+
+  // Check for unexpected high-order row bits
+  if (row & ~(((U32) bit_above_row) - 1)) {
+    return FALSE;
+  }
+
+  // check for unexpected high-order column bits
+  if (col & ~((((U16) 1) << num_col_bits) - 1)) {
+    return FALSE;
+  }
+
+
+  //
+  // Done with checking. Now reverse decode the address.
+  //
+
+  // determine if we are doing DIMM and Rank interleaving
+  dimm_and_rank_interleaving = get_dimm_and_rank_intlv (MAD_DIMM);
+
+  // determine if we are doing high order rank interleave
+  high_order_rank_interleave = get_high_order_intlv_mode (MAD_DIMM);
+
+  // determine if we are doing Enhanced Interleave Mode (EIM) (XOR rank & bank bits)
+  enhanced_interleave_mode   = get_enhanced_intlv_mode (MAD_DIMM);
+
+  // start building the DIMM Address Space (as a cache-line address)
+
+  dimm_line = 0x0ULL;
+
+  // build the rank, bank, and row parts of the DIMM space address
+
+  if (dual_rank && high_order_rank_interleave) {
+    hori_addr = get_hori_addr (MAD_DIMM);
+
+    // Put the row part of the address into the dimm address
+
+    // Create a mask with all 1's in the positions of the row bits below the rank bit
+    row_mask = (1 << (hori_addr + 4)) - 1;
+
+    // Split the row address at the rank bit and put it into the dimm address
+    dimm_line = dimm_line | MrcOemMemoryLeftShiftU64 (((U64) (((row & ~row_mask) << 1) | (row & row_mask))), (16 - 6));
+
+    // put the bank part of the address into the dimm address
+    dimm_line = dimm_line | ((U64) (bank << (13 - 6)));
+
+    // Rank bit goes into the spot specified by hori_addr
+    dimm_line = dimm_line | ((U64) (rank << (20 - 6 + hori_addr)));
+
+    // reverse the XOR operation for enhanced interleave mode
+    //
+    // bank = DimmAddress[15:13] XOR DimmAddress[18:16]
+    //
+    if (enhanced_interleave_mode) {
+      dimm_line = dimm_line ^ MrcOemMemoryRightShiftU64 ((dimm_line & 0x1C00ULL), 3);
+    }
+  } else if (dual_rank && dimm_and_rank_interleaving) {
+    // put in the row part of the address
+    dimm_line = dimm_line | MrcOemMemoryLeftShiftU64 (((U64) row), 11);
+    //
+    // rank = DimmAddress[15:15]
+    // bank = {DimmAddress[16:16],DimmAddress[14:13]}
+    //
+    dimm_line = dimm_line | MrcOemMemoryLeftShiftU64 (((U64) rank), 9);
+    dimm_line = dimm_line | (MrcOemMemoryLeftShiftU64 (((U64) bank), 8) & 0x400ULL) |
+                            (MrcOemMemoryLeftShiftU64 (((U64) bank), 7) & 0x180ULL);
+    //
+    // reverse the XOR operation for enhanced interleave mode
+    //
+    // rank = DimmAddress[15:15] XOR DimmAddress[19:19]
+    // bank = {DimmAddress[16:16],DimmAddress[14:13]} XOR
+    //        {DimmAddress[20:20],DimmAddress[18:17]}
+    //
+    if (enhanced_interleave_mode) {
+      dimm_line = dimm_line ^ MrcOemMemoryRightShiftU64 ((dimm_line & 0x7800ULL), 4);
+    }
+  } else {
+    // put in the row part of the address
+    dimm_line = dimm_line | ((U64) (row << 10));
+
+    // put in the bank part of the address
+    dimm_line = dimm_line | ((U64) (bank << 7));
+
+    // rank 1 will set the rank bit
+    if (rank) {
+      dimm_line = dimm_line | MrcOemMemoryLeftShiftU64 (bit_above_row, 10);
+    }
+    //
+    // reverse the XOR operation for enhanced interleave mode
+    //
+    // bank = DimmAddress[15:13] XOR DimmAddress[18:16]
+    //
+    if (enhanced_interleave_mode) {
+      dimm_line = dimm_line ^ MrcOemMemoryRightShiftU64 ((dimm_line & 0x1C00ULL), 3);
+    }
+  }
+
+  // The column address bits make up the bottom of the DIMM address space.
+  // With the addition of LPDDR to HSW-ULT, the number column address bits may
+  // change from the standard 10 with DDR3 to 9 or 11 with some of the LPDDR
+  // organizations.  The entire DIMM address space can be shifted up or down
+  // with this change, then the column address can be inserted.
+  //
+  if (num_col_bits == 9) {
+    // rank, bank, and row bits are in 10-col-bit locations in dimm_line, shift them down to 9-col-bit locations.
+    dimm_line = MrcOemMemoryRightShiftU64 (dimm_line, 1);
+  }
+
+  if (num_col_bits == 11) {
+    // rank, bank, and row bits are in 10-col-bit locations in dimm_line, shift them up to 11-col-bit locations.
+    dimm_line = MrcOemMemoryLeftShiftU64 (dimm_line, 1);
+  }
+
+  // get the low order DIMM address space bits from the column
+  dimm_line = dimm_line | col >> 3; // no need to mask col because of previous checks
+
+
+
+
+  //
+  // DIMM address to channel address
+  //
+
+  // Find the DIMM sizes on our selected channel. adjust to cache-line granularity
+  dimm_a_size = get_dimm_a_size_as_cl (MAD_DIMM);
+  dimm_b_size = get_dimm_b_size_as_cl (MAD_DIMM);
+
+  //
+  // Both dimm_and_rank_interleaving and high_order_rank_interleave cause DIMM interleaving.
+  //
+  if (dimm_and_rank_interleaving || high_order_rank_interleave) {
+    if (dimm_line < dimm_b_size) { // Range 0 if DIMM address is less than DIMM B's size
+      //
+      // 2-way DIMM interleave. Channel address [15:15] is used to select DIMM.
+      // Need to insert dimm_select bit there.
+      //
+      chan_line = (MrcOemMemoryLeftShiftU64 (dimm_line, 1) & 0xFFFFFFFFFFFFFC00ULL) |
+                   MrcOemMemoryLeftShiftU64 (dimm_select, 9)                         |
+                  (dimm_line & 0x01FFULL);
+    } else { // not Range 0, must be Range 1
+      // Channel address is DIMM A address with DIMM B's contribution from Range 0 added in
+      chan_line = dimm_line + dimm_b_size;
+    }
+  } else { // no DIMM and Rank interleaving (nor HORI).
+    chan_line = dimm_line;
+    if (dimm_select) { // DIMM is B
+      chan_line += dimm_a_size;
+    }
+  }
+
+
+  //
+  // Channel address to remaped system address
+  //
+
+  // map physical channel to A or B
+  //
+  chan_select = physical_to_logical_chan (MAD_CHNL, chan);
+
+
+  //
+  // MAD_ZR Register field values are in 256MB granularity.
+  // They are stored here adjusted to cache-line granularity.
+  bandc    = get_bandc_as_cl (MAD_ZR);
+
+  // determine if we are in stacked mode; and if so, what the stacked size is.
+  stacked_mode = get_stacked_mode (MAD_CHNL);
+
+  if (stacked_mode) {
+    stacked_encoding = get_stacked_encoding (MAD_CHNL);
+    stacked_size = get_stacked_memory_size (stacked_encoding);
+
+    remap_line = chan_line;
+    //
+    // In stacked mode, the channel is chosen based on the bit corresponding to the
+    // size of the stacked register.  Bit-wise 'OR' in the channel selection bit into that
+    // position.
+    //
+    remap_line |= chan_select << (22 + stacked_encoding);
+  } else if (chan_line < bandc) { // Zone 1
+    remap_line = MrcOemMemoryLeftShiftU64 (chan_line, 1);
+
+    // Determine if the channel hash feature is being used
+    if (CHANNEL_HASH & HSW_MC_ADDR_CHAN_HASH_ENABLE_MASK) { // test enable bit
+      lsb_mask_bit = get_ch_hash_lsb_mask_bit (CHANNEL_HASH);
+      hash_mask = get_ch_hash_mask (CHANNEL_HASH);
+
+      // Don't need to force the selected lsb_mask_bit to be on because bit at lsb_mask_bit will be zero
+      //hash_mask = hash_mask | (1 << lsb_mask_bit);
+
+      // Reverse the swap of sys_addr bit 6 with bit pointed to by lsb_mask_bit
+      remap_line = remap_line | (MrcOemMemoryRightShiftU64 (remap_line, (U8) lsb_mask_bit) & 0x0000000000000001ULL); // copy lsb_mask_bit to bit 6
+      remap_line = remap_line & (~MrcOemMemoryLeftShiftU64 (0x0000000000000001ULL, (U8) lsb_mask_bit)); //  zero out lsb_mask_bit
+
+      // Get the bits used to produce chan_select, sans the bit at lsb_mask_bit
+      hash_line = ((U16) remap_line) & hash_mask;
+      //
+      // Recreate the value of the bit at lsb_mask_bit by doint the hash
+      // XORs.
+      //
+      hash_bit = 0;
+      for (i = 0 ; i < HSW_MC_ADDR_CHANNEL_HASH_MASK_SIZE ; i++) {
+        hash_bit = hash_bit ^ (hash_line >> i);
+      }
+      hash_bit = hash_bit & 1;
+      //
+      // Recreate the missing bit by XORing the chan_select (the result of
+      // the forward decode).
+      // (If X = A ^ B, then A = X ^ B)
+      //
+      hash_bit = hash_bit ^ chan_select;
+
+      // put the missing bit back into the address
+      remap_line = remap_line | (hash_bit << lsb_mask_bit);
+    } else {
+      // Without the hash, sys_addr[6:6] determines the channel
+      remap_line |= ((U64) chan_select);
+    }
+  } else { // Zone 2
+    remap_line = chan_line + bandc; // This works if we consider C or not.
+  }
+
+
+  // zero out unused register bits
+  TOLUD       &= HSW_MC_ADDR_TOLUD_MASK;
+  REMAP_BASE  &= HSW_MC_ADDR_REMAP_MASK;
+  REMAP_LIMIT &= HSW_MC_ADDR_REMAP_MASK;
+
+  REMAP_LIMIT |= HSW_MC_ADDR_REMAP_LIMIT_LOWER_BITS_MASK;
+
+  // work on full address instead of cache-line address;
+  remap_addr = MrcOemMemoryLeftShiftU64 (remap_line, 6);
+
+  //
+  // Determine if the address is under the remap zone and therefore must be a
+  // TCM.  remap_line can't be at or above TOM (Top Of Memory), so no need to
+  // check that.  Simply check if the remap_line is between the base and
+  // limit.
+  //
+  *p_is_tcm = (remap_addr <= REMAP_LIMIT) && (remap_addr >= REMAP_BASE); // b4194941 - REMAP_LIMIT is now inclusive
+
+
+  //
+  // reverse decode the remap region
+  //
+
+  *p_sys_addr = remap_addr; // if the remap doesn't apply system address is remap address
+
+  if (!(*p_is_tcm) && (REMAP_LIMIT > REMAP_BASE)) { // remap doesn't apply if remap zone disabled
+    top_of_remaped_mem = (U64) TOLUD;
+    top_of_remaped_mem += REMAP_LIMIT;
+    top_of_remaped_mem -= REMAP_BASE;
+    if ((remap_addr <= top_of_remaped_mem) && (remap_addr >= ((U64) TOLUD))) {
+      // remap applies. move the address to the remap zone
+      *p_sys_addr -= ((U64) TOLUD);
+      *p_sys_addr += REMAP_BASE;
+    }
+  }
+
+  // restore cache-line chunk order
+  *p_sys_addr = *p_sys_addr | (MrcOemMemoryLeftShiftU64 (((U64) col), 3) & 0x3FULL);
+
+  // successful reverse address decode
+  return TRUE;
+}
\ No newline at end of file
diff --git a/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/AddrDecode/MrcHswMcAddrDecode.h b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/AddrDecode/MrcHswMcAddrDecode.h
new file mode 100644
index 0000000..76eaf3d
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/AddrDecode/MrcHswMcAddrDecode.h
@@ -0,0 +1,129 @@
+/**
+This file contains an 'Intel Peripheral Driver' and uniquely
+identified as "Intel Reference Module" and is
+licensed for Intel CPUs and chipsets under the terms of your
+license agreement with Intel or your vendor.  This file may
+be modified by the user, subject to additional terms of the
+license agreement.
+
+Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved.
+This software and associated documentation (if any) is furnished
+under a license and may only be used or copied in accordance
+with the terms of the license. Except as permitted by such
+license, no part of this software or documentation may be
+reproduced, stored in a retrieval system, or transmitted in any
+form or by any means without the express written consent of
+Intel Corporation.
+
+@file:
+  MrcHswMcAddrDecode.h
+
+@brief:
+  File to support address decoding and encoding
+
+**/
+#ifndef _HSWULT_MC_ADDR_DECODE_H_
+#define _HSWULT_MC_ADDR_DECODE_H_
+
+
+#include "MrcOemAddrDecode.h"
+#include "MrcOemMemory.h"
+
+/**
+@brief
+  Address decode function
+  Converts system address to DRAM address
+
+  @param[in]      sys_addr - the 39-bit system address to convert
+  @param[in, out] p_is_tcm - is the transaction to sys_addr "traffic class for the manageability engine"
+  @param[in]      TOLUD - memory register
+  @param[in]      REMAP_BASE - memory register
+  @param[in]      REMAP_LIMIT - memory register
+  @param[in]      CHANNEL_HASH - memory register
+  @param[in]      MAD_ZR - memory register
+  @param[in]      MAD_CHNL - memory register
+  @param[in]      MAD_DIMM_ch0 - memory register
+  @param[in]      MAD_DIMM_ch1 - memory register
+  @param[in]      MAD_DIMM_ch2 - memory register
+  @param[out]     p_chan - channel sys_addr decodes to
+  @param[out]     p_dimm - DIMM sys_addr decodes to
+  @param[out]     p_rank - rank sys_addr decodes to
+  @param[out]     p_bank - bank sys_addr decodes to
+  @param[out]     p_row - row sys_addr decodes to
+  @param[out]     p_col - column sys_addr decodes to.
+
+  @retval True if successful.
+
+**/
+BOOL
+MrcHswDecode (
+  IN     U64  sys_addr,
+  IN OUT BOOL *p_is_tcm,
+  IN     U32  TOLUD,
+  IN     U64  REMAP_BASE,
+  IN     U64  REMAP_LIMIT,
+  IN     U32  CHANNEL_HASH,
+  IN     U32  MAD_ZR,
+  IN     U32  MAD_CHNL,
+  IN     U32  MAD_DIMM_ch0,
+  IN     U32  MAD_DIMM_ch1,
+  IN     U32  MAD_DIMM_ch2,
+  OUT    U16  *p_chan,
+  OUT    U16  *p_dimm,
+  OUT    U16  *p_rank,
+  OUT    U16  *p_bank,
+  OUT    U16  *p_row,
+  OUT    U16  *p_col
+  );
+
+/**
+@brief
+  Address encode function (reverse address decode)
+  DRAM address to system address conversion
+
+  @param[in]     p_chan - channel sys_addr to encode
+  @param[in]     p_dimm - DIMM sys_addr to encode
+  @param[in]     p_rank - rank sys_addr to encode
+  @param[in]     p_bank - bank sys_addr to encode
+  @param[in]     p_row - row sys_addr to encode
+  @param[in]     p_col - column sys_addr to encode. Note: The architecture is limited to
+                         half-cache-line granularity for burst order. Therefore the last
+                         two bits of the column are ignored.
+  @param[in]      TOLUD - memory register
+  @param[in]      REMAP_BASE - memory register
+  @param[in]      REMAP_LIMIT - memory register
+  @param[in]      CHANNEL_HASH - memory register
+  @param[in]      MAD_ZR - memory register
+  @param[in]      MAD_CHNL - memory register
+  @param[in]      MAD_DIMM_ch0 - memory register
+  @param[in]      MAD_DIMM_ch1 - memory register
+  @param[in]      MAD_DIMM_ch2 - memory register
+  @param[out]     sys_addr - the 39-bit system address convert to
+  @param[in, out] p_is_tcm - is the transaction to sys_addr "traffic class for the manageability engine"
+
+  @retval True if successful.
+
+**/
+BOOL
+MrcHswEncode (
+  IN  U16     chan,
+  IN  U16     dimm,
+  IN  U16     rank,
+  IN  U16     bank,
+  IN  U16     row,
+  IN  U16     col,
+  IN  U32     TOLUD,
+  IN  U64     REMAP_BASE,
+  IN  U64     REMAP_LIMIT,
+  IN  U32     CHANNEL_HASH,
+  IN  U32     MAD_ZR,
+  IN  U32     MAD_CHNL,
+  IN  U32     MAD_DIMM_ch0,
+  IN  U32     MAD_DIMM_ch1,
+  IN  U32     MAD_DIMM_ch2,
+  OUT U64     *p_sys_addr,
+  IN OUT BOOL *p_is_tcm
+  );
+
+
+#endif // _HSWULT_MC_ADDR_DECODE_H_
diff --git a/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Api/MrcApi.h b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Api/MrcApi.h
new file mode 100644
index 0000000..0348c38
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Api/MrcApi.h
@@ -0,0 +1,280 @@
+/** @file
+  Mrc definition of supported features.
+
+@copyright
+  Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved.
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement.
+**/
+
+#ifndef _MrcApi_h_
+#define _MrcApi_h_
+
+#include "MrcTypes.h"
+
+#define HPET_MIN          0x0001  ///< Minimum is one HPET tick = 69.841279ns
+#define HPET_1US          0x000F
+#define HPET_1MS          0x37EF
+
+#define START_TEST_DELAY  (2 * HPET_MIN)
+#define IO_RESET_DELAY    (2 * HPET_MIN)
+
+#define COMP_INT          0x0A    ///< For 10ms
+#define MAX_POSSIBLE_VREF 54      ///< Maximum possible margin for Vref
+#define MAX_POSSIBLE_TIME 31      ///< Maximum possible margin for time
+#define TXEQFULLDRV     (0x30)    ///< 12 Emphasize legs (not trained)
+#define DIMMRON         (ODIC_RZQ_6)
+#define BCLK_DEFAULT    (100 * 1000 * 1000)
+
+///
+/// Define the frequencies that may be possible in the memory controller.
+/// Note that not all these values may be supported.
+///
+#define fNoInit     (0)
+#define f800        (800)
+#define f1000       (1000)
+#define f1067       (1067)
+#define f1200       (1200)
+#define f1333       (1333)
+#define f1400       (1400)
+#define f1600       (1600)
+#define f1800       (1800)
+#define f1867       (1867)
+#define f2000       (2000)
+#define f2133       (2133)
+#define f2200       (2200)
+#define f2400       (2400)
+#define f2600       (2600)
+#define f2667       (2667)
+#define fUnSupport  (0x7FFFFFFF)
+typedef U32 MrcFrequency;
+
+///
+/// Define the memory nominal voltage (VDD).
+/// Note that not all these values may be supported.
+///
+typedef enum {
+  VDD_INVALID,
+  VDD_1_00    = 1000,
+  VDD_1_05    = 1050,
+  VDD_1_10    = 1100,
+  VDD_1_15    = 1150,
+  VDD_1_20    = 1200,
+  VDD_1_25    = 1250,
+  VDD_1_30    = 1300,
+  VDD_1_35    = 1350,
+  VDD_1_40    = 1400,
+  VDD_1_45    = 1450,
+  VDD_1_50    = 1500,
+  VDD_1_55    = 1550,
+  VDD_1_60    = 1600,
+  VDD_1_65    = 1650,
+  VDD_1_70    = 1700,
+  VDD_1_75    = 1750,
+  VDD_1_80    = 1800,
+  VDD_1_85    = 1850,
+  VDD_1_90    = 1900,
+  VDD_1_95    = 1950,
+  VDD_2_00    = 2000,
+  VDD_2_05    = 2050,
+  VDD_2_10    = 2100,
+  VDD_2_15    = 2150,
+  VDD_2_20    = 2200,
+  VDD_2_25    = 2250,
+  VDD_2_30    = 2300,
+  VDD_2_35    = 2350,
+  VDD_2_40    = 2400,
+  VDD_2_45    = 2450,
+  VDD_2_50    = 2500,
+  VDD_2_55    = 2550,
+  VDD_2_60    = 2600,
+  VDD_2_65    = 2650,
+  VDD_2_70    = 2700,
+  VDD_2_75    = 2750,
+  VDD_2_80    = 2800,
+  VDD_2_85    = 2850,
+  VDD_2_90    = 2900,
+  VDD_2_95    = 2950,
+  VDD_MAXIMUM = 0x7FFFFFFF
+} MrcVddSelect;
+
+///
+/// Compile time configuration parameters - START.
+/// The user must set these values for the system.
+///
+#define MAX_EDGES              2 ///< Maximum number of edges.
+#define MAX_BITS               8 ///< BITS per byte.
+#define MAX_MR_IN_DIMM         4 ///< Maximum number of mode registers in a DIMM.
+#define MAX_CPU_SOCKETS        1 ///< The maximum number of CPUs per system.
+#define MAX_CONTROLLERS        1 ///< The maximum number of memory controllers per CPU socket.
+#define MAX_CHANNEL            2 ///< The maximum number of channels per memory controller.
+
+#define MAX_DIMMS_IN_CHANNEL   2 ///< The maximum number of DIMMs per channel.
+
+#define MAX_RANK_IN_DIMM       2 ///< The maximum number of ranks per DIMM.
+#define MAX_RANK_IN_CHANNEL    (MAX_DIMMS_IN_CHANNEL * MAX_RANK_IN_DIMM) ///< The maximum number of ranks per channel.
+#define MAX_SDRAM_IN_DIMM      9           ///< The maximum number of SDRAMs per DIMM when ECC is enabled.
+#define MAX_STROBE             18          ///< Number of strobe groups.
+#define MAX_DQ                 72          ///< Number of Dq bits used by the rank.
+#define CHAR_BITS              8           ///< Number of bits in a char.
+#define DIMMSIZEMIN            512         ///< The minimum size of DIMM, in MBytes.
+#define DIMMSIZEMAX            (16 * 1024) ///< The maximum size of DIMM, in MBytes.
+#define FREQMIN                f1067       ///< The minimum valid frequency.
+
+#define SUPPORT_DDR3           SUPPORT     ///< SUPPORT means that DDR3 is supported by the MRC.
+#define ULT_SUPPORT_LPDDR3     SUPPORT     ///< SUPPORT means that LPDDR3 is supported by the MRC.
+#define TRAD_SUPPORT_LPDDR3    UNSUPPORT   ///< SUPPORT means that LPDDR3 is supported by the MRC.
+
+#define SUPPORT_SPD_CRC        UNSUPPORT   ///< SUPPORT means that the CRC of the DIMMs SPD must match.
+#define SUPPORT_FORCE          UNSUPPORT   ///< SUPPORT means to force tAA, tRCD, tRP to the same value.
+#define SUPPORT_ALLDIMMS       UNSUPPORT   ///< SUPPORT means all timings across all DIMMs in the system.
+                                           ///< UNSUPPORT means all timings across each memory channel's DIMMs.
+#define SUPPORT_XMP            SUPPORT     ///< SUPPORT means Extreme Memory Profiles are supported, else UNSUPPORT.
+#define SUPPORT_ECC            SUPPORT     ///< SUPPORT means ECC is suppported, else UNSUPPORT.
+#define SUPPORT_UDIMM          SUPPORT     ///< SUPPORT means that unbuffered DIMMs are supported, else UNSUPPORT.
+#define SUPPORT_SODIMM         SUPPORT     ///< SUPPORT means that SO-DIMMs are supported, else UNSUPPORT.
+#define SUPPORT_RDIMM          UNSUPPORT   ///< SUPPORT means that registered DIMMs are supported, else UNSUPPORT.
+#define SUPPORT_PRIWIDTH_8     UNSUPPORT   ///< SUPPORT means that SDRAM primary bus width of 8 is supported by the system.
+#define SUPPORT_PRIWIDTH_16    UNSUPPORT   ///< SUPPORT means that SDRAM primary bus width of 16 is supported by the system.
+#define SUPPORT_PRIWIDTH_32    UNSUPPORT   ///< SUPPORT means that SDRAM primary bus width of 32 is supported by the system.
+#define SUPPORT_PRIWIDTH_64    SUPPORT     ///< SUPPORT means that SDRAM primary bus width of 64 is supported by the system.
+#define SUPPORT_DEVWIDTH_4     UNSUPPORT   ///< SUPPORT means that SDRAM device width of 4 is supported by the system.
+#define SUPPORT_DEVWIDTH_8     SUPPORT     ///< SUPPORT means that SDRAM device width of 8 is supported by the system.
+#define SUPPORT_DEVWIDTH_16    SUPPORT     ///< SUPPORT means that SDRAM device width of 16 is supported by the system.
+#define SUPPORT_DEVWIDTH_32    SUPPORT     ///< SUPPORT means that SDRAM device width of 32 is supported by the system.
+#define SUPPORT_COLUMN_9       UNSUPPORT   ///< SUPPORT means that 9 bit size is supported by the system.
+
+#define ULT_SUPPORT_COLUMN_10  SUPPORT     ///< SUPPORT means that 10 bit size is supported by the system.
+#define ULT_SUPPORT_COLUMN_11  SUPPORT     ///< SUPPORT means that 11 bit size is supported by the system.
+#define ULT_SUPPORT_COLUMN_12  SUPPORT     ///< SUPPORT means that 12 bit size is supported by the system.
+#define TRAD_SUPPORT_COLUMN_10 SUPPORT     ///< SUPPORT means that 10 bit size is supported by the system.
+#define TRAD_SUPPORT_COLUMN_11 UNSUPPORT   ///< SUPPORT means that 11 bit size is supported by the system.
+#define TRAD_SUPPORT_COLUMN_12 UNSUPPORT   ///< SUPPORT means that 12 bit size is supported by the system.
+
+#define SUPPORT_ROW_12         SUPPORT     ///< SUPPORT means that 12 bit size is supported by the system.
+#define SUPPORT_ROW_13         SUPPORT     ///< SUPPORT means that 13 bit size is supported by the system.
+#define SUPPORT_ROW_14         SUPPORT     ///< SUPPORT means that 14 bit size is supported by the system.
+#define SUPPORT_ROW_15         SUPPORT     ///< SUPPORT means that 15 bit size is supported by the system.
+#define SUPPORT_ROW_16         SUPPORT     ///< SUPPORT means that 16 bit size is supported by the system.
+#define SUPPORT_BANK_8         SUPPORT     ///< SUPPORT means that 8 banks is supported by the system.
+#define SUPPORT_BANK_16        UNSUPPORT   ///< SUPPORT means that 16 banks is supported by the system.
+#define SUPPORT_BANK_32        UNSUPPORT   ///< SUPPORT means that 32 banks is supported by the system.
+#define SUPPORT_BANK_64        UNSUPPORT   ///< SUPPORT means that 64 banks is supported by the system.
+
+#define TAAMINPOSSIBLE         4           ///< tAAmin possible range, in number of tCK cycles.
+#define TAAMAXPOSSIBLE         24
+#define TWRMINPOSSIBLE         5           ///< tWRmin possible range, in number of tCK cycles.
+#define TWRMAXPOSSIBLE         16          ///< tWRmin values of 9, 11, 13 ,15 are not valid for DDR3.
+#define TRCDMINPOSSIBLE        4           ///< tRCDmin possible range, in number of tCK cycles.
+#define TRCDMAXPOSSIBLE        20
+#define TRRDMINPOSSIBLE        4           ///< tRRDmin possible range, in number of tCK cycles.
+#define TRRDSMINPOSSIBLE       4           ///< tRRD_Smin possible range, in number of tCK cycles.
+#define TRRDSMAXPOSSIBLE       65535
+#define TRRDLMINPOSSIBLE       4           ///< tRRD_Lmin possible range, in number of tCK cycles.
+#define TRRDLMAXPOSSIBLE       65535
+#define TRPMINPOSSIBLE         4           ///< tRPmin possible range, in number of tCK cycles.
+#define TRPMAXPOSSIBLE         15
+#define TRPABMINPOSSIBLE       4           ///< tRPabmin possible range, in number of tCK cycles.
+#define TRPABMAXPOSSIBLE       18
+#define TRASMINPOSSIBLE        10          ///< tRASmin possible range, in number of tCK cycles.
+#define TRASMAXPOSSIBLE        40
+#define TRCMINPOSSIBLE         1           ///< tRCmin possible range, in number of tCK cycles.
+#define TRCMAXPOSSIBLE         4095
+#define TRFCMINPOSSIBLE        1           ///< tRFCmin possible range, in number of tCK cycles.
+#define TRFCMAXPOSSIBLE        511
+#define TWTRMINPOSSIBLE        4           ///< tWTRmin possible range, in number of tCK cycles.
+#define TWTRMAXPOSSIBLE        10
+#define TRTPMINPOSSIBLE        4           ///< tRTPmin possible range, in number of tCK cycles.
+#define TRTPMAXPOSSIBLE        15
+#define TFAWMINPOSSIBLE        10          ///< tFAWmin possible range, in number of tCK cycles.
+#define TFAWMAXPOSSIBLE        54
+#define TCWLMINPOSSIBLE        5           ///< tCWLmin possible range, in number of tCK cycles.
+#define TCWLMAXPOSSIBLE        12
+#define TREFIMINPOSSIBLE       1           ///< tREFImin possible range, in number of tCK cycles.
+#define TREFIMAXPOSSIBLE       65535
+#define NMODEMINPOSSIBLE       1           ///< Command rate mode min possible range, in number of tCK cycles.
+#define NMODEMAXPOSSIBLE       3
+
+#define ULT_VDDMINPOSSIBLE     1200        ///< Vdd possible range, in milliVolts.
+#define ULT_VDDMAXPOSSIBLE     1350
+#define TRAD_VDDMINPOSSIBLE    1350        ///< Vdd possible range, in milliVolts.
+#define TRAD_VDDMAXPOSSIBLE    1500
+
+#define SPD3_MANUF_START       117         ///< The starting point for the SPD manufacturing data.
+#define SPD3_MANUF_END         127         ///< The ending point for the SPD manufacturing data.
+#define HOST_BRIDGE_BUS        0           ///< The host bridge bus number.
+#define HOST_BRIDGE_DEVICE     0           ///< The host bridge device number.
+#define HOST_BRIDGE_FUNCTION   0           ///< The host bridge function number.
+#define HOST_BRIDGE_DEVID      0           ///< The host bridge device id offset.
+#define HOST_BRIDGE_REVID      8           ///< The host bridge revision id offset.
+
+#define MEMORY_RATIO_MIN       3           ///< The minimum DDR ratio value that the hardware supports.
+#define MEMORY_RATIO_MAX       15          ///< The maximum DDR ratio value that the hardware supports.
+
+///
+/// Compile time configuration parameters - END.
+///
+
+#if (defined ULT_FLAG && defined TRAD_FLAG)
+#define SUPPORT_LPDDR3         (ULT_SUPPORT_LPDDR3 || TRAD_SUPPORT_LPDDR3)
+#define SUPPORT_COLUMN_10      (ULT_SUPPORT_COLUMN_10 || TRAD_SUPPORT_COLUMN_10)
+#define SUPPORT_COLUMN_11      (ULT_SUPPORT_COLUMN_11 || TRAD_SUPPORT_COLUMN_11)
+#define SUPPORT_COLUMN_12      (ULT_SUPPORT_COLUMN_12 || TRAD_SUPPORT_COLUMN_12)
+#define VDDMINPOSSIBLE         MIN (ULT_VDDMINPOSSIBLE, TRAD_VDDMINPOSSIBLE)
+#define VDDMAXPOSSIBLE         MAX (ULT_VDDMAXPOSSIBLE, TRAD_VDDMAXPOSSIBLE)
+#elif (defined ULT_FLAG)
+#define SUPPORT_LPDDR3         ULT_SUPPORT_LPDDR3
+#define SUPPORT_COLUMN_10      ULT_SUPPORT_COLUMN_10
+#define SUPPORT_COLUMN_11      ULT_SUPPORT_COLUMN_11
+#define SUPPORT_COLUMN_12      ULT_SUPPORT_COLUMN_12
+#define VDDMINPOSSIBLE         ULT_VDDMINPOSSIBLE
+#define VDDMAXPOSSIBLE         ULT_VDDMAXPOSSIBLE
+#elif (defined TRAD_FLAG)
+#define SUPPORT_LPDDR3         TRAD_SUPPORT_LPDDR3
+#define SUPPORT_COLUMN_10      TRAD_SUPPORT_COLUMN_10
+#define SUPPORT_COLUMN_11      TRAD_SUPPORT_COLUMN_11
+#define SUPPORT_COLUMN_12      TRAD_SUPPORT_COLUMN_12
+#define VDDMINPOSSIBLE         TRAD_VDDMINPOSSIBLE
+#define VDDMAXPOSSIBLE         TRAD_VDDMAXPOSSIBLE
+#endif // ULT_FLAG && TRAD_FLAG
+
+#define MRC_ALL_DDR_SUPPORTED    ((SUPPORT_DDR4 == SUPPORT) && ((SUPPORT_DDR3 == SUPPORT) || (SUPPORT_LPDDR3 == SUPPORT)))
+#define MRC_DDR3_LPDDR_SUPPORTED ((SUPPORT_DDR3 == SUPPORT) || (SUPPORT_LPDDR3 == SUPPORT))
+
+///
+/// Exit mode
+///
+typedef enum {
+  emSlow      = 0,
+  emFast      = 1,
+  emAuto      = 0xFF,
+} MrcExitMode;
+
+///
+/// System definitions
+///
+#define MRC_SYSTEM_BCLK (100)
+
+///
+/// Register default values
+///
+#define MRC_DIMM_RANK_INTERLEAVE      (1)
+#define MRC_ENHANCED_INTERLEAVE_MODE  (1)
+#define MRC_HORI_MODE                 (1)
+
+///
+/// Training definitions
+///
+#endif
diff --git a/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Api/MrcBdat.c b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Api/MrcBdat.c
new file mode 100644
index 0000000..7670487
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Api/MrcBdat.c
@@ -0,0 +1,529 @@
+/** @file
+  Copies the memory related timing and configuration information into the
+  Compatible BIOS data (BDAT) table.
+
+@copyright
+  Copyright (c) 2010 - 2012 Intel Corporation. All rights reserved.
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement.
+**/
+
+#include "MrcTypes.h"
+#include "MrcApi.h"
+#include "MrcGlobal.h"
+#include "MrcOem.h"
+#include "MrcSpdProcessing.h"
+#include "McAddress.h"
+
+#ifdef BDAT_SUPPORT
+#define TBD                       0
+#define CRC_SEED                  0
+#define CRC_XOR_MASK              0x1021
+#define MAX_UINT8_VALUE           (((1UL) << CHAR_BITS) - 1)
+#define HOST_BRIDGE_BUS           0
+#define HOST_BRIDGE_DEVICE        0
+#define HOST_BRIDGE_FUNCTION      0
+#define HOST_BRIDGE_OFFSET_DEVID  0
+#define HOST_BRIDGE_OFFSET_REVID  8
+#define CopyMem                   MrcOemMemoryCpy
+#define GetCrc16                  GetDimmCrc
+
+typedef U8  UINT8;
+typedef U16 UINT16;
+
+/**
+  @brief
+  Finds the window value for the given DQ value and if it is less than the
+    current value, then save the end point values.
+
+    @param[in, out] Rank1         - Pointer to the first rank training value (left or low).
+    @param[in, out] Rank2         - Pointer to the second rank training value (right or high).
+    @param[in, out] CurrentWindow - The current window value.
+    @param[in] Value1        - The first training value (left or low).
+    @param[in] Value2        - The second training value (right or high).
+
+    @retval Nothing.
+**/
+void
+ConvertDq2Rank (
+  IN OUT UINT8        *Rank1,
+  IN OUT UINT8        *Rank2,
+  IN OUT UINT8        *CurrentWindow,
+  IN     const UINT8  Value1,
+  IN     const UINT8  Value2
+  )
+{
+  UINT8 Window;  // The calculated window value.
+
+  Window = MAX (Value1, Value2) - MIN (Value1, Value2);
+  if (Window < *CurrentWindow) {
+    *CurrentWindow  = Window;
+    *Rank1          = Value1;
+    *Rank2          = Value2;
+  } // if
+  return;
+}
+
+/**
+@brief
+  Initialize the memory rank margin area of the RMT_STRUCTURE.
+
+  @param[in] MrcData - The MRC "global data".
+  @param[in, out] RmtRankMargin - Pointer to the start of the rank margin information in the RMT table.
+  @param[in] RmtDq         - Pointer to the start of the dq margin information in the RMT table.
+
+  @retval Nothing.
+**/
+void
+MrcFillRmtRankMargin (
+  IN     const MrcParameters  *MrcData,
+  IN OUT RmtRankMargin        *RmtRankMargin,
+  IN     RmtDqMargin          *RmtDq
+  )
+{
+  RmtDqMargin *RmtDqMargin;         // Pointer to the current DQ margin in the RMT structure.
+  UINT8       Dq;                   // DQ number in the rank.
+  UINT8       DqEnd;
+  UINT8       SmallestWindowRxDq;   // The smallest of the Rx DQ windows.
+  UINT8       SmallestWindowTxDq;   // The smallest of the Tx DQ windows.
+  UINT8       SmallestWindowRxVref; // The smallest of the Rx Vref windows.
+  UINT8       SmallestWindowTxVref; // The smallest of the Tx Vref windows.
+
+  SmallestWindowRxDq   = (UINT8) MAX_UINT8_VALUE;
+  SmallestWindowTxDq   = (UINT8) MAX_UINT8_VALUE;
+  SmallestWindowRxVref = (UINT8) MAX_UINT8_VALUE;
+  SmallestWindowTxVref = (UINT8) MAX_UINT8_VALUE;
+  DqEnd                = (MrcData->SysOut.Outputs.EccSupport) ? MAX_DQ : (MAX_DQ - MAX_BITS);
+  for (Dq = 0; Dq < DqEnd; Dq++) {
+    RmtDqMargin = &RmtDq[Dq];
+    ConvertDq2Rank (
+      &RmtRankMargin->RxDqLeft,
+      &RmtRankMargin->RxDqRight,
+      &SmallestWindowRxDq,
+      RmtDqMargin->RxDqLeft,
+      RmtDqMargin->RxDqRight
+      );
+    ConvertDq2Rank (
+      &RmtRankMargin->TxDqLeft,
+      &RmtRankMargin->TxDqRight,
+      &SmallestWindowTxDq,
+      RmtDqMargin->TxDqLeft,
+      RmtDqMargin->TxDqRight
+      );
+    ConvertDq2Rank (
+      &RmtRankMargin->RxVrefLow,
+      &RmtRankMargin->RxVrefHigh,
+      &SmallestWindowRxVref,
+      RmtDqMargin->RxVrefLow,
+      RmtDqMargin->RxVrefHigh
+      );
+    ConvertDq2Rank (
+      &RmtRankMargin->TxVrefLow,
+      &RmtRankMargin->TxVrefHigh,
+      &SmallestWindowTxVref,
+      RmtDqMargin->TxVrefLow,
+      RmtDqMargin->TxVrefHigh
+      );
+  } // Dq loop
+  return;
+}
+
+/**
+@brief
+  Initialize the memory DQ area of the RMT_STRUCTURE.
+
+  @param[in, out] RmtDq   - Pointer to the start of the DQ information in the RMT table.
+  @param[in] Channel - Specific Channel
+  @param[in] Dimm    - Specific Dimm
+  @param[in] Rank    - Specific Rank
+  @param[in] MrcData - The MRC "global data".
+
+  @retval Nothing.
+**/
+void
+MrcFillRmtDqMargin (
+  IN OUT RmtDqMargin          *RmtDq,
+  IN     const UINT8          Controller,
+  IN     const UINT8          Channel,
+  IN     const UINT8          Dimm,
+  IN     const UINT8          Rank,
+  IN     const MrcParameters  *MrcData
+  )
+{
+  const MrcOutput       *Outputs;
+  const MrcChannelOut   *ChannelOut;
+  const MrcDqTimeMargin *RxDqMargin;      // Pointer to the output portion of the MRC global data area.
+  const MrcDqTimeMargin *TxDqMargin;      // Pointer to the output portion of the MRC global data area.
+  const MrcDqVrefMargin *RxVrefDqMargin;  // Pointer to the output portion of the MRC global data area.
+  const MrcDqVrefMargin *TxVrefDqMargin;  // Pointer to the output portion of the MRC global data area.
+  RmtDqMargin           *RmtDqMargin;     // Pointer to the current DQ margin in the RMT structure.
+  UINT8                 RankInChannel;
+  UINT8                 Sdram;
+  UINT8                 Dq;               // DQ number in the rank.
+  UINT8                 DqEnd;
+  UINT8                 Bit;
+
+  Outputs       = &MrcData->SysOut.Outputs;
+  ChannelOut    = &Outputs->Controller[Controller].Channel[Channel];
+  RankInChannel = (Dimm * MAX_RANK_IN_DIMM) + Rank;
+  DqEnd         = (Outputs->EccSupport) ? MAX_DQ : (MAX_DQ - MAX_BITS);
+  for (Dq = 0; Dq < DqEnd; Dq++) {
+    Sdram                   = Dq / CHAR_BITS;
+    Bit                     = Dq % CHAR_BITS;
+    RxDqMargin              = &ChannelOut->RxDqPb[RankInChannel][Sdram][Bit];
+    TxDqMargin              = &ChannelOut->TxDqPb[RankInChannel][Sdram][Bit];
+    RxVrefDqMargin          = &ChannelOut->RxDqVrefPb[RankInChannel][Sdram][Bit];
+    TxVrefDqMargin          = &ChannelOut->TxDqVrefPb[RankInChannel][Sdram][Bit];
+    RmtDqMargin             = &RmtDq[Dq];
+    RmtDqMargin->RxDqLeft   = RxDqMargin->Left;
+    RmtDqMargin->RxDqRight  = RxDqMargin->Right;
+    RmtDqMargin->TxDqLeft   = TxDqMargin->Left;
+    RmtDqMargin->TxDqRight  = TxDqMargin->Right;
+    RmtDqMargin->RxVrefLow  = RxVrefDqMargin->Low;
+    RmtDqMargin->RxVrefHigh = RxVrefDqMargin->High;
+    RmtDqMargin->TxVrefLow  = TxVrefDqMargin->Low;
+    RmtDqMargin->TxVrefHigh = TxVrefDqMargin->High;
+  } // Dq loop
+  return;
+}
+
+/**
+@brief
+  Initialize the memory rank training area of the RMT_STRUCTURE.
+
+  @param[in, out] RmtRankTraining - Pointer to the start of the rank training information in the RMT table.
+  @param[in] Channel         - Specific Channel
+  @param[in] Dimm            - Specific Dimm
+  @param[in] Rank            - Specific Rank
+  @param[in] MrcData         - The MRC "global data".
+
+  @retval Nothing.
+**/
+void
+MrcFillRmtRankTraining (
+  IN OUT RmtRankTraining      *RmtRankTraining,
+  IN     const UINT8          Controller,
+  IN     const UINT8          Channel,
+  IN     const UINT8          Dimm,
+  IN     const UINT8          Rank,
+  IN     const MrcParameters  *MrcData
+  )
+{
+  const MrcOutput     *Outputs;     // Pointer to the output portion of the MRC global data area.
+  const MrcChannelOut *ChannelOut;  // Pointer to the channel portion of the MRC global data area.
+  UINT8               Index;
+  UINT8               RankInChannel;
+  UINT8               Sdram;
+  UINT8               Strobe;
+
+  Outputs       = &MrcData->SysOut.Outputs;
+  ChannelOut    = &Outputs->Controller[Controller].Channel[Channel];
+  RankInChannel = (Dimm * MAX_RANK_IN_DIMM) + Rank;
+  for (Strobe = 0; Strobe < MAX_STROBE; Strobe++) {
+    Sdram = Strobe / 2;
+    RmtRankTraining->RecEnDelay[Strobe] = ChannelOut->RcvEn[RankInChannel][Sdram];
+    RmtRankTraining->WlDelay[Strobe]    = ChannelOut->WlDelay[RankInChannel][Sdram];
+    RmtRankTraining->RxDqDelay[Strobe]  = (Strobe % 2)
+                                        ? ChannelOut->RxDqsN[RankInChannel][Sdram]
+                                        : ChannelOut->RxDqsP[RankInChannel][Sdram];
+    RmtRankTraining->TxDqDelay[Strobe]  = ((U8) (ChannelOut->TxDq[RankInChannel][Sdram] >> 6)) & 7;
+  } // Strobe loop
+  RmtRankTraining->ClkDelay = ChannelOut->ClkPiCode[RankInChannel];
+  RmtRankTraining->CtlDelay = ChannelOut->CtlPiCode[RankInChannel];
+  for (Index = 0; Index < (sizeof (RmtRankTraining->CmdDelay) / sizeof (RmtRankTraining->CmdDelay[0])); Index++) {
+    RmtRankTraining->CmdDelay[Index] = TBD;  // Need to implement code.
+  } // Index loop
+  RmtRankTraining->IoLatency = ChannelOut->IoLatency[RankInChannel];
+  RmtRankTraining->Roundtrip = ChannelOut->RTLatency[RankInChannel];
+  return;
+}
+
+/**
+@brief
+  Initialize the memory rank area of the RMT_STRUCTURE.
+
+  @param[in, out] RmtRank  - Pointer to the start of the rank information in the RMT table.
+  @param[in] MrcData  - The MRC "global data".
+  @param[in] Channel  - Current channel number.
+  @param[in] Dimm     - Current dimm number.
+
+  @retval Nothing.
+**/
+void
+MrcFillRmtRankStructure (
+  IN OUT RmtRankList         *RmtRank,
+  IN     const MrcParameters *MrcData,
+  IN     UINT8               Controller,
+  IN     UINT8               Channel,
+  IN     UINT8               Dimm
+)
+{
+  const MrcOutput     *Outputs;          // Pointer to the output portion of the MRC global data area.
+  const MrcChannelOut *ChannelOut;       // Pointer to the DIMM output portion of the MRC global data area.
+  const MrcDimmOut    *DimmOut;          // Pointer to the DIMM output portion of the MRC global data area.
+  RmtRankList         *RmtRankLists;     // Pointer to the current rank list in the RMT structure.
+  RmtRankTraining     *RmtRankTraining;  // Pointer to the current rank training in the RMT structure.
+  UINT8               Rank;              // Rank count for sequencing.
+  UINT8               RankInChannel;     // Rank number in a channel.
+
+  Outputs    = &MrcData->SysOut.Outputs;
+  ChannelOut = &Outputs->Controller[Controller].Channel[Channel];
+  DimmOut    = &ChannelOut->Dimm[Dimm];
+  for (Rank = 0; (Rank < MAX_RANK_IN_DIMM) && (Rank < DimmOut->RankInDIMM); Rank++) {
+    RmtRankLists                    = &RmtRank[Rank];
+    RmtRankTraining                 = &RmtRankLists->RankTraining;
+    RankInChannel                   = (Dimm * MAX_RANK_IN_DIMM) + Rank;
+    RmtRankLists->RankEnabled       = TRUE;
+    RmtRankLists->RankMarginEnabled = TRUE;
+    RmtRankLists->DqMarginEnabled   = TRUE;
+    MrcFillRmtDqMargin (&RmtRankLists->DqMargin[0], Controller, Channel, Dimm, Rank, MrcData);
+    MrcFillRmtRankMargin (MrcData, &RmtRankLists->RankMargin, &RmtRankLists->DqMargin[0]);
+    MrcFillRmtRankTraining (&RmtRankLists->RankTraining, Controller, Channel, Dimm, Rank, MrcData);
+    CopyMem (
+      (UINT8 *) &RmtRankLists->RankMRS.ModeRegister[0],
+      (UINT8 *) &DimmOut->Rank[Rank].MR[0],
+      sizeof (RmtRankMrs)
+      );
+    RmtRankLists->RankMargin.CmdLeft      = ChannelOut->Command[RankInChannel].Left;
+    RmtRankLists->RankMargin.CmdRight     = ChannelOut->Command[RankInChannel].Right;
+    RmtRankLists->RankMargin.CmdVrefLow   = ChannelOut->Command[RankInChannel].Low;
+    RmtRankLists->RankMargin.CmdVrefHigh  = ChannelOut->Command[RankInChannel].High;
+    RmtRankLists->RankMargin.RecvenLeft   = ChannelOut->ReceiveEnable[RankInChannel].Left;
+    RmtRankLists->RankMargin.RecvenRight  = ChannelOut->ReceiveEnable[RankInChannel].Right;
+    RmtRankLists->RankMargin.WrLevelLeft  = ChannelOut->WriteLevel[RankInChannel].Left;
+    RmtRankLists->RankMargin.WrLevelRight = ChannelOut->WriteLevel[RankInChannel].Right;
+  }  // Rank loop
+  return;
+}
+
+/**
+@brief
+  Initialize the memory dimm area of the RMT_STRUCTURE.
+
+  @param[in, out] RmtDimm - Pointer to the start of the dimm information in the RMT table.
+  @param[in] MrcData - The MRC "global data".
+  @param[in] Channel - Current channel number.
+
+  @retval Nothing.
+**/
+void
+MrcFillRmtDimmStructure (
+  IN OUT RmtDimmList         *RmtDimm,
+  IN     const MrcParameters *MrcData,
+  IN     UINT8               Controller,
+  IN     UINT8               Channel
+  )
+{
+  const MrcInput      *Inputs;              // Pointer to the input portion of the MRC global data area.
+  const MrcDimmIn     *DimmIn;              // Pointer to the DIMM input portion of the MRC global data area.
+  const MrcSpd        *SpdIn;               // Pointer to the SPD input portion of the MRC global data area.
+  const MrcOutput     *Outputs;             // Pointer to the output portion of the MRC global data area.
+  const MrcChannelOut *ChannelOut;          // Pointer to the channel output portion of the MRC global data area.
+  const MrcDimmOut    *DimmOut;             // Pointer to the DIMM output portion of the MRC global data area.
+  RmtDimmList         *RmtDimmList;         // Pointer to the current DIMM in the RMT structure.
+  RmtSpd              *RmtSpdList;          // Pointer to the current SPD in the RMT structure.
+  UINT8               Dimm;                 // Dimm count for sequencing.
+
+  Inputs     = &MrcData->SysIn.Inputs;
+  Outputs    = &MrcData->SysOut.Outputs;
+  ChannelOut = &Outputs->Controller[Controller].Channel[Channel];
+  for (Dimm = 0; Dimm < MAX_DIMMS_IN_CHANNEL; Dimm++) {
+    DimmOut = &ChannelOut->Dimm[Dimm];
+    if (DimmOut->Status == DIMM_PRESENT) {
+      RmtDimmList               = &RmtDimm[Dimm];
+      RmtSpdList                = &RmtDimmList->SpdBytes;
+      DimmIn                    = &Inputs->Controller[Controller].Channel[Channel].Dimm[Dimm];
+      SpdIn                     = &DimmIn->Spd;
+      RmtDimmList->DimmEnabled  = TRUE;
+      CopyMem ((UINT8 *) &RmtSpdList->SpdData[0], (UINT8 *) SpdIn, 128);
+#if (defined SUPPORT_XMP && SUPPORT_XMP == SUPPORT)
+      CopyMem (&RmtSpdList->SpdData[128], ((UINT8 *) SpdIn) + 128, 128);
+#endif // (defined SUPPORT_XMP && SUPPORT_XMP == SUPPORT)
+      CopyMem ((UINT8 *) &RmtSpdList->SpdValid, (UINT8 *) &DimmIn->SpdValid, sizeof (RmtDimmList->SpdBytes.SpdValid));
+
+      //
+      // Initialize the memory rank area of the RMT_STRUCTURE.
+      //
+      MrcFillRmtRankStructure (&RmtDimmList->RankList[0], MrcData, Controller, Channel, Dimm);
+    } // end if
+  } // Dimm loop
+  return;
+}
+
+/**
+@brief
+  Initialize the memory channel area of the RMT_STRUCTURE.
+
+  @param[in, out] RmtChannel - Pointer to the start of the channel information in the RMT table.
+  @param[in] MrcData     - The MRC "global data".
+
+  @retval Nothing.
+**/
+void
+MrcFillRmtChannelStructure (
+  IN OUT RmtChannelList      *RmtChannel,
+  IN     const MrcParameters *MrcData,
+  IN     const UINT8         Controller
+  )
+{
+  const MrcOutput *Outputs;             // Pointer to the output portion of the MRC global data area.
+  RmtChannelList  *RmtChannelList;      // Pointer to the current channel in the RMT structure.
+  UINT8           Channel;              // Channel count for sequencing.
+
+  Outputs = &MrcData->SysOut.Outputs;
+  for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+    if (Outputs->Controller[Controller].Channel[Channel].Status == CHANNEL_PRESENT) {
+      RmtChannelList                  = &RmtChannel[Channel];
+      RmtChannelList->ChannelEnabled  = TRUE;
+      RmtChannelList->NumDimmSlot     = MAX_DIMMS_IN_CHANNEL;
+
+      //
+      // Initialize the memory DIMM area of the RMT_STRUCTURE.
+      //
+      MrcFillRmtDimmStructure (&RmtChannelList->DimmList[0], MrcData, Controller, Channel);
+    } // end if
+  } // Channel loop
+  return;
+}
+
+/**
+@brief
+  Initialize the memory controller area of the RMT_STRUCTURE.
+
+  @param[in, out] RmtController - Pointer to the start of the controller information in the RMT table.
+  @param[in] MrcData        - The MRC "global data".
+
+  @retval Nothing.
+**/
+void
+MrcFillRmtControllerStructure (
+  IN OUT RmtControllerList   *RmtController,
+  IN     const MrcParameters *MrcData
+  )
+{
+  const MrcInput    *Inputs;
+  const MrcOutput   *Outputs;
+  RmtControllerList *RmtControllerList;
+  UINT8             Controller;
+  MrcVddSelect      VddVoltage;
+
+  Inputs     = &MrcData->SysIn.Inputs;
+  Outputs    = &MrcData->SysOut.Outputs;
+  VddVoltage = Outputs->VddVoltage[Inputs->MemoryProfile];
+  for (Controller = 0; Controller < MAX_CONTROLLERS; Controller++) {
+    if (Outputs->Controller[Controller].Status == CONTROLLER_PRESENT) {
+      RmtControllerList                       = &RmtController[Controller];
+      RmtControllerList->ControllerEnabled    = TRUE;
+      RmtControllerList->ControllerDeviceId   = Outputs->Controller[Controller].DeviceId;
+      RmtControllerList->ControllerRevisionId = Outputs->Controller[Controller].RevisionId;
+      RmtControllerList->MemoryFrequency      = (UINT16) (Outputs->Frequency / 10);
+      RmtControllerList->MemoryVoltage        = (UINT16) VddVoltage;
+      //
+      // Step unit = piStep * (tCK / 2048)
+      //
+      RmtControllerList->PiStep               = (UINT8) PI_STEP;
+      RmtControllerList->RecvenStep           = (UINT8) PI_STEP;
+      RmtControllerList->WrLevelStep          = (UINT8) PI_STEP;
+      if (VddVoltage > 0) {
+        //
+        // Step unit = __VrefStep * Vdd / 100
+        //
+        RmtControllerList->RxVrefStep  = (UINT16) RX_VREF (VddVoltage);
+        RmtControllerList->TxVrefStep  = (UINT16) TX_VREF (VddVoltage);
+        RmtControllerList->CaVrefStep  = (UINT16) CA_VREF (VddVoltage);
+      } else {
+        RmtControllerList->RxVrefStep  = 0;
+        RmtControllerList->TxVrefStep  = 0;
+        RmtControllerList->CaVrefStep  = 0;
+      }
+      //
+      // Initialize the memory channel area of the RMT_STRUCTURE.
+      //
+      MrcFillRmtChannelStructure (&RmtControllerList->ChannelList[0], MrcData, Controller);
+    } // Controller loop
+  }
+
+  return;
+}
+
+/**
+@brief
+  Fill the compatible data structure RMT with the information provided by
+  the memory initialization code.
+
+  @param[in, out] MrcData - Constant pointer to the Mrc data structure which conatins the Rmt structure to fill.
+
+  @retval Nothing.
+**/
+MrcStatus
+MrcFillRmtStructure (
+  IN OUT MrcParameters *const MrcData
+  )
+{
+  const UINT8       RmtHeaderSign[] = {'B', 'D', 'A', 'T', 'H', 'E', 'A', 'D'};
+  const MrcVersion  *Version;             // Pointer to the output portion of the MRC global data area.
+  RmtData           *Rmt;
+  RmtHeader         *RmtHeader;           // Pointer to the header data area in the RMT structure.
+  RmtSystem         *RmtSystem;           // Pointer to the system data area in the RMT structure.
+  const MrcInput    *Inputs;
+  MrcOutput         *Outputs;
+
+  Inputs  = &MrcData->SysIn.Inputs;
+  Outputs = &MrcData->SysOut.Outputs;
+  if (Inputs->RmtBdatEnable) {
+    //
+    // Initialize the header area of the RMT_STRUCTURE.
+    //
+    Rmt       = &MrcData->Rmt;
+    RmtHeader = &Rmt->RmtHeader;
+    CopyMem (&RmtHeader->BiosDataSignature[0], (UINT8 *) RmtHeaderSign, sizeof (RmtHeader->BiosDataSignature));
+    RmtHeader->BiosDataStructSize           = sizeof (RmtData);
+    RmtHeader->Version.S[PRIMARY_OFFSET]    = RMT_PRIMARY_VERSION;
+    RmtHeader->Version.S[SECONDARY_OFFSET]  = RMT_SECONDARY_VERSION;
+    RmtHeader->OemOffset                    = OEM_OFFSET;
+    RmtHeader->Reserved1 = (Inputs->BaseTime.Hours << 16) | (Inputs->BaseTime.Minutes << 8) | Inputs->BaseTime.Seconds;
+    RmtHeader->Reserved2 = (Inputs->BaseTime.Year << 16) | (Inputs->BaseTime.Month << 8) | Inputs->BaseTime.DayOfMonth;
+
+    //
+    // Initialize the system area of the RMT_STRUCTURE.
+    //
+    Version                               = &Outputs->Version;
+    RmtSystem                             = &Rmt->RmtSystem;
+    RmtSystem->RefCodeRevision.c.Major    = Version->Major;
+    RmtSystem->RefCodeRevision.c.Minor    = Version->Minor;
+    RmtSystem->RefCodeRevision.c.Revision = Version->Rev;
+    RmtSystem->RefCodeRevision.c.Build    = Version->Build;
+    RmtSystem->MaxController              = MAX_CONTROLLERS;
+    RmtSystem->MaxChannel                 = MAX_CHANNEL;
+    RmtSystem->MaxDimm                    = MAX_DIMMS_IN_CHANNEL;
+    RmtSystem->MaxRankDimm                = MAX_RANK_IN_DIMM;
+    RmtSystem->MaxStrobe                  = MAX_STROBE;
+    RmtSystem->MaxDq                      = MAX_DQ;
+    RmtSystem->MarginLoopCount            = Outputs->DQPatLC;
+    //
+    // Initialize the memory controller area of the RMT_STRUCTURE.
+    //
+    MrcFillRmtControllerStructure (&RmtSystem->ControllerList[0], MrcData);
+
+    //
+    // Initialize the CRC of the RMT_STRUCTURE.
+    // Ensure that the CRC calculation is the last field initialized.
+    //
+    GetCrc16 ((const UINT8 *const) Rmt, sizeof (RmtData), &Rmt->RmtHeader.Crc16);
+    MrcOemMmioWrite (NCDECS_CR_SCRATCHPAD_NCU_2_REG, (U32) Rmt, Inputs->MchBarBaseAddress);
+  } // end if
+  return mrcSuccess;
+}
+#endif // BDAT_SUPPORT
diff --git a/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Api/MrcBdat.h b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Api/MrcBdat.h
new file mode 100644
index 0000000..a7232ae
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Api/MrcBdat.h
@@ -0,0 +1,45 @@
+/** @file
+  Copies the memory related timing and configuration information into the
+  Compatible BIOS data (BDAT) table.
+
+@copyright
+  Copyright (c) 2010 - 2012 Intel Corporation. All rights reserved.
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement.
+**/
+
+#ifndef _MrcBdat_h_
+#define _MrcBdat_h_
+#pragma pack(push, 1)
+
+#include "MrcTypes.h"
+#include "MrcApi.h"
+
+/**
+  Fill the compatible data structure RMT with the information provided by
+  the memory initialization code.
+
+  @param[in, out] MrcData - Constant pointer to the Mrc data structure which conatins the Rmt structure to fill.
+
+  @retval Nothing.
+**/
+extern
+MrcStatus
+MrcFillRmtStructure (
+  IN OUT MrcParameters *const MrcData
+  );
+
+#pragma pack(pop)
+#endif // _MrcBdat_h_
diff --git a/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Api/MrcGeneral.c b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Api/MrcGeneral.c
new file mode 100644
index 0000000..635c786
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Api/MrcGeneral.c
@@ -0,0 +1,1577 @@
+/** @file
+  This file all the MRC general API to the MRC wrapper.
+
+@copyright
+  Copyright (c) 1999 - 2013 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement
+
+**/
+#include "MrcGeneral.h"
+#include "MrcDdr3.h"
+const MrcVersion  cVersion = {
+#include "MrcVersion.h"
+};
+
+#ifdef ULT_FLAG
+//
+// This table is used for LPDDR3 MR5 decoding
+//
+struct {
+  U8    VendorId;
+  char  *VendorName;
+} DramVendorList [] = {
+  { 1, "Samsung" },
+  { 3, "Elpida"  },
+  { 6, "Hynix"   }
+};
+#endif // ULT_FLAG
+
+/**
+@brief
+  Thisfunction performs Software Memory testing
+
+  @param[in] MrcData - Include all MRC global data.
+
+  @retval Always returns mrcSuccess.
+**/
+MrcStatus
+MrcHwMemTest (
+  IN     MrcParameters *const MrcData
+  )
+{
+  MrcStatus             Status;
+
+  Status  = mrcSuccess;
+
+  return Status;
+}
+
+/**
+@brief
+  This function changes the MC to normal mode, enables the ECC if needed, lock configuration and set PU_MRC_Done.
+  If the ECC is enabled, this function should be called after memory is cleaned.
+
+  @param[in, out] MrcData - Include all MRC global data.
+
+  @retval Always returns mrcSuccess.
+**/
+MrcStatus
+MrcMcActivate (
+  IN     MrcParameters *const MrcData
+  )
+{
+  const MrcInput                            *Inputs;
+  const MrcDebug                            *Debug;
+  MrcOutput                                 *Outputs;
+  MrcControllerOut                          *ControllerOut;
+  MrcChannelOut                             *ChannelOut;
+  MrcCpuModel                               CpuModel;
+  MrcCpuStepping                            CpuStepping;
+  MCHBAR_CH0_CR_CMD_RATE_STRUCT             CmdRate;
+  DDRSCRAM_CR_DDRSCRAMBLECH0_STRUCT         DdrScramble;
+  MCDECS_CR_MAD_DIMM_CH0_MCMAIN_STRUCT      DimmCh0McMain;
+  MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_STRUCT ReutChSeqCfg;
+  PCU_CR_M_COMP_PCU_STRUCT                  MCompPcu;
+  MCHBAR_CH0_CR_TC_BANK_RANK_A_STRUCT       TcBankRankA;
+  U32                                       Offset;
+  U32                                       GeneratedSeed;
+  U8                                        Controller;
+  U8                                        Channel;
+  U8                                        Byte;
+  U32                                       BurstEndOdtDelay;
+#ifdef ULT_FLAG
+  U8                                        Rank;
+  U8                                        MaxRcvEn;
+  U8                                        RcvEnDrift;
+  U8                                        RcvEnTurnOff;
+  S8                                        OdtTurnOff;
+#endif // ULT_FLAG
+  BOOL                                      Lpddr;
+
+  Inputs        = &MrcData->SysIn.Inputs;
+  Outputs       = &MrcData->SysOut.Outputs;
+  Debug         = &Inputs->Debug;
+  GeneratedSeed = 0;
+  CpuModel      = Inputs->CpuModel;
+  CpuStepping   = Inputs->CpuStepping;
+  
+  //
+  // Oem hook before normal mode configuration starts
+  //
+  MrcOemCheckPoint (MrcData, OemBeforeNormalMode, NULL);
+
+  for (Controller = 0; Controller < MAX_CONTROLLERS; Controller++) {
+    ControllerOut = &Outputs->Controller[Controller];
+    for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+      if (!(MrcChannelExist (Outputs, Channel))) {
+        continue;
+      }
+
+      ChannelOut = &ControllerOut->Channel[Channel];
+
+      //
+      // Make sure tRDRD (sr, dr, dd) are above 6 for Scrambler W/A
+      //
+      if ((Inputs->ScramblerEnable == TRUE) &&
+          ((CpuModel == cmHSW     && CpuStepping < csHswC0)    ||
+           (CpuModel == cmHSW_ULT && CpuStepping < csHswUltC0) ||
+           (CpuModel == cmCRW     && CpuStepping < csCrwC0)
+          )
+         ) {
+        MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Increasing tRDRD(sr,dr,dd) by two:\n");
+
+        Offset = MCHBAR_CH0_CR_TC_BANK_RANK_A_REG +
+          (MCHBAR_CH1_CR_TC_BANK_RANK_A_REG - MCHBAR_CH0_CR_TC_BANK_RANK_A_REG) * Channel;
+
+        TcBankRankA.Data = MrcReadCR (MrcData, Offset);
+
+        MRC_DEBUG_MSG (
+          Debug,
+          MSG_LEVEL_NOTE,
+          "Initial Value: Channel %d\n tRDRD    = 0x%X\n tRDRD_dr = 0x%X\n tRDRD_dd = 0x%X\n",
+          Channel,
+          TcBankRankA.Bits.tRDRD,
+          TcBankRankA.Bits.tRDRD_dr,
+          TcBankRankA.Bits.tRDRD_dd
+          );
+
+        TcBankRankA.Bits.tRDRD    = MAX (TcBankRankA.Bits.tRDRD, 6);
+        TcBankRankA.Bits.tRDRD_dr = MAX (TcBankRankA.Bits.tRDRD_dr, 6);
+        TcBankRankA.Bits.tRDRD_dd = MAX (TcBankRankA.Bits.tRDRD_dd, 6);
+
+        MrcWriteCR (MrcData, Offset, TcBankRankA.Data);
+        ChannelOut->MchbarBANKRANKA = TcBankRankA.Data;
+
+        MRC_DEBUG_MSG (
+          Debug,
+          MSG_LEVEL_NOTE,
+          "New value: Channel %d\n tRDRD    = 0x%X\n tRDRD_dr = 0x%X\n tRDRD_dd = 0x%X\n",
+          Channel,
+          TcBankRankA.Bits.tRDRD,
+          TcBankRankA.Bits.tRDRD_dr,
+          TcBankRankA.Bits.tRDRD_dd
+          );
+      }
+
+      //
+      // Enable Scrambling
+      //
+      if (Inputs->ScramblerEnable == TRUE) {
+        GeneratedSeed = MrcGetRandomNumber ();
+        //
+        // Set Scramble key and enable bits
+        //
+        DdrScramble.Data          = 0;
+        DdrScramble.Bits.ScramKey = GeneratedSeed;
+        DdrScramble.Bits.ScramEn  = 1;
+        MrcWriteCR (
+          MrcData,
+          DDRSCRAM_CR_DDRSCRAMBLECH0_REG + ((DDRSCRAM_CR_DDRSCRAMBLECH1_REG - DDRSCRAM_CR_DDRSCRAMBLECH0_REG) * Channel),
+          DdrScramble.Data
+          );
+      }
+
+      //
+      // If we are in 1N mode, set Command Rate Limit to 3
+      //
+      if (ChannelOut->Timing[Inputs->MemoryProfile].NMode == 1) {
+        Offset = MCHBAR_CH0_CR_CMD_RATE_REG + ((MCHBAR_CH1_CR_CMD_RATE_REG - MCHBAR_CH0_CR_CMD_RATE_REG) * Channel);
+        CmdRate.Data = MrcReadCR (MrcData, Offset);
+        CmdRate.Bits.enable_cmd_rate_limit  = 1;
+        CmdRate.Bits.cmd_rate_limit         = 3;
+        CmdRate.Bits.enable_cmd_rate_limit  = Inputs->EnCmdRate & 1;
+        CmdRate.Bits.cmd_rate_limit         = Inputs->EnCmdRate >> 1;
+        MrcWriteCR (MrcData, Offset, CmdRate.Data);
+      }
+
+      //
+      // Enable the command tri state at the end of the training.
+      //
+      if (!Inputs->CmdTriStateDis) {
+        TcBankRankA.Data            = ChannelOut->MchbarBANKRANKA;
+        TcBankRankA.Bits.CMD_3st    = 0;
+        ChannelOut->MchbarBANKRANKA = TcBankRankA.Data;
+        MrcWriteCR (
+          MrcData,
+          MCHBAR_CH0_CR_TC_BANK_RANK_A_REG +
+          ((MCHBAR_CH1_CR_TC_BANK_RANK_A_REG - MCHBAR_CH0_CR_TC_BANK_RANK_A_REG) * Channel),
+          ChannelOut->MchbarBANKRANKA
+          );
+      }
+
+      //
+      // set MC to normal mode and clean the odt and cke.
+      //
+      ReutChSeqCfg.Data                     = 0;
+      ReutChSeqCfg.Bits.Initialization_Mode = NOP_Mode;
+      MrcWriteCR (
+        MrcData,
+        MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_REG +
+        ((MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_REG - MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_REG) * Channel),
+        (U32) ReutChSeqCfg.Data
+        );
+
+      //
+      // set again the rank occupancy
+      //
+      MrcWriteCR8 (
+        MrcData,
+        MCHBAR_CH0_CR_MC_INIT_STATE_REG + ((MCHBAR_CH1_CR_MC_INIT_STATE_REG - MCHBAR_CH0_CR_MC_INIT_STATE_REG) * Channel),
+        ChannelOut->ValidRankBitMask
+        );
+
+      //
+      // Set the MC to ECC mode for all channels if needed.
+      //
+      if (Outputs->EccSupport == TRUE) {
+        MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "ECC support\n");
+        Offset = MCDECS_CR_MAD_DIMM_CH0_MCMAIN_REG + ((MCDECS_CR_MAD_DIMM_CH1_MCMAIN_REG - MCDECS_CR_MAD_DIMM_CH0_MCMAIN_REG) * Channel);
+        DimmCh0McMain.Data      = MrcReadCR (MrcData, Offset);
+        DimmCh0McMain.Bits.ECC  = emBothActive;
+        MrcWriteCR (MrcData, Offset, DimmCh0McMain.Data);
+      }
+    }
+  }
+
+  //
+  // Check if LPDDR3 memory is used
+  //
+  Lpddr = (Outputs->DdrType == MRC_DDR_TYPE_LPDDR3);
+
+  //
+  // Update Odt timing, Samp timing and SlaveDLL to minimize power
+  // @todo TAT step is skipped on LPDDR for now.
+  //
+  if ((Inputs->TrainingEnables.TAT == 0) || Lpddr) {
+    UpdateSampOdtTiming (MrcData, 0);
+  }
+#ifdef TRAD_FLAG
+  //
+  // Update Internal clock setting
+  //
+  if ((CpuModel == cmHSW) || (CpuModel == cmCRW)) {
+    UpdateInternalClksOn (MrcData);
+  }
+#endif // TRAD_FLAG
+
+  UpdateSlaveDLLLength (MrcData);
+
+  //
+  // Program BurstEndODTDelay - it should be zero during training steps
+  //
+  BurstEndOdtDelay = ((14300 * 20) / 100 + Outputs->Qclkps / 2) / Outputs->Qclkps;
+  if (BurstEndOdtDelay > 7) {
+    BurstEndOdtDelay = 7;
+  }
+  if (BurstEndOdtDelay < 3) {
+    BurstEndOdtDelay = 0;
+  } else if (BurstEndOdtDelay < 4) {
+    BurstEndOdtDelay = 4;
+  }
+
+  for (Controller = 0; Controller < MAX_CONTROLLERS; Controller++) {
+    ControllerOut = &Outputs->Controller[Controller];
+    for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+      if (MrcChannelExist (Outputs, Channel)) {
+        ChannelOut = &ControllerOut->Channel[Channel];
+        for (Byte = 0; Byte < Outputs->SdramCount; Byte++) {
+          if (CpuModel == cmHSW_ULT) {
+            ChannelOut->DqControl1[Byte].Bits.BurstEndODTDelay = (Lpddr) ? 0 : BurstEndOdtDelay;  // Must be Disabled for LPDDR
+          } else if ((CpuModel == cmHSW) && (CpuStepping == csHswA0)) {
+            ChannelOut->DqControl1[Byte].Bits.BurstEndODTDelay = 0;
+          } else {
+            ChannelOut->DqControl1[Byte].Bits.BurstEndODTDelay = BurstEndOdtDelay;
+          }
+          Offset = DDRDATA0CH0_CR_DDRCRDATACONTROL1_REG +
+            ((DDRDATA1CH0_CR_DDRCRDATACONTROL1_REG - DDRDATA0CH0_CR_DDRCRDATACONTROL1_REG) * Byte) +
+            ((DDRDATA0CH1_CR_DDRCRDATACONTROL1_REG - DDRDATA0CH0_CR_DDRCRDATACONTROL1_REG) * Channel);
+          MrcWriteCR (MrcData, Offset, ChannelOut->DqControl1[Byte].Data);
+        }
+      }
+    }
+  }
+
+#ifdef ULT_FLAG
+  if (CpuModel == cmHSW_ULT) {
+    //
+    // Program RxClkStgNum
+    //
+    for (Controller = 0; Controller < MAX_CONTROLLERS; Controller++) {
+      ControllerOut = &Outputs->Controller[Controller];
+      for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+        if (!MrcChannelExist (Outputs, Channel)) {
+          continue;
+        }
+        ChannelOut = &ControllerOut->Channel[Channel];
+        MaxRcvEn   = 0;
+        for (Rank = 0; Rank < MAX_RANK_IN_CHANNEL; Rank++) {
+          if (!MrcRankInChannelExist (MrcData, Rank, Channel)) {
+            continue;
+          }
+          for (Byte = 0; Byte < Outputs->SdramCount; Byte++) {
+            MaxRcvEn = (U8) MAX (MaxRcvEn, ChannelOut->RcvEn[Rank][Byte] / 64);
+          }
+        }
+        RcvEnDrift   = (Lpddr) ? (U8) ((tDQSCK_DRIFT + Outputs->Qclkps - 1) / Outputs->Qclkps) : 1;
+        RcvEnTurnOff = MaxRcvEn + (5 - 6) + 1 + 7 + 3 + 3 + 2 + (2 * RcvEnDrift);
+
+        for (Byte = 0; Byte < Outputs->SdramCount; Byte++) {
+          if (ChannelOut->DqControl1[Byte].Bits.LpDdrLongOdtEn) {
+            RcvEnTurnOff ++;
+          }
+
+          OdtTurnOff = MrcSE ((U8) ChannelOut->DqControl1[Byte].Bits.OdtDelay, 4, 8) +
+                              (U8) ChannelOut->DqControl1[Byte].Bits.OdtDuration + 14;
+
+          ChannelOut->DqControl2[Byte].Bits.RxClkStgNum = (ChannelOut->DqControl0.Bits.OdtSampExtendEn) ?
+            MAX (ChannelOut->DqControl2[Byte].Bits.RxClkStgNum, RcvEnTurnOff) : MAX (17, OdtTurnOff);
+          Offset = DDRDATA0CH0_CR_DDRCRDATACONTROL2_REG +
+            ((DDRDATA0CH1_CR_DDRCRDATACONTROL2_REG - DDRDATA0CH0_CR_DDRCRDATACONTROL2_REG) * Channel) +
+            ((DDRDATA1CH0_CR_DDRCRDATACONTROL2_REG - DDRDATA0CH0_CR_DDRCRDATACONTROL2_REG) * Byte);
+          MrcWriteCR (MrcData, Offset, ChannelOut->DqControl2[Byte].Data);
+        }
+      }
+    }
+  
+    //
+    // Program DDRPL_CR_DDR_TX_DELAY if Memory Trace is enabled
+    //
+    MrcSetDdrplTxDelay (MrcData);
+  }
+#endif // ULT_FLAG
+
+  //
+  // Enable Periodic Comp with periodic internal = 10uS*2^COMP_INT
+  //
+  MCompPcu.Data               = 0;
+  MCompPcu.Bits.COMP_INTERVAL = COMP_INT;
+  MrcWriteCR (MrcData, PCU_CR_M_COMP_PCU_REG, MCompPcu.Data);
+
+  //
+  // Enable the power mode before PCU start working.
+  //
+  MrcPowerModesPostTraining (MrcData);
+
+  //
+  // Set Idle timer and Self Refresh enable bits
+  //
+  EnterSR (MrcData);
+
+  //
+  // Oem hook when normal mode configuration is done
+  //
+  MrcOemCheckPoint (MrcData, OemAfterNormalMode, (void *) &Inputs->McLock);
+
+  if (Inputs->ThermalEnables.UserPowerWeightsEn == 0) {
+    //
+    // Apply power weight values
+    //
+    MrcPowerWeight (MrcData);
+  }
+
+  return mrcSuccess;
+}
+
+/**
+@brief
+  This function enables Normal Mode and configures the Power Down Modes
+  for the boot flows other than Cold Boot.
+
+  @param[in] MrcData - The MRC general data.
+
+  @retval Always returns mrcSuccess.
+**/
+MrcStatus
+MrcNormalMode (
+  IN MrcParameters *const MrcData
+  )
+{
+  MrcOutput *Outputs;
+  U8  Channel;
+  MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_STRUCT ReutChSeqCfg;
+  PCU_CR_M_COMP_PCU_STRUCT                  MCompPcu;
+
+  Outputs = &MrcData->SysOut.Outputs;
+
+  //
+  // Enable Periodic Comp with periodic internal = 10uS*2^COMP_INT
+  //
+  MCompPcu.Data               = 0;
+  MCompPcu.Bits.COMP_INTERVAL = COMP_INT;
+  MrcWriteCR (MrcData, PCU_CR_M_COMP_PCU_REG, MCompPcu.Data);
+  //
+  // Set Normal Operation Mode.
+  //
+  for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+    if (MrcChannelExist (Outputs, Channel)) {
+      ReutChSeqCfg.Data                     = 0;
+      ReutChSeqCfg.Bits.Initialization_Mode = NOP_Mode;
+      MrcWriteCR (
+        MrcData,
+        MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_REG +
+        ((MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_REG - MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_REG) * Channel),
+        (U32) ReutChSeqCfg.Data
+        );
+    }
+  }
+
+  //
+  // Configure Power Down CR
+  //
+  MrcPowerDownConfig (MrcData);
+
+  return mrcSuccess;
+}
+
+/**
+@brief
+  this function is the last funtion that call from the MRC core.
+    the function set DISB and set the MRC_Done.
+
+  @param[in] MrcData - include all the MRC general data.
+
+  @retval Always returns mrcSuccess.
+**/
+MrcStatus
+MrcDone (
+  IN     MrcParameters *const MrcData
+  )
+{
+  const MrcInput                          *Inputs;
+  const MrcDebug                          *Debug;
+  MCDECS_CR_MC_INIT_STATE_G_MCMAIN_STRUCT McInitStateG;
+#ifdef ULT_FLAG
+  MrcOutput                               *Outputs;
+  U32                                     Channel;
+  U32                                     Rank;
+  U8                                      MrrResult[4];
+  U32                                     MrAddr;
+  U32                                     Device;
+  U32                                     Index;
+#endif //ULT_FLAG
+
+  Inputs  = &MrcData->SysIn.Inputs;
+  Debug   = &Inputs->Debug;
+
+#ifdef ULT_FLAG
+  //
+  // LPDDR: Read MR5 and MR8
+  //
+  Outputs = &MrcData->SysOut.Outputs;
+  if (Outputs->DdrType == MRC_DDR_TYPE_LPDDR3) {
+    for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+      for (Rank = 0; Rank < MAX_RANK_IN_CHANNEL; Rank++) {
+        if (!MrcRankInChannelExist (MrcData, (U8) Rank, (U8) Channel)) {
+          continue;
+        }
+
+        //
+        // MR5 - Manufacturer ID
+        //
+        MrAddr = 5;
+        MrcIssueMrr (MrcData, Channel, Rank, MrAddr, MrrResult);
+        for (Device = 0; Device < 4; Device++) {
+          MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\tDevice[%d]= 0x%02X", Device, MrrResult[Device]);
+          for (Index = 0; Index < sizeof (DramVendorList) / sizeof (DramVendorList[0]); Index++) {
+            if (DramVendorList[Index].VendorId == MrrResult[Device]) {
+              MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, " %s\n", DramVendorList[Index].VendorName);
+            }
+          }
+        }
+
+        //
+        // MR8 - I/O Width, Density, Type
+        //
+        MrAddr = 8;
+        MrcIssueMrr (MrcData, Channel, Rank, MrAddr, MrrResult);
+        for (Device = 0; Device < 4; Device++) {
+          MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\tDevice[%d]= 0x%02X - %s\n", Device, MrrResult[Device],
+            (MRC_BIT6 & MrrResult[Device]) ? "x16" : "x32");
+        }
+      }
+    }
+  }
+#endif //ULT_FLAG
+
+  //
+  // Set Idle timer and Self Refresh enable bits
+  //  EnterSR (MrcData);
+  //
+  McInitStateG.Data = MrcReadCR (MrcData, MCDECS_CR_MC_INIT_STATE_G_MCMAIN_REG);
+  //
+  // Set refresh enable Bit
+  //
+  McInitStateG.Bits.refresh_enable = 1;
+
+  //
+  // used to know what is the state of the boot mode.
+  //
+  McInitStateG.Bits.pu_mrc_done = 1;
+
+  //
+  // set the MRC_Done bit.
+  //
+  McInitStateG.Bits.mrc_done = 1;
+
+  MrcWriteCR (MrcData, MCDECS_CR_MC_INIT_STATE_G_MCMAIN_REG, McInitStateG.Data);
+
+  //
+  // lock the MC and memory map registers.
+  //
+    McRegistersLock (MrcData);
+
+  //
+  // Poll for to make sure MRC is complete
+  //
+  // wait for mc_init_done
+  // @TODO: Possible infinite loop. Need to add a timeout counter/error handler.
+  //
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Waiting for mc_init_done Acknowledge\n");
+  do {
+    McInitStateG.Data = MrcReadCR (MrcData, MCDECS_CR_MC_INIT_STATE_G_MCMAIN_REG);
+  } while (McInitStateG.Bits.mc_init_done_ack == 0);
+  //
+  // move the MRC data to the graphics driver.
+  //
+  MrcWmRegSet (MrcData);
+  return mrcSuccess;
+}
+
+/**
+@brief
+  Print the MRC version to the MRC output device.
+
+  @param[in] Debug   - Pointer to the MRC Debug structure.
+  @param[in] Version - The MRC version.
+
+  @retval Nothing.
+**/
+void
+MrcVersionPrint (
+  IN const MrcParameters *MrcData,
+  IN const MrcVersion    *Version
+  )
+{
+#ifdef MRC_DEBUG_PRINT
+  const MrcDebug *Debug;
+
+  Debug = &MrcData->SysIn.Inputs.Debug;
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE,  "*********************************************************************\n");
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE,  "** Copyright (c) 2011-2012 Intel Corporation. All rights reserved. **\n");
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_ERROR, "** Haswell memory detection and initialization code.               **\n");
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_ERROR, "** Major version number is:   %2u                                   **\n", Version->Major);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_ERROR, "** Minor version number is:   %2u                                   **\n", Version->Minor);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_ERROR, "** Rev version number is:     %2u                                   **\n", Version->Rev);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_ERROR, "** Build number is:           %2u                                   **\n", Version->Build);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE,  "*********************************************************************\n");
+#endif
+  return;
+}
+
+/**
+@brief
+  This function return the MRC version.
+
+  @param[out] Version - Location to store the MRC version.
+
+  @retval Nothing.
+**/
+void
+MrcVersionGet (
+     OUT MrcVersion *const Version
+  )
+{
+  if (Version != NULL) {
+    MrcOemMemoryCpy ((U8 *) Version, (U8 *) &cVersion, sizeof (MrcVersion));
+  }
+}
+
+/**
+@brief
+  This function set the MRC vertion to MCDECS_SPARE register.
+  The function need to be call by the wrapper after MrcStartMemoryConfiguration function where the MC CLK enable.
+  The function write:
+  Major number to bits 16-23
+  Minor number to bits 8-15
+  Build number to bits 0 - 7
+
+  @param[in] MrcData - Include all MRC global data.
+
+  @retval Nothing.
+**/
+MrcStatus
+MrcSetMrcVersion (
+  IN     MrcParameters *const MrcData
+  )
+{
+  MrcVersion const                      *Version;
+  MCDECS_CR_MRC_REVISION_MCMAIN_STRUCT  MrcRevision;
+
+  Version = &MrcData->SysOut.Outputs.Version;
+  MrcRevision.Data = (((U32) Version->Major) << 24) |
+                     (((U32) Version->Minor) << 16) |
+                     (((U32) Version->Rev)   << 8)  |
+                     (((U32) Version->Build));
+
+  MrcWriteCR (MrcData, MCDECS_CR_MRC_REVISION_MCMAIN_REG, MrcRevision.Data);
+  return mrcSuccess;
+}
+
+/**
+@brief
+  This function locks the memory controller and memory map registers.
+
+  @param[in] MrcData - Include all MRC global data.
+
+  @retval Nothing.
+**/
+void
+McRegistersLock (
+  IN     MrcParameters *const MrcData
+  )
+{
+  const MrcInput                  *Inputs;
+  MCDECS_CR_MC_LOCK_MCMAIN_STRUCT McLock;
+  MRC_PCI_000_TOM_STRUCT          Tom;
+  MRC_PCI_000_TOLUD_STRUCT        Tolud;
+  MRC_PCI_000_TOUUD_STRUCT        Touud;
+  MRC_PCI_000_REMAPBASE_STRUCT    RemapBase;
+  MRC_PCI_000_REMAPLIMIT_STRUCT   RemapLimit;
+//  MRC_PCI_000_TSEGMB_STRUCT       Tsegmb;
+  MRC_PCI_000_BDSM_STRUCT         Bdsm;
+  MRC_PCI_000_BGSM_STRUCT         Bgsm;
+  MRC_PCI_000_MESEG_MASK_STRUCT   MeSegMask;
+  MRC_PCI_000_GGC_STRUCT          Ggc;
+  PCU_CR_DDR_PTM_CTL_PCU_STRUCT   DdrPtmCtl;
+  U32                             Offset;
+
+  Inputs = &MrcData->SysIn.Inputs;
+
+  //
+  // Lock the memory controller registers.
+  //
+  McLock.Data                   = 0;
+  McLock.Bits.lock_addr_map     = 1;
+  McLock.Bits.lock_mc_config    = 1;
+  McLock.Bits.lock_iosav_init   = 1;
+  McLock.Bits.lock_pwr_mngment  = 1;
+  McLock.Bits.lock_mc_dft       = 1;
+  MrcWriteCR (MrcData, MCDECS_CR_MC_LOCK_MCMAIN_REG, McLock.Data);
+
+  MRC_DEBUG_MSG (&Inputs->Debug, MSG_LEVEL_NOTE, "\nMemory controller config is locked\n");
+
+  if (Inputs->McLock) {
+    //
+    // Lock the memory map registers.
+    // Lock TOM.
+    //
+    Offset = MrcOemGetPcieDeviceAddress (0, 0, 0, MRC_PCI_000_TOM_REG);
+    MrcOemMmioRead (Offset, &Tom.Data32.Low.Data, Inputs->PciEBaseAddress);
+    Tom.Data32.Low.Bits.Lock = 1;
+    MrcOemMmioWrite (Offset, Tom.Data32.Low.Data, Inputs->PciEBaseAddress);
+
+    //
+    // Lock TOLUD.
+    //
+    Offset = MrcOemGetPcieDeviceAddress (0, 0, 0, MRC_PCI_000_TOLUD_REG);
+    MrcOemMmioRead (Offset, &Tolud.Data, Inputs->PciEBaseAddress);
+    Tolud.Bits.Lock = 1;
+    MrcOemMmioWrite (Offset, Tolud.Data, Inputs->PciEBaseAddress);
+
+    //
+    // Lock TOUUD.
+    //
+    Offset = MrcOemGetPcieDeviceAddress (0, 0, 0, MRC_PCI_000_TOUUD_REG);
+    MrcOemMmioRead (Offset, &Touud.Data32.Low.Data, Inputs->PciEBaseAddress);
+    Touud.Data32.Low.Bits.Lock = 1;
+    MrcOemMmioWrite (Offset, Touud.Data32.Low.Data, Inputs->PciEBaseAddress);
+
+    //
+    // Lock REMAPBASE.
+    //
+    Offset = MrcOemGetPcieDeviceAddress (0, 0, 0, MRC_PCI_000_REMAPBASE_REG);
+    MrcOemMmioRead (Offset, &RemapBase.Data32.Low.Data, Inputs->PciEBaseAddress);
+    RemapBase.Data32.Low.Bits.Lock = 1;
+    MrcOemMmioWrite (Offset, RemapBase.Data32.Low.Data, Inputs->PciEBaseAddress);
+
+    //
+    // Lock REMAPLIMIT.
+    //
+    Offset = MrcOemGetPcieDeviceAddress (0, 0, 0, MRC_PCI_000_REMAPLIMIT_REG);
+    MrcOemMmioRead (Offset, &RemapLimit.Data32.Low.Data, Inputs->PciEBaseAddress);
+    RemapLimit.Data32.Low.Bits.Lock = 1;
+    MrcOemMmioWrite (Offset, RemapLimit.Data32.Low.Data, Inputs->PciEBaseAddress);
+
+    //
+    // @todo:  - Confirm if this has been fixed and are who is locking TSEGMB
+    // Lock TSEGMB.
+    // Rapid Start requires TSEG_BASE access so do not lock it here.
+    //
+    //  Offset = MrcOemGetPcieDeviceAddress (0, 0, 0, MRC_PCI_000_TSEGMB_REG);
+    //  MrcOemMmioRead (Offset, &Tsegmb.Data, Inputs->PciEBaseAddress);
+    //  Tsegmb.Bits.Lock = 1;
+    //  MrcOemMmioWrite (Offset, Tsegmb.Data, Inputs->PciEBaseAddress);
+
+    //
+    // Lock DPR register
+    // Rapid Start requires DPR access so do not lock it here.
+    // System Agent RC SaSecurityLock() will lock it during ExitPmAuth callback
+    //
+
+    //
+    // Lock BDSM.
+    //
+    Offset = MrcOemGetPcieDeviceAddress (0, 0, 0, MRC_PCI_000_BDSM_REG);
+    MrcOemMmioRead (Offset, &Bdsm.Data, Inputs->PciEBaseAddress);
+    Bdsm.Bits.Lock = 1;
+    MrcOemMmioWrite (Offset, Bdsm.Data, Inputs->PciEBaseAddress);
+
+    //
+    // Lock BGSM.
+    //
+    Offset = MrcOemGetPcieDeviceAddress (0, 0, 0, MRC_PCI_000_BGSM_REG);
+    MrcOemMmioRead (Offset, &Bgsm.Data, Inputs->PciEBaseAddress);
+    Bgsm.Bits.Lock = 1;
+    MrcOemMmioWrite (Offset, Bgsm.Data, Inputs->PciEBaseAddress);
+
+    //
+    // Lock MESEG_MASK.
+    //
+    Offset = MrcOemGetPcieDeviceAddress (0, 0, 0, MRC_PCI_000_MESEG_MASK_REG);
+    MrcOemMmioRead (Offset, &MeSegMask.Data32.Low.Data, Inputs->PciEBaseAddress);
+    MeSegMask.Data32.Low.Bits.Lock = 1;
+    MrcOemMmioWrite (Offset, MeSegMask.Data32.Low.Data, Inputs->PciEBaseAddress);
+
+    //
+    // Lock GGC.
+    //
+    Offset = MrcOemGetPcieDeviceAddress (0, 0, 0, MRC_PCI_000_GGC_REG);
+    MrcOemMmioRead (Offset, &Ggc.Data, Inputs->PciEBaseAddress);
+    Ggc.Bits.Ggclck = 1;
+    MrcOemMmioWrite (Offset, Ggc.Data, Inputs->PciEBaseAddress);
+
+    //
+    // Lock POWER THERMAL MANAGEMENT CONTROL
+    //
+    DdrPtmCtl.Data                   = MrcReadCR (MrcData, PCU_CR_DDR_PTM_CTL_PCU_REG);
+    DdrPtmCtl.Bits.LOCK_PTM_REGS_PCU = Inputs->ThermalEnables.LockPTMregs;
+    MrcWriteCR (MrcData, PCU_CR_DDR_PTM_CTL_PCU_REG, DdrPtmCtl.Data);
+
+    MRC_DEBUG_MSG (&Inputs->Debug, MSG_LEVEL_NOTE, "\nMemory map registers are locked\n");
+    }
+
+  return;
+}
+
+/**
+@brief
+  This function returns the recommended MRC boot mode.
+
+  @param[in] void - No arguments
+
+  @retval bmWarm if we are in self refresh and the DISB bit is set, otherwise returns bmCold.
+**/
+MrcBootMode
+MrcGetBootMode (
+  void
+  )
+{
+  MrcBootMode BootMode;
+  U32         Register;
+  U32         ioAddress;
+
+  ioAddress = (U32) MrcOemGetPciDeviceAddress (
+                      GENERAL_PM_CONFIGURATION_2_BUS_ADDRESS,
+                      GENERAL_PM_CONFIGURATION_2_DEVICE_ADDRESS,
+                      GENERAL_PM_CONFIGURATION_2_FUNCTION_ADDRESS,
+                      GENERAL_PM_CONFIGURATION_2
+                      );
+
+  MrcOemOutPort32 (MrcOemPciIndex (), ioAddress);
+  //
+  // We read 32 bits but we need only 8 bits of GENERAL_PM_CONFIGURATION_2 that start at offset 0xA2 and not 0xA0.
+  //
+  Register = (MrcOemInPort32 (MrcOemPciData ()) >> 16);
+
+  if ((Register & GENERAL_PM_CONFIGURATION_2_MEM_SR_MASK) == GENERAL_PM_CONFIGURATION_2_MEM_SR_MASK &&
+      (Register & GENERAL_PM_CONFIGURATION_2_DISB_MASK) == GENERAL_PM_CONFIGURATION_2_DISB_MASK
+      ) {
+    BootMode = bmWarm;
+  } else {
+    BootMode = bmCold;
+  }
+
+  return BootMode;
+}
+//
+// @todo:  - Need to find out if we need it for PCH used in HSW timeframe
+//
+/**
+@brief
+  This function sets the DISB bit in General PM Configuration 2 B:D:F 0,31,0 offset 0xA2.
+
+  @param[in] void - No arguments
+
+  @retval Nothing.
+**/
+void
+MrcSetDISB (
+  void
+  )
+{
+  U32 Register;
+  U32 ioAddress;
+
+  ioAddress = (U32) MrcOemGetPciDeviceAddress (
+                      GENERAL_PM_CONFIGURATION_2_BUS_ADDRESS,
+                      GENERAL_PM_CONFIGURATION_2_DEVICE_ADDRESS,
+                      GENERAL_PM_CONFIGURATION_2_FUNCTION_ADDRESS,
+                      GENERAL_PM_CONFIGURATION_2
+                      );
+
+  MrcOemOutPort32 (MrcOemPciIndex (), ioAddress);
+  Register = MrcOemInPort32 (MrcOemPciData ());
+
+  //
+  // GENERAL_PM_CONFIGURATION_2 start in A2 and not in A0.
+  //
+  Register |= (GENERAL_PM_CONFIGURATION_2_DISB_MASK << 16);
+
+  MrcOemOutPort32 (MrcOemPciIndex (), ioAddress);
+  MrcOemOutPort32 (MrcOemPciData (), Register);
+}
+
+/**
+@brief
+  This function resets the DISB bit in General PM Configuration 2 B:D:F 0,31,0 offset 0xA2.
+
+  @param[in] void - No arguments
+
+  @retval Nothing.
+**/
+void
+MrcResetDISB (
+  void
+  )
+{
+  U32 Register;
+  U32 ioAddress;
+
+  ioAddress = (U32) MrcOemGetPciDeviceAddress (
+                      GENERAL_PM_CONFIGURATION_2_BUS_ADDRESS,
+                      GENERAL_PM_CONFIGURATION_2_DEVICE_ADDRESS,
+                      GENERAL_PM_CONFIGURATION_2_FUNCTION_ADDRESS,
+                      GENERAL_PM_CONFIGURATION_2
+                      );
+
+  MrcOemOutPort32 (MrcOemPciIndex (), ioAddress);
+  Register = MrcOemInPort32 (MrcOemPciData ());
+
+  //
+  // GENERAL_PM_CONFIGURATION_2 address is A2 and not A0.
+  //
+  Register &= ((~(GENERAL_PM_CONFIGURATION_2_DISB_MASK)) << 16);
+
+  MrcOemOutPort32 (MrcOemPciIndex (), ioAddress);
+  MrcOemOutPort32 (MrcOemPciData (), Register);
+}
+
+/**
+@brief
+  This function reads the CAPID0 register and sets the memory controller's capability.
+
+  @param[in, out] MrcData - All the MRC global data.
+
+  @retval Returns mrcSuccess if the memory controller's capability has been determined, otherwise returns mrcFail.
+**/
+MrcStatus
+MrcMcCapability (
+  IN OUT MrcParameters *const MrcData
+  )
+{
+  const MrcInput            *Inputs;
+  const MrcDebug            *Debug;
+  MrcSaveData               *Save;
+  MrcOutput                 *Outputs;
+  MrcControllerOut          *ControllerOut;
+  MrcChannelOut             *ChannelOut;
+  MrcDimmOut                *DimmOut;
+  BOOL                      EccSupport;
+  BOOL                      IgnoreNonEccDimm;
+  MRC_PCI_000_CAPID0_STRUCT Capid0Reg;
+  MRC_PCI_000_DEVEN_STRUCT  Deven;
+  MrcProfile                Profile;
+  U32                       ChannelCount;
+  U32                       DimmCount;
+  U32                       Max;
+  U32                       Size;
+  U32                       ChannelNum;
+  U32                       DimmNum;
+  U32                       ChDimmCount;
+  U32                       Offset;
+  U16                       NModeMinimum;
+  U8                        Controller;
+  U8                        Channel;
+  U8                        Dimm;
+
+  Inputs      = &MrcData->SysIn.Inputs;
+  Outputs     = &MrcData->SysOut.Outputs;
+  Save        = &MrcData->SysSave.Save.Data;
+  Debug       = &Inputs->Debug;
+  ChDimmCount = MAX_DIMMS_IN_CHANNEL;
+  Profile     = Inputs->MemoryProfile;
+
+  //
+  // Obtain the capabilities of the memory controller.
+  //
+  Offset = MrcOemGetPcieDeviceAddress (0, 0, 0, MRC_PCI_000_CAPID0_REG);
+  MrcOemMmioRead (Offset, &Capid0Reg.Data32.A.Data, Inputs->PciEBaseAddress);
+  MrcOemMmioRead (Offset + 4, &Capid0Reg.Data32.B.Data, Inputs->PciEBaseAddress);
+  Save->McCapId.Data  = Capid0Reg.Data;
+
+  Offset              = MrcOemGetPcieDeviceAddress (0, 0, 0, MRC_PCI_000_DEVEN_REG);
+  MrcOemMmioRead (Offset, &Deven.Data, Inputs->PciEBaseAddress);
+
+  //
+  // Determine if the internal graphics engine is supported.
+  //
+  if ((Capid0Reg.Data32.A.Bits.IGD == 0) && (Deven.Bits.D2EN > 0)) {
+    Outputs->GraphicsStolenSize = Inputs->GraphicsStolenSize;
+    Outputs->GraphicsGttSize    = Inputs->GraphicsGttSize;
+  } else {
+    Outputs->GraphicsStolenSize = 0;
+    Outputs->GraphicsGttSize    = 0;
+  }
+
+  MRC_DEBUG_MSG (
+    Debug,
+    MSG_LEVEL_NOTE,
+    "Memory allocated for IGD = %uMB and for GTT = %uMB.\n",
+    Outputs->GraphicsStolenSize,
+    Outputs->GraphicsGttSize
+    );
+
+  //
+  // Determine the maximum size of memory per channel, based on fuses.
+  //
+  switch (Capid0Reg.Data32.A.Bits.DDRSZ) {
+  case tcs16GB:
+    Outputs->MrcTotalChannelLimit = (16 * 1024);
+    break;
+
+  case tcs8GB:
+    Outputs->MrcTotalChannelLimit = (8 * 1024);
+    break;
+
+  case tcs2GB:
+    Outputs->MrcTotalChannelLimit = (2 * 1024);
+    break;
+
+  case tcs512MB:
+  default:
+    Outputs->MrcTotalChannelLimit = (512);
+    break;
+  }
+
+  MRC_DEBUG_MSG (
+    Debug,
+    MSG_LEVEL_NOTE,
+    "Maximum size of memory allowed on a channel = %uMB.\n",
+    Outputs->MrcTotalChannelLimit
+    );
+
+  //
+  // Determine how many channels are supported on this memory controller,
+  // based on fuse and how many channels have DIMMs installed.
+  //
+  ChannelCount  = (Capid0Reg.Data32.A.Bits.PDCD == 0) ? MAX_CHANNEL : 1;
+  DimmCount     = (Capid0Reg.Data32.A.Bits.DDPCD == 0) ? MAX_DIMMS_IN_CHANNEL : 1;
+
+#ifdef ULT_FLAG
+  if (Inputs->CpuModel == cmHSW_ULT) {
+    //
+    // Only 1DPC is supported on ULT platform
+    //
+    DimmCount = 1;
+  }
+#endif // ULT_FLAG
+
+#ifdef EMBEDDED_FLAG
+  if (Inputs->BoardType == btCRBEMB) {
+    //
+    // Only 1DPC is supported on EMBEDDED platform
+    //
+    DimmCount = 1;
+  }
+#endif
+
+  MRC_DEBUG_MSG (
+    Debug,
+    MSG_LEVEL_NOTE,
+    "Number of channels supported = %u\nNumber of DIMMs per channel supported = %u\n",
+    ChannelCount,
+    DimmCount
+    );
+
+  //
+  // Determine the minimum NMode supported on this memory controller.
+  //
+  NModeMinimum = (Capid0Reg.Data32.A.Bits.D1NM == 0) ? 1 : 2;
+
+  //
+  // Determine the ECC capability of the memory controller.
+  //
+  IgnoreNonEccDimm = (Capid0Reg.Data32.A.Bits.FDEE == 0) ? FALSE : TRUE;
+
+  //
+  // Set EccSupport flag to TRUE if we must NOT ignore ECC DIMMs
+  //
+  if (IgnoreNonEccDimm == TRUE) {
+    Outputs->EccSupport = TRUE;
+    EccSupport = TRUE; // FDEE has presedence over ECCDIS
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "ALL DIMMs MUST be ECC capable\n");
+  } else {
+    EccSupport = ((Capid0Reg.Data32.A.Bits.ECCDIS > 0) || (Outputs->EccSupport == FALSE)) ? FALSE : TRUE;
+  }
+  //
+  // Now copy ECC and NMode information to the channel and DIMM results.
+  //
+  for (Controller = 0; Controller < MAX_CONTROLLERS; Controller++) {
+    ControllerOut = &Outputs->Controller[Controller];
+    for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+      ChannelOut = &ControllerOut->Channel[Channel];
+      if (ChannelOut->Status == CHANNEL_PRESENT) {
+        if ((NModeMinimum >= 2) ||
+          ((Inputs->MemoryProfile == STD_PROFILE) &&
+          ((Outputs->Frequency > f1867) || ((ChannelOut->DimmCount >= 2) && (Outputs->Frequency >= f1333))))) {
+          ChannelOut->Timing[Profile].NMode = MAX (2, ChannelOut->Timing[Profile].NMode);
+        }
+        for (Dimm = 0; Dimm < MAX_DIMMS_IN_CHANNEL; Dimm++) {
+          DimmOut = &ChannelOut->Dimm[Dimm];
+          if (DimmOut->Status == DIMM_PRESENT) {
+            DimmOut->Timing[Profile].NMode = ChannelOut->Timing[Profile].NMode;
+            MRC_DEBUG_MSG (
+              Debug,
+              MSG_LEVEL_NOTE,
+              "  %s %u/%u/%u NMode = %u\n",
+              CcdString,
+              Controller,
+              Channel,
+              Dimm,
+              DimmOut->Timing[Profile].NMode
+            );
+            if (EccSupport == TRUE) {
+              if ((DimmOut->EccSupport == FALSE) && (IgnoreNonEccDimm == TRUE)) {
+                DimmOut->Status = DIMM_DISABLED;
+                MRC_DEBUG_MSG (
+                  Debug,
+                  MSG_LEVEL_NOTE,
+                  "  %s %u/%u/%u Disabling non-ECC capable DIMM\n",
+                  CcdString,
+                  Controller,
+                  Channel,
+                  Dimm
+                  );
+              } else if (DimmOut->EccSupport == TRUE) {
+                DimmOut->EccSupport = TRUE;
+                DimmOut->SdramCount = MAX_SDRAM_IN_DIMM;
+              } else {
+                DimmOut->SdramCount = MAX_SDRAM_IN_DIMM - 1;
+                Outputs->EccSupport = FALSE; // Final ECCSupport must be disabled if one DIMM is NOT capable
+              }
+            } else {
+              DimmOut->EccSupport = FALSE;
+              DimmOut->SdramCount = MAX_SDRAM_IN_DIMM - 1;
+              Outputs->EccSupport = FALSE; // Final ECCSupport must be disabled if ECCDIS is set
+            }
+          }
+        }
+      }
+    }
+  }
+
+  //
+  // Update FInal SdramCount
+  //
+  Outputs->SdramCount = (Outputs->EccSupport == TRUE) ? MAX_SDRAM_IN_DIMM : (MAX_SDRAM_IN_DIMM - 1);
+
+  //
+  // Determine the size of memory in each channel.
+  // Also determine the channel with the largest amount.
+  //
+  Max = ChannelNum = Outputs->MemoryMapData.TotalPhysicalMemorySize = 0;
+  for (Controller = 0; Controller < MAX_CONTROLLERS; Controller++) {
+    ControllerOut = &Outputs->Controller[Controller];
+    for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+      ChannelOut = &ControllerOut->Channel[Channel];
+      Size        = 0;
+      if (ChannelOut->Status == CHANNEL_PRESENT) {
+        for (Dimm = 0; Dimm < MAX_DIMMS_IN_CHANNEL; Dimm++) {
+          DimmOut = &ChannelOut->Dimm[Dimm];
+          if (DimmOut->Status == DIMM_PRESENT) {
+            Size += DimmOut->DimmCapacity;
+          }
+        }
+
+        ChannelOut->Capacity = Size;
+        if (Size > Max) {
+          Max         = Size;
+          ChannelNum  = Channel;
+          ChDimmCount = ChannelOut->DimmCount;
+        } else if ((Size == Max) && (DimmCount == 1)) {
+          //
+          // Choose channel with least amount of DIMMs if 2DPC is disabled
+          //
+          if (ChannelOut->DimmCount < ChDimmCount) {
+            ChDimmCount = ChannelOut->DimmCount;
+            ChannelNum  = Channel;
+          }
+        }
+      }
+
+      Outputs->MemoryMapData.TotalPhysicalMemorySize += ChannelOut->Capacity;
+    }
+  }
+
+  if (ChannelCount == 1) {
+    //
+    // Determine which channels are supported on this memory controller.
+    // If fused for one channel, we pick the channel with the most memory.
+    //
+    for (Controller = 0; Controller < MAX_CONTROLLERS; Controller++) {
+      ControllerOut = &Outputs->Controller[Controller];
+      for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+        ChannelOut = &ControllerOut->Channel[Channel];
+        if ((ChannelOut->Status == CHANNEL_PRESENT) && (Channel != ChannelNum)) {
+          //
+          // Disable Channel don't skip DIMM capacity
+          //
+          MrcChannelDisable (MrcData, (U8) Channel, 0);
+        }
+      }
+
+      MRC_DEBUG_MSG (
+        Debug,
+        MSG_LEVEL_NOTE,
+        "Controller configured to one channel, we've selected channel %u.\n",
+        ChannelNum
+        );
+    }
+  }
+
+  if (DimmCount == 1) {
+    //
+    // Determine which DIMMs are supported on this memory controller.
+    // If fused for one DIMM per channel, we pick the DIMM in a channel with the most memory.
+    //
+    for (Controller = 0; Controller < MAX_CONTROLLERS; Controller++) {
+      ControllerOut = &Outputs->Controller[Controller];
+      for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+        ChannelOut = &ControllerOut->Channel[Channel];
+        Max                   = Size = DimmNum = 0;
+        if (ChannelOut->Status == CHANNEL_PRESENT) {
+          for (Dimm = 0; Dimm < MAX_DIMMS_IN_CHANNEL; Dimm++) {
+            DimmOut = &ChannelOut->Dimm[Dimm];
+            if (DimmOut->Status == DIMM_PRESENT) {
+              Size = DimmOut->DimmCapacity;
+              MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "C%uD%uDimmCapacity = 0x%x\n", Channel, Dimm, DimmOut->DimmCapacity);
+              if (Size > Max) {
+                Max     = Size;
+                DimmNum = Dimm;
+              }
+            }
+          }
+
+          for (Dimm = 0; Dimm < MAX_DIMMS_IN_CHANNEL; Dimm++) {
+            DimmOut = &ChannelOut->Dimm[Dimm];
+            if ((DimmOut->Status == DIMM_PRESENT) && (Dimm != DimmNum)) {
+              DimmOut->Status = DIMM_DISABLED;
+            }
+          }
+
+          MRC_DEBUG_MSG (
+            Debug,
+            MSG_LEVEL_NOTE,
+            "Controller configured to one DIMM per channel, we've selected channel %u, Dimm %u.\n",
+            Channel,
+            DimmNum
+            );
+          MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "ValidRankBitMask = 0x%x\n", ChannelOut->ValidRankBitMask);
+        }
+      }
+    }
+  }
+
+  //
+  // Now that we know the enabled and disabled DIMM/Channel population,
+  // determine if all enabled DIMMS support ASR.
+  //
+  // It is necessary to have all DIMMS in ASR or no DIMMS in ASR
+  // when enabling 2x Refresh.
+  //
+  if (Inputs->RefreshRate2x == TRUE) {
+    Outputs->AutoSelfRefresh = TRUE;
+    for (Controller = 0; Controller < MAX_CONTROLLERS; Controller++) {
+      ControllerOut = &Outputs->Controller[Controller];
+      if (ControllerOut->Status == CONTROLLER_PRESENT) {
+        for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+          ChannelOut = &ControllerOut->Channel[Channel];
+          if (ChannelOut->Status == CHANNEL_PRESENT) {
+            for (Dimm = 0; Dimm < MAX_DIMMS_IN_CHANNEL; Dimm++) {
+              DimmOut = &ChannelOut->Dimm[Dimm];
+              if ((DimmOut->Status == DIMM_PRESENT) && (DimmOut->AutoSelfRefresh == FALSE)) {
+                MRC_DEBUG_MSG (
+                  Debug,
+                  MSG_LEVEL_NOTE,
+                  "Channel %d, Dimm %d does not support Auto Self Refresh.  Disabling ASR since 2x Refresh is enabled!\n",
+                  Channel,
+                  Dimm
+                  );
+                Outputs->AutoSelfRefresh = FALSE;
+              }
+            }
+          }
+        }
+      }
+    }
+  }
+
+  return mrcSuccess;
+}
+
+/**
+@brief
+  This function reads the CAPID0 register and sets the memory controller's capability.
+
+  @param[in, out] MrcData - All the MRC global data.
+
+  @retval Returns mrcSuccess if the memory controller's capability has been determined, otherwise returns mrcFail.
+**/
+MrcStatus
+MrcMcCapabilityPreSpd (
+  IN OUT MrcParameters *const MrcData
+  )
+{
+  const MrcInput            *Inputs;
+  const MrcDebug            *Debug;
+  MrcOutput                 *Outputs;
+  MrcFrequency              FreqMax;
+  MrcFrequency              FreqMax100;
+  MrcFrequency              FreqMax133;
+  MrcRefClkSelect           RefClk;
+  BOOL                      Capable;
+  MRC_PCI_000_CAPID0_STRUCT Capid0Reg;
+  U32                       Capable100;
+  U32                       Capable133;
+  U32                       Offset;
+
+  Inputs  = &MrcData->SysIn.Inputs;
+  Outputs = &MrcData->SysOut.Outputs;
+  Debug   = &Inputs->Debug;
+
+  //
+  // Obtain the capabilities of the memory controller.
+  //
+  Offset = MrcOemGetPcieDeviceAddress (0, 0, 0, MRC_PCI_000_CAPID0_REG);
+  MrcOemMmioRead (Offset, &Capid0Reg.Data32.A.Data, Inputs->PciEBaseAddress);
+  MrcOemMmioRead (Offset + 4, &Capid0Reg.Data32.B.Data, Inputs->PciEBaseAddress);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "CAPID0 = %X_%Xh\n", Capid0Reg.Data32.B.Data, Capid0Reg.Data32.A.Data);
+
+  //
+  // Determine the maximum memory frequency supported and the memory reference clock.
+  //
+  Capable          = (Capid0Reg.Data32.A.Bits.DDR_OVERCLOCK > 0) ? TRUE : FALSE;
+  Capable100       = Capid0Reg.Data32.B.Bits.PLL_REF100_CFG;
+  Capable133       = Capid0Reg.Data32.B.Bits.DMFC;
+  Outputs->RefClk  = Inputs->RefClk;
+  Outputs->FreqMax = ((Inputs->FreqMax > fNoInit) && (Inputs->FreqMax < fUnSupport)) ? Inputs->FreqMax : f2667;
+
+  if (Capable100 == 0) {
+    Outputs->RefClk = MRC_REF_CLOCK_133;
+  }
+
+  RefClk = Outputs->RefClk;
+  if (Capable) {
+    Capable133 = 0;
+    if (Capable100 > 0) {
+      Capable100 = CAPID0_B_PLL_REF100_CFG_MAX;
+      Outputs->Capable100 = TRUE;
+    }
+  }
+
+  FreqMax100  = (Capable100 == 0) ? fNoInit : MrcRatioToFrequency (MrcData, (MrcClockRatio) Capable100 + 6, MRC_REF_CLOCK_100, BCLK_DEFAULT);
+  FreqMax133  = MrcRatioToFrequency (MrcData, (MrcClockRatio) ((Capable133 == 0) ? 10 : 11 - Capable133), MRC_REF_CLOCK_133, BCLK_DEFAULT);
+  //
+  // If overclocking is supported, then there is no frequency limitation, otherwise check for limitation.
+  // Note 1: If we are using standard memory profile, DIMMS should run at RefClk 133.
+  // Note 2: If the 2 values are equal, then we want to pick RefClk 133.
+  //
+
+  if (Inputs->MemoryProfile == STD_PROFILE) {
+    FreqMax = FreqMax133;
+    RefClk  = MRC_REF_CLOCK_133;
+  } else {    
+    if (Capable) {
+      FreqMax = (RefClk == MRC_REF_CLOCK_100) ? FreqMax100 : FreqMax133;
+    } else if (FreqMax100 > FreqMax133) {
+      FreqMax = FreqMax100;
+      RefClk  = MRC_REF_CLOCK_100;
+    } else {
+      FreqMax = FreqMax133;
+      RefClk  = MRC_REF_CLOCK_133;
+    }
+  }
+
+  if (FreqMax < Outputs->FreqMax) {
+    Outputs->FreqMax  = FreqMax;
+    Outputs->RefClk   = RefClk;
+  }
+
+  Outputs->MemoryClockMax = ConvertFreq2Clock (MrcData, Outputs->FreqMax, NULL);
+
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "The maximum memory frequency allowed is %u (%ufs)\n", Outputs->FreqMax, Outputs->MemoryClockMax);
+  MRC_DEBUG_MSG (
+    Debug,
+    MSG_LEVEL_NOTE,
+    "%uMHz reference clock is selected\n",
+    (Outputs->RefClk == MRC_REF_CLOCK_133) ? 133 : 100
+    );
+
+  return mrcSuccess;
+}
+
+/**
+@brief
+  This function sets the appropriate timing overrides in the output structure
+  prior to Spd processing.
+
+  @param[in, out] MrcData - All the MRC global data.
+
+  @retval Returns mrcSuccess if the timing overrides have been conpleted.
+**/
+MrcStatus
+MrcSetOverridesPreSpd (
+  IN OUT MrcParameters *const MrcData
+  )
+{
+  return mrcSuccess;
+}
+
+/**
+@brief
+  This function reads the input data structure and sets the appropriate timing overrides in the output structure.
+
+  @param[in, out] MrcData - All the MRC global data.
+
+  @retval Returns mrcSuccess if the timing overrides have been conpleted.
+**/
+MrcStatus
+MrcSetOverrides (
+  IN OUT MrcParameters *const MrcData
+  )
+{
+  const MrcDebug                      *Debug;
+  const MrcInput                      *Inputs;
+  MrcOutput                           *Outputs;
+  MPCOHTRK_CR_GDXC_MOT_REGION_STRUCT  GdxcMotRegion;
+  MPCOHTRK_CR_GDXC_OCLA_REGION_STRUCT GdxcOclaRegion;
+
+  Inputs  = &MrcData->SysIn.Inputs;
+  Outputs = &MrcData->SysOut.Outputs;
+  Debug   = &Inputs->Debug;
+
+  Outputs->EccSupport       = Inputs->EccSupport;
+  Outputs->VddVoltageDone   = FALSE;
+
+  Outputs->Gdxc.GdxcEnable  = Inputs->Gdxc.GdxcEnable;
+
+  //
+  // Read MOT register
+  //
+  MrcOemMmioRead (MPCOHTRK_CR_GDXC_MOT_REGION_REG, &GdxcMotRegion.Data, Inputs->GdxcBaseAddress);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_ERROR, "----- GDXC MOT LOW : 0x%x\n", GdxcMotRegion.Bits.START_ADDRESS);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_ERROR, "----- GDXC MOT UPP : 0x%x\n", GdxcMotRegion.Bits.END_ADDRESS);
+  if (GdxcMotRegion.Bits.START_ADDRESS == 0  && GdxcMotRegion.Bits.END_ADDRESS > 1) {
+    Outputs->Gdxc.GdxcMotSize = (U8) (GdxcMotRegion.Bits.END_ADDRESS);
+  } else {
+    Outputs->Gdxc.GdxcMotSize = Inputs->Gdxc.GdxcMotSize;
+  }
+  //
+  // Read OCLA register
+  //
+  MrcOemMmioRead (MPCOHTRK_CR_GDXC_OCLA_REGION_REG, &GdxcOclaRegion.Data, Inputs->GdxcBaseAddress);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_ERROR, "----- GDXC IOT LOW : 0x%x\n", GdxcOclaRegion.Bits.START_ADDRESS);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_ERROR, "----- GDXC IOT UPP : 0x%x\n", GdxcOclaRegion.Bits.END_ADDRESS);
+
+  if (GdxcOclaRegion.Bits.START_ADDRESS == 0  && GdxcOclaRegion.Bits.END_ADDRESS > 1) {
+    Outputs->Gdxc.GdxcIotSize = (U8) (GdxcOclaRegion.Bits.END_ADDRESS);
+  } else {
+    Outputs->Gdxc.GdxcIotSize = Inputs->Gdxc.GdxcIotSize;
+  }
+
+  return mrcSuccess;
+}
+
+/**
+@brief
+  This function set the WM0-5 values. Those values are be using by the graphics driver.
+  need to be call after PU_MRC_DONE bit is set to 1.
+
+  @param[in] MrcData - include all the MRC data.
+
+  @retval Nothing.
+
+  **/
+void
+MrcWmRegSet (
+  IN     MrcParameters *const MrcData
+  )
+{
+  M_PCU_CR_SSKPD_PCU_STRUCT CrSskpdPcu;
+
+  CrSskpdPcu.Data        = 0;
+  CrSskpdPcu.Bits.NewWM0 = PCU_CR_SSKPD_PCU_NEW_WM0_DEF;
+  CrSskpdPcu.Bits.WM4    = PCU_CR_SSKPD_PCU_WM4_DEF;
+  CrSskpdPcu.Bits.WM3    = PCU_CR_SSKPD_PCU_WM3_DEF;
+  CrSskpdPcu.Bits.WM2    = PCU_CR_SSKPD_PCU_WM2_DEF;
+  CrSskpdPcu.Bits.WM1    = PCU_CR_SSKPD_PCU_WM1_DEF;
+  CrSskpdPcu.Bits.OldWM0 = PCU_CR_SSKPD_PCU_OLD_WM0_DEF;
+  MrcWriteCR64 (MrcData, PCU_CR_SSKPD_PCU_REG, CrSskpdPcu.Data);
+  return;
+}
+
+
+#ifdef ULT_FLAG
+/**
+@brief
+  Program DDRPL_CR_DDR_TX_DELAY if Memory Trace is enabled
+
+  @param[in] MrcData - The MRC general data.
+
+  @retval None
+**/
+void
+MrcSetDdrplTxDelay (
+  IN MrcParameters *const MrcData
+  )
+{
+  MrcInput                              *Inputs;
+  MrcOutput                             *Outputs;
+  MrcChannelOut                         *ChannelOut;
+  U32                                   Rank;
+  U32                                   TxDelay;
+  U32                                   Roundtrip;
+  U32                                   tCL;
+  U32                                   tWCL;
+  U32                                   CmdDelay;
+  U32                                   CmdStretch;
+  U32                                   DecWrd;
+  U32                                   AddWrDelay;
+  U32                                   tWCL5_reduction;
+  U32                                   StretchMode;
+  DDRPL_CR_DDR_TX_DELAY_STRUCT          DdrTxDelay;
+  MCHBAR_CH0_CR_SC_ROUNDT_LAT_STRUCT    ScRoundtLat;
+  MCHBAR_CH0_CR_SC_WR_ADD_DELAY_STRUCT  ScWrAddDelay;
+  MCHBAR_CH0_CR_TC_BANK_RANK_A_STRUCT   TcBankRankA;
+  MCHBAR_CH0_CR_TC_BANK_RANK_B_STRUCT   TcBankRankB;
+  MCHBAR_CH0_CR_TC_BANK_RANK_D_STRUCT   TcBankRankD;
+  MCSCHEDS_CR_STM_CONFIG_STRUCT         StmConfig;
+    
+  Inputs  = &MrcData->SysIn.Inputs;
+  Outputs = &MrcData->SysOut.Outputs;
+
+  if (!Inputs->MemoryTrace) {
+    return;
+  }
+
+  //
+  // TxDelay(rank) = Roundtrip(rank) - [2*RD_cmd2data_dclk_delay] + [2*Dec_WRD] - additional_wr_delay(rank) - [2*tCWL5_reduction] + [8*(STM - 1)] + Constant(5)
+  //
+  // RD_cmd2data_dclk_delay = tCL + tDQSCK + cmd_delay + cmd_stretch
+  //                        tCL, tDQSCK      - according to JEDEC spec
+  //                        cmd_delay        - MCSCHEDS_CR_TC_BANK_RANK_D. cmd_delay
+  //                        cmd_stretch      - MCSCHEDS_CR_TC_BANK_RANK_A. cmd_stretch (0,1,2 for 1N,2N,3N respectively)
+  //
+  // tCWL5_reduction = (ddr_type==DDR3 && (tCWL + cmd_stretch - Dec_WRD == 5)) ? 1 : 0;
+  //
+  // STM = (STM_mode == SYSTEM ? STM_stf : 1)
+
+  //
+  // Assume we are tracing DDR channel 0 - taking all the timing parameters from Channel 0
+  //
+  
+  ChannelOut = &Outputs->Controller[0].Channel[0];
+  
+  ScRoundtLat.Data  = MrcReadCR (MrcData, MCHBAR_CH0_CR_SC_ROUNDT_LAT_REG);
+  ScWrAddDelay.Data = MrcReadCR (MrcData, MCHBAR_CH0_CR_SC_WR_ADD_DELAY_REG);
+  StmConfig.Data    = MrcReadCR (MrcData, MCSCHEDS_CR_STM_CONFIG_REG);
+  TcBankRankA.Data  = ChannelOut->MchbarBANKRANKA;
+  TcBankRankB.Data  = ChannelOut->MchbarBANKRANKB;
+  TcBankRankD.Data  = ChannelOut->MchbarBANKRANKD;
+  tCL         = TcBankRankD.UltBits.tCL;
+  tWCL        = TcBankRankD.UltBits.tWCL;
+  CmdDelay    = TcBankRankD.UltBits.cmd_delay;
+  CmdStretch  = TcBankRankA.Bits.CMD_stretch;
+  DecWrd      = TcBankRankB.Bits.Dec_WRD;
+  
+  if ((Outputs->DdrType == MRC_DDR_TYPE_DDR3) && (tWCL + CmdStretch - DecWrd == 5)) {
+    tWCL5_reduction = 1;
+  } else {
+    tWCL5_reduction = 0;
+  }
+  
+  if (StmConfig.Bits.Stretch_mode == 2) {
+    StretchMode = StmConfig.Bits.STF;
+  } else {
+    StretchMode = 1;
+  }
+  
+  DdrTxDelay.Data = 0;
+  MRC_DEBUG_MSG (&Inputs->Debug, MSG_LEVEL_NOTE, "TX Delay values for Memory Trace:\n");
+  for (Rank = 0; Rank < MAX_RANK_IN_CHANNEL; Rank++) {
+    if (!MrcRankInChannelExist (MrcData, (U8) Rank, 0)) {
+      continue;
+    }
+  
+    Roundtrip  = (ScRoundtLat.Data >> (Rank * 8)) & MCHBAR_CH0_CR_SC_ROUNDT_LAT_Lat_R0D0_MSK;
+    AddWrDelay = (ScWrAddDelay.Data >> (Rank * 2)) & MCHBAR_CH0_CR_SC_WR_ADD_DELAY_D0R0_MSK;
+    
+    TxDelay = Roundtrip - (2 * tCL + 1 + 2 * CmdDelay + 2 * CmdStretch) + 
+      2 * DecWrd - 2 * AddWrDelay - 2 * tWCL5_reduction + 8 * (StretchMode - 1) + 5;
+    
+    DdrTxDelay.Data |= ((TxDelay & DDRPL_CR_DDR_TX_DELAY_Tx_Delay_R0_MSK) << (Rank * DDRPL_CR_DDR_TX_DELAY_Tx_Delay_R0_WID));
+    
+    MRC_DEBUG_MSG (
+      &Inputs->Debug,
+      MSG_LEVEL_NOTE,
+      "Rank%u:\n RT = %u\n tCL = %u\n cmd_delay = %u\n CMD_stretch = %u\n Dec_WRD = %u\n AddWrDelay = %u\n tWCL5_reduction = %u\n STM = %u\n",
+      Rank,
+      Roundtrip,
+      tCL,
+      CmdDelay,
+      CmdStretch,
+      DecWrd,
+      AddWrDelay,
+      tWCL5_reduction,
+      StretchMode
+      );
+  }
+
+  MRC_DEBUG_MSG (&Inputs->Debug, MSG_LEVEL_NOTE, "DDRPL_CR_DDR_TX_DELAY = 0x%08X\n", DdrTxDelay.Data);
+
+  MrcOemMmioWrite (DDRPL_CR_DDR_TX_DELAY_REG, DdrTxDelay.Data, Inputs->GdxcBaseAddress);
+}
+#endif // ULT_FLAG
diff --git a/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Api/MrcGeneral.h b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Api/MrcGeneral.h
new file mode 100644
index 0000000..04bd977
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Api/MrcGeneral.h
@@ -0,0 +1,303 @@
+/** @file
+  MRC Common / Generic functions
+
+@copyright
+  Copyright (c) 2011 - 2012 Intel Corporation. All rights reserved.
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement
+**/
+
+#ifndef _MrcGeneral_h_
+#define _MrcGeneral_h_
+
+#include "MrcTypes.h"
+#include "MrcApi.h"
+#include "MrcAddressDecodeConfiguration.h"
+#include "MrcCommon.h"
+#include "MrcCrosser.h"
+#include "MrcDebugHook.h"
+//
+// #include "MrcMemoryClean.h"
+//
+#include "MrcOem.h"
+#include "MrcPowerModes.h"
+//
+// #include "MrcRefreshConfiguration.h"
+//
+#include "MrcSpdProcessing.h"
+
+#define GENERAL_PM_CONFIGURATION_2_BUS_ADDRESS      (0)
+#define GENERAL_PM_CONFIGURATION_2_DEVICE_ADDRESS   (31)
+#define GENERAL_PM_CONFIGURATION_2_FUNCTION_ADDRESS (0)
+
+#define GENERAL_PM_CONFIGURATION_2                  ((0xA2) & (~0x03))
+
+#define GENERAL_PM_CONFIGURATION_2_DISB_OFFSET      (0x7)
+#define GENERAL_PM_CONFIGURATION_2_DISB_WIDTH       (0x1)
+#define GENERAL_PM_CONFIGURATION_2_DISB_MASK        (0x80)
+#define GENERAL_PM_CONFIGURATION_2_DISB_DEFAULT     (0x0)
+
+#define GENERAL_PM_CONFIGURATION_2_MEM_SR_OFFSET    (0x5)
+#define GENERAL_PM_CONFIGURATION_2_MEM_SR_WIDTH     (0x1)
+#define GENERAL_PM_CONFIGURATION_2_MEM_SR_MASK      (0x20)
+#define GENERAL_PM_CONFIGURATION_2_MEM_SR_DEFAULT   (0x0)
+
+#define MEMORY_TEST_CACHELINE                       (100) ///< max number can be 100 from one rank
+///
+/// Define the total memory size of a channel.
+///
+typedef enum {
+  tcs16GB,  ///< 16 GB per channel
+  tcs8GB,   ///< 8 GB
+  tcs2GB,   ///< 2 GB
+  tcs512MB  ///< 512 MB
+} MrcTotalChannelSize;
+
+extern MrcUpmPwrRetrainLimits  InitialLimits[MRC_NUMBER_UPM_PWR_RETRAIN_MARGINS];
+
+/**
+  Thisfunction performs Software Memory testing
+
+  @param[in] MrcData - Include all MRC global data.
+
+  @retval Always returns mrcSuccess.
+**/
+extern
+MrcStatus
+MrcHwMemTest (
+  IN     MrcParameters *const MrcData
+  );
+
+/**
+  This function changes the MC to normal mode, enables the ECC if needed, lock configuration and set PU_MRC_Done.
+  If the ECC is enabled, this function should be called after memory is cleaned.
+
+  @param[in, out] MrcData - Include all MRC global data.
+
+  @retval Always returns mrcSuccess.
+**/
+extern
+MrcStatus
+MrcMcActivate (
+  IN OUT MrcParameters *const MrcData
+  );
+
+/**
+  This function enables Normal Mode and configures the Power Down Modes
+  for the boot flows other than Cold Boot.
+
+  @param[in] MrcData - The MRC general data.
+
+  @retval Always returns mrcSuccess.
+**/
+extern
+MrcStatus
+MrcNormalMode (
+  IN MrcParameters *const MrcData
+  );
+
+/**
+  This function is the last funtion that call from the MRC core.
+  The function set DISB and set the MRC_Done.
+
+  @param[in, out] MrcData - include all the MRC general data.
+
+  @retval Always returns mrcSuccess.
+**/
+extern
+MrcStatus
+MrcDone (
+  IN OUT MrcParameters *const MrcData
+  );
+
+/**
+  Print the MRC version to the MRC output device.
+
+  @param[in] Debug   - Pointer to the MRC Debug structure.
+  @param[in] Version - The MRC version.
+
+  @retval Nothing.
+**/
+extern
+void
+MrcVersionPrint (
+  IN const MrcParameters *MrcData,
+  IN const MrcVersion    *Version
+  );
+
+/**
+  This function return the MRC version.
+
+  @param[out] Version - Location to store the MRC version.
+
+  @retval Nothing.
+**/
+extern
+void
+MrcVersionGet (
+     OUT MrcVersion *const Version
+  );
+
+/**
+  This function set the MRC vertion to MCDECS_SPARE register.
+  The function need to be call by the wrapper after MrcStartMemoryConfiguration function where the MC CLK enable.
+  The function write:
+  Major number to bits 16-23
+  Minor number to bits 8-15
+  Build number to bits 0 - 7
+
+  @param[in] MrcData - Include all MRC global data.
+
+  @retval Nothing.
+**/
+extern
+MrcStatus
+MrcSetMrcVersion (
+  IN     MrcParameters *const MrcData
+  );
+
+/**
+  This function locks the memory controller and memory map registers.
+
+  @param[in] MrcData - Include all MRC global data.
+
+  @retval Nothing.
+**/
+extern
+void
+McRegistersLock (
+  IN     MrcParameters *const MrcData
+  );
+
+/**
+  This function returns the recommended MRC boot mode.
+
+  @param[in] void - No arguments
+
+  @retval bmWarm if we are in self refresh and the DISB bit is set, otherwise returns bmCold.
+**/
+extern
+MrcBootMode
+MrcGetBootMode (
+  void
+  );
+
+/**
+  This function sets the DISB bit in General PM Configuration 2 B:D:F 0,31,0 offset 0xA2.
+
+  @param[in] void - No arguments
+
+  @retval Nothing.
+**/
+extern
+void
+MrcSetDISB (
+  void
+  );
+
+/**
+  This function resets the DISB bit in General PM Configuration 2 B:D:F 0,31,0 offset 0xA2.
+
+  @param[in] void - No arguments
+
+  @retval Nothing.
+**/
+extern
+void
+MrcResetDISB (
+  void
+  );
+
+/**
+  This function reads the CAPID0 register and sets the memory controller's capability.
+
+  @param[in, out] MrcData - All the MRC global data.
+
+  @retval Returns mrcSuccess if the memory controller's capability has been determined, otherwise returns mrcFail.
+**/
+extern
+MrcStatus
+MrcMcCapability (
+  IN OUT MrcParameters *const MrcData
+  );
+
+/**
+  This function reads the CAPID0 register and sets the memory controller's capability.
+
+  @param[in, out] MrcData - All the MRC global data.
+
+  @retval Returns mrcSuccess if the memory controller's capability has been determined, otherwise returns mrcFail.
+**/
+MrcStatus
+MrcMcCapabilityPreSpd (
+  IN OUT MrcParameters *const MrcData
+  );
+
+/**
+  This function sets the appropriate timing overrides in the output structure
+  prior to Spd processing.
+
+  @param[in, out] MrcData - All the MRC global data.
+
+  @retval Returns mrcSuccess if the timing overrides have been conpleted.
+**/
+extern
+MrcStatus
+MrcSetOverridesPreSpd (
+  IN OUT MrcParameters *const MrcData
+  );
+
+/**
+  This function reads the input data structure and sets the appropriate timing overrides in the output structure.
+
+  @param[in, out] MrcData - All the MRC global data.
+
+  @retval Returns mrcSuccess if the timing overrides have been conpleted.
+**/
+extern
+MrcStatus
+MrcSetOverrides (
+  IN OUT MrcParameters *const MrcData
+  );
+
+/**
+  This function set the WM0-5 values. Those values are be using by the graphics driver.
+  need to be call after PU_MRC_DONE bit is set to 1.
+
+  @param[in] MrcData - include all the MRC data.
+
+  @retval Nothing.
+
+  **/
+void
+MrcWmRegSet (
+  IN     MrcParameters *const MrcData
+  );
+
+
+/**
+@brief
+  Program DDRPL_CR_DDR_TX_DELAY if Memory Trace is enabled
+
+  @param[in] MrcData - The MRC general data.
+
+  @retval None
+**/
+void
+MrcSetDdrplTxDelay (
+  IN MrcParameters *const MrcData
+  );
+
+#endif
diff --git a/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Api/MrcMemoryScrub.c b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Api/MrcMemoryScrub.c
new file mode 100644
index 0000000..e140250
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Api/MrcMemoryScrub.c
@@ -0,0 +1,678 @@
+/** @file
+  This file contains the memory scrubbing and alias checking functions.
+
+@copyright
+  Copyright (c) 1999 - 2013 Intel Corporation. All rights reserved.
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement.
+
+**/
+
+#include "MrcTypes.h"
+#include "MrcApi.h"
+#include "MrcMemoryScrub.h"
+
+/**
+@brief
+  This function sets all the memory to a known value when ECC is enabled and
+  either we are not in warm boot or we are in warm boot and TXT is set.
+
+  @param[in] MrcData - Include all MRC global data.
+
+  @retval mrcSuccess if the clean succeeded, otherwise an error status.
+**/
+MrcStatus
+MrcEccClean (
+  IN     MrcParameters *const MrcData
+  )
+{
+  const MrcInput        *Inputs;
+  const MrcDebug        *Debug;
+  const U8              WrapCarryEn[MrcReutFieldMax] = {0, 0, 0, 0};
+  const U8              WrapTriggerEn[MrcReutFieldMax] = {0, 0, 1, 0};  // Trigger Stop on Bank Wrap
+  const U8              AddrInvertEn[MrcReutFieldMax] = {0, 0, 0, 0};
+  MrcControllerOut      *ControllerOut;
+  MrcDimmOut            *DimmOut;
+  MrcOutput             *Outputs;
+  MrcStatus             Status;
+  U32                   ReutSubSeqCtl0Data;
+  U8                    Pattern;
+  U8                    PMask;
+  U8                    Rank;
+  U8                    Bank;
+  U8                    Channel;
+  U8                    ActiveChBitMask;
+  U8                    RankToDimm;
+  MRC_REUTAddress       ReutAddress;
+  MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_STRUCT     ReutChSeqCfg;
+  MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_CTRL_STRUCT  ReutChPatWdbCl;
+
+  Inputs        = &MrcData->SysIn.Inputs;
+  Outputs       = &MrcData->SysOut.Outputs;
+  ControllerOut = &Outputs->Controller[0];
+  Debug         = &Inputs->Debug;
+  Status        = mrcSuccess;
+  Pattern       = 0;
+  PMask         = 0;
+  MrcOemMemorySet ((U8 *) &ReutAddress, 0, sizeof (ReutAddress));
+
+  if ((Outputs->EccSupport == TRUE) || (Inputs->OemCleanMemory == TRUE)) {
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Scrubbing Memory\n");
+    ReutAddress.IncVal[MrcReutFieldCol] = 1;  // Each write is 1 cache line which is 8 column addresses worth of data.
+    ReutAddress.IncVal[MrcReutFieldRow] = 1;  // Walk through rows 1 at a time.
+
+    //
+    // Setup the first cache line to zeros.
+    //
+    WriteWDBFixedPattern (MrcData, &Pattern, &PMask, 1, 0);
+
+    //
+    // Setup Reut for both channels.
+    //
+    for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+      if (!MrcChannelExist (Outputs, Channel)) {
+        continue;
+      }
+
+      //
+      // Write initial Reut Address Values.
+      //
+      MrcProgramSequenceAddress (
+       MrcData,
+       Channel,
+       ReutAddress.Start,
+       NULL,                // Stop
+       ReutAddress.Order,
+       ReutAddress.IncRate,
+       ReutAddress.IncVal,
+       WrapTriggerEn,
+       WrapCarryEn,
+       AddrInvertEn,
+       0,                 // AddrInvertRate
+       FALSE
+       );
+
+      //
+      // Set Reut to Write
+      //
+      ReutChSeqCfg.Data                                    = 0;
+      ReutChSeqCfg.Bits.Initialization_Mode                = REUT_Testing_Mode;
+      ReutChSeqCfg.Bits.Global_Control                     = 1;
+      ReutChSeqCfg.Bits.Start_Test_Delay                   = 2;
+      ReutChSeqCfg.Bits.Address_Update_Rate_Mode           = 1;
+      ReutChSeqCfg.Bits.Stop_Base_Sequence_On_Wrap_Trigger = 1;
+      MrcWriteCR64 (
+        MrcData,
+        MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_REG +
+        ((MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_REG - MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_REG) * Channel),
+        ReutChSeqCfg.Data
+        );
+
+      //
+      // Program new loopcount registers based on stepping.
+      //
+      if (
+          (Inputs->CpuModel == cmHSW && Inputs->CpuStepping >= csHswC0) ||
+          (Inputs->CpuModel == cmCRW && Inputs->CpuStepping >= csCrwC0) ||
+          (Inputs->CpuModel == cmHSW_ULT && Inputs->CpuStepping >= csHswUltC0) ||
+          (Inputs->CpuModel == cmBDW)
+         ) {
+        MrcWriteCR (
+          MrcData,
+          MCDFXS_CR_REUT_CH_SEQ_LOOPCOUNT_LIMIT_MCMAIN_0_REG +
+            ((MCDFXS_CR_REUT_CH_SEQ_LOOPCOUNT_LIMIT_MCMAIN_1_REG - MCDFXS_CR_REUT_CH_SEQ_LOOPCOUNT_LIMIT_MCMAIN_0_REG)
+            * Channel),
+          0
+          );
+      }
+
+      //
+      // Set up the Subsequence control.
+      //
+      ReutSubSeqCtl0Data = 0;
+      SetSubsequenceType (MrcData, &ReutSubSeqCtl0Data, BWr);
+      MrcWriteCR (
+        MrcData,
+        MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_REG +
+        ((MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_REG - MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_REG) * Channel),
+        ReutSubSeqCtl0Data
+        );
+
+      //
+      // Program Write Data Buffer Control.  Since we are using 1 cache line, we only need
+      // to set the increment scale to linear.
+      //
+      ReutChPatWdbCl.Data = 0;
+      ReutChPatWdbCl.Bits.WDB_Increment_Scale = 1;
+      MrcWriteCR (
+        MrcData,
+        MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_CTRL_REG +
+        ((MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_CTRL_REG - MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_CTRL_REG) * Channel),
+        ReutChPatWdbCl.Data
+        );
+    }
+
+    //
+    // Run Per Rank
+    //
+    for (Rank = 0; Rank < MAX_RANK_IN_CHANNEL; Rank++) {
+      if ((MRC_BIT0 << Rank) & Outputs->ValidRankMask) {
+        //
+        // Determine the Active Channels
+        //
+        ActiveChBitMask = 0;
+        for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+          ActiveChBitMask |= SelectReutRanks (MrcData, Channel, MRC_BIT0 << Rank, 0);
+        }
+
+        //
+        // Counter registers are not large enough to walk through 1 Rank for LPDDR3 support due to 11 column bits.
+        // Must walk through memory on a bank loop.
+        //
+        for (Bank = 0; Bank < 8; Bank++) {
+          ReutAddress.Start[MrcReutFieldBank] = Bank;
+          ReutAddress.Stop[MrcReutFieldBank]  = Bank;
+
+          for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+            if (ActiveChBitMask & (MRC_BIT0 << Channel)) {
+              //
+              // Update Bank start/stop
+              //
+              RankToDimm                           = RANK_TO_DIMM_NUMBER (Rank);
+              DimmOut                              = &ControllerOut->Channel[Channel].Dimm[RankToDimm];
+              ReutAddress.Stop[MrcReutFieldRow]    = (U16) DimmOut->RowSize - 1;
+              ReutAddress.Stop[MrcReutFieldCol]    = DimmOut->ColumnSize - WDB_CACHE_LINE_SIZE;
+              ReutAddress.IncRate[MrcReutFieldRow] = DimmOut->ColumnSize / WDB_CACHE_LINE_SIZE;
+              MrcProgramSequenceAddress (
+                MrcData,
+                Channel,
+                ReutAddress.Start,
+                ReutAddress.Stop,
+                NULL,                 // Order
+                ReutAddress.IncRate,
+                NULL,                 // IncVal
+                NULL,                 // WrapTriggerEn
+                NULL,                 // WrapCarryEn
+                NULL,                 // AddrInvertEn
+                0,                    // AddrInvertRate
+                FALSE
+                );
+            }
+          }
+
+          //
+          // Run the test
+          //
+          Status = MrcRunMemoryScrub (MrcData, ActiveChBitMask);
+          if (Status != mrcSuccess) {
+            MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Rank %d error!\n", Rank);
+            break;
+          }
+        }
+      }
+
+      if (Status != mrcSuccess) {
+        break;
+      }
+    }
+
+    //
+    // Return to normal operation mode
+    //
+    for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+      if (MrcChannelExist (Outputs, Channel)) {
+        ReutChSeqCfg.Data                     = 0;
+        ReutChSeqCfg.Bits.Initialization_Mode = NOP_Mode;
+        MrcWriteCR (
+          MrcData,
+          MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_REG +
+          ((MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_REG - MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_REG) * Channel),
+          (U32) ReutChSeqCfg.Data
+          );
+      }
+    }
+
+    if (Status != mrcSuccess) {
+      MrcOemDebugHook (MrcData, MRC_ECC_CLEAN_ERROR);
+    }
+  }
+
+  return Status;
+}
+
+/**
+@brief
+  This function performs a memory alias check.
+
+  @param[in] MrcData - The global host structure
+
+  @retval mrcSuccess or error value.
+**/
+MrcStatus
+MrcAliasCheck (
+  IN OUT MrcParameters *const MrcData
+  )
+{
+  const MrcDebug    *Debug;
+  const MrcInput    *Inputs;
+  const U8          WrapCarryEn[MrcReutFieldMax]   = {0, 0, 0, 0};
+  const U8          WrapTriggerEn[MrcReutFieldMax] = {0, 0, 0, 0};  // Trigger Stop on Bank Wrap
+  const U8          AddrInvertEn[MrcReutFieldMax] = {0, 0, 0, 0};
+  const U16         SdramCapacityTable[] = {256, 512, 1024, 2048, 4096, 8192, 16384, 32768}; // Mb
+  MrcOutput         *Outputs;
+  MrcControllerOut  *ControllerOut;
+  MrcDimmOut        *DimmOut;
+  MrcStatus         Status;
+  MrcDdrType        DdrType;
+  BOOL              InvalidSpdAddressingCapacity;
+  U32               SdramAddressingCapacity;
+  U32               CrOffset;
+  U16               SdramCapacity;
+  U16               WritesPerPage;
+  U16               ColumnIncValUnaligned;
+  U8                Rank;
+  U8                RankToDimm;
+  U8                Channel;
+  U8                ActiveChBitMask;
+  MRC_REUTAddress   ReutAddress;
+  MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_STRUCT       ReutChSeqCfg;
+  MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_CTRL_STRUCT    ReutChPatWdbCl;
+  MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_STRUCT ReutChPatWdbClMuxCfg;
+  MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_STRUCT   ReutSubSeqCtl;
+  MCDECS_CR_MAD_DIMM_CH0_MCMAIN_STRUCT            MadDimmCh[MAX_CHANNEL];
+  MCDECS_CR_MAD_DIMM_CH0_MCMAIN_STRUCT            MadDimm;
+
+  Outputs                       = &MrcData->SysOut.Outputs;
+  Inputs                        = &MrcData->SysIn.Inputs;
+  Debug                         = &Inputs->Debug;
+  ControllerOut                 = &Outputs->Controller[0];
+  Status                        = mrcSuccess;
+  InvalidSpdAddressingCapacity  = FALSE;
+  DdrType                       = Outputs->DdrType;
+  //
+  // Check to see if the SDRAM Addressing * Primary Bus Width == SDRAM capacity.
+  // If not, report an alias and exit.
+  //
+  for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+    for (Rank = 0; Rank < MAX_RANK_IN_CHANNEL; Rank += MAX_RANK_IN_DIMM) {
+      if (MrcRankInChannelExist (MrcData, Rank, Channel)) {
+        RankToDimm              = RANK_TO_DIMM_NUMBER (Rank);
+        DimmOut                 = &ControllerOut->Channel[Channel].Dimm[RankToDimm];
+        SdramAddressingCapacity = (DimmOut->ColumnSize * DimmOut->RowSize);
+        //
+        // Since the minimum number of row and coulmn bits are 12 and 9 respectivly,
+        // we can shift by 20 to get the result in Mb before multiplying by the bus width.
+        //
+        SdramAddressingCapacity  = SdramAddressingCapacity >> 20;
+        SdramAddressingCapacity *= DimmOut->Banks;
+        SdramAddressingCapacity *= (DimmOut->BankGroups > 0) ? DimmOut->BankGroups : 1;
+        SdramAddressingCapacity *= DimmOut->SdramWidth;
+        SdramCapacity            = SdramCapacityTable[DimmOut->DensityIndex];
+        if (SdramCapacity != SdramAddressingCapacity) {
+          InvalidSpdAddressingCapacity = TRUE;
+          MRC_DEBUG_MSG (
+            Debug,
+            MSG_LEVEL_ERROR,
+            "ERROR: Channel %d Dimm %d SPD SDRAM Adressing Capacity(0x%xMb) does not match SDRAM Capacity(0x%xMb)\nPlease verify:\n",
+            Channel,
+            RankToDimm,
+            SdramAddressingCapacity,
+            SdramCapacity
+            );
+          MRC_DEBUG_MSG (
+            Debug,
+            MSG_LEVEL_ERROR,
+            " Capacity: 0x%x\n RowSize: 0x%x\n ColumnSize: 0x%x\n Banks: 0x%x\n Bank Groups: 0x%x\n Device Width: 0x%x\n",
+            SdramCapacity,
+            DimmOut->RowSize,
+            DimmOut->ColumnSize,
+            DimmOut->Banks,
+            DimmOut->BankGroups,
+            DimmOut->SdramWidth
+            );
+          break;
+        }
+      }
+    }
+  }
+  //
+  // Since we will not hang the system, signal that an Alias could exist and return mrcSuccess.
+  //
+  if (TRUE == InvalidSpdAddressingCapacity) {
+    Outputs->SpdSecurityStatus = MrcSpdStatusAliased;
+    return Status;
+  }
+
+  if ((Inputs->CpuModel == cmHSW && Inputs->CpuStepping >= csHswB0) || (Inputs->CpuModel != cmHSW)) {
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Performing Alias Test\n");
+    MrcOemMemorySet ((U8 *) &ReutAddress, 0, sizeof (ReutAddress));
+
+    //
+    // Determine if we are ECC enabled.  If so, disable ECC since the ECC scrub has yet to occur.
+    //
+    if (Outputs->EccSupport == TRUE) {
+      MRC_DEBUG_MSG(Debug, MSG_LEVEL_NOTE, "ECC enabled.  Disabling ECC for the test.  Must scrub after this!!!\n");
+      for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+        if (MrcChannelExist (Outputs, Channel)) {
+          CrOffset = MCDECS_CR_MAD_DIMM_CH0_MCMAIN_REG +
+            ((MCDECS_CR_MAD_DIMM_CH1_MCMAIN_REG - MCDECS_CR_MAD_DIMM_CH0_MCMAIN_REG) * Channel);
+
+          MadDimmCh[Channel].Data = MrcReadCR (MrcData, CrOffset);
+          MadDimm.Data            = MadDimmCh[Channel].Data;
+          MadDimm.Bits.ECC        = emNoEcc;
+          MrcWriteCR (MrcData, CrOffset, MadDimm.Data);
+        }
+      }
+    }
+
+    //
+    // Test Initialization
+    //
+    //
+    // Start with IncRate = 3 so we have 4 column writes per page.  This will change with Column Size.
+    // Must have 4 (reg + 1) writes to move to the next LFSR code for unique values.
+    //
+    ReutAddress.IncRate[MrcReutFieldRow]  = 3;
+    //
+    // IncVal[Col] is chosen to be 1/4 of the minimum column supported to get 4 writes per page.
+    // Each write is 1 cache line (8 column addresses worth of data).
+    // IncVal is on a cache line basis when programmed.  Account for this here ( >> 3).
+    //
+    ColumnIncValUnaligned = MRC_BIT10 >> 2; // divide by 4
+    ReutAddress.IncVal[MrcReutFieldCol]   = ColumnIncValUnaligned >> 3; // cache line shift
+    //
+    // Smallest Row address size is 2^12, but Row_Base_Address_Increment is a 12-bit signed field [0-11].
+    // Thus we have to increment by 2^10.
+    //
+    ReutAddress.IncVal[MrcReutFieldRow]   = MRC_BIT10;
+    ReutAddress.Stop[MrcReutFieldCol]     = 24; // 4 ([0-3] << 3) column writes before wrapping
+    ReutAddress.Start[MrcReutFieldBank]   = 1;
+    ReutAddress.Stop[MrcReutFieldBank]    = 1;
+
+    //
+    // Setup Reut all present channels.
+    //
+    for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+      if (!MrcChannelExist (Outputs, Channel)) {
+        continue;
+      }
+
+      //
+      // Write initial Reut Address Values.
+      //
+      MrcProgramSequenceAddress (
+       MrcData,
+       Channel,
+       ReutAddress.Start,
+       NULL,              // Stop
+       ReutAddress.Order,
+       ReutAddress.IncRate,
+       ReutAddress.IncVal,
+       WrapTriggerEn,
+       WrapCarryEn,
+       AddrInvertEn,
+       0,
+       FALSE
+       );
+
+      //
+      // Set Reut to Write
+      //
+      ReutChSeqCfg.Data                                     = 0;
+      ReutChSeqCfg.Bits.Initialization_Mode                 = REUT_Testing_Mode;
+      ReutChSeqCfg.Bits.Global_Control                      = 1;
+      ReutChSeqCfg.Bits.Start_Test_Delay                    = 2;
+      ReutChSeqCfg.Bits.Subsequence_End_Pointer             = 1;
+
+     if (
+          (Inputs->CpuModel == cmHSW && Inputs->CpuStepping < csHswC0) ||
+          (Inputs->CpuModel == cmCRW && Inputs->CpuStepping < csCrwC0) ||
+          (Inputs->CpuModel == cmHSW_ULT && Inputs->CpuStepping < csHswUltC0) ||
+          (Inputs->CpuModel == cmBDW)
+         ) {
+        ReutChSeqCfg.Bits.Loopcount = 1;
+      } else {
+        CrOffset = MCDFXS_CR_REUT_CH_SEQ_LOOPCOUNT_LIMIT_MCMAIN_0_REG +
+          ((MCDFXS_CR_REUT_CH_SEQ_LOOPCOUNT_LIMIT_MCMAIN_1_REG - MCDFXS_CR_REUT_CH_SEQ_LOOPCOUNT_LIMIT_MCMAIN_0_REG) *
+          Channel);
+        MrcWriteCR (MrcData, CrOffset, 1);
+      }
+
+      CrOffset = MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_REG +
+        ((MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_REG - MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_REG) * Channel);
+      MrcWriteCR64 (
+        MrcData,
+        CrOffset,
+        ReutChSeqCfg.Data
+        );
+
+      //
+      // Program Write Data Buffer Control.
+      //
+      ReutChPatWdbCl.Data = 0;
+      ReutChPatWdbCl.Bits.WDB_Increment_Scale = 1;
+      MrcWriteCR (
+        MrcData,
+        MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_CTRL_REG +
+        ((MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_CTRL_REG - MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_CTRL_REG) * Channel),
+        ReutChPatWdbCl.Data
+        );
+
+      ReutChPatWdbClMuxCfg.Bits.ECC_Data_Source_Sel = 1;
+      ReutChPatWdbClMuxCfg.Bits.Mux2_Control        = LFSRMode;
+      ReutChPatWdbClMuxCfg.Bits.Mux1_Control        = LFSRMode;
+      ReutChPatWdbClMuxCfg.Bits.Mux0_Control        = LFSRMode;
+      CrOffset = MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_REG +
+        ((MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_REG - MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_REG) * Channel);
+      MrcWriteCR (MrcData, CrOffset, ReutChPatWdbClMuxCfg.Data);
+    }
+
+    //
+    // Run test Per Dimm
+    //
+    for (Rank = 0; Rank < MAX_RANK_IN_CHANNEL; Rank += MAX_RANK_IN_DIMM){
+      if ((MRC_BIT0 << Rank) & Outputs->ValidRankMask) {
+        MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Testing Dimm %d\n", Rank / 2);
+        //
+        // Determine Active Channels
+        //
+        ActiveChBitMask = 0;
+        for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+          ActiveChBitMask |= SelectReutRanks (MrcData, Channel, MRC_BIT0 << Rank, 0);
+          //
+          // Update Rank stop address based on DIMM SPD if Active.
+          //
+          if (ActiveChBitMask & (MRC_BIT0 << Channel)) {
+            RankToDimm  = RANK_TO_DIMM_NUMBER (Rank);
+            DimmOut     = &ControllerOut->Channel[Channel].Dimm[RankToDimm];
+            //
+            // Since we're counting cache lines and won't wrap the row address,
+            // program Row Stop to RowSize - 1 to avoid resetting the current address.
+            // Column must wrap.  The wrap occurs on the increment which is after writing,
+            // to that address.  Thus, we set wrap to be the last accessed column.
+            //
+            WritesPerPage = DimmOut->ColumnSize / ColumnIncValUnaligned;  // Should be >= 4
+            ReutAddress.Stop[MrcReutFieldRow]     = (U16) DimmOut->RowSize - 1;
+            ReutAddress.Stop[MrcReutFieldCol]     = DimmOut->ColumnSize - ColumnIncValUnaligned;
+            ReutAddress.IncRate[MrcReutFieldRow]  = WritesPerPage - 1; // IncRate is +1 the programmed value
+
+            MrcProgramSequenceAddress (
+              MrcData,
+              Channel,
+              NULL,
+              ReutAddress.Stop,
+              NULL,
+              ReutAddress.IncRate,
+              NULL,
+              NULL,
+              NULL,
+              NULL,
+              0,
+              FALSE
+              );
+            //
+            // Set up the Subsequence control.
+            //
+            CrOffset = MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_REG +
+              ((MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_REG - MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_REG) * Channel);
+            //
+            // @todo: Review that the settings programmed here are common between the steppings.
+            //
+            ReutSubSeqCtl.Data = 0;
+            ReutSubSeqCtl.Bits.Subsequence_Type = BWr;
+            //
+            // Instead of matching wrap addresses, we will stop on 1 less cache line write from the top.
+            // This works because when aliasing occurs, the physical addressing size must double for row/col.
+            //
+            ReutSubSeqCtl.Bits.Number_of_Cachelines = MrcLog2 (((DimmOut->RowSize / MRC_BIT10) * WritesPerPage) - 1);
+            MrcWriteCR (
+              MrcData,
+              CrOffset,
+              ReutSubSeqCtl.Data
+              );
+
+            CrOffset += MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_REG - MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_REG;
+            ReutSubSeqCtl.Bits.Reset_Current_Base_Address_To_Start  = 1;
+            ReutSubSeqCtl.Bits.Subsequence_Type = BRd;
+            MrcWriteCR (
+              MrcData,
+              CrOffset,
+              ReutSubSeqCtl.Data
+              );
+          }
+        }
+
+        //
+        // Run the test
+        //
+        Status = MrcRunMemoryScrub (MrcData, ActiveChBitMask);
+        if (Status != mrcSuccess) {
+          break;
+        }
+      }
+    }
+
+    if (Outputs->EccSupport == TRUE) {
+      MRC_DEBUG_MSG(Debug, MSG_LEVEL_NOTE, "ReEnabling ECC Logic.  Must scrub after this!\n");
+      for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+        if (MrcChannelExist (Outputs, Channel)) {
+          CrOffset = MCDECS_CR_MAD_DIMM_CH0_MCMAIN_REG +
+            ((MCDECS_CR_MAD_DIMM_CH1_MCMAIN_REG - MCDECS_CR_MAD_DIMM_CH0_MCMAIN_REG) * Channel);
+
+          MrcWriteCR (MrcData, CrOffset, MadDimmCh[Channel].Data);
+        }
+      }
+    }
+    //
+    // Wait 4 usec after enabling the ECC IO, needed by HW
+    //
+    MrcWait (MrcData, 4 * HPET_1US);
+
+    //
+    // Return to normal operation mode
+    //
+    for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+      if (MrcChannelExist (Outputs, Channel)) {
+        ReutChSeqCfg.Data                     = 0;
+        ReutChSeqCfg.Bits.Initialization_Mode = NOP_Mode;
+        MrcWriteCR (
+          MrcData,
+          MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_REG +
+          ((MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_REG - MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_REG) * Channel),
+          (U32) ReutChSeqCfg.Data
+          );
+      }
+    }
+  }
+
+  if (mrcSuccess != Status) {
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "*** Alias Detected!  See REUT Error above. ***\n");
+    Outputs->SpdSecurityStatus = MrcSpdStatusAliased;
+    Status = mrcSuccess;
+  }
+
+  return Status;
+}
+
+/**
+@brief
+  This function runs the srcubbing test reporting any timeouts/errors.
+
+  @param[in] MrcData - The global host structure
+  @param[in] ChBitMask - Bitmask of channels the test is run on.
+
+  @retval mrcSuccess or error value.
+**/
+MrcStatus
+MrcRunMemoryScrub (
+  IN OUT MrcParameters *const MrcData,
+  IN     U8                   ChBitMask
+  )
+{
+  const MrcDebug  *Debug;
+  MrcStatus       Status;
+  U8              ErrorStatus;
+  U8              TestDoneStatus;
+  MCDFXS_CR_REUT_GLOBAL_CTL_MCMAIN_STRUCT       ReutGlobalCtl;
+  MCDFXS_CR_REUT_GLOBAL_ERR_MCMAIN_STRUCT       ReutGlobalErr;
+  U32  Timer;
+
+  Status = mrcSuccess;
+  Debug  = &MrcData->SysIn.Inputs.Debug;
+
+  //
+  // Setup Timer and run the test
+  //
+  Timer = (U32) MrcGetCpuTime() + 10000; // 10 Second timeout
+  ReutGlobalCtl.Data                                = 0;
+  ReutGlobalCtl.Bits.Global_Start_Test              = 1;
+  ReutGlobalCtl.Bits.Global_Clear_Errors            = 1;
+  ReutGlobalCtl.Bits.Global_Stop_Test_On_Any_Error  = NSOE;
+  MrcWriteCR (MrcData, MCDFXS_CR_REUT_GLOBAL_CTL_MCMAIN_REG, ReutGlobalCtl.Data);
+
+  //
+  // Wait until Channel test done status matches ChbitMask or TimeoutCounter value reaches 0;
+  //
+  do {
+    ReutGlobalErr.Data = MrcReadCR (MrcData, MCDFXS_CR_REUT_GLOBAL_ERR_MCMAIN_REG);
+    TestDoneStatus     = (U8) ((ReutGlobalErr.Bits.Channel_Test_Done_Status_1 << 1) |
+                                ReutGlobalErr.Bits.Channel_Test_Done_Status_0);
+  } while (((TestDoneStatus & ChBitMask) != ChBitMask) && ((U32) MrcGetCpuTime () < Timer));
+
+  if ((TestDoneStatus & ChBitMask) != ChBitMask) {
+    Status = mrcDeviceBusy;
+    MRC_DEBUG_MSG (
+      Debug,
+      MSG_LEVEL_ERROR,
+      "Timeout occured while running the test: ReutGlobalErr: 0x%X.\n",
+      ReutGlobalErr.Data
+      );
+  }
+
+  ErrorStatus = (U8) ((ReutGlobalErr.Bits.Channel_Error_Status_1 << 1) | ReutGlobalErr.Bits.Channel_Error_Status_0);
+  if (ErrorStatus & ChBitMask) {
+    Status = mrcReutSequenceError;
+    MRC_DEBUG_MSG (
+      Debug,
+      MSG_LEVEL_ERROR,
+      "REUT Error: Channel(s):%s%s\n",
+      (ReutGlobalErr.Bits.Channel_Error_Status_0 == 1) ? " 0" : "",
+      (ReutGlobalErr.Bits.Channel_Error_Status_1 == 1) ? " 1" : ""
+      );
+  }
+
+  return Status;
+}
+
diff --git a/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Api/MrcMemoryScrub.h b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Api/MrcMemoryScrub.h
new file mode 100644
index 0000000..d6d1695
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Api/MrcMemoryScrub.h
@@ -0,0 +1,78 @@
+/** @file
+  This file contains memory scrubbing and alias checking related information.
+
+@copyright
+  Copyright (c) 2012 Intel Corporation. All rights reserved.
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement.
+**/
+
+#ifndef _MrcMemoryScrub_h_
+#define _MrcMemoryScrub_h_
+#pragma pack (push, 1)
+
+#include "MrcTypes.h"
+#include "MrcApi.h"
+#include "MrcCommon.h"
+#include "MrcDebugHook.h"
+#include "MrcGlobal.h"
+
+/**
+@brief
+  This function sets all the memory to a known value when ECC is enabled and
+  either we are not in warm boot or we are in warm boot and TXT is set.
+
+  @param[in] MrcData - Include all MRC global data.
+
+  @retval mrcSuccess if the clean succeeded, otherwise an error status.
+**/
+extern
+MrcStatus
+MrcEccClean (
+  IN     MrcParameters *const MrcData
+  );
+
+/**
+@brief
+  This function performs a memory alias check.
+
+  @param[in] MrcData - The global host structure
+
+  @retval mrcSuccess or error value.
+**/
+extern
+MrcStatus
+MrcAliasCheck (
+  IN OUT MrcParameters *const MrcData
+  );
+
+/**
+@brief
+  This function runs the srcubbing test reporting any timeouts/errors.
+
+  @param[in] MrcData - The global host structure
+  @param[in] ChBitMask - Bitmask of channels the test is run on.
+
+  @retval mrcSuccess or error value.
+**/
+extern
+MrcStatus
+MrcRunMemoryScrub (
+  IN OUT MrcParameters *const MrcData,
+  IN     U8                   ChBitMask
+  );
+
+#pragma pack (pop)
+#endif
diff --git a/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Api/MrcSaveRestore.c b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Api/MrcSaveRestore.c
new file mode 100644
index 0000000..89464a5
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Api/MrcSaveRestore.c
@@ -0,0 +1,481 @@
+/** @file
+
+  Power state and boot mode save and restore data functions.
+
+@copyright
+  Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved.
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement.
+
+**/
+
+//
+// Include files
+//
+#include "MrcTypes.h"
+#include "MrcCommon.h"
+#include "MrcGeneral.h"
+#include "MrcGlobal.h"
+#include "MrcOem.h"
+#include "MrcSaveRestore.h"
+#include "MrcSpdProcessing.h"
+
+//
+// ------- IMPORTANT NOTE --------
+// MRC_MC_REGISTER_COUNT in Global.h should match this table.
+// Update this define whenever you add/remove registers from this table.
+//
+// Total register count = 1872 + 624 = 2496
+//
+const SaveDataControl SaveDataArray[] = {
+  {0x0000, 0x003C}, {0x0048, 0x004C}, {0x005C, 0x0078},  // 40h + 8 + 20h = 68h => 104 * 18 = 1872
+  {0x0100, 0x013C}, {0x0148, 0x014C}, {0x015C, 0x0178},
+  {0x0200, 0x023C}, {0x0248, 0x024C}, {0x025C, 0x0278},
+  {0x0300, 0x033C}, {0x0348, 0x034C}, {0x035C, 0x0378},
+  {0x0400, 0x043C}, {0x0448, 0x044C}, {0x045C, 0x0478},
+  {0x0500, 0x053C}, {0x0548, 0x054C}, {0x055C, 0x0578},
+  {0x0600, 0x063C}, {0x0648, 0x064C}, {0x065C, 0x0678},
+  {0x0700, 0x073C}, {0x0748, 0x074C}, {0x075C, 0x0778},
+  {0x0800, 0x083C}, {0x0848, 0x084C}, {0x085C, 0x0878},
+  {0x0900, 0x093C}, {0x0948, 0x094C}, {0x095C, 0x0978},
+  {0x0A00, 0x0A3C}, {0x0A48, 0x0A4C}, {0x0A5C, 0x0A78},
+  {0x0B00, 0x0B3C}, {0x0B48, 0x0B4C}, {0x0B5C, 0x0B78},
+  {0x0C00, 0x0C3C}, {0x0C48, 0x0C4C}, {0x0C5C, 0x0C78},
+  {0x0D00, 0x0D3C}, {0x0D48, 0x0D4C}, {0x0D5C, 0x0D78},
+  {0x0E00, 0x0E3C}, {0x0E48, 0x0E4C}, {0x0E5C, 0x0E78},
+  {0x0F00, 0x0F3C}, {0x0F48, 0x0F4C}, {0x0F5C, 0x0F78},
+  {0x1000, 0x103C}, {0x1048, 0x104C}, {0x105C, 0x1078},
+  {0x1100, 0x113C}, {0x1148, 0x114C}, {0x115C, 0x1178},
+  {0x1204, 0x1208},  //   8
+  {0x1214, 0x121C},  //  12
+  {0x1304, 0x1308},  //   8
+  {0x1314, 0x131C},  //  12
+  {0x1404, 0x140C},  //  12
+  {0x1504, 0x150C},  //  12
+  {0x1808, 0x1810},  //  12
+  {0x1908, 0x1910},  //  12
+  {0x1A04, 0x1A0C},  //  12
+  {0x1B04, 0x1B0C},  //  12
+  {0x1C14, 0x1C1C},  //  12
+  {0x1D14, 0x1D1C},  //  12
+  {0x2000, 0x2008},  //  12
+  {0x3A14, 0x3A1C},  //  12
+  {0x3A24, 0x3A24},  //   4
+  {0x4000, 0x4014},  //  24
+  {0x4024, 0x4028},  //   8
+  {0x40D0, 0x40D0},  //   4
+  {0x4220, 0x4224},  //   8
+  {0x4294, 0x4294},  //   4
+  {0x429C, 0x42A0},  //   8
+  {0x42EC, 0x42FC},  //  20
+  {0x438C, 0x4390},  //   8
+  {0x4328, 0x4328},  //   4
+  {0x4400, 0x4414},  //  24
+  {0x4424, 0x4428},  //   8
+  {0x44D0, 0x44D0},  //   4
+  {0x4620, 0x4624},  //   8
+  {0x4694, 0x4694},  //   4
+  {0x469C, 0x46A0},  //   8
+  {0x46EC, 0x46FC},  //  20
+  {0x4728, 0x4728},  //   4
+  {0x478C, 0x4790},  //   8
+  {0x5884, 0x5888},  //   8
+  {0x5890, 0x589C},  //  16
+  {0x58A4, 0x58A4},  //   4
+  {0x58D0, 0x58E4},  //  24
+  {0x5880, 0x5880},  //   4
+  {0x5000, 0x50DC},  // 224
+  {0x59b8, 0x59b8}   //   4
+};                   // = 624
+
+/**
+@brief
+  This function verifies that neither CPU fuses or DIMMs have changed.
+
+  @param[in] MrcData - Include all MRC global data.
+
+  @retval mrcSuccess if fast boot is allowed, otherwise mrcColdBootRequired.
+**/
+MrcStatus
+MrcFastBootPermitted (
+  IN     MrcParameters *const MrcData
+  )
+{
+  const MrcInput            *Inputs;
+  const MrcDimmIn           *DimmIn;
+  const U8                  *CrcStart;
+  MrcSaveData               *Save;
+  MrcDimmOut                *DimmSave;
+  MRC_PCI_000_CAPID0_STRUCT Capid0Reg;
+  U32                       CrcSize;
+  U8                        Controller;
+  U8                        Channel;
+  U8                        Dimm;
+  U16                       DimmCrc;
+  U32                       Offset;
+
+  CrcStart = NULL;
+  CrcSize  = 0;
+  Inputs   = &MrcData->SysIn.Inputs;
+  Save     = &MrcData->SysSave.Save.Data;
+
+  //
+  // Obtain the capabilities of the memory controller and see if they have changed.
+  //
+  Offset = MrcOemGetPcieDeviceAddress (0, 0, 0, MRC_PCI_000_CAPID0_REG);
+  MrcOemMmioRead (Offset, &Capid0Reg.Data32.A.Data, Inputs->PciEBaseAddress);
+  MrcOemMmioRead (Offset + 4, &Capid0Reg.Data32.B.Data, Inputs->PciEBaseAddress);
+  if (Capid0Reg.Data != Save->McCapId.Data) {
+    MRC_DEBUG_MSG (&Inputs->Debug, MSG_LEVEL_NOTE, "Capabilities have changed, cold boot required\n");
+    MRC_DEBUG_MSG (
+      &Inputs->Debug,
+      MSG_LEVEL_NOTE,
+      "  '%X_%X' --> '%X_%X'\n",
+      Save->McCapId.Data32[1],
+      Save->McCapId.Data32[0],
+      Capid0Reg.Data32.B.Data,
+      Capid0Reg.Data32.A.Data
+      );
+    return mrcColdBootRequired;
+  }
+  //
+  // See if any of the DIMMs have changed.
+  //
+  for (Controller = 0; Controller < MAX_CONTROLLERS; Controller++) {
+    for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+      for (Dimm = 0; Dimm < MAX_DIMMS_IN_CHANNEL; Dimm++) {
+        DimmIn   = &Inputs->Controller[Controller].Channel[Channel].Dimm[Dimm];
+        DimmSave = &Save->Controller[Controller].Channel[Channel].Dimm[Dimm];
+        if (DimmIn->Status == DIMM_DISABLED) {
+          DimmCrc = 0;
+        } else {
+          CrcStart = MrcSpdCrcArea (MrcData, Controller, Channel, Dimm, &CrcSize);
+          GetDimmCrc ((const U8 *const) CrcStart, CrcSize, &DimmCrc);
+        }
+
+        if (DimmCrc != DimmSave->Crc) {
+          MRC_DEBUG_MSG (
+            &Inputs->Debug,
+            MSG_LEVEL_NOTE,
+            "Channel %u Dimm %u has changed, cold boot required\n",
+            Channel,
+            Dimm
+            );
+          MRC_DEBUG_MSG (&Inputs->Debug, MSG_LEVEL_NOTE, "  DimmCrc %Xh, DimmSave->Crc %Xh\n", DimmCrc, DimmSave->Crc);
+          return mrcColdBootRequired;
+        }
+      }
+    }
+  }
+  //
+  // Set RestoreMRs flag to use trained Opt Param Values for Power Savings.
+  //
+  MrcData->SysOut.Outputs.RestoreMRs = TRUE;
+
+  return mrcSuccess;
+}
+
+/**
+@brief
+  This function saves any values that need to be used during non-cold boots.
+
+  @param[in, out] MrcData - Include all the MRC global data.
+
+  @retval mrcSuccess if the save occurred with no errors, otherwise returns an error code.
+**/
+MrcStatus
+MrcSaveMCValues (
+  IN OUT MrcParameters *const MrcData
+  )
+{
+  const SaveDataControl *SaveIt;
+  const MrcInput        *Inputs;
+  const MrcControllerIn *ControllerIn;
+  const MrcChannelIn    *ChannelIn;
+  const MrcSpd          *SpdIn;
+  MrcOutput             *Outputs;
+  MrcSaveData           *SaveData;
+  MrcSaveHeader         *SaveHeader;
+  MrcControllerOut      *ControllerOut;
+  MrcChannelOut         *ChannelOut;
+  MrcContSave           *ControllerSave;
+  MrcChannelSave        *ChannelSave;
+  MrcSpdSave            *SpdSavePtr;
+  U32                   *McRegister;
+  U8                    *SpdBegin;
+  MrcProfile            Profile;
+  U32                   Offset;
+  U32                   Index;
+  U32                   Value;
+  U8                    Controller;
+  U8                    Channel;
+  U8                    Dimm;
+  U8                    CopySize;
+
+  //
+  // Copy channel and DIMM information to the data area that will be saved.
+  //
+  Inputs      = &MrcData->SysIn.Inputs;
+  Outputs     = &MrcData->SysOut.Outputs;
+  SaveData    = &MrcData->SysSave.Save.Data;
+  SaveHeader  = &MrcData->SysSave.Save.Header;
+  for (Controller = 0; Controller < MAX_CONTROLLERS; Controller++) {
+    ControllerIn                  = &Inputs->Controller[Controller];
+    ControllerOut                 = &Outputs->Controller[Controller];
+    ControllerSave                = &SaveData->Controller[Controller];
+    ControllerSave->ChannelCount  = ControllerOut->ChannelCount;
+    ControllerSave->Status        = ControllerOut->Status;
+
+    for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+      ChannelIn   = &ControllerIn->Channel[Channel];
+      ChannelOut  = &ControllerOut->Channel[Channel];
+      ChannelSave                   = &ControllerSave->Channel[Channel];
+      ChannelSave->DimmCount        = ChannelOut->DimmCount;
+      ChannelSave->ValidRankBitMask = ChannelOut->ValidRankBitMask;
+      ChannelSave->EccSupport       = ChannelOut->EccSupport;
+      ChannelSave->Status           = ChannelOut->Status;
+      for (Profile = STD_PROFILE; Profile < MAX_PROFILE; Profile++) {
+        MrcOemMemoryCpy ((U8 *) &ChannelSave->Timing[Profile], (U8 *) &ChannelOut->Timing[Profile], sizeof (MrcTiming));
+      }
+      for (Dimm = 0; Dimm < MAX_DIMMS_IN_CHANNEL; Dimm++) {
+        MrcOemMemoryCpy ((U8 *) &ChannelSave->Dimm[Dimm], (U8 *) &ChannelOut->Dimm[Dimm], sizeof (MrcDimmOut));
+        SpdIn = &ChannelIn->Dimm[Dimm].Spd;
+        SpdSavePtr = &ChannelSave->SpdSave[Dimm];
+        {
+          SpdSavePtr->SmbiosData.ModuleType           = SpdIn->Ddr3.General.ModuleType;
+          SpdSavePtr->SmbiosData.ModuleMemoryBusWidth = SpdIn->Ddr3.General.ModuleMemoryBusWidth;
+          SpdBegin = (U8 *) &SpdIn->Ddr3.ModuleId;
+          CopySize = sizeof (SpdSavePtr->ManufacturingData.Ddr3Data);
+        }
+        //
+        // Save just enough SPD information so it can be restored during non-cold boot.
+        //
+        MrcOemMemoryCpy ((U8 *) &SpdSavePtr->ManufacturingData, SpdBegin, CopySize);
+      } // for Dimm
+    } // for Channel
+  } // for Controller
+
+  for (Profile = STD_PROFILE; Profile < MAX_PROFILE; Profile++) {
+    SaveData->VddVoltage[Profile] = Outputs->VddVoltage[Profile];
+  }
+
+  //
+  // Copy specified memory controller MMIO registers to the data area that will be saved.
+  //
+  McRegister = SaveData->McRegister;
+  for (Index = 0; Index < (sizeof (SaveDataArray) / sizeof (SaveDataControl)); Index++) {
+    SaveIt = &SaveDataArray[Index];
+    for (Offset = SaveIt->StartMchbarOffset; Offset <= SaveIt->EndMchbarOffset; Offset += sizeof (U32)) {
+      Value         = MrcReadCR (MrcData, Offset);
+      *McRegister++ = Value;
+    }
+  }
+
+//
+// ------- IMPORTANT NOTE --------
+// MeStolenSize should not be saved/restored.  There is no rule stating that ME FW cannot request a different
+// amount of ME UMA space from one boot to the next.  Also, if ME FW is updated/changed, the UMA Size requested
+// from the previous version should not be restored.
+//
+
+  MrcVersionGet (&SaveData->Version);
+  SaveData->CpuModel         = Inputs->CpuModel;
+  SaveData->CpuStepping      = Inputs->CpuStepping;
+  SaveData->Frequency        = Outputs->Frequency;
+  SaveData->MemoryClock      = Outputs->MemoryClock;
+  SaveData->Ratio            = Outputs->Ratio;
+  SaveData->RefClk           = Outputs->RefClk;
+  SaveData->EccSupport       = Outputs->EccSupport;
+  SaveData->DdrType          = Outputs->DdrType;
+  SaveData->XmpProfileEnable = Outputs->XmpProfileEnable;
+
+  SaveData->SaMemCfgCrc = MrcCalculateCrc32 ((U8 *) Inputs->SaMemCfgAddress, Inputs->SaMemCfgSize);
+  SaveHeader->Crc       = MrcCalculateCrc32 ((U8 *) SaveData, sizeof (MrcSaveData));
+  MRC_DEBUG_MSG (&Inputs->Debug, MSG_LEVEL_NOTE, "Saved data CRC = %xh\n", SaveHeader->Crc);
+
+  return mrcSuccess;
+}
+
+/**
+@brief
+  This function copies the non-training information that needs to be restored
+  from the 'save' data structure to the 'Output' data structure.
+
+  @param[in, out] MrcData - include all the MRC global data.
+
+  @retval mrcSuccess if the copy completed with no errors, otherwise returns an error code.
+**/
+MrcStatus
+MrcRestoreNonTrainingValues (
+  IN OUT MrcParameters *const MrcData
+  )
+{
+  MrcInput          *Inputs;
+  MrcControllerIn   *ControllerIn;
+  MrcChannelIn      *ChannelIn;
+  MrcSaveData       *SaveData;
+  MrcContSave       *ControllerSave;
+  MrcChannelSave    *ChannelSave;
+  MrcDimmOut        *DimmSave;
+  MrcOutput         *Outputs;
+  MrcControllerOut  *ControllerOut;
+  MrcChannelOut     *ChannelOut;
+  MrcDimmOut        *DimmOut;
+  MrcSpd            *SpdIn;
+  MrcSpdSave        *SpdSavePtr;
+  U8                *SpdBegin;
+  MrcProfile        Profile;
+  U8                Controller;
+  U8                Channel;
+  U8                Dimm;
+  U8                CopySize;
+
+  SaveData = &MrcData->SysSave.Save.Data;
+  Outputs  = &MrcData->SysOut.Outputs;
+  Inputs = &MrcData->SysIn.Inputs;
+  for (Controller = 0; Controller < MAX_CONTROLLERS; Controller++) {
+    ControllerIn                = &Inputs->Controller[Controller];
+    ControllerSave              = &SaveData->Controller[Controller];
+    ControllerOut               = &Outputs->Controller[Controller];
+    ControllerOut->ChannelCount = ControllerSave->ChannelCount;
+    ControllerOut->Status       = ControllerSave->Status;
+    for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+      ChannelIn                     = &ControllerIn->Channel[Channel];
+      ChannelSave                   = &ControllerSave->Channel[Channel];
+      ChannelOut                    = &ControllerOut->Channel[Channel];
+      ChannelOut->DimmCount         = ChannelSave->DimmCount;
+      ChannelOut->ValidRankBitMask  = ChannelSave->ValidRankBitMask;
+      ChannelOut->EccSupport        = ChannelSave->EccSupport;
+      ChannelOut->Status            = ChannelSave->Status;
+      for (Profile = STD_PROFILE; Profile < MAX_PROFILE; Profile++) {
+        MrcOemMemoryCpy ((U8 *) &ChannelOut->Timing[Profile], (U8 *) &ChannelSave->Timing[Profile], sizeof (MrcTiming));
+      }
+      for (Dimm = 0; Dimm < MAX_DIMMS_IN_CHANNEL; Dimm++) {
+        DimmSave = &ChannelSave->Dimm[Dimm];
+        if (DimmSave->Status == DIMM_PRESENT || DimmSave->Status == DIMM_DISABLED) {
+          DimmOut     = &ChannelOut->Dimm[Dimm];
+          SpdIn       = &ChannelIn->Dimm[Dimm].Spd;
+          SpdSavePtr  = &ChannelSave->SpdSave[Dimm];
+          MrcOemMemoryCpy ((U8 *) DimmOut, (U8 *) DimmSave, sizeof (MrcDimmOut));
+          {
+            SpdIn->Ddr3.General.ModuleType           = SpdSavePtr->SmbiosData.ModuleType;
+            SpdIn->Ddr3.General.ModuleMemoryBusWidth = SpdSavePtr->SmbiosData.ModuleMemoryBusWidth;
+            SpdBegin = (U8 *) &SpdIn->Ddr3.ModuleId;
+            CopySize = sizeof (SpdSavePtr->ManufacturingData.Ddr3Data);
+          }
+          //
+          // Restore just enough SPD information so it can be passed out in the HOB.
+          //
+          MrcOemMemoryCpy (SpdBegin, (U8 *) &SpdSavePtr->ManufacturingData, CopySize);
+        } // if
+      } // for Dimm
+    } // for Channel
+  } // for Controller
+
+  for (Profile = STD_PROFILE; Profile < MAX_PROFILE; Profile++) {
+    Outputs->VddVoltage[Profile] = SaveData->VddVoltage[Profile];
+  }
+
+//
+// ------- IMPORTANT NOTE --------
+// MeStolenSize should not be saved/restored.  There is no rule stating that ME FW cannot request a different
+// amount of ME UMA space from one boot to the next.  Also, if ME FW is updated/changed, the UMA Size requested
+// from the previous version should not be restored.
+//
+
+  Inputs->CpuModel          = SaveData->CpuModel;
+  Inputs->CpuStepping       = SaveData->CpuStepping;
+  Outputs->Frequency        = SaveData->Frequency;
+  Outputs->MemoryClock      = SaveData->MemoryClock;
+  Outputs->Ratio            = SaveData->Ratio;
+  Outputs->RefClk           = SaveData->RefClk;
+  Outputs->EccSupport       = SaveData->EccSupport;
+  Outputs->DdrType          = SaveData->DdrType;
+  Outputs->XmpProfileEnable = SaveData->XmpProfileEnable;
+
+  return mrcSuccess;
+}
+
+/**
+@brief
+  This function writes the previously determined training values back to the memory controller.
+
+  @param[in] MrcData - Include all the MRC global data.
+
+  @retval mrcSuccess if the memory controller write back completed with no errors, otherwise returns an error code.
+**/
+MrcStatus
+MrcRestoreTrainingValues (
+  IN     MrcParameters *const MrcData
+  )
+{
+  const SaveDataControl *RestoreIt;
+  U32                   *McRegister;
+  U32                   Offset;
+  U32                   Index;
+  U32                   Value;
+
+  McRegister = MrcData->SysSave.Save.Data.McRegister;
+  for (Index = 0; Index < (sizeof (SaveDataArray) / sizeof (SaveDataControl)); Index++) {
+    RestoreIt = &SaveDataArray[Index];
+    for (Offset = RestoreIt->StartMchbarOffset; Offset <= RestoreIt->EndMchbarOffset; Offset += sizeof (U32)) {
+      Value = *McRegister++;
+      MrcWriteCR (MrcData, Offset, Value);
+    }
+  }
+
+  return mrcSuccess;
+}
+
+/**
+@brief
+  Calculates a CRC-32 of the specified data buffer.
+
+  @param[in] Data     - Pointer to the data buffer.
+  @param[in] DataSize - Size of the data buffer, in bytes.
+
+  @retval The CRC-32 value.
+**/
+U32
+MrcCalculateCrc32 (
+  IN     const U8          *const Data,
+  IN     const U32         DataSize
+  )
+{
+  U32 i;
+  U32 j;
+  U32 crc;
+  U32 CrcTable[256];
+
+  crc = (U32) (-1);
+
+  //
+  // Initialize the CRC base table.
+  //
+  for (i = 0; i < 256; i++) {
+    CrcTable[i] = i;
+    for (j = 8; j > 0; j--) {
+      CrcTable[i] = (CrcTable[i] & 1) ? (CrcTable[i] >> 1) ^ 0xEDB88320 : CrcTable[i] >> 1;
+    }
+  }
+  //
+  // Calculate the CRC.
+  //
+  for (i = 0; i < DataSize; i++) {
+    crc = (crc >> 8) ^ CrcTable[(U8) crc ^ (Data)[i]];
+  }
+
+  return ~crc;
+}
diff --git a/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Api/MrcSaveRestore.h b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Api/MrcSaveRestore.h
new file mode 100644
index 0000000..e752cd4
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Api/MrcSaveRestore.h
@@ -0,0 +1,117 @@
+/** @file
+  Power state and boot mode save and restore data functions.
+
+@copyright
+  Copyright (c) 2011 - 2012 Intel Corporation. All rights reserved.
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement
+**/
+
+#ifndef _MrcSaveRestore_h_
+#define _MrcSaveRestore_h_
+#pragma pack(push, 1)
+
+#include "MrcTypes.h"
+#include "MrcGlobal.h"
+
+typedef struct {
+  U16 StartMchbarOffset;
+  U16 EndMchbarOffset;
+} SaveDataControl;
+
+/**
+  This function verifies that neither CPU fuses or DIMMs have changed.
+
+  @param[in] MrcData - Include all MRC global data.
+
+  @retval mrcSuccess if fast boot is allowed, otherwise mrcColdBootRequired.
+**/
+extern
+MrcStatus
+MrcFastBootPermitted (
+  IN     MrcParameters *const MrcData
+  );
+
+/**
+  This function saves any values that need to be used during non-cold boots.
+
+  @param[in, out] MrcData - Include all the MRC global data.
+
+  @retval mrcSuccess if the save occurred with no errors, otherwise returns an error code.
+**/
+extern
+MrcStatus
+MrcSaveMCValues (
+  IN OUT MrcParameters *const MrcData
+  );
+
+/**
+@brief
+  This function saves any remaining values that need to be used during non-cold boots.
+
+  @param[in, out] MrcData - Include all the MRC global data.
+
+  @retval mrcSuccess if the save occurred with no errors, otherwise returns an error code.
+**/
+extern
+MrcStatus
+MrcSaveMCValuesFinal (
+  IN OUT MrcParameters *const MrcData
+  );
+
+/**
+  This function copies the non-training information that needs to be restored
+  from the 'save' data structure to the 'Output' data structure.
+
+  @param[in, out] MrcData - include all the MRC global data.
+
+  @retval mrcSuccess if the copy completed with no errors, otherwise returns an error code.
+**/
+extern
+MrcStatus
+MrcRestoreNonTrainingValues (
+  IN OUT MrcParameters *const MrcData
+  );
+
+/**
+  This function writes the previously determined training values back to the memory controller.
+
+  @param[in] MrcData - Include all the MRC global data.
+
+  @retval mrcSuccess if the memory controller write back completed with no errors, otherwise returns an error code.
+**/
+extern
+MrcStatus
+MrcRestoreTrainingValues (
+  IN     MrcParameters *const MrcData
+  );
+
+/**
+  Calculates a CRC-32 of the specified data buffer.
+
+  @param[in] Data     - Pointer to the data buffer.
+  @param[in] DataSize - Size of the data buffer, in bytes.
+
+  @retval The CRC-32 value.
+**/
+extern
+U32
+MrcCalculateCrc32 (
+  IN     const U8          *const Data,
+  IN     const U32         DataSize
+  );
+
+#pragma pack(pop)
+#endif
diff --git a/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Api/MrcStartMemoryConfiguration.c b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Api/MrcStartMemoryConfiguration.c
new file mode 100644
index 0000000..063e899
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Api/MrcStartMemoryConfiguration.c
@@ -0,0 +1,236 @@
+/** @file
+  Starting point for the core memory reference code.
+
+@copyright
+  Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved.
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement
+
+**/
+
+//
+// Include files
+//
+#include "MrcTypes.h"
+#include "MrcApi.h"
+#include "MrcCommandTraining.h"
+#include "MrcCommon.h"
+#include "MrcCrosser.h"
+#include "MrcDdr3.h"
+#include "MrcDebugHook.h"
+#include "MrcGeneral.h"
+#include "MrcGlobal.h"
+#include "MrcBdat.h"
+#include "MrcMcConfiguration.h"
+#include "MrcMemoryMap.h"
+#include "MrcMemoryScrub.h"
+#include "MrcOem.h"
+#include "MrcReadDqDqs.h"
+#include "MrcReadReceiveEnable.h"
+#include "MrcReset.h"
+#include "MrcSaveRestore.h"
+#include "MrcSpdProcessing.h"
+#include "MrcStartMemoryConfiguration.h"
+#include "MrcWriteDqDqs.h"
+#include "MrcWriteLeveling.h"
+
+/**
+  Print the input parameters to the debug message output port.
+
+  @param[in] MrcData - The MRC global data.
+
+  @retval mrcSuccess
+**/
+
+//
+// Functions:
+//
+const CallTableEntry  CallTable[] = {
+  ///
+  /// The functions are executed in the following order, as the policy flag dictates.
+  /// Mrctask, post_code, OEM command, policy_flag, iteration, debug_string
+  ///
+  {MrcFastBootPermitted,       MRC_FAST_BOOT_PERMITTED,      OemFastBootPermitted,                                           MRC_PF_FAST | MRC_PF_FULL_MRC | MRC_PF_MINI_MRC, MRC_ITERATION_MAX, MRC_DEBUG_TEXT("Fast boot permitted")},
+  {MrcRestoreNonTrainingValues,MRC_RESTORE_NON_TRAINING,     OemRestoreNonTraining,                MRC_PF_WARM | MRC_PF_S3 | MRC_PF_FAST | MRC_PF_FULL_MRC | MRC_PF_MINI_MRC, MRC_ITERATION_MAX, MRC_DEBUG_TEXT("Restore non-training values")},
+#ifdef MRC_DEBUG_PRINT
+  {MrcPrintInputParameters,    MRC_PRINT_INPUT_PARAMS,       OemPrintInputParameters,MRC_PF_COLD | MRC_PF_WARM             | MRC_PF_FAST | MRC_PF_FULL_MRC,                   MRC_ITERATION_MAX, MRC_DEBUG_TEXT("Print input parameters")},
+#endif // MRC_DEBUG_PRINT
+  {MrcSetOverridesPreSpd,      MRC_SET_OVERRIDES_PSPD,       OemSetOverridePreSpd,   MRC_PF_COLD | MRC_PF_WARM | MRC_PF_S3 | MRC_PF_FAST | MRC_PF_FULL_MRC | MRC_PF_MINI_MRC, MRC_ITERATION_MAX, MRC_DEBUG_TEXT("Pre-SPD Timing overrides")},
+  {MrcMcCapabilityPreSpd,      MRC_MC_CAPABILITY_PSPD,       OemMcCapabilityPreSpd,  MRC_PF_COLD | MRC_PF_WARM | MRC_PF_S3 | MRC_PF_FAST | MRC_PF_FULL_MRC | MRC_PF_MINI_MRC, MRC_ITERATION_MAX, MRC_DEBUG_TEXT("Pre-SPD MC Capabilities")},
+  {MrcSpdProcessing,           MRC_SPD_PROCESSING,           OemSpdProcessingRun,    MRC_PF_COLD                                         | MRC_PF_FULL_MRC | MRC_PF_MINI_MRC, MRC_ITERATION_MAX, MRC_DEBUG_TEXT("SPD PROCESSING")},
+  {MrcSetOverrides,            MRC_SET_OVERRIDES,            OemSetOverride,         MRC_PF_COLD | MRC_PF_WARM | MRC_PF_S3 | MRC_PF_FAST | MRC_PF_FULL_MRC | MRC_PF_MINI_MRC, MRC_ITERATION_MAX, MRC_DEBUG_TEXT("Timing overrides")},
+  {MrcMcCapability,            MRC_MC_CAPABILITY,            OemMcCapability,        MRC_PF_COLD | MRC_PF_WARM | MRC_PF_S3 | MRC_PF_FAST | MRC_PF_FULL_MRC | MRC_PF_MINI_MRC, MRC_ITERATION_MAX, MRC_DEBUG_TEXT("MC Capabilities")},
+  {MrcMcConfiguration,         MRC_MC_CONFIG,                OemMcInitRun,           MRC_PF_COLD | MRC_PF_WARM | MRC_PF_S3 | MRC_PF_FAST | MRC_PF_FULL_MRC | MRC_PF_MINI_MRC, MRC_ITERATION_MAX, MRC_DEBUG_TEXT("MC CONFIG")},
+  {MrcSetMemoryMap,            MRC_MC_MEMORY_MAP,            OemMcMemoryMap,         MRC_PF_COLD | MRC_PF_WARM | MRC_PF_S3 | MRC_PF_FAST | MRC_PF_FULL_MRC | MRC_PF_MINI_MRC, MRC_ITERATION_MAX, MRC_DEBUG_TEXT("MC MEMORY MAP")},
+  {MrcResetSequence,           MRC_RESET_SEQUENCE,           OemMcResetRun,          MRC_PF_COLD                           | MRC_PF_FAST | MRC_PF_FULL_MRC | MRC_PF_MINI_MRC, MRC_ITERATION_MAX, MRC_DEBUG_TEXT("JEDEC RESET")},
+  {MrcPreTraining,             MRC_PRE_TRAINING,             OemPreTraining,         MRC_PF_COLD                           | MRC_PF_FAST | MRC_PF_FULL_MRC | MRC_PF_MINI_MRC, MRC_ITERATION_MAX, MRC_DEBUG_TEXT("Pre-Training")},
+  {MrcSenseAmpOffsetTraining,  MRC_SENSE_AMP_OFFSET,         OemSenseAmpTraining,    MRC_PF_COLD                                         | MRC_PF_FULL_MRC | MRC_PF_MINI_MRC, MRC_ITERATION_MAX, MRC_DEBUG_TEXT("SenseAmp Offset Training")},
+  {MrcEarlyCommandTraining,    MRC_EARLY_COMMAND,            OemEarlyCommandTraining,MRC_PF_COLD                                         | MRC_PF_FULL_MRC | MRC_PF_MINI_MRC, MRC_ITERATION_MAX, MRC_DEBUG_TEXT("Early command training")},
+#ifdef ULT_FLAG
+  {MrcJedecInitLpddr3,         MRC_JEDEC_INIT_LPDDR3,        OemJedecInitLpddr3,     MRC_PF_COLD                                         | MRC_PF_FULL_MRC | MRC_PF_MINI_MRC, MRC_ITERATION_MAX, MRC_DEBUG_TEXT("LPDDR3 JEDEC INIT")},
+#endif // ULT_FLAG
+  {MrcReadLevelingTraining,    MRC_RECEIVE_ENABLE,           OemReceiveEnable,       MRC_PF_COLD                                         | MRC_PF_FULL_MRC | MRC_PF_MINI_MRC, MRC_ITERATION_MAX, MRC_DEBUG_TEXT("Read Leveling training")},
+  {MrcReadMprTraining,         MRC_READ_MPR,                 OemReadMprTraining,     MRC_PF_COLD                                         | MRC_PF_FULL_MRC | MRC_PF_MINI_MRC, MRC_ITERATION_MAX, MRC_DEBUG_TEXT("Read MPR training")},
+
+  {MrcJedecWriteLevelingTraining,MRC_JEDEC_WRITE_LEVELING,   OemJedecWriteLeveling,  MRC_PF_COLD                                         | MRC_PF_FULL_MRC | MRC_PF_MINI_MRC, MRC_ITERATION_MAX, MRC_DEBUG_TEXT("Jedec Write Leveling training")},
+
+  {MrcWriteTimingCentering,    MRC_WRITE_TIMING_1D,          OemWriteDqDqs,          MRC_PF_COLD                                         | MRC_PF_FULL_MRC | MRC_PF_MINI_MRC, MRC_ITERATION_MAX, MRC_DEBUG_TEXT("Write Timing Centering")},
+  {MrcReadTimingCentering,     MRC_READ_TIMING_1D,           OemReadDqDqs,           MRC_PF_COLD                                         | MRC_PF_FULL_MRC | MRC_PF_MINI_MRC, MRC_ITERATION_MAX, MRC_DEBUG_TEXT("Read Timing Centering")},
+
+  {MrcPowerSavingMeter,        MRC_PWR_MTR,                  OemPowerSavingMeter,    MRC_PF_COLD                                         | MRC_PF_FULL_MRC | MRC_PF_MINI_MRC, MRC_ITERATION_MAX, MRC_DEBUG_TEXT("PowerSavingMeter Base Line Update")},
+  {MrcDimmRonTraining,         MRC_DIMM_RON,                 OemDimmRonTraining,     MRC_PF_COLD                                         | MRC_PF_FULL_MRC | MRC_PF_MINI_MRC, MRC_ITERATION_MAX, MRC_DEBUG_TEXT("DIMM Ron Training")},
+  {MrcDimmODTTraining,         MRC_DIMM_ODT,                 OemDimmODTTraining,     MRC_PF_COLD                                         | MRC_PF_FULL_MRC | MRC_PF_MINI_MRC, MRC_ITERATION_MAX, MRC_DEBUG_TEXT("DIMM ODT Training")},
+  {MrcDimmODT1dTraining,       MRC_DIMM_ODT,                 OemDimmODT1dTraining,   MRC_PF_COLD                                         | MRC_PF_FULL_MRC | MRC_PF_MINI_MRC, MRC_ITERATION_MAX, MRC_DEBUG_TEXT("DIMM ODT 1d Training")},
+
+  {MrcWriteDriveStrength,      MRC_WRITE_DS,                 OemWriteDriveStrength,  MRC_PF_COLD                                         | MRC_PF_FULL_MRC | MRC_PF_MINI_MRC, MRC_ITERATION_MAX, MRC_DEBUG_TEXT("Write Drive Strength")},
+  {MrcWriteEQTraining,         MRC_WRITE_EQ,                 OemWriteEQTraining,     MRC_PF_COLD                                         | MRC_PF_FULL_MRC | MRC_PF_MINI_MRC, MRC_ITERATION_MAX, MRC_DEBUG_TEXT("Write Equalization Training")},
+  {MrcReadODTTraining,         MRC_READ_ODT,                 OemReadODTTraining,     MRC_PF_COLD                                         | MRC_PF_FULL_MRC | MRC_PF_MINI_MRC, MRC_ITERATION_MAX, MRC_DEBUG_TEXT("Read ODT Training")},
+
+  {MrcWriteSlewRate,           MRC_WRITE_SR,                 OemWriteSlewRate,       MRC_PF_COLD                                         | MRC_PF_FULL_MRC | MRC_PF_MINI_MRC, MRC_ITERATION_MAX, MRC_DEBUG_TEXT("Write Slew Rate")},
+  {MrcReadAmplifierPower,      MRC_READ_AMP_POWER,           OemReadAmplifierPower,  MRC_PF_COLD                                         | MRC_PF_FULL_MRC | MRC_PF_MINI_MRC, MRC_ITERATION_MAX, MRC_DEBUG_TEXT("Read Amplifier Power")},
+  {MrcReadEQTraining,          MRC_READ_EQ,                  OemReadEQTraining,      MRC_PF_COLD                                         | MRC_PF_FULL_MRC | MRC_PF_MINI_MRC, MRC_ITERATION_MAX, MRC_DEBUG_TEXT("Read Equalization Training")},
+  {MrcOptimizeComp,            MRC_CMP_OPT,                  OemOptimizeComp,        MRC_PF_COLD                                         | MRC_PF_FULL_MRC | MRC_PF_MINI_MRC, MRC_ITERATION_MAX, MRC_DEBUG_TEXT("Comp Optimization Training")},
+//
+/// @attention This sections of tests are left for future testing.  Determine later if we can remove.
+//  {MrcTestGetMarginBitWrTBit,     MRC_ODT_STRETCH_START,      OemReadODTTraining,     MRC_PF_COLD                                         | MRC_PF_FULL_MRC | MRC_PF_MINI_MRC, MRC_ITERATION_MAX, MRC_DEBUG_TEXT("Get the Margins per CHANNEL")},
+//  {MrcTestGetBERMarginByteWrT,    MRC_READ_START,             OemReadEQTraining,      MRC_PF_COLD                                         | MRC_PF_FULL_MRC | MRC_PF_MINI_MRC, MRC_ITERATION_MAX, MRC_DEBUG_TEXT("Get the Margins per BYTE for RcvEn")},
+//  {MrcTestGetBERMarginByteRdT,    MRC_READ_START,             OemReadAmplifierPower,  MRC_PF_COLD                                         | MRC_PF_FULL_MRC | MRC_PF_MINI_MRC, MRC_ITERATION_MAX, MRC_DEBUG_TEXT("Get the Margins per BYTE for RdT")},
+//  {MrcTestGetBERMarginByteRcvEna, MRC_WRITE_START,            OemWriteDqDqs2D,        MRC_PF_COLD                                         | MRC_PF_FULL_MRC | MRC_PF_MINI_MRC, MRC_ITERATION_MAX, MRC_DEBUG_TEXT("Get the Margins per BYTE for WrT")},
+//  {MrcTestGetBERMarginByteWrDqsT, MRC_READ_START,             OemReadDqDqs2D,         MRC_PF_COLD                                         | MRC_PF_FULL_MRC | MRC_PF_MINI_MRC, MRC_ITERATION_MAX, MRC_DEBUG_TEXT("Get the Margins per BYTE for WrdqsT")},
+//  {MrcTestGetBERMarginByteWrLevel,MRC_WRITE_START,            OemWriteVoltCentering2D,MRC_PF_COLD                                         | MRC_PF_FULL_MRC | MRC_PF_MINI_MRC, MRC_ITERATION_MAX, MRC_DEBUG_TEXT("Get the Margins per BYTE for WrLevel")},
+//  {MrcTestGetBERMarginCh,         MRC_READ_START,             OemReadVoltCentering2D, MRC_PF_COLD                                         | MRC_PF_FULL_MRC | MRC_PF_MINI_MRC, MRC_ITERATION_MAX, MRC_DEBUG_TEXT("Get the Margins per BIT for WrTBit")},
+//  {MrcTestGetMarginBitRdTBit,     MRC_READ_START,             OemWriteXtalkCancel,    MRC_PF_COLD                                         | MRC_PF_FULL_MRC | MRC_PF_MINI_MRC, MRC_ITERATION_MAX, MRC_DEBUG_TEXT("Get the Margins per BIT for RdTBit")},
+//
+  {MrcPostTraining,            MRC_POST_TRAINING,            OemPostTraining,        MRC_PF_COLD                                         | MRC_PF_FULL_MRC | MRC_PF_MINI_MRC, MRC_ITERATION_MAX, MRC_DEBUG_TEXT("Post-training")},
+  {MrcLateCommandTraining,     MRC_LATE_COMMAND,             OemLateCommandTraining, MRC_PF_COLD                                         | MRC_PF_FULL_MRC | MRC_PF_MINI_MRC, MRC_ITERATION_MAX, MRC_DEBUG_TEXT("Late command training")},
+
+  {MrcCmdVoltageCentering,     MRC_CMD_VREF,                 OemCmdVoltCentering,    MRC_PF_COLD                                         | MRC_PF_FULL_MRC | MRC_PF_MINI_MRC, MRC_ITERATION_MAX, MRC_DEBUG_TEXT("Command Voltage Centering")},
+  {MrcWriteVoltageCentering2D, MRC_WRITE_VREF_2D,            OemWriteVoltCentering2D,MRC_PF_COLD                                         | MRC_PF_FULL_MRC | MRC_PF_MINI_MRC, MRC_ITERATION_MAX, MRC_DEBUG_TEXT("Write Voltage Centering 2D")},
+  {MrcReadVoltageCentering2D,  MRC_READ_VREF_2D,             OemReadVoltCentering2D, MRC_PF_COLD                                         | MRC_PF_FULL_MRC | MRC_PF_MINI_MRC, MRC_ITERATION_MAX, MRC_DEBUG_TEXT("Read Voltage Centering 2D")},
+
+  {MrcWriteTimingCentering2D,  MRC_WRITE_TIMING_2D,          OemWriteDqDqs2D,        MRC_PF_COLD                                         | MRC_PF_FULL_MRC | MRC_PF_MINI_MRC, MRC_ITERATION_MAX, MRC_DEBUG_TEXT("Write Timing Centering 2D")},
+  {MrcReadTimingCentering2D,   MRC_READ_TIMING_2D,           OemReadDqDqs2D,         MRC_PF_COLD                                         | MRC_PF_FULL_MRC | MRC_PF_MINI_MRC, MRC_ITERATION_MAX, MRC_DEBUG_TEXT("Read Timing Centering 2D")},
+
+  {MrcRoundTripLatency,        MRC_ROUND_TRIP_LAT,           OemRoundTripLatency,    MRC_PF_COLD                                         | MRC_PF_FULL_MRC | MRC_PF_MINI_MRC, MRC_ITERATION_MAX, MRC_DEBUG_TEXT("Round Trip Latency Training")},
+  {MrcTurnAroundTiming,        MRC_TURN_AROUND,              OemTurnAroundTimes,     MRC_PF_COLD                                         | MRC_PF_FULL_MRC | MRC_PF_MINI_MRC, MRC_ITERATION_MAX, MRC_DEBUG_TEXT("Turn Around Trip Training")},
+#ifdef ULT_FLAG
+  {MrcReceiveEnTimingCentering,MRC_RCVEN_TIMING_1D,          OemRcvEnCentering1D,    MRC_PF_COLD                                         | MRC_PF_FULL_MRC | MRC_PF_MINI_MRC, MRC_ITERATION_MAX, MRC_DEBUG_TEXT("Receive Enable Timing Centering")},
+#endif // ULT_FLAG
+  {MrcRetrainMarginCheck,      MRC_RETRAIN_CHECK,            OemRetrainMarginCheck,  MRC_PF_COLD                                         | MRC_PF_FULL_MRC | MRC_PF_MINI_MRC, 1, MRC_DEBUG_TEXT("Check Margin for Retrain")},
+  {MrcRankMarginTool,          MRC_RMT_TOOL,                 OemRmt,                 MRC_PF_COLD                                         | MRC_PF_FULL_MRC | MRC_PF_MINI_MRC, MRC_ITERATION_MAX, MRC_DEBUG_TEXT("Rank Margin Tool")},
+  {MrcPowerSavingMeter,        MRC_PWR_MTR,                  OemPowerSavingMeter,    MRC_PF_COLD                                         | MRC_PF_FULL_MRC | MRC_PF_MINI_MRC, MRC_ITERATION_MAX, MRC_DEBUG_TEXT("PowerSavingMeter update")},
+  {MrcMcActivate,              MRC_MC_ACTIVATE,              OemMrcActivate,         MRC_PF_COLD                                         | MRC_PF_FULL_MRC | MRC_PF_MINI_MRC, MRC_ITERATION_MAX, MRC_DEBUG_TEXT("MRC activate")},
+  {MrcSaveMCValues,            MRC_SAVE_MC_VALUES,           OemSaveMCValues,        MRC_PF_COLD                                         | MRC_PF_FULL_MRC | MRC_PF_MINI_MRC, MRC_ITERATION_MAX, MRC_DEBUG_TEXT("Save MC Values")},
+  {MrcRestoreTrainingValues,   MRC_RESTORE_TRAINING,         OemRestoreTraining,                   MRC_PF_WARM | MRC_PF_S3 | MRC_PF_FAST | MRC_PF_FULL_MRC | MRC_PF_MINI_MRC, MRC_ITERATION_MAX, MRC_DEBUG_TEXT("Restore Training Values")},
+#ifdef ULT_FLAG
+  {MrcJedecInitLpddr3,         MRC_JEDEC_INIT_LPDDR3,        OemJedecInitLpddr3,                                             MRC_PF_FAST | MRC_PF_FULL_MRC | MRC_PF_MINI_MRC, MRC_ITERATION_MAX, MRC_DEBUG_TEXT("LPDDR3 JEDEC INIT")},
+#endif // ULT_FLAG
+  {MrcSelfRefreshExit,         MRC_SELF_REFRESH_EXIT,        OemSelfRefreshExit,                   MRC_PF_WARM | MRC_PF_S3               | MRC_PF_FULL_MRC | MRC_PF_MINI_MRC, MRC_ITERATION_MAX, MRC_DEBUG_TEXT("Perform Self Refresh Exit")},
+  {MrcNormalMode,              MRC_NORMAL_MODE,              OemNormalMode,                        MRC_PF_WARM | MRC_PF_S3 | MRC_PF_FAST | MRC_PF_FULL_MRC | MRC_PF_MINI_MRC, MRC_ITERATION_MAX, MRC_DEBUG_TEXT("Normal Operation For Non-Cold Boots")},
+/// @attention: MrcAliasCheck must run before any test modifying the WDB entries to zero for memory scrubbing.
+  {MrcAliasCheck,              MRC_ALIAS_CHECK,              OemAliasCheck,          MRC_PF_COLD                                         | MRC_PF_FULL_MRC | MRC_PF_MINI_MRC, MRC_ITERATION_MAX, MRC_DEBUG_TEXT("MRC Memory alias check")},
+  {MrcHwMemTest,               MRC_CPGC_MEMORY_TEST,         OemMemTest,             MRC_PF_COLD                                         | MRC_PF_FULL_MRC | MRC_PF_MINI_MRC, MRC_ITERATION_MAX, MRC_DEBUG_TEXT("MRC HW Memory testing")},
+  {MrcEccClean,                MRC_ECC_CLEAN_START,          OemHwMemInit,           MRC_PF_COLD                           | MRC_PF_FAST | MRC_PF_FULL_MRC | MRC_PF_MINI_MRC, MRC_ITERATION_MAX, MRC_DEBUG_TEXT("MRC HW Memory Init")},
+  {MrcDone,                    MRC_DONE,                     OemMrcDone,             MRC_PF_COLD | MRC_PF_WARM | MRC_PF_S3 | MRC_PF_FAST | MRC_PF_FULL_MRC | MRC_PF_MINI_MRC, MRC_ITERATION_MAX, MRC_DEBUG_TEXT("MRC done")},
+#ifdef BDAT_SUPPORT
+  {MrcFillRmtStructure,        MRC_FILL_RMT_STRUCTURE,       OemMrcFillRmt,          MRC_PF_COLD                                         | MRC_PF_FULL_MRC | MRC_PF_MINI_MRC, MRC_ITERATION_MAX, MRC_DEBUG_TEXT("MRC Fill RMT Structure")},
+#endif
+};
+
+/**
+  Initializes the memory controller and DIMMs.
+
+  @param[in, out] MrcData - Include all MRC global data.
+
+  @retval mrcSuccess if the initalization suceeded, otherwise an error status indicating the failure.
+**/
+MrcStatus
+MrcStartMemoryConfiguration (
+  IN OUT MrcParameters *const MrcData
+  )
+{
+  const CallTableEntry  *ctptr;
+  const MrcDebug        *Debug;
+  const MrcInput        *Inputs;
+  MrcOutput             *Outputs;
+  U64                   start_time;
+  U64                   finish_time;
+  U32                   ElapsedTime;
+  U32                   TotalTime;
+  U16                   index;
+  U8                    Run;
+  MrcPostCode           post_code;
+  MrcStatus             MrcStatus;
+
+  //
+  // Time to sequence thru the MRC tasks.
+  Inputs  = &MrcData->SysIn.Inputs;
+  Outputs = &MrcData->SysOut.Outputs;
+  Debug   = &Inputs->Debug;
+  Outputs->BootMode = Inputs->BootMode;
+  MrcVersionGet (&Outputs->Version);
+  MrcStatus = mrcFail;
+  post_code = MRC_INITIALIZATION_START;
+  Run       = 1;
+  TotalTime = 0;
+  for (index = 0; Run && (index < (sizeof (CallTable) / sizeof (CallTableEntry))); index++, post_code++) {
+    ctptr = &CallTable[index];
+    //
+    // Output post code to post code I/O port.
+    //
+    MrcOemDebugHook (MrcData, ((ctptr->post_code_ovr == POST_CODE_NO_OVR) ? post_code : ctptr->post_code_ovr));
+    //
+    // Decide if we need to execute the selected MRC task.
+    if ((NULL != ctptr->mrc_task) && (Inputs->Iteration < ctptr->iteration)) {
+      if  (((Inputs->MrcMode == MrcModeFull) && (ctptr->policy_flag & MRC_PF_FULL_MRC))
+        || ((Inputs->MrcMode == MrcModeMini) && (ctptr->policy_flag & MRC_PF_MINI_MRC))) {
+        if   (((Outputs->BootMode == bmS3)   && (ctptr->policy_flag & MRC_PF_S3))
+          ||  ((Outputs->BootMode == bmFast) && (ctptr->policy_flag & MRC_PF_FAST))
+          ||  ((Outputs->BootMode == bmWarm) && (ctptr->policy_flag & MRC_PF_WARM))
+          ||  ((Outputs->BootMode == bmCold) && (ctptr->policy_flag & MRC_PF_COLD))) {
+          if ((ctptr->oem_cmd < OemNumOfCommands) && (mrcSuccess != MrcOemCheckPoint (MrcData, ctptr->oem_cmd, NULL))) {
+            continue;
+          }
+          //
+          // Output debug string to serial output and execute the MRC task.
+          //
+          MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\nMRC task -- %s -- Started.\n", ctptr->String);
+          start_time  = MrcGetCpuTime ();
+          MrcStatus   = ctptr->mrc_task (MrcData);
+          finish_time = MrcGetCpuTime ();
+          MRC_DEBUG_MSG (
+            Debug,
+            MSG_LEVEL_ERROR,
+            "MRC task %s -- %s, Status = %Xh.\n",
+            ctptr->String,
+            (mrcSuccess == MrcStatus) ? "SUCCEEDED" : "FAILED",
+            MrcStatus
+            );
+          if (mrcSuccess != MrcStatus) {
+            Run = 0;  //Stop task execution on failure.
+          }
+
+          ElapsedTime = (U32) (finish_time - start_time);
+          TotalTime += ElapsedTime;
+          MRC_DEBUG_MSG (Debug, MSG_LEVEL_TIME, "MRC timer: Task %s took %u msec.\n", ctptr->String, ElapsedTime);
+        }
+      }
+    }
+  }
+
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_TIME, "MRC timer: Total time to execute tasks = %u msec.\n", TotalTime);
+
+  return MrcStatus;
+}
diff --git a/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Api/MrcStartMemoryConfiguration.h b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Api/MrcStartMemoryConfiguration.h
new file mode 100644
index 0000000..01aa9d0
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Api/MrcStartMemoryConfiguration.h
@@ -0,0 +1,74 @@
+/** @file
+  Starting point for the core memory reference code.
+
+@copyright
+  Copyright (c) 2010 - 2012 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement
+**/
+
+#ifndef __MRC_StartMemoryConfiguration_h__
+#define __MRC_StartMemoryConfiguration_h__
+
+//
+// Include files
+//
+#include "MrcTypes.h"
+#include "MrcApi.h"
+
+typedef U16 MrcPostCode;
+#define POST_CODE_NO_OVR  ((1 << ((sizeof (MrcPostCode) * 8) - 1)) + ((1 << ((sizeof (MrcPostCode) * 8) - 1)) - 1))
+
+typedef enum {
+  MRC_PF_NULL,                ///< All policy flags turned off.
+  MRC_PF_COLD     = (1 << 0), ///< Execute MRC function on cold reset.
+  MRC_PF_FAST     = (1 << 1), ///< Execute MRC function on cold reset when S3 data is present.
+  MRC_PF_WARM     = (1 << 2), ///< Execute MRC function on warm reset.
+  MRC_PF_S3       = (1 << 3), ///< Execute MRC function on S3 exit.
+  MRC_PF_FULL_MRC = (1 << 4), ///< Execute MRC function when in Full MRC mode.
+  MRC_PF_MINI_MRC = (1 << 5), ///< Execute MRC function when in Mini-MRC mode.
+  MRC_PF_UNUSED   = (3 << 6), ///< Unused policy flags.
+  MRC_PF_ALL      = (0xF)     ///< All policy flags turned off.
+} PFSelector;
+
+typedef U8 PolicyFlag;
+
+#pragma pack(push, 1)
+typedef struct {
+  MrcStatus (*mrc_task) (MrcParameters * const MrcData);  ///< Ptr to function to execute, with parameter list.
+  MrcPostCode   post_code_ovr;                            ///< BIOS post code output to the debug port if value <> 0.
+  U32           oem_cmd;                                  ///< OEM function to execute prior to MRC function.
+  PolicyFlag    policy_flag;                              ///< Call table flags
+  MrcIteration  iteration;                                ///< Maximum number of CPU only resets.
+#ifdef MRC_DEBUG_PRINT
+  char          *String;                                  ///< Output string describing this task (potentially output to debug serial port).
+#endif // MRC_DEBUG_PRINT
+} CallTableEntry;
+#pragma pack(pop)
+
+/**
+  Initializes the memory controller and DIMMs.
+
+  @param[in, out] MrcData - Include all MRC global data.
+
+  @retval mrcSuccess if the initalization suceeded, otherwise an error status indicating the failure.
+**/
+extern
+MrcStatus
+MrcStartMemoryConfiguration (
+  IN OUT MrcParameters *const MrcData
+  );
+
+#endif
diff --git a/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/McAddress.h b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/McAddress.h
new file mode 100644
index 0000000..ddd677b
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/McAddress.h
@@ -0,0 +1,131 @@
+/** @file
+  The contents of this file has all the memory controller register addresses
+  and register bit fields for the MRC.
+
+@copyright
+  Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement
+**/
+#ifndef __McAddress_h__
+#define __McAddress_h__
+
+#include "McGdxcbar.h"
+#include "McIoCkeCtl.h"
+#include "McIoClk.h"
+#include "McIoCmd.h"
+#include "McIoComp.h"
+#include "McIoData.h"
+#include "McMain.h"
+#include "McScramble.h"
+#include "Msa.h"
+#include "Pci000.h"
+
+///
+/// The following is a copy of M_PCU_CR_SSKPD_PCU_STRUCT, modified to add in the
+/// definition of the scratch pad bit fields.
+///
+typedef union {
+  struct {
+    U64 OldWM0     : 4;  ///< Bits 3:0
+    U64 WM1        : 8;  ///< Bits 11:4
+    U64 WM2        : 8;  ///< Bits 19:12
+    U64 WM3        : 9;  ///< Bits 28:20
+    U64            : 3;  ///< Bits 31:29
+    U64 WM4        : 9;  ///< Bits 40:32
+    U64            : 15; ///< Bits 55:41
+    U64 NewWM0     : 8;  ///< Bits 63:56
+  } Bits;
+  U64 Data;
+  U32 Data32[2];
+  U16 Data16[4];
+  U8  Data8[8];
+} M_PCU_CR_SSKPD_PCU_STRUCT;
+
+///
+/// Number of microseconds for level 0 old field (0.1us granularity).
+/// 00h 0 us
+/// 01h 0.1 us
+/// Fh 1.5 us
+///
+#define PCU_CR_SSKPD_PCU_OLD_WM0_OFF  (0)
+#define PCU_CR_SSKPD_PCU_OLD_WM0_WID  (4)
+#define PCU_CR_SSKPD_PCU_OLD_WM0_MSK  (0xF)
+#define PCU_CR_SSKPD_PCU_OLD_WM0_MAX  (0xF)
+#define PCU_CR_SSKPD_PCU_OLD_WM0_DEF  (0xF)
+
+///
+/// Number of microseconds for level 0 new field (0.1us granularity).
+/// 00h 0 us
+/// 01h 0.1 us
+/// FFh 25.5 us
+///
+#define PCU_CR_SSKPD_PCU_NEW_WM0_OFF  (56)
+#define PCU_CR_SSKPD_PCU_NEW_WM0_WID  (8)
+#define PCU_CR_SSKPD_PCU_NEW_WM0_MSK  (0xFF)
+#define PCU_CR_SSKPD_PCU_NEW_WM0_MAX  (0xFF)
+#define PCU_CR_SSKPD_PCU_NEW_WM0_DEF  (0x14)
+///
+/// Number of microseconds for level 1 (0.5us granularity).
+/// 00h 0 us
+/// 01h 0.5 us
+/// FFh 127.5 us
+///
+#define PCU_CR_SSKPD_PCU_WM1_OFF  (4)
+#define PCU_CR_SSKPD_PCU_WM1_WID  (8)
+#define PCU_CR_SSKPD_PCU_WM1_MSK  (0xFF)
+#define PCU_CR_SSKPD_PCU_WM1_MAX  (0xFF)
+#define PCU_CR_SSKPD_PCU_WM1_DEF  (4)
+
+///
+/// Number of microseconds for level 2 (0.5us granularity).
+/// 00h 0 us
+/// 01h 0.5 us
+/// FFh 127.5 us
+///
+#define PCU_CR_SSKPD_PCU_WM2_OFF  (12)
+#define PCU_CR_SSKPD_PCU_WM2_WID  (8)
+#define PCU_CR_SSKPD_PCU_WM2_MSK  (0xFF)
+#define PCU_CR_SSKPD_PCU_WM2_MAX  (0xFF)
+#define PCU_CR_SSKPD_PCU_WM2_DEF  (36)
+
+///
+/// Number of microseconds for level 3 (0.5us granularity).
+/// 00h 0 us
+/// 01h 0.5 us
+/// 01FFh 255.5 us
+///
+#define PCU_CR_SSKPD_PCU_WM3_OFF  (20)
+#define PCU_CR_SSKPD_PCU_WM3_WID  (9)
+#define PCU_CR_SSKPD_PCU_WM3_MSK  (0x1FF)
+#define PCU_CR_SSKPD_PCU_WM3_MAX  (0x1FF)
+#define PCU_CR_SSKPD_PCU_WM3_DEF  (90)
+
+///
+/// Number of microseconds for level 4 (0.5us granularity).
+/// 00h 0 us
+/// 01h 0.5 us
+/// 01FFh 255.5 us
+///
+#define PCU_CR_SSKPD_PCU_WM4_OFF  (32)
+#define PCU_CR_SSKPD_PCU_WM4_WID  (9)
+#define PCU_CR_SSKPD_PCU_WM4_MSK  (0x1FF)
+#define PCU_CR_SSKPD_PCU_WM4_MAX  (0x1FF)
+#define PCU_CR_SSKPD_PCU_WM4_DEF  (160)
+
+
+#define NCDECS_CR_GDXCBAR_NCU_MAX (0xFFFFF000)
+
+#endif // __McAddress_h__
diff --git a/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcCommandTraining.h b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcCommandTraining.h
new file mode 100644
index 0000000..c2b9b4a
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcCommandTraining.h
@@ -0,0 +1,302 @@
+/** @file
+  Command training definitions.
+
+@copyright
+  Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved.
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement.
+
+**/
+
+///
+/// Include files
+///
+#ifndef _MrcCommandTraining_h_
+#define _MrcCommandTraining_h_
+
+#include "MrcTypes.h"
+#include "MrcApi.h"
+#include "MrcCommon.h"
+#include "MrcDdr3.h"
+#include "MrcGlobal.h"
+#include "MrcIoControl.h"
+#include "MrcOem.h"
+#include "MrcReadReceiveEnable.h"
+#include "MrcReset.h"
+#include "MrcTimingConfiguration.h"
+
+#define ECT_CLK_START (0)
+#define ECT_CLK_STOP  (128)
+
+#define ECT_CLK_STEP  (2)
+
+#define ECT_CLK_LOOPS (ECT_CLK_STOP / ECT_CLK_STEP)
+
+#define ECT_DQS_START (-32)
+#define ECT_DQS_STOP  (32)
+#define ECT_DQS_STEP  (8)
+#define ECT_MIN_WIDTH (16)
+
+/**
+@brief
+  This function performs early command training.
+  Center CTL-CLK timing to allow subsequent steps to work
+
+  @param[in] MrcData - Include all MRC global data.
+
+  @retval MrcStatus -  mrcSuccess if it succeeded
+**/
+extern
+MrcStatus
+MrcEarlyCommandTraining (
+  IN MrcParameters *const MrcData
+  );
+
+/**
+@brief
+  This function performs Late command training.
+  Center CMD/CTL-CLK timing using complex patterns.
+
+  @param[in] MrcData - Include all MRC global data.
+
+  @retval MrcStatus - If it's a success return mrcSuccess
+**/
+extern
+MrcStatus
+MrcLateCommandTraining (
+  IN MrcParameters *const MrcData
+  );
+
+/**
+@brief
+  Perform Command Voltage Centering.
+
+  @param[in, out] MrcData - Include all MRC global data.
+
+  @retval MrcStatus - if it succeded returns mrcSuccess
+**/
+extern
+MrcStatus
+MrcCmdVoltageCentering (
+  IN OUT MrcParameters *const MrcData
+  );
+
+/**
+@brief
+  Centers Command Timing around a MidPoint
+
+  @param[in] MrcData         - Include all MRC global data.
+  @param[in] Iteration       - Determines which PI to shift
+  @param[in] Ranks           - Valid Rank bit mask
+  @param[in] GroupMask       - which LPDDR groups to work on for CMD/CLK/CKE; not used for DDR3
+  @param[in] MidPoint        - The MidPoint to center around (per channel)
+
+  @retval Nothing
+**/
+extern
+void
+CmdTimingCentering (
+  IN MrcParameters *const MrcData,
+  IN U8                   Iteration,
+  IN U8                   Ranks,
+  IN U8                   GroupMask,
+  IN U8                   MidPoint[MAX_CHANNEL]
+  );
+
+/**
+@brief
+  Use a linear search to find the edges between Low and High
+  if WrapAround = 0: Look for largest passing region between low and high
+  if WrapAround = 1: Look for largest passing region, including wrapping from high to low
+
+  @param[in, out] MrcData     - Include all MRC global data.
+  @param[in]      Iteration   - Determines which PI to shift
+  @param[in]      chBitMask   - Valid Channel bit mask
+  @param[in]      Ranks       - Valid Rank bit mask
+  @param[in]      GroupMask   - which LPDDR groups to work on for CMD/CLK/CKE; not used for DDR3
+  @param[in]      Low         - Low limit
+  @param[in]      High        - High limit
+  @param[in]      WrapAllowed - Determines the search region
+  @param[in]      VrefOffsets - Array of Vref offsets
+  @param[in]      SkipPrint   - Switch to enable or disable debug printing
+  @param[in]      SkipVref    - Skip changing CMD Vref offsets, only run test once at the current Vref.
+
+  @retval MrcStatus -  If it succeeds return mrcSuccess
+**/
+extern
+void
+CmdLinearFindEdges (
+  IN OUT MrcParameters *const MrcData,
+  IN     U8                   Iteration,
+  IN     U8                   chBitMask,
+  IN     U8                   Ranks,
+  IN     U8                   GroupMask,
+  IN     S8                   Low,
+  IN     U8                   High,
+  IN     U8                   WrapAllowed,
+  IN     S8                   *VrefOffsets,
+  IN     BOOL                 SkipPrint,
+  IN     BOOL                 SkipVref
+  );
+
+/**
+@brief
+  Use a binary search to find the edge between Low and High
+  High and Low track passing points
+  if CountUp: Low is a passing point and need to count up to find a failing point
+  if CountDn: High is a passing point and need to count dn to find a failing point
+
+  @param[in]      MrcData     - Include all MRC global data.
+  @param[in]      Iteration   - Determines which PI to shift
+  @param[in]      ChBitMask   - Valid Channel bit mask
+  @param[in]      Ranks       - Valid Rank bit mask
+  @param[in]      GroupMask   - which LPDDR groups to work on for CMD/CLK/CKE; not used for DDR3
+  @param[in, out] Low         - Low limit
+  @param[in, out] High        - High limit
+  @param[in]      CountUp     - The direction to search
+  @param[in]      VrefOffsets - Array of Vref offsets
+
+  @retval Nothing
+**/
+extern
+void
+CmdBinaryFindEdge (
+  IN     MrcParameters *const MrcData,
+  IN     U8                   Iteration,
+  IN     U8                   ChBitMask,
+  IN     U8                   Ranks,
+  IN     U8                   GroupMask,
+  IN OUT U8                   *Low,
+  IN OUT U8                   *High,
+  IN     U8                   CountUp,
+  IN     S8                   *VrefOffsets
+  );
+
+/**
+@brief
+  Shift the CLK/CTL Timing
+  Shift the CMD Timing
+
+  @param[in] MrcData    - Include all MRC global data.
+  @param[in] Channel    - Channel to shift
+  @param[in] Offset     - Offset to shift by
+  @param[in] UpdateHost - Switch to update the host structure
+
+  @retval Nothing
+**/
+extern
+void
+ShiftChannelTiming (
+  IN MrcParameters *const MrcData,
+  IN U8                   Channel,
+  IN S32                  Offset,
+  IN U8                   UpdateHost
+  );
+
+/**
+@brief
+  This function updtes Command Mode register, tXP and Round trip latency
+
+  @param[in, out] MrcData     - Include all MRC global data.
+  @param[in]      Channel     - Channel to perform update to
+  @param[in]      OldN        - Old N Mode value
+  @param[in]      NewN        - New N mode value
+
+  @retval Nothing
+**/
+extern
+void
+UpdateCmdNTiming (
+  IN OUT MrcParameters *const MrcData,
+  IN     U8                   Channel,
+  IN     U8                   OldN,
+  IN     U8                   NewN
+  );
+
+#ifdef ULT_FLAG
+
+typedef struct _CADB_LINE {
+  U32 CaHigh;
+  U32 CaLow;
+  U32 ChipSelect;
+} CADB_LINE;
+
+typedef enum {
+  CaTrainingMode41,     ///< Enter CA training mode using MRW41
+  CaTrainingMode48,     ///< Enter CA training mode using MRW48
+  CaTrainingMode42      ///< Exit CA training mode using MRW42
+} MrcCaTrainingMode;
+
+/**
+@brief
+  Early CA / CS training for LPDDR.
+  Main flow:
+  1. Put DRAMs in CA training mode using MRW41.
+  2. Run CS vs. CLK training.
+  3. Map DQ pins according to the board swizzling.
+  4. Run CA vs. CLK training.
+  5. Select optimal CA timings for each CA bus per rank
+
+  @param[in] MrcData - The MRC global data.
+
+  @retval mrcSuccess if succeeded
+**/
+extern
+MrcStatus
+EarlyCommandTrainingLpddr (
+  IN MrcParameters *const MrcData
+  );
+
+/**
+@brief
+  Early CS / CLK training for LPDDR.
+  Main flow:
+  1. Setup CADB pattern for CS Training.
+  2. Run CS vs. CLK training.
+  3. Select optimal CS and CLK timings
+
+  @param[in] MrcData - The MRC global data.
+
+  @retval mrcSuccess if succeeded
+**/
+extern
+MrcStatus
+EarlyChipSelectTraining (
+  IN MrcParameters *const MrcData
+  );
+
+/**
+@brief
+  Sweep right and left from the current point to find the margins.
+
+  @param[in, out] MrcData     - Include all MRC global data.
+  @param[in]      Iteration   - Determines which PI to shift
+  @param[in]      ChannelMask - Valid Channel bit mask
+  @param[in]      RankMask    - Valid Rank bit mask
+  @param[in]      DebugPrint  - Print debug messages or not
+
+  @retval MrcStatus -  If it succeeds return mrcSuccess
+**/
+void
+CmdLinearFindEdgesLpddr (
+  IN OUT MrcParameters *const MrcData,
+  IN     U8                   Iteration,
+  IN     U8                   ChannelMask,
+  IN     U8                   RankMask,
+  IN     BOOL                 DebugPrint
+  );
+
+#endif // ULT_FLAG
+#endif // _MrcCommandTraining_h_
diff --git a/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcCommon.h b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcCommon.h
new file mode 100644
index 0000000..718c066
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcCommon.h
@@ -0,0 +1,1836 @@
+/** @file
+  This file include all the MRC common data.
+
+@copyright
+  Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement
+**/
+#ifndef _MrcCommon_h_
+#define _MrcCommon_h_
+
+#include "MrcTypes.h"
+#include "MrcApi.h"
+#include "MrcIoControl.h"
+#include "McAddress.h"
+#include "MrcDdr3.h"
+#include "MrcReset.h"
+#include "MrcOem.h"
+#include "MrcOemPlatform.h"
+
+
+///
+/// Convert rank to dimm number
+///
+#ifndef RANK_TO_DIMM_NUMBER
+#define RANK_TO_DIMM_NUMBER(Rank) (Rank / 2)
+#endif
+
+///
+/// Convert rank to real rank number inside dimm
+///
+#ifndef RANK_TO_RANK_NUMBER_IN_DIMM
+#define RANK_TO_RANK_NUMBER_IN_DIMM(Rank) ((Rank % 2) + 1)
+#endif
+
+///
+/// Convert rank and dimm to channel rank number
+///
+#ifndef GET_RANK_NUMBER
+#define GET_RANK_NUMBER(Dimm, Rank) ((Dimm * 2) + Rank)
+#endif
+
+///
+/// Bit operation commands
+///
+#ifndef MRC_MASK
+#define MRC_MASK(offset, width) (((1 << width) - 1) << (offset))
+#endif
+
+#ifndef MRC_MASK_NOT
+#define MRC_MASK_NOT(offset, width) (~(MRC_MASK (offset, width)))
+#endif
+
+#ifndef MRC_CR_UPDATE
+#define MRC_CR_UPDATE(Register, Offset, Width, Value) \
+        (((Register) & MRC_MASK_NOT (Offset, Width)) | ((Value) << (Offset)))
+#endif
+
+#ifndef MRC_CR_DUMP
+#define MRC_CR_DUMP(Register, offset, Width)\
+        (((Register) & (MRC_MASK(offset, Width))) >> offset)
+#endif
+
+#define BER_TARGET              4
+#define BER_LOG_TARGET          7             ///< MRC_Log8(BER_TARGET) = 7
+#define BER_ERROR_MASK          0xFFFF00FF
+
+#define MRC_ASSERT(cond, DEBUG, ...)   \
+  if (!(cond)) { \
+    MRC_DEBUG_MSG (DEBUG, MSG_LEVEL_ERROR, __VA_ARGS__); \
+    MRC_DEADLOOP (); \
+  }
+
+///
+/// Cache line size
+///
+#define WDB_CACHE_LINE_SIZE (8)
+
+///
+/// CADB Entries
+///
+#define MRC_NUM_CADB_ENTRIES (8)
+
+///
+/// Number of WDB Mux
+///
+#define MRC_WDB_NUM_MUX_SEEDS (3)
+
+///
+/// Dimm Mode register selection
+///
+typedef enum {
+  mrMR0 = 0,
+  mrMR1,
+  mrMR2,
+  mrMR3,
+  mrMR11 = 11
+} MrcModeRegister;
+
+typedef enum {
+  dDIMM0= 0,
+  dDIMM1
+} MrcDimmType;
+
+typedef enum {
+  cCHANNEL0 = 0,
+  cCHANNEL1
+} MrcChannelType;
+
+typedef enum {
+  rRank0    = 0,
+  rRank1,
+  rRank2,
+  rRank3
+} MrcRank;
+
+typedef enum {
+  ssOne     = 0,
+  ssTwo,
+  ssThree,
+  ssFour
+} TSubSequencesNumber;
+
+///
+/// Define ECC mode.
+///
+typedef enum {
+  emNoEcc,
+  emEccIoActive,
+  emEccLogicActive,
+  emBothActive
+} TEccModes;
+
+///
+/// Raw card list
+///
+typedef enum {
+  rcA,
+  rcB,
+  rcC,
+  rcD,
+  rcE,
+  rcF,
+  rcG,
+  rcH,
+} TRawCard;
+
+///
+/// Reut Addressing Parameters
+///
+typedef enum {
+  MrcReutFieldRank,
+  MrcReutFieldBank,
+  MrcReutFieldRow,
+  MrcReutFieldCol,
+  MrcReutFieldMax   ///< This must be the last entry in the enum.
+} MrcReutField;
+
+typedef struct {
+  U16 Start[MrcReutFieldMax];   ///< (4, uint16)    // Rank, Bank, Row, Col
+  U16 Stop[MrcReutFieldMax];    ///< (4, uint16)    // Rank, Bank, Row, Col
+  U8  Order[MrcReutFieldMax];   ///< [4, uint8)     // Rank, Bank, Row, Col
+  U32 IncRate[MrcReutFieldMax]; ///< (4, unit32)    // Rank, Bank, Row, Col
+  U16 IncVal[MrcReutFieldMax];  ///< (4, unit16)    // Rank, Bank, Row, Col
+} MRC_REUTAddress;
+
+typedef struct {
+  U16 IncRate;                    ///< How quickly the WDB walks through cachelines (uint16)
+  U32 Start;                      ///< Starting pointer in WDB
+  U32 Stop;                       ///< Stopping pointer in WDB
+  U8  DQPat;                      ///< [0:BasicVA, 1:SegmentWDB, 2:CADB, 3:TurnAround,
+                                  ///< 4: LMNVa, 5: TurnAroundWR, 6: TurnAroundODT
+                                  ///< 7: CADBCol, 8: CADBRow]
+} MRC_WDBPattern;
+
+typedef enum {
+  BasicVA = 0,                    ///< Use 2 LFSR VicAggressor pattern with rotation of 10 bits
+  SegmentWDB,                     ///< Use 2 LFSR VA pattern 10 bit rotation + 3 LFSR VA pattern 6 bit rotation
+  CADB,                           ///< Do CADB on command/address bus and LMN VA on DQ (power supply noise)
+  TurnAround,
+  LMNVa,                          ///< Use (LMN aggressor + LFSR Victim) with rotation of 10 bits
+  TurnAroundWR,                   ///< Run 8 tests, one for each subsequence with RankIncRate = 1/2/2/2/2/2/2/1
+  TurnAroundODT,                  ///< Run 4 tests, one for each subsequence with RankIncRate = 1/2/1/2
+  CADBCol,
+  CADBRow,
+  RdRdTA,                         ///< Run 2 tests, one with Trdrd=4 and one with Trdrd=5
+  RdRdTA_All                      ///< Run 8 tests, Covering tRDRD_sr 4,5,6,7 and tRDRD_dr = Min,+1,+2,+3
+} MrcDqPat;
+
+typedef enum {
+  NSOE = 0,                       ///< Never Stop On Any Error
+  NTHSOE,                         ///< Stop on the Nth Any Lane Error
+  ABGSOE,                         ///< Stop on All Byte Groups Error
+  ALSOE                           ///< Stop on All Lanes Error
+} TStopOnError;
+
+typedef enum {
+  MrcRegFileRank,                 ///< Used if ChangeMargin is being called within a Rank loop and the Parameters are Rank based.
+  MrcRegFileStart,                ///< Used when changing parameters before the test.
+  MrcRegFileCurrent,              ///< Used when changing parameters after the test.
+  MrcRegFileMax                   ///< This must be the last in the list
+} MrcRegFile;
+
+///
+/// CADB commands
+///
+#define MRS_CMD                             0
+#define REF_CMD                             1
+#define PRE_CMD                             2
+#define ACT_CMD                             3
+#define WR_CMD                              4
+#define RD_CMD                              5
+#define ZQ_CMD                              6
+#define NOP_CMD                             7
+
+///
+/// REUT Init modes
+///
+#define Idle_Mode                           0
+#define REUT_Testing_Mode                   1
+#define MRS_Mode                            2
+#define NOP_Mode                            3  ///< Normal Operation Mode
+
+///
+/// REUT CmdPattern
+///
+#define PatWrRd                             0
+#define PatWr                               1
+#define PatRd                               2
+#define PatRdWrTA                           3
+#define PatWrRdTA                           4
+#define PatODTTA                            5
+#define DimmTest                            6
+#define PatCADBCol                          7
+#define PatCADBRow                          8
+
+///
+/// REUT Mux Control
+///
+#define LMNMode                             0
+#define BTBUFFER                            1
+#define LFSRMode                            2
+
+///
+/// REUT Subsequence types
+///
+#define BRd                                 0
+#define BWr                                 1
+#define BRdWr                               2
+#define BWrRd                               3
+#define ORd                                 4
+#define OWr                                 5
+
+///
+/// WDB Patterns
+///
+#define BASIC_VA_PATTERN_SPRED_8  0x01010101
+
+///
+/// DQ time centering param: read or write
+///
+///
+/// Margin params
+///
+
+/*
+ 1D Margin Types:
+  RcvEn:  Shifts just RcvEn.  Only side effect is it may eat into read dq-dqs for first bit of burst
+  RdT:    Shifts read DQS timing, changing where DQ is sampled
+  WrT:    Shifts write DQ timing, margining DQ-DQS timing
+  WrDqsT: Shifts write DQS timing, margining both DQ-DQS and DQS-CLK timing
+  RdV:    Shifts read Vref voltage for DQ only
+  WrV:    Shifts write Vref voltage for DQ only
+  WrLevel: Shifts write DQ and DQS timing, margining only DQS-CLK timing
+  WrTBit:  Shifts write DQ per bit timing.
+  RdTBit:  Shifts read DQ per bit timing.
+  RdVBit:  Shifts read DQ per bit voltage.
+
+ 2D Margin Types (Voltage, Time)
+  RdFan2:  Margins both RdV and RdT at { (off, -2/3*off),  (off, 2/3*off) }
+  WrFan2:  Margins both WrV and WrT at { (off, -2/3*off),  (off, 2/3*off) }
+  RdFan3:  argins both RdV and RdT at { (off, -2/3*off),  (5/4*off, 0),  (off, 2/3*off)  }
+  WrFan3:  Margins both WrV and WrT at { (off, -2/3*off),  (5/4*off, 0),  (off, 2/3*off)  }
+
+  param = {0:RcvEn, 1:RdT, 2:WrT, 3: WrDqsT, 4:RdV, 5:WrV, 6:WrLevel,
+          8:WrTBit, 9:RdTBit, 10:RdVBit,
+          16:RdFan2, 17:WrFan2, 32:RdFan3, 32:WrFan3}
+*/
+
+ typedef enum {
+  RcvEna = 0,
+  RdT,
+  WrT,
+  WrDqsT,
+  RdV,
+  WrV,
+  WrLevel,
+  WrTBox,
+  WrTBit,
+  RdTBit,
+  RdVBit,  ///< 10
+  RcvEnaX,
+  CmdT,
+  CmdV,
+  RdFan2 = 16,
+  WrFan2 = 17,
+  RdFan3 = 32,
+  WrFan3 = 33,
+  MarginTypeMax
+} MRC_MarginTypes;
+
+typedef enum {
+  OptWrDS = 0,
+  OptRdOdt,
+  OptSComp,
+  OptTComp,
+  OptTxEq,
+  OptRxEq,
+  OptRxBias,
+  OptDimmOdt,
+  OptDimmOdtWr,
+  OptDimmRon,
+  OptDefault
+} TOptParamOffset;
+
+typedef enum {
+  drrd2rd = 0,
+  ddrd2rd,
+  drwr2wr,
+  ddwr2wr,
+  drrd2wr,
+  ddrd2wr,
+  drwr2rd,
+  ddwr2rd,
+  rdodtd,
+  wrodtd,
+  mcodts,
+  mcodtd,
+  rtl,
+  srrd2rd,
+  srrd2wr
+} TOptParamTAT;
+
+///
+/// Self refresh idle timer value
+///
+#define SELF_REFRESH_IDLE_COUNT (0x200)
+
+#define RXF_SELECT_RC_100  (6)
+#define RXF_SELECT_RC_133  (4)
+#define RXF_SELECT_MIN     (0)
+#define RXF_SELECT_MAX     (4)
+#define RXF_SELECT_MAX_ULT (2)
+
+#ifdef MRC_DEBUG_PRINT
+extern const char CcdString[];
+#endif
+
+///
+/// MRC common functions
+///
+
+/**
+  Return the rank mask in channel if rank exist exist.
+
+  @param[in] MrcData - Pointer to MRC global data.
+  @param[in] Channel - Channel to work on.
+  @param[in] Rank    - Rank to check.
+
+  @retval Bit mask of Rank requested if the Rank exists in the system.
+**/
+extern
+U8
+MrcRankInChannelExist (
+  IN MrcParameters *const MrcData,
+  IN const U8             Rank,
+  IN const U8             Channel
+  );
+
+/**
+  Return the number of ranks in specific dimm.
+
+  @param[in] MrcData - Pointer to MRC global data.
+  @param[in] Channel - Channel to work on.
+  @param[in] Dimm    - Dimm in channel to return.
+
+  @retval The number of ranks in the dimm.
+**/
+extern
+U8
+MrcGetRankInDimm (
+  IN MrcParameters *const MrcData,
+  IN const U8             Dimm,
+  IN const U8             Channel
+  );
+
+/**
+  Returns whether Channel is or is not present.
+
+  @param[in] Outputs - Pointer to MRC global Output data.
+  @param[in] Channel - Channel to test.
+
+  @retval TRUE  - if there is at least one enabled DIMM in the channel.
+  @retval FALSE - if there are no enabled DIMMs in the channel.
+**/
+extern
+BOOL
+MrcChannelExist (
+  IN const MrcOutput *const Outputs,
+  IN const U8               Channel
+  );
+
+/**
+  This function disable channel parameters.
+  After this function the MRC don't use with the channel.
+
+  @param[in] MrcData           - Include all MRC global data.
+  @param[in] ChannelToDisable  - Channel to disable.
+  @param[in] SkipDimmCapacity  - Switch to skip setting the DimmCapacity to 0 for the dimms in the channel disabled.
+
+  @retval Nothing
+**/
+extern
+void
+MrcChannelDisable (
+  IN MrcParameters *const MrcData,
+  IN const U8             ChannelToDisable,
+  IN const U8             SkipDimmCapacity
+  );
+
+/**
+  Convert the given frequency and reference clock to a clock ratio.
+
+  @param[in] MrcData   - Pointer to MRC global data.
+  @param[in] Frequency - The memory frequency.
+  @param[in] RefClk    - The memory reference clock.
+  @param[in] BClk      - The base system reference clock.
+
+  @retval Returns the memory clock ratio.
+**/
+extern
+MrcClockRatio
+MrcFrequencyToRatio (
+  IN MrcParameters *const  MrcData,
+  IN const MrcFrequency    Frequency,
+  IN const MrcRefClkSelect RefClk,
+  IN const MrcBClkRef      BClk
+  );
+
+/**
+  @brief
+  Convert the given ratio and reference clocks to a memory frequency.
+
+  @param[in] MrcData - Pointer to MRC global data.
+  @param[in] Ratio   - The memory ratio.
+  @param[in] RefClk  - The memory reference clock.
+  @param[in] BClk    - The base system reference clock.
+
+  @retval Returns the memory frequency.
+**/
+extern
+MrcFrequency
+MrcRatioToFrequency (
+  IN MrcParameters *const  MrcData,
+  IN const MrcClockRatio   Ratio,
+  IN const MrcRefClkSelect RefClk,
+  IN const MrcBClkRef      BClk
+  );
+
+/**
+  Convert the given ratio and reference clocks to a memory clock. 
+
+  @param[in] Ratio  - The memory ratio.
+  @param[in] RefClk - The memory reference clock.
+  @param[in] BClk   - The base system reference clock.
+
+  @retval Returns the memory clock in femtoseconds.
+**/
+extern
+U32
+MrcRatioToClock (
+  IN const MrcClockRatio   Ratio,
+  IN const MrcRefClkSelect RefClk,
+  IN const MrcBClkRef      BClk
+);
+
+/**
+  This function return the DIMM number according to the rank number.
+
+  @param[in] Rank - The requested rank.
+
+  @retval The DIMM number.
+**/
+extern
+U8
+MrcGetDimmFromRank (
+  IN const U8 Rank
+  );
+
+/**
+  This function sets the memory frequency.
+
+  @param[in] MrcData - Include all MRC global data.
+
+  @retval mrcSuccess on success, mrcFrequencyError on error.
+**/
+extern
+MrcStatus
+McFrequencySet (
+  IN MrcParameters * const MrcData
+  );
+
+/**
+  Returns the extrapolated margin to a fixed # of errors (logT)
+  vrefpass is 10x the first passing margin (with no errors) (10x used for int math)
+  Errors at vrefpass/10+1 = log1
+  Errors at vrefpass/10+2 = logT
+
+  @param[in]      vrefpass      - 10x the first pass margin (w/no errors) (10x used for int match)
+  @param[in]      errLog_1      - Errors at vrefpass/10+1
+  @param[in]      errLog_2      - Errors at vrefpass/10+2
+  @param[in]      errLog_Target - Error target determines extrapolation vs interpolation
+  @param[in, out] *berStats     - Used to track interpolation vs extrapolation or if the slope is non-monotonic.
+                                  NOTE: target would be Interpolation only
+
+  @retval Interpolated/Extrapolated vref with the scale increased by 10.
+**/
+extern
+U32
+interpolateVref (
+  IN     U32  vrefpass,
+  IN     U32  errLog_1,
+  IN     U32  errLog_2,
+  IN     U32  errLog_Target,
+  IN OUT U32  *berStats
+  );
+
+/**
+  This function swaps a subfield, within a 32 bit integer value with the specified value.
+
+  @param[in] CurrentValue - 32 bit input value.
+  @param[in] NewValue     - 32 bit New value.
+  @param[in] Start        - Subfield start bit.
+  @param[in] Length       - Subfield length in bits/
+
+  @retval The updated 32 bit value.
+**/
+extern
+U32
+MrcBitSwap (
+  IN U32       CurrentValue,
+  IN const U32 NewValue,
+  IN const U8  Start,
+  IN const U8  Length
+  );
+
+/**
+  This function returns the maximim Rx margin for a given Channel, Rank(s), and byte.
+
+  @param[in] MrcData   - Pointer to MRC global data.
+  @param[in] Channel   - Channel to calculate max Rx margin.
+  @param[in] RankRx    - Rank index.  0xFF causes all ranks to be considered.
+  @param[in] byte      - Byte to check.
+  @param[in] sign      - Sign of the margins (0 - negative/min, 1 - positive/max).
+  @param[in] MaxMargin - Current max margin value.
+
+  @retval The max Rx margin, either MaxMargin or value from stored margins.
+**/
+extern
+U8
+MrcCalcMaxRxMargin (
+  IN MrcParameters  *const MrcData,
+  IN const U8              Channel,
+  IN const U8              RankRx,
+  IN const U8              byte,
+  IN const U8              sign,
+  IN U8                    MaxMargin
+  );
+
+/**
+  This function determines if a bit lane[0-7] has seen a pass and a fail in each byte for all channels populated.
+
+  @param[in] MrcData   - Pointer to MRC global data.
+  @param[in] chBitmask - Bit mask of channels to consider.
+  @param[in] OnePass   - Array of Bit masks marking DQ lanes has had a passing value.
+  @param[in] OneFail   - Array of Bit masks marking DQ lanes has had a failing value.
+
+  @retval The AND result of each Channel/byte for OnePass and OneFail.
+**/
+extern
+U8
+MrcAndBytes (
+  IN MrcParameters *const MrcData,
+  IN const U8             chBitmask,
+  IN U8                   OnePass[MAX_CHANNEL][MAX_SDRAM_IN_DIMM],
+  IN U8                   OneFail[MAX_CHANNEL][MAX_SDRAM_IN_DIMM]
+  );
+
+/**
+  This function Finds the margin for all channels/all bits. The margin sweep is a parameterized
+  Assume REUT test has already been fully setup to run
+  This will unscale the results such that future tests start at the correct point
+  Uses ChangeMargin function to handle a variety cases (Timing, Voltage, Fan, etc.)
+
+  @param[in]     MrcData    - Include all MRC global data.
+  @param[in]     chBitMask  - Channel BIT mask for Channel(s) to work on
+  @param[in]     Rank       - Rank to work on
+  @param[in,out] marginbit  - used as the return data ( real margin measurement, no 10x)
+                              marginbit[ch,byte,bit,sign] = abs(Margin)
+                              Note: If param == RdTBit/RdVBit/WrVBit, marginbit is also the starting point
+  @param[in,out] marginbyte - provides the starting point on a per byte basis (still 10x)
+  @param[in]     param      - defines the margin type
+  @param[in]     mode       - allows for different types of modes for margining
+                              {Bit0: PhLock (keep all bytes within in ch in phase),
+                               Bit1: Ch2Ch Data out of phase (LFSR seed)
+                               Bits 15:2: Reserved}
+  @param[in]     MaxMargin  - Default Maximum margin
+
+  @retval mrcSuccess if successful, otherwise it returns an error status.
+**/
+extern
+MrcStatus
+MrcGetMarginBit (
+  IN     MrcParameters *const MrcData,
+  IN     U8                   chBitMask,
+  IN     U8                   Rank,
+  IN OUT U32                  marginbit[MAX_CHANNEL][MAX_SDRAM_IN_DIMM][MAX_BITS][MAX_EDGES],
+  IN OUT U32                  marginbyte[MAX_CHANNEL][MAX_SDRAM_IN_DIMM][MAX_EDGES],
+  IN     U8                   param,
+  IN     U16                  mode,
+  IN     U8                   MaxMargin
+  );
+
+/**
+  Assume REUT test has already been fully setup to run
+  Finds the margin for all channels/all bytes
+  The margin sweep is parameterized
+  Uses ChangeMargin function to handle a variety of cases (Timing, Voltage, Fan, etc.)
+  mode allows for different types of modes for margining:
+    mode is {Bit0: PhLock (keep all bytes within in ch in phase),
+             Bit1: Ch2Ch Data out of phase (LFSR seed), Bit 15:2: Reserved}
+  marginByte is used as the starting point for the search (10x the actual margin)
+  marginch returns the results (10x the actual margin)
+  Interior: Search inside marginch limits, enabling multiple calls with different setups
+  To reduce repeatibility noise, the returned margins is actually a BER extrapolation
+
+  @param[in]     MrcData    - The global MrcData
+  @param[in,out] marginByte - Data structure with the latest margin results
+  @param[in]     chBitmask  - Bit mask of present channels
+  @param[in]     Rank       - Rank to change margins for
+  @param[in]     RankRx     - Ranks for Rx margin
+  @param[in]     param      - parameter to get margins for
+  @param[in]     mode       - allows for different types of modes for margining:
+  @param[in]     BMap       - Byte mapping to configure error counter control register
+  @param[in]     EnBER      - Enable BER extrapolation calculations
+  @param[in]     MaxMargin  - Max Margin allowed for the parameter
+  @param[in]     Interior   - Search inside marginch limits, enabling multiple calls with different setups
+  @param[in,out] BERStats   - Bit Error Rate Statistics.
+
+  @retval mrcSuccess if successful, otherwise returns an error status.
+**/
+extern
+MrcStatus
+MrcGetBERMarginByte (
+  IN     MrcParameters * const MrcData,
+  IN OUT U32             marginByte[MAX_RESULT_TYPE][MAX_RANK_IN_CHANNEL][MAX_CHANNEL][MAX_SDRAM_IN_DIMM][MAX_EDGES],
+  IN     U8              chBitmask,
+  IN     U8              Rank,
+  IN     U8              RankRx,
+  IN     U8              param,
+  IN     U16             mode,
+  IN     U8              *BMap,
+  IN     U8              EnBER,
+  IN     U8              MaxMargin,
+  IN     U8              Interior,
+  IN OUT U32             *BERStats
+  );
+
+/**
+  Assume REUT test has already been fully setup to run
+  Finds the margin for all channels/all bytes
+  The margin sweep is parameterized
+  Uses ChangeMargin function to handle a variety of cases (Timing, Voltage, Fan, etc.)
+  mode allows for different types of modes for margining:
+  mode is {Bit0: PhLock (keep all bytes within in ch in phase),
+  Bit1: Ch2Ch Data out of phase (LFSR seed), Bit 15:2: Reserved}
+  marginCh is used as the starting point for the search (10x the actual margin)
+  marginch returns the results (10x the actual margin)
+  Interior: Search inside marginch limits, enabling multiple calls with different setups
+  To reduce repeatibility noise, the returned margins is actually a BER extrapolation
+
+  @param[in]     MrcData   - The global MrcData
+  @param[in,out] marginCh  - Data structure with the latest margin results
+  @param[in]     chBitmask - Bit mask of present channels
+  @param[in]     RankRx    - Ranks for Rx margin
+  @param[in]     Rank      - Rank to change margins for
+  @param[in]     param     - parameter to get margins for
+  @param[in]     mode      - allows for different types of modes for margining:
+  @param[in]     EnBER     - Enable BER extrapolation calculations
+  @param[in]     MaxMargin - Max Margin allowed for the parameter
+  @param[in]     Interior  - Search inside marginch limits, enabling multiple calls with different setups
+  @param[in,out] BERStats  - Bit Error Rate Statistics.
+
+  @retval mrcSuccess if successful, otherwise returns an error status.
+**/
+extern
+MrcStatus
+MrcGetBERMarginCh (
+  IN     MrcParameters   *MrcData,
+  IN     U32             marginCh[MAX_RESULT_TYPE][MAX_RANK_IN_CHANNEL][MAX_CHANNEL][MAX_SDRAM_IN_DIMM][MAX_EDGES],
+  IN OUT U8              chBitmask,
+  IN     U8              RankRx,
+  IN     U8              Rank,
+  IN     U8              param,
+  IN     U16             mode,
+  IN     U8              EnBER,
+  IN     U8              MaxMargin,
+  IN     U8              Interior,
+  IN OUT U32             *BERStats
+  );
+
+/**
+  This function shifts a 32 bit int either positive or negative
+
+  @param[in] Value       - Input value to be shifted
+  @param[in] ShiftAmount - Number of bits places to be shifted.
+
+  @retval 0 if ShiftAmount exceeds +/- 31.  Otherwise the updated 32 bit value.
+**/
+extern
+U32
+MrcBitShift (
+  IN const U32 Value,
+  IN const S8  ShiftAmount
+  );
+
+/**
+  This function Sign extends OldMSB to NewMSB Bits (Eg: Bit 6 to Bit 7)
+
+  @param[in] CurrentValue - Input value to be shifted
+  @param[in] OldMSB       - The original most significant Bit
+  @param[in] NewMSB       - The new most significant bit.
+
+  @retval The updated 8 bit value.
+**/
+extern
+U8
+MrcSE (
+  IN U8        CurrentValue,
+  IN const U8  OldMSB,
+  IN const U8  NewMSB
+  );
+
+/**
+  This function calculates the Log base 2 of the value to a maximum of Bits
+
+  @param[in] Value - Input value
+
+  @retval Returns the log base 2 of input value
+**/
+extern
+U8
+MrcLog2 (
+  IN const U32 Value
+  );
+
+/**
+  ***** Has Buffer Overflow for 68-71, 544-575, 4352-4607, ... ****
+  This function calculates the Log base 8 of the Input parameter using integers
+
+  @param[in] Value - Input value
+
+  @retval Returns 10x the log base 8 of input Value
+**/
+extern
+U32
+MrcLog8 (
+  IN U32 Value
+  );
+
+/**
+  This function Sorts Arr from largest to smallest
+
+  @param[in,out] Arr     - Array to be sorted
+  @param[in]     Channel - Channel to sort.
+  @param[in]     lenArr  - Length of the array
+
+  @retval Nothing
+**/
+extern
+void
+MrcBsortPerChannel (
+  IN OUT U32      Arr[MAX_CHANNEL][4],
+  IN     const U8 Channel,
+  IN     const U8 lenArr
+  );
+
+/**
+  This function Sorts Arr from largest to smallest
+
+  @param[in,out] Arr    - Array to be sort
+  @param[in]     lenArr - Lenght of the array
+
+  @retval Nothing
+**/
+extern
+void
+MrcBsort (
+  IN OUT U32 *const Arr,
+  IN     const U8   lenArr
+  );
+
+/**
+  This function calculates the Natural Log of the Input parameter using integers
+
+  @param[in] Input - 100 times a number to get the Natural log from.
+                      Max Input Number is 40,000 (without 100x)
+
+  @retval 100 times the actual result. Accurate within +/- 2
+**/
+extern
+U32
+MrcNaturalLog (
+  IN U32 Input
+  );
+
+/**
+  This function calculates the number of bits set to 1 in a 32-bit value.
+
+  @param[in] Input - The value to work on.
+
+  @retval The number of bits set to 1 in Input.
+**/
+extern
+U8
+MrcCountBitsEqOne (
+  IN U32 Input
+  );
+
+/**
+  This function calculates e to the power of of the Input parameter using integers.
+
+  @param[in] Input - 100 times a number to elevate e to.
+
+  @retval 100 times the actual result. Accurate within +/- 2.
+**/
+extern
+U32
+Mrceexp (
+  IN U32 Input
+  );
+
+/**
+  This function writes a 32 bit register.
+
+  @param[in] MrcData - Include all MRC global data.
+  @param[in] Offset  - Offset of register from MchBar Base Address.
+  @param[in] Value   - Value to write.
+
+  @retval Nothing
+**/
+extern
+void
+MrcWriteCrMulticast (
+  IN MrcParameters *const MrcData,
+  IN const U32            Offset,
+  IN const U32            Value
+  );
+
+/**
+  This function writes a 64 bit register.
+
+  @param[in] MrcData - Include all MRC global data.
+  @param[in] Offset  - Offset of register from MchBar Base Address.
+  @param[in] Value   - Value to write.
+
+  @retval Nothing
+**/
+extern
+void
+MrcWriteCR64 (
+  IN MrcParameters *const MrcData,
+  IN const U32            Offset,
+  IN const U64            Value
+  );
+
+/**
+  This function writes a 32 bit register.
+
+  @param[in] MrcData - Include all MRC global data.
+  @param[in] Offset  - Offset of register from MchBar Base Address.
+  @param[in] Value   - Value to write.
+
+  @retval Nothing
+**/
+extern
+void
+MrcWriteCR (
+  IN MrcParameters *const MrcData,
+  IN const U32            Offset,
+  IN const U32            Value
+  );
+
+/**
+  This function writes a 8 bit register.
+
+  @param[in] MrcData - Include all MRC global data.
+  @param[in] Offset  - Offset of register from MchBar Base Address.
+  @param[in] Value   - The value to write.
+
+  @retval Nothing
+**/
+extern
+void
+MrcWriteCR8 (
+  IN MrcParameters*const MrcData,
+  IN const U32            Offset,
+  IN const U8             Value
+  );
+
+/**
+  This function reads a 64 bit register.
+
+  @param[in] MrcData - Include all MRC global data.
+  @param[in] Offset  - Offset of register from MchBar Base Address.
+
+  @retval Value read from the register.
+**/
+extern
+U64
+MrcReadCR64 (
+    IN MrcParameters *const MrcData,
+    IN const U32            Offset
+  );
+
+/**
+  This function reads a 32 bit register.
+
+  @param[in] MrcData - Include all MRC global data.
+  @param[in] Offset  - Offset of register from MchBar Base Address.
+
+  @retval Value read from the register
+**/
+extern
+U32
+MrcReadCR (
+  IN MrcParameters *const MrcData,
+  IN const U32            Offset
+  );
+
+/**
+  This function blocks the CPU for the duration specified in HPET Delay time.
+
+  @param[in] MrcData   - Include all MRC global data.
+  @param[in] DelayHPET - time to wait in 69.841279ns
+
+  @retval Nothing
+**/
+extern
+void
+MrcWait (
+  IN MrcParameters *const MrcData,
+  IN U32                  DelayHPET
+  );
+
+/**
+  This function forces an RCOMP.
+
+  @param[in] MrcData - Include all MRC global data.
+
+  @retval Nothing
+**/
+extern
+void
+ForceRcomp (
+  IN MrcParameters * const MrcData
+  );
+
+/**
+  This function sets the self refresh idle timer and enables it.
+
+  @param[in] MrcData - Include all MRC global data.
+
+  @retval Nothing
+**/
+extern
+void
+EnterSR (
+  IN MrcParameters * const MrcData
+  );
+
+/**
+  This function sets the self refresh idle timer and disables it.
+
+  @param[in] MrcData - Include all MRC global data.
+
+  @retval Nothing
+**/
+extern
+void
+ExitSR(
+  IN MrcParameters * const MrcData
+  );
+
+/**
+  This function programs the WDB.
+
+  @param[in] MrcData - Include all MRC global data.
+
+  @retval Nothing
+**/
+extern
+void
+SetupWDB(
+  IN MrcParameters * const MrcData
+  );
+
+/*
+  This function will program all present channels with the 3 seeds passed in.
+
+  @param[in]  MrcData - Global MRC data structure
+  @param[in]  seeds   - Array of 3 seeds programmed into PAT_WDB_CL_MUX_PB_RD/WR
+
+  @retval - Nothing
+*/
+extern
+void
+MrcProgramLFSR (
+  IN MrcParameters *const MrcData,
+  IN U32 const            seeds[MRC_WDB_NUM_MUX_SEEDS]
+  );
+
+/**
+  This function Write 1 cacheline worth of data to the WDB
+
+  @param[in] MrcData  - Include all MRC global data.
+  @param[in] Patterns - Array of bytes.  Each bytes represents 8 chunks of the cachelines for 1 lane.
+                         Each entry in Patterns represents a different cacheline for a different lane.
+  @param[in] PMask    - Array of len Spread uint8.  Maps the patterns to the actual DQ lanes.
+                         DQ[0] = Patterns[PMask[0]], ... DQ[Spread-1] = Patterns[PMask[Spread-1]]
+                         DQ[Spread] = DQ[0], ... DQ[2*Spread-1] = DQ[Spread-1]
+  @param[in] Start    - Starting entry in the WDB.
+
+  @retval Nothing
+**/
+extern
+void
+WriteWDBFixedPattern (
+  IN MrcParameters *const MrcData,
+  IN U8 *const            Patterns,
+  IN U8 *const            PMask,
+  IN const U8             Spread,
+  IN const U16            Start
+  );
+
+/**
+  This rotine performs the following steps:
+    Step 0: Iterate through all VicRots
+    Step 1: Create a compressed vector for a given 32 byte cacheline
+            Each byte has a value of LFSR0=AA/LFSR1=CC/LFSR2=F0
+    Step 2: Expand compressed vector into chunks and 32 bit segments
+
+  @param[in] MrcData - Include all MRC global data.
+  @param[in] vmask   - 32 bit victim mask.  1 indicates this bit should use LFSR0
+  @param[in] amask   - 32 bit aggressor mask. 0/1 indicates this bit should use LFSR1/2
+  @param[in] VicRot  - Number of times to circular rotate vmask/amask
+  @param[in] Start   - Starting entry in the WDB
+
+  @retval Nothing
+**/
+extern
+void
+WriteWDBVAPattern (
+  IN MrcParameters *const MrcData,
+  IN U32                  amask,
+  IN U32                  vmask,
+  IN const U8             VicRot,
+  IN const U16            Start
+  );
+
+/**
+  Write VA pattern in CADB
+  Use basic VA pattern for CADB with 2 LFSRs. Rotation is manual
+  Bit Order is  [CKE[3:0], ODT[3:0], CMD[2:0], CS[3:0], BA[2:0], MA[15:0]]
+  [59:56]  [51:48]  [42:40] [35:32]  [26:24]  [15:0]
+
+  NOTE: CKE, ODT and CS are not used in functional mode and are ignored
+
+  @param[in] MrcData   - Include all MRC global data.
+  @param[in] Channel   - Channel to setup.
+  @param[in] VicSpread - Separation of the Victim Bit.
+  @param[in] VicBit    - The Bit to be the Victim.
+  @param[in] LMNEn     - To enable LMN counter
+
+  @retval Nothing
+**/
+extern
+void
+SetupCADB (
+  IN MrcParameters *const MrcData,
+  IN const U8             Channel,
+  IN const U8             VicSpread,
+  IN const U8             VicBit,
+  IN const U8             LMNEn
+  );
+
+/**
+  Program the subsequence type field in a given MCDFXS_CR_REUT_CHx_SUBSEQ_CTL_MCMAIN_x_STRUCT register
+
+  @param[in]      MrcData    - MRC global data
+  @param[in, out] SubSeqCtl  - Address of the MCDFXS_CR_REUT_CHx_SUBSEQ_CTL_MCMAIN_x_STRUCT register
+  @param[in]      Type       - The subsequence type to program
+
+  @retval Nothing.
+**/
+void
+SetSubsequenceType (
+  IN     MrcParameters *const MrcData,
+  IN OUT U32                  *SubSeqCtl,
+  IN     U32                  Type
+  );
+
+/*
+  This function handles writing to the REUT Addressing sequence for IO Tests.
+  To not write a certain parameter, pass a NULL pointer to the function.
+
+  @param[in] MrcData       - MRC global data structure.
+  @param[in] Channel       - Specifies the channel to program.
+  @param[in] StartAddr     - Start value for Rank/Bank/Row/Col.
+  @param[in] StopAddr      - Stop value for Rank/Bank/Row/Col.
+  @param[in] FieldOrder    - Relative order for carry propagates of Rank/Bank/Row/Col.
+  @param[in] IncRate       - The number of writes to Rank/Bank/Row/Col before updating the address.
+                              Note: The function will handle linear vs exponential and a value of 0 specifies a rate of 1.
+  @param[in] IncValue      - The amount to increase Rank/Bank/Row/Col address.
+  @param[in] WrapTriggerEn - Enables wrap trigger for Rank/Bank/Row/Col to enable stopping on subsequence and sequence.
+  @param[in] WrapCarryEn   - Enables carry propagation on wrap to the next higest order field
+  @param[in] AddrInvertEn  - Enables inverting the Rank/Bank/Row/Col addresses based on AddrInvertRate.
+  @param[in] AddrIvertRate - Exponential rate of address inversion.  Only updated if AddrInvertEn != NULL.
+  @param[in] EnableDebug   - Enables/Disables debug printing.
+
+  @retval Nothing
+*/
+extern
+void
+MrcProgramSequenceAddress (
+  IN MrcParameters *const MrcData,
+  IN const U8             Channel,
+  IN const U16            StartAddr[MrcReutFieldMax],
+  IN const U16            StopAddr[MrcReutFieldMax],
+  IN const U8             FieldOrder[MrcReutFieldMax],
+  IN const U32            IncRate[MrcReutFieldMax],
+  IN const U16            IncValue[MrcReutFieldMax],
+  IN const U8             WrapTriggerEn[MrcReutFieldMax],
+  IN const U8             WrapCarryEn[MrcReutFieldMax],
+  IN const U8             AddrInvertEn[MrcReutFieldMax],
+  IN const U8             AddrInvertRate,
+  IN const BOOL           EnableDebug
+  );
+
+/**
+  Programs all the key registers to define a CPCG test
+
+  @param[in] MrcData     - Include all MRC global data.
+  @param[in] WDBPattern  - Structure that stores start, Stop, IncRate and Dqpat for pattern.
+  @param[in] ChbitMask   - Channel Bit mak for which test should be setup for.
+  @param[in] CmdPat      - [0: PatWrRd (Standard Write/Read Loopback),
+                            1: PatWr (Write Only),
+                            2: PatRd (Read Only),
+                            3: PatRdWrTA (ReadWrite Turnarounds),
+                            4: PatWrRdTA (WriteRead Turnarounds),
+                            5: PatODTTA (ODT Turnaround]
+  @param[in] NumCL       - Number of Cache lines
+  @param[in] LC          - Loop Count exponent
+  @param[in] REUTAddress - Structure that stores start, stop and increment details for address
+  @param[in] SOE         - [0: Never Stop, 1: Stop on Any Lane, 2: Stop on All Byte, 3: Stop on All Lane]
+  @param[in] WDBPattern  - Structure that stores start, Stop, IncRate and Dqpat for pattern.
+  @param[in] EnCADB      - Enable test to write random deselect packages on bus to create xtalk/isi
+  @param[in] EnCKE       - Enable CKE power down by adding 64
+  @param[in] SubSeqWait  - # of Dclks to stall at the end of a sub-sequence
+
+  @retval Nothing
+**/
+extern
+void
+SetupIOTest (
+  IN MrcParameters *const         MrcData,
+  IN const U8                     ChbitMask,
+  IN const U8                     CmdPat,
+  IN const U16                    NumCL,
+  IN const U8                     LC,
+  IN const MRC_REUTAddress *const REUTAddress,
+  IN const U8                     SOE,
+  IN MRC_WDBPattern *const        WDBPattern,
+  IN const U8                     EnCADB,
+  IN const U8                     EnCKE,
+  IN U16                          SubSeqWait
+  );
+
+/**
+  This function sets up a test with CADB for the given channel mask.
+
+  @param[in,out] MrcData   - Pointer to MRC global data.
+  @param[in]     ChbitMask - Bit masks of channels to enable for the test.
+  @param[in]     LC        - Exponential umber of loops to run the test.
+  @param[in]     SOE       - Error handling switch for test.
+  @param[in]     EnCADB    - Switch to enable CADB
+  @param[in]     EnCKE     - Switch to enable CKE.
+
+  @retval Nothing
+**/
+extern
+void
+SetupIOTestCADB (
+  IN OUT MrcParameters *const MrcData,
+  IN     const U8             ChbitMask,
+  IN     const U8             LC,
+  IN     const U8             SOE,
+  IN     const U8             EnCADB,
+  IN     const U8             EnCKE
+  );
+
+/**
+  This function sets up a basic victim-aggressor test for the given channel mask.
+
+  @param[in,out] MrcData   - Pointer to MRC global data.
+  @param[in]     ChbitMask - Bit masks of channels to enable for the test.
+  @param[in]     LC        - Exponential umber of loops to run the test.
+  @param[in]     SOE       - Error handling switch for test.
+  @param[in]     EnCADB    - Switch to enable CADB
+  @param[in]     EnCKE     - Switch to enable CKE.
+  @param[in]     Spread    - Stopping point of the pattern.
+
+  @retval Nothing
+**/
+extern
+void
+SetupIOTestBasicVA (
+  IN OUT MrcParameters *const MrcData,
+  IN     const U8             ChbitMask,
+  IN     const U8             LC,
+  IN     const U8             SOE,
+  IN     const U8             EnCADB,
+  IN     const U8             EnCKE,
+  IN     const U32            Spread
+  );
+
+/**
+  This function sets up a DQ test for the given channel mask.
+
+  @param[in,out] MrcData   - Pointer to MRC global data.
+  @param[in]     ChbitMask - Bit masks of channels to enable for the test.
+  @param[in]     LC        - Exponential umber of loops to run the test.
+  @param[in]     SOE       - Error handling switch for test.
+  @param[in]     EnCADB    - Switch to enable CADB
+  @param[in]     EnCKE     - Switch to enable CKE.
+
+  @retval Nothing
+**/
+extern
+void
+SetupIOTestDQ (
+  IN OUT MrcParameters *const MrcData,
+  IN     const U8             ChbitMask,
+  IN     const U8             LC,
+  IN     const U8             SOE,
+  IN     const U8             EnCADB,
+  IN     const U8             EnCKE
+  );
+
+/**
+  This function sets up a test with CADB for the given channel mask.
+
+  @param[in,out] MrcData   - Pointer to MRC global data.
+  @param[in]     ChbitMask - Bit masks of channels to enable for the test.
+  @param[in]     LC        - Exponential umber of loops to run the test.
+  @param[in]     SOE       - Error handling switch for test.
+  @param[in]     EnCADB    - Switch to enable CADB
+  @param[in]     EnCKE     - Switch to enable CKE.
+
+  @retval Nothing
+**/
+extern
+void
+SetupIOTestC2C (
+  IN OUT MrcParameters *const MrcData,
+  IN     const U8             ChbitMask,
+  IN     const U8             LC,
+  IN     const U8             SOE,
+  IN     const U8             EnCADB,
+  IN     const U8             EnCKE
+  );
+
+/**
+  This function sets up a MPR test for the given channel mask.
+
+  @param[in,out] MrcData   - Pointer to MRC global data.
+  @param[in]     ChbitMask - Bit masks of channels to enable for the test.
+  @param[in]     LC        - Exponential umber of loops to run the test.
+  @param[in]     SOE       - Error handling switch for test.
+  @param[in]     EnCADB    - Switch to enable CADB
+  @param[in]     EnCKE     - Switch to enable CKE.
+
+  @retval Nothing
+**/
+extern
+void
+SetupIOTestMPR (
+  IN OUT MrcParameters *const MrcData,
+  IN     const U8             ChbitMask,
+  IN     const U8             LC,
+  IN     const U8             SOE,
+  IN     const U8             EnCADB,
+  IN     const U8             EnCKE
+  );
+
+/**
+  Runs one or more REUT tests (based on TestType)
+
+  @param[in] MrcData     - Include all MRC global data.
+  @param[in] ChbitMask   - Channel Bit mask for which test should be setup for.
+  @param[in] DQPat       - [0: BasicVA
+                            1: SegmentWDB
+                            2: CADB
+                            3: TurnAround
+                            4: LMNVa
+                            5: TurnAroundWR
+                            6: TurnAroundODT
+                            7: RdRdTA]
+  @param[in] SeqLCs      - An array of one or more loopcounts.
+  @param[in] ClearErrors - Decision to clear or not errors.
+  @param[in] Mode        - Allows for different types of modes for margining
+                           {Bit0: PhLock (keep all bytes within in ch in phase),
+                            Bit1: Ch2Ch Data out of phase (LFSR seed)
+                            Bits 15:2: Reserved}
+
+  @retval Returns ch errors
+**/
+extern
+U8
+RunIOTest (
+  IN MrcParameters *const MrcData,
+  IN const U8             ChbitMask,
+  IN const U8             DQPat,
+  IN const U8 *const      SeqLCs,
+  IN const U8             ClearErrors,
+  IN const U16            Mode
+  );
+
+/**
+  Programs REUT to run on the selected physical ranks.
+
+  @param[in] MrcData           - Pointer to MRC global data.
+  @param[in] ch                - Channel to enable.
+  @param[in] RankBitMask       - Bit mask of ranks to enable.
+  @param[in] RankFeatureEnable - RankFeatureEnable is a bit mask that can enable CKE, Refresh or ZQ
+                                 RankFeatureEnable[0] enables Refresh on all non-selected ranks
+                                 RankFeatureEnable[1] enables Refresh on all ranks
+                                 RankFeatureEnable[2] enables ZQ on all non-selected ranks
+                                 RankFeatureEnable[3] enables ZQ on all ranks
+                                 RankFeatureEnable[4] enables CKE on all non-selected ranks
+                                 RankFeatureEnable[5] enables CKE on all ranks
+
+  @retval Bit mask of channel enabled if rank in the channel exists.
+**/
+extern
+U8
+SelectReutRanks (
+  IN MrcParameters *const MrcData,
+  IN const U8             ch,
+  IN U8                   RankBitMask,
+  IN const U8             RankFeatureEnable
+  );
+
+/**
+  This routine updates RXTRAINRANK register's specific fields defined by the subfield
+  subfield values:
+    0 - Update RcvEn   - leave other parameter the same
+    1 - Update RxDqsP  - leave other parameter the same
+    2 - Update RxEq    - leave other parameter the same
+    3 - Update RxDqsN  - leave other parameter the same
+    4 - Update RxVref  - leave other parameter the same
+    5 - Update RxDqsP & RxDqsN - leave other parameter the same
+    FF - leave all parameter the same
+
+  @param[in] MrcData  - Include all MRC global data.
+  @param[in] Channel  - Defines channel to update
+  @param[in] Rank     - Defines rank to update
+  @param[in] Byte     - Defines byte to update
+  @param[in] Subfield - Defines the register's field or fields to update
+  @param[in] Value    - value to be writen into register fields
+
+  @retval Nothing
+**/
+extern
+void
+UpdateRxT (
+  IN MrcParameters *const MrcData,
+  IN const U8             Channel,
+  IN const U8             Rank,
+  IN const U8             Byte,
+  IN const U8             Subfield,
+  IN const U16            Value
+  );
+
+/**
+  This routine updates TXTRAINRANK register's specific fields defined by the subfield
+  subfield values:
+    0 - Update TxDq    - leave other parameter the same
+    1 - Update TxDqs   - leave other parameter the same
+    2 - Update TxEq    - leave other parameter the same
+    3 - Update ALL from input value (non from Mrcdata structure)
+
+  @param[in] MrcData  - Include all MRC global data.
+  @param[in] Channel  - Defines channel to update
+  @param[in] Rank     - Defines rank to update
+  @param[in] Byte     - Defines byte to update
+  @param[in] Subfield - Defines the register's field or fields to update
+  @param[in] Value    - value to be writen into register fields
+
+  @retval Nothing
+**/
+extern
+void
+UpdateTxT (
+  IN MrcParameters *const MrcData,
+  IN const U8             Channel,
+  IN const U8             Rank,
+  IN const U8             Byte,
+  IN const U8             Subfield,
+  IN const U32            Value
+  );
+
+/**
+  Returns the index into the array MarginResult in the MrcOutput structure.
+
+  @param[in] ParamV - Margin parameter
+
+  @retval One of the following values: LastRxV(0), LastRxT (1), LastTxV(2), LastTxT (3), LastRcvEna (4),
+                                       LastWrLevel (5), LastCmdT (6), LastCmdV (7)
+**/
+extern
+U8
+GetMarginResultType (
+  IN const U8  ParamV
+  );
+
+/**
+  This function Reads MrcData structure and finds the minimum last recorded margin for param
+  Searches across all bytes and ranks in RankMask
+
+  @param[in]     MrcData         - Include all MRC global data.
+  @param[in,out] MarginResult    - Data structure with the latest margin results.
+  @param[in]     Param           - Defines the margin type
+  @param[in]     Ranks           - Condenses down the results from multiple ranks
+
+  @retval mrcWrongInputParameter if a bad Param is passed in, otherwise mrcSuccess.
+**/
+extern
+MrcStatus
+GetMarginCh (
+  IN     MrcParameters *const MrcData,
+  IN OUT U32                  MarginResult[MAX_RESULT_TYPE][MAX_RANK_IN_CHANNEL][MAX_CHANNEL][MAX_SDRAM_IN_DIMM][MAX_EDGES],
+  IN     const U8             Param,
+  IN     const U8             Ranks
+  );
+
+/**
+  Use this function to retrieve the last margin results from MrcData
+
+  @param[in]     MrcData         - Include all MRC global data.
+  @param[in,out] MarginResult    - Data structure with the latest margin results.
+  @param[in]     Param           - Defines the margin type
+  @param[in]     RankIn          - Which rank of the host structure you want the result returned on
+  @param[in]     Ranks           - Condenses down the results from multiple ranks
+
+  @retval MarginResult structure has been updated if MrcStatus returns mrcSuccess.
+  @retval Otherwise, mrcWrongInputParameter is returned if an incorrect Param is passed in.
+**/
+extern
+MrcStatus
+GetMarginByte (
+  IN     MrcParameters *const MrcData,
+  IN OUT U32                  MarginResult[MAX_RESULT_TYPE][MAX_RANK_IN_CHANNEL][MAX_CHANNEL][MAX_SDRAM_IN_DIMM][MAX_EDGES],
+  IN     const U8             Param,
+  IN     const U8             RankIn,
+  IN     const U8             Ranks
+  );
+
+/**
+  This function is use to "unscale" the MrcData last margin point
+  GetMarginByte will scale the results for FAN margin
+  This will unscale the results such that future tests start at the correct point
+
+  @param[in]     MrcData      - Include all MRC global data.
+  @param[in,out] MarginResult - Input array to be unscaled.
+  @param[in]     Param        - Defines the margin type for proper scale selection.
+  @param[in]     Rank         - Which rank of the host structure to work on
+
+  @retval mrcSuccess
+**/
+extern
+MrcStatus
+ScaleMarginByte (
+  IN     MrcParameters *const MrcData,
+  IN OUT U32                  MarginResult[MAX_RESULT_TYPE][MAX_RANK_IN_CHANNEL][MAX_CHANNEL][MAX_SDRAM_IN_DIMM][MAX_EDGES],
+  IN     const U8             Param,
+  IN     const U8             Rank
+  );
+
+/**
+  This function is used by most margin search functions to change te underlying margin parameter.
+  This function allows single search function to be used for different types of margins with minimal impact.
+  It provides multiple different parameters, including 2D parameters like Read or Write FAN.
+  It can work in either MultiCast or single register mode.
+
+  @param[in,out] MrcData       - Include all MRC global data.
+  @param[in]     param         - Includes parameter(s) to change including two dimentional.
+  @param[in]     value0        - Selected value to program margin param to
+  @param[in]     value1        - Selected value to program margin param to in 2D mode (FAN mode)
+  @param[in]     EnMultiCast   - To enable Multicast (broadcast) or single register mode
+  @param[in]     channel       - Desired Channel
+  @param[in]     rankIn        - Desired Rank - only used for the RxTBit and TxTBit settings and to propagate RdVref
+  @param[in]     byte          - Desired byte offset register
+  @param[in]     bitIn         - Desired bit offset Mrc data strucure if UpdateMrcData is 1
+  @param[in]     UpdateMrcData - Used to decide if Mrc host must be updated
+  @param[in]     SkipWait      - Used to skip wait until all channel are done
+  @param[in]     RegFileParam  - Used to determine which Rank to download.  Passed to MrcDownloadRegFile.
+
+  @retval MrcStatus -  if succeeded, return mrcSuccess
+**/
+extern
+MrcStatus
+ChangeMargin (
+  IN OUT MrcParameters *const MrcData,
+  IN     const U8             param,
+  IN     const S32            value0,
+  IN     const S32            value1,
+  IN     const U8             EnMultiCast,
+  IN     const U8             channel,
+  IN     const U8             rankIn,
+  IN     const U8             byte,
+  IN     const U8             bitIn,
+  IN     const U8             UpdateMrcData,
+  IN     const U8             SkipWait,
+  IN     const MrcRegFile     RegFileParam
+  );
+
+/**
+  This function triggers the hardware to download the specified RegFile.
+  The setting of ReadRfRd and ReadRfWr must be mutually exclusive.
+  Only 1 (start download) and 0 (do nothing) are valid values for ReadRfXx.
+
+  @param[in] MrcData       - Global MRC Data
+  @param[in] Channel       - The Channel to download target.
+  @param[in] ByteMulticast - Enable Multicasting all bytes on that Channel.
+  @param[in] Rank          - The Rank download target.
+  @param[in] RegFileParam  - Used to determine which Rank to download.
+                              MrcRegFileRank    - Uses the Rank Parameter.
+                              MrcRegFileStart   - Uses the Rank in REUT_CH_SEQ_BASE_ADDR_START after decoding logical to physical.
+                              MrcRegFileCurrent - Uses the Rank in REUT_CH_SEQ_BASE_ADDR_CURRENT after decoding logical to physical.
+  @param[in] Byte          - The Byte download target.
+  @param[in] ReadRfRd      - Download the read RegFile. 1 enables, 0 otherwise
+  @param[in] ReadRfWr      - Download the write RegFile. 1 enables, 0 otherwise
+
+  @retval MrcStatus - If both ReadRfRd and ReadRfWr are set, the functions returns mrcWrongInputParameters.
+                         Otherwise, mrcSuccess.
+**/
+void
+MrcDownloadRegFile (
+  IN MrcParameters * const  MrcData,
+  IN const U8               Channel,
+  IN const BOOL             ByteMulticast,
+  IN U8                     Rank,
+  IN const MrcRegFile       RegFileParam,
+  IN const U8               Byte,
+  IN const BOOL             ReadRfRd,
+  IN const BOOL             ReadRfWr
+  );
+
+/**
+  This procedure is meant to handle basic timing centering, places strobe in the middle of the data eye,
+  for both read and write DQ/DQS using a very robust, linear search algorthim.
+
+  @param[in,out] MrcData     - Include all MRC global data.
+  @param[in]     chBitMaskIn - Channel bit mask.
+  @param[in]     param       - {0:RcvEn, 1:RdT, 2:WrT, 3: WrDqsT, 4:RdV, 5:WrV, 6:WrLevel,
+                                8:WrTBit, 9:RdTBit, 10:RdVBit,
+                                16:RdFan2, 17:WrFan2, 32:RdFan3, 32:WrFan3}
+                                ONLY RdT and WrT are allowed in this function
+  @param[in]     ResetPerBit - Option to Reset PerBit Deskew to middle value before byte training
+  @param[in]     loopcount   - loop count
+
+  @retval MrcStatus -  If succeeded, return mrcSuccess
+**/
+extern
+MrcStatus
+DQTimeCentering1D (
+  IN OUT MrcParameters *const MrcData,
+  IN     const U8             chBitMaskIn,
+  IN     const U8             param,
+  IN     const U8             ResetPerBit,
+  IN     const U8             loopcount
+  );
+
+/**
+  This procedure is meant to handle much more complex centering that will use a 2D algorithm to optimize asymetical
+  eyes for both timing and voltage margin.
+
+  @param[in,out] MrcData         - Include all MRC global data.
+  @param[in,out] MarginResult    - Margin data from centering
+  @param[in]     ChBitMaskIn     - Channel bit mask.
+  @param[in]     param           - {0:RcvEn, 1:RdT, 2:WrT, 3: WrDqsT, 4:RdV, 5:WrV, 6:WrLevel,
+                                    8:WrTBit, 9:RdTBit, 10:RdVBit,
+                                    16:RdFan2, 17:WrFan2, 32:RdFan3, 32:WrFan3}
+                                    ONLY RdT and WrT are allowed in this function
+  @param[in]     EnPerBit        - Option to enable per bit margining
+  @param[in]     EnRxDutyCycleIn - Phase to center.
+  @param[in]     ResetPerBit     - Option to Reset PerBit Deskew to middle value before byte training
+  @param[in]     LoopCount       - loop count
+  @param[in]     En2D            - Option to only run center at nominal Vref point
+
+  @retval MrcStatus -  If succeeded, return mrcSuccess
+**/
+extern
+MrcStatus
+DataTimeCentering2D (
+  IN OUT MrcParameters *const MrcData,
+  IN OUT U32                  MarginResult[MAX_RESULT_TYPE][MAX_RANK_IN_CHANNEL][MAX_CHANNEL][MAX_SDRAM_IN_DIMM][MAX_EDGES],
+  IN     const U8             ChBitMaskIn,
+  IN     const U8             Param,
+  IN     const U8             EnPerBit,
+  IN     const U8             EnRxDutyCycleIn,
+  IN     const U8             ResetPerBit,
+  IN     const U8             LoopCount,
+  IN     const U8             En2D
+  );
+
+/**
+  Subfunction of 2D Timing Centering
+  Measures paramV margin across ch/bytes and updates the EH/VrefScale variables
+
+  @param[in]     MrcData   - Include all MRC global data.
+  @param[in]     ChBitMask - Channel Bit mak for which test should be setup for.
+  @param[in]     rank      - Defines rank to used for MrcData
+  @param[in]     ParamV    - Margin parameter
+  @param[in]     MaxVScale - Maximum Voltage Scale to use
+  @param[in]     BMap      - Byte mapping to configure error counter control register
+  @param[in,out] EH        - Structure that stores start, stop and increment details for address
+  @param[in,out] VrefScale - Parameter to be updated
+  @param[in,out] BERStats  - Bit Error Rate Statistics.
+
+  @retval mrcSuccess if successful, otherwise the function returns an error status.
+**/
+extern
+MrcStatus
+DQTimeCenterEH (
+  IN     MrcParameters * const MrcData,
+  IN     const U8              ChBitMask,
+  IN     const U8              rank,
+  IN     const U8              ParamV,
+  IN     const U8              MaxVScale,
+  IN     U8 * const            BMap,
+  IN OUT U32                   EH[MAX_CHANNEL][MAX_SDRAM_IN_DIMM],
+  IN OUT U32                   VrefScale[MAX_CHANNEL][MAX_SDRAM_IN_DIMM],
+  IN OUT U32 * const           BERStats
+  );
+
+/**
+  Update the Vref value
+  if VrefType = 0     Updates Ch0 Vref_Dq
+  if VrefType = 1     Updates Ch1 Vref_Dq
+  if VrefType = 2     Updates Vref_CA
+
+  @param[in,out] MrcData       - Include all MRC global data.
+  @param[in]     VrefType      - Determines the Vref to change
+  @param[in]     UpdateMrcData - Used to decide if Mrc host must be updated
+  @param[in]     Offset        - Vref value
+  @param[in]     SkipWait      - Determines if we will wait for vref to settle after writing to register
+
+  @retval Nothing
+**/
+extern
+void
+UpdateVrefWaitTilStable (
+  IN OUT MrcParameters *const MrcData,
+  IN     const U8             VrefType,
+  IN     const U8             UpdateMrcData,
+  IN     S32                  Offset,
+  IN     U8                   SkipWait
+  );
+
+/**
+  This function is used to move CMD/CTL/CLK/CKE PIs during training
+
+  @param[in,out] MrcData    - Include all MRC global data.
+  @param[in]     Channel    - Channel to shift PI for
+  @param[in]     Iteration  - Determines which PI to shift:
+                              MrcIterationClock = 0
+                              MrcIterationCmdN  = 1
+                              MrcIterationCmdS  = 2
+                              MrcIterationCke   = 3
+                              MrcIterationCtl   = 4
+                              MrcIterationCmdV  = 5
+  @param[in]     RankMask   - Ranks to work on
+  @param[in]     GroupMask  - which LPDDR groups to work on for CMD/CLK/CKE; not used for DDR3
+  @param[in]     NewValue   - value to shift in case of CLK Iteration, New value for all other cases
+  @param[in]     UpdateHost - Determines if MrcData structure is updated
+
+  @retval Nothing
+**/
+extern
+void
+ShiftPIforCmdTraining (
+  IN OUT MrcParameters *const MrcData,
+  IN     const U8             Channel,
+  IN     const U8             Iteration,
+  IN     const U8             RankMask,
+  IN     const U8             GroupMask,
+  IN     S32                  NewValue,
+  IN     const U8             UpdateHost
+  );
+
+/**
+  Shifts RcvEn, WriteLevel and WriteDQS timing for all bytes
+  Usually used when moving the clocks on a channel
+
+  @param[in,out] MrcData    - Include all MRC global data.
+  @param[in]     Channel    - Channel to update
+  @param[in]     Rank       - Rank to update
+  @param[in]     ByteMask   - Bytes to update
+  @param[in]     Offset     - value to shift
+  @param[in]     UpdateHost - Determines if MrcData structure is updated
+  @param[in]     SkipTx     - Determines if TX update should be skipped
+
+  @retval Nothing
+**/
+extern
+void
+ShiftDQPIs (
+  IN OUT MrcParameters *const MrcData,
+  IN     const U8             Channel,
+  IN     const U8             Rank,
+  IN     const U32            ByteMask,
+  IN     const S8             Offset,
+  IN     const U8             UpdateHost,
+  IN     const U8             SkipTx
+  );
+
+/**
+  Retrieve the current memory frequency and clock from the memory controller.
+
+    @param[in]      MrcData     - Include all MRC global data.
+    @param[in, out] MemoryClock - The current memory clock.
+    @param[in, out] Ratio       - The current memory ratio setting.
+    @param[in, out] RefClk      - The current memory reference clock.
+
+  @retval: The current memory frequency.
+**/
+extern
+MrcFrequency
+MrcGetCurrentMemoryFrequency (
+  IN MrcParameters * const       MrcData,
+  IN OUT U32 * const             MemoryClock,
+  IN OUT MrcClockRatio * const   Ratio,
+  IN OUT MrcRefClkSelect * const RefClk
+  );
+
+#ifdef ULT_FLAG
+/**
+  Translate LPDDR command from CA[9:0] high and low phase to DDR3 MA/BA/CMD.
+  This is needed to program CADB.
+
+  @param[in]   CaHigh  - CA[9:0] value on the rising clock
+  @param[in]   CaLow   - CA[9:0] value on the falling clock
+  @param[out]  MA      - Translated value of MA[15:0]
+  @param[out]  BA      - Translated value of BA[2:0]
+  @param[out]  CMD     - Translated value of CMD[2:0] = [RASb, CASb, WEb]
+
+  @retval none
+**/
+extern
+void
+MrcConvertLpddr2Ddr (
+  IN U32             const CaHigh,
+  IN U32             const CaLow,
+  OUT U32          * MA,
+  OUT U32          * BA,
+  OUT U32          * CMD
+  );
+
+/**
+  Run a short CADB sequence on selected channels
+
+  @param[in] MrcData      - The MRC global data.
+  @param[in] ChBitMask    - channels to work on.
+
+  @retval none
+**/
+extern
+void
+ShortRunCADB (
+  IN MrcParameters * const  MrcData,
+  IN U8                     ChBitMask
+  );
+
+#endif // ULT_FLAG
+/**
+  Get the Rx Bias values
+
+  @param[in, out] MrcData    - Include all MRC global data.
+  @param[in, out] RxFselect  - Location to save RxFselect.
+  @param[in, out] RxCBSelect - Location to save RxCBSelect.
+
+  @retval none
+**/
+extern
+void
+GetRxFselect (
+  IN MrcParameters *const MrcData,
+  IN OUT S8            *RxFselect,
+  IN OUT U8            *RxCBSelect
+  );
+
+#endif // _MrcCommon_h_
diff --git a/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcCrosser.h b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcCrosser.h
new file mode 100644
index 0000000..a0d838a
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcCrosser.h
@@ -0,0 +1,1329 @@
+/** @file
+    This file contains all the crosser training algorithm definitions.
+
+@Copyright
+  Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved.
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement.
+**/
+#ifndef _MrcCrosser_h_
+#define _MrcCrosser_h_
+
+//
+// Include files
+//
+#include "MrcTypes.h"
+#include "MrcApi.h"
+#include "McAddress.h"
+#include "MrcCommon.h"
+#include "MrcDdr3.h"
+#include "MrcIoControl.h"
+#include "MrcOem.h"
+#include "MrcReadDqDqs.h"
+#include "MrcWriteDqDqs.h"
+#include "MrcRefreshConfiguration.h"
+#include "MrcTimingConfiguration.h"
+#include "MrcReset.h"
+
+#define MAX_BITS_FOR_OFFSET_TRAINING    (MAX_BITS + 1)    ///< for ULT offset training done for 8 bits + DQS bit
+
+///
+/// Module Defines
+///
+#define CROSSER_DISABLE_SQUARED_FUNCTION (0)
+#define CROSSER_ENABLE_SQUARED_FUNCTION  (1)
+#define CROSSER_MIDDLE_SCALING_1         (1)
+#define CROSSER_OPTIMIZE_LOW_POWER       (0)
+#define CROSSER_OPTIMIZE_HIGH_POWER      (1)
+#define CROSSER_EXCLUDE_END_POINTS       (0)
+#define CROSSER_INCLUDE_END_POINTS       (1)
+
+///
+/// Enumerations and Structs
+///
+
+typedef enum {
+  RdOdt,
+  WrDS,
+  WrDSCmd,
+  WrDSCtl,
+  WrDSClk,
+  SCompDq,
+  SCompCmd,
+  SCompCtl,
+  SCompClk,
+  DisOdtStatic
+} TGlobalCompOffset;
+
+typedef enum {
+  RdSAmpOfft,
+  WrDSOfft,
+  RxEqOfft,
+  TxEqOfft,
+  RdOdtOfft,
+  SizeOfTCompOffset
+} TCompOffset;
+
+typedef enum {
+  rd2rdXtalk,
+  rd2wrXtalk,
+  wr2wrXtalk,
+  wr2rdXtalk,
+  AllXtalk
+} CrossTalkModes;
+
+///
+/// These enums index MoreResultsStrings in PrintCalcResultTableCh()
+///
+typedef enum {
+  MrcOptResultBest,
+  MrcOptResultGrdBnd,
+  MrcOptResultOffSel,
+  MrcOptResultScale,
+  MrcOptResultSignal,
+  MrcOptResultNoise,
+  MrcOptResultRatio,
+  MrcOptResultMaxPost,
+  MrcOptResultMinPost,
+  MrcOptResultTicks,
+  MrcOptResultSnrTot,
+
+  MrcOptResultMax
+} MrcOptResultString;
+
+
+#define  MaxOptOff       (35)
+
+#pragma pack (push, 1)
+typedef struct {
+  U32              EW;
+} OptResult;
+
+typedef struct {
+  U16              Best;
+  S8               GuardBand;
+  U8               Scale[5];
+  U32              Signal[5];
+  U32              Noise[5];
+  U32              Ratio[5];
+  U32              MaxPost[5];
+  U32              MinPost[5];
+  U16              Ticks[5];
+  U64              SNRTotal;
+  U64              MaxR;
+  U64              MinR;
+  U64              Result[MaxOptOff];
+  OptResult        Margins[5][MaxOptOff];
+} OptResultsPerByte;
+#pragma pack (pop)
+
+typedef struct {
+  S16              Offset[MAX_CHANNEL][MAX_SDRAM_IN_DIMM];
+  U16              Margins[4][MAX_CHANNEL];
+  U8               TestList[4][MAX_CHANNEL];
+  U8               NumTests;
+  U8               Best;
+} OptOffsetChByte;
+
+typedef struct {
+  U8        RttNom[MAX_CHANNEL][MAX_DIMMS_IN_CHANNEL];
+  U8        RttWr[MAX_CHANNEL][MAX_DIMMS_IN_CHANNEL];
+  S8        GRdOdt;
+  U32       GRdOdtCode;
+} DimmOffset;
+
+typedef struct {
+  U32        CpuPwrRd;
+  U32        DimmPwrRd;
+  U32        CpuPwrWr;
+  U32        DimmPwrWrNT;
+  U32        DimmPwrWrT;
+  U32        ACPowerRd;
+  U32        ACPowerWr;
+  U32        ACPower;
+  U16        CpuPower;
+  U16        DimmPwr;
+  U16        TotPwr;
+} MrcPower;
+
+typedef struct {
+  DimmOffset        ODTSet;
+  MrcPower          PowerCalc;
+  U16               Test[5][MAX_CHANNEL];
+  OptOffsetChByte   BestOptOff[SizeOfTCompOffset][MAX_RANK_IN_CHANNEL];
+  U8                NumTests;
+  U8                TestList[4];
+  U8                OptParamTestList[5];
+  U8                OptParamTestListSize;
+  U16               Points2Trade[5][MAX_CHANNEL];
+} DimmOptPoint;
+
+/**
+  This function implements Sense Amp Offset training.
+  SenseAmp/ODT offset cancellation
+  Find the best "average" point for Vref Control
+  Test Vref point with SampOffset=-7 and Test Vref Point with SampOffset=+7
+  Find Vref on per ch/byte basis where -7 samples all 1 and +7 samples all 0
+
+  @param[in,out] MrcData - Include all MRC global data.
+
+  @retval MrcStatus - if it succeded return mrcSuccess
+**/
+extern
+MrcStatus
+MrcSenseAmpOffsetTraining (
+  IN OUT MrcParameters *const MrcData
+  );
+
+/**
+  This function looks at the margin values stored in the global data structure and checks
+  WrT, WrV, RdT, and RdV to see if they are above the minimum margin required.
+
+  @param[in, out] MrcData - MRC global data.
+
+  @retval mrcSuccess if margins are acceptable.
+  @retval Otherwise, mrcRetrain.
+**/
+MrcStatus
+MrcRetrainMarginCheck (
+  IN OUT MrcParameters *const MrcData
+  );
+
+/**
+  This function implements Dimm Ron training.
+
+  @param[in] MrcData - Include all MRC global data.
+
+  @retval MrcStatus -  if it succeeds return mrcSuccess
+**/
+extern
+MrcStatus
+MrcDimmRonTraining (
+  IN MrcParameters *const MrcData
+  );
+
+/**
+  This function implements DIMM ODT training.
+  Adjust DIMM RTT_NOM/RTT_WR value to maximize read/write voltage/timing
+
+  RdOdtPriority Needs to be an input parameter
+  option to prioritize the ReadODT setting and attempt to optimize that value first,
+  reducing CPU TDP power (as opposed to system power for the DRAM).
+  For this case, the base value for ReadODT is changed at the compensation block
+  by looking at the following values:
+     RdOdt Global: (50, 64, 84, 110)
+
+  In the case of 2 dpc, the flow will first optimizing RttNom, while keeping RttWr fixed
+  at 60 Ohms (60 Ohms usually gives the best results).  It will then try to reduce RttWr
+  to 120 Ohms if possible.
+
+  In the case of 1 dpc, only RttNom is used and only a single pass is required.
+  However, it is important to note that the two channels are completely independent
+  and can have different numbers of dimms populated.
+
+  @param[in] MrcData         - Include all MRC global data.
+
+  @retval MrcStatus      - if it succeed return mrcSuccess
+**/
+extern
+MrcStatus
+MrcDimmODTTraining (
+  IN MrcParameters *const MrcData
+  );
+
+/**
+  This function implements Dimm Odt training.
+  Optimize Dimm Odt value for performance/power
+
+  @param[in] MrcData - Include all MRC global data.
+
+  @retval MrcStatus - If it succeded return mrcSuccess
+**/
+extern
+MrcStatus
+MrcDimmODT1dTraining (
+  IN MrcParameters *const MrcData
+  );
+
+/**
+  This function implements Read Equalization training.
+
+  @param[in] MrcData - Include all MRC global data.
+
+  @retval MrcStatus - if it succeeds return mrcSuccess
+**/
+extern
+MrcStatus
+MrcReadEQTraining (
+  IN MrcParameters *const MrcData
+  );
+
+/**
+  This function implements Write (Transmitter) Equalization training.
+
+  @param[in] MrcData - Include all MRC global data.
+
+  @retval MrcStatus - if it succeeds return mrcSuccess
+**/
+extern
+MrcStatus
+MrcWriteEQTraining (
+  IN MrcParameters *const MrcData
+  );
+
+/**
+  This function implements Read Amplifier Power training.
+
+  @param[in] MrcData - Include all MRC global data.
+
+  @retval MrcStatus - If it succeeds return mrcSuccess
+**/
+extern
+MrcStatus
+MrcReadAmplifierPower (
+  IN MrcParameters *const MrcData
+  );
+
+/**
+  Returns the index into the array OptResult in the MrcOutput structure.
+
+  @param[in] OptParam - Margin parameter
+
+  @retval One of the following values: RdSAmpOfft(0), WrDSOfft (1), RxEqOfft(2), TxEqOfft (3), RdOdtOfft(4)
+**/
+extern
+U8
+GetOptResultType(
+  IN U8 OptParam
+  );
+
+/**
+  This function implements Read ODT training and Write DS.
+  Optimize Read ODT strength for performance & power.
+
+  @param[in,out] MrcData         - Include all MRC global data.
+  @param[in,out] BestOff         - Structure containg the best offest and margins for th Opt param.
+  @param[in]     ChannelMask     - Channels to train
+  @param[in]     RankMask        - Condenses down the results from multiple ranks
+  @param[in]     OptParam        - Defines the OptParam Offsets.
+                               Supported OptParam = [0: WrDS, 1: RdODT, 2: SComp, 3: TComp, 3: TxEq, 4: RxEq,
+                                                     5: RxBias, 6: DimmOdt, 7: DimmOdtWr]
+  @param[in]     TestList        - List of margin params that will be tested (up to 4)
+  @param[in]     NumTests        - The length of TestList
+  @param[in]     Scale           - List of the relative importance between the 4 tests
+  @param[in]     PwrLimitsABC    - List of the values for each test margin, above which margin is "adequate"
+  @param[in]     Start           - Start point of sweeping the Comp values
+  @param[in]     Stop            - Stop point of sweeping the Comp values
+  @param[in]     LoopCount       - The number of loops to run in IO tests.
+  @param[in]     Repeats         - Number of times to repeat the test to average out any noise
+  @param[in]     NoPrint         - Switch to disable printing.
+  @param[in]     SkipOptUpdate   - Switch to train but not update Opt settings.
+  @param[in]     RdRd2Test       - Switch to run with different TA times: possible values are [0, RdRdTA, RdRdTA_All]
+  @param[in]     GuardBand       - Signed offset to apply to the Opt params best value.
+
+  @retval Nothing
+**/
+extern
+void
+TrainDDROptParam (
+  IN OUT MrcParameters *const MrcData,
+  IN OUT OptOffsetChByte      *BestOff,
+  IN     U8                   ChannelMask,
+  IN     U8                   RankMask,
+  IN     U8                   OptParam,
+  IN     U8                   *TestList,
+  IN     U8                   NumTests,
+  IN     U8                   *Scale,
+  IN     U16                  *PwrLimitsABC,
+  IN     S8                   Start,
+  IN     S8                   Stop,
+  IN     U8                   LoopCount,
+  IN     U8                   Repeats,
+  IN     BOOL                 NoPrint,
+  IN     BOOL                 SkipOptUpdate,
+  IN     U8                   RdRd2Test,
+  IN     S8                   GuardBand
+  );
+
+/**
+  This function implements Read ODT training.
+  Optimize Read ODT strength for performance & power
+
+  @param[in] MrcData - Include all MRC global data.
+
+  @retval MrcStatus - If it succeded return mrcSuccess
+**/
+extern
+MrcStatus
+MrcReadODTTraining (
+  IN MrcParameters *const MrcData
+  );
+
+/**
+  This function is the Write Drive Strength training entry point.
+  This step will optimize write drive strength for performance & power.
+
+  @param[in] MrcData - Include all MRC global data.
+
+  @retval MrcStatus - If it succeeds return mrcSuccess
+**/
+extern
+MrcStatus
+MrcWriteDriveStrength (
+  IN MrcParameters *const MrcData
+  );
+
+/**
+  Updates a given ch/Rank/byte combination with a new value for OptParam
+  OptParam can be: WrDS, RdOdt, TComp, SComp, RxEq, TxEq, RxBias or DimmOdt
+  OptParam == OptDefault restore values from Host except Dimms Odt's
+  @param[in,out] MrcData         - Include all MRC global data.
+  @param[in]     Channel         - Channel index to work on.
+  @param[in]     Ranks           - Condenses down the results from multiple ranks
+  @param[in]     Byte            - Byte index to work on.
+  @param[in]     OptParam        - Defines the OptParam Offsets.
+                                   Supported OptParam = [0: WrDS, 1: RdODT, 2: SComp, 3: TComp, 4: TxEq,
+                                                         5: RxEq, 6: RxBias, 7: DimmOdt, 8: DimmOdtWr]
+  @param[in]     Off             - Offset
+  @param[in]     UpdateHost      - Desides if MrcData has to be updated
+
+  @retval Nothing
+**/
+extern
+void
+UpdateOptParamOffset (
+  IN OUT MrcParameters *const MrcData,
+  IN     const U8             Channel,
+  IN     const U8             Ranks,
+  IN     const U8             Byte,
+  IN     const U8             OptParam,
+  IN     S16                  Off,
+  IN     const U8             UpdateHost
+  );
+
+/**
+  Slightly penalize any Asymmetry in margin
+
+  @param[in] NegEdge - Negative edge of the margin
+  @param[in] PosEdge - Positive edge of the margin
+
+  @retval p2p - Width/Height reduced by the asymmetric difference in margin.
+**/
+extern
+U16
+EffectiveMargin (
+  IN const U16 NegEdge,
+  IN const U16 PosEdge
+  );
+
+/**
+  This function does a running average on Margins in two dimentional fashion.
+
+  @param[in,out] Margins - Margins to average
+  @param[in]     Test    - Selects the Margins to average
+  @param[in]     MLen    - Determines the Y-Dimension lengths
+  @param[in]     XDim    - Determines the X-Dimension lengths
+  @param[in]     XMin    - Used to skip the first elements in the Margin when averaging.
+  @param[in]     CScale  - Used to place more weight on the center point.
+
+  @retval Nothing
+**/
+extern
+void
+RunningAverage2D (
+  IN OUT U16       Margins[2][24],
+  IN     const U8  Test,
+  IN     const U8  MLen,
+  IN     const U8  XDim,
+  IN     const U8  XMin,
+  IN     const U8  CScale
+  );
+
+/**
+    Updates a given ch/Rank/byte combination with a new value for OptParam
+    OptParam can be: WrDS, RdOdt, TComp, SComp, RxEq, TxEq, RxBias or DimmOdt
+
+    # Margins: Upto 4 arrays that contain lenMargin elements
+    # Index to the array represents some arbitrary parameter value that we are optimizing
+    # Scale is 4 element array that scales the relative importance on Margins[0] vs. [1] ...
+    #    ex: To make Margins[0] twice as important, set Scale = [1, 2, 2, 2]
+    #    Since the search optimizes the lowest margin, increasing 1/2/3 makes 0 more important
+    #    This function can be used to optimize only Margin[0] by setting Scale = [1, 0, 0, 0]
+    # EnSq = 1 uses a squared function to make the tradeoff between 0/1/2/3 steeper
+    # If AveN > 0, pre-processes the results with a N point running average filter
+    # IncEnds: By setting to 1, the running average will also include the end points
+    # ScaleM:  Allows the middle point of the running average to be scaled up
+    #
+    # In addition to optimizing for margin, this function can also optimize for power
+    # PwrLimit is a 4 element array that sets level where pwr is more important than margin
+    # Find any points where ((Margin[0]>PwrLimit[0]) & (Margin[1]>PwrLimit[1]) & ... )
+    # If such points exists and PwrOptHigh = 1, returns point with the highest X value
+    # If such points exists and PwrOptHigh = 0, returns point with the lowest X value
+    # If you don't want to optimize for power, set PwrLimitA and PwrLimitB to large number
+    # Power Optimize still uses the running average filter
+    #
+    # To avoid overflow, this function will automatic scale margins to fit in uint32
+
+  @param[in]     MrcData       - The global MRC data structure.
+  @param[in,out] OptResByte    - Structure containing the optimized results.
+  @param[in]     inputMargins  - Margins we are optimizing
+  @param[in]     MarginsLength - The length of inputMargins
+  @param[in]     LenMargin     - The length of inputMargins we are optimizing (0 - LenMargin -1).
+  @param[in]     Scale         - Controls the scaling of the input margin: 1-1, 1-2, ... and so on.
+  @param[in]     EnSq          - Enables the square root term in the optimization functions.
+  @param[in]     AveN          - The number of points used for the averaging filter.
+  @param[in]     IncEnds       - Controls if the endpoints are to be included.
+  @param[in]     ScaleM        - Controls the scaling of the middle point in 1-D average filter.
+  @param[in]     PwrLimit      - The power limit above which we only trade-off for power and not margin.
+  @param[in]     PwrOptHigh    - Controls returning the highest or lowest optimization point.
+  @param[in]     GuardBand     - Signed offest to check if margin drop is acceptable.  Save good guardband
+                                 in OptResByte.
+
+  @retval Nothing.
+**/
+extern
+void
+FindOptimalTradeOff (
+  IN     MrcParameters      *const MrcData,
+  IN OUT OptResultsPerByte         *OptResByte,
+  IN     void                      *inputMargins,
+  IN     U8                        MarginsLength,
+  IN     S8                        LenMargin,
+  IN     U8                        *Scale,
+  IN     U8                        EnSq,
+  IN     U8                        AveN,
+  IN     U8                        IncEnds,
+  IN     U8                        ScaleM,
+  IN     U16                       *PwrLimit,
+  IN     U8                        PwrOptHigh,
+  IN     S8                        GuardBand
+  );
+
+/**
+  This function implements Turn Around Timing training.
+  Optimize TA ODT Delay and Duration
+
+  @param[in] MrcData - Include all MRC global data.
+
+  @retval MrcStatus - If it succeeds return mrcSuccess.
+**/
+extern
+MrcStatus
+MrcTurnAroundTiming (
+  IN MrcParameters * const MrcData
+  );
+
+/**
+  General purpose function to optimize an abritray value, OptParam (see list above)
+    OptParam is generally some timing number that impacts performance or power
+    Expects that as OptParam gets smaller*, margins are flat until we hit a cliff
+    This procedure defines a cliff as a reducution of 4 ticks in eye height/width
+    * In the case of mcodts, higher values are actually worst
+    To stress out the timing, xxDDR_CLK is shifted by +/- 15 PI ticks
+
+  @param[in] MrcData         - Include all MRC global data.
+  @param[in] OptParam        - Supports Turnaround Timings and ODT Start / Duration
+  @param[in] TestList        - List of margin param to check to make sure timing are okay.
+  @param[in] NumTests        - The size of TestList
+  @param[in] Start           - Start point for this turn around time setting.
+  @param[in] Stop            - Stop point for this turnaround time setting.
+                                 Note that the Start/Stop values are the real values, not the encoded value
+  @param[in] LoopCount       - Length of a given test
+  @param[in] Update          - Update the CRs and host structure with ideal values
+  @param[in] ClkShifts       - Array of Pi clocks to be shifted
+  @param[in] MarginByte      - Byte level margins
+  @param[in] NumR2RPhases    - Number of PI clock phases
+  @param[in] rank            - rank to work on
+  @param[in] RankMask        - RankMask to be optimized
+  @param[in] GuardBand       - GuardBand to be added to last pass value (to be a bit conservative).
+
+  @retval MrcStatus      - If it succeeds return mrcSuccess
+**/
+extern
+MrcStatus
+TrainDDROptParamCliff (
+  IN MrcParameters *const MrcData,
+  IN U8                   OptParam,
+  IN U8                   TestList[],
+  IN U8                   NumTests,
+  IN S8                   Start,
+  IN S8                   Stop,
+  IN U8                   LoopCount,
+  IN U8                   Update,
+  IN U32                  MarginByte[MAX_RESULT_TYPE][MAX_RANK_IN_CHANNEL][MAX_CHANNEL][MAX_SDRAM_IN_DIMM][MAX_EDGES],
+  IN S8                   *ClkShifts,
+  IN U8                   NumR2RPhases,
+  IN U8                   rank,
+  IN U8                   RankMask,
+  IN U8                   GuardBand
+  );
+
+/**
+  Sets commnad margins when moving WrT, WrTBox, or WrV
+  NOTE: ONLY one, ResetDDR or SelfRefresh can be set inside this function
+
+  @param[in] MrcData         - Include all MRC global data.
+  @param[in] ChBitMask       - Bit mask of populated channels
+  @param[in] Ranks           - Bit Mask of populated ranks
+  @param[in] Param           - Input parameter to update
+  @param[in] Value0          - value to be added
+  @param[in] Value1          - value to be added
+  @param[in] ResetDDR        - Do we reset DDR?
+  @param[in] SelfRefresh     - Do we perform Self refresh?
+
+  @retval MrcStatus      - If it succeeds return mrcSuccess
+**/
+extern
+void
+SetCmdMargin (
+  IN MrcParameters *const MrcData,
+  IN const U8             ChBitMask,
+  IN const U8             Ranks,
+  IN const U8             Param,
+  IN const U8             Value0,
+  IN const U8             Value1,
+  IN U8                   ResetDDR,
+  IN const U8             SelfRefresh
+  );
+
+/**
+  Updates the value for following OptParamCliff variables:
+  drrd2rd=0, ddrd2rd=1, drwr2wr=2, ddwr2wr=3, drrd2wr=4, ddrd2wr=5, drwr2rd=6, ddwr2rd=7,
+  rdodtd=8, wrodtd=9, mcodts=10, mcodtd=11, rtl=12}
+
+  @param[in,out] MrcData    - Include all MRC global data.
+  @param[in]     Channel    - Channel to update the specificed parameter.
+  @param[in]     Byte       - Byte to update the specified parameter.
+  @param[in]     OptParam   - Parameter to update.
+  @param[in]     Off        - Value to offset the current setting.
+  @param[in]     UpdateHost - Switch to update the host structure with the new value.
+  @param[in]     SkipPrint  - Switch to skip debug prints.
+  @param[in]     RankMask   - Bit mask of Ranks to update.
+
+  @retval Nothing
+**/
+extern
+void
+UpdateTAParamOffset (
+  IN OUT MrcParameters *const MrcData,
+  IN     const U8             Channel,
+  IN     const U8             Byte,
+  IN     const U8             OptParam,
+  IN     const U8             Off,
+  IN     const U8             UpdateHost,
+  IN     const U8             SkipPrint,
+  IN     const U8             RankMask
+  );
+
+/**
+  This function applies the new DRAM ODT settings
+  Walks through various optimizations to get the best result with new ODT values
+  This includes WrDS, RdODT, Eq, etc.
+  Updates Best* variables if this point if better than the prior points
+  chDone is both an input and output.  Reports which channels have a good enough value
+  if SkipRd is high, it will skip the read related functions (RdODT, RdEq, RdTiming)
+
+  @param[in]     MrcData              - Include all MRC global data.
+  @param[in,out] DimmOptPoints        - Structure of all the DIMM ODT optimal settings.
+  @param[in]     ChMask               - Channel to work on.
+  @param[in]     RankMask             - Rank to work on.
+  @param[in]     skipGRdOdt           - Used to skip RdODT.
+  @param[in]     RttNom               - Rtt_Nom value for each DIMM.
+  @param[in]     RttWr                - Rtt_Wr value for each DIMM.
+  @param[in]     GRdOdt               - CPU Global Read ODT.
+  @param[in]     OptParamTestList     - List of Opt test(Drive Strength, RxBias, TxEq, RxEq) to run.
+  @param[in]     OptParamTestListSize - Size of OptParamTestList.
+  @param[in]     SubPwrLimits         - Switch to apply power limits to the suboptimization.
+  @param[in]     skipOptTests         - Skips the suboptimization.
+  @param[in]     skipOptPrint         - Skip printing of the suboptimization steps.
+  @param[in]     RdCenter             - Switch to recenter read.
+  @param[in]     WrCenter             - Switch to recenter write.
+  @param[in]     inputBestMargin      - Array of the best margin for each test.
+  @param[in]     MarginsLength        - Length of inputBestMargin.
+  @param[in]     OffsetPoint          - Index inside inputBestMargin to start.
+
+  @retval Nothing.
+**/
+extern
+void
+TrainDimmOdtSetting (
+  IN     MrcParameters *const MrcData,
+  IN OUT DimmOptPoint         *DimmOptPoints,
+  IN     U8                   ChMask,
+  IN     U8                   RankMask,
+  IN     U8                   skipGRdOdt,
+  IN     U8                   RttNom[MAX_CHANNEL][MAX_DIMMS_IN_CHANNEL],
+  IN     U8                   RttWr[MAX_CHANNEL][MAX_DIMMS_IN_CHANNEL],
+  IN     S8                   GRdOdt,
+  IN     U8                   *OptParamTestList,
+  IN     U8                   OptParamTestListSize,
+  IN     BOOL                 SubPwrLimits,
+  IN     BOOL                 skipOptTests,
+  IN     BOOL                 skipOptPrint,
+  IN     BOOL                 RdCenter,
+  IN     BOOL                 WrCenter,
+  IN     void                *inputBestMargin,
+  IN     U8                   MarginsLength,
+  IN     U8                   OffsetPoint
+  );
+
+/**
+  This function applies an offset to the global compensation logic.
+  Reruns Compensation and returns the new comp value
+
+  @param[in,out] MrcData         - Include all MRC global data.
+  @param[in]     param           - Parameter defining the desired global compensation logic
+  @param[in]     offset          - Value to apply
+  @param[in]     UpdateHost      - Desides if MrcData has to be updated
+
+  @retval Returns the new comp value.
+**/
+extern
+U32
+UpdateCompGlobalOffset (
+  IN OUT MrcParameters *const MrcData,
+  IN     const U8             param,
+  IN     const U32            offset,
+  IN     const U8             UpdateHost
+  );
+
+/**
+  Programs Delay/Duration for the SenseAmp and MCODT based on RcvEn timing
+  Provide GuardBand > 0 if needed to be more conservative in timing
+  Main goal is to optimize power
+
+  @param[in,out] MrcData   - Include all MRC global data.
+  @param[in]     GuardBand - Input parameter with more conservative value
+
+  @retval Nothing
+**/
+extern
+void
+UpdateSampOdtTiming(
+  IN OUT MrcParameters *const MrcData,
+  IN     const U8             GuardBand
+  );
+
+/**
+  Turns off unused portions of the slave DLL to save power
+
+  @param[in,out] MrcData - Include all MRC global data.
+
+  @retval Nothing
+**/
+extern
+void
+UpdateSlaveDLLLength(
+  IN OUT MrcParameters * const MrcData
+  );
+
+#ifdef TRAD_FLAG
+/**
+  Update Internal clocks on setting if needed.
+
+  @param[in,out] MrcData - Include all MRC global data.
+
+  @retval Nothing
+**/
+extern
+void
+UpdateInternalClksOn (
+  IN OUT MrcParameters *const MrcData
+  );
+#endif // TRAD_FLAG
+
+/**
+  This function Shifts the CMD timing.
+  NOTE: ONLY one, ResetDDR or SelfRefresh can be set inside this function
+
+  @param[in,out] MrcData     - Include all MRC global data.
+  @param[in]     Ranks       - Parameter defining the desired global compensation logic
+  @param[in]     offset      - per channel Value to shift picode for
+  @param[in]     ResetDDR    - Do we reset DDR?
+  @param[in]     SelfRefresh - Do we perform Self refresh?
+  @param[in]     UpdateHost  - Determines if MrcData has to be updated
+  @param[in]     SkipTx      - Determines if TX update should be skipped
+                               @todo: SkipTx is NOT USED at this time and we don't skip it anyway
+
+  @retval MrcStatus       - If it succeeds return mrcSuccess
+**/
+extern
+MrcStatus
+ShiftCh2Ch (
+  IN OUT MrcParameters *const MrcData,
+  IN     const U8             Ranks,
+  IN     const U8 *const      offset,
+  IN     U8                   ResetDDR,
+  IN     const U8             SelfRefresh,
+  IN     const U8             UpdateHost,
+  IN     const U8             SkipTx
+  );
+
+/**
+  Programs Delay/Duration for the SenseAmp and MCODT based on RcvEn timing
+  Provide GuardBand > 0 if needed to be more conservative in timing
+  Main goal is to optimize power
+
+  @param[in,out] MrcData          - Include all MRC global data.
+  @param[in]     ChMask           - Channel to work on.
+  @param[in,out] BestDimmOptPoint - Best DIMM Opt settings used to update hardware
+  @param[in]     SkipGRdOdt       - Switch to skip updating CPU ODT
+  @param[in]     SkipDimmOdts     - Switch to skip updating DIMM ODT
+  @param[in]     SkipBestOffsets  - Switch to skip updating Opt settings
+  @param[in]     UpdateHost       - Switch to skip updating MRC host structure
+
+  @retval Nothing
+**/
+extern
+void
+UpdateOdtsValues(
+  IN OUT MrcParameters *const MrcData,
+  IN     U8                   ChMask,
+  IN OUT DimmOptPoint         *BestDimmOptPoint,
+  IN     BOOL                 SkipGRdOdt,
+  IN     BOOL                 SkipDimmOdts,
+  IN     BOOL                 SkipBestOffsets,
+  IN     BOOL                 UpdateHost
+  );
+
+/**
+  Peform Read Voltage Centering in 2D.
+  Note: This function currently only supports param = RdV
+
+  @param[in,out] MrcData     - Include all MRC global data.
+  @param[in,out] MarginByte  - Pointer to Marging Results data structure
+  @param[in]     ChBitMask   - Channel bit mask.
+  @param[in]     Param       - {0:RcvEn, 1:RdT, 2:WrT, 3: WrDqsT, 4:RdV, 5:WrV, 6:WrLevel,
+                                8:WrTBit, 9:RdTBit, 10:RdVBit,
+                                16:RdFan2, 17:WrFan2, 32:RdFan3, 32:WrFan3}
+                                ONLY RdV is allowed in this function
+  @param[in]     EnPerBit    - Option to enable per bit margining
+  @param[in]     ResetPerBit - Option to Reset PerBit Deskew to middle value before byte training
+  @param[in]     LoopCount   - Loop count
+  @param[in]     En2D        - Option to only run center at nominal Vref point
+
+  @retval MrcStatus - If it succeded return mrcSuccess
+**/
+extern
+MrcStatus
+ReadVoltageCentering2D (
+  IN OUT MrcParameters *const MrcData,
+  IN OUT U32                  MarginByte[MAX_RESULT_TYPE][MAX_RANK_IN_CHANNEL][MAX_CHANNEL][MAX_SDRAM_IN_DIMM][MAX_EDGES],
+  IN     U8                   ChBitMask,
+  IN     U8                   Param,
+  IN     U8                   EnPerBit,
+  IN     U8                   ResetPerBit,
+  IN     U8                   LoopCount,
+  IN     U8                   En2D
+  );
+
+#ifdef MRC_DEBUG_PRINT
+/**
+  Prints OptParam values from CRs and Host structure for all ch/Rank/byte as well as
+  the Best optimization value (if requested)
+  OptWrDS = 0
+  OptRdOd = 1
+  OptSCom = 2
+  OptTComp = 3
+  OptTxEq = 4
+  OptRxEq = 5
+  OptRxBias = 6
+  OptDimmOdt = 7
+  OptDimmOdtWr = 8
+  OptDimmRon = 9
+  OptDefault = 10
+
+  @param[in] MrcData   - Include all MRC global data.
+  @param[in] ChMask    - Channel Mask to print the summary for
+  @param[in] RankMask  - Rank Mask to print the summary for (in case Rank is not applicable set RankMask = 0xF)
+  @param[in] OptParam  - Defines the OptParam Offsets. OptDefault reports all parameters
+  @param[in] OptOff    - Structure containg the best offest and margins for the OptParam.
+                         If OptOffsetChByte is not available, NullPtr needs to be passed (void  *NullPtr)
+  @param[in] OptResult - True/False: Whether to print the Best optimization value
+
+  @retval Nothing
+**/
+extern
+void
+ReadOptParamOffsetSum (
+  IN MrcParameters *const MrcData,
+  IN U8                   ChMask,
+  IN U8                   RankMask,
+  IN const U8             OptParam,
+  IN OptOffsetChByte      *OptOff,
+  IN BOOL                 OptResult
+  );
+
+/**
+  Reads OptParam value from CRs and Host structure for a given ch/Rank/byte combination
+  OptParam can be: WrDS, RdOdt, TComp, SComp, RxEq, TxEq, RxBias, DIMM Ron, DIMM RttNom or DIMM RttWr
+
+  @param[in]  MrcData  - Include all MRC global data.
+  @param[out] FinalVal - Pointer to the array consisting of CR value and Host value for a particular
+                         OptParam and given ch/Rank/byte combination.
+  @param[in]  Channel  - Channel index to work on.
+  @param[in]  Rank     - Rank index to work on (valid only for TxEq and RxEq, for others is ignored)
+  @param[in]  Byte     - Byte index to work on.
+  @param[in]  OptParam - Defines the OptParam Offsets. Supported OptParam =
+                         [0: WrDS, 1: RdODT, 2: SComp, 3: TComp, 3: TxEq,
+                          4: RxEq, 5: RxBias, 6: DimmOdt, 7: DimmOdtWr]
+
+  @retval Nothing
+**/
+extern
+void
+ReadOptParamOffset (
+  IN  MrcParameters *const MrcData,
+  OUT S16                  *FinalVal,
+  IN  const U8             Channel,
+  IN  const U8             Rank,
+  IN  const U8             Byte,
+  IN  const U8             OptParam
+  );
+
+/**
+  This function prints the Optimize margin result table
+  e.g: MarginResult[Test][Offset][Channel][Byte][sign]
+
+  @param[in] MrcData     - MRC data structure
+  @param[in] ChMask      - Channels to print
+  @param[in] ResultArray - Array with saved margin results
+  @param[in] TestNum     - Test index
+  @param[in] OffsetsNum  - number of offsets
+  @param[in] MidPoint    - Zero point
+  @param[in] Edges       - 1 edge or 2 edge
+  @param[in] OptParam    - Used to convert to the Opt param string for printing
+  @param[in] Param       - Margin type to be printed.
+  @param[in] PowerLimits - Power limits to print.
+  @param[in] noPrint     - Used to skip printing.
+
+  @retval Nothing
+**/
+extern
+void
+PrintResultTableByte4by24(
+  IN MrcParameters   *MrcData,
+  IN U8              ChMask,
+  IN U16             ResultArray[4][24][MAX_CHANNEL][MAX_SDRAM_IN_DIMM][MAX_EDGES],
+  IN U16             TestNum,
+  IN U8              OffsetsNum,
+  IN U8              MidPoint,
+  IN U8              Edges,
+  IN U8              OptParam,
+  IN U8              Param,
+  IN U16             *PowerLimits,
+  IN BOOL            noPrint
+  );
+
+/**
+  This function prints the Optimize margin result table
+  e.g: calcResultSummary[MAX_CHANNEL][MAX_SDRAM_IN_DIMM]
+
+  @param[in] MrcData           - MRC data structure
+  @param[in] calcResultSummary - The data array [MAX_CHANNEL][MAX_SDRAM_IN_DIMM]
+  @param[in] TestList          - Test list
+  @param[in] NumTest           - Number of test
+  @param[in] NumOffsets        - Number of offsets
+  @param[in] MidPoint          - Middle point
+  @param[in] IncEnds           - Print ends points
+  @param[in] OptParam          - Used to convert to the Opt param string for printing
+  @param[in] OptPower          - Opt Power values to be printed
+  @param[in] Channel           - Channel to print
+  @param[in] Ranks             - Ranks to print
+  @param[in] TrendLine         - Switch to print the trend line
+  @param[in] Nibble            - take low/high bytes
+  @param[in] perCh             - Switch to only print 1 Byte of data
+  @param[in] noPrint           - Boolean used to disable printing of results
+
+  @retval Nothing
+**/
+extern
+void
+PrintCalcResultTableCh(
+  IN MrcParameters *const MrcData,
+  IN OptResultsPerByte    calcResultSummary[MAX_CHANNEL][MAX_SDRAM_IN_DIMM],
+  IN U8                   *TestList,
+  IN U8                   NumTest,
+  IN U8                   NumOffsets,
+  IN S8                   MidPoint,
+  IN BOOL                 IncEnds,
+  IN U8                   OptParam,
+  IN U16                  *OptPower,
+  IN U8                   Channel,
+  IN U8                   Ranks,
+  IN BOOL                 TrendLine,
+  IN U8                   Nibble,
+  IN BOOL                 perCh,
+  IN BOOL                 noPrint
+  );
+
+/**
+  This function prints the Optimize margin result table
+  e.g: calcResultSummary[MAX_CHANNEL][MAX_SDRAM_IN_DIMM]
+
+  @param[in] MrcData           - MRC data structure
+  @param[in] calcResultSummary - The data array [MAX_CHANNEL][MAX_SDRAM_IN_DIMM]
+  @param[in] DimmOptPoints     - add argument and description to function comment
+  @param[in] TestList          - Test list
+  @param[in] NumTest           - Number of test
+  @param[in] NumOffsets        - Number of offsets
+  @param[in] MidPoint          - Middle point
+  @param[in] IncEnds           - Print ends points
+  @param[in] OptParam          - Used to convert to the Opt param string for printing
+  @param[in] Channel           - Channel to print
+  @param[in] Ranks             - Ranks to print
+  @param[in] TrendLine         - Switch to print the trend line
+  @param[in] Nibble            - take low/high bytes
+  @param[in] perCh             - Switch to only print 1 Byte of data
+
+  @retval Nothing
+**/
+extern
+void
+PrintODTResultTable(
+  IN MrcParameters *const MrcData,
+  IN OptResultsPerByte    *calcResultSummary,
+  IN DimmOptPoint         *DimmOptPoints,
+  IN U8                   NumOffsets,
+  IN S8                   MidPoint,
+  IN BOOL                 IncEnds,
+  IN U8                   OptParam,
+  IN U8                   Channel,
+  IN U8                   Ranks,
+  IN BOOL                 TrendLine,
+  IN U8                   Nibble,
+  IN BOOL                 perCh
+  );
+
+/**
+  This function will print out the last margin data collected of the Param passed in.
+  It will print both edges of all the requested bytes, Ranks and Channels.
+  NOTE: The function will not check to see if the Rank/Channel exists.  It will print out the
+  values stored in the margin array regardless of population status.
+
+  @param[in]  MrcData     - Global MRC data.
+  @param[in]  Param       - Parameter of MRC_MarginTypes of which to print the margin.
+  @param[in]  ChannelMask - Bit mask of channels to print.
+  @param[in]  RankMask    - Bit mask of ranks to print.
+  @param[in]  ByteMask    - Bit mask of bytes to print.
+
+  @retval Nothing.
+**/
+void
+MrcPrintLastMargins (
+  IN MrcParameters *const MrcData,
+  IN const U8             Param,
+  IN const U8             ChannelMask,
+  IN const U8             RankMask,
+  IN const U16            ByteMask
+  );
+#endif // MRC_DEBUG_PRINT
+
+/**
+  This function returns the UPM or PWR limit value for the specified parameter
+
+  @param[in] MrcData   - Pointer to MRC global data.
+  @param[in] Param     - Margin type
+  @param[in] LimitType - Type of limit: UpmLimit or PowerLimit
+
+  @retval Returns the UPM or PWR limit
+**/
+extern
+U16
+UpmPwrLimitValue (
+  IN MrcParameters *const MrcData,
+  IN U8                   Param,
+  IN U8                   LimitType
+  );
+
+/**
+  This function will adjust the requested Limit Type of the margin parameter by the signed offset passed in.
+
+  @param[in]  MrcData   - MRC global data.
+  @param[in]  Param     - Margin parameter type to adjust.
+  @param[in]  LimitType - MRC_MARGIN_LIMIT_TYPE to adjust.
+  @param[in]  Offset    - The adjustment value.
+
+  @retval U16 - The new value of Param[MRC_MARGIN_LIMIT_TYPE]
+**/
+U16
+MrcUpdateUpmPwrLimits (
+  IN OUT MrcParameters * const  MrcData,
+  IN U8                         Param,
+  IN U8                         LimitType,
+  IN S8                         Offset
+  );
+
+/**
+  Calculate Power based on Ron and Rodt
+  Includes both static power from Ron/Rodt and dynamic power from Cpad/Cline
+  The power results here are not absolutely correct but give a reasonable estimate (ie: within 2x) with the proper trends
+  Getting absolutely correct power numbers with simple calculations is fairly difficult given the transmission line nature of the system
+  Driver power is calculated as the amount of power drawn from the CPU pin (do we want this to be thermal power instead?) based on the Ron and ODTeff
+              ODTeff is calculated as both the real, resistive ODT on the bus in parallel with the effective impendence of the cap on the line
+              This effective impedance is how AC power is included in the measurements
+              This better models the real system behavior where the power consumed due to dynamic power reduces as termination strength increases
+  ODT power is calculated as a purely DC term based on Ron and Rodt
+  The final power reported back is a scaled version of the CPU and DRAM power
+  This allows one to weight the CPU vs. DRAM power differently in the optimization function based on what is more important
+              CPU power is generally more important since it can be translated into additional performance
+
+  @param[in]  MrcData  - Include all MRC global data.
+  @param[out] Results  - Results of the Power power calculations
+  @param[in]  RonCpu   - RON CPU value (ohm)
+  @param[in]  RonDimm  - RON DIMM value (ohm)
+  @param[in]  Rodtcpu  - RODT CPU value
+  @param[in]  Rodtdram - RODT DRAM value
+  @param[in]  Wodtdram - WODT DRAM value
+
+  @retval Nothing
+**/
+extern
+void
+CalcPower(
+  IN  MrcParameters *MrcData,
+  OUT MrcPower      *Results,
+  IN  U16           RonCpu,
+  IN  U8            RonDimm,
+  IN  U16           Rodtcpu,
+  IN  U16           Rodtdram,
+  IN  U16           Wodtdram
+  );
+
+/**
+  This function fill the input array (e.g array[ch][rank]) with the power calculation
+  per rank/ch for current sys. setting.
+
+  @param[in]     MrcData   - MRC data struct;
+  @param[in,out] PwrChRank - Array to fill;
+
+  @retval Nothing
+**/
+extern
+void
+CalcSysPower (
+  IN     MrcParameters *const MrcData,
+  IN OUT MrcPower             PwrChRank[MAX_CHANNEL][MAX_RANK_IN_CHANNEL]
+  );
+
+/**
+  Calculate Power Trend line based on Cpu and Dimms Ron and Odt's
+
+  @param[in]     MrcData       - Include all MRC global data.
+  @param[in]     Channel       - Channel to work on.
+  @param[in]     DimmMask      - DIMMs to work on.
+  @param[in,out] DimmOptPoints - Structure of all the DIMM ODT optimal settings.
+  @param[in]     Points2calc   - Data to build the trendline on.
+  @param[in]     ArrayLength   - Array length of Points2calc.
+  @param[in]     LenMargin     - The length of inputMargins we are optimizing (0 - LenMargin -1).
+  @param[in]     TestList      - TestList index in Points2cal: WrVref, RdVref, WrT, RdT
+  @param[in]     Scale         - Scale to apply per test to Points2calc
+  @param[in]     TestListSize  - Size of TestList/Scale
+  @param[in]     PwrCalc1d     - Determines if the power test is 1-D or 2-D.
+  @param[in]     PWRTrendSlope - Determines how aggressive the T-line will be.(0%-100%)
+
+  @retval Nothing
+**/
+extern
+void
+CalcPowerTrend(
+  IN     MrcParameters   *MrcData,
+  IN     U8              Channel,
+  IN     U8              DimmMask,
+  IN OUT void            *DimmOptPoints,
+  IN     void            *Points2calc,
+  IN     U8              ArrayLength,
+  IN     U8              LenMargin,
+  IN     U8              *TestList,
+  IN     U8              *Scale,
+  IN     U8              TestListSize,
+  IN     BOOL            PwrCalc1d,
+  IN     U8              PWRTrendSlope
+  );
+
+/**
+  This function returns the Actual Cpu Driver Impedance (1 segment) in ohm.
+
+  @param[in] MrcData - Pointer to MRC global data.
+  @param[in] Offset  - Vref Offset (+-8).
+
+  @retval Returns the CPU driver impedance value (for 1 segment)
+**/
+extern
+U16
+CalcDrvImp (
+  IN MrcParameters *const MrcData,
+  IN S8                   Offset
+  );
+
+/**
+  This function returns the Actual Cpu Odt termination in ohm.
+
+  @param[in] MrcData - Pointer to MRC global data.
+  @param[in] Offset  - Vref Offset (+-16).
+
+  @retval Returns the Odt termination value.
+**/
+extern
+U16
+CalcRdOdt (
+  IN MrcParameters *const MrcData,
+  IN S8                   Offset
+  );
+
+/**
+  Calculate Power for the selected Opt param based on
+
+  @param[in] MrcData     - Include all MRC global data.
+  @param[in] Channel     - Channel to work on
+  @param[in] Rank        - Rank to work on
+  @param[in] Byte        - Byte to work on
+  @param[in] OptParam    - The Opt Parameter to work on
+  @param[in] Offset      - The Offset to work on
+  @param[in] CurrentComp - The current Comp code for OptParam
+  @param[in] ReadHost    - Switch to read current offset and CompCode from Host structure.
+
+  @retval Calc power in mW
+**/
+extern
+U32
+CalcOptPower(
+  IN MrcParameters   *MrcData,
+  IN U8              Channel,
+  IN U8              Rank,
+  IN U8              Byte,
+  IN U8              OptParam,
+  IN S8              Offset,
+  IN S8              CurrentComp,
+  IN BOOL            ReadHost
+  );
+
+/**
+  This function implements Write Slew Rate training.
+  Optimize Write Slew Rate for performance & power
+
+  @param[in] MrcData - Include all MRC global data.
+
+  @retval mrcSuccess
+**/
+extern
+MrcStatus
+MrcWriteSlewRate (
+  IN MrcParameters *const MrcData
+  );
+
+/**
+  This function prints out the Margin eye diagram for ParamT/ParamV.
+
+
+  @param[in] MrcData - Include all MRC global data.
+  @param[in] Channel - Channel to margin.
+  @param[in] Ranks   - Bit mask of Ranks to margin.
+  @param[in] ParamT  - Time parameter to margin.
+  @param[in] ParamV  - Voltage parameter to margin.
+  @param[in] Start   - Starting point for margining.
+  @param[in] Stop    - Stopping point for margining.
+  @param[in] Repeats - Number of times to repeat the test to average out any noise.
+  @param[in] NoPrint - Switch to skip printing.
+
+  @retval Nothing
+**/
+extern
+void
+EyeMargin (
+  IN MrcParameters *const MrcData,
+  IN U8                   Channel,
+  IN U8                   Ranks,
+  IN U8                   ParamT,
+  IN U8                   ParamV,
+  IN S8                   Start,
+  IN S8                   Stop,
+  IN U16                  SearchLimits,
+  IN U8                   LoopCount,
+  IN U8                   Repeats,
+  IN BOOL                 NoPrint
+  );
+
+/**
+  This function optimize the digital offsets by reducing the digital
+  offset and apply the difference to the global one.
+
+  @param[in] MrcData    - Include all MRC global data.
+  @param[in] Param      - Parameter defining the desired digital compensation offset.
+  @param[in] UpdateHost - Decides if MrcData is to be updated.
+
+  @retval The new comp value.
+**/
+extern
+U32
+OptimizeCompOffset (
+  IN MrcParameters *const MrcData,
+  IN const U8             Param,
+  IN const U8             UpdateHost
+  );
+
+/**
+  This function implements the Write Drive Strength optimization for performance and power.
+
+  @param[in] MrcData    - Include all MRC global data.
+  @param[in] ChBitMask  - Channel mask to perform training on the Opt Param test list.
+  @param[in] RecenterLC - The loopcount for Write Time recentering.
+  @param[in] OptParamLC - The loopcount for training the Opt Param test list.
+  @param[in] Recenter   - Switch which determines if the step recenters Write Timing.
+
+  @retval If it succeeds return mrcSuccess
+**/
+extern
+MrcStatus
+TrainWriteDriveStrength (
+  IN MrcParameters *const MrcData,
+  IN const U8             ChBitMask,
+  IN const U8             RecenterLC,
+  IN const U8             OptParamLC,
+  IN const BOOL           Recenter
+  );
+
+/**
+  This step performs Comp Offset optimization on the param list defined in this function.
+
+  @param[in] MrcData - Include all MRC global data.
+
+  @retval MrcStatus - mrcSuccess
+**/
+extern
+MrcStatus
+MrcOptimizeComp (
+  IN MrcParameters *const MrcData
+  );
+
+/**
+  This function calculates the percent of power saving from the power optimization steps and
+  updates the proper registers in the PCU.  To get the correct base line for this calculation,
+  this routing needs to run first time early in the training in order to update the MrcStruct
+  with the base line.  After the power training steps, it will run again to get the actual
+  percent of power saving.
+
+  @param[in] MrcData - Include all MRC global data.
+
+  @retval MrcStatus - mrcSuccess
+
+**/
+extern
+MrcStatus
+MrcPowerSavingMeter (
+  IN MrcParameters *const MrcData
+  );
+
+#endif // _MrcCrosser_h_
diff --git a/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcDdr3.h b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcDdr3.h
new file mode 100644
index 0000000..a1ce4e1
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcDdr3.h
@@ -0,0 +1,449 @@
+/** @file
+  This file includes all the DDR3 specific characteristic definitions.
+
+@copyright
+  Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved.
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement.
+
+**/
+#ifndef _MrcDdr3_h_
+#define _MrcDdr3_h_
+
+#include "MrcTypes.h"
+#include "MrcApi.h"
+#include "McAddress.h"
+#include "MrcCommon.h"
+#include "MrcDdr3Registers.h"
+#include "MrcIoControl.h"
+#include "MrcOem.h"
+#include "MrcPowerModes.h"
+#include "MrcRefreshConfiguration.h"
+
+#pragma pack (push, 1)
+///
+/// in write leveling mode Rtt_Nom = Rtt_Wr
+///
+typedef struct {
+  U8  RttWr;  ///< Wa - Write ODT on active rank
+  U8  RttNom; ///< Wp - ODT on one of the ranks on passive DIMM during Write operation
+} TOdtValue;
+
+typedef enum {
+  oi1DPC1R  = 0,
+  oi1DPC2R,
+  oi2DPC1R1R,
+  oi2DPC1R2R,
+  oi2DPC2R1R,
+  oi2DPC2R2R,
+  oiNotValid
+} TOdtIndex;
+
+typedef enum {
+  ODIC_RZQ_6,
+  ODIC_RZQ_7,
+  ODIC_RSVD_0,
+  ODIC_RSVD_1
+} TOutputDriverImpedanceControl;
+
+///
+/// ZQ Calibration types
+///
+typedef enum {
+  MRC_ZQ_INIT,  ///< DDR3: ZQCL with tZQinit, LPDDR3: ZQ Init  with tZQinit
+  MRC_ZQ_LONG,  ///< DDR3: ZQCL with tZQoper, LPDDR3: ZQ Long  with tZQCL
+  MRC_ZQ_SHORT, ///< DDR3: ZQCS with tZQCS,   LPDDR3: ZQ Short with tZQCS
+  MRC_ZQ_RESET  ///< DDR3: not used,          LPDDR3: ZQ Reset with tZQreset
+} MrcZqType;
+
+#ifndef tZQinit
+#define tZQinit                     (512)   ///< define the tZQinit as define in jedec spec
+#endif
+
+#ifndef tWLMRD
+#define tWLMRD                      (40)    ///< First DQS/DQS# rising edge after write leveling mode is programmed.
+#endif
+
+#ifndef tWLOE
+#define tWLOE                       (40)    ///< Write leveling output error the time is 2ns ~ 2 nCK
+#endif
+
+#ifndef tZQCS_TIME
+#define tZQCS_TIME                  (64)    ///< jedec timing
+#endif
+
+#define MRC_DDR3_SDRAM_TYPE_NUMBER  (0x0B)  ///< use to know the DDR type that data came from Jedec SPD byte 2
+#define MRC_UDIMM_TYPE_NUMBER       (0x02)  ///< use to know if the DIMM type is UDIMM define in Jedec SPD byte 3
+#define MRC_SOIMM_TYPE_NUMBER       (0x03)  ///< use to know if the DIMM type is SO-DIMM define in Jedec SPD byte 3
+#define MRC_SDRAM_DEVICE_WIDTH_8    (0x1)   ///< use to know if the DDRAM is 8 bits width
+#define MRC_SDRAM_DEVICE_WIDTH_16   (0x2)   ///< use to know if the DDRAM is 16 bits width
+#define MRC_PRIMARY_BUS_WIDTH_64    (0x3)   ///< use to know if the DIMM primary bus width is not 64
+#define MRC_CL_MAX_OFFSET           (0xF)   ///< in the spd data include cl from bit 0 to bit 15 each bit represent different support CL
+#define MRC_CL_IN_NANO_SEC          (20)    ///< define the nax CL value in nano second
+
+/**
+@brief
+  this function reverses MA and BA bits for Rank1
+
+  @param[in] BA              - MRS command to be sent
+  @param[in] MA              - Value to be sent
+
+  @retval Proper MA and BA BITS.
+**/
+extern
+U32
+MrcMirror (
+  IN U8              BA,
+  IN U16             MA
+  );
+
+/**
+@brief
+  this function writes to CADB
+
+  @param[in] MrcData         - include all the MRC data
+  @param[in] Channel         - Channel to send command to
+  @param[in] RankMask        - Rank mask for which command will be sent to.
+  @param[in] CMD             - 0: MRS, 1: REF, 2: PRE, 3: ACT, 4: WR, 5: RD, 6: ZQ, 7: NOP
+  @param[in] BA              - MRS command to be sent
+  @param[in] MA              - Value to be sent
+  @param[in] Delay           - Delay in Dclocks
+
+  @retval MrcStatus
+**/
+extern
+MrcStatus
+MrcWriteCADBCmd (
+  IN MrcParameters *const MrcData,
+  IN const U8             Channel,
+  IN const U8             RankMask,
+  IN const U8             CMD,
+  IN const U8             BA,
+  IN const U16 *const     MA,
+  IN const U8             Delay
+  );
+
+/**
+@brief
+  This function sends the proper MRS command for specific ranks as indicated by RankMask
+
+  @param[in] MrcData         - include all the MRC data
+  @param[in] Channel         - Channel to send command to
+  @param[in] RankMask        - Rank mask for which command will be sent to
+  @param[in] MR              - MRS command to be sent
+  @param[in] DimmValue       - Dimm Values to be sent
+
+  @retval MrcStatus
+**/
+extern
+MrcStatus
+MrcWriteMRSAll (
+  IN MrcParameters *const MrcData,
+  IN const U8             Channel,
+  IN const U8             RankMask,
+  IN const U8             MR,
+  IN const U16 *const     DimmValue
+  );
+
+/**
+@brief
+  This function sends the proper MRS command for specific ranks as indicated by RankMask
+
+  @param[in] MrcData         - Include all the MRC data
+  @param[in] Channel         - Channel to send command to
+  @param[in] RankMask        - Rank mask for which command will be sent to
+  @param[in] MR              - MRS command to be sent
+  @param[in] Value           - Value to be sent
+
+  @retval MrcStatus
+**/
+extern
+MrcStatus
+MrcWriteMRS (
+  IN MrcParameters *const MrcData,
+  IN const U8             Channel,
+  IN const U8             RankMask,
+  IN const U8             MR,
+  IN const U16            Value
+  );
+
+/**
+@brief
+  Issue ZQ calibration command on all ranks.
+  When done, wait appropriate delay depending on the ZQ type.
+
+  @param[in] MrcData         - include all the MRC data
+  @param[in] chBitMask       - Channel bit mask to be sent to.
+  @param[in] ZqType          - Type of ZQ Calibration: see MrcZqType enum
+
+  @retval MrcStatus - mrcSuccess if passes, otherwise an error status
+**/
+extern
+MrcStatus
+MrcIssueZQ (
+  IN MrcParameters *const MrcData,
+  IN const U8             chBitMask,
+  IN const MrcZqType      ZqType
+  );
+
+/**
+@brief
+  This function writes the MR2 register for all the ranks and channels
+
+  @param[in, out] MrcData    - general data
+  @param[in]      Pasr       - Partial array self refresh bit A0-A2
+
+  @retval MrcStatus - mrcSuccess if passes, otherwise an error status
+**/
+extern
+MrcStatus
+MrcSetMR2 (
+  IN OUT MrcParameters *const MrcData,
+  IN     const U8             Pasr
+  );
+
+/**
+@brief
+  This function writes the MR3 register for all the ranks and channels
+
+  @param[in] MrcData         - include all the MRC data
+  @param[in] MPRLoc          - MPR Location bit A0-A1
+  @param[in] Mpr             - MPR bit A2
+
+  @retval MrcStatus - mrcSuccess if passes, otherwise an error status
+**/
+extern
+MrcStatus
+MrcSetMR3 (
+  IN MrcParameters *const MrcData,
+  IN const U8             MPRLoc,
+  IN const U8             Mpr
+  )
+;
+
+/**
+@brief
+  This function writes the MR1 register for all the ranks and channels
+
+  @param[in, out] MrcData         - include all the MRC data
+  @param[in]      DLLEnable       - DLL enable bit A0
+  @param[in]      Odic            - Output driver impedance control A5, A1
+  @param[in]      AdditiveLatency - Additive latency bit A3-A4
+  @param[in]      WlEnable        - Write leveling enable bit A7
+  @param[in]      Tdqs            - TDQS enable bit A11
+  @param[in]      Qoff            - Qoff bit A12
+
+  @retval MrcStatus - mrcSuccess if passes, otherwise an error status
+**/
+extern
+MrcStatus
+MrcSetMR1 (
+  IN OUT MrcParameters *const MrcData,
+  IN     const U8             DLLEnable,
+  IN     const U8             Odic,
+  IN     const U8             AdditiveLatency,
+  IN     const U8             WlEnable,
+  IN     const U8             Tdqs,
+  IN     const U8             Qoff
+  );
+
+/**
+@brief
+  This function writes the MR0 register for all the ranks
+
+  @param[in, out] MrcData         - include all the MRC data
+  @param[in]      CommandControl  - include the command control params
+  @param[in]      BurstLength     - Burst length bit A0-A1
+  @param[in]      ReadBurstType   - Read burst type bit A3
+  @param[in]      TestMode        - Test mode type bit A7
+  @param[in]      DllReset        - DLL reset bit A8
+
+  @retval MrcStatus - mrcSuccess if passes, otherwise an error status
+**/
+extern
+MrcStatus
+MrcSetMR0 (
+  IN OUT MrcParameters *const MrcData,
+  IN     const U8             Bl,
+  IN     const U8             Rbt,
+  IN     const U8             Tm,
+  IN     const U8             Dll
+  );
+
+/**
+@brief
+  This function return tWLO time. this time is Write leveling output delay.
+
+  @param[in] Frequency       - MC frequency.
+
+  @retval tWLO timein nCK.
+**/
+extern
+U32
+GetTwloTime (
+  IN const MrcFrequency  Frequency
+  );
+
+/**
+@brief
+  This funtion returns the odt table index for the given Dimm/Channel.
+
+  @param[in] MrcData         - Include all the mrc global data.
+  @param[in] Channel         - Channel to work on.
+  @param[in] Dimm            - Rank to work on.
+
+  @retval OdtValue - iThe pointer to the relevant Odt values.
+**/
+extern
+TOdtValue *
+GetOdtTableIndex (
+  IN MrcParameters *const MrcData,
+  IN const U8             Channel,
+  IN const U8             Dimm
+  );
+
+/**
+@brief
+  This funtion takes the MR1 register value and updates the odt value
+ inside the register.
+
+  @param[in] MrcData          - Include all the MRC general data.
+  @param[in] OdtValue         - Selected odt index.
+  @param[in] Ddr3ModeRegister - Register to update.
+
+  @retval Ddr3ModeRegister  - Updated register
+**/
+extern
+DDR3_MODE_REGISTER_1_STRUCT
+UpdateRttNomValue (
+  IN MrcParameters *const        MrcData,
+  IN const U8                    OdtValue,
+  IN DDR3_MODE_REGISTER_1_STRUCT Register
+  );
+
+/**
+@brief
+  This function updates the Rtt value in the MR2 value passed in.
+
+  @param[in] MrcData          - Include all the MRC general data.
+  @param[in] OdtValue         - Selected odt index.
+  @param[in] Ddr3ModeRegister - Register to update.
+
+  @retval Ddr3ModeRegister - Updated MR2 register
+**/
+extern
+DDR3_MODE_REGISTER_2_STRUCT
+UpdateRttWrValue (
+  IN MrcParameters *const        MrcData,
+  IN const U8                    OdtValue,
+  IN DDR3_MODE_REGISTER_2_STRUCT Ddr3ModeRegister
+  );
+
+/**
+@brief
+  this funtion select the ODT table according OEM/USER decision.
+  In the MRC have 4 table type Mb,Dt,User1,User2.
+  User1,User2 use as internal usage.
+
+  @param[in] MrcData         - Include all the MRC general data.
+  @param[in] Dimm            - selected DIMM.
+  @param[in] OdtIndex        - selected odt index.
+
+  @retval TOdtValue * - Pointer to the relevant table.
+                        The return value is NULL if the table could
+                        not be found
+**/
+extern
+TOdtValue *
+SelectTable (
+  IN MrcParameters *const MrcData,
+  IN const U8             Dimm,
+  IN const TOdtIndex      OdtIndex
+  );
+
+#ifdef ULT_FLAG
+
+/**
+@brief
+  Issue LPDDR MRW (Mode Register Write) command using MRH (Mode Register Handler).
+
+  @param[in] MrcData - Include all MRC global data.
+  @param[in] Channel - the channel to work on
+  @param[in] Rank    - the rank to work on
+  @param[in] Address - MRW address
+  @param[in] Data    - MRW Data
+  @param[in] InitMrw - when TRUE, command is stretched (used before CA training is done)
+  @param[in] ChipSelect2N - when TRUE, use 2N stretch mode for CS (used before CA training is done)
+
+  @retval mrcSuccess    - MRW was sent successfully
+  @retval mrcDeviceBusy - timed out waiting for MRH
+**/
+extern
+MrcStatus
+MrcIssueMrw (
+  IN MrcParameters *const MrcData,
+  IN U32                  Channel,
+  IN U32                  Rank,
+  IN U32                  Address,
+  IN U32                  Data,
+  IN BOOL                 InitMrw,
+  IN BOOL                 ChipSelect2N
+  );
+
+/**
+@brief
+  Issue LPDDR MRR (Mode Register Read) command using MRH (Mode Register Handler).
+  Use DQ mapping array to deswizzle the MR data.
+
+  @param[in]  MrcData - Include all MRC global data.
+  @param[in]  Channel - the channel to work on
+  @param[in]  Rank    - the rank to work on
+  @param[in]  Address - MRR address
+  @param[out] Data    - MRR Data array per SDRAM device
+
+  @retval mrcSuccess    - MRR was executed successfully
+  @retval mrcDeviceBusy - timed out waiting for MRH
+**/
+extern
+MrcStatus
+MrcIssueMrr (
+  IN MrcParameters *const MrcData,
+  IN U32                  Channel,
+  IN U32                  Rank,
+  IN U32                  Address,
+  OUT U8                  Data[4]
+  );
+
+/**
+@brief
+  Issue LPDDR PRECHARGE ALL command using CADB.
+
+  @param[in]  MrcData   - Include all MRC global data.
+  @param[in]  Channel   - The channel to work on
+  @param[in]  RankMask  - The rank(s) to work on
+
+  @retval none
+**/
+void
+MrcIssuePrechargeAll (
+  IN MrcParameters *const MrcData,
+  IN const U8             Channel,
+  IN const U8             RankMask
+  );
+
+#endif // ULT_FLAG
+
+#pragma pack (pop)
+#endif // _MrcDdr3_h_
diff --git a/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcDdr3Registers.h b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcDdr3Registers.h
new file mode 100644
index 0000000..7041495
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcDdr3Registers.h
@@ -0,0 +1,249 @@
+/** @file
+  Include all the DDR3 register definitions.
+
+@copyright
+  Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement.
+**/
+#ifndef _MrcDdr3Registers_h_
+#define _MrcDdr3Registers_h_
+
+#pragma pack(push, 1)
+
+typedef union {
+  struct {
+    U16 BurstLength                 : 2;    ///< Bits 0:1
+    U16 CasLatencyLow               : 1;    ///< Bits 2:2
+    U16 ReadBurstType               : 1;    ///< Bits 3:3
+    U16 CasLatencyHigh              : 3;    ///< Bits 4:6
+    U16 TestMode                    : 1;    ///< Bits 7:7
+    U16 DllReset                    : 1;    ///< Bits 8:8
+    U16 WriteRecovery               : 3;    ///< Bits 9:11
+    U16 PrechargePdDll              : 1;    ///< Bits 12:12
+    U16                             : 3;    ///< Bits 13:15
+  } Bits;
+  U16 Data;
+  U8  Data8[2];
+} DDR3_MODE_REGISTER_0_STRUCT;
+
+typedef union {
+  struct {
+    U16 DllEnable                   : 1;    ///< Bits 0:0
+    U16 ODImpedanceLow              : 1;    ///< Bits 1:1
+    U16 OdtRttValueLow              : 1;    ///< Bits 2:2
+    U16 AdditiveLatency             : 2;    ///< Bits 3:4
+    U16 ODImpedanceHigh             : 1;    ///< Bits 5:5
+    U16 OdtRttValueMid              : 1;    ///< Bits 6:6
+    U16 WriteLeveling               : 1;    ///< Bits 7:7
+    U16                             : 1;    ///< Bits 8:8
+    U16 OdtRttValueHigh             : 1;    ///< Bits 9:9
+    U16                             : 1;    ///< Bits 10:10
+    U16 Tdqs                        : 1;    ///< Bits 11:11
+    U16 Qoff                        : 1;    ///< Bits 12:12
+    U16                             : 3;    ///< Bits 13:15
+  } Bits;
+  U16 Data;
+  U8  Data8[2];
+} DDR3_MODE_REGISTER_1_STRUCT;
+
+typedef union {
+  struct {
+    U16 PartialArraySR              : 3;    ///< Bits 0:2
+    U16 CasWriteLatency             : 3;    ///< Bits 3:5
+    U16 AutoSelfRefresh             : 1;    ///< Bits 6:6
+    U16 SelfRefreshTemp             : 1;    ///< Bits 7:7
+    U16                             : 1;    ///< Bits 8:8
+    U16 DynamicOdt                  : 2;    ///< Bits 9:10
+    U16                             : 5;    ///< Bits 11:15
+  } Bits;
+  U16 Data;
+  U8  Data8[2];
+} DDR3_MODE_REGISTER_2_STRUCT;
+
+typedef union {
+  struct {
+    U16 MprLocation                 : 2;    ///< Bits 0:1
+    U16 MprOperation                : 1;    ///< Bits 2:2
+    U16                             : 13;   ///< Bits 3:15
+  } Bits;
+  U16 Data;
+  U8  Data8[2];
+} DDR3_MODE_REGISTER_3_STRUCT;
+
+///
+/// MR0 register
+///
+#define DDR3_MODE_REGISTER_0_BL_OFF     (0)
+#define DDR3_MODE_REGISTER_0_BL_WID     (2)
+#define DDR3_MODE_REGISTER_0_BL_MSK     (3)
+#define DDR3_MODE_REGISTER_0_BL_MAX     (3)
+#define DDR3_MODE_REGISTER_0_BL_DEF     (0)
+
+#define DDR3_MODE_REGISTER_0_CL_A2_OFF  (2)
+#define DDR3_MODE_REGISTER_0_CL_A2_WID  (1)
+#define DDR3_MODE_REGISTER_0_CL_A2_MSK  (1)
+#define DDR3_MODE_REGISTER_0_CL_A2_MAX  (1)
+#define DDR3_MODE_REGISTER_0_CL_A2_DEF  (0)
+
+#define DDR3_MODE_REGISTER_0_RBT_OFF    (3)
+#define DDR3_MODE_REGISTER_0_RBT_WID    (1)
+#define DDR3_MODE_REGISTER_0_RBT_MSK    (1)
+#define DDR3_MODE_REGISTER_0_RBT_MAX    (1)
+#define DDR3_MODE_REGISTER_0_RBT_DEF    (0)
+
+#define DDR3_MODE_REGISTER_0_CL_OFF     (4)
+#define DDR3_MODE_REGISTER_0_CL_WID     (3)
+#define DDR3_MODE_REGISTER_0_CL_MSK     (7)
+#define DDR3_MODE_REGISTER_0_CL_MAX     (7)
+#define DDR3_MODE_REGISTER_0_CL_DEF     (0)
+
+#define DDR3_MODE_REGISTER_0_TM_OFF     (7)
+#define DDR3_MODE_REGISTER_0_TM_WID     (1)
+#define DDR3_MODE_REGISTER_0_TM_MSK     (1)
+#define DDR3_MODE_REGISTER_0_TM_MAX     (1)
+#define DDR3_MODE_REGISTER_0_TM_DEF     (0)
+
+#define DDR3_MODE_REGISTER_0_DLL_OFF    (8)
+#define DDR3_MODE_REGISTER_0_DLL_WID    (1)
+#define DDR3_MODE_REGISTER_0_DLL_MSK    (1)
+#define DDR3_MODE_REGISTER_0_DLL_MAX    (1)
+#define DDR3_MODE_REGISTER_0_DLL_DEF    (0)
+
+#define DDR3_MODE_REGISTER_0_WR_OFF     (9)
+#define DDR3_MODE_REGISTER_0_WR_WID     (3)
+#define DDR3_MODE_REGISTER_0_WR_MSK     (7)
+#define DDR3_MODE_REGISTER_0_WR_MAX     (7)
+#define DDR3_MODE_REGISTER_0_WR_DEF     (0)
+
+#define DDR3_MODE_REGISTER_0_PPD_OFF    (12)
+#define DDR3_MODE_REGISTER_0_PPD_WID    (1)
+#define DDR3_MODE_REGISTER_0_PPD_MSK    (1)
+#define DDR3_MODE_REGISTER_0_PPD_MAX    (1)
+#define DDR3_MODE_REGISTER_0_PPD_DEF    (0)
+
+///
+/// MR1 register
+///
+#define DDR3_MODE_REGISTER_1_DLL_OFF        (0)
+#define DDR3_MODE_REGISTER_1_DLL_WID        (1)
+#define DDR3_MODE_REGISTER_1_DLL_MSK        (1)
+#define DDR3_MODE_REGISTER_1_DLL_MAX        (1)
+#define DDR3_MODE_REGISTER_1_DLL_DEF        (0)
+
+#define DDR3_MODE_REGISTER_1_D_I_C_A1_OFF   (1)
+#define DDR3_MODE_REGISTER_1_D_I_C_A1_WID   (1)
+#define DDR3_MODE_REGISTER_1_D_I_C_A1_MSK   (1)
+#define DDR3_MODE_REGISTER_1_D_I_C_A1_MAX   (1)
+#define DDR3_MODE_REGISTER_1_D_I_C_A1_DEF   (0)
+
+#define DDR3_MODE_REGISTER_1_Rtt_Nom_A2_OFF (2)
+#define DDR3_MODE_REGISTER_1_Rtt_Nom_A2_WID (1)
+#define DDR3_MODE_REGISTER_1_Rtt_Nom_A2_MSK (1)
+#define DDR3_MODE_REGISTER_1_Rtt_Nom_A2_MAX (1)
+#define DDR3_MODE_REGISTER_1_Rtt_Nom_A2_DEF (0)
+
+#define DDR3_MODE_REGISTER_1_AL_OFF         (3)
+#define DDR3_MODE_REGISTER_1_AL_WID         (2)
+#define DDR3_MODE_REGISTER_1_AL_MSK         (3)
+#define DDR3_MODE_REGISTER_1_AL_MAX         (3)
+#define DDR3_MODE_REGISTER_1_AL_DEF         (0)
+
+#define DDR3_MODE_REGISTER_1_D_I_C_A5_OFF   (5)
+#define DDR3_MODE_REGISTER_1_D_I_C_A5_WID   (1)
+#define DDR3_MODE_REGISTER_1_D_I_C_A5_MSK   (1)
+#define DDR3_MODE_REGISTER_1_D_I_C_A5_MAX   (1)
+#define DDR3_MODE_REGISTER_1_D_I_C_A5_DEF   (0)
+
+#define DDR3_MODE_REGISTER_1_Rtt_Nom_A6_OFF (6)
+#define DDR3_MODE_REGISTER_1_Rtt_Nom_A6_WID (1)
+#define DDR3_MODE_REGISTER_1_Rtt_Nom_A6_MSK (1)
+#define DDR3_MODE_REGISTER_1_Rtt_Nom_A6_MAX (1)
+#define DDR3_MODE_REGISTER_1_Rtt_Nom_A6_DEF (0)
+
+#define DDR3_MODE_REGISTER_1_LEVEL_OFF      (7)
+#define DDR3_MODE_REGISTER_1_LEVEL_WID      (1)
+#define DDR3_MODE_REGISTER_1_LEVEL_MSK      (1)
+#define DDR3_MODE_REGISTER_1_LEVEL_MAX      (1)
+#define DDR3_MODE_REGISTER_1_LEVEL_DEF      (0)
+
+#define DDR3_MODE_REGISTER_1_Rtt_Nom_A9_OFF (9)
+#define DDR3_MODE_REGISTER_1_Rtt_Nom_A9_WID (1)
+#define DDR3_MODE_REGISTER_1_Rtt_Nom_A9_MSK (1)
+#define DDR3_MODE_REGISTER_1_Rtt_Nom_A9_MAX (1)
+#define DDR3_MODE_REGISTER_1_Rtt_Nom_A9_DEF (0)
+
+#define DDR3_MODE_REGISTER_1_TDQS_OFF       (11)
+#define DDR3_MODE_REGISTER_1_TDQS_WID       (1)
+#define DDR3_MODE_REGISTER_1_TDQS_MSK       (1)
+#define DDR3_MODE_REGISTER_1_TDQS_MAX       (1)
+#define DDR3_MODE_REGISTER_1_TDQS_DEF       (0)
+
+#define DDR3_MODE_REGISTER_1_Qoff_OFF       (12)
+#define DDR3_MODE_REGISTER_1_Qoff_WID       (1)
+#define DDR3_MODE_REGISTER_1_Qoff_MSK       (1)
+#define DDR3_MODE_REGISTER_1_Qoff_MAX       (1)
+#define DDR3_MODE_REGISTER_1_Qoff_DEF       (0)
+
+///
+/// MR2 register
+///
+#define DDR3_MODE_REGISTER_2_PASR_OFF   (0)
+#define DDR3_MODE_REGISTER_2_PASR_WID   (3)
+#define DDR3_MODE_REGISTER_2_PASR_MSK   (7)
+#define DDR3_MODE_REGISTER_2_PASR_MAX   (7)
+#define DDR3_MODE_REGISTER_2_PASR_DEF   (0)
+
+#define DDR3_MODE_REGISTER_2_CWL_OFF    (3)
+#define DDR3_MODE_REGISTER_2_CWL_WID    (3)
+#define DDR3_MODE_REGISTER_2_CWL_MSK    (7)
+#define DDR3_MODE_REGISTER_2_CWL_MAX    (7)
+#define DDR3_MODE_REGISTER_2_CWL_DEF    (0)
+
+#define DDR3_MODE_REGISTER_2_ASR_OFF    (6)
+#define DDR3_MODE_REGISTER_2_ASR_WID    (1)
+#define DDR3_MODE_REGISTER_2_ASR_MSK    (1)
+#define DDR3_MODE_REGISTER_2_ASR_MAX    (1)
+#define DDR3_MODE_REGISTER_2_ASR_DEF    (0)
+
+#define DDR3_MODE_REGISTER_2_STR_OFF    (7)
+#define DDR3_MODE_REGISTER_2_STR_WID    (1)
+#define DDR3_MODE_REGISTER_2_STR_MSK    (1)
+#define DDR3_MODE_REGISTER_2_STR_MAX    (1)
+#define DDR3_MODE_REGISTER_2_STR_DEF    (0)
+
+#define DDR3_MODE_REGISTER_2_Rtt_WR_OFF (9)
+#define DDR3_MODE_REGISTER_2_Rtt_WR_WID (2)
+#define DDR3_MODE_REGISTER_2_Rtt_WR_MSK (3)
+#define DDR3_MODE_REGISTER_2_Rtt_WR_MAX (3)
+#define DDR3_MODE_REGISTER_2_Rtt_WR_DEF (0)
+
+///
+/// MR3 register
+///
+#define DDR3_MODE_REGISTER_3_MPR_LOC_OFF  (0)
+#define DDR3_MODE_REGISTER_3_MPR_LOC_WID  (2)
+#define DDR3_MODE_REGISTER_3_MPR_LOC_MSK  (3)
+#define DDR3_MODE_REGISTER_3_MPR_LOC_MAX  (3)
+#define DDR3_MODE_REGISTER_3_MPR_LOC_DEF  (0)
+
+#define DDR3_MODE_REGISTER_3_MPR_OFF      (2)
+#define DDR3_MODE_REGISTER_3_MPR_WID      (1)
+#define DDR3_MODE_REGISTER_3_MPR_MSK      (1)
+#define DDR3_MODE_REGISTER_3_MPR_MAX      (1)
+#define DDR3_MODE_REGISTER_3_MPR_DEF      (0)
+
+#pragma pack (pop)
+#endif
diff --git a/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcGlobal.h b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcGlobal.h
new file mode 100644
index 0000000..0264c6a
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcGlobal.h
@@ -0,0 +1,993 @@
+/** @file
+  This file includes all the data structures that the MRC considers "global data".
+
+@copyright
+  Copyright (c) 1999 - 2013 Intel Corporation. All rights reserved.
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement
+**/
+#ifndef _MrcGlobal_h_
+#define _MrcGlobal_h_
+#pragma pack (push, 1)
+
+#include "MrcTypes.h"
+#include "MrcApi.h"
+#include "MrcOemDebugPrint.h"
+#include "MrcRmtData.h"
+#include "MrcSpdData.h"
+#include "McAddress.h"
+
+///
+///***************************************************
+/// Structures common to all "global data" elements.
+///***************************************************
+///
+typedef U8 MrcIteration;
+#define MRC_ITERATION_MAX ((1 << ((sizeof (MrcIteration) * 8) - 1)) + ((1 << ((sizeof (MrcIteration) * 8) - 1)) - 1))
+
+#define MRC_NUMBER_UPM_PWR_RETRAIN_MARGINS (9)
+
+typedef struct {
+  ///
+  ///< Thermal Options
+  ///
+  U8  EnableExtts;
+  U8  EnableCltm;
+  U8  EnableOltm;
+  U8  EnablePwrDn;
+#ifdef ULT_FLAG
+  U8  EnablePwrDnLpddr;
+#endif // ULT_FLAG
+  U8  Refresh2X;
+  U8  LpddrThermalSensor;
+  U8  LockPTMregs;
+  U8  UserPowerWeightsEn;
+
+  U8  EnergyScaleFact;
+  U8  RaplPwrFl[MAX_CHANNEL];
+
+  U8  RaplLim2Lock;
+  U8  RaplLim2WindX;
+  U8  RaplLim2WindY;
+  U8  RaplLim2Ena;
+  U16 RaplLim2Pwr;
+  U8  RaplLim1WindX;
+  U8  RaplLim1WindY;
+  U8  RaplLim1Ena;
+  U16 RaplLim1Pwr;
+
+  U8  WarmThreshold[MAX_CHANNEL][MAX_DIMMS_IN_CHANNEL];
+  U8  HotThreshold[MAX_CHANNEL][MAX_DIMMS_IN_CHANNEL];
+  U8  WarmBudget[MAX_CHANNEL][MAX_DIMMS_IN_CHANNEL];
+  U8  HotBudget[MAX_CHANNEL][MAX_DIMMS_IN_CHANNEL];
+
+  U8  IdleEnergy[MAX_CHANNEL][MAX_DIMMS_IN_CHANNEL];
+  U8  PdEnergy[MAX_CHANNEL][MAX_DIMMS_IN_CHANNEL];
+  U8  ActEnergy[MAX_CHANNEL][MAX_DIMMS_IN_CHANNEL];
+  U8  RdEnergy[MAX_CHANNEL][MAX_DIMMS_IN_CHANNEL];
+  U8  WrEnergy[MAX_CHANNEL][MAX_DIMMS_IN_CHANNEL];
+  U8  SrefCfgEna;
+  U16 SrefCfgIdleTmr;
+  U8  ThrtCkeMinDefeat;
+  U8  ThrtCkeMinTmr;
+#ifdef ULT_FLAG
+  U8  ThrtCkeMinDefeatLpddr;
+  U8  ThrtCkeMinTmrLpddr;
+#endif // ULT_FLAG
+#ifdef UPSERVER_SUPPORT
+  // CLTM and TSOD settings
+  U8              Altitude; 
+  U8              UserThresholdEn;
+  U8              UserBudgetEn;
+  U8              TSOD_TcritMax;
+  U8              TSOD_EventMode;
+  U8              TSOD_EventPolarity;
+  U8              TSOD_CriticalEventOnly;
+  U8              TSOD_EventOutputControl;
+  U8              TSOD_AlarmwindowLockBit;
+  U8              TSOD_CriticaltripLockBit;
+  U8              TSOD_ShutdownMode;
+  U8              TSOD_ThigMax;
+  U8              TSOD_ManEn;
+
+#endif
+} ThermalMngmtEn;
+
+
+typedef struct {
+  MrcBool GdxcEnable;   ///< GDXC  MOT enable
+  U8      GdxcIotSize;  ///< IOT size in multiples of 8MEG
+  U8      GdxcMotSize;  ///< MOT size in multiples of 8MEG
+} MrcGdxc;
+
+typedef struct {
+  U32 ECT : 1;        ///< BIT0 - Early Command Training
+  U32 SOT : 1;        ///< BIT1 - Sense Amp Offset Training
+  U32 RDMPRT : 1;     ///< BIT2 - Read MPR Training
+  U32 RCVET : 1;      ///< BIT3 - Read Leveling Training (RcvEn)
+  U32 JWRL : 1;       ///< BIT4 - Jedec Write Leveling
+  U32 FWRL : 1;       ///< BIT5 - Functional Write Leveling
+  U32 WRTC1D : 1;     ///< BIT6 - Write Timing Centerin 1D
+  U32 RDTC1D : 1;     ///< BIT7 - Read Timing Centering 1D
+  U32 DIMMODTT : 1;   ///< BIT8 - Dimm ODT Training
+  U32 WRDST : 1;      ///< BIT9 - Write Drive Strength Training
+  U32 WREQT : 1;      ///< BIT10 - Write Equalization Training
+  U32 RCVENC1D: 1;    ///< BIT11 - Receive Enable Centering 1D
+  U32 RDODTT : 1;     ///< BIT12 - Read ODT Training
+  U32 RDEQT : 1;      ///< BIT13 - Read Equalization Training
+  U32 RDAPT : 1;      ///< BIT14 - Read Amplifier Power Training
+  U32 WRTC2D : 1;     ///< BIT15 - Write Timing Centerin 2D
+  U32 RDTC2D : 1;     ///< BIT16 - Read Timing Centering 2D
+  U32 CMDVC : 1;      ///< BIT17 - Command Voltage Centering
+  U32 WRVC2D : 1;     ///< BIT18 - Write Voltage Centering 2D
+  U32 RDVC2D : 1;     ///< BIT19 - Read Voltage Centering 2D
+  U32 RMC : 1;        ///< BIT20 - Retrain Margin Check
+  U32 : 1;            ///< BIT21 -
+  U32 LCT : 1;        ///< BIT22 - Late Command Training
+  U32 RTL : 1;        ///< BIT23 - Round Trip latency
+  U32 TAT : 1;        ///< BIT24 - Turn Around Timing
+  U32 RMT : 1;        ///< BIT25 - RMT Tool
+  U32 MEMTST : 1;     ///< BIT26 - Memory Test
+  U32 DIMMODTT1D : 1; ///< BIT27 - DIMMODTT1d
+  U32 WRSRT : 1;      ///< BIT28 - Write Slew Rate Training
+  U32 DIMMRONT : 1;   ///< BIT29 - Dimm Ron Training
+  U32 ALIASCHK: 1;    ///< BIT30 - SPD Alias Check
+} TrainingStepsEn;
+
+typedef enum {
+  MrcModeFull,
+  MrcModeMini
+} MrcMode;
+
+typedef enum {
+  LastRxV,
+  LastRxT,
+  LastTxV,
+  LastTxT,
+  LastRcvEna,
+  LastWrLevel,
+  LastCmdT,
+  LastCmdV,
+  MAX_RESULT_TYPE
+} MrcMarginResult;
+
+///
+/// Define the MRC recommended boot modes.
+///
+typedef enum {
+  bmCold, ///< Cold boot
+  bmWarm, ///< Warm boot
+  bmS3,   ///< S3 resume
+  bmFast, ///< Fast boot
+} MrcBootMode;
+
+///
+/// DIMM SPD Security Status
+///
+typedef enum {
+  MrcSpdStatusGood,      ///< Memory is in a secure state.
+  MrcSpdStatusAliased,   ///< Memory is aliased.
+
+  MrcSpdStatusLast       ///< Must be last in the list
+} MrcSpdStatus;
+
+///
+/// Define the virtual channel.
+///
+typedef enum {
+  vcA,  ///< Virtual channel A
+  vcB,  ///< Virtual channel B
+} MrcVirtualChannel;
+
+///
+/// Define the board types.
+///
+typedef enum {
+  btCRBMB,    ///< 0 - CRB Mobile
+  btCRBDT,    ///< 1 - CRB Desktop
+  btUser1,    ///< 2 - SV mobile
+  btUser2,    ///< 3 - SV desktop
+  btUser3,    ///< 4 - SV server?
+  btUser4,    ///< 5 - Ult
+  btCRBEMB,   ///< 6 - CRB Embedded
+  btUnknown,  ///< 7 - Unknown
+} MrcBoardType;
+
+///
+/// Define the CPU family/model.
+///
+typedef enum {
+  cmHSW     = 0x306C0,                  ///< Haswell
+  cmHSW_ULT = 0x40650,                  ///< Haswell-ULT
+  cmCRW     = 0x40660,                  ///< Crystalwell
+  cmBDW     = 0x306D0                   ///< Broadwell
+} MrcCpuModel;
+
+///
+/// Define the CPU stepping number.
+///
+typedef enum {
+  ///
+  /// Haswell
+  ///
+  csHswA0       = 1,
+  csHswB0       = 2,
+  csHswC0       = 3,
+  csHswLast     = csHswC0,
+
+  ///
+  /// Crystalwell
+  ///
+  csCrwB0       = 0,
+  csCrwC0       = 1,
+  csCrwLast     = csCrwC0,
+
+  ///
+  /// Haswell-ULT
+  ///
+  csHswUltB0    = 0,
+  csHswUltC0    = 1,
+  csHswUltLast  = csHswUltC0,
+
+  ///
+  /// Broadwell
+  ///
+  csBdwA0       = 0,
+  csBdwLast     = csBdwA0
+} MrcCpuStepping;
+
+typedef enum {
+  CONTROLLER_NOT_PRESENT, ///< There is no controller present in the system.
+  CONTROLLER_DISABLED,    ///< There is a controller present but it is disabled.
+  CONTROLLER_PRESENT      ///< There is a controller present and it is enabled.
+} MrcControllerSts;
+
+typedef enum {
+  CHANNEL_NOT_PRESENT,    ///< There is no channel present on the controller.
+  CHANNEL_DISABLED,       ///< There is a channel present but it is disabled.
+  CHANNEL_PRESENT         ///< There is a channel present and it is enabled.
+} MrcChannelSts;
+
+typedef enum {
+  DIMM_ENABLED,           ///< DIMM/rank Pair is enabled, presence TBD
+  DIMM_DISABLED,          ///< DIMM/rank Pair is disabled, regardless of presence.
+  DIMM_PRESENT,           ///< There is a DIMM present in the slot/rank pair and it will be used.
+  DIMM_NOT_PRESENT        ///< There is no DIMM present in the slot/rank pair.
+} MrcDimmSts;
+
+typedef enum {
+  STD_PROFILE,            ///< Standard DIMM profile select.
+  USER_PROFILE,           ///< User specifies various override values.
+  XMP_PROFILE1,           ///< XMP enthusiast settings select (XMP profile #1).
+  XMP_PROFILE2,           ///< XMP extreme settings select (XMP profile #2).
+  MAX_PROFILE             ///< Delimiter
+} MrcProfile;
+
+typedef enum {
+  MRC_REF_CLOCK_133,
+  MRC_REF_CLOCK_100,
+  MRC_REF_CLOCK_MAXIMUM   ///< Delimiter
+} MrcRefClkSelect;        ///< This value times the MrcClockRatio determines the MrcFrequency.
+
+typedef U32 MrcBClkRef;
+
+typedef enum {
+  MRC_DDR_TYPE_UNKNOWN,
+  MRC_DDR_TYPE_DDR3,
+  MRC_DDR_TYPE_LPDDR3
+} MrcDdrType;
+
+typedef enum {
+  MRC_MODULE_TYPE_UNKNOWN,
+  MRC_MODULE_TYPE_RDIMM,
+  MRC_MODULE_TYPE_UDIMM,
+  MRC_MODULE_TYPE_SODIMM,
+  MRC_MODULE_MICRO_DIMM,
+  MRC_MODULE_MINI_RDIMM,
+  MRC_MODULE_MINI_UDIMM,
+  MRC_MODULE_MINI_CDIMM,
+  MRC_MODULE_72B_SO_UDIMM,
+  MRC_MODULE_72B_SO_RDIMM,
+  MRC_MODULE_72B_SO_CDIMM,
+  MRC_MODULE_LRDIMM,
+  MRC_MODULE_16B_SO_DIMM,
+  MRC_MODULE_32B_SO_DIMM
+} MrcModuleType;
+
+typedef enum {
+  MrcIterationClock = 0,
+  MrcIterationCmdN  = 1,
+  MrcIterationCmdS  = 2,
+  MrcIterationCke   = 3,
+  MrcIterationCtl   = 4,
+  MrcIterationCmdV  = 5,
+  MrcIterationMax
+} MrcIterationType;
+
+typedef enum {
+  UpmLimit,
+  PowerLimit,
+  RetrainLimit,
+  MarginLimitMax
+} MRC_MARGIN_LIMIT_TYPE;
+
+typedef U8  MrcClockRatio;  ///< This value times the MrcRefClkSelect determines the MrcFrequency.
+typedef U32 MrcGfxDataSize; ///< The size of the stolen graphics data memory, in MBytes.
+typedef U32 MrcGfxGttSize;  ///< The size of the graphics translation table, in MBytes.
+
+///
+/// UPM PWR and Retrain Limits
+///
+typedef struct {
+  U8  Param;
+  U16 ParamLimit[MarginLimitMax];
+} MrcUpmPwrRetrainLimits;
+
+typedef union {
+  MrcUpmPwrRetrainLimits  *Pointer;
+  U64                     Data;
+} MrcUPRLimitPtr;
+
+typedef union {
+  U64 Data;
+  U32 Data32[2];
+} MrcCapId;                 ///< The memory controller capabilities.
+
+///
+/// MRC version description.
+///
+typedef struct {
+  U8  Major;  ///< Major version number
+  U8  Minor;  ///< Minor version number
+  U8  Rev;    ///< Revision number
+  U8  Build;  ///< Build number
+} MrcVersion;
+
+///
+/// Memory map configuration information.
+///
+typedef struct {
+  U32     TomMinusMe;
+  U32     ToludBase;
+  U32     BdsmBase;
+  U32     GttBase;
+  U32     GraphicsControlRegister;
+  U32     TsegBase;
+  MrcBool ReclaimEnable;
+  U32     RemapBase;
+  U32     RemapLimit;
+  U32     TouudBase;
+  U32     TotalPhysicalMemorySize;
+  U32     MeStolenBase;
+  U32     MeStolenSize;
+  U32     GdxcMotBase;
+  U32     GdxcMotSize;
+  U32     GdxcIotBase;
+  U32     GdxcIotSize;
+  U32     DprSize;
+  U32     FtpmStolenBase;
+} MrcMemoryMap;
+
+///
+/// Real time clock information.
+///
+typedef struct {
+  U8  Seconds;
+  U8  Minutes;
+  U8  Hours;
+  U8  DayOfMonth;
+  U8  Month;
+  U16 Year;
+} MrcBaseTime;
+
+///
+/// DIMM timings
+///
+typedef struct {
+  U32 tCK;    ///< Memory cycle time, in femtoseconds.
+  U16 NMode;  ///< Number of tCK cycles for the channel DIMM's command rate mode.
+  U16 tCL;    ///< Number of tCK cycles for the channel DIMM's CAS latency.
+  U16 tCWL;   ///< Number of tCK cycles for the channel DIMM's minimum CAS write latency time.
+  U16 tFAW;   ///< Number of tCK cycles for the channel DIMM's minimum four activate window delay time.
+  U16 tRAS;   ///< Number of tCK cycles for the channel DIMM's minimum active to precharge delay time.
+  U16 tRC;    ///< Number of tCK cycles for the channel DIMM's minimum active to active/refresh delay time.
+  U16 tRCD;   ///< Number of tCK cycles for the channel DIMM's minimum RAS# to CAS# delay time.
+  U16 tREFI;  ///< Number of tCK cycles for the channel DIMM's minimum Average Periodic Refresh Interval.
+  U16 tRFC;   ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
+  U16 tRFC2;  ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
+  U16 tRFC4;  ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
+  U16 tRP;    ///< Number of tCK cycles for the channel DIMM's minimum row precharge delay time.
+  U16 tRPab;  ///< Number of tCK cycles for the channel DIMM's minimum row precharge delay time for all banks.
+  U16 tRRD;   ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time.
+  U16 tRRD_L; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for same bank groups.
+  U16 tRRD_S; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for different bank groups.
+  U16 tRTP;   ///< Number of tCK cycles for the channel DIMM's minimum internal read to precharge command delay time.
+  U16 tWR;    ///< Number of tCK cycles for the channel DIMM's minimum write recovery time.
+  U16 tWTR;   ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time.
+} MrcTiming;
+
+typedef struct {
+  S32 Mtb;    ///< Medium time base.
+  S32 Ftb;    ///< Fine time base.
+} MrcTimeBase;
+
+typedef struct {
+  U8  Left;   ///< The left side of the timing eye.
+  U8  Center; ///< The center of the timing eye.
+  U8  Right;  ///< The right side of the timing eye.
+} MrcDqTimeMargin;
+
+typedef struct {
+  U8  High;   ///< The high side of the Vref eye.
+  U8  Center; ///< The center of the Vref eye.
+  U8  Low;    ///< The low side of the Vref eye.
+} MrcDqVrefMargin;
+
+typedef struct {
+  U8  Left;   ///< The left side of the command eye.
+  U8  Right;  ///< The right side of the command eye.
+  U8  High;   ///< The high side of the command eye.
+  U8  Low;    ///< The low side of the command eye.
+} MrcCommandMargin;
+
+typedef struct {
+  U8  Left;   ///< The left side of the receive enable eye.
+  U8  Right;  ///< The right side of the receive enableeye.
+} MrcRecvEnMargin;
+
+typedef struct {
+  U8  Left;   ///< The left side of the write leveling eye.
+  U8  Right;  ///< The right side of the write leveling eye.
+} MrcWrLevelMargin;
+
+#ifdef SSA_FLAG
+typedef struct {
+  U8   *BufBase;
+  U32  BufLimit;
+  union {
+    struct {
+      U8  Occupied : 1;
+      U8  HeapEnd  : 1;
+    } Bits;
+    U8 Data;
+  } BufFlags;
+} HeapBufHeader;
+#endif // SSA_FLAG
+
+#if ((defined SSA_FLAG) || (defined MRC_DEBUG_PRINT))
+typedef union {
+    struct {
+      U8  Init : 1; ///< 1 is SSA heap initialized.
+      U8       : 7;
+    } Bits;
+    U8 Data;
+  } SsaHeapFlagType;
+#endif
+
+///
+///*****************************************
+/// Output related "global data" structures.
+///*****************************************
+///
+/// This data structure contains all the "global data" values that are considered output by the MRC.
+/// The following are SDRAM level definitions. All ranks on a rank are set to these values.
+///
+/* Commented out until needed, in order to save space.
+typedef struct {
+} MrcSdramOut;
+*/
+
+///
+/// This data structure contains all the "global data" values that are considered output by the MRC.
+/// The following are rank level definitions. All ranks on a DIMM are set to these values.
+///
+typedef struct {
+//MrcSdramOut     Sdram[MAX_SDRAM_IN_DIMM];
+  U16             MR[MAX_MR_IN_DIMM]; ///< DRAM mode register value.
+#ifdef ULT_FLAG
+  U16             MR11; ///< LPDDR3 ODT MR
+#endif
+} MrcRankOut;
+
+///
+/// This data structure contains all the "global data" values that are considered output by the MRC.
+/// The following are DIMM level definitions. All ranks on a DIMM are set to these values.
+///
+typedef struct {
+  MrcDimmSts    Status;                 ///< See MrcDimmSts for the definition of this field.
+  MrcTiming     Timing[MAX_PROFILE];    ///< The DIMMs timing values.
+  MrcVddSelect  VddVoltage[MAX_PROFILE];///< The voltage (VDD) setting for this DIMM, per profile.
+  MrcBool       EccSupport;             ///< TRUE if ECC is enabled and supported on this DIMM.
+  MrcBool       IgnoreNonEccDimm;       ///< TRUE if a DIMM without ECC capability should be ignored.
+  MrcBool       AddressMirrored;        ///< TRUE if the DIMM is address mirrored.
+  MrcBool       SelfRefreshTemp;        ///< TRUE if the DIMM supports self refresh extended operating temperature range (SRT).
+  MrcBool       AutoSelfRefresh;        ///< TRUE if the DIMM supports automatic self refresh (ASR).
+  MrcBool       PartialSelfRefresh;     ///< TRUE if the DIMM supports Partial Array Self Refresh (PASR).
+  MrcBool       OnDieThermalSensor;     ///< TRUE if the DIMM supports On-die Thermal Sensor (ODTS) Readout.
+  MrcBool       ExtendedTemperRange;    ///< TRUE if the DIMM supports Extended Temperature Range (ETR).
+  MrcBool       ExtendedTemperRefresh;  ///< TRUE if the DIMM supports 1x Extended Temperature Refresh rate, FALSE = 2x.
+  MrcDdrType    DdrType;                ///< DDR type: DDR3 or LPDDR3
+  MrcModuleType ModuleType;             ///< Module type: UDIMM, SO-DIMM, etc.
+  U32           SdramCount;             ///< The number of SDRAM components on a DIMM.
+  U32           DimmCapacity;           ///< DIMM size in MBytes.
+  U32           RowSize;                ///< The DIMMs row address size.
+  U16           ColumnSize;             ///< The DIMMs column address size.
+  U16           Crc;                    ///< Calculated CRC16 of the DIMM's provided SPD. Can be used to detect DIMM change.
+  U8            RankInDIMM;             ///< The number of ranks in this DIMM.
+  U8            Banks;                  ///< Number of banks the DIMM contains.
+  U8            BankGroups;             ///< Number of bank groups the DIMM contains.
+  U8            PrimaryBusWidth;        ///< DIMM primary bus width.
+  U8            SdramWidth;             ///< DIMM SDRAM width.
+  U8            SdramWidthIndex;        ///< DIMM SDRAM width index (0 = x4, 1 = x8, 2 = x16, 3 = x32).
+  U8            DensityIndex;           ///< Total SDRAM capacity index (0 = 256Mb, 1 = 512Mb, 2 = 1Gb, etc).
+  U8            ReferenceRawCard;       ///< Indicates which JEDEC reference design raw card was used as the basis for the module assembly.
+  U8            XmpSupport;             ///< Indicates if XMP profiles are supported. 0 = None, 1 = XMP1 only, 2 = XMP2 only, 3 = All.
+  U8            XmpRevision;            ///< Indicates the XMP revision of this DIMM. 0 = None, 12h = 1.2, 13h = 1.3.
+  MrcRankOut    Rank[MAX_RANK_IN_DIMM];
+} MrcDimmOut;
+
+///
+/// This data structure contains all the "global data" values that are considered output by the MRC.
+/// The following are channel level definitions. All DIMMs on a memory channel are set to these values.
+///
+typedef struct {
+  MrcChannelSts     Status;                            ///< Indicates whether this channel should be used.
+  MrcVirtualChannel VirtualChannel;                    ///< define the virtual channel type A or B.
+  MrcTiming         Timing[MAX_PROFILE];               ///< The channel timing values.
+  MrcTimeBase       TimeBase[MAX_DIMMS_IN_CHANNEL][MAX_PROFILE];
+  MrcBool           EccSupport;                        ///< TRUE if ECC is enabled and supported on this channel.
+  U32               Capacity;                          ///< Amount of memory in this channel, in MBytes.
+  U32               DimmCount;                         ///< Number of valid DIMMs that exist in the channel.
+  U32               DataOffsetTrain[MAX_SDRAM_IN_DIMM];///< DataOffsetTrain CR
+  U32               DataCompOffset[MAX_SDRAM_IN_DIMM]; ///< DataCompOffset CR
+  DDRDATA0CH0_CR_DDRCRDATACONTROL0_STRUCT DqControl0;                    ///< DqControl0 CR
+  DDRDATA0CH0_CR_DDRCRDATACONTROL1_STRUCT DqControl1[MAX_SDRAM_IN_DIMM]; ///< DqControl1 CR
+  DDRDATA0CH0_CR_DDRCRDATACONTROL2_STRUCT DqControl2[MAX_SDRAM_IN_DIMM]; ///< DqControl2 CR
+  U32               CkeCmdPiCode[2];                   ///< CKE  CmdPiCode CR, per group
+  U32               CmdsCmdPiCode[2];                  ///< CmdS CmdPiCode CR, per group
+  U32               CmdnCmdPiCode[2];                  ///< CmdN CmdPiCode CR, per group
+  U32               MchbarBANK;                        ///< tRCD tRP tRAS tRDPRE (tRTP) tWRPRE and tRRD values.
+  U32               MchbarBANKRANKA;                   ///< Mchbar TC Read to Read Turnaround CR
+  U32               MchbarBANKRANKB;                   ///< Mchbar TC Write to x Turnaround CR
+  U32               MchbarBANKRANKC;                   ///< Mchbar TC Read to Write Turnaround CR
+  U32               MchbarBANKRANKD;                   ///< Mchbar TC Write /Read Duration
+  U32               TxXtalk[MAX_SDRAM_IN_DIMM];        ///< TxXtalk Setting
+  U16               TxDqs[MAX_RANK_IN_CHANNEL][MAX_SDRAM_IN_DIMM]; ///< TxDQS PI Code
+  U16               TxDq[MAX_RANK_IN_CHANNEL][MAX_SDRAM_IN_DIMM];  ///< TxDQ Pi Code
+  U16               RcvEn[MAX_RANK_IN_CHANNEL][MAX_SDRAM_IN_DIMM]; ///< RcvEn PI Code
+  U16               WlDelay[MAX_RANK_IN_CHANNEL][MAX_SDRAM_IN_DIMM];
+  U8                ClkPiCode[MAX_RANK_IN_CHANNEL];    ///< CLK ClkPiCode
+  U8                CtlPiCode[MAX_RANK_IN_CHANNEL];    ///< CTL CtlPiCode
+  U8                CkePiCode[MAX_RANK_IN_CHANNEL];    ///< CKE CtlPiCode
+  U8                TxEq[MAX_RANK_IN_CHANNEL][MAX_SDRAM_IN_DIMM];  ///< TxEq Setting
+  MrcCommandMargin  Command[MAX_RANK_IN_CHANNEL];
+  MrcDqTimeMargin   RxDqPb[MAX_RANK_IN_CHANNEL][MAX_SDRAM_IN_DIMM][MAX_BITS]; ///< Rx PerBit Pi Code
+  MrcDqTimeMargin   TxDqPb[MAX_RANK_IN_CHANNEL][MAX_SDRAM_IN_DIMM][MAX_BITS]; ///< Tx PerBit Pi Code
+  MrcDqVrefMargin   RxDqVrefPb[MAX_RANK_IN_CHANNEL][MAX_SDRAM_IN_DIMM][MAX_BITS]; ///< Rx PerBit Vref
+  MrcDqVrefMargin   TxDqVrefPb[MAX_RANK_IN_CHANNEL][MAX_SDRAM_IN_DIMM][MAX_BITS]; ///< Rx PerBit Vref
+  MrcRecvEnMargin   ReceiveEnable[MAX_RANK_IN_CHANNEL]; ///< Receive enable per rank
+  MrcWrLevelMargin  WriteLevel[MAX_RANK_IN_CHANNEL];   ///< Write leveling per rank
+  U8                IoLatency[MAX_RANK_IN_CHANNEL];    ///< IOLatency
+  U8                RTLatency[MAX_RANK_IN_CHANNEL];    ///< RoundTripLatency
+  U32               RTIoComp;                          ///< RoundTrip IO Compensation of the Channel
+  U8                RxVref[MAX_SDRAM_IN_DIMM];         ///< RX Vref in steps of 7.9 mv
+  U8                RxEq[MAX_RANK_IN_CHANNEL][MAX_SDRAM_IN_DIMM];  ///< RxEQ Setting
+  U8                RxDqsP[MAX_RANK_IN_CHANNEL][MAX_SDRAM_IN_DIMM];/// RxDQSP PI Code
+  U8                RxDqsN[MAX_RANK_IN_CHANNEL][MAX_SDRAM_IN_DIMM];/// RxDQSN PI Code
+  U8                RankInChannel;                     ///< Number of valid ranks that exist in the channel.
+  U8                ValidRankBitMask;                  ///< Bit map of the populated ranks per channel
+  U8                ValidCkeBitMask;                   ///< Bit map of the used CKE pins per channel
+  MrcDimmOut        Dimm[MAX_DIMMS_IN_CHANNEL];
+} MrcChannelOut;
+
+///
+/// This data structure contains all the "global data" values that are considered output by the MRC.
+/// The following are memory controller level definitions. All channels on a controller are set to these values.
+///
+typedef struct {
+  MrcControllerSts  Status;               ///< Indicates whether this controller should be used.
+  U16               DeviceId;             ///< The PCI device id of this memory controller.
+  U8                RevisionId;           ///< The PCI revision id of this memory controller.
+  U8                ChannelCount;         ///< Number of valid channels that exist on the controller.
+  MrcChannelOut     Channel[MAX_CHANNEL]; ///< The following are channel level definitions.
+} MrcControllerOut;
+
+///
+/// This data structure contains all the "DDR power saving data" values that are considered output by the MRC.
+/// The following are memory controller level definitions. All channels on a controller are set to these values.
+///
+typedef struct {
+  BOOL              BaseFlag;         ///< Indicates if the base line of power was already calculated.
+  U16               BaseSavingRd;     ///< Indicates the base line of power consume by the ddr on read.
+  U16               BaseSavingWr;     ///< Indicates the base line of power consume by the ddr on write.
+  U16               BaseSavingCmd;    ///< Indicates the base line of power consume by the ddr on command.
+  U16               MrcSavingRd;      ///< Indicates the power consume by the ddr on read at the end of MRC.
+  U16               MrcSavingWr;      ///< Indicates the power consume by the ddr on write at the end of MRC.
+  U16               MrcSavingCmd;     ///< Indicates the power consume by the ddr on command at the end of MRC.
+} MrcOdtPowerSaving;
+
+///
+/// This data structure contains all the "global data" values that are considered output by the MRC.
+/// The following are system level definitions. All memory controllers in the system are set to these values.
+///
+typedef struct {
+  MrcVersion              Version;                  ///< The memory reference code version.
+  MrcFrequency            FreqMax;                  ///< The requested maximum valid frequency.
+  MrcFrequency            Frequency;                ///< The system's common memory controller frequency.
+  U32                     MemoryClockMax;           ///< The system's common memory controller maximum clock, in femtoseconds.
+  U32                     MemoryClock;              ///< The system's common memory controller clock, in femtoseconds.
+  MrcRefClkSelect         RefClk;                   ///< The memory controller is going to use this reference clock.
+  MrcClockRatio           Ratio;                    ///< Request for this memory controller to use this clock ratio.
+  MrcBootMode             BootMode;                 ///< The system's common memory controller boot mode.
+  MrcMemoryMap            MemoryMapData;            ///< The system's memory map data.
+  MrcGfxDataSize          GraphicsStolenSize;       ///< Graphics Data Stolen Memory size in MB
+  MrcGfxGttSize           GraphicsGttSize;          ///< GTT graphics stolen memory size in MB
+  MrcVddSelect            VddVoltage[MAX_PROFILE];  ///< The currently running voltage (VDD) setting for all DIMMs in the system, per profile.
+  MrcGdxc                 Gdxc;                     ///< GDXC enable and size.
+  MrcBool                 VddVoltageDone;           ///< To determine if VddVoltageDone update has been done already
+  MrcBool                 EccSupport;               ///< TRUE if ECC is enabled and supported on this controller.
+  MrcBool                 EnDumRd;                  ///< Enable/Disable Logic Analizer
+  MrcBool                 RestoreMRs;               ///< Enable/Disable restoring
+  MrcBool                 AsyncOdtDis;              ///< Enable Asyncronous ODT
+  MrcBool                 LpddrEctDone;             ///< Set to TRUE once Early Command Training on LPDDR is done, and we can run JEDEC Init
+  MrcBool                 LpddrJedecInitDone;       ///< Set to TRUE once JEDEC Init on LPDDR is done
+  MrcBool                 XmpProfileEnable;         ///< XMP capable DIMMs detected in system (0 = no, 1 = yes).
+  MrcBool                 Capable100;               ///< The MC is capable of 100 reference clock (0 = no, 1 = yes).
+  MrcBool                 AutoSelfRefresh;          ///< Indicates ASR is supported for all the DIMMS for 2xRefresh
+  MrcDdrType              DdrType;                  ///< Current memory type: DDR3 or LPDDR3
+  MrcSpdStatus            SpdSecurityStatus;        ///< Status variable to inform BIOS that memory contains an alias.
+  U32                     MrcTotalChannelLimit;     ///< The maximum allowed memory size per channel, in MBytes.
+  U8                      SdramCount;               ///< The number of SDRAM components on a DIMM.
+  U32                     CompCtl0;                 ///< CompCtl0 CR
+  U32                     CompCtl1;                 ///< CompCtl1 CR
+  U32                     DimmVref;                 ///< DimmVref CR
+  U32                     MiscControl0;             ///< MiscCOntrol0 CR
+  U16                     Qclkps;                   ///< Qclk period in pS
+  U8                      DQPat;                    ///< Global Variables storing the current DQPat REUT Test
+  S8                      DQPatLC;                  ///< Global Variables storing the current DQPat Loopcount
+  U8                      ValidRankMask;            ///< Rank bit map - includes both channels
+  U8                      ValidChBitMask;           ///< Channel bit map of the populated channels
+  MrcUPRLimitPtr          UpmPwrRetrainLimits;      ///< Pointer to Global UPM/PWR/RETRAIN Limits on the stack the size of MRC_NUMBER_UPM_PWR_RETRAIN_MARGINS
+  U32                     MarginResult[MAX_RESULT_TYPE][MAX_RANK_IN_CHANNEL][MAX_CHANNEL][MAX_SDRAM_IN_DIMM][MAX_EDGES];  ///< Stores last margin measurement.
+  MrcControllerOut        Controller[MAX_CONTROLLERS];
+  MrcOdtPowerSaving       OdtPowerSavingData;
+#ifdef UPSERVER_SUPPORT
+  U16               CLTM_SPD_Conf;        ///< CLTM SPD Configuration Done(0 = process not executed, 0xFF = process failed, XX = process save CLTM_SPD_Conf
+#endif                                    ///< CLTM_SPD_Conf = h=2xRefreshState i = Density , j = Frequency , k1 = Adjacent DIMM prescence in Channel 1, k0 = Adjacent DIMM prescence in Channel 0 
+} MrcOutput;
+
+///
+///****************************************
+/// Input related "global data" structures.
+///****************************************
+///
+/// This data structure contains all the "global data" values that are considered input by the MRC.
+/// The following are SDRAM level definitions. All ranks on a rank are set to these values.
+///
+/* Commented out until needed, in order to save space.
+typedef struct {
+  U8  Placeholder;  ///< TODO: Is there anything that needs to go in here?
+} MrcSdramIn;
+*/
+
+///
+/// This data structure contains all the "global data" values that are considered input by the MRC.
+/// The following are rank level definitions. All ranks on a DIMM are set to these values.
+///
+/* Commented out until needed, in order to save space.
+typedef struct {
+  MrcSdramIn  Sdram[MAX_SDRAM_IN_DIMM];
+} MrcRankIn;
+*/
+
+///
+/// This data structure contains all the "global data" values that are considered input by the MRC.
+/// The following are DIMM level definitions. All ranks on a DIMM are set to these values.
+///
+typedef struct {
+  MrcDimmSts  Status; ///< Indicates whether this DIMM should be used.
+  U8          SpdValid[sizeof (MrcSpd) / (CHAR_BITS * sizeof (U8))]; ///< Each valid bit maps to SPD byte.
+  MrcSpd      Spd;        ///< The SPD data for each DIMM. SPDGeneral field = 0 when absent.
+  MrcTiming   Timing;     ///< The DIMMs requested timing overrides.
+  U8          SpdAddress; ///< The SMBus address for the DIMM's SPD data.
+//MrcRankIn   Rank[MAX_RANK_IN_DIMM];
+} MrcDimmIn;
+
+///
+/// This data structure contains all the "global data" values that are considered input by the MRC.
+/// The following are channel level definitions. All DIMMs on a memory channel are set to these values.
+///
+typedef struct {
+  MrcChannelSts Status;     ///< Indicates whether this channel should be used.
+  U32           DimmCount;  ///< The maximum number of DIMMs on this channel.
+  MrcDimmIn     Dimm[MAX_DIMMS_IN_CHANNEL];
+#ifdef ULT_FLAG
+  U8            DqsMapCpu2Dram[8];            ///< Mapping from CPU DQS pins to SDRAM DQS pins
+  U8            DqMapCpu2Dram[8][MAX_BITS];   ///< Mapping from CPU DQ pins to SDRAM DQ pins
+  U8            DQByteMap[MrcIterationMax][2];  ///< Maps which PI clocks are used by what LPDDR DQ Bytes (from CPU side), per group
+                            ///< DQByteMap[0] - ClkDQByteMap:
+                            ///<   If clock is per rank, program to [0xFF, 0xFF]
+                            ///<   If clock is shared by 2 ranks, program to [0xFF, 0] or [0, 0xFF]
+                            ///<   If clock is shared by 2 ranks but does not go to all bytes,
+                            ///<           Entry[i] defines which DQ bytes Group i services
+                            ///< DQByteMap[1] - CmdNDQByteMap: Entry[0] is CmdN/CAA and Entry[1] is CmdN/CAB
+                            ///< DQByteMap[2] - CmdSDQByteMap: Entry[0] is CmdS/CAA and Entry[1] is CmdS/CAB
+                            ///< DQByteMap[3] - CkeDQByteMap : Entry[0] is CKE /CAA and Entry[1] is CKE /CAB
+                            ///<                For DDR, DQByteMap[3:1] = [0xFF, 0]
+                            ///< DQByteMap[4] - CtlDQByteMap : Always program to [0xFF, 0] since we have 1 CTL / rank
+                            ///<                               Variable only exists to make the code easier to use
+                            ///< DQByteMap[5] - CmdVDQByteMap: Always program to [0xFF, 0] since we have 1 CA Vref
+                            ///<                               Variable only exists to make the code easier to use
+#endif // ULT_FLAG
+} MrcChannelIn;
+
+///
+/// This data structure contains all the "global data" values that are considered input by the MRC.
+/// The following are memory controller level definitions. All channels on a controller are set to these values.
+///
+typedef struct {
+  MrcControllerSts  Status;               ///< Indicates whether this controller should be used.
+  U8                ChannelCount;         ///< Number of valid channels that are requested on the controller.
+  MrcChannelIn      Channel[MAX_CHANNEL]; ///< The following are channel level definitions.
+} MrcControllerIn;
+
+///
+/// This data structure contains all the "global data" values that are considered input by the MRC.
+/// The following are system level definitions. All memory controllers in the system are set to these values.
+///
+typedef struct {
+  MrcDebug        Debug;
+  MrcFrequency    FreqMax;                    ///< The requested maximum valid frequency.
+  MrcClockRatio   Ratio;                      ///< Request for this memory controller to use this clock ratio.
+  MrcRefClkSelect RefClk;                     ///< Request for this memory controller to use this reference clock.
+  MrcBClkRef      BClkFrequency;              ///< Base reference clock value, in Hertz.
+  MrcBoardType    BoardType;                  ///< define the board type (CRBMB,CRBDT,User1,User2). the OEM can add more boards.
+  MrcCpuStepping  CpuStepping;                ///< define the CPU stepping.
+  MrcCpuModel     CpuModel;                   ///< define the CPU model.
+  MrcGfxDataSize  GraphicsStolenSize;         ///< Graphics Data Stolen Memory size in MB
+  MrcGfxGttSize   GraphicsGttSize;            ///< GTT graphics stolen memory size in MB
+  MrcBaseTime     BaseTime;                   ///< RTC base time.
+  MrcIteration    Iteration;                  ///
+  MrcMode         MrcMode;                    ///< The control for full or MiniBIOS MRC.
+  MrcVddSelect    VddVoltage;                 ///< The requested voltage (VDD) setting.
+  MrcProfile      MemoryProfile;              ///< The memory profile requested to be used.
+  MrcBootMode     BootMode;                   ///< The requested memory controller boot mode.
+  MrcBool         TxtFlag;                    ///
+  MrcBool         MobilePlatform;             ///< define Mobile or Desktop platform. true is mobile.
+  MrcBool         EccSupport;                 ///< Tell to the MRC if ECC supporting or not. if false the ecc will not be support even if the DIMM will support in ECC.
+  MrcBool         SetRxDqs32;                 ///
+  MrcBool         GfxIsVersatileAcceleration; ///< iGFX engines are in Versatile Acceleration
+  MrcBool         ScramblerEnable;            ///< Enable/Disable scrambling
+  MrcBool         McLock;                     ///
+  MrcBool         RemapEnable;                ///
+  MrcBool         AutoSelfRefreshSupport;     ///< FALSE = No auto self refresh support, TRUE = auto self refresh support.
+  MrcBool         ExtTemperatureSupport;      ///< FALSE = No extended temperature support, TRUE = extended temperature support.
+  U32             SaMemCfgAddress;
+  U32             SaMemCfgSize;
+  U32             PciEBaseAddress;            ///< define the PciE base address.
+  U32             MchBarBaseAddress;          ///< define the MCH bar base address.
+  U32             SmbusBaseAddress;           ///< This field defines the smbus base address.
+  U32             GdxcBaseAddress;            ///< This field defines the GDXC base address.
+  U32             HpetBaseAddress;            ///< This field defines the hpet base address.
+  U32             MeStolenSize;               ///< define the size that the ME need in MB.
+  U32             MmioSize;                   ///< define the MMIO size in MB.
+  U32             TsegSize;                   ///< TSEG size that require by the system in MB.
+  U32             IedSize;                    ///< IED size that require by the system in MB.
+  U32             DprSize;                    ///< DPR size required by system in MB.
+  U32             VddSettleWaitTime;          ///< The minimum time in nanoseconds to wait for VDD to settle after being changed.
+  U16             VccIomV;                    ///< VccIO logic voltage in mV.
+  U8              PowerDownMode;              ///< Option to select No PD, APD or PPD-DLLoff
+  U8              PwdwnIdleCounter;           ///< Option to select the power down Idle counter.
+  MrcBool         RankInterleave;             ///< Option to Enable Rank Interleave.
+  MrcBool         EnhancedInterleave;         ///< Option to Enable Enhanced Interleave.
+  MrcBool         WeaklockEn;                 ///< Option to Enable Weaklock for CMD, CTL and CKE
+  U8              EnCmdRate;                  ///< Option to Enable and select the number of CMDs for 1.5NMode
+  MrcBool         CmdTriStateDis;             ///< Option to Disable cmd tri-state
+  MrcBool         RefreshRate2x;              ///< Tells the MRC to enable 2x Refresh.
+  MrcBool         ChHashEnable;               ///< Option to Enable Channel Hash.
+  U16             ChHashMask;                 ///< Option to select Address bits[19:6] to include in Channel XOR function.
+  U8              ChHashInterleaveBit;        ///< Option to select interleave Address bit. Valid values are 0 - 3 for BITS 6 - 9.
+  ThermalMngmtEn  ThermalEnables;             ///< Options to Enable Thermal management settings
+  MrcControllerIn Controller[MAX_CONTROLLERS];
+#ifdef SSA_FLAG
+  U32             SsaCallbackPpi;
+#endif // SSA_FLAG
+#if ((defined SSA_FLAG) || (defined MRC_DEBUG_PRINT))
+  U32             SsaHeapBase;      ///< Starting address of the SSA services heap space.
+  U32             SsaHeapSize;      ///< Size of the SSA services heap space, in bytes.
+  SsaHeapFlagType SsaHeapFlag;      ///< Bit 0 = 1 is SSA heap initialized, all other bits reserved.
+#endif
+  MrcGdxc         Gdxc;             ///< GDXC enable and size.
+  MrcBool         MemoryTrace;      ///< Option to Enable Memory Trace to second DDR channel using Stacked Mode
+  TrainingStepsEn TrainingEnables;  ///< Options to Enable individual training steps
+  MrcBool         OemCleanMemory;   ///< TRUE to request a memory clean
+  MrcBool         RmtBdatEnable;    ///< Option to enable output of training results into BDAT.
+#ifdef ULT_FLAG
+  MrcBool         DqPinsInterleaved;  ///< Interleaving mode of DQ/DQS pins - depends on board routing
+  MrcBool         LpddrDramOdt;       ///< TRUE if LPDDR DRAM ODT is used - depends on board design
+  U8              CkeRankMapping;     ///< [3:0] - Channel 0, [7:4] - Channel 1.
+                                      ///< Bit [i] specifies which rank CKE[i] goes to.
+#endif
+  U8              MaxRttWr;           ///< Maximum DIMM RTT_WR to use in power training 0 = Off, 1 = 120 ohms
+} MrcInput;
+
+///
+///********************************************
+/// Saved data related "global data" structures.
+///********************************************
+///
+
+///
+/// This data structure contains all the "global data" values that are considered to be needed
+/// by the MRC between power state transitions (S0->S3->S0) and also fast and warm boot modes.
+/// The following are channel level definitions.
+///
+typedef struct {
+  MrcChannelSts Status;                               ///< Indicates whether this channel should be used.
+  MrcBool       EccSupport;                           ///< TRUE if ECC is enabled and supported on this DIMM.
+  U32           DimmCount;                            ///< Number of valid DIMMs that exist in the channel.
+  U8            ValidRankBitMask;                     ///< Bit map of the populated ranks per channel
+  MrcTiming     Timing[MAX_PROFILE];                  ///< The channel timing values.
+  MrcDimmOut    Dimm[MAX_DIMMS_IN_CHANNEL];
+  MrcSpdSave    SpdSave[MAX_DIMMS_IN_CHANNEL];        ///< Save SPD information needed for SMBIOS structure creation.
+} MrcChannelSave;
+
+///
+/// This data structure contains all the "global data" values that are considered to be needed
+/// by the MRC between power state transitions (S0->S3->S0) and also fast and warm boot modes.
+/// The following are controller level definitions.
+///
+typedef struct {
+  MrcControllerSts  Status;                           ///< Indicates whether this controller should be used.
+  U8                ChannelCount;                     ///< Number of valid channels that exist on the controller.
+  MrcChannelSave    Channel[MAX_CHANNEL];
+} MrcContSave;
+
+///
+/// This data structure contains all the "global data" values that are considered to be needed
+/// by the MRC between power state transitions (S0->S3->S0) and also fast and warm boot modes.
+/// The following are system level definitions.
+///
+typedef struct {
+  U32 Crc;                  ///< The CRC-32 of the data in this structure.
+} MrcSaveHeader;
+
+//
+// ------- IMPORTANT NOTE --------
+// MRC_MC_REGISTER_COUNT in Global.h should match the table in MrcSaveRestore.c.
+// Update this define whenever you add/remove registers from this table.
+//
+ #define MRC_MC_REGISTER_COUNT (1 + (2496 / sizeof (U32))) ///< The number of MC registers that need to be saved.
+
+typedef struct {
+  MrcCapId        McCapId;                            ///< The memory controller's capabilities.
+  U32             MeStolenSize;
+  U32             McRegister[MRC_MC_REGISTER_COUNT];  ///< The memory controllers registers.
+  MrcCpuStepping  CpuStepping;                        ///< The last cold boot happended with this CPU stepping.
+  MrcCpuModel     CpuModel;                           ///< The last cold boot happended with this CPU model.
+  MrcVersion      Version;                            ///< The last cold boot happended with this MRC version.
+  U32             SaMemCfgCrc;                        ///< The CRC32 of the system agent memory configuration structure.
+  MrcContSave     Controller[MAX_CONTROLLERS];
+  MrcFrequency    Frequency;                          ///< The system's common memory controller frequency.
+  U32             MemoryClock;                        ///< The system's common memory controller clock, in femtoseconds.
+  MrcRefClkSelect RefClk;                             ///< The memory controller is going to use this reference clock.
+  MrcClockRatio   Ratio;                              ///< Request for this memory controller to use this clock ratio.
+  MrcVddSelect    VddVoltage[MAX_PROFILE];            ///< The voltage (VDD) setting for all DIMMs in the system, per profile.
+  MrcBool         EccSupport;                         ///< TRUE if ECC is enabled and supported on this controller.
+  MrcDdrType      DdrType;                            ///< DDR type: DDR3 or LPDDR3
+  MrcBool         XmpProfileEnable;                   ///< XMP capable DIMMs detected in system (0 = no, 1 = yes).
+#ifdef UPSERVER_SUPPORT
+  U16              CLTM_SPD_Conf;                      ///< CLTM SPD Configuration Done(0 = process not executed, 0xFF = process failed, XX = process save CLTM_SPD_Conf
+#endif // UPSERVER_SUPPORT                            ///< CLTM_SPD_Conf = i = Density , j = Frequency , k1 = Adjacent DIMM prescence in Channel 1, k0 = Adjacent DIMM prescence in Channel 0 
+} MrcSaveData;
+
+typedef struct {
+  MrcSaveHeader Header;                               ///< The header portion of the MRC saved data.
+  MrcSaveData   Data;                                 ///< The data portion of the MRC saved data.
+} MrcSave;
+
+typedef struct {
+  MrcInput  Inputs;
+} SysInput;
+
+typedef struct {
+  MrcOutput Outputs;
+} SysOutput;
+
+typedef struct {
+  MrcSave Save;
+} SysSave;
+
+///
+/// This data structure contains all of the MRC "global data" values.
+///
+typedef struct {
+  U32       SaveSize;
+  SysSave   SysSave;
+  SysInput  SysIn;
+  SysOutput SysOut;
+  U64       Oem;
+#ifdef BDAT_SUPPORT
+  RmtData   Rmt;
+#endif
+} MrcParameters;
+
+#ifdef UPSERVER_SUPPORT
+
+
+
+#define WarmThreshold_1X_MAX_TEMP       83
+#define WarmThreshold_2X_MAX_TEMP       85
+#define HotThreshold_1X_MAX_TEMP        83
+#define HotThreshold_2X_MAX_TEMP        92
+
+
+#define CRITICAL_TEMP                    105
+#define THOT_2X_MAX_TEMP                 93
+#define THOT_1X_MAX_TEMP                 83
+#define DISABLE_REFRESH2X                0
+
+//Power Weight Table Defines
+#define WARM_BUDGET_POSITION             6
+
+// CLTM Process Status Defines
+#define PROCESS_NOT_INITIALIZED          0x0000
+#define PROCESS_FAILED                   0xFFFF
+#define CONTROLLER_NOT_LOADED            0xFF
+#define CLTM_DISABLE                     0
+
+//CAMARILLO Interrupt Defines
+#define TWOX_REFRESH_INTERRUPT_ENABLE    1
+#define FORCEMEMPR_INTERRUPT_ENABLE      1
+
+//TSE2002 Thermal Sensor Defines
+#define MTS_CAPABILITIES                 0
+#define MTS_CFG                          1
+#define MTS_THIGH                        2
+#define MTS_TLOW                         3
+#define MTS_TCRIT                        4
+#define TEMPERATURE_REGISTER             5
+#define MTS_MFGID                        6
+#define MTS_DID                          7
+#define THERMAL_MODULE_MASK              0x30
+
+//TSOD definitions
+#define HYST_DISABLE                      0
+
+typedef union {
+  struct {
+    U16 EVENT_MODE                              :  1;  // Bits 0:0
+    U16 EVENT_POLARITY                          :  1;  // Bits 1:1
+    U16 CRICAL_EVENT_ONLY                       :  1;  // Bits 2:2
+    U16 EVENT_OUTPUT_CONTROL                    :  1;  // Bits 3:3
+    U16 EVENT_STATUS                            :  1;  // Bits 4:4
+    U16 CLEAR_EVENT                             :  1;  // Bits 5:5
+    U16 ALARM_WINDOW_LOCK                       :  1;  // Bits 6:6
+    U16 CRITICAL_LOCK                           :  1;  // Bits 7:7
+    U16 SHUTDOWNMODE                            :  1;  // Bits 8:8
+    U16 HYST_ENABLE                             :  1;  // Bits 10:9                                              
+    U16                                         :  4;  // Bits 15:11
+  } Bits;
+  U16 Data;
+} TSOD_CONF_REGISTER_STRUCT;
+
+//#define MTS_CFG_EVENT                  ((0x01) | (0x04) | (0x08)) //Bit 0 = 1, Bit 1 = 0, Bit 2 = 1, Bit 3 = 1 , Bit8 = 0, Bit 10 =0 
+
+#endif //UPSERVER_SUPPORT
+
+
+#pragma pack (pop)
+#endif
+
diff --git a/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcIoControl.h b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcIoControl.h
new file mode 100644
index 0000000..2d00470
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcIoControl.h
@@ -0,0 +1,44 @@
+/** @file
+  Memory controller IO configuration definition header.
+
+@copyright
+  Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved.
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement.
+**/
+#ifndef _MrcIoControl_h_
+#define _MrcIoControl_h_
+
+#include "MrcTypes.h"
+#include "McAddress.h"
+#include "MrcCommon.h"
+#include "MrcGlobal.h"
+
+/**
+@brief
+  Reset the MC IO module. The MC hardware will handle creating the 20 dclk pulse
+  after the bit is set and will also clear the bit.
+
+  @param[in] MrcData - Include all MRC global data.
+
+  @retval mrcSuccess    - IO Reset was done successfully
+  @retval mrcDeviceBusy - Timed out waiting for the IO to clear the bit
+**/
+MrcStatus
+IoReset (
+  IN MrcParameters *const MrcData
+  );
+
+#endif // _MrcIoControl_h_
diff --git a/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcMcConfiguration.h b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcMcConfiguration.h
new file mode 100644
index 0000000..6a094d1
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcMcConfiguration.h
@@ -0,0 +1,114 @@
+/** @file
+  Non training specific memory controller configuration definitions.
+
+@copyright
+  Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved.
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement.
+**/
+#ifndef __MrcMcConfiguration_h__
+#define __MrcMcConfiguration_h__
+
+#include "MrcTypes.h"
+#include "MrcApi.h"
+#include "McAddress.h"
+#include "MrcAddressDecodeConfiguration.h"
+#include "MrcCommandTraining.h"
+#include "MrcCommon.h"
+#include "MrcGeneral.h"
+#include "MrcGlobal.h"
+#include "MrcOem.h"
+#include "MrcOemIo.h"
+#include "MrcRefreshConfiguration.h"
+#include "MrcSchedulerParameters.h"
+#include "MrcTimingConfiguration.h"
+
+#define DISABLE_ODT_STATIC  (0)     ///< May change in the future
+#define CDIEVSSHI           (2000)  ///< Constant CdieVssHi = 2000 (value in pF)
+#define RCMDREF             (100)   ///< Constant RcmdRef = 100 (value in ohm)
+
+/**
+@brief
+  This function calculates the two numbers that get you closest to the slope.
+
+  @param[in] Slope - targeted slope (multiplied by 100 for int match)
+
+  @retval Returns the Slope Index to be programmed for VtSlope.
+**/
+extern
+U8
+MrcCalcVtSlopeCode (
+  const U16 Slope
+  );
+
+/**
+@brief
+  This function performs the memory controller configuration non training sequence.
+
+  @param[in, out] MrcData - Include all MRC global data.
+
+  @retval MrcStatus - mrcSuccess if successful or an error status
+**/
+extern
+MrcStatus
+MrcMcConfiguration (
+  MrcParameters *const MrcData
+  );
+
+/**
+@brief
+  This function init all the necessary registers for the training.
+
+  @param[in] MrcData - Include all MRC global data.
+
+  @retval mrcSuccess
+**/
+extern
+MrcStatus
+MrcPreTraining (
+  MrcParameters *const MrcData
+  );
+
+/**
+@brief
+  This function initializes all the necessary registers after main training steps but before LCT.
+
+  @param[in] MrcData - Include all MRC global data.
+
+  @retval mrcSuccess
+**/
+extern
+MrcStatus
+MrcPostTraining (
+  MrcParameters *const MrcData
+  );
+
+/**
+@brief
+  Program PCU_CR_DDR_VOLTAGE register.
+
+  @param[in] MrcData    - Include all MRC global data.
+  @param[in] VddVoltage - Current DDR voltage.
+
+  @retval none
+**/
+extern
+void
+MrcSetPcuDdrVoltage (
+  IN OUT MrcParameters *MrcData,
+  IN     MrcVddSelect  VddVoltage
+  );
+
+#endif // __MrcMcConfiguration_h__
diff --git a/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcMemoryMap.h b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcMemoryMap.h
new file mode 100644
index 0000000..0ae9534
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcMemoryMap.h
@@ -0,0 +1,97 @@
+/** @file
+  The physical memory map configuration definitions.
+
+@copyright
+  Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved.
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement.
+**/
+#ifndef _MrcMemoryMap_h_
+#define _MrcMemoryMap_h_
+
+#include "MrcTypes.h"
+#include "MrcApi.h"
+#include "McAddress.h"
+#include "MrcCommon.h"
+#include "MrcOem.h"
+
+#define MEM_4GB (0x1000)  ///< Define the 4 GB size in 1MB units (1000MB = 1GB).
+
+/**
+@brief
+  After BIOS determines the total physical memory size.
+  Determines TOM which is defined by the total physical memory size.
+  Determines TOM minus the ME memory size. The ME memory size is calculated from MESEG_BASE and MESEG_MASK.
+  Determines MMIO allocation, which is system configuration dependent.
+
+  Determines TOLUD which is the minimum value by comparing between "4GB minus MMIO size" and "TOM minus ME size".
+  Determines Graphics Stolen Base, BDSM by subtracting the graphics data stolen memory size from TOLUD.
+  Graphics Data Stolen Memory size is given by GMS field in GGC register.  It must be define before this stage.
+  Determines Graphics GTT Stolen Base, BGSM by subtracting the GTT graphics stolen memory size from BDSM.
+  GTT Stolen Memory size is given by GGMS field in GGC register.  It must be define before this stage.
+  Determines TSEG Base, TSEGMB by subtracting TSEG size from BGSM.
+  TSEG should be defined.
+  Remove the memory hole caused by aligning TSEG to a 8MB boundary.
+  Determine whether Memory Reclaim is available.  If "TOM minus ME Stolem Memory Size" is greater than the value of TOLUD, then memory reclaim is available to enable.
+  Determine REMAPBASE if reclaim is enabled.  This is the maximum value by comparing between 4GB and "TOM minus ME size".
+  Determine REMAPLIMIT () if reclaim is enabled.  This is the value of REMAPBASE plus "the difference between the value in TOLUD register and the lower of either 4GB or 'TOM minus ME Stolen memory size", and then minus 1 boundary.
+  Determine TOUUD. TOUUD indicates the address one byte above the maximum DRAM.  If relcaim is disabled, this value is calculated by "TOM minus ME stolen size".  Otherwise, this value is set to REMAPLIMIT plus 1MB.
+
+  @param[in, out] MrcData - Include all MRC global data. include also the memory map data.
+
+  @retval MrcStatus -  if the reset is succeded.
+**/
+extern
+MrcStatus
+MrcSetMemoryMap (
+  MrcParameters *const MrcData
+  );
+
+/**
+
+@brief
+  This function find the total memory in the system.
+  and write it to TotalPhysicalMemorySize in MrcData structure.
+
+  @param[in, out] MrcData - Include all MRC global data.
+
+  @retval Nothing
+**/
+extern
+void
+MrcTotalMemory (
+  MrcParameters *const MrcData
+  );
+
+/**
+
+@brief
+  this function write to the memory init registers.
+
+  @param[in] PciEBaseAddress  - Address of the PCI Express BAR
+  @param[in] GdxcBaseAddress  - Address of the GDXC BAR
+  @param[in] MemoryMap        - Include all the memory map definitions
+
+  @retval Nothing
+**/
+extern
+void
+UpdateMemoryMapRegisters (
+  const U32                 PciEBaseAddress,
+  const U32                 GdxcBaseAddress,
+  const MrcMemoryMap *const MemoryMap
+  );
+
+#endif // _MrcMemoryMap_h_
diff --git a/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcOem.h b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcOem.h
new file mode 100644
index 0000000..0742d8d
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcOem.h
@@ -0,0 +1,464 @@
+/** @file
+  This file is the OEM interface to the MRC core.
+  This file includes the OEM MRC implementation and can be changed between projects.
+  Each MRC customer must provide those OEM interfaces.
+
+@copyright
+  Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement
+
+**/
+#ifndef _MrcOem_h_
+#define _MrcOem_h_
+
+#include "MrcTypes.h"
+#include "MrcApi.h"
+#include "MrcGlobal.h"
+
+//
+// OEM MMIO routines
+//
+#include "MrcOemMmio.h"
+
+//
+//////////////////////////////////////////////////////////////////////////////////////
+//                               OEM debug print routines and types                 //
+//////////////////////////////////////////////////////////////////////////////////////
+//
+#include "MrcOemDebugPrint.h"
+
+#ifndef MRC_DEBUG_MSG
+#error "MRC_DEBUG_MSG is not defined"
+#endif //MRC_DEBUG_MSG
+///
+//////////////////////////////////////////////////////////////////////////////////////
+///                           OEM platform  routines and types                      //
+//////////////////////////////////////////////////////////////////////////////////////
+///
+/// define the oem check points the OEM can define more point and locate them in the code.
+///
+typedef enum {
+  OemFastBootPermitted,     ///<  before fast boot.
+  OemRestoreNonTraining,
+  OemPrintInputParameters,  ///<  before printing input parameters
+  OemSpdProcessingRun,      ///<  before spd processing code
+  OemSetOverridePreSpd,     ///<  before set overrides pre spd
+  OemMcCapabilityPreSpd,    ///<  before MC capability pre spd
+  OemSetOverride,           ///<  before set overrides
+  OemMcCapability,          ///<  before MC capability
+  OemMcInitRun,             ///<  before mc init code
+  OemMcMemoryMap,           ///<  before memory map
+  OemMcResetRun,            ///<  before jedec reset
+  OemPreTraining,           ///<  before the training.
+  OemMcTrainingRun,         ///<  before training code
+  OemEarlyCommandTraining,  ///<  before Early Command training
+  OemJedecInitLpddr3,       ///<  before Jedec Init Lpddr3
+  OemSenseAmpTraining,      ///<  before Sense Amp Training
+  OemReadMprTraining,       ///<  before Read MPR Training
+  OemReceiveEnable,         ///<  before Read Leveling
+  OemJedecWriteLeveling,    ///<  before Jedec Write Leveling
+  OemWriteLeveling,         ///<  before Functional Write Leveling
+  OemWriteDqDqs,            ///<  before Write Timing Centering
+  OemReadDqDqs,             ///<  before Read Timing Centering
+  OemDimmRonTraining,       ///<  before DIMM Ron algorithm.
+  OemDimmODTTraining,       ///<  before DIMM ODT algorithm.
+  OemDimmODT1dTraining,     ///<  before DIMM ODT 1d algorithm.
+  OemWriteDriveStrength,    ///<  before Write DS
+  OemWriteSlewRate,         ///<  before Write SR
+  OemWriteEQTraining,       ///<  before Write Equalization Training
+  OemReadODTTraining,       ///<  before Read ODT algorithm.
+  OemReadEQTraining,        ///<  before Read Equalization Training
+  OemReadAmplifierPower,    ///<  before Read Amplifier Power
+  OemOptimizeComp,          ///<  before Comp Optimization Training
+  OemPowerSavingMeter,      ///<  before PowerSavingMeter step
+  OemWriteDqDqs2D,          ///<  before Write Timing Centering 2D
+  OemReadDqDqs2D,           ///<  before Read Timing Centering 2D
+  OemCmdVoltCentering,      ///<  before Command Voltage Centering
+  OemWriteVoltCentering2D,  ///<  before Write Voltage Centering 2D
+  OemReadVoltCentering2D,   ///<  before Read Voltage Centering 2D
+  OemLateCommandTraining,   ///<  before Late Command training
+  OemRoundTripLatency,      ///<  before Round Trip Latency Traiing
+  OemTurnAroundTimes,       ///<  before Turn Aorund Times.
+  OemRcvEnCentering1D,      ///<  before Receive Enable Centring 
+  OemSaveMCValues,          ///<  before saving memory controller values
+  OemRmt,                   ///<  before RMT crosser tool.
+  OemMemTest,               ///<  before Memory testing
+  OemRestoreTraining,       ///<  before Restoring Training Values
+  OemSelfRefreshExit,       ///<  before Self Refresh Exit
+  OemNormalMode,            ///<  before Normal Mode on non-cold boots.
+  OemAliasCheck,            ///<  before alias checking on cold boots.
+  OemHwMemInit,
+
+  OemPostTraining,          ///<  after the training.
+  OemMrcActivate,           ///<  before MrcActivate call.
+  OemMrcDone,               ///<  call to MrcOemCheckPoint when MRC was done.
+  OemFrequencySet,          ///<  do operation before frequency set.
+  OemFrequencySetDone,      ///<  do operation after frequency set.
+  OemStartMemoryConfiguration,
+  OemBeforeNormalMode,      ///<  call to MrcOemCheckPoint before normal mode is enalbed
+  OemAfterNormalMode,       ///<  call to MrcOemCheckPoint after normal mode is enalbed
+  OemMrcFillRmt,
+  OemRetrainMarginCheck,
+  ///
+  ///*********************************************************************************
+  ///
+  OemNumOfCommands          ///<  Should always be last in the list!
+} MRC_OemStatusCommand;
+
+///
+/// Define the MRC SMBUS devices type.
+///
+typedef enum {
+  datOemSpd_0_0,      ///< use for get the device address for channel 0 dimm 0
+  datOemSpd_0_1,      ///< use for get the device address for channel 0 dimm 1
+  datOemSpd_1_0,      ///< use for get the device address for channel 1 dimm 0
+  datOemSpd_1_1,      ///< use for get the device address for channel 1 dimm 1
+  datOemVrefWrite_0,  ///< use for get the device address for dimm vref controlled potentiometer channel 0
+  datOemVrefWrite_1,  ///< use for get the device address for dimm vref controlled potentiometer channel 1
+  datOemVrefRead      ///< use for get the device address for cpu vref controlled potentiometer
+} MRC_OemSmbusDeviceType;
+
+///
+//////////////////////////////////////////////////////////////////////////////////////
+///                             OEM IO routines and types                           //
+//////////////////////////////////////////////////////////////////////////////////////
+///
+
+/**
+  8 bit I/O port read.
+     Needs to be ported for OEM platform requirements.
+
+  @param[in] Address - the IO read address.
+
+  @retval return the read value.
+**/
+extern
+U8
+MrcOemInPort8 (
+  IN U16 IoAddress
+  );
+
+/**
+  8 bit I/O port write.
+     Needs to be ported for OEM platform requirements.
+
+  @param[in] IoAddress - The I/O port read address.
+  @param[in] Data      - The value to write.
+
+  @retval Nothing
+**/
+extern
+void
+MrcOemOutPort8 (
+  IN U16 IoAddress,
+  IN U8  data
+  );
+
+/**
+  16 bit I/O port read.
+     Needs to be ported for OEM platform requirements.
+
+  @param[in] IoAddress - The I/O port read address.
+
+  @retval return the read value.
+**/
+extern
+U16
+MrcOemInPort16 (
+  IN U16 IoAddress
+  );
+
+/**
+  16 bit I/O port write.
+     Needs to be ported for OEM platform requirements.
+
+  @param[in] IoAddress - The I/O port read address.
+  @param[in] Data      - The value to write.
+
+  @retval Nothing
+**/
+extern
+void
+MrcOemOutPort16 (
+  IN U16 IoAddress,
+  IN U16 data
+  );
+
+/**
+  32 bit I/O port read.
+     Needs to be ported for OEM platform requirements.
+
+  @param[in] IoAddress - The I/O port read address.
+
+  @retval The value read.
+**/
+extern
+U32
+MrcOemInPort32 (
+  IN U16 IoAddress
+  );
+
+/**
+  32 bit I/O port write.
+     Needs to be ported for OEM platform requirements.
+
+  @param[in] IoAddress - The I/O port read address.
+  @param[in] Data      - The value to write.
+
+  @retval Nothing
+**/
+extern
+void
+MrcOemOutPort32 (
+  IN U16 IoAddress,
+  IN U32 data
+  );
+
+/**
+  This function return the PCI index address.
+     Needs to be ported for OEM platform requirements.
+
+  @param[in] None.
+
+  @retval The PCI index address.
+**/
+extern
+U16
+MrcOemPciIndex (
+  void
+  );
+
+/**
+  This function return the PCI data address.
+     Needs to be ported for OEM platform requirements.
+
+  @param[in] None
+
+  @retval The PCI data address.
+**/
+extern
+U16
+MrcOemPciData (
+  void
+  );
+
+/**
+  This function return the PCI device address.
+      Needs to be ported for OEM platform requirements.
+
+  @param[in] Bus      - PCI bus
+  @param[in] Device   - PCI device
+  @param[in] Function - PCI function
+  @param[in] Offset   - Offset
+
+  @retval The PCI device address.
+**/
+extern
+U32
+MrcOemGetPciDeviceAddress (
+  IN U8 Bus,
+  IN U8 Device,
+  IN U8 Function,
+  IN U8 Offset
+  );
+
+/**
+  This function return the PCIE device address.
+      Needs to be ported for OEM platform requirements.
+
+  @param[in] Bus      - PCI bus
+  @param[in] Device   - PCI device
+  @param[in] Function - PCI function
+  @param[in] Offset   - Offset
+
+  @retval The PCIe device address.
+**/
+extern
+U32
+MrcOemGetPcieDeviceAddress (
+  IN U8 Bus,
+  IN U8 Device,
+  IN U8 Function,
+  IN U8 Offset
+  );
+
+/**
+  Returns the current time, as determined by reading the Real Time Clock (RTC) on the platform.
+  Since RTC time is stored in BCD, convert each value to binary.
+
+  @param[out] Seconds       - The current second (0-59).
+  @param[out] Minutes       - The current minute (0-59).
+  @param[out] Hours         - The current hour (0-23).
+  @param[out] DayOfMonth    - The current day of the month (1-31).
+  @param[out] Month         - The current month (1-12).
+  @param[out] Year          - The current year (2000-2099).
+
+  @retval Nothing
+**/
+extern
+void
+MrcOemGetRtcTime (
+  U8 *Seconds,
+  U8 *Minutes,
+  U8 *Hours,
+  U8 *DayOfMonth,
+  U8 *Month,
+  U16*Year
+  );
+
+///
+//////////////////////////////////////////////////////////////////////////////////////
+///                    OEM Memory routines and types                                //
+//////////////////////////////////////////////////////////////////////////////////////
+///
+
+/**
+  Copy the specified number of memory bytes, a byte at a time, from the
+  specified source to the specified destination.
+     Needs to be ported for OEM platform requirements.
+
+  @param[in, out] Dest            - Destination pointer.
+  @param[in]      Src             - Source pointer.
+  @param[in]      NumBytes        - The number of bytes to copy.
+
+  @retval Nothing
+**/
+extern
+void
+MrcOemMemoryCpy (
+  IN OUT U8  *Dest,
+  IN     U8  *Src,
+  IN     U32 NumBytes
+  );
+
+/**
+  Sets the specified number of memory bytes, a byte at a time, at the
+  specified destination.
+     Needs to be ported for OEM platform requirements.
+
+  @param[in, out] Dest            - Destination pointer.
+  @param[in]      Value           - The value to set.
+  @param[in]      NumBytes        - The number of bytes to set.
+
+  @retval Nothing
+**/
+extern
+void
+MrcOemMemorySet (
+  IN OUT U8  *Dest,
+  IN     U32 Value,
+  IN     U32 NumBytes
+  );
+
+/**
+  Sets the specified number of memory dwords, a dword at a time, at the
+  specified destination.
+
+  @param[in, out] Dest     - Destination pointer.
+  @param[in]      Value    - The value to set.
+  @param[in]      NumWords - The number of dwords to set.
+
+  @retval Nothing.
+**/
+extern
+void
+MrcOemMemorySetWord (
+  IN OUT U16    *Dest,
+  IN const U16  Value,
+  IN U32        NumWords
+  );
+
+/**
+  Sets the specified number of memory dwords, a dword at a time, at the
+  specified destination.
+
+  @param[in, out] Dest      - Destination pointer.
+  @param[in]      Value     - The value to set.
+  @param[in]      NumDwords - The number of dwords to set.
+
+  @retval Nothing.
+**/
+extern
+void
+MrcOemMemorySetDword (
+  IN OUT U32    *Dest,
+  IN const U32  Value,
+  IN U32        NumDwords
+  );
+
+/**
+  Shift the specified data value left by the specified count.
+    Needs to be ported for OEM platform requirements.
+
+  @param[in] Data            - 64 bit number to shift left.
+  @param[in] Count           - Number of bits to shift (0..63)
+
+  @retval The number of bits shifted left.
+**/
+extern
+U64
+MrcOemMemoryLeftShiftU64 (
+  IN const U64 Data,
+  IN const U8  Count
+  );
+
+/**
+  Shift the specified data value Right by the specified count.
+
+  @param[in] Data  - U64 number to shift
+  @param[in] Count - number of bits to shift (0..63)
+
+  @retval Returns the shifted U64 value.
+**/
+extern
+U64
+MrcOemMemoryRightShiftU64 (
+  IN const U64 Data,
+  IN const U8  Count
+  );
+
+/**
+  This function Multiply U64 with a U32 number. Result is <= 64 bits
+  Needs to be ported for OEM platform requirements.
+
+  @param[in] Multiplicand - U64 number to be multiplied with
+  @param[in] Multiplier   - U32 number to multiply
+
+  @retval Returns the multiplication result of U64 value.
+**/
+extern
+U64
+MrcOemMemoryMultiplyU64ByU32 (
+  IN const U64 Multiplicand,
+  IN const U32 Multiplier
+  );
+
+/**
+  Divide U64 with a U64 number. Result is <= 32 bits
+
+  @param[in] Dividend - U64 number to be multiplied with
+  @param[in] Divisor  - U32 number to multiply
+
+  @retval Returns the quotient result of U64 value.
+**/
+extern
+U64
+MrcOemMemoryDivideU64ByU64 (
+  IN const U64 Dividend,
+  IN const U64 Divisor
+  );
+
+#endif // _MrcOem_h_
diff --git a/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcRegisters/McGdxcbar.h b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcRegisters/McGdxcbar.h
new file mode 100644
index 0000000..fd91eba
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcRegisters/McGdxcbar.h
@@ -0,0 +1,2849 @@
+/** @file
+  This file was automatically generated. Modify at your own risk.
+
+@copyright
+  Copyright (c) 2010 - 2012 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement
+**/
+#ifndef __McGdxcbar_h__
+#define __McGdxcbar_h__
+
+#pragma pack(push, 1)
+#include "MrcTypes.h"
+
+typedef union {
+  struct {
+    U32 Tx_Delay_R0                             :  8;  // Bits 7:0
+    U32 Tx_Delay_R1                             :  8;  // Bits 15:8
+    U32 Tx_Delay_R2                             :  8;  // Bits 23:16
+    U32 Tx_Delay_R3                             :  8;  // Bits 31:24
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRPL_CR_DDR_TX_DELAY_STRUCT;
+
+typedef union {
+  struct {
+    U32 EN_SW_GDXC                              :  1;  // Bits 0:0
+    U32 EN_RING_ADQ                             :  1;  // Bits 1:1
+    U32 EN_RING_BLQ                             :  1;  // Bits 2:2
+    U32 EN_RING_AKQ                             :  1;  // Bits 3:3
+    U32 EN_RING_IVQ                             :  1;  // Bits 4:4
+    U32 EN_IDIQ                                 :  1;  // Bits 5:5
+    U32 EN_mc_UCLKQ                             :  1;  // Bits 6:6
+    U32                                         :  1;  // Bits 7:7
+    U32 UP_EN_ADQ                               :  1;  // Bits 8:8
+    U32 DN_EN_ADQ                               :  1;  // Bits 9:9
+    U32 UP_EN_BLQ                               :  1;  // Bits 10:10
+    U32 DN_EN_BLQ                               :  1;  // Bits 11:11
+    U32 UP_EN_AKQ                               :  1;  // Bits 12:12
+    U32 DN_EN_AKQ                               :  1;  // Bits 13:13
+    U32 MOTQ_TIMING_SELECT                      :  1;  // Bits 14:14
+    U32                                         :  1;  // Bits 15:15
+    U32 SPARE                                   :  8;  // Bits 23:16
+    U32                                         :  8;  // Bits 31:24
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MPCOHTRK_CR_GDXC_SW_ENABLE_STRUCT;
+
+typedef union {
+  struct {
+    U32 EN_Core0_T0                             :  1;  // Bits 0:0
+    U32 EN_Core0_T1                             :  1;  // Bits 1:1
+    U32 EN_Core1_T0                             :  1;  // Bits 2:2
+    U32 EN_Core1_T1                             :  1;  // Bits 3:3
+    U32 EN_Core2_T0                             :  1;  // Bits 4:4
+    U32 EN_Core2_T1                             :  1;  // Bits 5:5
+    U32 EN_Core3_T0                             :  1;  // Bits 6:6
+    U32 EN_Core3_T1                             :  1;  // Bits 7:7
+    U32 EN_GT                                   :  1;  // Bits 8:8
+    U32 MEM_CHR_RD                              :  1;  // Bits 9:9
+    U32 MEM_CHR_WR                              :  1;  // Bits 10:10
+    U32 MEM_NC                                  :  1;  // Bits 11:11
+    U32 EN_CBO_Exp_WB                           :  1;  // Bits 12:12
+    U32 SNP_Access                              :  1;  // Bits 13:13
+    U32 AD_EODLAT                               :  1;  // Bits 14:14
+    U32                                         :  17;  // Bits 31:15
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_STRUCT;
+
+typedef union {
+  struct {
+    U32 CR_CHR_RD                               :  3;  // Bits 2:0
+    U32 CHR_RD_STAT_MOD                         :  1;  // Bits 3:3
+    U32 CR_CHR_WR                               :  4;  // Bits 7:4
+    U32 CR_NC_RD                                :  3;  // Bits 10:8
+    U32 NC_RD_STAT_MOD                          :  1;  // Bits 11:11
+    U32 CR_NC_WR                                :  4;  // Bits 15:12
+    U32 NC_WR_STAT_MOD                          :  1;  // Bits 16:16
+    U32 Data_Core0                              :  1;  // Bits 17:17
+    U32 Data_Core1                              :  1;  // Bits 18:18
+    U32 Data_Core2                              :  1;  // Bits 19:19
+    U32 Data_Core3                              :  1;  // Bits 20:20
+    U32 Data_CBO                                :  1;  // Bits 21:21
+    U32 Data_GT                                 :  1;  // Bits 22:22
+    U32                                         :  9;  // Bits 31:23
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MPCOHTRK_CR_GDXC_QUALIFIER_BL_STRUCT;
+
+typedef union {
+  struct {
+    U32 OVF_Global                              :  1;  // Bits 0:0
+    U32 OVF_Ring_AD                             :  1;  // Bits 1:1
+    U32 OVF_Ring_BL                             :  1;  // Bits 2:2
+    U32 OVF_Ring_AK                             :  1;  // Bits 3:3
+    U32 OVF_Ring_IV                             :  1;  // Bits 4:4
+    U32                                         :  4;  // Bits 8:5
+    U32 OVF_IDI_center                          :  1;  // Bits 9:9
+    U32 OVF_mcUCLK                              :  1;  // Bits 10:10
+    U32 OVF_PWR_mcFCLK                          :  1;  // Bits 11:11
+    U32                                         :  20;  // Bits 31:12
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MPCOHTRK_CR_GDXC_OVF_STATUS_STRUCT;
+
+typedef union {
+  struct {
+    U32 MEM_PTR                                 :  32;  // Bits 31:0
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MPCOHTRK_CR_GDXC_MOT_ADDRESS_LO_STRUCT;
+
+typedef union {
+  struct {
+    U32 MEM_PTR                                 :  1;  // Bits 0:0
+    U32 BUFFER_WRAP                             :  1;  // Bits 1:1
+    U32 SPARE                                   :  30;  // Bits 31:2
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MPCOHTRK_CR_GDXC_MOT_ADDRESS_HI_STRUCT;
+
+typedef union {
+  struct {
+    U32 START_ADDRESS                           :  16;  // Bits 15:0
+    U32 END_ADDRESS                             :  16;  // Bits 31:16
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MPCOHTRK_CR_GDXC_MOT_REGION_STRUCT;
+
+typedef union {
+  struct {
+    U32 MEM_PTR                                 :  32;  // Bits 31:0
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MPCOHTRK_CR_GDXC_OCLA_ADDRESS_LO_STRUCT;
+
+typedef union {
+  struct {
+    U32 MEM_PTR                                 :  1;  // Bits 0:0
+    U32 BUFFER_WRAP                             :  1;  // Bits 1:1
+    U32 LOCK                                    :  1;  // Bits 2:2
+    U32 SPARE                                   :  29;  // Bits 31:3
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MPCOHTRK_CR_GDXC_OCLA_ADDRESS_HI_STRUCT;
+
+typedef union {
+  struct {
+    U32 START_ADDRESS                           :  16;  // Bits 15:0
+    U32 END_ADDRESS                             :  16;  // Bits 31:16
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MPCOHTRK_CR_GDXC_OCLA_REGION_STRUCT;
+
+typedef union {
+  struct {
+    U32 ARM_bits_packet                         :  32;  // Bits 31:0
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} GODLAT_CR_G_ODLAT_ARM_S0L_STRUCT;
+
+typedef union {
+  struct {
+    U32 ARM_bits_packet                         :  32;  // Bits 31:0
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} GODLAT_CR_G_ODLAT_ARM_S0H_STRUCT;
+
+typedef union {
+  struct {
+    U32 Mask_bits                               :  32;  // Bits 31:0
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} GODLAT_CR_G_ODLAT_MASK_S0L_STRUCT;
+
+typedef union {
+  struct {
+    U32 Mask_bits                               :  32;  // Bits 31:0
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} GODLAT_CR_G_ODLAT_MASK_S0H_STRUCT;
+
+typedef union {
+  struct {
+    U32 ARM_bits_packet                         :  32;  // Bits 31:0
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} GODLAT_CR_G_ODLAT_ARM_S1L_STRUCT;
+
+typedef union {
+  struct {
+    U32 ARM_bits_packet                         :  32;  // Bits 31:0
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} GODLAT_CR_G_ODLAT_ARM_S1H_STRUCT;
+
+typedef union {
+  struct {
+    U32 Mask_bits                               :  32;  // Bits 31:0
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} GODLAT_CR_G_ODLAT_MASK_S1L_STRUCT;
+
+typedef union {
+  struct {
+    U32 Mask_bits                               :  32;  // Bits 31:0
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} GODLAT_CR_G_ODLAT_MASK_S1H_STRUCT;
+
+typedef union {
+  struct {
+    U32 ARM_bits_packet                         :  32;  // Bits 31:0
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} GODLAT_CR_G_ODLAT_ARM_S2L_STRUCT;
+
+typedef union {
+  struct {
+    U32 ARM_bits_packet                         :  32;  // Bits 31:0
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} GODLAT_CR_G_ODLAT_ARM_S2H_STRUCT;
+
+typedef union {
+  struct {
+    U32 Mask_bits                               :  32;  // Bits 31:0
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} GODLAT_CR_G_ODLAT_MASK_S2L_STRUCT;
+
+typedef union {
+  struct {
+    U32 Mask_bits                               :  32;  // Bits 31:0
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} GODLAT_CR_G_ODLAT_MASK_S2H_STRUCT;
+
+typedef union {
+  struct {
+    U32 ARM_bits_packet                         :  32;  // Bits 31:0
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} GODLAT_CR_G_ODLAT_ARM_S3L_STRUCT;
+
+typedef union {
+  struct {
+    U32 ARM_bits_packet                         :  32;  // Bits 31:0
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} GODLAT_CR_G_ODLAT_ARM_S3H_STRUCT;
+
+typedef union {
+  struct {
+    U32 Mask_bits                               :  32;  // Bits 31:0
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} GODLAT_CR_G_ODLAT_MASK_S3L_STRUCT;
+
+typedef union {
+  struct {
+    U32 Mask_bits                               :  32;  // Bits 31:0
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} GODLAT_CR_G_ODLAT_MASK_S3H_STRUCT;
+
+typedef union {
+  struct {
+    U32 ARM_bits_packet                         :  32;  // Bits 31:0
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} GODLAT_CR_G_ODLAT_ARM_S4L_STRUCT;
+
+typedef union {
+  struct {
+    U32 ARM_bits_packet                         :  32;  // Bits 31:0
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} GODLAT_CR_G_ODLAT_ARM_S4H_STRUCT;
+
+typedef union {
+  struct {
+    U32 Mask_bits                               :  32;  // Bits 31:0
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} GODLAT_CR_G_ODLAT_MASK_S4L_STRUCT;
+
+typedef union {
+  struct {
+    U32 Mask_bits                               :  32;  // Bits 31:0
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} GODLAT_CR_G_ODLAT_MASK_S4H_STRUCT;
+
+typedef union {
+  struct {
+    U32 ARM_bits_packet                         :  32;  // Bits 31:0
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} GODLAT_CR_G_ODLAT_ARM_S5L_STRUCT;
+
+typedef union {
+  struct {
+    U32 ARM_bits_packet                         :  32;  // Bits 31:0
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} GODLAT_CR_G_ODLAT_ARM_S5H_STRUCT;
+
+typedef union {
+  struct {
+    U32 Mask_bits                               :  32;  // Bits 31:0
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} GODLAT_CR_G_ODLAT_MASK_S5L_STRUCT;
+
+typedef union {
+  struct {
+    U32 Mask_bits                               :  32;  // Bits 31:0
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} GODLAT_CR_G_ODLAT_MASK_S5H_STRUCT;
+
+typedef union {
+  struct {
+    U32 ARM_bits_packet                         :  32;  // Bits 31:0
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} GODLAT_CR_G_ODLAT_ARM_S6L_STRUCT;
+
+typedef union {
+  struct {
+    U32 ARM_bits_packet                         :  32;  // Bits 31:0
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} GODLAT_CR_G_ODLAT_ARM_S6H_STRUCT;
+
+typedef union {
+  struct {
+    U32 Mask_bits                               :  32;  // Bits 31:0
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} GODLAT_CR_G_ODLAT_MASK_S6L_STRUCT;
+
+typedef union {
+  struct {
+    U32 Mask_bits                               :  32;  // Bits 31:0
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} GODLAT_CR_G_ODLAT_MASK_S6H_STRUCT;
+
+typedef union {
+  struct {
+    U32 ARM_bits_packet                         :  32;  // Bits 31:0
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} GODLAT_CR_G_ODLAT_ARM_S7L_STRUCT;
+
+typedef union {
+  struct {
+    U32 ARM_bits_packet                         :  32;  // Bits 31:0
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} GODLAT_CR_G_ODLAT_ARM_S7H_STRUCT;
+
+typedef union {
+  struct {
+    U32 Mask_bits                               :  32;  // Bits 31:0
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} GODLAT_CR_G_ODLAT_MASK_S7L_STRUCT;
+
+typedef union {
+  struct {
+    U32 Mask_bits                               :  32;  // Bits 31:0
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} GODLAT_CR_G_ODLAT_MASK_S7H_STRUCT;
+
+typedef union {
+  struct {
+    U32 UX_TMR_BASE_A                           :  1;  // Bits 0:0
+    U32 UX_TMR_BASE_B                           :  1;  // Bits 1:1
+    U32 OVF_ARM_IDI                             :  1;  // Bits 2:2
+    U32 OVF_ARM_HIGH                            :  5;  // Bits 7:3
+    U32 OVF_Mask_HIGH                           :  5;  // Bits 12:8
+    U32                                         :  5;  // Bits 17:13
+    U32 TimerA_units                            :  3;  // Bits 20:18
+    U32 TimerB_units                            :  3;  // Bits 23:21
+    U32 Which_Time_Base                         :  4;  // Bits 27:24
+    U32 Tmr_Or_Cntr_Mode                        :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} GODLAT_CR_G_ODLAT_CMD_STRUCT;
+
+typedef union {
+  struct {
+    U32 EN_SW_G_ODLAT                           :  1;  // Bits 0:0
+    U32                                         :  7;  // Bits 7:1
+    U32 EN_S0                                   :  1;  // Bits 8:8
+    U32 EN_S1                                   :  1;  // Bits 9:9
+    U32 EN_S2                                   :  1;  // Bits 10:10
+    U32 EN_S3                                   :  1;  // Bits 11:11
+    U32 EN_S4                                   :  1;  // Bits 12:12
+    U32 EN_S5                                   :  1;  // Bits 13:13
+    U32 EN_S6                                   :  1;  // Bits 14:14
+    U32 EN_S7                                   :  1;  // Bits 15:15
+    U32 MBP_Enable                              :  1;  // Bits 16:16
+    U32                                         :  15;  // Bits 31:17
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} GODLAT_CR_G_ODLAT_SW_ENABLE_STRUCT;
+
+typedef union {
+  struct {
+    U32 Pulse_or_Sticky_Events                  :  8;  // Bits 7:0
+    U32 Pulse_or_Sticky_MBP                     :  1;  // Bits 8:8
+    U32 Pulse_or_Sticky_TO                      :  4;  // Bits 12:9
+    U32 OVF_ARM_LOW                             :  3;  // Bits 15:13
+    U32 OVF_MASK_LOW                            :  3;  // Bits 18:16
+    U32 Which_MBP_Pin_A                         :  3;  // Bits 21:19
+    U32 Which_MBP_Pin_B                         :  3;  // Bits 24:22
+    U32 Which_MBP_Pin_C                         :  3;  // Bits 27:25
+    U32 Which_MBP_Pin_D                         :  3;  // Bits 30:28
+    U32                                         :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} GODLAT_CR_G_ODLAT_MISC_CMD_STRUCT;
+
+typedef union {
+  struct {
+    U32 Ln0Mask                                 :  8;  // Bits 7:0
+    U32 Ln1Mask                                 :  8;  // Bits 15:8
+    U32 AssertMode                              :  1;  // Bits 16:16
+    U32 CompEn                                  :  1;  // Bits 17:17
+    U32 GT_VISA_En                              :  1;  // Bits 18:18
+    U32                                         :  13;  // Bits 31:19
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} GDXC_CR_GT_VISA2OCLA_CFG_FILTER_STRUCT;
+
+typedef union {
+  struct {
+    U32 Man_Reset_GDXC                          :  1;  // Bits 0:0
+    U32 Man_Reset_G_ODLAT                       :  1;  // Bits 1:1
+    U32 IOT_Start                               :  1;  // Bits 2:2
+    U32 IOT_Stop                                :  1;  // Bits 3:3
+    U32 IOT_Trigger                             :  1;  // Bits 4:4
+    U32 IOT_Force_Flush                         :  1;  // Bits 5:5
+    U32                                         :  10;  // Bits 15:6
+    U32 SPARE                                   :  8;  // Bits 23:16
+    U32                                         :  8;  // Bits 31:24
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} GDXC_CR_GDXC_MAN_CONFIG_STRUCT;
+
+typedef union {
+  struct {
+    U32 mbpout                                  :  2;  // Bits 1:0
+    U32                                         :  30;  // Bits 31:2
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} GDXC_CR_GDXC_ALIGN_STRUCT;
+
+typedef union {
+  struct {
+    U32 AD                                      :  6;  // Bits 5:0
+    U32 BLHDR0                                  :  7;  // Bits 12:6
+    U32 BLHDR1ADDR                              :  6;  // Bits 18:13
+    U32 AK                                      :  6;  // Bits 24:19
+    U32 IV                                      :  2;  // Bits 26:25
+    U32 Wrap                                    :  3;  // Bits 29:27
+    U32 MOT                                     :  5;  // Bits 34:30
+    U32 IDI                                     :  5;  // Bits 39:35
+    U32 FClk                                    :  5;  // Bits 44:40
+    U32 UClkMsgCh                               :  5;  // Bits 49:45
+    U32                                         :  14;  // Bits 63:50
+  } Bits;
+  U64 Data;
+  U32 Data32[2];
+  U16 Data16[4];
+  U8  Data8[8];
+} GDXC_CR_GDXC_RR_ARB_THRESH_STRUCT;
+
+typedef union {
+  struct {
+    U32 Start_Status                            :  1;  // Bits 0:0
+    U32 Trigger_Status                          :  1;  // Bits 1:1
+    U32 Stop_Status                             :  1;  // Bits 2:2
+    U32 Muliple_Hit                             :  1;  // Bits 3:3
+    U32 Bubbles_Status                          :  6;  // Bits 9:4
+    U32                                         :  22;  // Bits 31:10
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} GDXC_CR_G_ODLAT_FIRE_STATUS_STRUCT;
+
+typedef union {
+  struct {
+    U32 Delay_count                             :  25;  // Bits 24:0
+    U32                                         :  7;  // Bits 31:25
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} GDXC_CR_TRIGGER_TO_STOP_DELAY_STRUCT;
+
+typedef union {
+  struct {
+    U32 Disabled                                :  1;  // Bits 0:0
+    U32 Idle                                    :  1;  // Bits 1:1
+    U32 Running                                 :  1;  // Bits 2:2
+    U32 IOT_Triggered                           :  1;  // Bits 3:3
+    U32 Sticky_triggered                        :  1;  // Bits 4:4
+    U32                                         :  1;  // Bits 5:5
+    U32 Remaining_count                         :  25;  // Bits 30:6
+    U32                                         :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} GDXC_CR_IOT_STATUS_STRUCT;
+
+typedef union {
+  struct {
+    U32 S0_OclaHdr                              :  8;  // Bits 7:0
+    U32 S1_OclaHdr                              :  8;  // Bits 15:8
+    U32 S2_OclaHdr                              :  8;  // Bits 23:16
+    U32 S3_OclaHdr                              :  8;  // Bits 31:24
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} GODLAT_CR_G_ODLAT_OCLAHDR_S0TO3_STRUCT;
+
+typedef union {
+  struct {
+    U32 S4_OclaHdr                              :  8;  // Bits 7:0
+    U32 S5_OclaHdr                              :  8;  // Bits 15:8
+    U32 S6_OclaHdr                              :  8;  // Bits 23:16
+    U32 S7_OclaHdr                              :  8;  // Bits 31:24
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} GODLAT_CR_G_ODLAT_OCLAHDR_S4TO7_STRUCT;
+
+typedef union {
+  struct {
+    U32 S0_FST                                  :  2;  // Bits 1:0
+    U32 S1_FST                                  :  2;  // Bits 3:2
+    U32 S2_FST                                  :  2;  // Bits 5:4
+    U32 S3_FST                                  :  2;  // Bits 7:6
+    U32 S4_FST                                  :  2;  // Bits 9:8
+    U32 S5_FST                                  :  2;  // Bits 11:10
+    U32 S6_FST                                  :  2;  // Bits 13:12
+    U32 S7_FST                                  :  2;  // Bits 15:14
+    U32                                         :  16;  // Bits 31:16
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} GODLAT_CR_G_ODLAT_FST_STRUCT;
+
+typedef union {
+  struct {
+    U32 Arm                                     :  8;  // Bits 7:0
+    U32 MBP_Arm                                 :  1;  // Bits 8:8
+    U32 TO_Arm                                  :  4;  // Bits 12:9
+    U32                                         :  3;  // Bits 15:13
+    U32 Mask                                    :  8;  // Bits 23:16
+    U32 MBP_Mask                                :  1;  // Bits 24:24
+    U32 TO_Mask                                 :  4;  // Bits 28:25
+    U32                                         :  3;  // Bits 31:29
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B0_STRUCT;
+
+typedef union {
+  struct {
+    U32 Arm                                     :  8;  // Bits 7:0
+    U32 MBP_Arm                                 :  1;  // Bits 8:8
+    U32 TO_Arm                                  :  4;  // Bits 12:9
+    U32                                         :  3;  // Bits 15:13
+    U32 Mask                                    :  8;  // Bits 23:16
+    U32 MBP_Mask                                :  1;  // Bits 24:24
+    U32 TO_Mask                                 :  4;  // Bits 28:25
+    U32                                         :  3;  // Bits 31:29
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B1_STRUCT;
+
+typedef union {
+  struct {
+    U32 Arm                                     :  8;  // Bits 7:0
+    U32 MBP_Arm                                 :  1;  // Bits 8:8
+    U32 TO_Arm                                  :  4;  // Bits 12:9
+    U32                                         :  3;  // Bits 15:13
+    U32 Mask                                    :  8;  // Bits 23:16
+    U32 MBP_Mask                                :  1;  // Bits 24:24
+    U32 TO_Mask                                 :  4;  // Bits 28:25
+    U32                                         :  3;  // Bits 31:29
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B2_STRUCT;
+
+typedef union {
+  struct {
+    U32 Arm                                     :  8;  // Bits 7:0
+    U32 MBP_Arm                                 :  1;  // Bits 8:8
+    U32 TO_Arm                                  :  4;  // Bits 12:9
+    U32                                         :  3;  // Bits 15:13
+    U32 Mask                                    :  8;  // Bits 23:16
+    U32 MBP_Mask                                :  1;  // Bits 24:24
+    U32 TO_Mask                                 :  4;  // Bits 28:25
+    U32                                         :  3;  // Bits 31:29
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B3_STRUCT;
+
+typedef union {
+  struct {
+    U32 Arm                                     :  8;  // Bits 7:0
+    U32 MBP_Arm                                 :  1;  // Bits 8:8
+    U32 TO_Arm                                  :  4;  // Bits 12:9
+    U32                                         :  3;  // Bits 15:13
+    U32 Mask                                    :  8;  // Bits 23:16
+    U32 MBP_Mask                                :  1;  // Bits 24:24
+    U32 TO_Mask                                 :  4;  // Bits 28:25
+    U32                                         :  3;  // Bits 31:29
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B4_STRUCT;
+
+typedef union {
+  struct {
+    U32 Arm                                     :  8;  // Bits 7:0
+    U32 MBP_Arm                                 :  1;  // Bits 8:8
+    U32 TO_Arm                                  :  4;  // Bits 12:9
+    U32                                         :  3;  // Bits 15:13
+    U32 Mask                                    :  8;  // Bits 23:16
+    U32 MBP_Mask                                :  1;  // Bits 24:24
+    U32 TO_Mask                                 :  4;  // Bits 28:25
+    U32                                         :  3;  // Bits 31:29
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B5_STRUCT;
+
+typedef union {
+  struct {
+    U32 Arm                                     :  8;  // Bits 7:0
+    U32 MBP_Arm                                 :  1;  // Bits 8:8
+    U32 TO_Arm                                  :  4;  // Bits 12:9
+    U32 Stop                                    :  1;  // Bits 13:13
+    U32                                         :  2;  // Bits 15:14
+    U32 Mask                                    :  8;  // Bits 23:16
+    U32 MBP_Mask                                :  1;  // Bits 24:24
+    U32 TO_Mask                                 :  4;  // Bits 28:25
+    U32 Col_Rst                                 :  1;  // Bits 29:29
+    U32 Trigger                                 :  1;  // Bits 30:30
+    U32 Start                                   :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B0_STRUCT;
+
+typedef union {
+  struct {
+    U32 Arm                                     :  8;  // Bits 7:0
+    U32 MBP_Arm                                 :  1;  // Bits 8:8
+    U32 TO_Arm                                  :  4;  // Bits 12:9
+    U32                                         :  3;  // Bits 15:13
+    U32 Mask                                    :  8;  // Bits 23:16
+    U32 MBP_Mask                                :  1;  // Bits 24:24
+    U32 TO_Mask                                 :  4;  // Bits 28:25
+    U32                                         :  3;  // Bits 31:29
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B0_STRUCT;
+
+typedef union {
+  struct {
+    U32 Arm                                     :  8;  // Bits 7:0
+    U32 MBP_Arm                                 :  1;  // Bits 8:8
+    U32 TO_Arm                                  :  4;  // Bits 12:9
+    U32                                         :  3;  // Bits 15:13
+    U32 Mask                                    :  8;  // Bits 23:16
+    U32 MBP_Mask                                :  1;  // Bits 24:24
+    U32 TO_Mask                                 :  4;  // Bits 28:25
+    U32                                         :  3;  // Bits 31:29
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B1_STRUCT;
+
+typedef union {
+  struct {
+    U32 Arm                                     :  8;  // Bits 7:0
+    U32 MBP_Arm                                 :  1;  // Bits 8:8
+    U32 TO_Arm                                  :  4;  // Bits 12:9
+    U32                                         :  3;  // Bits 15:13
+    U32 Mask                                    :  8;  // Bits 23:16
+    U32 MBP_Mask                                :  1;  // Bits 24:24
+    U32 TO_Mask                                 :  4;  // Bits 28:25
+    U32                                         :  3;  // Bits 31:29
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B2_STRUCT;
+
+typedef union {
+  struct {
+    U32 Arm                                     :  8;  // Bits 7:0
+    U32 MBP_Arm                                 :  1;  // Bits 8:8
+    U32 TO_Arm                                  :  4;  // Bits 12:9
+    U32                                         :  3;  // Bits 15:13
+    U32 Mask                                    :  8;  // Bits 23:16
+    U32 MBP_Mask                                :  1;  // Bits 24:24
+    U32 TO_Mask                                 :  4;  // Bits 28:25
+    U32                                         :  3;  // Bits 31:29
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B3_STRUCT;
+
+typedef union {
+  struct {
+    U32 Arm                                     :  8;  // Bits 7:0
+    U32 MBP_Arm                                 :  1;  // Bits 8:8
+    U32 TO_Arm                                  :  4;  // Bits 12:9
+    U32                                         :  3;  // Bits 15:13
+    U32 Mask                                    :  8;  // Bits 23:16
+    U32 MBP_Mask                                :  1;  // Bits 24:24
+    U32 TO_Mask                                 :  4;  // Bits 28:25
+    U32                                         :  3;  // Bits 31:29
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B4_STRUCT;
+
+typedef union {
+  struct {
+    U32 Arm                                     :  8;  // Bits 7:0
+    U32 MBP_Arm                                 :  1;  // Bits 8:8
+    U32 TO_Arm                                  :  4;  // Bits 12:9
+    U32                                         :  3;  // Bits 15:13
+    U32 Mask                                    :  8;  // Bits 23:16
+    U32 MBP_Mask                                :  1;  // Bits 24:24
+    U32 TO_Mask                                 :  4;  // Bits 28:25
+    U32                                         :  3;  // Bits 31:29
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B5_STRUCT;
+
+typedef union {
+  struct {
+    U32 Arm                                     :  8;  // Bits 7:0
+    U32 MBP_Arm                                 :  1;  // Bits 8:8
+    U32 TO_Arm                                  :  4;  // Bits 12:9
+    U32 Stop                                    :  1;  // Bits 13:13
+    U32                                         :  2;  // Bits 15:14
+    U32 Mask                                    :  8;  // Bits 23:16
+    U32 MBP_Mask                                :  1;  // Bits 24:24
+    U32 TO_Mask                                 :  4;  // Bits 28:25
+    U32 Col_Rst                                 :  1;  // Bits 29:29
+    U32 Trigger                                 :  1;  // Bits 30:30
+    U32 Start                                   :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B1_STRUCT;
+
+typedef union {
+  struct {
+    U32 B0_Set                                  :  6;  // Bits 5:0
+    U32 B0_Rst                                  :  6;  // Bits 11:6
+    U32 B1_Set                                  :  6;  // Bits 17:12
+    U32 B1_Rst                                  :  6;  // Bits 23:18
+    U32                                         :  8;  // Bits 31:24
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} GODLAT_CR_G_ODLAT_TR_IF_MODE_B0_B1_STRUCT;
+
+typedef union {
+  struct {
+    U32 B2_Set                                  :  6;  // Bits 5:0
+    U32 B2_Rst                                  :  6;  // Bits 11:6
+    U32 B3_Set                                  :  6;  // Bits 17:12
+    U32 B3_Rst                                  :  6;  // Bits 23:18
+    U32                                         :  8;  // Bits 31:24
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} GODLAT_CR_G_ODLAT_TR_IF_MODE_B2_B3_STRUCT;
+
+typedef union {
+  struct {
+    U32 B4_Set                                  :  6;  // Bits 5:0
+    U32 B4_Rst                                  :  6;  // Bits 11:6
+    U32 B5_Set                                  :  6;  // Bits 17:12
+    U32 B5_Rst                                  :  6;  // Bits 23:18
+    U32                                         :  8;  // Bits 31:24
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} GODLAT_CR_G_ODLAT_TR_IF_MODE_B4_B5_STRUCT;
+
+typedef union {
+  struct {
+    U32 ElseIf_ElseIf_B0_Set                    :  6;  // Bits 5:0
+    U32 ElseIf_ElseIf_B0_Rst                    :  6;  // Bits 11:6
+    U32                                         :  20;  // Bits 31:12
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} GODLAT_CR_G_ODLAT_TR_IF_MODE_B6_B7_STRUCT;
+
+typedef union {
+  struct {
+    U32 B0_Set                                  :  6;  // Bits 5:0
+    U32 B0_Rst                                  :  6;  // Bits 11:6
+    U32 B1_Set                                  :  6;  // Bits 17:12
+    U32 B1_Rst                                  :  6;  // Bits 23:18
+    U32                                         :  8;  // Bits 31:24
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_B0_B1_STRUCT;
+
+typedef union {
+  struct {
+    U32 B2_Set                                  :  6;  // Bits 5:0
+    U32 B2_Rst                                  :  6;  // Bits 11:6
+    U32 B3_Set                                  :  6;  // Bits 17:12
+    U32 B3_Rst                                  :  6;  // Bits 23:18
+    U32                                         :  8;  // Bits 31:24
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_B2_B3_STRUCT;
+
+typedef union {
+  struct {
+    U32 B4_Set                                  :  6;  // Bits 5:0
+    U32 B4_Rst                                  :  6;  // Bits 11:6
+    U32 B5_Set                                  :  6;  // Bits 17:12
+    U32 B5_Rst                                  :  6;  // Bits 23:18
+    U32                                         :  8;  // Bits 31:24
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_B4_B5_STRUCT;
+
+typedef union {
+  struct {
+    U32 ElseIf_ElseIf_B1_Set                    :  6;  // Bits 5:0
+    U32 ElseIf_ElseIf_B1_Rst                    :  6;  // Bits 11:6
+    U32                                         :  20;  // Bits 31:12
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_B6_B7_STRUCT;
+
+typedef union {
+  struct {
+    U32 Init_Bits                               :  6;  // Bits 5:0
+    U32                                         :  26;  // Bits 31:6
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} GODLAT_CR_G_ODLAT_INIT_BUBBLES_STRUCT;
+
+typedef union {
+  struct {
+    U32 ColRst                                  :  6;  // Bits 5:0
+    U32 Start                                   :  6;  // Bits 11:6
+    U32 Trigger                                 :  6;  // Bits 17:12
+    U32 Stop                                    :  6;  // Bits 23:18
+    U32                                         :  8;  // Bits 31:24
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} GODLAT_CR_G_ODLAT_TR_IF_MODE_MISC_STRUCT;
+
+typedef union {
+  struct {
+    U32 ColRst                                  :  6;  // Bits 5:0
+    U32 Start                                   :  6;  // Bits 11:6
+    U32 Trigger                                 :  6;  // Bits 17:12
+    U32 Stop                                    :  6;  // Bits 23:18
+    U32                                         :  8;  // Bits 31:24
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_MISC_STRUCT;
+
+typedef union {
+  struct {
+    U32 B0_EN                                   :  4;  // Bits 3:0
+    U32 B1_EN                                   :  4;  // Bits 7:4
+    U32 B2_EN                                   :  4;  // Bits 11:8
+    U32 B3_EN                                   :  4;  // Bits 15:12
+    U32 B4_EN                                   :  4;  // Bits 19:16
+    U32 B5_EN                                   :  4;  // Bits 23:20
+    U32 ELSEIF_ELSEIF_B0_EN                     :  4;  // Bits 27:24
+    U32                                         :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} GODLAT_CR_G_ODLAT_TR_IF_MODE_TMREN_STRUCT;
+
+typedef union {
+  struct {
+    U32 B0_EN                                   :  4;  // Bits 3:0
+    U32 B1_EN                                   :  4;  // Bits 7:4
+    U32 B2_EN                                   :  4;  // Bits 11:8
+    U32 B3_EN                                   :  4;  // Bits 15:12
+    U32 B4_EN                                   :  4;  // Bits 19:16
+    U32 B5_EN                                   :  4;  // Bits 23:20
+    U32 ELSEIF_ELSEIF_B1_EN                     :  4;  // Bits 27:24
+    U32                                         :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_TMREN_STRUCT;
+
+typedef union {
+  struct {
+    U32 Timer0_load                             :  5;  // Bits 4:0
+    U32 Timer1_load                             :  5;  // Bits 9:5
+    U32 Timer2_load                             :  5;  // Bits 14:10
+    U32 Timer3_load                             :  16;  // Bits 30:15
+    U32                                         :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} GODLAT_CR_G_ODLAT_TIMER_PRELOAD_STRUCT;
+
+typedef union {
+  struct {
+    U32 MOT_PKT                                 :  8;  // Bits 7:0
+    U32                                         :  24;  // Bits 31:8
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} GODLAT_CR_G_ODLAT_MOT_HDR_HIT_STRUCT;
+
+typedef union {
+  struct {
+    U32 B0_RST                                  :  4;  // Bits 3:0
+    U32 B1_RST                                  :  4;  // Bits 7:4
+    U32 B2_RST                                  :  4;  // Bits 11:8
+    U32 B3_RST                                  :  4;  // Bits 15:12
+    U32 B4_RST                                  :  4;  // Bits 19:16
+    U32 B5_RST                                  :  4;  // Bits 23:20
+    U32 ELSEIF_ELSEIF_B0_RST                    :  4;  // Bits 27:24
+    U32                                         :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} GODLAT_CR_G_ODLAT_TR_IF_MODE_TMRRST_STRUCT;
+
+typedef union {
+  struct {
+    U32 B0_RST                                  :  4;  // Bits 3:0
+    U32 B1_RST                                  :  4;  // Bits 7:4
+    U32 B2_RST                                  :  4;  // Bits 11:8
+    U32 B3_RST                                  :  4;  // Bits 15:12
+    U32 B4_RST                                  :  4;  // Bits 19:16
+    U32 B5_RST                                  :  4;  // Bits 23:20
+    U32 ELSEIF_ELSEIF_B1_RST                    :  4;  // Bits 27:24
+    U32                                         :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_TMRRST_STRUCT;
+
+typedef union {
+  struct {
+    U32 SPARE                                   :  8;  // Bits 7:0
+    U32                                         :  24;  // Bits 31:8
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} GDXC_CR_DEBUP_STRUCT;
+
+typedef union {
+  struct {
+    U32 Ln0Src                                  :  2;  // Bits 1:0
+    U32 Ln1Src                                  :  2;  // Bits 3:2
+    U32 DEVisaEn                                :  1;  // Bits 4:4
+    U32                                         :  27;  // Bits 31:5
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MSGUTILS_CR_VISA2OCLA_CFG_STRUCT;
+
+#define DDRPL_CR_DDR_TX_DELAY_REG                                    (0x00000C04)
+  #define DDRPL_CR_DDR_TX_DELAY_Tx_Delay_R0_OFF                        ( 0)
+  #define DDRPL_CR_DDR_TX_DELAY_Tx_Delay_R0_WID                        ( 8)
+  #define DDRPL_CR_DDR_TX_DELAY_Tx_Delay_R0_MSK                        (0x000000FF)
+  #define DDRPL_CR_DDR_TX_DELAY_Tx_Delay_R0_MAX                        (0x000000FF)
+  #define DDRPL_CR_DDR_TX_DELAY_Tx_Delay_R0_DEF                        (0x00000010)
+  #define DDRPL_CR_DDR_TX_DELAY_Tx_Delay_R1_OFF                        ( 8)
+  #define DDRPL_CR_DDR_TX_DELAY_Tx_Delay_R1_WID                        ( 8)
+  #define DDRPL_CR_DDR_TX_DELAY_Tx_Delay_R1_MSK                        (0x0000FF00)
+  #define DDRPL_CR_DDR_TX_DELAY_Tx_Delay_R1_MAX                        (0x000000FF)
+  #define DDRPL_CR_DDR_TX_DELAY_Tx_Delay_R1_DEF                        (0x00000010)
+  #define DDRPL_CR_DDR_TX_DELAY_Tx_Delay_R2_OFF                        (16)
+  #define DDRPL_CR_DDR_TX_DELAY_Tx_Delay_R2_WID                        ( 8)
+  #define DDRPL_CR_DDR_TX_DELAY_Tx_Delay_R2_MSK                        (0x00FF0000)
+  #define DDRPL_CR_DDR_TX_DELAY_Tx_Delay_R2_MAX                        (0x000000FF)
+  #define DDRPL_CR_DDR_TX_DELAY_Tx_Delay_R2_DEF                        (0x00000010)
+  #define DDRPL_CR_DDR_TX_DELAY_Tx_Delay_R3_OFF                        (24)
+  #define DDRPL_CR_DDR_TX_DELAY_Tx_Delay_R3_WID                        ( 8)
+  #define DDRPL_CR_DDR_TX_DELAY_Tx_Delay_R3_MSK                        (0xFF000000)
+  #define DDRPL_CR_DDR_TX_DELAY_Tx_Delay_R3_MAX                        (0x000000FF)
+  #define DDRPL_CR_DDR_TX_DELAY_Tx_Delay_R3_DEF                        (0x00000010)
+
+#define MPCOHTRK_CR_GDXC_SW_ENABLE_REG                               (0x00000000)
+  #define MPCOHTRK_CR_GDXC_SW_ENABLE_EN_SW_GDXC_OFF                    ( 0)
+  #define MPCOHTRK_CR_GDXC_SW_ENABLE_EN_SW_GDXC_WID                    ( 1)
+  #define MPCOHTRK_CR_GDXC_SW_ENABLE_EN_SW_GDXC_MSK                    (0x00000001)
+  #define MPCOHTRK_CR_GDXC_SW_ENABLE_EN_SW_GDXC_MAX                    (0x00000001)
+  #define MPCOHTRK_CR_GDXC_SW_ENABLE_EN_SW_GDXC_DEF                    (0x00000000)
+  #define MPCOHTRK_CR_GDXC_SW_ENABLE_EN_RING_ADQ_OFF                   ( 1)
+  #define MPCOHTRK_CR_GDXC_SW_ENABLE_EN_RING_ADQ_WID                   ( 1)
+  #define MPCOHTRK_CR_GDXC_SW_ENABLE_EN_RING_ADQ_MSK                   (0x00000002)
+  #define MPCOHTRK_CR_GDXC_SW_ENABLE_EN_RING_ADQ_MAX                   (0x00000001)
+  #define MPCOHTRK_CR_GDXC_SW_ENABLE_EN_RING_ADQ_DEF                   (0x00000001)
+  #define MPCOHTRK_CR_GDXC_SW_ENABLE_EN_RING_BLQ_OFF                   ( 2)
+  #define MPCOHTRK_CR_GDXC_SW_ENABLE_EN_RING_BLQ_WID                   ( 1)
+  #define MPCOHTRK_CR_GDXC_SW_ENABLE_EN_RING_BLQ_MSK                   (0x00000004)
+  #define MPCOHTRK_CR_GDXC_SW_ENABLE_EN_RING_BLQ_MAX                   (0x00000001)
+  #define MPCOHTRK_CR_GDXC_SW_ENABLE_EN_RING_BLQ_DEF                   (0x00000001)
+  #define MPCOHTRK_CR_GDXC_SW_ENABLE_EN_RING_AKQ_OFF                   ( 3)
+  #define MPCOHTRK_CR_GDXC_SW_ENABLE_EN_RING_AKQ_WID                   ( 1)
+  #define MPCOHTRK_CR_GDXC_SW_ENABLE_EN_RING_AKQ_MSK                   (0x00000008)
+  #define MPCOHTRK_CR_GDXC_SW_ENABLE_EN_RING_AKQ_MAX                   (0x00000001)
+  #define MPCOHTRK_CR_GDXC_SW_ENABLE_EN_RING_AKQ_DEF                   (0x00000001)
+  #define MPCOHTRK_CR_GDXC_SW_ENABLE_EN_RING_IVQ_OFF                   ( 4)
+  #define MPCOHTRK_CR_GDXC_SW_ENABLE_EN_RING_IVQ_WID                   ( 1)
+  #define MPCOHTRK_CR_GDXC_SW_ENABLE_EN_RING_IVQ_MSK                   (0x00000010)
+  #define MPCOHTRK_CR_GDXC_SW_ENABLE_EN_RING_IVQ_MAX                   (0x00000001)
+  #define MPCOHTRK_CR_GDXC_SW_ENABLE_EN_RING_IVQ_DEF                   (0x00000001)
+  #define MPCOHTRK_CR_GDXC_SW_ENABLE_EN_IDIQ_OFF                       ( 5)
+  #define MPCOHTRK_CR_GDXC_SW_ENABLE_EN_IDIQ_WID                       ( 1)
+  #define MPCOHTRK_CR_GDXC_SW_ENABLE_EN_IDIQ_MSK                       (0x00000020)
+  #define MPCOHTRK_CR_GDXC_SW_ENABLE_EN_IDIQ_MAX                       (0x00000001)
+  #define MPCOHTRK_CR_GDXC_SW_ENABLE_EN_IDIQ_DEF                       (0x00000000)
+  #define MPCOHTRK_CR_GDXC_SW_ENABLE_EN_mc_UCLKQ_OFF                   ( 6)
+  #define MPCOHTRK_CR_GDXC_SW_ENABLE_EN_mc_UCLKQ_WID                   ( 1)
+  #define MPCOHTRK_CR_GDXC_SW_ENABLE_EN_mc_UCLKQ_MSK                   (0x00000040)
+  #define MPCOHTRK_CR_GDXC_SW_ENABLE_EN_mc_UCLKQ_MAX                   (0x00000001)
+  #define MPCOHTRK_CR_GDXC_SW_ENABLE_EN_mc_UCLKQ_DEF                   (0x00000001)
+  #define MPCOHTRK_CR_GDXC_SW_ENABLE_UP_EN_ADQ_OFF                     ( 8)
+  #define MPCOHTRK_CR_GDXC_SW_ENABLE_UP_EN_ADQ_WID                     ( 1)
+  #define MPCOHTRK_CR_GDXC_SW_ENABLE_UP_EN_ADQ_MSK                     (0x00000100)
+  #define MPCOHTRK_CR_GDXC_SW_ENABLE_UP_EN_ADQ_MAX                     (0x00000001)
+  #define MPCOHTRK_CR_GDXC_SW_ENABLE_UP_EN_ADQ_DEF                     (0x00000001)
+  #define MPCOHTRK_CR_GDXC_SW_ENABLE_DN_EN_ADQ_OFF                     ( 9)
+  #define MPCOHTRK_CR_GDXC_SW_ENABLE_DN_EN_ADQ_WID                     ( 1)
+  #define MPCOHTRK_CR_GDXC_SW_ENABLE_DN_EN_ADQ_MSK                     (0x00000200)
+  #define MPCOHTRK_CR_GDXC_SW_ENABLE_DN_EN_ADQ_MAX                     (0x00000001)
+  #define MPCOHTRK_CR_GDXC_SW_ENABLE_DN_EN_ADQ_DEF                     (0x00000001)
+  #define MPCOHTRK_CR_GDXC_SW_ENABLE_UP_EN_BLQ_OFF                     (10)
+  #define MPCOHTRK_CR_GDXC_SW_ENABLE_UP_EN_BLQ_WID                     ( 1)
+  #define MPCOHTRK_CR_GDXC_SW_ENABLE_UP_EN_BLQ_MSK                     (0x00000400)
+  #define MPCOHTRK_CR_GDXC_SW_ENABLE_UP_EN_BLQ_MAX                     (0x00000001)
+  #define MPCOHTRK_CR_GDXC_SW_ENABLE_UP_EN_BLQ_DEF                     (0x00000001)
+  #define MPCOHTRK_CR_GDXC_SW_ENABLE_DN_EN_BLQ_OFF                     (11)
+  #define MPCOHTRK_CR_GDXC_SW_ENABLE_DN_EN_BLQ_WID                     ( 1)
+  #define MPCOHTRK_CR_GDXC_SW_ENABLE_DN_EN_BLQ_MSK                     (0x00000800)
+  #define MPCOHTRK_CR_GDXC_SW_ENABLE_DN_EN_BLQ_MAX                     (0x00000001)
+  #define MPCOHTRK_CR_GDXC_SW_ENABLE_DN_EN_BLQ_DEF                     (0x00000001)
+  #define MPCOHTRK_CR_GDXC_SW_ENABLE_UP_EN_AKQ_OFF                     (12)
+  #define MPCOHTRK_CR_GDXC_SW_ENABLE_UP_EN_AKQ_WID                     ( 1)
+  #define MPCOHTRK_CR_GDXC_SW_ENABLE_UP_EN_AKQ_MSK                     (0x00001000)
+  #define MPCOHTRK_CR_GDXC_SW_ENABLE_UP_EN_AKQ_MAX                     (0x00000001)
+  #define MPCOHTRK_CR_GDXC_SW_ENABLE_UP_EN_AKQ_DEF                     (0x00000001)
+  #define MPCOHTRK_CR_GDXC_SW_ENABLE_DN_EN_AKQ_OFF                     (13)
+  #define MPCOHTRK_CR_GDXC_SW_ENABLE_DN_EN_AKQ_WID                     ( 1)
+  #define MPCOHTRK_CR_GDXC_SW_ENABLE_DN_EN_AKQ_MSK                     (0x00002000)
+  #define MPCOHTRK_CR_GDXC_SW_ENABLE_DN_EN_AKQ_MAX                     (0x00000001)
+  #define MPCOHTRK_CR_GDXC_SW_ENABLE_DN_EN_AKQ_DEF                     (0x00000001)
+  #define MPCOHTRK_CR_GDXC_SW_ENABLE_MOTQ_TIMING_SELECT_OFF            (14)
+  #define MPCOHTRK_CR_GDXC_SW_ENABLE_MOTQ_TIMING_SELECT_WID            ( 1)
+  #define MPCOHTRK_CR_GDXC_SW_ENABLE_MOTQ_TIMING_SELECT_MSK            (0x00004000)
+  #define MPCOHTRK_CR_GDXC_SW_ENABLE_MOTQ_TIMING_SELECT_MAX            (0x00000001)
+  #define MPCOHTRK_CR_GDXC_SW_ENABLE_MOTQ_TIMING_SELECT_DEF            (0x00000000)
+  #define MPCOHTRK_CR_GDXC_SW_ENABLE_SPARE_OFF                         (16)
+  #define MPCOHTRK_CR_GDXC_SW_ENABLE_SPARE_WID                         ( 8)
+  #define MPCOHTRK_CR_GDXC_SW_ENABLE_SPARE_MSK                         (0x00FF0000)
+  #define MPCOHTRK_CR_GDXC_SW_ENABLE_SPARE_MAX                         (0x000000FF)
+  #define MPCOHTRK_CR_GDXC_SW_ENABLE_SPARE_DEF                         (0x00000000)
+
+#define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_REG                        (0x00000004)
+  #define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_EN_Core0_T0_OFF            ( 0)
+  #define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_EN_Core0_T0_WID            ( 1)
+  #define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_EN_Core0_T0_MSK            (0x00000001)
+  #define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_EN_Core0_T0_MAX            (0x00000001)
+  #define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_EN_Core0_T0_DEF            (0x00000001)
+  #define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_EN_Core0_T1_OFF            ( 1)
+  #define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_EN_Core0_T1_WID            ( 1)
+  #define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_EN_Core0_T1_MSK            (0x00000002)
+  #define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_EN_Core0_T1_MAX            (0x00000001)
+  #define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_EN_Core0_T1_DEF            (0x00000001)
+  #define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_EN_Core1_T0_OFF            ( 2)
+  #define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_EN_Core1_T0_WID            ( 1)
+  #define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_EN_Core1_T0_MSK            (0x00000004)
+  #define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_EN_Core1_T0_MAX            (0x00000001)
+  #define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_EN_Core1_T0_DEF            (0x00000001)
+  #define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_EN_Core1_T1_OFF            ( 3)
+  #define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_EN_Core1_T1_WID            ( 1)
+  #define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_EN_Core1_T1_MSK            (0x00000008)
+  #define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_EN_Core1_T1_MAX            (0x00000001)
+  #define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_EN_Core1_T1_DEF            (0x00000001)
+  #define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_EN_Core2_T0_OFF            ( 4)
+  #define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_EN_Core2_T0_WID            ( 1)
+  #define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_EN_Core2_T0_MSK            (0x00000010)
+  #define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_EN_Core2_T0_MAX            (0x00000001)
+  #define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_EN_Core2_T0_DEF            (0x00000001)
+  #define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_EN_Core2_T1_OFF            ( 5)
+  #define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_EN_Core2_T1_WID            ( 1)
+  #define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_EN_Core2_T1_MSK            (0x00000020)
+  #define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_EN_Core2_T1_MAX            (0x00000001)
+  #define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_EN_Core2_T1_DEF            (0x00000001)
+  #define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_EN_Core3_T0_OFF            ( 6)
+  #define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_EN_Core3_T0_WID            ( 1)
+  #define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_EN_Core3_T0_MSK            (0x00000040)
+  #define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_EN_Core3_T0_MAX            (0x00000001)
+  #define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_EN_Core3_T0_DEF            (0x00000001)
+  #define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_EN_Core3_T1_OFF            ( 7)
+  #define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_EN_Core3_T1_WID            ( 1)
+  #define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_EN_Core3_T1_MSK            (0x00000080)
+  #define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_EN_Core3_T1_MAX            (0x00000001)
+  #define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_EN_Core3_T1_DEF            (0x00000001)
+  #define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_EN_GT_OFF                  ( 8)
+  #define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_EN_GT_WID                  ( 1)
+  #define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_EN_GT_MSK                  (0x00000100)
+  #define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_EN_GT_MAX                  (0x00000001)
+  #define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_EN_GT_DEF                  (0x00000000)
+  #define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_MEM_CHR_RD_OFF             ( 9)
+  #define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_MEM_CHR_RD_WID             ( 1)
+  #define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_MEM_CHR_RD_MSK             (0x00000200)
+  #define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_MEM_CHR_RD_MAX             (0x00000001)
+  #define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_MEM_CHR_RD_DEF             (0x00000001)
+  #define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_MEM_CHR_WR_OFF             (10)
+  #define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_MEM_CHR_WR_WID             ( 1)
+  #define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_MEM_CHR_WR_MSK             (0x00000400)
+  #define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_MEM_CHR_WR_MAX             (0x00000001)
+  #define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_MEM_CHR_WR_DEF             (0x00000001)
+  #define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_MEM_NC_OFF                 (11)
+  #define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_MEM_NC_WID                 ( 1)
+  #define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_MEM_NC_MSK                 (0x00000800)
+  #define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_MEM_NC_MAX                 (0x00000001)
+  #define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_MEM_NC_DEF                 (0x00000001)
+  #define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_EN_CBO_Exp_WB_OFF          (12)
+  #define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_EN_CBO_Exp_WB_WID          ( 1)
+  #define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_EN_CBO_Exp_WB_MSK          (0x00001000)
+  #define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_EN_CBO_Exp_WB_MAX          (0x00000001)
+  #define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_EN_CBO_Exp_WB_DEF          (0x00000000)
+  #define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_SNP_Access_OFF             (13)
+  #define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_SNP_Access_WID             ( 1)
+  #define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_SNP_Access_MSK             (0x00002000)
+  #define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_SNP_Access_MAX             (0x00000001)
+  #define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_SNP_Access_DEF             (0x00000001)
+  #define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_AD_EODLAT_OFF              (14)
+  #define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_AD_EODLAT_WID              ( 1)
+  #define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_AD_EODLAT_MSK              (0x00004000)
+  #define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_AD_EODLAT_MAX              (0x00000001)
+  #define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_AD_EODLAT_DEF              (0x00000001)
+
+#define MPCOHTRK_CR_GDXC_QUALIFIER_BL_REG                            (0x00000008)
+  #define MPCOHTRK_CR_GDXC_QUALIFIER_BL_CR_CHR_RD_OFF                  ( 0)
+  #define MPCOHTRK_CR_GDXC_QUALIFIER_BL_CR_CHR_RD_WID                  ( 3)
+  #define MPCOHTRK_CR_GDXC_QUALIFIER_BL_CR_CHR_RD_MSK                  (0x00000007)
+  #define MPCOHTRK_CR_GDXC_QUALIFIER_BL_CR_CHR_RD_MAX                  (0x00000007)
+  #define MPCOHTRK_CR_GDXC_QUALIFIER_BL_CR_CHR_RD_DEF                  (0x00000000)
+  #define MPCOHTRK_CR_GDXC_QUALIFIER_BL_CHR_RD_STAT_MOD_OFF            ( 3)
+  #define MPCOHTRK_CR_GDXC_QUALIFIER_BL_CHR_RD_STAT_MOD_WID            ( 1)
+  #define MPCOHTRK_CR_GDXC_QUALIFIER_BL_CHR_RD_STAT_MOD_MSK            (0x00000008)
+  #define MPCOHTRK_CR_GDXC_QUALIFIER_BL_CHR_RD_STAT_MOD_MAX            (0x00000001)
+  #define MPCOHTRK_CR_GDXC_QUALIFIER_BL_CHR_RD_STAT_MOD_DEF            (0x00000001)
+  #define MPCOHTRK_CR_GDXC_QUALIFIER_BL_CR_CHR_WR_OFF                  ( 4)
+  #define MPCOHTRK_CR_GDXC_QUALIFIER_BL_CR_CHR_WR_WID                  ( 4)
+  #define MPCOHTRK_CR_GDXC_QUALIFIER_BL_CR_CHR_WR_MSK                  (0x000000F0)
+  #define MPCOHTRK_CR_GDXC_QUALIFIER_BL_CR_CHR_WR_MAX                  (0x0000000F)
+  #define MPCOHTRK_CR_GDXC_QUALIFIER_BL_CR_CHR_WR_DEF                  (0x00000000)
+  #define MPCOHTRK_CR_GDXC_QUALIFIER_BL_CR_NC_RD_OFF                   ( 8)
+  #define MPCOHTRK_CR_GDXC_QUALIFIER_BL_CR_NC_RD_WID                   ( 3)
+  #define MPCOHTRK_CR_GDXC_QUALIFIER_BL_CR_NC_RD_MSK                   (0x00000700)
+  #define MPCOHTRK_CR_GDXC_QUALIFIER_BL_CR_NC_RD_MAX                   (0x00000007)
+  #define MPCOHTRK_CR_GDXC_QUALIFIER_BL_CR_NC_RD_DEF                   (0x00000000)
+  #define MPCOHTRK_CR_GDXC_QUALIFIER_BL_NC_RD_STAT_MOD_OFF             (11)
+  #define MPCOHTRK_CR_GDXC_QUALIFIER_BL_NC_RD_STAT_MOD_WID             ( 1)
+  #define MPCOHTRK_CR_GDXC_QUALIFIER_BL_NC_RD_STAT_MOD_MSK             (0x00000800)
+  #define MPCOHTRK_CR_GDXC_QUALIFIER_BL_NC_RD_STAT_MOD_MAX             (0x00000001)
+  #define MPCOHTRK_CR_GDXC_QUALIFIER_BL_NC_RD_STAT_MOD_DEF             (0x00000001)
+  #define MPCOHTRK_CR_GDXC_QUALIFIER_BL_CR_NC_WR_OFF                   (12)
+  #define MPCOHTRK_CR_GDXC_QUALIFIER_BL_CR_NC_WR_WID                   ( 4)
+  #define MPCOHTRK_CR_GDXC_QUALIFIER_BL_CR_NC_WR_MSK                   (0x0000F000)
+  #define MPCOHTRK_CR_GDXC_QUALIFIER_BL_CR_NC_WR_MAX                   (0x0000000F)
+  #define MPCOHTRK_CR_GDXC_QUALIFIER_BL_CR_NC_WR_DEF                   (0x00000000)
+  #define MPCOHTRK_CR_GDXC_QUALIFIER_BL_NC_WR_STAT_MOD_OFF             (16)
+  #define MPCOHTRK_CR_GDXC_QUALIFIER_BL_NC_WR_STAT_MOD_WID             ( 1)
+  #define MPCOHTRK_CR_GDXC_QUALIFIER_BL_NC_WR_STAT_MOD_MSK             (0x00010000)
+  #define MPCOHTRK_CR_GDXC_QUALIFIER_BL_NC_WR_STAT_MOD_MAX             (0x00000001)
+  #define MPCOHTRK_CR_GDXC_QUALIFIER_BL_NC_WR_STAT_MOD_DEF             (0x00000001)
+  #define MPCOHTRK_CR_GDXC_QUALIFIER_BL_Data_Core0_OFF                 (17)
+  #define MPCOHTRK_CR_GDXC_QUALIFIER_BL_Data_Core0_WID                 ( 1)
+  #define MPCOHTRK_CR_GDXC_QUALIFIER_BL_Data_Core0_MSK                 (0x00020000)
+  #define MPCOHTRK_CR_GDXC_QUALIFIER_BL_Data_Core0_MAX                 (0x00000001)
+  #define MPCOHTRK_CR_GDXC_QUALIFIER_BL_Data_Core0_DEF                 (0x00000000)
+  #define MPCOHTRK_CR_GDXC_QUALIFIER_BL_Data_Core1_OFF                 (18)
+  #define MPCOHTRK_CR_GDXC_QUALIFIER_BL_Data_Core1_WID                 ( 1)
+  #define MPCOHTRK_CR_GDXC_QUALIFIER_BL_Data_Core1_MSK                 (0x00040000)
+  #define MPCOHTRK_CR_GDXC_QUALIFIER_BL_Data_Core1_MAX                 (0x00000001)
+  #define MPCOHTRK_CR_GDXC_QUALIFIER_BL_Data_Core1_DEF                 (0x00000000)
+  #define MPCOHTRK_CR_GDXC_QUALIFIER_BL_Data_Core2_OFF                 (19)
+  #define MPCOHTRK_CR_GDXC_QUALIFIER_BL_Data_Core2_WID                 ( 1)
+  #define MPCOHTRK_CR_GDXC_QUALIFIER_BL_Data_Core2_MSK                 (0x00080000)
+  #define MPCOHTRK_CR_GDXC_QUALIFIER_BL_Data_Core2_MAX                 (0x00000001)
+  #define MPCOHTRK_CR_GDXC_QUALIFIER_BL_Data_Core2_DEF                 (0x00000000)
+  #define MPCOHTRK_CR_GDXC_QUALIFIER_BL_Data_Core3_OFF                 (20)
+  #define MPCOHTRK_CR_GDXC_QUALIFIER_BL_Data_Core3_WID                 ( 1)
+  #define MPCOHTRK_CR_GDXC_QUALIFIER_BL_Data_Core3_MSK                 (0x00100000)
+  #define MPCOHTRK_CR_GDXC_QUALIFIER_BL_Data_Core3_MAX                 (0x00000001)
+  #define MPCOHTRK_CR_GDXC_QUALIFIER_BL_Data_Core3_DEF                 (0x00000000)
+  #define MPCOHTRK_CR_GDXC_QUALIFIER_BL_Data_CBO_OFF                   (21)
+  #define MPCOHTRK_CR_GDXC_QUALIFIER_BL_Data_CBO_WID                   ( 1)
+  #define MPCOHTRK_CR_GDXC_QUALIFIER_BL_Data_CBO_MSK                   (0x00200000)
+  #define MPCOHTRK_CR_GDXC_QUALIFIER_BL_Data_CBO_MAX                   (0x00000001)
+  #define MPCOHTRK_CR_GDXC_QUALIFIER_BL_Data_CBO_DEF                   (0x00000000)
+  #define MPCOHTRK_CR_GDXC_QUALIFIER_BL_Data_GT_OFF                    (22)
+  #define MPCOHTRK_CR_GDXC_QUALIFIER_BL_Data_GT_WID                    ( 1)
+  #define MPCOHTRK_CR_GDXC_QUALIFIER_BL_Data_GT_MSK                    (0x00400000)
+  #define MPCOHTRK_CR_GDXC_QUALIFIER_BL_Data_GT_MAX                    (0x00000001)
+  #define MPCOHTRK_CR_GDXC_QUALIFIER_BL_Data_GT_DEF                    (0x00000000)
+
+#define MPCOHTRK_CR_GDXC_OVF_STATUS_REG                              (0x0000000C)
+  #define MPCOHTRK_CR_GDXC_OVF_STATUS_OVF_Global_OFF                   ( 0)
+  #define MPCOHTRK_CR_GDXC_OVF_STATUS_OVF_Global_WID                   ( 1)
+  #define MPCOHTRK_CR_GDXC_OVF_STATUS_OVF_Global_MSK                   (0x00000001)
+  #define MPCOHTRK_CR_GDXC_OVF_STATUS_OVF_Global_MAX                   (0x00000001)
+  #define MPCOHTRK_CR_GDXC_OVF_STATUS_OVF_Global_DEF                   (0x00000000)
+  #define MPCOHTRK_CR_GDXC_OVF_STATUS_OVF_Ring_AD_OFF                  ( 1)
+  #define MPCOHTRK_CR_GDXC_OVF_STATUS_OVF_Ring_AD_WID                  ( 1)
+  #define MPCOHTRK_CR_GDXC_OVF_STATUS_OVF_Ring_AD_MSK                  (0x00000002)
+  #define MPCOHTRK_CR_GDXC_OVF_STATUS_OVF_Ring_AD_MAX                  (0x00000001)
+  #define MPCOHTRK_CR_GDXC_OVF_STATUS_OVF_Ring_AD_DEF                  (0x00000000)
+  #define MPCOHTRK_CR_GDXC_OVF_STATUS_OVF_Ring_BL_OFF                  ( 2)
+  #define MPCOHTRK_CR_GDXC_OVF_STATUS_OVF_Ring_BL_WID                  ( 1)
+  #define MPCOHTRK_CR_GDXC_OVF_STATUS_OVF_Ring_BL_MSK                  (0x00000004)
+  #define MPCOHTRK_CR_GDXC_OVF_STATUS_OVF_Ring_BL_MAX                  (0x00000001)
+  #define MPCOHTRK_CR_GDXC_OVF_STATUS_OVF_Ring_BL_DEF                  (0x00000000)
+  #define MPCOHTRK_CR_GDXC_OVF_STATUS_OVF_Ring_AK_OFF                  ( 3)
+  #define MPCOHTRK_CR_GDXC_OVF_STATUS_OVF_Ring_AK_WID                  ( 1)
+  #define MPCOHTRK_CR_GDXC_OVF_STATUS_OVF_Ring_AK_MSK                  (0x00000008)
+  #define MPCOHTRK_CR_GDXC_OVF_STATUS_OVF_Ring_AK_MAX                  (0x00000001)
+  #define MPCOHTRK_CR_GDXC_OVF_STATUS_OVF_Ring_AK_DEF                  (0x00000000)
+  #define MPCOHTRK_CR_GDXC_OVF_STATUS_OVF_Ring_IV_OFF                  ( 4)
+  #define MPCOHTRK_CR_GDXC_OVF_STATUS_OVF_Ring_IV_WID                  ( 1)
+  #define MPCOHTRK_CR_GDXC_OVF_STATUS_OVF_Ring_IV_MSK                  (0x00000010)
+  #define MPCOHTRK_CR_GDXC_OVF_STATUS_OVF_Ring_IV_MAX                  (0x00000001)
+  #define MPCOHTRK_CR_GDXC_OVF_STATUS_OVF_Ring_IV_DEF                  (0x00000000)
+  #define MPCOHTRK_CR_GDXC_OVF_STATUS_OVF_IDI_center_OFF               ( 9)
+  #define MPCOHTRK_CR_GDXC_OVF_STATUS_OVF_IDI_center_WID               ( 1)
+  #define MPCOHTRK_CR_GDXC_OVF_STATUS_OVF_IDI_center_MSK               (0x00000200)
+  #define MPCOHTRK_CR_GDXC_OVF_STATUS_OVF_IDI_center_MAX               (0x00000001)
+  #define MPCOHTRK_CR_GDXC_OVF_STATUS_OVF_IDI_center_DEF               (0x00000000)
+  #define MPCOHTRK_CR_GDXC_OVF_STATUS_OVF_mcUCLK_OFF                   (10)
+  #define MPCOHTRK_CR_GDXC_OVF_STATUS_OVF_mcUCLK_WID                   ( 1)
+  #define MPCOHTRK_CR_GDXC_OVF_STATUS_OVF_mcUCLK_MSK                   (0x00000400)
+  #define MPCOHTRK_CR_GDXC_OVF_STATUS_OVF_mcUCLK_MAX                   (0x00000001)
+  #define MPCOHTRK_CR_GDXC_OVF_STATUS_OVF_mcUCLK_DEF                   (0x00000000)
+  #define MPCOHTRK_CR_GDXC_OVF_STATUS_OVF_PWR_mcFCLK_OFF               (11)
+  #define MPCOHTRK_CR_GDXC_OVF_STATUS_OVF_PWR_mcFCLK_WID               ( 1)
+  #define MPCOHTRK_CR_GDXC_OVF_STATUS_OVF_PWR_mcFCLK_MSK               (0x00000800)
+  #define MPCOHTRK_CR_GDXC_OVF_STATUS_OVF_PWR_mcFCLK_MAX               (0x00000001)
+  #define MPCOHTRK_CR_GDXC_OVF_STATUS_OVF_PWR_mcFCLK_DEF               (0x00000000)
+
+#define MPCOHTRK_CR_GDXC_MOT_ADDRESS_LO_REG                          (0x00000010)
+  #define MPCOHTRK_CR_GDXC_MOT_ADDRESS_LO_MEM_PTR_OFF                  ( 0)
+  #define MPCOHTRK_CR_GDXC_MOT_ADDRESS_LO_MEM_PTR_WID                  (32)
+  #define MPCOHTRK_CR_GDXC_MOT_ADDRESS_LO_MEM_PTR_MSK                  (0xFFFFFFFF)
+  #define MPCOHTRK_CR_GDXC_MOT_ADDRESS_LO_MEM_PTR_MAX                  (0xFFFFFFFF)
+  #define MPCOHTRK_CR_GDXC_MOT_ADDRESS_LO_MEM_PTR_DEF                  (0x00000000)
+
+#define MPCOHTRK_CR_GDXC_MOT_ADDRESS_HI_REG                          (0x00000014)
+  #define MPCOHTRK_CR_GDXC_MOT_ADDRESS_HI_MEM_PTR_OFF                  ( 0)
+  #define MPCOHTRK_CR_GDXC_MOT_ADDRESS_HI_MEM_PTR_WID                  ( 1)
+  #define MPCOHTRK_CR_GDXC_MOT_ADDRESS_HI_MEM_PTR_MSK                  (0x00000001)
+  #define MPCOHTRK_CR_GDXC_MOT_ADDRESS_HI_MEM_PTR_MAX                  (0x00000001)
+  #define MPCOHTRK_CR_GDXC_MOT_ADDRESS_HI_MEM_PTR_DEF                  (0x00000000)
+  #define MPCOHTRK_CR_GDXC_MOT_ADDRESS_HI_BUFFER_WRAP_OFF              ( 1)
+  #define MPCOHTRK_CR_GDXC_MOT_ADDRESS_HI_BUFFER_WRAP_WID              ( 1)
+  #define MPCOHTRK_CR_GDXC_MOT_ADDRESS_HI_BUFFER_WRAP_MSK              (0x00000002)
+  #define MPCOHTRK_CR_GDXC_MOT_ADDRESS_HI_BUFFER_WRAP_MAX              (0x00000001)
+  #define MPCOHTRK_CR_GDXC_MOT_ADDRESS_HI_BUFFER_WRAP_DEF              (0x00000000)
+  #define MPCOHTRK_CR_GDXC_MOT_ADDRESS_HI_SPARE_OFF                    ( 2)
+  #define MPCOHTRK_CR_GDXC_MOT_ADDRESS_HI_SPARE_WID                    (30)
+  #define MPCOHTRK_CR_GDXC_MOT_ADDRESS_HI_SPARE_MSK                    (0xFFFFFFFC)
+  #define MPCOHTRK_CR_GDXC_MOT_ADDRESS_HI_SPARE_MAX                    (0x3FFFFFFF)
+  #define MPCOHTRK_CR_GDXC_MOT_ADDRESS_HI_SPARE_DEF                    (0x00000000)
+
+#define MPCOHTRK_CR_GDXC_MOT_REGION_REG                              (0x00000018)
+  #define MPCOHTRK_CR_GDXC_MOT_REGION_START_ADDRESS_OFF                ( 0)
+  #define MPCOHTRK_CR_GDXC_MOT_REGION_START_ADDRESS_WID                (16)
+  #define MPCOHTRK_CR_GDXC_MOT_REGION_START_ADDRESS_MSK                (0x0000FFFF)
+  #define MPCOHTRK_CR_GDXC_MOT_REGION_START_ADDRESS_MAX                (0x0000FFFF)
+  #define MPCOHTRK_CR_GDXC_MOT_REGION_START_ADDRESS_DEF                (0x00000000)
+  #define MPCOHTRK_CR_GDXC_MOT_REGION_END_ADDRESS_OFF                  (16)
+  #define MPCOHTRK_CR_GDXC_MOT_REGION_END_ADDRESS_WID                  (16)
+  #define MPCOHTRK_CR_GDXC_MOT_REGION_END_ADDRESS_MSK                  (0xFFFF0000)
+  #define MPCOHTRK_CR_GDXC_MOT_REGION_END_ADDRESS_MAX                  (0x0000FFFF)
+  #define MPCOHTRK_CR_GDXC_MOT_REGION_END_ADDRESS_DEF                  (0x00000001)
+
+#define MPCOHTRK_CR_GDXC_OCLA_ADDRESS_LO_REG                         (0x00000020)
+  #define MPCOHTRK_CR_GDXC_OCLA_ADDRESS_LO_MEM_PTR_OFF                 ( 0)
+  #define MPCOHTRK_CR_GDXC_OCLA_ADDRESS_LO_MEM_PTR_WID                 (32)
+  #define MPCOHTRK_CR_GDXC_OCLA_ADDRESS_LO_MEM_PTR_MSK                 (0xFFFFFFFF)
+  #define MPCOHTRK_CR_GDXC_OCLA_ADDRESS_LO_MEM_PTR_MAX                 (0xFFFFFFFF)
+  #define MPCOHTRK_CR_GDXC_OCLA_ADDRESS_LO_MEM_PTR_DEF                 (0x00000000)
+
+#define MPCOHTRK_CR_GDXC_OCLA_ADDRESS_HI_REG                         (0x00000024)
+  #define MPCOHTRK_CR_GDXC_OCLA_ADDRESS_HI_MEM_PTR_OFF                 ( 0)
+  #define MPCOHTRK_CR_GDXC_OCLA_ADDRESS_HI_MEM_PTR_WID                 ( 1)
+  #define MPCOHTRK_CR_GDXC_OCLA_ADDRESS_HI_MEM_PTR_MSK                 (0x00000001)
+  #define MPCOHTRK_CR_GDXC_OCLA_ADDRESS_HI_MEM_PTR_MAX                 (0x00000001)
+  #define MPCOHTRK_CR_GDXC_OCLA_ADDRESS_HI_MEM_PTR_DEF                 (0x00000000)
+  #define MPCOHTRK_CR_GDXC_OCLA_ADDRESS_HI_BUFFER_WRAP_OFF             ( 1)
+  #define MPCOHTRK_CR_GDXC_OCLA_ADDRESS_HI_BUFFER_WRAP_WID             ( 1)
+  #define MPCOHTRK_CR_GDXC_OCLA_ADDRESS_HI_BUFFER_WRAP_MSK             (0x00000002)
+  #define MPCOHTRK_CR_GDXC_OCLA_ADDRESS_HI_BUFFER_WRAP_MAX             (0x00000001)
+  #define MPCOHTRK_CR_GDXC_OCLA_ADDRESS_HI_BUFFER_WRAP_DEF             (0x00000000)
+  #define MPCOHTRK_CR_GDXC_OCLA_ADDRESS_HI_LOCK_OFF                    ( 2)
+  #define MPCOHTRK_CR_GDXC_OCLA_ADDRESS_HI_LOCK_WID                    ( 1)
+  #define MPCOHTRK_CR_GDXC_OCLA_ADDRESS_HI_LOCK_MSK                    (0x00000004)
+  #define MPCOHTRK_CR_GDXC_OCLA_ADDRESS_HI_LOCK_MAX                    (0x00000001)
+  #define MPCOHTRK_CR_GDXC_OCLA_ADDRESS_HI_LOCK_DEF                    (0x00000000)
+  #define MPCOHTRK_CR_GDXC_OCLA_ADDRESS_HI_SPARE_OFF                   ( 3)
+  #define MPCOHTRK_CR_GDXC_OCLA_ADDRESS_HI_SPARE_WID                   (29)
+  #define MPCOHTRK_CR_GDXC_OCLA_ADDRESS_HI_SPARE_MSK                   (0xFFFFFFF8)
+  #define MPCOHTRK_CR_GDXC_OCLA_ADDRESS_HI_SPARE_MAX                   (0x1FFFFFFF)
+  #define MPCOHTRK_CR_GDXC_OCLA_ADDRESS_HI_SPARE_DEF                   (0x00000000)
+
+#define MPCOHTRK_CR_GDXC_OCLA_REGION_REG                             (0x00000028)
+  #define MPCOHTRK_CR_GDXC_OCLA_REGION_START_ADDRESS_OFF               ( 0)
+  #define MPCOHTRK_CR_GDXC_OCLA_REGION_START_ADDRESS_WID               (16)
+  #define MPCOHTRK_CR_GDXC_OCLA_REGION_START_ADDRESS_MSK               (0x0000FFFF)
+  #define MPCOHTRK_CR_GDXC_OCLA_REGION_START_ADDRESS_MAX               (0x0000FFFF)
+  #define MPCOHTRK_CR_GDXC_OCLA_REGION_START_ADDRESS_DEF               (0x00000000)
+  #define MPCOHTRK_CR_GDXC_OCLA_REGION_END_ADDRESS_OFF                 (16)
+  #define MPCOHTRK_CR_GDXC_OCLA_REGION_END_ADDRESS_WID                 (16)
+  #define MPCOHTRK_CR_GDXC_OCLA_REGION_END_ADDRESS_MSK                 (0xFFFF0000)
+  #define MPCOHTRK_CR_GDXC_OCLA_REGION_END_ADDRESS_MAX                 (0x0000FFFF)
+  #define MPCOHTRK_CR_GDXC_OCLA_REGION_END_ADDRESS_DEF                 (0x00000001)
+
+#define GODLAT_CR_G_ODLAT_ARM_S0L_REG                                (0x00000400)
+  #define GODLAT_CR_G_ODLAT_ARM_S0L_ARM_bits_packet_OFF                ( 0)
+  #define GODLAT_CR_G_ODLAT_ARM_S0L_ARM_bits_packet_WID                (32)
+  #define GODLAT_CR_G_ODLAT_ARM_S0L_ARM_bits_packet_MSK                (0xFFFFFFFF)
+  #define GODLAT_CR_G_ODLAT_ARM_S0L_ARM_bits_packet_MAX                (0xFFFFFFFF)
+
+#define GODLAT_CR_G_ODLAT_ARM_S0H_REG                                (0x00000404)
+  #define GODLAT_CR_G_ODLAT_ARM_S0H_ARM_bits_packet_OFF                ( 0)
+  #define GODLAT_CR_G_ODLAT_ARM_S0H_ARM_bits_packet_WID                (32)
+  #define GODLAT_CR_G_ODLAT_ARM_S0H_ARM_bits_packet_MSK                (0xFFFFFFFF)
+  #define GODLAT_CR_G_ODLAT_ARM_S0H_ARM_bits_packet_MAX                (0xFFFFFFFF)
+
+#define GODLAT_CR_G_ODLAT_MASK_S0L_REG                               (0x00000408)
+  #define GODLAT_CR_G_ODLAT_MASK_S0L_Mask_bits_OFF                     ( 0)
+  #define GODLAT_CR_G_ODLAT_MASK_S0L_Mask_bits_WID                     (32)
+  #define GODLAT_CR_G_ODLAT_MASK_S0L_Mask_bits_MSK                     (0xFFFFFFFF)
+  #define GODLAT_CR_G_ODLAT_MASK_S0L_Mask_bits_MAX                     (0xFFFFFFFF)
+
+#define GODLAT_CR_G_ODLAT_MASK_S0H_REG                               (0x0000040C)
+  #define GODLAT_CR_G_ODLAT_MASK_S0H_Mask_bits_OFF                     ( 0)
+  #define GODLAT_CR_G_ODLAT_MASK_S0H_Mask_bits_WID                     (32)
+  #define GODLAT_CR_G_ODLAT_MASK_S0H_Mask_bits_MSK                     (0xFFFFFFFF)
+  #define GODLAT_CR_G_ODLAT_MASK_S0H_Mask_bits_MAX                     (0xFFFFFFFF)
+
+#define GODLAT_CR_G_ODLAT_ARM_S1L_REG                                (0x00000410)
+  #define GODLAT_CR_G_ODLAT_ARM_S1L_ARM_bits_packet_OFF                ( 0)
+  #define GODLAT_CR_G_ODLAT_ARM_S1L_ARM_bits_packet_WID                (32)
+  #define GODLAT_CR_G_ODLAT_ARM_S1L_ARM_bits_packet_MSK                (0xFFFFFFFF)
+  #define GODLAT_CR_G_ODLAT_ARM_S1L_ARM_bits_packet_MAX                (0xFFFFFFFF)
+
+#define GODLAT_CR_G_ODLAT_ARM_S1H_REG                                (0x00000414)
+  #define GODLAT_CR_G_ODLAT_ARM_S1H_ARM_bits_packet_OFF                ( 0)
+  #define GODLAT_CR_G_ODLAT_ARM_S1H_ARM_bits_packet_WID                (32)
+  #define GODLAT_CR_G_ODLAT_ARM_S1H_ARM_bits_packet_MSK                (0xFFFFFFFF)
+  #define GODLAT_CR_G_ODLAT_ARM_S1H_ARM_bits_packet_MAX                (0xFFFFFFFF)
+
+#define GODLAT_CR_G_ODLAT_MASK_S1L_REG                               (0x00000418)
+  #define GODLAT_CR_G_ODLAT_MASK_S1L_Mask_bits_OFF                     ( 0)
+  #define GODLAT_CR_G_ODLAT_MASK_S1L_Mask_bits_WID                     (32)
+  #define GODLAT_CR_G_ODLAT_MASK_S1L_Mask_bits_MSK                     (0xFFFFFFFF)
+  #define GODLAT_CR_G_ODLAT_MASK_S1L_Mask_bits_MAX                     (0xFFFFFFFF)
+
+#define GODLAT_CR_G_ODLAT_MASK_S1H_REG                               (0x0000041C)
+  #define GODLAT_CR_G_ODLAT_MASK_S1H_Mask_bits_OFF                     ( 0)
+  #define GODLAT_CR_G_ODLAT_MASK_S1H_Mask_bits_WID                     (32)
+  #define GODLAT_CR_G_ODLAT_MASK_S1H_Mask_bits_MSK                     (0xFFFFFFFF)
+  #define GODLAT_CR_G_ODLAT_MASK_S1H_Mask_bits_MAX                     (0xFFFFFFFF)
+
+#define GODLAT_CR_G_ODLAT_ARM_S2L_REG                                (0x00000420)
+  #define GODLAT_CR_G_ODLAT_ARM_S2L_ARM_bits_packet_OFF                ( 0)
+  #define GODLAT_CR_G_ODLAT_ARM_S2L_ARM_bits_packet_WID                (32)
+  #define GODLAT_CR_G_ODLAT_ARM_S2L_ARM_bits_packet_MSK                (0xFFFFFFFF)
+  #define GODLAT_CR_G_ODLAT_ARM_S2L_ARM_bits_packet_MAX                (0xFFFFFFFF)
+
+#define GODLAT_CR_G_ODLAT_ARM_S2H_REG                                (0x00000424)
+  #define GODLAT_CR_G_ODLAT_ARM_S2H_ARM_bits_packet_OFF                ( 0)
+  #define GODLAT_CR_G_ODLAT_ARM_S2H_ARM_bits_packet_WID                (32)
+  #define GODLAT_CR_G_ODLAT_ARM_S2H_ARM_bits_packet_MSK                (0xFFFFFFFF)
+  #define GODLAT_CR_G_ODLAT_ARM_S2H_ARM_bits_packet_MAX                (0xFFFFFFFF)
+
+#define GODLAT_CR_G_ODLAT_MASK_S2L_REG                               (0x00000428)
+  #define GODLAT_CR_G_ODLAT_MASK_S2L_Mask_bits_OFF                     ( 0)
+  #define GODLAT_CR_G_ODLAT_MASK_S2L_Mask_bits_WID                     (32)
+  #define GODLAT_CR_G_ODLAT_MASK_S2L_Mask_bits_MSK                     (0xFFFFFFFF)
+  #define GODLAT_CR_G_ODLAT_MASK_S2L_Mask_bits_MAX                     (0xFFFFFFFF)
+
+#define GODLAT_CR_G_ODLAT_MASK_S2H_REG                               (0x0000042C)
+  #define GODLAT_CR_G_ODLAT_MASK_S2H_Mask_bits_OFF                     ( 0)
+  #define GODLAT_CR_G_ODLAT_MASK_S2H_Mask_bits_WID                     (32)
+  #define GODLAT_CR_G_ODLAT_MASK_S2H_Mask_bits_MSK                     (0xFFFFFFFF)
+  #define GODLAT_CR_G_ODLAT_MASK_S2H_Mask_bits_MAX                     (0xFFFFFFFF)
+
+#define GODLAT_CR_G_ODLAT_ARM_S3L_REG                                (0x00000430)
+  #define GODLAT_CR_G_ODLAT_ARM_S3L_ARM_bits_packet_OFF                ( 0)
+  #define GODLAT_CR_G_ODLAT_ARM_S3L_ARM_bits_packet_WID                (32)
+  #define GODLAT_CR_G_ODLAT_ARM_S3L_ARM_bits_packet_MSK                (0xFFFFFFFF)
+  #define GODLAT_CR_G_ODLAT_ARM_S3L_ARM_bits_packet_MAX                (0xFFFFFFFF)
+
+#define GODLAT_CR_G_ODLAT_ARM_S3H_REG                                (0x00000434)
+  #define GODLAT_CR_G_ODLAT_ARM_S3H_ARM_bits_packet_OFF                ( 0)
+  #define GODLAT_CR_G_ODLAT_ARM_S3H_ARM_bits_packet_WID                (32)
+  #define GODLAT_CR_G_ODLAT_ARM_S3H_ARM_bits_packet_MSK                (0xFFFFFFFF)
+  #define GODLAT_CR_G_ODLAT_ARM_S3H_ARM_bits_packet_MAX                (0xFFFFFFFF)
+
+#define GODLAT_CR_G_ODLAT_MASK_S3L_REG                               (0x00000438)
+  #define GODLAT_CR_G_ODLAT_MASK_S3L_Mask_bits_OFF                     ( 0)
+  #define GODLAT_CR_G_ODLAT_MASK_S3L_Mask_bits_WID                     (32)
+  #define GODLAT_CR_G_ODLAT_MASK_S3L_Mask_bits_MSK                     (0xFFFFFFFF)
+  #define GODLAT_CR_G_ODLAT_MASK_S3L_Mask_bits_MAX                     (0xFFFFFFFF)
+
+#define GODLAT_CR_G_ODLAT_MASK_S3H_REG                               (0x0000043C)
+  #define GODLAT_CR_G_ODLAT_MASK_S3H_Mask_bits_OFF                     ( 0)
+  #define GODLAT_CR_G_ODLAT_MASK_S3H_Mask_bits_WID                     (32)
+  #define GODLAT_CR_G_ODLAT_MASK_S3H_Mask_bits_MSK                     (0xFFFFFFFF)
+  #define GODLAT_CR_G_ODLAT_MASK_S3H_Mask_bits_MAX                     (0xFFFFFFFF)
+
+#define GODLAT_CR_G_ODLAT_ARM_S4L_REG                                (0x00000440)
+  #define GODLAT_CR_G_ODLAT_ARM_S4L_ARM_bits_packet_OFF                ( 0)
+  #define GODLAT_CR_G_ODLAT_ARM_S4L_ARM_bits_packet_WID                (32)
+  #define GODLAT_CR_G_ODLAT_ARM_S4L_ARM_bits_packet_MSK                (0xFFFFFFFF)
+  #define GODLAT_CR_G_ODLAT_ARM_S4L_ARM_bits_packet_MAX                (0xFFFFFFFF)
+
+#define GODLAT_CR_G_ODLAT_ARM_S4H_REG                                (0x00000444)
+  #define GODLAT_CR_G_ODLAT_ARM_S4H_ARM_bits_packet_OFF                ( 0)
+  #define GODLAT_CR_G_ODLAT_ARM_S4H_ARM_bits_packet_WID                (32)
+  #define GODLAT_CR_G_ODLAT_ARM_S4H_ARM_bits_packet_MSK                (0xFFFFFFFF)
+  #define GODLAT_CR_G_ODLAT_ARM_S4H_ARM_bits_packet_MAX                (0xFFFFFFFF)
+
+#define GODLAT_CR_G_ODLAT_MASK_S4L_REG                               (0x00000448)
+  #define GODLAT_CR_G_ODLAT_MASK_S4L_Mask_bits_OFF                     ( 0)
+  #define GODLAT_CR_G_ODLAT_MASK_S4L_Mask_bits_WID                     (32)
+  #define GODLAT_CR_G_ODLAT_MASK_S4L_Mask_bits_MSK                     (0xFFFFFFFF)
+  #define GODLAT_CR_G_ODLAT_MASK_S4L_Mask_bits_MAX                     (0xFFFFFFFF)
+
+#define GODLAT_CR_G_ODLAT_MASK_S4H_REG                               (0x0000044C)
+  #define GODLAT_CR_G_ODLAT_MASK_S4H_Mask_bits_OFF                     ( 0)
+  #define GODLAT_CR_G_ODLAT_MASK_S4H_Mask_bits_WID                     (32)
+  #define GODLAT_CR_G_ODLAT_MASK_S4H_Mask_bits_MSK                     (0xFFFFFFFF)
+  #define GODLAT_CR_G_ODLAT_MASK_S4H_Mask_bits_MAX                     (0xFFFFFFFF)
+
+#define GODLAT_CR_G_ODLAT_ARM_S5L_REG                                (0x00000450)
+  #define GODLAT_CR_G_ODLAT_ARM_S5L_ARM_bits_packet_OFF                ( 0)
+  #define GODLAT_CR_G_ODLAT_ARM_S5L_ARM_bits_packet_WID                (32)
+  #define GODLAT_CR_G_ODLAT_ARM_S5L_ARM_bits_packet_MSK                (0xFFFFFFFF)
+  #define GODLAT_CR_G_ODLAT_ARM_S5L_ARM_bits_packet_MAX                (0xFFFFFFFF)
+
+#define GODLAT_CR_G_ODLAT_ARM_S5H_REG                                (0x00000454)
+  #define GODLAT_CR_G_ODLAT_ARM_S5H_ARM_bits_packet_OFF                ( 0)
+  #define GODLAT_CR_G_ODLAT_ARM_S5H_ARM_bits_packet_WID                (32)
+  #define GODLAT_CR_G_ODLAT_ARM_S5H_ARM_bits_packet_MSK                (0xFFFFFFFF)
+  #define GODLAT_CR_G_ODLAT_ARM_S5H_ARM_bits_packet_MAX                (0xFFFFFFFF)
+
+#define GODLAT_CR_G_ODLAT_MASK_S5L_REG                               (0x00000458)
+  #define GODLAT_CR_G_ODLAT_MASK_S5L_Mask_bits_OFF                     ( 0)
+  #define GODLAT_CR_G_ODLAT_MASK_S5L_Mask_bits_WID                     (32)
+  #define GODLAT_CR_G_ODLAT_MASK_S5L_Mask_bits_MSK                     (0xFFFFFFFF)
+  #define GODLAT_CR_G_ODLAT_MASK_S5L_Mask_bits_MAX                     (0xFFFFFFFF)
+
+#define GODLAT_CR_G_ODLAT_MASK_S5H_REG                               (0x0000045C)
+  #define GODLAT_CR_G_ODLAT_MASK_S5H_Mask_bits_OFF                     ( 0)
+  #define GODLAT_CR_G_ODLAT_MASK_S5H_Mask_bits_WID                     (32)
+  #define GODLAT_CR_G_ODLAT_MASK_S5H_Mask_bits_MSK                     (0xFFFFFFFF)
+  #define GODLAT_CR_G_ODLAT_MASK_S5H_Mask_bits_MAX                     (0xFFFFFFFF)
+
+#define GODLAT_CR_G_ODLAT_ARM_S6L_REG                                (0x00000460)
+  #define GODLAT_CR_G_ODLAT_ARM_S6L_ARM_bits_packet_OFF                ( 0)
+  #define GODLAT_CR_G_ODLAT_ARM_S6L_ARM_bits_packet_WID                (32)
+  #define GODLAT_CR_G_ODLAT_ARM_S6L_ARM_bits_packet_MSK                (0xFFFFFFFF)
+  #define GODLAT_CR_G_ODLAT_ARM_S6L_ARM_bits_packet_MAX                (0xFFFFFFFF)
+
+#define GODLAT_CR_G_ODLAT_ARM_S6H_REG                                (0x00000464)
+  #define GODLAT_CR_G_ODLAT_ARM_S6H_ARM_bits_packet_OFF                ( 0)
+  #define GODLAT_CR_G_ODLAT_ARM_S6H_ARM_bits_packet_WID                (32)
+  #define GODLAT_CR_G_ODLAT_ARM_S6H_ARM_bits_packet_MSK                (0xFFFFFFFF)
+  #define GODLAT_CR_G_ODLAT_ARM_S6H_ARM_bits_packet_MAX                (0xFFFFFFFF)
+
+#define GODLAT_CR_G_ODLAT_MASK_S6L_REG                               (0x00000468)
+  #define GODLAT_CR_G_ODLAT_MASK_S6L_Mask_bits_OFF                     ( 0)
+  #define GODLAT_CR_G_ODLAT_MASK_S6L_Mask_bits_WID                     (32)
+  #define GODLAT_CR_G_ODLAT_MASK_S6L_Mask_bits_MSK                     (0xFFFFFFFF)
+  #define GODLAT_CR_G_ODLAT_MASK_S6L_Mask_bits_MAX                     (0xFFFFFFFF)
+
+#define GODLAT_CR_G_ODLAT_MASK_S6H_REG                               (0x0000046C)
+  #define GODLAT_CR_G_ODLAT_MASK_S6H_Mask_bits_OFF                     ( 0)
+  #define GODLAT_CR_G_ODLAT_MASK_S6H_Mask_bits_WID                     (32)
+  #define GODLAT_CR_G_ODLAT_MASK_S6H_Mask_bits_MSK                     (0xFFFFFFFF)
+  #define GODLAT_CR_G_ODLAT_MASK_S6H_Mask_bits_MAX                     (0xFFFFFFFF)
+
+#define GODLAT_CR_G_ODLAT_ARM_S7L_REG                                (0x00000470)
+  #define GODLAT_CR_G_ODLAT_ARM_S7L_ARM_bits_packet_OFF                ( 0)
+  #define GODLAT_CR_G_ODLAT_ARM_S7L_ARM_bits_packet_WID                (32)
+  #define GODLAT_CR_G_ODLAT_ARM_S7L_ARM_bits_packet_MSK                (0xFFFFFFFF)
+  #define GODLAT_CR_G_ODLAT_ARM_S7L_ARM_bits_packet_MAX                (0xFFFFFFFF)
+
+#define GODLAT_CR_G_ODLAT_ARM_S7H_REG                                (0x00000474)
+  #define GODLAT_CR_G_ODLAT_ARM_S7H_ARM_bits_packet_OFF                ( 0)
+  #define GODLAT_CR_G_ODLAT_ARM_S7H_ARM_bits_packet_WID                (32)
+  #define GODLAT_CR_G_ODLAT_ARM_S7H_ARM_bits_packet_MSK                (0xFFFFFFFF)
+  #define GODLAT_CR_G_ODLAT_ARM_S7H_ARM_bits_packet_MAX                (0xFFFFFFFF)
+
+#define GODLAT_CR_G_ODLAT_MASK_S7L_REG                               (0x00000478)
+  #define GODLAT_CR_G_ODLAT_MASK_S7L_Mask_bits_OFF                     ( 0)
+  #define GODLAT_CR_G_ODLAT_MASK_S7L_Mask_bits_WID                     (32)
+  #define GODLAT_CR_G_ODLAT_MASK_S7L_Mask_bits_MSK                     (0xFFFFFFFF)
+  #define GODLAT_CR_G_ODLAT_MASK_S7L_Mask_bits_MAX                     (0xFFFFFFFF)
+
+#define GODLAT_CR_G_ODLAT_MASK_S7H_REG                               (0x0000047C)
+  #define GODLAT_CR_G_ODLAT_MASK_S7H_Mask_bits_OFF                     ( 0)
+  #define GODLAT_CR_G_ODLAT_MASK_S7H_Mask_bits_WID                     (32)
+  #define GODLAT_CR_G_ODLAT_MASK_S7H_Mask_bits_MSK                     (0xFFFFFFFF)
+  #define GODLAT_CR_G_ODLAT_MASK_S7H_Mask_bits_MAX                     (0xFFFFFFFF)
+
+#define GODLAT_CR_G_ODLAT_CMD_REG                                    (0x00000480)
+  #define GODLAT_CR_G_ODLAT_CMD_UX_TMR_BASE_A_OFF                      ( 0)
+  #define GODLAT_CR_G_ODLAT_CMD_UX_TMR_BASE_A_WID                      ( 1)
+  #define GODLAT_CR_G_ODLAT_CMD_UX_TMR_BASE_A_MSK                      (0x00000001)
+  #define GODLAT_CR_G_ODLAT_CMD_UX_TMR_BASE_A_MAX                      (0x00000001)
+  #define GODLAT_CR_G_ODLAT_CMD_UX_TMR_BASE_A_DEF                      (0x00000000)
+  #define GODLAT_CR_G_ODLAT_CMD_UX_TMR_BASE_B_OFF                      ( 1)
+  #define GODLAT_CR_G_ODLAT_CMD_UX_TMR_BASE_B_WID                      ( 1)
+  #define GODLAT_CR_G_ODLAT_CMD_UX_TMR_BASE_B_MSK                      (0x00000002)
+  #define GODLAT_CR_G_ODLAT_CMD_UX_TMR_BASE_B_MAX                      (0x00000001)
+  #define GODLAT_CR_G_ODLAT_CMD_UX_TMR_BASE_B_DEF                      (0x00000000)
+  #define GODLAT_CR_G_ODLAT_CMD_OVF_ARM_IDI_OFF                        ( 2)
+  #define GODLAT_CR_G_ODLAT_CMD_OVF_ARM_IDI_WID                        ( 1)
+  #define GODLAT_CR_G_ODLAT_CMD_OVF_ARM_IDI_MSK                        (0x00000004)
+  #define GODLAT_CR_G_ODLAT_CMD_OVF_ARM_IDI_MAX                        (0x00000001)
+  #define GODLAT_CR_G_ODLAT_CMD_OVF_ARM_IDI_DEF                        (0x00000000)
+  #define GODLAT_CR_G_ODLAT_CMD_OVF_ARM_HIGH_OFF                       ( 3)
+  #define GODLAT_CR_G_ODLAT_CMD_OVF_ARM_HIGH_WID                       ( 5)
+  #define GODLAT_CR_G_ODLAT_CMD_OVF_ARM_HIGH_MSK                       (0x000000F8)
+  #define GODLAT_CR_G_ODLAT_CMD_OVF_ARM_HIGH_MAX                       (0x0000001F)
+  #define GODLAT_CR_G_ODLAT_CMD_OVF_ARM_HIGH_DEF                       (0x00000000)
+  #define GODLAT_CR_G_ODLAT_CMD_OVF_Mask_HIGH_OFF                      ( 8)
+  #define GODLAT_CR_G_ODLAT_CMD_OVF_Mask_HIGH_WID                      ( 5)
+  #define GODLAT_CR_G_ODLAT_CMD_OVF_Mask_HIGH_MSK                      (0x00001F00)
+  #define GODLAT_CR_G_ODLAT_CMD_OVF_Mask_HIGH_MAX                      (0x0000001F)
+  #define GODLAT_CR_G_ODLAT_CMD_OVF_Mask_HIGH_DEF                      (0x00000000)
+  #define GODLAT_CR_G_ODLAT_CMD_TimerA_units_OFF                       (18)
+  #define GODLAT_CR_G_ODLAT_CMD_TimerA_units_WID                       ( 3)
+  #define GODLAT_CR_G_ODLAT_CMD_TimerA_units_MSK                       (0x001C0000)
+  #define GODLAT_CR_G_ODLAT_CMD_TimerA_units_MAX                       (0x00000007)
+  #define GODLAT_CR_G_ODLAT_CMD_TimerA_units_DEF                       (0x00000000)
+  #define GODLAT_CR_G_ODLAT_CMD_TimerB_units_OFF                       (21)
+  #define GODLAT_CR_G_ODLAT_CMD_TimerB_units_WID                       ( 3)
+  #define GODLAT_CR_G_ODLAT_CMD_TimerB_units_MSK                       (0x00E00000)
+  #define GODLAT_CR_G_ODLAT_CMD_TimerB_units_MAX                       (0x00000007)
+  #define GODLAT_CR_G_ODLAT_CMD_TimerB_units_DEF                       (0x00000000)
+  #define GODLAT_CR_G_ODLAT_CMD_Which_Time_Base_OFF                    (24)
+  #define GODLAT_CR_G_ODLAT_CMD_Which_Time_Base_WID                    ( 4)
+  #define GODLAT_CR_G_ODLAT_CMD_Which_Time_Base_MSK                    (0x0F000000)
+  #define GODLAT_CR_G_ODLAT_CMD_Which_Time_Base_MAX                    (0x0000000F)
+  #define GODLAT_CR_G_ODLAT_CMD_Which_Time_Base_DEF                    (0x00000000)
+  #define GODLAT_CR_G_ODLAT_CMD_Tmr_Or_Cntr_Mode_OFF                   (28)
+  #define GODLAT_CR_G_ODLAT_CMD_Tmr_Or_Cntr_Mode_WID                   ( 4)
+  #define GODLAT_CR_G_ODLAT_CMD_Tmr_Or_Cntr_Mode_MSK                   (0xF0000000)
+  #define GODLAT_CR_G_ODLAT_CMD_Tmr_Or_Cntr_Mode_MAX                   (0x0000000F)
+  #define GODLAT_CR_G_ODLAT_CMD_Tmr_Or_Cntr_Mode_DEF                   (0x00000000)
+
+#define GODLAT_CR_G_ODLAT_SW_ENABLE_REG                              (0x00000484)
+  #define GODLAT_CR_G_ODLAT_SW_ENABLE_EN_SW_G_ODLAT_OFF                ( 0)
+  #define GODLAT_CR_G_ODLAT_SW_ENABLE_EN_SW_G_ODLAT_WID                ( 1)
+  #define GODLAT_CR_G_ODLAT_SW_ENABLE_EN_SW_G_ODLAT_MSK                (0x00000001)
+  #define GODLAT_CR_G_ODLAT_SW_ENABLE_EN_SW_G_ODLAT_MAX                (0x00000001)
+  #define GODLAT_CR_G_ODLAT_SW_ENABLE_EN_SW_G_ODLAT_DEF                (0x00000000)
+  #define GODLAT_CR_G_ODLAT_SW_ENABLE_EN_S0_OFF                        ( 8)
+  #define GODLAT_CR_G_ODLAT_SW_ENABLE_EN_S0_WID                        ( 1)
+  #define GODLAT_CR_G_ODLAT_SW_ENABLE_EN_S0_MSK                        (0x00000100)
+  #define GODLAT_CR_G_ODLAT_SW_ENABLE_EN_S0_MAX                        (0x00000001)
+  #define GODLAT_CR_G_ODLAT_SW_ENABLE_EN_S0_DEF                        (0x00000000)
+  #define GODLAT_CR_G_ODLAT_SW_ENABLE_EN_S1_OFF                        ( 9)
+  #define GODLAT_CR_G_ODLAT_SW_ENABLE_EN_S1_WID                        ( 1)
+  #define GODLAT_CR_G_ODLAT_SW_ENABLE_EN_S1_MSK                        (0x00000200)
+  #define GODLAT_CR_G_ODLAT_SW_ENABLE_EN_S1_MAX                        (0x00000001)
+  #define GODLAT_CR_G_ODLAT_SW_ENABLE_EN_S1_DEF                        (0x00000000)
+  #define GODLAT_CR_G_ODLAT_SW_ENABLE_EN_S2_OFF                        (10)
+  #define GODLAT_CR_G_ODLAT_SW_ENABLE_EN_S2_WID                        ( 1)
+  #define GODLAT_CR_G_ODLAT_SW_ENABLE_EN_S2_MSK                        (0x00000400)
+  #define GODLAT_CR_G_ODLAT_SW_ENABLE_EN_S2_MAX                        (0x00000001)
+  #define GODLAT_CR_G_ODLAT_SW_ENABLE_EN_S2_DEF                        (0x00000000)
+  #define GODLAT_CR_G_ODLAT_SW_ENABLE_EN_S3_OFF                        (11)
+  #define GODLAT_CR_G_ODLAT_SW_ENABLE_EN_S3_WID                        ( 1)
+  #define GODLAT_CR_G_ODLAT_SW_ENABLE_EN_S3_MSK                        (0x00000800)
+  #define GODLAT_CR_G_ODLAT_SW_ENABLE_EN_S3_MAX                        (0x00000001)
+  #define GODLAT_CR_G_ODLAT_SW_ENABLE_EN_S3_DEF                        (0x00000000)
+  #define GODLAT_CR_G_ODLAT_SW_ENABLE_EN_S4_OFF                        (12)
+  #define GODLAT_CR_G_ODLAT_SW_ENABLE_EN_S4_WID                        ( 1)
+  #define GODLAT_CR_G_ODLAT_SW_ENABLE_EN_S4_MSK                        (0x00001000)
+  #define GODLAT_CR_G_ODLAT_SW_ENABLE_EN_S4_MAX                        (0x00000001)
+  #define GODLAT_CR_G_ODLAT_SW_ENABLE_EN_S4_DEF                        (0x00000000)
+  #define GODLAT_CR_G_ODLAT_SW_ENABLE_EN_S5_OFF                        (13)
+  #define GODLAT_CR_G_ODLAT_SW_ENABLE_EN_S5_WID                        ( 1)
+  #define GODLAT_CR_G_ODLAT_SW_ENABLE_EN_S5_MSK                        (0x00002000)
+  #define GODLAT_CR_G_ODLAT_SW_ENABLE_EN_S5_MAX                        (0x00000001)
+  #define GODLAT_CR_G_ODLAT_SW_ENABLE_EN_S5_DEF                        (0x00000000)
+  #define GODLAT_CR_G_ODLAT_SW_ENABLE_EN_S6_OFF                        (14)
+  #define GODLAT_CR_G_ODLAT_SW_ENABLE_EN_S6_WID                        ( 1)
+  #define GODLAT_CR_G_ODLAT_SW_ENABLE_EN_S6_MSK                        (0x00004000)
+  #define GODLAT_CR_G_ODLAT_SW_ENABLE_EN_S6_MAX                        (0x00000001)
+  #define GODLAT_CR_G_ODLAT_SW_ENABLE_EN_S6_DEF                        (0x00000000)
+  #define GODLAT_CR_G_ODLAT_SW_ENABLE_EN_S7_OFF                        (15)
+  #define GODLAT_CR_G_ODLAT_SW_ENABLE_EN_S7_WID                        ( 1)
+  #define GODLAT_CR_G_ODLAT_SW_ENABLE_EN_S7_MSK                        (0x00008000)
+  #define GODLAT_CR_G_ODLAT_SW_ENABLE_EN_S7_MAX                        (0x00000001)
+  #define GODLAT_CR_G_ODLAT_SW_ENABLE_EN_S7_DEF                        (0x00000000)
+  #define GODLAT_CR_G_ODLAT_SW_ENABLE_MBP_Enable_OFF                   (16)
+  #define GODLAT_CR_G_ODLAT_SW_ENABLE_MBP_Enable_WID                   ( 1)
+  #define GODLAT_CR_G_ODLAT_SW_ENABLE_MBP_Enable_MSK                   (0x00010000)
+  #define GODLAT_CR_G_ODLAT_SW_ENABLE_MBP_Enable_MAX                   (0x00000001)
+  #define GODLAT_CR_G_ODLAT_SW_ENABLE_MBP_Enable_DEF                   (0x00000000)
+
+#define GODLAT_CR_G_ODLAT_MISC_CMD_REG                               (0x0000048C)
+  #define GODLAT_CR_G_ODLAT_MISC_CMD_Pulse_or_Sticky_Events_OFF        ( 0)
+  #define GODLAT_CR_G_ODLAT_MISC_CMD_Pulse_or_Sticky_Events_WID        ( 8)
+  #define GODLAT_CR_G_ODLAT_MISC_CMD_Pulse_or_Sticky_Events_MSK        (0x000000FF)
+  #define GODLAT_CR_G_ODLAT_MISC_CMD_Pulse_or_Sticky_Events_MAX        (0x000000FF)
+  #define GODLAT_CR_G_ODLAT_MISC_CMD_Pulse_or_Sticky_Events_DEF        (0x00000000)
+  #define GODLAT_CR_G_ODLAT_MISC_CMD_Pulse_or_Sticky_MBP_OFF           ( 8)
+  #define GODLAT_CR_G_ODLAT_MISC_CMD_Pulse_or_Sticky_MBP_WID           ( 1)
+  #define GODLAT_CR_G_ODLAT_MISC_CMD_Pulse_or_Sticky_MBP_MSK           (0x00000100)
+  #define GODLAT_CR_G_ODLAT_MISC_CMD_Pulse_or_Sticky_MBP_MAX           (0x00000001)
+  #define GODLAT_CR_G_ODLAT_MISC_CMD_Pulse_or_Sticky_MBP_DEF           (0x00000000)
+  #define GODLAT_CR_G_ODLAT_MISC_CMD_Pulse_or_Sticky_TO_OFF            ( 9)
+  #define GODLAT_CR_G_ODLAT_MISC_CMD_Pulse_or_Sticky_TO_WID            ( 4)
+  #define GODLAT_CR_G_ODLAT_MISC_CMD_Pulse_or_Sticky_TO_MSK            (0x00001E00)
+  #define GODLAT_CR_G_ODLAT_MISC_CMD_Pulse_or_Sticky_TO_MAX            (0x0000000F)
+  #define GODLAT_CR_G_ODLAT_MISC_CMD_Pulse_or_Sticky_TO_DEF            (0x00000000)
+  #define GODLAT_CR_G_ODLAT_MISC_CMD_OVF_ARM_LOW_OFF                   (13)
+  #define GODLAT_CR_G_ODLAT_MISC_CMD_OVF_ARM_LOW_WID                   ( 3)
+  #define GODLAT_CR_G_ODLAT_MISC_CMD_OVF_ARM_LOW_MSK                   (0x0000E000)
+  #define GODLAT_CR_G_ODLAT_MISC_CMD_OVF_ARM_LOW_MAX                   (0x00000007)
+  #define GODLAT_CR_G_ODLAT_MISC_CMD_OVF_ARM_LOW_DEF                   (0x00000000)
+  #define GODLAT_CR_G_ODLAT_MISC_CMD_OVF_MASK_LOW_OFF                  (16)
+  #define GODLAT_CR_G_ODLAT_MISC_CMD_OVF_MASK_LOW_WID                  ( 3)
+  #define GODLAT_CR_G_ODLAT_MISC_CMD_OVF_MASK_LOW_MSK                  (0x00070000)
+  #define GODLAT_CR_G_ODLAT_MISC_CMD_OVF_MASK_LOW_MAX                  (0x00000007)
+  #define GODLAT_CR_G_ODLAT_MISC_CMD_OVF_MASK_LOW_DEF                  (0x00000000)
+  #define GODLAT_CR_G_ODLAT_MISC_CMD_Which_MBP_Pin_A_OFF               (19)
+  #define GODLAT_CR_G_ODLAT_MISC_CMD_Which_MBP_Pin_A_WID               ( 3)
+  #define GODLAT_CR_G_ODLAT_MISC_CMD_Which_MBP_Pin_A_MSK               (0x00380000)
+  #define GODLAT_CR_G_ODLAT_MISC_CMD_Which_MBP_Pin_A_MAX               (0x00000007)
+  #define GODLAT_CR_G_ODLAT_MISC_CMD_Which_MBP_Pin_A_DEF               (0x00000000)
+  #define GODLAT_CR_G_ODLAT_MISC_CMD_Which_MBP_Pin_B_OFF               (22)
+  #define GODLAT_CR_G_ODLAT_MISC_CMD_Which_MBP_Pin_B_WID               ( 3)
+  #define GODLAT_CR_G_ODLAT_MISC_CMD_Which_MBP_Pin_B_MSK               (0x01C00000)
+  #define GODLAT_CR_G_ODLAT_MISC_CMD_Which_MBP_Pin_B_MAX               (0x00000007)
+  #define GODLAT_CR_G_ODLAT_MISC_CMD_Which_MBP_Pin_B_DEF               (0x00000000)
+  #define GODLAT_CR_G_ODLAT_MISC_CMD_Which_MBP_Pin_C_OFF               (25)
+  #define GODLAT_CR_G_ODLAT_MISC_CMD_Which_MBP_Pin_C_WID               ( 3)
+  #define GODLAT_CR_G_ODLAT_MISC_CMD_Which_MBP_Pin_C_MSK               (0x0E000000)
+  #define GODLAT_CR_G_ODLAT_MISC_CMD_Which_MBP_Pin_C_MAX               (0x00000007)
+  #define GODLAT_CR_G_ODLAT_MISC_CMD_Which_MBP_Pin_C_DEF               (0x00000000)
+  #define GODLAT_CR_G_ODLAT_MISC_CMD_Which_MBP_Pin_D_OFF               (28)
+  #define GODLAT_CR_G_ODLAT_MISC_CMD_Which_MBP_Pin_D_WID               ( 3)
+  #define GODLAT_CR_G_ODLAT_MISC_CMD_Which_MBP_Pin_D_MSK               (0x70000000)
+  #define GODLAT_CR_G_ODLAT_MISC_CMD_Which_MBP_Pin_D_MAX               (0x00000007)
+  #define GODLAT_CR_G_ODLAT_MISC_CMD_Which_MBP_Pin_D_DEF               (0x00000000)
+
+#define GDXC_CR_GT_VISA2OCLA_CFG_FILTER_REG                          (0x00000500)
+  #define GDXC_CR_GT_VISA2OCLA_CFG_FILTER_Ln0Mask_OFF                  ( 0)
+  #define GDXC_CR_GT_VISA2OCLA_CFG_FILTER_Ln0Mask_WID                  ( 8)
+  #define GDXC_CR_GT_VISA2OCLA_CFG_FILTER_Ln0Mask_MSK                  (0x000000FF)
+  #define GDXC_CR_GT_VISA2OCLA_CFG_FILTER_Ln0Mask_MAX                  (0x000000FF)
+  #define GDXC_CR_GT_VISA2OCLA_CFG_FILTER_Ln0Mask_DEF                  (0x00000000)
+  #define GDXC_CR_GT_VISA2OCLA_CFG_FILTER_Ln1Mask_OFF                  ( 8)
+  #define GDXC_CR_GT_VISA2OCLA_CFG_FILTER_Ln1Mask_WID                  ( 8)
+  #define GDXC_CR_GT_VISA2OCLA_CFG_FILTER_Ln1Mask_MSK                  (0x0000FF00)
+  #define GDXC_CR_GT_VISA2OCLA_CFG_FILTER_Ln1Mask_MAX                  (0x000000FF)
+  #define GDXC_CR_GT_VISA2OCLA_CFG_FILTER_Ln1Mask_DEF                  (0x00000000)
+  #define GDXC_CR_GT_VISA2OCLA_CFG_FILTER_AssertMode_OFF               (16)
+  #define GDXC_CR_GT_VISA2OCLA_CFG_FILTER_AssertMode_WID               ( 1)
+  #define GDXC_CR_GT_VISA2OCLA_CFG_FILTER_AssertMode_MSK               (0x00010000)
+  #define GDXC_CR_GT_VISA2OCLA_CFG_FILTER_AssertMode_MAX               (0x00000001)
+  #define GDXC_CR_GT_VISA2OCLA_CFG_FILTER_AssertMode_DEF               (0x00000000)
+  #define GDXC_CR_GT_VISA2OCLA_CFG_FILTER_CompEn_OFF                   (17)
+  #define GDXC_CR_GT_VISA2OCLA_CFG_FILTER_CompEn_WID                   ( 1)
+  #define GDXC_CR_GT_VISA2OCLA_CFG_FILTER_CompEn_MSK                   (0x00020000)
+  #define GDXC_CR_GT_VISA2OCLA_CFG_FILTER_CompEn_MAX                   (0x00000001)
+  #define GDXC_CR_GT_VISA2OCLA_CFG_FILTER_CompEn_DEF                   (0x00000001)
+  #define GDXC_CR_GT_VISA2OCLA_CFG_FILTER_GT_VISA_En_OFF               (18)
+  #define GDXC_CR_GT_VISA2OCLA_CFG_FILTER_GT_VISA_En_WID               ( 1)
+  #define GDXC_CR_GT_VISA2OCLA_CFG_FILTER_GT_VISA_En_MSK               (0x00040000)
+  #define GDXC_CR_GT_VISA2OCLA_CFG_FILTER_GT_VISA_En_MAX               (0x00000001)
+  #define GDXC_CR_GT_VISA2OCLA_CFG_FILTER_GT_VISA_En_DEF               (0x00000000)
+
+#define GDXC_CR_GDXC_MAN_CONFIG_REG                                  (0x00000504)
+  #define GDXC_CR_GDXC_MAN_CONFIG_Man_Reset_GDXC_OFF                   ( 0)
+  #define GDXC_CR_GDXC_MAN_CONFIG_Man_Reset_GDXC_WID                   ( 1)
+  #define GDXC_CR_GDXC_MAN_CONFIG_Man_Reset_GDXC_MSK                   (0x00000001)
+  #define GDXC_CR_GDXC_MAN_CONFIG_Man_Reset_GDXC_MAX                   (0x00000001)
+  #define GDXC_CR_GDXC_MAN_CONFIG_Man_Reset_GDXC_DEF                   (0x00000000)
+  #define GDXC_CR_GDXC_MAN_CONFIG_Man_Reset_G_ODLAT_OFF                ( 1)
+  #define GDXC_CR_GDXC_MAN_CONFIG_Man_Reset_G_ODLAT_WID                ( 1)
+  #define GDXC_CR_GDXC_MAN_CONFIG_Man_Reset_G_ODLAT_MSK                (0x00000002)
+  #define GDXC_CR_GDXC_MAN_CONFIG_Man_Reset_G_ODLAT_MAX                (0x00000001)
+  #define GDXC_CR_GDXC_MAN_CONFIG_Man_Reset_G_ODLAT_DEF                (0x00000000)
+  #define GDXC_CR_GDXC_MAN_CONFIG_IOT_Start_OFF                        ( 2)
+  #define GDXC_CR_GDXC_MAN_CONFIG_IOT_Start_WID                        ( 1)
+  #define GDXC_CR_GDXC_MAN_CONFIG_IOT_Start_MSK                        (0x00000004)
+  #define GDXC_CR_GDXC_MAN_CONFIG_IOT_Start_MAX                        (0x00000001)
+  #define GDXC_CR_GDXC_MAN_CONFIG_IOT_Start_DEF                        (0x00000000)
+  #define GDXC_CR_GDXC_MAN_CONFIG_IOT_Stop_OFF                         ( 3)
+  #define GDXC_CR_GDXC_MAN_CONFIG_IOT_Stop_WID                         ( 1)
+  #define GDXC_CR_GDXC_MAN_CONFIG_IOT_Stop_MSK                         (0x00000008)
+  #define GDXC_CR_GDXC_MAN_CONFIG_IOT_Stop_MAX                         (0x00000001)
+  #define GDXC_CR_GDXC_MAN_CONFIG_IOT_Stop_DEF                         (0x00000000)
+  #define GDXC_CR_GDXC_MAN_CONFIG_IOT_Trigger_OFF                      ( 4)
+  #define GDXC_CR_GDXC_MAN_CONFIG_IOT_Trigger_WID                      ( 1)
+  #define GDXC_CR_GDXC_MAN_CONFIG_IOT_Trigger_MSK                      (0x00000010)
+  #define GDXC_CR_GDXC_MAN_CONFIG_IOT_Trigger_MAX                      (0x00000001)
+  #define GDXC_CR_GDXC_MAN_CONFIG_IOT_Trigger_DEF                      (0x00000000)
+  #define GDXC_CR_GDXC_MAN_CONFIG_IOT_Force_Flush_OFF                  ( 5)
+  #define GDXC_CR_GDXC_MAN_CONFIG_IOT_Force_Flush_WID                  ( 1)
+  #define GDXC_CR_GDXC_MAN_CONFIG_IOT_Force_Flush_MSK                  (0x00000020)
+  #define GDXC_CR_GDXC_MAN_CONFIG_IOT_Force_Flush_MAX                  (0x00000001)
+  #define GDXC_CR_GDXC_MAN_CONFIG_IOT_Force_Flush_DEF                  (0x00000000)
+  #define GDXC_CR_GDXC_MAN_CONFIG_SPARE_OFF                            (16)
+  #define GDXC_CR_GDXC_MAN_CONFIG_SPARE_WID                            ( 8)
+  #define GDXC_CR_GDXC_MAN_CONFIG_SPARE_MSK                            (0x00FF0000)
+  #define GDXC_CR_GDXC_MAN_CONFIG_SPARE_MAX                            (0x000000FF)
+  #define GDXC_CR_GDXC_MAN_CONFIG_SPARE_DEF                            (0x00000000)
+
+#define GDXC_CR_GDXC_ALIGN_REG                                       (0x00000508)
+  #define GDXC_CR_GDXC_ALIGN_mbpout_OFF                                ( 0)
+  #define GDXC_CR_GDXC_ALIGN_mbpout_WID                                ( 2)
+  #define GDXC_CR_GDXC_ALIGN_mbpout_MSK                                (0x00000003)
+  #define GDXC_CR_GDXC_ALIGN_mbpout_MAX                                (0x00000003)
+  #define GDXC_CR_GDXC_ALIGN_mbpout_DEF                                (0x00000001)
+
+#define GDXC_CR_GDXC_RR_ARB_THRESH_REG                               (0x00000510)
+  #define GDXC_CR_GDXC_RR_ARB_THRESH_AD_OFF                            ( 0)
+  #define GDXC_CR_GDXC_RR_ARB_THRESH_AD_WID                            ( 6)
+  #define GDXC_CR_GDXC_RR_ARB_THRESH_AD_MSK                            (0x0000003F)
+  #define GDXC_CR_GDXC_RR_ARB_THRESH_AD_MAX                            (0x0000003F)
+  #define GDXC_CR_GDXC_RR_ARB_THRESH_AD_DEF                            (0x00000004)
+  #define GDXC_CR_GDXC_RR_ARB_THRESH_BLHDR0_OFF                        ( 6)
+  #define GDXC_CR_GDXC_RR_ARB_THRESH_BLHDR0_WID                        ( 7)
+  #define GDXC_CR_GDXC_RR_ARB_THRESH_BLHDR0_MSK                        (0x00001FC0)
+  #define GDXC_CR_GDXC_RR_ARB_THRESH_BLHDR0_MAX                        (0x0000007F)
+  #define GDXC_CR_GDXC_RR_ARB_THRESH_BLHDR0_DEF                        (0x00000004)
+  #define GDXC_CR_GDXC_RR_ARB_THRESH_BLHDR1ADDR_OFF                    (13)
+  #define GDXC_CR_GDXC_RR_ARB_THRESH_BLHDR1ADDR_WID                    ( 6)
+  #define GDXC_CR_GDXC_RR_ARB_THRESH_BLHDR1ADDR_MSK                    (0x0007E000)
+  #define GDXC_CR_GDXC_RR_ARB_THRESH_BLHDR1ADDR_MAX                    (0x0000003F)
+  #define GDXC_CR_GDXC_RR_ARB_THRESH_BLHDR1ADDR_DEF                    (0x00000008)
+  #define GDXC_CR_GDXC_RR_ARB_THRESH_AK_OFF                            (19)
+  #define GDXC_CR_GDXC_RR_ARB_THRESH_AK_WID                            ( 6)
+  #define GDXC_CR_GDXC_RR_ARB_THRESH_AK_MSK                            (0x01F80000)
+  #define GDXC_CR_GDXC_RR_ARB_THRESH_AK_MAX                            (0x0000003F)
+  #define GDXC_CR_GDXC_RR_ARB_THRESH_AK_DEF                            (0x00000004)
+  #define GDXC_CR_GDXC_RR_ARB_THRESH_IV_OFF                            (25)
+  #define GDXC_CR_GDXC_RR_ARB_THRESH_IV_WID                            ( 2)
+  #define GDXC_CR_GDXC_RR_ARB_THRESH_IV_MSK                            (0x06000000)
+  #define GDXC_CR_GDXC_RR_ARB_THRESH_IV_MAX                            (0x00000003)
+  #define GDXC_CR_GDXC_RR_ARB_THRESH_IV_DEF                            (0x00000003)
+  #define GDXC_CR_GDXC_RR_ARB_THRESH_Wrap_OFF                          (27)
+  #define GDXC_CR_GDXC_RR_ARB_THRESH_Wrap_WID                          ( 3)
+  #define GDXC_CR_GDXC_RR_ARB_THRESH_Wrap_MSK                          (0x38000000)
+  #define GDXC_CR_GDXC_RR_ARB_THRESH_Wrap_MAX                          (0x00000007)
+  #define GDXC_CR_GDXC_RR_ARB_THRESH_Wrap_DEF                          (0x00000002)
+  #define GDXC_CR_GDXC_RR_ARB_THRESH_MOT_OFF                           (30)
+  #define GDXC_CR_GDXC_RR_ARB_THRESH_MOT_WID                           ( 5)
+  #define GDXC_CR_GDXC_RR_ARB_THRESH_MOT_MSK                           (0x7C0000000)
+  #define GDXC_CR_GDXC_RR_ARB_THRESH_MOT_MAX                           (0x0000001F)
+  #define GDXC_CR_GDXC_RR_ARB_THRESH_MOT_DEF                           (0x00000002)
+  #define GDXC_CR_GDXC_RR_ARB_THRESH_IDI_OFF                           (35)
+  #define GDXC_CR_GDXC_RR_ARB_THRESH_IDI_WID                           ( 5)
+  #define GDXC_CR_GDXC_RR_ARB_THRESH_IDI_MSK                           (0xF800000000)
+  #define GDXC_CR_GDXC_RR_ARB_THRESH_IDI_MAX                           (0x0000001F)
+  #define GDXC_CR_GDXC_RR_ARB_THRESH_IDI_DEF                           (0x00000002)
+  #define GDXC_CR_GDXC_RR_ARB_THRESH_FClk_OFF                          (40)
+  #define GDXC_CR_GDXC_RR_ARB_THRESH_FClk_WID                          ( 5)
+  #define GDXC_CR_GDXC_RR_ARB_THRESH_FClk_MSK                          (0x1F0000000000)
+  #define GDXC_CR_GDXC_RR_ARB_THRESH_FClk_MAX                          (0x0000001F)
+  #define GDXC_CR_GDXC_RR_ARB_THRESH_FClk_DEF                          (0x00000002)
+  #define GDXC_CR_GDXC_RR_ARB_THRESH_UClkMsgCh_OFF                     (45)
+  #define GDXC_CR_GDXC_RR_ARB_THRESH_UClkMsgCh_WID                     ( 5)
+  #define GDXC_CR_GDXC_RR_ARB_THRESH_UClkMsgCh_MSK                     (0x3E00000000000)
+  #define GDXC_CR_GDXC_RR_ARB_THRESH_UClkMsgCh_MAX                     (0x0000001F)
+  #define GDXC_CR_GDXC_RR_ARB_THRESH_UClkMsgCh_DEF                     (0x00000002)
+
+#define GDXC_CR_G_ODLAT_FIRE_STATUS_REG                              (0x00000518)
+  #define GDXC_CR_G_ODLAT_FIRE_STATUS_Start_Status_OFF                 ( 0)
+  #define GDXC_CR_G_ODLAT_FIRE_STATUS_Start_Status_WID                 ( 1)
+  #define GDXC_CR_G_ODLAT_FIRE_STATUS_Start_Status_MSK                 (0x00000001)
+  #define GDXC_CR_G_ODLAT_FIRE_STATUS_Start_Status_MAX                 (0x00000001)
+  #define GDXC_CR_G_ODLAT_FIRE_STATUS_Start_Status_DEF                 (0x00000000)
+  #define GDXC_CR_G_ODLAT_FIRE_STATUS_Trigger_Status_OFF               ( 1)
+  #define GDXC_CR_G_ODLAT_FIRE_STATUS_Trigger_Status_WID               ( 1)
+  #define GDXC_CR_G_ODLAT_FIRE_STATUS_Trigger_Status_MSK               (0x00000002)
+  #define GDXC_CR_G_ODLAT_FIRE_STATUS_Trigger_Status_MAX               (0x00000001)
+  #define GDXC_CR_G_ODLAT_FIRE_STATUS_Trigger_Status_DEF               (0x00000000)
+  #define GDXC_CR_G_ODLAT_FIRE_STATUS_Stop_Status_OFF                  ( 2)
+  #define GDXC_CR_G_ODLAT_FIRE_STATUS_Stop_Status_WID                  ( 1)
+  #define GDXC_CR_G_ODLAT_FIRE_STATUS_Stop_Status_MSK                  (0x00000004)
+  #define GDXC_CR_G_ODLAT_FIRE_STATUS_Stop_Status_MAX                  (0x00000001)
+  #define GDXC_CR_G_ODLAT_FIRE_STATUS_Stop_Status_DEF                  (0x00000000)
+  #define GDXC_CR_G_ODLAT_FIRE_STATUS_Muliple_Hit_OFF                  ( 3)
+  #define GDXC_CR_G_ODLAT_FIRE_STATUS_Muliple_Hit_WID                  ( 1)
+  #define GDXC_CR_G_ODLAT_FIRE_STATUS_Muliple_Hit_MSK                  (0x00000008)
+  #define GDXC_CR_G_ODLAT_FIRE_STATUS_Muliple_Hit_MAX                  (0x00000001)
+  #define GDXC_CR_G_ODLAT_FIRE_STATUS_Muliple_Hit_DEF                  (0x00000000)
+  #define GDXC_CR_G_ODLAT_FIRE_STATUS_Bubbles_Status_OFF               ( 4)
+  #define GDXC_CR_G_ODLAT_FIRE_STATUS_Bubbles_Status_WID               ( 6)
+  #define GDXC_CR_G_ODLAT_FIRE_STATUS_Bubbles_Status_MSK               (0x000003F0)
+  #define GDXC_CR_G_ODLAT_FIRE_STATUS_Bubbles_Status_MAX               (0x0000003F)
+  #define GDXC_CR_G_ODLAT_FIRE_STATUS_Bubbles_Status_DEF               (0x00000000)
+
+#define GDXC_CR_TRIGGER_TO_STOP_DELAY_REG                            (0x00000520)
+  #define GDXC_CR_TRIGGER_TO_STOP_DELAY_Delay_count_OFF                ( 0)
+  #define GDXC_CR_TRIGGER_TO_STOP_DELAY_Delay_count_WID                (25)
+  #define GDXC_CR_TRIGGER_TO_STOP_DELAY_Delay_count_MSK                (0x01FFFFFF)
+  #define GDXC_CR_TRIGGER_TO_STOP_DELAY_Delay_count_MAX                (0x01FFFFFF)
+  #define GDXC_CR_TRIGGER_TO_STOP_DELAY_Delay_count_DEF                (0x00000000)
+
+#define GDXC_CR_IOT_STATUS_REG                                       (0x00000524)
+  #define GDXC_CR_IOT_STATUS_Disabled_OFF                              ( 0)
+  #define GDXC_CR_IOT_STATUS_Disabled_WID                              ( 1)
+  #define GDXC_CR_IOT_STATUS_Disabled_MSK                              (0x00000001)
+  #define GDXC_CR_IOT_STATUS_Disabled_MAX                              (0x00000001)
+  #define GDXC_CR_IOT_STATUS_Disabled_DEF                              (0x00000001)
+  #define GDXC_CR_IOT_STATUS_Idle_OFF                                  ( 1)
+  #define GDXC_CR_IOT_STATUS_Idle_WID                                  ( 1)
+  #define GDXC_CR_IOT_STATUS_Idle_MSK                                  (0x00000002)
+  #define GDXC_CR_IOT_STATUS_Idle_MAX                                  (0x00000001)
+  #define GDXC_CR_IOT_STATUS_Idle_DEF                                  (0x00000000)
+  #define GDXC_CR_IOT_STATUS_Running_OFF                               ( 2)
+  #define GDXC_CR_IOT_STATUS_Running_WID                               ( 1)
+  #define GDXC_CR_IOT_STATUS_Running_MSK                               (0x00000004)
+  #define GDXC_CR_IOT_STATUS_Running_MAX                               (0x00000001)
+  #define GDXC_CR_IOT_STATUS_Running_DEF                               (0x00000000)
+  #define GDXC_CR_IOT_STATUS_IOT_Triggered_OFF                         ( 3)
+  #define GDXC_CR_IOT_STATUS_IOT_Triggered_WID                         ( 1)
+  #define GDXC_CR_IOT_STATUS_IOT_Triggered_MSK                         (0x00000008)
+  #define GDXC_CR_IOT_STATUS_IOT_Triggered_MAX                         (0x00000001)
+  #define GDXC_CR_IOT_STATUS_IOT_Triggered_DEF                         (0x00000000)
+  #define GDXC_CR_IOT_STATUS_Sticky_triggered_OFF                      ( 4)
+  #define GDXC_CR_IOT_STATUS_Sticky_triggered_WID                      ( 1)
+  #define GDXC_CR_IOT_STATUS_Sticky_triggered_MSK                      (0x00000010)
+  #define GDXC_CR_IOT_STATUS_Sticky_triggered_MAX                      (0x00000001)
+  #define GDXC_CR_IOT_STATUS_Sticky_triggered_DEF                      (0x00000000)
+  #define GDXC_CR_IOT_STATUS_Remaining_count_OFF                       ( 6)
+  #define GDXC_CR_IOT_STATUS_Remaining_count_WID                       (25)
+  #define GDXC_CR_IOT_STATUS_Remaining_count_MSK                       (0x7FFFFFC0)
+  #define GDXC_CR_IOT_STATUS_Remaining_count_MAX                       (0x01FFFFFF)
+  #define GDXC_CR_IOT_STATUS_Remaining_count_DEF                       (0x00000000)
+
+#define GODLAT_CR_G_ODLAT_OCLAHDR_S0TO3_REG                          (0x00000528)
+  #define GODLAT_CR_G_ODLAT_OCLAHDR_S0TO3_S0_OclaHdr_OFF               ( 0)
+  #define GODLAT_CR_G_ODLAT_OCLAHDR_S0TO3_S0_OclaHdr_WID               ( 8)
+  #define GODLAT_CR_G_ODLAT_OCLAHDR_S0TO3_S0_OclaHdr_MSK               (0x000000FF)
+  #define GODLAT_CR_G_ODLAT_OCLAHDR_S0TO3_S0_OclaHdr_MAX               (0x000000FF)
+  #define GODLAT_CR_G_ODLAT_OCLAHDR_S0TO3_S1_OclaHdr_OFF               ( 8)
+  #define GODLAT_CR_G_ODLAT_OCLAHDR_S0TO3_S1_OclaHdr_WID               ( 8)
+  #define GODLAT_CR_G_ODLAT_OCLAHDR_S0TO3_S1_OclaHdr_MSK               (0x0000FF00)
+  #define GODLAT_CR_G_ODLAT_OCLAHDR_S0TO3_S1_OclaHdr_MAX               (0x000000FF)
+  #define GODLAT_CR_G_ODLAT_OCLAHDR_S0TO3_S2_OclaHdr_OFF               (16)
+  #define GODLAT_CR_G_ODLAT_OCLAHDR_S0TO3_S2_OclaHdr_WID               ( 8)
+  #define GODLAT_CR_G_ODLAT_OCLAHDR_S0TO3_S2_OclaHdr_MSK               (0x00FF0000)
+  #define GODLAT_CR_G_ODLAT_OCLAHDR_S0TO3_S2_OclaHdr_MAX               (0x000000FF)
+  #define GODLAT_CR_G_ODLAT_OCLAHDR_S0TO3_S3_OclaHdr_OFF               (24)
+  #define GODLAT_CR_G_ODLAT_OCLAHDR_S0TO3_S3_OclaHdr_WID               ( 8)
+  #define GODLAT_CR_G_ODLAT_OCLAHDR_S0TO3_S3_OclaHdr_MSK               (0xFF000000)
+  #define GODLAT_CR_G_ODLAT_OCLAHDR_S0TO3_S3_OclaHdr_MAX               (0x000000FF)
+
+#define GODLAT_CR_G_ODLAT_OCLAHDR_S4TO7_REG                          (0x0000052C)
+  #define GODLAT_CR_G_ODLAT_OCLAHDR_S4TO7_S4_OclaHdr_OFF               ( 0)
+  #define GODLAT_CR_G_ODLAT_OCLAHDR_S4TO7_S4_OclaHdr_WID               ( 8)
+  #define GODLAT_CR_G_ODLAT_OCLAHDR_S4TO7_S4_OclaHdr_MSK               (0x000000FF)
+  #define GODLAT_CR_G_ODLAT_OCLAHDR_S4TO7_S4_OclaHdr_MAX               (0x000000FF)
+  #define GODLAT_CR_G_ODLAT_OCLAHDR_S4TO7_S5_OclaHdr_OFF               ( 8)
+  #define GODLAT_CR_G_ODLAT_OCLAHDR_S4TO7_S5_OclaHdr_WID               ( 8)
+  #define GODLAT_CR_G_ODLAT_OCLAHDR_S4TO7_S5_OclaHdr_MSK               (0x0000FF00)
+  #define GODLAT_CR_G_ODLAT_OCLAHDR_S4TO7_S5_OclaHdr_MAX               (0x000000FF)
+  #define GODLAT_CR_G_ODLAT_OCLAHDR_S4TO7_S6_OclaHdr_OFF               (16)
+  #define GODLAT_CR_G_ODLAT_OCLAHDR_S4TO7_S6_OclaHdr_WID               ( 8)
+  #define GODLAT_CR_G_ODLAT_OCLAHDR_S4TO7_S6_OclaHdr_MSK               (0x00FF0000)
+  #define GODLAT_CR_G_ODLAT_OCLAHDR_S4TO7_S6_OclaHdr_MAX               (0x000000FF)
+  #define GODLAT_CR_G_ODLAT_OCLAHDR_S4TO7_S7_OclaHdr_OFF               (24)
+  #define GODLAT_CR_G_ODLAT_OCLAHDR_S4TO7_S7_OclaHdr_WID               ( 8)
+  #define GODLAT_CR_G_ODLAT_OCLAHDR_S4TO7_S7_OclaHdr_MSK               (0xFF000000)
+  #define GODLAT_CR_G_ODLAT_OCLAHDR_S4TO7_S7_OclaHdr_MAX               (0x000000FF)
+
+#define GODLAT_CR_G_ODLAT_FST_REG                                    (0x00000530)
+  #define GODLAT_CR_G_ODLAT_FST_S0_FST_OFF                             ( 0)
+  #define GODLAT_CR_G_ODLAT_FST_S0_FST_WID                             ( 2)
+  #define GODLAT_CR_G_ODLAT_FST_S0_FST_MSK                             (0x00000003)
+  #define GODLAT_CR_G_ODLAT_FST_S0_FST_MAX                             (0x00000003)
+  #define GODLAT_CR_G_ODLAT_FST_S1_FST_OFF                             ( 2)
+  #define GODLAT_CR_G_ODLAT_FST_S1_FST_WID                             ( 2)
+  #define GODLAT_CR_G_ODLAT_FST_S1_FST_MSK                             (0x0000000C)
+  #define GODLAT_CR_G_ODLAT_FST_S1_FST_MAX                             (0x00000003)
+  #define GODLAT_CR_G_ODLAT_FST_S2_FST_OFF                             ( 4)
+  #define GODLAT_CR_G_ODLAT_FST_S2_FST_WID                             ( 2)
+  #define GODLAT_CR_G_ODLAT_FST_S2_FST_MSK                             (0x00000030)
+  #define GODLAT_CR_G_ODLAT_FST_S2_FST_MAX                             (0x00000003)
+  #define GODLAT_CR_G_ODLAT_FST_S3_FST_OFF                             ( 6)
+  #define GODLAT_CR_G_ODLAT_FST_S3_FST_WID                             ( 2)
+  #define GODLAT_CR_G_ODLAT_FST_S3_FST_MSK                             (0x000000C0)
+  #define GODLAT_CR_G_ODLAT_FST_S3_FST_MAX                             (0x00000003)
+  #define GODLAT_CR_G_ODLAT_FST_S4_FST_OFF                             ( 8)
+  #define GODLAT_CR_G_ODLAT_FST_S4_FST_WID                             ( 2)
+  #define GODLAT_CR_G_ODLAT_FST_S4_FST_MSK                             (0x00000300)
+  #define GODLAT_CR_G_ODLAT_FST_S4_FST_MAX                             (0x00000003)
+  #define GODLAT_CR_G_ODLAT_FST_S5_FST_OFF                             (10)
+  #define GODLAT_CR_G_ODLAT_FST_S5_FST_WID                             ( 2)
+  #define GODLAT_CR_G_ODLAT_FST_S5_FST_MSK                             (0x00000C00)
+  #define GODLAT_CR_G_ODLAT_FST_S5_FST_MAX                             (0x00000003)
+  #define GODLAT_CR_G_ODLAT_FST_S6_FST_OFF                             (12)
+  #define GODLAT_CR_G_ODLAT_FST_S6_FST_WID                             ( 2)
+  #define GODLAT_CR_G_ODLAT_FST_S6_FST_MSK                             (0x00003000)
+  #define GODLAT_CR_G_ODLAT_FST_S6_FST_MAX                             (0x00000003)
+  #define GODLAT_CR_G_ODLAT_FST_S7_FST_OFF                             (14)
+  #define GODLAT_CR_G_ODLAT_FST_S7_FST_WID                             ( 2)
+  #define GODLAT_CR_G_ODLAT_FST_S7_FST_MSK                             (0x0000C000)
+  #define GODLAT_CR_G_ODLAT_FST_S7_FST_MAX                             (0x00000003)
+
+#define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B0_REG                      (0x00000534)
+  #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B0_Arm_OFF                  ( 0)
+  #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B0_Arm_WID                  ( 8)
+  #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B0_Arm_MSK                  (0x000000FF)
+  #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B0_Arm_MAX                  (0x000000FF)
+  #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B0_MBP_Arm_OFF              ( 8)
+  #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B0_MBP_Arm_WID              ( 1)
+  #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B0_MBP_Arm_MSK              (0x00000100)
+  #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B0_MBP_Arm_MAX              (0x00000001)
+  #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B0_TO_Arm_OFF               ( 9)
+  #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B0_TO_Arm_WID               ( 4)
+  #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B0_TO_Arm_MSK               (0x00001E00)
+  #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B0_TO_Arm_MAX               (0x0000000F)
+  #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B0_Mask_OFF                 (16)
+  #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B0_Mask_WID                 ( 8)
+  #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B0_Mask_MSK                 (0x00FF0000)
+  #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B0_Mask_MAX                 (0x000000FF)
+  #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B0_MBP_Mask_OFF             (24)
+  #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B0_MBP_Mask_WID             ( 1)
+  #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B0_MBP_Mask_MSK             (0x01000000)
+  #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B0_MBP_Mask_MAX             (0x00000001)
+  #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B0_TO_Mask_OFF              (25)
+  #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B0_TO_Mask_WID              ( 4)
+  #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B0_TO_Mask_MSK              (0x1E000000)
+  #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B0_TO_Mask_MAX              (0x0000000F)
+
+#define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B1_REG                      (0x00000538)
+  #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B1_Arm_OFF                  ( 0)
+  #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B1_Arm_WID                  ( 8)
+  #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B1_Arm_MSK                  (0x000000FF)
+  #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B1_Arm_MAX                  (0x000000FF)
+  #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B1_MBP_Arm_OFF              ( 8)
+  #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B1_MBP_Arm_WID              ( 1)
+  #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B1_MBP_Arm_MSK              (0x00000100)
+  #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B1_MBP_Arm_MAX              (0x00000001)
+  #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B1_TO_Arm_OFF               ( 9)
+  #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B1_TO_Arm_WID               ( 4)
+  #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B1_TO_Arm_MSK               (0x00001E00)
+  #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B1_TO_Arm_MAX               (0x0000000F)
+  #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B1_Mask_OFF                 (16)
+  #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B1_Mask_WID                 ( 8)
+  #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B1_Mask_MSK                 (0x00FF0000)
+  #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B1_Mask_MAX                 (0x000000FF)
+  #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B1_MBP_Mask_OFF             (24)
+  #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B1_MBP_Mask_WID             ( 1)
+  #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B1_MBP_Mask_MSK             (0x01000000)
+  #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B1_MBP_Mask_MAX             (0x00000001)
+  #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B1_TO_Mask_OFF              (25)
+  #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B1_TO_Mask_WID              ( 4)
+  #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B1_TO_Mask_MSK              (0x1E000000)
+  #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B1_TO_Mask_MAX              (0x0000000F)
+
+#define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B2_REG                      (0x0000053C)
+  #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B2_Arm_OFF                  ( 0)
+  #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B2_Arm_WID                  ( 8)
+  #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B2_Arm_MSK                  (0x000000FF)
+  #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B2_Arm_MAX                  (0x000000FF)
+  #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B2_MBP_Arm_OFF              ( 8)
+  #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B2_MBP_Arm_WID              ( 1)
+  #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B2_MBP_Arm_MSK              (0x00000100)
+  #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B2_MBP_Arm_MAX              (0x00000001)
+  #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B2_TO_Arm_OFF               ( 9)
+  #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B2_TO_Arm_WID               ( 4)
+  #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B2_TO_Arm_MSK               (0x00001E00)
+  #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B2_TO_Arm_MAX               (0x0000000F)
+  #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B2_Mask_OFF                 (16)
+  #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B2_Mask_WID                 ( 8)
+  #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B2_Mask_MSK                 (0x00FF0000)
+  #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B2_Mask_MAX                 (0x000000FF)
+  #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B2_MBP_Mask_OFF             (24)
+  #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B2_MBP_Mask_WID             ( 1)
+  #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B2_MBP_Mask_MSK             (0x01000000)
+  #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B2_MBP_Mask_MAX             (0x00000001)
+  #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B2_TO_Mask_OFF              (25)
+  #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B2_TO_Mask_WID              ( 4)
+  #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B2_TO_Mask_MSK              (0x1E000000)
+  #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B2_TO_Mask_MAX              (0x0000000F)
+
+#define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B3_REG                      (0x00000540)
+  #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B3_Arm_OFF                  ( 0)
+  #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B3_Arm_WID                  ( 8)
+  #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B3_Arm_MSK                  (0x000000FF)
+  #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B3_Arm_MAX                  (0x000000FF)
+  #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B3_MBP_Arm_OFF              ( 8)
+  #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B3_MBP_Arm_WID              ( 1)
+  #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B3_MBP_Arm_MSK              (0x00000100)
+  #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B3_MBP_Arm_MAX              (0x00000001)
+  #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B3_TO_Arm_OFF               ( 9)
+  #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B3_TO_Arm_WID               ( 4)
+  #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B3_TO_Arm_MSK               (0x00001E00)
+  #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B3_TO_Arm_MAX               (0x0000000F)
+  #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B3_Mask_OFF                 (16)
+  #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B3_Mask_WID                 ( 8)
+  #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B3_Mask_MSK                 (0x00FF0000)
+  #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B3_Mask_MAX                 (0x000000FF)
+  #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B3_MBP_Mask_OFF             (24)
+  #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B3_MBP_Mask_WID             ( 1)
+  #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B3_MBP_Mask_MSK             (0x01000000)
+  #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B3_MBP_Mask_MAX             (0x00000001)
+  #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B3_TO_Mask_OFF              (25)
+  #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B3_TO_Mask_WID              ( 4)
+  #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B3_TO_Mask_MSK              (0x1E000000)
+  #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B3_TO_Mask_MAX              (0x0000000F)
+
+#define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B4_REG                      (0x00000544)
+  #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B4_Arm_OFF                  ( 0)
+  #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B4_Arm_WID                  ( 8)
+  #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B4_Arm_MSK                  (0x000000FF)
+  #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B4_Arm_MAX                  (0x000000FF)
+  #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B4_MBP_Arm_OFF              ( 8)
+  #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B4_MBP_Arm_WID              ( 1)
+  #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B4_MBP_Arm_MSK              (0x00000100)
+  #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B4_MBP_Arm_MAX              (0x00000001)
+  #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B4_TO_Arm_OFF               ( 9)
+  #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B4_TO_Arm_WID               ( 4)
+  #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B4_TO_Arm_MSK               (0x00001E00)
+  #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B4_TO_Arm_MAX               (0x0000000F)
+  #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B4_Mask_OFF                 (16)
+  #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B4_Mask_WID                 ( 8)
+  #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B4_Mask_MSK                 (0x00FF0000)
+  #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B4_Mask_MAX                 (0x000000FF)
+  #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B4_MBP_Mask_OFF             (24)
+  #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B4_MBP_Mask_WID             ( 1)
+  #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B4_MBP_Mask_MSK             (0x01000000)
+  #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B4_MBP_Mask_MAX             (0x00000001)
+  #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B4_TO_Mask_OFF              (25)
+  #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B4_TO_Mask_WID              ( 4)
+  #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B4_TO_Mask_MSK              (0x1E000000)
+  #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B4_TO_Mask_MAX              (0x0000000F)
+
+#define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B5_REG                      (0x00000548)
+  #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B5_Arm_OFF                  ( 0)
+  #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B5_Arm_WID                  ( 8)
+  #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B5_Arm_MSK                  (0x000000FF)
+  #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B5_Arm_MAX                  (0x000000FF)
+  #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B5_MBP_Arm_OFF              ( 8)
+  #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B5_MBP_Arm_WID              ( 1)
+  #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B5_MBP_Arm_MSK              (0x00000100)
+  #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B5_MBP_Arm_MAX              (0x00000001)
+  #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B5_TO_Arm_OFF               ( 9)
+  #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B5_TO_Arm_WID               ( 4)
+  #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B5_TO_Arm_MSK               (0x00001E00)
+  #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B5_TO_Arm_MAX               (0x0000000F)
+  #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B5_Mask_OFF                 (16)
+  #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B5_Mask_WID                 ( 8)
+  #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B5_Mask_MSK                 (0x00FF0000)
+  #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B5_Mask_MAX                 (0x000000FF)
+  #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B5_MBP_Mask_OFF             (24)
+  #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B5_MBP_Mask_WID             ( 1)
+  #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B5_MBP_Mask_MSK             (0x01000000)
+  #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B5_MBP_Mask_MAX             (0x00000001)
+  #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B5_TO_Mask_OFF              (25)
+  #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B5_TO_Mask_WID              ( 4)
+  #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B5_TO_Mask_MSK              (0x1E000000)
+  #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B5_TO_Mask_MAX              (0x0000000F)
+
+#define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B0_REG           (0x00000550)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B0_Arm_OFF       ( 0)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B0_Arm_WID       ( 8)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B0_Arm_MSK       (0x000000FF)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B0_Arm_MAX       (0x000000FF)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B0_MBP_Arm_OFF   ( 8)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B0_MBP_Arm_WID   ( 1)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B0_MBP_Arm_MSK   (0x00000100)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B0_MBP_Arm_MAX   (0x00000001)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B0_TO_Arm_OFF    ( 9)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B0_TO_Arm_WID    ( 4)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B0_TO_Arm_MSK    (0x00001E00)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B0_TO_Arm_MAX    (0x0000000F)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B0_Stop_OFF      (13)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B0_Stop_WID      ( 1)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B0_Stop_MSK      (0x00002000)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B0_Stop_MAX      (0x00000001)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B0_Mask_OFF      (16)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B0_Mask_WID      ( 8)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B0_Mask_MSK      (0x00FF0000)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B0_Mask_MAX      (0x000000FF)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B0_MBP_Mask_OFF  (24)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B0_MBP_Mask_WID  ( 1)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B0_MBP_Mask_MSK  (0x01000000)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B0_MBP_Mask_MAX  (0x00000001)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B0_TO_Mask_OFF   (25)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B0_TO_Mask_WID   ( 4)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B0_TO_Mask_MSK   (0x1E000000)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B0_TO_Mask_MAX   (0x0000000F)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B0_Col_Rst_OFF   (29)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B0_Col_Rst_WID   ( 1)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B0_Col_Rst_MSK   (0x20000000)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B0_Col_Rst_MAX   (0x00000001)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B0_Trigger_OFF   (30)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B0_Trigger_WID   ( 1)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B0_Trigger_MSK   (0x40000000)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B0_Trigger_MAX   (0x00000001)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B0_Start_OFF     (31)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B0_Start_WID     ( 1)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B0_Start_MSK     (0x80000000)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B0_Start_MAX     (0x00000001)
+
+#define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B0_REG                  (0x00000554)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B0_Arm_OFF              ( 0)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B0_Arm_WID              ( 8)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B0_Arm_MSK              (0x000000FF)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B0_Arm_MAX              (0x000000FF)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B0_MBP_Arm_OFF          ( 8)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B0_MBP_Arm_WID          ( 1)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B0_MBP_Arm_MSK          (0x00000100)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B0_MBP_Arm_MAX          (0x00000001)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B0_TO_Arm_OFF           ( 9)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B0_TO_Arm_WID           ( 4)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B0_TO_Arm_MSK           (0x00001E00)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B0_TO_Arm_MAX           (0x0000000F)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B0_Mask_OFF             (16)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B0_Mask_WID             ( 8)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B0_Mask_MSK             (0x00FF0000)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B0_Mask_MAX             (0x000000FF)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B0_MBP_Mask_OFF         (24)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B0_MBP_Mask_WID         ( 1)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B0_MBP_Mask_MSK         (0x01000000)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B0_MBP_Mask_MAX         (0x00000001)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B0_TO_Mask_OFF          (25)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B0_TO_Mask_WID          ( 4)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B0_TO_Mask_MSK          (0x1E000000)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B0_TO_Mask_MAX          (0x0000000F)
+
+#define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B1_REG                  (0x00000558)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B1_Arm_OFF              ( 0)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B1_Arm_WID              ( 8)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B1_Arm_MSK              (0x000000FF)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B1_Arm_MAX              (0x000000FF)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B1_MBP_Arm_OFF          ( 8)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B1_MBP_Arm_WID          ( 1)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B1_MBP_Arm_MSK          (0x00000100)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B1_MBP_Arm_MAX          (0x00000001)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B1_TO_Arm_OFF           ( 9)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B1_TO_Arm_WID           ( 4)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B1_TO_Arm_MSK           (0x00001E00)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B1_TO_Arm_MAX           (0x0000000F)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B1_Mask_OFF             (16)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B1_Mask_WID             ( 8)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B1_Mask_MSK             (0x00FF0000)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B1_Mask_MAX             (0x000000FF)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B1_MBP_Mask_OFF         (24)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B1_MBP_Mask_WID         ( 1)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B1_MBP_Mask_MSK         (0x01000000)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B1_MBP_Mask_MAX         (0x00000001)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B1_TO_Mask_OFF          (25)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B1_TO_Mask_WID          ( 4)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B1_TO_Mask_MSK          (0x1E000000)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B1_TO_Mask_MAX          (0x0000000F)
+
+#define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B2_REG                  (0x0000055C)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B2_Arm_OFF              ( 0)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B2_Arm_WID              ( 8)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B2_Arm_MSK              (0x000000FF)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B2_Arm_MAX              (0x000000FF)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B2_MBP_Arm_OFF          ( 8)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B2_MBP_Arm_WID          ( 1)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B2_MBP_Arm_MSK          (0x00000100)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B2_MBP_Arm_MAX          (0x00000001)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B2_TO_Arm_OFF           ( 9)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B2_TO_Arm_WID           ( 4)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B2_TO_Arm_MSK           (0x00001E00)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B2_TO_Arm_MAX           (0x0000000F)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B2_Mask_OFF             (16)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B2_Mask_WID             ( 8)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B2_Mask_MSK             (0x00FF0000)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B2_Mask_MAX             (0x000000FF)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B2_MBP_Mask_OFF         (24)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B2_MBP_Mask_WID         ( 1)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B2_MBP_Mask_MSK         (0x01000000)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B2_MBP_Mask_MAX         (0x00000001)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B2_TO_Mask_OFF          (25)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B2_TO_Mask_WID          ( 4)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B2_TO_Mask_MSK          (0x1E000000)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B2_TO_Mask_MAX          (0x0000000F)
+
+#define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B3_REG                  (0x00000560)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B3_Arm_OFF              ( 0)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B3_Arm_WID              ( 8)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B3_Arm_MSK              (0x000000FF)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B3_Arm_MAX              (0x000000FF)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B3_MBP_Arm_OFF          ( 8)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B3_MBP_Arm_WID          ( 1)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B3_MBP_Arm_MSK          (0x00000100)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B3_MBP_Arm_MAX          (0x00000001)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B3_TO_Arm_OFF           ( 9)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B3_TO_Arm_WID           ( 4)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B3_TO_Arm_MSK           (0x00001E00)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B3_TO_Arm_MAX           (0x0000000F)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B3_Mask_OFF             (16)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B3_Mask_WID             ( 8)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B3_Mask_MSK             (0x00FF0000)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B3_Mask_MAX             (0x000000FF)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B3_MBP_Mask_OFF         (24)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B3_MBP_Mask_WID         ( 1)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B3_MBP_Mask_MSK         (0x01000000)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B3_MBP_Mask_MAX         (0x00000001)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B3_TO_Mask_OFF          (25)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B3_TO_Mask_WID          ( 4)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B3_TO_Mask_MSK          (0x1E000000)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B3_TO_Mask_MAX          (0x0000000F)
+
+#define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B4_REG                  (0x00000564)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B4_Arm_OFF              ( 0)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B4_Arm_WID              ( 8)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B4_Arm_MSK              (0x000000FF)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B4_Arm_MAX              (0x000000FF)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B4_MBP_Arm_OFF          ( 8)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B4_MBP_Arm_WID          ( 1)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B4_MBP_Arm_MSK          (0x00000100)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B4_MBP_Arm_MAX          (0x00000001)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B4_TO_Arm_OFF           ( 9)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B4_TO_Arm_WID           ( 4)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B4_TO_Arm_MSK           (0x00001E00)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B4_TO_Arm_MAX           (0x0000000F)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B4_Mask_OFF             (16)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B4_Mask_WID             ( 8)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B4_Mask_MSK             (0x00FF0000)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B4_Mask_MAX             (0x000000FF)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B4_MBP_Mask_OFF         (24)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B4_MBP_Mask_WID         ( 1)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B4_MBP_Mask_MSK         (0x01000000)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B4_MBP_Mask_MAX         (0x00000001)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B4_TO_Mask_OFF          (25)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B4_TO_Mask_WID          ( 4)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B4_TO_Mask_MSK          (0x1E000000)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B4_TO_Mask_MAX          (0x0000000F)
+
+#define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B5_REG                  (0x00000568)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B5_Arm_OFF              ( 0)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B5_Arm_WID              ( 8)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B5_Arm_MSK              (0x000000FF)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B5_Arm_MAX              (0x000000FF)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B5_MBP_Arm_OFF          ( 8)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B5_MBP_Arm_WID          ( 1)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B5_MBP_Arm_MSK          (0x00000100)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B5_MBP_Arm_MAX          (0x00000001)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B5_TO_Arm_OFF           ( 9)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B5_TO_Arm_WID           ( 4)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B5_TO_Arm_MSK           (0x00001E00)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B5_TO_Arm_MAX           (0x0000000F)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B5_Mask_OFF             (16)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B5_Mask_WID             ( 8)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B5_Mask_MSK             (0x00FF0000)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B5_Mask_MAX             (0x000000FF)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B5_MBP_Mask_OFF         (24)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B5_MBP_Mask_WID         ( 1)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B5_MBP_Mask_MSK         (0x01000000)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B5_MBP_Mask_MAX         (0x00000001)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B5_TO_Mask_OFF          (25)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B5_TO_Mask_WID          ( 4)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B5_TO_Mask_MSK          (0x1E000000)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B5_TO_Mask_MAX          (0x0000000F)
+
+#define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B1_REG           (0x00000570)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B1_Arm_OFF       ( 0)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B1_Arm_WID       ( 8)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B1_Arm_MSK       (0x000000FF)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B1_Arm_MAX       (0x000000FF)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B1_MBP_Arm_OFF   ( 8)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B1_MBP_Arm_WID   ( 1)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B1_MBP_Arm_MSK   (0x00000100)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B1_MBP_Arm_MAX   (0x00000001)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B1_TO_Arm_OFF    ( 9)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B1_TO_Arm_WID    ( 4)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B1_TO_Arm_MSK    (0x00001E00)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B1_TO_Arm_MAX    (0x0000000F)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B1_Stop_OFF      (13)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B1_Stop_WID      ( 1)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B1_Stop_MSK      (0x00002000)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B1_Stop_MAX      (0x00000001)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B1_Mask_OFF      (16)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B1_Mask_WID      ( 8)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B1_Mask_MSK      (0x00FF0000)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B1_Mask_MAX      (0x000000FF)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B1_MBP_Mask_OFF  (24)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B1_MBP_Mask_WID  ( 1)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B1_MBP_Mask_MSK  (0x01000000)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B1_MBP_Mask_MAX  (0x00000001)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B1_TO_Mask_OFF   (25)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B1_TO_Mask_WID   ( 4)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B1_TO_Mask_MSK   (0x1E000000)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B1_TO_Mask_MAX   (0x0000000F)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B1_Col_Rst_OFF   (29)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B1_Col_Rst_WID   ( 1)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B1_Col_Rst_MSK   (0x20000000)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B1_Col_Rst_MAX   (0x00000001)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B1_Trigger_OFF   (30)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B1_Trigger_WID   ( 1)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B1_Trigger_MSK   (0x40000000)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B1_Trigger_MAX   (0x00000001)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B1_Start_OFF     (31)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B1_Start_WID     ( 1)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B1_Start_MSK     (0x80000000)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B1_Start_MAX     (0x00000001)
+
+#define GODLAT_CR_G_ODLAT_TR_IF_MODE_B0_B1_REG                       (0x00000574)
+  #define GODLAT_CR_G_ODLAT_TR_IF_MODE_B0_B1_B0_Set_OFF                ( 0)
+  #define GODLAT_CR_G_ODLAT_TR_IF_MODE_B0_B1_B0_Set_WID                ( 6)
+  #define GODLAT_CR_G_ODLAT_TR_IF_MODE_B0_B1_B0_Set_MSK                (0x0000003F)
+  #define GODLAT_CR_G_ODLAT_TR_IF_MODE_B0_B1_B0_Set_MAX                (0x0000003F)
+  #define GODLAT_CR_G_ODLAT_TR_IF_MODE_B0_B1_B0_Rst_OFF                ( 6)
+  #define GODLAT_CR_G_ODLAT_TR_IF_MODE_B0_B1_B0_Rst_WID                ( 6)
+  #define GODLAT_CR_G_ODLAT_TR_IF_MODE_B0_B1_B0_Rst_MSK                (0x00000FC0)
+  #define GODLAT_CR_G_ODLAT_TR_IF_MODE_B0_B1_B0_Rst_MAX                (0x0000003F)
+  #define GODLAT_CR_G_ODLAT_TR_IF_MODE_B0_B1_B1_Set_OFF                (12)
+  #define GODLAT_CR_G_ODLAT_TR_IF_MODE_B0_B1_B1_Set_WID                ( 6)
+  #define GODLAT_CR_G_ODLAT_TR_IF_MODE_B0_B1_B1_Set_MSK                (0x0003F000)
+  #define GODLAT_CR_G_ODLAT_TR_IF_MODE_B0_B1_B1_Set_MAX                (0x0000003F)
+  #define GODLAT_CR_G_ODLAT_TR_IF_MODE_B0_B1_B1_Rst_OFF                (18)
+  #define GODLAT_CR_G_ODLAT_TR_IF_MODE_B0_B1_B1_Rst_WID                ( 6)
+  #define GODLAT_CR_G_ODLAT_TR_IF_MODE_B0_B1_B1_Rst_MSK                (0x00FC0000)
+  #define GODLAT_CR_G_ODLAT_TR_IF_MODE_B0_B1_B1_Rst_MAX                (0x0000003F)
+
+#define GODLAT_CR_G_ODLAT_TR_IF_MODE_B2_B3_REG                       (0x00000578)
+  #define GODLAT_CR_G_ODLAT_TR_IF_MODE_B2_B3_B2_Set_OFF                ( 0)
+  #define GODLAT_CR_G_ODLAT_TR_IF_MODE_B2_B3_B2_Set_WID                ( 6)
+  #define GODLAT_CR_G_ODLAT_TR_IF_MODE_B2_B3_B2_Set_MSK                (0x0000003F)
+  #define GODLAT_CR_G_ODLAT_TR_IF_MODE_B2_B3_B2_Set_MAX                (0x0000003F)
+  #define GODLAT_CR_G_ODLAT_TR_IF_MODE_B2_B3_B2_Rst_OFF                ( 6)
+  #define GODLAT_CR_G_ODLAT_TR_IF_MODE_B2_B3_B2_Rst_WID                ( 6)
+  #define GODLAT_CR_G_ODLAT_TR_IF_MODE_B2_B3_B2_Rst_MSK                (0x00000FC0)
+  #define GODLAT_CR_G_ODLAT_TR_IF_MODE_B2_B3_B2_Rst_MAX                (0x0000003F)
+  #define GODLAT_CR_G_ODLAT_TR_IF_MODE_B2_B3_B3_Set_OFF                (12)
+  #define GODLAT_CR_G_ODLAT_TR_IF_MODE_B2_B3_B3_Set_WID                ( 6)
+  #define GODLAT_CR_G_ODLAT_TR_IF_MODE_B2_B3_B3_Set_MSK                (0x0003F000)
+  #define GODLAT_CR_G_ODLAT_TR_IF_MODE_B2_B3_B3_Set_MAX                (0x0000003F)
+  #define GODLAT_CR_G_ODLAT_TR_IF_MODE_B2_B3_B3_Rst_OFF                (18)
+  #define GODLAT_CR_G_ODLAT_TR_IF_MODE_B2_B3_B3_Rst_WID                ( 6)
+  #define GODLAT_CR_G_ODLAT_TR_IF_MODE_B2_B3_B3_Rst_MSK                (0x00FC0000)
+  #define GODLAT_CR_G_ODLAT_TR_IF_MODE_B2_B3_B3_Rst_MAX                (0x0000003F)
+
+#define GODLAT_CR_G_ODLAT_TR_IF_MODE_B4_B5_REG                       (0x0000057C)
+  #define GODLAT_CR_G_ODLAT_TR_IF_MODE_B4_B5_B4_Set_OFF                ( 0)
+  #define GODLAT_CR_G_ODLAT_TR_IF_MODE_B4_B5_B4_Set_WID                ( 6)
+  #define GODLAT_CR_G_ODLAT_TR_IF_MODE_B4_B5_B4_Set_MSK                (0x0000003F)
+  #define GODLAT_CR_G_ODLAT_TR_IF_MODE_B4_B5_B4_Set_MAX                (0x0000003F)
+  #define GODLAT_CR_G_ODLAT_TR_IF_MODE_B4_B5_B4_Rst_OFF                ( 6)
+  #define GODLAT_CR_G_ODLAT_TR_IF_MODE_B4_B5_B4_Rst_WID                ( 6)
+  #define GODLAT_CR_G_ODLAT_TR_IF_MODE_B4_B5_B4_Rst_MSK                (0x00000FC0)
+  #define GODLAT_CR_G_ODLAT_TR_IF_MODE_B4_B5_B4_Rst_MAX                (0x0000003F)
+  #define GODLAT_CR_G_ODLAT_TR_IF_MODE_B4_B5_B5_Set_OFF                (12)
+  #define GODLAT_CR_G_ODLAT_TR_IF_MODE_B4_B5_B5_Set_WID                ( 6)
+  #define GODLAT_CR_G_ODLAT_TR_IF_MODE_B4_B5_B5_Set_MSK                (0x0003F000)
+  #define GODLAT_CR_G_ODLAT_TR_IF_MODE_B4_B5_B5_Set_MAX                (0x0000003F)
+  #define GODLAT_CR_G_ODLAT_TR_IF_MODE_B4_B5_B5_Rst_OFF                (18)
+  #define GODLAT_CR_G_ODLAT_TR_IF_MODE_B4_B5_B5_Rst_WID                ( 6)
+  #define GODLAT_CR_G_ODLAT_TR_IF_MODE_B4_B5_B5_Rst_MSK                (0x00FC0000)
+  #define GODLAT_CR_G_ODLAT_TR_IF_MODE_B4_B5_B5_Rst_MAX                (0x0000003F)
+
+#define GODLAT_CR_G_ODLAT_TR_IF_MODE_B6_B7_REG                       (0x00000580)
+  #define GODLAT_CR_G_ODLAT_TR_IF_MODE_B6_B7_ElseIf_ElseIf_B0_Set_OFF  ( 0)
+  #define GODLAT_CR_G_ODLAT_TR_IF_MODE_B6_B7_ElseIf_ElseIf_B0_Set_WID  ( 6)
+  #define GODLAT_CR_G_ODLAT_TR_IF_MODE_B6_B7_ElseIf_ElseIf_B0_Set_MSK  (0x0000003F)
+  #define GODLAT_CR_G_ODLAT_TR_IF_MODE_B6_B7_ElseIf_ElseIf_B0_Set_MAX  (0x0000003F)
+  #define GODLAT_CR_G_ODLAT_TR_IF_MODE_B6_B7_ElseIf_ElseIf_B0_Rst_OFF  ( 6)
+  #define GODLAT_CR_G_ODLAT_TR_IF_MODE_B6_B7_ElseIf_ElseIf_B0_Rst_WID  ( 6)
+  #define GODLAT_CR_G_ODLAT_TR_IF_MODE_B6_B7_ElseIf_ElseIf_B0_Rst_MSK  (0x00000FC0)
+  #define GODLAT_CR_G_ODLAT_TR_IF_MODE_B6_B7_ElseIf_ElseIf_B0_Rst_MAX  (0x0000003F)
+
+#define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_B0_B1_REG                   (0x00000584)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_B0_B1_B0_Set_OFF            ( 0)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_B0_B1_B0_Set_WID            ( 6)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_B0_B1_B0_Set_MSK            (0x0000003F)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_B0_B1_B0_Set_MAX            (0x0000003F)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_B0_B1_B0_Rst_OFF            ( 6)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_B0_B1_B0_Rst_WID            ( 6)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_B0_B1_B0_Rst_MSK            (0x00000FC0)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_B0_B1_B0_Rst_MAX            (0x0000003F)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_B0_B1_B1_Set_OFF            (12)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_B0_B1_B1_Set_WID            ( 6)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_B0_B1_B1_Set_MSK            (0x0003F000)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_B0_B1_B1_Set_MAX            (0x0000003F)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_B0_B1_B1_Rst_OFF            (18)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_B0_B1_B1_Rst_WID            ( 6)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_B0_B1_B1_Rst_MSK            (0x00FC0000)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_B0_B1_B1_Rst_MAX            (0x0000003F)
+
+#define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_B2_B3_REG                   (0x00000588)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_B2_B3_B2_Set_OFF            ( 0)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_B2_B3_B2_Set_WID            ( 6)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_B2_B3_B2_Set_MSK            (0x0000003F)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_B2_B3_B2_Set_MAX            (0x0000003F)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_B2_B3_B2_Rst_OFF            ( 6)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_B2_B3_B2_Rst_WID            ( 6)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_B2_B3_B2_Rst_MSK            (0x00000FC0)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_B2_B3_B2_Rst_MAX            (0x0000003F)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_B2_B3_B3_Set_OFF            (12)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_B2_B3_B3_Set_WID            ( 6)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_B2_B3_B3_Set_MSK            (0x0003F000)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_B2_B3_B3_Set_MAX            (0x0000003F)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_B2_B3_B3_Rst_OFF            (18)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_B2_B3_B3_Rst_WID            ( 6)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_B2_B3_B3_Rst_MSK            (0x00FC0000)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_B2_B3_B3_Rst_MAX            (0x0000003F)
+
+#define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_B4_B5_REG                   (0x0000058C)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_B4_B5_B4_Set_OFF            ( 0)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_B4_B5_B4_Set_WID            ( 6)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_B4_B5_B4_Set_MSK            (0x0000003F)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_B4_B5_B4_Set_MAX            (0x0000003F)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_B4_B5_B4_Rst_OFF            ( 6)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_B4_B5_B4_Rst_WID            ( 6)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_B4_B5_B4_Rst_MSK            (0x00000FC0)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_B4_B5_B4_Rst_MAX            (0x0000003F)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_B4_B5_B5_Set_OFF            (12)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_B4_B5_B5_Set_WID            ( 6)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_B4_B5_B5_Set_MSK            (0x0003F000)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_B4_B5_B5_Set_MAX            (0x0000003F)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_B4_B5_B5_Rst_OFF            (18)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_B4_B5_B5_Rst_WID            ( 6)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_B4_B5_B5_Rst_MSK            (0x00FC0000)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_B4_B5_B5_Rst_MAX            (0x0000003F)
+
+#define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_B6_B7_REG                   (0x00000590)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_B6_B7_ElseIf_ElseIf_B1_Set_OFF ( 0)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_B6_B7_ElseIf_ElseIf_B1_Set_WID ( 6)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_B6_B7_ElseIf_ElseIf_B1_Set_MSK (0x0000003F)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_B6_B7_ElseIf_ElseIf_B1_Set_MAX (0x0000003F)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_B6_B7_ElseIf_ElseIf_B1_Rst_OFF ( 6)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_B6_B7_ElseIf_ElseIf_B1_Rst_WID ( 6)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_B6_B7_ElseIf_ElseIf_B1_Rst_MSK (0x00000FC0)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_B6_B7_ElseIf_ElseIf_B1_Rst_MAX (0x0000003F)
+
+#define GODLAT_CR_G_ODLAT_INIT_BUBBLES_REG                           (0x00000594)
+  #define GODLAT_CR_G_ODLAT_INIT_BUBBLES_Init_Bits_OFF                 ( 0)
+  #define GODLAT_CR_G_ODLAT_INIT_BUBBLES_Init_Bits_WID                 ( 6)
+  #define GODLAT_CR_G_ODLAT_INIT_BUBBLES_Init_Bits_MSK                 (0x0000003F)
+  #define GODLAT_CR_G_ODLAT_INIT_BUBBLES_Init_Bits_MAX                 (0x0000003F)
+
+#define GODLAT_CR_G_ODLAT_TR_IF_MODE_MISC_REG                        (0x00000598)
+  #define GODLAT_CR_G_ODLAT_TR_IF_MODE_MISC_ColRst_OFF                 ( 0)
+  #define GODLAT_CR_G_ODLAT_TR_IF_MODE_MISC_ColRst_WID                 ( 6)
+  #define GODLAT_CR_G_ODLAT_TR_IF_MODE_MISC_ColRst_MSK                 (0x0000003F)
+  #define GODLAT_CR_G_ODLAT_TR_IF_MODE_MISC_ColRst_MAX                 (0x0000003F)
+  #define GODLAT_CR_G_ODLAT_TR_IF_MODE_MISC_Start_OFF                  ( 6)
+  #define GODLAT_CR_G_ODLAT_TR_IF_MODE_MISC_Start_WID                  ( 6)
+  #define GODLAT_CR_G_ODLAT_TR_IF_MODE_MISC_Start_MSK                  (0x00000FC0)
+  #define GODLAT_CR_G_ODLAT_TR_IF_MODE_MISC_Start_MAX                  (0x0000003F)
+  #define GODLAT_CR_G_ODLAT_TR_IF_MODE_MISC_Trigger_OFF                (12)
+  #define GODLAT_CR_G_ODLAT_TR_IF_MODE_MISC_Trigger_WID                ( 6)
+  #define GODLAT_CR_G_ODLAT_TR_IF_MODE_MISC_Trigger_MSK                (0x0003F000)
+  #define GODLAT_CR_G_ODLAT_TR_IF_MODE_MISC_Trigger_MAX                (0x0000003F)
+  #define GODLAT_CR_G_ODLAT_TR_IF_MODE_MISC_Stop_OFF                   (18)
+  #define GODLAT_CR_G_ODLAT_TR_IF_MODE_MISC_Stop_WID                   ( 6)
+  #define GODLAT_CR_G_ODLAT_TR_IF_MODE_MISC_Stop_MSK                   (0x00FC0000)
+  #define GODLAT_CR_G_ODLAT_TR_IF_MODE_MISC_Stop_MAX                   (0x0000003F)
+
+#define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_MISC_REG                    (0x0000059C)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_MISC_ColRst_OFF             ( 0)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_MISC_ColRst_WID             ( 6)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_MISC_ColRst_MSK             (0x0000003F)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_MISC_ColRst_MAX             (0x0000003F)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_MISC_Start_OFF              ( 6)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_MISC_Start_WID              ( 6)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_MISC_Start_MSK              (0x00000FC0)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_MISC_Start_MAX              (0x0000003F)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_MISC_Trigger_OFF            (12)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_MISC_Trigger_WID            ( 6)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_MISC_Trigger_MSK            (0x0003F000)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_MISC_Trigger_MAX            (0x0000003F)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_MISC_Stop_OFF               (18)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_MISC_Stop_WID               ( 6)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_MISC_Stop_MSK               (0x00FC0000)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_MISC_Stop_MAX               (0x0000003F)
+
+#define GODLAT_CR_G_ODLAT_TR_IF_MODE_TMREN_REG                       (0x00000600)
+  #define GODLAT_CR_G_ODLAT_TR_IF_MODE_TMREN_B0_EN_OFF                 ( 0)
+  #define GODLAT_CR_G_ODLAT_TR_IF_MODE_TMREN_B0_EN_WID                 ( 4)
+  #define GODLAT_CR_G_ODLAT_TR_IF_MODE_TMREN_B0_EN_MSK                 (0x0000000F)
+  #define GODLAT_CR_G_ODLAT_TR_IF_MODE_TMREN_B0_EN_MAX                 (0x0000000F)
+  #define GODLAT_CR_G_ODLAT_TR_IF_MODE_TMREN_B1_EN_OFF                 ( 4)
+  #define GODLAT_CR_G_ODLAT_TR_IF_MODE_TMREN_B1_EN_WID                 ( 4)
+  #define GODLAT_CR_G_ODLAT_TR_IF_MODE_TMREN_B1_EN_MSK                 (0x000000F0)
+  #define GODLAT_CR_G_ODLAT_TR_IF_MODE_TMREN_B1_EN_MAX                 (0x0000000F)
+  #define GODLAT_CR_G_ODLAT_TR_IF_MODE_TMREN_B2_EN_OFF                 ( 8)
+  #define GODLAT_CR_G_ODLAT_TR_IF_MODE_TMREN_B2_EN_WID                 ( 4)
+  #define GODLAT_CR_G_ODLAT_TR_IF_MODE_TMREN_B2_EN_MSK                 (0x00000F00)
+  #define GODLAT_CR_G_ODLAT_TR_IF_MODE_TMREN_B2_EN_MAX                 (0x0000000F)
+  #define GODLAT_CR_G_ODLAT_TR_IF_MODE_TMREN_B3_EN_OFF                 (12)
+  #define GODLAT_CR_G_ODLAT_TR_IF_MODE_TMREN_B3_EN_WID                 ( 4)
+  #define GODLAT_CR_G_ODLAT_TR_IF_MODE_TMREN_B3_EN_MSK                 (0x0000F000)
+  #define GODLAT_CR_G_ODLAT_TR_IF_MODE_TMREN_B3_EN_MAX                 (0x0000000F)
+  #define GODLAT_CR_G_ODLAT_TR_IF_MODE_TMREN_B4_EN_OFF                 (16)
+  #define GODLAT_CR_G_ODLAT_TR_IF_MODE_TMREN_B4_EN_WID                 ( 4)
+  #define GODLAT_CR_G_ODLAT_TR_IF_MODE_TMREN_B4_EN_MSK                 (0x000F0000)
+  #define GODLAT_CR_G_ODLAT_TR_IF_MODE_TMREN_B4_EN_MAX                 (0x0000000F)
+  #define GODLAT_CR_G_ODLAT_TR_IF_MODE_TMREN_B5_EN_OFF                 (20)
+  #define GODLAT_CR_G_ODLAT_TR_IF_MODE_TMREN_B5_EN_WID                 ( 4)
+  #define GODLAT_CR_G_ODLAT_TR_IF_MODE_TMREN_B5_EN_MSK                 (0x00F00000)
+  #define GODLAT_CR_G_ODLAT_TR_IF_MODE_TMREN_B5_EN_MAX                 (0x0000000F)
+  #define GODLAT_CR_G_ODLAT_TR_IF_MODE_TMREN_ELSEIF_ELSEIF_B0_EN_OFF   (24)
+  #define GODLAT_CR_G_ODLAT_TR_IF_MODE_TMREN_ELSEIF_ELSEIF_B0_EN_WID   ( 4)
+  #define GODLAT_CR_G_ODLAT_TR_IF_MODE_TMREN_ELSEIF_ELSEIF_B0_EN_MSK   (0x0F000000)
+  #define GODLAT_CR_G_ODLAT_TR_IF_MODE_TMREN_ELSEIF_ELSEIF_B0_EN_MAX   (0x0000000F)
+
+#define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_TMREN_REG                   (0x00000604)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_TMREN_B0_EN_OFF             ( 0)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_TMREN_B0_EN_WID             ( 4)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_TMREN_B0_EN_MSK             (0x0000000F)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_TMREN_B0_EN_MAX             (0x0000000F)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_TMREN_B1_EN_OFF             ( 4)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_TMREN_B1_EN_WID             ( 4)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_TMREN_B1_EN_MSK             (0x000000F0)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_TMREN_B1_EN_MAX             (0x0000000F)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_TMREN_B2_EN_OFF             ( 8)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_TMREN_B2_EN_WID             ( 4)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_TMREN_B2_EN_MSK             (0x00000F00)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_TMREN_B2_EN_MAX             (0x0000000F)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_TMREN_B3_EN_OFF             (12)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_TMREN_B3_EN_WID             ( 4)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_TMREN_B3_EN_MSK             (0x0000F000)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_TMREN_B3_EN_MAX             (0x0000000F)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_TMREN_B4_EN_OFF             (16)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_TMREN_B4_EN_WID             ( 4)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_TMREN_B4_EN_MSK             (0x000F0000)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_TMREN_B4_EN_MAX             (0x0000000F)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_TMREN_B5_EN_OFF             (20)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_TMREN_B5_EN_WID             ( 4)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_TMREN_B5_EN_MSK             (0x00F00000)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_TMREN_B5_EN_MAX             (0x0000000F)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_TMREN_ELSEIF_ELSEIF_B1_EN_OFF (24)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_TMREN_ELSEIF_ELSEIF_B1_EN_WID ( 4)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_TMREN_ELSEIF_ELSEIF_B1_EN_MSK (0x0F000000)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_TMREN_ELSEIF_ELSEIF_B1_EN_MAX (0x0000000F)
+
+#define GODLAT_CR_G_ODLAT_TIMER_PRELOAD_REG                          (0x00000608)
+  #define GODLAT_CR_G_ODLAT_TIMER_PRELOAD_Timer0_load_OFF              ( 0)
+  #define GODLAT_CR_G_ODLAT_TIMER_PRELOAD_Timer0_load_WID              ( 5)
+  #define GODLAT_CR_G_ODLAT_TIMER_PRELOAD_Timer0_load_MSK              (0x0000001F)
+  #define GODLAT_CR_G_ODLAT_TIMER_PRELOAD_Timer0_load_MAX              (0x0000001F)
+  #define GODLAT_CR_G_ODLAT_TIMER_PRELOAD_Timer0_load_DEF              (0x00000000)
+  #define GODLAT_CR_G_ODLAT_TIMER_PRELOAD_Timer1_load_OFF              ( 5)
+  #define GODLAT_CR_G_ODLAT_TIMER_PRELOAD_Timer1_load_WID              ( 5)
+  #define GODLAT_CR_G_ODLAT_TIMER_PRELOAD_Timer1_load_MSK              (0x000003E0)
+  #define GODLAT_CR_G_ODLAT_TIMER_PRELOAD_Timer1_load_MAX              (0x0000001F)
+  #define GODLAT_CR_G_ODLAT_TIMER_PRELOAD_Timer1_load_DEF              (0x00000000)
+  #define GODLAT_CR_G_ODLAT_TIMER_PRELOAD_Timer2_load_OFF              (10)
+  #define GODLAT_CR_G_ODLAT_TIMER_PRELOAD_Timer2_load_WID              ( 5)
+  #define GODLAT_CR_G_ODLAT_TIMER_PRELOAD_Timer2_load_MSK              (0x00007C00)
+  #define GODLAT_CR_G_ODLAT_TIMER_PRELOAD_Timer2_load_MAX              (0x0000001F)
+  #define GODLAT_CR_G_ODLAT_TIMER_PRELOAD_Timer2_load_DEF              (0x00000000)
+  #define GODLAT_CR_G_ODLAT_TIMER_PRELOAD_Timer3_load_OFF              (15)
+  #define GODLAT_CR_G_ODLAT_TIMER_PRELOAD_Timer3_load_WID              (16)
+  #define GODLAT_CR_G_ODLAT_TIMER_PRELOAD_Timer3_load_MSK              (0x7FFF8000)
+  #define GODLAT_CR_G_ODLAT_TIMER_PRELOAD_Timer3_load_MAX              (0x0000FFFF)
+  #define GODLAT_CR_G_ODLAT_TIMER_PRELOAD_Timer3_load_DEF              (0x00000000)
+
+#define GODLAT_CR_G_ODLAT_MOT_HDR_HIT_REG                            (0x0000060C)
+  #define GODLAT_CR_G_ODLAT_MOT_HDR_HIT_MOT_PKT_OFF                    ( 0)
+  #define GODLAT_CR_G_ODLAT_MOT_HDR_HIT_MOT_PKT_WID                    ( 8)
+  #define GODLAT_CR_G_ODLAT_MOT_HDR_HIT_MOT_PKT_MSK                    (0x000000FF)
+  #define GODLAT_CR_G_ODLAT_MOT_HDR_HIT_MOT_PKT_MAX                    (0x000000FF)
+
+#define GODLAT_CR_G_ODLAT_TR_IF_MODE_TMRRST_REG                      (0x00000610)
+  #define GODLAT_CR_G_ODLAT_TR_IF_MODE_TMRRST_B0_RST_OFF               ( 0)
+  #define GODLAT_CR_G_ODLAT_TR_IF_MODE_TMRRST_B0_RST_WID               ( 4)
+  #define GODLAT_CR_G_ODLAT_TR_IF_MODE_TMRRST_B0_RST_MSK               (0x0000000F)
+  #define GODLAT_CR_G_ODLAT_TR_IF_MODE_TMRRST_B0_RST_MAX               (0x0000000F)
+  #define GODLAT_CR_G_ODLAT_TR_IF_MODE_TMRRST_B1_RST_OFF               ( 4)
+  #define GODLAT_CR_G_ODLAT_TR_IF_MODE_TMRRST_B1_RST_WID               ( 4)
+  #define GODLAT_CR_G_ODLAT_TR_IF_MODE_TMRRST_B1_RST_MSK               (0x000000F0)
+  #define GODLAT_CR_G_ODLAT_TR_IF_MODE_TMRRST_B1_RST_MAX               (0x0000000F)
+  #define GODLAT_CR_G_ODLAT_TR_IF_MODE_TMRRST_B2_RST_OFF               ( 8)
+  #define GODLAT_CR_G_ODLAT_TR_IF_MODE_TMRRST_B2_RST_WID               ( 4)
+  #define GODLAT_CR_G_ODLAT_TR_IF_MODE_TMRRST_B2_RST_MSK               (0x00000F00)
+  #define GODLAT_CR_G_ODLAT_TR_IF_MODE_TMRRST_B2_RST_MAX               (0x0000000F)
+  #define GODLAT_CR_G_ODLAT_TR_IF_MODE_TMRRST_B3_RST_OFF               (12)
+  #define GODLAT_CR_G_ODLAT_TR_IF_MODE_TMRRST_B3_RST_WID               ( 4)
+  #define GODLAT_CR_G_ODLAT_TR_IF_MODE_TMRRST_B3_RST_MSK               (0x0000F000)
+  #define GODLAT_CR_G_ODLAT_TR_IF_MODE_TMRRST_B3_RST_MAX               (0x0000000F)
+  #define GODLAT_CR_G_ODLAT_TR_IF_MODE_TMRRST_B4_RST_OFF               (16)
+  #define GODLAT_CR_G_ODLAT_TR_IF_MODE_TMRRST_B4_RST_WID               ( 4)
+  #define GODLAT_CR_G_ODLAT_TR_IF_MODE_TMRRST_B4_RST_MSK               (0x000F0000)
+  #define GODLAT_CR_G_ODLAT_TR_IF_MODE_TMRRST_B4_RST_MAX               (0x0000000F)
+  #define GODLAT_CR_G_ODLAT_TR_IF_MODE_TMRRST_B5_RST_OFF               (20)
+  #define GODLAT_CR_G_ODLAT_TR_IF_MODE_TMRRST_B5_RST_WID               ( 4)
+  #define GODLAT_CR_G_ODLAT_TR_IF_MODE_TMRRST_B5_RST_MSK               (0x00F00000)
+  #define GODLAT_CR_G_ODLAT_TR_IF_MODE_TMRRST_B5_RST_MAX               (0x0000000F)
+  #define GODLAT_CR_G_ODLAT_TR_IF_MODE_TMRRST_ELSEIF_ELSEIF_B0_RST_OFF (24)
+  #define GODLAT_CR_G_ODLAT_TR_IF_MODE_TMRRST_ELSEIF_ELSEIF_B0_RST_WID ( 4)
+  #define GODLAT_CR_G_ODLAT_TR_IF_MODE_TMRRST_ELSEIF_ELSEIF_B0_RST_MSK (0x0F000000)
+  #define GODLAT_CR_G_ODLAT_TR_IF_MODE_TMRRST_ELSEIF_ELSEIF_B0_RST_MAX (0x0000000F)
+
+#define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_TMRRST_REG                  (0x00000614)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_TMRRST_B0_RST_OFF           ( 0)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_TMRRST_B0_RST_WID           ( 4)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_TMRRST_B0_RST_MSK           (0x0000000F)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_TMRRST_B0_RST_MAX           (0x0000000F)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_TMRRST_B1_RST_OFF           ( 4)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_TMRRST_B1_RST_WID           ( 4)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_TMRRST_B1_RST_MSK           (0x000000F0)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_TMRRST_B1_RST_MAX           (0x0000000F)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_TMRRST_B2_RST_OFF           ( 8)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_TMRRST_B2_RST_WID           ( 4)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_TMRRST_B2_RST_MSK           (0x00000F00)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_TMRRST_B2_RST_MAX           (0x0000000F)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_TMRRST_B3_RST_OFF           (12)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_TMRRST_B3_RST_WID           ( 4)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_TMRRST_B3_RST_MSK           (0x0000F000)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_TMRRST_B3_RST_MAX           (0x0000000F)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_TMRRST_B4_RST_OFF           (16)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_TMRRST_B4_RST_WID           ( 4)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_TMRRST_B4_RST_MSK           (0x000F0000)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_TMRRST_B4_RST_MAX           (0x0000000F)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_TMRRST_B5_RST_OFF           (20)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_TMRRST_B5_RST_WID           ( 4)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_TMRRST_B5_RST_MSK           (0x00F00000)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_TMRRST_B5_RST_MAX           (0x0000000F)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_TMRRST_ELSEIF_ELSEIF_B1_RST_OFF (24)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_TMRRST_ELSEIF_ELSEIF_B1_RST_WID ( 4)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_TMRRST_ELSEIF_ELSEIF_B1_RST_MSK (0x0F000000)
+  #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_TMRRST_ELSEIF_ELSEIF_B1_RST_MAX (0x0000000F)
+
+#define GDXC_CR_DEBUP_REG                                            (0x00000700)
+  #define GDXC_CR_DEBUP_SPARE_OFF                                      ( 0)
+  #define GDXC_CR_DEBUP_SPARE_WID                                      ( 8)
+  #define GDXC_CR_DEBUP_SPARE_MSK                                      (0x000000FF)
+  #define GDXC_CR_DEBUP_SPARE_MAX                                      (0x000000FF)
+  #define GDXC_CR_DEBUP_SPARE_DEF                                      (0x00000000)
+
+#define MSGUTILS_CR_VISA2OCLA_CFG_REG                                (0x00000A04)
+  #define MSGUTILS_CR_VISA2OCLA_CFG_Ln0Src_OFF                         ( 0)
+  #define MSGUTILS_CR_VISA2OCLA_CFG_Ln0Src_WID                         ( 2)
+  #define MSGUTILS_CR_VISA2OCLA_CFG_Ln0Src_MSK                         (0x00000003)
+  #define MSGUTILS_CR_VISA2OCLA_CFG_Ln0Src_MAX                         (0x00000003)
+  #define MSGUTILS_CR_VISA2OCLA_CFG_Ln0Src_DEF                         (0x00000002)
+  #define MSGUTILS_CR_VISA2OCLA_CFG_Ln1Src_OFF                         ( 2)
+  #define MSGUTILS_CR_VISA2OCLA_CFG_Ln1Src_WID                         ( 2)
+  #define MSGUTILS_CR_VISA2OCLA_CFG_Ln1Src_MSK                         (0x0000000C)
+  #define MSGUTILS_CR_VISA2OCLA_CFG_Ln1Src_MAX                         (0x00000003)
+  #define MSGUTILS_CR_VISA2OCLA_CFG_Ln1Src_DEF                         (0x00000002)
+  #define MSGUTILS_CR_VISA2OCLA_CFG_DEVisaEn_OFF                       ( 4)
+  #define MSGUTILS_CR_VISA2OCLA_CFG_DEVisaEn_WID                       ( 1)
+  #define MSGUTILS_CR_VISA2OCLA_CFG_DEVisaEn_MSK                       (0x00000010)
+  #define MSGUTILS_CR_VISA2OCLA_CFG_DEVisaEn_MAX                       (0x00000001)
+  #define MSGUTILS_CR_VISA2OCLA_CFG_DEVisaEn_DEF                       (0x00000000)
+
+#pragma pack(pop)
+#endif  // __McGdxcbar_h__
diff --git a/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcRegisters/McIoCkeCtl.h b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcRegisters/McIoCkeCtl.h
new file mode 100644
index 0000000..45afcc5
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcRegisters/McIoCkeCtl.h
@@ -0,0 +1,2594 @@
+/** @file
+  This file was automatically generated. Modify at your own risk.
+
+@copyright
+  Copyright (c) 2010 - 2012 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement
+**/
+#ifndef __McIoCkeCtl_h__
+#define __McIoCkeCtl_h__
+
+#pragma pack(push, 1)
+#include "MrcTypes.h"
+
+typedef union {
+  struct {
+    U32 Scomp                                   :  6;  // Bits 5:0
+    U32 TcoComp                                 :  6;  // Bits 11:6
+    U32 RcompDrvUp                              :  6;  // Bits 17:12
+    U32 RcompDrvDown                            :  6;  // Bits 23:18
+    U32 LsComp                                  :  3;  // Bits 26:24
+    U32 Spare                                   :  5;  // Bits 31:27
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRCKECTL_CR_DDRCRCTLCOMP_STRUCT;
+
+typedef union {
+  struct {
+    U32 ScompOffset                             :  5;  // Bits 4:0
+    U32 TcoCompOffset                           :  4;  // Bits 8:5
+    U32 RcompDrvUpOffset                        :  4;  // Bits 12:9
+    U32 RcompDrvDownOffset                      :  4;  // Bits 16:13
+    U32 Spare                                   :  15;  // Bits 31:17
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRCKECTL_CR_DDRCRCTLCOMPOFFSET_STRUCT;
+
+typedef union {
+  struct {
+    U32 CtlPiCode0                              :  7;  // Bits 6:0
+    U32 CtlPiCode1                              :  7;  // Bits 13:7
+    U32 CtlPiCode2                              :  7;  // Bits 20:14
+    U32 CtlPiCode3                              :  7;  // Bits 27:21
+    U32 CtlXoverEnable                          :  1;  // Bits 28:28
+    U32 Spare                                   :  3;  // Bits 31:29
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRCKECTL_CR_DDRCRCTLPICODING_STRUCT;
+
+typedef union {
+  struct {
+    U32 RefPi                                   :  4;  // Bits 3:0
+    U32 DllMask                                 :  2;  // Bits 5:4
+    U32 DllRsvd1                                :  1;  // Bits 6:6
+    U32 TxOn                                    :  1;  // Bits 7:7
+    U32 IntClkOn                                :  1;  // Bits 8:8
+    U32 RepClkOn                                :  1;  // Bits 9:9
+    U32 IOLBCtl                                 :  2;  // Bits 11:10
+    U32 OdtMode                                 :  1;  // Bits 12:12
+    U32 CmdTxEq                                 :  2;  // Bits 14:13
+    U32 EarlyWeakDrive                          :  2;  // Bits 16:15
+    U32 CtlTxEq                                 :  2;  // Bits 18:17
+    U32 CtlSRDrv                                :  2;  // Bits 20:19
+    U32 RxVref                                  :  6;  // Bits 26:21
+    U32 VccddqHi                                :  1;  // Bits 27:27
+    U32 DllWeakLock                             :  1;  // Bits 28:28
+    U32 LPDDR_Mode                              :  1;  // Bits 29:29
+    U32 LaDrvEnOvrd                             :  1;  // Bits 30:30
+    U32 LPDdrCAA_Dis                            :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRCKECTL_CR_DDRCRCTLCONTROLS_STRUCT;
+
+typedef union {
+  struct {
+    U32 RankEn                                  :  4;  // Bits 3:0
+    U32 OdtDisable                              :  2;  // Bits 5:4
+    U32 Spare                                   :  26;  // Bits 31:6
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRCKECTL_CR_DDRCRCTLRANKSUSED_STRUCT;
+
+typedef union {
+  struct {
+    U32 RunTest                                 :  1;  // Bits 0:0
+    U32 Load                                    :  1;  // Bits 1:1
+    U32 ModeHVM                                 :  1;  // Bits 2:2
+    U32 ModeDV                                  :  1;  // Bits 3:3
+    U32 ModeADC                                 :  1;  // Bits 4:4
+    U32 LoadCount                               :  10;  // Bits 14:5
+    U32 CountStatus                             :  10;  // Bits 24:15
+    U32 Spare                                   :  7;  // Bits 31:25
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRCKECTL_CR_DLLPITESTANDADC_STRUCT;
+
+typedef union {
+  struct {
+    U32 Scomp                                   :  6;  // Bits 5:0
+    U32 TcoComp                                 :  6;  // Bits 11:6
+    U32 RcompDrvUp                              :  6;  // Bits 17:12
+    U32 RcompDrvDown                            :  6;  // Bits 23:18
+    U32 LsComp                                  :  3;  // Bits 26:24
+    U32 Spare                                   :  5;  // Bits 31:27
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRCKECTLCH0_CR_DDRCRCTLCOMP_STRUCT;
+
+typedef union {
+  struct {
+    U32 ScompOffset                             :  5;  // Bits 4:0
+    U32 TcoCompOffset                           :  4;  // Bits 8:5
+    U32 RcompDrvUpOffset                        :  4;  // Bits 12:9
+    U32 RcompDrvDownOffset                      :  4;  // Bits 16:13
+    U32 Spare                                   :  15;  // Bits 31:17
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRCKECTLCH0_CR_DDRCRCTLCOMPOFFSET_STRUCT;
+
+typedef union {
+  struct {
+    U32 CtlPiCode0                              :  7;  // Bits 6:0
+    U32 CtlPiCode1                              :  7;  // Bits 13:7
+    U32 CtlPiCode2                              :  7;  // Bits 20:14
+    U32 CtlPiCode3                              :  7;  // Bits 27:21
+    U32 CtlXoverEnable                          :  1;  // Bits 28:28
+    U32 Spare                                   :  3;  // Bits 31:29
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRCKECTLCH0_CR_DDRCRCTLPICODING_STRUCT;
+
+typedef union {
+  struct {
+    U32 RefPi                                   :  4;  // Bits 3:0
+    U32 DllMask                                 :  2;  // Bits 5:4
+    U32 DllRsvd1                                :  1;  // Bits 6:6
+    U32 TxOn                                    :  1;  // Bits 7:7
+    U32 IntClkOn                                :  1;  // Bits 8:8
+    U32 RepClkOn                                :  1;  // Bits 9:9
+    U32 IOLBCtl                                 :  2;  // Bits 11:10
+    U32 OdtMode                                 :  1;  // Bits 12:12
+    U32 CmdTxEq                                 :  2;  // Bits 14:13
+    U32 EarlyWeakDrive                          :  2;  // Bits 16:15
+    U32 CtlTxEq                                 :  2;  // Bits 18:17
+    U32 CtlSRDrv                                :  2;  // Bits 20:19
+    U32 RxVref                                  :  6;  // Bits 26:21
+    U32 VccddqHi                                :  1;  // Bits 27:27
+    U32 DllWeakLock                             :  1;  // Bits 28:28
+    U32 LPDDR_Mode                              :  1;  // Bits 29:29
+    U32 LaDrvEnOvrd                             :  1;  // Bits 30:30
+    U32 LPDdrCAA_Dis                            :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_STRUCT;
+
+typedef union {
+  struct {
+    U32 RankEn                                  :  4;  // Bits 3:0
+    U32 OdtDisable                              :  2;  // Bits 5:4
+    U32 Spare                                   :  26;  // Bits 31:6
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRCKECTLCH0_CR_DDRCRCTLRANKSUSED_STRUCT;
+
+typedef union {
+  struct {
+    U32 RunTest                                 :  1;  // Bits 0:0
+    U32 Load                                    :  1;  // Bits 1:1
+    U32 ModeHVM                                 :  1;  // Bits 2:2
+    U32 ModeDV                                  :  1;  // Bits 3:3
+    U32 ModeADC                                 :  1;  // Bits 4:4
+    U32 LoadCount                               :  10;  // Bits 14:5
+    U32 CountStatus                             :  10;  // Bits 24:15
+    U32 Spare                                   :  7;  // Bits 31:25
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRCKECTLCH0_CR_DLLPITESTANDADC_STRUCT;
+
+typedef union {
+  struct {
+    U32 Scomp                                   :  6;  // Bits 5:0
+    U32 TcoComp                                 :  6;  // Bits 11:6
+    U32 RcompDrvUp                              :  6;  // Bits 17:12
+    U32 RcompDrvDown                            :  6;  // Bits 23:18
+    U32 LsComp                                  :  3;  // Bits 26:24
+    U32 Spare                                   :  5;  // Bits 31:27
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRCKECTLCH1_CR_DDRCRCTLCOMP_STRUCT;
+
+typedef union {
+  struct {
+    U32 ScompOffset                             :  5;  // Bits 4:0
+    U32 TcoCompOffset                           :  4;  // Bits 8:5
+    U32 RcompDrvUpOffset                        :  4;  // Bits 12:9
+    U32 RcompDrvDownOffset                      :  4;  // Bits 16:13
+    U32 Spare                                   :  15;  // Bits 31:17
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRCKECTLCH1_CR_DDRCRCTLCOMPOFFSET_STRUCT;
+
+typedef union {
+  struct {
+    U32 CtlPiCode0                              :  7;  // Bits 6:0
+    U32 CtlPiCode1                              :  7;  // Bits 13:7
+    U32 CtlPiCode2                              :  7;  // Bits 20:14
+    U32 CtlPiCode3                              :  7;  // Bits 27:21
+    U32 CtlXoverEnable                          :  1;  // Bits 28:28
+    U32 Spare                                   :  3;  // Bits 31:29
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRCKECTLCH1_CR_DDRCRCTLPICODING_STRUCT;
+
+typedef union {
+  struct {
+    U32 RefPi                                   :  4;  // Bits 3:0
+    U32 DllMask                                 :  2;  // Bits 5:4
+    U32 DllRsvd1                                :  1;  // Bits 6:6
+    U32 TxOn                                    :  1;  // Bits 7:7
+    U32 IntClkOn                                :  1;  // Bits 8:8
+    U32 RepClkOn                                :  1;  // Bits 9:9
+    U32 IOLBCtl                                 :  2;  // Bits 11:10
+    U32 OdtMode                                 :  1;  // Bits 12:12
+    U32 CmdTxEq                                 :  2;  // Bits 14:13
+    U32 EarlyWeakDrive                          :  2;  // Bits 16:15
+    U32 CtlTxEq                                 :  2;  // Bits 18:17
+    U32 CtlSRDrv                                :  2;  // Bits 20:19
+    U32 RxVref                                  :  6;  // Bits 26:21
+    U32 VccddqHi                                :  1;  // Bits 27:27
+    U32 DllWeakLock                             :  1;  // Bits 28:28
+    U32 LPDDR_Mode                              :  1;  // Bits 29:29
+    U32 LaDrvEnOvrd                             :  1;  // Bits 30:30
+    U32 LPDdrCAA_Dis                            :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_STRUCT;
+
+typedef union {
+  struct {
+    U32 RankEn                                  :  4;  // Bits 3:0
+    U32 OdtDisable                              :  2;  // Bits 5:4
+    U32 Spare                                   :  26;  // Bits 31:6
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRCKECTLCH1_CR_DDRCRCTLRANKSUSED_STRUCT;
+
+typedef union {
+  struct {
+    U32 RunTest                                 :  1;  // Bits 0:0
+    U32 Load                                    :  1;  // Bits 1:1
+    U32 ModeHVM                                 :  1;  // Bits 2:2
+    U32 ModeDV                                  :  1;  // Bits 3:3
+    U32 ModeADC                                 :  1;  // Bits 4:4
+    U32 LoadCount                               :  10;  // Bits 14:5
+    U32 CountStatus                             :  10;  // Bits 24:15
+    U32 Spare                                   :  7;  // Bits 31:25
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRCKECTLCH1_CR_DLLPITESTANDADC_STRUCT;
+
+typedef union {
+  struct {
+    U32 Scomp                                   :  6;  // Bits 5:0
+    U32 TcoComp                                 :  6;  // Bits 11:6
+    U32 RcompDrvUp                              :  6;  // Bits 17:12
+    U32 RcompDrvDown                            :  6;  // Bits 23:18
+    U32 LsComp                                  :  3;  // Bits 26:24
+    U32 Spare                                   :  5;  // Bits 31:27
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRCKECH0_CR_DDRCRCMDCOMP_STRUCT;
+
+typedef union {
+  struct {
+    U32 ScompOffset                             :  5;  // Bits 4:0
+    U32 TcoCompOffset                           :  4;  // Bits 8:5
+    U32 RcompDrvUpOffset                        :  4;  // Bits 12:9
+    U32 RcompDrvDownOffset                      :  4;  // Bits 16:13
+    U32 Spare                                   :  15;  // Bits 31:17
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRCKECH0_CR_DDRCRCMDCOMPOFFSET_STRUCT;
+
+typedef union {
+  struct {
+    U32 CmdPi0Code                              :  7;  // Bits 6:0
+    U32 CmdPi1Code                              :  7;  // Bits 13:7
+    U32 Spare                                   :  18;  // Bits 31:14
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRCKECH0_CR_DDRCRCMDPICODING_STRUCT;
+
+typedef union {
+  struct {
+    U32 Scomp                                   :  6;  // Bits 5:0
+    U32 TcoComp                                 :  6;  // Bits 11:6
+    U32 RcompDrvUp                              :  6;  // Bits 17:12
+    U32 RcompDrvDown                            :  6;  // Bits 23:18
+    U32 LsComp                                  :  3;  // Bits 26:24
+    U32 Spare                                   :  5;  // Bits 31:27
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRCKECH0_CR_DDRCRCTLCOMP_STRUCT;
+
+typedef union {
+  struct {
+    U32 ScompOffset                             :  5;  // Bits 4:0
+    U32 TcoCompOffset                           :  4;  // Bits 8:5
+    U32 RcompDrvUpOffset                        :  4;  // Bits 12:9
+    U32 RcompDrvDownOffset                      :  4;  // Bits 16:13
+    U32 Spare                                   :  15;  // Bits 31:17
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRCKECH0_CR_DDRCRCTLCOMPOFFSET_STRUCT;
+
+typedef union {
+  struct {
+    U32 CtlPiCode0                              :  7;  // Bits 6:0
+    U32 CtlPiCode1                              :  7;  // Bits 13:7
+    U32 CtlPiCode2                              :  7;  // Bits 20:14
+    U32 CtlPiCode3                              :  7;  // Bits 27:21
+    U32 CtlXoverEnable                          :  1;  // Bits 28:28
+    U32 Spare                                   :  3;  // Bits 31:29
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRCKECH0_CR_DDRCRCTLPICODING_STRUCT;
+
+typedef union {
+  struct {
+    U32 RefPi                                   :  4;  // Bits 3:0
+    U32 DllMask                                 :  2;  // Bits 5:4
+    U32 DllRsvd1                                :  1;  // Bits 6:6
+    U32 TxOn                                    :  1;  // Bits 7:7
+    U32 IntClkOn                                :  1;  // Bits 8:8
+    U32 RepClkOn                                :  1;  // Bits 9:9
+    U32 IOLBCtl                                 :  2;  // Bits 11:10
+    U32 OdtMode                                 :  1;  // Bits 12:12
+    U32 CmdTxEq                                 :  2;  // Bits 14:13
+    U32 EarlyWeakDrive                          :  2;  // Bits 16:15
+    U32 CtlTxEq                                 :  2;  // Bits 18:17
+    U32 CtlSRDrv                                :  2;  // Bits 20:19
+    U32 RxVref                                  :  6;  // Bits 26:21
+    U32 VccddqHi                                :  1;  // Bits 27:27
+    U32 DllWeakLock                             :  1;  // Bits 28:28
+    U32 LPDDR_Mode                              :  1;  // Bits 29:29
+    U32 LaDrvEnOvrd                             :  1;  // Bits 30:30
+    U32 LPDdrCAA_Dis                            :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRCKECH0_CR_DDRCRCTLCONTROLS_STRUCT;
+
+typedef union {
+  struct {
+    U32 RankEn                                  :  4;  // Bits 3:0
+    U32 OdtDisable                              :  2;  // Bits 5:4
+    U32 Spare                                   :  26;  // Bits 31:6
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRCKECH0_CR_DDRCRCTLRANKSUSED_STRUCT;
+
+typedef union {
+  struct {
+    U32 RunTest                                 :  1;  // Bits 0:0
+    U32 Load                                    :  1;  // Bits 1:1
+    U32 ModeHVM                                 :  1;  // Bits 2:2
+    U32 ModeDV                                  :  1;  // Bits 3:3
+    U32 ModeADC                                 :  1;  // Bits 4:4
+    U32 LoadCount                               :  10;  // Bits 14:5
+    U32 CountStatus                             :  10;  // Bits 24:15
+    U32 Spare                                   :  7;  // Bits 31:25
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRCKECH0_CR_DLLPITESTANDADC_STRUCT;
+
+typedef union {
+  struct {
+    U32 Scomp                                   :  6;  // Bits 5:0
+    U32 TcoComp                                 :  6;  // Bits 11:6
+    U32 RcompDrvUp                              :  6;  // Bits 17:12
+    U32 RcompDrvDown                            :  6;  // Bits 23:18
+    U32 LsComp                                  :  3;  // Bits 26:24
+    U32 Spare                                   :  5;  // Bits 31:27
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRCKECH1_CR_DDRCRCMDCOMP_STRUCT;
+
+typedef union {
+  struct {
+    U32 ScompOffset                             :  5;  // Bits 4:0
+    U32 TcoCompOffset                           :  4;  // Bits 8:5
+    U32 RcompDrvUpOffset                        :  4;  // Bits 12:9
+    U32 RcompDrvDownOffset                      :  4;  // Bits 16:13
+    U32 Spare                                   :  15;  // Bits 31:17
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRCKECH1_CR_DDRCRCMDCOMPOFFSET_STRUCT;
+
+typedef union {
+  struct {
+    U32 CmdPi0Code                              :  7;  // Bits 6:0
+    U32 CmdPi1Code                              :  7;  // Bits 13:7
+    U32 Spare                                   :  18;  // Bits 31:14
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRCKECH1_CR_DDRCRCMDPICODING_STRUCT;
+
+typedef union {
+  struct {
+    U32 Scomp                                   :  6;  // Bits 5:0
+    U32 TcoComp                                 :  6;  // Bits 11:6
+    U32 RcompDrvUp                              :  6;  // Bits 17:12
+    U32 RcompDrvDown                            :  6;  // Bits 23:18
+    U32 LsComp                                  :  3;  // Bits 26:24
+    U32 Spare                                   :  5;  // Bits 31:27
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRCKECH1_CR_DDRCRCTLCOMP_STRUCT;
+
+typedef union {
+  struct {
+    U32 ScompOffset                             :  5;  // Bits 4:0
+    U32 TcoCompOffset                           :  4;  // Bits 8:5
+    U32 RcompDrvUpOffset                        :  4;  // Bits 12:9
+    U32 RcompDrvDownOffset                      :  4;  // Bits 16:13
+    U32 Spare                                   :  15;  // Bits 31:17
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRCKECH1_CR_DDRCRCTLCOMPOFFSET_STRUCT;
+
+typedef union {
+  struct {
+    U32 CtlPiCode0                              :  7;  // Bits 6:0
+    U32 CtlPiCode1                              :  7;  // Bits 13:7
+    U32 CtlPiCode2                              :  7;  // Bits 20:14
+    U32 CtlPiCode3                              :  7;  // Bits 27:21
+    U32 CtlXoverEnable                          :  1;  // Bits 28:28
+    U32 Spare                                   :  3;  // Bits 31:29
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRCKECH1_CR_DDRCRCTLPICODING_STRUCT;
+
+typedef union {
+  struct {
+    U32 RefPi                                   :  4;  // Bits 3:0
+    U32 DllMask                                 :  2;  // Bits 5:4
+    U32 DllRsvd1                                :  1;  // Bits 6:6
+    U32 TxOn                                    :  1;  // Bits 7:7
+    U32 IntClkOn                                :  1;  // Bits 8:8
+    U32 RepClkOn                                :  1;  // Bits 9:9
+    U32 IOLBCtl                                 :  2;  // Bits 11:10
+    U32 OdtMode                                 :  1;  // Bits 12:12
+    U32 CmdTxEq                                 :  2;  // Bits 14:13
+    U32 EarlyWeakDrive                          :  2;  // Bits 16:15
+    U32 CtlTxEq                                 :  2;  // Bits 18:17
+    U32 CtlSRDrv                                :  2;  // Bits 20:19
+    U32 RxVref                                  :  6;  // Bits 26:21
+    U32 VccddqHi                                :  1;  // Bits 27:27
+    U32 DllWeakLock                             :  1;  // Bits 28:28
+    U32 LPDDR_Mode                              :  1;  // Bits 29:29
+    U32 LaDrvEnOvrd                             :  1;  // Bits 30:30
+    U32 LPDdrCAA_Dis                            :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRCKECH1_CR_DDRCRCTLCONTROLS_STRUCT;
+
+typedef union {
+  struct {
+    U32 RankEn                                  :  4;  // Bits 3:0
+    U32 OdtDisable                              :  2;  // Bits 5:4
+    U32 Spare                                   :  26;  // Bits 31:6
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRCKECH1_CR_DDRCRCTLRANKSUSED_STRUCT;
+
+typedef union {
+  struct {
+    U32 RunTest                                 :  1;  // Bits 0:0
+    U32 Load                                    :  1;  // Bits 1:1
+    U32 ModeHVM                                 :  1;  // Bits 2:2
+    U32 ModeDV                                  :  1;  // Bits 3:3
+    U32 ModeADC                                 :  1;  // Bits 4:4
+    U32 LoadCount                               :  10;  // Bits 14:5
+    U32 CountStatus                             :  10;  // Bits 24:15
+    U32 Spare                                   :  7;  // Bits 31:25
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRCKECH1_CR_DLLPITESTANDADC_STRUCT;
+
+typedef union {
+  struct {
+    U32 Scomp                                   :  6;  // Bits 5:0
+    U32 TcoComp                                 :  6;  // Bits 11:6
+    U32 RcompDrvUp                              :  6;  // Bits 17:12
+    U32 RcompDrvDown                            :  6;  // Bits 23:18
+    U32 LsComp                                  :  3;  // Bits 26:24
+    U32 Spare                                   :  5;  // Bits 31:27
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRCTLCH0_CR_DDRCRCTLCOMP_STRUCT;
+
+typedef union {
+  struct {
+    U32 ScompOffset                             :  5;  // Bits 4:0
+    U32 TcoCompOffset                           :  4;  // Bits 8:5
+    U32 RcompDrvUpOffset                        :  4;  // Bits 12:9
+    U32 RcompDrvDownOffset                      :  4;  // Bits 16:13
+    U32 Spare                                   :  15;  // Bits 31:17
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRCTLCH0_CR_DDRCRCTLCOMPOFFSET_STRUCT;
+
+typedef union {
+  struct {
+    U32 CtlPiCode0                              :  7;  // Bits 6:0
+    U32 CtlPiCode1                              :  7;  // Bits 13:7
+    U32 CtlPiCode2                              :  7;  // Bits 20:14
+    U32 CtlPiCode3                              :  7;  // Bits 27:21
+    U32 CtlXoverEnable                          :  1;  // Bits 28:28
+    U32 Spare                                   :  3;  // Bits 31:29
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRCTLCH0_CR_DDRCRCTLPICODING_STRUCT;
+
+typedef union {
+  struct {
+    U32 RefPi                                   :  4;  // Bits 3:0
+    U32 DllMask                                 :  2;  // Bits 5:4
+    U32 DllRsvd1                                :  1;  // Bits 6:6
+    U32 TxOn                                    :  1;  // Bits 7:7
+    U32 IntClkOn                                :  1;  // Bits 8:8
+    U32 RepClkOn                                :  1;  // Bits 9:9
+    U32 IOLBCtl                                 :  2;  // Bits 11:10
+    U32 OdtMode                                 :  1;  // Bits 12:12
+    U32 CmdTxEq                                 :  2;  // Bits 14:13
+    U32 EarlyWeakDrive                          :  2;  // Bits 16:15
+    U32 CtlTxEq                                 :  2;  // Bits 18:17
+    U32 CtlSRDrv                                :  2;  // Bits 20:19
+    U32 RxVref                                  :  6;  // Bits 26:21
+    U32 VccddqHi                                :  1;  // Bits 27:27
+    U32 DllWeakLock                             :  1;  // Bits 28:28
+    U32 LPDDR_Mode                              :  1;  // Bits 29:29
+    U32 LaDrvEnOvrd                             :  1;  // Bits 30:30
+    U32 LPDdrCAA_Dis                            :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRCTLCH0_CR_DDRCRCTLCONTROLS_STRUCT;
+
+typedef union {
+  struct {
+    U32 RankEn                                  :  4;  // Bits 3:0
+    U32 OdtDisable                              :  2;  // Bits 5:4
+    U32 Spare                                   :  26;  // Bits 31:6
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRCTLCH0_CR_DDRCRCTLRANKSUSED_STRUCT;
+
+typedef union {
+  struct {
+    U32 RunTest                                 :  1;  // Bits 0:0
+    U32 Load                                    :  1;  // Bits 1:1
+    U32 ModeHVM                                 :  1;  // Bits 2:2
+    U32 ModeDV                                  :  1;  // Bits 3:3
+    U32 ModeADC                                 :  1;  // Bits 4:4
+    U32 LoadCount                               :  10;  // Bits 14:5
+    U32 CountStatus                             :  10;  // Bits 24:15
+    U32 Spare                                   :  7;  // Bits 31:25
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRCTLCH0_CR_DLLPITESTANDADC_STRUCT;
+
+typedef union {
+  struct {
+    U32 Scomp                                   :  6;  // Bits 5:0
+    U32 TcoComp                                 :  6;  // Bits 11:6
+    U32 RcompDrvUp                              :  6;  // Bits 17:12
+    U32 RcompDrvDown                            :  6;  // Bits 23:18
+    U32 LsComp                                  :  3;  // Bits 26:24
+    U32 Spare                                   :  5;  // Bits 31:27
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRCTLCH1_CR_DDRCRCTLCOMP_STRUCT;
+
+typedef union {
+  struct {
+    U32 ScompOffset                             :  5;  // Bits 4:0
+    U32 TcoCompOffset                           :  4;  // Bits 8:5
+    U32 RcompDrvUpOffset                        :  4;  // Bits 12:9
+    U32 RcompDrvDownOffset                      :  4;  // Bits 16:13
+    U32 Spare                                   :  15;  // Bits 31:17
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRCTLCH1_CR_DDRCRCTLCOMPOFFSET_STRUCT;
+
+typedef union {
+  struct {
+    U32 CtlPiCode0                              :  7;  // Bits 6:0
+    U32 CtlPiCode1                              :  7;  // Bits 13:7
+    U32 CtlPiCode2                              :  7;  // Bits 20:14
+    U32 CtlPiCode3                              :  7;  // Bits 27:21
+    U32 CtlXoverEnable                          :  1;  // Bits 28:28
+    U32 Spare                                   :  3;  // Bits 31:29
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRCTLCH1_CR_DDRCRCTLPICODING_STRUCT;
+
+typedef union {
+  struct {
+    U32 RefPi                                   :  4;  // Bits 3:0
+    U32 DllMask                                 :  2;  // Bits 5:4
+    U32 DllRsvd1                                :  1;  // Bits 6:6
+    U32 TxOn                                    :  1;  // Bits 7:7
+    U32 IntClkOn                                :  1;  // Bits 8:8
+    U32 RepClkOn                                :  1;  // Bits 9:9
+    U32 IOLBCtl                                 :  2;  // Bits 11:10
+    U32 OdtMode                                 :  1;  // Bits 12:12
+    U32 CmdTxEq                                 :  2;  // Bits 14:13
+    U32 EarlyWeakDrive                          :  2;  // Bits 16:15
+    U32 CtlTxEq                                 :  2;  // Bits 18:17
+    U32 CtlSRDrv                                :  2;  // Bits 20:19
+    U32 RxVref                                  :  6;  // Bits 26:21
+    U32 VccddqHi                                :  1;  // Bits 27:27
+    U32 DllWeakLock                             :  1;  // Bits 28:28
+    U32 LPDDR_Mode                              :  1;  // Bits 29:29
+    U32 LaDrvEnOvrd                             :  1;  // Bits 30:30
+    U32 LPDdrCAA_Dis                            :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRCTLCH1_CR_DDRCRCTLCONTROLS_STRUCT;
+
+typedef union {
+  struct {
+    U32 RankEn                                  :  4;  // Bits 3:0
+    U32 OdtDisable                              :  2;  // Bits 5:4
+    U32 Spare                                   :  26;  // Bits 31:6
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRCTLCH1_CR_DDRCRCTLRANKSUSED_STRUCT;
+
+typedef union {
+  struct {
+    U32 RunTest                                 :  1;  // Bits 0:0
+    U32 Load                                    :  1;  // Bits 1:1
+    U32 ModeHVM                                 :  1;  // Bits 2:2
+    U32 ModeDV                                  :  1;  // Bits 3:3
+    U32 ModeADC                                 :  1;  // Bits 4:4
+    U32 LoadCount                               :  10;  // Bits 14:5
+    U32 CountStatus                             :  10;  // Bits 24:15
+    U32 Spare                                   :  7;  // Bits 31:25
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRCTLCH1_CR_DLLPITESTANDADC_STRUCT;
+
+#define DDRCKECTL_CR_DDRCRCTLCOMP_REG                                (0x00003810)
+  #define DDRCKECTL_CR_DDRCRCTLCOMP_Scomp_OFF                          ( 0)
+  #define DDRCKECTL_CR_DDRCRCTLCOMP_Scomp_WID                          ( 6)
+  #define DDRCKECTL_CR_DDRCRCTLCOMP_Scomp_MSK                          (0x0000003F)
+  #define DDRCKECTL_CR_DDRCRCTLCOMP_Scomp_MAX                          (0x0000003F)
+  #define DDRCKECTL_CR_DDRCRCTLCOMP_Scomp_DEF                          (0x00000000)
+  #define DDRCKECTL_CR_DDRCRCTLCOMP_TcoComp_OFF                        ( 6)
+  #define DDRCKECTL_CR_DDRCRCTLCOMP_TcoComp_WID                        ( 6)
+  #define DDRCKECTL_CR_DDRCRCTLCOMP_TcoComp_MSK                        (0x00000FC0)
+  #define DDRCKECTL_CR_DDRCRCTLCOMP_TcoComp_MAX                        (0x0000003F)
+  #define DDRCKECTL_CR_DDRCRCTLCOMP_TcoComp_DEF                        (0x00000000)
+  #define DDRCKECTL_CR_DDRCRCTLCOMP_RcompDrvUp_OFF                     (12)
+  #define DDRCKECTL_CR_DDRCRCTLCOMP_RcompDrvUp_WID                     ( 6)
+  #define DDRCKECTL_CR_DDRCRCTLCOMP_RcompDrvUp_MSK                     (0x0003F000)
+  #define DDRCKECTL_CR_DDRCRCTLCOMP_RcompDrvUp_MAX                     (0x0000003F)
+  #define DDRCKECTL_CR_DDRCRCTLCOMP_RcompDrvUp_DEF                     (0x00000000)
+  #define DDRCKECTL_CR_DDRCRCTLCOMP_RcompDrvDown_OFF                   (18)
+  #define DDRCKECTL_CR_DDRCRCTLCOMP_RcompDrvDown_WID                   ( 6)
+  #define DDRCKECTL_CR_DDRCRCTLCOMP_RcompDrvDown_MSK                   (0x00FC0000)
+  #define DDRCKECTL_CR_DDRCRCTLCOMP_RcompDrvDown_MAX                   (0x0000003F)
+  #define DDRCKECTL_CR_DDRCRCTLCOMP_RcompDrvDown_DEF                   (0x00000000)
+  #define DDRCKECTL_CR_DDRCRCTLCOMP_LsComp_OFF                         (24)
+  #define DDRCKECTL_CR_DDRCRCTLCOMP_LsComp_WID                         ( 3)
+  #define DDRCKECTL_CR_DDRCRCTLCOMP_LsComp_MSK                         (0x07000000)
+  #define DDRCKECTL_CR_DDRCRCTLCOMP_LsComp_MAX                         (0x00000007)
+  #define DDRCKECTL_CR_DDRCRCTLCOMP_LsComp_DEF                         (0x00000000)
+  #define DDRCKECTL_CR_DDRCRCTLCOMP_Spare_OFF                          (27)
+  #define DDRCKECTL_CR_DDRCRCTLCOMP_Spare_WID                          ( 5)
+  #define DDRCKECTL_CR_DDRCRCTLCOMP_Spare_MSK                          (0xF8000000)
+  #define DDRCKECTL_CR_DDRCRCTLCOMP_Spare_MAX                          (0x0000001F)
+  #define DDRCKECTL_CR_DDRCRCTLCOMP_Spare_DEF                          (0x00000000)
+
+#define DDRCKECTL_CR_DDRCRCTLCOMPOFFSET_REG                          (0x00003814)
+  #define DDRCKECTL_CR_DDRCRCTLCOMPOFFSET_ScompOffset_OFF              ( 0)
+  #define DDRCKECTL_CR_DDRCRCTLCOMPOFFSET_ScompOffset_WID              ( 5)
+  #define DDRCKECTL_CR_DDRCRCTLCOMPOFFSET_ScompOffset_MSK              (0x0000001F)
+  #define DDRCKECTL_CR_DDRCRCTLCOMPOFFSET_ScompOffset_MAX              (0x0000001F)
+  #define DDRCKECTL_CR_DDRCRCTLCOMPOFFSET_ScompOffset_DEF              (0x00000000)
+  #define DDRCKECTL_CR_DDRCRCTLCOMPOFFSET_TcoCompOffset_OFF            ( 5)
+  #define DDRCKECTL_CR_DDRCRCTLCOMPOFFSET_TcoCompOffset_WID            ( 4)
+  #define DDRCKECTL_CR_DDRCRCTLCOMPOFFSET_TcoCompOffset_MSK            (0x000001E0)
+  #define DDRCKECTL_CR_DDRCRCTLCOMPOFFSET_TcoCompOffset_MAX            (0x0000000F)
+  #define DDRCKECTL_CR_DDRCRCTLCOMPOFFSET_TcoCompOffset_DEF            (0x00000000)
+  #define DDRCKECTL_CR_DDRCRCTLCOMPOFFSET_RcompDrvUpOffset_OFF         ( 9)
+  #define DDRCKECTL_CR_DDRCRCTLCOMPOFFSET_RcompDrvUpOffset_WID         ( 4)
+  #define DDRCKECTL_CR_DDRCRCTLCOMPOFFSET_RcompDrvUpOffset_MSK         (0x00001E00)
+  #define DDRCKECTL_CR_DDRCRCTLCOMPOFFSET_RcompDrvUpOffset_MAX         (0x0000000F)
+  #define DDRCKECTL_CR_DDRCRCTLCOMPOFFSET_RcompDrvUpOffset_DEF         (0x00000000)
+  #define DDRCKECTL_CR_DDRCRCTLCOMPOFFSET_RcompDrvDownOffset_OFF       (13)
+  #define DDRCKECTL_CR_DDRCRCTLCOMPOFFSET_RcompDrvDownOffset_WID       ( 4)
+  #define DDRCKECTL_CR_DDRCRCTLCOMPOFFSET_RcompDrvDownOffset_MSK       (0x0001E000)
+  #define DDRCKECTL_CR_DDRCRCTLCOMPOFFSET_RcompDrvDownOffset_MAX       (0x0000000F)
+  #define DDRCKECTL_CR_DDRCRCTLCOMPOFFSET_RcompDrvDownOffset_DEF       (0x00000000)
+  #define DDRCKECTL_CR_DDRCRCTLCOMPOFFSET_Spare_OFF                    (17)
+  #define DDRCKECTL_CR_DDRCRCTLCOMPOFFSET_Spare_WID                    (15)
+  #define DDRCKECTL_CR_DDRCRCTLCOMPOFFSET_Spare_MSK                    (0xFFFE0000)
+  #define DDRCKECTL_CR_DDRCRCTLCOMPOFFSET_Spare_MAX                    (0x00007FFF)
+  #define DDRCKECTL_CR_DDRCRCTLCOMPOFFSET_Spare_DEF                    (0x00000000)
+
+#define DDRCKECTL_CR_DDRCRCTLPICODING_REG                            (0x00003818)
+  #define DDRCKECTL_CR_DDRCRCTLPICODING_CtlPiCode0_OFF                 ( 0)
+  #define DDRCKECTL_CR_DDRCRCTLPICODING_CtlPiCode0_WID                 ( 7)
+  #define DDRCKECTL_CR_DDRCRCTLPICODING_CtlPiCode0_MSK                 (0x0000007F)
+  #define DDRCKECTL_CR_DDRCRCTLPICODING_CtlPiCode0_MAX                 (0x0000007F)
+  #define DDRCKECTL_CR_DDRCRCTLPICODING_CtlPiCode0_DEF                 (0x00000000)
+  #define DDRCKECTL_CR_DDRCRCTLPICODING_CtlPiCode1_OFF                 ( 7)
+  #define DDRCKECTL_CR_DDRCRCTLPICODING_CtlPiCode1_WID                 ( 7)
+  #define DDRCKECTL_CR_DDRCRCTLPICODING_CtlPiCode1_MSK                 (0x00003F80)
+  #define DDRCKECTL_CR_DDRCRCTLPICODING_CtlPiCode1_MAX                 (0x0000007F)
+  #define DDRCKECTL_CR_DDRCRCTLPICODING_CtlPiCode1_DEF                 (0x00000000)
+  #define DDRCKECTL_CR_DDRCRCTLPICODING_CtlPiCode2_OFF                 (14)
+  #define DDRCKECTL_CR_DDRCRCTLPICODING_CtlPiCode2_WID                 ( 7)
+  #define DDRCKECTL_CR_DDRCRCTLPICODING_CtlPiCode2_MSK                 (0x001FC000)
+  #define DDRCKECTL_CR_DDRCRCTLPICODING_CtlPiCode2_MAX                 (0x0000007F)
+  #define DDRCKECTL_CR_DDRCRCTLPICODING_CtlPiCode2_DEF                 (0x00000000)
+  #define DDRCKECTL_CR_DDRCRCTLPICODING_CtlPiCode3_OFF                 (21)
+  #define DDRCKECTL_CR_DDRCRCTLPICODING_CtlPiCode3_WID                 ( 7)
+  #define DDRCKECTL_CR_DDRCRCTLPICODING_CtlPiCode3_MSK                 (0x0FE00000)
+  #define DDRCKECTL_CR_DDRCRCTLPICODING_CtlPiCode3_MAX                 (0x0000007F)
+  #define DDRCKECTL_CR_DDRCRCTLPICODING_CtlPiCode3_DEF                 (0x00000000)
+  #define DDRCKECTL_CR_DDRCRCTLPICODING_CtlXoverEnable_OFF             (28)
+  #define DDRCKECTL_CR_DDRCRCTLPICODING_CtlXoverEnable_WID             ( 1)
+  #define DDRCKECTL_CR_DDRCRCTLPICODING_CtlXoverEnable_MSK             (0x10000000)
+  #define DDRCKECTL_CR_DDRCRCTLPICODING_CtlXoverEnable_MAX             (0x00000001)
+  #define DDRCKECTL_CR_DDRCRCTLPICODING_CtlXoverEnable_DEF             (0x00000000)
+  #define DDRCKECTL_CR_DDRCRCTLPICODING_Spare_OFF                      (29)
+  #define DDRCKECTL_CR_DDRCRCTLPICODING_Spare_WID                      ( 3)
+  #define DDRCKECTL_CR_DDRCRCTLPICODING_Spare_MSK                      (0xE0000000)
+  #define DDRCKECTL_CR_DDRCRCTLPICODING_Spare_MAX                      (0x00000007)
+  #define DDRCKECTL_CR_DDRCRCTLPICODING_Spare_DEF                      (0x00000000)
+
+#define DDRCKECTL_CR_DDRCRCTLCONTROLS_REG                            (0x0000381C)
+  #define DDRCKECTL_CR_DDRCRCTLCONTROLS_RefPi_OFF                      ( 0)
+  #define DDRCKECTL_CR_DDRCRCTLCONTROLS_RefPi_WID                      ( 4)
+  #define DDRCKECTL_CR_DDRCRCTLCONTROLS_RefPi_MSK                      (0x0000000F)
+  #define DDRCKECTL_CR_DDRCRCTLCONTROLS_RefPi_MAX                      (0x0000000F)
+  #define DDRCKECTL_CR_DDRCRCTLCONTROLS_RefPi_DEF                      (0x00000000)
+  #define DDRCKECTL_CR_DDRCRCTLCONTROLS_DllMask_OFF                    ( 4)
+  #define DDRCKECTL_CR_DDRCRCTLCONTROLS_DllMask_WID                    ( 2)
+  #define DDRCKECTL_CR_DDRCRCTLCONTROLS_DllMask_MSK                    (0x00000030)
+  #define DDRCKECTL_CR_DDRCRCTLCONTROLS_DllMask_MAX                    (0x00000003)
+  #define DDRCKECTL_CR_DDRCRCTLCONTROLS_DllMask_DEF                    (0x00000000)
+  #define DDRCKECTL_CR_DDRCRCTLCONTROLS_DllRsvd1_OFF                   ( 6)
+  #define DDRCKECTL_CR_DDRCRCTLCONTROLS_DllRsvd1_WID                   ( 1)
+  #define DDRCKECTL_CR_DDRCRCTLCONTROLS_DllRsvd1_MSK                   (0x00000040)
+  #define DDRCKECTL_CR_DDRCRCTLCONTROLS_DllRsvd1_MAX                   (0x00000001)
+  #define DDRCKECTL_CR_DDRCRCTLCONTROLS_DllRsvd1_DEF                   (0x00000000)
+  #define DDRCKECTL_CR_DDRCRCTLCONTROLS_TxOn_OFF                       ( 7)
+  #define DDRCKECTL_CR_DDRCRCTLCONTROLS_TxOn_WID                       ( 1)
+  #define DDRCKECTL_CR_DDRCRCTLCONTROLS_TxOn_MSK                       (0x00000080)
+  #define DDRCKECTL_CR_DDRCRCTLCONTROLS_TxOn_MAX                       (0x00000001)
+  #define DDRCKECTL_CR_DDRCRCTLCONTROLS_TxOn_DEF                       (0x00000000)
+  #define DDRCKECTL_CR_DDRCRCTLCONTROLS_IntClkOn_OFF                   ( 8)
+  #define DDRCKECTL_CR_DDRCRCTLCONTROLS_IntClkOn_WID                   ( 1)
+  #define DDRCKECTL_CR_DDRCRCTLCONTROLS_IntClkOn_MSK                   (0x00000100)
+  #define DDRCKECTL_CR_DDRCRCTLCONTROLS_IntClkOn_MAX                   (0x00000001)
+  #define DDRCKECTL_CR_DDRCRCTLCONTROLS_IntClkOn_DEF                   (0x00000000)
+  #define DDRCKECTL_CR_DDRCRCTLCONTROLS_RepClkOn_OFF                   ( 9)
+  #define DDRCKECTL_CR_DDRCRCTLCONTROLS_RepClkOn_WID                   ( 1)
+  #define DDRCKECTL_CR_DDRCRCTLCONTROLS_RepClkOn_MSK                   (0x00000200)
+  #define DDRCKECTL_CR_DDRCRCTLCONTROLS_RepClkOn_MAX                   (0x00000001)
+  #define DDRCKECTL_CR_DDRCRCTLCONTROLS_RepClkOn_DEF                   (0x00000000)
+  #define DDRCKECTL_CR_DDRCRCTLCONTROLS_IOLBCtl_OFF                    (10)
+  #define DDRCKECTL_CR_DDRCRCTLCONTROLS_IOLBCtl_WID                    ( 2)
+  #define DDRCKECTL_CR_DDRCRCTLCONTROLS_IOLBCtl_MSK                    (0x00000C00)
+  #define DDRCKECTL_CR_DDRCRCTLCONTROLS_IOLBCtl_MAX                    (0x00000003)
+  #define DDRCKECTL_CR_DDRCRCTLCONTROLS_IOLBCtl_DEF                    (0x00000000)
+  #define DDRCKECTL_CR_DDRCRCTLCONTROLS_OdtMode_OFF                    (12)
+  #define DDRCKECTL_CR_DDRCRCTLCONTROLS_OdtMode_WID                    ( 1)
+  #define DDRCKECTL_CR_DDRCRCTLCONTROLS_OdtMode_MSK                    (0x00001000)
+  #define DDRCKECTL_CR_DDRCRCTLCONTROLS_OdtMode_MAX                    (0x00000001)
+  #define DDRCKECTL_CR_DDRCRCTLCONTROLS_OdtMode_DEF                    (0x00000000)
+  #define DDRCKECTL_CR_DDRCRCTLCONTROLS_CmdTxEq_OFF                    (13)
+  #define DDRCKECTL_CR_DDRCRCTLCONTROLS_CmdTxEq_WID                    ( 2)
+  #define DDRCKECTL_CR_DDRCRCTLCONTROLS_CmdTxEq_MSK                    (0x00006000)
+  #define DDRCKECTL_CR_DDRCRCTLCONTROLS_CmdTxEq_MAX                    (0x00000003)
+  #define DDRCKECTL_CR_DDRCRCTLCONTROLS_CmdTxEq_DEF                    (0x00000000)
+  #define DDRCKECTL_CR_DDRCRCTLCONTROLS_EarlyWeakDrive_OFF             (15)
+  #define DDRCKECTL_CR_DDRCRCTLCONTROLS_EarlyWeakDrive_WID             ( 2)
+  #define DDRCKECTL_CR_DDRCRCTLCONTROLS_EarlyWeakDrive_MSK             (0x00018000)
+  #define DDRCKECTL_CR_DDRCRCTLCONTROLS_EarlyWeakDrive_MAX             (0x00000003)
+  #define DDRCKECTL_CR_DDRCRCTLCONTROLS_EarlyWeakDrive_DEF             (0x00000000)
+  #define DDRCKECTL_CR_DDRCRCTLCONTROLS_CtlTxEq_OFF                    (17)
+  #define DDRCKECTL_CR_DDRCRCTLCONTROLS_CtlTxEq_WID                    ( 2)
+  #define DDRCKECTL_CR_DDRCRCTLCONTROLS_CtlTxEq_MSK                    (0x00060000)
+  #define DDRCKECTL_CR_DDRCRCTLCONTROLS_CtlTxEq_MAX                    (0x00000003)
+  #define DDRCKECTL_CR_DDRCRCTLCONTROLS_CtlTxEq_DEF                    (0x00000000)
+  #define DDRCKECTL_CR_DDRCRCTLCONTROLS_CtlSRDrv_OFF                   (19)
+  #define DDRCKECTL_CR_DDRCRCTLCONTROLS_CtlSRDrv_WID                   ( 2)
+  #define DDRCKECTL_CR_DDRCRCTLCONTROLS_CtlSRDrv_MSK                   (0x00180000)
+  #define DDRCKECTL_CR_DDRCRCTLCONTROLS_CtlSRDrv_MAX                   (0x00000003)
+  #define DDRCKECTL_CR_DDRCRCTLCONTROLS_CtlSRDrv_DEF                   (0x00000000)
+  #define DDRCKECTL_CR_DDRCRCTLCONTROLS_RxVref_OFF                     (21)
+  #define DDRCKECTL_CR_DDRCRCTLCONTROLS_RxVref_WID                     ( 6)
+  #define DDRCKECTL_CR_DDRCRCTLCONTROLS_RxVref_MSK                     (0x07E00000)
+  #define DDRCKECTL_CR_DDRCRCTLCONTROLS_RxVref_MAX                     (0x0000003F)
+  #define DDRCKECTL_CR_DDRCRCTLCONTROLS_RxVref_DEF                     (0x00000000)
+  #define DDRCKECTL_CR_DDRCRCTLCONTROLS_VccddqHi_OFF                   (27)
+  #define DDRCKECTL_CR_DDRCRCTLCONTROLS_VccddqHi_WID                   ( 1)
+  #define DDRCKECTL_CR_DDRCRCTLCONTROLS_VccddqHi_MSK                   (0x08000000)
+  #define DDRCKECTL_CR_DDRCRCTLCONTROLS_VccddqHi_MAX                   (0x00000001)
+  #define DDRCKECTL_CR_DDRCRCTLCONTROLS_VccddqHi_DEF                   (0x00000000)
+  #define DDRCKECTL_CR_DDRCRCTLCONTROLS_DllWeakLock_OFF                (28)
+  #define DDRCKECTL_CR_DDRCRCTLCONTROLS_DllWeakLock_WID                ( 1)
+  #define DDRCKECTL_CR_DDRCRCTLCONTROLS_DllWeakLock_MSK                (0x10000000)
+  #define DDRCKECTL_CR_DDRCRCTLCONTROLS_DllWeakLock_MAX                (0x00000001)
+  #define DDRCKECTL_CR_DDRCRCTLCONTROLS_DllWeakLock_DEF                (0x00000000)
+  #define DDRCKECTL_CR_DDRCRCTLCONTROLS_LPDDR_Mode_OFF                 (29)
+  #define DDRCKECTL_CR_DDRCRCTLCONTROLS_LPDDR_Mode_WID                 ( 1)
+  #define DDRCKECTL_CR_DDRCRCTLCONTROLS_LPDDR_Mode_MSK                 (0x20000000)
+  #define DDRCKECTL_CR_DDRCRCTLCONTROLS_LPDDR_Mode_MAX                 (0x00000001)
+  #define DDRCKECTL_CR_DDRCRCTLCONTROLS_LPDDR_Mode_DEF                 (0x00000000)
+  #define DDRCKECTL_CR_DDRCRCTLCONTROLS_LaDrvEnOvrd_OFF                (30)
+  #define DDRCKECTL_CR_DDRCRCTLCONTROLS_LaDrvEnOvrd_WID                ( 1)
+  #define DDRCKECTL_CR_DDRCRCTLCONTROLS_LaDrvEnOvrd_MSK                (0x40000000)
+  #define DDRCKECTL_CR_DDRCRCTLCONTROLS_LaDrvEnOvrd_MAX                (0x00000001)
+  #define DDRCKECTL_CR_DDRCRCTLCONTROLS_LaDrvEnOvrd_DEF                (0x00000000)
+  #define DDRCKECTL_CR_DDRCRCTLCONTROLS_LPDdrCAA_Dis_OFF               (31)
+  #define DDRCKECTL_CR_DDRCRCTLCONTROLS_LPDdrCAA_Dis_WID               ( 1)
+  #define DDRCKECTL_CR_DDRCRCTLCONTROLS_LPDdrCAA_Dis_MSK               (0x80000000)
+  #define DDRCKECTL_CR_DDRCRCTLCONTROLS_LPDdrCAA_Dis_MAX               (0x00000001)
+  #define DDRCKECTL_CR_DDRCRCTLCONTROLS_LPDdrCAA_Dis_DEF               (0x00000000)
+
+#define DDRCKECTL_CR_DDRCRCTLRANKSUSED_REG                           (0x00003820)
+  #define DDRCKECTL_CR_DDRCRCTLRANKSUSED_RankEn_OFF                    ( 0)
+  #define DDRCKECTL_CR_DDRCRCTLRANKSUSED_RankEn_WID                    ( 4)
+  #define DDRCKECTL_CR_DDRCRCTLRANKSUSED_RankEn_MSK                    (0x0000000F)
+  #define DDRCKECTL_CR_DDRCRCTLRANKSUSED_RankEn_MAX                    (0x0000000F)
+  #define DDRCKECTL_CR_DDRCRCTLRANKSUSED_RankEn_DEF                    (0x0000000F)
+  #define DDRCKECTL_CR_DDRCRCTLRANKSUSED_OdtDisable_OFF                ( 4)
+  #define DDRCKECTL_CR_DDRCRCTLRANKSUSED_OdtDisable_WID                ( 2)
+  #define DDRCKECTL_CR_DDRCRCTLRANKSUSED_OdtDisable_MSK                (0x00000030)
+  #define DDRCKECTL_CR_DDRCRCTLRANKSUSED_OdtDisable_MAX                (0x00000003)
+  #define DDRCKECTL_CR_DDRCRCTLRANKSUSED_OdtDisable_DEF                (0x00000000)
+  #define DDRCKECTL_CR_DDRCRCTLRANKSUSED_Spare_OFF                     ( 6)
+  #define DDRCKECTL_CR_DDRCRCTLRANKSUSED_Spare_WID                     (26)
+  #define DDRCKECTL_CR_DDRCRCTLRANKSUSED_Spare_MSK                     (0xFFFFFFC0)
+  #define DDRCKECTL_CR_DDRCRCTLRANKSUSED_Spare_MAX                     (0x03FFFFFF)
+  #define DDRCKECTL_CR_DDRCRCTLRANKSUSED_Spare_DEF                     (0x00000000)
+
+#define DDRCKECTL_CR_DLLPITESTANDADC_REG                             (0x00003824)
+  #define DDRCKECTL_CR_DLLPITESTANDADC_RunTest_OFF                     ( 0)
+  #define DDRCKECTL_CR_DLLPITESTANDADC_RunTest_WID                     ( 1)
+  #define DDRCKECTL_CR_DLLPITESTANDADC_RunTest_MSK                     (0x00000001)
+  #define DDRCKECTL_CR_DLLPITESTANDADC_RunTest_MAX                     (0x00000001)
+  #define DDRCKECTL_CR_DLLPITESTANDADC_RunTest_DEF                     (0x00000000)
+  #define DDRCKECTL_CR_DLLPITESTANDADC_Load_OFF                        ( 1)
+  #define DDRCKECTL_CR_DLLPITESTANDADC_Load_WID                        ( 1)
+  #define DDRCKECTL_CR_DLLPITESTANDADC_Load_MSK                        (0x00000002)
+  #define DDRCKECTL_CR_DLLPITESTANDADC_Load_MAX                        (0x00000001)
+  #define DDRCKECTL_CR_DLLPITESTANDADC_Load_DEF                        (0x00000000)
+  #define DDRCKECTL_CR_DLLPITESTANDADC_ModeHVM_OFF                     ( 2)
+  #define DDRCKECTL_CR_DLLPITESTANDADC_ModeHVM_WID                     ( 1)
+  #define DDRCKECTL_CR_DLLPITESTANDADC_ModeHVM_MSK                     (0x00000004)
+  #define DDRCKECTL_CR_DLLPITESTANDADC_ModeHVM_MAX                     (0x00000001)
+  #define DDRCKECTL_CR_DLLPITESTANDADC_ModeHVM_DEF                     (0x00000000)
+  #define DDRCKECTL_CR_DLLPITESTANDADC_ModeDV_OFF                      ( 3)
+  #define DDRCKECTL_CR_DLLPITESTANDADC_ModeDV_WID                      ( 1)
+  #define DDRCKECTL_CR_DLLPITESTANDADC_ModeDV_MSK                      (0x00000008)
+  #define DDRCKECTL_CR_DLLPITESTANDADC_ModeDV_MAX                      (0x00000001)
+  #define DDRCKECTL_CR_DLLPITESTANDADC_ModeDV_DEF                      (0x00000000)
+  #define DDRCKECTL_CR_DLLPITESTANDADC_ModeADC_OFF                     ( 4)
+  #define DDRCKECTL_CR_DLLPITESTANDADC_ModeADC_WID                     ( 1)
+  #define DDRCKECTL_CR_DLLPITESTANDADC_ModeADC_MSK                     (0x00000010)
+  #define DDRCKECTL_CR_DLLPITESTANDADC_ModeADC_MAX                     (0x00000001)
+  #define DDRCKECTL_CR_DLLPITESTANDADC_ModeADC_DEF                     (0x00000000)
+  #define DDRCKECTL_CR_DLLPITESTANDADC_LoadCount_OFF                   ( 5)
+  #define DDRCKECTL_CR_DLLPITESTANDADC_LoadCount_WID                   (10)
+  #define DDRCKECTL_CR_DLLPITESTANDADC_LoadCount_MSK                   (0x00007FE0)
+  #define DDRCKECTL_CR_DLLPITESTANDADC_LoadCount_MAX                   (0x000003FF)
+  #define DDRCKECTL_CR_DLLPITESTANDADC_CountStatus_OFF                 (15)
+  #define DDRCKECTL_CR_DLLPITESTANDADC_CountStatus_WID                 (10)
+  #define DDRCKECTL_CR_DLLPITESTANDADC_CountStatus_MSK                 (0x01FF8000)
+  #define DDRCKECTL_CR_DLLPITESTANDADC_CountStatus_MAX                 (0x000003FF)
+  #define DDRCKECTL_CR_DLLPITESTANDADC_CountStatus_DEF                 (0x00000000)
+  #define DDRCKECTL_CR_DLLPITESTANDADC_Spare_OFF                       (25)
+  #define DDRCKECTL_CR_DLLPITESTANDADC_Spare_WID                       ( 7)
+  #define DDRCKECTL_CR_DLLPITESTANDADC_Spare_MSK                       (0xFE000000)
+  #define DDRCKECTL_CR_DLLPITESTANDADC_Spare_MAX                       (0x0000007F)
+
+#define DDRCKECTLCH0_CR_DDRCRCTLCOMP_REG                             (0x00003410)
+  #define DDRCKECTLCH0_CR_DDRCRCTLCOMP_Scomp_OFF                       ( 0)
+  #define DDRCKECTLCH0_CR_DDRCRCTLCOMP_Scomp_WID                       ( 6)
+  #define DDRCKECTLCH0_CR_DDRCRCTLCOMP_Scomp_MSK                       (0x0000003F)
+  #define DDRCKECTLCH0_CR_DDRCRCTLCOMP_Scomp_MAX                       (0x0000003F)
+  #define DDRCKECTLCH0_CR_DDRCRCTLCOMP_Scomp_DEF                       (0x00000000)
+  #define DDRCKECTLCH0_CR_DDRCRCTLCOMP_TcoComp_OFF                     ( 6)
+  #define DDRCKECTLCH0_CR_DDRCRCTLCOMP_TcoComp_WID                     ( 6)
+  #define DDRCKECTLCH0_CR_DDRCRCTLCOMP_TcoComp_MSK                     (0x00000FC0)
+  #define DDRCKECTLCH0_CR_DDRCRCTLCOMP_TcoComp_MAX                     (0x0000003F)
+  #define DDRCKECTLCH0_CR_DDRCRCTLCOMP_TcoComp_DEF                     (0x00000000)
+  #define DDRCKECTLCH0_CR_DDRCRCTLCOMP_RcompDrvUp_OFF                  (12)
+  #define DDRCKECTLCH0_CR_DDRCRCTLCOMP_RcompDrvUp_WID                  ( 6)
+  #define DDRCKECTLCH0_CR_DDRCRCTLCOMP_RcompDrvUp_MSK                  (0x0003F000)
+  #define DDRCKECTLCH0_CR_DDRCRCTLCOMP_RcompDrvUp_MAX                  (0x0000003F)
+  #define DDRCKECTLCH0_CR_DDRCRCTLCOMP_RcompDrvUp_DEF                  (0x00000000)
+  #define DDRCKECTLCH0_CR_DDRCRCTLCOMP_RcompDrvDown_OFF                (18)
+  #define DDRCKECTLCH0_CR_DDRCRCTLCOMP_RcompDrvDown_WID                ( 6)
+  #define DDRCKECTLCH0_CR_DDRCRCTLCOMP_RcompDrvDown_MSK                (0x00FC0000)
+  #define DDRCKECTLCH0_CR_DDRCRCTLCOMP_RcompDrvDown_MAX                (0x0000003F)
+  #define DDRCKECTLCH0_CR_DDRCRCTLCOMP_RcompDrvDown_DEF                (0x00000000)
+  #define DDRCKECTLCH0_CR_DDRCRCTLCOMP_LsComp_OFF                      (24)
+  #define DDRCKECTLCH0_CR_DDRCRCTLCOMP_LsComp_WID                      ( 3)
+  #define DDRCKECTLCH0_CR_DDRCRCTLCOMP_LsComp_MSK                      (0x07000000)
+  #define DDRCKECTLCH0_CR_DDRCRCTLCOMP_LsComp_MAX                      (0x00000007)
+  #define DDRCKECTLCH0_CR_DDRCRCTLCOMP_LsComp_DEF                      (0x00000000)
+  #define DDRCKECTLCH0_CR_DDRCRCTLCOMP_Spare_OFF                       (27)
+  #define DDRCKECTLCH0_CR_DDRCRCTLCOMP_Spare_WID                       ( 5)
+  #define DDRCKECTLCH0_CR_DDRCRCTLCOMP_Spare_MSK                       (0xF8000000)
+  #define DDRCKECTLCH0_CR_DDRCRCTLCOMP_Spare_MAX                       (0x0000001F)
+  #define DDRCKECTLCH0_CR_DDRCRCTLCOMP_Spare_DEF                       (0x00000000)
+
+#define DDRCKECTLCH0_CR_DDRCRCTLCOMPOFFSET_REG                       (0x00003414)
+  #define DDRCKECTLCH0_CR_DDRCRCTLCOMPOFFSET_ScompOffset_OFF           ( 0)
+  #define DDRCKECTLCH0_CR_DDRCRCTLCOMPOFFSET_ScompOffset_WID           ( 5)
+  #define DDRCKECTLCH0_CR_DDRCRCTLCOMPOFFSET_ScompOffset_MSK           (0x0000001F)
+  #define DDRCKECTLCH0_CR_DDRCRCTLCOMPOFFSET_ScompOffset_MAX           (0x0000001F)
+  #define DDRCKECTLCH0_CR_DDRCRCTLCOMPOFFSET_ScompOffset_DEF           (0x00000000)
+  #define DDRCKECTLCH0_CR_DDRCRCTLCOMPOFFSET_TcoCompOffset_OFF         ( 5)
+  #define DDRCKECTLCH0_CR_DDRCRCTLCOMPOFFSET_TcoCompOffset_WID         ( 4)
+  #define DDRCKECTLCH0_CR_DDRCRCTLCOMPOFFSET_TcoCompOffset_MSK         (0x000001E0)
+  #define DDRCKECTLCH0_CR_DDRCRCTLCOMPOFFSET_TcoCompOffset_MAX         (0x0000000F)
+  #define DDRCKECTLCH0_CR_DDRCRCTLCOMPOFFSET_TcoCompOffset_DEF         (0x00000000)
+  #define DDRCKECTLCH0_CR_DDRCRCTLCOMPOFFSET_RcompDrvUpOffset_OFF      ( 9)
+  #define DDRCKECTLCH0_CR_DDRCRCTLCOMPOFFSET_RcompDrvUpOffset_WID      ( 4)
+  #define DDRCKECTLCH0_CR_DDRCRCTLCOMPOFFSET_RcompDrvUpOffset_MSK      (0x00001E00)
+  #define DDRCKECTLCH0_CR_DDRCRCTLCOMPOFFSET_RcompDrvUpOffset_MAX      (0x0000000F)
+  #define DDRCKECTLCH0_CR_DDRCRCTLCOMPOFFSET_RcompDrvUpOffset_DEF      (0x00000000)
+  #define DDRCKECTLCH0_CR_DDRCRCTLCOMPOFFSET_RcompDrvDownOffset_OFF    (13)
+  #define DDRCKECTLCH0_CR_DDRCRCTLCOMPOFFSET_RcompDrvDownOffset_WID    ( 4)
+  #define DDRCKECTLCH0_CR_DDRCRCTLCOMPOFFSET_RcompDrvDownOffset_MSK    (0x0001E000)
+  #define DDRCKECTLCH0_CR_DDRCRCTLCOMPOFFSET_RcompDrvDownOffset_MAX    (0x0000000F)
+  #define DDRCKECTLCH0_CR_DDRCRCTLCOMPOFFSET_RcompDrvDownOffset_DEF    (0x00000000)
+  #define DDRCKECTLCH0_CR_DDRCRCTLCOMPOFFSET_Spare_OFF                 (17)
+  #define DDRCKECTLCH0_CR_DDRCRCTLCOMPOFFSET_Spare_WID                 (15)
+  #define DDRCKECTLCH0_CR_DDRCRCTLCOMPOFFSET_Spare_MSK                 (0xFFFE0000)
+  #define DDRCKECTLCH0_CR_DDRCRCTLCOMPOFFSET_Spare_MAX                 (0x00007FFF)
+  #define DDRCKECTLCH0_CR_DDRCRCTLCOMPOFFSET_Spare_DEF                 (0x00000000)
+
+#define DDRCKECTLCH0_CR_DDRCRCTLPICODING_REG                         (0x00003418)
+  #define DDRCKECTLCH0_CR_DDRCRCTLPICODING_CtlPiCode0_OFF              ( 0)
+  #define DDRCKECTLCH0_CR_DDRCRCTLPICODING_CtlPiCode0_WID              ( 7)
+  #define DDRCKECTLCH0_CR_DDRCRCTLPICODING_CtlPiCode0_MSK              (0x0000007F)
+  #define DDRCKECTLCH0_CR_DDRCRCTLPICODING_CtlPiCode0_MAX              (0x0000007F)
+  #define DDRCKECTLCH0_CR_DDRCRCTLPICODING_CtlPiCode0_DEF              (0x00000000)
+  #define DDRCKECTLCH0_CR_DDRCRCTLPICODING_CtlPiCode1_OFF              ( 7)
+  #define DDRCKECTLCH0_CR_DDRCRCTLPICODING_CtlPiCode1_WID              ( 7)
+  #define DDRCKECTLCH0_CR_DDRCRCTLPICODING_CtlPiCode1_MSK              (0x00003F80)
+  #define DDRCKECTLCH0_CR_DDRCRCTLPICODING_CtlPiCode1_MAX              (0x0000007F)
+  #define DDRCKECTLCH0_CR_DDRCRCTLPICODING_CtlPiCode1_DEF              (0x00000000)
+  #define DDRCKECTLCH0_CR_DDRCRCTLPICODING_CtlPiCode2_OFF              (14)
+  #define DDRCKECTLCH0_CR_DDRCRCTLPICODING_CtlPiCode2_WID              ( 7)
+  #define DDRCKECTLCH0_CR_DDRCRCTLPICODING_CtlPiCode2_MSK              (0x001FC000)
+  #define DDRCKECTLCH0_CR_DDRCRCTLPICODING_CtlPiCode2_MAX              (0x0000007F)
+  #define DDRCKECTLCH0_CR_DDRCRCTLPICODING_CtlPiCode2_DEF              (0x00000000)
+  #define DDRCKECTLCH0_CR_DDRCRCTLPICODING_CtlPiCode3_OFF              (21)
+  #define DDRCKECTLCH0_CR_DDRCRCTLPICODING_CtlPiCode3_WID              ( 7)
+  #define DDRCKECTLCH0_CR_DDRCRCTLPICODING_CtlPiCode3_MSK              (0x0FE00000)
+  #define DDRCKECTLCH0_CR_DDRCRCTLPICODING_CtlPiCode3_MAX              (0x0000007F)
+  #define DDRCKECTLCH0_CR_DDRCRCTLPICODING_CtlPiCode3_DEF              (0x00000000)
+  #define DDRCKECTLCH0_CR_DDRCRCTLPICODING_CtlXoverEnable_OFF          (28)
+  #define DDRCKECTLCH0_CR_DDRCRCTLPICODING_CtlXoverEnable_WID          ( 1)
+  #define DDRCKECTLCH0_CR_DDRCRCTLPICODING_CtlXoverEnable_MSK          (0x10000000)
+  #define DDRCKECTLCH0_CR_DDRCRCTLPICODING_CtlXoverEnable_MAX          (0x00000001)
+  #define DDRCKECTLCH0_CR_DDRCRCTLPICODING_CtlXoverEnable_DEF          (0x00000000)
+  #define DDRCKECTLCH0_CR_DDRCRCTLPICODING_Spare_OFF                   (29)
+  #define DDRCKECTLCH0_CR_DDRCRCTLPICODING_Spare_WID                   ( 3)
+  #define DDRCKECTLCH0_CR_DDRCRCTLPICODING_Spare_MSK                   (0xE0000000)
+  #define DDRCKECTLCH0_CR_DDRCRCTLPICODING_Spare_MAX                   (0x00000007)
+  #define DDRCKECTLCH0_CR_DDRCRCTLPICODING_Spare_DEF                   (0x00000000)
+
+#define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_REG                         (0x0000341C)
+  #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_RefPi_OFF                   ( 0)
+  #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_RefPi_WID                   ( 4)
+  #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_RefPi_MSK                   (0x0000000F)
+  #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_RefPi_MAX                   (0x0000000F)
+  #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_RefPi_DEF                   (0x00000000)
+  #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_DllMask_OFF                 ( 4)
+  #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_DllMask_WID                 ( 2)
+  #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_DllMask_MSK                 (0x00000030)
+  #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_DllMask_MAX                 (0x00000003)
+  #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_DllMask_DEF                 (0x00000000)
+  #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_DllRsvd1_OFF                ( 6)
+  #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_DllRsvd1_WID                ( 1)
+  #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_DllRsvd1_MSK                (0x00000040)
+  #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_DllRsvd1_MAX                (0x00000001)
+  #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_DllRsvd1_DEF                (0x00000000)
+  #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_TxOn_OFF                    ( 7)
+  #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_TxOn_WID                    ( 1)
+  #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_TxOn_MSK                    (0x00000080)
+  #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_TxOn_MAX                    (0x00000001)
+  #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_TxOn_DEF                    (0x00000000)
+  #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_IntClkOn_OFF                ( 8)
+  #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_IntClkOn_WID                ( 1)
+  #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_IntClkOn_MSK                (0x00000100)
+  #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_IntClkOn_MAX                (0x00000001)
+  #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_IntClkOn_DEF                (0x00000000)
+  #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_RepClkOn_OFF                ( 9)
+  #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_RepClkOn_WID                ( 1)
+  #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_RepClkOn_MSK                (0x00000200)
+  #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_RepClkOn_MAX                (0x00000001)
+  #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_RepClkOn_DEF                (0x00000000)
+  #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_IOLBCtl_OFF                 (10)
+  #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_IOLBCtl_WID                 ( 2)
+  #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_IOLBCtl_MSK                 (0x00000C00)
+  #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_IOLBCtl_MAX                 (0x00000003)
+  #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_IOLBCtl_DEF                 (0x00000000)
+  #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_OdtMode_OFF                 (12)
+  #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_OdtMode_WID                 ( 1)
+  #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_OdtMode_MSK                 (0x00001000)
+  #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_OdtMode_MAX                 (0x00000001)
+  #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_OdtMode_DEF                 (0x00000000)
+  #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_CmdTxEq_OFF                 (13)
+  #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_CmdTxEq_WID                 ( 2)
+  #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_CmdTxEq_MSK                 (0x00006000)
+  #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_CmdTxEq_MAX                 (0x00000003)
+  #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_CmdTxEq_DEF                 (0x00000000)
+  #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_EarlyWeakDrive_OFF          (15)
+  #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_EarlyWeakDrive_WID          ( 2)
+  #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_EarlyWeakDrive_MSK          (0x00018000)
+  #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_EarlyWeakDrive_MAX          (0x00000003)
+  #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_EarlyWeakDrive_DEF          (0x00000000)
+  #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_CtlTxEq_OFF                 (17)
+  #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_CtlTxEq_WID                 ( 2)
+  #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_CtlTxEq_MSK                 (0x00060000)
+  #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_CtlTxEq_MAX                 (0x00000003)
+  #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_CtlTxEq_DEF                 (0x00000000)
+  #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_CtlSRDrv_OFF                (19)
+  #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_CtlSRDrv_WID                ( 2)
+  #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_CtlSRDrv_MSK                (0x00180000)
+  #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_CtlSRDrv_MAX                (0x00000003)
+  #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_CtlSRDrv_DEF                (0x00000000)
+  #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_RxVref_OFF                  (21)
+  #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_RxVref_WID                  ( 6)
+  #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_RxVref_MSK                  (0x07E00000)
+  #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_RxVref_MAX                  (0x0000003F)
+  #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_RxVref_DEF                  (0x00000000)
+  #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_VccddqHi_OFF                (27)
+  #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_VccddqHi_WID                ( 1)
+  #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_VccddqHi_MSK                (0x08000000)
+  #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_VccddqHi_MAX                (0x00000001)
+  #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_VccddqHi_DEF                (0x00000000)
+  #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_DllWeakLock_OFF             (28)
+  #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_DllWeakLock_WID             ( 1)
+  #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_DllWeakLock_MSK             (0x10000000)
+  #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_DllWeakLock_MAX             (0x00000001)
+  #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_DllWeakLock_DEF             (0x00000000)
+  #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_LPDDR_Mode_OFF              (29)
+  #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_LPDDR_Mode_WID              ( 1)
+  #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_LPDDR_Mode_MSK              (0x20000000)
+  #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_LPDDR_Mode_MAX              (0x00000001)
+  #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_LPDDR_Mode_DEF              (0x00000000)
+  #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_LaDrvEnOvrd_OFF             (30)
+  #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_LaDrvEnOvrd_WID             ( 1)
+  #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_LaDrvEnOvrd_MSK             (0x40000000)
+  #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_LaDrvEnOvrd_MAX             (0x00000001)
+  #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_LaDrvEnOvrd_DEF             (0x00000000)
+  #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_LPDdrCAA_Dis_OFF            (31)
+  #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_LPDdrCAA_Dis_WID            ( 1)
+  #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_LPDdrCAA_Dis_MSK            (0x80000000)
+  #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_LPDdrCAA_Dis_MAX            (0x00000001)
+  #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_LPDdrCAA_Dis_DEF            (0x00000000)
+
+#define DDRCKECTLCH0_CR_DDRCRCTLRANKSUSED_REG                        (0x00003420)
+  #define DDRCKECTLCH0_CR_DDRCRCTLRANKSUSED_RankEn_OFF                 ( 0)
+  #define DDRCKECTLCH0_CR_DDRCRCTLRANKSUSED_RankEn_WID                 ( 4)
+  #define DDRCKECTLCH0_CR_DDRCRCTLRANKSUSED_RankEn_MSK                 (0x0000000F)
+  #define DDRCKECTLCH0_CR_DDRCRCTLRANKSUSED_RankEn_MAX                 (0x0000000F)
+  #define DDRCKECTLCH0_CR_DDRCRCTLRANKSUSED_RankEn_DEF                 (0x0000000F)
+  #define DDRCKECTLCH0_CR_DDRCRCTLRANKSUSED_OdtDisable_OFF             ( 4)
+  #define DDRCKECTLCH0_CR_DDRCRCTLRANKSUSED_OdtDisable_WID             ( 2)
+  #define DDRCKECTLCH0_CR_DDRCRCTLRANKSUSED_OdtDisable_MSK             (0x00000030)
+  #define DDRCKECTLCH0_CR_DDRCRCTLRANKSUSED_OdtDisable_MAX             (0x00000003)
+  #define DDRCKECTLCH0_CR_DDRCRCTLRANKSUSED_OdtDisable_DEF             (0x00000000)
+  #define DDRCKECTLCH0_CR_DDRCRCTLRANKSUSED_Spare_OFF                  ( 6)
+  #define DDRCKECTLCH0_CR_DDRCRCTLRANKSUSED_Spare_WID                  (26)
+  #define DDRCKECTLCH0_CR_DDRCRCTLRANKSUSED_Spare_MSK                  (0xFFFFFFC0)
+  #define DDRCKECTLCH0_CR_DDRCRCTLRANKSUSED_Spare_MAX                  (0x03FFFFFF)
+  #define DDRCKECTLCH0_CR_DDRCRCTLRANKSUSED_Spare_DEF                  (0x00000000)
+
+#define DDRCKECTLCH0_CR_DLLPITESTANDADC_REG                          (0x00003424)
+  #define DDRCKECTLCH0_CR_DLLPITESTANDADC_RunTest_OFF                  ( 0)
+  #define DDRCKECTLCH0_CR_DLLPITESTANDADC_RunTest_WID                  ( 1)
+  #define DDRCKECTLCH0_CR_DLLPITESTANDADC_RunTest_MSK                  (0x00000001)
+  #define DDRCKECTLCH0_CR_DLLPITESTANDADC_RunTest_MAX                  (0x00000001)
+  #define DDRCKECTLCH0_CR_DLLPITESTANDADC_RunTest_DEF                  (0x00000000)
+  #define DDRCKECTLCH0_CR_DLLPITESTANDADC_Load_OFF                     ( 1)
+  #define DDRCKECTLCH0_CR_DLLPITESTANDADC_Load_WID                     ( 1)
+  #define DDRCKECTLCH0_CR_DLLPITESTANDADC_Load_MSK                     (0x00000002)
+  #define DDRCKECTLCH0_CR_DLLPITESTANDADC_Load_MAX                     (0x00000001)
+  #define DDRCKECTLCH0_CR_DLLPITESTANDADC_Load_DEF                     (0x00000000)
+  #define DDRCKECTLCH0_CR_DLLPITESTANDADC_ModeHVM_OFF                  ( 2)
+  #define DDRCKECTLCH0_CR_DLLPITESTANDADC_ModeHVM_WID                  ( 1)
+  #define DDRCKECTLCH0_CR_DLLPITESTANDADC_ModeHVM_MSK                  (0x00000004)
+  #define DDRCKECTLCH0_CR_DLLPITESTANDADC_ModeHVM_MAX                  (0x00000001)
+  #define DDRCKECTLCH0_CR_DLLPITESTANDADC_ModeHVM_DEF                  (0x00000000)
+  #define DDRCKECTLCH0_CR_DLLPITESTANDADC_ModeDV_OFF                   ( 3)
+  #define DDRCKECTLCH0_CR_DLLPITESTANDADC_ModeDV_WID                   ( 1)
+  #define DDRCKECTLCH0_CR_DLLPITESTANDADC_ModeDV_MSK                   (0x00000008)
+  #define DDRCKECTLCH0_CR_DLLPITESTANDADC_ModeDV_MAX                   (0x00000001)
+  #define DDRCKECTLCH0_CR_DLLPITESTANDADC_ModeDV_DEF                   (0x00000000)
+  #define DDRCKECTLCH0_CR_DLLPITESTANDADC_ModeADC_OFF                  ( 4)
+  #define DDRCKECTLCH0_CR_DLLPITESTANDADC_ModeADC_WID                  ( 1)
+  #define DDRCKECTLCH0_CR_DLLPITESTANDADC_ModeADC_MSK                  (0x00000010)
+  #define DDRCKECTLCH0_CR_DLLPITESTANDADC_ModeADC_MAX                  (0x00000001)
+  #define DDRCKECTLCH0_CR_DLLPITESTANDADC_ModeADC_DEF                  (0x00000000)
+  #define DDRCKECTLCH0_CR_DLLPITESTANDADC_LoadCount_OFF                ( 5)
+  #define DDRCKECTLCH0_CR_DLLPITESTANDADC_LoadCount_WID                (10)
+  #define DDRCKECTLCH0_CR_DLLPITESTANDADC_LoadCount_MSK                (0x00007FE0)
+  #define DDRCKECTLCH0_CR_DLLPITESTANDADC_LoadCount_MAX                (0x000003FF)
+  #define DDRCKECTLCH0_CR_DLLPITESTANDADC_CountStatus_OFF              (15)
+  #define DDRCKECTLCH0_CR_DLLPITESTANDADC_CountStatus_WID              (10)
+  #define DDRCKECTLCH0_CR_DLLPITESTANDADC_CountStatus_MSK              (0x01FF8000)
+  #define DDRCKECTLCH0_CR_DLLPITESTANDADC_CountStatus_MAX              (0x000003FF)
+  #define DDRCKECTLCH0_CR_DLLPITESTANDADC_CountStatus_DEF              (0x00000000)
+  #define DDRCKECTLCH0_CR_DLLPITESTANDADC_Spare_OFF                    (25)
+  #define DDRCKECTLCH0_CR_DLLPITESTANDADC_Spare_WID                    ( 7)
+  #define DDRCKECTLCH0_CR_DLLPITESTANDADC_Spare_MSK                    (0xFE000000)
+  #define DDRCKECTLCH0_CR_DLLPITESTANDADC_Spare_MAX                    (0x0000007F)
+
+#define DDRCKECTLCH1_CR_DDRCRCTLCOMP_REG                             (0x00003510)
+  #define DDRCKECTLCH1_CR_DDRCRCTLCOMP_Scomp_OFF                       ( 0)
+  #define DDRCKECTLCH1_CR_DDRCRCTLCOMP_Scomp_WID                       ( 6)
+  #define DDRCKECTLCH1_CR_DDRCRCTLCOMP_Scomp_MSK                       (0x0000003F)
+  #define DDRCKECTLCH1_CR_DDRCRCTLCOMP_Scomp_MAX                       (0x0000003F)
+  #define DDRCKECTLCH1_CR_DDRCRCTLCOMP_Scomp_DEF                       (0x00000000)
+  #define DDRCKECTLCH1_CR_DDRCRCTLCOMP_TcoComp_OFF                     ( 6)
+  #define DDRCKECTLCH1_CR_DDRCRCTLCOMP_TcoComp_WID                     ( 6)
+  #define DDRCKECTLCH1_CR_DDRCRCTLCOMP_TcoComp_MSK                     (0x00000FC0)
+  #define DDRCKECTLCH1_CR_DDRCRCTLCOMP_TcoComp_MAX                     (0x0000003F)
+  #define DDRCKECTLCH1_CR_DDRCRCTLCOMP_TcoComp_DEF                     (0x00000000)
+  #define DDRCKECTLCH1_CR_DDRCRCTLCOMP_RcompDrvUp_OFF                  (12)
+  #define DDRCKECTLCH1_CR_DDRCRCTLCOMP_RcompDrvUp_WID                  ( 6)
+  #define DDRCKECTLCH1_CR_DDRCRCTLCOMP_RcompDrvUp_MSK                  (0x0003F000)
+  #define DDRCKECTLCH1_CR_DDRCRCTLCOMP_RcompDrvUp_MAX                  (0x0000003F)
+  #define DDRCKECTLCH1_CR_DDRCRCTLCOMP_RcompDrvUp_DEF                  (0x00000000)
+  #define DDRCKECTLCH1_CR_DDRCRCTLCOMP_RcompDrvDown_OFF                (18)
+  #define DDRCKECTLCH1_CR_DDRCRCTLCOMP_RcompDrvDown_WID                ( 6)
+  #define DDRCKECTLCH1_CR_DDRCRCTLCOMP_RcompDrvDown_MSK                (0x00FC0000)
+  #define DDRCKECTLCH1_CR_DDRCRCTLCOMP_RcompDrvDown_MAX                (0x0000003F)
+  #define DDRCKECTLCH1_CR_DDRCRCTLCOMP_RcompDrvDown_DEF                (0x00000000)
+  #define DDRCKECTLCH1_CR_DDRCRCTLCOMP_LsComp_OFF                      (24)
+  #define DDRCKECTLCH1_CR_DDRCRCTLCOMP_LsComp_WID                      ( 3)
+  #define DDRCKECTLCH1_CR_DDRCRCTLCOMP_LsComp_MSK                      (0x07000000)
+  #define DDRCKECTLCH1_CR_DDRCRCTLCOMP_LsComp_MAX                      (0x00000007)
+  #define DDRCKECTLCH1_CR_DDRCRCTLCOMP_LsComp_DEF                      (0x00000000)
+  #define DDRCKECTLCH1_CR_DDRCRCTLCOMP_Spare_OFF                       (27)
+  #define DDRCKECTLCH1_CR_DDRCRCTLCOMP_Spare_WID                       ( 5)
+  #define DDRCKECTLCH1_CR_DDRCRCTLCOMP_Spare_MSK                       (0xF8000000)
+  #define DDRCKECTLCH1_CR_DDRCRCTLCOMP_Spare_MAX                       (0x0000001F)
+  #define DDRCKECTLCH1_CR_DDRCRCTLCOMP_Spare_DEF                       (0x00000000)
+
+#define DDRCKECTLCH1_CR_DDRCRCTLCOMPOFFSET_REG                       (0x00003514)
+  #define DDRCKECTLCH1_CR_DDRCRCTLCOMPOFFSET_ScompOffset_OFF           ( 0)
+  #define DDRCKECTLCH1_CR_DDRCRCTLCOMPOFFSET_ScompOffset_WID           ( 5)
+  #define DDRCKECTLCH1_CR_DDRCRCTLCOMPOFFSET_ScompOffset_MSK           (0x0000001F)
+  #define DDRCKECTLCH1_CR_DDRCRCTLCOMPOFFSET_ScompOffset_MAX           (0x0000001F)
+  #define DDRCKECTLCH1_CR_DDRCRCTLCOMPOFFSET_ScompOffset_DEF           (0x00000000)
+  #define DDRCKECTLCH1_CR_DDRCRCTLCOMPOFFSET_TcoCompOffset_OFF         ( 5)
+  #define DDRCKECTLCH1_CR_DDRCRCTLCOMPOFFSET_TcoCompOffset_WID         ( 4)
+  #define DDRCKECTLCH1_CR_DDRCRCTLCOMPOFFSET_TcoCompOffset_MSK         (0x000001E0)
+  #define DDRCKECTLCH1_CR_DDRCRCTLCOMPOFFSET_TcoCompOffset_MAX         (0x0000000F)
+  #define DDRCKECTLCH1_CR_DDRCRCTLCOMPOFFSET_TcoCompOffset_DEF         (0x00000000)
+  #define DDRCKECTLCH1_CR_DDRCRCTLCOMPOFFSET_RcompDrvUpOffset_OFF      ( 9)
+  #define DDRCKECTLCH1_CR_DDRCRCTLCOMPOFFSET_RcompDrvUpOffset_WID      ( 4)
+  #define DDRCKECTLCH1_CR_DDRCRCTLCOMPOFFSET_RcompDrvUpOffset_MSK      (0x00001E00)
+  #define DDRCKECTLCH1_CR_DDRCRCTLCOMPOFFSET_RcompDrvUpOffset_MAX      (0x0000000F)
+  #define DDRCKECTLCH1_CR_DDRCRCTLCOMPOFFSET_RcompDrvUpOffset_DEF      (0x00000000)
+  #define DDRCKECTLCH1_CR_DDRCRCTLCOMPOFFSET_RcompDrvDownOffset_OFF    (13)
+  #define DDRCKECTLCH1_CR_DDRCRCTLCOMPOFFSET_RcompDrvDownOffset_WID    ( 4)
+  #define DDRCKECTLCH1_CR_DDRCRCTLCOMPOFFSET_RcompDrvDownOffset_MSK    (0x0001E000)
+  #define DDRCKECTLCH1_CR_DDRCRCTLCOMPOFFSET_RcompDrvDownOffset_MAX    (0x0000000F)
+  #define DDRCKECTLCH1_CR_DDRCRCTLCOMPOFFSET_RcompDrvDownOffset_DEF    (0x00000000)
+  #define DDRCKECTLCH1_CR_DDRCRCTLCOMPOFFSET_Spare_OFF                 (17)
+  #define DDRCKECTLCH1_CR_DDRCRCTLCOMPOFFSET_Spare_WID                 (15)
+  #define DDRCKECTLCH1_CR_DDRCRCTLCOMPOFFSET_Spare_MSK                 (0xFFFE0000)
+  #define DDRCKECTLCH1_CR_DDRCRCTLCOMPOFFSET_Spare_MAX                 (0x00007FFF)
+  #define DDRCKECTLCH1_CR_DDRCRCTLCOMPOFFSET_Spare_DEF                 (0x00000000)
+
+#define DDRCKECTLCH1_CR_DDRCRCTLPICODING_REG                         (0x00003518)
+  #define DDRCKECTLCH1_CR_DDRCRCTLPICODING_CtlPiCode0_OFF              ( 0)
+  #define DDRCKECTLCH1_CR_DDRCRCTLPICODING_CtlPiCode0_WID              ( 7)
+  #define DDRCKECTLCH1_CR_DDRCRCTLPICODING_CtlPiCode0_MSK              (0x0000007F)
+  #define DDRCKECTLCH1_CR_DDRCRCTLPICODING_CtlPiCode0_MAX              (0x0000007F)
+  #define DDRCKECTLCH1_CR_DDRCRCTLPICODING_CtlPiCode0_DEF              (0x00000000)
+  #define DDRCKECTLCH1_CR_DDRCRCTLPICODING_CtlPiCode1_OFF              ( 7)
+  #define DDRCKECTLCH1_CR_DDRCRCTLPICODING_CtlPiCode1_WID              ( 7)
+  #define DDRCKECTLCH1_CR_DDRCRCTLPICODING_CtlPiCode1_MSK              (0x00003F80)
+  #define DDRCKECTLCH1_CR_DDRCRCTLPICODING_CtlPiCode1_MAX              (0x0000007F)
+  #define DDRCKECTLCH1_CR_DDRCRCTLPICODING_CtlPiCode1_DEF              (0x00000000)
+  #define DDRCKECTLCH1_CR_DDRCRCTLPICODING_CtlPiCode2_OFF              (14)
+  #define DDRCKECTLCH1_CR_DDRCRCTLPICODING_CtlPiCode2_WID              ( 7)
+  #define DDRCKECTLCH1_CR_DDRCRCTLPICODING_CtlPiCode2_MSK              (0x001FC000)
+  #define DDRCKECTLCH1_CR_DDRCRCTLPICODING_CtlPiCode2_MAX              (0x0000007F)
+  #define DDRCKECTLCH1_CR_DDRCRCTLPICODING_CtlPiCode2_DEF              (0x00000000)
+  #define DDRCKECTLCH1_CR_DDRCRCTLPICODING_CtlPiCode3_OFF              (21)
+  #define DDRCKECTLCH1_CR_DDRCRCTLPICODING_CtlPiCode3_WID              ( 7)
+  #define DDRCKECTLCH1_CR_DDRCRCTLPICODING_CtlPiCode3_MSK              (0x0FE00000)
+  #define DDRCKECTLCH1_CR_DDRCRCTLPICODING_CtlPiCode3_MAX              (0x0000007F)
+  #define DDRCKECTLCH1_CR_DDRCRCTLPICODING_CtlPiCode3_DEF              (0x00000000)
+  #define DDRCKECTLCH1_CR_DDRCRCTLPICODING_CtlXoverEnable_OFF          (28)
+  #define DDRCKECTLCH1_CR_DDRCRCTLPICODING_CtlXoverEnable_WID          ( 1)
+  #define DDRCKECTLCH1_CR_DDRCRCTLPICODING_CtlXoverEnable_MSK          (0x10000000)
+  #define DDRCKECTLCH1_CR_DDRCRCTLPICODING_CtlXoverEnable_MAX          (0x00000001)
+  #define DDRCKECTLCH1_CR_DDRCRCTLPICODING_CtlXoverEnable_DEF          (0x00000000)
+  #define DDRCKECTLCH1_CR_DDRCRCTLPICODING_Spare_OFF                   (29)
+  #define DDRCKECTLCH1_CR_DDRCRCTLPICODING_Spare_WID                   ( 3)
+  #define DDRCKECTLCH1_CR_DDRCRCTLPICODING_Spare_MSK                   (0xE0000000)
+  #define DDRCKECTLCH1_CR_DDRCRCTLPICODING_Spare_MAX                   (0x00000007)
+  #define DDRCKECTLCH1_CR_DDRCRCTLPICODING_Spare_DEF                   (0x00000000)
+
+#define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_REG                         (0x0000351C)
+  #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_RefPi_OFF                   ( 0)
+  #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_RefPi_WID                   ( 4)
+  #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_RefPi_MSK                   (0x0000000F)
+  #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_RefPi_MAX                   (0x0000000F)
+  #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_RefPi_DEF                   (0x00000000)
+  #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_DllMask_OFF                 ( 4)
+  #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_DllMask_WID                 ( 2)
+  #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_DllMask_MSK                 (0x00000030)
+  #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_DllMask_MAX                 (0x00000003)
+  #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_DllMask_DEF                 (0x00000000)
+  #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_DllRsvd1_OFF                ( 6)
+  #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_DllRsvd1_WID                ( 1)
+  #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_DllRsvd1_MSK                (0x00000040)
+  #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_DllRsvd1_MAX                (0x00000001)
+  #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_DllRsvd1_DEF                (0x00000000)
+  #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_TxOn_OFF                    ( 7)
+  #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_TxOn_WID                    ( 1)
+  #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_TxOn_MSK                    (0x00000080)
+  #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_TxOn_MAX                    (0x00000001)
+  #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_TxOn_DEF                    (0x00000000)
+  #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_IntClkOn_OFF                ( 8)
+  #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_IntClkOn_WID                ( 1)
+  #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_IntClkOn_MSK                (0x00000100)
+  #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_IntClkOn_MAX                (0x00000001)
+  #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_IntClkOn_DEF                (0x00000000)
+  #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_RepClkOn_OFF                ( 9)
+  #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_RepClkOn_WID                ( 1)
+  #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_RepClkOn_MSK                (0x00000200)
+  #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_RepClkOn_MAX                (0x00000001)
+  #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_RepClkOn_DEF                (0x00000000)
+  #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_IOLBCtl_OFF                 (10)
+  #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_IOLBCtl_WID                 ( 2)
+  #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_IOLBCtl_MSK                 (0x00000C00)
+  #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_IOLBCtl_MAX                 (0x00000003)
+  #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_IOLBCtl_DEF                 (0x00000000)
+  #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_OdtMode_OFF                 (12)
+  #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_OdtMode_WID                 ( 1)
+  #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_OdtMode_MSK                 (0x00001000)
+  #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_OdtMode_MAX                 (0x00000001)
+  #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_OdtMode_DEF                 (0x00000000)
+  #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_CmdTxEq_OFF                 (13)
+  #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_CmdTxEq_WID                 ( 2)
+  #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_CmdTxEq_MSK                 (0x00006000)
+  #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_CmdTxEq_MAX                 (0x00000003)
+  #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_CmdTxEq_DEF                 (0x00000000)
+  #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_EarlyWeakDrive_OFF          (15)
+  #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_EarlyWeakDrive_WID          ( 2)
+  #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_EarlyWeakDrive_MSK          (0x00018000)
+  #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_EarlyWeakDrive_MAX          (0x00000003)
+  #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_EarlyWeakDrive_DEF          (0x00000000)
+  #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_CtlTxEq_OFF                 (17)
+  #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_CtlTxEq_WID                 ( 2)
+  #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_CtlTxEq_MSK                 (0x00060000)
+  #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_CtlTxEq_MAX                 (0x00000003)
+  #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_CtlTxEq_DEF                 (0x00000000)
+  #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_CtlSRDrv_OFF                (19)
+  #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_CtlSRDrv_WID                ( 2)
+  #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_CtlSRDrv_MSK                (0x00180000)
+  #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_CtlSRDrv_MAX                (0x00000003)
+  #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_CtlSRDrv_DEF                (0x00000000)
+  #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_RxVref_OFF                  (21)
+  #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_RxVref_WID                  ( 6)
+  #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_RxVref_MSK                  (0x07E00000)
+  #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_RxVref_MAX                  (0x0000003F)
+  #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_RxVref_DEF                  (0x00000000)
+  #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_VccddqHi_OFF                (27)
+  #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_VccddqHi_WID                ( 1)
+  #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_VccddqHi_MSK                (0x08000000)
+  #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_VccddqHi_MAX                (0x00000001)
+  #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_VccddqHi_DEF                (0x00000000)
+  #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_DllWeakLock_OFF             (28)
+  #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_DllWeakLock_WID             ( 1)
+  #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_DllWeakLock_MSK             (0x10000000)
+  #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_DllWeakLock_MAX             (0x00000001)
+  #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_DllWeakLock_DEF             (0x00000000)
+  #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_LPDDR_Mode_OFF              (29)
+  #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_LPDDR_Mode_WID              ( 1)
+  #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_LPDDR_Mode_MSK              (0x20000000)
+  #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_LPDDR_Mode_MAX              (0x00000001)
+  #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_LPDDR_Mode_DEF              (0x00000000)
+  #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_LaDrvEnOvrd_OFF             (30)
+  #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_LaDrvEnOvrd_WID             ( 1)
+  #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_LaDrvEnOvrd_MSK             (0x40000000)
+  #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_LaDrvEnOvrd_MAX             (0x00000001)
+  #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_LaDrvEnOvrd_DEF             (0x00000000)
+  #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_LPDdrCAA_Dis_OFF            (31)
+  #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_LPDdrCAA_Dis_WID            ( 1)
+  #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_LPDdrCAA_Dis_MSK            (0x80000000)
+  #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_LPDdrCAA_Dis_MAX            (0x00000001)
+  #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_LPDdrCAA_Dis_DEF            (0x00000000)
+
+#define DDRCKECTLCH1_CR_DDRCRCTLRANKSUSED_REG                        (0x00003520)
+  #define DDRCKECTLCH1_CR_DDRCRCTLRANKSUSED_RankEn_OFF                 ( 0)
+  #define DDRCKECTLCH1_CR_DDRCRCTLRANKSUSED_RankEn_WID                 ( 4)
+  #define DDRCKECTLCH1_CR_DDRCRCTLRANKSUSED_RankEn_MSK                 (0x0000000F)
+  #define DDRCKECTLCH1_CR_DDRCRCTLRANKSUSED_RankEn_MAX                 (0x0000000F)
+  #define DDRCKECTLCH1_CR_DDRCRCTLRANKSUSED_RankEn_DEF                 (0x0000000F)
+  #define DDRCKECTLCH1_CR_DDRCRCTLRANKSUSED_OdtDisable_OFF             ( 4)
+  #define DDRCKECTLCH1_CR_DDRCRCTLRANKSUSED_OdtDisable_WID             ( 2)
+  #define DDRCKECTLCH1_CR_DDRCRCTLRANKSUSED_OdtDisable_MSK             (0x00000030)
+  #define DDRCKECTLCH1_CR_DDRCRCTLRANKSUSED_OdtDisable_MAX             (0x00000003)
+  #define DDRCKECTLCH1_CR_DDRCRCTLRANKSUSED_OdtDisable_DEF             (0x00000000)
+  #define DDRCKECTLCH1_CR_DDRCRCTLRANKSUSED_Spare_OFF                  ( 6)
+  #define DDRCKECTLCH1_CR_DDRCRCTLRANKSUSED_Spare_WID                  (26)
+  #define DDRCKECTLCH1_CR_DDRCRCTLRANKSUSED_Spare_MSK                  (0xFFFFFFC0)
+  #define DDRCKECTLCH1_CR_DDRCRCTLRANKSUSED_Spare_MAX                  (0x03FFFFFF)
+  #define DDRCKECTLCH1_CR_DDRCRCTLRANKSUSED_Spare_DEF                  (0x00000000)
+
+#define DDRCKECTLCH1_CR_DLLPITESTANDADC_REG                          (0x00003524)
+  #define DDRCKECTLCH1_CR_DLLPITESTANDADC_RunTest_OFF                  ( 0)
+  #define DDRCKECTLCH1_CR_DLLPITESTANDADC_RunTest_WID                  ( 1)
+  #define DDRCKECTLCH1_CR_DLLPITESTANDADC_RunTest_MSK                  (0x00000001)
+  #define DDRCKECTLCH1_CR_DLLPITESTANDADC_RunTest_MAX                  (0x00000001)
+  #define DDRCKECTLCH1_CR_DLLPITESTANDADC_RunTest_DEF                  (0x00000000)
+  #define DDRCKECTLCH1_CR_DLLPITESTANDADC_Load_OFF                     ( 1)
+  #define DDRCKECTLCH1_CR_DLLPITESTANDADC_Load_WID                     ( 1)
+  #define DDRCKECTLCH1_CR_DLLPITESTANDADC_Load_MSK                     (0x00000002)
+  #define DDRCKECTLCH1_CR_DLLPITESTANDADC_Load_MAX                     (0x00000001)
+  #define DDRCKECTLCH1_CR_DLLPITESTANDADC_Load_DEF                     (0x00000000)
+  #define DDRCKECTLCH1_CR_DLLPITESTANDADC_ModeHVM_OFF                  ( 2)
+  #define DDRCKECTLCH1_CR_DLLPITESTANDADC_ModeHVM_WID                  ( 1)
+  #define DDRCKECTLCH1_CR_DLLPITESTANDADC_ModeHVM_MSK                  (0x00000004)
+  #define DDRCKECTLCH1_CR_DLLPITESTANDADC_ModeHVM_MAX                  (0x00000001)
+  #define DDRCKECTLCH1_CR_DLLPITESTANDADC_ModeHVM_DEF                  (0x00000000)
+  #define DDRCKECTLCH1_CR_DLLPITESTANDADC_ModeDV_OFF                   ( 3)
+  #define DDRCKECTLCH1_CR_DLLPITESTANDADC_ModeDV_WID                   ( 1)
+  #define DDRCKECTLCH1_CR_DLLPITESTANDADC_ModeDV_MSK                   (0x00000008)
+  #define DDRCKECTLCH1_CR_DLLPITESTANDADC_ModeDV_MAX                   (0x00000001)
+  #define DDRCKECTLCH1_CR_DLLPITESTANDADC_ModeDV_DEF                   (0x00000000)
+  #define DDRCKECTLCH1_CR_DLLPITESTANDADC_ModeADC_OFF                  ( 4)
+  #define DDRCKECTLCH1_CR_DLLPITESTANDADC_ModeADC_WID                  ( 1)
+  #define DDRCKECTLCH1_CR_DLLPITESTANDADC_ModeADC_MSK                  (0x00000010)
+  #define DDRCKECTLCH1_CR_DLLPITESTANDADC_ModeADC_MAX                  (0x00000001)
+  #define DDRCKECTLCH1_CR_DLLPITESTANDADC_ModeADC_DEF                  (0x00000000)
+  #define DDRCKECTLCH1_CR_DLLPITESTANDADC_LoadCount_OFF                ( 5)
+  #define DDRCKECTLCH1_CR_DLLPITESTANDADC_LoadCount_WID                (10)
+  #define DDRCKECTLCH1_CR_DLLPITESTANDADC_LoadCount_MSK                (0x00007FE0)
+  #define DDRCKECTLCH1_CR_DLLPITESTANDADC_LoadCount_MAX                (0x000003FF)
+  #define DDRCKECTLCH1_CR_DLLPITESTANDADC_CountStatus_OFF              (15)
+  #define DDRCKECTLCH1_CR_DLLPITESTANDADC_CountStatus_WID              (10)
+  #define DDRCKECTLCH1_CR_DLLPITESTANDADC_CountStatus_MSK              (0x01FF8000)
+  #define DDRCKECTLCH1_CR_DLLPITESTANDADC_CountStatus_MAX              (0x000003FF)
+  #define DDRCKECTLCH1_CR_DLLPITESTANDADC_CountStatus_DEF              (0x00000000)
+  #define DDRCKECTLCH1_CR_DLLPITESTANDADC_Spare_OFF                    (25)
+  #define DDRCKECTLCH1_CR_DLLPITESTANDADC_Spare_WID                    ( 7)
+  #define DDRCKECTLCH1_CR_DLLPITESTANDADC_Spare_MSK                    (0xFE000000)
+  #define DDRCKECTLCH1_CR_DLLPITESTANDADC_Spare_MAX                    (0x0000007F)
+
+#define DDRCKECH0_CR_DDRCRCMDCOMP_REG                                (0x00001200)
+  #define DDRCKECH0_CR_DDRCRCMDCOMP_Scomp_OFF                          ( 0)
+  #define DDRCKECH0_CR_DDRCRCMDCOMP_Scomp_WID                          ( 6)
+  #define DDRCKECH0_CR_DDRCRCMDCOMP_Scomp_MSK                          (0x0000003F)
+  #define DDRCKECH0_CR_DDRCRCMDCOMP_Scomp_MAX                          (0x0000003F)
+  #define DDRCKECH0_CR_DDRCRCMDCOMP_Scomp_DEF                          (0x00000000)
+  #define DDRCKECH0_CR_DDRCRCMDCOMP_TcoComp_OFF                        ( 6)
+  #define DDRCKECH0_CR_DDRCRCMDCOMP_TcoComp_WID                        ( 6)
+  #define DDRCKECH0_CR_DDRCRCMDCOMP_TcoComp_MSK                        (0x00000FC0)
+  #define DDRCKECH0_CR_DDRCRCMDCOMP_TcoComp_MAX                        (0x0000003F)
+  #define DDRCKECH0_CR_DDRCRCMDCOMP_TcoComp_DEF                        (0x00000000)
+  #define DDRCKECH0_CR_DDRCRCMDCOMP_RcompDrvUp_OFF                     (12)
+  #define DDRCKECH0_CR_DDRCRCMDCOMP_RcompDrvUp_WID                     ( 6)
+  #define DDRCKECH0_CR_DDRCRCMDCOMP_RcompDrvUp_MSK                     (0x0003F000)
+  #define DDRCKECH0_CR_DDRCRCMDCOMP_RcompDrvUp_MAX                     (0x0000003F)
+  #define DDRCKECH0_CR_DDRCRCMDCOMP_RcompDrvUp_DEF                     (0x00000000)
+  #define DDRCKECH0_CR_DDRCRCMDCOMP_RcompDrvDown_OFF                   (18)
+  #define DDRCKECH0_CR_DDRCRCMDCOMP_RcompDrvDown_WID                   ( 6)
+  #define DDRCKECH0_CR_DDRCRCMDCOMP_RcompDrvDown_MSK                   (0x00FC0000)
+  #define DDRCKECH0_CR_DDRCRCMDCOMP_RcompDrvDown_MAX                   (0x0000003F)
+  #define DDRCKECH0_CR_DDRCRCMDCOMP_RcompDrvDown_DEF                   (0x00000000)
+  #define DDRCKECH0_CR_DDRCRCMDCOMP_LsComp_OFF                         (24)
+  #define DDRCKECH0_CR_DDRCRCMDCOMP_LsComp_WID                         ( 3)
+  #define DDRCKECH0_CR_DDRCRCMDCOMP_LsComp_MSK                         (0x07000000)
+  #define DDRCKECH0_CR_DDRCRCMDCOMP_LsComp_MAX                         (0x00000007)
+  #define DDRCKECH0_CR_DDRCRCMDCOMP_LsComp_DEF                         (0x00000004)
+  #define DDRCKECH0_CR_DDRCRCMDCOMP_Spare_OFF                          (27)
+  #define DDRCKECH0_CR_DDRCRCMDCOMP_Spare_WID                          ( 5)
+  #define DDRCKECH0_CR_DDRCRCMDCOMP_Spare_MSK                          (0xF8000000)
+  #define DDRCKECH0_CR_DDRCRCMDCOMP_Spare_MAX                          (0x0000001F)
+  #define DDRCKECH0_CR_DDRCRCMDCOMP_Spare_DEF                          (0x00000000)
+
+#define DDRCKECH0_CR_DDRCRCMDCOMPOFFSET_REG                          (0x00001204)
+  #define DDRCKECH0_CR_DDRCRCMDCOMPOFFSET_ScompOffset_OFF              ( 0)
+  #define DDRCKECH0_CR_DDRCRCMDCOMPOFFSET_ScompOffset_WID              ( 5)
+  #define DDRCKECH0_CR_DDRCRCMDCOMPOFFSET_ScompOffset_MSK              (0x0000001F)
+  #define DDRCKECH0_CR_DDRCRCMDCOMPOFFSET_ScompOffset_MAX              (0x0000001F)
+  #define DDRCKECH0_CR_DDRCRCMDCOMPOFFSET_ScompOffset_DEF              (0x00000000)
+  #define DDRCKECH0_CR_DDRCRCMDCOMPOFFSET_TcoCompOffset_OFF            ( 5)
+  #define DDRCKECH0_CR_DDRCRCMDCOMPOFFSET_TcoCompOffset_WID            ( 4)
+  #define DDRCKECH0_CR_DDRCRCMDCOMPOFFSET_TcoCompOffset_MSK            (0x000001E0)
+  #define DDRCKECH0_CR_DDRCRCMDCOMPOFFSET_TcoCompOffset_MAX            (0x0000000F)
+  #define DDRCKECH0_CR_DDRCRCMDCOMPOFFSET_TcoCompOffset_DEF            (0x00000000)
+  #define DDRCKECH0_CR_DDRCRCMDCOMPOFFSET_RcompDrvUpOffset_OFF         ( 9)
+  #define DDRCKECH0_CR_DDRCRCMDCOMPOFFSET_RcompDrvUpOffset_WID         ( 4)
+  #define DDRCKECH0_CR_DDRCRCMDCOMPOFFSET_RcompDrvUpOffset_MSK         (0x00001E00)
+  #define DDRCKECH0_CR_DDRCRCMDCOMPOFFSET_RcompDrvUpOffset_MAX         (0x0000000F)
+  #define DDRCKECH0_CR_DDRCRCMDCOMPOFFSET_RcompDrvUpOffset_DEF         (0x00000000)
+  #define DDRCKECH0_CR_DDRCRCMDCOMPOFFSET_RcompDrvDownOffset_OFF       (13)
+  #define DDRCKECH0_CR_DDRCRCMDCOMPOFFSET_RcompDrvDownOffset_WID       ( 4)
+  #define DDRCKECH0_CR_DDRCRCMDCOMPOFFSET_RcompDrvDownOffset_MSK       (0x0001E000)
+  #define DDRCKECH0_CR_DDRCRCMDCOMPOFFSET_RcompDrvDownOffset_MAX       (0x0000000F)
+  #define DDRCKECH0_CR_DDRCRCMDCOMPOFFSET_RcompDrvDownOffset_DEF       (0x00000000)
+  #define DDRCKECH0_CR_DDRCRCMDCOMPOFFSET_Spare_OFF                    (17)
+  #define DDRCKECH0_CR_DDRCRCMDCOMPOFFSET_Spare_WID                    (15)
+  #define DDRCKECH0_CR_DDRCRCMDCOMPOFFSET_Spare_MSK                    (0xFFFE0000)
+  #define DDRCKECH0_CR_DDRCRCMDCOMPOFFSET_Spare_MAX                    (0x00007FFF)
+  #define DDRCKECH0_CR_DDRCRCMDCOMPOFFSET_Spare_DEF                    (0x00000000)
+
+#define DDRCKECH0_CR_DDRCRCMDPICODING_REG                            (0x00001208)
+  #define DDRCKECH0_CR_DDRCRCMDPICODING_CmdPi0Code_OFF                 ( 0)
+  #define DDRCKECH0_CR_DDRCRCMDPICODING_CmdPi0Code_WID                 ( 7)
+  #define DDRCKECH0_CR_DDRCRCMDPICODING_CmdPi0Code_MSK                 (0x0000007F)
+  #define DDRCKECH0_CR_DDRCRCMDPICODING_CmdPi0Code_MAX                 (0x0000007F)
+  #define DDRCKECH0_CR_DDRCRCMDPICODING_CmdPi0Code_DEF                 (0x00000000)
+  #define DDRCKECH0_CR_DDRCRCMDPICODING_CmdPi1Code_OFF                 ( 7)
+  #define DDRCKECH0_CR_DDRCRCMDPICODING_CmdPi1Code_WID                 ( 7)
+  #define DDRCKECH0_CR_DDRCRCMDPICODING_CmdPi1Code_MSK                 (0x00003F80)
+  #define DDRCKECH0_CR_DDRCRCMDPICODING_CmdPi1Code_MAX                 (0x0000007F)
+  #define DDRCKECH0_CR_DDRCRCMDPICODING_CmdPi1Code_DEF                 (0x00000000)
+  #define DDRCKECH0_CR_DDRCRCMDPICODING_Spare_OFF                      (14)
+  #define DDRCKECH0_CR_DDRCRCMDPICODING_Spare_WID                      (18)
+  #define DDRCKECH0_CR_DDRCRCMDPICODING_Spare_MSK                      (0xFFFFC000)
+  #define DDRCKECH0_CR_DDRCRCMDPICODING_Spare_MAX                      (0x0003FFFF)
+  #define DDRCKECH0_CR_DDRCRCMDPICODING_Spare_DEF                      (0x00000000)
+
+#define DDRCKECH0_CR_DDRCRCTLCOMP_REG                                (0x00001210)
+  #define DDRCKECH0_CR_DDRCRCTLCOMP_Scomp_OFF                          ( 0)
+  #define DDRCKECH0_CR_DDRCRCTLCOMP_Scomp_WID                          ( 6)
+  #define DDRCKECH0_CR_DDRCRCTLCOMP_Scomp_MSK                          (0x0000003F)
+  #define DDRCKECH0_CR_DDRCRCTLCOMP_Scomp_MAX                          (0x0000003F)
+  #define DDRCKECH0_CR_DDRCRCTLCOMP_Scomp_DEF                          (0x00000000)
+  #define DDRCKECH0_CR_DDRCRCTLCOMP_TcoComp_OFF                        ( 6)
+  #define DDRCKECH0_CR_DDRCRCTLCOMP_TcoComp_WID                        ( 6)
+  #define DDRCKECH0_CR_DDRCRCTLCOMP_TcoComp_MSK                        (0x00000FC0)
+  #define DDRCKECH0_CR_DDRCRCTLCOMP_TcoComp_MAX                        (0x0000003F)
+  #define DDRCKECH0_CR_DDRCRCTLCOMP_TcoComp_DEF                        (0x00000000)
+  #define DDRCKECH0_CR_DDRCRCTLCOMP_RcompDrvUp_OFF                     (12)
+  #define DDRCKECH0_CR_DDRCRCTLCOMP_RcompDrvUp_WID                     ( 6)
+  #define DDRCKECH0_CR_DDRCRCTLCOMP_RcompDrvUp_MSK                     (0x0003F000)
+  #define DDRCKECH0_CR_DDRCRCTLCOMP_RcompDrvUp_MAX                     (0x0000003F)
+  #define DDRCKECH0_CR_DDRCRCTLCOMP_RcompDrvUp_DEF                     (0x00000000)
+  #define DDRCKECH0_CR_DDRCRCTLCOMP_RcompDrvDown_OFF                   (18)
+  #define DDRCKECH0_CR_DDRCRCTLCOMP_RcompDrvDown_WID                   ( 6)
+  #define DDRCKECH0_CR_DDRCRCTLCOMP_RcompDrvDown_MSK                   (0x00FC0000)
+  #define DDRCKECH0_CR_DDRCRCTLCOMP_RcompDrvDown_MAX                   (0x0000003F)
+  #define DDRCKECH0_CR_DDRCRCTLCOMP_RcompDrvDown_DEF                   (0x00000000)
+  #define DDRCKECH0_CR_DDRCRCTLCOMP_LsComp_OFF                         (24)
+  #define DDRCKECH0_CR_DDRCRCTLCOMP_LsComp_WID                         ( 3)
+  #define DDRCKECH0_CR_DDRCRCTLCOMP_LsComp_MSK                         (0x07000000)
+  #define DDRCKECH0_CR_DDRCRCTLCOMP_LsComp_MAX                         (0x00000007)
+  #define DDRCKECH0_CR_DDRCRCTLCOMP_LsComp_DEF                         (0x00000000)
+  #define DDRCKECH0_CR_DDRCRCTLCOMP_Spare_OFF                          (27)
+  #define DDRCKECH0_CR_DDRCRCTLCOMP_Spare_WID                          ( 5)
+  #define DDRCKECH0_CR_DDRCRCTLCOMP_Spare_MSK                          (0xF8000000)
+  #define DDRCKECH0_CR_DDRCRCTLCOMP_Spare_MAX                          (0x0000001F)
+  #define DDRCKECH0_CR_DDRCRCTLCOMP_Spare_DEF                          (0x00000000)
+
+#define DDRCKECH0_CR_DDRCRCTLCOMPOFFSET_REG                          (0x00001214)
+  #define DDRCKECH0_CR_DDRCRCTLCOMPOFFSET_ScompOffset_OFF              ( 0)
+  #define DDRCKECH0_CR_DDRCRCTLCOMPOFFSET_ScompOffset_WID              ( 5)
+  #define DDRCKECH0_CR_DDRCRCTLCOMPOFFSET_ScompOffset_MSK              (0x0000001F)
+  #define DDRCKECH0_CR_DDRCRCTLCOMPOFFSET_ScompOffset_MAX              (0x0000001F)
+  #define DDRCKECH0_CR_DDRCRCTLCOMPOFFSET_ScompOffset_DEF              (0x00000000)
+  #define DDRCKECH0_CR_DDRCRCTLCOMPOFFSET_TcoCompOffset_OFF            ( 5)
+  #define DDRCKECH0_CR_DDRCRCTLCOMPOFFSET_TcoCompOffset_WID            ( 4)
+  #define DDRCKECH0_CR_DDRCRCTLCOMPOFFSET_TcoCompOffset_MSK            (0x000001E0)
+  #define DDRCKECH0_CR_DDRCRCTLCOMPOFFSET_TcoCompOffset_MAX            (0x0000000F)
+  #define DDRCKECH0_CR_DDRCRCTLCOMPOFFSET_TcoCompOffset_DEF            (0x00000000)
+  #define DDRCKECH0_CR_DDRCRCTLCOMPOFFSET_RcompDrvUpOffset_OFF         ( 9)
+  #define DDRCKECH0_CR_DDRCRCTLCOMPOFFSET_RcompDrvUpOffset_WID         ( 4)
+  #define DDRCKECH0_CR_DDRCRCTLCOMPOFFSET_RcompDrvUpOffset_MSK         (0x00001E00)
+  #define DDRCKECH0_CR_DDRCRCTLCOMPOFFSET_RcompDrvUpOffset_MAX         (0x0000000F)
+  #define DDRCKECH0_CR_DDRCRCTLCOMPOFFSET_RcompDrvUpOffset_DEF         (0x00000000)
+  #define DDRCKECH0_CR_DDRCRCTLCOMPOFFSET_RcompDrvDownOffset_OFF       (13)
+  #define DDRCKECH0_CR_DDRCRCTLCOMPOFFSET_RcompDrvDownOffset_WID       ( 4)
+  #define DDRCKECH0_CR_DDRCRCTLCOMPOFFSET_RcompDrvDownOffset_MSK       (0x0001E000)
+  #define DDRCKECH0_CR_DDRCRCTLCOMPOFFSET_RcompDrvDownOffset_MAX       (0x0000000F)
+  #define DDRCKECH0_CR_DDRCRCTLCOMPOFFSET_RcompDrvDownOffset_DEF       (0x00000000)
+  #define DDRCKECH0_CR_DDRCRCTLCOMPOFFSET_Spare_OFF                    (17)
+  #define DDRCKECH0_CR_DDRCRCTLCOMPOFFSET_Spare_WID                    (15)
+  #define DDRCKECH0_CR_DDRCRCTLCOMPOFFSET_Spare_MSK                    (0xFFFE0000)
+  #define DDRCKECH0_CR_DDRCRCTLCOMPOFFSET_Spare_MAX                    (0x00007FFF)
+  #define DDRCKECH0_CR_DDRCRCTLCOMPOFFSET_Spare_DEF                    (0x00000000)
+
+#define DDRCKECH0_CR_DDRCRCTLPICODING_REG                            (0x00001218)
+  #define DDRCKECH0_CR_DDRCRCTLPICODING_CtlPiCode0_OFF                 ( 0)
+  #define DDRCKECH0_CR_DDRCRCTLPICODING_CtlPiCode0_WID                 ( 7)
+  #define DDRCKECH0_CR_DDRCRCTLPICODING_CtlPiCode0_MSK                 (0x0000007F)
+  #define DDRCKECH0_CR_DDRCRCTLPICODING_CtlPiCode0_MAX                 (0x0000007F)
+  #define DDRCKECH0_CR_DDRCRCTLPICODING_CtlPiCode0_DEF                 (0x00000000)
+  #define DDRCKECH0_CR_DDRCRCTLPICODING_CtlPiCode1_OFF                 ( 7)
+  #define DDRCKECH0_CR_DDRCRCTLPICODING_CtlPiCode1_WID                 ( 7)
+  #define DDRCKECH0_CR_DDRCRCTLPICODING_CtlPiCode1_MSK                 (0x00003F80)
+  #define DDRCKECH0_CR_DDRCRCTLPICODING_CtlPiCode1_MAX                 (0x0000007F)
+  #define DDRCKECH0_CR_DDRCRCTLPICODING_CtlPiCode1_DEF                 (0x00000000)
+  #define DDRCKECH0_CR_DDRCRCTLPICODING_CtlPiCode2_OFF                 (14)
+  #define DDRCKECH0_CR_DDRCRCTLPICODING_CtlPiCode2_WID                 ( 7)
+  #define DDRCKECH0_CR_DDRCRCTLPICODING_CtlPiCode2_MSK                 (0x001FC000)
+  #define DDRCKECH0_CR_DDRCRCTLPICODING_CtlPiCode2_MAX                 (0x0000007F)
+  #define DDRCKECH0_CR_DDRCRCTLPICODING_CtlPiCode2_DEF                 (0x00000000)
+  #define DDRCKECH0_CR_DDRCRCTLPICODING_CtlPiCode3_OFF                 (21)
+  #define DDRCKECH0_CR_DDRCRCTLPICODING_CtlPiCode3_WID                 ( 7)
+  #define DDRCKECH0_CR_DDRCRCTLPICODING_CtlPiCode3_MSK                 (0x0FE00000)
+  #define DDRCKECH0_CR_DDRCRCTLPICODING_CtlPiCode3_MAX                 (0x0000007F)
+  #define DDRCKECH0_CR_DDRCRCTLPICODING_CtlPiCode3_DEF                 (0x00000000)
+  #define DDRCKECH0_CR_DDRCRCTLPICODING_CtlXoverEnable_OFF             (28)
+  #define DDRCKECH0_CR_DDRCRCTLPICODING_CtlXoverEnable_WID             ( 1)
+  #define DDRCKECH0_CR_DDRCRCTLPICODING_CtlXoverEnable_MSK             (0x10000000)
+  #define DDRCKECH0_CR_DDRCRCTLPICODING_CtlXoverEnable_MAX             (0x00000001)
+  #define DDRCKECH0_CR_DDRCRCTLPICODING_CtlXoverEnable_DEF             (0x00000000)
+  #define DDRCKECH0_CR_DDRCRCTLPICODING_Spare_OFF                      (29)
+  #define DDRCKECH0_CR_DDRCRCTLPICODING_Spare_WID                      ( 3)
+  #define DDRCKECH0_CR_DDRCRCTLPICODING_Spare_MSK                      (0xE0000000)
+  #define DDRCKECH0_CR_DDRCRCTLPICODING_Spare_MAX                      (0x00000007)
+  #define DDRCKECH0_CR_DDRCRCTLPICODING_Spare_DEF                      (0x00000000)
+
+#define DDRCKECH0_CR_DDRCRCTLCONTROLS_REG                            (0x0000121C)
+  #define DDRCKECH0_CR_DDRCRCTLCONTROLS_RefPi_OFF                      ( 0)
+  #define DDRCKECH0_CR_DDRCRCTLCONTROLS_RefPi_WID                      ( 4)
+  #define DDRCKECH0_CR_DDRCRCTLCONTROLS_RefPi_MSK                      (0x0000000F)
+  #define DDRCKECH0_CR_DDRCRCTLCONTROLS_RefPi_MAX                      (0x0000000F)
+  #define DDRCKECH0_CR_DDRCRCTLCONTROLS_RefPi_DEF                      (0x00000000)
+  #define DDRCKECH0_CR_DDRCRCTLCONTROLS_DllMask_OFF                    ( 4)
+  #define DDRCKECH0_CR_DDRCRCTLCONTROLS_DllMask_WID                    ( 2)
+  #define DDRCKECH0_CR_DDRCRCTLCONTROLS_DllMask_MSK                    (0x00000030)
+  #define DDRCKECH0_CR_DDRCRCTLCONTROLS_DllMask_MAX                    (0x00000003)
+  #define DDRCKECH0_CR_DDRCRCTLCONTROLS_DllMask_DEF                    (0x00000000)
+  #define DDRCKECH0_CR_DDRCRCTLCONTROLS_DllRsvd1_OFF                   ( 6)
+  #define DDRCKECH0_CR_DDRCRCTLCONTROLS_DllRsvd1_WID                   ( 1)
+  #define DDRCKECH0_CR_DDRCRCTLCONTROLS_DllRsvd1_MSK                   (0x00000040)
+  #define DDRCKECH0_CR_DDRCRCTLCONTROLS_DllRsvd1_MAX                   (0x00000001)
+  #define DDRCKECH0_CR_DDRCRCTLCONTROLS_DllRsvd1_DEF                   (0x00000000)
+  #define DDRCKECH0_CR_DDRCRCTLCONTROLS_TxOn_OFF                       ( 7)
+  #define DDRCKECH0_CR_DDRCRCTLCONTROLS_TxOn_WID                       ( 1)
+  #define DDRCKECH0_CR_DDRCRCTLCONTROLS_TxOn_MSK                       (0x00000080)
+  #define DDRCKECH0_CR_DDRCRCTLCONTROLS_TxOn_MAX                       (0x00000001)
+  #define DDRCKECH0_CR_DDRCRCTLCONTROLS_TxOn_DEF                       (0x00000000)
+  #define DDRCKECH0_CR_DDRCRCTLCONTROLS_IntClkOn_OFF                   ( 8)
+  #define DDRCKECH0_CR_DDRCRCTLCONTROLS_IntClkOn_WID                   ( 1)
+  #define DDRCKECH0_CR_DDRCRCTLCONTROLS_IntClkOn_MSK                   (0x00000100)
+  #define DDRCKECH0_CR_DDRCRCTLCONTROLS_IntClkOn_MAX                   (0x00000001)
+  #define DDRCKECH0_CR_DDRCRCTLCONTROLS_IntClkOn_DEF                   (0x00000000)
+  #define DDRCKECH0_CR_DDRCRCTLCONTROLS_RepClkOn_OFF                   ( 9)
+  #define DDRCKECH0_CR_DDRCRCTLCONTROLS_RepClkOn_WID                   ( 1)
+  #define DDRCKECH0_CR_DDRCRCTLCONTROLS_RepClkOn_MSK                   (0x00000200)
+  #define DDRCKECH0_CR_DDRCRCTLCONTROLS_RepClkOn_MAX                   (0x00000001)
+  #define DDRCKECH0_CR_DDRCRCTLCONTROLS_RepClkOn_DEF                   (0x00000000)
+  #define DDRCKECH0_CR_DDRCRCTLCONTROLS_IOLBCtl_OFF                    (10)
+  #define DDRCKECH0_CR_DDRCRCTLCONTROLS_IOLBCtl_WID                    ( 2)
+  #define DDRCKECH0_CR_DDRCRCTLCONTROLS_IOLBCtl_MSK                    (0x00000C00)
+  #define DDRCKECH0_CR_DDRCRCTLCONTROLS_IOLBCtl_MAX                    (0x00000003)
+  #define DDRCKECH0_CR_DDRCRCTLCONTROLS_IOLBCtl_DEF                    (0x00000000)
+  #define DDRCKECH0_CR_DDRCRCTLCONTROLS_OdtMode_OFF                    (12)
+  #define DDRCKECH0_CR_DDRCRCTLCONTROLS_OdtMode_WID                    ( 1)
+  #define DDRCKECH0_CR_DDRCRCTLCONTROLS_OdtMode_MSK                    (0x00001000)
+  #define DDRCKECH0_CR_DDRCRCTLCONTROLS_OdtMode_MAX                    (0x00000001)
+  #define DDRCKECH0_CR_DDRCRCTLCONTROLS_OdtMode_DEF                    (0x00000000)
+  #define DDRCKECH0_CR_DDRCRCTLCONTROLS_CmdTxEq_OFF                    (13)
+  #define DDRCKECH0_CR_DDRCRCTLCONTROLS_CmdTxEq_WID                    ( 2)
+  #define DDRCKECH0_CR_DDRCRCTLCONTROLS_CmdTxEq_MSK                    (0x00006000)
+  #define DDRCKECH0_CR_DDRCRCTLCONTROLS_CmdTxEq_MAX                    (0x00000003)
+  #define DDRCKECH0_CR_DDRCRCTLCONTROLS_CmdTxEq_DEF                    (0x00000000)
+  #define DDRCKECH0_CR_DDRCRCTLCONTROLS_EarlyWeakDrive_OFF             (15)
+  #define DDRCKECH0_CR_DDRCRCTLCONTROLS_EarlyWeakDrive_WID             ( 2)
+  #define DDRCKECH0_CR_DDRCRCTLCONTROLS_EarlyWeakDrive_MSK             (0x00018000)
+  #define DDRCKECH0_CR_DDRCRCTLCONTROLS_EarlyWeakDrive_MAX             (0x00000003)
+  #define DDRCKECH0_CR_DDRCRCTLCONTROLS_EarlyWeakDrive_DEF             (0x00000000)
+  #define DDRCKECH0_CR_DDRCRCTLCONTROLS_CtlTxEq_OFF                    (17)
+  #define DDRCKECH0_CR_DDRCRCTLCONTROLS_CtlTxEq_WID                    ( 2)
+  #define DDRCKECH0_CR_DDRCRCTLCONTROLS_CtlTxEq_MSK                    (0x00060000)
+  #define DDRCKECH0_CR_DDRCRCTLCONTROLS_CtlTxEq_MAX                    (0x00000003)
+  #define DDRCKECH0_CR_DDRCRCTLCONTROLS_CtlTxEq_DEF                    (0x00000000)
+  #define DDRCKECH0_CR_DDRCRCTLCONTROLS_CtlSRDrv_OFF                   (19)
+  #define DDRCKECH0_CR_DDRCRCTLCONTROLS_CtlSRDrv_WID                   ( 2)
+  #define DDRCKECH0_CR_DDRCRCTLCONTROLS_CtlSRDrv_MSK                   (0x00180000)
+  #define DDRCKECH0_CR_DDRCRCTLCONTROLS_CtlSRDrv_MAX                   (0x00000003)
+  #define DDRCKECH0_CR_DDRCRCTLCONTROLS_CtlSRDrv_DEF                   (0x00000000)
+  #define DDRCKECH0_CR_DDRCRCTLCONTROLS_RxVref_OFF                     (21)
+  #define DDRCKECH0_CR_DDRCRCTLCONTROLS_RxVref_WID                     ( 6)
+  #define DDRCKECH0_CR_DDRCRCTLCONTROLS_RxVref_MSK                     (0x07E00000)
+  #define DDRCKECH0_CR_DDRCRCTLCONTROLS_RxVref_MAX                     (0x0000003F)
+  #define DDRCKECH0_CR_DDRCRCTLCONTROLS_RxVref_DEF                     (0x00000000)
+  #define DDRCKECH0_CR_DDRCRCTLCONTROLS_VccddqHi_OFF                   (27)
+  #define DDRCKECH0_CR_DDRCRCTLCONTROLS_VccddqHi_WID                   ( 1)
+  #define DDRCKECH0_CR_DDRCRCTLCONTROLS_VccddqHi_MSK                   (0x08000000)
+  #define DDRCKECH0_CR_DDRCRCTLCONTROLS_VccddqHi_MAX                   (0x00000001)
+  #define DDRCKECH0_CR_DDRCRCTLCONTROLS_VccddqHi_DEF                   (0x00000000)
+  #define DDRCKECH0_CR_DDRCRCTLCONTROLS_DllWeakLock_OFF                (28)
+  #define DDRCKECH0_CR_DDRCRCTLCONTROLS_DllWeakLock_WID                ( 1)
+  #define DDRCKECH0_CR_DDRCRCTLCONTROLS_DllWeakLock_MSK                (0x10000000)
+  #define DDRCKECH0_CR_DDRCRCTLCONTROLS_DllWeakLock_MAX                (0x00000001)
+  #define DDRCKECH0_CR_DDRCRCTLCONTROLS_DllWeakLock_DEF                (0x00000000)
+  #define DDRCKECH0_CR_DDRCRCTLCONTROLS_LPDDR_Mode_OFF                 (29)
+  #define DDRCKECH0_CR_DDRCRCTLCONTROLS_LPDDR_Mode_WID                 ( 1)
+  #define DDRCKECH0_CR_DDRCRCTLCONTROLS_LPDDR_Mode_MSK                 (0x20000000)
+  #define DDRCKECH0_CR_DDRCRCTLCONTROLS_LPDDR_Mode_MAX                 (0x00000001)
+  #define DDRCKECH0_CR_DDRCRCTLCONTROLS_LPDDR_Mode_DEF                 (0x00000000)
+  #define DDRCKECH0_CR_DDRCRCTLCONTROLS_LaDrvEnOvrd_OFF                (30)
+  #define DDRCKECH0_CR_DDRCRCTLCONTROLS_LaDrvEnOvrd_WID                ( 1)
+  #define DDRCKECH0_CR_DDRCRCTLCONTROLS_LaDrvEnOvrd_MSK                (0x40000000)
+  #define DDRCKECH0_CR_DDRCRCTLCONTROLS_LaDrvEnOvrd_MAX                (0x00000001)
+  #define DDRCKECH0_CR_DDRCRCTLCONTROLS_LaDrvEnOvrd_DEF                (0x00000000)
+  #define DDRCKECH0_CR_DDRCRCTLCONTROLS_LPDdrCAA_Dis_OFF               (31)
+  #define DDRCKECH0_CR_DDRCRCTLCONTROLS_LPDdrCAA_Dis_WID               ( 1)
+  #define DDRCKECH0_CR_DDRCRCTLCONTROLS_LPDdrCAA_Dis_MSK               (0x80000000)
+  #define DDRCKECH0_CR_DDRCRCTLCONTROLS_LPDdrCAA_Dis_MAX               (0x00000001)
+  #define DDRCKECH0_CR_DDRCRCTLCONTROLS_LPDdrCAA_Dis_DEF               (0x00000000)
+
+#define DDRCKECH0_CR_DDRCRCTLRANKSUSED_REG                           (0x00001220)
+  #define DDRCKECH0_CR_DDRCRCTLRANKSUSED_RankEn_OFF                    ( 0)
+  #define DDRCKECH0_CR_DDRCRCTLRANKSUSED_RankEn_WID                    ( 4)
+  #define DDRCKECH0_CR_DDRCRCTLRANKSUSED_RankEn_MSK                    (0x0000000F)
+  #define DDRCKECH0_CR_DDRCRCTLRANKSUSED_RankEn_MAX                    (0x0000000F)
+  #define DDRCKECH0_CR_DDRCRCTLRANKSUSED_RankEn_DEF                    (0x0000000F)
+  #define DDRCKECH0_CR_DDRCRCTLRANKSUSED_OdtDisable_OFF                ( 4)
+  #define DDRCKECH0_CR_DDRCRCTLRANKSUSED_OdtDisable_WID                ( 2)
+  #define DDRCKECH0_CR_DDRCRCTLRANKSUSED_OdtDisable_MSK                (0x00000030)
+  #define DDRCKECH0_CR_DDRCRCTLRANKSUSED_OdtDisable_MAX                (0x00000003)
+  #define DDRCKECH0_CR_DDRCRCTLRANKSUSED_OdtDisable_DEF                (0x00000000)
+  #define DDRCKECH0_CR_DDRCRCTLRANKSUSED_Spare_OFF                     ( 6)
+  #define DDRCKECH0_CR_DDRCRCTLRANKSUSED_Spare_WID                     (26)
+  #define DDRCKECH0_CR_DDRCRCTLRANKSUSED_Spare_MSK                     (0xFFFFFFC0)
+  #define DDRCKECH0_CR_DDRCRCTLRANKSUSED_Spare_MAX                     (0x03FFFFFF)
+  #define DDRCKECH0_CR_DDRCRCTLRANKSUSED_Spare_DEF                     (0x00000000)
+
+#define DDRCKECH0_CR_DLLPITESTANDADC_REG                             (0x00001224)
+  #define DDRCKECH0_CR_DLLPITESTANDADC_RunTest_OFF                     ( 0)
+  #define DDRCKECH0_CR_DLLPITESTANDADC_RunTest_WID                     ( 1)
+  #define DDRCKECH0_CR_DLLPITESTANDADC_RunTest_MSK                     (0x00000001)
+  #define DDRCKECH0_CR_DLLPITESTANDADC_RunTest_MAX                     (0x00000001)
+  #define DDRCKECH0_CR_DLLPITESTANDADC_RunTest_DEF                     (0x00000000)
+  #define DDRCKECH0_CR_DLLPITESTANDADC_Load_OFF                        ( 1)
+  #define DDRCKECH0_CR_DLLPITESTANDADC_Load_WID                        ( 1)
+  #define DDRCKECH0_CR_DLLPITESTANDADC_Load_MSK                        (0x00000002)
+  #define DDRCKECH0_CR_DLLPITESTANDADC_Load_MAX                        (0x00000001)
+  #define DDRCKECH0_CR_DLLPITESTANDADC_Load_DEF                        (0x00000000)
+  #define DDRCKECH0_CR_DLLPITESTANDADC_ModeHVM_OFF                     ( 2)
+  #define DDRCKECH0_CR_DLLPITESTANDADC_ModeHVM_WID                     ( 1)
+  #define DDRCKECH0_CR_DLLPITESTANDADC_ModeHVM_MSK                     (0x00000004)
+  #define DDRCKECH0_CR_DLLPITESTANDADC_ModeHVM_MAX                     (0x00000001)
+  #define DDRCKECH0_CR_DLLPITESTANDADC_ModeHVM_DEF                     (0x00000000)
+  #define DDRCKECH0_CR_DLLPITESTANDADC_ModeDV_OFF                      ( 3)
+  #define DDRCKECH0_CR_DLLPITESTANDADC_ModeDV_WID                      ( 1)
+  #define DDRCKECH0_CR_DLLPITESTANDADC_ModeDV_MSK                      (0x00000008)
+  #define DDRCKECH0_CR_DLLPITESTANDADC_ModeDV_MAX                      (0x00000001)
+  #define DDRCKECH0_CR_DLLPITESTANDADC_ModeDV_DEF                      (0x00000000)
+  #define DDRCKECH0_CR_DLLPITESTANDADC_ModeADC_OFF                     ( 4)
+  #define DDRCKECH0_CR_DLLPITESTANDADC_ModeADC_WID                     ( 1)
+  #define DDRCKECH0_CR_DLLPITESTANDADC_ModeADC_MSK                     (0x00000010)
+  #define DDRCKECH0_CR_DLLPITESTANDADC_ModeADC_MAX                     (0x00000001)
+  #define DDRCKECH0_CR_DLLPITESTANDADC_ModeADC_DEF                     (0x00000000)
+  #define DDRCKECH0_CR_DLLPITESTANDADC_LoadCount_OFF                   ( 5)
+  #define DDRCKECH0_CR_DLLPITESTANDADC_LoadCount_WID                   (10)
+  #define DDRCKECH0_CR_DLLPITESTANDADC_LoadCount_MSK                   (0x00007FE0)
+  #define DDRCKECH0_CR_DLLPITESTANDADC_LoadCount_MAX                   (0x000003FF)
+  #define DDRCKECH0_CR_DLLPITESTANDADC_CountStatus_OFF                 (15)
+  #define DDRCKECH0_CR_DLLPITESTANDADC_CountStatus_WID                 (10)
+  #define DDRCKECH0_CR_DLLPITESTANDADC_CountStatus_MSK                 (0x01FF8000)
+  #define DDRCKECH0_CR_DLLPITESTANDADC_CountStatus_MAX                 (0x000003FF)
+  #define DDRCKECH0_CR_DLLPITESTANDADC_CountStatus_DEF                 (0x00000000)
+  #define DDRCKECH0_CR_DLLPITESTANDADC_Spare_OFF                       (25)
+  #define DDRCKECH0_CR_DLLPITESTANDADC_Spare_WID                       ( 7)
+  #define DDRCKECH0_CR_DLLPITESTANDADC_Spare_MSK                       (0xFE000000)
+  #define DDRCKECH0_CR_DLLPITESTANDADC_Spare_MAX                       (0x0000007F)
+
+#define DDRCKECH1_CR_DDRCRCMDCOMP_REG                                (0x00001300)
+  #define DDRCKECH1_CR_DDRCRCMDCOMP_Scomp_OFF                          ( 0)
+  #define DDRCKECH1_CR_DDRCRCMDCOMP_Scomp_WID                          ( 6)
+  #define DDRCKECH1_CR_DDRCRCMDCOMP_Scomp_MSK                          (0x0000003F)
+  #define DDRCKECH1_CR_DDRCRCMDCOMP_Scomp_MAX                          (0x0000003F)
+  #define DDRCKECH1_CR_DDRCRCMDCOMP_Scomp_DEF                          (0x00000000)
+  #define DDRCKECH1_CR_DDRCRCMDCOMP_TcoComp_OFF                        ( 6)
+  #define DDRCKECH1_CR_DDRCRCMDCOMP_TcoComp_WID                        ( 6)
+  #define DDRCKECH1_CR_DDRCRCMDCOMP_TcoComp_MSK                        (0x00000FC0)
+  #define DDRCKECH1_CR_DDRCRCMDCOMP_TcoComp_MAX                        (0x0000003F)
+  #define DDRCKECH1_CR_DDRCRCMDCOMP_TcoComp_DEF                        (0x00000000)
+  #define DDRCKECH1_CR_DDRCRCMDCOMP_RcompDrvUp_OFF                     (12)
+  #define DDRCKECH1_CR_DDRCRCMDCOMP_RcompDrvUp_WID                     ( 6)
+  #define DDRCKECH1_CR_DDRCRCMDCOMP_RcompDrvUp_MSK                     (0x0003F000)
+  #define DDRCKECH1_CR_DDRCRCMDCOMP_RcompDrvUp_MAX                     (0x0000003F)
+  #define DDRCKECH1_CR_DDRCRCMDCOMP_RcompDrvUp_DEF                     (0x00000000)
+  #define DDRCKECH1_CR_DDRCRCMDCOMP_RcompDrvDown_OFF                   (18)
+  #define DDRCKECH1_CR_DDRCRCMDCOMP_RcompDrvDown_WID                   ( 6)
+  #define DDRCKECH1_CR_DDRCRCMDCOMP_RcompDrvDown_MSK                   (0x00FC0000)
+  #define DDRCKECH1_CR_DDRCRCMDCOMP_RcompDrvDown_MAX                   (0x0000003F)
+  #define DDRCKECH1_CR_DDRCRCMDCOMP_RcompDrvDown_DEF                   (0x00000000)
+  #define DDRCKECH1_CR_DDRCRCMDCOMP_LsComp_OFF                         (24)
+  #define DDRCKECH1_CR_DDRCRCMDCOMP_LsComp_WID                         ( 3)
+  #define DDRCKECH1_CR_DDRCRCMDCOMP_LsComp_MSK                         (0x07000000)
+  #define DDRCKECH1_CR_DDRCRCMDCOMP_LsComp_MAX                         (0x00000007)
+  #define DDRCKECH1_CR_DDRCRCMDCOMP_LsComp_DEF                         (0x00000004)
+  #define DDRCKECH1_CR_DDRCRCMDCOMP_Spare_OFF                          (27)
+  #define DDRCKECH1_CR_DDRCRCMDCOMP_Spare_WID                          ( 5)
+  #define DDRCKECH1_CR_DDRCRCMDCOMP_Spare_MSK                          (0xF8000000)
+  #define DDRCKECH1_CR_DDRCRCMDCOMP_Spare_MAX                          (0x0000001F)
+  #define DDRCKECH1_CR_DDRCRCMDCOMP_Spare_DEF                          (0x00000000)
+
+#define DDRCKECH1_CR_DDRCRCMDCOMPOFFSET_REG                          (0x00001304)
+  #define DDRCKECH1_CR_DDRCRCMDCOMPOFFSET_ScompOffset_OFF              ( 0)
+  #define DDRCKECH1_CR_DDRCRCMDCOMPOFFSET_ScompOffset_WID              ( 5)
+  #define DDRCKECH1_CR_DDRCRCMDCOMPOFFSET_ScompOffset_MSK              (0x0000001F)
+  #define DDRCKECH1_CR_DDRCRCMDCOMPOFFSET_ScompOffset_MAX              (0x0000001F)
+  #define DDRCKECH1_CR_DDRCRCMDCOMPOFFSET_ScompOffset_DEF              (0x00000000)
+  #define DDRCKECH1_CR_DDRCRCMDCOMPOFFSET_TcoCompOffset_OFF            ( 5)
+  #define DDRCKECH1_CR_DDRCRCMDCOMPOFFSET_TcoCompOffset_WID            ( 4)
+  #define DDRCKECH1_CR_DDRCRCMDCOMPOFFSET_TcoCompOffset_MSK            (0x000001E0)
+  #define DDRCKECH1_CR_DDRCRCMDCOMPOFFSET_TcoCompOffset_MAX            (0x0000000F)
+  #define DDRCKECH1_CR_DDRCRCMDCOMPOFFSET_TcoCompOffset_DEF            (0x00000000)
+  #define DDRCKECH1_CR_DDRCRCMDCOMPOFFSET_RcompDrvUpOffset_OFF         ( 9)
+  #define DDRCKECH1_CR_DDRCRCMDCOMPOFFSET_RcompDrvUpOffset_WID         ( 4)
+  #define DDRCKECH1_CR_DDRCRCMDCOMPOFFSET_RcompDrvUpOffset_MSK         (0x00001E00)
+  #define DDRCKECH1_CR_DDRCRCMDCOMPOFFSET_RcompDrvUpOffset_MAX         (0x0000000F)
+  #define DDRCKECH1_CR_DDRCRCMDCOMPOFFSET_RcompDrvUpOffset_DEF         (0x00000000)
+  #define DDRCKECH1_CR_DDRCRCMDCOMPOFFSET_RcompDrvDownOffset_OFF       (13)
+  #define DDRCKECH1_CR_DDRCRCMDCOMPOFFSET_RcompDrvDownOffset_WID       ( 4)
+  #define DDRCKECH1_CR_DDRCRCMDCOMPOFFSET_RcompDrvDownOffset_MSK       (0x0001E000)
+  #define DDRCKECH1_CR_DDRCRCMDCOMPOFFSET_RcompDrvDownOffset_MAX       (0x0000000F)
+  #define DDRCKECH1_CR_DDRCRCMDCOMPOFFSET_RcompDrvDownOffset_DEF       (0x00000000)
+  #define DDRCKECH1_CR_DDRCRCMDCOMPOFFSET_Spare_OFF                    (17)
+  #define DDRCKECH1_CR_DDRCRCMDCOMPOFFSET_Spare_WID                    (15)
+  #define DDRCKECH1_CR_DDRCRCMDCOMPOFFSET_Spare_MSK                    (0xFFFE0000)
+  #define DDRCKECH1_CR_DDRCRCMDCOMPOFFSET_Spare_MAX                    (0x00007FFF)
+  #define DDRCKECH1_CR_DDRCRCMDCOMPOFFSET_Spare_DEF                    (0x00000000)
+
+#define DDRCKECH1_CR_DDRCRCMDPICODING_REG                            (0x00001308)
+  #define DDRCKECH1_CR_DDRCRCMDPICODING_CmdPi0Code_OFF                 ( 0)
+  #define DDRCKECH1_CR_DDRCRCMDPICODING_CmdPi0Code_WID                 ( 7)
+  #define DDRCKECH1_CR_DDRCRCMDPICODING_CmdPi0Code_MSK                 (0x0000007F)
+  #define DDRCKECH1_CR_DDRCRCMDPICODING_CmdPi0Code_MAX                 (0x0000007F)
+  #define DDRCKECH1_CR_DDRCRCMDPICODING_CmdPi0Code_DEF                 (0x00000000)
+  #define DDRCKECH1_CR_DDRCRCMDPICODING_CmdPi1Code_OFF                 ( 7)
+  #define DDRCKECH1_CR_DDRCRCMDPICODING_CmdPi1Code_WID                 ( 7)
+  #define DDRCKECH1_CR_DDRCRCMDPICODING_CmdPi1Code_MSK                 (0x00003F80)
+  #define DDRCKECH1_CR_DDRCRCMDPICODING_CmdPi1Code_MAX                 (0x0000007F)
+  #define DDRCKECH1_CR_DDRCRCMDPICODING_CmdPi1Code_DEF                 (0x00000000)
+  #define DDRCKECH1_CR_DDRCRCMDPICODING_Spare_OFF                      (14)
+  #define DDRCKECH1_CR_DDRCRCMDPICODING_Spare_WID                      (18)
+  #define DDRCKECH1_CR_DDRCRCMDPICODING_Spare_MSK                      (0xFFFFC000)
+  #define DDRCKECH1_CR_DDRCRCMDPICODING_Spare_MAX                      (0x0003FFFF)
+  #define DDRCKECH1_CR_DDRCRCMDPICODING_Spare_DEF                      (0x00000000)
+
+#define DDRCKECH1_CR_DDRCRCTLCOMP_REG                                (0x00001310)
+  #define DDRCKECH1_CR_DDRCRCTLCOMP_Scomp_OFF                          ( 0)
+  #define DDRCKECH1_CR_DDRCRCTLCOMP_Scomp_WID                          ( 6)
+  #define DDRCKECH1_CR_DDRCRCTLCOMP_Scomp_MSK                          (0x0000003F)
+  #define DDRCKECH1_CR_DDRCRCTLCOMP_Scomp_MAX                          (0x0000003F)
+  #define DDRCKECH1_CR_DDRCRCTLCOMP_Scomp_DEF                          (0x00000000)
+  #define DDRCKECH1_CR_DDRCRCTLCOMP_TcoComp_OFF                        ( 6)
+  #define DDRCKECH1_CR_DDRCRCTLCOMP_TcoComp_WID                        ( 6)
+  #define DDRCKECH1_CR_DDRCRCTLCOMP_TcoComp_MSK                        (0x00000FC0)
+  #define DDRCKECH1_CR_DDRCRCTLCOMP_TcoComp_MAX                        (0x0000003F)
+  #define DDRCKECH1_CR_DDRCRCTLCOMP_TcoComp_DEF                        (0x00000000)
+  #define DDRCKECH1_CR_DDRCRCTLCOMP_RcompDrvUp_OFF                     (12)
+  #define DDRCKECH1_CR_DDRCRCTLCOMP_RcompDrvUp_WID                     ( 6)
+  #define DDRCKECH1_CR_DDRCRCTLCOMP_RcompDrvUp_MSK                     (0x0003F000)
+  #define DDRCKECH1_CR_DDRCRCTLCOMP_RcompDrvUp_MAX                     (0x0000003F)
+  #define DDRCKECH1_CR_DDRCRCTLCOMP_RcompDrvUp_DEF                     (0x00000000)
+  #define DDRCKECH1_CR_DDRCRCTLCOMP_RcompDrvDown_OFF                   (18)
+  #define DDRCKECH1_CR_DDRCRCTLCOMP_RcompDrvDown_WID                   ( 6)
+  #define DDRCKECH1_CR_DDRCRCTLCOMP_RcompDrvDown_MSK                   (0x00FC0000)
+  #define DDRCKECH1_CR_DDRCRCTLCOMP_RcompDrvDown_MAX                   (0x0000003F)
+  #define DDRCKECH1_CR_DDRCRCTLCOMP_RcompDrvDown_DEF                   (0x00000000)
+  #define DDRCKECH1_CR_DDRCRCTLCOMP_LsComp_OFF                         (24)
+  #define DDRCKECH1_CR_DDRCRCTLCOMP_LsComp_WID                         ( 3)
+  #define DDRCKECH1_CR_DDRCRCTLCOMP_LsComp_MSK                         (0x07000000)
+  #define DDRCKECH1_CR_DDRCRCTLCOMP_LsComp_MAX                         (0x00000007)
+  #define DDRCKECH1_CR_DDRCRCTLCOMP_LsComp_DEF                         (0x00000000)
+  #define DDRCKECH1_CR_DDRCRCTLCOMP_Spare_OFF                          (27)
+  #define DDRCKECH1_CR_DDRCRCTLCOMP_Spare_WID                          ( 5)
+  #define DDRCKECH1_CR_DDRCRCTLCOMP_Spare_MSK                          (0xF8000000)
+  #define DDRCKECH1_CR_DDRCRCTLCOMP_Spare_MAX                          (0x0000001F)
+  #define DDRCKECH1_CR_DDRCRCTLCOMP_Spare_DEF                          (0x00000000)
+
+#define DDRCKECH1_CR_DDRCRCTLCOMPOFFSET_REG                          (0x00001314)
+  #define DDRCKECH1_CR_DDRCRCTLCOMPOFFSET_ScompOffset_OFF              ( 0)
+  #define DDRCKECH1_CR_DDRCRCTLCOMPOFFSET_ScompOffset_WID              ( 5)
+  #define DDRCKECH1_CR_DDRCRCTLCOMPOFFSET_ScompOffset_MSK              (0x0000001F)
+  #define DDRCKECH1_CR_DDRCRCTLCOMPOFFSET_ScompOffset_MAX              (0x0000001F)
+  #define DDRCKECH1_CR_DDRCRCTLCOMPOFFSET_ScompOffset_DEF              (0x00000000)
+  #define DDRCKECH1_CR_DDRCRCTLCOMPOFFSET_TcoCompOffset_OFF            ( 5)
+  #define DDRCKECH1_CR_DDRCRCTLCOMPOFFSET_TcoCompOffset_WID            ( 4)
+  #define DDRCKECH1_CR_DDRCRCTLCOMPOFFSET_TcoCompOffset_MSK            (0x000001E0)
+  #define DDRCKECH1_CR_DDRCRCTLCOMPOFFSET_TcoCompOffset_MAX            (0x0000000F)
+  #define DDRCKECH1_CR_DDRCRCTLCOMPOFFSET_TcoCompOffset_DEF            (0x00000000)
+  #define DDRCKECH1_CR_DDRCRCTLCOMPOFFSET_RcompDrvUpOffset_OFF         ( 9)
+  #define DDRCKECH1_CR_DDRCRCTLCOMPOFFSET_RcompDrvUpOffset_WID         ( 4)
+  #define DDRCKECH1_CR_DDRCRCTLCOMPOFFSET_RcompDrvUpOffset_MSK         (0x00001E00)
+  #define DDRCKECH1_CR_DDRCRCTLCOMPOFFSET_RcompDrvUpOffset_MAX         (0x0000000F)
+  #define DDRCKECH1_CR_DDRCRCTLCOMPOFFSET_RcompDrvUpOffset_DEF         (0x00000000)
+  #define DDRCKECH1_CR_DDRCRCTLCOMPOFFSET_RcompDrvDownOffset_OFF       (13)
+  #define DDRCKECH1_CR_DDRCRCTLCOMPOFFSET_RcompDrvDownOffset_WID       ( 4)
+  #define DDRCKECH1_CR_DDRCRCTLCOMPOFFSET_RcompDrvDownOffset_MSK       (0x0001E000)
+  #define DDRCKECH1_CR_DDRCRCTLCOMPOFFSET_RcompDrvDownOffset_MAX       (0x0000000F)
+  #define DDRCKECH1_CR_DDRCRCTLCOMPOFFSET_RcompDrvDownOffset_DEF       (0x00000000)
+  #define DDRCKECH1_CR_DDRCRCTLCOMPOFFSET_Spare_OFF                    (17)
+  #define DDRCKECH1_CR_DDRCRCTLCOMPOFFSET_Spare_WID                    (15)
+  #define DDRCKECH1_CR_DDRCRCTLCOMPOFFSET_Spare_MSK                    (0xFFFE0000)
+  #define DDRCKECH1_CR_DDRCRCTLCOMPOFFSET_Spare_MAX                    (0x00007FFF)
+  #define DDRCKECH1_CR_DDRCRCTLCOMPOFFSET_Spare_DEF                    (0x00000000)
+
+#define DDRCKECH1_CR_DDRCRCTLPICODING_REG                            (0x00001318)
+  #define DDRCKECH1_CR_DDRCRCTLPICODING_CtlPiCode0_OFF                 ( 0)
+  #define DDRCKECH1_CR_DDRCRCTLPICODING_CtlPiCode0_WID                 ( 7)
+  #define DDRCKECH1_CR_DDRCRCTLPICODING_CtlPiCode0_MSK                 (0x0000007F)
+  #define DDRCKECH1_CR_DDRCRCTLPICODING_CtlPiCode0_MAX                 (0x0000007F)
+  #define DDRCKECH1_CR_DDRCRCTLPICODING_CtlPiCode0_DEF                 (0x00000000)
+  #define DDRCKECH1_CR_DDRCRCTLPICODING_CtlPiCode1_OFF                 ( 7)
+  #define DDRCKECH1_CR_DDRCRCTLPICODING_CtlPiCode1_WID                 ( 7)
+  #define DDRCKECH1_CR_DDRCRCTLPICODING_CtlPiCode1_MSK                 (0x00003F80)
+  #define DDRCKECH1_CR_DDRCRCTLPICODING_CtlPiCode1_MAX                 (0x0000007F)
+  #define DDRCKECH1_CR_DDRCRCTLPICODING_CtlPiCode1_DEF                 (0x00000000)
+  #define DDRCKECH1_CR_DDRCRCTLPICODING_CtlPiCode2_OFF                 (14)
+  #define DDRCKECH1_CR_DDRCRCTLPICODING_CtlPiCode2_WID                 ( 7)
+  #define DDRCKECH1_CR_DDRCRCTLPICODING_CtlPiCode2_MSK                 (0x001FC000)
+  #define DDRCKECH1_CR_DDRCRCTLPICODING_CtlPiCode2_MAX                 (0x0000007F)
+  #define DDRCKECH1_CR_DDRCRCTLPICODING_CtlPiCode2_DEF                 (0x00000000)
+  #define DDRCKECH1_CR_DDRCRCTLPICODING_CtlPiCode3_OFF                 (21)
+  #define DDRCKECH1_CR_DDRCRCTLPICODING_CtlPiCode3_WID                 ( 7)
+  #define DDRCKECH1_CR_DDRCRCTLPICODING_CtlPiCode3_MSK                 (0x0FE00000)
+  #define DDRCKECH1_CR_DDRCRCTLPICODING_CtlPiCode3_MAX                 (0x0000007F)
+  #define DDRCKECH1_CR_DDRCRCTLPICODING_CtlPiCode3_DEF                 (0x00000000)
+  #define DDRCKECH1_CR_DDRCRCTLPICODING_CtlXoverEnable_OFF             (28)
+  #define DDRCKECH1_CR_DDRCRCTLPICODING_CtlXoverEnable_WID             ( 1)
+  #define DDRCKECH1_CR_DDRCRCTLPICODING_CtlXoverEnable_MSK             (0x10000000)
+  #define DDRCKECH1_CR_DDRCRCTLPICODING_CtlXoverEnable_MAX             (0x00000001)
+  #define DDRCKECH1_CR_DDRCRCTLPICODING_CtlXoverEnable_DEF             (0x00000000)
+  #define DDRCKECH1_CR_DDRCRCTLPICODING_Spare_OFF                      (29)
+  #define DDRCKECH1_CR_DDRCRCTLPICODING_Spare_WID                      ( 3)
+  #define DDRCKECH1_CR_DDRCRCTLPICODING_Spare_MSK                      (0xE0000000)
+  #define DDRCKECH1_CR_DDRCRCTLPICODING_Spare_MAX                      (0x00000007)
+  #define DDRCKECH1_CR_DDRCRCTLPICODING_Spare_DEF                      (0x00000000)
+
+#define DDRCKECH1_CR_DDRCRCTLCONTROLS_REG                            (0x0000131C)
+  #define DDRCKECH1_CR_DDRCRCTLCONTROLS_RefPi_OFF                      ( 0)
+  #define DDRCKECH1_CR_DDRCRCTLCONTROLS_RefPi_WID                      ( 4)
+  #define DDRCKECH1_CR_DDRCRCTLCONTROLS_RefPi_MSK                      (0x0000000F)
+  #define DDRCKECH1_CR_DDRCRCTLCONTROLS_RefPi_MAX                      (0x0000000F)
+  #define DDRCKECH1_CR_DDRCRCTLCONTROLS_RefPi_DEF                      (0x00000000)
+  #define DDRCKECH1_CR_DDRCRCTLCONTROLS_DllMask_OFF                    ( 4)
+  #define DDRCKECH1_CR_DDRCRCTLCONTROLS_DllMask_WID                    ( 2)
+  #define DDRCKECH1_CR_DDRCRCTLCONTROLS_DllMask_MSK                    (0x00000030)
+  #define DDRCKECH1_CR_DDRCRCTLCONTROLS_DllMask_MAX                    (0x00000003)
+  #define DDRCKECH1_CR_DDRCRCTLCONTROLS_DllMask_DEF                    (0x00000000)
+  #define DDRCKECH1_CR_DDRCRCTLCONTROLS_DllRsvd1_OFF                   ( 6)
+  #define DDRCKECH1_CR_DDRCRCTLCONTROLS_DllRsvd1_WID                   ( 1)
+  #define DDRCKECH1_CR_DDRCRCTLCONTROLS_DllRsvd1_MSK                   (0x00000040)
+  #define DDRCKECH1_CR_DDRCRCTLCONTROLS_DllRsvd1_MAX                   (0x00000001)
+  #define DDRCKECH1_CR_DDRCRCTLCONTROLS_DllRsvd1_DEF                   (0x00000000)
+  #define DDRCKECH1_CR_DDRCRCTLCONTROLS_TxOn_OFF                       ( 7)
+  #define DDRCKECH1_CR_DDRCRCTLCONTROLS_TxOn_WID                       ( 1)
+  #define DDRCKECH1_CR_DDRCRCTLCONTROLS_TxOn_MSK                       (0x00000080)
+  #define DDRCKECH1_CR_DDRCRCTLCONTROLS_TxOn_MAX                       (0x00000001)
+  #define DDRCKECH1_CR_DDRCRCTLCONTROLS_TxOn_DEF                       (0x00000000)
+  #define DDRCKECH1_CR_DDRCRCTLCONTROLS_IntClkOn_OFF                   ( 8)
+  #define DDRCKECH1_CR_DDRCRCTLCONTROLS_IntClkOn_WID                   ( 1)
+  #define DDRCKECH1_CR_DDRCRCTLCONTROLS_IntClkOn_MSK                   (0x00000100)
+  #define DDRCKECH1_CR_DDRCRCTLCONTROLS_IntClkOn_MAX                   (0x00000001)
+  #define DDRCKECH1_CR_DDRCRCTLCONTROLS_IntClkOn_DEF                   (0x00000000)
+  #define DDRCKECH1_CR_DDRCRCTLCONTROLS_RepClkOn_OFF                   ( 9)
+  #define DDRCKECH1_CR_DDRCRCTLCONTROLS_RepClkOn_WID                   ( 1)
+  #define DDRCKECH1_CR_DDRCRCTLCONTROLS_RepClkOn_MSK                   (0x00000200)
+  #define DDRCKECH1_CR_DDRCRCTLCONTROLS_RepClkOn_MAX                   (0x00000001)
+  #define DDRCKECH1_CR_DDRCRCTLCONTROLS_RepClkOn_DEF                   (0x00000000)
+  #define DDRCKECH1_CR_DDRCRCTLCONTROLS_IOLBCtl_OFF                    (10)
+  #define DDRCKECH1_CR_DDRCRCTLCONTROLS_IOLBCtl_WID                    ( 2)
+  #define DDRCKECH1_CR_DDRCRCTLCONTROLS_IOLBCtl_MSK                    (0x00000C00)
+  #define DDRCKECH1_CR_DDRCRCTLCONTROLS_IOLBCtl_MAX                    (0x00000003)
+  #define DDRCKECH1_CR_DDRCRCTLCONTROLS_IOLBCtl_DEF                    (0x00000000)
+  #define DDRCKECH1_CR_DDRCRCTLCONTROLS_OdtMode_OFF                    (12)
+  #define DDRCKECH1_CR_DDRCRCTLCONTROLS_OdtMode_WID                    ( 1)
+  #define DDRCKECH1_CR_DDRCRCTLCONTROLS_OdtMode_MSK                    (0x00001000)
+  #define DDRCKECH1_CR_DDRCRCTLCONTROLS_OdtMode_MAX                    (0x00000001)
+  #define DDRCKECH1_CR_DDRCRCTLCONTROLS_OdtMode_DEF                    (0x00000000)
+  #define DDRCKECH1_CR_DDRCRCTLCONTROLS_CmdTxEq_OFF                    (13)
+  #define DDRCKECH1_CR_DDRCRCTLCONTROLS_CmdTxEq_WID                    ( 2)
+  #define DDRCKECH1_CR_DDRCRCTLCONTROLS_CmdTxEq_MSK                    (0x00006000)
+  #define DDRCKECH1_CR_DDRCRCTLCONTROLS_CmdTxEq_MAX                    (0x00000003)
+  #define DDRCKECH1_CR_DDRCRCTLCONTROLS_CmdTxEq_DEF                    (0x00000000)
+  #define DDRCKECH1_CR_DDRCRCTLCONTROLS_EarlyWeakDrive_OFF             (15)
+  #define DDRCKECH1_CR_DDRCRCTLCONTROLS_EarlyWeakDrive_WID             ( 2)
+  #define DDRCKECH1_CR_DDRCRCTLCONTROLS_EarlyWeakDrive_MSK             (0x00018000)
+  #define DDRCKECH1_CR_DDRCRCTLCONTROLS_EarlyWeakDrive_MAX             (0x00000003)
+  #define DDRCKECH1_CR_DDRCRCTLCONTROLS_EarlyWeakDrive_DEF             (0x00000000)
+  #define DDRCKECH1_CR_DDRCRCTLCONTROLS_CtlTxEq_OFF                    (17)
+  #define DDRCKECH1_CR_DDRCRCTLCONTROLS_CtlTxEq_WID                    ( 2)
+  #define DDRCKECH1_CR_DDRCRCTLCONTROLS_CtlTxEq_MSK                    (0x00060000)
+  #define DDRCKECH1_CR_DDRCRCTLCONTROLS_CtlTxEq_MAX                    (0x00000003)
+  #define DDRCKECH1_CR_DDRCRCTLCONTROLS_CtlTxEq_DEF                    (0x00000000)
+  #define DDRCKECH1_CR_DDRCRCTLCONTROLS_CtlSRDrv_OFF                   (19)
+  #define DDRCKECH1_CR_DDRCRCTLCONTROLS_CtlSRDrv_WID                   ( 2)
+  #define DDRCKECH1_CR_DDRCRCTLCONTROLS_CtlSRDrv_MSK                   (0x00180000)
+  #define DDRCKECH1_CR_DDRCRCTLCONTROLS_CtlSRDrv_MAX                   (0x00000003)
+  #define DDRCKECH1_CR_DDRCRCTLCONTROLS_CtlSRDrv_DEF                   (0x00000000)
+  #define DDRCKECH1_CR_DDRCRCTLCONTROLS_RxVref_OFF                     (21)
+  #define DDRCKECH1_CR_DDRCRCTLCONTROLS_RxVref_WID                     ( 6)
+  #define DDRCKECH1_CR_DDRCRCTLCONTROLS_RxVref_MSK                     (0x07E00000)
+  #define DDRCKECH1_CR_DDRCRCTLCONTROLS_RxVref_MAX                     (0x0000003F)
+  #define DDRCKECH1_CR_DDRCRCTLCONTROLS_RxVref_DEF                     (0x00000000)
+  #define DDRCKECH1_CR_DDRCRCTLCONTROLS_VccddqHi_OFF                   (27)
+  #define DDRCKECH1_CR_DDRCRCTLCONTROLS_VccddqHi_WID                   ( 1)
+  #define DDRCKECH1_CR_DDRCRCTLCONTROLS_VccddqHi_MSK                   (0x08000000)
+  #define DDRCKECH1_CR_DDRCRCTLCONTROLS_VccddqHi_MAX                   (0x00000001)
+  #define DDRCKECH1_CR_DDRCRCTLCONTROLS_VccddqHi_DEF                   (0x00000000)
+  #define DDRCKECH1_CR_DDRCRCTLCONTROLS_DllWeakLock_OFF                (28)
+  #define DDRCKECH1_CR_DDRCRCTLCONTROLS_DllWeakLock_WID                ( 1)
+  #define DDRCKECH1_CR_DDRCRCTLCONTROLS_DllWeakLock_MSK                (0x10000000)
+  #define DDRCKECH1_CR_DDRCRCTLCONTROLS_DllWeakLock_MAX                (0x00000001)
+  #define DDRCKECH1_CR_DDRCRCTLCONTROLS_DllWeakLock_DEF                (0x00000000)
+  #define DDRCKECH1_CR_DDRCRCTLCONTROLS_LPDDR_Mode_OFF                 (29)
+  #define DDRCKECH1_CR_DDRCRCTLCONTROLS_LPDDR_Mode_WID                 ( 1)
+  #define DDRCKECH1_CR_DDRCRCTLCONTROLS_LPDDR_Mode_MSK                 (0x20000000)
+  #define DDRCKECH1_CR_DDRCRCTLCONTROLS_LPDDR_Mode_MAX                 (0x00000001)
+  #define DDRCKECH1_CR_DDRCRCTLCONTROLS_LPDDR_Mode_DEF                 (0x00000000)
+  #define DDRCKECH1_CR_DDRCRCTLCONTROLS_LaDrvEnOvrd_OFF                (30)
+  #define DDRCKECH1_CR_DDRCRCTLCONTROLS_LaDrvEnOvrd_WID                ( 1)
+  #define DDRCKECH1_CR_DDRCRCTLCONTROLS_LaDrvEnOvrd_MSK                (0x40000000)
+  #define DDRCKECH1_CR_DDRCRCTLCONTROLS_LaDrvEnOvrd_MAX                (0x00000001)
+  #define DDRCKECH1_CR_DDRCRCTLCONTROLS_LaDrvEnOvrd_DEF                (0x00000000)
+  #define DDRCKECH1_CR_DDRCRCTLCONTROLS_LPDdrCAA_Dis_OFF               (31)
+  #define DDRCKECH1_CR_DDRCRCTLCONTROLS_LPDdrCAA_Dis_WID               ( 1)
+  #define DDRCKECH1_CR_DDRCRCTLCONTROLS_LPDdrCAA_Dis_MSK               (0x80000000)
+  #define DDRCKECH1_CR_DDRCRCTLCONTROLS_LPDdrCAA_Dis_MAX               (0x00000001)
+  #define DDRCKECH1_CR_DDRCRCTLCONTROLS_LPDdrCAA_Dis_DEF               (0x00000000)
+
+#define DDRCKECH1_CR_DDRCRCTLRANKSUSED_REG                           (0x00001320)
+  #define DDRCKECH1_CR_DDRCRCTLRANKSUSED_RankEn_OFF                    ( 0)
+  #define DDRCKECH1_CR_DDRCRCTLRANKSUSED_RankEn_WID                    ( 4)
+  #define DDRCKECH1_CR_DDRCRCTLRANKSUSED_RankEn_MSK                    (0x0000000F)
+  #define DDRCKECH1_CR_DDRCRCTLRANKSUSED_RankEn_MAX                    (0x0000000F)
+  #define DDRCKECH1_CR_DDRCRCTLRANKSUSED_RankEn_DEF                    (0x0000000F)
+  #define DDRCKECH1_CR_DDRCRCTLRANKSUSED_OdtDisable_OFF                ( 4)
+  #define DDRCKECH1_CR_DDRCRCTLRANKSUSED_OdtDisable_WID                ( 2)
+  #define DDRCKECH1_CR_DDRCRCTLRANKSUSED_OdtDisable_MSK                (0x00000030)
+  #define DDRCKECH1_CR_DDRCRCTLRANKSUSED_OdtDisable_MAX                (0x00000003)
+  #define DDRCKECH1_CR_DDRCRCTLRANKSUSED_OdtDisable_DEF                (0x00000000)
+  #define DDRCKECH1_CR_DDRCRCTLRANKSUSED_Spare_OFF                     ( 6)
+  #define DDRCKECH1_CR_DDRCRCTLRANKSUSED_Spare_WID                     (26)
+  #define DDRCKECH1_CR_DDRCRCTLRANKSUSED_Spare_MSK                     (0xFFFFFFC0)
+  #define DDRCKECH1_CR_DDRCRCTLRANKSUSED_Spare_MAX                     (0x03FFFFFF)
+  #define DDRCKECH1_CR_DDRCRCTLRANKSUSED_Spare_DEF                     (0x00000000)
+
+#define DDRCKECH1_CR_DLLPITESTANDADC_REG                             (0x00001324)
+  #define DDRCKECH1_CR_DLLPITESTANDADC_RunTest_OFF                     ( 0)
+  #define DDRCKECH1_CR_DLLPITESTANDADC_RunTest_WID                     ( 1)
+  #define DDRCKECH1_CR_DLLPITESTANDADC_RunTest_MSK                     (0x00000001)
+  #define DDRCKECH1_CR_DLLPITESTANDADC_RunTest_MAX                     (0x00000001)
+  #define DDRCKECH1_CR_DLLPITESTANDADC_RunTest_DEF                     (0x00000000)
+  #define DDRCKECH1_CR_DLLPITESTANDADC_Load_OFF                        ( 1)
+  #define DDRCKECH1_CR_DLLPITESTANDADC_Load_WID                        ( 1)
+  #define DDRCKECH1_CR_DLLPITESTANDADC_Load_MSK                        (0x00000002)
+  #define DDRCKECH1_CR_DLLPITESTANDADC_Load_MAX                        (0x00000001)
+  #define DDRCKECH1_CR_DLLPITESTANDADC_Load_DEF                        (0x00000000)
+  #define DDRCKECH1_CR_DLLPITESTANDADC_ModeHVM_OFF                     ( 2)
+  #define DDRCKECH1_CR_DLLPITESTANDADC_ModeHVM_WID                     ( 1)
+  #define DDRCKECH1_CR_DLLPITESTANDADC_ModeHVM_MSK                     (0x00000004)
+  #define DDRCKECH1_CR_DLLPITESTANDADC_ModeHVM_MAX                     (0x00000001)
+  #define DDRCKECH1_CR_DLLPITESTANDADC_ModeHVM_DEF                     (0x00000000)
+  #define DDRCKECH1_CR_DLLPITESTANDADC_ModeDV_OFF                      ( 3)
+  #define DDRCKECH1_CR_DLLPITESTANDADC_ModeDV_WID                      ( 1)
+  #define DDRCKECH1_CR_DLLPITESTANDADC_ModeDV_MSK                      (0x00000008)
+  #define DDRCKECH1_CR_DLLPITESTANDADC_ModeDV_MAX                      (0x00000001)
+  #define DDRCKECH1_CR_DLLPITESTANDADC_ModeDV_DEF                      (0x00000000)
+  #define DDRCKECH1_CR_DLLPITESTANDADC_ModeADC_OFF                     ( 4)
+  #define DDRCKECH1_CR_DLLPITESTANDADC_ModeADC_WID                     ( 1)
+  #define DDRCKECH1_CR_DLLPITESTANDADC_ModeADC_MSK                     (0x00000010)
+  #define DDRCKECH1_CR_DLLPITESTANDADC_ModeADC_MAX                     (0x00000001)
+  #define DDRCKECH1_CR_DLLPITESTANDADC_ModeADC_DEF                     (0x00000000)
+  #define DDRCKECH1_CR_DLLPITESTANDADC_LoadCount_OFF                   ( 5)
+  #define DDRCKECH1_CR_DLLPITESTANDADC_LoadCount_WID                   (10)
+  #define DDRCKECH1_CR_DLLPITESTANDADC_LoadCount_MSK                   (0x00007FE0)
+  #define DDRCKECH1_CR_DLLPITESTANDADC_LoadCount_MAX                   (0x000003FF)
+  #define DDRCKECH1_CR_DLLPITESTANDADC_CountStatus_OFF                 (15)
+  #define DDRCKECH1_CR_DLLPITESTANDADC_CountStatus_WID                 (10)
+  #define DDRCKECH1_CR_DLLPITESTANDADC_CountStatus_MSK                 (0x01FF8000)
+  #define DDRCKECH1_CR_DLLPITESTANDADC_CountStatus_MAX                 (0x000003FF)
+  #define DDRCKECH1_CR_DLLPITESTANDADC_CountStatus_DEF                 (0x00000000)
+  #define DDRCKECH1_CR_DLLPITESTANDADC_Spare_OFF                       (25)
+  #define DDRCKECH1_CR_DLLPITESTANDADC_Spare_WID                       ( 7)
+  #define DDRCKECH1_CR_DLLPITESTANDADC_Spare_MSK                       (0xFE000000)
+  #define DDRCKECH1_CR_DLLPITESTANDADC_Spare_MAX                       (0x0000007F)
+
+#define DDRCTLCH0_CR_DDRCRCTLCOMP_REG                                (0x00001C10)
+  #define DDRCTLCH0_CR_DDRCRCTLCOMP_Scomp_OFF                          ( 0)
+  #define DDRCTLCH0_CR_DDRCRCTLCOMP_Scomp_WID                          ( 6)
+  #define DDRCTLCH0_CR_DDRCRCTLCOMP_Scomp_MSK                          (0x0000003F)
+  #define DDRCTLCH0_CR_DDRCRCTLCOMP_Scomp_MAX                          (0x0000003F)
+  #define DDRCTLCH0_CR_DDRCRCTLCOMP_Scomp_DEF                          (0x00000000)
+  #define DDRCTLCH0_CR_DDRCRCTLCOMP_TcoComp_OFF                        ( 6)
+  #define DDRCTLCH0_CR_DDRCRCTLCOMP_TcoComp_WID                        ( 6)
+  #define DDRCTLCH0_CR_DDRCRCTLCOMP_TcoComp_MSK                        (0x00000FC0)
+  #define DDRCTLCH0_CR_DDRCRCTLCOMP_TcoComp_MAX                        (0x0000003F)
+  #define DDRCTLCH0_CR_DDRCRCTLCOMP_TcoComp_DEF                        (0x00000000)
+  #define DDRCTLCH0_CR_DDRCRCTLCOMP_RcompDrvUp_OFF                     (12)
+  #define DDRCTLCH0_CR_DDRCRCTLCOMP_RcompDrvUp_WID                     ( 6)
+  #define DDRCTLCH0_CR_DDRCRCTLCOMP_RcompDrvUp_MSK                     (0x0003F000)
+  #define DDRCTLCH0_CR_DDRCRCTLCOMP_RcompDrvUp_MAX                     (0x0000003F)
+  #define DDRCTLCH0_CR_DDRCRCTLCOMP_RcompDrvUp_DEF                     (0x00000000)
+  #define DDRCTLCH0_CR_DDRCRCTLCOMP_RcompDrvDown_OFF                   (18)
+  #define DDRCTLCH0_CR_DDRCRCTLCOMP_RcompDrvDown_WID                   ( 6)
+  #define DDRCTLCH0_CR_DDRCRCTLCOMP_RcompDrvDown_MSK                   (0x00FC0000)
+  #define DDRCTLCH0_CR_DDRCRCTLCOMP_RcompDrvDown_MAX                   (0x0000003F)
+  #define DDRCTLCH0_CR_DDRCRCTLCOMP_RcompDrvDown_DEF                   (0x00000000)
+  #define DDRCTLCH0_CR_DDRCRCTLCOMP_LsComp_OFF                         (24)
+  #define DDRCTLCH0_CR_DDRCRCTLCOMP_LsComp_WID                         ( 3)
+  #define DDRCTLCH0_CR_DDRCRCTLCOMP_LsComp_MSK                         (0x07000000)
+  #define DDRCTLCH0_CR_DDRCRCTLCOMP_LsComp_MAX                         (0x00000007)
+  #define DDRCTLCH0_CR_DDRCRCTLCOMP_LsComp_DEF                         (0x00000000)
+  #define DDRCTLCH0_CR_DDRCRCTLCOMP_Spare_OFF                          (27)
+  #define DDRCTLCH0_CR_DDRCRCTLCOMP_Spare_WID                          ( 5)
+  #define DDRCTLCH0_CR_DDRCRCTLCOMP_Spare_MSK                          (0xF8000000)
+  #define DDRCTLCH0_CR_DDRCRCTLCOMP_Spare_MAX                          (0x0000001F)
+  #define DDRCTLCH0_CR_DDRCRCTLCOMP_Spare_DEF                          (0x00000000)
+
+#define DDRCTLCH0_CR_DDRCRCTLCOMPOFFSET_REG                          (0x00001C14)
+  #define DDRCTLCH0_CR_DDRCRCTLCOMPOFFSET_ScompOffset_OFF              ( 0)
+  #define DDRCTLCH0_CR_DDRCRCTLCOMPOFFSET_ScompOffset_WID              ( 5)
+  #define DDRCTLCH0_CR_DDRCRCTLCOMPOFFSET_ScompOffset_MSK              (0x0000001F)
+  #define DDRCTLCH0_CR_DDRCRCTLCOMPOFFSET_ScompOffset_MAX              (0x0000001F)
+  #define DDRCTLCH0_CR_DDRCRCTLCOMPOFFSET_ScompOffset_DEF              (0x00000000)
+  #define DDRCTLCH0_CR_DDRCRCTLCOMPOFFSET_TcoCompOffset_OFF            ( 5)
+  #define DDRCTLCH0_CR_DDRCRCTLCOMPOFFSET_TcoCompOffset_WID            ( 4)
+  #define DDRCTLCH0_CR_DDRCRCTLCOMPOFFSET_TcoCompOffset_MSK            (0x000001E0)
+  #define DDRCTLCH0_CR_DDRCRCTLCOMPOFFSET_TcoCompOffset_MAX            (0x0000000F)
+  #define DDRCTLCH0_CR_DDRCRCTLCOMPOFFSET_TcoCompOffset_DEF            (0x00000000)
+  #define DDRCTLCH0_CR_DDRCRCTLCOMPOFFSET_RcompDrvUpOffset_OFF         ( 9)
+  #define DDRCTLCH0_CR_DDRCRCTLCOMPOFFSET_RcompDrvUpOffset_WID         ( 4)
+  #define DDRCTLCH0_CR_DDRCRCTLCOMPOFFSET_RcompDrvUpOffset_MSK         (0x00001E00)
+  #define DDRCTLCH0_CR_DDRCRCTLCOMPOFFSET_RcompDrvUpOffset_MAX         (0x0000000F)
+  #define DDRCTLCH0_CR_DDRCRCTLCOMPOFFSET_RcompDrvUpOffset_DEF         (0x00000000)
+  #define DDRCTLCH0_CR_DDRCRCTLCOMPOFFSET_RcompDrvDownOffset_OFF       (13)
+  #define DDRCTLCH0_CR_DDRCRCTLCOMPOFFSET_RcompDrvDownOffset_WID       ( 4)
+  #define DDRCTLCH0_CR_DDRCRCTLCOMPOFFSET_RcompDrvDownOffset_MSK       (0x0001E000)
+  #define DDRCTLCH0_CR_DDRCRCTLCOMPOFFSET_RcompDrvDownOffset_MAX       (0x0000000F)
+  #define DDRCTLCH0_CR_DDRCRCTLCOMPOFFSET_RcompDrvDownOffset_DEF       (0x00000000)
+  #define DDRCTLCH0_CR_DDRCRCTLCOMPOFFSET_Spare_OFF                    (17)
+  #define DDRCTLCH0_CR_DDRCRCTLCOMPOFFSET_Spare_WID                    (15)
+  #define DDRCTLCH0_CR_DDRCRCTLCOMPOFFSET_Spare_MSK                    (0xFFFE0000)
+  #define DDRCTLCH0_CR_DDRCRCTLCOMPOFFSET_Spare_MAX                    (0x00007FFF)
+  #define DDRCTLCH0_CR_DDRCRCTLCOMPOFFSET_Spare_DEF                    (0x00000000)
+
+#define DDRCTLCH0_CR_DDRCRCTLPICODING_REG                            (0x00001C18)
+  #define DDRCTLCH0_CR_DDRCRCTLPICODING_CtlPiCode0_OFF                 ( 0)
+  #define DDRCTLCH0_CR_DDRCRCTLPICODING_CtlPiCode0_WID                 ( 7)
+  #define DDRCTLCH0_CR_DDRCRCTLPICODING_CtlPiCode0_MSK                 (0x0000007F)
+  #define DDRCTLCH0_CR_DDRCRCTLPICODING_CtlPiCode0_MAX                 (0x0000007F)
+  #define DDRCTLCH0_CR_DDRCRCTLPICODING_CtlPiCode0_DEF                 (0x00000000)
+  #define DDRCTLCH0_CR_DDRCRCTLPICODING_CtlPiCode1_OFF                 ( 7)
+  #define DDRCTLCH0_CR_DDRCRCTLPICODING_CtlPiCode1_WID                 ( 7)
+  #define DDRCTLCH0_CR_DDRCRCTLPICODING_CtlPiCode1_MSK                 (0x00003F80)
+  #define DDRCTLCH0_CR_DDRCRCTLPICODING_CtlPiCode1_MAX                 (0x0000007F)
+  #define DDRCTLCH0_CR_DDRCRCTLPICODING_CtlPiCode1_DEF                 (0x00000000)
+  #define DDRCTLCH0_CR_DDRCRCTLPICODING_CtlPiCode2_OFF                 (14)
+  #define DDRCTLCH0_CR_DDRCRCTLPICODING_CtlPiCode2_WID                 ( 7)
+  #define DDRCTLCH0_CR_DDRCRCTLPICODING_CtlPiCode2_MSK                 (0x001FC000)
+  #define DDRCTLCH0_CR_DDRCRCTLPICODING_CtlPiCode2_MAX                 (0x0000007F)
+  #define DDRCTLCH0_CR_DDRCRCTLPICODING_CtlPiCode2_DEF                 (0x00000000)
+  #define DDRCTLCH0_CR_DDRCRCTLPICODING_CtlPiCode3_OFF                 (21)
+  #define DDRCTLCH0_CR_DDRCRCTLPICODING_CtlPiCode3_WID                 ( 7)
+  #define DDRCTLCH0_CR_DDRCRCTLPICODING_CtlPiCode3_MSK                 (0x0FE00000)
+  #define DDRCTLCH0_CR_DDRCRCTLPICODING_CtlPiCode3_MAX                 (0x0000007F)
+  #define DDRCTLCH0_CR_DDRCRCTLPICODING_CtlPiCode3_DEF                 (0x00000000)
+  #define DDRCTLCH0_CR_DDRCRCTLPICODING_CtlXoverEnable_OFF             (28)
+  #define DDRCTLCH0_CR_DDRCRCTLPICODING_CtlXoverEnable_WID             ( 1)
+  #define DDRCTLCH0_CR_DDRCRCTLPICODING_CtlXoverEnable_MSK             (0x10000000)
+  #define DDRCTLCH0_CR_DDRCRCTLPICODING_CtlXoverEnable_MAX             (0x00000001)
+  #define DDRCTLCH0_CR_DDRCRCTLPICODING_CtlXoverEnable_DEF             (0x00000000)
+  #define DDRCTLCH0_CR_DDRCRCTLPICODING_Spare_OFF                      (29)
+  #define DDRCTLCH0_CR_DDRCRCTLPICODING_Spare_WID                      ( 3)
+  #define DDRCTLCH0_CR_DDRCRCTLPICODING_Spare_MSK                      (0xE0000000)
+  #define DDRCTLCH0_CR_DDRCRCTLPICODING_Spare_MAX                      (0x00000007)
+  #define DDRCTLCH0_CR_DDRCRCTLPICODING_Spare_DEF                      (0x00000000)
+
+#define DDRCTLCH0_CR_DDRCRCTLCONTROLS_REG                            (0x00001C1C)
+  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_RefPi_OFF                      ( 0)
+  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_RefPi_WID                      ( 4)
+  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_RefPi_MSK                      (0x0000000F)
+  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_RefPi_MAX                      (0x0000000F)
+  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_RefPi_DEF                      (0x00000000)
+  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_DllMask_OFF                    ( 4)
+  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_DllMask_WID                    ( 2)
+  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_DllMask_MSK                    (0x00000030)
+  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_DllMask_MAX                    (0x00000003)
+  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_DllMask_DEF                    (0x00000000)
+  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_DllRsvd1_OFF                   ( 6)
+  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_DllRsvd1_WID                   ( 1)
+  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_DllRsvd1_MSK                   (0x00000040)
+  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_DllRsvd1_MAX                   (0x00000001)
+  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_DllRsvd1_DEF                   (0x00000000)
+  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_TxOn_OFF                       ( 7)
+  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_TxOn_WID                       ( 1)
+  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_TxOn_MSK                       (0x00000080)
+  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_TxOn_MAX                       (0x00000001)
+  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_TxOn_DEF                       (0x00000000)
+  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_IntClkOn_OFF                   ( 8)
+  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_IntClkOn_WID                   ( 1)
+  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_IntClkOn_MSK                   (0x00000100)
+  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_IntClkOn_MAX                   (0x00000001)
+  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_IntClkOn_DEF                   (0x00000000)
+  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_RepClkOn_OFF                   ( 9)
+  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_RepClkOn_WID                   ( 1)
+  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_RepClkOn_MSK                   (0x00000200)
+  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_RepClkOn_MAX                   (0x00000001)
+  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_RepClkOn_DEF                   (0x00000000)
+  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_IOLBCtl_OFF                    (10)
+  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_IOLBCtl_WID                    ( 2)
+  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_IOLBCtl_MSK                    (0x00000C00)
+  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_IOLBCtl_MAX                    (0x00000003)
+  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_IOLBCtl_DEF                    (0x00000000)
+  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_OdtMode_OFF                    (12)
+  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_OdtMode_WID                    ( 1)
+  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_OdtMode_MSK                    (0x00001000)
+  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_OdtMode_MAX                    (0x00000001)
+  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_OdtMode_DEF                    (0x00000000)
+  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_CmdTxEq_OFF                    (13)
+  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_CmdTxEq_WID                    ( 2)
+  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_CmdTxEq_MSK                    (0x00006000)
+  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_CmdTxEq_MAX                    (0x00000003)
+  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_CmdTxEq_DEF                    (0x00000000)
+  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_EarlyWeakDrive_OFF             (15)
+  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_EarlyWeakDrive_WID             ( 2)
+  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_EarlyWeakDrive_MSK             (0x00018000)
+  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_EarlyWeakDrive_MAX             (0x00000003)
+  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_EarlyWeakDrive_DEF             (0x00000000)
+  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_CtlTxEq_OFF                    (17)
+  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_CtlTxEq_WID                    ( 2)
+  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_CtlTxEq_MSK                    (0x00060000)
+  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_CtlTxEq_MAX                    (0x00000003)
+  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_CtlTxEq_DEF                    (0x00000000)
+  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_CtlSRDrv_OFF                   (19)
+  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_CtlSRDrv_WID                   ( 2)
+  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_CtlSRDrv_MSK                   (0x00180000)
+  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_CtlSRDrv_MAX                   (0x00000003)
+  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_CtlSRDrv_DEF                   (0x00000000)
+  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_RxVref_OFF                     (21)
+  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_RxVref_WID                     ( 6)
+  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_RxVref_MSK                     (0x07E00000)
+  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_RxVref_MAX                     (0x0000003F)
+  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_RxVref_DEF                     (0x00000000)
+  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_VccddqHi_OFF                   (27)
+  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_VccddqHi_WID                   ( 1)
+  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_VccddqHi_MSK                   (0x08000000)
+  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_VccddqHi_MAX                   (0x00000001)
+  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_VccddqHi_DEF                   (0x00000000)
+  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_DllWeakLock_OFF                (28)
+  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_DllWeakLock_WID                ( 1)
+  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_DllWeakLock_MSK                (0x10000000)
+  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_DllWeakLock_MAX                (0x00000001)
+  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_DllWeakLock_DEF                (0x00000000)
+  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_LPDDR_Mode_OFF                 (29)
+  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_LPDDR_Mode_WID                 ( 1)
+  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_LPDDR_Mode_MSK                 (0x20000000)
+  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_LPDDR_Mode_MAX                 (0x00000001)
+  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_LPDDR_Mode_DEF                 (0x00000000)
+  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_LaDrvEnOvrd_OFF                (30)
+  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_LaDrvEnOvrd_WID                ( 1)
+  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_LaDrvEnOvrd_MSK                (0x40000000)
+  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_LaDrvEnOvrd_MAX                (0x00000001)
+  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_LaDrvEnOvrd_DEF                (0x00000000)
+  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_LPDdrCAA_Dis_OFF               (31)
+  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_LPDdrCAA_Dis_WID               ( 1)
+  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_LPDdrCAA_Dis_MSK               (0x80000000)
+  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_LPDdrCAA_Dis_MAX               (0x00000001)
+  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_LPDdrCAA_Dis_DEF               (0x00000000)
+
+#define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_REG                           (0x00001C20)
+  #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_RankEn_OFF                    ( 0)
+  #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_RankEn_WID                    ( 4)
+  #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_RankEn_MSK                    (0x0000000F)
+  #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_RankEn_MAX                    (0x0000000F)
+  #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_RankEn_DEF                    (0x0000000F)
+  #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_OdtDisable_OFF                ( 4)
+  #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_OdtDisable_WID                ( 2)
+  #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_OdtDisable_MSK                (0x00000030)
+  #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_OdtDisable_MAX                (0x00000003)
+  #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_OdtDisable_DEF                (0x00000000)
+  #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_Spare_OFF                     ( 6)
+  #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_Spare_WID                     (26)
+  #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_Spare_MSK                     (0xFFFFFFC0)
+  #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_Spare_MAX                     (0x03FFFFFF)
+  #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_Spare_DEF                     (0x00000000)
+
+#define DDRCTLCH0_CR_DLLPITESTANDADC_REG                             (0x00001C24)
+  #define DDRCTLCH0_CR_DLLPITESTANDADC_RunTest_OFF                     ( 0)
+  #define DDRCTLCH0_CR_DLLPITESTANDADC_RunTest_WID                     ( 1)
+  #define DDRCTLCH0_CR_DLLPITESTANDADC_RunTest_MSK                     (0x00000001)
+  #define DDRCTLCH0_CR_DLLPITESTANDADC_RunTest_MAX                     (0x00000001)
+  #define DDRCTLCH0_CR_DLLPITESTANDADC_RunTest_DEF                     (0x00000000)
+  #define DDRCTLCH0_CR_DLLPITESTANDADC_Load_OFF                        ( 1)
+  #define DDRCTLCH0_CR_DLLPITESTANDADC_Load_WID                        ( 1)
+  #define DDRCTLCH0_CR_DLLPITESTANDADC_Load_MSK                        (0x00000002)
+  #define DDRCTLCH0_CR_DLLPITESTANDADC_Load_MAX                        (0x00000001)
+  #define DDRCTLCH0_CR_DLLPITESTANDADC_Load_DEF                        (0x00000000)
+  #define DDRCTLCH0_CR_DLLPITESTANDADC_ModeHVM_OFF                     ( 2)
+  #define DDRCTLCH0_CR_DLLPITESTANDADC_ModeHVM_WID                     ( 1)
+  #define DDRCTLCH0_CR_DLLPITESTANDADC_ModeHVM_MSK                     (0x00000004)
+  #define DDRCTLCH0_CR_DLLPITESTANDADC_ModeHVM_MAX                     (0x00000001)
+  #define DDRCTLCH0_CR_DLLPITESTANDADC_ModeHVM_DEF                     (0x00000000)
+  #define DDRCTLCH0_CR_DLLPITESTANDADC_ModeDV_OFF                      ( 3)
+  #define DDRCTLCH0_CR_DLLPITESTANDADC_ModeDV_WID                      ( 1)
+  #define DDRCTLCH0_CR_DLLPITESTANDADC_ModeDV_MSK                      (0x00000008)
+  #define DDRCTLCH0_CR_DLLPITESTANDADC_ModeDV_MAX                      (0x00000001)
+  #define DDRCTLCH0_CR_DLLPITESTANDADC_ModeDV_DEF                      (0x00000000)
+  #define DDRCTLCH0_CR_DLLPITESTANDADC_ModeADC_OFF                     ( 4)
+  #define DDRCTLCH0_CR_DLLPITESTANDADC_ModeADC_WID                     ( 1)
+  #define DDRCTLCH0_CR_DLLPITESTANDADC_ModeADC_MSK                     (0x00000010)
+  #define DDRCTLCH0_CR_DLLPITESTANDADC_ModeADC_MAX                     (0x00000001)
+  #define DDRCTLCH0_CR_DLLPITESTANDADC_ModeADC_DEF                     (0x00000000)
+  #define DDRCTLCH0_CR_DLLPITESTANDADC_LoadCount_OFF                   ( 5)
+  #define DDRCTLCH0_CR_DLLPITESTANDADC_LoadCount_WID                   (10)
+  #define DDRCTLCH0_CR_DLLPITESTANDADC_LoadCount_MSK                   (0x00007FE0)
+  #define DDRCTLCH0_CR_DLLPITESTANDADC_LoadCount_MAX                   (0x000003FF)
+  #define DDRCTLCH0_CR_DLLPITESTANDADC_CountStatus_OFF                 (15)
+  #define DDRCTLCH0_CR_DLLPITESTANDADC_CountStatus_WID                 (10)
+  #define DDRCTLCH0_CR_DLLPITESTANDADC_CountStatus_MSK                 (0x01FF8000)
+  #define DDRCTLCH0_CR_DLLPITESTANDADC_CountStatus_MAX                 (0x000003FF)
+  #define DDRCTLCH0_CR_DLLPITESTANDADC_CountStatus_DEF                 (0x00000000)
+  #define DDRCTLCH0_CR_DLLPITESTANDADC_Spare_OFF                       (25)
+  #define DDRCTLCH0_CR_DLLPITESTANDADC_Spare_WID                       ( 7)
+  #define DDRCTLCH0_CR_DLLPITESTANDADC_Spare_MSK                       (0xFE000000)
+  #define DDRCTLCH0_CR_DLLPITESTANDADC_Spare_MAX                       (0x0000007F)
+
+#define DDRCTLCH1_CR_DDRCRCTLCOMP_REG                                (0x00001D10)
+  #define DDRCTLCH1_CR_DDRCRCTLCOMP_Scomp_OFF                          ( 0)
+  #define DDRCTLCH1_CR_DDRCRCTLCOMP_Scomp_WID                          ( 6)
+  #define DDRCTLCH1_CR_DDRCRCTLCOMP_Scomp_MSK                          (0x0000003F)
+  #define DDRCTLCH1_CR_DDRCRCTLCOMP_Scomp_MAX                          (0x0000003F)
+  #define DDRCTLCH1_CR_DDRCRCTLCOMP_Scomp_DEF                          (0x00000000)
+  #define DDRCTLCH1_CR_DDRCRCTLCOMP_TcoComp_OFF                        ( 6)
+  #define DDRCTLCH1_CR_DDRCRCTLCOMP_TcoComp_WID                        ( 6)
+  #define DDRCTLCH1_CR_DDRCRCTLCOMP_TcoComp_MSK                        (0x00000FC0)
+  #define DDRCTLCH1_CR_DDRCRCTLCOMP_TcoComp_MAX                        (0x0000003F)
+  #define DDRCTLCH1_CR_DDRCRCTLCOMP_TcoComp_DEF                        (0x00000000)
+  #define DDRCTLCH1_CR_DDRCRCTLCOMP_RcompDrvUp_OFF                     (12)
+  #define DDRCTLCH1_CR_DDRCRCTLCOMP_RcompDrvUp_WID                     ( 6)
+  #define DDRCTLCH1_CR_DDRCRCTLCOMP_RcompDrvUp_MSK                     (0x0003F000)
+  #define DDRCTLCH1_CR_DDRCRCTLCOMP_RcompDrvUp_MAX                     (0x0000003F)
+  #define DDRCTLCH1_CR_DDRCRCTLCOMP_RcompDrvUp_DEF                     (0x00000000)
+  #define DDRCTLCH1_CR_DDRCRCTLCOMP_RcompDrvDown_OFF                   (18)
+  #define DDRCTLCH1_CR_DDRCRCTLCOMP_RcompDrvDown_WID                   ( 6)
+  #define DDRCTLCH1_CR_DDRCRCTLCOMP_RcompDrvDown_MSK                   (0x00FC0000)
+  #define DDRCTLCH1_CR_DDRCRCTLCOMP_RcompDrvDown_MAX                   (0x0000003F)
+  #define DDRCTLCH1_CR_DDRCRCTLCOMP_RcompDrvDown_DEF                   (0x00000000)
+  #define DDRCTLCH1_CR_DDRCRCTLCOMP_LsComp_OFF                         (24)
+  #define DDRCTLCH1_CR_DDRCRCTLCOMP_LsComp_WID                         ( 3)
+  #define DDRCTLCH1_CR_DDRCRCTLCOMP_LsComp_MSK                         (0x07000000)
+  #define DDRCTLCH1_CR_DDRCRCTLCOMP_LsComp_MAX                         (0x00000007)
+  #define DDRCTLCH1_CR_DDRCRCTLCOMP_LsComp_DEF                         (0x00000000)
+  #define DDRCTLCH1_CR_DDRCRCTLCOMP_Spare_OFF                          (27)
+  #define DDRCTLCH1_CR_DDRCRCTLCOMP_Spare_WID                          ( 5)
+  #define DDRCTLCH1_CR_DDRCRCTLCOMP_Spare_MSK                          (0xF8000000)
+  #define DDRCTLCH1_CR_DDRCRCTLCOMP_Spare_MAX                          (0x0000001F)
+  #define DDRCTLCH1_CR_DDRCRCTLCOMP_Spare_DEF                          (0x00000000)
+
+#define DDRCTLCH1_CR_DDRCRCTLCOMPOFFSET_REG                          (0x00001D14)
+  #define DDRCTLCH1_CR_DDRCRCTLCOMPOFFSET_ScompOffset_OFF              ( 0)
+  #define DDRCTLCH1_CR_DDRCRCTLCOMPOFFSET_ScompOffset_WID              ( 5)
+  #define DDRCTLCH1_CR_DDRCRCTLCOMPOFFSET_ScompOffset_MSK              (0x0000001F)
+  #define DDRCTLCH1_CR_DDRCRCTLCOMPOFFSET_ScompOffset_MAX              (0x0000001F)
+  #define DDRCTLCH1_CR_DDRCRCTLCOMPOFFSET_ScompOffset_DEF              (0x00000000)
+  #define DDRCTLCH1_CR_DDRCRCTLCOMPOFFSET_TcoCompOffset_OFF            ( 5)
+  #define DDRCTLCH1_CR_DDRCRCTLCOMPOFFSET_TcoCompOffset_WID            ( 4)
+  #define DDRCTLCH1_CR_DDRCRCTLCOMPOFFSET_TcoCompOffset_MSK            (0x000001E0)
+  #define DDRCTLCH1_CR_DDRCRCTLCOMPOFFSET_TcoCompOffset_MAX            (0x0000000F)
+  #define DDRCTLCH1_CR_DDRCRCTLCOMPOFFSET_TcoCompOffset_DEF            (0x00000000)
+  #define DDRCTLCH1_CR_DDRCRCTLCOMPOFFSET_RcompDrvUpOffset_OFF         ( 9)
+  #define DDRCTLCH1_CR_DDRCRCTLCOMPOFFSET_RcompDrvUpOffset_WID         ( 4)
+  #define DDRCTLCH1_CR_DDRCRCTLCOMPOFFSET_RcompDrvUpOffset_MSK         (0x00001E00)
+  #define DDRCTLCH1_CR_DDRCRCTLCOMPOFFSET_RcompDrvUpOffset_MAX         (0x0000000F)
+  #define DDRCTLCH1_CR_DDRCRCTLCOMPOFFSET_RcompDrvUpOffset_DEF         (0x00000000)
+  #define DDRCTLCH1_CR_DDRCRCTLCOMPOFFSET_RcompDrvDownOffset_OFF       (13)
+  #define DDRCTLCH1_CR_DDRCRCTLCOMPOFFSET_RcompDrvDownOffset_WID       ( 4)
+  #define DDRCTLCH1_CR_DDRCRCTLCOMPOFFSET_RcompDrvDownOffset_MSK       (0x0001E000)
+  #define DDRCTLCH1_CR_DDRCRCTLCOMPOFFSET_RcompDrvDownOffset_MAX       (0x0000000F)
+  #define DDRCTLCH1_CR_DDRCRCTLCOMPOFFSET_RcompDrvDownOffset_DEF       (0x00000000)
+  #define DDRCTLCH1_CR_DDRCRCTLCOMPOFFSET_Spare_OFF                    (17)
+  #define DDRCTLCH1_CR_DDRCRCTLCOMPOFFSET_Spare_WID                    (15)
+  #define DDRCTLCH1_CR_DDRCRCTLCOMPOFFSET_Spare_MSK                    (0xFFFE0000)
+  #define DDRCTLCH1_CR_DDRCRCTLCOMPOFFSET_Spare_MAX                    (0x00007FFF)
+  #define DDRCTLCH1_CR_DDRCRCTLCOMPOFFSET_Spare_DEF                    (0x00000000)
+
+#define DDRCTLCH1_CR_DDRCRCTLPICODING_REG                            (0x00001D18)
+  #define DDRCTLCH1_CR_DDRCRCTLPICODING_CtlPiCode0_OFF                 ( 0)
+  #define DDRCTLCH1_CR_DDRCRCTLPICODING_CtlPiCode0_WID                 ( 7)
+  #define DDRCTLCH1_CR_DDRCRCTLPICODING_CtlPiCode0_MSK                 (0x0000007F)
+  #define DDRCTLCH1_CR_DDRCRCTLPICODING_CtlPiCode0_MAX                 (0x0000007F)
+  #define DDRCTLCH1_CR_DDRCRCTLPICODING_CtlPiCode0_DEF                 (0x00000000)
+  #define DDRCTLCH1_CR_DDRCRCTLPICODING_CtlPiCode1_OFF                 ( 7)
+  #define DDRCTLCH1_CR_DDRCRCTLPICODING_CtlPiCode1_WID                 ( 7)
+  #define DDRCTLCH1_CR_DDRCRCTLPICODING_CtlPiCode1_MSK                 (0x00003F80)
+  #define DDRCTLCH1_CR_DDRCRCTLPICODING_CtlPiCode1_MAX                 (0x0000007F)
+  #define DDRCTLCH1_CR_DDRCRCTLPICODING_CtlPiCode1_DEF                 (0x00000000)
+  #define DDRCTLCH1_CR_DDRCRCTLPICODING_CtlPiCode2_OFF                 (14)
+  #define DDRCTLCH1_CR_DDRCRCTLPICODING_CtlPiCode2_WID                 ( 7)
+  #define DDRCTLCH1_CR_DDRCRCTLPICODING_CtlPiCode2_MSK                 (0x001FC000)
+  #define DDRCTLCH1_CR_DDRCRCTLPICODING_CtlPiCode2_MAX                 (0x0000007F)
+  #define DDRCTLCH1_CR_DDRCRCTLPICODING_CtlPiCode2_DEF                 (0x00000000)
+  #define DDRCTLCH1_CR_DDRCRCTLPICODING_CtlPiCode3_OFF                 (21)
+  #define DDRCTLCH1_CR_DDRCRCTLPICODING_CtlPiCode3_WID                 ( 7)
+  #define DDRCTLCH1_CR_DDRCRCTLPICODING_CtlPiCode3_MSK                 (0x0FE00000)
+  #define DDRCTLCH1_CR_DDRCRCTLPICODING_CtlPiCode3_MAX                 (0x0000007F)
+  #define DDRCTLCH1_CR_DDRCRCTLPICODING_CtlPiCode3_DEF                 (0x00000000)
+  #define DDRCTLCH1_CR_DDRCRCTLPICODING_CtlXoverEnable_OFF             (28)
+  #define DDRCTLCH1_CR_DDRCRCTLPICODING_CtlXoverEnable_WID             ( 1)
+  #define DDRCTLCH1_CR_DDRCRCTLPICODING_CtlXoverEnable_MSK             (0x10000000)
+  #define DDRCTLCH1_CR_DDRCRCTLPICODING_CtlXoverEnable_MAX             (0x00000001)
+  #define DDRCTLCH1_CR_DDRCRCTLPICODING_CtlXoverEnable_DEF             (0x00000000)
+  #define DDRCTLCH1_CR_DDRCRCTLPICODING_Spare_OFF                      (29)
+  #define DDRCTLCH1_CR_DDRCRCTLPICODING_Spare_WID                      ( 3)
+  #define DDRCTLCH1_CR_DDRCRCTLPICODING_Spare_MSK                      (0xE0000000)
+  #define DDRCTLCH1_CR_DDRCRCTLPICODING_Spare_MAX                      (0x00000007)
+  #define DDRCTLCH1_CR_DDRCRCTLPICODING_Spare_DEF                      (0x00000000)
+
+#define DDRCTLCH1_CR_DDRCRCTLCONTROLS_REG                            (0x00001D1C)
+  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_RefPi_OFF                      ( 0)
+  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_RefPi_WID                      ( 4)
+  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_RefPi_MSK                      (0x0000000F)
+  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_RefPi_MAX                      (0x0000000F)
+  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_RefPi_DEF                      (0x00000000)
+  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_DllMask_OFF                    ( 4)
+  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_DllMask_WID                    ( 2)
+  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_DllMask_MSK                    (0x00000030)
+  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_DllMask_MAX                    (0x00000003)
+  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_DllMask_DEF                    (0x00000000)
+  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_DllRsvd1_OFF                   ( 6)
+  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_DllRsvd1_WID                   ( 1)
+  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_DllRsvd1_MSK                   (0x00000040)
+  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_DllRsvd1_MAX                   (0x00000001)
+  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_DllRsvd1_DEF                   (0x00000000)
+  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_TxOn_OFF                       ( 7)
+  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_TxOn_WID                       ( 1)
+  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_TxOn_MSK                       (0x00000080)
+  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_TxOn_MAX                       (0x00000001)
+  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_TxOn_DEF                       (0x00000000)
+  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_IntClkOn_OFF                   ( 8)
+  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_IntClkOn_WID                   ( 1)
+  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_IntClkOn_MSK                   (0x00000100)
+  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_IntClkOn_MAX                   (0x00000001)
+  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_IntClkOn_DEF                   (0x00000000)
+  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_RepClkOn_OFF                   ( 9)
+  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_RepClkOn_WID                   ( 1)
+  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_RepClkOn_MSK                   (0x00000200)
+  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_RepClkOn_MAX                   (0x00000001)
+  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_RepClkOn_DEF                   (0x00000000)
+  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_IOLBCtl_OFF                    (10)
+  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_IOLBCtl_WID                    ( 2)
+  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_IOLBCtl_MSK                    (0x00000C00)
+  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_IOLBCtl_MAX                    (0x00000003)
+  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_IOLBCtl_DEF                    (0x00000000)
+  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_OdtMode_OFF                    (12)
+  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_OdtMode_WID                    ( 1)
+  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_OdtMode_MSK                    (0x00001000)
+  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_OdtMode_MAX                    (0x00000001)
+  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_OdtMode_DEF                    (0x00000000)
+  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_CmdTxEq_OFF                    (13)
+  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_CmdTxEq_WID                    ( 2)
+  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_CmdTxEq_MSK                    (0x00006000)
+  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_CmdTxEq_MAX                    (0x00000003)
+  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_CmdTxEq_DEF                    (0x00000000)
+  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_EarlyWeakDrive_OFF             (15)
+  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_EarlyWeakDrive_WID             ( 2)
+  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_EarlyWeakDrive_MSK             (0x00018000)
+  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_EarlyWeakDrive_MAX             (0x00000003)
+  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_EarlyWeakDrive_DEF             (0x00000000)
+  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_CtlTxEq_OFF                    (17)
+  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_CtlTxEq_WID                    ( 2)
+  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_CtlTxEq_MSK                    (0x00060000)
+  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_CtlTxEq_MAX                    (0x00000003)
+  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_CtlTxEq_DEF                    (0x00000000)
+  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_CtlSRDrv_OFF                   (19)
+  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_CtlSRDrv_WID                   ( 2)
+  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_CtlSRDrv_MSK                   (0x00180000)
+  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_CtlSRDrv_MAX                   (0x00000003)
+  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_CtlSRDrv_DEF                   (0x00000000)
+  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_RxVref_OFF                     (21)
+  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_RxVref_WID                     ( 6)
+  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_RxVref_MSK                     (0x07E00000)
+  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_RxVref_MAX                     (0x0000003F)
+  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_RxVref_DEF                     (0x00000000)
+  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_VccddqHi_OFF                   (27)
+  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_VccddqHi_WID                   ( 1)
+  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_VccddqHi_MSK                   (0x08000000)
+  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_VccddqHi_MAX                   (0x00000001)
+  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_VccddqHi_DEF                   (0x00000000)
+  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_DllWeakLock_OFF                (28)
+  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_DllWeakLock_WID                ( 1)
+  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_DllWeakLock_MSK                (0x10000000)
+  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_DllWeakLock_MAX                (0x00000001)
+  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_DllWeakLock_DEF                (0x00000000)
+  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_LPDDR_Mode_OFF                 (29)
+  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_LPDDR_Mode_WID                 ( 1)
+  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_LPDDR_Mode_MSK                 (0x20000000)
+  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_LPDDR_Mode_MAX                 (0x00000001)
+  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_LPDDR_Mode_DEF                 (0x00000000)
+  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_LaDrvEnOvrd_OFF                (30)
+  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_LaDrvEnOvrd_WID                ( 1)
+  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_LaDrvEnOvrd_MSK                (0x40000000)
+  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_LaDrvEnOvrd_MAX                (0x00000001)
+  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_LaDrvEnOvrd_DEF                (0x00000000)
+  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_LPDdrCAA_Dis_OFF               (31)
+  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_LPDdrCAA_Dis_WID               ( 1)
+  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_LPDdrCAA_Dis_MSK               (0x80000000)
+  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_LPDdrCAA_Dis_MAX               (0x00000001)
+  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_LPDdrCAA_Dis_DEF               (0x00000000)
+
+#define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_REG                           (0x00001D20)
+  #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_RankEn_OFF                    ( 0)
+  #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_RankEn_WID                    ( 4)
+  #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_RankEn_MSK                    (0x0000000F)
+  #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_RankEn_MAX                    (0x0000000F)
+  #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_RankEn_DEF                    (0x0000000F)
+  #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_OdtDisable_OFF                ( 4)
+  #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_OdtDisable_WID                ( 2)
+  #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_OdtDisable_MSK                (0x00000030)
+  #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_OdtDisable_MAX                (0x00000003)
+  #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_OdtDisable_DEF                (0x00000000)
+  #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_Spare_OFF                     ( 6)
+  #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_Spare_WID                     (26)
+  #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_Spare_MSK                     (0xFFFFFFC0)
+  #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_Spare_MAX                     (0x03FFFFFF)
+  #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_Spare_DEF                     (0x00000000)
+
+#define DDRCTLCH1_CR_DLLPITESTANDADC_REG                             (0x00001D24)
+  #define DDRCTLCH1_CR_DLLPITESTANDADC_RunTest_OFF                     ( 0)
+  #define DDRCTLCH1_CR_DLLPITESTANDADC_RunTest_WID                     ( 1)
+  #define DDRCTLCH1_CR_DLLPITESTANDADC_RunTest_MSK                     (0x00000001)
+  #define DDRCTLCH1_CR_DLLPITESTANDADC_RunTest_MAX                     (0x00000001)
+  #define DDRCTLCH1_CR_DLLPITESTANDADC_RunTest_DEF                     (0x00000000)
+  #define DDRCTLCH1_CR_DLLPITESTANDADC_Load_OFF                        ( 1)
+  #define DDRCTLCH1_CR_DLLPITESTANDADC_Load_WID                        ( 1)
+  #define DDRCTLCH1_CR_DLLPITESTANDADC_Load_MSK                        (0x00000002)
+  #define DDRCTLCH1_CR_DLLPITESTANDADC_Load_MAX                        (0x00000001)
+  #define DDRCTLCH1_CR_DLLPITESTANDADC_Load_DEF                        (0x00000000)
+  #define DDRCTLCH1_CR_DLLPITESTANDADC_ModeHVM_OFF                     ( 2)
+  #define DDRCTLCH1_CR_DLLPITESTANDADC_ModeHVM_WID                     ( 1)
+  #define DDRCTLCH1_CR_DLLPITESTANDADC_ModeHVM_MSK                     (0x00000004)
+  #define DDRCTLCH1_CR_DLLPITESTANDADC_ModeHVM_MAX                     (0x00000001)
+  #define DDRCTLCH1_CR_DLLPITESTANDADC_ModeHVM_DEF                     (0x00000000)
+  #define DDRCTLCH1_CR_DLLPITESTANDADC_ModeDV_OFF                      ( 3)
+  #define DDRCTLCH1_CR_DLLPITESTANDADC_ModeDV_WID                      ( 1)
+  #define DDRCTLCH1_CR_DLLPITESTANDADC_ModeDV_MSK                      (0x00000008)
+  #define DDRCTLCH1_CR_DLLPITESTANDADC_ModeDV_MAX                      (0x00000001)
+  #define DDRCTLCH1_CR_DLLPITESTANDADC_ModeDV_DEF                      (0x00000000)
+  #define DDRCTLCH1_CR_DLLPITESTANDADC_ModeADC_OFF                     ( 4)
+  #define DDRCTLCH1_CR_DLLPITESTANDADC_ModeADC_WID                     ( 1)
+  #define DDRCTLCH1_CR_DLLPITESTANDADC_ModeADC_MSK                     (0x00000010)
+  #define DDRCTLCH1_CR_DLLPITESTANDADC_ModeADC_MAX                     (0x00000001)
+  #define DDRCTLCH1_CR_DLLPITESTANDADC_ModeADC_DEF                     (0x00000000)
+  #define DDRCTLCH1_CR_DLLPITESTANDADC_LoadCount_OFF                   ( 5)
+  #define DDRCTLCH1_CR_DLLPITESTANDADC_LoadCount_WID                   (10)
+  #define DDRCTLCH1_CR_DLLPITESTANDADC_LoadCount_MSK                   (0x00007FE0)
+  #define DDRCTLCH1_CR_DLLPITESTANDADC_LoadCount_MAX                   (0x000003FF)
+  #define DDRCTLCH1_CR_DLLPITESTANDADC_CountStatus_OFF                 (15)
+  #define DDRCTLCH1_CR_DLLPITESTANDADC_CountStatus_WID                 (10)
+  #define DDRCTLCH1_CR_DLLPITESTANDADC_CountStatus_MSK                 (0x01FF8000)
+  #define DDRCTLCH1_CR_DLLPITESTANDADC_CountStatus_MAX                 (0x000003FF)
+  #define DDRCTLCH1_CR_DLLPITESTANDADC_CountStatus_DEF                 (0x00000000)
+  #define DDRCTLCH1_CR_DLLPITESTANDADC_Spare_OFF                       (25)
+  #define DDRCTLCH1_CR_DLLPITESTANDADC_Spare_WID                       ( 7)
+  #define DDRCTLCH1_CR_DLLPITESTANDADC_Spare_MSK                       (0xFE000000)
+  #define DDRCTLCH1_CR_DLLPITESTANDADC_Spare_MAX                       (0x0000007F)
+
+#pragma pack(pop)
+#endif  // __McIoCkeCtl_h__
diff --git a/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcRegisters/McIoClk.h b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcRegisters/McIoClk.h
new file mode 100644
index 0000000..a190ed0
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcRegisters/McIoClk.h
@@ -0,0 +1,988 @@
+/** @file
+  This file was automatically generated. Modify at your own risk.
+
+@copyright
+  Copyright (c) 2010 - 2012 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement
+**/
+#ifndef __McIoClk_h__
+#define __McIoClk_h__
+
+#pragma pack(push, 1)
+#include "MrcTypes.h"
+
+typedef union {
+  struct {
+    U32 RankEn                                  :  4;  // Bits 3:0
+    U32 Spare                                   :  28;  // Bits 31:4
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRCLK_CR_DDRCRCLKRANKSUSED_STRUCT;
+
+typedef union {
+  struct {
+    U32 Scomp                                   :  5;  // Bits 4:0
+    U32 TcoComp                                 :  6;  // Bits 10:5
+    U32 RcompDrvUp                              :  6;  // Bits 16:11
+    U32 RcompDrvDown                            :  6;  // Bits 22:17
+    U32 LsComp                                  :  3;  // Bits 25:23
+    U32 Spare                                   :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRCLK_CR_DDRCRCLKCOMP_STRUCT;
+
+typedef union {
+  struct {
+    U32 ScompOffset                             :  4;  // Bits 3:0
+    U32 TcoCompOffset                           :  4;  // Bits 7:4
+    U32 RcompDrvUpOffset                        :  4;  // Bits 11:8
+    U32 RcompDrvDownOffset                      :  4;  // Bits 15:12
+    U32 Spare                                   :  16;  // Bits 31:16
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRCLK_CR_DDRCRCLKCOMPOFFSET_STRUCT;
+
+typedef union {
+  struct {
+    U32 PiSettingRank0                          :  7;  // Bits 6:0
+    U32 PiSettingRank1                          :  7;  // Bits 13:7
+    U32 PiSettingRank2                          :  7;  // Bits 20:14
+    U32 PiSettingRank3                          :  7;  // Bits 27:21
+    U32 Spare                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRCLK_CR_DDRCRCLKPICODE_STRUCT;
+
+typedef union {
+  struct {
+    U32 RefPi                                   :  4;  // Bits 3:0
+    U32 DllMask                                 :  2;  // Bits 5:4
+    U32 DllRsvd1                                :  1;  // Bits 6:6
+    U32 TxOn                                    :  1;  // Bits 7:7
+    U32 IntClkOn                                :  1;  // Bits 8:8
+    U32 RepClkOn                                :  1;  // Bits 9:9
+    U32 IOLBCtl                                 :  2;  // Bits 11:10
+    U32 OdtMode                                 :  1;  // Bits 12:12
+    U32 Reserved                                :  8;  // Bits 20:13
+    U32 RxVref                                  :  6;  // Bits 26:21
+    U32 VccddqHi                                :  1;  // Bits 27:27
+    U32 DllWeakLock                             :  1;  // Bits 28:28
+    U32 LPDDR_Mode                              :  1;  // Bits 29:29
+    U32 Spare                                   :  2;  // Bits 31:30
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRCLK_CR_DDRCRCLKCONTROLS_STRUCT;
+
+typedef union {
+  struct {
+    U32 RunTest                                 :  1;  // Bits 0:0
+    U32 Load                                    :  1;  // Bits 1:1
+    U32 ModeHVM                                 :  1;  // Bits 2:2
+    U32 ModeDV                                  :  1;  // Bits 3:3
+    U32 ModeADC                                 :  1;  // Bits 4:4
+    U32 LoadCount                               :  10;  // Bits 14:5
+    U32 CountStatus                             :  10;  // Bits 24:15
+    U32 Spare                                   :  7;  // Bits 31:25
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRCLK_CR_DLLPITESTANDADC_STRUCT;
+
+typedef union {
+  struct {
+    U32 DllCB                                   :  2;  // Bits 1:0
+    U32 Spare                                   :  30;  // Bits 31:2
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRCLK_CR_DDRCBSTATUS_STRUCT;
+
+typedef union {
+  struct {
+    U32 RankEn                                  :  4;  // Bits 3:0
+    U32 Spare                                   :  28;  // Bits 31:4
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRCLKCH0_CR_DDRCRCLKRANKSUSED_STRUCT;
+
+typedef union {
+  struct {
+    U32 Scomp                                   :  5;  // Bits 4:0
+    U32 TcoComp                                 :  6;  // Bits 10:5
+    U32 RcompDrvUp                              :  6;  // Bits 16:11
+    U32 RcompDrvDown                            :  6;  // Bits 22:17
+    U32 LsComp                                  :  3;  // Bits 25:23
+    U32 Spare                                   :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRCLKCH0_CR_DDRCRCLKCOMP_STRUCT;
+
+typedef union {
+  struct {
+    U32 ScompOffset                             :  4;  // Bits 3:0
+    U32 TcoCompOffset                           :  4;  // Bits 7:4
+    U32 RcompDrvUpOffset                        :  4;  // Bits 11:8
+    U32 RcompDrvDownOffset                      :  4;  // Bits 15:12
+    U32 Spare                                   :  16;  // Bits 31:16
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRCLKCH0_CR_DDRCRCLKCOMPOFFSET_STRUCT;
+
+typedef union {
+  struct {
+    U32 PiSettingRank0                          :  7;  // Bits 6:0
+    U32 PiSettingRank1                          :  7;  // Bits 13:7
+    U32 PiSettingRank2                          :  7;  // Bits 20:14
+    U32 PiSettingRank3                          :  7;  // Bits 27:21
+    U32 Spare                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRCLKCH0_CR_DDRCRCLKPICODE_STRUCT;
+
+typedef union {
+  struct {
+    U32 RefPi                                   :  4;  // Bits 3:0
+    U32 DllMask                                 :  2;  // Bits 5:4
+    U32 DllRsvd1                                :  1;  // Bits 6:6
+    U32 TxOn                                    :  1;  // Bits 7:7
+    U32 IntClkOn                                :  1;  // Bits 8:8
+    U32 RepClkOn                                :  1;  // Bits 9:9
+    U32 IOLBCtl                                 :  2;  // Bits 11:10
+    U32 OdtMode                                 :  1;  // Bits 12:12
+    U32 Reserved                                :  8;  // Bits 20:13
+    U32 RxVref                                  :  6;  // Bits 26:21
+    U32 VccddqHi                                :  1;  // Bits 27:27
+    U32 DllWeakLock                             :  1;  // Bits 28:28
+    U32 LPDDR_Mode                              :  1;  // Bits 29:29
+    U32 Spare                                   :  2;  // Bits 31:30
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRCLKCH0_CR_DDRCRCLKCONTROLS_STRUCT;
+
+typedef union {
+  struct {
+    U32 RunTest                                 :  1;  // Bits 0:0
+    U32 Load                                    :  1;  // Bits 1:1
+    U32 ModeHVM                                 :  1;  // Bits 2:2
+    U32 ModeDV                                  :  1;  // Bits 3:3
+    U32 ModeADC                                 :  1;  // Bits 4:4
+    U32 LoadCount                               :  10;  // Bits 14:5
+    U32 CountStatus                             :  10;  // Bits 24:15
+    U32 Spare                                   :  7;  // Bits 31:25
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRCLKCH0_CR_DLLPITESTANDADC_STRUCT;
+
+typedef union {
+  struct {
+    U32 DllCB                                   :  2;  // Bits 1:0
+    U32 Spare                                   :  30;  // Bits 31:2
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRCLKCH0_CR_DDRCBSTATUS_STRUCT;
+
+typedef union {
+  struct {
+    U32 RankEn                                  :  4;  // Bits 3:0
+    U32 Spare                                   :  28;  // Bits 31:4
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRCLKCH1_CR_DDRCRCLKRANKSUSED_STRUCT;
+
+typedef union {
+  struct {
+    U32 Scomp                                   :  5;  // Bits 4:0
+    U32 TcoComp                                 :  6;  // Bits 10:5
+    U32 RcompDrvUp                              :  6;  // Bits 16:11
+    U32 RcompDrvDown                            :  6;  // Bits 22:17
+    U32 LsComp                                  :  3;  // Bits 25:23
+    U32 Spare                                   :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRCLKCH1_CR_DDRCRCLKCOMP_STRUCT;
+
+typedef union {
+  struct {
+    U32 ScompOffset                             :  4;  // Bits 3:0
+    U32 TcoCompOffset                           :  4;  // Bits 7:4
+    U32 RcompDrvUpOffset                        :  4;  // Bits 11:8
+    U32 RcompDrvDownOffset                      :  4;  // Bits 15:12
+    U32 Spare                                   :  16;  // Bits 31:16
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRCLKCH1_CR_DDRCRCLKCOMPOFFSET_STRUCT;
+
+typedef union {
+  struct {
+    U32 PiSettingRank0                          :  7;  // Bits 6:0
+    U32 PiSettingRank1                          :  7;  // Bits 13:7
+    U32 PiSettingRank2                          :  7;  // Bits 20:14
+    U32 PiSettingRank3                          :  7;  // Bits 27:21
+    U32 Spare                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRCLKCH1_CR_DDRCRCLKPICODE_STRUCT;
+
+typedef union {
+  struct {
+    U32 RefPi                                   :  4;  // Bits 3:0
+    U32 DllMask                                 :  2;  // Bits 5:4
+    U32 DllRsvd1                                :  1;  // Bits 6:6
+    U32 TxOn                                    :  1;  // Bits 7:7
+    U32 IntClkOn                                :  1;  // Bits 8:8
+    U32 RepClkOn                                :  1;  // Bits 9:9
+    U32 IOLBCtl                                 :  2;  // Bits 11:10
+    U32 OdtMode                                 :  1;  // Bits 12:12
+    U32 Reserved                                :  8;  // Bits 20:13
+    U32 RxVref                                  :  6;  // Bits 26:21
+    U32 VccddqHi                                :  1;  // Bits 27:27
+    U32 DllWeakLock                             :  1;  // Bits 28:28
+    U32 LPDDR_Mode                              :  1;  // Bits 29:29
+    U32 Spare                                   :  2;  // Bits 31:30
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRCLKCH1_CR_DDRCRCLKCONTROLS_STRUCT;
+
+typedef union {
+  struct {
+    U32 RunTest                                 :  1;  // Bits 0:0
+    U32 Load                                    :  1;  // Bits 1:1
+    U32 ModeHVM                                 :  1;  // Bits 2:2
+    U32 ModeDV                                  :  1;  // Bits 3:3
+    U32 ModeADC                                 :  1;  // Bits 4:4
+    U32 LoadCount                               :  10;  // Bits 14:5
+    U32 CountStatus                             :  10;  // Bits 24:15
+    U32 Spare                                   :  7;  // Bits 31:25
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRCLKCH1_CR_DLLPITESTANDADC_STRUCT;
+
+typedef union {
+  struct {
+    U32 DllCB                                   :  2;  // Bits 1:0
+    U32 Spare                                   :  30;  // Bits 31:2
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRCLKCH1_CR_DDRCBSTATUS_STRUCT;
+
+#define DDRCLK_CR_DDRCRCLKRANKSUSED_REG                              (0x00003900)
+  #define DDRCLK_CR_DDRCRCLKRANKSUSED_RankEn_OFF                       ( 0)
+  #define DDRCLK_CR_DDRCRCLKRANKSUSED_RankEn_WID                       ( 4)
+  #define DDRCLK_CR_DDRCRCLKRANKSUSED_RankEn_MSK                       (0x0000000F)
+  #define DDRCLK_CR_DDRCRCLKRANKSUSED_RankEn_MAX                       (0x0000000F)
+  #define DDRCLK_CR_DDRCRCLKRANKSUSED_RankEn_DEF                       (0x0000000F)
+  #define DDRCLK_CR_DDRCRCLKRANKSUSED_Spare_OFF                        ( 4)
+  #define DDRCLK_CR_DDRCRCLKRANKSUSED_Spare_WID                        (28)
+  #define DDRCLK_CR_DDRCRCLKRANKSUSED_Spare_MSK                        (0xFFFFFFF0)
+  #define DDRCLK_CR_DDRCRCLKRANKSUSED_Spare_MAX                        (0x0FFFFFFF)
+  #define DDRCLK_CR_DDRCRCLKRANKSUSED_Spare_DEF                        (0x00000000)
+
+#define DDRCLK_CR_DDRCRCLKCOMP_REG                                   (0x00003904)
+  #define DDRCLK_CR_DDRCRCLKCOMP_Scomp_OFF                             ( 0)
+  #define DDRCLK_CR_DDRCRCLKCOMP_Scomp_WID                             ( 5)
+  #define DDRCLK_CR_DDRCRCLKCOMP_Scomp_MSK                             (0x0000001F)
+  #define DDRCLK_CR_DDRCRCLKCOMP_Scomp_MAX                             (0x0000001F)
+  #define DDRCLK_CR_DDRCRCLKCOMP_Scomp_DEF                             (0x00000000)
+  #define DDRCLK_CR_DDRCRCLKCOMP_TcoComp_OFF                           ( 5)
+  #define DDRCLK_CR_DDRCRCLKCOMP_TcoComp_WID                           ( 6)
+  #define DDRCLK_CR_DDRCRCLKCOMP_TcoComp_MSK                           (0x000007E0)
+  #define DDRCLK_CR_DDRCRCLKCOMP_TcoComp_MAX                           (0x0000003F)
+  #define DDRCLK_CR_DDRCRCLKCOMP_TcoComp_DEF                           (0x00000000)
+  #define DDRCLK_CR_DDRCRCLKCOMP_RcompDrvUp_OFF                        (11)
+  #define DDRCLK_CR_DDRCRCLKCOMP_RcompDrvUp_WID                        ( 6)
+  #define DDRCLK_CR_DDRCRCLKCOMP_RcompDrvUp_MSK                        (0x0001F800)
+  #define DDRCLK_CR_DDRCRCLKCOMP_RcompDrvUp_MAX                        (0x0000003F)
+  #define DDRCLK_CR_DDRCRCLKCOMP_RcompDrvUp_DEF                        (0x00000000)
+  #define DDRCLK_CR_DDRCRCLKCOMP_RcompDrvDown_OFF                      (17)
+  #define DDRCLK_CR_DDRCRCLKCOMP_RcompDrvDown_WID                      ( 6)
+  #define DDRCLK_CR_DDRCRCLKCOMP_RcompDrvDown_MSK                      (0x007E0000)
+  #define DDRCLK_CR_DDRCRCLKCOMP_RcompDrvDown_MAX                      (0x0000003F)
+  #define DDRCLK_CR_DDRCRCLKCOMP_RcompDrvDown_DEF                      (0x00000000)
+  #define DDRCLK_CR_DDRCRCLKCOMP_LsComp_OFF                            (23)
+  #define DDRCLK_CR_DDRCRCLKCOMP_LsComp_WID                            ( 3)
+  #define DDRCLK_CR_DDRCRCLKCOMP_LsComp_MSK                            (0x03800000)
+  #define DDRCLK_CR_DDRCRCLKCOMP_LsComp_MAX                            (0x00000007)
+  #define DDRCLK_CR_DDRCRCLKCOMP_LsComp_DEF                            (0x00000004)
+  #define DDRCLK_CR_DDRCRCLKCOMP_Spare_OFF                             (26)
+  #define DDRCLK_CR_DDRCRCLKCOMP_Spare_WID                             ( 6)
+  #define DDRCLK_CR_DDRCRCLKCOMP_Spare_MSK                             (0xFC000000)
+  #define DDRCLK_CR_DDRCRCLKCOMP_Spare_MAX                             (0x0000003F)
+  #define DDRCLK_CR_DDRCRCLKCOMP_Spare_DEF                             (0x00000000)
+
+#define DDRCLK_CR_DDRCRCLKCOMPOFFSET_REG                             (0x00003908)
+  #define DDRCLK_CR_DDRCRCLKCOMPOFFSET_ScompOffset_OFF                 ( 0)
+  #define DDRCLK_CR_DDRCRCLKCOMPOFFSET_ScompOffset_WID                 ( 4)
+  #define DDRCLK_CR_DDRCRCLKCOMPOFFSET_ScompOffset_MSK                 (0x0000000F)
+  #define DDRCLK_CR_DDRCRCLKCOMPOFFSET_ScompOffset_MAX                 (0x0000000F)
+  #define DDRCLK_CR_DDRCRCLKCOMPOFFSET_ScompOffset_DEF                 (0x00000000)
+  #define DDRCLK_CR_DDRCRCLKCOMPOFFSET_TcoCompOffset_OFF               ( 4)
+  #define DDRCLK_CR_DDRCRCLKCOMPOFFSET_TcoCompOffset_WID               ( 4)
+  #define DDRCLK_CR_DDRCRCLKCOMPOFFSET_TcoCompOffset_MSK               (0x000000F0)
+  #define DDRCLK_CR_DDRCRCLKCOMPOFFSET_TcoCompOffset_MAX               (0x0000000F)
+  #define DDRCLK_CR_DDRCRCLKCOMPOFFSET_TcoCompOffset_DEF               (0x00000000)
+  #define DDRCLK_CR_DDRCRCLKCOMPOFFSET_RcompDrvUpOffset_OFF            ( 8)
+  #define DDRCLK_CR_DDRCRCLKCOMPOFFSET_RcompDrvUpOffset_WID            ( 4)
+  #define DDRCLK_CR_DDRCRCLKCOMPOFFSET_RcompDrvUpOffset_MSK            (0x00000F00)
+  #define DDRCLK_CR_DDRCRCLKCOMPOFFSET_RcompDrvUpOffset_MAX            (0x0000000F)
+  #define DDRCLK_CR_DDRCRCLKCOMPOFFSET_RcompDrvUpOffset_DEF            (0x00000000)
+  #define DDRCLK_CR_DDRCRCLKCOMPOFFSET_RcompDrvDownOffset_OFF          (12)
+  #define DDRCLK_CR_DDRCRCLKCOMPOFFSET_RcompDrvDownOffset_WID          ( 4)
+  #define DDRCLK_CR_DDRCRCLKCOMPOFFSET_RcompDrvDownOffset_MSK          (0x0000F000)
+  #define DDRCLK_CR_DDRCRCLKCOMPOFFSET_RcompDrvDownOffset_MAX          (0x0000000F)
+  #define DDRCLK_CR_DDRCRCLKCOMPOFFSET_RcompDrvDownOffset_DEF          (0x00000000)
+  #define DDRCLK_CR_DDRCRCLKCOMPOFFSET_Spare_OFF                       (16)
+  #define DDRCLK_CR_DDRCRCLKCOMPOFFSET_Spare_WID                       (16)
+  #define DDRCLK_CR_DDRCRCLKCOMPOFFSET_Spare_MSK                       (0xFFFF0000)
+  #define DDRCLK_CR_DDRCRCLKCOMPOFFSET_Spare_MAX                       (0x0000FFFF)
+  #define DDRCLK_CR_DDRCRCLKCOMPOFFSET_Spare_DEF                       (0x00000000)
+
+#define DDRCLK_CR_DDRCRCLKPICODE_REG                                 (0x0000390C)
+  #define DDRCLK_CR_DDRCRCLKPICODE_PiSettingRank0_OFF                  ( 0)
+  #define DDRCLK_CR_DDRCRCLKPICODE_PiSettingRank0_WID                  ( 7)
+  #define DDRCLK_CR_DDRCRCLKPICODE_PiSettingRank0_MSK                  (0x0000007F)
+  #define DDRCLK_CR_DDRCRCLKPICODE_PiSettingRank0_MAX                  (0x0000007F)
+  #define DDRCLK_CR_DDRCRCLKPICODE_PiSettingRank0_DEF                  (0x00000000)
+  #define DDRCLK_CR_DDRCRCLKPICODE_PiSettingRank1_OFF                  ( 7)
+  #define DDRCLK_CR_DDRCRCLKPICODE_PiSettingRank1_WID                  ( 7)
+  #define DDRCLK_CR_DDRCRCLKPICODE_PiSettingRank1_MSK                  (0x00003F80)
+  #define DDRCLK_CR_DDRCRCLKPICODE_PiSettingRank1_MAX                  (0x0000007F)
+  #define DDRCLK_CR_DDRCRCLKPICODE_PiSettingRank1_DEF                  (0x00000000)
+  #define DDRCLK_CR_DDRCRCLKPICODE_PiSettingRank2_OFF                  (14)
+  #define DDRCLK_CR_DDRCRCLKPICODE_PiSettingRank2_WID                  ( 7)
+  #define DDRCLK_CR_DDRCRCLKPICODE_PiSettingRank2_MSK                  (0x001FC000)
+  #define DDRCLK_CR_DDRCRCLKPICODE_PiSettingRank2_MAX                  (0x0000007F)
+  #define DDRCLK_CR_DDRCRCLKPICODE_PiSettingRank2_DEF                  (0x00000000)
+  #define DDRCLK_CR_DDRCRCLKPICODE_PiSettingRank3_OFF                  (21)
+  #define DDRCLK_CR_DDRCRCLKPICODE_PiSettingRank3_WID                  ( 7)
+  #define DDRCLK_CR_DDRCRCLKPICODE_PiSettingRank3_MSK                  (0x0FE00000)
+  #define DDRCLK_CR_DDRCRCLKPICODE_PiSettingRank3_MAX                  (0x0000007F)
+  #define DDRCLK_CR_DDRCRCLKPICODE_PiSettingRank3_DEF                  (0x00000000)
+  #define DDRCLK_CR_DDRCRCLKPICODE_Spare_OFF                           (28)
+  #define DDRCLK_CR_DDRCRCLKPICODE_Spare_WID                           ( 4)
+  #define DDRCLK_CR_DDRCRCLKPICODE_Spare_MSK                           (0xF0000000)
+  #define DDRCLK_CR_DDRCRCLKPICODE_Spare_MAX                           (0x0000000F)
+  #define DDRCLK_CR_DDRCRCLKPICODE_Spare_DEF                           (0x00000000)
+
+#define DDRCLK_CR_DDRCRCLKCONTROLS_REG                               (0x00003910)
+  #define DDRCLK_CR_DDRCRCLKCONTROLS_RefPi_OFF                         ( 0)
+  #define DDRCLK_CR_DDRCRCLKCONTROLS_RefPi_WID                         ( 4)
+  #define DDRCLK_CR_DDRCRCLKCONTROLS_RefPi_MSK                         (0x0000000F)
+  #define DDRCLK_CR_DDRCRCLKCONTROLS_RefPi_MAX                         (0x0000000F)
+  #define DDRCLK_CR_DDRCRCLKCONTROLS_RefPi_DEF                         (0x00000000)
+  #define DDRCLK_CR_DDRCRCLKCONTROLS_DllMask_OFF                       ( 4)
+  #define DDRCLK_CR_DDRCRCLKCONTROLS_DllMask_WID                       ( 2)
+  #define DDRCLK_CR_DDRCRCLKCONTROLS_DllMask_MSK                       (0x00000030)
+  #define DDRCLK_CR_DDRCRCLKCONTROLS_DllMask_MAX                       (0x00000003)
+  #define DDRCLK_CR_DDRCRCLKCONTROLS_DllMask_DEF                       (0x00000000)
+  #define DDRCLK_CR_DDRCRCLKCONTROLS_DllRsvd1_OFF                      ( 6)
+  #define DDRCLK_CR_DDRCRCLKCONTROLS_DllRsvd1_WID                      ( 1)
+  #define DDRCLK_CR_DDRCRCLKCONTROLS_DllRsvd1_MSK                      (0x00000040)
+  #define DDRCLK_CR_DDRCRCLKCONTROLS_DllRsvd1_MAX                      (0x00000001)
+  #define DDRCLK_CR_DDRCRCLKCONTROLS_DllRsvd1_DEF                      (0x00000000)
+  #define DDRCLK_CR_DDRCRCLKCONTROLS_TxOn_OFF                          ( 7)
+  #define DDRCLK_CR_DDRCRCLKCONTROLS_TxOn_WID                          ( 1)
+  #define DDRCLK_CR_DDRCRCLKCONTROLS_TxOn_MSK                          (0x00000080)
+  #define DDRCLK_CR_DDRCRCLKCONTROLS_TxOn_MAX                          (0x00000001)
+  #define DDRCLK_CR_DDRCRCLKCONTROLS_TxOn_DEF                          (0x00000000)
+  #define DDRCLK_CR_DDRCRCLKCONTROLS_IntClkOn_OFF                      ( 8)
+  #define DDRCLK_CR_DDRCRCLKCONTROLS_IntClkOn_WID                      ( 1)
+  #define DDRCLK_CR_DDRCRCLKCONTROLS_IntClkOn_MSK                      (0x00000100)
+  #define DDRCLK_CR_DDRCRCLKCONTROLS_IntClkOn_MAX                      (0x00000001)
+  #define DDRCLK_CR_DDRCRCLKCONTROLS_IntClkOn_DEF                      (0x00000000)
+  #define DDRCLK_CR_DDRCRCLKCONTROLS_RepClkOn_OFF                      ( 9)
+  #define DDRCLK_CR_DDRCRCLKCONTROLS_RepClkOn_WID                      ( 1)
+  #define DDRCLK_CR_DDRCRCLKCONTROLS_RepClkOn_MSK                      (0x00000200)
+  #define DDRCLK_CR_DDRCRCLKCONTROLS_RepClkOn_MAX                      (0x00000001)
+  #define DDRCLK_CR_DDRCRCLKCONTROLS_RepClkOn_DEF                      (0x00000000)
+  #define DDRCLK_CR_DDRCRCLKCONTROLS_IOLBCtl_OFF                       (10)
+  #define DDRCLK_CR_DDRCRCLKCONTROLS_IOLBCtl_WID                       ( 2)
+  #define DDRCLK_CR_DDRCRCLKCONTROLS_IOLBCtl_MSK                       (0x00000C00)
+  #define DDRCLK_CR_DDRCRCLKCONTROLS_IOLBCtl_MAX                       (0x00000003)
+  #define DDRCLK_CR_DDRCRCLKCONTROLS_IOLBCtl_DEF                       (0x00000000)
+  #define DDRCLK_CR_DDRCRCLKCONTROLS_OdtMode_OFF                       (12)
+  #define DDRCLK_CR_DDRCRCLKCONTROLS_OdtMode_WID                       ( 1)
+  #define DDRCLK_CR_DDRCRCLKCONTROLS_OdtMode_MSK                       (0x00001000)
+  #define DDRCLK_CR_DDRCRCLKCONTROLS_OdtMode_MAX                       (0x00000001)
+  #define DDRCLK_CR_DDRCRCLKCONTROLS_OdtMode_DEF                       (0x00000000)
+  #define DDRCLK_CR_DDRCRCLKCONTROLS_Reserved_OFF                      (13)
+  #define DDRCLK_CR_DDRCRCLKCONTROLS_Reserved_WID                      ( 8)
+  #define DDRCLK_CR_DDRCRCLKCONTROLS_Reserved_MSK                      (0x001FE000)
+  #define DDRCLK_CR_DDRCRCLKCONTROLS_Reserved_MAX                      (0x000000FF)
+  #define DDRCLK_CR_DDRCRCLKCONTROLS_Reserved_DEF                      (0x00000000)
+  #define DDRCLK_CR_DDRCRCLKCONTROLS_RxVref_OFF                        (21)
+  #define DDRCLK_CR_DDRCRCLKCONTROLS_RxVref_WID                        ( 6)
+  #define DDRCLK_CR_DDRCRCLKCONTROLS_RxVref_MSK                        (0x07E00000)
+  #define DDRCLK_CR_DDRCRCLKCONTROLS_RxVref_MAX                        (0x0000003F)
+  #define DDRCLK_CR_DDRCRCLKCONTROLS_RxVref_DEF                        (0x00000000)
+  #define DDRCLK_CR_DDRCRCLKCONTROLS_VccddqHi_OFF                      (27)
+  #define DDRCLK_CR_DDRCRCLKCONTROLS_VccddqHi_WID                      ( 1)
+  #define DDRCLK_CR_DDRCRCLKCONTROLS_VccddqHi_MSK                      (0x08000000)
+  #define DDRCLK_CR_DDRCRCLKCONTROLS_VccddqHi_MAX                      (0x00000001)
+  #define DDRCLK_CR_DDRCRCLKCONTROLS_VccddqHi_DEF                      (0x00000000)
+  #define DDRCLK_CR_DDRCRCLKCONTROLS_DllWeakLock_OFF                   (28)
+  #define DDRCLK_CR_DDRCRCLKCONTROLS_DllWeakLock_WID                   ( 1)
+  #define DDRCLK_CR_DDRCRCLKCONTROLS_DllWeakLock_MSK                   (0x10000000)
+  #define DDRCLK_CR_DDRCRCLKCONTROLS_DllWeakLock_MAX                   (0x00000001)
+  #define DDRCLK_CR_DDRCRCLKCONTROLS_DllWeakLock_DEF                   (0x00000000)
+  #define DDRCLK_CR_DDRCRCLKCONTROLS_LPDDR_Mode_OFF                    (29)
+  #define DDRCLK_CR_DDRCRCLKCONTROLS_LPDDR_Mode_WID                    ( 1)
+  #define DDRCLK_CR_DDRCRCLKCONTROLS_LPDDR_Mode_MSK                    (0x20000000)
+  #define DDRCLK_CR_DDRCRCLKCONTROLS_LPDDR_Mode_MAX                    (0x00000001)
+  #define DDRCLK_CR_DDRCRCLKCONTROLS_LPDDR_Mode_DEF                    (0x00000000)
+  #define DDRCLK_CR_DDRCRCLKCONTROLS_Spare_OFF                         (30)
+  #define DDRCLK_CR_DDRCRCLKCONTROLS_Spare_WID                         ( 2)
+  #define DDRCLK_CR_DDRCRCLKCONTROLS_Spare_MSK                         (0xC0000000)
+  #define DDRCLK_CR_DDRCRCLKCONTROLS_Spare_MAX                         (0x00000003)
+  #define DDRCLK_CR_DDRCRCLKCONTROLS_Spare_DEF                         (0x00000000)
+
+#define DDRCLK_CR_DLLPITESTANDADC_REG                                (0x00003914)
+  #define DDRCLK_CR_DLLPITESTANDADC_RunTest_OFF                        ( 0)
+  #define DDRCLK_CR_DLLPITESTANDADC_RunTest_WID                        ( 1)
+  #define DDRCLK_CR_DLLPITESTANDADC_RunTest_MSK                        (0x00000001)
+  #define DDRCLK_CR_DLLPITESTANDADC_RunTest_MAX                        (0x00000001)
+  #define DDRCLK_CR_DLLPITESTANDADC_RunTest_DEF                        (0x00000000)
+  #define DDRCLK_CR_DLLPITESTANDADC_Load_OFF                           ( 1)
+  #define DDRCLK_CR_DLLPITESTANDADC_Load_WID                           ( 1)
+  #define DDRCLK_CR_DLLPITESTANDADC_Load_MSK                           (0x00000002)
+  #define DDRCLK_CR_DLLPITESTANDADC_Load_MAX                           (0x00000001)
+  #define DDRCLK_CR_DLLPITESTANDADC_Load_DEF                           (0x00000000)
+  #define DDRCLK_CR_DLLPITESTANDADC_ModeHVM_OFF                        ( 2)
+  #define DDRCLK_CR_DLLPITESTANDADC_ModeHVM_WID                        ( 1)
+  #define DDRCLK_CR_DLLPITESTANDADC_ModeHVM_MSK                        (0x00000004)
+  #define DDRCLK_CR_DLLPITESTANDADC_ModeHVM_MAX                        (0x00000001)
+  #define DDRCLK_CR_DLLPITESTANDADC_ModeHVM_DEF                        (0x00000000)
+  #define DDRCLK_CR_DLLPITESTANDADC_ModeDV_OFF                         ( 3)
+  #define DDRCLK_CR_DLLPITESTANDADC_ModeDV_WID                         ( 1)
+  #define DDRCLK_CR_DLLPITESTANDADC_ModeDV_MSK                         (0x00000008)
+  #define DDRCLK_CR_DLLPITESTANDADC_ModeDV_MAX                         (0x00000001)
+  #define DDRCLK_CR_DLLPITESTANDADC_ModeDV_DEF                         (0x00000000)
+  #define DDRCLK_CR_DLLPITESTANDADC_ModeADC_OFF                        ( 4)
+  #define DDRCLK_CR_DLLPITESTANDADC_ModeADC_WID                        ( 1)
+  #define DDRCLK_CR_DLLPITESTANDADC_ModeADC_MSK                        (0x00000010)
+  #define DDRCLK_CR_DLLPITESTANDADC_ModeADC_MAX                        (0x00000001)
+  #define DDRCLK_CR_DLLPITESTANDADC_ModeADC_DEF                        (0x00000000)
+  #define DDRCLK_CR_DLLPITESTANDADC_LoadCount_OFF                      ( 5)
+  #define DDRCLK_CR_DLLPITESTANDADC_LoadCount_WID                      (10)
+  #define DDRCLK_CR_DLLPITESTANDADC_LoadCount_MSK                      (0x00007FE0)
+  #define DDRCLK_CR_DLLPITESTANDADC_LoadCount_MAX                      (0x000003FF)
+  #define DDRCLK_CR_DLLPITESTANDADC_CountStatus_OFF                    (15)
+  #define DDRCLK_CR_DLLPITESTANDADC_CountStatus_WID                    (10)
+  #define DDRCLK_CR_DLLPITESTANDADC_CountStatus_MSK                    (0x01FF8000)
+  #define DDRCLK_CR_DLLPITESTANDADC_CountStatus_MAX                    (0x000003FF)
+  #define DDRCLK_CR_DLLPITESTANDADC_CountStatus_DEF                    (0x00000000)
+  #define DDRCLK_CR_DLLPITESTANDADC_Spare_OFF                          (25)
+  #define DDRCLK_CR_DLLPITESTANDADC_Spare_WID                          ( 7)
+  #define DDRCLK_CR_DLLPITESTANDADC_Spare_MSK                          (0xFE000000)
+  #define DDRCLK_CR_DLLPITESTANDADC_Spare_MAX                          (0x0000007F)
+
+#define DDRCLK_CR_DDRCBSTATUS_REG                                    (0x00003918)
+  #define DDRCLK_CR_DDRCBSTATUS_DllCB_OFF                              ( 0)
+  #define DDRCLK_CR_DDRCBSTATUS_DllCB_WID                              ( 2)
+  #define DDRCLK_CR_DDRCBSTATUS_DllCB_MSK                              (0x00000003)
+  #define DDRCLK_CR_DDRCBSTATUS_DllCB_MAX                              (0x00000003)
+  #define DDRCLK_CR_DDRCBSTATUS_DllCB_DEF                              (0x00000000)
+  #define DDRCLK_CR_DDRCBSTATUS_Spare_OFF                              ( 2)
+  #define DDRCLK_CR_DDRCBSTATUS_Spare_WID                              (30)
+  #define DDRCLK_CR_DDRCBSTATUS_Spare_MSK                              (0xFFFFFFFC)
+  #define DDRCLK_CR_DDRCBSTATUS_Spare_MAX                              (0x3FFFFFFF)
+  #define DDRCLK_CR_DDRCBSTATUS_Spare_DEF                              (0x00000000)
+
+#define DDRCLKCH0_CR_DDRCRCLKRANKSUSED_REG                           (0x00001800)
+  #define DDRCLKCH0_CR_DDRCRCLKRANKSUSED_RankEn_OFF                    ( 0)
+  #define DDRCLKCH0_CR_DDRCRCLKRANKSUSED_RankEn_WID                    ( 4)
+  #define DDRCLKCH0_CR_DDRCRCLKRANKSUSED_RankEn_MSK                    (0x0000000F)
+  #define DDRCLKCH0_CR_DDRCRCLKRANKSUSED_RankEn_MAX                    (0x0000000F)
+  #define DDRCLKCH0_CR_DDRCRCLKRANKSUSED_RankEn_DEF                    (0x0000000F)
+  #define DDRCLKCH0_CR_DDRCRCLKRANKSUSED_Spare_OFF                     ( 4)
+  #define DDRCLKCH0_CR_DDRCRCLKRANKSUSED_Spare_WID                     (28)
+  #define DDRCLKCH0_CR_DDRCRCLKRANKSUSED_Spare_MSK                     (0xFFFFFFF0)
+  #define DDRCLKCH0_CR_DDRCRCLKRANKSUSED_Spare_MAX                     (0x0FFFFFFF)
+  #define DDRCLKCH0_CR_DDRCRCLKRANKSUSED_Spare_DEF                     (0x00000000)
+
+#define DDRCLKCH0_CR_DDRCRCLKCOMP_REG                                (0x00001804)
+  #define DDRCLKCH0_CR_DDRCRCLKCOMP_Scomp_OFF                          ( 0)
+  #define DDRCLKCH0_CR_DDRCRCLKCOMP_Scomp_WID                          ( 5)
+  #define DDRCLKCH0_CR_DDRCRCLKCOMP_Scomp_MSK                          (0x0000001F)
+  #define DDRCLKCH0_CR_DDRCRCLKCOMP_Scomp_MAX                          (0x0000001F)
+  #define DDRCLKCH0_CR_DDRCRCLKCOMP_Scomp_DEF                          (0x00000000)
+  #define DDRCLKCH0_CR_DDRCRCLKCOMP_TcoComp_OFF                        ( 5)
+  #define DDRCLKCH0_CR_DDRCRCLKCOMP_TcoComp_WID                        ( 6)
+  #define DDRCLKCH0_CR_DDRCRCLKCOMP_TcoComp_MSK                        (0x000007E0)
+  #define DDRCLKCH0_CR_DDRCRCLKCOMP_TcoComp_MAX                        (0x0000003F)
+  #define DDRCLKCH0_CR_DDRCRCLKCOMP_TcoComp_DEF                        (0x00000000)
+  #define DDRCLKCH0_CR_DDRCRCLKCOMP_RcompDrvUp_OFF                     (11)
+  #define DDRCLKCH0_CR_DDRCRCLKCOMP_RcompDrvUp_WID                     ( 6)
+  #define DDRCLKCH0_CR_DDRCRCLKCOMP_RcompDrvUp_MSK                     (0x0001F800)
+  #define DDRCLKCH0_CR_DDRCRCLKCOMP_RcompDrvUp_MAX                     (0x0000003F)
+  #define DDRCLKCH0_CR_DDRCRCLKCOMP_RcompDrvUp_DEF                     (0x00000000)
+  #define DDRCLKCH0_CR_DDRCRCLKCOMP_RcompDrvDown_OFF                   (17)
+  #define DDRCLKCH0_CR_DDRCRCLKCOMP_RcompDrvDown_WID                   ( 6)
+  #define DDRCLKCH0_CR_DDRCRCLKCOMP_RcompDrvDown_MSK                   (0x007E0000)
+  #define DDRCLKCH0_CR_DDRCRCLKCOMP_RcompDrvDown_MAX                   (0x0000003F)
+  #define DDRCLKCH0_CR_DDRCRCLKCOMP_RcompDrvDown_DEF                   (0x00000000)
+  #define DDRCLKCH0_CR_DDRCRCLKCOMP_LsComp_OFF                         (23)
+  #define DDRCLKCH0_CR_DDRCRCLKCOMP_LsComp_WID                         ( 3)
+  #define DDRCLKCH0_CR_DDRCRCLKCOMP_LsComp_MSK                         (0x03800000)
+  #define DDRCLKCH0_CR_DDRCRCLKCOMP_LsComp_MAX                         (0x00000007)
+  #define DDRCLKCH0_CR_DDRCRCLKCOMP_LsComp_DEF                         (0x00000004)
+  #define DDRCLKCH0_CR_DDRCRCLKCOMP_Spare_OFF                          (26)
+  #define DDRCLKCH0_CR_DDRCRCLKCOMP_Spare_WID                          ( 6)
+  #define DDRCLKCH0_CR_DDRCRCLKCOMP_Spare_MSK                          (0xFC000000)
+  #define DDRCLKCH0_CR_DDRCRCLKCOMP_Spare_MAX                          (0x0000003F)
+  #define DDRCLKCH0_CR_DDRCRCLKCOMP_Spare_DEF                          (0x00000000)
+
+#define DDRCLKCH0_CR_DDRCRCLKCOMPOFFSET_REG                          (0x00001808)
+  #define DDRCLKCH0_CR_DDRCRCLKCOMPOFFSET_ScompOffset_OFF              ( 0)
+  #define DDRCLKCH0_CR_DDRCRCLKCOMPOFFSET_ScompOffset_WID              ( 4)
+  #define DDRCLKCH0_CR_DDRCRCLKCOMPOFFSET_ScompOffset_MSK              (0x0000000F)
+  #define DDRCLKCH0_CR_DDRCRCLKCOMPOFFSET_ScompOffset_MAX              (0x0000000F)
+  #define DDRCLKCH0_CR_DDRCRCLKCOMPOFFSET_ScompOffset_DEF              (0x00000000)
+  #define DDRCLKCH0_CR_DDRCRCLKCOMPOFFSET_TcoCompOffset_OFF            ( 4)
+  #define DDRCLKCH0_CR_DDRCRCLKCOMPOFFSET_TcoCompOffset_WID            ( 4)
+  #define DDRCLKCH0_CR_DDRCRCLKCOMPOFFSET_TcoCompOffset_MSK            (0x000000F0)
+  #define DDRCLKCH0_CR_DDRCRCLKCOMPOFFSET_TcoCompOffset_MAX            (0x0000000F)
+  #define DDRCLKCH0_CR_DDRCRCLKCOMPOFFSET_TcoCompOffset_DEF            (0x00000000)
+  #define DDRCLKCH0_CR_DDRCRCLKCOMPOFFSET_RcompDrvUpOffset_OFF         ( 8)
+  #define DDRCLKCH0_CR_DDRCRCLKCOMPOFFSET_RcompDrvUpOffset_WID         ( 4)
+  #define DDRCLKCH0_CR_DDRCRCLKCOMPOFFSET_RcompDrvUpOffset_MSK         (0x00000F00)
+  #define DDRCLKCH0_CR_DDRCRCLKCOMPOFFSET_RcompDrvUpOffset_MAX         (0x0000000F)
+  #define DDRCLKCH0_CR_DDRCRCLKCOMPOFFSET_RcompDrvUpOffset_DEF         (0x00000000)
+  #define DDRCLKCH0_CR_DDRCRCLKCOMPOFFSET_RcompDrvDownOffset_OFF       (12)
+  #define DDRCLKCH0_CR_DDRCRCLKCOMPOFFSET_RcompDrvDownOffset_WID       ( 4)
+  #define DDRCLKCH0_CR_DDRCRCLKCOMPOFFSET_RcompDrvDownOffset_MSK       (0x0000F000)
+  #define DDRCLKCH0_CR_DDRCRCLKCOMPOFFSET_RcompDrvDownOffset_MAX       (0x0000000F)
+  #define DDRCLKCH0_CR_DDRCRCLKCOMPOFFSET_RcompDrvDownOffset_DEF       (0x00000000)
+  #define DDRCLKCH0_CR_DDRCRCLKCOMPOFFSET_Spare_OFF                    (16)
+  #define DDRCLKCH0_CR_DDRCRCLKCOMPOFFSET_Spare_WID                    (16)
+  #define DDRCLKCH0_CR_DDRCRCLKCOMPOFFSET_Spare_MSK                    (0xFFFF0000)
+  #define DDRCLKCH0_CR_DDRCRCLKCOMPOFFSET_Spare_MAX                    (0x0000FFFF)
+  #define DDRCLKCH0_CR_DDRCRCLKCOMPOFFSET_Spare_DEF                    (0x00000000)
+
+#define DDRCLKCH0_CR_DDRCRCLKPICODE_REG                              (0x0000180C)
+  #define DDRCLKCH0_CR_DDRCRCLKPICODE_PiSettingRank0_OFF               ( 0)
+  #define DDRCLKCH0_CR_DDRCRCLKPICODE_PiSettingRank0_WID               ( 7)
+  #define DDRCLKCH0_CR_DDRCRCLKPICODE_PiSettingRank0_MSK               (0x0000007F)
+  #define DDRCLKCH0_CR_DDRCRCLKPICODE_PiSettingRank0_MAX               (0x0000007F)
+  #define DDRCLKCH0_CR_DDRCRCLKPICODE_PiSettingRank0_DEF               (0x00000000)
+  #define DDRCLKCH0_CR_DDRCRCLKPICODE_PiSettingRank1_OFF               ( 7)
+  #define DDRCLKCH0_CR_DDRCRCLKPICODE_PiSettingRank1_WID               ( 7)
+  #define DDRCLKCH0_CR_DDRCRCLKPICODE_PiSettingRank1_MSK               (0x00003F80)
+  #define DDRCLKCH0_CR_DDRCRCLKPICODE_PiSettingRank1_MAX               (0x0000007F)
+  #define DDRCLKCH0_CR_DDRCRCLKPICODE_PiSettingRank1_DEF               (0x00000000)
+  #define DDRCLKCH0_CR_DDRCRCLKPICODE_PiSettingRank2_OFF               (14)
+  #define DDRCLKCH0_CR_DDRCRCLKPICODE_PiSettingRank2_WID               ( 7)
+  #define DDRCLKCH0_CR_DDRCRCLKPICODE_PiSettingRank2_MSK               (0x001FC000)
+  #define DDRCLKCH0_CR_DDRCRCLKPICODE_PiSettingRank2_MAX               (0x0000007F)
+  #define DDRCLKCH0_CR_DDRCRCLKPICODE_PiSettingRank2_DEF               (0x00000000)
+  #define DDRCLKCH0_CR_DDRCRCLKPICODE_PiSettingRank3_OFF               (21)
+  #define DDRCLKCH0_CR_DDRCRCLKPICODE_PiSettingRank3_WID               ( 7)
+  #define DDRCLKCH0_CR_DDRCRCLKPICODE_PiSettingRank3_MSK               (0x0FE00000)
+  #define DDRCLKCH0_CR_DDRCRCLKPICODE_PiSettingRank3_MAX               (0x0000007F)
+  #define DDRCLKCH0_CR_DDRCRCLKPICODE_PiSettingRank3_DEF               (0x00000000)
+  #define DDRCLKCH0_CR_DDRCRCLKPICODE_Spare_OFF                        (28)
+  #define DDRCLKCH0_CR_DDRCRCLKPICODE_Spare_WID                        ( 4)
+  #define DDRCLKCH0_CR_DDRCRCLKPICODE_Spare_MSK                        (0xF0000000)
+  #define DDRCLKCH0_CR_DDRCRCLKPICODE_Spare_MAX                        (0x0000000F)
+  #define DDRCLKCH0_CR_DDRCRCLKPICODE_Spare_DEF                        (0x00000000)
+
+#define DDRCLKCH0_CR_DDRCRCLKCONTROLS_REG                            (0x00001810)
+  #define DDRCLKCH0_CR_DDRCRCLKCONTROLS_RefPi_OFF                      ( 0)
+  #define DDRCLKCH0_CR_DDRCRCLKCONTROLS_RefPi_WID                      ( 4)
+  #define DDRCLKCH0_CR_DDRCRCLKCONTROLS_RefPi_MSK                      (0x0000000F)
+  #define DDRCLKCH0_CR_DDRCRCLKCONTROLS_RefPi_MAX                      (0x0000000F)
+  #define DDRCLKCH0_CR_DDRCRCLKCONTROLS_RefPi_DEF                      (0x00000000)
+  #define DDRCLKCH0_CR_DDRCRCLKCONTROLS_DllMask_OFF                    ( 4)
+  #define DDRCLKCH0_CR_DDRCRCLKCONTROLS_DllMask_WID                    ( 2)
+  #define DDRCLKCH0_CR_DDRCRCLKCONTROLS_DllMask_MSK                    (0x00000030)
+  #define DDRCLKCH0_CR_DDRCRCLKCONTROLS_DllMask_MAX                    (0x00000003)
+  #define DDRCLKCH0_CR_DDRCRCLKCONTROLS_DllMask_DEF                    (0x00000000)
+  #define DDRCLKCH0_CR_DDRCRCLKCONTROLS_DllRsvd1_OFF                   ( 6)
+  #define DDRCLKCH0_CR_DDRCRCLKCONTROLS_DllRsvd1_WID                   ( 1)
+  #define DDRCLKCH0_CR_DDRCRCLKCONTROLS_DllRsvd1_MSK                   (0x00000040)
+  #define DDRCLKCH0_CR_DDRCRCLKCONTROLS_DllRsvd1_MAX                   (0x00000001)
+  #define DDRCLKCH0_CR_DDRCRCLKCONTROLS_DllRsvd1_DEF                   (0x00000000)
+  #define DDRCLKCH0_CR_DDRCRCLKCONTROLS_TxOn_OFF                       ( 7)
+  #define DDRCLKCH0_CR_DDRCRCLKCONTROLS_TxOn_WID                       ( 1)
+  #define DDRCLKCH0_CR_DDRCRCLKCONTROLS_TxOn_MSK                       (0x00000080)
+  #define DDRCLKCH0_CR_DDRCRCLKCONTROLS_TxOn_MAX                       (0x00000001)
+  #define DDRCLKCH0_CR_DDRCRCLKCONTROLS_TxOn_DEF                       (0x00000000)
+  #define DDRCLKCH0_CR_DDRCRCLKCONTROLS_IntClkOn_OFF                   ( 8)
+  #define DDRCLKCH0_CR_DDRCRCLKCONTROLS_IntClkOn_WID                   ( 1)
+  #define DDRCLKCH0_CR_DDRCRCLKCONTROLS_IntClkOn_MSK                   (0x00000100)
+  #define DDRCLKCH0_CR_DDRCRCLKCONTROLS_IntClkOn_MAX                   (0x00000001)
+  #define DDRCLKCH0_CR_DDRCRCLKCONTROLS_IntClkOn_DEF                   (0x00000000)
+  #define DDRCLKCH0_CR_DDRCRCLKCONTROLS_RepClkOn_OFF                   ( 9)
+  #define DDRCLKCH0_CR_DDRCRCLKCONTROLS_RepClkOn_WID                   ( 1)
+  #define DDRCLKCH0_CR_DDRCRCLKCONTROLS_RepClkOn_MSK                   (0x00000200)
+  #define DDRCLKCH0_CR_DDRCRCLKCONTROLS_RepClkOn_MAX                   (0x00000001)
+  #define DDRCLKCH0_CR_DDRCRCLKCONTROLS_RepClkOn_DEF                   (0x00000000)
+  #define DDRCLKCH0_CR_DDRCRCLKCONTROLS_IOLBCtl_OFF                    (10)
+  #define DDRCLKCH0_CR_DDRCRCLKCONTROLS_IOLBCtl_WID                    ( 2)
+  #define DDRCLKCH0_CR_DDRCRCLKCONTROLS_IOLBCtl_MSK                    (0x00000C00)
+  #define DDRCLKCH0_CR_DDRCRCLKCONTROLS_IOLBCtl_MAX                    (0x00000003)
+  #define DDRCLKCH0_CR_DDRCRCLKCONTROLS_IOLBCtl_DEF                    (0x00000000)
+  #define DDRCLKCH0_CR_DDRCRCLKCONTROLS_OdtMode_OFF                    (12)
+  #define DDRCLKCH0_CR_DDRCRCLKCONTROLS_OdtMode_WID                    ( 1)
+  #define DDRCLKCH0_CR_DDRCRCLKCONTROLS_OdtMode_MSK                    (0x00001000)
+  #define DDRCLKCH0_CR_DDRCRCLKCONTROLS_OdtMode_MAX                    (0x00000001)
+  #define DDRCLKCH0_CR_DDRCRCLKCONTROLS_OdtMode_DEF                    (0x00000000)
+  #define DDRCLKCH0_CR_DDRCRCLKCONTROLS_Reserved_OFF                   (13)
+  #define DDRCLKCH0_CR_DDRCRCLKCONTROLS_Reserved_WID                   ( 8)
+  #define DDRCLKCH0_CR_DDRCRCLKCONTROLS_Reserved_MSK                   (0x001FE000)
+  #define DDRCLKCH0_CR_DDRCRCLKCONTROLS_Reserved_MAX                   (0x000000FF)
+  #define DDRCLKCH0_CR_DDRCRCLKCONTROLS_Reserved_DEF                   (0x00000000)
+  #define DDRCLKCH0_CR_DDRCRCLKCONTROLS_RxVref_OFF                     (21)
+  #define DDRCLKCH0_CR_DDRCRCLKCONTROLS_RxVref_WID                     ( 6)
+  #define DDRCLKCH0_CR_DDRCRCLKCONTROLS_RxVref_MSK                     (0x07E00000)
+  #define DDRCLKCH0_CR_DDRCRCLKCONTROLS_RxVref_MAX                     (0x0000003F)
+  #define DDRCLKCH0_CR_DDRCRCLKCONTROLS_RxVref_DEF                     (0x00000000)
+  #define DDRCLKCH0_CR_DDRCRCLKCONTROLS_VccddqHi_OFF                   (27)
+  #define DDRCLKCH0_CR_DDRCRCLKCONTROLS_VccddqHi_WID                   ( 1)
+  #define DDRCLKCH0_CR_DDRCRCLKCONTROLS_VccddqHi_MSK                   (0x08000000)
+  #define DDRCLKCH0_CR_DDRCRCLKCONTROLS_VccddqHi_MAX                   (0x00000001)
+  #define DDRCLKCH0_CR_DDRCRCLKCONTROLS_VccddqHi_DEF                   (0x00000000)
+  #define DDRCLKCH0_CR_DDRCRCLKCONTROLS_DllWeakLock_OFF                (28)
+  #define DDRCLKCH0_CR_DDRCRCLKCONTROLS_DllWeakLock_WID                ( 1)
+  #define DDRCLKCH0_CR_DDRCRCLKCONTROLS_DllWeakLock_MSK                (0x10000000)
+  #define DDRCLKCH0_CR_DDRCRCLKCONTROLS_DllWeakLock_MAX                (0x00000001)
+  #define DDRCLKCH0_CR_DDRCRCLKCONTROLS_DllWeakLock_DEF                (0x00000000)
+  #define DDRCLKCH0_CR_DDRCRCLKCONTROLS_LPDDR_Mode_OFF                 (29)
+  #define DDRCLKCH0_CR_DDRCRCLKCONTROLS_LPDDR_Mode_WID                 ( 1)
+  #define DDRCLKCH0_CR_DDRCRCLKCONTROLS_LPDDR_Mode_MSK                 (0x20000000)
+  #define DDRCLKCH0_CR_DDRCRCLKCONTROLS_LPDDR_Mode_MAX                 (0x00000001)
+  #define DDRCLKCH0_CR_DDRCRCLKCONTROLS_LPDDR_Mode_DEF                 (0x00000000)
+  #define DDRCLKCH0_CR_DDRCRCLKCONTROLS_Spare_OFF                      (30)
+  #define DDRCLKCH0_CR_DDRCRCLKCONTROLS_Spare_WID                      ( 2)
+  #define DDRCLKCH0_CR_DDRCRCLKCONTROLS_Spare_MSK                      (0xC0000000)
+  #define DDRCLKCH0_CR_DDRCRCLKCONTROLS_Spare_MAX                      (0x00000003)
+  #define DDRCLKCH0_CR_DDRCRCLKCONTROLS_Spare_DEF                      (0x00000000)
+
+#define DDRCLKCH0_CR_DLLPITESTANDADC_REG                             (0x00001814)
+  #define DDRCLKCH0_CR_DLLPITESTANDADC_RunTest_OFF                     ( 0)
+  #define DDRCLKCH0_CR_DLLPITESTANDADC_RunTest_WID                     ( 1)
+  #define DDRCLKCH0_CR_DLLPITESTANDADC_RunTest_MSK                     (0x00000001)
+  #define DDRCLKCH0_CR_DLLPITESTANDADC_RunTest_MAX                     (0x00000001)
+  #define DDRCLKCH0_CR_DLLPITESTANDADC_RunTest_DEF                     (0x00000000)
+  #define DDRCLKCH0_CR_DLLPITESTANDADC_Load_OFF                        ( 1)
+  #define DDRCLKCH0_CR_DLLPITESTANDADC_Load_WID                        ( 1)
+  #define DDRCLKCH0_CR_DLLPITESTANDADC_Load_MSK                        (0x00000002)
+  #define DDRCLKCH0_CR_DLLPITESTANDADC_Load_MAX                        (0x00000001)
+  #define DDRCLKCH0_CR_DLLPITESTANDADC_Load_DEF                        (0x00000000)
+  #define DDRCLKCH0_CR_DLLPITESTANDADC_ModeHVM_OFF                     ( 2)
+  #define DDRCLKCH0_CR_DLLPITESTANDADC_ModeHVM_WID                     ( 1)
+  #define DDRCLKCH0_CR_DLLPITESTANDADC_ModeHVM_MSK                     (0x00000004)
+  #define DDRCLKCH0_CR_DLLPITESTANDADC_ModeHVM_MAX                     (0x00000001)
+  #define DDRCLKCH0_CR_DLLPITESTANDADC_ModeHVM_DEF                     (0x00000000)
+  #define DDRCLKCH0_CR_DLLPITESTANDADC_ModeDV_OFF                      ( 3)
+  #define DDRCLKCH0_CR_DLLPITESTANDADC_ModeDV_WID                      ( 1)
+  #define DDRCLKCH0_CR_DLLPITESTANDADC_ModeDV_MSK                      (0x00000008)
+  #define DDRCLKCH0_CR_DLLPITESTANDADC_ModeDV_MAX                      (0x00000001)
+  #define DDRCLKCH0_CR_DLLPITESTANDADC_ModeDV_DEF                      (0x00000000)
+  #define DDRCLKCH0_CR_DLLPITESTANDADC_ModeADC_OFF                     ( 4)
+  #define DDRCLKCH0_CR_DLLPITESTANDADC_ModeADC_WID                     ( 1)
+  #define DDRCLKCH0_CR_DLLPITESTANDADC_ModeADC_MSK                     (0x00000010)
+  #define DDRCLKCH0_CR_DLLPITESTANDADC_ModeADC_MAX                     (0x00000001)
+  #define DDRCLKCH0_CR_DLLPITESTANDADC_ModeADC_DEF                     (0x00000000)
+  #define DDRCLKCH0_CR_DLLPITESTANDADC_LoadCount_OFF                   ( 5)
+  #define DDRCLKCH0_CR_DLLPITESTANDADC_LoadCount_WID                   (10)
+  #define DDRCLKCH0_CR_DLLPITESTANDADC_LoadCount_MSK                   (0x00007FE0)
+  #define DDRCLKCH0_CR_DLLPITESTANDADC_LoadCount_MAX                   (0x000003FF)
+  #define DDRCLKCH0_CR_DLLPITESTANDADC_CountStatus_OFF                 (15)
+  #define DDRCLKCH0_CR_DLLPITESTANDADC_CountStatus_WID                 (10)
+  #define DDRCLKCH0_CR_DLLPITESTANDADC_CountStatus_MSK                 (0x01FF8000)
+  #define DDRCLKCH0_CR_DLLPITESTANDADC_CountStatus_MAX                 (0x000003FF)
+  #define DDRCLKCH0_CR_DLLPITESTANDADC_CountStatus_DEF                 (0x00000000)
+  #define DDRCLKCH0_CR_DLLPITESTANDADC_Spare_OFF                       (25)
+  #define DDRCLKCH0_CR_DLLPITESTANDADC_Spare_WID                       ( 7)
+  #define DDRCLKCH0_CR_DLLPITESTANDADC_Spare_MSK                       (0xFE000000)
+  #define DDRCLKCH0_CR_DLLPITESTANDADC_Spare_MAX                       (0x0000007F)
+
+#define DDRCLKCH0_CR_DDRCBSTATUS_REG                                 (0x00001818)
+  #define DDRCLKCH0_CR_DDRCBSTATUS_DllCB_OFF                           ( 0)
+  #define DDRCLKCH0_CR_DDRCBSTATUS_DllCB_WID                           ( 2)
+  #define DDRCLKCH0_CR_DDRCBSTATUS_DllCB_MSK                           (0x00000003)
+  #define DDRCLKCH0_CR_DDRCBSTATUS_DllCB_MAX                           (0x00000003)
+  #define DDRCLKCH0_CR_DDRCBSTATUS_DllCB_DEF                           (0x00000000)
+  #define DDRCLKCH0_CR_DDRCBSTATUS_Spare_OFF                           ( 2)
+  #define DDRCLKCH0_CR_DDRCBSTATUS_Spare_WID                           (30)
+  #define DDRCLKCH0_CR_DDRCBSTATUS_Spare_MSK                           (0xFFFFFFFC)
+  #define DDRCLKCH0_CR_DDRCBSTATUS_Spare_MAX                           (0x3FFFFFFF)
+  #define DDRCLKCH0_CR_DDRCBSTATUS_Spare_DEF                           (0x00000000)
+
+#define DDRCLKCH1_CR_DDRCRCLKRANKSUSED_REG                           (0x00001900)
+  #define DDRCLKCH1_CR_DDRCRCLKRANKSUSED_RankEn_OFF                    ( 0)
+  #define DDRCLKCH1_CR_DDRCRCLKRANKSUSED_RankEn_WID                    ( 4)
+  #define DDRCLKCH1_CR_DDRCRCLKRANKSUSED_RankEn_MSK                    (0x0000000F)
+  #define DDRCLKCH1_CR_DDRCRCLKRANKSUSED_RankEn_MAX                    (0x0000000F)
+  #define DDRCLKCH1_CR_DDRCRCLKRANKSUSED_RankEn_DEF                    (0x0000000F)
+  #define DDRCLKCH1_CR_DDRCRCLKRANKSUSED_Spare_OFF                     ( 4)
+  #define DDRCLKCH1_CR_DDRCRCLKRANKSUSED_Spare_WID                     (28)
+  #define DDRCLKCH1_CR_DDRCRCLKRANKSUSED_Spare_MSK                     (0xFFFFFFF0)
+  #define DDRCLKCH1_CR_DDRCRCLKRANKSUSED_Spare_MAX                     (0x0FFFFFFF)
+  #define DDRCLKCH1_CR_DDRCRCLKRANKSUSED_Spare_DEF                     (0x00000000)
+
+#define DDRCLKCH1_CR_DDRCRCLKCOMP_REG                                (0x00001904)
+  #define DDRCLKCH1_CR_DDRCRCLKCOMP_Scomp_OFF                          ( 0)
+  #define DDRCLKCH1_CR_DDRCRCLKCOMP_Scomp_WID                          ( 5)
+  #define DDRCLKCH1_CR_DDRCRCLKCOMP_Scomp_MSK                          (0x0000001F)
+  #define DDRCLKCH1_CR_DDRCRCLKCOMP_Scomp_MAX                          (0x0000001F)
+  #define DDRCLKCH1_CR_DDRCRCLKCOMP_Scomp_DEF                          (0x00000000)
+  #define DDRCLKCH1_CR_DDRCRCLKCOMP_TcoComp_OFF                        ( 5)
+  #define DDRCLKCH1_CR_DDRCRCLKCOMP_TcoComp_WID                        ( 6)
+  #define DDRCLKCH1_CR_DDRCRCLKCOMP_TcoComp_MSK                        (0x000007E0)
+  #define DDRCLKCH1_CR_DDRCRCLKCOMP_TcoComp_MAX                        (0x0000003F)
+  #define DDRCLKCH1_CR_DDRCRCLKCOMP_TcoComp_DEF                        (0x00000000)
+  #define DDRCLKCH1_CR_DDRCRCLKCOMP_RcompDrvUp_OFF                     (11)
+  #define DDRCLKCH1_CR_DDRCRCLKCOMP_RcompDrvUp_WID                     ( 6)
+  #define DDRCLKCH1_CR_DDRCRCLKCOMP_RcompDrvUp_MSK                     (0x0001F800)
+  #define DDRCLKCH1_CR_DDRCRCLKCOMP_RcompDrvUp_MAX                     (0x0000003F)
+  #define DDRCLKCH1_CR_DDRCRCLKCOMP_RcompDrvUp_DEF                     (0x00000000)
+  #define DDRCLKCH1_CR_DDRCRCLKCOMP_RcompDrvDown_OFF                   (17)
+  #define DDRCLKCH1_CR_DDRCRCLKCOMP_RcompDrvDown_WID                   ( 6)
+  #define DDRCLKCH1_CR_DDRCRCLKCOMP_RcompDrvDown_MSK                   (0x007E0000)
+  #define DDRCLKCH1_CR_DDRCRCLKCOMP_RcompDrvDown_MAX                   (0x0000003F)
+  #define DDRCLKCH1_CR_DDRCRCLKCOMP_RcompDrvDown_DEF                   (0x00000000)
+  #define DDRCLKCH1_CR_DDRCRCLKCOMP_LsComp_OFF                         (23)
+  #define DDRCLKCH1_CR_DDRCRCLKCOMP_LsComp_WID                         ( 3)
+  #define DDRCLKCH1_CR_DDRCRCLKCOMP_LsComp_MSK                         (0x03800000)
+  #define DDRCLKCH1_CR_DDRCRCLKCOMP_LsComp_MAX                         (0x00000007)
+  #define DDRCLKCH1_CR_DDRCRCLKCOMP_LsComp_DEF                         (0x00000004)
+  #define DDRCLKCH1_CR_DDRCRCLKCOMP_Spare_OFF                          (26)
+  #define DDRCLKCH1_CR_DDRCRCLKCOMP_Spare_WID                          ( 6)
+  #define DDRCLKCH1_CR_DDRCRCLKCOMP_Spare_MSK                          (0xFC000000)
+  #define DDRCLKCH1_CR_DDRCRCLKCOMP_Spare_MAX                          (0x0000003F)
+  #define DDRCLKCH1_CR_DDRCRCLKCOMP_Spare_DEF                          (0x00000000)
+
+#define DDRCLKCH1_CR_DDRCRCLKCOMPOFFSET_REG                          (0x00001908)
+  #define DDRCLKCH1_CR_DDRCRCLKCOMPOFFSET_ScompOffset_OFF              ( 0)
+  #define DDRCLKCH1_CR_DDRCRCLKCOMPOFFSET_ScompOffset_WID              ( 4)
+  #define DDRCLKCH1_CR_DDRCRCLKCOMPOFFSET_ScompOffset_MSK              (0x0000000F)
+  #define DDRCLKCH1_CR_DDRCRCLKCOMPOFFSET_ScompOffset_MAX              (0x0000000F)
+  #define DDRCLKCH1_CR_DDRCRCLKCOMPOFFSET_ScompOffset_DEF              (0x00000000)
+  #define DDRCLKCH1_CR_DDRCRCLKCOMPOFFSET_TcoCompOffset_OFF            ( 4)
+  #define DDRCLKCH1_CR_DDRCRCLKCOMPOFFSET_TcoCompOffset_WID            ( 4)
+  #define DDRCLKCH1_CR_DDRCRCLKCOMPOFFSET_TcoCompOffset_MSK            (0x000000F0)
+  #define DDRCLKCH1_CR_DDRCRCLKCOMPOFFSET_TcoCompOffset_MAX            (0x0000000F)
+  #define DDRCLKCH1_CR_DDRCRCLKCOMPOFFSET_TcoCompOffset_DEF            (0x00000000)
+  #define DDRCLKCH1_CR_DDRCRCLKCOMPOFFSET_RcompDrvUpOffset_OFF         ( 8)
+  #define DDRCLKCH1_CR_DDRCRCLKCOMPOFFSET_RcompDrvUpOffset_WID         ( 4)
+  #define DDRCLKCH1_CR_DDRCRCLKCOMPOFFSET_RcompDrvUpOffset_MSK         (0x00000F00)
+  #define DDRCLKCH1_CR_DDRCRCLKCOMPOFFSET_RcompDrvUpOffset_MAX         (0x0000000F)
+  #define DDRCLKCH1_CR_DDRCRCLKCOMPOFFSET_RcompDrvUpOffset_DEF         (0x00000000)
+  #define DDRCLKCH1_CR_DDRCRCLKCOMPOFFSET_RcompDrvDownOffset_OFF       (12)
+  #define DDRCLKCH1_CR_DDRCRCLKCOMPOFFSET_RcompDrvDownOffset_WID       ( 4)
+  #define DDRCLKCH1_CR_DDRCRCLKCOMPOFFSET_RcompDrvDownOffset_MSK       (0x0000F000)
+  #define DDRCLKCH1_CR_DDRCRCLKCOMPOFFSET_RcompDrvDownOffset_MAX       (0x0000000F)
+  #define DDRCLKCH1_CR_DDRCRCLKCOMPOFFSET_RcompDrvDownOffset_DEF       (0x00000000)
+  #define DDRCLKCH1_CR_DDRCRCLKCOMPOFFSET_Spare_OFF                    (16)
+  #define DDRCLKCH1_CR_DDRCRCLKCOMPOFFSET_Spare_WID                    (16)
+  #define DDRCLKCH1_CR_DDRCRCLKCOMPOFFSET_Spare_MSK                    (0xFFFF0000)
+  #define DDRCLKCH1_CR_DDRCRCLKCOMPOFFSET_Spare_MAX                    (0x0000FFFF)
+  #define DDRCLKCH1_CR_DDRCRCLKCOMPOFFSET_Spare_DEF                    (0x00000000)
+
+#define DDRCLKCH1_CR_DDRCRCLKPICODE_REG                              (0x0000190C)
+  #define DDRCLKCH1_CR_DDRCRCLKPICODE_PiSettingRank0_OFF               ( 0)
+  #define DDRCLKCH1_CR_DDRCRCLKPICODE_PiSettingRank0_WID               ( 7)
+  #define DDRCLKCH1_CR_DDRCRCLKPICODE_PiSettingRank0_MSK               (0x0000007F)
+  #define DDRCLKCH1_CR_DDRCRCLKPICODE_PiSettingRank0_MAX               (0x0000007F)
+  #define DDRCLKCH1_CR_DDRCRCLKPICODE_PiSettingRank0_DEF               (0x00000000)
+  #define DDRCLKCH1_CR_DDRCRCLKPICODE_PiSettingRank1_OFF               ( 7)
+  #define DDRCLKCH1_CR_DDRCRCLKPICODE_PiSettingRank1_WID               ( 7)
+  #define DDRCLKCH1_CR_DDRCRCLKPICODE_PiSettingRank1_MSK               (0x00003F80)
+  #define DDRCLKCH1_CR_DDRCRCLKPICODE_PiSettingRank1_MAX               (0x0000007F)
+  #define DDRCLKCH1_CR_DDRCRCLKPICODE_PiSettingRank1_DEF               (0x00000000)
+  #define DDRCLKCH1_CR_DDRCRCLKPICODE_PiSettingRank2_OFF               (14)
+  #define DDRCLKCH1_CR_DDRCRCLKPICODE_PiSettingRank2_WID               ( 7)
+  #define DDRCLKCH1_CR_DDRCRCLKPICODE_PiSettingRank2_MSK               (0x001FC000)
+  #define DDRCLKCH1_CR_DDRCRCLKPICODE_PiSettingRank2_MAX               (0x0000007F)
+  #define DDRCLKCH1_CR_DDRCRCLKPICODE_PiSettingRank2_DEF               (0x00000000)
+  #define DDRCLKCH1_CR_DDRCRCLKPICODE_PiSettingRank3_OFF               (21)
+  #define DDRCLKCH1_CR_DDRCRCLKPICODE_PiSettingRank3_WID               ( 7)
+  #define DDRCLKCH1_CR_DDRCRCLKPICODE_PiSettingRank3_MSK               (0x0FE00000)
+  #define DDRCLKCH1_CR_DDRCRCLKPICODE_PiSettingRank3_MAX               (0x0000007F)
+  #define DDRCLKCH1_CR_DDRCRCLKPICODE_PiSettingRank3_DEF               (0x00000000)
+  #define DDRCLKCH1_CR_DDRCRCLKPICODE_Spare_OFF                        (28)
+  #define DDRCLKCH1_CR_DDRCRCLKPICODE_Spare_WID                        ( 4)
+  #define DDRCLKCH1_CR_DDRCRCLKPICODE_Spare_MSK                        (0xF0000000)
+  #define DDRCLKCH1_CR_DDRCRCLKPICODE_Spare_MAX                        (0x0000000F)
+  #define DDRCLKCH1_CR_DDRCRCLKPICODE_Spare_DEF                        (0x00000000)
+
+#define DDRCLKCH1_CR_DDRCRCLKCONTROLS_REG                            (0x00001910)
+  #define DDRCLKCH1_CR_DDRCRCLKCONTROLS_RefPi_OFF                      ( 0)
+  #define DDRCLKCH1_CR_DDRCRCLKCONTROLS_RefPi_WID                      ( 4)
+  #define DDRCLKCH1_CR_DDRCRCLKCONTROLS_RefPi_MSK                      (0x0000000F)
+  #define DDRCLKCH1_CR_DDRCRCLKCONTROLS_RefPi_MAX                      (0x0000000F)
+  #define DDRCLKCH1_CR_DDRCRCLKCONTROLS_RefPi_DEF                      (0x00000000)
+  #define DDRCLKCH1_CR_DDRCRCLKCONTROLS_DllMask_OFF                    ( 4)
+  #define DDRCLKCH1_CR_DDRCRCLKCONTROLS_DllMask_WID                    ( 2)
+  #define DDRCLKCH1_CR_DDRCRCLKCONTROLS_DllMask_MSK                    (0x00000030)
+  #define DDRCLKCH1_CR_DDRCRCLKCONTROLS_DllMask_MAX                    (0x00000003)
+  #define DDRCLKCH1_CR_DDRCRCLKCONTROLS_DllMask_DEF                    (0x00000000)
+  #define DDRCLKCH1_CR_DDRCRCLKCONTROLS_DllRsvd1_OFF                   ( 6)
+  #define DDRCLKCH1_CR_DDRCRCLKCONTROLS_DllRsvd1_WID                   ( 1)
+  #define DDRCLKCH1_CR_DDRCRCLKCONTROLS_DllRsvd1_MSK                   (0x00000040)
+  #define DDRCLKCH1_CR_DDRCRCLKCONTROLS_DllRsvd1_MAX                   (0x00000001)
+  #define DDRCLKCH1_CR_DDRCRCLKCONTROLS_DllRsvd1_DEF                   (0x00000000)
+  #define DDRCLKCH1_CR_DDRCRCLKCONTROLS_TxOn_OFF                       ( 7)
+  #define DDRCLKCH1_CR_DDRCRCLKCONTROLS_TxOn_WID                       ( 1)
+  #define DDRCLKCH1_CR_DDRCRCLKCONTROLS_TxOn_MSK                       (0x00000080)
+  #define DDRCLKCH1_CR_DDRCRCLKCONTROLS_TxOn_MAX                       (0x00000001)
+  #define DDRCLKCH1_CR_DDRCRCLKCONTROLS_TxOn_DEF                       (0x00000000)
+  #define DDRCLKCH1_CR_DDRCRCLKCONTROLS_IntClkOn_OFF                   ( 8)
+  #define DDRCLKCH1_CR_DDRCRCLKCONTROLS_IntClkOn_WID                   ( 1)
+  #define DDRCLKCH1_CR_DDRCRCLKCONTROLS_IntClkOn_MSK                   (0x00000100)
+  #define DDRCLKCH1_CR_DDRCRCLKCONTROLS_IntClkOn_MAX                   (0x00000001)
+  #define DDRCLKCH1_CR_DDRCRCLKCONTROLS_IntClkOn_DEF                   (0x00000000)
+  #define DDRCLKCH1_CR_DDRCRCLKCONTROLS_RepClkOn_OFF                   ( 9)
+  #define DDRCLKCH1_CR_DDRCRCLKCONTROLS_RepClkOn_WID                   ( 1)
+  #define DDRCLKCH1_CR_DDRCRCLKCONTROLS_RepClkOn_MSK                   (0x00000200)
+  #define DDRCLKCH1_CR_DDRCRCLKCONTROLS_RepClkOn_MAX                   (0x00000001)
+  #define DDRCLKCH1_CR_DDRCRCLKCONTROLS_RepClkOn_DEF                   (0x00000000)
+  #define DDRCLKCH1_CR_DDRCRCLKCONTROLS_IOLBCtl_OFF                    (10)
+  #define DDRCLKCH1_CR_DDRCRCLKCONTROLS_IOLBCtl_WID                    ( 2)
+  #define DDRCLKCH1_CR_DDRCRCLKCONTROLS_IOLBCtl_MSK                    (0x00000C00)
+  #define DDRCLKCH1_CR_DDRCRCLKCONTROLS_IOLBCtl_MAX                    (0x00000003)
+  #define DDRCLKCH1_CR_DDRCRCLKCONTROLS_IOLBCtl_DEF                    (0x00000000)
+  #define DDRCLKCH1_CR_DDRCRCLKCONTROLS_OdtMode_OFF                    (12)
+  #define DDRCLKCH1_CR_DDRCRCLKCONTROLS_OdtMode_WID                    ( 1)
+  #define DDRCLKCH1_CR_DDRCRCLKCONTROLS_OdtMode_MSK                    (0x00001000)
+  #define DDRCLKCH1_CR_DDRCRCLKCONTROLS_OdtMode_MAX                    (0x00000001)
+  #define DDRCLKCH1_CR_DDRCRCLKCONTROLS_OdtMode_DEF                    (0x00000000)
+  #define DDRCLKCH1_CR_DDRCRCLKCONTROLS_Reserved_OFF                   (13)
+  #define DDRCLKCH1_CR_DDRCRCLKCONTROLS_Reserved_WID                   ( 8)
+  #define DDRCLKCH1_CR_DDRCRCLKCONTROLS_Reserved_MSK                   (0x001FE000)
+  #define DDRCLKCH1_CR_DDRCRCLKCONTROLS_Reserved_MAX                   (0x000000FF)
+  #define DDRCLKCH1_CR_DDRCRCLKCONTROLS_Reserved_DEF                   (0x00000000)
+  #define DDRCLKCH1_CR_DDRCRCLKCONTROLS_RxVref_OFF                     (21)
+  #define DDRCLKCH1_CR_DDRCRCLKCONTROLS_RxVref_WID                     ( 6)
+  #define DDRCLKCH1_CR_DDRCRCLKCONTROLS_RxVref_MSK                     (0x07E00000)
+  #define DDRCLKCH1_CR_DDRCRCLKCONTROLS_RxVref_MAX                     (0x0000003F)
+  #define DDRCLKCH1_CR_DDRCRCLKCONTROLS_RxVref_DEF                     (0x00000000)
+  #define DDRCLKCH1_CR_DDRCRCLKCONTROLS_VccddqHi_OFF                   (27)
+  #define DDRCLKCH1_CR_DDRCRCLKCONTROLS_VccddqHi_WID                   ( 1)
+  #define DDRCLKCH1_CR_DDRCRCLKCONTROLS_VccddqHi_MSK                   (0x08000000)
+  #define DDRCLKCH1_CR_DDRCRCLKCONTROLS_VccddqHi_MAX                   (0x00000001)
+  #define DDRCLKCH1_CR_DDRCRCLKCONTROLS_VccddqHi_DEF                   (0x00000000)
+  #define DDRCLKCH1_CR_DDRCRCLKCONTROLS_DllWeakLock_OFF                (28)
+  #define DDRCLKCH1_CR_DDRCRCLKCONTROLS_DllWeakLock_WID                ( 1)
+  #define DDRCLKCH1_CR_DDRCRCLKCONTROLS_DllWeakLock_MSK                (0x10000000)
+  #define DDRCLKCH1_CR_DDRCRCLKCONTROLS_DllWeakLock_MAX                (0x00000001)
+  #define DDRCLKCH1_CR_DDRCRCLKCONTROLS_DllWeakLock_DEF                (0x00000000)
+  #define DDRCLKCH1_CR_DDRCRCLKCONTROLS_LPDDR_Mode_OFF                 (29)
+  #define DDRCLKCH1_CR_DDRCRCLKCONTROLS_LPDDR_Mode_WID                 ( 1)
+  #define DDRCLKCH1_CR_DDRCRCLKCONTROLS_LPDDR_Mode_MSK                 (0x20000000)
+  #define DDRCLKCH1_CR_DDRCRCLKCONTROLS_LPDDR_Mode_MAX                 (0x00000001)
+  #define DDRCLKCH1_CR_DDRCRCLKCONTROLS_LPDDR_Mode_DEF                 (0x00000000)
+  #define DDRCLKCH1_CR_DDRCRCLKCONTROLS_Spare_OFF                      (30)
+  #define DDRCLKCH1_CR_DDRCRCLKCONTROLS_Spare_WID                      ( 2)
+  #define DDRCLKCH1_CR_DDRCRCLKCONTROLS_Spare_MSK                      (0xC0000000)
+  #define DDRCLKCH1_CR_DDRCRCLKCONTROLS_Spare_MAX                      (0x00000003)
+  #define DDRCLKCH1_CR_DDRCRCLKCONTROLS_Spare_DEF                      (0x00000000)
+
+#define DDRCLKCH1_CR_DLLPITESTANDADC_REG                             (0x00001914)
+  #define DDRCLKCH1_CR_DLLPITESTANDADC_RunTest_OFF                     ( 0)
+  #define DDRCLKCH1_CR_DLLPITESTANDADC_RunTest_WID                     ( 1)
+  #define DDRCLKCH1_CR_DLLPITESTANDADC_RunTest_MSK                     (0x00000001)
+  #define DDRCLKCH1_CR_DLLPITESTANDADC_RunTest_MAX                     (0x00000001)
+  #define DDRCLKCH1_CR_DLLPITESTANDADC_RunTest_DEF                     (0x00000000)
+  #define DDRCLKCH1_CR_DLLPITESTANDADC_Load_OFF                        ( 1)
+  #define DDRCLKCH1_CR_DLLPITESTANDADC_Load_WID                        ( 1)
+  #define DDRCLKCH1_CR_DLLPITESTANDADC_Load_MSK                        (0x00000002)
+  #define DDRCLKCH1_CR_DLLPITESTANDADC_Load_MAX                        (0x00000001)
+  #define DDRCLKCH1_CR_DLLPITESTANDADC_Load_DEF                        (0x00000000)
+  #define DDRCLKCH1_CR_DLLPITESTANDADC_ModeHVM_OFF                     ( 2)
+  #define DDRCLKCH1_CR_DLLPITESTANDADC_ModeHVM_WID                     ( 1)
+  #define DDRCLKCH1_CR_DLLPITESTANDADC_ModeHVM_MSK                     (0x00000004)
+  #define DDRCLKCH1_CR_DLLPITESTANDADC_ModeHVM_MAX                     (0x00000001)
+  #define DDRCLKCH1_CR_DLLPITESTANDADC_ModeHVM_DEF                     (0x00000000)
+  #define DDRCLKCH1_CR_DLLPITESTANDADC_ModeDV_OFF                      ( 3)
+  #define DDRCLKCH1_CR_DLLPITESTANDADC_ModeDV_WID                      ( 1)
+  #define DDRCLKCH1_CR_DLLPITESTANDADC_ModeDV_MSK                      (0x00000008)
+  #define DDRCLKCH1_CR_DLLPITESTANDADC_ModeDV_MAX                      (0x00000001)
+  #define DDRCLKCH1_CR_DLLPITESTANDADC_ModeDV_DEF                      (0x00000000)
+  #define DDRCLKCH1_CR_DLLPITESTANDADC_ModeADC_OFF                     ( 4)
+  #define DDRCLKCH1_CR_DLLPITESTANDADC_ModeADC_WID                     ( 1)
+  #define DDRCLKCH1_CR_DLLPITESTANDADC_ModeADC_MSK                     (0x00000010)
+  #define DDRCLKCH1_CR_DLLPITESTANDADC_ModeADC_MAX                     (0x00000001)
+  #define DDRCLKCH1_CR_DLLPITESTANDADC_ModeADC_DEF                     (0x00000000)
+  #define DDRCLKCH1_CR_DLLPITESTANDADC_LoadCount_OFF                   ( 5)
+  #define DDRCLKCH1_CR_DLLPITESTANDADC_LoadCount_WID                   (10)
+  #define DDRCLKCH1_CR_DLLPITESTANDADC_LoadCount_MSK                   (0x00007FE0)
+  #define DDRCLKCH1_CR_DLLPITESTANDADC_LoadCount_MAX                   (0x000003FF)
+  #define DDRCLKCH1_CR_DLLPITESTANDADC_CountStatus_OFF                 (15)
+  #define DDRCLKCH1_CR_DLLPITESTANDADC_CountStatus_WID                 (10)
+  #define DDRCLKCH1_CR_DLLPITESTANDADC_CountStatus_MSK                 (0x01FF8000)
+  #define DDRCLKCH1_CR_DLLPITESTANDADC_CountStatus_MAX                 (0x000003FF)
+  #define DDRCLKCH1_CR_DLLPITESTANDADC_CountStatus_DEF                 (0x00000000)
+  #define DDRCLKCH1_CR_DLLPITESTANDADC_Spare_OFF                       (25)
+  #define DDRCLKCH1_CR_DLLPITESTANDADC_Spare_WID                       ( 7)
+  #define DDRCLKCH1_CR_DLLPITESTANDADC_Spare_MSK                       (0xFE000000)
+  #define DDRCLKCH1_CR_DLLPITESTANDADC_Spare_MAX                       (0x0000007F)
+
+#define DDRCLKCH1_CR_DDRCBSTATUS_REG                                 (0x00001918)
+  #define DDRCLKCH1_CR_DDRCBSTATUS_DllCB_OFF                           ( 0)
+  #define DDRCLKCH1_CR_DDRCBSTATUS_DllCB_WID                           ( 2)
+  #define DDRCLKCH1_CR_DDRCBSTATUS_DllCB_MSK                           (0x00000003)
+  #define DDRCLKCH1_CR_DDRCBSTATUS_DllCB_MAX                           (0x00000003)
+  #define DDRCLKCH1_CR_DDRCBSTATUS_DllCB_DEF                           (0x00000000)
+  #define DDRCLKCH1_CR_DDRCBSTATUS_Spare_OFF                           ( 2)
+  #define DDRCLKCH1_CR_DDRCBSTATUS_Spare_WID                           (30)
+  #define DDRCLKCH1_CR_DDRCBSTATUS_Spare_MSK                           (0xFFFFFFFC)
+  #define DDRCLKCH1_CR_DDRCBSTATUS_Spare_MAX                           (0x3FFFFFFF)
+  #define DDRCLKCH1_CR_DDRCBSTATUS_Spare_DEF                           (0x00000000)
+
+#pragma pack(pop)
+#endif  // __McIoClk_h__
diff --git a/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcRegisters/McIoCmd.h b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcRegisters/McIoCmd.h
new file mode 100644
index 0000000..79c6146
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcRegisters/McIoCmd.h
@@ -0,0 +1,2002 @@
+/** @file
+  This file was automatically generated. Modify at your own risk.
+
+@copyright
+  Copyright (c) 2010 - 2012 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement
+**/
+#ifndef __McIoCmd_h__
+#define __McIoCmd_h__
+
+#pragma pack(push, 1)
+#include "MrcTypes.h"
+
+typedef union {
+  struct {
+    U32 Scomp                                   :  6;  // Bits 5:0
+    U32 TcoComp                                 :  6;  // Bits 11:6
+    U32 RcompDrvUp                              :  6;  // Bits 17:12
+    U32 RcompDrvDown                            :  6;  // Bits 23:18
+    U32 LsComp                                  :  3;  // Bits 26:24
+    U32 Spare                                   :  5;  // Bits 31:27
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRCMD_CR_DDRCRCMDCOMP_STRUCT;
+
+typedef union {
+  struct {
+    U32 ScompOffset                             :  5;  // Bits 4:0
+    U32 TcoCompOffset                           :  4;  // Bits 8:5
+    U32 RcompDrvUpOffset                        :  4;  // Bits 12:9
+    U32 RcompDrvDownOffset                      :  4;  // Bits 16:13
+    U32 Spare                                   :  15;  // Bits 31:17
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRCMD_CR_DDRCRCMDCOMPOFFSET_STRUCT;
+
+typedef union {
+  struct {
+    U32 CmdPi0Code                              :  7;  // Bits 6:0
+    U32 CmdPi1Code                              :  7;  // Bits 13:7
+    U32 Spare                                   :  18;  // Bits 31:14
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRCMD_CR_DDRCRCMDPICODING_STRUCT;
+
+typedef union {
+  struct {
+    U32 RefPi                                   :  4;  // Bits 3:0
+    U32 DllMask                                 :  2;  // Bits 5:4
+    U32 DllRsvd1                                :  1;  // Bits 6:6
+    U32 TxOn                                    :  1;  // Bits 7:7
+    U32 IntClkOn                                :  1;  // Bits 8:8
+    U32 RepClkOn                                :  1;  // Bits 9:9
+    U32 IOLBCtl                                 :  2;  // Bits 11:10
+    U32 OdtMode                                 :  1;  // Bits 12:12
+    U32 CmdTxEq                                 :  2;  // Bits 14:13
+    U32 EarlyWeakDrive                          :  2;  // Bits 16:15
+    U32 Reserved                                :  4;  // Bits 20:17
+    U32 RxVref                                  :  6;  // Bits 26:21
+    U32 VccddqHi                                :  1;  // Bits 27:27
+    U32 DllWeakLock                             :  1;  // Bits 28:28
+    U32 LPDDR_Mode                              :  1;  // Bits 29:29
+    U32 LPDdrCAA_Dis                            :  1;  // Bits 30:30
+    U32 LPDdrCAB_Dis                            :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRCMD_CR_DDRCRCMDCONTROLS_STRUCT;
+
+typedef union {
+  struct {
+    U32 RunTest                                 :  1;  // Bits 0:0
+    U32 Load                                    :  1;  // Bits 1:1
+    U32 ModeHVM                                 :  1;  // Bits 2:2
+    U32 ModeDV                                  :  1;  // Bits 3:3
+    U32 ModeADC                                 :  1;  // Bits 4:4
+    U32 LoadCount                               :  10;  // Bits 14:5
+    U32 CountStatus                             :  10;  // Bits 24:15
+    U32 Spare                                   :  7;  // Bits 31:25
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRCMD_CR_DLLPITESTANDADC_STRUCT;
+
+typedef union {
+  struct {
+    U32 Scomp                                   :  6;  // Bits 5:0
+    U32 TcoComp                                 :  6;  // Bits 11:6
+    U32 RcompDrvUp                              :  6;  // Bits 17:12
+    U32 RcompDrvDown                            :  6;  // Bits 23:18
+    U32 LsComp                                  :  3;  // Bits 26:24
+    U32 Spare                                   :  5;  // Bits 31:27
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRCMDNCH0_CR_DDRCRCMDCOMP_STRUCT;
+
+typedef union {
+  struct {
+    U32 ScompOffset                             :  5;  // Bits 4:0
+    U32 TcoCompOffset                           :  4;  // Bits 8:5
+    U32 RcompDrvUpOffset                        :  4;  // Bits 12:9
+    U32 RcompDrvDownOffset                      :  4;  // Bits 16:13
+    U32 Spare                                   :  15;  // Bits 31:17
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRCMDNCH0_CR_DDRCRCMDCOMPOFFSET_STRUCT;
+
+typedef union {
+  struct {
+    U32 CmdPi0Code                              :  7;  // Bits 6:0
+    U32 CmdPi1Code                              :  7;  // Bits 13:7
+    U32 Spare                                   :  18;  // Bits 31:14
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRCMDNCH0_CR_DDRCRCMDPICODING_STRUCT;
+
+typedef union {
+  struct {
+    U32 RefPi                                   :  4;  // Bits 3:0
+    U32 DllMask                                 :  2;  // Bits 5:4
+    U32 DllRsvd1                                :  1;  // Bits 6:6
+    U32 TxOn                                    :  1;  // Bits 7:7
+    U32 IntClkOn                                :  1;  // Bits 8:8
+    U32 RepClkOn                                :  1;  // Bits 9:9
+    U32 IOLBCtl                                 :  2;  // Bits 11:10
+    U32 OdtMode                                 :  1;  // Bits 12:12
+    U32 CmdTxEq                                 :  2;  // Bits 14:13
+    U32 EarlyWeakDrive                          :  2;  // Bits 16:15
+    U32 Reserved                                :  4;  // Bits 20:17
+    U32 RxVref                                  :  6;  // Bits 26:21
+    U32 VccddqHi                                :  1;  // Bits 27:27
+    U32 DllWeakLock                             :  1;  // Bits 28:28
+    U32 LPDDR_Mode                              :  1;  // Bits 29:29
+    U32 LPDdrCAA_Dis                            :  1;  // Bits 30:30
+    U32 LPDdrCAB_Dis                            :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRCMDNCH0_CR_DDRCRCMDCONTROLS_STRUCT;
+
+typedef union {
+  struct {
+    U32 RunTest                                 :  1;  // Bits 0:0
+    U32 Load                                    :  1;  // Bits 1:1
+    U32 ModeHVM                                 :  1;  // Bits 2:2
+    U32 ModeDV                                  :  1;  // Bits 3:3
+    U32 ModeADC                                 :  1;  // Bits 4:4
+    U32 LoadCount                               :  10;  // Bits 14:5
+    U32 CountStatus                             :  10;  // Bits 24:15
+    U32 Spare                                   :  7;  // Bits 31:25
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRCMDNCH0_CR_DLLPITESTANDADC_STRUCT;
+
+typedef union {
+  struct {
+    U32 Scomp                                   :  6;  // Bits 5:0
+    U32 TcoComp                                 :  6;  // Bits 11:6
+    U32 RcompDrvUp                              :  6;  // Bits 17:12
+    U32 RcompDrvDown                            :  6;  // Bits 23:18
+    U32 LsComp                                  :  3;  // Bits 26:24
+    U32 Spare                                   :  5;  // Bits 31:27
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRCMDNCH1_CR_DDRCRCMDCOMP_STRUCT;
+
+typedef union {
+  struct {
+    U32 ScompOffset                             :  5;  // Bits 4:0
+    U32 TcoCompOffset                           :  4;  // Bits 8:5
+    U32 RcompDrvUpOffset                        :  4;  // Bits 12:9
+    U32 RcompDrvDownOffset                      :  4;  // Bits 16:13
+    U32 Spare                                   :  15;  // Bits 31:17
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRCMDNCH1_CR_DDRCRCMDCOMPOFFSET_STRUCT;
+
+typedef union {
+  struct {
+    U32 CmdPi0Code                              :  7;  // Bits 6:0
+    U32 CmdPi1Code                              :  7;  // Bits 13:7
+    U32 Spare                                   :  18;  // Bits 31:14
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRCMDNCH1_CR_DDRCRCMDPICODING_STRUCT;
+
+typedef union {
+  struct {
+    U32 RefPi                                   :  4;  // Bits 3:0
+    U32 DllMask                                 :  2;  // Bits 5:4
+    U32 DllRsvd1                                :  1;  // Bits 6:6
+    U32 TxOn                                    :  1;  // Bits 7:7
+    U32 IntClkOn                                :  1;  // Bits 8:8
+    U32 RepClkOn                                :  1;  // Bits 9:9
+    U32 IOLBCtl                                 :  2;  // Bits 11:10
+    U32 OdtMode                                 :  1;  // Bits 12:12
+    U32 CmdTxEq                                 :  2;  // Bits 14:13
+    U32 EarlyWeakDrive                          :  2;  // Bits 16:15
+    U32 Reserved                                :  4;  // Bits 20:17
+    U32 RxVref                                  :  6;  // Bits 26:21
+    U32 VccddqHi                                :  1;  // Bits 27:27
+    U32 DllWeakLock                             :  1;  // Bits 28:28
+    U32 LPDDR_Mode                              :  1;  // Bits 29:29
+    U32 LPDdrCAA_Dis                            :  1;  // Bits 30:30
+    U32 LPDdrCAB_Dis                            :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRCMDNCH1_CR_DDRCRCMDCONTROLS_STRUCT;
+
+typedef union {
+  struct {
+    U32 RunTest                                 :  1;  // Bits 0:0
+    U32 Load                                    :  1;  // Bits 1:1
+    U32 ModeHVM                                 :  1;  // Bits 2:2
+    U32 ModeDV                                  :  1;  // Bits 3:3
+    U32 ModeADC                                 :  1;  // Bits 4:4
+    U32 LoadCount                               :  10;  // Bits 14:5
+    U32 CountStatus                             :  10;  // Bits 24:15
+    U32 Spare                                   :  7;  // Bits 31:25
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRCMDNCH1_CR_DLLPITESTANDADC_STRUCT;
+
+typedef union {
+  struct {
+    U32 Scomp                                   :  6;  // Bits 5:0
+    U32 TcoComp                                 :  6;  // Bits 11:6
+    U32 RcompDrvUp                              :  6;  // Bits 17:12
+    U32 RcompDrvDown                            :  6;  // Bits 23:18
+    U32 LsComp                                  :  3;  // Bits 26:24
+    U32 Spare                                   :  5;  // Bits 31:27
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRCMDSCH0_CR_DDRCRCMDCOMP_STRUCT;
+
+typedef union {
+  struct {
+    U32 ScompOffset                             :  5;  // Bits 4:0
+    U32 TcoCompOffset                           :  4;  // Bits 8:5
+    U32 RcompDrvUpOffset                        :  4;  // Bits 12:9
+    U32 RcompDrvDownOffset                      :  4;  // Bits 16:13
+    U32 Spare                                   :  15;  // Bits 31:17
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRCMDSCH0_CR_DDRCRCMDCOMPOFFSET_STRUCT;
+
+typedef union {
+  struct {
+    U32 CmdPi0Code                              :  7;  // Bits 6:0
+    U32 CmdPi1Code                              :  7;  // Bits 13:7
+    U32 Spare                                   :  18;  // Bits 31:14
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRCMDSCH0_CR_DDRCRCMDPICODING_STRUCT;
+
+typedef union {
+  struct {
+    U32 RefPi                                   :  4;  // Bits 3:0
+    U32 DllMask                                 :  2;  // Bits 5:4
+    U32 DllRsvd1                                :  1;  // Bits 6:6
+    U32 TxOn                                    :  1;  // Bits 7:7
+    U32 IntClkOn                                :  1;  // Bits 8:8
+    U32 RepClkOn                                :  1;  // Bits 9:9
+    U32 IOLBCtl                                 :  2;  // Bits 11:10
+    U32 OdtMode                                 :  1;  // Bits 12:12
+    U32 CmdTxEq                                 :  2;  // Bits 14:13
+    U32 EarlyWeakDrive                          :  2;  // Bits 16:15
+    U32 Reserved                                :  4;  // Bits 20:17
+    U32 RxVref                                  :  6;  // Bits 26:21
+    U32 VccddqHi                                :  1;  // Bits 27:27
+    U32 DllWeakLock                             :  1;  // Bits 28:28
+    U32 LPDDR_Mode                              :  1;  // Bits 29:29
+    U32 LPDdrCAA_Dis                            :  1;  // Bits 30:30
+    U32 LPDdrCAB_Dis                            :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRCMDSCH0_CR_DDRCRCMDCONTROLS_STRUCT;
+
+typedef union {
+  struct {
+    U32 RunTest                                 :  1;  // Bits 0:0
+    U32 Load                                    :  1;  // Bits 1:1
+    U32 ModeHVM                                 :  1;  // Bits 2:2
+    U32 ModeDV                                  :  1;  // Bits 3:3
+    U32 ModeADC                                 :  1;  // Bits 4:4
+    U32 LoadCount                               :  10;  // Bits 14:5
+    U32 CountStatus                             :  10;  // Bits 24:15
+    U32 Spare                                   :  7;  // Bits 31:25
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRCMDSCH0_CR_DLLPITESTANDADC_STRUCT;
+
+typedef union {
+  struct {
+    U32 Scomp                                   :  6;  // Bits 5:0
+    U32 TcoComp                                 :  6;  // Bits 11:6
+    U32 RcompDrvUp                              :  6;  // Bits 17:12
+    U32 RcompDrvDown                            :  6;  // Bits 23:18
+    U32 LsComp                                  :  3;  // Bits 26:24
+    U32 Spare                                   :  5;  // Bits 31:27
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRCMDSCH1_CR_DDRCRCMDCOMP_STRUCT;
+
+typedef union {
+  struct {
+    U32 ScompOffset                             :  5;  // Bits 4:0
+    U32 TcoCompOffset                           :  4;  // Bits 8:5
+    U32 RcompDrvUpOffset                        :  4;  // Bits 12:9
+    U32 RcompDrvDownOffset                      :  4;  // Bits 16:13
+    U32 Spare                                   :  15;  // Bits 31:17
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRCMDSCH1_CR_DDRCRCMDCOMPOFFSET_STRUCT;
+
+typedef union {
+  struct {
+    U32 CmdPi0Code                              :  7;  // Bits 6:0
+    U32 CmdPi1Code                              :  7;  // Bits 13:7
+    U32 Spare                                   :  18;  // Bits 31:14
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRCMDSCH1_CR_DDRCRCMDPICODING_STRUCT;
+
+typedef union {
+  struct {
+    U32 RefPi                                   :  4;  // Bits 3:0
+    U32 DllMask                                 :  2;  // Bits 5:4
+    U32 DllRsvd1                                :  1;  // Bits 6:6
+    U32 TxOn                                    :  1;  // Bits 7:7
+    U32 IntClkOn                                :  1;  // Bits 8:8
+    U32 RepClkOn                                :  1;  // Bits 9:9
+    U32 IOLBCtl                                 :  2;  // Bits 11:10
+    U32 OdtMode                                 :  1;  // Bits 12:12
+    U32 CmdTxEq                                 :  2;  // Bits 14:13
+    U32 EarlyWeakDrive                          :  2;  // Bits 16:15
+    U32 Reserved                                :  4;  // Bits 20:17
+    U32 RxVref                                  :  6;  // Bits 26:21
+    U32 VccddqHi                                :  1;  // Bits 27:27
+    U32 DllWeakLock                             :  1;  // Bits 28:28
+    U32 LPDDR_Mode                              :  1;  // Bits 29:29
+    U32 LPDdrCAA_Dis                            :  1;  // Bits 30:30
+    U32 LPDdrCAB_Dis                            :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRCMDSCH1_CR_DDRCRCMDCONTROLS_STRUCT;
+
+typedef union {
+  struct {
+    U32 RunTest                                 :  1;  // Bits 0:0
+    U32 Load                                    :  1;  // Bits 1:1
+    U32 ModeHVM                                 :  1;  // Bits 2:2
+    U32 ModeDV                                  :  1;  // Bits 3:3
+    U32 ModeADC                                 :  1;  // Bits 4:4
+    U32 LoadCount                               :  10;  // Bits 14:5
+    U32 CountStatus                             :  10;  // Bits 24:15
+    U32 Spare                                   :  7;  // Bits 31:25
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRCMDSCH1_CR_DLLPITESTANDADC_STRUCT;
+
+typedef union {
+  struct {
+    U32 Scomp                                   :  6;  // Bits 5:0
+    U32 TcoComp                                 :  6;  // Bits 11:6
+    U32 RcompDrvUp                              :  6;  // Bits 17:12
+    U32 RcompDrvDown                            :  6;  // Bits 23:18
+    U32 LsComp                                  :  3;  // Bits 26:24
+    U32 Spare                                   :  5;  // Bits 31:27
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRCMDCH0_CR_DDRCRCMDCOMP_STRUCT;
+
+typedef union {
+  struct {
+    U32 ScompOffset                             :  5;  // Bits 4:0
+    U32 TcoCompOffset                           :  4;  // Bits 8:5
+    U32 RcompDrvUpOffset                        :  4;  // Bits 12:9
+    U32 RcompDrvDownOffset                      :  4;  // Bits 16:13
+    U32 Spare                                   :  15;  // Bits 31:17
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRCMDCH0_CR_DDRCRCMDCOMPOFFSET_STRUCT;
+
+typedef union {
+  struct {
+    U32 CmdPi0Code                              :  7;  // Bits 6:0
+    U32 CmdPi1Code                              :  7;  // Bits 13:7
+    U32 Spare                                   :  18;  // Bits 31:14
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRCMDCH0_CR_DDRCRCMDPICODING_STRUCT;
+
+typedef union {
+  struct {
+    U32 RefPi                                   :  4;  // Bits 3:0
+    U32 DllMask                                 :  2;  // Bits 5:4
+    U32 DllRsvd1                                :  1;  // Bits 6:6
+    U32 TxOn                                    :  1;  // Bits 7:7
+    U32 IntClkOn                                :  1;  // Bits 8:8
+    U32 RepClkOn                                :  1;  // Bits 9:9
+    U32 IOLBCtl                                 :  2;  // Bits 11:10
+    U32 OdtMode                                 :  1;  // Bits 12:12
+    U32 CmdTxEq                                 :  2;  // Bits 14:13
+    U32 EarlyWeakDrive                          :  2;  // Bits 16:15
+    U32 Reserved                                :  4;  // Bits 20:17
+    U32 RxVref                                  :  6;  // Bits 26:21
+    U32 VccddqHi                                :  1;  // Bits 27:27
+    U32 DllWeakLock                             :  1;  // Bits 28:28
+    U32 LPDDR_Mode                              :  1;  // Bits 29:29
+    U32 LPDdrCAA_Dis                            :  1;  // Bits 30:30
+    U32 LPDdrCAB_Dis                            :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRCMDCH0_CR_DDRCRCMDCONTROLS_STRUCT;
+
+typedef union {
+  struct {
+    U32 RunTest                                 :  1;  // Bits 0:0
+    U32 Load                                    :  1;  // Bits 1:1
+    U32 ModeHVM                                 :  1;  // Bits 2:2
+    U32 ModeDV                                  :  1;  // Bits 3:3
+    U32 ModeADC                                 :  1;  // Bits 4:4
+    U32 LoadCount                               :  10;  // Bits 14:5
+    U32 CountStatus                             :  10;  // Bits 24:15
+    U32 Spare                                   :  7;  // Bits 31:25
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRCMDCH0_CR_DLLPITESTANDADC_STRUCT;
+
+typedef union {
+  struct {
+    U32 Scomp                                   :  6;  // Bits 5:0
+    U32 TcoComp                                 :  6;  // Bits 11:6
+    U32 RcompDrvUp                              :  6;  // Bits 17:12
+    U32 RcompDrvDown                            :  6;  // Bits 23:18
+    U32 LsComp                                  :  3;  // Bits 26:24
+    U32 Spare                                   :  5;  // Bits 31:27
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRCMDCH1_CR_DDRCRCMDCOMP_STRUCT;
+
+typedef union {
+  struct {
+    U32 ScompOffset                             :  5;  // Bits 4:0
+    U32 TcoCompOffset                           :  4;  // Bits 8:5
+    U32 RcompDrvUpOffset                        :  4;  // Bits 12:9
+    U32 RcompDrvDownOffset                      :  4;  // Bits 16:13
+    U32 Spare                                   :  15;  // Bits 31:17
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRCMDCH1_CR_DDRCRCMDCOMPOFFSET_STRUCT;
+
+typedef union {
+  struct {
+    U32 CmdPi0Code                              :  7;  // Bits 6:0
+    U32 CmdPi1Code                              :  7;  // Bits 13:7
+    U32 Spare                                   :  18;  // Bits 31:14
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRCMDCH1_CR_DDRCRCMDPICODING_STRUCT;
+
+typedef union {
+  struct {
+    U32 RefPi                                   :  4;  // Bits 3:0
+    U32 DllMask                                 :  2;  // Bits 5:4
+    U32 DllRsvd1                                :  1;  // Bits 6:6
+    U32 TxOn                                    :  1;  // Bits 7:7
+    U32 IntClkOn                                :  1;  // Bits 8:8
+    U32 RepClkOn                                :  1;  // Bits 9:9
+    U32 IOLBCtl                                 :  2;  // Bits 11:10
+    U32 OdtMode                                 :  1;  // Bits 12:12
+    U32 CmdTxEq                                 :  2;  // Bits 14:13
+    U32 EarlyWeakDrive                          :  2;  // Bits 16:15
+    U32 Reserved                                :  4;  // Bits 20:17
+    U32 RxVref                                  :  6;  // Bits 26:21
+    U32 VccddqHi                                :  1;  // Bits 27:27
+    U32 DllWeakLock                             :  1;  // Bits 28:28
+    U32 LPDDR_Mode                              :  1;  // Bits 29:29
+    U32 LPDdrCAA_Dis                            :  1;  // Bits 30:30
+    U32 LPDdrCAB_Dis                            :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRCMDCH1_CR_DDRCRCMDCONTROLS_STRUCT;
+
+typedef union {
+  struct {
+    U32 RunTest                                 :  1;  // Bits 0:0
+    U32 Load                                    :  1;  // Bits 1:1
+    U32 ModeHVM                                 :  1;  // Bits 2:2
+    U32 ModeDV                                  :  1;  // Bits 3:3
+    U32 ModeADC                                 :  1;  // Bits 4:4
+    U32 LoadCount                               :  10;  // Bits 14:5
+    U32 CountStatus                             :  10;  // Bits 24:15
+    U32 Spare                                   :  7;  // Bits 31:25
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRCMDCH1_CR_DLLPITESTANDADC_STRUCT;
+
+#define DDRCMD_CR_DDRCRCMDCOMP_REG                                   (0x00003700)
+  #define DDRCMD_CR_DDRCRCMDCOMP_Scomp_OFF                             ( 0)
+  #define DDRCMD_CR_DDRCRCMDCOMP_Scomp_WID                             ( 6)
+  #define DDRCMD_CR_DDRCRCMDCOMP_Scomp_MSK                             (0x0000003F)
+  #define DDRCMD_CR_DDRCRCMDCOMP_Scomp_MAX                             (0x0000003F)
+  #define DDRCMD_CR_DDRCRCMDCOMP_Scomp_DEF                             (0x00000000)
+  #define DDRCMD_CR_DDRCRCMDCOMP_TcoComp_OFF                           ( 6)
+  #define DDRCMD_CR_DDRCRCMDCOMP_TcoComp_WID                           ( 6)
+  #define DDRCMD_CR_DDRCRCMDCOMP_TcoComp_MSK                           (0x00000FC0)
+  #define DDRCMD_CR_DDRCRCMDCOMP_TcoComp_MAX                           (0x0000003F)
+  #define DDRCMD_CR_DDRCRCMDCOMP_TcoComp_DEF                           (0x00000000)
+  #define DDRCMD_CR_DDRCRCMDCOMP_RcompDrvUp_OFF                        (12)
+  #define DDRCMD_CR_DDRCRCMDCOMP_RcompDrvUp_WID                        ( 6)
+  #define DDRCMD_CR_DDRCRCMDCOMP_RcompDrvUp_MSK                        (0x0003F000)
+  #define DDRCMD_CR_DDRCRCMDCOMP_RcompDrvUp_MAX                        (0x0000003F)
+  #define DDRCMD_CR_DDRCRCMDCOMP_RcompDrvUp_DEF                        (0x00000000)
+  #define DDRCMD_CR_DDRCRCMDCOMP_RcompDrvDown_OFF                      (18)
+  #define DDRCMD_CR_DDRCRCMDCOMP_RcompDrvDown_WID                      ( 6)
+  #define DDRCMD_CR_DDRCRCMDCOMP_RcompDrvDown_MSK                      (0x00FC0000)
+  #define DDRCMD_CR_DDRCRCMDCOMP_RcompDrvDown_MAX                      (0x0000003F)
+  #define DDRCMD_CR_DDRCRCMDCOMP_RcompDrvDown_DEF                      (0x00000000)
+  #define DDRCMD_CR_DDRCRCMDCOMP_LsComp_OFF                            (24)
+  #define DDRCMD_CR_DDRCRCMDCOMP_LsComp_WID                            ( 3)
+  #define DDRCMD_CR_DDRCRCMDCOMP_LsComp_MSK                            (0x07000000)
+  #define DDRCMD_CR_DDRCRCMDCOMP_LsComp_MAX                            (0x00000007)
+  #define DDRCMD_CR_DDRCRCMDCOMP_LsComp_DEF                            (0x00000004)
+  #define DDRCMD_CR_DDRCRCMDCOMP_Spare_OFF                             (27)
+  #define DDRCMD_CR_DDRCRCMDCOMP_Spare_WID                             ( 5)
+  #define DDRCMD_CR_DDRCRCMDCOMP_Spare_MSK                             (0xF8000000)
+  #define DDRCMD_CR_DDRCRCMDCOMP_Spare_MAX                             (0x0000001F)
+  #define DDRCMD_CR_DDRCRCMDCOMP_Spare_DEF                             (0x00000000)
+
+#define DDRCMD_CR_DDRCRCMDCOMPOFFSET_REG                             (0x00003704)
+  #define DDRCMD_CR_DDRCRCMDCOMPOFFSET_ScompOffset_OFF                 ( 0)
+  #define DDRCMD_CR_DDRCRCMDCOMPOFFSET_ScompOffset_WID                 ( 5)
+  #define DDRCMD_CR_DDRCRCMDCOMPOFFSET_ScompOffset_MSK                 (0x0000001F)
+  #define DDRCMD_CR_DDRCRCMDCOMPOFFSET_ScompOffset_MAX                 (0x0000001F)
+  #define DDRCMD_CR_DDRCRCMDCOMPOFFSET_ScompOffset_DEF                 (0x00000000)
+  #define DDRCMD_CR_DDRCRCMDCOMPOFFSET_TcoCompOffset_OFF               ( 5)
+  #define DDRCMD_CR_DDRCRCMDCOMPOFFSET_TcoCompOffset_WID               ( 4)
+  #define DDRCMD_CR_DDRCRCMDCOMPOFFSET_TcoCompOffset_MSK               (0x000001E0)
+  #define DDRCMD_CR_DDRCRCMDCOMPOFFSET_TcoCompOffset_MAX               (0x0000000F)
+  #define DDRCMD_CR_DDRCRCMDCOMPOFFSET_TcoCompOffset_DEF               (0x00000000)
+  #define DDRCMD_CR_DDRCRCMDCOMPOFFSET_RcompDrvUpOffset_OFF            ( 9)
+  #define DDRCMD_CR_DDRCRCMDCOMPOFFSET_RcompDrvUpOffset_WID            ( 4)
+  #define DDRCMD_CR_DDRCRCMDCOMPOFFSET_RcompDrvUpOffset_MSK            (0x00001E00)
+  #define DDRCMD_CR_DDRCRCMDCOMPOFFSET_RcompDrvUpOffset_MAX            (0x0000000F)
+  #define DDRCMD_CR_DDRCRCMDCOMPOFFSET_RcompDrvUpOffset_DEF            (0x00000000)
+  #define DDRCMD_CR_DDRCRCMDCOMPOFFSET_RcompDrvDownOffset_OFF          (13)
+  #define DDRCMD_CR_DDRCRCMDCOMPOFFSET_RcompDrvDownOffset_WID          ( 4)
+  #define DDRCMD_CR_DDRCRCMDCOMPOFFSET_RcompDrvDownOffset_MSK          (0x0001E000)
+  #define DDRCMD_CR_DDRCRCMDCOMPOFFSET_RcompDrvDownOffset_MAX          (0x0000000F)
+  #define DDRCMD_CR_DDRCRCMDCOMPOFFSET_RcompDrvDownOffset_DEF          (0x00000000)
+  #define DDRCMD_CR_DDRCRCMDCOMPOFFSET_Spare_OFF                       (17)
+  #define DDRCMD_CR_DDRCRCMDCOMPOFFSET_Spare_WID                       (15)
+  #define DDRCMD_CR_DDRCRCMDCOMPOFFSET_Spare_MSK                       (0xFFFE0000)
+  #define DDRCMD_CR_DDRCRCMDCOMPOFFSET_Spare_MAX                       (0x00007FFF)
+  #define DDRCMD_CR_DDRCRCMDCOMPOFFSET_Spare_DEF                       (0x00000000)
+
+#define DDRCMD_CR_DDRCRCMDPICODING_REG                               (0x00003708)
+  #define DDRCMD_CR_DDRCRCMDPICODING_CmdPi0Code_OFF                    ( 0)
+  #define DDRCMD_CR_DDRCRCMDPICODING_CmdPi0Code_WID                    ( 7)
+  #define DDRCMD_CR_DDRCRCMDPICODING_CmdPi0Code_MSK                    (0x0000007F)
+  #define DDRCMD_CR_DDRCRCMDPICODING_CmdPi0Code_MAX                    (0x0000007F)
+  #define DDRCMD_CR_DDRCRCMDPICODING_CmdPi0Code_DEF                    (0x00000000)
+  #define DDRCMD_CR_DDRCRCMDPICODING_CmdPi1Code_OFF                    ( 7)
+  #define DDRCMD_CR_DDRCRCMDPICODING_CmdPi1Code_WID                    ( 7)
+  #define DDRCMD_CR_DDRCRCMDPICODING_CmdPi1Code_MSK                    (0x00003F80)
+  #define DDRCMD_CR_DDRCRCMDPICODING_CmdPi1Code_MAX                    (0x0000007F)
+  #define DDRCMD_CR_DDRCRCMDPICODING_CmdPi1Code_DEF                    (0x00000000)
+  #define DDRCMD_CR_DDRCRCMDPICODING_Spare_OFF                         (14)
+  #define DDRCMD_CR_DDRCRCMDPICODING_Spare_WID                         (18)
+  #define DDRCMD_CR_DDRCRCMDPICODING_Spare_MSK                         (0xFFFFC000)
+  #define DDRCMD_CR_DDRCRCMDPICODING_Spare_MAX                         (0x0003FFFF)
+  #define DDRCMD_CR_DDRCRCMDPICODING_Spare_DEF                         (0x00000000)
+
+#define DDRCMD_CR_DDRCRCMDCONTROLS_REG                               (0x0000370C)
+  #define DDRCMD_CR_DDRCRCMDCONTROLS_RefPi_OFF                         ( 0)
+  #define DDRCMD_CR_DDRCRCMDCONTROLS_RefPi_WID                         ( 4)
+  #define DDRCMD_CR_DDRCRCMDCONTROLS_RefPi_MSK                         (0x0000000F)
+  #define DDRCMD_CR_DDRCRCMDCONTROLS_RefPi_MAX                         (0x0000000F)
+  #define DDRCMD_CR_DDRCRCMDCONTROLS_RefPi_DEF                         (0x00000000)
+  #define DDRCMD_CR_DDRCRCMDCONTROLS_DllMask_OFF                       ( 4)
+  #define DDRCMD_CR_DDRCRCMDCONTROLS_DllMask_WID                       ( 2)
+  #define DDRCMD_CR_DDRCRCMDCONTROLS_DllMask_MSK                       (0x00000030)
+  #define DDRCMD_CR_DDRCRCMDCONTROLS_DllMask_MAX                       (0x00000003)
+  #define DDRCMD_CR_DDRCRCMDCONTROLS_DllMask_DEF                       (0x00000000)
+  #define DDRCMD_CR_DDRCRCMDCONTROLS_DllRsvd1_OFF                      ( 6)
+  #define DDRCMD_CR_DDRCRCMDCONTROLS_DllRsvd1_WID                      ( 1)
+  #define DDRCMD_CR_DDRCRCMDCONTROLS_DllRsvd1_MSK                      (0x00000040)
+  #define DDRCMD_CR_DDRCRCMDCONTROLS_DllRsvd1_MAX                      (0x00000001)
+  #define DDRCMD_CR_DDRCRCMDCONTROLS_DllRsvd1_DEF                      (0x00000000)
+  #define DDRCMD_CR_DDRCRCMDCONTROLS_TxOn_OFF                          ( 7)
+  #define DDRCMD_CR_DDRCRCMDCONTROLS_TxOn_WID                          ( 1)
+  #define DDRCMD_CR_DDRCRCMDCONTROLS_TxOn_MSK                          (0x00000080)
+  #define DDRCMD_CR_DDRCRCMDCONTROLS_TxOn_MAX                          (0x00000001)
+  #define DDRCMD_CR_DDRCRCMDCONTROLS_TxOn_DEF                          (0x00000000)
+  #define DDRCMD_CR_DDRCRCMDCONTROLS_IntClkOn_OFF                      ( 8)
+  #define DDRCMD_CR_DDRCRCMDCONTROLS_IntClkOn_WID                      ( 1)
+  #define DDRCMD_CR_DDRCRCMDCONTROLS_IntClkOn_MSK                      (0x00000100)
+  #define DDRCMD_CR_DDRCRCMDCONTROLS_IntClkOn_MAX                      (0x00000001)
+  #define DDRCMD_CR_DDRCRCMDCONTROLS_IntClkOn_DEF                      (0x00000000)
+  #define DDRCMD_CR_DDRCRCMDCONTROLS_RepClkOn_OFF                      ( 9)
+  #define DDRCMD_CR_DDRCRCMDCONTROLS_RepClkOn_WID                      ( 1)
+  #define DDRCMD_CR_DDRCRCMDCONTROLS_RepClkOn_MSK                      (0x00000200)
+  #define DDRCMD_CR_DDRCRCMDCONTROLS_RepClkOn_MAX                      (0x00000001)
+  #define DDRCMD_CR_DDRCRCMDCONTROLS_RepClkOn_DEF                      (0x00000000)
+  #define DDRCMD_CR_DDRCRCMDCONTROLS_IOLBCtl_OFF                       (10)
+  #define DDRCMD_CR_DDRCRCMDCONTROLS_IOLBCtl_WID                       ( 2)
+  #define DDRCMD_CR_DDRCRCMDCONTROLS_IOLBCtl_MSK                       (0x00000C00)
+  #define DDRCMD_CR_DDRCRCMDCONTROLS_IOLBCtl_MAX                       (0x00000003)
+  #define DDRCMD_CR_DDRCRCMDCONTROLS_IOLBCtl_DEF                       (0x00000000)
+  #define DDRCMD_CR_DDRCRCMDCONTROLS_OdtMode_OFF                       (12)
+  #define DDRCMD_CR_DDRCRCMDCONTROLS_OdtMode_WID                       ( 1)
+  #define DDRCMD_CR_DDRCRCMDCONTROLS_OdtMode_MSK                       (0x00001000)
+  #define DDRCMD_CR_DDRCRCMDCONTROLS_OdtMode_MAX                       (0x00000001)
+  #define DDRCMD_CR_DDRCRCMDCONTROLS_OdtMode_DEF                       (0x00000000)
+  #define DDRCMD_CR_DDRCRCMDCONTROLS_CmdTxEq_OFF                       (13)
+  #define DDRCMD_CR_DDRCRCMDCONTROLS_CmdTxEq_WID                       ( 2)
+  #define DDRCMD_CR_DDRCRCMDCONTROLS_CmdTxEq_MSK                       (0x00006000)
+  #define DDRCMD_CR_DDRCRCMDCONTROLS_CmdTxEq_MAX                       (0x00000003)
+  #define DDRCMD_CR_DDRCRCMDCONTROLS_CmdTxEq_DEF                       (0x00000000)
+  #define DDRCMD_CR_DDRCRCMDCONTROLS_EarlyWeakDrive_OFF                (15)
+  #define DDRCMD_CR_DDRCRCMDCONTROLS_EarlyWeakDrive_WID                ( 2)
+  #define DDRCMD_CR_DDRCRCMDCONTROLS_EarlyWeakDrive_MSK                (0x00018000)
+  #define DDRCMD_CR_DDRCRCMDCONTROLS_EarlyWeakDrive_MAX                (0x00000003)
+  #define DDRCMD_CR_DDRCRCMDCONTROLS_EarlyWeakDrive_DEF                (0x00000000)
+  #define DDRCMD_CR_DDRCRCMDCONTROLS_Reserved_OFF                      (17)
+  #define DDRCMD_CR_DDRCRCMDCONTROLS_Reserved_WID                      ( 4)
+  #define DDRCMD_CR_DDRCRCMDCONTROLS_Reserved_MSK                      (0x001E0000)
+  #define DDRCMD_CR_DDRCRCMDCONTROLS_Reserved_MAX                      (0x0000000F)
+  #define DDRCMD_CR_DDRCRCMDCONTROLS_Reserved_DEF                      (0x00000000)
+  #define DDRCMD_CR_DDRCRCMDCONTROLS_RxVref_OFF                        (21)
+  #define DDRCMD_CR_DDRCRCMDCONTROLS_RxVref_WID                        ( 6)
+  #define DDRCMD_CR_DDRCRCMDCONTROLS_RxVref_MSK                        (0x07E00000)
+  #define DDRCMD_CR_DDRCRCMDCONTROLS_RxVref_MAX                        (0x0000003F)
+  #define DDRCMD_CR_DDRCRCMDCONTROLS_RxVref_DEF                        (0x00000000)
+  #define DDRCMD_CR_DDRCRCMDCONTROLS_VccddqHi_OFF                      (27)
+  #define DDRCMD_CR_DDRCRCMDCONTROLS_VccddqHi_WID                      ( 1)
+  #define DDRCMD_CR_DDRCRCMDCONTROLS_VccddqHi_MSK                      (0x08000000)
+  #define DDRCMD_CR_DDRCRCMDCONTROLS_VccddqHi_MAX                      (0x00000001)
+  #define DDRCMD_CR_DDRCRCMDCONTROLS_VccddqHi_DEF                      (0x00000000)
+  #define DDRCMD_CR_DDRCRCMDCONTROLS_DllWeakLock_OFF                   (28)
+  #define DDRCMD_CR_DDRCRCMDCONTROLS_DllWeakLock_WID                   ( 1)
+  #define DDRCMD_CR_DDRCRCMDCONTROLS_DllWeakLock_MSK                   (0x10000000)
+  #define DDRCMD_CR_DDRCRCMDCONTROLS_DllWeakLock_MAX                   (0x00000001)
+  #define DDRCMD_CR_DDRCRCMDCONTROLS_DllWeakLock_DEF                   (0x00000000)
+  #define DDRCMD_CR_DDRCRCMDCONTROLS_LPDDR_Mode_OFF                    (29)
+  #define DDRCMD_CR_DDRCRCMDCONTROLS_LPDDR_Mode_WID                    ( 1)
+  #define DDRCMD_CR_DDRCRCMDCONTROLS_LPDDR_Mode_MSK                    (0x20000000)
+  #define DDRCMD_CR_DDRCRCMDCONTROLS_LPDDR_Mode_MAX                    (0x00000001)
+  #define DDRCMD_CR_DDRCRCMDCONTROLS_LPDDR_Mode_DEF                    (0x00000000)
+  #define DDRCMD_CR_DDRCRCMDCONTROLS_LPDdrCAA_Dis_OFF                  (30)
+  #define DDRCMD_CR_DDRCRCMDCONTROLS_LPDdrCAA_Dis_WID                  ( 1)
+  #define DDRCMD_CR_DDRCRCMDCONTROLS_LPDdrCAA_Dis_MSK                  (0x40000000)
+  #define DDRCMD_CR_DDRCRCMDCONTROLS_LPDdrCAA_Dis_MAX                  (0x00000001)
+  #define DDRCMD_CR_DDRCRCMDCONTROLS_LPDdrCAA_Dis_DEF                  (0x00000000)
+  #define DDRCMD_CR_DDRCRCMDCONTROLS_LPDdrCAB_Dis_OFF                  (31)
+  #define DDRCMD_CR_DDRCRCMDCONTROLS_LPDdrCAB_Dis_WID                  ( 1)
+  #define DDRCMD_CR_DDRCRCMDCONTROLS_LPDdrCAB_Dis_MSK                  (0x80000000)
+  #define DDRCMD_CR_DDRCRCMDCONTROLS_LPDdrCAB_Dis_MAX                  (0x00000001)
+  #define DDRCMD_CR_DDRCRCMDCONTROLS_LPDdrCAB_Dis_DEF                  (0x00000000)
+
+#define DDRCMD_CR_DLLPITESTANDADC_REG                                (0x00003724)
+  #define DDRCMD_CR_DLLPITESTANDADC_RunTest_OFF                        ( 0)
+  #define DDRCMD_CR_DLLPITESTANDADC_RunTest_WID                        ( 1)
+  #define DDRCMD_CR_DLLPITESTANDADC_RunTest_MSK                        (0x00000001)
+  #define DDRCMD_CR_DLLPITESTANDADC_RunTest_MAX                        (0x00000001)
+  #define DDRCMD_CR_DLLPITESTANDADC_RunTest_DEF                        (0x00000000)
+  #define DDRCMD_CR_DLLPITESTANDADC_Load_OFF                           ( 1)
+  #define DDRCMD_CR_DLLPITESTANDADC_Load_WID                           ( 1)
+  #define DDRCMD_CR_DLLPITESTANDADC_Load_MSK                           (0x00000002)
+  #define DDRCMD_CR_DLLPITESTANDADC_Load_MAX                           (0x00000001)
+  #define DDRCMD_CR_DLLPITESTANDADC_Load_DEF                           (0x00000000)
+  #define DDRCMD_CR_DLLPITESTANDADC_ModeHVM_OFF                        ( 2)
+  #define DDRCMD_CR_DLLPITESTANDADC_ModeHVM_WID                        ( 1)
+  #define DDRCMD_CR_DLLPITESTANDADC_ModeHVM_MSK                        (0x00000004)
+  #define DDRCMD_CR_DLLPITESTANDADC_ModeHVM_MAX                        (0x00000001)
+  #define DDRCMD_CR_DLLPITESTANDADC_ModeHVM_DEF                        (0x00000000)
+  #define DDRCMD_CR_DLLPITESTANDADC_ModeDV_OFF                         ( 3)
+  #define DDRCMD_CR_DLLPITESTANDADC_ModeDV_WID                         ( 1)
+  #define DDRCMD_CR_DLLPITESTANDADC_ModeDV_MSK                         (0x00000008)
+  #define DDRCMD_CR_DLLPITESTANDADC_ModeDV_MAX                         (0x00000001)
+  #define DDRCMD_CR_DLLPITESTANDADC_ModeDV_DEF                         (0x00000000)
+  #define DDRCMD_CR_DLLPITESTANDADC_ModeADC_OFF                        ( 4)
+  #define DDRCMD_CR_DLLPITESTANDADC_ModeADC_WID                        ( 1)
+  #define DDRCMD_CR_DLLPITESTANDADC_ModeADC_MSK                        (0x00000010)
+  #define DDRCMD_CR_DLLPITESTANDADC_ModeADC_MAX                        (0x00000001)
+  #define DDRCMD_CR_DLLPITESTANDADC_ModeADC_DEF                        (0x00000000)
+  #define DDRCMD_CR_DLLPITESTANDADC_LoadCount_OFF                      ( 5)
+  #define DDRCMD_CR_DLLPITESTANDADC_LoadCount_WID                      (10)
+  #define DDRCMD_CR_DLLPITESTANDADC_LoadCount_MSK                      (0x00007FE0)
+  #define DDRCMD_CR_DLLPITESTANDADC_LoadCount_MAX                      (0x000003FF)
+  #define DDRCMD_CR_DLLPITESTANDADC_CountStatus_OFF                    (15)
+  #define DDRCMD_CR_DLLPITESTANDADC_CountStatus_WID                    (10)
+  #define DDRCMD_CR_DLLPITESTANDADC_CountStatus_MSK                    (0x01FF8000)
+  #define DDRCMD_CR_DLLPITESTANDADC_CountStatus_MAX                    (0x000003FF)
+  #define DDRCMD_CR_DLLPITESTANDADC_CountStatus_DEF                    (0x00000000)
+  #define DDRCMD_CR_DLLPITESTANDADC_Spare_OFF                          (25)
+  #define DDRCMD_CR_DLLPITESTANDADC_Spare_WID                          ( 7)
+  #define DDRCMD_CR_DLLPITESTANDADC_Spare_MSK                          (0xFE000000)
+  #define DDRCMD_CR_DLLPITESTANDADC_Spare_MAX                          (0x0000007F)
+
+#define DDRCMDNCH0_CR_DDRCRCMDCOMP_REG                               (0x00001400)
+  #define DDRCMDNCH0_CR_DDRCRCMDCOMP_Scomp_OFF                         ( 0)
+  #define DDRCMDNCH0_CR_DDRCRCMDCOMP_Scomp_WID                         ( 6)
+  #define DDRCMDNCH0_CR_DDRCRCMDCOMP_Scomp_MSK                         (0x0000003F)
+  #define DDRCMDNCH0_CR_DDRCRCMDCOMP_Scomp_MAX                         (0x0000003F)
+  #define DDRCMDNCH0_CR_DDRCRCMDCOMP_Scomp_DEF                         (0x00000000)
+  #define DDRCMDNCH0_CR_DDRCRCMDCOMP_TcoComp_OFF                       ( 6)
+  #define DDRCMDNCH0_CR_DDRCRCMDCOMP_TcoComp_WID                       ( 6)
+  #define DDRCMDNCH0_CR_DDRCRCMDCOMP_TcoComp_MSK                       (0x00000FC0)
+  #define DDRCMDNCH0_CR_DDRCRCMDCOMP_TcoComp_MAX                       (0x0000003F)
+  #define DDRCMDNCH0_CR_DDRCRCMDCOMP_TcoComp_DEF                       (0x00000000)
+  #define DDRCMDNCH0_CR_DDRCRCMDCOMP_RcompDrvUp_OFF                    (12)
+  #define DDRCMDNCH0_CR_DDRCRCMDCOMP_RcompDrvUp_WID                    ( 6)
+  #define DDRCMDNCH0_CR_DDRCRCMDCOMP_RcompDrvUp_MSK                    (0x0003F000)
+  #define DDRCMDNCH0_CR_DDRCRCMDCOMP_RcompDrvUp_MAX                    (0x0000003F)
+  #define DDRCMDNCH0_CR_DDRCRCMDCOMP_RcompDrvUp_DEF                    (0x00000000)
+  #define DDRCMDNCH0_CR_DDRCRCMDCOMP_RcompDrvDown_OFF                  (18)
+  #define DDRCMDNCH0_CR_DDRCRCMDCOMP_RcompDrvDown_WID                  ( 6)
+  #define DDRCMDNCH0_CR_DDRCRCMDCOMP_RcompDrvDown_MSK                  (0x00FC0000)
+  #define DDRCMDNCH0_CR_DDRCRCMDCOMP_RcompDrvDown_MAX                  (0x0000003F)
+  #define DDRCMDNCH0_CR_DDRCRCMDCOMP_RcompDrvDown_DEF                  (0x00000000)
+  #define DDRCMDNCH0_CR_DDRCRCMDCOMP_LsComp_OFF                        (24)
+  #define DDRCMDNCH0_CR_DDRCRCMDCOMP_LsComp_WID                        ( 3)
+  #define DDRCMDNCH0_CR_DDRCRCMDCOMP_LsComp_MSK                        (0x07000000)
+  #define DDRCMDNCH0_CR_DDRCRCMDCOMP_LsComp_MAX                        (0x00000007)
+  #define DDRCMDNCH0_CR_DDRCRCMDCOMP_LsComp_DEF                        (0x00000004)
+  #define DDRCMDNCH0_CR_DDRCRCMDCOMP_Spare_OFF                         (27)
+  #define DDRCMDNCH0_CR_DDRCRCMDCOMP_Spare_WID                         ( 5)
+  #define DDRCMDNCH0_CR_DDRCRCMDCOMP_Spare_MSK                         (0xF8000000)
+  #define DDRCMDNCH0_CR_DDRCRCMDCOMP_Spare_MAX                         (0x0000001F)
+  #define DDRCMDNCH0_CR_DDRCRCMDCOMP_Spare_DEF                         (0x00000000)
+
+#define DDRCMDNCH0_CR_DDRCRCMDCOMPOFFSET_REG                         (0x00001404)
+  #define DDRCMDNCH0_CR_DDRCRCMDCOMPOFFSET_ScompOffset_OFF             ( 0)
+  #define DDRCMDNCH0_CR_DDRCRCMDCOMPOFFSET_ScompOffset_WID             ( 5)
+  #define DDRCMDNCH0_CR_DDRCRCMDCOMPOFFSET_ScompOffset_MSK             (0x0000001F)
+  #define DDRCMDNCH0_CR_DDRCRCMDCOMPOFFSET_ScompOffset_MAX             (0x0000001F)
+  #define DDRCMDNCH0_CR_DDRCRCMDCOMPOFFSET_ScompOffset_DEF             (0x00000000)
+  #define DDRCMDNCH0_CR_DDRCRCMDCOMPOFFSET_TcoCompOffset_OFF           ( 5)
+  #define DDRCMDNCH0_CR_DDRCRCMDCOMPOFFSET_TcoCompOffset_WID           ( 4)
+  #define DDRCMDNCH0_CR_DDRCRCMDCOMPOFFSET_TcoCompOffset_MSK           (0x000001E0)
+  #define DDRCMDNCH0_CR_DDRCRCMDCOMPOFFSET_TcoCompOffset_MAX           (0x0000000F)
+  #define DDRCMDNCH0_CR_DDRCRCMDCOMPOFFSET_TcoCompOffset_DEF           (0x00000000)
+  #define DDRCMDNCH0_CR_DDRCRCMDCOMPOFFSET_RcompDrvUpOffset_OFF        ( 9)
+  #define DDRCMDNCH0_CR_DDRCRCMDCOMPOFFSET_RcompDrvUpOffset_WID        ( 4)
+  #define DDRCMDNCH0_CR_DDRCRCMDCOMPOFFSET_RcompDrvUpOffset_MSK        (0x00001E00)
+  #define DDRCMDNCH0_CR_DDRCRCMDCOMPOFFSET_RcompDrvUpOffset_MAX        (0x0000000F)
+  #define DDRCMDNCH0_CR_DDRCRCMDCOMPOFFSET_RcompDrvUpOffset_DEF        (0x00000000)
+  #define DDRCMDNCH0_CR_DDRCRCMDCOMPOFFSET_RcompDrvDownOffset_OFF      (13)
+  #define DDRCMDNCH0_CR_DDRCRCMDCOMPOFFSET_RcompDrvDownOffset_WID      ( 4)
+  #define DDRCMDNCH0_CR_DDRCRCMDCOMPOFFSET_RcompDrvDownOffset_MSK      (0x0001E000)
+  #define DDRCMDNCH0_CR_DDRCRCMDCOMPOFFSET_RcompDrvDownOffset_MAX      (0x0000000F)
+  #define DDRCMDNCH0_CR_DDRCRCMDCOMPOFFSET_RcompDrvDownOffset_DEF      (0x00000000)
+  #define DDRCMDNCH0_CR_DDRCRCMDCOMPOFFSET_Spare_OFF                   (17)
+  #define DDRCMDNCH0_CR_DDRCRCMDCOMPOFFSET_Spare_WID                   (15)
+  #define DDRCMDNCH0_CR_DDRCRCMDCOMPOFFSET_Spare_MSK                   (0xFFFE0000)
+  #define DDRCMDNCH0_CR_DDRCRCMDCOMPOFFSET_Spare_MAX                   (0x00007FFF)
+  #define DDRCMDNCH0_CR_DDRCRCMDCOMPOFFSET_Spare_DEF                   (0x00000000)
+
+#define DDRCMDNCH0_CR_DDRCRCMDPICODING_REG                           (0x00001408)
+  #define DDRCMDNCH0_CR_DDRCRCMDPICODING_CmdPi0Code_OFF                ( 0)
+  #define DDRCMDNCH0_CR_DDRCRCMDPICODING_CmdPi0Code_WID                ( 7)
+  #define DDRCMDNCH0_CR_DDRCRCMDPICODING_CmdPi0Code_MSK                (0x0000007F)
+  #define DDRCMDNCH0_CR_DDRCRCMDPICODING_CmdPi0Code_MAX                (0x0000007F)
+  #define DDRCMDNCH0_CR_DDRCRCMDPICODING_CmdPi0Code_DEF                (0x00000000)
+  #define DDRCMDNCH0_CR_DDRCRCMDPICODING_CmdPi1Code_OFF                ( 7)
+  #define DDRCMDNCH0_CR_DDRCRCMDPICODING_CmdPi1Code_WID                ( 7)
+  #define DDRCMDNCH0_CR_DDRCRCMDPICODING_CmdPi1Code_MSK                (0x00003F80)
+  #define DDRCMDNCH0_CR_DDRCRCMDPICODING_CmdPi1Code_MAX                (0x0000007F)
+  #define DDRCMDNCH0_CR_DDRCRCMDPICODING_CmdPi1Code_DEF                (0x00000000)
+  #define DDRCMDNCH0_CR_DDRCRCMDPICODING_Spare_OFF                     (14)
+  #define DDRCMDNCH0_CR_DDRCRCMDPICODING_Spare_WID                     (18)
+  #define DDRCMDNCH0_CR_DDRCRCMDPICODING_Spare_MSK                     (0xFFFFC000)
+  #define DDRCMDNCH0_CR_DDRCRCMDPICODING_Spare_MAX                     (0x0003FFFF)
+  #define DDRCMDNCH0_CR_DDRCRCMDPICODING_Spare_DEF                     (0x00000000)
+
+#define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_REG                           (0x0000140C)
+  #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_RefPi_OFF                     ( 0)
+  #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_RefPi_WID                     ( 4)
+  #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_RefPi_MSK                     (0x0000000F)
+  #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_RefPi_MAX                     (0x0000000F)
+  #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_RefPi_DEF                     (0x00000000)
+  #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_DllMask_OFF                   ( 4)
+  #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_DllMask_WID                   ( 2)
+  #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_DllMask_MSK                   (0x00000030)
+  #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_DllMask_MAX                   (0x00000003)
+  #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_DllMask_DEF                   (0x00000000)
+  #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_DllRsvd1_OFF                  ( 6)
+  #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_DllRsvd1_WID                  ( 1)
+  #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_DllRsvd1_MSK                  (0x00000040)
+  #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_DllRsvd1_MAX                  (0x00000001)
+  #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_DllRsvd1_DEF                  (0x00000000)
+  #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_TxOn_OFF                      ( 7)
+  #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_TxOn_WID                      ( 1)
+  #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_TxOn_MSK                      (0x00000080)
+  #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_TxOn_MAX                      (0x00000001)
+  #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_TxOn_DEF                      (0x00000000)
+  #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_IntClkOn_OFF                  ( 8)
+  #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_IntClkOn_WID                  ( 1)
+  #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_IntClkOn_MSK                  (0x00000100)
+  #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_IntClkOn_MAX                  (0x00000001)
+  #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_IntClkOn_DEF                  (0x00000000)
+  #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_RepClkOn_OFF                  ( 9)
+  #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_RepClkOn_WID                  ( 1)
+  #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_RepClkOn_MSK                  (0x00000200)
+  #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_RepClkOn_MAX                  (0x00000001)
+  #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_RepClkOn_DEF                  (0x00000000)
+  #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_IOLBCtl_OFF                   (10)
+  #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_IOLBCtl_WID                   ( 2)
+  #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_IOLBCtl_MSK                   (0x00000C00)
+  #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_IOLBCtl_MAX                   (0x00000003)
+  #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_IOLBCtl_DEF                   (0x00000000)
+  #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_OdtMode_OFF                   (12)
+  #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_OdtMode_WID                   ( 1)
+  #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_OdtMode_MSK                   (0x00001000)
+  #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_OdtMode_MAX                   (0x00000001)
+  #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_OdtMode_DEF                   (0x00000000)
+  #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_CmdTxEq_OFF                   (13)
+  #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_CmdTxEq_WID                   ( 2)
+  #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_CmdTxEq_MSK                   (0x00006000)
+  #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_CmdTxEq_MAX                   (0x00000003)
+  #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_CmdTxEq_DEF                   (0x00000000)
+  #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_EarlyWeakDrive_OFF            (15)
+  #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_EarlyWeakDrive_WID            ( 2)
+  #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_EarlyWeakDrive_MSK            (0x00018000)
+  #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_EarlyWeakDrive_MAX            (0x00000003)
+  #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_EarlyWeakDrive_DEF            (0x00000000)
+  #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_Reserved_OFF                  (17)
+  #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_Reserved_WID                  ( 4)
+  #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_Reserved_MSK                  (0x001E0000)
+  #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_Reserved_MAX                  (0x0000000F)
+  #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_Reserved_DEF                  (0x00000000)
+  #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_RxVref_OFF                    (21)
+  #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_RxVref_WID                    ( 6)
+  #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_RxVref_MSK                    (0x07E00000)
+  #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_RxVref_MAX                    (0x0000003F)
+  #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_RxVref_DEF                    (0x00000000)
+  #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_VccddqHi_OFF                  (27)
+  #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_VccddqHi_WID                  ( 1)
+  #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_VccddqHi_MSK                  (0x08000000)
+  #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_VccddqHi_MAX                  (0x00000001)
+  #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_VccddqHi_DEF                  (0x00000000)
+  #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_DllWeakLock_OFF               (28)
+  #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_DllWeakLock_WID               ( 1)
+  #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_DllWeakLock_MSK               (0x10000000)
+  #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_DllWeakLock_MAX               (0x00000001)
+  #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_DllWeakLock_DEF               (0x00000000)
+  #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_LPDDR_Mode_OFF                (29)
+  #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_LPDDR_Mode_WID                ( 1)
+  #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_LPDDR_Mode_MSK                (0x20000000)
+  #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_LPDDR_Mode_MAX                (0x00000001)
+  #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_LPDDR_Mode_DEF                (0x00000000)
+  #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_LPDdrCAA_Dis_OFF              (30)
+  #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_LPDdrCAA_Dis_WID              ( 1)
+  #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_LPDdrCAA_Dis_MSK              (0x40000000)
+  #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_LPDdrCAA_Dis_MAX              (0x00000001)
+  #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_LPDdrCAA_Dis_DEF              (0x00000000)
+  #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_LPDdrCAB_Dis_OFF              (31)
+  #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_LPDdrCAB_Dis_WID              ( 1)
+  #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_LPDdrCAB_Dis_MSK              (0x80000000)
+  #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_LPDdrCAB_Dis_MAX              (0x00000001)
+  #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_LPDdrCAB_Dis_DEF              (0x00000000)
+
+#define DDRCMDNCH0_CR_DLLPITESTANDADC_REG                            (0x00001424)
+  #define DDRCMDNCH0_CR_DLLPITESTANDADC_RunTest_OFF                    ( 0)
+  #define DDRCMDNCH0_CR_DLLPITESTANDADC_RunTest_WID                    ( 1)
+  #define DDRCMDNCH0_CR_DLLPITESTANDADC_RunTest_MSK                    (0x00000001)
+  #define DDRCMDNCH0_CR_DLLPITESTANDADC_RunTest_MAX                    (0x00000001)
+  #define DDRCMDNCH0_CR_DLLPITESTANDADC_RunTest_DEF                    (0x00000000)
+  #define DDRCMDNCH0_CR_DLLPITESTANDADC_Load_OFF                       ( 1)
+  #define DDRCMDNCH0_CR_DLLPITESTANDADC_Load_WID                       ( 1)
+  #define DDRCMDNCH0_CR_DLLPITESTANDADC_Load_MSK                       (0x00000002)
+  #define DDRCMDNCH0_CR_DLLPITESTANDADC_Load_MAX                       (0x00000001)
+  #define DDRCMDNCH0_CR_DLLPITESTANDADC_Load_DEF                       (0x00000000)
+  #define DDRCMDNCH0_CR_DLLPITESTANDADC_ModeHVM_OFF                    ( 2)
+  #define DDRCMDNCH0_CR_DLLPITESTANDADC_ModeHVM_WID                    ( 1)
+  #define DDRCMDNCH0_CR_DLLPITESTANDADC_ModeHVM_MSK                    (0x00000004)
+  #define DDRCMDNCH0_CR_DLLPITESTANDADC_ModeHVM_MAX                    (0x00000001)
+  #define DDRCMDNCH0_CR_DLLPITESTANDADC_ModeHVM_DEF                    (0x00000000)
+  #define DDRCMDNCH0_CR_DLLPITESTANDADC_ModeDV_OFF                     ( 3)
+  #define DDRCMDNCH0_CR_DLLPITESTANDADC_ModeDV_WID                     ( 1)
+  #define DDRCMDNCH0_CR_DLLPITESTANDADC_ModeDV_MSK                     (0x00000008)
+  #define DDRCMDNCH0_CR_DLLPITESTANDADC_ModeDV_MAX                     (0x00000001)
+  #define DDRCMDNCH0_CR_DLLPITESTANDADC_ModeDV_DEF                     (0x00000000)
+  #define DDRCMDNCH0_CR_DLLPITESTANDADC_ModeADC_OFF                    ( 4)
+  #define DDRCMDNCH0_CR_DLLPITESTANDADC_ModeADC_WID                    ( 1)
+  #define DDRCMDNCH0_CR_DLLPITESTANDADC_ModeADC_MSK                    (0x00000010)
+  #define DDRCMDNCH0_CR_DLLPITESTANDADC_ModeADC_MAX                    (0x00000001)
+  #define DDRCMDNCH0_CR_DLLPITESTANDADC_ModeADC_DEF                    (0x00000000)
+  #define DDRCMDNCH0_CR_DLLPITESTANDADC_LoadCount_OFF                  ( 5)
+  #define DDRCMDNCH0_CR_DLLPITESTANDADC_LoadCount_WID                  (10)
+  #define DDRCMDNCH0_CR_DLLPITESTANDADC_LoadCount_MSK                  (0x00007FE0)
+  #define DDRCMDNCH0_CR_DLLPITESTANDADC_LoadCount_MAX                  (0x000003FF)
+  #define DDRCMDNCH0_CR_DLLPITESTANDADC_CountStatus_OFF                (15)
+  #define DDRCMDNCH0_CR_DLLPITESTANDADC_CountStatus_WID                (10)
+  #define DDRCMDNCH0_CR_DLLPITESTANDADC_CountStatus_MSK                (0x01FF8000)
+  #define DDRCMDNCH0_CR_DLLPITESTANDADC_CountStatus_MAX                (0x000003FF)
+  #define DDRCMDNCH0_CR_DLLPITESTANDADC_CountStatus_DEF                (0x00000000)
+  #define DDRCMDNCH0_CR_DLLPITESTANDADC_Spare_OFF                      (25)
+  #define DDRCMDNCH0_CR_DLLPITESTANDADC_Spare_WID                      ( 7)
+  #define DDRCMDNCH0_CR_DLLPITESTANDADC_Spare_MSK                      (0xFE000000)
+  #define DDRCMDNCH0_CR_DLLPITESTANDADC_Spare_MAX                      (0x0000007F)
+
+#define DDRCMDNCH1_CR_DDRCRCMDCOMP_REG                               (0x00001500)
+  #define DDRCMDNCH1_CR_DDRCRCMDCOMP_Scomp_OFF                         ( 0)
+  #define DDRCMDNCH1_CR_DDRCRCMDCOMP_Scomp_WID                         ( 6)
+  #define DDRCMDNCH1_CR_DDRCRCMDCOMP_Scomp_MSK                         (0x0000003F)
+  #define DDRCMDNCH1_CR_DDRCRCMDCOMP_Scomp_MAX                         (0x0000003F)
+  #define DDRCMDNCH1_CR_DDRCRCMDCOMP_Scomp_DEF                         (0x00000000)
+  #define DDRCMDNCH1_CR_DDRCRCMDCOMP_TcoComp_OFF                       ( 6)
+  #define DDRCMDNCH1_CR_DDRCRCMDCOMP_TcoComp_WID                       ( 6)
+  #define DDRCMDNCH1_CR_DDRCRCMDCOMP_TcoComp_MSK                       (0x00000FC0)
+  #define DDRCMDNCH1_CR_DDRCRCMDCOMP_TcoComp_MAX                       (0x0000003F)
+  #define DDRCMDNCH1_CR_DDRCRCMDCOMP_TcoComp_DEF                       (0x00000000)
+  #define DDRCMDNCH1_CR_DDRCRCMDCOMP_RcompDrvUp_OFF                    (12)
+  #define DDRCMDNCH1_CR_DDRCRCMDCOMP_RcompDrvUp_WID                    ( 6)
+  #define DDRCMDNCH1_CR_DDRCRCMDCOMP_RcompDrvUp_MSK                    (0x0003F000)
+  #define DDRCMDNCH1_CR_DDRCRCMDCOMP_RcompDrvUp_MAX                    (0x0000003F)
+  #define DDRCMDNCH1_CR_DDRCRCMDCOMP_RcompDrvUp_DEF                    (0x00000000)
+  #define DDRCMDNCH1_CR_DDRCRCMDCOMP_RcompDrvDown_OFF                  (18)
+  #define DDRCMDNCH1_CR_DDRCRCMDCOMP_RcompDrvDown_WID                  ( 6)
+  #define DDRCMDNCH1_CR_DDRCRCMDCOMP_RcompDrvDown_MSK                  (0x00FC0000)
+  #define DDRCMDNCH1_CR_DDRCRCMDCOMP_RcompDrvDown_MAX                  (0x0000003F)
+  #define DDRCMDNCH1_CR_DDRCRCMDCOMP_RcompDrvDown_DEF                  (0x00000000)
+  #define DDRCMDNCH1_CR_DDRCRCMDCOMP_LsComp_OFF                        (24)
+  #define DDRCMDNCH1_CR_DDRCRCMDCOMP_LsComp_WID                        ( 3)
+  #define DDRCMDNCH1_CR_DDRCRCMDCOMP_LsComp_MSK                        (0x07000000)
+  #define DDRCMDNCH1_CR_DDRCRCMDCOMP_LsComp_MAX                        (0x00000007)
+  #define DDRCMDNCH1_CR_DDRCRCMDCOMP_LsComp_DEF                        (0x00000004)
+  #define DDRCMDNCH1_CR_DDRCRCMDCOMP_Spare_OFF                         (27)
+  #define DDRCMDNCH1_CR_DDRCRCMDCOMP_Spare_WID                         ( 5)
+  #define DDRCMDNCH1_CR_DDRCRCMDCOMP_Spare_MSK                         (0xF8000000)
+  #define DDRCMDNCH1_CR_DDRCRCMDCOMP_Spare_MAX                         (0x0000001F)
+  #define DDRCMDNCH1_CR_DDRCRCMDCOMP_Spare_DEF                         (0x00000000)
+
+#define DDRCMDNCH1_CR_DDRCRCMDCOMPOFFSET_REG                         (0x00001504)
+  #define DDRCMDNCH1_CR_DDRCRCMDCOMPOFFSET_ScompOffset_OFF             ( 0)
+  #define DDRCMDNCH1_CR_DDRCRCMDCOMPOFFSET_ScompOffset_WID             ( 5)
+  #define DDRCMDNCH1_CR_DDRCRCMDCOMPOFFSET_ScompOffset_MSK             (0x0000001F)
+  #define DDRCMDNCH1_CR_DDRCRCMDCOMPOFFSET_ScompOffset_MAX             (0x0000001F)
+  #define DDRCMDNCH1_CR_DDRCRCMDCOMPOFFSET_ScompOffset_DEF             (0x00000000)
+  #define DDRCMDNCH1_CR_DDRCRCMDCOMPOFFSET_TcoCompOffset_OFF           ( 5)
+  #define DDRCMDNCH1_CR_DDRCRCMDCOMPOFFSET_TcoCompOffset_WID           ( 4)
+  #define DDRCMDNCH1_CR_DDRCRCMDCOMPOFFSET_TcoCompOffset_MSK           (0x000001E0)
+  #define DDRCMDNCH1_CR_DDRCRCMDCOMPOFFSET_TcoCompOffset_MAX           (0x0000000F)
+  #define DDRCMDNCH1_CR_DDRCRCMDCOMPOFFSET_TcoCompOffset_DEF           (0x00000000)
+  #define DDRCMDNCH1_CR_DDRCRCMDCOMPOFFSET_RcompDrvUpOffset_OFF        ( 9)
+  #define DDRCMDNCH1_CR_DDRCRCMDCOMPOFFSET_RcompDrvUpOffset_WID        ( 4)
+  #define DDRCMDNCH1_CR_DDRCRCMDCOMPOFFSET_RcompDrvUpOffset_MSK        (0x00001E00)
+  #define DDRCMDNCH1_CR_DDRCRCMDCOMPOFFSET_RcompDrvUpOffset_MAX        (0x0000000F)
+  #define DDRCMDNCH1_CR_DDRCRCMDCOMPOFFSET_RcompDrvUpOffset_DEF        (0x00000000)
+  #define DDRCMDNCH1_CR_DDRCRCMDCOMPOFFSET_RcompDrvDownOffset_OFF      (13)
+  #define DDRCMDNCH1_CR_DDRCRCMDCOMPOFFSET_RcompDrvDownOffset_WID      ( 4)
+  #define DDRCMDNCH1_CR_DDRCRCMDCOMPOFFSET_RcompDrvDownOffset_MSK      (0x0001E000)
+  #define DDRCMDNCH1_CR_DDRCRCMDCOMPOFFSET_RcompDrvDownOffset_MAX      (0x0000000F)
+  #define DDRCMDNCH1_CR_DDRCRCMDCOMPOFFSET_RcompDrvDownOffset_DEF      (0x00000000)
+  #define DDRCMDNCH1_CR_DDRCRCMDCOMPOFFSET_Spare_OFF                   (17)
+  #define DDRCMDNCH1_CR_DDRCRCMDCOMPOFFSET_Spare_WID                   (15)
+  #define DDRCMDNCH1_CR_DDRCRCMDCOMPOFFSET_Spare_MSK                   (0xFFFE0000)
+  #define DDRCMDNCH1_CR_DDRCRCMDCOMPOFFSET_Spare_MAX                   (0x00007FFF)
+  #define DDRCMDNCH1_CR_DDRCRCMDCOMPOFFSET_Spare_DEF                   (0x00000000)
+
+#define DDRCMDNCH1_CR_DDRCRCMDPICODING_REG                           (0x00001508)
+  #define DDRCMDNCH1_CR_DDRCRCMDPICODING_CmdPi0Code_OFF                ( 0)
+  #define DDRCMDNCH1_CR_DDRCRCMDPICODING_CmdPi0Code_WID                ( 7)
+  #define DDRCMDNCH1_CR_DDRCRCMDPICODING_CmdPi0Code_MSK                (0x0000007F)
+  #define DDRCMDNCH1_CR_DDRCRCMDPICODING_CmdPi0Code_MAX                (0x0000007F)
+  #define DDRCMDNCH1_CR_DDRCRCMDPICODING_CmdPi0Code_DEF                (0x00000000)
+  #define DDRCMDNCH1_CR_DDRCRCMDPICODING_CmdPi1Code_OFF                ( 7)
+  #define DDRCMDNCH1_CR_DDRCRCMDPICODING_CmdPi1Code_WID                ( 7)
+  #define DDRCMDNCH1_CR_DDRCRCMDPICODING_CmdPi1Code_MSK                (0x00003F80)
+  #define DDRCMDNCH1_CR_DDRCRCMDPICODING_CmdPi1Code_MAX                (0x0000007F)
+  #define DDRCMDNCH1_CR_DDRCRCMDPICODING_CmdPi1Code_DEF                (0x00000000)
+  #define DDRCMDNCH1_CR_DDRCRCMDPICODING_Spare_OFF                     (14)
+  #define DDRCMDNCH1_CR_DDRCRCMDPICODING_Spare_WID                     (18)
+  #define DDRCMDNCH1_CR_DDRCRCMDPICODING_Spare_MSK                     (0xFFFFC000)
+  #define DDRCMDNCH1_CR_DDRCRCMDPICODING_Spare_MAX                     (0x0003FFFF)
+  #define DDRCMDNCH1_CR_DDRCRCMDPICODING_Spare_DEF                     (0x00000000)
+
+#define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_REG                           (0x0000150C)
+  #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_RefPi_OFF                     ( 0)
+  #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_RefPi_WID                     ( 4)
+  #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_RefPi_MSK                     (0x0000000F)
+  #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_RefPi_MAX                     (0x0000000F)
+  #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_RefPi_DEF                     (0x00000000)
+  #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_DllMask_OFF                   ( 4)
+  #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_DllMask_WID                   ( 2)
+  #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_DllMask_MSK                   (0x00000030)
+  #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_DllMask_MAX                   (0x00000003)
+  #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_DllMask_DEF                   (0x00000000)
+  #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_DllRsvd1_OFF                  ( 6)
+  #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_DllRsvd1_WID                  ( 1)
+  #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_DllRsvd1_MSK                  (0x00000040)
+  #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_DllRsvd1_MAX                  (0x00000001)
+  #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_DllRsvd1_DEF                  (0x00000000)
+  #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_TxOn_OFF                      ( 7)
+  #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_TxOn_WID                      ( 1)
+  #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_TxOn_MSK                      (0x00000080)
+  #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_TxOn_MAX                      (0x00000001)
+  #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_TxOn_DEF                      (0x00000000)
+  #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_IntClkOn_OFF                  ( 8)
+  #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_IntClkOn_WID                  ( 1)
+  #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_IntClkOn_MSK                  (0x00000100)
+  #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_IntClkOn_MAX                  (0x00000001)
+  #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_IntClkOn_DEF                  (0x00000000)
+  #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_RepClkOn_OFF                  ( 9)
+  #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_RepClkOn_WID                  ( 1)
+  #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_RepClkOn_MSK                  (0x00000200)
+  #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_RepClkOn_MAX                  (0x00000001)
+  #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_RepClkOn_DEF                  (0x00000000)
+  #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_IOLBCtl_OFF                   (10)
+  #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_IOLBCtl_WID                   ( 2)
+  #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_IOLBCtl_MSK                   (0x00000C00)
+  #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_IOLBCtl_MAX                   (0x00000003)
+  #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_IOLBCtl_DEF                   (0x00000000)
+  #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_OdtMode_OFF                   (12)
+  #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_OdtMode_WID                   ( 1)
+  #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_OdtMode_MSK                   (0x00001000)
+  #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_OdtMode_MAX                   (0x00000001)
+  #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_OdtMode_DEF                   (0x00000000)
+  #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_CmdTxEq_OFF                   (13)
+  #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_CmdTxEq_WID                   ( 2)
+  #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_CmdTxEq_MSK                   (0x00006000)
+  #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_CmdTxEq_MAX                   (0x00000003)
+  #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_CmdTxEq_DEF                   (0x00000000)
+  #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_EarlyWeakDrive_OFF            (15)
+  #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_EarlyWeakDrive_WID            ( 2)
+  #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_EarlyWeakDrive_MSK            (0x00018000)
+  #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_EarlyWeakDrive_MAX            (0x00000003)
+  #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_EarlyWeakDrive_DEF            (0x00000000)
+  #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_Reserved_OFF                  (17)
+  #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_Reserved_WID                  ( 4)
+  #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_Reserved_MSK                  (0x001E0000)
+  #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_Reserved_MAX                  (0x0000000F)
+  #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_Reserved_DEF                  (0x00000000)
+  #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_RxVref_OFF                    (21)
+  #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_RxVref_WID                    ( 6)
+  #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_RxVref_MSK                    (0x07E00000)
+  #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_RxVref_MAX                    (0x0000003F)
+  #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_RxVref_DEF                    (0x00000000)
+  #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_VccddqHi_OFF                  (27)
+  #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_VccddqHi_WID                  ( 1)
+  #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_VccddqHi_MSK                  (0x08000000)
+  #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_VccddqHi_MAX                  (0x00000001)
+  #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_VccddqHi_DEF                  (0x00000000)
+  #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_DllWeakLock_OFF               (28)
+  #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_DllWeakLock_WID               ( 1)
+  #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_DllWeakLock_MSK               (0x10000000)
+  #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_DllWeakLock_MAX               (0x00000001)
+  #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_DllWeakLock_DEF               (0x00000000)
+  #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_LPDDR_Mode_OFF                (29)
+  #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_LPDDR_Mode_WID                ( 1)
+  #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_LPDDR_Mode_MSK                (0x20000000)
+  #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_LPDDR_Mode_MAX                (0x00000001)
+  #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_LPDDR_Mode_DEF                (0x00000000)
+  #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_LPDdrCAA_Dis_OFF              (30)
+  #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_LPDdrCAA_Dis_WID              ( 1)
+  #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_LPDdrCAA_Dis_MSK              (0x40000000)
+  #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_LPDdrCAA_Dis_MAX              (0x00000001)
+  #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_LPDdrCAA_Dis_DEF              (0x00000000)
+  #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_LPDdrCAB_Dis_OFF              (31)
+  #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_LPDdrCAB_Dis_WID              ( 1)
+  #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_LPDdrCAB_Dis_MSK              (0x80000000)
+  #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_LPDdrCAB_Dis_MAX              (0x00000001)
+  #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_LPDdrCAB_Dis_DEF              (0x00000000)
+
+#define DDRCMDNCH1_CR_DLLPITESTANDADC_REG                            (0x00001524)
+  #define DDRCMDNCH1_CR_DLLPITESTANDADC_RunTest_OFF                    ( 0)
+  #define DDRCMDNCH1_CR_DLLPITESTANDADC_RunTest_WID                    ( 1)
+  #define DDRCMDNCH1_CR_DLLPITESTANDADC_RunTest_MSK                    (0x00000001)
+  #define DDRCMDNCH1_CR_DLLPITESTANDADC_RunTest_MAX                    (0x00000001)
+  #define DDRCMDNCH1_CR_DLLPITESTANDADC_RunTest_DEF                    (0x00000000)
+  #define DDRCMDNCH1_CR_DLLPITESTANDADC_Load_OFF                       ( 1)
+  #define DDRCMDNCH1_CR_DLLPITESTANDADC_Load_WID                       ( 1)
+  #define DDRCMDNCH1_CR_DLLPITESTANDADC_Load_MSK                       (0x00000002)
+  #define DDRCMDNCH1_CR_DLLPITESTANDADC_Load_MAX                       (0x00000001)
+  #define DDRCMDNCH1_CR_DLLPITESTANDADC_Load_DEF                       (0x00000000)
+  #define DDRCMDNCH1_CR_DLLPITESTANDADC_ModeHVM_OFF                    ( 2)
+  #define DDRCMDNCH1_CR_DLLPITESTANDADC_ModeHVM_WID                    ( 1)
+  #define DDRCMDNCH1_CR_DLLPITESTANDADC_ModeHVM_MSK                    (0x00000004)
+  #define DDRCMDNCH1_CR_DLLPITESTANDADC_ModeHVM_MAX                    (0x00000001)
+  #define DDRCMDNCH1_CR_DLLPITESTANDADC_ModeHVM_DEF                    (0x00000000)
+  #define DDRCMDNCH1_CR_DLLPITESTANDADC_ModeDV_OFF                     ( 3)
+  #define DDRCMDNCH1_CR_DLLPITESTANDADC_ModeDV_WID                     ( 1)
+  #define DDRCMDNCH1_CR_DLLPITESTANDADC_ModeDV_MSK                     (0x00000008)
+  #define DDRCMDNCH1_CR_DLLPITESTANDADC_ModeDV_MAX                     (0x00000001)
+  #define DDRCMDNCH1_CR_DLLPITESTANDADC_ModeDV_DEF                     (0x00000000)
+  #define DDRCMDNCH1_CR_DLLPITESTANDADC_ModeADC_OFF                    ( 4)
+  #define DDRCMDNCH1_CR_DLLPITESTANDADC_ModeADC_WID                    ( 1)
+  #define DDRCMDNCH1_CR_DLLPITESTANDADC_ModeADC_MSK                    (0x00000010)
+  #define DDRCMDNCH1_CR_DLLPITESTANDADC_ModeADC_MAX                    (0x00000001)
+  #define DDRCMDNCH1_CR_DLLPITESTANDADC_ModeADC_DEF                    (0x00000000)
+  #define DDRCMDNCH1_CR_DLLPITESTANDADC_LoadCount_OFF                  ( 5)
+  #define DDRCMDNCH1_CR_DLLPITESTANDADC_LoadCount_WID                  (10)
+  #define DDRCMDNCH1_CR_DLLPITESTANDADC_LoadCount_MSK                  (0x00007FE0)
+  #define DDRCMDNCH1_CR_DLLPITESTANDADC_LoadCount_MAX                  (0x000003FF)
+  #define DDRCMDNCH1_CR_DLLPITESTANDADC_CountStatus_OFF                (15)
+  #define DDRCMDNCH1_CR_DLLPITESTANDADC_CountStatus_WID                (10)
+  #define DDRCMDNCH1_CR_DLLPITESTANDADC_CountStatus_MSK                (0x01FF8000)
+  #define DDRCMDNCH1_CR_DLLPITESTANDADC_CountStatus_MAX                (0x000003FF)
+  #define DDRCMDNCH1_CR_DLLPITESTANDADC_CountStatus_DEF                (0x00000000)
+  #define DDRCMDNCH1_CR_DLLPITESTANDADC_Spare_OFF                      (25)
+  #define DDRCMDNCH1_CR_DLLPITESTANDADC_Spare_WID                      ( 7)
+  #define DDRCMDNCH1_CR_DLLPITESTANDADC_Spare_MSK                      (0xFE000000)
+  #define DDRCMDNCH1_CR_DLLPITESTANDADC_Spare_MAX                      (0x0000007F)
+
+#define DDRCMDSCH0_CR_DDRCRCMDCOMP_REG                               (0x00001A00)
+  #define DDRCMDSCH0_CR_DDRCRCMDCOMP_Scomp_OFF                         ( 0)
+  #define DDRCMDSCH0_CR_DDRCRCMDCOMP_Scomp_WID                         ( 6)
+  #define DDRCMDSCH0_CR_DDRCRCMDCOMP_Scomp_MSK                         (0x0000003F)
+  #define DDRCMDSCH0_CR_DDRCRCMDCOMP_Scomp_MAX                         (0x0000003F)
+  #define DDRCMDSCH0_CR_DDRCRCMDCOMP_Scomp_DEF                         (0x00000000)
+  #define DDRCMDSCH0_CR_DDRCRCMDCOMP_TcoComp_OFF                       ( 6)
+  #define DDRCMDSCH0_CR_DDRCRCMDCOMP_TcoComp_WID                       ( 6)
+  #define DDRCMDSCH0_CR_DDRCRCMDCOMP_TcoComp_MSK                       (0x00000FC0)
+  #define DDRCMDSCH0_CR_DDRCRCMDCOMP_TcoComp_MAX                       (0x0000003F)
+  #define DDRCMDSCH0_CR_DDRCRCMDCOMP_TcoComp_DEF                       (0x00000000)
+  #define DDRCMDSCH0_CR_DDRCRCMDCOMP_RcompDrvUp_OFF                    (12)
+  #define DDRCMDSCH0_CR_DDRCRCMDCOMP_RcompDrvUp_WID                    ( 6)
+  #define DDRCMDSCH0_CR_DDRCRCMDCOMP_RcompDrvUp_MSK                    (0x0003F000)
+  #define DDRCMDSCH0_CR_DDRCRCMDCOMP_RcompDrvUp_MAX                    (0x0000003F)
+  #define DDRCMDSCH0_CR_DDRCRCMDCOMP_RcompDrvUp_DEF                    (0x00000000)
+  #define DDRCMDSCH0_CR_DDRCRCMDCOMP_RcompDrvDown_OFF                  (18)
+  #define DDRCMDSCH0_CR_DDRCRCMDCOMP_RcompDrvDown_WID                  ( 6)
+  #define DDRCMDSCH0_CR_DDRCRCMDCOMP_RcompDrvDown_MSK                  (0x00FC0000)
+  #define DDRCMDSCH0_CR_DDRCRCMDCOMP_RcompDrvDown_MAX                  (0x0000003F)
+  #define DDRCMDSCH0_CR_DDRCRCMDCOMP_RcompDrvDown_DEF                  (0x00000000)
+  #define DDRCMDSCH0_CR_DDRCRCMDCOMP_LsComp_OFF                        (24)
+  #define DDRCMDSCH0_CR_DDRCRCMDCOMP_LsComp_WID                        ( 3)
+  #define DDRCMDSCH0_CR_DDRCRCMDCOMP_LsComp_MSK                        (0x07000000)
+  #define DDRCMDSCH0_CR_DDRCRCMDCOMP_LsComp_MAX                        (0x00000007)
+  #define DDRCMDSCH0_CR_DDRCRCMDCOMP_LsComp_DEF                        (0x00000004)
+  #define DDRCMDSCH0_CR_DDRCRCMDCOMP_Spare_OFF                         (27)
+  #define DDRCMDSCH0_CR_DDRCRCMDCOMP_Spare_WID                         ( 5)
+  #define DDRCMDSCH0_CR_DDRCRCMDCOMP_Spare_MSK                         (0xF8000000)
+  #define DDRCMDSCH0_CR_DDRCRCMDCOMP_Spare_MAX                         (0x0000001F)
+  #define DDRCMDSCH0_CR_DDRCRCMDCOMP_Spare_DEF                         (0x00000000)
+
+#define DDRCMDSCH0_CR_DDRCRCMDCOMPOFFSET_REG                         (0x00001A04)
+  #define DDRCMDSCH0_CR_DDRCRCMDCOMPOFFSET_ScompOffset_OFF             ( 0)
+  #define DDRCMDSCH0_CR_DDRCRCMDCOMPOFFSET_ScompOffset_WID             ( 5)
+  #define DDRCMDSCH0_CR_DDRCRCMDCOMPOFFSET_ScompOffset_MSK             (0x0000001F)
+  #define DDRCMDSCH0_CR_DDRCRCMDCOMPOFFSET_ScompOffset_MAX             (0x0000001F)
+  #define DDRCMDSCH0_CR_DDRCRCMDCOMPOFFSET_ScompOffset_DEF             (0x00000000)
+  #define DDRCMDSCH0_CR_DDRCRCMDCOMPOFFSET_TcoCompOffset_OFF           ( 5)
+  #define DDRCMDSCH0_CR_DDRCRCMDCOMPOFFSET_TcoCompOffset_WID           ( 4)
+  #define DDRCMDSCH0_CR_DDRCRCMDCOMPOFFSET_TcoCompOffset_MSK           (0x000001E0)
+  #define DDRCMDSCH0_CR_DDRCRCMDCOMPOFFSET_TcoCompOffset_MAX           (0x0000000F)
+  #define DDRCMDSCH0_CR_DDRCRCMDCOMPOFFSET_TcoCompOffset_DEF           (0x00000000)
+  #define DDRCMDSCH0_CR_DDRCRCMDCOMPOFFSET_RcompDrvUpOffset_OFF        ( 9)
+  #define DDRCMDSCH0_CR_DDRCRCMDCOMPOFFSET_RcompDrvUpOffset_WID        ( 4)
+  #define DDRCMDSCH0_CR_DDRCRCMDCOMPOFFSET_RcompDrvUpOffset_MSK        (0x00001E00)
+  #define DDRCMDSCH0_CR_DDRCRCMDCOMPOFFSET_RcompDrvUpOffset_MAX        (0x0000000F)
+  #define DDRCMDSCH0_CR_DDRCRCMDCOMPOFFSET_RcompDrvUpOffset_DEF        (0x00000000)
+  #define DDRCMDSCH0_CR_DDRCRCMDCOMPOFFSET_RcompDrvDownOffset_OFF      (13)
+  #define DDRCMDSCH0_CR_DDRCRCMDCOMPOFFSET_RcompDrvDownOffset_WID      ( 4)
+  #define DDRCMDSCH0_CR_DDRCRCMDCOMPOFFSET_RcompDrvDownOffset_MSK      (0x0001E000)
+  #define DDRCMDSCH0_CR_DDRCRCMDCOMPOFFSET_RcompDrvDownOffset_MAX      (0x0000000F)
+  #define DDRCMDSCH0_CR_DDRCRCMDCOMPOFFSET_RcompDrvDownOffset_DEF      (0x00000000)
+  #define DDRCMDSCH0_CR_DDRCRCMDCOMPOFFSET_Spare_OFF                   (17)
+  #define DDRCMDSCH0_CR_DDRCRCMDCOMPOFFSET_Spare_WID                   (15)
+  #define DDRCMDSCH0_CR_DDRCRCMDCOMPOFFSET_Spare_MSK                   (0xFFFE0000)
+  #define DDRCMDSCH0_CR_DDRCRCMDCOMPOFFSET_Spare_MAX                   (0x00007FFF)
+  #define DDRCMDSCH0_CR_DDRCRCMDCOMPOFFSET_Spare_DEF                   (0x00000000)
+
+#define DDRCMDSCH0_CR_DDRCRCMDPICODING_REG                           (0x00001A08)
+  #define DDRCMDSCH0_CR_DDRCRCMDPICODING_CmdPi0Code_OFF                ( 0)
+  #define DDRCMDSCH0_CR_DDRCRCMDPICODING_CmdPi0Code_WID                ( 7)
+  #define DDRCMDSCH0_CR_DDRCRCMDPICODING_CmdPi0Code_MSK                (0x0000007F)
+  #define DDRCMDSCH0_CR_DDRCRCMDPICODING_CmdPi0Code_MAX                (0x0000007F)
+  #define DDRCMDSCH0_CR_DDRCRCMDPICODING_CmdPi0Code_DEF                (0x00000000)
+  #define DDRCMDSCH0_CR_DDRCRCMDPICODING_CmdPi1Code_OFF                ( 7)
+  #define DDRCMDSCH0_CR_DDRCRCMDPICODING_CmdPi1Code_WID                ( 7)
+  #define DDRCMDSCH0_CR_DDRCRCMDPICODING_CmdPi1Code_MSK                (0x00003F80)
+  #define DDRCMDSCH0_CR_DDRCRCMDPICODING_CmdPi1Code_MAX                (0x0000007F)
+  #define DDRCMDSCH0_CR_DDRCRCMDPICODING_CmdPi1Code_DEF                (0x00000000)
+  #define DDRCMDSCH0_CR_DDRCRCMDPICODING_Spare_OFF                     (14)
+  #define DDRCMDSCH0_CR_DDRCRCMDPICODING_Spare_WID                     (18)
+  #define DDRCMDSCH0_CR_DDRCRCMDPICODING_Spare_MSK                     (0xFFFFC000)
+  #define DDRCMDSCH0_CR_DDRCRCMDPICODING_Spare_MAX                     (0x0003FFFF)
+  #define DDRCMDSCH0_CR_DDRCRCMDPICODING_Spare_DEF                     (0x00000000)
+
+#define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_REG                           (0x00001A0C)
+  #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_RefPi_OFF                     ( 0)
+  #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_RefPi_WID                     ( 4)
+  #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_RefPi_MSK                     (0x0000000F)
+  #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_RefPi_MAX                     (0x0000000F)
+  #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_RefPi_DEF                     (0x00000000)
+  #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_DllMask_OFF                   ( 4)
+  #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_DllMask_WID                   ( 2)
+  #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_DllMask_MSK                   (0x00000030)
+  #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_DllMask_MAX                   (0x00000003)
+  #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_DllMask_DEF                   (0x00000000)
+  #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_DllRsvd1_OFF                  ( 6)
+  #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_DllRsvd1_WID                  ( 1)
+  #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_DllRsvd1_MSK                  (0x00000040)
+  #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_DllRsvd1_MAX                  (0x00000001)
+  #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_DllRsvd1_DEF                  (0x00000000)
+  #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_TxOn_OFF                      ( 7)
+  #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_TxOn_WID                      ( 1)
+  #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_TxOn_MSK                      (0x00000080)
+  #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_TxOn_MAX                      (0x00000001)
+  #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_TxOn_DEF                      (0x00000000)
+  #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_IntClkOn_OFF                  ( 8)
+  #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_IntClkOn_WID                  ( 1)
+  #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_IntClkOn_MSK                  (0x00000100)
+  #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_IntClkOn_MAX                  (0x00000001)
+  #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_IntClkOn_DEF                  (0x00000000)
+  #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_RepClkOn_OFF                  ( 9)
+  #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_RepClkOn_WID                  ( 1)
+  #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_RepClkOn_MSK                  (0x00000200)
+  #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_RepClkOn_MAX                  (0x00000001)
+  #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_RepClkOn_DEF                  (0x00000000)
+  #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_IOLBCtl_OFF                   (10)
+  #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_IOLBCtl_WID                   ( 2)
+  #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_IOLBCtl_MSK                   (0x00000C00)
+  #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_IOLBCtl_MAX                   (0x00000003)
+  #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_IOLBCtl_DEF                   (0x00000000)
+  #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_OdtMode_OFF                   (12)
+  #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_OdtMode_WID                   ( 1)
+  #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_OdtMode_MSK                   (0x00001000)
+  #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_OdtMode_MAX                   (0x00000001)
+  #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_OdtMode_DEF                   (0x00000000)
+  #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_CmdTxEq_OFF                   (13)
+  #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_CmdTxEq_WID                   ( 2)
+  #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_CmdTxEq_MSK                   (0x00006000)
+  #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_CmdTxEq_MAX                   (0x00000003)
+  #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_CmdTxEq_DEF                   (0x00000000)
+  #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_EarlyWeakDrive_OFF            (15)
+  #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_EarlyWeakDrive_WID            ( 2)
+  #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_EarlyWeakDrive_MSK            (0x00018000)
+  #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_EarlyWeakDrive_MAX            (0x00000003)
+  #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_EarlyWeakDrive_DEF            (0x00000000)
+  #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_Reserved_OFF                  (17)
+  #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_Reserved_WID                  ( 4)
+  #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_Reserved_MSK                  (0x001E0000)
+  #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_Reserved_MAX                  (0x0000000F)
+  #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_Reserved_DEF                  (0x00000000)
+  #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_RxVref_OFF                    (21)
+  #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_RxVref_WID                    ( 6)
+  #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_RxVref_MSK                    (0x07E00000)
+  #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_RxVref_MAX                    (0x0000003F)
+  #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_RxVref_DEF                    (0x00000000)
+  #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_VccddqHi_OFF                  (27)
+  #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_VccddqHi_WID                  ( 1)
+  #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_VccddqHi_MSK                  (0x08000000)
+  #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_VccddqHi_MAX                  (0x00000001)
+  #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_VccddqHi_DEF                  (0x00000000)
+  #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_DllWeakLock_OFF               (28)
+  #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_DllWeakLock_WID               ( 1)
+  #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_DllWeakLock_MSK               (0x10000000)
+  #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_DllWeakLock_MAX               (0x00000001)
+  #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_DllWeakLock_DEF               (0x00000000)
+  #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_LPDDR_Mode_OFF                (29)
+  #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_LPDDR_Mode_WID                ( 1)
+  #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_LPDDR_Mode_MSK                (0x20000000)
+  #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_LPDDR_Mode_MAX                (0x00000001)
+  #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_LPDDR_Mode_DEF                (0x00000000)
+  #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_LPDdrCAA_Dis_OFF              (30)
+  #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_LPDdrCAA_Dis_WID              ( 1)
+  #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_LPDdrCAA_Dis_MSK              (0x40000000)
+  #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_LPDdrCAA_Dis_MAX              (0x00000001)
+  #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_LPDdrCAA_Dis_DEF              (0x00000000)
+  #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_LPDdrCAB_Dis_OFF              (31)
+  #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_LPDdrCAB_Dis_WID              ( 1)
+  #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_LPDdrCAB_Dis_MSK              (0x80000000)
+  #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_LPDdrCAB_Dis_MAX              (0x00000001)
+  #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_LPDdrCAB_Dis_DEF              (0x00000000)
+
+#define DDRCMDSCH0_CR_DLLPITESTANDADC_REG                            (0x00001A24)
+  #define DDRCMDSCH0_CR_DLLPITESTANDADC_RunTest_OFF                    ( 0)
+  #define DDRCMDSCH0_CR_DLLPITESTANDADC_RunTest_WID                    ( 1)
+  #define DDRCMDSCH0_CR_DLLPITESTANDADC_RunTest_MSK                    (0x00000001)
+  #define DDRCMDSCH0_CR_DLLPITESTANDADC_RunTest_MAX                    (0x00000001)
+  #define DDRCMDSCH0_CR_DLLPITESTANDADC_RunTest_DEF                    (0x00000000)
+  #define DDRCMDSCH0_CR_DLLPITESTANDADC_Load_OFF                       ( 1)
+  #define DDRCMDSCH0_CR_DLLPITESTANDADC_Load_WID                       ( 1)
+  #define DDRCMDSCH0_CR_DLLPITESTANDADC_Load_MSK                       (0x00000002)
+  #define DDRCMDSCH0_CR_DLLPITESTANDADC_Load_MAX                       (0x00000001)
+  #define DDRCMDSCH0_CR_DLLPITESTANDADC_Load_DEF                       (0x00000000)
+  #define DDRCMDSCH0_CR_DLLPITESTANDADC_ModeHVM_OFF                    ( 2)
+  #define DDRCMDSCH0_CR_DLLPITESTANDADC_ModeHVM_WID                    ( 1)
+  #define DDRCMDSCH0_CR_DLLPITESTANDADC_ModeHVM_MSK                    (0x00000004)
+  #define DDRCMDSCH0_CR_DLLPITESTANDADC_ModeHVM_MAX                    (0x00000001)
+  #define DDRCMDSCH0_CR_DLLPITESTANDADC_ModeHVM_DEF                    (0x00000000)
+  #define DDRCMDSCH0_CR_DLLPITESTANDADC_ModeDV_OFF                     ( 3)
+  #define DDRCMDSCH0_CR_DLLPITESTANDADC_ModeDV_WID                     ( 1)
+  #define DDRCMDSCH0_CR_DLLPITESTANDADC_ModeDV_MSK                     (0x00000008)
+  #define DDRCMDSCH0_CR_DLLPITESTANDADC_ModeDV_MAX                     (0x00000001)
+  #define DDRCMDSCH0_CR_DLLPITESTANDADC_ModeDV_DEF                     (0x00000000)
+  #define DDRCMDSCH0_CR_DLLPITESTANDADC_ModeADC_OFF                    ( 4)
+  #define DDRCMDSCH0_CR_DLLPITESTANDADC_ModeADC_WID                    ( 1)
+  #define DDRCMDSCH0_CR_DLLPITESTANDADC_ModeADC_MSK                    (0x00000010)
+  #define DDRCMDSCH0_CR_DLLPITESTANDADC_ModeADC_MAX                    (0x00000001)
+  #define DDRCMDSCH0_CR_DLLPITESTANDADC_ModeADC_DEF                    (0x00000000)
+  #define DDRCMDSCH0_CR_DLLPITESTANDADC_LoadCount_OFF                  ( 5)
+  #define DDRCMDSCH0_CR_DLLPITESTANDADC_LoadCount_WID                  (10)
+  #define DDRCMDSCH0_CR_DLLPITESTANDADC_LoadCount_MSK                  (0x00007FE0)
+  #define DDRCMDSCH0_CR_DLLPITESTANDADC_LoadCount_MAX                  (0x000003FF)
+  #define DDRCMDSCH0_CR_DLLPITESTANDADC_CountStatus_OFF                (15)
+  #define DDRCMDSCH0_CR_DLLPITESTANDADC_CountStatus_WID                (10)
+  #define DDRCMDSCH0_CR_DLLPITESTANDADC_CountStatus_MSK                (0x01FF8000)
+  #define DDRCMDSCH0_CR_DLLPITESTANDADC_CountStatus_MAX                (0x000003FF)
+  #define DDRCMDSCH0_CR_DLLPITESTANDADC_CountStatus_DEF                (0x00000000)
+  #define DDRCMDSCH0_CR_DLLPITESTANDADC_Spare_OFF                      (25)
+  #define DDRCMDSCH0_CR_DLLPITESTANDADC_Spare_WID                      ( 7)
+  #define DDRCMDSCH0_CR_DLLPITESTANDADC_Spare_MSK                      (0xFE000000)
+  #define DDRCMDSCH0_CR_DLLPITESTANDADC_Spare_MAX                      (0x0000007F)
+
+#define DDRCMDSCH1_CR_DDRCRCMDCOMP_REG                               (0x00001B00)
+  #define DDRCMDSCH1_CR_DDRCRCMDCOMP_Scomp_OFF                         ( 0)
+  #define DDRCMDSCH1_CR_DDRCRCMDCOMP_Scomp_WID                         ( 6)
+  #define DDRCMDSCH1_CR_DDRCRCMDCOMP_Scomp_MSK                         (0x0000003F)
+  #define DDRCMDSCH1_CR_DDRCRCMDCOMP_Scomp_MAX                         (0x0000003F)
+  #define DDRCMDSCH1_CR_DDRCRCMDCOMP_Scomp_DEF                         (0x00000000)
+  #define DDRCMDSCH1_CR_DDRCRCMDCOMP_TcoComp_OFF                       ( 6)
+  #define DDRCMDSCH1_CR_DDRCRCMDCOMP_TcoComp_WID                       ( 6)
+  #define DDRCMDSCH1_CR_DDRCRCMDCOMP_TcoComp_MSK                       (0x00000FC0)
+  #define DDRCMDSCH1_CR_DDRCRCMDCOMP_TcoComp_MAX                       (0x0000003F)
+  #define DDRCMDSCH1_CR_DDRCRCMDCOMP_TcoComp_DEF                       (0x00000000)
+  #define DDRCMDSCH1_CR_DDRCRCMDCOMP_RcompDrvUp_OFF                    (12)
+  #define DDRCMDSCH1_CR_DDRCRCMDCOMP_RcompDrvUp_WID                    ( 6)
+  #define DDRCMDSCH1_CR_DDRCRCMDCOMP_RcompDrvUp_MSK                    (0x0003F000)
+  #define DDRCMDSCH1_CR_DDRCRCMDCOMP_RcompDrvUp_MAX                    (0x0000003F)
+  #define DDRCMDSCH1_CR_DDRCRCMDCOMP_RcompDrvUp_DEF                    (0x00000000)
+  #define DDRCMDSCH1_CR_DDRCRCMDCOMP_RcompDrvDown_OFF                  (18)
+  #define DDRCMDSCH1_CR_DDRCRCMDCOMP_RcompDrvDown_WID                  ( 6)
+  #define DDRCMDSCH1_CR_DDRCRCMDCOMP_RcompDrvDown_MSK                  (0x00FC0000)
+  #define DDRCMDSCH1_CR_DDRCRCMDCOMP_RcompDrvDown_MAX                  (0x0000003F)
+  #define DDRCMDSCH1_CR_DDRCRCMDCOMP_RcompDrvDown_DEF                  (0x00000000)
+  #define DDRCMDSCH1_CR_DDRCRCMDCOMP_LsComp_OFF                        (24)
+  #define DDRCMDSCH1_CR_DDRCRCMDCOMP_LsComp_WID                        ( 3)
+  #define DDRCMDSCH1_CR_DDRCRCMDCOMP_LsComp_MSK                        (0x07000000)
+  #define DDRCMDSCH1_CR_DDRCRCMDCOMP_LsComp_MAX                        (0x00000007)
+  #define DDRCMDSCH1_CR_DDRCRCMDCOMP_LsComp_DEF                        (0x00000004)
+  #define DDRCMDSCH1_CR_DDRCRCMDCOMP_Spare_OFF                         (27)
+  #define DDRCMDSCH1_CR_DDRCRCMDCOMP_Spare_WID                         ( 5)
+  #define DDRCMDSCH1_CR_DDRCRCMDCOMP_Spare_MSK                         (0xF8000000)
+  #define DDRCMDSCH1_CR_DDRCRCMDCOMP_Spare_MAX                         (0x0000001F)
+  #define DDRCMDSCH1_CR_DDRCRCMDCOMP_Spare_DEF                         (0x00000000)
+
+#define DDRCMDSCH1_CR_DDRCRCMDCOMPOFFSET_REG                         (0x00001B04)
+  #define DDRCMDSCH1_CR_DDRCRCMDCOMPOFFSET_ScompOffset_OFF             ( 0)
+  #define DDRCMDSCH1_CR_DDRCRCMDCOMPOFFSET_ScompOffset_WID             ( 5)
+  #define DDRCMDSCH1_CR_DDRCRCMDCOMPOFFSET_ScompOffset_MSK             (0x0000001F)
+  #define DDRCMDSCH1_CR_DDRCRCMDCOMPOFFSET_ScompOffset_MAX             (0x0000001F)
+  #define DDRCMDSCH1_CR_DDRCRCMDCOMPOFFSET_ScompOffset_DEF             (0x00000000)
+  #define DDRCMDSCH1_CR_DDRCRCMDCOMPOFFSET_TcoCompOffset_OFF           ( 5)
+  #define DDRCMDSCH1_CR_DDRCRCMDCOMPOFFSET_TcoCompOffset_WID           ( 4)
+  #define DDRCMDSCH1_CR_DDRCRCMDCOMPOFFSET_TcoCompOffset_MSK           (0x000001E0)
+  #define DDRCMDSCH1_CR_DDRCRCMDCOMPOFFSET_TcoCompOffset_MAX           (0x0000000F)
+  #define DDRCMDSCH1_CR_DDRCRCMDCOMPOFFSET_TcoCompOffset_DEF           (0x00000000)
+  #define DDRCMDSCH1_CR_DDRCRCMDCOMPOFFSET_RcompDrvUpOffset_OFF        ( 9)
+  #define DDRCMDSCH1_CR_DDRCRCMDCOMPOFFSET_RcompDrvUpOffset_WID        ( 4)
+  #define DDRCMDSCH1_CR_DDRCRCMDCOMPOFFSET_RcompDrvUpOffset_MSK        (0x00001E00)
+  #define DDRCMDSCH1_CR_DDRCRCMDCOMPOFFSET_RcompDrvUpOffset_MAX        (0x0000000F)
+  #define DDRCMDSCH1_CR_DDRCRCMDCOMPOFFSET_RcompDrvUpOffset_DEF        (0x00000000)
+  #define DDRCMDSCH1_CR_DDRCRCMDCOMPOFFSET_RcompDrvDownOffset_OFF      (13)
+  #define DDRCMDSCH1_CR_DDRCRCMDCOMPOFFSET_RcompDrvDownOffset_WID      ( 4)
+  #define DDRCMDSCH1_CR_DDRCRCMDCOMPOFFSET_RcompDrvDownOffset_MSK      (0x0001E000)
+  #define DDRCMDSCH1_CR_DDRCRCMDCOMPOFFSET_RcompDrvDownOffset_MAX      (0x0000000F)
+  #define DDRCMDSCH1_CR_DDRCRCMDCOMPOFFSET_RcompDrvDownOffset_DEF      (0x00000000)
+  #define DDRCMDSCH1_CR_DDRCRCMDCOMPOFFSET_Spare_OFF                   (17)
+  #define DDRCMDSCH1_CR_DDRCRCMDCOMPOFFSET_Spare_WID                   (15)
+  #define DDRCMDSCH1_CR_DDRCRCMDCOMPOFFSET_Spare_MSK                   (0xFFFE0000)
+  #define DDRCMDSCH1_CR_DDRCRCMDCOMPOFFSET_Spare_MAX                   (0x00007FFF)
+  #define DDRCMDSCH1_CR_DDRCRCMDCOMPOFFSET_Spare_DEF                   (0x00000000)
+
+#define DDRCMDSCH1_CR_DDRCRCMDPICODING_REG                           (0x00001B08)
+  #define DDRCMDSCH1_CR_DDRCRCMDPICODING_CmdPi0Code_OFF                ( 0)
+  #define DDRCMDSCH1_CR_DDRCRCMDPICODING_CmdPi0Code_WID                ( 7)
+  #define DDRCMDSCH1_CR_DDRCRCMDPICODING_CmdPi0Code_MSK                (0x0000007F)
+  #define DDRCMDSCH1_CR_DDRCRCMDPICODING_CmdPi0Code_MAX                (0x0000007F)
+  #define DDRCMDSCH1_CR_DDRCRCMDPICODING_CmdPi0Code_DEF                (0x00000000)
+  #define DDRCMDSCH1_CR_DDRCRCMDPICODING_CmdPi1Code_OFF                ( 7)
+  #define DDRCMDSCH1_CR_DDRCRCMDPICODING_CmdPi1Code_WID                ( 7)
+  #define DDRCMDSCH1_CR_DDRCRCMDPICODING_CmdPi1Code_MSK                (0x00003F80)
+  #define DDRCMDSCH1_CR_DDRCRCMDPICODING_CmdPi1Code_MAX                (0x0000007F)
+  #define DDRCMDSCH1_CR_DDRCRCMDPICODING_CmdPi1Code_DEF                (0x00000000)
+  #define DDRCMDSCH1_CR_DDRCRCMDPICODING_Spare_OFF                     (14)
+  #define DDRCMDSCH1_CR_DDRCRCMDPICODING_Spare_WID                     (18)
+  #define DDRCMDSCH1_CR_DDRCRCMDPICODING_Spare_MSK                     (0xFFFFC000)
+  #define DDRCMDSCH1_CR_DDRCRCMDPICODING_Spare_MAX                     (0x0003FFFF)
+  #define DDRCMDSCH1_CR_DDRCRCMDPICODING_Spare_DEF                     (0x00000000)
+
+#define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_REG                           (0x00001B0C)
+  #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_RefPi_OFF                     ( 0)
+  #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_RefPi_WID                     ( 4)
+  #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_RefPi_MSK                     (0x0000000F)
+  #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_RefPi_MAX                     (0x0000000F)
+  #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_RefPi_DEF                     (0x00000000)
+  #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_DllMask_OFF                   ( 4)
+  #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_DllMask_WID                   ( 2)
+  #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_DllMask_MSK                   (0x00000030)
+  #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_DllMask_MAX                   (0x00000003)
+  #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_DllMask_DEF                   (0x00000000)
+  #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_DllRsvd1_OFF                  ( 6)
+  #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_DllRsvd1_WID                  ( 1)
+  #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_DllRsvd1_MSK                  (0x00000040)
+  #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_DllRsvd1_MAX                  (0x00000001)
+  #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_DllRsvd1_DEF                  (0x00000000)
+  #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_TxOn_OFF                      ( 7)
+  #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_TxOn_WID                      ( 1)
+  #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_TxOn_MSK                      (0x00000080)
+  #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_TxOn_MAX                      (0x00000001)
+  #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_TxOn_DEF                      (0x00000000)
+  #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_IntClkOn_OFF                  ( 8)
+  #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_IntClkOn_WID                  ( 1)
+  #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_IntClkOn_MSK                  (0x00000100)
+  #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_IntClkOn_MAX                  (0x00000001)
+  #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_IntClkOn_DEF                  (0x00000000)
+  #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_RepClkOn_OFF                  ( 9)
+  #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_RepClkOn_WID                  ( 1)
+  #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_RepClkOn_MSK                  (0x00000200)
+  #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_RepClkOn_MAX                  (0x00000001)
+  #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_RepClkOn_DEF                  (0x00000000)
+  #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_IOLBCtl_OFF                   (10)
+  #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_IOLBCtl_WID                   ( 2)
+  #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_IOLBCtl_MSK                   (0x00000C00)
+  #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_IOLBCtl_MAX                   (0x00000003)
+  #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_IOLBCtl_DEF                   (0x00000000)
+  #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_OdtMode_OFF                   (12)
+  #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_OdtMode_WID                   ( 1)
+  #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_OdtMode_MSK                   (0x00001000)
+  #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_OdtMode_MAX                   (0x00000001)
+  #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_OdtMode_DEF                   (0x00000000)
+  #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_CmdTxEq_OFF                   (13)
+  #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_CmdTxEq_WID                   ( 2)
+  #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_CmdTxEq_MSK                   (0x00006000)
+  #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_CmdTxEq_MAX                   (0x00000003)
+  #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_CmdTxEq_DEF                   (0x00000000)
+  #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_EarlyWeakDrive_OFF            (15)
+  #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_EarlyWeakDrive_WID            ( 2)
+  #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_EarlyWeakDrive_MSK            (0x00018000)
+  #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_EarlyWeakDrive_MAX            (0x00000003)
+  #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_EarlyWeakDrive_DEF            (0x00000000)
+  #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_Reserved_OFF                  (17)
+  #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_Reserved_WID                  ( 4)
+  #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_Reserved_MSK                  (0x001E0000)
+  #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_Reserved_MAX                  (0x0000000F)
+  #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_Reserved_DEF                  (0x00000000)
+  #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_RxVref_OFF                    (21)
+  #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_RxVref_WID                    ( 6)
+  #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_RxVref_MSK                    (0x07E00000)
+  #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_RxVref_MAX                    (0x0000003F)
+  #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_RxVref_DEF                    (0x00000000)
+  #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_VccddqHi_OFF                  (27)
+  #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_VccddqHi_WID                  ( 1)
+  #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_VccddqHi_MSK                  (0x08000000)
+  #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_VccddqHi_MAX                  (0x00000001)
+  #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_VccddqHi_DEF                  (0x00000000)
+  #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_DllWeakLock_OFF               (28)
+  #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_DllWeakLock_WID               ( 1)
+  #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_DllWeakLock_MSK               (0x10000000)
+  #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_DllWeakLock_MAX               (0x00000001)
+  #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_DllWeakLock_DEF               (0x00000000)
+  #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_LPDDR_Mode_OFF                (29)
+  #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_LPDDR_Mode_WID                ( 1)
+  #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_LPDDR_Mode_MSK                (0x20000000)
+  #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_LPDDR_Mode_MAX                (0x00000001)
+  #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_LPDDR_Mode_DEF                (0x00000000)
+  #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_LPDdrCAA_Dis_OFF              (30)
+  #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_LPDdrCAA_Dis_WID              ( 1)
+  #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_LPDdrCAA_Dis_MSK              (0x40000000)
+  #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_LPDdrCAA_Dis_MAX              (0x00000001)
+  #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_LPDdrCAA_Dis_DEF              (0x00000000)
+  #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_LPDdrCAB_Dis_OFF              (31)
+  #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_LPDdrCAB_Dis_WID              ( 1)
+  #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_LPDdrCAB_Dis_MSK              (0x80000000)
+  #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_LPDdrCAB_Dis_MAX              (0x00000001)
+  #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_LPDdrCAB_Dis_DEF              (0x00000000)
+
+#define DDRCMDSCH1_CR_DLLPITESTANDADC_REG                            (0x00001B24)
+  #define DDRCMDSCH1_CR_DLLPITESTANDADC_RunTest_OFF                    ( 0)
+  #define DDRCMDSCH1_CR_DLLPITESTANDADC_RunTest_WID                    ( 1)
+  #define DDRCMDSCH1_CR_DLLPITESTANDADC_RunTest_MSK                    (0x00000001)
+  #define DDRCMDSCH1_CR_DLLPITESTANDADC_RunTest_MAX                    (0x00000001)
+  #define DDRCMDSCH1_CR_DLLPITESTANDADC_RunTest_DEF                    (0x00000000)
+  #define DDRCMDSCH1_CR_DLLPITESTANDADC_Load_OFF                       ( 1)
+  #define DDRCMDSCH1_CR_DLLPITESTANDADC_Load_WID                       ( 1)
+  #define DDRCMDSCH1_CR_DLLPITESTANDADC_Load_MSK                       (0x00000002)
+  #define DDRCMDSCH1_CR_DLLPITESTANDADC_Load_MAX                       (0x00000001)
+  #define DDRCMDSCH1_CR_DLLPITESTANDADC_Load_DEF                       (0x00000000)
+  #define DDRCMDSCH1_CR_DLLPITESTANDADC_ModeHVM_OFF                    ( 2)
+  #define DDRCMDSCH1_CR_DLLPITESTANDADC_ModeHVM_WID                    ( 1)
+  #define DDRCMDSCH1_CR_DLLPITESTANDADC_ModeHVM_MSK                    (0x00000004)
+  #define DDRCMDSCH1_CR_DLLPITESTANDADC_ModeHVM_MAX                    (0x00000001)
+  #define DDRCMDSCH1_CR_DLLPITESTANDADC_ModeHVM_DEF                    (0x00000000)
+  #define DDRCMDSCH1_CR_DLLPITESTANDADC_ModeDV_OFF                     ( 3)
+  #define DDRCMDSCH1_CR_DLLPITESTANDADC_ModeDV_WID                     ( 1)
+  #define DDRCMDSCH1_CR_DLLPITESTANDADC_ModeDV_MSK                     (0x00000008)
+  #define DDRCMDSCH1_CR_DLLPITESTANDADC_ModeDV_MAX                     (0x00000001)
+  #define DDRCMDSCH1_CR_DLLPITESTANDADC_ModeDV_DEF                     (0x00000000)
+  #define DDRCMDSCH1_CR_DLLPITESTANDADC_ModeADC_OFF                    ( 4)
+  #define DDRCMDSCH1_CR_DLLPITESTANDADC_ModeADC_WID                    ( 1)
+  #define DDRCMDSCH1_CR_DLLPITESTANDADC_ModeADC_MSK                    (0x00000010)
+  #define DDRCMDSCH1_CR_DLLPITESTANDADC_ModeADC_MAX                    (0x00000001)
+  #define DDRCMDSCH1_CR_DLLPITESTANDADC_ModeADC_DEF                    (0x00000000)
+  #define DDRCMDSCH1_CR_DLLPITESTANDADC_LoadCount_OFF                  ( 5)
+  #define DDRCMDSCH1_CR_DLLPITESTANDADC_LoadCount_WID                  (10)
+  #define DDRCMDSCH1_CR_DLLPITESTANDADC_LoadCount_MSK                  (0x00007FE0)
+  #define DDRCMDSCH1_CR_DLLPITESTANDADC_LoadCount_MAX                  (0x000003FF)
+  #define DDRCMDSCH1_CR_DLLPITESTANDADC_CountStatus_OFF                (15)
+  #define DDRCMDSCH1_CR_DLLPITESTANDADC_CountStatus_WID                (10)
+  #define DDRCMDSCH1_CR_DLLPITESTANDADC_CountStatus_MSK                (0x01FF8000)
+  #define DDRCMDSCH1_CR_DLLPITESTANDADC_CountStatus_MAX                (0x000003FF)
+  #define DDRCMDSCH1_CR_DLLPITESTANDADC_CountStatus_DEF                (0x00000000)
+  #define DDRCMDSCH1_CR_DLLPITESTANDADC_Spare_OFF                      (25)
+  #define DDRCMDSCH1_CR_DLLPITESTANDADC_Spare_WID                      ( 7)
+  #define DDRCMDSCH1_CR_DLLPITESTANDADC_Spare_MSK                      (0xFE000000)
+  #define DDRCMDSCH1_CR_DLLPITESTANDADC_Spare_MAX                      (0x0000007F)
+
+#define DDRCMDCH0_CR_DDRCRCMDCOMP_REG                                (0x00003200)
+  #define DDRCMDCH0_CR_DDRCRCMDCOMP_Scomp_OFF                          ( 0)
+  #define DDRCMDCH0_CR_DDRCRCMDCOMP_Scomp_WID                          ( 6)
+  #define DDRCMDCH0_CR_DDRCRCMDCOMP_Scomp_MSK                          (0x0000003F)
+  #define DDRCMDCH0_CR_DDRCRCMDCOMP_Scomp_MAX                          (0x0000003F)
+  #define DDRCMDCH0_CR_DDRCRCMDCOMP_Scomp_DEF                          (0x00000000)
+  #define DDRCMDCH0_CR_DDRCRCMDCOMP_TcoComp_OFF                        ( 6)
+  #define DDRCMDCH0_CR_DDRCRCMDCOMP_TcoComp_WID                        ( 6)
+  #define DDRCMDCH0_CR_DDRCRCMDCOMP_TcoComp_MSK                        (0x00000FC0)
+  #define DDRCMDCH0_CR_DDRCRCMDCOMP_TcoComp_MAX                        (0x0000003F)
+  #define DDRCMDCH0_CR_DDRCRCMDCOMP_TcoComp_DEF                        (0x00000000)
+  #define DDRCMDCH0_CR_DDRCRCMDCOMP_RcompDrvUp_OFF                     (12)
+  #define DDRCMDCH0_CR_DDRCRCMDCOMP_RcompDrvUp_WID                     ( 6)
+  #define DDRCMDCH0_CR_DDRCRCMDCOMP_RcompDrvUp_MSK                     (0x0003F000)
+  #define DDRCMDCH0_CR_DDRCRCMDCOMP_RcompDrvUp_MAX                     (0x0000003F)
+  #define DDRCMDCH0_CR_DDRCRCMDCOMP_RcompDrvUp_DEF                     (0x00000000)
+  #define DDRCMDCH0_CR_DDRCRCMDCOMP_RcompDrvDown_OFF                   (18)
+  #define DDRCMDCH0_CR_DDRCRCMDCOMP_RcompDrvDown_WID                   ( 6)
+  #define DDRCMDCH0_CR_DDRCRCMDCOMP_RcompDrvDown_MSK                   (0x00FC0000)
+  #define DDRCMDCH0_CR_DDRCRCMDCOMP_RcompDrvDown_MAX                   (0x0000003F)
+  #define DDRCMDCH0_CR_DDRCRCMDCOMP_RcompDrvDown_DEF                   (0x00000000)
+  #define DDRCMDCH0_CR_DDRCRCMDCOMP_LsComp_OFF                         (24)
+  #define DDRCMDCH0_CR_DDRCRCMDCOMP_LsComp_WID                         ( 3)
+  #define DDRCMDCH0_CR_DDRCRCMDCOMP_LsComp_MSK                         (0x07000000)
+  #define DDRCMDCH0_CR_DDRCRCMDCOMP_LsComp_MAX                         (0x00000007)
+  #define DDRCMDCH0_CR_DDRCRCMDCOMP_LsComp_DEF                         (0x00000004)
+  #define DDRCMDCH0_CR_DDRCRCMDCOMP_Spare_OFF                          (27)
+  #define DDRCMDCH0_CR_DDRCRCMDCOMP_Spare_WID                          ( 5)
+  #define DDRCMDCH0_CR_DDRCRCMDCOMP_Spare_MSK                          (0xF8000000)
+  #define DDRCMDCH0_CR_DDRCRCMDCOMP_Spare_MAX                          (0x0000001F)
+  #define DDRCMDCH0_CR_DDRCRCMDCOMP_Spare_DEF                          (0x00000000)
+
+#define DDRCMDCH0_CR_DDRCRCMDCOMPOFFSET_REG                          (0x00003204)
+  #define DDRCMDCH0_CR_DDRCRCMDCOMPOFFSET_ScompOffset_OFF              ( 0)
+  #define DDRCMDCH0_CR_DDRCRCMDCOMPOFFSET_ScompOffset_WID              ( 5)
+  #define DDRCMDCH0_CR_DDRCRCMDCOMPOFFSET_ScompOffset_MSK              (0x0000001F)
+  #define DDRCMDCH0_CR_DDRCRCMDCOMPOFFSET_ScompOffset_MAX              (0x0000001F)
+  #define DDRCMDCH0_CR_DDRCRCMDCOMPOFFSET_ScompOffset_DEF              (0x00000000)
+  #define DDRCMDCH0_CR_DDRCRCMDCOMPOFFSET_TcoCompOffset_OFF            ( 5)
+  #define DDRCMDCH0_CR_DDRCRCMDCOMPOFFSET_TcoCompOffset_WID            ( 4)
+  #define DDRCMDCH0_CR_DDRCRCMDCOMPOFFSET_TcoCompOffset_MSK            (0x000001E0)
+  #define DDRCMDCH0_CR_DDRCRCMDCOMPOFFSET_TcoCompOffset_MAX            (0x0000000F)
+  #define DDRCMDCH0_CR_DDRCRCMDCOMPOFFSET_TcoCompOffset_DEF            (0x00000000)
+  #define DDRCMDCH0_CR_DDRCRCMDCOMPOFFSET_RcompDrvUpOffset_OFF         ( 9)
+  #define DDRCMDCH0_CR_DDRCRCMDCOMPOFFSET_RcompDrvUpOffset_WID         ( 4)
+  #define DDRCMDCH0_CR_DDRCRCMDCOMPOFFSET_RcompDrvUpOffset_MSK         (0x00001E00)
+  #define DDRCMDCH0_CR_DDRCRCMDCOMPOFFSET_RcompDrvUpOffset_MAX         (0x0000000F)
+  #define DDRCMDCH0_CR_DDRCRCMDCOMPOFFSET_RcompDrvUpOffset_DEF         (0x00000000)
+  #define DDRCMDCH0_CR_DDRCRCMDCOMPOFFSET_RcompDrvDownOffset_OFF       (13)
+  #define DDRCMDCH0_CR_DDRCRCMDCOMPOFFSET_RcompDrvDownOffset_WID       ( 4)
+  #define DDRCMDCH0_CR_DDRCRCMDCOMPOFFSET_RcompDrvDownOffset_MSK       (0x0001E000)
+  #define DDRCMDCH0_CR_DDRCRCMDCOMPOFFSET_RcompDrvDownOffset_MAX       (0x0000000F)
+  #define DDRCMDCH0_CR_DDRCRCMDCOMPOFFSET_RcompDrvDownOffset_DEF       (0x00000000)
+  #define DDRCMDCH0_CR_DDRCRCMDCOMPOFFSET_Spare_OFF                    (17)
+  #define DDRCMDCH0_CR_DDRCRCMDCOMPOFFSET_Spare_WID                    (15)
+  #define DDRCMDCH0_CR_DDRCRCMDCOMPOFFSET_Spare_MSK                    (0xFFFE0000)
+  #define DDRCMDCH0_CR_DDRCRCMDCOMPOFFSET_Spare_MAX                    (0x00007FFF)
+  #define DDRCMDCH0_CR_DDRCRCMDCOMPOFFSET_Spare_DEF                    (0x00000000)
+
+#define DDRCMDCH0_CR_DDRCRCMDPICODING_REG                            (0x00003208)
+  #define DDRCMDCH0_CR_DDRCRCMDPICODING_CmdPi0Code_OFF                 ( 0)
+  #define DDRCMDCH0_CR_DDRCRCMDPICODING_CmdPi0Code_WID                 ( 7)
+  #define DDRCMDCH0_CR_DDRCRCMDPICODING_CmdPi0Code_MSK                 (0x0000007F)
+  #define DDRCMDCH0_CR_DDRCRCMDPICODING_CmdPi0Code_MAX                 (0x0000007F)
+  #define DDRCMDCH0_CR_DDRCRCMDPICODING_CmdPi0Code_DEF                 (0x00000000)
+  #define DDRCMDCH0_CR_DDRCRCMDPICODING_CmdPi1Code_OFF                 ( 7)
+  #define DDRCMDCH0_CR_DDRCRCMDPICODING_CmdPi1Code_WID                 ( 7)
+  #define DDRCMDCH0_CR_DDRCRCMDPICODING_CmdPi1Code_MSK                 (0x00003F80)
+  #define DDRCMDCH0_CR_DDRCRCMDPICODING_CmdPi1Code_MAX                 (0x0000007F)
+  #define DDRCMDCH0_CR_DDRCRCMDPICODING_CmdPi1Code_DEF                 (0x00000000)
+  #define DDRCMDCH0_CR_DDRCRCMDPICODING_Spare_OFF                      (14)
+  #define DDRCMDCH0_CR_DDRCRCMDPICODING_Spare_WID                      (18)
+  #define DDRCMDCH0_CR_DDRCRCMDPICODING_Spare_MSK                      (0xFFFFC000)
+  #define DDRCMDCH0_CR_DDRCRCMDPICODING_Spare_MAX                      (0x0003FFFF)
+  #define DDRCMDCH0_CR_DDRCRCMDPICODING_Spare_DEF                      (0x00000000)
+
+#define DDRCMDCH0_CR_DDRCRCMDCONTROLS_REG                            (0x0000320C)
+  #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_RefPi_OFF                      ( 0)
+  #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_RefPi_WID                      ( 4)
+  #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_RefPi_MSK                      (0x0000000F)
+  #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_RefPi_MAX                      (0x0000000F)
+  #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_RefPi_DEF                      (0x00000000)
+  #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_DllMask_OFF                    ( 4)
+  #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_DllMask_WID                    ( 2)
+  #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_DllMask_MSK                    (0x00000030)
+  #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_DllMask_MAX                    (0x00000003)
+  #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_DllMask_DEF                    (0x00000000)
+  #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_DllRsvd1_OFF                   ( 6)
+  #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_DllRsvd1_WID                   ( 1)
+  #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_DllRsvd1_MSK                   (0x00000040)
+  #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_DllRsvd1_MAX                   (0x00000001)
+  #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_DllRsvd1_DEF                   (0x00000000)
+  #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_TxOn_OFF                       ( 7)
+  #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_TxOn_WID                       ( 1)
+  #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_TxOn_MSK                       (0x00000080)
+  #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_TxOn_MAX                       (0x00000001)
+  #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_TxOn_DEF                       (0x00000000)
+  #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_IntClkOn_OFF                   ( 8)
+  #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_IntClkOn_WID                   ( 1)
+  #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_IntClkOn_MSK                   (0x00000100)
+  #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_IntClkOn_MAX                   (0x00000001)
+  #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_IntClkOn_DEF                   (0x00000000)
+  #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_RepClkOn_OFF                   ( 9)
+  #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_RepClkOn_WID                   ( 1)
+  #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_RepClkOn_MSK                   (0x00000200)
+  #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_RepClkOn_MAX                   (0x00000001)
+  #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_RepClkOn_DEF                   (0x00000000)
+  #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_IOLBCtl_OFF                    (10)
+  #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_IOLBCtl_WID                    ( 2)
+  #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_IOLBCtl_MSK                    (0x00000C00)
+  #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_IOLBCtl_MAX                    (0x00000003)
+  #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_IOLBCtl_DEF                    (0x00000000)
+  #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_OdtMode_OFF                    (12)
+  #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_OdtMode_WID                    ( 1)
+  #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_OdtMode_MSK                    (0x00001000)
+  #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_OdtMode_MAX                    (0x00000001)
+  #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_OdtMode_DEF                    (0x00000000)
+  #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_CmdTxEq_OFF                    (13)
+  #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_CmdTxEq_WID                    ( 2)
+  #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_CmdTxEq_MSK                    (0x00006000)
+  #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_CmdTxEq_MAX                    (0x00000003)
+  #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_CmdTxEq_DEF                    (0x00000000)
+  #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_EarlyWeakDrive_OFF             (15)
+  #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_EarlyWeakDrive_WID             ( 2)
+  #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_EarlyWeakDrive_MSK             (0x00018000)
+  #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_EarlyWeakDrive_MAX             (0x00000003)
+  #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_EarlyWeakDrive_DEF             (0x00000000)
+  #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_Reserved_OFF                   (17)
+  #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_Reserved_WID                   ( 4)
+  #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_Reserved_MSK                   (0x001E0000)
+  #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_Reserved_MAX                   (0x0000000F)
+  #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_Reserved_DEF                   (0x00000000)
+  #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_RxVref_OFF                     (21)
+  #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_RxVref_WID                     ( 6)
+  #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_RxVref_MSK                     (0x07E00000)
+  #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_RxVref_MAX                     (0x0000003F)
+  #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_RxVref_DEF                     (0x00000000)
+  #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_VccddqHi_OFF                   (27)
+  #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_VccddqHi_WID                   ( 1)
+  #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_VccddqHi_MSK                   (0x08000000)
+  #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_VccddqHi_MAX                   (0x00000001)
+  #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_VccddqHi_DEF                   (0x00000000)
+  #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_DllWeakLock_OFF                (28)
+  #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_DllWeakLock_WID                ( 1)
+  #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_DllWeakLock_MSK                (0x10000000)
+  #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_DllWeakLock_MAX                (0x00000001)
+  #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_DllWeakLock_DEF                (0x00000000)
+  #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_LPDDR_Mode_OFF                 (29)
+  #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_LPDDR_Mode_WID                 ( 1)
+  #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_LPDDR_Mode_MSK                 (0x20000000)
+  #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_LPDDR_Mode_MAX                 (0x00000001)
+  #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_LPDDR_Mode_DEF                 (0x00000000)
+  #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_LPDdrCAA_Dis_OFF               (30)
+  #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_LPDdrCAA_Dis_WID               ( 1)
+  #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_LPDdrCAA_Dis_MSK               (0x40000000)
+  #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_LPDdrCAA_Dis_MAX               (0x00000001)
+  #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_LPDdrCAA_Dis_DEF               (0x00000000)
+  #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_LPDdrCAB_Dis_OFF               (31)
+  #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_LPDdrCAB_Dis_WID               ( 1)
+  #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_LPDdrCAB_Dis_MSK               (0x80000000)
+  #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_LPDdrCAB_Dis_MAX               (0x00000001)
+  #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_LPDdrCAB_Dis_DEF               (0x00000000)
+
+#define DDRCMDCH0_CR_DLLPITESTANDADC_REG                             (0x00003224)
+  #define DDRCMDCH0_CR_DLLPITESTANDADC_RunTest_OFF                     ( 0)
+  #define DDRCMDCH0_CR_DLLPITESTANDADC_RunTest_WID                     ( 1)
+  #define DDRCMDCH0_CR_DLLPITESTANDADC_RunTest_MSK                     (0x00000001)
+  #define DDRCMDCH0_CR_DLLPITESTANDADC_RunTest_MAX                     (0x00000001)
+  #define DDRCMDCH0_CR_DLLPITESTANDADC_RunTest_DEF                     (0x00000000)
+  #define DDRCMDCH0_CR_DLLPITESTANDADC_Load_OFF                        ( 1)
+  #define DDRCMDCH0_CR_DLLPITESTANDADC_Load_WID                        ( 1)
+  #define DDRCMDCH0_CR_DLLPITESTANDADC_Load_MSK                        (0x00000002)
+  #define DDRCMDCH0_CR_DLLPITESTANDADC_Load_MAX                        (0x00000001)
+  #define DDRCMDCH0_CR_DLLPITESTANDADC_Load_DEF                        (0x00000000)
+  #define DDRCMDCH0_CR_DLLPITESTANDADC_ModeHVM_OFF                     ( 2)
+  #define DDRCMDCH0_CR_DLLPITESTANDADC_ModeHVM_WID                     ( 1)
+  #define DDRCMDCH0_CR_DLLPITESTANDADC_ModeHVM_MSK                     (0x00000004)
+  #define DDRCMDCH0_CR_DLLPITESTANDADC_ModeHVM_MAX                     (0x00000001)
+  #define DDRCMDCH0_CR_DLLPITESTANDADC_ModeHVM_DEF                     (0x00000000)
+  #define DDRCMDCH0_CR_DLLPITESTANDADC_ModeDV_OFF                      ( 3)
+  #define DDRCMDCH0_CR_DLLPITESTANDADC_ModeDV_WID                      ( 1)
+  #define DDRCMDCH0_CR_DLLPITESTANDADC_ModeDV_MSK                      (0x00000008)
+  #define DDRCMDCH0_CR_DLLPITESTANDADC_ModeDV_MAX                      (0x00000001)
+  #define DDRCMDCH0_CR_DLLPITESTANDADC_ModeDV_DEF                      (0x00000000)
+  #define DDRCMDCH0_CR_DLLPITESTANDADC_ModeADC_OFF                     ( 4)
+  #define DDRCMDCH0_CR_DLLPITESTANDADC_ModeADC_WID                     ( 1)
+  #define DDRCMDCH0_CR_DLLPITESTANDADC_ModeADC_MSK                     (0x00000010)
+  #define DDRCMDCH0_CR_DLLPITESTANDADC_ModeADC_MAX                     (0x00000001)
+  #define DDRCMDCH0_CR_DLLPITESTANDADC_ModeADC_DEF                     (0x00000000)
+  #define DDRCMDCH0_CR_DLLPITESTANDADC_LoadCount_OFF                   ( 5)
+  #define DDRCMDCH0_CR_DLLPITESTANDADC_LoadCount_WID                   (10)
+  #define DDRCMDCH0_CR_DLLPITESTANDADC_LoadCount_MSK                   (0x00007FE0)
+  #define DDRCMDCH0_CR_DLLPITESTANDADC_LoadCount_MAX                   (0x000003FF)
+  #define DDRCMDCH0_CR_DLLPITESTANDADC_CountStatus_OFF                 (15)
+  #define DDRCMDCH0_CR_DLLPITESTANDADC_CountStatus_WID                 (10)
+  #define DDRCMDCH0_CR_DLLPITESTANDADC_CountStatus_MSK                 (0x01FF8000)
+  #define DDRCMDCH0_CR_DLLPITESTANDADC_CountStatus_MAX                 (0x000003FF)
+  #define DDRCMDCH0_CR_DLLPITESTANDADC_CountStatus_DEF                 (0x00000000)
+  #define DDRCMDCH0_CR_DLLPITESTANDADC_Spare_OFF                       (25)
+  #define DDRCMDCH0_CR_DLLPITESTANDADC_Spare_WID                       ( 7)
+  #define DDRCMDCH0_CR_DLLPITESTANDADC_Spare_MSK                       (0xFE000000)
+  #define DDRCMDCH0_CR_DLLPITESTANDADC_Spare_MAX                       (0x0000007F)
+
+#define DDRCMDCH1_CR_DDRCRCMDCOMP_REG                                (0x00003300)
+  #define DDRCMDCH1_CR_DDRCRCMDCOMP_Scomp_OFF                          ( 0)
+  #define DDRCMDCH1_CR_DDRCRCMDCOMP_Scomp_WID                          ( 6)
+  #define DDRCMDCH1_CR_DDRCRCMDCOMP_Scomp_MSK                          (0x0000003F)
+  #define DDRCMDCH1_CR_DDRCRCMDCOMP_Scomp_MAX                          (0x0000003F)
+  #define DDRCMDCH1_CR_DDRCRCMDCOMP_Scomp_DEF                          (0x00000000)
+  #define DDRCMDCH1_CR_DDRCRCMDCOMP_TcoComp_OFF                        ( 6)
+  #define DDRCMDCH1_CR_DDRCRCMDCOMP_TcoComp_WID                        ( 6)
+  #define DDRCMDCH1_CR_DDRCRCMDCOMP_TcoComp_MSK                        (0x00000FC0)
+  #define DDRCMDCH1_CR_DDRCRCMDCOMP_TcoComp_MAX                        (0x0000003F)
+  #define DDRCMDCH1_CR_DDRCRCMDCOMP_TcoComp_DEF                        (0x00000000)
+  #define DDRCMDCH1_CR_DDRCRCMDCOMP_RcompDrvUp_OFF                     (12)
+  #define DDRCMDCH1_CR_DDRCRCMDCOMP_RcompDrvUp_WID                     ( 6)
+  #define DDRCMDCH1_CR_DDRCRCMDCOMP_RcompDrvUp_MSK                     (0x0003F000)
+  #define DDRCMDCH1_CR_DDRCRCMDCOMP_RcompDrvUp_MAX                     (0x0000003F)
+  #define DDRCMDCH1_CR_DDRCRCMDCOMP_RcompDrvUp_DEF                     (0x00000000)
+  #define DDRCMDCH1_CR_DDRCRCMDCOMP_RcompDrvDown_OFF                   (18)
+  #define DDRCMDCH1_CR_DDRCRCMDCOMP_RcompDrvDown_WID                   ( 6)
+  #define DDRCMDCH1_CR_DDRCRCMDCOMP_RcompDrvDown_MSK                   (0x00FC0000)
+  #define DDRCMDCH1_CR_DDRCRCMDCOMP_RcompDrvDown_MAX                   (0x0000003F)
+  #define DDRCMDCH1_CR_DDRCRCMDCOMP_RcompDrvDown_DEF                   (0x00000000)
+  #define DDRCMDCH1_CR_DDRCRCMDCOMP_LsComp_OFF                         (24)
+  #define DDRCMDCH1_CR_DDRCRCMDCOMP_LsComp_WID                         ( 3)
+  #define DDRCMDCH1_CR_DDRCRCMDCOMP_LsComp_MSK                         (0x07000000)
+  #define DDRCMDCH1_CR_DDRCRCMDCOMP_LsComp_MAX                         (0x00000007)
+  #define DDRCMDCH1_CR_DDRCRCMDCOMP_LsComp_DEF                         (0x00000004)
+  #define DDRCMDCH1_CR_DDRCRCMDCOMP_Spare_OFF                          (27)
+  #define DDRCMDCH1_CR_DDRCRCMDCOMP_Spare_WID                          ( 5)
+  #define DDRCMDCH1_CR_DDRCRCMDCOMP_Spare_MSK                          (0xF8000000)
+  #define DDRCMDCH1_CR_DDRCRCMDCOMP_Spare_MAX                          (0x0000001F)
+  #define DDRCMDCH1_CR_DDRCRCMDCOMP_Spare_DEF                          (0x00000000)
+
+#define DDRCMDCH1_CR_DDRCRCMDCOMPOFFSET_REG                          (0x00003304)
+  #define DDRCMDCH1_CR_DDRCRCMDCOMPOFFSET_ScompOffset_OFF              ( 0)
+  #define DDRCMDCH1_CR_DDRCRCMDCOMPOFFSET_ScompOffset_WID              ( 5)
+  #define DDRCMDCH1_CR_DDRCRCMDCOMPOFFSET_ScompOffset_MSK              (0x0000001F)
+  #define DDRCMDCH1_CR_DDRCRCMDCOMPOFFSET_ScompOffset_MAX              (0x0000001F)
+  #define DDRCMDCH1_CR_DDRCRCMDCOMPOFFSET_ScompOffset_DEF              (0x00000000)
+  #define DDRCMDCH1_CR_DDRCRCMDCOMPOFFSET_TcoCompOffset_OFF            ( 5)
+  #define DDRCMDCH1_CR_DDRCRCMDCOMPOFFSET_TcoCompOffset_WID            ( 4)
+  #define DDRCMDCH1_CR_DDRCRCMDCOMPOFFSET_TcoCompOffset_MSK            (0x000001E0)
+  #define DDRCMDCH1_CR_DDRCRCMDCOMPOFFSET_TcoCompOffset_MAX            (0x0000000F)
+  #define DDRCMDCH1_CR_DDRCRCMDCOMPOFFSET_TcoCompOffset_DEF            (0x00000000)
+  #define DDRCMDCH1_CR_DDRCRCMDCOMPOFFSET_RcompDrvUpOffset_OFF         ( 9)
+  #define DDRCMDCH1_CR_DDRCRCMDCOMPOFFSET_RcompDrvUpOffset_WID         ( 4)
+  #define DDRCMDCH1_CR_DDRCRCMDCOMPOFFSET_RcompDrvUpOffset_MSK         (0x00001E00)
+  #define DDRCMDCH1_CR_DDRCRCMDCOMPOFFSET_RcompDrvUpOffset_MAX         (0x0000000F)
+  #define DDRCMDCH1_CR_DDRCRCMDCOMPOFFSET_RcompDrvUpOffset_DEF         (0x00000000)
+  #define DDRCMDCH1_CR_DDRCRCMDCOMPOFFSET_RcompDrvDownOffset_OFF       (13)
+  #define DDRCMDCH1_CR_DDRCRCMDCOMPOFFSET_RcompDrvDownOffset_WID       ( 4)
+  #define DDRCMDCH1_CR_DDRCRCMDCOMPOFFSET_RcompDrvDownOffset_MSK       (0x0001E000)
+  #define DDRCMDCH1_CR_DDRCRCMDCOMPOFFSET_RcompDrvDownOffset_MAX       (0x0000000F)
+  #define DDRCMDCH1_CR_DDRCRCMDCOMPOFFSET_RcompDrvDownOffset_DEF       (0x00000000)
+  #define DDRCMDCH1_CR_DDRCRCMDCOMPOFFSET_Spare_OFF                    (17)
+  #define DDRCMDCH1_CR_DDRCRCMDCOMPOFFSET_Spare_WID                    (15)
+  #define DDRCMDCH1_CR_DDRCRCMDCOMPOFFSET_Spare_MSK                    (0xFFFE0000)
+  #define DDRCMDCH1_CR_DDRCRCMDCOMPOFFSET_Spare_MAX                    (0x00007FFF)
+  #define DDRCMDCH1_CR_DDRCRCMDCOMPOFFSET_Spare_DEF                    (0x00000000)
+
+#define DDRCMDCH1_CR_DDRCRCMDPICODING_REG                            (0x00003308)
+  #define DDRCMDCH1_CR_DDRCRCMDPICODING_CmdPi0Code_OFF                 ( 0)
+  #define DDRCMDCH1_CR_DDRCRCMDPICODING_CmdPi0Code_WID                 ( 7)
+  #define DDRCMDCH1_CR_DDRCRCMDPICODING_CmdPi0Code_MSK                 (0x0000007F)
+  #define DDRCMDCH1_CR_DDRCRCMDPICODING_CmdPi0Code_MAX                 (0x0000007F)
+  #define DDRCMDCH1_CR_DDRCRCMDPICODING_CmdPi0Code_DEF                 (0x00000000)
+  #define DDRCMDCH1_CR_DDRCRCMDPICODING_CmdPi1Code_OFF                 ( 7)
+  #define DDRCMDCH1_CR_DDRCRCMDPICODING_CmdPi1Code_WID                 ( 7)
+  #define DDRCMDCH1_CR_DDRCRCMDPICODING_CmdPi1Code_MSK                 (0x00003F80)
+  #define DDRCMDCH1_CR_DDRCRCMDPICODING_CmdPi1Code_MAX                 (0x0000007F)
+  #define DDRCMDCH1_CR_DDRCRCMDPICODING_CmdPi1Code_DEF                 (0x00000000)
+  #define DDRCMDCH1_CR_DDRCRCMDPICODING_Spare_OFF                      (14)
+  #define DDRCMDCH1_CR_DDRCRCMDPICODING_Spare_WID                      (18)
+  #define DDRCMDCH1_CR_DDRCRCMDPICODING_Spare_MSK                      (0xFFFFC000)
+  #define DDRCMDCH1_CR_DDRCRCMDPICODING_Spare_MAX                      (0x0003FFFF)
+  #define DDRCMDCH1_CR_DDRCRCMDPICODING_Spare_DEF                      (0x00000000)
+
+#define DDRCMDCH1_CR_DDRCRCMDCONTROLS_REG                            (0x0000330C)
+  #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_RefPi_OFF                      ( 0)
+  #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_RefPi_WID                      ( 4)
+  #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_RefPi_MSK                      (0x0000000F)
+  #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_RefPi_MAX                      (0x0000000F)
+  #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_RefPi_DEF                      (0x00000000)
+  #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_DllMask_OFF                    ( 4)
+  #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_DllMask_WID                    ( 2)
+  #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_DllMask_MSK                    (0x00000030)
+  #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_DllMask_MAX                    (0x00000003)
+  #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_DllMask_DEF                    (0x00000000)
+  #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_DllRsvd1_OFF                   ( 6)
+  #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_DllRsvd1_WID                   ( 1)
+  #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_DllRsvd1_MSK                   (0x00000040)
+  #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_DllRsvd1_MAX                   (0x00000001)
+  #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_DllRsvd1_DEF                   (0x00000000)
+  #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_TxOn_OFF                       ( 7)
+  #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_TxOn_WID                       ( 1)
+  #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_TxOn_MSK                       (0x00000080)
+  #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_TxOn_MAX                       (0x00000001)
+  #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_TxOn_DEF                       (0x00000000)
+  #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_IntClkOn_OFF                   ( 8)
+  #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_IntClkOn_WID                   ( 1)
+  #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_IntClkOn_MSK                   (0x00000100)
+  #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_IntClkOn_MAX                   (0x00000001)
+  #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_IntClkOn_DEF                   (0x00000000)
+  #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_RepClkOn_OFF                   ( 9)
+  #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_RepClkOn_WID                   ( 1)
+  #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_RepClkOn_MSK                   (0x00000200)
+  #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_RepClkOn_MAX                   (0x00000001)
+  #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_RepClkOn_DEF                   (0x00000000)
+  #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_IOLBCtl_OFF                    (10)
+  #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_IOLBCtl_WID                    ( 2)
+  #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_IOLBCtl_MSK                    (0x00000C00)
+  #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_IOLBCtl_MAX                    (0x00000003)
+  #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_IOLBCtl_DEF                    (0x00000000)
+  #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_OdtMode_OFF                    (12)
+  #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_OdtMode_WID                    ( 1)
+  #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_OdtMode_MSK                    (0x00001000)
+  #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_OdtMode_MAX                    (0x00000001)
+  #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_OdtMode_DEF                    (0x00000000)
+  #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_CmdTxEq_OFF                    (13)
+  #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_CmdTxEq_WID                    ( 2)
+  #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_CmdTxEq_MSK                    (0x00006000)
+  #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_CmdTxEq_MAX                    (0x00000003)
+  #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_CmdTxEq_DEF                    (0x00000000)
+  #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_EarlyWeakDrive_OFF             (15)
+  #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_EarlyWeakDrive_WID             ( 2)
+  #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_EarlyWeakDrive_MSK             (0x00018000)
+  #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_EarlyWeakDrive_MAX             (0x00000003)
+  #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_EarlyWeakDrive_DEF             (0x00000000)
+  #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_Reserved_OFF                   (17)
+  #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_Reserved_WID                   ( 4)
+  #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_Reserved_MSK                   (0x001E0000)
+  #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_Reserved_MAX                   (0x0000000F)
+  #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_Reserved_DEF                   (0x00000000)
+  #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_RxVref_OFF                     (21)
+  #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_RxVref_WID                     ( 6)
+  #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_RxVref_MSK                     (0x07E00000)
+  #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_RxVref_MAX                     (0x0000003F)
+  #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_RxVref_DEF                     (0x00000000)
+  #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_VccddqHi_OFF                   (27)
+  #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_VccddqHi_WID                   ( 1)
+  #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_VccddqHi_MSK                   (0x08000000)
+  #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_VccddqHi_MAX                   (0x00000001)
+  #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_VccddqHi_DEF                   (0x00000000)
+  #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_DllWeakLock_OFF                (28)
+  #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_DllWeakLock_WID                ( 1)
+  #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_DllWeakLock_MSK                (0x10000000)
+  #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_DllWeakLock_MAX                (0x00000001)
+  #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_DllWeakLock_DEF                (0x00000000)
+  #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_LPDDR_Mode_OFF                 (29)
+  #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_LPDDR_Mode_WID                 ( 1)
+  #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_LPDDR_Mode_MSK                 (0x20000000)
+  #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_LPDDR_Mode_MAX                 (0x00000001)
+  #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_LPDDR_Mode_DEF                 (0x00000000)
+  #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_LPDdrCAA_Dis_OFF               (30)
+  #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_LPDdrCAA_Dis_WID               ( 1)
+  #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_LPDdrCAA_Dis_MSK               (0x40000000)
+  #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_LPDdrCAA_Dis_MAX               (0x00000001)
+  #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_LPDdrCAA_Dis_DEF               (0x00000000)
+  #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_LPDdrCAB_Dis_OFF               (31)
+  #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_LPDdrCAB_Dis_WID               ( 1)
+  #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_LPDdrCAB_Dis_MSK               (0x80000000)
+  #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_LPDdrCAB_Dis_MAX               (0x00000001)
+  #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_LPDdrCAB_Dis_DEF               (0x00000000)
+
+#define DDRCMDCH1_CR_DLLPITESTANDADC_REG                             (0x00003324)
+  #define DDRCMDCH1_CR_DLLPITESTANDADC_RunTest_OFF                     ( 0)
+  #define DDRCMDCH1_CR_DLLPITESTANDADC_RunTest_WID                     ( 1)
+  #define DDRCMDCH1_CR_DLLPITESTANDADC_RunTest_MSK                     (0x00000001)
+  #define DDRCMDCH1_CR_DLLPITESTANDADC_RunTest_MAX                     (0x00000001)
+  #define DDRCMDCH1_CR_DLLPITESTANDADC_RunTest_DEF                     (0x00000000)
+  #define DDRCMDCH1_CR_DLLPITESTANDADC_Load_OFF                        ( 1)
+  #define DDRCMDCH1_CR_DLLPITESTANDADC_Load_WID                        ( 1)
+  #define DDRCMDCH1_CR_DLLPITESTANDADC_Load_MSK                        (0x00000002)
+  #define DDRCMDCH1_CR_DLLPITESTANDADC_Load_MAX                        (0x00000001)
+  #define DDRCMDCH1_CR_DLLPITESTANDADC_Load_DEF                        (0x00000000)
+  #define DDRCMDCH1_CR_DLLPITESTANDADC_ModeHVM_OFF                     ( 2)
+  #define DDRCMDCH1_CR_DLLPITESTANDADC_ModeHVM_WID                     ( 1)
+  #define DDRCMDCH1_CR_DLLPITESTANDADC_ModeHVM_MSK                     (0x00000004)
+  #define DDRCMDCH1_CR_DLLPITESTANDADC_ModeHVM_MAX                     (0x00000001)
+  #define DDRCMDCH1_CR_DLLPITESTANDADC_ModeHVM_DEF                     (0x00000000)
+  #define DDRCMDCH1_CR_DLLPITESTANDADC_ModeDV_OFF                      ( 3)
+  #define DDRCMDCH1_CR_DLLPITESTANDADC_ModeDV_WID                      ( 1)
+  #define DDRCMDCH1_CR_DLLPITESTANDADC_ModeDV_MSK                      (0x00000008)
+  #define DDRCMDCH1_CR_DLLPITESTANDADC_ModeDV_MAX                      (0x00000001)
+  #define DDRCMDCH1_CR_DLLPITESTANDADC_ModeDV_DEF                      (0x00000000)
+  #define DDRCMDCH1_CR_DLLPITESTANDADC_ModeADC_OFF                     ( 4)
+  #define DDRCMDCH1_CR_DLLPITESTANDADC_ModeADC_WID                     ( 1)
+  #define DDRCMDCH1_CR_DLLPITESTANDADC_ModeADC_MSK                     (0x00000010)
+  #define DDRCMDCH1_CR_DLLPITESTANDADC_ModeADC_MAX                     (0x00000001)
+  #define DDRCMDCH1_CR_DLLPITESTANDADC_ModeADC_DEF                     (0x00000000)
+  #define DDRCMDCH1_CR_DLLPITESTANDADC_LoadCount_OFF                   ( 5)
+  #define DDRCMDCH1_CR_DLLPITESTANDADC_LoadCount_WID                   (10)
+  #define DDRCMDCH1_CR_DLLPITESTANDADC_LoadCount_MSK                   (0x00007FE0)
+  #define DDRCMDCH1_CR_DLLPITESTANDADC_LoadCount_MAX                   (0x000003FF)
+  #define DDRCMDCH1_CR_DLLPITESTANDADC_CountStatus_OFF                 (15)
+  #define DDRCMDCH1_CR_DLLPITESTANDADC_CountStatus_WID                 (10)
+  #define DDRCMDCH1_CR_DLLPITESTANDADC_CountStatus_MSK                 (0x01FF8000)
+  #define DDRCMDCH1_CR_DLLPITESTANDADC_CountStatus_MAX                 (0x000003FF)
+  #define DDRCMDCH1_CR_DLLPITESTANDADC_CountStatus_DEF                 (0x00000000)
+  #define DDRCMDCH1_CR_DLLPITESTANDADC_Spare_OFF                       (25)
+  #define DDRCMDCH1_CR_DLLPITESTANDADC_Spare_WID                       ( 7)
+  #define DDRCMDCH1_CR_DLLPITESTANDADC_Spare_MSK                       (0xFE000000)
+  #define DDRCMDCH1_CR_DLLPITESTANDADC_Spare_MAX                       (0x0000007F)
+
+#pragma pack(pop)
+#endif  // __McIoCmd_h__
diff --git a/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcRegisters/McIoComp.h b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcRegisters/McIoComp.h
new file mode 100644
index 0000000..94eb0f0
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcRegisters/McIoComp.h
@@ -0,0 +1,648 @@
+/** @file
+  This file was automatically generated. Modify at your own risk.
+
+@copyright
+  Copyright (c) 2010 - 2012 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement
+**/
+#ifndef __McIoComp_h__
+#define __McIoComp_h__
+
+#pragma pack(push, 1)
+#include "MrcTypes.h"
+
+typedef union {
+  struct {
+    U32 RcompDrvUp                              :  6;  // Bits 5:0
+    U32 Spare0                                  :  3;  // Bits 8:6
+    U32 RcompDrvDown                            :  6;  // Bits 14:9
+    U32 VTComp                                  :  5;  // Bits 19:15
+    U32 TcoComp                                 :  6;  // Bits 25:20
+    U32 SlewRateComp                            :  5;  // Bits 30:26
+    U32 Spare2                                  :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRCOMP_CR_DDRCRDATACOMP0_STRUCT;
+
+typedef union {
+  struct {
+    U32 RcompOdtUp                              :  6;  // Bits 5:0
+    U32 Spare0                                  :  3;  // Bits 8:6
+    U32 RcompOdtDown                            :  6;  // Bits 14:9
+    U32 Spare1                                  :  1;  // Bits 15:15
+    U32 PanicDrvDn                              :  6;  // Bits 21:16
+    U32 PanicDrvUp                              :  6;  // Bits 27:22
+    U32 LevelShifterComp                        :  3;  // Bits 30:28
+    U32 Spare2                                  :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRCOMP_CR_DDRCRDATACOMP1_STRUCT;
+
+typedef union {
+  struct {
+    U32 Scomp                                   :  6;  // Bits 5:0
+    U32 TcoComp                                 :  6;  // Bits 11:6
+    U32 RcompDrvUp                              :  6;  // Bits 17:12
+    U32 RcompDrvDown                            :  6;  // Bits 23:18
+    U32 LsComp                                  :  3;  // Bits 26:24
+    U32 Spare                                   :  5;  // Bits 31:27
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRCOMP_CR_DDRCRCMDCOMP_STRUCT;
+
+typedef union {
+  struct {
+    U32 Scomp                                   :  6;  // Bits 5:0
+    U32 TcoComp                                 :  6;  // Bits 11:6
+    U32 RcompDrvUp                              :  6;  // Bits 17:12
+    U32 RcompDrvDown                            :  6;  // Bits 23:18
+    U32 LsComp                                  :  4;  // Bits 27:24
+    U32 Spare                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRCOMP_CR_DDRCRCTLCOMP_STRUCT;
+
+typedef union {
+  struct {
+    U32 Scomp                                   :  5;  // Bits 4:0
+    U32 TcoComp                                 :  6;  // Bits 10:5
+    U32 RcompDrvUp                              :  6;  // Bits 16:11
+    U32 RcompDrvDown                            :  6;  // Bits 22:17
+    U32 LsComp                                  :  4;  // Bits 26:23
+    U32 Spare                                   :  5;  // Bits 31:27
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRCOMP_CR_DDRCRCLKCOMP_STRUCT;
+
+typedef union {
+  struct {
+    U32 Rsvd                                    :  3;  // Bits 2:0
+    U32 DisableOdtStatic                        :  1;  // Bits 3:3
+    U32 DqOdtUpDnOff                            :  6;  // Bits 9:4
+    U32 FixOdtD                                 :  1;  // Bits 10:10
+    U32 DqDrvVref                               :  4;  // Bits 14:11
+    U32 DqOdtVref                               :  5;  // Bits 19:15
+    U32 CmdDrvVref                              :  4;  // Bits 23:20
+    U32 CtlDrvVref                              :  4;  // Bits 27:24
+    U32 ClkDrvVref                              :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRCOMP_CR_DDRCRCOMPCTL0_STRUCT;
+
+typedef union {
+  struct {
+    U32 DqScompCells                            :  4;  // Bits 3:0
+    U32 DqScompPC                               :  1;  // Bits 4:4
+    U32 CmdScompCells                           :  4;  // Bits 8:5
+    U32 CmdScompPC                              :  1;  // Bits 9:9
+    U32 CtlScompCells                           :  4;  // Bits 13:10
+    U32 CtlScompPC                              :  1;  // Bits 14:14
+    U32 ClkScompCells                           :  4;  // Bits 18:15
+    U32 ClkScompPC                              :  1;  // Bits 19:19
+    U32 TcoCmdOffset                            :  4;  // Bits 23:20
+    U32 CompClkOn                               :  1;  // Bits 24:24
+    U32 VccddqHi                                :  1;  // Bits 25:25
+    U32 spare                                   :  3;  // Bits 28:26
+    U32 DisableQuickComp                        :  1;  // Bits 29:29
+    U32 SinStep                                 :  1;  // Bits 30:30
+    U32 SinStepAdv                              :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRCOMP_CR_DDRCRCOMPCTL1_STRUCT;
+
+typedef union {
+  struct {
+    U32 PanicDrvDnVref                          :  6;  // Bits 5:0
+    U32 PanicDrvUpVref                          :  6;  // Bits 11:6
+    U32 VtOffset                                :  5;  // Bits 16:12
+    U32 VtSlopeA                                :  3;  // Bits 19:17
+    U32 VtSlopeB                                :  3;  // Bits 22:20
+    U32 Spare                                   :  9;  // Bits 31:23
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRCOMP_CR_DDRCRCOMPVSSHI_STRUCT;
+
+typedef union {
+  struct {
+    U32 DqDrvU                                  :  1;  // Bits 0:0
+    U32 DqDrvD                                  :  1;  // Bits 1:1
+    U32 DqOdtU                                  :  1;  // Bits 2:2
+    U32 DqOdtD                                  :  1;  // Bits 3:3
+    U32 CmdDrvU                                 :  1;  // Bits 4:4
+    U32 CmdDrvD                                 :  1;  // Bits 5:5
+    U32 CtlDrvU                                 :  1;  // Bits 6:6
+    U32 CtlDrvD                                 :  1;  // Bits 7:7
+    U32 ClkDrvU                                 :  1;  // Bits 8:8
+    U32 ClkDrvD                                 :  1;  // Bits 9:9
+    U32 DqSR                                    :  1;  // Bits 10:10
+    U32 CmdSR                                   :  1;  // Bits 11:11
+    U32 CtlSR                                   :  1;  // Bits 12:12
+    U32 ClkSR                                   :  1;  // Bits 13:13
+    U32 DqTcoOff                                :  1;  // Bits 14:14
+    U32 CmdTcoOff                               :  1;  // Bits 15:15
+    U32 DqTco                                   :  1;  // Bits 16:16
+    U32 CmdTco                                  :  1;  // Bits 17:17
+    U32 CtlTco                                  :  1;  // Bits 18:18
+    U32 ClkTco                                  :  1;  // Bits 19:19
+    U32 Spare1                                  :  1;  // Bits 20:20
+    U32 PanicDrvUp                              :  1;  // Bits 21:21
+    U32 PanicDrvDn                              :  1;  // Bits 22:22
+    U32 VTComp                                  :  1;  // Bits 23:23
+    U32 LsComp                                  :  3;  // Bits 26:24
+    U32 Spare2                                  :  5;  // Bits 31:27
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRCOMP_CR_DDRCRCOMPOVR_STRUCT;
+
+typedef union {
+  struct {
+    U32 Target                                  :  6;  // Bits 5:0
+    U32 HiBWDivider                             :  2;  // Bits 7:6
+    U32 LoBWDivider                             :  2;  // Bits 9:8
+    U32 SampleDivider                           :  3;  // Bits 12:10
+    U32 OpenLoop                                :  1;  // Bits 13:13
+    U32 BWError                                 :  2;  // Bits 15:14
+    U32 PanicEn                                 :  1;  // Bits 16:16
+    U32 Rsvd                                    :  1;  // Bits 17:17
+    U32 PanicVoltage                            :  4;  // Bits 21:18
+    U32 GainBoost                               :  1;  // Bits 22:22
+    U32 SelCode                                 :  1;  // Bits 23:23
+    U32 OutputCode                              :  8;  // Bits 31:24
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRCOMP_CR_DDRCRCOMPVSSHICONTROL_STRUCT;
+
+#define DDRCOMP_CR_DDRCRDATACOMP0_REG                                (0x00003A00)
+  #define DDRCOMP_CR_DDRCRDATACOMP0_RcompDrvUp_OFF                     ( 0)
+  #define DDRCOMP_CR_DDRCRDATACOMP0_RcompDrvUp_WID                     ( 6)
+  #define DDRCOMP_CR_DDRCRDATACOMP0_RcompDrvUp_MSK                     (0x0000003F)
+  #define DDRCOMP_CR_DDRCRDATACOMP0_RcompDrvUp_MAX                     (0x0000003F)
+  #define DDRCOMP_CR_DDRCRDATACOMP0_Spare0_OFF                         ( 6)
+  #define DDRCOMP_CR_DDRCRDATACOMP0_Spare0_WID                         ( 3)
+  #define DDRCOMP_CR_DDRCRDATACOMP0_Spare0_MSK                         (0x000001C0)
+  #define DDRCOMP_CR_DDRCRDATACOMP0_Spare0_MAX                         (0x00000007)
+  #define DDRCOMP_CR_DDRCRDATACOMP0_RcompDrvDown_OFF                   ( 9)
+  #define DDRCOMP_CR_DDRCRDATACOMP0_RcompDrvDown_WID                   ( 6)
+  #define DDRCOMP_CR_DDRCRDATACOMP0_RcompDrvDown_MSK                   (0x00007E00)
+  #define DDRCOMP_CR_DDRCRDATACOMP0_RcompDrvDown_MAX                   (0x0000003F)
+  #define DDRCOMP_CR_DDRCRDATACOMP0_VTComp_OFF                         (15)
+  #define DDRCOMP_CR_DDRCRDATACOMP0_VTComp_WID                         ( 5)
+  #define DDRCOMP_CR_DDRCRDATACOMP0_VTComp_MSK                         (0x000F8000)
+  #define DDRCOMP_CR_DDRCRDATACOMP0_VTComp_MAX                         (0x0000001F)
+  #define DDRCOMP_CR_DDRCRDATACOMP0_VTComp_DEF                         (0x00000005)
+  #define DDRCOMP_CR_DDRCRDATACOMP0_TcoComp_OFF                        (20)
+  #define DDRCOMP_CR_DDRCRDATACOMP0_TcoComp_WID                        ( 6)
+  #define DDRCOMP_CR_DDRCRDATACOMP0_TcoComp_MSK                        (0x03F00000)
+  #define DDRCOMP_CR_DDRCRDATACOMP0_TcoComp_MAX                        (0x0000003F)
+  #define DDRCOMP_CR_DDRCRDATACOMP0_SlewRateComp_OFF                   (26)
+  #define DDRCOMP_CR_DDRCRDATACOMP0_SlewRateComp_WID                   ( 5)
+  #define DDRCOMP_CR_DDRCRDATACOMP0_SlewRateComp_MSK                   (0x7C000000)
+  #define DDRCOMP_CR_DDRCRDATACOMP0_SlewRateComp_MAX                   (0x0000001F)
+  #define DDRCOMP_CR_DDRCRDATACOMP0_Spare2_OFF                         (31)
+  #define DDRCOMP_CR_DDRCRDATACOMP0_Spare2_WID                         ( 1)
+  #define DDRCOMP_CR_DDRCRDATACOMP0_Spare2_MSK                         (0x80000000)
+  #define DDRCOMP_CR_DDRCRDATACOMP0_Spare2_MAX                         (0x00000001)
+
+#define DDRCOMP_CR_DDRCRDATACOMP1_REG                                (0x00003A04)
+  #define DDRCOMP_CR_DDRCRDATACOMP1_RcompOdtUp_OFF                     ( 0)
+  #define DDRCOMP_CR_DDRCRDATACOMP1_RcompOdtUp_WID                     ( 6)
+  #define DDRCOMP_CR_DDRCRDATACOMP1_RcompOdtUp_MSK                     (0x0000003F)
+  #define DDRCOMP_CR_DDRCRDATACOMP1_RcompOdtUp_MAX                     (0x0000003F)
+  #define DDRCOMP_CR_DDRCRDATACOMP1_Spare0_OFF                         ( 6)
+  #define DDRCOMP_CR_DDRCRDATACOMP1_Spare0_WID                         ( 3)
+  #define DDRCOMP_CR_DDRCRDATACOMP1_Spare0_MSK                         (0x000001C0)
+  #define DDRCOMP_CR_DDRCRDATACOMP1_Spare0_MAX                         (0x00000007)
+  #define DDRCOMP_CR_DDRCRDATACOMP1_RcompOdtDown_OFF                   ( 9)
+  #define DDRCOMP_CR_DDRCRDATACOMP1_RcompOdtDown_WID                   ( 6)
+  #define DDRCOMP_CR_DDRCRDATACOMP1_RcompOdtDown_MSK                   (0x00007E00)
+  #define DDRCOMP_CR_DDRCRDATACOMP1_RcompOdtDown_MAX                   (0x0000003F)
+  #define DDRCOMP_CR_DDRCRDATACOMP1_Spare1_OFF                         (15)
+  #define DDRCOMP_CR_DDRCRDATACOMP1_Spare1_WID                         ( 1)
+  #define DDRCOMP_CR_DDRCRDATACOMP1_Spare1_MSK                         (0x00008000)
+  #define DDRCOMP_CR_DDRCRDATACOMP1_Spare1_MAX                         (0x00000001)
+  #define DDRCOMP_CR_DDRCRDATACOMP1_PanicDrvDn_OFF                     (16)
+  #define DDRCOMP_CR_DDRCRDATACOMP1_PanicDrvDn_WID                     ( 6)
+  #define DDRCOMP_CR_DDRCRDATACOMP1_PanicDrvDn_MSK                     (0x003F0000)
+  #define DDRCOMP_CR_DDRCRDATACOMP1_PanicDrvDn_MAX                     (0x0000003F)
+  #define DDRCOMP_CR_DDRCRDATACOMP1_PanicDrvDn_DEF                     (0x00000010)
+  #define DDRCOMP_CR_DDRCRDATACOMP1_PanicDrvUp_OFF                     (22)
+  #define DDRCOMP_CR_DDRCRDATACOMP1_PanicDrvUp_WID                     ( 6)
+  #define DDRCOMP_CR_DDRCRDATACOMP1_PanicDrvUp_MSK                     (0x0FC00000)
+  #define DDRCOMP_CR_DDRCRDATACOMP1_PanicDrvUp_MAX                     (0x0000003F)
+  #define DDRCOMP_CR_DDRCRDATACOMP1_PanicDrvUp_DEF                     (0x00000010)
+  #define DDRCOMP_CR_DDRCRDATACOMP1_LevelShifterComp_OFF               (28)
+  #define DDRCOMP_CR_DDRCRDATACOMP1_LevelShifterComp_WID               ( 3)
+  #define DDRCOMP_CR_DDRCRDATACOMP1_LevelShifterComp_MSK               (0x70000000)
+  #define DDRCOMP_CR_DDRCRDATACOMP1_LevelShifterComp_MAX               (0x00000007)
+  #define DDRCOMP_CR_DDRCRDATACOMP1_LevelShifterComp_DEF               (0x00000004)
+  #define DDRCOMP_CR_DDRCRDATACOMP1_Spare2_OFF                         (31)
+  #define DDRCOMP_CR_DDRCRDATACOMP1_Spare2_WID                         ( 1)
+  #define DDRCOMP_CR_DDRCRDATACOMP1_Spare2_MSK                         (0x80000000)
+  #define DDRCOMP_CR_DDRCRDATACOMP1_Spare2_MAX                         (0x00000001)
+
+#define DDRCOMP_CR_DDRCRCMDCOMP_REG                                  (0x00003A08)
+  #define DDRCOMP_CR_DDRCRCMDCOMP_Scomp_OFF                            ( 0)
+  #define DDRCOMP_CR_DDRCRCMDCOMP_Scomp_WID                            ( 6)
+  #define DDRCOMP_CR_DDRCRCMDCOMP_Scomp_MSK                            (0x0000003F)
+  #define DDRCOMP_CR_DDRCRCMDCOMP_Scomp_MAX                            (0x0000003F)
+  #define DDRCOMP_CR_DDRCRCMDCOMP_TcoComp_OFF                          ( 6)
+  #define DDRCOMP_CR_DDRCRCMDCOMP_TcoComp_WID                          ( 6)
+  #define DDRCOMP_CR_DDRCRCMDCOMP_TcoComp_MSK                          (0x00000FC0)
+  #define DDRCOMP_CR_DDRCRCMDCOMP_TcoComp_MAX                          (0x0000003F)
+  #define DDRCOMP_CR_DDRCRCMDCOMP_RcompDrvUp_OFF                       (12)
+  #define DDRCOMP_CR_DDRCRCMDCOMP_RcompDrvUp_WID                       ( 6)
+  #define DDRCOMP_CR_DDRCRCMDCOMP_RcompDrvUp_MSK                       (0x0003F000)
+  #define DDRCOMP_CR_DDRCRCMDCOMP_RcompDrvUp_MAX                       (0x0000003F)
+  #define DDRCOMP_CR_DDRCRCMDCOMP_RcompDrvDown_OFF                     (18)
+  #define DDRCOMP_CR_DDRCRCMDCOMP_RcompDrvDown_WID                     ( 6)
+  #define DDRCOMP_CR_DDRCRCMDCOMP_RcompDrvDown_MSK                     (0x00FC0000)
+  #define DDRCOMP_CR_DDRCRCMDCOMP_RcompDrvDown_MAX                     (0x0000003F)
+  #define DDRCOMP_CR_DDRCRCMDCOMP_LsComp_OFF                           (24)
+  #define DDRCOMP_CR_DDRCRCMDCOMP_LsComp_WID                           ( 3)
+  #define DDRCOMP_CR_DDRCRCMDCOMP_LsComp_MSK                           (0x07000000)
+  #define DDRCOMP_CR_DDRCRCMDCOMP_LsComp_MAX                           (0x00000007)
+  #define DDRCOMP_CR_DDRCRCMDCOMP_LsComp_DEF                           (0x00000004)
+  #define DDRCOMP_CR_DDRCRCMDCOMP_Spare_OFF                            (27)
+  #define DDRCOMP_CR_DDRCRCMDCOMP_Spare_WID                            ( 5)
+  #define DDRCOMP_CR_DDRCRCMDCOMP_Spare_MSK                            (0xF8000000)
+  #define DDRCOMP_CR_DDRCRCMDCOMP_Spare_MAX                            (0x0000001F)
+
+#define DDRCOMP_CR_DDRCRCTLCOMP_REG                                  (0x00003A0C)
+  #define DDRCOMP_CR_DDRCRCTLCOMP_Scomp_OFF                            ( 0)
+  #define DDRCOMP_CR_DDRCRCTLCOMP_Scomp_WID                            ( 6)
+  #define DDRCOMP_CR_DDRCRCTLCOMP_Scomp_MSK                            (0x0000003F)
+  #define DDRCOMP_CR_DDRCRCTLCOMP_Scomp_MAX                            (0x0000003F)
+  #define DDRCOMP_CR_DDRCRCTLCOMP_TcoComp_OFF                          ( 6)
+  #define DDRCOMP_CR_DDRCRCTLCOMP_TcoComp_WID                          ( 6)
+  #define DDRCOMP_CR_DDRCRCTLCOMP_TcoComp_MSK                          (0x00000FC0)
+  #define DDRCOMP_CR_DDRCRCTLCOMP_TcoComp_MAX                          (0x0000003F)
+  #define DDRCOMP_CR_DDRCRCTLCOMP_RcompDrvUp_OFF                       (12)
+  #define DDRCOMP_CR_DDRCRCTLCOMP_RcompDrvUp_WID                       ( 6)
+  #define DDRCOMP_CR_DDRCRCTLCOMP_RcompDrvUp_MSK                       (0x0003F000)
+  #define DDRCOMP_CR_DDRCRCTLCOMP_RcompDrvUp_MAX                       (0x0000003F)
+  #define DDRCOMP_CR_DDRCRCTLCOMP_RcompDrvDown_OFF                     (18)
+  #define DDRCOMP_CR_DDRCRCTLCOMP_RcompDrvDown_WID                     ( 6)
+  #define DDRCOMP_CR_DDRCRCTLCOMP_RcompDrvDown_MSK                     (0x00FC0000)
+  #define DDRCOMP_CR_DDRCRCTLCOMP_RcompDrvDown_MAX                     (0x0000003F)
+  #define DDRCOMP_CR_DDRCRCTLCOMP_LsComp_OFF                           (24)
+  #define DDRCOMP_CR_DDRCRCTLCOMP_LsComp_WID                           ( 4)
+  #define DDRCOMP_CR_DDRCRCTLCOMP_LsComp_MSK                           (0x0F000000)
+  #define DDRCOMP_CR_DDRCRCTLCOMP_LsComp_MAX                           (0x0000000F)
+  #define DDRCOMP_CR_DDRCRCTLCOMP_LsComp_DEF                           (0x00000004)
+  #define DDRCOMP_CR_DDRCRCTLCOMP_Spare_OFF                            (28)
+  #define DDRCOMP_CR_DDRCRCTLCOMP_Spare_WID                            ( 4)
+  #define DDRCOMP_CR_DDRCRCTLCOMP_Spare_MSK                            (0xF0000000)
+  #define DDRCOMP_CR_DDRCRCTLCOMP_Spare_MAX                            (0x0000000F)
+
+#define DDRCOMP_CR_DDRCRCLKCOMP_REG                                  (0x00003A10)
+  #define DDRCOMP_CR_DDRCRCLKCOMP_Scomp_OFF                            ( 0)
+  #define DDRCOMP_CR_DDRCRCLKCOMP_Scomp_WID                            ( 5)
+  #define DDRCOMP_CR_DDRCRCLKCOMP_Scomp_MSK                            (0x0000001F)
+  #define DDRCOMP_CR_DDRCRCLKCOMP_Scomp_MAX                            (0x0000001F)
+  #define DDRCOMP_CR_DDRCRCLKCOMP_TcoComp_OFF                          ( 5)
+  #define DDRCOMP_CR_DDRCRCLKCOMP_TcoComp_WID                          ( 6)
+  #define DDRCOMP_CR_DDRCRCLKCOMP_TcoComp_MSK                          (0x000007E0)
+  #define DDRCOMP_CR_DDRCRCLKCOMP_TcoComp_MAX                          (0x0000003F)
+  #define DDRCOMP_CR_DDRCRCLKCOMP_RcompDrvUp_OFF                       (11)
+  #define DDRCOMP_CR_DDRCRCLKCOMP_RcompDrvUp_WID                       ( 6)
+  #define DDRCOMP_CR_DDRCRCLKCOMP_RcompDrvUp_MSK                       (0x0001F800)
+  #define DDRCOMP_CR_DDRCRCLKCOMP_RcompDrvUp_MAX                       (0x0000003F)
+  #define DDRCOMP_CR_DDRCRCLKCOMP_RcompDrvDown_OFF                     (17)
+  #define DDRCOMP_CR_DDRCRCLKCOMP_RcompDrvDown_WID                     ( 6)
+  #define DDRCOMP_CR_DDRCRCLKCOMP_RcompDrvDown_MSK                     (0x007E0000)
+  #define DDRCOMP_CR_DDRCRCLKCOMP_RcompDrvDown_MAX                     (0x0000003F)
+  #define DDRCOMP_CR_DDRCRCLKCOMP_LsComp_OFF                           (23)
+  #define DDRCOMP_CR_DDRCRCLKCOMP_LsComp_WID                           ( 4)
+  #define DDRCOMP_CR_DDRCRCLKCOMP_LsComp_MSK                           (0x07800000)
+  #define DDRCOMP_CR_DDRCRCLKCOMP_LsComp_MAX                           (0x0000000F)
+  #define DDRCOMP_CR_DDRCRCLKCOMP_LsComp_DEF                           (0x00000004)
+  #define DDRCOMP_CR_DDRCRCLKCOMP_Spare_OFF                            (27)
+  #define DDRCOMP_CR_DDRCRCLKCOMP_Spare_WID                            ( 5)
+  #define DDRCOMP_CR_DDRCRCLKCOMP_Spare_MSK                            (0xF8000000)
+  #define DDRCOMP_CR_DDRCRCLKCOMP_Spare_MAX                            (0x0000001F)
+
+#define DDRCOMP_CR_DDRCRCOMPCTL0_REG                                 (0x00003A14)
+  #define DDRCOMP_CR_DDRCRCOMPCTL0_Rsvd_OFF                            ( 0)
+  #define DDRCOMP_CR_DDRCRCOMPCTL0_Rsvd_WID                            ( 3)
+  #define DDRCOMP_CR_DDRCRCOMPCTL0_Rsvd_MSK                            (0x00000007)
+  #define DDRCOMP_CR_DDRCRCOMPCTL0_Rsvd_MAX                            (0x00000007)
+  #define DDRCOMP_CR_DDRCRCOMPCTL0_DisableOdtStatic_OFF                ( 3)
+  #define DDRCOMP_CR_DDRCRCOMPCTL0_DisableOdtStatic_WID                ( 1)
+  #define DDRCOMP_CR_DDRCRCOMPCTL0_DisableOdtStatic_MSK                (0x00000008)
+  #define DDRCOMP_CR_DDRCRCOMPCTL0_DisableOdtStatic_MAX                (0x00000001)
+  #define DDRCOMP_CR_DDRCRCOMPCTL0_DqOdtUpDnOff_OFF                    ( 4)
+  #define DDRCOMP_CR_DDRCRCOMPCTL0_DqOdtUpDnOff_WID                    ( 6)
+  #define DDRCOMP_CR_DDRCRCOMPCTL0_DqOdtUpDnOff_MSK                    (0x000003F0)
+  #define DDRCOMP_CR_DDRCRCOMPCTL0_DqOdtUpDnOff_MAX                    (0x0000003F)
+  #define DDRCOMP_CR_DDRCRCOMPCTL0_FixOdtD_OFF                         (10)
+  #define DDRCOMP_CR_DDRCRCOMPCTL0_FixOdtD_WID                         ( 1)
+  #define DDRCOMP_CR_DDRCRCOMPCTL0_FixOdtD_MSK                         (0x00000400)
+  #define DDRCOMP_CR_DDRCRCOMPCTL0_FixOdtD_MAX                         (0x00000001)
+  #define DDRCOMP_CR_DDRCRCOMPCTL0_DqDrvVref_OFF                       (11)
+  #define DDRCOMP_CR_DDRCRCOMPCTL0_DqDrvVref_WID                       ( 4)
+  #define DDRCOMP_CR_DDRCRCOMPCTL0_DqDrvVref_MSK                       (0x00007800)
+  #define DDRCOMP_CR_DDRCRCOMPCTL0_DqDrvVref_MAX                       (0x0000000F)
+  #define DDRCOMP_CR_DDRCRCOMPCTL0_DqOdtVref_OFF                       (15)
+  #define DDRCOMP_CR_DDRCRCOMPCTL0_DqOdtVref_WID                       ( 5)
+  #define DDRCOMP_CR_DDRCRCOMPCTL0_DqOdtVref_MSK                       (0x000F8000)
+  #define DDRCOMP_CR_DDRCRCOMPCTL0_DqOdtVref_MAX                       (0x0000001F)
+  #define DDRCOMP_CR_DDRCRCOMPCTL0_CmdDrvVref_OFF                      (20)
+  #define DDRCOMP_CR_DDRCRCOMPCTL0_CmdDrvVref_WID                      ( 4)
+  #define DDRCOMP_CR_DDRCRCOMPCTL0_CmdDrvVref_MSK                      (0x00F00000)
+  #define DDRCOMP_CR_DDRCRCOMPCTL0_CmdDrvVref_MAX                      (0x0000000F)
+  #define DDRCOMP_CR_DDRCRCOMPCTL0_CtlDrvVref_OFF                      (24)
+  #define DDRCOMP_CR_DDRCRCOMPCTL0_CtlDrvVref_WID                      ( 4)
+  #define DDRCOMP_CR_DDRCRCOMPCTL0_CtlDrvVref_MSK                      (0x0F000000)
+  #define DDRCOMP_CR_DDRCRCOMPCTL0_CtlDrvVref_MAX                      (0x0000000F)
+  #define DDRCOMP_CR_DDRCRCOMPCTL0_ClkDrvVref_OFF                      (28)
+  #define DDRCOMP_CR_DDRCRCOMPCTL0_ClkDrvVref_WID                      ( 4)
+  #define DDRCOMP_CR_DDRCRCOMPCTL0_ClkDrvVref_MSK                      (0xF0000000)
+  #define DDRCOMP_CR_DDRCRCOMPCTL0_ClkDrvVref_MAX                      (0x0000000F)
+
+#define DDRCOMP_CR_DDRCRCOMPCTL1_REG                                 (0x00003A18)
+  #define DDRCOMP_CR_DDRCRCOMPCTL1_DqScompCells_OFF                    ( 0)
+  #define DDRCOMP_CR_DDRCRCOMPCTL1_DqScompCells_WID                    ( 4)
+  #define DDRCOMP_CR_DDRCRCOMPCTL1_DqScompCells_MSK                    (0x0000000F)
+  #define DDRCOMP_CR_DDRCRCOMPCTL1_DqScompCells_MAX                    (0x0000000F)
+  #define DDRCOMP_CR_DDRCRCOMPCTL1_DqScompPC_OFF                       ( 4)
+  #define DDRCOMP_CR_DDRCRCOMPCTL1_DqScompPC_WID                       ( 1)
+  #define DDRCOMP_CR_DDRCRCOMPCTL1_DqScompPC_MSK                       (0x00000010)
+  #define DDRCOMP_CR_DDRCRCOMPCTL1_DqScompPC_MAX                       (0x00000001)
+  #define DDRCOMP_CR_DDRCRCOMPCTL1_CmdScompCells_OFF                   ( 5)
+  #define DDRCOMP_CR_DDRCRCOMPCTL1_CmdScompCells_WID                   ( 4)
+  #define DDRCOMP_CR_DDRCRCOMPCTL1_CmdScompCells_MSK                   (0x000001E0)
+  #define DDRCOMP_CR_DDRCRCOMPCTL1_CmdScompCells_MAX                   (0x0000000F)
+  #define DDRCOMP_CR_DDRCRCOMPCTL1_CmdScompPC_OFF                      ( 9)
+  #define DDRCOMP_CR_DDRCRCOMPCTL1_CmdScompPC_WID                      ( 1)
+  #define DDRCOMP_CR_DDRCRCOMPCTL1_CmdScompPC_MSK                      (0x00000200)
+  #define DDRCOMP_CR_DDRCRCOMPCTL1_CmdScompPC_MAX                      (0x00000001)
+  #define DDRCOMP_CR_DDRCRCOMPCTL1_CtlScompCells_OFF                   (10)
+  #define DDRCOMP_CR_DDRCRCOMPCTL1_CtlScompCells_WID                   ( 4)
+  #define DDRCOMP_CR_DDRCRCOMPCTL1_CtlScompCells_MSK                   (0x00003C00)
+  #define DDRCOMP_CR_DDRCRCOMPCTL1_CtlScompCells_MAX                   (0x0000000F)
+  #define DDRCOMP_CR_DDRCRCOMPCTL1_CtlScompPC_OFF                      (14)
+  #define DDRCOMP_CR_DDRCRCOMPCTL1_CtlScompPC_WID                      ( 1)
+  #define DDRCOMP_CR_DDRCRCOMPCTL1_CtlScompPC_MSK                      (0x00004000)
+  #define DDRCOMP_CR_DDRCRCOMPCTL1_CtlScompPC_MAX                      (0x00000001)
+  #define DDRCOMP_CR_DDRCRCOMPCTL1_ClkScompCells_OFF                   (15)
+  #define DDRCOMP_CR_DDRCRCOMPCTL1_ClkScompCells_WID                   ( 4)
+  #define DDRCOMP_CR_DDRCRCOMPCTL1_ClkScompCells_MSK                   (0x00078000)
+  #define DDRCOMP_CR_DDRCRCOMPCTL1_ClkScompCells_MAX                   (0x0000000F)
+  #define DDRCOMP_CR_DDRCRCOMPCTL1_ClkScompPC_OFF                      (19)
+  #define DDRCOMP_CR_DDRCRCOMPCTL1_ClkScompPC_WID                      ( 1)
+  #define DDRCOMP_CR_DDRCRCOMPCTL1_ClkScompPC_MSK                      (0x00080000)
+  #define DDRCOMP_CR_DDRCRCOMPCTL1_ClkScompPC_MAX                      (0x00000001)
+  #define DDRCOMP_CR_DDRCRCOMPCTL1_TcoCmdOffset_OFF                    (20)
+  #define DDRCOMP_CR_DDRCRCOMPCTL1_TcoCmdOffset_WID                    ( 4)
+  #define DDRCOMP_CR_DDRCRCOMPCTL1_TcoCmdOffset_MSK                    (0x00F00000)
+  #define DDRCOMP_CR_DDRCRCOMPCTL1_TcoCmdOffset_MAX                    (0x0000000F)
+  #define DDRCOMP_CR_DDRCRCOMPCTL1_CompClkOn_OFF                       (24)
+  #define DDRCOMP_CR_DDRCRCOMPCTL1_CompClkOn_WID                       ( 1)
+  #define DDRCOMP_CR_DDRCRCOMPCTL1_CompClkOn_MSK                       (0x01000000)
+  #define DDRCOMP_CR_DDRCRCOMPCTL1_CompClkOn_MAX                       (0x00000001)
+  #define DDRCOMP_CR_DDRCRCOMPCTL1_VccddqHi_OFF                        (25)
+  #define DDRCOMP_CR_DDRCRCOMPCTL1_VccddqHi_WID                        ( 1)
+  #define DDRCOMP_CR_DDRCRCOMPCTL1_VccddqHi_MSK                        (0x02000000)
+  #define DDRCOMP_CR_DDRCRCOMPCTL1_VccddqHi_MAX                        (0x00000001)
+  #define DDRCOMP_CR_DDRCRCOMPCTL1_spare_OFF                           (26)
+  #define DDRCOMP_CR_DDRCRCOMPCTL1_spare_WID                           ( 3)
+  #define DDRCOMP_CR_DDRCRCOMPCTL1_spare_MSK                           (0x1C000000)
+  #define DDRCOMP_CR_DDRCRCOMPCTL1_spare_MAX                           (0x00000007)
+  #define DDRCOMP_CR_DDRCRCOMPCTL1_DisableQuickComp_OFF                (29)
+  #define DDRCOMP_CR_DDRCRCOMPCTL1_DisableQuickComp_WID                ( 1)
+  #define DDRCOMP_CR_DDRCRCOMPCTL1_DisableQuickComp_MSK                (0x20000000)
+  #define DDRCOMP_CR_DDRCRCOMPCTL1_DisableQuickComp_MAX                (0x00000001)
+  #define DDRCOMP_CR_DDRCRCOMPCTL1_SinStep_OFF                         (30)
+  #define DDRCOMP_CR_DDRCRCOMPCTL1_SinStep_WID                         ( 1)
+  #define DDRCOMP_CR_DDRCRCOMPCTL1_SinStep_MSK                         (0x40000000)
+  #define DDRCOMP_CR_DDRCRCOMPCTL1_SinStep_MAX                         (0x00000001)
+  #define DDRCOMP_CR_DDRCRCOMPCTL1_SinStepAdv_OFF                      (31)
+  #define DDRCOMP_CR_DDRCRCOMPCTL1_SinStepAdv_WID                      ( 1)
+  #define DDRCOMP_CR_DDRCRCOMPCTL1_SinStepAdv_MSK                      (0x80000000)
+  #define DDRCOMP_CR_DDRCRCOMPCTL1_SinStepAdv_MAX                      (0x00000001)
+
+#define DDRCOMP_CR_DDRCRCOMPVSSHI_REG                                (0x00003A1C)
+  #define DDRCOMP_CR_DDRCRCOMPVSSHI_PanicDrvDnVref_OFF                 ( 0)
+  #define DDRCOMP_CR_DDRCRCOMPVSSHI_PanicDrvDnVref_WID                 ( 6)
+  #define DDRCOMP_CR_DDRCRCOMPVSSHI_PanicDrvDnVref_MSK                 (0x0000003F)
+  #define DDRCOMP_CR_DDRCRCOMPVSSHI_PanicDrvDnVref_MAX                 (0x0000003F)
+  #define DDRCOMP_CR_DDRCRCOMPVSSHI_PanicDrvUpVref_OFF                 ( 6)
+  #define DDRCOMP_CR_DDRCRCOMPVSSHI_PanicDrvUpVref_WID                 ( 6)
+  #define DDRCOMP_CR_DDRCRCOMPVSSHI_PanicDrvUpVref_MSK                 (0x00000FC0)
+  #define DDRCOMP_CR_DDRCRCOMPVSSHI_PanicDrvUpVref_MAX                 (0x0000003F)
+  #define DDRCOMP_CR_DDRCRCOMPVSSHI_VtOffset_OFF                       (12)
+  #define DDRCOMP_CR_DDRCRCOMPVSSHI_VtOffset_WID                       ( 5)
+  #define DDRCOMP_CR_DDRCRCOMPVSSHI_VtOffset_MSK                       (0x0001F000)
+  #define DDRCOMP_CR_DDRCRCOMPVSSHI_VtOffset_MAX                       (0x0000001F)
+  #define DDRCOMP_CR_DDRCRCOMPVSSHI_VtSlopeA_OFF                       (17)
+  #define DDRCOMP_CR_DDRCRCOMPVSSHI_VtSlopeA_WID                       ( 3)
+  #define DDRCOMP_CR_DDRCRCOMPVSSHI_VtSlopeA_MSK                       (0x000E0000)
+  #define DDRCOMP_CR_DDRCRCOMPVSSHI_VtSlopeA_MAX                       (0x00000007)
+  #define DDRCOMP_CR_DDRCRCOMPVSSHI_VtSlopeB_OFF                       (20)
+  #define DDRCOMP_CR_DDRCRCOMPVSSHI_VtSlopeB_WID                       ( 3)
+  #define DDRCOMP_CR_DDRCRCOMPVSSHI_VtSlopeB_MSK                       (0x00700000)
+  #define DDRCOMP_CR_DDRCRCOMPVSSHI_VtSlopeB_MAX                       (0x00000007)
+  #define DDRCOMP_CR_DDRCRCOMPVSSHI_Spare_OFF                          (23)
+  #define DDRCOMP_CR_DDRCRCOMPVSSHI_Spare_WID                          ( 9)
+  #define DDRCOMP_CR_DDRCRCOMPVSSHI_Spare_MSK                          (0xFF800000)
+  #define DDRCOMP_CR_DDRCRCOMPVSSHI_Spare_MAX                          (0x000001FF)
+
+#define DDRCOMP_CR_DDRCRCOMPOVR_REG                                  (0x00003A20)
+  #define DDRCOMP_CR_DDRCRCOMPOVR_DqDrvU_OFF                           ( 0)
+  #define DDRCOMP_CR_DDRCRCOMPOVR_DqDrvU_WID                           ( 1)
+  #define DDRCOMP_CR_DDRCRCOMPOVR_DqDrvU_MSK                           (0x00000001)
+  #define DDRCOMP_CR_DDRCRCOMPOVR_DqDrvU_MAX                           (0x00000001)
+  #define DDRCOMP_CR_DDRCRCOMPOVR_DqDrvD_OFF                           ( 1)
+  #define DDRCOMP_CR_DDRCRCOMPOVR_DqDrvD_WID                           ( 1)
+  #define DDRCOMP_CR_DDRCRCOMPOVR_DqDrvD_MSK                           (0x00000002)
+  #define DDRCOMP_CR_DDRCRCOMPOVR_DqDrvD_MAX                           (0x00000001)
+  #define DDRCOMP_CR_DDRCRCOMPOVR_DqOdtU_OFF                           ( 2)
+  #define DDRCOMP_CR_DDRCRCOMPOVR_DqOdtU_WID                           ( 1)
+  #define DDRCOMP_CR_DDRCRCOMPOVR_DqOdtU_MSK                           (0x00000004)
+  #define DDRCOMP_CR_DDRCRCOMPOVR_DqOdtU_MAX                           (0x00000001)
+  #define DDRCOMP_CR_DDRCRCOMPOVR_DqOdtD_OFF                           ( 3)
+  #define DDRCOMP_CR_DDRCRCOMPOVR_DqOdtD_WID                           ( 1)
+  #define DDRCOMP_CR_DDRCRCOMPOVR_DqOdtD_MSK                           (0x00000008)
+  #define DDRCOMP_CR_DDRCRCOMPOVR_DqOdtD_MAX                           (0x00000001)
+  #define DDRCOMP_CR_DDRCRCOMPOVR_CmdDrvU_OFF                          ( 4)
+  #define DDRCOMP_CR_DDRCRCOMPOVR_CmdDrvU_WID                          ( 1)
+  #define DDRCOMP_CR_DDRCRCOMPOVR_CmdDrvU_MSK                          (0x00000010)
+  #define DDRCOMP_CR_DDRCRCOMPOVR_CmdDrvU_MAX                          (0x00000001)
+  #define DDRCOMP_CR_DDRCRCOMPOVR_CmdDrvD_OFF                          ( 5)
+  #define DDRCOMP_CR_DDRCRCOMPOVR_CmdDrvD_WID                          ( 1)
+  #define DDRCOMP_CR_DDRCRCOMPOVR_CmdDrvD_MSK                          (0x00000020)
+  #define DDRCOMP_CR_DDRCRCOMPOVR_CmdDrvD_MAX                          (0x00000001)
+  #define DDRCOMP_CR_DDRCRCOMPOVR_CtlDrvU_OFF                          ( 6)
+  #define DDRCOMP_CR_DDRCRCOMPOVR_CtlDrvU_WID                          ( 1)
+  #define DDRCOMP_CR_DDRCRCOMPOVR_CtlDrvU_MSK                          (0x00000040)
+  #define DDRCOMP_CR_DDRCRCOMPOVR_CtlDrvU_MAX                          (0x00000001)
+  #define DDRCOMP_CR_DDRCRCOMPOVR_CtlDrvD_OFF                          ( 7)
+  #define DDRCOMP_CR_DDRCRCOMPOVR_CtlDrvD_WID                          ( 1)
+  #define DDRCOMP_CR_DDRCRCOMPOVR_CtlDrvD_MSK                          (0x00000080)
+  #define DDRCOMP_CR_DDRCRCOMPOVR_CtlDrvD_MAX                          (0x00000001)
+  #define DDRCOMP_CR_DDRCRCOMPOVR_ClkDrvU_OFF                          ( 8)
+  #define DDRCOMP_CR_DDRCRCOMPOVR_ClkDrvU_WID                          ( 1)
+  #define DDRCOMP_CR_DDRCRCOMPOVR_ClkDrvU_MSK                          (0x00000100)
+  #define DDRCOMP_CR_DDRCRCOMPOVR_ClkDrvU_MAX                          (0x00000001)
+  #define DDRCOMP_CR_DDRCRCOMPOVR_ClkDrvD_OFF                          ( 9)
+  #define DDRCOMP_CR_DDRCRCOMPOVR_ClkDrvD_WID                          ( 1)
+  #define DDRCOMP_CR_DDRCRCOMPOVR_ClkDrvD_MSK                          (0x00000200)
+  #define DDRCOMP_CR_DDRCRCOMPOVR_ClkDrvD_MAX                          (0x00000001)
+  #define DDRCOMP_CR_DDRCRCOMPOVR_DqSR_OFF                             (10)
+  #define DDRCOMP_CR_DDRCRCOMPOVR_DqSR_WID                             ( 1)
+  #define DDRCOMP_CR_DDRCRCOMPOVR_DqSR_MSK                             (0x00000400)
+  #define DDRCOMP_CR_DDRCRCOMPOVR_DqSR_MAX                             (0x00000001)
+  #define DDRCOMP_CR_DDRCRCOMPOVR_CmdSR_OFF                            (11)
+  #define DDRCOMP_CR_DDRCRCOMPOVR_CmdSR_WID                            ( 1)
+  #define DDRCOMP_CR_DDRCRCOMPOVR_CmdSR_MSK                            (0x00000800)
+  #define DDRCOMP_CR_DDRCRCOMPOVR_CmdSR_MAX                            (0x00000001)
+  #define DDRCOMP_CR_DDRCRCOMPOVR_CtlSR_OFF                            (12)
+  #define DDRCOMP_CR_DDRCRCOMPOVR_CtlSR_WID                            ( 1)
+  #define DDRCOMP_CR_DDRCRCOMPOVR_CtlSR_MSK                            (0x00001000)
+  #define DDRCOMP_CR_DDRCRCOMPOVR_CtlSR_MAX                            (0x00000001)
+  #define DDRCOMP_CR_DDRCRCOMPOVR_ClkSR_OFF                            (13)
+  #define DDRCOMP_CR_DDRCRCOMPOVR_ClkSR_WID                            ( 1)
+  #define DDRCOMP_CR_DDRCRCOMPOVR_ClkSR_MSK                            (0x00002000)
+  #define DDRCOMP_CR_DDRCRCOMPOVR_ClkSR_MAX                            (0x00000001)
+  #define DDRCOMP_CR_DDRCRCOMPOVR_DqTcoOff_OFF                         (14)
+  #define DDRCOMP_CR_DDRCRCOMPOVR_DqTcoOff_WID                         ( 1)
+  #define DDRCOMP_CR_DDRCRCOMPOVR_DqTcoOff_MSK                         (0x00004000)
+  #define DDRCOMP_CR_DDRCRCOMPOVR_DqTcoOff_MAX                         (0x00000001)
+  #define DDRCOMP_CR_DDRCRCOMPOVR_CmdTcoOff_OFF                        (15)
+  #define DDRCOMP_CR_DDRCRCOMPOVR_CmdTcoOff_WID                        ( 1)
+  #define DDRCOMP_CR_DDRCRCOMPOVR_CmdTcoOff_MSK                        (0x00008000)
+  #define DDRCOMP_CR_DDRCRCOMPOVR_CmdTcoOff_MAX                        (0x00000001)
+  #define DDRCOMP_CR_DDRCRCOMPOVR_DqTco_OFF                            (16)
+  #define DDRCOMP_CR_DDRCRCOMPOVR_DqTco_WID                            ( 1)
+  #define DDRCOMP_CR_DDRCRCOMPOVR_DqTco_MSK                            (0x00010000)
+  #define DDRCOMP_CR_DDRCRCOMPOVR_DqTco_MAX                            (0x00000001)
+  #define DDRCOMP_CR_DDRCRCOMPOVR_CmdTco_OFF                           (17)
+  #define DDRCOMP_CR_DDRCRCOMPOVR_CmdTco_WID                           ( 1)
+  #define DDRCOMP_CR_DDRCRCOMPOVR_CmdTco_MSK                           (0x00020000)
+  #define DDRCOMP_CR_DDRCRCOMPOVR_CmdTco_MAX                           (0x00000001)
+  #define DDRCOMP_CR_DDRCRCOMPOVR_CtlTco_OFF                           (18)
+  #define DDRCOMP_CR_DDRCRCOMPOVR_CtlTco_WID                           ( 1)
+  #define DDRCOMP_CR_DDRCRCOMPOVR_CtlTco_MSK                           (0x00040000)
+  #define DDRCOMP_CR_DDRCRCOMPOVR_CtlTco_MAX                           (0x00000001)
+  #define DDRCOMP_CR_DDRCRCOMPOVR_ClkTco_OFF                           (19)
+  #define DDRCOMP_CR_DDRCRCOMPOVR_ClkTco_WID                           ( 1)
+  #define DDRCOMP_CR_DDRCRCOMPOVR_ClkTco_MSK                           (0x00080000)
+  #define DDRCOMP_CR_DDRCRCOMPOVR_ClkTco_MAX                           (0x00000001)
+  #define DDRCOMP_CR_DDRCRCOMPOVR_Spare1_OFF                           (20)
+  #define DDRCOMP_CR_DDRCRCOMPOVR_Spare1_WID                           ( 1)
+  #define DDRCOMP_CR_DDRCRCOMPOVR_Spare1_MSK                           (0x00100000)
+  #define DDRCOMP_CR_DDRCRCOMPOVR_Spare1_MAX                           (0x00000001)
+  #define DDRCOMP_CR_DDRCRCOMPOVR_PanicDrvUp_OFF                       (21)
+  #define DDRCOMP_CR_DDRCRCOMPOVR_PanicDrvUp_WID                       ( 1)
+  #define DDRCOMP_CR_DDRCRCOMPOVR_PanicDrvUp_MSK                       (0x00200000)
+  #define DDRCOMP_CR_DDRCRCOMPOVR_PanicDrvUp_MAX                       (0x00000001)
+  #define DDRCOMP_CR_DDRCRCOMPOVR_PanicDrvDn_OFF                       (22)
+  #define DDRCOMP_CR_DDRCRCOMPOVR_PanicDrvDn_WID                       ( 1)
+  #define DDRCOMP_CR_DDRCRCOMPOVR_PanicDrvDn_MSK                       (0x00400000)
+  #define DDRCOMP_CR_DDRCRCOMPOVR_PanicDrvDn_MAX                       (0x00000001)
+  #define DDRCOMP_CR_DDRCRCOMPOVR_VTComp_OFF                           (23)
+  #define DDRCOMP_CR_DDRCRCOMPOVR_VTComp_WID                           ( 1)
+  #define DDRCOMP_CR_DDRCRCOMPOVR_VTComp_MSK                           (0x00800000)
+  #define DDRCOMP_CR_DDRCRCOMPOVR_VTComp_MAX                           (0x00000001)
+  #define DDRCOMP_CR_DDRCRCOMPOVR_LsComp_OFF                           (24)
+  #define DDRCOMP_CR_DDRCRCOMPOVR_LsComp_WID                           ( 3)
+  #define DDRCOMP_CR_DDRCRCOMPOVR_LsComp_MSK                           (0x07000000)
+  #define DDRCOMP_CR_DDRCRCOMPOVR_LsComp_MAX                           (0x00000007)
+  #define DDRCOMP_CR_DDRCRCOMPOVR_LsComp_DEF                           (0x00000004)
+  #define DDRCOMP_CR_DDRCRCOMPOVR_Spare2_OFF                           (27)
+  #define DDRCOMP_CR_DDRCRCOMPOVR_Spare2_WID                           ( 5)
+  #define DDRCOMP_CR_DDRCRCOMPOVR_Spare2_MSK                           (0xF8000000)
+  #define DDRCOMP_CR_DDRCRCOMPOVR_Spare2_MAX                           (0x0000001F)
+
+#define DDRCOMP_CR_DDRCRCOMPVSSHICONTROL_REG                         (0x00003A24)
+  #define DDRCOMP_CR_DDRCRCOMPVSSHICONTROL_Target_OFF                  ( 0)
+  #define DDRCOMP_CR_DDRCRCOMPVSSHICONTROL_Target_WID                  ( 6)
+  #define DDRCOMP_CR_DDRCRCOMPVSSHICONTROL_Target_MSK                  (0x0000003F)
+  #define DDRCOMP_CR_DDRCRCOMPVSSHICONTROL_Target_MAX                  (0x0000003F)
+  #define DDRCOMP_CR_DDRCRCOMPVSSHICONTROL_Target_DEF                  (0x00000038)
+  #define DDRCOMP_CR_DDRCRCOMPVSSHICONTROL_HiBWDivider_OFF             ( 6)
+  #define DDRCOMP_CR_DDRCRCOMPVSSHICONTROL_HiBWDivider_WID             ( 2)
+  #define DDRCOMP_CR_DDRCRCOMPVSSHICONTROL_HiBWDivider_MSK             (0x000000C0)
+  #define DDRCOMP_CR_DDRCRCOMPVSSHICONTROL_HiBWDivider_MAX             (0x00000003)
+  #define DDRCOMP_CR_DDRCRCOMPVSSHICONTROL_HiBWDivider_DEF             (0x00000000)
+  #define DDRCOMP_CR_DDRCRCOMPVSSHICONTROL_LoBWDivider_OFF             ( 8)
+  #define DDRCOMP_CR_DDRCRCOMPVSSHICONTROL_LoBWDivider_WID             ( 2)
+  #define DDRCOMP_CR_DDRCRCOMPVSSHICONTROL_LoBWDivider_MSK             (0x00000300)
+  #define DDRCOMP_CR_DDRCRCOMPVSSHICONTROL_LoBWDivider_MAX             (0x00000003)
+  #define DDRCOMP_CR_DDRCRCOMPVSSHICONTROL_LoBWDivider_DEF             (0x00000002)
+  #define DDRCOMP_CR_DDRCRCOMPVSSHICONTROL_SampleDivider_OFF           (10)
+  #define DDRCOMP_CR_DDRCRCOMPVSSHICONTROL_SampleDivider_WID           ( 3)
+  #define DDRCOMP_CR_DDRCRCOMPVSSHICONTROL_SampleDivider_MSK           (0x00001C00)
+  #define DDRCOMP_CR_DDRCRCOMPVSSHICONTROL_SampleDivider_MAX           (0x00000007)
+  #define DDRCOMP_CR_DDRCRCOMPVSSHICONTROL_OpenLoop_OFF                (13)
+  #define DDRCOMP_CR_DDRCRCOMPVSSHICONTROL_OpenLoop_WID                ( 1)
+  #define DDRCOMP_CR_DDRCRCOMPVSSHICONTROL_OpenLoop_MSK                (0x00002000)
+  #define DDRCOMP_CR_DDRCRCOMPVSSHICONTROL_OpenLoop_MAX                (0x00000001)
+  #define DDRCOMP_CR_DDRCRCOMPVSSHICONTROL_BWError_OFF                 (14)
+  #define DDRCOMP_CR_DDRCRCOMPVSSHICONTROL_BWError_WID                 ( 2)
+  #define DDRCOMP_CR_DDRCRCOMPVSSHICONTROL_BWError_MSK                 (0x0000C000)
+  #define DDRCOMP_CR_DDRCRCOMPVSSHICONTROL_BWError_MAX                 (0x00000003)
+  #define DDRCOMP_CR_DDRCRCOMPVSSHICONTROL_BWError_DEF                 (0x00000002)
+  #define DDRCOMP_CR_DDRCRCOMPVSSHICONTROL_PanicEn_OFF                 (16)
+  #define DDRCOMP_CR_DDRCRCOMPVSSHICONTROL_PanicEn_WID                 ( 1)
+  #define DDRCOMP_CR_DDRCRCOMPVSSHICONTROL_PanicEn_MSK                 (0x00010000)
+  #define DDRCOMP_CR_DDRCRCOMPVSSHICONTROL_PanicEn_MAX                 (0x00000001)
+  #define DDRCOMP_CR_DDRCRCOMPVSSHICONTROL_PanicEn_DEF                 (0x00000001)
+  #define DDRCOMP_CR_DDRCRCOMPVSSHICONTROL_Rsvd_OFF                    (17)
+  #define DDRCOMP_CR_DDRCRCOMPVSSHICONTROL_Rsvd_WID                    ( 1)
+  #define DDRCOMP_CR_DDRCRCOMPVSSHICONTROL_Rsvd_MSK                    (0x00020000)
+  #define DDRCOMP_CR_DDRCRCOMPVSSHICONTROL_Rsvd_MAX                    (0x00000001)
+  #define DDRCOMP_CR_DDRCRCOMPVSSHICONTROL_PanicVoltage_OFF            (18)
+  #define DDRCOMP_CR_DDRCRCOMPVSSHICONTROL_PanicVoltage_WID            ( 4)
+  #define DDRCOMP_CR_DDRCRCOMPVSSHICONTROL_PanicVoltage_MSK            (0x003C0000)
+  #define DDRCOMP_CR_DDRCRCOMPVSSHICONTROL_PanicVoltage_MAX            (0x0000000F)
+  #define DDRCOMP_CR_DDRCRCOMPVSSHICONTROL_PanicVoltage_DEF            (0x00000003)
+  #define DDRCOMP_CR_DDRCRCOMPVSSHICONTROL_GainBoost_OFF               (22)
+  #define DDRCOMP_CR_DDRCRCOMPVSSHICONTROL_GainBoost_WID               ( 1)
+  #define DDRCOMP_CR_DDRCRCOMPVSSHICONTROL_GainBoost_MSK               (0x00400000)
+  #define DDRCOMP_CR_DDRCRCOMPVSSHICONTROL_GainBoost_MAX               (0x00000001)
+  #define DDRCOMP_CR_DDRCRCOMPVSSHICONTROL_GainBoost_DEF               (0x00000001)
+  #define DDRCOMP_CR_DDRCRCOMPVSSHICONTROL_SelCode_OFF                 (23)
+  #define DDRCOMP_CR_DDRCRCOMPVSSHICONTROL_SelCode_WID                 ( 1)
+  #define DDRCOMP_CR_DDRCRCOMPVSSHICONTROL_SelCode_MSK                 (0x00800000)
+  #define DDRCOMP_CR_DDRCRCOMPVSSHICONTROL_SelCode_MAX                 (0x00000001)
+  #define DDRCOMP_CR_DDRCRCOMPVSSHICONTROL_OutputCode_OFF              (24)
+  #define DDRCOMP_CR_DDRCRCOMPVSSHICONTROL_OutputCode_WID              ( 8)
+  #define DDRCOMP_CR_DDRCRCOMPVSSHICONTROL_OutputCode_MSK              (0xFF000000)
+  #define DDRCOMP_CR_DDRCRCOMPVSSHICONTROL_OutputCode_MAX              (0x000000FF)
+
+#pragma pack(pop)
+#endif  // __McIoComp_h__
diff --git a/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcRegisters/McIoData.h b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcRegisters/McIoData.h
new file mode 100644
index 0000000..4e6e898
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcRegisters/McIoData.h
@@ -0,0 +1,31196 @@
+/** @file
+  This file was automatically generated. Modify at your own risk.
+
+@copyright
+  Copyright (c) 2010 - 2012 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement
+**/
+#ifndef __McIoData_h__
+#define __McIoData_h__
+
+#pragma pack(push, 1)
+#include "MrcTypes.h"
+
+typedef union {
+  struct {
+    U32 RxRcvEnPi                               :  9;  // Bits 8:0
+    U32 RxDqsPPi                                :  6;  // Bits 14:9
+    U32 RxEq                                    :  5;  // Bits 19:15
+    U32 RxDqsNPi                                :  6;  // Bits 25:20
+    U32 RxVref                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA_CR_RXTRAINRANK0_STRUCT;
+
+typedef union {
+  struct {
+    U32 RxRcvEnPi                               :  9;  // Bits 8:0
+    U32 RxDqsPPi                                :  6;  // Bits 14:9
+    U32 RxEq                                    :  5;  // Bits 19:15
+    U32 RxDqsNPi                                :  6;  // Bits 25:20
+    U32 RxVref                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA_CR_RXTRAINRANK1_STRUCT;
+
+typedef union {
+  struct {
+    U32 RxRcvEnPi                               :  9;  // Bits 8:0
+    U32 RxDqsPPi                                :  6;  // Bits 14:9
+    U32 RxEq                                    :  5;  // Bits 19:15
+    U32 RxDqsNPi                                :  6;  // Bits 25:20
+    U32 RxVref                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA_CR_RXTRAINRANK2_STRUCT;
+
+typedef union {
+  struct {
+    U32 RxRcvEnPi                               :  9;  // Bits 8:0
+    U32 RxDqsPPi                                :  6;  // Bits 14:9
+    U32 RxEq                                    :  5;  // Bits 19:15
+    U32 RxDqsNPi                                :  6;  // Bits 25:20
+    U32 RxVref                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA_CR_RXTRAINRANK3_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA_CR_RXPERBITRANK0_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA_CR_RXPERBITRANK1_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA_CR_RXPERBITRANK2_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA_CR_RXPERBITRANK3_STRUCT;
+
+typedef union {
+  struct {
+    U32 TxDqDelay                               :  9;  // Bits 8:0
+    U32 TxDqsDelay                              :  9;  // Bits 17:9
+    U32 Spare0                                  :  2;  // Bits 19:18
+    U32 TxEqualization                          :  6;  // Bits 25:20
+    U32 Spare1                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA_CR_TXTRAINRANK0_STRUCT;
+
+typedef union {
+  struct {
+    U32 TxDqDelay                               :  9;  // Bits 8:0
+    U32 TxDqsDelay                              :  9;  // Bits 17:9
+    U32 Spare0                                  :  2;  // Bits 19:18
+    U32 TxEqualization                          :  6;  // Bits 25:20
+    U32 Spare1                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA_CR_TXTRAINRANK1_STRUCT;
+
+typedef union {
+  struct {
+    U32 TxDqDelay                               :  9;  // Bits 8:0
+    U32 TxDqsDelay                              :  9;  // Bits 17:9
+    U32 Spare0                                  :  2;  // Bits 19:18
+    U32 TxEqualization                          :  6;  // Bits 25:20
+    U32 Spare1                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA_CR_TXTRAINRANK2_STRUCT;
+
+typedef union {
+  struct {
+    U32 TxDqDelay                               :  9;  // Bits 8:0
+    U32 TxDqsDelay                              :  9;  // Bits 17:9
+    U32 Spare0                                  :  2;  // Bits 19:18
+    U32 TxEqualization                          :  6;  // Bits 25:20
+    U32 Spare1                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA_CR_TXTRAINRANK3_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA_CR_TXPERBITRANK0_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA_CR_TXPERBITRANK1_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA_CR_TXPERBITRANK2_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA_CR_TXPERBITRANK3_STRUCT;
+
+typedef union {
+  struct {
+    U32 RcompDrvUp                              :  6;  // Bits 5:0
+    U32 Spare0                                  :  3;  // Bits 8:6
+    U32 RcompDrvDown                            :  6;  // Bits 14:9
+    U32 VTComp                                  :  5;  // Bits 19:15
+    U32 TcoComp                                 :  6;  // Bits 25:20
+    U32 SlewRateComp                            :  5;  // Bits 30:26
+    U32 Spare2                                  :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA_CR_RCOMPDATA0_STRUCT;
+
+typedef union {
+  struct {
+    U32 RcompOdtUp                              :  6;  // Bits 5:0
+    U32 Spare0                                  :  3;  // Bits 8:6
+    U32 RcompOdtDown                            :  6;  // Bits 14:9
+    U32 Spare1                                  :  1;  // Bits 15:15
+    U32 PanicDrvDn                              :  6;  // Bits 21:16
+    U32 PanicDrvUp                              :  6;  // Bits 27:22
+    U32 LevelShifterComp                        :  3;  // Bits 30:28
+    U32 Spare2                                  :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA_CR_RCOMPDATA1_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA_CR_TXXTALK_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA_CR_RXOFFSETVDQ_STRUCT;
+
+typedef union {
+  struct {
+    U32 Spare                                   :  32;  // Bits 31:0
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA_CR_DDRDATARESERVED_STRUCT;
+
+typedef union {
+  struct {
+    U32 DataTrainFeedback                       :  9;  // Bits 8:0
+    U32 Spare                                   :  23;  // Bits 31:9
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA_CR_DATATRAINFEEDBACK_STRUCT;
+
+typedef union {
+  struct {
+    U32 RunTest                                 :  1;  // Bits 0:0
+    U32 Load                                    :  1;  // Bits 1:1
+    U32 ModeHVM                                 :  1;  // Bits 2:2
+    U32 ModeDV                                  :  1;  // Bits 3:3
+    U32 ModeADC                                 :  1;  // Bits 4:4
+    U32 LoadCount                               :  10;  // Bits 14:5
+    U32 CountStatus                             :  10;  // Bits 24:15
+    U32 Spare                                   :  7;  // Bits 31:25
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA_CR_DLLPITESTANDADC_STRUCT;
+
+typedef union {
+  struct {
+    U32 DqDrvUpCompOffset                       :  6;  // Bits 5:0
+    U32 DqDrvDownCompOffset                     :  6;  // Bits 11:6
+    U32 DqOdtUpCompOffset                       :  5;  // Bits 16:12
+    U32 DqOdtDownCompOffset                     :  5;  // Bits 21:17
+    U32 DqTcoCompOffset                         :  5;  // Bits 26:22
+    U32 DqSlewRateCompOffset                    :  5;  // Bits 31:27
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA_CR_DDRCRDATAOFFSETCOMP_STRUCT;
+
+typedef union {
+  struct {
+    U32 RefPi                                   :  4;  // Bits 3:0
+    U32 DllMask                                 :  2;  // Bits 5:4
+    U32 DllWeakLock                             :  1;  // Bits 6:6
+    U32 SdllSegmentDisable                      :  3;  // Bits 9:7
+    U32 RxBiasCtl                               :  3;  // Bits 12:10
+    U32 OdtDelay                                :  4;  // Bits 16:13
+    U32 OdtDuration                             :  3;  // Bits 19:17
+    U32 SenseAmpDelay                           :  4;  // Bits 23:20
+    U32 SenseAmpDuration                        :  3;  // Bits 26:24
+    U32 BurstEndODTDelay                        :  3;  // Bits 29:27
+    U32 LpDdrLongOdtEn                          :  1;  // Bits 30:30
+    U32 Rsvd1                                   :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA_CR_DDRCRDATACONTROL1_STRUCT;
+
+typedef union {
+  struct {
+    U32 RxStaggerCtl                            :  5;  // Bits 4:0
+    U32 ForceBiasOn                             :  1;  // Bits 5:5
+    U32 ForceRxOn                               :  1;  // Bits 6:6
+    U32 LeakerComp                              :  2;  // Bits 8:7
+    U32 RxDqsAmpOffset                          :  4;  // Bits 12:9
+    U32 RxClkStgNum                             :  5;  // Bits 17:13
+    U32 WlLongDelEn                             :  1;  // Bits 18:18
+    U32 Spare                                   :  13;  // Bits 31:19
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA_CR_DDRCRDATACONTROL2_STRUCT;
+
+typedef union {
+  struct {
+    U32 VrefCtl                                 :  24;  // Bits 23:0
+    U32 OutputCode                              :  8;  // Bits 31:24
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA_CR_DDRCRVREFCONTROL_STRUCT;
+
+typedef union {
+  struct {
+    U32 VssHiCtl                                :  24;  // Bits 23:0
+    U32 OutputCode                              :  8;  // Bits 31:24
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA_CR_DDRCRVSSHICONTROL_STRUCT;
+
+typedef union {
+  struct {
+    U32 VssHiOrVrefCtl                          :  24;  // Bits 23:0
+    U32 OutputCode                              :  8;  // Bits 31:24
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA_CR_DDRCRVSSHIORVREFCONTROL_STRUCT;
+
+typedef union {
+  struct {
+    U32 RcvEnOffset                             :  6;  // Bits 5:0
+    U32 RxDqsOffset                             :  6;  // Bits 11:6
+    U32 TxDqOffset                              :  6;  // Bits 17:12
+    U32 TxDqsOffset                             :  6;  // Bits 23:18
+    U32 VrefOffset                              :  7;  // Bits 30:24
+    U32 Spare                                   :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA_CR_DDRCRDATAOFFSETTRAIN_STRUCT;
+
+typedef union {
+  struct {
+    U32 RxTrainingMode                          :  1;  // Bits 0:0
+    U32 WLTrainingMode                          :  1;  // Bits 1:1
+    U32 RLTrainingMode                          :  1;  // Bits 2:2
+    U32 SenseampTrainingMode                    :  1;  // Bits 3:3
+    U32 TxOn                                    :  1;  // Bits 4:4
+    U32 RfOn                                    :  1;  // Bits 5:5
+    U32 RxPiOn                                  :  1;  // Bits 6:6
+    U32 TxPiOn                                  :  1;  // Bits 7:7
+    U32 InternalClocksOn                        :  1;  // Bits 8:8
+    U32 RepeaterClocksOn                        :  1;  // Bits 9:9
+    U32 TxDisable                               :  1;  // Bits 10:10
+    U32 RxDisable                               :  1;  // Bits 11:11
+    U32 TxLong                                  :  1;  // Bits 12:12
+    U32 RxDqsCtle                               :  2;  // Bits 14:13
+    U32 RxReadPointer                           :  3;  // Bits 17:15
+    U32 DriverSegmentEnable                     :  1;  // Bits 18:18
+    U32 DataVccddqHi                            :  1;  // Bits 19:19
+    U32 ReadRFRd                                :  1;  // Bits 20:20
+    U32 ReadRFWr                                :  1;  // Bits 21:21
+    U32 ReadRFRank                              :  2;  // Bits 23:22
+    U32 ForceOdtOn                              :  1;  // Bits 24:24
+    U32 OdtSampOff                              :  1;  // Bits 25:25
+    U32 DisableOdtStatic                        :  1;  // Bits 26:26
+    U32 DdrCRForceODTOn                         :  1;  // Bits 27:27
+    U32 LPDDR_Mode                              :  1;  // Bits 28:28
+    U32 EnReadPreamble                          :  1;  // Bits 29:29
+    U32 OdtSampExtendEn                         :  1;  // Bits 30:30
+    U32 EarlyRleakEn                            :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA_CR_DDRCRDATACONTROL0_STRUCT;
+
+typedef union {
+  struct {
+    U32 CAVrefCtl                               :  7;  // Bits 6:0
+    U32 Ch1VrefCtl                              :  7;  // Bits 13:7
+    U32 Ch0VrefCtl                              :  7;  // Bits 20:14
+    U32 EnDimmVrefCA                            :  1;  // Bits 21:21
+    U32 EnDimmVrefCh1                           :  1;  // Bits 22:22
+    U32 EnDimmVrefCh0                           :  1;  // Bits 23:23
+    U32 HiZTimerCtrl                            :  2;  // Bits 25:24
+    U32 VccddqHiQnnnH                           :  1;  // Bits 26:26
+    U32 Rsvd                                    :  2;  // Bits 28:27
+    U32 caSlowBW                                :  1;  // Bits 29:29
+    U32 ch0SlowBW                               :  1;  // Bits 30:30
+    U32 ch1SlowBW                               :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA_CR_DDRCRVREFADJUST1_STRUCT;
+
+typedef union {
+  struct {
+    U32 RxRcvEnPi                               :  9;  // Bits 8:0
+    U32 RxDqsPPi                                :  6;  // Bits 14:9
+    U32 RxEq                                    :  5;  // Bits 19:15
+    U32 RxDqsNPi                                :  6;  // Bits 25:20
+    U32 RxVref                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATACH0_CR_RXTRAINRANK0_STRUCT;
+
+typedef union {
+  struct {
+    U32 RxRcvEnPi                               :  9;  // Bits 8:0
+    U32 RxDqsPPi                                :  6;  // Bits 14:9
+    U32 RxEq                                    :  5;  // Bits 19:15
+    U32 RxDqsNPi                                :  6;  // Bits 25:20
+    U32 RxVref                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATACH0_CR_RXTRAINRANK1_STRUCT;
+
+typedef union {
+  struct {
+    U32 RxRcvEnPi                               :  9;  // Bits 8:0
+    U32 RxDqsPPi                                :  6;  // Bits 14:9
+    U32 RxEq                                    :  5;  // Bits 19:15
+    U32 RxDqsNPi                                :  6;  // Bits 25:20
+    U32 RxVref                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATACH0_CR_RXTRAINRANK2_STRUCT;
+
+typedef union {
+  struct {
+    U32 RxRcvEnPi                               :  9;  // Bits 8:0
+    U32 RxDqsPPi                                :  6;  // Bits 14:9
+    U32 RxEq                                    :  5;  // Bits 19:15
+    U32 RxDqsNPi                                :  6;  // Bits 25:20
+    U32 RxVref                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATACH0_CR_RXTRAINRANK3_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATACH0_CR_RXPERBITRANK0_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATACH0_CR_RXPERBITRANK1_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATACH0_CR_RXPERBITRANK2_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATACH0_CR_RXPERBITRANK3_STRUCT;
+
+typedef union {
+  struct {
+    U32 TxDqDelay                               :  9;  // Bits 8:0
+    U32 TxDqsDelay                              :  9;  // Bits 17:9
+    U32 Spare0                                  :  2;  // Bits 19:18
+    U32 TxEqualization                          :  6;  // Bits 25:20
+    U32 Spare1                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATACH0_CR_TXTRAINRANK0_STRUCT;
+
+typedef union {
+  struct {
+    U32 TxDqDelay                               :  9;  // Bits 8:0
+    U32 TxDqsDelay                              :  9;  // Bits 17:9
+    U32 Spare0                                  :  2;  // Bits 19:18
+    U32 TxEqualization                          :  6;  // Bits 25:20
+    U32 Spare1                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATACH0_CR_TXTRAINRANK1_STRUCT;
+
+typedef union {
+  struct {
+    U32 TxDqDelay                               :  9;  // Bits 8:0
+    U32 TxDqsDelay                              :  9;  // Bits 17:9
+    U32 Spare0                                  :  2;  // Bits 19:18
+    U32 TxEqualization                          :  6;  // Bits 25:20
+    U32 Spare1                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATACH0_CR_TXTRAINRANK2_STRUCT;
+
+typedef union {
+  struct {
+    U32 TxDqDelay                               :  9;  // Bits 8:0
+    U32 TxDqsDelay                              :  9;  // Bits 17:9
+    U32 Spare0                                  :  2;  // Bits 19:18
+    U32 TxEqualization                          :  6;  // Bits 25:20
+    U32 Spare1                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATACH0_CR_TXTRAINRANK3_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATACH0_CR_TXPERBITRANK0_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATACH0_CR_TXPERBITRANK1_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATACH0_CR_TXPERBITRANK2_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATACH0_CR_TXPERBITRANK3_STRUCT;
+
+typedef union {
+  struct {
+    U32 RcompDrvUp                              :  6;  // Bits 5:0
+    U32 Spare0                                  :  3;  // Bits 8:6
+    U32 RcompDrvDown                            :  6;  // Bits 14:9
+    U32 VTComp                                  :  5;  // Bits 19:15
+    U32 TcoComp                                 :  6;  // Bits 25:20
+    U32 SlewRateComp                            :  5;  // Bits 30:26
+    U32 Spare2                                  :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATACH0_CR_RCOMPDATA0_STRUCT;
+
+typedef union {
+  struct {
+    U32 RcompOdtUp                              :  6;  // Bits 5:0
+    U32 Spare0                                  :  3;  // Bits 8:6
+    U32 RcompOdtDown                            :  6;  // Bits 14:9
+    U32 Spare1                                  :  1;  // Bits 15:15
+    U32 PanicDrvDn                              :  6;  // Bits 21:16
+    U32 PanicDrvUp                              :  6;  // Bits 27:22
+    U32 LevelShifterComp                        :  3;  // Bits 30:28
+    U32 Spare2                                  :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATACH0_CR_RCOMPDATA1_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATACH0_CR_TXXTALK_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATACH0_CR_RXOFFSETVDQ_STRUCT;
+
+typedef union {
+  struct {
+    U32 Spare                                   :  32;  // Bits 31:0
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATACH0_CR_DDRDATARESERVED_STRUCT;
+
+typedef union {
+  struct {
+    U32 DataTrainFeedback                       :  9;  // Bits 8:0
+    U32 Spare                                   :  23;  // Bits 31:9
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATACH0_CR_DATATRAINFEEDBACK_STRUCT;
+
+typedef union {
+  struct {
+    U32 RunTest                                 :  1;  // Bits 0:0
+    U32 Load                                    :  1;  // Bits 1:1
+    U32 ModeHVM                                 :  1;  // Bits 2:2
+    U32 ModeDV                                  :  1;  // Bits 3:3
+    U32 ModeADC                                 :  1;  // Bits 4:4
+    U32 LoadCount                               :  10;  // Bits 14:5
+    U32 CountStatus                             :  10;  // Bits 24:15
+    U32 Spare                                   :  7;  // Bits 31:25
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATACH0_CR_DLLPITESTANDADC_STRUCT;
+
+typedef union {
+  struct {
+    U32 DqDrvUpCompOffset                       :  6;  // Bits 5:0
+    U32 DqDrvDownCompOffset                     :  6;  // Bits 11:6
+    U32 DqOdtUpCompOffset                       :  5;  // Bits 16:12
+    U32 DqOdtDownCompOffset                     :  5;  // Bits 21:17
+    U32 DqTcoCompOffset                         :  5;  // Bits 26:22
+    U32 DqSlewRateCompOffset                    :  5;  // Bits 31:27
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATACH0_CR_DDRCRDATAOFFSETCOMP_STRUCT;
+
+typedef union {
+  struct {
+    U32 RefPi                                   :  4;  // Bits 3:0
+    U32 DllMask                                 :  2;  // Bits 5:4
+    U32 DllWeakLock                             :  1;  // Bits 6:6
+    U32 SdllSegmentDisable                      :  3;  // Bits 9:7
+    U32 RxBiasCtl                               :  3;  // Bits 12:10
+    U32 OdtDelay                                :  4;  // Bits 16:13
+    U32 OdtDuration                             :  3;  // Bits 19:17
+    U32 SenseAmpDelay                           :  4;  // Bits 23:20
+    U32 SenseAmpDuration                        :  3;  // Bits 26:24
+    U32 BurstEndODTDelay                        :  3;  // Bits 29:27
+    U32 LpDdrLongOdtEn                          :  1;  // Bits 30:30
+    U32 Rsvd1                                   :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATACH0_CR_DDRCRDATACONTROL1_STRUCT;
+
+typedef union {
+  struct {
+    U32 RxStaggerCtl                            :  5;  // Bits 4:0
+    U32 ForceBiasOn                             :  1;  // Bits 5:5
+    U32 ForceRxOn                               :  1;  // Bits 6:6
+    U32 LeakerComp                              :  2;  // Bits 8:7
+    U32 RxDqsAmpOffset                          :  4;  // Bits 12:9
+    U32 RxClkStgNum                             :  5;  // Bits 17:13
+    U32 WlLongDelEn                             :  1;  // Bits 18:18
+    U32 Spare                                   :  13;  // Bits 31:19
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATACH0_CR_DDRCRDATACONTROL2_STRUCT;
+
+typedef union {
+  struct {
+    U32 VssHiOrVrefCtl                          :  24;  // Bits 23:0
+    U32 OutputCode                              :  8;  // Bits 31:24
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATACH0_CR_DDRCRVSSHIORVREFCONTROL_STRUCT;
+
+typedef union {
+  struct {
+    U32 RcvEnOffset                             :  6;  // Bits 5:0
+    U32 RxDqsOffset                             :  6;  // Bits 11:6
+    U32 TxDqOffset                              :  6;  // Bits 17:12
+    U32 TxDqsOffset                             :  6;  // Bits 23:18
+    U32 VrefOffset                              :  7;  // Bits 30:24
+    U32 Spare                                   :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN_STRUCT;
+
+typedef union {
+  struct {
+    U32 RxTrainingMode                          :  1;  // Bits 0:0
+    U32 WLTrainingMode                          :  1;  // Bits 1:1
+    U32 RLTrainingMode                          :  1;  // Bits 2:2
+    U32 SenseampTrainingMode                    :  1;  // Bits 3:3
+    U32 TxOn                                    :  1;  // Bits 4:4
+    U32 RfOn                                    :  1;  // Bits 5:5
+    U32 RxPiOn                                  :  1;  // Bits 6:6
+    U32 TxPiOn                                  :  1;  // Bits 7:7
+    U32 InternalClocksOn                        :  1;  // Bits 8:8
+    U32 RepeaterClocksOn                        :  1;  // Bits 9:9
+    U32 TxDisable                               :  1;  // Bits 10:10
+    U32 RxDisable                               :  1;  // Bits 11:11
+    U32 TxLong                                  :  1;  // Bits 12:12
+    U32 RxDqsCtle                               :  2;  // Bits 14:13
+    U32 RxReadPointer                           :  3;  // Bits 17:15
+    U32 DriverSegmentEnable                     :  1;  // Bits 18:18
+    U32 DataVccddqHi                            :  1;  // Bits 19:19
+    U32 ReadRFRd                                :  1;  // Bits 20:20
+    U32 ReadRFWr                                :  1;  // Bits 21:21
+    U32 ReadRFRank                              :  2;  // Bits 23:22
+    U32 ForceOdtOn                              :  1;  // Bits 24:24
+    U32 OdtSampOff                              :  1;  // Bits 25:25
+    U32 DisableOdtStatic                        :  1;  // Bits 26:26
+    U32 DdrCRForceODTOn                         :  1;  // Bits 27:27
+    U32 LPDDR_Mode                              :  1;  // Bits 28:28
+    U32 EnReadPreamble                          :  1;  // Bits 29:29
+    U32 OdtSampExtendEn                         :  1;  // Bits 30:30
+    U32 EarlyRleakEn                            :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATACH0_CR_DDRCRDATACONTROL0_STRUCT;
+
+typedef union {
+  struct {
+    U32 CAVrefCtl                               :  7;  // Bits 6:0
+    U32 Ch1VrefCtl                              :  7;  // Bits 13:7
+    U32 Ch0VrefCtl                              :  7;  // Bits 20:14
+    U32 EnDimmVrefCA                            :  1;  // Bits 21:21
+    U32 EnDimmVrefCh1                           :  1;  // Bits 22:22
+    U32 EnDimmVrefCh0                           :  1;  // Bits 23:23
+    U32 HiZTimerCtrl                            :  2;  // Bits 25:24
+    U32 VccddqHiQnnnH                           :  1;  // Bits 26:26
+    U32 Rsvd                                    :  2;  // Bits 28:27
+    U32 caSlowBW                                :  1;  // Bits 29:29
+    U32 ch0SlowBW                               :  1;  // Bits 30:30
+    U32 ch1SlowBW                               :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATACH0_CR_DDRCRVREFADJUST1_STRUCT;
+
+typedef union {
+  struct {
+    U32 RxRcvEnPi                               :  9;  // Bits 8:0
+    U32 RxDqsPPi                                :  6;  // Bits 14:9
+    U32 RxEq                                    :  5;  // Bits 19:15
+    U32 RxDqsNPi                                :  6;  // Bits 25:20
+    U32 RxVref                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATACH1_CR_RXTRAINRANK0_STRUCT;
+
+typedef union {
+  struct {
+    U32 RxRcvEnPi                               :  9;  // Bits 8:0
+    U32 RxDqsPPi                                :  6;  // Bits 14:9
+    U32 RxEq                                    :  5;  // Bits 19:15
+    U32 RxDqsNPi                                :  6;  // Bits 25:20
+    U32 RxVref                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATACH1_CR_RXTRAINRANK1_STRUCT;
+
+typedef union {
+  struct {
+    U32 RxRcvEnPi                               :  9;  // Bits 8:0
+    U32 RxDqsPPi                                :  6;  // Bits 14:9
+    U32 RxEq                                    :  5;  // Bits 19:15
+    U32 RxDqsNPi                                :  6;  // Bits 25:20
+    U32 RxVref                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATACH1_CR_RXTRAINRANK2_STRUCT;
+
+typedef union {
+  struct {
+    U32 RxRcvEnPi                               :  9;  // Bits 8:0
+    U32 RxDqsPPi                                :  6;  // Bits 14:9
+    U32 RxEq                                    :  5;  // Bits 19:15
+    U32 RxDqsNPi                                :  6;  // Bits 25:20
+    U32 RxVref                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATACH1_CR_RXTRAINRANK3_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATACH1_CR_RXPERBITRANK0_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATACH1_CR_RXPERBITRANK1_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATACH1_CR_RXPERBITRANK2_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATACH1_CR_RXPERBITRANK3_STRUCT;
+
+typedef union {
+  struct {
+    U32 TxDqDelay                               :  9;  // Bits 8:0
+    U32 TxDqsDelay                              :  9;  // Bits 17:9
+    U32 Spare0                                  :  2;  // Bits 19:18
+    U32 TxEqualization                          :  6;  // Bits 25:20
+    U32 Spare1                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATACH1_CR_TXTRAINRANK0_STRUCT;
+
+typedef union {
+  struct {
+    U32 TxDqDelay                               :  9;  // Bits 8:0
+    U32 TxDqsDelay                              :  9;  // Bits 17:9
+    U32 Spare0                                  :  2;  // Bits 19:18
+    U32 TxEqualization                          :  6;  // Bits 25:20
+    U32 Spare1                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATACH1_CR_TXTRAINRANK1_STRUCT;
+
+typedef union {
+  struct {
+    U32 TxDqDelay                               :  9;  // Bits 8:0
+    U32 TxDqsDelay                              :  9;  // Bits 17:9
+    U32 Spare0                                  :  2;  // Bits 19:18
+    U32 TxEqualization                          :  6;  // Bits 25:20
+    U32 Spare1                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATACH1_CR_TXTRAINRANK2_STRUCT;
+
+typedef union {
+  struct {
+    U32 TxDqDelay                               :  9;  // Bits 8:0
+    U32 TxDqsDelay                              :  9;  // Bits 17:9
+    U32 Spare0                                  :  2;  // Bits 19:18
+    U32 TxEqualization                          :  6;  // Bits 25:20
+    U32 Spare1                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATACH1_CR_TXTRAINRANK3_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATACH1_CR_TXPERBITRANK0_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATACH1_CR_TXPERBITRANK1_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATACH1_CR_TXPERBITRANK2_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATACH1_CR_TXPERBITRANK3_STRUCT;
+
+typedef union {
+  struct {
+    U32 RcompDrvUp                              :  6;  // Bits 5:0
+    U32 Spare0                                  :  3;  // Bits 8:6
+    U32 RcompDrvDown                            :  6;  // Bits 14:9
+    U32 VTComp                                  :  5;  // Bits 19:15
+    U32 TcoComp                                 :  6;  // Bits 25:20
+    U32 SlewRateComp                            :  5;  // Bits 30:26
+    U32 Spare2                                  :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATACH1_CR_RCOMPDATA0_STRUCT;
+
+typedef union {
+  struct {
+    U32 RcompOdtUp                              :  6;  // Bits 5:0
+    U32 Spare0                                  :  3;  // Bits 8:6
+    U32 RcompOdtDown                            :  6;  // Bits 14:9
+    U32 Spare1                                  :  1;  // Bits 15:15
+    U32 PanicDrvDn                              :  6;  // Bits 21:16
+    U32 PanicDrvUp                              :  6;  // Bits 27:22
+    U32 LevelShifterComp                        :  3;  // Bits 30:28
+    U32 Spare2                                  :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATACH1_CR_RCOMPDATA1_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATACH1_CR_TXXTALK_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATACH1_CR_RXOFFSETVDQ_STRUCT;
+
+typedef union {
+  struct {
+    U32 Spare                                   :  32;  // Bits 31:0
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATACH1_CR_DDRDATARESERVED_STRUCT;
+
+typedef union {
+  struct {
+    U32 DataTrainFeedback                       :  9;  // Bits 8:0
+    U32 Spare                                   :  23;  // Bits 31:9
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATACH1_CR_DATATRAINFEEDBACK_STRUCT;
+
+typedef union {
+  struct {
+    U32 RunTest                                 :  1;  // Bits 0:0
+    U32 Load                                    :  1;  // Bits 1:1
+    U32 ModeHVM                                 :  1;  // Bits 2:2
+    U32 ModeDV                                  :  1;  // Bits 3:3
+    U32 ModeADC                                 :  1;  // Bits 4:4
+    U32 LoadCount                               :  10;  // Bits 14:5
+    U32 CountStatus                             :  10;  // Bits 24:15
+    U32 Spare                                   :  7;  // Bits 31:25
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATACH1_CR_DLLPITESTANDADC_STRUCT;
+
+typedef union {
+  struct {
+    U32 DqDrvUpCompOffset                       :  6;  // Bits 5:0
+    U32 DqDrvDownCompOffset                     :  6;  // Bits 11:6
+    U32 DqOdtUpCompOffset                       :  5;  // Bits 16:12
+    U32 DqOdtDownCompOffset                     :  5;  // Bits 21:17
+    U32 DqTcoCompOffset                         :  5;  // Bits 26:22
+    U32 DqSlewRateCompOffset                    :  5;  // Bits 31:27
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATACH1_CR_DDRCRDATAOFFSETCOMP_STRUCT;
+
+typedef union {
+  struct {
+    U32 RefPi                                   :  4;  // Bits 3:0
+    U32 DllMask                                 :  2;  // Bits 5:4
+    U32 DllWeakLock                             :  1;  // Bits 6:6
+    U32 SdllSegmentDisable                      :  3;  // Bits 9:7
+    U32 RxBiasCtl                               :  3;  // Bits 12:10
+    U32 OdtDelay                                :  4;  // Bits 16:13
+    U32 OdtDuration                             :  3;  // Bits 19:17
+    U32 SenseAmpDelay                           :  4;  // Bits 23:20
+    U32 SenseAmpDuration                        :  3;  // Bits 26:24
+    U32 BurstEndODTDelay                        :  3;  // Bits 29:27
+    U32 LpDdrLongOdtEn                          :  1;  // Bits 30:30
+    U32 Rsvd1                                   :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATACH1_CR_DDRCRDATACONTROL1_STRUCT;
+
+typedef union {
+  struct {
+    U32 RxStaggerCtl                            :  5;  // Bits 4:0
+    U32 ForceBiasOn                             :  1;  // Bits 5:5
+    U32 ForceRxOn                               :  1;  // Bits 6:6
+    U32 LeakerComp                              :  2;  // Bits 8:7
+    U32 RxDqsAmpOffset                          :  4;  // Bits 12:9
+    U32 RxClkStgNum                             :  5;  // Bits 17:13
+    U32 WlLongDelEn                             :  1;  // Bits 18:18
+    U32 Spare                                   :  13;  // Bits 31:19
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATACH1_CR_DDRCRDATACONTROL2_STRUCT;
+
+typedef union {
+  struct {
+    U32 VssHiOrVrefCtl                          :  24;  // Bits 23:0
+    U32 OutputCode                              :  8;  // Bits 31:24
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATACH1_CR_DDRCRVSSHIORVREFCONTROL_STRUCT;
+
+typedef union {
+  struct {
+    U32 RcvEnOffset                             :  6;  // Bits 5:0
+    U32 RxDqsOffset                             :  6;  // Bits 11:6
+    U32 TxDqOffset                              :  6;  // Bits 17:12
+    U32 TxDqsOffset                             :  6;  // Bits 23:18
+    U32 VrefOffset                              :  7;  // Bits 30:24
+    U32 Spare                                   :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATACH1_CR_DDRCRDATAOFFSETTRAIN_STRUCT;
+
+typedef union {
+  struct {
+    U32 RxTrainingMode                          :  1;  // Bits 0:0
+    U32 WLTrainingMode                          :  1;  // Bits 1:1
+    U32 RLTrainingMode                          :  1;  // Bits 2:2
+    U32 SenseampTrainingMode                    :  1;  // Bits 3:3
+    U32 TxOn                                    :  1;  // Bits 4:4
+    U32 RfOn                                    :  1;  // Bits 5:5
+    U32 RxPiOn                                  :  1;  // Bits 6:6
+    U32 TxPiOn                                  :  1;  // Bits 7:7
+    U32 InternalClocksOn                        :  1;  // Bits 8:8
+    U32 RepeaterClocksOn                        :  1;  // Bits 9:9
+    U32 TxDisable                               :  1;  // Bits 10:10
+    U32 RxDisable                               :  1;  // Bits 11:11
+    U32 TxLong                                  :  1;  // Bits 12:12
+    U32 RxDqsCtle                               :  2;  // Bits 14:13
+    U32 RxReadPointer                           :  3;  // Bits 17:15
+    U32 DriverSegmentEnable                     :  1;  // Bits 18:18
+    U32 DataVccddqHi                            :  1;  // Bits 19:19
+    U32 ReadRFRd                                :  1;  // Bits 20:20
+    U32 ReadRFWr                                :  1;  // Bits 21:21
+    U32 ReadRFRank                              :  2;  // Bits 23:22
+    U32 ForceOdtOn                              :  1;  // Bits 24:24
+    U32 OdtSampOff                              :  1;  // Bits 25:25
+    U32 DisableOdtStatic                        :  1;  // Bits 26:26
+    U32 DdrCRForceODTOn                         :  1;  // Bits 27:27
+    U32 LPDDR_Mode                              :  1;  // Bits 28:28
+    U32 EnReadPreamble                          :  1;  // Bits 29:29
+    U32 OdtSampExtendEn                         :  1;  // Bits 30:30
+    U32 EarlyRleakEn                            :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATACH1_CR_DDRCRDATACONTROL0_STRUCT;
+
+typedef union {
+  struct {
+    U32 CAVrefCtl                               :  7;  // Bits 6:0
+    U32 Ch1VrefCtl                              :  7;  // Bits 13:7
+    U32 Ch0VrefCtl                              :  7;  // Bits 20:14
+    U32 EnDimmVrefCA                            :  1;  // Bits 21:21
+    U32 EnDimmVrefCh1                           :  1;  // Bits 22:22
+    U32 EnDimmVrefCh0                           :  1;  // Bits 23:23
+    U32 HiZTimerCtrl                            :  2;  // Bits 25:24
+    U32 VccddqHiQnnnH                           :  1;  // Bits 26:26
+    U32 Rsvd                                    :  2;  // Bits 28:27
+    U32 caSlowBW                                :  1;  // Bits 29:29
+    U32 ch0SlowBW                               :  1;  // Bits 30:30
+    U32 ch1SlowBW                               :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATACH1_CR_DDRCRVREFADJUST1_STRUCT;
+
+typedef union {
+  struct {
+    U32 RxRcvEnPi                               :  9;  // Bits 8:0
+    U32 RxDqsPPi                                :  6;  // Bits 14:9
+    U32 RxEq                                    :  5;  // Bits 19:15
+    U32 RxDqsNPi                                :  6;  // Bits 25:20
+    U32 RxVref                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA0CH0_CR_RXTRAINRANK0_STRUCT;
+
+typedef union {
+  struct {
+    U32 RxRcvEnPi                               :  9;  // Bits 8:0
+    U32 RxDqsPPi                                :  6;  // Bits 14:9
+    U32 RxEq                                    :  5;  // Bits 19:15
+    U32 RxDqsNPi                                :  6;  // Bits 25:20
+    U32 RxVref                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA0CH0_CR_RXTRAINRANK1_STRUCT;
+
+typedef union {
+  struct {
+    U32 RxRcvEnPi                               :  9;  // Bits 8:0
+    U32 RxDqsPPi                                :  6;  // Bits 14:9
+    U32 RxEq                                    :  5;  // Bits 19:15
+    U32 RxDqsNPi                                :  6;  // Bits 25:20
+    U32 RxVref                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA0CH0_CR_RXTRAINRANK2_STRUCT;
+
+typedef union {
+  struct {
+    U32 RxRcvEnPi                               :  9;  // Bits 8:0
+    U32 RxDqsPPi                                :  6;  // Bits 14:9
+    U32 RxEq                                    :  5;  // Bits 19:15
+    U32 RxDqsNPi                                :  6;  // Bits 25:20
+    U32 RxVref                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA0CH0_CR_RXTRAINRANK3_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA0CH0_CR_RXPERBITRANK0_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA0CH0_CR_RXPERBITRANK1_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA0CH0_CR_RXPERBITRANK2_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA0CH0_CR_RXPERBITRANK3_STRUCT;
+
+typedef union {
+  struct {
+    U32 TxDqDelay                               :  9;  // Bits 8:0
+    U32 TxDqsDelay                              :  9;  // Bits 17:9
+    U32 Spare0                                  :  2;  // Bits 19:18
+    U32 TxEqualization                          :  6;  // Bits 25:20
+    U32 Spare1                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA0CH0_CR_TXTRAINRANK0_STRUCT;
+
+typedef union {
+  struct {
+    U32 TxDqDelay                               :  9;  // Bits 8:0
+    U32 TxDqsDelay                              :  9;  // Bits 17:9
+    U32 Spare0                                  :  2;  // Bits 19:18
+    U32 TxEqualization                          :  6;  // Bits 25:20
+    U32 Spare1                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA0CH0_CR_TXTRAINRANK1_STRUCT;
+
+typedef union {
+  struct {
+    U32 TxDqDelay                               :  9;  // Bits 8:0
+    U32 TxDqsDelay                              :  9;  // Bits 17:9
+    U32 Spare0                                  :  2;  // Bits 19:18
+    U32 TxEqualization                          :  6;  // Bits 25:20
+    U32 Spare1                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA0CH0_CR_TXTRAINRANK2_STRUCT;
+
+typedef union {
+  struct {
+    U32 TxDqDelay                               :  9;  // Bits 8:0
+    U32 TxDqsDelay                              :  9;  // Bits 17:9
+    U32 Spare0                                  :  2;  // Bits 19:18
+    U32 TxEqualization                          :  6;  // Bits 25:20
+    U32 Spare1                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA0CH0_CR_TXTRAINRANK3_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA0CH0_CR_TXPERBITRANK0_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA0CH0_CR_TXPERBITRANK1_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA0CH0_CR_TXPERBITRANK2_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA0CH0_CR_TXPERBITRANK3_STRUCT;
+
+typedef union {
+  struct {
+    U32 RcompDrvUp                              :  6;  // Bits 5:0
+    U32 Spare0                                  :  3;  // Bits 8:6
+    U32 RcompDrvDown                            :  6;  // Bits 14:9
+    U32 VTComp                                  :  5;  // Bits 19:15
+    U32 TcoComp                                 :  6;  // Bits 25:20
+    U32 SlewRateComp                            :  5;  // Bits 30:26
+    U32 Spare2                                  :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA0CH0_CR_RCOMPDATA0_STRUCT;
+
+typedef union {
+  struct {
+    U32 RcompOdtUp                              :  6;  // Bits 5:0
+    U32 Spare0                                  :  3;  // Bits 8:6
+    U32 RcompOdtDown                            :  6;  // Bits 14:9
+    U32 Spare1                                  :  1;  // Bits 15:15
+    U32 PanicDrvDn                              :  6;  // Bits 21:16
+    U32 PanicDrvUp                              :  6;  // Bits 27:22
+    U32 LevelShifterComp                        :  3;  // Bits 30:28
+    U32 Spare2                                  :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA0CH0_CR_RCOMPDATA1_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA0CH0_CR_TXXTALK_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA0CH0_CR_RXOFFSETVDQ_STRUCT;
+
+typedef union {
+  struct {
+    U32 Spare                                   :  32;  // Bits 31:0
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA0CH0_CR_DDRDATARESERVED_STRUCT;
+
+typedef union {
+  struct {
+    U32 DataTrainFeedback                       :  9;  // Bits 8:0
+    U32 Spare                                   :  23;  // Bits 31:9
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA0CH0_CR_DATATRAINFEEDBACK_STRUCT;
+
+typedef union {
+  struct {
+    U32 RunTest                                 :  1;  // Bits 0:0
+    U32 Load                                    :  1;  // Bits 1:1
+    U32 ModeHVM                                 :  1;  // Bits 2:2
+    U32 ModeDV                                  :  1;  // Bits 3:3
+    U32 ModeADC                                 :  1;  // Bits 4:4
+    U32 LoadCount                               :  10;  // Bits 14:5
+    U32 CountStatus                             :  10;  // Bits 24:15
+    U32 Spare                                   :  7;  // Bits 31:25
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA0CH0_CR_DLLPITESTANDADC_STRUCT;
+
+typedef union {
+  struct {
+    U32 DqDrvUpCompOffset                       :  6;  // Bits 5:0
+    U32 DqDrvDownCompOffset                     :  6;  // Bits 11:6
+    U32 DqOdtUpCompOffset                       :  5;  // Bits 16:12
+    U32 DqOdtDownCompOffset                     :  5;  // Bits 21:17
+    U32 DqTcoCompOffset                         :  5;  // Bits 26:22
+    U32 DqSlewRateCompOffset                    :  5;  // Bits 31:27
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA0CH0_CR_DDRCRDATAOFFSETCOMP_STRUCT;
+
+typedef union {
+  struct {
+    U32 RefPi                                   :  4;  // Bits 3:0
+    U32 DllMask                                 :  2;  // Bits 5:4
+    U32 DllWeakLock                             :  1;  // Bits 6:6
+    U32 SdllSegmentDisable                      :  3;  // Bits 9:7
+    U32 RxBiasCtl                               :  3;  // Bits 12:10
+    U32 OdtDelay                                :  4;  // Bits 16:13
+    U32 OdtDuration                             :  3;  // Bits 19:17
+    U32 SenseAmpDelay                           :  4;  // Bits 23:20
+    U32 SenseAmpDuration                        :  3;  // Bits 26:24
+    U32 BurstEndODTDelay                        :  3;  // Bits 29:27
+    U32 LpDdrLongOdtEn                          :  1;  // Bits 30:30
+    U32 Rsvd1                                   :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA0CH0_CR_DDRCRDATACONTROL1_STRUCT;
+
+typedef union {
+  struct {
+    U32 RxStaggerCtl                            :  5;  // Bits 4:0
+    U32 ForceBiasOn                             :  1;  // Bits 5:5
+    U32 ForceRxOn                               :  1;  // Bits 6:6
+    U32 LeakerComp                              :  2;  // Bits 8:7
+    U32 RxDqsAmpOffset                          :  4;  // Bits 12:9
+    U32 RxClkStgNum                             :  5;  // Bits 17:13
+    U32 WlLongDelEn                             :  1;  // Bits 18:18
+    U32 Spare                                   :  13;  // Bits 31:19
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA0CH0_CR_DDRCRDATACONTROL2_STRUCT;
+
+typedef union {
+  struct {
+    U32 VssHiOrVrefCtl                          :  24;  // Bits 23:0
+    U32 OutputCode                              :  8;  // Bits 31:24
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA0CH0_CR_DDRCRVSSHIORVREFCONTROL_STRUCT;
+
+typedef union {
+  struct {
+    U32 RcvEnOffset                             :  6;  // Bits 5:0
+    U32 RxDqsOffset                             :  6;  // Bits 11:6
+    U32 TxDqOffset                              :  6;  // Bits 17:12
+    U32 TxDqsOffset                             :  6;  // Bits 23:18
+    U32 VrefOffset                              :  7;  // Bits 30:24
+    U32 Spare                                   :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA0CH0_CR_DDRCRDATAOFFSETTRAIN_STRUCT;
+
+typedef union {
+  struct {
+    U32 RxTrainingMode                          :  1;  // Bits 0:0
+    U32 WLTrainingMode                          :  1;  // Bits 1:1
+    U32 RLTrainingMode                          :  1;  // Bits 2:2
+    U32 SenseampTrainingMode                    :  1;  // Bits 3:3
+    U32 TxOn                                    :  1;  // Bits 4:4
+    U32 RfOn                                    :  1;  // Bits 5:5
+    U32 RxPiOn                                  :  1;  // Bits 6:6
+    U32 TxPiOn                                  :  1;  // Bits 7:7
+    U32 InternalClocksOn                        :  1;  // Bits 8:8
+    U32 RepeaterClocksOn                        :  1;  // Bits 9:9
+    U32 TxDisable                               :  1;  // Bits 10:10
+    U32 RxDisable                               :  1;  // Bits 11:11
+    U32 TxLong                                  :  1;  // Bits 12:12
+    U32 RxDqsCtle                               :  2;  // Bits 14:13
+    U32 RxReadPointer                           :  3;  // Bits 17:15
+    U32 DriverSegmentEnable                     :  1;  // Bits 18:18
+    U32 DataVccddqHi                            :  1;  // Bits 19:19
+    U32 ReadRFRd                                :  1;  // Bits 20:20
+    U32 ReadRFWr                                :  1;  // Bits 21:21
+    U32 ReadRFRank                              :  2;  // Bits 23:22
+    U32 ForceOdtOn                              :  1;  // Bits 24:24
+    U32 OdtSampOff                              :  1;  // Bits 25:25
+    U32 DisableOdtStatic                        :  1;  // Bits 26:26
+    U32 DdrCRForceODTOn                         :  1;  // Bits 27:27
+    U32 LPDDR_Mode                              :  1;  // Bits 28:28
+    U32 EnReadPreamble                          :  1;  // Bits 29:29
+    U32 OdtSampExtendEn                         :  1;  // Bits 30:30
+    U32 EarlyRleakEn                            :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA0CH0_CR_DDRCRDATACONTROL0_STRUCT;
+
+typedef union {
+  struct {
+    U32 CAVrefCtl                               :  7;  // Bits 6:0
+    U32 Ch1VrefCtl                              :  7;  // Bits 13:7
+    U32 Ch0VrefCtl                              :  7;  // Bits 20:14
+    U32 EnDimmVrefCA                            :  1;  // Bits 21:21
+    U32 EnDimmVrefCh1                           :  1;  // Bits 22:22
+    U32 EnDimmVrefCh0                           :  1;  // Bits 23:23
+    U32 HiZTimerCtrl                            :  2;  // Bits 25:24
+    U32 VccddqHiQnnnH                           :  1;  // Bits 26:26
+    U32 Rsvd                                    :  2;  // Bits 28:27
+    U32 caSlowBW                                :  1;  // Bits 29:29
+    U32 ch0SlowBW                               :  1;  // Bits 30:30
+    U32 ch1SlowBW                               :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA0CH0_CR_DDRCRVREFADJUST1_STRUCT;
+
+typedef union {
+  struct {
+    U32 RxRcvEnPi                               :  9;  // Bits 8:0
+    U32 RxDqsPPi                                :  6;  // Bits 14:9
+    U32 RxEq                                    :  5;  // Bits 19:15
+    U32 RxDqsNPi                                :  6;  // Bits 25:20
+    U32 RxVref                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA0CH1_CR_RXTRAINRANK0_STRUCT;
+
+typedef union {
+  struct {
+    U32 RxRcvEnPi                               :  9;  // Bits 8:0
+    U32 RxDqsPPi                                :  6;  // Bits 14:9
+    U32 RxEq                                    :  5;  // Bits 19:15
+    U32 RxDqsNPi                                :  6;  // Bits 25:20
+    U32 RxVref                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA0CH1_CR_RXTRAINRANK1_STRUCT;
+
+typedef union {
+  struct {
+    U32 RxRcvEnPi                               :  9;  // Bits 8:0
+    U32 RxDqsPPi                                :  6;  // Bits 14:9
+    U32 RxEq                                    :  5;  // Bits 19:15
+    U32 RxDqsNPi                                :  6;  // Bits 25:20
+    U32 RxVref                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA0CH1_CR_RXTRAINRANK2_STRUCT;
+
+typedef union {
+  struct {
+    U32 RxRcvEnPi                               :  9;  // Bits 8:0
+    U32 RxDqsPPi                                :  6;  // Bits 14:9
+    U32 RxEq                                    :  5;  // Bits 19:15
+    U32 RxDqsNPi                                :  6;  // Bits 25:20
+    U32 RxVref                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA0CH1_CR_RXTRAINRANK3_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA0CH1_CR_RXPERBITRANK0_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA0CH1_CR_RXPERBITRANK1_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA0CH1_CR_RXPERBITRANK2_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA0CH1_CR_RXPERBITRANK3_STRUCT;
+
+typedef union {
+  struct {
+    U32 TxDqDelay                               :  9;  // Bits 8:0
+    U32 TxDqsDelay                              :  9;  // Bits 17:9
+    U32 Spare0                                  :  2;  // Bits 19:18
+    U32 TxEqualization                          :  6;  // Bits 25:20
+    U32 Spare1                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA0CH1_CR_TXTRAINRANK0_STRUCT;
+
+typedef union {
+  struct {
+    U32 TxDqDelay                               :  9;  // Bits 8:0
+    U32 TxDqsDelay                              :  9;  // Bits 17:9
+    U32 Spare0                                  :  2;  // Bits 19:18
+    U32 TxEqualization                          :  6;  // Bits 25:20
+    U32 Spare1                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA0CH1_CR_TXTRAINRANK1_STRUCT;
+
+typedef union {
+  struct {
+    U32 TxDqDelay                               :  9;  // Bits 8:0
+    U32 TxDqsDelay                              :  9;  // Bits 17:9
+    U32 Spare0                                  :  2;  // Bits 19:18
+    U32 TxEqualization                          :  6;  // Bits 25:20
+    U32 Spare1                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA0CH1_CR_TXTRAINRANK2_STRUCT;
+
+typedef union {
+  struct {
+    U32 TxDqDelay                               :  9;  // Bits 8:0
+    U32 TxDqsDelay                              :  9;  // Bits 17:9
+    U32 Spare0                                  :  2;  // Bits 19:18
+    U32 TxEqualization                          :  6;  // Bits 25:20
+    U32 Spare1                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA0CH1_CR_TXTRAINRANK3_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA0CH1_CR_TXPERBITRANK0_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA0CH1_CR_TXPERBITRANK1_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA0CH1_CR_TXPERBITRANK2_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA0CH1_CR_TXPERBITRANK3_STRUCT;
+
+typedef union {
+  struct {
+    U32 RcompDrvUp                              :  6;  // Bits 5:0
+    U32 Spare0                                  :  3;  // Bits 8:6
+    U32 RcompDrvDown                            :  6;  // Bits 14:9
+    U32 VTComp                                  :  5;  // Bits 19:15
+    U32 TcoComp                                 :  6;  // Bits 25:20
+    U32 SlewRateComp                            :  5;  // Bits 30:26
+    U32 Spare2                                  :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA0CH1_CR_RCOMPDATA0_STRUCT;
+
+typedef union {
+  struct {
+    U32 RcompOdtUp                              :  6;  // Bits 5:0
+    U32 Spare0                                  :  3;  // Bits 8:6
+    U32 RcompOdtDown                            :  6;  // Bits 14:9
+    U32 Spare1                                  :  1;  // Bits 15:15
+    U32 PanicDrvDn                              :  6;  // Bits 21:16
+    U32 PanicDrvUp                              :  6;  // Bits 27:22
+    U32 LevelShifterComp                        :  3;  // Bits 30:28
+    U32 Spare2                                  :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA0CH1_CR_RCOMPDATA1_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA0CH1_CR_TXXTALK_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA0CH1_CR_RXOFFSETVDQ_STRUCT;
+
+typedef union {
+  struct {
+    U32 Spare                                   :  32;  // Bits 31:0
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA0CH1_CR_DDRDATARESERVED_STRUCT;
+
+typedef union {
+  struct {
+    U32 DataTrainFeedback                       :  9;  // Bits 8:0
+    U32 Spare                                   :  23;  // Bits 31:9
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA0CH1_CR_DATATRAINFEEDBACK_STRUCT;
+
+typedef union {
+  struct {
+    U32 RunTest                                 :  1;  // Bits 0:0
+    U32 Load                                    :  1;  // Bits 1:1
+    U32 ModeHVM                                 :  1;  // Bits 2:2
+    U32 ModeDV                                  :  1;  // Bits 3:3
+    U32 ModeADC                                 :  1;  // Bits 4:4
+    U32 LoadCount                               :  10;  // Bits 14:5
+    U32 CountStatus                             :  10;  // Bits 24:15
+    U32 Spare                                   :  7;  // Bits 31:25
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA0CH1_CR_DLLPITESTANDADC_STRUCT;
+
+typedef union {
+  struct {
+    U32 DqDrvUpCompOffset                       :  6;  // Bits 5:0
+    U32 DqDrvDownCompOffset                     :  6;  // Bits 11:6
+    U32 DqOdtUpCompOffset                       :  5;  // Bits 16:12
+    U32 DqOdtDownCompOffset                     :  5;  // Bits 21:17
+    U32 DqTcoCompOffset                         :  5;  // Bits 26:22
+    U32 DqSlewRateCompOffset                    :  5;  // Bits 31:27
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA0CH1_CR_DDRCRDATAOFFSETCOMP_STRUCT;
+
+typedef union {
+  struct {
+    U32 RefPi                                   :  4;  // Bits 3:0
+    U32 DllMask                                 :  2;  // Bits 5:4
+    U32 DllWeakLock                             :  1;  // Bits 6:6
+    U32 SdllSegmentDisable                      :  3;  // Bits 9:7
+    U32 RxBiasCtl                               :  3;  // Bits 12:10
+    U32 OdtDelay                                :  4;  // Bits 16:13
+    U32 OdtDuration                             :  3;  // Bits 19:17
+    U32 SenseAmpDelay                           :  4;  // Bits 23:20
+    U32 SenseAmpDuration                        :  3;  // Bits 26:24
+    U32 BurstEndODTDelay                        :  3;  // Bits 29:27
+    U32 LpDdrLongOdtEn                          :  1;  // Bits 30:30
+    U32 Rsvd1                                   :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA0CH1_CR_DDRCRDATACONTROL1_STRUCT;
+
+typedef union {
+  struct {
+    U32 RxStaggerCtl                            :  5;  // Bits 4:0
+    U32 ForceBiasOn                             :  1;  // Bits 5:5
+    U32 ForceRxOn                               :  1;  // Bits 6:6
+    U32 LeakerComp                              :  2;  // Bits 8:7
+    U32 RxDqsAmpOffset                          :  4;  // Bits 12:9
+    U32 RxClkStgNum                             :  5;  // Bits 17:13
+    U32 WlLongDelEn                             :  1;  // Bits 18:18
+    U32 Spare                                   :  13;  // Bits 31:19
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA0CH1_CR_DDRCRDATACONTROL2_STRUCT;
+
+typedef union {
+  struct {
+    U32 VssHiOrVrefCtl                          :  24;  // Bits 23:0
+    U32 OutputCode                              :  8;  // Bits 31:24
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA0CH1_CR_DDRCRVSSHIORVREFCONTROL_STRUCT;
+
+typedef union {
+  struct {
+    U32 RcvEnOffset                             :  6;  // Bits 5:0
+    U32 RxDqsOffset                             :  6;  // Bits 11:6
+    U32 TxDqOffset                              :  6;  // Bits 17:12
+    U32 TxDqsOffset                             :  6;  // Bits 23:18
+    U32 VrefOffset                              :  7;  // Bits 30:24
+    U32 Spare                                   :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA0CH1_CR_DDRCRDATAOFFSETTRAIN_STRUCT;
+
+typedef union {
+  struct {
+    U32 RxTrainingMode                          :  1;  // Bits 0:0
+    U32 WLTrainingMode                          :  1;  // Bits 1:1
+    U32 RLTrainingMode                          :  1;  // Bits 2:2
+    U32 SenseampTrainingMode                    :  1;  // Bits 3:3
+    U32 TxOn                                    :  1;  // Bits 4:4
+    U32 RfOn                                    :  1;  // Bits 5:5
+    U32 RxPiOn                                  :  1;  // Bits 6:6
+    U32 TxPiOn                                  :  1;  // Bits 7:7
+    U32 InternalClocksOn                        :  1;  // Bits 8:8
+    U32 RepeaterClocksOn                        :  1;  // Bits 9:9
+    U32 TxDisable                               :  1;  // Bits 10:10
+    U32 RxDisable                               :  1;  // Bits 11:11
+    U32 TxLong                                  :  1;  // Bits 12:12
+    U32 RxDqsCtle                               :  2;  // Bits 14:13
+    U32 RxReadPointer                           :  3;  // Bits 17:15
+    U32 DriverSegmentEnable                     :  1;  // Bits 18:18
+    U32 DataVccddqHi                            :  1;  // Bits 19:19
+    U32 ReadRFRd                                :  1;  // Bits 20:20
+    U32 ReadRFWr                                :  1;  // Bits 21:21
+    U32 ReadRFRank                              :  2;  // Bits 23:22
+    U32 ForceOdtOn                              :  1;  // Bits 24:24
+    U32 OdtSampOff                              :  1;  // Bits 25:25
+    U32 DisableOdtStatic                        :  1;  // Bits 26:26
+    U32 DdrCRForceODTOn                         :  1;  // Bits 27:27
+    U32 LPDDR_Mode                              :  1;  // Bits 28:28
+    U32 EnReadPreamble                          :  1;  // Bits 29:29
+    U32 OdtSampExtendEn                         :  1;  // Bits 30:30
+    U32 EarlyRleakEn                            :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA0CH1_CR_DDRCRDATACONTROL0_STRUCT;
+
+typedef union {
+  struct {
+    U32 CAVrefCtl                               :  7;  // Bits 6:0
+    U32 Ch1VrefCtl                              :  7;  // Bits 13:7
+    U32 Ch0VrefCtl                              :  7;  // Bits 20:14
+    U32 EnDimmVrefCA                            :  1;  // Bits 21:21
+    U32 EnDimmVrefCh1                           :  1;  // Bits 22:22
+    U32 EnDimmVrefCh0                           :  1;  // Bits 23:23
+    U32 HiZTimerCtrl                            :  2;  // Bits 25:24
+    U32 VccddqHiQnnnH                           :  1;  // Bits 26:26
+    U32 Rsvd                                    :  2;  // Bits 28:27
+    U32 caSlowBW                                :  1;  // Bits 29:29
+    U32 ch0SlowBW                               :  1;  // Bits 30:30
+    U32 ch1SlowBW                               :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA0CH1_CR_DDRCRVREFADJUST1_STRUCT;
+
+typedef union {
+  struct {
+    U32 RxRcvEnPi                               :  9;  // Bits 8:0
+    U32 RxDqsPPi                                :  6;  // Bits 14:9
+    U32 RxEq                                    :  5;  // Bits 19:15
+    U32 RxDqsNPi                                :  6;  // Bits 25:20
+    U32 RxVref                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA1CH0_CR_RXTRAINRANK0_STRUCT;
+
+typedef union {
+  struct {
+    U32 RxRcvEnPi                               :  9;  // Bits 8:0
+    U32 RxDqsPPi                                :  6;  // Bits 14:9
+    U32 RxEq                                    :  5;  // Bits 19:15
+    U32 RxDqsNPi                                :  6;  // Bits 25:20
+    U32 RxVref                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA1CH0_CR_RXTRAINRANK1_STRUCT;
+
+typedef union {
+  struct {
+    U32 RxRcvEnPi                               :  9;  // Bits 8:0
+    U32 RxDqsPPi                                :  6;  // Bits 14:9
+    U32 RxEq                                    :  5;  // Bits 19:15
+    U32 RxDqsNPi                                :  6;  // Bits 25:20
+    U32 RxVref                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA1CH0_CR_RXTRAINRANK2_STRUCT;
+
+typedef union {
+  struct {
+    U32 RxRcvEnPi                               :  9;  // Bits 8:0
+    U32 RxDqsPPi                                :  6;  // Bits 14:9
+    U32 RxEq                                    :  5;  // Bits 19:15
+    U32 RxDqsNPi                                :  6;  // Bits 25:20
+    U32 RxVref                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA1CH0_CR_RXTRAINRANK3_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA1CH0_CR_RXPERBITRANK0_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA1CH0_CR_RXPERBITRANK1_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA1CH0_CR_RXPERBITRANK2_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA1CH0_CR_RXPERBITRANK3_STRUCT;
+
+typedef union {
+  struct {
+    U32 TxDqDelay                               :  9;  // Bits 8:0
+    U32 TxDqsDelay                              :  9;  // Bits 17:9
+    U32 Spare0                                  :  2;  // Bits 19:18
+    U32 TxEqualization                          :  6;  // Bits 25:20
+    U32 Spare1                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA1CH0_CR_TXTRAINRANK0_STRUCT;
+
+typedef union {
+  struct {
+    U32 TxDqDelay                               :  9;  // Bits 8:0
+    U32 TxDqsDelay                              :  9;  // Bits 17:9
+    U32 Spare0                                  :  2;  // Bits 19:18
+    U32 TxEqualization                          :  6;  // Bits 25:20
+    U32 Spare1                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA1CH0_CR_TXTRAINRANK1_STRUCT;
+
+typedef union {
+  struct {
+    U32 TxDqDelay                               :  9;  // Bits 8:0
+    U32 TxDqsDelay                              :  9;  // Bits 17:9
+    U32 Spare0                                  :  2;  // Bits 19:18
+    U32 TxEqualization                          :  6;  // Bits 25:20
+    U32 Spare1                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA1CH0_CR_TXTRAINRANK2_STRUCT;
+
+typedef union {
+  struct {
+    U32 TxDqDelay                               :  9;  // Bits 8:0
+    U32 TxDqsDelay                              :  9;  // Bits 17:9
+    U32 Spare0                                  :  2;  // Bits 19:18
+    U32 TxEqualization                          :  6;  // Bits 25:20
+    U32 Spare1                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA1CH0_CR_TXTRAINRANK3_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA1CH0_CR_TXPERBITRANK0_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA1CH0_CR_TXPERBITRANK1_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA1CH0_CR_TXPERBITRANK2_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA1CH0_CR_TXPERBITRANK3_STRUCT;
+
+typedef union {
+  struct {
+    U32 RcompDrvUp                              :  6;  // Bits 5:0
+    U32 Spare0                                  :  3;  // Bits 8:6
+    U32 RcompDrvDown                            :  6;  // Bits 14:9
+    U32 VTComp                                  :  5;  // Bits 19:15
+    U32 TcoComp                                 :  6;  // Bits 25:20
+    U32 SlewRateComp                            :  5;  // Bits 30:26
+    U32 Spare2                                  :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA1CH0_CR_RCOMPDATA0_STRUCT;
+
+typedef union {
+  struct {
+    U32 RcompOdtUp                              :  6;  // Bits 5:0
+    U32 Spare0                                  :  3;  // Bits 8:6
+    U32 RcompOdtDown                            :  6;  // Bits 14:9
+    U32 Spare1                                  :  1;  // Bits 15:15
+    U32 PanicDrvDn                              :  6;  // Bits 21:16
+    U32 PanicDrvUp                              :  6;  // Bits 27:22
+    U32 LevelShifterComp                        :  3;  // Bits 30:28
+    U32 Spare2                                  :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA1CH0_CR_RCOMPDATA1_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA1CH0_CR_TXXTALK_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA1CH0_CR_RXOFFSETVDQ_STRUCT;
+
+typedef union {
+  struct {
+    U32 Spare                                   :  32;  // Bits 31:0
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA1CH0_CR_DDRDATARESERVED_STRUCT;
+
+typedef union {
+  struct {
+    U32 DataTrainFeedback                       :  9;  // Bits 8:0
+    U32 Spare                                   :  23;  // Bits 31:9
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA1CH0_CR_DATATRAINFEEDBACK_STRUCT;
+
+typedef union {
+  struct {
+    U32 RunTest                                 :  1;  // Bits 0:0
+    U32 Load                                    :  1;  // Bits 1:1
+    U32 ModeHVM                                 :  1;  // Bits 2:2
+    U32 ModeDV                                  :  1;  // Bits 3:3
+    U32 ModeADC                                 :  1;  // Bits 4:4
+    U32 LoadCount                               :  10;  // Bits 14:5
+    U32 CountStatus                             :  10;  // Bits 24:15
+    U32 Spare                                   :  7;  // Bits 31:25
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA1CH0_CR_DLLPITESTANDADC_STRUCT;
+
+typedef union {
+  struct {
+    U32 DqDrvUpCompOffset                       :  6;  // Bits 5:0
+    U32 DqDrvDownCompOffset                     :  6;  // Bits 11:6
+    U32 DqOdtUpCompOffset                       :  5;  // Bits 16:12
+    U32 DqOdtDownCompOffset                     :  5;  // Bits 21:17
+    U32 DqTcoCompOffset                         :  5;  // Bits 26:22
+    U32 DqSlewRateCompOffset                    :  5;  // Bits 31:27
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA1CH0_CR_DDRCRDATAOFFSETCOMP_STRUCT;
+
+typedef union {
+  struct {
+    U32 RefPi                                   :  4;  // Bits 3:0
+    U32 DllMask                                 :  2;  // Bits 5:4
+    U32 DllWeakLock                             :  1;  // Bits 6:6
+    U32 SdllSegmentDisable                      :  3;  // Bits 9:7
+    U32 RxBiasCtl                               :  3;  // Bits 12:10
+    U32 OdtDelay                                :  4;  // Bits 16:13
+    U32 OdtDuration                             :  3;  // Bits 19:17
+    U32 SenseAmpDelay                           :  4;  // Bits 23:20
+    U32 SenseAmpDuration                        :  3;  // Bits 26:24
+    U32 BurstEndODTDelay                        :  3;  // Bits 29:27
+    U32 LpDdrLongOdtEn                          :  1;  // Bits 30:30
+    U32 Rsvd1                                   :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA1CH0_CR_DDRCRDATACONTROL1_STRUCT;
+
+typedef union {
+  struct {
+    U32 RxStaggerCtl                            :  5;  // Bits 4:0
+    U32 ForceBiasOn                             :  1;  // Bits 5:5
+    U32 ForceRxOn                               :  1;  // Bits 6:6
+    U32 LeakerComp                              :  2;  // Bits 8:7
+    U32 RxDqsAmpOffset                          :  4;  // Bits 12:9
+    U32 RxClkStgNum                             :  5;  // Bits 17:13
+    U32 WlLongDelEn                             :  1;  // Bits 18:18
+    U32 Spare                                   :  13;  // Bits 31:19
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA1CH0_CR_DDRCRDATACONTROL2_STRUCT;
+
+typedef union {
+  struct {
+    U32 VssHiOrVrefCtl                          :  24;  // Bits 23:0
+    U32 OutputCode                              :  8;  // Bits 31:24
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA1CH0_CR_DDRCRVSSHIORVREFCONTROL_STRUCT;
+
+typedef union {
+  struct {
+    U32 RcvEnOffset                             :  6;  // Bits 5:0
+    U32 RxDqsOffset                             :  6;  // Bits 11:6
+    U32 TxDqOffset                              :  6;  // Bits 17:12
+    U32 TxDqsOffset                             :  6;  // Bits 23:18
+    U32 VrefOffset                              :  7;  // Bits 30:24
+    U32 Spare                                   :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA1CH0_CR_DDRCRDATAOFFSETTRAIN_STRUCT;
+
+typedef union {
+  struct {
+    U32 RxTrainingMode                          :  1;  // Bits 0:0
+    U32 WLTrainingMode                          :  1;  // Bits 1:1
+    U32 RLTrainingMode                          :  1;  // Bits 2:2
+    U32 SenseampTrainingMode                    :  1;  // Bits 3:3
+    U32 TxOn                                    :  1;  // Bits 4:4
+    U32 RfOn                                    :  1;  // Bits 5:5
+    U32 RxPiOn                                  :  1;  // Bits 6:6
+    U32 TxPiOn                                  :  1;  // Bits 7:7
+    U32 InternalClocksOn                        :  1;  // Bits 8:8
+    U32 RepeaterClocksOn                        :  1;  // Bits 9:9
+    U32 TxDisable                               :  1;  // Bits 10:10
+    U32 RxDisable                               :  1;  // Bits 11:11
+    U32 TxLong                                  :  1;  // Bits 12:12
+    U32 RxDqsCtle                               :  2;  // Bits 14:13
+    U32 RxReadPointer                           :  3;  // Bits 17:15
+    U32 DriverSegmentEnable                     :  1;  // Bits 18:18
+    U32 DataVccddqHi                            :  1;  // Bits 19:19
+    U32 ReadRFRd                                :  1;  // Bits 20:20
+    U32 ReadRFWr                                :  1;  // Bits 21:21
+    U32 ReadRFRank                              :  2;  // Bits 23:22
+    U32 ForceOdtOn                              :  1;  // Bits 24:24
+    U32 OdtSampOff                              :  1;  // Bits 25:25
+    U32 DisableOdtStatic                        :  1;  // Bits 26:26
+    U32 DdrCRForceODTOn                         :  1;  // Bits 27:27
+    U32 LPDDR_Mode                              :  1;  // Bits 28:28
+    U32 EnReadPreamble                          :  1;  // Bits 29:29
+    U32 OdtSampExtendEn                         :  1;  // Bits 30:30
+    U32 EarlyRleakEn                            :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA1CH0_CR_DDRCRDATACONTROL0_STRUCT;
+
+typedef union {
+  struct {
+    U32 CAVrefCtl                               :  7;  // Bits 6:0
+    U32 Ch1VrefCtl                              :  7;  // Bits 13:7
+    U32 Ch0VrefCtl                              :  7;  // Bits 20:14
+    U32 EnDimmVrefCA                            :  1;  // Bits 21:21
+    U32 EnDimmVrefCh1                           :  1;  // Bits 22:22
+    U32 EnDimmVrefCh0                           :  1;  // Bits 23:23
+    U32 HiZTimerCtrl                            :  2;  // Bits 25:24
+    U32 VccddqHiQnnnH                           :  1;  // Bits 26:26
+    U32 Rsvd                                    :  2;  // Bits 28:27
+    U32 caSlowBW                                :  1;  // Bits 29:29
+    U32 ch0SlowBW                               :  1;  // Bits 30:30
+    U32 ch1SlowBW                               :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA1CH0_CR_DDRCRVREFADJUST1_STRUCT;
+
+typedef union {
+  struct {
+    U32 RxRcvEnPi                               :  9;  // Bits 8:0
+    U32 RxDqsPPi                                :  6;  // Bits 14:9
+    U32 RxEq                                    :  5;  // Bits 19:15
+    U32 RxDqsNPi                                :  6;  // Bits 25:20
+    U32 RxVref                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA1CH1_CR_RXTRAINRANK0_STRUCT;
+
+typedef union {
+  struct {
+    U32 RxRcvEnPi                               :  9;  // Bits 8:0
+    U32 RxDqsPPi                                :  6;  // Bits 14:9
+    U32 RxEq                                    :  5;  // Bits 19:15
+    U32 RxDqsNPi                                :  6;  // Bits 25:20
+    U32 RxVref                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA1CH1_CR_RXTRAINRANK1_STRUCT;
+
+typedef union {
+  struct {
+    U32 RxRcvEnPi                               :  9;  // Bits 8:0
+    U32 RxDqsPPi                                :  6;  // Bits 14:9
+    U32 RxEq                                    :  5;  // Bits 19:15
+    U32 RxDqsNPi                                :  6;  // Bits 25:20
+    U32 RxVref                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA1CH1_CR_RXTRAINRANK2_STRUCT;
+
+typedef union {
+  struct {
+    U32 RxRcvEnPi                               :  9;  // Bits 8:0
+    U32 RxDqsPPi                                :  6;  // Bits 14:9
+    U32 RxEq                                    :  5;  // Bits 19:15
+    U32 RxDqsNPi                                :  6;  // Bits 25:20
+    U32 RxVref                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA1CH1_CR_RXTRAINRANK3_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA1CH1_CR_RXPERBITRANK0_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA1CH1_CR_RXPERBITRANK1_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA1CH1_CR_RXPERBITRANK2_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA1CH1_CR_RXPERBITRANK3_STRUCT;
+
+typedef union {
+  struct {
+    U32 TxDqDelay                               :  9;  // Bits 8:0
+    U32 TxDqsDelay                              :  9;  // Bits 17:9
+    U32 Spare0                                  :  2;  // Bits 19:18
+    U32 TxEqualization                          :  6;  // Bits 25:20
+    U32 Spare1                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA1CH1_CR_TXTRAINRANK0_STRUCT;
+
+typedef union {
+  struct {
+    U32 TxDqDelay                               :  9;  // Bits 8:0
+    U32 TxDqsDelay                              :  9;  // Bits 17:9
+    U32 Spare0                                  :  2;  // Bits 19:18
+    U32 TxEqualization                          :  6;  // Bits 25:20
+    U32 Spare1                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA1CH1_CR_TXTRAINRANK1_STRUCT;
+
+typedef union {
+  struct {
+    U32 TxDqDelay                               :  9;  // Bits 8:0
+    U32 TxDqsDelay                              :  9;  // Bits 17:9
+    U32 Spare0                                  :  2;  // Bits 19:18
+    U32 TxEqualization                          :  6;  // Bits 25:20
+    U32 Spare1                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA1CH1_CR_TXTRAINRANK2_STRUCT;
+
+typedef union {
+  struct {
+    U32 TxDqDelay                               :  9;  // Bits 8:0
+    U32 TxDqsDelay                              :  9;  // Bits 17:9
+    U32 Spare0                                  :  2;  // Bits 19:18
+    U32 TxEqualization                          :  6;  // Bits 25:20
+    U32 Spare1                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA1CH1_CR_TXTRAINRANK3_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA1CH1_CR_TXPERBITRANK0_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA1CH1_CR_TXPERBITRANK1_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA1CH1_CR_TXPERBITRANK2_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA1CH1_CR_TXPERBITRANK3_STRUCT;
+
+typedef union {
+  struct {
+    U32 RcompDrvUp                              :  6;  // Bits 5:0
+    U32 Spare0                                  :  3;  // Bits 8:6
+    U32 RcompDrvDown                            :  6;  // Bits 14:9
+    U32 VTComp                                  :  5;  // Bits 19:15
+    U32 TcoComp                                 :  6;  // Bits 25:20
+    U32 SlewRateComp                            :  5;  // Bits 30:26
+    U32 Spare2                                  :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA1CH1_CR_RCOMPDATA0_STRUCT;
+
+typedef union {
+  struct {
+    U32 RcompOdtUp                              :  6;  // Bits 5:0
+    U32 Spare0                                  :  3;  // Bits 8:6
+    U32 RcompOdtDown                            :  6;  // Bits 14:9
+    U32 Spare1                                  :  1;  // Bits 15:15
+    U32 PanicDrvDn                              :  6;  // Bits 21:16
+    U32 PanicDrvUp                              :  6;  // Bits 27:22
+    U32 LevelShifterComp                        :  3;  // Bits 30:28
+    U32 Spare2                                  :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA1CH1_CR_RCOMPDATA1_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA1CH1_CR_TXXTALK_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA1CH1_CR_RXOFFSETVDQ_STRUCT;
+
+typedef union {
+  struct {
+    U32 Spare                                   :  32;  // Bits 31:0
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA1CH1_CR_DDRDATARESERVED_STRUCT;
+
+typedef union {
+  struct {
+    U32 DataTrainFeedback                       :  9;  // Bits 8:0
+    U32 Spare                                   :  23;  // Bits 31:9
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA1CH1_CR_DATATRAINFEEDBACK_STRUCT;
+
+typedef union {
+  struct {
+    U32 RunTest                                 :  1;  // Bits 0:0
+    U32 Load                                    :  1;  // Bits 1:1
+    U32 ModeHVM                                 :  1;  // Bits 2:2
+    U32 ModeDV                                  :  1;  // Bits 3:3
+    U32 ModeADC                                 :  1;  // Bits 4:4
+    U32 LoadCount                               :  10;  // Bits 14:5
+    U32 CountStatus                             :  10;  // Bits 24:15
+    U32 Spare                                   :  7;  // Bits 31:25
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA1CH1_CR_DLLPITESTANDADC_STRUCT;
+
+typedef union {
+  struct {
+    U32 DqDrvUpCompOffset                       :  6;  // Bits 5:0
+    U32 DqDrvDownCompOffset                     :  6;  // Bits 11:6
+    U32 DqOdtUpCompOffset                       :  5;  // Bits 16:12
+    U32 DqOdtDownCompOffset                     :  5;  // Bits 21:17
+    U32 DqTcoCompOffset                         :  5;  // Bits 26:22
+    U32 DqSlewRateCompOffset                    :  5;  // Bits 31:27
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA1CH1_CR_DDRCRDATAOFFSETCOMP_STRUCT;
+
+typedef union {
+  struct {
+    U32 RefPi                                   :  4;  // Bits 3:0
+    U32 DllMask                                 :  2;  // Bits 5:4
+    U32 DllWeakLock                             :  1;  // Bits 6:6
+    U32 SdllSegmentDisable                      :  3;  // Bits 9:7
+    U32 RxBiasCtl                               :  3;  // Bits 12:10
+    U32 OdtDelay                                :  4;  // Bits 16:13
+    U32 OdtDuration                             :  3;  // Bits 19:17
+    U32 SenseAmpDelay                           :  4;  // Bits 23:20
+    U32 SenseAmpDuration                        :  3;  // Bits 26:24
+    U32 BurstEndODTDelay                        :  3;  // Bits 29:27
+    U32 LpDdrLongOdtEn                          :  1;  // Bits 30:30
+    U32 Rsvd1                                   :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA1CH1_CR_DDRCRDATACONTROL1_STRUCT;
+
+typedef union {
+  struct {
+    U32 RxStaggerCtl                            :  5;  // Bits 4:0
+    U32 ForceBiasOn                             :  1;  // Bits 5:5
+    U32 ForceRxOn                               :  1;  // Bits 6:6
+    U32 LeakerComp                              :  2;  // Bits 8:7
+    U32 RxDqsAmpOffset                          :  4;  // Bits 12:9
+    U32 RxClkStgNum                             :  5;  // Bits 17:13
+    U32 WlLongDelEn                             :  1;  // Bits 18:18
+    U32 Spare                                   :  13;  // Bits 31:19
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA1CH1_CR_DDRCRDATACONTROL2_STRUCT;
+
+typedef union {
+  struct {
+    U32 VssHiOrVrefCtl                          :  24;  // Bits 23:0
+    U32 OutputCode                              :  8;  // Bits 31:24
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA1CH1_CR_DDRCRVSSHIORVREFCONTROL_STRUCT;
+
+typedef union {
+  struct {
+    U32 RcvEnOffset                             :  6;  // Bits 5:0
+    U32 RxDqsOffset                             :  6;  // Bits 11:6
+    U32 TxDqOffset                              :  6;  // Bits 17:12
+    U32 TxDqsOffset                             :  6;  // Bits 23:18
+    U32 VrefOffset                              :  7;  // Bits 30:24
+    U32 Spare                                   :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA1CH1_CR_DDRCRDATAOFFSETTRAIN_STRUCT;
+
+typedef union {
+  struct {
+    U32 RxTrainingMode                          :  1;  // Bits 0:0
+    U32 WLTrainingMode                          :  1;  // Bits 1:1
+    U32 RLTrainingMode                          :  1;  // Bits 2:2
+    U32 SenseampTrainingMode                    :  1;  // Bits 3:3
+    U32 TxOn                                    :  1;  // Bits 4:4
+    U32 RfOn                                    :  1;  // Bits 5:5
+    U32 RxPiOn                                  :  1;  // Bits 6:6
+    U32 TxPiOn                                  :  1;  // Bits 7:7
+    U32 InternalClocksOn                        :  1;  // Bits 8:8
+    U32 RepeaterClocksOn                        :  1;  // Bits 9:9
+    U32 TxDisable                               :  1;  // Bits 10:10
+    U32 RxDisable                               :  1;  // Bits 11:11
+    U32 TxLong                                  :  1;  // Bits 12:12
+    U32 RxDqsCtle                               :  2;  // Bits 14:13
+    U32 RxReadPointer                           :  3;  // Bits 17:15
+    U32 DriverSegmentEnable                     :  1;  // Bits 18:18
+    U32 DataVccddqHi                            :  1;  // Bits 19:19
+    U32 ReadRFRd                                :  1;  // Bits 20:20
+    U32 ReadRFWr                                :  1;  // Bits 21:21
+    U32 ReadRFRank                              :  2;  // Bits 23:22
+    U32 ForceOdtOn                              :  1;  // Bits 24:24
+    U32 OdtSampOff                              :  1;  // Bits 25:25
+    U32 DisableOdtStatic                        :  1;  // Bits 26:26
+    U32 DdrCRForceODTOn                         :  1;  // Bits 27:27
+    U32 LPDDR_Mode                              :  1;  // Bits 28:28
+    U32 EnReadPreamble                          :  1;  // Bits 29:29
+    U32 OdtSampExtendEn                         :  1;  // Bits 30:30
+    U32 EarlyRleakEn                            :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA1CH1_CR_DDRCRDATACONTROL0_STRUCT;
+
+typedef union {
+  struct {
+    U32 CAVrefCtl                               :  7;  // Bits 6:0
+    U32 Ch1VrefCtl                              :  7;  // Bits 13:7
+    U32 Ch0VrefCtl                              :  7;  // Bits 20:14
+    U32 EnDimmVrefCA                            :  1;  // Bits 21:21
+    U32 EnDimmVrefCh1                           :  1;  // Bits 22:22
+    U32 EnDimmVrefCh0                           :  1;  // Bits 23:23
+    U32 HiZTimerCtrl                            :  2;  // Bits 25:24
+    U32 VccddqHiQnnnH                           :  1;  // Bits 26:26
+    U32 Rsvd                                    :  2;  // Bits 28:27
+    U32 caSlowBW                                :  1;  // Bits 29:29
+    U32 ch0SlowBW                               :  1;  // Bits 30:30
+    U32 ch1SlowBW                               :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA1CH1_CR_DDRCRVREFADJUST1_STRUCT;
+
+typedef union {
+  struct {
+    U32 RxRcvEnPi                               :  9;  // Bits 8:0
+    U32 RxDqsPPi                                :  6;  // Bits 14:9
+    U32 RxEq                                    :  5;  // Bits 19:15
+    U32 RxDqsNPi                                :  6;  // Bits 25:20
+    U32 RxVref                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA2CH0_CR_RXTRAINRANK0_STRUCT;
+
+typedef union {
+  struct {
+    U32 RxRcvEnPi                               :  9;  // Bits 8:0
+    U32 RxDqsPPi                                :  6;  // Bits 14:9
+    U32 RxEq                                    :  5;  // Bits 19:15
+    U32 RxDqsNPi                                :  6;  // Bits 25:20
+    U32 RxVref                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA2CH0_CR_RXTRAINRANK1_STRUCT;
+
+typedef union {
+  struct {
+    U32 RxRcvEnPi                               :  9;  // Bits 8:0
+    U32 RxDqsPPi                                :  6;  // Bits 14:9
+    U32 RxEq                                    :  5;  // Bits 19:15
+    U32 RxDqsNPi                                :  6;  // Bits 25:20
+    U32 RxVref                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA2CH0_CR_RXTRAINRANK2_STRUCT;
+
+typedef union {
+  struct {
+    U32 RxRcvEnPi                               :  9;  // Bits 8:0
+    U32 RxDqsPPi                                :  6;  // Bits 14:9
+    U32 RxEq                                    :  5;  // Bits 19:15
+    U32 RxDqsNPi                                :  6;  // Bits 25:20
+    U32 RxVref                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA2CH0_CR_RXTRAINRANK3_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA2CH0_CR_RXPERBITRANK0_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA2CH0_CR_RXPERBITRANK1_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA2CH0_CR_RXPERBITRANK2_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA2CH0_CR_RXPERBITRANK3_STRUCT;
+
+typedef union {
+  struct {
+    U32 TxDqDelay                               :  9;  // Bits 8:0
+    U32 TxDqsDelay                              :  9;  // Bits 17:9
+    U32 Spare0                                  :  2;  // Bits 19:18
+    U32 TxEqualization                          :  6;  // Bits 25:20
+    U32 Spare1                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA2CH0_CR_TXTRAINRANK0_STRUCT;
+
+typedef union {
+  struct {
+    U32 TxDqDelay                               :  9;  // Bits 8:0
+    U32 TxDqsDelay                              :  9;  // Bits 17:9
+    U32 Spare0                                  :  2;  // Bits 19:18
+    U32 TxEqualization                          :  6;  // Bits 25:20
+    U32 Spare1                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA2CH0_CR_TXTRAINRANK1_STRUCT;
+
+typedef union {
+  struct {
+    U32 TxDqDelay                               :  9;  // Bits 8:0
+    U32 TxDqsDelay                              :  9;  // Bits 17:9
+    U32 Spare0                                  :  2;  // Bits 19:18
+    U32 TxEqualization                          :  6;  // Bits 25:20
+    U32 Spare1                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA2CH0_CR_TXTRAINRANK2_STRUCT;
+
+typedef union {
+  struct {
+    U32 TxDqDelay                               :  9;  // Bits 8:0
+    U32 TxDqsDelay                              :  9;  // Bits 17:9
+    U32 Spare0                                  :  2;  // Bits 19:18
+    U32 TxEqualization                          :  6;  // Bits 25:20
+    U32 Spare1                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA2CH0_CR_TXTRAINRANK3_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA2CH0_CR_TXPERBITRANK0_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA2CH0_CR_TXPERBITRANK1_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA2CH0_CR_TXPERBITRANK2_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA2CH0_CR_TXPERBITRANK3_STRUCT;
+
+typedef union {
+  struct {
+    U32 RcompDrvUp                              :  6;  // Bits 5:0
+    U32 Spare0                                  :  3;  // Bits 8:6
+    U32 RcompDrvDown                            :  6;  // Bits 14:9
+    U32 VTComp                                  :  5;  // Bits 19:15
+    U32 TcoComp                                 :  6;  // Bits 25:20
+    U32 SlewRateComp                            :  5;  // Bits 30:26
+    U32 Spare2                                  :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA2CH0_CR_RCOMPDATA0_STRUCT;
+
+typedef union {
+  struct {
+    U32 RcompOdtUp                              :  6;  // Bits 5:0
+    U32 Spare0                                  :  3;  // Bits 8:6
+    U32 RcompOdtDown                            :  6;  // Bits 14:9
+    U32 Spare1                                  :  1;  // Bits 15:15
+    U32 PanicDrvDn                              :  6;  // Bits 21:16
+    U32 PanicDrvUp                              :  6;  // Bits 27:22
+    U32 LevelShifterComp                        :  3;  // Bits 30:28
+    U32 Spare2                                  :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA2CH0_CR_RCOMPDATA1_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA2CH0_CR_TXXTALK_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA2CH0_CR_RXOFFSETVDQ_STRUCT;
+
+typedef union {
+  struct {
+    U32 Spare                                   :  32;  // Bits 31:0
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA2CH0_CR_DDRDATARESERVED_STRUCT;
+
+typedef union {
+  struct {
+    U32 DataTrainFeedback                       :  9;  // Bits 8:0
+    U32 Spare                                   :  23;  // Bits 31:9
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA2CH0_CR_DATATRAINFEEDBACK_STRUCT;
+
+typedef union {
+  struct {
+    U32 RunTest                                 :  1;  // Bits 0:0
+    U32 Load                                    :  1;  // Bits 1:1
+    U32 ModeHVM                                 :  1;  // Bits 2:2
+    U32 ModeDV                                  :  1;  // Bits 3:3
+    U32 ModeADC                                 :  1;  // Bits 4:4
+    U32 LoadCount                               :  10;  // Bits 14:5
+    U32 CountStatus                             :  10;  // Bits 24:15
+    U32 Spare                                   :  7;  // Bits 31:25
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA2CH0_CR_DLLPITESTANDADC_STRUCT;
+
+typedef union {
+  struct {
+    U32 DqDrvUpCompOffset                       :  6;  // Bits 5:0
+    U32 DqDrvDownCompOffset                     :  6;  // Bits 11:6
+    U32 DqOdtUpCompOffset                       :  5;  // Bits 16:12
+    U32 DqOdtDownCompOffset                     :  5;  // Bits 21:17
+    U32 DqTcoCompOffset                         :  5;  // Bits 26:22
+    U32 DqSlewRateCompOffset                    :  5;  // Bits 31:27
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA2CH0_CR_DDRCRDATAOFFSETCOMP_STRUCT;
+
+typedef union {
+  struct {
+    U32 RefPi                                   :  4;  // Bits 3:0
+    U32 DllMask                                 :  2;  // Bits 5:4
+    U32 DllWeakLock                             :  1;  // Bits 6:6
+    U32 SdllSegmentDisable                      :  3;  // Bits 9:7
+    U32 RxBiasCtl                               :  3;  // Bits 12:10
+    U32 OdtDelay                                :  4;  // Bits 16:13
+    U32 OdtDuration                             :  3;  // Bits 19:17
+    U32 SenseAmpDelay                           :  4;  // Bits 23:20
+    U32 SenseAmpDuration                        :  3;  // Bits 26:24
+    U32 BurstEndODTDelay                        :  3;  // Bits 29:27
+    U32 LpDdrLongOdtEn                          :  1;  // Bits 30:30
+    U32 Rsvd1                                   :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA2CH0_CR_DDRCRDATACONTROL1_STRUCT;
+
+typedef union {
+  struct {
+    U32 RxStaggerCtl                            :  5;  // Bits 4:0
+    U32 ForceBiasOn                             :  1;  // Bits 5:5
+    U32 ForceRxOn                               :  1;  // Bits 6:6
+    U32 LeakerComp                              :  2;  // Bits 8:7
+    U32 RxDqsAmpOffset                          :  4;  // Bits 12:9
+    U32 RxClkStgNum                             :  5;  // Bits 17:13
+    U32 WlLongDelEn                             :  1;  // Bits 18:18
+    U32 Spare                                   :  13;  // Bits 31:19
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA2CH0_CR_DDRCRDATACONTROL2_STRUCT;
+
+typedef union {
+  struct {
+    U32 VssHiOrVrefCtl                          :  24;  // Bits 23:0
+    U32 OutputCode                              :  8;  // Bits 31:24
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA2CH0_CR_DDRCRVSSHIORVREFCONTROL_STRUCT;
+
+typedef union {
+  struct {
+    U32 RcvEnOffset                             :  6;  // Bits 5:0
+    U32 RxDqsOffset                             :  6;  // Bits 11:6
+    U32 TxDqOffset                              :  6;  // Bits 17:12
+    U32 TxDqsOffset                             :  6;  // Bits 23:18
+    U32 VrefOffset                              :  7;  // Bits 30:24
+    U32 Spare                                   :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA2CH0_CR_DDRCRDATAOFFSETTRAIN_STRUCT;
+
+typedef union {
+  struct {
+    U32 RxTrainingMode                          :  1;  // Bits 0:0
+    U32 WLTrainingMode                          :  1;  // Bits 1:1
+    U32 RLTrainingMode                          :  1;  // Bits 2:2
+    U32 SenseampTrainingMode                    :  1;  // Bits 3:3
+    U32 TxOn                                    :  1;  // Bits 4:4
+    U32 RfOn                                    :  1;  // Bits 5:5
+    U32 RxPiOn                                  :  1;  // Bits 6:6
+    U32 TxPiOn                                  :  1;  // Bits 7:7
+    U32 InternalClocksOn                        :  1;  // Bits 8:8
+    U32 RepeaterClocksOn                        :  1;  // Bits 9:9
+    U32 TxDisable                               :  1;  // Bits 10:10
+    U32 RxDisable                               :  1;  // Bits 11:11
+    U32 TxLong                                  :  1;  // Bits 12:12
+    U32 RxDqsCtle                               :  2;  // Bits 14:13
+    U32 RxReadPointer                           :  3;  // Bits 17:15
+    U32 DriverSegmentEnable                     :  1;  // Bits 18:18
+    U32 DataVccddqHi                            :  1;  // Bits 19:19
+    U32 ReadRFRd                                :  1;  // Bits 20:20
+    U32 ReadRFWr                                :  1;  // Bits 21:21
+    U32 ReadRFRank                              :  2;  // Bits 23:22
+    U32 ForceOdtOn                              :  1;  // Bits 24:24
+    U32 OdtSampOff                              :  1;  // Bits 25:25
+    U32 DisableOdtStatic                        :  1;  // Bits 26:26
+    U32 DdrCRForceODTOn                         :  1;  // Bits 27:27
+    U32 LPDDR_Mode                              :  1;  // Bits 28:28
+    U32 EnReadPreamble                          :  1;  // Bits 29:29
+    U32 OdtSampExtendEn                         :  1;  // Bits 30:30
+    U32 EarlyRleakEn                            :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA2CH0_CR_DDRCRDATACONTROL0_STRUCT;
+
+typedef union {
+  struct {
+    U32 CAVrefCtl                               :  7;  // Bits 6:0
+    U32 Ch1VrefCtl                              :  7;  // Bits 13:7
+    U32 Ch0VrefCtl                              :  7;  // Bits 20:14
+    U32 EnDimmVrefCA                            :  1;  // Bits 21:21
+    U32 EnDimmVrefCh1                           :  1;  // Bits 22:22
+    U32 EnDimmVrefCh0                           :  1;  // Bits 23:23
+    U32 HiZTimerCtrl                            :  2;  // Bits 25:24
+    U32 VccddqHiQnnnH                           :  1;  // Bits 26:26
+    U32 Rsvd                                    :  2;  // Bits 28:27
+    U32 caSlowBW                                :  1;  // Bits 29:29
+    U32 ch0SlowBW                               :  1;  // Bits 30:30
+    U32 ch1SlowBW                               :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA2CH0_CR_DDRCRVREFADJUST1_STRUCT;
+
+typedef union {
+  struct {
+    U32 RxRcvEnPi                               :  9;  // Bits 8:0
+    U32 RxDqsPPi                                :  6;  // Bits 14:9
+    U32 RxEq                                    :  5;  // Bits 19:15
+    U32 RxDqsNPi                                :  6;  // Bits 25:20
+    U32 RxVref                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA2CH1_CR_RXTRAINRANK0_STRUCT;
+
+typedef union {
+  struct {
+    U32 RxRcvEnPi                               :  9;  // Bits 8:0
+    U32 RxDqsPPi                                :  6;  // Bits 14:9
+    U32 RxEq                                    :  5;  // Bits 19:15
+    U32 RxDqsNPi                                :  6;  // Bits 25:20
+    U32 RxVref                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA2CH1_CR_RXTRAINRANK1_STRUCT;
+
+typedef union {
+  struct {
+    U32 RxRcvEnPi                               :  9;  // Bits 8:0
+    U32 RxDqsPPi                                :  6;  // Bits 14:9
+    U32 RxEq                                    :  5;  // Bits 19:15
+    U32 RxDqsNPi                                :  6;  // Bits 25:20
+    U32 RxVref                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA2CH1_CR_RXTRAINRANK2_STRUCT;
+
+typedef union {
+  struct {
+    U32 RxRcvEnPi                               :  9;  // Bits 8:0
+    U32 RxDqsPPi                                :  6;  // Bits 14:9
+    U32 RxEq                                    :  5;  // Bits 19:15
+    U32 RxDqsNPi                                :  6;  // Bits 25:20
+    U32 RxVref                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA2CH1_CR_RXTRAINRANK3_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA2CH1_CR_RXPERBITRANK0_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA2CH1_CR_RXPERBITRANK1_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA2CH1_CR_RXPERBITRANK2_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA2CH1_CR_RXPERBITRANK3_STRUCT;
+
+typedef union {
+  struct {
+    U32 TxDqDelay                               :  9;  // Bits 8:0
+    U32 TxDqsDelay                              :  9;  // Bits 17:9
+    U32 Spare0                                  :  2;  // Bits 19:18
+    U32 TxEqualization                          :  6;  // Bits 25:20
+    U32 Spare1                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA2CH1_CR_TXTRAINRANK0_STRUCT;
+
+typedef union {
+  struct {
+    U32 TxDqDelay                               :  9;  // Bits 8:0
+    U32 TxDqsDelay                              :  9;  // Bits 17:9
+    U32 Spare0                                  :  2;  // Bits 19:18
+    U32 TxEqualization                          :  6;  // Bits 25:20
+    U32 Spare1                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA2CH1_CR_TXTRAINRANK1_STRUCT;
+
+typedef union {
+  struct {
+    U32 TxDqDelay                               :  9;  // Bits 8:0
+    U32 TxDqsDelay                              :  9;  // Bits 17:9
+    U32 Spare0                                  :  2;  // Bits 19:18
+    U32 TxEqualization                          :  6;  // Bits 25:20
+    U32 Spare1                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA2CH1_CR_TXTRAINRANK2_STRUCT;
+
+typedef union {
+  struct {
+    U32 TxDqDelay                               :  9;  // Bits 8:0
+    U32 TxDqsDelay                              :  9;  // Bits 17:9
+    U32 Spare0                                  :  2;  // Bits 19:18
+    U32 TxEqualization                          :  6;  // Bits 25:20
+    U32 Spare1                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA2CH1_CR_TXTRAINRANK3_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA2CH1_CR_TXPERBITRANK0_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA2CH1_CR_TXPERBITRANK1_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA2CH1_CR_TXPERBITRANK2_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA2CH1_CR_TXPERBITRANK3_STRUCT;
+
+typedef union {
+  struct {
+    U32 RcompDrvUp                              :  6;  // Bits 5:0
+    U32 Spare0                                  :  3;  // Bits 8:6
+    U32 RcompDrvDown                            :  6;  // Bits 14:9
+    U32 VTComp                                  :  5;  // Bits 19:15
+    U32 TcoComp                                 :  6;  // Bits 25:20
+    U32 SlewRateComp                            :  5;  // Bits 30:26
+    U32 Spare2                                  :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA2CH1_CR_RCOMPDATA0_STRUCT;
+
+typedef union {
+  struct {
+    U32 RcompOdtUp                              :  6;  // Bits 5:0
+    U32 Spare0                                  :  3;  // Bits 8:6
+    U32 RcompOdtDown                            :  6;  // Bits 14:9
+    U32 Spare1                                  :  1;  // Bits 15:15
+    U32 PanicDrvDn                              :  6;  // Bits 21:16
+    U32 PanicDrvUp                              :  6;  // Bits 27:22
+    U32 LevelShifterComp                        :  3;  // Bits 30:28
+    U32 Spare2                                  :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA2CH1_CR_RCOMPDATA1_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA2CH1_CR_TXXTALK_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA2CH1_CR_RXOFFSETVDQ_STRUCT;
+
+typedef union {
+  struct {
+    U32 Spare                                   :  32;  // Bits 31:0
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA2CH1_CR_DDRDATARESERVED_STRUCT;
+
+typedef union {
+  struct {
+    U32 DataTrainFeedback                       :  9;  // Bits 8:0
+    U32 Spare                                   :  23;  // Bits 31:9
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA2CH1_CR_DATATRAINFEEDBACK_STRUCT;
+
+typedef union {
+  struct {
+    U32 RunTest                                 :  1;  // Bits 0:0
+    U32 Load                                    :  1;  // Bits 1:1
+    U32 ModeHVM                                 :  1;  // Bits 2:2
+    U32 ModeDV                                  :  1;  // Bits 3:3
+    U32 ModeADC                                 :  1;  // Bits 4:4
+    U32 LoadCount                               :  10;  // Bits 14:5
+    U32 CountStatus                             :  10;  // Bits 24:15
+    U32 Spare                                   :  7;  // Bits 31:25
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA2CH1_CR_DLLPITESTANDADC_STRUCT;
+
+typedef union {
+  struct {
+    U32 DqDrvUpCompOffset                       :  6;  // Bits 5:0
+    U32 DqDrvDownCompOffset                     :  6;  // Bits 11:6
+    U32 DqOdtUpCompOffset                       :  5;  // Bits 16:12
+    U32 DqOdtDownCompOffset                     :  5;  // Bits 21:17
+    U32 DqTcoCompOffset                         :  5;  // Bits 26:22
+    U32 DqSlewRateCompOffset                    :  5;  // Bits 31:27
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA2CH1_CR_DDRCRDATAOFFSETCOMP_STRUCT;
+
+typedef union {
+  struct {
+    U32 RefPi                                   :  4;  // Bits 3:0
+    U32 DllMask                                 :  2;  // Bits 5:4
+    U32 DllWeakLock                             :  1;  // Bits 6:6
+    U32 SdllSegmentDisable                      :  3;  // Bits 9:7
+    U32 RxBiasCtl                               :  3;  // Bits 12:10
+    U32 OdtDelay                                :  4;  // Bits 16:13
+    U32 OdtDuration                             :  3;  // Bits 19:17
+    U32 SenseAmpDelay                           :  4;  // Bits 23:20
+    U32 SenseAmpDuration                        :  3;  // Bits 26:24
+    U32 BurstEndODTDelay                        :  3;  // Bits 29:27
+    U32 LpDdrLongOdtEn                          :  1;  // Bits 30:30
+    U32 Rsvd1                                   :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA2CH1_CR_DDRCRDATACONTROL1_STRUCT;
+
+typedef union {
+  struct {
+    U32 RxStaggerCtl                            :  5;  // Bits 4:0
+    U32 ForceBiasOn                             :  1;  // Bits 5:5
+    U32 ForceRxOn                               :  1;  // Bits 6:6
+    U32 LeakerComp                              :  2;  // Bits 8:7
+    U32 RxDqsAmpOffset                          :  4;  // Bits 12:9
+    U32 RxClkStgNum                             :  5;  // Bits 17:13
+    U32 WlLongDelEn                             :  1;  // Bits 18:18
+    U32 Spare                                   :  13;  // Bits 31:19
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA2CH1_CR_DDRCRDATACONTROL2_STRUCT;
+
+typedef union {
+  struct {
+    U32 VssHiOrVrefCtl                          :  24;  // Bits 23:0
+    U32 OutputCode                              :  8;  // Bits 31:24
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA2CH1_CR_DDRCRVSSHIORVREFCONTROL_STRUCT;
+
+typedef union {
+  struct {
+    U32 RcvEnOffset                             :  6;  // Bits 5:0
+    U32 RxDqsOffset                             :  6;  // Bits 11:6
+    U32 TxDqOffset                              :  6;  // Bits 17:12
+    U32 TxDqsOffset                             :  6;  // Bits 23:18
+    U32 VrefOffset                              :  7;  // Bits 30:24
+    U32 Spare                                   :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA2CH1_CR_DDRCRDATAOFFSETTRAIN_STRUCT;
+
+typedef union {
+  struct {
+    U32 RxTrainingMode                          :  1;  // Bits 0:0
+    U32 WLTrainingMode                          :  1;  // Bits 1:1
+    U32 RLTrainingMode                          :  1;  // Bits 2:2
+    U32 SenseampTrainingMode                    :  1;  // Bits 3:3
+    U32 TxOn                                    :  1;  // Bits 4:4
+    U32 RfOn                                    :  1;  // Bits 5:5
+    U32 RxPiOn                                  :  1;  // Bits 6:6
+    U32 TxPiOn                                  :  1;  // Bits 7:7
+    U32 InternalClocksOn                        :  1;  // Bits 8:8
+    U32 RepeaterClocksOn                        :  1;  // Bits 9:9
+    U32 TxDisable                               :  1;  // Bits 10:10
+    U32 RxDisable                               :  1;  // Bits 11:11
+    U32 TxLong                                  :  1;  // Bits 12:12
+    U32 RxDqsCtle                               :  2;  // Bits 14:13
+    U32 RxReadPointer                           :  3;  // Bits 17:15
+    U32 DriverSegmentEnable                     :  1;  // Bits 18:18
+    U32 DataVccddqHi                            :  1;  // Bits 19:19
+    U32 ReadRFRd                                :  1;  // Bits 20:20
+    U32 ReadRFWr                                :  1;  // Bits 21:21
+    U32 ReadRFRank                              :  2;  // Bits 23:22
+    U32 ForceOdtOn                              :  1;  // Bits 24:24
+    U32 OdtSampOff                              :  1;  // Bits 25:25
+    U32 DisableOdtStatic                        :  1;  // Bits 26:26
+    U32 DdrCRForceODTOn                         :  1;  // Bits 27:27
+    U32 LPDDR_Mode                              :  1;  // Bits 28:28
+    U32 EnReadPreamble                          :  1;  // Bits 29:29
+    U32 OdtSampExtendEn                         :  1;  // Bits 30:30
+    U32 EarlyRleakEn                            :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA2CH1_CR_DDRCRDATACONTROL0_STRUCT;
+
+typedef union {
+  struct {
+    U32 CAVrefCtl                               :  7;  // Bits 6:0
+    U32 Ch1VrefCtl                              :  7;  // Bits 13:7
+    U32 Ch0VrefCtl                              :  7;  // Bits 20:14
+    U32 EnDimmVrefCA                            :  1;  // Bits 21:21
+    U32 EnDimmVrefCh1                           :  1;  // Bits 22:22
+    U32 EnDimmVrefCh0                           :  1;  // Bits 23:23
+    U32 HiZTimerCtrl                            :  2;  // Bits 25:24
+    U32 VccddqHiQnnnH                           :  1;  // Bits 26:26
+    U32 Rsvd                                    :  2;  // Bits 28:27
+    U32 caSlowBW                                :  1;  // Bits 29:29
+    U32 ch0SlowBW                               :  1;  // Bits 30:30
+    U32 ch1SlowBW                               :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA2CH1_CR_DDRCRVREFADJUST1_STRUCT;
+
+typedef union {
+  struct {
+    U32 RxRcvEnPi                               :  9;  // Bits 8:0
+    U32 RxDqsPPi                                :  6;  // Bits 14:9
+    U32 RxEq                                    :  5;  // Bits 19:15
+    U32 RxDqsNPi                                :  6;  // Bits 25:20
+    U32 RxVref                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA3CH0_CR_RXTRAINRANK0_STRUCT;
+
+typedef union {
+  struct {
+    U32 RxRcvEnPi                               :  9;  // Bits 8:0
+    U32 RxDqsPPi                                :  6;  // Bits 14:9
+    U32 RxEq                                    :  5;  // Bits 19:15
+    U32 RxDqsNPi                                :  6;  // Bits 25:20
+    U32 RxVref                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA3CH0_CR_RXTRAINRANK1_STRUCT;
+
+typedef union {
+  struct {
+    U32 RxRcvEnPi                               :  9;  // Bits 8:0
+    U32 RxDqsPPi                                :  6;  // Bits 14:9
+    U32 RxEq                                    :  5;  // Bits 19:15
+    U32 RxDqsNPi                                :  6;  // Bits 25:20
+    U32 RxVref                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA3CH0_CR_RXTRAINRANK2_STRUCT;
+
+typedef union {
+  struct {
+    U32 RxRcvEnPi                               :  9;  // Bits 8:0
+    U32 RxDqsPPi                                :  6;  // Bits 14:9
+    U32 RxEq                                    :  5;  // Bits 19:15
+    U32 RxDqsNPi                                :  6;  // Bits 25:20
+    U32 RxVref                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA3CH0_CR_RXTRAINRANK3_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA3CH0_CR_RXPERBITRANK0_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA3CH0_CR_RXPERBITRANK1_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA3CH0_CR_RXPERBITRANK2_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA3CH0_CR_RXPERBITRANK3_STRUCT;
+
+typedef union {
+  struct {
+    U32 TxDqDelay                               :  9;  // Bits 8:0
+    U32 TxDqsDelay                              :  9;  // Bits 17:9
+    U32 Spare0                                  :  2;  // Bits 19:18
+    U32 TxEqualization                          :  6;  // Bits 25:20
+    U32 Spare1                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA3CH0_CR_TXTRAINRANK0_STRUCT;
+
+typedef union {
+  struct {
+    U32 TxDqDelay                               :  9;  // Bits 8:0
+    U32 TxDqsDelay                              :  9;  // Bits 17:9
+    U32 Spare0                                  :  2;  // Bits 19:18
+    U32 TxEqualization                          :  6;  // Bits 25:20
+    U32 Spare1                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA3CH0_CR_TXTRAINRANK1_STRUCT;
+
+typedef union {
+  struct {
+    U32 TxDqDelay                               :  9;  // Bits 8:0
+    U32 TxDqsDelay                              :  9;  // Bits 17:9
+    U32 Spare0                                  :  2;  // Bits 19:18
+    U32 TxEqualization                          :  6;  // Bits 25:20
+    U32 Spare1                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA3CH0_CR_TXTRAINRANK2_STRUCT;
+
+typedef union {
+  struct {
+    U32 TxDqDelay                               :  9;  // Bits 8:0
+    U32 TxDqsDelay                              :  9;  // Bits 17:9
+    U32 Spare0                                  :  2;  // Bits 19:18
+    U32 TxEqualization                          :  6;  // Bits 25:20
+    U32 Spare1                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA3CH0_CR_TXTRAINRANK3_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA3CH0_CR_TXPERBITRANK0_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA3CH0_CR_TXPERBITRANK1_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA3CH0_CR_TXPERBITRANK2_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA3CH0_CR_TXPERBITRANK3_STRUCT;
+
+typedef union {
+  struct {
+    U32 RcompDrvUp                              :  6;  // Bits 5:0
+    U32 Spare0                                  :  3;  // Bits 8:6
+    U32 RcompDrvDown                            :  6;  // Bits 14:9
+    U32 VTComp                                  :  5;  // Bits 19:15
+    U32 TcoComp                                 :  6;  // Bits 25:20
+    U32 SlewRateComp                            :  5;  // Bits 30:26
+    U32 Spare2                                  :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA3CH0_CR_RCOMPDATA0_STRUCT;
+
+typedef union {
+  struct {
+    U32 RcompOdtUp                              :  6;  // Bits 5:0
+    U32 Spare0                                  :  3;  // Bits 8:6
+    U32 RcompOdtDown                            :  6;  // Bits 14:9
+    U32 Spare1                                  :  1;  // Bits 15:15
+    U32 PanicDrvDn                              :  6;  // Bits 21:16
+    U32 PanicDrvUp                              :  6;  // Bits 27:22
+    U32 LevelShifterComp                        :  3;  // Bits 30:28
+    U32 Spare2                                  :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA3CH0_CR_RCOMPDATA1_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA3CH0_CR_TXXTALK_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA3CH0_CR_RXOFFSETVDQ_STRUCT;
+
+typedef union {
+  struct {
+    U32 Spare                                   :  32;  // Bits 31:0
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA3CH0_CR_DDRDATARESERVED_STRUCT;
+
+typedef union {
+  struct {
+    U32 DataTrainFeedback                       :  9;  // Bits 8:0
+    U32 Spare                                   :  23;  // Bits 31:9
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA3CH0_CR_DATATRAINFEEDBACK_STRUCT;
+
+typedef union {
+  struct {
+    U32 RunTest                                 :  1;  // Bits 0:0
+    U32 Load                                    :  1;  // Bits 1:1
+    U32 ModeHVM                                 :  1;  // Bits 2:2
+    U32 ModeDV                                  :  1;  // Bits 3:3
+    U32 ModeADC                                 :  1;  // Bits 4:4
+    U32 LoadCount                               :  10;  // Bits 14:5
+    U32 CountStatus                             :  10;  // Bits 24:15
+    U32 Spare                                   :  7;  // Bits 31:25
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA3CH0_CR_DLLPITESTANDADC_STRUCT;
+
+typedef union {
+  struct {
+    U32 DqDrvUpCompOffset                       :  6;  // Bits 5:0
+    U32 DqDrvDownCompOffset                     :  6;  // Bits 11:6
+    U32 DqOdtUpCompOffset                       :  5;  // Bits 16:12
+    U32 DqOdtDownCompOffset                     :  5;  // Bits 21:17
+    U32 DqTcoCompOffset                         :  5;  // Bits 26:22
+    U32 DqSlewRateCompOffset                    :  5;  // Bits 31:27
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA3CH0_CR_DDRCRDATAOFFSETCOMP_STRUCT;
+
+typedef union {
+  struct {
+    U32 RefPi                                   :  4;  // Bits 3:0
+    U32 DllMask                                 :  2;  // Bits 5:4
+    U32 DllWeakLock                             :  1;  // Bits 6:6
+    U32 SdllSegmentDisable                      :  3;  // Bits 9:7
+    U32 RxBiasCtl                               :  3;  // Bits 12:10
+    U32 OdtDelay                                :  4;  // Bits 16:13
+    U32 OdtDuration                             :  3;  // Bits 19:17
+    U32 SenseAmpDelay                           :  4;  // Bits 23:20
+    U32 SenseAmpDuration                        :  3;  // Bits 26:24
+    U32 BurstEndODTDelay                        :  3;  // Bits 29:27
+    U32 LpDdrLongOdtEn                          :  1;  // Bits 30:30
+    U32 Rsvd1                                   :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA3CH0_CR_DDRCRDATACONTROL1_STRUCT;
+
+typedef union {
+  struct {
+    U32 RxStaggerCtl                            :  5;  // Bits 4:0
+    U32 ForceBiasOn                             :  1;  // Bits 5:5
+    U32 ForceRxOn                               :  1;  // Bits 6:6
+    U32 LeakerComp                              :  2;  // Bits 8:7
+    U32 RxDqsAmpOffset                          :  4;  // Bits 12:9
+    U32 RxClkStgNum                             :  5;  // Bits 17:13
+    U32 WlLongDelEn                             :  1;  // Bits 18:18
+    U32 Spare                                   :  13;  // Bits 31:19
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA3CH0_CR_DDRCRDATACONTROL2_STRUCT;
+
+typedef union {
+  struct {
+    U32 VssHiOrVrefCtl                          :  24;  // Bits 23:0
+    U32 OutputCode                              :  8;  // Bits 31:24
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA3CH0_CR_DDRCRVSSHIORVREFCONTROL_STRUCT;
+
+typedef union {
+  struct {
+    U32 RcvEnOffset                             :  6;  // Bits 5:0
+    U32 RxDqsOffset                             :  6;  // Bits 11:6
+    U32 TxDqOffset                              :  6;  // Bits 17:12
+    U32 TxDqsOffset                             :  6;  // Bits 23:18
+    U32 VrefOffset                              :  7;  // Bits 30:24
+    U32 Spare                                   :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA3CH0_CR_DDRCRDATAOFFSETTRAIN_STRUCT;
+
+typedef union {
+  struct {
+    U32 RxTrainingMode                          :  1;  // Bits 0:0
+    U32 WLTrainingMode                          :  1;  // Bits 1:1
+    U32 RLTrainingMode                          :  1;  // Bits 2:2
+    U32 SenseampTrainingMode                    :  1;  // Bits 3:3
+    U32 TxOn                                    :  1;  // Bits 4:4
+    U32 RfOn                                    :  1;  // Bits 5:5
+    U32 RxPiOn                                  :  1;  // Bits 6:6
+    U32 TxPiOn                                  :  1;  // Bits 7:7
+    U32 InternalClocksOn                        :  1;  // Bits 8:8
+    U32 RepeaterClocksOn                        :  1;  // Bits 9:9
+    U32 TxDisable                               :  1;  // Bits 10:10
+    U32 RxDisable                               :  1;  // Bits 11:11
+    U32 TxLong                                  :  1;  // Bits 12:12
+    U32 RxDqsCtle                               :  2;  // Bits 14:13
+    U32 RxReadPointer                           :  3;  // Bits 17:15
+    U32 DriverSegmentEnable                     :  1;  // Bits 18:18
+    U32 DataVccddqHi                            :  1;  // Bits 19:19
+    U32 ReadRFRd                                :  1;  // Bits 20:20
+    U32 ReadRFWr                                :  1;  // Bits 21:21
+    U32 ReadRFRank                              :  2;  // Bits 23:22
+    U32 ForceOdtOn                              :  1;  // Bits 24:24
+    U32 OdtSampOff                              :  1;  // Bits 25:25
+    U32 DisableOdtStatic                        :  1;  // Bits 26:26
+    U32 DdrCRForceODTOn                         :  1;  // Bits 27:27
+    U32 LPDDR_Mode                              :  1;  // Bits 28:28
+    U32 EnReadPreamble                          :  1;  // Bits 29:29
+    U32 OdtSampExtendEn                         :  1;  // Bits 30:30
+    U32 EarlyRleakEn                            :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA3CH0_CR_DDRCRDATACONTROL0_STRUCT;
+
+typedef union {
+  struct {
+    U32 CAVrefCtl                               :  7;  // Bits 6:0
+    U32 Ch1VrefCtl                              :  7;  // Bits 13:7
+    U32 Ch0VrefCtl                              :  7;  // Bits 20:14
+    U32 EnDimmVrefCA                            :  1;  // Bits 21:21
+    U32 EnDimmVrefCh1                           :  1;  // Bits 22:22
+    U32 EnDimmVrefCh0                           :  1;  // Bits 23:23
+    U32 HiZTimerCtrl                            :  2;  // Bits 25:24
+    U32 VccddqHiQnnnH                           :  1;  // Bits 26:26
+    U32 Rsvd                                    :  2;  // Bits 28:27
+    U32 caSlowBW                                :  1;  // Bits 29:29
+    U32 ch0SlowBW                               :  1;  // Bits 30:30
+    U32 ch1SlowBW                               :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA3CH0_CR_DDRCRVREFADJUST1_STRUCT;
+
+typedef union {
+  struct {
+    U32 RxRcvEnPi                               :  9;  // Bits 8:0
+    U32 RxDqsPPi                                :  6;  // Bits 14:9
+    U32 RxEq                                    :  5;  // Bits 19:15
+    U32 RxDqsNPi                                :  6;  // Bits 25:20
+    U32 RxVref                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA3CH1_CR_RXTRAINRANK0_STRUCT;
+
+typedef union {
+  struct {
+    U32 RxRcvEnPi                               :  9;  // Bits 8:0
+    U32 RxDqsPPi                                :  6;  // Bits 14:9
+    U32 RxEq                                    :  5;  // Bits 19:15
+    U32 RxDqsNPi                                :  6;  // Bits 25:20
+    U32 RxVref                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA3CH1_CR_RXTRAINRANK1_STRUCT;
+
+typedef union {
+  struct {
+    U32 RxRcvEnPi                               :  9;  // Bits 8:0
+    U32 RxDqsPPi                                :  6;  // Bits 14:9
+    U32 RxEq                                    :  5;  // Bits 19:15
+    U32 RxDqsNPi                                :  6;  // Bits 25:20
+    U32 RxVref                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA3CH1_CR_RXTRAINRANK2_STRUCT;
+
+typedef union {
+  struct {
+    U32 RxRcvEnPi                               :  9;  // Bits 8:0
+    U32 RxDqsPPi                                :  6;  // Bits 14:9
+    U32 RxEq                                    :  5;  // Bits 19:15
+    U32 RxDqsNPi                                :  6;  // Bits 25:20
+    U32 RxVref                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA3CH1_CR_RXTRAINRANK3_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA3CH1_CR_RXPERBITRANK0_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA3CH1_CR_RXPERBITRANK1_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA3CH1_CR_RXPERBITRANK2_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA3CH1_CR_RXPERBITRANK3_STRUCT;
+
+typedef union {
+  struct {
+    U32 TxDqDelay                               :  9;  // Bits 8:0
+    U32 TxDqsDelay                              :  9;  // Bits 17:9
+    U32 Spare0                                  :  2;  // Bits 19:18
+    U32 TxEqualization                          :  6;  // Bits 25:20
+    U32 Spare1                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA3CH1_CR_TXTRAINRANK0_STRUCT;
+
+typedef union {
+  struct {
+    U32 TxDqDelay                               :  9;  // Bits 8:0
+    U32 TxDqsDelay                              :  9;  // Bits 17:9
+    U32 Spare0                                  :  2;  // Bits 19:18
+    U32 TxEqualization                          :  6;  // Bits 25:20
+    U32 Spare1                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA3CH1_CR_TXTRAINRANK1_STRUCT;
+
+typedef union {
+  struct {
+    U32 TxDqDelay                               :  9;  // Bits 8:0
+    U32 TxDqsDelay                              :  9;  // Bits 17:9
+    U32 Spare0                                  :  2;  // Bits 19:18
+    U32 TxEqualization                          :  6;  // Bits 25:20
+    U32 Spare1                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA3CH1_CR_TXTRAINRANK2_STRUCT;
+
+typedef union {
+  struct {
+    U32 TxDqDelay                               :  9;  // Bits 8:0
+    U32 TxDqsDelay                              :  9;  // Bits 17:9
+    U32 Spare0                                  :  2;  // Bits 19:18
+    U32 TxEqualization                          :  6;  // Bits 25:20
+    U32 Spare1                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA3CH1_CR_TXTRAINRANK3_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA3CH1_CR_TXPERBITRANK0_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA3CH1_CR_TXPERBITRANK1_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA3CH1_CR_TXPERBITRANK2_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA3CH1_CR_TXPERBITRANK3_STRUCT;
+
+typedef union {
+  struct {
+    U32 RcompDrvUp                              :  6;  // Bits 5:0
+    U32 Spare0                                  :  3;  // Bits 8:6
+    U32 RcompDrvDown                            :  6;  // Bits 14:9
+    U32 VTComp                                  :  5;  // Bits 19:15
+    U32 TcoComp                                 :  6;  // Bits 25:20
+    U32 SlewRateComp                            :  5;  // Bits 30:26
+    U32 Spare2                                  :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA3CH1_CR_RCOMPDATA0_STRUCT;
+
+typedef union {
+  struct {
+    U32 RcompOdtUp                              :  6;  // Bits 5:0
+    U32 Spare0                                  :  3;  // Bits 8:6
+    U32 RcompOdtDown                            :  6;  // Bits 14:9
+    U32 Spare1                                  :  1;  // Bits 15:15
+    U32 PanicDrvDn                              :  6;  // Bits 21:16
+    U32 PanicDrvUp                              :  6;  // Bits 27:22
+    U32 LevelShifterComp                        :  3;  // Bits 30:28
+    U32 Spare2                                  :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA3CH1_CR_RCOMPDATA1_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA3CH1_CR_TXXTALK_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA3CH1_CR_RXOFFSETVDQ_STRUCT;
+
+typedef union {
+  struct {
+    U32 Spare                                   :  32;  // Bits 31:0
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA3CH1_CR_DDRDATARESERVED_STRUCT;
+
+typedef union {
+  struct {
+    U32 DataTrainFeedback                       :  9;  // Bits 8:0
+    U32 Spare                                   :  23;  // Bits 31:9
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA3CH1_CR_DATATRAINFEEDBACK_STRUCT;
+
+typedef union {
+  struct {
+    U32 RunTest                                 :  1;  // Bits 0:0
+    U32 Load                                    :  1;  // Bits 1:1
+    U32 ModeHVM                                 :  1;  // Bits 2:2
+    U32 ModeDV                                  :  1;  // Bits 3:3
+    U32 ModeADC                                 :  1;  // Bits 4:4
+    U32 LoadCount                               :  10;  // Bits 14:5
+    U32 CountStatus                             :  10;  // Bits 24:15
+    U32 Spare                                   :  7;  // Bits 31:25
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA3CH1_CR_DLLPITESTANDADC_STRUCT;
+
+typedef union {
+  struct {
+    U32 DqDrvUpCompOffset                       :  6;  // Bits 5:0
+    U32 DqDrvDownCompOffset                     :  6;  // Bits 11:6
+    U32 DqOdtUpCompOffset                       :  5;  // Bits 16:12
+    U32 DqOdtDownCompOffset                     :  5;  // Bits 21:17
+    U32 DqTcoCompOffset                         :  5;  // Bits 26:22
+    U32 DqSlewRateCompOffset                    :  5;  // Bits 31:27
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA3CH1_CR_DDRCRDATAOFFSETCOMP_STRUCT;
+
+typedef union {
+  struct {
+    U32 RefPi                                   :  4;  // Bits 3:0
+    U32 DllMask                                 :  2;  // Bits 5:4
+    U32 DllWeakLock                             :  1;  // Bits 6:6
+    U32 SdllSegmentDisable                      :  3;  // Bits 9:7
+    U32 RxBiasCtl                               :  3;  // Bits 12:10
+    U32 OdtDelay                                :  4;  // Bits 16:13
+    U32 OdtDuration                             :  3;  // Bits 19:17
+    U32 SenseAmpDelay                           :  4;  // Bits 23:20
+    U32 SenseAmpDuration                        :  3;  // Bits 26:24
+    U32 BurstEndODTDelay                        :  3;  // Bits 29:27
+    U32 LpDdrLongOdtEn                          :  1;  // Bits 30:30
+    U32 Rsvd1                                   :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA3CH1_CR_DDRCRDATACONTROL1_STRUCT;
+
+typedef union {
+  struct {
+    U32 RxStaggerCtl                            :  5;  // Bits 4:0
+    U32 ForceBiasOn                             :  1;  // Bits 5:5
+    U32 ForceRxOn                               :  1;  // Bits 6:6
+    U32 LeakerComp                              :  2;  // Bits 8:7
+    U32 RxDqsAmpOffset                          :  4;  // Bits 12:9
+    U32 RxClkStgNum                             :  5;  // Bits 17:13
+    U32 WlLongDelEn                             :  1;  // Bits 18:18
+    U32 Spare                                   :  13;  // Bits 31:19
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA3CH1_CR_DDRCRDATACONTROL2_STRUCT;
+
+typedef union {
+  struct {
+    U32 VssHiOrVrefCtl                          :  24;  // Bits 23:0
+    U32 OutputCode                              :  8;  // Bits 31:24
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA3CH1_CR_DDRCRVSSHIORVREFCONTROL_STRUCT;
+
+typedef union {
+  struct {
+    U32 RcvEnOffset                             :  6;  // Bits 5:0
+    U32 RxDqsOffset                             :  6;  // Bits 11:6
+    U32 TxDqOffset                              :  6;  // Bits 17:12
+    U32 TxDqsOffset                             :  6;  // Bits 23:18
+    U32 VrefOffset                              :  7;  // Bits 30:24
+    U32 Spare                                   :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA3CH1_CR_DDRCRDATAOFFSETTRAIN_STRUCT;
+
+typedef union {
+  struct {
+    U32 RxTrainingMode                          :  1;  // Bits 0:0
+    U32 WLTrainingMode                          :  1;  // Bits 1:1
+    U32 RLTrainingMode                          :  1;  // Bits 2:2
+    U32 SenseampTrainingMode                    :  1;  // Bits 3:3
+    U32 TxOn                                    :  1;  // Bits 4:4
+    U32 RfOn                                    :  1;  // Bits 5:5
+    U32 RxPiOn                                  :  1;  // Bits 6:6
+    U32 TxPiOn                                  :  1;  // Bits 7:7
+    U32 InternalClocksOn                        :  1;  // Bits 8:8
+    U32 RepeaterClocksOn                        :  1;  // Bits 9:9
+    U32 TxDisable                               :  1;  // Bits 10:10
+    U32 RxDisable                               :  1;  // Bits 11:11
+    U32 TxLong                                  :  1;  // Bits 12:12
+    U32 RxDqsCtle                               :  2;  // Bits 14:13
+    U32 RxReadPointer                           :  3;  // Bits 17:15
+    U32 DriverSegmentEnable                     :  1;  // Bits 18:18
+    U32 DataVccddqHi                            :  1;  // Bits 19:19
+    U32 ReadRFRd                                :  1;  // Bits 20:20
+    U32 ReadRFWr                                :  1;  // Bits 21:21
+    U32 ReadRFRank                              :  2;  // Bits 23:22
+    U32 ForceOdtOn                              :  1;  // Bits 24:24
+    U32 OdtSampOff                              :  1;  // Bits 25:25
+    U32 DisableOdtStatic                        :  1;  // Bits 26:26
+    U32 DdrCRForceODTOn                         :  1;  // Bits 27:27
+    U32 LPDDR_Mode                              :  1;  // Bits 28:28
+    U32 EnReadPreamble                          :  1;  // Bits 29:29
+    U32 OdtSampExtendEn                         :  1;  // Bits 30:30
+    U32 EarlyRleakEn                            :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA3CH1_CR_DDRCRDATACONTROL0_STRUCT;
+
+typedef union {
+  struct {
+    U32 CAVrefCtl                               :  7;  // Bits 6:0
+    U32 Ch1VrefCtl                              :  7;  // Bits 13:7
+    U32 Ch0VrefCtl                              :  7;  // Bits 20:14
+    U32 EnDimmVrefCA                            :  1;  // Bits 21:21
+    U32 EnDimmVrefCh1                           :  1;  // Bits 22:22
+    U32 EnDimmVrefCh0                           :  1;  // Bits 23:23
+    U32 HiZTimerCtrl                            :  2;  // Bits 25:24
+    U32 VccddqHiQnnnH                           :  1;  // Bits 26:26
+    U32 Rsvd                                    :  2;  // Bits 28:27
+    U32 caSlowBW                                :  1;  // Bits 29:29
+    U32 ch0SlowBW                               :  1;  // Bits 30:30
+    U32 ch1SlowBW                               :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA3CH1_CR_DDRCRVREFADJUST1_STRUCT;
+
+typedef union {
+  struct {
+    U32 RxRcvEnPi                               :  9;  // Bits 8:0
+    U32 RxDqsPPi                                :  6;  // Bits 14:9
+    U32 RxEq                                    :  5;  // Bits 19:15
+    U32 RxDqsNPi                                :  6;  // Bits 25:20
+    U32 RxVref                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA4CH0_CR_RXTRAINRANK0_STRUCT;
+
+typedef union {
+  struct {
+    U32 RxRcvEnPi                               :  9;  // Bits 8:0
+    U32 RxDqsPPi                                :  6;  // Bits 14:9
+    U32 RxEq                                    :  5;  // Bits 19:15
+    U32 RxDqsNPi                                :  6;  // Bits 25:20
+    U32 RxVref                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA4CH0_CR_RXTRAINRANK1_STRUCT;
+
+typedef union {
+  struct {
+    U32 RxRcvEnPi                               :  9;  // Bits 8:0
+    U32 RxDqsPPi                                :  6;  // Bits 14:9
+    U32 RxEq                                    :  5;  // Bits 19:15
+    U32 RxDqsNPi                                :  6;  // Bits 25:20
+    U32 RxVref                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA4CH0_CR_RXTRAINRANK2_STRUCT;
+
+typedef union {
+  struct {
+    U32 RxRcvEnPi                               :  9;  // Bits 8:0
+    U32 RxDqsPPi                                :  6;  // Bits 14:9
+    U32 RxEq                                    :  5;  // Bits 19:15
+    U32 RxDqsNPi                                :  6;  // Bits 25:20
+    U32 RxVref                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA4CH0_CR_RXTRAINRANK3_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA4CH0_CR_RXPERBITRANK0_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA4CH0_CR_RXPERBITRANK1_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA4CH0_CR_RXPERBITRANK2_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA4CH0_CR_RXPERBITRANK3_STRUCT;
+
+typedef union {
+  struct {
+    U32 TxDqDelay                               :  9;  // Bits 8:0
+    U32 TxDqsDelay                              :  9;  // Bits 17:9
+    U32 Spare0                                  :  2;  // Bits 19:18
+    U32 TxEqualization                          :  6;  // Bits 25:20
+    U32 Spare1                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA4CH0_CR_TXTRAINRANK0_STRUCT;
+
+typedef union {
+  struct {
+    U32 TxDqDelay                               :  9;  // Bits 8:0
+    U32 TxDqsDelay                              :  9;  // Bits 17:9
+    U32 Spare0                                  :  2;  // Bits 19:18
+    U32 TxEqualization                          :  6;  // Bits 25:20
+    U32 Spare1                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA4CH0_CR_TXTRAINRANK1_STRUCT;
+
+typedef union {
+  struct {
+    U32 TxDqDelay                               :  9;  // Bits 8:0
+    U32 TxDqsDelay                              :  9;  // Bits 17:9
+    U32 Spare0                                  :  2;  // Bits 19:18
+    U32 TxEqualization                          :  6;  // Bits 25:20
+    U32 Spare1                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA4CH0_CR_TXTRAINRANK2_STRUCT;
+
+typedef union {
+  struct {
+    U32 TxDqDelay                               :  9;  // Bits 8:0
+    U32 TxDqsDelay                              :  9;  // Bits 17:9
+    U32 Spare0                                  :  2;  // Bits 19:18
+    U32 TxEqualization                          :  6;  // Bits 25:20
+    U32 Spare1                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA4CH0_CR_TXTRAINRANK3_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA4CH0_CR_TXPERBITRANK0_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA4CH0_CR_TXPERBITRANK1_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA4CH0_CR_TXPERBITRANK2_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA4CH0_CR_TXPERBITRANK3_STRUCT;
+
+typedef union {
+  struct {
+    U32 RcompDrvUp                              :  6;  // Bits 5:0
+    U32 Spare0                                  :  3;  // Bits 8:6
+    U32 RcompDrvDown                            :  6;  // Bits 14:9
+    U32 VTComp                                  :  5;  // Bits 19:15
+    U32 TcoComp                                 :  6;  // Bits 25:20
+    U32 SlewRateComp                            :  5;  // Bits 30:26
+    U32 Spare2                                  :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA4CH0_CR_RCOMPDATA0_STRUCT;
+
+typedef union {
+  struct {
+    U32 RcompOdtUp                              :  6;  // Bits 5:0
+    U32 Spare0                                  :  3;  // Bits 8:6
+    U32 RcompOdtDown                            :  6;  // Bits 14:9
+    U32 Spare1                                  :  1;  // Bits 15:15
+    U32 PanicDrvDn                              :  6;  // Bits 21:16
+    U32 PanicDrvUp                              :  6;  // Bits 27:22
+    U32 LevelShifterComp                        :  3;  // Bits 30:28
+    U32 Spare2                                  :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA4CH0_CR_RCOMPDATA1_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA4CH0_CR_TXXTALK_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA4CH0_CR_RXOFFSETVDQ_STRUCT;
+
+typedef union {
+  struct {
+    U32 Spare                                   :  32;  // Bits 31:0
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA4CH0_CR_DDRDATARESERVED_STRUCT;
+
+typedef union {
+  struct {
+    U32 DataTrainFeedback                       :  9;  // Bits 8:0
+    U32 Spare                                   :  23;  // Bits 31:9
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA4CH0_CR_DATATRAINFEEDBACK_STRUCT;
+
+typedef union {
+  struct {
+    U32 RunTest                                 :  1;  // Bits 0:0
+    U32 Load                                    :  1;  // Bits 1:1
+    U32 ModeHVM                                 :  1;  // Bits 2:2
+    U32 ModeDV                                  :  1;  // Bits 3:3
+    U32 ModeADC                                 :  1;  // Bits 4:4
+    U32 LoadCount                               :  10;  // Bits 14:5
+    U32 CountStatus                             :  10;  // Bits 24:15
+    U32 Spare                                   :  7;  // Bits 31:25
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA4CH0_CR_DLLPITESTANDADC_STRUCT;
+
+typedef union {
+  struct {
+    U32 DqDrvUpCompOffset                       :  6;  // Bits 5:0
+    U32 DqDrvDownCompOffset                     :  6;  // Bits 11:6
+    U32 DqOdtUpCompOffset                       :  5;  // Bits 16:12
+    U32 DqOdtDownCompOffset                     :  5;  // Bits 21:17
+    U32 DqTcoCompOffset                         :  5;  // Bits 26:22
+    U32 DqSlewRateCompOffset                    :  5;  // Bits 31:27
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA4CH0_CR_DDRCRDATAOFFSETCOMP_STRUCT;
+
+typedef union {
+  struct {
+    U32 RefPi                                   :  4;  // Bits 3:0
+    U32 DllMask                                 :  2;  // Bits 5:4
+    U32 DllWeakLock                             :  1;  // Bits 6:6
+    U32 SdllSegmentDisable                      :  3;  // Bits 9:7
+    U32 RxBiasCtl                               :  3;  // Bits 12:10
+    U32 OdtDelay                                :  4;  // Bits 16:13
+    U32 OdtDuration                             :  3;  // Bits 19:17
+    U32 SenseAmpDelay                           :  4;  // Bits 23:20
+    U32 SenseAmpDuration                        :  3;  // Bits 26:24
+    U32 BurstEndODTDelay                        :  3;  // Bits 29:27
+    U32 LpDdrLongOdtEn                          :  1;  // Bits 30:30
+    U32 Rsvd1                                   :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA4CH0_CR_DDRCRDATACONTROL1_STRUCT;
+
+typedef union {
+  struct {
+    U32 RxStaggerCtl                            :  5;  // Bits 4:0
+    U32 ForceBiasOn                             :  1;  // Bits 5:5
+    U32 ForceRxOn                               :  1;  // Bits 6:6
+    U32 LeakerComp                              :  2;  // Bits 8:7
+    U32 RxDqsAmpOffset                          :  4;  // Bits 12:9
+    U32 RxClkStgNum                             :  5;  // Bits 17:13
+    U32 WlLongDelEn                             :  1;  // Bits 18:18
+    U32 Spare                                   :  13;  // Bits 31:19
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA4CH0_CR_DDRCRDATACONTROL2_STRUCT;
+
+typedef union {
+  struct {
+    U32 VssHiOrVrefCtl                          :  24;  // Bits 23:0
+    U32 OutputCode                              :  8;  // Bits 31:24
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA4CH0_CR_DDRCRVSSHIORVREFCONTROL_STRUCT;
+
+typedef union {
+  struct {
+    U32 RcvEnOffset                             :  6;  // Bits 5:0
+    U32 RxDqsOffset                             :  6;  // Bits 11:6
+    U32 TxDqOffset                              :  6;  // Bits 17:12
+    U32 TxDqsOffset                             :  6;  // Bits 23:18
+    U32 VrefOffset                              :  7;  // Bits 30:24
+    U32 Spare                                   :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA4CH0_CR_DDRCRDATAOFFSETTRAIN_STRUCT;
+
+typedef union {
+  struct {
+    U32 RxTrainingMode                          :  1;  // Bits 0:0
+    U32 WLTrainingMode                          :  1;  // Bits 1:1
+    U32 RLTrainingMode                          :  1;  // Bits 2:2
+    U32 SenseampTrainingMode                    :  1;  // Bits 3:3
+    U32 TxOn                                    :  1;  // Bits 4:4
+    U32 RfOn                                    :  1;  // Bits 5:5
+    U32 RxPiOn                                  :  1;  // Bits 6:6
+    U32 TxPiOn                                  :  1;  // Bits 7:7
+    U32 InternalClocksOn                        :  1;  // Bits 8:8
+    U32 RepeaterClocksOn                        :  1;  // Bits 9:9
+    U32 TxDisable                               :  1;  // Bits 10:10
+    U32 RxDisable                               :  1;  // Bits 11:11
+    U32 TxLong                                  :  1;  // Bits 12:12
+    U32 RxDqsCtle                               :  2;  // Bits 14:13
+    U32 RxReadPointer                           :  3;  // Bits 17:15
+    U32 DriverSegmentEnable                     :  1;  // Bits 18:18
+    U32 DataVccddqHi                            :  1;  // Bits 19:19
+    U32 ReadRFRd                                :  1;  // Bits 20:20
+    U32 ReadRFWr                                :  1;  // Bits 21:21
+    U32 ReadRFRank                              :  2;  // Bits 23:22
+    U32 ForceOdtOn                              :  1;  // Bits 24:24
+    U32 OdtSampOff                              :  1;  // Bits 25:25
+    U32 DisableOdtStatic                        :  1;  // Bits 26:26
+    U32 DdrCRForceODTOn                         :  1;  // Bits 27:27
+    U32 LPDDR_Mode                              :  1;  // Bits 28:28
+    U32 EnReadPreamble                          :  1;  // Bits 29:29
+    U32 OdtSampExtendEn                         :  1;  // Bits 30:30
+    U32 EarlyRleakEn                            :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA4CH0_CR_DDRCRDATACONTROL0_STRUCT;
+
+typedef union {
+  struct {
+    U32 CAVrefCtl                               :  7;  // Bits 6:0
+    U32 Ch1VrefCtl                              :  7;  // Bits 13:7
+    U32 Ch0VrefCtl                              :  7;  // Bits 20:14
+    U32 EnDimmVrefCA                            :  1;  // Bits 21:21
+    U32 EnDimmVrefCh1                           :  1;  // Bits 22:22
+    U32 EnDimmVrefCh0                           :  1;  // Bits 23:23
+    U32 HiZTimerCtrl                            :  2;  // Bits 25:24
+    U32 VccddqHiQnnnH                           :  1;  // Bits 26:26
+    U32 Rsvd                                    :  2;  // Bits 28:27
+    U32 caSlowBW                                :  1;  // Bits 29:29
+    U32 ch0SlowBW                               :  1;  // Bits 30:30
+    U32 ch1SlowBW                               :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA4CH0_CR_DDRCRVREFADJUST1_STRUCT;
+
+typedef union {
+  struct {
+    U32 RxRcvEnPi                               :  9;  // Bits 8:0
+    U32 RxDqsPPi                                :  6;  // Bits 14:9
+    U32 RxEq                                    :  5;  // Bits 19:15
+    U32 RxDqsNPi                                :  6;  // Bits 25:20
+    U32 RxVref                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA4CH1_CR_RXTRAINRANK0_STRUCT;
+
+typedef union {
+  struct {
+    U32 RxRcvEnPi                               :  9;  // Bits 8:0
+    U32 RxDqsPPi                                :  6;  // Bits 14:9
+    U32 RxEq                                    :  5;  // Bits 19:15
+    U32 RxDqsNPi                                :  6;  // Bits 25:20
+    U32 RxVref                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA4CH1_CR_RXTRAINRANK1_STRUCT;
+
+typedef union {
+  struct {
+    U32 RxRcvEnPi                               :  9;  // Bits 8:0
+    U32 RxDqsPPi                                :  6;  // Bits 14:9
+    U32 RxEq                                    :  5;  // Bits 19:15
+    U32 RxDqsNPi                                :  6;  // Bits 25:20
+    U32 RxVref                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA4CH1_CR_RXTRAINRANK2_STRUCT;
+
+typedef union {
+  struct {
+    U32 RxRcvEnPi                               :  9;  // Bits 8:0
+    U32 RxDqsPPi                                :  6;  // Bits 14:9
+    U32 RxEq                                    :  5;  // Bits 19:15
+    U32 RxDqsNPi                                :  6;  // Bits 25:20
+    U32 RxVref                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA4CH1_CR_RXTRAINRANK3_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA4CH1_CR_RXPERBITRANK0_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA4CH1_CR_RXPERBITRANK1_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA4CH1_CR_RXPERBITRANK2_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA4CH1_CR_RXPERBITRANK3_STRUCT;
+
+typedef union {
+  struct {
+    U32 TxDqDelay                               :  9;  // Bits 8:0
+    U32 TxDqsDelay                              :  9;  // Bits 17:9
+    U32 Spare0                                  :  2;  // Bits 19:18
+    U32 TxEqualization                          :  6;  // Bits 25:20
+    U32 Spare1                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA4CH1_CR_TXTRAINRANK0_STRUCT;
+
+typedef union {
+  struct {
+    U32 TxDqDelay                               :  9;  // Bits 8:0
+    U32 TxDqsDelay                              :  9;  // Bits 17:9
+    U32 Spare0                                  :  2;  // Bits 19:18
+    U32 TxEqualization                          :  6;  // Bits 25:20
+    U32 Spare1                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA4CH1_CR_TXTRAINRANK1_STRUCT;
+
+typedef union {
+  struct {
+    U32 TxDqDelay                               :  9;  // Bits 8:0
+    U32 TxDqsDelay                              :  9;  // Bits 17:9
+    U32 Spare0                                  :  2;  // Bits 19:18
+    U32 TxEqualization                          :  6;  // Bits 25:20
+    U32 Spare1                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA4CH1_CR_TXTRAINRANK2_STRUCT;
+
+typedef union {
+  struct {
+    U32 TxDqDelay                               :  9;  // Bits 8:0
+    U32 TxDqsDelay                              :  9;  // Bits 17:9
+    U32 Spare0                                  :  2;  // Bits 19:18
+    U32 TxEqualization                          :  6;  // Bits 25:20
+    U32 Spare1                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA4CH1_CR_TXTRAINRANK3_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA4CH1_CR_TXPERBITRANK0_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA4CH1_CR_TXPERBITRANK1_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA4CH1_CR_TXPERBITRANK2_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA4CH1_CR_TXPERBITRANK3_STRUCT;
+
+typedef union {
+  struct {
+    U32 RcompDrvUp                              :  6;  // Bits 5:0
+    U32 Spare0                                  :  3;  // Bits 8:6
+    U32 RcompDrvDown                            :  6;  // Bits 14:9
+    U32 VTComp                                  :  5;  // Bits 19:15
+    U32 TcoComp                                 :  6;  // Bits 25:20
+    U32 SlewRateComp                            :  5;  // Bits 30:26
+    U32 Spare2                                  :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA4CH1_CR_RCOMPDATA0_STRUCT;
+
+typedef union {
+  struct {
+    U32 RcompOdtUp                              :  6;  // Bits 5:0
+    U32 Spare0                                  :  3;  // Bits 8:6
+    U32 RcompOdtDown                            :  6;  // Bits 14:9
+    U32 Spare1                                  :  1;  // Bits 15:15
+    U32 PanicDrvDn                              :  6;  // Bits 21:16
+    U32 PanicDrvUp                              :  6;  // Bits 27:22
+    U32 LevelShifterComp                        :  3;  // Bits 30:28
+    U32 Spare2                                  :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA4CH1_CR_RCOMPDATA1_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA4CH1_CR_TXXTALK_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA4CH1_CR_RXOFFSETVDQ_STRUCT;
+
+typedef union {
+  struct {
+    U32 Spare                                   :  32;  // Bits 31:0
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA4CH1_CR_DDRDATARESERVED_STRUCT;
+
+typedef union {
+  struct {
+    U32 DataTrainFeedback                       :  9;  // Bits 8:0
+    U32 Spare                                   :  23;  // Bits 31:9
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA4CH1_CR_DATATRAINFEEDBACK_STRUCT;
+
+typedef union {
+  struct {
+    U32 RunTest                                 :  1;  // Bits 0:0
+    U32 Load                                    :  1;  // Bits 1:1
+    U32 ModeHVM                                 :  1;  // Bits 2:2
+    U32 ModeDV                                  :  1;  // Bits 3:3
+    U32 ModeADC                                 :  1;  // Bits 4:4
+    U32 LoadCount                               :  10;  // Bits 14:5
+    U32 CountStatus                             :  10;  // Bits 24:15
+    U32 Spare                                   :  7;  // Bits 31:25
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA4CH1_CR_DLLPITESTANDADC_STRUCT;
+
+typedef union {
+  struct {
+    U32 DqDrvUpCompOffset                       :  6;  // Bits 5:0
+    U32 DqDrvDownCompOffset                     :  6;  // Bits 11:6
+    U32 DqOdtUpCompOffset                       :  5;  // Bits 16:12
+    U32 DqOdtDownCompOffset                     :  5;  // Bits 21:17
+    U32 DqTcoCompOffset                         :  5;  // Bits 26:22
+    U32 DqSlewRateCompOffset                    :  5;  // Bits 31:27
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA4CH1_CR_DDRCRDATAOFFSETCOMP_STRUCT;
+
+typedef union {
+  struct {
+    U32 RefPi                                   :  4;  // Bits 3:0
+    U32 DllMask                                 :  2;  // Bits 5:4
+    U32 DllWeakLock                             :  1;  // Bits 6:6
+    U32 SdllSegmentDisable                      :  3;  // Bits 9:7
+    U32 RxBiasCtl                               :  3;  // Bits 12:10
+    U32 OdtDelay                                :  4;  // Bits 16:13
+    U32 OdtDuration                             :  3;  // Bits 19:17
+    U32 SenseAmpDelay                           :  4;  // Bits 23:20
+    U32 SenseAmpDuration                        :  3;  // Bits 26:24
+    U32 BurstEndODTDelay                        :  3;  // Bits 29:27
+    U32 LpDdrLongOdtEn                          :  1;  // Bits 30:30
+    U32 Rsvd1                                   :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA4CH1_CR_DDRCRDATACONTROL1_STRUCT;
+
+typedef union {
+  struct {
+    U32 RxStaggerCtl                            :  5;  // Bits 4:0
+    U32 ForceBiasOn                             :  1;  // Bits 5:5
+    U32 ForceRxOn                               :  1;  // Bits 6:6
+    U32 LeakerComp                              :  2;  // Bits 8:7
+    U32 RxDqsAmpOffset                          :  4;  // Bits 12:9
+    U32 RxClkStgNum                             :  5;  // Bits 17:13
+    U32 WlLongDelEn                             :  1;  // Bits 18:18
+    U32 Spare                                   :  13;  // Bits 31:19
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA4CH1_CR_DDRCRDATACONTROL2_STRUCT;
+
+typedef union {
+  struct {
+    U32 VssHiOrVrefCtl                          :  24;  // Bits 23:0
+    U32 OutputCode                              :  8;  // Bits 31:24
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA4CH1_CR_DDRCRVSSHIORVREFCONTROL_STRUCT;
+
+typedef union {
+  struct {
+    U32 RcvEnOffset                             :  6;  // Bits 5:0
+    U32 RxDqsOffset                             :  6;  // Bits 11:6
+    U32 TxDqOffset                              :  6;  // Bits 17:12
+    U32 TxDqsOffset                             :  6;  // Bits 23:18
+    U32 VrefOffset                              :  7;  // Bits 30:24
+    U32 Spare                                   :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA4CH1_CR_DDRCRDATAOFFSETTRAIN_STRUCT;
+
+typedef union {
+  struct {
+    U32 RxTrainingMode                          :  1;  // Bits 0:0
+    U32 WLTrainingMode                          :  1;  // Bits 1:1
+    U32 RLTrainingMode                          :  1;  // Bits 2:2
+    U32 SenseampTrainingMode                    :  1;  // Bits 3:3
+    U32 TxOn                                    :  1;  // Bits 4:4
+    U32 RfOn                                    :  1;  // Bits 5:5
+    U32 RxPiOn                                  :  1;  // Bits 6:6
+    U32 TxPiOn                                  :  1;  // Bits 7:7
+    U32 InternalClocksOn                        :  1;  // Bits 8:8
+    U32 RepeaterClocksOn                        :  1;  // Bits 9:9
+    U32 TxDisable                               :  1;  // Bits 10:10
+    U32 RxDisable                               :  1;  // Bits 11:11
+    U32 TxLong                                  :  1;  // Bits 12:12
+    U32 RxDqsCtle                               :  2;  // Bits 14:13
+    U32 RxReadPointer                           :  3;  // Bits 17:15
+    U32 DriverSegmentEnable                     :  1;  // Bits 18:18
+    U32 DataVccddqHi                            :  1;  // Bits 19:19
+    U32 ReadRFRd                                :  1;  // Bits 20:20
+    U32 ReadRFWr                                :  1;  // Bits 21:21
+    U32 ReadRFRank                              :  2;  // Bits 23:22
+    U32 ForceOdtOn                              :  1;  // Bits 24:24
+    U32 OdtSampOff                              :  1;  // Bits 25:25
+    U32 DisableOdtStatic                        :  1;  // Bits 26:26
+    U32 DdrCRForceODTOn                         :  1;  // Bits 27:27
+    U32 LPDDR_Mode                              :  1;  // Bits 28:28
+    U32 EnReadPreamble                          :  1;  // Bits 29:29
+    U32 OdtSampExtendEn                         :  1;  // Bits 30:30
+    U32 EarlyRleakEn                            :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA4CH1_CR_DDRCRDATACONTROL0_STRUCT;
+
+typedef union {
+  struct {
+    U32 CAVrefCtl                               :  7;  // Bits 6:0
+    U32 Ch1VrefCtl                              :  7;  // Bits 13:7
+    U32 Ch0VrefCtl                              :  7;  // Bits 20:14
+    U32 EnDimmVrefCA                            :  1;  // Bits 21:21
+    U32 EnDimmVrefCh1                           :  1;  // Bits 22:22
+    U32 EnDimmVrefCh0                           :  1;  // Bits 23:23
+    U32 HiZTimerCtrl                            :  2;  // Bits 25:24
+    U32 VccddqHiQnnnH                           :  1;  // Bits 26:26
+    U32 Rsvd                                    :  2;  // Bits 28:27
+    U32 caSlowBW                                :  1;  // Bits 29:29
+    U32 ch0SlowBW                               :  1;  // Bits 30:30
+    U32 ch1SlowBW                               :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA4CH1_CR_DDRCRVREFADJUST1_STRUCT;
+
+typedef union {
+  struct {
+    U32 RxRcvEnPi                               :  9;  // Bits 8:0
+    U32 RxDqsPPi                                :  6;  // Bits 14:9
+    U32 RxEq                                    :  5;  // Bits 19:15
+    U32 RxDqsNPi                                :  6;  // Bits 25:20
+    U32 RxVref                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA5CH0_CR_RXTRAINRANK0_STRUCT;
+
+typedef union {
+  struct {
+    U32 RxRcvEnPi                               :  9;  // Bits 8:0
+    U32 RxDqsPPi                                :  6;  // Bits 14:9
+    U32 RxEq                                    :  5;  // Bits 19:15
+    U32 RxDqsNPi                                :  6;  // Bits 25:20
+    U32 RxVref                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA5CH0_CR_RXTRAINRANK1_STRUCT;
+
+typedef union {
+  struct {
+    U32 RxRcvEnPi                               :  9;  // Bits 8:0
+    U32 RxDqsPPi                                :  6;  // Bits 14:9
+    U32 RxEq                                    :  5;  // Bits 19:15
+    U32 RxDqsNPi                                :  6;  // Bits 25:20
+    U32 RxVref                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA5CH0_CR_RXTRAINRANK2_STRUCT;
+
+typedef union {
+  struct {
+    U32 RxRcvEnPi                               :  9;  // Bits 8:0
+    U32 RxDqsPPi                                :  6;  // Bits 14:9
+    U32 RxEq                                    :  5;  // Bits 19:15
+    U32 RxDqsNPi                                :  6;  // Bits 25:20
+    U32 RxVref                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA5CH0_CR_RXTRAINRANK3_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA5CH0_CR_RXPERBITRANK0_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA5CH0_CR_RXPERBITRANK1_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA5CH0_CR_RXPERBITRANK2_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA5CH0_CR_RXPERBITRANK3_STRUCT;
+
+typedef union {
+  struct {
+    U32 TxDqDelay                               :  9;  // Bits 8:0
+    U32 TxDqsDelay                              :  9;  // Bits 17:9
+    U32 Spare0                                  :  2;  // Bits 19:18
+    U32 TxEqualization                          :  6;  // Bits 25:20
+    U32 Spare1                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA5CH0_CR_TXTRAINRANK0_STRUCT;
+
+typedef union {
+  struct {
+    U32 TxDqDelay                               :  9;  // Bits 8:0
+    U32 TxDqsDelay                              :  9;  // Bits 17:9
+    U32 Spare0                                  :  2;  // Bits 19:18
+    U32 TxEqualization                          :  6;  // Bits 25:20
+    U32 Spare1                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA5CH0_CR_TXTRAINRANK1_STRUCT;
+
+typedef union {
+  struct {
+    U32 TxDqDelay                               :  9;  // Bits 8:0
+    U32 TxDqsDelay                              :  9;  // Bits 17:9
+    U32 Spare0                                  :  2;  // Bits 19:18
+    U32 TxEqualization                          :  6;  // Bits 25:20
+    U32 Spare1                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA5CH0_CR_TXTRAINRANK2_STRUCT;
+
+typedef union {
+  struct {
+    U32 TxDqDelay                               :  9;  // Bits 8:0
+    U32 TxDqsDelay                              :  9;  // Bits 17:9
+    U32 Spare0                                  :  2;  // Bits 19:18
+    U32 TxEqualization                          :  6;  // Bits 25:20
+    U32 Spare1                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA5CH0_CR_TXTRAINRANK3_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA5CH0_CR_TXPERBITRANK0_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA5CH0_CR_TXPERBITRANK1_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA5CH0_CR_TXPERBITRANK2_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA5CH0_CR_TXPERBITRANK3_STRUCT;
+
+typedef union {
+  struct {
+    U32 RcompDrvUp                              :  6;  // Bits 5:0
+    U32 Spare0                                  :  3;  // Bits 8:6
+    U32 RcompDrvDown                            :  6;  // Bits 14:9
+    U32 VTComp                                  :  5;  // Bits 19:15
+    U32 TcoComp                                 :  6;  // Bits 25:20
+    U32 SlewRateComp                            :  5;  // Bits 30:26
+    U32 Spare2                                  :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA5CH0_CR_RCOMPDATA0_STRUCT;
+
+typedef union {
+  struct {
+    U32 RcompOdtUp                              :  6;  // Bits 5:0
+    U32 Spare0                                  :  3;  // Bits 8:6
+    U32 RcompOdtDown                            :  6;  // Bits 14:9
+    U32 Spare1                                  :  1;  // Bits 15:15
+    U32 PanicDrvDn                              :  6;  // Bits 21:16
+    U32 PanicDrvUp                              :  6;  // Bits 27:22
+    U32 LevelShifterComp                        :  3;  // Bits 30:28
+    U32 Spare2                                  :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA5CH0_CR_RCOMPDATA1_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA5CH0_CR_TXXTALK_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA5CH0_CR_RXOFFSETVDQ_STRUCT;
+
+typedef union {
+  struct {
+    U32 Spare                                   :  32;  // Bits 31:0
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA5CH0_CR_DDRDATARESERVED_STRUCT;
+
+typedef union {
+  struct {
+    U32 DataTrainFeedback                       :  9;  // Bits 8:0
+    U32 Spare                                   :  23;  // Bits 31:9
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA5CH0_CR_DATATRAINFEEDBACK_STRUCT;
+
+typedef union {
+  struct {
+    U32 RunTest                                 :  1;  // Bits 0:0
+    U32 Load                                    :  1;  // Bits 1:1
+    U32 ModeHVM                                 :  1;  // Bits 2:2
+    U32 ModeDV                                  :  1;  // Bits 3:3
+    U32 ModeADC                                 :  1;  // Bits 4:4
+    U32 LoadCount                               :  10;  // Bits 14:5
+    U32 CountStatus                             :  10;  // Bits 24:15
+    U32 Spare                                   :  7;  // Bits 31:25
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA5CH0_CR_DLLPITESTANDADC_STRUCT;
+
+typedef union {
+  struct {
+    U32 DqDrvUpCompOffset                       :  6;  // Bits 5:0
+    U32 DqDrvDownCompOffset                     :  6;  // Bits 11:6
+    U32 DqOdtUpCompOffset                       :  5;  // Bits 16:12
+    U32 DqOdtDownCompOffset                     :  5;  // Bits 21:17
+    U32 DqTcoCompOffset                         :  5;  // Bits 26:22
+    U32 DqSlewRateCompOffset                    :  5;  // Bits 31:27
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA5CH0_CR_DDRCRDATAOFFSETCOMP_STRUCT;
+
+typedef union {
+  struct {
+    U32 RefPi                                   :  4;  // Bits 3:0
+    U32 DllMask                                 :  2;  // Bits 5:4
+    U32 DllWeakLock                             :  1;  // Bits 6:6
+    U32 SdllSegmentDisable                      :  3;  // Bits 9:7
+    U32 RxBiasCtl                               :  3;  // Bits 12:10
+    U32 OdtDelay                                :  4;  // Bits 16:13
+    U32 OdtDuration                             :  3;  // Bits 19:17
+    U32 SenseAmpDelay                           :  4;  // Bits 23:20
+    U32 SenseAmpDuration                        :  3;  // Bits 26:24
+    U32 BurstEndODTDelay                        :  3;  // Bits 29:27
+    U32 LpDdrLongOdtEn                          :  1;  // Bits 30:30
+    U32 Rsvd1                                   :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA5CH0_CR_DDRCRDATACONTROL1_STRUCT;
+
+typedef union {
+  struct {
+    U32 RxStaggerCtl                            :  5;  // Bits 4:0
+    U32 ForceBiasOn                             :  1;  // Bits 5:5
+    U32 ForceRxOn                               :  1;  // Bits 6:6
+    U32 LeakerComp                              :  2;  // Bits 8:7
+    U32 RxDqsAmpOffset                          :  4;  // Bits 12:9
+    U32 RxClkStgNum                             :  5;  // Bits 17:13
+    U32 WlLongDelEn                             :  1;  // Bits 18:18
+    U32 Spare                                   :  13;  // Bits 31:19
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA5CH0_CR_DDRCRDATACONTROL2_STRUCT;
+
+typedef union {
+  struct {
+    U32 VssHiOrVrefCtl                          :  24;  // Bits 23:0
+    U32 OutputCode                              :  8;  // Bits 31:24
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA5CH0_CR_DDRCRVSSHIORVREFCONTROL_STRUCT;
+
+typedef union {
+  struct {
+    U32 RcvEnOffset                             :  6;  // Bits 5:0
+    U32 RxDqsOffset                             :  6;  // Bits 11:6
+    U32 TxDqOffset                              :  6;  // Bits 17:12
+    U32 TxDqsOffset                             :  6;  // Bits 23:18
+    U32 VrefOffset                              :  7;  // Bits 30:24
+    U32 Spare                                   :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA5CH0_CR_DDRCRDATAOFFSETTRAIN_STRUCT;
+
+typedef union {
+  struct {
+    U32 RxTrainingMode                          :  1;  // Bits 0:0
+    U32 WLTrainingMode                          :  1;  // Bits 1:1
+    U32 RLTrainingMode                          :  1;  // Bits 2:2
+    U32 SenseampTrainingMode                    :  1;  // Bits 3:3
+    U32 TxOn                                    :  1;  // Bits 4:4
+    U32 RfOn                                    :  1;  // Bits 5:5
+    U32 RxPiOn                                  :  1;  // Bits 6:6
+    U32 TxPiOn                                  :  1;  // Bits 7:7
+    U32 InternalClocksOn                        :  1;  // Bits 8:8
+    U32 RepeaterClocksOn                        :  1;  // Bits 9:9
+    U32 TxDisable                               :  1;  // Bits 10:10
+    U32 RxDisable                               :  1;  // Bits 11:11
+    U32 TxLong                                  :  1;  // Bits 12:12
+    U32 RxDqsCtle                               :  2;  // Bits 14:13
+    U32 RxReadPointer                           :  3;  // Bits 17:15
+    U32 DriverSegmentEnable                     :  1;  // Bits 18:18
+    U32 DataVccddqHi                            :  1;  // Bits 19:19
+    U32 ReadRFRd                                :  1;  // Bits 20:20
+    U32 ReadRFWr                                :  1;  // Bits 21:21
+    U32 ReadRFRank                              :  2;  // Bits 23:22
+    U32 ForceOdtOn                              :  1;  // Bits 24:24
+    U32 OdtSampOff                              :  1;  // Bits 25:25
+    U32 DisableOdtStatic                        :  1;  // Bits 26:26
+    U32 DdrCRForceODTOn                         :  1;  // Bits 27:27
+    U32 LPDDR_Mode                              :  1;  // Bits 28:28
+    U32 EnReadPreamble                          :  1;  // Bits 29:29
+    U32 OdtSampExtendEn                         :  1;  // Bits 30:30
+    U32 EarlyRleakEn                            :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA5CH0_CR_DDRCRDATACONTROL0_STRUCT;
+
+typedef union {
+  struct {
+    U32 CAVrefCtl                               :  7;  // Bits 6:0
+    U32 Ch1VrefCtl                              :  7;  // Bits 13:7
+    U32 Ch0VrefCtl                              :  7;  // Bits 20:14
+    U32 EnDimmVrefCA                            :  1;  // Bits 21:21
+    U32 EnDimmVrefCh1                           :  1;  // Bits 22:22
+    U32 EnDimmVrefCh0                           :  1;  // Bits 23:23
+    U32 HiZTimerCtrl                            :  2;  // Bits 25:24
+    U32 VccddqHiQnnnH                           :  1;  // Bits 26:26
+    U32 Rsvd                                    :  2;  // Bits 28:27
+    U32 caSlowBW                                :  1;  // Bits 29:29
+    U32 ch0SlowBW                               :  1;  // Bits 30:30
+    U32 ch1SlowBW                               :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA5CH0_CR_DDRCRVREFADJUST1_STRUCT;
+
+typedef union {
+  struct {
+    U32 RxRcvEnPi                               :  9;  // Bits 8:0
+    U32 RxDqsPPi                                :  6;  // Bits 14:9
+    U32 RxEq                                    :  5;  // Bits 19:15
+    U32 RxDqsNPi                                :  6;  // Bits 25:20
+    U32 RxVref                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA5CH1_CR_RXTRAINRANK0_STRUCT;
+
+typedef union {
+  struct {
+    U32 RxRcvEnPi                               :  9;  // Bits 8:0
+    U32 RxDqsPPi                                :  6;  // Bits 14:9
+    U32 RxEq                                    :  5;  // Bits 19:15
+    U32 RxDqsNPi                                :  6;  // Bits 25:20
+    U32 RxVref                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA5CH1_CR_RXTRAINRANK1_STRUCT;
+
+typedef union {
+  struct {
+    U32 RxRcvEnPi                               :  9;  // Bits 8:0
+    U32 RxDqsPPi                                :  6;  // Bits 14:9
+    U32 RxEq                                    :  5;  // Bits 19:15
+    U32 RxDqsNPi                                :  6;  // Bits 25:20
+    U32 RxVref                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA5CH1_CR_RXTRAINRANK2_STRUCT;
+
+typedef union {
+  struct {
+    U32 RxRcvEnPi                               :  9;  // Bits 8:0
+    U32 RxDqsPPi                                :  6;  // Bits 14:9
+    U32 RxEq                                    :  5;  // Bits 19:15
+    U32 RxDqsNPi                                :  6;  // Bits 25:20
+    U32 RxVref                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA5CH1_CR_RXTRAINRANK3_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA5CH1_CR_RXPERBITRANK0_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA5CH1_CR_RXPERBITRANK1_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA5CH1_CR_RXPERBITRANK2_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA5CH1_CR_RXPERBITRANK3_STRUCT;
+
+typedef union {
+  struct {
+    U32 TxDqDelay                               :  9;  // Bits 8:0
+    U32 TxDqsDelay                              :  9;  // Bits 17:9
+    U32 Spare0                                  :  2;  // Bits 19:18
+    U32 TxEqualization                          :  6;  // Bits 25:20
+    U32 Spare1                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA5CH1_CR_TXTRAINRANK0_STRUCT;
+
+typedef union {
+  struct {
+    U32 TxDqDelay                               :  9;  // Bits 8:0
+    U32 TxDqsDelay                              :  9;  // Bits 17:9
+    U32 Spare0                                  :  2;  // Bits 19:18
+    U32 TxEqualization                          :  6;  // Bits 25:20
+    U32 Spare1                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA5CH1_CR_TXTRAINRANK1_STRUCT;
+
+typedef union {
+  struct {
+    U32 TxDqDelay                               :  9;  // Bits 8:0
+    U32 TxDqsDelay                              :  9;  // Bits 17:9
+    U32 Spare0                                  :  2;  // Bits 19:18
+    U32 TxEqualization                          :  6;  // Bits 25:20
+    U32 Spare1                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA5CH1_CR_TXTRAINRANK2_STRUCT;
+
+typedef union {
+  struct {
+    U32 TxDqDelay                               :  9;  // Bits 8:0
+    U32 TxDqsDelay                              :  9;  // Bits 17:9
+    U32 Spare0                                  :  2;  // Bits 19:18
+    U32 TxEqualization                          :  6;  // Bits 25:20
+    U32 Spare1                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA5CH1_CR_TXTRAINRANK3_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA5CH1_CR_TXPERBITRANK0_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA5CH1_CR_TXPERBITRANK1_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA5CH1_CR_TXPERBITRANK2_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA5CH1_CR_TXPERBITRANK3_STRUCT;
+
+typedef union {
+  struct {
+    U32 RcompDrvUp                              :  6;  // Bits 5:0
+    U32 Spare0                                  :  3;  // Bits 8:6
+    U32 RcompDrvDown                            :  6;  // Bits 14:9
+    U32 VTComp                                  :  5;  // Bits 19:15
+    U32 TcoComp                                 :  6;  // Bits 25:20
+    U32 SlewRateComp                            :  5;  // Bits 30:26
+    U32 Spare2                                  :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA5CH1_CR_RCOMPDATA0_STRUCT;
+
+typedef union {
+  struct {
+    U32 RcompOdtUp                              :  6;  // Bits 5:0
+    U32 Spare0                                  :  3;  // Bits 8:6
+    U32 RcompOdtDown                            :  6;  // Bits 14:9
+    U32 Spare1                                  :  1;  // Bits 15:15
+    U32 PanicDrvDn                              :  6;  // Bits 21:16
+    U32 PanicDrvUp                              :  6;  // Bits 27:22
+    U32 LevelShifterComp                        :  3;  // Bits 30:28
+    U32 Spare2                                  :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA5CH1_CR_RCOMPDATA1_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA5CH1_CR_TXXTALK_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA5CH1_CR_RXOFFSETVDQ_STRUCT;
+
+typedef union {
+  struct {
+    U32 Spare                                   :  32;  // Bits 31:0
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA5CH1_CR_DDRDATARESERVED_STRUCT;
+
+typedef union {
+  struct {
+    U32 DataTrainFeedback                       :  9;  // Bits 8:0
+    U32 Spare                                   :  23;  // Bits 31:9
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA5CH1_CR_DATATRAINFEEDBACK_STRUCT;
+
+typedef union {
+  struct {
+    U32 RunTest                                 :  1;  // Bits 0:0
+    U32 Load                                    :  1;  // Bits 1:1
+    U32 ModeHVM                                 :  1;  // Bits 2:2
+    U32 ModeDV                                  :  1;  // Bits 3:3
+    U32 ModeADC                                 :  1;  // Bits 4:4
+    U32 LoadCount                               :  10;  // Bits 14:5
+    U32 CountStatus                             :  10;  // Bits 24:15
+    U32 Spare                                   :  7;  // Bits 31:25
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA5CH1_CR_DLLPITESTANDADC_STRUCT;
+
+typedef union {
+  struct {
+    U32 DqDrvUpCompOffset                       :  6;  // Bits 5:0
+    U32 DqDrvDownCompOffset                     :  6;  // Bits 11:6
+    U32 DqOdtUpCompOffset                       :  5;  // Bits 16:12
+    U32 DqOdtDownCompOffset                     :  5;  // Bits 21:17
+    U32 DqTcoCompOffset                         :  5;  // Bits 26:22
+    U32 DqSlewRateCompOffset                    :  5;  // Bits 31:27
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA5CH1_CR_DDRCRDATAOFFSETCOMP_STRUCT;
+
+typedef union {
+  struct {
+    U32 RefPi                                   :  4;  // Bits 3:0
+    U32 DllMask                                 :  2;  // Bits 5:4
+    U32 DllWeakLock                             :  1;  // Bits 6:6
+    U32 SdllSegmentDisable                      :  3;  // Bits 9:7
+    U32 RxBiasCtl                               :  3;  // Bits 12:10
+    U32 OdtDelay                                :  4;  // Bits 16:13
+    U32 OdtDuration                             :  3;  // Bits 19:17
+    U32 SenseAmpDelay                           :  4;  // Bits 23:20
+    U32 SenseAmpDuration                        :  3;  // Bits 26:24
+    U32 BurstEndODTDelay                        :  3;  // Bits 29:27
+    U32 LpDdrLongOdtEn                          :  1;  // Bits 30:30
+    U32 Rsvd1                                   :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA5CH1_CR_DDRCRDATACONTROL1_STRUCT;
+
+typedef union {
+  struct {
+    U32 RxStaggerCtl                            :  5;  // Bits 4:0
+    U32 ForceBiasOn                             :  1;  // Bits 5:5
+    U32 ForceRxOn                               :  1;  // Bits 6:6
+    U32 LeakerComp                              :  2;  // Bits 8:7
+    U32 RxDqsAmpOffset                          :  4;  // Bits 12:9
+    U32 RxClkStgNum                             :  5;  // Bits 17:13
+    U32 WlLongDelEn                             :  1;  // Bits 18:18
+    U32 Spare                                   :  13;  // Bits 31:19
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA5CH1_CR_DDRCRDATACONTROL2_STRUCT;
+
+typedef union {
+  struct {
+    U32 VssHiOrVrefCtl                          :  24;  // Bits 23:0
+    U32 OutputCode                              :  8;  // Bits 31:24
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA5CH1_CR_DDRCRVSSHIORVREFCONTROL_STRUCT;
+
+typedef union {
+  struct {
+    U32 RcvEnOffset                             :  6;  // Bits 5:0
+    U32 RxDqsOffset                             :  6;  // Bits 11:6
+    U32 TxDqOffset                              :  6;  // Bits 17:12
+    U32 TxDqsOffset                             :  6;  // Bits 23:18
+    U32 VrefOffset                              :  7;  // Bits 30:24
+    U32 Spare                                   :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA5CH1_CR_DDRCRDATAOFFSETTRAIN_STRUCT;
+
+typedef union {
+  struct {
+    U32 RxTrainingMode                          :  1;  // Bits 0:0
+    U32 WLTrainingMode                          :  1;  // Bits 1:1
+    U32 RLTrainingMode                          :  1;  // Bits 2:2
+    U32 SenseampTrainingMode                    :  1;  // Bits 3:3
+    U32 TxOn                                    :  1;  // Bits 4:4
+    U32 RfOn                                    :  1;  // Bits 5:5
+    U32 RxPiOn                                  :  1;  // Bits 6:6
+    U32 TxPiOn                                  :  1;  // Bits 7:7
+    U32 InternalClocksOn                        :  1;  // Bits 8:8
+    U32 RepeaterClocksOn                        :  1;  // Bits 9:9
+    U32 TxDisable                               :  1;  // Bits 10:10
+    U32 RxDisable                               :  1;  // Bits 11:11
+    U32 TxLong                                  :  1;  // Bits 12:12
+    U32 RxDqsCtle                               :  2;  // Bits 14:13
+    U32 RxReadPointer                           :  3;  // Bits 17:15
+    U32 DriverSegmentEnable                     :  1;  // Bits 18:18
+    U32 DataVccddqHi                            :  1;  // Bits 19:19
+    U32 ReadRFRd                                :  1;  // Bits 20:20
+    U32 ReadRFWr                                :  1;  // Bits 21:21
+    U32 ReadRFRank                              :  2;  // Bits 23:22
+    U32 ForceOdtOn                              :  1;  // Bits 24:24
+    U32 OdtSampOff                              :  1;  // Bits 25:25
+    U32 DisableOdtStatic                        :  1;  // Bits 26:26
+    U32 DdrCRForceODTOn                         :  1;  // Bits 27:27
+    U32 LPDDR_Mode                              :  1;  // Bits 28:28
+    U32 EnReadPreamble                          :  1;  // Bits 29:29
+    U32 OdtSampExtendEn                         :  1;  // Bits 30:30
+    U32 EarlyRleakEn                            :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA5CH1_CR_DDRCRDATACONTROL0_STRUCT;
+
+typedef union {
+  struct {
+    U32 CAVrefCtl                               :  7;  // Bits 6:0
+    U32 Ch1VrefCtl                              :  7;  // Bits 13:7
+    U32 Ch0VrefCtl                              :  7;  // Bits 20:14
+    U32 EnDimmVrefCA                            :  1;  // Bits 21:21
+    U32 EnDimmVrefCh1                           :  1;  // Bits 22:22
+    U32 EnDimmVrefCh0                           :  1;  // Bits 23:23
+    U32 HiZTimerCtrl                            :  2;  // Bits 25:24
+    U32 VccddqHiQnnnH                           :  1;  // Bits 26:26
+    U32 Rsvd                                    :  2;  // Bits 28:27
+    U32 caSlowBW                                :  1;  // Bits 29:29
+    U32 ch0SlowBW                               :  1;  // Bits 30:30
+    U32 ch1SlowBW                               :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA5CH1_CR_DDRCRVREFADJUST1_STRUCT;
+
+typedef union {
+  struct {
+    U32 RxRcvEnPi                               :  9;  // Bits 8:0
+    U32 RxDqsPPi                                :  6;  // Bits 14:9
+    U32 RxEq                                    :  5;  // Bits 19:15
+    U32 RxDqsNPi                                :  6;  // Bits 25:20
+    U32 RxVref                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA6CH0_CR_RXTRAINRANK0_STRUCT;
+
+typedef union {
+  struct {
+    U32 RxRcvEnPi                               :  9;  // Bits 8:0
+    U32 RxDqsPPi                                :  6;  // Bits 14:9
+    U32 RxEq                                    :  5;  // Bits 19:15
+    U32 RxDqsNPi                                :  6;  // Bits 25:20
+    U32 RxVref                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA6CH0_CR_RXTRAINRANK1_STRUCT;
+
+typedef union {
+  struct {
+    U32 RxRcvEnPi                               :  9;  // Bits 8:0
+    U32 RxDqsPPi                                :  6;  // Bits 14:9
+    U32 RxEq                                    :  5;  // Bits 19:15
+    U32 RxDqsNPi                                :  6;  // Bits 25:20
+    U32 RxVref                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA6CH0_CR_RXTRAINRANK2_STRUCT;
+
+typedef union {
+  struct {
+    U32 RxRcvEnPi                               :  9;  // Bits 8:0
+    U32 RxDqsPPi                                :  6;  // Bits 14:9
+    U32 RxEq                                    :  5;  // Bits 19:15
+    U32 RxDqsNPi                                :  6;  // Bits 25:20
+    U32 RxVref                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA6CH0_CR_RXTRAINRANK3_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA6CH0_CR_RXPERBITRANK0_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA6CH0_CR_RXPERBITRANK1_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA6CH0_CR_RXPERBITRANK2_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA6CH0_CR_RXPERBITRANK3_STRUCT;
+
+typedef union {
+  struct {
+    U32 TxDqDelay                               :  9;  // Bits 8:0
+    U32 TxDqsDelay                              :  9;  // Bits 17:9
+    U32 Spare0                                  :  2;  // Bits 19:18
+    U32 TxEqualization                          :  6;  // Bits 25:20
+    U32 Spare1                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA6CH0_CR_TXTRAINRANK0_STRUCT;
+
+typedef union {
+  struct {
+    U32 TxDqDelay                               :  9;  // Bits 8:0
+    U32 TxDqsDelay                              :  9;  // Bits 17:9
+    U32 Spare0                                  :  2;  // Bits 19:18
+    U32 TxEqualization                          :  6;  // Bits 25:20
+    U32 Spare1                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA6CH0_CR_TXTRAINRANK1_STRUCT;
+
+typedef union {
+  struct {
+    U32 TxDqDelay                               :  9;  // Bits 8:0
+    U32 TxDqsDelay                              :  9;  // Bits 17:9
+    U32 Spare0                                  :  2;  // Bits 19:18
+    U32 TxEqualization                          :  6;  // Bits 25:20
+    U32 Spare1                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA6CH0_CR_TXTRAINRANK2_STRUCT;
+
+typedef union {
+  struct {
+    U32 TxDqDelay                               :  9;  // Bits 8:0
+    U32 TxDqsDelay                              :  9;  // Bits 17:9
+    U32 Spare0                                  :  2;  // Bits 19:18
+    U32 TxEqualization                          :  6;  // Bits 25:20
+    U32 Spare1                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA6CH0_CR_TXTRAINRANK3_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA6CH0_CR_TXPERBITRANK0_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA6CH0_CR_TXPERBITRANK1_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA6CH0_CR_TXPERBITRANK2_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA6CH0_CR_TXPERBITRANK3_STRUCT;
+
+typedef union {
+  struct {
+    U32 RcompDrvUp                              :  6;  // Bits 5:0
+    U32 Spare0                                  :  3;  // Bits 8:6
+    U32 RcompDrvDown                            :  6;  // Bits 14:9
+    U32 VTComp                                  :  5;  // Bits 19:15
+    U32 TcoComp                                 :  6;  // Bits 25:20
+    U32 SlewRateComp                            :  5;  // Bits 30:26
+    U32 Spare2                                  :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA6CH0_CR_RCOMPDATA0_STRUCT;
+
+typedef union {
+  struct {
+    U32 RcompOdtUp                              :  6;  // Bits 5:0
+    U32 Spare0                                  :  3;  // Bits 8:6
+    U32 RcompOdtDown                            :  6;  // Bits 14:9
+    U32 Spare1                                  :  1;  // Bits 15:15
+    U32 PanicDrvDn                              :  6;  // Bits 21:16
+    U32 PanicDrvUp                              :  6;  // Bits 27:22
+    U32 LevelShifterComp                        :  3;  // Bits 30:28
+    U32 Spare2                                  :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA6CH0_CR_RCOMPDATA1_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA6CH0_CR_TXXTALK_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA6CH0_CR_RXOFFSETVDQ_STRUCT;
+
+typedef union {
+  struct {
+    U32 Spare                                   :  32;  // Bits 31:0
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA6CH0_CR_DDRDATARESERVED_STRUCT;
+
+typedef union {
+  struct {
+    U32 DataTrainFeedback                       :  9;  // Bits 8:0
+    U32 Spare                                   :  23;  // Bits 31:9
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA6CH0_CR_DATATRAINFEEDBACK_STRUCT;
+
+typedef union {
+  struct {
+    U32 RunTest                                 :  1;  // Bits 0:0
+    U32 Load                                    :  1;  // Bits 1:1
+    U32 ModeHVM                                 :  1;  // Bits 2:2
+    U32 ModeDV                                  :  1;  // Bits 3:3
+    U32 ModeADC                                 :  1;  // Bits 4:4
+    U32 LoadCount                               :  10;  // Bits 14:5
+    U32 CountStatus                             :  10;  // Bits 24:15
+    U32 Spare                                   :  7;  // Bits 31:25
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA6CH0_CR_DLLPITESTANDADC_STRUCT;
+
+typedef union {
+  struct {
+    U32 DqDrvUpCompOffset                       :  6;  // Bits 5:0
+    U32 DqDrvDownCompOffset                     :  6;  // Bits 11:6
+    U32 DqOdtUpCompOffset                       :  5;  // Bits 16:12
+    U32 DqOdtDownCompOffset                     :  5;  // Bits 21:17
+    U32 DqTcoCompOffset                         :  5;  // Bits 26:22
+    U32 DqSlewRateCompOffset                    :  5;  // Bits 31:27
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA6CH0_CR_DDRCRDATAOFFSETCOMP_STRUCT;
+
+typedef union {
+  struct {
+    U32 RefPi                                   :  4;  // Bits 3:0
+    U32 DllMask                                 :  2;  // Bits 5:4
+    U32 DllWeakLock                             :  1;  // Bits 6:6
+    U32 SdllSegmentDisable                      :  3;  // Bits 9:7
+    U32 RxBiasCtl                               :  3;  // Bits 12:10
+    U32 OdtDelay                                :  4;  // Bits 16:13
+    U32 OdtDuration                             :  3;  // Bits 19:17
+    U32 SenseAmpDelay                           :  4;  // Bits 23:20
+    U32 SenseAmpDuration                        :  3;  // Bits 26:24
+    U32 BurstEndODTDelay                        :  3;  // Bits 29:27
+    U32 LpDdrLongOdtEn                          :  1;  // Bits 30:30
+    U32 Rsvd1                                   :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA6CH0_CR_DDRCRDATACONTROL1_STRUCT;
+
+typedef union {
+  struct {
+    U32 RxStaggerCtl                            :  5;  // Bits 4:0
+    U32 ForceBiasOn                             :  1;  // Bits 5:5
+    U32 ForceRxOn                               :  1;  // Bits 6:6
+    U32 LeakerComp                              :  2;  // Bits 8:7
+    U32 RxDqsAmpOffset                          :  4;  // Bits 12:9
+    U32 RxClkStgNum                             :  5;  // Bits 17:13
+    U32 WlLongDelEn                             :  1;  // Bits 18:18
+    U32 Spare                                   :  13;  // Bits 31:19
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA6CH0_CR_DDRCRDATACONTROL2_STRUCT;
+
+typedef union {
+  struct {
+    U32 VssHiOrVrefCtl                          :  24;  // Bits 23:0
+    U32 OutputCode                              :  8;  // Bits 31:24
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA6CH0_CR_DDRCRVSSHIORVREFCONTROL_STRUCT;
+
+typedef union {
+  struct {
+    U32 RcvEnOffset                             :  6;  // Bits 5:0
+    U32 RxDqsOffset                             :  6;  // Bits 11:6
+    U32 TxDqOffset                              :  6;  // Bits 17:12
+    U32 TxDqsOffset                             :  6;  // Bits 23:18
+    U32 VrefOffset                              :  7;  // Bits 30:24
+    U32 Spare                                   :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA6CH0_CR_DDRCRDATAOFFSETTRAIN_STRUCT;
+
+typedef union {
+  struct {
+    U32 RxTrainingMode                          :  1;  // Bits 0:0
+    U32 WLTrainingMode                          :  1;  // Bits 1:1
+    U32 RLTrainingMode                          :  1;  // Bits 2:2
+    U32 SenseampTrainingMode                    :  1;  // Bits 3:3
+    U32 TxOn                                    :  1;  // Bits 4:4
+    U32 RfOn                                    :  1;  // Bits 5:5
+    U32 RxPiOn                                  :  1;  // Bits 6:6
+    U32 TxPiOn                                  :  1;  // Bits 7:7
+    U32 InternalClocksOn                        :  1;  // Bits 8:8
+    U32 RepeaterClocksOn                        :  1;  // Bits 9:9
+    U32 TxDisable                               :  1;  // Bits 10:10
+    U32 RxDisable                               :  1;  // Bits 11:11
+    U32 TxLong                                  :  1;  // Bits 12:12
+    U32 RxDqsCtle                               :  2;  // Bits 14:13
+    U32 RxReadPointer                           :  3;  // Bits 17:15
+    U32 DriverSegmentEnable                     :  1;  // Bits 18:18
+    U32 DataVccddqHi                            :  1;  // Bits 19:19
+    U32 ReadRFRd                                :  1;  // Bits 20:20
+    U32 ReadRFWr                                :  1;  // Bits 21:21
+    U32 ReadRFRank                              :  2;  // Bits 23:22
+    U32 ForceOdtOn                              :  1;  // Bits 24:24
+    U32 OdtSampOff                              :  1;  // Bits 25:25
+    U32 DisableOdtStatic                        :  1;  // Bits 26:26
+    U32 DdrCRForceODTOn                         :  1;  // Bits 27:27
+    U32 LPDDR_Mode                              :  1;  // Bits 28:28
+    U32 EnReadPreamble                          :  1;  // Bits 29:29
+    U32 OdtSampExtendEn                         :  1;  // Bits 30:30
+    U32 EarlyRleakEn                            :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA6CH0_CR_DDRCRDATACONTROL0_STRUCT;
+
+typedef union {
+  struct {
+    U32 CAVrefCtl                               :  7;  // Bits 6:0
+    U32 Ch1VrefCtl                              :  7;  // Bits 13:7
+    U32 Ch0VrefCtl                              :  7;  // Bits 20:14
+    U32 EnDimmVrefCA                            :  1;  // Bits 21:21
+    U32 EnDimmVrefCh1                           :  1;  // Bits 22:22
+    U32 EnDimmVrefCh0                           :  1;  // Bits 23:23
+    U32 HiZTimerCtrl                            :  2;  // Bits 25:24
+    U32 VccddqHiQnnnH                           :  1;  // Bits 26:26
+    U32 Rsvd                                    :  2;  // Bits 28:27
+    U32 caSlowBW                                :  1;  // Bits 29:29
+    U32 ch0SlowBW                               :  1;  // Bits 30:30
+    U32 ch1SlowBW                               :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA6CH0_CR_DDRCRVREFADJUST1_STRUCT;
+
+typedef union {
+  struct {
+    U32 RxRcvEnPi                               :  9;  // Bits 8:0
+    U32 RxDqsPPi                                :  6;  // Bits 14:9
+    U32 RxEq                                    :  5;  // Bits 19:15
+    U32 RxDqsNPi                                :  6;  // Bits 25:20
+    U32 RxVref                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA6CH1_CR_RXTRAINRANK0_STRUCT;
+
+typedef union {
+  struct {
+    U32 RxRcvEnPi                               :  9;  // Bits 8:0
+    U32 RxDqsPPi                                :  6;  // Bits 14:9
+    U32 RxEq                                    :  5;  // Bits 19:15
+    U32 RxDqsNPi                                :  6;  // Bits 25:20
+    U32 RxVref                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA6CH1_CR_RXTRAINRANK1_STRUCT;
+
+typedef union {
+  struct {
+    U32 RxRcvEnPi                               :  9;  // Bits 8:0
+    U32 RxDqsPPi                                :  6;  // Bits 14:9
+    U32 RxEq                                    :  5;  // Bits 19:15
+    U32 RxDqsNPi                                :  6;  // Bits 25:20
+    U32 RxVref                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA6CH1_CR_RXTRAINRANK2_STRUCT;
+
+typedef union {
+  struct {
+    U32 RxRcvEnPi                               :  9;  // Bits 8:0
+    U32 RxDqsPPi                                :  6;  // Bits 14:9
+    U32 RxEq                                    :  5;  // Bits 19:15
+    U32 RxDqsNPi                                :  6;  // Bits 25:20
+    U32 RxVref                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA6CH1_CR_RXTRAINRANK3_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA6CH1_CR_RXPERBITRANK0_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA6CH1_CR_RXPERBITRANK1_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA6CH1_CR_RXPERBITRANK2_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA6CH1_CR_RXPERBITRANK3_STRUCT;
+
+typedef union {
+  struct {
+    U32 TxDqDelay                               :  9;  // Bits 8:0
+    U32 TxDqsDelay                              :  9;  // Bits 17:9
+    U32 Spare0                                  :  2;  // Bits 19:18
+    U32 TxEqualization                          :  6;  // Bits 25:20
+    U32 Spare1                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA6CH1_CR_TXTRAINRANK0_STRUCT;
+
+typedef union {
+  struct {
+    U32 TxDqDelay                               :  9;  // Bits 8:0
+    U32 TxDqsDelay                              :  9;  // Bits 17:9
+    U32 Spare0                                  :  2;  // Bits 19:18
+    U32 TxEqualization                          :  6;  // Bits 25:20
+    U32 Spare1                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA6CH1_CR_TXTRAINRANK1_STRUCT;
+
+typedef union {
+  struct {
+    U32 TxDqDelay                               :  9;  // Bits 8:0
+    U32 TxDqsDelay                              :  9;  // Bits 17:9
+    U32 Spare0                                  :  2;  // Bits 19:18
+    U32 TxEqualization                          :  6;  // Bits 25:20
+    U32 Spare1                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA6CH1_CR_TXTRAINRANK2_STRUCT;
+
+typedef union {
+  struct {
+    U32 TxDqDelay                               :  9;  // Bits 8:0
+    U32 TxDqsDelay                              :  9;  // Bits 17:9
+    U32 Spare0                                  :  2;  // Bits 19:18
+    U32 TxEqualization                          :  6;  // Bits 25:20
+    U32 Spare1                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA6CH1_CR_TXTRAINRANK3_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA6CH1_CR_TXPERBITRANK0_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA6CH1_CR_TXPERBITRANK1_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA6CH1_CR_TXPERBITRANK2_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA6CH1_CR_TXPERBITRANK3_STRUCT;
+
+typedef union {
+  struct {
+    U32 RcompDrvUp                              :  6;  // Bits 5:0
+    U32 Spare0                                  :  3;  // Bits 8:6
+    U32 RcompDrvDown                            :  6;  // Bits 14:9
+    U32 VTComp                                  :  5;  // Bits 19:15
+    U32 TcoComp                                 :  6;  // Bits 25:20
+    U32 SlewRateComp                            :  5;  // Bits 30:26
+    U32 Spare2                                  :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA6CH1_CR_RCOMPDATA0_STRUCT;
+
+typedef union {
+  struct {
+    U32 RcompOdtUp                              :  6;  // Bits 5:0
+    U32 Spare0                                  :  3;  // Bits 8:6
+    U32 RcompOdtDown                            :  6;  // Bits 14:9
+    U32 Spare1                                  :  1;  // Bits 15:15
+    U32 PanicDrvDn                              :  6;  // Bits 21:16
+    U32 PanicDrvUp                              :  6;  // Bits 27:22
+    U32 LevelShifterComp                        :  3;  // Bits 30:28
+    U32 Spare2                                  :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA6CH1_CR_RCOMPDATA1_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA6CH1_CR_TXXTALK_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA6CH1_CR_RXOFFSETVDQ_STRUCT;
+
+typedef union {
+  struct {
+    U32 Spare                                   :  32;  // Bits 31:0
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA6CH1_CR_DDRDATARESERVED_STRUCT;
+
+typedef union {
+  struct {
+    U32 DataTrainFeedback                       :  9;  // Bits 8:0
+    U32 Spare                                   :  23;  // Bits 31:9
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA6CH1_CR_DATATRAINFEEDBACK_STRUCT;
+
+typedef union {
+  struct {
+    U32 RunTest                                 :  1;  // Bits 0:0
+    U32 Load                                    :  1;  // Bits 1:1
+    U32 ModeHVM                                 :  1;  // Bits 2:2
+    U32 ModeDV                                  :  1;  // Bits 3:3
+    U32 ModeADC                                 :  1;  // Bits 4:4
+    U32 LoadCount                               :  10;  // Bits 14:5
+    U32 CountStatus                             :  10;  // Bits 24:15
+    U32 Spare                                   :  7;  // Bits 31:25
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA6CH1_CR_DLLPITESTANDADC_STRUCT;
+
+typedef union {
+  struct {
+    U32 DqDrvUpCompOffset                       :  6;  // Bits 5:0
+    U32 DqDrvDownCompOffset                     :  6;  // Bits 11:6
+    U32 DqOdtUpCompOffset                       :  5;  // Bits 16:12
+    U32 DqOdtDownCompOffset                     :  5;  // Bits 21:17
+    U32 DqTcoCompOffset                         :  5;  // Bits 26:22
+    U32 DqSlewRateCompOffset                    :  5;  // Bits 31:27
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA6CH1_CR_DDRCRDATAOFFSETCOMP_STRUCT;
+
+typedef union {
+  struct {
+    U32 RefPi                                   :  4;  // Bits 3:0
+    U32 DllMask                                 :  2;  // Bits 5:4
+    U32 DllWeakLock                             :  1;  // Bits 6:6
+    U32 SdllSegmentDisable                      :  3;  // Bits 9:7
+    U32 RxBiasCtl                               :  3;  // Bits 12:10
+    U32 OdtDelay                                :  4;  // Bits 16:13
+    U32 OdtDuration                             :  3;  // Bits 19:17
+    U32 SenseAmpDelay                           :  4;  // Bits 23:20
+    U32 SenseAmpDuration                        :  3;  // Bits 26:24
+    U32 BurstEndODTDelay                        :  3;  // Bits 29:27
+    U32 LpDdrLongOdtEn                          :  1;  // Bits 30:30
+    U32 Rsvd1                                   :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA6CH1_CR_DDRCRDATACONTROL1_STRUCT;
+
+typedef union {
+  struct {
+    U32 RxStaggerCtl                            :  5;  // Bits 4:0
+    U32 ForceBiasOn                             :  1;  // Bits 5:5
+    U32 ForceRxOn                               :  1;  // Bits 6:6
+    U32 LeakerComp                              :  2;  // Bits 8:7
+    U32 RxDqsAmpOffset                          :  4;  // Bits 12:9
+    U32 RxClkStgNum                             :  5;  // Bits 17:13
+    U32 WlLongDelEn                             :  1;  // Bits 18:18
+    U32 Spare                                   :  13;  // Bits 31:19
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA6CH1_CR_DDRCRDATACONTROL2_STRUCT;
+
+typedef union {
+  struct {
+    U32 VssHiOrVrefCtl                          :  24;  // Bits 23:0
+    U32 OutputCode                              :  8;  // Bits 31:24
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA6CH1_CR_DDRCRVSSHIORVREFCONTROL_STRUCT;
+
+typedef union {
+  struct {
+    U32 RcvEnOffset                             :  6;  // Bits 5:0
+    U32 RxDqsOffset                             :  6;  // Bits 11:6
+    U32 TxDqOffset                              :  6;  // Bits 17:12
+    U32 TxDqsOffset                             :  6;  // Bits 23:18
+    U32 VrefOffset                              :  7;  // Bits 30:24
+    U32 Spare                                   :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA6CH1_CR_DDRCRDATAOFFSETTRAIN_STRUCT;
+
+typedef union {
+  struct {
+    U32 RxTrainingMode                          :  1;  // Bits 0:0
+    U32 WLTrainingMode                          :  1;  // Bits 1:1
+    U32 RLTrainingMode                          :  1;  // Bits 2:2
+    U32 SenseampTrainingMode                    :  1;  // Bits 3:3
+    U32 TxOn                                    :  1;  // Bits 4:4
+    U32 RfOn                                    :  1;  // Bits 5:5
+    U32 RxPiOn                                  :  1;  // Bits 6:6
+    U32 TxPiOn                                  :  1;  // Bits 7:7
+    U32 InternalClocksOn                        :  1;  // Bits 8:8
+    U32 RepeaterClocksOn                        :  1;  // Bits 9:9
+    U32 TxDisable                               :  1;  // Bits 10:10
+    U32 RxDisable                               :  1;  // Bits 11:11
+    U32 TxLong                                  :  1;  // Bits 12:12
+    U32 RxDqsCtle                               :  2;  // Bits 14:13
+    U32 RxReadPointer                           :  3;  // Bits 17:15
+    U32 DriverSegmentEnable                     :  1;  // Bits 18:18
+    U32 DataVccddqHi                            :  1;  // Bits 19:19
+    U32 ReadRFRd                                :  1;  // Bits 20:20
+    U32 ReadRFWr                                :  1;  // Bits 21:21
+    U32 ReadRFRank                              :  2;  // Bits 23:22
+    U32 ForceOdtOn                              :  1;  // Bits 24:24
+    U32 OdtSampOff                              :  1;  // Bits 25:25
+    U32 DisableOdtStatic                        :  1;  // Bits 26:26
+    U32 DdrCRForceODTOn                         :  1;  // Bits 27:27
+    U32 LPDDR_Mode                              :  1;  // Bits 28:28
+    U32 EnReadPreamble                          :  1;  // Bits 29:29
+    U32 OdtSampExtendEn                         :  1;  // Bits 30:30
+    U32 EarlyRleakEn                            :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA6CH1_CR_DDRCRDATACONTROL0_STRUCT;
+
+typedef union {
+  struct {
+    U32 CAVrefCtl                               :  7;  // Bits 6:0
+    U32 Ch1VrefCtl                              :  7;  // Bits 13:7
+    U32 Ch0VrefCtl                              :  7;  // Bits 20:14
+    U32 EnDimmVrefCA                            :  1;  // Bits 21:21
+    U32 EnDimmVrefCh1                           :  1;  // Bits 22:22
+    U32 EnDimmVrefCh0                           :  1;  // Bits 23:23
+    U32 HiZTimerCtrl                            :  2;  // Bits 25:24
+    U32 VccddqHiQnnnH                           :  1;  // Bits 26:26
+    U32 Rsvd                                    :  2;  // Bits 28:27
+    U32 caSlowBW                                :  1;  // Bits 29:29
+    U32 ch0SlowBW                               :  1;  // Bits 30:30
+    U32 ch1SlowBW                               :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA6CH1_CR_DDRCRVREFADJUST1_STRUCT;
+
+typedef union {
+  struct {
+    U32 RxRcvEnPi                               :  9;  // Bits 8:0
+    U32 RxDqsPPi                                :  6;  // Bits 14:9
+    U32 RxEq                                    :  5;  // Bits 19:15
+    U32 RxDqsNPi                                :  6;  // Bits 25:20
+    U32 RxVref                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA7CH0_CR_RXTRAINRANK0_STRUCT;
+
+typedef union {
+  struct {
+    U32 RxRcvEnPi                               :  9;  // Bits 8:0
+    U32 RxDqsPPi                                :  6;  // Bits 14:9
+    U32 RxEq                                    :  5;  // Bits 19:15
+    U32 RxDqsNPi                                :  6;  // Bits 25:20
+    U32 RxVref                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA7CH0_CR_RXTRAINRANK1_STRUCT;
+
+typedef union {
+  struct {
+    U32 RxRcvEnPi                               :  9;  // Bits 8:0
+    U32 RxDqsPPi                                :  6;  // Bits 14:9
+    U32 RxEq                                    :  5;  // Bits 19:15
+    U32 RxDqsNPi                                :  6;  // Bits 25:20
+    U32 RxVref                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA7CH0_CR_RXTRAINRANK2_STRUCT;
+
+typedef union {
+  struct {
+    U32 RxRcvEnPi                               :  9;  // Bits 8:0
+    U32 RxDqsPPi                                :  6;  // Bits 14:9
+    U32 RxEq                                    :  5;  // Bits 19:15
+    U32 RxDqsNPi                                :  6;  // Bits 25:20
+    U32 RxVref                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA7CH0_CR_RXTRAINRANK3_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA7CH0_CR_RXPERBITRANK0_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA7CH0_CR_RXPERBITRANK1_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA7CH0_CR_RXPERBITRANK2_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA7CH0_CR_RXPERBITRANK3_STRUCT;
+
+typedef union {
+  struct {
+    U32 TxDqDelay                               :  9;  // Bits 8:0
+    U32 TxDqsDelay                              :  9;  // Bits 17:9
+    U32 Spare0                                  :  2;  // Bits 19:18
+    U32 TxEqualization                          :  6;  // Bits 25:20
+    U32 Spare1                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA7CH0_CR_TXTRAINRANK0_STRUCT;
+
+typedef union {
+  struct {
+    U32 TxDqDelay                               :  9;  // Bits 8:0
+    U32 TxDqsDelay                              :  9;  // Bits 17:9
+    U32 Spare0                                  :  2;  // Bits 19:18
+    U32 TxEqualization                          :  6;  // Bits 25:20
+    U32 Spare1                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA7CH0_CR_TXTRAINRANK1_STRUCT;
+
+typedef union {
+  struct {
+    U32 TxDqDelay                               :  9;  // Bits 8:0
+    U32 TxDqsDelay                              :  9;  // Bits 17:9
+    U32 Spare0                                  :  2;  // Bits 19:18
+    U32 TxEqualization                          :  6;  // Bits 25:20
+    U32 Spare1                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA7CH0_CR_TXTRAINRANK2_STRUCT;
+
+typedef union {
+  struct {
+    U32 TxDqDelay                               :  9;  // Bits 8:0
+    U32 TxDqsDelay                              :  9;  // Bits 17:9
+    U32 Spare0                                  :  2;  // Bits 19:18
+    U32 TxEqualization                          :  6;  // Bits 25:20
+    U32 Spare1                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA7CH0_CR_TXTRAINRANK3_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA7CH0_CR_TXPERBITRANK0_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA7CH0_CR_TXPERBITRANK1_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA7CH0_CR_TXPERBITRANK2_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA7CH0_CR_TXPERBITRANK3_STRUCT;
+
+typedef union {
+  struct {
+    U32 RcompDrvUp                              :  6;  // Bits 5:0
+    U32 Spare0                                  :  3;  // Bits 8:6
+    U32 RcompDrvDown                            :  6;  // Bits 14:9
+    U32 VTComp                                  :  5;  // Bits 19:15
+    U32 TcoComp                                 :  6;  // Bits 25:20
+    U32 SlewRateComp                            :  5;  // Bits 30:26
+    U32 Spare2                                  :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA7CH0_CR_RCOMPDATA0_STRUCT;
+
+typedef union {
+  struct {
+    U32 RcompOdtUp                              :  6;  // Bits 5:0
+    U32 Spare0                                  :  3;  // Bits 8:6
+    U32 RcompOdtDown                            :  6;  // Bits 14:9
+    U32 Spare1                                  :  1;  // Bits 15:15
+    U32 PanicDrvDn                              :  6;  // Bits 21:16
+    U32 PanicDrvUp                              :  6;  // Bits 27:22
+    U32 LevelShifterComp                        :  3;  // Bits 30:28
+    U32 Spare2                                  :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA7CH0_CR_RCOMPDATA1_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA7CH0_CR_TXXTALK_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA7CH0_CR_RXOFFSETVDQ_STRUCT;
+
+typedef union {
+  struct {
+    U32 Spare                                   :  32;  // Bits 31:0
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA7CH0_CR_DDRDATARESERVED_STRUCT;
+
+typedef union {
+  struct {
+    U32 DataTrainFeedback                       :  9;  // Bits 8:0
+    U32 Spare                                   :  23;  // Bits 31:9
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA7CH0_CR_DATATRAINFEEDBACK_STRUCT;
+
+typedef union {
+  struct {
+    U32 RunTest                                 :  1;  // Bits 0:0
+    U32 Load                                    :  1;  // Bits 1:1
+    U32 ModeHVM                                 :  1;  // Bits 2:2
+    U32 ModeDV                                  :  1;  // Bits 3:3
+    U32 ModeADC                                 :  1;  // Bits 4:4
+    U32 LoadCount                               :  10;  // Bits 14:5
+    U32 CountStatus                             :  10;  // Bits 24:15
+    U32 Spare                                   :  7;  // Bits 31:25
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA7CH0_CR_DLLPITESTANDADC_STRUCT;
+
+typedef union {
+  struct {
+    U32 DqDrvUpCompOffset                       :  6;  // Bits 5:0
+    U32 DqDrvDownCompOffset                     :  6;  // Bits 11:6
+    U32 DqOdtUpCompOffset                       :  5;  // Bits 16:12
+    U32 DqOdtDownCompOffset                     :  5;  // Bits 21:17
+    U32 DqTcoCompOffset                         :  5;  // Bits 26:22
+    U32 DqSlewRateCompOffset                    :  5;  // Bits 31:27
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA7CH0_CR_DDRCRDATAOFFSETCOMP_STRUCT;
+
+typedef union {
+  struct {
+    U32 RefPi                                   :  4;  // Bits 3:0
+    U32 DllMask                                 :  2;  // Bits 5:4
+    U32 DllWeakLock                             :  1;  // Bits 6:6
+    U32 SdllSegmentDisable                      :  3;  // Bits 9:7
+    U32 RxBiasCtl                               :  3;  // Bits 12:10
+    U32 OdtDelay                                :  4;  // Bits 16:13
+    U32 OdtDuration                             :  3;  // Bits 19:17
+    U32 SenseAmpDelay                           :  4;  // Bits 23:20
+    U32 SenseAmpDuration                        :  3;  // Bits 26:24
+    U32 BurstEndODTDelay                        :  3;  // Bits 29:27
+    U32 LpDdrLongOdtEn                          :  1;  // Bits 30:30
+    U32 Rsvd1                                   :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA7CH0_CR_DDRCRDATACONTROL1_STRUCT;
+
+typedef union {
+  struct {
+    U32 RxStaggerCtl                            :  5;  // Bits 4:0
+    U32 ForceBiasOn                             :  1;  // Bits 5:5
+    U32 ForceRxOn                               :  1;  // Bits 6:6
+    U32 LeakerComp                              :  2;  // Bits 8:7
+    U32 RxDqsAmpOffset                          :  4;  // Bits 12:9
+    U32 RxClkStgNum                             :  5;  // Bits 17:13
+    U32 WlLongDelEn                             :  1;  // Bits 18:18
+    U32 Spare                                   :  13;  // Bits 31:19
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA7CH0_CR_DDRCRDATACONTROL2_STRUCT;
+
+typedef union {
+  struct {
+    U32 VssHiOrVrefCtl                          :  24;  // Bits 23:0
+    U32 OutputCode                              :  8;  // Bits 31:24
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA7CH0_CR_DDRCRVSSHIORVREFCONTROL_STRUCT;
+
+typedef union {
+  struct {
+    U32 RcvEnOffset                             :  6;  // Bits 5:0
+    U32 RxDqsOffset                             :  6;  // Bits 11:6
+    U32 TxDqOffset                              :  6;  // Bits 17:12
+    U32 TxDqsOffset                             :  6;  // Bits 23:18
+    U32 VrefOffset                              :  7;  // Bits 30:24
+    U32 Spare                                   :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA7CH0_CR_DDRCRDATAOFFSETTRAIN_STRUCT;
+
+typedef union {
+  struct {
+    U32 RxTrainingMode                          :  1;  // Bits 0:0
+    U32 WLTrainingMode                          :  1;  // Bits 1:1
+    U32 RLTrainingMode                          :  1;  // Bits 2:2
+    U32 SenseampTrainingMode                    :  1;  // Bits 3:3
+    U32 TxOn                                    :  1;  // Bits 4:4
+    U32 RfOn                                    :  1;  // Bits 5:5
+    U32 RxPiOn                                  :  1;  // Bits 6:6
+    U32 TxPiOn                                  :  1;  // Bits 7:7
+    U32 InternalClocksOn                        :  1;  // Bits 8:8
+    U32 RepeaterClocksOn                        :  1;  // Bits 9:9
+    U32 TxDisable                               :  1;  // Bits 10:10
+    U32 RxDisable                               :  1;  // Bits 11:11
+    U32 TxLong                                  :  1;  // Bits 12:12
+    U32 RxDqsCtle                               :  2;  // Bits 14:13
+    U32 RxReadPointer                           :  3;  // Bits 17:15
+    U32 DriverSegmentEnable                     :  1;  // Bits 18:18
+    U32 DataVccddqHi                            :  1;  // Bits 19:19
+    U32 ReadRFRd                                :  1;  // Bits 20:20
+    U32 ReadRFWr                                :  1;  // Bits 21:21
+    U32 ReadRFRank                              :  2;  // Bits 23:22
+    U32 ForceOdtOn                              :  1;  // Bits 24:24
+    U32 OdtSampOff                              :  1;  // Bits 25:25
+    U32 DisableOdtStatic                        :  1;  // Bits 26:26
+    U32 DdrCRForceODTOn                         :  1;  // Bits 27:27
+    U32 LPDDR_Mode                              :  1;  // Bits 28:28
+    U32 EnReadPreamble                          :  1;  // Bits 29:29
+    U32 OdtSampExtendEn                         :  1;  // Bits 30:30
+    U32 EarlyRleakEn                            :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA7CH0_CR_DDRCRDATACONTROL0_STRUCT;
+
+typedef union {
+  struct {
+    U32 CAVrefCtl                               :  7;  // Bits 6:0
+    U32 Ch1VrefCtl                              :  7;  // Bits 13:7
+    U32 Ch0VrefCtl                              :  7;  // Bits 20:14
+    U32 EnDimmVrefCA                            :  1;  // Bits 21:21
+    U32 EnDimmVrefCh1                           :  1;  // Bits 22:22
+    U32 EnDimmVrefCh0                           :  1;  // Bits 23:23
+    U32 HiZTimerCtrl                            :  2;  // Bits 25:24
+    U32 VccddqHiQnnnH                           :  1;  // Bits 26:26
+    U32 Rsvd                                    :  2;  // Bits 28:27
+    U32 caSlowBW                                :  1;  // Bits 29:29
+    U32 ch0SlowBW                               :  1;  // Bits 30:30
+    U32 ch1SlowBW                               :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA7CH0_CR_DDRCRVREFADJUST1_STRUCT;
+
+typedef union {
+  struct {
+    U32 RxRcvEnPi                               :  9;  // Bits 8:0
+    U32 RxDqsPPi                                :  6;  // Bits 14:9
+    U32 RxEq                                    :  5;  // Bits 19:15
+    U32 RxDqsNPi                                :  6;  // Bits 25:20
+    U32 RxVref                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA7CH1_CR_RXTRAINRANK0_STRUCT;
+
+typedef union {
+  struct {
+    U32 RxRcvEnPi                               :  9;  // Bits 8:0
+    U32 RxDqsPPi                                :  6;  // Bits 14:9
+    U32 RxEq                                    :  5;  // Bits 19:15
+    U32 RxDqsNPi                                :  6;  // Bits 25:20
+    U32 RxVref                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA7CH1_CR_RXTRAINRANK1_STRUCT;
+
+typedef union {
+  struct {
+    U32 RxRcvEnPi                               :  9;  // Bits 8:0
+    U32 RxDqsPPi                                :  6;  // Bits 14:9
+    U32 RxEq                                    :  5;  // Bits 19:15
+    U32 RxDqsNPi                                :  6;  // Bits 25:20
+    U32 RxVref                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA7CH1_CR_RXTRAINRANK2_STRUCT;
+
+typedef union {
+  struct {
+    U32 RxRcvEnPi                               :  9;  // Bits 8:0
+    U32 RxDqsPPi                                :  6;  // Bits 14:9
+    U32 RxEq                                    :  5;  // Bits 19:15
+    U32 RxDqsNPi                                :  6;  // Bits 25:20
+    U32 RxVref                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA7CH1_CR_RXTRAINRANK3_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA7CH1_CR_RXPERBITRANK0_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA7CH1_CR_RXPERBITRANK1_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA7CH1_CR_RXPERBITRANK2_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA7CH1_CR_RXPERBITRANK3_STRUCT;
+
+typedef union {
+  struct {
+    U32 TxDqDelay                               :  9;  // Bits 8:0
+    U32 TxDqsDelay                              :  9;  // Bits 17:9
+    U32 Spare0                                  :  2;  // Bits 19:18
+    U32 TxEqualization                          :  6;  // Bits 25:20
+    U32 Spare1                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA7CH1_CR_TXTRAINRANK0_STRUCT;
+
+typedef union {
+  struct {
+    U32 TxDqDelay                               :  9;  // Bits 8:0
+    U32 TxDqsDelay                              :  9;  // Bits 17:9
+    U32 Spare0                                  :  2;  // Bits 19:18
+    U32 TxEqualization                          :  6;  // Bits 25:20
+    U32 Spare1                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA7CH1_CR_TXTRAINRANK1_STRUCT;
+
+typedef union {
+  struct {
+    U32 TxDqDelay                               :  9;  // Bits 8:0
+    U32 TxDqsDelay                              :  9;  // Bits 17:9
+    U32 Spare0                                  :  2;  // Bits 19:18
+    U32 TxEqualization                          :  6;  // Bits 25:20
+    U32 Spare1                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA7CH1_CR_TXTRAINRANK2_STRUCT;
+
+typedef union {
+  struct {
+    U32 TxDqDelay                               :  9;  // Bits 8:0
+    U32 TxDqsDelay                              :  9;  // Bits 17:9
+    U32 Spare0                                  :  2;  // Bits 19:18
+    U32 TxEqualization                          :  6;  // Bits 25:20
+    U32 Spare1                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA7CH1_CR_TXTRAINRANK3_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA7CH1_CR_TXPERBITRANK0_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA7CH1_CR_TXPERBITRANK1_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA7CH1_CR_TXPERBITRANK2_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA7CH1_CR_TXPERBITRANK3_STRUCT;
+
+typedef union {
+  struct {
+    U32 RcompDrvUp                              :  6;  // Bits 5:0
+    U32 Spare0                                  :  3;  // Bits 8:6
+    U32 RcompDrvDown                            :  6;  // Bits 14:9
+    U32 VTComp                                  :  5;  // Bits 19:15
+    U32 TcoComp                                 :  6;  // Bits 25:20
+    U32 SlewRateComp                            :  5;  // Bits 30:26
+    U32 Spare2                                  :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA7CH1_CR_RCOMPDATA0_STRUCT;
+
+typedef union {
+  struct {
+    U32 RcompOdtUp                              :  6;  // Bits 5:0
+    U32 Spare0                                  :  3;  // Bits 8:6
+    U32 RcompOdtDown                            :  6;  // Bits 14:9
+    U32 Spare1                                  :  1;  // Bits 15:15
+    U32 PanicDrvDn                              :  6;  // Bits 21:16
+    U32 PanicDrvUp                              :  6;  // Bits 27:22
+    U32 LevelShifterComp                        :  3;  // Bits 30:28
+    U32 Spare2                                  :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA7CH1_CR_RCOMPDATA1_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA7CH1_CR_TXXTALK_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA7CH1_CR_RXOFFSETVDQ_STRUCT;
+
+typedef union {
+  struct {
+    U32 Spare                                   :  32;  // Bits 31:0
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA7CH1_CR_DDRDATARESERVED_STRUCT;
+
+typedef union {
+  struct {
+    U32 DataTrainFeedback                       :  9;  // Bits 8:0
+    U32 Spare                                   :  23;  // Bits 31:9
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA7CH1_CR_DATATRAINFEEDBACK_STRUCT;
+
+typedef union {
+  struct {
+    U32 RunTest                                 :  1;  // Bits 0:0
+    U32 Load                                    :  1;  // Bits 1:1
+    U32 ModeHVM                                 :  1;  // Bits 2:2
+    U32 ModeDV                                  :  1;  // Bits 3:3
+    U32 ModeADC                                 :  1;  // Bits 4:4
+    U32 LoadCount                               :  10;  // Bits 14:5
+    U32 CountStatus                             :  10;  // Bits 24:15
+    U32 Spare                                   :  7;  // Bits 31:25
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA7CH1_CR_DLLPITESTANDADC_STRUCT;
+
+typedef union {
+  struct {
+    U32 DqDrvUpCompOffset                       :  6;  // Bits 5:0
+    U32 DqDrvDownCompOffset                     :  6;  // Bits 11:6
+    U32 DqOdtUpCompOffset                       :  5;  // Bits 16:12
+    U32 DqOdtDownCompOffset                     :  5;  // Bits 21:17
+    U32 DqTcoCompOffset                         :  5;  // Bits 26:22
+    U32 DqSlewRateCompOffset                    :  5;  // Bits 31:27
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA7CH1_CR_DDRCRDATAOFFSETCOMP_STRUCT;
+
+typedef union {
+  struct {
+    U32 RefPi                                   :  4;  // Bits 3:0
+    U32 DllMask                                 :  2;  // Bits 5:4
+    U32 DllWeakLock                             :  1;  // Bits 6:6
+    U32 SdllSegmentDisable                      :  3;  // Bits 9:7
+    U32 RxBiasCtl                               :  3;  // Bits 12:10
+    U32 OdtDelay                                :  4;  // Bits 16:13
+    U32 OdtDuration                             :  3;  // Bits 19:17
+    U32 SenseAmpDelay                           :  4;  // Bits 23:20
+    U32 SenseAmpDuration                        :  3;  // Bits 26:24
+    U32 BurstEndODTDelay                        :  3;  // Bits 29:27
+    U32 LpDdrLongOdtEn                          :  1;  // Bits 30:30
+    U32 Rsvd1                                   :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA7CH1_CR_DDRCRDATACONTROL1_STRUCT;
+
+typedef union {
+  struct {
+    U32 RxStaggerCtl                            :  5;  // Bits 4:0
+    U32 ForceBiasOn                             :  1;  // Bits 5:5
+    U32 ForceRxOn                               :  1;  // Bits 6:6
+    U32 LeakerComp                              :  2;  // Bits 8:7
+    U32 RxDqsAmpOffset                          :  4;  // Bits 12:9
+    U32 RxClkStgNum                             :  5;  // Bits 17:13
+    U32 WlLongDelEn                             :  1;  // Bits 18:18
+    U32 Spare                                   :  13;  // Bits 31:19
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA7CH1_CR_DDRCRDATACONTROL2_STRUCT;
+
+typedef union {
+  struct {
+    U32 VrefCtl                                 :  24;  // Bits 23:0
+    U32 OutputCode                              :  8;  // Bits 31:24
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA7CH1_CR_DDRCRVREFCONTROL_STRUCT;
+
+typedef union {
+  struct {
+    U32 VssHiCtl                                :  24;  // Bits 23:0
+    U32 OutputCode                              :  8;  // Bits 31:24
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA7CH1_CR_DDRCRVSSHICONTROL_STRUCT;
+
+typedef union {
+  struct {
+    U32 VssHiOrVrefCtl                          :  24;  // Bits 23:0
+    U32 OutputCode                              :  8;  // Bits 31:24
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA7CH1_CR_DDRCRVSSHIORVREFCONTROL_STRUCT;
+
+typedef union {
+  struct {
+    U32 RcvEnOffset                             :  6;  // Bits 5:0
+    U32 RxDqsOffset                             :  6;  // Bits 11:6
+    U32 TxDqOffset                              :  6;  // Bits 17:12
+    U32 TxDqsOffset                             :  6;  // Bits 23:18
+    U32 VrefOffset                              :  7;  // Bits 30:24
+    U32 Spare                                   :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA7CH1_CR_DDRCRDATAOFFSETTRAIN_STRUCT;
+
+typedef union {
+  struct {
+    U32 RxTrainingMode                          :  1;  // Bits 0:0
+    U32 WLTrainingMode                          :  1;  // Bits 1:1
+    U32 RLTrainingMode                          :  1;  // Bits 2:2
+    U32 SenseampTrainingMode                    :  1;  // Bits 3:3
+    U32 TxOn                                    :  1;  // Bits 4:4
+    U32 RfOn                                    :  1;  // Bits 5:5
+    U32 RxPiOn                                  :  1;  // Bits 6:6
+    U32 TxPiOn                                  :  1;  // Bits 7:7
+    U32 InternalClocksOn                        :  1;  // Bits 8:8
+    U32 RepeaterClocksOn                        :  1;  // Bits 9:9
+    U32 TxDisable                               :  1;  // Bits 10:10
+    U32 RxDisable                               :  1;  // Bits 11:11
+    U32 TxLong                                  :  1;  // Bits 12:12
+    U32 RxDqsCtle                               :  2;  // Bits 14:13
+    U32 RxReadPointer                           :  3;  // Bits 17:15
+    U32 DriverSegmentEnable                     :  1;  // Bits 18:18
+    U32 DataVccddqHi                            :  1;  // Bits 19:19
+    U32 ReadRFRd                                :  1;  // Bits 20:20
+    U32 ReadRFWr                                :  1;  // Bits 21:21
+    U32 ReadRFRank                              :  2;  // Bits 23:22
+    U32 ForceOdtOn                              :  1;  // Bits 24:24
+    U32 OdtSampOff                              :  1;  // Bits 25:25
+    U32 DisableOdtStatic                        :  1;  // Bits 26:26
+    U32 DdrCRForceODTOn                         :  1;  // Bits 27:27
+    U32 LPDDR_Mode                              :  1;  // Bits 28:28
+    U32 EnReadPreamble                          :  1;  // Bits 29:29
+    U32 OdtSampExtendEn                         :  1;  // Bits 30:30
+    U32 EarlyRleakEn                            :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA7CH1_CR_DDRCRDATACONTROL0_STRUCT;
+
+typedef union {
+  struct {
+    U32 CAVrefCtl                               :  7;  // Bits 6:0
+    U32 Ch1VrefCtl                              :  7;  // Bits 13:7
+    U32 Ch0VrefCtl                              :  7;  // Bits 20:14
+    U32 EnDimmVrefCA                            :  1;  // Bits 21:21
+    U32 EnDimmVrefCh1                           :  1;  // Bits 22:22
+    U32 EnDimmVrefCh0                           :  1;  // Bits 23:23
+    U32 HiZTimerCtrl                            :  2;  // Bits 25:24
+    U32 VccddqHiQnnnH                           :  1;  // Bits 26:26
+    U32 Rsvd                                    :  2;  // Bits 28:27
+    U32 caSlowBW                                :  1;  // Bits 29:29
+    U32 ch0SlowBW                               :  1;  // Bits 30:30
+    U32 ch1SlowBW                               :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA7CH1_CR_DDRCRVREFADJUST1_STRUCT;
+
+typedef union {
+  struct {
+    U32 RxRcvEnPi                               :  9;  // Bits 8:0
+    U32 RxDqsPPi                                :  6;  // Bits 14:9
+    U32 RxEq                                    :  5;  // Bits 19:15
+    U32 RxDqsNPi                                :  6;  // Bits 25:20
+    U32 RxVref                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA8CH0_CR_RXTRAINRANK0_STRUCT;
+
+typedef union {
+  struct {
+    U32 RxRcvEnPi                               :  9;  // Bits 8:0
+    U32 RxDqsPPi                                :  6;  // Bits 14:9
+    U32 RxEq                                    :  5;  // Bits 19:15
+    U32 RxDqsNPi                                :  6;  // Bits 25:20
+    U32 RxVref                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA8CH0_CR_RXTRAINRANK1_STRUCT;
+
+typedef union {
+  struct {
+    U32 RxRcvEnPi                               :  9;  // Bits 8:0
+    U32 RxDqsPPi                                :  6;  // Bits 14:9
+    U32 RxEq                                    :  5;  // Bits 19:15
+    U32 RxDqsNPi                                :  6;  // Bits 25:20
+    U32 RxVref                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA8CH0_CR_RXTRAINRANK2_STRUCT;
+
+typedef union {
+  struct {
+    U32 RxRcvEnPi                               :  9;  // Bits 8:0
+    U32 RxDqsPPi                                :  6;  // Bits 14:9
+    U32 RxEq                                    :  5;  // Bits 19:15
+    U32 RxDqsNPi                                :  6;  // Bits 25:20
+    U32 RxVref                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA8CH0_CR_RXTRAINRANK3_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA8CH0_CR_RXPERBITRANK0_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA8CH0_CR_RXPERBITRANK1_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA8CH0_CR_RXPERBITRANK2_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA8CH0_CR_RXPERBITRANK3_STRUCT;
+
+typedef union {
+  struct {
+    U32 TxDqDelay                               :  9;  // Bits 8:0
+    U32 TxDqsDelay                              :  9;  // Bits 17:9
+    U32 Spare0                                  :  2;  // Bits 19:18
+    U32 TxEqualization                          :  6;  // Bits 25:20
+    U32 Spare1                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA8CH0_CR_TXTRAINRANK0_STRUCT;
+
+typedef union {
+  struct {
+    U32 TxDqDelay                               :  9;  // Bits 8:0
+    U32 TxDqsDelay                              :  9;  // Bits 17:9
+    U32 Spare0                                  :  2;  // Bits 19:18
+    U32 TxEqualization                          :  6;  // Bits 25:20
+    U32 Spare1                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA8CH0_CR_TXTRAINRANK1_STRUCT;
+
+typedef union {
+  struct {
+    U32 TxDqDelay                               :  9;  // Bits 8:0
+    U32 TxDqsDelay                              :  9;  // Bits 17:9
+    U32 Spare0                                  :  2;  // Bits 19:18
+    U32 TxEqualization                          :  6;  // Bits 25:20
+    U32 Spare1                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA8CH0_CR_TXTRAINRANK2_STRUCT;
+
+typedef union {
+  struct {
+    U32 TxDqDelay                               :  9;  // Bits 8:0
+    U32 TxDqsDelay                              :  9;  // Bits 17:9
+    U32 Spare0                                  :  2;  // Bits 19:18
+    U32 TxEqualization                          :  6;  // Bits 25:20
+    U32 Spare1                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA8CH0_CR_TXTRAINRANK3_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA8CH0_CR_TXPERBITRANK0_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA8CH0_CR_TXPERBITRANK1_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA8CH0_CR_TXPERBITRANK2_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA8CH0_CR_TXPERBITRANK3_STRUCT;
+
+typedef union {
+  struct {
+    U32 RcompDrvUp                              :  6;  // Bits 5:0
+    U32 Spare0                                  :  3;  // Bits 8:6
+    U32 RcompDrvDown                            :  6;  // Bits 14:9
+    U32 VTComp                                  :  5;  // Bits 19:15
+    U32 TcoComp                                 :  6;  // Bits 25:20
+    U32 SlewRateComp                            :  5;  // Bits 30:26
+    U32 Spare2                                  :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA8CH0_CR_RCOMPDATA0_STRUCT;
+
+typedef union {
+  struct {
+    U32 RcompOdtUp                              :  6;  // Bits 5:0
+    U32 Spare0                                  :  3;  // Bits 8:6
+    U32 RcompOdtDown                            :  6;  // Bits 14:9
+    U32 Spare1                                  :  1;  // Bits 15:15
+    U32 PanicDrvDn                              :  6;  // Bits 21:16
+    U32 PanicDrvUp                              :  6;  // Bits 27:22
+    U32 LevelShifterComp                        :  3;  // Bits 30:28
+    U32 Spare2                                  :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA8CH0_CR_RCOMPDATA1_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA8CH0_CR_TXXTALK_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA8CH0_CR_RXOFFSETVDQ_STRUCT;
+
+typedef union {
+  struct {
+    U32 Spare                                   :  32;  // Bits 31:0
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA8CH0_CR_DDRDATARESERVED_STRUCT;
+
+typedef union {
+  struct {
+    U32 DataTrainFeedback                       :  9;  // Bits 8:0
+    U32 Spare                                   :  23;  // Bits 31:9
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA8CH0_CR_DATATRAINFEEDBACK_STRUCT;
+
+typedef union {
+  struct {
+    U32 RunTest                                 :  1;  // Bits 0:0
+    U32 Load                                    :  1;  // Bits 1:1
+    U32 ModeHVM                                 :  1;  // Bits 2:2
+    U32 ModeDV                                  :  1;  // Bits 3:3
+    U32 ModeADC                                 :  1;  // Bits 4:4
+    U32 LoadCount                               :  10;  // Bits 14:5
+    U32 CountStatus                             :  10;  // Bits 24:15
+    U32 Spare                                   :  7;  // Bits 31:25
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA8CH0_CR_DLLPITESTANDADC_STRUCT;
+
+typedef union {
+  struct {
+    U32 DqDrvUpCompOffset                       :  6;  // Bits 5:0
+    U32 DqDrvDownCompOffset                     :  6;  // Bits 11:6
+    U32 DqOdtUpCompOffset                       :  5;  // Bits 16:12
+    U32 DqOdtDownCompOffset                     :  5;  // Bits 21:17
+    U32 DqTcoCompOffset                         :  5;  // Bits 26:22
+    U32 DqSlewRateCompOffset                    :  5;  // Bits 31:27
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA8CH0_CR_DDRCRDATAOFFSETCOMP_STRUCT;
+
+typedef union {
+  struct {
+    U32 RefPi                                   :  4;  // Bits 3:0
+    U32 DllMask                                 :  2;  // Bits 5:4
+    U32 DllWeakLock                             :  1;  // Bits 6:6
+    U32 SdllSegmentDisable                      :  3;  // Bits 9:7
+    U32 RxBiasCtl                               :  3;  // Bits 12:10
+    U32 OdtDelay                                :  4;  // Bits 16:13
+    U32 OdtDuration                             :  3;  // Bits 19:17
+    U32 SenseAmpDelay                           :  4;  // Bits 23:20
+    U32 SenseAmpDuration                        :  3;  // Bits 26:24
+    U32 BurstEndODTDelay                        :  3;  // Bits 29:27
+    U32 LpDdrLongOdtEn                          :  1;  // Bits 30:30
+    U32 Rsvd1                                   :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA8CH0_CR_DDRCRDATACONTROL1_STRUCT;
+
+typedef union {
+  struct {
+    U32 RxStaggerCtl                            :  5;  // Bits 4:0
+    U32 ForceBiasOn                             :  1;  // Bits 5:5
+    U32 ForceRxOn                               :  1;  // Bits 6:6
+    U32 LeakerComp                              :  2;  // Bits 8:7
+    U32 RxDqsAmpOffset                          :  4;  // Bits 12:9
+    U32 RxClkStgNum                             :  5;  // Bits 17:13
+    U32 WlLongDelEn                             :  1;  // Bits 18:18
+    U32 Spare                                   :  13;  // Bits 31:19
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA8CH0_CR_DDRCRDATACONTROL2_STRUCT;
+
+typedef union {
+  struct {
+    U32 VssHiOrVrefCtl                          :  24;  // Bits 23:0
+    U32 OutputCode                              :  8;  // Bits 31:24
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA8CH0_CR_DDRCRVSSHIORVREFCONTROL_STRUCT;
+
+typedef union {
+  struct {
+    U32 RcvEnOffset                             :  6;  // Bits 5:0
+    U32 RxDqsOffset                             :  6;  // Bits 11:6
+    U32 TxDqOffset                              :  6;  // Bits 17:12
+    U32 TxDqsOffset                             :  6;  // Bits 23:18
+    U32 VrefOffset                              :  7;  // Bits 30:24
+    U32 Spare                                   :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA8CH0_CR_DDRCRDATAOFFSETTRAIN_STRUCT;
+
+typedef union {
+  struct {
+    U32 RxTrainingMode                          :  1;  // Bits 0:0
+    U32 WLTrainingMode                          :  1;  // Bits 1:1
+    U32 RLTrainingMode                          :  1;  // Bits 2:2
+    U32 SenseampTrainingMode                    :  1;  // Bits 3:3
+    U32 TxOn                                    :  1;  // Bits 4:4
+    U32 RfOn                                    :  1;  // Bits 5:5
+    U32 RxPiOn                                  :  1;  // Bits 6:6
+    U32 TxPiOn                                  :  1;  // Bits 7:7
+    U32 InternalClocksOn                        :  1;  // Bits 8:8
+    U32 RepeaterClocksOn                        :  1;  // Bits 9:9
+    U32 TxDisable                               :  1;  // Bits 10:10
+    U32 RxDisable                               :  1;  // Bits 11:11
+    U32 TxLong                                  :  1;  // Bits 12:12
+    U32 RxDqsCtle                               :  2;  // Bits 14:13
+    U32 RxReadPointer                           :  3;  // Bits 17:15
+    U32 DriverSegmentEnable                     :  1;  // Bits 18:18
+    U32 DataVccddqHi                            :  1;  // Bits 19:19
+    U32 ReadRFRd                                :  1;  // Bits 20:20
+    U32 ReadRFWr                                :  1;  // Bits 21:21
+    U32 ReadRFRank                              :  2;  // Bits 23:22
+    U32 ForceOdtOn                              :  1;  // Bits 24:24
+    U32 OdtSampOff                              :  1;  // Bits 25:25
+    U32 DisableOdtStatic                        :  1;  // Bits 26:26
+    U32 DdrCRForceODTOn                         :  1;  // Bits 27:27
+    U32 LPDDR_Mode                              :  1;  // Bits 28:28
+    U32 EnReadPreamble                          :  1;  // Bits 29:29
+    U32 OdtSampExtendEn                         :  1;  // Bits 30:30
+    U32 EarlyRleakEn                            :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA8CH0_CR_DDRCRDATACONTROL0_STRUCT;
+
+typedef union {
+  struct {
+    U32 CAVrefCtl                               :  7;  // Bits 6:0
+    U32 Ch1VrefCtl                              :  7;  // Bits 13:7
+    U32 Ch0VrefCtl                              :  7;  // Bits 20:14
+    U32 EnDimmVrefCA                            :  1;  // Bits 21:21
+    U32 EnDimmVrefCh1                           :  1;  // Bits 22:22
+    U32 EnDimmVrefCh0                           :  1;  // Bits 23:23
+    U32 HiZTimerCtrl                            :  2;  // Bits 25:24
+    U32 VccddqHiQnnnH                           :  1;  // Bits 26:26
+    U32 Rsvd                                    :  2;  // Bits 28:27
+    U32 caSlowBW                                :  1;  // Bits 29:29
+    U32 ch0SlowBW                               :  1;  // Bits 30:30
+    U32 ch1SlowBW                               :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA8CH0_CR_DDRCRVREFADJUST1_STRUCT;
+
+typedef union {
+  struct {
+    U32 RxRcvEnPi                               :  9;  // Bits 8:0
+    U32 RxDqsPPi                                :  6;  // Bits 14:9
+    U32 RxEq                                    :  5;  // Bits 19:15
+    U32 RxDqsNPi                                :  6;  // Bits 25:20
+    U32 RxVref                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA8CH1_CR_RXTRAINRANK0_STRUCT;
+
+typedef union {
+  struct {
+    U32 RxRcvEnPi                               :  9;  // Bits 8:0
+    U32 RxDqsPPi                                :  6;  // Bits 14:9
+    U32 RxEq                                    :  5;  // Bits 19:15
+    U32 RxDqsNPi                                :  6;  // Bits 25:20
+    U32 RxVref                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA8CH1_CR_RXTRAINRANK1_STRUCT;
+
+typedef union {
+  struct {
+    U32 RxRcvEnPi                               :  9;  // Bits 8:0
+    U32 RxDqsPPi                                :  6;  // Bits 14:9
+    U32 RxEq                                    :  5;  // Bits 19:15
+    U32 RxDqsNPi                                :  6;  // Bits 25:20
+    U32 RxVref                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA8CH1_CR_RXTRAINRANK2_STRUCT;
+
+typedef union {
+  struct {
+    U32 RxRcvEnPi                               :  9;  // Bits 8:0
+    U32 RxDqsPPi                                :  6;  // Bits 14:9
+    U32 RxEq                                    :  5;  // Bits 19:15
+    U32 RxDqsNPi                                :  6;  // Bits 25:20
+    U32 RxVref                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA8CH1_CR_RXTRAINRANK3_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA8CH1_CR_RXPERBITRANK0_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA8CH1_CR_RXPERBITRANK1_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA8CH1_CR_RXPERBITRANK2_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA8CH1_CR_RXPERBITRANK3_STRUCT;
+
+typedef union {
+  struct {
+    U32 TxDqDelay                               :  9;  // Bits 8:0
+    U32 TxDqsDelay                              :  9;  // Bits 17:9
+    U32 Spare0                                  :  2;  // Bits 19:18
+    U32 TxEqualization                          :  6;  // Bits 25:20
+    U32 Spare1                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA8CH1_CR_TXTRAINRANK0_STRUCT;
+
+typedef union {
+  struct {
+    U32 TxDqDelay                               :  9;  // Bits 8:0
+    U32 TxDqsDelay                              :  9;  // Bits 17:9
+    U32 Spare0                                  :  2;  // Bits 19:18
+    U32 TxEqualization                          :  6;  // Bits 25:20
+    U32 Spare1                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA8CH1_CR_TXTRAINRANK1_STRUCT;
+
+typedef union {
+  struct {
+    U32 TxDqDelay                               :  9;  // Bits 8:0
+    U32 TxDqsDelay                              :  9;  // Bits 17:9
+    U32 Spare0                                  :  2;  // Bits 19:18
+    U32 TxEqualization                          :  6;  // Bits 25:20
+    U32 Spare1                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA8CH1_CR_TXTRAINRANK2_STRUCT;
+
+typedef union {
+  struct {
+    U32 TxDqDelay                               :  9;  // Bits 8:0
+    U32 TxDqsDelay                              :  9;  // Bits 17:9
+    U32 Spare0                                  :  2;  // Bits 19:18
+    U32 TxEqualization                          :  6;  // Bits 25:20
+    U32 Spare1                                  :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA8CH1_CR_TXTRAINRANK3_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA8CH1_CR_TXPERBITRANK0_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA8CH1_CR_TXPERBITRANK1_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA8CH1_CR_TXPERBITRANK2_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA8CH1_CR_TXPERBITRANK3_STRUCT;
+
+typedef union {
+  struct {
+    U32 RcompDrvUp                              :  6;  // Bits 5:0
+    U32 Spare0                                  :  3;  // Bits 8:6
+    U32 RcompDrvDown                            :  6;  // Bits 14:9
+    U32 VTComp                                  :  5;  // Bits 19:15
+    U32 TcoComp                                 :  6;  // Bits 25:20
+    U32 SlewRateComp                            :  5;  // Bits 30:26
+    U32 Spare2                                  :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA8CH1_CR_RCOMPDATA0_STRUCT;
+
+typedef union {
+  struct {
+    U32 RcompOdtUp                              :  6;  // Bits 5:0
+    U32 Spare0                                  :  3;  // Bits 8:6
+    U32 RcompOdtDown                            :  6;  // Bits 14:9
+    U32 Spare1                                  :  1;  // Bits 15:15
+    U32 PanicDrvDn                              :  6;  // Bits 21:16
+    U32 PanicDrvUp                              :  6;  // Bits 27:22
+    U32 LevelShifterComp                        :  3;  // Bits 30:28
+    U32 Spare2                                  :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA8CH1_CR_RCOMPDATA1_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA8CH1_CR_TXXTALK_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lane0                                   :  4;  // Bits 3:0
+    U32 Lane1                                   :  4;  // Bits 7:4
+    U32 Lane2                                   :  4;  // Bits 11:8
+    U32 Lane3                                   :  4;  // Bits 15:12
+    U32 Lane4                                   :  4;  // Bits 19:16
+    U32 Lane5                                   :  4;  // Bits 23:20
+    U32 Lane6                                   :  4;  // Bits 27:24
+    U32 Lane7                                   :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA8CH1_CR_RXOFFSETVDQ_STRUCT;
+
+typedef union {
+  struct {
+    U32 Spare                                   :  32;  // Bits 31:0
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA8CH1_CR_DDRDATARESERVED_STRUCT;
+
+typedef union {
+  struct {
+    U32 DataTrainFeedback                       :  9;  // Bits 8:0
+    U32 Spare                                   :  23;  // Bits 31:9
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA8CH1_CR_DATATRAINFEEDBACK_STRUCT;
+
+typedef union {
+  struct {
+    U32 RunTest                                 :  1;  // Bits 0:0
+    U32 Load                                    :  1;  // Bits 1:1
+    U32 ModeHVM                                 :  1;  // Bits 2:2
+    U32 ModeDV                                  :  1;  // Bits 3:3
+    U32 ModeADC                                 :  1;  // Bits 4:4
+    U32 LoadCount                               :  10;  // Bits 14:5
+    U32 CountStatus                             :  10;  // Bits 24:15
+    U32 Spare                                   :  7;  // Bits 31:25
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA8CH1_CR_DLLPITESTANDADC_STRUCT;
+
+typedef union {
+  struct {
+    U32 DqDrvUpCompOffset                       :  6;  // Bits 5:0
+    U32 DqDrvDownCompOffset                     :  6;  // Bits 11:6
+    U32 DqOdtUpCompOffset                       :  5;  // Bits 16:12
+    U32 DqOdtDownCompOffset                     :  5;  // Bits 21:17
+    U32 DqTcoCompOffset                         :  5;  // Bits 26:22
+    U32 DqSlewRateCompOffset                    :  5;  // Bits 31:27
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA8CH1_CR_DDRCRDATAOFFSETCOMP_STRUCT;
+
+typedef union {
+  struct {
+    U32 RefPi                                   :  4;  // Bits 3:0
+    U32 DllMask                                 :  2;  // Bits 5:4
+    U32 DllWeakLock                             :  1;  // Bits 6:6
+    U32 SdllSegmentDisable                      :  3;  // Bits 9:7
+    U32 RxBiasCtl                               :  3;  // Bits 12:10
+    U32 OdtDelay                                :  4;  // Bits 16:13
+    U32 OdtDuration                             :  3;  // Bits 19:17
+    U32 SenseAmpDelay                           :  4;  // Bits 23:20
+    U32 SenseAmpDuration                        :  3;  // Bits 26:24
+    U32 BurstEndODTDelay                        :  3;  // Bits 29:27
+    U32 LpDdrLongOdtEn                          :  1;  // Bits 30:30
+    U32 Rsvd1                                   :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA8CH1_CR_DDRCRDATACONTROL1_STRUCT;
+
+typedef union {
+  struct {
+    U32 RxStaggerCtl                            :  5;  // Bits 4:0
+    U32 ForceBiasOn                             :  1;  // Bits 5:5
+    U32 ForceRxOn                               :  1;  // Bits 6:6
+    U32 LeakerComp                              :  2;  // Bits 8:7
+    U32 RxDqsAmpOffset                          :  4;  // Bits 12:9
+    U32 RxClkStgNum                             :  5;  // Bits 17:13
+    U32 WlLongDelEn                             :  1;  // Bits 18:18
+    U32 Spare                                   :  13;  // Bits 31:19
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA8CH1_CR_DDRCRDATACONTROL2_STRUCT;
+
+typedef union {
+  struct {
+    U32 VssHiOrVrefCtl                          :  24;  // Bits 23:0
+    U32 OutputCode                              :  8;  // Bits 31:24
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA8CH1_CR_DDRCRVSSHIORVREFCONTROL_STRUCT;
+
+typedef union {
+  struct {
+    U32 RcvEnOffset                             :  6;  // Bits 5:0
+    U32 RxDqsOffset                             :  6;  // Bits 11:6
+    U32 TxDqOffset                              :  6;  // Bits 17:12
+    U32 TxDqsOffset                             :  6;  // Bits 23:18
+    U32 VrefOffset                              :  7;  // Bits 30:24
+    U32 Spare                                   :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA8CH1_CR_DDRCRDATAOFFSETTRAIN_STRUCT;
+
+typedef union {
+  struct {
+    U32 RxTrainingMode                          :  1;  // Bits 0:0
+    U32 WLTrainingMode                          :  1;  // Bits 1:1
+    U32 RLTrainingMode                          :  1;  // Bits 2:2
+    U32 SenseampTrainingMode                    :  1;  // Bits 3:3
+    U32 TxOn                                    :  1;  // Bits 4:4
+    U32 RfOn                                    :  1;  // Bits 5:5
+    U32 RxPiOn                                  :  1;  // Bits 6:6
+    U32 TxPiOn                                  :  1;  // Bits 7:7
+    U32 InternalClocksOn                        :  1;  // Bits 8:8
+    U32 RepeaterClocksOn                        :  1;  // Bits 9:9
+    U32 TxDisable                               :  1;  // Bits 10:10
+    U32 RxDisable                               :  1;  // Bits 11:11
+    U32 TxLong                                  :  1;  // Bits 12:12
+    U32 RxDqsCtle                               :  2;  // Bits 14:13
+    U32 RxReadPointer                           :  3;  // Bits 17:15
+    U32 DriverSegmentEnable                     :  1;  // Bits 18:18
+    U32 DataVccddqHi                            :  1;  // Bits 19:19
+    U32 ReadRFRd                                :  1;  // Bits 20:20
+    U32 ReadRFWr                                :  1;  // Bits 21:21
+    U32 ReadRFRank                              :  2;  // Bits 23:22
+    U32 ForceOdtOn                              :  1;  // Bits 24:24
+    U32 OdtSampOff                              :  1;  // Bits 25:25
+    U32 DisableOdtStatic                        :  1;  // Bits 26:26
+    U32 DdrCRForceODTOn                         :  1;  // Bits 27:27
+    U32 LPDDR_Mode                              :  1;  // Bits 28:28
+    U32 EnReadPreamble                          :  1;  // Bits 29:29
+    U32 OdtSampExtendEn                         :  1;  // Bits 30:30
+    U32 EarlyRleakEn                            :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA8CH1_CR_DDRCRDATACONTROL0_STRUCT;
+
+typedef union {
+  struct {
+    U32 CAVrefCtl                               :  7;  // Bits 6:0
+    U32 Ch1VrefCtl                              :  7;  // Bits 13:7
+    U32 Ch0VrefCtl                              :  7;  // Bits 20:14
+    U32 EnDimmVrefCA                            :  1;  // Bits 21:21
+    U32 EnDimmVrefCh1                           :  1;  // Bits 22:22
+    U32 EnDimmVrefCh0                           :  1;  // Bits 23:23
+    U32 HiZTimerCtrl                            :  2;  // Bits 25:24
+    U32 VccddqHiQnnnH                           :  1;  // Bits 26:26
+    U32 Rsvd                                    :  2;  // Bits 28:27
+    U32 caSlowBW                                :  1;  // Bits 29:29
+    U32 ch0SlowBW                               :  1;  // Bits 30:30
+    U32 ch1SlowBW                               :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRDATA8CH1_CR_DDRCRVREFADJUST1_STRUCT;
+
+#define DDRDATA_CR_RXTRAINRANK0_REG                                  (0x00003600)
+  #define DDRDATA_CR_RXTRAINRANK0_RxRcvEnPi_OFF                        ( 0)
+  #define DDRDATA_CR_RXTRAINRANK0_RxRcvEnPi_WID                        ( 9)
+  #define DDRDATA_CR_RXTRAINRANK0_RxRcvEnPi_MSK                        (0x000001FF)
+  #define DDRDATA_CR_RXTRAINRANK0_RxRcvEnPi_MAX                        (0x000001FF)
+  #define DDRDATA_CR_RXTRAINRANK0_RxDqsPPi_OFF                         ( 9)
+  #define DDRDATA_CR_RXTRAINRANK0_RxDqsPPi_WID                         ( 6)
+  #define DDRDATA_CR_RXTRAINRANK0_RxDqsPPi_MSK                         (0x00007E00)
+  #define DDRDATA_CR_RXTRAINRANK0_RxDqsPPi_MAX                         (0x0000003F)
+  #define DDRDATA_CR_RXTRAINRANK0_RxEq_OFF                             (15)
+  #define DDRDATA_CR_RXTRAINRANK0_RxEq_WID                             ( 5)
+  #define DDRDATA_CR_RXTRAINRANK0_RxEq_MSK                             (0x000F8000)
+  #define DDRDATA_CR_RXTRAINRANK0_RxEq_MAX                             (0x0000001F)
+  #define DDRDATA_CR_RXTRAINRANK0_RxDqsNPi_OFF                         (20)
+  #define DDRDATA_CR_RXTRAINRANK0_RxDqsNPi_WID                         ( 6)
+  #define DDRDATA_CR_RXTRAINRANK0_RxDqsNPi_MSK                         (0x03F00000)
+  #define DDRDATA_CR_RXTRAINRANK0_RxDqsNPi_MAX                         (0x0000003F)
+  #define DDRDATA_CR_RXTRAINRANK0_RxVref_OFF                           (26)
+  #define DDRDATA_CR_RXTRAINRANK0_RxVref_WID                           ( 6)
+  #define DDRDATA_CR_RXTRAINRANK0_RxVref_MSK                           (0xFC000000)
+  #define DDRDATA_CR_RXTRAINRANK0_RxVref_MAX                           (0x0000003F)
+
+#define DDRDATA_CR_RXTRAINRANK1_REG                                  (0x00003604)
+  #define DDRDATA_CR_RXTRAINRANK1_RxRcvEnPi_OFF                        ( 0)
+  #define DDRDATA_CR_RXTRAINRANK1_RxRcvEnPi_WID                        ( 9)
+  #define DDRDATA_CR_RXTRAINRANK1_RxRcvEnPi_MSK                        (0x000001FF)
+  #define DDRDATA_CR_RXTRAINRANK1_RxRcvEnPi_MAX                        (0x000001FF)
+  #define DDRDATA_CR_RXTRAINRANK1_RxDqsPPi_OFF                         ( 9)
+  #define DDRDATA_CR_RXTRAINRANK1_RxDqsPPi_WID                         ( 6)
+  #define DDRDATA_CR_RXTRAINRANK1_RxDqsPPi_MSK                         (0x00007E00)
+  #define DDRDATA_CR_RXTRAINRANK1_RxDqsPPi_MAX                         (0x0000003F)
+  #define DDRDATA_CR_RXTRAINRANK1_RxEq_OFF                             (15)
+  #define DDRDATA_CR_RXTRAINRANK1_RxEq_WID                             ( 5)
+  #define DDRDATA_CR_RXTRAINRANK1_RxEq_MSK                             (0x000F8000)
+  #define DDRDATA_CR_RXTRAINRANK1_RxEq_MAX                             (0x0000001F)
+  #define DDRDATA_CR_RXTRAINRANK1_RxDqsNPi_OFF                         (20)
+  #define DDRDATA_CR_RXTRAINRANK1_RxDqsNPi_WID                         ( 6)
+  #define DDRDATA_CR_RXTRAINRANK1_RxDqsNPi_MSK                         (0x03F00000)
+  #define DDRDATA_CR_RXTRAINRANK1_RxDqsNPi_MAX                         (0x0000003F)
+  #define DDRDATA_CR_RXTRAINRANK1_RxVref_OFF                           (26)
+  #define DDRDATA_CR_RXTRAINRANK1_RxVref_WID                           ( 6)
+  #define DDRDATA_CR_RXTRAINRANK1_RxVref_MSK                           (0xFC000000)
+  #define DDRDATA_CR_RXTRAINRANK1_RxVref_MAX                           (0x0000003F)
+
+#define DDRDATA_CR_RXTRAINRANK2_REG                                  (0x00003608)
+  #define DDRDATA_CR_RXTRAINRANK2_RxRcvEnPi_OFF                        ( 0)
+  #define DDRDATA_CR_RXTRAINRANK2_RxRcvEnPi_WID                        ( 9)
+  #define DDRDATA_CR_RXTRAINRANK2_RxRcvEnPi_MSK                        (0x000001FF)
+  #define DDRDATA_CR_RXTRAINRANK2_RxRcvEnPi_MAX                        (0x000001FF)
+  #define DDRDATA_CR_RXTRAINRANK2_RxDqsPPi_OFF                         ( 9)
+  #define DDRDATA_CR_RXTRAINRANK2_RxDqsPPi_WID                         ( 6)
+  #define DDRDATA_CR_RXTRAINRANK2_RxDqsPPi_MSK                         (0x00007E00)
+  #define DDRDATA_CR_RXTRAINRANK2_RxDqsPPi_MAX                         (0x0000003F)
+  #define DDRDATA_CR_RXTRAINRANK2_RxEq_OFF                             (15)
+  #define DDRDATA_CR_RXTRAINRANK2_RxEq_WID                             ( 5)
+  #define DDRDATA_CR_RXTRAINRANK2_RxEq_MSK                             (0x000F8000)
+  #define DDRDATA_CR_RXTRAINRANK2_RxEq_MAX                             (0x0000001F)
+  #define DDRDATA_CR_RXTRAINRANK2_RxDqsNPi_OFF                         (20)
+  #define DDRDATA_CR_RXTRAINRANK2_RxDqsNPi_WID                         ( 6)
+  #define DDRDATA_CR_RXTRAINRANK2_RxDqsNPi_MSK                         (0x03F00000)
+  #define DDRDATA_CR_RXTRAINRANK2_RxDqsNPi_MAX                         (0x0000003F)
+  #define DDRDATA_CR_RXTRAINRANK2_RxVref_OFF                           (26)
+  #define DDRDATA_CR_RXTRAINRANK2_RxVref_WID                           ( 6)
+  #define DDRDATA_CR_RXTRAINRANK2_RxVref_MSK                           (0xFC000000)
+  #define DDRDATA_CR_RXTRAINRANK2_RxVref_MAX                           (0x0000003F)
+
+#define DDRDATA_CR_RXTRAINRANK3_REG                                  (0x0000360C)
+  #define DDRDATA_CR_RXTRAINRANK3_RxRcvEnPi_OFF                        ( 0)
+  #define DDRDATA_CR_RXTRAINRANK3_RxRcvEnPi_WID                        ( 9)
+  #define DDRDATA_CR_RXTRAINRANK3_RxRcvEnPi_MSK                        (0x000001FF)
+  #define DDRDATA_CR_RXTRAINRANK3_RxRcvEnPi_MAX                        (0x000001FF)
+  #define DDRDATA_CR_RXTRAINRANK3_RxDqsPPi_OFF                         ( 9)
+  #define DDRDATA_CR_RXTRAINRANK3_RxDqsPPi_WID                         ( 6)
+  #define DDRDATA_CR_RXTRAINRANK3_RxDqsPPi_MSK                         (0x00007E00)
+  #define DDRDATA_CR_RXTRAINRANK3_RxDqsPPi_MAX                         (0x0000003F)
+  #define DDRDATA_CR_RXTRAINRANK3_RxEq_OFF                             (15)
+  #define DDRDATA_CR_RXTRAINRANK3_RxEq_WID                             ( 5)
+  #define DDRDATA_CR_RXTRAINRANK3_RxEq_MSK                             (0x000F8000)
+  #define DDRDATA_CR_RXTRAINRANK3_RxEq_MAX                             (0x0000001F)
+  #define DDRDATA_CR_RXTRAINRANK3_RxDqsNPi_OFF                         (20)
+  #define DDRDATA_CR_RXTRAINRANK3_RxDqsNPi_WID                         ( 6)
+  #define DDRDATA_CR_RXTRAINRANK3_RxDqsNPi_MSK                         (0x03F00000)
+  #define DDRDATA_CR_RXTRAINRANK3_RxDqsNPi_MAX                         (0x0000003F)
+  #define DDRDATA_CR_RXTRAINRANK3_RxVref_OFF                           (26)
+  #define DDRDATA_CR_RXTRAINRANK3_RxVref_WID                           ( 6)
+  #define DDRDATA_CR_RXTRAINRANK3_RxVref_MSK                           (0xFC000000)
+  #define DDRDATA_CR_RXTRAINRANK3_RxVref_MAX                           (0x0000003F)
+
+#define DDRDATA_CR_RXPERBITRANK0_REG                                 (0x00003610)
+  #define DDRDATA_CR_RXPERBITRANK0_Lane0_OFF                           ( 0)
+  #define DDRDATA_CR_RXPERBITRANK0_Lane0_WID                           ( 4)
+  #define DDRDATA_CR_RXPERBITRANK0_Lane0_MSK                           (0x0000000F)
+  #define DDRDATA_CR_RXPERBITRANK0_Lane0_MAX                           (0x0000000F)
+  #define DDRDATA_CR_RXPERBITRANK0_Lane1_OFF                           ( 4)
+  #define DDRDATA_CR_RXPERBITRANK0_Lane1_WID                           ( 4)
+  #define DDRDATA_CR_RXPERBITRANK0_Lane1_MSK                           (0x000000F0)
+  #define DDRDATA_CR_RXPERBITRANK0_Lane1_MAX                           (0x0000000F)
+  #define DDRDATA_CR_RXPERBITRANK0_Lane2_OFF                           ( 8)
+  #define DDRDATA_CR_RXPERBITRANK0_Lane2_WID                           ( 4)
+  #define DDRDATA_CR_RXPERBITRANK0_Lane2_MSK                           (0x00000F00)
+  #define DDRDATA_CR_RXPERBITRANK0_Lane2_MAX                           (0x0000000F)
+  #define DDRDATA_CR_RXPERBITRANK0_Lane3_OFF                           (12)
+  #define DDRDATA_CR_RXPERBITRANK0_Lane3_WID                           ( 4)
+  #define DDRDATA_CR_RXPERBITRANK0_Lane3_MSK                           (0x0000F000)
+  #define DDRDATA_CR_RXPERBITRANK0_Lane3_MAX                           (0x0000000F)
+  #define DDRDATA_CR_RXPERBITRANK0_Lane4_OFF                           (16)
+  #define DDRDATA_CR_RXPERBITRANK0_Lane4_WID                           ( 4)
+  #define DDRDATA_CR_RXPERBITRANK0_Lane4_MSK                           (0x000F0000)
+  #define DDRDATA_CR_RXPERBITRANK0_Lane4_MAX                           (0x0000000F)
+  #define DDRDATA_CR_RXPERBITRANK0_Lane5_OFF                           (20)
+  #define DDRDATA_CR_RXPERBITRANK0_Lane5_WID                           ( 4)
+  #define DDRDATA_CR_RXPERBITRANK0_Lane5_MSK                           (0x00F00000)
+  #define DDRDATA_CR_RXPERBITRANK0_Lane5_MAX                           (0x0000000F)
+  #define DDRDATA_CR_RXPERBITRANK0_Lane6_OFF                           (24)
+  #define DDRDATA_CR_RXPERBITRANK0_Lane6_WID                           ( 4)
+  #define DDRDATA_CR_RXPERBITRANK0_Lane6_MSK                           (0x0F000000)
+  #define DDRDATA_CR_RXPERBITRANK0_Lane6_MAX                           (0x0000000F)
+  #define DDRDATA_CR_RXPERBITRANK0_Lane7_OFF                           (28)
+  #define DDRDATA_CR_RXPERBITRANK0_Lane7_WID                           ( 4)
+  #define DDRDATA_CR_RXPERBITRANK0_Lane7_MSK                           (0xF0000000)
+  #define DDRDATA_CR_RXPERBITRANK0_Lane7_MAX                           (0x0000000F)
+
+#define DDRDATA_CR_RXPERBITRANK1_REG                                 (0x00003614)
+  #define DDRDATA_CR_RXPERBITRANK1_Lane0_OFF                           ( 0)
+  #define DDRDATA_CR_RXPERBITRANK1_Lane0_WID                           ( 4)
+  #define DDRDATA_CR_RXPERBITRANK1_Lane0_MSK                           (0x0000000F)
+  #define DDRDATA_CR_RXPERBITRANK1_Lane0_MAX                           (0x0000000F)
+  #define DDRDATA_CR_RXPERBITRANK1_Lane1_OFF                           ( 4)
+  #define DDRDATA_CR_RXPERBITRANK1_Lane1_WID                           ( 4)
+  #define DDRDATA_CR_RXPERBITRANK1_Lane1_MSK                           (0x000000F0)
+  #define DDRDATA_CR_RXPERBITRANK1_Lane1_MAX                           (0x0000000F)
+  #define DDRDATA_CR_RXPERBITRANK1_Lane2_OFF                           ( 8)
+  #define DDRDATA_CR_RXPERBITRANK1_Lane2_WID                           ( 4)
+  #define DDRDATA_CR_RXPERBITRANK1_Lane2_MSK                           (0x00000F00)
+  #define DDRDATA_CR_RXPERBITRANK1_Lane2_MAX                           (0x0000000F)
+  #define DDRDATA_CR_RXPERBITRANK1_Lane3_OFF                           (12)
+  #define DDRDATA_CR_RXPERBITRANK1_Lane3_WID                           ( 4)
+  #define DDRDATA_CR_RXPERBITRANK1_Lane3_MSK                           (0x0000F000)
+  #define DDRDATA_CR_RXPERBITRANK1_Lane3_MAX                           (0x0000000F)
+  #define DDRDATA_CR_RXPERBITRANK1_Lane4_OFF                           (16)
+  #define DDRDATA_CR_RXPERBITRANK1_Lane4_WID                           ( 4)
+  #define DDRDATA_CR_RXPERBITRANK1_Lane4_MSK                           (0x000F0000)
+  #define DDRDATA_CR_RXPERBITRANK1_Lane4_MAX                           (0x0000000F)
+  #define DDRDATA_CR_RXPERBITRANK1_Lane5_OFF                           (20)
+  #define DDRDATA_CR_RXPERBITRANK1_Lane5_WID                           ( 4)
+  #define DDRDATA_CR_RXPERBITRANK1_Lane5_MSK                           (0x00F00000)
+  #define DDRDATA_CR_RXPERBITRANK1_Lane5_MAX                           (0x0000000F)
+  #define DDRDATA_CR_RXPERBITRANK1_Lane6_OFF                           (24)
+  #define DDRDATA_CR_RXPERBITRANK1_Lane6_WID                           ( 4)
+  #define DDRDATA_CR_RXPERBITRANK1_Lane6_MSK                           (0x0F000000)
+  #define DDRDATA_CR_RXPERBITRANK1_Lane6_MAX                           (0x0000000F)
+  #define DDRDATA_CR_RXPERBITRANK1_Lane7_OFF                           (28)
+  #define DDRDATA_CR_RXPERBITRANK1_Lane7_WID                           ( 4)
+  #define DDRDATA_CR_RXPERBITRANK1_Lane7_MSK                           (0xF0000000)
+  #define DDRDATA_CR_RXPERBITRANK1_Lane7_MAX                           (0x0000000F)
+
+#define DDRDATA_CR_RXPERBITRANK2_REG                                 (0x00003618)
+  #define DDRDATA_CR_RXPERBITRANK2_Lane0_OFF                           ( 0)
+  #define DDRDATA_CR_RXPERBITRANK2_Lane0_WID                           ( 4)
+  #define DDRDATA_CR_RXPERBITRANK2_Lane0_MSK                           (0x0000000F)
+  #define DDRDATA_CR_RXPERBITRANK2_Lane0_MAX                           (0x0000000F)
+  #define DDRDATA_CR_RXPERBITRANK2_Lane1_OFF                           ( 4)
+  #define DDRDATA_CR_RXPERBITRANK2_Lane1_WID                           ( 4)
+  #define DDRDATA_CR_RXPERBITRANK2_Lane1_MSK                           (0x000000F0)
+  #define DDRDATA_CR_RXPERBITRANK2_Lane1_MAX                           (0x0000000F)
+  #define DDRDATA_CR_RXPERBITRANK2_Lane2_OFF                           ( 8)
+  #define DDRDATA_CR_RXPERBITRANK2_Lane2_WID                           ( 4)
+  #define DDRDATA_CR_RXPERBITRANK2_Lane2_MSK                           (0x00000F00)
+  #define DDRDATA_CR_RXPERBITRANK2_Lane2_MAX                           (0x0000000F)
+  #define DDRDATA_CR_RXPERBITRANK2_Lane3_OFF                           (12)
+  #define DDRDATA_CR_RXPERBITRANK2_Lane3_WID                           ( 4)
+  #define DDRDATA_CR_RXPERBITRANK2_Lane3_MSK                           (0x0000F000)
+  #define DDRDATA_CR_RXPERBITRANK2_Lane3_MAX                           (0x0000000F)
+  #define DDRDATA_CR_RXPERBITRANK2_Lane4_OFF                           (16)
+  #define DDRDATA_CR_RXPERBITRANK2_Lane4_WID                           ( 4)
+  #define DDRDATA_CR_RXPERBITRANK2_Lane4_MSK                           (0x000F0000)
+  #define DDRDATA_CR_RXPERBITRANK2_Lane4_MAX                           (0x0000000F)
+  #define DDRDATA_CR_RXPERBITRANK2_Lane5_OFF                           (20)
+  #define DDRDATA_CR_RXPERBITRANK2_Lane5_WID                           ( 4)
+  #define DDRDATA_CR_RXPERBITRANK2_Lane5_MSK                           (0x00F00000)
+  #define DDRDATA_CR_RXPERBITRANK2_Lane5_MAX                           (0x0000000F)
+  #define DDRDATA_CR_RXPERBITRANK2_Lane6_OFF                           (24)
+  #define DDRDATA_CR_RXPERBITRANK2_Lane6_WID                           ( 4)
+  #define DDRDATA_CR_RXPERBITRANK2_Lane6_MSK                           (0x0F000000)
+  #define DDRDATA_CR_RXPERBITRANK2_Lane6_MAX                           (0x0000000F)
+  #define DDRDATA_CR_RXPERBITRANK2_Lane7_OFF                           (28)
+  #define DDRDATA_CR_RXPERBITRANK2_Lane7_WID                           ( 4)
+  #define DDRDATA_CR_RXPERBITRANK2_Lane7_MSK                           (0xF0000000)
+  #define DDRDATA_CR_RXPERBITRANK2_Lane7_MAX                           (0x0000000F)
+
+#define DDRDATA_CR_RXPERBITRANK3_REG                                 (0x0000361C)
+  #define DDRDATA_CR_RXPERBITRANK3_Lane0_OFF                           ( 0)
+  #define DDRDATA_CR_RXPERBITRANK3_Lane0_WID                           ( 4)
+  #define DDRDATA_CR_RXPERBITRANK3_Lane0_MSK                           (0x0000000F)
+  #define DDRDATA_CR_RXPERBITRANK3_Lane0_MAX                           (0x0000000F)
+  #define DDRDATA_CR_RXPERBITRANK3_Lane1_OFF                           ( 4)
+  #define DDRDATA_CR_RXPERBITRANK3_Lane1_WID                           ( 4)
+  #define DDRDATA_CR_RXPERBITRANK3_Lane1_MSK                           (0x000000F0)
+  #define DDRDATA_CR_RXPERBITRANK3_Lane1_MAX                           (0x0000000F)
+  #define DDRDATA_CR_RXPERBITRANK3_Lane2_OFF                           ( 8)
+  #define DDRDATA_CR_RXPERBITRANK3_Lane2_WID                           ( 4)
+  #define DDRDATA_CR_RXPERBITRANK3_Lane2_MSK                           (0x00000F00)
+  #define DDRDATA_CR_RXPERBITRANK3_Lane2_MAX                           (0x0000000F)
+  #define DDRDATA_CR_RXPERBITRANK3_Lane3_OFF                           (12)
+  #define DDRDATA_CR_RXPERBITRANK3_Lane3_WID                           ( 4)
+  #define DDRDATA_CR_RXPERBITRANK3_Lane3_MSK                           (0x0000F000)
+  #define DDRDATA_CR_RXPERBITRANK3_Lane3_MAX                           (0x0000000F)
+  #define DDRDATA_CR_RXPERBITRANK3_Lane4_OFF                           (16)
+  #define DDRDATA_CR_RXPERBITRANK3_Lane4_WID                           ( 4)
+  #define DDRDATA_CR_RXPERBITRANK3_Lane4_MSK                           (0x000F0000)
+  #define DDRDATA_CR_RXPERBITRANK3_Lane4_MAX                           (0x0000000F)
+  #define DDRDATA_CR_RXPERBITRANK3_Lane5_OFF                           (20)
+  #define DDRDATA_CR_RXPERBITRANK3_Lane5_WID                           ( 4)
+  #define DDRDATA_CR_RXPERBITRANK3_Lane5_MSK                           (0x00F00000)
+  #define DDRDATA_CR_RXPERBITRANK3_Lane5_MAX                           (0x0000000F)
+  #define DDRDATA_CR_RXPERBITRANK3_Lane6_OFF                           (24)
+  #define DDRDATA_CR_RXPERBITRANK3_Lane6_WID                           ( 4)
+  #define DDRDATA_CR_RXPERBITRANK3_Lane6_MSK                           (0x0F000000)
+  #define DDRDATA_CR_RXPERBITRANK3_Lane6_MAX                           (0x0000000F)
+  #define DDRDATA_CR_RXPERBITRANK3_Lane7_OFF                           (28)
+  #define DDRDATA_CR_RXPERBITRANK3_Lane7_WID                           ( 4)
+  #define DDRDATA_CR_RXPERBITRANK3_Lane7_MSK                           (0xF0000000)
+  #define DDRDATA_CR_RXPERBITRANK3_Lane7_MAX                           (0x0000000F)
+
+#define DDRDATA_CR_TXTRAINRANK0_REG                                  (0x00003620)
+  #define DDRDATA_CR_TXTRAINRANK0_TxDqDelay_OFF                        ( 0)
+  #define DDRDATA_CR_TXTRAINRANK0_TxDqDelay_WID                        ( 9)
+  #define DDRDATA_CR_TXTRAINRANK0_TxDqDelay_MSK                        (0x000001FF)
+  #define DDRDATA_CR_TXTRAINRANK0_TxDqDelay_MAX                        (0x000001FF)
+  #define DDRDATA_CR_TXTRAINRANK0_TxDqsDelay_OFF                       ( 9)
+  #define DDRDATA_CR_TXTRAINRANK0_TxDqsDelay_WID                       ( 9)
+  #define DDRDATA_CR_TXTRAINRANK0_TxDqsDelay_MSK                       (0x0003FE00)
+  #define DDRDATA_CR_TXTRAINRANK0_TxDqsDelay_MAX                       (0x000001FF)
+  #define DDRDATA_CR_TXTRAINRANK0_Spare0_OFF                           (18)
+  #define DDRDATA_CR_TXTRAINRANK0_Spare0_WID                           ( 2)
+  #define DDRDATA_CR_TXTRAINRANK0_Spare0_MSK                           (0x000C0000)
+  #define DDRDATA_CR_TXTRAINRANK0_Spare0_MAX                           (0x00000003)
+  #define DDRDATA_CR_TXTRAINRANK0_TxEqualization_OFF                   (20)
+  #define DDRDATA_CR_TXTRAINRANK0_TxEqualization_WID                   ( 6)
+  #define DDRDATA_CR_TXTRAINRANK0_TxEqualization_MSK                   (0x03F00000)
+  #define DDRDATA_CR_TXTRAINRANK0_TxEqualization_MAX                   (0x0000003F)
+  #define DDRDATA_CR_TXTRAINRANK0_Spare1_OFF                           (26)
+  #define DDRDATA_CR_TXTRAINRANK0_Spare1_WID                           ( 6)
+  #define DDRDATA_CR_TXTRAINRANK0_Spare1_MSK                           (0xFC000000)
+  #define DDRDATA_CR_TXTRAINRANK0_Spare1_MAX                           (0x0000003F)
+
+#define DDRDATA_CR_TXTRAINRANK1_REG                                  (0x00003624)
+  #define DDRDATA_CR_TXTRAINRANK1_TxDqDelay_OFF                        ( 0)
+  #define DDRDATA_CR_TXTRAINRANK1_TxDqDelay_WID                        ( 9)
+  #define DDRDATA_CR_TXTRAINRANK1_TxDqDelay_MSK                        (0x000001FF)
+  #define DDRDATA_CR_TXTRAINRANK1_TxDqDelay_MAX                        (0x000001FF)
+  #define DDRDATA_CR_TXTRAINRANK1_TxDqsDelay_OFF                       ( 9)
+  #define DDRDATA_CR_TXTRAINRANK1_TxDqsDelay_WID                       ( 9)
+  #define DDRDATA_CR_TXTRAINRANK1_TxDqsDelay_MSK                       (0x0003FE00)
+  #define DDRDATA_CR_TXTRAINRANK1_TxDqsDelay_MAX                       (0x000001FF)
+  #define DDRDATA_CR_TXTRAINRANK1_Spare0_OFF                           (18)
+  #define DDRDATA_CR_TXTRAINRANK1_Spare0_WID                           ( 2)
+  #define DDRDATA_CR_TXTRAINRANK1_Spare0_MSK                           (0x000C0000)
+  #define DDRDATA_CR_TXTRAINRANK1_Spare0_MAX                           (0x00000003)
+  #define DDRDATA_CR_TXTRAINRANK1_TxEqualization_OFF                   (20)
+  #define DDRDATA_CR_TXTRAINRANK1_TxEqualization_WID                   ( 6)
+  #define DDRDATA_CR_TXTRAINRANK1_TxEqualization_MSK                   (0x03F00000)
+  #define DDRDATA_CR_TXTRAINRANK1_TxEqualization_MAX                   (0x0000003F)
+  #define DDRDATA_CR_TXTRAINRANK1_Spare1_OFF                           (26)
+  #define DDRDATA_CR_TXTRAINRANK1_Spare1_WID                           ( 6)
+  #define DDRDATA_CR_TXTRAINRANK1_Spare1_MSK                           (0xFC000000)
+  #define DDRDATA_CR_TXTRAINRANK1_Spare1_MAX                           (0x0000003F)
+
+#define DDRDATA_CR_TXTRAINRANK2_REG                                  (0x00003628)
+  #define DDRDATA_CR_TXTRAINRANK2_TxDqDelay_OFF                        ( 0)
+  #define DDRDATA_CR_TXTRAINRANK2_TxDqDelay_WID                        ( 9)
+  #define DDRDATA_CR_TXTRAINRANK2_TxDqDelay_MSK                        (0x000001FF)
+  #define DDRDATA_CR_TXTRAINRANK2_TxDqDelay_MAX                        (0x000001FF)
+  #define DDRDATA_CR_TXTRAINRANK2_TxDqsDelay_OFF                       ( 9)
+  #define DDRDATA_CR_TXTRAINRANK2_TxDqsDelay_WID                       ( 9)
+  #define DDRDATA_CR_TXTRAINRANK2_TxDqsDelay_MSK                       (0x0003FE00)
+  #define DDRDATA_CR_TXTRAINRANK2_TxDqsDelay_MAX                       (0x000001FF)
+  #define DDRDATA_CR_TXTRAINRANK2_Spare0_OFF                           (18)
+  #define DDRDATA_CR_TXTRAINRANK2_Spare0_WID                           ( 2)
+  #define DDRDATA_CR_TXTRAINRANK2_Spare0_MSK                           (0x000C0000)
+  #define DDRDATA_CR_TXTRAINRANK2_Spare0_MAX                           (0x00000003)
+  #define DDRDATA_CR_TXTRAINRANK2_TxEqualization_OFF                   (20)
+  #define DDRDATA_CR_TXTRAINRANK2_TxEqualization_WID                   ( 6)
+  #define DDRDATA_CR_TXTRAINRANK2_TxEqualization_MSK                   (0x03F00000)
+  #define DDRDATA_CR_TXTRAINRANK2_TxEqualization_MAX                   (0x0000003F)
+  #define DDRDATA_CR_TXTRAINRANK2_Spare1_OFF                           (26)
+  #define DDRDATA_CR_TXTRAINRANK2_Spare1_WID                           ( 6)
+  #define DDRDATA_CR_TXTRAINRANK2_Spare1_MSK                           (0xFC000000)
+  #define DDRDATA_CR_TXTRAINRANK2_Spare1_MAX                           (0x0000003F)
+
+#define DDRDATA_CR_TXTRAINRANK3_REG                                  (0x0000362C)
+  #define DDRDATA_CR_TXTRAINRANK3_TxDqDelay_OFF                        ( 0)
+  #define DDRDATA_CR_TXTRAINRANK3_TxDqDelay_WID                        ( 9)
+  #define DDRDATA_CR_TXTRAINRANK3_TxDqDelay_MSK                        (0x000001FF)
+  #define DDRDATA_CR_TXTRAINRANK3_TxDqDelay_MAX                        (0x000001FF)
+  #define DDRDATA_CR_TXTRAINRANK3_TxDqsDelay_OFF                       ( 9)
+  #define DDRDATA_CR_TXTRAINRANK3_TxDqsDelay_WID                       ( 9)
+  #define DDRDATA_CR_TXTRAINRANK3_TxDqsDelay_MSK                       (0x0003FE00)
+  #define DDRDATA_CR_TXTRAINRANK3_TxDqsDelay_MAX                       (0x000001FF)
+  #define DDRDATA_CR_TXTRAINRANK3_Spare0_OFF                           (18)
+  #define DDRDATA_CR_TXTRAINRANK3_Spare0_WID                           ( 2)
+  #define DDRDATA_CR_TXTRAINRANK3_Spare0_MSK                           (0x000C0000)
+  #define DDRDATA_CR_TXTRAINRANK3_Spare0_MAX                           (0x00000003)
+  #define DDRDATA_CR_TXTRAINRANK3_TxEqualization_OFF                   (20)
+  #define DDRDATA_CR_TXTRAINRANK3_TxEqualization_WID                   ( 6)
+  #define DDRDATA_CR_TXTRAINRANK3_TxEqualization_MSK                   (0x03F00000)
+  #define DDRDATA_CR_TXTRAINRANK3_TxEqualization_MAX                   (0x0000003F)
+  #define DDRDATA_CR_TXTRAINRANK3_Spare1_OFF                           (26)
+  #define DDRDATA_CR_TXTRAINRANK3_Spare1_WID                           ( 6)
+  #define DDRDATA_CR_TXTRAINRANK3_Spare1_MSK                           (0xFC000000)
+  #define DDRDATA_CR_TXTRAINRANK3_Spare1_MAX                           (0x0000003F)
+
+#define DDRDATA_CR_TXPERBITRANK0_REG                                 (0x00003630)
+  #define DDRDATA_CR_TXPERBITRANK0_Lane0_OFF                           ( 0)
+  #define DDRDATA_CR_TXPERBITRANK0_Lane0_WID                           ( 4)
+  #define DDRDATA_CR_TXPERBITRANK0_Lane0_MSK                           (0x0000000F)
+  #define DDRDATA_CR_TXPERBITRANK0_Lane0_MAX                           (0x0000000F)
+  #define DDRDATA_CR_TXPERBITRANK0_Lane1_OFF                           ( 4)
+  #define DDRDATA_CR_TXPERBITRANK0_Lane1_WID                           ( 4)
+  #define DDRDATA_CR_TXPERBITRANK0_Lane1_MSK                           (0x000000F0)
+  #define DDRDATA_CR_TXPERBITRANK0_Lane1_MAX                           (0x0000000F)
+  #define DDRDATA_CR_TXPERBITRANK0_Lane2_OFF                           ( 8)
+  #define DDRDATA_CR_TXPERBITRANK0_Lane2_WID                           ( 4)
+  #define DDRDATA_CR_TXPERBITRANK0_Lane2_MSK                           (0x00000F00)
+  #define DDRDATA_CR_TXPERBITRANK0_Lane2_MAX                           (0x0000000F)
+  #define DDRDATA_CR_TXPERBITRANK0_Lane3_OFF                           (12)
+  #define DDRDATA_CR_TXPERBITRANK0_Lane3_WID                           ( 4)
+  #define DDRDATA_CR_TXPERBITRANK0_Lane3_MSK                           (0x0000F000)
+  #define DDRDATA_CR_TXPERBITRANK0_Lane3_MAX                           (0x0000000F)
+  #define DDRDATA_CR_TXPERBITRANK0_Lane4_OFF                           (16)
+  #define DDRDATA_CR_TXPERBITRANK0_Lane4_WID                           ( 4)
+  #define DDRDATA_CR_TXPERBITRANK0_Lane4_MSK                           (0x000F0000)
+  #define DDRDATA_CR_TXPERBITRANK0_Lane4_MAX                           (0x0000000F)
+  #define DDRDATA_CR_TXPERBITRANK0_Lane5_OFF                           (20)
+  #define DDRDATA_CR_TXPERBITRANK0_Lane5_WID                           ( 4)
+  #define DDRDATA_CR_TXPERBITRANK0_Lane5_MSK                           (0x00F00000)
+  #define DDRDATA_CR_TXPERBITRANK0_Lane5_MAX                           (0x0000000F)
+  #define DDRDATA_CR_TXPERBITRANK0_Lane6_OFF                           (24)
+  #define DDRDATA_CR_TXPERBITRANK0_Lane6_WID                           ( 4)
+  #define DDRDATA_CR_TXPERBITRANK0_Lane6_MSK                           (0x0F000000)
+  #define DDRDATA_CR_TXPERBITRANK0_Lane6_MAX                           (0x0000000F)
+  #define DDRDATA_CR_TXPERBITRANK0_Lane7_OFF                           (28)
+  #define DDRDATA_CR_TXPERBITRANK0_Lane7_WID                           ( 4)
+  #define DDRDATA_CR_TXPERBITRANK0_Lane7_MSK                           (0xF0000000)
+  #define DDRDATA_CR_TXPERBITRANK0_Lane7_MAX                           (0x0000000F)
+
+#define DDRDATA_CR_TXPERBITRANK1_REG                                 (0x00003634)
+  #define DDRDATA_CR_TXPERBITRANK1_Lane0_OFF                           ( 0)
+  #define DDRDATA_CR_TXPERBITRANK1_Lane0_WID                           ( 4)
+  #define DDRDATA_CR_TXPERBITRANK1_Lane0_MSK                           (0x0000000F)
+  #define DDRDATA_CR_TXPERBITRANK1_Lane0_MAX                           (0x0000000F)
+  #define DDRDATA_CR_TXPERBITRANK1_Lane1_OFF                           ( 4)
+  #define DDRDATA_CR_TXPERBITRANK1_Lane1_WID                           ( 4)
+  #define DDRDATA_CR_TXPERBITRANK1_Lane1_MSK                           (0x000000F0)
+  #define DDRDATA_CR_TXPERBITRANK1_Lane1_MAX                           (0x0000000F)
+  #define DDRDATA_CR_TXPERBITRANK1_Lane2_OFF                           ( 8)
+  #define DDRDATA_CR_TXPERBITRANK1_Lane2_WID                           ( 4)
+  #define DDRDATA_CR_TXPERBITRANK1_Lane2_MSK                           (0x00000F00)
+  #define DDRDATA_CR_TXPERBITRANK1_Lane2_MAX                           (0x0000000F)
+  #define DDRDATA_CR_TXPERBITRANK1_Lane3_OFF                           (12)
+  #define DDRDATA_CR_TXPERBITRANK1_Lane3_WID                           ( 4)
+  #define DDRDATA_CR_TXPERBITRANK1_Lane3_MSK                           (0x0000F000)
+  #define DDRDATA_CR_TXPERBITRANK1_Lane3_MAX                           (0x0000000F)
+  #define DDRDATA_CR_TXPERBITRANK1_Lane4_OFF                           (16)
+  #define DDRDATA_CR_TXPERBITRANK1_Lane4_WID                           ( 4)
+  #define DDRDATA_CR_TXPERBITRANK1_Lane4_MSK                           (0x000F0000)
+  #define DDRDATA_CR_TXPERBITRANK1_Lane4_MAX                           (0x0000000F)
+  #define DDRDATA_CR_TXPERBITRANK1_Lane5_OFF                           (20)
+  #define DDRDATA_CR_TXPERBITRANK1_Lane5_WID                           ( 4)
+  #define DDRDATA_CR_TXPERBITRANK1_Lane5_MSK                           (0x00F00000)
+  #define DDRDATA_CR_TXPERBITRANK1_Lane5_MAX                           (0x0000000F)
+  #define DDRDATA_CR_TXPERBITRANK1_Lane6_OFF                           (24)
+  #define DDRDATA_CR_TXPERBITRANK1_Lane6_WID                           ( 4)
+  #define DDRDATA_CR_TXPERBITRANK1_Lane6_MSK                           (0x0F000000)
+  #define DDRDATA_CR_TXPERBITRANK1_Lane6_MAX                           (0x0000000F)
+  #define DDRDATA_CR_TXPERBITRANK1_Lane7_OFF                           (28)
+  #define DDRDATA_CR_TXPERBITRANK1_Lane7_WID                           ( 4)
+  #define DDRDATA_CR_TXPERBITRANK1_Lane7_MSK                           (0xF0000000)
+  #define DDRDATA_CR_TXPERBITRANK1_Lane7_MAX                           (0x0000000F)
+
+#define DDRDATA_CR_TXPERBITRANK2_REG                                 (0x00003638)
+  #define DDRDATA_CR_TXPERBITRANK2_Lane0_OFF                           ( 0)
+  #define DDRDATA_CR_TXPERBITRANK2_Lane0_WID                           ( 4)
+  #define DDRDATA_CR_TXPERBITRANK2_Lane0_MSK                           (0x0000000F)
+  #define DDRDATA_CR_TXPERBITRANK2_Lane0_MAX                           (0x0000000F)
+  #define DDRDATA_CR_TXPERBITRANK2_Lane1_OFF                           ( 4)
+  #define DDRDATA_CR_TXPERBITRANK2_Lane1_WID                           ( 4)
+  #define DDRDATA_CR_TXPERBITRANK2_Lane1_MSK                           (0x000000F0)
+  #define DDRDATA_CR_TXPERBITRANK2_Lane1_MAX                           (0x0000000F)
+  #define DDRDATA_CR_TXPERBITRANK2_Lane2_OFF                           ( 8)
+  #define DDRDATA_CR_TXPERBITRANK2_Lane2_WID                           ( 4)
+  #define DDRDATA_CR_TXPERBITRANK2_Lane2_MSK                           (0x00000F00)
+  #define DDRDATA_CR_TXPERBITRANK2_Lane2_MAX                           (0x0000000F)
+  #define DDRDATA_CR_TXPERBITRANK2_Lane3_OFF                           (12)
+  #define DDRDATA_CR_TXPERBITRANK2_Lane3_WID                           ( 4)
+  #define DDRDATA_CR_TXPERBITRANK2_Lane3_MSK                           (0x0000F000)
+  #define DDRDATA_CR_TXPERBITRANK2_Lane3_MAX                           (0x0000000F)
+  #define DDRDATA_CR_TXPERBITRANK2_Lane4_OFF                           (16)
+  #define DDRDATA_CR_TXPERBITRANK2_Lane4_WID                           ( 4)
+  #define DDRDATA_CR_TXPERBITRANK2_Lane4_MSK                           (0x000F0000)
+  #define DDRDATA_CR_TXPERBITRANK2_Lane4_MAX                           (0x0000000F)
+  #define DDRDATA_CR_TXPERBITRANK2_Lane5_OFF                           (20)
+  #define DDRDATA_CR_TXPERBITRANK2_Lane5_WID                           ( 4)
+  #define DDRDATA_CR_TXPERBITRANK2_Lane5_MSK                           (0x00F00000)
+  #define DDRDATA_CR_TXPERBITRANK2_Lane5_MAX                           (0x0000000F)
+  #define DDRDATA_CR_TXPERBITRANK2_Lane6_OFF                           (24)
+  #define DDRDATA_CR_TXPERBITRANK2_Lane6_WID                           ( 4)
+  #define DDRDATA_CR_TXPERBITRANK2_Lane6_MSK                           (0x0F000000)
+  #define DDRDATA_CR_TXPERBITRANK2_Lane6_MAX                           (0x0000000F)
+  #define DDRDATA_CR_TXPERBITRANK2_Lane7_OFF                           (28)
+  #define DDRDATA_CR_TXPERBITRANK2_Lane7_WID                           ( 4)
+  #define DDRDATA_CR_TXPERBITRANK2_Lane7_MSK                           (0xF0000000)
+  #define DDRDATA_CR_TXPERBITRANK2_Lane7_MAX                           (0x0000000F)
+
+#define DDRDATA_CR_TXPERBITRANK3_REG                                 (0x0000363C)
+  #define DDRDATA_CR_TXPERBITRANK3_Lane0_OFF                           ( 0)
+  #define DDRDATA_CR_TXPERBITRANK3_Lane0_WID                           ( 4)
+  #define DDRDATA_CR_TXPERBITRANK3_Lane0_MSK                           (0x0000000F)
+  #define DDRDATA_CR_TXPERBITRANK3_Lane0_MAX                           (0x0000000F)
+  #define DDRDATA_CR_TXPERBITRANK3_Lane1_OFF                           ( 4)
+  #define DDRDATA_CR_TXPERBITRANK3_Lane1_WID                           ( 4)
+  #define DDRDATA_CR_TXPERBITRANK3_Lane1_MSK                           (0x000000F0)
+  #define DDRDATA_CR_TXPERBITRANK3_Lane1_MAX                           (0x0000000F)
+  #define DDRDATA_CR_TXPERBITRANK3_Lane2_OFF                           ( 8)
+  #define DDRDATA_CR_TXPERBITRANK3_Lane2_WID                           ( 4)
+  #define DDRDATA_CR_TXPERBITRANK3_Lane2_MSK                           (0x00000F00)
+  #define DDRDATA_CR_TXPERBITRANK3_Lane2_MAX                           (0x0000000F)
+  #define DDRDATA_CR_TXPERBITRANK3_Lane3_OFF                           (12)
+  #define DDRDATA_CR_TXPERBITRANK3_Lane3_WID                           ( 4)
+  #define DDRDATA_CR_TXPERBITRANK3_Lane3_MSK                           (0x0000F000)
+  #define DDRDATA_CR_TXPERBITRANK3_Lane3_MAX                           (0x0000000F)
+  #define DDRDATA_CR_TXPERBITRANK3_Lane4_OFF                           (16)
+  #define DDRDATA_CR_TXPERBITRANK3_Lane4_WID                           ( 4)
+  #define DDRDATA_CR_TXPERBITRANK3_Lane4_MSK                           (0x000F0000)
+  #define DDRDATA_CR_TXPERBITRANK3_Lane4_MAX                           (0x0000000F)
+  #define DDRDATA_CR_TXPERBITRANK3_Lane5_OFF                           (20)
+  #define DDRDATA_CR_TXPERBITRANK3_Lane5_WID                           ( 4)
+  #define DDRDATA_CR_TXPERBITRANK3_Lane5_MSK                           (0x00F00000)
+  #define DDRDATA_CR_TXPERBITRANK3_Lane5_MAX                           (0x0000000F)
+  #define DDRDATA_CR_TXPERBITRANK3_Lane6_OFF                           (24)
+  #define DDRDATA_CR_TXPERBITRANK3_Lane6_WID                           ( 4)
+  #define DDRDATA_CR_TXPERBITRANK3_Lane6_MSK                           (0x0F000000)
+  #define DDRDATA_CR_TXPERBITRANK3_Lane6_MAX                           (0x0000000F)
+  #define DDRDATA_CR_TXPERBITRANK3_Lane7_OFF                           (28)
+  #define DDRDATA_CR_TXPERBITRANK3_Lane7_WID                           ( 4)
+  #define DDRDATA_CR_TXPERBITRANK3_Lane7_MSK                           (0xF0000000)
+  #define DDRDATA_CR_TXPERBITRANK3_Lane7_MAX                           (0x0000000F)
+
+#define DDRDATA_CR_RCOMPDATA0_REG                                    (0x00003640)
+  #define DDRDATA_CR_RCOMPDATA0_RcompDrvUp_OFF                         ( 0)
+  #define DDRDATA_CR_RCOMPDATA0_RcompDrvUp_WID                         ( 6)
+  #define DDRDATA_CR_RCOMPDATA0_RcompDrvUp_MSK                         (0x0000003F)
+  #define DDRDATA_CR_RCOMPDATA0_RcompDrvUp_MAX                         (0x0000003F)
+  #define DDRDATA_CR_RCOMPDATA0_Spare0_OFF                             ( 6)
+  #define DDRDATA_CR_RCOMPDATA0_Spare0_WID                             ( 3)
+  #define DDRDATA_CR_RCOMPDATA0_Spare0_MSK                             (0x000001C0)
+  #define DDRDATA_CR_RCOMPDATA0_Spare0_MAX                             (0x00000007)
+  #define DDRDATA_CR_RCOMPDATA0_RcompDrvDown_OFF                       ( 9)
+  #define DDRDATA_CR_RCOMPDATA0_RcompDrvDown_WID                       ( 6)
+  #define DDRDATA_CR_RCOMPDATA0_RcompDrvDown_MSK                       (0x00007E00)
+  #define DDRDATA_CR_RCOMPDATA0_RcompDrvDown_MAX                       (0x0000003F)
+  #define DDRDATA_CR_RCOMPDATA0_VTComp_OFF                             (15)
+  #define DDRDATA_CR_RCOMPDATA0_VTComp_WID                             ( 5)
+  #define DDRDATA_CR_RCOMPDATA0_VTComp_MSK                             (0x000F8000)
+  #define DDRDATA_CR_RCOMPDATA0_VTComp_MAX                             (0x0000001F)
+  #define DDRDATA_CR_RCOMPDATA0_TcoComp_OFF                            (20)
+  #define DDRDATA_CR_RCOMPDATA0_TcoComp_WID                            ( 6)
+  #define DDRDATA_CR_RCOMPDATA0_TcoComp_MSK                            (0x03F00000)
+  #define DDRDATA_CR_RCOMPDATA0_TcoComp_MAX                            (0x0000003F)
+  #define DDRDATA_CR_RCOMPDATA0_SlewRateComp_OFF                       (26)
+  #define DDRDATA_CR_RCOMPDATA0_SlewRateComp_WID                       ( 5)
+  #define DDRDATA_CR_RCOMPDATA0_SlewRateComp_MSK                       (0x7C000000)
+  #define DDRDATA_CR_RCOMPDATA0_SlewRateComp_MAX                       (0x0000001F)
+  #define DDRDATA_CR_RCOMPDATA0_Spare2_OFF                             (31)
+  #define DDRDATA_CR_RCOMPDATA0_Spare2_WID                             ( 1)
+  #define DDRDATA_CR_RCOMPDATA0_Spare2_MSK                             (0x80000000)
+  #define DDRDATA_CR_RCOMPDATA0_Spare2_MAX                             (0x00000001)
+
+#define DDRDATA_CR_RCOMPDATA1_REG                                    (0x00003644)
+  #define DDRDATA_CR_RCOMPDATA1_RcompOdtUp_OFF                         ( 0)
+  #define DDRDATA_CR_RCOMPDATA1_RcompOdtUp_WID                         ( 6)
+  #define DDRDATA_CR_RCOMPDATA1_RcompOdtUp_MSK                         (0x0000003F)
+  #define DDRDATA_CR_RCOMPDATA1_RcompOdtUp_MAX                         (0x0000003F)
+  #define DDRDATA_CR_RCOMPDATA1_Spare0_OFF                             ( 6)
+  #define DDRDATA_CR_RCOMPDATA1_Spare0_WID                             ( 3)
+  #define DDRDATA_CR_RCOMPDATA1_Spare0_MSK                             (0x000001C0)
+  #define DDRDATA_CR_RCOMPDATA1_Spare0_MAX                             (0x00000007)
+  #define DDRDATA_CR_RCOMPDATA1_RcompOdtDown_OFF                       ( 9)
+  #define DDRDATA_CR_RCOMPDATA1_RcompOdtDown_WID                       ( 6)
+  #define DDRDATA_CR_RCOMPDATA1_RcompOdtDown_MSK                       (0x00007E00)
+  #define DDRDATA_CR_RCOMPDATA1_RcompOdtDown_MAX                       (0x0000003F)
+  #define DDRDATA_CR_RCOMPDATA1_Spare1_OFF                             (15)
+  #define DDRDATA_CR_RCOMPDATA1_Spare1_WID                             ( 1)
+  #define DDRDATA_CR_RCOMPDATA1_Spare1_MSK                             (0x00008000)
+  #define DDRDATA_CR_RCOMPDATA1_Spare1_MAX                             (0x00000001)
+  #define DDRDATA_CR_RCOMPDATA1_PanicDrvDn_OFF                         (16)
+  #define DDRDATA_CR_RCOMPDATA1_PanicDrvDn_WID                         ( 6)
+  #define DDRDATA_CR_RCOMPDATA1_PanicDrvDn_MSK                         (0x003F0000)
+  #define DDRDATA_CR_RCOMPDATA1_PanicDrvDn_MAX                         (0x0000003F)
+  #define DDRDATA_CR_RCOMPDATA1_PanicDrvUp_OFF                         (22)
+  #define DDRDATA_CR_RCOMPDATA1_PanicDrvUp_WID                         ( 6)
+  #define DDRDATA_CR_RCOMPDATA1_PanicDrvUp_MSK                         (0x0FC00000)
+  #define DDRDATA_CR_RCOMPDATA1_PanicDrvUp_MAX                         (0x0000003F)
+  #define DDRDATA_CR_RCOMPDATA1_LevelShifterComp_OFF                   (28)
+  #define DDRDATA_CR_RCOMPDATA1_LevelShifterComp_WID                   ( 3)
+  #define DDRDATA_CR_RCOMPDATA1_LevelShifterComp_MSK                   (0x70000000)
+  #define DDRDATA_CR_RCOMPDATA1_LevelShifterComp_MAX                   (0x00000007)
+  #define DDRDATA_CR_RCOMPDATA1_Spare2_OFF                             (31)
+  #define DDRDATA_CR_RCOMPDATA1_Spare2_WID                             ( 1)
+  #define DDRDATA_CR_RCOMPDATA1_Spare2_MSK                             (0x80000000)
+  #define DDRDATA_CR_RCOMPDATA1_Spare2_MAX                             (0x00000001)
+
+#define DDRDATA_CR_TXXTALK_REG                                       (0x00003648)
+  #define DDRDATA_CR_TXXTALK_Lane0_OFF                                 ( 0)
+  #define DDRDATA_CR_TXXTALK_Lane0_WID                                 ( 4)
+  #define DDRDATA_CR_TXXTALK_Lane0_MSK                                 (0x0000000F)
+  #define DDRDATA_CR_TXXTALK_Lane0_MAX                                 (0x0000000F)
+  #define DDRDATA_CR_TXXTALK_Lane1_OFF                                 ( 4)
+  #define DDRDATA_CR_TXXTALK_Lane1_WID                                 ( 4)
+  #define DDRDATA_CR_TXXTALK_Lane1_MSK                                 (0x000000F0)
+  #define DDRDATA_CR_TXXTALK_Lane1_MAX                                 (0x0000000F)
+  #define DDRDATA_CR_TXXTALK_Lane2_OFF                                 ( 8)
+  #define DDRDATA_CR_TXXTALK_Lane2_WID                                 ( 4)
+  #define DDRDATA_CR_TXXTALK_Lane2_MSK                                 (0x00000F00)
+  #define DDRDATA_CR_TXXTALK_Lane2_MAX                                 (0x0000000F)
+  #define DDRDATA_CR_TXXTALK_Lane3_OFF                                 (12)
+  #define DDRDATA_CR_TXXTALK_Lane3_WID                                 ( 4)
+  #define DDRDATA_CR_TXXTALK_Lane3_MSK                                 (0x0000F000)
+  #define DDRDATA_CR_TXXTALK_Lane3_MAX                                 (0x0000000F)
+  #define DDRDATA_CR_TXXTALK_Lane4_OFF                                 (16)
+  #define DDRDATA_CR_TXXTALK_Lane4_WID                                 ( 4)
+  #define DDRDATA_CR_TXXTALK_Lane4_MSK                                 (0x000F0000)
+  #define DDRDATA_CR_TXXTALK_Lane4_MAX                                 (0x0000000F)
+  #define DDRDATA_CR_TXXTALK_Lane5_OFF                                 (20)
+  #define DDRDATA_CR_TXXTALK_Lane5_WID                                 ( 4)
+  #define DDRDATA_CR_TXXTALK_Lane5_MSK                                 (0x00F00000)
+  #define DDRDATA_CR_TXXTALK_Lane5_MAX                                 (0x0000000F)
+  #define DDRDATA_CR_TXXTALK_Lane6_OFF                                 (24)
+  #define DDRDATA_CR_TXXTALK_Lane6_WID                                 ( 4)
+  #define DDRDATA_CR_TXXTALK_Lane6_MSK                                 (0x0F000000)
+  #define DDRDATA_CR_TXXTALK_Lane6_MAX                                 (0x0000000F)
+  #define DDRDATA_CR_TXXTALK_Lane7_OFF                                 (28)
+  #define DDRDATA_CR_TXXTALK_Lane7_WID                                 ( 4)
+  #define DDRDATA_CR_TXXTALK_Lane7_MSK                                 (0xF0000000)
+  #define DDRDATA_CR_TXXTALK_Lane7_MAX                                 (0x0000000F)
+
+#define DDRDATA_CR_RXOFFSETVDQ_REG                                   (0x0000364C)
+  #define DDRDATA_CR_RXOFFSETVDQ_Lane0_OFF                             ( 0)
+  #define DDRDATA_CR_RXOFFSETVDQ_Lane0_WID                             ( 4)
+  #define DDRDATA_CR_RXOFFSETVDQ_Lane0_MSK                             (0x0000000F)
+  #define DDRDATA_CR_RXOFFSETVDQ_Lane0_MAX                             (0x0000000F)
+  #define DDRDATA_CR_RXOFFSETVDQ_Lane1_OFF                             ( 4)
+  #define DDRDATA_CR_RXOFFSETVDQ_Lane1_WID                             ( 4)
+  #define DDRDATA_CR_RXOFFSETVDQ_Lane1_MSK                             (0x000000F0)
+  #define DDRDATA_CR_RXOFFSETVDQ_Lane1_MAX                             (0x0000000F)
+  #define DDRDATA_CR_RXOFFSETVDQ_Lane2_OFF                             ( 8)
+  #define DDRDATA_CR_RXOFFSETVDQ_Lane2_WID                             ( 4)
+  #define DDRDATA_CR_RXOFFSETVDQ_Lane2_MSK                             (0x00000F00)
+  #define DDRDATA_CR_RXOFFSETVDQ_Lane2_MAX                             (0x0000000F)
+  #define DDRDATA_CR_RXOFFSETVDQ_Lane3_OFF                             (12)
+  #define DDRDATA_CR_RXOFFSETVDQ_Lane3_WID                             ( 4)
+  #define DDRDATA_CR_RXOFFSETVDQ_Lane3_MSK                             (0x0000F000)
+  #define DDRDATA_CR_RXOFFSETVDQ_Lane3_MAX                             (0x0000000F)
+  #define DDRDATA_CR_RXOFFSETVDQ_Lane4_OFF                             (16)
+  #define DDRDATA_CR_RXOFFSETVDQ_Lane4_WID                             ( 4)
+  #define DDRDATA_CR_RXOFFSETVDQ_Lane4_MSK                             (0x000F0000)
+  #define DDRDATA_CR_RXOFFSETVDQ_Lane4_MAX                             (0x0000000F)
+  #define DDRDATA_CR_RXOFFSETVDQ_Lane5_OFF                             (20)
+  #define DDRDATA_CR_RXOFFSETVDQ_Lane5_WID                             ( 4)
+  #define DDRDATA_CR_RXOFFSETVDQ_Lane5_MSK                             (0x00F00000)
+  #define DDRDATA_CR_RXOFFSETVDQ_Lane5_MAX                             (0x0000000F)
+  #define DDRDATA_CR_RXOFFSETVDQ_Lane6_OFF                             (24)
+  #define DDRDATA_CR_RXOFFSETVDQ_Lane6_WID                             ( 4)
+  #define DDRDATA_CR_RXOFFSETVDQ_Lane6_MSK                             (0x0F000000)
+  #define DDRDATA_CR_RXOFFSETVDQ_Lane6_MAX                             (0x0000000F)
+  #define DDRDATA_CR_RXOFFSETVDQ_Lane7_OFF                             (28)
+  #define DDRDATA_CR_RXOFFSETVDQ_Lane7_WID                             ( 4)
+  #define DDRDATA_CR_RXOFFSETVDQ_Lane7_MSK                             (0xF0000000)
+  #define DDRDATA_CR_RXOFFSETVDQ_Lane7_MAX                             (0x0000000F)
+
+#define DDRDATA_CR_DDRDATARESERVED_REG                               (0x00003650)
+  #define DDRDATA_CR_DDRDATARESERVED_Spare_OFF                         ( 0)
+  #define DDRDATA_CR_DDRDATARESERVED_Spare_WID                         (32)
+  #define DDRDATA_CR_DDRDATARESERVED_Spare_MSK                         (0xFFFFFFFF)
+  #define DDRDATA_CR_DDRDATARESERVED_Spare_MAX                         (0xFFFFFFFF)
+
+#define DDRDATA_CR_DATATRAINFEEDBACK_REG                             (0x00003654)
+  #define DDRDATA_CR_DATATRAINFEEDBACK_DataTrainFeedback_OFF           ( 0)
+  #define DDRDATA_CR_DATATRAINFEEDBACK_DataTrainFeedback_WID           ( 9)
+  #define DDRDATA_CR_DATATRAINFEEDBACK_DataTrainFeedback_MSK           (0x000001FF)
+  #define DDRDATA_CR_DATATRAINFEEDBACK_DataTrainFeedback_MAX           (0x000001FF)
+  #define DDRDATA_CR_DATATRAINFEEDBACK_Spare_OFF                       ( 9)
+  #define DDRDATA_CR_DATATRAINFEEDBACK_Spare_WID                       (23)
+  #define DDRDATA_CR_DATATRAINFEEDBACK_Spare_MSK                       (0xFFFFFE00)
+  #define DDRDATA_CR_DATATRAINFEEDBACK_Spare_MAX                       (0x007FFFFF)
+
+#define DDRDATA_CR_DLLPITESTANDADC_REG                               (0x00003658)
+  #define DDRDATA_CR_DLLPITESTANDADC_RunTest_OFF                       ( 0)
+  #define DDRDATA_CR_DLLPITESTANDADC_RunTest_WID                       ( 1)
+  #define DDRDATA_CR_DLLPITESTANDADC_RunTest_MSK                       (0x00000001)
+  #define DDRDATA_CR_DLLPITESTANDADC_RunTest_MAX                       (0x00000001)
+  #define DDRDATA_CR_DLLPITESTANDADC_RunTest_DEF                       (0x00000000)
+  #define DDRDATA_CR_DLLPITESTANDADC_Load_OFF                          ( 1)
+  #define DDRDATA_CR_DLLPITESTANDADC_Load_WID                          ( 1)
+  #define DDRDATA_CR_DLLPITESTANDADC_Load_MSK                          (0x00000002)
+  #define DDRDATA_CR_DLLPITESTANDADC_Load_MAX                          (0x00000001)
+  #define DDRDATA_CR_DLLPITESTANDADC_Load_DEF                          (0x00000000)
+  #define DDRDATA_CR_DLLPITESTANDADC_ModeHVM_OFF                       ( 2)
+  #define DDRDATA_CR_DLLPITESTANDADC_ModeHVM_WID                       ( 1)
+  #define DDRDATA_CR_DLLPITESTANDADC_ModeHVM_MSK                       (0x00000004)
+  #define DDRDATA_CR_DLLPITESTANDADC_ModeHVM_MAX                       (0x00000001)
+  #define DDRDATA_CR_DLLPITESTANDADC_ModeHVM_DEF                       (0x00000000)
+  #define DDRDATA_CR_DLLPITESTANDADC_ModeDV_OFF                        ( 3)
+  #define DDRDATA_CR_DLLPITESTANDADC_ModeDV_WID                        ( 1)
+  #define DDRDATA_CR_DLLPITESTANDADC_ModeDV_MSK                        (0x00000008)
+  #define DDRDATA_CR_DLLPITESTANDADC_ModeDV_MAX                        (0x00000001)
+  #define DDRDATA_CR_DLLPITESTANDADC_ModeDV_DEF                        (0x00000000)
+  #define DDRDATA_CR_DLLPITESTANDADC_ModeADC_OFF                       ( 4)
+  #define DDRDATA_CR_DLLPITESTANDADC_ModeADC_WID                       ( 1)
+  #define DDRDATA_CR_DLLPITESTANDADC_ModeADC_MSK                       (0x00000010)
+  #define DDRDATA_CR_DLLPITESTANDADC_ModeADC_MAX                       (0x00000001)
+  #define DDRDATA_CR_DLLPITESTANDADC_ModeADC_DEF                       (0x00000000)
+  #define DDRDATA_CR_DLLPITESTANDADC_LoadCount_OFF                     ( 5)
+  #define DDRDATA_CR_DLLPITESTANDADC_LoadCount_WID                     (10)
+  #define DDRDATA_CR_DLLPITESTANDADC_LoadCount_MSK                     (0x00007FE0)
+  #define DDRDATA_CR_DLLPITESTANDADC_LoadCount_MAX                     (0x000003FF)
+  #define DDRDATA_CR_DLLPITESTANDADC_CountStatus_OFF                   (15)
+  #define DDRDATA_CR_DLLPITESTANDADC_CountStatus_WID                   (10)
+  #define DDRDATA_CR_DLLPITESTANDADC_CountStatus_MSK                   (0x01FF8000)
+  #define DDRDATA_CR_DLLPITESTANDADC_CountStatus_MAX                   (0x000003FF)
+  #define DDRDATA_CR_DLLPITESTANDADC_CountStatus_DEF                   (0x00000000)
+  #define DDRDATA_CR_DLLPITESTANDADC_Spare_OFF                         (25)
+  #define DDRDATA_CR_DLLPITESTANDADC_Spare_WID                         ( 7)
+  #define DDRDATA_CR_DLLPITESTANDADC_Spare_MSK                         (0xFE000000)
+  #define DDRDATA_CR_DLLPITESTANDADC_Spare_MAX                         (0x0000007F)
+
+#define DDRDATA_CR_DDRCRDATAOFFSETCOMP_REG                           (0x0000365C)
+  #define DDRDATA_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_OFF         ( 0)
+  #define DDRDATA_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_WID         ( 6)
+  #define DDRDATA_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MSK         (0x0000003F)
+  #define DDRDATA_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MAX         (0x0000003F)
+  #define DDRDATA_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_DEF         (0x00000000)
+  #define DDRDATA_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_OFF       ( 6)
+  #define DDRDATA_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_WID       ( 6)
+  #define DDRDATA_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MSK       (0x00000FC0)
+  #define DDRDATA_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MAX       (0x0000003F)
+  #define DDRDATA_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_DEF       (0x00000000)
+  #define DDRDATA_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_OFF         (12)
+  #define DDRDATA_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_WID         ( 5)
+  #define DDRDATA_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MSK         (0x0001F000)
+  #define DDRDATA_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MAX         (0x0000001F)
+  #define DDRDATA_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_DEF         (0x00000000)
+  #define DDRDATA_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_OFF       (17)
+  #define DDRDATA_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_WID       ( 5)
+  #define DDRDATA_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MSK       (0x003E0000)
+  #define DDRDATA_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MAX       (0x0000001F)
+  #define DDRDATA_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_DEF       (0x00000000)
+  #define DDRDATA_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_OFF           (22)
+  #define DDRDATA_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_WID           ( 5)
+  #define DDRDATA_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_MSK           (0x07C00000)
+  #define DDRDATA_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_MAX           (0x0000001F)
+  #define DDRDATA_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_DEF           (0x00000000)
+  #define DDRDATA_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_OFF      (27)
+  #define DDRDATA_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_WID      ( 5)
+  #define DDRDATA_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MSK      (0xF8000000)
+  #define DDRDATA_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MAX      (0x0000001F)
+  #define DDRDATA_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_DEF      (0x00000000)
+
+#define DDRDATA_CR_DDRCRDATACONTROL1_REG                             (0x00003660)
+  #define DDRDATA_CR_DDRCRDATACONTROL1_RefPi_OFF                       ( 0)
+  #define DDRDATA_CR_DDRCRDATACONTROL1_RefPi_WID                       ( 4)
+  #define DDRDATA_CR_DDRCRDATACONTROL1_RefPi_MSK                       (0x0000000F)
+  #define DDRDATA_CR_DDRCRDATACONTROL1_RefPi_MAX                       (0x0000000F)
+  #define DDRDATA_CR_DDRCRDATACONTROL1_RefPi_DEF                       (0x00000000)
+  #define DDRDATA_CR_DDRCRDATACONTROL1_DllMask_OFF                     ( 4)
+  #define DDRDATA_CR_DDRCRDATACONTROL1_DllMask_WID                     ( 2)
+  #define DDRDATA_CR_DDRCRDATACONTROL1_DllMask_MSK                     (0x00000030)
+  #define DDRDATA_CR_DDRCRDATACONTROL1_DllMask_MAX                     (0x00000003)
+  #define DDRDATA_CR_DDRCRDATACONTROL1_DllMask_DEF                     (0x00000000)
+  #define DDRDATA_CR_DDRCRDATACONTROL1_DllWeakLock_OFF                 ( 6)
+  #define DDRDATA_CR_DDRCRDATACONTROL1_DllWeakLock_WID                 ( 1)
+  #define DDRDATA_CR_DDRCRDATACONTROL1_DllWeakLock_MSK                 (0x00000040)
+  #define DDRDATA_CR_DDRCRDATACONTROL1_DllWeakLock_MAX                 (0x00000001)
+  #define DDRDATA_CR_DDRCRDATACONTROL1_DllWeakLock_DEF                 (0x00000000)
+  #define DDRDATA_CR_DDRCRDATACONTROL1_SdllSegmentDisable_OFF          ( 7)
+  #define DDRDATA_CR_DDRCRDATACONTROL1_SdllSegmentDisable_WID          ( 3)
+  #define DDRDATA_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MSK          (0x00000380)
+  #define DDRDATA_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MAX          (0x00000007)
+  #define DDRDATA_CR_DDRCRDATACONTROL1_SdllSegmentDisable_DEF          (0x00000000)
+  #define DDRDATA_CR_DDRCRDATACONTROL1_RxBiasCtl_OFF                   (10)
+  #define DDRDATA_CR_DDRCRDATACONTROL1_RxBiasCtl_WID                   ( 3)
+  #define DDRDATA_CR_DDRCRDATACONTROL1_RxBiasCtl_MSK                   (0x00001C00)
+  #define DDRDATA_CR_DDRCRDATACONTROL1_RxBiasCtl_MAX                   (0x00000007)
+  #define DDRDATA_CR_DDRCRDATACONTROL1_RxBiasCtl_DEF                   (0x00000000)
+  #define DDRDATA_CR_DDRCRDATACONTROL1_OdtDelay_OFF                    (13)
+  #define DDRDATA_CR_DDRCRDATACONTROL1_OdtDelay_WID                    ( 4)
+  #define DDRDATA_CR_DDRCRDATACONTROL1_OdtDelay_MSK                    (0x0001E000)
+  #define DDRDATA_CR_DDRCRDATACONTROL1_OdtDelay_MAX                    (0x0000000F)
+  #define DDRDATA_CR_DDRCRDATACONTROL1_OdtDelay_DEF                    (0x00000000)
+  #define DDRDATA_CR_DDRCRDATACONTROL1_OdtDuration_OFF                 (17)
+  #define DDRDATA_CR_DDRCRDATACONTROL1_OdtDuration_WID                 ( 3)
+  #define DDRDATA_CR_DDRCRDATACONTROL1_OdtDuration_MSK                 (0x000E0000)
+  #define DDRDATA_CR_DDRCRDATACONTROL1_OdtDuration_MAX                 (0x00000007)
+  #define DDRDATA_CR_DDRCRDATACONTROL1_OdtDuration_DEF                 (0x00000000)
+  #define DDRDATA_CR_DDRCRDATACONTROL1_SenseAmpDelay_OFF               (20)
+  #define DDRDATA_CR_DDRCRDATACONTROL1_SenseAmpDelay_WID               ( 4)
+  #define DDRDATA_CR_DDRCRDATACONTROL1_SenseAmpDelay_MSK               (0x00F00000)
+  #define DDRDATA_CR_DDRCRDATACONTROL1_SenseAmpDelay_MAX               (0x0000000F)
+  #define DDRDATA_CR_DDRCRDATACONTROL1_SenseAmpDelay_DEF               (0x00000000)
+  #define DDRDATA_CR_DDRCRDATACONTROL1_SenseAmpDuration_OFF            (24)
+  #define DDRDATA_CR_DDRCRDATACONTROL1_SenseAmpDuration_WID            ( 3)
+  #define DDRDATA_CR_DDRCRDATACONTROL1_SenseAmpDuration_MSK            (0x07000000)
+  #define DDRDATA_CR_DDRCRDATACONTROL1_SenseAmpDuration_MAX            (0x00000007)
+  #define DDRDATA_CR_DDRCRDATACONTROL1_SenseAmpDuration_DEF            (0x00000000)
+  #define DDRDATA_CR_DDRCRDATACONTROL1_BurstEndODTDelay_OFF            (27)
+  #define DDRDATA_CR_DDRCRDATACONTROL1_BurstEndODTDelay_WID            ( 3)
+  #define DDRDATA_CR_DDRCRDATACONTROL1_BurstEndODTDelay_MSK            (0x38000000)
+  #define DDRDATA_CR_DDRCRDATACONTROL1_BurstEndODTDelay_MAX            (0x00000007)
+  #define DDRDATA_CR_DDRCRDATACONTROL1_BurstEndODTDelay_DEF            (0x00000000)
+  #define DDRDATA_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_OFF              (30)
+  #define DDRDATA_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_WID              ( 1)
+  #define DDRDATA_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_MSK              (0x40000000)
+  #define DDRDATA_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_MAX              (0x00000001)
+  #define DDRDATA_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_DEF              (0x00000000)
+  #define DDRDATA_CR_DDRCRDATACONTROL1_Rsvd1_OFF                       (31)
+  #define DDRDATA_CR_DDRCRDATACONTROL1_Rsvd1_WID                       ( 1)
+  #define DDRDATA_CR_DDRCRDATACONTROL1_Rsvd1_MSK                       (0x80000000)
+  #define DDRDATA_CR_DDRCRDATACONTROL1_Rsvd1_MAX                       (0x00000001)
+  #define DDRDATA_CR_DDRCRDATACONTROL1_Rsvd1_DEF                       (0x00000000)
+
+#define DDRDATA_CR_DDRCRDATACONTROL2_REG                             (0x00003664)
+  #define DDRDATA_CR_DDRCRDATACONTROL2_RxStaggerCtl_OFF                ( 0)
+  #define DDRDATA_CR_DDRCRDATACONTROL2_RxStaggerCtl_WID                ( 5)
+  #define DDRDATA_CR_DDRCRDATACONTROL2_RxStaggerCtl_MSK                (0x0000001F)
+  #define DDRDATA_CR_DDRCRDATACONTROL2_RxStaggerCtl_MAX                (0x0000001F)
+  #define DDRDATA_CR_DDRCRDATACONTROL2_RxStaggerCtl_DEF                (0x00000000)
+  #define DDRDATA_CR_DDRCRDATACONTROL2_ForceBiasOn_OFF                 ( 5)
+  #define DDRDATA_CR_DDRCRDATACONTROL2_ForceBiasOn_WID                 ( 1)
+  #define DDRDATA_CR_DDRCRDATACONTROL2_ForceBiasOn_MSK                 (0x00000020)
+  #define DDRDATA_CR_DDRCRDATACONTROL2_ForceBiasOn_MAX                 (0x00000001)
+  #define DDRDATA_CR_DDRCRDATACONTROL2_ForceBiasOn_DEF                 (0x00000000)
+  #define DDRDATA_CR_DDRCRDATACONTROL2_ForceRxOn_OFF                   ( 6)
+  #define DDRDATA_CR_DDRCRDATACONTROL2_ForceRxOn_WID                   ( 1)
+  #define DDRDATA_CR_DDRCRDATACONTROL2_ForceRxOn_MSK                   (0x00000040)
+  #define DDRDATA_CR_DDRCRDATACONTROL2_ForceRxOn_MAX                   (0x00000001)
+  #define DDRDATA_CR_DDRCRDATACONTROL2_ForceRxOn_DEF                   (0x00000000)
+  #define DDRDATA_CR_DDRCRDATACONTROL2_LeakerComp_OFF                  ( 7)
+  #define DDRDATA_CR_DDRCRDATACONTROL2_LeakerComp_WID                  ( 2)
+  #define DDRDATA_CR_DDRCRDATACONTROL2_LeakerComp_MSK                  (0x00000180)
+  #define DDRDATA_CR_DDRCRDATACONTROL2_LeakerComp_MAX                  (0x00000003)
+  #define DDRDATA_CR_DDRCRDATACONTROL2_LeakerComp_DEF                  (0x00000000)
+  #define DDRDATA_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_OFF              ( 9)
+  #define DDRDATA_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_WID              ( 4)
+  #define DDRDATA_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_MSK              (0x00001E00)
+  #define DDRDATA_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_MAX              (0x0000000F)
+  #define DDRDATA_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_DEF              (0x00000008)
+  #define DDRDATA_CR_DDRCRDATACONTROL2_RxClkStgNum_OFF                 (13)
+  #define DDRDATA_CR_DDRCRDATACONTROL2_RxClkStgNum_WID                 ( 5)
+  #define DDRDATA_CR_DDRCRDATACONTROL2_RxClkStgNum_MSK                 (0x0003E000)
+  #define DDRDATA_CR_DDRCRDATACONTROL2_RxClkStgNum_MAX                 (0x0000001F)
+  #define DDRDATA_CR_DDRCRDATACONTROL2_RxClkStgNum_DEF                 (0x00000011)
+  #define DDRDATA_CR_DDRCRDATACONTROL2_WlLongDelEn_OFF                 (18)
+  #define DDRDATA_CR_DDRCRDATACONTROL2_WlLongDelEn_WID                 ( 1)
+  #define DDRDATA_CR_DDRCRDATACONTROL2_WlLongDelEn_MSK                 (0x00040000)
+  #define DDRDATA_CR_DDRCRDATACONTROL2_WlLongDelEn_MAX                 (0x00000001)
+  #define DDRDATA_CR_DDRCRDATACONTROL2_WlLongDelEn_DEF                 (0x00000000)
+  #define DDRDATA_CR_DDRCRDATACONTROL2_Spare_OFF                       (19)
+  #define DDRDATA_CR_DDRCRDATACONTROL2_Spare_WID                       (13)
+  #define DDRDATA_CR_DDRCRDATACONTROL2_Spare_MSK                       (0xFFF80000)
+  #define DDRDATA_CR_DDRCRDATACONTROL2_Spare_MAX                       (0x00001FFF)
+  #define DDRDATA_CR_DDRCRDATACONTROL2_Spare_DEF                       (0x00000000)
+
+#define DDRDATA_CR_DDRCRVREFCONTROL_REG                              (0x00003668)
+  #define DDRDATA_CR_DDRCRVREFCONTROL_VrefCtl_OFF                      ( 0)
+  #define DDRDATA_CR_DDRCRVREFCONTROL_VrefCtl_WID                      (24)
+  #define DDRDATA_CR_DDRCRVREFCONTROL_VrefCtl_MSK                      (0x00FFFFFF)
+  #define DDRDATA_CR_DDRCRVREFCONTROL_VrefCtl_MAX                      (0x00FFFFFF)
+  #define DDRDATA_CR_DDRCRVREFCONTROL_VrefCtl_DEF                      (0x000E453A)
+  #define DDRDATA_CR_DDRCRVREFCONTROL_OutputCode_OFF                   (24)
+  #define DDRDATA_CR_DDRCRVREFCONTROL_OutputCode_WID                   ( 8)
+  #define DDRDATA_CR_DDRCRVREFCONTROL_OutputCode_MSK                   (0xFF000000)
+  #define DDRDATA_CR_DDRCRVREFCONTROL_OutputCode_MAX                   (0x000000FF)
+  #define DDRDATA_CR_DDRCRVREFCONTROL_OutputCode_DEF                   (0x00000000)
+
+#define DDRDATA_CR_DDRCRVSSHICONTROL_REG                             (0x0000366C)
+  #define DDRDATA_CR_DDRCRVSSHICONTROL_VssHiCtl_OFF                    ( 0)
+  #define DDRDATA_CR_DDRCRVSSHICONTROL_VssHiCtl_WID                    (24)
+  #define DDRDATA_CR_DDRCRVSSHICONTROL_VssHiCtl_MSK                    (0x00FFFFFF)
+  #define DDRDATA_CR_DDRCRVSSHICONTROL_VssHiCtl_MAX                    (0x00FFFFFF)
+  #define DDRDATA_CR_DDRCRVSSHICONTROL_VssHiCtl_DEF                    (0x004D8238)
+  #define DDRDATA_CR_DDRCRVSSHICONTROL_OutputCode_OFF                  (24)
+  #define DDRDATA_CR_DDRCRVSSHICONTROL_OutputCode_WID                  ( 8)
+  #define DDRDATA_CR_DDRCRVSSHICONTROL_OutputCode_MSK                  (0xFF000000)
+  #define DDRDATA_CR_DDRCRVSSHICONTROL_OutputCode_MAX                  (0x000000FF)
+  #define DDRDATA_CR_DDRCRVSSHICONTROL_OutputCode_DEF                  (0x00000000)
+
+#define DDRDATA_CR_DDRCRVSSHIORVREFCONTROL_REG                       (0x0000366C)
+  #define DDRDATA_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_OFF        ( 0)
+  #define DDRDATA_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_WID        (24)
+  #define DDRDATA_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_MSK        (0x00FFFFFF)
+  #define DDRDATA_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_MAX        (0x00FFFFFF)
+  #define DDRDATA_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_DEF        (0x00000000)
+  #define DDRDATA_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_OFF            (24)
+  #define DDRDATA_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_WID            ( 8)
+  #define DDRDATA_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_MSK            (0xFF000000)
+  #define DDRDATA_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_MAX            (0x000000FF)
+  #define DDRDATA_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_DEF            (0x00000000)
+
+#define DDRDATA_CR_DDRCRDATAOFFSETTRAIN_REG                          (0x00003670)
+  #define DDRDATA_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_OFF              ( 0)
+  #define DDRDATA_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_WID              ( 6)
+  #define DDRDATA_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MSK              (0x0000003F)
+  #define DDRDATA_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MAX              (0x0000003F)
+  #define DDRDATA_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_DEF              (0x00000000)
+  #define DDRDATA_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_OFF              ( 6)
+  #define DDRDATA_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_WID              ( 6)
+  #define DDRDATA_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MSK              (0x00000FC0)
+  #define DDRDATA_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MAX              (0x0000003F)
+  #define DDRDATA_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_DEF              (0x00000000)
+  #define DDRDATA_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_OFF               (12)
+  #define DDRDATA_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_WID               ( 6)
+  #define DDRDATA_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MSK               (0x0003F000)
+  #define DDRDATA_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MAX               (0x0000003F)
+  #define DDRDATA_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_DEF               (0x00000000)
+  #define DDRDATA_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_OFF              (18)
+  #define DDRDATA_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_WID              ( 6)
+  #define DDRDATA_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MSK              (0x00FC0000)
+  #define DDRDATA_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MAX              (0x0000003F)
+  #define DDRDATA_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_DEF              (0x00000000)
+  #define DDRDATA_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_OFF               (24)
+  #define DDRDATA_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_WID               ( 7)
+  #define DDRDATA_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MSK               (0x7F000000)
+  #define DDRDATA_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MAX               (0x0000007F)
+  #define DDRDATA_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_DEF               (0x00000000)
+  #define DDRDATA_CR_DDRCRDATAOFFSETTRAIN_Spare_OFF                    (31)
+  #define DDRDATA_CR_DDRCRDATAOFFSETTRAIN_Spare_WID                    ( 1)
+  #define DDRDATA_CR_DDRCRDATAOFFSETTRAIN_Spare_MSK                    (0x80000000)
+  #define DDRDATA_CR_DDRCRDATAOFFSETTRAIN_Spare_MAX                    (0x00000001)
+  #define DDRDATA_CR_DDRCRDATAOFFSETTRAIN_Spare_DEF                    (0x00000000)
+
+#define DDRDATA_CR_DDRCRDATACONTROL0_REG                             (0x00003674)
+  #define DDRDATA_CR_DDRCRDATACONTROL0_RxTrainingMode_OFF              ( 0)
+  #define DDRDATA_CR_DDRCRDATACONTROL0_RxTrainingMode_WID              ( 1)
+  #define DDRDATA_CR_DDRCRDATACONTROL0_RxTrainingMode_MSK              (0x00000001)
+  #define DDRDATA_CR_DDRCRDATACONTROL0_RxTrainingMode_MAX              (0x00000001)
+  #define DDRDATA_CR_DDRCRDATACONTROL0_RxTrainingMode_DEF              (0x00000000)
+  #define DDRDATA_CR_DDRCRDATACONTROL0_WLTrainingMode_OFF              ( 1)
+  #define DDRDATA_CR_DDRCRDATACONTROL0_WLTrainingMode_WID              ( 1)
+  #define DDRDATA_CR_DDRCRDATACONTROL0_WLTrainingMode_MSK              (0x00000002)
+  #define DDRDATA_CR_DDRCRDATACONTROL0_WLTrainingMode_MAX              (0x00000001)
+  #define DDRDATA_CR_DDRCRDATACONTROL0_WLTrainingMode_DEF              (0x00000000)
+  #define DDRDATA_CR_DDRCRDATACONTROL0_RLTrainingMode_OFF              ( 2)
+  #define DDRDATA_CR_DDRCRDATACONTROL0_RLTrainingMode_WID              ( 1)
+  #define DDRDATA_CR_DDRCRDATACONTROL0_RLTrainingMode_MSK              (0x00000004)
+  #define DDRDATA_CR_DDRCRDATACONTROL0_RLTrainingMode_MAX              (0x00000001)
+  #define DDRDATA_CR_DDRCRDATACONTROL0_RLTrainingMode_DEF              (0x00000000)
+  #define DDRDATA_CR_DDRCRDATACONTROL0_SenseampTrainingMode_OFF        ( 3)
+  #define DDRDATA_CR_DDRCRDATACONTROL0_SenseampTrainingMode_WID        ( 1)
+  #define DDRDATA_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MSK        (0x00000008)
+  #define DDRDATA_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MAX        (0x00000001)
+  #define DDRDATA_CR_DDRCRDATACONTROL0_SenseampTrainingMode_DEF        (0x00000000)
+  #define DDRDATA_CR_DDRCRDATACONTROL0_TxOn_OFF                        ( 4)
+  #define DDRDATA_CR_DDRCRDATACONTROL0_TxOn_WID                        ( 1)
+  #define DDRDATA_CR_DDRCRDATACONTROL0_TxOn_MSK                        (0x00000010)
+  #define DDRDATA_CR_DDRCRDATACONTROL0_TxOn_MAX                        (0x00000001)
+  #define DDRDATA_CR_DDRCRDATACONTROL0_TxOn_DEF                        (0x00000000)
+  #define DDRDATA_CR_DDRCRDATACONTROL0_RfOn_OFF                        ( 5)
+  #define DDRDATA_CR_DDRCRDATACONTROL0_RfOn_WID                        ( 1)
+  #define DDRDATA_CR_DDRCRDATACONTROL0_RfOn_MSK                        (0x00000020)
+  #define DDRDATA_CR_DDRCRDATACONTROL0_RfOn_MAX                        (0x00000001)
+  #define DDRDATA_CR_DDRCRDATACONTROL0_RfOn_DEF                        (0x00000000)
+  #define DDRDATA_CR_DDRCRDATACONTROL0_RxPiOn_OFF                      ( 6)
+  #define DDRDATA_CR_DDRCRDATACONTROL0_RxPiOn_WID                      ( 1)
+  #define DDRDATA_CR_DDRCRDATACONTROL0_RxPiOn_MSK                      (0x00000040)
+  #define DDRDATA_CR_DDRCRDATACONTROL0_RxPiOn_MAX                      (0x00000001)
+  #define DDRDATA_CR_DDRCRDATACONTROL0_RxPiOn_DEF                      (0x00000000)
+  #define DDRDATA_CR_DDRCRDATACONTROL0_TxPiOn_OFF                      ( 7)
+  #define DDRDATA_CR_DDRCRDATACONTROL0_TxPiOn_WID                      ( 1)
+  #define DDRDATA_CR_DDRCRDATACONTROL0_TxPiOn_MSK                      (0x00000080)
+  #define DDRDATA_CR_DDRCRDATACONTROL0_TxPiOn_MAX                      (0x00000001)
+  #define DDRDATA_CR_DDRCRDATACONTROL0_TxPiOn_DEF                      (0x00000000)
+  #define DDRDATA_CR_DDRCRDATACONTROL0_InternalClocksOn_OFF            ( 8)
+  #define DDRDATA_CR_DDRCRDATACONTROL0_InternalClocksOn_WID            ( 1)
+  #define DDRDATA_CR_DDRCRDATACONTROL0_InternalClocksOn_MSK            (0x00000100)
+  #define DDRDATA_CR_DDRCRDATACONTROL0_InternalClocksOn_MAX            (0x00000001)
+  #define DDRDATA_CR_DDRCRDATACONTROL0_InternalClocksOn_DEF            (0x00000000)
+  #define DDRDATA_CR_DDRCRDATACONTROL0_RepeaterClocksOn_OFF            ( 9)
+  #define DDRDATA_CR_DDRCRDATACONTROL0_RepeaterClocksOn_WID            ( 1)
+  #define DDRDATA_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MSK            (0x00000200)
+  #define DDRDATA_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MAX            (0x00000001)
+  #define DDRDATA_CR_DDRCRDATACONTROL0_RepeaterClocksOn_DEF            (0x00000000)
+  #define DDRDATA_CR_DDRCRDATACONTROL0_TxDisable_OFF                   (10)
+  #define DDRDATA_CR_DDRCRDATACONTROL0_TxDisable_WID                   ( 1)
+  #define DDRDATA_CR_DDRCRDATACONTROL0_TxDisable_MSK                   (0x00000400)
+  #define DDRDATA_CR_DDRCRDATACONTROL0_TxDisable_MAX                   (0x00000001)
+  #define DDRDATA_CR_DDRCRDATACONTROL0_TxDisable_DEF                   (0x00000000)
+  #define DDRDATA_CR_DDRCRDATACONTROL0_RxDisable_OFF                   (11)
+  #define DDRDATA_CR_DDRCRDATACONTROL0_RxDisable_WID                   ( 1)
+  #define DDRDATA_CR_DDRCRDATACONTROL0_RxDisable_MSK                   (0x00000800)
+  #define DDRDATA_CR_DDRCRDATACONTROL0_RxDisable_MAX                   (0x00000001)
+  #define DDRDATA_CR_DDRCRDATACONTROL0_RxDisable_DEF                   (0x00000000)
+  #define DDRDATA_CR_DDRCRDATACONTROL0_TxLong_OFF                      (12)
+  #define DDRDATA_CR_DDRCRDATACONTROL0_TxLong_WID                      ( 1)
+  #define DDRDATA_CR_DDRCRDATACONTROL0_TxLong_MSK                      (0x00001000)
+  #define DDRDATA_CR_DDRCRDATACONTROL0_TxLong_MAX                      (0x00000001)
+  #define DDRDATA_CR_DDRCRDATACONTROL0_TxLong_DEF                      (0x00000000)
+  #define DDRDATA_CR_DDRCRDATACONTROL0_RxDqsCtle_OFF                   (13)
+  #define DDRDATA_CR_DDRCRDATACONTROL0_RxDqsCtle_WID                   ( 2)
+  #define DDRDATA_CR_DDRCRDATACONTROL0_RxDqsCtle_MSK                   (0x00006000)
+  #define DDRDATA_CR_DDRCRDATACONTROL0_RxDqsCtle_MAX                   (0x00000003)
+  #define DDRDATA_CR_DDRCRDATACONTROL0_RxDqsCtle_DEF                   (0x00000000)
+  #define DDRDATA_CR_DDRCRDATACONTROL0_RxReadPointer_OFF               (15)
+  #define DDRDATA_CR_DDRCRDATACONTROL0_RxReadPointer_WID               ( 3)
+  #define DDRDATA_CR_DDRCRDATACONTROL0_RxReadPointer_MSK               (0x00038000)
+  #define DDRDATA_CR_DDRCRDATACONTROL0_RxReadPointer_MAX               (0x00000007)
+  #define DDRDATA_CR_DDRCRDATACONTROL0_RxReadPointer_DEF               (0x00000000)
+  #define DDRDATA_CR_DDRCRDATACONTROL0_DriverSegmentEnable_OFF         (18)
+  #define DDRDATA_CR_DDRCRDATACONTROL0_DriverSegmentEnable_WID         ( 1)
+  #define DDRDATA_CR_DDRCRDATACONTROL0_DriverSegmentEnable_MSK         (0x00040000)
+  #define DDRDATA_CR_DDRCRDATACONTROL0_DriverSegmentEnable_MAX         (0x00000001)
+  #define DDRDATA_CR_DDRCRDATACONTROL0_DriverSegmentEnable_DEF         (0x00000000)
+  #define DDRDATA_CR_DDRCRDATACONTROL0_DataVccddqHi_OFF                (19)
+  #define DDRDATA_CR_DDRCRDATACONTROL0_DataVccddqHi_WID                ( 1)
+  #define DDRDATA_CR_DDRCRDATACONTROL0_DataVccddqHi_MSK                (0x00080000)
+  #define DDRDATA_CR_DDRCRDATACONTROL0_DataVccddqHi_MAX                (0x00000001)
+  #define DDRDATA_CR_DDRCRDATACONTROL0_DataVccddqHi_DEF                (0x00000000)
+  #define DDRDATA_CR_DDRCRDATACONTROL0_ReadRFRd_OFF                    (20)
+  #define DDRDATA_CR_DDRCRDATACONTROL0_ReadRFRd_WID                    ( 1)
+  #define DDRDATA_CR_DDRCRDATACONTROL0_ReadRFRd_MSK                    (0x00100000)
+  #define DDRDATA_CR_DDRCRDATACONTROL0_ReadRFRd_MAX                    (0x00000001)
+  #define DDRDATA_CR_DDRCRDATACONTROL0_ReadRFRd_DEF                    (0x00000000)
+  #define DDRDATA_CR_DDRCRDATACONTROL0_ReadRFWr_OFF                    (21)
+  #define DDRDATA_CR_DDRCRDATACONTROL0_ReadRFWr_WID                    ( 1)
+  #define DDRDATA_CR_DDRCRDATACONTROL0_ReadRFWr_MSK                    (0x00200000)
+  #define DDRDATA_CR_DDRCRDATACONTROL0_ReadRFWr_MAX                    (0x00000001)
+  #define DDRDATA_CR_DDRCRDATACONTROL0_ReadRFWr_DEF                    (0x00000000)
+  #define DDRDATA_CR_DDRCRDATACONTROL0_ReadRFRank_OFF                  (22)
+  #define DDRDATA_CR_DDRCRDATACONTROL0_ReadRFRank_WID                  ( 2)
+  #define DDRDATA_CR_DDRCRDATACONTROL0_ReadRFRank_MSK                  (0x00C00000)
+  #define DDRDATA_CR_DDRCRDATACONTROL0_ReadRFRank_MAX                  (0x00000003)
+  #define DDRDATA_CR_DDRCRDATACONTROL0_ReadRFRank_DEF                  (0x00000000)
+  #define DDRDATA_CR_DDRCRDATACONTROL0_ForceOdtOn_OFF                  (24)
+  #define DDRDATA_CR_DDRCRDATACONTROL0_ForceOdtOn_WID                  ( 1)
+  #define DDRDATA_CR_DDRCRDATACONTROL0_ForceOdtOn_MSK                  (0x01000000)
+  #define DDRDATA_CR_DDRCRDATACONTROL0_ForceOdtOn_MAX                  (0x00000001)
+  #define DDRDATA_CR_DDRCRDATACONTROL0_ForceOdtOn_DEF                  (0x00000000)
+  #define DDRDATA_CR_DDRCRDATACONTROL0_OdtSampOff_OFF                  (25)
+  #define DDRDATA_CR_DDRCRDATACONTROL0_OdtSampOff_WID                  ( 1)
+  #define DDRDATA_CR_DDRCRDATACONTROL0_OdtSampOff_MSK                  (0x02000000)
+  #define DDRDATA_CR_DDRCRDATACONTROL0_OdtSampOff_MAX                  (0x00000001)
+  #define DDRDATA_CR_DDRCRDATACONTROL0_OdtSampOff_DEF                  (0x00000000)
+  #define DDRDATA_CR_DDRCRDATACONTROL0_DisableOdtStatic_OFF            (26)
+  #define DDRDATA_CR_DDRCRDATACONTROL0_DisableOdtStatic_WID            ( 1)
+  #define DDRDATA_CR_DDRCRDATACONTROL0_DisableOdtStatic_MSK            (0x04000000)
+  #define DDRDATA_CR_DDRCRDATACONTROL0_DisableOdtStatic_MAX            (0x00000001)
+  #define DDRDATA_CR_DDRCRDATACONTROL0_DisableOdtStatic_DEF            (0x00000000)
+  #define DDRDATA_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_OFF             (27)
+  #define DDRDATA_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_WID             ( 1)
+  #define DDRDATA_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MSK             (0x08000000)
+  #define DDRDATA_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MAX             (0x00000001)
+  #define DDRDATA_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_DEF             (0x00000000)
+  #define DDRDATA_CR_DDRCRDATACONTROL0_LPDDR_Mode_OFF                  (28)
+  #define DDRDATA_CR_DDRCRDATACONTROL0_LPDDR_Mode_WID                  ( 1)
+  #define DDRDATA_CR_DDRCRDATACONTROL0_LPDDR_Mode_MSK                  (0x10000000)
+  #define DDRDATA_CR_DDRCRDATACONTROL0_LPDDR_Mode_MAX                  (0x00000001)
+  #define DDRDATA_CR_DDRCRDATACONTROL0_LPDDR_Mode_DEF                  (0x00000000)
+  #define DDRDATA_CR_DDRCRDATACONTROL0_EnReadPreamble_OFF              (29)
+  #define DDRDATA_CR_DDRCRDATACONTROL0_EnReadPreamble_WID              ( 1)
+  #define DDRDATA_CR_DDRCRDATACONTROL0_EnReadPreamble_MSK              (0x20000000)
+  #define DDRDATA_CR_DDRCRDATACONTROL0_EnReadPreamble_MAX              (0x00000001)
+  #define DDRDATA_CR_DDRCRDATACONTROL0_EnReadPreamble_DEF              (0x00000000)
+  #define DDRDATA_CR_DDRCRDATACONTROL0_OdtSampExtendEn_OFF             (30)
+  #define DDRDATA_CR_DDRCRDATACONTROL0_OdtSampExtendEn_WID             ( 1)
+  #define DDRDATA_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MSK             (0x40000000)
+  #define DDRDATA_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MAX             (0x00000001)
+  #define DDRDATA_CR_DDRCRDATACONTROL0_OdtSampExtendEn_DEF             (0x00000000)
+  #define DDRDATA_CR_DDRCRDATACONTROL0_EarlyRleakEn_OFF                (31)
+  #define DDRDATA_CR_DDRCRDATACONTROL0_EarlyRleakEn_WID                ( 1)
+  #define DDRDATA_CR_DDRCRDATACONTROL0_EarlyRleakEn_MSK                (0x80000000)
+  #define DDRDATA_CR_DDRCRDATACONTROL0_EarlyRleakEn_MAX                (0x00000001)
+  #define DDRDATA_CR_DDRCRDATACONTROL0_EarlyRleakEn_DEF                (0x00000000)
+
+#define DDRDATA_CR_DDRCRVREFADJUST1_REG                              (0x00003678)
+  #define DDRDATA_CR_DDRCRVREFADJUST1_CAVrefCtl_OFF                    ( 0)
+  #define DDRDATA_CR_DDRCRVREFADJUST1_CAVrefCtl_WID                    ( 7)
+  #define DDRDATA_CR_DDRCRVREFADJUST1_CAVrefCtl_MSK                    (0x0000007F)
+  #define DDRDATA_CR_DDRCRVREFADJUST1_CAVrefCtl_MAX                    (0x0000007F)
+  #define DDRDATA_CR_DDRCRVREFADJUST1_CAVrefCtl_DEF                    (0x00000000)
+  #define DDRDATA_CR_DDRCRVREFADJUST1_Ch1VrefCtl_OFF                   ( 7)
+  #define DDRDATA_CR_DDRCRVREFADJUST1_Ch1VrefCtl_WID                   ( 7)
+  #define DDRDATA_CR_DDRCRVREFADJUST1_Ch1VrefCtl_MSK                   (0x00003F80)
+  #define DDRDATA_CR_DDRCRVREFADJUST1_Ch1VrefCtl_MAX                   (0x0000007F)
+  #define DDRDATA_CR_DDRCRVREFADJUST1_Ch1VrefCtl_DEF                   (0x00000000)
+  #define DDRDATA_CR_DDRCRVREFADJUST1_Ch0VrefCtl_OFF                   (14)
+  #define DDRDATA_CR_DDRCRVREFADJUST1_Ch0VrefCtl_WID                   ( 7)
+  #define DDRDATA_CR_DDRCRVREFADJUST1_Ch0VrefCtl_MSK                   (0x001FC000)
+  #define DDRDATA_CR_DDRCRVREFADJUST1_Ch0VrefCtl_MAX                   (0x0000007F)
+  #define DDRDATA_CR_DDRCRVREFADJUST1_Ch0VrefCtl_DEF                   (0x00000000)
+  #define DDRDATA_CR_DDRCRVREFADJUST1_EnDimmVrefCA_OFF                 (21)
+  #define DDRDATA_CR_DDRCRVREFADJUST1_EnDimmVrefCA_WID                 ( 1)
+  #define DDRDATA_CR_DDRCRVREFADJUST1_EnDimmVrefCA_MSK                 (0x00200000)
+  #define DDRDATA_CR_DDRCRVREFADJUST1_EnDimmVrefCA_MAX                 (0x00000001)
+  #define DDRDATA_CR_DDRCRVREFADJUST1_EnDimmVrefCA_DEF                 (0x00000000)
+  #define DDRDATA_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_OFF                (22)
+  #define DDRDATA_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_WID                ( 1)
+  #define DDRDATA_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_MSK                (0x00400000)
+  #define DDRDATA_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_MAX                (0x00000001)
+  #define DDRDATA_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_DEF                (0x00000000)
+  #define DDRDATA_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_OFF                (23)
+  #define DDRDATA_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_WID                ( 1)
+  #define DDRDATA_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_MSK                (0x00800000)
+  #define DDRDATA_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_MAX                (0x00000001)
+  #define DDRDATA_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_DEF                (0x00000000)
+  #define DDRDATA_CR_DDRCRVREFADJUST1_HiZTimerCtrl_OFF                 (24)
+  #define DDRDATA_CR_DDRCRVREFADJUST1_HiZTimerCtrl_WID                 ( 2)
+  #define DDRDATA_CR_DDRCRVREFADJUST1_HiZTimerCtrl_MSK                 (0x03000000)
+  #define DDRDATA_CR_DDRCRVREFADJUST1_HiZTimerCtrl_MAX                 (0x00000003)
+  #define DDRDATA_CR_DDRCRVREFADJUST1_HiZTimerCtrl_DEF                 (0x00000000)
+  #define DDRDATA_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_OFF                (26)
+  #define DDRDATA_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_WID                ( 1)
+  #define DDRDATA_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_MSK                (0x04000000)
+  #define DDRDATA_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_MAX                (0x00000001)
+  #define DDRDATA_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_DEF                (0x00000000)
+  #define DDRDATA_CR_DDRCRVREFADJUST1_Rsvd_OFF                         (27)
+  #define DDRDATA_CR_DDRCRVREFADJUST1_Rsvd_WID                         ( 2)
+  #define DDRDATA_CR_DDRCRVREFADJUST1_Rsvd_MSK                         (0x18000000)
+  #define DDRDATA_CR_DDRCRVREFADJUST1_Rsvd_MAX                         (0x00000003)
+  #define DDRDATA_CR_DDRCRVREFADJUST1_Rsvd_DEF                         (0x00000000)
+  #define DDRDATA_CR_DDRCRVREFADJUST1_caSlowBW_OFF                     (29)
+  #define DDRDATA_CR_DDRCRVREFADJUST1_caSlowBW_WID                     ( 1)
+  #define DDRDATA_CR_DDRCRVREFADJUST1_caSlowBW_MSK                     (0x20000000)
+  #define DDRDATA_CR_DDRCRVREFADJUST1_caSlowBW_MAX                     (0x00000001)
+  #define DDRDATA_CR_DDRCRVREFADJUST1_caSlowBW_DEF                     (0x00000000)
+  #define DDRDATA_CR_DDRCRVREFADJUST1_ch0SlowBW_OFF                    (30)
+  #define DDRDATA_CR_DDRCRVREFADJUST1_ch0SlowBW_WID                    ( 1)
+  #define DDRDATA_CR_DDRCRVREFADJUST1_ch0SlowBW_MSK                    (0x40000000)
+  #define DDRDATA_CR_DDRCRVREFADJUST1_ch0SlowBW_MAX                    (0x00000001)
+  #define DDRDATA_CR_DDRCRVREFADJUST1_ch0SlowBW_DEF                    (0x00000000)
+  #define DDRDATA_CR_DDRCRVREFADJUST1_ch1SlowBW_OFF                    (31)
+  #define DDRDATA_CR_DDRCRVREFADJUST1_ch1SlowBW_WID                    ( 1)
+  #define DDRDATA_CR_DDRCRVREFADJUST1_ch1SlowBW_MSK                    (0x80000000)
+  #define DDRDATA_CR_DDRCRVREFADJUST1_ch1SlowBW_MAX                    (0x00000001)
+  #define DDRDATA_CR_DDRCRVREFADJUST1_ch1SlowBW_DEF                    (0x00000000)
+
+#define DDRDATACH0_CR_RXTRAINRANK0_REG                               (0x00003000)
+  #define DDRDATACH0_CR_RXTRAINRANK0_RxRcvEnPi_OFF                     ( 0)
+  #define DDRDATACH0_CR_RXTRAINRANK0_RxRcvEnPi_WID                     ( 9)
+  #define DDRDATACH0_CR_RXTRAINRANK0_RxRcvEnPi_MSK                     (0x000001FF)
+  #define DDRDATACH0_CR_RXTRAINRANK0_RxRcvEnPi_MAX                     (0x000001FF)
+  #define DDRDATACH0_CR_RXTRAINRANK0_RxDqsPPi_OFF                      ( 9)
+  #define DDRDATACH0_CR_RXTRAINRANK0_RxDqsPPi_WID                      ( 6)
+  #define DDRDATACH0_CR_RXTRAINRANK0_RxDqsPPi_MSK                      (0x00007E00)
+  #define DDRDATACH0_CR_RXTRAINRANK0_RxDqsPPi_MAX                      (0x0000003F)
+  #define DDRDATACH0_CR_RXTRAINRANK0_RxEq_OFF                          (15)
+  #define DDRDATACH0_CR_RXTRAINRANK0_RxEq_WID                          ( 5)
+  #define DDRDATACH0_CR_RXTRAINRANK0_RxEq_MSK                          (0x000F8000)
+  #define DDRDATACH0_CR_RXTRAINRANK0_RxEq_MAX                          (0x0000001F)
+  #define DDRDATACH0_CR_RXTRAINRANK0_RxDqsNPi_OFF                      (20)
+  #define DDRDATACH0_CR_RXTRAINRANK0_RxDqsNPi_WID                      ( 6)
+  #define DDRDATACH0_CR_RXTRAINRANK0_RxDqsNPi_MSK                      (0x03F00000)
+  #define DDRDATACH0_CR_RXTRAINRANK0_RxDqsNPi_MAX                      (0x0000003F)
+  #define DDRDATACH0_CR_RXTRAINRANK0_RxVref_OFF                        (26)
+  #define DDRDATACH0_CR_RXTRAINRANK0_RxVref_WID                        ( 6)
+  #define DDRDATACH0_CR_RXTRAINRANK0_RxVref_MSK                        (0xFC000000)
+  #define DDRDATACH0_CR_RXTRAINRANK0_RxVref_MAX                        (0x0000003F)
+
+#define DDRDATACH0_CR_RXTRAINRANK1_REG                               (0x00003004)
+  #define DDRDATACH0_CR_RXTRAINRANK1_RxRcvEnPi_OFF                     ( 0)
+  #define DDRDATACH0_CR_RXTRAINRANK1_RxRcvEnPi_WID                     ( 9)
+  #define DDRDATACH0_CR_RXTRAINRANK1_RxRcvEnPi_MSK                     (0x000001FF)
+  #define DDRDATACH0_CR_RXTRAINRANK1_RxRcvEnPi_MAX                     (0x000001FF)
+  #define DDRDATACH0_CR_RXTRAINRANK1_RxDqsPPi_OFF                      ( 9)
+  #define DDRDATACH0_CR_RXTRAINRANK1_RxDqsPPi_WID                      ( 6)
+  #define DDRDATACH0_CR_RXTRAINRANK1_RxDqsPPi_MSK                      (0x00007E00)
+  #define DDRDATACH0_CR_RXTRAINRANK1_RxDqsPPi_MAX                      (0x0000003F)
+  #define DDRDATACH0_CR_RXTRAINRANK1_RxEq_OFF                          (15)
+  #define DDRDATACH0_CR_RXTRAINRANK1_RxEq_WID                          ( 5)
+  #define DDRDATACH0_CR_RXTRAINRANK1_RxEq_MSK                          (0x000F8000)
+  #define DDRDATACH0_CR_RXTRAINRANK1_RxEq_MAX                          (0x0000001F)
+  #define DDRDATACH0_CR_RXTRAINRANK1_RxDqsNPi_OFF                      (20)
+  #define DDRDATACH0_CR_RXTRAINRANK1_RxDqsNPi_WID                      ( 6)
+  #define DDRDATACH0_CR_RXTRAINRANK1_RxDqsNPi_MSK                      (0x03F00000)
+  #define DDRDATACH0_CR_RXTRAINRANK1_RxDqsNPi_MAX                      (0x0000003F)
+  #define DDRDATACH0_CR_RXTRAINRANK1_RxVref_OFF                        (26)
+  #define DDRDATACH0_CR_RXTRAINRANK1_RxVref_WID                        ( 6)
+  #define DDRDATACH0_CR_RXTRAINRANK1_RxVref_MSK                        (0xFC000000)
+  #define DDRDATACH0_CR_RXTRAINRANK1_RxVref_MAX                        (0x0000003F)
+
+#define DDRDATACH0_CR_RXTRAINRANK2_REG                               (0x00003008)
+  #define DDRDATACH0_CR_RXTRAINRANK2_RxRcvEnPi_OFF                     ( 0)
+  #define DDRDATACH0_CR_RXTRAINRANK2_RxRcvEnPi_WID                     ( 9)
+  #define DDRDATACH0_CR_RXTRAINRANK2_RxRcvEnPi_MSK                     (0x000001FF)
+  #define DDRDATACH0_CR_RXTRAINRANK2_RxRcvEnPi_MAX                     (0x000001FF)
+  #define DDRDATACH0_CR_RXTRAINRANK2_RxDqsPPi_OFF                      ( 9)
+  #define DDRDATACH0_CR_RXTRAINRANK2_RxDqsPPi_WID                      ( 6)
+  #define DDRDATACH0_CR_RXTRAINRANK2_RxDqsPPi_MSK                      (0x00007E00)
+  #define DDRDATACH0_CR_RXTRAINRANK2_RxDqsPPi_MAX                      (0x0000003F)
+  #define DDRDATACH0_CR_RXTRAINRANK2_RxEq_OFF                          (15)
+  #define DDRDATACH0_CR_RXTRAINRANK2_RxEq_WID                          ( 5)
+  #define DDRDATACH0_CR_RXTRAINRANK2_RxEq_MSK                          (0x000F8000)
+  #define DDRDATACH0_CR_RXTRAINRANK2_RxEq_MAX                          (0x0000001F)
+  #define DDRDATACH0_CR_RXTRAINRANK2_RxDqsNPi_OFF                      (20)
+  #define DDRDATACH0_CR_RXTRAINRANK2_RxDqsNPi_WID                      ( 6)
+  #define DDRDATACH0_CR_RXTRAINRANK2_RxDqsNPi_MSK                      (0x03F00000)
+  #define DDRDATACH0_CR_RXTRAINRANK2_RxDqsNPi_MAX                      (0x0000003F)
+  #define DDRDATACH0_CR_RXTRAINRANK2_RxVref_OFF                        (26)
+  #define DDRDATACH0_CR_RXTRAINRANK2_RxVref_WID                        ( 6)
+  #define DDRDATACH0_CR_RXTRAINRANK2_RxVref_MSK                        (0xFC000000)
+  #define DDRDATACH0_CR_RXTRAINRANK2_RxVref_MAX                        (0x0000003F)
+
+#define DDRDATACH0_CR_RXTRAINRANK3_REG                               (0x0000300C)
+  #define DDRDATACH0_CR_RXTRAINRANK3_RxRcvEnPi_OFF                     ( 0)
+  #define DDRDATACH0_CR_RXTRAINRANK3_RxRcvEnPi_WID                     ( 9)
+  #define DDRDATACH0_CR_RXTRAINRANK3_RxRcvEnPi_MSK                     (0x000001FF)
+  #define DDRDATACH0_CR_RXTRAINRANK3_RxRcvEnPi_MAX                     (0x000001FF)
+  #define DDRDATACH0_CR_RXTRAINRANK3_RxDqsPPi_OFF                      ( 9)
+  #define DDRDATACH0_CR_RXTRAINRANK3_RxDqsPPi_WID                      ( 6)
+  #define DDRDATACH0_CR_RXTRAINRANK3_RxDqsPPi_MSK                      (0x00007E00)
+  #define DDRDATACH0_CR_RXTRAINRANK3_RxDqsPPi_MAX                      (0x0000003F)
+  #define DDRDATACH0_CR_RXTRAINRANK3_RxEq_OFF                          (15)
+  #define DDRDATACH0_CR_RXTRAINRANK3_RxEq_WID                          ( 5)
+  #define DDRDATACH0_CR_RXTRAINRANK3_RxEq_MSK                          (0x000F8000)
+  #define DDRDATACH0_CR_RXTRAINRANK3_RxEq_MAX                          (0x0000001F)
+  #define DDRDATACH0_CR_RXTRAINRANK3_RxDqsNPi_OFF                      (20)
+  #define DDRDATACH0_CR_RXTRAINRANK3_RxDqsNPi_WID                      ( 6)
+  #define DDRDATACH0_CR_RXTRAINRANK3_RxDqsNPi_MSK                      (0x03F00000)
+  #define DDRDATACH0_CR_RXTRAINRANK3_RxDqsNPi_MAX                      (0x0000003F)
+  #define DDRDATACH0_CR_RXTRAINRANK3_RxVref_OFF                        (26)
+  #define DDRDATACH0_CR_RXTRAINRANK3_RxVref_WID                        ( 6)
+  #define DDRDATACH0_CR_RXTRAINRANK3_RxVref_MSK                        (0xFC000000)
+  #define DDRDATACH0_CR_RXTRAINRANK3_RxVref_MAX                        (0x0000003F)
+
+#define DDRDATACH0_CR_RXPERBITRANK0_REG                              (0x00003010)
+  #define DDRDATACH0_CR_RXPERBITRANK0_Lane0_OFF                        ( 0)
+  #define DDRDATACH0_CR_RXPERBITRANK0_Lane0_WID                        ( 4)
+  #define DDRDATACH0_CR_RXPERBITRANK0_Lane0_MSK                        (0x0000000F)
+  #define DDRDATACH0_CR_RXPERBITRANK0_Lane0_MAX                        (0x0000000F)
+  #define DDRDATACH0_CR_RXPERBITRANK0_Lane1_OFF                        ( 4)
+  #define DDRDATACH0_CR_RXPERBITRANK0_Lane1_WID                        ( 4)
+  #define DDRDATACH0_CR_RXPERBITRANK0_Lane1_MSK                        (0x000000F0)
+  #define DDRDATACH0_CR_RXPERBITRANK0_Lane1_MAX                        (0x0000000F)
+  #define DDRDATACH0_CR_RXPERBITRANK0_Lane2_OFF                        ( 8)
+  #define DDRDATACH0_CR_RXPERBITRANK0_Lane2_WID                        ( 4)
+  #define DDRDATACH0_CR_RXPERBITRANK0_Lane2_MSK                        (0x00000F00)
+  #define DDRDATACH0_CR_RXPERBITRANK0_Lane2_MAX                        (0x0000000F)
+  #define DDRDATACH0_CR_RXPERBITRANK0_Lane3_OFF                        (12)
+  #define DDRDATACH0_CR_RXPERBITRANK0_Lane3_WID                        ( 4)
+  #define DDRDATACH0_CR_RXPERBITRANK0_Lane3_MSK                        (0x0000F000)
+  #define DDRDATACH0_CR_RXPERBITRANK0_Lane3_MAX                        (0x0000000F)
+  #define DDRDATACH0_CR_RXPERBITRANK0_Lane4_OFF                        (16)
+  #define DDRDATACH0_CR_RXPERBITRANK0_Lane4_WID                        ( 4)
+  #define DDRDATACH0_CR_RXPERBITRANK0_Lane4_MSK                        (0x000F0000)
+  #define DDRDATACH0_CR_RXPERBITRANK0_Lane4_MAX                        (0x0000000F)
+  #define DDRDATACH0_CR_RXPERBITRANK0_Lane5_OFF                        (20)
+  #define DDRDATACH0_CR_RXPERBITRANK0_Lane5_WID                        ( 4)
+  #define DDRDATACH0_CR_RXPERBITRANK0_Lane5_MSK                        (0x00F00000)
+  #define DDRDATACH0_CR_RXPERBITRANK0_Lane5_MAX                        (0x0000000F)
+  #define DDRDATACH0_CR_RXPERBITRANK0_Lane6_OFF                        (24)
+  #define DDRDATACH0_CR_RXPERBITRANK0_Lane6_WID                        ( 4)
+  #define DDRDATACH0_CR_RXPERBITRANK0_Lane6_MSK                        (0x0F000000)
+  #define DDRDATACH0_CR_RXPERBITRANK0_Lane6_MAX                        (0x0000000F)
+  #define DDRDATACH0_CR_RXPERBITRANK0_Lane7_OFF                        (28)
+  #define DDRDATACH0_CR_RXPERBITRANK0_Lane7_WID                        ( 4)
+  #define DDRDATACH0_CR_RXPERBITRANK0_Lane7_MSK                        (0xF0000000)
+  #define DDRDATACH0_CR_RXPERBITRANK0_Lane7_MAX                        (0x0000000F)
+
+#define DDRDATACH0_CR_RXPERBITRANK1_REG                              (0x00003014)
+  #define DDRDATACH0_CR_RXPERBITRANK1_Lane0_OFF                        ( 0)
+  #define DDRDATACH0_CR_RXPERBITRANK1_Lane0_WID                        ( 4)
+  #define DDRDATACH0_CR_RXPERBITRANK1_Lane0_MSK                        (0x0000000F)
+  #define DDRDATACH0_CR_RXPERBITRANK1_Lane0_MAX                        (0x0000000F)
+  #define DDRDATACH0_CR_RXPERBITRANK1_Lane1_OFF                        ( 4)
+  #define DDRDATACH0_CR_RXPERBITRANK1_Lane1_WID                        ( 4)
+  #define DDRDATACH0_CR_RXPERBITRANK1_Lane1_MSK                        (0x000000F0)
+  #define DDRDATACH0_CR_RXPERBITRANK1_Lane1_MAX                        (0x0000000F)
+  #define DDRDATACH0_CR_RXPERBITRANK1_Lane2_OFF                        ( 8)
+  #define DDRDATACH0_CR_RXPERBITRANK1_Lane2_WID                        ( 4)
+  #define DDRDATACH0_CR_RXPERBITRANK1_Lane2_MSK                        (0x00000F00)
+  #define DDRDATACH0_CR_RXPERBITRANK1_Lane2_MAX                        (0x0000000F)
+  #define DDRDATACH0_CR_RXPERBITRANK1_Lane3_OFF                        (12)
+  #define DDRDATACH0_CR_RXPERBITRANK1_Lane3_WID                        ( 4)
+  #define DDRDATACH0_CR_RXPERBITRANK1_Lane3_MSK                        (0x0000F000)
+  #define DDRDATACH0_CR_RXPERBITRANK1_Lane3_MAX                        (0x0000000F)
+  #define DDRDATACH0_CR_RXPERBITRANK1_Lane4_OFF                        (16)
+  #define DDRDATACH0_CR_RXPERBITRANK1_Lane4_WID                        ( 4)
+  #define DDRDATACH0_CR_RXPERBITRANK1_Lane4_MSK                        (0x000F0000)
+  #define DDRDATACH0_CR_RXPERBITRANK1_Lane4_MAX                        (0x0000000F)
+  #define DDRDATACH0_CR_RXPERBITRANK1_Lane5_OFF                        (20)
+  #define DDRDATACH0_CR_RXPERBITRANK1_Lane5_WID                        ( 4)
+  #define DDRDATACH0_CR_RXPERBITRANK1_Lane5_MSK                        (0x00F00000)
+  #define DDRDATACH0_CR_RXPERBITRANK1_Lane5_MAX                        (0x0000000F)
+  #define DDRDATACH0_CR_RXPERBITRANK1_Lane6_OFF                        (24)
+  #define DDRDATACH0_CR_RXPERBITRANK1_Lane6_WID                        ( 4)
+  #define DDRDATACH0_CR_RXPERBITRANK1_Lane6_MSK                        (0x0F000000)
+  #define DDRDATACH0_CR_RXPERBITRANK1_Lane6_MAX                        (0x0000000F)
+  #define DDRDATACH0_CR_RXPERBITRANK1_Lane7_OFF                        (28)
+  #define DDRDATACH0_CR_RXPERBITRANK1_Lane7_WID                        ( 4)
+  #define DDRDATACH0_CR_RXPERBITRANK1_Lane7_MSK                        (0xF0000000)
+  #define DDRDATACH0_CR_RXPERBITRANK1_Lane7_MAX                        (0x0000000F)
+
+#define DDRDATACH0_CR_RXPERBITRANK2_REG                              (0x00003018)
+  #define DDRDATACH0_CR_RXPERBITRANK2_Lane0_OFF                        ( 0)
+  #define DDRDATACH0_CR_RXPERBITRANK2_Lane0_WID                        ( 4)
+  #define DDRDATACH0_CR_RXPERBITRANK2_Lane0_MSK                        (0x0000000F)
+  #define DDRDATACH0_CR_RXPERBITRANK2_Lane0_MAX                        (0x0000000F)
+  #define DDRDATACH0_CR_RXPERBITRANK2_Lane1_OFF                        ( 4)
+  #define DDRDATACH0_CR_RXPERBITRANK2_Lane1_WID                        ( 4)
+  #define DDRDATACH0_CR_RXPERBITRANK2_Lane1_MSK                        (0x000000F0)
+  #define DDRDATACH0_CR_RXPERBITRANK2_Lane1_MAX                        (0x0000000F)
+  #define DDRDATACH0_CR_RXPERBITRANK2_Lane2_OFF                        ( 8)
+  #define DDRDATACH0_CR_RXPERBITRANK2_Lane2_WID                        ( 4)
+  #define DDRDATACH0_CR_RXPERBITRANK2_Lane2_MSK                        (0x00000F00)
+  #define DDRDATACH0_CR_RXPERBITRANK2_Lane2_MAX                        (0x0000000F)
+  #define DDRDATACH0_CR_RXPERBITRANK2_Lane3_OFF                        (12)
+  #define DDRDATACH0_CR_RXPERBITRANK2_Lane3_WID                        ( 4)
+  #define DDRDATACH0_CR_RXPERBITRANK2_Lane3_MSK                        (0x0000F000)
+  #define DDRDATACH0_CR_RXPERBITRANK2_Lane3_MAX                        (0x0000000F)
+  #define DDRDATACH0_CR_RXPERBITRANK2_Lane4_OFF                        (16)
+  #define DDRDATACH0_CR_RXPERBITRANK2_Lane4_WID                        ( 4)
+  #define DDRDATACH0_CR_RXPERBITRANK2_Lane4_MSK                        (0x000F0000)
+  #define DDRDATACH0_CR_RXPERBITRANK2_Lane4_MAX                        (0x0000000F)
+  #define DDRDATACH0_CR_RXPERBITRANK2_Lane5_OFF                        (20)
+  #define DDRDATACH0_CR_RXPERBITRANK2_Lane5_WID                        ( 4)
+  #define DDRDATACH0_CR_RXPERBITRANK2_Lane5_MSK                        (0x00F00000)
+  #define DDRDATACH0_CR_RXPERBITRANK2_Lane5_MAX                        (0x0000000F)
+  #define DDRDATACH0_CR_RXPERBITRANK2_Lane6_OFF                        (24)
+  #define DDRDATACH0_CR_RXPERBITRANK2_Lane6_WID                        ( 4)
+  #define DDRDATACH0_CR_RXPERBITRANK2_Lane6_MSK                        (0x0F000000)
+  #define DDRDATACH0_CR_RXPERBITRANK2_Lane6_MAX                        (0x0000000F)
+  #define DDRDATACH0_CR_RXPERBITRANK2_Lane7_OFF                        (28)
+  #define DDRDATACH0_CR_RXPERBITRANK2_Lane7_WID                        ( 4)
+  #define DDRDATACH0_CR_RXPERBITRANK2_Lane7_MSK                        (0xF0000000)
+  #define DDRDATACH0_CR_RXPERBITRANK2_Lane7_MAX                        (0x0000000F)
+
+#define DDRDATACH0_CR_RXPERBITRANK3_REG                              (0x0000301C)
+  #define DDRDATACH0_CR_RXPERBITRANK3_Lane0_OFF                        ( 0)
+  #define DDRDATACH0_CR_RXPERBITRANK3_Lane0_WID                        ( 4)
+  #define DDRDATACH0_CR_RXPERBITRANK3_Lane0_MSK                        (0x0000000F)
+  #define DDRDATACH0_CR_RXPERBITRANK3_Lane0_MAX                        (0x0000000F)
+  #define DDRDATACH0_CR_RXPERBITRANK3_Lane1_OFF                        ( 4)
+  #define DDRDATACH0_CR_RXPERBITRANK3_Lane1_WID                        ( 4)
+  #define DDRDATACH0_CR_RXPERBITRANK3_Lane1_MSK                        (0x000000F0)
+  #define DDRDATACH0_CR_RXPERBITRANK3_Lane1_MAX                        (0x0000000F)
+  #define DDRDATACH0_CR_RXPERBITRANK3_Lane2_OFF                        ( 8)
+  #define DDRDATACH0_CR_RXPERBITRANK3_Lane2_WID                        ( 4)
+  #define DDRDATACH0_CR_RXPERBITRANK3_Lane2_MSK                        (0x00000F00)
+  #define DDRDATACH0_CR_RXPERBITRANK3_Lane2_MAX                        (0x0000000F)
+  #define DDRDATACH0_CR_RXPERBITRANK3_Lane3_OFF                        (12)
+  #define DDRDATACH0_CR_RXPERBITRANK3_Lane3_WID                        ( 4)
+  #define DDRDATACH0_CR_RXPERBITRANK3_Lane3_MSK                        (0x0000F000)
+  #define DDRDATACH0_CR_RXPERBITRANK3_Lane3_MAX                        (0x0000000F)
+  #define DDRDATACH0_CR_RXPERBITRANK3_Lane4_OFF                        (16)
+  #define DDRDATACH0_CR_RXPERBITRANK3_Lane4_WID                        ( 4)
+  #define DDRDATACH0_CR_RXPERBITRANK3_Lane4_MSK                        (0x000F0000)
+  #define DDRDATACH0_CR_RXPERBITRANK3_Lane4_MAX                        (0x0000000F)
+  #define DDRDATACH0_CR_RXPERBITRANK3_Lane5_OFF                        (20)
+  #define DDRDATACH0_CR_RXPERBITRANK3_Lane5_WID                        ( 4)
+  #define DDRDATACH0_CR_RXPERBITRANK3_Lane5_MSK                        (0x00F00000)
+  #define DDRDATACH0_CR_RXPERBITRANK3_Lane5_MAX                        (0x0000000F)
+  #define DDRDATACH0_CR_RXPERBITRANK3_Lane6_OFF                        (24)
+  #define DDRDATACH0_CR_RXPERBITRANK3_Lane6_WID                        ( 4)
+  #define DDRDATACH0_CR_RXPERBITRANK3_Lane6_MSK                        (0x0F000000)
+  #define DDRDATACH0_CR_RXPERBITRANK3_Lane6_MAX                        (0x0000000F)
+  #define DDRDATACH0_CR_RXPERBITRANK3_Lane7_OFF                        (28)
+  #define DDRDATACH0_CR_RXPERBITRANK3_Lane7_WID                        ( 4)
+  #define DDRDATACH0_CR_RXPERBITRANK3_Lane7_MSK                        (0xF0000000)
+  #define DDRDATACH0_CR_RXPERBITRANK3_Lane7_MAX                        (0x0000000F)
+
+#define DDRDATACH0_CR_TXTRAINRANK0_REG                               (0x00003020)
+  #define DDRDATACH0_CR_TXTRAINRANK0_TxDqDelay_OFF                     ( 0)
+  #define DDRDATACH0_CR_TXTRAINRANK0_TxDqDelay_WID                     ( 9)
+  #define DDRDATACH0_CR_TXTRAINRANK0_TxDqDelay_MSK                     (0x000001FF)
+  #define DDRDATACH0_CR_TXTRAINRANK0_TxDqDelay_MAX                     (0x000001FF)
+  #define DDRDATACH0_CR_TXTRAINRANK0_TxDqsDelay_OFF                    ( 9)
+  #define DDRDATACH0_CR_TXTRAINRANK0_TxDqsDelay_WID                    ( 9)
+  #define DDRDATACH0_CR_TXTRAINRANK0_TxDqsDelay_MSK                    (0x0003FE00)
+  #define DDRDATACH0_CR_TXTRAINRANK0_TxDqsDelay_MAX                    (0x000001FF)
+  #define DDRDATACH0_CR_TXTRAINRANK0_Spare0_OFF                        (18)
+  #define DDRDATACH0_CR_TXTRAINRANK0_Spare0_WID                        ( 2)
+  #define DDRDATACH0_CR_TXTRAINRANK0_Spare0_MSK                        (0x000C0000)
+  #define DDRDATACH0_CR_TXTRAINRANK0_Spare0_MAX                        (0x00000003)
+  #define DDRDATACH0_CR_TXTRAINRANK0_TxEqualization_OFF                (20)
+  #define DDRDATACH0_CR_TXTRAINRANK0_TxEqualization_WID                ( 6)
+  #define DDRDATACH0_CR_TXTRAINRANK0_TxEqualization_MSK                (0x03F00000)
+  #define DDRDATACH0_CR_TXTRAINRANK0_TxEqualization_MAX                (0x0000003F)
+  #define DDRDATACH0_CR_TXTRAINRANK0_Spare1_OFF                        (26)
+  #define DDRDATACH0_CR_TXTRAINRANK0_Spare1_WID                        ( 6)
+  #define DDRDATACH0_CR_TXTRAINRANK0_Spare1_MSK                        (0xFC000000)
+  #define DDRDATACH0_CR_TXTRAINRANK0_Spare1_MAX                        (0x0000003F)
+
+#define DDRDATACH0_CR_TXTRAINRANK1_REG                               (0x00003024)
+  #define DDRDATACH0_CR_TXTRAINRANK1_TxDqDelay_OFF                     ( 0)
+  #define DDRDATACH0_CR_TXTRAINRANK1_TxDqDelay_WID                     ( 9)
+  #define DDRDATACH0_CR_TXTRAINRANK1_TxDqDelay_MSK                     (0x000001FF)
+  #define DDRDATACH0_CR_TXTRAINRANK1_TxDqDelay_MAX                     (0x000001FF)
+  #define DDRDATACH0_CR_TXTRAINRANK1_TxDqsDelay_OFF                    ( 9)
+  #define DDRDATACH0_CR_TXTRAINRANK1_TxDqsDelay_WID                    ( 9)
+  #define DDRDATACH0_CR_TXTRAINRANK1_TxDqsDelay_MSK                    (0x0003FE00)
+  #define DDRDATACH0_CR_TXTRAINRANK1_TxDqsDelay_MAX                    (0x000001FF)
+  #define DDRDATACH0_CR_TXTRAINRANK1_Spare0_OFF                        (18)
+  #define DDRDATACH0_CR_TXTRAINRANK1_Spare0_WID                        ( 2)
+  #define DDRDATACH0_CR_TXTRAINRANK1_Spare0_MSK                        (0x000C0000)
+  #define DDRDATACH0_CR_TXTRAINRANK1_Spare0_MAX                        (0x00000003)
+  #define DDRDATACH0_CR_TXTRAINRANK1_TxEqualization_OFF                (20)
+  #define DDRDATACH0_CR_TXTRAINRANK1_TxEqualization_WID                ( 6)
+  #define DDRDATACH0_CR_TXTRAINRANK1_TxEqualization_MSK                (0x03F00000)
+  #define DDRDATACH0_CR_TXTRAINRANK1_TxEqualization_MAX                (0x0000003F)
+  #define DDRDATACH0_CR_TXTRAINRANK1_Spare1_OFF                        (26)
+  #define DDRDATACH0_CR_TXTRAINRANK1_Spare1_WID                        ( 6)
+  #define DDRDATACH0_CR_TXTRAINRANK1_Spare1_MSK                        (0xFC000000)
+  #define DDRDATACH0_CR_TXTRAINRANK1_Spare1_MAX                        (0x0000003F)
+
+#define DDRDATACH0_CR_TXTRAINRANK2_REG                               (0x00003028)
+  #define DDRDATACH0_CR_TXTRAINRANK2_TxDqDelay_OFF                     ( 0)
+  #define DDRDATACH0_CR_TXTRAINRANK2_TxDqDelay_WID                     ( 9)
+  #define DDRDATACH0_CR_TXTRAINRANK2_TxDqDelay_MSK                     (0x000001FF)
+  #define DDRDATACH0_CR_TXTRAINRANK2_TxDqDelay_MAX                     (0x000001FF)
+  #define DDRDATACH0_CR_TXTRAINRANK2_TxDqsDelay_OFF                    ( 9)
+  #define DDRDATACH0_CR_TXTRAINRANK2_TxDqsDelay_WID                    ( 9)
+  #define DDRDATACH0_CR_TXTRAINRANK2_TxDqsDelay_MSK                    (0x0003FE00)
+  #define DDRDATACH0_CR_TXTRAINRANK2_TxDqsDelay_MAX                    (0x000001FF)
+  #define DDRDATACH0_CR_TXTRAINRANK2_Spare0_OFF                        (18)
+  #define DDRDATACH0_CR_TXTRAINRANK2_Spare0_WID                        ( 2)
+  #define DDRDATACH0_CR_TXTRAINRANK2_Spare0_MSK                        (0x000C0000)
+  #define DDRDATACH0_CR_TXTRAINRANK2_Spare0_MAX                        (0x00000003)
+  #define DDRDATACH0_CR_TXTRAINRANK2_TxEqualization_OFF                (20)
+  #define DDRDATACH0_CR_TXTRAINRANK2_TxEqualization_WID                ( 6)
+  #define DDRDATACH0_CR_TXTRAINRANK2_TxEqualization_MSK                (0x03F00000)
+  #define DDRDATACH0_CR_TXTRAINRANK2_TxEqualization_MAX                (0x0000003F)
+  #define DDRDATACH0_CR_TXTRAINRANK2_Spare1_OFF                        (26)
+  #define DDRDATACH0_CR_TXTRAINRANK2_Spare1_WID                        ( 6)
+  #define DDRDATACH0_CR_TXTRAINRANK2_Spare1_MSK                        (0xFC000000)
+  #define DDRDATACH0_CR_TXTRAINRANK2_Spare1_MAX                        (0x0000003F)
+
+#define DDRDATACH0_CR_TXTRAINRANK3_REG                               (0x0000302C)
+  #define DDRDATACH0_CR_TXTRAINRANK3_TxDqDelay_OFF                     ( 0)
+  #define DDRDATACH0_CR_TXTRAINRANK3_TxDqDelay_WID                     ( 9)
+  #define DDRDATACH0_CR_TXTRAINRANK3_TxDqDelay_MSK                     (0x000001FF)
+  #define DDRDATACH0_CR_TXTRAINRANK3_TxDqDelay_MAX                     (0x000001FF)
+  #define DDRDATACH0_CR_TXTRAINRANK3_TxDqsDelay_OFF                    ( 9)
+  #define DDRDATACH0_CR_TXTRAINRANK3_TxDqsDelay_WID                    ( 9)
+  #define DDRDATACH0_CR_TXTRAINRANK3_TxDqsDelay_MSK                    (0x0003FE00)
+  #define DDRDATACH0_CR_TXTRAINRANK3_TxDqsDelay_MAX                    (0x000001FF)
+  #define DDRDATACH0_CR_TXTRAINRANK3_Spare0_OFF                        (18)
+  #define DDRDATACH0_CR_TXTRAINRANK3_Spare0_WID                        ( 2)
+  #define DDRDATACH0_CR_TXTRAINRANK3_Spare0_MSK                        (0x000C0000)
+  #define DDRDATACH0_CR_TXTRAINRANK3_Spare0_MAX                        (0x00000003)
+  #define DDRDATACH0_CR_TXTRAINRANK3_TxEqualization_OFF                (20)
+  #define DDRDATACH0_CR_TXTRAINRANK3_TxEqualization_WID                ( 6)
+  #define DDRDATACH0_CR_TXTRAINRANK3_TxEqualization_MSK                (0x03F00000)
+  #define DDRDATACH0_CR_TXTRAINRANK3_TxEqualization_MAX                (0x0000003F)
+  #define DDRDATACH0_CR_TXTRAINRANK3_Spare1_OFF                        (26)
+  #define DDRDATACH0_CR_TXTRAINRANK3_Spare1_WID                        ( 6)
+  #define DDRDATACH0_CR_TXTRAINRANK3_Spare1_MSK                        (0xFC000000)
+  #define DDRDATACH0_CR_TXTRAINRANK3_Spare1_MAX                        (0x0000003F)
+
+#define DDRDATACH0_CR_TXPERBITRANK0_REG                              (0x00003030)
+  #define DDRDATACH0_CR_TXPERBITRANK0_Lane0_OFF                        ( 0)
+  #define DDRDATACH0_CR_TXPERBITRANK0_Lane0_WID                        ( 4)
+  #define DDRDATACH0_CR_TXPERBITRANK0_Lane0_MSK                        (0x0000000F)
+  #define DDRDATACH0_CR_TXPERBITRANK0_Lane0_MAX                        (0x0000000F)
+  #define DDRDATACH0_CR_TXPERBITRANK0_Lane1_OFF                        ( 4)
+  #define DDRDATACH0_CR_TXPERBITRANK0_Lane1_WID                        ( 4)
+  #define DDRDATACH0_CR_TXPERBITRANK0_Lane1_MSK                        (0x000000F0)
+  #define DDRDATACH0_CR_TXPERBITRANK0_Lane1_MAX                        (0x0000000F)
+  #define DDRDATACH0_CR_TXPERBITRANK0_Lane2_OFF                        ( 8)
+  #define DDRDATACH0_CR_TXPERBITRANK0_Lane2_WID                        ( 4)
+  #define DDRDATACH0_CR_TXPERBITRANK0_Lane2_MSK                        (0x00000F00)
+  #define DDRDATACH0_CR_TXPERBITRANK0_Lane2_MAX                        (0x0000000F)
+  #define DDRDATACH0_CR_TXPERBITRANK0_Lane3_OFF                        (12)
+  #define DDRDATACH0_CR_TXPERBITRANK0_Lane3_WID                        ( 4)
+  #define DDRDATACH0_CR_TXPERBITRANK0_Lane3_MSK                        (0x0000F000)
+  #define DDRDATACH0_CR_TXPERBITRANK0_Lane3_MAX                        (0x0000000F)
+  #define DDRDATACH0_CR_TXPERBITRANK0_Lane4_OFF                        (16)
+  #define DDRDATACH0_CR_TXPERBITRANK0_Lane4_WID                        ( 4)
+  #define DDRDATACH0_CR_TXPERBITRANK0_Lane4_MSK                        (0x000F0000)
+  #define DDRDATACH0_CR_TXPERBITRANK0_Lane4_MAX                        (0x0000000F)
+  #define DDRDATACH0_CR_TXPERBITRANK0_Lane5_OFF                        (20)
+  #define DDRDATACH0_CR_TXPERBITRANK0_Lane5_WID                        ( 4)
+  #define DDRDATACH0_CR_TXPERBITRANK0_Lane5_MSK                        (0x00F00000)
+  #define DDRDATACH0_CR_TXPERBITRANK0_Lane5_MAX                        (0x0000000F)
+  #define DDRDATACH0_CR_TXPERBITRANK0_Lane6_OFF                        (24)
+  #define DDRDATACH0_CR_TXPERBITRANK0_Lane6_WID                        ( 4)
+  #define DDRDATACH0_CR_TXPERBITRANK0_Lane6_MSK                        (0x0F000000)
+  #define DDRDATACH0_CR_TXPERBITRANK0_Lane6_MAX                        (0x0000000F)
+  #define DDRDATACH0_CR_TXPERBITRANK0_Lane7_OFF                        (28)
+  #define DDRDATACH0_CR_TXPERBITRANK0_Lane7_WID                        ( 4)
+  #define DDRDATACH0_CR_TXPERBITRANK0_Lane7_MSK                        (0xF0000000)
+  #define DDRDATACH0_CR_TXPERBITRANK0_Lane7_MAX                        (0x0000000F)
+
+#define DDRDATACH0_CR_TXPERBITRANK1_REG                              (0x00003034)
+  #define DDRDATACH0_CR_TXPERBITRANK1_Lane0_OFF                        ( 0)
+  #define DDRDATACH0_CR_TXPERBITRANK1_Lane0_WID                        ( 4)
+  #define DDRDATACH0_CR_TXPERBITRANK1_Lane0_MSK                        (0x0000000F)
+  #define DDRDATACH0_CR_TXPERBITRANK1_Lane0_MAX                        (0x0000000F)
+  #define DDRDATACH0_CR_TXPERBITRANK1_Lane1_OFF                        ( 4)
+  #define DDRDATACH0_CR_TXPERBITRANK1_Lane1_WID                        ( 4)
+  #define DDRDATACH0_CR_TXPERBITRANK1_Lane1_MSK                        (0x000000F0)
+  #define DDRDATACH0_CR_TXPERBITRANK1_Lane1_MAX                        (0x0000000F)
+  #define DDRDATACH0_CR_TXPERBITRANK1_Lane2_OFF                        ( 8)
+  #define DDRDATACH0_CR_TXPERBITRANK1_Lane2_WID                        ( 4)
+  #define DDRDATACH0_CR_TXPERBITRANK1_Lane2_MSK                        (0x00000F00)
+  #define DDRDATACH0_CR_TXPERBITRANK1_Lane2_MAX                        (0x0000000F)
+  #define DDRDATACH0_CR_TXPERBITRANK1_Lane3_OFF                        (12)
+  #define DDRDATACH0_CR_TXPERBITRANK1_Lane3_WID                        ( 4)
+  #define DDRDATACH0_CR_TXPERBITRANK1_Lane3_MSK                        (0x0000F000)
+  #define DDRDATACH0_CR_TXPERBITRANK1_Lane3_MAX                        (0x0000000F)
+  #define DDRDATACH0_CR_TXPERBITRANK1_Lane4_OFF                        (16)
+  #define DDRDATACH0_CR_TXPERBITRANK1_Lane4_WID                        ( 4)
+  #define DDRDATACH0_CR_TXPERBITRANK1_Lane4_MSK                        (0x000F0000)
+  #define DDRDATACH0_CR_TXPERBITRANK1_Lane4_MAX                        (0x0000000F)
+  #define DDRDATACH0_CR_TXPERBITRANK1_Lane5_OFF                        (20)
+  #define DDRDATACH0_CR_TXPERBITRANK1_Lane5_WID                        ( 4)
+  #define DDRDATACH0_CR_TXPERBITRANK1_Lane5_MSK                        (0x00F00000)
+  #define DDRDATACH0_CR_TXPERBITRANK1_Lane5_MAX                        (0x0000000F)
+  #define DDRDATACH0_CR_TXPERBITRANK1_Lane6_OFF                        (24)
+  #define DDRDATACH0_CR_TXPERBITRANK1_Lane6_WID                        ( 4)
+  #define DDRDATACH0_CR_TXPERBITRANK1_Lane6_MSK                        (0x0F000000)
+  #define DDRDATACH0_CR_TXPERBITRANK1_Lane6_MAX                        (0x0000000F)
+  #define DDRDATACH0_CR_TXPERBITRANK1_Lane7_OFF                        (28)
+  #define DDRDATACH0_CR_TXPERBITRANK1_Lane7_WID                        ( 4)
+  #define DDRDATACH0_CR_TXPERBITRANK1_Lane7_MSK                        (0xF0000000)
+  #define DDRDATACH0_CR_TXPERBITRANK1_Lane7_MAX                        (0x0000000F)
+
+#define DDRDATACH0_CR_TXPERBITRANK2_REG                              (0x00003038)
+  #define DDRDATACH0_CR_TXPERBITRANK2_Lane0_OFF                        ( 0)
+  #define DDRDATACH0_CR_TXPERBITRANK2_Lane0_WID                        ( 4)
+  #define DDRDATACH0_CR_TXPERBITRANK2_Lane0_MSK                        (0x0000000F)
+  #define DDRDATACH0_CR_TXPERBITRANK2_Lane0_MAX                        (0x0000000F)
+  #define DDRDATACH0_CR_TXPERBITRANK2_Lane1_OFF                        ( 4)
+  #define DDRDATACH0_CR_TXPERBITRANK2_Lane1_WID                        ( 4)
+  #define DDRDATACH0_CR_TXPERBITRANK2_Lane1_MSK                        (0x000000F0)
+  #define DDRDATACH0_CR_TXPERBITRANK2_Lane1_MAX                        (0x0000000F)
+  #define DDRDATACH0_CR_TXPERBITRANK2_Lane2_OFF                        ( 8)
+  #define DDRDATACH0_CR_TXPERBITRANK2_Lane2_WID                        ( 4)
+  #define DDRDATACH0_CR_TXPERBITRANK2_Lane2_MSK                        (0x00000F00)
+  #define DDRDATACH0_CR_TXPERBITRANK2_Lane2_MAX                        (0x0000000F)
+  #define DDRDATACH0_CR_TXPERBITRANK2_Lane3_OFF                        (12)
+  #define DDRDATACH0_CR_TXPERBITRANK2_Lane3_WID                        ( 4)
+  #define DDRDATACH0_CR_TXPERBITRANK2_Lane3_MSK                        (0x0000F000)
+  #define DDRDATACH0_CR_TXPERBITRANK2_Lane3_MAX                        (0x0000000F)
+  #define DDRDATACH0_CR_TXPERBITRANK2_Lane4_OFF                        (16)
+  #define DDRDATACH0_CR_TXPERBITRANK2_Lane4_WID                        ( 4)
+  #define DDRDATACH0_CR_TXPERBITRANK2_Lane4_MSK                        (0x000F0000)
+  #define DDRDATACH0_CR_TXPERBITRANK2_Lane4_MAX                        (0x0000000F)
+  #define DDRDATACH0_CR_TXPERBITRANK2_Lane5_OFF                        (20)
+  #define DDRDATACH0_CR_TXPERBITRANK2_Lane5_WID                        ( 4)
+  #define DDRDATACH0_CR_TXPERBITRANK2_Lane5_MSK                        (0x00F00000)
+  #define DDRDATACH0_CR_TXPERBITRANK2_Lane5_MAX                        (0x0000000F)
+  #define DDRDATACH0_CR_TXPERBITRANK2_Lane6_OFF                        (24)
+  #define DDRDATACH0_CR_TXPERBITRANK2_Lane6_WID                        ( 4)
+  #define DDRDATACH0_CR_TXPERBITRANK2_Lane6_MSK                        (0x0F000000)
+  #define DDRDATACH0_CR_TXPERBITRANK2_Lane6_MAX                        (0x0000000F)
+  #define DDRDATACH0_CR_TXPERBITRANK2_Lane7_OFF                        (28)
+  #define DDRDATACH0_CR_TXPERBITRANK2_Lane7_WID                        ( 4)
+  #define DDRDATACH0_CR_TXPERBITRANK2_Lane7_MSK                        (0xF0000000)
+  #define DDRDATACH0_CR_TXPERBITRANK2_Lane7_MAX                        (0x0000000F)
+
+#define DDRDATACH0_CR_TXPERBITRANK3_REG                              (0x0000303C)
+  #define DDRDATACH0_CR_TXPERBITRANK3_Lane0_OFF                        ( 0)
+  #define DDRDATACH0_CR_TXPERBITRANK3_Lane0_WID                        ( 4)
+  #define DDRDATACH0_CR_TXPERBITRANK3_Lane0_MSK                        (0x0000000F)
+  #define DDRDATACH0_CR_TXPERBITRANK3_Lane0_MAX                        (0x0000000F)
+  #define DDRDATACH0_CR_TXPERBITRANK3_Lane1_OFF                        ( 4)
+  #define DDRDATACH0_CR_TXPERBITRANK3_Lane1_WID                        ( 4)
+  #define DDRDATACH0_CR_TXPERBITRANK3_Lane1_MSK                        (0x000000F0)
+  #define DDRDATACH0_CR_TXPERBITRANK3_Lane1_MAX                        (0x0000000F)
+  #define DDRDATACH0_CR_TXPERBITRANK3_Lane2_OFF                        ( 8)
+  #define DDRDATACH0_CR_TXPERBITRANK3_Lane2_WID                        ( 4)
+  #define DDRDATACH0_CR_TXPERBITRANK3_Lane2_MSK                        (0x00000F00)
+  #define DDRDATACH0_CR_TXPERBITRANK3_Lane2_MAX                        (0x0000000F)
+  #define DDRDATACH0_CR_TXPERBITRANK3_Lane3_OFF                        (12)
+  #define DDRDATACH0_CR_TXPERBITRANK3_Lane3_WID                        ( 4)
+  #define DDRDATACH0_CR_TXPERBITRANK3_Lane3_MSK                        (0x0000F000)
+  #define DDRDATACH0_CR_TXPERBITRANK3_Lane3_MAX                        (0x0000000F)
+  #define DDRDATACH0_CR_TXPERBITRANK3_Lane4_OFF                        (16)
+  #define DDRDATACH0_CR_TXPERBITRANK3_Lane4_WID                        ( 4)
+  #define DDRDATACH0_CR_TXPERBITRANK3_Lane4_MSK                        (0x000F0000)
+  #define DDRDATACH0_CR_TXPERBITRANK3_Lane4_MAX                        (0x0000000F)
+  #define DDRDATACH0_CR_TXPERBITRANK3_Lane5_OFF                        (20)
+  #define DDRDATACH0_CR_TXPERBITRANK3_Lane5_WID                        ( 4)
+  #define DDRDATACH0_CR_TXPERBITRANK3_Lane5_MSK                        (0x00F00000)
+  #define DDRDATACH0_CR_TXPERBITRANK3_Lane5_MAX                        (0x0000000F)
+  #define DDRDATACH0_CR_TXPERBITRANK3_Lane6_OFF                        (24)
+  #define DDRDATACH0_CR_TXPERBITRANK3_Lane6_WID                        ( 4)
+  #define DDRDATACH0_CR_TXPERBITRANK3_Lane6_MSK                        (0x0F000000)
+  #define DDRDATACH0_CR_TXPERBITRANK3_Lane6_MAX                        (0x0000000F)
+  #define DDRDATACH0_CR_TXPERBITRANK3_Lane7_OFF                        (28)
+  #define DDRDATACH0_CR_TXPERBITRANK3_Lane7_WID                        ( 4)
+  #define DDRDATACH0_CR_TXPERBITRANK3_Lane7_MSK                        (0xF0000000)
+  #define DDRDATACH0_CR_TXPERBITRANK3_Lane7_MAX                        (0x0000000F)
+
+#define DDRDATACH0_CR_RCOMPDATA0_REG                                 (0x00003040)
+  #define DDRDATACH0_CR_RCOMPDATA0_RcompDrvUp_OFF                      ( 0)
+  #define DDRDATACH0_CR_RCOMPDATA0_RcompDrvUp_WID                      ( 6)
+  #define DDRDATACH0_CR_RCOMPDATA0_RcompDrvUp_MSK                      (0x0000003F)
+  #define DDRDATACH0_CR_RCOMPDATA0_RcompDrvUp_MAX                      (0x0000003F)
+  #define DDRDATACH0_CR_RCOMPDATA0_Spare0_OFF                          ( 6)
+  #define DDRDATACH0_CR_RCOMPDATA0_Spare0_WID                          ( 3)
+  #define DDRDATACH0_CR_RCOMPDATA0_Spare0_MSK                          (0x000001C0)
+  #define DDRDATACH0_CR_RCOMPDATA0_Spare0_MAX                          (0x00000007)
+  #define DDRDATACH0_CR_RCOMPDATA0_RcompDrvDown_OFF                    ( 9)
+  #define DDRDATACH0_CR_RCOMPDATA0_RcompDrvDown_WID                    ( 6)
+  #define DDRDATACH0_CR_RCOMPDATA0_RcompDrvDown_MSK                    (0x00007E00)
+  #define DDRDATACH0_CR_RCOMPDATA0_RcompDrvDown_MAX                    (0x0000003F)
+  #define DDRDATACH0_CR_RCOMPDATA0_VTComp_OFF                          (15)
+  #define DDRDATACH0_CR_RCOMPDATA0_VTComp_WID                          ( 5)
+  #define DDRDATACH0_CR_RCOMPDATA0_VTComp_MSK                          (0x000F8000)
+  #define DDRDATACH0_CR_RCOMPDATA0_VTComp_MAX                          (0x0000001F)
+  #define DDRDATACH0_CR_RCOMPDATA0_TcoComp_OFF                         (20)
+  #define DDRDATACH0_CR_RCOMPDATA0_TcoComp_WID                         ( 6)
+  #define DDRDATACH0_CR_RCOMPDATA0_TcoComp_MSK                         (0x03F00000)
+  #define DDRDATACH0_CR_RCOMPDATA0_TcoComp_MAX                         (0x0000003F)
+  #define DDRDATACH0_CR_RCOMPDATA0_SlewRateComp_OFF                    (26)
+  #define DDRDATACH0_CR_RCOMPDATA0_SlewRateComp_WID                    ( 5)
+  #define DDRDATACH0_CR_RCOMPDATA0_SlewRateComp_MSK                    (0x7C000000)
+  #define DDRDATACH0_CR_RCOMPDATA0_SlewRateComp_MAX                    (0x0000001F)
+  #define DDRDATACH0_CR_RCOMPDATA0_Spare2_OFF                          (31)
+  #define DDRDATACH0_CR_RCOMPDATA0_Spare2_WID                          ( 1)
+  #define DDRDATACH0_CR_RCOMPDATA0_Spare2_MSK                          (0x80000000)
+  #define DDRDATACH0_CR_RCOMPDATA0_Spare2_MAX                          (0x00000001)
+
+#define DDRDATACH0_CR_RCOMPDATA1_REG                                 (0x00003044)
+  #define DDRDATACH0_CR_RCOMPDATA1_RcompOdtUp_OFF                      ( 0)
+  #define DDRDATACH0_CR_RCOMPDATA1_RcompOdtUp_WID                      ( 6)
+  #define DDRDATACH0_CR_RCOMPDATA1_RcompOdtUp_MSK                      (0x0000003F)
+  #define DDRDATACH0_CR_RCOMPDATA1_RcompOdtUp_MAX                      (0x0000003F)
+  #define DDRDATACH0_CR_RCOMPDATA1_Spare0_OFF                          ( 6)
+  #define DDRDATACH0_CR_RCOMPDATA1_Spare0_WID                          ( 3)
+  #define DDRDATACH0_CR_RCOMPDATA1_Spare0_MSK                          (0x000001C0)
+  #define DDRDATACH0_CR_RCOMPDATA1_Spare0_MAX                          (0x00000007)
+  #define DDRDATACH0_CR_RCOMPDATA1_RcompOdtDown_OFF                    ( 9)
+  #define DDRDATACH0_CR_RCOMPDATA1_RcompOdtDown_WID                    ( 6)
+  #define DDRDATACH0_CR_RCOMPDATA1_RcompOdtDown_MSK                    (0x00007E00)
+  #define DDRDATACH0_CR_RCOMPDATA1_RcompOdtDown_MAX                    (0x0000003F)
+  #define DDRDATACH0_CR_RCOMPDATA1_Spare1_OFF                          (15)
+  #define DDRDATACH0_CR_RCOMPDATA1_Spare1_WID                          ( 1)
+  #define DDRDATACH0_CR_RCOMPDATA1_Spare1_MSK                          (0x00008000)
+  #define DDRDATACH0_CR_RCOMPDATA1_Spare1_MAX                          (0x00000001)
+  #define DDRDATACH0_CR_RCOMPDATA1_PanicDrvDn_OFF                      (16)
+  #define DDRDATACH0_CR_RCOMPDATA1_PanicDrvDn_WID                      ( 6)
+  #define DDRDATACH0_CR_RCOMPDATA1_PanicDrvDn_MSK                      (0x003F0000)
+  #define DDRDATACH0_CR_RCOMPDATA1_PanicDrvDn_MAX                      (0x0000003F)
+  #define DDRDATACH0_CR_RCOMPDATA1_PanicDrvUp_OFF                      (22)
+  #define DDRDATACH0_CR_RCOMPDATA1_PanicDrvUp_WID                      ( 6)
+  #define DDRDATACH0_CR_RCOMPDATA1_PanicDrvUp_MSK                      (0x0FC00000)
+  #define DDRDATACH0_CR_RCOMPDATA1_PanicDrvUp_MAX                      (0x0000003F)
+  #define DDRDATACH0_CR_RCOMPDATA1_LevelShifterComp_OFF                (28)
+  #define DDRDATACH0_CR_RCOMPDATA1_LevelShifterComp_WID                ( 3)
+  #define DDRDATACH0_CR_RCOMPDATA1_LevelShifterComp_MSK                (0x70000000)
+  #define DDRDATACH0_CR_RCOMPDATA1_LevelShifterComp_MAX                (0x00000007)
+  #define DDRDATACH0_CR_RCOMPDATA1_Spare2_OFF                          (31)
+  #define DDRDATACH0_CR_RCOMPDATA1_Spare2_WID                          ( 1)
+  #define DDRDATACH0_CR_RCOMPDATA1_Spare2_MSK                          (0x80000000)
+  #define DDRDATACH0_CR_RCOMPDATA1_Spare2_MAX                          (0x00000001)
+
+#define DDRDATACH0_CR_TXXTALK_REG                                    (0x00003048)
+  #define DDRDATACH0_CR_TXXTALK_Lane0_OFF                              ( 0)
+  #define DDRDATACH0_CR_TXXTALK_Lane0_WID                              ( 4)
+  #define DDRDATACH0_CR_TXXTALK_Lane0_MSK                              (0x0000000F)
+  #define DDRDATACH0_CR_TXXTALK_Lane0_MAX                              (0x0000000F)
+  #define DDRDATACH0_CR_TXXTALK_Lane1_OFF                              ( 4)
+  #define DDRDATACH0_CR_TXXTALK_Lane1_WID                              ( 4)
+  #define DDRDATACH0_CR_TXXTALK_Lane1_MSK                              (0x000000F0)
+  #define DDRDATACH0_CR_TXXTALK_Lane1_MAX                              (0x0000000F)
+  #define DDRDATACH0_CR_TXXTALK_Lane2_OFF                              ( 8)
+  #define DDRDATACH0_CR_TXXTALK_Lane2_WID                              ( 4)
+  #define DDRDATACH0_CR_TXXTALK_Lane2_MSK                              (0x00000F00)
+  #define DDRDATACH0_CR_TXXTALK_Lane2_MAX                              (0x0000000F)
+  #define DDRDATACH0_CR_TXXTALK_Lane3_OFF                              (12)
+  #define DDRDATACH0_CR_TXXTALK_Lane3_WID                              ( 4)
+  #define DDRDATACH0_CR_TXXTALK_Lane3_MSK                              (0x0000F000)
+  #define DDRDATACH0_CR_TXXTALK_Lane3_MAX                              (0x0000000F)
+  #define DDRDATACH0_CR_TXXTALK_Lane4_OFF                              (16)
+  #define DDRDATACH0_CR_TXXTALK_Lane4_WID                              ( 4)
+  #define DDRDATACH0_CR_TXXTALK_Lane4_MSK                              (0x000F0000)
+  #define DDRDATACH0_CR_TXXTALK_Lane4_MAX                              (0x0000000F)
+  #define DDRDATACH0_CR_TXXTALK_Lane5_OFF                              (20)
+  #define DDRDATACH0_CR_TXXTALK_Lane5_WID                              ( 4)
+  #define DDRDATACH0_CR_TXXTALK_Lane5_MSK                              (0x00F00000)
+  #define DDRDATACH0_CR_TXXTALK_Lane5_MAX                              (0x0000000F)
+  #define DDRDATACH0_CR_TXXTALK_Lane6_OFF                              (24)
+  #define DDRDATACH0_CR_TXXTALK_Lane6_WID                              ( 4)
+  #define DDRDATACH0_CR_TXXTALK_Lane6_MSK                              (0x0F000000)
+  #define DDRDATACH0_CR_TXXTALK_Lane6_MAX                              (0x0000000F)
+  #define DDRDATACH0_CR_TXXTALK_Lane7_OFF                              (28)
+  #define DDRDATACH0_CR_TXXTALK_Lane7_WID                              ( 4)
+  #define DDRDATACH0_CR_TXXTALK_Lane7_MSK                              (0xF0000000)
+  #define DDRDATACH0_CR_TXXTALK_Lane7_MAX                              (0x0000000F)
+
+#define DDRDATACH0_CR_RXOFFSETVDQ_REG                                (0x0000304C)
+  #define DDRDATACH0_CR_RXOFFSETVDQ_Lane0_OFF                          ( 0)
+  #define DDRDATACH0_CR_RXOFFSETVDQ_Lane0_WID                          ( 4)
+  #define DDRDATACH0_CR_RXOFFSETVDQ_Lane0_MSK                          (0x0000000F)
+  #define DDRDATACH0_CR_RXOFFSETVDQ_Lane0_MAX                          (0x0000000F)
+  #define DDRDATACH0_CR_RXOFFSETVDQ_Lane1_OFF                          ( 4)
+  #define DDRDATACH0_CR_RXOFFSETVDQ_Lane1_WID                          ( 4)
+  #define DDRDATACH0_CR_RXOFFSETVDQ_Lane1_MSK                          (0x000000F0)
+  #define DDRDATACH0_CR_RXOFFSETVDQ_Lane1_MAX                          (0x0000000F)
+  #define DDRDATACH0_CR_RXOFFSETVDQ_Lane2_OFF                          ( 8)
+  #define DDRDATACH0_CR_RXOFFSETVDQ_Lane2_WID                          ( 4)
+  #define DDRDATACH0_CR_RXOFFSETVDQ_Lane2_MSK                          (0x00000F00)
+  #define DDRDATACH0_CR_RXOFFSETVDQ_Lane2_MAX                          (0x0000000F)
+  #define DDRDATACH0_CR_RXOFFSETVDQ_Lane3_OFF                          (12)
+  #define DDRDATACH0_CR_RXOFFSETVDQ_Lane3_WID                          ( 4)
+  #define DDRDATACH0_CR_RXOFFSETVDQ_Lane3_MSK                          (0x0000F000)
+  #define DDRDATACH0_CR_RXOFFSETVDQ_Lane3_MAX                          (0x0000000F)
+  #define DDRDATACH0_CR_RXOFFSETVDQ_Lane4_OFF                          (16)
+  #define DDRDATACH0_CR_RXOFFSETVDQ_Lane4_WID                          ( 4)
+  #define DDRDATACH0_CR_RXOFFSETVDQ_Lane4_MSK                          (0x000F0000)
+  #define DDRDATACH0_CR_RXOFFSETVDQ_Lane4_MAX                          (0x0000000F)
+  #define DDRDATACH0_CR_RXOFFSETVDQ_Lane5_OFF                          (20)
+  #define DDRDATACH0_CR_RXOFFSETVDQ_Lane5_WID                          ( 4)
+  #define DDRDATACH0_CR_RXOFFSETVDQ_Lane5_MSK                          (0x00F00000)
+  #define DDRDATACH0_CR_RXOFFSETVDQ_Lane5_MAX                          (0x0000000F)
+  #define DDRDATACH0_CR_RXOFFSETVDQ_Lane6_OFF                          (24)
+  #define DDRDATACH0_CR_RXOFFSETVDQ_Lane6_WID                          ( 4)
+  #define DDRDATACH0_CR_RXOFFSETVDQ_Lane6_MSK                          (0x0F000000)
+  #define DDRDATACH0_CR_RXOFFSETVDQ_Lane6_MAX                          (0x0000000F)
+  #define DDRDATACH0_CR_RXOFFSETVDQ_Lane7_OFF                          (28)
+  #define DDRDATACH0_CR_RXOFFSETVDQ_Lane7_WID                          ( 4)
+  #define DDRDATACH0_CR_RXOFFSETVDQ_Lane7_MSK                          (0xF0000000)
+  #define DDRDATACH0_CR_RXOFFSETVDQ_Lane7_MAX                          (0x0000000F)
+
+#define DDRDATACH0_CR_DDRDATARESERVED_REG                            (0x00003050)
+  #define DDRDATACH0_CR_DDRDATARESERVED_Spare_OFF                      ( 0)
+  #define DDRDATACH0_CR_DDRDATARESERVED_Spare_WID                      (32)
+  #define DDRDATACH0_CR_DDRDATARESERVED_Spare_MSK                      (0xFFFFFFFF)
+  #define DDRDATACH0_CR_DDRDATARESERVED_Spare_MAX                      (0xFFFFFFFF)
+
+#define DDRDATACH0_CR_DATATRAINFEEDBACK_REG                          (0x00003054)
+  #define DDRDATACH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_OFF        ( 0)
+  #define DDRDATACH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_WID        ( 9)
+  #define DDRDATACH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_MSK        (0x000001FF)
+  #define DDRDATACH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_MAX        (0x000001FF)
+  #define DDRDATACH0_CR_DATATRAINFEEDBACK_Spare_OFF                    ( 9)
+  #define DDRDATACH0_CR_DATATRAINFEEDBACK_Spare_WID                    (23)
+  #define DDRDATACH0_CR_DATATRAINFEEDBACK_Spare_MSK                    (0xFFFFFE00)
+  #define DDRDATACH0_CR_DATATRAINFEEDBACK_Spare_MAX                    (0x007FFFFF)
+
+#define DDRDATACH0_CR_DLLPITESTANDADC_REG                            (0x00003058)
+  #define DDRDATACH0_CR_DLLPITESTANDADC_RunTest_OFF                    ( 0)
+  #define DDRDATACH0_CR_DLLPITESTANDADC_RunTest_WID                    ( 1)
+  #define DDRDATACH0_CR_DLLPITESTANDADC_RunTest_MSK                    (0x00000001)
+  #define DDRDATACH0_CR_DLLPITESTANDADC_RunTest_MAX                    (0x00000001)
+  #define DDRDATACH0_CR_DLLPITESTANDADC_RunTest_DEF                    (0x00000000)
+  #define DDRDATACH0_CR_DLLPITESTANDADC_Load_OFF                       ( 1)
+  #define DDRDATACH0_CR_DLLPITESTANDADC_Load_WID                       ( 1)
+  #define DDRDATACH0_CR_DLLPITESTANDADC_Load_MSK                       (0x00000002)
+  #define DDRDATACH0_CR_DLLPITESTANDADC_Load_MAX                       (0x00000001)
+  #define DDRDATACH0_CR_DLLPITESTANDADC_Load_DEF                       (0x00000000)
+  #define DDRDATACH0_CR_DLLPITESTANDADC_ModeHVM_OFF                    ( 2)
+  #define DDRDATACH0_CR_DLLPITESTANDADC_ModeHVM_WID                    ( 1)
+  #define DDRDATACH0_CR_DLLPITESTANDADC_ModeHVM_MSK                    (0x00000004)
+  #define DDRDATACH0_CR_DLLPITESTANDADC_ModeHVM_MAX                    (0x00000001)
+  #define DDRDATACH0_CR_DLLPITESTANDADC_ModeHVM_DEF                    (0x00000000)
+  #define DDRDATACH0_CR_DLLPITESTANDADC_ModeDV_OFF                     ( 3)
+  #define DDRDATACH0_CR_DLLPITESTANDADC_ModeDV_WID                     ( 1)
+  #define DDRDATACH0_CR_DLLPITESTANDADC_ModeDV_MSK                     (0x00000008)
+  #define DDRDATACH0_CR_DLLPITESTANDADC_ModeDV_MAX                     (0x00000001)
+  #define DDRDATACH0_CR_DLLPITESTANDADC_ModeDV_DEF                     (0x00000000)
+  #define DDRDATACH0_CR_DLLPITESTANDADC_ModeADC_OFF                    ( 4)
+  #define DDRDATACH0_CR_DLLPITESTANDADC_ModeADC_WID                    ( 1)
+  #define DDRDATACH0_CR_DLLPITESTANDADC_ModeADC_MSK                    (0x00000010)
+  #define DDRDATACH0_CR_DLLPITESTANDADC_ModeADC_MAX                    (0x00000001)
+  #define DDRDATACH0_CR_DLLPITESTANDADC_ModeADC_DEF                    (0x00000000)
+  #define DDRDATACH0_CR_DLLPITESTANDADC_LoadCount_OFF                  ( 5)
+  #define DDRDATACH0_CR_DLLPITESTANDADC_LoadCount_WID                  (10)
+  #define DDRDATACH0_CR_DLLPITESTANDADC_LoadCount_MSK                  (0x00007FE0)
+  #define DDRDATACH0_CR_DLLPITESTANDADC_LoadCount_MAX                  (0x000003FF)
+  #define DDRDATACH0_CR_DLLPITESTANDADC_CountStatus_OFF                (15)
+  #define DDRDATACH0_CR_DLLPITESTANDADC_CountStatus_WID                (10)
+  #define DDRDATACH0_CR_DLLPITESTANDADC_CountStatus_MSK                (0x01FF8000)
+  #define DDRDATACH0_CR_DLLPITESTANDADC_CountStatus_MAX                (0x000003FF)
+  #define DDRDATACH0_CR_DLLPITESTANDADC_CountStatus_DEF                (0x00000000)
+  #define DDRDATACH0_CR_DLLPITESTANDADC_Spare_OFF                      (25)
+  #define DDRDATACH0_CR_DLLPITESTANDADC_Spare_WID                      ( 7)
+  #define DDRDATACH0_CR_DLLPITESTANDADC_Spare_MSK                      (0xFE000000)
+  #define DDRDATACH0_CR_DLLPITESTANDADC_Spare_MAX                      (0x0000007F)
+
+#define DDRDATACH0_CR_DDRCRDATAOFFSETCOMP_REG                        (0x0000305C)
+  #define DDRDATACH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_OFF      ( 0)
+  #define DDRDATACH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_WID      ( 6)
+  #define DDRDATACH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MSK      (0x0000003F)
+  #define DDRDATACH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MAX      (0x0000003F)
+  #define DDRDATACH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_DEF      (0x00000000)
+  #define DDRDATACH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_OFF    ( 6)
+  #define DDRDATACH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_WID    ( 6)
+  #define DDRDATACH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MSK    (0x00000FC0)
+  #define DDRDATACH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MAX    (0x0000003F)
+  #define DDRDATACH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_DEF    (0x00000000)
+  #define DDRDATACH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_OFF      (12)
+  #define DDRDATACH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_WID      ( 5)
+  #define DDRDATACH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MSK      (0x0001F000)
+  #define DDRDATACH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MAX      (0x0000001F)
+  #define DDRDATACH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_DEF      (0x00000000)
+  #define DDRDATACH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_OFF    (17)
+  #define DDRDATACH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_WID    ( 5)
+  #define DDRDATACH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MSK    (0x003E0000)
+  #define DDRDATACH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MAX    (0x0000001F)
+  #define DDRDATACH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_DEF    (0x00000000)
+  #define DDRDATACH0_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_OFF        (22)
+  #define DDRDATACH0_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_WID        ( 5)
+  #define DDRDATACH0_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_MSK        (0x07C00000)
+  #define DDRDATACH0_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_MAX        (0x0000001F)
+  #define DDRDATACH0_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_DEF        (0x00000000)
+  #define DDRDATACH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_OFF   (27)
+  #define DDRDATACH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_WID   ( 5)
+  #define DDRDATACH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MSK   (0xF8000000)
+  #define DDRDATACH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MAX   (0x0000001F)
+  #define DDRDATACH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_DEF   (0x00000000)
+
+#define DDRDATACH0_CR_DDRCRDATACONTROL1_REG                          (0x00003060)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL1_RefPi_OFF                    ( 0)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL1_RefPi_WID                    ( 4)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL1_RefPi_MSK                    (0x0000000F)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL1_RefPi_MAX                    (0x0000000F)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL1_RefPi_DEF                    (0x00000000)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL1_DllMask_OFF                  ( 4)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL1_DllMask_WID                  ( 2)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL1_DllMask_MSK                  (0x00000030)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL1_DllMask_MAX                  (0x00000003)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL1_DllMask_DEF                  (0x00000000)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL1_DllWeakLock_OFF              ( 6)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL1_DllWeakLock_WID              ( 1)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL1_DllWeakLock_MSK              (0x00000040)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL1_DllWeakLock_MAX              (0x00000001)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL1_DllWeakLock_DEF              (0x00000000)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_OFF       ( 7)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_WID       ( 3)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MSK       (0x00000380)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MAX       (0x00000007)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_DEF       (0x00000000)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL1_RxBiasCtl_OFF                (10)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL1_RxBiasCtl_WID                ( 3)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL1_RxBiasCtl_MSK                (0x00001C00)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL1_RxBiasCtl_MAX                (0x00000007)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL1_RxBiasCtl_DEF                (0x00000000)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL1_OdtDelay_OFF                 (13)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL1_OdtDelay_WID                 ( 4)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL1_OdtDelay_MSK                 (0x0001E000)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL1_OdtDelay_MAX                 (0x0000000F)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL1_OdtDelay_DEF                 (0x00000000)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL1_OdtDuration_OFF              (17)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL1_OdtDuration_WID              ( 3)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL1_OdtDuration_MSK              (0x000E0000)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL1_OdtDuration_MAX              (0x00000007)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL1_OdtDuration_DEF              (0x00000000)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_OFF            (20)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_WID            ( 4)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_MSK            (0x00F00000)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_MAX            (0x0000000F)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_DEF            (0x00000000)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_OFF         (24)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_WID         ( 3)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_MSK         (0x07000000)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_MAX         (0x00000007)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_DEF         (0x00000000)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL1_BurstEndODTDelay_OFF         (27)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL1_BurstEndODTDelay_WID         ( 3)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL1_BurstEndODTDelay_MSK         (0x38000000)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL1_BurstEndODTDelay_MAX         (0x00000007)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL1_BurstEndODTDelay_DEF         (0x00000000)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_OFF           (30)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_WID           ( 1)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_MSK           (0x40000000)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_MAX           (0x00000001)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_DEF           (0x00000000)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL1_Rsvd1_OFF                    (31)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL1_Rsvd1_WID                    ( 1)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL1_Rsvd1_MSK                    (0x80000000)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL1_Rsvd1_MAX                    (0x00000001)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL1_Rsvd1_DEF                    (0x00000000)
+
+#define DDRDATACH0_CR_DDRCRDATACONTROL2_REG                          (0x00003064)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_OFF             ( 0)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_WID             ( 5)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_MSK             (0x0000001F)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_MAX             (0x0000001F)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_DEF             (0x00000000)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL2_ForceBiasOn_OFF              ( 5)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL2_ForceBiasOn_WID              ( 1)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL2_ForceBiasOn_MSK              (0x00000020)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL2_ForceBiasOn_MAX              (0x00000001)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL2_ForceBiasOn_DEF              (0x00000000)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL2_ForceRxOn_OFF                ( 6)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL2_ForceRxOn_WID                ( 1)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL2_ForceRxOn_MSK                (0x00000040)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL2_ForceRxOn_MAX                (0x00000001)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL2_ForceRxOn_DEF                (0x00000000)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL2_LeakerComp_OFF               ( 7)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL2_LeakerComp_WID               ( 2)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL2_LeakerComp_MSK               (0x00000180)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL2_LeakerComp_MAX               (0x00000003)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL2_LeakerComp_DEF               (0x00000000)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_OFF           ( 9)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_WID           ( 4)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_MSK           (0x00001E00)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_MAX           (0x0000000F)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_DEF           (0x00000008)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL2_RxClkStgNum_OFF              (13)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL2_RxClkStgNum_WID              ( 5)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL2_RxClkStgNum_MSK              (0x0003E000)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL2_RxClkStgNum_MAX              (0x0000001F)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL2_RxClkStgNum_DEF              (0x00000011)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL2_WlLongDelEn_OFF              (18)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL2_WlLongDelEn_WID              ( 1)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL2_WlLongDelEn_MSK              (0x00040000)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL2_WlLongDelEn_MAX              (0x00000001)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL2_WlLongDelEn_DEF              (0x00000000)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL2_Spare_OFF                    (19)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL2_Spare_WID                    (13)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL2_Spare_MSK                    (0xFFF80000)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL2_Spare_MAX                    (0x00001FFF)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL2_Spare_DEF                    (0x00000000)
+
+#define DDRDATACH0_CR_DDRCRVSSHIORVREFCONTROL_REG                    (0x0000306C)
+  #define DDRDATACH0_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_OFF     ( 0)
+  #define DDRDATACH0_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_WID     (24)
+  #define DDRDATACH0_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_MSK     (0x00FFFFFF)
+  #define DDRDATACH0_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_MAX     (0x00FFFFFF)
+  #define DDRDATACH0_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_DEF     (0x00000000)
+  #define DDRDATACH0_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_OFF         (24)
+  #define DDRDATACH0_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_WID         ( 8)
+  #define DDRDATACH0_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_MSK         (0xFF000000)
+  #define DDRDATACH0_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_MAX         (0x000000FF)
+  #define DDRDATACH0_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_DEF         (0x00000000)
+
+#define DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN_REG                       (0x00003070)
+  #define DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_OFF           ( 0)
+  #define DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_WID           ( 6)
+  #define DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MSK           (0x0000003F)
+  #define DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MAX           (0x0000003F)
+  #define DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_DEF           (0x00000000)
+  #define DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_OFF           ( 6)
+  #define DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_WID           ( 6)
+  #define DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MSK           (0x00000FC0)
+  #define DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MAX           (0x0000003F)
+  #define DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_DEF           (0x00000000)
+  #define DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_OFF            (12)
+  #define DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_WID            ( 6)
+  #define DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MSK            (0x0003F000)
+  #define DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MAX            (0x0000003F)
+  #define DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_DEF            (0x00000000)
+  #define DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_OFF           (18)
+  #define DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_WID           ( 6)
+  #define DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MSK           (0x00FC0000)
+  #define DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MAX           (0x0000003F)
+  #define DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_DEF           (0x00000000)
+  #define DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_OFF            (24)
+  #define DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_WID            ( 7)
+  #define DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MSK            (0x7F000000)
+  #define DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MAX            (0x0000007F)
+  #define DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_DEF            (0x00000000)
+  #define DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN_Spare_OFF                 (31)
+  #define DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN_Spare_WID                 ( 1)
+  #define DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN_Spare_MSK                 (0x80000000)
+  #define DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN_Spare_MAX                 (0x00000001)
+  #define DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN_Spare_DEF                 (0x00000000)
+
+#define DDRDATACH0_CR_DDRCRDATACONTROL0_REG                          (0x00003074)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL0_RxTrainingMode_OFF           ( 0)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL0_RxTrainingMode_WID           ( 1)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL0_RxTrainingMode_MSK           (0x00000001)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL0_RxTrainingMode_MAX           (0x00000001)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL0_RxTrainingMode_DEF           (0x00000000)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL0_WLTrainingMode_OFF           ( 1)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL0_WLTrainingMode_WID           ( 1)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL0_WLTrainingMode_MSK           (0x00000002)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL0_WLTrainingMode_MAX           (0x00000001)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL0_WLTrainingMode_DEF           (0x00000000)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL0_RLTrainingMode_OFF           ( 2)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL0_RLTrainingMode_WID           ( 1)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL0_RLTrainingMode_MSK           (0x00000004)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL0_RLTrainingMode_MAX           (0x00000001)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL0_RLTrainingMode_DEF           (0x00000000)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_OFF     ( 3)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_WID     ( 1)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MSK     (0x00000008)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MAX     (0x00000001)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_DEF     (0x00000000)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL0_TxOn_OFF                     ( 4)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL0_TxOn_WID                     ( 1)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL0_TxOn_MSK                     (0x00000010)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL0_TxOn_MAX                     (0x00000001)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL0_TxOn_DEF                     (0x00000000)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL0_RfOn_OFF                     ( 5)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL0_RfOn_WID                     ( 1)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL0_RfOn_MSK                     (0x00000020)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL0_RfOn_MAX                     (0x00000001)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL0_RfOn_DEF                     (0x00000000)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL0_RxPiOn_OFF                   ( 6)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL0_RxPiOn_WID                   ( 1)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL0_RxPiOn_MSK                   (0x00000040)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL0_RxPiOn_MAX                   (0x00000001)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL0_RxPiOn_DEF                   (0x00000000)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL0_TxPiOn_OFF                   ( 7)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL0_TxPiOn_WID                   ( 1)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL0_TxPiOn_MSK                   (0x00000080)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL0_TxPiOn_MAX                   (0x00000001)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL0_TxPiOn_DEF                   (0x00000000)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL0_InternalClocksOn_OFF         ( 8)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL0_InternalClocksOn_WID         ( 1)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL0_InternalClocksOn_MSK         (0x00000100)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL0_InternalClocksOn_MAX         (0x00000001)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL0_InternalClocksOn_DEF         (0x00000000)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_OFF         ( 9)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_WID         ( 1)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MSK         (0x00000200)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MAX         (0x00000001)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_DEF         (0x00000000)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL0_TxDisable_OFF                (10)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL0_TxDisable_WID                ( 1)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL0_TxDisable_MSK                (0x00000400)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL0_TxDisable_MAX                (0x00000001)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL0_TxDisable_DEF                (0x00000000)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL0_RxDisable_OFF                (11)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL0_RxDisable_WID                ( 1)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL0_RxDisable_MSK                (0x00000800)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL0_RxDisable_MAX                (0x00000001)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL0_RxDisable_DEF                (0x00000000)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL0_TxLong_OFF                   (12)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL0_TxLong_WID                   ( 1)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL0_TxLong_MSK                   (0x00001000)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL0_TxLong_MAX                   (0x00000001)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL0_TxLong_DEF                   (0x00000000)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL0_RxDqsCtle_OFF                (13)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL0_RxDqsCtle_WID                ( 2)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL0_RxDqsCtle_MSK                (0x00006000)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL0_RxDqsCtle_MAX                (0x00000003)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL0_RxDqsCtle_DEF                (0x00000000)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL0_RxReadPointer_OFF            (15)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL0_RxReadPointer_WID            ( 3)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL0_RxReadPointer_MSK            (0x00038000)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL0_RxReadPointer_MAX            (0x00000007)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL0_RxReadPointer_DEF            (0x00000000)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL0_DriverSegmentEnable_OFF      (18)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL0_DriverSegmentEnable_WID      ( 1)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL0_DriverSegmentEnable_MSK      (0x00040000)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL0_DriverSegmentEnable_MAX      (0x00000001)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL0_DriverSegmentEnable_DEF      (0x00000000)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL0_DataVccddqHi_OFF             (19)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL0_DataVccddqHi_WID             ( 1)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL0_DataVccddqHi_MSK             (0x00080000)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL0_DataVccddqHi_MAX             (0x00000001)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL0_DataVccddqHi_DEF             (0x00000000)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL0_ReadRFRd_OFF                 (20)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL0_ReadRFRd_WID                 ( 1)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL0_ReadRFRd_MSK                 (0x00100000)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL0_ReadRFRd_MAX                 (0x00000001)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL0_ReadRFRd_DEF                 (0x00000000)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL0_ReadRFWr_OFF                 (21)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL0_ReadRFWr_WID                 ( 1)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL0_ReadRFWr_MSK                 (0x00200000)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL0_ReadRFWr_MAX                 (0x00000001)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL0_ReadRFWr_DEF                 (0x00000000)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL0_ReadRFRank_OFF               (22)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL0_ReadRFRank_WID               ( 2)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL0_ReadRFRank_MSK               (0x00C00000)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL0_ReadRFRank_MAX               (0x00000003)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL0_ReadRFRank_DEF               (0x00000000)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL0_ForceOdtOn_OFF               (24)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL0_ForceOdtOn_WID               ( 1)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL0_ForceOdtOn_MSK               (0x01000000)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL0_ForceOdtOn_MAX               (0x00000001)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL0_ForceOdtOn_DEF               (0x00000000)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL0_OdtSampOff_OFF               (25)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL0_OdtSampOff_WID               ( 1)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL0_OdtSampOff_MSK               (0x02000000)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL0_OdtSampOff_MAX               (0x00000001)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL0_OdtSampOff_DEF               (0x00000000)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_OFF         (26)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_WID         ( 1)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_MSK         (0x04000000)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_MAX         (0x00000001)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_DEF         (0x00000000)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_OFF          (27)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_WID          ( 1)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MSK          (0x08000000)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MAX          (0x00000001)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_DEF          (0x00000000)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_OFF               (28)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_WID               ( 1)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_MSK               (0x10000000)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_MAX               (0x00000001)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_DEF               (0x00000000)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL0_EnReadPreamble_OFF           (29)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL0_EnReadPreamble_WID           ( 1)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL0_EnReadPreamble_MSK           (0x20000000)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL0_EnReadPreamble_MAX           (0x00000001)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL0_EnReadPreamble_DEF           (0x00000000)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_OFF          (30)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_WID          ( 1)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MSK          (0x40000000)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MAX          (0x00000001)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_DEF          (0x00000000)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_OFF             (31)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_WID             ( 1)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_MSK             (0x80000000)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_MAX             (0x00000001)
+  #define DDRDATACH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_DEF             (0x00000000)
+
+#define DDRDATACH0_CR_DDRCRVREFADJUST1_REG                           (0x00003078)
+  #define DDRDATACH0_CR_DDRCRVREFADJUST1_CAVrefCtl_OFF                 ( 0)
+  #define DDRDATACH0_CR_DDRCRVREFADJUST1_CAVrefCtl_WID                 ( 7)
+  #define DDRDATACH0_CR_DDRCRVREFADJUST1_CAVrefCtl_MSK                 (0x0000007F)
+  #define DDRDATACH0_CR_DDRCRVREFADJUST1_CAVrefCtl_MAX                 (0x0000007F)
+  #define DDRDATACH0_CR_DDRCRVREFADJUST1_CAVrefCtl_DEF                 (0x00000000)
+  #define DDRDATACH0_CR_DDRCRVREFADJUST1_Ch1VrefCtl_OFF                ( 7)
+  #define DDRDATACH0_CR_DDRCRVREFADJUST1_Ch1VrefCtl_WID                ( 7)
+  #define DDRDATACH0_CR_DDRCRVREFADJUST1_Ch1VrefCtl_MSK                (0x00003F80)
+  #define DDRDATACH0_CR_DDRCRVREFADJUST1_Ch1VrefCtl_MAX                (0x0000007F)
+  #define DDRDATACH0_CR_DDRCRVREFADJUST1_Ch1VrefCtl_DEF                (0x00000000)
+  #define DDRDATACH0_CR_DDRCRVREFADJUST1_Ch0VrefCtl_OFF                (14)
+  #define DDRDATACH0_CR_DDRCRVREFADJUST1_Ch0VrefCtl_WID                ( 7)
+  #define DDRDATACH0_CR_DDRCRVREFADJUST1_Ch0VrefCtl_MSK                (0x001FC000)
+  #define DDRDATACH0_CR_DDRCRVREFADJUST1_Ch0VrefCtl_MAX                (0x0000007F)
+  #define DDRDATACH0_CR_DDRCRVREFADJUST1_Ch0VrefCtl_DEF                (0x00000000)
+  #define DDRDATACH0_CR_DDRCRVREFADJUST1_EnDimmVrefCA_OFF              (21)
+  #define DDRDATACH0_CR_DDRCRVREFADJUST1_EnDimmVrefCA_WID              ( 1)
+  #define DDRDATACH0_CR_DDRCRVREFADJUST1_EnDimmVrefCA_MSK              (0x00200000)
+  #define DDRDATACH0_CR_DDRCRVREFADJUST1_EnDimmVrefCA_MAX              (0x00000001)
+  #define DDRDATACH0_CR_DDRCRVREFADJUST1_EnDimmVrefCA_DEF              (0x00000000)
+  #define DDRDATACH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_OFF             (22)
+  #define DDRDATACH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_WID             ( 1)
+  #define DDRDATACH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_MSK             (0x00400000)
+  #define DDRDATACH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_MAX             (0x00000001)
+  #define DDRDATACH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_DEF             (0x00000000)
+  #define DDRDATACH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_OFF             (23)
+  #define DDRDATACH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_WID             ( 1)
+  #define DDRDATACH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_MSK             (0x00800000)
+  #define DDRDATACH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_MAX             (0x00000001)
+  #define DDRDATACH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_DEF             (0x00000000)
+  #define DDRDATACH0_CR_DDRCRVREFADJUST1_HiZTimerCtrl_OFF              (24)
+  #define DDRDATACH0_CR_DDRCRVREFADJUST1_HiZTimerCtrl_WID              ( 2)
+  #define DDRDATACH0_CR_DDRCRVREFADJUST1_HiZTimerCtrl_MSK              (0x03000000)
+  #define DDRDATACH0_CR_DDRCRVREFADJUST1_HiZTimerCtrl_MAX              (0x00000003)
+  #define DDRDATACH0_CR_DDRCRVREFADJUST1_HiZTimerCtrl_DEF              (0x00000000)
+  #define DDRDATACH0_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_OFF             (26)
+  #define DDRDATACH0_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_WID             ( 1)
+  #define DDRDATACH0_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_MSK             (0x04000000)
+  #define DDRDATACH0_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_MAX             (0x00000001)
+  #define DDRDATACH0_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_DEF             (0x00000000)
+  #define DDRDATACH0_CR_DDRCRVREFADJUST1_Rsvd_OFF                      (27)
+  #define DDRDATACH0_CR_DDRCRVREFADJUST1_Rsvd_WID                      ( 2)
+  #define DDRDATACH0_CR_DDRCRVREFADJUST1_Rsvd_MSK                      (0x18000000)
+  #define DDRDATACH0_CR_DDRCRVREFADJUST1_Rsvd_MAX                      (0x00000003)
+  #define DDRDATACH0_CR_DDRCRVREFADJUST1_Rsvd_DEF                      (0x00000000)
+  #define DDRDATACH0_CR_DDRCRVREFADJUST1_caSlowBW_OFF                  (29)
+  #define DDRDATACH0_CR_DDRCRVREFADJUST1_caSlowBW_WID                  ( 1)
+  #define DDRDATACH0_CR_DDRCRVREFADJUST1_caSlowBW_MSK                  (0x20000000)
+  #define DDRDATACH0_CR_DDRCRVREFADJUST1_caSlowBW_MAX                  (0x00000001)
+  #define DDRDATACH0_CR_DDRCRVREFADJUST1_caSlowBW_DEF                  (0x00000000)
+  #define DDRDATACH0_CR_DDRCRVREFADJUST1_ch0SlowBW_OFF                 (30)
+  #define DDRDATACH0_CR_DDRCRVREFADJUST1_ch0SlowBW_WID                 ( 1)
+  #define DDRDATACH0_CR_DDRCRVREFADJUST1_ch0SlowBW_MSK                 (0x40000000)
+  #define DDRDATACH0_CR_DDRCRVREFADJUST1_ch0SlowBW_MAX                 (0x00000001)
+  #define DDRDATACH0_CR_DDRCRVREFADJUST1_ch0SlowBW_DEF                 (0x00000000)
+  #define DDRDATACH0_CR_DDRCRVREFADJUST1_ch1SlowBW_OFF                 (31)
+  #define DDRDATACH0_CR_DDRCRVREFADJUST1_ch1SlowBW_WID                 ( 1)
+  #define DDRDATACH0_CR_DDRCRVREFADJUST1_ch1SlowBW_MSK                 (0x80000000)
+  #define DDRDATACH0_CR_DDRCRVREFADJUST1_ch1SlowBW_MAX                 (0x00000001)
+  #define DDRDATACH0_CR_DDRCRVREFADJUST1_ch1SlowBW_DEF                 (0x00000000)
+
+#define DDRDATACH1_CR_RXTRAINRANK0_REG                               (0x00003100)
+  #define DDRDATACH1_CR_RXTRAINRANK0_RxRcvEnPi_OFF                     ( 0)
+  #define DDRDATACH1_CR_RXTRAINRANK0_RxRcvEnPi_WID                     ( 9)
+  #define DDRDATACH1_CR_RXTRAINRANK0_RxRcvEnPi_MSK                     (0x000001FF)
+  #define DDRDATACH1_CR_RXTRAINRANK0_RxRcvEnPi_MAX                     (0x000001FF)
+  #define DDRDATACH1_CR_RXTRAINRANK0_RxDqsPPi_OFF                      ( 9)
+  #define DDRDATACH1_CR_RXTRAINRANK0_RxDqsPPi_WID                      ( 6)
+  #define DDRDATACH1_CR_RXTRAINRANK0_RxDqsPPi_MSK                      (0x00007E00)
+  #define DDRDATACH1_CR_RXTRAINRANK0_RxDqsPPi_MAX                      (0x0000003F)
+  #define DDRDATACH1_CR_RXTRAINRANK0_RxEq_OFF                          (15)
+  #define DDRDATACH1_CR_RXTRAINRANK0_RxEq_WID                          ( 5)
+  #define DDRDATACH1_CR_RXTRAINRANK0_RxEq_MSK                          (0x000F8000)
+  #define DDRDATACH1_CR_RXTRAINRANK0_RxEq_MAX                          (0x0000001F)
+  #define DDRDATACH1_CR_RXTRAINRANK0_RxDqsNPi_OFF                      (20)
+  #define DDRDATACH1_CR_RXTRAINRANK0_RxDqsNPi_WID                      ( 6)
+  #define DDRDATACH1_CR_RXTRAINRANK0_RxDqsNPi_MSK                      (0x03F00000)
+  #define DDRDATACH1_CR_RXTRAINRANK0_RxDqsNPi_MAX                      (0x0000003F)
+  #define DDRDATACH1_CR_RXTRAINRANK0_RxVref_OFF                        (26)
+  #define DDRDATACH1_CR_RXTRAINRANK0_RxVref_WID                        ( 6)
+  #define DDRDATACH1_CR_RXTRAINRANK0_RxVref_MSK                        (0xFC000000)
+  #define DDRDATACH1_CR_RXTRAINRANK0_RxVref_MAX                        (0x0000003F)
+
+#define DDRDATACH1_CR_RXTRAINRANK1_REG                               (0x00003104)
+  #define DDRDATACH1_CR_RXTRAINRANK1_RxRcvEnPi_OFF                     ( 0)
+  #define DDRDATACH1_CR_RXTRAINRANK1_RxRcvEnPi_WID                     ( 9)
+  #define DDRDATACH1_CR_RXTRAINRANK1_RxRcvEnPi_MSK                     (0x000001FF)
+  #define DDRDATACH1_CR_RXTRAINRANK1_RxRcvEnPi_MAX                     (0x000001FF)
+  #define DDRDATACH1_CR_RXTRAINRANK1_RxDqsPPi_OFF                      ( 9)
+  #define DDRDATACH1_CR_RXTRAINRANK1_RxDqsPPi_WID                      ( 6)
+  #define DDRDATACH1_CR_RXTRAINRANK1_RxDqsPPi_MSK                      (0x00007E00)
+  #define DDRDATACH1_CR_RXTRAINRANK1_RxDqsPPi_MAX                      (0x0000003F)
+  #define DDRDATACH1_CR_RXTRAINRANK1_RxEq_OFF                          (15)
+  #define DDRDATACH1_CR_RXTRAINRANK1_RxEq_WID                          ( 5)
+  #define DDRDATACH1_CR_RXTRAINRANK1_RxEq_MSK                          (0x000F8000)
+  #define DDRDATACH1_CR_RXTRAINRANK1_RxEq_MAX                          (0x0000001F)
+  #define DDRDATACH1_CR_RXTRAINRANK1_RxDqsNPi_OFF                      (20)
+  #define DDRDATACH1_CR_RXTRAINRANK1_RxDqsNPi_WID                      ( 6)
+  #define DDRDATACH1_CR_RXTRAINRANK1_RxDqsNPi_MSK                      (0x03F00000)
+  #define DDRDATACH1_CR_RXTRAINRANK1_RxDqsNPi_MAX                      (0x0000003F)
+  #define DDRDATACH1_CR_RXTRAINRANK1_RxVref_OFF                        (26)
+  #define DDRDATACH1_CR_RXTRAINRANK1_RxVref_WID                        ( 6)
+  #define DDRDATACH1_CR_RXTRAINRANK1_RxVref_MSK                        (0xFC000000)
+  #define DDRDATACH1_CR_RXTRAINRANK1_RxVref_MAX                        (0x0000003F)
+
+#define DDRDATACH1_CR_RXTRAINRANK2_REG                               (0x00003108)
+  #define DDRDATACH1_CR_RXTRAINRANK2_RxRcvEnPi_OFF                     ( 0)
+  #define DDRDATACH1_CR_RXTRAINRANK2_RxRcvEnPi_WID                     ( 9)
+  #define DDRDATACH1_CR_RXTRAINRANK2_RxRcvEnPi_MSK                     (0x000001FF)
+  #define DDRDATACH1_CR_RXTRAINRANK2_RxRcvEnPi_MAX                     (0x000001FF)
+  #define DDRDATACH1_CR_RXTRAINRANK2_RxDqsPPi_OFF                      ( 9)
+  #define DDRDATACH1_CR_RXTRAINRANK2_RxDqsPPi_WID                      ( 6)
+  #define DDRDATACH1_CR_RXTRAINRANK2_RxDqsPPi_MSK                      (0x00007E00)
+  #define DDRDATACH1_CR_RXTRAINRANK2_RxDqsPPi_MAX                      (0x0000003F)
+  #define DDRDATACH1_CR_RXTRAINRANK2_RxEq_OFF                          (15)
+  #define DDRDATACH1_CR_RXTRAINRANK2_RxEq_WID                          ( 5)
+  #define DDRDATACH1_CR_RXTRAINRANK2_RxEq_MSK                          (0x000F8000)
+  #define DDRDATACH1_CR_RXTRAINRANK2_RxEq_MAX                          (0x0000001F)
+  #define DDRDATACH1_CR_RXTRAINRANK2_RxDqsNPi_OFF                      (20)
+  #define DDRDATACH1_CR_RXTRAINRANK2_RxDqsNPi_WID                      ( 6)
+  #define DDRDATACH1_CR_RXTRAINRANK2_RxDqsNPi_MSK                      (0x03F00000)
+  #define DDRDATACH1_CR_RXTRAINRANK2_RxDqsNPi_MAX                      (0x0000003F)
+  #define DDRDATACH1_CR_RXTRAINRANK2_RxVref_OFF                        (26)
+  #define DDRDATACH1_CR_RXTRAINRANK2_RxVref_WID                        ( 6)
+  #define DDRDATACH1_CR_RXTRAINRANK2_RxVref_MSK                        (0xFC000000)
+  #define DDRDATACH1_CR_RXTRAINRANK2_RxVref_MAX                        (0x0000003F)
+
+#define DDRDATACH1_CR_RXTRAINRANK3_REG                               (0x0000310C)
+  #define DDRDATACH1_CR_RXTRAINRANK3_RxRcvEnPi_OFF                     ( 0)
+  #define DDRDATACH1_CR_RXTRAINRANK3_RxRcvEnPi_WID                     ( 9)
+  #define DDRDATACH1_CR_RXTRAINRANK3_RxRcvEnPi_MSK                     (0x000001FF)
+  #define DDRDATACH1_CR_RXTRAINRANK3_RxRcvEnPi_MAX                     (0x000001FF)
+  #define DDRDATACH1_CR_RXTRAINRANK3_RxDqsPPi_OFF                      ( 9)
+  #define DDRDATACH1_CR_RXTRAINRANK3_RxDqsPPi_WID                      ( 6)
+  #define DDRDATACH1_CR_RXTRAINRANK3_RxDqsPPi_MSK                      (0x00007E00)
+  #define DDRDATACH1_CR_RXTRAINRANK3_RxDqsPPi_MAX                      (0x0000003F)
+  #define DDRDATACH1_CR_RXTRAINRANK3_RxEq_OFF                          (15)
+  #define DDRDATACH1_CR_RXTRAINRANK3_RxEq_WID                          ( 5)
+  #define DDRDATACH1_CR_RXTRAINRANK3_RxEq_MSK                          (0x000F8000)
+  #define DDRDATACH1_CR_RXTRAINRANK3_RxEq_MAX                          (0x0000001F)
+  #define DDRDATACH1_CR_RXTRAINRANK3_RxDqsNPi_OFF                      (20)
+  #define DDRDATACH1_CR_RXTRAINRANK3_RxDqsNPi_WID                      ( 6)
+  #define DDRDATACH1_CR_RXTRAINRANK3_RxDqsNPi_MSK                      (0x03F00000)
+  #define DDRDATACH1_CR_RXTRAINRANK3_RxDqsNPi_MAX                      (0x0000003F)
+  #define DDRDATACH1_CR_RXTRAINRANK3_RxVref_OFF                        (26)
+  #define DDRDATACH1_CR_RXTRAINRANK3_RxVref_WID                        ( 6)
+  #define DDRDATACH1_CR_RXTRAINRANK3_RxVref_MSK                        (0xFC000000)
+  #define DDRDATACH1_CR_RXTRAINRANK3_RxVref_MAX                        (0x0000003F)
+
+#define DDRDATACH1_CR_RXPERBITRANK0_REG                              (0x00003110)
+  #define DDRDATACH1_CR_RXPERBITRANK0_Lane0_OFF                        ( 0)
+  #define DDRDATACH1_CR_RXPERBITRANK0_Lane0_WID                        ( 4)
+  #define DDRDATACH1_CR_RXPERBITRANK0_Lane0_MSK                        (0x0000000F)
+  #define DDRDATACH1_CR_RXPERBITRANK0_Lane0_MAX                        (0x0000000F)
+  #define DDRDATACH1_CR_RXPERBITRANK0_Lane1_OFF                        ( 4)
+  #define DDRDATACH1_CR_RXPERBITRANK0_Lane1_WID                        ( 4)
+  #define DDRDATACH1_CR_RXPERBITRANK0_Lane1_MSK                        (0x000000F0)
+  #define DDRDATACH1_CR_RXPERBITRANK0_Lane1_MAX                        (0x0000000F)
+  #define DDRDATACH1_CR_RXPERBITRANK0_Lane2_OFF                        ( 8)
+  #define DDRDATACH1_CR_RXPERBITRANK0_Lane2_WID                        ( 4)
+  #define DDRDATACH1_CR_RXPERBITRANK0_Lane2_MSK                        (0x00000F00)
+  #define DDRDATACH1_CR_RXPERBITRANK0_Lane2_MAX                        (0x0000000F)
+  #define DDRDATACH1_CR_RXPERBITRANK0_Lane3_OFF                        (12)
+  #define DDRDATACH1_CR_RXPERBITRANK0_Lane3_WID                        ( 4)
+  #define DDRDATACH1_CR_RXPERBITRANK0_Lane3_MSK                        (0x0000F000)
+  #define DDRDATACH1_CR_RXPERBITRANK0_Lane3_MAX                        (0x0000000F)
+  #define DDRDATACH1_CR_RXPERBITRANK0_Lane4_OFF                        (16)
+  #define DDRDATACH1_CR_RXPERBITRANK0_Lane4_WID                        ( 4)
+  #define DDRDATACH1_CR_RXPERBITRANK0_Lane4_MSK                        (0x000F0000)
+  #define DDRDATACH1_CR_RXPERBITRANK0_Lane4_MAX                        (0x0000000F)
+  #define DDRDATACH1_CR_RXPERBITRANK0_Lane5_OFF                        (20)
+  #define DDRDATACH1_CR_RXPERBITRANK0_Lane5_WID                        ( 4)
+  #define DDRDATACH1_CR_RXPERBITRANK0_Lane5_MSK                        (0x00F00000)
+  #define DDRDATACH1_CR_RXPERBITRANK0_Lane5_MAX                        (0x0000000F)
+  #define DDRDATACH1_CR_RXPERBITRANK0_Lane6_OFF                        (24)
+  #define DDRDATACH1_CR_RXPERBITRANK0_Lane6_WID                        ( 4)
+  #define DDRDATACH1_CR_RXPERBITRANK0_Lane6_MSK                        (0x0F000000)
+  #define DDRDATACH1_CR_RXPERBITRANK0_Lane6_MAX                        (0x0000000F)
+  #define DDRDATACH1_CR_RXPERBITRANK0_Lane7_OFF                        (28)
+  #define DDRDATACH1_CR_RXPERBITRANK0_Lane7_WID                        ( 4)
+  #define DDRDATACH1_CR_RXPERBITRANK0_Lane7_MSK                        (0xF0000000)
+  #define DDRDATACH1_CR_RXPERBITRANK0_Lane7_MAX                        (0x0000000F)
+
+#define DDRDATACH1_CR_RXPERBITRANK1_REG                              (0x00003114)
+  #define DDRDATACH1_CR_RXPERBITRANK1_Lane0_OFF                        ( 0)
+  #define DDRDATACH1_CR_RXPERBITRANK1_Lane0_WID                        ( 4)
+  #define DDRDATACH1_CR_RXPERBITRANK1_Lane0_MSK                        (0x0000000F)
+  #define DDRDATACH1_CR_RXPERBITRANK1_Lane0_MAX                        (0x0000000F)
+  #define DDRDATACH1_CR_RXPERBITRANK1_Lane1_OFF                        ( 4)
+  #define DDRDATACH1_CR_RXPERBITRANK1_Lane1_WID                        ( 4)
+  #define DDRDATACH1_CR_RXPERBITRANK1_Lane1_MSK                        (0x000000F0)
+  #define DDRDATACH1_CR_RXPERBITRANK1_Lane1_MAX                        (0x0000000F)
+  #define DDRDATACH1_CR_RXPERBITRANK1_Lane2_OFF                        ( 8)
+  #define DDRDATACH1_CR_RXPERBITRANK1_Lane2_WID                        ( 4)
+  #define DDRDATACH1_CR_RXPERBITRANK1_Lane2_MSK                        (0x00000F00)
+  #define DDRDATACH1_CR_RXPERBITRANK1_Lane2_MAX                        (0x0000000F)
+  #define DDRDATACH1_CR_RXPERBITRANK1_Lane3_OFF                        (12)
+  #define DDRDATACH1_CR_RXPERBITRANK1_Lane3_WID                        ( 4)
+  #define DDRDATACH1_CR_RXPERBITRANK1_Lane3_MSK                        (0x0000F000)
+  #define DDRDATACH1_CR_RXPERBITRANK1_Lane3_MAX                        (0x0000000F)
+  #define DDRDATACH1_CR_RXPERBITRANK1_Lane4_OFF                        (16)
+  #define DDRDATACH1_CR_RXPERBITRANK1_Lane4_WID                        ( 4)
+  #define DDRDATACH1_CR_RXPERBITRANK1_Lane4_MSK                        (0x000F0000)
+  #define DDRDATACH1_CR_RXPERBITRANK1_Lane4_MAX                        (0x0000000F)
+  #define DDRDATACH1_CR_RXPERBITRANK1_Lane5_OFF                        (20)
+  #define DDRDATACH1_CR_RXPERBITRANK1_Lane5_WID                        ( 4)
+  #define DDRDATACH1_CR_RXPERBITRANK1_Lane5_MSK                        (0x00F00000)
+  #define DDRDATACH1_CR_RXPERBITRANK1_Lane5_MAX                        (0x0000000F)
+  #define DDRDATACH1_CR_RXPERBITRANK1_Lane6_OFF                        (24)
+  #define DDRDATACH1_CR_RXPERBITRANK1_Lane6_WID                        ( 4)
+  #define DDRDATACH1_CR_RXPERBITRANK1_Lane6_MSK                        (0x0F000000)
+  #define DDRDATACH1_CR_RXPERBITRANK1_Lane6_MAX                        (0x0000000F)
+  #define DDRDATACH1_CR_RXPERBITRANK1_Lane7_OFF                        (28)
+  #define DDRDATACH1_CR_RXPERBITRANK1_Lane7_WID                        ( 4)
+  #define DDRDATACH1_CR_RXPERBITRANK1_Lane7_MSK                        (0xF0000000)
+  #define DDRDATACH1_CR_RXPERBITRANK1_Lane7_MAX                        (0x0000000F)
+
+#define DDRDATACH1_CR_RXPERBITRANK2_REG                              (0x00003118)
+  #define DDRDATACH1_CR_RXPERBITRANK2_Lane0_OFF                        ( 0)
+  #define DDRDATACH1_CR_RXPERBITRANK2_Lane0_WID                        ( 4)
+  #define DDRDATACH1_CR_RXPERBITRANK2_Lane0_MSK                        (0x0000000F)
+  #define DDRDATACH1_CR_RXPERBITRANK2_Lane0_MAX                        (0x0000000F)
+  #define DDRDATACH1_CR_RXPERBITRANK2_Lane1_OFF                        ( 4)
+  #define DDRDATACH1_CR_RXPERBITRANK2_Lane1_WID                        ( 4)
+  #define DDRDATACH1_CR_RXPERBITRANK2_Lane1_MSK                        (0x000000F0)
+  #define DDRDATACH1_CR_RXPERBITRANK2_Lane1_MAX                        (0x0000000F)
+  #define DDRDATACH1_CR_RXPERBITRANK2_Lane2_OFF                        ( 8)
+  #define DDRDATACH1_CR_RXPERBITRANK2_Lane2_WID                        ( 4)
+  #define DDRDATACH1_CR_RXPERBITRANK2_Lane2_MSK                        (0x00000F00)
+  #define DDRDATACH1_CR_RXPERBITRANK2_Lane2_MAX                        (0x0000000F)
+  #define DDRDATACH1_CR_RXPERBITRANK2_Lane3_OFF                        (12)
+  #define DDRDATACH1_CR_RXPERBITRANK2_Lane3_WID                        ( 4)
+  #define DDRDATACH1_CR_RXPERBITRANK2_Lane3_MSK                        (0x0000F000)
+  #define DDRDATACH1_CR_RXPERBITRANK2_Lane3_MAX                        (0x0000000F)
+  #define DDRDATACH1_CR_RXPERBITRANK2_Lane4_OFF                        (16)
+  #define DDRDATACH1_CR_RXPERBITRANK2_Lane4_WID                        ( 4)
+  #define DDRDATACH1_CR_RXPERBITRANK2_Lane4_MSK                        (0x000F0000)
+  #define DDRDATACH1_CR_RXPERBITRANK2_Lane4_MAX                        (0x0000000F)
+  #define DDRDATACH1_CR_RXPERBITRANK2_Lane5_OFF                        (20)
+  #define DDRDATACH1_CR_RXPERBITRANK2_Lane5_WID                        ( 4)
+  #define DDRDATACH1_CR_RXPERBITRANK2_Lane5_MSK                        (0x00F00000)
+  #define DDRDATACH1_CR_RXPERBITRANK2_Lane5_MAX                        (0x0000000F)
+  #define DDRDATACH1_CR_RXPERBITRANK2_Lane6_OFF                        (24)
+  #define DDRDATACH1_CR_RXPERBITRANK2_Lane6_WID                        ( 4)
+  #define DDRDATACH1_CR_RXPERBITRANK2_Lane6_MSK                        (0x0F000000)
+  #define DDRDATACH1_CR_RXPERBITRANK2_Lane6_MAX                        (0x0000000F)
+  #define DDRDATACH1_CR_RXPERBITRANK2_Lane7_OFF                        (28)
+  #define DDRDATACH1_CR_RXPERBITRANK2_Lane7_WID                        ( 4)
+  #define DDRDATACH1_CR_RXPERBITRANK2_Lane7_MSK                        (0xF0000000)
+  #define DDRDATACH1_CR_RXPERBITRANK2_Lane7_MAX                        (0x0000000F)
+
+#define DDRDATACH1_CR_RXPERBITRANK3_REG                              (0x0000311C)
+  #define DDRDATACH1_CR_RXPERBITRANK3_Lane0_OFF                        ( 0)
+  #define DDRDATACH1_CR_RXPERBITRANK3_Lane0_WID                        ( 4)
+  #define DDRDATACH1_CR_RXPERBITRANK3_Lane0_MSK                        (0x0000000F)
+  #define DDRDATACH1_CR_RXPERBITRANK3_Lane0_MAX                        (0x0000000F)
+  #define DDRDATACH1_CR_RXPERBITRANK3_Lane1_OFF                        ( 4)
+  #define DDRDATACH1_CR_RXPERBITRANK3_Lane1_WID                        ( 4)
+  #define DDRDATACH1_CR_RXPERBITRANK3_Lane1_MSK                        (0x000000F0)
+  #define DDRDATACH1_CR_RXPERBITRANK3_Lane1_MAX                        (0x0000000F)
+  #define DDRDATACH1_CR_RXPERBITRANK3_Lane2_OFF                        ( 8)
+  #define DDRDATACH1_CR_RXPERBITRANK3_Lane2_WID                        ( 4)
+  #define DDRDATACH1_CR_RXPERBITRANK3_Lane2_MSK                        (0x00000F00)
+  #define DDRDATACH1_CR_RXPERBITRANK3_Lane2_MAX                        (0x0000000F)
+  #define DDRDATACH1_CR_RXPERBITRANK3_Lane3_OFF                        (12)
+  #define DDRDATACH1_CR_RXPERBITRANK3_Lane3_WID                        ( 4)
+  #define DDRDATACH1_CR_RXPERBITRANK3_Lane3_MSK                        (0x0000F000)
+  #define DDRDATACH1_CR_RXPERBITRANK3_Lane3_MAX                        (0x0000000F)
+  #define DDRDATACH1_CR_RXPERBITRANK3_Lane4_OFF                        (16)
+  #define DDRDATACH1_CR_RXPERBITRANK3_Lane4_WID                        ( 4)
+  #define DDRDATACH1_CR_RXPERBITRANK3_Lane4_MSK                        (0x000F0000)
+  #define DDRDATACH1_CR_RXPERBITRANK3_Lane4_MAX                        (0x0000000F)
+  #define DDRDATACH1_CR_RXPERBITRANK3_Lane5_OFF                        (20)
+  #define DDRDATACH1_CR_RXPERBITRANK3_Lane5_WID                        ( 4)
+  #define DDRDATACH1_CR_RXPERBITRANK3_Lane5_MSK                        (0x00F00000)
+  #define DDRDATACH1_CR_RXPERBITRANK3_Lane5_MAX                        (0x0000000F)
+  #define DDRDATACH1_CR_RXPERBITRANK3_Lane6_OFF                        (24)
+  #define DDRDATACH1_CR_RXPERBITRANK3_Lane6_WID                        ( 4)
+  #define DDRDATACH1_CR_RXPERBITRANK3_Lane6_MSK                        (0x0F000000)
+  #define DDRDATACH1_CR_RXPERBITRANK3_Lane6_MAX                        (0x0000000F)
+  #define DDRDATACH1_CR_RXPERBITRANK3_Lane7_OFF                        (28)
+  #define DDRDATACH1_CR_RXPERBITRANK3_Lane7_WID                        ( 4)
+  #define DDRDATACH1_CR_RXPERBITRANK3_Lane7_MSK                        (0xF0000000)
+  #define DDRDATACH1_CR_RXPERBITRANK3_Lane7_MAX                        (0x0000000F)
+
+#define DDRDATACH1_CR_TXTRAINRANK0_REG                               (0x00003120)
+  #define DDRDATACH1_CR_TXTRAINRANK0_TxDqDelay_OFF                     ( 0)
+  #define DDRDATACH1_CR_TXTRAINRANK0_TxDqDelay_WID                     ( 9)
+  #define DDRDATACH1_CR_TXTRAINRANK0_TxDqDelay_MSK                     (0x000001FF)
+  #define DDRDATACH1_CR_TXTRAINRANK0_TxDqDelay_MAX                     (0x000001FF)
+  #define DDRDATACH1_CR_TXTRAINRANK0_TxDqsDelay_OFF                    ( 9)
+  #define DDRDATACH1_CR_TXTRAINRANK0_TxDqsDelay_WID                    ( 9)
+  #define DDRDATACH1_CR_TXTRAINRANK0_TxDqsDelay_MSK                    (0x0003FE00)
+  #define DDRDATACH1_CR_TXTRAINRANK0_TxDqsDelay_MAX                    (0x000001FF)
+  #define DDRDATACH1_CR_TXTRAINRANK0_Spare0_OFF                        (18)
+  #define DDRDATACH1_CR_TXTRAINRANK0_Spare0_WID                        ( 2)
+  #define DDRDATACH1_CR_TXTRAINRANK0_Spare0_MSK                        (0x000C0000)
+  #define DDRDATACH1_CR_TXTRAINRANK0_Spare0_MAX                        (0x00000003)
+  #define DDRDATACH1_CR_TXTRAINRANK0_TxEqualization_OFF                (20)
+  #define DDRDATACH1_CR_TXTRAINRANK0_TxEqualization_WID                ( 6)
+  #define DDRDATACH1_CR_TXTRAINRANK0_TxEqualization_MSK                (0x03F00000)
+  #define DDRDATACH1_CR_TXTRAINRANK0_TxEqualization_MAX                (0x0000003F)
+  #define DDRDATACH1_CR_TXTRAINRANK0_Spare1_OFF                        (26)
+  #define DDRDATACH1_CR_TXTRAINRANK0_Spare1_WID                        ( 6)
+  #define DDRDATACH1_CR_TXTRAINRANK0_Spare1_MSK                        (0xFC000000)
+  #define DDRDATACH1_CR_TXTRAINRANK0_Spare1_MAX                        (0x0000003F)
+
+#define DDRDATACH1_CR_TXTRAINRANK1_REG                               (0x00003124)
+  #define DDRDATACH1_CR_TXTRAINRANK1_TxDqDelay_OFF                     ( 0)
+  #define DDRDATACH1_CR_TXTRAINRANK1_TxDqDelay_WID                     ( 9)
+  #define DDRDATACH1_CR_TXTRAINRANK1_TxDqDelay_MSK                     (0x000001FF)
+  #define DDRDATACH1_CR_TXTRAINRANK1_TxDqDelay_MAX                     (0x000001FF)
+  #define DDRDATACH1_CR_TXTRAINRANK1_TxDqsDelay_OFF                    ( 9)
+  #define DDRDATACH1_CR_TXTRAINRANK1_TxDqsDelay_WID                    ( 9)
+  #define DDRDATACH1_CR_TXTRAINRANK1_TxDqsDelay_MSK                    (0x0003FE00)
+  #define DDRDATACH1_CR_TXTRAINRANK1_TxDqsDelay_MAX                    (0x000001FF)
+  #define DDRDATACH1_CR_TXTRAINRANK1_Spare0_OFF                        (18)
+  #define DDRDATACH1_CR_TXTRAINRANK1_Spare0_WID                        ( 2)
+  #define DDRDATACH1_CR_TXTRAINRANK1_Spare0_MSK                        (0x000C0000)
+  #define DDRDATACH1_CR_TXTRAINRANK1_Spare0_MAX                        (0x00000003)
+  #define DDRDATACH1_CR_TXTRAINRANK1_TxEqualization_OFF                (20)
+  #define DDRDATACH1_CR_TXTRAINRANK1_TxEqualization_WID                ( 6)
+  #define DDRDATACH1_CR_TXTRAINRANK1_TxEqualization_MSK                (0x03F00000)
+  #define DDRDATACH1_CR_TXTRAINRANK1_TxEqualization_MAX                (0x0000003F)
+  #define DDRDATACH1_CR_TXTRAINRANK1_Spare1_OFF                        (26)
+  #define DDRDATACH1_CR_TXTRAINRANK1_Spare1_WID                        ( 6)
+  #define DDRDATACH1_CR_TXTRAINRANK1_Spare1_MSK                        (0xFC000000)
+  #define DDRDATACH1_CR_TXTRAINRANK1_Spare1_MAX                        (0x0000003F)
+
+#define DDRDATACH1_CR_TXTRAINRANK2_REG                               (0x00003128)
+  #define DDRDATACH1_CR_TXTRAINRANK2_TxDqDelay_OFF                     ( 0)
+  #define DDRDATACH1_CR_TXTRAINRANK2_TxDqDelay_WID                     ( 9)
+  #define DDRDATACH1_CR_TXTRAINRANK2_TxDqDelay_MSK                     (0x000001FF)
+  #define DDRDATACH1_CR_TXTRAINRANK2_TxDqDelay_MAX                     (0x000001FF)
+  #define DDRDATACH1_CR_TXTRAINRANK2_TxDqsDelay_OFF                    ( 9)
+  #define DDRDATACH1_CR_TXTRAINRANK2_TxDqsDelay_WID                    ( 9)
+  #define DDRDATACH1_CR_TXTRAINRANK2_TxDqsDelay_MSK                    (0x0003FE00)
+  #define DDRDATACH1_CR_TXTRAINRANK2_TxDqsDelay_MAX                    (0x000001FF)
+  #define DDRDATACH1_CR_TXTRAINRANK2_Spare0_OFF                        (18)
+  #define DDRDATACH1_CR_TXTRAINRANK2_Spare0_WID                        ( 2)
+  #define DDRDATACH1_CR_TXTRAINRANK2_Spare0_MSK                        (0x000C0000)
+  #define DDRDATACH1_CR_TXTRAINRANK2_Spare0_MAX                        (0x00000003)
+  #define DDRDATACH1_CR_TXTRAINRANK2_TxEqualization_OFF                (20)
+  #define DDRDATACH1_CR_TXTRAINRANK2_TxEqualization_WID                ( 6)
+  #define DDRDATACH1_CR_TXTRAINRANK2_TxEqualization_MSK                (0x03F00000)
+  #define DDRDATACH1_CR_TXTRAINRANK2_TxEqualization_MAX                (0x0000003F)
+  #define DDRDATACH1_CR_TXTRAINRANK2_Spare1_OFF                        (26)
+  #define DDRDATACH1_CR_TXTRAINRANK2_Spare1_WID                        ( 6)
+  #define DDRDATACH1_CR_TXTRAINRANK2_Spare1_MSK                        (0xFC000000)
+  #define DDRDATACH1_CR_TXTRAINRANK2_Spare1_MAX                        (0x0000003F)
+
+#define DDRDATACH1_CR_TXTRAINRANK3_REG                               (0x0000312C)
+  #define DDRDATACH1_CR_TXTRAINRANK3_TxDqDelay_OFF                     ( 0)
+  #define DDRDATACH1_CR_TXTRAINRANK3_TxDqDelay_WID                     ( 9)
+  #define DDRDATACH1_CR_TXTRAINRANK3_TxDqDelay_MSK                     (0x000001FF)
+  #define DDRDATACH1_CR_TXTRAINRANK3_TxDqDelay_MAX                     (0x000001FF)
+  #define DDRDATACH1_CR_TXTRAINRANK3_TxDqsDelay_OFF                    ( 9)
+  #define DDRDATACH1_CR_TXTRAINRANK3_TxDqsDelay_WID                    ( 9)
+  #define DDRDATACH1_CR_TXTRAINRANK3_TxDqsDelay_MSK                    (0x0003FE00)
+  #define DDRDATACH1_CR_TXTRAINRANK3_TxDqsDelay_MAX                    (0x000001FF)
+  #define DDRDATACH1_CR_TXTRAINRANK3_Spare0_OFF                        (18)
+  #define DDRDATACH1_CR_TXTRAINRANK3_Spare0_WID                        ( 2)
+  #define DDRDATACH1_CR_TXTRAINRANK3_Spare0_MSK                        (0x000C0000)
+  #define DDRDATACH1_CR_TXTRAINRANK3_Spare0_MAX                        (0x00000003)
+  #define DDRDATACH1_CR_TXTRAINRANK3_TxEqualization_OFF                (20)
+  #define DDRDATACH1_CR_TXTRAINRANK3_TxEqualization_WID                ( 6)
+  #define DDRDATACH1_CR_TXTRAINRANK3_TxEqualization_MSK                (0x03F00000)
+  #define DDRDATACH1_CR_TXTRAINRANK3_TxEqualization_MAX                (0x0000003F)
+  #define DDRDATACH1_CR_TXTRAINRANK3_Spare1_OFF                        (26)
+  #define DDRDATACH1_CR_TXTRAINRANK3_Spare1_WID                        ( 6)
+  #define DDRDATACH1_CR_TXTRAINRANK3_Spare1_MSK                        (0xFC000000)
+  #define DDRDATACH1_CR_TXTRAINRANK3_Spare1_MAX                        (0x0000003F)
+
+#define DDRDATACH1_CR_TXPERBITRANK0_REG                              (0x00003130)
+  #define DDRDATACH1_CR_TXPERBITRANK0_Lane0_OFF                        ( 0)
+  #define DDRDATACH1_CR_TXPERBITRANK0_Lane0_WID                        ( 4)
+  #define DDRDATACH1_CR_TXPERBITRANK0_Lane0_MSK                        (0x0000000F)
+  #define DDRDATACH1_CR_TXPERBITRANK0_Lane0_MAX                        (0x0000000F)
+  #define DDRDATACH1_CR_TXPERBITRANK0_Lane1_OFF                        ( 4)
+  #define DDRDATACH1_CR_TXPERBITRANK0_Lane1_WID                        ( 4)
+  #define DDRDATACH1_CR_TXPERBITRANK0_Lane1_MSK                        (0x000000F0)
+  #define DDRDATACH1_CR_TXPERBITRANK0_Lane1_MAX                        (0x0000000F)
+  #define DDRDATACH1_CR_TXPERBITRANK0_Lane2_OFF                        ( 8)
+  #define DDRDATACH1_CR_TXPERBITRANK0_Lane2_WID                        ( 4)
+  #define DDRDATACH1_CR_TXPERBITRANK0_Lane2_MSK                        (0x00000F00)
+  #define DDRDATACH1_CR_TXPERBITRANK0_Lane2_MAX                        (0x0000000F)
+  #define DDRDATACH1_CR_TXPERBITRANK0_Lane3_OFF                        (12)
+  #define DDRDATACH1_CR_TXPERBITRANK0_Lane3_WID                        ( 4)
+  #define DDRDATACH1_CR_TXPERBITRANK0_Lane3_MSK                        (0x0000F000)
+  #define DDRDATACH1_CR_TXPERBITRANK0_Lane3_MAX                        (0x0000000F)
+  #define DDRDATACH1_CR_TXPERBITRANK0_Lane4_OFF                        (16)
+  #define DDRDATACH1_CR_TXPERBITRANK0_Lane4_WID                        ( 4)
+  #define DDRDATACH1_CR_TXPERBITRANK0_Lane4_MSK                        (0x000F0000)
+  #define DDRDATACH1_CR_TXPERBITRANK0_Lane4_MAX                        (0x0000000F)
+  #define DDRDATACH1_CR_TXPERBITRANK0_Lane5_OFF                        (20)
+  #define DDRDATACH1_CR_TXPERBITRANK0_Lane5_WID                        ( 4)
+  #define DDRDATACH1_CR_TXPERBITRANK0_Lane5_MSK                        (0x00F00000)
+  #define DDRDATACH1_CR_TXPERBITRANK0_Lane5_MAX                        (0x0000000F)
+  #define DDRDATACH1_CR_TXPERBITRANK0_Lane6_OFF                        (24)
+  #define DDRDATACH1_CR_TXPERBITRANK0_Lane6_WID                        ( 4)
+  #define DDRDATACH1_CR_TXPERBITRANK0_Lane6_MSK                        (0x0F000000)
+  #define DDRDATACH1_CR_TXPERBITRANK0_Lane6_MAX                        (0x0000000F)
+  #define DDRDATACH1_CR_TXPERBITRANK0_Lane7_OFF                        (28)
+  #define DDRDATACH1_CR_TXPERBITRANK0_Lane7_WID                        ( 4)
+  #define DDRDATACH1_CR_TXPERBITRANK0_Lane7_MSK                        (0xF0000000)
+  #define DDRDATACH1_CR_TXPERBITRANK0_Lane7_MAX                        (0x0000000F)
+
+#define DDRDATACH1_CR_TXPERBITRANK1_REG                              (0x00003134)
+  #define DDRDATACH1_CR_TXPERBITRANK1_Lane0_OFF                        ( 0)
+  #define DDRDATACH1_CR_TXPERBITRANK1_Lane0_WID                        ( 4)
+  #define DDRDATACH1_CR_TXPERBITRANK1_Lane0_MSK                        (0x0000000F)
+  #define DDRDATACH1_CR_TXPERBITRANK1_Lane0_MAX                        (0x0000000F)
+  #define DDRDATACH1_CR_TXPERBITRANK1_Lane1_OFF                        ( 4)
+  #define DDRDATACH1_CR_TXPERBITRANK1_Lane1_WID                        ( 4)
+  #define DDRDATACH1_CR_TXPERBITRANK1_Lane1_MSK                        (0x000000F0)
+  #define DDRDATACH1_CR_TXPERBITRANK1_Lane1_MAX                        (0x0000000F)
+  #define DDRDATACH1_CR_TXPERBITRANK1_Lane2_OFF                        ( 8)
+  #define DDRDATACH1_CR_TXPERBITRANK1_Lane2_WID                        ( 4)
+  #define DDRDATACH1_CR_TXPERBITRANK1_Lane2_MSK                        (0x00000F00)
+  #define DDRDATACH1_CR_TXPERBITRANK1_Lane2_MAX                        (0x0000000F)
+  #define DDRDATACH1_CR_TXPERBITRANK1_Lane3_OFF                        (12)
+  #define DDRDATACH1_CR_TXPERBITRANK1_Lane3_WID                        ( 4)
+  #define DDRDATACH1_CR_TXPERBITRANK1_Lane3_MSK                        (0x0000F000)
+  #define DDRDATACH1_CR_TXPERBITRANK1_Lane3_MAX                        (0x0000000F)
+  #define DDRDATACH1_CR_TXPERBITRANK1_Lane4_OFF                        (16)
+  #define DDRDATACH1_CR_TXPERBITRANK1_Lane4_WID                        ( 4)
+  #define DDRDATACH1_CR_TXPERBITRANK1_Lane4_MSK                        (0x000F0000)
+  #define DDRDATACH1_CR_TXPERBITRANK1_Lane4_MAX                        (0x0000000F)
+  #define DDRDATACH1_CR_TXPERBITRANK1_Lane5_OFF                        (20)
+  #define DDRDATACH1_CR_TXPERBITRANK1_Lane5_WID                        ( 4)
+  #define DDRDATACH1_CR_TXPERBITRANK1_Lane5_MSK                        (0x00F00000)
+  #define DDRDATACH1_CR_TXPERBITRANK1_Lane5_MAX                        (0x0000000F)
+  #define DDRDATACH1_CR_TXPERBITRANK1_Lane6_OFF                        (24)
+  #define DDRDATACH1_CR_TXPERBITRANK1_Lane6_WID                        ( 4)
+  #define DDRDATACH1_CR_TXPERBITRANK1_Lane6_MSK                        (0x0F000000)
+  #define DDRDATACH1_CR_TXPERBITRANK1_Lane6_MAX                        (0x0000000F)
+  #define DDRDATACH1_CR_TXPERBITRANK1_Lane7_OFF                        (28)
+  #define DDRDATACH1_CR_TXPERBITRANK1_Lane7_WID                        ( 4)
+  #define DDRDATACH1_CR_TXPERBITRANK1_Lane7_MSK                        (0xF0000000)
+  #define DDRDATACH1_CR_TXPERBITRANK1_Lane7_MAX                        (0x0000000F)
+
+#define DDRDATACH1_CR_TXPERBITRANK2_REG                              (0x00003138)
+  #define DDRDATACH1_CR_TXPERBITRANK2_Lane0_OFF                        ( 0)
+  #define DDRDATACH1_CR_TXPERBITRANK2_Lane0_WID                        ( 4)
+  #define DDRDATACH1_CR_TXPERBITRANK2_Lane0_MSK                        (0x0000000F)
+  #define DDRDATACH1_CR_TXPERBITRANK2_Lane0_MAX                        (0x0000000F)
+  #define DDRDATACH1_CR_TXPERBITRANK2_Lane1_OFF                        ( 4)
+  #define DDRDATACH1_CR_TXPERBITRANK2_Lane1_WID                        ( 4)
+  #define DDRDATACH1_CR_TXPERBITRANK2_Lane1_MSK                        (0x000000F0)
+  #define DDRDATACH1_CR_TXPERBITRANK2_Lane1_MAX                        (0x0000000F)
+  #define DDRDATACH1_CR_TXPERBITRANK2_Lane2_OFF                        ( 8)
+  #define DDRDATACH1_CR_TXPERBITRANK2_Lane2_WID                        ( 4)
+  #define DDRDATACH1_CR_TXPERBITRANK2_Lane2_MSK                        (0x00000F00)
+  #define DDRDATACH1_CR_TXPERBITRANK2_Lane2_MAX                        (0x0000000F)
+  #define DDRDATACH1_CR_TXPERBITRANK2_Lane3_OFF                        (12)
+  #define DDRDATACH1_CR_TXPERBITRANK2_Lane3_WID                        ( 4)
+  #define DDRDATACH1_CR_TXPERBITRANK2_Lane3_MSK                        (0x0000F000)
+  #define DDRDATACH1_CR_TXPERBITRANK2_Lane3_MAX                        (0x0000000F)
+  #define DDRDATACH1_CR_TXPERBITRANK2_Lane4_OFF                        (16)
+  #define DDRDATACH1_CR_TXPERBITRANK2_Lane4_WID                        ( 4)
+  #define DDRDATACH1_CR_TXPERBITRANK2_Lane4_MSK                        (0x000F0000)
+  #define DDRDATACH1_CR_TXPERBITRANK2_Lane4_MAX                        (0x0000000F)
+  #define DDRDATACH1_CR_TXPERBITRANK2_Lane5_OFF                        (20)
+  #define DDRDATACH1_CR_TXPERBITRANK2_Lane5_WID                        ( 4)
+  #define DDRDATACH1_CR_TXPERBITRANK2_Lane5_MSK                        (0x00F00000)
+  #define DDRDATACH1_CR_TXPERBITRANK2_Lane5_MAX                        (0x0000000F)
+  #define DDRDATACH1_CR_TXPERBITRANK2_Lane6_OFF                        (24)
+  #define DDRDATACH1_CR_TXPERBITRANK2_Lane6_WID                        ( 4)
+  #define DDRDATACH1_CR_TXPERBITRANK2_Lane6_MSK                        (0x0F000000)
+  #define DDRDATACH1_CR_TXPERBITRANK2_Lane6_MAX                        (0x0000000F)
+  #define DDRDATACH1_CR_TXPERBITRANK2_Lane7_OFF                        (28)
+  #define DDRDATACH1_CR_TXPERBITRANK2_Lane7_WID                        ( 4)
+  #define DDRDATACH1_CR_TXPERBITRANK2_Lane7_MSK                        (0xF0000000)
+  #define DDRDATACH1_CR_TXPERBITRANK2_Lane7_MAX                        (0x0000000F)
+
+#define DDRDATACH1_CR_TXPERBITRANK3_REG                              (0x0000313C)
+  #define DDRDATACH1_CR_TXPERBITRANK3_Lane0_OFF                        ( 0)
+  #define DDRDATACH1_CR_TXPERBITRANK3_Lane0_WID                        ( 4)
+  #define DDRDATACH1_CR_TXPERBITRANK3_Lane0_MSK                        (0x0000000F)
+  #define DDRDATACH1_CR_TXPERBITRANK3_Lane0_MAX                        (0x0000000F)
+  #define DDRDATACH1_CR_TXPERBITRANK3_Lane1_OFF                        ( 4)
+  #define DDRDATACH1_CR_TXPERBITRANK3_Lane1_WID                        ( 4)
+  #define DDRDATACH1_CR_TXPERBITRANK3_Lane1_MSK                        (0x000000F0)
+  #define DDRDATACH1_CR_TXPERBITRANK3_Lane1_MAX                        (0x0000000F)
+  #define DDRDATACH1_CR_TXPERBITRANK3_Lane2_OFF                        ( 8)
+  #define DDRDATACH1_CR_TXPERBITRANK3_Lane2_WID                        ( 4)
+  #define DDRDATACH1_CR_TXPERBITRANK3_Lane2_MSK                        (0x00000F00)
+  #define DDRDATACH1_CR_TXPERBITRANK3_Lane2_MAX                        (0x0000000F)
+  #define DDRDATACH1_CR_TXPERBITRANK3_Lane3_OFF                        (12)
+  #define DDRDATACH1_CR_TXPERBITRANK3_Lane3_WID                        ( 4)
+  #define DDRDATACH1_CR_TXPERBITRANK3_Lane3_MSK                        (0x0000F000)
+  #define DDRDATACH1_CR_TXPERBITRANK3_Lane3_MAX                        (0x0000000F)
+  #define DDRDATACH1_CR_TXPERBITRANK3_Lane4_OFF                        (16)
+  #define DDRDATACH1_CR_TXPERBITRANK3_Lane4_WID                        ( 4)
+  #define DDRDATACH1_CR_TXPERBITRANK3_Lane4_MSK                        (0x000F0000)
+  #define DDRDATACH1_CR_TXPERBITRANK3_Lane4_MAX                        (0x0000000F)
+  #define DDRDATACH1_CR_TXPERBITRANK3_Lane5_OFF                        (20)
+  #define DDRDATACH1_CR_TXPERBITRANK3_Lane5_WID                        ( 4)
+  #define DDRDATACH1_CR_TXPERBITRANK3_Lane5_MSK                        (0x00F00000)
+  #define DDRDATACH1_CR_TXPERBITRANK3_Lane5_MAX                        (0x0000000F)
+  #define DDRDATACH1_CR_TXPERBITRANK3_Lane6_OFF                        (24)
+  #define DDRDATACH1_CR_TXPERBITRANK3_Lane6_WID                        ( 4)
+  #define DDRDATACH1_CR_TXPERBITRANK3_Lane6_MSK                        (0x0F000000)
+  #define DDRDATACH1_CR_TXPERBITRANK3_Lane6_MAX                        (0x0000000F)
+  #define DDRDATACH1_CR_TXPERBITRANK3_Lane7_OFF                        (28)
+  #define DDRDATACH1_CR_TXPERBITRANK3_Lane7_WID                        ( 4)
+  #define DDRDATACH1_CR_TXPERBITRANK3_Lane7_MSK                        (0xF0000000)
+  #define DDRDATACH1_CR_TXPERBITRANK3_Lane7_MAX                        (0x0000000F)
+
+#define DDRDATACH1_CR_RCOMPDATA0_REG                                 (0x00003140)
+  #define DDRDATACH1_CR_RCOMPDATA0_RcompDrvUp_OFF                      ( 0)
+  #define DDRDATACH1_CR_RCOMPDATA0_RcompDrvUp_WID                      ( 6)
+  #define DDRDATACH1_CR_RCOMPDATA0_RcompDrvUp_MSK                      (0x0000003F)
+  #define DDRDATACH1_CR_RCOMPDATA0_RcompDrvUp_MAX                      (0x0000003F)
+  #define DDRDATACH1_CR_RCOMPDATA0_Spare0_OFF                          ( 6)
+  #define DDRDATACH1_CR_RCOMPDATA0_Spare0_WID                          ( 3)
+  #define DDRDATACH1_CR_RCOMPDATA0_Spare0_MSK                          (0x000001C0)
+  #define DDRDATACH1_CR_RCOMPDATA0_Spare0_MAX                          (0x00000007)
+  #define DDRDATACH1_CR_RCOMPDATA0_RcompDrvDown_OFF                    ( 9)
+  #define DDRDATACH1_CR_RCOMPDATA0_RcompDrvDown_WID                    ( 6)
+  #define DDRDATACH1_CR_RCOMPDATA0_RcompDrvDown_MSK                    (0x00007E00)
+  #define DDRDATACH1_CR_RCOMPDATA0_RcompDrvDown_MAX                    (0x0000003F)
+  #define DDRDATACH1_CR_RCOMPDATA0_VTComp_OFF                          (15)
+  #define DDRDATACH1_CR_RCOMPDATA0_VTComp_WID                          ( 5)
+  #define DDRDATACH1_CR_RCOMPDATA0_VTComp_MSK                          (0x000F8000)
+  #define DDRDATACH1_CR_RCOMPDATA0_VTComp_MAX                          (0x0000001F)
+  #define DDRDATACH1_CR_RCOMPDATA0_TcoComp_OFF                         (20)
+  #define DDRDATACH1_CR_RCOMPDATA0_TcoComp_WID                         ( 6)
+  #define DDRDATACH1_CR_RCOMPDATA0_TcoComp_MSK                         (0x03F00000)
+  #define DDRDATACH1_CR_RCOMPDATA0_TcoComp_MAX                         (0x0000003F)
+  #define DDRDATACH1_CR_RCOMPDATA0_SlewRateComp_OFF                    (26)
+  #define DDRDATACH1_CR_RCOMPDATA0_SlewRateComp_WID                    ( 5)
+  #define DDRDATACH1_CR_RCOMPDATA0_SlewRateComp_MSK                    (0x7C000000)
+  #define DDRDATACH1_CR_RCOMPDATA0_SlewRateComp_MAX                    (0x0000001F)
+  #define DDRDATACH1_CR_RCOMPDATA0_Spare2_OFF                          (31)
+  #define DDRDATACH1_CR_RCOMPDATA0_Spare2_WID                          ( 1)
+  #define DDRDATACH1_CR_RCOMPDATA0_Spare2_MSK                          (0x80000000)
+  #define DDRDATACH1_CR_RCOMPDATA0_Spare2_MAX                          (0x00000001)
+
+#define DDRDATACH1_CR_RCOMPDATA1_REG                                 (0x00003144)
+  #define DDRDATACH1_CR_RCOMPDATA1_RcompOdtUp_OFF                      ( 0)
+  #define DDRDATACH1_CR_RCOMPDATA1_RcompOdtUp_WID                      ( 6)
+  #define DDRDATACH1_CR_RCOMPDATA1_RcompOdtUp_MSK                      (0x0000003F)
+  #define DDRDATACH1_CR_RCOMPDATA1_RcompOdtUp_MAX                      (0x0000003F)
+  #define DDRDATACH1_CR_RCOMPDATA1_Spare0_OFF                          ( 6)
+  #define DDRDATACH1_CR_RCOMPDATA1_Spare0_WID                          ( 3)
+  #define DDRDATACH1_CR_RCOMPDATA1_Spare0_MSK                          (0x000001C0)
+  #define DDRDATACH1_CR_RCOMPDATA1_Spare0_MAX                          (0x00000007)
+  #define DDRDATACH1_CR_RCOMPDATA1_RcompOdtDown_OFF                    ( 9)
+  #define DDRDATACH1_CR_RCOMPDATA1_RcompOdtDown_WID                    ( 6)
+  #define DDRDATACH1_CR_RCOMPDATA1_RcompOdtDown_MSK                    (0x00007E00)
+  #define DDRDATACH1_CR_RCOMPDATA1_RcompOdtDown_MAX                    (0x0000003F)
+  #define DDRDATACH1_CR_RCOMPDATA1_Spare1_OFF                          (15)
+  #define DDRDATACH1_CR_RCOMPDATA1_Spare1_WID                          ( 1)
+  #define DDRDATACH1_CR_RCOMPDATA1_Spare1_MSK                          (0x00008000)
+  #define DDRDATACH1_CR_RCOMPDATA1_Spare1_MAX                          (0x00000001)
+  #define DDRDATACH1_CR_RCOMPDATA1_PanicDrvDn_OFF                      (16)
+  #define DDRDATACH1_CR_RCOMPDATA1_PanicDrvDn_WID                      ( 6)
+  #define DDRDATACH1_CR_RCOMPDATA1_PanicDrvDn_MSK                      (0x003F0000)
+  #define DDRDATACH1_CR_RCOMPDATA1_PanicDrvDn_MAX                      (0x0000003F)
+  #define DDRDATACH1_CR_RCOMPDATA1_PanicDrvUp_OFF                      (22)
+  #define DDRDATACH1_CR_RCOMPDATA1_PanicDrvUp_WID                      ( 6)
+  #define DDRDATACH1_CR_RCOMPDATA1_PanicDrvUp_MSK                      (0x0FC00000)
+  #define DDRDATACH1_CR_RCOMPDATA1_PanicDrvUp_MAX                      (0x0000003F)
+  #define DDRDATACH1_CR_RCOMPDATA1_LevelShifterComp_OFF                (28)
+  #define DDRDATACH1_CR_RCOMPDATA1_LevelShifterComp_WID                ( 3)
+  #define DDRDATACH1_CR_RCOMPDATA1_LevelShifterComp_MSK                (0x70000000)
+  #define DDRDATACH1_CR_RCOMPDATA1_LevelShifterComp_MAX                (0x00000007)
+  #define DDRDATACH1_CR_RCOMPDATA1_Spare2_OFF                          (31)
+  #define DDRDATACH1_CR_RCOMPDATA1_Spare2_WID                          ( 1)
+  #define DDRDATACH1_CR_RCOMPDATA1_Spare2_MSK                          (0x80000000)
+  #define DDRDATACH1_CR_RCOMPDATA1_Spare2_MAX                          (0x00000001)
+
+#define DDRDATACH1_CR_TXXTALK_REG                                    (0x00003148)
+  #define DDRDATACH1_CR_TXXTALK_Lane0_OFF                              ( 0)
+  #define DDRDATACH1_CR_TXXTALK_Lane0_WID                              ( 4)
+  #define DDRDATACH1_CR_TXXTALK_Lane0_MSK                              (0x0000000F)
+  #define DDRDATACH1_CR_TXXTALK_Lane0_MAX                              (0x0000000F)
+  #define DDRDATACH1_CR_TXXTALK_Lane1_OFF                              ( 4)
+  #define DDRDATACH1_CR_TXXTALK_Lane1_WID                              ( 4)
+  #define DDRDATACH1_CR_TXXTALK_Lane1_MSK                              (0x000000F0)
+  #define DDRDATACH1_CR_TXXTALK_Lane1_MAX                              (0x0000000F)
+  #define DDRDATACH1_CR_TXXTALK_Lane2_OFF                              ( 8)
+  #define DDRDATACH1_CR_TXXTALK_Lane2_WID                              ( 4)
+  #define DDRDATACH1_CR_TXXTALK_Lane2_MSK                              (0x00000F00)
+  #define DDRDATACH1_CR_TXXTALK_Lane2_MAX                              (0x0000000F)
+  #define DDRDATACH1_CR_TXXTALK_Lane3_OFF                              (12)
+  #define DDRDATACH1_CR_TXXTALK_Lane3_WID                              ( 4)
+  #define DDRDATACH1_CR_TXXTALK_Lane3_MSK                              (0x0000F000)
+  #define DDRDATACH1_CR_TXXTALK_Lane3_MAX                              (0x0000000F)
+  #define DDRDATACH1_CR_TXXTALK_Lane4_OFF                              (16)
+  #define DDRDATACH1_CR_TXXTALK_Lane4_WID                              ( 4)
+  #define DDRDATACH1_CR_TXXTALK_Lane4_MSK                              (0x000F0000)
+  #define DDRDATACH1_CR_TXXTALK_Lane4_MAX                              (0x0000000F)
+  #define DDRDATACH1_CR_TXXTALK_Lane5_OFF                              (20)
+  #define DDRDATACH1_CR_TXXTALK_Lane5_WID                              ( 4)
+  #define DDRDATACH1_CR_TXXTALK_Lane5_MSK                              (0x00F00000)
+  #define DDRDATACH1_CR_TXXTALK_Lane5_MAX                              (0x0000000F)
+  #define DDRDATACH1_CR_TXXTALK_Lane6_OFF                              (24)
+  #define DDRDATACH1_CR_TXXTALK_Lane6_WID                              ( 4)
+  #define DDRDATACH1_CR_TXXTALK_Lane6_MSK                              (0x0F000000)
+  #define DDRDATACH1_CR_TXXTALK_Lane6_MAX                              (0x0000000F)
+  #define DDRDATACH1_CR_TXXTALK_Lane7_OFF                              (28)
+  #define DDRDATACH1_CR_TXXTALK_Lane7_WID                              ( 4)
+  #define DDRDATACH1_CR_TXXTALK_Lane7_MSK                              (0xF0000000)
+  #define DDRDATACH1_CR_TXXTALK_Lane7_MAX                              (0x0000000F)
+
+#define DDRDATACH1_CR_RXOFFSETVDQ_REG                                (0x0000314C)
+  #define DDRDATACH1_CR_RXOFFSETVDQ_Lane0_OFF                          ( 0)
+  #define DDRDATACH1_CR_RXOFFSETVDQ_Lane0_WID                          ( 4)
+  #define DDRDATACH1_CR_RXOFFSETVDQ_Lane0_MSK                          (0x0000000F)
+  #define DDRDATACH1_CR_RXOFFSETVDQ_Lane0_MAX                          (0x0000000F)
+  #define DDRDATACH1_CR_RXOFFSETVDQ_Lane1_OFF                          ( 4)
+  #define DDRDATACH1_CR_RXOFFSETVDQ_Lane1_WID                          ( 4)
+  #define DDRDATACH1_CR_RXOFFSETVDQ_Lane1_MSK                          (0x000000F0)
+  #define DDRDATACH1_CR_RXOFFSETVDQ_Lane1_MAX                          (0x0000000F)
+  #define DDRDATACH1_CR_RXOFFSETVDQ_Lane2_OFF                          ( 8)
+  #define DDRDATACH1_CR_RXOFFSETVDQ_Lane2_WID                          ( 4)
+  #define DDRDATACH1_CR_RXOFFSETVDQ_Lane2_MSK                          (0x00000F00)
+  #define DDRDATACH1_CR_RXOFFSETVDQ_Lane2_MAX                          (0x0000000F)
+  #define DDRDATACH1_CR_RXOFFSETVDQ_Lane3_OFF                          (12)
+  #define DDRDATACH1_CR_RXOFFSETVDQ_Lane3_WID                          ( 4)
+  #define DDRDATACH1_CR_RXOFFSETVDQ_Lane3_MSK                          (0x0000F000)
+  #define DDRDATACH1_CR_RXOFFSETVDQ_Lane3_MAX                          (0x0000000F)
+  #define DDRDATACH1_CR_RXOFFSETVDQ_Lane4_OFF                          (16)
+  #define DDRDATACH1_CR_RXOFFSETVDQ_Lane4_WID                          ( 4)
+  #define DDRDATACH1_CR_RXOFFSETVDQ_Lane4_MSK                          (0x000F0000)
+  #define DDRDATACH1_CR_RXOFFSETVDQ_Lane4_MAX                          (0x0000000F)
+  #define DDRDATACH1_CR_RXOFFSETVDQ_Lane5_OFF                          (20)
+  #define DDRDATACH1_CR_RXOFFSETVDQ_Lane5_WID                          ( 4)
+  #define DDRDATACH1_CR_RXOFFSETVDQ_Lane5_MSK                          (0x00F00000)
+  #define DDRDATACH1_CR_RXOFFSETVDQ_Lane5_MAX                          (0x0000000F)
+  #define DDRDATACH1_CR_RXOFFSETVDQ_Lane6_OFF                          (24)
+  #define DDRDATACH1_CR_RXOFFSETVDQ_Lane6_WID                          ( 4)
+  #define DDRDATACH1_CR_RXOFFSETVDQ_Lane6_MSK                          (0x0F000000)
+  #define DDRDATACH1_CR_RXOFFSETVDQ_Lane6_MAX                          (0x0000000F)
+  #define DDRDATACH1_CR_RXOFFSETVDQ_Lane7_OFF                          (28)
+  #define DDRDATACH1_CR_RXOFFSETVDQ_Lane7_WID                          ( 4)
+  #define DDRDATACH1_CR_RXOFFSETVDQ_Lane7_MSK                          (0xF0000000)
+  #define DDRDATACH1_CR_RXOFFSETVDQ_Lane7_MAX                          (0x0000000F)
+
+#define DDRDATACH1_CR_DDRDATARESERVED_REG                            (0x00003150)
+  #define DDRDATACH1_CR_DDRDATARESERVED_Spare_OFF                      ( 0)
+  #define DDRDATACH1_CR_DDRDATARESERVED_Spare_WID                      (32)
+  #define DDRDATACH1_CR_DDRDATARESERVED_Spare_MSK                      (0xFFFFFFFF)
+  #define DDRDATACH1_CR_DDRDATARESERVED_Spare_MAX                      (0xFFFFFFFF)
+
+#define DDRDATACH1_CR_DATATRAINFEEDBACK_REG                          (0x00003154)
+  #define DDRDATACH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_OFF        ( 0)
+  #define DDRDATACH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_WID        ( 9)
+  #define DDRDATACH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_MSK        (0x000001FF)
+  #define DDRDATACH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_MAX        (0x000001FF)
+  #define DDRDATACH1_CR_DATATRAINFEEDBACK_Spare_OFF                    ( 9)
+  #define DDRDATACH1_CR_DATATRAINFEEDBACK_Spare_WID                    (23)
+  #define DDRDATACH1_CR_DATATRAINFEEDBACK_Spare_MSK                    (0xFFFFFE00)
+  #define DDRDATACH1_CR_DATATRAINFEEDBACK_Spare_MAX                    (0x007FFFFF)
+
+#define DDRDATACH1_CR_DLLPITESTANDADC_REG                            (0x00003158)
+  #define DDRDATACH1_CR_DLLPITESTANDADC_RunTest_OFF                    ( 0)
+  #define DDRDATACH1_CR_DLLPITESTANDADC_RunTest_WID                    ( 1)
+  #define DDRDATACH1_CR_DLLPITESTANDADC_RunTest_MSK                    (0x00000001)
+  #define DDRDATACH1_CR_DLLPITESTANDADC_RunTest_MAX                    (0x00000001)
+  #define DDRDATACH1_CR_DLLPITESTANDADC_RunTest_DEF                    (0x00000000)
+  #define DDRDATACH1_CR_DLLPITESTANDADC_Load_OFF                       ( 1)
+  #define DDRDATACH1_CR_DLLPITESTANDADC_Load_WID                       ( 1)
+  #define DDRDATACH1_CR_DLLPITESTANDADC_Load_MSK                       (0x00000002)
+  #define DDRDATACH1_CR_DLLPITESTANDADC_Load_MAX                       (0x00000001)
+  #define DDRDATACH1_CR_DLLPITESTANDADC_Load_DEF                       (0x00000000)
+  #define DDRDATACH1_CR_DLLPITESTANDADC_ModeHVM_OFF                    ( 2)
+  #define DDRDATACH1_CR_DLLPITESTANDADC_ModeHVM_WID                    ( 1)
+  #define DDRDATACH1_CR_DLLPITESTANDADC_ModeHVM_MSK                    (0x00000004)
+  #define DDRDATACH1_CR_DLLPITESTANDADC_ModeHVM_MAX                    (0x00000001)
+  #define DDRDATACH1_CR_DLLPITESTANDADC_ModeHVM_DEF                    (0x00000000)
+  #define DDRDATACH1_CR_DLLPITESTANDADC_ModeDV_OFF                     ( 3)
+  #define DDRDATACH1_CR_DLLPITESTANDADC_ModeDV_WID                     ( 1)
+  #define DDRDATACH1_CR_DLLPITESTANDADC_ModeDV_MSK                     (0x00000008)
+  #define DDRDATACH1_CR_DLLPITESTANDADC_ModeDV_MAX                     (0x00000001)
+  #define DDRDATACH1_CR_DLLPITESTANDADC_ModeDV_DEF                     (0x00000000)
+  #define DDRDATACH1_CR_DLLPITESTANDADC_ModeADC_OFF                    ( 4)
+  #define DDRDATACH1_CR_DLLPITESTANDADC_ModeADC_WID                    ( 1)
+  #define DDRDATACH1_CR_DLLPITESTANDADC_ModeADC_MSK                    (0x00000010)
+  #define DDRDATACH1_CR_DLLPITESTANDADC_ModeADC_MAX                    (0x00000001)
+  #define DDRDATACH1_CR_DLLPITESTANDADC_ModeADC_DEF                    (0x00000000)
+  #define DDRDATACH1_CR_DLLPITESTANDADC_LoadCount_OFF                  ( 5)
+  #define DDRDATACH1_CR_DLLPITESTANDADC_LoadCount_WID                  (10)
+  #define DDRDATACH1_CR_DLLPITESTANDADC_LoadCount_MSK                  (0x00007FE0)
+  #define DDRDATACH1_CR_DLLPITESTANDADC_LoadCount_MAX                  (0x000003FF)
+  #define DDRDATACH1_CR_DLLPITESTANDADC_CountStatus_OFF                (15)
+  #define DDRDATACH1_CR_DLLPITESTANDADC_CountStatus_WID                (10)
+  #define DDRDATACH1_CR_DLLPITESTANDADC_CountStatus_MSK                (0x01FF8000)
+  #define DDRDATACH1_CR_DLLPITESTANDADC_CountStatus_MAX                (0x000003FF)
+  #define DDRDATACH1_CR_DLLPITESTANDADC_CountStatus_DEF                (0x00000000)
+  #define DDRDATACH1_CR_DLLPITESTANDADC_Spare_OFF                      (25)
+  #define DDRDATACH1_CR_DLLPITESTANDADC_Spare_WID                      ( 7)
+  #define DDRDATACH1_CR_DLLPITESTANDADC_Spare_MSK                      (0xFE000000)
+  #define DDRDATACH1_CR_DLLPITESTANDADC_Spare_MAX                      (0x0000007F)
+
+#define DDRDATACH1_CR_DDRCRDATAOFFSETCOMP_REG                        (0x0000315C)
+  #define DDRDATACH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_OFF      ( 0)
+  #define DDRDATACH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_WID      ( 6)
+  #define DDRDATACH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MSK      (0x0000003F)
+  #define DDRDATACH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MAX      (0x0000003F)
+  #define DDRDATACH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_DEF      (0x00000000)
+  #define DDRDATACH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_OFF    ( 6)
+  #define DDRDATACH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_WID    ( 6)
+  #define DDRDATACH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MSK    (0x00000FC0)
+  #define DDRDATACH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MAX    (0x0000003F)
+  #define DDRDATACH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_DEF    (0x00000000)
+  #define DDRDATACH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_OFF      (12)
+  #define DDRDATACH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_WID      ( 5)
+  #define DDRDATACH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MSK      (0x0001F000)
+  #define DDRDATACH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MAX      (0x0000001F)
+  #define DDRDATACH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_DEF      (0x00000000)
+  #define DDRDATACH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_OFF    (17)
+  #define DDRDATACH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_WID    ( 5)
+  #define DDRDATACH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MSK    (0x003E0000)
+  #define DDRDATACH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MAX    (0x0000001F)
+  #define DDRDATACH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_DEF    (0x00000000)
+  #define DDRDATACH1_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_OFF        (22)
+  #define DDRDATACH1_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_WID        ( 5)
+  #define DDRDATACH1_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_MSK        (0x07C00000)
+  #define DDRDATACH1_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_MAX        (0x0000001F)
+  #define DDRDATACH1_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_DEF        (0x00000000)
+  #define DDRDATACH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_OFF   (27)
+  #define DDRDATACH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_WID   ( 5)
+  #define DDRDATACH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MSK   (0xF8000000)
+  #define DDRDATACH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MAX   (0x0000001F)
+  #define DDRDATACH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_DEF   (0x00000000)
+
+#define DDRDATACH1_CR_DDRCRDATACONTROL1_REG                          (0x00003160)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL1_RefPi_OFF                    ( 0)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL1_RefPi_WID                    ( 4)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL1_RefPi_MSK                    (0x0000000F)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL1_RefPi_MAX                    (0x0000000F)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL1_RefPi_DEF                    (0x00000000)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL1_DllMask_OFF                  ( 4)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL1_DllMask_WID                  ( 2)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL1_DllMask_MSK                  (0x00000030)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL1_DllMask_MAX                  (0x00000003)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL1_DllMask_DEF                  (0x00000000)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL1_DllWeakLock_OFF              ( 6)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL1_DllWeakLock_WID              ( 1)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL1_DllWeakLock_MSK              (0x00000040)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL1_DllWeakLock_MAX              (0x00000001)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL1_DllWeakLock_DEF              (0x00000000)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_OFF       ( 7)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_WID       ( 3)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MSK       (0x00000380)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MAX       (0x00000007)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_DEF       (0x00000000)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL1_RxBiasCtl_OFF                (10)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL1_RxBiasCtl_WID                ( 3)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL1_RxBiasCtl_MSK                (0x00001C00)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL1_RxBiasCtl_MAX                (0x00000007)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL1_RxBiasCtl_DEF                (0x00000000)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL1_OdtDelay_OFF                 (13)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL1_OdtDelay_WID                 ( 4)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL1_OdtDelay_MSK                 (0x0001E000)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL1_OdtDelay_MAX                 (0x0000000F)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL1_OdtDelay_DEF                 (0x00000000)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL1_OdtDuration_OFF              (17)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL1_OdtDuration_WID              ( 3)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL1_OdtDuration_MSK              (0x000E0000)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL1_OdtDuration_MAX              (0x00000007)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL1_OdtDuration_DEF              (0x00000000)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_OFF            (20)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_WID            ( 4)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_MSK            (0x00F00000)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_MAX            (0x0000000F)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_DEF            (0x00000000)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_OFF         (24)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_WID         ( 3)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_MSK         (0x07000000)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_MAX         (0x00000007)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_DEF         (0x00000000)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL1_BurstEndODTDelay_OFF         (27)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL1_BurstEndODTDelay_WID         ( 3)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL1_BurstEndODTDelay_MSK         (0x38000000)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL1_BurstEndODTDelay_MAX         (0x00000007)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL1_BurstEndODTDelay_DEF         (0x00000000)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_OFF           (30)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_WID           ( 1)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_MSK           (0x40000000)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_MAX           (0x00000001)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_DEF           (0x00000000)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL1_Rsvd1_OFF                    (31)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL1_Rsvd1_WID                    ( 1)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL1_Rsvd1_MSK                    (0x80000000)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL1_Rsvd1_MAX                    (0x00000001)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL1_Rsvd1_DEF                    (0x00000000)
+
+#define DDRDATACH1_CR_DDRCRDATACONTROL2_REG                          (0x00003164)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_OFF             ( 0)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_WID             ( 5)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_MSK             (0x0000001F)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_MAX             (0x0000001F)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_DEF             (0x00000000)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL2_ForceBiasOn_OFF              ( 5)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL2_ForceBiasOn_WID              ( 1)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL2_ForceBiasOn_MSK              (0x00000020)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL2_ForceBiasOn_MAX              (0x00000001)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL2_ForceBiasOn_DEF              (0x00000000)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL2_ForceRxOn_OFF                ( 6)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL2_ForceRxOn_WID                ( 1)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL2_ForceRxOn_MSK                (0x00000040)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL2_ForceRxOn_MAX                (0x00000001)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL2_ForceRxOn_DEF                (0x00000000)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL2_LeakerComp_OFF               ( 7)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL2_LeakerComp_WID               ( 2)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL2_LeakerComp_MSK               (0x00000180)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL2_LeakerComp_MAX               (0x00000003)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL2_LeakerComp_DEF               (0x00000000)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_OFF           ( 9)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_WID           ( 4)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_MSK           (0x00001E00)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_MAX           (0x0000000F)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_DEF           (0x00000008)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL2_RxClkStgNum_OFF              (13)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL2_RxClkStgNum_WID              ( 5)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL2_RxClkStgNum_MSK              (0x0003E000)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL2_RxClkStgNum_MAX              (0x0000001F)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL2_RxClkStgNum_DEF              (0x00000011)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL2_WlLongDelEn_OFF              (18)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL2_WlLongDelEn_WID              ( 1)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL2_WlLongDelEn_MSK              (0x00040000)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL2_WlLongDelEn_MAX              (0x00000001)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL2_WlLongDelEn_DEF              (0x00000000)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL2_Spare_OFF                    (19)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL2_Spare_WID                    (13)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL2_Spare_MSK                    (0xFFF80000)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL2_Spare_MAX                    (0x00001FFF)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL2_Spare_DEF                    (0x00000000)
+
+#define DDRDATACH1_CR_DDRCRVSSHIORVREFCONTROL_REG                    (0x0000316C)
+  #define DDRDATACH1_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_OFF     ( 0)
+  #define DDRDATACH1_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_WID     (24)
+  #define DDRDATACH1_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_MSK     (0x00FFFFFF)
+  #define DDRDATACH1_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_MAX     (0x00FFFFFF)
+  #define DDRDATACH1_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_DEF     (0x00000000)
+  #define DDRDATACH1_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_OFF         (24)
+  #define DDRDATACH1_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_WID         ( 8)
+  #define DDRDATACH1_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_MSK         (0xFF000000)
+  #define DDRDATACH1_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_MAX         (0x000000FF)
+  #define DDRDATACH1_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_DEF         (0x00000000)
+
+#define DDRDATACH1_CR_DDRCRDATAOFFSETTRAIN_REG                       (0x00003170)
+  #define DDRDATACH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_OFF           ( 0)
+  #define DDRDATACH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_WID           ( 6)
+  #define DDRDATACH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MSK           (0x0000003F)
+  #define DDRDATACH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MAX           (0x0000003F)
+  #define DDRDATACH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_DEF           (0x00000000)
+  #define DDRDATACH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_OFF           ( 6)
+  #define DDRDATACH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_WID           ( 6)
+  #define DDRDATACH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MSK           (0x00000FC0)
+  #define DDRDATACH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MAX           (0x0000003F)
+  #define DDRDATACH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_DEF           (0x00000000)
+  #define DDRDATACH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_OFF            (12)
+  #define DDRDATACH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_WID            ( 6)
+  #define DDRDATACH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MSK            (0x0003F000)
+  #define DDRDATACH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MAX            (0x0000003F)
+  #define DDRDATACH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_DEF            (0x00000000)
+  #define DDRDATACH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_OFF           (18)
+  #define DDRDATACH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_WID           ( 6)
+  #define DDRDATACH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MSK           (0x00FC0000)
+  #define DDRDATACH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MAX           (0x0000003F)
+  #define DDRDATACH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_DEF           (0x00000000)
+  #define DDRDATACH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_OFF            (24)
+  #define DDRDATACH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_WID            ( 7)
+  #define DDRDATACH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MSK            (0x7F000000)
+  #define DDRDATACH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MAX            (0x0000007F)
+  #define DDRDATACH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_DEF            (0x00000000)
+  #define DDRDATACH1_CR_DDRCRDATAOFFSETTRAIN_Spare_OFF                 (31)
+  #define DDRDATACH1_CR_DDRCRDATAOFFSETTRAIN_Spare_WID                 ( 1)
+  #define DDRDATACH1_CR_DDRCRDATAOFFSETTRAIN_Spare_MSK                 (0x80000000)
+  #define DDRDATACH1_CR_DDRCRDATAOFFSETTRAIN_Spare_MAX                 (0x00000001)
+  #define DDRDATACH1_CR_DDRCRDATAOFFSETTRAIN_Spare_DEF                 (0x00000000)
+
+#define DDRDATACH1_CR_DDRCRDATACONTROL0_REG                          (0x00003174)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL0_RxTrainingMode_OFF           ( 0)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL0_RxTrainingMode_WID           ( 1)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL0_RxTrainingMode_MSK           (0x00000001)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL0_RxTrainingMode_MAX           (0x00000001)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL0_RxTrainingMode_DEF           (0x00000000)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL0_WLTrainingMode_OFF           ( 1)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL0_WLTrainingMode_WID           ( 1)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL0_WLTrainingMode_MSK           (0x00000002)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL0_WLTrainingMode_MAX           (0x00000001)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL0_WLTrainingMode_DEF           (0x00000000)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL0_RLTrainingMode_OFF           ( 2)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL0_RLTrainingMode_WID           ( 1)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL0_RLTrainingMode_MSK           (0x00000004)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL0_RLTrainingMode_MAX           (0x00000001)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL0_RLTrainingMode_DEF           (0x00000000)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_OFF     ( 3)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_WID     ( 1)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MSK     (0x00000008)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MAX     (0x00000001)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_DEF     (0x00000000)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL0_TxOn_OFF                     ( 4)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL0_TxOn_WID                     ( 1)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL0_TxOn_MSK                     (0x00000010)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL0_TxOn_MAX                     (0x00000001)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL0_TxOn_DEF                     (0x00000000)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL0_RfOn_OFF                     ( 5)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL0_RfOn_WID                     ( 1)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL0_RfOn_MSK                     (0x00000020)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL0_RfOn_MAX                     (0x00000001)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL0_RfOn_DEF                     (0x00000000)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL0_RxPiOn_OFF                   ( 6)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL0_RxPiOn_WID                   ( 1)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL0_RxPiOn_MSK                   (0x00000040)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL0_RxPiOn_MAX                   (0x00000001)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL0_RxPiOn_DEF                   (0x00000000)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL0_TxPiOn_OFF                   ( 7)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL0_TxPiOn_WID                   ( 1)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL0_TxPiOn_MSK                   (0x00000080)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL0_TxPiOn_MAX                   (0x00000001)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL0_TxPiOn_DEF                   (0x00000000)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL0_InternalClocksOn_OFF         ( 8)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL0_InternalClocksOn_WID         ( 1)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL0_InternalClocksOn_MSK         (0x00000100)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL0_InternalClocksOn_MAX         (0x00000001)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL0_InternalClocksOn_DEF         (0x00000000)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_OFF         ( 9)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_WID         ( 1)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MSK         (0x00000200)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MAX         (0x00000001)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_DEF         (0x00000000)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL0_TxDisable_OFF                (10)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL0_TxDisable_WID                ( 1)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL0_TxDisable_MSK                (0x00000400)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL0_TxDisable_MAX                (0x00000001)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL0_TxDisable_DEF                (0x00000000)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL0_RxDisable_OFF                (11)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL0_RxDisable_WID                ( 1)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL0_RxDisable_MSK                (0x00000800)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL0_RxDisable_MAX                (0x00000001)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL0_RxDisable_DEF                (0x00000000)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL0_TxLong_OFF                   (12)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL0_TxLong_WID                   ( 1)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL0_TxLong_MSK                   (0x00001000)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL0_TxLong_MAX                   (0x00000001)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL0_TxLong_DEF                   (0x00000000)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL0_RxDqsCtle_OFF                (13)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL0_RxDqsCtle_WID                ( 2)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL0_RxDqsCtle_MSK                (0x00006000)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL0_RxDqsCtle_MAX                (0x00000003)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL0_RxDqsCtle_DEF                (0x00000000)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL0_RxReadPointer_OFF            (15)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL0_RxReadPointer_WID            ( 3)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL0_RxReadPointer_MSK            (0x00038000)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL0_RxReadPointer_MAX            (0x00000007)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL0_RxReadPointer_DEF            (0x00000000)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL0_DriverSegmentEnable_OFF      (18)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL0_DriverSegmentEnable_WID      ( 1)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL0_DriverSegmentEnable_MSK      (0x00040000)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL0_DriverSegmentEnable_MAX      (0x00000001)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL0_DriverSegmentEnable_DEF      (0x00000000)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL0_DataVccddqHi_OFF             (19)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL0_DataVccddqHi_WID             ( 1)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL0_DataVccddqHi_MSK             (0x00080000)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL0_DataVccddqHi_MAX             (0x00000001)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL0_DataVccddqHi_DEF             (0x00000000)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL0_ReadRFRd_OFF                 (20)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL0_ReadRFRd_WID                 ( 1)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL0_ReadRFRd_MSK                 (0x00100000)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL0_ReadRFRd_MAX                 (0x00000001)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL0_ReadRFRd_DEF                 (0x00000000)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL0_ReadRFWr_OFF                 (21)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL0_ReadRFWr_WID                 ( 1)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL0_ReadRFWr_MSK                 (0x00200000)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL0_ReadRFWr_MAX                 (0x00000001)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL0_ReadRFWr_DEF                 (0x00000000)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL0_ReadRFRank_OFF               (22)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL0_ReadRFRank_WID               ( 2)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL0_ReadRFRank_MSK               (0x00C00000)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL0_ReadRFRank_MAX               (0x00000003)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL0_ReadRFRank_DEF               (0x00000000)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL0_ForceOdtOn_OFF               (24)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL0_ForceOdtOn_WID               ( 1)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL0_ForceOdtOn_MSK               (0x01000000)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL0_ForceOdtOn_MAX               (0x00000001)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL0_ForceOdtOn_DEF               (0x00000000)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL0_OdtSampOff_OFF               (25)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL0_OdtSampOff_WID               ( 1)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL0_OdtSampOff_MSK               (0x02000000)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL0_OdtSampOff_MAX               (0x00000001)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL0_OdtSampOff_DEF               (0x00000000)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_OFF         (26)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_WID         ( 1)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_MSK         (0x04000000)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_MAX         (0x00000001)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_DEF         (0x00000000)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_OFF          (27)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_WID          ( 1)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MSK          (0x08000000)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MAX          (0x00000001)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_DEF          (0x00000000)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_OFF               (28)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_WID               ( 1)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_MSK               (0x10000000)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_MAX               (0x00000001)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_DEF               (0x00000000)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL0_EnReadPreamble_OFF           (29)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL0_EnReadPreamble_WID           ( 1)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL0_EnReadPreamble_MSK           (0x20000000)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL0_EnReadPreamble_MAX           (0x00000001)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL0_EnReadPreamble_DEF           (0x00000000)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_OFF          (30)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_WID          ( 1)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MSK          (0x40000000)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MAX          (0x00000001)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_DEF          (0x00000000)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_OFF             (31)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_WID             ( 1)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_MSK             (0x80000000)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_MAX             (0x00000001)
+  #define DDRDATACH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_DEF             (0x00000000)
+
+#define DDRDATACH1_CR_DDRCRVREFADJUST1_REG                           (0x00003178)
+  #define DDRDATACH1_CR_DDRCRVREFADJUST1_CAVrefCtl_OFF                 ( 0)
+  #define DDRDATACH1_CR_DDRCRVREFADJUST1_CAVrefCtl_WID                 ( 7)
+  #define DDRDATACH1_CR_DDRCRVREFADJUST1_CAVrefCtl_MSK                 (0x0000007F)
+  #define DDRDATACH1_CR_DDRCRVREFADJUST1_CAVrefCtl_MAX                 (0x0000007F)
+  #define DDRDATACH1_CR_DDRCRVREFADJUST1_CAVrefCtl_DEF                 (0x00000000)
+  #define DDRDATACH1_CR_DDRCRVREFADJUST1_Ch1VrefCtl_OFF                ( 7)
+  #define DDRDATACH1_CR_DDRCRVREFADJUST1_Ch1VrefCtl_WID                ( 7)
+  #define DDRDATACH1_CR_DDRCRVREFADJUST1_Ch1VrefCtl_MSK                (0x00003F80)
+  #define DDRDATACH1_CR_DDRCRVREFADJUST1_Ch1VrefCtl_MAX                (0x0000007F)
+  #define DDRDATACH1_CR_DDRCRVREFADJUST1_Ch1VrefCtl_DEF                (0x00000000)
+  #define DDRDATACH1_CR_DDRCRVREFADJUST1_Ch0VrefCtl_OFF                (14)
+  #define DDRDATACH1_CR_DDRCRVREFADJUST1_Ch0VrefCtl_WID                ( 7)
+  #define DDRDATACH1_CR_DDRCRVREFADJUST1_Ch0VrefCtl_MSK                (0x001FC000)
+  #define DDRDATACH1_CR_DDRCRVREFADJUST1_Ch0VrefCtl_MAX                (0x0000007F)
+  #define DDRDATACH1_CR_DDRCRVREFADJUST1_Ch0VrefCtl_DEF                (0x00000000)
+  #define DDRDATACH1_CR_DDRCRVREFADJUST1_EnDimmVrefCA_OFF              (21)
+  #define DDRDATACH1_CR_DDRCRVREFADJUST1_EnDimmVrefCA_WID              ( 1)
+  #define DDRDATACH1_CR_DDRCRVREFADJUST1_EnDimmVrefCA_MSK              (0x00200000)
+  #define DDRDATACH1_CR_DDRCRVREFADJUST1_EnDimmVrefCA_MAX              (0x00000001)
+  #define DDRDATACH1_CR_DDRCRVREFADJUST1_EnDimmVrefCA_DEF              (0x00000000)
+  #define DDRDATACH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_OFF             (22)
+  #define DDRDATACH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_WID             ( 1)
+  #define DDRDATACH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_MSK             (0x00400000)
+  #define DDRDATACH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_MAX             (0x00000001)
+  #define DDRDATACH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_DEF             (0x00000000)
+  #define DDRDATACH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_OFF             (23)
+  #define DDRDATACH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_WID             ( 1)
+  #define DDRDATACH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_MSK             (0x00800000)
+  #define DDRDATACH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_MAX             (0x00000001)
+  #define DDRDATACH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_DEF             (0x00000000)
+  #define DDRDATACH1_CR_DDRCRVREFADJUST1_HiZTimerCtrl_OFF              (24)
+  #define DDRDATACH1_CR_DDRCRVREFADJUST1_HiZTimerCtrl_WID              ( 2)
+  #define DDRDATACH1_CR_DDRCRVREFADJUST1_HiZTimerCtrl_MSK              (0x03000000)
+  #define DDRDATACH1_CR_DDRCRVREFADJUST1_HiZTimerCtrl_MAX              (0x00000003)
+  #define DDRDATACH1_CR_DDRCRVREFADJUST1_HiZTimerCtrl_DEF              (0x00000000)
+  #define DDRDATACH1_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_OFF             (26)
+  #define DDRDATACH1_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_WID             ( 1)
+  #define DDRDATACH1_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_MSK             (0x04000000)
+  #define DDRDATACH1_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_MAX             (0x00000001)
+  #define DDRDATACH1_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_DEF             (0x00000000)
+  #define DDRDATACH1_CR_DDRCRVREFADJUST1_Rsvd_OFF                      (27)
+  #define DDRDATACH1_CR_DDRCRVREFADJUST1_Rsvd_WID                      ( 2)
+  #define DDRDATACH1_CR_DDRCRVREFADJUST1_Rsvd_MSK                      (0x18000000)
+  #define DDRDATACH1_CR_DDRCRVREFADJUST1_Rsvd_MAX                      (0x00000003)
+  #define DDRDATACH1_CR_DDRCRVREFADJUST1_Rsvd_DEF                      (0x00000000)
+  #define DDRDATACH1_CR_DDRCRVREFADJUST1_caSlowBW_OFF                  (29)
+  #define DDRDATACH1_CR_DDRCRVREFADJUST1_caSlowBW_WID                  ( 1)
+  #define DDRDATACH1_CR_DDRCRVREFADJUST1_caSlowBW_MSK                  (0x20000000)
+  #define DDRDATACH1_CR_DDRCRVREFADJUST1_caSlowBW_MAX                  (0x00000001)
+  #define DDRDATACH1_CR_DDRCRVREFADJUST1_caSlowBW_DEF                  (0x00000000)
+  #define DDRDATACH1_CR_DDRCRVREFADJUST1_ch0SlowBW_OFF                 (30)
+  #define DDRDATACH1_CR_DDRCRVREFADJUST1_ch0SlowBW_WID                 ( 1)
+  #define DDRDATACH1_CR_DDRCRVREFADJUST1_ch0SlowBW_MSK                 (0x40000000)
+  #define DDRDATACH1_CR_DDRCRVREFADJUST1_ch0SlowBW_MAX                 (0x00000001)
+  #define DDRDATACH1_CR_DDRCRVREFADJUST1_ch0SlowBW_DEF                 (0x00000000)
+  #define DDRDATACH1_CR_DDRCRVREFADJUST1_ch1SlowBW_OFF                 (31)
+  #define DDRDATACH1_CR_DDRCRVREFADJUST1_ch1SlowBW_WID                 ( 1)
+  #define DDRDATACH1_CR_DDRCRVREFADJUST1_ch1SlowBW_MSK                 (0x80000000)
+  #define DDRDATACH1_CR_DDRCRVREFADJUST1_ch1SlowBW_MAX                 (0x00000001)
+  #define DDRDATACH1_CR_DDRCRVREFADJUST1_ch1SlowBW_DEF                 (0x00000000)
+
+#define DDRDATA0CH0_CR_RXTRAINRANK0_REG                              (0x00000000)
+  #define DDRDATA0CH0_CR_RXTRAINRANK0_RxRcvEnPi_OFF                    ( 0)
+  #define DDRDATA0CH0_CR_RXTRAINRANK0_RxRcvEnPi_WID                    ( 9)
+  #define DDRDATA0CH0_CR_RXTRAINRANK0_RxRcvEnPi_MSK                    (0x000001FF)
+  #define DDRDATA0CH0_CR_RXTRAINRANK0_RxRcvEnPi_MAX                    (0x000001FF)
+  #define DDRDATA0CH0_CR_RXTRAINRANK0_RxDqsPPi_OFF                     ( 9)
+  #define DDRDATA0CH0_CR_RXTRAINRANK0_RxDqsPPi_WID                     ( 6)
+  #define DDRDATA0CH0_CR_RXTRAINRANK0_RxDqsPPi_MSK                     (0x00007E00)
+  #define DDRDATA0CH0_CR_RXTRAINRANK0_RxDqsPPi_MAX                     (0x0000003F)
+  #define DDRDATA0CH0_CR_RXTRAINRANK0_RxEq_OFF                         (15)
+  #define DDRDATA0CH0_CR_RXTRAINRANK0_RxEq_WID                         ( 5)
+  #define DDRDATA0CH0_CR_RXTRAINRANK0_RxEq_MSK                         (0x000F8000)
+  #define DDRDATA0CH0_CR_RXTRAINRANK0_RxEq_MAX                         (0x0000001F)
+  #define DDRDATA0CH0_CR_RXTRAINRANK0_RxDqsNPi_OFF                     (20)
+  #define DDRDATA0CH0_CR_RXTRAINRANK0_RxDqsNPi_WID                     ( 6)
+  #define DDRDATA0CH0_CR_RXTRAINRANK0_RxDqsNPi_MSK                     (0x03F00000)
+  #define DDRDATA0CH0_CR_RXTRAINRANK0_RxDqsNPi_MAX                     (0x0000003F)
+  #define DDRDATA0CH0_CR_RXTRAINRANK0_RxVref_OFF                       (26)
+  #define DDRDATA0CH0_CR_RXTRAINRANK0_RxVref_WID                       ( 6)
+  #define DDRDATA0CH0_CR_RXTRAINRANK0_RxVref_MSK                       (0xFC000000)
+  #define DDRDATA0CH0_CR_RXTRAINRANK0_RxVref_MAX                       (0x0000003F)
+
+#define DDRDATA0CH0_CR_RXTRAINRANK1_REG                              (0x00000004)
+  #define DDRDATA0CH0_CR_RXTRAINRANK1_RxRcvEnPi_OFF                    ( 0)
+  #define DDRDATA0CH0_CR_RXTRAINRANK1_RxRcvEnPi_WID                    ( 9)
+  #define DDRDATA0CH0_CR_RXTRAINRANK1_RxRcvEnPi_MSK                    (0x000001FF)
+  #define DDRDATA0CH0_CR_RXTRAINRANK1_RxRcvEnPi_MAX                    (0x000001FF)
+  #define DDRDATA0CH0_CR_RXTRAINRANK1_RxDqsPPi_OFF                     ( 9)
+  #define DDRDATA0CH0_CR_RXTRAINRANK1_RxDqsPPi_WID                     ( 6)
+  #define DDRDATA0CH0_CR_RXTRAINRANK1_RxDqsPPi_MSK                     (0x00007E00)
+  #define DDRDATA0CH0_CR_RXTRAINRANK1_RxDqsPPi_MAX                     (0x0000003F)
+  #define DDRDATA0CH0_CR_RXTRAINRANK1_RxEq_OFF                         (15)
+  #define DDRDATA0CH0_CR_RXTRAINRANK1_RxEq_WID                         ( 5)
+  #define DDRDATA0CH0_CR_RXTRAINRANK1_RxEq_MSK                         (0x000F8000)
+  #define DDRDATA0CH0_CR_RXTRAINRANK1_RxEq_MAX                         (0x0000001F)
+  #define DDRDATA0CH0_CR_RXTRAINRANK1_RxDqsNPi_OFF                     (20)
+  #define DDRDATA0CH0_CR_RXTRAINRANK1_RxDqsNPi_WID                     ( 6)
+  #define DDRDATA0CH0_CR_RXTRAINRANK1_RxDqsNPi_MSK                     (0x03F00000)
+  #define DDRDATA0CH0_CR_RXTRAINRANK1_RxDqsNPi_MAX                     (0x0000003F)
+  #define DDRDATA0CH0_CR_RXTRAINRANK1_RxVref_OFF                       (26)
+  #define DDRDATA0CH0_CR_RXTRAINRANK1_RxVref_WID                       ( 6)
+  #define DDRDATA0CH0_CR_RXTRAINRANK1_RxVref_MSK                       (0xFC000000)
+  #define DDRDATA0CH0_CR_RXTRAINRANK1_RxVref_MAX                       (0x0000003F)
+
+#define DDRDATA0CH0_CR_RXTRAINRANK2_REG                              (0x00000008)
+  #define DDRDATA0CH0_CR_RXTRAINRANK2_RxRcvEnPi_OFF                    ( 0)
+  #define DDRDATA0CH0_CR_RXTRAINRANK2_RxRcvEnPi_WID                    ( 9)
+  #define DDRDATA0CH0_CR_RXTRAINRANK2_RxRcvEnPi_MSK                    (0x000001FF)
+  #define DDRDATA0CH0_CR_RXTRAINRANK2_RxRcvEnPi_MAX                    (0x000001FF)
+  #define DDRDATA0CH0_CR_RXTRAINRANK2_RxDqsPPi_OFF                     ( 9)
+  #define DDRDATA0CH0_CR_RXTRAINRANK2_RxDqsPPi_WID                     ( 6)
+  #define DDRDATA0CH0_CR_RXTRAINRANK2_RxDqsPPi_MSK                     (0x00007E00)
+  #define DDRDATA0CH0_CR_RXTRAINRANK2_RxDqsPPi_MAX                     (0x0000003F)
+  #define DDRDATA0CH0_CR_RXTRAINRANK2_RxEq_OFF                         (15)
+  #define DDRDATA0CH0_CR_RXTRAINRANK2_RxEq_WID                         ( 5)
+  #define DDRDATA0CH0_CR_RXTRAINRANK2_RxEq_MSK                         (0x000F8000)
+  #define DDRDATA0CH0_CR_RXTRAINRANK2_RxEq_MAX                         (0x0000001F)
+  #define DDRDATA0CH0_CR_RXTRAINRANK2_RxDqsNPi_OFF                     (20)
+  #define DDRDATA0CH0_CR_RXTRAINRANK2_RxDqsNPi_WID                     ( 6)
+  #define DDRDATA0CH0_CR_RXTRAINRANK2_RxDqsNPi_MSK                     (0x03F00000)
+  #define DDRDATA0CH0_CR_RXTRAINRANK2_RxDqsNPi_MAX                     (0x0000003F)
+  #define DDRDATA0CH0_CR_RXTRAINRANK2_RxVref_OFF                       (26)
+  #define DDRDATA0CH0_CR_RXTRAINRANK2_RxVref_WID                       ( 6)
+  #define DDRDATA0CH0_CR_RXTRAINRANK2_RxVref_MSK                       (0xFC000000)
+  #define DDRDATA0CH0_CR_RXTRAINRANK2_RxVref_MAX                       (0x0000003F)
+
+#define DDRDATA0CH0_CR_RXTRAINRANK3_REG                              (0x0000000C)
+  #define DDRDATA0CH0_CR_RXTRAINRANK3_RxRcvEnPi_OFF                    ( 0)
+  #define DDRDATA0CH0_CR_RXTRAINRANK3_RxRcvEnPi_WID                    ( 9)
+  #define DDRDATA0CH0_CR_RXTRAINRANK3_RxRcvEnPi_MSK                    (0x000001FF)
+  #define DDRDATA0CH0_CR_RXTRAINRANK3_RxRcvEnPi_MAX                    (0x000001FF)
+  #define DDRDATA0CH0_CR_RXTRAINRANK3_RxDqsPPi_OFF                     ( 9)
+  #define DDRDATA0CH0_CR_RXTRAINRANK3_RxDqsPPi_WID                     ( 6)
+  #define DDRDATA0CH0_CR_RXTRAINRANK3_RxDqsPPi_MSK                     (0x00007E00)
+  #define DDRDATA0CH0_CR_RXTRAINRANK3_RxDqsPPi_MAX                     (0x0000003F)
+  #define DDRDATA0CH0_CR_RXTRAINRANK3_RxEq_OFF                         (15)
+  #define DDRDATA0CH0_CR_RXTRAINRANK3_RxEq_WID                         ( 5)
+  #define DDRDATA0CH0_CR_RXTRAINRANK3_RxEq_MSK                         (0x000F8000)
+  #define DDRDATA0CH0_CR_RXTRAINRANK3_RxEq_MAX                         (0x0000001F)
+  #define DDRDATA0CH0_CR_RXTRAINRANK3_RxDqsNPi_OFF                     (20)
+  #define DDRDATA0CH0_CR_RXTRAINRANK3_RxDqsNPi_WID                     ( 6)
+  #define DDRDATA0CH0_CR_RXTRAINRANK3_RxDqsNPi_MSK                     (0x03F00000)
+  #define DDRDATA0CH0_CR_RXTRAINRANK3_RxDqsNPi_MAX                     (0x0000003F)
+  #define DDRDATA0CH0_CR_RXTRAINRANK3_RxVref_OFF                       (26)
+  #define DDRDATA0CH0_CR_RXTRAINRANK3_RxVref_WID                       ( 6)
+  #define DDRDATA0CH0_CR_RXTRAINRANK3_RxVref_MSK                       (0xFC000000)
+  #define DDRDATA0CH0_CR_RXTRAINRANK3_RxVref_MAX                       (0x0000003F)
+
+#define DDRDATA0CH0_CR_RXPERBITRANK0_REG                             (0x00000010)
+  #define DDRDATA0CH0_CR_RXPERBITRANK0_Lane0_OFF                       ( 0)
+  #define DDRDATA0CH0_CR_RXPERBITRANK0_Lane0_WID                       ( 4)
+  #define DDRDATA0CH0_CR_RXPERBITRANK0_Lane0_MSK                       (0x0000000F)
+  #define DDRDATA0CH0_CR_RXPERBITRANK0_Lane0_MAX                       (0x0000000F)
+  #define DDRDATA0CH0_CR_RXPERBITRANK0_Lane1_OFF                       ( 4)
+  #define DDRDATA0CH0_CR_RXPERBITRANK0_Lane1_WID                       ( 4)
+  #define DDRDATA0CH0_CR_RXPERBITRANK0_Lane1_MSK                       (0x000000F0)
+  #define DDRDATA0CH0_CR_RXPERBITRANK0_Lane1_MAX                       (0x0000000F)
+  #define DDRDATA0CH0_CR_RXPERBITRANK0_Lane2_OFF                       ( 8)
+  #define DDRDATA0CH0_CR_RXPERBITRANK0_Lane2_WID                       ( 4)
+  #define DDRDATA0CH0_CR_RXPERBITRANK0_Lane2_MSK                       (0x00000F00)
+  #define DDRDATA0CH0_CR_RXPERBITRANK0_Lane2_MAX                       (0x0000000F)
+  #define DDRDATA0CH0_CR_RXPERBITRANK0_Lane3_OFF                       (12)
+  #define DDRDATA0CH0_CR_RXPERBITRANK0_Lane3_WID                       ( 4)
+  #define DDRDATA0CH0_CR_RXPERBITRANK0_Lane3_MSK                       (0x0000F000)
+  #define DDRDATA0CH0_CR_RXPERBITRANK0_Lane3_MAX                       (0x0000000F)
+  #define DDRDATA0CH0_CR_RXPERBITRANK0_Lane4_OFF                       (16)
+  #define DDRDATA0CH0_CR_RXPERBITRANK0_Lane4_WID                       ( 4)
+  #define DDRDATA0CH0_CR_RXPERBITRANK0_Lane4_MSK                       (0x000F0000)
+  #define DDRDATA0CH0_CR_RXPERBITRANK0_Lane4_MAX                       (0x0000000F)
+  #define DDRDATA0CH0_CR_RXPERBITRANK0_Lane5_OFF                       (20)
+  #define DDRDATA0CH0_CR_RXPERBITRANK0_Lane5_WID                       ( 4)
+  #define DDRDATA0CH0_CR_RXPERBITRANK0_Lane5_MSK                       (0x00F00000)
+  #define DDRDATA0CH0_CR_RXPERBITRANK0_Lane5_MAX                       (0x0000000F)
+  #define DDRDATA0CH0_CR_RXPERBITRANK0_Lane6_OFF                       (24)
+  #define DDRDATA0CH0_CR_RXPERBITRANK0_Lane6_WID                       ( 4)
+  #define DDRDATA0CH0_CR_RXPERBITRANK0_Lane6_MSK                       (0x0F000000)
+  #define DDRDATA0CH0_CR_RXPERBITRANK0_Lane6_MAX                       (0x0000000F)
+  #define DDRDATA0CH0_CR_RXPERBITRANK0_Lane7_OFF                       (28)
+  #define DDRDATA0CH0_CR_RXPERBITRANK0_Lane7_WID                       ( 4)
+  #define DDRDATA0CH0_CR_RXPERBITRANK0_Lane7_MSK                       (0xF0000000)
+  #define DDRDATA0CH0_CR_RXPERBITRANK0_Lane7_MAX                       (0x0000000F)
+
+#define DDRDATA0CH0_CR_RXPERBITRANK1_REG                             (0x00000014)
+  #define DDRDATA0CH0_CR_RXPERBITRANK1_Lane0_OFF                       ( 0)
+  #define DDRDATA0CH0_CR_RXPERBITRANK1_Lane0_WID                       ( 4)
+  #define DDRDATA0CH0_CR_RXPERBITRANK1_Lane0_MSK                       (0x0000000F)
+  #define DDRDATA0CH0_CR_RXPERBITRANK1_Lane0_MAX                       (0x0000000F)
+  #define DDRDATA0CH0_CR_RXPERBITRANK1_Lane1_OFF                       ( 4)
+  #define DDRDATA0CH0_CR_RXPERBITRANK1_Lane1_WID                       ( 4)
+  #define DDRDATA0CH0_CR_RXPERBITRANK1_Lane1_MSK                       (0x000000F0)
+  #define DDRDATA0CH0_CR_RXPERBITRANK1_Lane1_MAX                       (0x0000000F)
+  #define DDRDATA0CH0_CR_RXPERBITRANK1_Lane2_OFF                       ( 8)
+  #define DDRDATA0CH0_CR_RXPERBITRANK1_Lane2_WID                       ( 4)
+  #define DDRDATA0CH0_CR_RXPERBITRANK1_Lane2_MSK                       (0x00000F00)
+  #define DDRDATA0CH0_CR_RXPERBITRANK1_Lane2_MAX                       (0x0000000F)
+  #define DDRDATA0CH0_CR_RXPERBITRANK1_Lane3_OFF                       (12)
+  #define DDRDATA0CH0_CR_RXPERBITRANK1_Lane3_WID                       ( 4)
+  #define DDRDATA0CH0_CR_RXPERBITRANK1_Lane3_MSK                       (0x0000F000)
+  #define DDRDATA0CH0_CR_RXPERBITRANK1_Lane3_MAX                       (0x0000000F)
+  #define DDRDATA0CH0_CR_RXPERBITRANK1_Lane4_OFF                       (16)
+  #define DDRDATA0CH0_CR_RXPERBITRANK1_Lane4_WID                       ( 4)
+  #define DDRDATA0CH0_CR_RXPERBITRANK1_Lane4_MSK                       (0x000F0000)
+  #define DDRDATA0CH0_CR_RXPERBITRANK1_Lane4_MAX                       (0x0000000F)
+  #define DDRDATA0CH0_CR_RXPERBITRANK1_Lane5_OFF                       (20)
+  #define DDRDATA0CH0_CR_RXPERBITRANK1_Lane5_WID                       ( 4)
+  #define DDRDATA0CH0_CR_RXPERBITRANK1_Lane5_MSK                       (0x00F00000)
+  #define DDRDATA0CH0_CR_RXPERBITRANK1_Lane5_MAX                       (0x0000000F)
+  #define DDRDATA0CH0_CR_RXPERBITRANK1_Lane6_OFF                       (24)
+  #define DDRDATA0CH0_CR_RXPERBITRANK1_Lane6_WID                       ( 4)
+  #define DDRDATA0CH0_CR_RXPERBITRANK1_Lane6_MSK                       (0x0F000000)
+  #define DDRDATA0CH0_CR_RXPERBITRANK1_Lane6_MAX                       (0x0000000F)
+  #define DDRDATA0CH0_CR_RXPERBITRANK1_Lane7_OFF                       (28)
+  #define DDRDATA0CH0_CR_RXPERBITRANK1_Lane7_WID                       ( 4)
+  #define DDRDATA0CH0_CR_RXPERBITRANK1_Lane7_MSK                       (0xF0000000)
+  #define DDRDATA0CH0_CR_RXPERBITRANK1_Lane7_MAX                       (0x0000000F)
+
+#define DDRDATA0CH0_CR_RXPERBITRANK2_REG                             (0x00000018)
+  #define DDRDATA0CH0_CR_RXPERBITRANK2_Lane0_OFF                       ( 0)
+  #define DDRDATA0CH0_CR_RXPERBITRANK2_Lane0_WID                       ( 4)
+  #define DDRDATA0CH0_CR_RXPERBITRANK2_Lane0_MSK                       (0x0000000F)
+  #define DDRDATA0CH0_CR_RXPERBITRANK2_Lane0_MAX                       (0x0000000F)
+  #define DDRDATA0CH0_CR_RXPERBITRANK2_Lane1_OFF                       ( 4)
+  #define DDRDATA0CH0_CR_RXPERBITRANK2_Lane1_WID                       ( 4)
+  #define DDRDATA0CH0_CR_RXPERBITRANK2_Lane1_MSK                       (0x000000F0)
+  #define DDRDATA0CH0_CR_RXPERBITRANK2_Lane1_MAX                       (0x0000000F)
+  #define DDRDATA0CH0_CR_RXPERBITRANK2_Lane2_OFF                       ( 8)
+  #define DDRDATA0CH0_CR_RXPERBITRANK2_Lane2_WID                       ( 4)
+  #define DDRDATA0CH0_CR_RXPERBITRANK2_Lane2_MSK                       (0x00000F00)
+  #define DDRDATA0CH0_CR_RXPERBITRANK2_Lane2_MAX                       (0x0000000F)
+  #define DDRDATA0CH0_CR_RXPERBITRANK2_Lane3_OFF                       (12)
+  #define DDRDATA0CH0_CR_RXPERBITRANK2_Lane3_WID                       ( 4)
+  #define DDRDATA0CH0_CR_RXPERBITRANK2_Lane3_MSK                       (0x0000F000)
+  #define DDRDATA0CH0_CR_RXPERBITRANK2_Lane3_MAX                       (0x0000000F)
+  #define DDRDATA0CH0_CR_RXPERBITRANK2_Lane4_OFF                       (16)
+  #define DDRDATA0CH0_CR_RXPERBITRANK2_Lane4_WID                       ( 4)
+  #define DDRDATA0CH0_CR_RXPERBITRANK2_Lane4_MSK                       (0x000F0000)
+  #define DDRDATA0CH0_CR_RXPERBITRANK2_Lane4_MAX                       (0x0000000F)
+  #define DDRDATA0CH0_CR_RXPERBITRANK2_Lane5_OFF                       (20)
+  #define DDRDATA0CH0_CR_RXPERBITRANK2_Lane5_WID                       ( 4)
+  #define DDRDATA0CH0_CR_RXPERBITRANK2_Lane5_MSK                       (0x00F00000)
+  #define DDRDATA0CH0_CR_RXPERBITRANK2_Lane5_MAX                       (0x0000000F)
+  #define DDRDATA0CH0_CR_RXPERBITRANK2_Lane6_OFF                       (24)
+  #define DDRDATA0CH0_CR_RXPERBITRANK2_Lane6_WID                       ( 4)
+  #define DDRDATA0CH0_CR_RXPERBITRANK2_Lane6_MSK                       (0x0F000000)
+  #define DDRDATA0CH0_CR_RXPERBITRANK2_Lane6_MAX                       (0x0000000F)
+  #define DDRDATA0CH0_CR_RXPERBITRANK2_Lane7_OFF                       (28)
+  #define DDRDATA0CH0_CR_RXPERBITRANK2_Lane7_WID                       ( 4)
+  #define DDRDATA0CH0_CR_RXPERBITRANK2_Lane7_MSK                       (0xF0000000)
+  #define DDRDATA0CH0_CR_RXPERBITRANK2_Lane7_MAX                       (0x0000000F)
+
+#define DDRDATA0CH0_CR_RXPERBITRANK3_REG                             (0x0000001C)
+  #define DDRDATA0CH0_CR_RXPERBITRANK3_Lane0_OFF                       ( 0)
+  #define DDRDATA0CH0_CR_RXPERBITRANK3_Lane0_WID                       ( 4)
+  #define DDRDATA0CH0_CR_RXPERBITRANK3_Lane0_MSK                       (0x0000000F)
+  #define DDRDATA0CH0_CR_RXPERBITRANK3_Lane0_MAX                       (0x0000000F)
+  #define DDRDATA0CH0_CR_RXPERBITRANK3_Lane1_OFF                       ( 4)
+  #define DDRDATA0CH0_CR_RXPERBITRANK3_Lane1_WID                       ( 4)
+  #define DDRDATA0CH0_CR_RXPERBITRANK3_Lane1_MSK                       (0x000000F0)
+  #define DDRDATA0CH0_CR_RXPERBITRANK3_Lane1_MAX                       (0x0000000F)
+  #define DDRDATA0CH0_CR_RXPERBITRANK3_Lane2_OFF                       ( 8)
+  #define DDRDATA0CH0_CR_RXPERBITRANK3_Lane2_WID                       ( 4)
+  #define DDRDATA0CH0_CR_RXPERBITRANK3_Lane2_MSK                       (0x00000F00)
+  #define DDRDATA0CH0_CR_RXPERBITRANK3_Lane2_MAX                       (0x0000000F)
+  #define DDRDATA0CH0_CR_RXPERBITRANK3_Lane3_OFF                       (12)
+  #define DDRDATA0CH0_CR_RXPERBITRANK3_Lane3_WID                       ( 4)
+  #define DDRDATA0CH0_CR_RXPERBITRANK3_Lane3_MSK                       (0x0000F000)
+  #define DDRDATA0CH0_CR_RXPERBITRANK3_Lane3_MAX                       (0x0000000F)
+  #define DDRDATA0CH0_CR_RXPERBITRANK3_Lane4_OFF                       (16)
+  #define DDRDATA0CH0_CR_RXPERBITRANK3_Lane4_WID                       ( 4)
+  #define DDRDATA0CH0_CR_RXPERBITRANK3_Lane4_MSK                       (0x000F0000)
+  #define DDRDATA0CH0_CR_RXPERBITRANK3_Lane4_MAX                       (0x0000000F)
+  #define DDRDATA0CH0_CR_RXPERBITRANK3_Lane5_OFF                       (20)
+  #define DDRDATA0CH0_CR_RXPERBITRANK3_Lane5_WID                       ( 4)
+  #define DDRDATA0CH0_CR_RXPERBITRANK3_Lane5_MSK                       (0x00F00000)
+  #define DDRDATA0CH0_CR_RXPERBITRANK3_Lane5_MAX                       (0x0000000F)
+  #define DDRDATA0CH0_CR_RXPERBITRANK3_Lane6_OFF                       (24)
+  #define DDRDATA0CH0_CR_RXPERBITRANK3_Lane6_WID                       ( 4)
+  #define DDRDATA0CH0_CR_RXPERBITRANK3_Lane6_MSK                       (0x0F000000)
+  #define DDRDATA0CH0_CR_RXPERBITRANK3_Lane6_MAX                       (0x0000000F)
+  #define DDRDATA0CH0_CR_RXPERBITRANK3_Lane7_OFF                       (28)
+  #define DDRDATA0CH0_CR_RXPERBITRANK3_Lane7_WID                       ( 4)
+  #define DDRDATA0CH0_CR_RXPERBITRANK3_Lane7_MSK                       (0xF0000000)
+  #define DDRDATA0CH0_CR_RXPERBITRANK3_Lane7_MAX                       (0x0000000F)
+
+#define DDRDATA0CH0_CR_TXTRAINRANK0_REG                              (0x00000020)
+  #define DDRDATA0CH0_CR_TXTRAINRANK0_TxDqDelay_OFF                    ( 0)
+  #define DDRDATA0CH0_CR_TXTRAINRANK0_TxDqDelay_WID                    ( 9)
+  #define DDRDATA0CH0_CR_TXTRAINRANK0_TxDqDelay_MSK                    (0x000001FF)
+  #define DDRDATA0CH0_CR_TXTRAINRANK0_TxDqDelay_MAX                    (0x000001FF)
+  #define DDRDATA0CH0_CR_TXTRAINRANK0_TxDqsDelay_OFF                   ( 9)
+  #define DDRDATA0CH0_CR_TXTRAINRANK0_TxDqsDelay_WID                   ( 9)
+  #define DDRDATA0CH0_CR_TXTRAINRANK0_TxDqsDelay_MSK                   (0x0003FE00)
+  #define DDRDATA0CH0_CR_TXTRAINRANK0_TxDqsDelay_MAX                   (0x000001FF)
+  #define DDRDATA0CH0_CR_TXTRAINRANK0_Spare0_OFF                       (18)
+  #define DDRDATA0CH0_CR_TXTRAINRANK0_Spare0_WID                       ( 2)
+  #define DDRDATA0CH0_CR_TXTRAINRANK0_Spare0_MSK                       (0x000C0000)
+  #define DDRDATA0CH0_CR_TXTRAINRANK0_Spare0_MAX                       (0x00000003)
+  #define DDRDATA0CH0_CR_TXTRAINRANK0_TxEqualization_OFF               (20)
+  #define DDRDATA0CH0_CR_TXTRAINRANK0_TxEqualization_WID               ( 6)
+  #define DDRDATA0CH0_CR_TXTRAINRANK0_TxEqualization_MSK               (0x03F00000)
+  #define DDRDATA0CH0_CR_TXTRAINRANK0_TxEqualization_MAX               (0x0000003F)
+  #define DDRDATA0CH0_CR_TXTRAINRANK0_Spare1_OFF                       (26)
+  #define DDRDATA0CH0_CR_TXTRAINRANK0_Spare1_WID                       ( 6)
+  #define DDRDATA0CH0_CR_TXTRAINRANK0_Spare1_MSK                       (0xFC000000)
+  #define DDRDATA0CH0_CR_TXTRAINRANK0_Spare1_MAX                       (0x0000003F)
+
+#define DDRDATA0CH0_CR_TXTRAINRANK1_REG                              (0x00000024)
+  #define DDRDATA0CH0_CR_TXTRAINRANK1_TxDqDelay_OFF                    ( 0)
+  #define DDRDATA0CH0_CR_TXTRAINRANK1_TxDqDelay_WID                    ( 9)
+  #define DDRDATA0CH0_CR_TXTRAINRANK1_TxDqDelay_MSK                    (0x000001FF)
+  #define DDRDATA0CH0_CR_TXTRAINRANK1_TxDqDelay_MAX                    (0x000001FF)
+  #define DDRDATA0CH0_CR_TXTRAINRANK1_TxDqsDelay_OFF                   ( 9)
+  #define DDRDATA0CH0_CR_TXTRAINRANK1_TxDqsDelay_WID                   ( 9)
+  #define DDRDATA0CH0_CR_TXTRAINRANK1_TxDqsDelay_MSK                   (0x0003FE00)
+  #define DDRDATA0CH0_CR_TXTRAINRANK1_TxDqsDelay_MAX                   (0x000001FF)
+  #define DDRDATA0CH0_CR_TXTRAINRANK1_Spare0_OFF                       (18)
+  #define DDRDATA0CH0_CR_TXTRAINRANK1_Spare0_WID                       ( 2)
+  #define DDRDATA0CH0_CR_TXTRAINRANK1_Spare0_MSK                       (0x000C0000)
+  #define DDRDATA0CH0_CR_TXTRAINRANK1_Spare0_MAX                       (0x00000003)
+  #define DDRDATA0CH0_CR_TXTRAINRANK1_TxEqualization_OFF               (20)
+  #define DDRDATA0CH0_CR_TXTRAINRANK1_TxEqualization_WID               ( 6)
+  #define DDRDATA0CH0_CR_TXTRAINRANK1_TxEqualization_MSK               (0x03F00000)
+  #define DDRDATA0CH0_CR_TXTRAINRANK1_TxEqualization_MAX               (0x0000003F)
+  #define DDRDATA0CH0_CR_TXTRAINRANK1_Spare1_OFF                       (26)
+  #define DDRDATA0CH0_CR_TXTRAINRANK1_Spare1_WID                       ( 6)
+  #define DDRDATA0CH0_CR_TXTRAINRANK1_Spare1_MSK                       (0xFC000000)
+  #define DDRDATA0CH0_CR_TXTRAINRANK1_Spare1_MAX                       (0x0000003F)
+
+#define DDRDATA0CH0_CR_TXTRAINRANK2_REG                              (0x00000028)
+  #define DDRDATA0CH0_CR_TXTRAINRANK2_TxDqDelay_OFF                    ( 0)
+  #define DDRDATA0CH0_CR_TXTRAINRANK2_TxDqDelay_WID                    ( 9)
+  #define DDRDATA0CH0_CR_TXTRAINRANK2_TxDqDelay_MSK                    (0x000001FF)
+  #define DDRDATA0CH0_CR_TXTRAINRANK2_TxDqDelay_MAX                    (0x000001FF)
+  #define DDRDATA0CH0_CR_TXTRAINRANK2_TxDqsDelay_OFF                   ( 9)
+  #define DDRDATA0CH0_CR_TXTRAINRANK2_TxDqsDelay_WID                   ( 9)
+  #define DDRDATA0CH0_CR_TXTRAINRANK2_TxDqsDelay_MSK                   (0x0003FE00)
+  #define DDRDATA0CH0_CR_TXTRAINRANK2_TxDqsDelay_MAX                   (0x000001FF)
+  #define DDRDATA0CH0_CR_TXTRAINRANK2_Spare0_OFF                       (18)
+  #define DDRDATA0CH0_CR_TXTRAINRANK2_Spare0_WID                       ( 2)
+  #define DDRDATA0CH0_CR_TXTRAINRANK2_Spare0_MSK                       (0x000C0000)
+  #define DDRDATA0CH0_CR_TXTRAINRANK2_Spare0_MAX                       (0x00000003)
+  #define DDRDATA0CH0_CR_TXTRAINRANK2_TxEqualization_OFF               (20)
+  #define DDRDATA0CH0_CR_TXTRAINRANK2_TxEqualization_WID               ( 6)
+  #define DDRDATA0CH0_CR_TXTRAINRANK2_TxEqualization_MSK               (0x03F00000)
+  #define DDRDATA0CH0_CR_TXTRAINRANK2_TxEqualization_MAX               (0x0000003F)
+  #define DDRDATA0CH0_CR_TXTRAINRANK2_Spare1_OFF                       (26)
+  #define DDRDATA0CH0_CR_TXTRAINRANK2_Spare1_WID                       ( 6)
+  #define DDRDATA0CH0_CR_TXTRAINRANK2_Spare1_MSK                       (0xFC000000)
+  #define DDRDATA0CH0_CR_TXTRAINRANK2_Spare1_MAX                       (0x0000003F)
+
+#define DDRDATA0CH0_CR_TXTRAINRANK3_REG                              (0x0000002C)
+  #define DDRDATA0CH0_CR_TXTRAINRANK3_TxDqDelay_OFF                    ( 0)
+  #define DDRDATA0CH0_CR_TXTRAINRANK3_TxDqDelay_WID                    ( 9)
+  #define DDRDATA0CH0_CR_TXTRAINRANK3_TxDqDelay_MSK                    (0x000001FF)
+  #define DDRDATA0CH0_CR_TXTRAINRANK3_TxDqDelay_MAX                    (0x000001FF)
+  #define DDRDATA0CH0_CR_TXTRAINRANK3_TxDqsDelay_OFF                   ( 9)
+  #define DDRDATA0CH0_CR_TXTRAINRANK3_TxDqsDelay_WID                   ( 9)
+  #define DDRDATA0CH0_CR_TXTRAINRANK3_TxDqsDelay_MSK                   (0x0003FE00)
+  #define DDRDATA0CH0_CR_TXTRAINRANK3_TxDqsDelay_MAX                   (0x000001FF)
+  #define DDRDATA0CH0_CR_TXTRAINRANK3_Spare0_OFF                       (18)
+  #define DDRDATA0CH0_CR_TXTRAINRANK3_Spare0_WID                       ( 2)
+  #define DDRDATA0CH0_CR_TXTRAINRANK3_Spare0_MSK                       (0x000C0000)
+  #define DDRDATA0CH0_CR_TXTRAINRANK3_Spare0_MAX                       (0x00000003)
+  #define DDRDATA0CH0_CR_TXTRAINRANK3_TxEqualization_OFF               (20)
+  #define DDRDATA0CH0_CR_TXTRAINRANK3_TxEqualization_WID               ( 6)
+  #define DDRDATA0CH0_CR_TXTRAINRANK3_TxEqualization_MSK               (0x03F00000)
+  #define DDRDATA0CH0_CR_TXTRAINRANK3_TxEqualization_MAX               (0x0000003F)
+  #define DDRDATA0CH0_CR_TXTRAINRANK3_Spare1_OFF                       (26)
+  #define DDRDATA0CH0_CR_TXTRAINRANK3_Spare1_WID                       ( 6)
+  #define DDRDATA0CH0_CR_TXTRAINRANK3_Spare1_MSK                       (0xFC000000)
+  #define DDRDATA0CH0_CR_TXTRAINRANK3_Spare1_MAX                       (0x0000003F)
+
+#define DDRDATA0CH0_CR_TXPERBITRANK0_REG                             (0x00000030)
+  #define DDRDATA0CH0_CR_TXPERBITRANK0_Lane0_OFF                       ( 0)
+  #define DDRDATA0CH0_CR_TXPERBITRANK0_Lane0_WID                       ( 4)
+  #define DDRDATA0CH0_CR_TXPERBITRANK0_Lane0_MSK                       (0x0000000F)
+  #define DDRDATA0CH0_CR_TXPERBITRANK0_Lane0_MAX                       (0x0000000F)
+  #define DDRDATA0CH0_CR_TXPERBITRANK0_Lane1_OFF                       ( 4)
+  #define DDRDATA0CH0_CR_TXPERBITRANK0_Lane1_WID                       ( 4)
+  #define DDRDATA0CH0_CR_TXPERBITRANK0_Lane1_MSK                       (0x000000F0)
+  #define DDRDATA0CH0_CR_TXPERBITRANK0_Lane1_MAX                       (0x0000000F)
+  #define DDRDATA0CH0_CR_TXPERBITRANK0_Lane2_OFF                       ( 8)
+  #define DDRDATA0CH0_CR_TXPERBITRANK0_Lane2_WID                       ( 4)
+  #define DDRDATA0CH0_CR_TXPERBITRANK0_Lane2_MSK                       (0x00000F00)
+  #define DDRDATA0CH0_CR_TXPERBITRANK0_Lane2_MAX                       (0x0000000F)
+  #define DDRDATA0CH0_CR_TXPERBITRANK0_Lane3_OFF                       (12)
+  #define DDRDATA0CH0_CR_TXPERBITRANK0_Lane3_WID                       ( 4)
+  #define DDRDATA0CH0_CR_TXPERBITRANK0_Lane3_MSK                       (0x0000F000)
+  #define DDRDATA0CH0_CR_TXPERBITRANK0_Lane3_MAX                       (0x0000000F)
+  #define DDRDATA0CH0_CR_TXPERBITRANK0_Lane4_OFF                       (16)
+  #define DDRDATA0CH0_CR_TXPERBITRANK0_Lane4_WID                       ( 4)
+  #define DDRDATA0CH0_CR_TXPERBITRANK0_Lane4_MSK                       (0x000F0000)
+  #define DDRDATA0CH0_CR_TXPERBITRANK0_Lane4_MAX                       (0x0000000F)
+  #define DDRDATA0CH0_CR_TXPERBITRANK0_Lane5_OFF                       (20)
+  #define DDRDATA0CH0_CR_TXPERBITRANK0_Lane5_WID                       ( 4)
+  #define DDRDATA0CH0_CR_TXPERBITRANK0_Lane5_MSK                       (0x00F00000)
+  #define DDRDATA0CH0_CR_TXPERBITRANK0_Lane5_MAX                       (0x0000000F)
+  #define DDRDATA0CH0_CR_TXPERBITRANK0_Lane6_OFF                       (24)
+  #define DDRDATA0CH0_CR_TXPERBITRANK0_Lane6_WID                       ( 4)
+  #define DDRDATA0CH0_CR_TXPERBITRANK0_Lane6_MSK                       (0x0F000000)
+  #define DDRDATA0CH0_CR_TXPERBITRANK0_Lane6_MAX                       (0x0000000F)
+  #define DDRDATA0CH0_CR_TXPERBITRANK0_Lane7_OFF                       (28)
+  #define DDRDATA0CH0_CR_TXPERBITRANK0_Lane7_WID                       ( 4)
+  #define DDRDATA0CH0_CR_TXPERBITRANK0_Lane7_MSK                       (0xF0000000)
+  #define DDRDATA0CH0_CR_TXPERBITRANK0_Lane7_MAX                       (0x0000000F)
+
+#define DDRDATA0CH0_CR_TXPERBITRANK1_REG                             (0x00000034)
+  #define DDRDATA0CH0_CR_TXPERBITRANK1_Lane0_OFF                       ( 0)
+  #define DDRDATA0CH0_CR_TXPERBITRANK1_Lane0_WID                       ( 4)
+  #define DDRDATA0CH0_CR_TXPERBITRANK1_Lane0_MSK                       (0x0000000F)
+  #define DDRDATA0CH0_CR_TXPERBITRANK1_Lane0_MAX                       (0x0000000F)
+  #define DDRDATA0CH0_CR_TXPERBITRANK1_Lane1_OFF                       ( 4)
+  #define DDRDATA0CH0_CR_TXPERBITRANK1_Lane1_WID                       ( 4)
+  #define DDRDATA0CH0_CR_TXPERBITRANK1_Lane1_MSK                       (0x000000F0)
+  #define DDRDATA0CH0_CR_TXPERBITRANK1_Lane1_MAX                       (0x0000000F)
+  #define DDRDATA0CH0_CR_TXPERBITRANK1_Lane2_OFF                       ( 8)
+  #define DDRDATA0CH0_CR_TXPERBITRANK1_Lane2_WID                       ( 4)
+  #define DDRDATA0CH0_CR_TXPERBITRANK1_Lane2_MSK                       (0x00000F00)
+  #define DDRDATA0CH0_CR_TXPERBITRANK1_Lane2_MAX                       (0x0000000F)
+  #define DDRDATA0CH0_CR_TXPERBITRANK1_Lane3_OFF                       (12)
+  #define DDRDATA0CH0_CR_TXPERBITRANK1_Lane3_WID                       ( 4)
+  #define DDRDATA0CH0_CR_TXPERBITRANK1_Lane3_MSK                       (0x0000F000)
+  #define DDRDATA0CH0_CR_TXPERBITRANK1_Lane3_MAX                       (0x0000000F)
+  #define DDRDATA0CH0_CR_TXPERBITRANK1_Lane4_OFF                       (16)
+  #define DDRDATA0CH0_CR_TXPERBITRANK1_Lane4_WID                       ( 4)
+  #define DDRDATA0CH0_CR_TXPERBITRANK1_Lane4_MSK                       (0x000F0000)
+  #define DDRDATA0CH0_CR_TXPERBITRANK1_Lane4_MAX                       (0x0000000F)
+  #define DDRDATA0CH0_CR_TXPERBITRANK1_Lane5_OFF                       (20)
+  #define DDRDATA0CH0_CR_TXPERBITRANK1_Lane5_WID                       ( 4)
+  #define DDRDATA0CH0_CR_TXPERBITRANK1_Lane5_MSK                       (0x00F00000)
+  #define DDRDATA0CH0_CR_TXPERBITRANK1_Lane5_MAX                       (0x0000000F)
+  #define DDRDATA0CH0_CR_TXPERBITRANK1_Lane6_OFF                       (24)
+  #define DDRDATA0CH0_CR_TXPERBITRANK1_Lane6_WID                       ( 4)
+  #define DDRDATA0CH0_CR_TXPERBITRANK1_Lane6_MSK                       (0x0F000000)
+  #define DDRDATA0CH0_CR_TXPERBITRANK1_Lane6_MAX                       (0x0000000F)
+  #define DDRDATA0CH0_CR_TXPERBITRANK1_Lane7_OFF                       (28)
+  #define DDRDATA0CH0_CR_TXPERBITRANK1_Lane7_WID                       ( 4)
+  #define DDRDATA0CH0_CR_TXPERBITRANK1_Lane7_MSK                       (0xF0000000)
+  #define DDRDATA0CH0_CR_TXPERBITRANK1_Lane7_MAX                       (0x0000000F)
+
+#define DDRDATA0CH0_CR_TXPERBITRANK2_REG                             (0x00000038)
+  #define DDRDATA0CH0_CR_TXPERBITRANK2_Lane0_OFF                       ( 0)
+  #define DDRDATA0CH0_CR_TXPERBITRANK2_Lane0_WID                       ( 4)
+  #define DDRDATA0CH0_CR_TXPERBITRANK2_Lane0_MSK                       (0x0000000F)
+  #define DDRDATA0CH0_CR_TXPERBITRANK2_Lane0_MAX                       (0x0000000F)
+  #define DDRDATA0CH0_CR_TXPERBITRANK2_Lane1_OFF                       ( 4)
+  #define DDRDATA0CH0_CR_TXPERBITRANK2_Lane1_WID                       ( 4)
+  #define DDRDATA0CH0_CR_TXPERBITRANK2_Lane1_MSK                       (0x000000F0)
+  #define DDRDATA0CH0_CR_TXPERBITRANK2_Lane1_MAX                       (0x0000000F)
+  #define DDRDATA0CH0_CR_TXPERBITRANK2_Lane2_OFF                       ( 8)
+  #define DDRDATA0CH0_CR_TXPERBITRANK2_Lane2_WID                       ( 4)
+  #define DDRDATA0CH0_CR_TXPERBITRANK2_Lane2_MSK                       (0x00000F00)
+  #define DDRDATA0CH0_CR_TXPERBITRANK2_Lane2_MAX                       (0x0000000F)
+  #define DDRDATA0CH0_CR_TXPERBITRANK2_Lane3_OFF                       (12)
+  #define DDRDATA0CH0_CR_TXPERBITRANK2_Lane3_WID                       ( 4)
+  #define DDRDATA0CH0_CR_TXPERBITRANK2_Lane3_MSK                       (0x0000F000)
+  #define DDRDATA0CH0_CR_TXPERBITRANK2_Lane3_MAX                       (0x0000000F)
+  #define DDRDATA0CH0_CR_TXPERBITRANK2_Lane4_OFF                       (16)
+  #define DDRDATA0CH0_CR_TXPERBITRANK2_Lane4_WID                       ( 4)
+  #define DDRDATA0CH0_CR_TXPERBITRANK2_Lane4_MSK                       (0x000F0000)
+  #define DDRDATA0CH0_CR_TXPERBITRANK2_Lane4_MAX                       (0x0000000F)
+  #define DDRDATA0CH0_CR_TXPERBITRANK2_Lane5_OFF                       (20)
+  #define DDRDATA0CH0_CR_TXPERBITRANK2_Lane5_WID                       ( 4)
+  #define DDRDATA0CH0_CR_TXPERBITRANK2_Lane5_MSK                       (0x00F00000)
+  #define DDRDATA0CH0_CR_TXPERBITRANK2_Lane5_MAX                       (0x0000000F)
+  #define DDRDATA0CH0_CR_TXPERBITRANK2_Lane6_OFF                       (24)
+  #define DDRDATA0CH0_CR_TXPERBITRANK2_Lane6_WID                       ( 4)
+  #define DDRDATA0CH0_CR_TXPERBITRANK2_Lane6_MSK                       (0x0F000000)
+  #define DDRDATA0CH0_CR_TXPERBITRANK2_Lane6_MAX                       (0x0000000F)
+  #define DDRDATA0CH0_CR_TXPERBITRANK2_Lane7_OFF                       (28)
+  #define DDRDATA0CH0_CR_TXPERBITRANK2_Lane7_WID                       ( 4)
+  #define DDRDATA0CH0_CR_TXPERBITRANK2_Lane7_MSK                       (0xF0000000)
+  #define DDRDATA0CH0_CR_TXPERBITRANK2_Lane7_MAX                       (0x0000000F)
+
+#define DDRDATA0CH0_CR_TXPERBITRANK3_REG                             (0x0000003C)
+  #define DDRDATA0CH0_CR_TXPERBITRANK3_Lane0_OFF                       ( 0)
+  #define DDRDATA0CH0_CR_TXPERBITRANK3_Lane0_WID                       ( 4)
+  #define DDRDATA0CH0_CR_TXPERBITRANK3_Lane0_MSK                       (0x0000000F)
+  #define DDRDATA0CH0_CR_TXPERBITRANK3_Lane0_MAX                       (0x0000000F)
+  #define DDRDATA0CH0_CR_TXPERBITRANK3_Lane1_OFF                       ( 4)
+  #define DDRDATA0CH0_CR_TXPERBITRANK3_Lane1_WID                       ( 4)
+  #define DDRDATA0CH0_CR_TXPERBITRANK3_Lane1_MSK                       (0x000000F0)
+  #define DDRDATA0CH0_CR_TXPERBITRANK3_Lane1_MAX                       (0x0000000F)
+  #define DDRDATA0CH0_CR_TXPERBITRANK3_Lane2_OFF                       ( 8)
+  #define DDRDATA0CH0_CR_TXPERBITRANK3_Lane2_WID                       ( 4)
+  #define DDRDATA0CH0_CR_TXPERBITRANK3_Lane2_MSK                       (0x00000F00)
+  #define DDRDATA0CH0_CR_TXPERBITRANK3_Lane2_MAX                       (0x0000000F)
+  #define DDRDATA0CH0_CR_TXPERBITRANK3_Lane3_OFF                       (12)
+  #define DDRDATA0CH0_CR_TXPERBITRANK3_Lane3_WID                       ( 4)
+  #define DDRDATA0CH0_CR_TXPERBITRANK3_Lane3_MSK                       (0x0000F000)
+  #define DDRDATA0CH0_CR_TXPERBITRANK3_Lane3_MAX                       (0x0000000F)
+  #define DDRDATA0CH0_CR_TXPERBITRANK3_Lane4_OFF                       (16)
+  #define DDRDATA0CH0_CR_TXPERBITRANK3_Lane4_WID                       ( 4)
+  #define DDRDATA0CH0_CR_TXPERBITRANK3_Lane4_MSK                       (0x000F0000)
+  #define DDRDATA0CH0_CR_TXPERBITRANK3_Lane4_MAX                       (0x0000000F)
+  #define DDRDATA0CH0_CR_TXPERBITRANK3_Lane5_OFF                       (20)
+  #define DDRDATA0CH0_CR_TXPERBITRANK3_Lane5_WID                       ( 4)
+  #define DDRDATA0CH0_CR_TXPERBITRANK3_Lane5_MSK                       (0x00F00000)
+  #define DDRDATA0CH0_CR_TXPERBITRANK3_Lane5_MAX                       (0x0000000F)
+  #define DDRDATA0CH0_CR_TXPERBITRANK3_Lane6_OFF                       (24)
+  #define DDRDATA0CH0_CR_TXPERBITRANK3_Lane6_WID                       ( 4)
+  #define DDRDATA0CH0_CR_TXPERBITRANK3_Lane6_MSK                       (0x0F000000)
+  #define DDRDATA0CH0_CR_TXPERBITRANK3_Lane6_MAX                       (0x0000000F)
+  #define DDRDATA0CH0_CR_TXPERBITRANK3_Lane7_OFF                       (28)
+  #define DDRDATA0CH0_CR_TXPERBITRANK3_Lane7_WID                       ( 4)
+  #define DDRDATA0CH0_CR_TXPERBITRANK3_Lane7_MSK                       (0xF0000000)
+  #define DDRDATA0CH0_CR_TXPERBITRANK3_Lane7_MAX                       (0x0000000F)
+
+#define DDRDATA0CH0_CR_RCOMPDATA0_REG                                (0x00000040)
+  #define DDRDATA0CH0_CR_RCOMPDATA0_RcompDrvUp_OFF                     ( 0)
+  #define DDRDATA0CH0_CR_RCOMPDATA0_RcompDrvUp_WID                     ( 6)
+  #define DDRDATA0CH0_CR_RCOMPDATA0_RcompDrvUp_MSK                     (0x0000003F)
+  #define DDRDATA0CH0_CR_RCOMPDATA0_RcompDrvUp_MAX                     (0x0000003F)
+  #define DDRDATA0CH0_CR_RCOMPDATA0_Spare0_OFF                         ( 6)
+  #define DDRDATA0CH0_CR_RCOMPDATA0_Spare0_WID                         ( 3)
+  #define DDRDATA0CH0_CR_RCOMPDATA0_Spare0_MSK                         (0x000001C0)
+  #define DDRDATA0CH0_CR_RCOMPDATA0_Spare0_MAX                         (0x00000007)
+  #define DDRDATA0CH0_CR_RCOMPDATA0_RcompDrvDown_OFF                   ( 9)
+  #define DDRDATA0CH0_CR_RCOMPDATA0_RcompDrvDown_WID                   ( 6)
+  #define DDRDATA0CH0_CR_RCOMPDATA0_RcompDrvDown_MSK                   (0x00007E00)
+  #define DDRDATA0CH0_CR_RCOMPDATA0_RcompDrvDown_MAX                   (0x0000003F)
+  #define DDRDATA0CH0_CR_RCOMPDATA0_VTComp_OFF                         (15)
+  #define DDRDATA0CH0_CR_RCOMPDATA0_VTComp_WID                         ( 5)
+  #define DDRDATA0CH0_CR_RCOMPDATA0_VTComp_MSK                         (0x000F8000)
+  #define DDRDATA0CH0_CR_RCOMPDATA0_VTComp_MAX                         (0x0000001F)
+  #define DDRDATA0CH0_CR_RCOMPDATA0_TcoComp_OFF                        (20)
+  #define DDRDATA0CH0_CR_RCOMPDATA0_TcoComp_WID                        ( 6)
+  #define DDRDATA0CH0_CR_RCOMPDATA0_TcoComp_MSK                        (0x03F00000)
+  #define DDRDATA0CH0_CR_RCOMPDATA0_TcoComp_MAX                        (0x0000003F)
+  #define DDRDATA0CH0_CR_RCOMPDATA0_SlewRateComp_OFF                   (26)
+  #define DDRDATA0CH0_CR_RCOMPDATA0_SlewRateComp_WID                   ( 5)
+  #define DDRDATA0CH0_CR_RCOMPDATA0_SlewRateComp_MSK                   (0x7C000000)
+  #define DDRDATA0CH0_CR_RCOMPDATA0_SlewRateComp_MAX                   (0x0000001F)
+  #define DDRDATA0CH0_CR_RCOMPDATA0_Spare2_OFF                         (31)
+  #define DDRDATA0CH0_CR_RCOMPDATA0_Spare2_WID                         ( 1)
+  #define DDRDATA0CH0_CR_RCOMPDATA0_Spare2_MSK                         (0x80000000)
+  #define DDRDATA0CH0_CR_RCOMPDATA0_Spare2_MAX                         (0x00000001)
+
+#define DDRDATA0CH0_CR_RCOMPDATA1_REG                                (0x00000044)
+  #define DDRDATA0CH0_CR_RCOMPDATA1_RcompOdtUp_OFF                     ( 0)
+  #define DDRDATA0CH0_CR_RCOMPDATA1_RcompOdtUp_WID                     ( 6)
+  #define DDRDATA0CH0_CR_RCOMPDATA1_RcompOdtUp_MSK                     (0x0000003F)
+  #define DDRDATA0CH0_CR_RCOMPDATA1_RcompOdtUp_MAX                     (0x0000003F)
+  #define DDRDATA0CH0_CR_RCOMPDATA1_Spare0_OFF                         ( 6)
+  #define DDRDATA0CH0_CR_RCOMPDATA1_Spare0_WID                         ( 3)
+  #define DDRDATA0CH0_CR_RCOMPDATA1_Spare0_MSK                         (0x000001C0)
+  #define DDRDATA0CH0_CR_RCOMPDATA1_Spare0_MAX                         (0x00000007)
+  #define DDRDATA0CH0_CR_RCOMPDATA1_RcompOdtDown_OFF                   ( 9)
+  #define DDRDATA0CH0_CR_RCOMPDATA1_RcompOdtDown_WID                   ( 6)
+  #define DDRDATA0CH0_CR_RCOMPDATA1_RcompOdtDown_MSK                   (0x00007E00)
+  #define DDRDATA0CH0_CR_RCOMPDATA1_RcompOdtDown_MAX                   (0x0000003F)
+  #define DDRDATA0CH0_CR_RCOMPDATA1_Spare1_OFF                         (15)
+  #define DDRDATA0CH0_CR_RCOMPDATA1_Spare1_WID                         ( 1)
+  #define DDRDATA0CH0_CR_RCOMPDATA1_Spare1_MSK                         (0x00008000)
+  #define DDRDATA0CH0_CR_RCOMPDATA1_Spare1_MAX                         (0x00000001)
+  #define DDRDATA0CH0_CR_RCOMPDATA1_PanicDrvDn_OFF                     (16)
+  #define DDRDATA0CH0_CR_RCOMPDATA1_PanicDrvDn_WID                     ( 6)
+  #define DDRDATA0CH0_CR_RCOMPDATA1_PanicDrvDn_MSK                     (0x003F0000)
+  #define DDRDATA0CH0_CR_RCOMPDATA1_PanicDrvDn_MAX                     (0x0000003F)
+  #define DDRDATA0CH0_CR_RCOMPDATA1_PanicDrvUp_OFF                     (22)
+  #define DDRDATA0CH0_CR_RCOMPDATA1_PanicDrvUp_WID                     ( 6)
+  #define DDRDATA0CH0_CR_RCOMPDATA1_PanicDrvUp_MSK                     (0x0FC00000)
+  #define DDRDATA0CH0_CR_RCOMPDATA1_PanicDrvUp_MAX                     (0x0000003F)
+  #define DDRDATA0CH0_CR_RCOMPDATA1_LevelShifterComp_OFF               (28)
+  #define DDRDATA0CH0_CR_RCOMPDATA1_LevelShifterComp_WID               ( 3)
+  #define DDRDATA0CH0_CR_RCOMPDATA1_LevelShifterComp_MSK               (0x70000000)
+  #define DDRDATA0CH0_CR_RCOMPDATA1_LevelShifterComp_MAX               (0x00000007)
+  #define DDRDATA0CH0_CR_RCOMPDATA1_Spare2_OFF                         (31)
+  #define DDRDATA0CH0_CR_RCOMPDATA1_Spare2_WID                         ( 1)
+  #define DDRDATA0CH0_CR_RCOMPDATA1_Spare2_MSK                         (0x80000000)
+  #define DDRDATA0CH0_CR_RCOMPDATA1_Spare2_MAX                         (0x00000001)
+
+#define DDRDATA0CH0_CR_TXXTALK_REG                                   (0x00000048)
+  #define DDRDATA0CH0_CR_TXXTALK_Lane0_OFF                             ( 0)
+  #define DDRDATA0CH0_CR_TXXTALK_Lane0_WID                             ( 4)
+  #define DDRDATA0CH0_CR_TXXTALK_Lane0_MSK                             (0x0000000F)
+  #define DDRDATA0CH0_CR_TXXTALK_Lane0_MAX                             (0x0000000F)
+  #define DDRDATA0CH0_CR_TXXTALK_Lane1_OFF                             ( 4)
+  #define DDRDATA0CH0_CR_TXXTALK_Lane1_WID                             ( 4)
+  #define DDRDATA0CH0_CR_TXXTALK_Lane1_MSK                             (0x000000F0)
+  #define DDRDATA0CH0_CR_TXXTALK_Lane1_MAX                             (0x0000000F)
+  #define DDRDATA0CH0_CR_TXXTALK_Lane2_OFF                             ( 8)
+  #define DDRDATA0CH0_CR_TXXTALK_Lane2_WID                             ( 4)
+  #define DDRDATA0CH0_CR_TXXTALK_Lane2_MSK                             (0x00000F00)
+  #define DDRDATA0CH0_CR_TXXTALK_Lane2_MAX                             (0x0000000F)
+  #define DDRDATA0CH0_CR_TXXTALK_Lane3_OFF                             (12)
+  #define DDRDATA0CH0_CR_TXXTALK_Lane3_WID                             ( 4)
+  #define DDRDATA0CH0_CR_TXXTALK_Lane3_MSK                             (0x0000F000)
+  #define DDRDATA0CH0_CR_TXXTALK_Lane3_MAX                             (0x0000000F)
+  #define DDRDATA0CH0_CR_TXXTALK_Lane4_OFF                             (16)
+  #define DDRDATA0CH0_CR_TXXTALK_Lane4_WID                             ( 4)
+  #define DDRDATA0CH0_CR_TXXTALK_Lane4_MSK                             (0x000F0000)
+  #define DDRDATA0CH0_CR_TXXTALK_Lane4_MAX                             (0x0000000F)
+  #define DDRDATA0CH0_CR_TXXTALK_Lane5_OFF                             (20)
+  #define DDRDATA0CH0_CR_TXXTALK_Lane5_WID                             ( 4)
+  #define DDRDATA0CH0_CR_TXXTALK_Lane5_MSK                             (0x00F00000)
+  #define DDRDATA0CH0_CR_TXXTALK_Lane5_MAX                             (0x0000000F)
+  #define DDRDATA0CH0_CR_TXXTALK_Lane6_OFF                             (24)
+  #define DDRDATA0CH0_CR_TXXTALK_Lane6_WID                             ( 4)
+  #define DDRDATA0CH0_CR_TXXTALK_Lane6_MSK                             (0x0F000000)
+  #define DDRDATA0CH0_CR_TXXTALK_Lane6_MAX                             (0x0000000F)
+  #define DDRDATA0CH0_CR_TXXTALK_Lane7_OFF                             (28)
+  #define DDRDATA0CH0_CR_TXXTALK_Lane7_WID                             ( 4)
+  #define DDRDATA0CH0_CR_TXXTALK_Lane7_MSK                             (0xF0000000)
+  #define DDRDATA0CH0_CR_TXXTALK_Lane7_MAX                             (0x0000000F)
+
+#define DDRDATA0CH0_CR_RXOFFSETVDQ_REG                               (0x0000004C)
+  #define DDRDATA0CH0_CR_RXOFFSETVDQ_Lane0_OFF                         ( 0)
+  #define DDRDATA0CH0_CR_RXOFFSETVDQ_Lane0_WID                         ( 4)
+  #define DDRDATA0CH0_CR_RXOFFSETVDQ_Lane0_MSK                         (0x0000000F)
+  #define DDRDATA0CH0_CR_RXOFFSETVDQ_Lane0_MAX                         (0x0000000F)
+  #define DDRDATA0CH0_CR_RXOFFSETVDQ_Lane1_OFF                         ( 4)
+  #define DDRDATA0CH0_CR_RXOFFSETVDQ_Lane1_WID                         ( 4)
+  #define DDRDATA0CH0_CR_RXOFFSETVDQ_Lane1_MSK                         (0x000000F0)
+  #define DDRDATA0CH0_CR_RXOFFSETVDQ_Lane1_MAX                         (0x0000000F)
+  #define DDRDATA0CH0_CR_RXOFFSETVDQ_Lane2_OFF                         ( 8)
+  #define DDRDATA0CH0_CR_RXOFFSETVDQ_Lane2_WID                         ( 4)
+  #define DDRDATA0CH0_CR_RXOFFSETVDQ_Lane2_MSK                         (0x00000F00)
+  #define DDRDATA0CH0_CR_RXOFFSETVDQ_Lane2_MAX                         (0x0000000F)
+  #define DDRDATA0CH0_CR_RXOFFSETVDQ_Lane3_OFF                         (12)
+  #define DDRDATA0CH0_CR_RXOFFSETVDQ_Lane3_WID                         ( 4)
+  #define DDRDATA0CH0_CR_RXOFFSETVDQ_Lane3_MSK                         (0x0000F000)
+  #define DDRDATA0CH0_CR_RXOFFSETVDQ_Lane3_MAX                         (0x0000000F)
+  #define DDRDATA0CH0_CR_RXOFFSETVDQ_Lane4_OFF                         (16)
+  #define DDRDATA0CH0_CR_RXOFFSETVDQ_Lane4_WID                         ( 4)
+  #define DDRDATA0CH0_CR_RXOFFSETVDQ_Lane4_MSK                         (0x000F0000)
+  #define DDRDATA0CH0_CR_RXOFFSETVDQ_Lane4_MAX                         (0x0000000F)
+  #define DDRDATA0CH0_CR_RXOFFSETVDQ_Lane5_OFF                         (20)
+  #define DDRDATA0CH0_CR_RXOFFSETVDQ_Lane5_WID                         ( 4)
+  #define DDRDATA0CH0_CR_RXOFFSETVDQ_Lane5_MSK                         (0x00F00000)
+  #define DDRDATA0CH0_CR_RXOFFSETVDQ_Lane5_MAX                         (0x0000000F)
+  #define DDRDATA0CH0_CR_RXOFFSETVDQ_Lane6_OFF                         (24)
+  #define DDRDATA0CH0_CR_RXOFFSETVDQ_Lane6_WID                         ( 4)
+  #define DDRDATA0CH0_CR_RXOFFSETVDQ_Lane6_MSK                         (0x0F000000)
+  #define DDRDATA0CH0_CR_RXOFFSETVDQ_Lane6_MAX                         (0x0000000F)
+  #define DDRDATA0CH0_CR_RXOFFSETVDQ_Lane7_OFF                         (28)
+  #define DDRDATA0CH0_CR_RXOFFSETVDQ_Lane7_WID                         ( 4)
+  #define DDRDATA0CH0_CR_RXOFFSETVDQ_Lane7_MSK                         (0xF0000000)
+  #define DDRDATA0CH0_CR_RXOFFSETVDQ_Lane7_MAX                         (0x0000000F)
+
+#define DDRDATA0CH0_CR_DDRDATARESERVED_REG                           (0x00000050)
+  #define DDRDATA0CH0_CR_DDRDATARESERVED_Spare_OFF                     ( 0)
+  #define DDRDATA0CH0_CR_DDRDATARESERVED_Spare_WID                     (32)
+  #define DDRDATA0CH0_CR_DDRDATARESERVED_Spare_MSK                     (0xFFFFFFFF)
+  #define DDRDATA0CH0_CR_DDRDATARESERVED_Spare_MAX                     (0xFFFFFFFF)
+
+#define DDRDATA0CH0_CR_DATATRAINFEEDBACK_REG                         (0x00000054)
+  #define DDRDATA0CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_OFF       ( 0)
+  #define DDRDATA0CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_WID       ( 9)
+  #define DDRDATA0CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_MSK       (0x000001FF)
+  #define DDRDATA0CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_MAX       (0x000001FF)
+  #define DDRDATA0CH0_CR_DATATRAINFEEDBACK_Spare_OFF                   ( 9)
+  #define DDRDATA0CH0_CR_DATATRAINFEEDBACK_Spare_WID                   (23)
+  #define DDRDATA0CH0_CR_DATATRAINFEEDBACK_Spare_MSK                   (0xFFFFFE00)
+  #define DDRDATA0CH0_CR_DATATRAINFEEDBACK_Spare_MAX                   (0x007FFFFF)
+
+#define DDRDATA0CH0_CR_DLLPITESTANDADC_REG                           (0x00000058)
+  #define DDRDATA0CH0_CR_DLLPITESTANDADC_RunTest_OFF                   ( 0)
+  #define DDRDATA0CH0_CR_DLLPITESTANDADC_RunTest_WID                   ( 1)
+  #define DDRDATA0CH0_CR_DLLPITESTANDADC_RunTest_MSK                   (0x00000001)
+  #define DDRDATA0CH0_CR_DLLPITESTANDADC_RunTest_MAX                   (0x00000001)
+  #define DDRDATA0CH0_CR_DLLPITESTANDADC_RunTest_DEF                   (0x00000000)
+  #define DDRDATA0CH0_CR_DLLPITESTANDADC_Load_OFF                      ( 1)
+  #define DDRDATA0CH0_CR_DLLPITESTANDADC_Load_WID                      ( 1)
+  #define DDRDATA0CH0_CR_DLLPITESTANDADC_Load_MSK                      (0x00000002)
+  #define DDRDATA0CH0_CR_DLLPITESTANDADC_Load_MAX                      (0x00000001)
+  #define DDRDATA0CH0_CR_DLLPITESTANDADC_Load_DEF                      (0x00000000)
+  #define DDRDATA0CH0_CR_DLLPITESTANDADC_ModeHVM_OFF                   ( 2)
+  #define DDRDATA0CH0_CR_DLLPITESTANDADC_ModeHVM_WID                   ( 1)
+  #define DDRDATA0CH0_CR_DLLPITESTANDADC_ModeHVM_MSK                   (0x00000004)
+  #define DDRDATA0CH0_CR_DLLPITESTANDADC_ModeHVM_MAX                   (0x00000001)
+  #define DDRDATA0CH0_CR_DLLPITESTANDADC_ModeHVM_DEF                   (0x00000000)
+  #define DDRDATA0CH0_CR_DLLPITESTANDADC_ModeDV_OFF                    ( 3)
+  #define DDRDATA0CH0_CR_DLLPITESTANDADC_ModeDV_WID                    ( 1)
+  #define DDRDATA0CH0_CR_DLLPITESTANDADC_ModeDV_MSK                    (0x00000008)
+  #define DDRDATA0CH0_CR_DLLPITESTANDADC_ModeDV_MAX                    (0x00000001)
+  #define DDRDATA0CH0_CR_DLLPITESTANDADC_ModeDV_DEF                    (0x00000000)
+  #define DDRDATA0CH0_CR_DLLPITESTANDADC_ModeADC_OFF                   ( 4)
+  #define DDRDATA0CH0_CR_DLLPITESTANDADC_ModeADC_WID                   ( 1)
+  #define DDRDATA0CH0_CR_DLLPITESTANDADC_ModeADC_MSK                   (0x00000010)
+  #define DDRDATA0CH0_CR_DLLPITESTANDADC_ModeADC_MAX                   (0x00000001)
+  #define DDRDATA0CH0_CR_DLLPITESTANDADC_ModeADC_DEF                   (0x00000000)
+  #define DDRDATA0CH0_CR_DLLPITESTANDADC_LoadCount_OFF                 ( 5)
+  #define DDRDATA0CH0_CR_DLLPITESTANDADC_LoadCount_WID                 (10)
+  #define DDRDATA0CH0_CR_DLLPITESTANDADC_LoadCount_MSK                 (0x00007FE0)
+  #define DDRDATA0CH0_CR_DLLPITESTANDADC_LoadCount_MAX                 (0x000003FF)
+  #define DDRDATA0CH0_CR_DLLPITESTANDADC_CountStatus_OFF               (15)
+  #define DDRDATA0CH0_CR_DLLPITESTANDADC_CountStatus_WID               (10)
+  #define DDRDATA0CH0_CR_DLLPITESTANDADC_CountStatus_MSK               (0x01FF8000)
+  #define DDRDATA0CH0_CR_DLLPITESTANDADC_CountStatus_MAX               (0x000003FF)
+  #define DDRDATA0CH0_CR_DLLPITESTANDADC_CountStatus_DEF               (0x00000000)
+  #define DDRDATA0CH0_CR_DLLPITESTANDADC_Spare_OFF                     (25)
+  #define DDRDATA0CH0_CR_DLLPITESTANDADC_Spare_WID                     ( 7)
+  #define DDRDATA0CH0_CR_DLLPITESTANDADC_Spare_MSK                     (0xFE000000)
+  #define DDRDATA0CH0_CR_DLLPITESTANDADC_Spare_MAX                     (0x0000007F)
+
+#define DDRDATA0CH0_CR_DDRCRDATAOFFSETCOMP_REG                       (0x0000005C)
+  #define DDRDATA0CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_OFF     ( 0)
+  #define DDRDATA0CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_WID     ( 6)
+  #define DDRDATA0CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MSK     (0x0000003F)
+  #define DDRDATA0CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MAX     (0x0000003F)
+  #define DDRDATA0CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_DEF     (0x00000000)
+  #define DDRDATA0CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_OFF   ( 6)
+  #define DDRDATA0CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_WID   ( 6)
+  #define DDRDATA0CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MSK   (0x00000FC0)
+  #define DDRDATA0CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MAX   (0x0000003F)
+  #define DDRDATA0CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_DEF   (0x00000000)
+  #define DDRDATA0CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_OFF     (12)
+  #define DDRDATA0CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_WID     ( 5)
+  #define DDRDATA0CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MSK     (0x0001F000)
+  #define DDRDATA0CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MAX     (0x0000001F)
+  #define DDRDATA0CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_DEF     (0x00000000)
+  #define DDRDATA0CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_OFF   (17)
+  #define DDRDATA0CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_WID   ( 5)
+  #define DDRDATA0CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MSK   (0x003E0000)
+  #define DDRDATA0CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MAX   (0x0000001F)
+  #define DDRDATA0CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_DEF   (0x00000000)
+  #define DDRDATA0CH0_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_OFF       (22)
+  #define DDRDATA0CH0_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_WID       ( 5)
+  #define DDRDATA0CH0_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_MSK       (0x07C00000)
+  #define DDRDATA0CH0_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_MAX       (0x0000001F)
+  #define DDRDATA0CH0_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_DEF       (0x00000000)
+  #define DDRDATA0CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_OFF  (27)
+  #define DDRDATA0CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_WID  ( 5)
+  #define DDRDATA0CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MSK  (0xF8000000)
+  #define DDRDATA0CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MAX  (0x0000001F)
+  #define DDRDATA0CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_DEF  (0x00000000)
+
+#define DDRDATA0CH0_CR_DDRCRDATACONTROL1_REG                         (0x00000060)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_RefPi_OFF                   ( 0)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_RefPi_WID                   ( 4)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_RefPi_MSK                   (0x0000000F)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_RefPi_MAX                   (0x0000000F)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_RefPi_DEF                   (0x00000000)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_DllMask_OFF                 ( 4)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_DllMask_WID                 ( 2)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_DllMask_MSK                 (0x00000030)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_DllMask_MAX                 (0x00000003)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_DllMask_DEF                 (0x00000000)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_DllWeakLock_OFF             ( 6)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_DllWeakLock_WID             ( 1)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_DllWeakLock_MSK             (0x00000040)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_DllWeakLock_MAX             (0x00000001)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_DllWeakLock_DEF             (0x00000000)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_OFF      ( 7)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_WID      ( 3)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MSK      (0x00000380)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MAX      (0x00000007)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_DEF      (0x00000000)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_OFF               (10)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_WID               ( 3)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_MSK               (0x00001C00)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_MAX               (0x00000007)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_DEF               (0x00000000)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_OdtDelay_OFF                (13)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_OdtDelay_WID                ( 4)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_OdtDelay_MSK                (0x0001E000)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_OdtDelay_MAX                (0x0000000F)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_OdtDelay_DEF                (0x00000000)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_OdtDuration_OFF             (17)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_OdtDuration_WID             ( 3)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_OdtDuration_MSK             (0x000E0000)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_OdtDuration_MAX             (0x00000007)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_OdtDuration_DEF             (0x00000000)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_OFF           (20)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_WID           ( 4)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_MSK           (0x00F00000)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_MAX           (0x0000000F)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_DEF           (0x00000000)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_OFF        (24)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_WID        ( 3)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_MSK        (0x07000000)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_MAX        (0x00000007)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_DEF        (0x00000000)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_BurstEndODTDelay_OFF        (27)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_BurstEndODTDelay_WID        ( 3)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_BurstEndODTDelay_MSK        (0x38000000)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_BurstEndODTDelay_MAX        (0x00000007)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_BurstEndODTDelay_DEF        (0x00000000)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_OFF          (30)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_WID          ( 1)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_MSK          (0x40000000)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_MAX          (0x00000001)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_DEF          (0x00000000)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_Rsvd1_OFF                   (31)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_Rsvd1_WID                   ( 1)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_Rsvd1_MSK                   (0x80000000)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_Rsvd1_MAX                   (0x00000001)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_Rsvd1_DEF                   (0x00000000)
+
+#define DDRDATA0CH0_CR_DDRCRDATACONTROL2_REG                         (0x00000064)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_OFF            ( 0)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_WID            ( 5)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_MSK            (0x0000001F)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_MAX            (0x0000001F)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_DEF            (0x00000000)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_OFF             ( 5)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_WID             ( 1)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_MSK             (0x00000020)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_MAX             (0x00000001)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_DEF             (0x00000000)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_ForceRxOn_OFF               ( 6)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_ForceRxOn_WID               ( 1)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_ForceRxOn_MSK               (0x00000040)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_ForceRxOn_MAX               (0x00000001)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_ForceRxOn_DEF               (0x00000000)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_LeakerComp_OFF              ( 7)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_LeakerComp_WID              ( 2)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_LeakerComp_MSK              (0x00000180)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_LeakerComp_MAX              (0x00000003)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_LeakerComp_DEF              (0x00000000)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_OFF          ( 9)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_WID          ( 4)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_MSK          (0x00001E00)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_MAX          (0x0000000F)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_DEF          (0x00000008)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_OFF             (13)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_WID             ( 5)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_MSK             (0x0003E000)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_MAX             (0x0000001F)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_DEF             (0x00000011)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_OFF             (18)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_WID             ( 1)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_MSK             (0x00040000)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_MAX             (0x00000001)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_DEF             (0x00000000)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_Spare_OFF                   (19)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_Spare_WID                   (13)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_Spare_MSK                   (0xFFF80000)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_Spare_MAX                   (0x00001FFF)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_Spare_DEF                   (0x00000000)
+
+#define DDRDATA0CH0_CR_DDRCRVSSHIORVREFCONTROL_REG                   (0x0000006C)
+  #define DDRDATA0CH0_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_OFF    ( 0)
+  #define DDRDATA0CH0_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_WID    (24)
+  #define DDRDATA0CH0_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_MSK    (0x00FFFFFF)
+  #define DDRDATA0CH0_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_MAX    (0x00FFFFFF)
+  #define DDRDATA0CH0_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_DEF    (0x00000000)
+  #define DDRDATA0CH0_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_OFF        (24)
+  #define DDRDATA0CH0_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_WID        ( 8)
+  #define DDRDATA0CH0_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_MSK        (0xFF000000)
+  #define DDRDATA0CH0_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_MAX        (0x000000FF)
+  #define DDRDATA0CH0_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_DEF        (0x00000000)
+
+#define DDRDATA0CH0_CR_DDRCRDATAOFFSETTRAIN_REG                      (0x00000070)
+  #define DDRDATA0CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_OFF          ( 0)
+  #define DDRDATA0CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_WID          ( 6)
+  #define DDRDATA0CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MSK          (0x0000003F)
+  #define DDRDATA0CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MAX          (0x0000003F)
+  #define DDRDATA0CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_DEF          (0x00000000)
+  #define DDRDATA0CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_OFF          ( 6)
+  #define DDRDATA0CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_WID          ( 6)
+  #define DDRDATA0CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MSK          (0x00000FC0)
+  #define DDRDATA0CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MAX          (0x0000003F)
+  #define DDRDATA0CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_DEF          (0x00000000)
+  #define DDRDATA0CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_OFF           (12)
+  #define DDRDATA0CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_WID           ( 6)
+  #define DDRDATA0CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MSK           (0x0003F000)
+  #define DDRDATA0CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MAX           (0x0000003F)
+  #define DDRDATA0CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_DEF           (0x00000000)
+  #define DDRDATA0CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_OFF          (18)
+  #define DDRDATA0CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_WID          ( 6)
+  #define DDRDATA0CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MSK          (0x00FC0000)
+  #define DDRDATA0CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MAX          (0x0000003F)
+  #define DDRDATA0CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_DEF          (0x00000000)
+  #define DDRDATA0CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_OFF           (24)
+  #define DDRDATA0CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_WID           ( 7)
+  #define DDRDATA0CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MSK           (0x7F000000)
+  #define DDRDATA0CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MAX           (0x0000007F)
+  #define DDRDATA0CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_DEF           (0x00000000)
+  #define DDRDATA0CH0_CR_DDRCRDATAOFFSETTRAIN_Spare_OFF                (31)
+  #define DDRDATA0CH0_CR_DDRCRDATAOFFSETTRAIN_Spare_WID                ( 1)
+  #define DDRDATA0CH0_CR_DDRCRDATAOFFSETTRAIN_Spare_MSK                (0x80000000)
+  #define DDRDATA0CH0_CR_DDRCRDATAOFFSETTRAIN_Spare_MAX                (0x00000001)
+  #define DDRDATA0CH0_CR_DDRCRDATAOFFSETTRAIN_Spare_DEF                (0x00000000)
+
+#define DDRDATA0CH0_CR_DDRCRDATACONTROL0_REG                         (0x00000074)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_OFF          ( 0)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_WID          ( 1)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_MSK          (0x00000001)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_MAX          (0x00000001)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_DEF          (0x00000000)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_OFF          ( 1)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_WID          ( 1)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_MSK          (0x00000002)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_MAX          (0x00000001)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_DEF          (0x00000000)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_OFF          ( 2)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_WID          ( 1)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_MSK          (0x00000004)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_MAX          (0x00000001)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_DEF          (0x00000000)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_OFF    ( 3)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_WID    ( 1)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MSK    (0x00000008)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MAX    (0x00000001)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_DEF    (0x00000000)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_TxOn_OFF                    ( 4)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_TxOn_WID                    ( 1)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_TxOn_MSK                    (0x00000010)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_TxOn_MAX                    (0x00000001)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_TxOn_DEF                    (0x00000000)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RfOn_OFF                    ( 5)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RfOn_WID                    ( 1)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RfOn_MSK                    (0x00000020)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RfOn_MAX                    (0x00000001)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RfOn_DEF                    (0x00000000)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RxPiOn_OFF                  ( 6)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RxPiOn_WID                  ( 1)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RxPiOn_MSK                  (0x00000040)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RxPiOn_MAX                  (0x00000001)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RxPiOn_DEF                  (0x00000000)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_TxPiOn_OFF                  ( 7)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_TxPiOn_WID                  ( 1)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_TxPiOn_MSK                  (0x00000080)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_TxPiOn_MAX                  (0x00000001)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_TxPiOn_DEF                  (0x00000000)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_OFF        ( 8)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_WID        ( 1)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_MSK        (0x00000100)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_MAX        (0x00000001)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_DEF        (0x00000000)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_OFF        ( 9)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_WID        ( 1)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MSK        (0x00000200)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MAX        (0x00000001)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_DEF        (0x00000000)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_TxDisable_OFF               (10)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_TxDisable_WID               ( 1)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_TxDisable_MSK               (0x00000400)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_TxDisable_MAX               (0x00000001)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_TxDisable_DEF               (0x00000000)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RxDisable_OFF               (11)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RxDisable_WID               ( 1)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RxDisable_MSK               (0x00000800)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RxDisable_MAX               (0x00000001)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RxDisable_DEF               (0x00000000)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_TxLong_OFF                  (12)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_TxLong_WID                  ( 1)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_TxLong_MSK                  (0x00001000)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_TxLong_MAX                  (0x00000001)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_TxLong_DEF                  (0x00000000)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_OFF               (13)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_WID               ( 2)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_MSK               (0x00006000)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_MAX               (0x00000003)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_DEF               (0x00000000)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RxReadPointer_OFF           (15)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RxReadPointer_WID           ( 3)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RxReadPointer_MSK           (0x00038000)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RxReadPointer_MAX           (0x00000007)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RxReadPointer_DEF           (0x00000000)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_DriverSegmentEnable_OFF     (18)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_DriverSegmentEnable_WID     ( 1)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_DriverSegmentEnable_MSK     (0x00040000)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_DriverSegmentEnable_MAX     (0x00000001)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_DriverSegmentEnable_DEF     (0x00000000)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_DataVccddqHi_OFF            (19)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_DataVccddqHi_WID            ( 1)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_DataVccddqHi_MSK            (0x00080000)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_DataVccddqHi_MAX            (0x00000001)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_DataVccddqHi_DEF            (0x00000000)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_ReadRFRd_OFF                (20)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_ReadRFRd_WID                ( 1)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_ReadRFRd_MSK                (0x00100000)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_ReadRFRd_MAX                (0x00000001)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_ReadRFRd_DEF                (0x00000000)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_ReadRFWr_OFF                (21)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_ReadRFWr_WID                ( 1)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_ReadRFWr_MSK                (0x00200000)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_ReadRFWr_MAX                (0x00000001)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_ReadRFWr_DEF                (0x00000000)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_ReadRFRank_OFF              (22)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_ReadRFRank_WID              ( 2)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_ReadRFRank_MSK              (0x00C00000)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_ReadRFRank_MAX              (0x00000003)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_ReadRFRank_DEF              (0x00000000)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_OFF              (24)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_WID              ( 1)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_MSK              (0x01000000)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_MAX              (0x00000001)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_DEF              (0x00000000)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_OdtSampOff_OFF              (25)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_OdtSampOff_WID              ( 1)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_OdtSampOff_MSK              (0x02000000)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_OdtSampOff_MAX              (0x00000001)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_OdtSampOff_DEF              (0x00000000)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_OFF        (26)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_WID        ( 1)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_MSK        (0x04000000)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_MAX        (0x00000001)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_DEF        (0x00000000)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_OFF         (27)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_WID         ( 1)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MSK         (0x08000000)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MAX         (0x00000001)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_DEF         (0x00000000)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_OFF              (28)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_WID              ( 1)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_MSK              (0x10000000)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_MAX              (0x00000001)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_DEF              (0x00000000)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_EnReadPreamble_OFF          (29)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_EnReadPreamble_WID          ( 1)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_EnReadPreamble_MSK          (0x20000000)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_EnReadPreamble_MAX          (0x00000001)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_EnReadPreamble_DEF          (0x00000000)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_OFF         (30)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_WID         ( 1)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MSK         (0x40000000)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MAX         (0x00000001)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_DEF         (0x00000000)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_OFF            (31)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_WID            ( 1)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_MSK            (0x80000000)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_MAX            (0x00000001)
+  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_DEF            (0x00000000)
+
+#define DDRDATA0CH0_CR_DDRCRVREFADJUST1_REG                          (0x00000078)
+  #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_CAVrefCtl_OFF                ( 0)
+  #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_CAVrefCtl_WID                ( 7)
+  #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_CAVrefCtl_MSK                (0x0000007F)
+  #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_CAVrefCtl_MAX                (0x0000007F)
+  #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_CAVrefCtl_DEF                (0x00000000)
+  #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_Ch1VrefCtl_OFF               ( 7)
+  #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_Ch1VrefCtl_WID               ( 7)
+  #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_Ch1VrefCtl_MSK               (0x00003F80)
+  #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_Ch1VrefCtl_MAX               (0x0000007F)
+  #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_Ch1VrefCtl_DEF               (0x00000000)
+  #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_Ch0VrefCtl_OFF               (14)
+  #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_Ch0VrefCtl_WID               ( 7)
+  #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_Ch0VrefCtl_MSK               (0x001FC000)
+  #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_Ch0VrefCtl_MAX               (0x0000007F)
+  #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_Ch0VrefCtl_DEF               (0x00000000)
+  #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCA_OFF             (21)
+  #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCA_WID             ( 1)
+  #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCA_MSK             (0x00200000)
+  #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCA_MAX             (0x00000001)
+  #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCA_DEF             (0x00000000)
+  #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_OFF            (22)
+  #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_WID            ( 1)
+  #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_MSK            (0x00400000)
+  #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_MAX            (0x00000001)
+  #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_DEF            (0x00000000)
+  #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_OFF            (23)
+  #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_WID            ( 1)
+  #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_MSK            (0x00800000)
+  #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_MAX            (0x00000001)
+  #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_DEF            (0x00000000)
+  #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_HiZTimerCtrl_OFF             (24)
+  #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_HiZTimerCtrl_WID             ( 2)
+  #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_HiZTimerCtrl_MSK             (0x03000000)
+  #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_HiZTimerCtrl_MAX             (0x00000003)
+  #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_HiZTimerCtrl_DEF             (0x00000000)
+  #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_OFF            (26)
+  #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_WID            ( 1)
+  #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_MSK            (0x04000000)
+  #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_MAX            (0x00000001)
+  #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_DEF            (0x00000000)
+  #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_Rsvd_OFF                     (27)
+  #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_Rsvd_WID                     ( 2)
+  #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_Rsvd_MSK                     (0x18000000)
+  #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_Rsvd_MAX                     (0x00000003)
+  #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_Rsvd_DEF                     (0x00000000)
+  #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_caSlowBW_OFF                 (29)
+  #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_caSlowBW_WID                 ( 1)
+  #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_caSlowBW_MSK                 (0x20000000)
+  #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_caSlowBW_MAX                 (0x00000001)
+  #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_caSlowBW_DEF                 (0x00000000)
+  #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_ch0SlowBW_OFF                (30)
+  #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_ch0SlowBW_WID                ( 1)
+  #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_ch0SlowBW_MSK                (0x40000000)
+  #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_ch0SlowBW_MAX                (0x00000001)
+  #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_ch0SlowBW_DEF                (0x00000000)
+  #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_ch1SlowBW_OFF                (31)
+  #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_ch1SlowBW_WID                ( 1)
+  #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_ch1SlowBW_MSK                (0x80000000)
+  #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_ch1SlowBW_MAX                (0x00000001)
+  #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_ch1SlowBW_DEF                (0x00000000)
+
+#define DDRDATA0CH1_CR_RXTRAINRANK0_REG                              (0x00000100)
+  #define DDRDATA0CH1_CR_RXTRAINRANK0_RxRcvEnPi_OFF                    ( 0)
+  #define DDRDATA0CH1_CR_RXTRAINRANK0_RxRcvEnPi_WID                    ( 9)
+  #define DDRDATA0CH1_CR_RXTRAINRANK0_RxRcvEnPi_MSK                    (0x000001FF)
+  #define DDRDATA0CH1_CR_RXTRAINRANK0_RxRcvEnPi_MAX                    (0x000001FF)
+  #define DDRDATA0CH1_CR_RXTRAINRANK0_RxDqsPPi_OFF                     ( 9)
+  #define DDRDATA0CH1_CR_RXTRAINRANK0_RxDqsPPi_WID                     ( 6)
+  #define DDRDATA0CH1_CR_RXTRAINRANK0_RxDqsPPi_MSK                     (0x00007E00)
+  #define DDRDATA0CH1_CR_RXTRAINRANK0_RxDqsPPi_MAX                     (0x0000003F)
+  #define DDRDATA0CH1_CR_RXTRAINRANK0_RxEq_OFF                         (15)
+  #define DDRDATA0CH1_CR_RXTRAINRANK0_RxEq_WID                         ( 5)
+  #define DDRDATA0CH1_CR_RXTRAINRANK0_RxEq_MSK                         (0x000F8000)
+  #define DDRDATA0CH1_CR_RXTRAINRANK0_RxEq_MAX                         (0x0000001F)
+  #define DDRDATA0CH1_CR_RXTRAINRANK0_RxDqsNPi_OFF                     (20)
+  #define DDRDATA0CH1_CR_RXTRAINRANK0_RxDqsNPi_WID                     ( 6)
+  #define DDRDATA0CH1_CR_RXTRAINRANK0_RxDqsNPi_MSK                     (0x03F00000)
+  #define DDRDATA0CH1_CR_RXTRAINRANK0_RxDqsNPi_MAX                     (0x0000003F)
+  #define DDRDATA0CH1_CR_RXTRAINRANK0_RxVref_OFF                       (26)
+  #define DDRDATA0CH1_CR_RXTRAINRANK0_RxVref_WID                       ( 6)
+  #define DDRDATA0CH1_CR_RXTRAINRANK0_RxVref_MSK                       (0xFC000000)
+  #define DDRDATA0CH1_CR_RXTRAINRANK0_RxVref_MAX                       (0x0000003F)
+
+#define DDRDATA0CH1_CR_RXTRAINRANK1_REG                              (0x00000104)
+  #define DDRDATA0CH1_CR_RXTRAINRANK1_RxRcvEnPi_OFF                    ( 0)
+  #define DDRDATA0CH1_CR_RXTRAINRANK1_RxRcvEnPi_WID                    ( 9)
+  #define DDRDATA0CH1_CR_RXTRAINRANK1_RxRcvEnPi_MSK                    (0x000001FF)
+  #define DDRDATA0CH1_CR_RXTRAINRANK1_RxRcvEnPi_MAX                    (0x000001FF)
+  #define DDRDATA0CH1_CR_RXTRAINRANK1_RxDqsPPi_OFF                     ( 9)
+  #define DDRDATA0CH1_CR_RXTRAINRANK1_RxDqsPPi_WID                     ( 6)
+  #define DDRDATA0CH1_CR_RXTRAINRANK1_RxDqsPPi_MSK                     (0x00007E00)
+  #define DDRDATA0CH1_CR_RXTRAINRANK1_RxDqsPPi_MAX                     (0x0000003F)
+  #define DDRDATA0CH1_CR_RXTRAINRANK1_RxEq_OFF                         (15)
+  #define DDRDATA0CH1_CR_RXTRAINRANK1_RxEq_WID                         ( 5)
+  #define DDRDATA0CH1_CR_RXTRAINRANK1_RxEq_MSK                         (0x000F8000)
+  #define DDRDATA0CH1_CR_RXTRAINRANK1_RxEq_MAX                         (0x0000001F)
+  #define DDRDATA0CH1_CR_RXTRAINRANK1_RxDqsNPi_OFF                     (20)
+  #define DDRDATA0CH1_CR_RXTRAINRANK1_RxDqsNPi_WID                     ( 6)
+  #define DDRDATA0CH1_CR_RXTRAINRANK1_RxDqsNPi_MSK                     (0x03F00000)
+  #define DDRDATA0CH1_CR_RXTRAINRANK1_RxDqsNPi_MAX                     (0x0000003F)
+  #define DDRDATA0CH1_CR_RXTRAINRANK1_RxVref_OFF                       (26)
+  #define DDRDATA0CH1_CR_RXTRAINRANK1_RxVref_WID                       ( 6)
+  #define DDRDATA0CH1_CR_RXTRAINRANK1_RxVref_MSK                       (0xFC000000)
+  #define DDRDATA0CH1_CR_RXTRAINRANK1_RxVref_MAX                       (0x0000003F)
+
+#define DDRDATA0CH1_CR_RXTRAINRANK2_REG                              (0x00000108)
+  #define DDRDATA0CH1_CR_RXTRAINRANK2_RxRcvEnPi_OFF                    ( 0)
+  #define DDRDATA0CH1_CR_RXTRAINRANK2_RxRcvEnPi_WID                    ( 9)
+  #define DDRDATA0CH1_CR_RXTRAINRANK2_RxRcvEnPi_MSK                    (0x000001FF)
+  #define DDRDATA0CH1_CR_RXTRAINRANK2_RxRcvEnPi_MAX                    (0x000001FF)
+  #define DDRDATA0CH1_CR_RXTRAINRANK2_RxDqsPPi_OFF                     ( 9)
+  #define DDRDATA0CH1_CR_RXTRAINRANK2_RxDqsPPi_WID                     ( 6)
+  #define DDRDATA0CH1_CR_RXTRAINRANK2_RxDqsPPi_MSK                     (0x00007E00)
+  #define DDRDATA0CH1_CR_RXTRAINRANK2_RxDqsPPi_MAX                     (0x0000003F)
+  #define DDRDATA0CH1_CR_RXTRAINRANK2_RxEq_OFF                         (15)
+  #define DDRDATA0CH1_CR_RXTRAINRANK2_RxEq_WID                         ( 5)
+  #define DDRDATA0CH1_CR_RXTRAINRANK2_RxEq_MSK                         (0x000F8000)
+  #define DDRDATA0CH1_CR_RXTRAINRANK2_RxEq_MAX                         (0x0000001F)
+  #define DDRDATA0CH1_CR_RXTRAINRANK2_RxDqsNPi_OFF                     (20)
+  #define DDRDATA0CH1_CR_RXTRAINRANK2_RxDqsNPi_WID                     ( 6)
+  #define DDRDATA0CH1_CR_RXTRAINRANK2_RxDqsNPi_MSK                     (0x03F00000)
+  #define DDRDATA0CH1_CR_RXTRAINRANK2_RxDqsNPi_MAX                     (0x0000003F)
+  #define DDRDATA0CH1_CR_RXTRAINRANK2_RxVref_OFF                       (26)
+  #define DDRDATA0CH1_CR_RXTRAINRANK2_RxVref_WID                       ( 6)
+  #define DDRDATA0CH1_CR_RXTRAINRANK2_RxVref_MSK                       (0xFC000000)
+  #define DDRDATA0CH1_CR_RXTRAINRANK2_RxVref_MAX                       (0x0000003F)
+
+#define DDRDATA0CH1_CR_RXTRAINRANK3_REG                              (0x0000010C)
+  #define DDRDATA0CH1_CR_RXTRAINRANK3_RxRcvEnPi_OFF                    ( 0)
+  #define DDRDATA0CH1_CR_RXTRAINRANK3_RxRcvEnPi_WID                    ( 9)
+  #define DDRDATA0CH1_CR_RXTRAINRANK3_RxRcvEnPi_MSK                    (0x000001FF)
+  #define DDRDATA0CH1_CR_RXTRAINRANK3_RxRcvEnPi_MAX                    (0x000001FF)
+  #define DDRDATA0CH1_CR_RXTRAINRANK3_RxDqsPPi_OFF                     ( 9)
+  #define DDRDATA0CH1_CR_RXTRAINRANK3_RxDqsPPi_WID                     ( 6)
+  #define DDRDATA0CH1_CR_RXTRAINRANK3_RxDqsPPi_MSK                     (0x00007E00)
+  #define DDRDATA0CH1_CR_RXTRAINRANK3_RxDqsPPi_MAX                     (0x0000003F)
+  #define DDRDATA0CH1_CR_RXTRAINRANK3_RxEq_OFF                         (15)
+  #define DDRDATA0CH1_CR_RXTRAINRANK3_RxEq_WID                         ( 5)
+  #define DDRDATA0CH1_CR_RXTRAINRANK3_RxEq_MSK                         (0x000F8000)
+  #define DDRDATA0CH1_CR_RXTRAINRANK3_RxEq_MAX                         (0x0000001F)
+  #define DDRDATA0CH1_CR_RXTRAINRANK3_RxDqsNPi_OFF                     (20)
+  #define DDRDATA0CH1_CR_RXTRAINRANK3_RxDqsNPi_WID                     ( 6)
+  #define DDRDATA0CH1_CR_RXTRAINRANK3_RxDqsNPi_MSK                     (0x03F00000)
+  #define DDRDATA0CH1_CR_RXTRAINRANK3_RxDqsNPi_MAX                     (0x0000003F)
+  #define DDRDATA0CH1_CR_RXTRAINRANK3_RxVref_OFF                       (26)
+  #define DDRDATA0CH1_CR_RXTRAINRANK3_RxVref_WID                       ( 6)
+  #define DDRDATA0CH1_CR_RXTRAINRANK3_RxVref_MSK                       (0xFC000000)
+  #define DDRDATA0CH1_CR_RXTRAINRANK3_RxVref_MAX                       (0x0000003F)
+
+#define DDRDATA0CH1_CR_RXPERBITRANK0_REG                             (0x00000110)
+  #define DDRDATA0CH1_CR_RXPERBITRANK0_Lane0_OFF                       ( 0)
+  #define DDRDATA0CH1_CR_RXPERBITRANK0_Lane0_WID                       ( 4)
+  #define DDRDATA0CH1_CR_RXPERBITRANK0_Lane0_MSK                       (0x0000000F)
+  #define DDRDATA0CH1_CR_RXPERBITRANK0_Lane0_MAX                       (0x0000000F)
+  #define DDRDATA0CH1_CR_RXPERBITRANK0_Lane1_OFF                       ( 4)
+  #define DDRDATA0CH1_CR_RXPERBITRANK0_Lane1_WID                       ( 4)
+  #define DDRDATA0CH1_CR_RXPERBITRANK0_Lane1_MSK                       (0x000000F0)
+  #define DDRDATA0CH1_CR_RXPERBITRANK0_Lane1_MAX                       (0x0000000F)
+  #define DDRDATA0CH1_CR_RXPERBITRANK0_Lane2_OFF                       ( 8)
+  #define DDRDATA0CH1_CR_RXPERBITRANK0_Lane2_WID                       ( 4)
+  #define DDRDATA0CH1_CR_RXPERBITRANK0_Lane2_MSK                       (0x00000F00)
+  #define DDRDATA0CH1_CR_RXPERBITRANK0_Lane2_MAX                       (0x0000000F)
+  #define DDRDATA0CH1_CR_RXPERBITRANK0_Lane3_OFF                       (12)
+  #define DDRDATA0CH1_CR_RXPERBITRANK0_Lane3_WID                       ( 4)
+  #define DDRDATA0CH1_CR_RXPERBITRANK0_Lane3_MSK                       (0x0000F000)
+  #define DDRDATA0CH1_CR_RXPERBITRANK0_Lane3_MAX                       (0x0000000F)
+  #define DDRDATA0CH1_CR_RXPERBITRANK0_Lane4_OFF                       (16)
+  #define DDRDATA0CH1_CR_RXPERBITRANK0_Lane4_WID                       ( 4)
+  #define DDRDATA0CH1_CR_RXPERBITRANK0_Lane4_MSK                       (0x000F0000)
+  #define DDRDATA0CH1_CR_RXPERBITRANK0_Lane4_MAX                       (0x0000000F)
+  #define DDRDATA0CH1_CR_RXPERBITRANK0_Lane5_OFF                       (20)
+  #define DDRDATA0CH1_CR_RXPERBITRANK0_Lane5_WID                       ( 4)
+  #define DDRDATA0CH1_CR_RXPERBITRANK0_Lane5_MSK                       (0x00F00000)
+  #define DDRDATA0CH1_CR_RXPERBITRANK0_Lane5_MAX                       (0x0000000F)
+  #define DDRDATA0CH1_CR_RXPERBITRANK0_Lane6_OFF                       (24)
+  #define DDRDATA0CH1_CR_RXPERBITRANK0_Lane6_WID                       ( 4)
+  #define DDRDATA0CH1_CR_RXPERBITRANK0_Lane6_MSK                       (0x0F000000)
+  #define DDRDATA0CH1_CR_RXPERBITRANK0_Lane6_MAX                       (0x0000000F)
+  #define DDRDATA0CH1_CR_RXPERBITRANK0_Lane7_OFF                       (28)
+  #define DDRDATA0CH1_CR_RXPERBITRANK0_Lane7_WID                       ( 4)
+  #define DDRDATA0CH1_CR_RXPERBITRANK0_Lane7_MSK                       (0xF0000000)
+  #define DDRDATA0CH1_CR_RXPERBITRANK0_Lane7_MAX                       (0x0000000F)
+
+#define DDRDATA0CH1_CR_RXPERBITRANK1_REG                             (0x00000114)
+  #define DDRDATA0CH1_CR_RXPERBITRANK1_Lane0_OFF                       ( 0)
+  #define DDRDATA0CH1_CR_RXPERBITRANK1_Lane0_WID                       ( 4)
+  #define DDRDATA0CH1_CR_RXPERBITRANK1_Lane0_MSK                       (0x0000000F)
+  #define DDRDATA0CH1_CR_RXPERBITRANK1_Lane0_MAX                       (0x0000000F)
+  #define DDRDATA0CH1_CR_RXPERBITRANK1_Lane1_OFF                       ( 4)
+  #define DDRDATA0CH1_CR_RXPERBITRANK1_Lane1_WID                       ( 4)
+  #define DDRDATA0CH1_CR_RXPERBITRANK1_Lane1_MSK                       (0x000000F0)
+  #define DDRDATA0CH1_CR_RXPERBITRANK1_Lane1_MAX                       (0x0000000F)
+  #define DDRDATA0CH1_CR_RXPERBITRANK1_Lane2_OFF                       ( 8)
+  #define DDRDATA0CH1_CR_RXPERBITRANK1_Lane2_WID                       ( 4)
+  #define DDRDATA0CH1_CR_RXPERBITRANK1_Lane2_MSK                       (0x00000F00)
+  #define DDRDATA0CH1_CR_RXPERBITRANK1_Lane2_MAX                       (0x0000000F)
+  #define DDRDATA0CH1_CR_RXPERBITRANK1_Lane3_OFF                       (12)
+  #define DDRDATA0CH1_CR_RXPERBITRANK1_Lane3_WID                       ( 4)
+  #define DDRDATA0CH1_CR_RXPERBITRANK1_Lane3_MSK                       (0x0000F000)
+  #define DDRDATA0CH1_CR_RXPERBITRANK1_Lane3_MAX                       (0x0000000F)
+  #define DDRDATA0CH1_CR_RXPERBITRANK1_Lane4_OFF                       (16)
+  #define DDRDATA0CH1_CR_RXPERBITRANK1_Lane4_WID                       ( 4)
+  #define DDRDATA0CH1_CR_RXPERBITRANK1_Lane4_MSK                       (0x000F0000)
+  #define DDRDATA0CH1_CR_RXPERBITRANK1_Lane4_MAX                       (0x0000000F)
+  #define DDRDATA0CH1_CR_RXPERBITRANK1_Lane5_OFF                       (20)
+  #define DDRDATA0CH1_CR_RXPERBITRANK1_Lane5_WID                       ( 4)
+  #define DDRDATA0CH1_CR_RXPERBITRANK1_Lane5_MSK                       (0x00F00000)
+  #define DDRDATA0CH1_CR_RXPERBITRANK1_Lane5_MAX                       (0x0000000F)
+  #define DDRDATA0CH1_CR_RXPERBITRANK1_Lane6_OFF                       (24)
+  #define DDRDATA0CH1_CR_RXPERBITRANK1_Lane6_WID                       ( 4)
+  #define DDRDATA0CH1_CR_RXPERBITRANK1_Lane6_MSK                       (0x0F000000)
+  #define DDRDATA0CH1_CR_RXPERBITRANK1_Lane6_MAX                       (0x0000000F)
+  #define DDRDATA0CH1_CR_RXPERBITRANK1_Lane7_OFF                       (28)
+  #define DDRDATA0CH1_CR_RXPERBITRANK1_Lane7_WID                       ( 4)
+  #define DDRDATA0CH1_CR_RXPERBITRANK1_Lane7_MSK                       (0xF0000000)
+  #define DDRDATA0CH1_CR_RXPERBITRANK1_Lane7_MAX                       (0x0000000F)
+
+#define DDRDATA0CH1_CR_RXPERBITRANK2_REG                             (0x00000118)
+  #define DDRDATA0CH1_CR_RXPERBITRANK2_Lane0_OFF                       ( 0)
+  #define DDRDATA0CH1_CR_RXPERBITRANK2_Lane0_WID                       ( 4)
+  #define DDRDATA0CH1_CR_RXPERBITRANK2_Lane0_MSK                       (0x0000000F)
+  #define DDRDATA0CH1_CR_RXPERBITRANK2_Lane0_MAX                       (0x0000000F)
+  #define DDRDATA0CH1_CR_RXPERBITRANK2_Lane1_OFF                       ( 4)
+  #define DDRDATA0CH1_CR_RXPERBITRANK2_Lane1_WID                       ( 4)
+  #define DDRDATA0CH1_CR_RXPERBITRANK2_Lane1_MSK                       (0x000000F0)
+  #define DDRDATA0CH1_CR_RXPERBITRANK2_Lane1_MAX                       (0x0000000F)
+  #define DDRDATA0CH1_CR_RXPERBITRANK2_Lane2_OFF                       ( 8)
+  #define DDRDATA0CH1_CR_RXPERBITRANK2_Lane2_WID                       ( 4)
+  #define DDRDATA0CH1_CR_RXPERBITRANK2_Lane2_MSK                       (0x00000F00)
+  #define DDRDATA0CH1_CR_RXPERBITRANK2_Lane2_MAX                       (0x0000000F)
+  #define DDRDATA0CH1_CR_RXPERBITRANK2_Lane3_OFF                       (12)
+  #define DDRDATA0CH1_CR_RXPERBITRANK2_Lane3_WID                       ( 4)
+  #define DDRDATA0CH1_CR_RXPERBITRANK2_Lane3_MSK                       (0x0000F000)
+  #define DDRDATA0CH1_CR_RXPERBITRANK2_Lane3_MAX                       (0x0000000F)
+  #define DDRDATA0CH1_CR_RXPERBITRANK2_Lane4_OFF                       (16)
+  #define DDRDATA0CH1_CR_RXPERBITRANK2_Lane4_WID                       ( 4)
+  #define DDRDATA0CH1_CR_RXPERBITRANK2_Lane4_MSK                       (0x000F0000)
+  #define DDRDATA0CH1_CR_RXPERBITRANK2_Lane4_MAX                       (0x0000000F)
+  #define DDRDATA0CH1_CR_RXPERBITRANK2_Lane5_OFF                       (20)
+  #define DDRDATA0CH1_CR_RXPERBITRANK2_Lane5_WID                       ( 4)
+  #define DDRDATA0CH1_CR_RXPERBITRANK2_Lane5_MSK                       (0x00F00000)
+  #define DDRDATA0CH1_CR_RXPERBITRANK2_Lane5_MAX                       (0x0000000F)
+  #define DDRDATA0CH1_CR_RXPERBITRANK2_Lane6_OFF                       (24)
+  #define DDRDATA0CH1_CR_RXPERBITRANK2_Lane6_WID                       ( 4)
+  #define DDRDATA0CH1_CR_RXPERBITRANK2_Lane6_MSK                       (0x0F000000)
+  #define DDRDATA0CH1_CR_RXPERBITRANK2_Lane6_MAX                       (0x0000000F)
+  #define DDRDATA0CH1_CR_RXPERBITRANK2_Lane7_OFF                       (28)
+  #define DDRDATA0CH1_CR_RXPERBITRANK2_Lane7_WID                       ( 4)
+  #define DDRDATA0CH1_CR_RXPERBITRANK2_Lane7_MSK                       (0xF0000000)
+  #define DDRDATA0CH1_CR_RXPERBITRANK2_Lane7_MAX                       (0x0000000F)
+
+#define DDRDATA0CH1_CR_RXPERBITRANK3_REG                             (0x0000011C)
+  #define DDRDATA0CH1_CR_RXPERBITRANK3_Lane0_OFF                       ( 0)
+  #define DDRDATA0CH1_CR_RXPERBITRANK3_Lane0_WID                       ( 4)
+  #define DDRDATA0CH1_CR_RXPERBITRANK3_Lane0_MSK                       (0x0000000F)
+  #define DDRDATA0CH1_CR_RXPERBITRANK3_Lane0_MAX                       (0x0000000F)
+  #define DDRDATA0CH1_CR_RXPERBITRANK3_Lane1_OFF                       ( 4)
+  #define DDRDATA0CH1_CR_RXPERBITRANK3_Lane1_WID                       ( 4)
+  #define DDRDATA0CH1_CR_RXPERBITRANK3_Lane1_MSK                       (0x000000F0)
+  #define DDRDATA0CH1_CR_RXPERBITRANK3_Lane1_MAX                       (0x0000000F)
+  #define DDRDATA0CH1_CR_RXPERBITRANK3_Lane2_OFF                       ( 8)
+  #define DDRDATA0CH1_CR_RXPERBITRANK3_Lane2_WID                       ( 4)
+  #define DDRDATA0CH1_CR_RXPERBITRANK3_Lane2_MSK                       (0x00000F00)
+  #define DDRDATA0CH1_CR_RXPERBITRANK3_Lane2_MAX                       (0x0000000F)
+  #define DDRDATA0CH1_CR_RXPERBITRANK3_Lane3_OFF                       (12)
+  #define DDRDATA0CH1_CR_RXPERBITRANK3_Lane3_WID                       ( 4)
+  #define DDRDATA0CH1_CR_RXPERBITRANK3_Lane3_MSK                       (0x0000F000)
+  #define DDRDATA0CH1_CR_RXPERBITRANK3_Lane3_MAX                       (0x0000000F)
+  #define DDRDATA0CH1_CR_RXPERBITRANK3_Lane4_OFF                       (16)
+  #define DDRDATA0CH1_CR_RXPERBITRANK3_Lane4_WID                       ( 4)
+  #define DDRDATA0CH1_CR_RXPERBITRANK3_Lane4_MSK                       (0x000F0000)
+  #define DDRDATA0CH1_CR_RXPERBITRANK3_Lane4_MAX                       (0x0000000F)
+  #define DDRDATA0CH1_CR_RXPERBITRANK3_Lane5_OFF                       (20)
+  #define DDRDATA0CH1_CR_RXPERBITRANK3_Lane5_WID                       ( 4)
+  #define DDRDATA0CH1_CR_RXPERBITRANK3_Lane5_MSK                       (0x00F00000)
+  #define DDRDATA0CH1_CR_RXPERBITRANK3_Lane5_MAX                       (0x0000000F)
+  #define DDRDATA0CH1_CR_RXPERBITRANK3_Lane6_OFF                       (24)
+  #define DDRDATA0CH1_CR_RXPERBITRANK3_Lane6_WID                       ( 4)
+  #define DDRDATA0CH1_CR_RXPERBITRANK3_Lane6_MSK                       (0x0F000000)
+  #define DDRDATA0CH1_CR_RXPERBITRANK3_Lane6_MAX                       (0x0000000F)
+  #define DDRDATA0CH1_CR_RXPERBITRANK3_Lane7_OFF                       (28)
+  #define DDRDATA0CH1_CR_RXPERBITRANK3_Lane7_WID                       ( 4)
+  #define DDRDATA0CH1_CR_RXPERBITRANK3_Lane7_MSK                       (0xF0000000)
+  #define DDRDATA0CH1_CR_RXPERBITRANK3_Lane7_MAX                       (0x0000000F)
+
+#define DDRDATA0CH1_CR_TXTRAINRANK0_REG                              (0x00000120)
+  #define DDRDATA0CH1_CR_TXTRAINRANK0_TxDqDelay_OFF                    ( 0)
+  #define DDRDATA0CH1_CR_TXTRAINRANK0_TxDqDelay_WID                    ( 9)
+  #define DDRDATA0CH1_CR_TXTRAINRANK0_TxDqDelay_MSK                    (0x000001FF)
+  #define DDRDATA0CH1_CR_TXTRAINRANK0_TxDqDelay_MAX                    (0x000001FF)
+  #define DDRDATA0CH1_CR_TXTRAINRANK0_TxDqsDelay_OFF                   ( 9)
+  #define DDRDATA0CH1_CR_TXTRAINRANK0_TxDqsDelay_WID                   ( 9)
+  #define DDRDATA0CH1_CR_TXTRAINRANK0_TxDqsDelay_MSK                   (0x0003FE00)
+  #define DDRDATA0CH1_CR_TXTRAINRANK0_TxDqsDelay_MAX                   (0x000001FF)
+  #define DDRDATA0CH1_CR_TXTRAINRANK0_Spare0_OFF                       (18)
+  #define DDRDATA0CH1_CR_TXTRAINRANK0_Spare0_WID                       ( 2)
+  #define DDRDATA0CH1_CR_TXTRAINRANK0_Spare0_MSK                       (0x000C0000)
+  #define DDRDATA0CH1_CR_TXTRAINRANK0_Spare0_MAX                       (0x00000003)
+  #define DDRDATA0CH1_CR_TXTRAINRANK0_TxEqualization_OFF               (20)
+  #define DDRDATA0CH1_CR_TXTRAINRANK0_TxEqualization_WID               ( 6)
+  #define DDRDATA0CH1_CR_TXTRAINRANK0_TxEqualization_MSK               (0x03F00000)
+  #define DDRDATA0CH1_CR_TXTRAINRANK0_TxEqualization_MAX               (0x0000003F)
+  #define DDRDATA0CH1_CR_TXTRAINRANK0_Spare1_OFF                       (26)
+  #define DDRDATA0CH1_CR_TXTRAINRANK0_Spare1_WID                       ( 6)
+  #define DDRDATA0CH1_CR_TXTRAINRANK0_Spare1_MSK                       (0xFC000000)
+  #define DDRDATA0CH1_CR_TXTRAINRANK0_Spare1_MAX                       (0x0000003F)
+
+#define DDRDATA0CH1_CR_TXTRAINRANK1_REG                              (0x00000124)
+  #define DDRDATA0CH1_CR_TXTRAINRANK1_TxDqDelay_OFF                    ( 0)
+  #define DDRDATA0CH1_CR_TXTRAINRANK1_TxDqDelay_WID                    ( 9)
+  #define DDRDATA0CH1_CR_TXTRAINRANK1_TxDqDelay_MSK                    (0x000001FF)
+  #define DDRDATA0CH1_CR_TXTRAINRANK1_TxDqDelay_MAX                    (0x000001FF)
+  #define DDRDATA0CH1_CR_TXTRAINRANK1_TxDqsDelay_OFF                   ( 9)
+  #define DDRDATA0CH1_CR_TXTRAINRANK1_TxDqsDelay_WID                   ( 9)
+  #define DDRDATA0CH1_CR_TXTRAINRANK1_TxDqsDelay_MSK                   (0x0003FE00)
+  #define DDRDATA0CH1_CR_TXTRAINRANK1_TxDqsDelay_MAX                   (0x000001FF)
+  #define DDRDATA0CH1_CR_TXTRAINRANK1_Spare0_OFF                       (18)
+  #define DDRDATA0CH1_CR_TXTRAINRANK1_Spare0_WID                       ( 2)
+  #define DDRDATA0CH1_CR_TXTRAINRANK1_Spare0_MSK                       (0x000C0000)
+  #define DDRDATA0CH1_CR_TXTRAINRANK1_Spare0_MAX                       (0x00000003)
+  #define DDRDATA0CH1_CR_TXTRAINRANK1_TxEqualization_OFF               (20)
+  #define DDRDATA0CH1_CR_TXTRAINRANK1_TxEqualization_WID               ( 6)
+  #define DDRDATA0CH1_CR_TXTRAINRANK1_TxEqualization_MSK               (0x03F00000)
+  #define DDRDATA0CH1_CR_TXTRAINRANK1_TxEqualization_MAX               (0x0000003F)
+  #define DDRDATA0CH1_CR_TXTRAINRANK1_Spare1_OFF                       (26)
+  #define DDRDATA0CH1_CR_TXTRAINRANK1_Spare1_WID                       ( 6)
+  #define DDRDATA0CH1_CR_TXTRAINRANK1_Spare1_MSK                       (0xFC000000)
+  #define DDRDATA0CH1_CR_TXTRAINRANK1_Spare1_MAX                       (0x0000003F)
+
+#define DDRDATA0CH1_CR_TXTRAINRANK2_REG                              (0x00000128)
+  #define DDRDATA0CH1_CR_TXTRAINRANK2_TxDqDelay_OFF                    ( 0)
+  #define DDRDATA0CH1_CR_TXTRAINRANK2_TxDqDelay_WID                    ( 9)
+  #define DDRDATA0CH1_CR_TXTRAINRANK2_TxDqDelay_MSK                    (0x000001FF)
+  #define DDRDATA0CH1_CR_TXTRAINRANK2_TxDqDelay_MAX                    (0x000001FF)
+  #define DDRDATA0CH1_CR_TXTRAINRANK2_TxDqsDelay_OFF                   ( 9)
+  #define DDRDATA0CH1_CR_TXTRAINRANK2_TxDqsDelay_WID                   ( 9)
+  #define DDRDATA0CH1_CR_TXTRAINRANK2_TxDqsDelay_MSK                   (0x0003FE00)
+  #define DDRDATA0CH1_CR_TXTRAINRANK2_TxDqsDelay_MAX                   (0x000001FF)
+  #define DDRDATA0CH1_CR_TXTRAINRANK2_Spare0_OFF                       (18)
+  #define DDRDATA0CH1_CR_TXTRAINRANK2_Spare0_WID                       ( 2)
+  #define DDRDATA0CH1_CR_TXTRAINRANK2_Spare0_MSK                       (0x000C0000)
+  #define DDRDATA0CH1_CR_TXTRAINRANK2_Spare0_MAX                       (0x00000003)
+  #define DDRDATA0CH1_CR_TXTRAINRANK2_TxEqualization_OFF               (20)
+  #define DDRDATA0CH1_CR_TXTRAINRANK2_TxEqualization_WID               ( 6)
+  #define DDRDATA0CH1_CR_TXTRAINRANK2_TxEqualization_MSK               (0x03F00000)
+  #define DDRDATA0CH1_CR_TXTRAINRANK2_TxEqualization_MAX               (0x0000003F)
+  #define DDRDATA0CH1_CR_TXTRAINRANK2_Spare1_OFF                       (26)
+  #define DDRDATA0CH1_CR_TXTRAINRANK2_Spare1_WID                       ( 6)
+  #define DDRDATA0CH1_CR_TXTRAINRANK2_Spare1_MSK                       (0xFC000000)
+  #define DDRDATA0CH1_CR_TXTRAINRANK2_Spare1_MAX                       (0x0000003F)
+
+#define DDRDATA0CH1_CR_TXTRAINRANK3_REG                              (0x0000012C)
+  #define DDRDATA0CH1_CR_TXTRAINRANK3_TxDqDelay_OFF                    ( 0)
+  #define DDRDATA0CH1_CR_TXTRAINRANK3_TxDqDelay_WID                    ( 9)
+  #define DDRDATA0CH1_CR_TXTRAINRANK3_TxDqDelay_MSK                    (0x000001FF)
+  #define DDRDATA0CH1_CR_TXTRAINRANK3_TxDqDelay_MAX                    (0x000001FF)
+  #define DDRDATA0CH1_CR_TXTRAINRANK3_TxDqsDelay_OFF                   ( 9)
+  #define DDRDATA0CH1_CR_TXTRAINRANK3_TxDqsDelay_WID                   ( 9)
+  #define DDRDATA0CH1_CR_TXTRAINRANK3_TxDqsDelay_MSK                   (0x0003FE00)
+  #define DDRDATA0CH1_CR_TXTRAINRANK3_TxDqsDelay_MAX                   (0x000001FF)
+  #define DDRDATA0CH1_CR_TXTRAINRANK3_Spare0_OFF                       (18)
+  #define DDRDATA0CH1_CR_TXTRAINRANK3_Spare0_WID                       ( 2)
+  #define DDRDATA0CH1_CR_TXTRAINRANK3_Spare0_MSK                       (0x000C0000)
+  #define DDRDATA0CH1_CR_TXTRAINRANK3_Spare0_MAX                       (0x00000003)
+  #define DDRDATA0CH1_CR_TXTRAINRANK3_TxEqualization_OFF               (20)
+  #define DDRDATA0CH1_CR_TXTRAINRANK3_TxEqualization_WID               ( 6)
+  #define DDRDATA0CH1_CR_TXTRAINRANK3_TxEqualization_MSK               (0x03F00000)
+  #define DDRDATA0CH1_CR_TXTRAINRANK3_TxEqualization_MAX               (0x0000003F)
+  #define DDRDATA0CH1_CR_TXTRAINRANK3_Spare1_OFF                       (26)
+  #define DDRDATA0CH1_CR_TXTRAINRANK3_Spare1_WID                       ( 6)
+  #define DDRDATA0CH1_CR_TXTRAINRANK3_Spare1_MSK                       (0xFC000000)
+  #define DDRDATA0CH1_CR_TXTRAINRANK3_Spare1_MAX                       (0x0000003F)
+
+#define DDRDATA0CH1_CR_TXPERBITRANK0_REG                             (0x00000130)
+  #define DDRDATA0CH1_CR_TXPERBITRANK0_Lane0_OFF                       ( 0)
+  #define DDRDATA0CH1_CR_TXPERBITRANK0_Lane0_WID                       ( 4)
+  #define DDRDATA0CH1_CR_TXPERBITRANK0_Lane0_MSK                       (0x0000000F)
+  #define DDRDATA0CH1_CR_TXPERBITRANK0_Lane0_MAX                       (0x0000000F)
+  #define DDRDATA0CH1_CR_TXPERBITRANK0_Lane1_OFF                       ( 4)
+  #define DDRDATA0CH1_CR_TXPERBITRANK0_Lane1_WID                       ( 4)
+  #define DDRDATA0CH1_CR_TXPERBITRANK0_Lane1_MSK                       (0x000000F0)
+  #define DDRDATA0CH1_CR_TXPERBITRANK0_Lane1_MAX                       (0x0000000F)
+  #define DDRDATA0CH1_CR_TXPERBITRANK0_Lane2_OFF                       ( 8)
+  #define DDRDATA0CH1_CR_TXPERBITRANK0_Lane2_WID                       ( 4)
+  #define DDRDATA0CH1_CR_TXPERBITRANK0_Lane2_MSK                       (0x00000F00)
+  #define DDRDATA0CH1_CR_TXPERBITRANK0_Lane2_MAX                       (0x0000000F)
+  #define DDRDATA0CH1_CR_TXPERBITRANK0_Lane3_OFF                       (12)
+  #define DDRDATA0CH1_CR_TXPERBITRANK0_Lane3_WID                       ( 4)
+  #define DDRDATA0CH1_CR_TXPERBITRANK0_Lane3_MSK                       (0x0000F000)
+  #define DDRDATA0CH1_CR_TXPERBITRANK0_Lane3_MAX                       (0x0000000F)
+  #define DDRDATA0CH1_CR_TXPERBITRANK0_Lane4_OFF                       (16)
+  #define DDRDATA0CH1_CR_TXPERBITRANK0_Lane4_WID                       ( 4)
+  #define DDRDATA0CH1_CR_TXPERBITRANK0_Lane4_MSK                       (0x000F0000)
+  #define DDRDATA0CH1_CR_TXPERBITRANK0_Lane4_MAX                       (0x0000000F)
+  #define DDRDATA0CH1_CR_TXPERBITRANK0_Lane5_OFF                       (20)
+  #define DDRDATA0CH1_CR_TXPERBITRANK0_Lane5_WID                       ( 4)
+  #define DDRDATA0CH1_CR_TXPERBITRANK0_Lane5_MSK                       (0x00F00000)
+  #define DDRDATA0CH1_CR_TXPERBITRANK0_Lane5_MAX                       (0x0000000F)
+  #define DDRDATA0CH1_CR_TXPERBITRANK0_Lane6_OFF                       (24)
+  #define DDRDATA0CH1_CR_TXPERBITRANK0_Lane6_WID                       ( 4)
+  #define DDRDATA0CH1_CR_TXPERBITRANK0_Lane6_MSK                       (0x0F000000)
+  #define DDRDATA0CH1_CR_TXPERBITRANK0_Lane6_MAX                       (0x0000000F)
+  #define DDRDATA0CH1_CR_TXPERBITRANK0_Lane7_OFF                       (28)
+  #define DDRDATA0CH1_CR_TXPERBITRANK0_Lane7_WID                       ( 4)
+  #define DDRDATA0CH1_CR_TXPERBITRANK0_Lane7_MSK                       (0xF0000000)
+  #define DDRDATA0CH1_CR_TXPERBITRANK0_Lane7_MAX                       (0x0000000F)
+
+#define DDRDATA0CH1_CR_TXPERBITRANK1_REG                             (0x00000134)
+  #define DDRDATA0CH1_CR_TXPERBITRANK1_Lane0_OFF                       ( 0)
+  #define DDRDATA0CH1_CR_TXPERBITRANK1_Lane0_WID                       ( 4)
+  #define DDRDATA0CH1_CR_TXPERBITRANK1_Lane0_MSK                       (0x0000000F)
+  #define DDRDATA0CH1_CR_TXPERBITRANK1_Lane0_MAX                       (0x0000000F)
+  #define DDRDATA0CH1_CR_TXPERBITRANK1_Lane1_OFF                       ( 4)
+  #define DDRDATA0CH1_CR_TXPERBITRANK1_Lane1_WID                       ( 4)
+  #define DDRDATA0CH1_CR_TXPERBITRANK1_Lane1_MSK                       (0x000000F0)
+  #define DDRDATA0CH1_CR_TXPERBITRANK1_Lane1_MAX                       (0x0000000F)
+  #define DDRDATA0CH1_CR_TXPERBITRANK1_Lane2_OFF                       ( 8)
+  #define DDRDATA0CH1_CR_TXPERBITRANK1_Lane2_WID                       ( 4)
+  #define DDRDATA0CH1_CR_TXPERBITRANK1_Lane2_MSK                       (0x00000F00)
+  #define DDRDATA0CH1_CR_TXPERBITRANK1_Lane2_MAX                       (0x0000000F)
+  #define DDRDATA0CH1_CR_TXPERBITRANK1_Lane3_OFF                       (12)
+  #define DDRDATA0CH1_CR_TXPERBITRANK1_Lane3_WID                       ( 4)
+  #define DDRDATA0CH1_CR_TXPERBITRANK1_Lane3_MSK                       (0x0000F000)
+  #define DDRDATA0CH1_CR_TXPERBITRANK1_Lane3_MAX                       (0x0000000F)
+  #define DDRDATA0CH1_CR_TXPERBITRANK1_Lane4_OFF                       (16)
+  #define DDRDATA0CH1_CR_TXPERBITRANK1_Lane4_WID                       ( 4)
+  #define DDRDATA0CH1_CR_TXPERBITRANK1_Lane4_MSK                       (0x000F0000)
+  #define DDRDATA0CH1_CR_TXPERBITRANK1_Lane4_MAX                       (0x0000000F)
+  #define DDRDATA0CH1_CR_TXPERBITRANK1_Lane5_OFF                       (20)
+  #define DDRDATA0CH1_CR_TXPERBITRANK1_Lane5_WID                       ( 4)
+  #define DDRDATA0CH1_CR_TXPERBITRANK1_Lane5_MSK                       (0x00F00000)
+  #define DDRDATA0CH1_CR_TXPERBITRANK1_Lane5_MAX                       (0x0000000F)
+  #define DDRDATA0CH1_CR_TXPERBITRANK1_Lane6_OFF                       (24)
+  #define DDRDATA0CH1_CR_TXPERBITRANK1_Lane6_WID                       ( 4)
+  #define DDRDATA0CH1_CR_TXPERBITRANK1_Lane6_MSK                       (0x0F000000)
+  #define DDRDATA0CH1_CR_TXPERBITRANK1_Lane6_MAX                       (0x0000000F)
+  #define DDRDATA0CH1_CR_TXPERBITRANK1_Lane7_OFF                       (28)
+  #define DDRDATA0CH1_CR_TXPERBITRANK1_Lane7_WID                       ( 4)
+  #define DDRDATA0CH1_CR_TXPERBITRANK1_Lane7_MSK                       (0xF0000000)
+  #define DDRDATA0CH1_CR_TXPERBITRANK1_Lane7_MAX                       (0x0000000F)
+
+#define DDRDATA0CH1_CR_TXPERBITRANK2_REG                             (0x00000138)
+  #define DDRDATA0CH1_CR_TXPERBITRANK2_Lane0_OFF                       ( 0)
+  #define DDRDATA0CH1_CR_TXPERBITRANK2_Lane0_WID                       ( 4)
+  #define DDRDATA0CH1_CR_TXPERBITRANK2_Lane0_MSK                       (0x0000000F)
+  #define DDRDATA0CH1_CR_TXPERBITRANK2_Lane0_MAX                       (0x0000000F)
+  #define DDRDATA0CH1_CR_TXPERBITRANK2_Lane1_OFF                       ( 4)
+  #define DDRDATA0CH1_CR_TXPERBITRANK2_Lane1_WID                       ( 4)
+  #define DDRDATA0CH1_CR_TXPERBITRANK2_Lane1_MSK                       (0x000000F0)
+  #define DDRDATA0CH1_CR_TXPERBITRANK2_Lane1_MAX                       (0x0000000F)
+  #define DDRDATA0CH1_CR_TXPERBITRANK2_Lane2_OFF                       ( 8)
+  #define DDRDATA0CH1_CR_TXPERBITRANK2_Lane2_WID                       ( 4)
+  #define DDRDATA0CH1_CR_TXPERBITRANK2_Lane2_MSK                       (0x00000F00)
+  #define DDRDATA0CH1_CR_TXPERBITRANK2_Lane2_MAX                       (0x0000000F)
+  #define DDRDATA0CH1_CR_TXPERBITRANK2_Lane3_OFF                       (12)
+  #define DDRDATA0CH1_CR_TXPERBITRANK2_Lane3_WID                       ( 4)
+  #define DDRDATA0CH1_CR_TXPERBITRANK2_Lane3_MSK                       (0x0000F000)
+  #define DDRDATA0CH1_CR_TXPERBITRANK2_Lane3_MAX                       (0x0000000F)
+  #define DDRDATA0CH1_CR_TXPERBITRANK2_Lane4_OFF                       (16)
+  #define DDRDATA0CH1_CR_TXPERBITRANK2_Lane4_WID                       ( 4)
+  #define DDRDATA0CH1_CR_TXPERBITRANK2_Lane4_MSK                       (0x000F0000)
+  #define DDRDATA0CH1_CR_TXPERBITRANK2_Lane4_MAX                       (0x0000000F)
+  #define DDRDATA0CH1_CR_TXPERBITRANK2_Lane5_OFF                       (20)
+  #define DDRDATA0CH1_CR_TXPERBITRANK2_Lane5_WID                       ( 4)
+  #define DDRDATA0CH1_CR_TXPERBITRANK2_Lane5_MSK                       (0x00F00000)
+  #define DDRDATA0CH1_CR_TXPERBITRANK2_Lane5_MAX                       (0x0000000F)
+  #define DDRDATA0CH1_CR_TXPERBITRANK2_Lane6_OFF                       (24)
+  #define DDRDATA0CH1_CR_TXPERBITRANK2_Lane6_WID                       ( 4)
+  #define DDRDATA0CH1_CR_TXPERBITRANK2_Lane6_MSK                       (0x0F000000)
+  #define DDRDATA0CH1_CR_TXPERBITRANK2_Lane6_MAX                       (0x0000000F)
+  #define DDRDATA0CH1_CR_TXPERBITRANK2_Lane7_OFF                       (28)
+  #define DDRDATA0CH1_CR_TXPERBITRANK2_Lane7_WID                       ( 4)
+  #define DDRDATA0CH1_CR_TXPERBITRANK2_Lane7_MSK                       (0xF0000000)
+  #define DDRDATA0CH1_CR_TXPERBITRANK2_Lane7_MAX                       (0x0000000F)
+
+#define DDRDATA0CH1_CR_TXPERBITRANK3_REG                             (0x0000013C)
+  #define DDRDATA0CH1_CR_TXPERBITRANK3_Lane0_OFF                       ( 0)
+  #define DDRDATA0CH1_CR_TXPERBITRANK3_Lane0_WID                       ( 4)
+  #define DDRDATA0CH1_CR_TXPERBITRANK3_Lane0_MSK                       (0x0000000F)
+  #define DDRDATA0CH1_CR_TXPERBITRANK3_Lane0_MAX                       (0x0000000F)
+  #define DDRDATA0CH1_CR_TXPERBITRANK3_Lane1_OFF                       ( 4)
+  #define DDRDATA0CH1_CR_TXPERBITRANK3_Lane1_WID                       ( 4)
+  #define DDRDATA0CH1_CR_TXPERBITRANK3_Lane1_MSK                       (0x000000F0)
+  #define DDRDATA0CH1_CR_TXPERBITRANK3_Lane1_MAX                       (0x0000000F)
+  #define DDRDATA0CH1_CR_TXPERBITRANK3_Lane2_OFF                       ( 8)
+  #define DDRDATA0CH1_CR_TXPERBITRANK3_Lane2_WID                       ( 4)
+  #define DDRDATA0CH1_CR_TXPERBITRANK3_Lane2_MSK                       (0x00000F00)
+  #define DDRDATA0CH1_CR_TXPERBITRANK3_Lane2_MAX                       (0x0000000F)
+  #define DDRDATA0CH1_CR_TXPERBITRANK3_Lane3_OFF                       (12)
+  #define DDRDATA0CH1_CR_TXPERBITRANK3_Lane3_WID                       ( 4)
+  #define DDRDATA0CH1_CR_TXPERBITRANK3_Lane3_MSK                       (0x0000F000)
+  #define DDRDATA0CH1_CR_TXPERBITRANK3_Lane3_MAX                       (0x0000000F)
+  #define DDRDATA0CH1_CR_TXPERBITRANK3_Lane4_OFF                       (16)
+  #define DDRDATA0CH1_CR_TXPERBITRANK3_Lane4_WID                       ( 4)
+  #define DDRDATA0CH1_CR_TXPERBITRANK3_Lane4_MSK                       (0x000F0000)
+  #define DDRDATA0CH1_CR_TXPERBITRANK3_Lane4_MAX                       (0x0000000F)
+  #define DDRDATA0CH1_CR_TXPERBITRANK3_Lane5_OFF                       (20)
+  #define DDRDATA0CH1_CR_TXPERBITRANK3_Lane5_WID                       ( 4)
+  #define DDRDATA0CH1_CR_TXPERBITRANK3_Lane5_MSK                       (0x00F00000)
+  #define DDRDATA0CH1_CR_TXPERBITRANK3_Lane5_MAX                       (0x0000000F)
+  #define DDRDATA0CH1_CR_TXPERBITRANK3_Lane6_OFF                       (24)
+  #define DDRDATA0CH1_CR_TXPERBITRANK3_Lane6_WID                       ( 4)
+  #define DDRDATA0CH1_CR_TXPERBITRANK3_Lane6_MSK                       (0x0F000000)
+  #define DDRDATA0CH1_CR_TXPERBITRANK3_Lane6_MAX                       (0x0000000F)
+  #define DDRDATA0CH1_CR_TXPERBITRANK3_Lane7_OFF                       (28)
+  #define DDRDATA0CH1_CR_TXPERBITRANK3_Lane7_WID                       ( 4)
+  #define DDRDATA0CH1_CR_TXPERBITRANK3_Lane7_MSK                       (0xF0000000)
+  #define DDRDATA0CH1_CR_TXPERBITRANK3_Lane7_MAX                       (0x0000000F)
+
+#define DDRDATA0CH1_CR_RCOMPDATA0_REG                                (0x00000140)
+  #define DDRDATA0CH1_CR_RCOMPDATA0_RcompDrvUp_OFF                     ( 0)
+  #define DDRDATA0CH1_CR_RCOMPDATA0_RcompDrvUp_WID                     ( 6)
+  #define DDRDATA0CH1_CR_RCOMPDATA0_RcompDrvUp_MSK                     (0x0000003F)
+  #define DDRDATA0CH1_CR_RCOMPDATA0_RcompDrvUp_MAX                     (0x0000003F)
+  #define DDRDATA0CH1_CR_RCOMPDATA0_Spare0_OFF                         ( 6)
+  #define DDRDATA0CH1_CR_RCOMPDATA0_Spare0_WID                         ( 3)
+  #define DDRDATA0CH1_CR_RCOMPDATA0_Spare0_MSK                         (0x000001C0)
+  #define DDRDATA0CH1_CR_RCOMPDATA0_Spare0_MAX                         (0x00000007)
+  #define DDRDATA0CH1_CR_RCOMPDATA0_RcompDrvDown_OFF                   ( 9)
+  #define DDRDATA0CH1_CR_RCOMPDATA0_RcompDrvDown_WID                   ( 6)
+  #define DDRDATA0CH1_CR_RCOMPDATA0_RcompDrvDown_MSK                   (0x00007E00)
+  #define DDRDATA0CH1_CR_RCOMPDATA0_RcompDrvDown_MAX                   (0x0000003F)
+  #define DDRDATA0CH1_CR_RCOMPDATA0_VTComp_OFF                         (15)
+  #define DDRDATA0CH1_CR_RCOMPDATA0_VTComp_WID                         ( 5)
+  #define DDRDATA0CH1_CR_RCOMPDATA0_VTComp_MSK                         (0x000F8000)
+  #define DDRDATA0CH1_CR_RCOMPDATA0_VTComp_MAX                         (0x0000001F)
+  #define DDRDATA0CH1_CR_RCOMPDATA0_TcoComp_OFF                        (20)
+  #define DDRDATA0CH1_CR_RCOMPDATA0_TcoComp_WID                        ( 6)
+  #define DDRDATA0CH1_CR_RCOMPDATA0_TcoComp_MSK                        (0x03F00000)
+  #define DDRDATA0CH1_CR_RCOMPDATA0_TcoComp_MAX                        (0x0000003F)
+  #define DDRDATA0CH1_CR_RCOMPDATA0_SlewRateComp_OFF                   (26)
+  #define DDRDATA0CH1_CR_RCOMPDATA0_SlewRateComp_WID                   ( 5)
+  #define DDRDATA0CH1_CR_RCOMPDATA0_SlewRateComp_MSK                   (0x7C000000)
+  #define DDRDATA0CH1_CR_RCOMPDATA0_SlewRateComp_MAX                   (0x0000001F)
+  #define DDRDATA0CH1_CR_RCOMPDATA0_Spare2_OFF                         (31)
+  #define DDRDATA0CH1_CR_RCOMPDATA0_Spare2_WID                         ( 1)
+  #define DDRDATA0CH1_CR_RCOMPDATA0_Spare2_MSK                         (0x80000000)
+  #define DDRDATA0CH1_CR_RCOMPDATA0_Spare2_MAX                         (0x00000001)
+
+#define DDRDATA0CH1_CR_RCOMPDATA1_REG                                (0x00000144)
+  #define DDRDATA0CH1_CR_RCOMPDATA1_RcompOdtUp_OFF                     ( 0)
+  #define DDRDATA0CH1_CR_RCOMPDATA1_RcompOdtUp_WID                     ( 6)
+  #define DDRDATA0CH1_CR_RCOMPDATA1_RcompOdtUp_MSK                     (0x0000003F)
+  #define DDRDATA0CH1_CR_RCOMPDATA1_RcompOdtUp_MAX                     (0x0000003F)
+  #define DDRDATA0CH1_CR_RCOMPDATA1_Spare0_OFF                         ( 6)
+  #define DDRDATA0CH1_CR_RCOMPDATA1_Spare0_WID                         ( 3)
+  #define DDRDATA0CH1_CR_RCOMPDATA1_Spare0_MSK                         (0x000001C0)
+  #define DDRDATA0CH1_CR_RCOMPDATA1_Spare0_MAX                         (0x00000007)
+  #define DDRDATA0CH1_CR_RCOMPDATA1_RcompOdtDown_OFF                   ( 9)
+  #define DDRDATA0CH1_CR_RCOMPDATA1_RcompOdtDown_WID                   ( 6)
+  #define DDRDATA0CH1_CR_RCOMPDATA1_RcompOdtDown_MSK                   (0x00007E00)
+  #define DDRDATA0CH1_CR_RCOMPDATA1_RcompOdtDown_MAX                   (0x0000003F)
+  #define DDRDATA0CH1_CR_RCOMPDATA1_Spare1_OFF                         (15)
+  #define DDRDATA0CH1_CR_RCOMPDATA1_Spare1_WID                         ( 1)
+  #define DDRDATA0CH1_CR_RCOMPDATA1_Spare1_MSK                         (0x00008000)
+  #define DDRDATA0CH1_CR_RCOMPDATA1_Spare1_MAX                         (0x00000001)
+  #define DDRDATA0CH1_CR_RCOMPDATA1_PanicDrvDn_OFF                     (16)
+  #define DDRDATA0CH1_CR_RCOMPDATA1_PanicDrvDn_WID                     ( 6)
+  #define DDRDATA0CH1_CR_RCOMPDATA1_PanicDrvDn_MSK                     (0x003F0000)
+  #define DDRDATA0CH1_CR_RCOMPDATA1_PanicDrvDn_MAX                     (0x0000003F)
+  #define DDRDATA0CH1_CR_RCOMPDATA1_PanicDrvUp_OFF                     (22)
+  #define DDRDATA0CH1_CR_RCOMPDATA1_PanicDrvUp_WID                     ( 6)
+  #define DDRDATA0CH1_CR_RCOMPDATA1_PanicDrvUp_MSK                     (0x0FC00000)
+  #define DDRDATA0CH1_CR_RCOMPDATA1_PanicDrvUp_MAX                     (0x0000003F)
+  #define DDRDATA0CH1_CR_RCOMPDATA1_LevelShifterComp_OFF               (28)
+  #define DDRDATA0CH1_CR_RCOMPDATA1_LevelShifterComp_WID               ( 3)
+  #define DDRDATA0CH1_CR_RCOMPDATA1_LevelShifterComp_MSK               (0x70000000)
+  #define DDRDATA0CH1_CR_RCOMPDATA1_LevelShifterComp_MAX               (0x00000007)
+  #define DDRDATA0CH1_CR_RCOMPDATA1_Spare2_OFF                         (31)
+  #define DDRDATA0CH1_CR_RCOMPDATA1_Spare2_WID                         ( 1)
+  #define DDRDATA0CH1_CR_RCOMPDATA1_Spare2_MSK                         (0x80000000)
+  #define DDRDATA0CH1_CR_RCOMPDATA1_Spare2_MAX                         (0x00000001)
+
+#define DDRDATA0CH1_CR_TXXTALK_REG                                   (0x00000148)
+  #define DDRDATA0CH1_CR_TXXTALK_Lane0_OFF                             ( 0)
+  #define DDRDATA0CH1_CR_TXXTALK_Lane0_WID                             ( 4)
+  #define DDRDATA0CH1_CR_TXXTALK_Lane0_MSK                             (0x0000000F)
+  #define DDRDATA0CH1_CR_TXXTALK_Lane0_MAX                             (0x0000000F)
+  #define DDRDATA0CH1_CR_TXXTALK_Lane1_OFF                             ( 4)
+  #define DDRDATA0CH1_CR_TXXTALK_Lane1_WID                             ( 4)
+  #define DDRDATA0CH1_CR_TXXTALK_Lane1_MSK                             (0x000000F0)
+  #define DDRDATA0CH1_CR_TXXTALK_Lane1_MAX                             (0x0000000F)
+  #define DDRDATA0CH1_CR_TXXTALK_Lane2_OFF                             ( 8)
+  #define DDRDATA0CH1_CR_TXXTALK_Lane2_WID                             ( 4)
+  #define DDRDATA0CH1_CR_TXXTALK_Lane2_MSK                             (0x00000F00)
+  #define DDRDATA0CH1_CR_TXXTALK_Lane2_MAX                             (0x0000000F)
+  #define DDRDATA0CH1_CR_TXXTALK_Lane3_OFF                             (12)
+  #define DDRDATA0CH1_CR_TXXTALK_Lane3_WID                             ( 4)
+  #define DDRDATA0CH1_CR_TXXTALK_Lane3_MSK                             (0x0000F000)
+  #define DDRDATA0CH1_CR_TXXTALK_Lane3_MAX                             (0x0000000F)
+  #define DDRDATA0CH1_CR_TXXTALK_Lane4_OFF                             (16)
+  #define DDRDATA0CH1_CR_TXXTALK_Lane4_WID                             ( 4)
+  #define DDRDATA0CH1_CR_TXXTALK_Lane4_MSK                             (0x000F0000)
+  #define DDRDATA0CH1_CR_TXXTALK_Lane4_MAX                             (0x0000000F)
+  #define DDRDATA0CH1_CR_TXXTALK_Lane5_OFF                             (20)
+  #define DDRDATA0CH1_CR_TXXTALK_Lane5_WID                             ( 4)
+  #define DDRDATA0CH1_CR_TXXTALK_Lane5_MSK                             (0x00F00000)
+  #define DDRDATA0CH1_CR_TXXTALK_Lane5_MAX                             (0x0000000F)
+  #define DDRDATA0CH1_CR_TXXTALK_Lane6_OFF                             (24)
+  #define DDRDATA0CH1_CR_TXXTALK_Lane6_WID                             ( 4)
+  #define DDRDATA0CH1_CR_TXXTALK_Lane6_MSK                             (0x0F000000)
+  #define DDRDATA0CH1_CR_TXXTALK_Lane6_MAX                             (0x0000000F)
+  #define DDRDATA0CH1_CR_TXXTALK_Lane7_OFF                             (28)
+  #define DDRDATA0CH1_CR_TXXTALK_Lane7_WID                             ( 4)
+  #define DDRDATA0CH1_CR_TXXTALK_Lane7_MSK                             (0xF0000000)
+  #define DDRDATA0CH1_CR_TXXTALK_Lane7_MAX                             (0x0000000F)
+
+#define DDRDATA0CH1_CR_RXOFFSETVDQ_REG                               (0x0000014C)
+  #define DDRDATA0CH1_CR_RXOFFSETVDQ_Lane0_OFF                         ( 0)
+  #define DDRDATA0CH1_CR_RXOFFSETVDQ_Lane0_WID                         ( 4)
+  #define DDRDATA0CH1_CR_RXOFFSETVDQ_Lane0_MSK                         (0x0000000F)
+  #define DDRDATA0CH1_CR_RXOFFSETVDQ_Lane0_MAX                         (0x0000000F)
+  #define DDRDATA0CH1_CR_RXOFFSETVDQ_Lane1_OFF                         ( 4)
+  #define DDRDATA0CH1_CR_RXOFFSETVDQ_Lane1_WID                         ( 4)
+  #define DDRDATA0CH1_CR_RXOFFSETVDQ_Lane1_MSK                         (0x000000F0)
+  #define DDRDATA0CH1_CR_RXOFFSETVDQ_Lane1_MAX                         (0x0000000F)
+  #define DDRDATA0CH1_CR_RXOFFSETVDQ_Lane2_OFF                         ( 8)
+  #define DDRDATA0CH1_CR_RXOFFSETVDQ_Lane2_WID                         ( 4)
+  #define DDRDATA0CH1_CR_RXOFFSETVDQ_Lane2_MSK                         (0x00000F00)
+  #define DDRDATA0CH1_CR_RXOFFSETVDQ_Lane2_MAX                         (0x0000000F)
+  #define DDRDATA0CH1_CR_RXOFFSETVDQ_Lane3_OFF                         (12)
+  #define DDRDATA0CH1_CR_RXOFFSETVDQ_Lane3_WID                         ( 4)
+  #define DDRDATA0CH1_CR_RXOFFSETVDQ_Lane3_MSK                         (0x0000F000)
+  #define DDRDATA0CH1_CR_RXOFFSETVDQ_Lane3_MAX                         (0x0000000F)
+  #define DDRDATA0CH1_CR_RXOFFSETVDQ_Lane4_OFF                         (16)
+  #define DDRDATA0CH1_CR_RXOFFSETVDQ_Lane4_WID                         ( 4)
+  #define DDRDATA0CH1_CR_RXOFFSETVDQ_Lane4_MSK                         (0x000F0000)
+  #define DDRDATA0CH1_CR_RXOFFSETVDQ_Lane4_MAX                         (0x0000000F)
+  #define DDRDATA0CH1_CR_RXOFFSETVDQ_Lane5_OFF                         (20)
+  #define DDRDATA0CH1_CR_RXOFFSETVDQ_Lane5_WID                         ( 4)
+  #define DDRDATA0CH1_CR_RXOFFSETVDQ_Lane5_MSK                         (0x00F00000)
+  #define DDRDATA0CH1_CR_RXOFFSETVDQ_Lane5_MAX                         (0x0000000F)
+  #define DDRDATA0CH1_CR_RXOFFSETVDQ_Lane6_OFF                         (24)
+  #define DDRDATA0CH1_CR_RXOFFSETVDQ_Lane6_WID                         ( 4)
+  #define DDRDATA0CH1_CR_RXOFFSETVDQ_Lane6_MSK                         (0x0F000000)
+  #define DDRDATA0CH1_CR_RXOFFSETVDQ_Lane6_MAX                         (0x0000000F)
+  #define DDRDATA0CH1_CR_RXOFFSETVDQ_Lane7_OFF                         (28)
+  #define DDRDATA0CH1_CR_RXOFFSETVDQ_Lane7_WID                         ( 4)
+  #define DDRDATA0CH1_CR_RXOFFSETVDQ_Lane7_MSK                         (0xF0000000)
+  #define DDRDATA0CH1_CR_RXOFFSETVDQ_Lane7_MAX                         (0x0000000F)
+
+#define DDRDATA0CH1_CR_DDRDATARESERVED_REG                           (0x00000150)
+  #define DDRDATA0CH1_CR_DDRDATARESERVED_Spare_OFF                     ( 0)
+  #define DDRDATA0CH1_CR_DDRDATARESERVED_Spare_WID                     (32)
+  #define DDRDATA0CH1_CR_DDRDATARESERVED_Spare_MSK                     (0xFFFFFFFF)
+  #define DDRDATA0CH1_CR_DDRDATARESERVED_Spare_MAX                     (0xFFFFFFFF)
+
+#define DDRDATA0CH1_CR_DATATRAINFEEDBACK_REG                         (0x00000154)
+  #define DDRDATA0CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_OFF       ( 0)
+  #define DDRDATA0CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_WID       ( 9)
+  #define DDRDATA0CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_MSK       (0x000001FF)
+  #define DDRDATA0CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_MAX       (0x000001FF)
+  #define DDRDATA0CH1_CR_DATATRAINFEEDBACK_Spare_OFF                   ( 9)
+  #define DDRDATA0CH1_CR_DATATRAINFEEDBACK_Spare_WID                   (23)
+  #define DDRDATA0CH1_CR_DATATRAINFEEDBACK_Spare_MSK                   (0xFFFFFE00)
+  #define DDRDATA0CH1_CR_DATATRAINFEEDBACK_Spare_MAX                   (0x007FFFFF)
+
+#define DDRDATA0CH1_CR_DLLPITESTANDADC_REG                           (0x00000158)
+  #define DDRDATA0CH1_CR_DLLPITESTANDADC_RunTest_OFF                   ( 0)
+  #define DDRDATA0CH1_CR_DLLPITESTANDADC_RunTest_WID                   ( 1)
+  #define DDRDATA0CH1_CR_DLLPITESTANDADC_RunTest_MSK                   (0x00000001)
+  #define DDRDATA0CH1_CR_DLLPITESTANDADC_RunTest_MAX                   (0x00000001)
+  #define DDRDATA0CH1_CR_DLLPITESTANDADC_RunTest_DEF                   (0x00000000)
+  #define DDRDATA0CH1_CR_DLLPITESTANDADC_Load_OFF                      ( 1)
+  #define DDRDATA0CH1_CR_DLLPITESTANDADC_Load_WID                      ( 1)
+  #define DDRDATA0CH1_CR_DLLPITESTANDADC_Load_MSK                      (0x00000002)
+  #define DDRDATA0CH1_CR_DLLPITESTANDADC_Load_MAX                      (0x00000001)
+  #define DDRDATA0CH1_CR_DLLPITESTANDADC_Load_DEF                      (0x00000000)
+  #define DDRDATA0CH1_CR_DLLPITESTANDADC_ModeHVM_OFF                   ( 2)
+  #define DDRDATA0CH1_CR_DLLPITESTANDADC_ModeHVM_WID                   ( 1)
+  #define DDRDATA0CH1_CR_DLLPITESTANDADC_ModeHVM_MSK                   (0x00000004)
+  #define DDRDATA0CH1_CR_DLLPITESTANDADC_ModeHVM_MAX                   (0x00000001)
+  #define DDRDATA0CH1_CR_DLLPITESTANDADC_ModeHVM_DEF                   (0x00000000)
+  #define DDRDATA0CH1_CR_DLLPITESTANDADC_ModeDV_OFF                    ( 3)
+  #define DDRDATA0CH1_CR_DLLPITESTANDADC_ModeDV_WID                    ( 1)
+  #define DDRDATA0CH1_CR_DLLPITESTANDADC_ModeDV_MSK                    (0x00000008)
+  #define DDRDATA0CH1_CR_DLLPITESTANDADC_ModeDV_MAX                    (0x00000001)
+  #define DDRDATA0CH1_CR_DLLPITESTANDADC_ModeDV_DEF                    (0x00000000)
+  #define DDRDATA0CH1_CR_DLLPITESTANDADC_ModeADC_OFF                   ( 4)
+  #define DDRDATA0CH1_CR_DLLPITESTANDADC_ModeADC_WID                   ( 1)
+  #define DDRDATA0CH1_CR_DLLPITESTANDADC_ModeADC_MSK                   (0x00000010)
+  #define DDRDATA0CH1_CR_DLLPITESTANDADC_ModeADC_MAX                   (0x00000001)
+  #define DDRDATA0CH1_CR_DLLPITESTANDADC_ModeADC_DEF                   (0x00000000)
+  #define DDRDATA0CH1_CR_DLLPITESTANDADC_LoadCount_OFF                 ( 5)
+  #define DDRDATA0CH1_CR_DLLPITESTANDADC_LoadCount_WID                 (10)
+  #define DDRDATA0CH1_CR_DLLPITESTANDADC_LoadCount_MSK                 (0x00007FE0)
+  #define DDRDATA0CH1_CR_DLLPITESTANDADC_LoadCount_MAX                 (0x000003FF)
+  #define DDRDATA0CH1_CR_DLLPITESTANDADC_CountStatus_OFF               (15)
+  #define DDRDATA0CH1_CR_DLLPITESTANDADC_CountStatus_WID               (10)
+  #define DDRDATA0CH1_CR_DLLPITESTANDADC_CountStatus_MSK               (0x01FF8000)
+  #define DDRDATA0CH1_CR_DLLPITESTANDADC_CountStatus_MAX               (0x000003FF)
+  #define DDRDATA0CH1_CR_DLLPITESTANDADC_CountStatus_DEF               (0x00000000)
+  #define DDRDATA0CH1_CR_DLLPITESTANDADC_Spare_OFF                     (25)
+  #define DDRDATA0CH1_CR_DLLPITESTANDADC_Spare_WID                     ( 7)
+  #define DDRDATA0CH1_CR_DLLPITESTANDADC_Spare_MSK                     (0xFE000000)
+  #define DDRDATA0CH1_CR_DLLPITESTANDADC_Spare_MAX                     (0x0000007F)
+
+#define DDRDATA0CH1_CR_DDRCRDATAOFFSETCOMP_REG                       (0x0000015C)
+  #define DDRDATA0CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_OFF     ( 0)
+  #define DDRDATA0CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_WID     ( 6)
+  #define DDRDATA0CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MSK     (0x0000003F)
+  #define DDRDATA0CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MAX     (0x0000003F)
+  #define DDRDATA0CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_DEF     (0x00000000)
+  #define DDRDATA0CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_OFF   ( 6)
+  #define DDRDATA0CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_WID   ( 6)
+  #define DDRDATA0CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MSK   (0x00000FC0)
+  #define DDRDATA0CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MAX   (0x0000003F)
+  #define DDRDATA0CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_DEF   (0x00000000)
+  #define DDRDATA0CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_OFF     (12)
+  #define DDRDATA0CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_WID     ( 5)
+  #define DDRDATA0CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MSK     (0x0001F000)
+  #define DDRDATA0CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MAX     (0x0000001F)
+  #define DDRDATA0CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_DEF     (0x00000000)
+  #define DDRDATA0CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_OFF   (17)
+  #define DDRDATA0CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_WID   ( 5)
+  #define DDRDATA0CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MSK   (0x003E0000)
+  #define DDRDATA0CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MAX   (0x0000001F)
+  #define DDRDATA0CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_DEF   (0x00000000)
+  #define DDRDATA0CH1_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_OFF       (22)
+  #define DDRDATA0CH1_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_WID       ( 5)
+  #define DDRDATA0CH1_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_MSK       (0x07C00000)
+  #define DDRDATA0CH1_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_MAX       (0x0000001F)
+  #define DDRDATA0CH1_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_DEF       (0x00000000)
+  #define DDRDATA0CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_OFF  (27)
+  #define DDRDATA0CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_WID  ( 5)
+  #define DDRDATA0CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MSK  (0xF8000000)
+  #define DDRDATA0CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MAX  (0x0000001F)
+  #define DDRDATA0CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_DEF  (0x00000000)
+
+#define DDRDATA0CH1_CR_DDRCRDATACONTROL1_REG                         (0x00000160)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_RefPi_OFF                   ( 0)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_RefPi_WID                   ( 4)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_RefPi_MSK                   (0x0000000F)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_RefPi_MAX                   (0x0000000F)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_RefPi_DEF                   (0x00000000)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_DllMask_OFF                 ( 4)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_DllMask_WID                 ( 2)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_DllMask_MSK                 (0x00000030)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_DllMask_MAX                 (0x00000003)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_DllMask_DEF                 (0x00000000)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_DllWeakLock_OFF             ( 6)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_DllWeakLock_WID             ( 1)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_DllWeakLock_MSK             (0x00000040)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_DllWeakLock_MAX             (0x00000001)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_DllWeakLock_DEF             (0x00000000)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_OFF      ( 7)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_WID      ( 3)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MSK      (0x00000380)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MAX      (0x00000007)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_DEF      (0x00000000)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_OFF               (10)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_WID               ( 3)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_MSK               (0x00001C00)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_MAX               (0x00000007)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_DEF               (0x00000000)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_OdtDelay_OFF                (13)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_OdtDelay_WID                ( 4)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_OdtDelay_MSK                (0x0001E000)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_OdtDelay_MAX                (0x0000000F)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_OdtDelay_DEF                (0x00000000)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_OdtDuration_OFF             (17)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_OdtDuration_WID             ( 3)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_OdtDuration_MSK             (0x000E0000)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_OdtDuration_MAX             (0x00000007)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_OdtDuration_DEF             (0x00000000)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_OFF           (20)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_WID           ( 4)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_MSK           (0x00F00000)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_MAX           (0x0000000F)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_DEF           (0x00000000)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_OFF        (24)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_WID        ( 3)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_MSK        (0x07000000)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_MAX        (0x00000007)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_DEF        (0x00000000)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_BurstEndODTDelay_OFF        (27)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_BurstEndODTDelay_WID        ( 3)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_BurstEndODTDelay_MSK        (0x38000000)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_BurstEndODTDelay_MAX        (0x00000007)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_BurstEndODTDelay_DEF        (0x00000000)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_OFF          (30)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_WID          ( 1)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_MSK          (0x40000000)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_MAX          (0x00000001)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_DEF          (0x00000000)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_Rsvd1_OFF                   (31)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_Rsvd1_WID                   ( 1)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_Rsvd1_MSK                   (0x80000000)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_Rsvd1_MAX                   (0x00000001)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_Rsvd1_DEF                   (0x00000000)
+
+#define DDRDATA0CH1_CR_DDRCRDATACONTROL2_REG                         (0x00000164)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_OFF            ( 0)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_WID            ( 5)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_MSK            (0x0000001F)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_MAX            (0x0000001F)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_DEF            (0x00000000)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_OFF             ( 5)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_WID             ( 1)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_MSK             (0x00000020)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_MAX             (0x00000001)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_DEF             (0x00000000)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_ForceRxOn_OFF               ( 6)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_ForceRxOn_WID               ( 1)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_ForceRxOn_MSK               (0x00000040)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_ForceRxOn_MAX               (0x00000001)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_ForceRxOn_DEF               (0x00000000)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_LeakerComp_OFF              ( 7)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_LeakerComp_WID              ( 2)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_LeakerComp_MSK              (0x00000180)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_LeakerComp_MAX              (0x00000003)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_LeakerComp_DEF              (0x00000000)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_OFF          ( 9)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_WID          ( 4)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_MSK          (0x00001E00)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_MAX          (0x0000000F)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_DEF          (0x00000008)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_OFF             (13)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_WID             ( 5)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_MSK             (0x0003E000)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_MAX             (0x0000001F)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_DEF             (0x00000011)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_OFF             (18)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_WID             ( 1)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_MSK             (0x00040000)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_MAX             (0x00000001)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_DEF             (0x00000000)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_Spare_OFF                   (19)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_Spare_WID                   (13)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_Spare_MSK                   (0xFFF80000)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_Spare_MAX                   (0x00001FFF)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_Spare_DEF                   (0x00000000)
+
+#define DDRDATA0CH1_CR_DDRCRVSSHIORVREFCONTROL_REG                   (0x0000016C)
+  #define DDRDATA0CH1_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_OFF    ( 0)
+  #define DDRDATA0CH1_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_WID    (24)
+  #define DDRDATA0CH1_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_MSK    (0x00FFFFFF)
+  #define DDRDATA0CH1_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_MAX    (0x00FFFFFF)
+  #define DDRDATA0CH1_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_DEF    (0x00000000)
+  #define DDRDATA0CH1_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_OFF        (24)
+  #define DDRDATA0CH1_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_WID        ( 8)
+  #define DDRDATA0CH1_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_MSK        (0xFF000000)
+  #define DDRDATA0CH1_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_MAX        (0x000000FF)
+  #define DDRDATA0CH1_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_DEF        (0x00000000)
+
+#define DDRDATA0CH1_CR_DDRCRDATAOFFSETTRAIN_REG                      (0x00000170)
+  #define DDRDATA0CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_OFF          ( 0)
+  #define DDRDATA0CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_WID          ( 6)
+  #define DDRDATA0CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MSK          (0x0000003F)
+  #define DDRDATA0CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MAX          (0x0000003F)
+  #define DDRDATA0CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_DEF          (0x00000000)
+  #define DDRDATA0CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_OFF          ( 6)
+  #define DDRDATA0CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_WID          ( 6)
+  #define DDRDATA0CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MSK          (0x00000FC0)
+  #define DDRDATA0CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MAX          (0x0000003F)
+  #define DDRDATA0CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_DEF          (0x00000000)
+  #define DDRDATA0CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_OFF           (12)
+  #define DDRDATA0CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_WID           ( 6)
+  #define DDRDATA0CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MSK           (0x0003F000)
+  #define DDRDATA0CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MAX           (0x0000003F)
+  #define DDRDATA0CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_DEF           (0x00000000)
+  #define DDRDATA0CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_OFF          (18)
+  #define DDRDATA0CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_WID          ( 6)
+  #define DDRDATA0CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MSK          (0x00FC0000)
+  #define DDRDATA0CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MAX          (0x0000003F)
+  #define DDRDATA0CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_DEF          (0x00000000)
+  #define DDRDATA0CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_OFF           (24)
+  #define DDRDATA0CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_WID           ( 7)
+  #define DDRDATA0CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MSK           (0x7F000000)
+  #define DDRDATA0CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MAX           (0x0000007F)
+  #define DDRDATA0CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_DEF           (0x00000000)
+  #define DDRDATA0CH1_CR_DDRCRDATAOFFSETTRAIN_Spare_OFF                (31)
+  #define DDRDATA0CH1_CR_DDRCRDATAOFFSETTRAIN_Spare_WID                ( 1)
+  #define DDRDATA0CH1_CR_DDRCRDATAOFFSETTRAIN_Spare_MSK                (0x80000000)
+  #define DDRDATA0CH1_CR_DDRCRDATAOFFSETTRAIN_Spare_MAX                (0x00000001)
+  #define DDRDATA0CH1_CR_DDRCRDATAOFFSETTRAIN_Spare_DEF                (0x00000000)
+
+#define DDRDATA0CH1_CR_DDRCRDATACONTROL0_REG                         (0x00000174)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_OFF          ( 0)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_WID          ( 1)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_MSK          (0x00000001)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_MAX          (0x00000001)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_DEF          (0x00000000)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_OFF          ( 1)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_WID          ( 1)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_MSK          (0x00000002)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_MAX          (0x00000001)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_DEF          (0x00000000)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_OFF          ( 2)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_WID          ( 1)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_MSK          (0x00000004)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_MAX          (0x00000001)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_DEF          (0x00000000)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_OFF    ( 3)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_WID    ( 1)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MSK    (0x00000008)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MAX    (0x00000001)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_DEF    (0x00000000)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_TxOn_OFF                    ( 4)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_TxOn_WID                    ( 1)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_TxOn_MSK                    (0x00000010)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_TxOn_MAX                    (0x00000001)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_TxOn_DEF                    (0x00000000)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RfOn_OFF                    ( 5)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RfOn_WID                    ( 1)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RfOn_MSK                    (0x00000020)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RfOn_MAX                    (0x00000001)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RfOn_DEF                    (0x00000000)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RxPiOn_OFF                  ( 6)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RxPiOn_WID                  ( 1)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RxPiOn_MSK                  (0x00000040)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RxPiOn_MAX                  (0x00000001)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RxPiOn_DEF                  (0x00000000)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_TxPiOn_OFF                  ( 7)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_TxPiOn_WID                  ( 1)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_TxPiOn_MSK                  (0x00000080)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_TxPiOn_MAX                  (0x00000001)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_TxPiOn_DEF                  (0x00000000)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_OFF        ( 8)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_WID        ( 1)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_MSK        (0x00000100)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_MAX        (0x00000001)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_DEF        (0x00000000)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_OFF        ( 9)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_WID        ( 1)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MSK        (0x00000200)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MAX        (0x00000001)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_DEF        (0x00000000)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_TxDisable_OFF               (10)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_TxDisable_WID               ( 1)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_TxDisable_MSK               (0x00000400)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_TxDisable_MAX               (0x00000001)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_TxDisable_DEF               (0x00000000)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RxDisable_OFF               (11)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RxDisable_WID               ( 1)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RxDisable_MSK               (0x00000800)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RxDisable_MAX               (0x00000001)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RxDisable_DEF               (0x00000000)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_TxLong_OFF                  (12)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_TxLong_WID                  ( 1)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_TxLong_MSK                  (0x00001000)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_TxLong_MAX                  (0x00000001)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_TxLong_DEF                  (0x00000000)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_OFF               (13)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_WID               ( 2)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_MSK               (0x00006000)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_MAX               (0x00000003)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_DEF               (0x00000000)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RxReadPointer_OFF           (15)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RxReadPointer_WID           ( 3)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RxReadPointer_MSK           (0x00038000)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RxReadPointer_MAX           (0x00000007)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RxReadPointer_DEF           (0x00000000)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_DriverSegmentEnable_OFF     (18)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_DriverSegmentEnable_WID     ( 1)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_DriverSegmentEnable_MSK     (0x00040000)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_DriverSegmentEnable_MAX     (0x00000001)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_DriverSegmentEnable_DEF     (0x00000000)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_DataVccddqHi_OFF            (19)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_DataVccddqHi_WID            ( 1)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_DataVccddqHi_MSK            (0x00080000)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_DataVccddqHi_MAX            (0x00000001)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_DataVccddqHi_DEF            (0x00000000)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_ReadRFRd_OFF                (20)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_ReadRFRd_WID                ( 1)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_ReadRFRd_MSK                (0x00100000)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_ReadRFRd_MAX                (0x00000001)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_ReadRFRd_DEF                (0x00000000)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_ReadRFWr_OFF                (21)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_ReadRFWr_WID                ( 1)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_ReadRFWr_MSK                (0x00200000)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_ReadRFWr_MAX                (0x00000001)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_ReadRFWr_DEF                (0x00000000)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_ReadRFRank_OFF              (22)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_ReadRFRank_WID              ( 2)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_ReadRFRank_MSK              (0x00C00000)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_ReadRFRank_MAX              (0x00000003)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_ReadRFRank_DEF              (0x00000000)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_OFF              (24)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_WID              ( 1)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_MSK              (0x01000000)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_MAX              (0x00000001)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_DEF              (0x00000000)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_OdtSampOff_OFF              (25)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_OdtSampOff_WID              ( 1)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_OdtSampOff_MSK              (0x02000000)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_OdtSampOff_MAX              (0x00000001)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_OdtSampOff_DEF              (0x00000000)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_OFF        (26)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_WID        ( 1)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_MSK        (0x04000000)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_MAX        (0x00000001)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_DEF        (0x00000000)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_OFF         (27)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_WID         ( 1)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MSK         (0x08000000)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MAX         (0x00000001)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_DEF         (0x00000000)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_OFF              (28)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_WID              ( 1)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_MSK              (0x10000000)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_MAX              (0x00000001)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_DEF              (0x00000000)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_EnReadPreamble_OFF          (29)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_EnReadPreamble_WID          ( 1)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_EnReadPreamble_MSK          (0x20000000)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_EnReadPreamble_MAX          (0x00000001)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_EnReadPreamble_DEF          (0x00000000)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_OFF         (30)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_WID         ( 1)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MSK         (0x40000000)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MAX         (0x00000001)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_DEF         (0x00000000)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_OFF            (31)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_WID            ( 1)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_MSK            (0x80000000)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_MAX            (0x00000001)
+  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_DEF            (0x00000000)
+
+#define DDRDATA0CH1_CR_DDRCRVREFADJUST1_REG                          (0x00000178)
+  #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_CAVrefCtl_OFF                ( 0)
+  #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_CAVrefCtl_WID                ( 7)
+  #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_CAVrefCtl_MSK                (0x0000007F)
+  #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_CAVrefCtl_MAX                (0x0000007F)
+  #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_CAVrefCtl_DEF                (0x00000000)
+  #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_Ch1VrefCtl_OFF               ( 7)
+  #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_Ch1VrefCtl_WID               ( 7)
+  #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_Ch1VrefCtl_MSK               (0x00003F80)
+  #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_Ch1VrefCtl_MAX               (0x0000007F)
+  #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_Ch1VrefCtl_DEF               (0x00000000)
+  #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_Ch0VrefCtl_OFF               (14)
+  #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_Ch0VrefCtl_WID               ( 7)
+  #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_Ch0VrefCtl_MSK               (0x001FC000)
+  #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_Ch0VrefCtl_MAX               (0x0000007F)
+  #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_Ch0VrefCtl_DEF               (0x00000000)
+  #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCA_OFF             (21)
+  #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCA_WID             ( 1)
+  #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCA_MSK             (0x00200000)
+  #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCA_MAX             (0x00000001)
+  #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCA_DEF             (0x00000000)
+  #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_OFF            (22)
+  #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_WID            ( 1)
+  #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_MSK            (0x00400000)
+  #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_MAX            (0x00000001)
+  #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_DEF            (0x00000000)
+  #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_OFF            (23)
+  #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_WID            ( 1)
+  #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_MSK            (0x00800000)
+  #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_MAX            (0x00000001)
+  #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_DEF            (0x00000000)
+  #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_HiZTimerCtrl_OFF             (24)
+  #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_HiZTimerCtrl_WID             ( 2)
+  #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_HiZTimerCtrl_MSK             (0x03000000)
+  #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_HiZTimerCtrl_MAX             (0x00000003)
+  #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_HiZTimerCtrl_DEF             (0x00000000)
+  #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_OFF            (26)
+  #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_WID            ( 1)
+  #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_MSK            (0x04000000)
+  #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_MAX            (0x00000001)
+  #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_DEF            (0x00000000)
+  #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_Rsvd_OFF                     (27)
+  #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_Rsvd_WID                     ( 2)
+  #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_Rsvd_MSK                     (0x18000000)
+  #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_Rsvd_MAX                     (0x00000003)
+  #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_Rsvd_DEF                     (0x00000000)
+  #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_caSlowBW_OFF                 (29)
+  #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_caSlowBW_WID                 ( 1)
+  #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_caSlowBW_MSK                 (0x20000000)
+  #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_caSlowBW_MAX                 (0x00000001)
+  #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_caSlowBW_DEF                 (0x00000000)
+  #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_ch0SlowBW_OFF                (30)
+  #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_ch0SlowBW_WID                ( 1)
+  #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_ch0SlowBW_MSK                (0x40000000)
+  #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_ch0SlowBW_MAX                (0x00000001)
+  #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_ch0SlowBW_DEF                (0x00000000)
+  #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_ch1SlowBW_OFF                (31)
+  #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_ch1SlowBW_WID                ( 1)
+  #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_ch1SlowBW_MSK                (0x80000000)
+  #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_ch1SlowBW_MAX                (0x00000001)
+  #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_ch1SlowBW_DEF                (0x00000000)
+
+#define DDRDATA1CH0_CR_RXTRAINRANK0_REG                              (0x00000200)
+  #define DDRDATA1CH0_CR_RXTRAINRANK0_RxRcvEnPi_OFF                    ( 0)
+  #define DDRDATA1CH0_CR_RXTRAINRANK0_RxRcvEnPi_WID                    ( 9)
+  #define DDRDATA1CH0_CR_RXTRAINRANK0_RxRcvEnPi_MSK                    (0x000001FF)
+  #define DDRDATA1CH0_CR_RXTRAINRANK0_RxRcvEnPi_MAX                    (0x000001FF)
+  #define DDRDATA1CH0_CR_RXTRAINRANK0_RxDqsPPi_OFF                     ( 9)
+  #define DDRDATA1CH0_CR_RXTRAINRANK0_RxDqsPPi_WID                     ( 6)
+  #define DDRDATA1CH0_CR_RXTRAINRANK0_RxDqsPPi_MSK                     (0x00007E00)
+  #define DDRDATA1CH0_CR_RXTRAINRANK0_RxDqsPPi_MAX                     (0x0000003F)
+  #define DDRDATA1CH0_CR_RXTRAINRANK0_RxEq_OFF                         (15)
+  #define DDRDATA1CH0_CR_RXTRAINRANK0_RxEq_WID                         ( 5)
+  #define DDRDATA1CH0_CR_RXTRAINRANK0_RxEq_MSK                         (0x000F8000)
+  #define DDRDATA1CH0_CR_RXTRAINRANK0_RxEq_MAX                         (0x0000001F)
+  #define DDRDATA1CH0_CR_RXTRAINRANK0_RxDqsNPi_OFF                     (20)
+  #define DDRDATA1CH0_CR_RXTRAINRANK0_RxDqsNPi_WID                     ( 6)
+  #define DDRDATA1CH0_CR_RXTRAINRANK0_RxDqsNPi_MSK                     (0x03F00000)
+  #define DDRDATA1CH0_CR_RXTRAINRANK0_RxDqsNPi_MAX                     (0x0000003F)
+  #define DDRDATA1CH0_CR_RXTRAINRANK0_RxVref_OFF                       (26)
+  #define DDRDATA1CH0_CR_RXTRAINRANK0_RxVref_WID                       ( 6)
+  #define DDRDATA1CH0_CR_RXTRAINRANK0_RxVref_MSK                       (0xFC000000)
+  #define DDRDATA1CH0_CR_RXTRAINRANK0_RxVref_MAX                       (0x0000003F)
+
+#define DDRDATA1CH0_CR_RXTRAINRANK1_REG                              (0x00000204)
+  #define DDRDATA1CH0_CR_RXTRAINRANK1_RxRcvEnPi_OFF                    ( 0)
+  #define DDRDATA1CH0_CR_RXTRAINRANK1_RxRcvEnPi_WID                    ( 9)
+  #define DDRDATA1CH0_CR_RXTRAINRANK1_RxRcvEnPi_MSK                    (0x000001FF)
+  #define DDRDATA1CH0_CR_RXTRAINRANK1_RxRcvEnPi_MAX                    (0x000001FF)
+  #define DDRDATA1CH0_CR_RXTRAINRANK1_RxDqsPPi_OFF                     ( 9)
+  #define DDRDATA1CH0_CR_RXTRAINRANK1_RxDqsPPi_WID                     ( 6)
+  #define DDRDATA1CH0_CR_RXTRAINRANK1_RxDqsPPi_MSK                     (0x00007E00)
+  #define DDRDATA1CH0_CR_RXTRAINRANK1_RxDqsPPi_MAX                     (0x0000003F)
+  #define DDRDATA1CH0_CR_RXTRAINRANK1_RxEq_OFF                         (15)
+  #define DDRDATA1CH0_CR_RXTRAINRANK1_RxEq_WID                         ( 5)
+  #define DDRDATA1CH0_CR_RXTRAINRANK1_RxEq_MSK                         (0x000F8000)
+  #define DDRDATA1CH0_CR_RXTRAINRANK1_RxEq_MAX                         (0x0000001F)
+  #define DDRDATA1CH0_CR_RXTRAINRANK1_RxDqsNPi_OFF                     (20)
+  #define DDRDATA1CH0_CR_RXTRAINRANK1_RxDqsNPi_WID                     ( 6)
+  #define DDRDATA1CH0_CR_RXTRAINRANK1_RxDqsNPi_MSK                     (0x03F00000)
+  #define DDRDATA1CH0_CR_RXTRAINRANK1_RxDqsNPi_MAX                     (0x0000003F)
+  #define DDRDATA1CH0_CR_RXTRAINRANK1_RxVref_OFF                       (26)
+  #define DDRDATA1CH0_CR_RXTRAINRANK1_RxVref_WID                       ( 6)
+  #define DDRDATA1CH0_CR_RXTRAINRANK1_RxVref_MSK                       (0xFC000000)
+  #define DDRDATA1CH0_CR_RXTRAINRANK1_RxVref_MAX                       (0x0000003F)
+
+#define DDRDATA1CH0_CR_RXTRAINRANK2_REG                              (0x00000208)
+  #define DDRDATA1CH0_CR_RXTRAINRANK2_RxRcvEnPi_OFF                    ( 0)
+  #define DDRDATA1CH0_CR_RXTRAINRANK2_RxRcvEnPi_WID                    ( 9)
+  #define DDRDATA1CH0_CR_RXTRAINRANK2_RxRcvEnPi_MSK                    (0x000001FF)
+  #define DDRDATA1CH0_CR_RXTRAINRANK2_RxRcvEnPi_MAX                    (0x000001FF)
+  #define DDRDATA1CH0_CR_RXTRAINRANK2_RxDqsPPi_OFF                     ( 9)
+  #define DDRDATA1CH0_CR_RXTRAINRANK2_RxDqsPPi_WID                     ( 6)
+  #define DDRDATA1CH0_CR_RXTRAINRANK2_RxDqsPPi_MSK                     (0x00007E00)
+  #define DDRDATA1CH0_CR_RXTRAINRANK2_RxDqsPPi_MAX                     (0x0000003F)
+  #define DDRDATA1CH0_CR_RXTRAINRANK2_RxEq_OFF                         (15)
+  #define DDRDATA1CH0_CR_RXTRAINRANK2_RxEq_WID                         ( 5)
+  #define DDRDATA1CH0_CR_RXTRAINRANK2_RxEq_MSK                         (0x000F8000)
+  #define DDRDATA1CH0_CR_RXTRAINRANK2_RxEq_MAX                         (0x0000001F)
+  #define DDRDATA1CH0_CR_RXTRAINRANK2_RxDqsNPi_OFF                     (20)
+  #define DDRDATA1CH0_CR_RXTRAINRANK2_RxDqsNPi_WID                     ( 6)
+  #define DDRDATA1CH0_CR_RXTRAINRANK2_RxDqsNPi_MSK                     (0x03F00000)
+  #define DDRDATA1CH0_CR_RXTRAINRANK2_RxDqsNPi_MAX                     (0x0000003F)
+  #define DDRDATA1CH0_CR_RXTRAINRANK2_RxVref_OFF                       (26)
+  #define DDRDATA1CH0_CR_RXTRAINRANK2_RxVref_WID                       ( 6)
+  #define DDRDATA1CH0_CR_RXTRAINRANK2_RxVref_MSK                       (0xFC000000)
+  #define DDRDATA1CH0_CR_RXTRAINRANK2_RxVref_MAX                       (0x0000003F)
+
+#define DDRDATA1CH0_CR_RXTRAINRANK3_REG                              (0x0000020C)
+  #define DDRDATA1CH0_CR_RXTRAINRANK3_RxRcvEnPi_OFF                    ( 0)
+  #define DDRDATA1CH0_CR_RXTRAINRANK3_RxRcvEnPi_WID                    ( 9)
+  #define DDRDATA1CH0_CR_RXTRAINRANK3_RxRcvEnPi_MSK                    (0x000001FF)
+  #define DDRDATA1CH0_CR_RXTRAINRANK3_RxRcvEnPi_MAX                    (0x000001FF)
+  #define DDRDATA1CH0_CR_RXTRAINRANK3_RxDqsPPi_OFF                     ( 9)
+  #define DDRDATA1CH0_CR_RXTRAINRANK3_RxDqsPPi_WID                     ( 6)
+  #define DDRDATA1CH0_CR_RXTRAINRANK3_RxDqsPPi_MSK                     (0x00007E00)
+  #define DDRDATA1CH0_CR_RXTRAINRANK3_RxDqsPPi_MAX                     (0x0000003F)
+  #define DDRDATA1CH0_CR_RXTRAINRANK3_RxEq_OFF                         (15)
+  #define DDRDATA1CH0_CR_RXTRAINRANK3_RxEq_WID                         ( 5)
+  #define DDRDATA1CH0_CR_RXTRAINRANK3_RxEq_MSK                         (0x000F8000)
+  #define DDRDATA1CH0_CR_RXTRAINRANK3_RxEq_MAX                         (0x0000001F)
+  #define DDRDATA1CH0_CR_RXTRAINRANK3_RxDqsNPi_OFF                     (20)
+  #define DDRDATA1CH0_CR_RXTRAINRANK3_RxDqsNPi_WID                     ( 6)
+  #define DDRDATA1CH0_CR_RXTRAINRANK3_RxDqsNPi_MSK                     (0x03F00000)
+  #define DDRDATA1CH0_CR_RXTRAINRANK3_RxDqsNPi_MAX                     (0x0000003F)
+  #define DDRDATA1CH0_CR_RXTRAINRANK3_RxVref_OFF                       (26)
+  #define DDRDATA1CH0_CR_RXTRAINRANK3_RxVref_WID                       ( 6)
+  #define DDRDATA1CH0_CR_RXTRAINRANK3_RxVref_MSK                       (0xFC000000)
+  #define DDRDATA1CH0_CR_RXTRAINRANK3_RxVref_MAX                       (0x0000003F)
+
+#define DDRDATA1CH0_CR_RXPERBITRANK0_REG                             (0x00000210)
+  #define DDRDATA1CH0_CR_RXPERBITRANK0_Lane0_OFF                       ( 0)
+  #define DDRDATA1CH0_CR_RXPERBITRANK0_Lane0_WID                       ( 4)
+  #define DDRDATA1CH0_CR_RXPERBITRANK0_Lane0_MSK                       (0x0000000F)
+  #define DDRDATA1CH0_CR_RXPERBITRANK0_Lane0_MAX                       (0x0000000F)
+  #define DDRDATA1CH0_CR_RXPERBITRANK0_Lane1_OFF                       ( 4)
+  #define DDRDATA1CH0_CR_RXPERBITRANK0_Lane1_WID                       ( 4)
+  #define DDRDATA1CH0_CR_RXPERBITRANK0_Lane1_MSK                       (0x000000F0)
+  #define DDRDATA1CH0_CR_RXPERBITRANK0_Lane1_MAX                       (0x0000000F)
+  #define DDRDATA1CH0_CR_RXPERBITRANK0_Lane2_OFF                       ( 8)
+  #define DDRDATA1CH0_CR_RXPERBITRANK0_Lane2_WID                       ( 4)
+  #define DDRDATA1CH0_CR_RXPERBITRANK0_Lane2_MSK                       (0x00000F00)
+  #define DDRDATA1CH0_CR_RXPERBITRANK0_Lane2_MAX                       (0x0000000F)
+  #define DDRDATA1CH0_CR_RXPERBITRANK0_Lane3_OFF                       (12)
+  #define DDRDATA1CH0_CR_RXPERBITRANK0_Lane3_WID                       ( 4)
+  #define DDRDATA1CH0_CR_RXPERBITRANK0_Lane3_MSK                       (0x0000F000)
+  #define DDRDATA1CH0_CR_RXPERBITRANK0_Lane3_MAX                       (0x0000000F)
+  #define DDRDATA1CH0_CR_RXPERBITRANK0_Lane4_OFF                       (16)
+  #define DDRDATA1CH0_CR_RXPERBITRANK0_Lane4_WID                       ( 4)
+  #define DDRDATA1CH0_CR_RXPERBITRANK0_Lane4_MSK                       (0x000F0000)
+  #define DDRDATA1CH0_CR_RXPERBITRANK0_Lane4_MAX                       (0x0000000F)
+  #define DDRDATA1CH0_CR_RXPERBITRANK0_Lane5_OFF                       (20)
+  #define DDRDATA1CH0_CR_RXPERBITRANK0_Lane5_WID                       ( 4)
+  #define DDRDATA1CH0_CR_RXPERBITRANK0_Lane5_MSK                       (0x00F00000)
+  #define DDRDATA1CH0_CR_RXPERBITRANK0_Lane5_MAX                       (0x0000000F)
+  #define DDRDATA1CH0_CR_RXPERBITRANK0_Lane6_OFF                       (24)
+  #define DDRDATA1CH0_CR_RXPERBITRANK0_Lane6_WID                       ( 4)
+  #define DDRDATA1CH0_CR_RXPERBITRANK0_Lane6_MSK                       (0x0F000000)
+  #define DDRDATA1CH0_CR_RXPERBITRANK0_Lane6_MAX                       (0x0000000F)
+  #define DDRDATA1CH0_CR_RXPERBITRANK0_Lane7_OFF                       (28)
+  #define DDRDATA1CH0_CR_RXPERBITRANK0_Lane7_WID                       ( 4)
+  #define DDRDATA1CH0_CR_RXPERBITRANK0_Lane7_MSK                       (0xF0000000)
+  #define DDRDATA1CH0_CR_RXPERBITRANK0_Lane7_MAX                       (0x0000000F)
+
+#define DDRDATA1CH0_CR_RXPERBITRANK1_REG                             (0x00000214)
+  #define DDRDATA1CH0_CR_RXPERBITRANK1_Lane0_OFF                       ( 0)
+  #define DDRDATA1CH0_CR_RXPERBITRANK1_Lane0_WID                       ( 4)
+  #define DDRDATA1CH0_CR_RXPERBITRANK1_Lane0_MSK                       (0x0000000F)
+  #define DDRDATA1CH0_CR_RXPERBITRANK1_Lane0_MAX                       (0x0000000F)
+  #define DDRDATA1CH0_CR_RXPERBITRANK1_Lane1_OFF                       ( 4)
+  #define DDRDATA1CH0_CR_RXPERBITRANK1_Lane1_WID                       ( 4)
+  #define DDRDATA1CH0_CR_RXPERBITRANK1_Lane1_MSK                       (0x000000F0)
+  #define DDRDATA1CH0_CR_RXPERBITRANK1_Lane1_MAX                       (0x0000000F)
+  #define DDRDATA1CH0_CR_RXPERBITRANK1_Lane2_OFF                       ( 8)
+  #define DDRDATA1CH0_CR_RXPERBITRANK1_Lane2_WID                       ( 4)
+  #define DDRDATA1CH0_CR_RXPERBITRANK1_Lane2_MSK                       (0x00000F00)
+  #define DDRDATA1CH0_CR_RXPERBITRANK1_Lane2_MAX                       (0x0000000F)
+  #define DDRDATA1CH0_CR_RXPERBITRANK1_Lane3_OFF                       (12)
+  #define DDRDATA1CH0_CR_RXPERBITRANK1_Lane3_WID                       ( 4)
+  #define DDRDATA1CH0_CR_RXPERBITRANK1_Lane3_MSK                       (0x0000F000)
+  #define DDRDATA1CH0_CR_RXPERBITRANK1_Lane3_MAX                       (0x0000000F)
+  #define DDRDATA1CH0_CR_RXPERBITRANK1_Lane4_OFF                       (16)
+  #define DDRDATA1CH0_CR_RXPERBITRANK1_Lane4_WID                       ( 4)
+  #define DDRDATA1CH0_CR_RXPERBITRANK1_Lane4_MSK                       (0x000F0000)
+  #define DDRDATA1CH0_CR_RXPERBITRANK1_Lane4_MAX                       (0x0000000F)
+  #define DDRDATA1CH0_CR_RXPERBITRANK1_Lane5_OFF                       (20)
+  #define DDRDATA1CH0_CR_RXPERBITRANK1_Lane5_WID                       ( 4)
+  #define DDRDATA1CH0_CR_RXPERBITRANK1_Lane5_MSK                       (0x00F00000)
+  #define DDRDATA1CH0_CR_RXPERBITRANK1_Lane5_MAX                       (0x0000000F)
+  #define DDRDATA1CH0_CR_RXPERBITRANK1_Lane6_OFF                       (24)
+  #define DDRDATA1CH0_CR_RXPERBITRANK1_Lane6_WID                       ( 4)
+  #define DDRDATA1CH0_CR_RXPERBITRANK1_Lane6_MSK                       (0x0F000000)
+  #define DDRDATA1CH0_CR_RXPERBITRANK1_Lane6_MAX                       (0x0000000F)
+  #define DDRDATA1CH0_CR_RXPERBITRANK1_Lane7_OFF                       (28)
+  #define DDRDATA1CH0_CR_RXPERBITRANK1_Lane7_WID                       ( 4)
+  #define DDRDATA1CH0_CR_RXPERBITRANK1_Lane7_MSK                       (0xF0000000)
+  #define DDRDATA1CH0_CR_RXPERBITRANK1_Lane7_MAX                       (0x0000000F)
+
+#define DDRDATA1CH0_CR_RXPERBITRANK2_REG                             (0x00000218)
+  #define DDRDATA1CH0_CR_RXPERBITRANK2_Lane0_OFF                       ( 0)
+  #define DDRDATA1CH0_CR_RXPERBITRANK2_Lane0_WID                       ( 4)
+  #define DDRDATA1CH0_CR_RXPERBITRANK2_Lane0_MSK                       (0x0000000F)
+  #define DDRDATA1CH0_CR_RXPERBITRANK2_Lane0_MAX                       (0x0000000F)
+  #define DDRDATA1CH0_CR_RXPERBITRANK2_Lane1_OFF                       ( 4)
+  #define DDRDATA1CH0_CR_RXPERBITRANK2_Lane1_WID                       ( 4)
+  #define DDRDATA1CH0_CR_RXPERBITRANK2_Lane1_MSK                       (0x000000F0)
+  #define DDRDATA1CH0_CR_RXPERBITRANK2_Lane1_MAX                       (0x0000000F)
+  #define DDRDATA1CH0_CR_RXPERBITRANK2_Lane2_OFF                       ( 8)
+  #define DDRDATA1CH0_CR_RXPERBITRANK2_Lane2_WID                       ( 4)
+  #define DDRDATA1CH0_CR_RXPERBITRANK2_Lane2_MSK                       (0x00000F00)
+  #define DDRDATA1CH0_CR_RXPERBITRANK2_Lane2_MAX                       (0x0000000F)
+  #define DDRDATA1CH0_CR_RXPERBITRANK2_Lane3_OFF                       (12)
+  #define DDRDATA1CH0_CR_RXPERBITRANK2_Lane3_WID                       ( 4)
+  #define DDRDATA1CH0_CR_RXPERBITRANK2_Lane3_MSK                       (0x0000F000)
+  #define DDRDATA1CH0_CR_RXPERBITRANK2_Lane3_MAX                       (0x0000000F)
+  #define DDRDATA1CH0_CR_RXPERBITRANK2_Lane4_OFF                       (16)
+  #define DDRDATA1CH0_CR_RXPERBITRANK2_Lane4_WID                       ( 4)
+  #define DDRDATA1CH0_CR_RXPERBITRANK2_Lane4_MSK                       (0x000F0000)
+  #define DDRDATA1CH0_CR_RXPERBITRANK2_Lane4_MAX                       (0x0000000F)
+  #define DDRDATA1CH0_CR_RXPERBITRANK2_Lane5_OFF                       (20)
+  #define DDRDATA1CH0_CR_RXPERBITRANK2_Lane5_WID                       ( 4)
+  #define DDRDATA1CH0_CR_RXPERBITRANK2_Lane5_MSK                       (0x00F00000)
+  #define DDRDATA1CH0_CR_RXPERBITRANK2_Lane5_MAX                       (0x0000000F)
+  #define DDRDATA1CH0_CR_RXPERBITRANK2_Lane6_OFF                       (24)
+  #define DDRDATA1CH0_CR_RXPERBITRANK2_Lane6_WID                       ( 4)
+  #define DDRDATA1CH0_CR_RXPERBITRANK2_Lane6_MSK                       (0x0F000000)
+  #define DDRDATA1CH0_CR_RXPERBITRANK2_Lane6_MAX                       (0x0000000F)
+  #define DDRDATA1CH0_CR_RXPERBITRANK2_Lane7_OFF                       (28)
+  #define DDRDATA1CH0_CR_RXPERBITRANK2_Lane7_WID                       ( 4)
+  #define DDRDATA1CH0_CR_RXPERBITRANK2_Lane7_MSK                       (0xF0000000)
+  #define DDRDATA1CH0_CR_RXPERBITRANK2_Lane7_MAX                       (0x0000000F)
+
+#define DDRDATA1CH0_CR_RXPERBITRANK3_REG                             (0x0000021C)
+  #define DDRDATA1CH0_CR_RXPERBITRANK3_Lane0_OFF                       ( 0)
+  #define DDRDATA1CH0_CR_RXPERBITRANK3_Lane0_WID                       ( 4)
+  #define DDRDATA1CH0_CR_RXPERBITRANK3_Lane0_MSK                       (0x0000000F)
+  #define DDRDATA1CH0_CR_RXPERBITRANK3_Lane0_MAX                       (0x0000000F)
+  #define DDRDATA1CH0_CR_RXPERBITRANK3_Lane1_OFF                       ( 4)
+  #define DDRDATA1CH0_CR_RXPERBITRANK3_Lane1_WID                       ( 4)
+  #define DDRDATA1CH0_CR_RXPERBITRANK3_Lane1_MSK                       (0x000000F0)
+  #define DDRDATA1CH0_CR_RXPERBITRANK3_Lane1_MAX                       (0x0000000F)
+  #define DDRDATA1CH0_CR_RXPERBITRANK3_Lane2_OFF                       ( 8)
+  #define DDRDATA1CH0_CR_RXPERBITRANK3_Lane2_WID                       ( 4)
+  #define DDRDATA1CH0_CR_RXPERBITRANK3_Lane2_MSK                       (0x00000F00)
+  #define DDRDATA1CH0_CR_RXPERBITRANK3_Lane2_MAX                       (0x0000000F)
+  #define DDRDATA1CH0_CR_RXPERBITRANK3_Lane3_OFF                       (12)
+  #define DDRDATA1CH0_CR_RXPERBITRANK3_Lane3_WID                       ( 4)
+  #define DDRDATA1CH0_CR_RXPERBITRANK3_Lane3_MSK                       (0x0000F000)
+  #define DDRDATA1CH0_CR_RXPERBITRANK3_Lane3_MAX                       (0x0000000F)
+  #define DDRDATA1CH0_CR_RXPERBITRANK3_Lane4_OFF                       (16)
+  #define DDRDATA1CH0_CR_RXPERBITRANK3_Lane4_WID                       ( 4)
+  #define DDRDATA1CH0_CR_RXPERBITRANK3_Lane4_MSK                       (0x000F0000)
+  #define DDRDATA1CH0_CR_RXPERBITRANK3_Lane4_MAX                       (0x0000000F)
+  #define DDRDATA1CH0_CR_RXPERBITRANK3_Lane5_OFF                       (20)
+  #define DDRDATA1CH0_CR_RXPERBITRANK3_Lane5_WID                       ( 4)
+  #define DDRDATA1CH0_CR_RXPERBITRANK3_Lane5_MSK                       (0x00F00000)
+  #define DDRDATA1CH0_CR_RXPERBITRANK3_Lane5_MAX                       (0x0000000F)
+  #define DDRDATA1CH0_CR_RXPERBITRANK3_Lane6_OFF                       (24)
+  #define DDRDATA1CH0_CR_RXPERBITRANK3_Lane6_WID                       ( 4)
+  #define DDRDATA1CH0_CR_RXPERBITRANK3_Lane6_MSK                       (0x0F000000)
+  #define DDRDATA1CH0_CR_RXPERBITRANK3_Lane6_MAX                       (0x0000000F)
+  #define DDRDATA1CH0_CR_RXPERBITRANK3_Lane7_OFF                       (28)
+  #define DDRDATA1CH0_CR_RXPERBITRANK3_Lane7_WID                       ( 4)
+  #define DDRDATA1CH0_CR_RXPERBITRANK3_Lane7_MSK                       (0xF0000000)
+  #define DDRDATA1CH0_CR_RXPERBITRANK3_Lane7_MAX                       (0x0000000F)
+
+#define DDRDATA1CH0_CR_TXTRAINRANK0_REG                              (0x00000220)
+  #define DDRDATA1CH0_CR_TXTRAINRANK0_TxDqDelay_OFF                    ( 0)
+  #define DDRDATA1CH0_CR_TXTRAINRANK0_TxDqDelay_WID                    ( 9)
+  #define DDRDATA1CH0_CR_TXTRAINRANK0_TxDqDelay_MSK                    (0x000001FF)
+  #define DDRDATA1CH0_CR_TXTRAINRANK0_TxDqDelay_MAX                    (0x000001FF)
+  #define DDRDATA1CH0_CR_TXTRAINRANK0_TxDqsDelay_OFF                   ( 9)
+  #define DDRDATA1CH0_CR_TXTRAINRANK0_TxDqsDelay_WID                   ( 9)
+  #define DDRDATA1CH0_CR_TXTRAINRANK0_TxDqsDelay_MSK                   (0x0003FE00)
+  #define DDRDATA1CH0_CR_TXTRAINRANK0_TxDqsDelay_MAX                   (0x000001FF)
+  #define DDRDATA1CH0_CR_TXTRAINRANK0_Spare0_OFF                       (18)
+  #define DDRDATA1CH0_CR_TXTRAINRANK0_Spare0_WID                       ( 2)
+  #define DDRDATA1CH0_CR_TXTRAINRANK0_Spare0_MSK                       (0x000C0000)
+  #define DDRDATA1CH0_CR_TXTRAINRANK0_Spare0_MAX                       (0x00000003)
+  #define DDRDATA1CH0_CR_TXTRAINRANK0_TxEqualization_OFF               (20)
+  #define DDRDATA1CH0_CR_TXTRAINRANK0_TxEqualization_WID               ( 6)
+  #define DDRDATA1CH0_CR_TXTRAINRANK0_TxEqualization_MSK               (0x03F00000)
+  #define DDRDATA1CH0_CR_TXTRAINRANK0_TxEqualization_MAX               (0x0000003F)
+  #define DDRDATA1CH0_CR_TXTRAINRANK0_Spare1_OFF                       (26)
+  #define DDRDATA1CH0_CR_TXTRAINRANK0_Spare1_WID                       ( 6)
+  #define DDRDATA1CH0_CR_TXTRAINRANK0_Spare1_MSK                       (0xFC000000)
+  #define DDRDATA1CH0_CR_TXTRAINRANK0_Spare1_MAX                       (0x0000003F)
+
+#define DDRDATA1CH0_CR_TXTRAINRANK1_REG                              (0x00000224)
+  #define DDRDATA1CH0_CR_TXTRAINRANK1_TxDqDelay_OFF                    ( 0)
+  #define DDRDATA1CH0_CR_TXTRAINRANK1_TxDqDelay_WID                    ( 9)
+  #define DDRDATA1CH0_CR_TXTRAINRANK1_TxDqDelay_MSK                    (0x000001FF)
+  #define DDRDATA1CH0_CR_TXTRAINRANK1_TxDqDelay_MAX                    (0x000001FF)
+  #define DDRDATA1CH0_CR_TXTRAINRANK1_TxDqsDelay_OFF                   ( 9)
+  #define DDRDATA1CH0_CR_TXTRAINRANK1_TxDqsDelay_WID                   ( 9)
+  #define DDRDATA1CH0_CR_TXTRAINRANK1_TxDqsDelay_MSK                   (0x0003FE00)
+  #define DDRDATA1CH0_CR_TXTRAINRANK1_TxDqsDelay_MAX                   (0x000001FF)
+  #define DDRDATA1CH0_CR_TXTRAINRANK1_Spare0_OFF                       (18)
+  #define DDRDATA1CH0_CR_TXTRAINRANK1_Spare0_WID                       ( 2)
+  #define DDRDATA1CH0_CR_TXTRAINRANK1_Spare0_MSK                       (0x000C0000)
+  #define DDRDATA1CH0_CR_TXTRAINRANK1_Spare0_MAX                       (0x00000003)
+  #define DDRDATA1CH0_CR_TXTRAINRANK1_TxEqualization_OFF               (20)
+  #define DDRDATA1CH0_CR_TXTRAINRANK1_TxEqualization_WID               ( 6)
+  #define DDRDATA1CH0_CR_TXTRAINRANK1_TxEqualization_MSK               (0x03F00000)
+  #define DDRDATA1CH0_CR_TXTRAINRANK1_TxEqualization_MAX               (0x0000003F)
+  #define DDRDATA1CH0_CR_TXTRAINRANK1_Spare1_OFF                       (26)
+  #define DDRDATA1CH0_CR_TXTRAINRANK1_Spare1_WID                       ( 6)
+  #define DDRDATA1CH0_CR_TXTRAINRANK1_Spare1_MSK                       (0xFC000000)
+  #define DDRDATA1CH0_CR_TXTRAINRANK1_Spare1_MAX                       (0x0000003F)
+
+#define DDRDATA1CH0_CR_TXTRAINRANK2_REG                              (0x00000228)
+  #define DDRDATA1CH0_CR_TXTRAINRANK2_TxDqDelay_OFF                    ( 0)
+  #define DDRDATA1CH0_CR_TXTRAINRANK2_TxDqDelay_WID                    ( 9)
+  #define DDRDATA1CH0_CR_TXTRAINRANK2_TxDqDelay_MSK                    (0x000001FF)
+  #define DDRDATA1CH0_CR_TXTRAINRANK2_TxDqDelay_MAX                    (0x000001FF)
+  #define DDRDATA1CH0_CR_TXTRAINRANK2_TxDqsDelay_OFF                   ( 9)
+  #define DDRDATA1CH0_CR_TXTRAINRANK2_TxDqsDelay_WID                   ( 9)
+  #define DDRDATA1CH0_CR_TXTRAINRANK2_TxDqsDelay_MSK                   (0x0003FE00)
+  #define DDRDATA1CH0_CR_TXTRAINRANK2_TxDqsDelay_MAX                   (0x000001FF)
+  #define DDRDATA1CH0_CR_TXTRAINRANK2_Spare0_OFF                       (18)
+  #define DDRDATA1CH0_CR_TXTRAINRANK2_Spare0_WID                       ( 2)
+  #define DDRDATA1CH0_CR_TXTRAINRANK2_Spare0_MSK                       (0x000C0000)
+  #define DDRDATA1CH0_CR_TXTRAINRANK2_Spare0_MAX                       (0x00000003)
+  #define DDRDATA1CH0_CR_TXTRAINRANK2_TxEqualization_OFF               (20)
+  #define DDRDATA1CH0_CR_TXTRAINRANK2_TxEqualization_WID               ( 6)
+  #define DDRDATA1CH0_CR_TXTRAINRANK2_TxEqualization_MSK               (0x03F00000)
+  #define DDRDATA1CH0_CR_TXTRAINRANK2_TxEqualization_MAX               (0x0000003F)
+  #define DDRDATA1CH0_CR_TXTRAINRANK2_Spare1_OFF                       (26)
+  #define DDRDATA1CH0_CR_TXTRAINRANK2_Spare1_WID                       ( 6)
+  #define DDRDATA1CH0_CR_TXTRAINRANK2_Spare1_MSK                       (0xFC000000)
+  #define DDRDATA1CH0_CR_TXTRAINRANK2_Spare1_MAX                       (0x0000003F)
+
+#define DDRDATA1CH0_CR_TXTRAINRANK3_REG                              (0x0000022C)
+  #define DDRDATA1CH0_CR_TXTRAINRANK3_TxDqDelay_OFF                    ( 0)
+  #define DDRDATA1CH0_CR_TXTRAINRANK3_TxDqDelay_WID                    ( 9)
+  #define DDRDATA1CH0_CR_TXTRAINRANK3_TxDqDelay_MSK                    (0x000001FF)
+  #define DDRDATA1CH0_CR_TXTRAINRANK3_TxDqDelay_MAX                    (0x000001FF)
+  #define DDRDATA1CH0_CR_TXTRAINRANK3_TxDqsDelay_OFF                   ( 9)
+  #define DDRDATA1CH0_CR_TXTRAINRANK3_TxDqsDelay_WID                   ( 9)
+  #define DDRDATA1CH0_CR_TXTRAINRANK3_TxDqsDelay_MSK                   (0x0003FE00)
+  #define DDRDATA1CH0_CR_TXTRAINRANK3_TxDqsDelay_MAX                   (0x000001FF)
+  #define DDRDATA1CH0_CR_TXTRAINRANK3_Spare0_OFF                       (18)
+  #define DDRDATA1CH0_CR_TXTRAINRANK3_Spare0_WID                       ( 2)
+  #define DDRDATA1CH0_CR_TXTRAINRANK3_Spare0_MSK                       (0x000C0000)
+  #define DDRDATA1CH0_CR_TXTRAINRANK3_Spare0_MAX                       (0x00000003)
+  #define DDRDATA1CH0_CR_TXTRAINRANK3_TxEqualization_OFF               (20)
+  #define DDRDATA1CH0_CR_TXTRAINRANK3_TxEqualization_WID               ( 6)
+  #define DDRDATA1CH0_CR_TXTRAINRANK3_TxEqualization_MSK               (0x03F00000)
+  #define DDRDATA1CH0_CR_TXTRAINRANK3_TxEqualization_MAX               (0x0000003F)
+  #define DDRDATA1CH0_CR_TXTRAINRANK3_Spare1_OFF                       (26)
+  #define DDRDATA1CH0_CR_TXTRAINRANK3_Spare1_WID                       ( 6)
+  #define DDRDATA1CH0_CR_TXTRAINRANK3_Spare1_MSK                       (0xFC000000)
+  #define DDRDATA1CH0_CR_TXTRAINRANK3_Spare1_MAX                       (0x0000003F)
+
+#define DDRDATA1CH0_CR_TXPERBITRANK0_REG                             (0x00000230)
+  #define DDRDATA1CH0_CR_TXPERBITRANK0_Lane0_OFF                       ( 0)
+  #define DDRDATA1CH0_CR_TXPERBITRANK0_Lane0_WID                       ( 4)
+  #define DDRDATA1CH0_CR_TXPERBITRANK0_Lane0_MSK                       (0x0000000F)
+  #define DDRDATA1CH0_CR_TXPERBITRANK0_Lane0_MAX                       (0x0000000F)
+  #define DDRDATA1CH0_CR_TXPERBITRANK0_Lane1_OFF                       ( 4)
+  #define DDRDATA1CH0_CR_TXPERBITRANK0_Lane1_WID                       ( 4)
+  #define DDRDATA1CH0_CR_TXPERBITRANK0_Lane1_MSK                       (0x000000F0)
+  #define DDRDATA1CH0_CR_TXPERBITRANK0_Lane1_MAX                       (0x0000000F)
+  #define DDRDATA1CH0_CR_TXPERBITRANK0_Lane2_OFF                       ( 8)
+  #define DDRDATA1CH0_CR_TXPERBITRANK0_Lane2_WID                       ( 4)
+  #define DDRDATA1CH0_CR_TXPERBITRANK0_Lane2_MSK                       (0x00000F00)
+  #define DDRDATA1CH0_CR_TXPERBITRANK0_Lane2_MAX                       (0x0000000F)
+  #define DDRDATA1CH0_CR_TXPERBITRANK0_Lane3_OFF                       (12)
+  #define DDRDATA1CH0_CR_TXPERBITRANK0_Lane3_WID                       ( 4)
+  #define DDRDATA1CH0_CR_TXPERBITRANK0_Lane3_MSK                       (0x0000F000)
+  #define DDRDATA1CH0_CR_TXPERBITRANK0_Lane3_MAX                       (0x0000000F)
+  #define DDRDATA1CH0_CR_TXPERBITRANK0_Lane4_OFF                       (16)
+  #define DDRDATA1CH0_CR_TXPERBITRANK0_Lane4_WID                       ( 4)
+  #define DDRDATA1CH0_CR_TXPERBITRANK0_Lane4_MSK                       (0x000F0000)
+  #define DDRDATA1CH0_CR_TXPERBITRANK0_Lane4_MAX                       (0x0000000F)
+  #define DDRDATA1CH0_CR_TXPERBITRANK0_Lane5_OFF                       (20)
+  #define DDRDATA1CH0_CR_TXPERBITRANK0_Lane5_WID                       ( 4)
+  #define DDRDATA1CH0_CR_TXPERBITRANK0_Lane5_MSK                       (0x00F00000)
+  #define DDRDATA1CH0_CR_TXPERBITRANK0_Lane5_MAX                       (0x0000000F)
+  #define DDRDATA1CH0_CR_TXPERBITRANK0_Lane6_OFF                       (24)
+  #define DDRDATA1CH0_CR_TXPERBITRANK0_Lane6_WID                       ( 4)
+  #define DDRDATA1CH0_CR_TXPERBITRANK0_Lane6_MSK                       (0x0F000000)
+  #define DDRDATA1CH0_CR_TXPERBITRANK0_Lane6_MAX                       (0x0000000F)
+  #define DDRDATA1CH0_CR_TXPERBITRANK0_Lane7_OFF                       (28)
+  #define DDRDATA1CH0_CR_TXPERBITRANK0_Lane7_WID                       ( 4)
+  #define DDRDATA1CH0_CR_TXPERBITRANK0_Lane7_MSK                       (0xF0000000)
+  #define DDRDATA1CH0_CR_TXPERBITRANK0_Lane7_MAX                       (0x0000000F)
+
+#define DDRDATA1CH0_CR_TXPERBITRANK1_REG                             (0x00000234)
+  #define DDRDATA1CH0_CR_TXPERBITRANK1_Lane0_OFF                       ( 0)
+  #define DDRDATA1CH0_CR_TXPERBITRANK1_Lane0_WID                       ( 4)
+  #define DDRDATA1CH0_CR_TXPERBITRANK1_Lane0_MSK                       (0x0000000F)
+  #define DDRDATA1CH0_CR_TXPERBITRANK1_Lane0_MAX                       (0x0000000F)
+  #define DDRDATA1CH0_CR_TXPERBITRANK1_Lane1_OFF                       ( 4)
+  #define DDRDATA1CH0_CR_TXPERBITRANK1_Lane1_WID                       ( 4)
+  #define DDRDATA1CH0_CR_TXPERBITRANK1_Lane1_MSK                       (0x000000F0)
+  #define DDRDATA1CH0_CR_TXPERBITRANK1_Lane1_MAX                       (0x0000000F)
+  #define DDRDATA1CH0_CR_TXPERBITRANK1_Lane2_OFF                       ( 8)
+  #define DDRDATA1CH0_CR_TXPERBITRANK1_Lane2_WID                       ( 4)
+  #define DDRDATA1CH0_CR_TXPERBITRANK1_Lane2_MSK                       (0x00000F00)
+  #define DDRDATA1CH0_CR_TXPERBITRANK1_Lane2_MAX                       (0x0000000F)
+  #define DDRDATA1CH0_CR_TXPERBITRANK1_Lane3_OFF                       (12)
+  #define DDRDATA1CH0_CR_TXPERBITRANK1_Lane3_WID                       ( 4)
+  #define DDRDATA1CH0_CR_TXPERBITRANK1_Lane3_MSK                       (0x0000F000)
+  #define DDRDATA1CH0_CR_TXPERBITRANK1_Lane3_MAX                       (0x0000000F)
+  #define DDRDATA1CH0_CR_TXPERBITRANK1_Lane4_OFF                       (16)
+  #define DDRDATA1CH0_CR_TXPERBITRANK1_Lane4_WID                       ( 4)
+  #define DDRDATA1CH0_CR_TXPERBITRANK1_Lane4_MSK                       (0x000F0000)
+  #define DDRDATA1CH0_CR_TXPERBITRANK1_Lane4_MAX                       (0x0000000F)
+  #define DDRDATA1CH0_CR_TXPERBITRANK1_Lane5_OFF                       (20)
+  #define DDRDATA1CH0_CR_TXPERBITRANK1_Lane5_WID                       ( 4)
+  #define DDRDATA1CH0_CR_TXPERBITRANK1_Lane5_MSK                       (0x00F00000)
+  #define DDRDATA1CH0_CR_TXPERBITRANK1_Lane5_MAX                       (0x0000000F)
+  #define DDRDATA1CH0_CR_TXPERBITRANK1_Lane6_OFF                       (24)
+  #define DDRDATA1CH0_CR_TXPERBITRANK1_Lane6_WID                       ( 4)
+  #define DDRDATA1CH0_CR_TXPERBITRANK1_Lane6_MSK                       (0x0F000000)
+  #define DDRDATA1CH0_CR_TXPERBITRANK1_Lane6_MAX                       (0x0000000F)
+  #define DDRDATA1CH0_CR_TXPERBITRANK1_Lane7_OFF                       (28)
+  #define DDRDATA1CH0_CR_TXPERBITRANK1_Lane7_WID                       ( 4)
+  #define DDRDATA1CH0_CR_TXPERBITRANK1_Lane7_MSK                       (0xF0000000)
+  #define DDRDATA1CH0_CR_TXPERBITRANK1_Lane7_MAX                       (0x0000000F)
+
+#define DDRDATA1CH0_CR_TXPERBITRANK2_REG                             (0x00000238)
+  #define DDRDATA1CH0_CR_TXPERBITRANK2_Lane0_OFF                       ( 0)
+  #define DDRDATA1CH0_CR_TXPERBITRANK2_Lane0_WID                       ( 4)
+  #define DDRDATA1CH0_CR_TXPERBITRANK2_Lane0_MSK                       (0x0000000F)
+  #define DDRDATA1CH0_CR_TXPERBITRANK2_Lane0_MAX                       (0x0000000F)
+  #define DDRDATA1CH0_CR_TXPERBITRANK2_Lane1_OFF                       ( 4)
+  #define DDRDATA1CH0_CR_TXPERBITRANK2_Lane1_WID                       ( 4)
+  #define DDRDATA1CH0_CR_TXPERBITRANK2_Lane1_MSK                       (0x000000F0)
+  #define DDRDATA1CH0_CR_TXPERBITRANK2_Lane1_MAX                       (0x0000000F)
+  #define DDRDATA1CH0_CR_TXPERBITRANK2_Lane2_OFF                       ( 8)
+  #define DDRDATA1CH0_CR_TXPERBITRANK2_Lane2_WID                       ( 4)
+  #define DDRDATA1CH0_CR_TXPERBITRANK2_Lane2_MSK                       (0x00000F00)
+  #define DDRDATA1CH0_CR_TXPERBITRANK2_Lane2_MAX                       (0x0000000F)
+  #define DDRDATA1CH0_CR_TXPERBITRANK2_Lane3_OFF                       (12)
+  #define DDRDATA1CH0_CR_TXPERBITRANK2_Lane3_WID                       ( 4)
+  #define DDRDATA1CH0_CR_TXPERBITRANK2_Lane3_MSK                       (0x0000F000)
+  #define DDRDATA1CH0_CR_TXPERBITRANK2_Lane3_MAX                       (0x0000000F)
+  #define DDRDATA1CH0_CR_TXPERBITRANK2_Lane4_OFF                       (16)
+  #define DDRDATA1CH0_CR_TXPERBITRANK2_Lane4_WID                       ( 4)
+  #define DDRDATA1CH0_CR_TXPERBITRANK2_Lane4_MSK                       (0x000F0000)
+  #define DDRDATA1CH0_CR_TXPERBITRANK2_Lane4_MAX                       (0x0000000F)
+  #define DDRDATA1CH0_CR_TXPERBITRANK2_Lane5_OFF                       (20)
+  #define DDRDATA1CH0_CR_TXPERBITRANK2_Lane5_WID                       ( 4)
+  #define DDRDATA1CH0_CR_TXPERBITRANK2_Lane5_MSK                       (0x00F00000)
+  #define DDRDATA1CH0_CR_TXPERBITRANK2_Lane5_MAX                       (0x0000000F)
+  #define DDRDATA1CH0_CR_TXPERBITRANK2_Lane6_OFF                       (24)
+  #define DDRDATA1CH0_CR_TXPERBITRANK2_Lane6_WID                       ( 4)
+  #define DDRDATA1CH0_CR_TXPERBITRANK2_Lane6_MSK                       (0x0F000000)
+  #define DDRDATA1CH0_CR_TXPERBITRANK2_Lane6_MAX                       (0x0000000F)
+  #define DDRDATA1CH0_CR_TXPERBITRANK2_Lane7_OFF                       (28)
+  #define DDRDATA1CH0_CR_TXPERBITRANK2_Lane7_WID                       ( 4)
+  #define DDRDATA1CH0_CR_TXPERBITRANK2_Lane7_MSK                       (0xF0000000)
+  #define DDRDATA1CH0_CR_TXPERBITRANK2_Lane7_MAX                       (0x0000000F)
+
+#define DDRDATA1CH0_CR_TXPERBITRANK3_REG                             (0x0000023C)
+  #define DDRDATA1CH0_CR_TXPERBITRANK3_Lane0_OFF                       ( 0)
+  #define DDRDATA1CH0_CR_TXPERBITRANK3_Lane0_WID                       ( 4)
+  #define DDRDATA1CH0_CR_TXPERBITRANK3_Lane0_MSK                       (0x0000000F)
+  #define DDRDATA1CH0_CR_TXPERBITRANK3_Lane0_MAX                       (0x0000000F)
+  #define DDRDATA1CH0_CR_TXPERBITRANK3_Lane1_OFF                       ( 4)
+  #define DDRDATA1CH0_CR_TXPERBITRANK3_Lane1_WID                       ( 4)
+  #define DDRDATA1CH0_CR_TXPERBITRANK3_Lane1_MSK                       (0x000000F0)
+  #define DDRDATA1CH0_CR_TXPERBITRANK3_Lane1_MAX                       (0x0000000F)
+  #define DDRDATA1CH0_CR_TXPERBITRANK3_Lane2_OFF                       ( 8)
+  #define DDRDATA1CH0_CR_TXPERBITRANK3_Lane2_WID                       ( 4)
+  #define DDRDATA1CH0_CR_TXPERBITRANK3_Lane2_MSK                       (0x00000F00)
+  #define DDRDATA1CH0_CR_TXPERBITRANK3_Lane2_MAX                       (0x0000000F)
+  #define DDRDATA1CH0_CR_TXPERBITRANK3_Lane3_OFF                       (12)
+  #define DDRDATA1CH0_CR_TXPERBITRANK3_Lane3_WID                       ( 4)
+  #define DDRDATA1CH0_CR_TXPERBITRANK3_Lane3_MSK                       (0x0000F000)
+  #define DDRDATA1CH0_CR_TXPERBITRANK3_Lane3_MAX                       (0x0000000F)
+  #define DDRDATA1CH0_CR_TXPERBITRANK3_Lane4_OFF                       (16)
+  #define DDRDATA1CH0_CR_TXPERBITRANK3_Lane4_WID                       ( 4)
+  #define DDRDATA1CH0_CR_TXPERBITRANK3_Lane4_MSK                       (0x000F0000)
+  #define DDRDATA1CH0_CR_TXPERBITRANK3_Lane4_MAX                       (0x0000000F)
+  #define DDRDATA1CH0_CR_TXPERBITRANK3_Lane5_OFF                       (20)
+  #define DDRDATA1CH0_CR_TXPERBITRANK3_Lane5_WID                       ( 4)
+  #define DDRDATA1CH0_CR_TXPERBITRANK3_Lane5_MSK                       (0x00F00000)
+  #define DDRDATA1CH0_CR_TXPERBITRANK3_Lane5_MAX                       (0x0000000F)
+  #define DDRDATA1CH0_CR_TXPERBITRANK3_Lane6_OFF                       (24)
+  #define DDRDATA1CH0_CR_TXPERBITRANK3_Lane6_WID                       ( 4)
+  #define DDRDATA1CH0_CR_TXPERBITRANK3_Lane6_MSK                       (0x0F000000)
+  #define DDRDATA1CH0_CR_TXPERBITRANK3_Lane6_MAX                       (0x0000000F)
+  #define DDRDATA1CH0_CR_TXPERBITRANK3_Lane7_OFF                       (28)
+  #define DDRDATA1CH0_CR_TXPERBITRANK3_Lane7_WID                       ( 4)
+  #define DDRDATA1CH0_CR_TXPERBITRANK3_Lane7_MSK                       (0xF0000000)
+  #define DDRDATA1CH0_CR_TXPERBITRANK3_Lane7_MAX                       (0x0000000F)
+
+#define DDRDATA1CH0_CR_RCOMPDATA0_REG                                (0x00000240)
+  #define DDRDATA1CH0_CR_RCOMPDATA0_RcompDrvUp_OFF                     ( 0)
+  #define DDRDATA1CH0_CR_RCOMPDATA0_RcompDrvUp_WID                     ( 6)
+  #define DDRDATA1CH0_CR_RCOMPDATA0_RcompDrvUp_MSK                     (0x0000003F)
+  #define DDRDATA1CH0_CR_RCOMPDATA0_RcompDrvUp_MAX                     (0x0000003F)
+  #define DDRDATA1CH0_CR_RCOMPDATA0_Spare0_OFF                         ( 6)
+  #define DDRDATA1CH0_CR_RCOMPDATA0_Spare0_WID                         ( 3)
+  #define DDRDATA1CH0_CR_RCOMPDATA0_Spare0_MSK                         (0x000001C0)
+  #define DDRDATA1CH0_CR_RCOMPDATA0_Spare0_MAX                         (0x00000007)
+  #define DDRDATA1CH0_CR_RCOMPDATA0_RcompDrvDown_OFF                   ( 9)
+  #define DDRDATA1CH0_CR_RCOMPDATA0_RcompDrvDown_WID                   ( 6)
+  #define DDRDATA1CH0_CR_RCOMPDATA0_RcompDrvDown_MSK                   (0x00007E00)
+  #define DDRDATA1CH0_CR_RCOMPDATA0_RcompDrvDown_MAX                   (0x0000003F)
+  #define DDRDATA1CH0_CR_RCOMPDATA0_VTComp_OFF                         (15)
+  #define DDRDATA1CH0_CR_RCOMPDATA0_VTComp_WID                         ( 5)
+  #define DDRDATA1CH0_CR_RCOMPDATA0_VTComp_MSK                         (0x000F8000)
+  #define DDRDATA1CH0_CR_RCOMPDATA0_VTComp_MAX                         (0x0000001F)
+  #define DDRDATA1CH0_CR_RCOMPDATA0_TcoComp_OFF                        (20)
+  #define DDRDATA1CH0_CR_RCOMPDATA0_TcoComp_WID                        ( 6)
+  #define DDRDATA1CH0_CR_RCOMPDATA0_TcoComp_MSK                        (0x03F00000)
+  #define DDRDATA1CH0_CR_RCOMPDATA0_TcoComp_MAX                        (0x0000003F)
+  #define DDRDATA1CH0_CR_RCOMPDATA0_SlewRateComp_OFF                   (26)
+  #define DDRDATA1CH0_CR_RCOMPDATA0_SlewRateComp_WID                   ( 5)
+  #define DDRDATA1CH0_CR_RCOMPDATA0_SlewRateComp_MSK                   (0x7C000000)
+  #define DDRDATA1CH0_CR_RCOMPDATA0_SlewRateComp_MAX                   (0x0000001F)
+  #define DDRDATA1CH0_CR_RCOMPDATA0_Spare2_OFF                         (31)
+  #define DDRDATA1CH0_CR_RCOMPDATA0_Spare2_WID                         ( 1)
+  #define DDRDATA1CH0_CR_RCOMPDATA0_Spare2_MSK                         (0x80000000)
+  #define DDRDATA1CH0_CR_RCOMPDATA0_Spare2_MAX                         (0x00000001)
+
+#define DDRDATA1CH0_CR_RCOMPDATA1_REG                                (0x00000244)
+  #define DDRDATA1CH0_CR_RCOMPDATA1_RcompOdtUp_OFF                     ( 0)
+  #define DDRDATA1CH0_CR_RCOMPDATA1_RcompOdtUp_WID                     ( 6)
+  #define DDRDATA1CH0_CR_RCOMPDATA1_RcompOdtUp_MSK                     (0x0000003F)
+  #define DDRDATA1CH0_CR_RCOMPDATA1_RcompOdtUp_MAX                     (0x0000003F)
+  #define DDRDATA1CH0_CR_RCOMPDATA1_Spare0_OFF                         ( 6)
+  #define DDRDATA1CH0_CR_RCOMPDATA1_Spare0_WID                         ( 3)
+  #define DDRDATA1CH0_CR_RCOMPDATA1_Spare0_MSK                         (0x000001C0)
+  #define DDRDATA1CH0_CR_RCOMPDATA1_Spare0_MAX                         (0x00000007)
+  #define DDRDATA1CH0_CR_RCOMPDATA1_RcompOdtDown_OFF                   ( 9)
+  #define DDRDATA1CH0_CR_RCOMPDATA1_RcompOdtDown_WID                   ( 6)
+  #define DDRDATA1CH0_CR_RCOMPDATA1_RcompOdtDown_MSK                   (0x00007E00)
+  #define DDRDATA1CH0_CR_RCOMPDATA1_RcompOdtDown_MAX                   (0x0000003F)
+  #define DDRDATA1CH0_CR_RCOMPDATA1_Spare1_OFF                         (15)
+  #define DDRDATA1CH0_CR_RCOMPDATA1_Spare1_WID                         ( 1)
+  #define DDRDATA1CH0_CR_RCOMPDATA1_Spare1_MSK                         (0x00008000)
+  #define DDRDATA1CH0_CR_RCOMPDATA1_Spare1_MAX                         (0x00000001)
+  #define DDRDATA1CH0_CR_RCOMPDATA1_PanicDrvDn_OFF                     (16)
+  #define DDRDATA1CH0_CR_RCOMPDATA1_PanicDrvDn_WID                     ( 6)
+  #define DDRDATA1CH0_CR_RCOMPDATA1_PanicDrvDn_MSK                     (0x003F0000)
+  #define DDRDATA1CH0_CR_RCOMPDATA1_PanicDrvDn_MAX                     (0x0000003F)
+  #define DDRDATA1CH0_CR_RCOMPDATA1_PanicDrvUp_OFF                     (22)
+  #define DDRDATA1CH0_CR_RCOMPDATA1_PanicDrvUp_WID                     ( 6)
+  #define DDRDATA1CH0_CR_RCOMPDATA1_PanicDrvUp_MSK                     (0x0FC00000)
+  #define DDRDATA1CH0_CR_RCOMPDATA1_PanicDrvUp_MAX                     (0x0000003F)
+  #define DDRDATA1CH0_CR_RCOMPDATA1_LevelShifterComp_OFF               (28)
+  #define DDRDATA1CH0_CR_RCOMPDATA1_LevelShifterComp_WID               ( 3)
+  #define DDRDATA1CH0_CR_RCOMPDATA1_LevelShifterComp_MSK               (0x70000000)
+  #define DDRDATA1CH0_CR_RCOMPDATA1_LevelShifterComp_MAX               (0x00000007)
+  #define DDRDATA1CH0_CR_RCOMPDATA1_Spare2_OFF                         (31)
+  #define DDRDATA1CH0_CR_RCOMPDATA1_Spare2_WID                         ( 1)
+  #define DDRDATA1CH0_CR_RCOMPDATA1_Spare2_MSK                         (0x80000000)
+  #define DDRDATA1CH0_CR_RCOMPDATA1_Spare2_MAX                         (0x00000001)
+
+#define DDRDATA1CH0_CR_TXXTALK_REG                                   (0x00000248)
+  #define DDRDATA1CH0_CR_TXXTALK_Lane0_OFF                             ( 0)
+  #define DDRDATA1CH0_CR_TXXTALK_Lane0_WID                             ( 4)
+  #define DDRDATA1CH0_CR_TXXTALK_Lane0_MSK                             (0x0000000F)
+  #define DDRDATA1CH0_CR_TXXTALK_Lane0_MAX                             (0x0000000F)
+  #define DDRDATA1CH0_CR_TXXTALK_Lane1_OFF                             ( 4)
+  #define DDRDATA1CH0_CR_TXXTALK_Lane1_WID                             ( 4)
+  #define DDRDATA1CH0_CR_TXXTALK_Lane1_MSK                             (0x000000F0)
+  #define DDRDATA1CH0_CR_TXXTALK_Lane1_MAX                             (0x0000000F)
+  #define DDRDATA1CH0_CR_TXXTALK_Lane2_OFF                             ( 8)
+  #define DDRDATA1CH0_CR_TXXTALK_Lane2_WID                             ( 4)
+  #define DDRDATA1CH0_CR_TXXTALK_Lane2_MSK                             (0x00000F00)
+  #define DDRDATA1CH0_CR_TXXTALK_Lane2_MAX                             (0x0000000F)
+  #define DDRDATA1CH0_CR_TXXTALK_Lane3_OFF                             (12)
+  #define DDRDATA1CH0_CR_TXXTALK_Lane3_WID                             ( 4)
+  #define DDRDATA1CH0_CR_TXXTALK_Lane3_MSK                             (0x0000F000)
+  #define DDRDATA1CH0_CR_TXXTALK_Lane3_MAX                             (0x0000000F)
+  #define DDRDATA1CH0_CR_TXXTALK_Lane4_OFF                             (16)
+  #define DDRDATA1CH0_CR_TXXTALK_Lane4_WID                             ( 4)
+  #define DDRDATA1CH0_CR_TXXTALK_Lane4_MSK                             (0x000F0000)
+  #define DDRDATA1CH0_CR_TXXTALK_Lane4_MAX                             (0x0000000F)
+  #define DDRDATA1CH0_CR_TXXTALK_Lane5_OFF                             (20)
+  #define DDRDATA1CH0_CR_TXXTALK_Lane5_WID                             ( 4)
+  #define DDRDATA1CH0_CR_TXXTALK_Lane5_MSK                             (0x00F00000)
+  #define DDRDATA1CH0_CR_TXXTALK_Lane5_MAX                             (0x0000000F)
+  #define DDRDATA1CH0_CR_TXXTALK_Lane6_OFF                             (24)
+  #define DDRDATA1CH0_CR_TXXTALK_Lane6_WID                             ( 4)
+  #define DDRDATA1CH0_CR_TXXTALK_Lane6_MSK                             (0x0F000000)
+  #define DDRDATA1CH0_CR_TXXTALK_Lane6_MAX                             (0x0000000F)
+  #define DDRDATA1CH0_CR_TXXTALK_Lane7_OFF                             (28)
+  #define DDRDATA1CH0_CR_TXXTALK_Lane7_WID                             ( 4)
+  #define DDRDATA1CH0_CR_TXXTALK_Lane7_MSK                             (0xF0000000)
+  #define DDRDATA1CH0_CR_TXXTALK_Lane7_MAX                             (0x0000000F)
+
+#define DDRDATA1CH0_CR_RXOFFSETVDQ_REG                               (0x0000024C)
+  #define DDRDATA1CH0_CR_RXOFFSETVDQ_Lane0_OFF                         ( 0)
+  #define DDRDATA1CH0_CR_RXOFFSETVDQ_Lane0_WID                         ( 4)
+  #define DDRDATA1CH0_CR_RXOFFSETVDQ_Lane0_MSK                         (0x0000000F)
+  #define DDRDATA1CH0_CR_RXOFFSETVDQ_Lane0_MAX                         (0x0000000F)
+  #define DDRDATA1CH0_CR_RXOFFSETVDQ_Lane1_OFF                         ( 4)
+  #define DDRDATA1CH0_CR_RXOFFSETVDQ_Lane1_WID                         ( 4)
+  #define DDRDATA1CH0_CR_RXOFFSETVDQ_Lane1_MSK                         (0x000000F0)
+  #define DDRDATA1CH0_CR_RXOFFSETVDQ_Lane1_MAX                         (0x0000000F)
+  #define DDRDATA1CH0_CR_RXOFFSETVDQ_Lane2_OFF                         ( 8)
+  #define DDRDATA1CH0_CR_RXOFFSETVDQ_Lane2_WID                         ( 4)
+  #define DDRDATA1CH0_CR_RXOFFSETVDQ_Lane2_MSK                         (0x00000F00)
+  #define DDRDATA1CH0_CR_RXOFFSETVDQ_Lane2_MAX                         (0x0000000F)
+  #define DDRDATA1CH0_CR_RXOFFSETVDQ_Lane3_OFF                         (12)
+  #define DDRDATA1CH0_CR_RXOFFSETVDQ_Lane3_WID                         ( 4)
+  #define DDRDATA1CH0_CR_RXOFFSETVDQ_Lane3_MSK                         (0x0000F000)
+  #define DDRDATA1CH0_CR_RXOFFSETVDQ_Lane3_MAX                         (0x0000000F)
+  #define DDRDATA1CH0_CR_RXOFFSETVDQ_Lane4_OFF                         (16)
+  #define DDRDATA1CH0_CR_RXOFFSETVDQ_Lane4_WID                         ( 4)
+  #define DDRDATA1CH0_CR_RXOFFSETVDQ_Lane4_MSK                         (0x000F0000)
+  #define DDRDATA1CH0_CR_RXOFFSETVDQ_Lane4_MAX                         (0x0000000F)
+  #define DDRDATA1CH0_CR_RXOFFSETVDQ_Lane5_OFF                         (20)
+  #define DDRDATA1CH0_CR_RXOFFSETVDQ_Lane5_WID                         ( 4)
+  #define DDRDATA1CH0_CR_RXOFFSETVDQ_Lane5_MSK                         (0x00F00000)
+  #define DDRDATA1CH0_CR_RXOFFSETVDQ_Lane5_MAX                         (0x0000000F)
+  #define DDRDATA1CH0_CR_RXOFFSETVDQ_Lane6_OFF                         (24)
+  #define DDRDATA1CH0_CR_RXOFFSETVDQ_Lane6_WID                         ( 4)
+  #define DDRDATA1CH0_CR_RXOFFSETVDQ_Lane6_MSK                         (0x0F000000)
+  #define DDRDATA1CH0_CR_RXOFFSETVDQ_Lane6_MAX                         (0x0000000F)
+  #define DDRDATA1CH0_CR_RXOFFSETVDQ_Lane7_OFF                         (28)
+  #define DDRDATA1CH0_CR_RXOFFSETVDQ_Lane7_WID                         ( 4)
+  #define DDRDATA1CH0_CR_RXOFFSETVDQ_Lane7_MSK                         (0xF0000000)
+  #define DDRDATA1CH0_CR_RXOFFSETVDQ_Lane7_MAX                         (0x0000000F)
+
+#define DDRDATA1CH0_CR_DDRDATARESERVED_REG                           (0x00000250)
+  #define DDRDATA1CH0_CR_DDRDATARESERVED_Spare_OFF                     ( 0)
+  #define DDRDATA1CH0_CR_DDRDATARESERVED_Spare_WID                     (32)
+  #define DDRDATA1CH0_CR_DDRDATARESERVED_Spare_MSK                     (0xFFFFFFFF)
+  #define DDRDATA1CH0_CR_DDRDATARESERVED_Spare_MAX                     (0xFFFFFFFF)
+
+#define DDRDATA1CH0_CR_DATATRAINFEEDBACK_REG                         (0x00000254)
+  #define DDRDATA1CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_OFF       ( 0)
+  #define DDRDATA1CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_WID       ( 9)
+  #define DDRDATA1CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_MSK       (0x000001FF)
+  #define DDRDATA1CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_MAX       (0x000001FF)
+  #define DDRDATA1CH0_CR_DATATRAINFEEDBACK_Spare_OFF                   ( 9)
+  #define DDRDATA1CH0_CR_DATATRAINFEEDBACK_Spare_WID                   (23)
+  #define DDRDATA1CH0_CR_DATATRAINFEEDBACK_Spare_MSK                   (0xFFFFFE00)
+  #define DDRDATA1CH0_CR_DATATRAINFEEDBACK_Spare_MAX                   (0x007FFFFF)
+
+#define DDRDATA1CH0_CR_DLLPITESTANDADC_REG                           (0x00000258)
+  #define DDRDATA1CH0_CR_DLLPITESTANDADC_RunTest_OFF                   ( 0)
+  #define DDRDATA1CH0_CR_DLLPITESTANDADC_RunTest_WID                   ( 1)
+  #define DDRDATA1CH0_CR_DLLPITESTANDADC_RunTest_MSK                   (0x00000001)
+  #define DDRDATA1CH0_CR_DLLPITESTANDADC_RunTest_MAX                   (0x00000001)
+  #define DDRDATA1CH0_CR_DLLPITESTANDADC_RunTest_DEF                   (0x00000000)
+  #define DDRDATA1CH0_CR_DLLPITESTANDADC_Load_OFF                      ( 1)
+  #define DDRDATA1CH0_CR_DLLPITESTANDADC_Load_WID                      ( 1)
+  #define DDRDATA1CH0_CR_DLLPITESTANDADC_Load_MSK                      (0x00000002)
+  #define DDRDATA1CH0_CR_DLLPITESTANDADC_Load_MAX                      (0x00000001)
+  #define DDRDATA1CH0_CR_DLLPITESTANDADC_Load_DEF                      (0x00000000)
+  #define DDRDATA1CH0_CR_DLLPITESTANDADC_ModeHVM_OFF                   ( 2)
+  #define DDRDATA1CH0_CR_DLLPITESTANDADC_ModeHVM_WID                   ( 1)
+  #define DDRDATA1CH0_CR_DLLPITESTANDADC_ModeHVM_MSK                   (0x00000004)
+  #define DDRDATA1CH0_CR_DLLPITESTANDADC_ModeHVM_MAX                   (0x00000001)
+  #define DDRDATA1CH0_CR_DLLPITESTANDADC_ModeHVM_DEF                   (0x00000000)
+  #define DDRDATA1CH0_CR_DLLPITESTANDADC_ModeDV_OFF                    ( 3)
+  #define DDRDATA1CH0_CR_DLLPITESTANDADC_ModeDV_WID                    ( 1)
+  #define DDRDATA1CH0_CR_DLLPITESTANDADC_ModeDV_MSK                    (0x00000008)
+  #define DDRDATA1CH0_CR_DLLPITESTANDADC_ModeDV_MAX                    (0x00000001)
+  #define DDRDATA1CH0_CR_DLLPITESTANDADC_ModeDV_DEF                    (0x00000000)
+  #define DDRDATA1CH0_CR_DLLPITESTANDADC_ModeADC_OFF                   ( 4)
+  #define DDRDATA1CH0_CR_DLLPITESTANDADC_ModeADC_WID                   ( 1)
+  #define DDRDATA1CH0_CR_DLLPITESTANDADC_ModeADC_MSK                   (0x00000010)
+  #define DDRDATA1CH0_CR_DLLPITESTANDADC_ModeADC_MAX                   (0x00000001)
+  #define DDRDATA1CH0_CR_DLLPITESTANDADC_ModeADC_DEF                   (0x00000000)
+  #define DDRDATA1CH0_CR_DLLPITESTANDADC_LoadCount_OFF                 ( 5)
+  #define DDRDATA1CH0_CR_DLLPITESTANDADC_LoadCount_WID                 (10)
+  #define DDRDATA1CH0_CR_DLLPITESTANDADC_LoadCount_MSK                 (0x00007FE0)
+  #define DDRDATA1CH0_CR_DLLPITESTANDADC_LoadCount_MAX                 (0x000003FF)
+  #define DDRDATA1CH0_CR_DLLPITESTANDADC_CountStatus_OFF               (15)
+  #define DDRDATA1CH0_CR_DLLPITESTANDADC_CountStatus_WID               (10)
+  #define DDRDATA1CH0_CR_DLLPITESTANDADC_CountStatus_MSK               (0x01FF8000)
+  #define DDRDATA1CH0_CR_DLLPITESTANDADC_CountStatus_MAX               (0x000003FF)
+  #define DDRDATA1CH0_CR_DLLPITESTANDADC_CountStatus_DEF               (0x00000000)
+  #define DDRDATA1CH0_CR_DLLPITESTANDADC_Spare_OFF                     (25)
+  #define DDRDATA1CH0_CR_DLLPITESTANDADC_Spare_WID                     ( 7)
+  #define DDRDATA1CH0_CR_DLLPITESTANDADC_Spare_MSK                     (0xFE000000)
+  #define DDRDATA1CH0_CR_DLLPITESTANDADC_Spare_MAX                     (0x0000007F)
+
+#define DDRDATA1CH0_CR_DDRCRDATAOFFSETCOMP_REG                       (0x0000025C)
+  #define DDRDATA1CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_OFF     ( 0)
+  #define DDRDATA1CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_WID     ( 6)
+  #define DDRDATA1CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MSK     (0x0000003F)
+  #define DDRDATA1CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MAX     (0x0000003F)
+  #define DDRDATA1CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_DEF     (0x00000000)
+  #define DDRDATA1CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_OFF   ( 6)
+  #define DDRDATA1CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_WID   ( 6)
+  #define DDRDATA1CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MSK   (0x00000FC0)
+  #define DDRDATA1CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MAX   (0x0000003F)
+  #define DDRDATA1CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_DEF   (0x00000000)
+  #define DDRDATA1CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_OFF     (12)
+  #define DDRDATA1CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_WID     ( 5)
+  #define DDRDATA1CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MSK     (0x0001F000)
+  #define DDRDATA1CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MAX     (0x0000001F)
+  #define DDRDATA1CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_DEF     (0x00000000)
+  #define DDRDATA1CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_OFF   (17)
+  #define DDRDATA1CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_WID   ( 5)
+  #define DDRDATA1CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MSK   (0x003E0000)
+  #define DDRDATA1CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MAX   (0x0000001F)
+  #define DDRDATA1CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_DEF   (0x00000000)
+  #define DDRDATA1CH0_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_OFF       (22)
+  #define DDRDATA1CH0_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_WID       ( 5)
+  #define DDRDATA1CH0_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_MSK       (0x07C00000)
+  #define DDRDATA1CH0_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_MAX       (0x0000001F)
+  #define DDRDATA1CH0_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_DEF       (0x00000000)
+  #define DDRDATA1CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_OFF  (27)
+  #define DDRDATA1CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_WID  ( 5)
+  #define DDRDATA1CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MSK  (0xF8000000)
+  #define DDRDATA1CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MAX  (0x0000001F)
+  #define DDRDATA1CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_DEF  (0x00000000)
+
+#define DDRDATA1CH0_CR_DDRCRDATACONTROL1_REG                         (0x00000260)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_RefPi_OFF                   ( 0)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_RefPi_WID                   ( 4)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_RefPi_MSK                   (0x0000000F)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_RefPi_MAX                   (0x0000000F)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_RefPi_DEF                   (0x00000000)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_DllMask_OFF                 ( 4)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_DllMask_WID                 ( 2)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_DllMask_MSK                 (0x00000030)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_DllMask_MAX                 (0x00000003)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_DllMask_DEF                 (0x00000000)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_DllWeakLock_OFF             ( 6)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_DllWeakLock_WID             ( 1)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_DllWeakLock_MSK             (0x00000040)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_DllWeakLock_MAX             (0x00000001)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_DllWeakLock_DEF             (0x00000000)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_OFF      ( 7)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_WID      ( 3)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MSK      (0x00000380)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MAX      (0x00000007)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_DEF      (0x00000000)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_OFF               (10)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_WID               ( 3)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_MSK               (0x00001C00)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_MAX               (0x00000007)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_DEF               (0x00000000)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_OdtDelay_OFF                (13)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_OdtDelay_WID                ( 4)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_OdtDelay_MSK                (0x0001E000)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_OdtDelay_MAX                (0x0000000F)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_OdtDelay_DEF                (0x00000000)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_OdtDuration_OFF             (17)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_OdtDuration_WID             ( 3)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_OdtDuration_MSK             (0x000E0000)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_OdtDuration_MAX             (0x00000007)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_OdtDuration_DEF             (0x00000000)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_OFF           (20)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_WID           ( 4)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_MSK           (0x00F00000)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_MAX           (0x0000000F)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_DEF           (0x00000000)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_OFF        (24)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_WID        ( 3)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_MSK        (0x07000000)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_MAX        (0x00000007)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_DEF        (0x00000000)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_BurstEndODTDelay_OFF        (27)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_BurstEndODTDelay_WID        ( 3)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_BurstEndODTDelay_MSK        (0x38000000)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_BurstEndODTDelay_MAX        (0x00000007)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_BurstEndODTDelay_DEF        (0x00000000)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_OFF          (30)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_WID          ( 1)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_MSK          (0x40000000)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_MAX          (0x00000001)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_DEF          (0x00000000)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_Rsvd1_OFF                   (31)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_Rsvd1_WID                   ( 1)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_Rsvd1_MSK                   (0x80000000)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_Rsvd1_MAX                   (0x00000001)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_Rsvd1_DEF                   (0x00000000)
+
+#define DDRDATA1CH0_CR_DDRCRDATACONTROL2_REG                         (0x00000264)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_OFF            ( 0)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_WID            ( 5)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_MSK            (0x0000001F)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_MAX            (0x0000001F)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_DEF            (0x00000000)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_OFF             ( 5)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_WID             ( 1)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_MSK             (0x00000020)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_MAX             (0x00000001)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_DEF             (0x00000000)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_ForceRxOn_OFF               ( 6)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_ForceRxOn_WID               ( 1)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_ForceRxOn_MSK               (0x00000040)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_ForceRxOn_MAX               (0x00000001)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_ForceRxOn_DEF               (0x00000000)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_LeakerComp_OFF              ( 7)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_LeakerComp_WID              ( 2)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_LeakerComp_MSK              (0x00000180)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_LeakerComp_MAX              (0x00000003)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_LeakerComp_DEF              (0x00000000)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_OFF          ( 9)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_WID          ( 4)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_MSK          (0x00001E00)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_MAX          (0x0000000F)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_DEF          (0x00000008)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_OFF             (13)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_WID             ( 5)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_MSK             (0x0003E000)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_MAX             (0x0000001F)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_DEF             (0x00000011)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_OFF             (18)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_WID             ( 1)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_MSK             (0x00040000)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_MAX             (0x00000001)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_DEF             (0x00000000)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_Spare_OFF                   (19)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_Spare_WID                   (13)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_Spare_MSK                   (0xFFF80000)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_Spare_MAX                   (0x00001FFF)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_Spare_DEF                   (0x00000000)
+
+#define DDRDATA1CH0_CR_DDRCRVSSHIORVREFCONTROL_REG                   (0x0000026C)
+  #define DDRDATA1CH0_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_OFF    ( 0)
+  #define DDRDATA1CH0_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_WID    (24)
+  #define DDRDATA1CH0_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_MSK    (0x00FFFFFF)
+  #define DDRDATA1CH0_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_MAX    (0x00FFFFFF)
+  #define DDRDATA1CH0_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_DEF    (0x00000000)
+  #define DDRDATA1CH0_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_OFF        (24)
+  #define DDRDATA1CH0_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_WID        ( 8)
+  #define DDRDATA1CH0_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_MSK        (0xFF000000)
+  #define DDRDATA1CH0_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_MAX        (0x000000FF)
+  #define DDRDATA1CH0_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_DEF        (0x00000000)
+
+#define DDRDATA1CH0_CR_DDRCRDATAOFFSETTRAIN_REG                      (0x00000270)
+  #define DDRDATA1CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_OFF          ( 0)
+  #define DDRDATA1CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_WID          ( 6)
+  #define DDRDATA1CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MSK          (0x0000003F)
+  #define DDRDATA1CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MAX          (0x0000003F)
+  #define DDRDATA1CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_DEF          (0x00000000)
+  #define DDRDATA1CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_OFF          ( 6)
+  #define DDRDATA1CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_WID          ( 6)
+  #define DDRDATA1CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MSK          (0x00000FC0)
+  #define DDRDATA1CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MAX          (0x0000003F)
+  #define DDRDATA1CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_DEF          (0x00000000)
+  #define DDRDATA1CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_OFF           (12)
+  #define DDRDATA1CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_WID           ( 6)
+  #define DDRDATA1CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MSK           (0x0003F000)
+  #define DDRDATA1CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MAX           (0x0000003F)
+  #define DDRDATA1CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_DEF           (0x00000000)
+  #define DDRDATA1CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_OFF          (18)
+  #define DDRDATA1CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_WID          ( 6)
+  #define DDRDATA1CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MSK          (0x00FC0000)
+  #define DDRDATA1CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MAX          (0x0000003F)
+  #define DDRDATA1CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_DEF          (0x00000000)
+  #define DDRDATA1CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_OFF           (24)
+  #define DDRDATA1CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_WID           ( 7)
+  #define DDRDATA1CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MSK           (0x7F000000)
+  #define DDRDATA1CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MAX           (0x0000007F)
+  #define DDRDATA1CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_DEF           (0x00000000)
+  #define DDRDATA1CH0_CR_DDRCRDATAOFFSETTRAIN_Spare_OFF                (31)
+  #define DDRDATA1CH0_CR_DDRCRDATAOFFSETTRAIN_Spare_WID                ( 1)
+  #define DDRDATA1CH0_CR_DDRCRDATAOFFSETTRAIN_Spare_MSK                (0x80000000)
+  #define DDRDATA1CH0_CR_DDRCRDATAOFFSETTRAIN_Spare_MAX                (0x00000001)
+  #define DDRDATA1CH0_CR_DDRCRDATAOFFSETTRAIN_Spare_DEF                (0x00000000)
+
+#define DDRDATA1CH0_CR_DDRCRDATACONTROL0_REG                         (0x00000274)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_OFF          ( 0)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_WID          ( 1)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_MSK          (0x00000001)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_MAX          (0x00000001)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_DEF          (0x00000000)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_OFF          ( 1)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_WID          ( 1)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_MSK          (0x00000002)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_MAX          (0x00000001)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_DEF          (0x00000000)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_OFF          ( 2)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_WID          ( 1)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_MSK          (0x00000004)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_MAX          (0x00000001)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_DEF          (0x00000000)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_OFF    ( 3)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_WID    ( 1)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MSK    (0x00000008)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MAX    (0x00000001)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_DEF    (0x00000000)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_TxOn_OFF                    ( 4)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_TxOn_WID                    ( 1)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_TxOn_MSK                    (0x00000010)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_TxOn_MAX                    (0x00000001)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_TxOn_DEF                    (0x00000000)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RfOn_OFF                    ( 5)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RfOn_WID                    ( 1)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RfOn_MSK                    (0x00000020)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RfOn_MAX                    (0x00000001)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RfOn_DEF                    (0x00000000)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RxPiOn_OFF                  ( 6)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RxPiOn_WID                  ( 1)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RxPiOn_MSK                  (0x00000040)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RxPiOn_MAX                  (0x00000001)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RxPiOn_DEF                  (0x00000000)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_TxPiOn_OFF                  ( 7)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_TxPiOn_WID                  ( 1)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_TxPiOn_MSK                  (0x00000080)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_TxPiOn_MAX                  (0x00000001)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_TxPiOn_DEF                  (0x00000000)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_OFF        ( 8)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_WID        ( 1)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_MSK        (0x00000100)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_MAX        (0x00000001)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_DEF        (0x00000000)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_OFF        ( 9)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_WID        ( 1)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MSK        (0x00000200)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MAX        (0x00000001)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_DEF        (0x00000000)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_TxDisable_OFF               (10)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_TxDisable_WID               ( 1)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_TxDisable_MSK               (0x00000400)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_TxDisable_MAX               (0x00000001)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_TxDisable_DEF               (0x00000000)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RxDisable_OFF               (11)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RxDisable_WID               ( 1)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RxDisable_MSK               (0x00000800)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RxDisable_MAX               (0x00000001)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RxDisable_DEF               (0x00000000)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_TxLong_OFF                  (12)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_TxLong_WID                  ( 1)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_TxLong_MSK                  (0x00001000)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_TxLong_MAX                  (0x00000001)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_TxLong_DEF                  (0x00000000)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_OFF               (13)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_WID               ( 2)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_MSK               (0x00006000)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_MAX               (0x00000003)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_DEF               (0x00000000)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RxReadPointer_OFF           (15)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RxReadPointer_WID           ( 3)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RxReadPointer_MSK           (0x00038000)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RxReadPointer_MAX           (0x00000007)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RxReadPointer_DEF           (0x00000000)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_DriverSegmentEnable_OFF     (18)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_DriverSegmentEnable_WID     ( 1)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_DriverSegmentEnable_MSK     (0x00040000)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_DriverSegmentEnable_MAX     (0x00000001)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_DriverSegmentEnable_DEF     (0x00000000)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_DataVccddqHi_OFF            (19)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_DataVccddqHi_WID            ( 1)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_DataVccddqHi_MSK            (0x00080000)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_DataVccddqHi_MAX            (0x00000001)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_DataVccddqHi_DEF            (0x00000000)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_ReadRFRd_OFF                (20)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_ReadRFRd_WID                ( 1)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_ReadRFRd_MSK                (0x00100000)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_ReadRFRd_MAX                (0x00000001)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_ReadRFRd_DEF                (0x00000000)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_ReadRFWr_OFF                (21)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_ReadRFWr_WID                ( 1)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_ReadRFWr_MSK                (0x00200000)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_ReadRFWr_MAX                (0x00000001)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_ReadRFWr_DEF                (0x00000000)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_ReadRFRank_OFF              (22)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_ReadRFRank_WID              ( 2)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_ReadRFRank_MSK              (0x00C00000)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_ReadRFRank_MAX              (0x00000003)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_ReadRFRank_DEF              (0x00000000)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_OFF              (24)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_WID              ( 1)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_MSK              (0x01000000)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_MAX              (0x00000001)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_DEF              (0x00000000)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_OdtSampOff_OFF              (25)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_OdtSampOff_WID              ( 1)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_OdtSampOff_MSK              (0x02000000)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_OdtSampOff_MAX              (0x00000001)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_OdtSampOff_DEF              (0x00000000)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_OFF        (26)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_WID        ( 1)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_MSK        (0x04000000)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_MAX        (0x00000001)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_DEF        (0x00000000)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_OFF         (27)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_WID         ( 1)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MSK         (0x08000000)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MAX         (0x00000001)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_DEF         (0x00000000)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_OFF              (28)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_WID              ( 1)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_MSK              (0x10000000)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_MAX              (0x00000001)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_DEF              (0x00000000)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_EnReadPreamble_OFF          (29)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_EnReadPreamble_WID          ( 1)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_EnReadPreamble_MSK          (0x20000000)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_EnReadPreamble_MAX          (0x00000001)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_EnReadPreamble_DEF          (0x00000000)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_OFF         (30)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_WID         ( 1)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MSK         (0x40000000)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MAX         (0x00000001)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_DEF         (0x00000000)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_OFF            (31)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_WID            ( 1)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_MSK            (0x80000000)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_MAX            (0x00000001)
+  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_DEF            (0x00000000)
+
+#define DDRDATA1CH0_CR_DDRCRVREFADJUST1_REG                          (0x00000278)
+  #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_CAVrefCtl_OFF                ( 0)
+  #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_CAVrefCtl_WID                ( 7)
+  #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_CAVrefCtl_MSK                (0x0000007F)
+  #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_CAVrefCtl_MAX                (0x0000007F)
+  #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_CAVrefCtl_DEF                (0x00000000)
+  #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_Ch1VrefCtl_OFF               ( 7)
+  #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_Ch1VrefCtl_WID               ( 7)
+  #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_Ch1VrefCtl_MSK               (0x00003F80)
+  #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_Ch1VrefCtl_MAX               (0x0000007F)
+  #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_Ch1VrefCtl_DEF               (0x00000000)
+  #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_Ch0VrefCtl_OFF               (14)
+  #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_Ch0VrefCtl_WID               ( 7)
+  #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_Ch0VrefCtl_MSK               (0x001FC000)
+  #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_Ch0VrefCtl_MAX               (0x0000007F)
+  #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_Ch0VrefCtl_DEF               (0x00000000)
+  #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCA_OFF             (21)
+  #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCA_WID             ( 1)
+  #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCA_MSK             (0x00200000)
+  #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCA_MAX             (0x00000001)
+  #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCA_DEF             (0x00000000)
+  #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_OFF            (22)
+  #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_WID            ( 1)
+  #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_MSK            (0x00400000)
+  #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_MAX            (0x00000001)
+  #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_DEF            (0x00000000)
+  #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_OFF            (23)
+  #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_WID            ( 1)
+  #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_MSK            (0x00800000)
+  #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_MAX            (0x00000001)
+  #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_DEF            (0x00000000)
+  #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_HiZTimerCtrl_OFF             (24)
+  #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_HiZTimerCtrl_WID             ( 2)
+  #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_HiZTimerCtrl_MSK             (0x03000000)
+  #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_HiZTimerCtrl_MAX             (0x00000003)
+  #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_HiZTimerCtrl_DEF             (0x00000000)
+  #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_OFF            (26)
+  #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_WID            ( 1)
+  #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_MSK            (0x04000000)
+  #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_MAX            (0x00000001)
+  #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_DEF            (0x00000000)
+  #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_Rsvd_OFF                     (27)
+  #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_Rsvd_WID                     ( 2)
+  #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_Rsvd_MSK                     (0x18000000)
+  #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_Rsvd_MAX                     (0x00000003)
+  #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_Rsvd_DEF                     (0x00000000)
+  #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_caSlowBW_OFF                 (29)
+  #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_caSlowBW_WID                 ( 1)
+  #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_caSlowBW_MSK                 (0x20000000)
+  #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_caSlowBW_MAX                 (0x00000001)
+  #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_caSlowBW_DEF                 (0x00000000)
+  #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_ch0SlowBW_OFF                (30)
+  #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_ch0SlowBW_WID                ( 1)
+  #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_ch0SlowBW_MSK                (0x40000000)
+  #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_ch0SlowBW_MAX                (0x00000001)
+  #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_ch0SlowBW_DEF                (0x00000000)
+  #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_ch1SlowBW_OFF                (31)
+  #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_ch1SlowBW_WID                ( 1)
+  #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_ch1SlowBW_MSK                (0x80000000)
+  #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_ch1SlowBW_MAX                (0x00000001)
+  #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_ch1SlowBW_DEF                (0x00000000)
+
+#define DDRDATA1CH1_CR_RXTRAINRANK0_REG                              (0x00000300)
+  #define DDRDATA1CH1_CR_RXTRAINRANK0_RxRcvEnPi_OFF                    ( 0)
+  #define DDRDATA1CH1_CR_RXTRAINRANK0_RxRcvEnPi_WID                    ( 9)
+  #define DDRDATA1CH1_CR_RXTRAINRANK0_RxRcvEnPi_MSK                    (0x000001FF)
+  #define DDRDATA1CH1_CR_RXTRAINRANK0_RxRcvEnPi_MAX                    (0x000001FF)
+  #define DDRDATA1CH1_CR_RXTRAINRANK0_RxDqsPPi_OFF                     ( 9)
+  #define DDRDATA1CH1_CR_RXTRAINRANK0_RxDqsPPi_WID                     ( 6)
+  #define DDRDATA1CH1_CR_RXTRAINRANK0_RxDqsPPi_MSK                     (0x00007E00)
+  #define DDRDATA1CH1_CR_RXTRAINRANK0_RxDqsPPi_MAX                     (0x0000003F)
+  #define DDRDATA1CH1_CR_RXTRAINRANK0_RxEq_OFF                         (15)
+  #define DDRDATA1CH1_CR_RXTRAINRANK0_RxEq_WID                         ( 5)
+  #define DDRDATA1CH1_CR_RXTRAINRANK0_RxEq_MSK                         (0x000F8000)
+  #define DDRDATA1CH1_CR_RXTRAINRANK0_RxEq_MAX                         (0x0000001F)
+  #define DDRDATA1CH1_CR_RXTRAINRANK0_RxDqsNPi_OFF                     (20)
+  #define DDRDATA1CH1_CR_RXTRAINRANK0_RxDqsNPi_WID                     ( 6)
+  #define DDRDATA1CH1_CR_RXTRAINRANK0_RxDqsNPi_MSK                     (0x03F00000)
+  #define DDRDATA1CH1_CR_RXTRAINRANK0_RxDqsNPi_MAX                     (0x0000003F)
+  #define DDRDATA1CH1_CR_RXTRAINRANK0_RxVref_OFF                       (26)
+  #define DDRDATA1CH1_CR_RXTRAINRANK0_RxVref_WID                       ( 6)
+  #define DDRDATA1CH1_CR_RXTRAINRANK0_RxVref_MSK                       (0xFC000000)
+  #define DDRDATA1CH1_CR_RXTRAINRANK0_RxVref_MAX                       (0x0000003F)
+
+#define DDRDATA1CH1_CR_RXTRAINRANK1_REG                              (0x00000304)
+  #define DDRDATA1CH1_CR_RXTRAINRANK1_RxRcvEnPi_OFF                    ( 0)
+  #define DDRDATA1CH1_CR_RXTRAINRANK1_RxRcvEnPi_WID                    ( 9)
+  #define DDRDATA1CH1_CR_RXTRAINRANK1_RxRcvEnPi_MSK                    (0x000001FF)
+  #define DDRDATA1CH1_CR_RXTRAINRANK1_RxRcvEnPi_MAX                    (0x000001FF)
+  #define DDRDATA1CH1_CR_RXTRAINRANK1_RxDqsPPi_OFF                     ( 9)
+  #define DDRDATA1CH1_CR_RXTRAINRANK1_RxDqsPPi_WID                     ( 6)
+  #define DDRDATA1CH1_CR_RXTRAINRANK1_RxDqsPPi_MSK                     (0x00007E00)
+  #define DDRDATA1CH1_CR_RXTRAINRANK1_RxDqsPPi_MAX                     (0x0000003F)
+  #define DDRDATA1CH1_CR_RXTRAINRANK1_RxEq_OFF                         (15)
+  #define DDRDATA1CH1_CR_RXTRAINRANK1_RxEq_WID                         ( 5)
+  #define DDRDATA1CH1_CR_RXTRAINRANK1_RxEq_MSK                         (0x000F8000)
+  #define DDRDATA1CH1_CR_RXTRAINRANK1_RxEq_MAX                         (0x0000001F)
+  #define DDRDATA1CH1_CR_RXTRAINRANK1_RxDqsNPi_OFF                     (20)
+  #define DDRDATA1CH1_CR_RXTRAINRANK1_RxDqsNPi_WID                     ( 6)
+  #define DDRDATA1CH1_CR_RXTRAINRANK1_RxDqsNPi_MSK                     (0x03F00000)
+  #define DDRDATA1CH1_CR_RXTRAINRANK1_RxDqsNPi_MAX                     (0x0000003F)
+  #define DDRDATA1CH1_CR_RXTRAINRANK1_RxVref_OFF                       (26)
+  #define DDRDATA1CH1_CR_RXTRAINRANK1_RxVref_WID                       ( 6)
+  #define DDRDATA1CH1_CR_RXTRAINRANK1_RxVref_MSK                       (0xFC000000)
+  #define DDRDATA1CH1_CR_RXTRAINRANK1_RxVref_MAX                       (0x0000003F)
+
+#define DDRDATA1CH1_CR_RXTRAINRANK2_REG                              (0x00000308)
+  #define DDRDATA1CH1_CR_RXTRAINRANK2_RxRcvEnPi_OFF                    ( 0)
+  #define DDRDATA1CH1_CR_RXTRAINRANK2_RxRcvEnPi_WID                    ( 9)
+  #define DDRDATA1CH1_CR_RXTRAINRANK2_RxRcvEnPi_MSK                    (0x000001FF)
+  #define DDRDATA1CH1_CR_RXTRAINRANK2_RxRcvEnPi_MAX                    (0x000001FF)
+  #define DDRDATA1CH1_CR_RXTRAINRANK2_RxDqsPPi_OFF                     ( 9)
+  #define DDRDATA1CH1_CR_RXTRAINRANK2_RxDqsPPi_WID                     ( 6)
+  #define DDRDATA1CH1_CR_RXTRAINRANK2_RxDqsPPi_MSK                     (0x00007E00)
+  #define DDRDATA1CH1_CR_RXTRAINRANK2_RxDqsPPi_MAX                     (0x0000003F)
+  #define DDRDATA1CH1_CR_RXTRAINRANK2_RxEq_OFF                         (15)
+  #define DDRDATA1CH1_CR_RXTRAINRANK2_RxEq_WID                         ( 5)
+  #define DDRDATA1CH1_CR_RXTRAINRANK2_RxEq_MSK                         (0x000F8000)
+  #define DDRDATA1CH1_CR_RXTRAINRANK2_RxEq_MAX                         (0x0000001F)
+  #define DDRDATA1CH1_CR_RXTRAINRANK2_RxDqsNPi_OFF                     (20)
+  #define DDRDATA1CH1_CR_RXTRAINRANK2_RxDqsNPi_WID                     ( 6)
+  #define DDRDATA1CH1_CR_RXTRAINRANK2_RxDqsNPi_MSK                     (0x03F00000)
+  #define DDRDATA1CH1_CR_RXTRAINRANK2_RxDqsNPi_MAX                     (0x0000003F)
+  #define DDRDATA1CH1_CR_RXTRAINRANK2_RxVref_OFF                       (26)
+  #define DDRDATA1CH1_CR_RXTRAINRANK2_RxVref_WID                       ( 6)
+  #define DDRDATA1CH1_CR_RXTRAINRANK2_RxVref_MSK                       (0xFC000000)
+  #define DDRDATA1CH1_CR_RXTRAINRANK2_RxVref_MAX                       (0x0000003F)
+
+#define DDRDATA1CH1_CR_RXTRAINRANK3_REG                              (0x0000030C)
+  #define DDRDATA1CH1_CR_RXTRAINRANK3_RxRcvEnPi_OFF                    ( 0)
+  #define DDRDATA1CH1_CR_RXTRAINRANK3_RxRcvEnPi_WID                    ( 9)
+  #define DDRDATA1CH1_CR_RXTRAINRANK3_RxRcvEnPi_MSK                    (0x000001FF)
+  #define DDRDATA1CH1_CR_RXTRAINRANK3_RxRcvEnPi_MAX                    (0x000001FF)
+  #define DDRDATA1CH1_CR_RXTRAINRANK3_RxDqsPPi_OFF                     ( 9)
+  #define DDRDATA1CH1_CR_RXTRAINRANK3_RxDqsPPi_WID                     ( 6)
+  #define DDRDATA1CH1_CR_RXTRAINRANK3_RxDqsPPi_MSK                     (0x00007E00)
+  #define DDRDATA1CH1_CR_RXTRAINRANK3_RxDqsPPi_MAX                     (0x0000003F)
+  #define DDRDATA1CH1_CR_RXTRAINRANK3_RxEq_OFF                         (15)
+  #define DDRDATA1CH1_CR_RXTRAINRANK3_RxEq_WID                         ( 5)
+  #define DDRDATA1CH1_CR_RXTRAINRANK3_RxEq_MSK                         (0x000F8000)
+  #define DDRDATA1CH1_CR_RXTRAINRANK3_RxEq_MAX                         (0x0000001F)
+  #define DDRDATA1CH1_CR_RXTRAINRANK3_RxDqsNPi_OFF                     (20)
+  #define DDRDATA1CH1_CR_RXTRAINRANK3_RxDqsNPi_WID                     ( 6)
+  #define DDRDATA1CH1_CR_RXTRAINRANK3_RxDqsNPi_MSK                     (0x03F00000)
+  #define DDRDATA1CH1_CR_RXTRAINRANK3_RxDqsNPi_MAX                     (0x0000003F)
+  #define DDRDATA1CH1_CR_RXTRAINRANK3_RxVref_OFF                       (26)
+  #define DDRDATA1CH1_CR_RXTRAINRANK3_RxVref_WID                       ( 6)
+  #define DDRDATA1CH1_CR_RXTRAINRANK3_RxVref_MSK                       (0xFC000000)
+  #define DDRDATA1CH1_CR_RXTRAINRANK3_RxVref_MAX                       (0x0000003F)
+
+#define DDRDATA1CH1_CR_RXPERBITRANK0_REG                             (0x00000310)
+  #define DDRDATA1CH1_CR_RXPERBITRANK0_Lane0_OFF                       ( 0)
+  #define DDRDATA1CH1_CR_RXPERBITRANK0_Lane0_WID                       ( 4)
+  #define DDRDATA1CH1_CR_RXPERBITRANK0_Lane0_MSK                       (0x0000000F)
+  #define DDRDATA1CH1_CR_RXPERBITRANK0_Lane0_MAX                       (0x0000000F)
+  #define DDRDATA1CH1_CR_RXPERBITRANK0_Lane1_OFF                       ( 4)
+  #define DDRDATA1CH1_CR_RXPERBITRANK0_Lane1_WID                       ( 4)
+  #define DDRDATA1CH1_CR_RXPERBITRANK0_Lane1_MSK                       (0x000000F0)
+  #define DDRDATA1CH1_CR_RXPERBITRANK0_Lane1_MAX                       (0x0000000F)
+  #define DDRDATA1CH1_CR_RXPERBITRANK0_Lane2_OFF                       ( 8)
+  #define DDRDATA1CH1_CR_RXPERBITRANK0_Lane2_WID                       ( 4)
+  #define DDRDATA1CH1_CR_RXPERBITRANK0_Lane2_MSK                       (0x00000F00)
+  #define DDRDATA1CH1_CR_RXPERBITRANK0_Lane2_MAX                       (0x0000000F)
+  #define DDRDATA1CH1_CR_RXPERBITRANK0_Lane3_OFF                       (12)
+  #define DDRDATA1CH1_CR_RXPERBITRANK0_Lane3_WID                       ( 4)
+  #define DDRDATA1CH1_CR_RXPERBITRANK0_Lane3_MSK                       (0x0000F000)
+  #define DDRDATA1CH1_CR_RXPERBITRANK0_Lane3_MAX                       (0x0000000F)
+  #define DDRDATA1CH1_CR_RXPERBITRANK0_Lane4_OFF                       (16)
+  #define DDRDATA1CH1_CR_RXPERBITRANK0_Lane4_WID                       ( 4)
+  #define DDRDATA1CH1_CR_RXPERBITRANK0_Lane4_MSK                       (0x000F0000)
+  #define DDRDATA1CH1_CR_RXPERBITRANK0_Lane4_MAX                       (0x0000000F)
+  #define DDRDATA1CH1_CR_RXPERBITRANK0_Lane5_OFF                       (20)
+  #define DDRDATA1CH1_CR_RXPERBITRANK0_Lane5_WID                       ( 4)
+  #define DDRDATA1CH1_CR_RXPERBITRANK0_Lane5_MSK                       (0x00F00000)
+  #define DDRDATA1CH1_CR_RXPERBITRANK0_Lane5_MAX                       (0x0000000F)
+  #define DDRDATA1CH1_CR_RXPERBITRANK0_Lane6_OFF                       (24)
+  #define DDRDATA1CH1_CR_RXPERBITRANK0_Lane6_WID                       ( 4)
+  #define DDRDATA1CH1_CR_RXPERBITRANK0_Lane6_MSK                       (0x0F000000)
+  #define DDRDATA1CH1_CR_RXPERBITRANK0_Lane6_MAX                       (0x0000000F)
+  #define DDRDATA1CH1_CR_RXPERBITRANK0_Lane7_OFF                       (28)
+  #define DDRDATA1CH1_CR_RXPERBITRANK0_Lane7_WID                       ( 4)
+  #define DDRDATA1CH1_CR_RXPERBITRANK0_Lane7_MSK                       (0xF0000000)
+  #define DDRDATA1CH1_CR_RXPERBITRANK0_Lane7_MAX                       (0x0000000F)
+
+#define DDRDATA1CH1_CR_RXPERBITRANK1_REG                             (0x00000314)
+  #define DDRDATA1CH1_CR_RXPERBITRANK1_Lane0_OFF                       ( 0)
+  #define DDRDATA1CH1_CR_RXPERBITRANK1_Lane0_WID                       ( 4)
+  #define DDRDATA1CH1_CR_RXPERBITRANK1_Lane0_MSK                       (0x0000000F)
+  #define DDRDATA1CH1_CR_RXPERBITRANK1_Lane0_MAX                       (0x0000000F)
+  #define DDRDATA1CH1_CR_RXPERBITRANK1_Lane1_OFF                       ( 4)
+  #define DDRDATA1CH1_CR_RXPERBITRANK1_Lane1_WID                       ( 4)
+  #define DDRDATA1CH1_CR_RXPERBITRANK1_Lane1_MSK                       (0x000000F0)
+  #define DDRDATA1CH1_CR_RXPERBITRANK1_Lane1_MAX                       (0x0000000F)
+  #define DDRDATA1CH1_CR_RXPERBITRANK1_Lane2_OFF                       ( 8)
+  #define DDRDATA1CH1_CR_RXPERBITRANK1_Lane2_WID                       ( 4)
+  #define DDRDATA1CH1_CR_RXPERBITRANK1_Lane2_MSK                       (0x00000F00)
+  #define DDRDATA1CH1_CR_RXPERBITRANK1_Lane2_MAX                       (0x0000000F)
+  #define DDRDATA1CH1_CR_RXPERBITRANK1_Lane3_OFF                       (12)
+  #define DDRDATA1CH1_CR_RXPERBITRANK1_Lane3_WID                       ( 4)
+  #define DDRDATA1CH1_CR_RXPERBITRANK1_Lane3_MSK                       (0x0000F000)
+  #define DDRDATA1CH1_CR_RXPERBITRANK1_Lane3_MAX                       (0x0000000F)
+  #define DDRDATA1CH1_CR_RXPERBITRANK1_Lane4_OFF                       (16)
+  #define DDRDATA1CH1_CR_RXPERBITRANK1_Lane4_WID                       ( 4)
+  #define DDRDATA1CH1_CR_RXPERBITRANK1_Lane4_MSK                       (0x000F0000)
+  #define DDRDATA1CH1_CR_RXPERBITRANK1_Lane4_MAX                       (0x0000000F)
+  #define DDRDATA1CH1_CR_RXPERBITRANK1_Lane5_OFF                       (20)
+  #define DDRDATA1CH1_CR_RXPERBITRANK1_Lane5_WID                       ( 4)
+  #define DDRDATA1CH1_CR_RXPERBITRANK1_Lane5_MSK                       (0x00F00000)
+  #define DDRDATA1CH1_CR_RXPERBITRANK1_Lane5_MAX                       (0x0000000F)
+  #define DDRDATA1CH1_CR_RXPERBITRANK1_Lane6_OFF                       (24)
+  #define DDRDATA1CH1_CR_RXPERBITRANK1_Lane6_WID                       ( 4)
+  #define DDRDATA1CH1_CR_RXPERBITRANK1_Lane6_MSK                       (0x0F000000)
+  #define DDRDATA1CH1_CR_RXPERBITRANK1_Lane6_MAX                       (0x0000000F)
+  #define DDRDATA1CH1_CR_RXPERBITRANK1_Lane7_OFF                       (28)
+  #define DDRDATA1CH1_CR_RXPERBITRANK1_Lane7_WID                       ( 4)
+  #define DDRDATA1CH1_CR_RXPERBITRANK1_Lane7_MSK                       (0xF0000000)
+  #define DDRDATA1CH1_CR_RXPERBITRANK1_Lane7_MAX                       (0x0000000F)
+
+#define DDRDATA1CH1_CR_RXPERBITRANK2_REG                             (0x00000318)
+  #define DDRDATA1CH1_CR_RXPERBITRANK2_Lane0_OFF                       ( 0)
+  #define DDRDATA1CH1_CR_RXPERBITRANK2_Lane0_WID                       ( 4)
+  #define DDRDATA1CH1_CR_RXPERBITRANK2_Lane0_MSK                       (0x0000000F)
+  #define DDRDATA1CH1_CR_RXPERBITRANK2_Lane0_MAX                       (0x0000000F)
+  #define DDRDATA1CH1_CR_RXPERBITRANK2_Lane1_OFF                       ( 4)
+  #define DDRDATA1CH1_CR_RXPERBITRANK2_Lane1_WID                       ( 4)
+  #define DDRDATA1CH1_CR_RXPERBITRANK2_Lane1_MSK                       (0x000000F0)
+  #define DDRDATA1CH1_CR_RXPERBITRANK2_Lane1_MAX                       (0x0000000F)
+  #define DDRDATA1CH1_CR_RXPERBITRANK2_Lane2_OFF                       ( 8)
+  #define DDRDATA1CH1_CR_RXPERBITRANK2_Lane2_WID                       ( 4)
+  #define DDRDATA1CH1_CR_RXPERBITRANK2_Lane2_MSK                       (0x00000F00)
+  #define DDRDATA1CH1_CR_RXPERBITRANK2_Lane2_MAX                       (0x0000000F)
+  #define DDRDATA1CH1_CR_RXPERBITRANK2_Lane3_OFF                       (12)
+  #define DDRDATA1CH1_CR_RXPERBITRANK2_Lane3_WID                       ( 4)
+  #define DDRDATA1CH1_CR_RXPERBITRANK2_Lane3_MSK                       (0x0000F000)
+  #define DDRDATA1CH1_CR_RXPERBITRANK2_Lane3_MAX                       (0x0000000F)
+  #define DDRDATA1CH1_CR_RXPERBITRANK2_Lane4_OFF                       (16)
+  #define DDRDATA1CH1_CR_RXPERBITRANK2_Lane4_WID                       ( 4)
+  #define DDRDATA1CH1_CR_RXPERBITRANK2_Lane4_MSK                       (0x000F0000)
+  #define DDRDATA1CH1_CR_RXPERBITRANK2_Lane4_MAX                       (0x0000000F)
+  #define DDRDATA1CH1_CR_RXPERBITRANK2_Lane5_OFF                       (20)
+  #define DDRDATA1CH1_CR_RXPERBITRANK2_Lane5_WID                       ( 4)
+  #define DDRDATA1CH1_CR_RXPERBITRANK2_Lane5_MSK                       (0x00F00000)
+  #define DDRDATA1CH1_CR_RXPERBITRANK2_Lane5_MAX                       (0x0000000F)
+  #define DDRDATA1CH1_CR_RXPERBITRANK2_Lane6_OFF                       (24)
+  #define DDRDATA1CH1_CR_RXPERBITRANK2_Lane6_WID                       ( 4)
+  #define DDRDATA1CH1_CR_RXPERBITRANK2_Lane6_MSK                       (0x0F000000)
+  #define DDRDATA1CH1_CR_RXPERBITRANK2_Lane6_MAX                       (0x0000000F)
+  #define DDRDATA1CH1_CR_RXPERBITRANK2_Lane7_OFF                       (28)
+  #define DDRDATA1CH1_CR_RXPERBITRANK2_Lane7_WID                       ( 4)
+  #define DDRDATA1CH1_CR_RXPERBITRANK2_Lane7_MSK                       (0xF0000000)
+  #define DDRDATA1CH1_CR_RXPERBITRANK2_Lane7_MAX                       (0x0000000F)
+
+#define DDRDATA1CH1_CR_RXPERBITRANK3_REG                             (0x0000031C)
+  #define DDRDATA1CH1_CR_RXPERBITRANK3_Lane0_OFF                       ( 0)
+  #define DDRDATA1CH1_CR_RXPERBITRANK3_Lane0_WID                       ( 4)
+  #define DDRDATA1CH1_CR_RXPERBITRANK3_Lane0_MSK                       (0x0000000F)
+  #define DDRDATA1CH1_CR_RXPERBITRANK3_Lane0_MAX                       (0x0000000F)
+  #define DDRDATA1CH1_CR_RXPERBITRANK3_Lane1_OFF                       ( 4)
+  #define DDRDATA1CH1_CR_RXPERBITRANK3_Lane1_WID                       ( 4)
+  #define DDRDATA1CH1_CR_RXPERBITRANK3_Lane1_MSK                       (0x000000F0)
+  #define DDRDATA1CH1_CR_RXPERBITRANK3_Lane1_MAX                       (0x0000000F)
+  #define DDRDATA1CH1_CR_RXPERBITRANK3_Lane2_OFF                       ( 8)
+  #define DDRDATA1CH1_CR_RXPERBITRANK3_Lane2_WID                       ( 4)
+  #define DDRDATA1CH1_CR_RXPERBITRANK3_Lane2_MSK                       (0x00000F00)
+  #define DDRDATA1CH1_CR_RXPERBITRANK3_Lane2_MAX                       (0x0000000F)
+  #define DDRDATA1CH1_CR_RXPERBITRANK3_Lane3_OFF                       (12)
+  #define DDRDATA1CH1_CR_RXPERBITRANK3_Lane3_WID                       ( 4)
+  #define DDRDATA1CH1_CR_RXPERBITRANK3_Lane3_MSK                       (0x0000F000)
+  #define DDRDATA1CH1_CR_RXPERBITRANK3_Lane3_MAX                       (0x0000000F)
+  #define DDRDATA1CH1_CR_RXPERBITRANK3_Lane4_OFF                       (16)
+  #define DDRDATA1CH1_CR_RXPERBITRANK3_Lane4_WID                       ( 4)
+  #define DDRDATA1CH1_CR_RXPERBITRANK3_Lane4_MSK                       (0x000F0000)
+  #define DDRDATA1CH1_CR_RXPERBITRANK3_Lane4_MAX                       (0x0000000F)
+  #define DDRDATA1CH1_CR_RXPERBITRANK3_Lane5_OFF                       (20)
+  #define DDRDATA1CH1_CR_RXPERBITRANK3_Lane5_WID                       ( 4)
+  #define DDRDATA1CH1_CR_RXPERBITRANK3_Lane5_MSK                       (0x00F00000)
+  #define DDRDATA1CH1_CR_RXPERBITRANK3_Lane5_MAX                       (0x0000000F)
+  #define DDRDATA1CH1_CR_RXPERBITRANK3_Lane6_OFF                       (24)
+  #define DDRDATA1CH1_CR_RXPERBITRANK3_Lane6_WID                       ( 4)
+  #define DDRDATA1CH1_CR_RXPERBITRANK3_Lane6_MSK                       (0x0F000000)
+  #define DDRDATA1CH1_CR_RXPERBITRANK3_Lane6_MAX                       (0x0000000F)
+  #define DDRDATA1CH1_CR_RXPERBITRANK3_Lane7_OFF                       (28)
+  #define DDRDATA1CH1_CR_RXPERBITRANK3_Lane7_WID                       ( 4)
+  #define DDRDATA1CH1_CR_RXPERBITRANK3_Lane7_MSK                       (0xF0000000)
+  #define DDRDATA1CH1_CR_RXPERBITRANK3_Lane7_MAX                       (0x0000000F)
+
+#define DDRDATA1CH1_CR_TXTRAINRANK0_REG                              (0x00000320)
+  #define DDRDATA1CH1_CR_TXTRAINRANK0_TxDqDelay_OFF                    ( 0)
+  #define DDRDATA1CH1_CR_TXTRAINRANK0_TxDqDelay_WID                    ( 9)
+  #define DDRDATA1CH1_CR_TXTRAINRANK0_TxDqDelay_MSK                    (0x000001FF)
+  #define DDRDATA1CH1_CR_TXTRAINRANK0_TxDqDelay_MAX                    (0x000001FF)
+  #define DDRDATA1CH1_CR_TXTRAINRANK0_TxDqsDelay_OFF                   ( 9)
+  #define DDRDATA1CH1_CR_TXTRAINRANK0_TxDqsDelay_WID                   ( 9)
+  #define DDRDATA1CH1_CR_TXTRAINRANK0_TxDqsDelay_MSK                   (0x0003FE00)
+  #define DDRDATA1CH1_CR_TXTRAINRANK0_TxDqsDelay_MAX                   (0x000001FF)
+  #define DDRDATA1CH1_CR_TXTRAINRANK0_Spare0_OFF                       (18)
+  #define DDRDATA1CH1_CR_TXTRAINRANK0_Spare0_WID                       ( 2)
+  #define DDRDATA1CH1_CR_TXTRAINRANK0_Spare0_MSK                       (0x000C0000)
+  #define DDRDATA1CH1_CR_TXTRAINRANK0_Spare0_MAX                       (0x00000003)
+  #define DDRDATA1CH1_CR_TXTRAINRANK0_TxEqualization_OFF               (20)
+  #define DDRDATA1CH1_CR_TXTRAINRANK0_TxEqualization_WID               ( 6)
+  #define DDRDATA1CH1_CR_TXTRAINRANK0_TxEqualization_MSK               (0x03F00000)
+  #define DDRDATA1CH1_CR_TXTRAINRANK0_TxEqualization_MAX               (0x0000003F)
+  #define DDRDATA1CH1_CR_TXTRAINRANK0_Spare1_OFF                       (26)
+  #define DDRDATA1CH1_CR_TXTRAINRANK0_Spare1_WID                       ( 6)
+  #define DDRDATA1CH1_CR_TXTRAINRANK0_Spare1_MSK                       (0xFC000000)
+  #define DDRDATA1CH1_CR_TXTRAINRANK0_Spare1_MAX                       (0x0000003F)
+
+#define DDRDATA1CH1_CR_TXTRAINRANK1_REG                              (0x00000324)
+  #define DDRDATA1CH1_CR_TXTRAINRANK1_TxDqDelay_OFF                    ( 0)
+  #define DDRDATA1CH1_CR_TXTRAINRANK1_TxDqDelay_WID                    ( 9)
+  #define DDRDATA1CH1_CR_TXTRAINRANK1_TxDqDelay_MSK                    (0x000001FF)
+  #define DDRDATA1CH1_CR_TXTRAINRANK1_TxDqDelay_MAX                    (0x000001FF)
+  #define DDRDATA1CH1_CR_TXTRAINRANK1_TxDqsDelay_OFF                   ( 9)
+  #define DDRDATA1CH1_CR_TXTRAINRANK1_TxDqsDelay_WID                   ( 9)
+  #define DDRDATA1CH1_CR_TXTRAINRANK1_TxDqsDelay_MSK                   (0x0003FE00)
+  #define DDRDATA1CH1_CR_TXTRAINRANK1_TxDqsDelay_MAX                   (0x000001FF)
+  #define DDRDATA1CH1_CR_TXTRAINRANK1_Spare0_OFF                       (18)
+  #define DDRDATA1CH1_CR_TXTRAINRANK1_Spare0_WID                       ( 2)
+  #define DDRDATA1CH1_CR_TXTRAINRANK1_Spare0_MSK                       (0x000C0000)
+  #define DDRDATA1CH1_CR_TXTRAINRANK1_Spare0_MAX                       (0x00000003)
+  #define DDRDATA1CH1_CR_TXTRAINRANK1_TxEqualization_OFF               (20)
+  #define DDRDATA1CH1_CR_TXTRAINRANK1_TxEqualization_WID               ( 6)
+  #define DDRDATA1CH1_CR_TXTRAINRANK1_TxEqualization_MSK               (0x03F00000)
+  #define DDRDATA1CH1_CR_TXTRAINRANK1_TxEqualization_MAX               (0x0000003F)
+  #define DDRDATA1CH1_CR_TXTRAINRANK1_Spare1_OFF                       (26)
+  #define DDRDATA1CH1_CR_TXTRAINRANK1_Spare1_WID                       ( 6)
+  #define DDRDATA1CH1_CR_TXTRAINRANK1_Spare1_MSK                       (0xFC000000)
+  #define DDRDATA1CH1_CR_TXTRAINRANK1_Spare1_MAX                       (0x0000003F)
+
+#define DDRDATA1CH1_CR_TXTRAINRANK2_REG                              (0x00000328)
+  #define DDRDATA1CH1_CR_TXTRAINRANK2_TxDqDelay_OFF                    ( 0)
+  #define DDRDATA1CH1_CR_TXTRAINRANK2_TxDqDelay_WID                    ( 9)
+  #define DDRDATA1CH1_CR_TXTRAINRANK2_TxDqDelay_MSK                    (0x000001FF)
+  #define DDRDATA1CH1_CR_TXTRAINRANK2_TxDqDelay_MAX                    (0x000001FF)
+  #define DDRDATA1CH1_CR_TXTRAINRANK2_TxDqsDelay_OFF                   ( 9)
+  #define DDRDATA1CH1_CR_TXTRAINRANK2_TxDqsDelay_WID                   ( 9)
+  #define DDRDATA1CH1_CR_TXTRAINRANK2_TxDqsDelay_MSK                   (0x0003FE00)
+  #define DDRDATA1CH1_CR_TXTRAINRANK2_TxDqsDelay_MAX                   (0x000001FF)
+  #define DDRDATA1CH1_CR_TXTRAINRANK2_Spare0_OFF                       (18)
+  #define DDRDATA1CH1_CR_TXTRAINRANK2_Spare0_WID                       ( 2)
+  #define DDRDATA1CH1_CR_TXTRAINRANK2_Spare0_MSK                       (0x000C0000)
+  #define DDRDATA1CH1_CR_TXTRAINRANK2_Spare0_MAX                       (0x00000003)
+  #define DDRDATA1CH1_CR_TXTRAINRANK2_TxEqualization_OFF               (20)
+  #define DDRDATA1CH1_CR_TXTRAINRANK2_TxEqualization_WID               ( 6)
+  #define DDRDATA1CH1_CR_TXTRAINRANK2_TxEqualization_MSK               (0x03F00000)
+  #define DDRDATA1CH1_CR_TXTRAINRANK2_TxEqualization_MAX               (0x0000003F)
+  #define DDRDATA1CH1_CR_TXTRAINRANK2_Spare1_OFF                       (26)
+  #define DDRDATA1CH1_CR_TXTRAINRANK2_Spare1_WID                       ( 6)
+  #define DDRDATA1CH1_CR_TXTRAINRANK2_Spare1_MSK                       (0xFC000000)
+  #define DDRDATA1CH1_CR_TXTRAINRANK2_Spare1_MAX                       (0x0000003F)
+
+#define DDRDATA1CH1_CR_TXTRAINRANK3_REG                              (0x0000032C)
+  #define DDRDATA1CH1_CR_TXTRAINRANK3_TxDqDelay_OFF                    ( 0)
+  #define DDRDATA1CH1_CR_TXTRAINRANK3_TxDqDelay_WID                    ( 9)
+  #define DDRDATA1CH1_CR_TXTRAINRANK3_TxDqDelay_MSK                    (0x000001FF)
+  #define DDRDATA1CH1_CR_TXTRAINRANK3_TxDqDelay_MAX                    (0x000001FF)
+  #define DDRDATA1CH1_CR_TXTRAINRANK3_TxDqsDelay_OFF                   ( 9)
+  #define DDRDATA1CH1_CR_TXTRAINRANK3_TxDqsDelay_WID                   ( 9)
+  #define DDRDATA1CH1_CR_TXTRAINRANK3_TxDqsDelay_MSK                   (0x0003FE00)
+  #define DDRDATA1CH1_CR_TXTRAINRANK3_TxDqsDelay_MAX                   (0x000001FF)
+  #define DDRDATA1CH1_CR_TXTRAINRANK3_Spare0_OFF                       (18)
+  #define DDRDATA1CH1_CR_TXTRAINRANK3_Spare0_WID                       ( 2)
+  #define DDRDATA1CH1_CR_TXTRAINRANK3_Spare0_MSK                       (0x000C0000)
+  #define DDRDATA1CH1_CR_TXTRAINRANK3_Spare0_MAX                       (0x00000003)
+  #define DDRDATA1CH1_CR_TXTRAINRANK3_TxEqualization_OFF               (20)
+  #define DDRDATA1CH1_CR_TXTRAINRANK3_TxEqualization_WID               ( 6)
+  #define DDRDATA1CH1_CR_TXTRAINRANK3_TxEqualization_MSK               (0x03F00000)
+  #define DDRDATA1CH1_CR_TXTRAINRANK3_TxEqualization_MAX               (0x0000003F)
+  #define DDRDATA1CH1_CR_TXTRAINRANK3_Spare1_OFF                       (26)
+  #define DDRDATA1CH1_CR_TXTRAINRANK3_Spare1_WID                       ( 6)
+  #define DDRDATA1CH1_CR_TXTRAINRANK3_Spare1_MSK                       (0xFC000000)
+  #define DDRDATA1CH1_CR_TXTRAINRANK3_Spare1_MAX                       (0x0000003F)
+
+#define DDRDATA1CH1_CR_TXPERBITRANK0_REG                             (0x00000330)
+  #define DDRDATA1CH1_CR_TXPERBITRANK0_Lane0_OFF                       ( 0)
+  #define DDRDATA1CH1_CR_TXPERBITRANK0_Lane0_WID                       ( 4)
+  #define DDRDATA1CH1_CR_TXPERBITRANK0_Lane0_MSK                       (0x0000000F)
+  #define DDRDATA1CH1_CR_TXPERBITRANK0_Lane0_MAX                       (0x0000000F)
+  #define DDRDATA1CH1_CR_TXPERBITRANK0_Lane1_OFF                       ( 4)
+  #define DDRDATA1CH1_CR_TXPERBITRANK0_Lane1_WID                       ( 4)
+  #define DDRDATA1CH1_CR_TXPERBITRANK0_Lane1_MSK                       (0x000000F0)
+  #define DDRDATA1CH1_CR_TXPERBITRANK0_Lane1_MAX                       (0x0000000F)
+  #define DDRDATA1CH1_CR_TXPERBITRANK0_Lane2_OFF                       ( 8)
+  #define DDRDATA1CH1_CR_TXPERBITRANK0_Lane2_WID                       ( 4)
+  #define DDRDATA1CH1_CR_TXPERBITRANK0_Lane2_MSK                       (0x00000F00)
+  #define DDRDATA1CH1_CR_TXPERBITRANK0_Lane2_MAX                       (0x0000000F)
+  #define DDRDATA1CH1_CR_TXPERBITRANK0_Lane3_OFF                       (12)
+  #define DDRDATA1CH1_CR_TXPERBITRANK0_Lane3_WID                       ( 4)
+  #define DDRDATA1CH1_CR_TXPERBITRANK0_Lane3_MSK                       (0x0000F000)
+  #define DDRDATA1CH1_CR_TXPERBITRANK0_Lane3_MAX                       (0x0000000F)
+  #define DDRDATA1CH1_CR_TXPERBITRANK0_Lane4_OFF                       (16)
+  #define DDRDATA1CH1_CR_TXPERBITRANK0_Lane4_WID                       ( 4)
+  #define DDRDATA1CH1_CR_TXPERBITRANK0_Lane4_MSK                       (0x000F0000)
+  #define DDRDATA1CH1_CR_TXPERBITRANK0_Lane4_MAX                       (0x0000000F)
+  #define DDRDATA1CH1_CR_TXPERBITRANK0_Lane5_OFF                       (20)
+  #define DDRDATA1CH1_CR_TXPERBITRANK0_Lane5_WID                       ( 4)
+  #define DDRDATA1CH1_CR_TXPERBITRANK0_Lane5_MSK                       (0x00F00000)
+  #define DDRDATA1CH1_CR_TXPERBITRANK0_Lane5_MAX                       (0x0000000F)
+  #define DDRDATA1CH1_CR_TXPERBITRANK0_Lane6_OFF                       (24)
+  #define DDRDATA1CH1_CR_TXPERBITRANK0_Lane6_WID                       ( 4)
+  #define DDRDATA1CH1_CR_TXPERBITRANK0_Lane6_MSK                       (0x0F000000)
+  #define DDRDATA1CH1_CR_TXPERBITRANK0_Lane6_MAX                       (0x0000000F)
+  #define DDRDATA1CH1_CR_TXPERBITRANK0_Lane7_OFF                       (28)
+  #define DDRDATA1CH1_CR_TXPERBITRANK0_Lane7_WID                       ( 4)
+  #define DDRDATA1CH1_CR_TXPERBITRANK0_Lane7_MSK                       (0xF0000000)
+  #define DDRDATA1CH1_CR_TXPERBITRANK0_Lane7_MAX                       (0x0000000F)
+
+#define DDRDATA1CH1_CR_TXPERBITRANK1_REG                             (0x00000334)
+  #define DDRDATA1CH1_CR_TXPERBITRANK1_Lane0_OFF                       ( 0)
+  #define DDRDATA1CH1_CR_TXPERBITRANK1_Lane0_WID                       ( 4)
+  #define DDRDATA1CH1_CR_TXPERBITRANK1_Lane0_MSK                       (0x0000000F)
+  #define DDRDATA1CH1_CR_TXPERBITRANK1_Lane0_MAX                       (0x0000000F)
+  #define DDRDATA1CH1_CR_TXPERBITRANK1_Lane1_OFF                       ( 4)
+  #define DDRDATA1CH1_CR_TXPERBITRANK1_Lane1_WID                       ( 4)
+  #define DDRDATA1CH1_CR_TXPERBITRANK1_Lane1_MSK                       (0x000000F0)
+  #define DDRDATA1CH1_CR_TXPERBITRANK1_Lane1_MAX                       (0x0000000F)
+  #define DDRDATA1CH1_CR_TXPERBITRANK1_Lane2_OFF                       ( 8)
+  #define DDRDATA1CH1_CR_TXPERBITRANK1_Lane2_WID                       ( 4)
+  #define DDRDATA1CH1_CR_TXPERBITRANK1_Lane2_MSK                       (0x00000F00)
+  #define DDRDATA1CH1_CR_TXPERBITRANK1_Lane2_MAX                       (0x0000000F)
+  #define DDRDATA1CH1_CR_TXPERBITRANK1_Lane3_OFF                       (12)
+  #define DDRDATA1CH1_CR_TXPERBITRANK1_Lane3_WID                       ( 4)
+  #define DDRDATA1CH1_CR_TXPERBITRANK1_Lane3_MSK                       (0x0000F000)
+  #define DDRDATA1CH1_CR_TXPERBITRANK1_Lane3_MAX                       (0x0000000F)
+  #define DDRDATA1CH1_CR_TXPERBITRANK1_Lane4_OFF                       (16)
+  #define DDRDATA1CH1_CR_TXPERBITRANK1_Lane4_WID                       ( 4)
+  #define DDRDATA1CH1_CR_TXPERBITRANK1_Lane4_MSK                       (0x000F0000)
+  #define DDRDATA1CH1_CR_TXPERBITRANK1_Lane4_MAX                       (0x0000000F)
+  #define DDRDATA1CH1_CR_TXPERBITRANK1_Lane5_OFF                       (20)
+  #define DDRDATA1CH1_CR_TXPERBITRANK1_Lane5_WID                       ( 4)
+  #define DDRDATA1CH1_CR_TXPERBITRANK1_Lane5_MSK                       (0x00F00000)
+  #define DDRDATA1CH1_CR_TXPERBITRANK1_Lane5_MAX                       (0x0000000F)
+  #define DDRDATA1CH1_CR_TXPERBITRANK1_Lane6_OFF                       (24)
+  #define DDRDATA1CH1_CR_TXPERBITRANK1_Lane6_WID                       ( 4)
+  #define DDRDATA1CH1_CR_TXPERBITRANK1_Lane6_MSK                       (0x0F000000)
+  #define DDRDATA1CH1_CR_TXPERBITRANK1_Lane6_MAX                       (0x0000000F)
+  #define DDRDATA1CH1_CR_TXPERBITRANK1_Lane7_OFF                       (28)
+  #define DDRDATA1CH1_CR_TXPERBITRANK1_Lane7_WID                       ( 4)
+  #define DDRDATA1CH1_CR_TXPERBITRANK1_Lane7_MSK                       (0xF0000000)
+  #define DDRDATA1CH1_CR_TXPERBITRANK1_Lane7_MAX                       (0x0000000F)
+
+#define DDRDATA1CH1_CR_TXPERBITRANK2_REG                             (0x00000338)
+  #define DDRDATA1CH1_CR_TXPERBITRANK2_Lane0_OFF                       ( 0)
+  #define DDRDATA1CH1_CR_TXPERBITRANK2_Lane0_WID                       ( 4)
+  #define DDRDATA1CH1_CR_TXPERBITRANK2_Lane0_MSK                       (0x0000000F)
+  #define DDRDATA1CH1_CR_TXPERBITRANK2_Lane0_MAX                       (0x0000000F)
+  #define DDRDATA1CH1_CR_TXPERBITRANK2_Lane1_OFF                       ( 4)
+  #define DDRDATA1CH1_CR_TXPERBITRANK2_Lane1_WID                       ( 4)
+  #define DDRDATA1CH1_CR_TXPERBITRANK2_Lane1_MSK                       (0x000000F0)
+  #define DDRDATA1CH1_CR_TXPERBITRANK2_Lane1_MAX                       (0x0000000F)
+  #define DDRDATA1CH1_CR_TXPERBITRANK2_Lane2_OFF                       ( 8)
+  #define DDRDATA1CH1_CR_TXPERBITRANK2_Lane2_WID                       ( 4)
+  #define DDRDATA1CH1_CR_TXPERBITRANK2_Lane2_MSK                       (0x00000F00)
+  #define DDRDATA1CH1_CR_TXPERBITRANK2_Lane2_MAX                       (0x0000000F)
+  #define DDRDATA1CH1_CR_TXPERBITRANK2_Lane3_OFF                       (12)
+  #define DDRDATA1CH1_CR_TXPERBITRANK2_Lane3_WID                       ( 4)
+  #define DDRDATA1CH1_CR_TXPERBITRANK2_Lane3_MSK                       (0x0000F000)
+  #define DDRDATA1CH1_CR_TXPERBITRANK2_Lane3_MAX                       (0x0000000F)
+  #define DDRDATA1CH1_CR_TXPERBITRANK2_Lane4_OFF                       (16)
+  #define DDRDATA1CH1_CR_TXPERBITRANK2_Lane4_WID                       ( 4)
+  #define DDRDATA1CH1_CR_TXPERBITRANK2_Lane4_MSK                       (0x000F0000)
+  #define DDRDATA1CH1_CR_TXPERBITRANK2_Lane4_MAX                       (0x0000000F)
+  #define DDRDATA1CH1_CR_TXPERBITRANK2_Lane5_OFF                       (20)
+  #define DDRDATA1CH1_CR_TXPERBITRANK2_Lane5_WID                       ( 4)
+  #define DDRDATA1CH1_CR_TXPERBITRANK2_Lane5_MSK                       (0x00F00000)
+  #define DDRDATA1CH1_CR_TXPERBITRANK2_Lane5_MAX                       (0x0000000F)
+  #define DDRDATA1CH1_CR_TXPERBITRANK2_Lane6_OFF                       (24)
+  #define DDRDATA1CH1_CR_TXPERBITRANK2_Lane6_WID                       ( 4)
+  #define DDRDATA1CH1_CR_TXPERBITRANK2_Lane6_MSK                       (0x0F000000)
+  #define DDRDATA1CH1_CR_TXPERBITRANK2_Lane6_MAX                       (0x0000000F)
+  #define DDRDATA1CH1_CR_TXPERBITRANK2_Lane7_OFF                       (28)
+  #define DDRDATA1CH1_CR_TXPERBITRANK2_Lane7_WID                       ( 4)
+  #define DDRDATA1CH1_CR_TXPERBITRANK2_Lane7_MSK                       (0xF0000000)
+  #define DDRDATA1CH1_CR_TXPERBITRANK2_Lane7_MAX                       (0x0000000F)
+
+#define DDRDATA1CH1_CR_TXPERBITRANK3_REG                             (0x0000033C)
+  #define DDRDATA1CH1_CR_TXPERBITRANK3_Lane0_OFF                       ( 0)
+  #define DDRDATA1CH1_CR_TXPERBITRANK3_Lane0_WID                       ( 4)
+  #define DDRDATA1CH1_CR_TXPERBITRANK3_Lane0_MSK                       (0x0000000F)
+  #define DDRDATA1CH1_CR_TXPERBITRANK3_Lane0_MAX                       (0x0000000F)
+  #define DDRDATA1CH1_CR_TXPERBITRANK3_Lane1_OFF                       ( 4)
+  #define DDRDATA1CH1_CR_TXPERBITRANK3_Lane1_WID                       ( 4)
+  #define DDRDATA1CH1_CR_TXPERBITRANK3_Lane1_MSK                       (0x000000F0)
+  #define DDRDATA1CH1_CR_TXPERBITRANK3_Lane1_MAX                       (0x0000000F)
+  #define DDRDATA1CH1_CR_TXPERBITRANK3_Lane2_OFF                       ( 8)
+  #define DDRDATA1CH1_CR_TXPERBITRANK3_Lane2_WID                       ( 4)
+  #define DDRDATA1CH1_CR_TXPERBITRANK3_Lane2_MSK                       (0x00000F00)
+  #define DDRDATA1CH1_CR_TXPERBITRANK3_Lane2_MAX                       (0x0000000F)
+  #define DDRDATA1CH1_CR_TXPERBITRANK3_Lane3_OFF                       (12)
+  #define DDRDATA1CH1_CR_TXPERBITRANK3_Lane3_WID                       ( 4)
+  #define DDRDATA1CH1_CR_TXPERBITRANK3_Lane3_MSK                       (0x0000F000)
+  #define DDRDATA1CH1_CR_TXPERBITRANK3_Lane3_MAX                       (0x0000000F)
+  #define DDRDATA1CH1_CR_TXPERBITRANK3_Lane4_OFF                       (16)
+  #define DDRDATA1CH1_CR_TXPERBITRANK3_Lane4_WID                       ( 4)
+  #define DDRDATA1CH1_CR_TXPERBITRANK3_Lane4_MSK                       (0x000F0000)
+  #define DDRDATA1CH1_CR_TXPERBITRANK3_Lane4_MAX                       (0x0000000F)
+  #define DDRDATA1CH1_CR_TXPERBITRANK3_Lane5_OFF                       (20)
+  #define DDRDATA1CH1_CR_TXPERBITRANK3_Lane5_WID                       ( 4)
+  #define DDRDATA1CH1_CR_TXPERBITRANK3_Lane5_MSK                       (0x00F00000)
+  #define DDRDATA1CH1_CR_TXPERBITRANK3_Lane5_MAX                       (0x0000000F)
+  #define DDRDATA1CH1_CR_TXPERBITRANK3_Lane6_OFF                       (24)
+  #define DDRDATA1CH1_CR_TXPERBITRANK3_Lane6_WID                       ( 4)
+  #define DDRDATA1CH1_CR_TXPERBITRANK3_Lane6_MSK                       (0x0F000000)
+  #define DDRDATA1CH1_CR_TXPERBITRANK3_Lane6_MAX                       (0x0000000F)
+  #define DDRDATA1CH1_CR_TXPERBITRANK3_Lane7_OFF                       (28)
+  #define DDRDATA1CH1_CR_TXPERBITRANK3_Lane7_WID                       ( 4)
+  #define DDRDATA1CH1_CR_TXPERBITRANK3_Lane7_MSK                       (0xF0000000)
+  #define DDRDATA1CH1_CR_TXPERBITRANK3_Lane7_MAX                       (0x0000000F)
+
+#define DDRDATA1CH1_CR_RCOMPDATA0_REG                                (0x00000340)
+  #define DDRDATA1CH1_CR_RCOMPDATA0_RcompDrvUp_OFF                     ( 0)
+  #define DDRDATA1CH1_CR_RCOMPDATA0_RcompDrvUp_WID                     ( 6)
+  #define DDRDATA1CH1_CR_RCOMPDATA0_RcompDrvUp_MSK                     (0x0000003F)
+  #define DDRDATA1CH1_CR_RCOMPDATA0_RcompDrvUp_MAX                     (0x0000003F)
+  #define DDRDATA1CH1_CR_RCOMPDATA0_Spare0_OFF                         ( 6)
+  #define DDRDATA1CH1_CR_RCOMPDATA0_Spare0_WID                         ( 3)
+  #define DDRDATA1CH1_CR_RCOMPDATA0_Spare0_MSK                         (0x000001C0)
+  #define DDRDATA1CH1_CR_RCOMPDATA0_Spare0_MAX                         (0x00000007)
+  #define DDRDATA1CH1_CR_RCOMPDATA0_RcompDrvDown_OFF                   ( 9)
+  #define DDRDATA1CH1_CR_RCOMPDATA0_RcompDrvDown_WID                   ( 6)
+  #define DDRDATA1CH1_CR_RCOMPDATA0_RcompDrvDown_MSK                   (0x00007E00)
+  #define DDRDATA1CH1_CR_RCOMPDATA0_RcompDrvDown_MAX                   (0x0000003F)
+  #define DDRDATA1CH1_CR_RCOMPDATA0_VTComp_OFF                         (15)
+  #define DDRDATA1CH1_CR_RCOMPDATA0_VTComp_WID                         ( 5)
+  #define DDRDATA1CH1_CR_RCOMPDATA0_VTComp_MSK                         (0x000F8000)
+  #define DDRDATA1CH1_CR_RCOMPDATA0_VTComp_MAX                         (0x0000001F)
+  #define DDRDATA1CH1_CR_RCOMPDATA0_TcoComp_OFF                        (20)
+  #define DDRDATA1CH1_CR_RCOMPDATA0_TcoComp_WID                        ( 6)
+  #define DDRDATA1CH1_CR_RCOMPDATA0_TcoComp_MSK                        (0x03F00000)
+  #define DDRDATA1CH1_CR_RCOMPDATA0_TcoComp_MAX                        (0x0000003F)
+  #define DDRDATA1CH1_CR_RCOMPDATA0_SlewRateComp_OFF                   (26)
+  #define DDRDATA1CH1_CR_RCOMPDATA0_SlewRateComp_WID                   ( 5)
+  #define DDRDATA1CH1_CR_RCOMPDATA0_SlewRateComp_MSK                   (0x7C000000)
+  #define DDRDATA1CH1_CR_RCOMPDATA0_SlewRateComp_MAX                   (0x0000001F)
+  #define DDRDATA1CH1_CR_RCOMPDATA0_Spare2_OFF                         (31)
+  #define DDRDATA1CH1_CR_RCOMPDATA0_Spare2_WID                         ( 1)
+  #define DDRDATA1CH1_CR_RCOMPDATA0_Spare2_MSK                         (0x80000000)
+  #define DDRDATA1CH1_CR_RCOMPDATA0_Spare2_MAX                         (0x00000001)
+
+#define DDRDATA1CH1_CR_RCOMPDATA1_REG                                (0x00000344)
+  #define DDRDATA1CH1_CR_RCOMPDATA1_RcompOdtUp_OFF                     ( 0)
+  #define DDRDATA1CH1_CR_RCOMPDATA1_RcompOdtUp_WID                     ( 6)
+  #define DDRDATA1CH1_CR_RCOMPDATA1_RcompOdtUp_MSK                     (0x0000003F)
+  #define DDRDATA1CH1_CR_RCOMPDATA1_RcompOdtUp_MAX                     (0x0000003F)
+  #define DDRDATA1CH1_CR_RCOMPDATA1_Spare0_OFF                         ( 6)
+  #define DDRDATA1CH1_CR_RCOMPDATA1_Spare0_WID                         ( 3)
+  #define DDRDATA1CH1_CR_RCOMPDATA1_Spare0_MSK                         (0x000001C0)
+  #define DDRDATA1CH1_CR_RCOMPDATA1_Spare0_MAX                         (0x00000007)
+  #define DDRDATA1CH1_CR_RCOMPDATA1_RcompOdtDown_OFF                   ( 9)
+  #define DDRDATA1CH1_CR_RCOMPDATA1_RcompOdtDown_WID                   ( 6)
+  #define DDRDATA1CH1_CR_RCOMPDATA1_RcompOdtDown_MSK                   (0x00007E00)
+  #define DDRDATA1CH1_CR_RCOMPDATA1_RcompOdtDown_MAX                   (0x0000003F)
+  #define DDRDATA1CH1_CR_RCOMPDATA1_Spare1_OFF                         (15)
+  #define DDRDATA1CH1_CR_RCOMPDATA1_Spare1_WID                         ( 1)
+  #define DDRDATA1CH1_CR_RCOMPDATA1_Spare1_MSK                         (0x00008000)
+  #define DDRDATA1CH1_CR_RCOMPDATA1_Spare1_MAX                         (0x00000001)
+  #define DDRDATA1CH1_CR_RCOMPDATA1_PanicDrvDn_OFF                     (16)
+  #define DDRDATA1CH1_CR_RCOMPDATA1_PanicDrvDn_WID                     ( 6)
+  #define DDRDATA1CH1_CR_RCOMPDATA1_PanicDrvDn_MSK                     (0x003F0000)
+  #define DDRDATA1CH1_CR_RCOMPDATA1_PanicDrvDn_MAX                     (0x0000003F)
+  #define DDRDATA1CH1_CR_RCOMPDATA1_PanicDrvUp_OFF                     (22)
+  #define DDRDATA1CH1_CR_RCOMPDATA1_PanicDrvUp_WID                     ( 6)
+  #define DDRDATA1CH1_CR_RCOMPDATA1_PanicDrvUp_MSK                     (0x0FC00000)
+  #define DDRDATA1CH1_CR_RCOMPDATA1_PanicDrvUp_MAX                     (0x0000003F)
+  #define DDRDATA1CH1_CR_RCOMPDATA1_LevelShifterComp_OFF               (28)
+  #define DDRDATA1CH1_CR_RCOMPDATA1_LevelShifterComp_WID               ( 3)
+  #define DDRDATA1CH1_CR_RCOMPDATA1_LevelShifterComp_MSK               (0x70000000)
+  #define DDRDATA1CH1_CR_RCOMPDATA1_LevelShifterComp_MAX               (0x00000007)
+  #define DDRDATA1CH1_CR_RCOMPDATA1_Spare2_OFF                         (31)
+  #define DDRDATA1CH1_CR_RCOMPDATA1_Spare2_WID                         ( 1)
+  #define DDRDATA1CH1_CR_RCOMPDATA1_Spare2_MSK                         (0x80000000)
+  #define DDRDATA1CH1_CR_RCOMPDATA1_Spare2_MAX                         (0x00000001)
+
+#define DDRDATA1CH1_CR_TXXTALK_REG                                   (0x00000348)
+  #define DDRDATA1CH1_CR_TXXTALK_Lane0_OFF                             ( 0)
+  #define DDRDATA1CH1_CR_TXXTALK_Lane0_WID                             ( 4)
+  #define DDRDATA1CH1_CR_TXXTALK_Lane0_MSK                             (0x0000000F)
+  #define DDRDATA1CH1_CR_TXXTALK_Lane0_MAX                             (0x0000000F)
+  #define DDRDATA1CH1_CR_TXXTALK_Lane1_OFF                             ( 4)
+  #define DDRDATA1CH1_CR_TXXTALK_Lane1_WID                             ( 4)
+  #define DDRDATA1CH1_CR_TXXTALK_Lane1_MSK                             (0x000000F0)
+  #define DDRDATA1CH1_CR_TXXTALK_Lane1_MAX                             (0x0000000F)
+  #define DDRDATA1CH1_CR_TXXTALK_Lane2_OFF                             ( 8)
+  #define DDRDATA1CH1_CR_TXXTALK_Lane2_WID                             ( 4)
+  #define DDRDATA1CH1_CR_TXXTALK_Lane2_MSK                             (0x00000F00)
+  #define DDRDATA1CH1_CR_TXXTALK_Lane2_MAX                             (0x0000000F)
+  #define DDRDATA1CH1_CR_TXXTALK_Lane3_OFF                             (12)
+  #define DDRDATA1CH1_CR_TXXTALK_Lane3_WID                             ( 4)
+  #define DDRDATA1CH1_CR_TXXTALK_Lane3_MSK                             (0x0000F000)
+  #define DDRDATA1CH1_CR_TXXTALK_Lane3_MAX                             (0x0000000F)
+  #define DDRDATA1CH1_CR_TXXTALK_Lane4_OFF                             (16)
+  #define DDRDATA1CH1_CR_TXXTALK_Lane4_WID                             ( 4)
+  #define DDRDATA1CH1_CR_TXXTALK_Lane4_MSK                             (0x000F0000)
+  #define DDRDATA1CH1_CR_TXXTALK_Lane4_MAX                             (0x0000000F)
+  #define DDRDATA1CH1_CR_TXXTALK_Lane5_OFF                             (20)
+  #define DDRDATA1CH1_CR_TXXTALK_Lane5_WID                             ( 4)
+  #define DDRDATA1CH1_CR_TXXTALK_Lane5_MSK                             (0x00F00000)
+  #define DDRDATA1CH1_CR_TXXTALK_Lane5_MAX                             (0x0000000F)
+  #define DDRDATA1CH1_CR_TXXTALK_Lane6_OFF                             (24)
+  #define DDRDATA1CH1_CR_TXXTALK_Lane6_WID                             ( 4)
+  #define DDRDATA1CH1_CR_TXXTALK_Lane6_MSK                             (0x0F000000)
+  #define DDRDATA1CH1_CR_TXXTALK_Lane6_MAX                             (0x0000000F)
+  #define DDRDATA1CH1_CR_TXXTALK_Lane7_OFF                             (28)
+  #define DDRDATA1CH1_CR_TXXTALK_Lane7_WID                             ( 4)
+  #define DDRDATA1CH1_CR_TXXTALK_Lane7_MSK                             (0xF0000000)
+  #define DDRDATA1CH1_CR_TXXTALK_Lane7_MAX                             (0x0000000F)
+
+#define DDRDATA1CH1_CR_RXOFFSETVDQ_REG                               (0x0000034C)
+  #define DDRDATA1CH1_CR_RXOFFSETVDQ_Lane0_OFF                         ( 0)
+  #define DDRDATA1CH1_CR_RXOFFSETVDQ_Lane0_WID                         ( 4)
+  #define DDRDATA1CH1_CR_RXOFFSETVDQ_Lane0_MSK                         (0x0000000F)
+  #define DDRDATA1CH1_CR_RXOFFSETVDQ_Lane0_MAX                         (0x0000000F)
+  #define DDRDATA1CH1_CR_RXOFFSETVDQ_Lane1_OFF                         ( 4)
+  #define DDRDATA1CH1_CR_RXOFFSETVDQ_Lane1_WID                         ( 4)
+  #define DDRDATA1CH1_CR_RXOFFSETVDQ_Lane1_MSK                         (0x000000F0)
+  #define DDRDATA1CH1_CR_RXOFFSETVDQ_Lane1_MAX                         (0x0000000F)
+  #define DDRDATA1CH1_CR_RXOFFSETVDQ_Lane2_OFF                         ( 8)
+  #define DDRDATA1CH1_CR_RXOFFSETVDQ_Lane2_WID                         ( 4)
+  #define DDRDATA1CH1_CR_RXOFFSETVDQ_Lane2_MSK                         (0x00000F00)
+  #define DDRDATA1CH1_CR_RXOFFSETVDQ_Lane2_MAX                         (0x0000000F)
+  #define DDRDATA1CH1_CR_RXOFFSETVDQ_Lane3_OFF                         (12)
+  #define DDRDATA1CH1_CR_RXOFFSETVDQ_Lane3_WID                         ( 4)
+  #define DDRDATA1CH1_CR_RXOFFSETVDQ_Lane3_MSK                         (0x0000F000)
+  #define DDRDATA1CH1_CR_RXOFFSETVDQ_Lane3_MAX                         (0x0000000F)
+  #define DDRDATA1CH1_CR_RXOFFSETVDQ_Lane4_OFF                         (16)
+  #define DDRDATA1CH1_CR_RXOFFSETVDQ_Lane4_WID                         ( 4)
+  #define DDRDATA1CH1_CR_RXOFFSETVDQ_Lane4_MSK                         (0x000F0000)
+  #define DDRDATA1CH1_CR_RXOFFSETVDQ_Lane4_MAX                         (0x0000000F)
+  #define DDRDATA1CH1_CR_RXOFFSETVDQ_Lane5_OFF                         (20)
+  #define DDRDATA1CH1_CR_RXOFFSETVDQ_Lane5_WID                         ( 4)
+  #define DDRDATA1CH1_CR_RXOFFSETVDQ_Lane5_MSK                         (0x00F00000)
+  #define DDRDATA1CH1_CR_RXOFFSETVDQ_Lane5_MAX                         (0x0000000F)
+  #define DDRDATA1CH1_CR_RXOFFSETVDQ_Lane6_OFF                         (24)
+  #define DDRDATA1CH1_CR_RXOFFSETVDQ_Lane6_WID                         ( 4)
+  #define DDRDATA1CH1_CR_RXOFFSETVDQ_Lane6_MSK                         (0x0F000000)
+  #define DDRDATA1CH1_CR_RXOFFSETVDQ_Lane6_MAX                         (0x0000000F)
+  #define DDRDATA1CH1_CR_RXOFFSETVDQ_Lane7_OFF                         (28)
+  #define DDRDATA1CH1_CR_RXOFFSETVDQ_Lane7_WID                         ( 4)
+  #define DDRDATA1CH1_CR_RXOFFSETVDQ_Lane7_MSK                         (0xF0000000)
+  #define DDRDATA1CH1_CR_RXOFFSETVDQ_Lane7_MAX                         (0x0000000F)
+
+#define DDRDATA1CH1_CR_DDRDATARESERVED_REG                           (0x00000350)
+  #define DDRDATA1CH1_CR_DDRDATARESERVED_Spare_OFF                     ( 0)
+  #define DDRDATA1CH1_CR_DDRDATARESERVED_Spare_WID                     (32)
+  #define DDRDATA1CH1_CR_DDRDATARESERVED_Spare_MSK                     (0xFFFFFFFF)
+  #define DDRDATA1CH1_CR_DDRDATARESERVED_Spare_MAX                     (0xFFFFFFFF)
+
+#define DDRDATA1CH1_CR_DATATRAINFEEDBACK_REG                         (0x00000354)
+  #define DDRDATA1CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_OFF       ( 0)
+  #define DDRDATA1CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_WID       ( 9)
+  #define DDRDATA1CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_MSK       (0x000001FF)
+  #define DDRDATA1CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_MAX       (0x000001FF)
+  #define DDRDATA1CH1_CR_DATATRAINFEEDBACK_Spare_OFF                   ( 9)
+  #define DDRDATA1CH1_CR_DATATRAINFEEDBACK_Spare_WID                   (23)
+  #define DDRDATA1CH1_CR_DATATRAINFEEDBACK_Spare_MSK                   (0xFFFFFE00)
+  #define DDRDATA1CH1_CR_DATATRAINFEEDBACK_Spare_MAX                   (0x007FFFFF)
+
+#define DDRDATA1CH1_CR_DLLPITESTANDADC_REG                           (0x00000358)
+  #define DDRDATA1CH1_CR_DLLPITESTANDADC_RunTest_OFF                   ( 0)
+  #define DDRDATA1CH1_CR_DLLPITESTANDADC_RunTest_WID                   ( 1)
+  #define DDRDATA1CH1_CR_DLLPITESTANDADC_RunTest_MSK                   (0x00000001)
+  #define DDRDATA1CH1_CR_DLLPITESTANDADC_RunTest_MAX                   (0x00000001)
+  #define DDRDATA1CH1_CR_DLLPITESTANDADC_RunTest_DEF                   (0x00000000)
+  #define DDRDATA1CH1_CR_DLLPITESTANDADC_Load_OFF                      ( 1)
+  #define DDRDATA1CH1_CR_DLLPITESTANDADC_Load_WID                      ( 1)
+  #define DDRDATA1CH1_CR_DLLPITESTANDADC_Load_MSK                      (0x00000002)
+  #define DDRDATA1CH1_CR_DLLPITESTANDADC_Load_MAX                      (0x00000001)
+  #define DDRDATA1CH1_CR_DLLPITESTANDADC_Load_DEF                      (0x00000000)
+  #define DDRDATA1CH1_CR_DLLPITESTANDADC_ModeHVM_OFF                   ( 2)
+  #define DDRDATA1CH1_CR_DLLPITESTANDADC_ModeHVM_WID                   ( 1)
+  #define DDRDATA1CH1_CR_DLLPITESTANDADC_ModeHVM_MSK                   (0x00000004)
+  #define DDRDATA1CH1_CR_DLLPITESTANDADC_ModeHVM_MAX                   (0x00000001)
+  #define DDRDATA1CH1_CR_DLLPITESTANDADC_ModeHVM_DEF                   (0x00000000)
+  #define DDRDATA1CH1_CR_DLLPITESTANDADC_ModeDV_OFF                    ( 3)
+  #define DDRDATA1CH1_CR_DLLPITESTANDADC_ModeDV_WID                    ( 1)
+  #define DDRDATA1CH1_CR_DLLPITESTANDADC_ModeDV_MSK                    (0x00000008)
+  #define DDRDATA1CH1_CR_DLLPITESTANDADC_ModeDV_MAX                    (0x00000001)
+  #define DDRDATA1CH1_CR_DLLPITESTANDADC_ModeDV_DEF                    (0x00000000)
+  #define DDRDATA1CH1_CR_DLLPITESTANDADC_ModeADC_OFF                   ( 4)
+  #define DDRDATA1CH1_CR_DLLPITESTANDADC_ModeADC_WID                   ( 1)
+  #define DDRDATA1CH1_CR_DLLPITESTANDADC_ModeADC_MSK                   (0x00000010)
+  #define DDRDATA1CH1_CR_DLLPITESTANDADC_ModeADC_MAX                   (0x00000001)
+  #define DDRDATA1CH1_CR_DLLPITESTANDADC_ModeADC_DEF                   (0x00000000)
+  #define DDRDATA1CH1_CR_DLLPITESTANDADC_LoadCount_OFF                 ( 5)
+  #define DDRDATA1CH1_CR_DLLPITESTANDADC_LoadCount_WID                 (10)
+  #define DDRDATA1CH1_CR_DLLPITESTANDADC_LoadCount_MSK                 (0x00007FE0)
+  #define DDRDATA1CH1_CR_DLLPITESTANDADC_LoadCount_MAX                 (0x000003FF)
+  #define DDRDATA1CH1_CR_DLLPITESTANDADC_CountStatus_OFF               (15)
+  #define DDRDATA1CH1_CR_DLLPITESTANDADC_CountStatus_WID               (10)
+  #define DDRDATA1CH1_CR_DLLPITESTANDADC_CountStatus_MSK               (0x01FF8000)
+  #define DDRDATA1CH1_CR_DLLPITESTANDADC_CountStatus_MAX               (0x000003FF)
+  #define DDRDATA1CH1_CR_DLLPITESTANDADC_CountStatus_DEF               (0x00000000)
+  #define DDRDATA1CH1_CR_DLLPITESTANDADC_Spare_OFF                     (25)
+  #define DDRDATA1CH1_CR_DLLPITESTANDADC_Spare_WID                     ( 7)
+  #define DDRDATA1CH1_CR_DLLPITESTANDADC_Spare_MSK                     (0xFE000000)
+  #define DDRDATA1CH1_CR_DLLPITESTANDADC_Spare_MAX                     (0x0000007F)
+
+#define DDRDATA1CH1_CR_DDRCRDATAOFFSETCOMP_REG                       (0x0000035C)
+  #define DDRDATA1CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_OFF     ( 0)
+  #define DDRDATA1CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_WID     ( 6)
+  #define DDRDATA1CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MSK     (0x0000003F)
+  #define DDRDATA1CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MAX     (0x0000003F)
+  #define DDRDATA1CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_DEF     (0x00000000)
+  #define DDRDATA1CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_OFF   ( 6)
+  #define DDRDATA1CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_WID   ( 6)
+  #define DDRDATA1CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MSK   (0x00000FC0)
+  #define DDRDATA1CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MAX   (0x0000003F)
+  #define DDRDATA1CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_DEF   (0x00000000)
+  #define DDRDATA1CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_OFF     (12)
+  #define DDRDATA1CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_WID     ( 5)
+  #define DDRDATA1CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MSK     (0x0001F000)
+  #define DDRDATA1CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MAX     (0x0000001F)
+  #define DDRDATA1CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_DEF     (0x00000000)
+  #define DDRDATA1CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_OFF   (17)
+  #define DDRDATA1CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_WID   ( 5)
+  #define DDRDATA1CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MSK   (0x003E0000)
+  #define DDRDATA1CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MAX   (0x0000001F)
+  #define DDRDATA1CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_DEF   (0x00000000)
+  #define DDRDATA1CH1_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_OFF       (22)
+  #define DDRDATA1CH1_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_WID       ( 5)
+  #define DDRDATA1CH1_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_MSK       (0x07C00000)
+  #define DDRDATA1CH1_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_MAX       (0x0000001F)
+  #define DDRDATA1CH1_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_DEF       (0x00000000)
+  #define DDRDATA1CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_OFF  (27)
+  #define DDRDATA1CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_WID  ( 5)
+  #define DDRDATA1CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MSK  (0xF8000000)
+  #define DDRDATA1CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MAX  (0x0000001F)
+  #define DDRDATA1CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_DEF  (0x00000000)
+
+#define DDRDATA1CH1_CR_DDRCRDATACONTROL1_REG                         (0x00000360)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_RefPi_OFF                   ( 0)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_RefPi_WID                   ( 4)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_RefPi_MSK                   (0x0000000F)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_RefPi_MAX                   (0x0000000F)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_RefPi_DEF                   (0x00000000)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_DllMask_OFF                 ( 4)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_DllMask_WID                 ( 2)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_DllMask_MSK                 (0x00000030)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_DllMask_MAX                 (0x00000003)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_DllMask_DEF                 (0x00000000)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_DllWeakLock_OFF             ( 6)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_DllWeakLock_WID             ( 1)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_DllWeakLock_MSK             (0x00000040)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_DllWeakLock_MAX             (0x00000001)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_DllWeakLock_DEF             (0x00000000)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_OFF      ( 7)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_WID      ( 3)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MSK      (0x00000380)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MAX      (0x00000007)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_DEF      (0x00000000)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_OFF               (10)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_WID               ( 3)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_MSK               (0x00001C00)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_MAX               (0x00000007)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_DEF               (0x00000000)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_OdtDelay_OFF                (13)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_OdtDelay_WID                ( 4)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_OdtDelay_MSK                (0x0001E000)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_OdtDelay_MAX                (0x0000000F)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_OdtDelay_DEF                (0x00000000)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_OdtDuration_OFF             (17)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_OdtDuration_WID             ( 3)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_OdtDuration_MSK             (0x000E0000)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_OdtDuration_MAX             (0x00000007)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_OdtDuration_DEF             (0x00000000)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_OFF           (20)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_WID           ( 4)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_MSK           (0x00F00000)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_MAX           (0x0000000F)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_DEF           (0x00000000)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_OFF        (24)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_WID        ( 3)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_MSK        (0x07000000)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_MAX        (0x00000007)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_DEF        (0x00000000)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_BurstEndODTDelay_OFF        (27)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_BurstEndODTDelay_WID        ( 3)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_BurstEndODTDelay_MSK        (0x38000000)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_BurstEndODTDelay_MAX        (0x00000007)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_BurstEndODTDelay_DEF        (0x00000000)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_OFF          (30)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_WID          ( 1)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_MSK          (0x40000000)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_MAX          (0x00000001)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_DEF          (0x00000000)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_Rsvd1_OFF                   (31)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_Rsvd1_WID                   ( 1)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_Rsvd1_MSK                   (0x80000000)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_Rsvd1_MAX                   (0x00000001)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_Rsvd1_DEF                   (0x00000000)
+
+#define DDRDATA1CH1_CR_DDRCRDATACONTROL2_REG                         (0x00000364)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_OFF            ( 0)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_WID            ( 5)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_MSK            (0x0000001F)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_MAX            (0x0000001F)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_DEF            (0x00000000)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_OFF             ( 5)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_WID             ( 1)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_MSK             (0x00000020)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_MAX             (0x00000001)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_DEF             (0x00000000)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_ForceRxOn_OFF               ( 6)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_ForceRxOn_WID               ( 1)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_ForceRxOn_MSK               (0x00000040)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_ForceRxOn_MAX               (0x00000001)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_ForceRxOn_DEF               (0x00000000)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_LeakerComp_OFF              ( 7)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_LeakerComp_WID              ( 2)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_LeakerComp_MSK              (0x00000180)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_LeakerComp_MAX              (0x00000003)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_LeakerComp_DEF              (0x00000000)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_OFF          ( 9)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_WID          ( 4)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_MSK          (0x00001E00)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_MAX          (0x0000000F)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_DEF          (0x00000008)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_OFF             (13)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_WID             ( 5)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_MSK             (0x0003E000)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_MAX             (0x0000001F)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_DEF             (0x00000011)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_OFF             (18)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_WID             ( 1)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_MSK             (0x00040000)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_MAX             (0x00000001)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_DEF             (0x00000000)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_Spare_OFF                   (19)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_Spare_WID                   (13)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_Spare_MSK                   (0xFFF80000)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_Spare_MAX                   (0x00001FFF)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_Spare_DEF                   (0x00000000)
+
+#define DDRDATA1CH1_CR_DDRCRVSSHIORVREFCONTROL_REG                   (0x0000036C)
+  #define DDRDATA1CH1_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_OFF    ( 0)
+  #define DDRDATA1CH1_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_WID    (24)
+  #define DDRDATA1CH1_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_MSK    (0x00FFFFFF)
+  #define DDRDATA1CH1_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_MAX    (0x00FFFFFF)
+  #define DDRDATA1CH1_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_DEF    (0x00000000)
+  #define DDRDATA1CH1_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_OFF        (24)
+  #define DDRDATA1CH1_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_WID        ( 8)
+  #define DDRDATA1CH1_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_MSK        (0xFF000000)
+  #define DDRDATA1CH1_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_MAX        (0x000000FF)
+  #define DDRDATA1CH1_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_DEF        (0x00000000)
+
+#define DDRDATA1CH1_CR_DDRCRDATAOFFSETTRAIN_REG                      (0x00000370)
+  #define DDRDATA1CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_OFF          ( 0)
+  #define DDRDATA1CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_WID          ( 6)
+  #define DDRDATA1CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MSK          (0x0000003F)
+  #define DDRDATA1CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MAX          (0x0000003F)
+  #define DDRDATA1CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_DEF          (0x00000000)
+  #define DDRDATA1CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_OFF          ( 6)
+  #define DDRDATA1CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_WID          ( 6)
+  #define DDRDATA1CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MSK          (0x00000FC0)
+  #define DDRDATA1CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MAX          (0x0000003F)
+  #define DDRDATA1CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_DEF          (0x00000000)
+  #define DDRDATA1CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_OFF           (12)
+  #define DDRDATA1CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_WID           ( 6)
+  #define DDRDATA1CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MSK           (0x0003F000)
+  #define DDRDATA1CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MAX           (0x0000003F)
+  #define DDRDATA1CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_DEF           (0x00000000)
+  #define DDRDATA1CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_OFF          (18)
+  #define DDRDATA1CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_WID          ( 6)
+  #define DDRDATA1CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MSK          (0x00FC0000)
+  #define DDRDATA1CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MAX          (0x0000003F)
+  #define DDRDATA1CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_DEF          (0x00000000)
+  #define DDRDATA1CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_OFF           (24)
+  #define DDRDATA1CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_WID           ( 7)
+  #define DDRDATA1CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MSK           (0x7F000000)
+  #define DDRDATA1CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MAX           (0x0000007F)
+  #define DDRDATA1CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_DEF           (0x00000000)
+  #define DDRDATA1CH1_CR_DDRCRDATAOFFSETTRAIN_Spare_OFF                (31)
+  #define DDRDATA1CH1_CR_DDRCRDATAOFFSETTRAIN_Spare_WID                ( 1)
+  #define DDRDATA1CH1_CR_DDRCRDATAOFFSETTRAIN_Spare_MSK                (0x80000000)
+  #define DDRDATA1CH1_CR_DDRCRDATAOFFSETTRAIN_Spare_MAX                (0x00000001)
+  #define DDRDATA1CH1_CR_DDRCRDATAOFFSETTRAIN_Spare_DEF                (0x00000000)
+
+#define DDRDATA1CH1_CR_DDRCRDATACONTROL0_REG                         (0x00000374)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_OFF          ( 0)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_WID          ( 1)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_MSK          (0x00000001)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_MAX          (0x00000001)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_DEF          (0x00000000)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_OFF          ( 1)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_WID          ( 1)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_MSK          (0x00000002)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_MAX          (0x00000001)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_DEF          (0x00000000)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_OFF          ( 2)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_WID          ( 1)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_MSK          (0x00000004)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_MAX          (0x00000001)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_DEF          (0x00000000)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_OFF    ( 3)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_WID    ( 1)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MSK    (0x00000008)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MAX    (0x00000001)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_DEF    (0x00000000)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_TxOn_OFF                    ( 4)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_TxOn_WID                    ( 1)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_TxOn_MSK                    (0x00000010)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_TxOn_MAX                    (0x00000001)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_TxOn_DEF                    (0x00000000)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RfOn_OFF                    ( 5)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RfOn_WID                    ( 1)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RfOn_MSK                    (0x00000020)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RfOn_MAX                    (0x00000001)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RfOn_DEF                    (0x00000000)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RxPiOn_OFF                  ( 6)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RxPiOn_WID                  ( 1)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RxPiOn_MSK                  (0x00000040)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RxPiOn_MAX                  (0x00000001)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RxPiOn_DEF                  (0x00000000)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_TxPiOn_OFF                  ( 7)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_TxPiOn_WID                  ( 1)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_TxPiOn_MSK                  (0x00000080)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_TxPiOn_MAX                  (0x00000001)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_TxPiOn_DEF                  (0x00000000)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_OFF        ( 8)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_WID        ( 1)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_MSK        (0x00000100)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_MAX        (0x00000001)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_DEF        (0x00000000)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_OFF        ( 9)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_WID        ( 1)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MSK        (0x00000200)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MAX        (0x00000001)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_DEF        (0x00000000)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_TxDisable_OFF               (10)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_TxDisable_WID               ( 1)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_TxDisable_MSK               (0x00000400)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_TxDisable_MAX               (0x00000001)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_TxDisable_DEF               (0x00000000)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RxDisable_OFF               (11)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RxDisable_WID               ( 1)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RxDisable_MSK               (0x00000800)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RxDisable_MAX               (0x00000001)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RxDisable_DEF               (0x00000000)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_TxLong_OFF                  (12)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_TxLong_WID                  ( 1)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_TxLong_MSK                  (0x00001000)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_TxLong_MAX                  (0x00000001)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_TxLong_DEF                  (0x00000000)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_OFF               (13)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_WID               ( 2)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_MSK               (0x00006000)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_MAX               (0x00000003)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_DEF               (0x00000000)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RxReadPointer_OFF           (15)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RxReadPointer_WID           ( 3)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RxReadPointer_MSK           (0x00038000)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RxReadPointer_MAX           (0x00000007)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RxReadPointer_DEF           (0x00000000)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_DriverSegmentEnable_OFF     (18)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_DriverSegmentEnable_WID     ( 1)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_DriverSegmentEnable_MSK     (0x00040000)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_DriverSegmentEnable_MAX     (0x00000001)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_DriverSegmentEnable_DEF     (0x00000000)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_DataVccddqHi_OFF            (19)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_DataVccddqHi_WID            ( 1)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_DataVccddqHi_MSK            (0x00080000)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_DataVccddqHi_MAX            (0x00000001)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_DataVccddqHi_DEF            (0x00000000)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_ReadRFRd_OFF                (20)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_ReadRFRd_WID                ( 1)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_ReadRFRd_MSK                (0x00100000)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_ReadRFRd_MAX                (0x00000001)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_ReadRFRd_DEF                (0x00000000)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_ReadRFWr_OFF                (21)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_ReadRFWr_WID                ( 1)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_ReadRFWr_MSK                (0x00200000)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_ReadRFWr_MAX                (0x00000001)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_ReadRFWr_DEF                (0x00000000)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_ReadRFRank_OFF              (22)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_ReadRFRank_WID              ( 2)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_ReadRFRank_MSK              (0x00C00000)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_ReadRFRank_MAX              (0x00000003)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_ReadRFRank_DEF              (0x00000000)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_OFF              (24)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_WID              ( 1)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_MSK              (0x01000000)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_MAX              (0x00000001)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_DEF              (0x00000000)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_OdtSampOff_OFF              (25)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_OdtSampOff_WID              ( 1)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_OdtSampOff_MSK              (0x02000000)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_OdtSampOff_MAX              (0x00000001)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_OdtSampOff_DEF              (0x00000000)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_OFF        (26)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_WID        ( 1)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_MSK        (0x04000000)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_MAX        (0x00000001)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_DEF        (0x00000000)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_OFF         (27)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_WID         ( 1)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MSK         (0x08000000)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MAX         (0x00000001)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_DEF         (0x00000000)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_OFF              (28)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_WID              ( 1)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_MSK              (0x10000000)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_MAX              (0x00000001)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_DEF              (0x00000000)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_EnReadPreamble_OFF          (29)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_EnReadPreamble_WID          ( 1)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_EnReadPreamble_MSK          (0x20000000)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_EnReadPreamble_MAX          (0x00000001)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_EnReadPreamble_DEF          (0x00000000)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_OFF         (30)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_WID         ( 1)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MSK         (0x40000000)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MAX         (0x00000001)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_DEF         (0x00000000)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_OFF            (31)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_WID            ( 1)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_MSK            (0x80000000)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_MAX            (0x00000001)
+  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_DEF            (0x00000000)
+
+#define DDRDATA1CH1_CR_DDRCRVREFADJUST1_REG                          (0x00000378)
+  #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_CAVrefCtl_OFF                ( 0)
+  #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_CAVrefCtl_WID                ( 7)
+  #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_CAVrefCtl_MSK                (0x0000007F)
+  #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_CAVrefCtl_MAX                (0x0000007F)
+  #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_CAVrefCtl_DEF                (0x00000000)
+  #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_Ch1VrefCtl_OFF               ( 7)
+  #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_Ch1VrefCtl_WID               ( 7)
+  #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_Ch1VrefCtl_MSK               (0x00003F80)
+  #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_Ch1VrefCtl_MAX               (0x0000007F)
+  #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_Ch1VrefCtl_DEF               (0x00000000)
+  #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_Ch0VrefCtl_OFF               (14)
+  #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_Ch0VrefCtl_WID               ( 7)
+  #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_Ch0VrefCtl_MSK               (0x001FC000)
+  #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_Ch0VrefCtl_MAX               (0x0000007F)
+  #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_Ch0VrefCtl_DEF               (0x00000000)
+  #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCA_OFF             (21)
+  #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCA_WID             ( 1)
+  #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCA_MSK             (0x00200000)
+  #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCA_MAX             (0x00000001)
+  #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCA_DEF             (0x00000000)
+  #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_OFF            (22)
+  #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_WID            ( 1)
+  #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_MSK            (0x00400000)
+  #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_MAX            (0x00000001)
+  #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_DEF            (0x00000000)
+  #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_OFF            (23)
+  #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_WID            ( 1)
+  #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_MSK            (0x00800000)
+  #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_MAX            (0x00000001)
+  #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_DEF            (0x00000000)
+  #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_HiZTimerCtrl_OFF             (24)
+  #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_HiZTimerCtrl_WID             ( 2)
+  #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_HiZTimerCtrl_MSK             (0x03000000)
+  #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_HiZTimerCtrl_MAX             (0x00000003)
+  #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_HiZTimerCtrl_DEF             (0x00000000)
+  #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_OFF            (26)
+  #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_WID            ( 1)
+  #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_MSK            (0x04000000)
+  #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_MAX            (0x00000001)
+  #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_DEF            (0x00000000)
+  #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_Rsvd_OFF                     (27)
+  #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_Rsvd_WID                     ( 2)
+  #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_Rsvd_MSK                     (0x18000000)
+  #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_Rsvd_MAX                     (0x00000003)
+  #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_Rsvd_DEF                     (0x00000000)
+  #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_caSlowBW_OFF                 (29)
+  #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_caSlowBW_WID                 ( 1)
+  #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_caSlowBW_MSK                 (0x20000000)
+  #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_caSlowBW_MAX                 (0x00000001)
+  #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_caSlowBW_DEF                 (0x00000000)
+  #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_ch0SlowBW_OFF                (30)
+  #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_ch0SlowBW_WID                ( 1)
+  #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_ch0SlowBW_MSK                (0x40000000)
+  #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_ch0SlowBW_MAX                (0x00000001)
+  #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_ch0SlowBW_DEF                (0x00000000)
+  #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_ch1SlowBW_OFF                (31)
+  #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_ch1SlowBW_WID                ( 1)
+  #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_ch1SlowBW_MSK                (0x80000000)
+  #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_ch1SlowBW_MAX                (0x00000001)
+  #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_ch1SlowBW_DEF                (0x00000000)
+
+#define DDRDATA2CH0_CR_RXTRAINRANK0_REG                              (0x00000400)
+  #define DDRDATA2CH0_CR_RXTRAINRANK0_RxRcvEnPi_OFF                    ( 0)
+  #define DDRDATA2CH0_CR_RXTRAINRANK0_RxRcvEnPi_WID                    ( 9)
+  #define DDRDATA2CH0_CR_RXTRAINRANK0_RxRcvEnPi_MSK                    (0x000001FF)
+  #define DDRDATA2CH0_CR_RXTRAINRANK0_RxRcvEnPi_MAX                    (0x000001FF)
+  #define DDRDATA2CH0_CR_RXTRAINRANK0_RxDqsPPi_OFF                     ( 9)
+  #define DDRDATA2CH0_CR_RXTRAINRANK0_RxDqsPPi_WID                     ( 6)
+  #define DDRDATA2CH0_CR_RXTRAINRANK0_RxDqsPPi_MSK                     (0x00007E00)
+  #define DDRDATA2CH0_CR_RXTRAINRANK0_RxDqsPPi_MAX                     (0x0000003F)
+  #define DDRDATA2CH0_CR_RXTRAINRANK0_RxEq_OFF                         (15)
+  #define DDRDATA2CH0_CR_RXTRAINRANK0_RxEq_WID                         ( 5)
+  #define DDRDATA2CH0_CR_RXTRAINRANK0_RxEq_MSK                         (0x000F8000)
+  #define DDRDATA2CH0_CR_RXTRAINRANK0_RxEq_MAX                         (0x0000001F)
+  #define DDRDATA2CH0_CR_RXTRAINRANK0_RxDqsNPi_OFF                     (20)
+  #define DDRDATA2CH0_CR_RXTRAINRANK0_RxDqsNPi_WID                     ( 6)
+  #define DDRDATA2CH0_CR_RXTRAINRANK0_RxDqsNPi_MSK                     (0x03F00000)
+  #define DDRDATA2CH0_CR_RXTRAINRANK0_RxDqsNPi_MAX                     (0x0000003F)
+  #define DDRDATA2CH0_CR_RXTRAINRANK0_RxVref_OFF                       (26)
+  #define DDRDATA2CH0_CR_RXTRAINRANK0_RxVref_WID                       ( 6)
+  #define DDRDATA2CH0_CR_RXTRAINRANK0_RxVref_MSK                       (0xFC000000)
+  #define DDRDATA2CH0_CR_RXTRAINRANK0_RxVref_MAX                       (0x0000003F)
+
+#define DDRDATA2CH0_CR_RXTRAINRANK1_REG                              (0x00000404)
+  #define DDRDATA2CH0_CR_RXTRAINRANK1_RxRcvEnPi_OFF                    ( 0)
+  #define DDRDATA2CH0_CR_RXTRAINRANK1_RxRcvEnPi_WID                    ( 9)
+  #define DDRDATA2CH0_CR_RXTRAINRANK1_RxRcvEnPi_MSK                    (0x000001FF)
+  #define DDRDATA2CH0_CR_RXTRAINRANK1_RxRcvEnPi_MAX                    (0x000001FF)
+  #define DDRDATA2CH0_CR_RXTRAINRANK1_RxDqsPPi_OFF                     ( 9)
+  #define DDRDATA2CH0_CR_RXTRAINRANK1_RxDqsPPi_WID                     ( 6)
+  #define DDRDATA2CH0_CR_RXTRAINRANK1_RxDqsPPi_MSK                     (0x00007E00)
+  #define DDRDATA2CH0_CR_RXTRAINRANK1_RxDqsPPi_MAX                     (0x0000003F)
+  #define DDRDATA2CH0_CR_RXTRAINRANK1_RxEq_OFF                         (15)
+  #define DDRDATA2CH0_CR_RXTRAINRANK1_RxEq_WID                         ( 5)
+  #define DDRDATA2CH0_CR_RXTRAINRANK1_RxEq_MSK                         (0x000F8000)
+  #define DDRDATA2CH0_CR_RXTRAINRANK1_RxEq_MAX                         (0x0000001F)
+  #define DDRDATA2CH0_CR_RXTRAINRANK1_RxDqsNPi_OFF                     (20)
+  #define DDRDATA2CH0_CR_RXTRAINRANK1_RxDqsNPi_WID                     ( 6)
+  #define DDRDATA2CH0_CR_RXTRAINRANK1_RxDqsNPi_MSK                     (0x03F00000)
+  #define DDRDATA2CH0_CR_RXTRAINRANK1_RxDqsNPi_MAX                     (0x0000003F)
+  #define DDRDATA2CH0_CR_RXTRAINRANK1_RxVref_OFF                       (26)
+  #define DDRDATA2CH0_CR_RXTRAINRANK1_RxVref_WID                       ( 6)
+  #define DDRDATA2CH0_CR_RXTRAINRANK1_RxVref_MSK                       (0xFC000000)
+  #define DDRDATA2CH0_CR_RXTRAINRANK1_RxVref_MAX                       (0x0000003F)
+
+#define DDRDATA2CH0_CR_RXTRAINRANK2_REG                              (0x00000408)
+  #define DDRDATA2CH0_CR_RXTRAINRANK2_RxRcvEnPi_OFF                    ( 0)
+  #define DDRDATA2CH0_CR_RXTRAINRANK2_RxRcvEnPi_WID                    ( 9)
+  #define DDRDATA2CH0_CR_RXTRAINRANK2_RxRcvEnPi_MSK                    (0x000001FF)
+  #define DDRDATA2CH0_CR_RXTRAINRANK2_RxRcvEnPi_MAX                    (0x000001FF)
+  #define DDRDATA2CH0_CR_RXTRAINRANK2_RxDqsPPi_OFF                     ( 9)
+  #define DDRDATA2CH0_CR_RXTRAINRANK2_RxDqsPPi_WID                     ( 6)
+  #define DDRDATA2CH0_CR_RXTRAINRANK2_RxDqsPPi_MSK                     (0x00007E00)
+  #define DDRDATA2CH0_CR_RXTRAINRANK2_RxDqsPPi_MAX                     (0x0000003F)
+  #define DDRDATA2CH0_CR_RXTRAINRANK2_RxEq_OFF                         (15)
+  #define DDRDATA2CH0_CR_RXTRAINRANK2_RxEq_WID                         ( 5)
+  #define DDRDATA2CH0_CR_RXTRAINRANK2_RxEq_MSK                         (0x000F8000)
+  #define DDRDATA2CH0_CR_RXTRAINRANK2_RxEq_MAX                         (0x0000001F)
+  #define DDRDATA2CH0_CR_RXTRAINRANK2_RxDqsNPi_OFF                     (20)
+  #define DDRDATA2CH0_CR_RXTRAINRANK2_RxDqsNPi_WID                     ( 6)
+  #define DDRDATA2CH0_CR_RXTRAINRANK2_RxDqsNPi_MSK                     (0x03F00000)
+  #define DDRDATA2CH0_CR_RXTRAINRANK2_RxDqsNPi_MAX                     (0x0000003F)
+  #define DDRDATA2CH0_CR_RXTRAINRANK2_RxVref_OFF                       (26)
+  #define DDRDATA2CH0_CR_RXTRAINRANK2_RxVref_WID                       ( 6)
+  #define DDRDATA2CH0_CR_RXTRAINRANK2_RxVref_MSK                       (0xFC000000)
+  #define DDRDATA2CH0_CR_RXTRAINRANK2_RxVref_MAX                       (0x0000003F)
+
+#define DDRDATA2CH0_CR_RXTRAINRANK3_REG                              (0x0000040C)
+  #define DDRDATA2CH0_CR_RXTRAINRANK3_RxRcvEnPi_OFF                    ( 0)
+  #define DDRDATA2CH0_CR_RXTRAINRANK3_RxRcvEnPi_WID                    ( 9)
+  #define DDRDATA2CH0_CR_RXTRAINRANK3_RxRcvEnPi_MSK                    (0x000001FF)
+  #define DDRDATA2CH0_CR_RXTRAINRANK3_RxRcvEnPi_MAX                    (0x000001FF)
+  #define DDRDATA2CH0_CR_RXTRAINRANK3_RxDqsPPi_OFF                     ( 9)
+  #define DDRDATA2CH0_CR_RXTRAINRANK3_RxDqsPPi_WID                     ( 6)
+  #define DDRDATA2CH0_CR_RXTRAINRANK3_RxDqsPPi_MSK                     (0x00007E00)
+  #define DDRDATA2CH0_CR_RXTRAINRANK3_RxDqsPPi_MAX                     (0x0000003F)
+  #define DDRDATA2CH0_CR_RXTRAINRANK3_RxEq_OFF                         (15)
+  #define DDRDATA2CH0_CR_RXTRAINRANK3_RxEq_WID                         ( 5)
+  #define DDRDATA2CH0_CR_RXTRAINRANK3_RxEq_MSK                         (0x000F8000)
+  #define DDRDATA2CH0_CR_RXTRAINRANK3_RxEq_MAX                         (0x0000001F)
+  #define DDRDATA2CH0_CR_RXTRAINRANK3_RxDqsNPi_OFF                     (20)
+  #define DDRDATA2CH0_CR_RXTRAINRANK3_RxDqsNPi_WID                     ( 6)
+  #define DDRDATA2CH0_CR_RXTRAINRANK3_RxDqsNPi_MSK                     (0x03F00000)
+  #define DDRDATA2CH0_CR_RXTRAINRANK3_RxDqsNPi_MAX                     (0x0000003F)
+  #define DDRDATA2CH0_CR_RXTRAINRANK3_RxVref_OFF                       (26)
+  #define DDRDATA2CH0_CR_RXTRAINRANK3_RxVref_WID                       ( 6)
+  #define DDRDATA2CH0_CR_RXTRAINRANK3_RxVref_MSK                       (0xFC000000)
+  #define DDRDATA2CH0_CR_RXTRAINRANK3_RxVref_MAX                       (0x0000003F)
+
+#define DDRDATA2CH0_CR_RXPERBITRANK0_REG                             (0x00000410)
+  #define DDRDATA2CH0_CR_RXPERBITRANK0_Lane0_OFF                       ( 0)
+  #define DDRDATA2CH0_CR_RXPERBITRANK0_Lane0_WID                       ( 4)
+  #define DDRDATA2CH0_CR_RXPERBITRANK0_Lane0_MSK                       (0x0000000F)
+  #define DDRDATA2CH0_CR_RXPERBITRANK0_Lane0_MAX                       (0x0000000F)
+  #define DDRDATA2CH0_CR_RXPERBITRANK0_Lane1_OFF                       ( 4)
+  #define DDRDATA2CH0_CR_RXPERBITRANK0_Lane1_WID                       ( 4)
+  #define DDRDATA2CH0_CR_RXPERBITRANK0_Lane1_MSK                       (0x000000F0)
+  #define DDRDATA2CH0_CR_RXPERBITRANK0_Lane1_MAX                       (0x0000000F)
+  #define DDRDATA2CH0_CR_RXPERBITRANK0_Lane2_OFF                       ( 8)
+  #define DDRDATA2CH0_CR_RXPERBITRANK0_Lane2_WID                       ( 4)
+  #define DDRDATA2CH0_CR_RXPERBITRANK0_Lane2_MSK                       (0x00000F00)
+  #define DDRDATA2CH0_CR_RXPERBITRANK0_Lane2_MAX                       (0x0000000F)
+  #define DDRDATA2CH0_CR_RXPERBITRANK0_Lane3_OFF                       (12)
+  #define DDRDATA2CH0_CR_RXPERBITRANK0_Lane3_WID                       ( 4)
+  #define DDRDATA2CH0_CR_RXPERBITRANK0_Lane3_MSK                       (0x0000F000)
+  #define DDRDATA2CH0_CR_RXPERBITRANK0_Lane3_MAX                       (0x0000000F)
+  #define DDRDATA2CH0_CR_RXPERBITRANK0_Lane4_OFF                       (16)
+  #define DDRDATA2CH0_CR_RXPERBITRANK0_Lane4_WID                       ( 4)
+  #define DDRDATA2CH0_CR_RXPERBITRANK0_Lane4_MSK                       (0x000F0000)
+  #define DDRDATA2CH0_CR_RXPERBITRANK0_Lane4_MAX                       (0x0000000F)
+  #define DDRDATA2CH0_CR_RXPERBITRANK0_Lane5_OFF                       (20)
+  #define DDRDATA2CH0_CR_RXPERBITRANK0_Lane5_WID                       ( 4)
+  #define DDRDATA2CH0_CR_RXPERBITRANK0_Lane5_MSK                       (0x00F00000)
+  #define DDRDATA2CH0_CR_RXPERBITRANK0_Lane5_MAX                       (0x0000000F)
+  #define DDRDATA2CH0_CR_RXPERBITRANK0_Lane6_OFF                       (24)
+  #define DDRDATA2CH0_CR_RXPERBITRANK0_Lane6_WID                       ( 4)
+  #define DDRDATA2CH0_CR_RXPERBITRANK0_Lane6_MSK                       (0x0F000000)
+  #define DDRDATA2CH0_CR_RXPERBITRANK0_Lane6_MAX                       (0x0000000F)
+  #define DDRDATA2CH0_CR_RXPERBITRANK0_Lane7_OFF                       (28)
+  #define DDRDATA2CH0_CR_RXPERBITRANK0_Lane7_WID                       ( 4)
+  #define DDRDATA2CH0_CR_RXPERBITRANK0_Lane7_MSK                       (0xF0000000)
+  #define DDRDATA2CH0_CR_RXPERBITRANK0_Lane7_MAX                       (0x0000000F)
+
+#define DDRDATA2CH0_CR_RXPERBITRANK1_REG                             (0x00000414)
+  #define DDRDATA2CH0_CR_RXPERBITRANK1_Lane0_OFF                       ( 0)
+  #define DDRDATA2CH0_CR_RXPERBITRANK1_Lane0_WID                       ( 4)
+  #define DDRDATA2CH0_CR_RXPERBITRANK1_Lane0_MSK                       (0x0000000F)
+  #define DDRDATA2CH0_CR_RXPERBITRANK1_Lane0_MAX                       (0x0000000F)
+  #define DDRDATA2CH0_CR_RXPERBITRANK1_Lane1_OFF                       ( 4)
+  #define DDRDATA2CH0_CR_RXPERBITRANK1_Lane1_WID                       ( 4)
+  #define DDRDATA2CH0_CR_RXPERBITRANK1_Lane1_MSK                       (0x000000F0)
+  #define DDRDATA2CH0_CR_RXPERBITRANK1_Lane1_MAX                       (0x0000000F)
+  #define DDRDATA2CH0_CR_RXPERBITRANK1_Lane2_OFF                       ( 8)
+  #define DDRDATA2CH0_CR_RXPERBITRANK1_Lane2_WID                       ( 4)
+  #define DDRDATA2CH0_CR_RXPERBITRANK1_Lane2_MSK                       (0x00000F00)
+  #define DDRDATA2CH0_CR_RXPERBITRANK1_Lane2_MAX                       (0x0000000F)
+  #define DDRDATA2CH0_CR_RXPERBITRANK1_Lane3_OFF                       (12)
+  #define DDRDATA2CH0_CR_RXPERBITRANK1_Lane3_WID                       ( 4)
+  #define DDRDATA2CH0_CR_RXPERBITRANK1_Lane3_MSK                       (0x0000F000)
+  #define DDRDATA2CH0_CR_RXPERBITRANK1_Lane3_MAX                       (0x0000000F)
+  #define DDRDATA2CH0_CR_RXPERBITRANK1_Lane4_OFF                       (16)
+  #define DDRDATA2CH0_CR_RXPERBITRANK1_Lane4_WID                       ( 4)
+  #define DDRDATA2CH0_CR_RXPERBITRANK1_Lane4_MSK                       (0x000F0000)
+  #define DDRDATA2CH0_CR_RXPERBITRANK1_Lane4_MAX                       (0x0000000F)
+  #define DDRDATA2CH0_CR_RXPERBITRANK1_Lane5_OFF                       (20)
+  #define DDRDATA2CH0_CR_RXPERBITRANK1_Lane5_WID                       ( 4)
+  #define DDRDATA2CH0_CR_RXPERBITRANK1_Lane5_MSK                       (0x00F00000)
+  #define DDRDATA2CH0_CR_RXPERBITRANK1_Lane5_MAX                       (0x0000000F)
+  #define DDRDATA2CH0_CR_RXPERBITRANK1_Lane6_OFF                       (24)
+  #define DDRDATA2CH0_CR_RXPERBITRANK1_Lane6_WID                       ( 4)
+  #define DDRDATA2CH0_CR_RXPERBITRANK1_Lane6_MSK                       (0x0F000000)
+  #define DDRDATA2CH0_CR_RXPERBITRANK1_Lane6_MAX                       (0x0000000F)
+  #define DDRDATA2CH0_CR_RXPERBITRANK1_Lane7_OFF                       (28)
+  #define DDRDATA2CH0_CR_RXPERBITRANK1_Lane7_WID                       ( 4)
+  #define DDRDATA2CH0_CR_RXPERBITRANK1_Lane7_MSK                       (0xF0000000)
+  #define DDRDATA2CH0_CR_RXPERBITRANK1_Lane7_MAX                       (0x0000000F)
+
+#define DDRDATA2CH0_CR_RXPERBITRANK2_REG                             (0x00000418)
+  #define DDRDATA2CH0_CR_RXPERBITRANK2_Lane0_OFF                       ( 0)
+  #define DDRDATA2CH0_CR_RXPERBITRANK2_Lane0_WID                       ( 4)
+  #define DDRDATA2CH0_CR_RXPERBITRANK2_Lane0_MSK                       (0x0000000F)
+  #define DDRDATA2CH0_CR_RXPERBITRANK2_Lane0_MAX                       (0x0000000F)
+  #define DDRDATA2CH0_CR_RXPERBITRANK2_Lane1_OFF                       ( 4)
+  #define DDRDATA2CH0_CR_RXPERBITRANK2_Lane1_WID                       ( 4)
+  #define DDRDATA2CH0_CR_RXPERBITRANK2_Lane1_MSK                       (0x000000F0)
+  #define DDRDATA2CH0_CR_RXPERBITRANK2_Lane1_MAX                       (0x0000000F)
+  #define DDRDATA2CH0_CR_RXPERBITRANK2_Lane2_OFF                       ( 8)
+  #define DDRDATA2CH0_CR_RXPERBITRANK2_Lane2_WID                       ( 4)
+  #define DDRDATA2CH0_CR_RXPERBITRANK2_Lane2_MSK                       (0x00000F00)
+  #define DDRDATA2CH0_CR_RXPERBITRANK2_Lane2_MAX                       (0x0000000F)
+  #define DDRDATA2CH0_CR_RXPERBITRANK2_Lane3_OFF                       (12)
+  #define DDRDATA2CH0_CR_RXPERBITRANK2_Lane3_WID                       ( 4)
+  #define DDRDATA2CH0_CR_RXPERBITRANK2_Lane3_MSK                       (0x0000F000)
+  #define DDRDATA2CH0_CR_RXPERBITRANK2_Lane3_MAX                       (0x0000000F)
+  #define DDRDATA2CH0_CR_RXPERBITRANK2_Lane4_OFF                       (16)
+  #define DDRDATA2CH0_CR_RXPERBITRANK2_Lane4_WID                       ( 4)
+  #define DDRDATA2CH0_CR_RXPERBITRANK2_Lane4_MSK                       (0x000F0000)
+  #define DDRDATA2CH0_CR_RXPERBITRANK2_Lane4_MAX                       (0x0000000F)
+  #define DDRDATA2CH0_CR_RXPERBITRANK2_Lane5_OFF                       (20)
+  #define DDRDATA2CH0_CR_RXPERBITRANK2_Lane5_WID                       ( 4)
+  #define DDRDATA2CH0_CR_RXPERBITRANK2_Lane5_MSK                       (0x00F00000)
+  #define DDRDATA2CH0_CR_RXPERBITRANK2_Lane5_MAX                       (0x0000000F)
+  #define DDRDATA2CH0_CR_RXPERBITRANK2_Lane6_OFF                       (24)
+  #define DDRDATA2CH0_CR_RXPERBITRANK2_Lane6_WID                       ( 4)
+  #define DDRDATA2CH0_CR_RXPERBITRANK2_Lane6_MSK                       (0x0F000000)
+  #define DDRDATA2CH0_CR_RXPERBITRANK2_Lane6_MAX                       (0x0000000F)
+  #define DDRDATA2CH0_CR_RXPERBITRANK2_Lane7_OFF                       (28)
+  #define DDRDATA2CH0_CR_RXPERBITRANK2_Lane7_WID                       ( 4)
+  #define DDRDATA2CH0_CR_RXPERBITRANK2_Lane7_MSK                       (0xF0000000)
+  #define DDRDATA2CH0_CR_RXPERBITRANK2_Lane7_MAX                       (0x0000000F)
+
+#define DDRDATA2CH0_CR_RXPERBITRANK3_REG                             (0x0000041C)
+  #define DDRDATA2CH0_CR_RXPERBITRANK3_Lane0_OFF                       ( 0)
+  #define DDRDATA2CH0_CR_RXPERBITRANK3_Lane0_WID                       ( 4)
+  #define DDRDATA2CH0_CR_RXPERBITRANK3_Lane0_MSK                       (0x0000000F)
+  #define DDRDATA2CH0_CR_RXPERBITRANK3_Lane0_MAX                       (0x0000000F)
+  #define DDRDATA2CH0_CR_RXPERBITRANK3_Lane1_OFF                       ( 4)
+  #define DDRDATA2CH0_CR_RXPERBITRANK3_Lane1_WID                       ( 4)
+  #define DDRDATA2CH0_CR_RXPERBITRANK3_Lane1_MSK                       (0x000000F0)
+  #define DDRDATA2CH0_CR_RXPERBITRANK3_Lane1_MAX                       (0x0000000F)
+  #define DDRDATA2CH0_CR_RXPERBITRANK3_Lane2_OFF                       ( 8)
+  #define DDRDATA2CH0_CR_RXPERBITRANK3_Lane2_WID                       ( 4)
+  #define DDRDATA2CH0_CR_RXPERBITRANK3_Lane2_MSK                       (0x00000F00)
+  #define DDRDATA2CH0_CR_RXPERBITRANK3_Lane2_MAX                       (0x0000000F)
+  #define DDRDATA2CH0_CR_RXPERBITRANK3_Lane3_OFF                       (12)
+  #define DDRDATA2CH0_CR_RXPERBITRANK3_Lane3_WID                       ( 4)
+  #define DDRDATA2CH0_CR_RXPERBITRANK3_Lane3_MSK                       (0x0000F000)
+  #define DDRDATA2CH0_CR_RXPERBITRANK3_Lane3_MAX                       (0x0000000F)
+  #define DDRDATA2CH0_CR_RXPERBITRANK3_Lane4_OFF                       (16)
+  #define DDRDATA2CH0_CR_RXPERBITRANK3_Lane4_WID                       ( 4)
+  #define DDRDATA2CH0_CR_RXPERBITRANK3_Lane4_MSK                       (0x000F0000)
+  #define DDRDATA2CH0_CR_RXPERBITRANK3_Lane4_MAX                       (0x0000000F)
+  #define DDRDATA2CH0_CR_RXPERBITRANK3_Lane5_OFF                       (20)
+  #define DDRDATA2CH0_CR_RXPERBITRANK3_Lane5_WID                       ( 4)
+  #define DDRDATA2CH0_CR_RXPERBITRANK3_Lane5_MSK                       (0x00F00000)
+  #define DDRDATA2CH0_CR_RXPERBITRANK3_Lane5_MAX                       (0x0000000F)
+  #define DDRDATA2CH0_CR_RXPERBITRANK3_Lane6_OFF                       (24)
+  #define DDRDATA2CH0_CR_RXPERBITRANK3_Lane6_WID                       ( 4)
+  #define DDRDATA2CH0_CR_RXPERBITRANK3_Lane6_MSK                       (0x0F000000)
+  #define DDRDATA2CH0_CR_RXPERBITRANK3_Lane6_MAX                       (0x0000000F)
+  #define DDRDATA2CH0_CR_RXPERBITRANK3_Lane7_OFF                       (28)
+  #define DDRDATA2CH0_CR_RXPERBITRANK3_Lane7_WID                       ( 4)
+  #define DDRDATA2CH0_CR_RXPERBITRANK3_Lane7_MSK                       (0xF0000000)
+  #define DDRDATA2CH0_CR_RXPERBITRANK3_Lane7_MAX                       (0x0000000F)
+
+#define DDRDATA2CH0_CR_TXTRAINRANK0_REG                              (0x00000420)
+  #define DDRDATA2CH0_CR_TXTRAINRANK0_TxDqDelay_OFF                    ( 0)
+  #define DDRDATA2CH0_CR_TXTRAINRANK0_TxDqDelay_WID                    ( 9)
+  #define DDRDATA2CH0_CR_TXTRAINRANK0_TxDqDelay_MSK                    (0x000001FF)
+  #define DDRDATA2CH0_CR_TXTRAINRANK0_TxDqDelay_MAX                    (0x000001FF)
+  #define DDRDATA2CH0_CR_TXTRAINRANK0_TxDqsDelay_OFF                   ( 9)
+  #define DDRDATA2CH0_CR_TXTRAINRANK0_TxDqsDelay_WID                   ( 9)
+  #define DDRDATA2CH0_CR_TXTRAINRANK0_TxDqsDelay_MSK                   (0x0003FE00)
+  #define DDRDATA2CH0_CR_TXTRAINRANK0_TxDqsDelay_MAX                   (0x000001FF)
+  #define DDRDATA2CH0_CR_TXTRAINRANK0_Spare0_OFF                       (18)
+  #define DDRDATA2CH0_CR_TXTRAINRANK0_Spare0_WID                       ( 2)
+  #define DDRDATA2CH0_CR_TXTRAINRANK0_Spare0_MSK                       (0x000C0000)
+  #define DDRDATA2CH0_CR_TXTRAINRANK0_Spare0_MAX                       (0x00000003)
+  #define DDRDATA2CH0_CR_TXTRAINRANK0_TxEqualization_OFF               (20)
+  #define DDRDATA2CH0_CR_TXTRAINRANK0_TxEqualization_WID               ( 6)
+  #define DDRDATA2CH0_CR_TXTRAINRANK0_TxEqualization_MSK               (0x03F00000)
+  #define DDRDATA2CH0_CR_TXTRAINRANK0_TxEqualization_MAX               (0x0000003F)
+  #define DDRDATA2CH0_CR_TXTRAINRANK0_Spare1_OFF                       (26)
+  #define DDRDATA2CH0_CR_TXTRAINRANK0_Spare1_WID                       ( 6)
+  #define DDRDATA2CH0_CR_TXTRAINRANK0_Spare1_MSK                       (0xFC000000)
+  #define DDRDATA2CH0_CR_TXTRAINRANK0_Spare1_MAX                       (0x0000003F)
+
+#define DDRDATA2CH0_CR_TXTRAINRANK1_REG                              (0x00000424)
+  #define DDRDATA2CH0_CR_TXTRAINRANK1_TxDqDelay_OFF                    ( 0)
+  #define DDRDATA2CH0_CR_TXTRAINRANK1_TxDqDelay_WID                    ( 9)
+  #define DDRDATA2CH0_CR_TXTRAINRANK1_TxDqDelay_MSK                    (0x000001FF)
+  #define DDRDATA2CH0_CR_TXTRAINRANK1_TxDqDelay_MAX                    (0x000001FF)
+  #define DDRDATA2CH0_CR_TXTRAINRANK1_TxDqsDelay_OFF                   ( 9)
+  #define DDRDATA2CH0_CR_TXTRAINRANK1_TxDqsDelay_WID                   ( 9)
+  #define DDRDATA2CH0_CR_TXTRAINRANK1_TxDqsDelay_MSK                   (0x0003FE00)
+  #define DDRDATA2CH0_CR_TXTRAINRANK1_TxDqsDelay_MAX                   (0x000001FF)
+  #define DDRDATA2CH0_CR_TXTRAINRANK1_Spare0_OFF                       (18)
+  #define DDRDATA2CH0_CR_TXTRAINRANK1_Spare0_WID                       ( 2)
+  #define DDRDATA2CH0_CR_TXTRAINRANK1_Spare0_MSK                       (0x000C0000)
+  #define DDRDATA2CH0_CR_TXTRAINRANK1_Spare0_MAX                       (0x00000003)
+  #define DDRDATA2CH0_CR_TXTRAINRANK1_TxEqualization_OFF               (20)
+  #define DDRDATA2CH0_CR_TXTRAINRANK1_TxEqualization_WID               ( 6)
+  #define DDRDATA2CH0_CR_TXTRAINRANK1_TxEqualization_MSK               (0x03F00000)
+  #define DDRDATA2CH0_CR_TXTRAINRANK1_TxEqualization_MAX               (0x0000003F)
+  #define DDRDATA2CH0_CR_TXTRAINRANK1_Spare1_OFF                       (26)
+  #define DDRDATA2CH0_CR_TXTRAINRANK1_Spare1_WID                       ( 6)
+  #define DDRDATA2CH0_CR_TXTRAINRANK1_Spare1_MSK                       (0xFC000000)
+  #define DDRDATA2CH0_CR_TXTRAINRANK1_Spare1_MAX                       (0x0000003F)
+
+#define DDRDATA2CH0_CR_TXTRAINRANK2_REG                              (0x00000428)
+  #define DDRDATA2CH0_CR_TXTRAINRANK2_TxDqDelay_OFF                    ( 0)
+  #define DDRDATA2CH0_CR_TXTRAINRANK2_TxDqDelay_WID                    ( 9)
+  #define DDRDATA2CH0_CR_TXTRAINRANK2_TxDqDelay_MSK                    (0x000001FF)
+  #define DDRDATA2CH0_CR_TXTRAINRANK2_TxDqDelay_MAX                    (0x000001FF)
+  #define DDRDATA2CH0_CR_TXTRAINRANK2_TxDqsDelay_OFF                   ( 9)
+  #define DDRDATA2CH0_CR_TXTRAINRANK2_TxDqsDelay_WID                   ( 9)
+  #define DDRDATA2CH0_CR_TXTRAINRANK2_TxDqsDelay_MSK                   (0x0003FE00)
+  #define DDRDATA2CH0_CR_TXTRAINRANK2_TxDqsDelay_MAX                   (0x000001FF)
+  #define DDRDATA2CH0_CR_TXTRAINRANK2_Spare0_OFF                       (18)
+  #define DDRDATA2CH0_CR_TXTRAINRANK2_Spare0_WID                       ( 2)
+  #define DDRDATA2CH0_CR_TXTRAINRANK2_Spare0_MSK                       (0x000C0000)
+  #define DDRDATA2CH0_CR_TXTRAINRANK2_Spare0_MAX                       (0x00000003)
+  #define DDRDATA2CH0_CR_TXTRAINRANK2_TxEqualization_OFF               (20)
+  #define DDRDATA2CH0_CR_TXTRAINRANK2_TxEqualization_WID               ( 6)
+  #define DDRDATA2CH0_CR_TXTRAINRANK2_TxEqualization_MSK               (0x03F00000)
+  #define DDRDATA2CH0_CR_TXTRAINRANK2_TxEqualization_MAX               (0x0000003F)
+  #define DDRDATA2CH0_CR_TXTRAINRANK2_Spare1_OFF                       (26)
+  #define DDRDATA2CH0_CR_TXTRAINRANK2_Spare1_WID                       ( 6)
+  #define DDRDATA2CH0_CR_TXTRAINRANK2_Spare1_MSK                       (0xFC000000)
+  #define DDRDATA2CH0_CR_TXTRAINRANK2_Spare1_MAX                       (0x0000003F)
+
+#define DDRDATA2CH0_CR_TXTRAINRANK3_REG                              (0x0000042C)
+  #define DDRDATA2CH0_CR_TXTRAINRANK3_TxDqDelay_OFF                    ( 0)
+  #define DDRDATA2CH0_CR_TXTRAINRANK3_TxDqDelay_WID                    ( 9)
+  #define DDRDATA2CH0_CR_TXTRAINRANK3_TxDqDelay_MSK                    (0x000001FF)
+  #define DDRDATA2CH0_CR_TXTRAINRANK3_TxDqDelay_MAX                    (0x000001FF)
+  #define DDRDATA2CH0_CR_TXTRAINRANK3_TxDqsDelay_OFF                   ( 9)
+  #define DDRDATA2CH0_CR_TXTRAINRANK3_TxDqsDelay_WID                   ( 9)
+  #define DDRDATA2CH0_CR_TXTRAINRANK3_TxDqsDelay_MSK                   (0x0003FE00)
+  #define DDRDATA2CH0_CR_TXTRAINRANK3_TxDqsDelay_MAX                   (0x000001FF)
+  #define DDRDATA2CH0_CR_TXTRAINRANK3_Spare0_OFF                       (18)
+  #define DDRDATA2CH0_CR_TXTRAINRANK3_Spare0_WID                       ( 2)
+  #define DDRDATA2CH0_CR_TXTRAINRANK3_Spare0_MSK                       (0x000C0000)
+  #define DDRDATA2CH0_CR_TXTRAINRANK3_Spare0_MAX                       (0x00000003)
+  #define DDRDATA2CH0_CR_TXTRAINRANK3_TxEqualization_OFF               (20)
+  #define DDRDATA2CH0_CR_TXTRAINRANK3_TxEqualization_WID               ( 6)
+  #define DDRDATA2CH0_CR_TXTRAINRANK3_TxEqualization_MSK               (0x03F00000)
+  #define DDRDATA2CH0_CR_TXTRAINRANK3_TxEqualization_MAX               (0x0000003F)
+  #define DDRDATA2CH0_CR_TXTRAINRANK3_Spare1_OFF                       (26)
+  #define DDRDATA2CH0_CR_TXTRAINRANK3_Spare1_WID                       ( 6)
+  #define DDRDATA2CH0_CR_TXTRAINRANK3_Spare1_MSK                       (0xFC000000)
+  #define DDRDATA2CH0_CR_TXTRAINRANK3_Spare1_MAX                       (0x0000003F)
+
+#define DDRDATA2CH0_CR_TXPERBITRANK0_REG                             (0x00000430)
+  #define DDRDATA2CH0_CR_TXPERBITRANK0_Lane0_OFF                       ( 0)
+  #define DDRDATA2CH0_CR_TXPERBITRANK0_Lane0_WID                       ( 4)
+  #define DDRDATA2CH0_CR_TXPERBITRANK0_Lane0_MSK                       (0x0000000F)
+  #define DDRDATA2CH0_CR_TXPERBITRANK0_Lane0_MAX                       (0x0000000F)
+  #define DDRDATA2CH0_CR_TXPERBITRANK0_Lane1_OFF                       ( 4)
+  #define DDRDATA2CH0_CR_TXPERBITRANK0_Lane1_WID                       ( 4)
+  #define DDRDATA2CH0_CR_TXPERBITRANK0_Lane1_MSK                       (0x000000F0)
+  #define DDRDATA2CH0_CR_TXPERBITRANK0_Lane1_MAX                       (0x0000000F)
+  #define DDRDATA2CH0_CR_TXPERBITRANK0_Lane2_OFF                       ( 8)
+  #define DDRDATA2CH0_CR_TXPERBITRANK0_Lane2_WID                       ( 4)
+  #define DDRDATA2CH0_CR_TXPERBITRANK0_Lane2_MSK                       (0x00000F00)
+  #define DDRDATA2CH0_CR_TXPERBITRANK0_Lane2_MAX                       (0x0000000F)
+  #define DDRDATA2CH0_CR_TXPERBITRANK0_Lane3_OFF                       (12)
+  #define DDRDATA2CH0_CR_TXPERBITRANK0_Lane3_WID                       ( 4)
+  #define DDRDATA2CH0_CR_TXPERBITRANK0_Lane3_MSK                       (0x0000F000)
+  #define DDRDATA2CH0_CR_TXPERBITRANK0_Lane3_MAX                       (0x0000000F)
+  #define DDRDATA2CH0_CR_TXPERBITRANK0_Lane4_OFF                       (16)
+  #define DDRDATA2CH0_CR_TXPERBITRANK0_Lane4_WID                       ( 4)
+  #define DDRDATA2CH0_CR_TXPERBITRANK0_Lane4_MSK                       (0x000F0000)
+  #define DDRDATA2CH0_CR_TXPERBITRANK0_Lane4_MAX                       (0x0000000F)
+  #define DDRDATA2CH0_CR_TXPERBITRANK0_Lane5_OFF                       (20)
+  #define DDRDATA2CH0_CR_TXPERBITRANK0_Lane5_WID                       ( 4)
+  #define DDRDATA2CH0_CR_TXPERBITRANK0_Lane5_MSK                       (0x00F00000)
+  #define DDRDATA2CH0_CR_TXPERBITRANK0_Lane5_MAX                       (0x0000000F)
+  #define DDRDATA2CH0_CR_TXPERBITRANK0_Lane6_OFF                       (24)
+  #define DDRDATA2CH0_CR_TXPERBITRANK0_Lane6_WID                       ( 4)
+  #define DDRDATA2CH0_CR_TXPERBITRANK0_Lane6_MSK                       (0x0F000000)
+  #define DDRDATA2CH0_CR_TXPERBITRANK0_Lane6_MAX                       (0x0000000F)
+  #define DDRDATA2CH0_CR_TXPERBITRANK0_Lane7_OFF                       (28)
+  #define DDRDATA2CH0_CR_TXPERBITRANK0_Lane7_WID                       ( 4)
+  #define DDRDATA2CH0_CR_TXPERBITRANK0_Lane7_MSK                       (0xF0000000)
+  #define DDRDATA2CH0_CR_TXPERBITRANK0_Lane7_MAX                       (0x0000000F)
+
+#define DDRDATA2CH0_CR_TXPERBITRANK1_REG                             (0x00000434)
+  #define DDRDATA2CH0_CR_TXPERBITRANK1_Lane0_OFF                       ( 0)
+  #define DDRDATA2CH0_CR_TXPERBITRANK1_Lane0_WID                       ( 4)
+  #define DDRDATA2CH0_CR_TXPERBITRANK1_Lane0_MSK                       (0x0000000F)
+  #define DDRDATA2CH0_CR_TXPERBITRANK1_Lane0_MAX                       (0x0000000F)
+  #define DDRDATA2CH0_CR_TXPERBITRANK1_Lane1_OFF                       ( 4)
+  #define DDRDATA2CH0_CR_TXPERBITRANK1_Lane1_WID                       ( 4)
+  #define DDRDATA2CH0_CR_TXPERBITRANK1_Lane1_MSK                       (0x000000F0)
+  #define DDRDATA2CH0_CR_TXPERBITRANK1_Lane1_MAX                       (0x0000000F)
+  #define DDRDATA2CH0_CR_TXPERBITRANK1_Lane2_OFF                       ( 8)
+  #define DDRDATA2CH0_CR_TXPERBITRANK1_Lane2_WID                       ( 4)
+  #define DDRDATA2CH0_CR_TXPERBITRANK1_Lane2_MSK                       (0x00000F00)
+  #define DDRDATA2CH0_CR_TXPERBITRANK1_Lane2_MAX                       (0x0000000F)
+  #define DDRDATA2CH0_CR_TXPERBITRANK1_Lane3_OFF                       (12)
+  #define DDRDATA2CH0_CR_TXPERBITRANK1_Lane3_WID                       ( 4)
+  #define DDRDATA2CH0_CR_TXPERBITRANK1_Lane3_MSK                       (0x0000F000)
+  #define DDRDATA2CH0_CR_TXPERBITRANK1_Lane3_MAX                       (0x0000000F)
+  #define DDRDATA2CH0_CR_TXPERBITRANK1_Lane4_OFF                       (16)
+  #define DDRDATA2CH0_CR_TXPERBITRANK1_Lane4_WID                       ( 4)
+  #define DDRDATA2CH0_CR_TXPERBITRANK1_Lane4_MSK                       (0x000F0000)
+  #define DDRDATA2CH0_CR_TXPERBITRANK1_Lane4_MAX                       (0x0000000F)
+  #define DDRDATA2CH0_CR_TXPERBITRANK1_Lane5_OFF                       (20)
+  #define DDRDATA2CH0_CR_TXPERBITRANK1_Lane5_WID                       ( 4)
+  #define DDRDATA2CH0_CR_TXPERBITRANK1_Lane5_MSK                       (0x00F00000)
+  #define DDRDATA2CH0_CR_TXPERBITRANK1_Lane5_MAX                       (0x0000000F)
+  #define DDRDATA2CH0_CR_TXPERBITRANK1_Lane6_OFF                       (24)
+  #define DDRDATA2CH0_CR_TXPERBITRANK1_Lane6_WID                       ( 4)
+  #define DDRDATA2CH0_CR_TXPERBITRANK1_Lane6_MSK                       (0x0F000000)
+  #define DDRDATA2CH0_CR_TXPERBITRANK1_Lane6_MAX                       (0x0000000F)
+  #define DDRDATA2CH0_CR_TXPERBITRANK1_Lane7_OFF                       (28)
+  #define DDRDATA2CH0_CR_TXPERBITRANK1_Lane7_WID                       ( 4)
+  #define DDRDATA2CH0_CR_TXPERBITRANK1_Lane7_MSK                       (0xF0000000)
+  #define DDRDATA2CH0_CR_TXPERBITRANK1_Lane7_MAX                       (0x0000000F)
+
+#define DDRDATA2CH0_CR_TXPERBITRANK2_REG                             (0x00000438)
+  #define DDRDATA2CH0_CR_TXPERBITRANK2_Lane0_OFF                       ( 0)
+  #define DDRDATA2CH0_CR_TXPERBITRANK2_Lane0_WID                       ( 4)
+  #define DDRDATA2CH0_CR_TXPERBITRANK2_Lane0_MSK                       (0x0000000F)
+  #define DDRDATA2CH0_CR_TXPERBITRANK2_Lane0_MAX                       (0x0000000F)
+  #define DDRDATA2CH0_CR_TXPERBITRANK2_Lane1_OFF                       ( 4)
+  #define DDRDATA2CH0_CR_TXPERBITRANK2_Lane1_WID                       ( 4)
+  #define DDRDATA2CH0_CR_TXPERBITRANK2_Lane1_MSK                       (0x000000F0)
+  #define DDRDATA2CH0_CR_TXPERBITRANK2_Lane1_MAX                       (0x0000000F)
+  #define DDRDATA2CH0_CR_TXPERBITRANK2_Lane2_OFF                       ( 8)
+  #define DDRDATA2CH0_CR_TXPERBITRANK2_Lane2_WID                       ( 4)
+  #define DDRDATA2CH0_CR_TXPERBITRANK2_Lane2_MSK                       (0x00000F00)
+  #define DDRDATA2CH0_CR_TXPERBITRANK2_Lane2_MAX                       (0x0000000F)
+  #define DDRDATA2CH0_CR_TXPERBITRANK2_Lane3_OFF                       (12)
+  #define DDRDATA2CH0_CR_TXPERBITRANK2_Lane3_WID                       ( 4)
+  #define DDRDATA2CH0_CR_TXPERBITRANK2_Lane3_MSK                       (0x0000F000)
+  #define DDRDATA2CH0_CR_TXPERBITRANK2_Lane3_MAX                       (0x0000000F)
+  #define DDRDATA2CH0_CR_TXPERBITRANK2_Lane4_OFF                       (16)
+  #define DDRDATA2CH0_CR_TXPERBITRANK2_Lane4_WID                       ( 4)
+  #define DDRDATA2CH0_CR_TXPERBITRANK2_Lane4_MSK                       (0x000F0000)
+  #define DDRDATA2CH0_CR_TXPERBITRANK2_Lane4_MAX                       (0x0000000F)
+  #define DDRDATA2CH0_CR_TXPERBITRANK2_Lane5_OFF                       (20)
+  #define DDRDATA2CH0_CR_TXPERBITRANK2_Lane5_WID                       ( 4)
+  #define DDRDATA2CH0_CR_TXPERBITRANK2_Lane5_MSK                       (0x00F00000)
+  #define DDRDATA2CH0_CR_TXPERBITRANK2_Lane5_MAX                       (0x0000000F)
+  #define DDRDATA2CH0_CR_TXPERBITRANK2_Lane6_OFF                       (24)
+  #define DDRDATA2CH0_CR_TXPERBITRANK2_Lane6_WID                       ( 4)
+  #define DDRDATA2CH0_CR_TXPERBITRANK2_Lane6_MSK                       (0x0F000000)
+  #define DDRDATA2CH0_CR_TXPERBITRANK2_Lane6_MAX                       (0x0000000F)
+  #define DDRDATA2CH0_CR_TXPERBITRANK2_Lane7_OFF                       (28)
+  #define DDRDATA2CH0_CR_TXPERBITRANK2_Lane7_WID                       ( 4)
+  #define DDRDATA2CH0_CR_TXPERBITRANK2_Lane7_MSK                       (0xF0000000)
+  #define DDRDATA2CH0_CR_TXPERBITRANK2_Lane7_MAX                       (0x0000000F)
+
+#define DDRDATA2CH0_CR_TXPERBITRANK3_REG                             (0x0000043C)
+  #define DDRDATA2CH0_CR_TXPERBITRANK3_Lane0_OFF                       ( 0)
+  #define DDRDATA2CH0_CR_TXPERBITRANK3_Lane0_WID                       ( 4)
+  #define DDRDATA2CH0_CR_TXPERBITRANK3_Lane0_MSK                       (0x0000000F)
+  #define DDRDATA2CH0_CR_TXPERBITRANK3_Lane0_MAX                       (0x0000000F)
+  #define DDRDATA2CH0_CR_TXPERBITRANK3_Lane1_OFF                       ( 4)
+  #define DDRDATA2CH0_CR_TXPERBITRANK3_Lane1_WID                       ( 4)
+  #define DDRDATA2CH0_CR_TXPERBITRANK3_Lane1_MSK                       (0x000000F0)
+  #define DDRDATA2CH0_CR_TXPERBITRANK3_Lane1_MAX                       (0x0000000F)
+  #define DDRDATA2CH0_CR_TXPERBITRANK3_Lane2_OFF                       ( 8)
+  #define DDRDATA2CH0_CR_TXPERBITRANK3_Lane2_WID                       ( 4)
+  #define DDRDATA2CH0_CR_TXPERBITRANK3_Lane2_MSK                       (0x00000F00)
+  #define DDRDATA2CH0_CR_TXPERBITRANK3_Lane2_MAX                       (0x0000000F)
+  #define DDRDATA2CH0_CR_TXPERBITRANK3_Lane3_OFF                       (12)
+  #define DDRDATA2CH0_CR_TXPERBITRANK3_Lane3_WID                       ( 4)
+  #define DDRDATA2CH0_CR_TXPERBITRANK3_Lane3_MSK                       (0x0000F000)
+  #define DDRDATA2CH0_CR_TXPERBITRANK3_Lane3_MAX                       (0x0000000F)
+  #define DDRDATA2CH0_CR_TXPERBITRANK3_Lane4_OFF                       (16)
+  #define DDRDATA2CH0_CR_TXPERBITRANK3_Lane4_WID                       ( 4)
+  #define DDRDATA2CH0_CR_TXPERBITRANK3_Lane4_MSK                       (0x000F0000)
+  #define DDRDATA2CH0_CR_TXPERBITRANK3_Lane4_MAX                       (0x0000000F)
+  #define DDRDATA2CH0_CR_TXPERBITRANK3_Lane5_OFF                       (20)
+  #define DDRDATA2CH0_CR_TXPERBITRANK3_Lane5_WID                       ( 4)
+  #define DDRDATA2CH0_CR_TXPERBITRANK3_Lane5_MSK                       (0x00F00000)
+  #define DDRDATA2CH0_CR_TXPERBITRANK3_Lane5_MAX                       (0x0000000F)
+  #define DDRDATA2CH0_CR_TXPERBITRANK3_Lane6_OFF                       (24)
+  #define DDRDATA2CH0_CR_TXPERBITRANK3_Lane6_WID                       ( 4)
+  #define DDRDATA2CH0_CR_TXPERBITRANK3_Lane6_MSK                       (0x0F000000)
+  #define DDRDATA2CH0_CR_TXPERBITRANK3_Lane6_MAX                       (0x0000000F)
+  #define DDRDATA2CH0_CR_TXPERBITRANK3_Lane7_OFF                       (28)
+  #define DDRDATA2CH0_CR_TXPERBITRANK3_Lane7_WID                       ( 4)
+  #define DDRDATA2CH0_CR_TXPERBITRANK3_Lane7_MSK                       (0xF0000000)
+  #define DDRDATA2CH0_CR_TXPERBITRANK3_Lane7_MAX                       (0x0000000F)
+
+#define DDRDATA2CH0_CR_RCOMPDATA0_REG                                (0x00000440)
+  #define DDRDATA2CH0_CR_RCOMPDATA0_RcompDrvUp_OFF                     ( 0)
+  #define DDRDATA2CH0_CR_RCOMPDATA0_RcompDrvUp_WID                     ( 6)
+  #define DDRDATA2CH0_CR_RCOMPDATA0_RcompDrvUp_MSK                     (0x0000003F)
+  #define DDRDATA2CH0_CR_RCOMPDATA0_RcompDrvUp_MAX                     (0x0000003F)
+  #define DDRDATA2CH0_CR_RCOMPDATA0_Spare0_OFF                         ( 6)
+  #define DDRDATA2CH0_CR_RCOMPDATA0_Spare0_WID                         ( 3)
+  #define DDRDATA2CH0_CR_RCOMPDATA0_Spare0_MSK                         (0x000001C0)
+  #define DDRDATA2CH0_CR_RCOMPDATA0_Spare0_MAX                         (0x00000007)
+  #define DDRDATA2CH0_CR_RCOMPDATA0_RcompDrvDown_OFF                   ( 9)
+  #define DDRDATA2CH0_CR_RCOMPDATA0_RcompDrvDown_WID                   ( 6)
+  #define DDRDATA2CH0_CR_RCOMPDATA0_RcompDrvDown_MSK                   (0x00007E00)
+  #define DDRDATA2CH0_CR_RCOMPDATA0_RcompDrvDown_MAX                   (0x0000003F)
+  #define DDRDATA2CH0_CR_RCOMPDATA0_VTComp_OFF                         (15)
+  #define DDRDATA2CH0_CR_RCOMPDATA0_VTComp_WID                         ( 5)
+  #define DDRDATA2CH0_CR_RCOMPDATA0_VTComp_MSK                         (0x000F8000)
+  #define DDRDATA2CH0_CR_RCOMPDATA0_VTComp_MAX                         (0x0000001F)
+  #define DDRDATA2CH0_CR_RCOMPDATA0_TcoComp_OFF                        (20)
+  #define DDRDATA2CH0_CR_RCOMPDATA0_TcoComp_WID                        ( 6)
+  #define DDRDATA2CH0_CR_RCOMPDATA0_TcoComp_MSK                        (0x03F00000)
+  #define DDRDATA2CH0_CR_RCOMPDATA0_TcoComp_MAX                        (0x0000003F)
+  #define DDRDATA2CH0_CR_RCOMPDATA0_SlewRateComp_OFF                   (26)
+  #define DDRDATA2CH0_CR_RCOMPDATA0_SlewRateComp_WID                   ( 5)
+  #define DDRDATA2CH0_CR_RCOMPDATA0_SlewRateComp_MSK                   (0x7C000000)
+  #define DDRDATA2CH0_CR_RCOMPDATA0_SlewRateComp_MAX                   (0x0000001F)
+  #define DDRDATA2CH0_CR_RCOMPDATA0_Spare2_OFF                         (31)
+  #define DDRDATA2CH0_CR_RCOMPDATA0_Spare2_WID                         ( 1)
+  #define DDRDATA2CH0_CR_RCOMPDATA0_Spare2_MSK                         (0x80000000)
+  #define DDRDATA2CH0_CR_RCOMPDATA0_Spare2_MAX                         (0x00000001)
+
+#define DDRDATA2CH0_CR_RCOMPDATA1_REG                                (0x00000444)
+  #define DDRDATA2CH0_CR_RCOMPDATA1_RcompOdtUp_OFF                     ( 0)
+  #define DDRDATA2CH0_CR_RCOMPDATA1_RcompOdtUp_WID                     ( 6)
+  #define DDRDATA2CH0_CR_RCOMPDATA1_RcompOdtUp_MSK                     (0x0000003F)
+  #define DDRDATA2CH0_CR_RCOMPDATA1_RcompOdtUp_MAX                     (0x0000003F)
+  #define DDRDATA2CH0_CR_RCOMPDATA1_Spare0_OFF                         ( 6)
+  #define DDRDATA2CH0_CR_RCOMPDATA1_Spare0_WID                         ( 3)
+  #define DDRDATA2CH0_CR_RCOMPDATA1_Spare0_MSK                         (0x000001C0)
+  #define DDRDATA2CH0_CR_RCOMPDATA1_Spare0_MAX                         (0x00000007)
+  #define DDRDATA2CH0_CR_RCOMPDATA1_RcompOdtDown_OFF                   ( 9)
+  #define DDRDATA2CH0_CR_RCOMPDATA1_RcompOdtDown_WID                   ( 6)
+  #define DDRDATA2CH0_CR_RCOMPDATA1_RcompOdtDown_MSK                   (0x00007E00)
+  #define DDRDATA2CH0_CR_RCOMPDATA1_RcompOdtDown_MAX                   (0x0000003F)
+  #define DDRDATA2CH0_CR_RCOMPDATA1_Spare1_OFF                         (15)
+  #define DDRDATA2CH0_CR_RCOMPDATA1_Spare1_WID                         ( 1)
+  #define DDRDATA2CH0_CR_RCOMPDATA1_Spare1_MSK                         (0x00008000)
+  #define DDRDATA2CH0_CR_RCOMPDATA1_Spare1_MAX                         (0x00000001)
+  #define DDRDATA2CH0_CR_RCOMPDATA1_PanicDrvDn_OFF                     (16)
+  #define DDRDATA2CH0_CR_RCOMPDATA1_PanicDrvDn_WID                     ( 6)
+  #define DDRDATA2CH0_CR_RCOMPDATA1_PanicDrvDn_MSK                     (0x003F0000)
+  #define DDRDATA2CH0_CR_RCOMPDATA1_PanicDrvDn_MAX                     (0x0000003F)
+  #define DDRDATA2CH0_CR_RCOMPDATA1_PanicDrvUp_OFF                     (22)
+  #define DDRDATA2CH0_CR_RCOMPDATA1_PanicDrvUp_WID                     ( 6)
+  #define DDRDATA2CH0_CR_RCOMPDATA1_PanicDrvUp_MSK                     (0x0FC00000)
+  #define DDRDATA2CH0_CR_RCOMPDATA1_PanicDrvUp_MAX                     (0x0000003F)
+  #define DDRDATA2CH0_CR_RCOMPDATA1_LevelShifterComp_OFF               (28)
+  #define DDRDATA2CH0_CR_RCOMPDATA1_LevelShifterComp_WID               ( 3)
+  #define DDRDATA2CH0_CR_RCOMPDATA1_LevelShifterComp_MSK               (0x70000000)
+  #define DDRDATA2CH0_CR_RCOMPDATA1_LevelShifterComp_MAX               (0x00000007)
+  #define DDRDATA2CH0_CR_RCOMPDATA1_Spare2_OFF                         (31)
+  #define DDRDATA2CH0_CR_RCOMPDATA1_Spare2_WID                         ( 1)
+  #define DDRDATA2CH0_CR_RCOMPDATA1_Spare2_MSK                         (0x80000000)
+  #define DDRDATA2CH0_CR_RCOMPDATA1_Spare2_MAX                         (0x00000001)
+
+#define DDRDATA2CH0_CR_TXXTALK_REG                                   (0x00000448)
+  #define DDRDATA2CH0_CR_TXXTALK_Lane0_OFF                             ( 0)
+  #define DDRDATA2CH0_CR_TXXTALK_Lane0_WID                             ( 4)
+  #define DDRDATA2CH0_CR_TXXTALK_Lane0_MSK                             (0x0000000F)
+  #define DDRDATA2CH0_CR_TXXTALK_Lane0_MAX                             (0x0000000F)
+  #define DDRDATA2CH0_CR_TXXTALK_Lane1_OFF                             ( 4)
+  #define DDRDATA2CH0_CR_TXXTALK_Lane1_WID                             ( 4)
+  #define DDRDATA2CH0_CR_TXXTALK_Lane1_MSK                             (0x000000F0)
+  #define DDRDATA2CH0_CR_TXXTALK_Lane1_MAX                             (0x0000000F)
+  #define DDRDATA2CH0_CR_TXXTALK_Lane2_OFF                             ( 8)
+  #define DDRDATA2CH0_CR_TXXTALK_Lane2_WID                             ( 4)
+  #define DDRDATA2CH0_CR_TXXTALK_Lane2_MSK                             (0x00000F00)
+  #define DDRDATA2CH0_CR_TXXTALK_Lane2_MAX                             (0x0000000F)
+  #define DDRDATA2CH0_CR_TXXTALK_Lane3_OFF                             (12)
+  #define DDRDATA2CH0_CR_TXXTALK_Lane3_WID                             ( 4)
+  #define DDRDATA2CH0_CR_TXXTALK_Lane3_MSK                             (0x0000F000)
+  #define DDRDATA2CH0_CR_TXXTALK_Lane3_MAX                             (0x0000000F)
+  #define DDRDATA2CH0_CR_TXXTALK_Lane4_OFF                             (16)
+  #define DDRDATA2CH0_CR_TXXTALK_Lane4_WID                             ( 4)
+  #define DDRDATA2CH0_CR_TXXTALK_Lane4_MSK                             (0x000F0000)
+  #define DDRDATA2CH0_CR_TXXTALK_Lane4_MAX                             (0x0000000F)
+  #define DDRDATA2CH0_CR_TXXTALK_Lane5_OFF                             (20)
+  #define DDRDATA2CH0_CR_TXXTALK_Lane5_WID                             ( 4)
+  #define DDRDATA2CH0_CR_TXXTALK_Lane5_MSK                             (0x00F00000)
+  #define DDRDATA2CH0_CR_TXXTALK_Lane5_MAX                             (0x0000000F)
+  #define DDRDATA2CH0_CR_TXXTALK_Lane6_OFF                             (24)
+  #define DDRDATA2CH0_CR_TXXTALK_Lane6_WID                             ( 4)
+  #define DDRDATA2CH0_CR_TXXTALK_Lane6_MSK                             (0x0F000000)
+  #define DDRDATA2CH0_CR_TXXTALK_Lane6_MAX                             (0x0000000F)
+  #define DDRDATA2CH0_CR_TXXTALK_Lane7_OFF                             (28)
+  #define DDRDATA2CH0_CR_TXXTALK_Lane7_WID                             ( 4)
+  #define DDRDATA2CH0_CR_TXXTALK_Lane7_MSK                             (0xF0000000)
+  #define DDRDATA2CH0_CR_TXXTALK_Lane7_MAX                             (0x0000000F)
+
+#define DDRDATA2CH0_CR_RXOFFSETVDQ_REG                               (0x0000044C)
+  #define DDRDATA2CH0_CR_RXOFFSETVDQ_Lane0_OFF                         ( 0)
+  #define DDRDATA2CH0_CR_RXOFFSETVDQ_Lane0_WID                         ( 4)
+  #define DDRDATA2CH0_CR_RXOFFSETVDQ_Lane0_MSK                         (0x0000000F)
+  #define DDRDATA2CH0_CR_RXOFFSETVDQ_Lane0_MAX                         (0x0000000F)
+  #define DDRDATA2CH0_CR_RXOFFSETVDQ_Lane1_OFF                         ( 4)
+  #define DDRDATA2CH0_CR_RXOFFSETVDQ_Lane1_WID                         ( 4)
+  #define DDRDATA2CH0_CR_RXOFFSETVDQ_Lane1_MSK                         (0x000000F0)
+  #define DDRDATA2CH0_CR_RXOFFSETVDQ_Lane1_MAX                         (0x0000000F)
+  #define DDRDATA2CH0_CR_RXOFFSETVDQ_Lane2_OFF                         ( 8)
+  #define DDRDATA2CH0_CR_RXOFFSETVDQ_Lane2_WID                         ( 4)
+  #define DDRDATA2CH0_CR_RXOFFSETVDQ_Lane2_MSK                         (0x00000F00)
+  #define DDRDATA2CH0_CR_RXOFFSETVDQ_Lane2_MAX                         (0x0000000F)
+  #define DDRDATA2CH0_CR_RXOFFSETVDQ_Lane3_OFF                         (12)
+  #define DDRDATA2CH0_CR_RXOFFSETVDQ_Lane3_WID                         ( 4)
+  #define DDRDATA2CH0_CR_RXOFFSETVDQ_Lane3_MSK                         (0x0000F000)
+  #define DDRDATA2CH0_CR_RXOFFSETVDQ_Lane3_MAX                         (0x0000000F)
+  #define DDRDATA2CH0_CR_RXOFFSETVDQ_Lane4_OFF                         (16)
+  #define DDRDATA2CH0_CR_RXOFFSETVDQ_Lane4_WID                         ( 4)
+  #define DDRDATA2CH0_CR_RXOFFSETVDQ_Lane4_MSK                         (0x000F0000)
+  #define DDRDATA2CH0_CR_RXOFFSETVDQ_Lane4_MAX                         (0x0000000F)
+  #define DDRDATA2CH0_CR_RXOFFSETVDQ_Lane5_OFF                         (20)
+  #define DDRDATA2CH0_CR_RXOFFSETVDQ_Lane5_WID                         ( 4)
+  #define DDRDATA2CH0_CR_RXOFFSETVDQ_Lane5_MSK                         (0x00F00000)
+  #define DDRDATA2CH0_CR_RXOFFSETVDQ_Lane5_MAX                         (0x0000000F)
+  #define DDRDATA2CH0_CR_RXOFFSETVDQ_Lane6_OFF                         (24)
+  #define DDRDATA2CH0_CR_RXOFFSETVDQ_Lane6_WID                         ( 4)
+  #define DDRDATA2CH0_CR_RXOFFSETVDQ_Lane6_MSK                         (0x0F000000)
+  #define DDRDATA2CH0_CR_RXOFFSETVDQ_Lane6_MAX                         (0x0000000F)
+  #define DDRDATA2CH0_CR_RXOFFSETVDQ_Lane7_OFF                         (28)
+  #define DDRDATA2CH0_CR_RXOFFSETVDQ_Lane7_WID                         ( 4)
+  #define DDRDATA2CH0_CR_RXOFFSETVDQ_Lane7_MSK                         (0xF0000000)
+  #define DDRDATA2CH0_CR_RXOFFSETVDQ_Lane7_MAX                         (0x0000000F)
+
+#define DDRDATA2CH0_CR_DDRDATARESERVED_REG                           (0x00000450)
+  #define DDRDATA2CH0_CR_DDRDATARESERVED_Spare_OFF                     ( 0)
+  #define DDRDATA2CH0_CR_DDRDATARESERVED_Spare_WID                     (32)
+  #define DDRDATA2CH0_CR_DDRDATARESERVED_Spare_MSK                     (0xFFFFFFFF)
+  #define DDRDATA2CH0_CR_DDRDATARESERVED_Spare_MAX                     (0xFFFFFFFF)
+
+#define DDRDATA2CH0_CR_DATATRAINFEEDBACK_REG                         (0x00000454)
+  #define DDRDATA2CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_OFF       ( 0)
+  #define DDRDATA2CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_WID       ( 9)
+  #define DDRDATA2CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_MSK       (0x000001FF)
+  #define DDRDATA2CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_MAX       (0x000001FF)
+  #define DDRDATA2CH0_CR_DATATRAINFEEDBACK_Spare_OFF                   ( 9)
+  #define DDRDATA2CH0_CR_DATATRAINFEEDBACK_Spare_WID                   (23)
+  #define DDRDATA2CH0_CR_DATATRAINFEEDBACK_Spare_MSK                   (0xFFFFFE00)
+  #define DDRDATA2CH0_CR_DATATRAINFEEDBACK_Spare_MAX                   (0x007FFFFF)
+
+#define DDRDATA2CH0_CR_DLLPITESTANDADC_REG                           (0x00000458)
+  #define DDRDATA2CH0_CR_DLLPITESTANDADC_RunTest_OFF                   ( 0)
+  #define DDRDATA2CH0_CR_DLLPITESTANDADC_RunTest_WID                   ( 1)
+  #define DDRDATA2CH0_CR_DLLPITESTANDADC_RunTest_MSK                   (0x00000001)
+  #define DDRDATA2CH0_CR_DLLPITESTANDADC_RunTest_MAX                   (0x00000001)
+  #define DDRDATA2CH0_CR_DLLPITESTANDADC_RunTest_DEF                   (0x00000000)
+  #define DDRDATA2CH0_CR_DLLPITESTANDADC_Load_OFF                      ( 1)
+  #define DDRDATA2CH0_CR_DLLPITESTANDADC_Load_WID                      ( 1)
+  #define DDRDATA2CH0_CR_DLLPITESTANDADC_Load_MSK                      (0x00000002)
+  #define DDRDATA2CH0_CR_DLLPITESTANDADC_Load_MAX                      (0x00000001)
+  #define DDRDATA2CH0_CR_DLLPITESTANDADC_Load_DEF                      (0x00000000)
+  #define DDRDATA2CH0_CR_DLLPITESTANDADC_ModeHVM_OFF                   ( 2)
+  #define DDRDATA2CH0_CR_DLLPITESTANDADC_ModeHVM_WID                   ( 1)
+  #define DDRDATA2CH0_CR_DLLPITESTANDADC_ModeHVM_MSK                   (0x00000004)
+  #define DDRDATA2CH0_CR_DLLPITESTANDADC_ModeHVM_MAX                   (0x00000001)
+  #define DDRDATA2CH0_CR_DLLPITESTANDADC_ModeHVM_DEF                   (0x00000000)
+  #define DDRDATA2CH0_CR_DLLPITESTANDADC_ModeDV_OFF                    ( 3)
+  #define DDRDATA2CH0_CR_DLLPITESTANDADC_ModeDV_WID                    ( 1)
+  #define DDRDATA2CH0_CR_DLLPITESTANDADC_ModeDV_MSK                    (0x00000008)
+  #define DDRDATA2CH0_CR_DLLPITESTANDADC_ModeDV_MAX                    (0x00000001)
+  #define DDRDATA2CH0_CR_DLLPITESTANDADC_ModeDV_DEF                    (0x00000000)
+  #define DDRDATA2CH0_CR_DLLPITESTANDADC_ModeADC_OFF                   ( 4)
+  #define DDRDATA2CH0_CR_DLLPITESTANDADC_ModeADC_WID                   ( 1)
+  #define DDRDATA2CH0_CR_DLLPITESTANDADC_ModeADC_MSK                   (0x00000010)
+  #define DDRDATA2CH0_CR_DLLPITESTANDADC_ModeADC_MAX                   (0x00000001)
+  #define DDRDATA2CH0_CR_DLLPITESTANDADC_ModeADC_DEF                   (0x00000000)
+  #define DDRDATA2CH0_CR_DLLPITESTANDADC_LoadCount_OFF                 ( 5)
+  #define DDRDATA2CH0_CR_DLLPITESTANDADC_LoadCount_WID                 (10)
+  #define DDRDATA2CH0_CR_DLLPITESTANDADC_LoadCount_MSK                 (0x00007FE0)
+  #define DDRDATA2CH0_CR_DLLPITESTANDADC_LoadCount_MAX                 (0x000003FF)
+  #define DDRDATA2CH0_CR_DLLPITESTANDADC_CountStatus_OFF               (15)
+  #define DDRDATA2CH0_CR_DLLPITESTANDADC_CountStatus_WID               (10)
+  #define DDRDATA2CH0_CR_DLLPITESTANDADC_CountStatus_MSK               (0x01FF8000)
+  #define DDRDATA2CH0_CR_DLLPITESTANDADC_CountStatus_MAX               (0x000003FF)
+  #define DDRDATA2CH0_CR_DLLPITESTANDADC_CountStatus_DEF               (0x00000000)
+  #define DDRDATA2CH0_CR_DLLPITESTANDADC_Spare_OFF                     (25)
+  #define DDRDATA2CH0_CR_DLLPITESTANDADC_Spare_WID                     ( 7)
+  #define DDRDATA2CH0_CR_DLLPITESTANDADC_Spare_MSK                     (0xFE000000)
+  #define DDRDATA2CH0_CR_DLLPITESTANDADC_Spare_MAX                     (0x0000007F)
+
+#define DDRDATA2CH0_CR_DDRCRDATAOFFSETCOMP_REG                       (0x0000045C)
+  #define DDRDATA2CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_OFF     ( 0)
+  #define DDRDATA2CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_WID     ( 6)
+  #define DDRDATA2CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MSK     (0x0000003F)
+  #define DDRDATA2CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MAX     (0x0000003F)
+  #define DDRDATA2CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_DEF     (0x00000000)
+  #define DDRDATA2CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_OFF   ( 6)
+  #define DDRDATA2CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_WID   ( 6)
+  #define DDRDATA2CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MSK   (0x00000FC0)
+  #define DDRDATA2CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MAX   (0x0000003F)
+  #define DDRDATA2CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_DEF   (0x00000000)
+  #define DDRDATA2CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_OFF     (12)
+  #define DDRDATA2CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_WID     ( 5)
+  #define DDRDATA2CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MSK     (0x0001F000)
+  #define DDRDATA2CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MAX     (0x0000001F)
+  #define DDRDATA2CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_DEF     (0x00000000)
+  #define DDRDATA2CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_OFF   (17)
+  #define DDRDATA2CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_WID   ( 5)
+  #define DDRDATA2CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MSK   (0x003E0000)
+  #define DDRDATA2CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MAX   (0x0000001F)
+  #define DDRDATA2CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_DEF   (0x00000000)
+  #define DDRDATA2CH0_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_OFF       (22)
+  #define DDRDATA2CH0_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_WID       ( 5)
+  #define DDRDATA2CH0_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_MSK       (0x07C00000)
+  #define DDRDATA2CH0_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_MAX       (0x0000001F)
+  #define DDRDATA2CH0_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_DEF       (0x00000000)
+  #define DDRDATA2CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_OFF  (27)
+  #define DDRDATA2CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_WID  ( 5)
+  #define DDRDATA2CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MSK  (0xF8000000)
+  #define DDRDATA2CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MAX  (0x0000001F)
+  #define DDRDATA2CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_DEF  (0x00000000)
+
+#define DDRDATA2CH0_CR_DDRCRDATACONTROL1_REG                         (0x00000460)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_RefPi_OFF                   ( 0)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_RefPi_WID                   ( 4)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_RefPi_MSK                   (0x0000000F)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_RefPi_MAX                   (0x0000000F)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_RefPi_DEF                   (0x00000000)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_DllMask_OFF                 ( 4)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_DllMask_WID                 ( 2)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_DllMask_MSK                 (0x00000030)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_DllMask_MAX                 (0x00000003)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_DllMask_DEF                 (0x00000000)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_DllWeakLock_OFF             ( 6)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_DllWeakLock_WID             ( 1)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_DllWeakLock_MSK             (0x00000040)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_DllWeakLock_MAX             (0x00000001)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_DllWeakLock_DEF             (0x00000000)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_OFF      ( 7)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_WID      ( 3)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MSK      (0x00000380)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MAX      (0x00000007)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_DEF      (0x00000000)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_OFF               (10)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_WID               ( 3)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_MSK               (0x00001C00)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_MAX               (0x00000007)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_DEF               (0x00000000)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_OdtDelay_OFF                (13)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_OdtDelay_WID                ( 4)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_OdtDelay_MSK                (0x0001E000)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_OdtDelay_MAX                (0x0000000F)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_OdtDelay_DEF                (0x00000000)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_OdtDuration_OFF             (17)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_OdtDuration_WID             ( 3)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_OdtDuration_MSK             (0x000E0000)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_OdtDuration_MAX             (0x00000007)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_OdtDuration_DEF             (0x00000000)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_OFF           (20)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_WID           ( 4)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_MSK           (0x00F00000)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_MAX           (0x0000000F)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_DEF           (0x00000000)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_OFF        (24)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_WID        ( 3)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_MSK        (0x07000000)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_MAX        (0x00000007)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_DEF        (0x00000000)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_BurstEndODTDelay_OFF        (27)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_BurstEndODTDelay_WID        ( 3)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_BurstEndODTDelay_MSK        (0x38000000)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_BurstEndODTDelay_MAX        (0x00000007)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_BurstEndODTDelay_DEF        (0x00000000)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_OFF          (30)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_WID          ( 1)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_MSK          (0x40000000)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_MAX          (0x00000001)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_DEF          (0x00000000)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_Rsvd1_OFF                   (31)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_Rsvd1_WID                   ( 1)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_Rsvd1_MSK                   (0x80000000)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_Rsvd1_MAX                   (0x00000001)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_Rsvd1_DEF                   (0x00000000)
+
+#define DDRDATA2CH0_CR_DDRCRDATACONTROL2_REG                         (0x00000464)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_OFF            ( 0)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_WID            ( 5)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_MSK            (0x0000001F)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_MAX            (0x0000001F)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_DEF            (0x00000000)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_OFF             ( 5)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_WID             ( 1)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_MSK             (0x00000020)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_MAX             (0x00000001)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_DEF             (0x00000000)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_ForceRxOn_OFF               ( 6)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_ForceRxOn_WID               ( 1)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_ForceRxOn_MSK               (0x00000040)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_ForceRxOn_MAX               (0x00000001)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_ForceRxOn_DEF               (0x00000000)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_LeakerComp_OFF              ( 7)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_LeakerComp_WID              ( 2)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_LeakerComp_MSK              (0x00000180)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_LeakerComp_MAX              (0x00000003)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_LeakerComp_DEF              (0x00000000)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_OFF          ( 9)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_WID          ( 4)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_MSK          (0x00001E00)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_MAX          (0x0000000F)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_DEF          (0x00000008)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_OFF             (13)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_WID             ( 5)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_MSK             (0x0003E000)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_MAX             (0x0000001F)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_DEF             (0x00000011)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_OFF             (18)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_WID             ( 1)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_MSK             (0x00040000)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_MAX             (0x00000001)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_DEF             (0x00000000)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_Spare_OFF                   (19)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_Spare_WID                   (13)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_Spare_MSK                   (0xFFF80000)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_Spare_MAX                   (0x00001FFF)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_Spare_DEF                   (0x00000000)
+
+#define DDRDATA2CH0_CR_DDRCRVSSHIORVREFCONTROL_REG                   (0x0000046C)
+  #define DDRDATA2CH0_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_OFF    ( 0)
+  #define DDRDATA2CH0_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_WID    (24)
+  #define DDRDATA2CH0_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_MSK    (0x00FFFFFF)
+  #define DDRDATA2CH0_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_MAX    (0x00FFFFFF)
+  #define DDRDATA2CH0_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_DEF    (0x00000000)
+  #define DDRDATA2CH0_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_OFF        (24)
+  #define DDRDATA2CH0_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_WID        ( 8)
+  #define DDRDATA2CH0_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_MSK        (0xFF000000)
+  #define DDRDATA2CH0_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_MAX        (0x000000FF)
+  #define DDRDATA2CH0_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_DEF        (0x00000000)
+
+#define DDRDATA2CH0_CR_DDRCRDATAOFFSETTRAIN_REG                      (0x00000470)
+  #define DDRDATA2CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_OFF          ( 0)
+  #define DDRDATA2CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_WID          ( 6)
+  #define DDRDATA2CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MSK          (0x0000003F)
+  #define DDRDATA2CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MAX          (0x0000003F)
+  #define DDRDATA2CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_DEF          (0x00000000)
+  #define DDRDATA2CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_OFF          ( 6)
+  #define DDRDATA2CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_WID          ( 6)
+  #define DDRDATA2CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MSK          (0x00000FC0)
+  #define DDRDATA2CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MAX          (0x0000003F)
+  #define DDRDATA2CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_DEF          (0x00000000)
+  #define DDRDATA2CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_OFF           (12)
+  #define DDRDATA2CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_WID           ( 6)
+  #define DDRDATA2CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MSK           (0x0003F000)
+  #define DDRDATA2CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MAX           (0x0000003F)
+  #define DDRDATA2CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_DEF           (0x00000000)
+  #define DDRDATA2CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_OFF          (18)
+  #define DDRDATA2CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_WID          ( 6)
+  #define DDRDATA2CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MSK          (0x00FC0000)
+  #define DDRDATA2CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MAX          (0x0000003F)
+  #define DDRDATA2CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_DEF          (0x00000000)
+  #define DDRDATA2CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_OFF           (24)
+  #define DDRDATA2CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_WID           ( 7)
+  #define DDRDATA2CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MSK           (0x7F000000)
+  #define DDRDATA2CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MAX           (0x0000007F)
+  #define DDRDATA2CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_DEF           (0x00000000)
+  #define DDRDATA2CH0_CR_DDRCRDATAOFFSETTRAIN_Spare_OFF                (31)
+  #define DDRDATA2CH0_CR_DDRCRDATAOFFSETTRAIN_Spare_WID                ( 1)
+  #define DDRDATA2CH0_CR_DDRCRDATAOFFSETTRAIN_Spare_MSK                (0x80000000)
+  #define DDRDATA2CH0_CR_DDRCRDATAOFFSETTRAIN_Spare_MAX                (0x00000001)
+  #define DDRDATA2CH0_CR_DDRCRDATAOFFSETTRAIN_Spare_DEF                (0x00000000)
+
+#define DDRDATA2CH0_CR_DDRCRDATACONTROL0_REG                         (0x00000474)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_OFF          ( 0)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_WID          ( 1)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_MSK          (0x00000001)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_MAX          (0x00000001)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_DEF          (0x00000000)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_OFF          ( 1)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_WID          ( 1)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_MSK          (0x00000002)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_MAX          (0x00000001)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_DEF          (0x00000000)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_OFF          ( 2)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_WID          ( 1)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_MSK          (0x00000004)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_MAX          (0x00000001)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_DEF          (0x00000000)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_OFF    ( 3)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_WID    ( 1)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MSK    (0x00000008)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MAX    (0x00000001)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_DEF    (0x00000000)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_TxOn_OFF                    ( 4)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_TxOn_WID                    ( 1)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_TxOn_MSK                    (0x00000010)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_TxOn_MAX                    (0x00000001)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_TxOn_DEF                    (0x00000000)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RfOn_OFF                    ( 5)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RfOn_WID                    ( 1)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RfOn_MSK                    (0x00000020)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RfOn_MAX                    (0x00000001)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RfOn_DEF                    (0x00000000)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RxPiOn_OFF                  ( 6)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RxPiOn_WID                  ( 1)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RxPiOn_MSK                  (0x00000040)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RxPiOn_MAX                  (0x00000001)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RxPiOn_DEF                  (0x00000000)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_TxPiOn_OFF                  ( 7)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_TxPiOn_WID                  ( 1)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_TxPiOn_MSK                  (0x00000080)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_TxPiOn_MAX                  (0x00000001)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_TxPiOn_DEF                  (0x00000000)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_OFF        ( 8)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_WID        ( 1)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_MSK        (0x00000100)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_MAX        (0x00000001)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_DEF        (0x00000000)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_OFF        ( 9)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_WID        ( 1)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MSK        (0x00000200)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MAX        (0x00000001)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_DEF        (0x00000000)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_TxDisable_OFF               (10)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_TxDisable_WID               ( 1)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_TxDisable_MSK               (0x00000400)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_TxDisable_MAX               (0x00000001)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_TxDisable_DEF               (0x00000000)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RxDisable_OFF               (11)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RxDisable_WID               ( 1)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RxDisable_MSK               (0x00000800)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RxDisable_MAX               (0x00000001)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RxDisable_DEF               (0x00000000)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_TxLong_OFF                  (12)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_TxLong_WID                  ( 1)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_TxLong_MSK                  (0x00001000)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_TxLong_MAX                  (0x00000001)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_TxLong_DEF                  (0x00000000)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_OFF               (13)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_WID               ( 2)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_MSK               (0x00006000)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_MAX               (0x00000003)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_DEF               (0x00000000)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RxReadPointer_OFF           (15)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RxReadPointer_WID           ( 3)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RxReadPointer_MSK           (0x00038000)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RxReadPointer_MAX           (0x00000007)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RxReadPointer_DEF           (0x00000000)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_DriverSegmentEnable_OFF     (18)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_DriverSegmentEnable_WID     ( 1)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_DriverSegmentEnable_MSK     (0x00040000)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_DriverSegmentEnable_MAX     (0x00000001)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_DriverSegmentEnable_DEF     (0x00000000)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_DataVccddqHi_OFF            (19)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_DataVccddqHi_WID            ( 1)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_DataVccddqHi_MSK            (0x00080000)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_DataVccddqHi_MAX            (0x00000001)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_DataVccddqHi_DEF            (0x00000000)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_ReadRFRd_OFF                (20)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_ReadRFRd_WID                ( 1)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_ReadRFRd_MSK                (0x00100000)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_ReadRFRd_MAX                (0x00000001)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_ReadRFRd_DEF                (0x00000000)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_ReadRFWr_OFF                (21)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_ReadRFWr_WID                ( 1)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_ReadRFWr_MSK                (0x00200000)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_ReadRFWr_MAX                (0x00000001)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_ReadRFWr_DEF                (0x00000000)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_ReadRFRank_OFF              (22)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_ReadRFRank_WID              ( 2)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_ReadRFRank_MSK              (0x00C00000)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_ReadRFRank_MAX              (0x00000003)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_ReadRFRank_DEF              (0x00000000)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_OFF              (24)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_WID              ( 1)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_MSK              (0x01000000)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_MAX              (0x00000001)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_DEF              (0x00000000)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_OdtSampOff_OFF              (25)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_OdtSampOff_WID              ( 1)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_OdtSampOff_MSK              (0x02000000)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_OdtSampOff_MAX              (0x00000001)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_OdtSampOff_DEF              (0x00000000)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_OFF        (26)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_WID        ( 1)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_MSK        (0x04000000)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_MAX        (0x00000001)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_DEF        (0x00000000)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_OFF         (27)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_WID         ( 1)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MSK         (0x08000000)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MAX         (0x00000001)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_DEF         (0x00000000)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_OFF              (28)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_WID              ( 1)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_MSK              (0x10000000)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_MAX              (0x00000001)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_DEF              (0x00000000)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_EnReadPreamble_OFF          (29)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_EnReadPreamble_WID          ( 1)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_EnReadPreamble_MSK          (0x20000000)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_EnReadPreamble_MAX          (0x00000001)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_EnReadPreamble_DEF          (0x00000000)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_OFF         (30)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_WID         ( 1)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MSK         (0x40000000)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MAX         (0x00000001)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_DEF         (0x00000000)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_OFF            (31)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_WID            ( 1)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_MSK            (0x80000000)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_MAX            (0x00000001)
+  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_DEF            (0x00000000)
+
+#define DDRDATA2CH0_CR_DDRCRVREFADJUST1_REG                          (0x00000478)
+  #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_CAVrefCtl_OFF                ( 0)
+  #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_CAVrefCtl_WID                ( 7)
+  #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_CAVrefCtl_MSK                (0x0000007F)
+  #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_CAVrefCtl_MAX                (0x0000007F)
+  #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_CAVrefCtl_DEF                (0x00000000)
+  #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_Ch1VrefCtl_OFF               ( 7)
+  #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_Ch1VrefCtl_WID               ( 7)
+  #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_Ch1VrefCtl_MSK               (0x00003F80)
+  #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_Ch1VrefCtl_MAX               (0x0000007F)
+  #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_Ch1VrefCtl_DEF               (0x00000000)
+  #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_Ch0VrefCtl_OFF               (14)
+  #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_Ch0VrefCtl_WID               ( 7)
+  #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_Ch0VrefCtl_MSK               (0x001FC000)
+  #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_Ch0VrefCtl_MAX               (0x0000007F)
+  #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_Ch0VrefCtl_DEF               (0x00000000)
+  #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCA_OFF             (21)
+  #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCA_WID             ( 1)
+  #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCA_MSK             (0x00200000)
+  #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCA_MAX             (0x00000001)
+  #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCA_DEF             (0x00000000)
+  #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_OFF            (22)
+  #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_WID            ( 1)
+  #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_MSK            (0x00400000)
+  #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_MAX            (0x00000001)
+  #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_DEF            (0x00000000)
+  #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_OFF            (23)
+  #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_WID            ( 1)
+  #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_MSK            (0x00800000)
+  #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_MAX            (0x00000001)
+  #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_DEF            (0x00000000)
+  #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_HiZTimerCtrl_OFF             (24)
+  #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_HiZTimerCtrl_WID             ( 2)
+  #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_HiZTimerCtrl_MSK             (0x03000000)
+  #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_HiZTimerCtrl_MAX             (0x00000003)
+  #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_HiZTimerCtrl_DEF             (0x00000000)
+  #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_OFF            (26)
+  #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_WID            ( 1)
+  #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_MSK            (0x04000000)
+  #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_MAX            (0x00000001)
+  #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_DEF            (0x00000000)
+  #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_Rsvd_OFF                     (27)
+  #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_Rsvd_WID                     ( 2)
+  #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_Rsvd_MSK                     (0x18000000)
+  #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_Rsvd_MAX                     (0x00000003)
+  #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_Rsvd_DEF                     (0x00000000)
+  #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_caSlowBW_OFF                 (29)
+  #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_caSlowBW_WID                 ( 1)
+  #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_caSlowBW_MSK                 (0x20000000)
+  #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_caSlowBW_MAX                 (0x00000001)
+  #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_caSlowBW_DEF                 (0x00000000)
+  #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_ch0SlowBW_OFF                (30)
+  #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_ch0SlowBW_WID                ( 1)
+  #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_ch0SlowBW_MSK                (0x40000000)
+  #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_ch0SlowBW_MAX                (0x00000001)
+  #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_ch0SlowBW_DEF                (0x00000000)
+  #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_ch1SlowBW_OFF                (31)
+  #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_ch1SlowBW_WID                ( 1)
+  #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_ch1SlowBW_MSK                (0x80000000)
+  #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_ch1SlowBW_MAX                (0x00000001)
+  #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_ch1SlowBW_DEF                (0x00000000)
+
+#define DDRDATA2CH1_CR_RXTRAINRANK0_REG                              (0x00000500)
+  #define DDRDATA2CH1_CR_RXTRAINRANK0_RxRcvEnPi_OFF                    ( 0)
+  #define DDRDATA2CH1_CR_RXTRAINRANK0_RxRcvEnPi_WID                    ( 9)
+  #define DDRDATA2CH1_CR_RXTRAINRANK0_RxRcvEnPi_MSK                    (0x000001FF)
+  #define DDRDATA2CH1_CR_RXTRAINRANK0_RxRcvEnPi_MAX                    (0x000001FF)
+  #define DDRDATA2CH1_CR_RXTRAINRANK0_RxDqsPPi_OFF                     ( 9)
+  #define DDRDATA2CH1_CR_RXTRAINRANK0_RxDqsPPi_WID                     ( 6)
+  #define DDRDATA2CH1_CR_RXTRAINRANK0_RxDqsPPi_MSK                     (0x00007E00)
+  #define DDRDATA2CH1_CR_RXTRAINRANK0_RxDqsPPi_MAX                     (0x0000003F)
+  #define DDRDATA2CH1_CR_RXTRAINRANK0_RxEq_OFF                         (15)
+  #define DDRDATA2CH1_CR_RXTRAINRANK0_RxEq_WID                         ( 5)
+  #define DDRDATA2CH1_CR_RXTRAINRANK0_RxEq_MSK                         (0x000F8000)
+  #define DDRDATA2CH1_CR_RXTRAINRANK0_RxEq_MAX                         (0x0000001F)
+  #define DDRDATA2CH1_CR_RXTRAINRANK0_RxDqsNPi_OFF                     (20)
+  #define DDRDATA2CH1_CR_RXTRAINRANK0_RxDqsNPi_WID                     ( 6)
+  #define DDRDATA2CH1_CR_RXTRAINRANK0_RxDqsNPi_MSK                     (0x03F00000)
+  #define DDRDATA2CH1_CR_RXTRAINRANK0_RxDqsNPi_MAX                     (0x0000003F)
+  #define DDRDATA2CH1_CR_RXTRAINRANK0_RxVref_OFF                       (26)
+  #define DDRDATA2CH1_CR_RXTRAINRANK0_RxVref_WID                       ( 6)
+  #define DDRDATA2CH1_CR_RXTRAINRANK0_RxVref_MSK                       (0xFC000000)
+  #define DDRDATA2CH1_CR_RXTRAINRANK0_RxVref_MAX                       (0x0000003F)
+
+#define DDRDATA2CH1_CR_RXTRAINRANK1_REG                              (0x00000504)
+  #define DDRDATA2CH1_CR_RXTRAINRANK1_RxRcvEnPi_OFF                    ( 0)
+  #define DDRDATA2CH1_CR_RXTRAINRANK1_RxRcvEnPi_WID                    ( 9)
+  #define DDRDATA2CH1_CR_RXTRAINRANK1_RxRcvEnPi_MSK                    (0x000001FF)
+  #define DDRDATA2CH1_CR_RXTRAINRANK1_RxRcvEnPi_MAX                    (0x000001FF)
+  #define DDRDATA2CH1_CR_RXTRAINRANK1_RxDqsPPi_OFF                     ( 9)
+  #define DDRDATA2CH1_CR_RXTRAINRANK1_RxDqsPPi_WID                     ( 6)
+  #define DDRDATA2CH1_CR_RXTRAINRANK1_RxDqsPPi_MSK                     (0x00007E00)
+  #define DDRDATA2CH1_CR_RXTRAINRANK1_RxDqsPPi_MAX                     (0x0000003F)
+  #define DDRDATA2CH1_CR_RXTRAINRANK1_RxEq_OFF                         (15)
+  #define DDRDATA2CH1_CR_RXTRAINRANK1_RxEq_WID                         ( 5)
+  #define DDRDATA2CH1_CR_RXTRAINRANK1_RxEq_MSK                         (0x000F8000)
+  #define DDRDATA2CH1_CR_RXTRAINRANK1_RxEq_MAX                         (0x0000001F)
+  #define DDRDATA2CH1_CR_RXTRAINRANK1_RxDqsNPi_OFF                     (20)
+  #define DDRDATA2CH1_CR_RXTRAINRANK1_RxDqsNPi_WID                     ( 6)
+  #define DDRDATA2CH1_CR_RXTRAINRANK1_RxDqsNPi_MSK                     (0x03F00000)
+  #define DDRDATA2CH1_CR_RXTRAINRANK1_RxDqsNPi_MAX                     (0x0000003F)
+  #define DDRDATA2CH1_CR_RXTRAINRANK1_RxVref_OFF                       (26)
+  #define DDRDATA2CH1_CR_RXTRAINRANK1_RxVref_WID                       ( 6)
+  #define DDRDATA2CH1_CR_RXTRAINRANK1_RxVref_MSK                       (0xFC000000)
+  #define DDRDATA2CH1_CR_RXTRAINRANK1_RxVref_MAX                       (0x0000003F)
+
+#define DDRDATA2CH1_CR_RXTRAINRANK2_REG                              (0x00000508)
+  #define DDRDATA2CH1_CR_RXTRAINRANK2_RxRcvEnPi_OFF                    ( 0)
+  #define DDRDATA2CH1_CR_RXTRAINRANK2_RxRcvEnPi_WID                    ( 9)
+  #define DDRDATA2CH1_CR_RXTRAINRANK2_RxRcvEnPi_MSK                    (0x000001FF)
+  #define DDRDATA2CH1_CR_RXTRAINRANK2_RxRcvEnPi_MAX                    (0x000001FF)
+  #define DDRDATA2CH1_CR_RXTRAINRANK2_RxDqsPPi_OFF                     ( 9)
+  #define DDRDATA2CH1_CR_RXTRAINRANK2_RxDqsPPi_WID                     ( 6)
+  #define DDRDATA2CH1_CR_RXTRAINRANK2_RxDqsPPi_MSK                     (0x00007E00)
+  #define DDRDATA2CH1_CR_RXTRAINRANK2_RxDqsPPi_MAX                     (0x0000003F)
+  #define DDRDATA2CH1_CR_RXTRAINRANK2_RxEq_OFF                         (15)
+  #define DDRDATA2CH1_CR_RXTRAINRANK2_RxEq_WID                         ( 5)
+  #define DDRDATA2CH1_CR_RXTRAINRANK2_RxEq_MSK                         (0x000F8000)
+  #define DDRDATA2CH1_CR_RXTRAINRANK2_RxEq_MAX                         (0x0000001F)
+  #define DDRDATA2CH1_CR_RXTRAINRANK2_RxDqsNPi_OFF                     (20)
+  #define DDRDATA2CH1_CR_RXTRAINRANK2_RxDqsNPi_WID                     ( 6)
+  #define DDRDATA2CH1_CR_RXTRAINRANK2_RxDqsNPi_MSK                     (0x03F00000)
+  #define DDRDATA2CH1_CR_RXTRAINRANK2_RxDqsNPi_MAX                     (0x0000003F)
+  #define DDRDATA2CH1_CR_RXTRAINRANK2_RxVref_OFF                       (26)
+  #define DDRDATA2CH1_CR_RXTRAINRANK2_RxVref_WID                       ( 6)
+  #define DDRDATA2CH1_CR_RXTRAINRANK2_RxVref_MSK                       (0xFC000000)
+  #define DDRDATA2CH1_CR_RXTRAINRANK2_RxVref_MAX                       (0x0000003F)
+
+#define DDRDATA2CH1_CR_RXTRAINRANK3_REG                              (0x0000050C)
+  #define DDRDATA2CH1_CR_RXTRAINRANK3_RxRcvEnPi_OFF                    ( 0)
+  #define DDRDATA2CH1_CR_RXTRAINRANK3_RxRcvEnPi_WID                    ( 9)
+  #define DDRDATA2CH1_CR_RXTRAINRANK3_RxRcvEnPi_MSK                    (0x000001FF)
+  #define DDRDATA2CH1_CR_RXTRAINRANK3_RxRcvEnPi_MAX                    (0x000001FF)
+  #define DDRDATA2CH1_CR_RXTRAINRANK3_RxDqsPPi_OFF                     ( 9)
+  #define DDRDATA2CH1_CR_RXTRAINRANK3_RxDqsPPi_WID                     ( 6)
+  #define DDRDATA2CH1_CR_RXTRAINRANK3_RxDqsPPi_MSK                     (0x00007E00)
+  #define DDRDATA2CH1_CR_RXTRAINRANK3_RxDqsPPi_MAX                     (0x0000003F)
+  #define DDRDATA2CH1_CR_RXTRAINRANK3_RxEq_OFF                         (15)
+  #define DDRDATA2CH1_CR_RXTRAINRANK3_RxEq_WID                         ( 5)
+  #define DDRDATA2CH1_CR_RXTRAINRANK3_RxEq_MSK                         (0x000F8000)
+  #define DDRDATA2CH1_CR_RXTRAINRANK3_RxEq_MAX                         (0x0000001F)
+  #define DDRDATA2CH1_CR_RXTRAINRANK3_RxDqsNPi_OFF                     (20)
+  #define DDRDATA2CH1_CR_RXTRAINRANK3_RxDqsNPi_WID                     ( 6)
+  #define DDRDATA2CH1_CR_RXTRAINRANK3_RxDqsNPi_MSK                     (0x03F00000)
+  #define DDRDATA2CH1_CR_RXTRAINRANK3_RxDqsNPi_MAX                     (0x0000003F)
+  #define DDRDATA2CH1_CR_RXTRAINRANK3_RxVref_OFF                       (26)
+  #define DDRDATA2CH1_CR_RXTRAINRANK3_RxVref_WID                       ( 6)
+  #define DDRDATA2CH1_CR_RXTRAINRANK3_RxVref_MSK                       (0xFC000000)
+  #define DDRDATA2CH1_CR_RXTRAINRANK3_RxVref_MAX                       (0x0000003F)
+
+#define DDRDATA2CH1_CR_RXPERBITRANK0_REG                             (0x00000510)
+  #define DDRDATA2CH1_CR_RXPERBITRANK0_Lane0_OFF                       ( 0)
+  #define DDRDATA2CH1_CR_RXPERBITRANK0_Lane0_WID                       ( 4)
+  #define DDRDATA2CH1_CR_RXPERBITRANK0_Lane0_MSK                       (0x0000000F)
+  #define DDRDATA2CH1_CR_RXPERBITRANK0_Lane0_MAX                       (0x0000000F)
+  #define DDRDATA2CH1_CR_RXPERBITRANK0_Lane1_OFF                       ( 4)
+  #define DDRDATA2CH1_CR_RXPERBITRANK0_Lane1_WID                       ( 4)
+  #define DDRDATA2CH1_CR_RXPERBITRANK0_Lane1_MSK                       (0x000000F0)
+  #define DDRDATA2CH1_CR_RXPERBITRANK0_Lane1_MAX                       (0x0000000F)
+  #define DDRDATA2CH1_CR_RXPERBITRANK0_Lane2_OFF                       ( 8)
+  #define DDRDATA2CH1_CR_RXPERBITRANK0_Lane2_WID                       ( 4)
+  #define DDRDATA2CH1_CR_RXPERBITRANK0_Lane2_MSK                       (0x00000F00)
+  #define DDRDATA2CH1_CR_RXPERBITRANK0_Lane2_MAX                       (0x0000000F)
+  #define DDRDATA2CH1_CR_RXPERBITRANK0_Lane3_OFF                       (12)
+  #define DDRDATA2CH1_CR_RXPERBITRANK0_Lane3_WID                       ( 4)
+  #define DDRDATA2CH1_CR_RXPERBITRANK0_Lane3_MSK                       (0x0000F000)
+  #define DDRDATA2CH1_CR_RXPERBITRANK0_Lane3_MAX                       (0x0000000F)
+  #define DDRDATA2CH1_CR_RXPERBITRANK0_Lane4_OFF                       (16)
+  #define DDRDATA2CH1_CR_RXPERBITRANK0_Lane4_WID                       ( 4)
+  #define DDRDATA2CH1_CR_RXPERBITRANK0_Lane4_MSK                       (0x000F0000)
+  #define DDRDATA2CH1_CR_RXPERBITRANK0_Lane4_MAX                       (0x0000000F)
+  #define DDRDATA2CH1_CR_RXPERBITRANK0_Lane5_OFF                       (20)
+  #define DDRDATA2CH1_CR_RXPERBITRANK0_Lane5_WID                       ( 4)
+  #define DDRDATA2CH1_CR_RXPERBITRANK0_Lane5_MSK                       (0x00F00000)
+  #define DDRDATA2CH1_CR_RXPERBITRANK0_Lane5_MAX                       (0x0000000F)
+  #define DDRDATA2CH1_CR_RXPERBITRANK0_Lane6_OFF                       (24)
+  #define DDRDATA2CH1_CR_RXPERBITRANK0_Lane6_WID                       ( 4)
+  #define DDRDATA2CH1_CR_RXPERBITRANK0_Lane6_MSK                       (0x0F000000)
+  #define DDRDATA2CH1_CR_RXPERBITRANK0_Lane6_MAX                       (0x0000000F)
+  #define DDRDATA2CH1_CR_RXPERBITRANK0_Lane7_OFF                       (28)
+  #define DDRDATA2CH1_CR_RXPERBITRANK0_Lane7_WID                       ( 4)
+  #define DDRDATA2CH1_CR_RXPERBITRANK0_Lane7_MSK                       (0xF0000000)
+  #define DDRDATA2CH1_CR_RXPERBITRANK0_Lane7_MAX                       (0x0000000F)
+
+#define DDRDATA2CH1_CR_RXPERBITRANK1_REG                             (0x00000514)
+  #define DDRDATA2CH1_CR_RXPERBITRANK1_Lane0_OFF                       ( 0)
+  #define DDRDATA2CH1_CR_RXPERBITRANK1_Lane0_WID                       ( 4)
+  #define DDRDATA2CH1_CR_RXPERBITRANK1_Lane0_MSK                       (0x0000000F)
+  #define DDRDATA2CH1_CR_RXPERBITRANK1_Lane0_MAX                       (0x0000000F)
+  #define DDRDATA2CH1_CR_RXPERBITRANK1_Lane1_OFF                       ( 4)
+  #define DDRDATA2CH1_CR_RXPERBITRANK1_Lane1_WID                       ( 4)
+  #define DDRDATA2CH1_CR_RXPERBITRANK1_Lane1_MSK                       (0x000000F0)
+  #define DDRDATA2CH1_CR_RXPERBITRANK1_Lane1_MAX                       (0x0000000F)
+  #define DDRDATA2CH1_CR_RXPERBITRANK1_Lane2_OFF                       ( 8)
+  #define DDRDATA2CH1_CR_RXPERBITRANK1_Lane2_WID                       ( 4)
+  #define DDRDATA2CH1_CR_RXPERBITRANK1_Lane2_MSK                       (0x00000F00)
+  #define DDRDATA2CH1_CR_RXPERBITRANK1_Lane2_MAX                       (0x0000000F)
+  #define DDRDATA2CH1_CR_RXPERBITRANK1_Lane3_OFF                       (12)
+  #define DDRDATA2CH1_CR_RXPERBITRANK1_Lane3_WID                       ( 4)
+  #define DDRDATA2CH1_CR_RXPERBITRANK1_Lane3_MSK                       (0x0000F000)
+  #define DDRDATA2CH1_CR_RXPERBITRANK1_Lane3_MAX                       (0x0000000F)
+  #define DDRDATA2CH1_CR_RXPERBITRANK1_Lane4_OFF                       (16)
+  #define DDRDATA2CH1_CR_RXPERBITRANK1_Lane4_WID                       ( 4)
+  #define DDRDATA2CH1_CR_RXPERBITRANK1_Lane4_MSK                       (0x000F0000)
+  #define DDRDATA2CH1_CR_RXPERBITRANK1_Lane4_MAX                       (0x0000000F)
+  #define DDRDATA2CH1_CR_RXPERBITRANK1_Lane5_OFF                       (20)
+  #define DDRDATA2CH1_CR_RXPERBITRANK1_Lane5_WID                       ( 4)
+  #define DDRDATA2CH1_CR_RXPERBITRANK1_Lane5_MSK                       (0x00F00000)
+  #define DDRDATA2CH1_CR_RXPERBITRANK1_Lane5_MAX                       (0x0000000F)
+  #define DDRDATA2CH1_CR_RXPERBITRANK1_Lane6_OFF                       (24)
+  #define DDRDATA2CH1_CR_RXPERBITRANK1_Lane6_WID                       ( 4)
+  #define DDRDATA2CH1_CR_RXPERBITRANK1_Lane6_MSK                       (0x0F000000)
+  #define DDRDATA2CH1_CR_RXPERBITRANK1_Lane6_MAX                       (0x0000000F)
+  #define DDRDATA2CH1_CR_RXPERBITRANK1_Lane7_OFF                       (28)
+  #define DDRDATA2CH1_CR_RXPERBITRANK1_Lane7_WID                       ( 4)
+  #define DDRDATA2CH1_CR_RXPERBITRANK1_Lane7_MSK                       (0xF0000000)
+  #define DDRDATA2CH1_CR_RXPERBITRANK1_Lane7_MAX                       (0x0000000F)
+
+#define DDRDATA2CH1_CR_RXPERBITRANK2_REG                             (0x00000518)
+  #define DDRDATA2CH1_CR_RXPERBITRANK2_Lane0_OFF                       ( 0)
+  #define DDRDATA2CH1_CR_RXPERBITRANK2_Lane0_WID                       ( 4)
+  #define DDRDATA2CH1_CR_RXPERBITRANK2_Lane0_MSK                       (0x0000000F)
+  #define DDRDATA2CH1_CR_RXPERBITRANK2_Lane0_MAX                       (0x0000000F)
+  #define DDRDATA2CH1_CR_RXPERBITRANK2_Lane1_OFF                       ( 4)
+  #define DDRDATA2CH1_CR_RXPERBITRANK2_Lane1_WID                       ( 4)
+  #define DDRDATA2CH1_CR_RXPERBITRANK2_Lane1_MSK                       (0x000000F0)
+  #define DDRDATA2CH1_CR_RXPERBITRANK2_Lane1_MAX                       (0x0000000F)
+  #define DDRDATA2CH1_CR_RXPERBITRANK2_Lane2_OFF                       ( 8)
+  #define DDRDATA2CH1_CR_RXPERBITRANK2_Lane2_WID                       ( 4)
+  #define DDRDATA2CH1_CR_RXPERBITRANK2_Lane2_MSK                       (0x00000F00)
+  #define DDRDATA2CH1_CR_RXPERBITRANK2_Lane2_MAX                       (0x0000000F)
+  #define DDRDATA2CH1_CR_RXPERBITRANK2_Lane3_OFF                       (12)
+  #define DDRDATA2CH1_CR_RXPERBITRANK2_Lane3_WID                       ( 4)
+  #define DDRDATA2CH1_CR_RXPERBITRANK2_Lane3_MSK                       (0x0000F000)
+  #define DDRDATA2CH1_CR_RXPERBITRANK2_Lane3_MAX                       (0x0000000F)
+  #define DDRDATA2CH1_CR_RXPERBITRANK2_Lane4_OFF                       (16)
+  #define DDRDATA2CH1_CR_RXPERBITRANK2_Lane4_WID                       ( 4)
+  #define DDRDATA2CH1_CR_RXPERBITRANK2_Lane4_MSK                       (0x000F0000)
+  #define DDRDATA2CH1_CR_RXPERBITRANK2_Lane4_MAX                       (0x0000000F)
+  #define DDRDATA2CH1_CR_RXPERBITRANK2_Lane5_OFF                       (20)
+  #define DDRDATA2CH1_CR_RXPERBITRANK2_Lane5_WID                       ( 4)
+  #define DDRDATA2CH1_CR_RXPERBITRANK2_Lane5_MSK                       (0x00F00000)
+  #define DDRDATA2CH1_CR_RXPERBITRANK2_Lane5_MAX                       (0x0000000F)
+  #define DDRDATA2CH1_CR_RXPERBITRANK2_Lane6_OFF                       (24)
+  #define DDRDATA2CH1_CR_RXPERBITRANK2_Lane6_WID                       ( 4)
+  #define DDRDATA2CH1_CR_RXPERBITRANK2_Lane6_MSK                       (0x0F000000)
+  #define DDRDATA2CH1_CR_RXPERBITRANK2_Lane6_MAX                       (0x0000000F)
+  #define DDRDATA2CH1_CR_RXPERBITRANK2_Lane7_OFF                       (28)
+  #define DDRDATA2CH1_CR_RXPERBITRANK2_Lane7_WID                       ( 4)
+  #define DDRDATA2CH1_CR_RXPERBITRANK2_Lane7_MSK                       (0xF0000000)
+  #define DDRDATA2CH1_CR_RXPERBITRANK2_Lane7_MAX                       (0x0000000F)
+
+#define DDRDATA2CH1_CR_RXPERBITRANK3_REG                             (0x0000051C)
+  #define DDRDATA2CH1_CR_RXPERBITRANK3_Lane0_OFF                       ( 0)
+  #define DDRDATA2CH1_CR_RXPERBITRANK3_Lane0_WID                       ( 4)
+  #define DDRDATA2CH1_CR_RXPERBITRANK3_Lane0_MSK                       (0x0000000F)
+  #define DDRDATA2CH1_CR_RXPERBITRANK3_Lane0_MAX                       (0x0000000F)
+  #define DDRDATA2CH1_CR_RXPERBITRANK3_Lane1_OFF                       ( 4)
+  #define DDRDATA2CH1_CR_RXPERBITRANK3_Lane1_WID                       ( 4)
+  #define DDRDATA2CH1_CR_RXPERBITRANK3_Lane1_MSK                       (0x000000F0)
+  #define DDRDATA2CH1_CR_RXPERBITRANK3_Lane1_MAX                       (0x0000000F)
+  #define DDRDATA2CH1_CR_RXPERBITRANK3_Lane2_OFF                       ( 8)
+  #define DDRDATA2CH1_CR_RXPERBITRANK3_Lane2_WID                       ( 4)
+  #define DDRDATA2CH1_CR_RXPERBITRANK3_Lane2_MSK                       (0x00000F00)
+  #define DDRDATA2CH1_CR_RXPERBITRANK3_Lane2_MAX                       (0x0000000F)
+  #define DDRDATA2CH1_CR_RXPERBITRANK3_Lane3_OFF                       (12)
+  #define DDRDATA2CH1_CR_RXPERBITRANK3_Lane3_WID                       ( 4)
+  #define DDRDATA2CH1_CR_RXPERBITRANK3_Lane3_MSK                       (0x0000F000)
+  #define DDRDATA2CH1_CR_RXPERBITRANK3_Lane3_MAX                       (0x0000000F)
+  #define DDRDATA2CH1_CR_RXPERBITRANK3_Lane4_OFF                       (16)
+  #define DDRDATA2CH1_CR_RXPERBITRANK3_Lane4_WID                       ( 4)
+  #define DDRDATA2CH1_CR_RXPERBITRANK3_Lane4_MSK                       (0x000F0000)
+  #define DDRDATA2CH1_CR_RXPERBITRANK3_Lane4_MAX                       (0x0000000F)
+  #define DDRDATA2CH1_CR_RXPERBITRANK3_Lane5_OFF                       (20)
+  #define DDRDATA2CH1_CR_RXPERBITRANK3_Lane5_WID                       ( 4)
+  #define DDRDATA2CH1_CR_RXPERBITRANK3_Lane5_MSK                       (0x00F00000)
+  #define DDRDATA2CH1_CR_RXPERBITRANK3_Lane5_MAX                       (0x0000000F)
+  #define DDRDATA2CH1_CR_RXPERBITRANK3_Lane6_OFF                       (24)
+  #define DDRDATA2CH1_CR_RXPERBITRANK3_Lane6_WID                       ( 4)
+  #define DDRDATA2CH1_CR_RXPERBITRANK3_Lane6_MSK                       (0x0F000000)
+  #define DDRDATA2CH1_CR_RXPERBITRANK3_Lane6_MAX                       (0x0000000F)
+  #define DDRDATA2CH1_CR_RXPERBITRANK3_Lane7_OFF                       (28)
+  #define DDRDATA2CH1_CR_RXPERBITRANK3_Lane7_WID                       ( 4)
+  #define DDRDATA2CH1_CR_RXPERBITRANK3_Lane7_MSK                       (0xF0000000)
+  #define DDRDATA2CH1_CR_RXPERBITRANK3_Lane7_MAX                       (0x0000000F)
+
+#define DDRDATA2CH1_CR_TXTRAINRANK0_REG                              (0x00000520)
+  #define DDRDATA2CH1_CR_TXTRAINRANK0_TxDqDelay_OFF                    ( 0)
+  #define DDRDATA2CH1_CR_TXTRAINRANK0_TxDqDelay_WID                    ( 9)
+  #define DDRDATA2CH1_CR_TXTRAINRANK0_TxDqDelay_MSK                    (0x000001FF)
+  #define DDRDATA2CH1_CR_TXTRAINRANK0_TxDqDelay_MAX                    (0x000001FF)
+  #define DDRDATA2CH1_CR_TXTRAINRANK0_TxDqsDelay_OFF                   ( 9)
+  #define DDRDATA2CH1_CR_TXTRAINRANK0_TxDqsDelay_WID                   ( 9)
+  #define DDRDATA2CH1_CR_TXTRAINRANK0_TxDqsDelay_MSK                   (0x0003FE00)
+  #define DDRDATA2CH1_CR_TXTRAINRANK0_TxDqsDelay_MAX                   (0x000001FF)
+  #define DDRDATA2CH1_CR_TXTRAINRANK0_Spare0_OFF                       (18)
+  #define DDRDATA2CH1_CR_TXTRAINRANK0_Spare0_WID                       ( 2)
+  #define DDRDATA2CH1_CR_TXTRAINRANK0_Spare0_MSK                       (0x000C0000)
+  #define DDRDATA2CH1_CR_TXTRAINRANK0_Spare0_MAX                       (0x00000003)
+  #define DDRDATA2CH1_CR_TXTRAINRANK0_TxEqualization_OFF               (20)
+  #define DDRDATA2CH1_CR_TXTRAINRANK0_TxEqualization_WID               ( 6)
+  #define DDRDATA2CH1_CR_TXTRAINRANK0_TxEqualization_MSK               (0x03F00000)
+  #define DDRDATA2CH1_CR_TXTRAINRANK0_TxEqualization_MAX               (0x0000003F)
+  #define DDRDATA2CH1_CR_TXTRAINRANK0_Spare1_OFF                       (26)
+  #define DDRDATA2CH1_CR_TXTRAINRANK0_Spare1_WID                       ( 6)
+  #define DDRDATA2CH1_CR_TXTRAINRANK0_Spare1_MSK                       (0xFC000000)
+  #define DDRDATA2CH1_CR_TXTRAINRANK0_Spare1_MAX                       (0x0000003F)
+
+#define DDRDATA2CH1_CR_TXTRAINRANK1_REG                              (0x00000524)
+  #define DDRDATA2CH1_CR_TXTRAINRANK1_TxDqDelay_OFF                    ( 0)
+  #define DDRDATA2CH1_CR_TXTRAINRANK1_TxDqDelay_WID                    ( 9)
+  #define DDRDATA2CH1_CR_TXTRAINRANK1_TxDqDelay_MSK                    (0x000001FF)
+  #define DDRDATA2CH1_CR_TXTRAINRANK1_TxDqDelay_MAX                    (0x000001FF)
+  #define DDRDATA2CH1_CR_TXTRAINRANK1_TxDqsDelay_OFF                   ( 9)
+  #define DDRDATA2CH1_CR_TXTRAINRANK1_TxDqsDelay_WID                   ( 9)
+  #define DDRDATA2CH1_CR_TXTRAINRANK1_TxDqsDelay_MSK                   (0x0003FE00)
+  #define DDRDATA2CH1_CR_TXTRAINRANK1_TxDqsDelay_MAX                   (0x000001FF)
+  #define DDRDATA2CH1_CR_TXTRAINRANK1_Spare0_OFF                       (18)
+  #define DDRDATA2CH1_CR_TXTRAINRANK1_Spare0_WID                       ( 2)
+  #define DDRDATA2CH1_CR_TXTRAINRANK1_Spare0_MSK                       (0x000C0000)
+  #define DDRDATA2CH1_CR_TXTRAINRANK1_Spare0_MAX                       (0x00000003)
+  #define DDRDATA2CH1_CR_TXTRAINRANK1_TxEqualization_OFF               (20)
+  #define DDRDATA2CH1_CR_TXTRAINRANK1_TxEqualization_WID               ( 6)
+  #define DDRDATA2CH1_CR_TXTRAINRANK1_TxEqualization_MSK               (0x03F00000)
+  #define DDRDATA2CH1_CR_TXTRAINRANK1_TxEqualization_MAX               (0x0000003F)
+  #define DDRDATA2CH1_CR_TXTRAINRANK1_Spare1_OFF                       (26)
+  #define DDRDATA2CH1_CR_TXTRAINRANK1_Spare1_WID                       ( 6)
+  #define DDRDATA2CH1_CR_TXTRAINRANK1_Spare1_MSK                       (0xFC000000)
+  #define DDRDATA2CH1_CR_TXTRAINRANK1_Spare1_MAX                       (0x0000003F)
+
+#define DDRDATA2CH1_CR_TXTRAINRANK2_REG                              (0x00000528)
+  #define DDRDATA2CH1_CR_TXTRAINRANK2_TxDqDelay_OFF                    ( 0)
+  #define DDRDATA2CH1_CR_TXTRAINRANK2_TxDqDelay_WID                    ( 9)
+  #define DDRDATA2CH1_CR_TXTRAINRANK2_TxDqDelay_MSK                    (0x000001FF)
+  #define DDRDATA2CH1_CR_TXTRAINRANK2_TxDqDelay_MAX                    (0x000001FF)
+  #define DDRDATA2CH1_CR_TXTRAINRANK2_TxDqsDelay_OFF                   ( 9)
+  #define DDRDATA2CH1_CR_TXTRAINRANK2_TxDqsDelay_WID                   ( 9)
+  #define DDRDATA2CH1_CR_TXTRAINRANK2_TxDqsDelay_MSK                   (0x0003FE00)
+  #define DDRDATA2CH1_CR_TXTRAINRANK2_TxDqsDelay_MAX                   (0x000001FF)
+  #define DDRDATA2CH1_CR_TXTRAINRANK2_Spare0_OFF                       (18)
+  #define DDRDATA2CH1_CR_TXTRAINRANK2_Spare0_WID                       ( 2)
+  #define DDRDATA2CH1_CR_TXTRAINRANK2_Spare0_MSK                       (0x000C0000)
+  #define DDRDATA2CH1_CR_TXTRAINRANK2_Spare0_MAX                       (0x00000003)
+  #define DDRDATA2CH1_CR_TXTRAINRANK2_TxEqualization_OFF               (20)
+  #define DDRDATA2CH1_CR_TXTRAINRANK2_TxEqualization_WID               ( 6)
+  #define DDRDATA2CH1_CR_TXTRAINRANK2_TxEqualization_MSK               (0x03F00000)
+  #define DDRDATA2CH1_CR_TXTRAINRANK2_TxEqualization_MAX               (0x0000003F)
+  #define DDRDATA2CH1_CR_TXTRAINRANK2_Spare1_OFF                       (26)
+  #define DDRDATA2CH1_CR_TXTRAINRANK2_Spare1_WID                       ( 6)
+  #define DDRDATA2CH1_CR_TXTRAINRANK2_Spare1_MSK                       (0xFC000000)
+  #define DDRDATA2CH1_CR_TXTRAINRANK2_Spare1_MAX                       (0x0000003F)
+
+#define DDRDATA2CH1_CR_TXTRAINRANK3_REG                              (0x0000052C)
+  #define DDRDATA2CH1_CR_TXTRAINRANK3_TxDqDelay_OFF                    ( 0)
+  #define DDRDATA2CH1_CR_TXTRAINRANK3_TxDqDelay_WID                    ( 9)
+  #define DDRDATA2CH1_CR_TXTRAINRANK3_TxDqDelay_MSK                    (0x000001FF)
+  #define DDRDATA2CH1_CR_TXTRAINRANK3_TxDqDelay_MAX                    (0x000001FF)
+  #define DDRDATA2CH1_CR_TXTRAINRANK3_TxDqsDelay_OFF                   ( 9)
+  #define DDRDATA2CH1_CR_TXTRAINRANK3_TxDqsDelay_WID                   ( 9)
+  #define DDRDATA2CH1_CR_TXTRAINRANK3_TxDqsDelay_MSK                   (0x0003FE00)
+  #define DDRDATA2CH1_CR_TXTRAINRANK3_TxDqsDelay_MAX                   (0x000001FF)
+  #define DDRDATA2CH1_CR_TXTRAINRANK3_Spare0_OFF                       (18)
+  #define DDRDATA2CH1_CR_TXTRAINRANK3_Spare0_WID                       ( 2)
+  #define DDRDATA2CH1_CR_TXTRAINRANK3_Spare0_MSK                       (0x000C0000)
+  #define DDRDATA2CH1_CR_TXTRAINRANK3_Spare0_MAX                       (0x00000003)
+  #define DDRDATA2CH1_CR_TXTRAINRANK3_TxEqualization_OFF               (20)
+  #define DDRDATA2CH1_CR_TXTRAINRANK3_TxEqualization_WID               ( 6)
+  #define DDRDATA2CH1_CR_TXTRAINRANK3_TxEqualization_MSK               (0x03F00000)
+  #define DDRDATA2CH1_CR_TXTRAINRANK3_TxEqualization_MAX               (0x0000003F)
+  #define DDRDATA2CH1_CR_TXTRAINRANK3_Spare1_OFF                       (26)
+  #define DDRDATA2CH1_CR_TXTRAINRANK3_Spare1_WID                       ( 6)
+  #define DDRDATA2CH1_CR_TXTRAINRANK3_Spare1_MSK                       (0xFC000000)
+  #define DDRDATA2CH1_CR_TXTRAINRANK3_Spare1_MAX                       (0x0000003F)
+
+#define DDRDATA2CH1_CR_TXPERBITRANK0_REG                             (0x00000530)
+  #define DDRDATA2CH1_CR_TXPERBITRANK0_Lane0_OFF                       ( 0)
+  #define DDRDATA2CH1_CR_TXPERBITRANK0_Lane0_WID                       ( 4)
+  #define DDRDATA2CH1_CR_TXPERBITRANK0_Lane0_MSK                       (0x0000000F)
+  #define DDRDATA2CH1_CR_TXPERBITRANK0_Lane0_MAX                       (0x0000000F)
+  #define DDRDATA2CH1_CR_TXPERBITRANK0_Lane1_OFF                       ( 4)
+  #define DDRDATA2CH1_CR_TXPERBITRANK0_Lane1_WID                       ( 4)
+  #define DDRDATA2CH1_CR_TXPERBITRANK0_Lane1_MSK                       (0x000000F0)
+  #define DDRDATA2CH1_CR_TXPERBITRANK0_Lane1_MAX                       (0x0000000F)
+  #define DDRDATA2CH1_CR_TXPERBITRANK0_Lane2_OFF                       ( 8)
+  #define DDRDATA2CH1_CR_TXPERBITRANK0_Lane2_WID                       ( 4)
+  #define DDRDATA2CH1_CR_TXPERBITRANK0_Lane2_MSK                       (0x00000F00)
+  #define DDRDATA2CH1_CR_TXPERBITRANK0_Lane2_MAX                       (0x0000000F)
+  #define DDRDATA2CH1_CR_TXPERBITRANK0_Lane3_OFF                       (12)
+  #define DDRDATA2CH1_CR_TXPERBITRANK0_Lane3_WID                       ( 4)
+  #define DDRDATA2CH1_CR_TXPERBITRANK0_Lane3_MSK                       (0x0000F000)
+  #define DDRDATA2CH1_CR_TXPERBITRANK0_Lane3_MAX                       (0x0000000F)
+  #define DDRDATA2CH1_CR_TXPERBITRANK0_Lane4_OFF                       (16)
+  #define DDRDATA2CH1_CR_TXPERBITRANK0_Lane4_WID                       ( 4)
+  #define DDRDATA2CH1_CR_TXPERBITRANK0_Lane4_MSK                       (0x000F0000)
+  #define DDRDATA2CH1_CR_TXPERBITRANK0_Lane4_MAX                       (0x0000000F)
+  #define DDRDATA2CH1_CR_TXPERBITRANK0_Lane5_OFF                       (20)
+  #define DDRDATA2CH1_CR_TXPERBITRANK0_Lane5_WID                       ( 4)
+  #define DDRDATA2CH1_CR_TXPERBITRANK0_Lane5_MSK                       (0x00F00000)
+  #define DDRDATA2CH1_CR_TXPERBITRANK0_Lane5_MAX                       (0x0000000F)
+  #define DDRDATA2CH1_CR_TXPERBITRANK0_Lane6_OFF                       (24)
+  #define DDRDATA2CH1_CR_TXPERBITRANK0_Lane6_WID                       ( 4)
+  #define DDRDATA2CH1_CR_TXPERBITRANK0_Lane6_MSK                       (0x0F000000)
+  #define DDRDATA2CH1_CR_TXPERBITRANK0_Lane6_MAX                       (0x0000000F)
+  #define DDRDATA2CH1_CR_TXPERBITRANK0_Lane7_OFF                       (28)
+  #define DDRDATA2CH1_CR_TXPERBITRANK0_Lane7_WID                       ( 4)
+  #define DDRDATA2CH1_CR_TXPERBITRANK0_Lane7_MSK                       (0xF0000000)
+  #define DDRDATA2CH1_CR_TXPERBITRANK0_Lane7_MAX                       (0x0000000F)
+
+#define DDRDATA2CH1_CR_TXPERBITRANK1_REG                             (0x00000534)
+  #define DDRDATA2CH1_CR_TXPERBITRANK1_Lane0_OFF                       ( 0)
+  #define DDRDATA2CH1_CR_TXPERBITRANK1_Lane0_WID                       ( 4)
+  #define DDRDATA2CH1_CR_TXPERBITRANK1_Lane0_MSK                       (0x0000000F)
+  #define DDRDATA2CH1_CR_TXPERBITRANK1_Lane0_MAX                       (0x0000000F)
+  #define DDRDATA2CH1_CR_TXPERBITRANK1_Lane1_OFF                       ( 4)
+  #define DDRDATA2CH1_CR_TXPERBITRANK1_Lane1_WID                       ( 4)
+  #define DDRDATA2CH1_CR_TXPERBITRANK1_Lane1_MSK                       (0x000000F0)
+  #define DDRDATA2CH1_CR_TXPERBITRANK1_Lane1_MAX                       (0x0000000F)
+  #define DDRDATA2CH1_CR_TXPERBITRANK1_Lane2_OFF                       ( 8)
+  #define DDRDATA2CH1_CR_TXPERBITRANK1_Lane2_WID                       ( 4)
+  #define DDRDATA2CH1_CR_TXPERBITRANK1_Lane2_MSK                       (0x00000F00)
+  #define DDRDATA2CH1_CR_TXPERBITRANK1_Lane2_MAX                       (0x0000000F)
+  #define DDRDATA2CH1_CR_TXPERBITRANK1_Lane3_OFF                       (12)
+  #define DDRDATA2CH1_CR_TXPERBITRANK1_Lane3_WID                       ( 4)
+  #define DDRDATA2CH1_CR_TXPERBITRANK1_Lane3_MSK                       (0x0000F000)
+  #define DDRDATA2CH1_CR_TXPERBITRANK1_Lane3_MAX                       (0x0000000F)
+  #define DDRDATA2CH1_CR_TXPERBITRANK1_Lane4_OFF                       (16)
+  #define DDRDATA2CH1_CR_TXPERBITRANK1_Lane4_WID                       ( 4)
+  #define DDRDATA2CH1_CR_TXPERBITRANK1_Lane4_MSK                       (0x000F0000)
+  #define DDRDATA2CH1_CR_TXPERBITRANK1_Lane4_MAX                       (0x0000000F)
+  #define DDRDATA2CH1_CR_TXPERBITRANK1_Lane5_OFF                       (20)
+  #define DDRDATA2CH1_CR_TXPERBITRANK1_Lane5_WID                       ( 4)
+  #define DDRDATA2CH1_CR_TXPERBITRANK1_Lane5_MSK                       (0x00F00000)
+  #define DDRDATA2CH1_CR_TXPERBITRANK1_Lane5_MAX                       (0x0000000F)
+  #define DDRDATA2CH1_CR_TXPERBITRANK1_Lane6_OFF                       (24)
+  #define DDRDATA2CH1_CR_TXPERBITRANK1_Lane6_WID                       ( 4)
+  #define DDRDATA2CH1_CR_TXPERBITRANK1_Lane6_MSK                       (0x0F000000)
+  #define DDRDATA2CH1_CR_TXPERBITRANK1_Lane6_MAX                       (0x0000000F)
+  #define DDRDATA2CH1_CR_TXPERBITRANK1_Lane7_OFF                       (28)
+  #define DDRDATA2CH1_CR_TXPERBITRANK1_Lane7_WID                       ( 4)
+  #define DDRDATA2CH1_CR_TXPERBITRANK1_Lane7_MSK                       (0xF0000000)
+  #define DDRDATA2CH1_CR_TXPERBITRANK1_Lane7_MAX                       (0x0000000F)
+
+#define DDRDATA2CH1_CR_TXPERBITRANK2_REG                             (0x00000538)
+  #define DDRDATA2CH1_CR_TXPERBITRANK2_Lane0_OFF                       ( 0)
+  #define DDRDATA2CH1_CR_TXPERBITRANK2_Lane0_WID                       ( 4)
+  #define DDRDATA2CH1_CR_TXPERBITRANK2_Lane0_MSK                       (0x0000000F)
+  #define DDRDATA2CH1_CR_TXPERBITRANK2_Lane0_MAX                       (0x0000000F)
+  #define DDRDATA2CH1_CR_TXPERBITRANK2_Lane1_OFF                       ( 4)
+  #define DDRDATA2CH1_CR_TXPERBITRANK2_Lane1_WID                       ( 4)
+  #define DDRDATA2CH1_CR_TXPERBITRANK2_Lane1_MSK                       (0x000000F0)
+  #define DDRDATA2CH1_CR_TXPERBITRANK2_Lane1_MAX                       (0x0000000F)
+  #define DDRDATA2CH1_CR_TXPERBITRANK2_Lane2_OFF                       ( 8)
+  #define DDRDATA2CH1_CR_TXPERBITRANK2_Lane2_WID                       ( 4)
+  #define DDRDATA2CH1_CR_TXPERBITRANK2_Lane2_MSK                       (0x00000F00)
+  #define DDRDATA2CH1_CR_TXPERBITRANK2_Lane2_MAX                       (0x0000000F)
+  #define DDRDATA2CH1_CR_TXPERBITRANK2_Lane3_OFF                       (12)
+  #define DDRDATA2CH1_CR_TXPERBITRANK2_Lane3_WID                       ( 4)
+  #define DDRDATA2CH1_CR_TXPERBITRANK2_Lane3_MSK                       (0x0000F000)
+  #define DDRDATA2CH1_CR_TXPERBITRANK2_Lane3_MAX                       (0x0000000F)
+  #define DDRDATA2CH1_CR_TXPERBITRANK2_Lane4_OFF                       (16)
+  #define DDRDATA2CH1_CR_TXPERBITRANK2_Lane4_WID                       ( 4)
+  #define DDRDATA2CH1_CR_TXPERBITRANK2_Lane4_MSK                       (0x000F0000)
+  #define DDRDATA2CH1_CR_TXPERBITRANK2_Lane4_MAX                       (0x0000000F)
+  #define DDRDATA2CH1_CR_TXPERBITRANK2_Lane5_OFF                       (20)
+  #define DDRDATA2CH1_CR_TXPERBITRANK2_Lane5_WID                       ( 4)
+  #define DDRDATA2CH1_CR_TXPERBITRANK2_Lane5_MSK                       (0x00F00000)
+  #define DDRDATA2CH1_CR_TXPERBITRANK2_Lane5_MAX                       (0x0000000F)
+  #define DDRDATA2CH1_CR_TXPERBITRANK2_Lane6_OFF                       (24)
+  #define DDRDATA2CH1_CR_TXPERBITRANK2_Lane6_WID                       ( 4)
+  #define DDRDATA2CH1_CR_TXPERBITRANK2_Lane6_MSK                       (0x0F000000)
+  #define DDRDATA2CH1_CR_TXPERBITRANK2_Lane6_MAX                       (0x0000000F)
+  #define DDRDATA2CH1_CR_TXPERBITRANK2_Lane7_OFF                       (28)
+  #define DDRDATA2CH1_CR_TXPERBITRANK2_Lane7_WID                       ( 4)
+  #define DDRDATA2CH1_CR_TXPERBITRANK2_Lane7_MSK                       (0xF0000000)
+  #define DDRDATA2CH1_CR_TXPERBITRANK2_Lane7_MAX                       (0x0000000F)
+
+#define DDRDATA2CH1_CR_TXPERBITRANK3_REG                             (0x0000053C)
+  #define DDRDATA2CH1_CR_TXPERBITRANK3_Lane0_OFF                       ( 0)
+  #define DDRDATA2CH1_CR_TXPERBITRANK3_Lane0_WID                       ( 4)
+  #define DDRDATA2CH1_CR_TXPERBITRANK3_Lane0_MSK                       (0x0000000F)
+  #define DDRDATA2CH1_CR_TXPERBITRANK3_Lane0_MAX                       (0x0000000F)
+  #define DDRDATA2CH1_CR_TXPERBITRANK3_Lane1_OFF                       ( 4)
+  #define DDRDATA2CH1_CR_TXPERBITRANK3_Lane1_WID                       ( 4)
+  #define DDRDATA2CH1_CR_TXPERBITRANK3_Lane1_MSK                       (0x000000F0)
+  #define DDRDATA2CH1_CR_TXPERBITRANK3_Lane1_MAX                       (0x0000000F)
+  #define DDRDATA2CH1_CR_TXPERBITRANK3_Lane2_OFF                       ( 8)
+  #define DDRDATA2CH1_CR_TXPERBITRANK3_Lane2_WID                       ( 4)
+  #define DDRDATA2CH1_CR_TXPERBITRANK3_Lane2_MSK                       (0x00000F00)
+  #define DDRDATA2CH1_CR_TXPERBITRANK3_Lane2_MAX                       (0x0000000F)
+  #define DDRDATA2CH1_CR_TXPERBITRANK3_Lane3_OFF                       (12)
+  #define DDRDATA2CH1_CR_TXPERBITRANK3_Lane3_WID                       ( 4)
+  #define DDRDATA2CH1_CR_TXPERBITRANK3_Lane3_MSK                       (0x0000F000)
+  #define DDRDATA2CH1_CR_TXPERBITRANK3_Lane3_MAX                       (0x0000000F)
+  #define DDRDATA2CH1_CR_TXPERBITRANK3_Lane4_OFF                       (16)
+  #define DDRDATA2CH1_CR_TXPERBITRANK3_Lane4_WID                       ( 4)
+  #define DDRDATA2CH1_CR_TXPERBITRANK3_Lane4_MSK                       (0x000F0000)
+  #define DDRDATA2CH1_CR_TXPERBITRANK3_Lane4_MAX                       (0x0000000F)
+  #define DDRDATA2CH1_CR_TXPERBITRANK3_Lane5_OFF                       (20)
+  #define DDRDATA2CH1_CR_TXPERBITRANK3_Lane5_WID                       ( 4)
+  #define DDRDATA2CH1_CR_TXPERBITRANK3_Lane5_MSK                       (0x00F00000)
+  #define DDRDATA2CH1_CR_TXPERBITRANK3_Lane5_MAX                       (0x0000000F)
+  #define DDRDATA2CH1_CR_TXPERBITRANK3_Lane6_OFF                       (24)
+  #define DDRDATA2CH1_CR_TXPERBITRANK3_Lane6_WID                       ( 4)
+  #define DDRDATA2CH1_CR_TXPERBITRANK3_Lane6_MSK                       (0x0F000000)
+  #define DDRDATA2CH1_CR_TXPERBITRANK3_Lane6_MAX                       (0x0000000F)
+  #define DDRDATA2CH1_CR_TXPERBITRANK3_Lane7_OFF                       (28)
+  #define DDRDATA2CH1_CR_TXPERBITRANK3_Lane7_WID                       ( 4)
+  #define DDRDATA2CH1_CR_TXPERBITRANK3_Lane7_MSK                       (0xF0000000)
+  #define DDRDATA2CH1_CR_TXPERBITRANK3_Lane7_MAX                       (0x0000000F)
+
+#define DDRDATA2CH1_CR_RCOMPDATA0_REG                                (0x00000540)
+  #define DDRDATA2CH1_CR_RCOMPDATA0_RcompDrvUp_OFF                     ( 0)
+  #define DDRDATA2CH1_CR_RCOMPDATA0_RcompDrvUp_WID                     ( 6)
+  #define DDRDATA2CH1_CR_RCOMPDATA0_RcompDrvUp_MSK                     (0x0000003F)
+  #define DDRDATA2CH1_CR_RCOMPDATA0_RcompDrvUp_MAX                     (0x0000003F)
+  #define DDRDATA2CH1_CR_RCOMPDATA0_Spare0_OFF                         ( 6)
+  #define DDRDATA2CH1_CR_RCOMPDATA0_Spare0_WID                         ( 3)
+  #define DDRDATA2CH1_CR_RCOMPDATA0_Spare0_MSK                         (0x000001C0)
+  #define DDRDATA2CH1_CR_RCOMPDATA0_Spare0_MAX                         (0x00000007)
+  #define DDRDATA2CH1_CR_RCOMPDATA0_RcompDrvDown_OFF                   ( 9)
+  #define DDRDATA2CH1_CR_RCOMPDATA0_RcompDrvDown_WID                   ( 6)
+  #define DDRDATA2CH1_CR_RCOMPDATA0_RcompDrvDown_MSK                   (0x00007E00)
+  #define DDRDATA2CH1_CR_RCOMPDATA0_RcompDrvDown_MAX                   (0x0000003F)
+  #define DDRDATA2CH1_CR_RCOMPDATA0_VTComp_OFF                         (15)
+  #define DDRDATA2CH1_CR_RCOMPDATA0_VTComp_WID                         ( 5)
+  #define DDRDATA2CH1_CR_RCOMPDATA0_VTComp_MSK                         (0x000F8000)
+  #define DDRDATA2CH1_CR_RCOMPDATA0_VTComp_MAX                         (0x0000001F)
+  #define DDRDATA2CH1_CR_RCOMPDATA0_TcoComp_OFF                        (20)
+  #define DDRDATA2CH1_CR_RCOMPDATA0_TcoComp_WID                        ( 6)
+  #define DDRDATA2CH1_CR_RCOMPDATA0_TcoComp_MSK                        (0x03F00000)
+  #define DDRDATA2CH1_CR_RCOMPDATA0_TcoComp_MAX                        (0x0000003F)
+  #define DDRDATA2CH1_CR_RCOMPDATA0_SlewRateComp_OFF                   (26)
+  #define DDRDATA2CH1_CR_RCOMPDATA0_SlewRateComp_WID                   ( 5)
+  #define DDRDATA2CH1_CR_RCOMPDATA0_SlewRateComp_MSK                   (0x7C000000)
+  #define DDRDATA2CH1_CR_RCOMPDATA0_SlewRateComp_MAX                   (0x0000001F)
+  #define DDRDATA2CH1_CR_RCOMPDATA0_Spare2_OFF                         (31)
+  #define DDRDATA2CH1_CR_RCOMPDATA0_Spare2_WID                         ( 1)
+  #define DDRDATA2CH1_CR_RCOMPDATA0_Spare2_MSK                         (0x80000000)
+  #define DDRDATA2CH1_CR_RCOMPDATA0_Spare2_MAX                         (0x00000001)
+
+#define DDRDATA2CH1_CR_RCOMPDATA1_REG                                (0x00000544)
+  #define DDRDATA2CH1_CR_RCOMPDATA1_RcompOdtUp_OFF                     ( 0)
+  #define DDRDATA2CH1_CR_RCOMPDATA1_RcompOdtUp_WID                     ( 6)
+  #define DDRDATA2CH1_CR_RCOMPDATA1_RcompOdtUp_MSK                     (0x0000003F)
+  #define DDRDATA2CH1_CR_RCOMPDATA1_RcompOdtUp_MAX                     (0x0000003F)
+  #define DDRDATA2CH1_CR_RCOMPDATA1_Spare0_OFF                         ( 6)
+  #define DDRDATA2CH1_CR_RCOMPDATA1_Spare0_WID                         ( 3)
+  #define DDRDATA2CH1_CR_RCOMPDATA1_Spare0_MSK                         (0x000001C0)
+  #define DDRDATA2CH1_CR_RCOMPDATA1_Spare0_MAX                         (0x00000007)
+  #define DDRDATA2CH1_CR_RCOMPDATA1_RcompOdtDown_OFF                   ( 9)
+  #define DDRDATA2CH1_CR_RCOMPDATA1_RcompOdtDown_WID                   ( 6)
+  #define DDRDATA2CH1_CR_RCOMPDATA1_RcompOdtDown_MSK                   (0x00007E00)
+  #define DDRDATA2CH1_CR_RCOMPDATA1_RcompOdtDown_MAX                   (0x0000003F)
+  #define DDRDATA2CH1_CR_RCOMPDATA1_Spare1_OFF                         (15)
+  #define DDRDATA2CH1_CR_RCOMPDATA1_Spare1_WID                         ( 1)
+  #define DDRDATA2CH1_CR_RCOMPDATA1_Spare1_MSK                         (0x00008000)
+  #define DDRDATA2CH1_CR_RCOMPDATA1_Spare1_MAX                         (0x00000001)
+  #define DDRDATA2CH1_CR_RCOMPDATA1_PanicDrvDn_OFF                     (16)
+  #define DDRDATA2CH1_CR_RCOMPDATA1_PanicDrvDn_WID                     ( 6)
+  #define DDRDATA2CH1_CR_RCOMPDATA1_PanicDrvDn_MSK                     (0x003F0000)
+  #define DDRDATA2CH1_CR_RCOMPDATA1_PanicDrvDn_MAX                     (0x0000003F)
+  #define DDRDATA2CH1_CR_RCOMPDATA1_PanicDrvUp_OFF                     (22)
+  #define DDRDATA2CH1_CR_RCOMPDATA1_PanicDrvUp_WID                     ( 6)
+  #define DDRDATA2CH1_CR_RCOMPDATA1_PanicDrvUp_MSK                     (0x0FC00000)
+  #define DDRDATA2CH1_CR_RCOMPDATA1_PanicDrvUp_MAX                     (0x0000003F)
+  #define DDRDATA2CH1_CR_RCOMPDATA1_LevelShifterComp_OFF               (28)
+  #define DDRDATA2CH1_CR_RCOMPDATA1_LevelShifterComp_WID               ( 3)
+  #define DDRDATA2CH1_CR_RCOMPDATA1_LevelShifterComp_MSK               (0x70000000)
+  #define DDRDATA2CH1_CR_RCOMPDATA1_LevelShifterComp_MAX               (0x00000007)
+  #define DDRDATA2CH1_CR_RCOMPDATA1_Spare2_OFF                         (31)
+  #define DDRDATA2CH1_CR_RCOMPDATA1_Spare2_WID                         ( 1)
+  #define DDRDATA2CH1_CR_RCOMPDATA1_Spare2_MSK                         (0x80000000)
+  #define DDRDATA2CH1_CR_RCOMPDATA1_Spare2_MAX                         (0x00000001)
+
+#define DDRDATA2CH1_CR_TXXTALK_REG                                   (0x00000548)
+  #define DDRDATA2CH1_CR_TXXTALK_Lane0_OFF                             ( 0)
+  #define DDRDATA2CH1_CR_TXXTALK_Lane0_WID                             ( 4)
+  #define DDRDATA2CH1_CR_TXXTALK_Lane0_MSK                             (0x0000000F)
+  #define DDRDATA2CH1_CR_TXXTALK_Lane0_MAX                             (0x0000000F)
+  #define DDRDATA2CH1_CR_TXXTALK_Lane1_OFF                             ( 4)
+  #define DDRDATA2CH1_CR_TXXTALK_Lane1_WID                             ( 4)
+  #define DDRDATA2CH1_CR_TXXTALK_Lane1_MSK                             (0x000000F0)
+  #define DDRDATA2CH1_CR_TXXTALK_Lane1_MAX                             (0x0000000F)
+  #define DDRDATA2CH1_CR_TXXTALK_Lane2_OFF                             ( 8)
+  #define DDRDATA2CH1_CR_TXXTALK_Lane2_WID                             ( 4)
+  #define DDRDATA2CH1_CR_TXXTALK_Lane2_MSK                             (0x00000F00)
+  #define DDRDATA2CH1_CR_TXXTALK_Lane2_MAX                             (0x0000000F)
+  #define DDRDATA2CH1_CR_TXXTALK_Lane3_OFF                             (12)
+  #define DDRDATA2CH1_CR_TXXTALK_Lane3_WID                             ( 4)
+  #define DDRDATA2CH1_CR_TXXTALK_Lane3_MSK                             (0x0000F000)
+  #define DDRDATA2CH1_CR_TXXTALK_Lane3_MAX                             (0x0000000F)
+  #define DDRDATA2CH1_CR_TXXTALK_Lane4_OFF                             (16)
+  #define DDRDATA2CH1_CR_TXXTALK_Lane4_WID                             ( 4)
+  #define DDRDATA2CH1_CR_TXXTALK_Lane4_MSK                             (0x000F0000)
+  #define DDRDATA2CH1_CR_TXXTALK_Lane4_MAX                             (0x0000000F)
+  #define DDRDATA2CH1_CR_TXXTALK_Lane5_OFF                             (20)
+  #define DDRDATA2CH1_CR_TXXTALK_Lane5_WID                             ( 4)
+  #define DDRDATA2CH1_CR_TXXTALK_Lane5_MSK                             (0x00F00000)
+  #define DDRDATA2CH1_CR_TXXTALK_Lane5_MAX                             (0x0000000F)
+  #define DDRDATA2CH1_CR_TXXTALK_Lane6_OFF                             (24)
+  #define DDRDATA2CH1_CR_TXXTALK_Lane6_WID                             ( 4)
+  #define DDRDATA2CH1_CR_TXXTALK_Lane6_MSK                             (0x0F000000)
+  #define DDRDATA2CH1_CR_TXXTALK_Lane6_MAX                             (0x0000000F)
+  #define DDRDATA2CH1_CR_TXXTALK_Lane7_OFF                             (28)
+  #define DDRDATA2CH1_CR_TXXTALK_Lane7_WID                             ( 4)
+  #define DDRDATA2CH1_CR_TXXTALK_Lane7_MSK                             (0xF0000000)
+  #define DDRDATA2CH1_CR_TXXTALK_Lane7_MAX                             (0x0000000F)
+
+#define DDRDATA2CH1_CR_RXOFFSETVDQ_REG                               (0x0000054C)
+  #define DDRDATA2CH1_CR_RXOFFSETVDQ_Lane0_OFF                         ( 0)
+  #define DDRDATA2CH1_CR_RXOFFSETVDQ_Lane0_WID                         ( 4)
+  #define DDRDATA2CH1_CR_RXOFFSETVDQ_Lane0_MSK                         (0x0000000F)
+  #define DDRDATA2CH1_CR_RXOFFSETVDQ_Lane0_MAX                         (0x0000000F)
+  #define DDRDATA2CH1_CR_RXOFFSETVDQ_Lane1_OFF                         ( 4)
+  #define DDRDATA2CH1_CR_RXOFFSETVDQ_Lane1_WID                         ( 4)
+  #define DDRDATA2CH1_CR_RXOFFSETVDQ_Lane1_MSK                         (0x000000F0)
+  #define DDRDATA2CH1_CR_RXOFFSETVDQ_Lane1_MAX                         (0x0000000F)
+  #define DDRDATA2CH1_CR_RXOFFSETVDQ_Lane2_OFF                         ( 8)
+  #define DDRDATA2CH1_CR_RXOFFSETVDQ_Lane2_WID                         ( 4)
+  #define DDRDATA2CH1_CR_RXOFFSETVDQ_Lane2_MSK                         (0x00000F00)
+  #define DDRDATA2CH1_CR_RXOFFSETVDQ_Lane2_MAX                         (0x0000000F)
+  #define DDRDATA2CH1_CR_RXOFFSETVDQ_Lane3_OFF                         (12)
+  #define DDRDATA2CH1_CR_RXOFFSETVDQ_Lane3_WID                         ( 4)
+  #define DDRDATA2CH1_CR_RXOFFSETVDQ_Lane3_MSK                         (0x0000F000)
+  #define DDRDATA2CH1_CR_RXOFFSETVDQ_Lane3_MAX                         (0x0000000F)
+  #define DDRDATA2CH1_CR_RXOFFSETVDQ_Lane4_OFF                         (16)
+  #define DDRDATA2CH1_CR_RXOFFSETVDQ_Lane4_WID                         ( 4)
+  #define DDRDATA2CH1_CR_RXOFFSETVDQ_Lane4_MSK                         (0x000F0000)
+  #define DDRDATA2CH1_CR_RXOFFSETVDQ_Lane4_MAX                         (0x0000000F)
+  #define DDRDATA2CH1_CR_RXOFFSETVDQ_Lane5_OFF                         (20)
+  #define DDRDATA2CH1_CR_RXOFFSETVDQ_Lane5_WID                         ( 4)
+  #define DDRDATA2CH1_CR_RXOFFSETVDQ_Lane5_MSK                         (0x00F00000)
+  #define DDRDATA2CH1_CR_RXOFFSETVDQ_Lane5_MAX                         (0x0000000F)
+  #define DDRDATA2CH1_CR_RXOFFSETVDQ_Lane6_OFF                         (24)
+  #define DDRDATA2CH1_CR_RXOFFSETVDQ_Lane6_WID                         ( 4)
+  #define DDRDATA2CH1_CR_RXOFFSETVDQ_Lane6_MSK                         (0x0F000000)
+  #define DDRDATA2CH1_CR_RXOFFSETVDQ_Lane6_MAX                         (0x0000000F)
+  #define DDRDATA2CH1_CR_RXOFFSETVDQ_Lane7_OFF                         (28)
+  #define DDRDATA2CH1_CR_RXOFFSETVDQ_Lane7_WID                         ( 4)
+  #define DDRDATA2CH1_CR_RXOFFSETVDQ_Lane7_MSK                         (0xF0000000)
+  #define DDRDATA2CH1_CR_RXOFFSETVDQ_Lane7_MAX                         (0x0000000F)
+
+#define DDRDATA2CH1_CR_DDRDATARESERVED_REG                           (0x00000550)
+  #define DDRDATA2CH1_CR_DDRDATARESERVED_Spare_OFF                     ( 0)
+  #define DDRDATA2CH1_CR_DDRDATARESERVED_Spare_WID                     (32)
+  #define DDRDATA2CH1_CR_DDRDATARESERVED_Spare_MSK                     (0xFFFFFFFF)
+  #define DDRDATA2CH1_CR_DDRDATARESERVED_Spare_MAX                     (0xFFFFFFFF)
+
+#define DDRDATA2CH1_CR_DATATRAINFEEDBACK_REG                         (0x00000554)
+  #define DDRDATA2CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_OFF       ( 0)
+  #define DDRDATA2CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_WID       ( 9)
+  #define DDRDATA2CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_MSK       (0x000001FF)
+  #define DDRDATA2CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_MAX       (0x000001FF)
+  #define DDRDATA2CH1_CR_DATATRAINFEEDBACK_Spare_OFF                   ( 9)
+  #define DDRDATA2CH1_CR_DATATRAINFEEDBACK_Spare_WID                   (23)
+  #define DDRDATA2CH1_CR_DATATRAINFEEDBACK_Spare_MSK                   (0xFFFFFE00)
+  #define DDRDATA2CH1_CR_DATATRAINFEEDBACK_Spare_MAX                   (0x007FFFFF)
+
+#define DDRDATA2CH1_CR_DLLPITESTANDADC_REG                           (0x00000558)
+  #define DDRDATA2CH1_CR_DLLPITESTANDADC_RunTest_OFF                   ( 0)
+  #define DDRDATA2CH1_CR_DLLPITESTANDADC_RunTest_WID                   ( 1)
+  #define DDRDATA2CH1_CR_DLLPITESTANDADC_RunTest_MSK                   (0x00000001)
+  #define DDRDATA2CH1_CR_DLLPITESTANDADC_RunTest_MAX                   (0x00000001)
+  #define DDRDATA2CH1_CR_DLLPITESTANDADC_RunTest_DEF                   (0x00000000)
+  #define DDRDATA2CH1_CR_DLLPITESTANDADC_Load_OFF                      ( 1)
+  #define DDRDATA2CH1_CR_DLLPITESTANDADC_Load_WID                      ( 1)
+  #define DDRDATA2CH1_CR_DLLPITESTANDADC_Load_MSK                      (0x00000002)
+  #define DDRDATA2CH1_CR_DLLPITESTANDADC_Load_MAX                      (0x00000001)
+  #define DDRDATA2CH1_CR_DLLPITESTANDADC_Load_DEF                      (0x00000000)
+  #define DDRDATA2CH1_CR_DLLPITESTANDADC_ModeHVM_OFF                   ( 2)
+  #define DDRDATA2CH1_CR_DLLPITESTANDADC_ModeHVM_WID                   ( 1)
+  #define DDRDATA2CH1_CR_DLLPITESTANDADC_ModeHVM_MSK                   (0x00000004)
+  #define DDRDATA2CH1_CR_DLLPITESTANDADC_ModeHVM_MAX                   (0x00000001)
+  #define DDRDATA2CH1_CR_DLLPITESTANDADC_ModeHVM_DEF                   (0x00000000)
+  #define DDRDATA2CH1_CR_DLLPITESTANDADC_ModeDV_OFF                    ( 3)
+  #define DDRDATA2CH1_CR_DLLPITESTANDADC_ModeDV_WID                    ( 1)
+  #define DDRDATA2CH1_CR_DLLPITESTANDADC_ModeDV_MSK                    (0x00000008)
+  #define DDRDATA2CH1_CR_DLLPITESTANDADC_ModeDV_MAX                    (0x00000001)
+  #define DDRDATA2CH1_CR_DLLPITESTANDADC_ModeDV_DEF                    (0x00000000)
+  #define DDRDATA2CH1_CR_DLLPITESTANDADC_ModeADC_OFF                   ( 4)
+  #define DDRDATA2CH1_CR_DLLPITESTANDADC_ModeADC_WID                   ( 1)
+  #define DDRDATA2CH1_CR_DLLPITESTANDADC_ModeADC_MSK                   (0x00000010)
+  #define DDRDATA2CH1_CR_DLLPITESTANDADC_ModeADC_MAX                   (0x00000001)
+  #define DDRDATA2CH1_CR_DLLPITESTANDADC_ModeADC_DEF                   (0x00000000)
+  #define DDRDATA2CH1_CR_DLLPITESTANDADC_LoadCount_OFF                 ( 5)
+  #define DDRDATA2CH1_CR_DLLPITESTANDADC_LoadCount_WID                 (10)
+  #define DDRDATA2CH1_CR_DLLPITESTANDADC_LoadCount_MSK                 (0x00007FE0)
+  #define DDRDATA2CH1_CR_DLLPITESTANDADC_LoadCount_MAX                 (0x000003FF)
+  #define DDRDATA2CH1_CR_DLLPITESTANDADC_CountStatus_OFF               (15)
+  #define DDRDATA2CH1_CR_DLLPITESTANDADC_CountStatus_WID               (10)
+  #define DDRDATA2CH1_CR_DLLPITESTANDADC_CountStatus_MSK               (0x01FF8000)
+  #define DDRDATA2CH1_CR_DLLPITESTANDADC_CountStatus_MAX               (0x000003FF)
+  #define DDRDATA2CH1_CR_DLLPITESTANDADC_CountStatus_DEF               (0x00000000)
+  #define DDRDATA2CH1_CR_DLLPITESTANDADC_Spare_OFF                     (25)
+  #define DDRDATA2CH1_CR_DLLPITESTANDADC_Spare_WID                     ( 7)
+  #define DDRDATA2CH1_CR_DLLPITESTANDADC_Spare_MSK                     (0xFE000000)
+  #define DDRDATA2CH1_CR_DLLPITESTANDADC_Spare_MAX                     (0x0000007F)
+
+#define DDRDATA2CH1_CR_DDRCRDATAOFFSETCOMP_REG                       (0x0000055C)
+  #define DDRDATA2CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_OFF     ( 0)
+  #define DDRDATA2CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_WID     ( 6)
+  #define DDRDATA2CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MSK     (0x0000003F)
+  #define DDRDATA2CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MAX     (0x0000003F)
+  #define DDRDATA2CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_DEF     (0x00000000)
+  #define DDRDATA2CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_OFF   ( 6)
+  #define DDRDATA2CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_WID   ( 6)
+  #define DDRDATA2CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MSK   (0x00000FC0)
+  #define DDRDATA2CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MAX   (0x0000003F)
+  #define DDRDATA2CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_DEF   (0x00000000)
+  #define DDRDATA2CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_OFF     (12)
+  #define DDRDATA2CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_WID     ( 5)
+  #define DDRDATA2CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MSK     (0x0001F000)
+  #define DDRDATA2CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MAX     (0x0000001F)
+  #define DDRDATA2CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_DEF     (0x00000000)
+  #define DDRDATA2CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_OFF   (17)
+  #define DDRDATA2CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_WID   ( 5)
+  #define DDRDATA2CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MSK   (0x003E0000)
+  #define DDRDATA2CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MAX   (0x0000001F)
+  #define DDRDATA2CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_DEF   (0x00000000)
+  #define DDRDATA2CH1_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_OFF       (22)
+  #define DDRDATA2CH1_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_WID       ( 5)
+  #define DDRDATA2CH1_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_MSK       (0x07C00000)
+  #define DDRDATA2CH1_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_MAX       (0x0000001F)
+  #define DDRDATA2CH1_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_DEF       (0x00000000)
+  #define DDRDATA2CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_OFF  (27)
+  #define DDRDATA2CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_WID  ( 5)
+  #define DDRDATA2CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MSK  (0xF8000000)
+  #define DDRDATA2CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MAX  (0x0000001F)
+  #define DDRDATA2CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_DEF  (0x00000000)
+
+#define DDRDATA2CH1_CR_DDRCRDATACONTROL1_REG                         (0x00000560)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_RefPi_OFF                   ( 0)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_RefPi_WID                   ( 4)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_RefPi_MSK                   (0x0000000F)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_RefPi_MAX                   (0x0000000F)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_RefPi_DEF                   (0x00000000)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_DllMask_OFF                 ( 4)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_DllMask_WID                 ( 2)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_DllMask_MSK                 (0x00000030)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_DllMask_MAX                 (0x00000003)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_DllMask_DEF                 (0x00000000)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_DllWeakLock_OFF             ( 6)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_DllWeakLock_WID             ( 1)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_DllWeakLock_MSK             (0x00000040)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_DllWeakLock_MAX             (0x00000001)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_DllWeakLock_DEF             (0x00000000)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_OFF      ( 7)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_WID      ( 3)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MSK      (0x00000380)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MAX      (0x00000007)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_DEF      (0x00000000)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_OFF               (10)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_WID               ( 3)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_MSK               (0x00001C00)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_MAX               (0x00000007)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_DEF               (0x00000000)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_OdtDelay_OFF                (13)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_OdtDelay_WID                ( 4)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_OdtDelay_MSK                (0x0001E000)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_OdtDelay_MAX                (0x0000000F)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_OdtDelay_DEF                (0x00000000)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_OdtDuration_OFF             (17)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_OdtDuration_WID             ( 3)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_OdtDuration_MSK             (0x000E0000)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_OdtDuration_MAX             (0x00000007)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_OdtDuration_DEF             (0x00000000)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_OFF           (20)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_WID           ( 4)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_MSK           (0x00F00000)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_MAX           (0x0000000F)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_DEF           (0x00000000)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_OFF        (24)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_WID        ( 3)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_MSK        (0x07000000)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_MAX        (0x00000007)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_DEF        (0x00000000)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_BurstEndODTDelay_OFF        (27)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_BurstEndODTDelay_WID        ( 3)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_BurstEndODTDelay_MSK        (0x38000000)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_BurstEndODTDelay_MAX        (0x00000007)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_BurstEndODTDelay_DEF        (0x00000000)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_OFF          (30)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_WID          ( 1)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_MSK          (0x40000000)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_MAX          (0x00000001)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_DEF          (0x00000000)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_Rsvd1_OFF                   (31)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_Rsvd1_WID                   ( 1)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_Rsvd1_MSK                   (0x80000000)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_Rsvd1_MAX                   (0x00000001)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_Rsvd1_DEF                   (0x00000000)
+
+#define DDRDATA2CH1_CR_DDRCRDATACONTROL2_REG                         (0x00000564)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_OFF            ( 0)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_WID            ( 5)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_MSK            (0x0000001F)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_MAX            (0x0000001F)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_DEF            (0x00000000)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_OFF             ( 5)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_WID             ( 1)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_MSK             (0x00000020)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_MAX             (0x00000001)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_DEF             (0x00000000)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_ForceRxOn_OFF               ( 6)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_ForceRxOn_WID               ( 1)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_ForceRxOn_MSK               (0x00000040)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_ForceRxOn_MAX               (0x00000001)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_ForceRxOn_DEF               (0x00000000)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_LeakerComp_OFF              ( 7)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_LeakerComp_WID              ( 2)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_LeakerComp_MSK              (0x00000180)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_LeakerComp_MAX              (0x00000003)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_LeakerComp_DEF              (0x00000000)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_OFF          ( 9)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_WID          ( 4)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_MSK          (0x00001E00)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_MAX          (0x0000000F)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_DEF          (0x00000008)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_OFF             (13)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_WID             ( 5)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_MSK             (0x0003E000)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_MAX             (0x0000001F)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_DEF             (0x00000011)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_OFF             (18)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_WID             ( 1)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_MSK             (0x00040000)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_MAX             (0x00000001)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_DEF             (0x00000000)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_Spare_OFF                   (19)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_Spare_WID                   (13)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_Spare_MSK                   (0xFFF80000)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_Spare_MAX                   (0x00001FFF)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_Spare_DEF                   (0x00000000)
+
+#define DDRDATA2CH1_CR_DDRCRVSSHIORVREFCONTROL_REG                   (0x0000056C)
+  #define DDRDATA2CH1_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_OFF    ( 0)
+  #define DDRDATA2CH1_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_WID    (24)
+  #define DDRDATA2CH1_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_MSK    (0x00FFFFFF)
+  #define DDRDATA2CH1_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_MAX    (0x00FFFFFF)
+  #define DDRDATA2CH1_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_DEF    (0x00000000)
+  #define DDRDATA2CH1_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_OFF        (24)
+  #define DDRDATA2CH1_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_WID        ( 8)
+  #define DDRDATA2CH1_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_MSK        (0xFF000000)
+  #define DDRDATA2CH1_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_MAX        (0x000000FF)
+  #define DDRDATA2CH1_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_DEF        (0x00000000)
+
+#define DDRDATA2CH1_CR_DDRCRDATAOFFSETTRAIN_REG                      (0x00000570)
+  #define DDRDATA2CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_OFF          ( 0)
+  #define DDRDATA2CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_WID          ( 6)
+  #define DDRDATA2CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MSK          (0x0000003F)
+  #define DDRDATA2CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MAX          (0x0000003F)
+  #define DDRDATA2CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_DEF          (0x00000000)
+  #define DDRDATA2CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_OFF          ( 6)
+  #define DDRDATA2CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_WID          ( 6)
+  #define DDRDATA2CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MSK          (0x00000FC0)
+  #define DDRDATA2CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MAX          (0x0000003F)
+  #define DDRDATA2CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_DEF          (0x00000000)
+  #define DDRDATA2CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_OFF           (12)
+  #define DDRDATA2CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_WID           ( 6)
+  #define DDRDATA2CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MSK           (0x0003F000)
+  #define DDRDATA2CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MAX           (0x0000003F)
+  #define DDRDATA2CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_DEF           (0x00000000)
+  #define DDRDATA2CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_OFF          (18)
+  #define DDRDATA2CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_WID          ( 6)
+  #define DDRDATA2CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MSK          (0x00FC0000)
+  #define DDRDATA2CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MAX          (0x0000003F)
+  #define DDRDATA2CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_DEF          (0x00000000)
+  #define DDRDATA2CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_OFF           (24)
+  #define DDRDATA2CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_WID           ( 7)
+  #define DDRDATA2CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MSK           (0x7F000000)
+  #define DDRDATA2CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MAX           (0x0000007F)
+  #define DDRDATA2CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_DEF           (0x00000000)
+  #define DDRDATA2CH1_CR_DDRCRDATAOFFSETTRAIN_Spare_OFF                (31)
+  #define DDRDATA2CH1_CR_DDRCRDATAOFFSETTRAIN_Spare_WID                ( 1)
+  #define DDRDATA2CH1_CR_DDRCRDATAOFFSETTRAIN_Spare_MSK                (0x80000000)
+  #define DDRDATA2CH1_CR_DDRCRDATAOFFSETTRAIN_Spare_MAX                (0x00000001)
+  #define DDRDATA2CH1_CR_DDRCRDATAOFFSETTRAIN_Spare_DEF                (0x00000000)
+
+#define DDRDATA2CH1_CR_DDRCRDATACONTROL0_REG                         (0x00000574)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_OFF          ( 0)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_WID          ( 1)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_MSK          (0x00000001)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_MAX          (0x00000001)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_DEF          (0x00000000)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_OFF          ( 1)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_WID          ( 1)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_MSK          (0x00000002)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_MAX          (0x00000001)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_DEF          (0x00000000)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_OFF          ( 2)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_WID          ( 1)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_MSK          (0x00000004)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_MAX          (0x00000001)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_DEF          (0x00000000)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_OFF    ( 3)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_WID    ( 1)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MSK    (0x00000008)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MAX    (0x00000001)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_DEF    (0x00000000)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_TxOn_OFF                    ( 4)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_TxOn_WID                    ( 1)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_TxOn_MSK                    (0x00000010)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_TxOn_MAX                    (0x00000001)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_TxOn_DEF                    (0x00000000)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RfOn_OFF                    ( 5)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RfOn_WID                    ( 1)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RfOn_MSK                    (0x00000020)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RfOn_MAX                    (0x00000001)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RfOn_DEF                    (0x00000000)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RxPiOn_OFF                  ( 6)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RxPiOn_WID                  ( 1)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RxPiOn_MSK                  (0x00000040)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RxPiOn_MAX                  (0x00000001)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RxPiOn_DEF                  (0x00000000)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_TxPiOn_OFF                  ( 7)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_TxPiOn_WID                  ( 1)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_TxPiOn_MSK                  (0x00000080)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_TxPiOn_MAX                  (0x00000001)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_TxPiOn_DEF                  (0x00000000)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_OFF        ( 8)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_WID        ( 1)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_MSK        (0x00000100)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_MAX        (0x00000001)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_DEF        (0x00000000)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_OFF        ( 9)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_WID        ( 1)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MSK        (0x00000200)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MAX        (0x00000001)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_DEF        (0x00000000)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_TxDisable_OFF               (10)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_TxDisable_WID               ( 1)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_TxDisable_MSK               (0x00000400)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_TxDisable_MAX               (0x00000001)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_TxDisable_DEF               (0x00000000)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RxDisable_OFF               (11)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RxDisable_WID               ( 1)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RxDisable_MSK               (0x00000800)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RxDisable_MAX               (0x00000001)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RxDisable_DEF               (0x00000000)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_TxLong_OFF                  (12)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_TxLong_WID                  ( 1)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_TxLong_MSK                  (0x00001000)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_TxLong_MAX                  (0x00000001)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_TxLong_DEF                  (0x00000000)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_OFF               (13)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_WID               ( 2)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_MSK               (0x00006000)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_MAX               (0x00000003)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_DEF               (0x00000000)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RxReadPointer_OFF           (15)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RxReadPointer_WID           ( 3)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RxReadPointer_MSK           (0x00038000)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RxReadPointer_MAX           (0x00000007)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RxReadPointer_DEF           (0x00000000)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_DriverSegmentEnable_OFF     (18)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_DriverSegmentEnable_WID     ( 1)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_DriverSegmentEnable_MSK     (0x00040000)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_DriverSegmentEnable_MAX     (0x00000001)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_DriverSegmentEnable_DEF     (0x00000000)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_DataVccddqHi_OFF            (19)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_DataVccddqHi_WID            ( 1)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_DataVccddqHi_MSK            (0x00080000)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_DataVccddqHi_MAX            (0x00000001)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_DataVccddqHi_DEF            (0x00000000)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_ReadRFRd_OFF                (20)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_ReadRFRd_WID                ( 1)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_ReadRFRd_MSK                (0x00100000)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_ReadRFRd_MAX                (0x00000001)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_ReadRFRd_DEF                (0x00000000)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_ReadRFWr_OFF                (21)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_ReadRFWr_WID                ( 1)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_ReadRFWr_MSK                (0x00200000)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_ReadRFWr_MAX                (0x00000001)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_ReadRFWr_DEF                (0x00000000)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_ReadRFRank_OFF              (22)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_ReadRFRank_WID              ( 2)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_ReadRFRank_MSK              (0x00C00000)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_ReadRFRank_MAX              (0x00000003)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_ReadRFRank_DEF              (0x00000000)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_OFF              (24)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_WID              ( 1)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_MSK              (0x01000000)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_MAX              (0x00000001)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_DEF              (0x00000000)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_OdtSampOff_OFF              (25)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_OdtSampOff_WID              ( 1)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_OdtSampOff_MSK              (0x02000000)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_OdtSampOff_MAX              (0x00000001)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_OdtSampOff_DEF              (0x00000000)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_OFF        (26)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_WID        ( 1)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_MSK        (0x04000000)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_MAX        (0x00000001)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_DEF        (0x00000000)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_OFF         (27)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_WID         ( 1)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MSK         (0x08000000)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MAX         (0x00000001)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_DEF         (0x00000000)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_OFF              (28)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_WID              ( 1)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_MSK              (0x10000000)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_MAX              (0x00000001)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_DEF              (0x00000000)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_EnReadPreamble_OFF          (29)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_EnReadPreamble_WID          ( 1)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_EnReadPreamble_MSK          (0x20000000)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_EnReadPreamble_MAX          (0x00000001)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_EnReadPreamble_DEF          (0x00000000)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_OFF         (30)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_WID         ( 1)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MSK         (0x40000000)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MAX         (0x00000001)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_DEF         (0x00000000)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_OFF            (31)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_WID            ( 1)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_MSK            (0x80000000)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_MAX            (0x00000001)
+  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_DEF            (0x00000000)
+
+#define DDRDATA2CH1_CR_DDRCRVREFADJUST1_REG                          (0x00000578)
+  #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_CAVrefCtl_OFF                ( 0)
+  #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_CAVrefCtl_WID                ( 7)
+  #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_CAVrefCtl_MSK                (0x0000007F)
+  #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_CAVrefCtl_MAX                (0x0000007F)
+  #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_CAVrefCtl_DEF                (0x00000000)
+  #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_Ch1VrefCtl_OFF               ( 7)
+  #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_Ch1VrefCtl_WID               ( 7)
+  #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_Ch1VrefCtl_MSK               (0x00003F80)
+  #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_Ch1VrefCtl_MAX               (0x0000007F)
+  #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_Ch1VrefCtl_DEF               (0x00000000)
+  #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_Ch0VrefCtl_OFF               (14)
+  #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_Ch0VrefCtl_WID               ( 7)
+  #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_Ch0VrefCtl_MSK               (0x001FC000)
+  #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_Ch0VrefCtl_MAX               (0x0000007F)
+  #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_Ch0VrefCtl_DEF               (0x00000000)
+  #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCA_OFF             (21)
+  #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCA_WID             ( 1)
+  #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCA_MSK             (0x00200000)
+  #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCA_MAX             (0x00000001)
+  #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCA_DEF             (0x00000000)
+  #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_OFF            (22)
+  #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_WID            ( 1)
+  #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_MSK            (0x00400000)
+  #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_MAX            (0x00000001)
+  #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_DEF            (0x00000000)
+  #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_OFF            (23)
+  #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_WID            ( 1)
+  #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_MSK            (0x00800000)
+  #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_MAX            (0x00000001)
+  #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_DEF            (0x00000000)
+  #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_HiZTimerCtrl_OFF             (24)
+  #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_HiZTimerCtrl_WID             ( 2)
+  #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_HiZTimerCtrl_MSK             (0x03000000)
+  #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_HiZTimerCtrl_MAX             (0x00000003)
+  #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_HiZTimerCtrl_DEF             (0x00000000)
+  #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_OFF            (26)
+  #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_WID            ( 1)
+  #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_MSK            (0x04000000)
+  #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_MAX            (0x00000001)
+  #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_DEF            (0x00000000)
+  #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_Rsvd_OFF                     (27)
+  #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_Rsvd_WID                     ( 2)
+  #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_Rsvd_MSK                     (0x18000000)
+  #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_Rsvd_MAX                     (0x00000003)
+  #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_Rsvd_DEF                     (0x00000000)
+  #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_caSlowBW_OFF                 (29)
+  #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_caSlowBW_WID                 ( 1)
+  #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_caSlowBW_MSK                 (0x20000000)
+  #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_caSlowBW_MAX                 (0x00000001)
+  #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_caSlowBW_DEF                 (0x00000000)
+  #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_ch0SlowBW_OFF                (30)
+  #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_ch0SlowBW_WID                ( 1)
+  #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_ch0SlowBW_MSK                (0x40000000)
+  #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_ch0SlowBW_MAX                (0x00000001)
+  #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_ch0SlowBW_DEF                (0x00000000)
+  #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_ch1SlowBW_OFF                (31)
+  #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_ch1SlowBW_WID                ( 1)
+  #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_ch1SlowBW_MSK                (0x80000000)
+  #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_ch1SlowBW_MAX                (0x00000001)
+  #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_ch1SlowBW_DEF                (0x00000000)
+
+#define DDRDATA3CH0_CR_RXTRAINRANK0_REG                              (0x00000600)
+  #define DDRDATA3CH0_CR_RXTRAINRANK0_RxRcvEnPi_OFF                    ( 0)
+  #define DDRDATA3CH0_CR_RXTRAINRANK0_RxRcvEnPi_WID                    ( 9)
+  #define DDRDATA3CH0_CR_RXTRAINRANK0_RxRcvEnPi_MSK                    (0x000001FF)
+  #define DDRDATA3CH0_CR_RXTRAINRANK0_RxRcvEnPi_MAX                    (0x000001FF)
+  #define DDRDATA3CH0_CR_RXTRAINRANK0_RxDqsPPi_OFF                     ( 9)
+  #define DDRDATA3CH0_CR_RXTRAINRANK0_RxDqsPPi_WID                     ( 6)
+  #define DDRDATA3CH0_CR_RXTRAINRANK0_RxDqsPPi_MSK                     (0x00007E00)
+  #define DDRDATA3CH0_CR_RXTRAINRANK0_RxDqsPPi_MAX                     (0x0000003F)
+  #define DDRDATA3CH0_CR_RXTRAINRANK0_RxEq_OFF                         (15)
+  #define DDRDATA3CH0_CR_RXTRAINRANK0_RxEq_WID                         ( 5)
+  #define DDRDATA3CH0_CR_RXTRAINRANK0_RxEq_MSK                         (0x000F8000)
+  #define DDRDATA3CH0_CR_RXTRAINRANK0_RxEq_MAX                         (0x0000001F)
+  #define DDRDATA3CH0_CR_RXTRAINRANK0_RxDqsNPi_OFF                     (20)
+  #define DDRDATA3CH0_CR_RXTRAINRANK0_RxDqsNPi_WID                     ( 6)
+  #define DDRDATA3CH0_CR_RXTRAINRANK0_RxDqsNPi_MSK                     (0x03F00000)
+  #define DDRDATA3CH0_CR_RXTRAINRANK0_RxDqsNPi_MAX                     (0x0000003F)
+  #define DDRDATA3CH0_CR_RXTRAINRANK0_RxVref_OFF                       (26)
+  #define DDRDATA3CH0_CR_RXTRAINRANK0_RxVref_WID                       ( 6)
+  #define DDRDATA3CH0_CR_RXTRAINRANK0_RxVref_MSK                       (0xFC000000)
+  #define DDRDATA3CH0_CR_RXTRAINRANK0_RxVref_MAX                       (0x0000003F)
+
+#define DDRDATA3CH0_CR_RXTRAINRANK1_REG                              (0x00000604)
+  #define DDRDATA3CH0_CR_RXTRAINRANK1_RxRcvEnPi_OFF                    ( 0)
+  #define DDRDATA3CH0_CR_RXTRAINRANK1_RxRcvEnPi_WID                    ( 9)
+  #define DDRDATA3CH0_CR_RXTRAINRANK1_RxRcvEnPi_MSK                    (0x000001FF)
+  #define DDRDATA3CH0_CR_RXTRAINRANK1_RxRcvEnPi_MAX                    (0x000001FF)
+  #define DDRDATA3CH0_CR_RXTRAINRANK1_RxDqsPPi_OFF                     ( 9)
+  #define DDRDATA3CH0_CR_RXTRAINRANK1_RxDqsPPi_WID                     ( 6)
+  #define DDRDATA3CH0_CR_RXTRAINRANK1_RxDqsPPi_MSK                     (0x00007E00)
+  #define DDRDATA3CH0_CR_RXTRAINRANK1_RxDqsPPi_MAX                     (0x0000003F)
+  #define DDRDATA3CH0_CR_RXTRAINRANK1_RxEq_OFF                         (15)
+  #define DDRDATA3CH0_CR_RXTRAINRANK1_RxEq_WID                         ( 5)
+  #define DDRDATA3CH0_CR_RXTRAINRANK1_RxEq_MSK                         (0x000F8000)
+  #define DDRDATA3CH0_CR_RXTRAINRANK1_RxEq_MAX                         (0x0000001F)
+  #define DDRDATA3CH0_CR_RXTRAINRANK1_RxDqsNPi_OFF                     (20)
+  #define DDRDATA3CH0_CR_RXTRAINRANK1_RxDqsNPi_WID                     ( 6)
+  #define DDRDATA3CH0_CR_RXTRAINRANK1_RxDqsNPi_MSK                     (0x03F00000)
+  #define DDRDATA3CH0_CR_RXTRAINRANK1_RxDqsNPi_MAX                     (0x0000003F)
+  #define DDRDATA3CH0_CR_RXTRAINRANK1_RxVref_OFF                       (26)
+  #define DDRDATA3CH0_CR_RXTRAINRANK1_RxVref_WID                       ( 6)
+  #define DDRDATA3CH0_CR_RXTRAINRANK1_RxVref_MSK                       (0xFC000000)
+  #define DDRDATA3CH0_CR_RXTRAINRANK1_RxVref_MAX                       (0x0000003F)
+
+#define DDRDATA3CH0_CR_RXTRAINRANK2_REG                              (0x00000608)
+  #define DDRDATA3CH0_CR_RXTRAINRANK2_RxRcvEnPi_OFF                    ( 0)
+  #define DDRDATA3CH0_CR_RXTRAINRANK2_RxRcvEnPi_WID                    ( 9)
+  #define DDRDATA3CH0_CR_RXTRAINRANK2_RxRcvEnPi_MSK                    (0x000001FF)
+  #define DDRDATA3CH0_CR_RXTRAINRANK2_RxRcvEnPi_MAX                    (0x000001FF)
+  #define DDRDATA3CH0_CR_RXTRAINRANK2_RxDqsPPi_OFF                     ( 9)
+  #define DDRDATA3CH0_CR_RXTRAINRANK2_RxDqsPPi_WID                     ( 6)
+  #define DDRDATA3CH0_CR_RXTRAINRANK2_RxDqsPPi_MSK                     (0x00007E00)
+  #define DDRDATA3CH0_CR_RXTRAINRANK2_RxDqsPPi_MAX                     (0x0000003F)
+  #define DDRDATA3CH0_CR_RXTRAINRANK2_RxEq_OFF                         (15)
+  #define DDRDATA3CH0_CR_RXTRAINRANK2_RxEq_WID                         ( 5)
+  #define DDRDATA3CH0_CR_RXTRAINRANK2_RxEq_MSK                         (0x000F8000)
+  #define DDRDATA3CH0_CR_RXTRAINRANK2_RxEq_MAX                         (0x0000001F)
+  #define DDRDATA3CH0_CR_RXTRAINRANK2_RxDqsNPi_OFF                     (20)
+  #define DDRDATA3CH0_CR_RXTRAINRANK2_RxDqsNPi_WID                     ( 6)
+  #define DDRDATA3CH0_CR_RXTRAINRANK2_RxDqsNPi_MSK                     (0x03F00000)
+  #define DDRDATA3CH0_CR_RXTRAINRANK2_RxDqsNPi_MAX                     (0x0000003F)
+  #define DDRDATA3CH0_CR_RXTRAINRANK2_RxVref_OFF                       (26)
+  #define DDRDATA3CH0_CR_RXTRAINRANK2_RxVref_WID                       ( 6)
+  #define DDRDATA3CH0_CR_RXTRAINRANK2_RxVref_MSK                       (0xFC000000)
+  #define DDRDATA3CH0_CR_RXTRAINRANK2_RxVref_MAX                       (0x0000003F)
+
+#define DDRDATA3CH0_CR_RXTRAINRANK3_REG                              (0x0000060C)
+  #define DDRDATA3CH0_CR_RXTRAINRANK3_RxRcvEnPi_OFF                    ( 0)
+  #define DDRDATA3CH0_CR_RXTRAINRANK3_RxRcvEnPi_WID                    ( 9)
+  #define DDRDATA3CH0_CR_RXTRAINRANK3_RxRcvEnPi_MSK                    (0x000001FF)
+  #define DDRDATA3CH0_CR_RXTRAINRANK3_RxRcvEnPi_MAX                    (0x000001FF)
+  #define DDRDATA3CH0_CR_RXTRAINRANK3_RxDqsPPi_OFF                     ( 9)
+  #define DDRDATA3CH0_CR_RXTRAINRANK3_RxDqsPPi_WID                     ( 6)
+  #define DDRDATA3CH0_CR_RXTRAINRANK3_RxDqsPPi_MSK                     (0x00007E00)
+  #define DDRDATA3CH0_CR_RXTRAINRANK3_RxDqsPPi_MAX                     (0x0000003F)
+  #define DDRDATA3CH0_CR_RXTRAINRANK3_RxEq_OFF                         (15)
+  #define DDRDATA3CH0_CR_RXTRAINRANK3_RxEq_WID                         ( 5)
+  #define DDRDATA3CH0_CR_RXTRAINRANK3_RxEq_MSK                         (0x000F8000)
+  #define DDRDATA3CH0_CR_RXTRAINRANK3_RxEq_MAX                         (0x0000001F)
+  #define DDRDATA3CH0_CR_RXTRAINRANK3_RxDqsNPi_OFF                     (20)
+  #define DDRDATA3CH0_CR_RXTRAINRANK3_RxDqsNPi_WID                     ( 6)
+  #define DDRDATA3CH0_CR_RXTRAINRANK3_RxDqsNPi_MSK                     (0x03F00000)
+  #define DDRDATA3CH0_CR_RXTRAINRANK3_RxDqsNPi_MAX                     (0x0000003F)
+  #define DDRDATA3CH0_CR_RXTRAINRANK3_RxVref_OFF                       (26)
+  #define DDRDATA3CH0_CR_RXTRAINRANK3_RxVref_WID                       ( 6)
+  #define DDRDATA3CH0_CR_RXTRAINRANK3_RxVref_MSK                       (0xFC000000)
+  #define DDRDATA3CH0_CR_RXTRAINRANK3_RxVref_MAX                       (0x0000003F)
+
+#define DDRDATA3CH0_CR_RXPERBITRANK0_REG                             (0x00000610)
+  #define DDRDATA3CH0_CR_RXPERBITRANK0_Lane0_OFF                       ( 0)
+  #define DDRDATA3CH0_CR_RXPERBITRANK0_Lane0_WID                       ( 4)
+  #define DDRDATA3CH0_CR_RXPERBITRANK0_Lane0_MSK                       (0x0000000F)
+  #define DDRDATA3CH0_CR_RXPERBITRANK0_Lane0_MAX                       (0x0000000F)
+  #define DDRDATA3CH0_CR_RXPERBITRANK0_Lane1_OFF                       ( 4)
+  #define DDRDATA3CH0_CR_RXPERBITRANK0_Lane1_WID                       ( 4)
+  #define DDRDATA3CH0_CR_RXPERBITRANK0_Lane1_MSK                       (0x000000F0)
+  #define DDRDATA3CH0_CR_RXPERBITRANK0_Lane1_MAX                       (0x0000000F)
+  #define DDRDATA3CH0_CR_RXPERBITRANK0_Lane2_OFF                       ( 8)
+  #define DDRDATA3CH0_CR_RXPERBITRANK0_Lane2_WID                       ( 4)
+  #define DDRDATA3CH0_CR_RXPERBITRANK0_Lane2_MSK                       (0x00000F00)
+  #define DDRDATA3CH0_CR_RXPERBITRANK0_Lane2_MAX                       (0x0000000F)
+  #define DDRDATA3CH0_CR_RXPERBITRANK0_Lane3_OFF                       (12)
+  #define DDRDATA3CH0_CR_RXPERBITRANK0_Lane3_WID                       ( 4)
+  #define DDRDATA3CH0_CR_RXPERBITRANK0_Lane3_MSK                       (0x0000F000)
+  #define DDRDATA3CH0_CR_RXPERBITRANK0_Lane3_MAX                       (0x0000000F)
+  #define DDRDATA3CH0_CR_RXPERBITRANK0_Lane4_OFF                       (16)
+  #define DDRDATA3CH0_CR_RXPERBITRANK0_Lane4_WID                       ( 4)
+  #define DDRDATA3CH0_CR_RXPERBITRANK0_Lane4_MSK                       (0x000F0000)
+  #define DDRDATA3CH0_CR_RXPERBITRANK0_Lane4_MAX                       (0x0000000F)
+  #define DDRDATA3CH0_CR_RXPERBITRANK0_Lane5_OFF                       (20)
+  #define DDRDATA3CH0_CR_RXPERBITRANK0_Lane5_WID                       ( 4)
+  #define DDRDATA3CH0_CR_RXPERBITRANK0_Lane5_MSK                       (0x00F00000)
+  #define DDRDATA3CH0_CR_RXPERBITRANK0_Lane5_MAX                       (0x0000000F)
+  #define DDRDATA3CH0_CR_RXPERBITRANK0_Lane6_OFF                       (24)
+  #define DDRDATA3CH0_CR_RXPERBITRANK0_Lane6_WID                       ( 4)
+  #define DDRDATA3CH0_CR_RXPERBITRANK0_Lane6_MSK                       (0x0F000000)
+  #define DDRDATA3CH0_CR_RXPERBITRANK0_Lane6_MAX                       (0x0000000F)
+  #define DDRDATA3CH0_CR_RXPERBITRANK0_Lane7_OFF                       (28)
+  #define DDRDATA3CH0_CR_RXPERBITRANK0_Lane7_WID                       ( 4)
+  #define DDRDATA3CH0_CR_RXPERBITRANK0_Lane7_MSK                       (0xF0000000)
+  #define DDRDATA3CH0_CR_RXPERBITRANK0_Lane7_MAX                       (0x0000000F)
+
+#define DDRDATA3CH0_CR_RXPERBITRANK1_REG                             (0x00000614)
+  #define DDRDATA3CH0_CR_RXPERBITRANK1_Lane0_OFF                       ( 0)
+  #define DDRDATA3CH0_CR_RXPERBITRANK1_Lane0_WID                       ( 4)
+  #define DDRDATA3CH0_CR_RXPERBITRANK1_Lane0_MSK                       (0x0000000F)
+  #define DDRDATA3CH0_CR_RXPERBITRANK1_Lane0_MAX                       (0x0000000F)
+  #define DDRDATA3CH0_CR_RXPERBITRANK1_Lane1_OFF                       ( 4)
+  #define DDRDATA3CH0_CR_RXPERBITRANK1_Lane1_WID                       ( 4)
+  #define DDRDATA3CH0_CR_RXPERBITRANK1_Lane1_MSK                       (0x000000F0)
+  #define DDRDATA3CH0_CR_RXPERBITRANK1_Lane1_MAX                       (0x0000000F)
+  #define DDRDATA3CH0_CR_RXPERBITRANK1_Lane2_OFF                       ( 8)
+  #define DDRDATA3CH0_CR_RXPERBITRANK1_Lane2_WID                       ( 4)
+  #define DDRDATA3CH0_CR_RXPERBITRANK1_Lane2_MSK                       (0x00000F00)
+  #define DDRDATA3CH0_CR_RXPERBITRANK1_Lane2_MAX                       (0x0000000F)
+  #define DDRDATA3CH0_CR_RXPERBITRANK1_Lane3_OFF                       (12)
+  #define DDRDATA3CH0_CR_RXPERBITRANK1_Lane3_WID                       ( 4)
+  #define DDRDATA3CH0_CR_RXPERBITRANK1_Lane3_MSK                       (0x0000F000)
+  #define DDRDATA3CH0_CR_RXPERBITRANK1_Lane3_MAX                       (0x0000000F)
+  #define DDRDATA3CH0_CR_RXPERBITRANK1_Lane4_OFF                       (16)
+  #define DDRDATA3CH0_CR_RXPERBITRANK1_Lane4_WID                       ( 4)
+  #define DDRDATA3CH0_CR_RXPERBITRANK1_Lane4_MSK                       (0x000F0000)
+  #define DDRDATA3CH0_CR_RXPERBITRANK1_Lane4_MAX                       (0x0000000F)
+  #define DDRDATA3CH0_CR_RXPERBITRANK1_Lane5_OFF                       (20)
+  #define DDRDATA3CH0_CR_RXPERBITRANK1_Lane5_WID                       ( 4)
+  #define DDRDATA3CH0_CR_RXPERBITRANK1_Lane5_MSK                       (0x00F00000)
+  #define DDRDATA3CH0_CR_RXPERBITRANK1_Lane5_MAX                       (0x0000000F)
+  #define DDRDATA3CH0_CR_RXPERBITRANK1_Lane6_OFF                       (24)
+  #define DDRDATA3CH0_CR_RXPERBITRANK1_Lane6_WID                       ( 4)
+  #define DDRDATA3CH0_CR_RXPERBITRANK1_Lane6_MSK                       (0x0F000000)
+  #define DDRDATA3CH0_CR_RXPERBITRANK1_Lane6_MAX                       (0x0000000F)
+  #define DDRDATA3CH0_CR_RXPERBITRANK1_Lane7_OFF                       (28)
+  #define DDRDATA3CH0_CR_RXPERBITRANK1_Lane7_WID                       ( 4)
+  #define DDRDATA3CH0_CR_RXPERBITRANK1_Lane7_MSK                       (0xF0000000)
+  #define DDRDATA3CH0_CR_RXPERBITRANK1_Lane7_MAX                       (0x0000000F)
+
+#define DDRDATA3CH0_CR_RXPERBITRANK2_REG                             (0x00000618)
+  #define DDRDATA3CH0_CR_RXPERBITRANK2_Lane0_OFF                       ( 0)
+  #define DDRDATA3CH0_CR_RXPERBITRANK2_Lane0_WID                       ( 4)
+  #define DDRDATA3CH0_CR_RXPERBITRANK2_Lane0_MSK                       (0x0000000F)
+  #define DDRDATA3CH0_CR_RXPERBITRANK2_Lane0_MAX                       (0x0000000F)
+  #define DDRDATA3CH0_CR_RXPERBITRANK2_Lane1_OFF                       ( 4)
+  #define DDRDATA3CH0_CR_RXPERBITRANK2_Lane1_WID                       ( 4)
+  #define DDRDATA3CH0_CR_RXPERBITRANK2_Lane1_MSK                       (0x000000F0)
+  #define DDRDATA3CH0_CR_RXPERBITRANK2_Lane1_MAX                       (0x0000000F)
+  #define DDRDATA3CH0_CR_RXPERBITRANK2_Lane2_OFF                       ( 8)
+  #define DDRDATA3CH0_CR_RXPERBITRANK2_Lane2_WID                       ( 4)
+  #define DDRDATA3CH0_CR_RXPERBITRANK2_Lane2_MSK                       (0x00000F00)
+  #define DDRDATA3CH0_CR_RXPERBITRANK2_Lane2_MAX                       (0x0000000F)
+  #define DDRDATA3CH0_CR_RXPERBITRANK2_Lane3_OFF                       (12)
+  #define DDRDATA3CH0_CR_RXPERBITRANK2_Lane3_WID                       ( 4)
+  #define DDRDATA3CH0_CR_RXPERBITRANK2_Lane3_MSK                       (0x0000F000)
+  #define DDRDATA3CH0_CR_RXPERBITRANK2_Lane3_MAX                       (0x0000000F)
+  #define DDRDATA3CH0_CR_RXPERBITRANK2_Lane4_OFF                       (16)
+  #define DDRDATA3CH0_CR_RXPERBITRANK2_Lane4_WID                       ( 4)
+  #define DDRDATA3CH0_CR_RXPERBITRANK2_Lane4_MSK                       (0x000F0000)
+  #define DDRDATA3CH0_CR_RXPERBITRANK2_Lane4_MAX                       (0x0000000F)
+  #define DDRDATA3CH0_CR_RXPERBITRANK2_Lane5_OFF                       (20)
+  #define DDRDATA3CH0_CR_RXPERBITRANK2_Lane5_WID                       ( 4)
+  #define DDRDATA3CH0_CR_RXPERBITRANK2_Lane5_MSK                       (0x00F00000)
+  #define DDRDATA3CH0_CR_RXPERBITRANK2_Lane5_MAX                       (0x0000000F)
+  #define DDRDATA3CH0_CR_RXPERBITRANK2_Lane6_OFF                       (24)
+  #define DDRDATA3CH0_CR_RXPERBITRANK2_Lane6_WID                       ( 4)
+  #define DDRDATA3CH0_CR_RXPERBITRANK2_Lane6_MSK                       (0x0F000000)
+  #define DDRDATA3CH0_CR_RXPERBITRANK2_Lane6_MAX                       (0x0000000F)
+  #define DDRDATA3CH0_CR_RXPERBITRANK2_Lane7_OFF                       (28)
+  #define DDRDATA3CH0_CR_RXPERBITRANK2_Lane7_WID                       ( 4)
+  #define DDRDATA3CH0_CR_RXPERBITRANK2_Lane7_MSK                       (0xF0000000)
+  #define DDRDATA3CH0_CR_RXPERBITRANK2_Lane7_MAX                       (0x0000000F)
+
+#define DDRDATA3CH0_CR_RXPERBITRANK3_REG                             (0x0000061C)
+  #define DDRDATA3CH0_CR_RXPERBITRANK3_Lane0_OFF                       ( 0)
+  #define DDRDATA3CH0_CR_RXPERBITRANK3_Lane0_WID                       ( 4)
+  #define DDRDATA3CH0_CR_RXPERBITRANK3_Lane0_MSK                       (0x0000000F)
+  #define DDRDATA3CH0_CR_RXPERBITRANK3_Lane0_MAX                       (0x0000000F)
+  #define DDRDATA3CH0_CR_RXPERBITRANK3_Lane1_OFF                       ( 4)
+  #define DDRDATA3CH0_CR_RXPERBITRANK3_Lane1_WID                       ( 4)
+  #define DDRDATA3CH0_CR_RXPERBITRANK3_Lane1_MSK                       (0x000000F0)
+  #define DDRDATA3CH0_CR_RXPERBITRANK3_Lane1_MAX                       (0x0000000F)
+  #define DDRDATA3CH0_CR_RXPERBITRANK3_Lane2_OFF                       ( 8)
+  #define DDRDATA3CH0_CR_RXPERBITRANK3_Lane2_WID                       ( 4)
+  #define DDRDATA3CH0_CR_RXPERBITRANK3_Lane2_MSK                       (0x00000F00)
+  #define DDRDATA3CH0_CR_RXPERBITRANK3_Lane2_MAX                       (0x0000000F)
+  #define DDRDATA3CH0_CR_RXPERBITRANK3_Lane3_OFF                       (12)
+  #define DDRDATA3CH0_CR_RXPERBITRANK3_Lane3_WID                       ( 4)
+  #define DDRDATA3CH0_CR_RXPERBITRANK3_Lane3_MSK                       (0x0000F000)
+  #define DDRDATA3CH0_CR_RXPERBITRANK3_Lane3_MAX                       (0x0000000F)
+  #define DDRDATA3CH0_CR_RXPERBITRANK3_Lane4_OFF                       (16)
+  #define DDRDATA3CH0_CR_RXPERBITRANK3_Lane4_WID                       ( 4)
+  #define DDRDATA3CH0_CR_RXPERBITRANK3_Lane4_MSK                       (0x000F0000)
+  #define DDRDATA3CH0_CR_RXPERBITRANK3_Lane4_MAX                       (0x0000000F)
+  #define DDRDATA3CH0_CR_RXPERBITRANK3_Lane5_OFF                       (20)
+  #define DDRDATA3CH0_CR_RXPERBITRANK3_Lane5_WID                       ( 4)
+  #define DDRDATA3CH0_CR_RXPERBITRANK3_Lane5_MSK                       (0x00F00000)
+  #define DDRDATA3CH0_CR_RXPERBITRANK3_Lane5_MAX                       (0x0000000F)
+  #define DDRDATA3CH0_CR_RXPERBITRANK3_Lane6_OFF                       (24)
+  #define DDRDATA3CH0_CR_RXPERBITRANK3_Lane6_WID                       ( 4)
+  #define DDRDATA3CH0_CR_RXPERBITRANK3_Lane6_MSK                       (0x0F000000)
+  #define DDRDATA3CH0_CR_RXPERBITRANK3_Lane6_MAX                       (0x0000000F)
+  #define DDRDATA3CH0_CR_RXPERBITRANK3_Lane7_OFF                       (28)
+  #define DDRDATA3CH0_CR_RXPERBITRANK3_Lane7_WID                       ( 4)
+  #define DDRDATA3CH0_CR_RXPERBITRANK3_Lane7_MSK                       (0xF0000000)
+  #define DDRDATA3CH0_CR_RXPERBITRANK3_Lane7_MAX                       (0x0000000F)
+
+#define DDRDATA3CH0_CR_TXTRAINRANK0_REG                              (0x00000620)
+  #define DDRDATA3CH0_CR_TXTRAINRANK0_TxDqDelay_OFF                    ( 0)
+  #define DDRDATA3CH0_CR_TXTRAINRANK0_TxDqDelay_WID                    ( 9)
+  #define DDRDATA3CH0_CR_TXTRAINRANK0_TxDqDelay_MSK                    (0x000001FF)
+  #define DDRDATA3CH0_CR_TXTRAINRANK0_TxDqDelay_MAX                    (0x000001FF)
+  #define DDRDATA3CH0_CR_TXTRAINRANK0_TxDqsDelay_OFF                   ( 9)
+  #define DDRDATA3CH0_CR_TXTRAINRANK0_TxDqsDelay_WID                   ( 9)
+  #define DDRDATA3CH0_CR_TXTRAINRANK0_TxDqsDelay_MSK                   (0x0003FE00)
+  #define DDRDATA3CH0_CR_TXTRAINRANK0_TxDqsDelay_MAX                   (0x000001FF)
+  #define DDRDATA3CH0_CR_TXTRAINRANK0_Spare0_OFF                       (18)
+  #define DDRDATA3CH0_CR_TXTRAINRANK0_Spare0_WID                       ( 2)
+  #define DDRDATA3CH0_CR_TXTRAINRANK0_Spare0_MSK                       (0x000C0000)
+  #define DDRDATA3CH0_CR_TXTRAINRANK0_Spare0_MAX                       (0x00000003)
+  #define DDRDATA3CH0_CR_TXTRAINRANK0_TxEqualization_OFF               (20)
+  #define DDRDATA3CH0_CR_TXTRAINRANK0_TxEqualization_WID               ( 6)
+  #define DDRDATA3CH0_CR_TXTRAINRANK0_TxEqualization_MSK               (0x03F00000)
+  #define DDRDATA3CH0_CR_TXTRAINRANK0_TxEqualization_MAX               (0x0000003F)
+  #define DDRDATA3CH0_CR_TXTRAINRANK0_Spare1_OFF                       (26)
+  #define DDRDATA3CH0_CR_TXTRAINRANK0_Spare1_WID                       ( 6)
+  #define DDRDATA3CH0_CR_TXTRAINRANK0_Spare1_MSK                       (0xFC000000)
+  #define DDRDATA3CH0_CR_TXTRAINRANK0_Spare1_MAX                       (0x0000003F)
+
+#define DDRDATA3CH0_CR_TXTRAINRANK1_REG                              (0x00000624)
+  #define DDRDATA3CH0_CR_TXTRAINRANK1_TxDqDelay_OFF                    ( 0)
+  #define DDRDATA3CH0_CR_TXTRAINRANK1_TxDqDelay_WID                    ( 9)
+  #define DDRDATA3CH0_CR_TXTRAINRANK1_TxDqDelay_MSK                    (0x000001FF)
+  #define DDRDATA3CH0_CR_TXTRAINRANK1_TxDqDelay_MAX                    (0x000001FF)
+  #define DDRDATA3CH0_CR_TXTRAINRANK1_TxDqsDelay_OFF                   ( 9)
+  #define DDRDATA3CH0_CR_TXTRAINRANK1_TxDqsDelay_WID                   ( 9)
+  #define DDRDATA3CH0_CR_TXTRAINRANK1_TxDqsDelay_MSK                   (0x0003FE00)
+  #define DDRDATA3CH0_CR_TXTRAINRANK1_TxDqsDelay_MAX                   (0x000001FF)
+  #define DDRDATA3CH0_CR_TXTRAINRANK1_Spare0_OFF                       (18)
+  #define DDRDATA3CH0_CR_TXTRAINRANK1_Spare0_WID                       ( 2)
+  #define DDRDATA3CH0_CR_TXTRAINRANK1_Spare0_MSK                       (0x000C0000)
+  #define DDRDATA3CH0_CR_TXTRAINRANK1_Spare0_MAX                       (0x00000003)
+  #define DDRDATA3CH0_CR_TXTRAINRANK1_TxEqualization_OFF               (20)
+  #define DDRDATA3CH0_CR_TXTRAINRANK1_TxEqualization_WID               ( 6)
+  #define DDRDATA3CH0_CR_TXTRAINRANK1_TxEqualization_MSK               (0x03F00000)
+  #define DDRDATA3CH0_CR_TXTRAINRANK1_TxEqualization_MAX               (0x0000003F)
+  #define DDRDATA3CH0_CR_TXTRAINRANK1_Spare1_OFF                       (26)
+  #define DDRDATA3CH0_CR_TXTRAINRANK1_Spare1_WID                       ( 6)
+  #define DDRDATA3CH0_CR_TXTRAINRANK1_Spare1_MSK                       (0xFC000000)
+  #define DDRDATA3CH0_CR_TXTRAINRANK1_Spare1_MAX                       (0x0000003F)
+
+#define DDRDATA3CH0_CR_TXTRAINRANK2_REG                              (0x00000628)
+  #define DDRDATA3CH0_CR_TXTRAINRANK2_TxDqDelay_OFF                    ( 0)
+  #define DDRDATA3CH0_CR_TXTRAINRANK2_TxDqDelay_WID                    ( 9)
+  #define DDRDATA3CH0_CR_TXTRAINRANK2_TxDqDelay_MSK                    (0x000001FF)
+  #define DDRDATA3CH0_CR_TXTRAINRANK2_TxDqDelay_MAX                    (0x000001FF)
+  #define DDRDATA3CH0_CR_TXTRAINRANK2_TxDqsDelay_OFF                   ( 9)
+  #define DDRDATA3CH0_CR_TXTRAINRANK2_TxDqsDelay_WID                   ( 9)
+  #define DDRDATA3CH0_CR_TXTRAINRANK2_TxDqsDelay_MSK                   (0x0003FE00)
+  #define DDRDATA3CH0_CR_TXTRAINRANK2_TxDqsDelay_MAX                   (0x000001FF)
+  #define DDRDATA3CH0_CR_TXTRAINRANK2_Spare0_OFF                       (18)
+  #define DDRDATA3CH0_CR_TXTRAINRANK2_Spare0_WID                       ( 2)
+  #define DDRDATA3CH0_CR_TXTRAINRANK2_Spare0_MSK                       (0x000C0000)
+  #define DDRDATA3CH0_CR_TXTRAINRANK2_Spare0_MAX                       (0x00000003)
+  #define DDRDATA3CH0_CR_TXTRAINRANK2_TxEqualization_OFF               (20)
+  #define DDRDATA3CH0_CR_TXTRAINRANK2_TxEqualization_WID               ( 6)
+  #define DDRDATA3CH0_CR_TXTRAINRANK2_TxEqualization_MSK               (0x03F00000)
+  #define DDRDATA3CH0_CR_TXTRAINRANK2_TxEqualization_MAX               (0x0000003F)
+  #define DDRDATA3CH0_CR_TXTRAINRANK2_Spare1_OFF                       (26)
+  #define DDRDATA3CH0_CR_TXTRAINRANK2_Spare1_WID                       ( 6)
+  #define DDRDATA3CH0_CR_TXTRAINRANK2_Spare1_MSK                       (0xFC000000)
+  #define DDRDATA3CH0_CR_TXTRAINRANK2_Spare1_MAX                       (0x0000003F)
+
+#define DDRDATA3CH0_CR_TXTRAINRANK3_REG                              (0x0000062C)
+  #define DDRDATA3CH0_CR_TXTRAINRANK3_TxDqDelay_OFF                    ( 0)
+  #define DDRDATA3CH0_CR_TXTRAINRANK3_TxDqDelay_WID                    ( 9)
+  #define DDRDATA3CH0_CR_TXTRAINRANK3_TxDqDelay_MSK                    (0x000001FF)
+  #define DDRDATA3CH0_CR_TXTRAINRANK3_TxDqDelay_MAX                    (0x000001FF)
+  #define DDRDATA3CH0_CR_TXTRAINRANK3_TxDqsDelay_OFF                   ( 9)
+  #define DDRDATA3CH0_CR_TXTRAINRANK3_TxDqsDelay_WID                   ( 9)
+  #define DDRDATA3CH0_CR_TXTRAINRANK3_TxDqsDelay_MSK                   (0x0003FE00)
+  #define DDRDATA3CH0_CR_TXTRAINRANK3_TxDqsDelay_MAX                   (0x000001FF)
+  #define DDRDATA3CH0_CR_TXTRAINRANK3_Spare0_OFF                       (18)
+  #define DDRDATA3CH0_CR_TXTRAINRANK3_Spare0_WID                       ( 2)
+  #define DDRDATA3CH0_CR_TXTRAINRANK3_Spare0_MSK                       (0x000C0000)
+  #define DDRDATA3CH0_CR_TXTRAINRANK3_Spare0_MAX                       (0x00000003)
+  #define DDRDATA3CH0_CR_TXTRAINRANK3_TxEqualization_OFF               (20)
+  #define DDRDATA3CH0_CR_TXTRAINRANK3_TxEqualization_WID               ( 6)
+  #define DDRDATA3CH0_CR_TXTRAINRANK3_TxEqualization_MSK               (0x03F00000)
+  #define DDRDATA3CH0_CR_TXTRAINRANK3_TxEqualization_MAX               (0x0000003F)
+  #define DDRDATA3CH0_CR_TXTRAINRANK3_Spare1_OFF                       (26)
+  #define DDRDATA3CH0_CR_TXTRAINRANK3_Spare1_WID                       ( 6)
+  #define DDRDATA3CH0_CR_TXTRAINRANK3_Spare1_MSK                       (0xFC000000)
+  #define DDRDATA3CH0_CR_TXTRAINRANK3_Spare1_MAX                       (0x0000003F)
+
+#define DDRDATA3CH0_CR_TXPERBITRANK0_REG                             (0x00000630)
+  #define DDRDATA3CH0_CR_TXPERBITRANK0_Lane0_OFF                       ( 0)
+  #define DDRDATA3CH0_CR_TXPERBITRANK0_Lane0_WID                       ( 4)
+  #define DDRDATA3CH0_CR_TXPERBITRANK0_Lane0_MSK                       (0x0000000F)
+  #define DDRDATA3CH0_CR_TXPERBITRANK0_Lane0_MAX                       (0x0000000F)
+  #define DDRDATA3CH0_CR_TXPERBITRANK0_Lane1_OFF                       ( 4)
+  #define DDRDATA3CH0_CR_TXPERBITRANK0_Lane1_WID                       ( 4)
+  #define DDRDATA3CH0_CR_TXPERBITRANK0_Lane1_MSK                       (0x000000F0)
+  #define DDRDATA3CH0_CR_TXPERBITRANK0_Lane1_MAX                       (0x0000000F)
+  #define DDRDATA3CH0_CR_TXPERBITRANK0_Lane2_OFF                       ( 8)
+  #define DDRDATA3CH0_CR_TXPERBITRANK0_Lane2_WID                       ( 4)
+  #define DDRDATA3CH0_CR_TXPERBITRANK0_Lane2_MSK                       (0x00000F00)
+  #define DDRDATA3CH0_CR_TXPERBITRANK0_Lane2_MAX                       (0x0000000F)
+  #define DDRDATA3CH0_CR_TXPERBITRANK0_Lane3_OFF                       (12)
+  #define DDRDATA3CH0_CR_TXPERBITRANK0_Lane3_WID                       ( 4)
+  #define DDRDATA3CH0_CR_TXPERBITRANK0_Lane3_MSK                       (0x0000F000)
+  #define DDRDATA3CH0_CR_TXPERBITRANK0_Lane3_MAX                       (0x0000000F)
+  #define DDRDATA3CH0_CR_TXPERBITRANK0_Lane4_OFF                       (16)
+  #define DDRDATA3CH0_CR_TXPERBITRANK0_Lane4_WID                       ( 4)
+  #define DDRDATA3CH0_CR_TXPERBITRANK0_Lane4_MSK                       (0x000F0000)
+  #define DDRDATA3CH0_CR_TXPERBITRANK0_Lane4_MAX                       (0x0000000F)
+  #define DDRDATA3CH0_CR_TXPERBITRANK0_Lane5_OFF                       (20)
+  #define DDRDATA3CH0_CR_TXPERBITRANK0_Lane5_WID                       ( 4)
+  #define DDRDATA3CH0_CR_TXPERBITRANK0_Lane5_MSK                       (0x00F00000)
+  #define DDRDATA3CH0_CR_TXPERBITRANK0_Lane5_MAX                       (0x0000000F)
+  #define DDRDATA3CH0_CR_TXPERBITRANK0_Lane6_OFF                       (24)
+  #define DDRDATA3CH0_CR_TXPERBITRANK0_Lane6_WID                       ( 4)
+  #define DDRDATA3CH0_CR_TXPERBITRANK0_Lane6_MSK                       (0x0F000000)
+  #define DDRDATA3CH0_CR_TXPERBITRANK0_Lane6_MAX                       (0x0000000F)
+  #define DDRDATA3CH0_CR_TXPERBITRANK0_Lane7_OFF                       (28)
+  #define DDRDATA3CH0_CR_TXPERBITRANK0_Lane7_WID                       ( 4)
+  #define DDRDATA3CH0_CR_TXPERBITRANK0_Lane7_MSK                       (0xF0000000)
+  #define DDRDATA3CH0_CR_TXPERBITRANK0_Lane7_MAX                       (0x0000000F)
+
+#define DDRDATA3CH0_CR_TXPERBITRANK1_REG                             (0x00000634)
+  #define DDRDATA3CH0_CR_TXPERBITRANK1_Lane0_OFF                       ( 0)
+  #define DDRDATA3CH0_CR_TXPERBITRANK1_Lane0_WID                       ( 4)
+  #define DDRDATA3CH0_CR_TXPERBITRANK1_Lane0_MSK                       (0x0000000F)
+  #define DDRDATA3CH0_CR_TXPERBITRANK1_Lane0_MAX                       (0x0000000F)
+  #define DDRDATA3CH0_CR_TXPERBITRANK1_Lane1_OFF                       ( 4)
+  #define DDRDATA3CH0_CR_TXPERBITRANK1_Lane1_WID                       ( 4)
+  #define DDRDATA3CH0_CR_TXPERBITRANK1_Lane1_MSK                       (0x000000F0)
+  #define DDRDATA3CH0_CR_TXPERBITRANK1_Lane1_MAX                       (0x0000000F)
+  #define DDRDATA3CH0_CR_TXPERBITRANK1_Lane2_OFF                       ( 8)
+  #define DDRDATA3CH0_CR_TXPERBITRANK1_Lane2_WID                       ( 4)
+  #define DDRDATA3CH0_CR_TXPERBITRANK1_Lane2_MSK                       (0x00000F00)
+  #define DDRDATA3CH0_CR_TXPERBITRANK1_Lane2_MAX                       (0x0000000F)
+  #define DDRDATA3CH0_CR_TXPERBITRANK1_Lane3_OFF                       (12)
+  #define DDRDATA3CH0_CR_TXPERBITRANK1_Lane3_WID                       ( 4)
+  #define DDRDATA3CH0_CR_TXPERBITRANK1_Lane3_MSK                       (0x0000F000)
+  #define DDRDATA3CH0_CR_TXPERBITRANK1_Lane3_MAX                       (0x0000000F)
+  #define DDRDATA3CH0_CR_TXPERBITRANK1_Lane4_OFF                       (16)
+  #define DDRDATA3CH0_CR_TXPERBITRANK1_Lane4_WID                       ( 4)
+  #define DDRDATA3CH0_CR_TXPERBITRANK1_Lane4_MSK                       (0x000F0000)
+  #define DDRDATA3CH0_CR_TXPERBITRANK1_Lane4_MAX                       (0x0000000F)
+  #define DDRDATA3CH0_CR_TXPERBITRANK1_Lane5_OFF                       (20)
+  #define DDRDATA3CH0_CR_TXPERBITRANK1_Lane5_WID                       ( 4)
+  #define DDRDATA3CH0_CR_TXPERBITRANK1_Lane5_MSK                       (0x00F00000)
+  #define DDRDATA3CH0_CR_TXPERBITRANK1_Lane5_MAX                       (0x0000000F)
+  #define DDRDATA3CH0_CR_TXPERBITRANK1_Lane6_OFF                       (24)
+  #define DDRDATA3CH0_CR_TXPERBITRANK1_Lane6_WID                       ( 4)
+  #define DDRDATA3CH0_CR_TXPERBITRANK1_Lane6_MSK                       (0x0F000000)
+  #define DDRDATA3CH0_CR_TXPERBITRANK1_Lane6_MAX                       (0x0000000F)
+  #define DDRDATA3CH0_CR_TXPERBITRANK1_Lane7_OFF                       (28)
+  #define DDRDATA3CH0_CR_TXPERBITRANK1_Lane7_WID                       ( 4)
+  #define DDRDATA3CH0_CR_TXPERBITRANK1_Lane7_MSK                       (0xF0000000)
+  #define DDRDATA3CH0_CR_TXPERBITRANK1_Lane7_MAX                       (0x0000000F)
+
+#define DDRDATA3CH0_CR_TXPERBITRANK2_REG                             (0x00000638)
+  #define DDRDATA3CH0_CR_TXPERBITRANK2_Lane0_OFF                       ( 0)
+  #define DDRDATA3CH0_CR_TXPERBITRANK2_Lane0_WID                       ( 4)
+  #define DDRDATA3CH0_CR_TXPERBITRANK2_Lane0_MSK                       (0x0000000F)
+  #define DDRDATA3CH0_CR_TXPERBITRANK2_Lane0_MAX                       (0x0000000F)
+  #define DDRDATA3CH0_CR_TXPERBITRANK2_Lane1_OFF                       ( 4)
+  #define DDRDATA3CH0_CR_TXPERBITRANK2_Lane1_WID                       ( 4)
+  #define DDRDATA3CH0_CR_TXPERBITRANK2_Lane1_MSK                       (0x000000F0)
+  #define DDRDATA3CH0_CR_TXPERBITRANK2_Lane1_MAX                       (0x0000000F)
+  #define DDRDATA3CH0_CR_TXPERBITRANK2_Lane2_OFF                       ( 8)
+  #define DDRDATA3CH0_CR_TXPERBITRANK2_Lane2_WID                       ( 4)
+  #define DDRDATA3CH0_CR_TXPERBITRANK2_Lane2_MSK                       (0x00000F00)
+  #define DDRDATA3CH0_CR_TXPERBITRANK2_Lane2_MAX                       (0x0000000F)
+  #define DDRDATA3CH0_CR_TXPERBITRANK2_Lane3_OFF                       (12)
+  #define DDRDATA3CH0_CR_TXPERBITRANK2_Lane3_WID                       ( 4)
+  #define DDRDATA3CH0_CR_TXPERBITRANK2_Lane3_MSK                       (0x0000F000)
+  #define DDRDATA3CH0_CR_TXPERBITRANK2_Lane3_MAX                       (0x0000000F)
+  #define DDRDATA3CH0_CR_TXPERBITRANK2_Lane4_OFF                       (16)
+  #define DDRDATA3CH0_CR_TXPERBITRANK2_Lane4_WID                       ( 4)
+  #define DDRDATA3CH0_CR_TXPERBITRANK2_Lane4_MSK                       (0x000F0000)
+  #define DDRDATA3CH0_CR_TXPERBITRANK2_Lane4_MAX                       (0x0000000F)
+  #define DDRDATA3CH0_CR_TXPERBITRANK2_Lane5_OFF                       (20)
+  #define DDRDATA3CH0_CR_TXPERBITRANK2_Lane5_WID                       ( 4)
+  #define DDRDATA3CH0_CR_TXPERBITRANK2_Lane5_MSK                       (0x00F00000)
+  #define DDRDATA3CH0_CR_TXPERBITRANK2_Lane5_MAX                       (0x0000000F)
+  #define DDRDATA3CH0_CR_TXPERBITRANK2_Lane6_OFF                       (24)
+  #define DDRDATA3CH0_CR_TXPERBITRANK2_Lane6_WID                       ( 4)
+  #define DDRDATA3CH0_CR_TXPERBITRANK2_Lane6_MSK                       (0x0F000000)
+  #define DDRDATA3CH0_CR_TXPERBITRANK2_Lane6_MAX                       (0x0000000F)
+  #define DDRDATA3CH0_CR_TXPERBITRANK2_Lane7_OFF                       (28)
+  #define DDRDATA3CH0_CR_TXPERBITRANK2_Lane7_WID                       ( 4)
+  #define DDRDATA3CH0_CR_TXPERBITRANK2_Lane7_MSK                       (0xF0000000)
+  #define DDRDATA3CH0_CR_TXPERBITRANK2_Lane7_MAX                       (0x0000000F)
+
+#define DDRDATA3CH0_CR_TXPERBITRANK3_REG                             (0x0000063C)
+  #define DDRDATA3CH0_CR_TXPERBITRANK3_Lane0_OFF                       ( 0)
+  #define DDRDATA3CH0_CR_TXPERBITRANK3_Lane0_WID                       ( 4)
+  #define DDRDATA3CH0_CR_TXPERBITRANK3_Lane0_MSK                       (0x0000000F)
+  #define DDRDATA3CH0_CR_TXPERBITRANK3_Lane0_MAX                       (0x0000000F)
+  #define DDRDATA3CH0_CR_TXPERBITRANK3_Lane1_OFF                       ( 4)
+  #define DDRDATA3CH0_CR_TXPERBITRANK3_Lane1_WID                       ( 4)
+  #define DDRDATA3CH0_CR_TXPERBITRANK3_Lane1_MSK                       (0x000000F0)
+  #define DDRDATA3CH0_CR_TXPERBITRANK3_Lane1_MAX                       (0x0000000F)
+  #define DDRDATA3CH0_CR_TXPERBITRANK3_Lane2_OFF                       ( 8)
+  #define DDRDATA3CH0_CR_TXPERBITRANK3_Lane2_WID                       ( 4)
+  #define DDRDATA3CH0_CR_TXPERBITRANK3_Lane2_MSK                       (0x00000F00)
+  #define DDRDATA3CH0_CR_TXPERBITRANK3_Lane2_MAX                       (0x0000000F)
+  #define DDRDATA3CH0_CR_TXPERBITRANK3_Lane3_OFF                       (12)
+  #define DDRDATA3CH0_CR_TXPERBITRANK3_Lane3_WID                       ( 4)
+  #define DDRDATA3CH0_CR_TXPERBITRANK3_Lane3_MSK                       (0x0000F000)
+  #define DDRDATA3CH0_CR_TXPERBITRANK3_Lane3_MAX                       (0x0000000F)
+  #define DDRDATA3CH0_CR_TXPERBITRANK3_Lane4_OFF                       (16)
+  #define DDRDATA3CH0_CR_TXPERBITRANK3_Lane4_WID                       ( 4)
+  #define DDRDATA3CH0_CR_TXPERBITRANK3_Lane4_MSK                       (0x000F0000)
+  #define DDRDATA3CH0_CR_TXPERBITRANK3_Lane4_MAX                       (0x0000000F)
+  #define DDRDATA3CH0_CR_TXPERBITRANK3_Lane5_OFF                       (20)
+  #define DDRDATA3CH0_CR_TXPERBITRANK3_Lane5_WID                       ( 4)
+  #define DDRDATA3CH0_CR_TXPERBITRANK3_Lane5_MSK                       (0x00F00000)
+  #define DDRDATA3CH0_CR_TXPERBITRANK3_Lane5_MAX                       (0x0000000F)
+  #define DDRDATA3CH0_CR_TXPERBITRANK3_Lane6_OFF                       (24)
+  #define DDRDATA3CH0_CR_TXPERBITRANK3_Lane6_WID                       ( 4)
+  #define DDRDATA3CH0_CR_TXPERBITRANK3_Lane6_MSK                       (0x0F000000)
+  #define DDRDATA3CH0_CR_TXPERBITRANK3_Lane6_MAX                       (0x0000000F)
+  #define DDRDATA3CH0_CR_TXPERBITRANK3_Lane7_OFF                       (28)
+  #define DDRDATA3CH0_CR_TXPERBITRANK3_Lane7_WID                       ( 4)
+  #define DDRDATA3CH0_CR_TXPERBITRANK3_Lane7_MSK                       (0xF0000000)
+  #define DDRDATA3CH0_CR_TXPERBITRANK3_Lane7_MAX                       (0x0000000F)
+
+#define DDRDATA3CH0_CR_RCOMPDATA0_REG                                (0x00000640)
+  #define DDRDATA3CH0_CR_RCOMPDATA0_RcompDrvUp_OFF                     ( 0)
+  #define DDRDATA3CH0_CR_RCOMPDATA0_RcompDrvUp_WID                     ( 6)
+  #define DDRDATA3CH0_CR_RCOMPDATA0_RcompDrvUp_MSK                     (0x0000003F)
+  #define DDRDATA3CH0_CR_RCOMPDATA0_RcompDrvUp_MAX                     (0x0000003F)
+  #define DDRDATA3CH0_CR_RCOMPDATA0_Spare0_OFF                         ( 6)
+  #define DDRDATA3CH0_CR_RCOMPDATA0_Spare0_WID                         ( 3)
+  #define DDRDATA3CH0_CR_RCOMPDATA0_Spare0_MSK                         (0x000001C0)
+  #define DDRDATA3CH0_CR_RCOMPDATA0_Spare0_MAX                         (0x00000007)
+  #define DDRDATA3CH0_CR_RCOMPDATA0_RcompDrvDown_OFF                   ( 9)
+  #define DDRDATA3CH0_CR_RCOMPDATA0_RcompDrvDown_WID                   ( 6)
+  #define DDRDATA3CH0_CR_RCOMPDATA0_RcompDrvDown_MSK                   (0x00007E00)
+  #define DDRDATA3CH0_CR_RCOMPDATA0_RcompDrvDown_MAX                   (0x0000003F)
+  #define DDRDATA3CH0_CR_RCOMPDATA0_VTComp_OFF                         (15)
+  #define DDRDATA3CH0_CR_RCOMPDATA0_VTComp_WID                         ( 5)
+  #define DDRDATA3CH0_CR_RCOMPDATA0_VTComp_MSK                         (0x000F8000)
+  #define DDRDATA3CH0_CR_RCOMPDATA0_VTComp_MAX                         (0x0000001F)
+  #define DDRDATA3CH0_CR_RCOMPDATA0_TcoComp_OFF                        (20)
+  #define DDRDATA3CH0_CR_RCOMPDATA0_TcoComp_WID                        ( 6)
+  #define DDRDATA3CH0_CR_RCOMPDATA0_TcoComp_MSK                        (0x03F00000)
+  #define DDRDATA3CH0_CR_RCOMPDATA0_TcoComp_MAX                        (0x0000003F)
+  #define DDRDATA3CH0_CR_RCOMPDATA0_SlewRateComp_OFF                   (26)
+  #define DDRDATA3CH0_CR_RCOMPDATA0_SlewRateComp_WID                   ( 5)
+  #define DDRDATA3CH0_CR_RCOMPDATA0_SlewRateComp_MSK                   (0x7C000000)
+  #define DDRDATA3CH0_CR_RCOMPDATA0_SlewRateComp_MAX                   (0x0000001F)
+  #define DDRDATA3CH0_CR_RCOMPDATA0_Spare2_OFF                         (31)
+  #define DDRDATA3CH0_CR_RCOMPDATA0_Spare2_WID                         ( 1)
+  #define DDRDATA3CH0_CR_RCOMPDATA0_Spare2_MSK                         (0x80000000)
+  #define DDRDATA3CH0_CR_RCOMPDATA0_Spare2_MAX                         (0x00000001)
+
+#define DDRDATA3CH0_CR_RCOMPDATA1_REG                                (0x00000644)
+  #define DDRDATA3CH0_CR_RCOMPDATA1_RcompOdtUp_OFF                     ( 0)
+  #define DDRDATA3CH0_CR_RCOMPDATA1_RcompOdtUp_WID                     ( 6)
+  #define DDRDATA3CH0_CR_RCOMPDATA1_RcompOdtUp_MSK                     (0x0000003F)
+  #define DDRDATA3CH0_CR_RCOMPDATA1_RcompOdtUp_MAX                     (0x0000003F)
+  #define DDRDATA3CH0_CR_RCOMPDATA1_Spare0_OFF                         ( 6)
+  #define DDRDATA3CH0_CR_RCOMPDATA1_Spare0_WID                         ( 3)
+  #define DDRDATA3CH0_CR_RCOMPDATA1_Spare0_MSK                         (0x000001C0)
+  #define DDRDATA3CH0_CR_RCOMPDATA1_Spare0_MAX                         (0x00000007)
+  #define DDRDATA3CH0_CR_RCOMPDATA1_RcompOdtDown_OFF                   ( 9)
+  #define DDRDATA3CH0_CR_RCOMPDATA1_RcompOdtDown_WID                   ( 6)
+  #define DDRDATA3CH0_CR_RCOMPDATA1_RcompOdtDown_MSK                   (0x00007E00)
+  #define DDRDATA3CH0_CR_RCOMPDATA1_RcompOdtDown_MAX                   (0x0000003F)
+  #define DDRDATA3CH0_CR_RCOMPDATA1_Spare1_OFF                         (15)
+  #define DDRDATA3CH0_CR_RCOMPDATA1_Spare1_WID                         ( 1)
+  #define DDRDATA3CH0_CR_RCOMPDATA1_Spare1_MSK                         (0x00008000)
+  #define DDRDATA3CH0_CR_RCOMPDATA1_Spare1_MAX                         (0x00000001)
+  #define DDRDATA3CH0_CR_RCOMPDATA1_PanicDrvDn_OFF                     (16)
+  #define DDRDATA3CH0_CR_RCOMPDATA1_PanicDrvDn_WID                     ( 6)
+  #define DDRDATA3CH0_CR_RCOMPDATA1_PanicDrvDn_MSK                     (0x003F0000)
+  #define DDRDATA3CH0_CR_RCOMPDATA1_PanicDrvDn_MAX                     (0x0000003F)
+  #define DDRDATA3CH0_CR_RCOMPDATA1_PanicDrvUp_OFF                     (22)
+  #define DDRDATA3CH0_CR_RCOMPDATA1_PanicDrvUp_WID                     ( 6)
+  #define DDRDATA3CH0_CR_RCOMPDATA1_PanicDrvUp_MSK                     (0x0FC00000)
+  #define DDRDATA3CH0_CR_RCOMPDATA1_PanicDrvUp_MAX                     (0x0000003F)
+  #define DDRDATA3CH0_CR_RCOMPDATA1_LevelShifterComp_OFF               (28)
+  #define DDRDATA3CH0_CR_RCOMPDATA1_LevelShifterComp_WID               ( 3)
+  #define DDRDATA3CH0_CR_RCOMPDATA1_LevelShifterComp_MSK               (0x70000000)
+  #define DDRDATA3CH0_CR_RCOMPDATA1_LevelShifterComp_MAX               (0x00000007)
+  #define DDRDATA3CH0_CR_RCOMPDATA1_Spare2_OFF                         (31)
+  #define DDRDATA3CH0_CR_RCOMPDATA1_Spare2_WID                         ( 1)
+  #define DDRDATA3CH0_CR_RCOMPDATA1_Spare2_MSK                         (0x80000000)
+  #define DDRDATA3CH0_CR_RCOMPDATA1_Spare2_MAX                         (0x00000001)
+
+#define DDRDATA3CH0_CR_TXXTALK_REG                                   (0x00000648)
+  #define DDRDATA3CH0_CR_TXXTALK_Lane0_OFF                             ( 0)
+  #define DDRDATA3CH0_CR_TXXTALK_Lane0_WID                             ( 4)
+  #define DDRDATA3CH0_CR_TXXTALK_Lane0_MSK                             (0x0000000F)
+  #define DDRDATA3CH0_CR_TXXTALK_Lane0_MAX                             (0x0000000F)
+  #define DDRDATA3CH0_CR_TXXTALK_Lane1_OFF                             ( 4)
+  #define DDRDATA3CH0_CR_TXXTALK_Lane1_WID                             ( 4)
+  #define DDRDATA3CH0_CR_TXXTALK_Lane1_MSK                             (0x000000F0)
+  #define DDRDATA3CH0_CR_TXXTALK_Lane1_MAX                             (0x0000000F)
+  #define DDRDATA3CH0_CR_TXXTALK_Lane2_OFF                             ( 8)
+  #define DDRDATA3CH0_CR_TXXTALK_Lane2_WID                             ( 4)
+  #define DDRDATA3CH0_CR_TXXTALK_Lane2_MSK                             (0x00000F00)
+  #define DDRDATA3CH0_CR_TXXTALK_Lane2_MAX                             (0x0000000F)
+  #define DDRDATA3CH0_CR_TXXTALK_Lane3_OFF                             (12)
+  #define DDRDATA3CH0_CR_TXXTALK_Lane3_WID                             ( 4)
+  #define DDRDATA3CH0_CR_TXXTALK_Lane3_MSK                             (0x0000F000)
+  #define DDRDATA3CH0_CR_TXXTALK_Lane3_MAX                             (0x0000000F)
+  #define DDRDATA3CH0_CR_TXXTALK_Lane4_OFF                             (16)
+  #define DDRDATA3CH0_CR_TXXTALK_Lane4_WID                             ( 4)
+  #define DDRDATA3CH0_CR_TXXTALK_Lane4_MSK                             (0x000F0000)
+  #define DDRDATA3CH0_CR_TXXTALK_Lane4_MAX                             (0x0000000F)
+  #define DDRDATA3CH0_CR_TXXTALK_Lane5_OFF                             (20)
+  #define DDRDATA3CH0_CR_TXXTALK_Lane5_WID                             ( 4)
+  #define DDRDATA3CH0_CR_TXXTALK_Lane5_MSK                             (0x00F00000)
+  #define DDRDATA3CH0_CR_TXXTALK_Lane5_MAX                             (0x0000000F)
+  #define DDRDATA3CH0_CR_TXXTALK_Lane6_OFF                             (24)
+  #define DDRDATA3CH0_CR_TXXTALK_Lane6_WID                             ( 4)
+  #define DDRDATA3CH0_CR_TXXTALK_Lane6_MSK                             (0x0F000000)
+  #define DDRDATA3CH0_CR_TXXTALK_Lane6_MAX                             (0x0000000F)
+  #define DDRDATA3CH0_CR_TXXTALK_Lane7_OFF                             (28)
+  #define DDRDATA3CH0_CR_TXXTALK_Lane7_WID                             ( 4)
+  #define DDRDATA3CH0_CR_TXXTALK_Lane7_MSK                             (0xF0000000)
+  #define DDRDATA3CH0_CR_TXXTALK_Lane7_MAX                             (0x0000000F)
+
+#define DDRDATA3CH0_CR_RXOFFSETVDQ_REG                               (0x0000064C)
+  #define DDRDATA3CH0_CR_RXOFFSETVDQ_Lane0_OFF                         ( 0)
+  #define DDRDATA3CH0_CR_RXOFFSETVDQ_Lane0_WID                         ( 4)
+  #define DDRDATA3CH0_CR_RXOFFSETVDQ_Lane0_MSK                         (0x0000000F)
+  #define DDRDATA3CH0_CR_RXOFFSETVDQ_Lane0_MAX                         (0x0000000F)
+  #define DDRDATA3CH0_CR_RXOFFSETVDQ_Lane1_OFF                         ( 4)
+  #define DDRDATA3CH0_CR_RXOFFSETVDQ_Lane1_WID                         ( 4)
+  #define DDRDATA3CH0_CR_RXOFFSETVDQ_Lane1_MSK                         (0x000000F0)
+  #define DDRDATA3CH0_CR_RXOFFSETVDQ_Lane1_MAX                         (0x0000000F)
+  #define DDRDATA3CH0_CR_RXOFFSETVDQ_Lane2_OFF                         ( 8)
+  #define DDRDATA3CH0_CR_RXOFFSETVDQ_Lane2_WID                         ( 4)
+  #define DDRDATA3CH0_CR_RXOFFSETVDQ_Lane2_MSK                         (0x00000F00)
+  #define DDRDATA3CH0_CR_RXOFFSETVDQ_Lane2_MAX                         (0x0000000F)
+  #define DDRDATA3CH0_CR_RXOFFSETVDQ_Lane3_OFF                         (12)
+  #define DDRDATA3CH0_CR_RXOFFSETVDQ_Lane3_WID                         ( 4)
+  #define DDRDATA3CH0_CR_RXOFFSETVDQ_Lane3_MSK                         (0x0000F000)
+  #define DDRDATA3CH0_CR_RXOFFSETVDQ_Lane3_MAX                         (0x0000000F)
+  #define DDRDATA3CH0_CR_RXOFFSETVDQ_Lane4_OFF                         (16)
+  #define DDRDATA3CH0_CR_RXOFFSETVDQ_Lane4_WID                         ( 4)
+  #define DDRDATA3CH0_CR_RXOFFSETVDQ_Lane4_MSK                         (0x000F0000)
+  #define DDRDATA3CH0_CR_RXOFFSETVDQ_Lane4_MAX                         (0x0000000F)
+  #define DDRDATA3CH0_CR_RXOFFSETVDQ_Lane5_OFF                         (20)
+  #define DDRDATA3CH0_CR_RXOFFSETVDQ_Lane5_WID                         ( 4)
+  #define DDRDATA3CH0_CR_RXOFFSETVDQ_Lane5_MSK                         (0x00F00000)
+  #define DDRDATA3CH0_CR_RXOFFSETVDQ_Lane5_MAX                         (0x0000000F)
+  #define DDRDATA3CH0_CR_RXOFFSETVDQ_Lane6_OFF                         (24)
+  #define DDRDATA3CH0_CR_RXOFFSETVDQ_Lane6_WID                         ( 4)
+  #define DDRDATA3CH0_CR_RXOFFSETVDQ_Lane6_MSK                         (0x0F000000)
+  #define DDRDATA3CH0_CR_RXOFFSETVDQ_Lane6_MAX                         (0x0000000F)
+  #define DDRDATA3CH0_CR_RXOFFSETVDQ_Lane7_OFF                         (28)
+  #define DDRDATA3CH0_CR_RXOFFSETVDQ_Lane7_WID                         ( 4)
+  #define DDRDATA3CH0_CR_RXOFFSETVDQ_Lane7_MSK                         (0xF0000000)
+  #define DDRDATA3CH0_CR_RXOFFSETVDQ_Lane7_MAX                         (0x0000000F)
+
+#define DDRDATA3CH0_CR_DDRDATARESERVED_REG                           (0x00000650)
+  #define DDRDATA3CH0_CR_DDRDATARESERVED_Spare_OFF                     ( 0)
+  #define DDRDATA3CH0_CR_DDRDATARESERVED_Spare_WID                     (32)
+  #define DDRDATA3CH0_CR_DDRDATARESERVED_Spare_MSK                     (0xFFFFFFFF)
+  #define DDRDATA3CH0_CR_DDRDATARESERVED_Spare_MAX                     (0xFFFFFFFF)
+
+#define DDRDATA3CH0_CR_DATATRAINFEEDBACK_REG                         (0x00000654)
+  #define DDRDATA3CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_OFF       ( 0)
+  #define DDRDATA3CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_WID       ( 9)
+  #define DDRDATA3CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_MSK       (0x000001FF)
+  #define DDRDATA3CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_MAX       (0x000001FF)
+  #define DDRDATA3CH0_CR_DATATRAINFEEDBACK_Spare_OFF                   ( 9)
+  #define DDRDATA3CH0_CR_DATATRAINFEEDBACK_Spare_WID                   (23)
+  #define DDRDATA3CH0_CR_DATATRAINFEEDBACK_Spare_MSK                   (0xFFFFFE00)
+  #define DDRDATA3CH0_CR_DATATRAINFEEDBACK_Spare_MAX                   (0x007FFFFF)
+
+#define DDRDATA3CH0_CR_DLLPITESTANDADC_REG                           (0x00000658)
+  #define DDRDATA3CH0_CR_DLLPITESTANDADC_RunTest_OFF                   ( 0)
+  #define DDRDATA3CH0_CR_DLLPITESTANDADC_RunTest_WID                   ( 1)
+  #define DDRDATA3CH0_CR_DLLPITESTANDADC_RunTest_MSK                   (0x00000001)
+  #define DDRDATA3CH0_CR_DLLPITESTANDADC_RunTest_MAX                   (0x00000001)
+  #define DDRDATA3CH0_CR_DLLPITESTANDADC_RunTest_DEF                   (0x00000000)
+  #define DDRDATA3CH0_CR_DLLPITESTANDADC_Load_OFF                      ( 1)
+  #define DDRDATA3CH0_CR_DLLPITESTANDADC_Load_WID                      ( 1)
+  #define DDRDATA3CH0_CR_DLLPITESTANDADC_Load_MSK                      (0x00000002)
+  #define DDRDATA3CH0_CR_DLLPITESTANDADC_Load_MAX                      (0x00000001)
+  #define DDRDATA3CH0_CR_DLLPITESTANDADC_Load_DEF                      (0x00000000)
+  #define DDRDATA3CH0_CR_DLLPITESTANDADC_ModeHVM_OFF                   ( 2)
+  #define DDRDATA3CH0_CR_DLLPITESTANDADC_ModeHVM_WID                   ( 1)
+  #define DDRDATA3CH0_CR_DLLPITESTANDADC_ModeHVM_MSK                   (0x00000004)
+  #define DDRDATA3CH0_CR_DLLPITESTANDADC_ModeHVM_MAX                   (0x00000001)
+  #define DDRDATA3CH0_CR_DLLPITESTANDADC_ModeHVM_DEF                   (0x00000000)
+  #define DDRDATA3CH0_CR_DLLPITESTANDADC_ModeDV_OFF                    ( 3)
+  #define DDRDATA3CH0_CR_DLLPITESTANDADC_ModeDV_WID                    ( 1)
+  #define DDRDATA3CH0_CR_DLLPITESTANDADC_ModeDV_MSK                    (0x00000008)
+  #define DDRDATA3CH0_CR_DLLPITESTANDADC_ModeDV_MAX                    (0x00000001)
+  #define DDRDATA3CH0_CR_DLLPITESTANDADC_ModeDV_DEF                    (0x00000000)
+  #define DDRDATA3CH0_CR_DLLPITESTANDADC_ModeADC_OFF                   ( 4)
+  #define DDRDATA3CH0_CR_DLLPITESTANDADC_ModeADC_WID                   ( 1)
+  #define DDRDATA3CH0_CR_DLLPITESTANDADC_ModeADC_MSK                   (0x00000010)
+  #define DDRDATA3CH0_CR_DLLPITESTANDADC_ModeADC_MAX                   (0x00000001)
+  #define DDRDATA3CH0_CR_DLLPITESTANDADC_ModeADC_DEF                   (0x00000000)
+  #define DDRDATA3CH0_CR_DLLPITESTANDADC_LoadCount_OFF                 ( 5)
+  #define DDRDATA3CH0_CR_DLLPITESTANDADC_LoadCount_WID                 (10)
+  #define DDRDATA3CH0_CR_DLLPITESTANDADC_LoadCount_MSK                 (0x00007FE0)
+  #define DDRDATA3CH0_CR_DLLPITESTANDADC_LoadCount_MAX                 (0x000003FF)
+  #define DDRDATA3CH0_CR_DLLPITESTANDADC_CountStatus_OFF               (15)
+  #define DDRDATA3CH0_CR_DLLPITESTANDADC_CountStatus_WID               (10)
+  #define DDRDATA3CH0_CR_DLLPITESTANDADC_CountStatus_MSK               (0x01FF8000)
+  #define DDRDATA3CH0_CR_DLLPITESTANDADC_CountStatus_MAX               (0x000003FF)
+  #define DDRDATA3CH0_CR_DLLPITESTANDADC_CountStatus_DEF               (0x00000000)
+  #define DDRDATA3CH0_CR_DLLPITESTANDADC_Spare_OFF                     (25)
+  #define DDRDATA3CH0_CR_DLLPITESTANDADC_Spare_WID                     ( 7)
+  #define DDRDATA3CH0_CR_DLLPITESTANDADC_Spare_MSK                     (0xFE000000)
+  #define DDRDATA3CH0_CR_DLLPITESTANDADC_Spare_MAX                     (0x0000007F)
+
+#define DDRDATA3CH0_CR_DDRCRDATAOFFSETCOMP_REG                       (0x0000065C)
+  #define DDRDATA3CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_OFF     ( 0)
+  #define DDRDATA3CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_WID     ( 6)
+  #define DDRDATA3CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MSK     (0x0000003F)
+  #define DDRDATA3CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MAX     (0x0000003F)
+  #define DDRDATA3CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_DEF     (0x00000000)
+  #define DDRDATA3CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_OFF   ( 6)
+  #define DDRDATA3CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_WID   ( 6)
+  #define DDRDATA3CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MSK   (0x00000FC0)
+  #define DDRDATA3CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MAX   (0x0000003F)
+  #define DDRDATA3CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_DEF   (0x00000000)
+  #define DDRDATA3CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_OFF     (12)
+  #define DDRDATA3CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_WID     ( 5)
+  #define DDRDATA3CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MSK     (0x0001F000)
+  #define DDRDATA3CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MAX     (0x0000001F)
+  #define DDRDATA3CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_DEF     (0x00000000)
+  #define DDRDATA3CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_OFF   (17)
+  #define DDRDATA3CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_WID   ( 5)
+  #define DDRDATA3CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MSK   (0x003E0000)
+  #define DDRDATA3CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MAX   (0x0000001F)
+  #define DDRDATA3CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_DEF   (0x00000000)
+  #define DDRDATA3CH0_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_OFF       (22)
+  #define DDRDATA3CH0_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_WID       ( 5)
+  #define DDRDATA3CH0_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_MSK       (0x07C00000)
+  #define DDRDATA3CH0_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_MAX       (0x0000001F)
+  #define DDRDATA3CH0_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_DEF       (0x00000000)
+  #define DDRDATA3CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_OFF  (27)
+  #define DDRDATA3CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_WID  ( 5)
+  #define DDRDATA3CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MSK  (0xF8000000)
+  #define DDRDATA3CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MAX  (0x0000001F)
+  #define DDRDATA3CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_DEF  (0x00000000)
+
+#define DDRDATA3CH0_CR_DDRCRDATACONTROL1_REG                         (0x00000660)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_RefPi_OFF                   ( 0)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_RefPi_WID                   ( 4)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_RefPi_MSK                   (0x0000000F)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_RefPi_MAX                   (0x0000000F)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_RefPi_DEF                   (0x00000000)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_DllMask_OFF                 ( 4)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_DllMask_WID                 ( 2)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_DllMask_MSK                 (0x00000030)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_DllMask_MAX                 (0x00000003)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_DllMask_DEF                 (0x00000000)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_DllWeakLock_OFF             ( 6)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_DllWeakLock_WID             ( 1)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_DllWeakLock_MSK             (0x00000040)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_DllWeakLock_MAX             (0x00000001)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_DllWeakLock_DEF             (0x00000000)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_OFF      ( 7)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_WID      ( 3)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MSK      (0x00000380)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MAX      (0x00000007)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_DEF      (0x00000000)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_OFF               (10)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_WID               ( 3)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_MSK               (0x00001C00)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_MAX               (0x00000007)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_DEF               (0x00000000)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_OdtDelay_OFF                (13)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_OdtDelay_WID                ( 4)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_OdtDelay_MSK                (0x0001E000)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_OdtDelay_MAX                (0x0000000F)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_OdtDelay_DEF                (0x00000000)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_OdtDuration_OFF             (17)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_OdtDuration_WID             ( 3)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_OdtDuration_MSK             (0x000E0000)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_OdtDuration_MAX             (0x00000007)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_OdtDuration_DEF             (0x00000000)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_OFF           (20)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_WID           ( 4)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_MSK           (0x00F00000)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_MAX           (0x0000000F)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_DEF           (0x00000000)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_OFF        (24)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_WID        ( 3)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_MSK        (0x07000000)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_MAX        (0x00000007)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_DEF        (0x00000000)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_BurstEndODTDelay_OFF        (27)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_BurstEndODTDelay_WID        ( 3)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_BurstEndODTDelay_MSK        (0x38000000)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_BurstEndODTDelay_MAX        (0x00000007)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_BurstEndODTDelay_DEF        (0x00000000)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_OFF          (30)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_WID          ( 1)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_MSK          (0x40000000)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_MAX          (0x00000001)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_DEF          (0x00000000)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_Rsvd1_OFF                   (31)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_Rsvd1_WID                   ( 1)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_Rsvd1_MSK                   (0x80000000)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_Rsvd1_MAX                   (0x00000001)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_Rsvd1_DEF                   (0x00000000)
+
+#define DDRDATA3CH0_CR_DDRCRDATACONTROL2_REG                         (0x00000664)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_OFF            ( 0)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_WID            ( 5)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_MSK            (0x0000001F)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_MAX            (0x0000001F)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_DEF            (0x00000000)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_OFF             ( 5)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_WID             ( 1)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_MSK             (0x00000020)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_MAX             (0x00000001)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_DEF             (0x00000000)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_ForceRxOn_OFF               ( 6)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_ForceRxOn_WID               ( 1)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_ForceRxOn_MSK               (0x00000040)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_ForceRxOn_MAX               (0x00000001)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_ForceRxOn_DEF               (0x00000000)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_LeakerComp_OFF              ( 7)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_LeakerComp_WID              ( 2)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_LeakerComp_MSK              (0x00000180)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_LeakerComp_MAX              (0x00000003)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_LeakerComp_DEF              (0x00000000)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_OFF          ( 9)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_WID          ( 4)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_MSK          (0x00001E00)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_MAX          (0x0000000F)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_DEF          (0x00000008)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_OFF             (13)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_WID             ( 5)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_MSK             (0x0003E000)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_MAX             (0x0000001F)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_DEF             (0x00000011)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_OFF             (18)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_WID             ( 1)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_MSK             (0x00040000)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_MAX             (0x00000001)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_DEF             (0x00000000)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_Spare_OFF                   (19)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_Spare_WID                   (13)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_Spare_MSK                   (0xFFF80000)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_Spare_MAX                   (0x00001FFF)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_Spare_DEF                   (0x00000000)
+
+#define DDRDATA3CH0_CR_DDRCRVSSHIORVREFCONTROL_REG                   (0x0000066C)
+  #define DDRDATA3CH0_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_OFF    ( 0)
+  #define DDRDATA3CH0_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_WID    (24)
+  #define DDRDATA3CH0_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_MSK    (0x00FFFFFF)
+  #define DDRDATA3CH0_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_MAX    (0x00FFFFFF)
+  #define DDRDATA3CH0_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_DEF    (0x00000000)
+  #define DDRDATA3CH0_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_OFF        (24)
+  #define DDRDATA3CH0_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_WID        ( 8)
+  #define DDRDATA3CH0_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_MSK        (0xFF000000)
+  #define DDRDATA3CH0_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_MAX        (0x000000FF)
+  #define DDRDATA3CH0_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_DEF        (0x00000000)
+
+#define DDRDATA3CH0_CR_DDRCRDATAOFFSETTRAIN_REG                      (0x00000670)
+  #define DDRDATA3CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_OFF          ( 0)
+  #define DDRDATA3CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_WID          ( 6)
+  #define DDRDATA3CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MSK          (0x0000003F)
+  #define DDRDATA3CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MAX          (0x0000003F)
+  #define DDRDATA3CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_DEF          (0x00000000)
+  #define DDRDATA3CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_OFF          ( 6)
+  #define DDRDATA3CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_WID          ( 6)
+  #define DDRDATA3CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MSK          (0x00000FC0)
+  #define DDRDATA3CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MAX          (0x0000003F)
+  #define DDRDATA3CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_DEF          (0x00000000)
+  #define DDRDATA3CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_OFF           (12)
+  #define DDRDATA3CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_WID           ( 6)
+  #define DDRDATA3CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MSK           (0x0003F000)
+  #define DDRDATA3CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MAX           (0x0000003F)
+  #define DDRDATA3CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_DEF           (0x00000000)
+  #define DDRDATA3CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_OFF          (18)
+  #define DDRDATA3CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_WID          ( 6)
+  #define DDRDATA3CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MSK          (0x00FC0000)
+  #define DDRDATA3CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MAX          (0x0000003F)
+  #define DDRDATA3CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_DEF          (0x00000000)
+  #define DDRDATA3CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_OFF           (24)
+  #define DDRDATA3CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_WID           ( 7)
+  #define DDRDATA3CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MSK           (0x7F000000)
+  #define DDRDATA3CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MAX           (0x0000007F)
+  #define DDRDATA3CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_DEF           (0x00000000)
+  #define DDRDATA3CH0_CR_DDRCRDATAOFFSETTRAIN_Spare_OFF                (31)
+  #define DDRDATA3CH0_CR_DDRCRDATAOFFSETTRAIN_Spare_WID                ( 1)
+  #define DDRDATA3CH0_CR_DDRCRDATAOFFSETTRAIN_Spare_MSK                (0x80000000)
+  #define DDRDATA3CH0_CR_DDRCRDATAOFFSETTRAIN_Spare_MAX                (0x00000001)
+  #define DDRDATA3CH0_CR_DDRCRDATAOFFSETTRAIN_Spare_DEF                (0x00000000)
+
+#define DDRDATA3CH0_CR_DDRCRDATACONTROL0_REG                         (0x00000674)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_OFF          ( 0)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_WID          ( 1)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_MSK          (0x00000001)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_MAX          (0x00000001)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_DEF          (0x00000000)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_OFF          ( 1)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_WID          ( 1)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_MSK          (0x00000002)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_MAX          (0x00000001)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_DEF          (0x00000000)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_OFF          ( 2)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_WID          ( 1)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_MSK          (0x00000004)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_MAX          (0x00000001)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_DEF          (0x00000000)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_OFF    ( 3)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_WID    ( 1)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MSK    (0x00000008)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MAX    (0x00000001)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_DEF    (0x00000000)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_TxOn_OFF                    ( 4)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_TxOn_WID                    ( 1)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_TxOn_MSK                    (0x00000010)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_TxOn_MAX                    (0x00000001)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_TxOn_DEF                    (0x00000000)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RfOn_OFF                    ( 5)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RfOn_WID                    ( 1)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RfOn_MSK                    (0x00000020)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RfOn_MAX                    (0x00000001)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RfOn_DEF                    (0x00000000)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RxPiOn_OFF                  ( 6)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RxPiOn_WID                  ( 1)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RxPiOn_MSK                  (0x00000040)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RxPiOn_MAX                  (0x00000001)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RxPiOn_DEF                  (0x00000000)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_TxPiOn_OFF                  ( 7)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_TxPiOn_WID                  ( 1)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_TxPiOn_MSK                  (0x00000080)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_TxPiOn_MAX                  (0x00000001)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_TxPiOn_DEF                  (0x00000000)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_OFF        ( 8)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_WID        ( 1)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_MSK        (0x00000100)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_MAX        (0x00000001)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_DEF        (0x00000000)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_OFF        ( 9)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_WID        ( 1)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MSK        (0x00000200)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MAX        (0x00000001)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_DEF        (0x00000000)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_TxDisable_OFF               (10)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_TxDisable_WID               ( 1)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_TxDisable_MSK               (0x00000400)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_TxDisable_MAX               (0x00000001)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_TxDisable_DEF               (0x00000000)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RxDisable_OFF               (11)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RxDisable_WID               ( 1)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RxDisable_MSK               (0x00000800)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RxDisable_MAX               (0x00000001)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RxDisable_DEF               (0x00000000)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_TxLong_OFF                  (12)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_TxLong_WID                  ( 1)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_TxLong_MSK                  (0x00001000)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_TxLong_MAX                  (0x00000001)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_TxLong_DEF                  (0x00000000)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_OFF               (13)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_WID               ( 2)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_MSK               (0x00006000)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_MAX               (0x00000003)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_DEF               (0x00000000)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RxReadPointer_OFF           (15)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RxReadPointer_WID           ( 3)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RxReadPointer_MSK           (0x00038000)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RxReadPointer_MAX           (0x00000007)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RxReadPointer_DEF           (0x00000000)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_DriverSegmentEnable_OFF     (18)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_DriverSegmentEnable_WID     ( 1)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_DriverSegmentEnable_MSK     (0x00040000)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_DriverSegmentEnable_MAX     (0x00000001)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_DriverSegmentEnable_DEF     (0x00000000)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_DataVccddqHi_OFF            (19)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_DataVccddqHi_WID            ( 1)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_DataVccddqHi_MSK            (0x00080000)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_DataVccddqHi_MAX            (0x00000001)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_DataVccddqHi_DEF            (0x00000000)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_ReadRFRd_OFF                (20)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_ReadRFRd_WID                ( 1)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_ReadRFRd_MSK                (0x00100000)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_ReadRFRd_MAX                (0x00000001)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_ReadRFRd_DEF                (0x00000000)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_ReadRFWr_OFF                (21)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_ReadRFWr_WID                ( 1)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_ReadRFWr_MSK                (0x00200000)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_ReadRFWr_MAX                (0x00000001)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_ReadRFWr_DEF                (0x00000000)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_ReadRFRank_OFF              (22)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_ReadRFRank_WID              ( 2)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_ReadRFRank_MSK              (0x00C00000)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_ReadRFRank_MAX              (0x00000003)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_ReadRFRank_DEF              (0x00000000)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_OFF              (24)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_WID              ( 1)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_MSK              (0x01000000)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_MAX              (0x00000001)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_DEF              (0x00000000)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_OdtSampOff_OFF              (25)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_OdtSampOff_WID              ( 1)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_OdtSampOff_MSK              (0x02000000)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_OdtSampOff_MAX              (0x00000001)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_OdtSampOff_DEF              (0x00000000)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_OFF        (26)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_WID        ( 1)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_MSK        (0x04000000)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_MAX        (0x00000001)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_DEF        (0x00000000)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_OFF         (27)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_WID         ( 1)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MSK         (0x08000000)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MAX         (0x00000001)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_DEF         (0x00000000)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_OFF              (28)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_WID              ( 1)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_MSK              (0x10000000)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_MAX              (0x00000001)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_DEF              (0x00000000)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_EnReadPreamble_OFF          (29)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_EnReadPreamble_WID          ( 1)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_EnReadPreamble_MSK          (0x20000000)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_EnReadPreamble_MAX          (0x00000001)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_EnReadPreamble_DEF          (0x00000000)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_OFF         (30)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_WID         ( 1)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MSK         (0x40000000)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MAX         (0x00000001)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_DEF         (0x00000000)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_OFF            (31)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_WID            ( 1)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_MSK            (0x80000000)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_MAX            (0x00000001)
+  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_DEF            (0x00000000)
+
+#define DDRDATA3CH0_CR_DDRCRVREFADJUST1_REG                          (0x00000678)
+  #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_CAVrefCtl_OFF                ( 0)
+  #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_CAVrefCtl_WID                ( 7)
+  #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_CAVrefCtl_MSK                (0x0000007F)
+  #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_CAVrefCtl_MAX                (0x0000007F)
+  #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_CAVrefCtl_DEF                (0x00000000)
+  #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_Ch1VrefCtl_OFF               ( 7)
+  #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_Ch1VrefCtl_WID               ( 7)
+  #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_Ch1VrefCtl_MSK               (0x00003F80)
+  #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_Ch1VrefCtl_MAX               (0x0000007F)
+  #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_Ch1VrefCtl_DEF               (0x00000000)
+  #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_Ch0VrefCtl_OFF               (14)
+  #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_Ch0VrefCtl_WID               ( 7)
+  #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_Ch0VrefCtl_MSK               (0x001FC000)
+  #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_Ch0VrefCtl_MAX               (0x0000007F)
+  #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_Ch0VrefCtl_DEF               (0x00000000)
+  #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCA_OFF             (21)
+  #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCA_WID             ( 1)
+  #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCA_MSK             (0x00200000)
+  #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCA_MAX             (0x00000001)
+  #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCA_DEF             (0x00000000)
+  #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_OFF            (22)
+  #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_WID            ( 1)
+  #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_MSK            (0x00400000)
+  #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_MAX            (0x00000001)
+  #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_DEF            (0x00000000)
+  #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_OFF            (23)
+  #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_WID            ( 1)
+  #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_MSK            (0x00800000)
+  #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_MAX            (0x00000001)
+  #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_DEF            (0x00000000)
+  #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_HiZTimerCtrl_OFF             (24)
+  #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_HiZTimerCtrl_WID             ( 2)
+  #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_HiZTimerCtrl_MSK             (0x03000000)
+  #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_HiZTimerCtrl_MAX             (0x00000003)
+  #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_HiZTimerCtrl_DEF             (0x00000000)
+  #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_OFF            (26)
+  #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_WID            ( 1)
+  #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_MSK            (0x04000000)
+  #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_MAX            (0x00000001)
+  #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_DEF            (0x00000000)
+  #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_Rsvd_OFF                     (27)
+  #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_Rsvd_WID                     ( 2)
+  #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_Rsvd_MSK                     (0x18000000)
+  #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_Rsvd_MAX                     (0x00000003)
+  #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_Rsvd_DEF                     (0x00000000)
+  #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_caSlowBW_OFF                 (29)
+  #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_caSlowBW_WID                 ( 1)
+  #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_caSlowBW_MSK                 (0x20000000)
+  #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_caSlowBW_MAX                 (0x00000001)
+  #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_caSlowBW_DEF                 (0x00000000)
+  #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_ch0SlowBW_OFF                (30)
+  #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_ch0SlowBW_WID                ( 1)
+  #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_ch0SlowBW_MSK                (0x40000000)
+  #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_ch0SlowBW_MAX                (0x00000001)
+  #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_ch0SlowBW_DEF                (0x00000000)
+  #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_ch1SlowBW_OFF                (31)
+  #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_ch1SlowBW_WID                ( 1)
+  #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_ch1SlowBW_MSK                (0x80000000)
+  #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_ch1SlowBW_MAX                (0x00000001)
+  #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_ch1SlowBW_DEF                (0x00000000)
+
+#define DDRDATA3CH1_CR_RXTRAINRANK0_REG                              (0x00000700)
+  #define DDRDATA3CH1_CR_RXTRAINRANK0_RxRcvEnPi_OFF                    ( 0)
+  #define DDRDATA3CH1_CR_RXTRAINRANK0_RxRcvEnPi_WID                    ( 9)
+  #define DDRDATA3CH1_CR_RXTRAINRANK0_RxRcvEnPi_MSK                    (0x000001FF)
+  #define DDRDATA3CH1_CR_RXTRAINRANK0_RxRcvEnPi_MAX                    (0x000001FF)
+  #define DDRDATA3CH1_CR_RXTRAINRANK0_RxDqsPPi_OFF                     ( 9)
+  #define DDRDATA3CH1_CR_RXTRAINRANK0_RxDqsPPi_WID                     ( 6)
+  #define DDRDATA3CH1_CR_RXTRAINRANK0_RxDqsPPi_MSK                     (0x00007E00)
+  #define DDRDATA3CH1_CR_RXTRAINRANK0_RxDqsPPi_MAX                     (0x0000003F)
+  #define DDRDATA3CH1_CR_RXTRAINRANK0_RxEq_OFF                         (15)
+  #define DDRDATA3CH1_CR_RXTRAINRANK0_RxEq_WID                         ( 5)
+  #define DDRDATA3CH1_CR_RXTRAINRANK0_RxEq_MSK                         (0x000F8000)
+  #define DDRDATA3CH1_CR_RXTRAINRANK0_RxEq_MAX                         (0x0000001F)
+  #define DDRDATA3CH1_CR_RXTRAINRANK0_RxDqsNPi_OFF                     (20)
+  #define DDRDATA3CH1_CR_RXTRAINRANK0_RxDqsNPi_WID                     ( 6)
+  #define DDRDATA3CH1_CR_RXTRAINRANK0_RxDqsNPi_MSK                     (0x03F00000)
+  #define DDRDATA3CH1_CR_RXTRAINRANK0_RxDqsNPi_MAX                     (0x0000003F)
+  #define DDRDATA3CH1_CR_RXTRAINRANK0_RxVref_OFF                       (26)
+  #define DDRDATA3CH1_CR_RXTRAINRANK0_RxVref_WID                       ( 6)
+  #define DDRDATA3CH1_CR_RXTRAINRANK0_RxVref_MSK                       (0xFC000000)
+  #define DDRDATA3CH1_CR_RXTRAINRANK0_RxVref_MAX                       (0x0000003F)
+
+#define DDRDATA3CH1_CR_RXTRAINRANK1_REG                              (0x00000704)
+  #define DDRDATA3CH1_CR_RXTRAINRANK1_RxRcvEnPi_OFF                    ( 0)
+  #define DDRDATA3CH1_CR_RXTRAINRANK1_RxRcvEnPi_WID                    ( 9)
+  #define DDRDATA3CH1_CR_RXTRAINRANK1_RxRcvEnPi_MSK                    (0x000001FF)
+  #define DDRDATA3CH1_CR_RXTRAINRANK1_RxRcvEnPi_MAX                    (0x000001FF)
+  #define DDRDATA3CH1_CR_RXTRAINRANK1_RxDqsPPi_OFF                     ( 9)
+  #define DDRDATA3CH1_CR_RXTRAINRANK1_RxDqsPPi_WID                     ( 6)
+  #define DDRDATA3CH1_CR_RXTRAINRANK1_RxDqsPPi_MSK                     (0x00007E00)
+  #define DDRDATA3CH1_CR_RXTRAINRANK1_RxDqsPPi_MAX                     (0x0000003F)
+  #define DDRDATA3CH1_CR_RXTRAINRANK1_RxEq_OFF                         (15)
+  #define DDRDATA3CH1_CR_RXTRAINRANK1_RxEq_WID                         ( 5)
+  #define DDRDATA3CH1_CR_RXTRAINRANK1_RxEq_MSK                         (0x000F8000)
+  #define DDRDATA3CH1_CR_RXTRAINRANK1_RxEq_MAX                         (0x0000001F)
+  #define DDRDATA3CH1_CR_RXTRAINRANK1_RxDqsNPi_OFF                     (20)
+  #define DDRDATA3CH1_CR_RXTRAINRANK1_RxDqsNPi_WID                     ( 6)
+  #define DDRDATA3CH1_CR_RXTRAINRANK1_RxDqsNPi_MSK                     (0x03F00000)
+  #define DDRDATA3CH1_CR_RXTRAINRANK1_RxDqsNPi_MAX                     (0x0000003F)
+  #define DDRDATA3CH1_CR_RXTRAINRANK1_RxVref_OFF                       (26)
+  #define DDRDATA3CH1_CR_RXTRAINRANK1_RxVref_WID                       ( 6)
+  #define DDRDATA3CH1_CR_RXTRAINRANK1_RxVref_MSK                       (0xFC000000)
+  #define DDRDATA3CH1_CR_RXTRAINRANK1_RxVref_MAX                       (0x0000003F)
+
+#define DDRDATA3CH1_CR_RXTRAINRANK2_REG                              (0x00000708)
+  #define DDRDATA3CH1_CR_RXTRAINRANK2_RxRcvEnPi_OFF                    ( 0)
+  #define DDRDATA3CH1_CR_RXTRAINRANK2_RxRcvEnPi_WID                    ( 9)
+  #define DDRDATA3CH1_CR_RXTRAINRANK2_RxRcvEnPi_MSK                    (0x000001FF)
+  #define DDRDATA3CH1_CR_RXTRAINRANK2_RxRcvEnPi_MAX                    (0x000001FF)
+  #define DDRDATA3CH1_CR_RXTRAINRANK2_RxDqsPPi_OFF                     ( 9)
+  #define DDRDATA3CH1_CR_RXTRAINRANK2_RxDqsPPi_WID                     ( 6)
+  #define DDRDATA3CH1_CR_RXTRAINRANK2_RxDqsPPi_MSK                     (0x00007E00)
+  #define DDRDATA3CH1_CR_RXTRAINRANK2_RxDqsPPi_MAX                     (0x0000003F)
+  #define DDRDATA3CH1_CR_RXTRAINRANK2_RxEq_OFF                         (15)
+  #define DDRDATA3CH1_CR_RXTRAINRANK2_RxEq_WID                         ( 5)
+  #define DDRDATA3CH1_CR_RXTRAINRANK2_RxEq_MSK                         (0x000F8000)
+  #define DDRDATA3CH1_CR_RXTRAINRANK2_RxEq_MAX                         (0x0000001F)
+  #define DDRDATA3CH1_CR_RXTRAINRANK2_RxDqsNPi_OFF                     (20)
+  #define DDRDATA3CH1_CR_RXTRAINRANK2_RxDqsNPi_WID                     ( 6)
+  #define DDRDATA3CH1_CR_RXTRAINRANK2_RxDqsNPi_MSK                     (0x03F00000)
+  #define DDRDATA3CH1_CR_RXTRAINRANK2_RxDqsNPi_MAX                     (0x0000003F)
+  #define DDRDATA3CH1_CR_RXTRAINRANK2_RxVref_OFF                       (26)
+  #define DDRDATA3CH1_CR_RXTRAINRANK2_RxVref_WID                       ( 6)
+  #define DDRDATA3CH1_CR_RXTRAINRANK2_RxVref_MSK                       (0xFC000000)
+  #define DDRDATA3CH1_CR_RXTRAINRANK2_RxVref_MAX                       (0x0000003F)
+
+#define DDRDATA3CH1_CR_RXTRAINRANK3_REG                              (0x0000070C)
+  #define DDRDATA3CH1_CR_RXTRAINRANK3_RxRcvEnPi_OFF                    ( 0)
+  #define DDRDATA3CH1_CR_RXTRAINRANK3_RxRcvEnPi_WID                    ( 9)
+  #define DDRDATA3CH1_CR_RXTRAINRANK3_RxRcvEnPi_MSK                    (0x000001FF)
+  #define DDRDATA3CH1_CR_RXTRAINRANK3_RxRcvEnPi_MAX                    (0x000001FF)
+  #define DDRDATA3CH1_CR_RXTRAINRANK3_RxDqsPPi_OFF                     ( 9)
+  #define DDRDATA3CH1_CR_RXTRAINRANK3_RxDqsPPi_WID                     ( 6)
+  #define DDRDATA3CH1_CR_RXTRAINRANK3_RxDqsPPi_MSK                     (0x00007E00)
+  #define DDRDATA3CH1_CR_RXTRAINRANK3_RxDqsPPi_MAX                     (0x0000003F)
+  #define DDRDATA3CH1_CR_RXTRAINRANK3_RxEq_OFF                         (15)
+  #define DDRDATA3CH1_CR_RXTRAINRANK3_RxEq_WID                         ( 5)
+  #define DDRDATA3CH1_CR_RXTRAINRANK3_RxEq_MSK                         (0x000F8000)
+  #define DDRDATA3CH1_CR_RXTRAINRANK3_RxEq_MAX                         (0x0000001F)
+  #define DDRDATA3CH1_CR_RXTRAINRANK3_RxDqsNPi_OFF                     (20)
+  #define DDRDATA3CH1_CR_RXTRAINRANK3_RxDqsNPi_WID                     ( 6)
+  #define DDRDATA3CH1_CR_RXTRAINRANK3_RxDqsNPi_MSK                     (0x03F00000)
+  #define DDRDATA3CH1_CR_RXTRAINRANK3_RxDqsNPi_MAX                     (0x0000003F)
+  #define DDRDATA3CH1_CR_RXTRAINRANK3_RxVref_OFF                       (26)
+  #define DDRDATA3CH1_CR_RXTRAINRANK3_RxVref_WID                       ( 6)
+  #define DDRDATA3CH1_CR_RXTRAINRANK3_RxVref_MSK                       (0xFC000000)
+  #define DDRDATA3CH1_CR_RXTRAINRANK3_RxVref_MAX                       (0x0000003F)
+
+#define DDRDATA3CH1_CR_RXPERBITRANK0_REG                             (0x00000710)
+  #define DDRDATA3CH1_CR_RXPERBITRANK0_Lane0_OFF                       ( 0)
+  #define DDRDATA3CH1_CR_RXPERBITRANK0_Lane0_WID                       ( 4)
+  #define DDRDATA3CH1_CR_RXPERBITRANK0_Lane0_MSK                       (0x0000000F)
+  #define DDRDATA3CH1_CR_RXPERBITRANK0_Lane0_MAX                       (0x0000000F)
+  #define DDRDATA3CH1_CR_RXPERBITRANK0_Lane1_OFF                       ( 4)
+  #define DDRDATA3CH1_CR_RXPERBITRANK0_Lane1_WID                       ( 4)
+  #define DDRDATA3CH1_CR_RXPERBITRANK0_Lane1_MSK                       (0x000000F0)
+  #define DDRDATA3CH1_CR_RXPERBITRANK0_Lane1_MAX                       (0x0000000F)
+  #define DDRDATA3CH1_CR_RXPERBITRANK0_Lane2_OFF                       ( 8)
+  #define DDRDATA3CH1_CR_RXPERBITRANK0_Lane2_WID                       ( 4)
+  #define DDRDATA3CH1_CR_RXPERBITRANK0_Lane2_MSK                       (0x00000F00)
+  #define DDRDATA3CH1_CR_RXPERBITRANK0_Lane2_MAX                       (0x0000000F)
+  #define DDRDATA3CH1_CR_RXPERBITRANK0_Lane3_OFF                       (12)
+  #define DDRDATA3CH1_CR_RXPERBITRANK0_Lane3_WID                       ( 4)
+  #define DDRDATA3CH1_CR_RXPERBITRANK0_Lane3_MSK                       (0x0000F000)
+  #define DDRDATA3CH1_CR_RXPERBITRANK0_Lane3_MAX                       (0x0000000F)
+  #define DDRDATA3CH1_CR_RXPERBITRANK0_Lane4_OFF                       (16)
+  #define DDRDATA3CH1_CR_RXPERBITRANK0_Lane4_WID                       ( 4)
+  #define DDRDATA3CH1_CR_RXPERBITRANK0_Lane4_MSK                       (0x000F0000)
+  #define DDRDATA3CH1_CR_RXPERBITRANK0_Lane4_MAX                       (0x0000000F)
+  #define DDRDATA3CH1_CR_RXPERBITRANK0_Lane5_OFF                       (20)
+  #define DDRDATA3CH1_CR_RXPERBITRANK0_Lane5_WID                       ( 4)
+  #define DDRDATA3CH1_CR_RXPERBITRANK0_Lane5_MSK                       (0x00F00000)
+  #define DDRDATA3CH1_CR_RXPERBITRANK0_Lane5_MAX                       (0x0000000F)
+  #define DDRDATA3CH1_CR_RXPERBITRANK0_Lane6_OFF                       (24)
+  #define DDRDATA3CH1_CR_RXPERBITRANK0_Lane6_WID                       ( 4)
+  #define DDRDATA3CH1_CR_RXPERBITRANK0_Lane6_MSK                       (0x0F000000)
+  #define DDRDATA3CH1_CR_RXPERBITRANK0_Lane6_MAX                       (0x0000000F)
+  #define DDRDATA3CH1_CR_RXPERBITRANK0_Lane7_OFF                       (28)
+  #define DDRDATA3CH1_CR_RXPERBITRANK0_Lane7_WID                       ( 4)
+  #define DDRDATA3CH1_CR_RXPERBITRANK0_Lane7_MSK                       (0xF0000000)
+  #define DDRDATA3CH1_CR_RXPERBITRANK0_Lane7_MAX                       (0x0000000F)
+
+#define DDRDATA3CH1_CR_RXPERBITRANK1_REG                             (0x00000714)
+  #define DDRDATA3CH1_CR_RXPERBITRANK1_Lane0_OFF                       ( 0)
+  #define DDRDATA3CH1_CR_RXPERBITRANK1_Lane0_WID                       ( 4)
+  #define DDRDATA3CH1_CR_RXPERBITRANK1_Lane0_MSK                       (0x0000000F)
+  #define DDRDATA3CH1_CR_RXPERBITRANK1_Lane0_MAX                       (0x0000000F)
+  #define DDRDATA3CH1_CR_RXPERBITRANK1_Lane1_OFF                       ( 4)
+  #define DDRDATA3CH1_CR_RXPERBITRANK1_Lane1_WID                       ( 4)
+  #define DDRDATA3CH1_CR_RXPERBITRANK1_Lane1_MSK                       (0x000000F0)
+  #define DDRDATA3CH1_CR_RXPERBITRANK1_Lane1_MAX                       (0x0000000F)
+  #define DDRDATA3CH1_CR_RXPERBITRANK1_Lane2_OFF                       ( 8)
+  #define DDRDATA3CH1_CR_RXPERBITRANK1_Lane2_WID                       ( 4)
+  #define DDRDATA3CH1_CR_RXPERBITRANK1_Lane2_MSK                       (0x00000F00)
+  #define DDRDATA3CH1_CR_RXPERBITRANK1_Lane2_MAX                       (0x0000000F)
+  #define DDRDATA3CH1_CR_RXPERBITRANK1_Lane3_OFF                       (12)
+  #define DDRDATA3CH1_CR_RXPERBITRANK1_Lane3_WID                       ( 4)
+  #define DDRDATA3CH1_CR_RXPERBITRANK1_Lane3_MSK                       (0x0000F000)
+  #define DDRDATA3CH1_CR_RXPERBITRANK1_Lane3_MAX                       (0x0000000F)
+  #define DDRDATA3CH1_CR_RXPERBITRANK1_Lane4_OFF                       (16)
+  #define DDRDATA3CH1_CR_RXPERBITRANK1_Lane4_WID                       ( 4)
+  #define DDRDATA3CH1_CR_RXPERBITRANK1_Lane4_MSK                       (0x000F0000)
+  #define DDRDATA3CH1_CR_RXPERBITRANK1_Lane4_MAX                       (0x0000000F)
+  #define DDRDATA3CH1_CR_RXPERBITRANK1_Lane5_OFF                       (20)
+  #define DDRDATA3CH1_CR_RXPERBITRANK1_Lane5_WID                       ( 4)
+  #define DDRDATA3CH1_CR_RXPERBITRANK1_Lane5_MSK                       (0x00F00000)
+  #define DDRDATA3CH1_CR_RXPERBITRANK1_Lane5_MAX                       (0x0000000F)
+  #define DDRDATA3CH1_CR_RXPERBITRANK1_Lane6_OFF                       (24)
+  #define DDRDATA3CH1_CR_RXPERBITRANK1_Lane6_WID                       ( 4)
+  #define DDRDATA3CH1_CR_RXPERBITRANK1_Lane6_MSK                       (0x0F000000)
+  #define DDRDATA3CH1_CR_RXPERBITRANK1_Lane6_MAX                       (0x0000000F)
+  #define DDRDATA3CH1_CR_RXPERBITRANK1_Lane7_OFF                       (28)
+  #define DDRDATA3CH1_CR_RXPERBITRANK1_Lane7_WID                       ( 4)
+  #define DDRDATA3CH1_CR_RXPERBITRANK1_Lane7_MSK                       (0xF0000000)
+  #define DDRDATA3CH1_CR_RXPERBITRANK1_Lane7_MAX                       (0x0000000F)
+
+#define DDRDATA3CH1_CR_RXPERBITRANK2_REG                             (0x00000718)
+  #define DDRDATA3CH1_CR_RXPERBITRANK2_Lane0_OFF                       ( 0)
+  #define DDRDATA3CH1_CR_RXPERBITRANK2_Lane0_WID                       ( 4)
+  #define DDRDATA3CH1_CR_RXPERBITRANK2_Lane0_MSK                       (0x0000000F)
+  #define DDRDATA3CH1_CR_RXPERBITRANK2_Lane0_MAX                       (0x0000000F)
+  #define DDRDATA3CH1_CR_RXPERBITRANK2_Lane1_OFF                       ( 4)
+  #define DDRDATA3CH1_CR_RXPERBITRANK2_Lane1_WID                       ( 4)
+  #define DDRDATA3CH1_CR_RXPERBITRANK2_Lane1_MSK                       (0x000000F0)
+  #define DDRDATA3CH1_CR_RXPERBITRANK2_Lane1_MAX                       (0x0000000F)
+  #define DDRDATA3CH1_CR_RXPERBITRANK2_Lane2_OFF                       ( 8)
+  #define DDRDATA3CH1_CR_RXPERBITRANK2_Lane2_WID                       ( 4)
+  #define DDRDATA3CH1_CR_RXPERBITRANK2_Lane2_MSK                       (0x00000F00)
+  #define DDRDATA3CH1_CR_RXPERBITRANK2_Lane2_MAX                       (0x0000000F)
+  #define DDRDATA3CH1_CR_RXPERBITRANK2_Lane3_OFF                       (12)
+  #define DDRDATA3CH1_CR_RXPERBITRANK2_Lane3_WID                       ( 4)
+  #define DDRDATA3CH1_CR_RXPERBITRANK2_Lane3_MSK                       (0x0000F000)
+  #define DDRDATA3CH1_CR_RXPERBITRANK2_Lane3_MAX                       (0x0000000F)
+  #define DDRDATA3CH1_CR_RXPERBITRANK2_Lane4_OFF                       (16)
+  #define DDRDATA3CH1_CR_RXPERBITRANK2_Lane4_WID                       ( 4)
+  #define DDRDATA3CH1_CR_RXPERBITRANK2_Lane4_MSK                       (0x000F0000)
+  #define DDRDATA3CH1_CR_RXPERBITRANK2_Lane4_MAX                       (0x0000000F)
+  #define DDRDATA3CH1_CR_RXPERBITRANK2_Lane5_OFF                       (20)
+  #define DDRDATA3CH1_CR_RXPERBITRANK2_Lane5_WID                       ( 4)
+  #define DDRDATA3CH1_CR_RXPERBITRANK2_Lane5_MSK                       (0x00F00000)
+  #define DDRDATA3CH1_CR_RXPERBITRANK2_Lane5_MAX                       (0x0000000F)
+  #define DDRDATA3CH1_CR_RXPERBITRANK2_Lane6_OFF                       (24)
+  #define DDRDATA3CH1_CR_RXPERBITRANK2_Lane6_WID                       ( 4)
+  #define DDRDATA3CH1_CR_RXPERBITRANK2_Lane6_MSK                       (0x0F000000)
+  #define DDRDATA3CH1_CR_RXPERBITRANK2_Lane6_MAX                       (0x0000000F)
+  #define DDRDATA3CH1_CR_RXPERBITRANK2_Lane7_OFF                       (28)
+  #define DDRDATA3CH1_CR_RXPERBITRANK2_Lane7_WID                       ( 4)
+  #define DDRDATA3CH1_CR_RXPERBITRANK2_Lane7_MSK                       (0xF0000000)
+  #define DDRDATA3CH1_CR_RXPERBITRANK2_Lane7_MAX                       (0x0000000F)
+
+#define DDRDATA3CH1_CR_RXPERBITRANK3_REG                             (0x0000071C)
+  #define DDRDATA3CH1_CR_RXPERBITRANK3_Lane0_OFF                       ( 0)
+  #define DDRDATA3CH1_CR_RXPERBITRANK3_Lane0_WID                       ( 4)
+  #define DDRDATA3CH1_CR_RXPERBITRANK3_Lane0_MSK                       (0x0000000F)
+  #define DDRDATA3CH1_CR_RXPERBITRANK3_Lane0_MAX                       (0x0000000F)
+  #define DDRDATA3CH1_CR_RXPERBITRANK3_Lane1_OFF                       ( 4)
+  #define DDRDATA3CH1_CR_RXPERBITRANK3_Lane1_WID                       ( 4)
+  #define DDRDATA3CH1_CR_RXPERBITRANK3_Lane1_MSK                       (0x000000F0)
+  #define DDRDATA3CH1_CR_RXPERBITRANK3_Lane1_MAX                       (0x0000000F)
+  #define DDRDATA3CH1_CR_RXPERBITRANK3_Lane2_OFF                       ( 8)
+  #define DDRDATA3CH1_CR_RXPERBITRANK3_Lane2_WID                       ( 4)
+  #define DDRDATA3CH1_CR_RXPERBITRANK3_Lane2_MSK                       (0x00000F00)
+  #define DDRDATA3CH1_CR_RXPERBITRANK3_Lane2_MAX                       (0x0000000F)
+  #define DDRDATA3CH1_CR_RXPERBITRANK3_Lane3_OFF                       (12)
+  #define DDRDATA3CH1_CR_RXPERBITRANK3_Lane3_WID                       ( 4)
+  #define DDRDATA3CH1_CR_RXPERBITRANK3_Lane3_MSK                       (0x0000F000)
+  #define DDRDATA3CH1_CR_RXPERBITRANK3_Lane3_MAX                       (0x0000000F)
+  #define DDRDATA3CH1_CR_RXPERBITRANK3_Lane4_OFF                       (16)
+  #define DDRDATA3CH1_CR_RXPERBITRANK3_Lane4_WID                       ( 4)
+  #define DDRDATA3CH1_CR_RXPERBITRANK3_Lane4_MSK                       (0x000F0000)
+  #define DDRDATA3CH1_CR_RXPERBITRANK3_Lane4_MAX                       (0x0000000F)
+  #define DDRDATA3CH1_CR_RXPERBITRANK3_Lane5_OFF                       (20)
+  #define DDRDATA3CH1_CR_RXPERBITRANK3_Lane5_WID                       ( 4)
+  #define DDRDATA3CH1_CR_RXPERBITRANK3_Lane5_MSK                       (0x00F00000)
+  #define DDRDATA3CH1_CR_RXPERBITRANK3_Lane5_MAX                       (0x0000000F)
+  #define DDRDATA3CH1_CR_RXPERBITRANK3_Lane6_OFF                       (24)
+  #define DDRDATA3CH1_CR_RXPERBITRANK3_Lane6_WID                       ( 4)
+  #define DDRDATA3CH1_CR_RXPERBITRANK3_Lane6_MSK                       (0x0F000000)
+  #define DDRDATA3CH1_CR_RXPERBITRANK3_Lane6_MAX                       (0x0000000F)
+  #define DDRDATA3CH1_CR_RXPERBITRANK3_Lane7_OFF                       (28)
+  #define DDRDATA3CH1_CR_RXPERBITRANK3_Lane7_WID                       ( 4)
+  #define DDRDATA3CH1_CR_RXPERBITRANK3_Lane7_MSK                       (0xF0000000)
+  #define DDRDATA3CH1_CR_RXPERBITRANK3_Lane7_MAX                       (0x0000000F)
+
+#define DDRDATA3CH1_CR_TXTRAINRANK0_REG                              (0x00000720)
+  #define DDRDATA3CH1_CR_TXTRAINRANK0_TxDqDelay_OFF                    ( 0)
+  #define DDRDATA3CH1_CR_TXTRAINRANK0_TxDqDelay_WID                    ( 9)
+  #define DDRDATA3CH1_CR_TXTRAINRANK0_TxDqDelay_MSK                    (0x000001FF)
+  #define DDRDATA3CH1_CR_TXTRAINRANK0_TxDqDelay_MAX                    (0x000001FF)
+  #define DDRDATA3CH1_CR_TXTRAINRANK0_TxDqsDelay_OFF                   ( 9)
+  #define DDRDATA3CH1_CR_TXTRAINRANK0_TxDqsDelay_WID                   ( 9)
+  #define DDRDATA3CH1_CR_TXTRAINRANK0_TxDqsDelay_MSK                   (0x0003FE00)
+  #define DDRDATA3CH1_CR_TXTRAINRANK0_TxDqsDelay_MAX                   (0x000001FF)
+  #define DDRDATA3CH1_CR_TXTRAINRANK0_Spare0_OFF                       (18)
+  #define DDRDATA3CH1_CR_TXTRAINRANK0_Spare0_WID                       ( 2)
+  #define DDRDATA3CH1_CR_TXTRAINRANK0_Spare0_MSK                       (0x000C0000)
+  #define DDRDATA3CH1_CR_TXTRAINRANK0_Spare0_MAX                       (0x00000003)
+  #define DDRDATA3CH1_CR_TXTRAINRANK0_TxEqualization_OFF               (20)
+  #define DDRDATA3CH1_CR_TXTRAINRANK0_TxEqualization_WID               ( 6)
+  #define DDRDATA3CH1_CR_TXTRAINRANK0_TxEqualization_MSK               (0x03F00000)
+  #define DDRDATA3CH1_CR_TXTRAINRANK0_TxEqualization_MAX               (0x0000003F)
+  #define DDRDATA3CH1_CR_TXTRAINRANK0_Spare1_OFF                       (26)
+  #define DDRDATA3CH1_CR_TXTRAINRANK0_Spare1_WID                       ( 6)
+  #define DDRDATA3CH1_CR_TXTRAINRANK0_Spare1_MSK                       (0xFC000000)
+  #define DDRDATA3CH1_CR_TXTRAINRANK0_Spare1_MAX                       (0x0000003F)
+
+#define DDRDATA3CH1_CR_TXTRAINRANK1_REG                              (0x00000724)
+  #define DDRDATA3CH1_CR_TXTRAINRANK1_TxDqDelay_OFF                    ( 0)
+  #define DDRDATA3CH1_CR_TXTRAINRANK1_TxDqDelay_WID                    ( 9)
+  #define DDRDATA3CH1_CR_TXTRAINRANK1_TxDqDelay_MSK                    (0x000001FF)
+  #define DDRDATA3CH1_CR_TXTRAINRANK1_TxDqDelay_MAX                    (0x000001FF)
+  #define DDRDATA3CH1_CR_TXTRAINRANK1_TxDqsDelay_OFF                   ( 9)
+  #define DDRDATA3CH1_CR_TXTRAINRANK1_TxDqsDelay_WID                   ( 9)
+  #define DDRDATA3CH1_CR_TXTRAINRANK1_TxDqsDelay_MSK                   (0x0003FE00)
+  #define DDRDATA3CH1_CR_TXTRAINRANK1_TxDqsDelay_MAX                   (0x000001FF)
+  #define DDRDATA3CH1_CR_TXTRAINRANK1_Spare0_OFF                       (18)
+  #define DDRDATA3CH1_CR_TXTRAINRANK1_Spare0_WID                       ( 2)
+  #define DDRDATA3CH1_CR_TXTRAINRANK1_Spare0_MSK                       (0x000C0000)
+  #define DDRDATA3CH1_CR_TXTRAINRANK1_Spare0_MAX                       (0x00000003)
+  #define DDRDATA3CH1_CR_TXTRAINRANK1_TxEqualization_OFF               (20)
+  #define DDRDATA3CH1_CR_TXTRAINRANK1_TxEqualization_WID               ( 6)
+  #define DDRDATA3CH1_CR_TXTRAINRANK1_TxEqualization_MSK               (0x03F00000)
+  #define DDRDATA3CH1_CR_TXTRAINRANK1_TxEqualization_MAX               (0x0000003F)
+  #define DDRDATA3CH1_CR_TXTRAINRANK1_Spare1_OFF                       (26)
+  #define DDRDATA3CH1_CR_TXTRAINRANK1_Spare1_WID                       ( 6)
+  #define DDRDATA3CH1_CR_TXTRAINRANK1_Spare1_MSK                       (0xFC000000)
+  #define DDRDATA3CH1_CR_TXTRAINRANK1_Spare1_MAX                       (0x0000003F)
+
+#define DDRDATA3CH1_CR_TXTRAINRANK2_REG                              (0x00000728)
+  #define DDRDATA3CH1_CR_TXTRAINRANK2_TxDqDelay_OFF                    ( 0)
+  #define DDRDATA3CH1_CR_TXTRAINRANK2_TxDqDelay_WID                    ( 9)
+  #define DDRDATA3CH1_CR_TXTRAINRANK2_TxDqDelay_MSK                    (0x000001FF)
+  #define DDRDATA3CH1_CR_TXTRAINRANK2_TxDqDelay_MAX                    (0x000001FF)
+  #define DDRDATA3CH1_CR_TXTRAINRANK2_TxDqsDelay_OFF                   ( 9)
+  #define DDRDATA3CH1_CR_TXTRAINRANK2_TxDqsDelay_WID                   ( 9)
+  #define DDRDATA3CH1_CR_TXTRAINRANK2_TxDqsDelay_MSK                   (0x0003FE00)
+  #define DDRDATA3CH1_CR_TXTRAINRANK2_TxDqsDelay_MAX                   (0x000001FF)
+  #define DDRDATA3CH1_CR_TXTRAINRANK2_Spare0_OFF                       (18)
+  #define DDRDATA3CH1_CR_TXTRAINRANK2_Spare0_WID                       ( 2)
+  #define DDRDATA3CH1_CR_TXTRAINRANK2_Spare0_MSK                       (0x000C0000)
+  #define DDRDATA3CH1_CR_TXTRAINRANK2_Spare0_MAX                       (0x00000003)
+  #define DDRDATA3CH1_CR_TXTRAINRANK2_TxEqualization_OFF               (20)
+  #define DDRDATA3CH1_CR_TXTRAINRANK2_TxEqualization_WID               ( 6)
+  #define DDRDATA3CH1_CR_TXTRAINRANK2_TxEqualization_MSK               (0x03F00000)
+  #define DDRDATA3CH1_CR_TXTRAINRANK2_TxEqualization_MAX               (0x0000003F)
+  #define DDRDATA3CH1_CR_TXTRAINRANK2_Spare1_OFF                       (26)
+  #define DDRDATA3CH1_CR_TXTRAINRANK2_Spare1_WID                       ( 6)
+  #define DDRDATA3CH1_CR_TXTRAINRANK2_Spare1_MSK                       (0xFC000000)
+  #define DDRDATA3CH1_CR_TXTRAINRANK2_Spare1_MAX                       (0x0000003F)
+
+#define DDRDATA3CH1_CR_TXTRAINRANK3_REG                              (0x0000072C)
+  #define DDRDATA3CH1_CR_TXTRAINRANK3_TxDqDelay_OFF                    ( 0)
+  #define DDRDATA3CH1_CR_TXTRAINRANK3_TxDqDelay_WID                    ( 9)
+  #define DDRDATA3CH1_CR_TXTRAINRANK3_TxDqDelay_MSK                    (0x000001FF)
+  #define DDRDATA3CH1_CR_TXTRAINRANK3_TxDqDelay_MAX                    (0x000001FF)
+  #define DDRDATA3CH1_CR_TXTRAINRANK3_TxDqsDelay_OFF                   ( 9)
+  #define DDRDATA3CH1_CR_TXTRAINRANK3_TxDqsDelay_WID                   ( 9)
+  #define DDRDATA3CH1_CR_TXTRAINRANK3_TxDqsDelay_MSK                   (0x0003FE00)
+  #define DDRDATA3CH1_CR_TXTRAINRANK3_TxDqsDelay_MAX                   (0x000001FF)
+  #define DDRDATA3CH1_CR_TXTRAINRANK3_Spare0_OFF                       (18)
+  #define DDRDATA3CH1_CR_TXTRAINRANK3_Spare0_WID                       ( 2)
+  #define DDRDATA3CH1_CR_TXTRAINRANK3_Spare0_MSK                       (0x000C0000)
+  #define DDRDATA3CH1_CR_TXTRAINRANK3_Spare0_MAX                       (0x00000003)
+  #define DDRDATA3CH1_CR_TXTRAINRANK3_TxEqualization_OFF               (20)
+  #define DDRDATA3CH1_CR_TXTRAINRANK3_TxEqualization_WID               ( 6)
+  #define DDRDATA3CH1_CR_TXTRAINRANK3_TxEqualization_MSK               (0x03F00000)
+  #define DDRDATA3CH1_CR_TXTRAINRANK3_TxEqualization_MAX               (0x0000003F)
+  #define DDRDATA3CH1_CR_TXTRAINRANK3_Spare1_OFF                       (26)
+  #define DDRDATA3CH1_CR_TXTRAINRANK3_Spare1_WID                       ( 6)
+  #define DDRDATA3CH1_CR_TXTRAINRANK3_Spare1_MSK                       (0xFC000000)
+  #define DDRDATA3CH1_CR_TXTRAINRANK3_Spare1_MAX                       (0x0000003F)
+
+#define DDRDATA3CH1_CR_TXPERBITRANK0_REG                             (0x00000730)
+  #define DDRDATA3CH1_CR_TXPERBITRANK0_Lane0_OFF                       ( 0)
+  #define DDRDATA3CH1_CR_TXPERBITRANK0_Lane0_WID                       ( 4)
+  #define DDRDATA3CH1_CR_TXPERBITRANK0_Lane0_MSK                       (0x0000000F)
+  #define DDRDATA3CH1_CR_TXPERBITRANK0_Lane0_MAX                       (0x0000000F)
+  #define DDRDATA3CH1_CR_TXPERBITRANK0_Lane1_OFF                       ( 4)
+  #define DDRDATA3CH1_CR_TXPERBITRANK0_Lane1_WID                       ( 4)
+  #define DDRDATA3CH1_CR_TXPERBITRANK0_Lane1_MSK                       (0x000000F0)
+  #define DDRDATA3CH1_CR_TXPERBITRANK0_Lane1_MAX                       (0x0000000F)
+  #define DDRDATA3CH1_CR_TXPERBITRANK0_Lane2_OFF                       ( 8)
+  #define DDRDATA3CH1_CR_TXPERBITRANK0_Lane2_WID                       ( 4)
+  #define DDRDATA3CH1_CR_TXPERBITRANK0_Lane2_MSK                       (0x00000F00)
+  #define DDRDATA3CH1_CR_TXPERBITRANK0_Lane2_MAX                       (0x0000000F)
+  #define DDRDATA3CH1_CR_TXPERBITRANK0_Lane3_OFF                       (12)
+  #define DDRDATA3CH1_CR_TXPERBITRANK0_Lane3_WID                       ( 4)
+  #define DDRDATA3CH1_CR_TXPERBITRANK0_Lane3_MSK                       (0x0000F000)
+  #define DDRDATA3CH1_CR_TXPERBITRANK0_Lane3_MAX                       (0x0000000F)
+  #define DDRDATA3CH1_CR_TXPERBITRANK0_Lane4_OFF                       (16)
+  #define DDRDATA3CH1_CR_TXPERBITRANK0_Lane4_WID                       ( 4)
+  #define DDRDATA3CH1_CR_TXPERBITRANK0_Lane4_MSK                       (0x000F0000)
+  #define DDRDATA3CH1_CR_TXPERBITRANK0_Lane4_MAX                       (0x0000000F)
+  #define DDRDATA3CH1_CR_TXPERBITRANK0_Lane5_OFF                       (20)
+  #define DDRDATA3CH1_CR_TXPERBITRANK0_Lane5_WID                       ( 4)
+  #define DDRDATA3CH1_CR_TXPERBITRANK0_Lane5_MSK                       (0x00F00000)
+  #define DDRDATA3CH1_CR_TXPERBITRANK0_Lane5_MAX                       (0x0000000F)
+  #define DDRDATA3CH1_CR_TXPERBITRANK0_Lane6_OFF                       (24)
+  #define DDRDATA3CH1_CR_TXPERBITRANK0_Lane6_WID                       ( 4)
+  #define DDRDATA3CH1_CR_TXPERBITRANK0_Lane6_MSK                       (0x0F000000)
+  #define DDRDATA3CH1_CR_TXPERBITRANK0_Lane6_MAX                       (0x0000000F)
+  #define DDRDATA3CH1_CR_TXPERBITRANK0_Lane7_OFF                       (28)
+  #define DDRDATA3CH1_CR_TXPERBITRANK0_Lane7_WID                       ( 4)
+  #define DDRDATA3CH1_CR_TXPERBITRANK0_Lane7_MSK                       (0xF0000000)
+  #define DDRDATA3CH1_CR_TXPERBITRANK0_Lane7_MAX                       (0x0000000F)
+
+#define DDRDATA3CH1_CR_TXPERBITRANK1_REG                             (0x00000734)
+  #define DDRDATA3CH1_CR_TXPERBITRANK1_Lane0_OFF                       ( 0)
+  #define DDRDATA3CH1_CR_TXPERBITRANK1_Lane0_WID                       ( 4)
+  #define DDRDATA3CH1_CR_TXPERBITRANK1_Lane0_MSK                       (0x0000000F)
+  #define DDRDATA3CH1_CR_TXPERBITRANK1_Lane0_MAX                       (0x0000000F)
+  #define DDRDATA3CH1_CR_TXPERBITRANK1_Lane1_OFF                       ( 4)
+  #define DDRDATA3CH1_CR_TXPERBITRANK1_Lane1_WID                       ( 4)
+  #define DDRDATA3CH1_CR_TXPERBITRANK1_Lane1_MSK                       (0x000000F0)
+  #define DDRDATA3CH1_CR_TXPERBITRANK1_Lane1_MAX                       (0x0000000F)
+  #define DDRDATA3CH1_CR_TXPERBITRANK1_Lane2_OFF                       ( 8)
+  #define DDRDATA3CH1_CR_TXPERBITRANK1_Lane2_WID                       ( 4)
+  #define DDRDATA3CH1_CR_TXPERBITRANK1_Lane2_MSK                       (0x00000F00)
+  #define DDRDATA3CH1_CR_TXPERBITRANK1_Lane2_MAX                       (0x0000000F)
+  #define DDRDATA3CH1_CR_TXPERBITRANK1_Lane3_OFF                       (12)
+  #define DDRDATA3CH1_CR_TXPERBITRANK1_Lane3_WID                       ( 4)
+  #define DDRDATA3CH1_CR_TXPERBITRANK1_Lane3_MSK                       (0x0000F000)
+  #define DDRDATA3CH1_CR_TXPERBITRANK1_Lane3_MAX                       (0x0000000F)
+  #define DDRDATA3CH1_CR_TXPERBITRANK1_Lane4_OFF                       (16)
+  #define DDRDATA3CH1_CR_TXPERBITRANK1_Lane4_WID                       ( 4)
+  #define DDRDATA3CH1_CR_TXPERBITRANK1_Lane4_MSK                       (0x000F0000)
+  #define DDRDATA3CH1_CR_TXPERBITRANK1_Lane4_MAX                       (0x0000000F)
+  #define DDRDATA3CH1_CR_TXPERBITRANK1_Lane5_OFF                       (20)
+  #define DDRDATA3CH1_CR_TXPERBITRANK1_Lane5_WID                       ( 4)
+  #define DDRDATA3CH1_CR_TXPERBITRANK1_Lane5_MSK                       (0x00F00000)
+  #define DDRDATA3CH1_CR_TXPERBITRANK1_Lane5_MAX                       (0x0000000F)
+  #define DDRDATA3CH1_CR_TXPERBITRANK1_Lane6_OFF                       (24)
+  #define DDRDATA3CH1_CR_TXPERBITRANK1_Lane6_WID                       ( 4)
+  #define DDRDATA3CH1_CR_TXPERBITRANK1_Lane6_MSK                       (0x0F000000)
+  #define DDRDATA3CH1_CR_TXPERBITRANK1_Lane6_MAX                       (0x0000000F)
+  #define DDRDATA3CH1_CR_TXPERBITRANK1_Lane7_OFF                       (28)
+  #define DDRDATA3CH1_CR_TXPERBITRANK1_Lane7_WID                       ( 4)
+  #define DDRDATA3CH1_CR_TXPERBITRANK1_Lane7_MSK                       (0xF0000000)
+  #define DDRDATA3CH1_CR_TXPERBITRANK1_Lane7_MAX                       (0x0000000F)
+
+#define DDRDATA3CH1_CR_TXPERBITRANK2_REG                             (0x00000738)
+  #define DDRDATA3CH1_CR_TXPERBITRANK2_Lane0_OFF                       ( 0)
+  #define DDRDATA3CH1_CR_TXPERBITRANK2_Lane0_WID                       ( 4)
+  #define DDRDATA3CH1_CR_TXPERBITRANK2_Lane0_MSK                       (0x0000000F)
+  #define DDRDATA3CH1_CR_TXPERBITRANK2_Lane0_MAX                       (0x0000000F)
+  #define DDRDATA3CH1_CR_TXPERBITRANK2_Lane1_OFF                       ( 4)
+  #define DDRDATA3CH1_CR_TXPERBITRANK2_Lane1_WID                       ( 4)
+  #define DDRDATA3CH1_CR_TXPERBITRANK2_Lane1_MSK                       (0x000000F0)
+  #define DDRDATA3CH1_CR_TXPERBITRANK2_Lane1_MAX                       (0x0000000F)
+  #define DDRDATA3CH1_CR_TXPERBITRANK2_Lane2_OFF                       ( 8)
+  #define DDRDATA3CH1_CR_TXPERBITRANK2_Lane2_WID                       ( 4)
+  #define DDRDATA3CH1_CR_TXPERBITRANK2_Lane2_MSK                       (0x00000F00)
+  #define DDRDATA3CH1_CR_TXPERBITRANK2_Lane2_MAX                       (0x0000000F)
+  #define DDRDATA3CH1_CR_TXPERBITRANK2_Lane3_OFF                       (12)
+  #define DDRDATA3CH1_CR_TXPERBITRANK2_Lane3_WID                       ( 4)
+  #define DDRDATA3CH1_CR_TXPERBITRANK2_Lane3_MSK                       (0x0000F000)
+  #define DDRDATA3CH1_CR_TXPERBITRANK2_Lane3_MAX                       (0x0000000F)
+  #define DDRDATA3CH1_CR_TXPERBITRANK2_Lane4_OFF                       (16)
+  #define DDRDATA3CH1_CR_TXPERBITRANK2_Lane4_WID                       ( 4)
+  #define DDRDATA3CH1_CR_TXPERBITRANK2_Lane4_MSK                       (0x000F0000)
+  #define DDRDATA3CH1_CR_TXPERBITRANK2_Lane4_MAX                       (0x0000000F)
+  #define DDRDATA3CH1_CR_TXPERBITRANK2_Lane5_OFF                       (20)
+  #define DDRDATA3CH1_CR_TXPERBITRANK2_Lane5_WID                       ( 4)
+  #define DDRDATA3CH1_CR_TXPERBITRANK2_Lane5_MSK                       (0x00F00000)
+  #define DDRDATA3CH1_CR_TXPERBITRANK2_Lane5_MAX                       (0x0000000F)
+  #define DDRDATA3CH1_CR_TXPERBITRANK2_Lane6_OFF                       (24)
+  #define DDRDATA3CH1_CR_TXPERBITRANK2_Lane6_WID                       ( 4)
+  #define DDRDATA3CH1_CR_TXPERBITRANK2_Lane6_MSK                       (0x0F000000)
+  #define DDRDATA3CH1_CR_TXPERBITRANK2_Lane6_MAX                       (0x0000000F)
+  #define DDRDATA3CH1_CR_TXPERBITRANK2_Lane7_OFF                       (28)
+  #define DDRDATA3CH1_CR_TXPERBITRANK2_Lane7_WID                       ( 4)
+  #define DDRDATA3CH1_CR_TXPERBITRANK2_Lane7_MSK                       (0xF0000000)
+  #define DDRDATA3CH1_CR_TXPERBITRANK2_Lane7_MAX                       (0x0000000F)
+
+#define DDRDATA3CH1_CR_TXPERBITRANK3_REG                             (0x0000073C)
+  #define DDRDATA3CH1_CR_TXPERBITRANK3_Lane0_OFF                       ( 0)
+  #define DDRDATA3CH1_CR_TXPERBITRANK3_Lane0_WID                       ( 4)
+  #define DDRDATA3CH1_CR_TXPERBITRANK3_Lane0_MSK                       (0x0000000F)
+  #define DDRDATA3CH1_CR_TXPERBITRANK3_Lane0_MAX                       (0x0000000F)
+  #define DDRDATA3CH1_CR_TXPERBITRANK3_Lane1_OFF                       ( 4)
+  #define DDRDATA3CH1_CR_TXPERBITRANK3_Lane1_WID                       ( 4)
+  #define DDRDATA3CH1_CR_TXPERBITRANK3_Lane1_MSK                       (0x000000F0)
+  #define DDRDATA3CH1_CR_TXPERBITRANK3_Lane1_MAX                       (0x0000000F)
+  #define DDRDATA3CH1_CR_TXPERBITRANK3_Lane2_OFF                       ( 8)
+  #define DDRDATA3CH1_CR_TXPERBITRANK3_Lane2_WID                       ( 4)
+  #define DDRDATA3CH1_CR_TXPERBITRANK3_Lane2_MSK                       (0x00000F00)
+  #define DDRDATA3CH1_CR_TXPERBITRANK3_Lane2_MAX                       (0x0000000F)
+  #define DDRDATA3CH1_CR_TXPERBITRANK3_Lane3_OFF                       (12)
+  #define DDRDATA3CH1_CR_TXPERBITRANK3_Lane3_WID                       ( 4)
+  #define DDRDATA3CH1_CR_TXPERBITRANK3_Lane3_MSK                       (0x0000F000)
+  #define DDRDATA3CH1_CR_TXPERBITRANK3_Lane3_MAX                       (0x0000000F)
+  #define DDRDATA3CH1_CR_TXPERBITRANK3_Lane4_OFF                       (16)
+  #define DDRDATA3CH1_CR_TXPERBITRANK3_Lane4_WID                       ( 4)
+  #define DDRDATA3CH1_CR_TXPERBITRANK3_Lane4_MSK                       (0x000F0000)
+  #define DDRDATA3CH1_CR_TXPERBITRANK3_Lane4_MAX                       (0x0000000F)
+  #define DDRDATA3CH1_CR_TXPERBITRANK3_Lane5_OFF                       (20)
+  #define DDRDATA3CH1_CR_TXPERBITRANK3_Lane5_WID                       ( 4)
+  #define DDRDATA3CH1_CR_TXPERBITRANK3_Lane5_MSK                       (0x00F00000)
+  #define DDRDATA3CH1_CR_TXPERBITRANK3_Lane5_MAX                       (0x0000000F)
+  #define DDRDATA3CH1_CR_TXPERBITRANK3_Lane6_OFF                       (24)
+  #define DDRDATA3CH1_CR_TXPERBITRANK3_Lane6_WID                       ( 4)
+  #define DDRDATA3CH1_CR_TXPERBITRANK3_Lane6_MSK                       (0x0F000000)
+  #define DDRDATA3CH1_CR_TXPERBITRANK3_Lane6_MAX                       (0x0000000F)
+  #define DDRDATA3CH1_CR_TXPERBITRANK3_Lane7_OFF                       (28)
+  #define DDRDATA3CH1_CR_TXPERBITRANK3_Lane7_WID                       ( 4)
+  #define DDRDATA3CH1_CR_TXPERBITRANK3_Lane7_MSK                       (0xF0000000)
+  #define DDRDATA3CH1_CR_TXPERBITRANK3_Lane7_MAX                       (0x0000000F)
+
+#define DDRDATA3CH1_CR_RCOMPDATA0_REG                                (0x00000740)
+  #define DDRDATA3CH1_CR_RCOMPDATA0_RcompDrvUp_OFF                     ( 0)
+  #define DDRDATA3CH1_CR_RCOMPDATA0_RcompDrvUp_WID                     ( 6)
+  #define DDRDATA3CH1_CR_RCOMPDATA0_RcompDrvUp_MSK                     (0x0000003F)
+  #define DDRDATA3CH1_CR_RCOMPDATA0_RcompDrvUp_MAX                     (0x0000003F)
+  #define DDRDATA3CH1_CR_RCOMPDATA0_Spare0_OFF                         ( 6)
+  #define DDRDATA3CH1_CR_RCOMPDATA0_Spare0_WID                         ( 3)
+  #define DDRDATA3CH1_CR_RCOMPDATA0_Spare0_MSK                         (0x000001C0)
+  #define DDRDATA3CH1_CR_RCOMPDATA0_Spare0_MAX                         (0x00000007)
+  #define DDRDATA3CH1_CR_RCOMPDATA0_RcompDrvDown_OFF                   ( 9)
+  #define DDRDATA3CH1_CR_RCOMPDATA0_RcompDrvDown_WID                   ( 6)
+  #define DDRDATA3CH1_CR_RCOMPDATA0_RcompDrvDown_MSK                   (0x00007E00)
+  #define DDRDATA3CH1_CR_RCOMPDATA0_RcompDrvDown_MAX                   (0x0000003F)
+  #define DDRDATA3CH1_CR_RCOMPDATA0_VTComp_OFF                         (15)
+  #define DDRDATA3CH1_CR_RCOMPDATA0_VTComp_WID                         ( 5)
+  #define DDRDATA3CH1_CR_RCOMPDATA0_VTComp_MSK                         (0x000F8000)
+  #define DDRDATA3CH1_CR_RCOMPDATA0_VTComp_MAX                         (0x0000001F)
+  #define DDRDATA3CH1_CR_RCOMPDATA0_TcoComp_OFF                        (20)
+  #define DDRDATA3CH1_CR_RCOMPDATA0_TcoComp_WID                        ( 6)
+  #define DDRDATA3CH1_CR_RCOMPDATA0_TcoComp_MSK                        (0x03F00000)
+  #define DDRDATA3CH1_CR_RCOMPDATA0_TcoComp_MAX                        (0x0000003F)
+  #define DDRDATA3CH1_CR_RCOMPDATA0_SlewRateComp_OFF                   (26)
+  #define DDRDATA3CH1_CR_RCOMPDATA0_SlewRateComp_WID                   ( 5)
+  #define DDRDATA3CH1_CR_RCOMPDATA0_SlewRateComp_MSK                   (0x7C000000)
+  #define DDRDATA3CH1_CR_RCOMPDATA0_SlewRateComp_MAX                   (0x0000001F)
+  #define DDRDATA3CH1_CR_RCOMPDATA0_Spare2_OFF                         (31)
+  #define DDRDATA3CH1_CR_RCOMPDATA0_Spare2_WID                         ( 1)
+  #define DDRDATA3CH1_CR_RCOMPDATA0_Spare2_MSK                         (0x80000000)
+  #define DDRDATA3CH1_CR_RCOMPDATA0_Spare2_MAX                         (0x00000001)
+
+#define DDRDATA3CH1_CR_RCOMPDATA1_REG                                (0x00000744)
+  #define DDRDATA3CH1_CR_RCOMPDATA1_RcompOdtUp_OFF                     ( 0)
+  #define DDRDATA3CH1_CR_RCOMPDATA1_RcompOdtUp_WID                     ( 6)
+  #define DDRDATA3CH1_CR_RCOMPDATA1_RcompOdtUp_MSK                     (0x0000003F)
+  #define DDRDATA3CH1_CR_RCOMPDATA1_RcompOdtUp_MAX                     (0x0000003F)
+  #define DDRDATA3CH1_CR_RCOMPDATA1_Spare0_OFF                         ( 6)
+  #define DDRDATA3CH1_CR_RCOMPDATA1_Spare0_WID                         ( 3)
+  #define DDRDATA3CH1_CR_RCOMPDATA1_Spare0_MSK                         (0x000001C0)
+  #define DDRDATA3CH1_CR_RCOMPDATA1_Spare0_MAX                         (0x00000007)
+  #define DDRDATA3CH1_CR_RCOMPDATA1_RcompOdtDown_OFF                   ( 9)
+  #define DDRDATA3CH1_CR_RCOMPDATA1_RcompOdtDown_WID                   ( 6)
+  #define DDRDATA3CH1_CR_RCOMPDATA1_RcompOdtDown_MSK                   (0x00007E00)
+  #define DDRDATA3CH1_CR_RCOMPDATA1_RcompOdtDown_MAX                   (0x0000003F)
+  #define DDRDATA3CH1_CR_RCOMPDATA1_Spare1_OFF                         (15)
+  #define DDRDATA3CH1_CR_RCOMPDATA1_Spare1_WID                         ( 1)
+  #define DDRDATA3CH1_CR_RCOMPDATA1_Spare1_MSK                         (0x00008000)
+  #define DDRDATA3CH1_CR_RCOMPDATA1_Spare1_MAX                         (0x00000001)
+  #define DDRDATA3CH1_CR_RCOMPDATA1_PanicDrvDn_OFF                     (16)
+  #define DDRDATA3CH1_CR_RCOMPDATA1_PanicDrvDn_WID                     ( 6)
+  #define DDRDATA3CH1_CR_RCOMPDATA1_PanicDrvDn_MSK                     (0x003F0000)
+  #define DDRDATA3CH1_CR_RCOMPDATA1_PanicDrvDn_MAX                     (0x0000003F)
+  #define DDRDATA3CH1_CR_RCOMPDATA1_PanicDrvUp_OFF                     (22)
+  #define DDRDATA3CH1_CR_RCOMPDATA1_PanicDrvUp_WID                     ( 6)
+  #define DDRDATA3CH1_CR_RCOMPDATA1_PanicDrvUp_MSK                     (0x0FC00000)
+  #define DDRDATA3CH1_CR_RCOMPDATA1_PanicDrvUp_MAX                     (0x0000003F)
+  #define DDRDATA3CH1_CR_RCOMPDATA1_LevelShifterComp_OFF               (28)
+  #define DDRDATA3CH1_CR_RCOMPDATA1_LevelShifterComp_WID               ( 3)
+  #define DDRDATA3CH1_CR_RCOMPDATA1_LevelShifterComp_MSK               (0x70000000)
+  #define DDRDATA3CH1_CR_RCOMPDATA1_LevelShifterComp_MAX               (0x00000007)
+  #define DDRDATA3CH1_CR_RCOMPDATA1_Spare2_OFF                         (31)
+  #define DDRDATA3CH1_CR_RCOMPDATA1_Spare2_WID                         ( 1)
+  #define DDRDATA3CH1_CR_RCOMPDATA1_Spare2_MSK                         (0x80000000)
+  #define DDRDATA3CH1_CR_RCOMPDATA1_Spare2_MAX                         (0x00000001)
+
+#define DDRDATA3CH1_CR_TXXTALK_REG                                   (0x00000748)
+  #define DDRDATA3CH1_CR_TXXTALK_Lane0_OFF                             ( 0)
+  #define DDRDATA3CH1_CR_TXXTALK_Lane0_WID                             ( 4)
+  #define DDRDATA3CH1_CR_TXXTALK_Lane0_MSK                             (0x0000000F)
+  #define DDRDATA3CH1_CR_TXXTALK_Lane0_MAX                             (0x0000000F)
+  #define DDRDATA3CH1_CR_TXXTALK_Lane1_OFF                             ( 4)
+  #define DDRDATA3CH1_CR_TXXTALK_Lane1_WID                             ( 4)
+  #define DDRDATA3CH1_CR_TXXTALK_Lane1_MSK                             (0x000000F0)
+  #define DDRDATA3CH1_CR_TXXTALK_Lane1_MAX                             (0x0000000F)
+  #define DDRDATA3CH1_CR_TXXTALK_Lane2_OFF                             ( 8)
+  #define DDRDATA3CH1_CR_TXXTALK_Lane2_WID                             ( 4)
+  #define DDRDATA3CH1_CR_TXXTALK_Lane2_MSK                             (0x00000F00)
+  #define DDRDATA3CH1_CR_TXXTALK_Lane2_MAX                             (0x0000000F)
+  #define DDRDATA3CH1_CR_TXXTALK_Lane3_OFF                             (12)
+  #define DDRDATA3CH1_CR_TXXTALK_Lane3_WID                             ( 4)
+  #define DDRDATA3CH1_CR_TXXTALK_Lane3_MSK                             (0x0000F000)
+  #define DDRDATA3CH1_CR_TXXTALK_Lane3_MAX                             (0x0000000F)
+  #define DDRDATA3CH1_CR_TXXTALK_Lane4_OFF                             (16)
+  #define DDRDATA3CH1_CR_TXXTALK_Lane4_WID                             ( 4)
+  #define DDRDATA3CH1_CR_TXXTALK_Lane4_MSK                             (0x000F0000)
+  #define DDRDATA3CH1_CR_TXXTALK_Lane4_MAX                             (0x0000000F)
+  #define DDRDATA3CH1_CR_TXXTALK_Lane5_OFF                             (20)
+  #define DDRDATA3CH1_CR_TXXTALK_Lane5_WID                             ( 4)
+  #define DDRDATA3CH1_CR_TXXTALK_Lane5_MSK                             (0x00F00000)
+  #define DDRDATA3CH1_CR_TXXTALK_Lane5_MAX                             (0x0000000F)
+  #define DDRDATA3CH1_CR_TXXTALK_Lane6_OFF                             (24)
+  #define DDRDATA3CH1_CR_TXXTALK_Lane6_WID                             ( 4)
+  #define DDRDATA3CH1_CR_TXXTALK_Lane6_MSK                             (0x0F000000)
+  #define DDRDATA3CH1_CR_TXXTALK_Lane6_MAX                             (0x0000000F)
+  #define DDRDATA3CH1_CR_TXXTALK_Lane7_OFF                             (28)
+  #define DDRDATA3CH1_CR_TXXTALK_Lane7_WID                             ( 4)
+  #define DDRDATA3CH1_CR_TXXTALK_Lane7_MSK                             (0xF0000000)
+  #define DDRDATA3CH1_CR_TXXTALK_Lane7_MAX                             (0x0000000F)
+
+#define DDRDATA3CH1_CR_RXOFFSETVDQ_REG                               (0x0000074C)
+  #define DDRDATA3CH1_CR_RXOFFSETVDQ_Lane0_OFF                         ( 0)
+  #define DDRDATA3CH1_CR_RXOFFSETVDQ_Lane0_WID                         ( 4)
+  #define DDRDATA3CH1_CR_RXOFFSETVDQ_Lane0_MSK                         (0x0000000F)
+  #define DDRDATA3CH1_CR_RXOFFSETVDQ_Lane0_MAX                         (0x0000000F)
+  #define DDRDATA3CH1_CR_RXOFFSETVDQ_Lane1_OFF                         ( 4)
+  #define DDRDATA3CH1_CR_RXOFFSETVDQ_Lane1_WID                         ( 4)
+  #define DDRDATA3CH1_CR_RXOFFSETVDQ_Lane1_MSK                         (0x000000F0)
+  #define DDRDATA3CH1_CR_RXOFFSETVDQ_Lane1_MAX                         (0x0000000F)
+  #define DDRDATA3CH1_CR_RXOFFSETVDQ_Lane2_OFF                         ( 8)
+  #define DDRDATA3CH1_CR_RXOFFSETVDQ_Lane2_WID                         ( 4)
+  #define DDRDATA3CH1_CR_RXOFFSETVDQ_Lane2_MSK                         (0x00000F00)
+  #define DDRDATA3CH1_CR_RXOFFSETVDQ_Lane2_MAX                         (0x0000000F)
+  #define DDRDATA3CH1_CR_RXOFFSETVDQ_Lane3_OFF                         (12)
+  #define DDRDATA3CH1_CR_RXOFFSETVDQ_Lane3_WID                         ( 4)
+  #define DDRDATA3CH1_CR_RXOFFSETVDQ_Lane3_MSK                         (0x0000F000)
+  #define DDRDATA3CH1_CR_RXOFFSETVDQ_Lane3_MAX                         (0x0000000F)
+  #define DDRDATA3CH1_CR_RXOFFSETVDQ_Lane4_OFF                         (16)
+  #define DDRDATA3CH1_CR_RXOFFSETVDQ_Lane4_WID                         ( 4)
+  #define DDRDATA3CH1_CR_RXOFFSETVDQ_Lane4_MSK                         (0x000F0000)
+  #define DDRDATA3CH1_CR_RXOFFSETVDQ_Lane4_MAX                         (0x0000000F)
+  #define DDRDATA3CH1_CR_RXOFFSETVDQ_Lane5_OFF                         (20)
+  #define DDRDATA3CH1_CR_RXOFFSETVDQ_Lane5_WID                         ( 4)
+  #define DDRDATA3CH1_CR_RXOFFSETVDQ_Lane5_MSK                         (0x00F00000)
+  #define DDRDATA3CH1_CR_RXOFFSETVDQ_Lane5_MAX                         (0x0000000F)
+  #define DDRDATA3CH1_CR_RXOFFSETVDQ_Lane6_OFF                         (24)
+  #define DDRDATA3CH1_CR_RXOFFSETVDQ_Lane6_WID                         ( 4)
+  #define DDRDATA3CH1_CR_RXOFFSETVDQ_Lane6_MSK                         (0x0F000000)
+  #define DDRDATA3CH1_CR_RXOFFSETVDQ_Lane6_MAX                         (0x0000000F)
+  #define DDRDATA3CH1_CR_RXOFFSETVDQ_Lane7_OFF                         (28)
+  #define DDRDATA3CH1_CR_RXOFFSETVDQ_Lane7_WID                         ( 4)
+  #define DDRDATA3CH1_CR_RXOFFSETVDQ_Lane7_MSK                         (0xF0000000)
+  #define DDRDATA3CH1_CR_RXOFFSETVDQ_Lane7_MAX                         (0x0000000F)
+
+#define DDRDATA3CH1_CR_DDRDATARESERVED_REG                           (0x00000750)
+  #define DDRDATA3CH1_CR_DDRDATARESERVED_Spare_OFF                     ( 0)
+  #define DDRDATA3CH1_CR_DDRDATARESERVED_Spare_WID                     (32)
+  #define DDRDATA3CH1_CR_DDRDATARESERVED_Spare_MSK                     (0xFFFFFFFF)
+  #define DDRDATA3CH1_CR_DDRDATARESERVED_Spare_MAX                     (0xFFFFFFFF)
+
+#define DDRDATA3CH1_CR_DATATRAINFEEDBACK_REG                         (0x00000754)
+  #define DDRDATA3CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_OFF       ( 0)
+  #define DDRDATA3CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_WID       ( 9)
+  #define DDRDATA3CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_MSK       (0x000001FF)
+  #define DDRDATA3CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_MAX       (0x000001FF)
+  #define DDRDATA3CH1_CR_DATATRAINFEEDBACK_Spare_OFF                   ( 9)
+  #define DDRDATA3CH1_CR_DATATRAINFEEDBACK_Spare_WID                   (23)
+  #define DDRDATA3CH1_CR_DATATRAINFEEDBACK_Spare_MSK                   (0xFFFFFE00)
+  #define DDRDATA3CH1_CR_DATATRAINFEEDBACK_Spare_MAX                   (0x007FFFFF)
+
+#define DDRDATA3CH1_CR_DLLPITESTANDADC_REG                           (0x00000758)
+  #define DDRDATA3CH1_CR_DLLPITESTANDADC_RunTest_OFF                   ( 0)
+  #define DDRDATA3CH1_CR_DLLPITESTANDADC_RunTest_WID                   ( 1)
+  #define DDRDATA3CH1_CR_DLLPITESTANDADC_RunTest_MSK                   (0x00000001)
+  #define DDRDATA3CH1_CR_DLLPITESTANDADC_RunTest_MAX                   (0x00000001)
+  #define DDRDATA3CH1_CR_DLLPITESTANDADC_RunTest_DEF                   (0x00000000)
+  #define DDRDATA3CH1_CR_DLLPITESTANDADC_Load_OFF                      ( 1)
+  #define DDRDATA3CH1_CR_DLLPITESTANDADC_Load_WID                      ( 1)
+  #define DDRDATA3CH1_CR_DLLPITESTANDADC_Load_MSK                      (0x00000002)
+  #define DDRDATA3CH1_CR_DLLPITESTANDADC_Load_MAX                      (0x00000001)
+  #define DDRDATA3CH1_CR_DLLPITESTANDADC_Load_DEF                      (0x00000000)
+  #define DDRDATA3CH1_CR_DLLPITESTANDADC_ModeHVM_OFF                   ( 2)
+  #define DDRDATA3CH1_CR_DLLPITESTANDADC_ModeHVM_WID                   ( 1)
+  #define DDRDATA3CH1_CR_DLLPITESTANDADC_ModeHVM_MSK                   (0x00000004)
+  #define DDRDATA3CH1_CR_DLLPITESTANDADC_ModeHVM_MAX                   (0x00000001)
+  #define DDRDATA3CH1_CR_DLLPITESTANDADC_ModeHVM_DEF                   (0x00000000)
+  #define DDRDATA3CH1_CR_DLLPITESTANDADC_ModeDV_OFF                    ( 3)
+  #define DDRDATA3CH1_CR_DLLPITESTANDADC_ModeDV_WID                    ( 1)
+  #define DDRDATA3CH1_CR_DLLPITESTANDADC_ModeDV_MSK                    (0x00000008)
+  #define DDRDATA3CH1_CR_DLLPITESTANDADC_ModeDV_MAX                    (0x00000001)
+  #define DDRDATA3CH1_CR_DLLPITESTANDADC_ModeDV_DEF                    (0x00000000)
+  #define DDRDATA3CH1_CR_DLLPITESTANDADC_ModeADC_OFF                   ( 4)
+  #define DDRDATA3CH1_CR_DLLPITESTANDADC_ModeADC_WID                   ( 1)
+  #define DDRDATA3CH1_CR_DLLPITESTANDADC_ModeADC_MSK                   (0x00000010)
+  #define DDRDATA3CH1_CR_DLLPITESTANDADC_ModeADC_MAX                   (0x00000001)
+  #define DDRDATA3CH1_CR_DLLPITESTANDADC_ModeADC_DEF                   (0x00000000)
+  #define DDRDATA3CH1_CR_DLLPITESTANDADC_LoadCount_OFF                 ( 5)
+  #define DDRDATA3CH1_CR_DLLPITESTANDADC_LoadCount_WID                 (10)
+  #define DDRDATA3CH1_CR_DLLPITESTANDADC_LoadCount_MSK                 (0x00007FE0)
+  #define DDRDATA3CH1_CR_DLLPITESTANDADC_LoadCount_MAX                 (0x000003FF)
+  #define DDRDATA3CH1_CR_DLLPITESTANDADC_CountStatus_OFF               (15)
+  #define DDRDATA3CH1_CR_DLLPITESTANDADC_CountStatus_WID               (10)
+  #define DDRDATA3CH1_CR_DLLPITESTANDADC_CountStatus_MSK               (0x01FF8000)
+  #define DDRDATA3CH1_CR_DLLPITESTANDADC_CountStatus_MAX               (0x000003FF)
+  #define DDRDATA3CH1_CR_DLLPITESTANDADC_CountStatus_DEF               (0x00000000)
+  #define DDRDATA3CH1_CR_DLLPITESTANDADC_Spare_OFF                     (25)
+  #define DDRDATA3CH1_CR_DLLPITESTANDADC_Spare_WID                     ( 7)
+  #define DDRDATA3CH1_CR_DLLPITESTANDADC_Spare_MSK                     (0xFE000000)
+  #define DDRDATA3CH1_CR_DLLPITESTANDADC_Spare_MAX                     (0x0000007F)
+
+#define DDRDATA3CH1_CR_DDRCRDATAOFFSETCOMP_REG                       (0x0000075C)
+  #define DDRDATA3CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_OFF     ( 0)
+  #define DDRDATA3CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_WID     ( 6)
+  #define DDRDATA3CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MSK     (0x0000003F)
+  #define DDRDATA3CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MAX     (0x0000003F)
+  #define DDRDATA3CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_DEF     (0x00000000)
+  #define DDRDATA3CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_OFF   ( 6)
+  #define DDRDATA3CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_WID   ( 6)
+  #define DDRDATA3CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MSK   (0x00000FC0)
+  #define DDRDATA3CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MAX   (0x0000003F)
+  #define DDRDATA3CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_DEF   (0x00000000)
+  #define DDRDATA3CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_OFF     (12)
+  #define DDRDATA3CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_WID     ( 5)
+  #define DDRDATA3CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MSK     (0x0001F000)
+  #define DDRDATA3CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MAX     (0x0000001F)
+  #define DDRDATA3CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_DEF     (0x00000000)
+  #define DDRDATA3CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_OFF   (17)
+  #define DDRDATA3CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_WID   ( 5)
+  #define DDRDATA3CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MSK   (0x003E0000)
+  #define DDRDATA3CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MAX   (0x0000001F)
+  #define DDRDATA3CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_DEF   (0x00000000)
+  #define DDRDATA3CH1_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_OFF       (22)
+  #define DDRDATA3CH1_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_WID       ( 5)
+  #define DDRDATA3CH1_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_MSK       (0x07C00000)
+  #define DDRDATA3CH1_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_MAX       (0x0000001F)
+  #define DDRDATA3CH1_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_DEF       (0x00000000)
+  #define DDRDATA3CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_OFF  (27)
+  #define DDRDATA3CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_WID  ( 5)
+  #define DDRDATA3CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MSK  (0xF8000000)
+  #define DDRDATA3CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MAX  (0x0000001F)
+  #define DDRDATA3CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_DEF  (0x00000000)
+
+#define DDRDATA3CH1_CR_DDRCRDATACONTROL1_REG                         (0x00000760)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_RefPi_OFF                   ( 0)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_RefPi_WID                   ( 4)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_RefPi_MSK                   (0x0000000F)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_RefPi_MAX                   (0x0000000F)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_RefPi_DEF                   (0x00000000)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_DllMask_OFF                 ( 4)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_DllMask_WID                 ( 2)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_DllMask_MSK                 (0x00000030)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_DllMask_MAX                 (0x00000003)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_DllMask_DEF                 (0x00000000)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_DllWeakLock_OFF             ( 6)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_DllWeakLock_WID             ( 1)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_DllWeakLock_MSK             (0x00000040)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_DllWeakLock_MAX             (0x00000001)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_DllWeakLock_DEF             (0x00000000)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_OFF      ( 7)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_WID      ( 3)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MSK      (0x00000380)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MAX      (0x00000007)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_DEF      (0x00000000)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_OFF               (10)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_WID               ( 3)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_MSK               (0x00001C00)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_MAX               (0x00000007)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_DEF               (0x00000000)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_OdtDelay_OFF                (13)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_OdtDelay_WID                ( 4)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_OdtDelay_MSK                (0x0001E000)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_OdtDelay_MAX                (0x0000000F)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_OdtDelay_DEF                (0x00000000)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_OdtDuration_OFF             (17)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_OdtDuration_WID             ( 3)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_OdtDuration_MSK             (0x000E0000)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_OdtDuration_MAX             (0x00000007)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_OdtDuration_DEF             (0x00000000)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_OFF           (20)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_WID           ( 4)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_MSK           (0x00F00000)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_MAX           (0x0000000F)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_DEF           (0x00000000)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_OFF        (24)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_WID        ( 3)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_MSK        (0x07000000)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_MAX        (0x00000007)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_DEF        (0x00000000)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_BurstEndODTDelay_OFF        (27)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_BurstEndODTDelay_WID        ( 3)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_BurstEndODTDelay_MSK        (0x38000000)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_BurstEndODTDelay_MAX        (0x00000007)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_BurstEndODTDelay_DEF        (0x00000000)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_OFF          (30)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_WID          ( 1)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_MSK          (0x40000000)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_MAX          (0x00000001)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_DEF          (0x00000000)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_Rsvd1_OFF                   (31)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_Rsvd1_WID                   ( 1)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_Rsvd1_MSK                   (0x80000000)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_Rsvd1_MAX                   (0x00000001)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_Rsvd1_DEF                   (0x00000000)
+
+#define DDRDATA3CH1_CR_DDRCRDATACONTROL2_REG                         (0x00000764)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_OFF            ( 0)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_WID            ( 5)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_MSK            (0x0000001F)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_MAX            (0x0000001F)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_DEF            (0x00000000)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_OFF             ( 5)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_WID             ( 1)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_MSK             (0x00000020)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_MAX             (0x00000001)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_DEF             (0x00000000)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_ForceRxOn_OFF               ( 6)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_ForceRxOn_WID               ( 1)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_ForceRxOn_MSK               (0x00000040)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_ForceRxOn_MAX               (0x00000001)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_ForceRxOn_DEF               (0x00000000)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_LeakerComp_OFF              ( 7)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_LeakerComp_WID              ( 2)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_LeakerComp_MSK              (0x00000180)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_LeakerComp_MAX              (0x00000003)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_LeakerComp_DEF              (0x00000000)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_OFF          ( 9)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_WID          ( 4)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_MSK          (0x00001E00)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_MAX          (0x0000000F)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_DEF          (0x00000008)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_OFF             (13)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_WID             ( 5)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_MSK             (0x0003E000)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_MAX             (0x0000001F)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_DEF             (0x00000011)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_OFF             (18)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_WID             ( 1)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_MSK             (0x00040000)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_MAX             (0x00000001)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_DEF             (0x00000000)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_Spare_OFF                   (19)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_Spare_WID                   (13)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_Spare_MSK                   (0xFFF80000)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_Spare_MAX                   (0x00001FFF)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_Spare_DEF                   (0x00000000)
+
+#define DDRDATA3CH1_CR_DDRCRVSSHIORVREFCONTROL_REG                   (0x0000076C)
+  #define DDRDATA3CH1_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_OFF    ( 0)
+  #define DDRDATA3CH1_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_WID    (24)
+  #define DDRDATA3CH1_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_MSK    (0x00FFFFFF)
+  #define DDRDATA3CH1_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_MAX    (0x00FFFFFF)
+  #define DDRDATA3CH1_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_DEF    (0x00000000)
+  #define DDRDATA3CH1_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_OFF        (24)
+  #define DDRDATA3CH1_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_WID        ( 8)
+  #define DDRDATA3CH1_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_MSK        (0xFF000000)
+  #define DDRDATA3CH1_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_MAX        (0x000000FF)
+  #define DDRDATA3CH1_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_DEF        (0x00000000)
+
+#define DDRDATA3CH1_CR_DDRCRDATAOFFSETTRAIN_REG                      (0x00000770)
+  #define DDRDATA3CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_OFF          ( 0)
+  #define DDRDATA3CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_WID          ( 6)
+  #define DDRDATA3CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MSK          (0x0000003F)
+  #define DDRDATA3CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MAX          (0x0000003F)
+  #define DDRDATA3CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_DEF          (0x00000000)
+  #define DDRDATA3CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_OFF          ( 6)
+  #define DDRDATA3CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_WID          ( 6)
+  #define DDRDATA3CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MSK          (0x00000FC0)
+  #define DDRDATA3CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MAX          (0x0000003F)
+  #define DDRDATA3CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_DEF          (0x00000000)
+  #define DDRDATA3CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_OFF           (12)
+  #define DDRDATA3CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_WID           ( 6)
+  #define DDRDATA3CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MSK           (0x0003F000)
+  #define DDRDATA3CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MAX           (0x0000003F)
+  #define DDRDATA3CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_DEF           (0x00000000)
+  #define DDRDATA3CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_OFF          (18)
+  #define DDRDATA3CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_WID          ( 6)
+  #define DDRDATA3CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MSK          (0x00FC0000)
+  #define DDRDATA3CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MAX          (0x0000003F)
+  #define DDRDATA3CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_DEF          (0x00000000)
+  #define DDRDATA3CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_OFF           (24)
+  #define DDRDATA3CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_WID           ( 7)
+  #define DDRDATA3CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MSK           (0x7F000000)
+  #define DDRDATA3CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MAX           (0x0000007F)
+  #define DDRDATA3CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_DEF           (0x00000000)
+  #define DDRDATA3CH1_CR_DDRCRDATAOFFSETTRAIN_Spare_OFF                (31)
+  #define DDRDATA3CH1_CR_DDRCRDATAOFFSETTRAIN_Spare_WID                ( 1)
+  #define DDRDATA3CH1_CR_DDRCRDATAOFFSETTRAIN_Spare_MSK                (0x80000000)
+  #define DDRDATA3CH1_CR_DDRCRDATAOFFSETTRAIN_Spare_MAX                (0x00000001)
+  #define DDRDATA3CH1_CR_DDRCRDATAOFFSETTRAIN_Spare_DEF                (0x00000000)
+
+#define DDRDATA3CH1_CR_DDRCRDATACONTROL0_REG                         (0x00000774)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_OFF          ( 0)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_WID          ( 1)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_MSK          (0x00000001)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_MAX          (0x00000001)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_DEF          (0x00000000)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_OFF          ( 1)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_WID          ( 1)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_MSK          (0x00000002)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_MAX          (0x00000001)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_DEF          (0x00000000)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_OFF          ( 2)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_WID          ( 1)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_MSK          (0x00000004)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_MAX          (0x00000001)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_DEF          (0x00000000)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_OFF    ( 3)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_WID    ( 1)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MSK    (0x00000008)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MAX    (0x00000001)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_DEF    (0x00000000)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_TxOn_OFF                    ( 4)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_TxOn_WID                    ( 1)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_TxOn_MSK                    (0x00000010)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_TxOn_MAX                    (0x00000001)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_TxOn_DEF                    (0x00000000)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RfOn_OFF                    ( 5)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RfOn_WID                    ( 1)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RfOn_MSK                    (0x00000020)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RfOn_MAX                    (0x00000001)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RfOn_DEF                    (0x00000000)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RxPiOn_OFF                  ( 6)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RxPiOn_WID                  ( 1)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RxPiOn_MSK                  (0x00000040)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RxPiOn_MAX                  (0x00000001)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RxPiOn_DEF                  (0x00000000)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_TxPiOn_OFF                  ( 7)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_TxPiOn_WID                  ( 1)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_TxPiOn_MSK                  (0x00000080)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_TxPiOn_MAX                  (0x00000001)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_TxPiOn_DEF                  (0x00000000)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_OFF        ( 8)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_WID        ( 1)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_MSK        (0x00000100)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_MAX        (0x00000001)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_DEF        (0x00000000)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_OFF        ( 9)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_WID        ( 1)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MSK        (0x00000200)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MAX        (0x00000001)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_DEF        (0x00000000)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_TxDisable_OFF               (10)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_TxDisable_WID               ( 1)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_TxDisable_MSK               (0x00000400)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_TxDisable_MAX               (0x00000001)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_TxDisable_DEF               (0x00000000)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RxDisable_OFF               (11)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RxDisable_WID               ( 1)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RxDisable_MSK               (0x00000800)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RxDisable_MAX               (0x00000001)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RxDisable_DEF               (0x00000000)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_TxLong_OFF                  (12)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_TxLong_WID                  ( 1)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_TxLong_MSK                  (0x00001000)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_TxLong_MAX                  (0x00000001)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_TxLong_DEF                  (0x00000000)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_OFF               (13)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_WID               ( 2)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_MSK               (0x00006000)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_MAX               (0x00000003)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_DEF               (0x00000000)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RxReadPointer_OFF           (15)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RxReadPointer_WID           ( 3)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RxReadPointer_MSK           (0x00038000)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RxReadPointer_MAX           (0x00000007)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RxReadPointer_DEF           (0x00000000)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_DriverSegmentEnable_OFF     (18)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_DriverSegmentEnable_WID     ( 1)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_DriverSegmentEnable_MSK     (0x00040000)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_DriverSegmentEnable_MAX     (0x00000001)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_DriverSegmentEnable_DEF     (0x00000000)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_DataVccddqHi_OFF            (19)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_DataVccddqHi_WID            ( 1)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_DataVccddqHi_MSK            (0x00080000)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_DataVccddqHi_MAX            (0x00000001)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_DataVccddqHi_DEF            (0x00000000)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_ReadRFRd_OFF                (20)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_ReadRFRd_WID                ( 1)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_ReadRFRd_MSK                (0x00100000)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_ReadRFRd_MAX                (0x00000001)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_ReadRFRd_DEF                (0x00000000)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_ReadRFWr_OFF                (21)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_ReadRFWr_WID                ( 1)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_ReadRFWr_MSK                (0x00200000)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_ReadRFWr_MAX                (0x00000001)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_ReadRFWr_DEF                (0x00000000)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_ReadRFRank_OFF              (22)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_ReadRFRank_WID              ( 2)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_ReadRFRank_MSK              (0x00C00000)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_ReadRFRank_MAX              (0x00000003)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_ReadRFRank_DEF              (0x00000000)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_OFF              (24)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_WID              ( 1)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_MSK              (0x01000000)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_MAX              (0x00000001)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_DEF              (0x00000000)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_OdtSampOff_OFF              (25)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_OdtSampOff_WID              ( 1)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_OdtSampOff_MSK              (0x02000000)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_OdtSampOff_MAX              (0x00000001)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_OdtSampOff_DEF              (0x00000000)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_OFF        (26)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_WID        ( 1)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_MSK        (0x04000000)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_MAX        (0x00000001)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_DEF        (0x00000000)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_OFF         (27)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_WID         ( 1)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MSK         (0x08000000)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MAX         (0x00000001)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_DEF         (0x00000000)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_OFF              (28)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_WID              ( 1)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_MSK              (0x10000000)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_MAX              (0x00000001)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_DEF              (0x00000000)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_EnReadPreamble_OFF          (29)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_EnReadPreamble_WID          ( 1)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_EnReadPreamble_MSK          (0x20000000)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_EnReadPreamble_MAX          (0x00000001)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_EnReadPreamble_DEF          (0x00000000)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_OFF         (30)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_WID         ( 1)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MSK         (0x40000000)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MAX         (0x00000001)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_DEF         (0x00000000)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_OFF            (31)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_WID            ( 1)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_MSK            (0x80000000)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_MAX            (0x00000001)
+  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_DEF            (0x00000000)
+
+#define DDRDATA3CH1_CR_DDRCRVREFADJUST1_REG                          (0x00000778)
+  #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_CAVrefCtl_OFF                ( 0)
+  #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_CAVrefCtl_WID                ( 7)
+  #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_CAVrefCtl_MSK                (0x0000007F)
+  #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_CAVrefCtl_MAX                (0x0000007F)
+  #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_CAVrefCtl_DEF                (0x00000000)
+  #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_Ch1VrefCtl_OFF               ( 7)
+  #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_Ch1VrefCtl_WID               ( 7)
+  #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_Ch1VrefCtl_MSK               (0x00003F80)
+  #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_Ch1VrefCtl_MAX               (0x0000007F)
+  #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_Ch1VrefCtl_DEF               (0x00000000)
+  #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_Ch0VrefCtl_OFF               (14)
+  #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_Ch0VrefCtl_WID               ( 7)
+  #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_Ch0VrefCtl_MSK               (0x001FC000)
+  #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_Ch0VrefCtl_MAX               (0x0000007F)
+  #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_Ch0VrefCtl_DEF               (0x00000000)
+  #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCA_OFF             (21)
+  #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCA_WID             ( 1)
+  #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCA_MSK             (0x00200000)
+  #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCA_MAX             (0x00000001)
+  #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCA_DEF             (0x00000000)
+  #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_OFF            (22)
+  #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_WID            ( 1)
+  #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_MSK            (0x00400000)
+  #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_MAX            (0x00000001)
+  #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_DEF            (0x00000000)
+  #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_OFF            (23)
+  #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_WID            ( 1)
+  #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_MSK            (0x00800000)
+  #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_MAX            (0x00000001)
+  #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_DEF            (0x00000000)
+  #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_HiZTimerCtrl_OFF             (24)
+  #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_HiZTimerCtrl_WID             ( 2)
+  #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_HiZTimerCtrl_MSK             (0x03000000)
+  #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_HiZTimerCtrl_MAX             (0x00000003)
+  #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_HiZTimerCtrl_DEF             (0x00000000)
+  #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_OFF            (26)
+  #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_WID            ( 1)
+  #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_MSK            (0x04000000)
+  #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_MAX            (0x00000001)
+  #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_DEF            (0x00000000)
+  #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_Rsvd_OFF                     (27)
+  #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_Rsvd_WID                     ( 2)
+  #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_Rsvd_MSK                     (0x18000000)
+  #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_Rsvd_MAX                     (0x00000003)
+  #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_Rsvd_DEF                     (0x00000000)
+  #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_caSlowBW_OFF                 (29)
+  #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_caSlowBW_WID                 ( 1)
+  #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_caSlowBW_MSK                 (0x20000000)
+  #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_caSlowBW_MAX                 (0x00000001)
+  #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_caSlowBW_DEF                 (0x00000000)
+  #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_ch0SlowBW_OFF                (30)
+  #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_ch0SlowBW_WID                ( 1)
+  #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_ch0SlowBW_MSK                (0x40000000)
+  #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_ch0SlowBW_MAX                (0x00000001)
+  #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_ch0SlowBW_DEF                (0x00000000)
+  #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_ch1SlowBW_OFF                (31)
+  #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_ch1SlowBW_WID                ( 1)
+  #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_ch1SlowBW_MSK                (0x80000000)
+  #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_ch1SlowBW_MAX                (0x00000001)
+  #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_ch1SlowBW_DEF                (0x00000000)
+
+#define DDRDATA4CH0_CR_RXTRAINRANK0_REG                              (0x00000800)
+  #define DDRDATA4CH0_CR_RXTRAINRANK0_RxRcvEnPi_OFF                    ( 0)
+  #define DDRDATA4CH0_CR_RXTRAINRANK0_RxRcvEnPi_WID                    ( 9)
+  #define DDRDATA4CH0_CR_RXTRAINRANK0_RxRcvEnPi_MSK                    (0x000001FF)
+  #define DDRDATA4CH0_CR_RXTRAINRANK0_RxRcvEnPi_MAX                    (0x000001FF)
+  #define DDRDATA4CH0_CR_RXTRAINRANK0_RxDqsPPi_OFF                     ( 9)
+  #define DDRDATA4CH0_CR_RXTRAINRANK0_RxDqsPPi_WID                     ( 6)
+  #define DDRDATA4CH0_CR_RXTRAINRANK0_RxDqsPPi_MSK                     (0x00007E00)
+  #define DDRDATA4CH0_CR_RXTRAINRANK0_RxDqsPPi_MAX                     (0x0000003F)
+  #define DDRDATA4CH0_CR_RXTRAINRANK0_RxEq_OFF                         (15)
+  #define DDRDATA4CH0_CR_RXTRAINRANK0_RxEq_WID                         ( 5)
+  #define DDRDATA4CH0_CR_RXTRAINRANK0_RxEq_MSK                         (0x000F8000)
+  #define DDRDATA4CH0_CR_RXTRAINRANK0_RxEq_MAX                         (0x0000001F)
+  #define DDRDATA4CH0_CR_RXTRAINRANK0_RxDqsNPi_OFF                     (20)
+  #define DDRDATA4CH0_CR_RXTRAINRANK0_RxDqsNPi_WID                     ( 6)
+  #define DDRDATA4CH0_CR_RXTRAINRANK0_RxDqsNPi_MSK                     (0x03F00000)
+  #define DDRDATA4CH0_CR_RXTRAINRANK0_RxDqsNPi_MAX                     (0x0000003F)
+  #define DDRDATA4CH0_CR_RXTRAINRANK0_RxVref_OFF                       (26)
+  #define DDRDATA4CH0_CR_RXTRAINRANK0_RxVref_WID                       ( 6)
+  #define DDRDATA4CH0_CR_RXTRAINRANK0_RxVref_MSK                       (0xFC000000)
+  #define DDRDATA4CH0_CR_RXTRAINRANK0_RxVref_MAX                       (0x0000003F)
+
+#define DDRDATA4CH0_CR_RXTRAINRANK1_REG                              (0x00000804)
+  #define DDRDATA4CH0_CR_RXTRAINRANK1_RxRcvEnPi_OFF                    ( 0)
+  #define DDRDATA4CH0_CR_RXTRAINRANK1_RxRcvEnPi_WID                    ( 9)
+  #define DDRDATA4CH0_CR_RXTRAINRANK1_RxRcvEnPi_MSK                    (0x000001FF)
+  #define DDRDATA4CH0_CR_RXTRAINRANK1_RxRcvEnPi_MAX                    (0x000001FF)
+  #define DDRDATA4CH0_CR_RXTRAINRANK1_RxDqsPPi_OFF                     ( 9)
+  #define DDRDATA4CH0_CR_RXTRAINRANK1_RxDqsPPi_WID                     ( 6)
+  #define DDRDATA4CH0_CR_RXTRAINRANK1_RxDqsPPi_MSK                     (0x00007E00)
+  #define DDRDATA4CH0_CR_RXTRAINRANK1_RxDqsPPi_MAX                     (0x0000003F)
+  #define DDRDATA4CH0_CR_RXTRAINRANK1_RxEq_OFF                         (15)
+  #define DDRDATA4CH0_CR_RXTRAINRANK1_RxEq_WID                         ( 5)
+  #define DDRDATA4CH0_CR_RXTRAINRANK1_RxEq_MSK                         (0x000F8000)
+  #define DDRDATA4CH0_CR_RXTRAINRANK1_RxEq_MAX                         (0x0000001F)
+  #define DDRDATA4CH0_CR_RXTRAINRANK1_RxDqsNPi_OFF                     (20)
+  #define DDRDATA4CH0_CR_RXTRAINRANK1_RxDqsNPi_WID                     ( 6)
+  #define DDRDATA4CH0_CR_RXTRAINRANK1_RxDqsNPi_MSK                     (0x03F00000)
+  #define DDRDATA4CH0_CR_RXTRAINRANK1_RxDqsNPi_MAX                     (0x0000003F)
+  #define DDRDATA4CH0_CR_RXTRAINRANK1_RxVref_OFF                       (26)
+  #define DDRDATA4CH0_CR_RXTRAINRANK1_RxVref_WID                       ( 6)
+  #define DDRDATA4CH0_CR_RXTRAINRANK1_RxVref_MSK                       (0xFC000000)
+  #define DDRDATA4CH0_CR_RXTRAINRANK1_RxVref_MAX                       (0x0000003F)
+
+#define DDRDATA4CH0_CR_RXTRAINRANK2_REG                              (0x00000808)
+  #define DDRDATA4CH0_CR_RXTRAINRANK2_RxRcvEnPi_OFF                    ( 0)
+  #define DDRDATA4CH0_CR_RXTRAINRANK2_RxRcvEnPi_WID                    ( 9)
+  #define DDRDATA4CH0_CR_RXTRAINRANK2_RxRcvEnPi_MSK                    (0x000001FF)
+  #define DDRDATA4CH0_CR_RXTRAINRANK2_RxRcvEnPi_MAX                    (0x000001FF)
+  #define DDRDATA4CH0_CR_RXTRAINRANK2_RxDqsPPi_OFF                     ( 9)
+  #define DDRDATA4CH0_CR_RXTRAINRANK2_RxDqsPPi_WID                     ( 6)
+  #define DDRDATA4CH0_CR_RXTRAINRANK2_RxDqsPPi_MSK                     (0x00007E00)
+  #define DDRDATA4CH0_CR_RXTRAINRANK2_RxDqsPPi_MAX                     (0x0000003F)
+  #define DDRDATA4CH0_CR_RXTRAINRANK2_RxEq_OFF                         (15)
+  #define DDRDATA4CH0_CR_RXTRAINRANK2_RxEq_WID                         ( 5)
+  #define DDRDATA4CH0_CR_RXTRAINRANK2_RxEq_MSK                         (0x000F8000)
+  #define DDRDATA4CH0_CR_RXTRAINRANK2_RxEq_MAX                         (0x0000001F)
+  #define DDRDATA4CH0_CR_RXTRAINRANK2_RxDqsNPi_OFF                     (20)
+  #define DDRDATA4CH0_CR_RXTRAINRANK2_RxDqsNPi_WID                     ( 6)
+  #define DDRDATA4CH0_CR_RXTRAINRANK2_RxDqsNPi_MSK                     (0x03F00000)
+  #define DDRDATA4CH0_CR_RXTRAINRANK2_RxDqsNPi_MAX                     (0x0000003F)
+  #define DDRDATA4CH0_CR_RXTRAINRANK2_RxVref_OFF                       (26)
+  #define DDRDATA4CH0_CR_RXTRAINRANK2_RxVref_WID                       ( 6)
+  #define DDRDATA4CH0_CR_RXTRAINRANK2_RxVref_MSK                       (0xFC000000)
+  #define DDRDATA4CH0_CR_RXTRAINRANK2_RxVref_MAX                       (0x0000003F)
+
+#define DDRDATA4CH0_CR_RXTRAINRANK3_REG                              (0x0000080C)
+  #define DDRDATA4CH0_CR_RXTRAINRANK3_RxRcvEnPi_OFF                    ( 0)
+  #define DDRDATA4CH0_CR_RXTRAINRANK3_RxRcvEnPi_WID                    ( 9)
+  #define DDRDATA4CH0_CR_RXTRAINRANK3_RxRcvEnPi_MSK                    (0x000001FF)
+  #define DDRDATA4CH0_CR_RXTRAINRANK3_RxRcvEnPi_MAX                    (0x000001FF)
+  #define DDRDATA4CH0_CR_RXTRAINRANK3_RxDqsPPi_OFF                     ( 9)
+  #define DDRDATA4CH0_CR_RXTRAINRANK3_RxDqsPPi_WID                     ( 6)
+  #define DDRDATA4CH0_CR_RXTRAINRANK3_RxDqsPPi_MSK                     (0x00007E00)
+  #define DDRDATA4CH0_CR_RXTRAINRANK3_RxDqsPPi_MAX                     (0x0000003F)
+  #define DDRDATA4CH0_CR_RXTRAINRANK3_RxEq_OFF                         (15)
+  #define DDRDATA4CH0_CR_RXTRAINRANK3_RxEq_WID                         ( 5)
+  #define DDRDATA4CH0_CR_RXTRAINRANK3_RxEq_MSK                         (0x000F8000)
+  #define DDRDATA4CH0_CR_RXTRAINRANK3_RxEq_MAX                         (0x0000001F)
+  #define DDRDATA4CH0_CR_RXTRAINRANK3_RxDqsNPi_OFF                     (20)
+  #define DDRDATA4CH0_CR_RXTRAINRANK3_RxDqsNPi_WID                     ( 6)
+  #define DDRDATA4CH0_CR_RXTRAINRANK3_RxDqsNPi_MSK                     (0x03F00000)
+  #define DDRDATA4CH0_CR_RXTRAINRANK3_RxDqsNPi_MAX                     (0x0000003F)
+  #define DDRDATA4CH0_CR_RXTRAINRANK3_RxVref_OFF                       (26)
+  #define DDRDATA4CH0_CR_RXTRAINRANK3_RxVref_WID                       ( 6)
+  #define DDRDATA4CH0_CR_RXTRAINRANK3_RxVref_MSK                       (0xFC000000)
+  #define DDRDATA4CH0_CR_RXTRAINRANK3_RxVref_MAX                       (0x0000003F)
+
+#define DDRDATA4CH0_CR_RXPERBITRANK0_REG                             (0x00000810)
+  #define DDRDATA4CH0_CR_RXPERBITRANK0_Lane0_OFF                       ( 0)
+  #define DDRDATA4CH0_CR_RXPERBITRANK0_Lane0_WID                       ( 4)
+  #define DDRDATA4CH0_CR_RXPERBITRANK0_Lane0_MSK                       (0x0000000F)
+  #define DDRDATA4CH0_CR_RXPERBITRANK0_Lane0_MAX                       (0x0000000F)
+  #define DDRDATA4CH0_CR_RXPERBITRANK0_Lane1_OFF                       ( 4)
+  #define DDRDATA4CH0_CR_RXPERBITRANK0_Lane1_WID                       ( 4)
+  #define DDRDATA4CH0_CR_RXPERBITRANK0_Lane1_MSK                       (0x000000F0)
+  #define DDRDATA4CH0_CR_RXPERBITRANK0_Lane1_MAX                       (0x0000000F)
+  #define DDRDATA4CH0_CR_RXPERBITRANK0_Lane2_OFF                       ( 8)
+  #define DDRDATA4CH0_CR_RXPERBITRANK0_Lane2_WID                       ( 4)
+  #define DDRDATA4CH0_CR_RXPERBITRANK0_Lane2_MSK                       (0x00000F00)
+  #define DDRDATA4CH0_CR_RXPERBITRANK0_Lane2_MAX                       (0x0000000F)
+  #define DDRDATA4CH0_CR_RXPERBITRANK0_Lane3_OFF                       (12)
+  #define DDRDATA4CH0_CR_RXPERBITRANK0_Lane3_WID                       ( 4)
+  #define DDRDATA4CH0_CR_RXPERBITRANK0_Lane3_MSK                       (0x0000F000)
+  #define DDRDATA4CH0_CR_RXPERBITRANK0_Lane3_MAX                       (0x0000000F)
+  #define DDRDATA4CH0_CR_RXPERBITRANK0_Lane4_OFF                       (16)
+  #define DDRDATA4CH0_CR_RXPERBITRANK0_Lane4_WID                       ( 4)
+  #define DDRDATA4CH0_CR_RXPERBITRANK0_Lane4_MSK                       (0x000F0000)
+  #define DDRDATA4CH0_CR_RXPERBITRANK0_Lane4_MAX                       (0x0000000F)
+  #define DDRDATA4CH0_CR_RXPERBITRANK0_Lane5_OFF                       (20)
+  #define DDRDATA4CH0_CR_RXPERBITRANK0_Lane5_WID                       ( 4)
+  #define DDRDATA4CH0_CR_RXPERBITRANK0_Lane5_MSK                       (0x00F00000)
+  #define DDRDATA4CH0_CR_RXPERBITRANK0_Lane5_MAX                       (0x0000000F)
+  #define DDRDATA4CH0_CR_RXPERBITRANK0_Lane6_OFF                       (24)
+  #define DDRDATA4CH0_CR_RXPERBITRANK0_Lane6_WID                       ( 4)
+  #define DDRDATA4CH0_CR_RXPERBITRANK0_Lane6_MSK                       (0x0F000000)
+  #define DDRDATA4CH0_CR_RXPERBITRANK0_Lane6_MAX                       (0x0000000F)
+  #define DDRDATA4CH0_CR_RXPERBITRANK0_Lane7_OFF                       (28)
+  #define DDRDATA4CH0_CR_RXPERBITRANK0_Lane7_WID                       ( 4)
+  #define DDRDATA4CH0_CR_RXPERBITRANK0_Lane7_MSK                       (0xF0000000)
+  #define DDRDATA4CH0_CR_RXPERBITRANK0_Lane7_MAX                       (0x0000000F)
+
+#define DDRDATA4CH0_CR_RXPERBITRANK1_REG                             (0x00000814)
+  #define DDRDATA4CH0_CR_RXPERBITRANK1_Lane0_OFF                       ( 0)
+  #define DDRDATA4CH0_CR_RXPERBITRANK1_Lane0_WID                       ( 4)
+  #define DDRDATA4CH0_CR_RXPERBITRANK1_Lane0_MSK                       (0x0000000F)
+  #define DDRDATA4CH0_CR_RXPERBITRANK1_Lane0_MAX                       (0x0000000F)
+  #define DDRDATA4CH0_CR_RXPERBITRANK1_Lane1_OFF                       ( 4)
+  #define DDRDATA4CH0_CR_RXPERBITRANK1_Lane1_WID                       ( 4)
+  #define DDRDATA4CH0_CR_RXPERBITRANK1_Lane1_MSK                       (0x000000F0)
+  #define DDRDATA4CH0_CR_RXPERBITRANK1_Lane1_MAX                       (0x0000000F)
+  #define DDRDATA4CH0_CR_RXPERBITRANK1_Lane2_OFF                       ( 8)
+  #define DDRDATA4CH0_CR_RXPERBITRANK1_Lane2_WID                       ( 4)
+  #define DDRDATA4CH0_CR_RXPERBITRANK1_Lane2_MSK                       (0x00000F00)
+  #define DDRDATA4CH0_CR_RXPERBITRANK1_Lane2_MAX                       (0x0000000F)
+  #define DDRDATA4CH0_CR_RXPERBITRANK1_Lane3_OFF                       (12)
+  #define DDRDATA4CH0_CR_RXPERBITRANK1_Lane3_WID                       ( 4)
+  #define DDRDATA4CH0_CR_RXPERBITRANK1_Lane3_MSK                       (0x0000F000)
+  #define DDRDATA4CH0_CR_RXPERBITRANK1_Lane3_MAX                       (0x0000000F)
+  #define DDRDATA4CH0_CR_RXPERBITRANK1_Lane4_OFF                       (16)
+  #define DDRDATA4CH0_CR_RXPERBITRANK1_Lane4_WID                       ( 4)
+  #define DDRDATA4CH0_CR_RXPERBITRANK1_Lane4_MSK                       (0x000F0000)
+  #define DDRDATA4CH0_CR_RXPERBITRANK1_Lane4_MAX                       (0x0000000F)
+  #define DDRDATA4CH0_CR_RXPERBITRANK1_Lane5_OFF                       (20)
+  #define DDRDATA4CH0_CR_RXPERBITRANK1_Lane5_WID                       ( 4)
+  #define DDRDATA4CH0_CR_RXPERBITRANK1_Lane5_MSK                       (0x00F00000)
+  #define DDRDATA4CH0_CR_RXPERBITRANK1_Lane5_MAX                       (0x0000000F)
+  #define DDRDATA4CH0_CR_RXPERBITRANK1_Lane6_OFF                       (24)
+  #define DDRDATA4CH0_CR_RXPERBITRANK1_Lane6_WID                       ( 4)
+  #define DDRDATA4CH0_CR_RXPERBITRANK1_Lane6_MSK                       (0x0F000000)
+  #define DDRDATA4CH0_CR_RXPERBITRANK1_Lane6_MAX                       (0x0000000F)
+  #define DDRDATA4CH0_CR_RXPERBITRANK1_Lane7_OFF                       (28)
+  #define DDRDATA4CH0_CR_RXPERBITRANK1_Lane7_WID                       ( 4)
+  #define DDRDATA4CH0_CR_RXPERBITRANK1_Lane7_MSK                       (0xF0000000)
+  #define DDRDATA4CH0_CR_RXPERBITRANK1_Lane7_MAX                       (0x0000000F)
+
+#define DDRDATA4CH0_CR_RXPERBITRANK2_REG                             (0x00000818)
+  #define DDRDATA4CH0_CR_RXPERBITRANK2_Lane0_OFF                       ( 0)
+  #define DDRDATA4CH0_CR_RXPERBITRANK2_Lane0_WID                       ( 4)
+  #define DDRDATA4CH0_CR_RXPERBITRANK2_Lane0_MSK                       (0x0000000F)
+  #define DDRDATA4CH0_CR_RXPERBITRANK2_Lane0_MAX                       (0x0000000F)
+  #define DDRDATA4CH0_CR_RXPERBITRANK2_Lane1_OFF                       ( 4)
+  #define DDRDATA4CH0_CR_RXPERBITRANK2_Lane1_WID                       ( 4)
+  #define DDRDATA4CH0_CR_RXPERBITRANK2_Lane1_MSK                       (0x000000F0)
+  #define DDRDATA4CH0_CR_RXPERBITRANK2_Lane1_MAX                       (0x0000000F)
+  #define DDRDATA4CH0_CR_RXPERBITRANK2_Lane2_OFF                       ( 8)
+  #define DDRDATA4CH0_CR_RXPERBITRANK2_Lane2_WID                       ( 4)
+  #define DDRDATA4CH0_CR_RXPERBITRANK2_Lane2_MSK                       (0x00000F00)
+  #define DDRDATA4CH0_CR_RXPERBITRANK2_Lane2_MAX                       (0x0000000F)
+  #define DDRDATA4CH0_CR_RXPERBITRANK2_Lane3_OFF                       (12)
+  #define DDRDATA4CH0_CR_RXPERBITRANK2_Lane3_WID                       ( 4)
+  #define DDRDATA4CH0_CR_RXPERBITRANK2_Lane3_MSK                       (0x0000F000)
+  #define DDRDATA4CH0_CR_RXPERBITRANK2_Lane3_MAX                       (0x0000000F)
+  #define DDRDATA4CH0_CR_RXPERBITRANK2_Lane4_OFF                       (16)
+  #define DDRDATA4CH0_CR_RXPERBITRANK2_Lane4_WID                       ( 4)
+  #define DDRDATA4CH0_CR_RXPERBITRANK2_Lane4_MSK                       (0x000F0000)
+  #define DDRDATA4CH0_CR_RXPERBITRANK2_Lane4_MAX                       (0x0000000F)
+  #define DDRDATA4CH0_CR_RXPERBITRANK2_Lane5_OFF                       (20)
+  #define DDRDATA4CH0_CR_RXPERBITRANK2_Lane5_WID                       ( 4)
+  #define DDRDATA4CH0_CR_RXPERBITRANK2_Lane5_MSK                       (0x00F00000)
+  #define DDRDATA4CH0_CR_RXPERBITRANK2_Lane5_MAX                       (0x0000000F)
+  #define DDRDATA4CH0_CR_RXPERBITRANK2_Lane6_OFF                       (24)
+  #define DDRDATA4CH0_CR_RXPERBITRANK2_Lane6_WID                       ( 4)
+  #define DDRDATA4CH0_CR_RXPERBITRANK2_Lane6_MSK                       (0x0F000000)
+  #define DDRDATA4CH0_CR_RXPERBITRANK2_Lane6_MAX                       (0x0000000F)
+  #define DDRDATA4CH0_CR_RXPERBITRANK2_Lane7_OFF                       (28)
+  #define DDRDATA4CH0_CR_RXPERBITRANK2_Lane7_WID                       ( 4)
+  #define DDRDATA4CH0_CR_RXPERBITRANK2_Lane7_MSK                       (0xF0000000)
+  #define DDRDATA4CH0_CR_RXPERBITRANK2_Lane7_MAX                       (0x0000000F)
+
+#define DDRDATA4CH0_CR_RXPERBITRANK3_REG                             (0x0000081C)
+  #define DDRDATA4CH0_CR_RXPERBITRANK3_Lane0_OFF                       ( 0)
+  #define DDRDATA4CH0_CR_RXPERBITRANK3_Lane0_WID                       ( 4)
+  #define DDRDATA4CH0_CR_RXPERBITRANK3_Lane0_MSK                       (0x0000000F)
+  #define DDRDATA4CH0_CR_RXPERBITRANK3_Lane0_MAX                       (0x0000000F)
+  #define DDRDATA4CH0_CR_RXPERBITRANK3_Lane1_OFF                       ( 4)
+  #define DDRDATA4CH0_CR_RXPERBITRANK3_Lane1_WID                       ( 4)
+  #define DDRDATA4CH0_CR_RXPERBITRANK3_Lane1_MSK                       (0x000000F0)
+  #define DDRDATA4CH0_CR_RXPERBITRANK3_Lane1_MAX                       (0x0000000F)
+  #define DDRDATA4CH0_CR_RXPERBITRANK3_Lane2_OFF                       ( 8)
+  #define DDRDATA4CH0_CR_RXPERBITRANK3_Lane2_WID                       ( 4)
+  #define DDRDATA4CH0_CR_RXPERBITRANK3_Lane2_MSK                       (0x00000F00)
+  #define DDRDATA4CH0_CR_RXPERBITRANK3_Lane2_MAX                       (0x0000000F)
+  #define DDRDATA4CH0_CR_RXPERBITRANK3_Lane3_OFF                       (12)
+  #define DDRDATA4CH0_CR_RXPERBITRANK3_Lane3_WID                       ( 4)
+  #define DDRDATA4CH0_CR_RXPERBITRANK3_Lane3_MSK                       (0x0000F000)
+  #define DDRDATA4CH0_CR_RXPERBITRANK3_Lane3_MAX                       (0x0000000F)
+  #define DDRDATA4CH0_CR_RXPERBITRANK3_Lane4_OFF                       (16)
+  #define DDRDATA4CH0_CR_RXPERBITRANK3_Lane4_WID                       ( 4)
+  #define DDRDATA4CH0_CR_RXPERBITRANK3_Lane4_MSK                       (0x000F0000)
+  #define DDRDATA4CH0_CR_RXPERBITRANK3_Lane4_MAX                       (0x0000000F)
+  #define DDRDATA4CH0_CR_RXPERBITRANK3_Lane5_OFF                       (20)
+  #define DDRDATA4CH0_CR_RXPERBITRANK3_Lane5_WID                       ( 4)
+  #define DDRDATA4CH0_CR_RXPERBITRANK3_Lane5_MSK                       (0x00F00000)
+  #define DDRDATA4CH0_CR_RXPERBITRANK3_Lane5_MAX                       (0x0000000F)
+  #define DDRDATA4CH0_CR_RXPERBITRANK3_Lane6_OFF                       (24)
+  #define DDRDATA4CH0_CR_RXPERBITRANK3_Lane6_WID                       ( 4)
+  #define DDRDATA4CH0_CR_RXPERBITRANK3_Lane6_MSK                       (0x0F000000)
+  #define DDRDATA4CH0_CR_RXPERBITRANK3_Lane6_MAX                       (0x0000000F)
+  #define DDRDATA4CH0_CR_RXPERBITRANK3_Lane7_OFF                       (28)
+  #define DDRDATA4CH0_CR_RXPERBITRANK3_Lane7_WID                       ( 4)
+  #define DDRDATA4CH0_CR_RXPERBITRANK3_Lane7_MSK                       (0xF0000000)
+  #define DDRDATA4CH0_CR_RXPERBITRANK3_Lane7_MAX                       (0x0000000F)
+
+#define DDRDATA4CH0_CR_TXTRAINRANK0_REG                              (0x00000820)
+  #define DDRDATA4CH0_CR_TXTRAINRANK0_TxDqDelay_OFF                    ( 0)
+  #define DDRDATA4CH0_CR_TXTRAINRANK0_TxDqDelay_WID                    ( 9)
+  #define DDRDATA4CH0_CR_TXTRAINRANK0_TxDqDelay_MSK                    (0x000001FF)
+  #define DDRDATA4CH0_CR_TXTRAINRANK0_TxDqDelay_MAX                    (0x000001FF)
+  #define DDRDATA4CH0_CR_TXTRAINRANK0_TxDqsDelay_OFF                   ( 9)
+  #define DDRDATA4CH0_CR_TXTRAINRANK0_TxDqsDelay_WID                   ( 9)
+  #define DDRDATA4CH0_CR_TXTRAINRANK0_TxDqsDelay_MSK                   (0x0003FE00)
+  #define DDRDATA4CH0_CR_TXTRAINRANK0_TxDqsDelay_MAX                   (0x000001FF)
+  #define DDRDATA4CH0_CR_TXTRAINRANK0_Spare0_OFF                       (18)
+  #define DDRDATA4CH0_CR_TXTRAINRANK0_Spare0_WID                       ( 2)
+  #define DDRDATA4CH0_CR_TXTRAINRANK0_Spare0_MSK                       (0x000C0000)
+  #define DDRDATA4CH0_CR_TXTRAINRANK0_Spare0_MAX                       (0x00000003)
+  #define DDRDATA4CH0_CR_TXTRAINRANK0_TxEqualization_OFF               (20)
+  #define DDRDATA4CH0_CR_TXTRAINRANK0_TxEqualization_WID               ( 6)
+  #define DDRDATA4CH0_CR_TXTRAINRANK0_TxEqualization_MSK               (0x03F00000)
+  #define DDRDATA4CH0_CR_TXTRAINRANK0_TxEqualization_MAX               (0x0000003F)
+  #define DDRDATA4CH0_CR_TXTRAINRANK0_Spare1_OFF                       (26)
+  #define DDRDATA4CH0_CR_TXTRAINRANK0_Spare1_WID                       ( 6)
+  #define DDRDATA4CH0_CR_TXTRAINRANK0_Spare1_MSK                       (0xFC000000)
+  #define DDRDATA4CH0_CR_TXTRAINRANK0_Spare1_MAX                       (0x0000003F)
+
+#define DDRDATA4CH0_CR_TXTRAINRANK1_REG                              (0x00000824)
+  #define DDRDATA4CH0_CR_TXTRAINRANK1_TxDqDelay_OFF                    ( 0)
+  #define DDRDATA4CH0_CR_TXTRAINRANK1_TxDqDelay_WID                    ( 9)
+  #define DDRDATA4CH0_CR_TXTRAINRANK1_TxDqDelay_MSK                    (0x000001FF)
+  #define DDRDATA4CH0_CR_TXTRAINRANK1_TxDqDelay_MAX                    (0x000001FF)
+  #define DDRDATA4CH0_CR_TXTRAINRANK1_TxDqsDelay_OFF                   ( 9)
+  #define DDRDATA4CH0_CR_TXTRAINRANK1_TxDqsDelay_WID                   ( 9)
+  #define DDRDATA4CH0_CR_TXTRAINRANK1_TxDqsDelay_MSK                   (0x0003FE00)
+  #define DDRDATA4CH0_CR_TXTRAINRANK1_TxDqsDelay_MAX                   (0x000001FF)
+  #define DDRDATA4CH0_CR_TXTRAINRANK1_Spare0_OFF                       (18)
+  #define DDRDATA4CH0_CR_TXTRAINRANK1_Spare0_WID                       ( 2)
+  #define DDRDATA4CH0_CR_TXTRAINRANK1_Spare0_MSK                       (0x000C0000)
+  #define DDRDATA4CH0_CR_TXTRAINRANK1_Spare0_MAX                       (0x00000003)
+  #define DDRDATA4CH0_CR_TXTRAINRANK1_TxEqualization_OFF               (20)
+  #define DDRDATA4CH0_CR_TXTRAINRANK1_TxEqualization_WID               ( 6)
+  #define DDRDATA4CH0_CR_TXTRAINRANK1_TxEqualization_MSK               (0x03F00000)
+  #define DDRDATA4CH0_CR_TXTRAINRANK1_TxEqualization_MAX               (0x0000003F)
+  #define DDRDATA4CH0_CR_TXTRAINRANK1_Spare1_OFF                       (26)
+  #define DDRDATA4CH0_CR_TXTRAINRANK1_Spare1_WID                       ( 6)
+  #define DDRDATA4CH0_CR_TXTRAINRANK1_Spare1_MSK                       (0xFC000000)
+  #define DDRDATA4CH0_CR_TXTRAINRANK1_Spare1_MAX                       (0x0000003F)
+
+#define DDRDATA4CH0_CR_TXTRAINRANK2_REG                              (0x00000828)
+  #define DDRDATA4CH0_CR_TXTRAINRANK2_TxDqDelay_OFF                    ( 0)
+  #define DDRDATA4CH0_CR_TXTRAINRANK2_TxDqDelay_WID                    ( 9)
+  #define DDRDATA4CH0_CR_TXTRAINRANK2_TxDqDelay_MSK                    (0x000001FF)
+  #define DDRDATA4CH0_CR_TXTRAINRANK2_TxDqDelay_MAX                    (0x000001FF)
+  #define DDRDATA4CH0_CR_TXTRAINRANK2_TxDqsDelay_OFF                   ( 9)
+  #define DDRDATA4CH0_CR_TXTRAINRANK2_TxDqsDelay_WID                   ( 9)
+  #define DDRDATA4CH0_CR_TXTRAINRANK2_TxDqsDelay_MSK                   (0x0003FE00)
+  #define DDRDATA4CH0_CR_TXTRAINRANK2_TxDqsDelay_MAX                   (0x000001FF)
+  #define DDRDATA4CH0_CR_TXTRAINRANK2_Spare0_OFF                       (18)
+  #define DDRDATA4CH0_CR_TXTRAINRANK2_Spare0_WID                       ( 2)
+  #define DDRDATA4CH0_CR_TXTRAINRANK2_Spare0_MSK                       (0x000C0000)
+  #define DDRDATA4CH0_CR_TXTRAINRANK2_Spare0_MAX                       (0x00000003)
+  #define DDRDATA4CH0_CR_TXTRAINRANK2_TxEqualization_OFF               (20)
+  #define DDRDATA4CH0_CR_TXTRAINRANK2_TxEqualization_WID               ( 6)
+  #define DDRDATA4CH0_CR_TXTRAINRANK2_TxEqualization_MSK               (0x03F00000)
+  #define DDRDATA4CH0_CR_TXTRAINRANK2_TxEqualization_MAX               (0x0000003F)
+  #define DDRDATA4CH0_CR_TXTRAINRANK2_Spare1_OFF                       (26)
+  #define DDRDATA4CH0_CR_TXTRAINRANK2_Spare1_WID                       ( 6)
+  #define DDRDATA4CH0_CR_TXTRAINRANK2_Spare1_MSK                       (0xFC000000)
+  #define DDRDATA4CH0_CR_TXTRAINRANK2_Spare1_MAX                       (0x0000003F)
+
+#define DDRDATA4CH0_CR_TXTRAINRANK3_REG                              (0x0000082C)
+  #define DDRDATA4CH0_CR_TXTRAINRANK3_TxDqDelay_OFF                    ( 0)
+  #define DDRDATA4CH0_CR_TXTRAINRANK3_TxDqDelay_WID                    ( 9)
+  #define DDRDATA4CH0_CR_TXTRAINRANK3_TxDqDelay_MSK                    (0x000001FF)
+  #define DDRDATA4CH0_CR_TXTRAINRANK3_TxDqDelay_MAX                    (0x000001FF)
+  #define DDRDATA4CH0_CR_TXTRAINRANK3_TxDqsDelay_OFF                   ( 9)
+  #define DDRDATA4CH0_CR_TXTRAINRANK3_TxDqsDelay_WID                   ( 9)
+  #define DDRDATA4CH0_CR_TXTRAINRANK3_TxDqsDelay_MSK                   (0x0003FE00)
+  #define DDRDATA4CH0_CR_TXTRAINRANK3_TxDqsDelay_MAX                   (0x000001FF)
+  #define DDRDATA4CH0_CR_TXTRAINRANK3_Spare0_OFF                       (18)
+  #define DDRDATA4CH0_CR_TXTRAINRANK3_Spare0_WID                       ( 2)
+  #define DDRDATA4CH0_CR_TXTRAINRANK3_Spare0_MSK                       (0x000C0000)
+  #define DDRDATA4CH0_CR_TXTRAINRANK3_Spare0_MAX                       (0x00000003)
+  #define DDRDATA4CH0_CR_TXTRAINRANK3_TxEqualization_OFF               (20)
+  #define DDRDATA4CH0_CR_TXTRAINRANK3_TxEqualization_WID               ( 6)
+  #define DDRDATA4CH0_CR_TXTRAINRANK3_TxEqualization_MSK               (0x03F00000)
+  #define DDRDATA4CH0_CR_TXTRAINRANK3_TxEqualization_MAX               (0x0000003F)
+  #define DDRDATA4CH0_CR_TXTRAINRANK3_Spare1_OFF                       (26)
+  #define DDRDATA4CH0_CR_TXTRAINRANK3_Spare1_WID                       ( 6)
+  #define DDRDATA4CH0_CR_TXTRAINRANK3_Spare1_MSK                       (0xFC000000)
+  #define DDRDATA4CH0_CR_TXTRAINRANK3_Spare1_MAX                       (0x0000003F)
+
+#define DDRDATA4CH0_CR_TXPERBITRANK0_REG                             (0x00000830)
+  #define DDRDATA4CH0_CR_TXPERBITRANK0_Lane0_OFF                       ( 0)
+  #define DDRDATA4CH0_CR_TXPERBITRANK0_Lane0_WID                       ( 4)
+  #define DDRDATA4CH0_CR_TXPERBITRANK0_Lane0_MSK                       (0x0000000F)
+  #define DDRDATA4CH0_CR_TXPERBITRANK0_Lane0_MAX                       (0x0000000F)
+  #define DDRDATA4CH0_CR_TXPERBITRANK0_Lane1_OFF                       ( 4)
+  #define DDRDATA4CH0_CR_TXPERBITRANK0_Lane1_WID                       ( 4)
+  #define DDRDATA4CH0_CR_TXPERBITRANK0_Lane1_MSK                       (0x000000F0)
+  #define DDRDATA4CH0_CR_TXPERBITRANK0_Lane1_MAX                       (0x0000000F)
+  #define DDRDATA4CH0_CR_TXPERBITRANK0_Lane2_OFF                       ( 8)
+  #define DDRDATA4CH0_CR_TXPERBITRANK0_Lane2_WID                       ( 4)
+  #define DDRDATA4CH0_CR_TXPERBITRANK0_Lane2_MSK                       (0x00000F00)
+  #define DDRDATA4CH0_CR_TXPERBITRANK0_Lane2_MAX                       (0x0000000F)
+  #define DDRDATA4CH0_CR_TXPERBITRANK0_Lane3_OFF                       (12)
+  #define DDRDATA4CH0_CR_TXPERBITRANK0_Lane3_WID                       ( 4)
+  #define DDRDATA4CH0_CR_TXPERBITRANK0_Lane3_MSK                       (0x0000F000)
+  #define DDRDATA4CH0_CR_TXPERBITRANK0_Lane3_MAX                       (0x0000000F)
+  #define DDRDATA4CH0_CR_TXPERBITRANK0_Lane4_OFF                       (16)
+  #define DDRDATA4CH0_CR_TXPERBITRANK0_Lane4_WID                       ( 4)
+  #define DDRDATA4CH0_CR_TXPERBITRANK0_Lane4_MSK                       (0x000F0000)
+  #define DDRDATA4CH0_CR_TXPERBITRANK0_Lane4_MAX                       (0x0000000F)
+  #define DDRDATA4CH0_CR_TXPERBITRANK0_Lane5_OFF                       (20)
+  #define DDRDATA4CH0_CR_TXPERBITRANK0_Lane5_WID                       ( 4)
+  #define DDRDATA4CH0_CR_TXPERBITRANK0_Lane5_MSK                       (0x00F00000)
+  #define DDRDATA4CH0_CR_TXPERBITRANK0_Lane5_MAX                       (0x0000000F)
+  #define DDRDATA4CH0_CR_TXPERBITRANK0_Lane6_OFF                       (24)
+  #define DDRDATA4CH0_CR_TXPERBITRANK0_Lane6_WID                       ( 4)
+  #define DDRDATA4CH0_CR_TXPERBITRANK0_Lane6_MSK                       (0x0F000000)
+  #define DDRDATA4CH0_CR_TXPERBITRANK0_Lane6_MAX                       (0x0000000F)
+  #define DDRDATA4CH0_CR_TXPERBITRANK0_Lane7_OFF                       (28)
+  #define DDRDATA4CH0_CR_TXPERBITRANK0_Lane7_WID                       ( 4)
+  #define DDRDATA4CH0_CR_TXPERBITRANK0_Lane7_MSK                       (0xF0000000)
+  #define DDRDATA4CH0_CR_TXPERBITRANK0_Lane7_MAX                       (0x0000000F)
+
+#define DDRDATA4CH0_CR_TXPERBITRANK1_REG                             (0x00000834)
+  #define DDRDATA4CH0_CR_TXPERBITRANK1_Lane0_OFF                       ( 0)
+  #define DDRDATA4CH0_CR_TXPERBITRANK1_Lane0_WID                       ( 4)
+  #define DDRDATA4CH0_CR_TXPERBITRANK1_Lane0_MSK                       (0x0000000F)
+  #define DDRDATA4CH0_CR_TXPERBITRANK1_Lane0_MAX                       (0x0000000F)
+  #define DDRDATA4CH0_CR_TXPERBITRANK1_Lane1_OFF                       ( 4)
+  #define DDRDATA4CH0_CR_TXPERBITRANK1_Lane1_WID                       ( 4)
+  #define DDRDATA4CH0_CR_TXPERBITRANK1_Lane1_MSK                       (0x000000F0)
+  #define DDRDATA4CH0_CR_TXPERBITRANK1_Lane1_MAX                       (0x0000000F)
+  #define DDRDATA4CH0_CR_TXPERBITRANK1_Lane2_OFF                       ( 8)
+  #define DDRDATA4CH0_CR_TXPERBITRANK1_Lane2_WID                       ( 4)
+  #define DDRDATA4CH0_CR_TXPERBITRANK1_Lane2_MSK                       (0x00000F00)
+  #define DDRDATA4CH0_CR_TXPERBITRANK1_Lane2_MAX                       (0x0000000F)
+  #define DDRDATA4CH0_CR_TXPERBITRANK1_Lane3_OFF                       (12)
+  #define DDRDATA4CH0_CR_TXPERBITRANK1_Lane3_WID                       ( 4)
+  #define DDRDATA4CH0_CR_TXPERBITRANK1_Lane3_MSK                       (0x0000F000)
+  #define DDRDATA4CH0_CR_TXPERBITRANK1_Lane3_MAX                       (0x0000000F)
+  #define DDRDATA4CH0_CR_TXPERBITRANK1_Lane4_OFF                       (16)
+  #define DDRDATA4CH0_CR_TXPERBITRANK1_Lane4_WID                       ( 4)
+  #define DDRDATA4CH0_CR_TXPERBITRANK1_Lane4_MSK                       (0x000F0000)
+  #define DDRDATA4CH0_CR_TXPERBITRANK1_Lane4_MAX                       (0x0000000F)
+  #define DDRDATA4CH0_CR_TXPERBITRANK1_Lane5_OFF                       (20)
+  #define DDRDATA4CH0_CR_TXPERBITRANK1_Lane5_WID                       ( 4)
+  #define DDRDATA4CH0_CR_TXPERBITRANK1_Lane5_MSK                       (0x00F00000)
+  #define DDRDATA4CH0_CR_TXPERBITRANK1_Lane5_MAX                       (0x0000000F)
+  #define DDRDATA4CH0_CR_TXPERBITRANK1_Lane6_OFF                       (24)
+  #define DDRDATA4CH0_CR_TXPERBITRANK1_Lane6_WID                       ( 4)
+  #define DDRDATA4CH0_CR_TXPERBITRANK1_Lane6_MSK                       (0x0F000000)
+  #define DDRDATA4CH0_CR_TXPERBITRANK1_Lane6_MAX                       (0x0000000F)
+  #define DDRDATA4CH0_CR_TXPERBITRANK1_Lane7_OFF                       (28)
+  #define DDRDATA4CH0_CR_TXPERBITRANK1_Lane7_WID                       ( 4)
+  #define DDRDATA4CH0_CR_TXPERBITRANK1_Lane7_MSK                       (0xF0000000)
+  #define DDRDATA4CH0_CR_TXPERBITRANK1_Lane7_MAX                       (0x0000000F)
+
+#define DDRDATA4CH0_CR_TXPERBITRANK2_REG                             (0x00000838)
+  #define DDRDATA4CH0_CR_TXPERBITRANK2_Lane0_OFF                       ( 0)
+  #define DDRDATA4CH0_CR_TXPERBITRANK2_Lane0_WID                       ( 4)
+  #define DDRDATA4CH0_CR_TXPERBITRANK2_Lane0_MSK                       (0x0000000F)
+  #define DDRDATA4CH0_CR_TXPERBITRANK2_Lane0_MAX                       (0x0000000F)
+  #define DDRDATA4CH0_CR_TXPERBITRANK2_Lane1_OFF                       ( 4)
+  #define DDRDATA4CH0_CR_TXPERBITRANK2_Lane1_WID                       ( 4)
+  #define DDRDATA4CH0_CR_TXPERBITRANK2_Lane1_MSK                       (0x000000F0)
+  #define DDRDATA4CH0_CR_TXPERBITRANK2_Lane1_MAX                       (0x0000000F)
+  #define DDRDATA4CH0_CR_TXPERBITRANK2_Lane2_OFF                       ( 8)
+  #define DDRDATA4CH0_CR_TXPERBITRANK2_Lane2_WID                       ( 4)
+  #define DDRDATA4CH0_CR_TXPERBITRANK2_Lane2_MSK                       (0x00000F00)
+  #define DDRDATA4CH0_CR_TXPERBITRANK2_Lane2_MAX                       (0x0000000F)
+  #define DDRDATA4CH0_CR_TXPERBITRANK2_Lane3_OFF                       (12)
+  #define DDRDATA4CH0_CR_TXPERBITRANK2_Lane3_WID                       ( 4)
+  #define DDRDATA4CH0_CR_TXPERBITRANK2_Lane3_MSK                       (0x0000F000)
+  #define DDRDATA4CH0_CR_TXPERBITRANK2_Lane3_MAX                       (0x0000000F)
+  #define DDRDATA4CH0_CR_TXPERBITRANK2_Lane4_OFF                       (16)
+  #define DDRDATA4CH0_CR_TXPERBITRANK2_Lane4_WID                       ( 4)
+  #define DDRDATA4CH0_CR_TXPERBITRANK2_Lane4_MSK                       (0x000F0000)
+  #define DDRDATA4CH0_CR_TXPERBITRANK2_Lane4_MAX                       (0x0000000F)
+  #define DDRDATA4CH0_CR_TXPERBITRANK2_Lane5_OFF                       (20)
+  #define DDRDATA4CH0_CR_TXPERBITRANK2_Lane5_WID                       ( 4)
+  #define DDRDATA4CH0_CR_TXPERBITRANK2_Lane5_MSK                       (0x00F00000)
+  #define DDRDATA4CH0_CR_TXPERBITRANK2_Lane5_MAX                       (0x0000000F)
+  #define DDRDATA4CH0_CR_TXPERBITRANK2_Lane6_OFF                       (24)
+  #define DDRDATA4CH0_CR_TXPERBITRANK2_Lane6_WID                       ( 4)
+  #define DDRDATA4CH0_CR_TXPERBITRANK2_Lane6_MSK                       (0x0F000000)
+  #define DDRDATA4CH0_CR_TXPERBITRANK2_Lane6_MAX                       (0x0000000F)
+  #define DDRDATA4CH0_CR_TXPERBITRANK2_Lane7_OFF                       (28)
+  #define DDRDATA4CH0_CR_TXPERBITRANK2_Lane7_WID                       ( 4)
+  #define DDRDATA4CH0_CR_TXPERBITRANK2_Lane7_MSK                       (0xF0000000)
+  #define DDRDATA4CH0_CR_TXPERBITRANK2_Lane7_MAX                       (0x0000000F)
+
+#define DDRDATA4CH0_CR_TXPERBITRANK3_REG                             (0x0000083C)
+  #define DDRDATA4CH0_CR_TXPERBITRANK3_Lane0_OFF                       ( 0)
+  #define DDRDATA4CH0_CR_TXPERBITRANK3_Lane0_WID                       ( 4)
+  #define DDRDATA4CH0_CR_TXPERBITRANK3_Lane0_MSK                       (0x0000000F)
+  #define DDRDATA4CH0_CR_TXPERBITRANK3_Lane0_MAX                       (0x0000000F)
+  #define DDRDATA4CH0_CR_TXPERBITRANK3_Lane1_OFF                       ( 4)
+  #define DDRDATA4CH0_CR_TXPERBITRANK3_Lane1_WID                       ( 4)
+  #define DDRDATA4CH0_CR_TXPERBITRANK3_Lane1_MSK                       (0x000000F0)
+  #define DDRDATA4CH0_CR_TXPERBITRANK3_Lane1_MAX                       (0x0000000F)
+  #define DDRDATA4CH0_CR_TXPERBITRANK3_Lane2_OFF                       ( 8)
+  #define DDRDATA4CH0_CR_TXPERBITRANK3_Lane2_WID                       ( 4)
+  #define DDRDATA4CH0_CR_TXPERBITRANK3_Lane2_MSK                       (0x00000F00)
+  #define DDRDATA4CH0_CR_TXPERBITRANK3_Lane2_MAX                       (0x0000000F)
+  #define DDRDATA4CH0_CR_TXPERBITRANK3_Lane3_OFF                       (12)
+  #define DDRDATA4CH0_CR_TXPERBITRANK3_Lane3_WID                       ( 4)
+  #define DDRDATA4CH0_CR_TXPERBITRANK3_Lane3_MSK                       (0x0000F000)
+  #define DDRDATA4CH0_CR_TXPERBITRANK3_Lane3_MAX                       (0x0000000F)
+  #define DDRDATA4CH0_CR_TXPERBITRANK3_Lane4_OFF                       (16)
+  #define DDRDATA4CH0_CR_TXPERBITRANK3_Lane4_WID                       ( 4)
+  #define DDRDATA4CH0_CR_TXPERBITRANK3_Lane4_MSK                       (0x000F0000)
+  #define DDRDATA4CH0_CR_TXPERBITRANK3_Lane4_MAX                       (0x0000000F)
+  #define DDRDATA4CH0_CR_TXPERBITRANK3_Lane5_OFF                       (20)
+  #define DDRDATA4CH0_CR_TXPERBITRANK3_Lane5_WID                       ( 4)
+  #define DDRDATA4CH0_CR_TXPERBITRANK3_Lane5_MSK                       (0x00F00000)
+  #define DDRDATA4CH0_CR_TXPERBITRANK3_Lane5_MAX                       (0x0000000F)
+  #define DDRDATA4CH0_CR_TXPERBITRANK3_Lane6_OFF                       (24)
+  #define DDRDATA4CH0_CR_TXPERBITRANK3_Lane6_WID                       ( 4)
+  #define DDRDATA4CH0_CR_TXPERBITRANK3_Lane6_MSK                       (0x0F000000)
+  #define DDRDATA4CH0_CR_TXPERBITRANK3_Lane6_MAX                       (0x0000000F)
+  #define DDRDATA4CH0_CR_TXPERBITRANK3_Lane7_OFF                       (28)
+  #define DDRDATA4CH0_CR_TXPERBITRANK3_Lane7_WID                       ( 4)
+  #define DDRDATA4CH0_CR_TXPERBITRANK3_Lane7_MSK                       (0xF0000000)
+  #define DDRDATA4CH0_CR_TXPERBITRANK3_Lane7_MAX                       (0x0000000F)
+
+#define DDRDATA4CH0_CR_RCOMPDATA0_REG                                (0x00000840)
+  #define DDRDATA4CH0_CR_RCOMPDATA0_RcompDrvUp_OFF                     ( 0)
+  #define DDRDATA4CH0_CR_RCOMPDATA0_RcompDrvUp_WID                     ( 6)
+  #define DDRDATA4CH0_CR_RCOMPDATA0_RcompDrvUp_MSK                     (0x0000003F)
+  #define DDRDATA4CH0_CR_RCOMPDATA0_RcompDrvUp_MAX                     (0x0000003F)
+  #define DDRDATA4CH0_CR_RCOMPDATA0_Spare0_OFF                         ( 6)
+  #define DDRDATA4CH0_CR_RCOMPDATA0_Spare0_WID                         ( 3)
+  #define DDRDATA4CH0_CR_RCOMPDATA0_Spare0_MSK                         (0x000001C0)
+  #define DDRDATA4CH0_CR_RCOMPDATA0_Spare0_MAX                         (0x00000007)
+  #define DDRDATA4CH0_CR_RCOMPDATA0_RcompDrvDown_OFF                   ( 9)
+  #define DDRDATA4CH0_CR_RCOMPDATA0_RcompDrvDown_WID                   ( 6)
+  #define DDRDATA4CH0_CR_RCOMPDATA0_RcompDrvDown_MSK                   (0x00007E00)
+  #define DDRDATA4CH0_CR_RCOMPDATA0_RcompDrvDown_MAX                   (0x0000003F)
+  #define DDRDATA4CH0_CR_RCOMPDATA0_VTComp_OFF                         (15)
+  #define DDRDATA4CH0_CR_RCOMPDATA0_VTComp_WID                         ( 5)
+  #define DDRDATA4CH0_CR_RCOMPDATA0_VTComp_MSK                         (0x000F8000)
+  #define DDRDATA4CH0_CR_RCOMPDATA0_VTComp_MAX                         (0x0000001F)
+  #define DDRDATA4CH0_CR_RCOMPDATA0_TcoComp_OFF                        (20)
+  #define DDRDATA4CH0_CR_RCOMPDATA0_TcoComp_WID                        ( 6)
+  #define DDRDATA4CH0_CR_RCOMPDATA0_TcoComp_MSK                        (0x03F00000)
+  #define DDRDATA4CH0_CR_RCOMPDATA0_TcoComp_MAX                        (0x0000003F)
+  #define DDRDATA4CH0_CR_RCOMPDATA0_SlewRateComp_OFF                   (26)
+  #define DDRDATA4CH0_CR_RCOMPDATA0_SlewRateComp_WID                   ( 5)
+  #define DDRDATA4CH0_CR_RCOMPDATA0_SlewRateComp_MSK                   (0x7C000000)
+  #define DDRDATA4CH0_CR_RCOMPDATA0_SlewRateComp_MAX                   (0x0000001F)
+  #define DDRDATA4CH0_CR_RCOMPDATA0_Spare2_OFF                         (31)
+  #define DDRDATA4CH0_CR_RCOMPDATA0_Spare2_WID                         ( 1)
+  #define DDRDATA4CH0_CR_RCOMPDATA0_Spare2_MSK                         (0x80000000)
+  #define DDRDATA4CH0_CR_RCOMPDATA0_Spare2_MAX                         (0x00000001)
+
+#define DDRDATA4CH0_CR_RCOMPDATA1_REG                                (0x00000844)
+  #define DDRDATA4CH0_CR_RCOMPDATA1_RcompOdtUp_OFF                     ( 0)
+  #define DDRDATA4CH0_CR_RCOMPDATA1_RcompOdtUp_WID                     ( 6)
+  #define DDRDATA4CH0_CR_RCOMPDATA1_RcompOdtUp_MSK                     (0x0000003F)
+  #define DDRDATA4CH0_CR_RCOMPDATA1_RcompOdtUp_MAX                     (0x0000003F)
+  #define DDRDATA4CH0_CR_RCOMPDATA1_Spare0_OFF                         ( 6)
+  #define DDRDATA4CH0_CR_RCOMPDATA1_Spare0_WID                         ( 3)
+  #define DDRDATA4CH0_CR_RCOMPDATA1_Spare0_MSK                         (0x000001C0)
+  #define DDRDATA4CH0_CR_RCOMPDATA1_Spare0_MAX                         (0x00000007)
+  #define DDRDATA4CH0_CR_RCOMPDATA1_RcompOdtDown_OFF                   ( 9)
+  #define DDRDATA4CH0_CR_RCOMPDATA1_RcompOdtDown_WID                   ( 6)
+  #define DDRDATA4CH0_CR_RCOMPDATA1_RcompOdtDown_MSK                   (0x00007E00)
+  #define DDRDATA4CH0_CR_RCOMPDATA1_RcompOdtDown_MAX                   (0x0000003F)
+  #define DDRDATA4CH0_CR_RCOMPDATA1_Spare1_OFF                         (15)
+  #define DDRDATA4CH0_CR_RCOMPDATA1_Spare1_WID                         ( 1)
+  #define DDRDATA4CH0_CR_RCOMPDATA1_Spare1_MSK                         (0x00008000)
+  #define DDRDATA4CH0_CR_RCOMPDATA1_Spare1_MAX                         (0x00000001)
+  #define DDRDATA4CH0_CR_RCOMPDATA1_PanicDrvDn_OFF                     (16)
+  #define DDRDATA4CH0_CR_RCOMPDATA1_PanicDrvDn_WID                     ( 6)
+  #define DDRDATA4CH0_CR_RCOMPDATA1_PanicDrvDn_MSK                     (0x003F0000)
+  #define DDRDATA4CH0_CR_RCOMPDATA1_PanicDrvDn_MAX                     (0x0000003F)
+  #define DDRDATA4CH0_CR_RCOMPDATA1_PanicDrvUp_OFF                     (22)
+  #define DDRDATA4CH0_CR_RCOMPDATA1_PanicDrvUp_WID                     ( 6)
+  #define DDRDATA4CH0_CR_RCOMPDATA1_PanicDrvUp_MSK                     (0x0FC00000)
+  #define DDRDATA4CH0_CR_RCOMPDATA1_PanicDrvUp_MAX                     (0x0000003F)
+  #define DDRDATA4CH0_CR_RCOMPDATA1_LevelShifterComp_OFF               (28)
+  #define DDRDATA4CH0_CR_RCOMPDATA1_LevelShifterComp_WID               ( 3)
+  #define DDRDATA4CH0_CR_RCOMPDATA1_LevelShifterComp_MSK               (0x70000000)
+  #define DDRDATA4CH0_CR_RCOMPDATA1_LevelShifterComp_MAX               (0x00000007)
+  #define DDRDATA4CH0_CR_RCOMPDATA1_Spare2_OFF                         (31)
+  #define DDRDATA4CH0_CR_RCOMPDATA1_Spare2_WID                         ( 1)
+  #define DDRDATA4CH0_CR_RCOMPDATA1_Spare2_MSK                         (0x80000000)
+  #define DDRDATA4CH0_CR_RCOMPDATA1_Spare2_MAX                         (0x00000001)
+
+#define DDRDATA4CH0_CR_TXXTALK_REG                                   (0x00000848)
+  #define DDRDATA4CH0_CR_TXXTALK_Lane0_OFF                             ( 0)
+  #define DDRDATA4CH0_CR_TXXTALK_Lane0_WID                             ( 4)
+  #define DDRDATA4CH0_CR_TXXTALK_Lane0_MSK                             (0x0000000F)
+  #define DDRDATA4CH0_CR_TXXTALK_Lane0_MAX                             (0x0000000F)
+  #define DDRDATA4CH0_CR_TXXTALK_Lane1_OFF                             ( 4)
+  #define DDRDATA4CH0_CR_TXXTALK_Lane1_WID                             ( 4)
+  #define DDRDATA4CH0_CR_TXXTALK_Lane1_MSK                             (0x000000F0)
+  #define DDRDATA4CH0_CR_TXXTALK_Lane1_MAX                             (0x0000000F)
+  #define DDRDATA4CH0_CR_TXXTALK_Lane2_OFF                             ( 8)
+  #define DDRDATA4CH0_CR_TXXTALK_Lane2_WID                             ( 4)
+  #define DDRDATA4CH0_CR_TXXTALK_Lane2_MSK                             (0x00000F00)
+  #define DDRDATA4CH0_CR_TXXTALK_Lane2_MAX                             (0x0000000F)
+  #define DDRDATA4CH0_CR_TXXTALK_Lane3_OFF                             (12)
+  #define DDRDATA4CH0_CR_TXXTALK_Lane3_WID                             ( 4)
+  #define DDRDATA4CH0_CR_TXXTALK_Lane3_MSK                             (0x0000F000)
+  #define DDRDATA4CH0_CR_TXXTALK_Lane3_MAX                             (0x0000000F)
+  #define DDRDATA4CH0_CR_TXXTALK_Lane4_OFF                             (16)
+  #define DDRDATA4CH0_CR_TXXTALK_Lane4_WID                             ( 4)
+  #define DDRDATA4CH0_CR_TXXTALK_Lane4_MSK                             (0x000F0000)
+  #define DDRDATA4CH0_CR_TXXTALK_Lane4_MAX                             (0x0000000F)
+  #define DDRDATA4CH0_CR_TXXTALK_Lane5_OFF                             (20)
+  #define DDRDATA4CH0_CR_TXXTALK_Lane5_WID                             ( 4)
+  #define DDRDATA4CH0_CR_TXXTALK_Lane5_MSK                             (0x00F00000)
+  #define DDRDATA4CH0_CR_TXXTALK_Lane5_MAX                             (0x0000000F)
+  #define DDRDATA4CH0_CR_TXXTALK_Lane6_OFF                             (24)
+  #define DDRDATA4CH0_CR_TXXTALK_Lane6_WID                             ( 4)
+  #define DDRDATA4CH0_CR_TXXTALK_Lane6_MSK                             (0x0F000000)
+  #define DDRDATA4CH0_CR_TXXTALK_Lane6_MAX                             (0x0000000F)
+  #define DDRDATA4CH0_CR_TXXTALK_Lane7_OFF                             (28)
+  #define DDRDATA4CH0_CR_TXXTALK_Lane7_WID                             ( 4)
+  #define DDRDATA4CH0_CR_TXXTALK_Lane7_MSK                             (0xF0000000)
+  #define DDRDATA4CH0_CR_TXXTALK_Lane7_MAX                             (0x0000000F)
+
+#define DDRDATA4CH0_CR_RXOFFSETVDQ_REG                               (0x0000084C)
+  #define DDRDATA4CH0_CR_RXOFFSETVDQ_Lane0_OFF                         ( 0)
+  #define DDRDATA4CH0_CR_RXOFFSETVDQ_Lane0_WID                         ( 4)
+  #define DDRDATA4CH0_CR_RXOFFSETVDQ_Lane0_MSK                         (0x0000000F)
+  #define DDRDATA4CH0_CR_RXOFFSETVDQ_Lane0_MAX                         (0x0000000F)
+  #define DDRDATA4CH0_CR_RXOFFSETVDQ_Lane1_OFF                         ( 4)
+  #define DDRDATA4CH0_CR_RXOFFSETVDQ_Lane1_WID                         ( 4)
+  #define DDRDATA4CH0_CR_RXOFFSETVDQ_Lane1_MSK                         (0x000000F0)
+  #define DDRDATA4CH0_CR_RXOFFSETVDQ_Lane1_MAX                         (0x0000000F)
+  #define DDRDATA4CH0_CR_RXOFFSETVDQ_Lane2_OFF                         ( 8)
+  #define DDRDATA4CH0_CR_RXOFFSETVDQ_Lane2_WID                         ( 4)
+  #define DDRDATA4CH0_CR_RXOFFSETVDQ_Lane2_MSK                         (0x00000F00)
+  #define DDRDATA4CH0_CR_RXOFFSETVDQ_Lane2_MAX                         (0x0000000F)
+  #define DDRDATA4CH0_CR_RXOFFSETVDQ_Lane3_OFF                         (12)
+  #define DDRDATA4CH0_CR_RXOFFSETVDQ_Lane3_WID                         ( 4)
+  #define DDRDATA4CH0_CR_RXOFFSETVDQ_Lane3_MSK                         (0x0000F000)
+  #define DDRDATA4CH0_CR_RXOFFSETVDQ_Lane3_MAX                         (0x0000000F)
+  #define DDRDATA4CH0_CR_RXOFFSETVDQ_Lane4_OFF                         (16)
+  #define DDRDATA4CH0_CR_RXOFFSETVDQ_Lane4_WID                         ( 4)
+  #define DDRDATA4CH0_CR_RXOFFSETVDQ_Lane4_MSK                         (0x000F0000)
+  #define DDRDATA4CH0_CR_RXOFFSETVDQ_Lane4_MAX                         (0x0000000F)
+  #define DDRDATA4CH0_CR_RXOFFSETVDQ_Lane5_OFF                         (20)
+  #define DDRDATA4CH0_CR_RXOFFSETVDQ_Lane5_WID                         ( 4)
+  #define DDRDATA4CH0_CR_RXOFFSETVDQ_Lane5_MSK                         (0x00F00000)
+  #define DDRDATA4CH0_CR_RXOFFSETVDQ_Lane5_MAX                         (0x0000000F)
+  #define DDRDATA4CH0_CR_RXOFFSETVDQ_Lane6_OFF                         (24)
+  #define DDRDATA4CH0_CR_RXOFFSETVDQ_Lane6_WID                         ( 4)
+  #define DDRDATA4CH0_CR_RXOFFSETVDQ_Lane6_MSK                         (0x0F000000)
+  #define DDRDATA4CH0_CR_RXOFFSETVDQ_Lane6_MAX                         (0x0000000F)
+  #define DDRDATA4CH0_CR_RXOFFSETVDQ_Lane7_OFF                         (28)
+  #define DDRDATA4CH0_CR_RXOFFSETVDQ_Lane7_WID                         ( 4)
+  #define DDRDATA4CH0_CR_RXOFFSETVDQ_Lane7_MSK                         (0xF0000000)
+  #define DDRDATA4CH0_CR_RXOFFSETVDQ_Lane7_MAX                         (0x0000000F)
+
+#define DDRDATA4CH0_CR_DDRDATARESERVED_REG                           (0x00000850)
+  #define DDRDATA4CH0_CR_DDRDATARESERVED_Spare_OFF                     ( 0)
+  #define DDRDATA4CH0_CR_DDRDATARESERVED_Spare_WID                     (32)
+  #define DDRDATA4CH0_CR_DDRDATARESERVED_Spare_MSK                     (0xFFFFFFFF)
+  #define DDRDATA4CH0_CR_DDRDATARESERVED_Spare_MAX                     (0xFFFFFFFF)
+
+#define DDRDATA4CH0_CR_DATATRAINFEEDBACK_REG                         (0x00000854)
+  #define DDRDATA4CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_OFF       ( 0)
+  #define DDRDATA4CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_WID       ( 9)
+  #define DDRDATA4CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_MSK       (0x000001FF)
+  #define DDRDATA4CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_MAX       (0x000001FF)
+  #define DDRDATA4CH0_CR_DATATRAINFEEDBACK_Spare_OFF                   ( 9)
+  #define DDRDATA4CH0_CR_DATATRAINFEEDBACK_Spare_WID                   (23)
+  #define DDRDATA4CH0_CR_DATATRAINFEEDBACK_Spare_MSK                   (0xFFFFFE00)
+  #define DDRDATA4CH0_CR_DATATRAINFEEDBACK_Spare_MAX                   (0x007FFFFF)
+
+#define DDRDATA4CH0_CR_DLLPITESTANDADC_REG                           (0x00000858)
+  #define DDRDATA4CH0_CR_DLLPITESTANDADC_RunTest_OFF                   ( 0)
+  #define DDRDATA4CH0_CR_DLLPITESTANDADC_RunTest_WID                   ( 1)
+  #define DDRDATA4CH0_CR_DLLPITESTANDADC_RunTest_MSK                   (0x00000001)
+  #define DDRDATA4CH0_CR_DLLPITESTANDADC_RunTest_MAX                   (0x00000001)
+  #define DDRDATA4CH0_CR_DLLPITESTANDADC_RunTest_DEF                   (0x00000000)
+  #define DDRDATA4CH0_CR_DLLPITESTANDADC_Load_OFF                      ( 1)
+  #define DDRDATA4CH0_CR_DLLPITESTANDADC_Load_WID                      ( 1)
+  #define DDRDATA4CH0_CR_DLLPITESTANDADC_Load_MSK                      (0x00000002)
+  #define DDRDATA4CH0_CR_DLLPITESTANDADC_Load_MAX                      (0x00000001)
+  #define DDRDATA4CH0_CR_DLLPITESTANDADC_Load_DEF                      (0x00000000)
+  #define DDRDATA4CH0_CR_DLLPITESTANDADC_ModeHVM_OFF                   ( 2)
+  #define DDRDATA4CH0_CR_DLLPITESTANDADC_ModeHVM_WID                   ( 1)
+  #define DDRDATA4CH0_CR_DLLPITESTANDADC_ModeHVM_MSK                   (0x00000004)
+  #define DDRDATA4CH0_CR_DLLPITESTANDADC_ModeHVM_MAX                   (0x00000001)
+  #define DDRDATA4CH0_CR_DLLPITESTANDADC_ModeHVM_DEF                   (0x00000000)
+  #define DDRDATA4CH0_CR_DLLPITESTANDADC_ModeDV_OFF                    ( 3)
+  #define DDRDATA4CH0_CR_DLLPITESTANDADC_ModeDV_WID                    ( 1)
+  #define DDRDATA4CH0_CR_DLLPITESTANDADC_ModeDV_MSK                    (0x00000008)
+  #define DDRDATA4CH0_CR_DLLPITESTANDADC_ModeDV_MAX                    (0x00000001)
+  #define DDRDATA4CH0_CR_DLLPITESTANDADC_ModeDV_DEF                    (0x00000000)
+  #define DDRDATA4CH0_CR_DLLPITESTANDADC_ModeADC_OFF                   ( 4)
+  #define DDRDATA4CH0_CR_DLLPITESTANDADC_ModeADC_WID                   ( 1)
+  #define DDRDATA4CH0_CR_DLLPITESTANDADC_ModeADC_MSK                   (0x00000010)
+  #define DDRDATA4CH0_CR_DLLPITESTANDADC_ModeADC_MAX                   (0x00000001)
+  #define DDRDATA4CH0_CR_DLLPITESTANDADC_ModeADC_DEF                   (0x00000000)
+  #define DDRDATA4CH0_CR_DLLPITESTANDADC_LoadCount_OFF                 ( 5)
+  #define DDRDATA4CH0_CR_DLLPITESTANDADC_LoadCount_WID                 (10)
+  #define DDRDATA4CH0_CR_DLLPITESTANDADC_LoadCount_MSK                 (0x00007FE0)
+  #define DDRDATA4CH0_CR_DLLPITESTANDADC_LoadCount_MAX                 (0x000003FF)
+  #define DDRDATA4CH0_CR_DLLPITESTANDADC_CountStatus_OFF               (15)
+  #define DDRDATA4CH0_CR_DLLPITESTANDADC_CountStatus_WID               (10)
+  #define DDRDATA4CH0_CR_DLLPITESTANDADC_CountStatus_MSK               (0x01FF8000)
+  #define DDRDATA4CH0_CR_DLLPITESTANDADC_CountStatus_MAX               (0x000003FF)
+  #define DDRDATA4CH0_CR_DLLPITESTANDADC_CountStatus_DEF               (0x00000000)
+  #define DDRDATA4CH0_CR_DLLPITESTANDADC_Spare_OFF                     (25)
+  #define DDRDATA4CH0_CR_DLLPITESTANDADC_Spare_WID                     ( 7)
+  #define DDRDATA4CH0_CR_DLLPITESTANDADC_Spare_MSK                     (0xFE000000)
+  #define DDRDATA4CH0_CR_DLLPITESTANDADC_Spare_MAX                     (0x0000007F)
+
+#define DDRDATA4CH0_CR_DDRCRDATAOFFSETCOMP_REG                       (0x0000085C)
+  #define DDRDATA4CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_OFF     ( 0)
+  #define DDRDATA4CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_WID     ( 6)
+  #define DDRDATA4CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MSK     (0x0000003F)
+  #define DDRDATA4CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MAX     (0x0000003F)
+  #define DDRDATA4CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_DEF     (0x00000000)
+  #define DDRDATA4CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_OFF   ( 6)
+  #define DDRDATA4CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_WID   ( 6)
+  #define DDRDATA4CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MSK   (0x00000FC0)
+  #define DDRDATA4CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MAX   (0x0000003F)
+  #define DDRDATA4CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_DEF   (0x00000000)
+  #define DDRDATA4CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_OFF     (12)
+  #define DDRDATA4CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_WID     ( 5)
+  #define DDRDATA4CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MSK     (0x0001F000)
+  #define DDRDATA4CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MAX     (0x0000001F)
+  #define DDRDATA4CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_DEF     (0x00000000)
+  #define DDRDATA4CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_OFF   (17)
+  #define DDRDATA4CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_WID   ( 5)
+  #define DDRDATA4CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MSK   (0x003E0000)
+  #define DDRDATA4CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MAX   (0x0000001F)
+  #define DDRDATA4CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_DEF   (0x00000000)
+  #define DDRDATA4CH0_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_OFF       (22)
+  #define DDRDATA4CH0_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_WID       ( 5)
+  #define DDRDATA4CH0_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_MSK       (0x07C00000)
+  #define DDRDATA4CH0_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_MAX       (0x0000001F)
+  #define DDRDATA4CH0_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_DEF       (0x00000000)
+  #define DDRDATA4CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_OFF  (27)
+  #define DDRDATA4CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_WID  ( 5)
+  #define DDRDATA4CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MSK  (0xF8000000)
+  #define DDRDATA4CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MAX  (0x0000001F)
+  #define DDRDATA4CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_DEF  (0x00000000)
+
+#define DDRDATA4CH0_CR_DDRCRDATACONTROL1_REG                         (0x00000860)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_RefPi_OFF                   ( 0)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_RefPi_WID                   ( 4)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_RefPi_MSK                   (0x0000000F)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_RefPi_MAX                   (0x0000000F)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_RefPi_DEF                   (0x00000000)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_DllMask_OFF                 ( 4)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_DllMask_WID                 ( 2)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_DllMask_MSK                 (0x00000030)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_DllMask_MAX                 (0x00000003)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_DllMask_DEF                 (0x00000000)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_DllWeakLock_OFF             ( 6)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_DllWeakLock_WID             ( 1)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_DllWeakLock_MSK             (0x00000040)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_DllWeakLock_MAX             (0x00000001)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_DllWeakLock_DEF             (0x00000000)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_OFF      ( 7)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_WID      ( 3)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MSK      (0x00000380)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MAX      (0x00000007)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_DEF      (0x00000000)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_OFF               (10)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_WID               ( 3)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_MSK               (0x00001C00)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_MAX               (0x00000007)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_DEF               (0x00000000)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_OdtDelay_OFF                (13)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_OdtDelay_WID                ( 4)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_OdtDelay_MSK                (0x0001E000)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_OdtDelay_MAX                (0x0000000F)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_OdtDelay_DEF                (0x00000000)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_OdtDuration_OFF             (17)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_OdtDuration_WID             ( 3)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_OdtDuration_MSK             (0x000E0000)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_OdtDuration_MAX             (0x00000007)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_OdtDuration_DEF             (0x00000000)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_OFF           (20)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_WID           ( 4)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_MSK           (0x00F00000)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_MAX           (0x0000000F)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_DEF           (0x00000000)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_OFF        (24)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_WID        ( 3)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_MSK        (0x07000000)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_MAX        (0x00000007)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_DEF        (0x00000000)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_BurstEndODTDelay_OFF        (27)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_BurstEndODTDelay_WID        ( 3)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_BurstEndODTDelay_MSK        (0x38000000)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_BurstEndODTDelay_MAX        (0x00000007)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_BurstEndODTDelay_DEF        (0x00000000)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_OFF          (30)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_WID          ( 1)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_MSK          (0x40000000)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_MAX          (0x00000001)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_DEF          (0x00000000)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_Rsvd1_OFF                   (31)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_Rsvd1_WID                   ( 1)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_Rsvd1_MSK                   (0x80000000)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_Rsvd1_MAX                   (0x00000001)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_Rsvd1_DEF                   (0x00000000)
+
+#define DDRDATA4CH0_CR_DDRCRDATACONTROL2_REG                         (0x00000864)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_OFF            ( 0)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_WID            ( 5)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_MSK            (0x0000001F)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_MAX            (0x0000001F)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_DEF            (0x00000000)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_OFF             ( 5)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_WID             ( 1)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_MSK             (0x00000020)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_MAX             (0x00000001)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_DEF             (0x00000000)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_ForceRxOn_OFF               ( 6)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_ForceRxOn_WID               ( 1)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_ForceRxOn_MSK               (0x00000040)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_ForceRxOn_MAX               (0x00000001)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_ForceRxOn_DEF               (0x00000000)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_LeakerComp_OFF              ( 7)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_LeakerComp_WID              ( 2)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_LeakerComp_MSK              (0x00000180)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_LeakerComp_MAX              (0x00000003)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_LeakerComp_DEF              (0x00000000)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_OFF          ( 9)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_WID          ( 4)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_MSK          (0x00001E00)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_MAX          (0x0000000F)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_DEF          (0x00000008)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_OFF             (13)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_WID             ( 5)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_MSK             (0x0003E000)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_MAX             (0x0000001F)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_DEF             (0x00000011)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_OFF             (18)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_WID             ( 1)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_MSK             (0x00040000)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_MAX             (0x00000001)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_DEF             (0x00000000)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_Spare_OFF                   (19)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_Spare_WID                   (13)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_Spare_MSK                   (0xFFF80000)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_Spare_MAX                   (0x00001FFF)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_Spare_DEF                   (0x00000000)
+
+#define DDRDATA4CH0_CR_DDRCRVSSHIORVREFCONTROL_REG                   (0x0000086C)
+  #define DDRDATA4CH0_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_OFF    ( 0)
+  #define DDRDATA4CH0_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_WID    (24)
+  #define DDRDATA4CH0_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_MSK    (0x00FFFFFF)
+  #define DDRDATA4CH0_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_MAX    (0x00FFFFFF)
+  #define DDRDATA4CH0_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_DEF    (0x00000000)
+  #define DDRDATA4CH0_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_OFF        (24)
+  #define DDRDATA4CH0_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_WID        ( 8)
+  #define DDRDATA4CH0_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_MSK        (0xFF000000)
+  #define DDRDATA4CH0_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_MAX        (0x000000FF)
+  #define DDRDATA4CH0_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_DEF        (0x00000000)
+
+#define DDRDATA4CH0_CR_DDRCRDATAOFFSETTRAIN_REG                      (0x00000870)
+  #define DDRDATA4CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_OFF          ( 0)
+  #define DDRDATA4CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_WID          ( 6)
+  #define DDRDATA4CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MSK          (0x0000003F)
+  #define DDRDATA4CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MAX          (0x0000003F)
+  #define DDRDATA4CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_DEF          (0x00000000)
+  #define DDRDATA4CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_OFF          ( 6)
+  #define DDRDATA4CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_WID          ( 6)
+  #define DDRDATA4CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MSK          (0x00000FC0)
+  #define DDRDATA4CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MAX          (0x0000003F)
+  #define DDRDATA4CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_DEF          (0x00000000)
+  #define DDRDATA4CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_OFF           (12)
+  #define DDRDATA4CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_WID           ( 6)
+  #define DDRDATA4CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MSK           (0x0003F000)
+  #define DDRDATA4CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MAX           (0x0000003F)
+  #define DDRDATA4CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_DEF           (0x00000000)
+  #define DDRDATA4CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_OFF          (18)
+  #define DDRDATA4CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_WID          ( 6)
+  #define DDRDATA4CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MSK          (0x00FC0000)
+  #define DDRDATA4CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MAX          (0x0000003F)
+  #define DDRDATA4CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_DEF          (0x00000000)
+  #define DDRDATA4CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_OFF           (24)
+  #define DDRDATA4CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_WID           ( 7)
+  #define DDRDATA4CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MSK           (0x7F000000)
+  #define DDRDATA4CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MAX           (0x0000007F)
+  #define DDRDATA4CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_DEF           (0x00000000)
+  #define DDRDATA4CH0_CR_DDRCRDATAOFFSETTRAIN_Spare_OFF                (31)
+  #define DDRDATA4CH0_CR_DDRCRDATAOFFSETTRAIN_Spare_WID                ( 1)
+  #define DDRDATA4CH0_CR_DDRCRDATAOFFSETTRAIN_Spare_MSK                (0x80000000)
+  #define DDRDATA4CH0_CR_DDRCRDATAOFFSETTRAIN_Spare_MAX                (0x00000001)
+  #define DDRDATA4CH0_CR_DDRCRDATAOFFSETTRAIN_Spare_DEF                (0x00000000)
+
+#define DDRDATA4CH0_CR_DDRCRDATACONTROL0_REG                         (0x00000874)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_OFF          ( 0)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_WID          ( 1)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_MSK          (0x00000001)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_MAX          (0x00000001)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_DEF          (0x00000000)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_OFF          ( 1)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_WID          ( 1)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_MSK          (0x00000002)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_MAX          (0x00000001)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_DEF          (0x00000000)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_OFF          ( 2)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_WID          ( 1)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_MSK          (0x00000004)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_MAX          (0x00000001)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_DEF          (0x00000000)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_OFF    ( 3)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_WID    ( 1)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MSK    (0x00000008)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MAX    (0x00000001)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_DEF    (0x00000000)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_TxOn_OFF                    ( 4)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_TxOn_WID                    ( 1)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_TxOn_MSK                    (0x00000010)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_TxOn_MAX                    (0x00000001)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_TxOn_DEF                    (0x00000000)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RfOn_OFF                    ( 5)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RfOn_WID                    ( 1)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RfOn_MSK                    (0x00000020)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RfOn_MAX                    (0x00000001)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RfOn_DEF                    (0x00000000)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RxPiOn_OFF                  ( 6)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RxPiOn_WID                  ( 1)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RxPiOn_MSK                  (0x00000040)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RxPiOn_MAX                  (0x00000001)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RxPiOn_DEF                  (0x00000000)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_TxPiOn_OFF                  ( 7)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_TxPiOn_WID                  ( 1)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_TxPiOn_MSK                  (0x00000080)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_TxPiOn_MAX                  (0x00000001)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_TxPiOn_DEF                  (0x00000000)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_OFF        ( 8)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_WID        ( 1)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_MSK        (0x00000100)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_MAX        (0x00000001)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_DEF        (0x00000000)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_OFF        ( 9)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_WID        ( 1)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MSK        (0x00000200)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MAX        (0x00000001)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_DEF        (0x00000000)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_TxDisable_OFF               (10)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_TxDisable_WID               ( 1)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_TxDisable_MSK               (0x00000400)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_TxDisable_MAX               (0x00000001)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_TxDisable_DEF               (0x00000000)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RxDisable_OFF               (11)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RxDisable_WID               ( 1)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RxDisable_MSK               (0x00000800)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RxDisable_MAX               (0x00000001)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RxDisable_DEF               (0x00000000)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_TxLong_OFF                  (12)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_TxLong_WID                  ( 1)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_TxLong_MSK                  (0x00001000)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_TxLong_MAX                  (0x00000001)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_TxLong_DEF                  (0x00000000)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_OFF               (13)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_WID               ( 2)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_MSK               (0x00006000)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_MAX               (0x00000003)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_DEF               (0x00000000)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RxReadPointer_OFF           (15)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RxReadPointer_WID           ( 3)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RxReadPointer_MSK           (0x00038000)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RxReadPointer_MAX           (0x00000007)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RxReadPointer_DEF           (0x00000000)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_DriverSegmentEnable_OFF     (18)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_DriverSegmentEnable_WID     ( 1)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_DriverSegmentEnable_MSK     (0x00040000)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_DriverSegmentEnable_MAX     (0x00000001)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_DriverSegmentEnable_DEF     (0x00000000)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_DataVccddqHi_OFF            (19)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_DataVccddqHi_WID            ( 1)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_DataVccddqHi_MSK            (0x00080000)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_DataVccddqHi_MAX            (0x00000001)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_DataVccddqHi_DEF            (0x00000000)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_ReadRFRd_OFF                (20)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_ReadRFRd_WID                ( 1)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_ReadRFRd_MSK                (0x00100000)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_ReadRFRd_MAX                (0x00000001)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_ReadRFRd_DEF                (0x00000000)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_ReadRFWr_OFF                (21)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_ReadRFWr_WID                ( 1)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_ReadRFWr_MSK                (0x00200000)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_ReadRFWr_MAX                (0x00000001)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_ReadRFWr_DEF                (0x00000000)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_ReadRFRank_OFF              (22)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_ReadRFRank_WID              ( 2)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_ReadRFRank_MSK              (0x00C00000)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_ReadRFRank_MAX              (0x00000003)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_ReadRFRank_DEF              (0x00000000)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_OFF              (24)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_WID              ( 1)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_MSK              (0x01000000)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_MAX              (0x00000001)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_DEF              (0x00000000)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_OdtSampOff_OFF              (25)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_OdtSampOff_WID              ( 1)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_OdtSampOff_MSK              (0x02000000)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_OdtSampOff_MAX              (0x00000001)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_OdtSampOff_DEF              (0x00000000)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_OFF        (26)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_WID        ( 1)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_MSK        (0x04000000)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_MAX        (0x00000001)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_DEF        (0x00000000)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_OFF         (27)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_WID         ( 1)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MSK         (0x08000000)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MAX         (0x00000001)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_DEF         (0x00000000)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_OFF              (28)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_WID              ( 1)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_MSK              (0x10000000)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_MAX              (0x00000001)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_DEF              (0x00000000)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_EnReadPreamble_OFF          (29)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_EnReadPreamble_WID          ( 1)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_EnReadPreamble_MSK          (0x20000000)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_EnReadPreamble_MAX          (0x00000001)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_EnReadPreamble_DEF          (0x00000000)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_OFF         (30)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_WID         ( 1)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MSK         (0x40000000)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MAX         (0x00000001)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_DEF         (0x00000000)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_OFF            (31)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_WID            ( 1)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_MSK            (0x80000000)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_MAX            (0x00000001)
+  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_DEF            (0x00000000)
+
+#define DDRDATA4CH0_CR_DDRCRVREFADJUST1_REG                          (0x00000878)
+  #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_CAVrefCtl_OFF                ( 0)
+  #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_CAVrefCtl_WID                ( 7)
+  #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_CAVrefCtl_MSK                (0x0000007F)
+  #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_CAVrefCtl_MAX                (0x0000007F)
+  #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_CAVrefCtl_DEF                (0x00000000)
+  #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_Ch1VrefCtl_OFF               ( 7)
+  #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_Ch1VrefCtl_WID               ( 7)
+  #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_Ch1VrefCtl_MSK               (0x00003F80)
+  #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_Ch1VrefCtl_MAX               (0x0000007F)
+  #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_Ch1VrefCtl_DEF               (0x00000000)
+  #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_Ch0VrefCtl_OFF               (14)
+  #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_Ch0VrefCtl_WID               ( 7)
+  #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_Ch0VrefCtl_MSK               (0x001FC000)
+  #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_Ch0VrefCtl_MAX               (0x0000007F)
+  #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_Ch0VrefCtl_DEF               (0x00000000)
+  #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCA_OFF             (21)
+  #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCA_WID             ( 1)
+  #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCA_MSK             (0x00200000)
+  #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCA_MAX             (0x00000001)
+  #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCA_DEF             (0x00000000)
+  #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_OFF            (22)
+  #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_WID            ( 1)
+  #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_MSK            (0x00400000)
+  #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_MAX            (0x00000001)
+  #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_DEF            (0x00000000)
+  #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_OFF            (23)
+  #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_WID            ( 1)
+  #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_MSK            (0x00800000)
+  #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_MAX            (0x00000001)
+  #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_DEF            (0x00000000)
+  #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_HiZTimerCtrl_OFF             (24)
+  #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_HiZTimerCtrl_WID             ( 2)
+  #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_HiZTimerCtrl_MSK             (0x03000000)
+  #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_HiZTimerCtrl_MAX             (0x00000003)
+  #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_HiZTimerCtrl_DEF             (0x00000000)
+  #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_OFF            (26)
+  #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_WID            ( 1)
+  #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_MSK            (0x04000000)
+  #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_MAX            (0x00000001)
+  #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_DEF            (0x00000000)
+  #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_Rsvd_OFF                     (27)
+  #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_Rsvd_WID                     ( 2)
+  #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_Rsvd_MSK                     (0x18000000)
+  #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_Rsvd_MAX                     (0x00000003)
+  #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_Rsvd_DEF                     (0x00000000)
+  #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_caSlowBW_OFF                 (29)
+  #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_caSlowBW_WID                 ( 1)
+  #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_caSlowBW_MSK                 (0x20000000)
+  #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_caSlowBW_MAX                 (0x00000001)
+  #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_caSlowBW_DEF                 (0x00000000)
+  #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_ch0SlowBW_OFF                (30)
+  #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_ch0SlowBW_WID                ( 1)
+  #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_ch0SlowBW_MSK                (0x40000000)
+  #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_ch0SlowBW_MAX                (0x00000001)
+  #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_ch0SlowBW_DEF                (0x00000000)
+  #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_ch1SlowBW_OFF                (31)
+  #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_ch1SlowBW_WID                ( 1)
+  #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_ch1SlowBW_MSK                (0x80000000)
+  #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_ch1SlowBW_MAX                (0x00000001)
+  #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_ch1SlowBW_DEF                (0x00000000)
+
+#define DDRDATA4CH1_CR_RXTRAINRANK0_REG                              (0x00000900)
+  #define DDRDATA4CH1_CR_RXTRAINRANK0_RxRcvEnPi_OFF                    ( 0)
+  #define DDRDATA4CH1_CR_RXTRAINRANK0_RxRcvEnPi_WID                    ( 9)
+  #define DDRDATA4CH1_CR_RXTRAINRANK0_RxRcvEnPi_MSK                    (0x000001FF)
+  #define DDRDATA4CH1_CR_RXTRAINRANK0_RxRcvEnPi_MAX                    (0x000001FF)
+  #define DDRDATA4CH1_CR_RXTRAINRANK0_RxDqsPPi_OFF                     ( 9)
+  #define DDRDATA4CH1_CR_RXTRAINRANK0_RxDqsPPi_WID                     ( 6)
+  #define DDRDATA4CH1_CR_RXTRAINRANK0_RxDqsPPi_MSK                     (0x00007E00)
+  #define DDRDATA4CH1_CR_RXTRAINRANK0_RxDqsPPi_MAX                     (0x0000003F)
+  #define DDRDATA4CH1_CR_RXTRAINRANK0_RxEq_OFF                         (15)
+  #define DDRDATA4CH1_CR_RXTRAINRANK0_RxEq_WID                         ( 5)
+  #define DDRDATA4CH1_CR_RXTRAINRANK0_RxEq_MSK                         (0x000F8000)
+  #define DDRDATA4CH1_CR_RXTRAINRANK0_RxEq_MAX                         (0x0000001F)
+  #define DDRDATA4CH1_CR_RXTRAINRANK0_RxDqsNPi_OFF                     (20)
+  #define DDRDATA4CH1_CR_RXTRAINRANK0_RxDqsNPi_WID                     ( 6)
+  #define DDRDATA4CH1_CR_RXTRAINRANK0_RxDqsNPi_MSK                     (0x03F00000)
+  #define DDRDATA4CH1_CR_RXTRAINRANK0_RxDqsNPi_MAX                     (0x0000003F)
+  #define DDRDATA4CH1_CR_RXTRAINRANK0_RxVref_OFF                       (26)
+  #define DDRDATA4CH1_CR_RXTRAINRANK0_RxVref_WID                       ( 6)
+  #define DDRDATA4CH1_CR_RXTRAINRANK0_RxVref_MSK                       (0xFC000000)
+  #define DDRDATA4CH1_CR_RXTRAINRANK0_RxVref_MAX                       (0x0000003F)
+
+#define DDRDATA4CH1_CR_RXTRAINRANK1_REG                              (0x00000904)
+  #define DDRDATA4CH1_CR_RXTRAINRANK1_RxRcvEnPi_OFF                    ( 0)
+  #define DDRDATA4CH1_CR_RXTRAINRANK1_RxRcvEnPi_WID                    ( 9)
+  #define DDRDATA4CH1_CR_RXTRAINRANK1_RxRcvEnPi_MSK                    (0x000001FF)
+  #define DDRDATA4CH1_CR_RXTRAINRANK1_RxRcvEnPi_MAX                    (0x000001FF)
+  #define DDRDATA4CH1_CR_RXTRAINRANK1_RxDqsPPi_OFF                     ( 9)
+  #define DDRDATA4CH1_CR_RXTRAINRANK1_RxDqsPPi_WID                     ( 6)
+  #define DDRDATA4CH1_CR_RXTRAINRANK1_RxDqsPPi_MSK                     (0x00007E00)
+  #define DDRDATA4CH1_CR_RXTRAINRANK1_RxDqsPPi_MAX                     (0x0000003F)
+  #define DDRDATA4CH1_CR_RXTRAINRANK1_RxEq_OFF                         (15)
+  #define DDRDATA4CH1_CR_RXTRAINRANK1_RxEq_WID                         ( 5)
+  #define DDRDATA4CH1_CR_RXTRAINRANK1_RxEq_MSK                         (0x000F8000)
+  #define DDRDATA4CH1_CR_RXTRAINRANK1_RxEq_MAX                         (0x0000001F)
+  #define DDRDATA4CH1_CR_RXTRAINRANK1_RxDqsNPi_OFF                     (20)
+  #define DDRDATA4CH1_CR_RXTRAINRANK1_RxDqsNPi_WID                     ( 6)
+  #define DDRDATA4CH1_CR_RXTRAINRANK1_RxDqsNPi_MSK                     (0x03F00000)
+  #define DDRDATA4CH1_CR_RXTRAINRANK1_RxDqsNPi_MAX                     (0x0000003F)
+  #define DDRDATA4CH1_CR_RXTRAINRANK1_RxVref_OFF                       (26)
+  #define DDRDATA4CH1_CR_RXTRAINRANK1_RxVref_WID                       ( 6)
+  #define DDRDATA4CH1_CR_RXTRAINRANK1_RxVref_MSK                       (0xFC000000)
+  #define DDRDATA4CH1_CR_RXTRAINRANK1_RxVref_MAX                       (0x0000003F)
+
+#define DDRDATA4CH1_CR_RXTRAINRANK2_REG                              (0x00000908)
+  #define DDRDATA4CH1_CR_RXTRAINRANK2_RxRcvEnPi_OFF                    ( 0)
+  #define DDRDATA4CH1_CR_RXTRAINRANK2_RxRcvEnPi_WID                    ( 9)
+  #define DDRDATA4CH1_CR_RXTRAINRANK2_RxRcvEnPi_MSK                    (0x000001FF)
+  #define DDRDATA4CH1_CR_RXTRAINRANK2_RxRcvEnPi_MAX                    (0x000001FF)
+  #define DDRDATA4CH1_CR_RXTRAINRANK2_RxDqsPPi_OFF                     ( 9)
+  #define DDRDATA4CH1_CR_RXTRAINRANK2_RxDqsPPi_WID                     ( 6)
+  #define DDRDATA4CH1_CR_RXTRAINRANK2_RxDqsPPi_MSK                     (0x00007E00)
+  #define DDRDATA4CH1_CR_RXTRAINRANK2_RxDqsPPi_MAX                     (0x0000003F)
+  #define DDRDATA4CH1_CR_RXTRAINRANK2_RxEq_OFF                         (15)
+  #define DDRDATA4CH1_CR_RXTRAINRANK2_RxEq_WID                         ( 5)
+  #define DDRDATA4CH1_CR_RXTRAINRANK2_RxEq_MSK                         (0x000F8000)
+  #define DDRDATA4CH1_CR_RXTRAINRANK2_RxEq_MAX                         (0x0000001F)
+  #define DDRDATA4CH1_CR_RXTRAINRANK2_RxDqsNPi_OFF                     (20)
+  #define DDRDATA4CH1_CR_RXTRAINRANK2_RxDqsNPi_WID                     ( 6)
+  #define DDRDATA4CH1_CR_RXTRAINRANK2_RxDqsNPi_MSK                     (0x03F00000)
+  #define DDRDATA4CH1_CR_RXTRAINRANK2_RxDqsNPi_MAX                     (0x0000003F)
+  #define DDRDATA4CH1_CR_RXTRAINRANK2_RxVref_OFF                       (26)
+  #define DDRDATA4CH1_CR_RXTRAINRANK2_RxVref_WID                       ( 6)
+  #define DDRDATA4CH1_CR_RXTRAINRANK2_RxVref_MSK                       (0xFC000000)
+  #define DDRDATA4CH1_CR_RXTRAINRANK2_RxVref_MAX                       (0x0000003F)
+
+#define DDRDATA4CH1_CR_RXTRAINRANK3_REG                              (0x0000090C)
+  #define DDRDATA4CH1_CR_RXTRAINRANK3_RxRcvEnPi_OFF                    ( 0)
+  #define DDRDATA4CH1_CR_RXTRAINRANK3_RxRcvEnPi_WID                    ( 9)
+  #define DDRDATA4CH1_CR_RXTRAINRANK3_RxRcvEnPi_MSK                    (0x000001FF)
+  #define DDRDATA4CH1_CR_RXTRAINRANK3_RxRcvEnPi_MAX                    (0x000001FF)
+  #define DDRDATA4CH1_CR_RXTRAINRANK3_RxDqsPPi_OFF                     ( 9)
+  #define DDRDATA4CH1_CR_RXTRAINRANK3_RxDqsPPi_WID                     ( 6)
+  #define DDRDATA4CH1_CR_RXTRAINRANK3_RxDqsPPi_MSK                     (0x00007E00)
+  #define DDRDATA4CH1_CR_RXTRAINRANK3_RxDqsPPi_MAX                     (0x0000003F)
+  #define DDRDATA4CH1_CR_RXTRAINRANK3_RxEq_OFF                         (15)
+  #define DDRDATA4CH1_CR_RXTRAINRANK3_RxEq_WID                         ( 5)
+  #define DDRDATA4CH1_CR_RXTRAINRANK3_RxEq_MSK                         (0x000F8000)
+  #define DDRDATA4CH1_CR_RXTRAINRANK3_RxEq_MAX                         (0x0000001F)
+  #define DDRDATA4CH1_CR_RXTRAINRANK3_RxDqsNPi_OFF                     (20)
+  #define DDRDATA4CH1_CR_RXTRAINRANK3_RxDqsNPi_WID                     ( 6)
+  #define DDRDATA4CH1_CR_RXTRAINRANK3_RxDqsNPi_MSK                     (0x03F00000)
+  #define DDRDATA4CH1_CR_RXTRAINRANK3_RxDqsNPi_MAX                     (0x0000003F)
+  #define DDRDATA4CH1_CR_RXTRAINRANK3_RxVref_OFF                       (26)
+  #define DDRDATA4CH1_CR_RXTRAINRANK3_RxVref_WID                       ( 6)
+  #define DDRDATA4CH1_CR_RXTRAINRANK3_RxVref_MSK                       (0xFC000000)
+  #define DDRDATA4CH1_CR_RXTRAINRANK3_RxVref_MAX                       (0x0000003F)
+
+#define DDRDATA4CH1_CR_RXPERBITRANK0_REG                             (0x00000910)
+  #define DDRDATA4CH1_CR_RXPERBITRANK0_Lane0_OFF                       ( 0)
+  #define DDRDATA4CH1_CR_RXPERBITRANK0_Lane0_WID                       ( 4)
+  #define DDRDATA4CH1_CR_RXPERBITRANK0_Lane0_MSK                       (0x0000000F)
+  #define DDRDATA4CH1_CR_RXPERBITRANK0_Lane0_MAX                       (0x0000000F)
+  #define DDRDATA4CH1_CR_RXPERBITRANK0_Lane1_OFF                       ( 4)
+  #define DDRDATA4CH1_CR_RXPERBITRANK0_Lane1_WID                       ( 4)
+  #define DDRDATA4CH1_CR_RXPERBITRANK0_Lane1_MSK                       (0x000000F0)
+  #define DDRDATA4CH1_CR_RXPERBITRANK0_Lane1_MAX                       (0x0000000F)
+  #define DDRDATA4CH1_CR_RXPERBITRANK0_Lane2_OFF                       ( 8)
+  #define DDRDATA4CH1_CR_RXPERBITRANK0_Lane2_WID                       ( 4)
+  #define DDRDATA4CH1_CR_RXPERBITRANK0_Lane2_MSK                       (0x00000F00)
+  #define DDRDATA4CH1_CR_RXPERBITRANK0_Lane2_MAX                       (0x0000000F)
+  #define DDRDATA4CH1_CR_RXPERBITRANK0_Lane3_OFF                       (12)
+  #define DDRDATA4CH1_CR_RXPERBITRANK0_Lane3_WID                       ( 4)
+  #define DDRDATA4CH1_CR_RXPERBITRANK0_Lane3_MSK                       (0x0000F000)
+  #define DDRDATA4CH1_CR_RXPERBITRANK0_Lane3_MAX                       (0x0000000F)
+  #define DDRDATA4CH1_CR_RXPERBITRANK0_Lane4_OFF                       (16)
+  #define DDRDATA4CH1_CR_RXPERBITRANK0_Lane4_WID                       ( 4)
+  #define DDRDATA4CH1_CR_RXPERBITRANK0_Lane4_MSK                       (0x000F0000)
+  #define DDRDATA4CH1_CR_RXPERBITRANK0_Lane4_MAX                       (0x0000000F)
+  #define DDRDATA4CH1_CR_RXPERBITRANK0_Lane5_OFF                       (20)
+  #define DDRDATA4CH1_CR_RXPERBITRANK0_Lane5_WID                       ( 4)
+  #define DDRDATA4CH1_CR_RXPERBITRANK0_Lane5_MSK                       (0x00F00000)
+  #define DDRDATA4CH1_CR_RXPERBITRANK0_Lane5_MAX                       (0x0000000F)
+  #define DDRDATA4CH1_CR_RXPERBITRANK0_Lane6_OFF                       (24)
+  #define DDRDATA4CH1_CR_RXPERBITRANK0_Lane6_WID                       ( 4)
+  #define DDRDATA4CH1_CR_RXPERBITRANK0_Lane6_MSK                       (0x0F000000)
+  #define DDRDATA4CH1_CR_RXPERBITRANK0_Lane6_MAX                       (0x0000000F)
+  #define DDRDATA4CH1_CR_RXPERBITRANK0_Lane7_OFF                       (28)
+  #define DDRDATA4CH1_CR_RXPERBITRANK0_Lane7_WID                       ( 4)
+  #define DDRDATA4CH1_CR_RXPERBITRANK0_Lane7_MSK                       (0xF0000000)
+  #define DDRDATA4CH1_CR_RXPERBITRANK0_Lane7_MAX                       (0x0000000F)
+
+#define DDRDATA4CH1_CR_RXPERBITRANK1_REG                             (0x00000914)
+  #define DDRDATA4CH1_CR_RXPERBITRANK1_Lane0_OFF                       ( 0)
+  #define DDRDATA4CH1_CR_RXPERBITRANK1_Lane0_WID                       ( 4)
+  #define DDRDATA4CH1_CR_RXPERBITRANK1_Lane0_MSK                       (0x0000000F)
+  #define DDRDATA4CH1_CR_RXPERBITRANK1_Lane0_MAX                       (0x0000000F)
+  #define DDRDATA4CH1_CR_RXPERBITRANK1_Lane1_OFF                       ( 4)
+  #define DDRDATA4CH1_CR_RXPERBITRANK1_Lane1_WID                       ( 4)
+  #define DDRDATA4CH1_CR_RXPERBITRANK1_Lane1_MSK                       (0x000000F0)
+  #define DDRDATA4CH1_CR_RXPERBITRANK1_Lane1_MAX                       (0x0000000F)
+  #define DDRDATA4CH1_CR_RXPERBITRANK1_Lane2_OFF                       ( 8)
+  #define DDRDATA4CH1_CR_RXPERBITRANK1_Lane2_WID                       ( 4)
+  #define DDRDATA4CH1_CR_RXPERBITRANK1_Lane2_MSK                       (0x00000F00)
+  #define DDRDATA4CH1_CR_RXPERBITRANK1_Lane2_MAX                       (0x0000000F)
+  #define DDRDATA4CH1_CR_RXPERBITRANK1_Lane3_OFF                       (12)
+  #define DDRDATA4CH1_CR_RXPERBITRANK1_Lane3_WID                       ( 4)
+  #define DDRDATA4CH1_CR_RXPERBITRANK1_Lane3_MSK                       (0x0000F000)
+  #define DDRDATA4CH1_CR_RXPERBITRANK1_Lane3_MAX                       (0x0000000F)
+  #define DDRDATA4CH1_CR_RXPERBITRANK1_Lane4_OFF                       (16)
+  #define DDRDATA4CH1_CR_RXPERBITRANK1_Lane4_WID                       ( 4)
+  #define DDRDATA4CH1_CR_RXPERBITRANK1_Lane4_MSK                       (0x000F0000)
+  #define DDRDATA4CH1_CR_RXPERBITRANK1_Lane4_MAX                       (0x0000000F)
+  #define DDRDATA4CH1_CR_RXPERBITRANK1_Lane5_OFF                       (20)
+  #define DDRDATA4CH1_CR_RXPERBITRANK1_Lane5_WID                       ( 4)
+  #define DDRDATA4CH1_CR_RXPERBITRANK1_Lane5_MSK                       (0x00F00000)
+  #define DDRDATA4CH1_CR_RXPERBITRANK1_Lane5_MAX                       (0x0000000F)
+  #define DDRDATA4CH1_CR_RXPERBITRANK1_Lane6_OFF                       (24)
+  #define DDRDATA4CH1_CR_RXPERBITRANK1_Lane6_WID                       ( 4)
+  #define DDRDATA4CH1_CR_RXPERBITRANK1_Lane6_MSK                       (0x0F000000)
+  #define DDRDATA4CH1_CR_RXPERBITRANK1_Lane6_MAX                       (0x0000000F)
+  #define DDRDATA4CH1_CR_RXPERBITRANK1_Lane7_OFF                       (28)
+  #define DDRDATA4CH1_CR_RXPERBITRANK1_Lane7_WID                       ( 4)
+  #define DDRDATA4CH1_CR_RXPERBITRANK1_Lane7_MSK                       (0xF0000000)
+  #define DDRDATA4CH1_CR_RXPERBITRANK1_Lane7_MAX                       (0x0000000F)
+
+#define DDRDATA4CH1_CR_RXPERBITRANK2_REG                             (0x00000918)
+  #define DDRDATA4CH1_CR_RXPERBITRANK2_Lane0_OFF                       ( 0)
+  #define DDRDATA4CH1_CR_RXPERBITRANK2_Lane0_WID                       ( 4)
+  #define DDRDATA4CH1_CR_RXPERBITRANK2_Lane0_MSK                       (0x0000000F)
+  #define DDRDATA4CH1_CR_RXPERBITRANK2_Lane0_MAX                       (0x0000000F)
+  #define DDRDATA4CH1_CR_RXPERBITRANK2_Lane1_OFF                       ( 4)
+  #define DDRDATA4CH1_CR_RXPERBITRANK2_Lane1_WID                       ( 4)
+  #define DDRDATA4CH1_CR_RXPERBITRANK2_Lane1_MSK                       (0x000000F0)
+  #define DDRDATA4CH1_CR_RXPERBITRANK2_Lane1_MAX                       (0x0000000F)
+  #define DDRDATA4CH1_CR_RXPERBITRANK2_Lane2_OFF                       ( 8)
+  #define DDRDATA4CH1_CR_RXPERBITRANK2_Lane2_WID                       ( 4)
+  #define DDRDATA4CH1_CR_RXPERBITRANK2_Lane2_MSK                       (0x00000F00)
+  #define DDRDATA4CH1_CR_RXPERBITRANK2_Lane2_MAX                       (0x0000000F)
+  #define DDRDATA4CH1_CR_RXPERBITRANK2_Lane3_OFF                       (12)
+  #define DDRDATA4CH1_CR_RXPERBITRANK2_Lane3_WID                       ( 4)
+  #define DDRDATA4CH1_CR_RXPERBITRANK2_Lane3_MSK                       (0x0000F000)
+  #define DDRDATA4CH1_CR_RXPERBITRANK2_Lane3_MAX                       (0x0000000F)
+  #define DDRDATA4CH1_CR_RXPERBITRANK2_Lane4_OFF                       (16)
+  #define DDRDATA4CH1_CR_RXPERBITRANK2_Lane4_WID                       ( 4)
+  #define DDRDATA4CH1_CR_RXPERBITRANK2_Lane4_MSK                       (0x000F0000)
+  #define DDRDATA4CH1_CR_RXPERBITRANK2_Lane4_MAX                       (0x0000000F)
+  #define DDRDATA4CH1_CR_RXPERBITRANK2_Lane5_OFF                       (20)
+  #define DDRDATA4CH1_CR_RXPERBITRANK2_Lane5_WID                       ( 4)
+  #define DDRDATA4CH1_CR_RXPERBITRANK2_Lane5_MSK                       (0x00F00000)
+  #define DDRDATA4CH1_CR_RXPERBITRANK2_Lane5_MAX                       (0x0000000F)
+  #define DDRDATA4CH1_CR_RXPERBITRANK2_Lane6_OFF                       (24)
+  #define DDRDATA4CH1_CR_RXPERBITRANK2_Lane6_WID                       ( 4)
+  #define DDRDATA4CH1_CR_RXPERBITRANK2_Lane6_MSK                       (0x0F000000)
+  #define DDRDATA4CH1_CR_RXPERBITRANK2_Lane6_MAX                       (0x0000000F)
+  #define DDRDATA4CH1_CR_RXPERBITRANK2_Lane7_OFF                       (28)
+  #define DDRDATA4CH1_CR_RXPERBITRANK2_Lane7_WID                       ( 4)
+  #define DDRDATA4CH1_CR_RXPERBITRANK2_Lane7_MSK                       (0xF0000000)
+  #define DDRDATA4CH1_CR_RXPERBITRANK2_Lane7_MAX                       (0x0000000F)
+
+#define DDRDATA4CH1_CR_RXPERBITRANK3_REG                             (0x0000091C)
+  #define DDRDATA4CH1_CR_RXPERBITRANK3_Lane0_OFF                       ( 0)
+  #define DDRDATA4CH1_CR_RXPERBITRANK3_Lane0_WID                       ( 4)
+  #define DDRDATA4CH1_CR_RXPERBITRANK3_Lane0_MSK                       (0x0000000F)
+  #define DDRDATA4CH1_CR_RXPERBITRANK3_Lane0_MAX                       (0x0000000F)
+  #define DDRDATA4CH1_CR_RXPERBITRANK3_Lane1_OFF                       ( 4)
+  #define DDRDATA4CH1_CR_RXPERBITRANK3_Lane1_WID                       ( 4)
+  #define DDRDATA4CH1_CR_RXPERBITRANK3_Lane1_MSK                       (0x000000F0)
+  #define DDRDATA4CH1_CR_RXPERBITRANK3_Lane1_MAX                       (0x0000000F)
+  #define DDRDATA4CH1_CR_RXPERBITRANK3_Lane2_OFF                       ( 8)
+  #define DDRDATA4CH1_CR_RXPERBITRANK3_Lane2_WID                       ( 4)
+  #define DDRDATA4CH1_CR_RXPERBITRANK3_Lane2_MSK                       (0x00000F00)
+  #define DDRDATA4CH1_CR_RXPERBITRANK3_Lane2_MAX                       (0x0000000F)
+  #define DDRDATA4CH1_CR_RXPERBITRANK3_Lane3_OFF                       (12)
+  #define DDRDATA4CH1_CR_RXPERBITRANK3_Lane3_WID                       ( 4)
+  #define DDRDATA4CH1_CR_RXPERBITRANK3_Lane3_MSK                       (0x0000F000)
+  #define DDRDATA4CH1_CR_RXPERBITRANK3_Lane3_MAX                       (0x0000000F)
+  #define DDRDATA4CH1_CR_RXPERBITRANK3_Lane4_OFF                       (16)
+  #define DDRDATA4CH1_CR_RXPERBITRANK3_Lane4_WID                       ( 4)
+  #define DDRDATA4CH1_CR_RXPERBITRANK3_Lane4_MSK                       (0x000F0000)
+  #define DDRDATA4CH1_CR_RXPERBITRANK3_Lane4_MAX                       (0x0000000F)
+  #define DDRDATA4CH1_CR_RXPERBITRANK3_Lane5_OFF                       (20)
+  #define DDRDATA4CH1_CR_RXPERBITRANK3_Lane5_WID                       ( 4)
+  #define DDRDATA4CH1_CR_RXPERBITRANK3_Lane5_MSK                       (0x00F00000)
+  #define DDRDATA4CH1_CR_RXPERBITRANK3_Lane5_MAX                       (0x0000000F)
+  #define DDRDATA4CH1_CR_RXPERBITRANK3_Lane6_OFF                       (24)
+  #define DDRDATA4CH1_CR_RXPERBITRANK3_Lane6_WID                       ( 4)
+  #define DDRDATA4CH1_CR_RXPERBITRANK3_Lane6_MSK                       (0x0F000000)
+  #define DDRDATA4CH1_CR_RXPERBITRANK3_Lane6_MAX                       (0x0000000F)
+  #define DDRDATA4CH1_CR_RXPERBITRANK3_Lane7_OFF                       (28)
+  #define DDRDATA4CH1_CR_RXPERBITRANK3_Lane7_WID                       ( 4)
+  #define DDRDATA4CH1_CR_RXPERBITRANK3_Lane7_MSK                       (0xF0000000)
+  #define DDRDATA4CH1_CR_RXPERBITRANK3_Lane7_MAX                       (0x0000000F)
+
+#define DDRDATA4CH1_CR_TXTRAINRANK0_REG                              (0x00000920)
+  #define DDRDATA4CH1_CR_TXTRAINRANK0_TxDqDelay_OFF                    ( 0)
+  #define DDRDATA4CH1_CR_TXTRAINRANK0_TxDqDelay_WID                    ( 9)
+  #define DDRDATA4CH1_CR_TXTRAINRANK0_TxDqDelay_MSK                    (0x000001FF)
+  #define DDRDATA4CH1_CR_TXTRAINRANK0_TxDqDelay_MAX                    (0x000001FF)
+  #define DDRDATA4CH1_CR_TXTRAINRANK0_TxDqsDelay_OFF                   ( 9)
+  #define DDRDATA4CH1_CR_TXTRAINRANK0_TxDqsDelay_WID                   ( 9)
+  #define DDRDATA4CH1_CR_TXTRAINRANK0_TxDqsDelay_MSK                   (0x0003FE00)
+  #define DDRDATA4CH1_CR_TXTRAINRANK0_TxDqsDelay_MAX                   (0x000001FF)
+  #define DDRDATA4CH1_CR_TXTRAINRANK0_Spare0_OFF                       (18)
+  #define DDRDATA4CH1_CR_TXTRAINRANK0_Spare0_WID                       ( 2)
+  #define DDRDATA4CH1_CR_TXTRAINRANK0_Spare0_MSK                       (0x000C0000)
+  #define DDRDATA4CH1_CR_TXTRAINRANK0_Spare0_MAX                       (0x00000003)
+  #define DDRDATA4CH1_CR_TXTRAINRANK0_TxEqualization_OFF               (20)
+  #define DDRDATA4CH1_CR_TXTRAINRANK0_TxEqualization_WID               ( 6)
+  #define DDRDATA4CH1_CR_TXTRAINRANK0_TxEqualization_MSK               (0x03F00000)
+  #define DDRDATA4CH1_CR_TXTRAINRANK0_TxEqualization_MAX               (0x0000003F)
+  #define DDRDATA4CH1_CR_TXTRAINRANK0_Spare1_OFF                       (26)
+  #define DDRDATA4CH1_CR_TXTRAINRANK0_Spare1_WID                       ( 6)
+  #define DDRDATA4CH1_CR_TXTRAINRANK0_Spare1_MSK                       (0xFC000000)
+  #define DDRDATA4CH1_CR_TXTRAINRANK0_Spare1_MAX                       (0x0000003F)
+
+#define DDRDATA4CH1_CR_TXTRAINRANK1_REG                              (0x00000924)
+  #define DDRDATA4CH1_CR_TXTRAINRANK1_TxDqDelay_OFF                    ( 0)
+  #define DDRDATA4CH1_CR_TXTRAINRANK1_TxDqDelay_WID                    ( 9)
+  #define DDRDATA4CH1_CR_TXTRAINRANK1_TxDqDelay_MSK                    (0x000001FF)
+  #define DDRDATA4CH1_CR_TXTRAINRANK1_TxDqDelay_MAX                    (0x000001FF)
+  #define DDRDATA4CH1_CR_TXTRAINRANK1_TxDqsDelay_OFF                   ( 9)
+  #define DDRDATA4CH1_CR_TXTRAINRANK1_TxDqsDelay_WID                   ( 9)
+  #define DDRDATA4CH1_CR_TXTRAINRANK1_TxDqsDelay_MSK                   (0x0003FE00)
+  #define DDRDATA4CH1_CR_TXTRAINRANK1_TxDqsDelay_MAX                   (0x000001FF)
+  #define DDRDATA4CH1_CR_TXTRAINRANK1_Spare0_OFF                       (18)
+  #define DDRDATA4CH1_CR_TXTRAINRANK1_Spare0_WID                       ( 2)
+  #define DDRDATA4CH1_CR_TXTRAINRANK1_Spare0_MSK                       (0x000C0000)
+  #define DDRDATA4CH1_CR_TXTRAINRANK1_Spare0_MAX                       (0x00000003)
+  #define DDRDATA4CH1_CR_TXTRAINRANK1_TxEqualization_OFF               (20)
+  #define DDRDATA4CH1_CR_TXTRAINRANK1_TxEqualization_WID               ( 6)
+  #define DDRDATA4CH1_CR_TXTRAINRANK1_TxEqualization_MSK               (0x03F00000)
+  #define DDRDATA4CH1_CR_TXTRAINRANK1_TxEqualization_MAX               (0x0000003F)
+  #define DDRDATA4CH1_CR_TXTRAINRANK1_Spare1_OFF                       (26)
+  #define DDRDATA4CH1_CR_TXTRAINRANK1_Spare1_WID                       ( 6)
+  #define DDRDATA4CH1_CR_TXTRAINRANK1_Spare1_MSK                       (0xFC000000)
+  #define DDRDATA4CH1_CR_TXTRAINRANK1_Spare1_MAX                       (0x0000003F)
+
+#define DDRDATA4CH1_CR_TXTRAINRANK2_REG                              (0x00000928)
+  #define DDRDATA4CH1_CR_TXTRAINRANK2_TxDqDelay_OFF                    ( 0)
+  #define DDRDATA4CH1_CR_TXTRAINRANK2_TxDqDelay_WID                    ( 9)
+  #define DDRDATA4CH1_CR_TXTRAINRANK2_TxDqDelay_MSK                    (0x000001FF)
+  #define DDRDATA4CH1_CR_TXTRAINRANK2_TxDqDelay_MAX                    (0x000001FF)
+  #define DDRDATA4CH1_CR_TXTRAINRANK2_TxDqsDelay_OFF                   ( 9)
+  #define DDRDATA4CH1_CR_TXTRAINRANK2_TxDqsDelay_WID                   ( 9)
+  #define DDRDATA4CH1_CR_TXTRAINRANK2_TxDqsDelay_MSK                   (0x0003FE00)
+  #define DDRDATA4CH1_CR_TXTRAINRANK2_TxDqsDelay_MAX                   (0x000001FF)
+  #define DDRDATA4CH1_CR_TXTRAINRANK2_Spare0_OFF                       (18)
+  #define DDRDATA4CH1_CR_TXTRAINRANK2_Spare0_WID                       ( 2)
+  #define DDRDATA4CH1_CR_TXTRAINRANK2_Spare0_MSK                       (0x000C0000)
+  #define DDRDATA4CH1_CR_TXTRAINRANK2_Spare0_MAX                       (0x00000003)
+  #define DDRDATA4CH1_CR_TXTRAINRANK2_TxEqualization_OFF               (20)
+  #define DDRDATA4CH1_CR_TXTRAINRANK2_TxEqualization_WID               ( 6)
+  #define DDRDATA4CH1_CR_TXTRAINRANK2_TxEqualization_MSK               (0x03F00000)
+  #define DDRDATA4CH1_CR_TXTRAINRANK2_TxEqualization_MAX               (0x0000003F)
+  #define DDRDATA4CH1_CR_TXTRAINRANK2_Spare1_OFF                       (26)
+  #define DDRDATA4CH1_CR_TXTRAINRANK2_Spare1_WID                       ( 6)
+  #define DDRDATA4CH1_CR_TXTRAINRANK2_Spare1_MSK                       (0xFC000000)
+  #define DDRDATA4CH1_CR_TXTRAINRANK2_Spare1_MAX                       (0x0000003F)
+
+#define DDRDATA4CH1_CR_TXTRAINRANK3_REG                              (0x0000092C)
+  #define DDRDATA4CH1_CR_TXTRAINRANK3_TxDqDelay_OFF                    ( 0)
+  #define DDRDATA4CH1_CR_TXTRAINRANK3_TxDqDelay_WID                    ( 9)
+  #define DDRDATA4CH1_CR_TXTRAINRANK3_TxDqDelay_MSK                    (0x000001FF)
+  #define DDRDATA4CH1_CR_TXTRAINRANK3_TxDqDelay_MAX                    (0x000001FF)
+  #define DDRDATA4CH1_CR_TXTRAINRANK3_TxDqsDelay_OFF                   ( 9)
+  #define DDRDATA4CH1_CR_TXTRAINRANK3_TxDqsDelay_WID                   ( 9)
+  #define DDRDATA4CH1_CR_TXTRAINRANK3_TxDqsDelay_MSK                   (0x0003FE00)
+  #define DDRDATA4CH1_CR_TXTRAINRANK3_TxDqsDelay_MAX                   (0x000001FF)
+  #define DDRDATA4CH1_CR_TXTRAINRANK3_Spare0_OFF                       (18)
+  #define DDRDATA4CH1_CR_TXTRAINRANK3_Spare0_WID                       ( 2)
+  #define DDRDATA4CH1_CR_TXTRAINRANK3_Spare0_MSK                       (0x000C0000)
+  #define DDRDATA4CH1_CR_TXTRAINRANK3_Spare0_MAX                       (0x00000003)
+  #define DDRDATA4CH1_CR_TXTRAINRANK3_TxEqualization_OFF               (20)
+  #define DDRDATA4CH1_CR_TXTRAINRANK3_TxEqualization_WID               ( 6)
+  #define DDRDATA4CH1_CR_TXTRAINRANK3_TxEqualization_MSK               (0x03F00000)
+  #define DDRDATA4CH1_CR_TXTRAINRANK3_TxEqualization_MAX               (0x0000003F)
+  #define DDRDATA4CH1_CR_TXTRAINRANK3_Spare1_OFF                       (26)
+  #define DDRDATA4CH1_CR_TXTRAINRANK3_Spare1_WID                       ( 6)
+  #define DDRDATA4CH1_CR_TXTRAINRANK3_Spare1_MSK                       (0xFC000000)
+  #define DDRDATA4CH1_CR_TXTRAINRANK3_Spare1_MAX                       (0x0000003F)
+
+#define DDRDATA4CH1_CR_TXPERBITRANK0_REG                             (0x00000930)
+  #define DDRDATA4CH1_CR_TXPERBITRANK0_Lane0_OFF                       ( 0)
+  #define DDRDATA4CH1_CR_TXPERBITRANK0_Lane0_WID                       ( 4)
+  #define DDRDATA4CH1_CR_TXPERBITRANK0_Lane0_MSK                       (0x0000000F)
+  #define DDRDATA4CH1_CR_TXPERBITRANK0_Lane0_MAX                       (0x0000000F)
+  #define DDRDATA4CH1_CR_TXPERBITRANK0_Lane1_OFF                       ( 4)
+  #define DDRDATA4CH1_CR_TXPERBITRANK0_Lane1_WID                       ( 4)
+  #define DDRDATA4CH1_CR_TXPERBITRANK0_Lane1_MSK                       (0x000000F0)
+  #define DDRDATA4CH1_CR_TXPERBITRANK0_Lane1_MAX                       (0x0000000F)
+  #define DDRDATA4CH1_CR_TXPERBITRANK0_Lane2_OFF                       ( 8)
+  #define DDRDATA4CH1_CR_TXPERBITRANK0_Lane2_WID                       ( 4)
+  #define DDRDATA4CH1_CR_TXPERBITRANK0_Lane2_MSK                       (0x00000F00)
+  #define DDRDATA4CH1_CR_TXPERBITRANK0_Lane2_MAX                       (0x0000000F)
+  #define DDRDATA4CH1_CR_TXPERBITRANK0_Lane3_OFF                       (12)
+  #define DDRDATA4CH1_CR_TXPERBITRANK0_Lane3_WID                       ( 4)
+  #define DDRDATA4CH1_CR_TXPERBITRANK0_Lane3_MSK                       (0x0000F000)
+  #define DDRDATA4CH1_CR_TXPERBITRANK0_Lane3_MAX                       (0x0000000F)
+  #define DDRDATA4CH1_CR_TXPERBITRANK0_Lane4_OFF                       (16)
+  #define DDRDATA4CH1_CR_TXPERBITRANK0_Lane4_WID                       ( 4)
+  #define DDRDATA4CH1_CR_TXPERBITRANK0_Lane4_MSK                       (0x000F0000)
+  #define DDRDATA4CH1_CR_TXPERBITRANK0_Lane4_MAX                       (0x0000000F)
+  #define DDRDATA4CH1_CR_TXPERBITRANK0_Lane5_OFF                       (20)
+  #define DDRDATA4CH1_CR_TXPERBITRANK0_Lane5_WID                       ( 4)
+  #define DDRDATA4CH1_CR_TXPERBITRANK0_Lane5_MSK                       (0x00F00000)
+  #define DDRDATA4CH1_CR_TXPERBITRANK0_Lane5_MAX                       (0x0000000F)
+  #define DDRDATA4CH1_CR_TXPERBITRANK0_Lane6_OFF                       (24)
+  #define DDRDATA4CH1_CR_TXPERBITRANK0_Lane6_WID                       ( 4)
+  #define DDRDATA4CH1_CR_TXPERBITRANK0_Lane6_MSK                       (0x0F000000)
+  #define DDRDATA4CH1_CR_TXPERBITRANK0_Lane6_MAX                       (0x0000000F)
+  #define DDRDATA4CH1_CR_TXPERBITRANK0_Lane7_OFF                       (28)
+  #define DDRDATA4CH1_CR_TXPERBITRANK0_Lane7_WID                       ( 4)
+  #define DDRDATA4CH1_CR_TXPERBITRANK0_Lane7_MSK                       (0xF0000000)
+  #define DDRDATA4CH1_CR_TXPERBITRANK0_Lane7_MAX                       (0x0000000F)
+
+#define DDRDATA4CH1_CR_TXPERBITRANK1_REG                             (0x00000934)
+  #define DDRDATA4CH1_CR_TXPERBITRANK1_Lane0_OFF                       ( 0)
+  #define DDRDATA4CH1_CR_TXPERBITRANK1_Lane0_WID                       ( 4)
+  #define DDRDATA4CH1_CR_TXPERBITRANK1_Lane0_MSK                       (0x0000000F)
+  #define DDRDATA4CH1_CR_TXPERBITRANK1_Lane0_MAX                       (0x0000000F)
+  #define DDRDATA4CH1_CR_TXPERBITRANK1_Lane1_OFF                       ( 4)
+  #define DDRDATA4CH1_CR_TXPERBITRANK1_Lane1_WID                       ( 4)
+  #define DDRDATA4CH1_CR_TXPERBITRANK1_Lane1_MSK                       (0x000000F0)
+  #define DDRDATA4CH1_CR_TXPERBITRANK1_Lane1_MAX                       (0x0000000F)
+  #define DDRDATA4CH1_CR_TXPERBITRANK1_Lane2_OFF                       ( 8)
+  #define DDRDATA4CH1_CR_TXPERBITRANK1_Lane2_WID                       ( 4)
+  #define DDRDATA4CH1_CR_TXPERBITRANK1_Lane2_MSK                       (0x00000F00)
+  #define DDRDATA4CH1_CR_TXPERBITRANK1_Lane2_MAX                       (0x0000000F)
+  #define DDRDATA4CH1_CR_TXPERBITRANK1_Lane3_OFF                       (12)
+  #define DDRDATA4CH1_CR_TXPERBITRANK1_Lane3_WID                       ( 4)
+  #define DDRDATA4CH1_CR_TXPERBITRANK1_Lane3_MSK                       (0x0000F000)
+  #define DDRDATA4CH1_CR_TXPERBITRANK1_Lane3_MAX                       (0x0000000F)
+  #define DDRDATA4CH1_CR_TXPERBITRANK1_Lane4_OFF                       (16)
+  #define DDRDATA4CH1_CR_TXPERBITRANK1_Lane4_WID                       ( 4)
+  #define DDRDATA4CH1_CR_TXPERBITRANK1_Lane4_MSK                       (0x000F0000)
+  #define DDRDATA4CH1_CR_TXPERBITRANK1_Lane4_MAX                       (0x0000000F)
+  #define DDRDATA4CH1_CR_TXPERBITRANK1_Lane5_OFF                       (20)
+  #define DDRDATA4CH1_CR_TXPERBITRANK1_Lane5_WID                       ( 4)
+  #define DDRDATA4CH1_CR_TXPERBITRANK1_Lane5_MSK                       (0x00F00000)
+  #define DDRDATA4CH1_CR_TXPERBITRANK1_Lane5_MAX                       (0x0000000F)
+  #define DDRDATA4CH1_CR_TXPERBITRANK1_Lane6_OFF                       (24)
+  #define DDRDATA4CH1_CR_TXPERBITRANK1_Lane6_WID                       ( 4)
+  #define DDRDATA4CH1_CR_TXPERBITRANK1_Lane6_MSK                       (0x0F000000)
+  #define DDRDATA4CH1_CR_TXPERBITRANK1_Lane6_MAX                       (0x0000000F)
+  #define DDRDATA4CH1_CR_TXPERBITRANK1_Lane7_OFF                       (28)
+  #define DDRDATA4CH1_CR_TXPERBITRANK1_Lane7_WID                       ( 4)
+  #define DDRDATA4CH1_CR_TXPERBITRANK1_Lane7_MSK                       (0xF0000000)
+  #define DDRDATA4CH1_CR_TXPERBITRANK1_Lane7_MAX                       (0x0000000F)
+
+#define DDRDATA4CH1_CR_TXPERBITRANK2_REG                             (0x00000938)
+  #define DDRDATA4CH1_CR_TXPERBITRANK2_Lane0_OFF                       ( 0)
+  #define DDRDATA4CH1_CR_TXPERBITRANK2_Lane0_WID                       ( 4)
+  #define DDRDATA4CH1_CR_TXPERBITRANK2_Lane0_MSK                       (0x0000000F)
+  #define DDRDATA4CH1_CR_TXPERBITRANK2_Lane0_MAX                       (0x0000000F)
+  #define DDRDATA4CH1_CR_TXPERBITRANK2_Lane1_OFF                       ( 4)
+  #define DDRDATA4CH1_CR_TXPERBITRANK2_Lane1_WID                       ( 4)
+  #define DDRDATA4CH1_CR_TXPERBITRANK2_Lane1_MSK                       (0x000000F0)
+  #define DDRDATA4CH1_CR_TXPERBITRANK2_Lane1_MAX                       (0x0000000F)
+  #define DDRDATA4CH1_CR_TXPERBITRANK2_Lane2_OFF                       ( 8)
+  #define DDRDATA4CH1_CR_TXPERBITRANK2_Lane2_WID                       ( 4)
+  #define DDRDATA4CH1_CR_TXPERBITRANK2_Lane2_MSK                       (0x00000F00)
+  #define DDRDATA4CH1_CR_TXPERBITRANK2_Lane2_MAX                       (0x0000000F)
+  #define DDRDATA4CH1_CR_TXPERBITRANK2_Lane3_OFF                       (12)
+  #define DDRDATA4CH1_CR_TXPERBITRANK2_Lane3_WID                       ( 4)
+  #define DDRDATA4CH1_CR_TXPERBITRANK2_Lane3_MSK                       (0x0000F000)
+  #define DDRDATA4CH1_CR_TXPERBITRANK2_Lane3_MAX                       (0x0000000F)
+  #define DDRDATA4CH1_CR_TXPERBITRANK2_Lane4_OFF                       (16)
+  #define DDRDATA4CH1_CR_TXPERBITRANK2_Lane4_WID                       ( 4)
+  #define DDRDATA4CH1_CR_TXPERBITRANK2_Lane4_MSK                       (0x000F0000)
+  #define DDRDATA4CH1_CR_TXPERBITRANK2_Lane4_MAX                       (0x0000000F)
+  #define DDRDATA4CH1_CR_TXPERBITRANK2_Lane5_OFF                       (20)
+  #define DDRDATA4CH1_CR_TXPERBITRANK2_Lane5_WID                       ( 4)
+  #define DDRDATA4CH1_CR_TXPERBITRANK2_Lane5_MSK                       (0x00F00000)
+  #define DDRDATA4CH1_CR_TXPERBITRANK2_Lane5_MAX                       (0x0000000F)
+  #define DDRDATA4CH1_CR_TXPERBITRANK2_Lane6_OFF                       (24)
+  #define DDRDATA4CH1_CR_TXPERBITRANK2_Lane6_WID                       ( 4)
+  #define DDRDATA4CH1_CR_TXPERBITRANK2_Lane6_MSK                       (0x0F000000)
+  #define DDRDATA4CH1_CR_TXPERBITRANK2_Lane6_MAX                       (0x0000000F)
+  #define DDRDATA4CH1_CR_TXPERBITRANK2_Lane7_OFF                       (28)
+  #define DDRDATA4CH1_CR_TXPERBITRANK2_Lane7_WID                       ( 4)
+  #define DDRDATA4CH1_CR_TXPERBITRANK2_Lane7_MSK                       (0xF0000000)
+  #define DDRDATA4CH1_CR_TXPERBITRANK2_Lane7_MAX                       (0x0000000F)
+
+#define DDRDATA4CH1_CR_TXPERBITRANK3_REG                             (0x0000093C)
+  #define DDRDATA4CH1_CR_TXPERBITRANK3_Lane0_OFF                       ( 0)
+  #define DDRDATA4CH1_CR_TXPERBITRANK3_Lane0_WID                       ( 4)
+  #define DDRDATA4CH1_CR_TXPERBITRANK3_Lane0_MSK                       (0x0000000F)
+  #define DDRDATA4CH1_CR_TXPERBITRANK3_Lane0_MAX                       (0x0000000F)
+  #define DDRDATA4CH1_CR_TXPERBITRANK3_Lane1_OFF                       ( 4)
+  #define DDRDATA4CH1_CR_TXPERBITRANK3_Lane1_WID                       ( 4)
+  #define DDRDATA4CH1_CR_TXPERBITRANK3_Lane1_MSK                       (0x000000F0)
+  #define DDRDATA4CH1_CR_TXPERBITRANK3_Lane1_MAX                       (0x0000000F)
+  #define DDRDATA4CH1_CR_TXPERBITRANK3_Lane2_OFF                       ( 8)
+  #define DDRDATA4CH1_CR_TXPERBITRANK3_Lane2_WID                       ( 4)
+  #define DDRDATA4CH1_CR_TXPERBITRANK3_Lane2_MSK                       (0x00000F00)
+  #define DDRDATA4CH1_CR_TXPERBITRANK3_Lane2_MAX                       (0x0000000F)
+  #define DDRDATA4CH1_CR_TXPERBITRANK3_Lane3_OFF                       (12)
+  #define DDRDATA4CH1_CR_TXPERBITRANK3_Lane3_WID                       ( 4)
+  #define DDRDATA4CH1_CR_TXPERBITRANK3_Lane3_MSK                       (0x0000F000)
+  #define DDRDATA4CH1_CR_TXPERBITRANK3_Lane3_MAX                       (0x0000000F)
+  #define DDRDATA4CH1_CR_TXPERBITRANK3_Lane4_OFF                       (16)
+  #define DDRDATA4CH1_CR_TXPERBITRANK3_Lane4_WID                       ( 4)
+  #define DDRDATA4CH1_CR_TXPERBITRANK3_Lane4_MSK                       (0x000F0000)
+  #define DDRDATA4CH1_CR_TXPERBITRANK3_Lane4_MAX                       (0x0000000F)
+  #define DDRDATA4CH1_CR_TXPERBITRANK3_Lane5_OFF                       (20)
+  #define DDRDATA4CH1_CR_TXPERBITRANK3_Lane5_WID                       ( 4)
+  #define DDRDATA4CH1_CR_TXPERBITRANK3_Lane5_MSK                       (0x00F00000)
+  #define DDRDATA4CH1_CR_TXPERBITRANK3_Lane5_MAX                       (0x0000000F)
+  #define DDRDATA4CH1_CR_TXPERBITRANK3_Lane6_OFF                       (24)
+  #define DDRDATA4CH1_CR_TXPERBITRANK3_Lane6_WID                       ( 4)
+  #define DDRDATA4CH1_CR_TXPERBITRANK3_Lane6_MSK                       (0x0F000000)
+  #define DDRDATA4CH1_CR_TXPERBITRANK3_Lane6_MAX                       (0x0000000F)
+  #define DDRDATA4CH1_CR_TXPERBITRANK3_Lane7_OFF                       (28)
+  #define DDRDATA4CH1_CR_TXPERBITRANK3_Lane7_WID                       ( 4)
+  #define DDRDATA4CH1_CR_TXPERBITRANK3_Lane7_MSK                       (0xF0000000)
+  #define DDRDATA4CH1_CR_TXPERBITRANK3_Lane7_MAX                       (0x0000000F)
+
+#define DDRDATA4CH1_CR_RCOMPDATA0_REG                                (0x00000940)
+  #define DDRDATA4CH1_CR_RCOMPDATA0_RcompDrvUp_OFF                     ( 0)
+  #define DDRDATA4CH1_CR_RCOMPDATA0_RcompDrvUp_WID                     ( 6)
+  #define DDRDATA4CH1_CR_RCOMPDATA0_RcompDrvUp_MSK                     (0x0000003F)
+  #define DDRDATA4CH1_CR_RCOMPDATA0_RcompDrvUp_MAX                     (0x0000003F)
+  #define DDRDATA4CH1_CR_RCOMPDATA0_Spare0_OFF                         ( 6)
+  #define DDRDATA4CH1_CR_RCOMPDATA0_Spare0_WID                         ( 3)
+  #define DDRDATA4CH1_CR_RCOMPDATA0_Spare0_MSK                         (0x000001C0)
+  #define DDRDATA4CH1_CR_RCOMPDATA0_Spare0_MAX                         (0x00000007)
+  #define DDRDATA4CH1_CR_RCOMPDATA0_RcompDrvDown_OFF                   ( 9)
+  #define DDRDATA4CH1_CR_RCOMPDATA0_RcompDrvDown_WID                   ( 6)
+  #define DDRDATA4CH1_CR_RCOMPDATA0_RcompDrvDown_MSK                   (0x00007E00)
+  #define DDRDATA4CH1_CR_RCOMPDATA0_RcompDrvDown_MAX                   (0x0000003F)
+  #define DDRDATA4CH1_CR_RCOMPDATA0_VTComp_OFF                         (15)
+  #define DDRDATA4CH1_CR_RCOMPDATA0_VTComp_WID                         ( 5)
+  #define DDRDATA4CH1_CR_RCOMPDATA0_VTComp_MSK                         (0x000F8000)
+  #define DDRDATA4CH1_CR_RCOMPDATA0_VTComp_MAX                         (0x0000001F)
+  #define DDRDATA4CH1_CR_RCOMPDATA0_TcoComp_OFF                        (20)
+  #define DDRDATA4CH1_CR_RCOMPDATA0_TcoComp_WID                        ( 6)
+  #define DDRDATA4CH1_CR_RCOMPDATA0_TcoComp_MSK                        (0x03F00000)
+  #define DDRDATA4CH1_CR_RCOMPDATA0_TcoComp_MAX                        (0x0000003F)
+  #define DDRDATA4CH1_CR_RCOMPDATA0_SlewRateComp_OFF                   (26)
+  #define DDRDATA4CH1_CR_RCOMPDATA0_SlewRateComp_WID                   ( 5)
+  #define DDRDATA4CH1_CR_RCOMPDATA0_SlewRateComp_MSK                   (0x7C000000)
+  #define DDRDATA4CH1_CR_RCOMPDATA0_SlewRateComp_MAX                   (0x0000001F)
+  #define DDRDATA4CH1_CR_RCOMPDATA0_Spare2_OFF                         (31)
+  #define DDRDATA4CH1_CR_RCOMPDATA0_Spare2_WID                         ( 1)
+  #define DDRDATA4CH1_CR_RCOMPDATA0_Spare2_MSK                         (0x80000000)
+  #define DDRDATA4CH1_CR_RCOMPDATA0_Spare2_MAX                         (0x00000001)
+
+#define DDRDATA4CH1_CR_RCOMPDATA1_REG                                (0x00000944)
+  #define DDRDATA4CH1_CR_RCOMPDATA1_RcompOdtUp_OFF                     ( 0)
+  #define DDRDATA4CH1_CR_RCOMPDATA1_RcompOdtUp_WID                     ( 6)
+  #define DDRDATA4CH1_CR_RCOMPDATA1_RcompOdtUp_MSK                     (0x0000003F)
+  #define DDRDATA4CH1_CR_RCOMPDATA1_RcompOdtUp_MAX                     (0x0000003F)
+  #define DDRDATA4CH1_CR_RCOMPDATA1_Spare0_OFF                         ( 6)
+  #define DDRDATA4CH1_CR_RCOMPDATA1_Spare0_WID                         ( 3)
+  #define DDRDATA4CH1_CR_RCOMPDATA1_Spare0_MSK                         (0x000001C0)
+  #define DDRDATA4CH1_CR_RCOMPDATA1_Spare0_MAX                         (0x00000007)
+  #define DDRDATA4CH1_CR_RCOMPDATA1_RcompOdtDown_OFF                   ( 9)
+  #define DDRDATA4CH1_CR_RCOMPDATA1_RcompOdtDown_WID                   ( 6)
+  #define DDRDATA4CH1_CR_RCOMPDATA1_RcompOdtDown_MSK                   (0x00007E00)
+  #define DDRDATA4CH1_CR_RCOMPDATA1_RcompOdtDown_MAX                   (0x0000003F)
+  #define DDRDATA4CH1_CR_RCOMPDATA1_Spare1_OFF                         (15)
+  #define DDRDATA4CH1_CR_RCOMPDATA1_Spare1_WID                         ( 1)
+  #define DDRDATA4CH1_CR_RCOMPDATA1_Spare1_MSK                         (0x00008000)
+  #define DDRDATA4CH1_CR_RCOMPDATA1_Spare1_MAX                         (0x00000001)
+  #define DDRDATA4CH1_CR_RCOMPDATA1_PanicDrvDn_OFF                     (16)
+  #define DDRDATA4CH1_CR_RCOMPDATA1_PanicDrvDn_WID                     ( 6)
+  #define DDRDATA4CH1_CR_RCOMPDATA1_PanicDrvDn_MSK                     (0x003F0000)
+  #define DDRDATA4CH1_CR_RCOMPDATA1_PanicDrvDn_MAX                     (0x0000003F)
+  #define DDRDATA4CH1_CR_RCOMPDATA1_PanicDrvUp_OFF                     (22)
+  #define DDRDATA4CH1_CR_RCOMPDATA1_PanicDrvUp_WID                     ( 6)
+  #define DDRDATA4CH1_CR_RCOMPDATA1_PanicDrvUp_MSK                     (0x0FC00000)
+  #define DDRDATA4CH1_CR_RCOMPDATA1_PanicDrvUp_MAX                     (0x0000003F)
+  #define DDRDATA4CH1_CR_RCOMPDATA1_LevelShifterComp_OFF               (28)
+  #define DDRDATA4CH1_CR_RCOMPDATA1_LevelShifterComp_WID               ( 3)
+  #define DDRDATA4CH1_CR_RCOMPDATA1_LevelShifterComp_MSK               (0x70000000)
+  #define DDRDATA4CH1_CR_RCOMPDATA1_LevelShifterComp_MAX               (0x00000007)
+  #define DDRDATA4CH1_CR_RCOMPDATA1_Spare2_OFF                         (31)
+  #define DDRDATA4CH1_CR_RCOMPDATA1_Spare2_WID                         ( 1)
+  #define DDRDATA4CH1_CR_RCOMPDATA1_Spare2_MSK                         (0x80000000)
+  #define DDRDATA4CH1_CR_RCOMPDATA1_Spare2_MAX                         (0x00000001)
+
+#define DDRDATA4CH1_CR_TXXTALK_REG                                   (0x00000948)
+  #define DDRDATA4CH1_CR_TXXTALK_Lane0_OFF                             ( 0)
+  #define DDRDATA4CH1_CR_TXXTALK_Lane0_WID                             ( 4)
+  #define DDRDATA4CH1_CR_TXXTALK_Lane0_MSK                             (0x0000000F)
+  #define DDRDATA4CH1_CR_TXXTALK_Lane0_MAX                             (0x0000000F)
+  #define DDRDATA4CH1_CR_TXXTALK_Lane1_OFF                             ( 4)
+  #define DDRDATA4CH1_CR_TXXTALK_Lane1_WID                             ( 4)
+  #define DDRDATA4CH1_CR_TXXTALK_Lane1_MSK                             (0x000000F0)
+  #define DDRDATA4CH1_CR_TXXTALK_Lane1_MAX                             (0x0000000F)
+  #define DDRDATA4CH1_CR_TXXTALK_Lane2_OFF                             ( 8)
+  #define DDRDATA4CH1_CR_TXXTALK_Lane2_WID                             ( 4)
+  #define DDRDATA4CH1_CR_TXXTALK_Lane2_MSK                             (0x00000F00)
+  #define DDRDATA4CH1_CR_TXXTALK_Lane2_MAX                             (0x0000000F)
+  #define DDRDATA4CH1_CR_TXXTALK_Lane3_OFF                             (12)
+  #define DDRDATA4CH1_CR_TXXTALK_Lane3_WID                             ( 4)
+  #define DDRDATA4CH1_CR_TXXTALK_Lane3_MSK                             (0x0000F000)
+  #define DDRDATA4CH1_CR_TXXTALK_Lane3_MAX                             (0x0000000F)
+  #define DDRDATA4CH1_CR_TXXTALK_Lane4_OFF                             (16)
+  #define DDRDATA4CH1_CR_TXXTALK_Lane4_WID                             ( 4)
+  #define DDRDATA4CH1_CR_TXXTALK_Lane4_MSK                             (0x000F0000)
+  #define DDRDATA4CH1_CR_TXXTALK_Lane4_MAX                             (0x0000000F)
+  #define DDRDATA4CH1_CR_TXXTALK_Lane5_OFF                             (20)
+  #define DDRDATA4CH1_CR_TXXTALK_Lane5_WID                             ( 4)
+  #define DDRDATA4CH1_CR_TXXTALK_Lane5_MSK                             (0x00F00000)
+  #define DDRDATA4CH1_CR_TXXTALK_Lane5_MAX                             (0x0000000F)
+  #define DDRDATA4CH1_CR_TXXTALK_Lane6_OFF                             (24)
+  #define DDRDATA4CH1_CR_TXXTALK_Lane6_WID                             ( 4)
+  #define DDRDATA4CH1_CR_TXXTALK_Lane6_MSK                             (0x0F000000)
+  #define DDRDATA4CH1_CR_TXXTALK_Lane6_MAX                             (0x0000000F)
+  #define DDRDATA4CH1_CR_TXXTALK_Lane7_OFF                             (28)
+  #define DDRDATA4CH1_CR_TXXTALK_Lane7_WID                             ( 4)
+  #define DDRDATA4CH1_CR_TXXTALK_Lane7_MSK                             (0xF0000000)
+  #define DDRDATA4CH1_CR_TXXTALK_Lane7_MAX                             (0x0000000F)
+
+#define DDRDATA4CH1_CR_RXOFFSETVDQ_REG                               (0x0000094C)
+  #define DDRDATA4CH1_CR_RXOFFSETVDQ_Lane0_OFF                         ( 0)
+  #define DDRDATA4CH1_CR_RXOFFSETVDQ_Lane0_WID                         ( 4)
+  #define DDRDATA4CH1_CR_RXOFFSETVDQ_Lane0_MSK                         (0x0000000F)
+  #define DDRDATA4CH1_CR_RXOFFSETVDQ_Lane0_MAX                         (0x0000000F)
+  #define DDRDATA4CH1_CR_RXOFFSETVDQ_Lane1_OFF                         ( 4)
+  #define DDRDATA4CH1_CR_RXOFFSETVDQ_Lane1_WID                         ( 4)
+  #define DDRDATA4CH1_CR_RXOFFSETVDQ_Lane1_MSK                         (0x000000F0)
+  #define DDRDATA4CH1_CR_RXOFFSETVDQ_Lane1_MAX                         (0x0000000F)
+  #define DDRDATA4CH1_CR_RXOFFSETVDQ_Lane2_OFF                         ( 8)
+  #define DDRDATA4CH1_CR_RXOFFSETVDQ_Lane2_WID                         ( 4)
+  #define DDRDATA4CH1_CR_RXOFFSETVDQ_Lane2_MSK                         (0x00000F00)
+  #define DDRDATA4CH1_CR_RXOFFSETVDQ_Lane2_MAX                         (0x0000000F)
+  #define DDRDATA4CH1_CR_RXOFFSETVDQ_Lane3_OFF                         (12)
+  #define DDRDATA4CH1_CR_RXOFFSETVDQ_Lane3_WID                         ( 4)
+  #define DDRDATA4CH1_CR_RXOFFSETVDQ_Lane3_MSK                         (0x0000F000)
+  #define DDRDATA4CH1_CR_RXOFFSETVDQ_Lane3_MAX                         (0x0000000F)
+  #define DDRDATA4CH1_CR_RXOFFSETVDQ_Lane4_OFF                         (16)
+  #define DDRDATA4CH1_CR_RXOFFSETVDQ_Lane4_WID                         ( 4)
+  #define DDRDATA4CH1_CR_RXOFFSETVDQ_Lane4_MSK                         (0x000F0000)
+  #define DDRDATA4CH1_CR_RXOFFSETVDQ_Lane4_MAX                         (0x0000000F)
+  #define DDRDATA4CH1_CR_RXOFFSETVDQ_Lane5_OFF                         (20)
+  #define DDRDATA4CH1_CR_RXOFFSETVDQ_Lane5_WID                         ( 4)
+  #define DDRDATA4CH1_CR_RXOFFSETVDQ_Lane5_MSK                         (0x00F00000)
+  #define DDRDATA4CH1_CR_RXOFFSETVDQ_Lane5_MAX                         (0x0000000F)
+  #define DDRDATA4CH1_CR_RXOFFSETVDQ_Lane6_OFF                         (24)
+  #define DDRDATA4CH1_CR_RXOFFSETVDQ_Lane6_WID                         ( 4)
+  #define DDRDATA4CH1_CR_RXOFFSETVDQ_Lane6_MSK                         (0x0F000000)
+  #define DDRDATA4CH1_CR_RXOFFSETVDQ_Lane6_MAX                         (0x0000000F)
+  #define DDRDATA4CH1_CR_RXOFFSETVDQ_Lane7_OFF                         (28)
+  #define DDRDATA4CH1_CR_RXOFFSETVDQ_Lane7_WID                         ( 4)
+  #define DDRDATA4CH1_CR_RXOFFSETVDQ_Lane7_MSK                         (0xF0000000)
+  #define DDRDATA4CH1_CR_RXOFFSETVDQ_Lane7_MAX                         (0x0000000F)
+
+#define DDRDATA4CH1_CR_DDRDATARESERVED_REG                           (0x00000950)
+  #define DDRDATA4CH1_CR_DDRDATARESERVED_Spare_OFF                     ( 0)
+  #define DDRDATA4CH1_CR_DDRDATARESERVED_Spare_WID                     (32)
+  #define DDRDATA4CH1_CR_DDRDATARESERVED_Spare_MSK                     (0xFFFFFFFF)
+  #define DDRDATA4CH1_CR_DDRDATARESERVED_Spare_MAX                     (0xFFFFFFFF)
+
+#define DDRDATA4CH1_CR_DATATRAINFEEDBACK_REG                         (0x00000954)
+  #define DDRDATA4CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_OFF       ( 0)
+  #define DDRDATA4CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_WID       ( 9)
+  #define DDRDATA4CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_MSK       (0x000001FF)
+  #define DDRDATA4CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_MAX       (0x000001FF)
+  #define DDRDATA4CH1_CR_DATATRAINFEEDBACK_Spare_OFF                   ( 9)
+  #define DDRDATA4CH1_CR_DATATRAINFEEDBACK_Spare_WID                   (23)
+  #define DDRDATA4CH1_CR_DATATRAINFEEDBACK_Spare_MSK                   (0xFFFFFE00)
+  #define DDRDATA4CH1_CR_DATATRAINFEEDBACK_Spare_MAX                   (0x007FFFFF)
+
+#define DDRDATA4CH1_CR_DLLPITESTANDADC_REG                           (0x00000958)
+  #define DDRDATA4CH1_CR_DLLPITESTANDADC_RunTest_OFF                   ( 0)
+  #define DDRDATA4CH1_CR_DLLPITESTANDADC_RunTest_WID                   ( 1)
+  #define DDRDATA4CH1_CR_DLLPITESTANDADC_RunTest_MSK                   (0x00000001)
+  #define DDRDATA4CH1_CR_DLLPITESTANDADC_RunTest_MAX                   (0x00000001)
+  #define DDRDATA4CH1_CR_DLLPITESTANDADC_RunTest_DEF                   (0x00000000)
+  #define DDRDATA4CH1_CR_DLLPITESTANDADC_Load_OFF                      ( 1)
+  #define DDRDATA4CH1_CR_DLLPITESTANDADC_Load_WID                      ( 1)
+  #define DDRDATA4CH1_CR_DLLPITESTANDADC_Load_MSK                      (0x00000002)
+  #define DDRDATA4CH1_CR_DLLPITESTANDADC_Load_MAX                      (0x00000001)
+  #define DDRDATA4CH1_CR_DLLPITESTANDADC_Load_DEF                      (0x00000000)
+  #define DDRDATA4CH1_CR_DLLPITESTANDADC_ModeHVM_OFF                   ( 2)
+  #define DDRDATA4CH1_CR_DLLPITESTANDADC_ModeHVM_WID                   ( 1)
+  #define DDRDATA4CH1_CR_DLLPITESTANDADC_ModeHVM_MSK                   (0x00000004)
+  #define DDRDATA4CH1_CR_DLLPITESTANDADC_ModeHVM_MAX                   (0x00000001)
+  #define DDRDATA4CH1_CR_DLLPITESTANDADC_ModeHVM_DEF                   (0x00000000)
+  #define DDRDATA4CH1_CR_DLLPITESTANDADC_ModeDV_OFF                    ( 3)
+  #define DDRDATA4CH1_CR_DLLPITESTANDADC_ModeDV_WID                    ( 1)
+  #define DDRDATA4CH1_CR_DLLPITESTANDADC_ModeDV_MSK                    (0x00000008)
+  #define DDRDATA4CH1_CR_DLLPITESTANDADC_ModeDV_MAX                    (0x00000001)
+  #define DDRDATA4CH1_CR_DLLPITESTANDADC_ModeDV_DEF                    (0x00000000)
+  #define DDRDATA4CH1_CR_DLLPITESTANDADC_ModeADC_OFF                   ( 4)
+  #define DDRDATA4CH1_CR_DLLPITESTANDADC_ModeADC_WID                   ( 1)
+  #define DDRDATA4CH1_CR_DLLPITESTANDADC_ModeADC_MSK                   (0x00000010)
+  #define DDRDATA4CH1_CR_DLLPITESTANDADC_ModeADC_MAX                   (0x00000001)
+  #define DDRDATA4CH1_CR_DLLPITESTANDADC_ModeADC_DEF                   (0x00000000)
+  #define DDRDATA4CH1_CR_DLLPITESTANDADC_LoadCount_OFF                 ( 5)
+  #define DDRDATA4CH1_CR_DLLPITESTANDADC_LoadCount_WID                 (10)
+  #define DDRDATA4CH1_CR_DLLPITESTANDADC_LoadCount_MSK                 (0x00007FE0)
+  #define DDRDATA4CH1_CR_DLLPITESTANDADC_LoadCount_MAX                 (0x000003FF)
+  #define DDRDATA4CH1_CR_DLLPITESTANDADC_CountStatus_OFF               (15)
+  #define DDRDATA4CH1_CR_DLLPITESTANDADC_CountStatus_WID               (10)
+  #define DDRDATA4CH1_CR_DLLPITESTANDADC_CountStatus_MSK               (0x01FF8000)
+  #define DDRDATA4CH1_CR_DLLPITESTANDADC_CountStatus_MAX               (0x000003FF)
+  #define DDRDATA4CH1_CR_DLLPITESTANDADC_CountStatus_DEF               (0x00000000)
+  #define DDRDATA4CH1_CR_DLLPITESTANDADC_Spare_OFF                     (25)
+  #define DDRDATA4CH1_CR_DLLPITESTANDADC_Spare_WID                     ( 7)
+  #define DDRDATA4CH1_CR_DLLPITESTANDADC_Spare_MSK                     (0xFE000000)
+  #define DDRDATA4CH1_CR_DLLPITESTANDADC_Spare_MAX                     (0x0000007F)
+
+#define DDRDATA4CH1_CR_DDRCRDATAOFFSETCOMP_REG                       (0x0000095C)
+  #define DDRDATA4CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_OFF     ( 0)
+  #define DDRDATA4CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_WID     ( 6)
+  #define DDRDATA4CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MSK     (0x0000003F)
+  #define DDRDATA4CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MAX     (0x0000003F)
+  #define DDRDATA4CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_DEF     (0x00000000)
+  #define DDRDATA4CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_OFF   ( 6)
+  #define DDRDATA4CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_WID   ( 6)
+  #define DDRDATA4CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MSK   (0x00000FC0)
+  #define DDRDATA4CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MAX   (0x0000003F)
+  #define DDRDATA4CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_DEF   (0x00000000)
+  #define DDRDATA4CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_OFF     (12)
+  #define DDRDATA4CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_WID     ( 5)
+  #define DDRDATA4CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MSK     (0x0001F000)
+  #define DDRDATA4CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MAX     (0x0000001F)
+  #define DDRDATA4CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_DEF     (0x00000000)
+  #define DDRDATA4CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_OFF   (17)
+  #define DDRDATA4CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_WID   ( 5)
+  #define DDRDATA4CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MSK   (0x003E0000)
+  #define DDRDATA4CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MAX   (0x0000001F)
+  #define DDRDATA4CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_DEF   (0x00000000)
+  #define DDRDATA4CH1_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_OFF       (22)
+  #define DDRDATA4CH1_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_WID       ( 5)
+  #define DDRDATA4CH1_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_MSK       (0x07C00000)
+  #define DDRDATA4CH1_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_MAX       (0x0000001F)
+  #define DDRDATA4CH1_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_DEF       (0x00000000)
+  #define DDRDATA4CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_OFF  (27)
+  #define DDRDATA4CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_WID  ( 5)
+  #define DDRDATA4CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MSK  (0xF8000000)
+  #define DDRDATA4CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MAX  (0x0000001F)
+  #define DDRDATA4CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_DEF  (0x00000000)
+
+#define DDRDATA4CH1_CR_DDRCRDATACONTROL1_REG                         (0x00000960)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_RefPi_OFF                   ( 0)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_RefPi_WID                   ( 4)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_RefPi_MSK                   (0x0000000F)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_RefPi_MAX                   (0x0000000F)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_RefPi_DEF                   (0x00000000)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_DllMask_OFF                 ( 4)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_DllMask_WID                 ( 2)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_DllMask_MSK                 (0x00000030)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_DllMask_MAX                 (0x00000003)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_DllMask_DEF                 (0x00000000)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_DllWeakLock_OFF             ( 6)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_DllWeakLock_WID             ( 1)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_DllWeakLock_MSK             (0x00000040)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_DllWeakLock_MAX             (0x00000001)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_DllWeakLock_DEF             (0x00000000)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_OFF      ( 7)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_WID      ( 3)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MSK      (0x00000380)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MAX      (0x00000007)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_DEF      (0x00000000)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_OFF               (10)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_WID               ( 3)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_MSK               (0x00001C00)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_MAX               (0x00000007)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_DEF               (0x00000000)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_OdtDelay_OFF                (13)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_OdtDelay_WID                ( 4)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_OdtDelay_MSK                (0x0001E000)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_OdtDelay_MAX                (0x0000000F)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_OdtDelay_DEF                (0x00000000)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_OdtDuration_OFF             (17)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_OdtDuration_WID             ( 3)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_OdtDuration_MSK             (0x000E0000)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_OdtDuration_MAX             (0x00000007)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_OdtDuration_DEF             (0x00000000)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_OFF           (20)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_WID           ( 4)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_MSK           (0x00F00000)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_MAX           (0x0000000F)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_DEF           (0x00000000)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_OFF        (24)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_WID        ( 3)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_MSK        (0x07000000)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_MAX        (0x00000007)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_DEF        (0x00000000)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_BurstEndODTDelay_OFF        (27)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_BurstEndODTDelay_WID        ( 3)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_BurstEndODTDelay_MSK        (0x38000000)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_BurstEndODTDelay_MAX        (0x00000007)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_BurstEndODTDelay_DEF        (0x00000000)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_OFF          (30)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_WID          ( 1)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_MSK          (0x40000000)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_MAX          (0x00000001)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_DEF          (0x00000000)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_Rsvd1_OFF                   (31)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_Rsvd1_WID                   ( 1)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_Rsvd1_MSK                   (0x80000000)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_Rsvd1_MAX                   (0x00000001)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_Rsvd1_DEF                   (0x00000000)
+
+#define DDRDATA4CH1_CR_DDRCRDATACONTROL2_REG                         (0x00000964)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_OFF            ( 0)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_WID            ( 5)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_MSK            (0x0000001F)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_MAX            (0x0000001F)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_DEF            (0x00000000)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_OFF             ( 5)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_WID             ( 1)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_MSK             (0x00000020)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_MAX             (0x00000001)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_DEF             (0x00000000)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_ForceRxOn_OFF               ( 6)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_ForceRxOn_WID               ( 1)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_ForceRxOn_MSK               (0x00000040)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_ForceRxOn_MAX               (0x00000001)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_ForceRxOn_DEF               (0x00000000)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_LeakerComp_OFF              ( 7)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_LeakerComp_WID              ( 2)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_LeakerComp_MSK              (0x00000180)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_LeakerComp_MAX              (0x00000003)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_LeakerComp_DEF              (0x00000000)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_OFF          ( 9)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_WID          ( 4)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_MSK          (0x00001E00)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_MAX          (0x0000000F)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_DEF          (0x00000008)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_OFF             (13)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_WID             ( 5)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_MSK             (0x0003E000)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_MAX             (0x0000001F)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_DEF             (0x00000011)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_OFF             (18)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_WID             ( 1)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_MSK             (0x00040000)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_MAX             (0x00000001)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_DEF             (0x00000000)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_Spare_OFF                   (19)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_Spare_WID                   (13)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_Spare_MSK                   (0xFFF80000)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_Spare_MAX                   (0x00001FFF)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_Spare_DEF                   (0x00000000)
+
+#define DDRDATA4CH1_CR_DDRCRVSSHIORVREFCONTROL_REG                   (0x0000096C)
+  #define DDRDATA4CH1_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_OFF    ( 0)
+  #define DDRDATA4CH1_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_WID    (24)
+  #define DDRDATA4CH1_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_MSK    (0x00FFFFFF)
+  #define DDRDATA4CH1_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_MAX    (0x00FFFFFF)
+  #define DDRDATA4CH1_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_DEF    (0x00000000)
+  #define DDRDATA4CH1_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_OFF        (24)
+  #define DDRDATA4CH1_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_WID        ( 8)
+  #define DDRDATA4CH1_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_MSK        (0xFF000000)
+  #define DDRDATA4CH1_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_MAX        (0x000000FF)
+  #define DDRDATA4CH1_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_DEF        (0x00000000)
+
+#define DDRDATA4CH1_CR_DDRCRDATAOFFSETTRAIN_REG                      (0x00000970)
+  #define DDRDATA4CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_OFF          ( 0)
+  #define DDRDATA4CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_WID          ( 6)
+  #define DDRDATA4CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MSK          (0x0000003F)
+  #define DDRDATA4CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MAX          (0x0000003F)
+  #define DDRDATA4CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_DEF          (0x00000000)
+  #define DDRDATA4CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_OFF          ( 6)
+  #define DDRDATA4CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_WID          ( 6)
+  #define DDRDATA4CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MSK          (0x00000FC0)
+  #define DDRDATA4CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MAX          (0x0000003F)
+  #define DDRDATA4CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_DEF          (0x00000000)
+  #define DDRDATA4CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_OFF           (12)
+  #define DDRDATA4CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_WID           ( 6)
+  #define DDRDATA4CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MSK           (0x0003F000)
+  #define DDRDATA4CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MAX           (0x0000003F)
+  #define DDRDATA4CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_DEF           (0x00000000)
+  #define DDRDATA4CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_OFF          (18)
+  #define DDRDATA4CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_WID          ( 6)
+  #define DDRDATA4CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MSK          (0x00FC0000)
+  #define DDRDATA4CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MAX          (0x0000003F)
+  #define DDRDATA4CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_DEF          (0x00000000)
+  #define DDRDATA4CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_OFF           (24)
+  #define DDRDATA4CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_WID           ( 7)
+  #define DDRDATA4CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MSK           (0x7F000000)
+  #define DDRDATA4CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MAX           (0x0000007F)
+  #define DDRDATA4CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_DEF           (0x00000000)
+  #define DDRDATA4CH1_CR_DDRCRDATAOFFSETTRAIN_Spare_OFF                (31)
+  #define DDRDATA4CH1_CR_DDRCRDATAOFFSETTRAIN_Spare_WID                ( 1)
+  #define DDRDATA4CH1_CR_DDRCRDATAOFFSETTRAIN_Spare_MSK                (0x80000000)
+  #define DDRDATA4CH1_CR_DDRCRDATAOFFSETTRAIN_Spare_MAX                (0x00000001)
+  #define DDRDATA4CH1_CR_DDRCRDATAOFFSETTRAIN_Spare_DEF                (0x00000000)
+
+#define DDRDATA4CH1_CR_DDRCRDATACONTROL0_REG                         (0x00000974)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_OFF          ( 0)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_WID          ( 1)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_MSK          (0x00000001)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_MAX          (0x00000001)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_DEF          (0x00000000)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_OFF          ( 1)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_WID          ( 1)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_MSK          (0x00000002)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_MAX          (0x00000001)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_DEF          (0x00000000)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_OFF          ( 2)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_WID          ( 1)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_MSK          (0x00000004)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_MAX          (0x00000001)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_DEF          (0x00000000)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_OFF    ( 3)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_WID    ( 1)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MSK    (0x00000008)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MAX    (0x00000001)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_DEF    (0x00000000)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_TxOn_OFF                    ( 4)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_TxOn_WID                    ( 1)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_TxOn_MSK                    (0x00000010)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_TxOn_MAX                    (0x00000001)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_TxOn_DEF                    (0x00000000)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RfOn_OFF                    ( 5)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RfOn_WID                    ( 1)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RfOn_MSK                    (0x00000020)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RfOn_MAX                    (0x00000001)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RfOn_DEF                    (0x00000000)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RxPiOn_OFF                  ( 6)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RxPiOn_WID                  ( 1)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RxPiOn_MSK                  (0x00000040)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RxPiOn_MAX                  (0x00000001)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RxPiOn_DEF                  (0x00000000)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_TxPiOn_OFF                  ( 7)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_TxPiOn_WID                  ( 1)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_TxPiOn_MSK                  (0x00000080)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_TxPiOn_MAX                  (0x00000001)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_TxPiOn_DEF                  (0x00000000)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_OFF        ( 8)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_WID        ( 1)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_MSK        (0x00000100)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_MAX        (0x00000001)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_DEF        (0x00000000)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_OFF        ( 9)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_WID        ( 1)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MSK        (0x00000200)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MAX        (0x00000001)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_DEF        (0x00000000)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_TxDisable_OFF               (10)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_TxDisable_WID               ( 1)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_TxDisable_MSK               (0x00000400)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_TxDisable_MAX               (0x00000001)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_TxDisable_DEF               (0x00000000)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RxDisable_OFF               (11)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RxDisable_WID               ( 1)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RxDisable_MSK               (0x00000800)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RxDisable_MAX               (0x00000001)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RxDisable_DEF               (0x00000000)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_TxLong_OFF                  (12)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_TxLong_WID                  ( 1)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_TxLong_MSK                  (0x00001000)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_TxLong_MAX                  (0x00000001)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_TxLong_DEF                  (0x00000000)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_OFF               (13)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_WID               ( 2)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_MSK               (0x00006000)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_MAX               (0x00000003)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_DEF               (0x00000000)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RxReadPointer_OFF           (15)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RxReadPointer_WID           ( 3)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RxReadPointer_MSK           (0x00038000)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RxReadPointer_MAX           (0x00000007)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RxReadPointer_DEF           (0x00000000)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_DriverSegmentEnable_OFF     (18)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_DriverSegmentEnable_WID     ( 1)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_DriverSegmentEnable_MSK     (0x00040000)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_DriverSegmentEnable_MAX     (0x00000001)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_DriverSegmentEnable_DEF     (0x00000000)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_DataVccddqHi_OFF            (19)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_DataVccddqHi_WID            ( 1)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_DataVccddqHi_MSK            (0x00080000)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_DataVccddqHi_MAX            (0x00000001)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_DataVccddqHi_DEF            (0x00000000)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_ReadRFRd_OFF                (20)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_ReadRFRd_WID                ( 1)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_ReadRFRd_MSK                (0x00100000)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_ReadRFRd_MAX                (0x00000001)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_ReadRFRd_DEF                (0x00000000)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_ReadRFWr_OFF                (21)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_ReadRFWr_WID                ( 1)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_ReadRFWr_MSK                (0x00200000)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_ReadRFWr_MAX                (0x00000001)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_ReadRFWr_DEF                (0x00000000)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_ReadRFRank_OFF              (22)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_ReadRFRank_WID              ( 2)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_ReadRFRank_MSK              (0x00C00000)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_ReadRFRank_MAX              (0x00000003)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_ReadRFRank_DEF              (0x00000000)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_OFF              (24)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_WID              ( 1)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_MSK              (0x01000000)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_MAX              (0x00000001)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_DEF              (0x00000000)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_OdtSampOff_OFF              (25)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_OdtSampOff_WID              ( 1)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_OdtSampOff_MSK              (0x02000000)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_OdtSampOff_MAX              (0x00000001)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_OdtSampOff_DEF              (0x00000000)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_OFF        (26)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_WID        ( 1)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_MSK        (0x04000000)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_MAX        (0x00000001)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_DEF        (0x00000000)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_OFF         (27)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_WID         ( 1)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MSK         (0x08000000)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MAX         (0x00000001)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_DEF         (0x00000000)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_OFF              (28)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_WID              ( 1)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_MSK              (0x10000000)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_MAX              (0x00000001)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_DEF              (0x00000000)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_EnReadPreamble_OFF          (29)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_EnReadPreamble_WID          ( 1)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_EnReadPreamble_MSK          (0x20000000)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_EnReadPreamble_MAX          (0x00000001)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_EnReadPreamble_DEF          (0x00000000)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_OFF         (30)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_WID         ( 1)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MSK         (0x40000000)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MAX         (0x00000001)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_DEF         (0x00000000)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_OFF            (31)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_WID            ( 1)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_MSK            (0x80000000)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_MAX            (0x00000001)
+  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_DEF            (0x00000000)
+
+#define DDRDATA4CH1_CR_DDRCRVREFADJUST1_REG                          (0x00000978)
+  #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_CAVrefCtl_OFF                ( 0)
+  #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_CAVrefCtl_WID                ( 7)
+  #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_CAVrefCtl_MSK                (0x0000007F)
+  #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_CAVrefCtl_MAX                (0x0000007F)
+  #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_CAVrefCtl_DEF                (0x00000000)
+  #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_Ch1VrefCtl_OFF               ( 7)
+  #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_Ch1VrefCtl_WID               ( 7)
+  #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_Ch1VrefCtl_MSK               (0x00003F80)
+  #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_Ch1VrefCtl_MAX               (0x0000007F)
+  #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_Ch1VrefCtl_DEF               (0x00000000)
+  #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_Ch0VrefCtl_OFF               (14)
+  #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_Ch0VrefCtl_WID               ( 7)
+  #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_Ch0VrefCtl_MSK               (0x001FC000)
+  #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_Ch0VrefCtl_MAX               (0x0000007F)
+  #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_Ch0VrefCtl_DEF               (0x00000000)
+  #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCA_OFF             (21)
+  #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCA_WID             ( 1)
+  #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCA_MSK             (0x00200000)
+  #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCA_MAX             (0x00000001)
+  #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCA_DEF             (0x00000000)
+  #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_OFF            (22)
+  #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_WID            ( 1)
+  #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_MSK            (0x00400000)
+  #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_MAX            (0x00000001)
+  #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_DEF            (0x00000000)
+  #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_OFF            (23)
+  #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_WID            ( 1)
+  #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_MSK            (0x00800000)
+  #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_MAX            (0x00000001)
+  #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_DEF            (0x00000000)
+  #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_HiZTimerCtrl_OFF             (24)
+  #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_HiZTimerCtrl_WID             ( 2)
+  #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_HiZTimerCtrl_MSK             (0x03000000)
+  #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_HiZTimerCtrl_MAX             (0x00000003)
+  #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_HiZTimerCtrl_DEF             (0x00000000)
+  #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_OFF            (26)
+  #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_WID            ( 1)
+  #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_MSK            (0x04000000)
+  #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_MAX            (0x00000001)
+  #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_DEF            (0x00000000)
+  #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_Rsvd_OFF                     (27)
+  #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_Rsvd_WID                     ( 2)
+  #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_Rsvd_MSK                     (0x18000000)
+  #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_Rsvd_MAX                     (0x00000003)
+  #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_Rsvd_DEF                     (0x00000000)
+  #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_caSlowBW_OFF                 (29)
+  #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_caSlowBW_WID                 ( 1)
+  #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_caSlowBW_MSK                 (0x20000000)
+  #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_caSlowBW_MAX                 (0x00000001)
+  #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_caSlowBW_DEF                 (0x00000000)
+  #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_ch0SlowBW_OFF                (30)
+  #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_ch0SlowBW_WID                ( 1)
+  #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_ch0SlowBW_MSK                (0x40000000)
+  #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_ch0SlowBW_MAX                (0x00000001)
+  #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_ch0SlowBW_DEF                (0x00000000)
+  #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_ch1SlowBW_OFF                (31)
+  #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_ch1SlowBW_WID                ( 1)
+  #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_ch1SlowBW_MSK                (0x80000000)
+  #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_ch1SlowBW_MAX                (0x00000001)
+  #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_ch1SlowBW_DEF                (0x00000000)
+
+#define DDRDATA5CH0_CR_RXTRAINRANK0_REG                              (0x00000A00)
+  #define DDRDATA5CH0_CR_RXTRAINRANK0_RxRcvEnPi_OFF                    ( 0)
+  #define DDRDATA5CH0_CR_RXTRAINRANK0_RxRcvEnPi_WID                    ( 9)
+  #define DDRDATA5CH0_CR_RXTRAINRANK0_RxRcvEnPi_MSK                    (0x000001FF)
+  #define DDRDATA5CH0_CR_RXTRAINRANK0_RxRcvEnPi_MAX                    (0x000001FF)
+  #define DDRDATA5CH0_CR_RXTRAINRANK0_RxDqsPPi_OFF                     ( 9)
+  #define DDRDATA5CH0_CR_RXTRAINRANK0_RxDqsPPi_WID                     ( 6)
+  #define DDRDATA5CH0_CR_RXTRAINRANK0_RxDqsPPi_MSK                     (0x00007E00)
+  #define DDRDATA5CH0_CR_RXTRAINRANK0_RxDqsPPi_MAX                     (0x0000003F)
+  #define DDRDATA5CH0_CR_RXTRAINRANK0_RxEq_OFF                         (15)
+  #define DDRDATA5CH0_CR_RXTRAINRANK0_RxEq_WID                         ( 5)
+  #define DDRDATA5CH0_CR_RXTRAINRANK0_RxEq_MSK                         (0x000F8000)
+  #define DDRDATA5CH0_CR_RXTRAINRANK0_RxEq_MAX                         (0x0000001F)
+  #define DDRDATA5CH0_CR_RXTRAINRANK0_RxDqsNPi_OFF                     (20)
+  #define DDRDATA5CH0_CR_RXTRAINRANK0_RxDqsNPi_WID                     ( 6)
+  #define DDRDATA5CH0_CR_RXTRAINRANK0_RxDqsNPi_MSK                     (0x03F00000)
+  #define DDRDATA5CH0_CR_RXTRAINRANK0_RxDqsNPi_MAX                     (0x0000003F)
+  #define DDRDATA5CH0_CR_RXTRAINRANK0_RxVref_OFF                       (26)
+  #define DDRDATA5CH0_CR_RXTRAINRANK0_RxVref_WID                       ( 6)
+  #define DDRDATA5CH0_CR_RXTRAINRANK0_RxVref_MSK                       (0xFC000000)
+  #define DDRDATA5CH0_CR_RXTRAINRANK0_RxVref_MAX                       (0x0000003F)
+
+#define DDRDATA5CH0_CR_RXTRAINRANK1_REG                              (0x00000A04)
+  #define DDRDATA5CH0_CR_RXTRAINRANK1_RxRcvEnPi_OFF                    ( 0)
+  #define DDRDATA5CH0_CR_RXTRAINRANK1_RxRcvEnPi_WID                    ( 9)
+  #define DDRDATA5CH0_CR_RXTRAINRANK1_RxRcvEnPi_MSK                    (0x000001FF)
+  #define DDRDATA5CH0_CR_RXTRAINRANK1_RxRcvEnPi_MAX                    (0x000001FF)
+  #define DDRDATA5CH0_CR_RXTRAINRANK1_RxDqsPPi_OFF                     ( 9)
+  #define DDRDATA5CH0_CR_RXTRAINRANK1_RxDqsPPi_WID                     ( 6)
+  #define DDRDATA5CH0_CR_RXTRAINRANK1_RxDqsPPi_MSK                     (0x00007E00)
+  #define DDRDATA5CH0_CR_RXTRAINRANK1_RxDqsPPi_MAX                     (0x0000003F)
+  #define DDRDATA5CH0_CR_RXTRAINRANK1_RxEq_OFF                         (15)
+  #define DDRDATA5CH0_CR_RXTRAINRANK1_RxEq_WID                         ( 5)
+  #define DDRDATA5CH0_CR_RXTRAINRANK1_RxEq_MSK                         (0x000F8000)
+  #define DDRDATA5CH0_CR_RXTRAINRANK1_RxEq_MAX                         (0x0000001F)
+  #define DDRDATA5CH0_CR_RXTRAINRANK1_RxDqsNPi_OFF                     (20)
+  #define DDRDATA5CH0_CR_RXTRAINRANK1_RxDqsNPi_WID                     ( 6)
+  #define DDRDATA5CH0_CR_RXTRAINRANK1_RxDqsNPi_MSK                     (0x03F00000)
+  #define DDRDATA5CH0_CR_RXTRAINRANK1_RxDqsNPi_MAX                     (0x0000003F)
+  #define DDRDATA5CH0_CR_RXTRAINRANK1_RxVref_OFF                       (26)
+  #define DDRDATA5CH0_CR_RXTRAINRANK1_RxVref_WID                       ( 6)
+  #define DDRDATA5CH0_CR_RXTRAINRANK1_RxVref_MSK                       (0xFC000000)
+  #define DDRDATA5CH0_CR_RXTRAINRANK1_RxVref_MAX                       (0x0000003F)
+
+#define DDRDATA5CH0_CR_RXTRAINRANK2_REG                              (0x00000A08)
+  #define DDRDATA5CH0_CR_RXTRAINRANK2_RxRcvEnPi_OFF                    ( 0)
+  #define DDRDATA5CH0_CR_RXTRAINRANK2_RxRcvEnPi_WID                    ( 9)
+  #define DDRDATA5CH0_CR_RXTRAINRANK2_RxRcvEnPi_MSK                    (0x000001FF)
+  #define DDRDATA5CH0_CR_RXTRAINRANK2_RxRcvEnPi_MAX                    (0x000001FF)
+  #define DDRDATA5CH0_CR_RXTRAINRANK2_RxDqsPPi_OFF                     ( 9)
+  #define DDRDATA5CH0_CR_RXTRAINRANK2_RxDqsPPi_WID                     ( 6)
+  #define DDRDATA5CH0_CR_RXTRAINRANK2_RxDqsPPi_MSK                     (0x00007E00)
+  #define DDRDATA5CH0_CR_RXTRAINRANK2_RxDqsPPi_MAX                     (0x0000003F)
+  #define DDRDATA5CH0_CR_RXTRAINRANK2_RxEq_OFF                         (15)
+  #define DDRDATA5CH0_CR_RXTRAINRANK2_RxEq_WID                         ( 5)
+  #define DDRDATA5CH0_CR_RXTRAINRANK2_RxEq_MSK                         (0x000F8000)
+  #define DDRDATA5CH0_CR_RXTRAINRANK2_RxEq_MAX                         (0x0000001F)
+  #define DDRDATA5CH0_CR_RXTRAINRANK2_RxDqsNPi_OFF                     (20)
+  #define DDRDATA5CH0_CR_RXTRAINRANK2_RxDqsNPi_WID                     ( 6)
+  #define DDRDATA5CH0_CR_RXTRAINRANK2_RxDqsNPi_MSK                     (0x03F00000)
+  #define DDRDATA5CH0_CR_RXTRAINRANK2_RxDqsNPi_MAX                     (0x0000003F)
+  #define DDRDATA5CH0_CR_RXTRAINRANK2_RxVref_OFF                       (26)
+  #define DDRDATA5CH0_CR_RXTRAINRANK2_RxVref_WID                       ( 6)
+  #define DDRDATA5CH0_CR_RXTRAINRANK2_RxVref_MSK                       (0xFC000000)
+  #define DDRDATA5CH0_CR_RXTRAINRANK2_RxVref_MAX                       (0x0000003F)
+
+#define DDRDATA5CH0_CR_RXTRAINRANK3_REG                              (0x00000A0C)
+  #define DDRDATA5CH0_CR_RXTRAINRANK3_RxRcvEnPi_OFF                    ( 0)
+  #define DDRDATA5CH0_CR_RXTRAINRANK3_RxRcvEnPi_WID                    ( 9)
+  #define DDRDATA5CH0_CR_RXTRAINRANK3_RxRcvEnPi_MSK                    (0x000001FF)
+  #define DDRDATA5CH0_CR_RXTRAINRANK3_RxRcvEnPi_MAX                    (0x000001FF)
+  #define DDRDATA5CH0_CR_RXTRAINRANK3_RxDqsPPi_OFF                     ( 9)
+  #define DDRDATA5CH0_CR_RXTRAINRANK3_RxDqsPPi_WID                     ( 6)
+  #define DDRDATA5CH0_CR_RXTRAINRANK3_RxDqsPPi_MSK                     (0x00007E00)
+  #define DDRDATA5CH0_CR_RXTRAINRANK3_RxDqsPPi_MAX                     (0x0000003F)
+  #define DDRDATA5CH0_CR_RXTRAINRANK3_RxEq_OFF                         (15)
+  #define DDRDATA5CH0_CR_RXTRAINRANK3_RxEq_WID                         ( 5)
+  #define DDRDATA5CH0_CR_RXTRAINRANK3_RxEq_MSK                         (0x000F8000)
+  #define DDRDATA5CH0_CR_RXTRAINRANK3_RxEq_MAX                         (0x0000001F)
+  #define DDRDATA5CH0_CR_RXTRAINRANK3_RxDqsNPi_OFF                     (20)
+  #define DDRDATA5CH0_CR_RXTRAINRANK3_RxDqsNPi_WID                     ( 6)
+  #define DDRDATA5CH0_CR_RXTRAINRANK3_RxDqsNPi_MSK                     (0x03F00000)
+  #define DDRDATA5CH0_CR_RXTRAINRANK3_RxDqsNPi_MAX                     (0x0000003F)
+  #define DDRDATA5CH0_CR_RXTRAINRANK3_RxVref_OFF                       (26)
+  #define DDRDATA5CH0_CR_RXTRAINRANK3_RxVref_WID                       ( 6)
+  #define DDRDATA5CH0_CR_RXTRAINRANK3_RxVref_MSK                       (0xFC000000)
+  #define DDRDATA5CH0_CR_RXTRAINRANK3_RxVref_MAX                       (0x0000003F)
+
+#define DDRDATA5CH0_CR_RXPERBITRANK0_REG                             (0x00000A10)
+  #define DDRDATA5CH0_CR_RXPERBITRANK0_Lane0_OFF                       ( 0)
+  #define DDRDATA5CH0_CR_RXPERBITRANK0_Lane0_WID                       ( 4)
+  #define DDRDATA5CH0_CR_RXPERBITRANK0_Lane0_MSK                       (0x0000000F)
+  #define DDRDATA5CH0_CR_RXPERBITRANK0_Lane0_MAX                       (0x0000000F)
+  #define DDRDATA5CH0_CR_RXPERBITRANK0_Lane1_OFF                       ( 4)
+  #define DDRDATA5CH0_CR_RXPERBITRANK0_Lane1_WID                       ( 4)
+  #define DDRDATA5CH0_CR_RXPERBITRANK0_Lane1_MSK                       (0x000000F0)
+  #define DDRDATA5CH0_CR_RXPERBITRANK0_Lane1_MAX                       (0x0000000F)
+  #define DDRDATA5CH0_CR_RXPERBITRANK0_Lane2_OFF                       ( 8)
+  #define DDRDATA5CH0_CR_RXPERBITRANK0_Lane2_WID                       ( 4)
+  #define DDRDATA5CH0_CR_RXPERBITRANK0_Lane2_MSK                       (0x00000F00)
+  #define DDRDATA5CH0_CR_RXPERBITRANK0_Lane2_MAX                       (0x0000000F)
+  #define DDRDATA5CH0_CR_RXPERBITRANK0_Lane3_OFF                       (12)
+  #define DDRDATA5CH0_CR_RXPERBITRANK0_Lane3_WID                       ( 4)
+  #define DDRDATA5CH0_CR_RXPERBITRANK0_Lane3_MSK                       (0x0000F000)
+  #define DDRDATA5CH0_CR_RXPERBITRANK0_Lane3_MAX                       (0x0000000F)
+  #define DDRDATA5CH0_CR_RXPERBITRANK0_Lane4_OFF                       (16)
+  #define DDRDATA5CH0_CR_RXPERBITRANK0_Lane4_WID                       ( 4)
+  #define DDRDATA5CH0_CR_RXPERBITRANK0_Lane4_MSK                       (0x000F0000)
+  #define DDRDATA5CH0_CR_RXPERBITRANK0_Lane4_MAX                       (0x0000000F)
+  #define DDRDATA5CH0_CR_RXPERBITRANK0_Lane5_OFF                       (20)
+  #define DDRDATA5CH0_CR_RXPERBITRANK0_Lane5_WID                       ( 4)
+  #define DDRDATA5CH0_CR_RXPERBITRANK0_Lane5_MSK                       (0x00F00000)
+  #define DDRDATA5CH0_CR_RXPERBITRANK0_Lane5_MAX                       (0x0000000F)
+  #define DDRDATA5CH0_CR_RXPERBITRANK0_Lane6_OFF                       (24)
+  #define DDRDATA5CH0_CR_RXPERBITRANK0_Lane6_WID                       ( 4)
+  #define DDRDATA5CH0_CR_RXPERBITRANK0_Lane6_MSK                       (0x0F000000)
+  #define DDRDATA5CH0_CR_RXPERBITRANK0_Lane6_MAX                       (0x0000000F)
+  #define DDRDATA5CH0_CR_RXPERBITRANK0_Lane7_OFF                       (28)
+  #define DDRDATA5CH0_CR_RXPERBITRANK0_Lane7_WID                       ( 4)
+  #define DDRDATA5CH0_CR_RXPERBITRANK0_Lane7_MSK                       (0xF0000000)
+  #define DDRDATA5CH0_CR_RXPERBITRANK0_Lane7_MAX                       (0x0000000F)
+
+#define DDRDATA5CH0_CR_RXPERBITRANK1_REG                             (0x00000A14)
+  #define DDRDATA5CH0_CR_RXPERBITRANK1_Lane0_OFF                       ( 0)
+  #define DDRDATA5CH0_CR_RXPERBITRANK1_Lane0_WID                       ( 4)
+  #define DDRDATA5CH0_CR_RXPERBITRANK1_Lane0_MSK                       (0x0000000F)
+  #define DDRDATA5CH0_CR_RXPERBITRANK1_Lane0_MAX                       (0x0000000F)
+  #define DDRDATA5CH0_CR_RXPERBITRANK1_Lane1_OFF                       ( 4)
+  #define DDRDATA5CH0_CR_RXPERBITRANK1_Lane1_WID                       ( 4)
+  #define DDRDATA5CH0_CR_RXPERBITRANK1_Lane1_MSK                       (0x000000F0)
+  #define DDRDATA5CH0_CR_RXPERBITRANK1_Lane1_MAX                       (0x0000000F)
+  #define DDRDATA5CH0_CR_RXPERBITRANK1_Lane2_OFF                       ( 8)
+  #define DDRDATA5CH0_CR_RXPERBITRANK1_Lane2_WID                       ( 4)
+  #define DDRDATA5CH0_CR_RXPERBITRANK1_Lane2_MSK                       (0x00000F00)
+  #define DDRDATA5CH0_CR_RXPERBITRANK1_Lane2_MAX                       (0x0000000F)
+  #define DDRDATA5CH0_CR_RXPERBITRANK1_Lane3_OFF                       (12)
+  #define DDRDATA5CH0_CR_RXPERBITRANK1_Lane3_WID                       ( 4)
+  #define DDRDATA5CH0_CR_RXPERBITRANK1_Lane3_MSK                       (0x0000F000)
+  #define DDRDATA5CH0_CR_RXPERBITRANK1_Lane3_MAX                       (0x0000000F)
+  #define DDRDATA5CH0_CR_RXPERBITRANK1_Lane4_OFF                       (16)
+  #define DDRDATA5CH0_CR_RXPERBITRANK1_Lane4_WID                       ( 4)
+  #define DDRDATA5CH0_CR_RXPERBITRANK1_Lane4_MSK                       (0x000F0000)
+  #define DDRDATA5CH0_CR_RXPERBITRANK1_Lane4_MAX                       (0x0000000F)
+  #define DDRDATA5CH0_CR_RXPERBITRANK1_Lane5_OFF                       (20)
+  #define DDRDATA5CH0_CR_RXPERBITRANK1_Lane5_WID                       ( 4)
+  #define DDRDATA5CH0_CR_RXPERBITRANK1_Lane5_MSK                       (0x00F00000)
+  #define DDRDATA5CH0_CR_RXPERBITRANK1_Lane5_MAX                       (0x0000000F)
+  #define DDRDATA5CH0_CR_RXPERBITRANK1_Lane6_OFF                       (24)
+  #define DDRDATA5CH0_CR_RXPERBITRANK1_Lane6_WID                       ( 4)
+  #define DDRDATA5CH0_CR_RXPERBITRANK1_Lane6_MSK                       (0x0F000000)
+  #define DDRDATA5CH0_CR_RXPERBITRANK1_Lane6_MAX                       (0x0000000F)
+  #define DDRDATA5CH0_CR_RXPERBITRANK1_Lane7_OFF                       (28)
+  #define DDRDATA5CH0_CR_RXPERBITRANK1_Lane7_WID                       ( 4)
+  #define DDRDATA5CH0_CR_RXPERBITRANK1_Lane7_MSK                       (0xF0000000)
+  #define DDRDATA5CH0_CR_RXPERBITRANK1_Lane7_MAX                       (0x0000000F)
+
+#define DDRDATA5CH0_CR_RXPERBITRANK2_REG                             (0x00000A18)
+  #define DDRDATA5CH0_CR_RXPERBITRANK2_Lane0_OFF                       ( 0)
+  #define DDRDATA5CH0_CR_RXPERBITRANK2_Lane0_WID                       ( 4)
+  #define DDRDATA5CH0_CR_RXPERBITRANK2_Lane0_MSK                       (0x0000000F)
+  #define DDRDATA5CH0_CR_RXPERBITRANK2_Lane0_MAX                       (0x0000000F)
+  #define DDRDATA5CH0_CR_RXPERBITRANK2_Lane1_OFF                       ( 4)
+  #define DDRDATA5CH0_CR_RXPERBITRANK2_Lane1_WID                       ( 4)
+  #define DDRDATA5CH0_CR_RXPERBITRANK2_Lane1_MSK                       (0x000000F0)
+  #define DDRDATA5CH0_CR_RXPERBITRANK2_Lane1_MAX                       (0x0000000F)
+  #define DDRDATA5CH0_CR_RXPERBITRANK2_Lane2_OFF                       ( 8)
+  #define DDRDATA5CH0_CR_RXPERBITRANK2_Lane2_WID                       ( 4)
+  #define DDRDATA5CH0_CR_RXPERBITRANK2_Lane2_MSK                       (0x00000F00)
+  #define DDRDATA5CH0_CR_RXPERBITRANK2_Lane2_MAX                       (0x0000000F)
+  #define DDRDATA5CH0_CR_RXPERBITRANK2_Lane3_OFF                       (12)
+  #define DDRDATA5CH0_CR_RXPERBITRANK2_Lane3_WID                       ( 4)
+  #define DDRDATA5CH0_CR_RXPERBITRANK2_Lane3_MSK                       (0x0000F000)
+  #define DDRDATA5CH0_CR_RXPERBITRANK2_Lane3_MAX                       (0x0000000F)
+  #define DDRDATA5CH0_CR_RXPERBITRANK2_Lane4_OFF                       (16)
+  #define DDRDATA5CH0_CR_RXPERBITRANK2_Lane4_WID                       ( 4)
+  #define DDRDATA5CH0_CR_RXPERBITRANK2_Lane4_MSK                       (0x000F0000)
+  #define DDRDATA5CH0_CR_RXPERBITRANK2_Lane4_MAX                       (0x0000000F)
+  #define DDRDATA5CH0_CR_RXPERBITRANK2_Lane5_OFF                       (20)
+  #define DDRDATA5CH0_CR_RXPERBITRANK2_Lane5_WID                       ( 4)
+  #define DDRDATA5CH0_CR_RXPERBITRANK2_Lane5_MSK                       (0x00F00000)
+  #define DDRDATA5CH0_CR_RXPERBITRANK2_Lane5_MAX                       (0x0000000F)
+  #define DDRDATA5CH0_CR_RXPERBITRANK2_Lane6_OFF                       (24)
+  #define DDRDATA5CH0_CR_RXPERBITRANK2_Lane6_WID                       ( 4)
+  #define DDRDATA5CH0_CR_RXPERBITRANK2_Lane6_MSK                       (0x0F000000)
+  #define DDRDATA5CH0_CR_RXPERBITRANK2_Lane6_MAX                       (0x0000000F)
+  #define DDRDATA5CH0_CR_RXPERBITRANK2_Lane7_OFF                       (28)
+  #define DDRDATA5CH0_CR_RXPERBITRANK2_Lane7_WID                       ( 4)
+  #define DDRDATA5CH0_CR_RXPERBITRANK2_Lane7_MSK                       (0xF0000000)
+  #define DDRDATA5CH0_CR_RXPERBITRANK2_Lane7_MAX                       (0x0000000F)
+
+#define DDRDATA5CH0_CR_RXPERBITRANK3_REG                             (0x00000A1C)
+  #define DDRDATA5CH0_CR_RXPERBITRANK3_Lane0_OFF                       ( 0)
+  #define DDRDATA5CH0_CR_RXPERBITRANK3_Lane0_WID                       ( 4)
+  #define DDRDATA5CH0_CR_RXPERBITRANK3_Lane0_MSK                       (0x0000000F)
+  #define DDRDATA5CH0_CR_RXPERBITRANK3_Lane0_MAX                       (0x0000000F)
+  #define DDRDATA5CH0_CR_RXPERBITRANK3_Lane1_OFF                       ( 4)
+  #define DDRDATA5CH0_CR_RXPERBITRANK3_Lane1_WID                       ( 4)
+  #define DDRDATA5CH0_CR_RXPERBITRANK3_Lane1_MSK                       (0x000000F0)
+  #define DDRDATA5CH0_CR_RXPERBITRANK3_Lane1_MAX                       (0x0000000F)
+  #define DDRDATA5CH0_CR_RXPERBITRANK3_Lane2_OFF                       ( 8)
+  #define DDRDATA5CH0_CR_RXPERBITRANK3_Lane2_WID                       ( 4)
+  #define DDRDATA5CH0_CR_RXPERBITRANK3_Lane2_MSK                       (0x00000F00)
+  #define DDRDATA5CH0_CR_RXPERBITRANK3_Lane2_MAX                       (0x0000000F)
+  #define DDRDATA5CH0_CR_RXPERBITRANK3_Lane3_OFF                       (12)
+  #define DDRDATA5CH0_CR_RXPERBITRANK3_Lane3_WID                       ( 4)
+  #define DDRDATA5CH0_CR_RXPERBITRANK3_Lane3_MSK                       (0x0000F000)
+  #define DDRDATA5CH0_CR_RXPERBITRANK3_Lane3_MAX                       (0x0000000F)
+  #define DDRDATA5CH0_CR_RXPERBITRANK3_Lane4_OFF                       (16)
+  #define DDRDATA5CH0_CR_RXPERBITRANK3_Lane4_WID                       ( 4)
+  #define DDRDATA5CH0_CR_RXPERBITRANK3_Lane4_MSK                       (0x000F0000)
+  #define DDRDATA5CH0_CR_RXPERBITRANK3_Lane4_MAX                       (0x0000000F)
+  #define DDRDATA5CH0_CR_RXPERBITRANK3_Lane5_OFF                       (20)
+  #define DDRDATA5CH0_CR_RXPERBITRANK3_Lane5_WID                       ( 4)
+  #define DDRDATA5CH0_CR_RXPERBITRANK3_Lane5_MSK                       (0x00F00000)
+  #define DDRDATA5CH0_CR_RXPERBITRANK3_Lane5_MAX                       (0x0000000F)
+  #define DDRDATA5CH0_CR_RXPERBITRANK3_Lane6_OFF                       (24)
+  #define DDRDATA5CH0_CR_RXPERBITRANK3_Lane6_WID                       ( 4)
+  #define DDRDATA5CH0_CR_RXPERBITRANK3_Lane6_MSK                       (0x0F000000)
+  #define DDRDATA5CH0_CR_RXPERBITRANK3_Lane6_MAX                       (0x0000000F)
+  #define DDRDATA5CH0_CR_RXPERBITRANK3_Lane7_OFF                       (28)
+  #define DDRDATA5CH0_CR_RXPERBITRANK3_Lane7_WID                       ( 4)
+  #define DDRDATA5CH0_CR_RXPERBITRANK3_Lane7_MSK                       (0xF0000000)
+  #define DDRDATA5CH0_CR_RXPERBITRANK3_Lane7_MAX                       (0x0000000F)
+
+#define DDRDATA5CH0_CR_TXTRAINRANK0_REG                              (0x00000A20)
+  #define DDRDATA5CH0_CR_TXTRAINRANK0_TxDqDelay_OFF                    ( 0)
+  #define DDRDATA5CH0_CR_TXTRAINRANK0_TxDqDelay_WID                    ( 9)
+  #define DDRDATA5CH0_CR_TXTRAINRANK0_TxDqDelay_MSK                    (0x000001FF)
+  #define DDRDATA5CH0_CR_TXTRAINRANK0_TxDqDelay_MAX                    (0x000001FF)
+  #define DDRDATA5CH0_CR_TXTRAINRANK0_TxDqsDelay_OFF                   ( 9)
+  #define DDRDATA5CH0_CR_TXTRAINRANK0_TxDqsDelay_WID                   ( 9)
+  #define DDRDATA5CH0_CR_TXTRAINRANK0_TxDqsDelay_MSK                   (0x0003FE00)
+  #define DDRDATA5CH0_CR_TXTRAINRANK0_TxDqsDelay_MAX                   (0x000001FF)
+  #define DDRDATA5CH0_CR_TXTRAINRANK0_Spare0_OFF                       (18)
+  #define DDRDATA5CH0_CR_TXTRAINRANK0_Spare0_WID                       ( 2)
+  #define DDRDATA5CH0_CR_TXTRAINRANK0_Spare0_MSK                       (0x000C0000)
+  #define DDRDATA5CH0_CR_TXTRAINRANK0_Spare0_MAX                       (0x00000003)
+  #define DDRDATA5CH0_CR_TXTRAINRANK0_TxEqualization_OFF               (20)
+  #define DDRDATA5CH0_CR_TXTRAINRANK0_TxEqualization_WID               ( 6)
+  #define DDRDATA5CH0_CR_TXTRAINRANK0_TxEqualization_MSK               (0x03F00000)
+  #define DDRDATA5CH0_CR_TXTRAINRANK0_TxEqualization_MAX               (0x0000003F)
+  #define DDRDATA5CH0_CR_TXTRAINRANK0_Spare1_OFF                       (26)
+  #define DDRDATA5CH0_CR_TXTRAINRANK0_Spare1_WID                       ( 6)
+  #define DDRDATA5CH0_CR_TXTRAINRANK0_Spare1_MSK                       (0xFC000000)
+  #define DDRDATA5CH0_CR_TXTRAINRANK0_Spare1_MAX                       (0x0000003F)
+
+#define DDRDATA5CH0_CR_TXTRAINRANK1_REG                              (0x00000A24)
+  #define DDRDATA5CH0_CR_TXTRAINRANK1_TxDqDelay_OFF                    ( 0)
+  #define DDRDATA5CH0_CR_TXTRAINRANK1_TxDqDelay_WID                    ( 9)
+  #define DDRDATA5CH0_CR_TXTRAINRANK1_TxDqDelay_MSK                    (0x000001FF)
+  #define DDRDATA5CH0_CR_TXTRAINRANK1_TxDqDelay_MAX                    (0x000001FF)
+  #define DDRDATA5CH0_CR_TXTRAINRANK1_TxDqsDelay_OFF                   ( 9)
+  #define DDRDATA5CH0_CR_TXTRAINRANK1_TxDqsDelay_WID                   ( 9)
+  #define DDRDATA5CH0_CR_TXTRAINRANK1_TxDqsDelay_MSK                   (0x0003FE00)
+  #define DDRDATA5CH0_CR_TXTRAINRANK1_TxDqsDelay_MAX                   (0x000001FF)
+  #define DDRDATA5CH0_CR_TXTRAINRANK1_Spare0_OFF                       (18)
+  #define DDRDATA5CH0_CR_TXTRAINRANK1_Spare0_WID                       ( 2)
+  #define DDRDATA5CH0_CR_TXTRAINRANK1_Spare0_MSK                       (0x000C0000)
+  #define DDRDATA5CH0_CR_TXTRAINRANK1_Spare0_MAX                       (0x00000003)
+  #define DDRDATA5CH0_CR_TXTRAINRANK1_TxEqualization_OFF               (20)
+  #define DDRDATA5CH0_CR_TXTRAINRANK1_TxEqualization_WID               ( 6)
+  #define DDRDATA5CH0_CR_TXTRAINRANK1_TxEqualization_MSK               (0x03F00000)
+  #define DDRDATA5CH0_CR_TXTRAINRANK1_TxEqualization_MAX               (0x0000003F)
+  #define DDRDATA5CH0_CR_TXTRAINRANK1_Spare1_OFF                       (26)
+  #define DDRDATA5CH0_CR_TXTRAINRANK1_Spare1_WID                       ( 6)
+  #define DDRDATA5CH0_CR_TXTRAINRANK1_Spare1_MSK                       (0xFC000000)
+  #define DDRDATA5CH0_CR_TXTRAINRANK1_Spare1_MAX                       (0x0000003F)
+
+#define DDRDATA5CH0_CR_TXTRAINRANK2_REG                              (0x00000A28)
+  #define DDRDATA5CH0_CR_TXTRAINRANK2_TxDqDelay_OFF                    ( 0)
+  #define DDRDATA5CH0_CR_TXTRAINRANK2_TxDqDelay_WID                    ( 9)
+  #define DDRDATA5CH0_CR_TXTRAINRANK2_TxDqDelay_MSK                    (0x000001FF)
+  #define DDRDATA5CH0_CR_TXTRAINRANK2_TxDqDelay_MAX                    (0x000001FF)
+  #define DDRDATA5CH0_CR_TXTRAINRANK2_TxDqsDelay_OFF                   ( 9)
+  #define DDRDATA5CH0_CR_TXTRAINRANK2_TxDqsDelay_WID                   ( 9)
+  #define DDRDATA5CH0_CR_TXTRAINRANK2_TxDqsDelay_MSK                   (0x0003FE00)
+  #define DDRDATA5CH0_CR_TXTRAINRANK2_TxDqsDelay_MAX                   (0x000001FF)
+  #define DDRDATA5CH0_CR_TXTRAINRANK2_Spare0_OFF                       (18)
+  #define DDRDATA5CH0_CR_TXTRAINRANK2_Spare0_WID                       ( 2)
+  #define DDRDATA5CH0_CR_TXTRAINRANK2_Spare0_MSK                       (0x000C0000)
+  #define DDRDATA5CH0_CR_TXTRAINRANK2_Spare0_MAX                       (0x00000003)
+  #define DDRDATA5CH0_CR_TXTRAINRANK2_TxEqualization_OFF               (20)
+  #define DDRDATA5CH0_CR_TXTRAINRANK2_TxEqualization_WID               ( 6)
+  #define DDRDATA5CH0_CR_TXTRAINRANK2_TxEqualization_MSK               (0x03F00000)
+  #define DDRDATA5CH0_CR_TXTRAINRANK2_TxEqualization_MAX               (0x0000003F)
+  #define DDRDATA5CH0_CR_TXTRAINRANK2_Spare1_OFF                       (26)
+  #define DDRDATA5CH0_CR_TXTRAINRANK2_Spare1_WID                       ( 6)
+  #define DDRDATA5CH0_CR_TXTRAINRANK2_Spare1_MSK                       (0xFC000000)
+  #define DDRDATA5CH0_CR_TXTRAINRANK2_Spare1_MAX                       (0x0000003F)
+
+#define DDRDATA5CH0_CR_TXTRAINRANK3_REG                              (0x00000A2C)
+  #define DDRDATA5CH0_CR_TXTRAINRANK3_TxDqDelay_OFF                    ( 0)
+  #define DDRDATA5CH0_CR_TXTRAINRANK3_TxDqDelay_WID                    ( 9)
+  #define DDRDATA5CH0_CR_TXTRAINRANK3_TxDqDelay_MSK                    (0x000001FF)
+  #define DDRDATA5CH0_CR_TXTRAINRANK3_TxDqDelay_MAX                    (0x000001FF)
+  #define DDRDATA5CH0_CR_TXTRAINRANK3_TxDqsDelay_OFF                   ( 9)
+  #define DDRDATA5CH0_CR_TXTRAINRANK3_TxDqsDelay_WID                   ( 9)
+  #define DDRDATA5CH0_CR_TXTRAINRANK3_TxDqsDelay_MSK                   (0x0003FE00)
+  #define DDRDATA5CH0_CR_TXTRAINRANK3_TxDqsDelay_MAX                   (0x000001FF)
+  #define DDRDATA5CH0_CR_TXTRAINRANK3_Spare0_OFF                       (18)
+  #define DDRDATA5CH0_CR_TXTRAINRANK3_Spare0_WID                       ( 2)
+  #define DDRDATA5CH0_CR_TXTRAINRANK3_Spare0_MSK                       (0x000C0000)
+  #define DDRDATA5CH0_CR_TXTRAINRANK3_Spare0_MAX                       (0x00000003)
+  #define DDRDATA5CH0_CR_TXTRAINRANK3_TxEqualization_OFF               (20)
+  #define DDRDATA5CH0_CR_TXTRAINRANK3_TxEqualization_WID               ( 6)
+  #define DDRDATA5CH0_CR_TXTRAINRANK3_TxEqualization_MSK               (0x03F00000)
+  #define DDRDATA5CH0_CR_TXTRAINRANK3_TxEqualization_MAX               (0x0000003F)
+  #define DDRDATA5CH0_CR_TXTRAINRANK3_Spare1_OFF                       (26)
+  #define DDRDATA5CH0_CR_TXTRAINRANK3_Spare1_WID                       ( 6)
+  #define DDRDATA5CH0_CR_TXTRAINRANK3_Spare1_MSK                       (0xFC000000)
+  #define DDRDATA5CH0_CR_TXTRAINRANK3_Spare1_MAX                       (0x0000003F)
+
+#define DDRDATA5CH0_CR_TXPERBITRANK0_REG                             (0x00000A30)
+  #define DDRDATA5CH0_CR_TXPERBITRANK0_Lane0_OFF                       ( 0)
+  #define DDRDATA5CH0_CR_TXPERBITRANK0_Lane0_WID                       ( 4)
+  #define DDRDATA5CH0_CR_TXPERBITRANK0_Lane0_MSK                       (0x0000000F)
+  #define DDRDATA5CH0_CR_TXPERBITRANK0_Lane0_MAX                       (0x0000000F)
+  #define DDRDATA5CH0_CR_TXPERBITRANK0_Lane1_OFF                       ( 4)
+  #define DDRDATA5CH0_CR_TXPERBITRANK0_Lane1_WID                       ( 4)
+  #define DDRDATA5CH0_CR_TXPERBITRANK0_Lane1_MSK                       (0x000000F0)
+  #define DDRDATA5CH0_CR_TXPERBITRANK0_Lane1_MAX                       (0x0000000F)
+  #define DDRDATA5CH0_CR_TXPERBITRANK0_Lane2_OFF                       ( 8)
+  #define DDRDATA5CH0_CR_TXPERBITRANK0_Lane2_WID                       ( 4)
+  #define DDRDATA5CH0_CR_TXPERBITRANK0_Lane2_MSK                       (0x00000F00)
+  #define DDRDATA5CH0_CR_TXPERBITRANK0_Lane2_MAX                       (0x0000000F)
+  #define DDRDATA5CH0_CR_TXPERBITRANK0_Lane3_OFF                       (12)
+  #define DDRDATA5CH0_CR_TXPERBITRANK0_Lane3_WID                       ( 4)
+  #define DDRDATA5CH0_CR_TXPERBITRANK0_Lane3_MSK                       (0x0000F000)
+  #define DDRDATA5CH0_CR_TXPERBITRANK0_Lane3_MAX                       (0x0000000F)
+  #define DDRDATA5CH0_CR_TXPERBITRANK0_Lane4_OFF                       (16)
+  #define DDRDATA5CH0_CR_TXPERBITRANK0_Lane4_WID                       ( 4)
+  #define DDRDATA5CH0_CR_TXPERBITRANK0_Lane4_MSK                       (0x000F0000)
+  #define DDRDATA5CH0_CR_TXPERBITRANK0_Lane4_MAX                       (0x0000000F)
+  #define DDRDATA5CH0_CR_TXPERBITRANK0_Lane5_OFF                       (20)
+  #define DDRDATA5CH0_CR_TXPERBITRANK0_Lane5_WID                       ( 4)
+  #define DDRDATA5CH0_CR_TXPERBITRANK0_Lane5_MSK                       (0x00F00000)
+  #define DDRDATA5CH0_CR_TXPERBITRANK0_Lane5_MAX                       (0x0000000F)
+  #define DDRDATA5CH0_CR_TXPERBITRANK0_Lane6_OFF                       (24)
+  #define DDRDATA5CH0_CR_TXPERBITRANK0_Lane6_WID                       ( 4)
+  #define DDRDATA5CH0_CR_TXPERBITRANK0_Lane6_MSK                       (0x0F000000)
+  #define DDRDATA5CH0_CR_TXPERBITRANK0_Lane6_MAX                       (0x0000000F)
+  #define DDRDATA5CH0_CR_TXPERBITRANK0_Lane7_OFF                       (28)
+  #define DDRDATA5CH0_CR_TXPERBITRANK0_Lane7_WID                       ( 4)
+  #define DDRDATA5CH0_CR_TXPERBITRANK0_Lane7_MSK                       (0xF0000000)
+  #define DDRDATA5CH0_CR_TXPERBITRANK0_Lane7_MAX                       (0x0000000F)
+
+#define DDRDATA5CH0_CR_TXPERBITRANK1_REG                             (0x00000A34)
+  #define DDRDATA5CH0_CR_TXPERBITRANK1_Lane0_OFF                       ( 0)
+  #define DDRDATA5CH0_CR_TXPERBITRANK1_Lane0_WID                       ( 4)
+  #define DDRDATA5CH0_CR_TXPERBITRANK1_Lane0_MSK                       (0x0000000F)
+  #define DDRDATA5CH0_CR_TXPERBITRANK1_Lane0_MAX                       (0x0000000F)
+  #define DDRDATA5CH0_CR_TXPERBITRANK1_Lane1_OFF                       ( 4)
+  #define DDRDATA5CH0_CR_TXPERBITRANK1_Lane1_WID                       ( 4)
+  #define DDRDATA5CH0_CR_TXPERBITRANK1_Lane1_MSK                       (0x000000F0)
+  #define DDRDATA5CH0_CR_TXPERBITRANK1_Lane1_MAX                       (0x0000000F)
+  #define DDRDATA5CH0_CR_TXPERBITRANK1_Lane2_OFF                       ( 8)
+  #define DDRDATA5CH0_CR_TXPERBITRANK1_Lane2_WID                       ( 4)
+  #define DDRDATA5CH0_CR_TXPERBITRANK1_Lane2_MSK                       (0x00000F00)
+  #define DDRDATA5CH0_CR_TXPERBITRANK1_Lane2_MAX                       (0x0000000F)
+  #define DDRDATA5CH0_CR_TXPERBITRANK1_Lane3_OFF                       (12)
+  #define DDRDATA5CH0_CR_TXPERBITRANK1_Lane3_WID                       ( 4)
+  #define DDRDATA5CH0_CR_TXPERBITRANK1_Lane3_MSK                       (0x0000F000)
+  #define DDRDATA5CH0_CR_TXPERBITRANK1_Lane3_MAX                       (0x0000000F)
+  #define DDRDATA5CH0_CR_TXPERBITRANK1_Lane4_OFF                       (16)
+  #define DDRDATA5CH0_CR_TXPERBITRANK1_Lane4_WID                       ( 4)
+  #define DDRDATA5CH0_CR_TXPERBITRANK1_Lane4_MSK                       (0x000F0000)
+  #define DDRDATA5CH0_CR_TXPERBITRANK1_Lane4_MAX                       (0x0000000F)
+  #define DDRDATA5CH0_CR_TXPERBITRANK1_Lane5_OFF                       (20)
+  #define DDRDATA5CH0_CR_TXPERBITRANK1_Lane5_WID                       ( 4)
+  #define DDRDATA5CH0_CR_TXPERBITRANK1_Lane5_MSK                       (0x00F00000)
+  #define DDRDATA5CH0_CR_TXPERBITRANK1_Lane5_MAX                       (0x0000000F)
+  #define DDRDATA5CH0_CR_TXPERBITRANK1_Lane6_OFF                       (24)
+  #define DDRDATA5CH0_CR_TXPERBITRANK1_Lane6_WID                       ( 4)
+  #define DDRDATA5CH0_CR_TXPERBITRANK1_Lane6_MSK                       (0x0F000000)
+  #define DDRDATA5CH0_CR_TXPERBITRANK1_Lane6_MAX                       (0x0000000F)
+  #define DDRDATA5CH0_CR_TXPERBITRANK1_Lane7_OFF                       (28)
+  #define DDRDATA5CH0_CR_TXPERBITRANK1_Lane7_WID                       ( 4)
+  #define DDRDATA5CH0_CR_TXPERBITRANK1_Lane7_MSK                       (0xF0000000)
+  #define DDRDATA5CH0_CR_TXPERBITRANK1_Lane7_MAX                       (0x0000000F)
+
+#define DDRDATA5CH0_CR_TXPERBITRANK2_REG                             (0x00000A38)
+  #define DDRDATA5CH0_CR_TXPERBITRANK2_Lane0_OFF                       ( 0)
+  #define DDRDATA5CH0_CR_TXPERBITRANK2_Lane0_WID                       ( 4)
+  #define DDRDATA5CH0_CR_TXPERBITRANK2_Lane0_MSK                       (0x0000000F)
+  #define DDRDATA5CH0_CR_TXPERBITRANK2_Lane0_MAX                       (0x0000000F)
+  #define DDRDATA5CH0_CR_TXPERBITRANK2_Lane1_OFF                       ( 4)
+  #define DDRDATA5CH0_CR_TXPERBITRANK2_Lane1_WID                       ( 4)
+  #define DDRDATA5CH0_CR_TXPERBITRANK2_Lane1_MSK                       (0x000000F0)
+  #define DDRDATA5CH0_CR_TXPERBITRANK2_Lane1_MAX                       (0x0000000F)
+  #define DDRDATA5CH0_CR_TXPERBITRANK2_Lane2_OFF                       ( 8)
+  #define DDRDATA5CH0_CR_TXPERBITRANK2_Lane2_WID                       ( 4)
+  #define DDRDATA5CH0_CR_TXPERBITRANK2_Lane2_MSK                       (0x00000F00)
+  #define DDRDATA5CH0_CR_TXPERBITRANK2_Lane2_MAX                       (0x0000000F)
+  #define DDRDATA5CH0_CR_TXPERBITRANK2_Lane3_OFF                       (12)
+  #define DDRDATA5CH0_CR_TXPERBITRANK2_Lane3_WID                       ( 4)
+  #define DDRDATA5CH0_CR_TXPERBITRANK2_Lane3_MSK                       (0x0000F000)
+  #define DDRDATA5CH0_CR_TXPERBITRANK2_Lane3_MAX                       (0x0000000F)
+  #define DDRDATA5CH0_CR_TXPERBITRANK2_Lane4_OFF                       (16)
+  #define DDRDATA5CH0_CR_TXPERBITRANK2_Lane4_WID                       ( 4)
+  #define DDRDATA5CH0_CR_TXPERBITRANK2_Lane4_MSK                       (0x000F0000)
+  #define DDRDATA5CH0_CR_TXPERBITRANK2_Lane4_MAX                       (0x0000000F)
+  #define DDRDATA5CH0_CR_TXPERBITRANK2_Lane5_OFF                       (20)
+  #define DDRDATA5CH0_CR_TXPERBITRANK2_Lane5_WID                       ( 4)
+  #define DDRDATA5CH0_CR_TXPERBITRANK2_Lane5_MSK                       (0x00F00000)
+  #define DDRDATA5CH0_CR_TXPERBITRANK2_Lane5_MAX                       (0x0000000F)
+  #define DDRDATA5CH0_CR_TXPERBITRANK2_Lane6_OFF                       (24)
+  #define DDRDATA5CH0_CR_TXPERBITRANK2_Lane6_WID                       ( 4)
+  #define DDRDATA5CH0_CR_TXPERBITRANK2_Lane6_MSK                       (0x0F000000)
+  #define DDRDATA5CH0_CR_TXPERBITRANK2_Lane6_MAX                       (0x0000000F)
+  #define DDRDATA5CH0_CR_TXPERBITRANK2_Lane7_OFF                       (28)
+  #define DDRDATA5CH0_CR_TXPERBITRANK2_Lane7_WID                       ( 4)
+  #define DDRDATA5CH0_CR_TXPERBITRANK2_Lane7_MSK                       (0xF0000000)
+  #define DDRDATA5CH0_CR_TXPERBITRANK2_Lane7_MAX                       (0x0000000F)
+
+#define DDRDATA5CH0_CR_TXPERBITRANK3_REG                             (0x00000A3C)
+  #define DDRDATA5CH0_CR_TXPERBITRANK3_Lane0_OFF                       ( 0)
+  #define DDRDATA5CH0_CR_TXPERBITRANK3_Lane0_WID                       ( 4)
+  #define DDRDATA5CH0_CR_TXPERBITRANK3_Lane0_MSK                       (0x0000000F)
+  #define DDRDATA5CH0_CR_TXPERBITRANK3_Lane0_MAX                       (0x0000000F)
+  #define DDRDATA5CH0_CR_TXPERBITRANK3_Lane1_OFF                       ( 4)
+  #define DDRDATA5CH0_CR_TXPERBITRANK3_Lane1_WID                       ( 4)
+  #define DDRDATA5CH0_CR_TXPERBITRANK3_Lane1_MSK                       (0x000000F0)
+  #define DDRDATA5CH0_CR_TXPERBITRANK3_Lane1_MAX                       (0x0000000F)
+  #define DDRDATA5CH0_CR_TXPERBITRANK3_Lane2_OFF                       ( 8)
+  #define DDRDATA5CH0_CR_TXPERBITRANK3_Lane2_WID                       ( 4)
+  #define DDRDATA5CH0_CR_TXPERBITRANK3_Lane2_MSK                       (0x00000F00)
+  #define DDRDATA5CH0_CR_TXPERBITRANK3_Lane2_MAX                       (0x0000000F)
+  #define DDRDATA5CH0_CR_TXPERBITRANK3_Lane3_OFF                       (12)
+  #define DDRDATA5CH0_CR_TXPERBITRANK3_Lane3_WID                       ( 4)
+  #define DDRDATA5CH0_CR_TXPERBITRANK3_Lane3_MSK                       (0x0000F000)
+  #define DDRDATA5CH0_CR_TXPERBITRANK3_Lane3_MAX                       (0x0000000F)
+  #define DDRDATA5CH0_CR_TXPERBITRANK3_Lane4_OFF                       (16)
+  #define DDRDATA5CH0_CR_TXPERBITRANK3_Lane4_WID                       ( 4)
+  #define DDRDATA5CH0_CR_TXPERBITRANK3_Lane4_MSK                       (0x000F0000)
+  #define DDRDATA5CH0_CR_TXPERBITRANK3_Lane4_MAX                       (0x0000000F)
+  #define DDRDATA5CH0_CR_TXPERBITRANK3_Lane5_OFF                       (20)
+  #define DDRDATA5CH0_CR_TXPERBITRANK3_Lane5_WID                       ( 4)
+  #define DDRDATA5CH0_CR_TXPERBITRANK3_Lane5_MSK                       (0x00F00000)
+  #define DDRDATA5CH0_CR_TXPERBITRANK3_Lane5_MAX                       (0x0000000F)
+  #define DDRDATA5CH0_CR_TXPERBITRANK3_Lane6_OFF                       (24)
+  #define DDRDATA5CH0_CR_TXPERBITRANK3_Lane6_WID                       ( 4)
+  #define DDRDATA5CH0_CR_TXPERBITRANK3_Lane6_MSK                       (0x0F000000)
+  #define DDRDATA5CH0_CR_TXPERBITRANK3_Lane6_MAX                       (0x0000000F)
+  #define DDRDATA5CH0_CR_TXPERBITRANK3_Lane7_OFF                       (28)
+  #define DDRDATA5CH0_CR_TXPERBITRANK3_Lane7_WID                       ( 4)
+  #define DDRDATA5CH0_CR_TXPERBITRANK3_Lane7_MSK                       (0xF0000000)
+  #define DDRDATA5CH0_CR_TXPERBITRANK3_Lane7_MAX                       (0x0000000F)
+
+#define DDRDATA5CH0_CR_RCOMPDATA0_REG                                (0x00000A40)
+  #define DDRDATA5CH0_CR_RCOMPDATA0_RcompDrvUp_OFF                     ( 0)
+  #define DDRDATA5CH0_CR_RCOMPDATA0_RcompDrvUp_WID                     ( 6)
+  #define DDRDATA5CH0_CR_RCOMPDATA0_RcompDrvUp_MSK                     (0x0000003F)
+  #define DDRDATA5CH0_CR_RCOMPDATA0_RcompDrvUp_MAX                     (0x0000003F)
+  #define DDRDATA5CH0_CR_RCOMPDATA0_Spare0_OFF                         ( 6)
+  #define DDRDATA5CH0_CR_RCOMPDATA0_Spare0_WID                         ( 3)
+  #define DDRDATA5CH0_CR_RCOMPDATA0_Spare0_MSK                         (0x000001C0)
+  #define DDRDATA5CH0_CR_RCOMPDATA0_Spare0_MAX                         (0x00000007)
+  #define DDRDATA5CH0_CR_RCOMPDATA0_RcompDrvDown_OFF                   ( 9)
+  #define DDRDATA5CH0_CR_RCOMPDATA0_RcompDrvDown_WID                   ( 6)
+  #define DDRDATA5CH0_CR_RCOMPDATA0_RcompDrvDown_MSK                   (0x00007E00)
+  #define DDRDATA5CH0_CR_RCOMPDATA0_RcompDrvDown_MAX                   (0x0000003F)
+  #define DDRDATA5CH0_CR_RCOMPDATA0_VTComp_OFF                         (15)
+  #define DDRDATA5CH0_CR_RCOMPDATA0_VTComp_WID                         ( 5)
+  #define DDRDATA5CH0_CR_RCOMPDATA0_VTComp_MSK                         (0x000F8000)
+  #define DDRDATA5CH0_CR_RCOMPDATA0_VTComp_MAX                         (0x0000001F)
+  #define DDRDATA5CH0_CR_RCOMPDATA0_TcoComp_OFF                        (20)
+  #define DDRDATA5CH0_CR_RCOMPDATA0_TcoComp_WID                        ( 6)
+  #define DDRDATA5CH0_CR_RCOMPDATA0_TcoComp_MSK                        (0x03F00000)
+  #define DDRDATA5CH0_CR_RCOMPDATA0_TcoComp_MAX                        (0x0000003F)
+  #define DDRDATA5CH0_CR_RCOMPDATA0_SlewRateComp_OFF                   (26)
+  #define DDRDATA5CH0_CR_RCOMPDATA0_SlewRateComp_WID                   ( 5)
+  #define DDRDATA5CH0_CR_RCOMPDATA0_SlewRateComp_MSK                   (0x7C000000)
+  #define DDRDATA5CH0_CR_RCOMPDATA0_SlewRateComp_MAX                   (0x0000001F)
+  #define DDRDATA5CH0_CR_RCOMPDATA0_Spare2_OFF                         (31)
+  #define DDRDATA5CH0_CR_RCOMPDATA0_Spare2_WID                         ( 1)
+  #define DDRDATA5CH0_CR_RCOMPDATA0_Spare2_MSK                         (0x80000000)
+  #define DDRDATA5CH0_CR_RCOMPDATA0_Spare2_MAX                         (0x00000001)
+
+#define DDRDATA5CH0_CR_RCOMPDATA1_REG                                (0x00000A44)
+  #define DDRDATA5CH0_CR_RCOMPDATA1_RcompOdtUp_OFF                     ( 0)
+  #define DDRDATA5CH0_CR_RCOMPDATA1_RcompOdtUp_WID                     ( 6)
+  #define DDRDATA5CH0_CR_RCOMPDATA1_RcompOdtUp_MSK                     (0x0000003F)
+  #define DDRDATA5CH0_CR_RCOMPDATA1_RcompOdtUp_MAX                     (0x0000003F)
+  #define DDRDATA5CH0_CR_RCOMPDATA1_Spare0_OFF                         ( 6)
+  #define DDRDATA5CH0_CR_RCOMPDATA1_Spare0_WID                         ( 3)
+  #define DDRDATA5CH0_CR_RCOMPDATA1_Spare0_MSK                         (0x000001C0)
+  #define DDRDATA5CH0_CR_RCOMPDATA1_Spare0_MAX                         (0x00000007)
+  #define DDRDATA5CH0_CR_RCOMPDATA1_RcompOdtDown_OFF                   ( 9)
+  #define DDRDATA5CH0_CR_RCOMPDATA1_RcompOdtDown_WID                   ( 6)
+  #define DDRDATA5CH0_CR_RCOMPDATA1_RcompOdtDown_MSK                   (0x00007E00)
+  #define DDRDATA5CH0_CR_RCOMPDATA1_RcompOdtDown_MAX                   (0x0000003F)
+  #define DDRDATA5CH0_CR_RCOMPDATA1_Spare1_OFF                         (15)
+  #define DDRDATA5CH0_CR_RCOMPDATA1_Spare1_WID                         ( 1)
+  #define DDRDATA5CH0_CR_RCOMPDATA1_Spare1_MSK                         (0x00008000)
+  #define DDRDATA5CH0_CR_RCOMPDATA1_Spare1_MAX                         (0x00000001)
+  #define DDRDATA5CH0_CR_RCOMPDATA1_PanicDrvDn_OFF                     (16)
+  #define DDRDATA5CH0_CR_RCOMPDATA1_PanicDrvDn_WID                     ( 6)
+  #define DDRDATA5CH0_CR_RCOMPDATA1_PanicDrvDn_MSK                     (0x003F0000)
+  #define DDRDATA5CH0_CR_RCOMPDATA1_PanicDrvDn_MAX                     (0x0000003F)
+  #define DDRDATA5CH0_CR_RCOMPDATA1_PanicDrvUp_OFF                     (22)
+  #define DDRDATA5CH0_CR_RCOMPDATA1_PanicDrvUp_WID                     ( 6)
+  #define DDRDATA5CH0_CR_RCOMPDATA1_PanicDrvUp_MSK                     (0x0FC00000)
+  #define DDRDATA5CH0_CR_RCOMPDATA1_PanicDrvUp_MAX                     (0x0000003F)
+  #define DDRDATA5CH0_CR_RCOMPDATA1_LevelShifterComp_OFF               (28)
+  #define DDRDATA5CH0_CR_RCOMPDATA1_LevelShifterComp_WID               ( 3)
+  #define DDRDATA5CH0_CR_RCOMPDATA1_LevelShifterComp_MSK               (0x70000000)
+  #define DDRDATA5CH0_CR_RCOMPDATA1_LevelShifterComp_MAX               (0x00000007)
+  #define DDRDATA5CH0_CR_RCOMPDATA1_Spare2_OFF                         (31)
+  #define DDRDATA5CH0_CR_RCOMPDATA1_Spare2_WID                         ( 1)
+  #define DDRDATA5CH0_CR_RCOMPDATA1_Spare2_MSK                         (0x80000000)
+  #define DDRDATA5CH0_CR_RCOMPDATA1_Spare2_MAX                         (0x00000001)
+
+#define DDRDATA5CH0_CR_TXXTALK_REG                                   (0x00000A48)
+  #define DDRDATA5CH0_CR_TXXTALK_Lane0_OFF                             ( 0)
+  #define DDRDATA5CH0_CR_TXXTALK_Lane0_WID                             ( 4)
+  #define DDRDATA5CH0_CR_TXXTALK_Lane0_MSK                             (0x0000000F)
+  #define DDRDATA5CH0_CR_TXXTALK_Lane0_MAX                             (0x0000000F)
+  #define DDRDATA5CH0_CR_TXXTALK_Lane1_OFF                             ( 4)
+  #define DDRDATA5CH0_CR_TXXTALK_Lane1_WID                             ( 4)
+  #define DDRDATA5CH0_CR_TXXTALK_Lane1_MSK                             (0x000000F0)
+  #define DDRDATA5CH0_CR_TXXTALK_Lane1_MAX                             (0x0000000F)
+  #define DDRDATA5CH0_CR_TXXTALK_Lane2_OFF                             ( 8)
+  #define DDRDATA5CH0_CR_TXXTALK_Lane2_WID                             ( 4)
+  #define DDRDATA5CH0_CR_TXXTALK_Lane2_MSK                             (0x00000F00)
+  #define DDRDATA5CH0_CR_TXXTALK_Lane2_MAX                             (0x0000000F)
+  #define DDRDATA5CH0_CR_TXXTALK_Lane3_OFF                             (12)
+  #define DDRDATA5CH0_CR_TXXTALK_Lane3_WID                             ( 4)
+  #define DDRDATA5CH0_CR_TXXTALK_Lane3_MSK                             (0x0000F000)
+  #define DDRDATA5CH0_CR_TXXTALK_Lane3_MAX                             (0x0000000F)
+  #define DDRDATA5CH0_CR_TXXTALK_Lane4_OFF                             (16)
+  #define DDRDATA5CH0_CR_TXXTALK_Lane4_WID                             ( 4)
+  #define DDRDATA5CH0_CR_TXXTALK_Lane4_MSK                             (0x000F0000)
+  #define DDRDATA5CH0_CR_TXXTALK_Lane4_MAX                             (0x0000000F)
+  #define DDRDATA5CH0_CR_TXXTALK_Lane5_OFF                             (20)
+  #define DDRDATA5CH0_CR_TXXTALK_Lane5_WID                             ( 4)
+  #define DDRDATA5CH0_CR_TXXTALK_Lane5_MSK                             (0x00F00000)
+  #define DDRDATA5CH0_CR_TXXTALK_Lane5_MAX                             (0x0000000F)
+  #define DDRDATA5CH0_CR_TXXTALK_Lane6_OFF                             (24)
+  #define DDRDATA5CH0_CR_TXXTALK_Lane6_WID                             ( 4)
+  #define DDRDATA5CH0_CR_TXXTALK_Lane6_MSK                             (0x0F000000)
+  #define DDRDATA5CH0_CR_TXXTALK_Lane6_MAX                             (0x0000000F)
+  #define DDRDATA5CH0_CR_TXXTALK_Lane7_OFF                             (28)
+  #define DDRDATA5CH0_CR_TXXTALK_Lane7_WID                             ( 4)
+  #define DDRDATA5CH0_CR_TXXTALK_Lane7_MSK                             (0xF0000000)
+  #define DDRDATA5CH0_CR_TXXTALK_Lane7_MAX                             (0x0000000F)
+
+#define DDRDATA5CH0_CR_RXOFFSETVDQ_REG                               (0x00000A4C)
+  #define DDRDATA5CH0_CR_RXOFFSETVDQ_Lane0_OFF                         ( 0)
+  #define DDRDATA5CH0_CR_RXOFFSETVDQ_Lane0_WID                         ( 4)
+  #define DDRDATA5CH0_CR_RXOFFSETVDQ_Lane0_MSK                         (0x0000000F)
+  #define DDRDATA5CH0_CR_RXOFFSETVDQ_Lane0_MAX                         (0x0000000F)
+  #define DDRDATA5CH0_CR_RXOFFSETVDQ_Lane1_OFF                         ( 4)
+  #define DDRDATA5CH0_CR_RXOFFSETVDQ_Lane1_WID                         ( 4)
+  #define DDRDATA5CH0_CR_RXOFFSETVDQ_Lane1_MSK                         (0x000000F0)
+  #define DDRDATA5CH0_CR_RXOFFSETVDQ_Lane1_MAX                         (0x0000000F)
+  #define DDRDATA5CH0_CR_RXOFFSETVDQ_Lane2_OFF                         ( 8)
+  #define DDRDATA5CH0_CR_RXOFFSETVDQ_Lane2_WID                         ( 4)
+  #define DDRDATA5CH0_CR_RXOFFSETVDQ_Lane2_MSK                         (0x00000F00)
+  #define DDRDATA5CH0_CR_RXOFFSETVDQ_Lane2_MAX                         (0x0000000F)
+  #define DDRDATA5CH0_CR_RXOFFSETVDQ_Lane3_OFF                         (12)
+  #define DDRDATA5CH0_CR_RXOFFSETVDQ_Lane3_WID                         ( 4)
+  #define DDRDATA5CH0_CR_RXOFFSETVDQ_Lane3_MSK                         (0x0000F000)
+  #define DDRDATA5CH0_CR_RXOFFSETVDQ_Lane3_MAX                         (0x0000000F)
+  #define DDRDATA5CH0_CR_RXOFFSETVDQ_Lane4_OFF                         (16)
+  #define DDRDATA5CH0_CR_RXOFFSETVDQ_Lane4_WID                         ( 4)
+  #define DDRDATA5CH0_CR_RXOFFSETVDQ_Lane4_MSK                         (0x000F0000)
+  #define DDRDATA5CH0_CR_RXOFFSETVDQ_Lane4_MAX                         (0x0000000F)
+  #define DDRDATA5CH0_CR_RXOFFSETVDQ_Lane5_OFF                         (20)
+  #define DDRDATA5CH0_CR_RXOFFSETVDQ_Lane5_WID                         ( 4)
+  #define DDRDATA5CH0_CR_RXOFFSETVDQ_Lane5_MSK                         (0x00F00000)
+  #define DDRDATA5CH0_CR_RXOFFSETVDQ_Lane5_MAX                         (0x0000000F)
+  #define DDRDATA5CH0_CR_RXOFFSETVDQ_Lane6_OFF                         (24)
+  #define DDRDATA5CH0_CR_RXOFFSETVDQ_Lane6_WID                         ( 4)
+  #define DDRDATA5CH0_CR_RXOFFSETVDQ_Lane6_MSK                         (0x0F000000)
+  #define DDRDATA5CH0_CR_RXOFFSETVDQ_Lane6_MAX                         (0x0000000F)
+  #define DDRDATA5CH0_CR_RXOFFSETVDQ_Lane7_OFF                         (28)
+  #define DDRDATA5CH0_CR_RXOFFSETVDQ_Lane7_WID                         ( 4)
+  #define DDRDATA5CH0_CR_RXOFFSETVDQ_Lane7_MSK                         (0xF0000000)
+  #define DDRDATA5CH0_CR_RXOFFSETVDQ_Lane7_MAX                         (0x0000000F)
+
+#define DDRDATA5CH0_CR_DDRDATARESERVED_REG                           (0x00000A50)
+  #define DDRDATA5CH0_CR_DDRDATARESERVED_Spare_OFF                     ( 0)
+  #define DDRDATA5CH0_CR_DDRDATARESERVED_Spare_WID                     (32)
+  #define DDRDATA5CH0_CR_DDRDATARESERVED_Spare_MSK                     (0xFFFFFFFF)
+  #define DDRDATA5CH0_CR_DDRDATARESERVED_Spare_MAX                     (0xFFFFFFFF)
+
+#define DDRDATA5CH0_CR_DATATRAINFEEDBACK_REG                         (0x00000A54)
+  #define DDRDATA5CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_OFF       ( 0)
+  #define DDRDATA5CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_WID       ( 9)
+  #define DDRDATA5CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_MSK       (0x000001FF)
+  #define DDRDATA5CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_MAX       (0x000001FF)
+  #define DDRDATA5CH0_CR_DATATRAINFEEDBACK_Spare_OFF                   ( 9)
+  #define DDRDATA5CH0_CR_DATATRAINFEEDBACK_Spare_WID                   (23)
+  #define DDRDATA5CH0_CR_DATATRAINFEEDBACK_Spare_MSK                   (0xFFFFFE00)
+  #define DDRDATA5CH0_CR_DATATRAINFEEDBACK_Spare_MAX                   (0x007FFFFF)
+
+#define DDRDATA5CH0_CR_DLLPITESTANDADC_REG                           (0x00000A58)
+  #define DDRDATA5CH0_CR_DLLPITESTANDADC_RunTest_OFF                   ( 0)
+  #define DDRDATA5CH0_CR_DLLPITESTANDADC_RunTest_WID                   ( 1)
+  #define DDRDATA5CH0_CR_DLLPITESTANDADC_RunTest_MSK                   (0x00000001)
+  #define DDRDATA5CH0_CR_DLLPITESTANDADC_RunTest_MAX                   (0x00000001)
+  #define DDRDATA5CH0_CR_DLLPITESTANDADC_RunTest_DEF                   (0x00000000)
+  #define DDRDATA5CH0_CR_DLLPITESTANDADC_Load_OFF                      ( 1)
+  #define DDRDATA5CH0_CR_DLLPITESTANDADC_Load_WID                      ( 1)
+  #define DDRDATA5CH0_CR_DLLPITESTANDADC_Load_MSK                      (0x00000002)
+  #define DDRDATA5CH0_CR_DLLPITESTANDADC_Load_MAX                      (0x00000001)
+  #define DDRDATA5CH0_CR_DLLPITESTANDADC_Load_DEF                      (0x00000000)
+  #define DDRDATA5CH0_CR_DLLPITESTANDADC_ModeHVM_OFF                   ( 2)
+  #define DDRDATA5CH0_CR_DLLPITESTANDADC_ModeHVM_WID                   ( 1)
+  #define DDRDATA5CH0_CR_DLLPITESTANDADC_ModeHVM_MSK                   (0x00000004)
+  #define DDRDATA5CH0_CR_DLLPITESTANDADC_ModeHVM_MAX                   (0x00000001)
+  #define DDRDATA5CH0_CR_DLLPITESTANDADC_ModeHVM_DEF                   (0x00000000)
+  #define DDRDATA5CH0_CR_DLLPITESTANDADC_ModeDV_OFF                    ( 3)
+  #define DDRDATA5CH0_CR_DLLPITESTANDADC_ModeDV_WID                    ( 1)
+  #define DDRDATA5CH0_CR_DLLPITESTANDADC_ModeDV_MSK                    (0x00000008)
+  #define DDRDATA5CH0_CR_DLLPITESTANDADC_ModeDV_MAX                    (0x00000001)
+  #define DDRDATA5CH0_CR_DLLPITESTANDADC_ModeDV_DEF                    (0x00000000)
+  #define DDRDATA5CH0_CR_DLLPITESTANDADC_ModeADC_OFF                   ( 4)
+  #define DDRDATA5CH0_CR_DLLPITESTANDADC_ModeADC_WID                   ( 1)
+  #define DDRDATA5CH0_CR_DLLPITESTANDADC_ModeADC_MSK                   (0x00000010)
+  #define DDRDATA5CH0_CR_DLLPITESTANDADC_ModeADC_MAX                   (0x00000001)
+  #define DDRDATA5CH0_CR_DLLPITESTANDADC_ModeADC_DEF                   (0x00000000)
+  #define DDRDATA5CH0_CR_DLLPITESTANDADC_LoadCount_OFF                 ( 5)
+  #define DDRDATA5CH0_CR_DLLPITESTANDADC_LoadCount_WID                 (10)
+  #define DDRDATA5CH0_CR_DLLPITESTANDADC_LoadCount_MSK                 (0x00007FE0)
+  #define DDRDATA5CH0_CR_DLLPITESTANDADC_LoadCount_MAX                 (0x000003FF)
+  #define DDRDATA5CH0_CR_DLLPITESTANDADC_CountStatus_OFF               (15)
+  #define DDRDATA5CH0_CR_DLLPITESTANDADC_CountStatus_WID               (10)
+  #define DDRDATA5CH0_CR_DLLPITESTANDADC_CountStatus_MSK               (0x01FF8000)
+  #define DDRDATA5CH0_CR_DLLPITESTANDADC_CountStatus_MAX               (0x000003FF)
+  #define DDRDATA5CH0_CR_DLLPITESTANDADC_CountStatus_DEF               (0x00000000)
+  #define DDRDATA5CH0_CR_DLLPITESTANDADC_Spare_OFF                     (25)
+  #define DDRDATA5CH0_CR_DLLPITESTANDADC_Spare_WID                     ( 7)
+  #define DDRDATA5CH0_CR_DLLPITESTANDADC_Spare_MSK                     (0xFE000000)
+  #define DDRDATA5CH0_CR_DLLPITESTANDADC_Spare_MAX                     (0x0000007F)
+
+#define DDRDATA5CH0_CR_DDRCRDATAOFFSETCOMP_REG                       (0x00000A5C)
+  #define DDRDATA5CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_OFF     ( 0)
+  #define DDRDATA5CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_WID     ( 6)
+  #define DDRDATA5CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MSK     (0x0000003F)
+  #define DDRDATA5CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MAX     (0x0000003F)
+  #define DDRDATA5CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_DEF     (0x00000000)
+  #define DDRDATA5CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_OFF   ( 6)
+  #define DDRDATA5CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_WID   ( 6)
+  #define DDRDATA5CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MSK   (0x00000FC0)
+  #define DDRDATA5CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MAX   (0x0000003F)
+  #define DDRDATA5CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_DEF   (0x00000000)
+  #define DDRDATA5CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_OFF     (12)
+  #define DDRDATA5CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_WID     ( 5)
+  #define DDRDATA5CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MSK     (0x0001F000)
+  #define DDRDATA5CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MAX     (0x0000001F)
+  #define DDRDATA5CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_DEF     (0x00000000)
+  #define DDRDATA5CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_OFF   (17)
+  #define DDRDATA5CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_WID   ( 5)
+  #define DDRDATA5CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MSK   (0x003E0000)
+  #define DDRDATA5CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MAX   (0x0000001F)
+  #define DDRDATA5CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_DEF   (0x00000000)
+  #define DDRDATA5CH0_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_OFF       (22)
+  #define DDRDATA5CH0_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_WID       ( 5)
+  #define DDRDATA5CH0_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_MSK       (0x07C00000)
+  #define DDRDATA5CH0_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_MAX       (0x0000001F)
+  #define DDRDATA5CH0_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_DEF       (0x00000000)
+  #define DDRDATA5CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_OFF  (27)
+  #define DDRDATA5CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_WID  ( 5)
+  #define DDRDATA5CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MSK  (0xF8000000)
+  #define DDRDATA5CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MAX  (0x0000001F)
+  #define DDRDATA5CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_DEF  (0x00000000)
+
+#define DDRDATA5CH0_CR_DDRCRDATACONTROL1_REG                         (0x00000A60)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_RefPi_OFF                   ( 0)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_RefPi_WID                   ( 4)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_RefPi_MSK                   (0x0000000F)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_RefPi_MAX                   (0x0000000F)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_RefPi_DEF                   (0x00000000)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_DllMask_OFF                 ( 4)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_DllMask_WID                 ( 2)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_DllMask_MSK                 (0x00000030)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_DllMask_MAX                 (0x00000003)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_DllMask_DEF                 (0x00000000)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_DllWeakLock_OFF             ( 6)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_DllWeakLock_WID             ( 1)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_DllWeakLock_MSK             (0x00000040)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_DllWeakLock_MAX             (0x00000001)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_DllWeakLock_DEF             (0x00000000)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_OFF      ( 7)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_WID      ( 3)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MSK      (0x00000380)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MAX      (0x00000007)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_DEF      (0x00000000)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_OFF               (10)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_WID               ( 3)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_MSK               (0x00001C00)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_MAX               (0x00000007)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_DEF               (0x00000000)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_OdtDelay_OFF                (13)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_OdtDelay_WID                ( 4)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_OdtDelay_MSK                (0x0001E000)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_OdtDelay_MAX                (0x0000000F)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_OdtDelay_DEF                (0x00000000)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_OdtDuration_OFF             (17)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_OdtDuration_WID             ( 3)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_OdtDuration_MSK             (0x000E0000)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_OdtDuration_MAX             (0x00000007)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_OdtDuration_DEF             (0x00000000)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_OFF           (20)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_WID           ( 4)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_MSK           (0x00F00000)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_MAX           (0x0000000F)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_DEF           (0x00000000)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_OFF        (24)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_WID        ( 3)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_MSK        (0x07000000)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_MAX        (0x00000007)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_DEF        (0x00000000)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_BurstEndODTDelay_OFF        (27)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_BurstEndODTDelay_WID        ( 3)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_BurstEndODTDelay_MSK        (0x38000000)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_BurstEndODTDelay_MAX        (0x00000007)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_BurstEndODTDelay_DEF        (0x00000000)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_OFF          (30)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_WID          ( 1)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_MSK          (0x40000000)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_MAX          (0x00000001)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_DEF          (0x00000000)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_Rsvd1_OFF                   (31)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_Rsvd1_WID                   ( 1)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_Rsvd1_MSK                   (0x80000000)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_Rsvd1_MAX                   (0x00000001)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_Rsvd1_DEF                   (0x00000000)
+
+#define DDRDATA5CH0_CR_DDRCRDATACONTROL2_REG                         (0x00000A64)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_OFF            ( 0)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_WID            ( 5)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_MSK            (0x0000001F)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_MAX            (0x0000001F)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_DEF            (0x00000000)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_OFF             ( 5)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_WID             ( 1)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_MSK             (0x00000020)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_MAX             (0x00000001)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_DEF             (0x00000000)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_ForceRxOn_OFF               ( 6)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_ForceRxOn_WID               ( 1)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_ForceRxOn_MSK               (0x00000040)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_ForceRxOn_MAX               (0x00000001)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_ForceRxOn_DEF               (0x00000000)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_LeakerComp_OFF              ( 7)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_LeakerComp_WID              ( 2)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_LeakerComp_MSK              (0x00000180)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_LeakerComp_MAX              (0x00000003)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_LeakerComp_DEF              (0x00000000)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_OFF          ( 9)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_WID          ( 4)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_MSK          (0x00001E00)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_MAX          (0x0000000F)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_DEF          (0x00000008)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_OFF             (13)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_WID             ( 5)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_MSK             (0x0003E000)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_MAX             (0x0000001F)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_DEF             (0x00000011)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_OFF             (18)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_WID             ( 1)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_MSK             (0x00040000)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_MAX             (0x00000001)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_DEF             (0x00000000)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_Spare_OFF                   (19)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_Spare_WID                   (13)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_Spare_MSK                   (0xFFF80000)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_Spare_MAX                   (0x00001FFF)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_Spare_DEF                   (0x00000000)
+
+#define DDRDATA5CH0_CR_DDRCRVSSHIORVREFCONTROL_REG                   (0x00000A6C)
+  #define DDRDATA5CH0_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_OFF    ( 0)
+  #define DDRDATA5CH0_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_WID    (24)
+  #define DDRDATA5CH0_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_MSK    (0x00FFFFFF)
+  #define DDRDATA5CH0_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_MAX    (0x00FFFFFF)
+  #define DDRDATA5CH0_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_DEF    (0x00000000)
+  #define DDRDATA5CH0_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_OFF        (24)
+  #define DDRDATA5CH0_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_WID        ( 8)
+  #define DDRDATA5CH0_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_MSK        (0xFF000000)
+  #define DDRDATA5CH0_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_MAX        (0x000000FF)
+  #define DDRDATA5CH0_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_DEF        (0x00000000)
+
+#define DDRDATA5CH0_CR_DDRCRDATAOFFSETTRAIN_REG                      (0x00000A70)
+  #define DDRDATA5CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_OFF          ( 0)
+  #define DDRDATA5CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_WID          ( 6)
+  #define DDRDATA5CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MSK          (0x0000003F)
+  #define DDRDATA5CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MAX          (0x0000003F)
+  #define DDRDATA5CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_DEF          (0x00000000)
+  #define DDRDATA5CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_OFF          ( 6)
+  #define DDRDATA5CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_WID          ( 6)
+  #define DDRDATA5CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MSK          (0x00000FC0)
+  #define DDRDATA5CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MAX          (0x0000003F)
+  #define DDRDATA5CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_DEF          (0x00000000)
+  #define DDRDATA5CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_OFF           (12)
+  #define DDRDATA5CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_WID           ( 6)
+  #define DDRDATA5CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MSK           (0x0003F000)
+  #define DDRDATA5CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MAX           (0x0000003F)
+  #define DDRDATA5CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_DEF           (0x00000000)
+  #define DDRDATA5CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_OFF          (18)
+  #define DDRDATA5CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_WID          ( 6)
+  #define DDRDATA5CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MSK          (0x00FC0000)
+  #define DDRDATA5CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MAX          (0x0000003F)
+  #define DDRDATA5CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_DEF          (0x00000000)
+  #define DDRDATA5CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_OFF           (24)
+  #define DDRDATA5CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_WID           ( 7)
+  #define DDRDATA5CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MSK           (0x7F000000)
+  #define DDRDATA5CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MAX           (0x0000007F)
+  #define DDRDATA5CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_DEF           (0x00000000)
+  #define DDRDATA5CH0_CR_DDRCRDATAOFFSETTRAIN_Spare_OFF                (31)
+  #define DDRDATA5CH0_CR_DDRCRDATAOFFSETTRAIN_Spare_WID                ( 1)
+  #define DDRDATA5CH0_CR_DDRCRDATAOFFSETTRAIN_Spare_MSK                (0x80000000)
+  #define DDRDATA5CH0_CR_DDRCRDATAOFFSETTRAIN_Spare_MAX                (0x00000001)
+  #define DDRDATA5CH0_CR_DDRCRDATAOFFSETTRAIN_Spare_DEF                (0x00000000)
+
+#define DDRDATA5CH0_CR_DDRCRDATACONTROL0_REG                         (0x00000A74)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_OFF          ( 0)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_WID          ( 1)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_MSK          (0x00000001)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_MAX          (0x00000001)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_DEF          (0x00000000)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_OFF          ( 1)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_WID          ( 1)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_MSK          (0x00000002)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_MAX          (0x00000001)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_DEF          (0x00000000)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_OFF          ( 2)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_WID          ( 1)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_MSK          (0x00000004)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_MAX          (0x00000001)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_DEF          (0x00000000)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_OFF    ( 3)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_WID    ( 1)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MSK    (0x00000008)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MAX    (0x00000001)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_DEF    (0x00000000)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_TxOn_OFF                    ( 4)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_TxOn_WID                    ( 1)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_TxOn_MSK                    (0x00000010)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_TxOn_MAX                    (0x00000001)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_TxOn_DEF                    (0x00000000)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RfOn_OFF                    ( 5)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RfOn_WID                    ( 1)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RfOn_MSK                    (0x00000020)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RfOn_MAX                    (0x00000001)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RfOn_DEF                    (0x00000000)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RxPiOn_OFF                  ( 6)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RxPiOn_WID                  ( 1)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RxPiOn_MSK                  (0x00000040)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RxPiOn_MAX                  (0x00000001)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RxPiOn_DEF                  (0x00000000)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_TxPiOn_OFF                  ( 7)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_TxPiOn_WID                  ( 1)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_TxPiOn_MSK                  (0x00000080)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_TxPiOn_MAX                  (0x00000001)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_TxPiOn_DEF                  (0x00000000)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_OFF        ( 8)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_WID        ( 1)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_MSK        (0x00000100)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_MAX        (0x00000001)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_DEF        (0x00000000)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_OFF        ( 9)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_WID        ( 1)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MSK        (0x00000200)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MAX        (0x00000001)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_DEF        (0x00000000)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_TxDisable_OFF               (10)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_TxDisable_WID               ( 1)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_TxDisable_MSK               (0x00000400)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_TxDisable_MAX               (0x00000001)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_TxDisable_DEF               (0x00000000)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RxDisable_OFF               (11)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RxDisable_WID               ( 1)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RxDisable_MSK               (0x00000800)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RxDisable_MAX               (0x00000001)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RxDisable_DEF               (0x00000000)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_TxLong_OFF                  (12)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_TxLong_WID                  ( 1)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_TxLong_MSK                  (0x00001000)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_TxLong_MAX                  (0x00000001)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_TxLong_DEF                  (0x00000000)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_OFF               (13)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_WID               ( 2)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_MSK               (0x00006000)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_MAX               (0x00000003)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_DEF               (0x00000000)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RxReadPointer_OFF           (15)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RxReadPointer_WID           ( 3)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RxReadPointer_MSK           (0x00038000)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RxReadPointer_MAX           (0x00000007)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RxReadPointer_DEF           (0x00000000)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_DriverSegmentEnable_OFF     (18)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_DriverSegmentEnable_WID     ( 1)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_DriverSegmentEnable_MSK     (0x00040000)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_DriverSegmentEnable_MAX     (0x00000001)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_DriverSegmentEnable_DEF     (0x00000000)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_DataVccddqHi_OFF            (19)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_DataVccddqHi_WID            ( 1)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_DataVccddqHi_MSK            (0x00080000)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_DataVccddqHi_MAX            (0x00000001)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_DataVccddqHi_DEF            (0x00000000)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_ReadRFRd_OFF                (20)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_ReadRFRd_WID                ( 1)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_ReadRFRd_MSK                (0x00100000)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_ReadRFRd_MAX                (0x00000001)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_ReadRFRd_DEF                (0x00000000)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_ReadRFWr_OFF                (21)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_ReadRFWr_WID                ( 1)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_ReadRFWr_MSK                (0x00200000)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_ReadRFWr_MAX                (0x00000001)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_ReadRFWr_DEF                (0x00000000)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_ReadRFRank_OFF              (22)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_ReadRFRank_WID              ( 2)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_ReadRFRank_MSK              (0x00C00000)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_ReadRFRank_MAX              (0x00000003)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_ReadRFRank_DEF              (0x00000000)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_OFF              (24)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_WID              ( 1)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_MSK              (0x01000000)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_MAX              (0x00000001)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_DEF              (0x00000000)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_OdtSampOff_OFF              (25)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_OdtSampOff_WID              ( 1)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_OdtSampOff_MSK              (0x02000000)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_OdtSampOff_MAX              (0x00000001)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_OdtSampOff_DEF              (0x00000000)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_OFF        (26)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_WID        ( 1)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_MSK        (0x04000000)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_MAX        (0x00000001)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_DEF        (0x00000000)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_OFF         (27)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_WID         ( 1)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MSK         (0x08000000)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MAX         (0x00000001)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_DEF         (0x00000000)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_OFF              (28)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_WID              ( 1)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_MSK              (0x10000000)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_MAX              (0x00000001)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_DEF              (0x00000000)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_EnReadPreamble_OFF          (29)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_EnReadPreamble_WID          ( 1)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_EnReadPreamble_MSK          (0x20000000)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_EnReadPreamble_MAX          (0x00000001)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_EnReadPreamble_DEF          (0x00000000)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_OFF         (30)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_WID         ( 1)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MSK         (0x40000000)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MAX         (0x00000001)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_DEF         (0x00000000)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_OFF            (31)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_WID            ( 1)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_MSK            (0x80000000)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_MAX            (0x00000001)
+  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_DEF            (0x00000000)
+
+#define DDRDATA5CH0_CR_DDRCRVREFADJUST1_REG                          (0x00000A78)
+  #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_CAVrefCtl_OFF                ( 0)
+  #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_CAVrefCtl_WID                ( 7)
+  #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_CAVrefCtl_MSK                (0x0000007F)
+  #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_CAVrefCtl_MAX                (0x0000007F)
+  #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_CAVrefCtl_DEF                (0x00000000)
+  #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_Ch1VrefCtl_OFF               ( 7)
+  #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_Ch1VrefCtl_WID               ( 7)
+  #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_Ch1VrefCtl_MSK               (0x00003F80)
+  #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_Ch1VrefCtl_MAX               (0x0000007F)
+  #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_Ch1VrefCtl_DEF               (0x00000000)
+  #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_Ch0VrefCtl_OFF               (14)
+  #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_Ch0VrefCtl_WID               ( 7)
+  #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_Ch0VrefCtl_MSK               (0x001FC000)
+  #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_Ch0VrefCtl_MAX               (0x0000007F)
+  #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_Ch0VrefCtl_DEF               (0x00000000)
+  #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCA_OFF             (21)
+  #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCA_WID             ( 1)
+  #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCA_MSK             (0x00200000)
+  #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCA_MAX             (0x00000001)
+  #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCA_DEF             (0x00000000)
+  #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_OFF            (22)
+  #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_WID            ( 1)
+  #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_MSK            (0x00400000)
+  #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_MAX            (0x00000001)
+  #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_DEF            (0x00000000)
+  #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_OFF            (23)
+  #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_WID            ( 1)
+  #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_MSK            (0x00800000)
+  #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_MAX            (0x00000001)
+  #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_DEF            (0x00000000)
+  #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_HiZTimerCtrl_OFF             (24)
+  #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_HiZTimerCtrl_WID             ( 2)
+  #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_HiZTimerCtrl_MSK             (0x03000000)
+  #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_HiZTimerCtrl_MAX             (0x00000003)
+  #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_HiZTimerCtrl_DEF             (0x00000000)
+  #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_OFF            (26)
+  #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_WID            ( 1)
+  #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_MSK            (0x04000000)
+  #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_MAX            (0x00000001)
+  #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_DEF            (0x00000000)
+  #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_Rsvd_OFF                     (27)
+  #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_Rsvd_WID                     ( 2)
+  #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_Rsvd_MSK                     (0x18000000)
+  #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_Rsvd_MAX                     (0x00000003)
+  #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_Rsvd_DEF                     (0x00000000)
+  #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_caSlowBW_OFF                 (29)
+  #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_caSlowBW_WID                 ( 1)
+  #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_caSlowBW_MSK                 (0x20000000)
+  #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_caSlowBW_MAX                 (0x00000001)
+  #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_caSlowBW_DEF                 (0x00000000)
+  #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_ch0SlowBW_OFF                (30)
+  #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_ch0SlowBW_WID                ( 1)
+  #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_ch0SlowBW_MSK                (0x40000000)
+  #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_ch0SlowBW_MAX                (0x00000001)
+  #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_ch0SlowBW_DEF                (0x00000000)
+  #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_ch1SlowBW_OFF                (31)
+  #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_ch1SlowBW_WID                ( 1)
+  #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_ch1SlowBW_MSK                (0x80000000)
+  #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_ch1SlowBW_MAX                (0x00000001)
+  #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_ch1SlowBW_DEF                (0x00000000)
+
+#define DDRDATA5CH1_CR_RXTRAINRANK0_REG                              (0x00000B00)
+  #define DDRDATA5CH1_CR_RXTRAINRANK0_RxRcvEnPi_OFF                    ( 0)
+  #define DDRDATA5CH1_CR_RXTRAINRANK0_RxRcvEnPi_WID                    ( 9)
+  #define DDRDATA5CH1_CR_RXTRAINRANK0_RxRcvEnPi_MSK                    (0x000001FF)
+  #define DDRDATA5CH1_CR_RXTRAINRANK0_RxRcvEnPi_MAX                    (0x000001FF)
+  #define DDRDATA5CH1_CR_RXTRAINRANK0_RxDqsPPi_OFF                     ( 9)
+  #define DDRDATA5CH1_CR_RXTRAINRANK0_RxDqsPPi_WID                     ( 6)
+  #define DDRDATA5CH1_CR_RXTRAINRANK0_RxDqsPPi_MSK                     (0x00007E00)
+  #define DDRDATA5CH1_CR_RXTRAINRANK0_RxDqsPPi_MAX                     (0x0000003F)
+  #define DDRDATA5CH1_CR_RXTRAINRANK0_RxEq_OFF                         (15)
+  #define DDRDATA5CH1_CR_RXTRAINRANK0_RxEq_WID                         ( 5)
+  #define DDRDATA5CH1_CR_RXTRAINRANK0_RxEq_MSK                         (0x000F8000)
+  #define DDRDATA5CH1_CR_RXTRAINRANK0_RxEq_MAX                         (0x0000001F)
+  #define DDRDATA5CH1_CR_RXTRAINRANK0_RxDqsNPi_OFF                     (20)
+  #define DDRDATA5CH1_CR_RXTRAINRANK0_RxDqsNPi_WID                     ( 6)
+  #define DDRDATA5CH1_CR_RXTRAINRANK0_RxDqsNPi_MSK                     (0x03F00000)
+  #define DDRDATA5CH1_CR_RXTRAINRANK0_RxDqsNPi_MAX                     (0x0000003F)
+  #define DDRDATA5CH1_CR_RXTRAINRANK0_RxVref_OFF                       (26)
+  #define DDRDATA5CH1_CR_RXTRAINRANK0_RxVref_WID                       ( 6)
+  #define DDRDATA5CH1_CR_RXTRAINRANK0_RxVref_MSK                       (0xFC000000)
+  #define DDRDATA5CH1_CR_RXTRAINRANK0_RxVref_MAX                       (0x0000003F)
+
+#define DDRDATA5CH1_CR_RXTRAINRANK1_REG                              (0x00000B04)
+  #define DDRDATA5CH1_CR_RXTRAINRANK1_RxRcvEnPi_OFF                    ( 0)
+  #define DDRDATA5CH1_CR_RXTRAINRANK1_RxRcvEnPi_WID                    ( 9)
+  #define DDRDATA5CH1_CR_RXTRAINRANK1_RxRcvEnPi_MSK                    (0x000001FF)
+  #define DDRDATA5CH1_CR_RXTRAINRANK1_RxRcvEnPi_MAX                    (0x000001FF)
+  #define DDRDATA5CH1_CR_RXTRAINRANK1_RxDqsPPi_OFF                     ( 9)
+  #define DDRDATA5CH1_CR_RXTRAINRANK1_RxDqsPPi_WID                     ( 6)
+  #define DDRDATA5CH1_CR_RXTRAINRANK1_RxDqsPPi_MSK                     (0x00007E00)
+  #define DDRDATA5CH1_CR_RXTRAINRANK1_RxDqsPPi_MAX                     (0x0000003F)
+  #define DDRDATA5CH1_CR_RXTRAINRANK1_RxEq_OFF                         (15)
+  #define DDRDATA5CH1_CR_RXTRAINRANK1_RxEq_WID                         ( 5)
+  #define DDRDATA5CH1_CR_RXTRAINRANK1_RxEq_MSK                         (0x000F8000)
+  #define DDRDATA5CH1_CR_RXTRAINRANK1_RxEq_MAX                         (0x0000001F)
+  #define DDRDATA5CH1_CR_RXTRAINRANK1_RxDqsNPi_OFF                     (20)
+  #define DDRDATA5CH1_CR_RXTRAINRANK1_RxDqsNPi_WID                     ( 6)
+  #define DDRDATA5CH1_CR_RXTRAINRANK1_RxDqsNPi_MSK                     (0x03F00000)
+  #define DDRDATA5CH1_CR_RXTRAINRANK1_RxDqsNPi_MAX                     (0x0000003F)
+  #define DDRDATA5CH1_CR_RXTRAINRANK1_RxVref_OFF                       (26)
+  #define DDRDATA5CH1_CR_RXTRAINRANK1_RxVref_WID                       ( 6)
+  #define DDRDATA5CH1_CR_RXTRAINRANK1_RxVref_MSK                       (0xFC000000)
+  #define DDRDATA5CH1_CR_RXTRAINRANK1_RxVref_MAX                       (0x0000003F)
+
+#define DDRDATA5CH1_CR_RXTRAINRANK2_REG                              (0x00000B08)
+  #define DDRDATA5CH1_CR_RXTRAINRANK2_RxRcvEnPi_OFF                    ( 0)
+  #define DDRDATA5CH1_CR_RXTRAINRANK2_RxRcvEnPi_WID                    ( 9)
+  #define DDRDATA5CH1_CR_RXTRAINRANK2_RxRcvEnPi_MSK                    (0x000001FF)
+  #define DDRDATA5CH1_CR_RXTRAINRANK2_RxRcvEnPi_MAX                    (0x000001FF)
+  #define DDRDATA5CH1_CR_RXTRAINRANK2_RxDqsPPi_OFF                     ( 9)
+  #define DDRDATA5CH1_CR_RXTRAINRANK2_RxDqsPPi_WID                     ( 6)
+  #define DDRDATA5CH1_CR_RXTRAINRANK2_RxDqsPPi_MSK                     (0x00007E00)
+  #define DDRDATA5CH1_CR_RXTRAINRANK2_RxDqsPPi_MAX                     (0x0000003F)
+  #define DDRDATA5CH1_CR_RXTRAINRANK2_RxEq_OFF                         (15)
+  #define DDRDATA5CH1_CR_RXTRAINRANK2_RxEq_WID                         ( 5)
+  #define DDRDATA5CH1_CR_RXTRAINRANK2_RxEq_MSK                         (0x000F8000)
+  #define DDRDATA5CH1_CR_RXTRAINRANK2_RxEq_MAX                         (0x0000001F)
+  #define DDRDATA5CH1_CR_RXTRAINRANK2_RxDqsNPi_OFF                     (20)
+  #define DDRDATA5CH1_CR_RXTRAINRANK2_RxDqsNPi_WID                     ( 6)
+  #define DDRDATA5CH1_CR_RXTRAINRANK2_RxDqsNPi_MSK                     (0x03F00000)
+  #define DDRDATA5CH1_CR_RXTRAINRANK2_RxDqsNPi_MAX                     (0x0000003F)
+  #define DDRDATA5CH1_CR_RXTRAINRANK2_RxVref_OFF                       (26)
+  #define DDRDATA5CH1_CR_RXTRAINRANK2_RxVref_WID                       ( 6)
+  #define DDRDATA5CH1_CR_RXTRAINRANK2_RxVref_MSK                       (0xFC000000)
+  #define DDRDATA5CH1_CR_RXTRAINRANK2_RxVref_MAX                       (0x0000003F)
+
+#define DDRDATA5CH1_CR_RXTRAINRANK3_REG                              (0x00000B0C)
+  #define DDRDATA5CH1_CR_RXTRAINRANK3_RxRcvEnPi_OFF                    ( 0)
+  #define DDRDATA5CH1_CR_RXTRAINRANK3_RxRcvEnPi_WID                    ( 9)
+  #define DDRDATA5CH1_CR_RXTRAINRANK3_RxRcvEnPi_MSK                    (0x000001FF)
+  #define DDRDATA5CH1_CR_RXTRAINRANK3_RxRcvEnPi_MAX                    (0x000001FF)
+  #define DDRDATA5CH1_CR_RXTRAINRANK3_RxDqsPPi_OFF                     ( 9)
+  #define DDRDATA5CH1_CR_RXTRAINRANK3_RxDqsPPi_WID                     ( 6)
+  #define DDRDATA5CH1_CR_RXTRAINRANK3_RxDqsPPi_MSK                     (0x00007E00)
+  #define DDRDATA5CH1_CR_RXTRAINRANK3_RxDqsPPi_MAX                     (0x0000003F)
+  #define DDRDATA5CH1_CR_RXTRAINRANK3_RxEq_OFF                         (15)
+  #define DDRDATA5CH1_CR_RXTRAINRANK3_RxEq_WID                         ( 5)
+  #define DDRDATA5CH1_CR_RXTRAINRANK3_RxEq_MSK                         (0x000F8000)
+  #define DDRDATA5CH1_CR_RXTRAINRANK3_RxEq_MAX                         (0x0000001F)
+  #define DDRDATA5CH1_CR_RXTRAINRANK3_RxDqsNPi_OFF                     (20)
+  #define DDRDATA5CH1_CR_RXTRAINRANK3_RxDqsNPi_WID                     ( 6)
+  #define DDRDATA5CH1_CR_RXTRAINRANK3_RxDqsNPi_MSK                     (0x03F00000)
+  #define DDRDATA5CH1_CR_RXTRAINRANK3_RxDqsNPi_MAX                     (0x0000003F)
+  #define DDRDATA5CH1_CR_RXTRAINRANK3_RxVref_OFF                       (26)
+  #define DDRDATA5CH1_CR_RXTRAINRANK3_RxVref_WID                       ( 6)
+  #define DDRDATA5CH1_CR_RXTRAINRANK3_RxVref_MSK                       (0xFC000000)
+  #define DDRDATA5CH1_CR_RXTRAINRANK3_RxVref_MAX                       (0x0000003F)
+
+#define DDRDATA5CH1_CR_RXPERBITRANK0_REG                             (0x00000B10)
+  #define DDRDATA5CH1_CR_RXPERBITRANK0_Lane0_OFF                       ( 0)
+  #define DDRDATA5CH1_CR_RXPERBITRANK0_Lane0_WID                       ( 4)
+  #define DDRDATA5CH1_CR_RXPERBITRANK0_Lane0_MSK                       (0x0000000F)
+  #define DDRDATA5CH1_CR_RXPERBITRANK0_Lane0_MAX                       (0x0000000F)
+  #define DDRDATA5CH1_CR_RXPERBITRANK0_Lane1_OFF                       ( 4)
+  #define DDRDATA5CH1_CR_RXPERBITRANK0_Lane1_WID                       ( 4)
+  #define DDRDATA5CH1_CR_RXPERBITRANK0_Lane1_MSK                       (0x000000F0)
+  #define DDRDATA5CH1_CR_RXPERBITRANK0_Lane1_MAX                       (0x0000000F)
+  #define DDRDATA5CH1_CR_RXPERBITRANK0_Lane2_OFF                       ( 8)
+  #define DDRDATA5CH1_CR_RXPERBITRANK0_Lane2_WID                       ( 4)
+  #define DDRDATA5CH1_CR_RXPERBITRANK0_Lane2_MSK                       (0x00000F00)
+  #define DDRDATA5CH1_CR_RXPERBITRANK0_Lane2_MAX                       (0x0000000F)
+  #define DDRDATA5CH1_CR_RXPERBITRANK0_Lane3_OFF                       (12)
+  #define DDRDATA5CH1_CR_RXPERBITRANK0_Lane3_WID                       ( 4)
+  #define DDRDATA5CH1_CR_RXPERBITRANK0_Lane3_MSK                       (0x0000F000)
+  #define DDRDATA5CH1_CR_RXPERBITRANK0_Lane3_MAX                       (0x0000000F)
+  #define DDRDATA5CH1_CR_RXPERBITRANK0_Lane4_OFF                       (16)
+  #define DDRDATA5CH1_CR_RXPERBITRANK0_Lane4_WID                       ( 4)
+  #define DDRDATA5CH1_CR_RXPERBITRANK0_Lane4_MSK                       (0x000F0000)
+  #define DDRDATA5CH1_CR_RXPERBITRANK0_Lane4_MAX                       (0x0000000F)
+  #define DDRDATA5CH1_CR_RXPERBITRANK0_Lane5_OFF                       (20)
+  #define DDRDATA5CH1_CR_RXPERBITRANK0_Lane5_WID                       ( 4)
+  #define DDRDATA5CH1_CR_RXPERBITRANK0_Lane5_MSK                       (0x00F00000)
+  #define DDRDATA5CH1_CR_RXPERBITRANK0_Lane5_MAX                       (0x0000000F)
+  #define DDRDATA5CH1_CR_RXPERBITRANK0_Lane6_OFF                       (24)
+  #define DDRDATA5CH1_CR_RXPERBITRANK0_Lane6_WID                       ( 4)
+  #define DDRDATA5CH1_CR_RXPERBITRANK0_Lane6_MSK                       (0x0F000000)
+  #define DDRDATA5CH1_CR_RXPERBITRANK0_Lane6_MAX                       (0x0000000F)
+  #define DDRDATA5CH1_CR_RXPERBITRANK0_Lane7_OFF                       (28)
+  #define DDRDATA5CH1_CR_RXPERBITRANK0_Lane7_WID                       ( 4)
+  #define DDRDATA5CH1_CR_RXPERBITRANK0_Lane7_MSK                       (0xF0000000)
+  #define DDRDATA5CH1_CR_RXPERBITRANK0_Lane7_MAX                       (0x0000000F)
+
+#define DDRDATA5CH1_CR_RXPERBITRANK1_REG                             (0x00000B14)
+  #define DDRDATA5CH1_CR_RXPERBITRANK1_Lane0_OFF                       ( 0)
+  #define DDRDATA5CH1_CR_RXPERBITRANK1_Lane0_WID                       ( 4)
+  #define DDRDATA5CH1_CR_RXPERBITRANK1_Lane0_MSK                       (0x0000000F)
+  #define DDRDATA5CH1_CR_RXPERBITRANK1_Lane0_MAX                       (0x0000000F)
+  #define DDRDATA5CH1_CR_RXPERBITRANK1_Lane1_OFF                       ( 4)
+  #define DDRDATA5CH1_CR_RXPERBITRANK1_Lane1_WID                       ( 4)
+  #define DDRDATA5CH1_CR_RXPERBITRANK1_Lane1_MSK                       (0x000000F0)
+  #define DDRDATA5CH1_CR_RXPERBITRANK1_Lane1_MAX                       (0x0000000F)
+  #define DDRDATA5CH1_CR_RXPERBITRANK1_Lane2_OFF                       ( 8)
+  #define DDRDATA5CH1_CR_RXPERBITRANK1_Lane2_WID                       ( 4)
+  #define DDRDATA5CH1_CR_RXPERBITRANK1_Lane2_MSK                       (0x00000F00)
+  #define DDRDATA5CH1_CR_RXPERBITRANK1_Lane2_MAX                       (0x0000000F)
+  #define DDRDATA5CH1_CR_RXPERBITRANK1_Lane3_OFF                       (12)
+  #define DDRDATA5CH1_CR_RXPERBITRANK1_Lane3_WID                       ( 4)
+  #define DDRDATA5CH1_CR_RXPERBITRANK1_Lane3_MSK                       (0x0000F000)
+  #define DDRDATA5CH1_CR_RXPERBITRANK1_Lane3_MAX                       (0x0000000F)
+  #define DDRDATA5CH1_CR_RXPERBITRANK1_Lane4_OFF                       (16)
+  #define DDRDATA5CH1_CR_RXPERBITRANK1_Lane4_WID                       ( 4)
+  #define DDRDATA5CH1_CR_RXPERBITRANK1_Lane4_MSK                       (0x000F0000)
+  #define DDRDATA5CH1_CR_RXPERBITRANK1_Lane4_MAX                       (0x0000000F)
+  #define DDRDATA5CH1_CR_RXPERBITRANK1_Lane5_OFF                       (20)
+  #define DDRDATA5CH1_CR_RXPERBITRANK1_Lane5_WID                       ( 4)
+  #define DDRDATA5CH1_CR_RXPERBITRANK1_Lane5_MSK                       (0x00F00000)
+  #define DDRDATA5CH1_CR_RXPERBITRANK1_Lane5_MAX                       (0x0000000F)
+  #define DDRDATA5CH1_CR_RXPERBITRANK1_Lane6_OFF                       (24)
+  #define DDRDATA5CH1_CR_RXPERBITRANK1_Lane6_WID                       ( 4)
+  #define DDRDATA5CH1_CR_RXPERBITRANK1_Lane6_MSK                       (0x0F000000)
+  #define DDRDATA5CH1_CR_RXPERBITRANK1_Lane6_MAX                       (0x0000000F)
+  #define DDRDATA5CH1_CR_RXPERBITRANK1_Lane7_OFF                       (28)
+  #define DDRDATA5CH1_CR_RXPERBITRANK1_Lane7_WID                       ( 4)
+  #define DDRDATA5CH1_CR_RXPERBITRANK1_Lane7_MSK                       (0xF0000000)
+  #define DDRDATA5CH1_CR_RXPERBITRANK1_Lane7_MAX                       (0x0000000F)
+
+#define DDRDATA5CH1_CR_RXPERBITRANK2_REG                             (0x00000B18)
+  #define DDRDATA5CH1_CR_RXPERBITRANK2_Lane0_OFF                       ( 0)
+  #define DDRDATA5CH1_CR_RXPERBITRANK2_Lane0_WID                       ( 4)
+  #define DDRDATA5CH1_CR_RXPERBITRANK2_Lane0_MSK                       (0x0000000F)
+  #define DDRDATA5CH1_CR_RXPERBITRANK2_Lane0_MAX                       (0x0000000F)
+  #define DDRDATA5CH1_CR_RXPERBITRANK2_Lane1_OFF                       ( 4)
+  #define DDRDATA5CH1_CR_RXPERBITRANK2_Lane1_WID                       ( 4)
+  #define DDRDATA5CH1_CR_RXPERBITRANK2_Lane1_MSK                       (0x000000F0)
+  #define DDRDATA5CH1_CR_RXPERBITRANK2_Lane1_MAX                       (0x0000000F)
+  #define DDRDATA5CH1_CR_RXPERBITRANK2_Lane2_OFF                       ( 8)
+  #define DDRDATA5CH1_CR_RXPERBITRANK2_Lane2_WID                       ( 4)
+  #define DDRDATA5CH1_CR_RXPERBITRANK2_Lane2_MSK                       (0x00000F00)
+  #define DDRDATA5CH1_CR_RXPERBITRANK2_Lane2_MAX                       (0x0000000F)
+  #define DDRDATA5CH1_CR_RXPERBITRANK2_Lane3_OFF                       (12)
+  #define DDRDATA5CH1_CR_RXPERBITRANK2_Lane3_WID                       ( 4)
+  #define DDRDATA5CH1_CR_RXPERBITRANK2_Lane3_MSK                       (0x0000F000)
+  #define DDRDATA5CH1_CR_RXPERBITRANK2_Lane3_MAX                       (0x0000000F)
+  #define DDRDATA5CH1_CR_RXPERBITRANK2_Lane4_OFF                       (16)
+  #define DDRDATA5CH1_CR_RXPERBITRANK2_Lane4_WID                       ( 4)
+  #define DDRDATA5CH1_CR_RXPERBITRANK2_Lane4_MSK                       (0x000F0000)
+  #define DDRDATA5CH1_CR_RXPERBITRANK2_Lane4_MAX                       (0x0000000F)
+  #define DDRDATA5CH1_CR_RXPERBITRANK2_Lane5_OFF                       (20)
+  #define DDRDATA5CH1_CR_RXPERBITRANK2_Lane5_WID                       ( 4)
+  #define DDRDATA5CH1_CR_RXPERBITRANK2_Lane5_MSK                       (0x00F00000)
+  #define DDRDATA5CH1_CR_RXPERBITRANK2_Lane5_MAX                       (0x0000000F)
+  #define DDRDATA5CH1_CR_RXPERBITRANK2_Lane6_OFF                       (24)
+  #define DDRDATA5CH1_CR_RXPERBITRANK2_Lane6_WID                       ( 4)
+  #define DDRDATA5CH1_CR_RXPERBITRANK2_Lane6_MSK                       (0x0F000000)
+  #define DDRDATA5CH1_CR_RXPERBITRANK2_Lane6_MAX                       (0x0000000F)
+  #define DDRDATA5CH1_CR_RXPERBITRANK2_Lane7_OFF                       (28)
+  #define DDRDATA5CH1_CR_RXPERBITRANK2_Lane7_WID                       ( 4)
+  #define DDRDATA5CH1_CR_RXPERBITRANK2_Lane7_MSK                       (0xF0000000)
+  #define DDRDATA5CH1_CR_RXPERBITRANK2_Lane7_MAX                       (0x0000000F)
+
+#define DDRDATA5CH1_CR_RXPERBITRANK3_REG                             (0x00000B1C)
+  #define DDRDATA5CH1_CR_RXPERBITRANK3_Lane0_OFF                       ( 0)
+  #define DDRDATA5CH1_CR_RXPERBITRANK3_Lane0_WID                       ( 4)
+  #define DDRDATA5CH1_CR_RXPERBITRANK3_Lane0_MSK                       (0x0000000F)
+  #define DDRDATA5CH1_CR_RXPERBITRANK3_Lane0_MAX                       (0x0000000F)
+  #define DDRDATA5CH1_CR_RXPERBITRANK3_Lane1_OFF                       ( 4)
+  #define DDRDATA5CH1_CR_RXPERBITRANK3_Lane1_WID                       ( 4)
+  #define DDRDATA5CH1_CR_RXPERBITRANK3_Lane1_MSK                       (0x000000F0)
+  #define DDRDATA5CH1_CR_RXPERBITRANK3_Lane1_MAX                       (0x0000000F)
+  #define DDRDATA5CH1_CR_RXPERBITRANK3_Lane2_OFF                       ( 8)
+  #define DDRDATA5CH1_CR_RXPERBITRANK3_Lane2_WID                       ( 4)
+  #define DDRDATA5CH1_CR_RXPERBITRANK3_Lane2_MSK                       (0x00000F00)
+  #define DDRDATA5CH1_CR_RXPERBITRANK3_Lane2_MAX                       (0x0000000F)
+  #define DDRDATA5CH1_CR_RXPERBITRANK3_Lane3_OFF                       (12)
+  #define DDRDATA5CH1_CR_RXPERBITRANK3_Lane3_WID                       ( 4)
+  #define DDRDATA5CH1_CR_RXPERBITRANK3_Lane3_MSK                       (0x0000F000)
+  #define DDRDATA5CH1_CR_RXPERBITRANK3_Lane3_MAX                       (0x0000000F)
+  #define DDRDATA5CH1_CR_RXPERBITRANK3_Lane4_OFF                       (16)
+  #define DDRDATA5CH1_CR_RXPERBITRANK3_Lane4_WID                       ( 4)
+  #define DDRDATA5CH1_CR_RXPERBITRANK3_Lane4_MSK                       (0x000F0000)
+  #define DDRDATA5CH1_CR_RXPERBITRANK3_Lane4_MAX                       (0x0000000F)
+  #define DDRDATA5CH1_CR_RXPERBITRANK3_Lane5_OFF                       (20)
+  #define DDRDATA5CH1_CR_RXPERBITRANK3_Lane5_WID                       ( 4)
+  #define DDRDATA5CH1_CR_RXPERBITRANK3_Lane5_MSK                       (0x00F00000)
+  #define DDRDATA5CH1_CR_RXPERBITRANK3_Lane5_MAX                       (0x0000000F)
+  #define DDRDATA5CH1_CR_RXPERBITRANK3_Lane6_OFF                       (24)
+  #define DDRDATA5CH1_CR_RXPERBITRANK3_Lane6_WID                       ( 4)
+  #define DDRDATA5CH1_CR_RXPERBITRANK3_Lane6_MSK                       (0x0F000000)
+  #define DDRDATA5CH1_CR_RXPERBITRANK3_Lane6_MAX                       (0x0000000F)
+  #define DDRDATA5CH1_CR_RXPERBITRANK3_Lane7_OFF                       (28)
+  #define DDRDATA5CH1_CR_RXPERBITRANK3_Lane7_WID                       ( 4)
+  #define DDRDATA5CH1_CR_RXPERBITRANK3_Lane7_MSK                       (0xF0000000)
+  #define DDRDATA5CH1_CR_RXPERBITRANK3_Lane7_MAX                       (0x0000000F)
+
+#define DDRDATA5CH1_CR_TXTRAINRANK0_REG                              (0x00000B20)
+  #define DDRDATA5CH1_CR_TXTRAINRANK0_TxDqDelay_OFF                    ( 0)
+  #define DDRDATA5CH1_CR_TXTRAINRANK0_TxDqDelay_WID                    ( 9)
+  #define DDRDATA5CH1_CR_TXTRAINRANK0_TxDqDelay_MSK                    (0x000001FF)
+  #define DDRDATA5CH1_CR_TXTRAINRANK0_TxDqDelay_MAX                    (0x000001FF)
+  #define DDRDATA5CH1_CR_TXTRAINRANK0_TxDqsDelay_OFF                   ( 9)
+  #define DDRDATA5CH1_CR_TXTRAINRANK0_TxDqsDelay_WID                   ( 9)
+  #define DDRDATA5CH1_CR_TXTRAINRANK0_TxDqsDelay_MSK                   (0x0003FE00)
+  #define DDRDATA5CH1_CR_TXTRAINRANK0_TxDqsDelay_MAX                   (0x000001FF)
+  #define DDRDATA5CH1_CR_TXTRAINRANK0_Spare0_OFF                       (18)
+  #define DDRDATA5CH1_CR_TXTRAINRANK0_Spare0_WID                       ( 2)
+  #define DDRDATA5CH1_CR_TXTRAINRANK0_Spare0_MSK                       (0x000C0000)
+  #define DDRDATA5CH1_CR_TXTRAINRANK0_Spare0_MAX                       (0x00000003)
+  #define DDRDATA5CH1_CR_TXTRAINRANK0_TxEqualization_OFF               (20)
+  #define DDRDATA5CH1_CR_TXTRAINRANK0_TxEqualization_WID               ( 6)
+  #define DDRDATA5CH1_CR_TXTRAINRANK0_TxEqualization_MSK               (0x03F00000)
+  #define DDRDATA5CH1_CR_TXTRAINRANK0_TxEqualization_MAX               (0x0000003F)
+  #define DDRDATA5CH1_CR_TXTRAINRANK0_Spare1_OFF                       (26)
+  #define DDRDATA5CH1_CR_TXTRAINRANK0_Spare1_WID                       ( 6)
+  #define DDRDATA5CH1_CR_TXTRAINRANK0_Spare1_MSK                       (0xFC000000)
+  #define DDRDATA5CH1_CR_TXTRAINRANK0_Spare1_MAX                       (0x0000003F)
+
+#define DDRDATA5CH1_CR_TXTRAINRANK1_REG                              (0x00000B24)
+  #define DDRDATA5CH1_CR_TXTRAINRANK1_TxDqDelay_OFF                    ( 0)
+  #define DDRDATA5CH1_CR_TXTRAINRANK1_TxDqDelay_WID                    ( 9)
+  #define DDRDATA5CH1_CR_TXTRAINRANK1_TxDqDelay_MSK                    (0x000001FF)
+  #define DDRDATA5CH1_CR_TXTRAINRANK1_TxDqDelay_MAX                    (0x000001FF)
+  #define DDRDATA5CH1_CR_TXTRAINRANK1_TxDqsDelay_OFF                   ( 9)
+  #define DDRDATA5CH1_CR_TXTRAINRANK1_TxDqsDelay_WID                   ( 9)
+  #define DDRDATA5CH1_CR_TXTRAINRANK1_TxDqsDelay_MSK                   (0x0003FE00)
+  #define DDRDATA5CH1_CR_TXTRAINRANK1_TxDqsDelay_MAX                   (0x000001FF)
+  #define DDRDATA5CH1_CR_TXTRAINRANK1_Spare0_OFF                       (18)
+  #define DDRDATA5CH1_CR_TXTRAINRANK1_Spare0_WID                       ( 2)
+  #define DDRDATA5CH1_CR_TXTRAINRANK1_Spare0_MSK                       (0x000C0000)
+  #define DDRDATA5CH1_CR_TXTRAINRANK1_Spare0_MAX                       (0x00000003)
+  #define DDRDATA5CH1_CR_TXTRAINRANK1_TxEqualization_OFF               (20)
+  #define DDRDATA5CH1_CR_TXTRAINRANK1_TxEqualization_WID               ( 6)
+  #define DDRDATA5CH1_CR_TXTRAINRANK1_TxEqualization_MSK               (0x03F00000)
+  #define DDRDATA5CH1_CR_TXTRAINRANK1_TxEqualization_MAX               (0x0000003F)
+  #define DDRDATA5CH1_CR_TXTRAINRANK1_Spare1_OFF                       (26)
+  #define DDRDATA5CH1_CR_TXTRAINRANK1_Spare1_WID                       ( 6)
+  #define DDRDATA5CH1_CR_TXTRAINRANK1_Spare1_MSK                       (0xFC000000)
+  #define DDRDATA5CH1_CR_TXTRAINRANK1_Spare1_MAX                       (0x0000003F)
+
+#define DDRDATA5CH1_CR_TXTRAINRANK2_REG                              (0x00000B28)
+  #define DDRDATA5CH1_CR_TXTRAINRANK2_TxDqDelay_OFF                    ( 0)
+  #define DDRDATA5CH1_CR_TXTRAINRANK2_TxDqDelay_WID                    ( 9)
+  #define DDRDATA5CH1_CR_TXTRAINRANK2_TxDqDelay_MSK                    (0x000001FF)
+  #define DDRDATA5CH1_CR_TXTRAINRANK2_TxDqDelay_MAX                    (0x000001FF)
+  #define DDRDATA5CH1_CR_TXTRAINRANK2_TxDqsDelay_OFF                   ( 9)
+  #define DDRDATA5CH1_CR_TXTRAINRANK2_TxDqsDelay_WID                   ( 9)
+  #define DDRDATA5CH1_CR_TXTRAINRANK2_TxDqsDelay_MSK                   (0x0003FE00)
+  #define DDRDATA5CH1_CR_TXTRAINRANK2_TxDqsDelay_MAX                   (0x000001FF)
+  #define DDRDATA5CH1_CR_TXTRAINRANK2_Spare0_OFF                       (18)
+  #define DDRDATA5CH1_CR_TXTRAINRANK2_Spare0_WID                       ( 2)
+  #define DDRDATA5CH1_CR_TXTRAINRANK2_Spare0_MSK                       (0x000C0000)
+  #define DDRDATA5CH1_CR_TXTRAINRANK2_Spare0_MAX                       (0x00000003)
+  #define DDRDATA5CH1_CR_TXTRAINRANK2_TxEqualization_OFF               (20)
+  #define DDRDATA5CH1_CR_TXTRAINRANK2_TxEqualization_WID               ( 6)
+  #define DDRDATA5CH1_CR_TXTRAINRANK2_TxEqualization_MSK               (0x03F00000)
+  #define DDRDATA5CH1_CR_TXTRAINRANK2_TxEqualization_MAX               (0x0000003F)
+  #define DDRDATA5CH1_CR_TXTRAINRANK2_Spare1_OFF                       (26)
+  #define DDRDATA5CH1_CR_TXTRAINRANK2_Spare1_WID                       ( 6)
+  #define DDRDATA5CH1_CR_TXTRAINRANK2_Spare1_MSK                       (0xFC000000)
+  #define DDRDATA5CH1_CR_TXTRAINRANK2_Spare1_MAX                       (0x0000003F)
+
+#define DDRDATA5CH1_CR_TXTRAINRANK3_REG                              (0x00000B2C)
+  #define DDRDATA5CH1_CR_TXTRAINRANK3_TxDqDelay_OFF                    ( 0)
+  #define DDRDATA5CH1_CR_TXTRAINRANK3_TxDqDelay_WID                    ( 9)
+  #define DDRDATA5CH1_CR_TXTRAINRANK3_TxDqDelay_MSK                    (0x000001FF)
+  #define DDRDATA5CH1_CR_TXTRAINRANK3_TxDqDelay_MAX                    (0x000001FF)
+  #define DDRDATA5CH1_CR_TXTRAINRANK3_TxDqsDelay_OFF                   ( 9)
+  #define DDRDATA5CH1_CR_TXTRAINRANK3_TxDqsDelay_WID                   ( 9)
+  #define DDRDATA5CH1_CR_TXTRAINRANK3_TxDqsDelay_MSK                   (0x0003FE00)
+  #define DDRDATA5CH1_CR_TXTRAINRANK3_TxDqsDelay_MAX                   (0x000001FF)
+  #define DDRDATA5CH1_CR_TXTRAINRANK3_Spare0_OFF                       (18)
+  #define DDRDATA5CH1_CR_TXTRAINRANK3_Spare0_WID                       ( 2)
+  #define DDRDATA5CH1_CR_TXTRAINRANK3_Spare0_MSK                       (0x000C0000)
+  #define DDRDATA5CH1_CR_TXTRAINRANK3_Spare0_MAX                       (0x00000003)
+  #define DDRDATA5CH1_CR_TXTRAINRANK3_TxEqualization_OFF               (20)
+  #define DDRDATA5CH1_CR_TXTRAINRANK3_TxEqualization_WID               ( 6)
+  #define DDRDATA5CH1_CR_TXTRAINRANK3_TxEqualization_MSK               (0x03F00000)
+  #define DDRDATA5CH1_CR_TXTRAINRANK3_TxEqualization_MAX               (0x0000003F)
+  #define DDRDATA5CH1_CR_TXTRAINRANK3_Spare1_OFF                       (26)
+  #define DDRDATA5CH1_CR_TXTRAINRANK3_Spare1_WID                       ( 6)
+  #define DDRDATA5CH1_CR_TXTRAINRANK3_Spare1_MSK                       (0xFC000000)
+  #define DDRDATA5CH1_CR_TXTRAINRANK3_Spare1_MAX                       (0x0000003F)
+
+#define DDRDATA5CH1_CR_TXPERBITRANK0_REG                             (0x00000B30)
+  #define DDRDATA5CH1_CR_TXPERBITRANK0_Lane0_OFF                       ( 0)
+  #define DDRDATA5CH1_CR_TXPERBITRANK0_Lane0_WID                       ( 4)
+  #define DDRDATA5CH1_CR_TXPERBITRANK0_Lane0_MSK                       (0x0000000F)
+  #define DDRDATA5CH1_CR_TXPERBITRANK0_Lane0_MAX                       (0x0000000F)
+  #define DDRDATA5CH1_CR_TXPERBITRANK0_Lane1_OFF                       ( 4)
+  #define DDRDATA5CH1_CR_TXPERBITRANK0_Lane1_WID                       ( 4)
+  #define DDRDATA5CH1_CR_TXPERBITRANK0_Lane1_MSK                       (0x000000F0)
+  #define DDRDATA5CH1_CR_TXPERBITRANK0_Lane1_MAX                       (0x0000000F)
+  #define DDRDATA5CH1_CR_TXPERBITRANK0_Lane2_OFF                       ( 8)
+  #define DDRDATA5CH1_CR_TXPERBITRANK0_Lane2_WID                       ( 4)
+  #define DDRDATA5CH1_CR_TXPERBITRANK0_Lane2_MSK                       (0x00000F00)
+  #define DDRDATA5CH1_CR_TXPERBITRANK0_Lane2_MAX                       (0x0000000F)
+  #define DDRDATA5CH1_CR_TXPERBITRANK0_Lane3_OFF                       (12)
+  #define DDRDATA5CH1_CR_TXPERBITRANK0_Lane3_WID                       ( 4)
+  #define DDRDATA5CH1_CR_TXPERBITRANK0_Lane3_MSK                       (0x0000F000)
+  #define DDRDATA5CH1_CR_TXPERBITRANK0_Lane3_MAX                       (0x0000000F)
+  #define DDRDATA5CH1_CR_TXPERBITRANK0_Lane4_OFF                       (16)
+  #define DDRDATA5CH1_CR_TXPERBITRANK0_Lane4_WID                       ( 4)
+  #define DDRDATA5CH1_CR_TXPERBITRANK0_Lane4_MSK                       (0x000F0000)
+  #define DDRDATA5CH1_CR_TXPERBITRANK0_Lane4_MAX                       (0x0000000F)
+  #define DDRDATA5CH1_CR_TXPERBITRANK0_Lane5_OFF                       (20)
+  #define DDRDATA5CH1_CR_TXPERBITRANK0_Lane5_WID                       ( 4)
+  #define DDRDATA5CH1_CR_TXPERBITRANK0_Lane5_MSK                       (0x00F00000)
+  #define DDRDATA5CH1_CR_TXPERBITRANK0_Lane5_MAX                       (0x0000000F)
+  #define DDRDATA5CH1_CR_TXPERBITRANK0_Lane6_OFF                       (24)
+  #define DDRDATA5CH1_CR_TXPERBITRANK0_Lane6_WID                       ( 4)
+  #define DDRDATA5CH1_CR_TXPERBITRANK0_Lane6_MSK                       (0x0F000000)
+  #define DDRDATA5CH1_CR_TXPERBITRANK0_Lane6_MAX                       (0x0000000F)
+  #define DDRDATA5CH1_CR_TXPERBITRANK0_Lane7_OFF                       (28)
+  #define DDRDATA5CH1_CR_TXPERBITRANK0_Lane7_WID                       ( 4)
+  #define DDRDATA5CH1_CR_TXPERBITRANK0_Lane7_MSK                       (0xF0000000)
+  #define DDRDATA5CH1_CR_TXPERBITRANK0_Lane7_MAX                       (0x0000000F)
+
+#define DDRDATA5CH1_CR_TXPERBITRANK1_REG                             (0x00000B34)
+  #define DDRDATA5CH1_CR_TXPERBITRANK1_Lane0_OFF                       ( 0)
+  #define DDRDATA5CH1_CR_TXPERBITRANK1_Lane0_WID                       ( 4)
+  #define DDRDATA5CH1_CR_TXPERBITRANK1_Lane0_MSK                       (0x0000000F)
+  #define DDRDATA5CH1_CR_TXPERBITRANK1_Lane0_MAX                       (0x0000000F)
+  #define DDRDATA5CH1_CR_TXPERBITRANK1_Lane1_OFF                       ( 4)
+  #define DDRDATA5CH1_CR_TXPERBITRANK1_Lane1_WID                       ( 4)
+  #define DDRDATA5CH1_CR_TXPERBITRANK1_Lane1_MSK                       (0x000000F0)
+  #define DDRDATA5CH1_CR_TXPERBITRANK1_Lane1_MAX                       (0x0000000F)
+  #define DDRDATA5CH1_CR_TXPERBITRANK1_Lane2_OFF                       ( 8)
+  #define DDRDATA5CH1_CR_TXPERBITRANK1_Lane2_WID                       ( 4)
+  #define DDRDATA5CH1_CR_TXPERBITRANK1_Lane2_MSK                       (0x00000F00)
+  #define DDRDATA5CH1_CR_TXPERBITRANK1_Lane2_MAX                       (0x0000000F)
+  #define DDRDATA5CH1_CR_TXPERBITRANK1_Lane3_OFF                       (12)
+  #define DDRDATA5CH1_CR_TXPERBITRANK1_Lane3_WID                       ( 4)
+  #define DDRDATA5CH1_CR_TXPERBITRANK1_Lane3_MSK                       (0x0000F000)
+  #define DDRDATA5CH1_CR_TXPERBITRANK1_Lane3_MAX                       (0x0000000F)
+  #define DDRDATA5CH1_CR_TXPERBITRANK1_Lane4_OFF                       (16)
+  #define DDRDATA5CH1_CR_TXPERBITRANK1_Lane4_WID                       ( 4)
+  #define DDRDATA5CH1_CR_TXPERBITRANK1_Lane4_MSK                       (0x000F0000)
+  #define DDRDATA5CH1_CR_TXPERBITRANK1_Lane4_MAX                       (0x0000000F)
+  #define DDRDATA5CH1_CR_TXPERBITRANK1_Lane5_OFF                       (20)
+  #define DDRDATA5CH1_CR_TXPERBITRANK1_Lane5_WID                       ( 4)
+  #define DDRDATA5CH1_CR_TXPERBITRANK1_Lane5_MSK                       (0x00F00000)
+  #define DDRDATA5CH1_CR_TXPERBITRANK1_Lane5_MAX                       (0x0000000F)
+  #define DDRDATA5CH1_CR_TXPERBITRANK1_Lane6_OFF                       (24)
+  #define DDRDATA5CH1_CR_TXPERBITRANK1_Lane6_WID                       ( 4)
+  #define DDRDATA5CH1_CR_TXPERBITRANK1_Lane6_MSK                       (0x0F000000)
+  #define DDRDATA5CH1_CR_TXPERBITRANK1_Lane6_MAX                       (0x0000000F)
+  #define DDRDATA5CH1_CR_TXPERBITRANK1_Lane7_OFF                       (28)
+  #define DDRDATA5CH1_CR_TXPERBITRANK1_Lane7_WID                       ( 4)
+  #define DDRDATA5CH1_CR_TXPERBITRANK1_Lane7_MSK                       (0xF0000000)
+  #define DDRDATA5CH1_CR_TXPERBITRANK1_Lane7_MAX                       (0x0000000F)
+
+#define DDRDATA5CH1_CR_TXPERBITRANK2_REG                             (0x00000B38)
+  #define DDRDATA5CH1_CR_TXPERBITRANK2_Lane0_OFF                       ( 0)
+  #define DDRDATA5CH1_CR_TXPERBITRANK2_Lane0_WID                       ( 4)
+  #define DDRDATA5CH1_CR_TXPERBITRANK2_Lane0_MSK                       (0x0000000F)
+  #define DDRDATA5CH1_CR_TXPERBITRANK2_Lane0_MAX                       (0x0000000F)
+  #define DDRDATA5CH1_CR_TXPERBITRANK2_Lane1_OFF                       ( 4)
+  #define DDRDATA5CH1_CR_TXPERBITRANK2_Lane1_WID                       ( 4)
+  #define DDRDATA5CH1_CR_TXPERBITRANK2_Lane1_MSK                       (0x000000F0)
+  #define DDRDATA5CH1_CR_TXPERBITRANK2_Lane1_MAX                       (0x0000000F)
+  #define DDRDATA5CH1_CR_TXPERBITRANK2_Lane2_OFF                       ( 8)
+  #define DDRDATA5CH1_CR_TXPERBITRANK2_Lane2_WID                       ( 4)
+  #define DDRDATA5CH1_CR_TXPERBITRANK2_Lane2_MSK                       (0x00000F00)
+  #define DDRDATA5CH1_CR_TXPERBITRANK2_Lane2_MAX                       (0x0000000F)
+  #define DDRDATA5CH1_CR_TXPERBITRANK2_Lane3_OFF                       (12)
+  #define DDRDATA5CH1_CR_TXPERBITRANK2_Lane3_WID                       ( 4)
+  #define DDRDATA5CH1_CR_TXPERBITRANK2_Lane3_MSK                       (0x0000F000)
+  #define DDRDATA5CH1_CR_TXPERBITRANK2_Lane3_MAX                       (0x0000000F)
+  #define DDRDATA5CH1_CR_TXPERBITRANK2_Lane4_OFF                       (16)
+  #define DDRDATA5CH1_CR_TXPERBITRANK2_Lane4_WID                       ( 4)
+  #define DDRDATA5CH1_CR_TXPERBITRANK2_Lane4_MSK                       (0x000F0000)
+  #define DDRDATA5CH1_CR_TXPERBITRANK2_Lane4_MAX                       (0x0000000F)
+  #define DDRDATA5CH1_CR_TXPERBITRANK2_Lane5_OFF                       (20)
+  #define DDRDATA5CH1_CR_TXPERBITRANK2_Lane5_WID                       ( 4)
+  #define DDRDATA5CH1_CR_TXPERBITRANK2_Lane5_MSK                       (0x00F00000)
+  #define DDRDATA5CH1_CR_TXPERBITRANK2_Lane5_MAX                       (0x0000000F)
+  #define DDRDATA5CH1_CR_TXPERBITRANK2_Lane6_OFF                       (24)
+  #define DDRDATA5CH1_CR_TXPERBITRANK2_Lane6_WID                       ( 4)
+  #define DDRDATA5CH1_CR_TXPERBITRANK2_Lane6_MSK                       (0x0F000000)
+  #define DDRDATA5CH1_CR_TXPERBITRANK2_Lane6_MAX                       (0x0000000F)
+  #define DDRDATA5CH1_CR_TXPERBITRANK2_Lane7_OFF                       (28)
+  #define DDRDATA5CH1_CR_TXPERBITRANK2_Lane7_WID                       ( 4)
+  #define DDRDATA5CH1_CR_TXPERBITRANK2_Lane7_MSK                       (0xF0000000)
+  #define DDRDATA5CH1_CR_TXPERBITRANK2_Lane7_MAX                       (0x0000000F)
+
+#define DDRDATA5CH1_CR_TXPERBITRANK3_REG                             (0x00000B3C)
+  #define DDRDATA5CH1_CR_TXPERBITRANK3_Lane0_OFF                       ( 0)
+  #define DDRDATA5CH1_CR_TXPERBITRANK3_Lane0_WID                       ( 4)
+  #define DDRDATA5CH1_CR_TXPERBITRANK3_Lane0_MSK                       (0x0000000F)
+  #define DDRDATA5CH1_CR_TXPERBITRANK3_Lane0_MAX                       (0x0000000F)
+  #define DDRDATA5CH1_CR_TXPERBITRANK3_Lane1_OFF                       ( 4)
+  #define DDRDATA5CH1_CR_TXPERBITRANK3_Lane1_WID                       ( 4)
+  #define DDRDATA5CH1_CR_TXPERBITRANK3_Lane1_MSK                       (0x000000F0)
+  #define DDRDATA5CH1_CR_TXPERBITRANK3_Lane1_MAX                       (0x0000000F)
+  #define DDRDATA5CH1_CR_TXPERBITRANK3_Lane2_OFF                       ( 8)
+  #define DDRDATA5CH1_CR_TXPERBITRANK3_Lane2_WID                       ( 4)
+  #define DDRDATA5CH1_CR_TXPERBITRANK3_Lane2_MSK                       (0x00000F00)
+  #define DDRDATA5CH1_CR_TXPERBITRANK3_Lane2_MAX                       (0x0000000F)
+  #define DDRDATA5CH1_CR_TXPERBITRANK3_Lane3_OFF                       (12)
+  #define DDRDATA5CH1_CR_TXPERBITRANK3_Lane3_WID                       ( 4)
+  #define DDRDATA5CH1_CR_TXPERBITRANK3_Lane3_MSK                       (0x0000F000)
+  #define DDRDATA5CH1_CR_TXPERBITRANK3_Lane3_MAX                       (0x0000000F)
+  #define DDRDATA5CH1_CR_TXPERBITRANK3_Lane4_OFF                       (16)
+  #define DDRDATA5CH1_CR_TXPERBITRANK3_Lane4_WID                       ( 4)
+  #define DDRDATA5CH1_CR_TXPERBITRANK3_Lane4_MSK                       (0x000F0000)
+  #define DDRDATA5CH1_CR_TXPERBITRANK3_Lane4_MAX                       (0x0000000F)
+  #define DDRDATA5CH1_CR_TXPERBITRANK3_Lane5_OFF                       (20)
+  #define DDRDATA5CH1_CR_TXPERBITRANK3_Lane5_WID                       ( 4)
+  #define DDRDATA5CH1_CR_TXPERBITRANK3_Lane5_MSK                       (0x00F00000)
+  #define DDRDATA5CH1_CR_TXPERBITRANK3_Lane5_MAX                       (0x0000000F)
+  #define DDRDATA5CH1_CR_TXPERBITRANK3_Lane6_OFF                       (24)
+  #define DDRDATA5CH1_CR_TXPERBITRANK3_Lane6_WID                       ( 4)
+  #define DDRDATA5CH1_CR_TXPERBITRANK3_Lane6_MSK                       (0x0F000000)
+  #define DDRDATA5CH1_CR_TXPERBITRANK3_Lane6_MAX                       (0x0000000F)
+  #define DDRDATA5CH1_CR_TXPERBITRANK3_Lane7_OFF                       (28)
+  #define DDRDATA5CH1_CR_TXPERBITRANK3_Lane7_WID                       ( 4)
+  #define DDRDATA5CH1_CR_TXPERBITRANK3_Lane7_MSK                       (0xF0000000)
+  #define DDRDATA5CH1_CR_TXPERBITRANK3_Lane7_MAX                       (0x0000000F)
+
+#define DDRDATA5CH1_CR_RCOMPDATA0_REG                                (0x00000B40)
+  #define DDRDATA5CH1_CR_RCOMPDATA0_RcompDrvUp_OFF                     ( 0)
+  #define DDRDATA5CH1_CR_RCOMPDATA0_RcompDrvUp_WID                     ( 6)
+  #define DDRDATA5CH1_CR_RCOMPDATA0_RcompDrvUp_MSK                     (0x0000003F)
+  #define DDRDATA5CH1_CR_RCOMPDATA0_RcompDrvUp_MAX                     (0x0000003F)
+  #define DDRDATA5CH1_CR_RCOMPDATA0_Spare0_OFF                         ( 6)
+  #define DDRDATA5CH1_CR_RCOMPDATA0_Spare0_WID                         ( 3)
+  #define DDRDATA5CH1_CR_RCOMPDATA0_Spare0_MSK                         (0x000001C0)
+  #define DDRDATA5CH1_CR_RCOMPDATA0_Spare0_MAX                         (0x00000007)
+  #define DDRDATA5CH1_CR_RCOMPDATA0_RcompDrvDown_OFF                   ( 9)
+  #define DDRDATA5CH1_CR_RCOMPDATA0_RcompDrvDown_WID                   ( 6)
+  #define DDRDATA5CH1_CR_RCOMPDATA0_RcompDrvDown_MSK                   (0x00007E00)
+  #define DDRDATA5CH1_CR_RCOMPDATA0_RcompDrvDown_MAX                   (0x0000003F)
+  #define DDRDATA5CH1_CR_RCOMPDATA0_VTComp_OFF                         (15)
+  #define DDRDATA5CH1_CR_RCOMPDATA0_VTComp_WID                         ( 5)
+  #define DDRDATA5CH1_CR_RCOMPDATA0_VTComp_MSK                         (0x000F8000)
+  #define DDRDATA5CH1_CR_RCOMPDATA0_VTComp_MAX                         (0x0000001F)
+  #define DDRDATA5CH1_CR_RCOMPDATA0_TcoComp_OFF                        (20)
+  #define DDRDATA5CH1_CR_RCOMPDATA0_TcoComp_WID                        ( 6)
+  #define DDRDATA5CH1_CR_RCOMPDATA0_TcoComp_MSK                        (0x03F00000)
+  #define DDRDATA5CH1_CR_RCOMPDATA0_TcoComp_MAX                        (0x0000003F)
+  #define DDRDATA5CH1_CR_RCOMPDATA0_SlewRateComp_OFF                   (26)
+  #define DDRDATA5CH1_CR_RCOMPDATA0_SlewRateComp_WID                   ( 5)
+  #define DDRDATA5CH1_CR_RCOMPDATA0_SlewRateComp_MSK                   (0x7C000000)
+  #define DDRDATA5CH1_CR_RCOMPDATA0_SlewRateComp_MAX                   (0x0000001F)
+  #define DDRDATA5CH1_CR_RCOMPDATA0_Spare2_OFF                         (31)
+  #define DDRDATA5CH1_CR_RCOMPDATA0_Spare2_WID                         ( 1)
+  #define DDRDATA5CH1_CR_RCOMPDATA0_Spare2_MSK                         (0x80000000)
+  #define DDRDATA5CH1_CR_RCOMPDATA0_Spare2_MAX                         (0x00000001)
+
+#define DDRDATA5CH1_CR_RCOMPDATA1_REG                                (0x00000B44)
+  #define DDRDATA5CH1_CR_RCOMPDATA1_RcompOdtUp_OFF                     ( 0)
+  #define DDRDATA5CH1_CR_RCOMPDATA1_RcompOdtUp_WID                     ( 6)
+  #define DDRDATA5CH1_CR_RCOMPDATA1_RcompOdtUp_MSK                     (0x0000003F)
+  #define DDRDATA5CH1_CR_RCOMPDATA1_RcompOdtUp_MAX                     (0x0000003F)
+  #define DDRDATA5CH1_CR_RCOMPDATA1_Spare0_OFF                         ( 6)
+  #define DDRDATA5CH1_CR_RCOMPDATA1_Spare0_WID                         ( 3)
+  #define DDRDATA5CH1_CR_RCOMPDATA1_Spare0_MSK                         (0x000001C0)
+  #define DDRDATA5CH1_CR_RCOMPDATA1_Spare0_MAX                         (0x00000007)
+  #define DDRDATA5CH1_CR_RCOMPDATA1_RcompOdtDown_OFF                   ( 9)
+  #define DDRDATA5CH1_CR_RCOMPDATA1_RcompOdtDown_WID                   ( 6)
+  #define DDRDATA5CH1_CR_RCOMPDATA1_RcompOdtDown_MSK                   (0x00007E00)
+  #define DDRDATA5CH1_CR_RCOMPDATA1_RcompOdtDown_MAX                   (0x0000003F)
+  #define DDRDATA5CH1_CR_RCOMPDATA1_Spare1_OFF                         (15)
+  #define DDRDATA5CH1_CR_RCOMPDATA1_Spare1_WID                         ( 1)
+  #define DDRDATA5CH1_CR_RCOMPDATA1_Spare1_MSK                         (0x00008000)
+  #define DDRDATA5CH1_CR_RCOMPDATA1_Spare1_MAX                         (0x00000001)
+  #define DDRDATA5CH1_CR_RCOMPDATA1_PanicDrvDn_OFF                     (16)
+  #define DDRDATA5CH1_CR_RCOMPDATA1_PanicDrvDn_WID                     ( 6)
+  #define DDRDATA5CH1_CR_RCOMPDATA1_PanicDrvDn_MSK                     (0x003F0000)
+  #define DDRDATA5CH1_CR_RCOMPDATA1_PanicDrvDn_MAX                     (0x0000003F)
+  #define DDRDATA5CH1_CR_RCOMPDATA1_PanicDrvUp_OFF                     (22)
+  #define DDRDATA5CH1_CR_RCOMPDATA1_PanicDrvUp_WID                     ( 6)
+  #define DDRDATA5CH1_CR_RCOMPDATA1_PanicDrvUp_MSK                     (0x0FC00000)
+  #define DDRDATA5CH1_CR_RCOMPDATA1_PanicDrvUp_MAX                     (0x0000003F)
+  #define DDRDATA5CH1_CR_RCOMPDATA1_LevelShifterComp_OFF               (28)
+  #define DDRDATA5CH1_CR_RCOMPDATA1_LevelShifterComp_WID               ( 3)
+  #define DDRDATA5CH1_CR_RCOMPDATA1_LevelShifterComp_MSK               (0x70000000)
+  #define DDRDATA5CH1_CR_RCOMPDATA1_LevelShifterComp_MAX               (0x00000007)
+  #define DDRDATA5CH1_CR_RCOMPDATA1_Spare2_OFF                         (31)
+  #define DDRDATA5CH1_CR_RCOMPDATA1_Spare2_WID                         ( 1)
+  #define DDRDATA5CH1_CR_RCOMPDATA1_Spare2_MSK                         (0x80000000)
+  #define DDRDATA5CH1_CR_RCOMPDATA1_Spare2_MAX                         (0x00000001)
+
+#define DDRDATA5CH1_CR_TXXTALK_REG                                   (0x00000B48)
+  #define DDRDATA5CH1_CR_TXXTALK_Lane0_OFF                             ( 0)
+  #define DDRDATA5CH1_CR_TXXTALK_Lane0_WID                             ( 4)
+  #define DDRDATA5CH1_CR_TXXTALK_Lane0_MSK                             (0x0000000F)
+  #define DDRDATA5CH1_CR_TXXTALK_Lane0_MAX                             (0x0000000F)
+  #define DDRDATA5CH1_CR_TXXTALK_Lane1_OFF                             ( 4)
+  #define DDRDATA5CH1_CR_TXXTALK_Lane1_WID                             ( 4)
+  #define DDRDATA5CH1_CR_TXXTALK_Lane1_MSK                             (0x000000F0)
+  #define DDRDATA5CH1_CR_TXXTALK_Lane1_MAX                             (0x0000000F)
+  #define DDRDATA5CH1_CR_TXXTALK_Lane2_OFF                             ( 8)
+  #define DDRDATA5CH1_CR_TXXTALK_Lane2_WID                             ( 4)
+  #define DDRDATA5CH1_CR_TXXTALK_Lane2_MSK                             (0x00000F00)
+  #define DDRDATA5CH1_CR_TXXTALK_Lane2_MAX                             (0x0000000F)
+  #define DDRDATA5CH1_CR_TXXTALK_Lane3_OFF                             (12)
+  #define DDRDATA5CH1_CR_TXXTALK_Lane3_WID                             ( 4)
+  #define DDRDATA5CH1_CR_TXXTALK_Lane3_MSK                             (0x0000F000)
+  #define DDRDATA5CH1_CR_TXXTALK_Lane3_MAX                             (0x0000000F)
+  #define DDRDATA5CH1_CR_TXXTALK_Lane4_OFF                             (16)
+  #define DDRDATA5CH1_CR_TXXTALK_Lane4_WID                             ( 4)
+  #define DDRDATA5CH1_CR_TXXTALK_Lane4_MSK                             (0x000F0000)
+  #define DDRDATA5CH1_CR_TXXTALK_Lane4_MAX                             (0x0000000F)
+  #define DDRDATA5CH1_CR_TXXTALK_Lane5_OFF                             (20)
+  #define DDRDATA5CH1_CR_TXXTALK_Lane5_WID                             ( 4)
+  #define DDRDATA5CH1_CR_TXXTALK_Lane5_MSK                             (0x00F00000)
+  #define DDRDATA5CH1_CR_TXXTALK_Lane5_MAX                             (0x0000000F)
+  #define DDRDATA5CH1_CR_TXXTALK_Lane6_OFF                             (24)
+  #define DDRDATA5CH1_CR_TXXTALK_Lane6_WID                             ( 4)
+  #define DDRDATA5CH1_CR_TXXTALK_Lane6_MSK                             (0x0F000000)
+  #define DDRDATA5CH1_CR_TXXTALK_Lane6_MAX                             (0x0000000F)
+  #define DDRDATA5CH1_CR_TXXTALK_Lane7_OFF                             (28)
+  #define DDRDATA5CH1_CR_TXXTALK_Lane7_WID                             ( 4)
+  #define DDRDATA5CH1_CR_TXXTALK_Lane7_MSK                             (0xF0000000)
+  #define DDRDATA5CH1_CR_TXXTALK_Lane7_MAX                             (0x0000000F)
+
+#define DDRDATA5CH1_CR_RXOFFSETVDQ_REG                               (0x00000B4C)
+  #define DDRDATA5CH1_CR_RXOFFSETVDQ_Lane0_OFF                         ( 0)
+  #define DDRDATA5CH1_CR_RXOFFSETVDQ_Lane0_WID                         ( 4)
+  #define DDRDATA5CH1_CR_RXOFFSETVDQ_Lane0_MSK                         (0x0000000F)
+  #define DDRDATA5CH1_CR_RXOFFSETVDQ_Lane0_MAX                         (0x0000000F)
+  #define DDRDATA5CH1_CR_RXOFFSETVDQ_Lane1_OFF                         ( 4)
+  #define DDRDATA5CH1_CR_RXOFFSETVDQ_Lane1_WID                         ( 4)
+  #define DDRDATA5CH1_CR_RXOFFSETVDQ_Lane1_MSK                         (0x000000F0)
+  #define DDRDATA5CH1_CR_RXOFFSETVDQ_Lane1_MAX                         (0x0000000F)
+  #define DDRDATA5CH1_CR_RXOFFSETVDQ_Lane2_OFF                         ( 8)
+  #define DDRDATA5CH1_CR_RXOFFSETVDQ_Lane2_WID                         ( 4)
+  #define DDRDATA5CH1_CR_RXOFFSETVDQ_Lane2_MSK                         (0x00000F00)
+  #define DDRDATA5CH1_CR_RXOFFSETVDQ_Lane2_MAX                         (0x0000000F)
+  #define DDRDATA5CH1_CR_RXOFFSETVDQ_Lane3_OFF                         (12)
+  #define DDRDATA5CH1_CR_RXOFFSETVDQ_Lane3_WID                         ( 4)
+  #define DDRDATA5CH1_CR_RXOFFSETVDQ_Lane3_MSK                         (0x0000F000)
+  #define DDRDATA5CH1_CR_RXOFFSETVDQ_Lane3_MAX                         (0x0000000F)
+  #define DDRDATA5CH1_CR_RXOFFSETVDQ_Lane4_OFF                         (16)
+  #define DDRDATA5CH1_CR_RXOFFSETVDQ_Lane4_WID                         ( 4)
+  #define DDRDATA5CH1_CR_RXOFFSETVDQ_Lane4_MSK                         (0x000F0000)
+  #define DDRDATA5CH1_CR_RXOFFSETVDQ_Lane4_MAX                         (0x0000000F)
+  #define DDRDATA5CH1_CR_RXOFFSETVDQ_Lane5_OFF                         (20)
+  #define DDRDATA5CH1_CR_RXOFFSETVDQ_Lane5_WID                         ( 4)
+  #define DDRDATA5CH1_CR_RXOFFSETVDQ_Lane5_MSK                         (0x00F00000)
+  #define DDRDATA5CH1_CR_RXOFFSETVDQ_Lane5_MAX                         (0x0000000F)
+  #define DDRDATA5CH1_CR_RXOFFSETVDQ_Lane6_OFF                         (24)
+  #define DDRDATA5CH1_CR_RXOFFSETVDQ_Lane6_WID                         ( 4)
+  #define DDRDATA5CH1_CR_RXOFFSETVDQ_Lane6_MSK                         (0x0F000000)
+  #define DDRDATA5CH1_CR_RXOFFSETVDQ_Lane6_MAX                         (0x0000000F)
+  #define DDRDATA5CH1_CR_RXOFFSETVDQ_Lane7_OFF                         (28)
+  #define DDRDATA5CH1_CR_RXOFFSETVDQ_Lane7_WID                         ( 4)
+  #define DDRDATA5CH1_CR_RXOFFSETVDQ_Lane7_MSK                         (0xF0000000)
+  #define DDRDATA5CH1_CR_RXOFFSETVDQ_Lane7_MAX                         (0x0000000F)
+
+#define DDRDATA5CH1_CR_DDRDATARESERVED_REG                           (0x00000B50)
+  #define DDRDATA5CH1_CR_DDRDATARESERVED_Spare_OFF                     ( 0)
+  #define DDRDATA5CH1_CR_DDRDATARESERVED_Spare_WID                     (32)
+  #define DDRDATA5CH1_CR_DDRDATARESERVED_Spare_MSK                     (0xFFFFFFFF)
+  #define DDRDATA5CH1_CR_DDRDATARESERVED_Spare_MAX                     (0xFFFFFFFF)
+
+#define DDRDATA5CH1_CR_DATATRAINFEEDBACK_REG                         (0x00000B54)
+  #define DDRDATA5CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_OFF       ( 0)
+  #define DDRDATA5CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_WID       ( 9)
+  #define DDRDATA5CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_MSK       (0x000001FF)
+  #define DDRDATA5CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_MAX       (0x000001FF)
+  #define DDRDATA5CH1_CR_DATATRAINFEEDBACK_Spare_OFF                   ( 9)
+  #define DDRDATA5CH1_CR_DATATRAINFEEDBACK_Spare_WID                   (23)
+  #define DDRDATA5CH1_CR_DATATRAINFEEDBACK_Spare_MSK                   (0xFFFFFE00)
+  #define DDRDATA5CH1_CR_DATATRAINFEEDBACK_Spare_MAX                   (0x007FFFFF)
+
+#define DDRDATA5CH1_CR_DLLPITESTANDADC_REG                           (0x00000B58)
+  #define DDRDATA5CH1_CR_DLLPITESTANDADC_RunTest_OFF                   ( 0)
+  #define DDRDATA5CH1_CR_DLLPITESTANDADC_RunTest_WID                   ( 1)
+  #define DDRDATA5CH1_CR_DLLPITESTANDADC_RunTest_MSK                   (0x00000001)
+  #define DDRDATA5CH1_CR_DLLPITESTANDADC_RunTest_MAX                   (0x00000001)
+  #define DDRDATA5CH1_CR_DLLPITESTANDADC_RunTest_DEF                   (0x00000000)
+  #define DDRDATA5CH1_CR_DLLPITESTANDADC_Load_OFF                      ( 1)
+  #define DDRDATA5CH1_CR_DLLPITESTANDADC_Load_WID                      ( 1)
+  #define DDRDATA5CH1_CR_DLLPITESTANDADC_Load_MSK                      (0x00000002)
+  #define DDRDATA5CH1_CR_DLLPITESTANDADC_Load_MAX                      (0x00000001)
+  #define DDRDATA5CH1_CR_DLLPITESTANDADC_Load_DEF                      (0x00000000)
+  #define DDRDATA5CH1_CR_DLLPITESTANDADC_ModeHVM_OFF                   ( 2)
+  #define DDRDATA5CH1_CR_DLLPITESTANDADC_ModeHVM_WID                   ( 1)
+  #define DDRDATA5CH1_CR_DLLPITESTANDADC_ModeHVM_MSK                   (0x00000004)
+  #define DDRDATA5CH1_CR_DLLPITESTANDADC_ModeHVM_MAX                   (0x00000001)
+  #define DDRDATA5CH1_CR_DLLPITESTANDADC_ModeHVM_DEF                   (0x00000000)
+  #define DDRDATA5CH1_CR_DLLPITESTANDADC_ModeDV_OFF                    ( 3)
+  #define DDRDATA5CH1_CR_DLLPITESTANDADC_ModeDV_WID                    ( 1)
+  #define DDRDATA5CH1_CR_DLLPITESTANDADC_ModeDV_MSK                    (0x00000008)
+  #define DDRDATA5CH1_CR_DLLPITESTANDADC_ModeDV_MAX                    (0x00000001)
+  #define DDRDATA5CH1_CR_DLLPITESTANDADC_ModeDV_DEF                    (0x00000000)
+  #define DDRDATA5CH1_CR_DLLPITESTANDADC_ModeADC_OFF                   ( 4)
+  #define DDRDATA5CH1_CR_DLLPITESTANDADC_ModeADC_WID                   ( 1)
+  #define DDRDATA5CH1_CR_DLLPITESTANDADC_ModeADC_MSK                   (0x00000010)
+  #define DDRDATA5CH1_CR_DLLPITESTANDADC_ModeADC_MAX                   (0x00000001)
+  #define DDRDATA5CH1_CR_DLLPITESTANDADC_ModeADC_DEF                   (0x00000000)
+  #define DDRDATA5CH1_CR_DLLPITESTANDADC_LoadCount_OFF                 ( 5)
+  #define DDRDATA5CH1_CR_DLLPITESTANDADC_LoadCount_WID                 (10)
+  #define DDRDATA5CH1_CR_DLLPITESTANDADC_LoadCount_MSK                 (0x00007FE0)
+  #define DDRDATA5CH1_CR_DLLPITESTANDADC_LoadCount_MAX                 (0x000003FF)
+  #define DDRDATA5CH1_CR_DLLPITESTANDADC_CountStatus_OFF               (15)
+  #define DDRDATA5CH1_CR_DLLPITESTANDADC_CountStatus_WID               (10)
+  #define DDRDATA5CH1_CR_DLLPITESTANDADC_CountStatus_MSK               (0x01FF8000)
+  #define DDRDATA5CH1_CR_DLLPITESTANDADC_CountStatus_MAX               (0x000003FF)
+  #define DDRDATA5CH1_CR_DLLPITESTANDADC_CountStatus_DEF               (0x00000000)
+  #define DDRDATA5CH1_CR_DLLPITESTANDADC_Spare_OFF                     (25)
+  #define DDRDATA5CH1_CR_DLLPITESTANDADC_Spare_WID                     ( 7)
+  #define DDRDATA5CH1_CR_DLLPITESTANDADC_Spare_MSK                     (0xFE000000)
+  #define DDRDATA5CH1_CR_DLLPITESTANDADC_Spare_MAX                     (0x0000007F)
+
+#define DDRDATA5CH1_CR_DDRCRDATAOFFSETCOMP_REG                       (0x00000B5C)
+  #define DDRDATA5CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_OFF     ( 0)
+  #define DDRDATA5CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_WID     ( 6)
+  #define DDRDATA5CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MSK     (0x0000003F)
+  #define DDRDATA5CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MAX     (0x0000003F)
+  #define DDRDATA5CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_DEF     (0x00000000)
+  #define DDRDATA5CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_OFF   ( 6)
+  #define DDRDATA5CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_WID   ( 6)
+  #define DDRDATA5CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MSK   (0x00000FC0)
+  #define DDRDATA5CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MAX   (0x0000003F)
+  #define DDRDATA5CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_DEF   (0x00000000)
+  #define DDRDATA5CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_OFF     (12)
+  #define DDRDATA5CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_WID     ( 5)
+  #define DDRDATA5CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MSK     (0x0001F000)
+  #define DDRDATA5CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MAX     (0x0000001F)
+  #define DDRDATA5CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_DEF     (0x00000000)
+  #define DDRDATA5CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_OFF   (17)
+  #define DDRDATA5CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_WID   ( 5)
+  #define DDRDATA5CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MSK   (0x003E0000)
+  #define DDRDATA5CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MAX   (0x0000001F)
+  #define DDRDATA5CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_DEF   (0x00000000)
+  #define DDRDATA5CH1_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_OFF       (22)
+  #define DDRDATA5CH1_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_WID       ( 5)
+  #define DDRDATA5CH1_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_MSK       (0x07C00000)
+  #define DDRDATA5CH1_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_MAX       (0x0000001F)
+  #define DDRDATA5CH1_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_DEF       (0x00000000)
+  #define DDRDATA5CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_OFF  (27)
+  #define DDRDATA5CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_WID  ( 5)
+  #define DDRDATA5CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MSK  (0xF8000000)
+  #define DDRDATA5CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MAX  (0x0000001F)
+  #define DDRDATA5CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_DEF  (0x00000000)
+
+#define DDRDATA5CH1_CR_DDRCRDATACONTROL1_REG                         (0x00000B60)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_RefPi_OFF                   ( 0)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_RefPi_WID                   ( 4)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_RefPi_MSK                   (0x0000000F)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_RefPi_MAX                   (0x0000000F)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_RefPi_DEF                   (0x00000000)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_DllMask_OFF                 ( 4)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_DllMask_WID                 ( 2)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_DllMask_MSK                 (0x00000030)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_DllMask_MAX                 (0x00000003)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_DllMask_DEF                 (0x00000000)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_DllWeakLock_OFF             ( 6)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_DllWeakLock_WID             ( 1)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_DllWeakLock_MSK             (0x00000040)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_DllWeakLock_MAX             (0x00000001)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_DllWeakLock_DEF             (0x00000000)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_OFF      ( 7)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_WID      ( 3)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MSK      (0x00000380)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MAX      (0x00000007)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_DEF      (0x00000000)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_OFF               (10)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_WID               ( 3)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_MSK               (0x00001C00)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_MAX               (0x00000007)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_DEF               (0x00000000)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_OdtDelay_OFF                (13)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_OdtDelay_WID                ( 4)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_OdtDelay_MSK                (0x0001E000)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_OdtDelay_MAX                (0x0000000F)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_OdtDelay_DEF                (0x00000000)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_OdtDuration_OFF             (17)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_OdtDuration_WID             ( 3)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_OdtDuration_MSK             (0x000E0000)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_OdtDuration_MAX             (0x00000007)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_OdtDuration_DEF             (0x00000000)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_OFF           (20)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_WID           ( 4)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_MSK           (0x00F00000)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_MAX           (0x0000000F)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_DEF           (0x00000000)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_OFF        (24)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_WID        ( 3)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_MSK        (0x07000000)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_MAX        (0x00000007)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_DEF        (0x00000000)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_BurstEndODTDelay_OFF        (27)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_BurstEndODTDelay_WID        ( 3)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_BurstEndODTDelay_MSK        (0x38000000)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_BurstEndODTDelay_MAX        (0x00000007)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_BurstEndODTDelay_DEF        (0x00000000)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_OFF          (30)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_WID          ( 1)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_MSK          (0x40000000)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_MAX          (0x00000001)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_DEF          (0x00000000)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_Rsvd1_OFF                   (31)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_Rsvd1_WID                   ( 1)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_Rsvd1_MSK                   (0x80000000)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_Rsvd1_MAX                   (0x00000001)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_Rsvd1_DEF                   (0x00000000)
+
+#define DDRDATA5CH1_CR_DDRCRDATACONTROL2_REG                         (0x00000B64)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_OFF            ( 0)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_WID            ( 5)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_MSK            (0x0000001F)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_MAX            (0x0000001F)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_DEF            (0x00000000)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_OFF             ( 5)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_WID             ( 1)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_MSK             (0x00000020)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_MAX             (0x00000001)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_DEF             (0x00000000)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_ForceRxOn_OFF               ( 6)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_ForceRxOn_WID               ( 1)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_ForceRxOn_MSK               (0x00000040)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_ForceRxOn_MAX               (0x00000001)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_ForceRxOn_DEF               (0x00000000)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_LeakerComp_OFF              ( 7)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_LeakerComp_WID              ( 2)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_LeakerComp_MSK              (0x00000180)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_LeakerComp_MAX              (0x00000003)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_LeakerComp_DEF              (0x00000000)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_OFF          ( 9)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_WID          ( 4)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_MSK          (0x00001E00)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_MAX          (0x0000000F)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_DEF          (0x00000008)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_OFF             (13)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_WID             ( 5)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_MSK             (0x0003E000)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_MAX             (0x0000001F)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_DEF             (0x00000011)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_OFF             (18)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_WID             ( 1)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_MSK             (0x00040000)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_MAX             (0x00000001)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_DEF             (0x00000000)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_Spare_OFF                   (19)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_Spare_WID                   (13)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_Spare_MSK                   (0xFFF80000)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_Spare_MAX                   (0x00001FFF)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_Spare_DEF                   (0x00000000)
+
+#define DDRDATA5CH1_CR_DDRCRVSSHIORVREFCONTROL_REG                   (0x00000B6C)
+  #define DDRDATA5CH1_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_OFF    ( 0)
+  #define DDRDATA5CH1_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_WID    (24)
+  #define DDRDATA5CH1_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_MSK    (0x00FFFFFF)
+  #define DDRDATA5CH1_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_MAX    (0x00FFFFFF)
+  #define DDRDATA5CH1_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_DEF    (0x00000000)
+  #define DDRDATA5CH1_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_OFF        (24)
+  #define DDRDATA5CH1_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_WID        ( 8)
+  #define DDRDATA5CH1_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_MSK        (0xFF000000)
+  #define DDRDATA5CH1_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_MAX        (0x000000FF)
+  #define DDRDATA5CH1_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_DEF        (0x00000000)
+
+#define DDRDATA5CH1_CR_DDRCRDATAOFFSETTRAIN_REG                      (0x00000B70)
+  #define DDRDATA5CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_OFF          ( 0)
+  #define DDRDATA5CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_WID          ( 6)
+  #define DDRDATA5CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MSK          (0x0000003F)
+  #define DDRDATA5CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MAX          (0x0000003F)
+  #define DDRDATA5CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_DEF          (0x00000000)
+  #define DDRDATA5CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_OFF          ( 6)
+  #define DDRDATA5CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_WID          ( 6)
+  #define DDRDATA5CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MSK          (0x00000FC0)
+  #define DDRDATA5CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MAX          (0x0000003F)
+  #define DDRDATA5CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_DEF          (0x00000000)
+  #define DDRDATA5CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_OFF           (12)
+  #define DDRDATA5CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_WID           ( 6)
+  #define DDRDATA5CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MSK           (0x0003F000)
+  #define DDRDATA5CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MAX           (0x0000003F)
+  #define DDRDATA5CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_DEF           (0x00000000)
+  #define DDRDATA5CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_OFF          (18)
+  #define DDRDATA5CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_WID          ( 6)
+  #define DDRDATA5CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MSK          (0x00FC0000)
+  #define DDRDATA5CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MAX          (0x0000003F)
+  #define DDRDATA5CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_DEF          (0x00000000)
+  #define DDRDATA5CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_OFF           (24)
+  #define DDRDATA5CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_WID           ( 7)
+  #define DDRDATA5CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MSK           (0x7F000000)
+  #define DDRDATA5CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MAX           (0x0000007F)
+  #define DDRDATA5CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_DEF           (0x00000000)
+  #define DDRDATA5CH1_CR_DDRCRDATAOFFSETTRAIN_Spare_OFF                (31)
+  #define DDRDATA5CH1_CR_DDRCRDATAOFFSETTRAIN_Spare_WID                ( 1)
+  #define DDRDATA5CH1_CR_DDRCRDATAOFFSETTRAIN_Spare_MSK                (0x80000000)
+  #define DDRDATA5CH1_CR_DDRCRDATAOFFSETTRAIN_Spare_MAX                (0x00000001)
+  #define DDRDATA5CH1_CR_DDRCRDATAOFFSETTRAIN_Spare_DEF                (0x00000000)
+
+#define DDRDATA5CH1_CR_DDRCRDATACONTROL0_REG                         (0x00000B74)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_OFF          ( 0)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_WID          ( 1)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_MSK          (0x00000001)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_MAX          (0x00000001)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_DEF          (0x00000000)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_OFF          ( 1)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_WID          ( 1)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_MSK          (0x00000002)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_MAX          (0x00000001)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_DEF          (0x00000000)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_OFF          ( 2)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_WID          ( 1)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_MSK          (0x00000004)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_MAX          (0x00000001)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_DEF          (0x00000000)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_OFF    ( 3)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_WID    ( 1)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MSK    (0x00000008)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MAX    (0x00000001)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_DEF    (0x00000000)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_TxOn_OFF                    ( 4)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_TxOn_WID                    ( 1)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_TxOn_MSK                    (0x00000010)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_TxOn_MAX                    (0x00000001)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_TxOn_DEF                    (0x00000000)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RfOn_OFF                    ( 5)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RfOn_WID                    ( 1)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RfOn_MSK                    (0x00000020)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RfOn_MAX                    (0x00000001)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RfOn_DEF                    (0x00000000)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RxPiOn_OFF                  ( 6)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RxPiOn_WID                  ( 1)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RxPiOn_MSK                  (0x00000040)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RxPiOn_MAX                  (0x00000001)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RxPiOn_DEF                  (0x00000000)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_TxPiOn_OFF                  ( 7)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_TxPiOn_WID                  ( 1)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_TxPiOn_MSK                  (0x00000080)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_TxPiOn_MAX                  (0x00000001)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_TxPiOn_DEF                  (0x00000000)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_OFF        ( 8)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_WID        ( 1)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_MSK        (0x00000100)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_MAX        (0x00000001)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_DEF        (0x00000000)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_OFF        ( 9)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_WID        ( 1)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MSK        (0x00000200)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MAX        (0x00000001)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_DEF        (0x00000000)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_TxDisable_OFF               (10)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_TxDisable_WID               ( 1)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_TxDisable_MSK               (0x00000400)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_TxDisable_MAX               (0x00000001)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_TxDisable_DEF               (0x00000000)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RxDisable_OFF               (11)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RxDisable_WID               ( 1)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RxDisable_MSK               (0x00000800)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RxDisable_MAX               (0x00000001)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RxDisable_DEF               (0x00000000)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_TxLong_OFF                  (12)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_TxLong_WID                  ( 1)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_TxLong_MSK                  (0x00001000)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_TxLong_MAX                  (0x00000001)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_TxLong_DEF                  (0x00000000)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_OFF               (13)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_WID               ( 2)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_MSK               (0x00006000)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_MAX               (0x00000003)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_DEF               (0x00000000)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RxReadPointer_OFF           (15)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RxReadPointer_WID           ( 3)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RxReadPointer_MSK           (0x00038000)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RxReadPointer_MAX           (0x00000007)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RxReadPointer_DEF           (0x00000000)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_DriverSegmentEnable_OFF     (18)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_DriverSegmentEnable_WID     ( 1)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_DriverSegmentEnable_MSK     (0x00040000)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_DriverSegmentEnable_MAX     (0x00000001)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_DriverSegmentEnable_DEF     (0x00000000)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_DataVccddqHi_OFF            (19)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_DataVccddqHi_WID            ( 1)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_DataVccddqHi_MSK            (0x00080000)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_DataVccddqHi_MAX            (0x00000001)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_DataVccddqHi_DEF            (0x00000000)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_ReadRFRd_OFF                (20)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_ReadRFRd_WID                ( 1)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_ReadRFRd_MSK                (0x00100000)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_ReadRFRd_MAX                (0x00000001)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_ReadRFRd_DEF                (0x00000000)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_ReadRFWr_OFF                (21)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_ReadRFWr_WID                ( 1)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_ReadRFWr_MSK                (0x00200000)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_ReadRFWr_MAX                (0x00000001)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_ReadRFWr_DEF                (0x00000000)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_ReadRFRank_OFF              (22)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_ReadRFRank_WID              ( 2)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_ReadRFRank_MSK              (0x00C00000)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_ReadRFRank_MAX              (0x00000003)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_ReadRFRank_DEF              (0x00000000)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_OFF              (24)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_WID              ( 1)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_MSK              (0x01000000)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_MAX              (0x00000001)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_DEF              (0x00000000)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_OdtSampOff_OFF              (25)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_OdtSampOff_WID              ( 1)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_OdtSampOff_MSK              (0x02000000)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_OdtSampOff_MAX              (0x00000001)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_OdtSampOff_DEF              (0x00000000)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_OFF        (26)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_WID        ( 1)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_MSK        (0x04000000)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_MAX        (0x00000001)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_DEF        (0x00000000)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_OFF         (27)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_WID         ( 1)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MSK         (0x08000000)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MAX         (0x00000001)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_DEF         (0x00000000)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_OFF              (28)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_WID              ( 1)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_MSK              (0x10000000)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_MAX              (0x00000001)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_DEF              (0x00000000)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_EnReadPreamble_OFF          (29)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_EnReadPreamble_WID          ( 1)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_EnReadPreamble_MSK          (0x20000000)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_EnReadPreamble_MAX          (0x00000001)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_EnReadPreamble_DEF          (0x00000000)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_OFF         (30)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_WID         ( 1)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MSK         (0x40000000)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MAX         (0x00000001)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_DEF         (0x00000000)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_OFF            (31)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_WID            ( 1)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_MSK            (0x80000000)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_MAX            (0x00000001)
+  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_DEF            (0x00000000)
+
+#define DDRDATA5CH1_CR_DDRCRVREFADJUST1_REG                          (0x00000B78)
+  #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_CAVrefCtl_OFF                ( 0)
+  #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_CAVrefCtl_WID                ( 7)
+  #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_CAVrefCtl_MSK                (0x0000007F)
+  #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_CAVrefCtl_MAX                (0x0000007F)
+  #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_CAVrefCtl_DEF                (0x00000000)
+  #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_Ch1VrefCtl_OFF               ( 7)
+  #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_Ch1VrefCtl_WID               ( 7)
+  #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_Ch1VrefCtl_MSK               (0x00003F80)
+  #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_Ch1VrefCtl_MAX               (0x0000007F)
+  #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_Ch1VrefCtl_DEF               (0x00000000)
+  #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_Ch0VrefCtl_OFF               (14)
+  #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_Ch0VrefCtl_WID               ( 7)
+  #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_Ch0VrefCtl_MSK               (0x001FC000)
+  #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_Ch0VrefCtl_MAX               (0x0000007F)
+  #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_Ch0VrefCtl_DEF               (0x00000000)
+  #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCA_OFF             (21)
+  #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCA_WID             ( 1)
+  #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCA_MSK             (0x00200000)
+  #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCA_MAX             (0x00000001)
+  #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCA_DEF             (0x00000000)
+  #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_OFF            (22)
+  #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_WID            ( 1)
+  #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_MSK            (0x00400000)
+  #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_MAX            (0x00000001)
+  #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_DEF            (0x00000000)
+  #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_OFF            (23)
+  #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_WID            ( 1)
+  #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_MSK            (0x00800000)
+  #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_MAX            (0x00000001)
+  #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_DEF            (0x00000000)
+  #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_HiZTimerCtrl_OFF             (24)
+  #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_HiZTimerCtrl_WID             ( 2)
+  #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_HiZTimerCtrl_MSK             (0x03000000)
+  #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_HiZTimerCtrl_MAX             (0x00000003)
+  #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_HiZTimerCtrl_DEF             (0x00000000)
+  #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_OFF            (26)
+  #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_WID            ( 1)
+  #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_MSK            (0x04000000)
+  #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_MAX            (0x00000001)
+  #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_DEF            (0x00000000)
+  #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_Rsvd_OFF                     (27)
+  #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_Rsvd_WID                     ( 2)
+  #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_Rsvd_MSK                     (0x18000000)
+  #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_Rsvd_MAX                     (0x00000003)
+  #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_Rsvd_DEF                     (0x00000000)
+  #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_caSlowBW_OFF                 (29)
+  #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_caSlowBW_WID                 ( 1)
+  #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_caSlowBW_MSK                 (0x20000000)
+  #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_caSlowBW_MAX                 (0x00000001)
+  #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_caSlowBW_DEF                 (0x00000000)
+  #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_ch0SlowBW_OFF                (30)
+  #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_ch0SlowBW_WID                ( 1)
+  #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_ch0SlowBW_MSK                (0x40000000)
+  #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_ch0SlowBW_MAX                (0x00000001)
+  #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_ch0SlowBW_DEF                (0x00000000)
+  #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_ch1SlowBW_OFF                (31)
+  #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_ch1SlowBW_WID                ( 1)
+  #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_ch1SlowBW_MSK                (0x80000000)
+  #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_ch1SlowBW_MAX                (0x00000001)
+  #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_ch1SlowBW_DEF                (0x00000000)
+
+#define DDRDATA6CH0_CR_RXTRAINRANK0_REG                              (0x00000C00)
+  #define DDRDATA6CH0_CR_RXTRAINRANK0_RxRcvEnPi_OFF                    ( 0)
+  #define DDRDATA6CH0_CR_RXTRAINRANK0_RxRcvEnPi_WID                    ( 9)
+  #define DDRDATA6CH0_CR_RXTRAINRANK0_RxRcvEnPi_MSK                    (0x000001FF)
+  #define DDRDATA6CH0_CR_RXTRAINRANK0_RxRcvEnPi_MAX                    (0x000001FF)
+  #define DDRDATA6CH0_CR_RXTRAINRANK0_RxDqsPPi_OFF                     ( 9)
+  #define DDRDATA6CH0_CR_RXTRAINRANK0_RxDqsPPi_WID                     ( 6)
+  #define DDRDATA6CH0_CR_RXTRAINRANK0_RxDqsPPi_MSK                     (0x00007E00)
+  #define DDRDATA6CH0_CR_RXTRAINRANK0_RxDqsPPi_MAX                     (0x0000003F)
+  #define DDRDATA6CH0_CR_RXTRAINRANK0_RxEq_OFF                         (15)
+  #define DDRDATA6CH0_CR_RXTRAINRANK0_RxEq_WID                         ( 5)
+  #define DDRDATA6CH0_CR_RXTRAINRANK0_RxEq_MSK                         (0x000F8000)
+  #define DDRDATA6CH0_CR_RXTRAINRANK0_RxEq_MAX                         (0x0000001F)
+  #define DDRDATA6CH0_CR_RXTRAINRANK0_RxDqsNPi_OFF                     (20)
+  #define DDRDATA6CH0_CR_RXTRAINRANK0_RxDqsNPi_WID                     ( 6)
+  #define DDRDATA6CH0_CR_RXTRAINRANK0_RxDqsNPi_MSK                     (0x03F00000)
+  #define DDRDATA6CH0_CR_RXTRAINRANK0_RxDqsNPi_MAX                     (0x0000003F)
+  #define DDRDATA6CH0_CR_RXTRAINRANK0_RxVref_OFF                       (26)
+  #define DDRDATA6CH0_CR_RXTRAINRANK0_RxVref_WID                       ( 6)
+  #define DDRDATA6CH0_CR_RXTRAINRANK0_RxVref_MSK                       (0xFC000000)
+  #define DDRDATA6CH0_CR_RXTRAINRANK0_RxVref_MAX                       (0x0000003F)
+
+#define DDRDATA6CH0_CR_RXTRAINRANK1_REG                              (0x00000C04)
+  #define DDRDATA6CH0_CR_RXTRAINRANK1_RxRcvEnPi_OFF                    ( 0)
+  #define DDRDATA6CH0_CR_RXTRAINRANK1_RxRcvEnPi_WID                    ( 9)
+  #define DDRDATA6CH0_CR_RXTRAINRANK1_RxRcvEnPi_MSK                    (0x000001FF)
+  #define DDRDATA6CH0_CR_RXTRAINRANK1_RxRcvEnPi_MAX                    (0x000001FF)
+  #define DDRDATA6CH0_CR_RXTRAINRANK1_RxDqsPPi_OFF                     ( 9)
+  #define DDRDATA6CH0_CR_RXTRAINRANK1_RxDqsPPi_WID                     ( 6)
+  #define DDRDATA6CH0_CR_RXTRAINRANK1_RxDqsPPi_MSK                     (0x00007E00)
+  #define DDRDATA6CH0_CR_RXTRAINRANK1_RxDqsPPi_MAX                     (0x0000003F)
+  #define DDRDATA6CH0_CR_RXTRAINRANK1_RxEq_OFF                         (15)
+  #define DDRDATA6CH0_CR_RXTRAINRANK1_RxEq_WID                         ( 5)
+  #define DDRDATA6CH0_CR_RXTRAINRANK1_RxEq_MSK                         (0x000F8000)
+  #define DDRDATA6CH0_CR_RXTRAINRANK1_RxEq_MAX                         (0x0000001F)
+  #define DDRDATA6CH0_CR_RXTRAINRANK1_RxDqsNPi_OFF                     (20)
+  #define DDRDATA6CH0_CR_RXTRAINRANK1_RxDqsNPi_WID                     ( 6)
+  #define DDRDATA6CH0_CR_RXTRAINRANK1_RxDqsNPi_MSK                     (0x03F00000)
+  #define DDRDATA6CH0_CR_RXTRAINRANK1_RxDqsNPi_MAX                     (0x0000003F)
+  #define DDRDATA6CH0_CR_RXTRAINRANK1_RxVref_OFF                       (26)
+  #define DDRDATA6CH0_CR_RXTRAINRANK1_RxVref_WID                       ( 6)
+  #define DDRDATA6CH0_CR_RXTRAINRANK1_RxVref_MSK                       (0xFC000000)
+  #define DDRDATA6CH0_CR_RXTRAINRANK1_RxVref_MAX                       (0x0000003F)
+
+#define DDRDATA6CH0_CR_RXTRAINRANK2_REG                              (0x00000C08)
+  #define DDRDATA6CH0_CR_RXTRAINRANK2_RxRcvEnPi_OFF                    ( 0)
+  #define DDRDATA6CH0_CR_RXTRAINRANK2_RxRcvEnPi_WID                    ( 9)
+  #define DDRDATA6CH0_CR_RXTRAINRANK2_RxRcvEnPi_MSK                    (0x000001FF)
+  #define DDRDATA6CH0_CR_RXTRAINRANK2_RxRcvEnPi_MAX                    (0x000001FF)
+  #define DDRDATA6CH0_CR_RXTRAINRANK2_RxDqsPPi_OFF                     ( 9)
+  #define DDRDATA6CH0_CR_RXTRAINRANK2_RxDqsPPi_WID                     ( 6)
+  #define DDRDATA6CH0_CR_RXTRAINRANK2_RxDqsPPi_MSK                     (0x00007E00)
+  #define DDRDATA6CH0_CR_RXTRAINRANK2_RxDqsPPi_MAX                     (0x0000003F)
+  #define DDRDATA6CH0_CR_RXTRAINRANK2_RxEq_OFF                         (15)
+  #define DDRDATA6CH0_CR_RXTRAINRANK2_RxEq_WID                         ( 5)
+  #define DDRDATA6CH0_CR_RXTRAINRANK2_RxEq_MSK                         (0x000F8000)
+  #define DDRDATA6CH0_CR_RXTRAINRANK2_RxEq_MAX                         (0x0000001F)
+  #define DDRDATA6CH0_CR_RXTRAINRANK2_RxDqsNPi_OFF                     (20)
+  #define DDRDATA6CH0_CR_RXTRAINRANK2_RxDqsNPi_WID                     ( 6)
+  #define DDRDATA6CH0_CR_RXTRAINRANK2_RxDqsNPi_MSK                     (0x03F00000)
+  #define DDRDATA6CH0_CR_RXTRAINRANK2_RxDqsNPi_MAX                     (0x0000003F)
+  #define DDRDATA6CH0_CR_RXTRAINRANK2_RxVref_OFF                       (26)
+  #define DDRDATA6CH0_CR_RXTRAINRANK2_RxVref_WID                       ( 6)
+  #define DDRDATA6CH0_CR_RXTRAINRANK2_RxVref_MSK                       (0xFC000000)
+  #define DDRDATA6CH0_CR_RXTRAINRANK2_RxVref_MAX                       (0x0000003F)
+
+#define DDRDATA6CH0_CR_RXTRAINRANK3_REG                              (0x00000C0C)
+  #define DDRDATA6CH0_CR_RXTRAINRANK3_RxRcvEnPi_OFF                    ( 0)
+  #define DDRDATA6CH0_CR_RXTRAINRANK3_RxRcvEnPi_WID                    ( 9)
+  #define DDRDATA6CH0_CR_RXTRAINRANK3_RxRcvEnPi_MSK                    (0x000001FF)
+  #define DDRDATA6CH0_CR_RXTRAINRANK3_RxRcvEnPi_MAX                    (0x000001FF)
+  #define DDRDATA6CH0_CR_RXTRAINRANK3_RxDqsPPi_OFF                     ( 9)
+  #define DDRDATA6CH0_CR_RXTRAINRANK3_RxDqsPPi_WID                     ( 6)
+  #define DDRDATA6CH0_CR_RXTRAINRANK3_RxDqsPPi_MSK                     (0x00007E00)
+  #define DDRDATA6CH0_CR_RXTRAINRANK3_RxDqsPPi_MAX                     (0x0000003F)
+  #define DDRDATA6CH0_CR_RXTRAINRANK3_RxEq_OFF                         (15)
+  #define DDRDATA6CH0_CR_RXTRAINRANK3_RxEq_WID                         ( 5)
+  #define DDRDATA6CH0_CR_RXTRAINRANK3_RxEq_MSK                         (0x000F8000)
+  #define DDRDATA6CH0_CR_RXTRAINRANK3_RxEq_MAX                         (0x0000001F)
+  #define DDRDATA6CH0_CR_RXTRAINRANK3_RxDqsNPi_OFF                     (20)
+  #define DDRDATA6CH0_CR_RXTRAINRANK3_RxDqsNPi_WID                     ( 6)
+  #define DDRDATA6CH0_CR_RXTRAINRANK3_RxDqsNPi_MSK                     (0x03F00000)
+  #define DDRDATA6CH0_CR_RXTRAINRANK3_RxDqsNPi_MAX                     (0x0000003F)
+  #define DDRDATA6CH0_CR_RXTRAINRANK3_RxVref_OFF                       (26)
+  #define DDRDATA6CH0_CR_RXTRAINRANK3_RxVref_WID                       ( 6)
+  #define DDRDATA6CH0_CR_RXTRAINRANK3_RxVref_MSK                       (0xFC000000)
+  #define DDRDATA6CH0_CR_RXTRAINRANK3_RxVref_MAX                       (0x0000003F)
+
+#define DDRDATA6CH0_CR_RXPERBITRANK0_REG                             (0x00000C10)
+  #define DDRDATA6CH0_CR_RXPERBITRANK0_Lane0_OFF                       ( 0)
+  #define DDRDATA6CH0_CR_RXPERBITRANK0_Lane0_WID                       ( 4)
+  #define DDRDATA6CH0_CR_RXPERBITRANK0_Lane0_MSK                       (0x0000000F)
+  #define DDRDATA6CH0_CR_RXPERBITRANK0_Lane0_MAX                       (0x0000000F)
+  #define DDRDATA6CH0_CR_RXPERBITRANK0_Lane1_OFF                       ( 4)
+  #define DDRDATA6CH0_CR_RXPERBITRANK0_Lane1_WID                       ( 4)
+  #define DDRDATA6CH0_CR_RXPERBITRANK0_Lane1_MSK                       (0x000000F0)
+  #define DDRDATA6CH0_CR_RXPERBITRANK0_Lane1_MAX                       (0x0000000F)
+  #define DDRDATA6CH0_CR_RXPERBITRANK0_Lane2_OFF                       ( 8)
+  #define DDRDATA6CH0_CR_RXPERBITRANK0_Lane2_WID                       ( 4)
+  #define DDRDATA6CH0_CR_RXPERBITRANK0_Lane2_MSK                       (0x00000F00)
+  #define DDRDATA6CH0_CR_RXPERBITRANK0_Lane2_MAX                       (0x0000000F)
+  #define DDRDATA6CH0_CR_RXPERBITRANK0_Lane3_OFF                       (12)
+  #define DDRDATA6CH0_CR_RXPERBITRANK0_Lane3_WID                       ( 4)
+  #define DDRDATA6CH0_CR_RXPERBITRANK0_Lane3_MSK                       (0x0000F000)
+  #define DDRDATA6CH0_CR_RXPERBITRANK0_Lane3_MAX                       (0x0000000F)
+  #define DDRDATA6CH0_CR_RXPERBITRANK0_Lane4_OFF                       (16)
+  #define DDRDATA6CH0_CR_RXPERBITRANK0_Lane4_WID                       ( 4)
+  #define DDRDATA6CH0_CR_RXPERBITRANK0_Lane4_MSK                       (0x000F0000)
+  #define DDRDATA6CH0_CR_RXPERBITRANK0_Lane4_MAX                       (0x0000000F)
+  #define DDRDATA6CH0_CR_RXPERBITRANK0_Lane5_OFF                       (20)
+  #define DDRDATA6CH0_CR_RXPERBITRANK0_Lane5_WID                       ( 4)
+  #define DDRDATA6CH0_CR_RXPERBITRANK0_Lane5_MSK                       (0x00F00000)
+  #define DDRDATA6CH0_CR_RXPERBITRANK0_Lane5_MAX                       (0x0000000F)
+  #define DDRDATA6CH0_CR_RXPERBITRANK0_Lane6_OFF                       (24)
+  #define DDRDATA6CH0_CR_RXPERBITRANK0_Lane6_WID                       ( 4)
+  #define DDRDATA6CH0_CR_RXPERBITRANK0_Lane6_MSK                       (0x0F000000)
+  #define DDRDATA6CH0_CR_RXPERBITRANK0_Lane6_MAX                       (0x0000000F)
+  #define DDRDATA6CH0_CR_RXPERBITRANK0_Lane7_OFF                       (28)
+  #define DDRDATA6CH0_CR_RXPERBITRANK0_Lane7_WID                       ( 4)
+  #define DDRDATA6CH0_CR_RXPERBITRANK0_Lane7_MSK                       (0xF0000000)
+  #define DDRDATA6CH0_CR_RXPERBITRANK0_Lane7_MAX                       (0x0000000F)
+
+#define DDRDATA6CH0_CR_RXPERBITRANK1_REG                             (0x00000C14)
+  #define DDRDATA6CH0_CR_RXPERBITRANK1_Lane0_OFF                       ( 0)
+  #define DDRDATA6CH0_CR_RXPERBITRANK1_Lane0_WID                       ( 4)
+  #define DDRDATA6CH0_CR_RXPERBITRANK1_Lane0_MSK                       (0x0000000F)
+  #define DDRDATA6CH0_CR_RXPERBITRANK1_Lane0_MAX                       (0x0000000F)
+  #define DDRDATA6CH0_CR_RXPERBITRANK1_Lane1_OFF                       ( 4)
+  #define DDRDATA6CH0_CR_RXPERBITRANK1_Lane1_WID                       ( 4)
+  #define DDRDATA6CH0_CR_RXPERBITRANK1_Lane1_MSK                       (0x000000F0)
+  #define DDRDATA6CH0_CR_RXPERBITRANK1_Lane1_MAX                       (0x0000000F)
+  #define DDRDATA6CH0_CR_RXPERBITRANK1_Lane2_OFF                       ( 8)
+  #define DDRDATA6CH0_CR_RXPERBITRANK1_Lane2_WID                       ( 4)
+  #define DDRDATA6CH0_CR_RXPERBITRANK1_Lane2_MSK                       (0x00000F00)
+  #define DDRDATA6CH0_CR_RXPERBITRANK1_Lane2_MAX                       (0x0000000F)
+  #define DDRDATA6CH0_CR_RXPERBITRANK1_Lane3_OFF                       (12)
+  #define DDRDATA6CH0_CR_RXPERBITRANK1_Lane3_WID                       ( 4)
+  #define DDRDATA6CH0_CR_RXPERBITRANK1_Lane3_MSK                       (0x0000F000)
+  #define DDRDATA6CH0_CR_RXPERBITRANK1_Lane3_MAX                       (0x0000000F)
+  #define DDRDATA6CH0_CR_RXPERBITRANK1_Lane4_OFF                       (16)
+  #define DDRDATA6CH0_CR_RXPERBITRANK1_Lane4_WID                       ( 4)
+  #define DDRDATA6CH0_CR_RXPERBITRANK1_Lane4_MSK                       (0x000F0000)
+  #define DDRDATA6CH0_CR_RXPERBITRANK1_Lane4_MAX                       (0x0000000F)
+  #define DDRDATA6CH0_CR_RXPERBITRANK1_Lane5_OFF                       (20)
+  #define DDRDATA6CH0_CR_RXPERBITRANK1_Lane5_WID                       ( 4)
+  #define DDRDATA6CH0_CR_RXPERBITRANK1_Lane5_MSK                       (0x00F00000)
+  #define DDRDATA6CH0_CR_RXPERBITRANK1_Lane5_MAX                       (0x0000000F)
+  #define DDRDATA6CH0_CR_RXPERBITRANK1_Lane6_OFF                       (24)
+  #define DDRDATA6CH0_CR_RXPERBITRANK1_Lane6_WID                       ( 4)
+  #define DDRDATA6CH0_CR_RXPERBITRANK1_Lane6_MSK                       (0x0F000000)
+  #define DDRDATA6CH0_CR_RXPERBITRANK1_Lane6_MAX                       (0x0000000F)
+  #define DDRDATA6CH0_CR_RXPERBITRANK1_Lane7_OFF                       (28)
+  #define DDRDATA6CH0_CR_RXPERBITRANK1_Lane7_WID                       ( 4)
+  #define DDRDATA6CH0_CR_RXPERBITRANK1_Lane7_MSK                       (0xF0000000)
+  #define DDRDATA6CH0_CR_RXPERBITRANK1_Lane7_MAX                       (0x0000000F)
+
+#define DDRDATA6CH0_CR_RXPERBITRANK2_REG                             (0x00000C18)
+  #define DDRDATA6CH0_CR_RXPERBITRANK2_Lane0_OFF                       ( 0)
+  #define DDRDATA6CH0_CR_RXPERBITRANK2_Lane0_WID                       ( 4)
+  #define DDRDATA6CH0_CR_RXPERBITRANK2_Lane0_MSK                       (0x0000000F)
+  #define DDRDATA6CH0_CR_RXPERBITRANK2_Lane0_MAX                       (0x0000000F)
+  #define DDRDATA6CH0_CR_RXPERBITRANK2_Lane1_OFF                       ( 4)
+  #define DDRDATA6CH0_CR_RXPERBITRANK2_Lane1_WID                       ( 4)
+  #define DDRDATA6CH0_CR_RXPERBITRANK2_Lane1_MSK                       (0x000000F0)
+  #define DDRDATA6CH0_CR_RXPERBITRANK2_Lane1_MAX                       (0x0000000F)
+  #define DDRDATA6CH0_CR_RXPERBITRANK2_Lane2_OFF                       ( 8)
+  #define DDRDATA6CH0_CR_RXPERBITRANK2_Lane2_WID                       ( 4)
+  #define DDRDATA6CH0_CR_RXPERBITRANK2_Lane2_MSK                       (0x00000F00)
+  #define DDRDATA6CH0_CR_RXPERBITRANK2_Lane2_MAX                       (0x0000000F)
+  #define DDRDATA6CH0_CR_RXPERBITRANK2_Lane3_OFF                       (12)
+  #define DDRDATA6CH0_CR_RXPERBITRANK2_Lane3_WID                       ( 4)
+  #define DDRDATA6CH0_CR_RXPERBITRANK2_Lane3_MSK                       (0x0000F000)
+  #define DDRDATA6CH0_CR_RXPERBITRANK2_Lane3_MAX                       (0x0000000F)
+  #define DDRDATA6CH0_CR_RXPERBITRANK2_Lane4_OFF                       (16)
+  #define DDRDATA6CH0_CR_RXPERBITRANK2_Lane4_WID                       ( 4)
+  #define DDRDATA6CH0_CR_RXPERBITRANK2_Lane4_MSK                       (0x000F0000)
+  #define DDRDATA6CH0_CR_RXPERBITRANK2_Lane4_MAX                       (0x0000000F)
+  #define DDRDATA6CH0_CR_RXPERBITRANK2_Lane5_OFF                       (20)
+  #define DDRDATA6CH0_CR_RXPERBITRANK2_Lane5_WID                       ( 4)
+  #define DDRDATA6CH0_CR_RXPERBITRANK2_Lane5_MSK                       (0x00F00000)
+  #define DDRDATA6CH0_CR_RXPERBITRANK2_Lane5_MAX                       (0x0000000F)
+  #define DDRDATA6CH0_CR_RXPERBITRANK2_Lane6_OFF                       (24)
+  #define DDRDATA6CH0_CR_RXPERBITRANK2_Lane6_WID                       ( 4)
+  #define DDRDATA6CH0_CR_RXPERBITRANK2_Lane6_MSK                       (0x0F000000)
+  #define DDRDATA6CH0_CR_RXPERBITRANK2_Lane6_MAX                       (0x0000000F)
+  #define DDRDATA6CH0_CR_RXPERBITRANK2_Lane7_OFF                       (28)
+  #define DDRDATA6CH0_CR_RXPERBITRANK2_Lane7_WID                       ( 4)
+  #define DDRDATA6CH0_CR_RXPERBITRANK2_Lane7_MSK                       (0xF0000000)
+  #define DDRDATA6CH0_CR_RXPERBITRANK2_Lane7_MAX                       (0x0000000F)
+
+#define DDRDATA6CH0_CR_RXPERBITRANK3_REG                             (0x00000C1C)
+  #define DDRDATA6CH0_CR_RXPERBITRANK3_Lane0_OFF                       ( 0)
+  #define DDRDATA6CH0_CR_RXPERBITRANK3_Lane0_WID                       ( 4)
+  #define DDRDATA6CH0_CR_RXPERBITRANK3_Lane0_MSK                       (0x0000000F)
+  #define DDRDATA6CH0_CR_RXPERBITRANK3_Lane0_MAX                       (0x0000000F)
+  #define DDRDATA6CH0_CR_RXPERBITRANK3_Lane1_OFF                       ( 4)
+  #define DDRDATA6CH0_CR_RXPERBITRANK3_Lane1_WID                       ( 4)
+  #define DDRDATA6CH0_CR_RXPERBITRANK3_Lane1_MSK                       (0x000000F0)
+  #define DDRDATA6CH0_CR_RXPERBITRANK3_Lane1_MAX                       (0x0000000F)
+  #define DDRDATA6CH0_CR_RXPERBITRANK3_Lane2_OFF                       ( 8)
+  #define DDRDATA6CH0_CR_RXPERBITRANK3_Lane2_WID                       ( 4)
+  #define DDRDATA6CH0_CR_RXPERBITRANK3_Lane2_MSK                       (0x00000F00)
+  #define DDRDATA6CH0_CR_RXPERBITRANK3_Lane2_MAX                       (0x0000000F)
+  #define DDRDATA6CH0_CR_RXPERBITRANK3_Lane3_OFF                       (12)
+  #define DDRDATA6CH0_CR_RXPERBITRANK3_Lane3_WID                       ( 4)
+  #define DDRDATA6CH0_CR_RXPERBITRANK3_Lane3_MSK                       (0x0000F000)
+  #define DDRDATA6CH0_CR_RXPERBITRANK3_Lane3_MAX                       (0x0000000F)
+  #define DDRDATA6CH0_CR_RXPERBITRANK3_Lane4_OFF                       (16)
+  #define DDRDATA6CH0_CR_RXPERBITRANK3_Lane4_WID                       ( 4)
+  #define DDRDATA6CH0_CR_RXPERBITRANK3_Lane4_MSK                       (0x000F0000)
+  #define DDRDATA6CH0_CR_RXPERBITRANK3_Lane4_MAX                       (0x0000000F)
+  #define DDRDATA6CH0_CR_RXPERBITRANK3_Lane5_OFF                       (20)
+  #define DDRDATA6CH0_CR_RXPERBITRANK3_Lane5_WID                       ( 4)
+  #define DDRDATA6CH0_CR_RXPERBITRANK3_Lane5_MSK                       (0x00F00000)
+  #define DDRDATA6CH0_CR_RXPERBITRANK3_Lane5_MAX                       (0x0000000F)
+  #define DDRDATA6CH0_CR_RXPERBITRANK3_Lane6_OFF                       (24)
+  #define DDRDATA6CH0_CR_RXPERBITRANK3_Lane6_WID                       ( 4)
+  #define DDRDATA6CH0_CR_RXPERBITRANK3_Lane6_MSK                       (0x0F000000)
+  #define DDRDATA6CH0_CR_RXPERBITRANK3_Lane6_MAX                       (0x0000000F)
+  #define DDRDATA6CH0_CR_RXPERBITRANK3_Lane7_OFF                       (28)
+  #define DDRDATA6CH0_CR_RXPERBITRANK3_Lane7_WID                       ( 4)
+  #define DDRDATA6CH0_CR_RXPERBITRANK3_Lane7_MSK                       (0xF0000000)
+  #define DDRDATA6CH0_CR_RXPERBITRANK3_Lane7_MAX                       (0x0000000F)
+
+#define DDRDATA6CH0_CR_TXTRAINRANK0_REG                              (0x00000C20)
+  #define DDRDATA6CH0_CR_TXTRAINRANK0_TxDqDelay_OFF                    ( 0)
+  #define DDRDATA6CH0_CR_TXTRAINRANK0_TxDqDelay_WID                    ( 9)
+  #define DDRDATA6CH0_CR_TXTRAINRANK0_TxDqDelay_MSK                    (0x000001FF)
+  #define DDRDATA6CH0_CR_TXTRAINRANK0_TxDqDelay_MAX                    (0x000001FF)
+  #define DDRDATA6CH0_CR_TXTRAINRANK0_TxDqsDelay_OFF                   ( 9)
+  #define DDRDATA6CH0_CR_TXTRAINRANK0_TxDqsDelay_WID                   ( 9)
+  #define DDRDATA6CH0_CR_TXTRAINRANK0_TxDqsDelay_MSK                   (0x0003FE00)
+  #define DDRDATA6CH0_CR_TXTRAINRANK0_TxDqsDelay_MAX                   (0x000001FF)
+  #define DDRDATA6CH0_CR_TXTRAINRANK0_Spare0_OFF                       (18)
+  #define DDRDATA6CH0_CR_TXTRAINRANK0_Spare0_WID                       ( 2)
+  #define DDRDATA6CH0_CR_TXTRAINRANK0_Spare0_MSK                       (0x000C0000)
+  #define DDRDATA6CH0_CR_TXTRAINRANK0_Spare0_MAX                       (0x00000003)
+  #define DDRDATA6CH0_CR_TXTRAINRANK0_TxEqualization_OFF               (20)
+  #define DDRDATA6CH0_CR_TXTRAINRANK0_TxEqualization_WID               ( 6)
+  #define DDRDATA6CH0_CR_TXTRAINRANK0_TxEqualization_MSK               (0x03F00000)
+  #define DDRDATA6CH0_CR_TXTRAINRANK0_TxEqualization_MAX               (0x0000003F)
+  #define DDRDATA6CH0_CR_TXTRAINRANK0_Spare1_OFF                       (26)
+  #define DDRDATA6CH0_CR_TXTRAINRANK0_Spare1_WID                       ( 6)
+  #define DDRDATA6CH0_CR_TXTRAINRANK0_Spare1_MSK                       (0xFC000000)
+  #define DDRDATA6CH0_CR_TXTRAINRANK0_Spare1_MAX                       (0x0000003F)
+
+#define DDRDATA6CH0_CR_TXTRAINRANK1_REG                              (0x00000C24)
+  #define DDRDATA6CH0_CR_TXTRAINRANK1_TxDqDelay_OFF                    ( 0)
+  #define DDRDATA6CH0_CR_TXTRAINRANK1_TxDqDelay_WID                    ( 9)
+  #define DDRDATA6CH0_CR_TXTRAINRANK1_TxDqDelay_MSK                    (0x000001FF)
+  #define DDRDATA6CH0_CR_TXTRAINRANK1_TxDqDelay_MAX                    (0x000001FF)
+  #define DDRDATA6CH0_CR_TXTRAINRANK1_TxDqsDelay_OFF                   ( 9)
+  #define DDRDATA6CH0_CR_TXTRAINRANK1_TxDqsDelay_WID                   ( 9)
+  #define DDRDATA6CH0_CR_TXTRAINRANK1_TxDqsDelay_MSK                   (0x0003FE00)
+  #define DDRDATA6CH0_CR_TXTRAINRANK1_TxDqsDelay_MAX                   (0x000001FF)
+  #define DDRDATA6CH0_CR_TXTRAINRANK1_Spare0_OFF                       (18)
+  #define DDRDATA6CH0_CR_TXTRAINRANK1_Spare0_WID                       ( 2)
+  #define DDRDATA6CH0_CR_TXTRAINRANK1_Spare0_MSK                       (0x000C0000)
+  #define DDRDATA6CH0_CR_TXTRAINRANK1_Spare0_MAX                       (0x00000003)
+  #define DDRDATA6CH0_CR_TXTRAINRANK1_TxEqualization_OFF               (20)
+  #define DDRDATA6CH0_CR_TXTRAINRANK1_TxEqualization_WID               ( 6)
+  #define DDRDATA6CH0_CR_TXTRAINRANK1_TxEqualization_MSK               (0x03F00000)
+  #define DDRDATA6CH0_CR_TXTRAINRANK1_TxEqualization_MAX               (0x0000003F)
+  #define DDRDATA6CH0_CR_TXTRAINRANK1_Spare1_OFF                       (26)
+  #define DDRDATA6CH0_CR_TXTRAINRANK1_Spare1_WID                       ( 6)
+  #define DDRDATA6CH0_CR_TXTRAINRANK1_Spare1_MSK                       (0xFC000000)
+  #define DDRDATA6CH0_CR_TXTRAINRANK1_Spare1_MAX                       (0x0000003F)
+
+#define DDRDATA6CH0_CR_TXTRAINRANK2_REG                              (0x00000C28)
+  #define DDRDATA6CH0_CR_TXTRAINRANK2_TxDqDelay_OFF                    ( 0)
+  #define DDRDATA6CH0_CR_TXTRAINRANK2_TxDqDelay_WID                    ( 9)
+  #define DDRDATA6CH0_CR_TXTRAINRANK2_TxDqDelay_MSK                    (0x000001FF)
+  #define DDRDATA6CH0_CR_TXTRAINRANK2_TxDqDelay_MAX                    (0x000001FF)
+  #define DDRDATA6CH0_CR_TXTRAINRANK2_TxDqsDelay_OFF                   ( 9)
+  #define DDRDATA6CH0_CR_TXTRAINRANK2_TxDqsDelay_WID                   ( 9)
+  #define DDRDATA6CH0_CR_TXTRAINRANK2_TxDqsDelay_MSK                   (0x0003FE00)
+  #define DDRDATA6CH0_CR_TXTRAINRANK2_TxDqsDelay_MAX                   (0x000001FF)
+  #define DDRDATA6CH0_CR_TXTRAINRANK2_Spare0_OFF                       (18)
+  #define DDRDATA6CH0_CR_TXTRAINRANK2_Spare0_WID                       ( 2)
+  #define DDRDATA6CH0_CR_TXTRAINRANK2_Spare0_MSK                       (0x000C0000)
+  #define DDRDATA6CH0_CR_TXTRAINRANK2_Spare0_MAX                       (0x00000003)
+  #define DDRDATA6CH0_CR_TXTRAINRANK2_TxEqualization_OFF               (20)
+  #define DDRDATA6CH0_CR_TXTRAINRANK2_TxEqualization_WID               ( 6)
+  #define DDRDATA6CH0_CR_TXTRAINRANK2_TxEqualization_MSK               (0x03F00000)
+  #define DDRDATA6CH0_CR_TXTRAINRANK2_TxEqualization_MAX               (0x0000003F)
+  #define DDRDATA6CH0_CR_TXTRAINRANK2_Spare1_OFF                       (26)
+  #define DDRDATA6CH0_CR_TXTRAINRANK2_Spare1_WID                       ( 6)
+  #define DDRDATA6CH0_CR_TXTRAINRANK2_Spare1_MSK                       (0xFC000000)
+  #define DDRDATA6CH0_CR_TXTRAINRANK2_Spare1_MAX                       (0x0000003F)
+
+#define DDRDATA6CH0_CR_TXTRAINRANK3_REG                              (0x00000C2C)
+  #define DDRDATA6CH0_CR_TXTRAINRANK3_TxDqDelay_OFF                    ( 0)
+  #define DDRDATA6CH0_CR_TXTRAINRANK3_TxDqDelay_WID                    ( 9)
+  #define DDRDATA6CH0_CR_TXTRAINRANK3_TxDqDelay_MSK                    (0x000001FF)
+  #define DDRDATA6CH0_CR_TXTRAINRANK3_TxDqDelay_MAX                    (0x000001FF)
+  #define DDRDATA6CH0_CR_TXTRAINRANK3_TxDqsDelay_OFF                   ( 9)
+  #define DDRDATA6CH0_CR_TXTRAINRANK3_TxDqsDelay_WID                   ( 9)
+  #define DDRDATA6CH0_CR_TXTRAINRANK3_TxDqsDelay_MSK                   (0x0003FE00)
+  #define DDRDATA6CH0_CR_TXTRAINRANK3_TxDqsDelay_MAX                   (0x000001FF)
+  #define DDRDATA6CH0_CR_TXTRAINRANK3_Spare0_OFF                       (18)
+  #define DDRDATA6CH0_CR_TXTRAINRANK3_Spare0_WID                       ( 2)
+  #define DDRDATA6CH0_CR_TXTRAINRANK3_Spare0_MSK                       (0x000C0000)
+  #define DDRDATA6CH0_CR_TXTRAINRANK3_Spare0_MAX                       (0x00000003)
+  #define DDRDATA6CH0_CR_TXTRAINRANK3_TxEqualization_OFF               (20)
+  #define DDRDATA6CH0_CR_TXTRAINRANK3_TxEqualization_WID               ( 6)
+  #define DDRDATA6CH0_CR_TXTRAINRANK3_TxEqualization_MSK               (0x03F00000)
+  #define DDRDATA6CH0_CR_TXTRAINRANK3_TxEqualization_MAX               (0x0000003F)
+  #define DDRDATA6CH0_CR_TXTRAINRANK3_Spare1_OFF                       (26)
+  #define DDRDATA6CH0_CR_TXTRAINRANK3_Spare1_WID                       ( 6)
+  #define DDRDATA6CH0_CR_TXTRAINRANK3_Spare1_MSK                       (0xFC000000)
+  #define DDRDATA6CH0_CR_TXTRAINRANK3_Spare1_MAX                       (0x0000003F)
+
+#define DDRDATA6CH0_CR_TXPERBITRANK0_REG                             (0x00000C30)
+  #define DDRDATA6CH0_CR_TXPERBITRANK0_Lane0_OFF                       ( 0)
+  #define DDRDATA6CH0_CR_TXPERBITRANK0_Lane0_WID                       ( 4)
+  #define DDRDATA6CH0_CR_TXPERBITRANK0_Lane0_MSK                       (0x0000000F)
+  #define DDRDATA6CH0_CR_TXPERBITRANK0_Lane0_MAX                       (0x0000000F)
+  #define DDRDATA6CH0_CR_TXPERBITRANK0_Lane1_OFF                       ( 4)
+  #define DDRDATA6CH0_CR_TXPERBITRANK0_Lane1_WID                       ( 4)
+  #define DDRDATA6CH0_CR_TXPERBITRANK0_Lane1_MSK                       (0x000000F0)
+  #define DDRDATA6CH0_CR_TXPERBITRANK0_Lane1_MAX                       (0x0000000F)
+  #define DDRDATA6CH0_CR_TXPERBITRANK0_Lane2_OFF                       ( 8)
+  #define DDRDATA6CH0_CR_TXPERBITRANK0_Lane2_WID                       ( 4)
+  #define DDRDATA6CH0_CR_TXPERBITRANK0_Lane2_MSK                       (0x00000F00)
+  #define DDRDATA6CH0_CR_TXPERBITRANK0_Lane2_MAX                       (0x0000000F)
+  #define DDRDATA6CH0_CR_TXPERBITRANK0_Lane3_OFF                       (12)
+  #define DDRDATA6CH0_CR_TXPERBITRANK0_Lane3_WID                       ( 4)
+  #define DDRDATA6CH0_CR_TXPERBITRANK0_Lane3_MSK                       (0x0000F000)
+  #define DDRDATA6CH0_CR_TXPERBITRANK0_Lane3_MAX                       (0x0000000F)
+  #define DDRDATA6CH0_CR_TXPERBITRANK0_Lane4_OFF                       (16)
+  #define DDRDATA6CH0_CR_TXPERBITRANK0_Lane4_WID                       ( 4)
+  #define DDRDATA6CH0_CR_TXPERBITRANK0_Lane4_MSK                       (0x000F0000)
+  #define DDRDATA6CH0_CR_TXPERBITRANK0_Lane4_MAX                       (0x0000000F)
+  #define DDRDATA6CH0_CR_TXPERBITRANK0_Lane5_OFF                       (20)
+  #define DDRDATA6CH0_CR_TXPERBITRANK0_Lane5_WID                       ( 4)
+  #define DDRDATA6CH0_CR_TXPERBITRANK0_Lane5_MSK                       (0x00F00000)
+  #define DDRDATA6CH0_CR_TXPERBITRANK0_Lane5_MAX                       (0x0000000F)
+  #define DDRDATA6CH0_CR_TXPERBITRANK0_Lane6_OFF                       (24)
+  #define DDRDATA6CH0_CR_TXPERBITRANK0_Lane6_WID                       ( 4)
+  #define DDRDATA6CH0_CR_TXPERBITRANK0_Lane6_MSK                       (0x0F000000)
+  #define DDRDATA6CH0_CR_TXPERBITRANK0_Lane6_MAX                       (0x0000000F)
+  #define DDRDATA6CH0_CR_TXPERBITRANK0_Lane7_OFF                       (28)
+  #define DDRDATA6CH0_CR_TXPERBITRANK0_Lane7_WID                       ( 4)
+  #define DDRDATA6CH0_CR_TXPERBITRANK0_Lane7_MSK                       (0xF0000000)
+  #define DDRDATA6CH0_CR_TXPERBITRANK0_Lane7_MAX                       (0x0000000F)
+
+#define DDRDATA6CH0_CR_TXPERBITRANK1_REG                             (0x00000C34)
+  #define DDRDATA6CH0_CR_TXPERBITRANK1_Lane0_OFF                       ( 0)
+  #define DDRDATA6CH0_CR_TXPERBITRANK1_Lane0_WID                       ( 4)
+  #define DDRDATA6CH0_CR_TXPERBITRANK1_Lane0_MSK                       (0x0000000F)
+  #define DDRDATA6CH0_CR_TXPERBITRANK1_Lane0_MAX                       (0x0000000F)
+  #define DDRDATA6CH0_CR_TXPERBITRANK1_Lane1_OFF                       ( 4)
+  #define DDRDATA6CH0_CR_TXPERBITRANK1_Lane1_WID                       ( 4)
+  #define DDRDATA6CH0_CR_TXPERBITRANK1_Lane1_MSK                       (0x000000F0)
+  #define DDRDATA6CH0_CR_TXPERBITRANK1_Lane1_MAX                       (0x0000000F)
+  #define DDRDATA6CH0_CR_TXPERBITRANK1_Lane2_OFF                       ( 8)
+  #define DDRDATA6CH0_CR_TXPERBITRANK1_Lane2_WID                       ( 4)
+  #define DDRDATA6CH0_CR_TXPERBITRANK1_Lane2_MSK                       (0x00000F00)
+  #define DDRDATA6CH0_CR_TXPERBITRANK1_Lane2_MAX                       (0x0000000F)
+  #define DDRDATA6CH0_CR_TXPERBITRANK1_Lane3_OFF                       (12)
+  #define DDRDATA6CH0_CR_TXPERBITRANK1_Lane3_WID                       ( 4)
+  #define DDRDATA6CH0_CR_TXPERBITRANK1_Lane3_MSK                       (0x0000F000)
+  #define DDRDATA6CH0_CR_TXPERBITRANK1_Lane3_MAX                       (0x0000000F)
+  #define DDRDATA6CH0_CR_TXPERBITRANK1_Lane4_OFF                       (16)
+  #define DDRDATA6CH0_CR_TXPERBITRANK1_Lane4_WID                       ( 4)
+  #define DDRDATA6CH0_CR_TXPERBITRANK1_Lane4_MSK                       (0x000F0000)
+  #define DDRDATA6CH0_CR_TXPERBITRANK1_Lane4_MAX                       (0x0000000F)
+  #define DDRDATA6CH0_CR_TXPERBITRANK1_Lane5_OFF                       (20)
+  #define DDRDATA6CH0_CR_TXPERBITRANK1_Lane5_WID                       ( 4)
+  #define DDRDATA6CH0_CR_TXPERBITRANK1_Lane5_MSK                       (0x00F00000)
+  #define DDRDATA6CH0_CR_TXPERBITRANK1_Lane5_MAX                       (0x0000000F)
+  #define DDRDATA6CH0_CR_TXPERBITRANK1_Lane6_OFF                       (24)
+  #define DDRDATA6CH0_CR_TXPERBITRANK1_Lane6_WID                       ( 4)
+  #define DDRDATA6CH0_CR_TXPERBITRANK1_Lane6_MSK                       (0x0F000000)
+  #define DDRDATA6CH0_CR_TXPERBITRANK1_Lane6_MAX                       (0x0000000F)
+  #define DDRDATA6CH0_CR_TXPERBITRANK1_Lane7_OFF                       (28)
+  #define DDRDATA6CH0_CR_TXPERBITRANK1_Lane7_WID                       ( 4)
+  #define DDRDATA6CH0_CR_TXPERBITRANK1_Lane7_MSK                       (0xF0000000)
+  #define DDRDATA6CH0_CR_TXPERBITRANK1_Lane7_MAX                       (0x0000000F)
+
+#define DDRDATA6CH0_CR_TXPERBITRANK2_REG                             (0x00000C38)
+  #define DDRDATA6CH0_CR_TXPERBITRANK2_Lane0_OFF                       ( 0)
+  #define DDRDATA6CH0_CR_TXPERBITRANK2_Lane0_WID                       ( 4)
+  #define DDRDATA6CH0_CR_TXPERBITRANK2_Lane0_MSK                       (0x0000000F)
+  #define DDRDATA6CH0_CR_TXPERBITRANK2_Lane0_MAX                       (0x0000000F)
+  #define DDRDATA6CH0_CR_TXPERBITRANK2_Lane1_OFF                       ( 4)
+  #define DDRDATA6CH0_CR_TXPERBITRANK2_Lane1_WID                       ( 4)
+  #define DDRDATA6CH0_CR_TXPERBITRANK2_Lane1_MSK                       (0x000000F0)
+  #define DDRDATA6CH0_CR_TXPERBITRANK2_Lane1_MAX                       (0x0000000F)
+  #define DDRDATA6CH0_CR_TXPERBITRANK2_Lane2_OFF                       ( 8)
+  #define DDRDATA6CH0_CR_TXPERBITRANK2_Lane2_WID                       ( 4)
+  #define DDRDATA6CH0_CR_TXPERBITRANK2_Lane2_MSK                       (0x00000F00)
+  #define DDRDATA6CH0_CR_TXPERBITRANK2_Lane2_MAX                       (0x0000000F)
+  #define DDRDATA6CH0_CR_TXPERBITRANK2_Lane3_OFF                       (12)
+  #define DDRDATA6CH0_CR_TXPERBITRANK2_Lane3_WID                       ( 4)
+  #define DDRDATA6CH0_CR_TXPERBITRANK2_Lane3_MSK                       (0x0000F000)
+  #define DDRDATA6CH0_CR_TXPERBITRANK2_Lane3_MAX                       (0x0000000F)
+  #define DDRDATA6CH0_CR_TXPERBITRANK2_Lane4_OFF                       (16)
+  #define DDRDATA6CH0_CR_TXPERBITRANK2_Lane4_WID                       ( 4)
+  #define DDRDATA6CH0_CR_TXPERBITRANK2_Lane4_MSK                       (0x000F0000)
+  #define DDRDATA6CH0_CR_TXPERBITRANK2_Lane4_MAX                       (0x0000000F)
+  #define DDRDATA6CH0_CR_TXPERBITRANK2_Lane5_OFF                       (20)
+  #define DDRDATA6CH0_CR_TXPERBITRANK2_Lane5_WID                       ( 4)
+  #define DDRDATA6CH0_CR_TXPERBITRANK2_Lane5_MSK                       (0x00F00000)
+  #define DDRDATA6CH0_CR_TXPERBITRANK2_Lane5_MAX                       (0x0000000F)
+  #define DDRDATA6CH0_CR_TXPERBITRANK2_Lane6_OFF                       (24)
+  #define DDRDATA6CH0_CR_TXPERBITRANK2_Lane6_WID                       ( 4)
+  #define DDRDATA6CH0_CR_TXPERBITRANK2_Lane6_MSK                       (0x0F000000)
+  #define DDRDATA6CH0_CR_TXPERBITRANK2_Lane6_MAX                       (0x0000000F)
+  #define DDRDATA6CH0_CR_TXPERBITRANK2_Lane7_OFF                       (28)
+  #define DDRDATA6CH0_CR_TXPERBITRANK2_Lane7_WID                       ( 4)
+  #define DDRDATA6CH0_CR_TXPERBITRANK2_Lane7_MSK                       (0xF0000000)
+  #define DDRDATA6CH0_CR_TXPERBITRANK2_Lane7_MAX                       (0x0000000F)
+
+#define DDRDATA6CH0_CR_TXPERBITRANK3_REG                             (0x00000C3C)
+  #define DDRDATA6CH0_CR_TXPERBITRANK3_Lane0_OFF                       ( 0)
+  #define DDRDATA6CH0_CR_TXPERBITRANK3_Lane0_WID                       ( 4)
+  #define DDRDATA6CH0_CR_TXPERBITRANK3_Lane0_MSK                       (0x0000000F)
+  #define DDRDATA6CH0_CR_TXPERBITRANK3_Lane0_MAX                       (0x0000000F)
+  #define DDRDATA6CH0_CR_TXPERBITRANK3_Lane1_OFF                       ( 4)
+  #define DDRDATA6CH0_CR_TXPERBITRANK3_Lane1_WID                       ( 4)
+  #define DDRDATA6CH0_CR_TXPERBITRANK3_Lane1_MSK                       (0x000000F0)
+  #define DDRDATA6CH0_CR_TXPERBITRANK3_Lane1_MAX                       (0x0000000F)
+  #define DDRDATA6CH0_CR_TXPERBITRANK3_Lane2_OFF                       ( 8)
+  #define DDRDATA6CH0_CR_TXPERBITRANK3_Lane2_WID                       ( 4)
+  #define DDRDATA6CH0_CR_TXPERBITRANK3_Lane2_MSK                       (0x00000F00)
+  #define DDRDATA6CH0_CR_TXPERBITRANK3_Lane2_MAX                       (0x0000000F)
+  #define DDRDATA6CH0_CR_TXPERBITRANK3_Lane3_OFF                       (12)
+  #define DDRDATA6CH0_CR_TXPERBITRANK3_Lane3_WID                       ( 4)
+  #define DDRDATA6CH0_CR_TXPERBITRANK3_Lane3_MSK                       (0x0000F000)
+  #define DDRDATA6CH0_CR_TXPERBITRANK3_Lane3_MAX                       (0x0000000F)
+  #define DDRDATA6CH0_CR_TXPERBITRANK3_Lane4_OFF                       (16)
+  #define DDRDATA6CH0_CR_TXPERBITRANK3_Lane4_WID                       ( 4)
+  #define DDRDATA6CH0_CR_TXPERBITRANK3_Lane4_MSK                       (0x000F0000)
+  #define DDRDATA6CH0_CR_TXPERBITRANK3_Lane4_MAX                       (0x0000000F)
+  #define DDRDATA6CH0_CR_TXPERBITRANK3_Lane5_OFF                       (20)
+  #define DDRDATA6CH0_CR_TXPERBITRANK3_Lane5_WID                       ( 4)
+  #define DDRDATA6CH0_CR_TXPERBITRANK3_Lane5_MSK                       (0x00F00000)
+  #define DDRDATA6CH0_CR_TXPERBITRANK3_Lane5_MAX                       (0x0000000F)
+  #define DDRDATA6CH0_CR_TXPERBITRANK3_Lane6_OFF                       (24)
+  #define DDRDATA6CH0_CR_TXPERBITRANK3_Lane6_WID                       ( 4)
+  #define DDRDATA6CH0_CR_TXPERBITRANK3_Lane6_MSK                       (0x0F000000)
+  #define DDRDATA6CH0_CR_TXPERBITRANK3_Lane6_MAX                       (0x0000000F)
+  #define DDRDATA6CH0_CR_TXPERBITRANK3_Lane7_OFF                       (28)
+  #define DDRDATA6CH0_CR_TXPERBITRANK3_Lane7_WID                       ( 4)
+  #define DDRDATA6CH0_CR_TXPERBITRANK3_Lane7_MSK                       (0xF0000000)
+  #define DDRDATA6CH0_CR_TXPERBITRANK3_Lane7_MAX                       (0x0000000F)
+
+#define DDRDATA6CH0_CR_RCOMPDATA0_REG                                (0x00000C40)
+  #define DDRDATA6CH0_CR_RCOMPDATA0_RcompDrvUp_OFF                     ( 0)
+  #define DDRDATA6CH0_CR_RCOMPDATA0_RcompDrvUp_WID                     ( 6)
+  #define DDRDATA6CH0_CR_RCOMPDATA0_RcompDrvUp_MSK                     (0x0000003F)
+  #define DDRDATA6CH0_CR_RCOMPDATA0_RcompDrvUp_MAX                     (0x0000003F)
+  #define DDRDATA6CH0_CR_RCOMPDATA0_Spare0_OFF                         ( 6)
+  #define DDRDATA6CH0_CR_RCOMPDATA0_Spare0_WID                         ( 3)
+  #define DDRDATA6CH0_CR_RCOMPDATA0_Spare0_MSK                         (0x000001C0)
+  #define DDRDATA6CH0_CR_RCOMPDATA0_Spare0_MAX                         (0x00000007)
+  #define DDRDATA6CH0_CR_RCOMPDATA0_RcompDrvDown_OFF                   ( 9)
+  #define DDRDATA6CH0_CR_RCOMPDATA0_RcompDrvDown_WID                   ( 6)
+  #define DDRDATA6CH0_CR_RCOMPDATA0_RcompDrvDown_MSK                   (0x00007E00)
+  #define DDRDATA6CH0_CR_RCOMPDATA0_RcompDrvDown_MAX                   (0x0000003F)
+  #define DDRDATA6CH0_CR_RCOMPDATA0_VTComp_OFF                         (15)
+  #define DDRDATA6CH0_CR_RCOMPDATA0_VTComp_WID                         ( 5)
+  #define DDRDATA6CH0_CR_RCOMPDATA0_VTComp_MSK                         (0x000F8000)
+  #define DDRDATA6CH0_CR_RCOMPDATA0_VTComp_MAX                         (0x0000001F)
+  #define DDRDATA6CH0_CR_RCOMPDATA0_TcoComp_OFF                        (20)
+  #define DDRDATA6CH0_CR_RCOMPDATA0_TcoComp_WID                        ( 6)
+  #define DDRDATA6CH0_CR_RCOMPDATA0_TcoComp_MSK                        (0x03F00000)
+  #define DDRDATA6CH0_CR_RCOMPDATA0_TcoComp_MAX                        (0x0000003F)
+  #define DDRDATA6CH0_CR_RCOMPDATA0_SlewRateComp_OFF                   (26)
+  #define DDRDATA6CH0_CR_RCOMPDATA0_SlewRateComp_WID                   ( 5)
+  #define DDRDATA6CH0_CR_RCOMPDATA0_SlewRateComp_MSK                   (0x7C000000)
+  #define DDRDATA6CH0_CR_RCOMPDATA0_SlewRateComp_MAX                   (0x0000001F)
+  #define DDRDATA6CH0_CR_RCOMPDATA0_Spare2_OFF                         (31)
+  #define DDRDATA6CH0_CR_RCOMPDATA0_Spare2_WID                         ( 1)
+  #define DDRDATA6CH0_CR_RCOMPDATA0_Spare2_MSK                         (0x80000000)
+  #define DDRDATA6CH0_CR_RCOMPDATA0_Spare2_MAX                         (0x00000001)
+
+#define DDRDATA6CH0_CR_RCOMPDATA1_REG                                (0x00000C44)
+  #define DDRDATA6CH0_CR_RCOMPDATA1_RcompOdtUp_OFF                     ( 0)
+  #define DDRDATA6CH0_CR_RCOMPDATA1_RcompOdtUp_WID                     ( 6)
+  #define DDRDATA6CH0_CR_RCOMPDATA1_RcompOdtUp_MSK                     (0x0000003F)
+  #define DDRDATA6CH0_CR_RCOMPDATA1_RcompOdtUp_MAX                     (0x0000003F)
+  #define DDRDATA6CH0_CR_RCOMPDATA1_Spare0_OFF                         ( 6)
+  #define DDRDATA6CH0_CR_RCOMPDATA1_Spare0_WID                         ( 3)
+  #define DDRDATA6CH0_CR_RCOMPDATA1_Spare0_MSK                         (0x000001C0)
+  #define DDRDATA6CH0_CR_RCOMPDATA1_Spare0_MAX                         (0x00000007)
+  #define DDRDATA6CH0_CR_RCOMPDATA1_RcompOdtDown_OFF                   ( 9)
+  #define DDRDATA6CH0_CR_RCOMPDATA1_RcompOdtDown_WID                   ( 6)
+  #define DDRDATA6CH0_CR_RCOMPDATA1_RcompOdtDown_MSK                   (0x00007E00)
+  #define DDRDATA6CH0_CR_RCOMPDATA1_RcompOdtDown_MAX                   (0x0000003F)
+  #define DDRDATA6CH0_CR_RCOMPDATA1_Spare1_OFF                         (15)
+  #define DDRDATA6CH0_CR_RCOMPDATA1_Spare1_WID                         ( 1)
+  #define DDRDATA6CH0_CR_RCOMPDATA1_Spare1_MSK                         (0x00008000)
+  #define DDRDATA6CH0_CR_RCOMPDATA1_Spare1_MAX                         (0x00000001)
+  #define DDRDATA6CH0_CR_RCOMPDATA1_PanicDrvDn_OFF                     (16)
+  #define DDRDATA6CH0_CR_RCOMPDATA1_PanicDrvDn_WID                     ( 6)
+  #define DDRDATA6CH0_CR_RCOMPDATA1_PanicDrvDn_MSK                     (0x003F0000)
+  #define DDRDATA6CH0_CR_RCOMPDATA1_PanicDrvDn_MAX                     (0x0000003F)
+  #define DDRDATA6CH0_CR_RCOMPDATA1_PanicDrvUp_OFF                     (22)
+  #define DDRDATA6CH0_CR_RCOMPDATA1_PanicDrvUp_WID                     ( 6)
+  #define DDRDATA6CH0_CR_RCOMPDATA1_PanicDrvUp_MSK                     (0x0FC00000)
+  #define DDRDATA6CH0_CR_RCOMPDATA1_PanicDrvUp_MAX                     (0x0000003F)
+  #define DDRDATA6CH0_CR_RCOMPDATA1_LevelShifterComp_OFF               (28)
+  #define DDRDATA6CH0_CR_RCOMPDATA1_LevelShifterComp_WID               ( 3)
+  #define DDRDATA6CH0_CR_RCOMPDATA1_LevelShifterComp_MSK               (0x70000000)
+  #define DDRDATA6CH0_CR_RCOMPDATA1_LevelShifterComp_MAX               (0x00000007)
+  #define DDRDATA6CH0_CR_RCOMPDATA1_Spare2_OFF                         (31)
+  #define DDRDATA6CH0_CR_RCOMPDATA1_Spare2_WID                         ( 1)
+  #define DDRDATA6CH0_CR_RCOMPDATA1_Spare2_MSK                         (0x80000000)
+  #define DDRDATA6CH0_CR_RCOMPDATA1_Spare2_MAX                         (0x00000001)
+
+#define DDRDATA6CH0_CR_TXXTALK_REG                                   (0x00000C48)
+  #define DDRDATA6CH0_CR_TXXTALK_Lane0_OFF                             ( 0)
+  #define DDRDATA6CH0_CR_TXXTALK_Lane0_WID                             ( 4)
+  #define DDRDATA6CH0_CR_TXXTALK_Lane0_MSK                             (0x0000000F)
+  #define DDRDATA6CH0_CR_TXXTALK_Lane0_MAX                             (0x0000000F)
+  #define DDRDATA6CH0_CR_TXXTALK_Lane1_OFF                             ( 4)
+  #define DDRDATA6CH0_CR_TXXTALK_Lane1_WID                             ( 4)
+  #define DDRDATA6CH0_CR_TXXTALK_Lane1_MSK                             (0x000000F0)
+  #define DDRDATA6CH0_CR_TXXTALK_Lane1_MAX                             (0x0000000F)
+  #define DDRDATA6CH0_CR_TXXTALK_Lane2_OFF                             ( 8)
+  #define DDRDATA6CH0_CR_TXXTALK_Lane2_WID                             ( 4)
+  #define DDRDATA6CH0_CR_TXXTALK_Lane2_MSK                             (0x00000F00)
+  #define DDRDATA6CH0_CR_TXXTALK_Lane2_MAX                             (0x0000000F)
+  #define DDRDATA6CH0_CR_TXXTALK_Lane3_OFF                             (12)
+  #define DDRDATA6CH0_CR_TXXTALK_Lane3_WID                             ( 4)
+  #define DDRDATA6CH0_CR_TXXTALK_Lane3_MSK                             (0x0000F000)
+  #define DDRDATA6CH0_CR_TXXTALK_Lane3_MAX                             (0x0000000F)
+  #define DDRDATA6CH0_CR_TXXTALK_Lane4_OFF                             (16)
+  #define DDRDATA6CH0_CR_TXXTALK_Lane4_WID                             ( 4)
+  #define DDRDATA6CH0_CR_TXXTALK_Lane4_MSK                             (0x000F0000)
+  #define DDRDATA6CH0_CR_TXXTALK_Lane4_MAX                             (0x0000000F)
+  #define DDRDATA6CH0_CR_TXXTALK_Lane5_OFF                             (20)
+  #define DDRDATA6CH0_CR_TXXTALK_Lane5_WID                             ( 4)
+  #define DDRDATA6CH0_CR_TXXTALK_Lane5_MSK                             (0x00F00000)
+  #define DDRDATA6CH0_CR_TXXTALK_Lane5_MAX                             (0x0000000F)
+  #define DDRDATA6CH0_CR_TXXTALK_Lane6_OFF                             (24)
+  #define DDRDATA6CH0_CR_TXXTALK_Lane6_WID                             ( 4)
+  #define DDRDATA6CH0_CR_TXXTALK_Lane6_MSK                             (0x0F000000)
+  #define DDRDATA6CH0_CR_TXXTALK_Lane6_MAX                             (0x0000000F)
+  #define DDRDATA6CH0_CR_TXXTALK_Lane7_OFF                             (28)
+  #define DDRDATA6CH0_CR_TXXTALK_Lane7_WID                             ( 4)
+  #define DDRDATA6CH0_CR_TXXTALK_Lane7_MSK                             (0xF0000000)
+  #define DDRDATA6CH0_CR_TXXTALK_Lane7_MAX                             (0x0000000F)
+
+#define DDRDATA6CH0_CR_RXOFFSETVDQ_REG                               (0x00000C4C)
+  #define DDRDATA6CH0_CR_RXOFFSETVDQ_Lane0_OFF                         ( 0)
+  #define DDRDATA6CH0_CR_RXOFFSETVDQ_Lane0_WID                         ( 4)
+  #define DDRDATA6CH0_CR_RXOFFSETVDQ_Lane0_MSK                         (0x0000000F)
+  #define DDRDATA6CH0_CR_RXOFFSETVDQ_Lane0_MAX                         (0x0000000F)
+  #define DDRDATA6CH0_CR_RXOFFSETVDQ_Lane1_OFF                         ( 4)
+  #define DDRDATA6CH0_CR_RXOFFSETVDQ_Lane1_WID                         ( 4)
+  #define DDRDATA6CH0_CR_RXOFFSETVDQ_Lane1_MSK                         (0x000000F0)
+  #define DDRDATA6CH0_CR_RXOFFSETVDQ_Lane1_MAX                         (0x0000000F)
+  #define DDRDATA6CH0_CR_RXOFFSETVDQ_Lane2_OFF                         ( 8)
+  #define DDRDATA6CH0_CR_RXOFFSETVDQ_Lane2_WID                         ( 4)
+  #define DDRDATA6CH0_CR_RXOFFSETVDQ_Lane2_MSK                         (0x00000F00)
+  #define DDRDATA6CH0_CR_RXOFFSETVDQ_Lane2_MAX                         (0x0000000F)
+  #define DDRDATA6CH0_CR_RXOFFSETVDQ_Lane3_OFF                         (12)
+  #define DDRDATA6CH0_CR_RXOFFSETVDQ_Lane3_WID                         ( 4)
+  #define DDRDATA6CH0_CR_RXOFFSETVDQ_Lane3_MSK                         (0x0000F000)
+  #define DDRDATA6CH0_CR_RXOFFSETVDQ_Lane3_MAX                         (0x0000000F)
+  #define DDRDATA6CH0_CR_RXOFFSETVDQ_Lane4_OFF                         (16)
+  #define DDRDATA6CH0_CR_RXOFFSETVDQ_Lane4_WID                         ( 4)
+  #define DDRDATA6CH0_CR_RXOFFSETVDQ_Lane4_MSK                         (0x000F0000)
+  #define DDRDATA6CH0_CR_RXOFFSETVDQ_Lane4_MAX                         (0x0000000F)
+  #define DDRDATA6CH0_CR_RXOFFSETVDQ_Lane5_OFF                         (20)
+  #define DDRDATA6CH0_CR_RXOFFSETVDQ_Lane5_WID                         ( 4)
+  #define DDRDATA6CH0_CR_RXOFFSETVDQ_Lane5_MSK                         (0x00F00000)
+  #define DDRDATA6CH0_CR_RXOFFSETVDQ_Lane5_MAX                         (0x0000000F)
+  #define DDRDATA6CH0_CR_RXOFFSETVDQ_Lane6_OFF                         (24)
+  #define DDRDATA6CH0_CR_RXOFFSETVDQ_Lane6_WID                         ( 4)
+  #define DDRDATA6CH0_CR_RXOFFSETVDQ_Lane6_MSK                         (0x0F000000)
+  #define DDRDATA6CH0_CR_RXOFFSETVDQ_Lane6_MAX                         (0x0000000F)
+  #define DDRDATA6CH0_CR_RXOFFSETVDQ_Lane7_OFF                         (28)
+  #define DDRDATA6CH0_CR_RXOFFSETVDQ_Lane7_WID                         ( 4)
+  #define DDRDATA6CH0_CR_RXOFFSETVDQ_Lane7_MSK                         (0xF0000000)
+  #define DDRDATA6CH0_CR_RXOFFSETVDQ_Lane7_MAX                         (0x0000000F)
+
+#define DDRDATA6CH0_CR_DDRDATARESERVED_REG                           (0x00000C50)
+  #define DDRDATA6CH0_CR_DDRDATARESERVED_Spare_OFF                     ( 0)
+  #define DDRDATA6CH0_CR_DDRDATARESERVED_Spare_WID                     (32)
+  #define DDRDATA6CH0_CR_DDRDATARESERVED_Spare_MSK                     (0xFFFFFFFF)
+  #define DDRDATA6CH0_CR_DDRDATARESERVED_Spare_MAX                     (0xFFFFFFFF)
+
+#define DDRDATA6CH0_CR_DATATRAINFEEDBACK_REG                         (0x00000C54)
+  #define DDRDATA6CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_OFF       ( 0)
+  #define DDRDATA6CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_WID       ( 9)
+  #define DDRDATA6CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_MSK       (0x000001FF)
+  #define DDRDATA6CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_MAX       (0x000001FF)
+  #define DDRDATA6CH0_CR_DATATRAINFEEDBACK_Spare_OFF                   ( 9)
+  #define DDRDATA6CH0_CR_DATATRAINFEEDBACK_Spare_WID                   (23)
+  #define DDRDATA6CH0_CR_DATATRAINFEEDBACK_Spare_MSK                   (0xFFFFFE00)
+  #define DDRDATA6CH0_CR_DATATRAINFEEDBACK_Spare_MAX                   (0x007FFFFF)
+
+#define DDRDATA6CH0_CR_DLLPITESTANDADC_REG                           (0x00000C58)
+  #define DDRDATA6CH0_CR_DLLPITESTANDADC_RunTest_OFF                   ( 0)
+  #define DDRDATA6CH0_CR_DLLPITESTANDADC_RunTest_WID                   ( 1)
+  #define DDRDATA6CH0_CR_DLLPITESTANDADC_RunTest_MSK                   (0x00000001)
+  #define DDRDATA6CH0_CR_DLLPITESTANDADC_RunTest_MAX                   (0x00000001)
+  #define DDRDATA6CH0_CR_DLLPITESTANDADC_RunTest_DEF                   (0x00000000)
+  #define DDRDATA6CH0_CR_DLLPITESTANDADC_Load_OFF                      ( 1)
+  #define DDRDATA6CH0_CR_DLLPITESTANDADC_Load_WID                      ( 1)
+  #define DDRDATA6CH0_CR_DLLPITESTANDADC_Load_MSK                      (0x00000002)
+  #define DDRDATA6CH0_CR_DLLPITESTANDADC_Load_MAX                      (0x00000001)
+  #define DDRDATA6CH0_CR_DLLPITESTANDADC_Load_DEF                      (0x00000000)
+  #define DDRDATA6CH0_CR_DLLPITESTANDADC_ModeHVM_OFF                   ( 2)
+  #define DDRDATA6CH0_CR_DLLPITESTANDADC_ModeHVM_WID                   ( 1)
+  #define DDRDATA6CH0_CR_DLLPITESTANDADC_ModeHVM_MSK                   (0x00000004)
+  #define DDRDATA6CH0_CR_DLLPITESTANDADC_ModeHVM_MAX                   (0x00000001)
+  #define DDRDATA6CH0_CR_DLLPITESTANDADC_ModeHVM_DEF                   (0x00000000)
+  #define DDRDATA6CH0_CR_DLLPITESTANDADC_ModeDV_OFF                    ( 3)
+  #define DDRDATA6CH0_CR_DLLPITESTANDADC_ModeDV_WID                    ( 1)
+  #define DDRDATA6CH0_CR_DLLPITESTANDADC_ModeDV_MSK                    (0x00000008)
+  #define DDRDATA6CH0_CR_DLLPITESTANDADC_ModeDV_MAX                    (0x00000001)
+  #define DDRDATA6CH0_CR_DLLPITESTANDADC_ModeDV_DEF                    (0x00000000)
+  #define DDRDATA6CH0_CR_DLLPITESTANDADC_ModeADC_OFF                   ( 4)
+  #define DDRDATA6CH0_CR_DLLPITESTANDADC_ModeADC_WID                   ( 1)
+  #define DDRDATA6CH0_CR_DLLPITESTANDADC_ModeADC_MSK                   (0x00000010)
+  #define DDRDATA6CH0_CR_DLLPITESTANDADC_ModeADC_MAX                   (0x00000001)
+  #define DDRDATA6CH0_CR_DLLPITESTANDADC_ModeADC_DEF                   (0x00000000)
+  #define DDRDATA6CH0_CR_DLLPITESTANDADC_LoadCount_OFF                 ( 5)
+  #define DDRDATA6CH0_CR_DLLPITESTANDADC_LoadCount_WID                 (10)
+  #define DDRDATA6CH0_CR_DLLPITESTANDADC_LoadCount_MSK                 (0x00007FE0)
+  #define DDRDATA6CH0_CR_DLLPITESTANDADC_LoadCount_MAX                 (0x000003FF)
+  #define DDRDATA6CH0_CR_DLLPITESTANDADC_CountStatus_OFF               (15)
+  #define DDRDATA6CH0_CR_DLLPITESTANDADC_CountStatus_WID               (10)
+  #define DDRDATA6CH0_CR_DLLPITESTANDADC_CountStatus_MSK               (0x01FF8000)
+  #define DDRDATA6CH0_CR_DLLPITESTANDADC_CountStatus_MAX               (0x000003FF)
+  #define DDRDATA6CH0_CR_DLLPITESTANDADC_CountStatus_DEF               (0x00000000)
+  #define DDRDATA6CH0_CR_DLLPITESTANDADC_Spare_OFF                     (25)
+  #define DDRDATA6CH0_CR_DLLPITESTANDADC_Spare_WID                     ( 7)
+  #define DDRDATA6CH0_CR_DLLPITESTANDADC_Spare_MSK                     (0xFE000000)
+  #define DDRDATA6CH0_CR_DLLPITESTANDADC_Spare_MAX                     (0x0000007F)
+
+#define DDRDATA6CH0_CR_DDRCRDATAOFFSETCOMP_REG                       (0x00000C5C)
+  #define DDRDATA6CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_OFF     ( 0)
+  #define DDRDATA6CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_WID     ( 6)
+  #define DDRDATA6CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MSK     (0x0000003F)
+  #define DDRDATA6CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MAX     (0x0000003F)
+  #define DDRDATA6CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_DEF     (0x00000000)
+  #define DDRDATA6CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_OFF   ( 6)
+  #define DDRDATA6CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_WID   ( 6)
+  #define DDRDATA6CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MSK   (0x00000FC0)
+  #define DDRDATA6CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MAX   (0x0000003F)
+  #define DDRDATA6CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_DEF   (0x00000000)
+  #define DDRDATA6CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_OFF     (12)
+  #define DDRDATA6CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_WID     ( 5)
+  #define DDRDATA6CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MSK     (0x0001F000)
+  #define DDRDATA6CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MAX     (0x0000001F)
+  #define DDRDATA6CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_DEF     (0x00000000)
+  #define DDRDATA6CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_OFF   (17)
+  #define DDRDATA6CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_WID   ( 5)
+  #define DDRDATA6CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MSK   (0x003E0000)
+  #define DDRDATA6CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MAX   (0x0000001F)
+  #define DDRDATA6CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_DEF   (0x00000000)
+  #define DDRDATA6CH0_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_OFF       (22)
+  #define DDRDATA6CH0_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_WID       ( 5)
+  #define DDRDATA6CH0_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_MSK       (0x07C00000)
+  #define DDRDATA6CH0_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_MAX       (0x0000001F)
+  #define DDRDATA6CH0_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_DEF       (0x00000000)
+  #define DDRDATA6CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_OFF  (27)
+  #define DDRDATA6CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_WID  ( 5)
+  #define DDRDATA6CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MSK  (0xF8000000)
+  #define DDRDATA6CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MAX  (0x0000001F)
+  #define DDRDATA6CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_DEF  (0x00000000)
+
+#define DDRDATA6CH0_CR_DDRCRDATACONTROL1_REG                         (0x00000C60)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_RefPi_OFF                   ( 0)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_RefPi_WID                   ( 4)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_RefPi_MSK                   (0x0000000F)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_RefPi_MAX                   (0x0000000F)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_RefPi_DEF                   (0x00000000)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_DllMask_OFF                 ( 4)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_DllMask_WID                 ( 2)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_DllMask_MSK                 (0x00000030)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_DllMask_MAX                 (0x00000003)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_DllMask_DEF                 (0x00000000)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_DllWeakLock_OFF             ( 6)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_DllWeakLock_WID             ( 1)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_DllWeakLock_MSK             (0x00000040)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_DllWeakLock_MAX             (0x00000001)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_DllWeakLock_DEF             (0x00000000)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_OFF      ( 7)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_WID      ( 3)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MSK      (0x00000380)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MAX      (0x00000007)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_DEF      (0x00000000)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_OFF               (10)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_WID               ( 3)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_MSK               (0x00001C00)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_MAX               (0x00000007)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_DEF               (0x00000000)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_OdtDelay_OFF                (13)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_OdtDelay_WID                ( 4)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_OdtDelay_MSK                (0x0001E000)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_OdtDelay_MAX                (0x0000000F)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_OdtDelay_DEF                (0x00000000)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_OdtDuration_OFF             (17)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_OdtDuration_WID             ( 3)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_OdtDuration_MSK             (0x000E0000)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_OdtDuration_MAX             (0x00000007)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_OdtDuration_DEF             (0x00000000)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_OFF           (20)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_WID           ( 4)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_MSK           (0x00F00000)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_MAX           (0x0000000F)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_DEF           (0x00000000)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_OFF        (24)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_WID        ( 3)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_MSK        (0x07000000)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_MAX        (0x00000007)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_DEF        (0x00000000)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_BurstEndODTDelay_OFF        (27)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_BurstEndODTDelay_WID        ( 3)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_BurstEndODTDelay_MSK        (0x38000000)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_BurstEndODTDelay_MAX        (0x00000007)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_BurstEndODTDelay_DEF        (0x00000000)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_OFF          (30)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_WID          ( 1)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_MSK          (0x40000000)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_MAX          (0x00000001)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_DEF          (0x00000000)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_Rsvd1_OFF                   (31)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_Rsvd1_WID                   ( 1)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_Rsvd1_MSK                   (0x80000000)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_Rsvd1_MAX                   (0x00000001)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_Rsvd1_DEF                   (0x00000000)
+
+#define DDRDATA6CH0_CR_DDRCRDATACONTROL2_REG                         (0x00000C64)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_OFF            ( 0)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_WID            ( 5)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_MSK            (0x0000001F)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_MAX            (0x0000001F)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_DEF            (0x00000000)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_OFF             ( 5)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_WID             ( 1)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_MSK             (0x00000020)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_MAX             (0x00000001)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_DEF             (0x00000000)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_ForceRxOn_OFF               ( 6)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_ForceRxOn_WID               ( 1)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_ForceRxOn_MSK               (0x00000040)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_ForceRxOn_MAX               (0x00000001)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_ForceRxOn_DEF               (0x00000000)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_LeakerComp_OFF              ( 7)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_LeakerComp_WID              ( 2)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_LeakerComp_MSK              (0x00000180)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_LeakerComp_MAX              (0x00000003)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_LeakerComp_DEF              (0x00000000)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_OFF          ( 9)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_WID          ( 4)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_MSK          (0x00001E00)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_MAX          (0x0000000F)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_DEF          (0x00000008)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_OFF             (13)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_WID             ( 5)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_MSK             (0x0003E000)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_MAX             (0x0000001F)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_DEF             (0x00000011)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_OFF             (18)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_WID             ( 1)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_MSK             (0x00040000)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_MAX             (0x00000001)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_DEF             (0x00000000)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_Spare_OFF                   (19)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_Spare_WID                   (13)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_Spare_MSK                   (0xFFF80000)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_Spare_MAX                   (0x00001FFF)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_Spare_DEF                   (0x00000000)
+
+#define DDRDATA6CH0_CR_DDRCRVSSHIORVREFCONTROL_REG                   (0x00000C6C)
+  #define DDRDATA6CH0_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_OFF    ( 0)
+  #define DDRDATA6CH0_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_WID    (24)
+  #define DDRDATA6CH0_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_MSK    (0x00FFFFFF)
+  #define DDRDATA6CH0_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_MAX    (0x00FFFFFF)
+  #define DDRDATA6CH0_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_DEF    (0x00000000)
+  #define DDRDATA6CH0_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_OFF        (24)
+  #define DDRDATA6CH0_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_WID        ( 8)
+  #define DDRDATA6CH0_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_MSK        (0xFF000000)
+  #define DDRDATA6CH0_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_MAX        (0x000000FF)
+  #define DDRDATA6CH0_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_DEF        (0x00000000)
+
+#define DDRDATA6CH0_CR_DDRCRDATAOFFSETTRAIN_REG                      (0x00000C70)
+  #define DDRDATA6CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_OFF          ( 0)
+  #define DDRDATA6CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_WID          ( 6)
+  #define DDRDATA6CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MSK          (0x0000003F)
+  #define DDRDATA6CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MAX          (0x0000003F)
+  #define DDRDATA6CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_DEF          (0x00000000)
+  #define DDRDATA6CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_OFF          ( 6)
+  #define DDRDATA6CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_WID          ( 6)
+  #define DDRDATA6CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MSK          (0x00000FC0)
+  #define DDRDATA6CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MAX          (0x0000003F)
+  #define DDRDATA6CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_DEF          (0x00000000)
+  #define DDRDATA6CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_OFF           (12)
+  #define DDRDATA6CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_WID           ( 6)
+  #define DDRDATA6CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MSK           (0x0003F000)
+  #define DDRDATA6CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MAX           (0x0000003F)
+  #define DDRDATA6CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_DEF           (0x00000000)
+  #define DDRDATA6CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_OFF          (18)
+  #define DDRDATA6CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_WID          ( 6)
+  #define DDRDATA6CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MSK          (0x00FC0000)
+  #define DDRDATA6CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MAX          (0x0000003F)
+  #define DDRDATA6CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_DEF          (0x00000000)
+  #define DDRDATA6CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_OFF           (24)
+  #define DDRDATA6CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_WID           ( 7)
+  #define DDRDATA6CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MSK           (0x7F000000)
+  #define DDRDATA6CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MAX           (0x0000007F)
+  #define DDRDATA6CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_DEF           (0x00000000)
+  #define DDRDATA6CH0_CR_DDRCRDATAOFFSETTRAIN_Spare_OFF                (31)
+  #define DDRDATA6CH0_CR_DDRCRDATAOFFSETTRAIN_Spare_WID                ( 1)
+  #define DDRDATA6CH0_CR_DDRCRDATAOFFSETTRAIN_Spare_MSK                (0x80000000)
+  #define DDRDATA6CH0_CR_DDRCRDATAOFFSETTRAIN_Spare_MAX                (0x00000001)
+  #define DDRDATA6CH0_CR_DDRCRDATAOFFSETTRAIN_Spare_DEF                (0x00000000)
+
+#define DDRDATA6CH0_CR_DDRCRDATACONTROL0_REG                         (0x00000C74)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_OFF          ( 0)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_WID          ( 1)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_MSK          (0x00000001)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_MAX          (0x00000001)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_DEF          (0x00000000)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_OFF          ( 1)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_WID          ( 1)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_MSK          (0x00000002)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_MAX          (0x00000001)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_DEF          (0x00000000)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_OFF          ( 2)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_WID          ( 1)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_MSK          (0x00000004)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_MAX          (0x00000001)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_DEF          (0x00000000)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_OFF    ( 3)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_WID    ( 1)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MSK    (0x00000008)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MAX    (0x00000001)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_DEF    (0x00000000)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_TxOn_OFF                    ( 4)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_TxOn_WID                    ( 1)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_TxOn_MSK                    (0x00000010)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_TxOn_MAX                    (0x00000001)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_TxOn_DEF                    (0x00000000)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RfOn_OFF                    ( 5)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RfOn_WID                    ( 1)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RfOn_MSK                    (0x00000020)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RfOn_MAX                    (0x00000001)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RfOn_DEF                    (0x00000000)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RxPiOn_OFF                  ( 6)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RxPiOn_WID                  ( 1)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RxPiOn_MSK                  (0x00000040)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RxPiOn_MAX                  (0x00000001)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RxPiOn_DEF                  (0x00000000)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_TxPiOn_OFF                  ( 7)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_TxPiOn_WID                  ( 1)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_TxPiOn_MSK                  (0x00000080)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_TxPiOn_MAX                  (0x00000001)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_TxPiOn_DEF                  (0x00000000)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_OFF        ( 8)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_WID        ( 1)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_MSK        (0x00000100)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_MAX        (0x00000001)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_DEF        (0x00000000)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_OFF        ( 9)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_WID        ( 1)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MSK        (0x00000200)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MAX        (0x00000001)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_DEF        (0x00000000)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_TxDisable_OFF               (10)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_TxDisable_WID               ( 1)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_TxDisable_MSK               (0x00000400)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_TxDisable_MAX               (0x00000001)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_TxDisable_DEF               (0x00000000)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RxDisable_OFF               (11)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RxDisable_WID               ( 1)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RxDisable_MSK               (0x00000800)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RxDisable_MAX               (0x00000001)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RxDisable_DEF               (0x00000000)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_TxLong_OFF                  (12)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_TxLong_WID                  ( 1)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_TxLong_MSK                  (0x00001000)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_TxLong_MAX                  (0x00000001)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_TxLong_DEF                  (0x00000000)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_OFF               (13)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_WID               ( 2)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_MSK               (0x00006000)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_MAX               (0x00000003)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_DEF               (0x00000000)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RxReadPointer_OFF           (15)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RxReadPointer_WID           ( 3)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RxReadPointer_MSK           (0x00038000)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RxReadPointer_MAX           (0x00000007)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RxReadPointer_DEF           (0x00000000)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_DriverSegmentEnable_OFF     (18)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_DriverSegmentEnable_WID     ( 1)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_DriverSegmentEnable_MSK     (0x00040000)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_DriverSegmentEnable_MAX     (0x00000001)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_DriverSegmentEnable_DEF     (0x00000000)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_DataVccddqHi_OFF            (19)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_DataVccddqHi_WID            ( 1)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_DataVccddqHi_MSK            (0x00080000)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_DataVccddqHi_MAX            (0x00000001)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_DataVccddqHi_DEF            (0x00000000)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_ReadRFRd_OFF                (20)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_ReadRFRd_WID                ( 1)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_ReadRFRd_MSK                (0x00100000)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_ReadRFRd_MAX                (0x00000001)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_ReadRFRd_DEF                (0x00000000)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_ReadRFWr_OFF                (21)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_ReadRFWr_WID                ( 1)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_ReadRFWr_MSK                (0x00200000)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_ReadRFWr_MAX                (0x00000001)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_ReadRFWr_DEF                (0x00000000)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_ReadRFRank_OFF              (22)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_ReadRFRank_WID              ( 2)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_ReadRFRank_MSK              (0x00C00000)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_ReadRFRank_MAX              (0x00000003)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_ReadRFRank_DEF              (0x00000000)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_OFF              (24)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_WID              ( 1)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_MSK              (0x01000000)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_MAX              (0x00000001)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_DEF              (0x00000000)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_OdtSampOff_OFF              (25)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_OdtSampOff_WID              ( 1)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_OdtSampOff_MSK              (0x02000000)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_OdtSampOff_MAX              (0x00000001)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_OdtSampOff_DEF              (0x00000000)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_OFF        (26)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_WID        ( 1)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_MSK        (0x04000000)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_MAX        (0x00000001)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_DEF        (0x00000000)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_OFF         (27)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_WID         ( 1)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MSK         (0x08000000)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MAX         (0x00000001)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_DEF         (0x00000000)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_OFF              (28)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_WID              ( 1)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_MSK              (0x10000000)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_MAX              (0x00000001)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_DEF              (0x00000000)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_EnReadPreamble_OFF          (29)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_EnReadPreamble_WID          ( 1)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_EnReadPreamble_MSK          (0x20000000)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_EnReadPreamble_MAX          (0x00000001)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_EnReadPreamble_DEF          (0x00000000)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_OFF         (30)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_WID         ( 1)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MSK         (0x40000000)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MAX         (0x00000001)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_DEF         (0x00000000)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_OFF            (31)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_WID            ( 1)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_MSK            (0x80000000)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_MAX            (0x00000001)
+  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_DEF            (0x00000000)
+
+#define DDRDATA6CH0_CR_DDRCRVREFADJUST1_REG                          (0x00000C78)
+  #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_CAVrefCtl_OFF                ( 0)
+  #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_CAVrefCtl_WID                ( 7)
+  #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_CAVrefCtl_MSK                (0x0000007F)
+  #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_CAVrefCtl_MAX                (0x0000007F)
+  #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_CAVrefCtl_DEF                (0x00000000)
+  #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_Ch1VrefCtl_OFF               ( 7)
+  #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_Ch1VrefCtl_WID               ( 7)
+  #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_Ch1VrefCtl_MSK               (0x00003F80)
+  #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_Ch1VrefCtl_MAX               (0x0000007F)
+  #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_Ch1VrefCtl_DEF               (0x00000000)
+  #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_Ch0VrefCtl_OFF               (14)
+  #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_Ch0VrefCtl_WID               ( 7)
+  #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_Ch0VrefCtl_MSK               (0x001FC000)
+  #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_Ch0VrefCtl_MAX               (0x0000007F)
+  #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_Ch0VrefCtl_DEF               (0x00000000)
+  #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCA_OFF             (21)
+  #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCA_WID             ( 1)
+  #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCA_MSK             (0x00200000)
+  #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCA_MAX             (0x00000001)
+  #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCA_DEF             (0x00000000)
+  #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_OFF            (22)
+  #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_WID            ( 1)
+  #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_MSK            (0x00400000)
+  #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_MAX            (0x00000001)
+  #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_DEF            (0x00000000)
+  #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_OFF            (23)
+  #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_WID            ( 1)
+  #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_MSK            (0x00800000)
+  #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_MAX            (0x00000001)
+  #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_DEF            (0x00000000)
+  #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_HiZTimerCtrl_OFF             (24)
+  #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_HiZTimerCtrl_WID             ( 2)
+  #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_HiZTimerCtrl_MSK             (0x03000000)
+  #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_HiZTimerCtrl_MAX             (0x00000003)
+  #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_HiZTimerCtrl_DEF             (0x00000000)
+  #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_OFF            (26)
+  #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_WID            ( 1)
+  #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_MSK            (0x04000000)
+  #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_MAX            (0x00000001)
+  #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_DEF            (0x00000000)
+  #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_Rsvd_OFF                     (27)
+  #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_Rsvd_WID                     ( 2)
+  #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_Rsvd_MSK                     (0x18000000)
+  #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_Rsvd_MAX                     (0x00000003)
+  #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_Rsvd_DEF                     (0x00000000)
+  #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_caSlowBW_OFF                 (29)
+  #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_caSlowBW_WID                 ( 1)
+  #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_caSlowBW_MSK                 (0x20000000)
+  #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_caSlowBW_MAX                 (0x00000001)
+  #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_caSlowBW_DEF                 (0x00000000)
+  #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_ch0SlowBW_OFF                (30)
+  #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_ch0SlowBW_WID                ( 1)
+  #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_ch0SlowBW_MSK                (0x40000000)
+  #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_ch0SlowBW_MAX                (0x00000001)
+  #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_ch0SlowBW_DEF                (0x00000000)
+  #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_ch1SlowBW_OFF                (31)
+  #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_ch1SlowBW_WID                ( 1)
+  #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_ch1SlowBW_MSK                (0x80000000)
+  #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_ch1SlowBW_MAX                (0x00000001)
+  #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_ch1SlowBW_DEF                (0x00000000)
+
+#define DDRDATA6CH1_CR_RXTRAINRANK0_REG                              (0x00000D00)
+  #define DDRDATA6CH1_CR_RXTRAINRANK0_RxRcvEnPi_OFF                    ( 0)
+  #define DDRDATA6CH1_CR_RXTRAINRANK0_RxRcvEnPi_WID                    ( 9)
+  #define DDRDATA6CH1_CR_RXTRAINRANK0_RxRcvEnPi_MSK                    (0x000001FF)
+  #define DDRDATA6CH1_CR_RXTRAINRANK0_RxRcvEnPi_MAX                    (0x000001FF)
+  #define DDRDATA6CH1_CR_RXTRAINRANK0_RxDqsPPi_OFF                     ( 9)
+  #define DDRDATA6CH1_CR_RXTRAINRANK0_RxDqsPPi_WID                     ( 6)
+  #define DDRDATA6CH1_CR_RXTRAINRANK0_RxDqsPPi_MSK                     (0x00007E00)
+  #define DDRDATA6CH1_CR_RXTRAINRANK0_RxDqsPPi_MAX                     (0x0000003F)
+  #define DDRDATA6CH1_CR_RXTRAINRANK0_RxEq_OFF                         (15)
+  #define DDRDATA6CH1_CR_RXTRAINRANK0_RxEq_WID                         ( 5)
+  #define DDRDATA6CH1_CR_RXTRAINRANK0_RxEq_MSK                         (0x000F8000)
+  #define DDRDATA6CH1_CR_RXTRAINRANK0_RxEq_MAX                         (0x0000001F)
+  #define DDRDATA6CH1_CR_RXTRAINRANK0_RxDqsNPi_OFF                     (20)
+  #define DDRDATA6CH1_CR_RXTRAINRANK0_RxDqsNPi_WID                     ( 6)
+  #define DDRDATA6CH1_CR_RXTRAINRANK0_RxDqsNPi_MSK                     (0x03F00000)
+  #define DDRDATA6CH1_CR_RXTRAINRANK0_RxDqsNPi_MAX                     (0x0000003F)
+  #define DDRDATA6CH1_CR_RXTRAINRANK0_RxVref_OFF                       (26)
+  #define DDRDATA6CH1_CR_RXTRAINRANK0_RxVref_WID                       ( 6)
+  #define DDRDATA6CH1_CR_RXTRAINRANK0_RxVref_MSK                       (0xFC000000)
+  #define DDRDATA6CH1_CR_RXTRAINRANK0_RxVref_MAX                       (0x0000003F)
+
+#define DDRDATA6CH1_CR_RXTRAINRANK1_REG                              (0x00000D04)
+  #define DDRDATA6CH1_CR_RXTRAINRANK1_RxRcvEnPi_OFF                    ( 0)
+  #define DDRDATA6CH1_CR_RXTRAINRANK1_RxRcvEnPi_WID                    ( 9)
+  #define DDRDATA6CH1_CR_RXTRAINRANK1_RxRcvEnPi_MSK                    (0x000001FF)
+  #define DDRDATA6CH1_CR_RXTRAINRANK1_RxRcvEnPi_MAX                    (0x000001FF)
+  #define DDRDATA6CH1_CR_RXTRAINRANK1_RxDqsPPi_OFF                     ( 9)
+  #define DDRDATA6CH1_CR_RXTRAINRANK1_RxDqsPPi_WID                     ( 6)
+  #define DDRDATA6CH1_CR_RXTRAINRANK1_RxDqsPPi_MSK                     (0x00007E00)
+  #define DDRDATA6CH1_CR_RXTRAINRANK1_RxDqsPPi_MAX                     (0x0000003F)
+  #define DDRDATA6CH1_CR_RXTRAINRANK1_RxEq_OFF                         (15)
+  #define DDRDATA6CH1_CR_RXTRAINRANK1_RxEq_WID                         ( 5)
+  #define DDRDATA6CH1_CR_RXTRAINRANK1_RxEq_MSK                         (0x000F8000)
+  #define DDRDATA6CH1_CR_RXTRAINRANK1_RxEq_MAX                         (0x0000001F)
+  #define DDRDATA6CH1_CR_RXTRAINRANK1_RxDqsNPi_OFF                     (20)
+  #define DDRDATA6CH1_CR_RXTRAINRANK1_RxDqsNPi_WID                     ( 6)
+  #define DDRDATA6CH1_CR_RXTRAINRANK1_RxDqsNPi_MSK                     (0x03F00000)
+  #define DDRDATA6CH1_CR_RXTRAINRANK1_RxDqsNPi_MAX                     (0x0000003F)
+  #define DDRDATA6CH1_CR_RXTRAINRANK1_RxVref_OFF                       (26)
+  #define DDRDATA6CH1_CR_RXTRAINRANK1_RxVref_WID                       ( 6)
+  #define DDRDATA6CH1_CR_RXTRAINRANK1_RxVref_MSK                       (0xFC000000)
+  #define DDRDATA6CH1_CR_RXTRAINRANK1_RxVref_MAX                       (0x0000003F)
+
+#define DDRDATA6CH1_CR_RXTRAINRANK2_REG                              (0x00000D08)
+  #define DDRDATA6CH1_CR_RXTRAINRANK2_RxRcvEnPi_OFF                    ( 0)
+  #define DDRDATA6CH1_CR_RXTRAINRANK2_RxRcvEnPi_WID                    ( 9)
+  #define DDRDATA6CH1_CR_RXTRAINRANK2_RxRcvEnPi_MSK                    (0x000001FF)
+  #define DDRDATA6CH1_CR_RXTRAINRANK2_RxRcvEnPi_MAX                    (0x000001FF)
+  #define DDRDATA6CH1_CR_RXTRAINRANK2_RxDqsPPi_OFF                     ( 9)
+  #define DDRDATA6CH1_CR_RXTRAINRANK2_RxDqsPPi_WID                     ( 6)
+  #define DDRDATA6CH1_CR_RXTRAINRANK2_RxDqsPPi_MSK                     (0x00007E00)
+  #define DDRDATA6CH1_CR_RXTRAINRANK2_RxDqsPPi_MAX                     (0x0000003F)
+  #define DDRDATA6CH1_CR_RXTRAINRANK2_RxEq_OFF                         (15)
+  #define DDRDATA6CH1_CR_RXTRAINRANK2_RxEq_WID                         ( 5)
+  #define DDRDATA6CH1_CR_RXTRAINRANK2_RxEq_MSK                         (0x000F8000)
+  #define DDRDATA6CH1_CR_RXTRAINRANK2_RxEq_MAX                         (0x0000001F)
+  #define DDRDATA6CH1_CR_RXTRAINRANK2_RxDqsNPi_OFF                     (20)
+  #define DDRDATA6CH1_CR_RXTRAINRANK2_RxDqsNPi_WID                     ( 6)
+  #define DDRDATA6CH1_CR_RXTRAINRANK2_RxDqsNPi_MSK                     (0x03F00000)
+  #define DDRDATA6CH1_CR_RXTRAINRANK2_RxDqsNPi_MAX                     (0x0000003F)
+  #define DDRDATA6CH1_CR_RXTRAINRANK2_RxVref_OFF                       (26)
+  #define DDRDATA6CH1_CR_RXTRAINRANK2_RxVref_WID                       ( 6)
+  #define DDRDATA6CH1_CR_RXTRAINRANK2_RxVref_MSK                       (0xFC000000)
+  #define DDRDATA6CH1_CR_RXTRAINRANK2_RxVref_MAX                       (0x0000003F)
+
+#define DDRDATA6CH1_CR_RXTRAINRANK3_REG                              (0x00000D0C)
+  #define DDRDATA6CH1_CR_RXTRAINRANK3_RxRcvEnPi_OFF                    ( 0)
+  #define DDRDATA6CH1_CR_RXTRAINRANK3_RxRcvEnPi_WID                    ( 9)
+  #define DDRDATA6CH1_CR_RXTRAINRANK3_RxRcvEnPi_MSK                    (0x000001FF)
+  #define DDRDATA6CH1_CR_RXTRAINRANK3_RxRcvEnPi_MAX                    (0x000001FF)
+  #define DDRDATA6CH1_CR_RXTRAINRANK3_RxDqsPPi_OFF                     ( 9)
+  #define DDRDATA6CH1_CR_RXTRAINRANK3_RxDqsPPi_WID                     ( 6)
+  #define DDRDATA6CH1_CR_RXTRAINRANK3_RxDqsPPi_MSK                     (0x00007E00)
+  #define DDRDATA6CH1_CR_RXTRAINRANK3_RxDqsPPi_MAX                     (0x0000003F)
+  #define DDRDATA6CH1_CR_RXTRAINRANK3_RxEq_OFF                         (15)
+  #define DDRDATA6CH1_CR_RXTRAINRANK3_RxEq_WID                         ( 5)
+  #define DDRDATA6CH1_CR_RXTRAINRANK3_RxEq_MSK                         (0x000F8000)
+  #define DDRDATA6CH1_CR_RXTRAINRANK3_RxEq_MAX                         (0x0000001F)
+  #define DDRDATA6CH1_CR_RXTRAINRANK3_RxDqsNPi_OFF                     (20)
+  #define DDRDATA6CH1_CR_RXTRAINRANK3_RxDqsNPi_WID                     ( 6)
+  #define DDRDATA6CH1_CR_RXTRAINRANK3_RxDqsNPi_MSK                     (0x03F00000)
+  #define DDRDATA6CH1_CR_RXTRAINRANK3_RxDqsNPi_MAX                     (0x0000003F)
+  #define DDRDATA6CH1_CR_RXTRAINRANK3_RxVref_OFF                       (26)
+  #define DDRDATA6CH1_CR_RXTRAINRANK3_RxVref_WID                       ( 6)
+  #define DDRDATA6CH1_CR_RXTRAINRANK3_RxVref_MSK                       (0xFC000000)
+  #define DDRDATA6CH1_CR_RXTRAINRANK3_RxVref_MAX                       (0x0000003F)
+
+#define DDRDATA6CH1_CR_RXPERBITRANK0_REG                             (0x00000D10)
+  #define DDRDATA6CH1_CR_RXPERBITRANK0_Lane0_OFF                       ( 0)
+  #define DDRDATA6CH1_CR_RXPERBITRANK0_Lane0_WID                       ( 4)
+  #define DDRDATA6CH1_CR_RXPERBITRANK0_Lane0_MSK                       (0x0000000F)
+  #define DDRDATA6CH1_CR_RXPERBITRANK0_Lane0_MAX                       (0x0000000F)
+  #define DDRDATA6CH1_CR_RXPERBITRANK0_Lane1_OFF                       ( 4)
+  #define DDRDATA6CH1_CR_RXPERBITRANK0_Lane1_WID                       ( 4)
+  #define DDRDATA6CH1_CR_RXPERBITRANK0_Lane1_MSK                       (0x000000F0)
+  #define DDRDATA6CH1_CR_RXPERBITRANK0_Lane1_MAX                       (0x0000000F)
+  #define DDRDATA6CH1_CR_RXPERBITRANK0_Lane2_OFF                       ( 8)
+  #define DDRDATA6CH1_CR_RXPERBITRANK0_Lane2_WID                       ( 4)
+  #define DDRDATA6CH1_CR_RXPERBITRANK0_Lane2_MSK                       (0x00000F00)
+  #define DDRDATA6CH1_CR_RXPERBITRANK0_Lane2_MAX                       (0x0000000F)
+  #define DDRDATA6CH1_CR_RXPERBITRANK0_Lane3_OFF                       (12)
+  #define DDRDATA6CH1_CR_RXPERBITRANK0_Lane3_WID                       ( 4)
+  #define DDRDATA6CH1_CR_RXPERBITRANK0_Lane3_MSK                       (0x0000F000)
+  #define DDRDATA6CH1_CR_RXPERBITRANK0_Lane3_MAX                       (0x0000000F)
+  #define DDRDATA6CH1_CR_RXPERBITRANK0_Lane4_OFF                       (16)
+  #define DDRDATA6CH1_CR_RXPERBITRANK0_Lane4_WID                       ( 4)
+  #define DDRDATA6CH1_CR_RXPERBITRANK0_Lane4_MSK                       (0x000F0000)
+  #define DDRDATA6CH1_CR_RXPERBITRANK0_Lane4_MAX                       (0x0000000F)
+  #define DDRDATA6CH1_CR_RXPERBITRANK0_Lane5_OFF                       (20)
+  #define DDRDATA6CH1_CR_RXPERBITRANK0_Lane5_WID                       ( 4)
+  #define DDRDATA6CH1_CR_RXPERBITRANK0_Lane5_MSK                       (0x00F00000)
+  #define DDRDATA6CH1_CR_RXPERBITRANK0_Lane5_MAX                       (0x0000000F)
+  #define DDRDATA6CH1_CR_RXPERBITRANK0_Lane6_OFF                       (24)
+  #define DDRDATA6CH1_CR_RXPERBITRANK0_Lane6_WID                       ( 4)
+  #define DDRDATA6CH1_CR_RXPERBITRANK0_Lane6_MSK                       (0x0F000000)
+  #define DDRDATA6CH1_CR_RXPERBITRANK0_Lane6_MAX                       (0x0000000F)
+  #define DDRDATA6CH1_CR_RXPERBITRANK0_Lane7_OFF                       (28)
+  #define DDRDATA6CH1_CR_RXPERBITRANK0_Lane7_WID                       ( 4)
+  #define DDRDATA6CH1_CR_RXPERBITRANK0_Lane7_MSK                       (0xF0000000)
+  #define DDRDATA6CH1_CR_RXPERBITRANK0_Lane7_MAX                       (0x0000000F)
+
+#define DDRDATA6CH1_CR_RXPERBITRANK1_REG                             (0x00000D14)
+  #define DDRDATA6CH1_CR_RXPERBITRANK1_Lane0_OFF                       ( 0)
+  #define DDRDATA6CH1_CR_RXPERBITRANK1_Lane0_WID                       ( 4)
+  #define DDRDATA6CH1_CR_RXPERBITRANK1_Lane0_MSK                       (0x0000000F)
+  #define DDRDATA6CH1_CR_RXPERBITRANK1_Lane0_MAX                       (0x0000000F)
+  #define DDRDATA6CH1_CR_RXPERBITRANK1_Lane1_OFF                       ( 4)
+  #define DDRDATA6CH1_CR_RXPERBITRANK1_Lane1_WID                       ( 4)
+  #define DDRDATA6CH1_CR_RXPERBITRANK1_Lane1_MSK                       (0x000000F0)
+  #define DDRDATA6CH1_CR_RXPERBITRANK1_Lane1_MAX                       (0x0000000F)
+  #define DDRDATA6CH1_CR_RXPERBITRANK1_Lane2_OFF                       ( 8)
+  #define DDRDATA6CH1_CR_RXPERBITRANK1_Lane2_WID                       ( 4)
+  #define DDRDATA6CH1_CR_RXPERBITRANK1_Lane2_MSK                       (0x00000F00)
+  #define DDRDATA6CH1_CR_RXPERBITRANK1_Lane2_MAX                       (0x0000000F)
+  #define DDRDATA6CH1_CR_RXPERBITRANK1_Lane3_OFF                       (12)
+  #define DDRDATA6CH1_CR_RXPERBITRANK1_Lane3_WID                       ( 4)
+  #define DDRDATA6CH1_CR_RXPERBITRANK1_Lane3_MSK                       (0x0000F000)
+  #define DDRDATA6CH1_CR_RXPERBITRANK1_Lane3_MAX                       (0x0000000F)
+  #define DDRDATA6CH1_CR_RXPERBITRANK1_Lane4_OFF                       (16)
+  #define DDRDATA6CH1_CR_RXPERBITRANK1_Lane4_WID                       ( 4)
+  #define DDRDATA6CH1_CR_RXPERBITRANK1_Lane4_MSK                       (0x000F0000)
+  #define DDRDATA6CH1_CR_RXPERBITRANK1_Lane4_MAX                       (0x0000000F)
+  #define DDRDATA6CH1_CR_RXPERBITRANK1_Lane5_OFF                       (20)
+  #define DDRDATA6CH1_CR_RXPERBITRANK1_Lane5_WID                       ( 4)
+  #define DDRDATA6CH1_CR_RXPERBITRANK1_Lane5_MSK                       (0x00F00000)
+  #define DDRDATA6CH1_CR_RXPERBITRANK1_Lane5_MAX                       (0x0000000F)
+  #define DDRDATA6CH1_CR_RXPERBITRANK1_Lane6_OFF                       (24)
+  #define DDRDATA6CH1_CR_RXPERBITRANK1_Lane6_WID                       ( 4)
+  #define DDRDATA6CH1_CR_RXPERBITRANK1_Lane6_MSK                       (0x0F000000)
+  #define DDRDATA6CH1_CR_RXPERBITRANK1_Lane6_MAX                       (0x0000000F)
+  #define DDRDATA6CH1_CR_RXPERBITRANK1_Lane7_OFF                       (28)
+  #define DDRDATA6CH1_CR_RXPERBITRANK1_Lane7_WID                       ( 4)
+  #define DDRDATA6CH1_CR_RXPERBITRANK1_Lane7_MSK                       (0xF0000000)
+  #define DDRDATA6CH1_CR_RXPERBITRANK1_Lane7_MAX                       (0x0000000F)
+
+#define DDRDATA6CH1_CR_RXPERBITRANK2_REG                             (0x00000D18)
+  #define DDRDATA6CH1_CR_RXPERBITRANK2_Lane0_OFF                       ( 0)
+  #define DDRDATA6CH1_CR_RXPERBITRANK2_Lane0_WID                       ( 4)
+  #define DDRDATA6CH1_CR_RXPERBITRANK2_Lane0_MSK                       (0x0000000F)
+  #define DDRDATA6CH1_CR_RXPERBITRANK2_Lane0_MAX                       (0x0000000F)
+  #define DDRDATA6CH1_CR_RXPERBITRANK2_Lane1_OFF                       ( 4)
+  #define DDRDATA6CH1_CR_RXPERBITRANK2_Lane1_WID                       ( 4)
+  #define DDRDATA6CH1_CR_RXPERBITRANK2_Lane1_MSK                       (0x000000F0)
+  #define DDRDATA6CH1_CR_RXPERBITRANK2_Lane1_MAX                       (0x0000000F)
+  #define DDRDATA6CH1_CR_RXPERBITRANK2_Lane2_OFF                       ( 8)
+  #define DDRDATA6CH1_CR_RXPERBITRANK2_Lane2_WID                       ( 4)
+  #define DDRDATA6CH1_CR_RXPERBITRANK2_Lane2_MSK                       (0x00000F00)
+  #define DDRDATA6CH1_CR_RXPERBITRANK2_Lane2_MAX                       (0x0000000F)
+  #define DDRDATA6CH1_CR_RXPERBITRANK2_Lane3_OFF                       (12)
+  #define DDRDATA6CH1_CR_RXPERBITRANK2_Lane3_WID                       ( 4)
+  #define DDRDATA6CH1_CR_RXPERBITRANK2_Lane3_MSK                       (0x0000F000)
+  #define DDRDATA6CH1_CR_RXPERBITRANK2_Lane3_MAX                       (0x0000000F)
+  #define DDRDATA6CH1_CR_RXPERBITRANK2_Lane4_OFF                       (16)
+  #define DDRDATA6CH1_CR_RXPERBITRANK2_Lane4_WID                       ( 4)
+  #define DDRDATA6CH1_CR_RXPERBITRANK2_Lane4_MSK                       (0x000F0000)
+  #define DDRDATA6CH1_CR_RXPERBITRANK2_Lane4_MAX                       (0x0000000F)
+  #define DDRDATA6CH1_CR_RXPERBITRANK2_Lane5_OFF                       (20)
+  #define DDRDATA6CH1_CR_RXPERBITRANK2_Lane5_WID                       ( 4)
+  #define DDRDATA6CH1_CR_RXPERBITRANK2_Lane5_MSK                       (0x00F00000)
+  #define DDRDATA6CH1_CR_RXPERBITRANK2_Lane5_MAX                       (0x0000000F)
+  #define DDRDATA6CH1_CR_RXPERBITRANK2_Lane6_OFF                       (24)
+  #define DDRDATA6CH1_CR_RXPERBITRANK2_Lane6_WID                       ( 4)
+  #define DDRDATA6CH1_CR_RXPERBITRANK2_Lane6_MSK                       (0x0F000000)
+  #define DDRDATA6CH1_CR_RXPERBITRANK2_Lane6_MAX                       (0x0000000F)
+  #define DDRDATA6CH1_CR_RXPERBITRANK2_Lane7_OFF                       (28)
+  #define DDRDATA6CH1_CR_RXPERBITRANK2_Lane7_WID                       ( 4)
+  #define DDRDATA6CH1_CR_RXPERBITRANK2_Lane7_MSK                       (0xF0000000)
+  #define DDRDATA6CH1_CR_RXPERBITRANK2_Lane7_MAX                       (0x0000000F)
+
+#define DDRDATA6CH1_CR_RXPERBITRANK3_REG                             (0x00000D1C)
+  #define DDRDATA6CH1_CR_RXPERBITRANK3_Lane0_OFF                       ( 0)
+  #define DDRDATA6CH1_CR_RXPERBITRANK3_Lane0_WID                       ( 4)
+  #define DDRDATA6CH1_CR_RXPERBITRANK3_Lane0_MSK                       (0x0000000F)
+  #define DDRDATA6CH1_CR_RXPERBITRANK3_Lane0_MAX                       (0x0000000F)
+  #define DDRDATA6CH1_CR_RXPERBITRANK3_Lane1_OFF                       ( 4)
+  #define DDRDATA6CH1_CR_RXPERBITRANK3_Lane1_WID                       ( 4)
+  #define DDRDATA6CH1_CR_RXPERBITRANK3_Lane1_MSK                       (0x000000F0)
+  #define DDRDATA6CH1_CR_RXPERBITRANK3_Lane1_MAX                       (0x0000000F)
+  #define DDRDATA6CH1_CR_RXPERBITRANK3_Lane2_OFF                       ( 8)
+  #define DDRDATA6CH1_CR_RXPERBITRANK3_Lane2_WID                       ( 4)
+  #define DDRDATA6CH1_CR_RXPERBITRANK3_Lane2_MSK                       (0x00000F00)
+  #define DDRDATA6CH1_CR_RXPERBITRANK3_Lane2_MAX                       (0x0000000F)
+  #define DDRDATA6CH1_CR_RXPERBITRANK3_Lane3_OFF                       (12)
+  #define DDRDATA6CH1_CR_RXPERBITRANK3_Lane3_WID                       ( 4)
+  #define DDRDATA6CH1_CR_RXPERBITRANK3_Lane3_MSK                       (0x0000F000)
+  #define DDRDATA6CH1_CR_RXPERBITRANK3_Lane3_MAX                       (0x0000000F)
+  #define DDRDATA6CH1_CR_RXPERBITRANK3_Lane4_OFF                       (16)
+  #define DDRDATA6CH1_CR_RXPERBITRANK3_Lane4_WID                       ( 4)
+  #define DDRDATA6CH1_CR_RXPERBITRANK3_Lane4_MSK                       (0x000F0000)
+  #define DDRDATA6CH1_CR_RXPERBITRANK3_Lane4_MAX                       (0x0000000F)
+  #define DDRDATA6CH1_CR_RXPERBITRANK3_Lane5_OFF                       (20)
+  #define DDRDATA6CH1_CR_RXPERBITRANK3_Lane5_WID                       ( 4)
+  #define DDRDATA6CH1_CR_RXPERBITRANK3_Lane5_MSK                       (0x00F00000)
+  #define DDRDATA6CH1_CR_RXPERBITRANK3_Lane5_MAX                       (0x0000000F)
+  #define DDRDATA6CH1_CR_RXPERBITRANK3_Lane6_OFF                       (24)
+  #define DDRDATA6CH1_CR_RXPERBITRANK3_Lane6_WID                       ( 4)
+  #define DDRDATA6CH1_CR_RXPERBITRANK3_Lane6_MSK                       (0x0F000000)
+  #define DDRDATA6CH1_CR_RXPERBITRANK3_Lane6_MAX                       (0x0000000F)
+  #define DDRDATA6CH1_CR_RXPERBITRANK3_Lane7_OFF                       (28)
+  #define DDRDATA6CH1_CR_RXPERBITRANK3_Lane7_WID                       ( 4)
+  #define DDRDATA6CH1_CR_RXPERBITRANK3_Lane7_MSK                       (0xF0000000)
+  #define DDRDATA6CH1_CR_RXPERBITRANK3_Lane7_MAX                       (0x0000000F)
+
+#define DDRDATA6CH1_CR_TXTRAINRANK0_REG                              (0x00000D20)
+  #define DDRDATA6CH1_CR_TXTRAINRANK0_TxDqDelay_OFF                    ( 0)
+  #define DDRDATA6CH1_CR_TXTRAINRANK0_TxDqDelay_WID                    ( 9)
+  #define DDRDATA6CH1_CR_TXTRAINRANK0_TxDqDelay_MSK                    (0x000001FF)
+  #define DDRDATA6CH1_CR_TXTRAINRANK0_TxDqDelay_MAX                    (0x000001FF)
+  #define DDRDATA6CH1_CR_TXTRAINRANK0_TxDqsDelay_OFF                   ( 9)
+  #define DDRDATA6CH1_CR_TXTRAINRANK0_TxDqsDelay_WID                   ( 9)
+  #define DDRDATA6CH1_CR_TXTRAINRANK0_TxDqsDelay_MSK                   (0x0003FE00)
+  #define DDRDATA6CH1_CR_TXTRAINRANK0_TxDqsDelay_MAX                   (0x000001FF)
+  #define DDRDATA6CH1_CR_TXTRAINRANK0_Spare0_OFF                       (18)
+  #define DDRDATA6CH1_CR_TXTRAINRANK0_Spare0_WID                       ( 2)
+  #define DDRDATA6CH1_CR_TXTRAINRANK0_Spare0_MSK                       (0x000C0000)
+  #define DDRDATA6CH1_CR_TXTRAINRANK0_Spare0_MAX                       (0x00000003)
+  #define DDRDATA6CH1_CR_TXTRAINRANK0_TxEqualization_OFF               (20)
+  #define DDRDATA6CH1_CR_TXTRAINRANK0_TxEqualization_WID               ( 6)
+  #define DDRDATA6CH1_CR_TXTRAINRANK0_TxEqualization_MSK               (0x03F00000)
+  #define DDRDATA6CH1_CR_TXTRAINRANK0_TxEqualization_MAX               (0x0000003F)
+  #define DDRDATA6CH1_CR_TXTRAINRANK0_Spare1_OFF                       (26)
+  #define DDRDATA6CH1_CR_TXTRAINRANK0_Spare1_WID                       ( 6)
+  #define DDRDATA6CH1_CR_TXTRAINRANK0_Spare1_MSK                       (0xFC000000)
+  #define DDRDATA6CH1_CR_TXTRAINRANK0_Spare1_MAX                       (0x0000003F)
+
+#define DDRDATA6CH1_CR_TXTRAINRANK1_REG                              (0x00000D24)
+  #define DDRDATA6CH1_CR_TXTRAINRANK1_TxDqDelay_OFF                    ( 0)
+  #define DDRDATA6CH1_CR_TXTRAINRANK1_TxDqDelay_WID                    ( 9)
+  #define DDRDATA6CH1_CR_TXTRAINRANK1_TxDqDelay_MSK                    (0x000001FF)
+  #define DDRDATA6CH1_CR_TXTRAINRANK1_TxDqDelay_MAX                    (0x000001FF)
+  #define DDRDATA6CH1_CR_TXTRAINRANK1_TxDqsDelay_OFF                   ( 9)
+  #define DDRDATA6CH1_CR_TXTRAINRANK1_TxDqsDelay_WID                   ( 9)
+  #define DDRDATA6CH1_CR_TXTRAINRANK1_TxDqsDelay_MSK                   (0x0003FE00)
+  #define DDRDATA6CH1_CR_TXTRAINRANK1_TxDqsDelay_MAX                   (0x000001FF)
+  #define DDRDATA6CH1_CR_TXTRAINRANK1_Spare0_OFF                       (18)
+  #define DDRDATA6CH1_CR_TXTRAINRANK1_Spare0_WID                       ( 2)
+  #define DDRDATA6CH1_CR_TXTRAINRANK1_Spare0_MSK                       (0x000C0000)
+  #define DDRDATA6CH1_CR_TXTRAINRANK1_Spare0_MAX                       (0x00000003)
+  #define DDRDATA6CH1_CR_TXTRAINRANK1_TxEqualization_OFF               (20)
+  #define DDRDATA6CH1_CR_TXTRAINRANK1_TxEqualization_WID               ( 6)
+  #define DDRDATA6CH1_CR_TXTRAINRANK1_TxEqualization_MSK               (0x03F00000)
+  #define DDRDATA6CH1_CR_TXTRAINRANK1_TxEqualization_MAX               (0x0000003F)
+  #define DDRDATA6CH1_CR_TXTRAINRANK1_Spare1_OFF                       (26)
+  #define DDRDATA6CH1_CR_TXTRAINRANK1_Spare1_WID                       ( 6)
+  #define DDRDATA6CH1_CR_TXTRAINRANK1_Spare1_MSK                       (0xFC000000)
+  #define DDRDATA6CH1_CR_TXTRAINRANK1_Spare1_MAX                       (0x0000003F)
+
+#define DDRDATA6CH1_CR_TXTRAINRANK2_REG                              (0x00000D28)
+  #define DDRDATA6CH1_CR_TXTRAINRANK2_TxDqDelay_OFF                    ( 0)
+  #define DDRDATA6CH1_CR_TXTRAINRANK2_TxDqDelay_WID                    ( 9)
+  #define DDRDATA6CH1_CR_TXTRAINRANK2_TxDqDelay_MSK                    (0x000001FF)
+  #define DDRDATA6CH1_CR_TXTRAINRANK2_TxDqDelay_MAX                    (0x000001FF)
+  #define DDRDATA6CH1_CR_TXTRAINRANK2_TxDqsDelay_OFF                   ( 9)
+  #define DDRDATA6CH1_CR_TXTRAINRANK2_TxDqsDelay_WID                   ( 9)
+  #define DDRDATA6CH1_CR_TXTRAINRANK2_TxDqsDelay_MSK                   (0x0003FE00)
+  #define DDRDATA6CH1_CR_TXTRAINRANK2_TxDqsDelay_MAX                   (0x000001FF)
+  #define DDRDATA6CH1_CR_TXTRAINRANK2_Spare0_OFF                       (18)
+  #define DDRDATA6CH1_CR_TXTRAINRANK2_Spare0_WID                       ( 2)
+  #define DDRDATA6CH1_CR_TXTRAINRANK2_Spare0_MSK                       (0x000C0000)
+  #define DDRDATA6CH1_CR_TXTRAINRANK2_Spare0_MAX                       (0x00000003)
+  #define DDRDATA6CH1_CR_TXTRAINRANK2_TxEqualization_OFF               (20)
+  #define DDRDATA6CH1_CR_TXTRAINRANK2_TxEqualization_WID               ( 6)
+  #define DDRDATA6CH1_CR_TXTRAINRANK2_TxEqualization_MSK               (0x03F00000)
+  #define DDRDATA6CH1_CR_TXTRAINRANK2_TxEqualization_MAX               (0x0000003F)
+  #define DDRDATA6CH1_CR_TXTRAINRANK2_Spare1_OFF                       (26)
+  #define DDRDATA6CH1_CR_TXTRAINRANK2_Spare1_WID                       ( 6)
+  #define DDRDATA6CH1_CR_TXTRAINRANK2_Spare1_MSK                       (0xFC000000)
+  #define DDRDATA6CH1_CR_TXTRAINRANK2_Spare1_MAX                       (0x0000003F)
+
+#define DDRDATA6CH1_CR_TXTRAINRANK3_REG                              (0x00000D2C)
+  #define DDRDATA6CH1_CR_TXTRAINRANK3_TxDqDelay_OFF                    ( 0)
+  #define DDRDATA6CH1_CR_TXTRAINRANK3_TxDqDelay_WID                    ( 9)
+  #define DDRDATA6CH1_CR_TXTRAINRANK3_TxDqDelay_MSK                    (0x000001FF)
+  #define DDRDATA6CH1_CR_TXTRAINRANK3_TxDqDelay_MAX                    (0x000001FF)
+  #define DDRDATA6CH1_CR_TXTRAINRANK3_TxDqsDelay_OFF                   ( 9)
+  #define DDRDATA6CH1_CR_TXTRAINRANK3_TxDqsDelay_WID                   ( 9)
+  #define DDRDATA6CH1_CR_TXTRAINRANK3_TxDqsDelay_MSK                   (0x0003FE00)
+  #define DDRDATA6CH1_CR_TXTRAINRANK3_TxDqsDelay_MAX                   (0x000001FF)
+  #define DDRDATA6CH1_CR_TXTRAINRANK3_Spare0_OFF                       (18)
+  #define DDRDATA6CH1_CR_TXTRAINRANK3_Spare0_WID                       ( 2)
+  #define DDRDATA6CH1_CR_TXTRAINRANK3_Spare0_MSK                       (0x000C0000)
+  #define DDRDATA6CH1_CR_TXTRAINRANK3_Spare0_MAX                       (0x00000003)
+  #define DDRDATA6CH1_CR_TXTRAINRANK3_TxEqualization_OFF               (20)
+  #define DDRDATA6CH1_CR_TXTRAINRANK3_TxEqualization_WID               ( 6)
+  #define DDRDATA6CH1_CR_TXTRAINRANK3_TxEqualization_MSK               (0x03F00000)
+  #define DDRDATA6CH1_CR_TXTRAINRANK3_TxEqualization_MAX               (0x0000003F)
+  #define DDRDATA6CH1_CR_TXTRAINRANK3_Spare1_OFF                       (26)
+  #define DDRDATA6CH1_CR_TXTRAINRANK3_Spare1_WID                       ( 6)
+  #define DDRDATA6CH1_CR_TXTRAINRANK3_Spare1_MSK                       (0xFC000000)
+  #define DDRDATA6CH1_CR_TXTRAINRANK3_Spare1_MAX                       (0x0000003F)
+
+#define DDRDATA6CH1_CR_TXPERBITRANK0_REG                             (0x00000D30)
+  #define DDRDATA6CH1_CR_TXPERBITRANK0_Lane0_OFF                       ( 0)
+  #define DDRDATA6CH1_CR_TXPERBITRANK0_Lane0_WID                       ( 4)
+  #define DDRDATA6CH1_CR_TXPERBITRANK0_Lane0_MSK                       (0x0000000F)
+  #define DDRDATA6CH1_CR_TXPERBITRANK0_Lane0_MAX                       (0x0000000F)
+  #define DDRDATA6CH1_CR_TXPERBITRANK0_Lane1_OFF                       ( 4)
+  #define DDRDATA6CH1_CR_TXPERBITRANK0_Lane1_WID                       ( 4)
+  #define DDRDATA6CH1_CR_TXPERBITRANK0_Lane1_MSK                       (0x000000F0)
+  #define DDRDATA6CH1_CR_TXPERBITRANK0_Lane1_MAX                       (0x0000000F)
+  #define DDRDATA6CH1_CR_TXPERBITRANK0_Lane2_OFF                       ( 8)
+  #define DDRDATA6CH1_CR_TXPERBITRANK0_Lane2_WID                       ( 4)
+  #define DDRDATA6CH1_CR_TXPERBITRANK0_Lane2_MSK                       (0x00000F00)
+  #define DDRDATA6CH1_CR_TXPERBITRANK0_Lane2_MAX                       (0x0000000F)
+  #define DDRDATA6CH1_CR_TXPERBITRANK0_Lane3_OFF                       (12)
+  #define DDRDATA6CH1_CR_TXPERBITRANK0_Lane3_WID                       ( 4)
+  #define DDRDATA6CH1_CR_TXPERBITRANK0_Lane3_MSK                       (0x0000F000)
+  #define DDRDATA6CH1_CR_TXPERBITRANK0_Lane3_MAX                       (0x0000000F)
+  #define DDRDATA6CH1_CR_TXPERBITRANK0_Lane4_OFF                       (16)
+  #define DDRDATA6CH1_CR_TXPERBITRANK0_Lane4_WID                       ( 4)
+  #define DDRDATA6CH1_CR_TXPERBITRANK0_Lane4_MSK                       (0x000F0000)
+  #define DDRDATA6CH1_CR_TXPERBITRANK0_Lane4_MAX                       (0x0000000F)
+  #define DDRDATA6CH1_CR_TXPERBITRANK0_Lane5_OFF                       (20)
+  #define DDRDATA6CH1_CR_TXPERBITRANK0_Lane5_WID                       ( 4)
+  #define DDRDATA6CH1_CR_TXPERBITRANK0_Lane5_MSK                       (0x00F00000)
+  #define DDRDATA6CH1_CR_TXPERBITRANK0_Lane5_MAX                       (0x0000000F)
+  #define DDRDATA6CH1_CR_TXPERBITRANK0_Lane6_OFF                       (24)
+  #define DDRDATA6CH1_CR_TXPERBITRANK0_Lane6_WID                       ( 4)
+  #define DDRDATA6CH1_CR_TXPERBITRANK0_Lane6_MSK                       (0x0F000000)
+  #define DDRDATA6CH1_CR_TXPERBITRANK0_Lane6_MAX                       (0x0000000F)
+  #define DDRDATA6CH1_CR_TXPERBITRANK0_Lane7_OFF                       (28)
+  #define DDRDATA6CH1_CR_TXPERBITRANK0_Lane7_WID                       ( 4)
+  #define DDRDATA6CH1_CR_TXPERBITRANK0_Lane7_MSK                       (0xF0000000)
+  #define DDRDATA6CH1_CR_TXPERBITRANK0_Lane7_MAX                       (0x0000000F)
+
+#define DDRDATA6CH1_CR_TXPERBITRANK1_REG                             (0x00000D34)
+  #define DDRDATA6CH1_CR_TXPERBITRANK1_Lane0_OFF                       ( 0)
+  #define DDRDATA6CH1_CR_TXPERBITRANK1_Lane0_WID                       ( 4)
+  #define DDRDATA6CH1_CR_TXPERBITRANK1_Lane0_MSK                       (0x0000000F)
+  #define DDRDATA6CH1_CR_TXPERBITRANK1_Lane0_MAX                       (0x0000000F)
+  #define DDRDATA6CH1_CR_TXPERBITRANK1_Lane1_OFF                       ( 4)
+  #define DDRDATA6CH1_CR_TXPERBITRANK1_Lane1_WID                       ( 4)
+  #define DDRDATA6CH1_CR_TXPERBITRANK1_Lane1_MSK                       (0x000000F0)
+  #define DDRDATA6CH1_CR_TXPERBITRANK1_Lane1_MAX                       (0x0000000F)
+  #define DDRDATA6CH1_CR_TXPERBITRANK1_Lane2_OFF                       ( 8)
+  #define DDRDATA6CH1_CR_TXPERBITRANK1_Lane2_WID                       ( 4)
+  #define DDRDATA6CH1_CR_TXPERBITRANK1_Lane2_MSK                       (0x00000F00)
+  #define DDRDATA6CH1_CR_TXPERBITRANK1_Lane2_MAX                       (0x0000000F)
+  #define DDRDATA6CH1_CR_TXPERBITRANK1_Lane3_OFF                       (12)
+  #define DDRDATA6CH1_CR_TXPERBITRANK1_Lane3_WID                       ( 4)
+  #define DDRDATA6CH1_CR_TXPERBITRANK1_Lane3_MSK                       (0x0000F000)
+  #define DDRDATA6CH1_CR_TXPERBITRANK1_Lane3_MAX                       (0x0000000F)
+  #define DDRDATA6CH1_CR_TXPERBITRANK1_Lane4_OFF                       (16)
+  #define DDRDATA6CH1_CR_TXPERBITRANK1_Lane4_WID                       ( 4)
+  #define DDRDATA6CH1_CR_TXPERBITRANK1_Lane4_MSK                       (0x000F0000)
+  #define DDRDATA6CH1_CR_TXPERBITRANK1_Lane4_MAX                       (0x0000000F)
+  #define DDRDATA6CH1_CR_TXPERBITRANK1_Lane5_OFF                       (20)
+  #define DDRDATA6CH1_CR_TXPERBITRANK1_Lane5_WID                       ( 4)
+  #define DDRDATA6CH1_CR_TXPERBITRANK1_Lane5_MSK                       (0x00F00000)
+  #define DDRDATA6CH1_CR_TXPERBITRANK1_Lane5_MAX                       (0x0000000F)
+  #define DDRDATA6CH1_CR_TXPERBITRANK1_Lane6_OFF                       (24)
+  #define DDRDATA6CH1_CR_TXPERBITRANK1_Lane6_WID                       ( 4)
+  #define DDRDATA6CH1_CR_TXPERBITRANK1_Lane6_MSK                       (0x0F000000)
+  #define DDRDATA6CH1_CR_TXPERBITRANK1_Lane6_MAX                       (0x0000000F)
+  #define DDRDATA6CH1_CR_TXPERBITRANK1_Lane7_OFF                       (28)
+  #define DDRDATA6CH1_CR_TXPERBITRANK1_Lane7_WID                       ( 4)
+  #define DDRDATA6CH1_CR_TXPERBITRANK1_Lane7_MSK                       (0xF0000000)
+  #define DDRDATA6CH1_CR_TXPERBITRANK1_Lane7_MAX                       (0x0000000F)
+
+#define DDRDATA6CH1_CR_TXPERBITRANK2_REG                             (0x00000D38)
+  #define DDRDATA6CH1_CR_TXPERBITRANK2_Lane0_OFF                       ( 0)
+  #define DDRDATA6CH1_CR_TXPERBITRANK2_Lane0_WID                       ( 4)
+  #define DDRDATA6CH1_CR_TXPERBITRANK2_Lane0_MSK                       (0x0000000F)
+  #define DDRDATA6CH1_CR_TXPERBITRANK2_Lane0_MAX                       (0x0000000F)
+  #define DDRDATA6CH1_CR_TXPERBITRANK2_Lane1_OFF                       ( 4)
+  #define DDRDATA6CH1_CR_TXPERBITRANK2_Lane1_WID                       ( 4)
+  #define DDRDATA6CH1_CR_TXPERBITRANK2_Lane1_MSK                       (0x000000F0)
+  #define DDRDATA6CH1_CR_TXPERBITRANK2_Lane1_MAX                       (0x0000000F)
+  #define DDRDATA6CH1_CR_TXPERBITRANK2_Lane2_OFF                       ( 8)
+  #define DDRDATA6CH1_CR_TXPERBITRANK2_Lane2_WID                       ( 4)
+  #define DDRDATA6CH1_CR_TXPERBITRANK2_Lane2_MSK                       (0x00000F00)
+  #define DDRDATA6CH1_CR_TXPERBITRANK2_Lane2_MAX                       (0x0000000F)
+  #define DDRDATA6CH1_CR_TXPERBITRANK2_Lane3_OFF                       (12)
+  #define DDRDATA6CH1_CR_TXPERBITRANK2_Lane3_WID                       ( 4)
+  #define DDRDATA6CH1_CR_TXPERBITRANK2_Lane3_MSK                       (0x0000F000)
+  #define DDRDATA6CH1_CR_TXPERBITRANK2_Lane3_MAX                       (0x0000000F)
+  #define DDRDATA6CH1_CR_TXPERBITRANK2_Lane4_OFF                       (16)
+  #define DDRDATA6CH1_CR_TXPERBITRANK2_Lane4_WID                       ( 4)
+  #define DDRDATA6CH1_CR_TXPERBITRANK2_Lane4_MSK                       (0x000F0000)
+  #define DDRDATA6CH1_CR_TXPERBITRANK2_Lane4_MAX                       (0x0000000F)
+  #define DDRDATA6CH1_CR_TXPERBITRANK2_Lane5_OFF                       (20)
+  #define DDRDATA6CH1_CR_TXPERBITRANK2_Lane5_WID                       ( 4)
+  #define DDRDATA6CH1_CR_TXPERBITRANK2_Lane5_MSK                       (0x00F00000)
+  #define DDRDATA6CH1_CR_TXPERBITRANK2_Lane5_MAX                       (0x0000000F)
+  #define DDRDATA6CH1_CR_TXPERBITRANK2_Lane6_OFF                       (24)
+  #define DDRDATA6CH1_CR_TXPERBITRANK2_Lane6_WID                       ( 4)
+  #define DDRDATA6CH1_CR_TXPERBITRANK2_Lane6_MSK                       (0x0F000000)
+  #define DDRDATA6CH1_CR_TXPERBITRANK2_Lane6_MAX                       (0x0000000F)
+  #define DDRDATA6CH1_CR_TXPERBITRANK2_Lane7_OFF                       (28)
+  #define DDRDATA6CH1_CR_TXPERBITRANK2_Lane7_WID                       ( 4)
+  #define DDRDATA6CH1_CR_TXPERBITRANK2_Lane7_MSK                       (0xF0000000)
+  #define DDRDATA6CH1_CR_TXPERBITRANK2_Lane7_MAX                       (0x0000000F)
+
+#define DDRDATA6CH1_CR_TXPERBITRANK3_REG                             (0x00000D3C)
+  #define DDRDATA6CH1_CR_TXPERBITRANK3_Lane0_OFF                       ( 0)
+  #define DDRDATA6CH1_CR_TXPERBITRANK3_Lane0_WID                       ( 4)
+  #define DDRDATA6CH1_CR_TXPERBITRANK3_Lane0_MSK                       (0x0000000F)
+  #define DDRDATA6CH1_CR_TXPERBITRANK3_Lane0_MAX                       (0x0000000F)
+  #define DDRDATA6CH1_CR_TXPERBITRANK3_Lane1_OFF                       ( 4)
+  #define DDRDATA6CH1_CR_TXPERBITRANK3_Lane1_WID                       ( 4)
+  #define DDRDATA6CH1_CR_TXPERBITRANK3_Lane1_MSK                       (0x000000F0)
+  #define DDRDATA6CH1_CR_TXPERBITRANK3_Lane1_MAX                       (0x0000000F)
+  #define DDRDATA6CH1_CR_TXPERBITRANK3_Lane2_OFF                       ( 8)
+  #define DDRDATA6CH1_CR_TXPERBITRANK3_Lane2_WID                       ( 4)
+  #define DDRDATA6CH1_CR_TXPERBITRANK3_Lane2_MSK                       (0x00000F00)
+  #define DDRDATA6CH1_CR_TXPERBITRANK3_Lane2_MAX                       (0x0000000F)
+  #define DDRDATA6CH1_CR_TXPERBITRANK3_Lane3_OFF                       (12)
+  #define DDRDATA6CH1_CR_TXPERBITRANK3_Lane3_WID                       ( 4)
+  #define DDRDATA6CH1_CR_TXPERBITRANK3_Lane3_MSK                       (0x0000F000)
+  #define DDRDATA6CH1_CR_TXPERBITRANK3_Lane3_MAX                       (0x0000000F)
+  #define DDRDATA6CH1_CR_TXPERBITRANK3_Lane4_OFF                       (16)
+  #define DDRDATA6CH1_CR_TXPERBITRANK3_Lane4_WID                       ( 4)
+  #define DDRDATA6CH1_CR_TXPERBITRANK3_Lane4_MSK                       (0x000F0000)
+  #define DDRDATA6CH1_CR_TXPERBITRANK3_Lane4_MAX                       (0x0000000F)
+  #define DDRDATA6CH1_CR_TXPERBITRANK3_Lane5_OFF                       (20)
+  #define DDRDATA6CH1_CR_TXPERBITRANK3_Lane5_WID                       ( 4)
+  #define DDRDATA6CH1_CR_TXPERBITRANK3_Lane5_MSK                       (0x00F00000)
+  #define DDRDATA6CH1_CR_TXPERBITRANK3_Lane5_MAX                       (0x0000000F)
+  #define DDRDATA6CH1_CR_TXPERBITRANK3_Lane6_OFF                       (24)
+  #define DDRDATA6CH1_CR_TXPERBITRANK3_Lane6_WID                       ( 4)
+  #define DDRDATA6CH1_CR_TXPERBITRANK3_Lane6_MSK                       (0x0F000000)
+  #define DDRDATA6CH1_CR_TXPERBITRANK3_Lane6_MAX                       (0x0000000F)
+  #define DDRDATA6CH1_CR_TXPERBITRANK3_Lane7_OFF                       (28)
+  #define DDRDATA6CH1_CR_TXPERBITRANK3_Lane7_WID                       ( 4)
+  #define DDRDATA6CH1_CR_TXPERBITRANK3_Lane7_MSK                       (0xF0000000)
+  #define DDRDATA6CH1_CR_TXPERBITRANK3_Lane7_MAX                       (0x0000000F)
+
+#define DDRDATA6CH1_CR_RCOMPDATA0_REG                                (0x00000D40)
+  #define DDRDATA6CH1_CR_RCOMPDATA0_RcompDrvUp_OFF                     ( 0)
+  #define DDRDATA6CH1_CR_RCOMPDATA0_RcompDrvUp_WID                     ( 6)
+  #define DDRDATA6CH1_CR_RCOMPDATA0_RcompDrvUp_MSK                     (0x0000003F)
+  #define DDRDATA6CH1_CR_RCOMPDATA0_RcompDrvUp_MAX                     (0x0000003F)
+  #define DDRDATA6CH1_CR_RCOMPDATA0_Spare0_OFF                         ( 6)
+  #define DDRDATA6CH1_CR_RCOMPDATA0_Spare0_WID                         ( 3)
+  #define DDRDATA6CH1_CR_RCOMPDATA0_Spare0_MSK                         (0x000001C0)
+  #define DDRDATA6CH1_CR_RCOMPDATA0_Spare0_MAX                         (0x00000007)
+  #define DDRDATA6CH1_CR_RCOMPDATA0_RcompDrvDown_OFF                   ( 9)
+  #define DDRDATA6CH1_CR_RCOMPDATA0_RcompDrvDown_WID                   ( 6)
+  #define DDRDATA6CH1_CR_RCOMPDATA0_RcompDrvDown_MSK                   (0x00007E00)
+  #define DDRDATA6CH1_CR_RCOMPDATA0_RcompDrvDown_MAX                   (0x0000003F)
+  #define DDRDATA6CH1_CR_RCOMPDATA0_VTComp_OFF                         (15)
+  #define DDRDATA6CH1_CR_RCOMPDATA0_VTComp_WID                         ( 5)
+  #define DDRDATA6CH1_CR_RCOMPDATA0_VTComp_MSK                         (0x000F8000)
+  #define DDRDATA6CH1_CR_RCOMPDATA0_VTComp_MAX                         (0x0000001F)
+  #define DDRDATA6CH1_CR_RCOMPDATA0_TcoComp_OFF                        (20)
+  #define DDRDATA6CH1_CR_RCOMPDATA0_TcoComp_WID                        ( 6)
+  #define DDRDATA6CH1_CR_RCOMPDATA0_TcoComp_MSK                        (0x03F00000)
+  #define DDRDATA6CH1_CR_RCOMPDATA0_TcoComp_MAX                        (0x0000003F)
+  #define DDRDATA6CH1_CR_RCOMPDATA0_SlewRateComp_OFF                   (26)
+  #define DDRDATA6CH1_CR_RCOMPDATA0_SlewRateComp_WID                   ( 5)
+  #define DDRDATA6CH1_CR_RCOMPDATA0_SlewRateComp_MSK                   (0x7C000000)
+  #define DDRDATA6CH1_CR_RCOMPDATA0_SlewRateComp_MAX                   (0x0000001F)
+  #define DDRDATA6CH1_CR_RCOMPDATA0_Spare2_OFF                         (31)
+  #define DDRDATA6CH1_CR_RCOMPDATA0_Spare2_WID                         ( 1)
+  #define DDRDATA6CH1_CR_RCOMPDATA0_Spare2_MSK                         (0x80000000)
+  #define DDRDATA6CH1_CR_RCOMPDATA0_Spare2_MAX                         (0x00000001)
+
+#define DDRDATA6CH1_CR_RCOMPDATA1_REG                                (0x00000D44)
+  #define DDRDATA6CH1_CR_RCOMPDATA1_RcompOdtUp_OFF                     ( 0)
+  #define DDRDATA6CH1_CR_RCOMPDATA1_RcompOdtUp_WID                     ( 6)
+  #define DDRDATA6CH1_CR_RCOMPDATA1_RcompOdtUp_MSK                     (0x0000003F)
+  #define DDRDATA6CH1_CR_RCOMPDATA1_RcompOdtUp_MAX                     (0x0000003F)
+  #define DDRDATA6CH1_CR_RCOMPDATA1_Spare0_OFF                         ( 6)
+  #define DDRDATA6CH1_CR_RCOMPDATA1_Spare0_WID                         ( 3)
+  #define DDRDATA6CH1_CR_RCOMPDATA1_Spare0_MSK                         (0x000001C0)
+  #define DDRDATA6CH1_CR_RCOMPDATA1_Spare0_MAX                         (0x00000007)
+  #define DDRDATA6CH1_CR_RCOMPDATA1_RcompOdtDown_OFF                   ( 9)
+  #define DDRDATA6CH1_CR_RCOMPDATA1_RcompOdtDown_WID                   ( 6)
+  #define DDRDATA6CH1_CR_RCOMPDATA1_RcompOdtDown_MSK                   (0x00007E00)
+  #define DDRDATA6CH1_CR_RCOMPDATA1_RcompOdtDown_MAX                   (0x0000003F)
+  #define DDRDATA6CH1_CR_RCOMPDATA1_Spare1_OFF                         (15)
+  #define DDRDATA6CH1_CR_RCOMPDATA1_Spare1_WID                         ( 1)
+  #define DDRDATA6CH1_CR_RCOMPDATA1_Spare1_MSK                         (0x00008000)
+  #define DDRDATA6CH1_CR_RCOMPDATA1_Spare1_MAX                         (0x00000001)
+  #define DDRDATA6CH1_CR_RCOMPDATA1_PanicDrvDn_OFF                     (16)
+  #define DDRDATA6CH1_CR_RCOMPDATA1_PanicDrvDn_WID                     ( 6)
+  #define DDRDATA6CH1_CR_RCOMPDATA1_PanicDrvDn_MSK                     (0x003F0000)
+  #define DDRDATA6CH1_CR_RCOMPDATA1_PanicDrvDn_MAX                     (0x0000003F)
+  #define DDRDATA6CH1_CR_RCOMPDATA1_PanicDrvUp_OFF                     (22)
+  #define DDRDATA6CH1_CR_RCOMPDATA1_PanicDrvUp_WID                     ( 6)
+  #define DDRDATA6CH1_CR_RCOMPDATA1_PanicDrvUp_MSK                     (0x0FC00000)
+  #define DDRDATA6CH1_CR_RCOMPDATA1_PanicDrvUp_MAX                     (0x0000003F)
+  #define DDRDATA6CH1_CR_RCOMPDATA1_LevelShifterComp_OFF               (28)
+  #define DDRDATA6CH1_CR_RCOMPDATA1_LevelShifterComp_WID               ( 3)
+  #define DDRDATA6CH1_CR_RCOMPDATA1_LevelShifterComp_MSK               (0x70000000)
+  #define DDRDATA6CH1_CR_RCOMPDATA1_LevelShifterComp_MAX               (0x00000007)
+  #define DDRDATA6CH1_CR_RCOMPDATA1_Spare2_OFF                         (31)
+  #define DDRDATA6CH1_CR_RCOMPDATA1_Spare2_WID                         ( 1)
+  #define DDRDATA6CH1_CR_RCOMPDATA1_Spare2_MSK                         (0x80000000)
+  #define DDRDATA6CH1_CR_RCOMPDATA1_Spare2_MAX                         (0x00000001)
+
+#define DDRDATA6CH1_CR_TXXTALK_REG                                   (0x00000D48)
+  #define DDRDATA6CH1_CR_TXXTALK_Lane0_OFF                             ( 0)
+  #define DDRDATA6CH1_CR_TXXTALK_Lane0_WID                             ( 4)
+  #define DDRDATA6CH1_CR_TXXTALK_Lane0_MSK                             (0x0000000F)
+  #define DDRDATA6CH1_CR_TXXTALK_Lane0_MAX                             (0x0000000F)
+  #define DDRDATA6CH1_CR_TXXTALK_Lane1_OFF                             ( 4)
+  #define DDRDATA6CH1_CR_TXXTALK_Lane1_WID                             ( 4)
+  #define DDRDATA6CH1_CR_TXXTALK_Lane1_MSK                             (0x000000F0)
+  #define DDRDATA6CH1_CR_TXXTALK_Lane1_MAX                             (0x0000000F)
+  #define DDRDATA6CH1_CR_TXXTALK_Lane2_OFF                             ( 8)
+  #define DDRDATA6CH1_CR_TXXTALK_Lane2_WID                             ( 4)
+  #define DDRDATA6CH1_CR_TXXTALK_Lane2_MSK                             (0x00000F00)
+  #define DDRDATA6CH1_CR_TXXTALK_Lane2_MAX                             (0x0000000F)
+  #define DDRDATA6CH1_CR_TXXTALK_Lane3_OFF                             (12)
+  #define DDRDATA6CH1_CR_TXXTALK_Lane3_WID                             ( 4)
+  #define DDRDATA6CH1_CR_TXXTALK_Lane3_MSK                             (0x0000F000)
+  #define DDRDATA6CH1_CR_TXXTALK_Lane3_MAX                             (0x0000000F)
+  #define DDRDATA6CH1_CR_TXXTALK_Lane4_OFF                             (16)
+  #define DDRDATA6CH1_CR_TXXTALK_Lane4_WID                             ( 4)
+  #define DDRDATA6CH1_CR_TXXTALK_Lane4_MSK                             (0x000F0000)
+  #define DDRDATA6CH1_CR_TXXTALK_Lane4_MAX                             (0x0000000F)
+  #define DDRDATA6CH1_CR_TXXTALK_Lane5_OFF                             (20)
+  #define DDRDATA6CH1_CR_TXXTALK_Lane5_WID                             ( 4)
+  #define DDRDATA6CH1_CR_TXXTALK_Lane5_MSK                             (0x00F00000)
+  #define DDRDATA6CH1_CR_TXXTALK_Lane5_MAX                             (0x0000000F)
+  #define DDRDATA6CH1_CR_TXXTALK_Lane6_OFF                             (24)
+  #define DDRDATA6CH1_CR_TXXTALK_Lane6_WID                             ( 4)
+  #define DDRDATA6CH1_CR_TXXTALK_Lane6_MSK                             (0x0F000000)
+  #define DDRDATA6CH1_CR_TXXTALK_Lane6_MAX                             (0x0000000F)
+  #define DDRDATA6CH1_CR_TXXTALK_Lane7_OFF                             (28)
+  #define DDRDATA6CH1_CR_TXXTALK_Lane7_WID                             ( 4)
+  #define DDRDATA6CH1_CR_TXXTALK_Lane7_MSK                             (0xF0000000)
+  #define DDRDATA6CH1_CR_TXXTALK_Lane7_MAX                             (0x0000000F)
+
+#define DDRDATA6CH1_CR_RXOFFSETVDQ_REG                               (0x00000D4C)
+  #define DDRDATA6CH1_CR_RXOFFSETVDQ_Lane0_OFF                         ( 0)
+  #define DDRDATA6CH1_CR_RXOFFSETVDQ_Lane0_WID                         ( 4)
+  #define DDRDATA6CH1_CR_RXOFFSETVDQ_Lane0_MSK                         (0x0000000F)
+  #define DDRDATA6CH1_CR_RXOFFSETVDQ_Lane0_MAX                         (0x0000000F)
+  #define DDRDATA6CH1_CR_RXOFFSETVDQ_Lane1_OFF                         ( 4)
+  #define DDRDATA6CH1_CR_RXOFFSETVDQ_Lane1_WID                         ( 4)
+  #define DDRDATA6CH1_CR_RXOFFSETVDQ_Lane1_MSK                         (0x000000F0)
+  #define DDRDATA6CH1_CR_RXOFFSETVDQ_Lane1_MAX                         (0x0000000F)
+  #define DDRDATA6CH1_CR_RXOFFSETVDQ_Lane2_OFF                         ( 8)
+  #define DDRDATA6CH1_CR_RXOFFSETVDQ_Lane2_WID                         ( 4)
+  #define DDRDATA6CH1_CR_RXOFFSETVDQ_Lane2_MSK                         (0x00000F00)
+  #define DDRDATA6CH1_CR_RXOFFSETVDQ_Lane2_MAX                         (0x0000000F)
+  #define DDRDATA6CH1_CR_RXOFFSETVDQ_Lane3_OFF                         (12)
+  #define DDRDATA6CH1_CR_RXOFFSETVDQ_Lane3_WID                         ( 4)
+  #define DDRDATA6CH1_CR_RXOFFSETVDQ_Lane3_MSK                         (0x0000F000)
+  #define DDRDATA6CH1_CR_RXOFFSETVDQ_Lane3_MAX                         (0x0000000F)
+  #define DDRDATA6CH1_CR_RXOFFSETVDQ_Lane4_OFF                         (16)
+  #define DDRDATA6CH1_CR_RXOFFSETVDQ_Lane4_WID                         ( 4)
+  #define DDRDATA6CH1_CR_RXOFFSETVDQ_Lane4_MSK                         (0x000F0000)
+  #define DDRDATA6CH1_CR_RXOFFSETVDQ_Lane4_MAX                         (0x0000000F)
+  #define DDRDATA6CH1_CR_RXOFFSETVDQ_Lane5_OFF                         (20)
+  #define DDRDATA6CH1_CR_RXOFFSETVDQ_Lane5_WID                         ( 4)
+  #define DDRDATA6CH1_CR_RXOFFSETVDQ_Lane5_MSK                         (0x00F00000)
+  #define DDRDATA6CH1_CR_RXOFFSETVDQ_Lane5_MAX                         (0x0000000F)
+  #define DDRDATA6CH1_CR_RXOFFSETVDQ_Lane6_OFF                         (24)
+  #define DDRDATA6CH1_CR_RXOFFSETVDQ_Lane6_WID                         ( 4)
+  #define DDRDATA6CH1_CR_RXOFFSETVDQ_Lane6_MSK                         (0x0F000000)
+  #define DDRDATA6CH1_CR_RXOFFSETVDQ_Lane6_MAX                         (0x0000000F)
+  #define DDRDATA6CH1_CR_RXOFFSETVDQ_Lane7_OFF                         (28)
+  #define DDRDATA6CH1_CR_RXOFFSETVDQ_Lane7_WID                         ( 4)
+  #define DDRDATA6CH1_CR_RXOFFSETVDQ_Lane7_MSK                         (0xF0000000)
+  #define DDRDATA6CH1_CR_RXOFFSETVDQ_Lane7_MAX                         (0x0000000F)
+
+#define DDRDATA6CH1_CR_DDRDATARESERVED_REG                           (0x00000D50)
+  #define DDRDATA6CH1_CR_DDRDATARESERVED_Spare_OFF                     ( 0)
+  #define DDRDATA6CH1_CR_DDRDATARESERVED_Spare_WID                     (32)
+  #define DDRDATA6CH1_CR_DDRDATARESERVED_Spare_MSK                     (0xFFFFFFFF)
+  #define DDRDATA6CH1_CR_DDRDATARESERVED_Spare_MAX                     (0xFFFFFFFF)
+
+#define DDRDATA6CH1_CR_DATATRAINFEEDBACK_REG                         (0x00000D54)
+  #define DDRDATA6CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_OFF       ( 0)
+  #define DDRDATA6CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_WID       ( 9)
+  #define DDRDATA6CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_MSK       (0x000001FF)
+  #define DDRDATA6CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_MAX       (0x000001FF)
+  #define DDRDATA6CH1_CR_DATATRAINFEEDBACK_Spare_OFF                   ( 9)
+  #define DDRDATA6CH1_CR_DATATRAINFEEDBACK_Spare_WID                   (23)
+  #define DDRDATA6CH1_CR_DATATRAINFEEDBACK_Spare_MSK                   (0xFFFFFE00)
+  #define DDRDATA6CH1_CR_DATATRAINFEEDBACK_Spare_MAX                   (0x007FFFFF)
+
+#define DDRDATA6CH1_CR_DLLPITESTANDADC_REG                           (0x00000D58)
+  #define DDRDATA6CH1_CR_DLLPITESTANDADC_RunTest_OFF                   ( 0)
+  #define DDRDATA6CH1_CR_DLLPITESTANDADC_RunTest_WID                   ( 1)
+  #define DDRDATA6CH1_CR_DLLPITESTANDADC_RunTest_MSK                   (0x00000001)
+  #define DDRDATA6CH1_CR_DLLPITESTANDADC_RunTest_MAX                   (0x00000001)
+  #define DDRDATA6CH1_CR_DLLPITESTANDADC_RunTest_DEF                   (0x00000000)
+  #define DDRDATA6CH1_CR_DLLPITESTANDADC_Load_OFF                      ( 1)
+  #define DDRDATA6CH1_CR_DLLPITESTANDADC_Load_WID                      ( 1)
+  #define DDRDATA6CH1_CR_DLLPITESTANDADC_Load_MSK                      (0x00000002)
+  #define DDRDATA6CH1_CR_DLLPITESTANDADC_Load_MAX                      (0x00000001)
+  #define DDRDATA6CH1_CR_DLLPITESTANDADC_Load_DEF                      (0x00000000)
+  #define DDRDATA6CH1_CR_DLLPITESTANDADC_ModeHVM_OFF                   ( 2)
+  #define DDRDATA6CH1_CR_DLLPITESTANDADC_ModeHVM_WID                   ( 1)
+  #define DDRDATA6CH1_CR_DLLPITESTANDADC_ModeHVM_MSK                   (0x00000004)
+  #define DDRDATA6CH1_CR_DLLPITESTANDADC_ModeHVM_MAX                   (0x00000001)
+  #define DDRDATA6CH1_CR_DLLPITESTANDADC_ModeHVM_DEF                   (0x00000000)
+  #define DDRDATA6CH1_CR_DLLPITESTANDADC_ModeDV_OFF                    ( 3)
+  #define DDRDATA6CH1_CR_DLLPITESTANDADC_ModeDV_WID                    ( 1)
+  #define DDRDATA6CH1_CR_DLLPITESTANDADC_ModeDV_MSK                    (0x00000008)
+  #define DDRDATA6CH1_CR_DLLPITESTANDADC_ModeDV_MAX                    (0x00000001)
+  #define DDRDATA6CH1_CR_DLLPITESTANDADC_ModeDV_DEF                    (0x00000000)
+  #define DDRDATA6CH1_CR_DLLPITESTANDADC_ModeADC_OFF                   ( 4)
+  #define DDRDATA6CH1_CR_DLLPITESTANDADC_ModeADC_WID                   ( 1)
+  #define DDRDATA6CH1_CR_DLLPITESTANDADC_ModeADC_MSK                   (0x00000010)
+  #define DDRDATA6CH1_CR_DLLPITESTANDADC_ModeADC_MAX                   (0x00000001)
+  #define DDRDATA6CH1_CR_DLLPITESTANDADC_ModeADC_DEF                   (0x00000000)
+  #define DDRDATA6CH1_CR_DLLPITESTANDADC_LoadCount_OFF                 ( 5)
+  #define DDRDATA6CH1_CR_DLLPITESTANDADC_LoadCount_WID                 (10)
+  #define DDRDATA6CH1_CR_DLLPITESTANDADC_LoadCount_MSK                 (0x00007FE0)
+  #define DDRDATA6CH1_CR_DLLPITESTANDADC_LoadCount_MAX                 (0x000003FF)
+  #define DDRDATA6CH1_CR_DLLPITESTANDADC_CountStatus_OFF               (15)
+  #define DDRDATA6CH1_CR_DLLPITESTANDADC_CountStatus_WID               (10)
+  #define DDRDATA6CH1_CR_DLLPITESTANDADC_CountStatus_MSK               (0x01FF8000)
+  #define DDRDATA6CH1_CR_DLLPITESTANDADC_CountStatus_MAX               (0x000003FF)
+  #define DDRDATA6CH1_CR_DLLPITESTANDADC_CountStatus_DEF               (0x00000000)
+  #define DDRDATA6CH1_CR_DLLPITESTANDADC_Spare_OFF                     (25)
+  #define DDRDATA6CH1_CR_DLLPITESTANDADC_Spare_WID                     ( 7)
+  #define DDRDATA6CH1_CR_DLLPITESTANDADC_Spare_MSK                     (0xFE000000)
+  #define DDRDATA6CH1_CR_DLLPITESTANDADC_Spare_MAX                     (0x0000007F)
+
+#define DDRDATA6CH1_CR_DDRCRDATAOFFSETCOMP_REG                       (0x00000D5C)
+  #define DDRDATA6CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_OFF     ( 0)
+  #define DDRDATA6CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_WID     ( 6)
+  #define DDRDATA6CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MSK     (0x0000003F)
+  #define DDRDATA6CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MAX     (0x0000003F)
+  #define DDRDATA6CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_DEF     (0x00000000)
+  #define DDRDATA6CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_OFF   ( 6)
+  #define DDRDATA6CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_WID   ( 6)
+  #define DDRDATA6CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MSK   (0x00000FC0)
+  #define DDRDATA6CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MAX   (0x0000003F)
+  #define DDRDATA6CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_DEF   (0x00000000)
+  #define DDRDATA6CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_OFF     (12)
+  #define DDRDATA6CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_WID     ( 5)
+  #define DDRDATA6CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MSK     (0x0001F000)
+  #define DDRDATA6CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MAX     (0x0000001F)
+  #define DDRDATA6CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_DEF     (0x00000000)
+  #define DDRDATA6CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_OFF   (17)
+  #define DDRDATA6CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_WID   ( 5)
+  #define DDRDATA6CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MSK   (0x003E0000)
+  #define DDRDATA6CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MAX   (0x0000001F)
+  #define DDRDATA6CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_DEF   (0x00000000)
+  #define DDRDATA6CH1_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_OFF       (22)
+  #define DDRDATA6CH1_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_WID       ( 5)
+  #define DDRDATA6CH1_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_MSK       (0x07C00000)
+  #define DDRDATA6CH1_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_MAX       (0x0000001F)
+  #define DDRDATA6CH1_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_DEF       (0x00000000)
+  #define DDRDATA6CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_OFF  (27)
+  #define DDRDATA6CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_WID  ( 5)
+  #define DDRDATA6CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MSK  (0xF8000000)
+  #define DDRDATA6CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MAX  (0x0000001F)
+  #define DDRDATA6CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_DEF  (0x00000000)
+
+#define DDRDATA6CH1_CR_DDRCRDATACONTROL1_REG                         (0x00000D60)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_RefPi_OFF                   ( 0)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_RefPi_WID                   ( 4)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_RefPi_MSK                   (0x0000000F)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_RefPi_MAX                   (0x0000000F)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_RefPi_DEF                   (0x00000000)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_DllMask_OFF                 ( 4)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_DllMask_WID                 ( 2)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_DllMask_MSK                 (0x00000030)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_DllMask_MAX                 (0x00000003)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_DllMask_DEF                 (0x00000000)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_DllWeakLock_OFF             ( 6)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_DllWeakLock_WID             ( 1)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_DllWeakLock_MSK             (0x00000040)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_DllWeakLock_MAX             (0x00000001)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_DllWeakLock_DEF             (0x00000000)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_OFF      ( 7)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_WID      ( 3)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MSK      (0x00000380)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MAX      (0x00000007)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_DEF      (0x00000000)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_OFF               (10)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_WID               ( 3)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_MSK               (0x00001C00)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_MAX               (0x00000007)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_DEF               (0x00000000)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_OdtDelay_OFF                (13)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_OdtDelay_WID                ( 4)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_OdtDelay_MSK                (0x0001E000)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_OdtDelay_MAX                (0x0000000F)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_OdtDelay_DEF                (0x00000000)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_OdtDuration_OFF             (17)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_OdtDuration_WID             ( 3)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_OdtDuration_MSK             (0x000E0000)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_OdtDuration_MAX             (0x00000007)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_OdtDuration_DEF             (0x00000000)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_OFF           (20)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_WID           ( 4)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_MSK           (0x00F00000)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_MAX           (0x0000000F)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_DEF           (0x00000000)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_OFF        (24)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_WID        ( 3)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_MSK        (0x07000000)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_MAX        (0x00000007)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_DEF        (0x00000000)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_BurstEndODTDelay_OFF        (27)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_BurstEndODTDelay_WID        ( 3)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_BurstEndODTDelay_MSK        (0x38000000)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_BurstEndODTDelay_MAX        (0x00000007)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_BurstEndODTDelay_DEF        (0x00000000)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_OFF          (30)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_WID          ( 1)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_MSK          (0x40000000)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_MAX          (0x00000001)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_DEF          (0x00000000)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_Rsvd1_OFF                   (31)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_Rsvd1_WID                   ( 1)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_Rsvd1_MSK                   (0x80000000)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_Rsvd1_MAX                   (0x00000001)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_Rsvd1_DEF                   (0x00000000)
+
+#define DDRDATA6CH1_CR_DDRCRDATACONTROL2_REG                         (0x00000D64)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_OFF            ( 0)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_WID            ( 5)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_MSK            (0x0000001F)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_MAX            (0x0000001F)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_DEF            (0x00000000)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_OFF             ( 5)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_WID             ( 1)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_MSK             (0x00000020)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_MAX             (0x00000001)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_DEF             (0x00000000)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_ForceRxOn_OFF               ( 6)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_ForceRxOn_WID               ( 1)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_ForceRxOn_MSK               (0x00000040)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_ForceRxOn_MAX               (0x00000001)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_ForceRxOn_DEF               (0x00000000)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_LeakerComp_OFF              ( 7)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_LeakerComp_WID              ( 2)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_LeakerComp_MSK              (0x00000180)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_LeakerComp_MAX              (0x00000003)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_LeakerComp_DEF              (0x00000000)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_OFF          ( 9)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_WID          ( 4)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_MSK          (0x00001E00)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_MAX          (0x0000000F)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_DEF          (0x00000008)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_OFF             (13)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_WID             ( 5)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_MSK             (0x0003E000)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_MAX             (0x0000001F)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_DEF             (0x00000011)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_OFF             (18)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_WID             ( 1)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_MSK             (0x00040000)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_MAX             (0x00000001)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_DEF             (0x00000000)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_Spare_OFF                   (19)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_Spare_WID                   (13)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_Spare_MSK                   (0xFFF80000)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_Spare_MAX                   (0x00001FFF)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_Spare_DEF                   (0x00000000)
+
+#define DDRDATA6CH1_CR_DDRCRVSSHIORVREFCONTROL_REG                   (0x00000D6C)
+  #define DDRDATA6CH1_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_OFF    ( 0)
+  #define DDRDATA6CH1_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_WID    (24)
+  #define DDRDATA6CH1_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_MSK    (0x00FFFFFF)
+  #define DDRDATA6CH1_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_MAX    (0x00FFFFFF)
+  #define DDRDATA6CH1_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_DEF    (0x00000000)
+  #define DDRDATA6CH1_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_OFF        (24)
+  #define DDRDATA6CH1_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_WID        ( 8)
+  #define DDRDATA6CH1_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_MSK        (0xFF000000)
+  #define DDRDATA6CH1_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_MAX        (0x000000FF)
+  #define DDRDATA6CH1_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_DEF        (0x00000000)
+
+#define DDRDATA6CH1_CR_DDRCRDATAOFFSETTRAIN_REG                      (0x00000D70)
+  #define DDRDATA6CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_OFF          ( 0)
+  #define DDRDATA6CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_WID          ( 6)
+  #define DDRDATA6CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MSK          (0x0000003F)
+  #define DDRDATA6CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MAX          (0x0000003F)
+  #define DDRDATA6CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_DEF          (0x00000000)
+  #define DDRDATA6CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_OFF          ( 6)
+  #define DDRDATA6CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_WID          ( 6)
+  #define DDRDATA6CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MSK          (0x00000FC0)
+  #define DDRDATA6CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MAX          (0x0000003F)
+  #define DDRDATA6CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_DEF          (0x00000000)
+  #define DDRDATA6CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_OFF           (12)
+  #define DDRDATA6CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_WID           ( 6)
+  #define DDRDATA6CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MSK           (0x0003F000)
+  #define DDRDATA6CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MAX           (0x0000003F)
+  #define DDRDATA6CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_DEF           (0x00000000)
+  #define DDRDATA6CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_OFF          (18)
+  #define DDRDATA6CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_WID          ( 6)
+  #define DDRDATA6CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MSK          (0x00FC0000)
+  #define DDRDATA6CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MAX          (0x0000003F)
+  #define DDRDATA6CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_DEF          (0x00000000)
+  #define DDRDATA6CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_OFF           (24)
+  #define DDRDATA6CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_WID           ( 7)
+  #define DDRDATA6CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MSK           (0x7F000000)
+  #define DDRDATA6CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MAX           (0x0000007F)
+  #define DDRDATA6CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_DEF           (0x00000000)
+  #define DDRDATA6CH1_CR_DDRCRDATAOFFSETTRAIN_Spare_OFF                (31)
+  #define DDRDATA6CH1_CR_DDRCRDATAOFFSETTRAIN_Spare_WID                ( 1)
+  #define DDRDATA6CH1_CR_DDRCRDATAOFFSETTRAIN_Spare_MSK                (0x80000000)
+  #define DDRDATA6CH1_CR_DDRCRDATAOFFSETTRAIN_Spare_MAX                (0x00000001)
+  #define DDRDATA6CH1_CR_DDRCRDATAOFFSETTRAIN_Spare_DEF                (0x00000000)
+
+#define DDRDATA6CH1_CR_DDRCRDATACONTROL0_REG                         (0x00000D74)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_OFF          ( 0)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_WID          ( 1)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_MSK          (0x00000001)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_MAX          (0x00000001)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_DEF          (0x00000000)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_OFF          ( 1)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_WID          ( 1)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_MSK          (0x00000002)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_MAX          (0x00000001)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_DEF          (0x00000000)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_OFF          ( 2)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_WID          ( 1)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_MSK          (0x00000004)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_MAX          (0x00000001)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_DEF          (0x00000000)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_OFF    ( 3)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_WID    ( 1)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MSK    (0x00000008)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MAX    (0x00000001)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_DEF    (0x00000000)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_TxOn_OFF                    ( 4)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_TxOn_WID                    ( 1)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_TxOn_MSK                    (0x00000010)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_TxOn_MAX                    (0x00000001)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_TxOn_DEF                    (0x00000000)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RfOn_OFF                    ( 5)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RfOn_WID                    ( 1)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RfOn_MSK                    (0x00000020)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RfOn_MAX                    (0x00000001)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RfOn_DEF                    (0x00000000)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RxPiOn_OFF                  ( 6)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RxPiOn_WID                  ( 1)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RxPiOn_MSK                  (0x00000040)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RxPiOn_MAX                  (0x00000001)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RxPiOn_DEF                  (0x00000000)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_TxPiOn_OFF                  ( 7)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_TxPiOn_WID                  ( 1)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_TxPiOn_MSK                  (0x00000080)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_TxPiOn_MAX                  (0x00000001)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_TxPiOn_DEF                  (0x00000000)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_OFF        ( 8)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_WID        ( 1)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_MSK        (0x00000100)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_MAX        (0x00000001)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_DEF        (0x00000000)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_OFF        ( 9)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_WID        ( 1)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MSK        (0x00000200)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MAX        (0x00000001)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_DEF        (0x00000000)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_TxDisable_OFF               (10)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_TxDisable_WID               ( 1)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_TxDisable_MSK               (0x00000400)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_TxDisable_MAX               (0x00000001)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_TxDisable_DEF               (0x00000000)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RxDisable_OFF               (11)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RxDisable_WID               ( 1)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RxDisable_MSK               (0x00000800)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RxDisable_MAX               (0x00000001)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RxDisable_DEF               (0x00000000)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_TxLong_OFF                  (12)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_TxLong_WID                  ( 1)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_TxLong_MSK                  (0x00001000)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_TxLong_MAX                  (0x00000001)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_TxLong_DEF                  (0x00000000)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_OFF               (13)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_WID               ( 2)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_MSK               (0x00006000)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_MAX               (0x00000003)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_DEF               (0x00000000)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RxReadPointer_OFF           (15)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RxReadPointer_WID           ( 3)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RxReadPointer_MSK           (0x00038000)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RxReadPointer_MAX           (0x00000007)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RxReadPointer_DEF           (0x00000000)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_DriverSegmentEnable_OFF     (18)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_DriverSegmentEnable_WID     ( 1)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_DriverSegmentEnable_MSK     (0x00040000)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_DriverSegmentEnable_MAX     (0x00000001)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_DriverSegmentEnable_DEF     (0x00000000)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_DataVccddqHi_OFF            (19)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_DataVccddqHi_WID            ( 1)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_DataVccddqHi_MSK            (0x00080000)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_DataVccddqHi_MAX            (0x00000001)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_DataVccddqHi_DEF            (0x00000000)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_ReadRFRd_OFF                (20)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_ReadRFRd_WID                ( 1)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_ReadRFRd_MSK                (0x00100000)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_ReadRFRd_MAX                (0x00000001)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_ReadRFRd_DEF                (0x00000000)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_ReadRFWr_OFF                (21)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_ReadRFWr_WID                ( 1)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_ReadRFWr_MSK                (0x00200000)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_ReadRFWr_MAX                (0x00000001)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_ReadRFWr_DEF                (0x00000000)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_ReadRFRank_OFF              (22)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_ReadRFRank_WID              ( 2)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_ReadRFRank_MSK              (0x00C00000)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_ReadRFRank_MAX              (0x00000003)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_ReadRFRank_DEF              (0x00000000)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_OFF              (24)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_WID              ( 1)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_MSK              (0x01000000)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_MAX              (0x00000001)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_DEF              (0x00000000)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_OdtSampOff_OFF              (25)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_OdtSampOff_WID              ( 1)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_OdtSampOff_MSK              (0x02000000)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_OdtSampOff_MAX              (0x00000001)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_OdtSampOff_DEF              (0x00000000)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_OFF        (26)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_WID        ( 1)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_MSK        (0x04000000)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_MAX        (0x00000001)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_DEF        (0x00000000)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_OFF         (27)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_WID         ( 1)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MSK         (0x08000000)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MAX         (0x00000001)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_DEF         (0x00000000)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_OFF              (28)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_WID              ( 1)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_MSK              (0x10000000)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_MAX              (0x00000001)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_DEF              (0x00000000)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_EnReadPreamble_OFF          (29)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_EnReadPreamble_WID          ( 1)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_EnReadPreamble_MSK          (0x20000000)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_EnReadPreamble_MAX          (0x00000001)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_EnReadPreamble_DEF          (0x00000000)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_OFF         (30)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_WID         ( 1)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MSK         (0x40000000)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MAX         (0x00000001)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_DEF         (0x00000000)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_OFF            (31)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_WID            ( 1)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_MSK            (0x80000000)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_MAX            (0x00000001)
+  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_DEF            (0x00000000)
+
+#define DDRDATA6CH1_CR_DDRCRVREFADJUST1_REG                          (0x00000D78)
+  #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_CAVrefCtl_OFF                ( 0)
+  #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_CAVrefCtl_WID                ( 7)
+  #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_CAVrefCtl_MSK                (0x0000007F)
+  #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_CAVrefCtl_MAX                (0x0000007F)
+  #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_CAVrefCtl_DEF                (0x00000000)
+  #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_Ch1VrefCtl_OFF               ( 7)
+  #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_Ch1VrefCtl_WID               ( 7)
+  #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_Ch1VrefCtl_MSK               (0x00003F80)
+  #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_Ch1VrefCtl_MAX               (0x0000007F)
+  #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_Ch1VrefCtl_DEF               (0x00000000)
+  #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_Ch0VrefCtl_OFF               (14)
+  #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_Ch0VrefCtl_WID               ( 7)
+  #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_Ch0VrefCtl_MSK               (0x001FC000)
+  #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_Ch0VrefCtl_MAX               (0x0000007F)
+  #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_Ch0VrefCtl_DEF               (0x00000000)
+  #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCA_OFF             (21)
+  #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCA_WID             ( 1)
+  #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCA_MSK             (0x00200000)
+  #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCA_MAX             (0x00000001)
+  #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCA_DEF             (0x00000000)
+  #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_OFF            (22)
+  #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_WID            ( 1)
+  #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_MSK            (0x00400000)
+  #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_MAX            (0x00000001)
+  #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_DEF            (0x00000000)
+  #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_OFF            (23)
+  #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_WID            ( 1)
+  #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_MSK            (0x00800000)
+  #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_MAX            (0x00000001)
+  #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_DEF            (0x00000000)
+  #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_HiZTimerCtrl_OFF             (24)
+  #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_HiZTimerCtrl_WID             ( 2)
+  #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_HiZTimerCtrl_MSK             (0x03000000)
+  #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_HiZTimerCtrl_MAX             (0x00000003)
+  #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_HiZTimerCtrl_DEF             (0x00000000)
+  #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_OFF            (26)
+  #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_WID            ( 1)
+  #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_MSK            (0x04000000)
+  #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_MAX            (0x00000001)
+  #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_DEF            (0x00000000)
+  #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_Rsvd_OFF                     (27)
+  #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_Rsvd_WID                     ( 2)
+  #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_Rsvd_MSK                     (0x18000000)
+  #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_Rsvd_MAX                     (0x00000003)
+  #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_Rsvd_DEF                     (0x00000000)
+  #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_caSlowBW_OFF                 (29)
+  #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_caSlowBW_WID                 ( 1)
+  #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_caSlowBW_MSK                 (0x20000000)
+  #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_caSlowBW_MAX                 (0x00000001)
+  #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_caSlowBW_DEF                 (0x00000000)
+  #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_ch0SlowBW_OFF                (30)
+  #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_ch0SlowBW_WID                ( 1)
+  #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_ch0SlowBW_MSK                (0x40000000)
+  #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_ch0SlowBW_MAX                (0x00000001)
+  #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_ch0SlowBW_DEF                (0x00000000)
+  #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_ch1SlowBW_OFF                (31)
+  #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_ch1SlowBW_WID                ( 1)
+  #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_ch1SlowBW_MSK                (0x80000000)
+  #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_ch1SlowBW_MAX                (0x00000001)
+  #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_ch1SlowBW_DEF                (0x00000000)
+
+#define DDRDATA7CH0_CR_RXTRAINRANK0_REG                              (0x00000E00)
+  #define DDRDATA7CH0_CR_RXTRAINRANK0_RxRcvEnPi_OFF                    ( 0)
+  #define DDRDATA7CH0_CR_RXTRAINRANK0_RxRcvEnPi_WID                    ( 9)
+  #define DDRDATA7CH0_CR_RXTRAINRANK0_RxRcvEnPi_MSK                    (0x000001FF)
+  #define DDRDATA7CH0_CR_RXTRAINRANK0_RxRcvEnPi_MAX                    (0x000001FF)
+  #define DDRDATA7CH0_CR_RXTRAINRANK0_RxDqsPPi_OFF                     ( 9)
+  #define DDRDATA7CH0_CR_RXTRAINRANK0_RxDqsPPi_WID                     ( 6)
+  #define DDRDATA7CH0_CR_RXTRAINRANK0_RxDqsPPi_MSK                     (0x00007E00)
+  #define DDRDATA7CH0_CR_RXTRAINRANK0_RxDqsPPi_MAX                     (0x0000003F)
+  #define DDRDATA7CH0_CR_RXTRAINRANK0_RxEq_OFF                         (15)
+  #define DDRDATA7CH0_CR_RXTRAINRANK0_RxEq_WID                         ( 5)
+  #define DDRDATA7CH0_CR_RXTRAINRANK0_RxEq_MSK                         (0x000F8000)
+  #define DDRDATA7CH0_CR_RXTRAINRANK0_RxEq_MAX                         (0x0000001F)
+  #define DDRDATA7CH0_CR_RXTRAINRANK0_RxDqsNPi_OFF                     (20)
+  #define DDRDATA7CH0_CR_RXTRAINRANK0_RxDqsNPi_WID                     ( 6)
+  #define DDRDATA7CH0_CR_RXTRAINRANK0_RxDqsNPi_MSK                     (0x03F00000)
+  #define DDRDATA7CH0_CR_RXTRAINRANK0_RxDqsNPi_MAX                     (0x0000003F)
+  #define DDRDATA7CH0_CR_RXTRAINRANK0_RxVref_OFF                       (26)
+  #define DDRDATA7CH0_CR_RXTRAINRANK0_RxVref_WID                       ( 6)
+  #define DDRDATA7CH0_CR_RXTRAINRANK0_RxVref_MSK                       (0xFC000000)
+  #define DDRDATA7CH0_CR_RXTRAINRANK0_RxVref_MAX                       (0x0000003F)
+
+#define DDRDATA7CH0_CR_RXTRAINRANK1_REG                              (0x00000E04)
+  #define DDRDATA7CH0_CR_RXTRAINRANK1_RxRcvEnPi_OFF                    ( 0)
+  #define DDRDATA7CH0_CR_RXTRAINRANK1_RxRcvEnPi_WID                    ( 9)
+  #define DDRDATA7CH0_CR_RXTRAINRANK1_RxRcvEnPi_MSK                    (0x000001FF)
+  #define DDRDATA7CH0_CR_RXTRAINRANK1_RxRcvEnPi_MAX                    (0x000001FF)
+  #define DDRDATA7CH0_CR_RXTRAINRANK1_RxDqsPPi_OFF                     ( 9)
+  #define DDRDATA7CH0_CR_RXTRAINRANK1_RxDqsPPi_WID                     ( 6)
+  #define DDRDATA7CH0_CR_RXTRAINRANK1_RxDqsPPi_MSK                     (0x00007E00)
+  #define DDRDATA7CH0_CR_RXTRAINRANK1_RxDqsPPi_MAX                     (0x0000003F)
+  #define DDRDATA7CH0_CR_RXTRAINRANK1_RxEq_OFF                         (15)
+  #define DDRDATA7CH0_CR_RXTRAINRANK1_RxEq_WID                         ( 5)
+  #define DDRDATA7CH0_CR_RXTRAINRANK1_RxEq_MSK                         (0x000F8000)
+  #define DDRDATA7CH0_CR_RXTRAINRANK1_RxEq_MAX                         (0x0000001F)
+  #define DDRDATA7CH0_CR_RXTRAINRANK1_RxDqsNPi_OFF                     (20)
+  #define DDRDATA7CH0_CR_RXTRAINRANK1_RxDqsNPi_WID                     ( 6)
+  #define DDRDATA7CH0_CR_RXTRAINRANK1_RxDqsNPi_MSK                     (0x03F00000)
+  #define DDRDATA7CH0_CR_RXTRAINRANK1_RxDqsNPi_MAX                     (0x0000003F)
+  #define DDRDATA7CH0_CR_RXTRAINRANK1_RxVref_OFF                       (26)
+  #define DDRDATA7CH0_CR_RXTRAINRANK1_RxVref_WID                       ( 6)
+  #define DDRDATA7CH0_CR_RXTRAINRANK1_RxVref_MSK                       (0xFC000000)
+  #define DDRDATA7CH0_CR_RXTRAINRANK1_RxVref_MAX                       (0x0000003F)
+
+#define DDRDATA7CH0_CR_RXTRAINRANK2_REG                              (0x00000E08)
+  #define DDRDATA7CH0_CR_RXTRAINRANK2_RxRcvEnPi_OFF                    ( 0)
+  #define DDRDATA7CH0_CR_RXTRAINRANK2_RxRcvEnPi_WID                    ( 9)
+  #define DDRDATA7CH0_CR_RXTRAINRANK2_RxRcvEnPi_MSK                    (0x000001FF)
+  #define DDRDATA7CH0_CR_RXTRAINRANK2_RxRcvEnPi_MAX                    (0x000001FF)
+  #define DDRDATA7CH0_CR_RXTRAINRANK2_RxDqsPPi_OFF                     ( 9)
+  #define DDRDATA7CH0_CR_RXTRAINRANK2_RxDqsPPi_WID                     ( 6)
+  #define DDRDATA7CH0_CR_RXTRAINRANK2_RxDqsPPi_MSK                     (0x00007E00)
+  #define DDRDATA7CH0_CR_RXTRAINRANK2_RxDqsPPi_MAX                     (0x0000003F)
+  #define DDRDATA7CH0_CR_RXTRAINRANK2_RxEq_OFF                         (15)
+  #define DDRDATA7CH0_CR_RXTRAINRANK2_RxEq_WID                         ( 5)
+  #define DDRDATA7CH0_CR_RXTRAINRANK2_RxEq_MSK                         (0x000F8000)
+  #define DDRDATA7CH0_CR_RXTRAINRANK2_RxEq_MAX                         (0x0000001F)
+  #define DDRDATA7CH0_CR_RXTRAINRANK2_RxDqsNPi_OFF                     (20)
+  #define DDRDATA7CH0_CR_RXTRAINRANK2_RxDqsNPi_WID                     ( 6)
+  #define DDRDATA7CH0_CR_RXTRAINRANK2_RxDqsNPi_MSK                     (0x03F00000)
+  #define DDRDATA7CH0_CR_RXTRAINRANK2_RxDqsNPi_MAX                     (0x0000003F)
+  #define DDRDATA7CH0_CR_RXTRAINRANK2_RxVref_OFF                       (26)
+  #define DDRDATA7CH0_CR_RXTRAINRANK2_RxVref_WID                       ( 6)
+  #define DDRDATA7CH0_CR_RXTRAINRANK2_RxVref_MSK                       (0xFC000000)
+  #define DDRDATA7CH0_CR_RXTRAINRANK2_RxVref_MAX                       (0x0000003F)
+
+#define DDRDATA7CH0_CR_RXTRAINRANK3_REG                              (0x00000E0C)
+  #define DDRDATA7CH0_CR_RXTRAINRANK3_RxRcvEnPi_OFF                    ( 0)
+  #define DDRDATA7CH0_CR_RXTRAINRANK3_RxRcvEnPi_WID                    ( 9)
+  #define DDRDATA7CH0_CR_RXTRAINRANK3_RxRcvEnPi_MSK                    (0x000001FF)
+  #define DDRDATA7CH0_CR_RXTRAINRANK3_RxRcvEnPi_MAX                    (0x000001FF)
+  #define DDRDATA7CH0_CR_RXTRAINRANK3_RxDqsPPi_OFF                     ( 9)
+  #define DDRDATA7CH0_CR_RXTRAINRANK3_RxDqsPPi_WID                     ( 6)
+  #define DDRDATA7CH0_CR_RXTRAINRANK3_RxDqsPPi_MSK                     (0x00007E00)
+  #define DDRDATA7CH0_CR_RXTRAINRANK3_RxDqsPPi_MAX                     (0x0000003F)
+  #define DDRDATA7CH0_CR_RXTRAINRANK3_RxEq_OFF                         (15)
+  #define DDRDATA7CH0_CR_RXTRAINRANK3_RxEq_WID                         ( 5)
+  #define DDRDATA7CH0_CR_RXTRAINRANK3_RxEq_MSK                         (0x000F8000)
+  #define DDRDATA7CH0_CR_RXTRAINRANK3_RxEq_MAX                         (0x0000001F)
+  #define DDRDATA7CH0_CR_RXTRAINRANK3_RxDqsNPi_OFF                     (20)
+  #define DDRDATA7CH0_CR_RXTRAINRANK3_RxDqsNPi_WID                     ( 6)
+  #define DDRDATA7CH0_CR_RXTRAINRANK3_RxDqsNPi_MSK                     (0x03F00000)
+  #define DDRDATA7CH0_CR_RXTRAINRANK3_RxDqsNPi_MAX                     (0x0000003F)
+  #define DDRDATA7CH0_CR_RXTRAINRANK3_RxVref_OFF                       (26)
+  #define DDRDATA7CH0_CR_RXTRAINRANK3_RxVref_WID                       ( 6)
+  #define DDRDATA7CH0_CR_RXTRAINRANK3_RxVref_MSK                       (0xFC000000)
+  #define DDRDATA7CH0_CR_RXTRAINRANK3_RxVref_MAX                       (0x0000003F)
+
+#define DDRDATA7CH0_CR_RXPERBITRANK0_REG                             (0x00000E10)
+  #define DDRDATA7CH0_CR_RXPERBITRANK0_Lane0_OFF                       ( 0)
+  #define DDRDATA7CH0_CR_RXPERBITRANK0_Lane0_WID                       ( 4)
+  #define DDRDATA7CH0_CR_RXPERBITRANK0_Lane0_MSK                       (0x0000000F)
+  #define DDRDATA7CH0_CR_RXPERBITRANK0_Lane0_MAX                       (0x0000000F)
+  #define DDRDATA7CH0_CR_RXPERBITRANK0_Lane1_OFF                       ( 4)
+  #define DDRDATA7CH0_CR_RXPERBITRANK0_Lane1_WID                       ( 4)
+  #define DDRDATA7CH0_CR_RXPERBITRANK0_Lane1_MSK                       (0x000000F0)
+  #define DDRDATA7CH0_CR_RXPERBITRANK0_Lane1_MAX                       (0x0000000F)
+  #define DDRDATA7CH0_CR_RXPERBITRANK0_Lane2_OFF                       ( 8)
+  #define DDRDATA7CH0_CR_RXPERBITRANK0_Lane2_WID                       ( 4)
+  #define DDRDATA7CH0_CR_RXPERBITRANK0_Lane2_MSK                       (0x00000F00)
+  #define DDRDATA7CH0_CR_RXPERBITRANK0_Lane2_MAX                       (0x0000000F)
+  #define DDRDATA7CH0_CR_RXPERBITRANK0_Lane3_OFF                       (12)
+  #define DDRDATA7CH0_CR_RXPERBITRANK0_Lane3_WID                       ( 4)
+  #define DDRDATA7CH0_CR_RXPERBITRANK0_Lane3_MSK                       (0x0000F000)
+  #define DDRDATA7CH0_CR_RXPERBITRANK0_Lane3_MAX                       (0x0000000F)
+  #define DDRDATA7CH0_CR_RXPERBITRANK0_Lane4_OFF                       (16)
+  #define DDRDATA7CH0_CR_RXPERBITRANK0_Lane4_WID                       ( 4)
+  #define DDRDATA7CH0_CR_RXPERBITRANK0_Lane4_MSK                       (0x000F0000)
+  #define DDRDATA7CH0_CR_RXPERBITRANK0_Lane4_MAX                       (0x0000000F)
+  #define DDRDATA7CH0_CR_RXPERBITRANK0_Lane5_OFF                       (20)
+  #define DDRDATA7CH0_CR_RXPERBITRANK0_Lane5_WID                       ( 4)
+  #define DDRDATA7CH0_CR_RXPERBITRANK0_Lane5_MSK                       (0x00F00000)
+  #define DDRDATA7CH0_CR_RXPERBITRANK0_Lane5_MAX                       (0x0000000F)
+  #define DDRDATA7CH0_CR_RXPERBITRANK0_Lane6_OFF                       (24)
+  #define DDRDATA7CH0_CR_RXPERBITRANK0_Lane6_WID                       ( 4)
+  #define DDRDATA7CH0_CR_RXPERBITRANK0_Lane6_MSK                       (0x0F000000)
+  #define DDRDATA7CH0_CR_RXPERBITRANK0_Lane6_MAX                       (0x0000000F)
+  #define DDRDATA7CH0_CR_RXPERBITRANK0_Lane7_OFF                       (28)
+  #define DDRDATA7CH0_CR_RXPERBITRANK0_Lane7_WID                       ( 4)
+  #define DDRDATA7CH0_CR_RXPERBITRANK0_Lane7_MSK                       (0xF0000000)
+  #define DDRDATA7CH0_CR_RXPERBITRANK0_Lane7_MAX                       (0x0000000F)
+
+#define DDRDATA7CH0_CR_RXPERBITRANK1_REG                             (0x00000E14)
+  #define DDRDATA7CH0_CR_RXPERBITRANK1_Lane0_OFF                       ( 0)
+  #define DDRDATA7CH0_CR_RXPERBITRANK1_Lane0_WID                       ( 4)
+  #define DDRDATA7CH0_CR_RXPERBITRANK1_Lane0_MSK                       (0x0000000F)
+  #define DDRDATA7CH0_CR_RXPERBITRANK1_Lane0_MAX                       (0x0000000F)
+  #define DDRDATA7CH0_CR_RXPERBITRANK1_Lane1_OFF                       ( 4)
+  #define DDRDATA7CH0_CR_RXPERBITRANK1_Lane1_WID                       ( 4)
+  #define DDRDATA7CH0_CR_RXPERBITRANK1_Lane1_MSK                       (0x000000F0)
+  #define DDRDATA7CH0_CR_RXPERBITRANK1_Lane1_MAX                       (0x0000000F)
+  #define DDRDATA7CH0_CR_RXPERBITRANK1_Lane2_OFF                       ( 8)
+  #define DDRDATA7CH0_CR_RXPERBITRANK1_Lane2_WID                       ( 4)
+  #define DDRDATA7CH0_CR_RXPERBITRANK1_Lane2_MSK                       (0x00000F00)
+  #define DDRDATA7CH0_CR_RXPERBITRANK1_Lane2_MAX                       (0x0000000F)
+  #define DDRDATA7CH0_CR_RXPERBITRANK1_Lane3_OFF                       (12)
+  #define DDRDATA7CH0_CR_RXPERBITRANK1_Lane3_WID                       ( 4)
+  #define DDRDATA7CH0_CR_RXPERBITRANK1_Lane3_MSK                       (0x0000F000)
+  #define DDRDATA7CH0_CR_RXPERBITRANK1_Lane3_MAX                       (0x0000000F)
+  #define DDRDATA7CH0_CR_RXPERBITRANK1_Lane4_OFF                       (16)
+  #define DDRDATA7CH0_CR_RXPERBITRANK1_Lane4_WID                       ( 4)
+  #define DDRDATA7CH0_CR_RXPERBITRANK1_Lane4_MSK                       (0x000F0000)
+  #define DDRDATA7CH0_CR_RXPERBITRANK1_Lane4_MAX                       (0x0000000F)
+  #define DDRDATA7CH0_CR_RXPERBITRANK1_Lane5_OFF                       (20)
+  #define DDRDATA7CH0_CR_RXPERBITRANK1_Lane5_WID                       ( 4)
+  #define DDRDATA7CH0_CR_RXPERBITRANK1_Lane5_MSK                       (0x00F00000)
+  #define DDRDATA7CH0_CR_RXPERBITRANK1_Lane5_MAX                       (0x0000000F)
+  #define DDRDATA7CH0_CR_RXPERBITRANK1_Lane6_OFF                       (24)
+  #define DDRDATA7CH0_CR_RXPERBITRANK1_Lane6_WID                       ( 4)
+  #define DDRDATA7CH0_CR_RXPERBITRANK1_Lane6_MSK                       (0x0F000000)
+  #define DDRDATA7CH0_CR_RXPERBITRANK1_Lane6_MAX                       (0x0000000F)
+  #define DDRDATA7CH0_CR_RXPERBITRANK1_Lane7_OFF                       (28)
+  #define DDRDATA7CH0_CR_RXPERBITRANK1_Lane7_WID                       ( 4)
+  #define DDRDATA7CH0_CR_RXPERBITRANK1_Lane7_MSK                       (0xF0000000)
+  #define DDRDATA7CH0_CR_RXPERBITRANK1_Lane7_MAX                       (0x0000000F)
+
+#define DDRDATA7CH0_CR_RXPERBITRANK2_REG                             (0x00000E18)
+  #define DDRDATA7CH0_CR_RXPERBITRANK2_Lane0_OFF                       ( 0)
+  #define DDRDATA7CH0_CR_RXPERBITRANK2_Lane0_WID                       ( 4)
+  #define DDRDATA7CH0_CR_RXPERBITRANK2_Lane0_MSK                       (0x0000000F)
+  #define DDRDATA7CH0_CR_RXPERBITRANK2_Lane0_MAX                       (0x0000000F)
+  #define DDRDATA7CH0_CR_RXPERBITRANK2_Lane1_OFF                       ( 4)
+  #define DDRDATA7CH0_CR_RXPERBITRANK2_Lane1_WID                       ( 4)
+  #define DDRDATA7CH0_CR_RXPERBITRANK2_Lane1_MSK                       (0x000000F0)
+  #define DDRDATA7CH0_CR_RXPERBITRANK2_Lane1_MAX                       (0x0000000F)
+  #define DDRDATA7CH0_CR_RXPERBITRANK2_Lane2_OFF                       ( 8)
+  #define DDRDATA7CH0_CR_RXPERBITRANK2_Lane2_WID                       ( 4)
+  #define DDRDATA7CH0_CR_RXPERBITRANK2_Lane2_MSK                       (0x00000F00)
+  #define DDRDATA7CH0_CR_RXPERBITRANK2_Lane2_MAX                       (0x0000000F)
+  #define DDRDATA7CH0_CR_RXPERBITRANK2_Lane3_OFF                       (12)
+  #define DDRDATA7CH0_CR_RXPERBITRANK2_Lane3_WID                       ( 4)
+  #define DDRDATA7CH0_CR_RXPERBITRANK2_Lane3_MSK                       (0x0000F000)
+  #define DDRDATA7CH0_CR_RXPERBITRANK2_Lane3_MAX                       (0x0000000F)
+  #define DDRDATA7CH0_CR_RXPERBITRANK2_Lane4_OFF                       (16)
+  #define DDRDATA7CH0_CR_RXPERBITRANK2_Lane4_WID                       ( 4)
+  #define DDRDATA7CH0_CR_RXPERBITRANK2_Lane4_MSK                       (0x000F0000)
+  #define DDRDATA7CH0_CR_RXPERBITRANK2_Lane4_MAX                       (0x0000000F)
+  #define DDRDATA7CH0_CR_RXPERBITRANK2_Lane5_OFF                       (20)
+  #define DDRDATA7CH0_CR_RXPERBITRANK2_Lane5_WID                       ( 4)
+  #define DDRDATA7CH0_CR_RXPERBITRANK2_Lane5_MSK                       (0x00F00000)
+  #define DDRDATA7CH0_CR_RXPERBITRANK2_Lane5_MAX                       (0x0000000F)
+  #define DDRDATA7CH0_CR_RXPERBITRANK2_Lane6_OFF                       (24)
+  #define DDRDATA7CH0_CR_RXPERBITRANK2_Lane6_WID                       ( 4)
+  #define DDRDATA7CH0_CR_RXPERBITRANK2_Lane6_MSK                       (0x0F000000)
+  #define DDRDATA7CH0_CR_RXPERBITRANK2_Lane6_MAX                       (0x0000000F)
+  #define DDRDATA7CH0_CR_RXPERBITRANK2_Lane7_OFF                       (28)
+  #define DDRDATA7CH0_CR_RXPERBITRANK2_Lane7_WID                       ( 4)
+  #define DDRDATA7CH0_CR_RXPERBITRANK2_Lane7_MSK                       (0xF0000000)
+  #define DDRDATA7CH0_CR_RXPERBITRANK2_Lane7_MAX                       (0x0000000F)
+
+#define DDRDATA7CH0_CR_RXPERBITRANK3_REG                             (0x00000E1C)
+  #define DDRDATA7CH0_CR_RXPERBITRANK3_Lane0_OFF                       ( 0)
+  #define DDRDATA7CH0_CR_RXPERBITRANK3_Lane0_WID                       ( 4)
+  #define DDRDATA7CH0_CR_RXPERBITRANK3_Lane0_MSK                       (0x0000000F)
+  #define DDRDATA7CH0_CR_RXPERBITRANK3_Lane0_MAX                       (0x0000000F)
+  #define DDRDATA7CH0_CR_RXPERBITRANK3_Lane1_OFF                       ( 4)
+  #define DDRDATA7CH0_CR_RXPERBITRANK3_Lane1_WID                       ( 4)
+  #define DDRDATA7CH0_CR_RXPERBITRANK3_Lane1_MSK                       (0x000000F0)
+  #define DDRDATA7CH0_CR_RXPERBITRANK3_Lane1_MAX                       (0x0000000F)
+  #define DDRDATA7CH0_CR_RXPERBITRANK3_Lane2_OFF                       ( 8)
+  #define DDRDATA7CH0_CR_RXPERBITRANK3_Lane2_WID                       ( 4)
+  #define DDRDATA7CH0_CR_RXPERBITRANK3_Lane2_MSK                       (0x00000F00)
+  #define DDRDATA7CH0_CR_RXPERBITRANK3_Lane2_MAX                       (0x0000000F)
+  #define DDRDATA7CH0_CR_RXPERBITRANK3_Lane3_OFF                       (12)
+  #define DDRDATA7CH0_CR_RXPERBITRANK3_Lane3_WID                       ( 4)
+  #define DDRDATA7CH0_CR_RXPERBITRANK3_Lane3_MSK                       (0x0000F000)
+  #define DDRDATA7CH0_CR_RXPERBITRANK3_Lane3_MAX                       (0x0000000F)
+  #define DDRDATA7CH0_CR_RXPERBITRANK3_Lane4_OFF                       (16)
+  #define DDRDATA7CH0_CR_RXPERBITRANK3_Lane4_WID                       ( 4)
+  #define DDRDATA7CH0_CR_RXPERBITRANK3_Lane4_MSK                       (0x000F0000)
+  #define DDRDATA7CH0_CR_RXPERBITRANK3_Lane4_MAX                       (0x0000000F)
+  #define DDRDATA7CH0_CR_RXPERBITRANK3_Lane5_OFF                       (20)
+  #define DDRDATA7CH0_CR_RXPERBITRANK3_Lane5_WID                       ( 4)
+  #define DDRDATA7CH0_CR_RXPERBITRANK3_Lane5_MSK                       (0x00F00000)
+  #define DDRDATA7CH0_CR_RXPERBITRANK3_Lane5_MAX                       (0x0000000F)
+  #define DDRDATA7CH0_CR_RXPERBITRANK3_Lane6_OFF                       (24)
+  #define DDRDATA7CH0_CR_RXPERBITRANK3_Lane6_WID                       ( 4)
+  #define DDRDATA7CH0_CR_RXPERBITRANK3_Lane6_MSK                       (0x0F000000)
+  #define DDRDATA7CH0_CR_RXPERBITRANK3_Lane6_MAX                       (0x0000000F)
+  #define DDRDATA7CH0_CR_RXPERBITRANK3_Lane7_OFF                       (28)
+  #define DDRDATA7CH0_CR_RXPERBITRANK3_Lane7_WID                       ( 4)
+  #define DDRDATA7CH0_CR_RXPERBITRANK3_Lane7_MSK                       (0xF0000000)
+  #define DDRDATA7CH0_CR_RXPERBITRANK3_Lane7_MAX                       (0x0000000F)
+
+#define DDRDATA7CH0_CR_TXTRAINRANK0_REG                              (0x00000E20)
+  #define DDRDATA7CH0_CR_TXTRAINRANK0_TxDqDelay_OFF                    ( 0)
+  #define DDRDATA7CH0_CR_TXTRAINRANK0_TxDqDelay_WID                    ( 9)
+  #define DDRDATA7CH0_CR_TXTRAINRANK0_TxDqDelay_MSK                    (0x000001FF)
+  #define DDRDATA7CH0_CR_TXTRAINRANK0_TxDqDelay_MAX                    (0x000001FF)
+  #define DDRDATA7CH0_CR_TXTRAINRANK0_TxDqsDelay_OFF                   ( 9)
+  #define DDRDATA7CH0_CR_TXTRAINRANK0_TxDqsDelay_WID                   ( 9)
+  #define DDRDATA7CH0_CR_TXTRAINRANK0_TxDqsDelay_MSK                   (0x0003FE00)
+  #define DDRDATA7CH0_CR_TXTRAINRANK0_TxDqsDelay_MAX                   (0x000001FF)
+  #define DDRDATA7CH0_CR_TXTRAINRANK0_Spare0_OFF                       (18)
+  #define DDRDATA7CH0_CR_TXTRAINRANK0_Spare0_WID                       ( 2)
+  #define DDRDATA7CH0_CR_TXTRAINRANK0_Spare0_MSK                       (0x000C0000)
+  #define DDRDATA7CH0_CR_TXTRAINRANK0_Spare0_MAX                       (0x00000003)
+  #define DDRDATA7CH0_CR_TXTRAINRANK0_TxEqualization_OFF               (20)
+  #define DDRDATA7CH0_CR_TXTRAINRANK0_TxEqualization_WID               ( 6)
+  #define DDRDATA7CH0_CR_TXTRAINRANK0_TxEqualization_MSK               (0x03F00000)
+  #define DDRDATA7CH0_CR_TXTRAINRANK0_TxEqualization_MAX               (0x0000003F)
+  #define DDRDATA7CH0_CR_TXTRAINRANK0_Spare1_OFF                       (26)
+  #define DDRDATA7CH0_CR_TXTRAINRANK0_Spare1_WID                       ( 6)
+  #define DDRDATA7CH0_CR_TXTRAINRANK0_Spare1_MSK                       (0xFC000000)
+  #define DDRDATA7CH0_CR_TXTRAINRANK0_Spare1_MAX                       (0x0000003F)
+
+#define DDRDATA7CH0_CR_TXTRAINRANK1_REG                              (0x00000E24)
+  #define DDRDATA7CH0_CR_TXTRAINRANK1_TxDqDelay_OFF                    ( 0)
+  #define DDRDATA7CH0_CR_TXTRAINRANK1_TxDqDelay_WID                    ( 9)
+  #define DDRDATA7CH0_CR_TXTRAINRANK1_TxDqDelay_MSK                    (0x000001FF)
+  #define DDRDATA7CH0_CR_TXTRAINRANK1_TxDqDelay_MAX                    (0x000001FF)
+  #define DDRDATA7CH0_CR_TXTRAINRANK1_TxDqsDelay_OFF                   ( 9)
+  #define DDRDATA7CH0_CR_TXTRAINRANK1_TxDqsDelay_WID                   ( 9)
+  #define DDRDATA7CH0_CR_TXTRAINRANK1_TxDqsDelay_MSK                   (0x0003FE00)
+  #define DDRDATA7CH0_CR_TXTRAINRANK1_TxDqsDelay_MAX                   (0x000001FF)
+  #define DDRDATA7CH0_CR_TXTRAINRANK1_Spare0_OFF                       (18)
+  #define DDRDATA7CH0_CR_TXTRAINRANK1_Spare0_WID                       ( 2)
+  #define DDRDATA7CH0_CR_TXTRAINRANK1_Spare0_MSK                       (0x000C0000)
+  #define DDRDATA7CH0_CR_TXTRAINRANK1_Spare0_MAX                       (0x00000003)
+  #define DDRDATA7CH0_CR_TXTRAINRANK1_TxEqualization_OFF               (20)
+  #define DDRDATA7CH0_CR_TXTRAINRANK1_TxEqualization_WID               ( 6)
+  #define DDRDATA7CH0_CR_TXTRAINRANK1_TxEqualization_MSK               (0x03F00000)
+  #define DDRDATA7CH0_CR_TXTRAINRANK1_TxEqualization_MAX               (0x0000003F)
+  #define DDRDATA7CH0_CR_TXTRAINRANK1_Spare1_OFF                       (26)
+  #define DDRDATA7CH0_CR_TXTRAINRANK1_Spare1_WID                       ( 6)
+  #define DDRDATA7CH0_CR_TXTRAINRANK1_Spare1_MSK                       (0xFC000000)
+  #define DDRDATA7CH0_CR_TXTRAINRANK1_Spare1_MAX                       (0x0000003F)
+
+#define DDRDATA7CH0_CR_TXTRAINRANK2_REG                              (0x00000E28)
+  #define DDRDATA7CH0_CR_TXTRAINRANK2_TxDqDelay_OFF                    ( 0)
+  #define DDRDATA7CH0_CR_TXTRAINRANK2_TxDqDelay_WID                    ( 9)
+  #define DDRDATA7CH0_CR_TXTRAINRANK2_TxDqDelay_MSK                    (0x000001FF)
+  #define DDRDATA7CH0_CR_TXTRAINRANK2_TxDqDelay_MAX                    (0x000001FF)
+  #define DDRDATA7CH0_CR_TXTRAINRANK2_TxDqsDelay_OFF                   ( 9)
+  #define DDRDATA7CH0_CR_TXTRAINRANK2_TxDqsDelay_WID                   ( 9)
+  #define DDRDATA7CH0_CR_TXTRAINRANK2_TxDqsDelay_MSK                   (0x0003FE00)
+  #define DDRDATA7CH0_CR_TXTRAINRANK2_TxDqsDelay_MAX                   (0x000001FF)
+  #define DDRDATA7CH0_CR_TXTRAINRANK2_Spare0_OFF                       (18)
+  #define DDRDATA7CH0_CR_TXTRAINRANK2_Spare0_WID                       ( 2)
+  #define DDRDATA7CH0_CR_TXTRAINRANK2_Spare0_MSK                       (0x000C0000)
+  #define DDRDATA7CH0_CR_TXTRAINRANK2_Spare0_MAX                       (0x00000003)
+  #define DDRDATA7CH0_CR_TXTRAINRANK2_TxEqualization_OFF               (20)
+  #define DDRDATA7CH0_CR_TXTRAINRANK2_TxEqualization_WID               ( 6)
+  #define DDRDATA7CH0_CR_TXTRAINRANK2_TxEqualization_MSK               (0x03F00000)
+  #define DDRDATA7CH0_CR_TXTRAINRANK2_TxEqualization_MAX               (0x0000003F)
+  #define DDRDATA7CH0_CR_TXTRAINRANK2_Spare1_OFF                       (26)
+  #define DDRDATA7CH0_CR_TXTRAINRANK2_Spare1_WID                       ( 6)
+  #define DDRDATA7CH0_CR_TXTRAINRANK2_Spare1_MSK                       (0xFC000000)
+  #define DDRDATA7CH0_CR_TXTRAINRANK2_Spare1_MAX                       (0x0000003F)
+
+#define DDRDATA7CH0_CR_TXTRAINRANK3_REG                              (0x00000E2C)
+  #define DDRDATA7CH0_CR_TXTRAINRANK3_TxDqDelay_OFF                    ( 0)
+  #define DDRDATA7CH0_CR_TXTRAINRANK3_TxDqDelay_WID                    ( 9)
+  #define DDRDATA7CH0_CR_TXTRAINRANK3_TxDqDelay_MSK                    (0x000001FF)
+  #define DDRDATA7CH0_CR_TXTRAINRANK3_TxDqDelay_MAX                    (0x000001FF)
+  #define DDRDATA7CH0_CR_TXTRAINRANK3_TxDqsDelay_OFF                   ( 9)
+  #define DDRDATA7CH0_CR_TXTRAINRANK3_TxDqsDelay_WID                   ( 9)
+  #define DDRDATA7CH0_CR_TXTRAINRANK3_TxDqsDelay_MSK                   (0x0003FE00)
+  #define DDRDATA7CH0_CR_TXTRAINRANK3_TxDqsDelay_MAX                   (0x000001FF)
+  #define DDRDATA7CH0_CR_TXTRAINRANK3_Spare0_OFF                       (18)
+  #define DDRDATA7CH0_CR_TXTRAINRANK3_Spare0_WID                       ( 2)
+  #define DDRDATA7CH0_CR_TXTRAINRANK3_Spare0_MSK                       (0x000C0000)
+  #define DDRDATA7CH0_CR_TXTRAINRANK3_Spare0_MAX                       (0x00000003)
+  #define DDRDATA7CH0_CR_TXTRAINRANK3_TxEqualization_OFF               (20)
+  #define DDRDATA7CH0_CR_TXTRAINRANK3_TxEqualization_WID               ( 6)
+  #define DDRDATA7CH0_CR_TXTRAINRANK3_TxEqualization_MSK               (0x03F00000)
+  #define DDRDATA7CH0_CR_TXTRAINRANK3_TxEqualization_MAX               (0x0000003F)
+  #define DDRDATA7CH0_CR_TXTRAINRANK3_Spare1_OFF                       (26)
+  #define DDRDATA7CH0_CR_TXTRAINRANK3_Spare1_WID                       ( 6)
+  #define DDRDATA7CH0_CR_TXTRAINRANK3_Spare1_MSK                       (0xFC000000)
+  #define DDRDATA7CH0_CR_TXTRAINRANK3_Spare1_MAX                       (0x0000003F)
+
+#define DDRDATA7CH0_CR_TXPERBITRANK0_REG                             (0x00000E30)
+  #define DDRDATA7CH0_CR_TXPERBITRANK0_Lane0_OFF                       ( 0)
+  #define DDRDATA7CH0_CR_TXPERBITRANK0_Lane0_WID                       ( 4)
+  #define DDRDATA7CH0_CR_TXPERBITRANK0_Lane0_MSK                       (0x0000000F)
+  #define DDRDATA7CH0_CR_TXPERBITRANK0_Lane0_MAX                       (0x0000000F)
+  #define DDRDATA7CH0_CR_TXPERBITRANK0_Lane1_OFF                       ( 4)
+  #define DDRDATA7CH0_CR_TXPERBITRANK0_Lane1_WID                       ( 4)
+  #define DDRDATA7CH0_CR_TXPERBITRANK0_Lane1_MSK                       (0x000000F0)
+  #define DDRDATA7CH0_CR_TXPERBITRANK0_Lane1_MAX                       (0x0000000F)
+  #define DDRDATA7CH0_CR_TXPERBITRANK0_Lane2_OFF                       ( 8)
+  #define DDRDATA7CH0_CR_TXPERBITRANK0_Lane2_WID                       ( 4)
+  #define DDRDATA7CH0_CR_TXPERBITRANK0_Lane2_MSK                       (0x00000F00)
+  #define DDRDATA7CH0_CR_TXPERBITRANK0_Lane2_MAX                       (0x0000000F)
+  #define DDRDATA7CH0_CR_TXPERBITRANK0_Lane3_OFF                       (12)
+  #define DDRDATA7CH0_CR_TXPERBITRANK0_Lane3_WID                       ( 4)
+  #define DDRDATA7CH0_CR_TXPERBITRANK0_Lane3_MSK                       (0x0000F000)
+  #define DDRDATA7CH0_CR_TXPERBITRANK0_Lane3_MAX                       (0x0000000F)
+  #define DDRDATA7CH0_CR_TXPERBITRANK0_Lane4_OFF                       (16)
+  #define DDRDATA7CH0_CR_TXPERBITRANK0_Lane4_WID                       ( 4)
+  #define DDRDATA7CH0_CR_TXPERBITRANK0_Lane4_MSK                       (0x000F0000)
+  #define DDRDATA7CH0_CR_TXPERBITRANK0_Lane4_MAX                       (0x0000000F)
+  #define DDRDATA7CH0_CR_TXPERBITRANK0_Lane5_OFF                       (20)
+  #define DDRDATA7CH0_CR_TXPERBITRANK0_Lane5_WID                       ( 4)
+  #define DDRDATA7CH0_CR_TXPERBITRANK0_Lane5_MSK                       (0x00F00000)
+  #define DDRDATA7CH0_CR_TXPERBITRANK0_Lane5_MAX                       (0x0000000F)
+  #define DDRDATA7CH0_CR_TXPERBITRANK0_Lane6_OFF                       (24)
+  #define DDRDATA7CH0_CR_TXPERBITRANK0_Lane6_WID                       ( 4)
+  #define DDRDATA7CH0_CR_TXPERBITRANK0_Lane6_MSK                       (0x0F000000)
+  #define DDRDATA7CH0_CR_TXPERBITRANK0_Lane6_MAX                       (0x0000000F)
+  #define DDRDATA7CH0_CR_TXPERBITRANK0_Lane7_OFF                       (28)
+  #define DDRDATA7CH0_CR_TXPERBITRANK0_Lane7_WID                       ( 4)
+  #define DDRDATA7CH0_CR_TXPERBITRANK0_Lane7_MSK                       (0xF0000000)
+  #define DDRDATA7CH0_CR_TXPERBITRANK0_Lane7_MAX                       (0x0000000F)
+
+#define DDRDATA7CH0_CR_TXPERBITRANK1_REG                             (0x00000E34)
+  #define DDRDATA7CH0_CR_TXPERBITRANK1_Lane0_OFF                       ( 0)
+  #define DDRDATA7CH0_CR_TXPERBITRANK1_Lane0_WID                       ( 4)
+  #define DDRDATA7CH0_CR_TXPERBITRANK1_Lane0_MSK                       (0x0000000F)
+  #define DDRDATA7CH0_CR_TXPERBITRANK1_Lane0_MAX                       (0x0000000F)
+  #define DDRDATA7CH0_CR_TXPERBITRANK1_Lane1_OFF                       ( 4)
+  #define DDRDATA7CH0_CR_TXPERBITRANK1_Lane1_WID                       ( 4)
+  #define DDRDATA7CH0_CR_TXPERBITRANK1_Lane1_MSK                       (0x000000F0)
+  #define DDRDATA7CH0_CR_TXPERBITRANK1_Lane1_MAX                       (0x0000000F)
+  #define DDRDATA7CH0_CR_TXPERBITRANK1_Lane2_OFF                       ( 8)
+  #define DDRDATA7CH0_CR_TXPERBITRANK1_Lane2_WID                       ( 4)
+  #define DDRDATA7CH0_CR_TXPERBITRANK1_Lane2_MSK                       (0x00000F00)
+  #define DDRDATA7CH0_CR_TXPERBITRANK1_Lane2_MAX                       (0x0000000F)
+  #define DDRDATA7CH0_CR_TXPERBITRANK1_Lane3_OFF                       (12)
+  #define DDRDATA7CH0_CR_TXPERBITRANK1_Lane3_WID                       ( 4)
+  #define DDRDATA7CH0_CR_TXPERBITRANK1_Lane3_MSK                       (0x0000F000)
+  #define DDRDATA7CH0_CR_TXPERBITRANK1_Lane3_MAX                       (0x0000000F)
+  #define DDRDATA7CH0_CR_TXPERBITRANK1_Lane4_OFF                       (16)
+  #define DDRDATA7CH0_CR_TXPERBITRANK1_Lane4_WID                       ( 4)
+  #define DDRDATA7CH0_CR_TXPERBITRANK1_Lane4_MSK                       (0x000F0000)
+  #define DDRDATA7CH0_CR_TXPERBITRANK1_Lane4_MAX                       (0x0000000F)
+  #define DDRDATA7CH0_CR_TXPERBITRANK1_Lane5_OFF                       (20)
+  #define DDRDATA7CH0_CR_TXPERBITRANK1_Lane5_WID                       ( 4)
+  #define DDRDATA7CH0_CR_TXPERBITRANK1_Lane5_MSK                       (0x00F00000)
+  #define DDRDATA7CH0_CR_TXPERBITRANK1_Lane5_MAX                       (0x0000000F)
+  #define DDRDATA7CH0_CR_TXPERBITRANK1_Lane6_OFF                       (24)
+  #define DDRDATA7CH0_CR_TXPERBITRANK1_Lane6_WID                       ( 4)
+  #define DDRDATA7CH0_CR_TXPERBITRANK1_Lane6_MSK                       (0x0F000000)
+  #define DDRDATA7CH0_CR_TXPERBITRANK1_Lane6_MAX                       (0x0000000F)
+  #define DDRDATA7CH0_CR_TXPERBITRANK1_Lane7_OFF                       (28)
+  #define DDRDATA7CH0_CR_TXPERBITRANK1_Lane7_WID                       ( 4)
+  #define DDRDATA7CH0_CR_TXPERBITRANK1_Lane7_MSK                       (0xF0000000)
+  #define DDRDATA7CH0_CR_TXPERBITRANK1_Lane7_MAX                       (0x0000000F)
+
+#define DDRDATA7CH0_CR_TXPERBITRANK2_REG                             (0x00000E38)
+  #define DDRDATA7CH0_CR_TXPERBITRANK2_Lane0_OFF                       ( 0)
+  #define DDRDATA7CH0_CR_TXPERBITRANK2_Lane0_WID                       ( 4)
+  #define DDRDATA7CH0_CR_TXPERBITRANK2_Lane0_MSK                       (0x0000000F)
+  #define DDRDATA7CH0_CR_TXPERBITRANK2_Lane0_MAX                       (0x0000000F)
+  #define DDRDATA7CH0_CR_TXPERBITRANK2_Lane1_OFF                       ( 4)
+  #define DDRDATA7CH0_CR_TXPERBITRANK2_Lane1_WID                       ( 4)
+  #define DDRDATA7CH0_CR_TXPERBITRANK2_Lane1_MSK                       (0x000000F0)
+  #define DDRDATA7CH0_CR_TXPERBITRANK2_Lane1_MAX                       (0x0000000F)
+  #define DDRDATA7CH0_CR_TXPERBITRANK2_Lane2_OFF                       ( 8)
+  #define DDRDATA7CH0_CR_TXPERBITRANK2_Lane2_WID                       ( 4)
+  #define DDRDATA7CH0_CR_TXPERBITRANK2_Lane2_MSK                       (0x00000F00)
+  #define DDRDATA7CH0_CR_TXPERBITRANK2_Lane2_MAX                       (0x0000000F)
+  #define DDRDATA7CH0_CR_TXPERBITRANK2_Lane3_OFF                       (12)
+  #define DDRDATA7CH0_CR_TXPERBITRANK2_Lane3_WID                       ( 4)
+  #define DDRDATA7CH0_CR_TXPERBITRANK2_Lane3_MSK                       (0x0000F000)
+  #define DDRDATA7CH0_CR_TXPERBITRANK2_Lane3_MAX                       (0x0000000F)
+  #define DDRDATA7CH0_CR_TXPERBITRANK2_Lane4_OFF                       (16)
+  #define DDRDATA7CH0_CR_TXPERBITRANK2_Lane4_WID                       ( 4)
+  #define DDRDATA7CH0_CR_TXPERBITRANK2_Lane4_MSK                       (0x000F0000)
+  #define DDRDATA7CH0_CR_TXPERBITRANK2_Lane4_MAX                       (0x0000000F)
+  #define DDRDATA7CH0_CR_TXPERBITRANK2_Lane5_OFF                       (20)
+  #define DDRDATA7CH0_CR_TXPERBITRANK2_Lane5_WID                       ( 4)
+  #define DDRDATA7CH0_CR_TXPERBITRANK2_Lane5_MSK                       (0x00F00000)
+  #define DDRDATA7CH0_CR_TXPERBITRANK2_Lane5_MAX                       (0x0000000F)
+  #define DDRDATA7CH0_CR_TXPERBITRANK2_Lane6_OFF                       (24)
+  #define DDRDATA7CH0_CR_TXPERBITRANK2_Lane6_WID                       ( 4)
+  #define DDRDATA7CH0_CR_TXPERBITRANK2_Lane6_MSK                       (0x0F000000)
+  #define DDRDATA7CH0_CR_TXPERBITRANK2_Lane6_MAX                       (0x0000000F)
+  #define DDRDATA7CH0_CR_TXPERBITRANK2_Lane7_OFF                       (28)
+  #define DDRDATA7CH0_CR_TXPERBITRANK2_Lane7_WID                       ( 4)
+  #define DDRDATA7CH0_CR_TXPERBITRANK2_Lane7_MSK                       (0xF0000000)
+  #define DDRDATA7CH0_CR_TXPERBITRANK2_Lane7_MAX                       (0x0000000F)
+
+#define DDRDATA7CH0_CR_TXPERBITRANK3_REG                             (0x00000E3C)
+  #define DDRDATA7CH0_CR_TXPERBITRANK3_Lane0_OFF                       ( 0)
+  #define DDRDATA7CH0_CR_TXPERBITRANK3_Lane0_WID                       ( 4)
+  #define DDRDATA7CH0_CR_TXPERBITRANK3_Lane0_MSK                       (0x0000000F)
+  #define DDRDATA7CH0_CR_TXPERBITRANK3_Lane0_MAX                       (0x0000000F)
+  #define DDRDATA7CH0_CR_TXPERBITRANK3_Lane1_OFF                       ( 4)
+  #define DDRDATA7CH0_CR_TXPERBITRANK3_Lane1_WID                       ( 4)
+  #define DDRDATA7CH0_CR_TXPERBITRANK3_Lane1_MSK                       (0x000000F0)
+  #define DDRDATA7CH0_CR_TXPERBITRANK3_Lane1_MAX                       (0x0000000F)
+  #define DDRDATA7CH0_CR_TXPERBITRANK3_Lane2_OFF                       ( 8)
+  #define DDRDATA7CH0_CR_TXPERBITRANK3_Lane2_WID                       ( 4)
+  #define DDRDATA7CH0_CR_TXPERBITRANK3_Lane2_MSK                       (0x00000F00)
+  #define DDRDATA7CH0_CR_TXPERBITRANK3_Lane2_MAX                       (0x0000000F)
+  #define DDRDATA7CH0_CR_TXPERBITRANK3_Lane3_OFF                       (12)
+  #define DDRDATA7CH0_CR_TXPERBITRANK3_Lane3_WID                       ( 4)
+  #define DDRDATA7CH0_CR_TXPERBITRANK3_Lane3_MSK                       (0x0000F000)
+  #define DDRDATA7CH0_CR_TXPERBITRANK3_Lane3_MAX                       (0x0000000F)
+  #define DDRDATA7CH0_CR_TXPERBITRANK3_Lane4_OFF                       (16)
+  #define DDRDATA7CH0_CR_TXPERBITRANK3_Lane4_WID                       ( 4)
+  #define DDRDATA7CH0_CR_TXPERBITRANK3_Lane4_MSK                       (0x000F0000)
+  #define DDRDATA7CH0_CR_TXPERBITRANK3_Lane4_MAX                       (0x0000000F)
+  #define DDRDATA7CH0_CR_TXPERBITRANK3_Lane5_OFF                       (20)
+  #define DDRDATA7CH0_CR_TXPERBITRANK3_Lane5_WID                       ( 4)
+  #define DDRDATA7CH0_CR_TXPERBITRANK3_Lane5_MSK                       (0x00F00000)
+  #define DDRDATA7CH0_CR_TXPERBITRANK3_Lane5_MAX                       (0x0000000F)
+  #define DDRDATA7CH0_CR_TXPERBITRANK3_Lane6_OFF                       (24)
+  #define DDRDATA7CH0_CR_TXPERBITRANK3_Lane6_WID                       ( 4)
+  #define DDRDATA7CH0_CR_TXPERBITRANK3_Lane6_MSK                       (0x0F000000)
+  #define DDRDATA7CH0_CR_TXPERBITRANK3_Lane6_MAX                       (0x0000000F)
+  #define DDRDATA7CH0_CR_TXPERBITRANK3_Lane7_OFF                       (28)
+  #define DDRDATA7CH0_CR_TXPERBITRANK3_Lane7_WID                       ( 4)
+  #define DDRDATA7CH0_CR_TXPERBITRANK3_Lane7_MSK                       (0xF0000000)
+  #define DDRDATA7CH0_CR_TXPERBITRANK3_Lane7_MAX                       (0x0000000F)
+
+#define DDRDATA7CH0_CR_RCOMPDATA0_REG                                (0x00000E40)
+  #define DDRDATA7CH0_CR_RCOMPDATA0_RcompDrvUp_OFF                     ( 0)
+  #define DDRDATA7CH0_CR_RCOMPDATA0_RcompDrvUp_WID                     ( 6)
+  #define DDRDATA7CH0_CR_RCOMPDATA0_RcompDrvUp_MSK                     (0x0000003F)
+  #define DDRDATA7CH0_CR_RCOMPDATA0_RcompDrvUp_MAX                     (0x0000003F)
+  #define DDRDATA7CH0_CR_RCOMPDATA0_Spare0_OFF                         ( 6)
+  #define DDRDATA7CH0_CR_RCOMPDATA0_Spare0_WID                         ( 3)
+  #define DDRDATA7CH0_CR_RCOMPDATA0_Spare0_MSK                         (0x000001C0)
+  #define DDRDATA7CH0_CR_RCOMPDATA0_Spare0_MAX                         (0x00000007)
+  #define DDRDATA7CH0_CR_RCOMPDATA0_RcompDrvDown_OFF                   ( 9)
+  #define DDRDATA7CH0_CR_RCOMPDATA0_RcompDrvDown_WID                   ( 6)
+  #define DDRDATA7CH0_CR_RCOMPDATA0_RcompDrvDown_MSK                   (0x00007E00)
+  #define DDRDATA7CH0_CR_RCOMPDATA0_RcompDrvDown_MAX                   (0x0000003F)
+  #define DDRDATA7CH0_CR_RCOMPDATA0_VTComp_OFF                         (15)
+  #define DDRDATA7CH0_CR_RCOMPDATA0_VTComp_WID                         ( 5)
+  #define DDRDATA7CH0_CR_RCOMPDATA0_VTComp_MSK                         (0x000F8000)
+  #define DDRDATA7CH0_CR_RCOMPDATA0_VTComp_MAX                         (0x0000001F)
+  #define DDRDATA7CH0_CR_RCOMPDATA0_TcoComp_OFF                        (20)
+  #define DDRDATA7CH0_CR_RCOMPDATA0_TcoComp_WID                        ( 6)
+  #define DDRDATA7CH0_CR_RCOMPDATA0_TcoComp_MSK                        (0x03F00000)
+  #define DDRDATA7CH0_CR_RCOMPDATA0_TcoComp_MAX                        (0x0000003F)
+  #define DDRDATA7CH0_CR_RCOMPDATA0_SlewRateComp_OFF                   (26)
+  #define DDRDATA7CH0_CR_RCOMPDATA0_SlewRateComp_WID                   ( 5)
+  #define DDRDATA7CH0_CR_RCOMPDATA0_SlewRateComp_MSK                   (0x7C000000)
+  #define DDRDATA7CH0_CR_RCOMPDATA0_SlewRateComp_MAX                   (0x0000001F)
+  #define DDRDATA7CH0_CR_RCOMPDATA0_Spare2_OFF                         (31)
+  #define DDRDATA7CH0_CR_RCOMPDATA0_Spare2_WID                         ( 1)
+  #define DDRDATA7CH0_CR_RCOMPDATA0_Spare2_MSK                         (0x80000000)
+  #define DDRDATA7CH0_CR_RCOMPDATA0_Spare2_MAX                         (0x00000001)
+
+#define DDRDATA7CH0_CR_RCOMPDATA1_REG                                (0x00000E44)
+  #define DDRDATA7CH0_CR_RCOMPDATA1_RcompOdtUp_OFF                     ( 0)
+  #define DDRDATA7CH0_CR_RCOMPDATA1_RcompOdtUp_WID                     ( 6)
+  #define DDRDATA7CH0_CR_RCOMPDATA1_RcompOdtUp_MSK                     (0x0000003F)
+  #define DDRDATA7CH0_CR_RCOMPDATA1_RcompOdtUp_MAX                     (0x0000003F)
+  #define DDRDATA7CH0_CR_RCOMPDATA1_Spare0_OFF                         ( 6)
+  #define DDRDATA7CH0_CR_RCOMPDATA1_Spare0_WID                         ( 3)
+  #define DDRDATA7CH0_CR_RCOMPDATA1_Spare0_MSK                         (0x000001C0)
+  #define DDRDATA7CH0_CR_RCOMPDATA1_Spare0_MAX                         (0x00000007)
+  #define DDRDATA7CH0_CR_RCOMPDATA1_RcompOdtDown_OFF                   ( 9)
+  #define DDRDATA7CH0_CR_RCOMPDATA1_RcompOdtDown_WID                   ( 6)
+  #define DDRDATA7CH0_CR_RCOMPDATA1_RcompOdtDown_MSK                   (0x00007E00)
+  #define DDRDATA7CH0_CR_RCOMPDATA1_RcompOdtDown_MAX                   (0x0000003F)
+  #define DDRDATA7CH0_CR_RCOMPDATA1_Spare1_OFF                         (15)
+  #define DDRDATA7CH0_CR_RCOMPDATA1_Spare1_WID                         ( 1)
+  #define DDRDATA7CH0_CR_RCOMPDATA1_Spare1_MSK                         (0x00008000)
+  #define DDRDATA7CH0_CR_RCOMPDATA1_Spare1_MAX                         (0x00000001)
+  #define DDRDATA7CH0_CR_RCOMPDATA1_PanicDrvDn_OFF                     (16)
+  #define DDRDATA7CH0_CR_RCOMPDATA1_PanicDrvDn_WID                     ( 6)
+  #define DDRDATA7CH0_CR_RCOMPDATA1_PanicDrvDn_MSK                     (0x003F0000)
+  #define DDRDATA7CH0_CR_RCOMPDATA1_PanicDrvDn_MAX                     (0x0000003F)
+  #define DDRDATA7CH0_CR_RCOMPDATA1_PanicDrvUp_OFF                     (22)
+  #define DDRDATA7CH0_CR_RCOMPDATA1_PanicDrvUp_WID                     ( 6)
+  #define DDRDATA7CH0_CR_RCOMPDATA1_PanicDrvUp_MSK                     (0x0FC00000)
+  #define DDRDATA7CH0_CR_RCOMPDATA1_PanicDrvUp_MAX                     (0x0000003F)
+  #define DDRDATA7CH0_CR_RCOMPDATA1_LevelShifterComp_OFF               (28)
+  #define DDRDATA7CH0_CR_RCOMPDATA1_LevelShifterComp_WID               ( 3)
+  #define DDRDATA7CH0_CR_RCOMPDATA1_LevelShifterComp_MSK               (0x70000000)
+  #define DDRDATA7CH0_CR_RCOMPDATA1_LevelShifterComp_MAX               (0x00000007)
+  #define DDRDATA7CH0_CR_RCOMPDATA1_Spare2_OFF                         (31)
+  #define DDRDATA7CH0_CR_RCOMPDATA1_Spare2_WID                         ( 1)
+  #define DDRDATA7CH0_CR_RCOMPDATA1_Spare2_MSK                         (0x80000000)
+  #define DDRDATA7CH0_CR_RCOMPDATA1_Spare2_MAX                         (0x00000001)
+
+#define DDRDATA7CH0_CR_TXXTALK_REG                                   (0x00000E48)
+  #define DDRDATA7CH0_CR_TXXTALK_Lane0_OFF                             ( 0)
+  #define DDRDATA7CH0_CR_TXXTALK_Lane0_WID                             ( 4)
+  #define DDRDATA7CH0_CR_TXXTALK_Lane0_MSK                             (0x0000000F)
+  #define DDRDATA7CH0_CR_TXXTALK_Lane0_MAX                             (0x0000000F)
+  #define DDRDATA7CH0_CR_TXXTALK_Lane1_OFF                             ( 4)
+  #define DDRDATA7CH0_CR_TXXTALK_Lane1_WID                             ( 4)
+  #define DDRDATA7CH0_CR_TXXTALK_Lane1_MSK                             (0x000000F0)
+  #define DDRDATA7CH0_CR_TXXTALK_Lane1_MAX                             (0x0000000F)
+  #define DDRDATA7CH0_CR_TXXTALK_Lane2_OFF                             ( 8)
+  #define DDRDATA7CH0_CR_TXXTALK_Lane2_WID                             ( 4)
+  #define DDRDATA7CH0_CR_TXXTALK_Lane2_MSK                             (0x00000F00)
+  #define DDRDATA7CH0_CR_TXXTALK_Lane2_MAX                             (0x0000000F)
+  #define DDRDATA7CH0_CR_TXXTALK_Lane3_OFF                             (12)
+  #define DDRDATA7CH0_CR_TXXTALK_Lane3_WID                             ( 4)
+  #define DDRDATA7CH0_CR_TXXTALK_Lane3_MSK                             (0x0000F000)
+  #define DDRDATA7CH0_CR_TXXTALK_Lane3_MAX                             (0x0000000F)
+  #define DDRDATA7CH0_CR_TXXTALK_Lane4_OFF                             (16)
+  #define DDRDATA7CH0_CR_TXXTALK_Lane4_WID                             ( 4)
+  #define DDRDATA7CH0_CR_TXXTALK_Lane4_MSK                             (0x000F0000)
+  #define DDRDATA7CH0_CR_TXXTALK_Lane4_MAX                             (0x0000000F)
+  #define DDRDATA7CH0_CR_TXXTALK_Lane5_OFF                             (20)
+  #define DDRDATA7CH0_CR_TXXTALK_Lane5_WID                             ( 4)
+  #define DDRDATA7CH0_CR_TXXTALK_Lane5_MSK                             (0x00F00000)
+  #define DDRDATA7CH0_CR_TXXTALK_Lane5_MAX                             (0x0000000F)
+  #define DDRDATA7CH0_CR_TXXTALK_Lane6_OFF                             (24)
+  #define DDRDATA7CH0_CR_TXXTALK_Lane6_WID                             ( 4)
+  #define DDRDATA7CH0_CR_TXXTALK_Lane6_MSK                             (0x0F000000)
+  #define DDRDATA7CH0_CR_TXXTALK_Lane6_MAX                             (0x0000000F)
+  #define DDRDATA7CH0_CR_TXXTALK_Lane7_OFF                             (28)
+  #define DDRDATA7CH0_CR_TXXTALK_Lane7_WID                             ( 4)
+  #define DDRDATA7CH0_CR_TXXTALK_Lane7_MSK                             (0xF0000000)
+  #define DDRDATA7CH0_CR_TXXTALK_Lane7_MAX                             (0x0000000F)
+
+#define DDRDATA7CH0_CR_RXOFFSETVDQ_REG                               (0x00000E4C)
+  #define DDRDATA7CH0_CR_RXOFFSETVDQ_Lane0_OFF                         ( 0)
+  #define DDRDATA7CH0_CR_RXOFFSETVDQ_Lane0_WID                         ( 4)
+  #define DDRDATA7CH0_CR_RXOFFSETVDQ_Lane0_MSK                         (0x0000000F)
+  #define DDRDATA7CH0_CR_RXOFFSETVDQ_Lane0_MAX                         (0x0000000F)
+  #define DDRDATA7CH0_CR_RXOFFSETVDQ_Lane1_OFF                         ( 4)
+  #define DDRDATA7CH0_CR_RXOFFSETVDQ_Lane1_WID                         ( 4)
+  #define DDRDATA7CH0_CR_RXOFFSETVDQ_Lane1_MSK                         (0x000000F0)
+  #define DDRDATA7CH0_CR_RXOFFSETVDQ_Lane1_MAX                         (0x0000000F)
+  #define DDRDATA7CH0_CR_RXOFFSETVDQ_Lane2_OFF                         ( 8)
+  #define DDRDATA7CH0_CR_RXOFFSETVDQ_Lane2_WID                         ( 4)
+  #define DDRDATA7CH0_CR_RXOFFSETVDQ_Lane2_MSK                         (0x00000F00)
+  #define DDRDATA7CH0_CR_RXOFFSETVDQ_Lane2_MAX                         (0x0000000F)
+  #define DDRDATA7CH0_CR_RXOFFSETVDQ_Lane3_OFF                         (12)
+  #define DDRDATA7CH0_CR_RXOFFSETVDQ_Lane3_WID                         ( 4)
+  #define DDRDATA7CH0_CR_RXOFFSETVDQ_Lane3_MSK                         (0x0000F000)
+  #define DDRDATA7CH0_CR_RXOFFSETVDQ_Lane3_MAX                         (0x0000000F)
+  #define DDRDATA7CH0_CR_RXOFFSETVDQ_Lane4_OFF                         (16)
+  #define DDRDATA7CH0_CR_RXOFFSETVDQ_Lane4_WID                         ( 4)
+  #define DDRDATA7CH0_CR_RXOFFSETVDQ_Lane4_MSK                         (0x000F0000)
+  #define DDRDATA7CH0_CR_RXOFFSETVDQ_Lane4_MAX                         (0x0000000F)
+  #define DDRDATA7CH0_CR_RXOFFSETVDQ_Lane5_OFF                         (20)
+  #define DDRDATA7CH0_CR_RXOFFSETVDQ_Lane5_WID                         ( 4)
+  #define DDRDATA7CH0_CR_RXOFFSETVDQ_Lane5_MSK                         (0x00F00000)
+  #define DDRDATA7CH0_CR_RXOFFSETVDQ_Lane5_MAX                         (0x0000000F)
+  #define DDRDATA7CH0_CR_RXOFFSETVDQ_Lane6_OFF                         (24)
+  #define DDRDATA7CH0_CR_RXOFFSETVDQ_Lane6_WID                         ( 4)
+  #define DDRDATA7CH0_CR_RXOFFSETVDQ_Lane6_MSK                         (0x0F000000)
+  #define DDRDATA7CH0_CR_RXOFFSETVDQ_Lane6_MAX                         (0x0000000F)
+  #define DDRDATA7CH0_CR_RXOFFSETVDQ_Lane7_OFF                         (28)
+  #define DDRDATA7CH0_CR_RXOFFSETVDQ_Lane7_WID                         ( 4)
+  #define DDRDATA7CH0_CR_RXOFFSETVDQ_Lane7_MSK                         (0xF0000000)
+  #define DDRDATA7CH0_CR_RXOFFSETVDQ_Lane7_MAX                         (0x0000000F)
+
+#define DDRDATA7CH0_CR_DDRDATARESERVED_REG                           (0x00000E50)
+  #define DDRDATA7CH0_CR_DDRDATARESERVED_Spare_OFF                     ( 0)
+  #define DDRDATA7CH0_CR_DDRDATARESERVED_Spare_WID                     (32)
+  #define DDRDATA7CH0_CR_DDRDATARESERVED_Spare_MSK                     (0xFFFFFFFF)
+  #define DDRDATA7CH0_CR_DDRDATARESERVED_Spare_MAX                     (0xFFFFFFFF)
+
+#define DDRDATA7CH0_CR_DATATRAINFEEDBACK_REG                         (0x00000E54)
+  #define DDRDATA7CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_OFF       ( 0)
+  #define DDRDATA7CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_WID       ( 9)
+  #define DDRDATA7CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_MSK       (0x000001FF)
+  #define DDRDATA7CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_MAX       (0x000001FF)
+  #define DDRDATA7CH0_CR_DATATRAINFEEDBACK_Spare_OFF                   ( 9)
+  #define DDRDATA7CH0_CR_DATATRAINFEEDBACK_Spare_WID                   (23)
+  #define DDRDATA7CH0_CR_DATATRAINFEEDBACK_Spare_MSK                   (0xFFFFFE00)
+  #define DDRDATA7CH0_CR_DATATRAINFEEDBACK_Spare_MAX                   (0x007FFFFF)
+
+#define DDRDATA7CH0_CR_DLLPITESTANDADC_REG                           (0x00000E58)
+  #define DDRDATA7CH0_CR_DLLPITESTANDADC_RunTest_OFF                   ( 0)
+  #define DDRDATA7CH0_CR_DLLPITESTANDADC_RunTest_WID                   ( 1)
+  #define DDRDATA7CH0_CR_DLLPITESTANDADC_RunTest_MSK                   (0x00000001)
+  #define DDRDATA7CH0_CR_DLLPITESTANDADC_RunTest_MAX                   (0x00000001)
+  #define DDRDATA7CH0_CR_DLLPITESTANDADC_RunTest_DEF                   (0x00000000)
+  #define DDRDATA7CH0_CR_DLLPITESTANDADC_Load_OFF                      ( 1)
+  #define DDRDATA7CH0_CR_DLLPITESTANDADC_Load_WID                      ( 1)
+  #define DDRDATA7CH0_CR_DLLPITESTANDADC_Load_MSK                      (0x00000002)
+  #define DDRDATA7CH0_CR_DLLPITESTANDADC_Load_MAX                      (0x00000001)
+  #define DDRDATA7CH0_CR_DLLPITESTANDADC_Load_DEF                      (0x00000000)
+  #define DDRDATA7CH0_CR_DLLPITESTANDADC_ModeHVM_OFF                   ( 2)
+  #define DDRDATA7CH0_CR_DLLPITESTANDADC_ModeHVM_WID                   ( 1)
+  #define DDRDATA7CH0_CR_DLLPITESTANDADC_ModeHVM_MSK                   (0x00000004)
+  #define DDRDATA7CH0_CR_DLLPITESTANDADC_ModeHVM_MAX                   (0x00000001)
+  #define DDRDATA7CH0_CR_DLLPITESTANDADC_ModeHVM_DEF                   (0x00000000)
+  #define DDRDATA7CH0_CR_DLLPITESTANDADC_ModeDV_OFF                    ( 3)
+  #define DDRDATA7CH0_CR_DLLPITESTANDADC_ModeDV_WID                    ( 1)
+  #define DDRDATA7CH0_CR_DLLPITESTANDADC_ModeDV_MSK                    (0x00000008)
+  #define DDRDATA7CH0_CR_DLLPITESTANDADC_ModeDV_MAX                    (0x00000001)
+  #define DDRDATA7CH0_CR_DLLPITESTANDADC_ModeDV_DEF                    (0x00000000)
+  #define DDRDATA7CH0_CR_DLLPITESTANDADC_ModeADC_OFF                   ( 4)
+  #define DDRDATA7CH0_CR_DLLPITESTANDADC_ModeADC_WID                   ( 1)
+  #define DDRDATA7CH0_CR_DLLPITESTANDADC_ModeADC_MSK                   (0x00000010)
+  #define DDRDATA7CH0_CR_DLLPITESTANDADC_ModeADC_MAX                   (0x00000001)
+  #define DDRDATA7CH0_CR_DLLPITESTANDADC_ModeADC_DEF                   (0x00000000)
+  #define DDRDATA7CH0_CR_DLLPITESTANDADC_LoadCount_OFF                 ( 5)
+  #define DDRDATA7CH0_CR_DLLPITESTANDADC_LoadCount_WID                 (10)
+  #define DDRDATA7CH0_CR_DLLPITESTANDADC_LoadCount_MSK                 (0x00007FE0)
+  #define DDRDATA7CH0_CR_DLLPITESTANDADC_LoadCount_MAX                 (0x000003FF)
+  #define DDRDATA7CH0_CR_DLLPITESTANDADC_CountStatus_OFF               (15)
+  #define DDRDATA7CH0_CR_DLLPITESTANDADC_CountStatus_WID               (10)
+  #define DDRDATA7CH0_CR_DLLPITESTANDADC_CountStatus_MSK               (0x01FF8000)
+  #define DDRDATA7CH0_CR_DLLPITESTANDADC_CountStatus_MAX               (0x000003FF)
+  #define DDRDATA7CH0_CR_DLLPITESTANDADC_CountStatus_DEF               (0x00000000)
+  #define DDRDATA7CH0_CR_DLLPITESTANDADC_Spare_OFF                     (25)
+  #define DDRDATA7CH0_CR_DLLPITESTANDADC_Spare_WID                     ( 7)
+  #define DDRDATA7CH0_CR_DLLPITESTANDADC_Spare_MSK                     (0xFE000000)
+  #define DDRDATA7CH0_CR_DLLPITESTANDADC_Spare_MAX                     (0x0000007F)
+
+#define DDRDATA7CH0_CR_DDRCRDATAOFFSETCOMP_REG                       (0x00000E5C)
+  #define DDRDATA7CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_OFF     ( 0)
+  #define DDRDATA7CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_WID     ( 6)
+  #define DDRDATA7CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MSK     (0x0000003F)
+  #define DDRDATA7CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MAX     (0x0000003F)
+  #define DDRDATA7CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_DEF     (0x00000000)
+  #define DDRDATA7CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_OFF   ( 6)
+  #define DDRDATA7CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_WID   ( 6)
+  #define DDRDATA7CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MSK   (0x00000FC0)
+  #define DDRDATA7CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MAX   (0x0000003F)
+  #define DDRDATA7CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_DEF   (0x00000000)
+  #define DDRDATA7CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_OFF     (12)
+  #define DDRDATA7CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_WID     ( 5)
+  #define DDRDATA7CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MSK     (0x0001F000)
+  #define DDRDATA7CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MAX     (0x0000001F)
+  #define DDRDATA7CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_DEF     (0x00000000)
+  #define DDRDATA7CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_OFF   (17)
+  #define DDRDATA7CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_WID   ( 5)
+  #define DDRDATA7CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MSK   (0x003E0000)
+  #define DDRDATA7CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MAX   (0x0000001F)
+  #define DDRDATA7CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_DEF   (0x00000000)
+  #define DDRDATA7CH0_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_OFF       (22)
+  #define DDRDATA7CH0_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_WID       ( 5)
+  #define DDRDATA7CH0_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_MSK       (0x07C00000)
+  #define DDRDATA7CH0_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_MAX       (0x0000001F)
+  #define DDRDATA7CH0_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_DEF       (0x00000000)
+  #define DDRDATA7CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_OFF  (27)
+  #define DDRDATA7CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_WID  ( 5)
+  #define DDRDATA7CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MSK  (0xF8000000)
+  #define DDRDATA7CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MAX  (0x0000001F)
+  #define DDRDATA7CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_DEF  (0x00000000)
+
+#define DDRDATA7CH0_CR_DDRCRDATACONTROL1_REG                         (0x00000E60)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_RefPi_OFF                   ( 0)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_RefPi_WID                   ( 4)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_RefPi_MSK                   (0x0000000F)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_RefPi_MAX                   (0x0000000F)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_RefPi_DEF                   (0x00000000)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_DllMask_OFF                 ( 4)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_DllMask_WID                 ( 2)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_DllMask_MSK                 (0x00000030)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_DllMask_MAX                 (0x00000003)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_DllMask_DEF                 (0x00000000)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_DllWeakLock_OFF             ( 6)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_DllWeakLock_WID             ( 1)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_DllWeakLock_MSK             (0x00000040)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_DllWeakLock_MAX             (0x00000001)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_DllWeakLock_DEF             (0x00000000)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_OFF      ( 7)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_WID      ( 3)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MSK      (0x00000380)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MAX      (0x00000007)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_DEF      (0x00000000)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_OFF               (10)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_WID               ( 3)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_MSK               (0x00001C00)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_MAX               (0x00000007)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_DEF               (0x00000000)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_OdtDelay_OFF                (13)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_OdtDelay_WID                ( 4)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_OdtDelay_MSK                (0x0001E000)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_OdtDelay_MAX                (0x0000000F)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_OdtDelay_DEF                (0x00000000)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_OdtDuration_OFF             (17)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_OdtDuration_WID             ( 3)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_OdtDuration_MSK             (0x000E0000)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_OdtDuration_MAX             (0x00000007)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_OdtDuration_DEF             (0x00000000)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_OFF           (20)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_WID           ( 4)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_MSK           (0x00F00000)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_MAX           (0x0000000F)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_DEF           (0x00000000)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_OFF        (24)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_WID        ( 3)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_MSK        (0x07000000)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_MAX        (0x00000007)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_DEF        (0x00000000)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_BurstEndODTDelay_OFF        (27)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_BurstEndODTDelay_WID        ( 3)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_BurstEndODTDelay_MSK        (0x38000000)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_BurstEndODTDelay_MAX        (0x00000007)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_BurstEndODTDelay_DEF        (0x00000000)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_OFF          (30)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_WID          ( 1)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_MSK          (0x40000000)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_MAX          (0x00000001)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_DEF          (0x00000000)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_Rsvd1_OFF                   (31)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_Rsvd1_WID                   ( 1)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_Rsvd1_MSK                   (0x80000000)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_Rsvd1_MAX                   (0x00000001)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_Rsvd1_DEF                   (0x00000000)
+
+#define DDRDATA7CH0_CR_DDRCRDATACONTROL2_REG                         (0x00000E64)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_OFF            ( 0)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_WID            ( 5)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_MSK            (0x0000001F)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_MAX            (0x0000001F)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_DEF            (0x00000000)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_OFF             ( 5)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_WID             ( 1)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_MSK             (0x00000020)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_MAX             (0x00000001)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_DEF             (0x00000000)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_ForceRxOn_OFF               ( 6)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_ForceRxOn_WID               ( 1)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_ForceRxOn_MSK               (0x00000040)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_ForceRxOn_MAX               (0x00000001)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_ForceRxOn_DEF               (0x00000000)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_LeakerComp_OFF              ( 7)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_LeakerComp_WID              ( 2)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_LeakerComp_MSK              (0x00000180)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_LeakerComp_MAX              (0x00000003)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_LeakerComp_DEF              (0x00000000)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_OFF          ( 9)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_WID          ( 4)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_MSK          (0x00001E00)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_MAX          (0x0000000F)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_DEF          (0x00000008)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_OFF             (13)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_WID             ( 5)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_MSK             (0x0003E000)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_MAX             (0x0000001F)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_DEF             (0x00000011)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_OFF             (18)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_WID             ( 1)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_MSK             (0x00040000)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_MAX             (0x00000001)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_DEF             (0x00000000)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_Spare_OFF                   (19)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_Spare_WID                   (13)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_Spare_MSK                   (0xFFF80000)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_Spare_MAX                   (0x00001FFF)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_Spare_DEF                   (0x00000000)
+
+#define DDRDATA7CH0_CR_DDRCRVSSHIORVREFCONTROL_REG                   (0x00000E6C)
+  #define DDRDATA7CH0_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_OFF    ( 0)
+  #define DDRDATA7CH0_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_WID    (24)
+  #define DDRDATA7CH0_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_MSK    (0x00FFFFFF)
+  #define DDRDATA7CH0_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_MAX    (0x00FFFFFF)
+  #define DDRDATA7CH0_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_DEF    (0x00000000)
+  #define DDRDATA7CH0_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_OFF        (24)
+  #define DDRDATA7CH0_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_WID        ( 8)
+  #define DDRDATA7CH0_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_MSK        (0xFF000000)
+  #define DDRDATA7CH0_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_MAX        (0x000000FF)
+  #define DDRDATA7CH0_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_DEF        (0x00000000)
+
+#define DDRDATA7CH0_CR_DDRCRDATAOFFSETTRAIN_REG                      (0x00000E70)
+  #define DDRDATA7CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_OFF          ( 0)
+  #define DDRDATA7CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_WID          ( 6)
+  #define DDRDATA7CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MSK          (0x0000003F)
+  #define DDRDATA7CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MAX          (0x0000003F)
+  #define DDRDATA7CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_DEF          (0x00000000)
+  #define DDRDATA7CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_OFF          ( 6)
+  #define DDRDATA7CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_WID          ( 6)
+  #define DDRDATA7CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MSK          (0x00000FC0)
+  #define DDRDATA7CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MAX          (0x0000003F)
+  #define DDRDATA7CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_DEF          (0x00000000)
+  #define DDRDATA7CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_OFF           (12)
+  #define DDRDATA7CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_WID           ( 6)
+  #define DDRDATA7CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MSK           (0x0003F000)
+  #define DDRDATA7CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MAX           (0x0000003F)
+  #define DDRDATA7CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_DEF           (0x00000000)
+  #define DDRDATA7CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_OFF          (18)
+  #define DDRDATA7CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_WID          ( 6)
+  #define DDRDATA7CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MSK          (0x00FC0000)
+  #define DDRDATA7CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MAX          (0x0000003F)
+  #define DDRDATA7CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_DEF          (0x00000000)
+  #define DDRDATA7CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_OFF           (24)
+  #define DDRDATA7CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_WID           ( 7)
+  #define DDRDATA7CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MSK           (0x7F000000)
+  #define DDRDATA7CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MAX           (0x0000007F)
+  #define DDRDATA7CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_DEF           (0x00000000)
+  #define DDRDATA7CH0_CR_DDRCRDATAOFFSETTRAIN_Spare_OFF                (31)
+  #define DDRDATA7CH0_CR_DDRCRDATAOFFSETTRAIN_Spare_WID                ( 1)
+  #define DDRDATA7CH0_CR_DDRCRDATAOFFSETTRAIN_Spare_MSK                (0x80000000)
+  #define DDRDATA7CH0_CR_DDRCRDATAOFFSETTRAIN_Spare_MAX                (0x00000001)
+  #define DDRDATA7CH0_CR_DDRCRDATAOFFSETTRAIN_Spare_DEF                (0x00000000)
+
+#define DDRDATA7CH0_CR_DDRCRDATACONTROL0_REG                         (0x00000E74)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_OFF          ( 0)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_WID          ( 1)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_MSK          (0x00000001)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_MAX          (0x00000001)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_DEF          (0x00000000)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_OFF          ( 1)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_WID          ( 1)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_MSK          (0x00000002)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_MAX          (0x00000001)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_DEF          (0x00000000)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_OFF          ( 2)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_WID          ( 1)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_MSK          (0x00000004)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_MAX          (0x00000001)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_DEF          (0x00000000)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_OFF    ( 3)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_WID    ( 1)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MSK    (0x00000008)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MAX    (0x00000001)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_DEF    (0x00000000)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_TxOn_OFF                    ( 4)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_TxOn_WID                    ( 1)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_TxOn_MSK                    (0x00000010)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_TxOn_MAX                    (0x00000001)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_TxOn_DEF                    (0x00000000)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RfOn_OFF                    ( 5)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RfOn_WID                    ( 1)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RfOn_MSK                    (0x00000020)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RfOn_MAX                    (0x00000001)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RfOn_DEF                    (0x00000000)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RxPiOn_OFF                  ( 6)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RxPiOn_WID                  ( 1)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RxPiOn_MSK                  (0x00000040)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RxPiOn_MAX                  (0x00000001)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RxPiOn_DEF                  (0x00000000)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_TxPiOn_OFF                  ( 7)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_TxPiOn_WID                  ( 1)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_TxPiOn_MSK                  (0x00000080)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_TxPiOn_MAX                  (0x00000001)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_TxPiOn_DEF                  (0x00000000)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_OFF        ( 8)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_WID        ( 1)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_MSK        (0x00000100)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_MAX        (0x00000001)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_DEF        (0x00000000)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_OFF        ( 9)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_WID        ( 1)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MSK        (0x00000200)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MAX        (0x00000001)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_DEF        (0x00000000)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_TxDisable_OFF               (10)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_TxDisable_WID               ( 1)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_TxDisable_MSK               (0x00000400)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_TxDisable_MAX               (0x00000001)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_TxDisable_DEF               (0x00000000)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RxDisable_OFF               (11)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RxDisable_WID               ( 1)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RxDisable_MSK               (0x00000800)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RxDisable_MAX               (0x00000001)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RxDisable_DEF               (0x00000000)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_TxLong_OFF                  (12)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_TxLong_WID                  ( 1)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_TxLong_MSK                  (0x00001000)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_TxLong_MAX                  (0x00000001)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_TxLong_DEF                  (0x00000000)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_OFF               (13)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_WID               ( 2)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_MSK               (0x00006000)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_MAX               (0x00000003)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_DEF               (0x00000000)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RxReadPointer_OFF           (15)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RxReadPointer_WID           ( 3)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RxReadPointer_MSK           (0x00038000)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RxReadPointer_MAX           (0x00000007)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RxReadPointer_DEF           (0x00000000)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_DriverSegmentEnable_OFF     (18)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_DriverSegmentEnable_WID     ( 1)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_DriverSegmentEnable_MSK     (0x00040000)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_DriverSegmentEnable_MAX     (0x00000001)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_DriverSegmentEnable_DEF     (0x00000000)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_DataVccddqHi_OFF            (19)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_DataVccddqHi_WID            ( 1)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_DataVccddqHi_MSK            (0x00080000)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_DataVccddqHi_MAX            (0x00000001)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_DataVccddqHi_DEF            (0x00000000)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_ReadRFRd_OFF                (20)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_ReadRFRd_WID                ( 1)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_ReadRFRd_MSK                (0x00100000)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_ReadRFRd_MAX                (0x00000001)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_ReadRFRd_DEF                (0x00000000)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_ReadRFWr_OFF                (21)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_ReadRFWr_WID                ( 1)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_ReadRFWr_MSK                (0x00200000)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_ReadRFWr_MAX                (0x00000001)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_ReadRFWr_DEF                (0x00000000)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_ReadRFRank_OFF              (22)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_ReadRFRank_WID              ( 2)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_ReadRFRank_MSK              (0x00C00000)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_ReadRFRank_MAX              (0x00000003)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_ReadRFRank_DEF              (0x00000000)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_OFF              (24)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_WID              ( 1)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_MSK              (0x01000000)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_MAX              (0x00000001)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_DEF              (0x00000000)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_OdtSampOff_OFF              (25)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_OdtSampOff_WID              ( 1)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_OdtSampOff_MSK              (0x02000000)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_OdtSampOff_MAX              (0x00000001)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_OdtSampOff_DEF              (0x00000000)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_OFF        (26)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_WID        ( 1)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_MSK        (0x04000000)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_MAX        (0x00000001)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_DEF        (0x00000000)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_OFF         (27)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_WID         ( 1)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MSK         (0x08000000)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MAX         (0x00000001)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_DEF         (0x00000000)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_OFF              (28)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_WID              ( 1)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_MSK              (0x10000000)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_MAX              (0x00000001)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_DEF              (0x00000000)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_EnReadPreamble_OFF          (29)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_EnReadPreamble_WID          ( 1)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_EnReadPreamble_MSK          (0x20000000)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_EnReadPreamble_MAX          (0x00000001)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_EnReadPreamble_DEF          (0x00000000)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_OFF         (30)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_WID         ( 1)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MSK         (0x40000000)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MAX         (0x00000001)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_DEF         (0x00000000)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_OFF            (31)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_WID            ( 1)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_MSK            (0x80000000)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_MAX            (0x00000001)
+  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_DEF            (0x00000000)
+
+#define DDRDATA7CH0_CR_DDRCRVREFADJUST1_REG                          (0x00000E78)
+  #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_CAVrefCtl_OFF                ( 0)
+  #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_CAVrefCtl_WID                ( 7)
+  #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_CAVrefCtl_MSK                (0x0000007F)
+  #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_CAVrefCtl_MAX                (0x0000007F)
+  #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_CAVrefCtl_DEF                (0x00000000)
+  #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_Ch1VrefCtl_OFF               ( 7)
+  #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_Ch1VrefCtl_WID               ( 7)
+  #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_Ch1VrefCtl_MSK               (0x00003F80)
+  #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_Ch1VrefCtl_MAX               (0x0000007F)
+  #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_Ch1VrefCtl_DEF               (0x00000000)
+  #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_Ch0VrefCtl_OFF               (14)
+  #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_Ch0VrefCtl_WID               ( 7)
+  #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_Ch0VrefCtl_MSK               (0x001FC000)
+  #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_Ch0VrefCtl_MAX               (0x0000007F)
+  #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_Ch0VrefCtl_DEF               (0x00000000)
+  #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCA_OFF             (21)
+  #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCA_WID             ( 1)
+  #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCA_MSK             (0x00200000)
+  #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCA_MAX             (0x00000001)
+  #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCA_DEF             (0x00000000)
+  #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_OFF            (22)
+  #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_WID            ( 1)
+  #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_MSK            (0x00400000)
+  #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_MAX            (0x00000001)
+  #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_DEF            (0x00000000)
+  #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_OFF            (23)
+  #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_WID            ( 1)
+  #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_MSK            (0x00800000)
+  #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_MAX            (0x00000001)
+  #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_DEF            (0x00000000)
+  #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_HiZTimerCtrl_OFF             (24)
+  #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_HiZTimerCtrl_WID             ( 2)
+  #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_HiZTimerCtrl_MSK             (0x03000000)
+  #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_HiZTimerCtrl_MAX             (0x00000003)
+  #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_HiZTimerCtrl_DEF             (0x00000000)
+  #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_OFF            (26)
+  #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_WID            ( 1)
+  #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_MSK            (0x04000000)
+  #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_MAX            (0x00000001)
+  #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_DEF            (0x00000000)
+  #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_Rsvd_OFF                     (27)
+  #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_Rsvd_WID                     ( 2)
+  #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_Rsvd_MSK                     (0x18000000)
+  #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_Rsvd_MAX                     (0x00000003)
+  #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_Rsvd_DEF                     (0x00000000)
+  #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_caSlowBW_OFF                 (29)
+  #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_caSlowBW_WID                 ( 1)
+  #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_caSlowBW_MSK                 (0x20000000)
+  #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_caSlowBW_MAX                 (0x00000001)
+  #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_caSlowBW_DEF                 (0x00000000)
+  #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_ch0SlowBW_OFF                (30)
+  #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_ch0SlowBW_WID                ( 1)
+  #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_ch0SlowBW_MSK                (0x40000000)
+  #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_ch0SlowBW_MAX                (0x00000001)
+  #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_ch0SlowBW_DEF                (0x00000000)
+  #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_ch1SlowBW_OFF                (31)
+  #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_ch1SlowBW_WID                ( 1)
+  #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_ch1SlowBW_MSK                (0x80000000)
+  #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_ch1SlowBW_MAX                (0x00000001)
+  #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_ch1SlowBW_DEF                (0x00000000)
+
+#define DDRDATA7CH1_CR_RXTRAINRANK0_REG                              (0x00000F00)
+  #define DDRDATA7CH1_CR_RXTRAINRANK0_RxRcvEnPi_OFF                    ( 0)
+  #define DDRDATA7CH1_CR_RXTRAINRANK0_RxRcvEnPi_WID                    ( 9)
+  #define DDRDATA7CH1_CR_RXTRAINRANK0_RxRcvEnPi_MSK                    (0x000001FF)
+  #define DDRDATA7CH1_CR_RXTRAINRANK0_RxRcvEnPi_MAX                    (0x000001FF)
+  #define DDRDATA7CH1_CR_RXTRAINRANK0_RxDqsPPi_OFF                     ( 9)
+  #define DDRDATA7CH1_CR_RXTRAINRANK0_RxDqsPPi_WID                     ( 6)
+  #define DDRDATA7CH1_CR_RXTRAINRANK0_RxDqsPPi_MSK                     (0x00007E00)
+  #define DDRDATA7CH1_CR_RXTRAINRANK0_RxDqsPPi_MAX                     (0x0000003F)
+  #define DDRDATA7CH1_CR_RXTRAINRANK0_RxEq_OFF                         (15)
+  #define DDRDATA7CH1_CR_RXTRAINRANK0_RxEq_WID                         ( 5)
+  #define DDRDATA7CH1_CR_RXTRAINRANK0_RxEq_MSK                         (0x000F8000)
+  #define DDRDATA7CH1_CR_RXTRAINRANK0_RxEq_MAX                         (0x0000001F)
+  #define DDRDATA7CH1_CR_RXTRAINRANK0_RxDqsNPi_OFF                     (20)
+  #define DDRDATA7CH1_CR_RXTRAINRANK0_RxDqsNPi_WID                     ( 6)
+  #define DDRDATA7CH1_CR_RXTRAINRANK0_RxDqsNPi_MSK                     (0x03F00000)
+  #define DDRDATA7CH1_CR_RXTRAINRANK0_RxDqsNPi_MAX                     (0x0000003F)
+  #define DDRDATA7CH1_CR_RXTRAINRANK0_RxVref_OFF                       (26)
+  #define DDRDATA7CH1_CR_RXTRAINRANK0_RxVref_WID                       ( 6)
+  #define DDRDATA7CH1_CR_RXTRAINRANK0_RxVref_MSK                       (0xFC000000)
+  #define DDRDATA7CH1_CR_RXTRAINRANK0_RxVref_MAX                       (0x0000003F)
+
+#define DDRDATA7CH1_CR_RXTRAINRANK1_REG                              (0x00000F04)
+  #define DDRDATA7CH1_CR_RXTRAINRANK1_RxRcvEnPi_OFF                    ( 0)
+  #define DDRDATA7CH1_CR_RXTRAINRANK1_RxRcvEnPi_WID                    ( 9)
+  #define DDRDATA7CH1_CR_RXTRAINRANK1_RxRcvEnPi_MSK                    (0x000001FF)
+  #define DDRDATA7CH1_CR_RXTRAINRANK1_RxRcvEnPi_MAX                    (0x000001FF)
+  #define DDRDATA7CH1_CR_RXTRAINRANK1_RxDqsPPi_OFF                     ( 9)
+  #define DDRDATA7CH1_CR_RXTRAINRANK1_RxDqsPPi_WID                     ( 6)
+  #define DDRDATA7CH1_CR_RXTRAINRANK1_RxDqsPPi_MSK                     (0x00007E00)
+  #define DDRDATA7CH1_CR_RXTRAINRANK1_RxDqsPPi_MAX                     (0x0000003F)
+  #define DDRDATA7CH1_CR_RXTRAINRANK1_RxEq_OFF                         (15)
+  #define DDRDATA7CH1_CR_RXTRAINRANK1_RxEq_WID                         ( 5)
+  #define DDRDATA7CH1_CR_RXTRAINRANK1_RxEq_MSK                         (0x000F8000)
+  #define DDRDATA7CH1_CR_RXTRAINRANK1_RxEq_MAX                         (0x0000001F)
+  #define DDRDATA7CH1_CR_RXTRAINRANK1_RxDqsNPi_OFF                     (20)
+  #define DDRDATA7CH1_CR_RXTRAINRANK1_RxDqsNPi_WID                     ( 6)
+  #define DDRDATA7CH1_CR_RXTRAINRANK1_RxDqsNPi_MSK                     (0x03F00000)
+  #define DDRDATA7CH1_CR_RXTRAINRANK1_RxDqsNPi_MAX                     (0x0000003F)
+  #define DDRDATA7CH1_CR_RXTRAINRANK1_RxVref_OFF                       (26)
+  #define DDRDATA7CH1_CR_RXTRAINRANK1_RxVref_WID                       ( 6)
+  #define DDRDATA7CH1_CR_RXTRAINRANK1_RxVref_MSK                       (0xFC000000)
+  #define DDRDATA7CH1_CR_RXTRAINRANK1_RxVref_MAX                       (0x0000003F)
+
+#define DDRDATA7CH1_CR_RXTRAINRANK2_REG                              (0x00000F08)
+  #define DDRDATA7CH1_CR_RXTRAINRANK2_RxRcvEnPi_OFF                    ( 0)
+  #define DDRDATA7CH1_CR_RXTRAINRANK2_RxRcvEnPi_WID                    ( 9)
+  #define DDRDATA7CH1_CR_RXTRAINRANK2_RxRcvEnPi_MSK                    (0x000001FF)
+  #define DDRDATA7CH1_CR_RXTRAINRANK2_RxRcvEnPi_MAX                    (0x000001FF)
+  #define DDRDATA7CH1_CR_RXTRAINRANK2_RxDqsPPi_OFF                     ( 9)
+  #define DDRDATA7CH1_CR_RXTRAINRANK2_RxDqsPPi_WID                     ( 6)
+  #define DDRDATA7CH1_CR_RXTRAINRANK2_RxDqsPPi_MSK                     (0x00007E00)
+  #define DDRDATA7CH1_CR_RXTRAINRANK2_RxDqsPPi_MAX                     (0x0000003F)
+  #define DDRDATA7CH1_CR_RXTRAINRANK2_RxEq_OFF                         (15)
+  #define DDRDATA7CH1_CR_RXTRAINRANK2_RxEq_WID                         ( 5)
+  #define DDRDATA7CH1_CR_RXTRAINRANK2_RxEq_MSK                         (0x000F8000)
+  #define DDRDATA7CH1_CR_RXTRAINRANK2_RxEq_MAX                         (0x0000001F)
+  #define DDRDATA7CH1_CR_RXTRAINRANK2_RxDqsNPi_OFF                     (20)
+  #define DDRDATA7CH1_CR_RXTRAINRANK2_RxDqsNPi_WID                     ( 6)
+  #define DDRDATA7CH1_CR_RXTRAINRANK2_RxDqsNPi_MSK                     (0x03F00000)
+  #define DDRDATA7CH1_CR_RXTRAINRANK2_RxDqsNPi_MAX                     (0x0000003F)
+  #define DDRDATA7CH1_CR_RXTRAINRANK2_RxVref_OFF                       (26)
+  #define DDRDATA7CH1_CR_RXTRAINRANK2_RxVref_WID                       ( 6)
+  #define DDRDATA7CH1_CR_RXTRAINRANK2_RxVref_MSK                       (0xFC000000)
+  #define DDRDATA7CH1_CR_RXTRAINRANK2_RxVref_MAX                       (0x0000003F)
+
+#define DDRDATA7CH1_CR_RXTRAINRANK3_REG                              (0x00000F0C)
+  #define DDRDATA7CH1_CR_RXTRAINRANK3_RxRcvEnPi_OFF                    ( 0)
+  #define DDRDATA7CH1_CR_RXTRAINRANK3_RxRcvEnPi_WID                    ( 9)
+  #define DDRDATA7CH1_CR_RXTRAINRANK3_RxRcvEnPi_MSK                    (0x000001FF)
+  #define DDRDATA7CH1_CR_RXTRAINRANK3_RxRcvEnPi_MAX                    (0x000001FF)
+  #define DDRDATA7CH1_CR_RXTRAINRANK3_RxDqsPPi_OFF                     ( 9)
+  #define DDRDATA7CH1_CR_RXTRAINRANK3_RxDqsPPi_WID                     ( 6)
+  #define DDRDATA7CH1_CR_RXTRAINRANK3_RxDqsPPi_MSK                     (0x00007E00)
+  #define DDRDATA7CH1_CR_RXTRAINRANK3_RxDqsPPi_MAX                     (0x0000003F)
+  #define DDRDATA7CH1_CR_RXTRAINRANK3_RxEq_OFF                         (15)
+  #define DDRDATA7CH1_CR_RXTRAINRANK3_RxEq_WID                         ( 5)
+  #define DDRDATA7CH1_CR_RXTRAINRANK3_RxEq_MSK                         (0x000F8000)
+  #define DDRDATA7CH1_CR_RXTRAINRANK3_RxEq_MAX                         (0x0000001F)
+  #define DDRDATA7CH1_CR_RXTRAINRANK3_RxDqsNPi_OFF                     (20)
+  #define DDRDATA7CH1_CR_RXTRAINRANK3_RxDqsNPi_WID                     ( 6)
+  #define DDRDATA7CH1_CR_RXTRAINRANK3_RxDqsNPi_MSK                     (0x03F00000)
+  #define DDRDATA7CH1_CR_RXTRAINRANK3_RxDqsNPi_MAX                     (0x0000003F)
+  #define DDRDATA7CH1_CR_RXTRAINRANK3_RxVref_OFF                       (26)
+  #define DDRDATA7CH1_CR_RXTRAINRANK3_RxVref_WID                       ( 6)
+  #define DDRDATA7CH1_CR_RXTRAINRANK3_RxVref_MSK                       (0xFC000000)
+  #define DDRDATA7CH1_CR_RXTRAINRANK3_RxVref_MAX                       (0x0000003F)
+
+#define DDRDATA7CH1_CR_RXPERBITRANK0_REG                             (0x00000F10)
+  #define DDRDATA7CH1_CR_RXPERBITRANK0_Lane0_OFF                       ( 0)
+  #define DDRDATA7CH1_CR_RXPERBITRANK0_Lane0_WID                       ( 4)
+  #define DDRDATA7CH1_CR_RXPERBITRANK0_Lane0_MSK                       (0x0000000F)
+  #define DDRDATA7CH1_CR_RXPERBITRANK0_Lane0_MAX                       (0x0000000F)
+  #define DDRDATA7CH1_CR_RXPERBITRANK0_Lane1_OFF                       ( 4)
+  #define DDRDATA7CH1_CR_RXPERBITRANK0_Lane1_WID                       ( 4)
+  #define DDRDATA7CH1_CR_RXPERBITRANK0_Lane1_MSK                       (0x000000F0)
+  #define DDRDATA7CH1_CR_RXPERBITRANK0_Lane1_MAX                       (0x0000000F)
+  #define DDRDATA7CH1_CR_RXPERBITRANK0_Lane2_OFF                       ( 8)
+  #define DDRDATA7CH1_CR_RXPERBITRANK0_Lane2_WID                       ( 4)
+  #define DDRDATA7CH1_CR_RXPERBITRANK0_Lane2_MSK                       (0x00000F00)
+  #define DDRDATA7CH1_CR_RXPERBITRANK0_Lane2_MAX                       (0x0000000F)
+  #define DDRDATA7CH1_CR_RXPERBITRANK0_Lane3_OFF                       (12)
+  #define DDRDATA7CH1_CR_RXPERBITRANK0_Lane3_WID                       ( 4)
+  #define DDRDATA7CH1_CR_RXPERBITRANK0_Lane3_MSK                       (0x0000F000)
+  #define DDRDATA7CH1_CR_RXPERBITRANK0_Lane3_MAX                       (0x0000000F)
+  #define DDRDATA7CH1_CR_RXPERBITRANK0_Lane4_OFF                       (16)
+  #define DDRDATA7CH1_CR_RXPERBITRANK0_Lane4_WID                       ( 4)
+  #define DDRDATA7CH1_CR_RXPERBITRANK0_Lane4_MSK                       (0x000F0000)
+  #define DDRDATA7CH1_CR_RXPERBITRANK0_Lane4_MAX                       (0x0000000F)
+  #define DDRDATA7CH1_CR_RXPERBITRANK0_Lane5_OFF                       (20)
+  #define DDRDATA7CH1_CR_RXPERBITRANK0_Lane5_WID                       ( 4)
+  #define DDRDATA7CH1_CR_RXPERBITRANK0_Lane5_MSK                       (0x00F00000)
+  #define DDRDATA7CH1_CR_RXPERBITRANK0_Lane5_MAX                       (0x0000000F)
+  #define DDRDATA7CH1_CR_RXPERBITRANK0_Lane6_OFF                       (24)
+  #define DDRDATA7CH1_CR_RXPERBITRANK0_Lane6_WID                       ( 4)
+  #define DDRDATA7CH1_CR_RXPERBITRANK0_Lane6_MSK                       (0x0F000000)
+  #define DDRDATA7CH1_CR_RXPERBITRANK0_Lane6_MAX                       (0x0000000F)
+  #define DDRDATA7CH1_CR_RXPERBITRANK0_Lane7_OFF                       (28)
+  #define DDRDATA7CH1_CR_RXPERBITRANK0_Lane7_WID                       ( 4)
+  #define DDRDATA7CH1_CR_RXPERBITRANK0_Lane7_MSK                       (0xF0000000)
+  #define DDRDATA7CH1_CR_RXPERBITRANK0_Lane7_MAX                       (0x0000000F)
+
+#define DDRDATA7CH1_CR_RXPERBITRANK1_REG                             (0x00000F14)
+  #define DDRDATA7CH1_CR_RXPERBITRANK1_Lane0_OFF                       ( 0)
+  #define DDRDATA7CH1_CR_RXPERBITRANK1_Lane0_WID                       ( 4)
+  #define DDRDATA7CH1_CR_RXPERBITRANK1_Lane0_MSK                       (0x0000000F)
+  #define DDRDATA7CH1_CR_RXPERBITRANK1_Lane0_MAX                       (0x0000000F)
+  #define DDRDATA7CH1_CR_RXPERBITRANK1_Lane1_OFF                       ( 4)
+  #define DDRDATA7CH1_CR_RXPERBITRANK1_Lane1_WID                       ( 4)
+  #define DDRDATA7CH1_CR_RXPERBITRANK1_Lane1_MSK                       (0x000000F0)
+  #define DDRDATA7CH1_CR_RXPERBITRANK1_Lane1_MAX                       (0x0000000F)
+  #define DDRDATA7CH1_CR_RXPERBITRANK1_Lane2_OFF                       ( 8)
+  #define DDRDATA7CH1_CR_RXPERBITRANK1_Lane2_WID                       ( 4)
+  #define DDRDATA7CH1_CR_RXPERBITRANK1_Lane2_MSK                       (0x00000F00)
+  #define DDRDATA7CH1_CR_RXPERBITRANK1_Lane2_MAX                       (0x0000000F)
+  #define DDRDATA7CH1_CR_RXPERBITRANK1_Lane3_OFF                       (12)
+  #define DDRDATA7CH1_CR_RXPERBITRANK1_Lane3_WID                       ( 4)
+  #define DDRDATA7CH1_CR_RXPERBITRANK1_Lane3_MSK                       (0x0000F000)
+  #define DDRDATA7CH1_CR_RXPERBITRANK1_Lane3_MAX                       (0x0000000F)
+  #define DDRDATA7CH1_CR_RXPERBITRANK1_Lane4_OFF                       (16)
+  #define DDRDATA7CH1_CR_RXPERBITRANK1_Lane4_WID                       ( 4)
+  #define DDRDATA7CH1_CR_RXPERBITRANK1_Lane4_MSK                       (0x000F0000)
+  #define DDRDATA7CH1_CR_RXPERBITRANK1_Lane4_MAX                       (0x0000000F)
+  #define DDRDATA7CH1_CR_RXPERBITRANK1_Lane5_OFF                       (20)
+  #define DDRDATA7CH1_CR_RXPERBITRANK1_Lane5_WID                       ( 4)
+  #define DDRDATA7CH1_CR_RXPERBITRANK1_Lane5_MSK                       (0x00F00000)
+  #define DDRDATA7CH1_CR_RXPERBITRANK1_Lane5_MAX                       (0x0000000F)
+  #define DDRDATA7CH1_CR_RXPERBITRANK1_Lane6_OFF                       (24)
+  #define DDRDATA7CH1_CR_RXPERBITRANK1_Lane6_WID                       ( 4)
+  #define DDRDATA7CH1_CR_RXPERBITRANK1_Lane6_MSK                       (0x0F000000)
+  #define DDRDATA7CH1_CR_RXPERBITRANK1_Lane6_MAX                       (0x0000000F)
+  #define DDRDATA7CH1_CR_RXPERBITRANK1_Lane7_OFF                       (28)
+  #define DDRDATA7CH1_CR_RXPERBITRANK1_Lane7_WID                       ( 4)
+  #define DDRDATA7CH1_CR_RXPERBITRANK1_Lane7_MSK                       (0xF0000000)
+  #define DDRDATA7CH1_CR_RXPERBITRANK1_Lane7_MAX                       (0x0000000F)
+
+#define DDRDATA7CH1_CR_RXPERBITRANK2_REG                             (0x00000F18)
+  #define DDRDATA7CH1_CR_RXPERBITRANK2_Lane0_OFF                       ( 0)
+  #define DDRDATA7CH1_CR_RXPERBITRANK2_Lane0_WID                       ( 4)
+  #define DDRDATA7CH1_CR_RXPERBITRANK2_Lane0_MSK                       (0x0000000F)
+  #define DDRDATA7CH1_CR_RXPERBITRANK2_Lane0_MAX                       (0x0000000F)
+  #define DDRDATA7CH1_CR_RXPERBITRANK2_Lane1_OFF                       ( 4)
+  #define DDRDATA7CH1_CR_RXPERBITRANK2_Lane1_WID                       ( 4)
+  #define DDRDATA7CH1_CR_RXPERBITRANK2_Lane1_MSK                       (0x000000F0)
+  #define DDRDATA7CH1_CR_RXPERBITRANK2_Lane1_MAX                       (0x0000000F)
+  #define DDRDATA7CH1_CR_RXPERBITRANK2_Lane2_OFF                       ( 8)
+  #define DDRDATA7CH1_CR_RXPERBITRANK2_Lane2_WID                       ( 4)
+  #define DDRDATA7CH1_CR_RXPERBITRANK2_Lane2_MSK                       (0x00000F00)
+  #define DDRDATA7CH1_CR_RXPERBITRANK2_Lane2_MAX                       (0x0000000F)
+  #define DDRDATA7CH1_CR_RXPERBITRANK2_Lane3_OFF                       (12)
+  #define DDRDATA7CH1_CR_RXPERBITRANK2_Lane3_WID                       ( 4)
+  #define DDRDATA7CH1_CR_RXPERBITRANK2_Lane3_MSK                       (0x0000F000)
+  #define DDRDATA7CH1_CR_RXPERBITRANK2_Lane3_MAX                       (0x0000000F)
+  #define DDRDATA7CH1_CR_RXPERBITRANK2_Lane4_OFF                       (16)
+  #define DDRDATA7CH1_CR_RXPERBITRANK2_Lane4_WID                       ( 4)
+  #define DDRDATA7CH1_CR_RXPERBITRANK2_Lane4_MSK                       (0x000F0000)
+  #define DDRDATA7CH1_CR_RXPERBITRANK2_Lane4_MAX                       (0x0000000F)
+  #define DDRDATA7CH1_CR_RXPERBITRANK2_Lane5_OFF                       (20)
+  #define DDRDATA7CH1_CR_RXPERBITRANK2_Lane5_WID                       ( 4)
+  #define DDRDATA7CH1_CR_RXPERBITRANK2_Lane5_MSK                       (0x00F00000)
+  #define DDRDATA7CH1_CR_RXPERBITRANK2_Lane5_MAX                       (0x0000000F)
+  #define DDRDATA7CH1_CR_RXPERBITRANK2_Lane6_OFF                       (24)
+  #define DDRDATA7CH1_CR_RXPERBITRANK2_Lane6_WID                       ( 4)
+  #define DDRDATA7CH1_CR_RXPERBITRANK2_Lane6_MSK                       (0x0F000000)
+  #define DDRDATA7CH1_CR_RXPERBITRANK2_Lane6_MAX                       (0x0000000F)
+  #define DDRDATA7CH1_CR_RXPERBITRANK2_Lane7_OFF                       (28)
+  #define DDRDATA7CH1_CR_RXPERBITRANK2_Lane7_WID                       ( 4)
+  #define DDRDATA7CH1_CR_RXPERBITRANK2_Lane7_MSK                       (0xF0000000)
+  #define DDRDATA7CH1_CR_RXPERBITRANK2_Lane7_MAX                       (0x0000000F)
+
+#define DDRDATA7CH1_CR_RXPERBITRANK3_REG                             (0x00000F1C)
+  #define DDRDATA7CH1_CR_RXPERBITRANK3_Lane0_OFF                       ( 0)
+  #define DDRDATA7CH1_CR_RXPERBITRANK3_Lane0_WID                       ( 4)
+  #define DDRDATA7CH1_CR_RXPERBITRANK3_Lane0_MSK                       (0x0000000F)
+  #define DDRDATA7CH1_CR_RXPERBITRANK3_Lane0_MAX                       (0x0000000F)
+  #define DDRDATA7CH1_CR_RXPERBITRANK3_Lane1_OFF                       ( 4)
+  #define DDRDATA7CH1_CR_RXPERBITRANK3_Lane1_WID                       ( 4)
+  #define DDRDATA7CH1_CR_RXPERBITRANK3_Lane1_MSK                       (0x000000F0)
+  #define DDRDATA7CH1_CR_RXPERBITRANK3_Lane1_MAX                       (0x0000000F)
+  #define DDRDATA7CH1_CR_RXPERBITRANK3_Lane2_OFF                       ( 8)
+  #define DDRDATA7CH1_CR_RXPERBITRANK3_Lane2_WID                       ( 4)
+  #define DDRDATA7CH1_CR_RXPERBITRANK3_Lane2_MSK                       (0x00000F00)
+  #define DDRDATA7CH1_CR_RXPERBITRANK3_Lane2_MAX                       (0x0000000F)
+  #define DDRDATA7CH1_CR_RXPERBITRANK3_Lane3_OFF                       (12)
+  #define DDRDATA7CH1_CR_RXPERBITRANK3_Lane3_WID                       ( 4)
+  #define DDRDATA7CH1_CR_RXPERBITRANK3_Lane3_MSK                       (0x0000F000)
+  #define DDRDATA7CH1_CR_RXPERBITRANK3_Lane3_MAX                       (0x0000000F)
+  #define DDRDATA7CH1_CR_RXPERBITRANK3_Lane4_OFF                       (16)
+  #define DDRDATA7CH1_CR_RXPERBITRANK3_Lane4_WID                       ( 4)
+  #define DDRDATA7CH1_CR_RXPERBITRANK3_Lane4_MSK                       (0x000F0000)
+  #define DDRDATA7CH1_CR_RXPERBITRANK3_Lane4_MAX                       (0x0000000F)
+  #define DDRDATA7CH1_CR_RXPERBITRANK3_Lane5_OFF                       (20)
+  #define DDRDATA7CH1_CR_RXPERBITRANK3_Lane5_WID                       ( 4)
+  #define DDRDATA7CH1_CR_RXPERBITRANK3_Lane5_MSK                       (0x00F00000)
+  #define DDRDATA7CH1_CR_RXPERBITRANK3_Lane5_MAX                       (0x0000000F)
+  #define DDRDATA7CH1_CR_RXPERBITRANK3_Lane6_OFF                       (24)
+  #define DDRDATA7CH1_CR_RXPERBITRANK3_Lane6_WID                       ( 4)
+  #define DDRDATA7CH1_CR_RXPERBITRANK3_Lane6_MSK                       (0x0F000000)
+  #define DDRDATA7CH1_CR_RXPERBITRANK3_Lane6_MAX                       (0x0000000F)
+  #define DDRDATA7CH1_CR_RXPERBITRANK3_Lane7_OFF                       (28)
+  #define DDRDATA7CH1_CR_RXPERBITRANK3_Lane7_WID                       ( 4)
+  #define DDRDATA7CH1_CR_RXPERBITRANK3_Lane7_MSK                       (0xF0000000)
+  #define DDRDATA7CH1_CR_RXPERBITRANK3_Lane7_MAX                       (0x0000000F)
+
+#define DDRDATA7CH1_CR_TXTRAINRANK0_REG                              (0x00000F20)
+  #define DDRDATA7CH1_CR_TXTRAINRANK0_TxDqDelay_OFF                    ( 0)
+  #define DDRDATA7CH1_CR_TXTRAINRANK0_TxDqDelay_WID                    ( 9)
+  #define DDRDATA7CH1_CR_TXTRAINRANK0_TxDqDelay_MSK                    (0x000001FF)
+  #define DDRDATA7CH1_CR_TXTRAINRANK0_TxDqDelay_MAX                    (0x000001FF)
+  #define DDRDATA7CH1_CR_TXTRAINRANK0_TxDqsDelay_OFF                   ( 9)
+  #define DDRDATA7CH1_CR_TXTRAINRANK0_TxDqsDelay_WID                   ( 9)
+  #define DDRDATA7CH1_CR_TXTRAINRANK0_TxDqsDelay_MSK                   (0x0003FE00)
+  #define DDRDATA7CH1_CR_TXTRAINRANK0_TxDqsDelay_MAX                   (0x000001FF)
+  #define DDRDATA7CH1_CR_TXTRAINRANK0_Spare0_OFF                       (18)
+  #define DDRDATA7CH1_CR_TXTRAINRANK0_Spare0_WID                       ( 2)
+  #define DDRDATA7CH1_CR_TXTRAINRANK0_Spare0_MSK                       (0x000C0000)
+  #define DDRDATA7CH1_CR_TXTRAINRANK0_Spare0_MAX                       (0x00000003)
+  #define DDRDATA7CH1_CR_TXTRAINRANK0_TxEqualization_OFF               (20)
+  #define DDRDATA7CH1_CR_TXTRAINRANK0_TxEqualization_WID               ( 6)
+  #define DDRDATA7CH1_CR_TXTRAINRANK0_TxEqualization_MSK               (0x03F00000)
+  #define DDRDATA7CH1_CR_TXTRAINRANK0_TxEqualization_MAX               (0x0000003F)
+  #define DDRDATA7CH1_CR_TXTRAINRANK0_Spare1_OFF                       (26)
+  #define DDRDATA7CH1_CR_TXTRAINRANK0_Spare1_WID                       ( 6)
+  #define DDRDATA7CH1_CR_TXTRAINRANK0_Spare1_MSK                       (0xFC000000)
+  #define DDRDATA7CH1_CR_TXTRAINRANK0_Spare1_MAX                       (0x0000003F)
+
+#define DDRDATA7CH1_CR_TXTRAINRANK1_REG                              (0x00000F24)
+  #define DDRDATA7CH1_CR_TXTRAINRANK1_TxDqDelay_OFF                    ( 0)
+  #define DDRDATA7CH1_CR_TXTRAINRANK1_TxDqDelay_WID                    ( 9)
+  #define DDRDATA7CH1_CR_TXTRAINRANK1_TxDqDelay_MSK                    (0x000001FF)
+  #define DDRDATA7CH1_CR_TXTRAINRANK1_TxDqDelay_MAX                    (0x000001FF)
+  #define DDRDATA7CH1_CR_TXTRAINRANK1_TxDqsDelay_OFF                   ( 9)
+  #define DDRDATA7CH1_CR_TXTRAINRANK1_TxDqsDelay_WID                   ( 9)
+  #define DDRDATA7CH1_CR_TXTRAINRANK1_TxDqsDelay_MSK                   (0x0003FE00)
+  #define DDRDATA7CH1_CR_TXTRAINRANK1_TxDqsDelay_MAX                   (0x000001FF)
+  #define DDRDATA7CH1_CR_TXTRAINRANK1_Spare0_OFF                       (18)
+  #define DDRDATA7CH1_CR_TXTRAINRANK1_Spare0_WID                       ( 2)
+  #define DDRDATA7CH1_CR_TXTRAINRANK1_Spare0_MSK                       (0x000C0000)
+  #define DDRDATA7CH1_CR_TXTRAINRANK1_Spare0_MAX                       (0x00000003)
+  #define DDRDATA7CH1_CR_TXTRAINRANK1_TxEqualization_OFF               (20)
+  #define DDRDATA7CH1_CR_TXTRAINRANK1_TxEqualization_WID               ( 6)
+  #define DDRDATA7CH1_CR_TXTRAINRANK1_TxEqualization_MSK               (0x03F00000)
+  #define DDRDATA7CH1_CR_TXTRAINRANK1_TxEqualization_MAX               (0x0000003F)
+  #define DDRDATA7CH1_CR_TXTRAINRANK1_Spare1_OFF                       (26)
+  #define DDRDATA7CH1_CR_TXTRAINRANK1_Spare1_WID                       ( 6)
+  #define DDRDATA7CH1_CR_TXTRAINRANK1_Spare1_MSK                       (0xFC000000)
+  #define DDRDATA7CH1_CR_TXTRAINRANK1_Spare1_MAX                       (0x0000003F)
+
+#define DDRDATA7CH1_CR_TXTRAINRANK2_REG                              (0x00000F28)
+  #define DDRDATA7CH1_CR_TXTRAINRANK2_TxDqDelay_OFF                    ( 0)
+  #define DDRDATA7CH1_CR_TXTRAINRANK2_TxDqDelay_WID                    ( 9)
+  #define DDRDATA7CH1_CR_TXTRAINRANK2_TxDqDelay_MSK                    (0x000001FF)
+  #define DDRDATA7CH1_CR_TXTRAINRANK2_TxDqDelay_MAX                    (0x000001FF)
+  #define DDRDATA7CH1_CR_TXTRAINRANK2_TxDqsDelay_OFF                   ( 9)
+  #define DDRDATA7CH1_CR_TXTRAINRANK2_TxDqsDelay_WID                   ( 9)
+  #define DDRDATA7CH1_CR_TXTRAINRANK2_TxDqsDelay_MSK                   (0x0003FE00)
+  #define DDRDATA7CH1_CR_TXTRAINRANK2_TxDqsDelay_MAX                   (0x000001FF)
+  #define DDRDATA7CH1_CR_TXTRAINRANK2_Spare0_OFF                       (18)
+  #define DDRDATA7CH1_CR_TXTRAINRANK2_Spare0_WID                       ( 2)
+  #define DDRDATA7CH1_CR_TXTRAINRANK2_Spare0_MSK                       (0x000C0000)
+  #define DDRDATA7CH1_CR_TXTRAINRANK2_Spare0_MAX                       (0x00000003)
+  #define DDRDATA7CH1_CR_TXTRAINRANK2_TxEqualization_OFF               (20)
+  #define DDRDATA7CH1_CR_TXTRAINRANK2_TxEqualization_WID               ( 6)
+  #define DDRDATA7CH1_CR_TXTRAINRANK2_TxEqualization_MSK               (0x03F00000)
+  #define DDRDATA7CH1_CR_TXTRAINRANK2_TxEqualization_MAX               (0x0000003F)
+  #define DDRDATA7CH1_CR_TXTRAINRANK2_Spare1_OFF                       (26)
+  #define DDRDATA7CH1_CR_TXTRAINRANK2_Spare1_WID                       ( 6)
+  #define DDRDATA7CH1_CR_TXTRAINRANK2_Spare1_MSK                       (0xFC000000)
+  #define DDRDATA7CH1_CR_TXTRAINRANK2_Spare1_MAX                       (0x0000003F)
+
+#define DDRDATA7CH1_CR_TXTRAINRANK3_REG                              (0x00000F2C)
+  #define DDRDATA7CH1_CR_TXTRAINRANK3_TxDqDelay_OFF                    ( 0)
+  #define DDRDATA7CH1_CR_TXTRAINRANK3_TxDqDelay_WID                    ( 9)
+  #define DDRDATA7CH1_CR_TXTRAINRANK3_TxDqDelay_MSK                    (0x000001FF)
+  #define DDRDATA7CH1_CR_TXTRAINRANK3_TxDqDelay_MAX                    (0x000001FF)
+  #define DDRDATA7CH1_CR_TXTRAINRANK3_TxDqsDelay_OFF                   ( 9)
+  #define DDRDATA7CH1_CR_TXTRAINRANK3_TxDqsDelay_WID                   ( 9)
+  #define DDRDATA7CH1_CR_TXTRAINRANK3_TxDqsDelay_MSK                   (0x0003FE00)
+  #define DDRDATA7CH1_CR_TXTRAINRANK3_TxDqsDelay_MAX                   (0x000001FF)
+  #define DDRDATA7CH1_CR_TXTRAINRANK3_Spare0_OFF                       (18)
+  #define DDRDATA7CH1_CR_TXTRAINRANK3_Spare0_WID                       ( 2)
+  #define DDRDATA7CH1_CR_TXTRAINRANK3_Spare0_MSK                       (0x000C0000)
+  #define DDRDATA7CH1_CR_TXTRAINRANK3_Spare0_MAX                       (0x00000003)
+  #define DDRDATA7CH1_CR_TXTRAINRANK3_TxEqualization_OFF               (20)
+  #define DDRDATA7CH1_CR_TXTRAINRANK3_TxEqualization_WID               ( 6)
+  #define DDRDATA7CH1_CR_TXTRAINRANK3_TxEqualization_MSK               (0x03F00000)
+  #define DDRDATA7CH1_CR_TXTRAINRANK3_TxEqualization_MAX               (0x0000003F)
+  #define DDRDATA7CH1_CR_TXTRAINRANK3_Spare1_OFF                       (26)
+  #define DDRDATA7CH1_CR_TXTRAINRANK3_Spare1_WID                       ( 6)
+  #define DDRDATA7CH1_CR_TXTRAINRANK3_Spare1_MSK                       (0xFC000000)
+  #define DDRDATA7CH1_CR_TXTRAINRANK3_Spare1_MAX                       (0x0000003F)
+
+#define DDRDATA7CH1_CR_TXPERBITRANK0_REG                             (0x00000F30)
+  #define DDRDATA7CH1_CR_TXPERBITRANK0_Lane0_OFF                       ( 0)
+  #define DDRDATA7CH1_CR_TXPERBITRANK0_Lane0_WID                       ( 4)
+  #define DDRDATA7CH1_CR_TXPERBITRANK0_Lane0_MSK                       (0x0000000F)
+  #define DDRDATA7CH1_CR_TXPERBITRANK0_Lane0_MAX                       (0x0000000F)
+  #define DDRDATA7CH1_CR_TXPERBITRANK0_Lane1_OFF                       ( 4)
+  #define DDRDATA7CH1_CR_TXPERBITRANK0_Lane1_WID                       ( 4)
+  #define DDRDATA7CH1_CR_TXPERBITRANK0_Lane1_MSK                       (0x000000F0)
+  #define DDRDATA7CH1_CR_TXPERBITRANK0_Lane1_MAX                       (0x0000000F)
+  #define DDRDATA7CH1_CR_TXPERBITRANK0_Lane2_OFF                       ( 8)
+  #define DDRDATA7CH1_CR_TXPERBITRANK0_Lane2_WID                       ( 4)
+  #define DDRDATA7CH1_CR_TXPERBITRANK0_Lane2_MSK                       (0x00000F00)
+  #define DDRDATA7CH1_CR_TXPERBITRANK0_Lane2_MAX                       (0x0000000F)
+  #define DDRDATA7CH1_CR_TXPERBITRANK0_Lane3_OFF                       (12)
+  #define DDRDATA7CH1_CR_TXPERBITRANK0_Lane3_WID                       ( 4)
+  #define DDRDATA7CH1_CR_TXPERBITRANK0_Lane3_MSK                       (0x0000F000)
+  #define DDRDATA7CH1_CR_TXPERBITRANK0_Lane3_MAX                       (0x0000000F)
+  #define DDRDATA7CH1_CR_TXPERBITRANK0_Lane4_OFF                       (16)
+  #define DDRDATA7CH1_CR_TXPERBITRANK0_Lane4_WID                       ( 4)
+  #define DDRDATA7CH1_CR_TXPERBITRANK0_Lane4_MSK                       (0x000F0000)
+  #define DDRDATA7CH1_CR_TXPERBITRANK0_Lane4_MAX                       (0x0000000F)
+  #define DDRDATA7CH1_CR_TXPERBITRANK0_Lane5_OFF                       (20)
+  #define DDRDATA7CH1_CR_TXPERBITRANK0_Lane5_WID                       ( 4)
+  #define DDRDATA7CH1_CR_TXPERBITRANK0_Lane5_MSK                       (0x00F00000)
+  #define DDRDATA7CH1_CR_TXPERBITRANK0_Lane5_MAX                       (0x0000000F)
+  #define DDRDATA7CH1_CR_TXPERBITRANK0_Lane6_OFF                       (24)
+  #define DDRDATA7CH1_CR_TXPERBITRANK0_Lane6_WID                       ( 4)
+  #define DDRDATA7CH1_CR_TXPERBITRANK0_Lane6_MSK                       (0x0F000000)
+  #define DDRDATA7CH1_CR_TXPERBITRANK0_Lane6_MAX                       (0x0000000F)
+  #define DDRDATA7CH1_CR_TXPERBITRANK0_Lane7_OFF                       (28)
+  #define DDRDATA7CH1_CR_TXPERBITRANK0_Lane7_WID                       ( 4)
+  #define DDRDATA7CH1_CR_TXPERBITRANK0_Lane7_MSK                       (0xF0000000)
+  #define DDRDATA7CH1_CR_TXPERBITRANK0_Lane7_MAX                       (0x0000000F)
+
+#define DDRDATA7CH1_CR_TXPERBITRANK1_REG                             (0x00000F34)
+  #define DDRDATA7CH1_CR_TXPERBITRANK1_Lane0_OFF                       ( 0)
+  #define DDRDATA7CH1_CR_TXPERBITRANK1_Lane0_WID                       ( 4)
+  #define DDRDATA7CH1_CR_TXPERBITRANK1_Lane0_MSK                       (0x0000000F)
+  #define DDRDATA7CH1_CR_TXPERBITRANK1_Lane0_MAX                       (0x0000000F)
+  #define DDRDATA7CH1_CR_TXPERBITRANK1_Lane1_OFF                       ( 4)
+  #define DDRDATA7CH1_CR_TXPERBITRANK1_Lane1_WID                       ( 4)
+  #define DDRDATA7CH1_CR_TXPERBITRANK1_Lane1_MSK                       (0x000000F0)
+  #define DDRDATA7CH1_CR_TXPERBITRANK1_Lane1_MAX                       (0x0000000F)
+  #define DDRDATA7CH1_CR_TXPERBITRANK1_Lane2_OFF                       ( 8)
+  #define DDRDATA7CH1_CR_TXPERBITRANK1_Lane2_WID                       ( 4)
+  #define DDRDATA7CH1_CR_TXPERBITRANK1_Lane2_MSK                       (0x00000F00)
+  #define DDRDATA7CH1_CR_TXPERBITRANK1_Lane2_MAX                       (0x0000000F)
+  #define DDRDATA7CH1_CR_TXPERBITRANK1_Lane3_OFF                       (12)
+  #define DDRDATA7CH1_CR_TXPERBITRANK1_Lane3_WID                       ( 4)
+  #define DDRDATA7CH1_CR_TXPERBITRANK1_Lane3_MSK                       (0x0000F000)
+  #define DDRDATA7CH1_CR_TXPERBITRANK1_Lane3_MAX                       (0x0000000F)
+  #define DDRDATA7CH1_CR_TXPERBITRANK1_Lane4_OFF                       (16)
+  #define DDRDATA7CH1_CR_TXPERBITRANK1_Lane4_WID                       ( 4)
+  #define DDRDATA7CH1_CR_TXPERBITRANK1_Lane4_MSK                       (0x000F0000)
+  #define DDRDATA7CH1_CR_TXPERBITRANK1_Lane4_MAX                       (0x0000000F)
+  #define DDRDATA7CH1_CR_TXPERBITRANK1_Lane5_OFF                       (20)
+  #define DDRDATA7CH1_CR_TXPERBITRANK1_Lane5_WID                       ( 4)
+  #define DDRDATA7CH1_CR_TXPERBITRANK1_Lane5_MSK                       (0x00F00000)
+  #define DDRDATA7CH1_CR_TXPERBITRANK1_Lane5_MAX                       (0x0000000F)
+  #define DDRDATA7CH1_CR_TXPERBITRANK1_Lane6_OFF                       (24)
+  #define DDRDATA7CH1_CR_TXPERBITRANK1_Lane6_WID                       ( 4)
+  #define DDRDATA7CH1_CR_TXPERBITRANK1_Lane6_MSK                       (0x0F000000)
+  #define DDRDATA7CH1_CR_TXPERBITRANK1_Lane6_MAX                       (0x0000000F)
+  #define DDRDATA7CH1_CR_TXPERBITRANK1_Lane7_OFF                       (28)
+  #define DDRDATA7CH1_CR_TXPERBITRANK1_Lane7_WID                       ( 4)
+  #define DDRDATA7CH1_CR_TXPERBITRANK1_Lane7_MSK                       (0xF0000000)
+  #define DDRDATA7CH1_CR_TXPERBITRANK1_Lane7_MAX                       (0x0000000F)
+
+#define DDRDATA7CH1_CR_TXPERBITRANK2_REG                             (0x00000F38)
+  #define DDRDATA7CH1_CR_TXPERBITRANK2_Lane0_OFF                       ( 0)
+  #define DDRDATA7CH1_CR_TXPERBITRANK2_Lane0_WID                       ( 4)
+  #define DDRDATA7CH1_CR_TXPERBITRANK2_Lane0_MSK                       (0x0000000F)
+  #define DDRDATA7CH1_CR_TXPERBITRANK2_Lane0_MAX                       (0x0000000F)
+  #define DDRDATA7CH1_CR_TXPERBITRANK2_Lane1_OFF                       ( 4)
+  #define DDRDATA7CH1_CR_TXPERBITRANK2_Lane1_WID                       ( 4)
+  #define DDRDATA7CH1_CR_TXPERBITRANK2_Lane1_MSK                       (0x000000F0)
+  #define DDRDATA7CH1_CR_TXPERBITRANK2_Lane1_MAX                       (0x0000000F)
+  #define DDRDATA7CH1_CR_TXPERBITRANK2_Lane2_OFF                       ( 8)
+  #define DDRDATA7CH1_CR_TXPERBITRANK2_Lane2_WID                       ( 4)
+  #define DDRDATA7CH1_CR_TXPERBITRANK2_Lane2_MSK                       (0x00000F00)
+  #define DDRDATA7CH1_CR_TXPERBITRANK2_Lane2_MAX                       (0x0000000F)
+  #define DDRDATA7CH1_CR_TXPERBITRANK2_Lane3_OFF                       (12)
+  #define DDRDATA7CH1_CR_TXPERBITRANK2_Lane3_WID                       ( 4)
+  #define DDRDATA7CH1_CR_TXPERBITRANK2_Lane3_MSK                       (0x0000F000)
+  #define DDRDATA7CH1_CR_TXPERBITRANK2_Lane3_MAX                       (0x0000000F)
+  #define DDRDATA7CH1_CR_TXPERBITRANK2_Lane4_OFF                       (16)
+  #define DDRDATA7CH1_CR_TXPERBITRANK2_Lane4_WID                       ( 4)
+  #define DDRDATA7CH1_CR_TXPERBITRANK2_Lane4_MSK                       (0x000F0000)
+  #define DDRDATA7CH1_CR_TXPERBITRANK2_Lane4_MAX                       (0x0000000F)
+  #define DDRDATA7CH1_CR_TXPERBITRANK2_Lane5_OFF                       (20)
+  #define DDRDATA7CH1_CR_TXPERBITRANK2_Lane5_WID                       ( 4)
+  #define DDRDATA7CH1_CR_TXPERBITRANK2_Lane5_MSK                       (0x00F00000)
+  #define DDRDATA7CH1_CR_TXPERBITRANK2_Lane5_MAX                       (0x0000000F)
+  #define DDRDATA7CH1_CR_TXPERBITRANK2_Lane6_OFF                       (24)
+  #define DDRDATA7CH1_CR_TXPERBITRANK2_Lane6_WID                       ( 4)
+  #define DDRDATA7CH1_CR_TXPERBITRANK2_Lane6_MSK                       (0x0F000000)
+  #define DDRDATA7CH1_CR_TXPERBITRANK2_Lane6_MAX                       (0x0000000F)
+  #define DDRDATA7CH1_CR_TXPERBITRANK2_Lane7_OFF                       (28)
+  #define DDRDATA7CH1_CR_TXPERBITRANK2_Lane7_WID                       ( 4)
+  #define DDRDATA7CH1_CR_TXPERBITRANK2_Lane7_MSK                       (0xF0000000)
+  #define DDRDATA7CH1_CR_TXPERBITRANK2_Lane7_MAX                       (0x0000000F)
+
+#define DDRDATA7CH1_CR_TXPERBITRANK3_REG                             (0x00000F3C)
+  #define DDRDATA7CH1_CR_TXPERBITRANK3_Lane0_OFF                       ( 0)
+  #define DDRDATA7CH1_CR_TXPERBITRANK3_Lane0_WID                       ( 4)
+  #define DDRDATA7CH1_CR_TXPERBITRANK3_Lane0_MSK                       (0x0000000F)
+  #define DDRDATA7CH1_CR_TXPERBITRANK3_Lane0_MAX                       (0x0000000F)
+  #define DDRDATA7CH1_CR_TXPERBITRANK3_Lane1_OFF                       ( 4)
+  #define DDRDATA7CH1_CR_TXPERBITRANK3_Lane1_WID                       ( 4)
+  #define DDRDATA7CH1_CR_TXPERBITRANK3_Lane1_MSK                       (0x000000F0)
+  #define DDRDATA7CH1_CR_TXPERBITRANK3_Lane1_MAX                       (0x0000000F)
+  #define DDRDATA7CH1_CR_TXPERBITRANK3_Lane2_OFF                       ( 8)
+  #define DDRDATA7CH1_CR_TXPERBITRANK3_Lane2_WID                       ( 4)
+  #define DDRDATA7CH1_CR_TXPERBITRANK3_Lane2_MSK                       (0x00000F00)
+  #define DDRDATA7CH1_CR_TXPERBITRANK3_Lane2_MAX                       (0x0000000F)
+  #define DDRDATA7CH1_CR_TXPERBITRANK3_Lane3_OFF                       (12)
+  #define DDRDATA7CH1_CR_TXPERBITRANK3_Lane3_WID                       ( 4)
+  #define DDRDATA7CH1_CR_TXPERBITRANK3_Lane3_MSK                       (0x0000F000)
+  #define DDRDATA7CH1_CR_TXPERBITRANK3_Lane3_MAX                       (0x0000000F)
+  #define DDRDATA7CH1_CR_TXPERBITRANK3_Lane4_OFF                       (16)
+  #define DDRDATA7CH1_CR_TXPERBITRANK3_Lane4_WID                       ( 4)
+  #define DDRDATA7CH1_CR_TXPERBITRANK3_Lane4_MSK                       (0x000F0000)
+  #define DDRDATA7CH1_CR_TXPERBITRANK3_Lane4_MAX                       (0x0000000F)
+  #define DDRDATA7CH1_CR_TXPERBITRANK3_Lane5_OFF                       (20)
+  #define DDRDATA7CH1_CR_TXPERBITRANK3_Lane5_WID                       ( 4)
+  #define DDRDATA7CH1_CR_TXPERBITRANK3_Lane5_MSK                       (0x00F00000)
+  #define DDRDATA7CH1_CR_TXPERBITRANK3_Lane5_MAX                       (0x0000000F)
+  #define DDRDATA7CH1_CR_TXPERBITRANK3_Lane6_OFF                       (24)
+  #define DDRDATA7CH1_CR_TXPERBITRANK3_Lane6_WID                       ( 4)
+  #define DDRDATA7CH1_CR_TXPERBITRANK3_Lane6_MSK                       (0x0F000000)
+  #define DDRDATA7CH1_CR_TXPERBITRANK3_Lane6_MAX                       (0x0000000F)
+  #define DDRDATA7CH1_CR_TXPERBITRANK3_Lane7_OFF                       (28)
+  #define DDRDATA7CH1_CR_TXPERBITRANK3_Lane7_WID                       ( 4)
+  #define DDRDATA7CH1_CR_TXPERBITRANK3_Lane7_MSK                       (0xF0000000)
+  #define DDRDATA7CH1_CR_TXPERBITRANK3_Lane7_MAX                       (0x0000000F)
+
+#define DDRDATA7CH1_CR_RCOMPDATA0_REG                                (0x00000F40)
+  #define DDRDATA7CH1_CR_RCOMPDATA0_RcompDrvUp_OFF                     ( 0)
+  #define DDRDATA7CH1_CR_RCOMPDATA0_RcompDrvUp_WID                     ( 6)
+  #define DDRDATA7CH1_CR_RCOMPDATA0_RcompDrvUp_MSK                     (0x0000003F)
+  #define DDRDATA7CH1_CR_RCOMPDATA0_RcompDrvUp_MAX                     (0x0000003F)
+  #define DDRDATA7CH1_CR_RCOMPDATA0_Spare0_OFF                         ( 6)
+  #define DDRDATA7CH1_CR_RCOMPDATA0_Spare0_WID                         ( 3)
+  #define DDRDATA7CH1_CR_RCOMPDATA0_Spare0_MSK                         (0x000001C0)
+  #define DDRDATA7CH1_CR_RCOMPDATA0_Spare0_MAX                         (0x00000007)
+  #define DDRDATA7CH1_CR_RCOMPDATA0_RcompDrvDown_OFF                   ( 9)
+  #define DDRDATA7CH1_CR_RCOMPDATA0_RcompDrvDown_WID                   ( 6)
+  #define DDRDATA7CH1_CR_RCOMPDATA0_RcompDrvDown_MSK                   (0x00007E00)
+  #define DDRDATA7CH1_CR_RCOMPDATA0_RcompDrvDown_MAX                   (0x0000003F)
+  #define DDRDATA7CH1_CR_RCOMPDATA0_VTComp_OFF                         (15)
+  #define DDRDATA7CH1_CR_RCOMPDATA0_VTComp_WID                         ( 5)
+  #define DDRDATA7CH1_CR_RCOMPDATA0_VTComp_MSK                         (0x000F8000)
+  #define DDRDATA7CH1_CR_RCOMPDATA0_VTComp_MAX                         (0x0000001F)
+  #define DDRDATA7CH1_CR_RCOMPDATA0_TcoComp_OFF                        (20)
+  #define DDRDATA7CH1_CR_RCOMPDATA0_TcoComp_WID                        ( 6)
+  #define DDRDATA7CH1_CR_RCOMPDATA0_TcoComp_MSK                        (0x03F00000)
+  #define DDRDATA7CH1_CR_RCOMPDATA0_TcoComp_MAX                        (0x0000003F)
+  #define DDRDATA7CH1_CR_RCOMPDATA0_SlewRateComp_OFF                   (26)
+  #define DDRDATA7CH1_CR_RCOMPDATA0_SlewRateComp_WID                   ( 5)
+  #define DDRDATA7CH1_CR_RCOMPDATA0_SlewRateComp_MSK                   (0x7C000000)
+  #define DDRDATA7CH1_CR_RCOMPDATA0_SlewRateComp_MAX                   (0x0000001F)
+  #define DDRDATA7CH1_CR_RCOMPDATA0_Spare2_OFF                         (31)
+  #define DDRDATA7CH1_CR_RCOMPDATA0_Spare2_WID                         ( 1)
+  #define DDRDATA7CH1_CR_RCOMPDATA0_Spare2_MSK                         (0x80000000)
+  #define DDRDATA7CH1_CR_RCOMPDATA0_Spare2_MAX                         (0x00000001)
+
+#define DDRDATA7CH1_CR_RCOMPDATA1_REG                                (0x00000F44)
+  #define DDRDATA7CH1_CR_RCOMPDATA1_RcompOdtUp_OFF                     ( 0)
+  #define DDRDATA7CH1_CR_RCOMPDATA1_RcompOdtUp_WID                     ( 6)
+  #define DDRDATA7CH1_CR_RCOMPDATA1_RcompOdtUp_MSK                     (0x0000003F)
+  #define DDRDATA7CH1_CR_RCOMPDATA1_RcompOdtUp_MAX                     (0x0000003F)
+  #define DDRDATA7CH1_CR_RCOMPDATA1_Spare0_OFF                         ( 6)
+  #define DDRDATA7CH1_CR_RCOMPDATA1_Spare0_WID                         ( 3)
+  #define DDRDATA7CH1_CR_RCOMPDATA1_Spare0_MSK                         (0x000001C0)
+  #define DDRDATA7CH1_CR_RCOMPDATA1_Spare0_MAX                         (0x00000007)
+  #define DDRDATA7CH1_CR_RCOMPDATA1_RcompOdtDown_OFF                   ( 9)
+  #define DDRDATA7CH1_CR_RCOMPDATA1_RcompOdtDown_WID                   ( 6)
+  #define DDRDATA7CH1_CR_RCOMPDATA1_RcompOdtDown_MSK                   (0x00007E00)
+  #define DDRDATA7CH1_CR_RCOMPDATA1_RcompOdtDown_MAX                   (0x0000003F)
+  #define DDRDATA7CH1_CR_RCOMPDATA1_Spare1_OFF                         (15)
+  #define DDRDATA7CH1_CR_RCOMPDATA1_Spare1_WID                         ( 1)
+  #define DDRDATA7CH1_CR_RCOMPDATA1_Spare1_MSK                         (0x00008000)
+  #define DDRDATA7CH1_CR_RCOMPDATA1_Spare1_MAX                         (0x00000001)
+  #define DDRDATA7CH1_CR_RCOMPDATA1_PanicDrvDn_OFF                     (16)
+  #define DDRDATA7CH1_CR_RCOMPDATA1_PanicDrvDn_WID                     ( 6)
+  #define DDRDATA7CH1_CR_RCOMPDATA1_PanicDrvDn_MSK                     (0x003F0000)
+  #define DDRDATA7CH1_CR_RCOMPDATA1_PanicDrvDn_MAX                     (0x0000003F)
+  #define DDRDATA7CH1_CR_RCOMPDATA1_PanicDrvUp_OFF                     (22)
+  #define DDRDATA7CH1_CR_RCOMPDATA1_PanicDrvUp_WID                     ( 6)
+  #define DDRDATA7CH1_CR_RCOMPDATA1_PanicDrvUp_MSK                     (0x0FC00000)
+  #define DDRDATA7CH1_CR_RCOMPDATA1_PanicDrvUp_MAX                     (0x0000003F)
+  #define DDRDATA7CH1_CR_RCOMPDATA1_LevelShifterComp_OFF               (28)
+  #define DDRDATA7CH1_CR_RCOMPDATA1_LevelShifterComp_WID               ( 3)
+  #define DDRDATA7CH1_CR_RCOMPDATA1_LevelShifterComp_MSK               (0x70000000)
+  #define DDRDATA7CH1_CR_RCOMPDATA1_LevelShifterComp_MAX               (0x00000007)
+  #define DDRDATA7CH1_CR_RCOMPDATA1_Spare2_OFF                         (31)
+  #define DDRDATA7CH1_CR_RCOMPDATA1_Spare2_WID                         ( 1)
+  #define DDRDATA7CH1_CR_RCOMPDATA1_Spare2_MSK                         (0x80000000)
+  #define DDRDATA7CH1_CR_RCOMPDATA1_Spare2_MAX                         (0x00000001)
+
+#define DDRDATA7CH1_CR_TXXTALK_REG                                   (0x00000F48)
+  #define DDRDATA7CH1_CR_TXXTALK_Lane0_OFF                             ( 0)
+  #define DDRDATA7CH1_CR_TXXTALK_Lane0_WID                             ( 4)
+  #define DDRDATA7CH1_CR_TXXTALK_Lane0_MSK                             (0x0000000F)
+  #define DDRDATA7CH1_CR_TXXTALK_Lane0_MAX                             (0x0000000F)
+  #define DDRDATA7CH1_CR_TXXTALK_Lane1_OFF                             ( 4)
+  #define DDRDATA7CH1_CR_TXXTALK_Lane1_WID                             ( 4)
+  #define DDRDATA7CH1_CR_TXXTALK_Lane1_MSK                             (0x000000F0)
+  #define DDRDATA7CH1_CR_TXXTALK_Lane1_MAX                             (0x0000000F)
+  #define DDRDATA7CH1_CR_TXXTALK_Lane2_OFF                             ( 8)
+  #define DDRDATA7CH1_CR_TXXTALK_Lane2_WID                             ( 4)
+  #define DDRDATA7CH1_CR_TXXTALK_Lane2_MSK                             (0x00000F00)
+  #define DDRDATA7CH1_CR_TXXTALK_Lane2_MAX                             (0x0000000F)
+  #define DDRDATA7CH1_CR_TXXTALK_Lane3_OFF                             (12)
+  #define DDRDATA7CH1_CR_TXXTALK_Lane3_WID                             ( 4)
+  #define DDRDATA7CH1_CR_TXXTALK_Lane3_MSK                             (0x0000F000)
+  #define DDRDATA7CH1_CR_TXXTALK_Lane3_MAX                             (0x0000000F)
+  #define DDRDATA7CH1_CR_TXXTALK_Lane4_OFF                             (16)
+  #define DDRDATA7CH1_CR_TXXTALK_Lane4_WID                             ( 4)
+  #define DDRDATA7CH1_CR_TXXTALK_Lane4_MSK                             (0x000F0000)
+  #define DDRDATA7CH1_CR_TXXTALK_Lane4_MAX                             (0x0000000F)
+  #define DDRDATA7CH1_CR_TXXTALK_Lane5_OFF                             (20)
+  #define DDRDATA7CH1_CR_TXXTALK_Lane5_WID                             ( 4)
+  #define DDRDATA7CH1_CR_TXXTALK_Lane5_MSK                             (0x00F00000)
+  #define DDRDATA7CH1_CR_TXXTALK_Lane5_MAX                             (0x0000000F)
+  #define DDRDATA7CH1_CR_TXXTALK_Lane6_OFF                             (24)
+  #define DDRDATA7CH1_CR_TXXTALK_Lane6_WID                             ( 4)
+  #define DDRDATA7CH1_CR_TXXTALK_Lane6_MSK                             (0x0F000000)
+  #define DDRDATA7CH1_CR_TXXTALK_Lane6_MAX                             (0x0000000F)
+  #define DDRDATA7CH1_CR_TXXTALK_Lane7_OFF                             (28)
+  #define DDRDATA7CH1_CR_TXXTALK_Lane7_WID                             ( 4)
+  #define DDRDATA7CH1_CR_TXXTALK_Lane7_MSK                             (0xF0000000)
+  #define DDRDATA7CH1_CR_TXXTALK_Lane7_MAX                             (0x0000000F)
+
+#define DDRDATA7CH1_CR_RXOFFSETVDQ_REG                               (0x00000F4C)
+  #define DDRDATA7CH1_CR_RXOFFSETVDQ_Lane0_OFF                         ( 0)
+  #define DDRDATA7CH1_CR_RXOFFSETVDQ_Lane0_WID                         ( 4)
+  #define DDRDATA7CH1_CR_RXOFFSETVDQ_Lane0_MSK                         (0x0000000F)
+  #define DDRDATA7CH1_CR_RXOFFSETVDQ_Lane0_MAX                         (0x0000000F)
+  #define DDRDATA7CH1_CR_RXOFFSETVDQ_Lane1_OFF                         ( 4)
+  #define DDRDATA7CH1_CR_RXOFFSETVDQ_Lane1_WID                         ( 4)
+  #define DDRDATA7CH1_CR_RXOFFSETVDQ_Lane1_MSK                         (0x000000F0)
+  #define DDRDATA7CH1_CR_RXOFFSETVDQ_Lane1_MAX                         (0x0000000F)
+  #define DDRDATA7CH1_CR_RXOFFSETVDQ_Lane2_OFF                         ( 8)
+  #define DDRDATA7CH1_CR_RXOFFSETVDQ_Lane2_WID                         ( 4)
+  #define DDRDATA7CH1_CR_RXOFFSETVDQ_Lane2_MSK                         (0x00000F00)
+  #define DDRDATA7CH1_CR_RXOFFSETVDQ_Lane2_MAX                         (0x0000000F)
+  #define DDRDATA7CH1_CR_RXOFFSETVDQ_Lane3_OFF                         (12)
+  #define DDRDATA7CH1_CR_RXOFFSETVDQ_Lane3_WID                         ( 4)
+  #define DDRDATA7CH1_CR_RXOFFSETVDQ_Lane3_MSK                         (0x0000F000)
+  #define DDRDATA7CH1_CR_RXOFFSETVDQ_Lane3_MAX                         (0x0000000F)
+  #define DDRDATA7CH1_CR_RXOFFSETVDQ_Lane4_OFF                         (16)
+  #define DDRDATA7CH1_CR_RXOFFSETVDQ_Lane4_WID                         ( 4)
+  #define DDRDATA7CH1_CR_RXOFFSETVDQ_Lane4_MSK                         (0x000F0000)
+  #define DDRDATA7CH1_CR_RXOFFSETVDQ_Lane4_MAX                         (0x0000000F)
+  #define DDRDATA7CH1_CR_RXOFFSETVDQ_Lane5_OFF                         (20)
+  #define DDRDATA7CH1_CR_RXOFFSETVDQ_Lane5_WID                         ( 4)
+  #define DDRDATA7CH1_CR_RXOFFSETVDQ_Lane5_MSK                         (0x00F00000)
+  #define DDRDATA7CH1_CR_RXOFFSETVDQ_Lane5_MAX                         (0x0000000F)
+  #define DDRDATA7CH1_CR_RXOFFSETVDQ_Lane6_OFF                         (24)
+  #define DDRDATA7CH1_CR_RXOFFSETVDQ_Lane6_WID                         ( 4)
+  #define DDRDATA7CH1_CR_RXOFFSETVDQ_Lane6_MSK                         (0x0F000000)
+  #define DDRDATA7CH1_CR_RXOFFSETVDQ_Lane6_MAX                         (0x0000000F)
+  #define DDRDATA7CH1_CR_RXOFFSETVDQ_Lane7_OFF                         (28)
+  #define DDRDATA7CH1_CR_RXOFFSETVDQ_Lane7_WID                         ( 4)
+  #define DDRDATA7CH1_CR_RXOFFSETVDQ_Lane7_MSK                         (0xF0000000)
+  #define DDRDATA7CH1_CR_RXOFFSETVDQ_Lane7_MAX                         (0x0000000F)
+
+#define DDRDATA7CH1_CR_DDRDATARESERVED_REG                           (0x00000F50)
+  #define DDRDATA7CH1_CR_DDRDATARESERVED_Spare_OFF                     ( 0)
+  #define DDRDATA7CH1_CR_DDRDATARESERVED_Spare_WID                     (32)
+  #define DDRDATA7CH1_CR_DDRDATARESERVED_Spare_MSK                     (0xFFFFFFFF)
+  #define DDRDATA7CH1_CR_DDRDATARESERVED_Spare_MAX                     (0xFFFFFFFF)
+
+#define DDRDATA7CH1_CR_DATATRAINFEEDBACK_REG                         (0x00000F54)
+  #define DDRDATA7CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_OFF       ( 0)
+  #define DDRDATA7CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_WID       ( 9)
+  #define DDRDATA7CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_MSK       (0x000001FF)
+  #define DDRDATA7CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_MAX       (0x000001FF)
+  #define DDRDATA7CH1_CR_DATATRAINFEEDBACK_Spare_OFF                   ( 9)
+  #define DDRDATA7CH1_CR_DATATRAINFEEDBACK_Spare_WID                   (23)
+  #define DDRDATA7CH1_CR_DATATRAINFEEDBACK_Spare_MSK                   (0xFFFFFE00)
+  #define DDRDATA7CH1_CR_DATATRAINFEEDBACK_Spare_MAX                   (0x007FFFFF)
+
+#define DDRDATA7CH1_CR_DLLPITESTANDADC_REG                           (0x00000F58)
+  #define DDRDATA7CH1_CR_DLLPITESTANDADC_RunTest_OFF                   ( 0)
+  #define DDRDATA7CH1_CR_DLLPITESTANDADC_RunTest_WID                   ( 1)
+  #define DDRDATA7CH1_CR_DLLPITESTANDADC_RunTest_MSK                   (0x00000001)
+  #define DDRDATA7CH1_CR_DLLPITESTANDADC_RunTest_MAX                   (0x00000001)
+  #define DDRDATA7CH1_CR_DLLPITESTANDADC_RunTest_DEF                   (0x00000000)
+  #define DDRDATA7CH1_CR_DLLPITESTANDADC_Load_OFF                      ( 1)
+  #define DDRDATA7CH1_CR_DLLPITESTANDADC_Load_WID                      ( 1)
+  #define DDRDATA7CH1_CR_DLLPITESTANDADC_Load_MSK                      (0x00000002)
+  #define DDRDATA7CH1_CR_DLLPITESTANDADC_Load_MAX                      (0x00000001)
+  #define DDRDATA7CH1_CR_DLLPITESTANDADC_Load_DEF                      (0x00000000)
+  #define DDRDATA7CH1_CR_DLLPITESTANDADC_ModeHVM_OFF                   ( 2)
+  #define DDRDATA7CH1_CR_DLLPITESTANDADC_ModeHVM_WID                   ( 1)
+  #define DDRDATA7CH1_CR_DLLPITESTANDADC_ModeHVM_MSK                   (0x00000004)
+  #define DDRDATA7CH1_CR_DLLPITESTANDADC_ModeHVM_MAX                   (0x00000001)
+  #define DDRDATA7CH1_CR_DLLPITESTANDADC_ModeHVM_DEF                   (0x00000000)
+  #define DDRDATA7CH1_CR_DLLPITESTANDADC_ModeDV_OFF                    ( 3)
+  #define DDRDATA7CH1_CR_DLLPITESTANDADC_ModeDV_WID                    ( 1)
+  #define DDRDATA7CH1_CR_DLLPITESTANDADC_ModeDV_MSK                    (0x00000008)
+  #define DDRDATA7CH1_CR_DLLPITESTANDADC_ModeDV_MAX                    (0x00000001)
+  #define DDRDATA7CH1_CR_DLLPITESTANDADC_ModeDV_DEF                    (0x00000000)
+  #define DDRDATA7CH1_CR_DLLPITESTANDADC_ModeADC_OFF                   ( 4)
+  #define DDRDATA7CH1_CR_DLLPITESTANDADC_ModeADC_WID                   ( 1)
+  #define DDRDATA7CH1_CR_DLLPITESTANDADC_ModeADC_MSK                   (0x00000010)
+  #define DDRDATA7CH1_CR_DLLPITESTANDADC_ModeADC_MAX                   (0x00000001)
+  #define DDRDATA7CH1_CR_DLLPITESTANDADC_ModeADC_DEF                   (0x00000000)
+  #define DDRDATA7CH1_CR_DLLPITESTANDADC_LoadCount_OFF                 ( 5)
+  #define DDRDATA7CH1_CR_DLLPITESTANDADC_LoadCount_WID                 (10)
+  #define DDRDATA7CH1_CR_DLLPITESTANDADC_LoadCount_MSK                 (0x00007FE0)
+  #define DDRDATA7CH1_CR_DLLPITESTANDADC_LoadCount_MAX                 (0x000003FF)
+  #define DDRDATA7CH1_CR_DLLPITESTANDADC_CountStatus_OFF               (15)
+  #define DDRDATA7CH1_CR_DLLPITESTANDADC_CountStatus_WID               (10)
+  #define DDRDATA7CH1_CR_DLLPITESTANDADC_CountStatus_MSK               (0x01FF8000)
+  #define DDRDATA7CH1_CR_DLLPITESTANDADC_CountStatus_MAX               (0x000003FF)
+  #define DDRDATA7CH1_CR_DLLPITESTANDADC_CountStatus_DEF               (0x00000000)
+  #define DDRDATA7CH1_CR_DLLPITESTANDADC_Spare_OFF                     (25)
+  #define DDRDATA7CH1_CR_DLLPITESTANDADC_Spare_WID                     ( 7)
+  #define DDRDATA7CH1_CR_DLLPITESTANDADC_Spare_MSK                     (0xFE000000)
+  #define DDRDATA7CH1_CR_DLLPITESTANDADC_Spare_MAX                     (0x0000007F)
+
+#define DDRDATA7CH1_CR_DDRCRDATAOFFSETCOMP_REG                       (0x00000F5C)
+  #define DDRDATA7CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_OFF     ( 0)
+  #define DDRDATA7CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_WID     ( 6)
+  #define DDRDATA7CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MSK     (0x0000003F)
+  #define DDRDATA7CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MAX     (0x0000003F)
+  #define DDRDATA7CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_DEF     (0x00000000)
+  #define DDRDATA7CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_OFF   ( 6)
+  #define DDRDATA7CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_WID   ( 6)
+  #define DDRDATA7CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MSK   (0x00000FC0)
+  #define DDRDATA7CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MAX   (0x0000003F)
+  #define DDRDATA7CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_DEF   (0x00000000)
+  #define DDRDATA7CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_OFF     (12)
+  #define DDRDATA7CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_WID     ( 5)
+  #define DDRDATA7CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MSK     (0x0001F000)
+  #define DDRDATA7CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MAX     (0x0000001F)
+  #define DDRDATA7CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_DEF     (0x00000000)
+  #define DDRDATA7CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_OFF   (17)
+  #define DDRDATA7CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_WID   ( 5)
+  #define DDRDATA7CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MSK   (0x003E0000)
+  #define DDRDATA7CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MAX   (0x0000001F)
+  #define DDRDATA7CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_DEF   (0x00000000)
+  #define DDRDATA7CH1_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_OFF       (22)
+  #define DDRDATA7CH1_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_WID       ( 5)
+  #define DDRDATA7CH1_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_MSK       (0x07C00000)
+  #define DDRDATA7CH1_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_MAX       (0x0000001F)
+  #define DDRDATA7CH1_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_DEF       (0x00000000)
+  #define DDRDATA7CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_OFF  (27)
+  #define DDRDATA7CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_WID  ( 5)
+  #define DDRDATA7CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MSK  (0xF8000000)
+  #define DDRDATA7CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MAX  (0x0000001F)
+  #define DDRDATA7CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_DEF  (0x00000000)
+
+#define DDRDATA7CH1_CR_DDRCRDATACONTROL1_REG                         (0x00000F60)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_RefPi_OFF                   ( 0)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_RefPi_WID                   ( 4)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_RefPi_MSK                   (0x0000000F)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_RefPi_MAX                   (0x0000000F)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_RefPi_DEF                   (0x00000000)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_DllMask_OFF                 ( 4)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_DllMask_WID                 ( 2)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_DllMask_MSK                 (0x00000030)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_DllMask_MAX                 (0x00000003)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_DllMask_DEF                 (0x00000000)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_DllWeakLock_OFF             ( 6)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_DllWeakLock_WID             ( 1)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_DllWeakLock_MSK             (0x00000040)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_DllWeakLock_MAX             (0x00000001)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_DllWeakLock_DEF             (0x00000000)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_OFF      ( 7)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_WID      ( 3)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MSK      (0x00000380)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MAX      (0x00000007)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_DEF      (0x00000000)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_OFF               (10)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_WID               ( 3)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_MSK               (0x00001C00)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_MAX               (0x00000007)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_DEF               (0x00000000)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_OdtDelay_OFF                (13)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_OdtDelay_WID                ( 4)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_OdtDelay_MSK                (0x0001E000)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_OdtDelay_MAX                (0x0000000F)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_OdtDelay_DEF                (0x00000000)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_OdtDuration_OFF             (17)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_OdtDuration_WID             ( 3)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_OdtDuration_MSK             (0x000E0000)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_OdtDuration_MAX             (0x00000007)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_OdtDuration_DEF             (0x00000000)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_OFF           (20)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_WID           ( 4)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_MSK           (0x00F00000)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_MAX           (0x0000000F)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_DEF           (0x00000000)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_OFF        (24)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_WID        ( 3)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_MSK        (0x07000000)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_MAX        (0x00000007)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_DEF        (0x00000000)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_BurstEndODTDelay_OFF        (27)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_BurstEndODTDelay_WID        ( 3)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_BurstEndODTDelay_MSK        (0x38000000)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_BurstEndODTDelay_MAX        (0x00000007)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_BurstEndODTDelay_DEF        (0x00000000)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_OFF          (30)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_WID          ( 1)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_MSK          (0x40000000)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_MAX          (0x00000001)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_DEF          (0x00000000)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_Rsvd1_OFF                   (31)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_Rsvd1_WID                   ( 1)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_Rsvd1_MSK                   (0x80000000)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_Rsvd1_MAX                   (0x00000001)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_Rsvd1_DEF                   (0x00000000)
+
+#define DDRDATA7CH1_CR_DDRCRDATACONTROL2_REG                         (0x00000F64)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_OFF            ( 0)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_WID            ( 5)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_MSK            (0x0000001F)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_MAX            (0x0000001F)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_DEF            (0x00000000)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_OFF             ( 5)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_WID             ( 1)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_MSK             (0x00000020)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_MAX             (0x00000001)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_DEF             (0x00000000)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_ForceRxOn_OFF               ( 6)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_ForceRxOn_WID               ( 1)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_ForceRxOn_MSK               (0x00000040)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_ForceRxOn_MAX               (0x00000001)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_ForceRxOn_DEF               (0x00000000)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_LeakerComp_OFF              ( 7)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_LeakerComp_WID              ( 2)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_LeakerComp_MSK              (0x00000180)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_LeakerComp_MAX              (0x00000003)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_LeakerComp_DEF              (0x00000000)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_OFF          ( 9)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_WID          ( 4)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_MSK          (0x00001E00)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_MAX          (0x0000000F)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_DEF          (0x00000008)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_OFF             (13)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_WID             ( 5)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_MSK             (0x0003E000)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_MAX             (0x0000001F)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_DEF             (0x00000011)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_OFF             (18)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_WID             ( 1)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_MSK             (0x00040000)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_MAX             (0x00000001)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_DEF             (0x00000000)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_Spare_OFF                   (19)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_Spare_WID                   (13)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_Spare_MSK                   (0xFFF80000)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_Spare_MAX                   (0x00001FFF)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_Spare_DEF                   (0x00000000)
+
+#define DDRDATA7CH1_CR_DDRCRVREFCONTROL_REG                          (0x00000F68)
+  #define DDRDATA7CH1_CR_DDRCRVREFCONTROL_VrefCtl_OFF                  ( 0)
+  #define DDRDATA7CH1_CR_DDRCRVREFCONTROL_VrefCtl_WID                  (24)
+  #define DDRDATA7CH1_CR_DDRCRVREFCONTROL_VrefCtl_MSK                  (0x00FFFFFF)
+  #define DDRDATA7CH1_CR_DDRCRVREFCONTROL_VrefCtl_MAX                  (0x00FFFFFF)
+  #define DDRDATA7CH1_CR_DDRCRVREFCONTROL_VrefCtl_DEF                  (0x000E453A)
+  #define DDRDATA7CH1_CR_DDRCRVREFCONTROL_OutputCode_OFF               (24)
+  #define DDRDATA7CH1_CR_DDRCRVREFCONTROL_OutputCode_WID               ( 8)
+  #define DDRDATA7CH1_CR_DDRCRVREFCONTROL_OutputCode_MSK               (0xFF000000)
+  #define DDRDATA7CH1_CR_DDRCRVREFCONTROL_OutputCode_MAX               (0x000000FF)
+  #define DDRDATA7CH1_CR_DDRCRVREFCONTROL_OutputCode_DEF               (0x00000000)
+
+#define DDRDATA7CH1_CR_DDRCRVSSHICONTROL_REG                         (0x00000F6C)
+  #define DDRDATA7CH1_CR_DDRCRVSSHICONTROL_VssHiCtl_OFF                ( 0)
+  #define DDRDATA7CH1_CR_DDRCRVSSHICONTROL_VssHiCtl_WID                (24)
+  #define DDRDATA7CH1_CR_DDRCRVSSHICONTROL_VssHiCtl_MSK                (0x00FFFFFF)
+  #define DDRDATA7CH1_CR_DDRCRVSSHICONTROL_VssHiCtl_MAX                (0x00FFFFFF)
+  #define DDRDATA7CH1_CR_DDRCRVSSHICONTROL_VssHiCtl_DEF                (0x004D8238)
+  #define DDRDATA7CH1_CR_DDRCRVSSHICONTROL_OutputCode_OFF              (24)
+  #define DDRDATA7CH1_CR_DDRCRVSSHICONTROL_OutputCode_WID              ( 8)
+  #define DDRDATA7CH1_CR_DDRCRVSSHICONTROL_OutputCode_MSK              (0xFF000000)
+  #define DDRDATA7CH1_CR_DDRCRVSSHICONTROL_OutputCode_MAX              (0x000000FF)
+  #define DDRDATA7CH1_CR_DDRCRVSSHICONTROL_OutputCode_DEF              (0x00000000)
+
+#define DDRDATA7CH1_CR_DDRCRVSSHIORVREFCONTROL_REG                   (0x00000F6C)
+  #define DDRDATA7CH1_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_OFF    ( 0)
+  #define DDRDATA7CH1_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_WID    (24)
+  #define DDRDATA7CH1_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_MSK    (0x00FFFFFF)
+  #define DDRDATA7CH1_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_MAX    (0x00FFFFFF)
+  #define DDRDATA7CH1_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_DEF    (0x00000000)
+  #define DDRDATA7CH1_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_OFF        (24)
+  #define DDRDATA7CH1_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_WID        ( 8)
+  #define DDRDATA7CH1_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_MSK        (0xFF000000)
+  #define DDRDATA7CH1_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_MAX        (0x000000FF)
+  #define DDRDATA7CH1_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_DEF        (0x00000000)
+
+#define DDRDATA7CH1_CR_DDRCRDATAOFFSETTRAIN_REG                      (0x00000F70)
+  #define DDRDATA7CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_OFF          ( 0)
+  #define DDRDATA7CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_WID          ( 6)
+  #define DDRDATA7CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MSK          (0x0000003F)
+  #define DDRDATA7CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MAX          (0x0000003F)
+  #define DDRDATA7CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_DEF          (0x00000000)
+  #define DDRDATA7CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_OFF          ( 6)
+  #define DDRDATA7CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_WID          ( 6)
+  #define DDRDATA7CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MSK          (0x00000FC0)
+  #define DDRDATA7CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MAX          (0x0000003F)
+  #define DDRDATA7CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_DEF          (0x00000000)
+  #define DDRDATA7CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_OFF           (12)
+  #define DDRDATA7CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_WID           ( 6)
+  #define DDRDATA7CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MSK           (0x0003F000)
+  #define DDRDATA7CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MAX           (0x0000003F)
+  #define DDRDATA7CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_DEF           (0x00000000)
+  #define DDRDATA7CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_OFF          (18)
+  #define DDRDATA7CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_WID          ( 6)
+  #define DDRDATA7CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MSK          (0x00FC0000)
+  #define DDRDATA7CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MAX          (0x0000003F)
+  #define DDRDATA7CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_DEF          (0x00000000)
+  #define DDRDATA7CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_OFF           (24)
+  #define DDRDATA7CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_WID           ( 7)
+  #define DDRDATA7CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MSK           (0x7F000000)
+  #define DDRDATA7CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MAX           (0x0000007F)
+  #define DDRDATA7CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_DEF           (0x00000000)
+  #define DDRDATA7CH1_CR_DDRCRDATAOFFSETTRAIN_Spare_OFF                (31)
+  #define DDRDATA7CH1_CR_DDRCRDATAOFFSETTRAIN_Spare_WID                ( 1)
+  #define DDRDATA7CH1_CR_DDRCRDATAOFFSETTRAIN_Spare_MSK                (0x80000000)
+  #define DDRDATA7CH1_CR_DDRCRDATAOFFSETTRAIN_Spare_MAX                (0x00000001)
+  #define DDRDATA7CH1_CR_DDRCRDATAOFFSETTRAIN_Spare_DEF                (0x00000000)
+
+#define DDRDATA7CH1_CR_DDRCRDATACONTROL0_REG                         (0x00000F74)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_OFF          ( 0)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_WID          ( 1)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_MSK          (0x00000001)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_MAX          (0x00000001)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_DEF          (0x00000000)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_OFF          ( 1)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_WID          ( 1)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_MSK          (0x00000002)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_MAX          (0x00000001)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_DEF          (0x00000000)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_OFF          ( 2)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_WID          ( 1)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_MSK          (0x00000004)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_MAX          (0x00000001)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_DEF          (0x00000000)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_OFF    ( 3)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_WID    ( 1)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MSK    (0x00000008)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MAX    (0x00000001)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_DEF    (0x00000000)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_TxOn_OFF                    ( 4)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_TxOn_WID                    ( 1)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_TxOn_MSK                    (0x00000010)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_TxOn_MAX                    (0x00000001)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_TxOn_DEF                    (0x00000000)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RfOn_OFF                    ( 5)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RfOn_WID                    ( 1)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RfOn_MSK                    (0x00000020)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RfOn_MAX                    (0x00000001)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RfOn_DEF                    (0x00000000)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RxPiOn_OFF                  ( 6)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RxPiOn_WID                  ( 1)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RxPiOn_MSK                  (0x00000040)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RxPiOn_MAX                  (0x00000001)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RxPiOn_DEF                  (0x00000000)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_TxPiOn_OFF                  ( 7)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_TxPiOn_WID                  ( 1)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_TxPiOn_MSK                  (0x00000080)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_TxPiOn_MAX                  (0x00000001)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_TxPiOn_DEF                  (0x00000000)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_OFF        ( 8)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_WID        ( 1)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_MSK        (0x00000100)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_MAX        (0x00000001)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_DEF        (0x00000000)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_OFF        ( 9)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_WID        ( 1)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MSK        (0x00000200)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MAX        (0x00000001)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_DEF        (0x00000000)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_TxDisable_OFF               (10)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_TxDisable_WID               ( 1)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_TxDisable_MSK               (0x00000400)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_TxDisable_MAX               (0x00000001)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_TxDisable_DEF               (0x00000000)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RxDisable_OFF               (11)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RxDisable_WID               ( 1)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RxDisable_MSK               (0x00000800)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RxDisable_MAX               (0x00000001)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RxDisable_DEF               (0x00000000)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_TxLong_OFF                  (12)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_TxLong_WID                  ( 1)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_TxLong_MSK                  (0x00001000)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_TxLong_MAX                  (0x00000001)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_TxLong_DEF                  (0x00000000)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_OFF               (13)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_WID               ( 2)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_MSK               (0x00006000)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_MAX               (0x00000003)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_DEF               (0x00000000)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RxReadPointer_OFF           (15)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RxReadPointer_WID           ( 3)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RxReadPointer_MSK           (0x00038000)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RxReadPointer_MAX           (0x00000007)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RxReadPointer_DEF           (0x00000000)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_DriverSegmentEnable_OFF     (18)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_DriverSegmentEnable_WID     ( 1)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_DriverSegmentEnable_MSK     (0x00040000)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_DriverSegmentEnable_MAX     (0x00000001)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_DriverSegmentEnable_DEF     (0x00000000)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_DataVccddqHi_OFF            (19)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_DataVccddqHi_WID            ( 1)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_DataVccddqHi_MSK            (0x00080000)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_DataVccddqHi_MAX            (0x00000001)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_DataVccddqHi_DEF            (0x00000000)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_ReadRFRd_OFF                (20)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_ReadRFRd_WID                ( 1)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_ReadRFRd_MSK                (0x00100000)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_ReadRFRd_MAX                (0x00000001)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_ReadRFRd_DEF                (0x00000000)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_ReadRFWr_OFF                (21)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_ReadRFWr_WID                ( 1)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_ReadRFWr_MSK                (0x00200000)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_ReadRFWr_MAX                (0x00000001)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_ReadRFWr_DEF                (0x00000000)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_ReadRFRank_OFF              (22)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_ReadRFRank_WID              ( 2)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_ReadRFRank_MSK              (0x00C00000)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_ReadRFRank_MAX              (0x00000003)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_ReadRFRank_DEF              (0x00000000)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_OFF              (24)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_WID              ( 1)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_MSK              (0x01000000)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_MAX              (0x00000001)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_DEF              (0x00000000)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_OdtSampOff_OFF              (25)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_OdtSampOff_WID              ( 1)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_OdtSampOff_MSK              (0x02000000)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_OdtSampOff_MAX              (0x00000001)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_OdtSampOff_DEF              (0x00000000)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_OFF        (26)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_WID        ( 1)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_MSK        (0x04000000)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_MAX        (0x00000001)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_DEF        (0x00000000)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_OFF         (27)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_WID         ( 1)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MSK         (0x08000000)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MAX         (0x00000001)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_DEF         (0x00000000)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_OFF              (28)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_WID              ( 1)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_MSK              (0x10000000)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_MAX              (0x00000001)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_DEF              (0x00000000)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_EnReadPreamble_OFF          (29)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_EnReadPreamble_WID          ( 1)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_EnReadPreamble_MSK          (0x20000000)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_EnReadPreamble_MAX          (0x00000001)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_EnReadPreamble_DEF          (0x00000000)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_OFF         (30)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_WID         ( 1)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MSK         (0x40000000)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MAX         (0x00000001)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_DEF         (0x00000000)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_OFF            (31)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_WID            ( 1)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_MSK            (0x80000000)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_MAX            (0x00000001)
+  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_DEF            (0x00000000)
+
+#define DDRDATA7CH1_CR_DDRCRVREFADJUST1_REG                          (0x00000F78)
+  #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_CAVrefCtl_OFF                ( 0)
+  #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_CAVrefCtl_WID                ( 7)
+  #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_CAVrefCtl_MSK                (0x0000007F)
+  #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_CAVrefCtl_MAX                (0x0000007F)
+  #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_CAVrefCtl_DEF                (0x00000000)
+  #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_Ch1VrefCtl_OFF               ( 7)
+  #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_Ch1VrefCtl_WID               ( 7)
+  #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_Ch1VrefCtl_MSK               (0x00003F80)
+  #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_Ch1VrefCtl_MAX               (0x0000007F)
+  #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_Ch1VrefCtl_DEF               (0x00000000)
+  #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_Ch0VrefCtl_OFF               (14)
+  #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_Ch0VrefCtl_WID               ( 7)
+  #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_Ch0VrefCtl_MSK               (0x001FC000)
+  #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_Ch0VrefCtl_MAX               (0x0000007F)
+  #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_Ch0VrefCtl_DEF               (0x00000000)
+  #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCA_OFF             (21)
+  #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCA_WID             ( 1)
+  #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCA_MSK             (0x00200000)
+  #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCA_MAX             (0x00000001)
+  #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCA_DEF             (0x00000000)
+  #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_OFF            (22)
+  #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_WID            ( 1)
+  #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_MSK            (0x00400000)
+  #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_MAX            (0x00000001)
+  #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_DEF            (0x00000000)
+  #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_OFF            (23)
+  #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_WID            ( 1)
+  #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_MSK            (0x00800000)
+  #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_MAX            (0x00000001)
+  #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_DEF            (0x00000000)
+  #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_HiZTimerCtrl_OFF             (24)
+  #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_HiZTimerCtrl_WID             ( 2)
+  #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_HiZTimerCtrl_MSK             (0x03000000)
+  #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_HiZTimerCtrl_MAX             (0x00000003)
+  #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_HiZTimerCtrl_DEF             (0x00000000)
+  #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_OFF            (26)
+  #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_WID            ( 1)
+  #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_MSK            (0x04000000)
+  #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_MAX            (0x00000001)
+  #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_DEF            (0x00000000)
+  #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_Rsvd_OFF                     (27)
+  #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_Rsvd_WID                     ( 2)
+  #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_Rsvd_MSK                     (0x18000000)
+  #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_Rsvd_MAX                     (0x00000003)
+  #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_Rsvd_DEF                     (0x00000000)
+  #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_caSlowBW_OFF                 (29)
+  #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_caSlowBW_WID                 ( 1)
+  #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_caSlowBW_MSK                 (0x20000000)
+  #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_caSlowBW_MAX                 (0x00000001)
+  #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_caSlowBW_DEF                 (0x00000000)
+  #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_ch0SlowBW_OFF                (30)
+  #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_ch0SlowBW_WID                ( 1)
+  #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_ch0SlowBW_MSK                (0x40000000)
+  #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_ch0SlowBW_MAX                (0x00000001)
+  #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_ch0SlowBW_DEF                (0x00000000)
+  #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_ch1SlowBW_OFF                (31)
+  #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_ch1SlowBW_WID                ( 1)
+  #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_ch1SlowBW_MSK                (0x80000000)
+  #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_ch1SlowBW_MAX                (0x00000001)
+  #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_ch1SlowBW_DEF                (0x00000000)
+
+#define DDRDATA8CH0_CR_RXTRAINRANK0_REG                              (0x00001000)
+  #define DDRDATA8CH0_CR_RXTRAINRANK0_RxRcvEnPi_OFF                    ( 0)
+  #define DDRDATA8CH0_CR_RXTRAINRANK0_RxRcvEnPi_WID                    ( 9)
+  #define DDRDATA8CH0_CR_RXTRAINRANK0_RxRcvEnPi_MSK                    (0x000001FF)
+  #define DDRDATA8CH0_CR_RXTRAINRANK0_RxRcvEnPi_MAX                    (0x000001FF)
+  #define DDRDATA8CH0_CR_RXTRAINRANK0_RxDqsPPi_OFF                     ( 9)
+  #define DDRDATA8CH0_CR_RXTRAINRANK0_RxDqsPPi_WID                     ( 6)
+  #define DDRDATA8CH0_CR_RXTRAINRANK0_RxDqsPPi_MSK                     (0x00007E00)
+  #define DDRDATA8CH0_CR_RXTRAINRANK0_RxDqsPPi_MAX                     (0x0000003F)
+  #define DDRDATA8CH0_CR_RXTRAINRANK0_RxEq_OFF                         (15)
+  #define DDRDATA8CH0_CR_RXTRAINRANK0_RxEq_WID                         ( 5)
+  #define DDRDATA8CH0_CR_RXTRAINRANK0_RxEq_MSK                         (0x000F8000)
+  #define DDRDATA8CH0_CR_RXTRAINRANK0_RxEq_MAX                         (0x0000001F)
+  #define DDRDATA8CH0_CR_RXTRAINRANK0_RxDqsNPi_OFF                     (20)
+  #define DDRDATA8CH0_CR_RXTRAINRANK0_RxDqsNPi_WID                     ( 6)
+  #define DDRDATA8CH0_CR_RXTRAINRANK0_RxDqsNPi_MSK                     (0x03F00000)
+  #define DDRDATA8CH0_CR_RXTRAINRANK0_RxDqsNPi_MAX                     (0x0000003F)
+  #define DDRDATA8CH0_CR_RXTRAINRANK0_RxVref_OFF                       (26)
+  #define DDRDATA8CH0_CR_RXTRAINRANK0_RxVref_WID                       ( 6)
+  #define DDRDATA8CH0_CR_RXTRAINRANK0_RxVref_MSK                       (0xFC000000)
+  #define DDRDATA8CH0_CR_RXTRAINRANK0_RxVref_MAX                       (0x0000003F)
+
+#define DDRDATA8CH0_CR_RXTRAINRANK1_REG                              (0x00001004)
+  #define DDRDATA8CH0_CR_RXTRAINRANK1_RxRcvEnPi_OFF                    ( 0)
+  #define DDRDATA8CH0_CR_RXTRAINRANK1_RxRcvEnPi_WID                    ( 9)
+  #define DDRDATA8CH0_CR_RXTRAINRANK1_RxRcvEnPi_MSK                    (0x000001FF)
+  #define DDRDATA8CH0_CR_RXTRAINRANK1_RxRcvEnPi_MAX                    (0x000001FF)
+  #define DDRDATA8CH0_CR_RXTRAINRANK1_RxDqsPPi_OFF                     ( 9)
+  #define DDRDATA8CH0_CR_RXTRAINRANK1_RxDqsPPi_WID                     ( 6)
+  #define DDRDATA8CH0_CR_RXTRAINRANK1_RxDqsPPi_MSK                     (0x00007E00)
+  #define DDRDATA8CH0_CR_RXTRAINRANK1_RxDqsPPi_MAX                     (0x0000003F)
+  #define DDRDATA8CH0_CR_RXTRAINRANK1_RxEq_OFF                         (15)
+  #define DDRDATA8CH0_CR_RXTRAINRANK1_RxEq_WID                         ( 5)
+  #define DDRDATA8CH0_CR_RXTRAINRANK1_RxEq_MSK                         (0x000F8000)
+  #define DDRDATA8CH0_CR_RXTRAINRANK1_RxEq_MAX                         (0x0000001F)
+  #define DDRDATA8CH0_CR_RXTRAINRANK1_RxDqsNPi_OFF                     (20)
+  #define DDRDATA8CH0_CR_RXTRAINRANK1_RxDqsNPi_WID                     ( 6)
+  #define DDRDATA8CH0_CR_RXTRAINRANK1_RxDqsNPi_MSK                     (0x03F00000)
+  #define DDRDATA8CH0_CR_RXTRAINRANK1_RxDqsNPi_MAX                     (0x0000003F)
+  #define DDRDATA8CH0_CR_RXTRAINRANK1_RxVref_OFF                       (26)
+  #define DDRDATA8CH0_CR_RXTRAINRANK1_RxVref_WID                       ( 6)
+  #define DDRDATA8CH0_CR_RXTRAINRANK1_RxVref_MSK                       (0xFC000000)
+  #define DDRDATA8CH0_CR_RXTRAINRANK1_RxVref_MAX                       (0x0000003F)
+
+#define DDRDATA8CH0_CR_RXTRAINRANK2_REG                              (0x00001008)
+  #define DDRDATA8CH0_CR_RXTRAINRANK2_RxRcvEnPi_OFF                    ( 0)
+  #define DDRDATA8CH0_CR_RXTRAINRANK2_RxRcvEnPi_WID                    ( 9)
+  #define DDRDATA8CH0_CR_RXTRAINRANK2_RxRcvEnPi_MSK                    (0x000001FF)
+  #define DDRDATA8CH0_CR_RXTRAINRANK2_RxRcvEnPi_MAX                    (0x000001FF)
+  #define DDRDATA8CH0_CR_RXTRAINRANK2_RxDqsPPi_OFF                     ( 9)
+  #define DDRDATA8CH0_CR_RXTRAINRANK2_RxDqsPPi_WID                     ( 6)
+  #define DDRDATA8CH0_CR_RXTRAINRANK2_RxDqsPPi_MSK                     (0x00007E00)
+  #define DDRDATA8CH0_CR_RXTRAINRANK2_RxDqsPPi_MAX                     (0x0000003F)
+  #define DDRDATA8CH0_CR_RXTRAINRANK2_RxEq_OFF                         (15)
+  #define DDRDATA8CH0_CR_RXTRAINRANK2_RxEq_WID                         ( 5)
+  #define DDRDATA8CH0_CR_RXTRAINRANK2_RxEq_MSK                         (0x000F8000)
+  #define DDRDATA8CH0_CR_RXTRAINRANK2_RxEq_MAX                         (0x0000001F)
+  #define DDRDATA8CH0_CR_RXTRAINRANK2_RxDqsNPi_OFF                     (20)
+  #define DDRDATA8CH0_CR_RXTRAINRANK2_RxDqsNPi_WID                     ( 6)
+  #define DDRDATA8CH0_CR_RXTRAINRANK2_RxDqsNPi_MSK                     (0x03F00000)
+  #define DDRDATA8CH0_CR_RXTRAINRANK2_RxDqsNPi_MAX                     (0x0000003F)
+  #define DDRDATA8CH0_CR_RXTRAINRANK2_RxVref_OFF                       (26)
+  #define DDRDATA8CH0_CR_RXTRAINRANK2_RxVref_WID                       ( 6)
+  #define DDRDATA8CH0_CR_RXTRAINRANK2_RxVref_MSK                       (0xFC000000)
+  #define DDRDATA8CH0_CR_RXTRAINRANK2_RxVref_MAX                       (0x0000003F)
+
+#define DDRDATA8CH0_CR_RXTRAINRANK3_REG                              (0x0000100C)
+  #define DDRDATA8CH0_CR_RXTRAINRANK3_RxRcvEnPi_OFF                    ( 0)
+  #define DDRDATA8CH0_CR_RXTRAINRANK3_RxRcvEnPi_WID                    ( 9)
+  #define DDRDATA8CH0_CR_RXTRAINRANK3_RxRcvEnPi_MSK                    (0x000001FF)
+  #define DDRDATA8CH0_CR_RXTRAINRANK3_RxRcvEnPi_MAX                    (0x000001FF)
+  #define DDRDATA8CH0_CR_RXTRAINRANK3_RxDqsPPi_OFF                     ( 9)
+  #define DDRDATA8CH0_CR_RXTRAINRANK3_RxDqsPPi_WID                     ( 6)
+  #define DDRDATA8CH0_CR_RXTRAINRANK3_RxDqsPPi_MSK                     (0x00007E00)
+  #define DDRDATA8CH0_CR_RXTRAINRANK3_RxDqsPPi_MAX                     (0x0000003F)
+  #define DDRDATA8CH0_CR_RXTRAINRANK3_RxEq_OFF                         (15)
+  #define DDRDATA8CH0_CR_RXTRAINRANK3_RxEq_WID                         ( 5)
+  #define DDRDATA8CH0_CR_RXTRAINRANK3_RxEq_MSK                         (0x000F8000)
+  #define DDRDATA8CH0_CR_RXTRAINRANK3_RxEq_MAX                         (0x0000001F)
+  #define DDRDATA8CH0_CR_RXTRAINRANK3_RxDqsNPi_OFF                     (20)
+  #define DDRDATA8CH0_CR_RXTRAINRANK3_RxDqsNPi_WID                     ( 6)
+  #define DDRDATA8CH0_CR_RXTRAINRANK3_RxDqsNPi_MSK                     (0x03F00000)
+  #define DDRDATA8CH0_CR_RXTRAINRANK3_RxDqsNPi_MAX                     (0x0000003F)
+  #define DDRDATA8CH0_CR_RXTRAINRANK3_RxVref_OFF                       (26)
+  #define DDRDATA8CH0_CR_RXTRAINRANK3_RxVref_WID                       ( 6)
+  #define DDRDATA8CH0_CR_RXTRAINRANK3_RxVref_MSK                       (0xFC000000)
+  #define DDRDATA8CH0_CR_RXTRAINRANK3_RxVref_MAX                       (0x0000003F)
+
+#define DDRDATA8CH0_CR_RXPERBITRANK0_REG                             (0x00001010)
+  #define DDRDATA8CH0_CR_RXPERBITRANK0_Lane0_OFF                       ( 0)
+  #define DDRDATA8CH0_CR_RXPERBITRANK0_Lane0_WID                       ( 4)
+  #define DDRDATA8CH0_CR_RXPERBITRANK0_Lane0_MSK                       (0x0000000F)
+  #define DDRDATA8CH0_CR_RXPERBITRANK0_Lane0_MAX                       (0x0000000F)
+  #define DDRDATA8CH0_CR_RXPERBITRANK0_Lane1_OFF                       ( 4)
+  #define DDRDATA8CH0_CR_RXPERBITRANK0_Lane1_WID                       ( 4)
+  #define DDRDATA8CH0_CR_RXPERBITRANK0_Lane1_MSK                       (0x000000F0)
+  #define DDRDATA8CH0_CR_RXPERBITRANK0_Lane1_MAX                       (0x0000000F)
+  #define DDRDATA8CH0_CR_RXPERBITRANK0_Lane2_OFF                       ( 8)
+  #define DDRDATA8CH0_CR_RXPERBITRANK0_Lane2_WID                       ( 4)
+  #define DDRDATA8CH0_CR_RXPERBITRANK0_Lane2_MSK                       (0x00000F00)
+  #define DDRDATA8CH0_CR_RXPERBITRANK0_Lane2_MAX                       (0x0000000F)
+  #define DDRDATA8CH0_CR_RXPERBITRANK0_Lane3_OFF                       (12)
+  #define DDRDATA8CH0_CR_RXPERBITRANK0_Lane3_WID                       ( 4)
+  #define DDRDATA8CH0_CR_RXPERBITRANK0_Lane3_MSK                       (0x0000F000)
+  #define DDRDATA8CH0_CR_RXPERBITRANK0_Lane3_MAX                       (0x0000000F)
+  #define DDRDATA8CH0_CR_RXPERBITRANK0_Lane4_OFF                       (16)
+  #define DDRDATA8CH0_CR_RXPERBITRANK0_Lane4_WID                       ( 4)
+  #define DDRDATA8CH0_CR_RXPERBITRANK0_Lane4_MSK                       (0x000F0000)
+  #define DDRDATA8CH0_CR_RXPERBITRANK0_Lane4_MAX                       (0x0000000F)
+  #define DDRDATA8CH0_CR_RXPERBITRANK0_Lane5_OFF                       (20)
+  #define DDRDATA8CH0_CR_RXPERBITRANK0_Lane5_WID                       ( 4)
+  #define DDRDATA8CH0_CR_RXPERBITRANK0_Lane5_MSK                       (0x00F00000)
+  #define DDRDATA8CH0_CR_RXPERBITRANK0_Lane5_MAX                       (0x0000000F)
+  #define DDRDATA8CH0_CR_RXPERBITRANK0_Lane6_OFF                       (24)
+  #define DDRDATA8CH0_CR_RXPERBITRANK0_Lane6_WID                       ( 4)
+  #define DDRDATA8CH0_CR_RXPERBITRANK0_Lane6_MSK                       (0x0F000000)
+  #define DDRDATA8CH0_CR_RXPERBITRANK0_Lane6_MAX                       (0x0000000F)
+  #define DDRDATA8CH0_CR_RXPERBITRANK0_Lane7_OFF                       (28)
+  #define DDRDATA8CH0_CR_RXPERBITRANK0_Lane7_WID                       ( 4)
+  #define DDRDATA8CH0_CR_RXPERBITRANK0_Lane7_MSK                       (0xF0000000)
+  #define DDRDATA8CH0_CR_RXPERBITRANK0_Lane7_MAX                       (0x0000000F)
+
+#define DDRDATA8CH0_CR_RXPERBITRANK1_REG                             (0x00001014)
+  #define DDRDATA8CH0_CR_RXPERBITRANK1_Lane0_OFF                       ( 0)
+  #define DDRDATA8CH0_CR_RXPERBITRANK1_Lane0_WID                       ( 4)
+  #define DDRDATA8CH0_CR_RXPERBITRANK1_Lane0_MSK                       (0x0000000F)
+  #define DDRDATA8CH0_CR_RXPERBITRANK1_Lane0_MAX                       (0x0000000F)
+  #define DDRDATA8CH0_CR_RXPERBITRANK1_Lane1_OFF                       ( 4)
+  #define DDRDATA8CH0_CR_RXPERBITRANK1_Lane1_WID                       ( 4)
+  #define DDRDATA8CH0_CR_RXPERBITRANK1_Lane1_MSK                       (0x000000F0)
+  #define DDRDATA8CH0_CR_RXPERBITRANK1_Lane1_MAX                       (0x0000000F)
+  #define DDRDATA8CH0_CR_RXPERBITRANK1_Lane2_OFF                       ( 8)
+  #define DDRDATA8CH0_CR_RXPERBITRANK1_Lane2_WID                       ( 4)
+  #define DDRDATA8CH0_CR_RXPERBITRANK1_Lane2_MSK                       (0x00000F00)
+  #define DDRDATA8CH0_CR_RXPERBITRANK1_Lane2_MAX                       (0x0000000F)
+  #define DDRDATA8CH0_CR_RXPERBITRANK1_Lane3_OFF                       (12)
+  #define DDRDATA8CH0_CR_RXPERBITRANK1_Lane3_WID                       ( 4)
+  #define DDRDATA8CH0_CR_RXPERBITRANK1_Lane3_MSK                       (0x0000F000)
+  #define DDRDATA8CH0_CR_RXPERBITRANK1_Lane3_MAX                       (0x0000000F)
+  #define DDRDATA8CH0_CR_RXPERBITRANK1_Lane4_OFF                       (16)
+  #define DDRDATA8CH0_CR_RXPERBITRANK1_Lane4_WID                       ( 4)
+  #define DDRDATA8CH0_CR_RXPERBITRANK1_Lane4_MSK                       (0x000F0000)
+  #define DDRDATA8CH0_CR_RXPERBITRANK1_Lane4_MAX                       (0x0000000F)
+  #define DDRDATA8CH0_CR_RXPERBITRANK1_Lane5_OFF                       (20)
+  #define DDRDATA8CH0_CR_RXPERBITRANK1_Lane5_WID                       ( 4)
+  #define DDRDATA8CH0_CR_RXPERBITRANK1_Lane5_MSK                       (0x00F00000)
+  #define DDRDATA8CH0_CR_RXPERBITRANK1_Lane5_MAX                       (0x0000000F)
+  #define DDRDATA8CH0_CR_RXPERBITRANK1_Lane6_OFF                       (24)
+  #define DDRDATA8CH0_CR_RXPERBITRANK1_Lane6_WID                       ( 4)
+  #define DDRDATA8CH0_CR_RXPERBITRANK1_Lane6_MSK                       (0x0F000000)
+  #define DDRDATA8CH0_CR_RXPERBITRANK1_Lane6_MAX                       (0x0000000F)
+  #define DDRDATA8CH0_CR_RXPERBITRANK1_Lane7_OFF                       (28)
+  #define DDRDATA8CH0_CR_RXPERBITRANK1_Lane7_WID                       ( 4)
+  #define DDRDATA8CH0_CR_RXPERBITRANK1_Lane7_MSK                       (0xF0000000)
+  #define DDRDATA8CH0_CR_RXPERBITRANK1_Lane7_MAX                       (0x0000000F)
+
+#define DDRDATA8CH0_CR_RXPERBITRANK2_REG                             (0x00001018)
+  #define DDRDATA8CH0_CR_RXPERBITRANK2_Lane0_OFF                       ( 0)
+  #define DDRDATA8CH0_CR_RXPERBITRANK2_Lane0_WID                       ( 4)
+  #define DDRDATA8CH0_CR_RXPERBITRANK2_Lane0_MSK                       (0x0000000F)
+  #define DDRDATA8CH0_CR_RXPERBITRANK2_Lane0_MAX                       (0x0000000F)
+  #define DDRDATA8CH0_CR_RXPERBITRANK2_Lane1_OFF                       ( 4)
+  #define DDRDATA8CH0_CR_RXPERBITRANK2_Lane1_WID                       ( 4)
+  #define DDRDATA8CH0_CR_RXPERBITRANK2_Lane1_MSK                       (0x000000F0)
+  #define DDRDATA8CH0_CR_RXPERBITRANK2_Lane1_MAX                       (0x0000000F)
+  #define DDRDATA8CH0_CR_RXPERBITRANK2_Lane2_OFF                       ( 8)
+  #define DDRDATA8CH0_CR_RXPERBITRANK2_Lane2_WID                       ( 4)
+  #define DDRDATA8CH0_CR_RXPERBITRANK2_Lane2_MSK                       (0x00000F00)
+  #define DDRDATA8CH0_CR_RXPERBITRANK2_Lane2_MAX                       (0x0000000F)
+  #define DDRDATA8CH0_CR_RXPERBITRANK2_Lane3_OFF                       (12)
+  #define DDRDATA8CH0_CR_RXPERBITRANK2_Lane3_WID                       ( 4)
+  #define DDRDATA8CH0_CR_RXPERBITRANK2_Lane3_MSK                       (0x0000F000)
+  #define DDRDATA8CH0_CR_RXPERBITRANK2_Lane3_MAX                       (0x0000000F)
+  #define DDRDATA8CH0_CR_RXPERBITRANK2_Lane4_OFF                       (16)
+  #define DDRDATA8CH0_CR_RXPERBITRANK2_Lane4_WID                       ( 4)
+  #define DDRDATA8CH0_CR_RXPERBITRANK2_Lane4_MSK                       (0x000F0000)
+  #define DDRDATA8CH0_CR_RXPERBITRANK2_Lane4_MAX                       (0x0000000F)
+  #define DDRDATA8CH0_CR_RXPERBITRANK2_Lane5_OFF                       (20)
+  #define DDRDATA8CH0_CR_RXPERBITRANK2_Lane5_WID                       ( 4)
+  #define DDRDATA8CH0_CR_RXPERBITRANK2_Lane5_MSK                       (0x00F00000)
+  #define DDRDATA8CH0_CR_RXPERBITRANK2_Lane5_MAX                       (0x0000000F)
+  #define DDRDATA8CH0_CR_RXPERBITRANK2_Lane6_OFF                       (24)
+  #define DDRDATA8CH0_CR_RXPERBITRANK2_Lane6_WID                       ( 4)
+  #define DDRDATA8CH0_CR_RXPERBITRANK2_Lane6_MSK                       (0x0F000000)
+  #define DDRDATA8CH0_CR_RXPERBITRANK2_Lane6_MAX                       (0x0000000F)
+  #define DDRDATA8CH0_CR_RXPERBITRANK2_Lane7_OFF                       (28)
+  #define DDRDATA8CH0_CR_RXPERBITRANK2_Lane7_WID                       ( 4)
+  #define DDRDATA8CH0_CR_RXPERBITRANK2_Lane7_MSK                       (0xF0000000)
+  #define DDRDATA8CH0_CR_RXPERBITRANK2_Lane7_MAX                       (0x0000000F)
+
+#define DDRDATA8CH0_CR_RXPERBITRANK3_REG                             (0x0000101C)
+  #define DDRDATA8CH0_CR_RXPERBITRANK3_Lane0_OFF                       ( 0)
+  #define DDRDATA8CH0_CR_RXPERBITRANK3_Lane0_WID                       ( 4)
+  #define DDRDATA8CH0_CR_RXPERBITRANK3_Lane0_MSK                       (0x0000000F)
+  #define DDRDATA8CH0_CR_RXPERBITRANK3_Lane0_MAX                       (0x0000000F)
+  #define DDRDATA8CH0_CR_RXPERBITRANK3_Lane1_OFF                       ( 4)
+  #define DDRDATA8CH0_CR_RXPERBITRANK3_Lane1_WID                       ( 4)
+  #define DDRDATA8CH0_CR_RXPERBITRANK3_Lane1_MSK                       (0x000000F0)
+  #define DDRDATA8CH0_CR_RXPERBITRANK3_Lane1_MAX                       (0x0000000F)
+  #define DDRDATA8CH0_CR_RXPERBITRANK3_Lane2_OFF                       ( 8)
+  #define DDRDATA8CH0_CR_RXPERBITRANK3_Lane2_WID                       ( 4)
+  #define DDRDATA8CH0_CR_RXPERBITRANK3_Lane2_MSK                       (0x00000F00)
+  #define DDRDATA8CH0_CR_RXPERBITRANK3_Lane2_MAX                       (0x0000000F)
+  #define DDRDATA8CH0_CR_RXPERBITRANK3_Lane3_OFF                       (12)
+  #define DDRDATA8CH0_CR_RXPERBITRANK3_Lane3_WID                       ( 4)
+  #define DDRDATA8CH0_CR_RXPERBITRANK3_Lane3_MSK                       (0x0000F000)
+  #define DDRDATA8CH0_CR_RXPERBITRANK3_Lane3_MAX                       (0x0000000F)
+  #define DDRDATA8CH0_CR_RXPERBITRANK3_Lane4_OFF                       (16)
+  #define DDRDATA8CH0_CR_RXPERBITRANK3_Lane4_WID                       ( 4)
+  #define DDRDATA8CH0_CR_RXPERBITRANK3_Lane4_MSK                       (0x000F0000)
+  #define DDRDATA8CH0_CR_RXPERBITRANK3_Lane4_MAX                       (0x0000000F)
+  #define DDRDATA8CH0_CR_RXPERBITRANK3_Lane5_OFF                       (20)
+  #define DDRDATA8CH0_CR_RXPERBITRANK3_Lane5_WID                       ( 4)
+  #define DDRDATA8CH0_CR_RXPERBITRANK3_Lane5_MSK                       (0x00F00000)
+  #define DDRDATA8CH0_CR_RXPERBITRANK3_Lane5_MAX                       (0x0000000F)
+  #define DDRDATA8CH0_CR_RXPERBITRANK3_Lane6_OFF                       (24)
+  #define DDRDATA8CH0_CR_RXPERBITRANK3_Lane6_WID                       ( 4)
+  #define DDRDATA8CH0_CR_RXPERBITRANK3_Lane6_MSK                       (0x0F000000)
+  #define DDRDATA8CH0_CR_RXPERBITRANK3_Lane6_MAX                       (0x0000000F)
+  #define DDRDATA8CH0_CR_RXPERBITRANK3_Lane7_OFF                       (28)
+  #define DDRDATA8CH0_CR_RXPERBITRANK3_Lane7_WID                       ( 4)
+  #define DDRDATA8CH0_CR_RXPERBITRANK3_Lane7_MSK                       (0xF0000000)
+  #define DDRDATA8CH0_CR_RXPERBITRANK3_Lane7_MAX                       (0x0000000F)
+
+#define DDRDATA8CH0_CR_TXTRAINRANK0_REG                              (0x00001020)
+  #define DDRDATA8CH0_CR_TXTRAINRANK0_TxDqDelay_OFF                    ( 0)
+  #define DDRDATA8CH0_CR_TXTRAINRANK0_TxDqDelay_WID                    ( 9)
+  #define DDRDATA8CH0_CR_TXTRAINRANK0_TxDqDelay_MSK                    (0x000001FF)
+  #define DDRDATA8CH0_CR_TXTRAINRANK0_TxDqDelay_MAX                    (0x000001FF)
+  #define DDRDATA8CH0_CR_TXTRAINRANK0_TxDqsDelay_OFF                   ( 9)
+  #define DDRDATA8CH0_CR_TXTRAINRANK0_TxDqsDelay_WID                   ( 9)
+  #define DDRDATA8CH0_CR_TXTRAINRANK0_TxDqsDelay_MSK                   (0x0003FE00)
+  #define DDRDATA8CH0_CR_TXTRAINRANK0_TxDqsDelay_MAX                   (0x000001FF)
+  #define DDRDATA8CH0_CR_TXTRAINRANK0_Spare0_OFF                       (18)
+  #define DDRDATA8CH0_CR_TXTRAINRANK0_Spare0_WID                       ( 2)
+  #define DDRDATA8CH0_CR_TXTRAINRANK0_Spare0_MSK                       (0x000C0000)
+  #define DDRDATA8CH0_CR_TXTRAINRANK0_Spare0_MAX                       (0x00000003)
+  #define DDRDATA8CH0_CR_TXTRAINRANK0_TxEqualization_OFF               (20)
+  #define DDRDATA8CH0_CR_TXTRAINRANK0_TxEqualization_WID               ( 6)
+  #define DDRDATA8CH0_CR_TXTRAINRANK0_TxEqualization_MSK               (0x03F00000)
+  #define DDRDATA8CH0_CR_TXTRAINRANK0_TxEqualization_MAX               (0x0000003F)
+  #define DDRDATA8CH0_CR_TXTRAINRANK0_Spare1_OFF                       (26)
+  #define DDRDATA8CH0_CR_TXTRAINRANK0_Spare1_WID                       ( 6)
+  #define DDRDATA8CH0_CR_TXTRAINRANK0_Spare1_MSK                       (0xFC000000)
+  #define DDRDATA8CH0_CR_TXTRAINRANK0_Spare1_MAX                       (0x0000003F)
+
+#define DDRDATA8CH0_CR_TXTRAINRANK1_REG                              (0x00001024)
+  #define DDRDATA8CH0_CR_TXTRAINRANK1_TxDqDelay_OFF                    ( 0)
+  #define DDRDATA8CH0_CR_TXTRAINRANK1_TxDqDelay_WID                    ( 9)
+  #define DDRDATA8CH0_CR_TXTRAINRANK1_TxDqDelay_MSK                    (0x000001FF)
+  #define DDRDATA8CH0_CR_TXTRAINRANK1_TxDqDelay_MAX                    (0x000001FF)
+  #define DDRDATA8CH0_CR_TXTRAINRANK1_TxDqsDelay_OFF                   ( 9)
+  #define DDRDATA8CH0_CR_TXTRAINRANK1_TxDqsDelay_WID                   ( 9)
+  #define DDRDATA8CH0_CR_TXTRAINRANK1_TxDqsDelay_MSK                   (0x0003FE00)
+  #define DDRDATA8CH0_CR_TXTRAINRANK1_TxDqsDelay_MAX                   (0x000001FF)
+  #define DDRDATA8CH0_CR_TXTRAINRANK1_Spare0_OFF                       (18)
+  #define DDRDATA8CH0_CR_TXTRAINRANK1_Spare0_WID                       ( 2)
+  #define DDRDATA8CH0_CR_TXTRAINRANK1_Spare0_MSK                       (0x000C0000)
+  #define DDRDATA8CH0_CR_TXTRAINRANK1_Spare0_MAX                       (0x00000003)
+  #define DDRDATA8CH0_CR_TXTRAINRANK1_TxEqualization_OFF               (20)
+  #define DDRDATA8CH0_CR_TXTRAINRANK1_TxEqualization_WID               ( 6)
+  #define DDRDATA8CH0_CR_TXTRAINRANK1_TxEqualization_MSK               (0x03F00000)
+  #define DDRDATA8CH0_CR_TXTRAINRANK1_TxEqualization_MAX               (0x0000003F)
+  #define DDRDATA8CH0_CR_TXTRAINRANK1_Spare1_OFF                       (26)
+  #define DDRDATA8CH0_CR_TXTRAINRANK1_Spare1_WID                       ( 6)
+  #define DDRDATA8CH0_CR_TXTRAINRANK1_Spare1_MSK                       (0xFC000000)
+  #define DDRDATA8CH0_CR_TXTRAINRANK1_Spare1_MAX                       (0x0000003F)
+
+#define DDRDATA8CH0_CR_TXTRAINRANK2_REG                              (0x00001028)
+  #define DDRDATA8CH0_CR_TXTRAINRANK2_TxDqDelay_OFF                    ( 0)
+  #define DDRDATA8CH0_CR_TXTRAINRANK2_TxDqDelay_WID                    ( 9)
+  #define DDRDATA8CH0_CR_TXTRAINRANK2_TxDqDelay_MSK                    (0x000001FF)
+  #define DDRDATA8CH0_CR_TXTRAINRANK2_TxDqDelay_MAX                    (0x000001FF)
+  #define DDRDATA8CH0_CR_TXTRAINRANK2_TxDqsDelay_OFF                   ( 9)
+  #define DDRDATA8CH0_CR_TXTRAINRANK2_TxDqsDelay_WID                   ( 9)
+  #define DDRDATA8CH0_CR_TXTRAINRANK2_TxDqsDelay_MSK                   (0x0003FE00)
+  #define DDRDATA8CH0_CR_TXTRAINRANK2_TxDqsDelay_MAX                   (0x000001FF)
+  #define DDRDATA8CH0_CR_TXTRAINRANK2_Spare0_OFF                       (18)
+  #define DDRDATA8CH0_CR_TXTRAINRANK2_Spare0_WID                       ( 2)
+  #define DDRDATA8CH0_CR_TXTRAINRANK2_Spare0_MSK                       (0x000C0000)
+  #define DDRDATA8CH0_CR_TXTRAINRANK2_Spare0_MAX                       (0x00000003)
+  #define DDRDATA8CH0_CR_TXTRAINRANK2_TxEqualization_OFF               (20)
+  #define DDRDATA8CH0_CR_TXTRAINRANK2_TxEqualization_WID               ( 6)
+  #define DDRDATA8CH0_CR_TXTRAINRANK2_TxEqualization_MSK               (0x03F00000)
+  #define DDRDATA8CH0_CR_TXTRAINRANK2_TxEqualization_MAX               (0x0000003F)
+  #define DDRDATA8CH0_CR_TXTRAINRANK2_Spare1_OFF                       (26)
+  #define DDRDATA8CH0_CR_TXTRAINRANK2_Spare1_WID                       ( 6)
+  #define DDRDATA8CH0_CR_TXTRAINRANK2_Spare1_MSK                       (0xFC000000)
+  #define DDRDATA8CH0_CR_TXTRAINRANK2_Spare1_MAX                       (0x0000003F)
+
+#define DDRDATA8CH0_CR_TXTRAINRANK3_REG                              (0x0000102C)
+  #define DDRDATA8CH0_CR_TXTRAINRANK3_TxDqDelay_OFF                    ( 0)
+  #define DDRDATA8CH0_CR_TXTRAINRANK3_TxDqDelay_WID                    ( 9)
+  #define DDRDATA8CH0_CR_TXTRAINRANK3_TxDqDelay_MSK                    (0x000001FF)
+  #define DDRDATA8CH0_CR_TXTRAINRANK3_TxDqDelay_MAX                    (0x000001FF)
+  #define DDRDATA8CH0_CR_TXTRAINRANK3_TxDqsDelay_OFF                   ( 9)
+  #define DDRDATA8CH0_CR_TXTRAINRANK3_TxDqsDelay_WID                   ( 9)
+  #define DDRDATA8CH0_CR_TXTRAINRANK3_TxDqsDelay_MSK                   (0x0003FE00)
+  #define DDRDATA8CH0_CR_TXTRAINRANK3_TxDqsDelay_MAX                   (0x000001FF)
+  #define DDRDATA8CH0_CR_TXTRAINRANK3_Spare0_OFF                       (18)
+  #define DDRDATA8CH0_CR_TXTRAINRANK3_Spare0_WID                       ( 2)
+  #define DDRDATA8CH0_CR_TXTRAINRANK3_Spare0_MSK                       (0x000C0000)
+  #define DDRDATA8CH0_CR_TXTRAINRANK3_Spare0_MAX                       (0x00000003)
+  #define DDRDATA8CH0_CR_TXTRAINRANK3_TxEqualization_OFF               (20)
+  #define DDRDATA8CH0_CR_TXTRAINRANK3_TxEqualization_WID               ( 6)
+  #define DDRDATA8CH0_CR_TXTRAINRANK3_TxEqualization_MSK               (0x03F00000)
+  #define DDRDATA8CH0_CR_TXTRAINRANK3_TxEqualization_MAX               (0x0000003F)
+  #define DDRDATA8CH0_CR_TXTRAINRANK3_Spare1_OFF                       (26)
+  #define DDRDATA8CH0_CR_TXTRAINRANK3_Spare1_WID                       ( 6)
+  #define DDRDATA8CH0_CR_TXTRAINRANK3_Spare1_MSK                       (0xFC000000)
+  #define DDRDATA8CH0_CR_TXTRAINRANK3_Spare1_MAX                       (0x0000003F)
+
+#define DDRDATA8CH0_CR_TXPERBITRANK0_REG                             (0x00001030)
+  #define DDRDATA8CH0_CR_TXPERBITRANK0_Lane0_OFF                       ( 0)
+  #define DDRDATA8CH0_CR_TXPERBITRANK0_Lane0_WID                       ( 4)
+  #define DDRDATA8CH0_CR_TXPERBITRANK0_Lane0_MSK                       (0x0000000F)
+  #define DDRDATA8CH0_CR_TXPERBITRANK0_Lane0_MAX                       (0x0000000F)
+  #define DDRDATA8CH0_CR_TXPERBITRANK0_Lane1_OFF                       ( 4)
+  #define DDRDATA8CH0_CR_TXPERBITRANK0_Lane1_WID                       ( 4)
+  #define DDRDATA8CH0_CR_TXPERBITRANK0_Lane1_MSK                       (0x000000F0)
+  #define DDRDATA8CH0_CR_TXPERBITRANK0_Lane1_MAX                       (0x0000000F)
+  #define DDRDATA8CH0_CR_TXPERBITRANK0_Lane2_OFF                       ( 8)
+  #define DDRDATA8CH0_CR_TXPERBITRANK0_Lane2_WID                       ( 4)
+  #define DDRDATA8CH0_CR_TXPERBITRANK0_Lane2_MSK                       (0x00000F00)
+  #define DDRDATA8CH0_CR_TXPERBITRANK0_Lane2_MAX                       (0x0000000F)
+  #define DDRDATA8CH0_CR_TXPERBITRANK0_Lane3_OFF                       (12)
+  #define DDRDATA8CH0_CR_TXPERBITRANK0_Lane3_WID                       ( 4)
+  #define DDRDATA8CH0_CR_TXPERBITRANK0_Lane3_MSK                       (0x0000F000)
+  #define DDRDATA8CH0_CR_TXPERBITRANK0_Lane3_MAX                       (0x0000000F)
+  #define DDRDATA8CH0_CR_TXPERBITRANK0_Lane4_OFF                       (16)
+  #define DDRDATA8CH0_CR_TXPERBITRANK0_Lane4_WID                       ( 4)
+  #define DDRDATA8CH0_CR_TXPERBITRANK0_Lane4_MSK                       (0x000F0000)
+  #define DDRDATA8CH0_CR_TXPERBITRANK0_Lane4_MAX                       (0x0000000F)
+  #define DDRDATA8CH0_CR_TXPERBITRANK0_Lane5_OFF                       (20)
+  #define DDRDATA8CH0_CR_TXPERBITRANK0_Lane5_WID                       ( 4)
+  #define DDRDATA8CH0_CR_TXPERBITRANK0_Lane5_MSK                       (0x00F00000)
+  #define DDRDATA8CH0_CR_TXPERBITRANK0_Lane5_MAX                       (0x0000000F)
+  #define DDRDATA8CH0_CR_TXPERBITRANK0_Lane6_OFF                       (24)
+  #define DDRDATA8CH0_CR_TXPERBITRANK0_Lane6_WID                       ( 4)
+  #define DDRDATA8CH0_CR_TXPERBITRANK0_Lane6_MSK                       (0x0F000000)
+  #define DDRDATA8CH0_CR_TXPERBITRANK0_Lane6_MAX                       (0x0000000F)
+  #define DDRDATA8CH0_CR_TXPERBITRANK0_Lane7_OFF                       (28)
+  #define DDRDATA8CH0_CR_TXPERBITRANK0_Lane7_WID                       ( 4)
+  #define DDRDATA8CH0_CR_TXPERBITRANK0_Lane7_MSK                       (0xF0000000)
+  #define DDRDATA8CH0_CR_TXPERBITRANK0_Lane7_MAX                       (0x0000000F)
+
+#define DDRDATA8CH0_CR_TXPERBITRANK1_REG                             (0x00001034)
+  #define DDRDATA8CH0_CR_TXPERBITRANK1_Lane0_OFF                       ( 0)
+  #define DDRDATA8CH0_CR_TXPERBITRANK1_Lane0_WID                       ( 4)
+  #define DDRDATA8CH0_CR_TXPERBITRANK1_Lane0_MSK                       (0x0000000F)
+  #define DDRDATA8CH0_CR_TXPERBITRANK1_Lane0_MAX                       (0x0000000F)
+  #define DDRDATA8CH0_CR_TXPERBITRANK1_Lane1_OFF                       ( 4)
+  #define DDRDATA8CH0_CR_TXPERBITRANK1_Lane1_WID                       ( 4)
+  #define DDRDATA8CH0_CR_TXPERBITRANK1_Lane1_MSK                       (0x000000F0)
+  #define DDRDATA8CH0_CR_TXPERBITRANK1_Lane1_MAX                       (0x0000000F)
+  #define DDRDATA8CH0_CR_TXPERBITRANK1_Lane2_OFF                       ( 8)
+  #define DDRDATA8CH0_CR_TXPERBITRANK1_Lane2_WID                       ( 4)
+  #define DDRDATA8CH0_CR_TXPERBITRANK1_Lane2_MSK                       (0x00000F00)
+  #define DDRDATA8CH0_CR_TXPERBITRANK1_Lane2_MAX                       (0x0000000F)
+  #define DDRDATA8CH0_CR_TXPERBITRANK1_Lane3_OFF                       (12)
+  #define DDRDATA8CH0_CR_TXPERBITRANK1_Lane3_WID                       ( 4)
+  #define DDRDATA8CH0_CR_TXPERBITRANK1_Lane3_MSK                       (0x0000F000)
+  #define DDRDATA8CH0_CR_TXPERBITRANK1_Lane3_MAX                       (0x0000000F)
+  #define DDRDATA8CH0_CR_TXPERBITRANK1_Lane4_OFF                       (16)
+  #define DDRDATA8CH0_CR_TXPERBITRANK1_Lane4_WID                       ( 4)
+  #define DDRDATA8CH0_CR_TXPERBITRANK1_Lane4_MSK                       (0x000F0000)
+  #define DDRDATA8CH0_CR_TXPERBITRANK1_Lane4_MAX                       (0x0000000F)
+  #define DDRDATA8CH0_CR_TXPERBITRANK1_Lane5_OFF                       (20)
+  #define DDRDATA8CH0_CR_TXPERBITRANK1_Lane5_WID                       ( 4)
+  #define DDRDATA8CH0_CR_TXPERBITRANK1_Lane5_MSK                       (0x00F00000)
+  #define DDRDATA8CH0_CR_TXPERBITRANK1_Lane5_MAX                       (0x0000000F)
+  #define DDRDATA8CH0_CR_TXPERBITRANK1_Lane6_OFF                       (24)
+  #define DDRDATA8CH0_CR_TXPERBITRANK1_Lane6_WID                       ( 4)
+  #define DDRDATA8CH0_CR_TXPERBITRANK1_Lane6_MSK                       (0x0F000000)
+  #define DDRDATA8CH0_CR_TXPERBITRANK1_Lane6_MAX                       (0x0000000F)
+  #define DDRDATA8CH0_CR_TXPERBITRANK1_Lane7_OFF                       (28)
+  #define DDRDATA8CH0_CR_TXPERBITRANK1_Lane7_WID                       ( 4)
+  #define DDRDATA8CH0_CR_TXPERBITRANK1_Lane7_MSK                       (0xF0000000)
+  #define DDRDATA8CH0_CR_TXPERBITRANK1_Lane7_MAX                       (0x0000000F)
+
+#define DDRDATA8CH0_CR_TXPERBITRANK2_REG                             (0x00001038)
+  #define DDRDATA8CH0_CR_TXPERBITRANK2_Lane0_OFF                       ( 0)
+  #define DDRDATA8CH0_CR_TXPERBITRANK2_Lane0_WID                       ( 4)
+  #define DDRDATA8CH0_CR_TXPERBITRANK2_Lane0_MSK                       (0x0000000F)
+  #define DDRDATA8CH0_CR_TXPERBITRANK2_Lane0_MAX                       (0x0000000F)
+  #define DDRDATA8CH0_CR_TXPERBITRANK2_Lane1_OFF                       ( 4)
+  #define DDRDATA8CH0_CR_TXPERBITRANK2_Lane1_WID                       ( 4)
+  #define DDRDATA8CH0_CR_TXPERBITRANK2_Lane1_MSK                       (0x000000F0)
+  #define DDRDATA8CH0_CR_TXPERBITRANK2_Lane1_MAX                       (0x0000000F)
+  #define DDRDATA8CH0_CR_TXPERBITRANK2_Lane2_OFF                       ( 8)
+  #define DDRDATA8CH0_CR_TXPERBITRANK2_Lane2_WID                       ( 4)
+  #define DDRDATA8CH0_CR_TXPERBITRANK2_Lane2_MSK                       (0x00000F00)
+  #define DDRDATA8CH0_CR_TXPERBITRANK2_Lane2_MAX                       (0x0000000F)
+  #define DDRDATA8CH0_CR_TXPERBITRANK2_Lane3_OFF                       (12)
+  #define DDRDATA8CH0_CR_TXPERBITRANK2_Lane3_WID                       ( 4)
+  #define DDRDATA8CH0_CR_TXPERBITRANK2_Lane3_MSK                       (0x0000F000)
+  #define DDRDATA8CH0_CR_TXPERBITRANK2_Lane3_MAX                       (0x0000000F)
+  #define DDRDATA8CH0_CR_TXPERBITRANK2_Lane4_OFF                       (16)
+  #define DDRDATA8CH0_CR_TXPERBITRANK2_Lane4_WID                       ( 4)
+  #define DDRDATA8CH0_CR_TXPERBITRANK2_Lane4_MSK                       (0x000F0000)
+  #define DDRDATA8CH0_CR_TXPERBITRANK2_Lane4_MAX                       (0x0000000F)
+  #define DDRDATA8CH0_CR_TXPERBITRANK2_Lane5_OFF                       (20)
+  #define DDRDATA8CH0_CR_TXPERBITRANK2_Lane5_WID                       ( 4)
+  #define DDRDATA8CH0_CR_TXPERBITRANK2_Lane5_MSK                       (0x00F00000)
+  #define DDRDATA8CH0_CR_TXPERBITRANK2_Lane5_MAX                       (0x0000000F)
+  #define DDRDATA8CH0_CR_TXPERBITRANK2_Lane6_OFF                       (24)
+  #define DDRDATA8CH0_CR_TXPERBITRANK2_Lane6_WID                       ( 4)
+  #define DDRDATA8CH0_CR_TXPERBITRANK2_Lane6_MSK                       (0x0F000000)
+  #define DDRDATA8CH0_CR_TXPERBITRANK2_Lane6_MAX                       (0x0000000F)
+  #define DDRDATA8CH0_CR_TXPERBITRANK2_Lane7_OFF                       (28)
+  #define DDRDATA8CH0_CR_TXPERBITRANK2_Lane7_WID                       ( 4)
+  #define DDRDATA8CH0_CR_TXPERBITRANK2_Lane7_MSK                       (0xF0000000)
+  #define DDRDATA8CH0_CR_TXPERBITRANK2_Lane7_MAX                       (0x0000000F)
+
+#define DDRDATA8CH0_CR_TXPERBITRANK3_REG                             (0x0000103C)
+  #define DDRDATA8CH0_CR_TXPERBITRANK3_Lane0_OFF                       ( 0)
+  #define DDRDATA8CH0_CR_TXPERBITRANK3_Lane0_WID                       ( 4)
+  #define DDRDATA8CH0_CR_TXPERBITRANK3_Lane0_MSK                       (0x0000000F)
+  #define DDRDATA8CH0_CR_TXPERBITRANK3_Lane0_MAX                       (0x0000000F)
+  #define DDRDATA8CH0_CR_TXPERBITRANK3_Lane1_OFF                       ( 4)
+  #define DDRDATA8CH0_CR_TXPERBITRANK3_Lane1_WID                       ( 4)
+  #define DDRDATA8CH0_CR_TXPERBITRANK3_Lane1_MSK                       (0x000000F0)
+  #define DDRDATA8CH0_CR_TXPERBITRANK3_Lane1_MAX                       (0x0000000F)
+  #define DDRDATA8CH0_CR_TXPERBITRANK3_Lane2_OFF                       ( 8)
+  #define DDRDATA8CH0_CR_TXPERBITRANK3_Lane2_WID                       ( 4)
+  #define DDRDATA8CH0_CR_TXPERBITRANK3_Lane2_MSK                       (0x00000F00)
+  #define DDRDATA8CH0_CR_TXPERBITRANK3_Lane2_MAX                       (0x0000000F)
+  #define DDRDATA8CH0_CR_TXPERBITRANK3_Lane3_OFF                       (12)
+  #define DDRDATA8CH0_CR_TXPERBITRANK3_Lane3_WID                       ( 4)
+  #define DDRDATA8CH0_CR_TXPERBITRANK3_Lane3_MSK                       (0x0000F000)
+  #define DDRDATA8CH0_CR_TXPERBITRANK3_Lane3_MAX                       (0x0000000F)
+  #define DDRDATA8CH0_CR_TXPERBITRANK3_Lane4_OFF                       (16)
+  #define DDRDATA8CH0_CR_TXPERBITRANK3_Lane4_WID                       ( 4)
+  #define DDRDATA8CH0_CR_TXPERBITRANK3_Lane4_MSK                       (0x000F0000)
+  #define DDRDATA8CH0_CR_TXPERBITRANK3_Lane4_MAX                       (0x0000000F)
+  #define DDRDATA8CH0_CR_TXPERBITRANK3_Lane5_OFF                       (20)
+  #define DDRDATA8CH0_CR_TXPERBITRANK3_Lane5_WID                       ( 4)
+  #define DDRDATA8CH0_CR_TXPERBITRANK3_Lane5_MSK                       (0x00F00000)
+  #define DDRDATA8CH0_CR_TXPERBITRANK3_Lane5_MAX                       (0x0000000F)
+  #define DDRDATA8CH0_CR_TXPERBITRANK3_Lane6_OFF                       (24)
+  #define DDRDATA8CH0_CR_TXPERBITRANK3_Lane6_WID                       ( 4)
+  #define DDRDATA8CH0_CR_TXPERBITRANK3_Lane6_MSK                       (0x0F000000)
+  #define DDRDATA8CH0_CR_TXPERBITRANK3_Lane6_MAX                       (0x0000000F)
+  #define DDRDATA8CH0_CR_TXPERBITRANK3_Lane7_OFF                       (28)
+  #define DDRDATA8CH0_CR_TXPERBITRANK3_Lane7_WID                       ( 4)
+  #define DDRDATA8CH0_CR_TXPERBITRANK3_Lane7_MSK                       (0xF0000000)
+  #define DDRDATA8CH0_CR_TXPERBITRANK3_Lane7_MAX                       (0x0000000F)
+
+#define DDRDATA8CH0_CR_RCOMPDATA0_REG                                (0x00001040)
+  #define DDRDATA8CH0_CR_RCOMPDATA0_RcompDrvUp_OFF                     ( 0)
+  #define DDRDATA8CH0_CR_RCOMPDATA0_RcompDrvUp_WID                     ( 6)
+  #define DDRDATA8CH0_CR_RCOMPDATA0_RcompDrvUp_MSK                     (0x0000003F)
+  #define DDRDATA8CH0_CR_RCOMPDATA0_RcompDrvUp_MAX                     (0x0000003F)
+  #define DDRDATA8CH0_CR_RCOMPDATA0_Spare0_OFF                         ( 6)
+  #define DDRDATA8CH0_CR_RCOMPDATA0_Spare0_WID                         ( 3)
+  #define DDRDATA8CH0_CR_RCOMPDATA0_Spare0_MSK                         (0x000001C0)
+  #define DDRDATA8CH0_CR_RCOMPDATA0_Spare0_MAX                         (0x00000007)
+  #define DDRDATA8CH0_CR_RCOMPDATA0_RcompDrvDown_OFF                   ( 9)
+  #define DDRDATA8CH0_CR_RCOMPDATA0_RcompDrvDown_WID                   ( 6)
+  #define DDRDATA8CH0_CR_RCOMPDATA0_RcompDrvDown_MSK                   (0x00007E00)
+  #define DDRDATA8CH0_CR_RCOMPDATA0_RcompDrvDown_MAX                   (0x0000003F)
+  #define DDRDATA8CH0_CR_RCOMPDATA0_VTComp_OFF                         (15)
+  #define DDRDATA8CH0_CR_RCOMPDATA0_VTComp_WID                         ( 5)
+  #define DDRDATA8CH0_CR_RCOMPDATA0_VTComp_MSK                         (0x000F8000)
+  #define DDRDATA8CH0_CR_RCOMPDATA0_VTComp_MAX                         (0x0000001F)
+  #define DDRDATA8CH0_CR_RCOMPDATA0_TcoComp_OFF                        (20)
+  #define DDRDATA8CH0_CR_RCOMPDATA0_TcoComp_WID                        ( 6)
+  #define DDRDATA8CH0_CR_RCOMPDATA0_TcoComp_MSK                        (0x03F00000)
+  #define DDRDATA8CH0_CR_RCOMPDATA0_TcoComp_MAX                        (0x0000003F)
+  #define DDRDATA8CH0_CR_RCOMPDATA0_SlewRateComp_OFF                   (26)
+  #define DDRDATA8CH0_CR_RCOMPDATA0_SlewRateComp_WID                   ( 5)
+  #define DDRDATA8CH0_CR_RCOMPDATA0_SlewRateComp_MSK                   (0x7C000000)
+  #define DDRDATA8CH0_CR_RCOMPDATA0_SlewRateComp_MAX                   (0x0000001F)
+  #define DDRDATA8CH0_CR_RCOMPDATA0_Spare2_OFF                         (31)
+  #define DDRDATA8CH0_CR_RCOMPDATA0_Spare2_WID                         ( 1)
+  #define DDRDATA8CH0_CR_RCOMPDATA0_Spare2_MSK                         (0x80000000)
+  #define DDRDATA8CH0_CR_RCOMPDATA0_Spare2_MAX                         (0x00000001)
+
+#define DDRDATA8CH0_CR_RCOMPDATA1_REG                                (0x00001044)
+  #define DDRDATA8CH0_CR_RCOMPDATA1_RcompOdtUp_OFF                     ( 0)
+  #define DDRDATA8CH0_CR_RCOMPDATA1_RcompOdtUp_WID                     ( 6)
+  #define DDRDATA8CH0_CR_RCOMPDATA1_RcompOdtUp_MSK                     (0x0000003F)
+  #define DDRDATA8CH0_CR_RCOMPDATA1_RcompOdtUp_MAX                     (0x0000003F)
+  #define DDRDATA8CH0_CR_RCOMPDATA1_Spare0_OFF                         ( 6)
+  #define DDRDATA8CH0_CR_RCOMPDATA1_Spare0_WID                         ( 3)
+  #define DDRDATA8CH0_CR_RCOMPDATA1_Spare0_MSK                         (0x000001C0)
+  #define DDRDATA8CH0_CR_RCOMPDATA1_Spare0_MAX                         (0x00000007)
+  #define DDRDATA8CH0_CR_RCOMPDATA1_RcompOdtDown_OFF                   ( 9)
+  #define DDRDATA8CH0_CR_RCOMPDATA1_RcompOdtDown_WID                   ( 6)
+  #define DDRDATA8CH0_CR_RCOMPDATA1_RcompOdtDown_MSK                   (0x00007E00)
+  #define DDRDATA8CH0_CR_RCOMPDATA1_RcompOdtDown_MAX                   (0x0000003F)
+  #define DDRDATA8CH0_CR_RCOMPDATA1_Spare1_OFF                         (15)
+  #define DDRDATA8CH0_CR_RCOMPDATA1_Spare1_WID                         ( 1)
+  #define DDRDATA8CH0_CR_RCOMPDATA1_Spare1_MSK                         (0x00008000)
+  #define DDRDATA8CH0_CR_RCOMPDATA1_Spare1_MAX                         (0x00000001)
+  #define DDRDATA8CH0_CR_RCOMPDATA1_PanicDrvDn_OFF                     (16)
+  #define DDRDATA8CH0_CR_RCOMPDATA1_PanicDrvDn_WID                     ( 6)
+  #define DDRDATA8CH0_CR_RCOMPDATA1_PanicDrvDn_MSK                     (0x003F0000)
+  #define DDRDATA8CH0_CR_RCOMPDATA1_PanicDrvDn_MAX                     (0x0000003F)
+  #define DDRDATA8CH0_CR_RCOMPDATA1_PanicDrvUp_OFF                     (22)
+  #define DDRDATA8CH0_CR_RCOMPDATA1_PanicDrvUp_WID                     ( 6)
+  #define DDRDATA8CH0_CR_RCOMPDATA1_PanicDrvUp_MSK                     (0x0FC00000)
+  #define DDRDATA8CH0_CR_RCOMPDATA1_PanicDrvUp_MAX                     (0x0000003F)
+  #define DDRDATA8CH0_CR_RCOMPDATA1_LevelShifterComp_OFF               (28)
+  #define DDRDATA8CH0_CR_RCOMPDATA1_LevelShifterComp_WID               ( 3)
+  #define DDRDATA8CH0_CR_RCOMPDATA1_LevelShifterComp_MSK               (0x70000000)
+  #define DDRDATA8CH0_CR_RCOMPDATA1_LevelShifterComp_MAX               (0x00000007)
+  #define DDRDATA8CH0_CR_RCOMPDATA1_Spare2_OFF                         (31)
+  #define DDRDATA8CH0_CR_RCOMPDATA1_Spare2_WID                         ( 1)
+  #define DDRDATA8CH0_CR_RCOMPDATA1_Spare2_MSK                         (0x80000000)
+  #define DDRDATA8CH0_CR_RCOMPDATA1_Spare2_MAX                         (0x00000001)
+
+#define DDRDATA8CH0_CR_TXXTALK_REG                                   (0x00001048)
+  #define DDRDATA8CH0_CR_TXXTALK_Lane0_OFF                             ( 0)
+  #define DDRDATA8CH0_CR_TXXTALK_Lane0_WID                             ( 4)
+  #define DDRDATA8CH0_CR_TXXTALK_Lane0_MSK                             (0x0000000F)
+  #define DDRDATA8CH0_CR_TXXTALK_Lane0_MAX                             (0x0000000F)
+  #define DDRDATA8CH0_CR_TXXTALK_Lane1_OFF                             ( 4)
+  #define DDRDATA8CH0_CR_TXXTALK_Lane1_WID                             ( 4)
+  #define DDRDATA8CH0_CR_TXXTALK_Lane1_MSK                             (0x000000F0)
+  #define DDRDATA8CH0_CR_TXXTALK_Lane1_MAX                             (0x0000000F)
+  #define DDRDATA8CH0_CR_TXXTALK_Lane2_OFF                             ( 8)
+  #define DDRDATA8CH0_CR_TXXTALK_Lane2_WID                             ( 4)
+  #define DDRDATA8CH0_CR_TXXTALK_Lane2_MSK                             (0x00000F00)
+  #define DDRDATA8CH0_CR_TXXTALK_Lane2_MAX                             (0x0000000F)
+  #define DDRDATA8CH0_CR_TXXTALK_Lane3_OFF                             (12)
+  #define DDRDATA8CH0_CR_TXXTALK_Lane3_WID                             ( 4)
+  #define DDRDATA8CH0_CR_TXXTALK_Lane3_MSK                             (0x0000F000)
+  #define DDRDATA8CH0_CR_TXXTALK_Lane3_MAX                             (0x0000000F)
+  #define DDRDATA8CH0_CR_TXXTALK_Lane4_OFF                             (16)
+  #define DDRDATA8CH0_CR_TXXTALK_Lane4_WID                             ( 4)
+  #define DDRDATA8CH0_CR_TXXTALK_Lane4_MSK                             (0x000F0000)
+  #define DDRDATA8CH0_CR_TXXTALK_Lane4_MAX                             (0x0000000F)
+  #define DDRDATA8CH0_CR_TXXTALK_Lane5_OFF                             (20)
+  #define DDRDATA8CH0_CR_TXXTALK_Lane5_WID                             ( 4)
+  #define DDRDATA8CH0_CR_TXXTALK_Lane5_MSK                             (0x00F00000)
+  #define DDRDATA8CH0_CR_TXXTALK_Lane5_MAX                             (0x0000000F)
+  #define DDRDATA8CH0_CR_TXXTALK_Lane6_OFF                             (24)
+  #define DDRDATA8CH0_CR_TXXTALK_Lane6_WID                             ( 4)
+  #define DDRDATA8CH0_CR_TXXTALK_Lane6_MSK                             (0x0F000000)
+  #define DDRDATA8CH0_CR_TXXTALK_Lane6_MAX                             (0x0000000F)
+  #define DDRDATA8CH0_CR_TXXTALK_Lane7_OFF                             (28)
+  #define DDRDATA8CH0_CR_TXXTALK_Lane7_WID                             ( 4)
+  #define DDRDATA8CH0_CR_TXXTALK_Lane7_MSK                             (0xF0000000)
+  #define DDRDATA8CH0_CR_TXXTALK_Lane7_MAX                             (0x0000000F)
+
+#define DDRDATA8CH0_CR_RXOFFSETVDQ_REG                               (0x0000104C)
+  #define DDRDATA8CH0_CR_RXOFFSETVDQ_Lane0_OFF                         ( 0)
+  #define DDRDATA8CH0_CR_RXOFFSETVDQ_Lane0_WID                         ( 4)
+  #define DDRDATA8CH0_CR_RXOFFSETVDQ_Lane0_MSK                         (0x0000000F)
+  #define DDRDATA8CH0_CR_RXOFFSETVDQ_Lane0_MAX                         (0x0000000F)
+  #define DDRDATA8CH0_CR_RXOFFSETVDQ_Lane1_OFF                         ( 4)
+  #define DDRDATA8CH0_CR_RXOFFSETVDQ_Lane1_WID                         ( 4)
+  #define DDRDATA8CH0_CR_RXOFFSETVDQ_Lane1_MSK                         (0x000000F0)
+  #define DDRDATA8CH0_CR_RXOFFSETVDQ_Lane1_MAX                         (0x0000000F)
+  #define DDRDATA8CH0_CR_RXOFFSETVDQ_Lane2_OFF                         ( 8)
+  #define DDRDATA8CH0_CR_RXOFFSETVDQ_Lane2_WID                         ( 4)
+  #define DDRDATA8CH0_CR_RXOFFSETVDQ_Lane2_MSK                         (0x00000F00)
+  #define DDRDATA8CH0_CR_RXOFFSETVDQ_Lane2_MAX                         (0x0000000F)
+  #define DDRDATA8CH0_CR_RXOFFSETVDQ_Lane3_OFF                         (12)
+  #define DDRDATA8CH0_CR_RXOFFSETVDQ_Lane3_WID                         ( 4)
+  #define DDRDATA8CH0_CR_RXOFFSETVDQ_Lane3_MSK                         (0x0000F000)
+  #define DDRDATA8CH0_CR_RXOFFSETVDQ_Lane3_MAX                         (0x0000000F)
+  #define DDRDATA8CH0_CR_RXOFFSETVDQ_Lane4_OFF                         (16)
+  #define DDRDATA8CH0_CR_RXOFFSETVDQ_Lane4_WID                         ( 4)
+  #define DDRDATA8CH0_CR_RXOFFSETVDQ_Lane4_MSK                         (0x000F0000)
+  #define DDRDATA8CH0_CR_RXOFFSETVDQ_Lane4_MAX                         (0x0000000F)
+  #define DDRDATA8CH0_CR_RXOFFSETVDQ_Lane5_OFF                         (20)
+  #define DDRDATA8CH0_CR_RXOFFSETVDQ_Lane5_WID                         ( 4)
+  #define DDRDATA8CH0_CR_RXOFFSETVDQ_Lane5_MSK                         (0x00F00000)
+  #define DDRDATA8CH0_CR_RXOFFSETVDQ_Lane5_MAX                         (0x0000000F)
+  #define DDRDATA8CH0_CR_RXOFFSETVDQ_Lane6_OFF                         (24)
+  #define DDRDATA8CH0_CR_RXOFFSETVDQ_Lane6_WID                         ( 4)
+  #define DDRDATA8CH0_CR_RXOFFSETVDQ_Lane6_MSK                         (0x0F000000)
+  #define DDRDATA8CH0_CR_RXOFFSETVDQ_Lane6_MAX                         (0x0000000F)
+  #define DDRDATA8CH0_CR_RXOFFSETVDQ_Lane7_OFF                         (28)
+  #define DDRDATA8CH0_CR_RXOFFSETVDQ_Lane7_WID                         ( 4)
+  #define DDRDATA8CH0_CR_RXOFFSETVDQ_Lane7_MSK                         (0xF0000000)
+  #define DDRDATA8CH0_CR_RXOFFSETVDQ_Lane7_MAX                         (0x0000000F)
+
+#define DDRDATA8CH0_CR_DDRDATARESERVED_REG                           (0x00001050)
+  #define DDRDATA8CH0_CR_DDRDATARESERVED_Spare_OFF                     ( 0)
+  #define DDRDATA8CH0_CR_DDRDATARESERVED_Spare_WID                     (32)
+  #define DDRDATA8CH0_CR_DDRDATARESERVED_Spare_MSK                     (0xFFFFFFFF)
+  #define DDRDATA8CH0_CR_DDRDATARESERVED_Spare_MAX                     (0xFFFFFFFF)
+
+#define DDRDATA8CH0_CR_DATATRAINFEEDBACK_REG                         (0x00001054)
+  #define DDRDATA8CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_OFF       ( 0)
+  #define DDRDATA8CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_WID       ( 9)
+  #define DDRDATA8CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_MSK       (0x000001FF)
+  #define DDRDATA8CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_MAX       (0x000001FF)
+  #define DDRDATA8CH0_CR_DATATRAINFEEDBACK_Spare_OFF                   ( 9)
+  #define DDRDATA8CH0_CR_DATATRAINFEEDBACK_Spare_WID                   (23)
+  #define DDRDATA8CH0_CR_DATATRAINFEEDBACK_Spare_MSK                   (0xFFFFFE00)
+  #define DDRDATA8CH0_CR_DATATRAINFEEDBACK_Spare_MAX                   (0x007FFFFF)
+
+#define DDRDATA8CH0_CR_DLLPITESTANDADC_REG                           (0x00001058)
+  #define DDRDATA8CH0_CR_DLLPITESTANDADC_RunTest_OFF                   ( 0)
+  #define DDRDATA8CH0_CR_DLLPITESTANDADC_RunTest_WID                   ( 1)
+  #define DDRDATA8CH0_CR_DLLPITESTANDADC_RunTest_MSK                   (0x00000001)
+  #define DDRDATA8CH0_CR_DLLPITESTANDADC_RunTest_MAX                   (0x00000001)
+  #define DDRDATA8CH0_CR_DLLPITESTANDADC_RunTest_DEF                   (0x00000000)
+  #define DDRDATA8CH0_CR_DLLPITESTANDADC_Load_OFF                      ( 1)
+  #define DDRDATA8CH0_CR_DLLPITESTANDADC_Load_WID                      ( 1)
+  #define DDRDATA8CH0_CR_DLLPITESTANDADC_Load_MSK                      (0x00000002)
+  #define DDRDATA8CH0_CR_DLLPITESTANDADC_Load_MAX                      (0x00000001)
+  #define DDRDATA8CH0_CR_DLLPITESTANDADC_Load_DEF                      (0x00000000)
+  #define DDRDATA8CH0_CR_DLLPITESTANDADC_ModeHVM_OFF                   ( 2)
+  #define DDRDATA8CH0_CR_DLLPITESTANDADC_ModeHVM_WID                   ( 1)
+  #define DDRDATA8CH0_CR_DLLPITESTANDADC_ModeHVM_MSK                   (0x00000004)
+  #define DDRDATA8CH0_CR_DLLPITESTANDADC_ModeHVM_MAX                   (0x00000001)
+  #define DDRDATA8CH0_CR_DLLPITESTANDADC_ModeHVM_DEF                   (0x00000000)
+  #define DDRDATA8CH0_CR_DLLPITESTANDADC_ModeDV_OFF                    ( 3)
+  #define DDRDATA8CH0_CR_DLLPITESTANDADC_ModeDV_WID                    ( 1)
+  #define DDRDATA8CH0_CR_DLLPITESTANDADC_ModeDV_MSK                    (0x00000008)
+  #define DDRDATA8CH0_CR_DLLPITESTANDADC_ModeDV_MAX                    (0x00000001)
+  #define DDRDATA8CH0_CR_DLLPITESTANDADC_ModeDV_DEF                    (0x00000000)
+  #define DDRDATA8CH0_CR_DLLPITESTANDADC_ModeADC_OFF                   ( 4)
+  #define DDRDATA8CH0_CR_DLLPITESTANDADC_ModeADC_WID                   ( 1)
+  #define DDRDATA8CH0_CR_DLLPITESTANDADC_ModeADC_MSK                   (0x00000010)
+  #define DDRDATA8CH0_CR_DLLPITESTANDADC_ModeADC_MAX                   (0x00000001)
+  #define DDRDATA8CH0_CR_DLLPITESTANDADC_ModeADC_DEF                   (0x00000000)
+  #define DDRDATA8CH0_CR_DLLPITESTANDADC_LoadCount_OFF                 ( 5)
+  #define DDRDATA8CH0_CR_DLLPITESTANDADC_LoadCount_WID                 (10)
+  #define DDRDATA8CH0_CR_DLLPITESTANDADC_LoadCount_MSK                 (0x00007FE0)
+  #define DDRDATA8CH0_CR_DLLPITESTANDADC_LoadCount_MAX                 (0x000003FF)
+  #define DDRDATA8CH0_CR_DLLPITESTANDADC_CountStatus_OFF               (15)
+  #define DDRDATA8CH0_CR_DLLPITESTANDADC_CountStatus_WID               (10)
+  #define DDRDATA8CH0_CR_DLLPITESTANDADC_CountStatus_MSK               (0x01FF8000)
+  #define DDRDATA8CH0_CR_DLLPITESTANDADC_CountStatus_MAX               (0x000003FF)
+  #define DDRDATA8CH0_CR_DLLPITESTANDADC_CountStatus_DEF               (0x00000000)
+  #define DDRDATA8CH0_CR_DLLPITESTANDADC_Spare_OFF                     (25)
+  #define DDRDATA8CH0_CR_DLLPITESTANDADC_Spare_WID                     ( 7)
+  #define DDRDATA8CH0_CR_DLLPITESTANDADC_Spare_MSK                     (0xFE000000)
+  #define DDRDATA8CH0_CR_DLLPITESTANDADC_Spare_MAX                     (0x0000007F)
+
+#define DDRDATA8CH0_CR_DDRCRDATAOFFSETCOMP_REG                       (0x0000105C)
+  #define DDRDATA8CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_OFF     ( 0)
+  #define DDRDATA8CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_WID     ( 6)
+  #define DDRDATA8CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MSK     (0x0000003F)
+  #define DDRDATA8CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MAX     (0x0000003F)
+  #define DDRDATA8CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_DEF     (0x00000000)
+  #define DDRDATA8CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_OFF   ( 6)
+  #define DDRDATA8CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_WID   ( 6)
+  #define DDRDATA8CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MSK   (0x00000FC0)
+  #define DDRDATA8CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MAX   (0x0000003F)
+  #define DDRDATA8CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_DEF   (0x00000000)
+  #define DDRDATA8CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_OFF     (12)
+  #define DDRDATA8CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_WID     ( 5)
+  #define DDRDATA8CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MSK     (0x0001F000)
+  #define DDRDATA8CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MAX     (0x0000001F)
+  #define DDRDATA8CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_DEF     (0x00000000)
+  #define DDRDATA8CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_OFF   (17)
+  #define DDRDATA8CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_WID   ( 5)
+  #define DDRDATA8CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MSK   (0x003E0000)
+  #define DDRDATA8CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MAX   (0x0000001F)
+  #define DDRDATA8CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_DEF   (0x00000000)
+  #define DDRDATA8CH0_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_OFF       (22)
+  #define DDRDATA8CH0_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_WID       ( 5)
+  #define DDRDATA8CH0_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_MSK       (0x07C00000)
+  #define DDRDATA8CH0_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_MAX       (0x0000001F)
+  #define DDRDATA8CH0_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_DEF       (0x00000000)
+  #define DDRDATA8CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_OFF  (27)
+  #define DDRDATA8CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_WID  ( 5)
+  #define DDRDATA8CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MSK  (0xF8000000)
+  #define DDRDATA8CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MAX  (0x0000001F)
+  #define DDRDATA8CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_DEF  (0x00000000)
+
+#define DDRDATA8CH0_CR_DDRCRDATACONTROL1_REG                         (0x00001060)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_RefPi_OFF                   ( 0)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_RefPi_WID                   ( 4)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_RefPi_MSK                   (0x0000000F)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_RefPi_MAX                   (0x0000000F)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_RefPi_DEF                   (0x00000000)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_DllMask_OFF                 ( 4)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_DllMask_WID                 ( 2)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_DllMask_MSK                 (0x00000030)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_DllMask_MAX                 (0x00000003)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_DllMask_DEF                 (0x00000000)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_DllWeakLock_OFF             ( 6)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_DllWeakLock_WID             ( 1)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_DllWeakLock_MSK             (0x00000040)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_DllWeakLock_MAX             (0x00000001)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_DllWeakLock_DEF             (0x00000000)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_OFF      ( 7)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_WID      ( 3)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MSK      (0x00000380)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MAX      (0x00000007)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_DEF      (0x00000000)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_OFF               (10)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_WID               ( 3)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_MSK               (0x00001C00)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_MAX               (0x00000007)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_DEF               (0x00000000)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_OdtDelay_OFF                (13)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_OdtDelay_WID                ( 4)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_OdtDelay_MSK                (0x0001E000)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_OdtDelay_MAX                (0x0000000F)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_OdtDelay_DEF                (0x00000000)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_OdtDuration_OFF             (17)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_OdtDuration_WID             ( 3)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_OdtDuration_MSK             (0x000E0000)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_OdtDuration_MAX             (0x00000007)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_OdtDuration_DEF             (0x00000000)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_OFF           (20)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_WID           ( 4)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_MSK           (0x00F00000)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_MAX           (0x0000000F)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_DEF           (0x00000000)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_OFF        (24)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_WID        ( 3)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_MSK        (0x07000000)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_MAX        (0x00000007)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_DEF        (0x00000000)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_BurstEndODTDelay_OFF        (27)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_BurstEndODTDelay_WID        ( 3)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_BurstEndODTDelay_MSK        (0x38000000)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_BurstEndODTDelay_MAX        (0x00000007)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_BurstEndODTDelay_DEF        (0x00000000)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_OFF          (30)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_WID          ( 1)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_MSK          (0x40000000)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_MAX          (0x00000001)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_DEF          (0x00000000)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_Rsvd1_OFF                   (31)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_Rsvd1_WID                   ( 1)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_Rsvd1_MSK                   (0x80000000)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_Rsvd1_MAX                   (0x00000001)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_Rsvd1_DEF                   (0x00000000)
+
+#define DDRDATA8CH0_CR_DDRCRDATACONTROL2_REG                         (0x00001064)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_OFF            ( 0)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_WID            ( 5)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_MSK            (0x0000001F)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_MAX            (0x0000001F)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_DEF            (0x00000000)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_OFF             ( 5)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_WID             ( 1)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_MSK             (0x00000020)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_MAX             (0x00000001)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_DEF             (0x00000000)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_ForceRxOn_OFF               ( 6)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_ForceRxOn_WID               ( 1)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_ForceRxOn_MSK               (0x00000040)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_ForceRxOn_MAX               (0x00000001)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_ForceRxOn_DEF               (0x00000000)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_LeakerComp_OFF              ( 7)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_LeakerComp_WID              ( 2)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_LeakerComp_MSK              (0x00000180)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_LeakerComp_MAX              (0x00000003)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_LeakerComp_DEF              (0x00000000)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_OFF          ( 9)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_WID          ( 4)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_MSK          (0x00001E00)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_MAX          (0x0000000F)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_DEF          (0x00000008)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_OFF             (13)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_WID             ( 5)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_MSK             (0x0003E000)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_MAX             (0x0000001F)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_DEF             (0x00000011)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_OFF             (18)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_WID             ( 1)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_MSK             (0x00040000)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_MAX             (0x00000001)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_DEF             (0x00000000)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_Spare_OFF                   (19)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_Spare_WID                   (13)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_Spare_MSK                   (0xFFF80000)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_Spare_MAX                   (0x00001FFF)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_Spare_DEF                   (0x00000000)
+
+#define DDRDATA8CH0_CR_DDRCRVSSHIORVREFCONTROL_REG                   (0x0000106C)
+  #define DDRDATA8CH0_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_OFF    ( 0)
+  #define DDRDATA8CH0_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_WID    (24)
+  #define DDRDATA8CH0_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_MSK    (0x00FFFFFF)
+  #define DDRDATA8CH0_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_MAX    (0x00FFFFFF)
+  #define DDRDATA8CH0_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_DEF    (0x00000000)
+  #define DDRDATA8CH0_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_OFF        (24)
+  #define DDRDATA8CH0_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_WID        ( 8)
+  #define DDRDATA8CH0_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_MSK        (0xFF000000)
+  #define DDRDATA8CH0_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_MAX        (0x000000FF)
+  #define DDRDATA8CH0_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_DEF        (0x00000000)
+
+#define DDRDATA8CH0_CR_DDRCRDATAOFFSETTRAIN_REG                      (0x00001070)
+  #define DDRDATA8CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_OFF          ( 0)
+  #define DDRDATA8CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_WID          ( 6)
+  #define DDRDATA8CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MSK          (0x0000003F)
+  #define DDRDATA8CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MAX          (0x0000003F)
+  #define DDRDATA8CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_DEF          (0x00000000)
+  #define DDRDATA8CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_OFF          ( 6)
+  #define DDRDATA8CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_WID          ( 6)
+  #define DDRDATA8CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MSK          (0x00000FC0)
+  #define DDRDATA8CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MAX          (0x0000003F)
+  #define DDRDATA8CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_DEF          (0x00000000)
+  #define DDRDATA8CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_OFF           (12)
+  #define DDRDATA8CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_WID           ( 6)
+  #define DDRDATA8CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MSK           (0x0003F000)
+  #define DDRDATA8CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MAX           (0x0000003F)
+  #define DDRDATA8CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_DEF           (0x00000000)
+  #define DDRDATA8CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_OFF          (18)
+  #define DDRDATA8CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_WID          ( 6)
+  #define DDRDATA8CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MSK          (0x00FC0000)
+  #define DDRDATA8CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MAX          (0x0000003F)
+  #define DDRDATA8CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_DEF          (0x00000000)
+  #define DDRDATA8CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_OFF           (24)
+  #define DDRDATA8CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_WID           ( 7)
+  #define DDRDATA8CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MSK           (0x7F000000)
+  #define DDRDATA8CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MAX           (0x0000007F)
+  #define DDRDATA8CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_DEF           (0x00000000)
+  #define DDRDATA8CH0_CR_DDRCRDATAOFFSETTRAIN_Spare_OFF                (31)
+  #define DDRDATA8CH0_CR_DDRCRDATAOFFSETTRAIN_Spare_WID                ( 1)
+  #define DDRDATA8CH0_CR_DDRCRDATAOFFSETTRAIN_Spare_MSK                (0x80000000)
+  #define DDRDATA8CH0_CR_DDRCRDATAOFFSETTRAIN_Spare_MAX                (0x00000001)
+  #define DDRDATA8CH0_CR_DDRCRDATAOFFSETTRAIN_Spare_DEF                (0x00000000)
+
+#define DDRDATA8CH0_CR_DDRCRDATACONTROL0_REG                         (0x00001074)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_OFF          ( 0)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_WID          ( 1)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_MSK          (0x00000001)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_MAX          (0x00000001)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_DEF          (0x00000000)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_OFF          ( 1)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_WID          ( 1)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_MSK          (0x00000002)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_MAX          (0x00000001)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_DEF          (0x00000000)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_OFF          ( 2)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_WID          ( 1)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_MSK          (0x00000004)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_MAX          (0x00000001)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_DEF          (0x00000000)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_OFF    ( 3)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_WID    ( 1)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MSK    (0x00000008)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MAX    (0x00000001)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_DEF    (0x00000000)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_TxOn_OFF                    ( 4)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_TxOn_WID                    ( 1)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_TxOn_MSK                    (0x00000010)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_TxOn_MAX                    (0x00000001)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_TxOn_DEF                    (0x00000000)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RfOn_OFF                    ( 5)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RfOn_WID                    ( 1)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RfOn_MSK                    (0x00000020)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RfOn_MAX                    (0x00000001)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RfOn_DEF                    (0x00000000)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RxPiOn_OFF                  ( 6)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RxPiOn_WID                  ( 1)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RxPiOn_MSK                  (0x00000040)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RxPiOn_MAX                  (0x00000001)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RxPiOn_DEF                  (0x00000000)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_TxPiOn_OFF                  ( 7)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_TxPiOn_WID                  ( 1)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_TxPiOn_MSK                  (0x00000080)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_TxPiOn_MAX                  (0x00000001)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_TxPiOn_DEF                  (0x00000000)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_OFF        ( 8)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_WID        ( 1)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_MSK        (0x00000100)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_MAX        (0x00000001)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_DEF        (0x00000000)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_OFF        ( 9)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_WID        ( 1)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MSK        (0x00000200)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MAX        (0x00000001)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_DEF        (0x00000000)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_TxDisable_OFF               (10)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_TxDisable_WID               ( 1)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_TxDisable_MSK               (0x00000400)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_TxDisable_MAX               (0x00000001)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_TxDisable_DEF               (0x00000000)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RxDisable_OFF               (11)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RxDisable_WID               ( 1)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RxDisable_MSK               (0x00000800)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RxDisable_MAX               (0x00000001)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RxDisable_DEF               (0x00000000)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_TxLong_OFF                  (12)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_TxLong_WID                  ( 1)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_TxLong_MSK                  (0x00001000)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_TxLong_MAX                  (0x00000001)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_TxLong_DEF                  (0x00000000)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_OFF               (13)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_WID               ( 2)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_MSK               (0x00006000)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_MAX               (0x00000003)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_DEF               (0x00000000)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RxReadPointer_OFF           (15)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RxReadPointer_WID           ( 3)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RxReadPointer_MSK           (0x00038000)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RxReadPointer_MAX           (0x00000007)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RxReadPointer_DEF           (0x00000000)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_DriverSegmentEnable_OFF     (18)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_DriverSegmentEnable_WID     ( 1)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_DriverSegmentEnable_MSK     (0x00040000)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_DriverSegmentEnable_MAX     (0x00000001)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_DriverSegmentEnable_DEF     (0x00000000)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_DataVccddqHi_OFF            (19)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_DataVccddqHi_WID            ( 1)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_DataVccddqHi_MSK            (0x00080000)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_DataVccddqHi_MAX            (0x00000001)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_DataVccddqHi_DEF            (0x00000000)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_ReadRFRd_OFF                (20)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_ReadRFRd_WID                ( 1)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_ReadRFRd_MSK                (0x00100000)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_ReadRFRd_MAX                (0x00000001)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_ReadRFRd_DEF                (0x00000000)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_ReadRFWr_OFF                (21)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_ReadRFWr_WID                ( 1)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_ReadRFWr_MSK                (0x00200000)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_ReadRFWr_MAX                (0x00000001)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_ReadRFWr_DEF                (0x00000000)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_ReadRFRank_OFF              (22)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_ReadRFRank_WID              ( 2)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_ReadRFRank_MSK              (0x00C00000)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_ReadRFRank_MAX              (0x00000003)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_ReadRFRank_DEF              (0x00000000)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_OFF              (24)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_WID              ( 1)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_MSK              (0x01000000)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_MAX              (0x00000001)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_DEF              (0x00000000)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_OdtSampOff_OFF              (25)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_OdtSampOff_WID              ( 1)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_OdtSampOff_MSK              (0x02000000)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_OdtSampOff_MAX              (0x00000001)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_OdtSampOff_DEF              (0x00000000)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_OFF        (26)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_WID        ( 1)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_MSK        (0x04000000)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_MAX        (0x00000001)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_DEF        (0x00000000)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_OFF         (27)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_WID         ( 1)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MSK         (0x08000000)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MAX         (0x00000001)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_DEF         (0x00000000)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_OFF              (28)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_WID              ( 1)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_MSK              (0x10000000)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_MAX              (0x00000001)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_DEF              (0x00000000)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_EnReadPreamble_OFF          (29)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_EnReadPreamble_WID          ( 1)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_EnReadPreamble_MSK          (0x20000000)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_EnReadPreamble_MAX          (0x00000001)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_EnReadPreamble_DEF          (0x00000000)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_OFF         (30)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_WID         ( 1)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MSK         (0x40000000)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MAX         (0x00000001)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_DEF         (0x00000000)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_OFF            (31)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_WID            ( 1)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_MSK            (0x80000000)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_MAX            (0x00000001)
+  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_DEF            (0x00000000)
+
+#define DDRDATA8CH0_CR_DDRCRVREFADJUST1_REG                          (0x00001078)
+  #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_CAVrefCtl_OFF                ( 0)
+  #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_CAVrefCtl_WID                ( 7)
+  #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_CAVrefCtl_MSK                (0x0000007F)
+  #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_CAVrefCtl_MAX                (0x0000007F)
+  #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_CAVrefCtl_DEF                (0x00000000)
+  #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_Ch1VrefCtl_OFF               ( 7)
+  #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_Ch1VrefCtl_WID               ( 7)
+  #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_Ch1VrefCtl_MSK               (0x00003F80)
+  #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_Ch1VrefCtl_MAX               (0x0000007F)
+  #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_Ch1VrefCtl_DEF               (0x00000000)
+  #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_Ch0VrefCtl_OFF               (14)
+  #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_Ch0VrefCtl_WID               ( 7)
+  #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_Ch0VrefCtl_MSK               (0x001FC000)
+  #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_Ch0VrefCtl_MAX               (0x0000007F)
+  #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_Ch0VrefCtl_DEF               (0x00000000)
+  #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCA_OFF             (21)
+  #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCA_WID             ( 1)
+  #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCA_MSK             (0x00200000)
+  #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCA_MAX             (0x00000001)
+  #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCA_DEF             (0x00000000)
+  #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_OFF            (22)
+  #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_WID            ( 1)
+  #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_MSK            (0x00400000)
+  #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_MAX            (0x00000001)
+  #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_DEF            (0x00000000)
+  #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_OFF            (23)
+  #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_WID            ( 1)
+  #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_MSK            (0x00800000)
+  #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_MAX            (0x00000001)
+  #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_DEF            (0x00000000)
+  #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_HiZTimerCtrl_OFF             (24)
+  #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_HiZTimerCtrl_WID             ( 2)
+  #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_HiZTimerCtrl_MSK             (0x03000000)
+  #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_HiZTimerCtrl_MAX             (0x00000003)
+  #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_HiZTimerCtrl_DEF             (0x00000000)
+  #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_OFF            (26)
+  #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_WID            ( 1)
+  #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_MSK            (0x04000000)
+  #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_MAX            (0x00000001)
+  #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_DEF            (0x00000000)
+  #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_Rsvd_OFF                     (27)
+  #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_Rsvd_WID                     ( 2)
+  #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_Rsvd_MSK                     (0x18000000)
+  #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_Rsvd_MAX                     (0x00000003)
+  #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_Rsvd_DEF                     (0x00000000)
+  #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_caSlowBW_OFF                 (29)
+  #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_caSlowBW_WID                 ( 1)
+  #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_caSlowBW_MSK                 (0x20000000)
+  #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_caSlowBW_MAX                 (0x00000001)
+  #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_caSlowBW_DEF                 (0x00000000)
+  #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_ch0SlowBW_OFF                (30)
+  #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_ch0SlowBW_WID                ( 1)
+  #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_ch0SlowBW_MSK                (0x40000000)
+  #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_ch0SlowBW_MAX                (0x00000001)
+  #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_ch0SlowBW_DEF                (0x00000000)
+  #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_ch1SlowBW_OFF                (31)
+  #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_ch1SlowBW_WID                ( 1)
+  #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_ch1SlowBW_MSK                (0x80000000)
+  #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_ch1SlowBW_MAX                (0x00000001)
+  #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_ch1SlowBW_DEF                (0x00000000)
+
+#define DDRDATA8CH1_CR_RXTRAINRANK0_REG                              (0x00001100)
+  #define DDRDATA8CH1_CR_RXTRAINRANK0_RxRcvEnPi_OFF                    ( 0)
+  #define DDRDATA8CH1_CR_RXTRAINRANK0_RxRcvEnPi_WID                    ( 9)
+  #define DDRDATA8CH1_CR_RXTRAINRANK0_RxRcvEnPi_MSK                    (0x000001FF)
+  #define DDRDATA8CH1_CR_RXTRAINRANK0_RxRcvEnPi_MAX                    (0x000001FF)
+  #define DDRDATA8CH1_CR_RXTRAINRANK0_RxDqsPPi_OFF                     ( 9)
+  #define DDRDATA8CH1_CR_RXTRAINRANK0_RxDqsPPi_WID                     ( 6)
+  #define DDRDATA8CH1_CR_RXTRAINRANK0_RxDqsPPi_MSK                     (0x00007E00)
+  #define DDRDATA8CH1_CR_RXTRAINRANK0_RxDqsPPi_MAX                     (0x0000003F)
+  #define DDRDATA8CH1_CR_RXTRAINRANK0_RxEq_OFF                         (15)
+  #define DDRDATA8CH1_CR_RXTRAINRANK0_RxEq_WID                         ( 5)
+  #define DDRDATA8CH1_CR_RXTRAINRANK0_RxEq_MSK                         (0x000F8000)
+  #define DDRDATA8CH1_CR_RXTRAINRANK0_RxEq_MAX                         (0x0000001F)
+  #define DDRDATA8CH1_CR_RXTRAINRANK0_RxDqsNPi_OFF                     (20)
+  #define DDRDATA8CH1_CR_RXTRAINRANK0_RxDqsNPi_WID                     ( 6)
+  #define DDRDATA8CH1_CR_RXTRAINRANK0_RxDqsNPi_MSK                     (0x03F00000)
+  #define DDRDATA8CH1_CR_RXTRAINRANK0_RxDqsNPi_MAX                     (0x0000003F)
+  #define DDRDATA8CH1_CR_RXTRAINRANK0_RxVref_OFF                       (26)
+  #define DDRDATA8CH1_CR_RXTRAINRANK0_RxVref_WID                       ( 6)
+  #define DDRDATA8CH1_CR_RXTRAINRANK0_RxVref_MSK                       (0xFC000000)
+  #define DDRDATA8CH1_CR_RXTRAINRANK0_RxVref_MAX                       (0x0000003F)
+
+#define DDRDATA8CH1_CR_RXTRAINRANK1_REG                              (0x00001104)
+  #define DDRDATA8CH1_CR_RXTRAINRANK1_RxRcvEnPi_OFF                    ( 0)
+  #define DDRDATA8CH1_CR_RXTRAINRANK1_RxRcvEnPi_WID                    ( 9)
+  #define DDRDATA8CH1_CR_RXTRAINRANK1_RxRcvEnPi_MSK                    (0x000001FF)
+  #define DDRDATA8CH1_CR_RXTRAINRANK1_RxRcvEnPi_MAX                    (0x000001FF)
+  #define DDRDATA8CH1_CR_RXTRAINRANK1_RxDqsPPi_OFF                     ( 9)
+  #define DDRDATA8CH1_CR_RXTRAINRANK1_RxDqsPPi_WID                     ( 6)
+  #define DDRDATA8CH1_CR_RXTRAINRANK1_RxDqsPPi_MSK                     (0x00007E00)
+  #define DDRDATA8CH1_CR_RXTRAINRANK1_RxDqsPPi_MAX                     (0x0000003F)
+  #define DDRDATA8CH1_CR_RXTRAINRANK1_RxEq_OFF                         (15)
+  #define DDRDATA8CH1_CR_RXTRAINRANK1_RxEq_WID                         ( 5)
+  #define DDRDATA8CH1_CR_RXTRAINRANK1_RxEq_MSK                         (0x000F8000)
+  #define DDRDATA8CH1_CR_RXTRAINRANK1_RxEq_MAX                         (0x0000001F)
+  #define DDRDATA8CH1_CR_RXTRAINRANK1_RxDqsNPi_OFF                     (20)
+  #define DDRDATA8CH1_CR_RXTRAINRANK1_RxDqsNPi_WID                     ( 6)
+  #define DDRDATA8CH1_CR_RXTRAINRANK1_RxDqsNPi_MSK                     (0x03F00000)
+  #define DDRDATA8CH1_CR_RXTRAINRANK1_RxDqsNPi_MAX                     (0x0000003F)
+  #define DDRDATA8CH1_CR_RXTRAINRANK1_RxVref_OFF                       (26)
+  #define DDRDATA8CH1_CR_RXTRAINRANK1_RxVref_WID                       ( 6)
+  #define DDRDATA8CH1_CR_RXTRAINRANK1_RxVref_MSK                       (0xFC000000)
+  #define DDRDATA8CH1_CR_RXTRAINRANK1_RxVref_MAX                       (0x0000003F)
+
+#define DDRDATA8CH1_CR_RXTRAINRANK2_REG                              (0x00001108)
+  #define DDRDATA8CH1_CR_RXTRAINRANK2_RxRcvEnPi_OFF                    ( 0)
+  #define DDRDATA8CH1_CR_RXTRAINRANK2_RxRcvEnPi_WID                    ( 9)
+  #define DDRDATA8CH1_CR_RXTRAINRANK2_RxRcvEnPi_MSK                    (0x000001FF)
+  #define DDRDATA8CH1_CR_RXTRAINRANK2_RxRcvEnPi_MAX                    (0x000001FF)
+  #define DDRDATA8CH1_CR_RXTRAINRANK2_RxDqsPPi_OFF                     ( 9)
+  #define DDRDATA8CH1_CR_RXTRAINRANK2_RxDqsPPi_WID                     ( 6)
+  #define DDRDATA8CH1_CR_RXTRAINRANK2_RxDqsPPi_MSK                     (0x00007E00)
+  #define DDRDATA8CH1_CR_RXTRAINRANK2_RxDqsPPi_MAX                     (0x0000003F)
+  #define DDRDATA8CH1_CR_RXTRAINRANK2_RxEq_OFF                         (15)
+  #define DDRDATA8CH1_CR_RXTRAINRANK2_RxEq_WID                         ( 5)
+  #define DDRDATA8CH1_CR_RXTRAINRANK2_RxEq_MSK                         (0x000F8000)
+  #define DDRDATA8CH1_CR_RXTRAINRANK2_RxEq_MAX                         (0x0000001F)
+  #define DDRDATA8CH1_CR_RXTRAINRANK2_RxDqsNPi_OFF                     (20)
+  #define DDRDATA8CH1_CR_RXTRAINRANK2_RxDqsNPi_WID                     ( 6)
+  #define DDRDATA8CH1_CR_RXTRAINRANK2_RxDqsNPi_MSK                     (0x03F00000)
+  #define DDRDATA8CH1_CR_RXTRAINRANK2_RxDqsNPi_MAX                     (0x0000003F)
+  #define DDRDATA8CH1_CR_RXTRAINRANK2_RxVref_OFF                       (26)
+  #define DDRDATA8CH1_CR_RXTRAINRANK2_RxVref_WID                       ( 6)
+  #define DDRDATA8CH1_CR_RXTRAINRANK2_RxVref_MSK                       (0xFC000000)
+  #define DDRDATA8CH1_CR_RXTRAINRANK2_RxVref_MAX                       (0x0000003F)
+
+#define DDRDATA8CH1_CR_RXTRAINRANK3_REG                              (0x0000110C)
+  #define DDRDATA8CH1_CR_RXTRAINRANK3_RxRcvEnPi_OFF                    ( 0)
+  #define DDRDATA8CH1_CR_RXTRAINRANK3_RxRcvEnPi_WID                    ( 9)
+  #define DDRDATA8CH1_CR_RXTRAINRANK3_RxRcvEnPi_MSK                    (0x000001FF)
+  #define DDRDATA8CH1_CR_RXTRAINRANK3_RxRcvEnPi_MAX                    (0x000001FF)
+  #define DDRDATA8CH1_CR_RXTRAINRANK3_RxDqsPPi_OFF                     ( 9)
+  #define DDRDATA8CH1_CR_RXTRAINRANK3_RxDqsPPi_WID                     ( 6)
+  #define DDRDATA8CH1_CR_RXTRAINRANK3_RxDqsPPi_MSK                     (0x00007E00)
+  #define DDRDATA8CH1_CR_RXTRAINRANK3_RxDqsPPi_MAX                     (0x0000003F)
+  #define DDRDATA8CH1_CR_RXTRAINRANK3_RxEq_OFF                         (15)
+  #define DDRDATA8CH1_CR_RXTRAINRANK3_RxEq_WID                         ( 5)
+  #define DDRDATA8CH1_CR_RXTRAINRANK3_RxEq_MSK                         (0x000F8000)
+  #define DDRDATA8CH1_CR_RXTRAINRANK3_RxEq_MAX                         (0x0000001F)
+  #define DDRDATA8CH1_CR_RXTRAINRANK3_RxDqsNPi_OFF                     (20)
+  #define DDRDATA8CH1_CR_RXTRAINRANK3_RxDqsNPi_WID                     ( 6)
+  #define DDRDATA8CH1_CR_RXTRAINRANK3_RxDqsNPi_MSK                     (0x03F00000)
+  #define DDRDATA8CH1_CR_RXTRAINRANK3_RxDqsNPi_MAX                     (0x0000003F)
+  #define DDRDATA8CH1_CR_RXTRAINRANK3_RxVref_OFF                       (26)
+  #define DDRDATA8CH1_CR_RXTRAINRANK3_RxVref_WID                       ( 6)
+  #define DDRDATA8CH1_CR_RXTRAINRANK3_RxVref_MSK                       (0xFC000000)
+  #define DDRDATA8CH1_CR_RXTRAINRANK3_RxVref_MAX                       (0x0000003F)
+
+#define DDRDATA8CH1_CR_RXPERBITRANK0_REG                             (0x00001110)
+  #define DDRDATA8CH1_CR_RXPERBITRANK0_Lane0_OFF                       ( 0)
+  #define DDRDATA8CH1_CR_RXPERBITRANK0_Lane0_WID                       ( 4)
+  #define DDRDATA8CH1_CR_RXPERBITRANK0_Lane0_MSK                       (0x0000000F)
+  #define DDRDATA8CH1_CR_RXPERBITRANK0_Lane0_MAX                       (0x0000000F)
+  #define DDRDATA8CH1_CR_RXPERBITRANK0_Lane1_OFF                       ( 4)
+  #define DDRDATA8CH1_CR_RXPERBITRANK0_Lane1_WID                       ( 4)
+  #define DDRDATA8CH1_CR_RXPERBITRANK0_Lane1_MSK                       (0x000000F0)
+  #define DDRDATA8CH1_CR_RXPERBITRANK0_Lane1_MAX                       (0x0000000F)
+  #define DDRDATA8CH1_CR_RXPERBITRANK0_Lane2_OFF                       ( 8)
+  #define DDRDATA8CH1_CR_RXPERBITRANK0_Lane2_WID                       ( 4)
+  #define DDRDATA8CH1_CR_RXPERBITRANK0_Lane2_MSK                       (0x00000F00)
+  #define DDRDATA8CH1_CR_RXPERBITRANK0_Lane2_MAX                       (0x0000000F)
+  #define DDRDATA8CH1_CR_RXPERBITRANK0_Lane3_OFF                       (12)
+  #define DDRDATA8CH1_CR_RXPERBITRANK0_Lane3_WID                       ( 4)
+  #define DDRDATA8CH1_CR_RXPERBITRANK0_Lane3_MSK                       (0x0000F000)
+  #define DDRDATA8CH1_CR_RXPERBITRANK0_Lane3_MAX                       (0x0000000F)
+  #define DDRDATA8CH1_CR_RXPERBITRANK0_Lane4_OFF                       (16)
+  #define DDRDATA8CH1_CR_RXPERBITRANK0_Lane4_WID                       ( 4)
+  #define DDRDATA8CH1_CR_RXPERBITRANK0_Lane4_MSK                       (0x000F0000)
+  #define DDRDATA8CH1_CR_RXPERBITRANK0_Lane4_MAX                       (0x0000000F)
+  #define DDRDATA8CH1_CR_RXPERBITRANK0_Lane5_OFF                       (20)
+  #define DDRDATA8CH1_CR_RXPERBITRANK0_Lane5_WID                       ( 4)
+  #define DDRDATA8CH1_CR_RXPERBITRANK0_Lane5_MSK                       (0x00F00000)
+  #define DDRDATA8CH1_CR_RXPERBITRANK0_Lane5_MAX                       (0x0000000F)
+  #define DDRDATA8CH1_CR_RXPERBITRANK0_Lane6_OFF                       (24)
+  #define DDRDATA8CH1_CR_RXPERBITRANK0_Lane6_WID                       ( 4)
+  #define DDRDATA8CH1_CR_RXPERBITRANK0_Lane6_MSK                       (0x0F000000)
+  #define DDRDATA8CH1_CR_RXPERBITRANK0_Lane6_MAX                       (0x0000000F)
+  #define DDRDATA8CH1_CR_RXPERBITRANK0_Lane7_OFF                       (28)
+  #define DDRDATA8CH1_CR_RXPERBITRANK0_Lane7_WID                       ( 4)
+  #define DDRDATA8CH1_CR_RXPERBITRANK0_Lane7_MSK                       (0xF0000000)
+  #define DDRDATA8CH1_CR_RXPERBITRANK0_Lane7_MAX                       (0x0000000F)
+
+#define DDRDATA8CH1_CR_RXPERBITRANK1_REG                             (0x00001114)
+  #define DDRDATA8CH1_CR_RXPERBITRANK1_Lane0_OFF                       ( 0)
+  #define DDRDATA8CH1_CR_RXPERBITRANK1_Lane0_WID                       ( 4)
+  #define DDRDATA8CH1_CR_RXPERBITRANK1_Lane0_MSK                       (0x0000000F)
+  #define DDRDATA8CH1_CR_RXPERBITRANK1_Lane0_MAX                       (0x0000000F)
+  #define DDRDATA8CH1_CR_RXPERBITRANK1_Lane1_OFF                       ( 4)
+  #define DDRDATA8CH1_CR_RXPERBITRANK1_Lane1_WID                       ( 4)
+  #define DDRDATA8CH1_CR_RXPERBITRANK1_Lane1_MSK                       (0x000000F0)
+  #define DDRDATA8CH1_CR_RXPERBITRANK1_Lane1_MAX                       (0x0000000F)
+  #define DDRDATA8CH1_CR_RXPERBITRANK1_Lane2_OFF                       ( 8)
+  #define DDRDATA8CH1_CR_RXPERBITRANK1_Lane2_WID                       ( 4)
+  #define DDRDATA8CH1_CR_RXPERBITRANK1_Lane2_MSK                       (0x00000F00)
+  #define DDRDATA8CH1_CR_RXPERBITRANK1_Lane2_MAX                       (0x0000000F)
+  #define DDRDATA8CH1_CR_RXPERBITRANK1_Lane3_OFF                       (12)
+  #define DDRDATA8CH1_CR_RXPERBITRANK1_Lane3_WID                       ( 4)
+  #define DDRDATA8CH1_CR_RXPERBITRANK1_Lane3_MSK                       (0x0000F000)
+  #define DDRDATA8CH1_CR_RXPERBITRANK1_Lane3_MAX                       (0x0000000F)
+  #define DDRDATA8CH1_CR_RXPERBITRANK1_Lane4_OFF                       (16)
+  #define DDRDATA8CH1_CR_RXPERBITRANK1_Lane4_WID                       ( 4)
+  #define DDRDATA8CH1_CR_RXPERBITRANK1_Lane4_MSK                       (0x000F0000)
+  #define DDRDATA8CH1_CR_RXPERBITRANK1_Lane4_MAX                       (0x0000000F)
+  #define DDRDATA8CH1_CR_RXPERBITRANK1_Lane5_OFF                       (20)
+  #define DDRDATA8CH1_CR_RXPERBITRANK1_Lane5_WID                       ( 4)
+  #define DDRDATA8CH1_CR_RXPERBITRANK1_Lane5_MSK                       (0x00F00000)
+  #define DDRDATA8CH1_CR_RXPERBITRANK1_Lane5_MAX                       (0x0000000F)
+  #define DDRDATA8CH1_CR_RXPERBITRANK1_Lane6_OFF                       (24)
+  #define DDRDATA8CH1_CR_RXPERBITRANK1_Lane6_WID                       ( 4)
+  #define DDRDATA8CH1_CR_RXPERBITRANK1_Lane6_MSK                       (0x0F000000)
+  #define DDRDATA8CH1_CR_RXPERBITRANK1_Lane6_MAX                       (0x0000000F)
+  #define DDRDATA8CH1_CR_RXPERBITRANK1_Lane7_OFF                       (28)
+  #define DDRDATA8CH1_CR_RXPERBITRANK1_Lane7_WID                       ( 4)
+  #define DDRDATA8CH1_CR_RXPERBITRANK1_Lane7_MSK                       (0xF0000000)
+  #define DDRDATA8CH1_CR_RXPERBITRANK1_Lane7_MAX                       (0x0000000F)
+
+#define DDRDATA8CH1_CR_RXPERBITRANK2_REG                             (0x00001118)
+  #define DDRDATA8CH1_CR_RXPERBITRANK2_Lane0_OFF                       ( 0)
+  #define DDRDATA8CH1_CR_RXPERBITRANK2_Lane0_WID                       ( 4)
+  #define DDRDATA8CH1_CR_RXPERBITRANK2_Lane0_MSK                       (0x0000000F)
+  #define DDRDATA8CH1_CR_RXPERBITRANK2_Lane0_MAX                       (0x0000000F)
+  #define DDRDATA8CH1_CR_RXPERBITRANK2_Lane1_OFF                       ( 4)
+  #define DDRDATA8CH1_CR_RXPERBITRANK2_Lane1_WID                       ( 4)
+  #define DDRDATA8CH1_CR_RXPERBITRANK2_Lane1_MSK                       (0x000000F0)
+  #define DDRDATA8CH1_CR_RXPERBITRANK2_Lane1_MAX                       (0x0000000F)
+  #define DDRDATA8CH1_CR_RXPERBITRANK2_Lane2_OFF                       ( 8)
+  #define DDRDATA8CH1_CR_RXPERBITRANK2_Lane2_WID                       ( 4)
+  #define DDRDATA8CH1_CR_RXPERBITRANK2_Lane2_MSK                       (0x00000F00)
+  #define DDRDATA8CH1_CR_RXPERBITRANK2_Lane2_MAX                       (0x0000000F)
+  #define DDRDATA8CH1_CR_RXPERBITRANK2_Lane3_OFF                       (12)
+  #define DDRDATA8CH1_CR_RXPERBITRANK2_Lane3_WID                       ( 4)
+  #define DDRDATA8CH1_CR_RXPERBITRANK2_Lane3_MSK                       (0x0000F000)
+  #define DDRDATA8CH1_CR_RXPERBITRANK2_Lane3_MAX                       (0x0000000F)
+  #define DDRDATA8CH1_CR_RXPERBITRANK2_Lane4_OFF                       (16)
+  #define DDRDATA8CH1_CR_RXPERBITRANK2_Lane4_WID                       ( 4)
+  #define DDRDATA8CH1_CR_RXPERBITRANK2_Lane4_MSK                       (0x000F0000)
+  #define DDRDATA8CH1_CR_RXPERBITRANK2_Lane4_MAX                       (0x0000000F)
+  #define DDRDATA8CH1_CR_RXPERBITRANK2_Lane5_OFF                       (20)
+  #define DDRDATA8CH1_CR_RXPERBITRANK2_Lane5_WID                       ( 4)
+  #define DDRDATA8CH1_CR_RXPERBITRANK2_Lane5_MSK                       (0x00F00000)
+  #define DDRDATA8CH1_CR_RXPERBITRANK2_Lane5_MAX                       (0x0000000F)
+  #define DDRDATA8CH1_CR_RXPERBITRANK2_Lane6_OFF                       (24)
+  #define DDRDATA8CH1_CR_RXPERBITRANK2_Lane6_WID                       ( 4)
+  #define DDRDATA8CH1_CR_RXPERBITRANK2_Lane6_MSK                       (0x0F000000)
+  #define DDRDATA8CH1_CR_RXPERBITRANK2_Lane6_MAX                       (0x0000000F)
+  #define DDRDATA8CH1_CR_RXPERBITRANK2_Lane7_OFF                       (28)
+  #define DDRDATA8CH1_CR_RXPERBITRANK2_Lane7_WID                       ( 4)
+  #define DDRDATA8CH1_CR_RXPERBITRANK2_Lane7_MSK                       (0xF0000000)
+  #define DDRDATA8CH1_CR_RXPERBITRANK2_Lane7_MAX                       (0x0000000F)
+
+#define DDRDATA8CH1_CR_RXPERBITRANK3_REG                             (0x0000111C)
+  #define DDRDATA8CH1_CR_RXPERBITRANK3_Lane0_OFF                       ( 0)
+  #define DDRDATA8CH1_CR_RXPERBITRANK3_Lane0_WID                       ( 4)
+  #define DDRDATA8CH1_CR_RXPERBITRANK3_Lane0_MSK                       (0x0000000F)
+  #define DDRDATA8CH1_CR_RXPERBITRANK3_Lane0_MAX                       (0x0000000F)
+  #define DDRDATA8CH1_CR_RXPERBITRANK3_Lane1_OFF                       ( 4)
+  #define DDRDATA8CH1_CR_RXPERBITRANK3_Lane1_WID                       ( 4)
+  #define DDRDATA8CH1_CR_RXPERBITRANK3_Lane1_MSK                       (0x000000F0)
+  #define DDRDATA8CH1_CR_RXPERBITRANK3_Lane1_MAX                       (0x0000000F)
+  #define DDRDATA8CH1_CR_RXPERBITRANK3_Lane2_OFF                       ( 8)
+  #define DDRDATA8CH1_CR_RXPERBITRANK3_Lane2_WID                       ( 4)
+  #define DDRDATA8CH1_CR_RXPERBITRANK3_Lane2_MSK                       (0x00000F00)
+  #define DDRDATA8CH1_CR_RXPERBITRANK3_Lane2_MAX                       (0x0000000F)
+  #define DDRDATA8CH1_CR_RXPERBITRANK3_Lane3_OFF                       (12)
+  #define DDRDATA8CH1_CR_RXPERBITRANK3_Lane3_WID                       ( 4)
+  #define DDRDATA8CH1_CR_RXPERBITRANK3_Lane3_MSK                       (0x0000F000)
+  #define DDRDATA8CH1_CR_RXPERBITRANK3_Lane3_MAX                       (0x0000000F)
+  #define DDRDATA8CH1_CR_RXPERBITRANK3_Lane4_OFF                       (16)
+  #define DDRDATA8CH1_CR_RXPERBITRANK3_Lane4_WID                       ( 4)
+  #define DDRDATA8CH1_CR_RXPERBITRANK3_Lane4_MSK                       (0x000F0000)
+  #define DDRDATA8CH1_CR_RXPERBITRANK3_Lane4_MAX                       (0x0000000F)
+  #define DDRDATA8CH1_CR_RXPERBITRANK3_Lane5_OFF                       (20)
+  #define DDRDATA8CH1_CR_RXPERBITRANK3_Lane5_WID                       ( 4)
+  #define DDRDATA8CH1_CR_RXPERBITRANK3_Lane5_MSK                       (0x00F00000)
+  #define DDRDATA8CH1_CR_RXPERBITRANK3_Lane5_MAX                       (0x0000000F)
+  #define DDRDATA8CH1_CR_RXPERBITRANK3_Lane6_OFF                       (24)
+  #define DDRDATA8CH1_CR_RXPERBITRANK3_Lane6_WID                       ( 4)
+  #define DDRDATA8CH1_CR_RXPERBITRANK3_Lane6_MSK                       (0x0F000000)
+  #define DDRDATA8CH1_CR_RXPERBITRANK3_Lane6_MAX                       (0x0000000F)
+  #define DDRDATA8CH1_CR_RXPERBITRANK3_Lane7_OFF                       (28)
+  #define DDRDATA8CH1_CR_RXPERBITRANK3_Lane7_WID                       ( 4)
+  #define DDRDATA8CH1_CR_RXPERBITRANK3_Lane7_MSK                       (0xF0000000)
+  #define DDRDATA8CH1_CR_RXPERBITRANK3_Lane7_MAX                       (0x0000000F)
+
+#define DDRDATA8CH1_CR_TXTRAINRANK0_REG                              (0x00001120)
+  #define DDRDATA8CH1_CR_TXTRAINRANK0_TxDqDelay_OFF                    ( 0)
+  #define DDRDATA8CH1_CR_TXTRAINRANK0_TxDqDelay_WID                    ( 9)
+  #define DDRDATA8CH1_CR_TXTRAINRANK0_TxDqDelay_MSK                    (0x000001FF)
+  #define DDRDATA8CH1_CR_TXTRAINRANK0_TxDqDelay_MAX                    (0x000001FF)
+  #define DDRDATA8CH1_CR_TXTRAINRANK0_TxDqsDelay_OFF                   ( 9)
+  #define DDRDATA8CH1_CR_TXTRAINRANK0_TxDqsDelay_WID                   ( 9)
+  #define DDRDATA8CH1_CR_TXTRAINRANK0_TxDqsDelay_MSK                   (0x0003FE00)
+  #define DDRDATA8CH1_CR_TXTRAINRANK0_TxDqsDelay_MAX                   (0x000001FF)
+  #define DDRDATA8CH1_CR_TXTRAINRANK0_Spare0_OFF                       (18)
+  #define DDRDATA8CH1_CR_TXTRAINRANK0_Spare0_WID                       ( 2)
+  #define DDRDATA8CH1_CR_TXTRAINRANK0_Spare0_MSK                       (0x000C0000)
+  #define DDRDATA8CH1_CR_TXTRAINRANK0_Spare0_MAX                       (0x00000003)
+  #define DDRDATA8CH1_CR_TXTRAINRANK0_TxEqualization_OFF               (20)
+  #define DDRDATA8CH1_CR_TXTRAINRANK0_TxEqualization_WID               ( 6)
+  #define DDRDATA8CH1_CR_TXTRAINRANK0_TxEqualization_MSK               (0x03F00000)
+  #define DDRDATA8CH1_CR_TXTRAINRANK0_TxEqualization_MAX               (0x0000003F)
+  #define DDRDATA8CH1_CR_TXTRAINRANK0_Spare1_OFF                       (26)
+  #define DDRDATA8CH1_CR_TXTRAINRANK0_Spare1_WID                       ( 6)
+  #define DDRDATA8CH1_CR_TXTRAINRANK0_Spare1_MSK                       (0xFC000000)
+  #define DDRDATA8CH1_CR_TXTRAINRANK0_Spare1_MAX                       (0x0000003F)
+
+#define DDRDATA8CH1_CR_TXTRAINRANK1_REG                              (0x00001124)
+  #define DDRDATA8CH1_CR_TXTRAINRANK1_TxDqDelay_OFF                    ( 0)
+  #define DDRDATA8CH1_CR_TXTRAINRANK1_TxDqDelay_WID                    ( 9)
+  #define DDRDATA8CH1_CR_TXTRAINRANK1_TxDqDelay_MSK                    (0x000001FF)
+  #define DDRDATA8CH1_CR_TXTRAINRANK1_TxDqDelay_MAX                    (0x000001FF)
+  #define DDRDATA8CH1_CR_TXTRAINRANK1_TxDqsDelay_OFF                   ( 9)
+  #define DDRDATA8CH1_CR_TXTRAINRANK1_TxDqsDelay_WID                   ( 9)
+  #define DDRDATA8CH1_CR_TXTRAINRANK1_TxDqsDelay_MSK                   (0x0003FE00)
+  #define DDRDATA8CH1_CR_TXTRAINRANK1_TxDqsDelay_MAX                   (0x000001FF)
+  #define DDRDATA8CH1_CR_TXTRAINRANK1_Spare0_OFF                       (18)
+  #define DDRDATA8CH1_CR_TXTRAINRANK1_Spare0_WID                       ( 2)
+  #define DDRDATA8CH1_CR_TXTRAINRANK1_Spare0_MSK                       (0x000C0000)
+  #define DDRDATA8CH1_CR_TXTRAINRANK1_Spare0_MAX                       (0x00000003)
+  #define DDRDATA8CH1_CR_TXTRAINRANK1_TxEqualization_OFF               (20)
+  #define DDRDATA8CH1_CR_TXTRAINRANK1_TxEqualization_WID               ( 6)
+  #define DDRDATA8CH1_CR_TXTRAINRANK1_TxEqualization_MSK               (0x03F00000)
+  #define DDRDATA8CH1_CR_TXTRAINRANK1_TxEqualization_MAX               (0x0000003F)
+  #define DDRDATA8CH1_CR_TXTRAINRANK1_Spare1_OFF                       (26)
+  #define DDRDATA8CH1_CR_TXTRAINRANK1_Spare1_WID                       ( 6)
+  #define DDRDATA8CH1_CR_TXTRAINRANK1_Spare1_MSK                       (0xFC000000)
+  #define DDRDATA8CH1_CR_TXTRAINRANK1_Spare1_MAX                       (0x0000003F)
+
+#define DDRDATA8CH1_CR_TXTRAINRANK2_REG                              (0x00001128)
+  #define DDRDATA8CH1_CR_TXTRAINRANK2_TxDqDelay_OFF                    ( 0)
+  #define DDRDATA8CH1_CR_TXTRAINRANK2_TxDqDelay_WID                    ( 9)
+  #define DDRDATA8CH1_CR_TXTRAINRANK2_TxDqDelay_MSK                    (0x000001FF)
+  #define DDRDATA8CH1_CR_TXTRAINRANK2_TxDqDelay_MAX                    (0x000001FF)
+  #define DDRDATA8CH1_CR_TXTRAINRANK2_TxDqsDelay_OFF                   ( 9)
+  #define DDRDATA8CH1_CR_TXTRAINRANK2_TxDqsDelay_WID                   ( 9)
+  #define DDRDATA8CH1_CR_TXTRAINRANK2_TxDqsDelay_MSK                   (0x0003FE00)
+  #define DDRDATA8CH1_CR_TXTRAINRANK2_TxDqsDelay_MAX                   (0x000001FF)
+  #define DDRDATA8CH1_CR_TXTRAINRANK2_Spare0_OFF                       (18)
+  #define DDRDATA8CH1_CR_TXTRAINRANK2_Spare0_WID                       ( 2)
+  #define DDRDATA8CH1_CR_TXTRAINRANK2_Spare0_MSK                       (0x000C0000)
+  #define DDRDATA8CH1_CR_TXTRAINRANK2_Spare0_MAX                       (0x00000003)
+  #define DDRDATA8CH1_CR_TXTRAINRANK2_TxEqualization_OFF               (20)
+  #define DDRDATA8CH1_CR_TXTRAINRANK2_TxEqualization_WID               ( 6)
+  #define DDRDATA8CH1_CR_TXTRAINRANK2_TxEqualization_MSK               (0x03F00000)
+  #define DDRDATA8CH1_CR_TXTRAINRANK2_TxEqualization_MAX               (0x0000003F)
+  #define DDRDATA8CH1_CR_TXTRAINRANK2_Spare1_OFF                       (26)
+  #define DDRDATA8CH1_CR_TXTRAINRANK2_Spare1_WID                       ( 6)
+  #define DDRDATA8CH1_CR_TXTRAINRANK2_Spare1_MSK                       (0xFC000000)
+  #define DDRDATA8CH1_CR_TXTRAINRANK2_Spare1_MAX                       (0x0000003F)
+
+#define DDRDATA8CH1_CR_TXTRAINRANK3_REG                              (0x0000112C)
+  #define DDRDATA8CH1_CR_TXTRAINRANK3_TxDqDelay_OFF                    ( 0)
+  #define DDRDATA8CH1_CR_TXTRAINRANK3_TxDqDelay_WID                    ( 9)
+  #define DDRDATA8CH1_CR_TXTRAINRANK3_TxDqDelay_MSK                    (0x000001FF)
+  #define DDRDATA8CH1_CR_TXTRAINRANK3_TxDqDelay_MAX                    (0x000001FF)
+  #define DDRDATA8CH1_CR_TXTRAINRANK3_TxDqsDelay_OFF                   ( 9)
+  #define DDRDATA8CH1_CR_TXTRAINRANK3_TxDqsDelay_WID                   ( 9)
+  #define DDRDATA8CH1_CR_TXTRAINRANK3_TxDqsDelay_MSK                   (0x0003FE00)
+  #define DDRDATA8CH1_CR_TXTRAINRANK3_TxDqsDelay_MAX                   (0x000001FF)
+  #define DDRDATA8CH1_CR_TXTRAINRANK3_Spare0_OFF                       (18)
+  #define DDRDATA8CH1_CR_TXTRAINRANK3_Spare0_WID                       ( 2)
+  #define DDRDATA8CH1_CR_TXTRAINRANK3_Spare0_MSK                       (0x000C0000)
+  #define DDRDATA8CH1_CR_TXTRAINRANK3_Spare0_MAX                       (0x00000003)
+  #define DDRDATA8CH1_CR_TXTRAINRANK3_TxEqualization_OFF               (20)
+  #define DDRDATA8CH1_CR_TXTRAINRANK3_TxEqualization_WID               ( 6)
+  #define DDRDATA8CH1_CR_TXTRAINRANK3_TxEqualization_MSK               (0x03F00000)
+  #define DDRDATA8CH1_CR_TXTRAINRANK3_TxEqualization_MAX               (0x0000003F)
+  #define DDRDATA8CH1_CR_TXTRAINRANK3_Spare1_OFF                       (26)
+  #define DDRDATA8CH1_CR_TXTRAINRANK3_Spare1_WID                       ( 6)
+  #define DDRDATA8CH1_CR_TXTRAINRANK3_Spare1_MSK                       (0xFC000000)
+  #define DDRDATA8CH1_CR_TXTRAINRANK3_Spare1_MAX                       (0x0000003F)
+
+#define DDRDATA8CH1_CR_TXPERBITRANK0_REG                             (0x00001130)
+  #define DDRDATA8CH1_CR_TXPERBITRANK0_Lane0_OFF                       ( 0)
+  #define DDRDATA8CH1_CR_TXPERBITRANK0_Lane0_WID                       ( 4)
+  #define DDRDATA8CH1_CR_TXPERBITRANK0_Lane0_MSK                       (0x0000000F)
+  #define DDRDATA8CH1_CR_TXPERBITRANK0_Lane0_MAX                       (0x0000000F)
+  #define DDRDATA8CH1_CR_TXPERBITRANK0_Lane1_OFF                       ( 4)
+  #define DDRDATA8CH1_CR_TXPERBITRANK0_Lane1_WID                       ( 4)
+  #define DDRDATA8CH1_CR_TXPERBITRANK0_Lane1_MSK                       (0x000000F0)
+  #define DDRDATA8CH1_CR_TXPERBITRANK0_Lane1_MAX                       (0x0000000F)
+  #define DDRDATA8CH1_CR_TXPERBITRANK0_Lane2_OFF                       ( 8)
+  #define DDRDATA8CH1_CR_TXPERBITRANK0_Lane2_WID                       ( 4)
+  #define DDRDATA8CH1_CR_TXPERBITRANK0_Lane2_MSK                       (0x00000F00)
+  #define DDRDATA8CH1_CR_TXPERBITRANK0_Lane2_MAX                       (0x0000000F)
+  #define DDRDATA8CH1_CR_TXPERBITRANK0_Lane3_OFF                       (12)
+  #define DDRDATA8CH1_CR_TXPERBITRANK0_Lane3_WID                       ( 4)
+  #define DDRDATA8CH1_CR_TXPERBITRANK0_Lane3_MSK                       (0x0000F000)
+  #define DDRDATA8CH1_CR_TXPERBITRANK0_Lane3_MAX                       (0x0000000F)
+  #define DDRDATA8CH1_CR_TXPERBITRANK0_Lane4_OFF                       (16)
+  #define DDRDATA8CH1_CR_TXPERBITRANK0_Lane4_WID                       ( 4)
+  #define DDRDATA8CH1_CR_TXPERBITRANK0_Lane4_MSK                       (0x000F0000)
+  #define DDRDATA8CH1_CR_TXPERBITRANK0_Lane4_MAX                       (0x0000000F)
+  #define DDRDATA8CH1_CR_TXPERBITRANK0_Lane5_OFF                       (20)
+  #define DDRDATA8CH1_CR_TXPERBITRANK0_Lane5_WID                       ( 4)
+  #define DDRDATA8CH1_CR_TXPERBITRANK0_Lane5_MSK                       (0x00F00000)
+  #define DDRDATA8CH1_CR_TXPERBITRANK0_Lane5_MAX                       (0x0000000F)
+  #define DDRDATA8CH1_CR_TXPERBITRANK0_Lane6_OFF                       (24)
+  #define DDRDATA8CH1_CR_TXPERBITRANK0_Lane6_WID                       ( 4)
+  #define DDRDATA8CH1_CR_TXPERBITRANK0_Lane6_MSK                       (0x0F000000)
+  #define DDRDATA8CH1_CR_TXPERBITRANK0_Lane6_MAX                       (0x0000000F)
+  #define DDRDATA8CH1_CR_TXPERBITRANK0_Lane7_OFF                       (28)
+  #define DDRDATA8CH1_CR_TXPERBITRANK0_Lane7_WID                       ( 4)
+  #define DDRDATA8CH1_CR_TXPERBITRANK0_Lane7_MSK                       (0xF0000000)
+  #define DDRDATA8CH1_CR_TXPERBITRANK0_Lane7_MAX                       (0x0000000F)
+
+#define DDRDATA8CH1_CR_TXPERBITRANK1_REG                             (0x00001134)
+  #define DDRDATA8CH1_CR_TXPERBITRANK1_Lane0_OFF                       ( 0)
+  #define DDRDATA8CH1_CR_TXPERBITRANK1_Lane0_WID                       ( 4)
+  #define DDRDATA8CH1_CR_TXPERBITRANK1_Lane0_MSK                       (0x0000000F)
+  #define DDRDATA8CH1_CR_TXPERBITRANK1_Lane0_MAX                       (0x0000000F)
+  #define DDRDATA8CH1_CR_TXPERBITRANK1_Lane1_OFF                       ( 4)
+  #define DDRDATA8CH1_CR_TXPERBITRANK1_Lane1_WID                       ( 4)
+  #define DDRDATA8CH1_CR_TXPERBITRANK1_Lane1_MSK                       (0x000000F0)
+  #define DDRDATA8CH1_CR_TXPERBITRANK1_Lane1_MAX                       (0x0000000F)
+  #define DDRDATA8CH1_CR_TXPERBITRANK1_Lane2_OFF                       ( 8)
+  #define DDRDATA8CH1_CR_TXPERBITRANK1_Lane2_WID                       ( 4)
+  #define DDRDATA8CH1_CR_TXPERBITRANK1_Lane2_MSK                       (0x00000F00)
+  #define DDRDATA8CH1_CR_TXPERBITRANK1_Lane2_MAX                       (0x0000000F)
+  #define DDRDATA8CH1_CR_TXPERBITRANK1_Lane3_OFF                       (12)
+  #define DDRDATA8CH1_CR_TXPERBITRANK1_Lane3_WID                       ( 4)
+  #define DDRDATA8CH1_CR_TXPERBITRANK1_Lane3_MSK                       (0x0000F000)
+  #define DDRDATA8CH1_CR_TXPERBITRANK1_Lane3_MAX                       (0x0000000F)
+  #define DDRDATA8CH1_CR_TXPERBITRANK1_Lane4_OFF                       (16)
+  #define DDRDATA8CH1_CR_TXPERBITRANK1_Lane4_WID                       ( 4)
+  #define DDRDATA8CH1_CR_TXPERBITRANK1_Lane4_MSK                       (0x000F0000)
+  #define DDRDATA8CH1_CR_TXPERBITRANK1_Lane4_MAX                       (0x0000000F)
+  #define DDRDATA8CH1_CR_TXPERBITRANK1_Lane5_OFF                       (20)
+  #define DDRDATA8CH1_CR_TXPERBITRANK1_Lane5_WID                       ( 4)
+  #define DDRDATA8CH1_CR_TXPERBITRANK1_Lane5_MSK                       (0x00F00000)
+  #define DDRDATA8CH1_CR_TXPERBITRANK1_Lane5_MAX                       (0x0000000F)
+  #define DDRDATA8CH1_CR_TXPERBITRANK1_Lane6_OFF                       (24)
+  #define DDRDATA8CH1_CR_TXPERBITRANK1_Lane6_WID                       ( 4)
+  #define DDRDATA8CH1_CR_TXPERBITRANK1_Lane6_MSK                       (0x0F000000)
+  #define DDRDATA8CH1_CR_TXPERBITRANK1_Lane6_MAX                       (0x0000000F)
+  #define DDRDATA8CH1_CR_TXPERBITRANK1_Lane7_OFF                       (28)
+  #define DDRDATA8CH1_CR_TXPERBITRANK1_Lane7_WID                       ( 4)
+  #define DDRDATA8CH1_CR_TXPERBITRANK1_Lane7_MSK                       (0xF0000000)
+  #define DDRDATA8CH1_CR_TXPERBITRANK1_Lane7_MAX                       (0x0000000F)
+
+#define DDRDATA8CH1_CR_TXPERBITRANK2_REG                             (0x00001138)
+  #define DDRDATA8CH1_CR_TXPERBITRANK2_Lane0_OFF                       ( 0)
+  #define DDRDATA8CH1_CR_TXPERBITRANK2_Lane0_WID                       ( 4)
+  #define DDRDATA8CH1_CR_TXPERBITRANK2_Lane0_MSK                       (0x0000000F)
+  #define DDRDATA8CH1_CR_TXPERBITRANK2_Lane0_MAX                       (0x0000000F)
+  #define DDRDATA8CH1_CR_TXPERBITRANK2_Lane1_OFF                       ( 4)
+  #define DDRDATA8CH1_CR_TXPERBITRANK2_Lane1_WID                       ( 4)
+  #define DDRDATA8CH1_CR_TXPERBITRANK2_Lane1_MSK                       (0x000000F0)
+  #define DDRDATA8CH1_CR_TXPERBITRANK2_Lane1_MAX                       (0x0000000F)
+  #define DDRDATA8CH1_CR_TXPERBITRANK2_Lane2_OFF                       ( 8)
+  #define DDRDATA8CH1_CR_TXPERBITRANK2_Lane2_WID                       ( 4)
+  #define DDRDATA8CH1_CR_TXPERBITRANK2_Lane2_MSK                       (0x00000F00)
+  #define DDRDATA8CH1_CR_TXPERBITRANK2_Lane2_MAX                       (0x0000000F)
+  #define DDRDATA8CH1_CR_TXPERBITRANK2_Lane3_OFF                       (12)
+  #define DDRDATA8CH1_CR_TXPERBITRANK2_Lane3_WID                       ( 4)
+  #define DDRDATA8CH1_CR_TXPERBITRANK2_Lane3_MSK                       (0x0000F000)
+  #define DDRDATA8CH1_CR_TXPERBITRANK2_Lane3_MAX                       (0x0000000F)
+  #define DDRDATA8CH1_CR_TXPERBITRANK2_Lane4_OFF                       (16)
+  #define DDRDATA8CH1_CR_TXPERBITRANK2_Lane4_WID                       ( 4)
+  #define DDRDATA8CH1_CR_TXPERBITRANK2_Lane4_MSK                       (0x000F0000)
+  #define DDRDATA8CH1_CR_TXPERBITRANK2_Lane4_MAX                       (0x0000000F)
+  #define DDRDATA8CH1_CR_TXPERBITRANK2_Lane5_OFF                       (20)
+  #define DDRDATA8CH1_CR_TXPERBITRANK2_Lane5_WID                       ( 4)
+  #define DDRDATA8CH1_CR_TXPERBITRANK2_Lane5_MSK                       (0x00F00000)
+  #define DDRDATA8CH1_CR_TXPERBITRANK2_Lane5_MAX                       (0x0000000F)
+  #define DDRDATA8CH1_CR_TXPERBITRANK2_Lane6_OFF                       (24)
+  #define DDRDATA8CH1_CR_TXPERBITRANK2_Lane6_WID                       ( 4)
+  #define DDRDATA8CH1_CR_TXPERBITRANK2_Lane6_MSK                       (0x0F000000)
+  #define DDRDATA8CH1_CR_TXPERBITRANK2_Lane6_MAX                       (0x0000000F)
+  #define DDRDATA8CH1_CR_TXPERBITRANK2_Lane7_OFF                       (28)
+  #define DDRDATA8CH1_CR_TXPERBITRANK2_Lane7_WID                       ( 4)
+  #define DDRDATA8CH1_CR_TXPERBITRANK2_Lane7_MSK                       (0xF0000000)
+  #define DDRDATA8CH1_CR_TXPERBITRANK2_Lane7_MAX                       (0x0000000F)
+
+#define DDRDATA8CH1_CR_TXPERBITRANK3_REG                             (0x0000113C)
+  #define DDRDATA8CH1_CR_TXPERBITRANK3_Lane0_OFF                       ( 0)
+  #define DDRDATA8CH1_CR_TXPERBITRANK3_Lane0_WID                       ( 4)
+  #define DDRDATA8CH1_CR_TXPERBITRANK3_Lane0_MSK                       (0x0000000F)
+  #define DDRDATA8CH1_CR_TXPERBITRANK3_Lane0_MAX                       (0x0000000F)
+  #define DDRDATA8CH1_CR_TXPERBITRANK3_Lane1_OFF                       ( 4)
+  #define DDRDATA8CH1_CR_TXPERBITRANK3_Lane1_WID                       ( 4)
+  #define DDRDATA8CH1_CR_TXPERBITRANK3_Lane1_MSK                       (0x000000F0)
+  #define DDRDATA8CH1_CR_TXPERBITRANK3_Lane1_MAX                       (0x0000000F)
+  #define DDRDATA8CH1_CR_TXPERBITRANK3_Lane2_OFF                       ( 8)
+  #define DDRDATA8CH1_CR_TXPERBITRANK3_Lane2_WID                       ( 4)
+  #define DDRDATA8CH1_CR_TXPERBITRANK3_Lane2_MSK                       (0x00000F00)
+  #define DDRDATA8CH1_CR_TXPERBITRANK3_Lane2_MAX                       (0x0000000F)
+  #define DDRDATA8CH1_CR_TXPERBITRANK3_Lane3_OFF                       (12)
+  #define DDRDATA8CH1_CR_TXPERBITRANK3_Lane3_WID                       ( 4)
+  #define DDRDATA8CH1_CR_TXPERBITRANK3_Lane3_MSK                       (0x0000F000)
+  #define DDRDATA8CH1_CR_TXPERBITRANK3_Lane3_MAX                       (0x0000000F)
+  #define DDRDATA8CH1_CR_TXPERBITRANK3_Lane4_OFF                       (16)
+  #define DDRDATA8CH1_CR_TXPERBITRANK3_Lane4_WID                       ( 4)
+  #define DDRDATA8CH1_CR_TXPERBITRANK3_Lane4_MSK                       (0x000F0000)
+  #define DDRDATA8CH1_CR_TXPERBITRANK3_Lane4_MAX                       (0x0000000F)
+  #define DDRDATA8CH1_CR_TXPERBITRANK3_Lane5_OFF                       (20)
+  #define DDRDATA8CH1_CR_TXPERBITRANK3_Lane5_WID                       ( 4)
+  #define DDRDATA8CH1_CR_TXPERBITRANK3_Lane5_MSK                       (0x00F00000)
+  #define DDRDATA8CH1_CR_TXPERBITRANK3_Lane5_MAX                       (0x0000000F)
+  #define DDRDATA8CH1_CR_TXPERBITRANK3_Lane6_OFF                       (24)
+  #define DDRDATA8CH1_CR_TXPERBITRANK3_Lane6_WID                       ( 4)
+  #define DDRDATA8CH1_CR_TXPERBITRANK3_Lane6_MSK                       (0x0F000000)
+  #define DDRDATA8CH1_CR_TXPERBITRANK3_Lane6_MAX                       (0x0000000F)
+  #define DDRDATA8CH1_CR_TXPERBITRANK3_Lane7_OFF                       (28)
+  #define DDRDATA8CH1_CR_TXPERBITRANK3_Lane7_WID                       ( 4)
+  #define DDRDATA8CH1_CR_TXPERBITRANK3_Lane7_MSK                       (0xF0000000)
+  #define DDRDATA8CH1_CR_TXPERBITRANK3_Lane7_MAX                       (0x0000000F)
+
+#define DDRDATA8CH1_CR_RCOMPDATA0_REG                                (0x00001140)
+  #define DDRDATA8CH1_CR_RCOMPDATA0_RcompDrvUp_OFF                     ( 0)
+  #define DDRDATA8CH1_CR_RCOMPDATA0_RcompDrvUp_WID                     ( 6)
+  #define DDRDATA8CH1_CR_RCOMPDATA0_RcompDrvUp_MSK                     (0x0000003F)
+  #define DDRDATA8CH1_CR_RCOMPDATA0_RcompDrvUp_MAX                     (0x0000003F)
+  #define DDRDATA8CH1_CR_RCOMPDATA0_Spare0_OFF                         ( 6)
+  #define DDRDATA8CH1_CR_RCOMPDATA0_Spare0_WID                         ( 3)
+  #define DDRDATA8CH1_CR_RCOMPDATA0_Spare0_MSK                         (0x000001C0)
+  #define DDRDATA8CH1_CR_RCOMPDATA0_Spare0_MAX                         (0x00000007)
+  #define DDRDATA8CH1_CR_RCOMPDATA0_RcompDrvDown_OFF                   ( 9)
+  #define DDRDATA8CH1_CR_RCOMPDATA0_RcompDrvDown_WID                   ( 6)
+  #define DDRDATA8CH1_CR_RCOMPDATA0_RcompDrvDown_MSK                   (0x00007E00)
+  #define DDRDATA8CH1_CR_RCOMPDATA0_RcompDrvDown_MAX                   (0x0000003F)
+  #define DDRDATA8CH1_CR_RCOMPDATA0_VTComp_OFF                         (15)
+  #define DDRDATA8CH1_CR_RCOMPDATA0_VTComp_WID                         ( 5)
+  #define DDRDATA8CH1_CR_RCOMPDATA0_VTComp_MSK                         (0x000F8000)
+  #define DDRDATA8CH1_CR_RCOMPDATA0_VTComp_MAX                         (0x0000001F)
+  #define DDRDATA8CH1_CR_RCOMPDATA0_TcoComp_OFF                        (20)
+  #define DDRDATA8CH1_CR_RCOMPDATA0_TcoComp_WID                        ( 6)
+  #define DDRDATA8CH1_CR_RCOMPDATA0_TcoComp_MSK                        (0x03F00000)
+  #define DDRDATA8CH1_CR_RCOMPDATA0_TcoComp_MAX                        (0x0000003F)
+  #define DDRDATA8CH1_CR_RCOMPDATA0_SlewRateComp_OFF                   (26)
+  #define DDRDATA8CH1_CR_RCOMPDATA0_SlewRateComp_WID                   ( 5)
+  #define DDRDATA8CH1_CR_RCOMPDATA0_SlewRateComp_MSK                   (0x7C000000)
+  #define DDRDATA8CH1_CR_RCOMPDATA0_SlewRateComp_MAX                   (0x0000001F)
+  #define DDRDATA8CH1_CR_RCOMPDATA0_Spare2_OFF                         (31)
+  #define DDRDATA8CH1_CR_RCOMPDATA0_Spare2_WID                         ( 1)
+  #define DDRDATA8CH1_CR_RCOMPDATA0_Spare2_MSK                         (0x80000000)
+  #define DDRDATA8CH1_CR_RCOMPDATA0_Spare2_MAX                         (0x00000001)
+
+#define DDRDATA8CH1_CR_RCOMPDATA1_REG                                (0x00001144)
+  #define DDRDATA8CH1_CR_RCOMPDATA1_RcompOdtUp_OFF                     ( 0)
+  #define DDRDATA8CH1_CR_RCOMPDATA1_RcompOdtUp_WID                     ( 6)
+  #define DDRDATA8CH1_CR_RCOMPDATA1_RcompOdtUp_MSK                     (0x0000003F)
+  #define DDRDATA8CH1_CR_RCOMPDATA1_RcompOdtUp_MAX                     (0x0000003F)
+  #define DDRDATA8CH1_CR_RCOMPDATA1_Spare0_OFF                         ( 6)
+  #define DDRDATA8CH1_CR_RCOMPDATA1_Spare0_WID                         ( 3)
+  #define DDRDATA8CH1_CR_RCOMPDATA1_Spare0_MSK                         (0x000001C0)
+  #define DDRDATA8CH1_CR_RCOMPDATA1_Spare0_MAX                         (0x00000007)
+  #define DDRDATA8CH1_CR_RCOMPDATA1_RcompOdtDown_OFF                   ( 9)
+  #define DDRDATA8CH1_CR_RCOMPDATA1_RcompOdtDown_WID                   ( 6)
+  #define DDRDATA8CH1_CR_RCOMPDATA1_RcompOdtDown_MSK                   (0x00007E00)
+  #define DDRDATA8CH1_CR_RCOMPDATA1_RcompOdtDown_MAX                   (0x0000003F)
+  #define DDRDATA8CH1_CR_RCOMPDATA1_Spare1_OFF                         (15)
+  #define DDRDATA8CH1_CR_RCOMPDATA1_Spare1_WID                         ( 1)
+  #define DDRDATA8CH1_CR_RCOMPDATA1_Spare1_MSK                         (0x00008000)
+  #define DDRDATA8CH1_CR_RCOMPDATA1_Spare1_MAX                         (0x00000001)
+  #define DDRDATA8CH1_CR_RCOMPDATA1_PanicDrvDn_OFF                     (16)
+  #define DDRDATA8CH1_CR_RCOMPDATA1_PanicDrvDn_WID                     ( 6)
+  #define DDRDATA8CH1_CR_RCOMPDATA1_PanicDrvDn_MSK                     (0x003F0000)
+  #define DDRDATA8CH1_CR_RCOMPDATA1_PanicDrvDn_MAX                     (0x0000003F)
+  #define DDRDATA8CH1_CR_RCOMPDATA1_PanicDrvUp_OFF                     (22)
+  #define DDRDATA8CH1_CR_RCOMPDATA1_PanicDrvUp_WID                     ( 6)
+  #define DDRDATA8CH1_CR_RCOMPDATA1_PanicDrvUp_MSK                     (0x0FC00000)
+  #define DDRDATA8CH1_CR_RCOMPDATA1_PanicDrvUp_MAX                     (0x0000003F)
+  #define DDRDATA8CH1_CR_RCOMPDATA1_LevelShifterComp_OFF               (28)
+  #define DDRDATA8CH1_CR_RCOMPDATA1_LevelShifterComp_WID               ( 3)
+  #define DDRDATA8CH1_CR_RCOMPDATA1_LevelShifterComp_MSK               (0x70000000)
+  #define DDRDATA8CH1_CR_RCOMPDATA1_LevelShifterComp_MAX               (0x00000007)
+  #define DDRDATA8CH1_CR_RCOMPDATA1_Spare2_OFF                         (31)
+  #define DDRDATA8CH1_CR_RCOMPDATA1_Spare2_WID                         ( 1)
+  #define DDRDATA8CH1_CR_RCOMPDATA1_Spare2_MSK                         (0x80000000)
+  #define DDRDATA8CH1_CR_RCOMPDATA1_Spare2_MAX                         (0x00000001)
+
+#define DDRDATA8CH1_CR_TXXTALK_REG                                   (0x00001148)
+  #define DDRDATA8CH1_CR_TXXTALK_Lane0_OFF                             ( 0)
+  #define DDRDATA8CH1_CR_TXXTALK_Lane0_WID                             ( 4)
+  #define DDRDATA8CH1_CR_TXXTALK_Lane0_MSK                             (0x0000000F)
+  #define DDRDATA8CH1_CR_TXXTALK_Lane0_MAX                             (0x0000000F)
+  #define DDRDATA8CH1_CR_TXXTALK_Lane1_OFF                             ( 4)
+  #define DDRDATA8CH1_CR_TXXTALK_Lane1_WID                             ( 4)
+  #define DDRDATA8CH1_CR_TXXTALK_Lane1_MSK                             (0x000000F0)
+  #define DDRDATA8CH1_CR_TXXTALK_Lane1_MAX                             (0x0000000F)
+  #define DDRDATA8CH1_CR_TXXTALK_Lane2_OFF                             ( 8)
+  #define DDRDATA8CH1_CR_TXXTALK_Lane2_WID                             ( 4)
+  #define DDRDATA8CH1_CR_TXXTALK_Lane2_MSK                             (0x00000F00)
+  #define DDRDATA8CH1_CR_TXXTALK_Lane2_MAX                             (0x0000000F)
+  #define DDRDATA8CH1_CR_TXXTALK_Lane3_OFF                             (12)
+  #define DDRDATA8CH1_CR_TXXTALK_Lane3_WID                             ( 4)
+  #define DDRDATA8CH1_CR_TXXTALK_Lane3_MSK                             (0x0000F000)
+  #define DDRDATA8CH1_CR_TXXTALK_Lane3_MAX                             (0x0000000F)
+  #define DDRDATA8CH1_CR_TXXTALK_Lane4_OFF                             (16)
+  #define DDRDATA8CH1_CR_TXXTALK_Lane4_WID                             ( 4)
+  #define DDRDATA8CH1_CR_TXXTALK_Lane4_MSK                             (0x000F0000)
+  #define DDRDATA8CH1_CR_TXXTALK_Lane4_MAX                             (0x0000000F)
+  #define DDRDATA8CH1_CR_TXXTALK_Lane5_OFF                             (20)
+  #define DDRDATA8CH1_CR_TXXTALK_Lane5_WID                             ( 4)
+  #define DDRDATA8CH1_CR_TXXTALK_Lane5_MSK                             (0x00F00000)
+  #define DDRDATA8CH1_CR_TXXTALK_Lane5_MAX                             (0x0000000F)
+  #define DDRDATA8CH1_CR_TXXTALK_Lane6_OFF                             (24)
+  #define DDRDATA8CH1_CR_TXXTALK_Lane6_WID                             ( 4)
+  #define DDRDATA8CH1_CR_TXXTALK_Lane6_MSK                             (0x0F000000)
+  #define DDRDATA8CH1_CR_TXXTALK_Lane6_MAX                             (0x0000000F)
+  #define DDRDATA8CH1_CR_TXXTALK_Lane7_OFF                             (28)
+  #define DDRDATA8CH1_CR_TXXTALK_Lane7_WID                             ( 4)
+  #define DDRDATA8CH1_CR_TXXTALK_Lane7_MSK                             (0xF0000000)
+  #define DDRDATA8CH1_CR_TXXTALK_Lane7_MAX                             (0x0000000F)
+
+#define DDRDATA8CH1_CR_RXOFFSETVDQ_REG                               (0x0000114C)
+  #define DDRDATA8CH1_CR_RXOFFSETVDQ_Lane0_OFF                         ( 0)
+  #define DDRDATA8CH1_CR_RXOFFSETVDQ_Lane0_WID                         ( 4)
+  #define DDRDATA8CH1_CR_RXOFFSETVDQ_Lane0_MSK                         (0x0000000F)
+  #define DDRDATA8CH1_CR_RXOFFSETVDQ_Lane0_MAX                         (0x0000000F)
+  #define DDRDATA8CH1_CR_RXOFFSETVDQ_Lane1_OFF                         ( 4)
+  #define DDRDATA8CH1_CR_RXOFFSETVDQ_Lane1_WID                         ( 4)
+  #define DDRDATA8CH1_CR_RXOFFSETVDQ_Lane1_MSK                         (0x000000F0)
+  #define DDRDATA8CH1_CR_RXOFFSETVDQ_Lane1_MAX                         (0x0000000F)
+  #define DDRDATA8CH1_CR_RXOFFSETVDQ_Lane2_OFF                         ( 8)
+  #define DDRDATA8CH1_CR_RXOFFSETVDQ_Lane2_WID                         ( 4)
+  #define DDRDATA8CH1_CR_RXOFFSETVDQ_Lane2_MSK                         (0x00000F00)
+  #define DDRDATA8CH1_CR_RXOFFSETVDQ_Lane2_MAX                         (0x0000000F)
+  #define DDRDATA8CH1_CR_RXOFFSETVDQ_Lane3_OFF                         (12)
+  #define DDRDATA8CH1_CR_RXOFFSETVDQ_Lane3_WID                         ( 4)
+  #define DDRDATA8CH1_CR_RXOFFSETVDQ_Lane3_MSK                         (0x0000F000)
+  #define DDRDATA8CH1_CR_RXOFFSETVDQ_Lane3_MAX                         (0x0000000F)
+  #define DDRDATA8CH1_CR_RXOFFSETVDQ_Lane4_OFF                         (16)
+  #define DDRDATA8CH1_CR_RXOFFSETVDQ_Lane4_WID                         ( 4)
+  #define DDRDATA8CH1_CR_RXOFFSETVDQ_Lane4_MSK                         (0x000F0000)
+  #define DDRDATA8CH1_CR_RXOFFSETVDQ_Lane4_MAX                         (0x0000000F)
+  #define DDRDATA8CH1_CR_RXOFFSETVDQ_Lane5_OFF                         (20)
+  #define DDRDATA8CH1_CR_RXOFFSETVDQ_Lane5_WID                         ( 4)
+  #define DDRDATA8CH1_CR_RXOFFSETVDQ_Lane5_MSK                         (0x00F00000)
+  #define DDRDATA8CH1_CR_RXOFFSETVDQ_Lane5_MAX                         (0x0000000F)
+  #define DDRDATA8CH1_CR_RXOFFSETVDQ_Lane6_OFF                         (24)
+  #define DDRDATA8CH1_CR_RXOFFSETVDQ_Lane6_WID                         ( 4)
+  #define DDRDATA8CH1_CR_RXOFFSETVDQ_Lane6_MSK                         (0x0F000000)
+  #define DDRDATA8CH1_CR_RXOFFSETVDQ_Lane6_MAX                         (0x0000000F)
+  #define DDRDATA8CH1_CR_RXOFFSETVDQ_Lane7_OFF                         (28)
+  #define DDRDATA8CH1_CR_RXOFFSETVDQ_Lane7_WID                         ( 4)
+  #define DDRDATA8CH1_CR_RXOFFSETVDQ_Lane7_MSK                         (0xF0000000)
+  #define DDRDATA8CH1_CR_RXOFFSETVDQ_Lane7_MAX                         (0x0000000F)
+
+#define DDRDATA8CH1_CR_DDRDATARESERVED_REG                           (0x00001150)
+  #define DDRDATA8CH1_CR_DDRDATARESERVED_Spare_OFF                     ( 0)
+  #define DDRDATA8CH1_CR_DDRDATARESERVED_Spare_WID                     (32)
+  #define DDRDATA8CH1_CR_DDRDATARESERVED_Spare_MSK                     (0xFFFFFFFF)
+  #define DDRDATA8CH1_CR_DDRDATARESERVED_Spare_MAX                     (0xFFFFFFFF)
+
+#define DDRDATA8CH1_CR_DATATRAINFEEDBACK_REG                         (0x00001154)
+  #define DDRDATA8CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_OFF       ( 0)
+  #define DDRDATA8CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_WID       ( 9)
+  #define DDRDATA8CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_MSK       (0x000001FF)
+  #define DDRDATA8CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_MAX       (0x000001FF)
+  #define DDRDATA8CH1_CR_DATATRAINFEEDBACK_Spare_OFF                   ( 9)
+  #define DDRDATA8CH1_CR_DATATRAINFEEDBACK_Spare_WID                   (23)
+  #define DDRDATA8CH1_CR_DATATRAINFEEDBACK_Spare_MSK                   (0xFFFFFE00)
+  #define DDRDATA8CH1_CR_DATATRAINFEEDBACK_Spare_MAX                   (0x007FFFFF)
+
+#define DDRDATA8CH1_CR_DLLPITESTANDADC_REG                           (0x00001158)
+  #define DDRDATA8CH1_CR_DLLPITESTANDADC_RunTest_OFF                   ( 0)
+  #define DDRDATA8CH1_CR_DLLPITESTANDADC_RunTest_WID                   ( 1)
+  #define DDRDATA8CH1_CR_DLLPITESTANDADC_RunTest_MSK                   (0x00000001)
+  #define DDRDATA8CH1_CR_DLLPITESTANDADC_RunTest_MAX                   (0x00000001)
+  #define DDRDATA8CH1_CR_DLLPITESTANDADC_RunTest_DEF                   (0x00000000)
+  #define DDRDATA8CH1_CR_DLLPITESTANDADC_Load_OFF                      ( 1)
+  #define DDRDATA8CH1_CR_DLLPITESTANDADC_Load_WID                      ( 1)
+  #define DDRDATA8CH1_CR_DLLPITESTANDADC_Load_MSK                      (0x00000002)
+  #define DDRDATA8CH1_CR_DLLPITESTANDADC_Load_MAX                      (0x00000001)
+  #define DDRDATA8CH1_CR_DLLPITESTANDADC_Load_DEF                      (0x00000000)
+  #define DDRDATA8CH1_CR_DLLPITESTANDADC_ModeHVM_OFF                   ( 2)
+  #define DDRDATA8CH1_CR_DLLPITESTANDADC_ModeHVM_WID                   ( 1)
+  #define DDRDATA8CH1_CR_DLLPITESTANDADC_ModeHVM_MSK                   (0x00000004)
+  #define DDRDATA8CH1_CR_DLLPITESTANDADC_ModeHVM_MAX                   (0x00000001)
+  #define DDRDATA8CH1_CR_DLLPITESTANDADC_ModeHVM_DEF                   (0x00000000)
+  #define DDRDATA8CH1_CR_DLLPITESTANDADC_ModeDV_OFF                    ( 3)
+  #define DDRDATA8CH1_CR_DLLPITESTANDADC_ModeDV_WID                    ( 1)
+  #define DDRDATA8CH1_CR_DLLPITESTANDADC_ModeDV_MSK                    (0x00000008)
+  #define DDRDATA8CH1_CR_DLLPITESTANDADC_ModeDV_MAX                    (0x00000001)
+  #define DDRDATA8CH1_CR_DLLPITESTANDADC_ModeDV_DEF                    (0x00000000)
+  #define DDRDATA8CH1_CR_DLLPITESTANDADC_ModeADC_OFF                   ( 4)
+  #define DDRDATA8CH1_CR_DLLPITESTANDADC_ModeADC_WID                   ( 1)
+  #define DDRDATA8CH1_CR_DLLPITESTANDADC_ModeADC_MSK                   (0x00000010)
+  #define DDRDATA8CH1_CR_DLLPITESTANDADC_ModeADC_MAX                   (0x00000001)
+  #define DDRDATA8CH1_CR_DLLPITESTANDADC_ModeADC_DEF                   (0x00000000)
+  #define DDRDATA8CH1_CR_DLLPITESTANDADC_LoadCount_OFF                 ( 5)
+  #define DDRDATA8CH1_CR_DLLPITESTANDADC_LoadCount_WID                 (10)
+  #define DDRDATA8CH1_CR_DLLPITESTANDADC_LoadCount_MSK                 (0x00007FE0)
+  #define DDRDATA8CH1_CR_DLLPITESTANDADC_LoadCount_MAX                 (0x000003FF)
+  #define DDRDATA8CH1_CR_DLLPITESTANDADC_CountStatus_OFF               (15)
+  #define DDRDATA8CH1_CR_DLLPITESTANDADC_CountStatus_WID               (10)
+  #define DDRDATA8CH1_CR_DLLPITESTANDADC_CountStatus_MSK               (0x01FF8000)
+  #define DDRDATA8CH1_CR_DLLPITESTANDADC_CountStatus_MAX               (0x000003FF)
+  #define DDRDATA8CH1_CR_DLLPITESTANDADC_CountStatus_DEF               (0x00000000)
+  #define DDRDATA8CH1_CR_DLLPITESTANDADC_Spare_OFF                     (25)
+  #define DDRDATA8CH1_CR_DLLPITESTANDADC_Spare_WID                     ( 7)
+  #define DDRDATA8CH1_CR_DLLPITESTANDADC_Spare_MSK                     (0xFE000000)
+  #define DDRDATA8CH1_CR_DLLPITESTANDADC_Spare_MAX                     (0x0000007F)
+
+#define DDRDATA8CH1_CR_DDRCRDATAOFFSETCOMP_REG                       (0x0000115C)
+  #define DDRDATA8CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_OFF     ( 0)
+  #define DDRDATA8CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_WID     ( 6)
+  #define DDRDATA8CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MSK     (0x0000003F)
+  #define DDRDATA8CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MAX     (0x0000003F)
+  #define DDRDATA8CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_DEF     (0x00000000)
+  #define DDRDATA8CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_OFF   ( 6)
+  #define DDRDATA8CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_WID   ( 6)
+  #define DDRDATA8CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MSK   (0x00000FC0)
+  #define DDRDATA8CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MAX   (0x0000003F)
+  #define DDRDATA8CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_DEF   (0x00000000)
+  #define DDRDATA8CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_OFF     (12)
+  #define DDRDATA8CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_WID     ( 5)
+  #define DDRDATA8CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MSK     (0x0001F000)
+  #define DDRDATA8CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MAX     (0x0000001F)
+  #define DDRDATA8CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_DEF     (0x00000000)
+  #define DDRDATA8CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_OFF   (17)
+  #define DDRDATA8CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_WID   ( 5)
+  #define DDRDATA8CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MSK   (0x003E0000)
+  #define DDRDATA8CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MAX   (0x0000001F)
+  #define DDRDATA8CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_DEF   (0x00000000)
+  #define DDRDATA8CH1_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_OFF       (22)
+  #define DDRDATA8CH1_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_WID       ( 5)
+  #define DDRDATA8CH1_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_MSK       (0x07C00000)
+  #define DDRDATA8CH1_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_MAX       (0x0000001F)
+  #define DDRDATA8CH1_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_DEF       (0x00000000)
+  #define DDRDATA8CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_OFF  (27)
+  #define DDRDATA8CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_WID  ( 5)
+  #define DDRDATA8CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MSK  (0xF8000000)
+  #define DDRDATA8CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MAX  (0x0000001F)
+  #define DDRDATA8CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_DEF  (0x00000000)
+
+#define DDRDATA8CH1_CR_DDRCRDATACONTROL1_REG                         (0x00001160)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_RefPi_OFF                   ( 0)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_RefPi_WID                   ( 4)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_RefPi_MSK                   (0x0000000F)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_RefPi_MAX                   (0x0000000F)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_RefPi_DEF                   (0x00000000)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_DllMask_OFF                 ( 4)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_DllMask_WID                 ( 2)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_DllMask_MSK                 (0x00000030)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_DllMask_MAX                 (0x00000003)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_DllMask_DEF                 (0x00000000)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_DllWeakLock_OFF             ( 6)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_DllWeakLock_WID             ( 1)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_DllWeakLock_MSK             (0x00000040)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_DllWeakLock_MAX             (0x00000001)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_DllWeakLock_DEF             (0x00000000)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_OFF      ( 7)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_WID      ( 3)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MSK      (0x00000380)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MAX      (0x00000007)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_DEF      (0x00000000)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_OFF               (10)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_WID               ( 3)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_MSK               (0x00001C00)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_MAX               (0x00000007)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_DEF               (0x00000000)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_OdtDelay_OFF                (13)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_OdtDelay_WID                ( 4)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_OdtDelay_MSK                (0x0001E000)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_OdtDelay_MAX                (0x0000000F)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_OdtDelay_DEF                (0x00000000)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_OdtDuration_OFF             (17)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_OdtDuration_WID             ( 3)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_OdtDuration_MSK             (0x000E0000)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_OdtDuration_MAX             (0x00000007)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_OdtDuration_DEF             (0x00000000)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_OFF           (20)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_WID           ( 4)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_MSK           (0x00F00000)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_MAX           (0x0000000F)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_DEF           (0x00000000)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_OFF        (24)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_WID        ( 3)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_MSK        (0x07000000)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_MAX        (0x00000007)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_DEF        (0x00000000)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_BurstEndODTDelay_OFF        (27)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_BurstEndODTDelay_WID        ( 3)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_BurstEndODTDelay_MSK        (0x38000000)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_BurstEndODTDelay_MAX        (0x00000007)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_BurstEndODTDelay_DEF        (0x00000000)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_OFF          (30)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_WID          ( 1)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_MSK          (0x40000000)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_MAX          (0x00000001)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_DEF          (0x00000000)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_Rsvd1_OFF                   (31)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_Rsvd1_WID                   ( 1)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_Rsvd1_MSK                   (0x80000000)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_Rsvd1_MAX                   (0x00000001)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_Rsvd1_DEF                   (0x00000000)
+
+#define DDRDATA8CH1_CR_DDRCRDATACONTROL2_REG                         (0x00001164)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_OFF            ( 0)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_WID            ( 5)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_MSK            (0x0000001F)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_MAX            (0x0000001F)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_DEF            (0x00000000)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_OFF             ( 5)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_WID             ( 1)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_MSK             (0x00000020)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_MAX             (0x00000001)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_DEF             (0x00000000)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_ForceRxOn_OFF               ( 6)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_ForceRxOn_WID               ( 1)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_ForceRxOn_MSK               (0x00000040)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_ForceRxOn_MAX               (0x00000001)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_ForceRxOn_DEF               (0x00000000)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_LeakerComp_OFF              ( 7)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_LeakerComp_WID              ( 2)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_LeakerComp_MSK              (0x00000180)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_LeakerComp_MAX              (0x00000003)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_LeakerComp_DEF              (0x00000000)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_OFF          ( 9)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_WID          ( 4)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_MSK          (0x00001E00)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_MAX          (0x0000000F)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_DEF          (0x00000008)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_OFF             (13)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_WID             ( 5)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_MSK             (0x0003E000)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_MAX             (0x0000001F)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_DEF             (0x00000011)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_OFF             (18)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_WID             ( 1)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_MSK             (0x00040000)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_MAX             (0x00000001)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_DEF             (0x00000000)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_Spare_OFF                   (19)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_Spare_WID                   (13)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_Spare_MSK                   (0xFFF80000)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_Spare_MAX                   (0x00001FFF)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_Spare_DEF                   (0x00000000)
+
+#define DDRDATA8CH1_CR_DDRCRVSSHIORVREFCONTROL_REG                   (0x0000116C)
+  #define DDRDATA8CH1_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_OFF    ( 0)
+  #define DDRDATA8CH1_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_WID    (24)
+  #define DDRDATA8CH1_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_MSK    (0x00FFFFFF)
+  #define DDRDATA8CH1_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_MAX    (0x00FFFFFF)
+  #define DDRDATA8CH1_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_DEF    (0x00000000)
+  #define DDRDATA8CH1_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_OFF        (24)
+  #define DDRDATA8CH1_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_WID        ( 8)
+  #define DDRDATA8CH1_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_MSK        (0xFF000000)
+  #define DDRDATA8CH1_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_MAX        (0x000000FF)
+  #define DDRDATA8CH1_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_DEF        (0x00000000)
+
+#define DDRDATA8CH1_CR_DDRCRDATAOFFSETTRAIN_REG                      (0x00001170)
+  #define DDRDATA8CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_OFF          ( 0)
+  #define DDRDATA8CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_WID          ( 6)
+  #define DDRDATA8CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MSK          (0x0000003F)
+  #define DDRDATA8CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MAX          (0x0000003F)
+  #define DDRDATA8CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_DEF          (0x00000000)
+  #define DDRDATA8CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_OFF          ( 6)
+  #define DDRDATA8CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_WID          ( 6)
+  #define DDRDATA8CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MSK          (0x00000FC0)
+  #define DDRDATA8CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MAX          (0x0000003F)
+  #define DDRDATA8CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_DEF          (0x00000000)
+  #define DDRDATA8CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_OFF           (12)
+  #define DDRDATA8CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_WID           ( 6)
+  #define DDRDATA8CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MSK           (0x0003F000)
+  #define DDRDATA8CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MAX           (0x0000003F)
+  #define DDRDATA8CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_DEF           (0x00000000)
+  #define DDRDATA8CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_OFF          (18)
+  #define DDRDATA8CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_WID          ( 6)
+  #define DDRDATA8CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MSK          (0x00FC0000)
+  #define DDRDATA8CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MAX          (0x0000003F)
+  #define DDRDATA8CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_DEF          (0x00000000)
+  #define DDRDATA8CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_OFF           (24)
+  #define DDRDATA8CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_WID           ( 7)
+  #define DDRDATA8CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MSK           (0x7F000000)
+  #define DDRDATA8CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MAX           (0x0000007F)
+  #define DDRDATA8CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_DEF           (0x00000000)
+  #define DDRDATA8CH1_CR_DDRCRDATAOFFSETTRAIN_Spare_OFF                (31)
+  #define DDRDATA8CH1_CR_DDRCRDATAOFFSETTRAIN_Spare_WID                ( 1)
+  #define DDRDATA8CH1_CR_DDRCRDATAOFFSETTRAIN_Spare_MSK                (0x80000000)
+  #define DDRDATA8CH1_CR_DDRCRDATAOFFSETTRAIN_Spare_MAX                (0x00000001)
+  #define DDRDATA8CH1_CR_DDRCRDATAOFFSETTRAIN_Spare_DEF                (0x00000000)
+
+#define DDRDATA8CH1_CR_DDRCRDATACONTROL0_REG                         (0x00001174)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_OFF          ( 0)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_WID          ( 1)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_MSK          (0x00000001)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_MAX          (0x00000001)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_DEF          (0x00000000)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_OFF          ( 1)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_WID          ( 1)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_MSK          (0x00000002)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_MAX          (0x00000001)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_DEF          (0x00000000)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_OFF          ( 2)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_WID          ( 1)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_MSK          (0x00000004)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_MAX          (0x00000001)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_DEF          (0x00000000)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_OFF    ( 3)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_WID    ( 1)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MSK    (0x00000008)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MAX    (0x00000001)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_DEF    (0x00000000)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_TxOn_OFF                    ( 4)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_TxOn_WID                    ( 1)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_TxOn_MSK                    (0x00000010)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_TxOn_MAX                    (0x00000001)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_TxOn_DEF                    (0x00000000)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RfOn_OFF                    ( 5)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RfOn_WID                    ( 1)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RfOn_MSK                    (0x00000020)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RfOn_MAX                    (0x00000001)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RfOn_DEF                    (0x00000000)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RxPiOn_OFF                  ( 6)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RxPiOn_WID                  ( 1)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RxPiOn_MSK                  (0x00000040)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RxPiOn_MAX                  (0x00000001)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RxPiOn_DEF                  (0x00000000)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_TxPiOn_OFF                  ( 7)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_TxPiOn_WID                  ( 1)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_TxPiOn_MSK                  (0x00000080)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_TxPiOn_MAX                  (0x00000001)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_TxPiOn_DEF                  (0x00000000)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_OFF        ( 8)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_WID        ( 1)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_MSK        (0x00000100)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_MAX        (0x00000001)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_DEF        (0x00000000)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_OFF        ( 9)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_WID        ( 1)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MSK        (0x00000200)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MAX        (0x00000001)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_DEF        (0x00000000)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_TxDisable_OFF               (10)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_TxDisable_WID               ( 1)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_TxDisable_MSK               (0x00000400)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_TxDisable_MAX               (0x00000001)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_TxDisable_DEF               (0x00000000)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RxDisable_OFF               (11)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RxDisable_WID               ( 1)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RxDisable_MSK               (0x00000800)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RxDisable_MAX               (0x00000001)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RxDisable_DEF               (0x00000000)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_TxLong_OFF                  (12)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_TxLong_WID                  ( 1)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_TxLong_MSK                  (0x00001000)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_TxLong_MAX                  (0x00000001)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_TxLong_DEF                  (0x00000000)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_OFF               (13)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_WID               ( 2)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_MSK               (0x00006000)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_MAX               (0x00000003)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_DEF               (0x00000000)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RxReadPointer_OFF           (15)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RxReadPointer_WID           ( 3)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RxReadPointer_MSK           (0x00038000)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RxReadPointer_MAX           (0x00000007)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RxReadPointer_DEF           (0x00000000)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_DriverSegmentEnable_OFF     (18)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_DriverSegmentEnable_WID     ( 1)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_DriverSegmentEnable_MSK     (0x00040000)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_DriverSegmentEnable_MAX     (0x00000001)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_DriverSegmentEnable_DEF     (0x00000000)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_DataVccddqHi_OFF            (19)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_DataVccddqHi_WID            ( 1)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_DataVccddqHi_MSK            (0x00080000)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_DataVccddqHi_MAX            (0x00000001)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_DataVccddqHi_DEF            (0x00000000)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_ReadRFRd_OFF                (20)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_ReadRFRd_WID                ( 1)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_ReadRFRd_MSK                (0x00100000)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_ReadRFRd_MAX                (0x00000001)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_ReadRFRd_DEF                (0x00000000)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_ReadRFWr_OFF                (21)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_ReadRFWr_WID                ( 1)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_ReadRFWr_MSK                (0x00200000)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_ReadRFWr_MAX                (0x00000001)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_ReadRFWr_DEF                (0x00000000)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_ReadRFRank_OFF              (22)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_ReadRFRank_WID              ( 2)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_ReadRFRank_MSK              (0x00C00000)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_ReadRFRank_MAX              (0x00000003)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_ReadRFRank_DEF              (0x00000000)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_OFF              (24)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_WID              ( 1)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_MSK              (0x01000000)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_MAX              (0x00000001)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_DEF              (0x00000000)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_OdtSampOff_OFF              (25)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_OdtSampOff_WID              ( 1)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_OdtSampOff_MSK              (0x02000000)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_OdtSampOff_MAX              (0x00000001)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_OdtSampOff_DEF              (0x00000000)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_OFF        (26)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_WID        ( 1)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_MSK        (0x04000000)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_MAX        (0x00000001)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_DEF        (0x00000000)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_OFF         (27)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_WID         ( 1)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MSK         (0x08000000)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MAX         (0x00000001)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_DEF         (0x00000000)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_OFF              (28)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_WID              ( 1)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_MSK              (0x10000000)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_MAX              (0x00000001)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_DEF              (0x00000000)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_EnReadPreamble_OFF          (29)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_EnReadPreamble_WID          ( 1)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_EnReadPreamble_MSK          (0x20000000)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_EnReadPreamble_MAX          (0x00000001)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_EnReadPreamble_DEF          (0x00000000)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_OFF         (30)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_WID         ( 1)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MSK         (0x40000000)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MAX         (0x00000001)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_DEF         (0x00000000)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_OFF            (31)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_WID            ( 1)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_MSK            (0x80000000)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_MAX            (0x00000001)
+  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_DEF            (0x00000000)
+
+#define DDRDATA8CH1_CR_DDRCRVREFADJUST1_REG                          (0x00001178)
+  #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_CAVrefCtl_OFF                ( 0)
+  #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_CAVrefCtl_WID                ( 7)
+  #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_CAVrefCtl_MSK                (0x0000007F)
+  #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_CAVrefCtl_MAX                (0x0000007F)
+  #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_CAVrefCtl_DEF                (0x00000000)
+  #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_Ch1VrefCtl_OFF               ( 7)
+  #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_Ch1VrefCtl_WID               ( 7)
+  #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_Ch1VrefCtl_MSK               (0x00003F80)
+  #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_Ch1VrefCtl_MAX               (0x0000007F)
+  #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_Ch1VrefCtl_DEF               (0x00000000)
+  #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_Ch0VrefCtl_OFF               (14)
+  #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_Ch0VrefCtl_WID               ( 7)
+  #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_Ch0VrefCtl_MSK               (0x001FC000)
+  #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_Ch0VrefCtl_MAX               (0x0000007F)
+  #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_Ch0VrefCtl_DEF               (0x00000000)
+  #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCA_OFF             (21)
+  #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCA_WID             ( 1)
+  #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCA_MSK             (0x00200000)
+  #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCA_MAX             (0x00000001)
+  #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCA_DEF             (0x00000000)
+  #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_OFF            (22)
+  #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_WID            ( 1)
+  #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_MSK            (0x00400000)
+  #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_MAX            (0x00000001)
+  #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_DEF            (0x00000000)
+  #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_OFF            (23)
+  #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_WID            ( 1)
+  #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_MSK            (0x00800000)
+  #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_MAX            (0x00000001)
+  #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_DEF            (0x00000000)
+  #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_HiZTimerCtrl_OFF             (24)
+  #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_HiZTimerCtrl_WID             ( 2)
+  #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_HiZTimerCtrl_MSK             (0x03000000)
+  #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_HiZTimerCtrl_MAX             (0x00000003)
+  #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_HiZTimerCtrl_DEF             (0x00000000)
+  #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_OFF            (26)
+  #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_WID            ( 1)
+  #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_MSK            (0x04000000)
+  #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_MAX            (0x00000001)
+  #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_DEF            (0x00000000)
+  #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_Rsvd_OFF                     (27)
+  #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_Rsvd_WID                     ( 2)
+  #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_Rsvd_MSK                     (0x18000000)
+  #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_Rsvd_MAX                     (0x00000003)
+  #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_Rsvd_DEF                     (0x00000000)
+  #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_caSlowBW_OFF                 (29)
+  #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_caSlowBW_WID                 ( 1)
+  #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_caSlowBW_MSK                 (0x20000000)
+  #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_caSlowBW_MAX                 (0x00000001)
+  #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_caSlowBW_DEF                 (0x00000000)
+  #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_ch0SlowBW_OFF                (30)
+  #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_ch0SlowBW_WID                ( 1)
+  #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_ch0SlowBW_MSK                (0x40000000)
+  #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_ch0SlowBW_MAX                (0x00000001)
+  #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_ch0SlowBW_DEF                (0x00000000)
+  #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_ch1SlowBW_OFF                (31)
+  #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_ch1SlowBW_WID                ( 1)
+  #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_ch1SlowBW_MSK                (0x80000000)
+  #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_ch1SlowBW_MAX                (0x00000001)
+  #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_ch1SlowBW_DEF                (0x00000000)
+
+#pragma pack(pop)
+#endif  // __McIoData_h__
diff --git a/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcRegisters/McMain.h b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcRegisters/McMain.h
new file mode 100644
index 0000000..fa1db62
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcRegisters/McMain.h
@@ -0,0 +1,19761 @@
+/** @file
+  This file was automatically generated. Modify at your own risk.
+
+@copyright
+  Copyright (c) 2010 - 2012 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement
+**/
+#ifndef __McMain_h__
+#define __McMain_h__
+
+#pragma pack(push, 1)
+#include "MrcTypes.h"
+
+typedef union {
+  struct {
+    U32 Global_Start_Test                       :  1;  // Bits 0:0
+    U32 Global_Stop_Test                        :  1;  // Bits 1:1
+    U32 Global_Clear_Errors                     :  1;  // Bits 2:2
+    U32                                         :  1;  // Bits 3:3
+    U32 Global_Stop_Test_On_Any_Error           :  1;  // Bits 4:4
+    U32                                         :  27;  // Bits 31:5
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCDFXS_CR_REUT_GLOBAL_CTL_MCMAIN_STRUCT;
+
+typedef union {
+  struct {
+    U32 Channel_Error_Status_0                  :  1;  // Bits 0:0
+    U32 Channel_Error_Status_1                  :  1;  // Bits 1:1
+    U32                                         :  14;  // Bits 15:2
+    U32 Channel_Test_Done_Status_0              :  1;  // Bits 16:16
+    U32 Channel_Test_Done_Status_1              :  1;  // Bits 17:17
+    U32                                         :  14;  // Bits 31:18
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCDFXS_CR_REUT_GLOBAL_ERR_MCMAIN_STRUCT;
+
+typedef union {
+  struct {
+    U32 Number_of_Cachelines                    :  7;  // Bits 6:0
+    U32 Number_of_Cachelines_Scale              :  1;  // Bits 7:7
+    U32 Subsequence_Wait                        :  10;  // Bits 17:8
+    U32                                         :  2;  // Bits 19:18
+    U32 Subsequence_Type                        :  4;  // Bits 23:20
+    U32                                         :  1;  // Bits 24:24
+    U32 Save_Current_Base_Address_To_Start      :  1;  // Bits 25:25
+    U32 Reset_Current_Base_Address_To_Start     :  1;  // Bits 26:26
+    U32 Data_and_ECC_Address_Inversion          :  2;  // Bits 28:27
+    U32                                         :  1;  // Bits 29:29
+    U32 Invert_Data_and_ECC                     :  1;  // Bits 30:30
+    U32 Stop_Base_Subsequence_On_Wrap_Trigger   :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_STRUCT_HSW_A0;
+
+typedef union {
+  struct {
+    U32 Number_of_Cachelines                    :  7;  // Bits 6:0
+    U32 Number_of_Cachelines_Scale              :  1;  // Bits 7:7
+    U32 Subsequence_Wait                        :  10;  // Bits 17:8
+    U32                                         :  2;  // Bits 19:18
+    U32 Subsequence_Type                        :  4;  // Bits 23:20
+    U32                                         :  1;  // Bits 24:24
+    U32 Save_Current_Base_Address_To_Start      :  1;  // Bits 25:25
+    U32 Reset_Current_Base_Address_To_Start     :  1;  // Bits 26:26
+    U32 Data_and_ECC_Address_Inversion          :  2;  // Bits 28:27
+    U32                                         :  1;  // Bits 29:29
+    U32 Invert_Data_and_ECC                     :  1;  // Bits 30:30
+    U32 Stop_Base_Subsequence_On_Wrap_Trigger   :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_STRUCT_HSW_A0;
+
+typedef union {
+  struct {
+    U32 Number_of_Cachelines                    :  7;  // Bits 6:0
+    U32 Number_of_Cachelines_Scale              :  1;  // Bits 7:7
+    U32 Subsequence_Wait                        :  10;  // Bits 17:8
+    U32                                         :  2;  // Bits 19:18
+    U32 Subsequence_Type                        :  4;  // Bits 23:20
+    U32                                         :  1;  // Bits 24:24
+    U32 Save_Current_Base_Address_To_Start      :  1;  // Bits 25:25
+    U32 Reset_Current_Base_Address_To_Start     :  1;  // Bits 26:26
+    U32 Data_and_ECC_Address_Inversion          :  2;  // Bits 28:27
+    U32                                         :  1;  // Bits 29:29
+    U32 Invert_Data_and_ECC                     :  1;  // Bits 30:30
+    U32 Stop_Base_Subsequence_On_Wrap_Trigger   :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_STRUCT_HSW_A0;
+
+typedef union {
+  struct {
+    U32 Number_of_Cachelines                    :  7;  // Bits 6:0
+    U32 Number_of_Cachelines_Scale              :  1;  // Bits 7:7
+    U32 Subsequence_Wait                        :  10;  // Bits 17:8
+    U32                                         :  2;  // Bits 19:18
+    U32 Subsequence_Type                        :  4;  // Bits 23:20
+    U32                                         :  1;  // Bits 24:24
+    U32 Save_Current_Base_Address_To_Start      :  1;  // Bits 25:25
+    U32 Reset_Current_Base_Address_To_Start     :  1;  // Bits 26:26
+    U32 Data_and_ECC_Address_Inversion          :  2;  // Bits 28:27
+    U32                                         :  1;  // Bits 29:29
+    U32 Invert_Data_and_ECC                     :  1;  // Bits 30:30
+    U32 Stop_Base_Subsequence_On_Wrap_Trigger   :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_STRUCT_HSW_A0;
+
+typedef union {
+  struct {
+    U32 Number_of_Cachelines                    :  7;  // Bits 6:0
+    U32 Number_of_Cachelines_Scale              :  1;  // Bits 7:7
+    U32 Subsequence_Wait                        :  10;  // Bits 17:8
+    U32                                         :  2;  // Bits 19:18
+    U32 Subsequence_Type                        :  4;  // Bits 23:20
+    U32                                         :  1;  // Bits 24:24
+    U32 Save_Current_Base_Address_To_Start      :  1;  // Bits 25:25
+    U32 Reset_Current_Base_Address_To_Start     :  1;  // Bits 26:26
+    U32 Data_and_ECC_Address_Inversion          :  2;  // Bits 28:27
+    U32                                         :  1;  // Bits 29:29
+    U32 Invert_Data_and_ECC                     :  1;  // Bits 30:30
+    U32 Stop_Base_Subsequence_On_Wrap_Trigger   :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_STRUCT_HSW_A0;
+
+typedef union {
+  struct {
+    U32 Number_of_Cachelines                    :  7;  // Bits 6:0
+    U32 Number_of_Cachelines_Scale              :  1;  // Bits 7:7
+    U32 Subsequence_Wait                        :  10;  // Bits 17:8
+    U32                                         :  2;  // Bits 19:18
+    U32 Subsequence_Type                        :  4;  // Bits 23:20
+    U32                                         :  1;  // Bits 24:24
+    U32 Save_Current_Base_Address_To_Start      :  1;  // Bits 25:25
+    U32 Reset_Current_Base_Address_To_Start     :  1;  // Bits 26:26
+    U32 Data_and_ECC_Address_Inversion          :  2;  // Bits 28:27
+    U32                                         :  1;  // Bits 29:29
+    U32 Invert_Data_and_ECC                     :  1;  // Bits 30:30
+    U32 Stop_Base_Subsequence_On_Wrap_Trigger   :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_STRUCT_HSW_A0;
+
+typedef union {
+  struct {
+    U32 Number_of_Cachelines                    :  7;  // Bits 6:0
+    U32 Number_of_Cachelines_Scale              :  1;  // Bits 7:7
+    U32 Subsequence_Wait                        :  10;  // Bits 17:8
+    U32                                         :  2;  // Bits 19:18
+    U32 Subsequence_Type                        :  4;  // Bits 23:20
+    U32                                         :  1;  // Bits 24:24
+    U32 Save_Current_Base_Address_To_Start      :  1;  // Bits 25:25
+    U32 Reset_Current_Base_Address_To_Start     :  1;  // Bits 26:26
+    U32 Data_and_ECC_Address_Inversion          :  2;  // Bits 28:27
+    U32                                         :  1;  // Bits 29:29
+    U32 Invert_Data_and_ECC                     :  1;  // Bits 30:30
+    U32 Stop_Base_Subsequence_On_Wrap_Trigger   :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_STRUCT_HSW_A0;
+
+typedef union {
+  struct {
+    U32 Number_of_Cachelines                    :  7;  // Bits 6:0
+    U32 Number_of_Cachelines_Scale              :  1;  // Bits 7:7
+    U32 Subsequence_Wait                        :  10;  // Bits 17:8
+    U32                                         :  2;  // Bits 19:18
+    U32 Subsequence_Type                        :  4;  // Bits 23:20
+    U32                                         :  1;  // Bits 24:24
+    U32 Save_Current_Base_Address_To_Start      :  1;  // Bits 25:25
+    U32 Reset_Current_Base_Address_To_Start     :  1;  // Bits 26:26
+    U32 Data_and_ECC_Address_Inversion          :  2;  // Bits 28:27
+    U32                                         :  1;  // Bits 29:29
+    U32 Invert_Data_and_ECC                     :  1;  // Bits 30:30
+    U32 Stop_Base_Subsequence_On_Wrap_Trigger   :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_STRUCT_HSW_A0;
+
+typedef union {
+  struct {
+    U32 Number_of_Cachelines                    :  7;  // Bits 6:0
+    U32 Number_of_Cachelines_Scale              :  1;  // Bits 7:7
+    U32 Subsequence_Wait                        :  8;  // Bits 15:8
+    U32                                         :  4;  // Bits 19:16
+    U32 Subsequence_Type                        :  4;  // Bits 23:20
+    U32                                         :  1;  // Bits 24:24
+    U32 Save_Current_Base_Address_To_Start      :  1;  // Bits 25:25
+    U32 Reset_Current_Base_Address_To_Start     :  1;  // Bits 26:26
+    U32 Data_and_ECC_Address_Inversion          :  2;  // Bits 28:27
+    U32                                         :  1;  // Bits 29:29
+    U32 Invert_Data_and_ECC                     :  1;  // Bits 30:30
+    U32 Stop_Base_Subsequence_On_Wrap_Trigger   :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_STRUCT_HSW_A0;
+
+typedef union {
+  struct {
+    U32 Number_of_Cachelines                    :  7;  // Bits 6:0
+    U32 Number_of_Cachelines_Scale              :  1;  // Bits 7:7
+    U32 Subsequence_Wait                        :  8;  // Bits 15:8
+    U32                                         :  4;  // Bits 19:16
+    U32 Subsequence_Type                        :  4;  // Bits 23:20
+    U32                                         :  1;  // Bits 24:24
+    U32 Save_Current_Base_Address_To_Start      :  1;  // Bits 25:25
+    U32 Reset_Current_Base_Address_To_Start     :  1;  // Bits 26:26
+    U32 Data_and_ECC_Address_Inversion          :  2;  // Bits 28:27
+    U32                                         :  1;  // Bits 29:29
+    U32 Invert_Data_and_ECC                     :  1;  // Bits 30:30
+    U32 Stop_Base_Subsequence_On_Wrap_Trigger   :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_STRUCT_HSW_A0;
+
+typedef union {
+  struct {
+    U32 Number_of_Cachelines                    :  7;  // Bits 6:0
+    U32 Number_of_Cachelines_Scale              :  1;  // Bits 7:7
+    U32 Subsequence_Wait                        :  8;  // Bits 15:8
+    U32                                         :  4;  // Bits 19:16
+    U32 Subsequence_Type                        :  4;  // Bits 23:20
+    U32                                         :  1;  // Bits 24:24
+    U32 Save_Current_Base_Address_To_Start      :  1;  // Bits 25:25
+    U32 Reset_Current_Base_Address_To_Start     :  1;  // Bits 26:26
+    U32 Data_and_ECC_Address_Inversion          :  2;  // Bits 28:27
+    U32                                         :  1;  // Bits 29:29
+    U32 Invert_Data_and_ECC                     :  1;  // Bits 30:30
+    U32 Stop_Base_Subsequence_On_Wrap_Trigger   :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_STRUCT_HSW_A0;
+
+typedef union {
+  struct {
+    U32 Number_of_Cachelines                    :  7;  // Bits 6:0
+    U32 Number_of_Cachelines_Scale              :  1;  // Bits 7:7
+    U32 Subsequence_Wait                        :  8;  // Bits 15:8
+    U32                                         :  4;  // Bits 19:16
+    U32 Subsequence_Type                        :  4;  // Bits 23:20
+    U32                                         :  1;  // Bits 24:24
+    U32 Save_Current_Base_Address_To_Start      :  1;  // Bits 25:25
+    U32 Reset_Current_Base_Address_To_Start     :  1;  // Bits 26:26
+    U32 Data_and_ECC_Address_Inversion          :  2;  // Bits 28:27
+    U32                                         :  1;  // Bits 29:29
+    U32 Invert_Data_and_ECC                     :  1;  // Bits 30:30
+    U32 Stop_Base_Subsequence_On_Wrap_Trigger   :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_STRUCT_HSW_A0;
+
+typedef union {
+  struct {
+    U32 Number_of_Cachelines                    :  7;  // Bits 6:0
+    U32 Number_of_Cachelines_Scale              :  1;  // Bits 7:7
+    U32 Subsequence_Wait                        :  8;  // Bits 15:8
+    U32                                         :  4;  // Bits 19:16
+    U32 Subsequence_Type                        :  4;  // Bits 23:20
+    U32                                         :  1;  // Bits 24:24
+    U32 Save_Current_Base_Address_To_Start      :  1;  // Bits 25:25
+    U32 Reset_Current_Base_Address_To_Start     :  1;  // Bits 26:26
+    U32 Data_and_ECC_Address_Inversion          :  2;  // Bits 28:27
+    U32                                         :  1;  // Bits 29:29
+    U32 Invert_Data_and_ECC                     :  1;  // Bits 30:30
+    U32 Stop_Base_Subsequence_On_Wrap_Trigger   :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_STRUCT_HSW_A0;
+
+typedef union {
+  struct {
+    U32 Number_of_Cachelines                    :  7;  // Bits 6:0
+    U32 Number_of_Cachelines_Scale              :  1;  // Bits 7:7
+    U32 Subsequence_Wait                        :  8;  // Bits 15:8
+    U32                                         :  4;  // Bits 19:16
+    U32 Subsequence_Type                        :  4;  // Bits 23:20
+    U32                                         :  1;  // Bits 24:24
+    U32 Save_Current_Base_Address_To_Start      :  1;  // Bits 25:25
+    U32 Reset_Current_Base_Address_To_Start     :  1;  // Bits 26:26
+    U32 Data_and_ECC_Address_Inversion          :  2;  // Bits 28:27
+    U32                                         :  1;  // Bits 29:29
+    U32 Invert_Data_and_ECC                     :  1;  // Bits 30:30
+    U32 Stop_Base_Subsequence_On_Wrap_Trigger   :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_STRUCT_HSW_A0;
+
+typedef union {
+  struct {
+    U32 Number_of_Cachelines                    :  7;  // Bits 6:0
+    U32 Number_of_Cachelines_Scale              :  1;  // Bits 7:7
+    U32 Subsequence_Wait                        :  8;  // Bits 15:8
+    U32                                         :  4;  // Bits 19:16
+    U32 Subsequence_Type                        :  4;  // Bits 23:20
+    U32                                         :  1;  // Bits 24:24
+    U32 Save_Current_Base_Address_To_Start      :  1;  // Bits 25:25
+    U32 Reset_Current_Base_Address_To_Start     :  1;  // Bits 26:26
+    U32 Data_and_ECC_Address_Inversion          :  2;  // Bits 28:27
+    U32                                         :  1;  // Bits 29:29
+    U32 Invert_Data_and_ECC                     :  1;  // Bits 30:30
+    U32 Stop_Base_Subsequence_On_Wrap_Trigger   :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_STRUCT_HSW_A0;
+
+typedef union {
+  struct {
+    U32 Number_of_Cachelines                    :  7;  // Bits 6:0
+    U32 Number_of_Cachelines_Scale              :  1;  // Bits 7:7
+    U32 Subsequence_Wait                        :  8;  // Bits 15:8
+    U32                                         :  4;  // Bits 19:16
+    U32 Subsequence_Type                        :  4;  // Bits 23:20
+    U32                                         :  1;  // Bits 24:24
+    U32 Save_Current_Base_Address_To_Start      :  1;  // Bits 25:25
+    U32 Reset_Current_Base_Address_To_Start     :  1;  // Bits 26:26
+    U32 Data_and_ECC_Address_Inversion          :  2;  // Bits 28:27
+    U32                                         :  1;  // Bits 29:29
+    U32 Invert_Data_and_ECC                     :  1;  // Bits 30:30
+    U32 Stop_Base_Subsequence_On_Wrap_Trigger   :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_STRUCT_HSW_A0;
+
+typedef union {
+  struct {
+    U32 Number_of_Cachelines                    :  7;  // Bits 6:0
+    U32 Number_of_Cachelines_Scale              :  1;  // Bits 7:7
+    U32 Subsequence_Wait                        :  14;  // Bits 21:8
+    U32 Subsequence_Type                        :  4;  // Bits 25:22
+    U32 Save_Current_Base_Address_To_Start      :  1;  // Bits 26:26
+    U32 Reset_Current_Base_Address_To_Start     :  1;  // Bits 27:27
+    U32 Data_and_ECC_Address_Inversion          :  2;  // Bits 29:28
+    U32 Invert_Data_and_ECC                     :  1;  // Bits 30:30
+    U32 Stop_Base_Subsequence_On_Wrap_Trigger   :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_STRUCT;
+
+typedef union {
+  struct {
+    U32 Number_of_Cachelines                    :  7;  // Bits 6:0
+    U32 Number_of_Cachelines_Scale              :  1;  // Bits 7:7
+    U32 Subsequence_Wait                        :  14;  // Bits 21:8
+    U32 Subsequence_Type                        :  4;  // Bits 25:22
+    U32 Save_Current_Base_Address_To_Start      :  1;  // Bits 26:26
+    U32 Reset_Current_Base_Address_To_Start     :  1;  // Bits 27:27
+    U32 Data_and_ECC_Address_Inversion          :  2;  // Bits 29:28
+    U32 Invert_Data_and_ECC                     :  1;  // Bits 30:30
+    U32 Stop_Base_Subsequence_On_Wrap_Trigger   :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_STRUCT;
+
+typedef union {
+  struct {
+    U32 Number_of_Cachelines                    :  7;  // Bits 6:0
+    U32 Number_of_Cachelines_Scale              :  1;  // Bits 7:7
+    U32 Subsequence_Wait                        :  14;  // Bits 21:8
+    U32 Subsequence_Type                        :  4;  // Bits 25:22
+    U32 Save_Current_Base_Address_To_Start      :  1;  // Bits 26:26
+    U32 Reset_Current_Base_Address_To_Start     :  1;  // Bits 27:27
+    U32 Data_and_ECC_Address_Inversion          :  2;  // Bits 29:28
+    U32 Invert_Data_and_ECC                     :  1;  // Bits 30:30
+    U32 Stop_Base_Subsequence_On_Wrap_Trigger   :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_STRUCT;
+
+typedef union {
+  struct {
+    U32 Number_of_Cachelines                    :  7;  // Bits 6:0
+    U32 Number_of_Cachelines_Scale              :  1;  // Bits 7:7
+    U32 Subsequence_Wait                        :  14;  // Bits 21:8
+    U32 Subsequence_Type                        :  4;  // Bits 25:22
+    U32 Save_Current_Base_Address_To_Start      :  1;  // Bits 26:26
+    U32 Reset_Current_Base_Address_To_Start     :  1;  // Bits 27:27
+    U32 Data_and_ECC_Address_Inversion          :  2;  // Bits 29:28
+    U32 Invert_Data_and_ECC                     :  1;  // Bits 30:30
+    U32 Stop_Base_Subsequence_On_Wrap_Trigger   :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_STRUCT;
+
+typedef union {
+  struct {
+    U32 Number_of_Cachelines                    :  7;  // Bits 6:0
+    U32 Number_of_Cachelines_Scale              :  1;  // Bits 7:7
+    U32 Subsequence_Wait                        :  14;  // Bits 21:8
+    U32 Subsequence_Type                        :  4;  // Bits 25:22
+    U32 Save_Current_Base_Address_To_Start      :  1;  // Bits 26:26
+    U32 Reset_Current_Base_Address_To_Start     :  1;  // Bits 27:27
+    U32 Data_and_ECC_Address_Inversion          :  2;  // Bits 29:28
+    U32 Invert_Data_and_ECC                     :  1;  // Bits 30:30
+    U32 Stop_Base_Subsequence_On_Wrap_Trigger   :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_STRUCT;
+
+typedef union {
+  struct {
+    U32 Number_of_Cachelines                    :  7;  // Bits 6:0
+    U32 Number_of_Cachelines_Scale              :  1;  // Bits 7:7
+    U32 Subsequence_Wait                        :  14;  // Bits 21:8
+    U32 Subsequence_Type                        :  4;  // Bits 25:22
+    U32 Save_Current_Base_Address_To_Start      :  1;  // Bits 26:26
+    U32 Reset_Current_Base_Address_To_Start     :  1;  // Bits 27:27
+    U32 Data_and_ECC_Address_Inversion          :  2;  // Bits 29:28
+    U32 Invert_Data_and_ECC                     :  1;  // Bits 30:30
+    U32 Stop_Base_Subsequence_On_Wrap_Trigger   :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_STRUCT;
+
+typedef union {
+  struct {
+    U32 Number_of_Cachelines                    :  7;  // Bits 6:0
+    U32 Number_of_Cachelines_Scale              :  1;  // Bits 7:7
+    U32 Subsequence_Wait                        :  14;  // Bits 21:8
+    U32 Subsequence_Type                        :  4;  // Bits 25:22
+    U32 Save_Current_Base_Address_To_Start      :  1;  // Bits 26:26
+    U32 Reset_Current_Base_Address_To_Start     :  1;  // Bits 27:27
+    U32 Data_and_ECC_Address_Inversion          :  2;  // Bits 29:28
+    U32 Invert_Data_and_ECC                     :  1;  // Bits 30:30
+    U32 Stop_Base_Subsequence_On_Wrap_Trigger   :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_STRUCT;
+
+typedef union {
+  struct {
+    U32 Number_of_Cachelines                    :  7;  // Bits 6:0
+    U32 Number_of_Cachelines_Scale              :  1;  // Bits 7:7
+    U32 Subsequence_Wait                        :  14;  // Bits 21:8
+    U32 Subsequence_Type                        :  4;  // Bits 25:22
+    U32 Save_Current_Base_Address_To_Start      :  1;  // Bits 26:26
+    U32 Reset_Current_Base_Address_To_Start     :  1;  // Bits 27:27
+    U32 Data_and_ECC_Address_Inversion          :  2;  // Bits 29:28
+    U32 Invert_Data_and_ECC                     :  1;  // Bits 30:30
+    U32 Stop_Base_Subsequence_On_Wrap_Trigger   :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_STRUCT;
+
+typedef union {
+  struct {
+    U32 Number_of_Cachelines                    :  7;  // Bits 6:0
+    U32 Number_of_Cachelines_Scale              :  1;  // Bits 7:7
+    U32 Subsequence_Wait                        :  14;  // Bits 21:8
+    U32 Subsequence_Type                        :  4;  // Bits 25:22
+    U32 Save_Current_Base_Address_To_Start      :  1;  // Bits 26:26
+    U32 Reset_Current_Base_Address_To_Start     :  1;  // Bits 27:27
+    U32 Data_and_ECC_Address_Inversion          :  2;  // Bits 29:28
+    U32 Invert_Data_and_ECC                     :  1;  // Bits 30:30
+    U32 Stop_Base_Subsequence_On_Wrap_Trigger   :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_STRUCT;
+
+typedef union {
+  struct {
+    U32 Number_of_Cachelines                    :  7;  // Bits 6:0
+    U32 Number_of_Cachelines_Scale              :  1;  // Bits 7:7
+    U32 Subsequence_Wait                        :  14;  // Bits 21:8
+    U32 Subsequence_Type                        :  4;  // Bits 25:22
+    U32 Save_Current_Base_Address_To_Start      :  1;  // Bits 26:26
+    U32 Reset_Current_Base_Address_To_Start     :  1;  // Bits 27:27
+    U32 Data_and_ECC_Address_Inversion          :  2;  // Bits 29:28
+    U32 Invert_Data_and_ECC                     :  1;  // Bits 30:30
+    U32 Stop_Base_Subsequence_On_Wrap_Trigger   :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_STRUCT;
+
+typedef union {
+  struct {
+    U32 Number_of_Cachelines                    :  7;  // Bits 6:0
+    U32 Number_of_Cachelines_Scale              :  1;  // Bits 7:7
+    U32 Subsequence_Wait                        :  14;  // Bits 21:8
+    U32 Subsequence_Type                        :  4;  // Bits 25:22
+    U32 Save_Current_Base_Address_To_Start      :  1;  // Bits 26:26
+    U32 Reset_Current_Base_Address_To_Start     :  1;  // Bits 27:27
+    U32 Data_and_ECC_Address_Inversion          :  2;  // Bits 29:28
+    U32 Invert_Data_and_ECC                     :  1;  // Bits 30:30
+    U32 Stop_Base_Subsequence_On_Wrap_Trigger   :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_STRUCT;
+
+typedef union {
+  struct {
+    U32 Number_of_Cachelines                    :  7;  // Bits 6:0
+    U32 Number_of_Cachelines_Scale              :  1;  // Bits 7:7
+    U32 Subsequence_Wait                        :  14;  // Bits 21:8
+    U32 Subsequence_Type                        :  4;  // Bits 25:22
+    U32 Save_Current_Base_Address_To_Start      :  1;  // Bits 26:26
+    U32 Reset_Current_Base_Address_To_Start     :  1;  // Bits 27:27
+    U32 Data_and_ECC_Address_Inversion          :  2;  // Bits 29:28
+    U32 Invert_Data_and_ECC                     :  1;  // Bits 30:30
+    U32 Stop_Base_Subsequence_On_Wrap_Trigger   :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_STRUCT;
+
+typedef union {
+  struct {
+    U32 Number_of_Cachelines                    :  7;  // Bits 6:0
+    U32 Number_of_Cachelines_Scale              :  1;  // Bits 7:7
+    U32 Subsequence_Wait                        :  14;  // Bits 21:8
+    U32 Subsequence_Type                        :  4;  // Bits 25:22
+    U32 Save_Current_Base_Address_To_Start      :  1;  // Bits 26:26
+    U32 Reset_Current_Base_Address_To_Start     :  1;  // Bits 27:27
+    U32 Data_and_ECC_Address_Inversion          :  2;  // Bits 29:28
+    U32 Invert_Data_and_ECC                     :  1;  // Bits 30:30
+    U32 Stop_Base_Subsequence_On_Wrap_Trigger   :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_STRUCT;
+
+typedef union {
+  struct {
+    U32 Number_of_Cachelines                    :  7;  // Bits 6:0
+    U32 Number_of_Cachelines_Scale              :  1;  // Bits 7:7
+    U32 Subsequence_Wait                        :  14;  // Bits 21:8
+    U32 Subsequence_Type                        :  4;  // Bits 25:22
+    U32 Save_Current_Base_Address_To_Start      :  1;  // Bits 26:26
+    U32 Reset_Current_Base_Address_To_Start     :  1;  // Bits 27:27
+    U32 Data_and_ECC_Address_Inversion          :  2;  // Bits 29:28
+    U32 Invert_Data_and_ECC                     :  1;  // Bits 30:30
+    U32 Stop_Base_Subsequence_On_Wrap_Trigger   :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_STRUCT;
+
+typedef union {
+  struct {
+    U32 Number_of_Cachelines                    :  7;  // Bits 6:0
+    U32 Number_of_Cachelines_Scale              :  1;  // Bits 7:7
+    U32 Subsequence_Wait                        :  14;  // Bits 21:8
+    U32 Subsequence_Type                        :  4;  // Bits 25:22
+    U32 Save_Current_Base_Address_To_Start      :  1;  // Bits 26:26
+    U32 Reset_Current_Base_Address_To_Start     :  1;  // Bits 27:27
+    U32 Data_and_ECC_Address_Inversion          :  2;  // Bits 29:28
+    U32 Invert_Data_and_ECC                     :  1;  // Bits 30:30
+    U32 Stop_Base_Subsequence_On_Wrap_Trigger   :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_STRUCT;
+
+typedef union {
+  struct {
+    U32 Number_of_Cachelines                    :  7;  // Bits 6:0
+    U32 Number_of_Cachelines_Scale              :  1;  // Bits 7:7
+    U32 Subsequence_Wait                        :  14;  // Bits 21:8
+    U32 Subsequence_Type                        :  4;  // Bits 25:22
+    U32 Save_Current_Base_Address_To_Start      :  1;  // Bits 26:26
+    U32 Reset_Current_Base_Address_To_Start     :  1;  // Bits 27:27
+    U32 Data_and_ECC_Address_Inversion          :  2;  // Bits 29:28
+    U32 Invert_Data_and_ECC                     :  1;  // Bits 30:30
+    U32 Stop_Base_Subsequence_On_Wrap_Trigger   :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_STRUCT;
+
+typedef union {
+  struct {
+    U32 Offset_Address_Update_Rate              :  5;  // Bits 4:0
+    U32                                         :  3;  // Bits 7:5
+    U32 Base_Subsequence_Repeat_Rate            :  5;  // Bits 12:8
+    U32                                         :  2;  // Bits 14:13
+    U32 Column_Offset_Wrap_Trigger_Enable       :  1;  // Bits 15:15
+    U32 Row_Offset_Wrap_Trigger_Enable          :  1;  // Bits 16:16
+    U32                                         :  3;  // Bits 19:17
+    U32 Base_Subsequence_Type                   :  1;  // Bits 20:20
+    U32 CADB_Deselect_Enable                    :  1;  // Bits 21:21
+    U32 CADB_Select_Enable                      :  1;  // Bits 22:22
+    U32 CADB_Seeds_Save_Enable                  :  1;  // Bits 23:23
+    U32 Column_Increment_Order                  :  1;  // Bits 24:24
+    U32                                         :  1;  // Bits 25:25
+    U32 Column_Increment_Enable                 :  1;  // Bits 26:26
+    U32 Row_Increment_Order                     :  1;  // Bits 27:27
+    U32                                         :  1;  // Bits 28:28
+    U32 Row_Increment_Enable                    :  1;  // Bits 29:29
+    U32 Base_Invert_Data_and_ECC                :  1;  // Bits 30:30
+    U32                                         :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_STRUCT;
+
+typedef union {
+  struct {
+    U32 Offset_Address_Update_Rate              :  5;  // Bits 4:0
+    U32                                         :  3;  // Bits 7:5
+    U32 Base_Subsequence_Repeat_Rate            :  5;  // Bits 12:8
+    U32                                         :  2;  // Bits 14:13
+    U32 Column_Offset_Wrap_Trigger_Enable       :  1;  // Bits 15:15
+    U32 Row_Offset_Wrap_Trigger_Enable          :  1;  // Bits 16:16
+    U32                                         :  3;  // Bits 19:17
+    U32 Base_Subsequence_Type                   :  1;  // Bits 20:20
+    U32 CADB_Deselect_Enable                    :  1;  // Bits 21:21
+    U32 CADB_Select_Enable                      :  1;  // Bits 22:22
+    U32 CADB_Seeds_Save_Enable                  :  1;  // Bits 23:23
+    U32 Column_Increment_Order                  :  1;  // Bits 24:24
+    U32                                         :  1;  // Bits 25:25
+    U32 Column_Increment_Enable                 :  1;  // Bits 26:26
+    U32 Row_Increment_Order                     :  1;  // Bits 27:27
+    U32                                         :  1;  // Bits 28:28
+    U32 Row_Increment_Enable                    :  1;  // Bits 29:29
+    U32 Base_Invert_Data_and_ECC                :  1;  // Bits 30:30
+    U32                                         :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_STRUCT;
+
+typedef union {
+  struct {
+    U32 Offset_Address_Update_Rate              :  5;  // Bits 4:0
+    U32                                         :  3;  // Bits 7:5
+    U32 Base_Subsequence_Repeat_Rate            :  5;  // Bits 12:8
+    U32                                         :  2;  // Bits 14:13
+    U32 Column_Offset_Wrap_Trigger_Enable       :  1;  // Bits 15:15
+    U32 Row_Offset_Wrap_Trigger_Enable          :  1;  // Bits 16:16
+    U32                                         :  3;  // Bits 19:17
+    U32 Base_Subsequence_Type                   :  1;  // Bits 20:20
+    U32 CADB_Deselect_Enable                    :  1;  // Bits 21:21
+    U32 CADB_Select_Enable                      :  1;  // Bits 22:22
+    U32 CADB_Seeds_Save_Enable                  :  1;  // Bits 23:23
+    U32 Column_Increment_Order                  :  1;  // Bits 24:24
+    U32                                         :  1;  // Bits 25:25
+    U32 Column_Increment_Enable                 :  1;  // Bits 26:26
+    U32 Row_Increment_Order                     :  1;  // Bits 27:27
+    U32                                         :  1;  // Bits 28:28
+    U32 Row_Increment_Enable                    :  1;  // Bits 29:29
+    U32 Base_Invert_Data_and_ECC                :  1;  // Bits 30:30
+    U32                                         :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_STRUCT;
+
+typedef union {
+  struct {
+    U32 Offset_Address_Update_Rate              :  5;  // Bits 4:0
+    U32                                         :  3;  // Bits 7:5
+    U32 Base_Subsequence_Repeat_Rate            :  5;  // Bits 12:8
+    U32                                         :  2;  // Bits 14:13
+    U32 Column_Offset_Wrap_Trigger_Enable       :  1;  // Bits 15:15
+    U32 Row_Offset_Wrap_Trigger_Enable          :  1;  // Bits 16:16
+    U32                                         :  3;  // Bits 19:17
+    U32 Base_Subsequence_Type                   :  1;  // Bits 20:20
+    U32 CADB_Deselect_Enable                    :  1;  // Bits 21:21
+    U32 CADB_Select_Enable                      :  1;  // Bits 22:22
+    U32 CADB_Seeds_Save_Enable                  :  1;  // Bits 23:23
+    U32 Column_Increment_Order                  :  1;  // Bits 24:24
+    U32                                         :  1;  // Bits 25:25
+    U32 Column_Increment_Enable                 :  1;  // Bits 26:26
+    U32 Row_Increment_Order                     :  1;  // Bits 27:27
+    U32                                         :  1;  // Bits 28:28
+    U32 Row_Increment_Enable                    :  1;  // Bits 29:29
+    U32 Base_Invert_Data_and_ECC                :  1;  // Bits 30:30
+    U32                                         :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_STRUCT;
+
+typedef union {
+  struct {
+    U32 Offset_Address_Update_Rate              :  5;  // Bits 4:0
+    U32                                         :  3;  // Bits 7:5
+    U32 Base_Subsequence_Repeat_Rate            :  5;  // Bits 12:8
+    U32                                         :  2;  // Bits 14:13
+    U32 Column_Offset_Wrap_Trigger_Enable       :  1;  // Bits 15:15
+    U32 Row_Offset_Wrap_Trigger_Enable          :  1;  // Bits 16:16
+    U32                                         :  3;  // Bits 19:17
+    U32 Base_Subsequence_Type                   :  1;  // Bits 20:20
+    U32 CADB_Deselect_Enable                    :  1;  // Bits 21:21
+    U32 CADB_Select_Enable                      :  1;  // Bits 22:22
+    U32 CADB_Seeds_Save_Enable                  :  1;  // Bits 23:23
+    U32 Column_Increment_Order                  :  1;  // Bits 24:24
+    U32                                         :  1;  // Bits 25:25
+    U32 Column_Increment_Enable                 :  1;  // Bits 26:26
+    U32 Row_Increment_Order                     :  1;  // Bits 27:27
+    U32                                         :  1;  // Bits 28:28
+    U32 Row_Increment_Enable                    :  1;  // Bits 29:29
+    U32 Base_Invert_Data_and_ECC                :  1;  // Bits 30:30
+    U32                                         :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_STRUCT;
+
+typedef union {
+  struct {
+    U32 Offset_Address_Update_Rate              :  5;  // Bits 4:0
+    U32                                         :  3;  // Bits 7:5
+    U32 Base_Subsequence_Repeat_Rate            :  5;  // Bits 12:8
+    U32                                         :  2;  // Bits 14:13
+    U32 Column_Offset_Wrap_Trigger_Enable       :  1;  // Bits 15:15
+    U32 Row_Offset_Wrap_Trigger_Enable          :  1;  // Bits 16:16
+    U32                                         :  3;  // Bits 19:17
+    U32 Base_Subsequence_Type                   :  1;  // Bits 20:20
+    U32 CADB_Deselect_Enable                    :  1;  // Bits 21:21
+    U32 CADB_Select_Enable                      :  1;  // Bits 22:22
+    U32 CADB_Seeds_Save_Enable                  :  1;  // Bits 23:23
+    U32 Column_Increment_Order                  :  1;  // Bits 24:24
+    U32                                         :  1;  // Bits 25:25
+    U32 Column_Increment_Enable                 :  1;  // Bits 26:26
+    U32 Row_Increment_Order                     :  1;  // Bits 27:27
+    U32                                         :  1;  // Bits 28:28
+    U32 Row_Increment_Enable                    :  1;  // Bits 29:29
+    U32 Base_Invert_Data_and_ECC                :  1;  // Bits 30:30
+    U32                                         :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_STRUCT;
+
+typedef union {
+  struct {
+    U32 Offset_Address_Update_Rate              :  5;  // Bits 4:0
+    U32                                         :  3;  // Bits 7:5
+    U32 Base_Subsequence_Repeat_Rate            :  5;  // Bits 12:8
+    U32                                         :  2;  // Bits 14:13
+    U32 Column_Offset_Wrap_Trigger_Enable       :  1;  // Bits 15:15
+    U32 Row_Offset_Wrap_Trigger_Enable          :  1;  // Bits 16:16
+    U32                                         :  3;  // Bits 19:17
+    U32 Base_Subsequence_Type                   :  1;  // Bits 20:20
+    U32 CADB_Deselect_Enable                    :  1;  // Bits 21:21
+    U32 CADB_Select_Enable                      :  1;  // Bits 22:22
+    U32 CADB_Seeds_Save_Enable                  :  1;  // Bits 23:23
+    U32 Column_Increment_Order                  :  1;  // Bits 24:24
+    U32                                         :  1;  // Bits 25:25
+    U32 Column_Increment_Enable                 :  1;  // Bits 26:26
+    U32 Row_Increment_Order                     :  1;  // Bits 27:27
+    U32                                         :  1;  // Bits 28:28
+    U32 Row_Increment_Enable                    :  1;  // Bits 29:29
+    U32 Base_Invert_Data_and_ECC                :  1;  // Bits 30:30
+    U32                                         :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_STRUCT;
+
+typedef union {
+  struct {
+    U32 Offset_Address_Update_Rate              :  5;  // Bits 4:0
+    U32                                         :  3;  // Bits 7:5
+    U32 Base_Subsequence_Repeat_Rate            :  5;  // Bits 12:8
+    U32                                         :  2;  // Bits 14:13
+    U32 Column_Offset_Wrap_Trigger_Enable       :  1;  // Bits 15:15
+    U32 Row_Offset_Wrap_Trigger_Enable          :  1;  // Bits 16:16
+    U32                                         :  3;  // Bits 19:17
+    U32 Base_Subsequence_Type                   :  1;  // Bits 20:20
+    U32 CADB_Deselect_Enable                    :  1;  // Bits 21:21
+    U32 CADB_Select_Enable                      :  1;  // Bits 22:22
+    U32 CADB_Seeds_Save_Enable                  :  1;  // Bits 23:23
+    U32 Column_Increment_Order                  :  1;  // Bits 24:24
+    U32                                         :  1;  // Bits 25:25
+    U32 Column_Increment_Enable                 :  1;  // Bits 26:26
+    U32 Row_Increment_Order                     :  1;  // Bits 27:27
+    U32                                         :  1;  // Bits 28:28
+    U32 Row_Increment_Enable                    :  1;  // Bits 29:29
+    U32 Base_Invert_Data_and_ECC                :  1;  // Bits 30:30
+    U32                                         :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_STRUCT;
+
+typedef union {
+  struct {
+    U32 Offset_Address_Update_Rate              :  5;  // Bits 4:0
+    U32                                         :  3;  // Bits 7:5
+    U32 Base_Subsequence_Repeat_Rate            :  5;  // Bits 12:8
+    U32                                         :  2;  // Bits 14:13
+    U32 Column_Offset_Wrap_Trigger_Enable       :  1;  // Bits 15:15
+    U32 Row_Offset_Wrap_Trigger_Enable          :  1;  // Bits 16:16
+    U32                                         :  3;  // Bits 19:17
+    U32 Base_Subsequence_Type                   :  1;  // Bits 20:20
+    U32 CADB_Deselect_Enable                    :  1;  // Bits 21:21
+    U32 CADB_Select_Enable                      :  1;  // Bits 22:22
+    U32 CADB_Seeds_Save_Enable                  :  1;  // Bits 23:23
+    U32 Column_Increment_Order                  :  1;  // Bits 24:24
+    U32                                         :  1;  // Bits 25:25
+    U32 Column_Increment_Enable                 :  1;  // Bits 26:26
+    U32 Row_Increment_Order                     :  1;  // Bits 27:27
+    U32                                         :  1;  // Bits 28:28
+    U32 Row_Increment_Enable                    :  1;  // Bits 29:29
+    U32 Base_Invert_Data_and_ECC                :  1;  // Bits 30:30
+    U32                                         :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_STRUCT;
+
+typedef union {
+  struct {
+    U32 Offset_Address_Update_Rate              :  5;  // Bits 4:0
+    U32                                         :  3;  // Bits 7:5
+    U32 Base_Subsequence_Repeat_Rate            :  5;  // Bits 12:8
+    U32                                         :  2;  // Bits 14:13
+    U32 Column_Offset_Wrap_Trigger_Enable       :  1;  // Bits 15:15
+    U32 Row_Offset_Wrap_Trigger_Enable          :  1;  // Bits 16:16
+    U32                                         :  3;  // Bits 19:17
+    U32 Base_Subsequence_Type                   :  1;  // Bits 20:20
+    U32 CADB_Deselect_Enable                    :  1;  // Bits 21:21
+    U32 CADB_Select_Enable                      :  1;  // Bits 22:22
+    U32 CADB_Seeds_Save_Enable                  :  1;  // Bits 23:23
+    U32 Column_Increment_Order                  :  1;  // Bits 24:24
+    U32                                         :  1;  // Bits 25:25
+    U32 Column_Increment_Enable                 :  1;  // Bits 26:26
+    U32 Row_Increment_Order                     :  1;  // Bits 27:27
+    U32                                         :  1;  // Bits 28:28
+    U32 Row_Increment_Enable                    :  1;  // Bits 29:29
+    U32 Base_Invert_Data_and_ECC                :  1;  // Bits 30:30
+    U32                                         :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_STRUCT;
+
+typedef union {
+  struct {
+    U32 Offset_Address_Update_Rate              :  5;  // Bits 4:0
+    U32                                         :  3;  // Bits 7:5
+    U32 Base_Subsequence_Repeat_Rate            :  5;  // Bits 12:8
+    U32                                         :  2;  // Bits 14:13
+    U32 Column_Offset_Wrap_Trigger_Enable       :  1;  // Bits 15:15
+    U32 Row_Offset_Wrap_Trigger_Enable          :  1;  // Bits 16:16
+    U32                                         :  3;  // Bits 19:17
+    U32 Base_Subsequence_Type                   :  1;  // Bits 20:20
+    U32 CADB_Deselect_Enable                    :  1;  // Bits 21:21
+    U32 CADB_Select_Enable                      :  1;  // Bits 22:22
+    U32 CADB_Seeds_Save_Enable                  :  1;  // Bits 23:23
+    U32 Column_Increment_Order                  :  1;  // Bits 24:24
+    U32                                         :  1;  // Bits 25:25
+    U32 Column_Increment_Enable                 :  1;  // Bits 26:26
+    U32 Row_Increment_Order                     :  1;  // Bits 27:27
+    U32                                         :  1;  // Bits 28:28
+    U32 Row_Increment_Enable                    :  1;  // Bits 29:29
+    U32 Base_Invert_Data_and_ECC                :  1;  // Bits 30:30
+    U32                                         :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_STRUCT;
+
+typedef union {
+  struct {
+    U32 Offset_Address_Update_Rate              :  5;  // Bits 4:0
+    U32                                         :  3;  // Bits 7:5
+    U32 Base_Subsequence_Repeat_Rate            :  5;  // Bits 12:8
+    U32                                         :  2;  // Bits 14:13
+    U32 Column_Offset_Wrap_Trigger_Enable       :  1;  // Bits 15:15
+    U32 Row_Offset_Wrap_Trigger_Enable          :  1;  // Bits 16:16
+    U32                                         :  3;  // Bits 19:17
+    U32 Base_Subsequence_Type                   :  1;  // Bits 20:20
+    U32 CADB_Deselect_Enable                    :  1;  // Bits 21:21
+    U32 CADB_Select_Enable                      :  1;  // Bits 22:22
+    U32 CADB_Seeds_Save_Enable                  :  1;  // Bits 23:23
+    U32 Column_Increment_Order                  :  1;  // Bits 24:24
+    U32                                         :  1;  // Bits 25:25
+    U32 Column_Increment_Enable                 :  1;  // Bits 26:26
+    U32 Row_Increment_Order                     :  1;  // Bits 27:27
+    U32                                         :  1;  // Bits 28:28
+    U32 Row_Increment_Enable                    :  1;  // Bits 29:29
+    U32 Base_Invert_Data_and_ECC                :  1;  // Bits 30:30
+    U32                                         :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_STRUCT;
+
+typedef union {
+  struct {
+    U32 Offset_Address_Update_Rate              :  5;  // Bits 4:0
+    U32                                         :  3;  // Bits 7:5
+    U32 Base_Subsequence_Repeat_Rate            :  5;  // Bits 12:8
+    U32                                         :  2;  // Bits 14:13
+    U32 Column_Offset_Wrap_Trigger_Enable       :  1;  // Bits 15:15
+    U32 Row_Offset_Wrap_Trigger_Enable          :  1;  // Bits 16:16
+    U32                                         :  3;  // Bits 19:17
+    U32 Base_Subsequence_Type                   :  1;  // Bits 20:20
+    U32 CADB_Deselect_Enable                    :  1;  // Bits 21:21
+    U32 CADB_Select_Enable                      :  1;  // Bits 22:22
+    U32 CADB_Seeds_Save_Enable                  :  1;  // Bits 23:23
+    U32 Column_Increment_Order                  :  1;  // Bits 24:24
+    U32                                         :  1;  // Bits 25:25
+    U32 Column_Increment_Enable                 :  1;  // Bits 26:26
+    U32 Row_Increment_Order                     :  1;  // Bits 27:27
+    U32                                         :  1;  // Bits 28:28
+    U32 Row_Increment_Enable                    :  1;  // Bits 29:29
+    U32 Base_Invert_Data_and_ECC                :  1;  // Bits 30:30
+    U32                                         :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_STRUCT;
+
+typedef union {
+  struct {
+    U32 Offset_Address_Update_Rate              :  5;  // Bits 4:0
+    U32                                         :  3;  // Bits 7:5
+    U32 Base_Subsequence_Repeat_Rate            :  5;  // Bits 12:8
+    U32                                         :  2;  // Bits 14:13
+    U32 Column_Offset_Wrap_Trigger_Enable       :  1;  // Bits 15:15
+    U32 Row_Offset_Wrap_Trigger_Enable          :  1;  // Bits 16:16
+    U32                                         :  3;  // Bits 19:17
+    U32 Base_Subsequence_Type                   :  1;  // Bits 20:20
+    U32 CADB_Deselect_Enable                    :  1;  // Bits 21:21
+    U32 CADB_Select_Enable                      :  1;  // Bits 22:22
+    U32 CADB_Seeds_Save_Enable                  :  1;  // Bits 23:23
+    U32 Column_Increment_Order                  :  1;  // Bits 24:24
+    U32                                         :  1;  // Bits 25:25
+    U32 Column_Increment_Enable                 :  1;  // Bits 26:26
+    U32 Row_Increment_Order                     :  1;  // Bits 27:27
+    U32                                         :  1;  // Bits 28:28
+    U32 Row_Increment_Enable                    :  1;  // Bits 29:29
+    U32 Base_Invert_Data_and_ECC                :  1;  // Bits 30:30
+    U32                                         :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_STRUCT;
+
+typedef union {
+  struct {
+    U32 Offset_Address_Update_Rate              :  5;  // Bits 4:0
+    U32                                         :  3;  // Bits 7:5
+    U32 Base_Subsequence_Repeat_Rate            :  5;  // Bits 12:8
+    U32                                         :  2;  // Bits 14:13
+    U32 Column_Offset_Wrap_Trigger_Enable       :  1;  // Bits 15:15
+    U32 Row_Offset_Wrap_Trigger_Enable          :  1;  // Bits 16:16
+    U32                                         :  3;  // Bits 19:17
+    U32 Base_Subsequence_Type                   :  1;  // Bits 20:20
+    U32 CADB_Deselect_Enable                    :  1;  // Bits 21:21
+    U32 CADB_Select_Enable                      :  1;  // Bits 22:22
+    U32 CADB_Seeds_Save_Enable                  :  1;  // Bits 23:23
+    U32 Column_Increment_Order                  :  1;  // Bits 24:24
+    U32                                         :  1;  // Bits 25:25
+    U32 Column_Increment_Enable                 :  1;  // Bits 26:26
+    U32 Row_Increment_Order                     :  1;  // Bits 27:27
+    U32                                         :  1;  // Bits 28:28
+    U32 Row_Increment_Enable                    :  1;  // Bits 29:29
+    U32 Base_Invert_Data_and_ECC                :  1;  // Bits 30:30
+    U32                                         :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_STRUCT;
+
+typedef union {
+  struct {
+    U32 Offset_Address_Update_Rate              :  5;  // Bits 4:0
+    U32                                         :  3;  // Bits 7:5
+    U32 Base_Subsequence_Repeat_Rate            :  5;  // Bits 12:8
+    U32                                         :  2;  // Bits 14:13
+    U32 Column_Offset_Wrap_Trigger_Enable       :  1;  // Bits 15:15
+    U32 Row_Offset_Wrap_Trigger_Enable          :  1;  // Bits 16:16
+    U32                                         :  3;  // Bits 19:17
+    U32 Base_Subsequence_Type                   :  1;  // Bits 20:20
+    U32 CADB_Deselect_Enable                    :  1;  // Bits 21:21
+    U32 CADB_Select_Enable                      :  1;  // Bits 22:22
+    U32 CADB_Seeds_Save_Enable                  :  1;  // Bits 23:23
+    U32 Column_Increment_Order                  :  1;  // Bits 24:24
+    U32                                         :  1;  // Bits 25:25
+    U32 Column_Increment_Enable                 :  1;  // Bits 26:26
+    U32 Row_Increment_Order                     :  1;  // Bits 27:27
+    U32                                         :  1;  // Bits 28:28
+    U32 Row_Increment_Enable                    :  1;  // Bits 29:29
+    U32 Base_Invert_Data_and_ECC                :  1;  // Bits 30:30
+    U32                                         :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_STRUCT;
+
+typedef union {
+  struct {
+    U32                                         :  3;  // Bits 2:0
+    U32 Stop_Base_Sequence_On_Wrap_Trigger      :  1;  // Bits 3:3
+    U32                                         :  1;  // Bits 4:4
+    U32 Address_Update_Rate_Mode                :  1;  // Bits 5:5
+    U32                                         :  1;  // Bits 6:6
+    U32 Enable_Dummy_Reads                      :  1;  // Bits 7:7
+    U32                                         :  2;  // Bits 9:8
+    U32 Enable_Constant_Write_Strobe            :  1;  // Bits 10:10
+    U32 Global_Control                          :  1;  // Bits 11:11
+    U32 Initialization_Mode                     :  2;  // Bits 13:12
+    U32                                         :  2;  // Bits 15:14
+    U32 Loopcount                               :  5;  // Bits 20:16  ** Does not exist in C0 **
+    U32                                         :  3;  // Bits 23:21
+    U32 Subsequence_Start_Pointer               :  3;  // Bits 26:24
+    U32                                         :  1;  // Bits 27:27
+    U32 Subsequence_End_Pointer                 :  3;  // Bits 30:28
+    U32                                         :  1;  // Bits 31:31
+    U32 Start_Test_Delay                        :  10;  // Bits 41:32
+    U32                                         :  22;  // Bits 63:42
+  } Bits;
+  U64 Data;
+  U32 Data32[2];
+  U16 Data16[4];
+  U8  Data8[8];
+} MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_STRUCT;
+
+typedef union {
+  struct {
+    U32                                         :  3;  // Bits 2:0
+    U32 Stop_Base_Sequence_On_Wrap_Trigger      :  1;  // Bits 3:3
+    U32                                         :  1;  // Bits 4:4
+    U32 Address_Update_Rate_Mode                :  1;  // Bits 5:5
+    U32                                         :  1;  // Bits 6:6
+    U32 Enable_Dummy_Reads                      :  1;  // Bits 7:7
+    U32                                         :  2;  // Bits 9:8
+    U32 Enable_Constant_Write_Strobe            :  1;  // Bits 10:10
+    U32 Global_Control                          :  1;  // Bits 11:11
+    U32 Initialization_Mode                     :  2;  // Bits 13:12
+    U32                                         :  2;  // Bits 15:14
+    U32 Loopcount                               :  5;  // Bits 20:16  ** Does not exist in C0 **
+    U32                                         :  3;  // Bits 23:21
+    U32 Subsequence_Start_Pointer               :  3;  // Bits 26:24
+    U32                                         :  1;  // Bits 27:27
+    U32 Subsequence_End_Pointer                 :  3;  // Bits 30:28
+    U32                                         :  1;  // Bits 31:31
+    U32 Start_Test_Delay                        :  10;  // Bits 41:32
+    U32                                         :  22;  // Bits 63:42
+  } Bits;
+  U64 Data;
+  U32 Data32[2];
+  U16 Data16[4];
+  U8  Data8[8];
+} MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_STRUCT;
+
+typedef union {
+  struct {
+    U32 Local_Start_Test                        :  1;  // Bits 0:0
+    U32 Local_Stop_Test                         :  1;  // Bits 1:1
+    U32 Local_Clear_Errors                      :  1;  // Bits 2:2
+    U32                                         :  29;  // Bits 31:3
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCDFXS_CR_REUT_CH_SEQ_CTL_MCMAIN_0_STRUCT;
+
+typedef union {
+  struct {
+    U32 Local_Start_Test                        :  1;  // Bits 0:0
+    U32 Local_Stop_Test                         :  1;  // Bits 1:1
+    U32 Local_Clear_Errors                      :  1;  // Bits 2:2
+    U32                                         :  29;  // Bits 31:3
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCDFXS_CR_REUT_CH_SEQ_CTL_MCMAIN_1_STRUCT;
+
+typedef union {
+  struct {
+    U32 Current_Loopcount                       :  32;  // Bits 31:0
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCDFXS_CR_REUT_CH_SEQ_LOOPCOUNT_STATUS_MCMAIN_0_STRUCT;
+
+typedef union {
+  struct {
+    U32 Current_Loopcount                       :  32;  // Bits 31:0
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCDFXS_CR_REUT_CH_SEQ_LOOPCOUNT_STATUS_MCMAIN_1_STRUCT;
+
+typedef union {
+  struct {
+    U32 Current_Subsequence_Pointer             :  3;  // Bits 2:0
+    U32                                         :  29;  // Bits 31:3
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCDFXS_CR_REUT_CH_SEQ_SUBSEQ_PNTR_MCMAIN_0_STRUCT;
+
+typedef union {
+  struct {
+    U32 Current_Subsequence_Pointer             :  3;  // Bits 2:0
+    U32                                         :  29;  // Bits 31:3
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCDFXS_CR_REUT_CH_SEQ_SUBSEQ_PNTR_MCMAIN_1_STRUCT;
+
+typedef union {
+  struct {
+    U32 Current_Cacheline                       :  16;  // Bits 15:0
+    U32                                         :  16;  // Bits 31:16
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCDFXS_CR_REUT_CH_SEQ_CACHELINE_STATUS_MCMAIN_0_STRUCT;
+
+typedef union {
+  struct {
+    U32 Current_Cacheline                       :  16;  // Bits 15:0
+    U32                                         :  16;  // Bits 31:16
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCDFXS_CR_REUT_CH_SEQ_CACHELINE_STATUS_MCMAIN_1_STRUCT;
+
+typedef union {
+  struct {
+    U32                                         :  3;  // Bits 2:0
+    U32 Column_Address                          :  8;  // Bits 10:3
+    U32                                         :  13;  // Bits 23:11
+    U32 Row_Address                             :  16;  // Bits 39:24
+    U32                                         :  8;  // Bits 47:40
+    U32 Bank_Address                            :  3;  // Bits 50:48
+    U32                                         :  5;  // Bits 55:51
+    U32 Rank_Address                            :  3;  // Bits 58:56
+    U32                                         :  5;  // Bits 63:59
+  } Bits;
+  U64 Data;
+  U32 Data32[2];
+  U16 Data16[4];
+  U8  Data8[8];
+} MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_0_STRUCT;
+
+typedef union {
+  struct {
+    U32                                         :  3;  // Bits 2:0
+    U32 Column_Address                          :  8;  // Bits 10:3
+    U32                                         :  13;  // Bits 23:11
+    U32 Row_Address                             :  16;  // Bits 39:24
+    U32                                         :  8;  // Bits 47:40
+    U32 Bank_Address                            :  3;  // Bits 50:48
+    U32                                         :  5;  // Bits 55:51
+    U32 Rank_Address                            :  3;  // Bits 58:56
+    U32                                         :  5;  // Bits 63:59
+  } Bits;
+  U64 Data;
+  U32 Data32[2];
+  U16 Data16[4];
+  U8  Data8[8];
+} MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_1_STRUCT;
+
+typedef union {
+  struct {
+    U32                                         :  3;  // Bits 2:0
+    U32 Column_Address                          :  8;  // Bits 10:3
+    U32                                         :  13;  // Bits 23:11
+    U32 Row_Address                             :  16;  // Bits 39:24
+    U32                                         :  8;  // Bits 47:40
+    U32 Bank_Address                            :  3;  // Bits 50:48
+    U32                                         :  5;  // Bits 55:51
+    U32 Rank_Address                            :  3;  // Bits 58:56
+    U32                                         :  5;  // Bits 63:59
+  } Bits;
+  U64 Data;
+  U32 Data32[2];
+  U16 Data16[4];
+  U8  Data8[8];
+} MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_0_STRUCT;
+
+typedef union {
+  struct {
+    U32                                         :  3;  // Bits 2:0
+    U32 Column_Address                          :  8;  // Bits 10:3
+    U32                                         :  13;  // Bits 23:11
+    U32 Row_Address                             :  16;  // Bits 39:24
+    U32                                         :  8;  // Bits 47:40
+    U32 Bank_Address                            :  3;  // Bits 50:48
+    U32                                         :  5;  // Bits 55:51
+    U32 Rank_Address                            :  3;  // Bits 58:56
+    U32                                         :  5;  // Bits 63:59
+  } Bits;
+  U64 Data;
+  U32 Data32[2];
+  U16 Data16[4];
+  U8  Data8[8];
+} MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_1_STRUCT;
+
+typedef union {
+  struct {
+    U32                                         :  3;  // Bits 2:0
+    U32 Column_Address                          :  8;  // Bits 10:3
+    U32                                         :  13;  // Bits 23:11
+    U32 Row_Address                             :  16;  // Bits 39:24
+    U32                                         :  8;  // Bits 47:40
+    U32 Bank_Address                            :  3;  // Bits 50:48
+    U32                                         :  5;  // Bits 55:51
+    U32 Rank_Address                            :  3;  // Bits 58:56
+    U32                                         :  5;  // Bits 63:59
+  } Bits;
+  U64 Data;
+  U32 Data32[2];
+  U16 Data16[4];
+  U8  Data8[8];
+} MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_0_STRUCT;
+
+typedef union {
+  struct {
+    U32                                         :  3;  // Bits 2:0
+    U32 Column_Address                          :  8;  // Bits 10:3
+    U32                                         :  13;  // Bits 23:11
+    U32 Row_Address                             :  16;  // Bits 39:24
+    U32                                         :  8;  // Bits 47:40
+    U32 Bank_Address                            :  3;  // Bits 50:48
+    U32                                         :  5;  // Bits 55:51
+    U32 Rank_Address                            :  3;  // Bits 58:56
+    U32                                         :  5;  // Bits 63:59
+  } Bits;
+  U64 Data;
+  U32 Data32[2];
+  U16 Data16[4];
+  U8  Data8[8];
+} MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_1_STRUCT;
+
+typedef union {
+  struct {
+    U32 Base_Column_Address_Order               :  2;  // Bits 1:0
+    U32 Base_Row_Address_Order                  :  2;  // Bits 3:2
+    U32 Base_Bank_Address_Order                 :  2;  // Bits 5:4
+    U32 Base_Rank_Address_Order                 :  2;  // Bits 7:6
+    U32                                         :  5;  // Bits 12:8
+    U32 Base_Address_Invert_Rate                :  3;  // Bits 15:13
+    U32                                         :  4;  // Bits 19:16
+    U32 Column_Base_Address_Invert_Enable       :  1;  // Bits 20:20
+    U32 Row_Base_Address_Invert_Enable          :  1;  // Bits 21:21
+    U32 Bank_Base_Address_Invert_Enable         :  1;  // Bits 22:22
+    U32 Rank_Base_Address_Invert_Enable         :  1;  // Bits 23:23
+    U32 Column_Base_Wrap_Trigger_Enable         :  1;  // Bits 24:24
+    U32 Row_Base_Wrap_Trigger_Enable            :  1;  // Bits 25:25
+    U32 Bank_Base_Wrap_Trigger_Enable           :  1;  // Bits 26:26
+    U32 Rank_Base_Wrap_Trigger_Enable           :  1;  // Bits 27:27
+    U32 Column_Base_Wrap_Carry_Enable           :  1;  // Bits 28:28
+    U32 Row_Base_Wrap_Carry_Enable              :  1;  // Bits 29:29
+    U32 Bank_Base_Wrap_Carry_Enable             :  1;  // Bits 30:30
+    U32 Rank_Base_Wrap_Carry_Enable             :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_STRUCT;
+
+typedef union {
+  struct {
+    U32 Base_Column_Address_Order               :  2;  // Bits 1:0
+    U32 Base_Row_Address_Order                  :  2;  // Bits 3:2
+    U32 Base_Bank_Address_Order                 :  2;  // Bits 5:4
+    U32 Base_Rank_Address_Order                 :  2;  // Bits 7:6
+    U32                                         :  5;  // Bits 12:8
+    U32 Base_Address_Invert_Rate                :  3;  // Bits 15:13
+    U32                                         :  4;  // Bits 19:16
+    U32 Column_Base_Address_Invert_Enable       :  1;  // Bits 20:20
+    U32 Row_Base_Address_Invert_Enable          :  1;  // Bits 21:21
+    U32 Bank_Base_Address_Invert_Enable         :  1;  // Bits 22:22
+    U32 Rank_Base_Address_Invert_Enable         :  1;  // Bits 23:23
+    U32 Column_Base_Wrap_Trigger_Enable         :  1;  // Bits 24:24
+    U32 Row_Base_Wrap_Trigger_Enable            :  1;  // Bits 25:25
+    U32 Bank_Base_Wrap_Trigger_Enable           :  1;  // Bits 26:26
+    U32 Rank_Base_Wrap_Trigger_Enable           :  1;  // Bits 27:27
+    U32 Column_Base_Wrap_Carry_Enable           :  1;  // Bits 28:28
+    U32 Row_Base_Wrap_Carry_Enable              :  1;  // Bits 29:29
+    U32 Bank_Base_Wrap_Carry_Enable             :  1;  // Bits 30:30
+    U32 Rank_Base_Wrap_Carry_Enable             :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_STRUCT;
+
+typedef union {
+  struct {
+    U32                                         :  3;  // Bits 2:0
+    U32 Column_Base_Address_Increment           :  8;  // Bits 10:3
+    U32                                         :  1;  // Bits 11:11
+    U32 Column_Base_Address_Update_Rate         :  5;  // Bits 16:12
+    U32                                         :  2;  // Bits 18:17
+    U32 Column_Base_Address_Update_Scale        :  1;  // Bits 19:19
+    U32 Row_Base_Address_Increment              :  12;  // Bits 31:20
+    U32 Row_Base_Address_Update_Rate            :  4;  // Bits 35:32
+    U32                                         :  1;  // Bits 36:36
+    U32 Row_Base_Address_Update_Scale           :  1;  // Bits 37:37
+    U32 Bank_Base_Address_Increment             :  3;  // Bits 40:38
+    U32                                         :  3;  // Bits 43:41
+    U32 Bank_Base_Address_Update_Rate           :  5;  // Bits 48:44
+    U32                                         :  2;  // Bits 50:49
+    U32 Bank_Base_Address_Update_Scale          :  1;  // Bits 51:51
+    U32 Rank_Base_Address_Increment             :  3;  // Bits 54:52
+    U32                                         :  1;  // Bits 55:55
+    U32 Rank_Base_Address_Update_Rate           :  5;  // Bits 60:56
+    U32                                         :  2;  // Bits 62:61
+    U32 Rank_Base_Address_Update_Scale          :  1;  // Bits 63:63
+  } Bits;
+  U64 Data;
+  U32 Data32[2];
+  U16 Data16[4];
+  U8  Data8[8];
+} MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_STRUCT;
+
+typedef union {
+  struct {
+    U32                                         :  3;  // Bits 2:0
+    U32 Column_Base_Address_Increment           :  8;  // Bits 10:3
+    U32                                         :  1;  // Bits 11:11
+    U32 Column_Base_Address_Update_Rate         :  5;  // Bits 16:12
+    U32                                         :  2;  // Bits 18:17
+    U32 Column_Base_Address_Update_Scale        :  1;  // Bits 19:19
+    U32 Row_Base_Address_Increment              :  12;  // Bits 31:20
+    U32 Row_Base_Address_Update_Rate            :  4;  // Bits 35:32
+    U32                                         :  1;  // Bits 36:36
+    U32 Row_Base_Address_Update_Scale           :  1;  // Bits 37:37
+    U32 Bank_Base_Address_Increment             :  3;  // Bits 40:38
+    U32                                         :  3;  // Bits 43:41
+    U32 Bank_Base_Address_Update_Rate           :  5;  // Bits 48:44
+    U32                                         :  2;  // Bits 50:49
+    U32 Bank_Base_Address_Update_Scale          :  1;  // Bits 51:51
+    U32 Rank_Base_Address_Increment             :  3;  // Bits 54:52
+    U32                                         :  1;  // Bits 55:55
+    U32 Rank_Base_Address_Update_Rate           :  5;  // Bits 60:56
+    U32                                         :  2;  // Bits 62:61
+    U32 Rank_Base_Address_Update_Scale          :  1;  // Bits 63:63
+  } Bits;
+  U64 Data;
+  U32 Data32[2];
+  U16 Data16[4];
+  U8  Data8[8];
+} MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_STRUCT;
+
+typedef union {
+  struct {
+    U32                                         :  3;  // Bits 2:0
+    U32 Column_Address                          :  8;  // Bits 10:3
+    U32                                         :  13;  // Bits 23:11
+    U32 Row_Address                             :  16;  // Bits 39:24
+    U32                                         :  24;  // Bits 63:40
+  } Bits;
+  U64 Data;
+  U32 Data32[2];
+  U16 Data16[4];
+  U8  Data8[8];
+} MCDFXS_CR_REUT_CH_SEQ_OFFSET_ADDR_CURRENT_MCMAIN_0_STRUCT;
+
+typedef union {
+  struct {
+    U32                                         :  3;  // Bits 2:0
+    U32 Column_Address                          :  8;  // Bits 10:3
+    U32                                         :  13;  // Bits 23:11
+    U32 Row_Address                             :  16;  // Bits 39:24
+    U32                                         :  24;  // Bits 63:40
+  } Bits;
+  U64 Data;
+  U32 Data32[2];
+  U16 Data16[4];
+  U8  Data8[8];
+} MCDFXS_CR_REUT_CH_SEQ_OFFSET_ADDR_CURRENT_MCMAIN_1_STRUCT;
+
+typedef union {
+  struct {
+    U32 Logical_to_Physical_Rank0_Mapping       :  2;  // Bits 1:0
+    U32                                         :  2;  // Bits 3:2
+    U32 Logical_to_Physical_Rank1_Mapping       :  2;  // Bits 5:4
+    U32                                         :  2;  // Bits 7:6
+    U32 Logical_to_Physical_Rank2_Mapping       :  2;  // Bits 9:8
+    U32                                         :  2;  // Bits 11:10
+    U32 Logical_to_Physical_Rank3_Mapping       :  2;  // Bits 13:12
+    U32                                         :  2;  // Bits 15:14
+    U32 Logical_to_Physical_Rank4_Mapping       :  2;  // Bits 17:16
+    U32                                         :  2;  // Bits 19:18
+    U32 Logical_to_Physical_Rank5_Mapping       :  2;  // Bits 21:20
+    U32                                         :  2;  // Bits 23:22
+    U32 Logical_to_Physical_Rank6_Mapping       :  2;  // Bits 25:24
+    U32                                         :  2;  // Bits 27:26
+    U32 Logical_to_Physical_Rank7_Mapping       :  2;  // Bits 29:28
+    U32                                         :  2;  // Bits 31:30
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_0_STRUCT;
+
+typedef union {
+  struct {
+    U32 Logical_to_Physical_Rank0_Mapping       :  2;  // Bits 1:0
+    U32                                         :  2;  // Bits 3:2
+    U32 Logical_to_Physical_Rank1_Mapping       :  2;  // Bits 5:4
+    U32                                         :  2;  // Bits 7:6
+    U32 Logical_to_Physical_Rank2_Mapping       :  2;  // Bits 9:8
+    U32                                         :  2;  // Bits 11:10
+    U32 Logical_to_Physical_Rank3_Mapping       :  2;  // Bits 13:12
+    U32                                         :  2;  // Bits 15:14
+    U32 Logical_to_Physical_Rank4_Mapping       :  2;  // Bits 17:16
+    U32                                         :  2;  // Bits 19:18
+    U32 Logical_to_Physical_Rank5_Mapping       :  2;  // Bits 21:20
+    U32                                         :  2;  // Bits 23:22
+    U32 Logical_to_Physical_Rank6_Mapping       :  2;  // Bits 25:24
+    U32                                         :  2;  // Bits 27:26
+    U32 Logical_to_Physical_Rank7_Mapping       :  2;  // Bits 29:28
+    U32                                         :  2;  // Bits 31:30
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_1_STRUCT;
+
+typedef union {
+  struct {
+    U32 Logical_to_Physical_Row0_Swizzle        :  4;  // Bits 3:0
+    U32                                         :  1;  // Bits 4:4
+    U32 Logical_to_Physical_Row1_Swizzle        :  4;  // Bits 8:5
+    U32                                         :  1;  // Bits 9:9
+    U32 Logical_to_Physical_Row2_Swizzle        :  4;  // Bits 13:10
+    U32                                         :  1;  // Bits 14:14
+    U32 Logical_to_Physical_Row3_Swizzle        :  4;  // Bits 18:15
+    U32                                         :  1;  // Bits 19:19
+    U32 Logical_to_Physical_Row4_Swizzle        :  4;  // Bits 23:20
+    U32                                         :  1;  // Bits 24:24
+    U32 Logical_to_Physical_Row5_Swizzle        :  4;  // Bits 28:25
+    U32                                         :  3;  // Bits 31:29
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_0_STRUCT;
+
+typedef union {
+  struct {
+    U32 Logical_to_Physical_Row0_Swizzle        :  4;  // Bits 3:0
+    U32                                         :  1;  // Bits 4:4
+    U32 Logical_to_Physical_Row1_Swizzle        :  4;  // Bits 8:5
+    U32                                         :  1;  // Bits 9:9
+    U32 Logical_to_Physical_Row2_Swizzle        :  4;  // Bits 13:10
+    U32                                         :  1;  // Bits 14:14
+    U32 Logical_to_Physical_Row3_Swizzle        :  4;  // Bits 18:15
+    U32                                         :  1;  // Bits 19:19
+    U32 Logical_to_Physical_Row4_Swizzle        :  4;  // Bits 23:20
+    U32                                         :  1;  // Bits 24:24
+    U32 Logical_to_Physical_Row5_Swizzle        :  4;  // Bits 28:25
+    U32                                         :  3;  // Bits 31:29
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_1_STRUCT;
+
+typedef union {
+  struct {
+    U32 Logical_to_Physical_Row6_Swizzle        :  4;  // Bits 3:0
+    U32                                         :  1;  // Bits 4:4
+    U32 Logical_to_Physical_Row7_Swizzle        :  4;  // Bits 8:5
+    U32                                         :  1;  // Bits 9:9
+    U32 Logical_to_Physical_Row8_Swizzle        :  4;  // Bits 13:10
+    U32                                         :  1;  // Bits 14:14
+    U32 Logical_to_Physical_Row9_Swizzle        :  4;  // Bits 18:15
+    U32                                         :  1;  // Bits 19:19
+    U32 Logical_to_Physical_Row10_Swizzle       :  4;  // Bits 23:20
+    U32                                         :  1;  // Bits 24:24
+    U32 Logical_to_Physical_Row11_Swizzle       :  4;  // Bits 28:25
+    U32                                         :  1;  // Bits 29:29
+    U32 Logical_to_Physical_Row12_Swizzle       :  4;  // Bits 33:30
+    U32                                         :  1;  // Bits 34:34
+    U32 Logical_to_Physical_Row13_Swizzle       :  4;  // Bits 38:35
+    U32                                         :  1;  // Bits 39:39
+    U32 Logical_to_Physical_Row14_Swizzle       :  4;  // Bits 43:40
+    U32                                         :  1;  // Bits 44:44
+    U32 Logical_to_Physical_Row15_Swizzle       :  4;  // Bits 48:45
+    U32                                         :  15;  // Bits 63:49
+  } Bits;
+  U64 Data;
+  U32 Data32[2];
+  U16 Data16[4];
+  U8  Data8[8];
+} MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_STRUCT;
+
+typedef union {
+  struct {
+    U32 Logical_to_Physical_Row6_Swizzle        :  4;  // Bits 3:0
+    U32                                         :  1;  // Bits 4:4
+    U32 Logical_to_Physical_Row7_Swizzle        :  4;  // Bits 8:5
+    U32                                         :  1;  // Bits 9:9
+    U32 Logical_to_Physical_Row8_Swizzle        :  4;  // Bits 13:10
+    U32                                         :  1;  // Bits 14:14
+    U32 Logical_to_Physical_Row9_Swizzle        :  4;  // Bits 18:15
+    U32                                         :  1;  // Bits 19:19
+    U32 Logical_to_Physical_Row10_Swizzle       :  4;  // Bits 23:20
+    U32                                         :  1;  // Bits 24:24
+    U32 Logical_to_Physical_Row11_Swizzle       :  4;  // Bits 28:25
+    U32                                         :  1;  // Bits 29:29
+    U32 Logical_to_Physical_Row12_Swizzle       :  4;  // Bits 33:30
+    U32                                         :  1;  // Bits 34:34
+    U32 Logical_to_Physical_Row13_Swizzle       :  4;  // Bits 38:35
+    U32                                         :  1;  // Bits 39:39
+    U32 Logical_to_Physical_Row14_Swizzle       :  4;  // Bits 43:40
+    U32                                         :  1;  // Bits 44:44
+    U32 Logical_to_Physical_Row15_Swizzle       :  4;  // Bits 48:45
+    U32                                         :  15;  // Bits 63:49
+  } Bits;
+  U64 Data;
+  U32 Data32[2];
+  U16 Data16[4];
+  U8  Data8[8];
+} MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_STRUCT;
+
+typedef union {
+  struct {
+    U32 Dummy_Read_Row_Current_Address          :  16;  // Bits 15:0
+    U32                                         :  8;  // Bits 23:16
+    U32 Dummy_Read_Bank_Current_Address         :  3;  // Bits 26:24
+    U32                                         :  5;  // Bits 31:27
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_ADDRESS_MCMAIN_0_STRUCT;
+
+typedef union {
+  struct {
+    U32 Dummy_Read_Row_Current_Address          :  16;  // Bits 15:0
+    U32                                         :  8;  // Bits 23:16
+    U32 Dummy_Read_Bank_Current_Address         :  3;  // Bits 26:24
+    U32                                         :  5;  // Bits 31:27
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_ADDRESS_MCMAIN_1_STRUCT;
+
+typedef union {
+  struct {
+    U32 Dummy_Read_Bank_Mask                    :  8;  // Bits 7:0
+    U32                                         :  24;  // Bits 31:8
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_MASK_MCMAIN_0_STRUCT;
+
+typedef union {
+  struct {
+    U32 Dummy_Read_Bank_Mask                    :  8;  // Bits 7:0
+    U32                                         :  24;  // Bits 31:8
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_MASK_MCMAIN_1_STRUCT;
+
+typedef union {
+  struct {
+    U32 L_DummyRead_Select                      :  1;  // Bits 0:0
+    U32 Enable_Sweep_Frequency                  :  1;  // Bits 1:1
+    U32                                         :  6;  // Bits 7:2
+    U32 L_counter                               :  8;  // Bits 15:8
+    U32 M_counter                               :  8;  // Bits 23:16
+    U32 N_Counter                               :  8;  // Bits 31:24
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_0_STRUCT;
+
+typedef union {
+  struct {
+    U32 L_DummyRead_Select                      :  1;  // Bits 0:0
+    U32 Enable_Sweep_Frequency                  :  1;  // Bits 1:1
+    U32                                         :  6;  // Bits 7:2
+    U32 L_counter                               :  8;  // Bits 15:8
+    U32 M_counter                               :  8;  // Bits 23:16
+    U32 N_Counter                               :  8;  // Bits 31:24
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_1_STRUCT;
+
+typedef union {
+  struct {
+    U32 EN_CLK                                  :  1;  // Bits 0:0
+    U32 L0_DATA_BYTE_SEL                        :  7;  // Bits 7:1
+    U32 L0_BYP_SEL                              :  1;  // Bits 8:8
+    U32 L1_DATA_BYTE_SEL                        :  7;  // Bits 15:9
+    U32 L1_BYP_SEL                              :  1;  // Bits 16:16
+    U32                                         :  15;  // Bits 31:17
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCDFXS_CR_VISA_CTL_MCDFXS_MCMAIN_STRUCT;
+
+typedef union {
+  struct {
+    U32 Trigger_In_Global_Start                 :  1;  // Bits 0:0
+    U32 Trigger_Out_Global_Start                :  1;  // Bits 1:1
+    U32                                         :  5;  // Bits 6:2
+    U32 Trigger_Out_On_Error_0                  :  1;  // Bits 7:7
+    U32 Trigger_Out_On_Error_1                  :  1;  // Bits 8:8
+    U32                                         :  6;  // Bits 14:9
+    U32 Trigger_Out_On_Channel_Test_Done_Status_0:  1;  // Bits 15:15
+    U32 Trigger_Out_On_Channel_Test_Done_Status_1:  1;  // Bits 16:16
+    U32                                         :  15;  // Bits 31:17
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCDFXS_CR_REUT_CH_ERR_TRIGGER_CTL_MCMAIN_STRUCT;
+
+typedef union {
+  struct {
+    U32 Loopcount_Limit                         :  32;  // Bits 31:0
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCDFXS_CR_REUT_CH_SEQ_LOOPCOUNT_LIMIT_MCMAIN_0_STRUCT;
+
+typedef union {
+  struct {
+    U32 Loopcount_Limit                         :  32;  // Bits 31:0
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCDFXS_CR_REUT_CH_SEQ_LOOPCOUNT_LIMIT_MCMAIN_1_STRUCT;
+
+typedef union {
+  struct {
+    U32 tRCD                                    :  5;  // Bits 4:0
+    U32 tRP                                     :  5;  // Bits 9:5
+    U32 tRAS                                    :  6;  // Bits 15:10
+    U32 tRDPRE                                  :  4;  // Bits 19:16
+    U32 tWRPRE                                  :  6;  // Bits 25:20
+    U32 tRRD                                    :  4;  // Bits 29:26
+    U32 tRPab_ext                               :  2;  // Bits 31:30
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCSCHEDS_CR_TC_BANK_STRUCT;
+
+typedef union {
+  struct {
+    U32 tCKE                                    :  4;  // Bits 3:0
+    U32 tFAW                                    :  8;  // Bits 11:4
+    U32 tRDRD                                   :  3;  // Bits 14:12
+    U32 tRDRD_dr                                :  4;  // Bits 18:15
+    U32 tRDRD_dd                                :  4;  // Bits 22:19
+    U32 tRDPDEN                                 :  5;  // Bits 27:23
+    U32                                         :  1;  // Bits 28:28
+    U32 CMD_3st                                 :  1;  // Bits 29:29
+    U32 CMD_stretch                             :  2;  // Bits 31:30
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCSCHEDS_CR_TC_BANK_RANK_A_STRUCT;
+
+typedef union {
+  struct {
+    U32 tWRRD                                   :  6;  // Bits 5:0
+    U32 tWRRD_dr                                :  4;  // Bits 9:6
+    U32 tWRRD_dd                                :  4;  // Bits 13:10
+    U32 tWRWR                                   :  3;  // Bits 16:14
+    U32 tWRWR_dr                                :  4;  // Bits 20:17
+    U32 tWRWR_dd                                :  4;  // Bits 24:21
+    U32 tWRPDEN                                 :  6;  // Bits 30:25
+    U32 Dec_WRD                                 :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCSCHEDS_CR_TC_BANK_RANK_B_STRUCT;
+
+typedef union {
+  struct {
+    U32 tXPDLL                                  :  6;  // Bits 5:0
+    U32 tXP                                     :  4;  // Bits 9:6
+    U32 TAONPD                                  :  4;  // Bits 13:10
+    U32 tRDWR                                   :  5;  // Bits 18:14
+    U32 tRDWR_dr                                :  5;  // Bits 23:19
+    U32 tRDWR_dd                                :  5;  // Bits 28:24
+    U32                                         :  3;  // Bits 31:29
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCSCHEDS_CR_TC_BANK_RANK_C_STRUCT;
+
+typedef union {
+  struct {
+    U32 enable_cmd_rate_limit                   :  1;  // Bits 0:0
+    U32 cmd_rate_limit                          :  3;  // Bits 3:1
+    U32 reset_on_command                        :  4;  // Bits 7:4
+    U32 reset_delay                             :  4;  // Bits 11:8
+    U32 ck_to_cke_delay                         :  2;  // Bits 13:12
+    U32 spare                                   :  17;  // Bits 30:14
+    U32 init_mrw_2n_cs                          :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCSCHEDS_CR_CMD_RATE_STRUCT;
+
+typedef union {
+  struct {
+    U32 tCL                                     :  5;  // Bits 4:0
+    U32 tWCL                                    :  5;  // Bits 9:5
+    U32 tCPDED                                  :  2;  // Bits 11:10
+    U32 tPRPDEN                                 :  2;  // Bits 13:12
+    U32 Odt_Read_Delay                          :  3;  // Bits 16:14
+    U32 Odt_Read_Duration                       :  2;  // Bits 18:17
+    U32 Odt_Write_Duration                      :  2;  // Bits 20:19
+    U32                                         :  11;  // Bits 31:21
+  } Bits;
+#ifdef ULT_FLAG
+  struct {
+    U32 tCL                                     :  5;  // Bits 4:0
+    U32 tWCL                                    :  5;  // Bits 9:5
+    U32 tCPDED                                  :  2;  // Bits 11:10
+    U32 tPRPDEN                                 :  2;  // Bits 13:12
+    U32 Odt_Read_Delay                          :  3;  // Bits 16:14
+    U32 Odt_Read_Duration                       :  2;  // Bits 18:17
+    U32 Odt_Write_Duration                      :  3;  // Bits 21:19
+    U32 Odt_Write_Delay                         :  3;  // Bits 24:22
+    U32 Odt_Always_Rank0                        :  1;  // Bits 25:25
+    U32 cmd_delay                               :  2;  // Bits 27:26
+    U32                                         :  4;  // Bits 31:28
+  } UltBits;
+#endif //ULT_FLAG
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCSCHEDS_CR_TC_BANK_RANK_D_STRUCT;
+
+typedef union {
+  struct {
+    U32 dis_opp_cas                             :  1;  // Bits 0:0
+    U32 dis_opp_is_cas                          :  1;  // Bits 1:1
+    U32 dis_opp_ras                             :  1;  // Bits 2:2
+    U32 dis_opp_is_ras                          :  1;  // Bits 3:3
+    U32 dis_1c_byp                              :  1;  // Bits 4:4
+    U32 dis_2c_byp                              :  1;  // Bits 5:5
+    U32 dis_deprd_opt                           :  1;  // Bits 6:6
+    U32 dis_pt_it                               :  1;  // Bits 7:7
+    U32 dis_prcnt_ring                          :  1;  // Bits 8:8
+    U32 dis_prcnt_sa                            :  1;  // Bits 9:9
+    U32 dis_blkr_ph                             :  1;  // Bits 10:10
+    U32 dis_blkr_pe                             :  1;  // Bits 11:11
+    U32 dis_blkr_pm                             :  1;  // Bits 12:12
+    U32 dis_odt                                 :  1;  // Bits 13:13
+    U32 OE_alw_off                              :  1;  // Bits 14:14
+    U32                                         :  1;  // Bits 15:15
+    U32 dis_aom                                 :  1;  // Bits 16:16
+    U32 block_rpq                               :  1;  // Bits 17:17
+    U32 block_wpq                               :  1;  // Bits 18:18
+    U32 invert_align                            :  1;  // Bits 19:19
+    U32 dis_write_gap                           :  1;  // Bits 20:20
+    U32 dis_zq                                  :  1;  // Bits 21:21
+    U32 dis_tt                                  :  1;  // Bits 22:22
+    U32 dis_opp_ref                             :  1;  // Bits 23:23
+    U32 Long_ZQ                                 :  1;  // Bits 24:24
+    U32 dis_srx_zq                              :  1;  // Bits 25:25
+    U32 Serialize_ZQ                            :  1;  // Bits 26:26
+    U32 ZQ_fast_exec                            :  1;  // Bits 27:27
+    U32 Dis_DriveNop                            :  1;  // Bits 28:28
+    U32 Pres_WDB_Ent                            :  1;  // Bits 29:29
+    U32 dis_clk_gate                            :  1;  // Bits 30:30
+    U32                                         :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCSCHEDS_CR_SCHED_CBIT_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lat_R0D0                                :  6;  // Bits 5:0
+    U32                                         :  2;  // Bits 7:6
+    U32 Lat_R1D0                                :  6;  // Bits 13:8
+    U32                                         :  2;  // Bits 15:14
+    U32 Lat_R0D1                                :  6;  // Bits 21:16
+    U32                                         :  2;  // Bits 23:22
+    U32 Lat_R1D1                                :  6;  // Bits 29:24
+    U32                                         :  2;  // Bits 31:30
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCSCHEDS_CR_SC_ROUNDT_LAT_STRUCT;
+
+typedef union {
+  struct {
+    U32 IOLAT_R0D0                              :  4;  // Bits 3:0
+    U32 IOLAT_R1D0                              :  4;  // Bits 7:4
+    U32 IOLAT_R0D1                              :  4;  // Bits 11:8
+    U32 IOLAT_R1D1                              :  4;  // Bits 15:12
+    U32 RT_IOCOMP                               :  6;  // Bits 21:16
+    U32                                         :  8;  // Bits 29:22
+    U32 three_channels                          :  1;  // Bits 30:30
+    U32 DIS_RT_CLK_GATE                         :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCSCHEDS_CR_SC_IO_LATENCY_STRUCT;
+
+typedef union {
+  struct {
+    U32 DATA                                    :  32;  // Bits 31:0
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCSCHEDS_CR_ROUND_TRIP_DFT_DATA_STRUCT;
+
+typedef union {
+  struct {
+    U32 WDAR                                    :  1;  // Bits 0:0
+    U32 safe_mask_sel                           :  3;  // Bits 3:1
+    U32 force_rcv_en                            :  1;  // Bits 4:4
+    U32                                         :  3;  // Bits 7:5
+    U32 DDR_QUAL                                :  2;  // Bits 9:8
+    U32 Qual_length                             :  2;  // Bits 11:10
+    U32 WDB_Block_En                            :  1;  // Bits 12:12
+    U32 RT_DFT_READ_PTR                         :  4;  // Bits 16:13
+    U32 RT_DFT_READ_ENABLE                      :  1;  // Bits 17:17
+    U32 RT_DFT_READ_SEL_ADDR                    :  1;  // Bits 18:18
+    U32                                         :  13;  // Bits 31:19
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCSCHEDS_CR_DFT_MISC_STRUCT;
+
+typedef union {
+  struct {
+    U32 ECC                                     :  8;  // Bits 7:0
+    U32 RRD_DFT_Mode                            :  2;  // Bits 9:8
+    U32 LFSR_Seed_Index                         :  5;  // Bits 14:10
+    U32 Inversion_Mode                          :  1;  // Bits 15:15
+    U32                                         :  16;  // Bits 31:16
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCSCHEDS_CR_READ_RETURN_DFT_STRUCT;
+
+typedef union {
+  struct {
+    U32 dis_imph_error                          :  1;  // Bits 0:0
+    U32                                         :  7;  // Bits 7:1
+    U32 dis_async_odt                           :  1;  // Bits 8:8
+    U32                                         :  23;  // Bits 31:9
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCSCHEDS_CR_SCHED_SECOND_CBIT_STRUCT;
+
+typedef union {
+  struct {
+    U32 Mux0_Control                            :  2;  // Bits 1:0
+    U32                                         :  1;  // Bits 2:2
+    U32 Mux1_Control                            :  2;  // Bits 4:3
+    U32                                         :  1;  // Bits 5:5
+    U32 Mux2_Control                            :  2;  // Bits 7:6
+    U32                                         :  6;  // Bits 13:8
+    U32 ECC_Replace_Byte_Control                :  1;  // Bits 14:14
+    U32 ECC_Data_Source_Sel                     :  1;  // Bits 15:15
+    U32 Save_LFSR_Seed_Rate                     :  6;  // Bits 21:16
+    U32                                         :  2;  // Bits 23:22
+    U32 Reload_LFSR_Seed_Rate                   :  3;  // Bits 26:24
+    U32                                         :  5;  // Bits 31:27
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_STRUCT;
+
+typedef union {
+  struct {
+    U32 WDB_Current_Read_Pointer                :  6;  // Bits 5:0
+    U32                                         :  26;  // Bits 31:6
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_RD_STATUS_STRUCT;
+
+typedef union {
+  struct {
+    U32 Pattern_Buffer                          :  24;  // Bits 23:0
+    U32                                         :  8;  // Bits 31:24
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_0_STRUCT;
+
+typedef union {
+  struct {
+    U32 Pattern_Buffer                          :  24;  // Bits 23:0
+    U32                                         :  8;  // Bits 31:24
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_1_STRUCT;
+
+typedef union {
+  struct {
+    U32 Pattern_Buffer                          :  24;  // Bits 23:0
+    U32                                         :  8;  // Bits 31:24
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_2_STRUCT;
+
+typedef union {
+  struct {
+    U32 Pattern_Buffer                          :  24;  // Bits 23:0
+    U32                                         :  8;  // Bits 31:24
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_0_STRUCT;
+
+typedef union {
+  struct {
+    U32 Pattern_Buffer                          :  24;  // Bits 23:0
+    U32                                         :  8;  // Bits 31:24
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_1_STRUCT;
+
+typedef union {
+  struct {
+    U32 Pattern_Buffer                          :  24;  // Bits 23:0
+    U32                                         :  8;  // Bits 31:24
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_2_STRUCT;
+
+typedef union {
+  struct {
+    U32 Pattern_Buffer                          :  24;  // Bits 23:0
+    U32                                         :  8;  // Bits 31:24
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_0_STRUCT;
+
+typedef union {
+  struct {
+    U32 Pattern_Buffer                          :  24;  // Bits 23:0
+    U32                                         :  8;  // Bits 31:24
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_1_STRUCT;
+
+typedef union {
+  struct {
+    U32 Pattern_Buffer                          :  24;  // Bits 23:0
+    U32                                         :  8;  // Bits 31:24
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_2_STRUCT;
+
+typedef union {
+  struct {
+    U32 Pattern_Buffer                          :  24;  // Bits 23:0
+    U32                                         :  8;  // Bits 31:24
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_0_STRUCT;
+
+typedef union {
+  struct {
+    U32 Pattern_Buffer                          :  24;  // Bits 23:0
+    U32                                         :  8;  // Bits 31:24
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_1_STRUCT;
+
+typedef union {
+  struct {
+    U32 Pattern_Buffer                          :  24;  // Bits 23:0
+    U32                                         :  8;  // Bits 31:24
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_2_STRUCT;
+
+typedef union {
+  struct {
+    U32 L_data_select                           :  1;  // Bits 0:0
+    U32 Enable_Sweep_Frequency                  :  1;  // Bits 1:1
+    U32                                         :  6;  // Bits 7:2
+    U32 L_counter                               :  8;  // Bits 15:8
+    U32 M_counter                               :  8;  // Bits 23:16
+    U32 N_counter                               :  8;  // Bits 31:24
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_STRUCT;
+
+typedef union {
+  struct {
+    U32 ECC_Inv_or_DC_Enable                    :  8;  // Bits 7:0
+    U32                                         :  8;  // Bits 15:8
+    U32 Inv_or_DC_Shift_Rate                    :  4;  // Bits 19:16
+    U32 DC_Polarity_Control                     :  1;  // Bits 20:20
+    U32                                         :  9;  // Bits 29:21
+    U32 Inv_or_DC_Control                       :  1;  // Bits 30:30
+    U32 Inv_or_DC_Shift_Enable                  :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCSCHEDS_CR_REUT_CH_PAT_WDB_INV_STRUCT;
+
+typedef union {
+  struct {
+    U64 Data_Inv_or_DC_Enable                   :  64;  // Bits 63:0
+  } Bits;
+  U64 Data;
+  U32 Data32[2];
+  U16 Data16[4];
+  U8  Data8[8];
+} MCSCHEDS_CR_REUT_CH_PAT_WDB_DATA_INV_STRUCT;
+
+typedef union {
+  struct {
+    U32 Stop_on_Nth_Error                       :  6;  // Bits 5:0
+    U32                                         :  6;  // Bits 11:6
+    U32 Stop_On_Error_Control                   :  2;  // Bits 13:12
+    U32                                         :  2;  // Bits 15:14
+    U32 Selective_Error_Enable_Chunk            :  8;  // Bits 23:16
+    U32 Selective_Error_Enable_Cacheline        :  8;  // Bits 31:24
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCSCHEDS_CR_REUT_CH_ERR_CTL_STRUCT;
+
+typedef union {
+  struct {
+    U32 ECC_Error_Mask                          :  8;  // Bits 7:0
+    U32                                         :  24;  // Bits 31:8
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCSCHEDS_CR_REUT_CH_ERR_ECC_MASK_STRUCT;
+
+typedef union {
+  struct {
+    U32 Stretch_mode                            :  2;  // Bits 1:0
+    U32                                         :  2;  // Bits 3:2
+    U32 STF                                     :  3;  // Bits 6:4
+    U32                                         :  25;  // Bits 31:7
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCSCHEDS_CR_STM_CONFIG_STRUCT;
+
+typedef union {
+  struct {
+    U32 Priority_count_ring                     :  10;  // Bits 9:0
+    U32                                         :  6;  // Bits 15:10
+    U32 Priority_count_SA                       :  10;  // Bits 25:16
+    U32                                         :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCSCHEDS_CR_SC_PR_CNT_CONFIG_STRUCT;
+
+typedef union {
+  struct {
+    U32 PCIT                                    :  8;  // Bits 7:0
+    U32                                         :  24;  // Bits 31:8
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCSCHEDS_CR_SC_PCIT_STRUCT;
+
+typedef union {
+  struct {
+    U32 PDWN_idle_counter                       :  12;  // Bits 11:0
+    U32 PDWN_mode                               :  4;  // Bits 15:12
+    U32                                         :  16;  // Bits 31:16
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCSCHEDS_CR_PM_PDWN_CONFIG_STRUCT;
+
+typedef union {
+  struct {
+    U32 Count                                   :  32;  // Bits 31:0
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCSCHEDS_CR_ECC_INJECT_COUNT_STRUCT;
+
+typedef union {
+  struct {
+    U32 ECC4ANA_fill                            :  8;  // Bits 7:0
+    U32 ECC4ANA_trigger                         :  2;  // Bits 9:8
+    U32 ECC4ANA_BS                              :  1;  // Bits 10:10
+    U32 ECC_Inject                              :  3;  // Bits 13:11
+    U32 ECC_correction_disable                  :  1;  // Bits 14:14
+    U32 ECC4ANA_Inject                          :  1;  // Bits 15:15
+    U32 DIS_MCA_LOG                             :  1;  // Bits 16:16
+    U32 DIS_PCH_EVENT                           :  1;  // Bits 17:17
+    U32 DIS_PCIE_POISON                         :  1;  // Bits 18:18
+    U32                                         :  13;  // Bits 31:19
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCSCHEDS_CR_ECC_DFT_STRUCT;
+
+typedef union {
+  struct {
+    U32 Data                                    :  18;  // Bits 17:0
+    U32                                         :  13;  // Bits 30:18
+    U32 VORANGE                                 :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCSCHEDS_CR_VISA_CTL_MCSCHEDS_STRUCT;
+
+typedef union {
+  struct {
+    U32 Data                                    :  32;  // Bits 31:0
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCSCHEDS_CR_VISA_XBAR_MCSCHEDS_STRUCT;
+
+typedef union {
+  struct {
+    U32 CERRSTS                                 :  1;  // Bits 0:0
+    U32 MERRSTS                                 :  1;  // Bits 1:1
+    U32                                         :  14;  // Bits 15:2
+    U32 ERRSYND                                 :  8;  // Bits 23:16
+    U32 ERRCHUNK                                :  3;  // Bits 26:24
+    U32 ERRRANK                                 :  2;  // Bits 28:27
+    U32 ERRBANK                                 :  3;  // Bits 31:29
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCSCHEDS_CR_ECCERRLOG0_STRUCT;
+
+typedef union {
+  struct {
+    U32 ERRROW                                  :  16;  // Bits 15:0
+    U32 ERRCOL                                  :  16;  // Bits 31:16
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCSCHEDS_CR_ECCERRLOG1_STRUCT;
+
+typedef union {
+  struct {
+    U32 D0R0                                    :  2;  // Bits 1:0
+    U32 D0R1                                    :  2;  // Bits 3:2
+    U32 D1R0                                    :  2;  // Bits 5:4
+    U32 D1R1                                    :  2;  // Bits 7:6
+    U32                                         :  24;  // Bits 31:8
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCSCHEDS_CR_SC_WR_ADD_DELAY_STRUCT;
+
+typedef union {
+  struct {
+    U32 Dis_Opp_rd                              :  1;  // Bits 0:0
+    U32 ACT_Enable                              :  1;  // Bits 1:1
+    U32 PRE_Enable                              :  1;  // Bits 2:2
+    U32 MAX_RPQ_Cas                             :  4;  // Bits 6:3
+    U32                                         :  25;  // Bits 31:7
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCSCHEDS_CR_WMM_READ_CONFIG_STRUCT;
+
+typedef union {
+  struct {
+    U64 Data_Error_Mask                         :  64;  // Bits 63:0
+  } Bits;
+  U64 Data;
+  U32 Data32[2];
+  U16 Data16[4];
+  U8  Data8[8];
+} MCSCHEDS_CR_REUT_CH_ERR_DATA_MASK_STRUCT;
+
+typedef union {
+  struct {
+    U64 Data_Error_Status                       :  64;  // Bits 63:0
+  } Bits;
+  U64 Data;
+  U32 Data32[2];
+  U16 Data16[4];
+  U8  Data8[8];
+} MCSCHEDS_CR_REUT_CH_ERR_DATA_STATUS_STRUCT;
+
+typedef union {
+  struct {
+    U32 ECC_Error_Status                        :  8;  // Bits 7:0
+    U32 Chunk_Error_Status                      :  8;  // Bits 15:8
+    U32 Rank_Error_Status                       :  4;  // Bits 19:16
+    U32                                         :  12;  // Bits 31:20
+    U32 Byte_Group_Error_Status                 :  9;  // Bits 40:32
+    U32                                         :  11;  // Bits 51:41
+    U32 WDB_Rd_Chunk_Num_Status                 :  3;  // Bits 54:52
+    U32                                         :  1;  // Bits 55:55
+    U32 Nth_Error                               :  6;  // Bits 61:56
+    U32                                         :  2;  // Bits 63:62
+  } Bits;
+  U64 Data;
+  U32 Data32[2];
+  U16 Data16[4];
+  U8  Data8[8];
+} MCSCHEDS_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_STRUCT;
+
+typedef union {
+  struct {
+    U32 Counter_Pointer                         :  7;  // Bits 6:0
+    U32 Counter_Control                         :  2;  // Bits 8:7
+    U32                                         :  23;  // Bits 31:9
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_0_STRUCT;
+
+typedef union {
+  struct {
+    U32 Counter_Pointer                         :  7;  // Bits 6:0
+    U32 Counter_Control                         :  2;  // Bits 8:7
+    U32                                         :  23;  // Bits 31:9
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_1_STRUCT;
+
+typedef union {
+  struct {
+    U32 Counter_Pointer                         :  7;  // Bits 6:0
+    U32 Counter_Control                         :  2;  // Bits 8:7
+    U32                                         :  23;  // Bits 31:9
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_2_STRUCT;
+
+typedef union {
+  struct {
+    U32 Counter_Pointer                         :  7;  // Bits 6:0
+    U32 Counter_Control                         :  2;  // Bits 8:7
+    U32                                         :  23;  // Bits 31:9
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_3_STRUCT;
+
+typedef union {
+  struct {
+    U32 Counter_Pointer                         :  7;  // Bits 6:0
+    U32 Counter_Control                         :  2;  // Bits 8:7
+    U32                                         :  23;  // Bits 31:9
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_4_STRUCT;
+
+typedef union {
+  struct {
+    U32 Counter_Pointer                         :  7;  // Bits 6:0
+    U32 Counter_Control                         :  2;  // Bits 8:7
+    U32                                         :  23;  // Bits 31:9
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_5_STRUCT;
+
+typedef union {
+  struct {
+    U32 Counter_Pointer                         :  7;  // Bits 6:0
+    U32 Counter_Control                         :  2;  // Bits 8:7
+    U32                                         :  23;  // Bits 31:9
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_6_STRUCT;
+
+typedef union {
+  struct {
+    U32 Counter_Pointer                         :  7;  // Bits 6:0
+    U32 Counter_Control                         :  2;  // Bits 8:7
+    U32                                         :  23;  // Bits 31:9
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_7_STRUCT;
+
+typedef union {
+  struct {
+    U32 Counter_Pointer                         :  7;  // Bits 6:0
+    U32 Counter_Control                         :  2;  // Bits 8:7
+    U32                                         :  23;  // Bits 31:9
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_8_STRUCT;
+
+typedef union {
+  struct {
+    U32 Counter_Status                          :  23;  // Bits 22:0
+    U32                                         :  9;  // Bits 31:23
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_0_STRUCT;
+
+typedef union {
+  struct {
+    U32 Counter_Status                          :  23;  // Bits 22:0
+    U32                                         :  9;  // Bits 31:23
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_1_STRUCT;
+
+typedef union {
+  struct {
+    U32 Counter_Status                          :  23;  // Bits 22:0
+    U32                                         :  9;  // Bits 31:23
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_2_STRUCT;
+
+typedef union {
+  struct {
+    U32 Counter_Status                          :  23;  // Bits 22:0
+    U32                                         :  9;  // Bits 31:23
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_3_STRUCT;
+
+typedef union {
+  struct {
+    U32 Counter_Status                          :  23;  // Bits 22:0
+    U32                                         :  9;  // Bits 31:23
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_4_STRUCT;
+
+typedef union {
+  struct {
+    U32 Counter_Status                          :  23;  // Bits 22:0
+    U32                                         :  9;  // Bits 31:23
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_5_STRUCT;
+
+typedef union {
+  struct {
+    U32 Counter_Status                          :  23;  // Bits 22:0
+    U32                                         :  9;  // Bits 31:23
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_6_STRUCT;
+
+typedef union {
+  struct {
+    U32 Counter_Status                          :  23;  // Bits 22:0
+    U32                                         :  9;  // Bits 31:23
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_7_STRUCT;
+
+typedef union {
+  struct {
+    U32 Counter_Status                          :  23;  // Bits 22:0
+    U32                                         :  9;  // Bits 31:23
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_8_STRUCT;
+
+typedef union {
+  struct {
+    U32 Counter_Overflow_Status                 :  9;  // Bits 8:0
+    U32                                         :  23;  // Bits 31:9
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCSCHEDS_CR_REUT_CH_ERR_COUNTER_OVERFLOW_STATUS_STRUCT;
+
+typedef union {
+  struct {
+    U32 Column_Address                          :  10;  // Bits 9:0
+    U32                                         :  14;  // Bits 23:10
+    U32 Row_Address                             :  16;  // Bits 39:24
+    U32                                         :  8;  // Bits 47:40
+    U32 Bank_Address                            :  3;  // Bits 50:48
+    U32                                         :  5;  // Bits 55:51
+    U32 Rank_Address                            :  2;  // Bits 57:56
+    U32                                         :  6;  // Bits 63:58
+  } Bits;
+  U64 Data;
+  U32 Data32[2];
+  U16 Data16[4];
+  U8  Data8[8];
+} MCSCHEDS_CR_REUT_CH_ERROR_ADDR_STRUCT;
+
+typedef union {
+  struct {
+    U32 WDB_Current_Error_Pointer               :  6;  // Bits 5:0
+    U32                                         :  26;  // Bits 31:6
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCSCHEDS_CR_REUT_CH_ERR_WDB_CAPTURE_STATUS_STRUCT;
+
+typedef union {
+  struct {
+    U32 Enable_WDB_Error_Capture                :  1;  // Bits 0:0
+    U32                                         :  7;  // Bits 7:1
+    U32 WDB_Starting_Error_Pointer              :  6;  // Bits 13:8
+    U32                                         :  2;  // Bits 15:14
+    U32 WDB_Ending_Error_Pointer                :  6;  // Bits 21:16
+    U32                                         :  10;  // Bits 31:22
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCSCHEDS_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_STRUCT;
+
+typedef union {
+  struct {
+    U32 CKE_Override                            :  4;  // Bits 3:0
+    U32                                         :  4;  // Bits 7:4
+    U32 CKE_En_Start_Test_Sync                  :  1;  // Bits 8:8
+    U32                                         :  7;  // Bits 15:9
+    U32 CKE_On                                  :  4;  // Bits 19:16
+    U32                                         :  12;  // Bits 31:20
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCSCHEDS_CR_REUT_CH_MISC_CKE_CTRL_STRUCT;
+
+typedef union {
+  struct {
+    U32 ODT_Override                            :  4;  // Bits 3:0
+    U32                                         :  12;  // Bits 15:4
+    U32 ODT_On                                  :  4;  // Bits 19:16
+    U32                                         :  11;  // Bits 30:20
+    U32 MPR_Train_DDR_On                        :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCSCHEDS_CR_REUT_CH_MISC_ODT_CTRL_STRUCT;
+
+typedef union {
+  struct {
+    U32 Enable_CADB_on_Deselect                 :  1;  // Bits 0:0
+    U32 Enable_CADB_Always_On                   :  1;  // Bits 1:1
+    U32 CMD_Deselect_Start                      :  4;  // Bits 5:2
+    U32 CMD_Deselect_Stop                       :  4;  // Bits 9:6
+    U32 Lane_Deselect_Enable                    :  4;  // Bits 13:10
+    U32 CAS_Select_Enable                       :  2;  // Bits 15:14
+    U32 ACT_Select_Enable                       :  2;  // Bits 17:16
+    U32 PRE_Select_Enable                       :  2;  // Bits 19:18
+    U32 Save_Current_Seed                       :  4;  // Bits 23:20
+    U32 Reload_Starting_Seed                    :  4;  // Bits 27:24
+    U32                                         :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_STRUCT;
+
+typedef union {
+  struct {
+    U32 MRS_Gap                                 :  3;  // Bits 2:0
+    U32                                         :  5;  // Bits 7:3
+    U32 CADB_MRS_Start_Pointer                  :  3;  // Bits 10:8
+    U32                                         :  5;  // Bits 15:11
+    U32 CADB_MRS_End_Pointer                    :  3;  // Bits 18:16
+    U32                                         :  5;  // Bits 23:19
+    U32 CADB_MRS_Current_Pointer                :  3;  // Bits 26:24
+    U32                                         :  5;  // Bits 31:27
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCSCHEDS_CR_REUT_CH_PAT_CADB_MRS_STRUCT;
+
+typedef union {
+  struct {
+    U32 Mux0_Control                            :  2;  // Bits 1:0
+    U32                                         :  2;  // Bits 3:2
+    U32 Mux1_Control                            :  2;  // Bits 5:4
+    U32                                         :  2;  // Bits 7:6
+    U32 Mux2_Control                            :  2;  // Bits 9:8
+    U32                                         :  6;  // Bits 15:10
+    U32 Select_Mux0_Control                     :  2;  // Bits 17:16
+    U32                                         :  2;  // Bits 19:18
+    U32 Select_Mux1_Control                     :  2;  // Bits 21:20
+    U32                                         :  2;  // Bits 23:22
+    U32 Select_Mux2_Control                     :  2;  // Bits 25:24
+    U32                                         :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_CTRL_STRUCT;
+
+typedef union {
+  struct {
+    U32 Pattern_Buffer                          :  16;  // Bits 15:0
+    U32                                         :  16;  // Bits 31:16
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_PB_0_STRUCT;
+
+typedef union {
+  struct {
+    U32 Pattern_Buffer                          :  16;  // Bits 15:0
+    U32                                         :  16;  // Bits 31:16
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_PB_1_STRUCT;
+
+typedef union {
+  struct {
+    U32 Pattern_Buffer                          :  16;  // Bits 15:0
+    U32                                         :  16;  // Bits 31:16
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_PB_2_STRUCT;
+
+typedef union {
+  struct {
+    U32 L_data_select                           :  1;  // Bits 0:0
+    U32 Enable_Sweep_Frequency                  :  1;  // Bits 1:1
+    U32                                         :  6;  // Bits 7:2
+    U32 L_counter                               :  8;  // Bits 15:8
+    U32 M_counter                               :  8;  // Bits 23:16
+    U32 N_counter                               :  8;  // Bits 31:24
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCSCHEDS_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_STRUCT;
+
+typedef union {
+  struct {
+    U32 CADB_Write_Pointer                      :  3;  // Bits 2:0
+    U32                                         :  29;  // Bits 31:3
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCSCHEDS_CR_REUT_CH_PAT_CADB_WRITE_POINTER_STRUCT;
+
+typedef union {
+  struct {
+    U32 CADB_Data_Address                       :  16;  // Bits 15:0
+    U32                                         :  8;  // Bits 23:16
+    U32 CADB_Data_Bank                          :  3;  // Bits 26:24
+    U32                                         :  5;  // Bits 31:27
+    U32 CADB_Data_CS                            :  4;  // Bits 35:32
+    U32                                         :  4;  // Bits 39:36
+    U32 CADB_Data_Control                       :  3;  // Bits 42:40
+    U32                                         :  5;  // Bits 47:43
+    U32 CADB_Data_ODT                           :  4;  // Bits 51:48
+    U32                                         :  4;  // Bits 55:52
+    U32 CADB_Data_CKE                           :  4;  // Bits 59:56
+    U32                                         :  4;  // Bits 63:60
+  } Bits;
+  U64 Data;
+  U32 Data32[2];
+  U16 Data16[4];
+  U8  Data8[8];
+} MCSCHEDS_CR_REUT_CH_PAT_CADB_PROG_STRUCT;
+
+typedef union {
+  struct {
+    U32 Pattern_Buffer                          :  16;  // Bits 15:0
+    U32                                         :  16;  // Bits 31:16
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCSCHEDS_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_0_STRUCT;
+
+typedef union {
+  struct {
+    U32 Pattern_Buffer                          :  16;  // Bits 15:0
+    U32                                         :  16;  // Bits 31:16
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCSCHEDS_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_1_STRUCT;
+
+typedef union {
+  struct {
+    U32 Pattern_Buffer                          :  16;  // Bits 15:0
+    U32                                         :  16;  // Bits 31:16
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCSCHEDS_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_2_STRUCT;
+
+typedef union {
+  struct {
+    U32 WDB_Increment_Rate                      :  5;  // Bits 4:0
+    U32 WDB_Increment_Scale                     :  1;  // Bits 5:5
+    U32                                         :  2;  // Bits 7:6
+    U32 WDB_Start_Pointer                       :  6;  // Bits 13:8
+    U32                                         :  2;  // Bits 15:14
+    U32 WDB_End_Pointer                         :  6;  // Bits 21:16
+    U32                                         :  10;  // Bits 31:22
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCMNTS_CR_REUT_CH_PAT_WDB_CL_CTRL_STRUCT;
+
+typedef union {
+  struct {
+    U32 Refresh_Rank_Mask                       :  4;  // Bits 3:0
+    U32                                         :  4;  // Bits 7:4
+    U32 RefZQ_En_Start_Test_Sync                :  1;  // Bits 8:8
+    U32                                         :  22;  // Bits 30:9
+    U32 Panic_Refresh_Only                      :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCMNTS_CR_REUT_CH_MISC_REFRESH_CTRL_STRUCT;
+
+typedef union {
+  struct {
+    U32 ZQ_Rank_Mask                            :  4;  // Bits 3:0
+    U32                                         :  27;  // Bits 30:4
+    U32 Always_Do_ZQ                            :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCMNTS_CR_REUT_CH_MISC_ZQ_CTRL_STRUCT;
+
+#ifdef ULT_FLAG
+typedef union {
+  struct {
+    U32 Rank_0_x32                              :  1;  // Bits 0:0
+    U32 Rank_1_x32                              :  1;  // Bits 1:1
+    U32 Rank_2_x32                              :  1;  // Bits 2:2
+    U32 Rank_3_x32                              :  1;  // Bits 3:3
+    U32 LPDDR2                                  :  1;  // Bits 4:4
+    U32                                         :  3;  // Bits 7:5
+    U32 MR4_PERIOD                              :  16;  // Bits 23:8
+    U32                                         :  8;  // Bits 31:24
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCMNTS_CR_LPDDR_MR_PARAMS_STRUCT;
+
+typedef union {
+  struct {
+    U32 Address                                 :  8;  // Bits 7:0
+    U32 Data                                    :  8;  // Bits 15:8
+    U32 Rank                                    :  2;  // Bits 17:16
+    U32 Write                                   :  1;  // Bits 18:18
+    U32 Init_MRW                                :  1;  // Bits 19:19
+    U32                                         :  11;  // Bits 30:20
+    U32 Busy                                    :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCMNTS_CR_LPDDR_MR_COMMAND_STRUCT;
+
+typedef union {
+  struct {
+    U32 Device_0                                :  8;  // Bits 7:0
+    U32 Device_1                                :  8;  // Bits 15:8
+    U32 Device_2                                :  8;  // Bits 23:16
+    U32 Device_3                                :  8;  // Bits 31:24
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCMNTS_CR_LPDDR_MR_RESULT_STRUCT;
+
+typedef union {
+  struct {
+    U32 Rank_0                                  :  3;  // Bits 2:0
+    U32                                         :  5;  // Bits 7:3
+    U32 Rank_1                                  :  3;  // Bits 10:8
+    U32                                         :  5;  // Bits 15:11
+    U32 Rank_2                                  :  3;  // Bits 18:16
+    U32                                         :  5;  // Bits 23:19
+    U32 Rank_3                                  :  3;  // Bits 26:24
+    U32                                         :  5;  // Bits 31:27
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCMNTS_CR_LPDDR_MR4_RANK_TEMPERATURE_STRUCT;
+
+typedef union {
+  struct {
+    U32 Bit_0                                   :  3;  // Bits 2:0
+    U32                                         :  1;  // Bits 3:3
+    U32 Bit_1                                   :  3;  // Bits 6:4
+    U32                                         :  1;  // Bits 7:7
+    U32 Bit_2                                   :  3;  // Bits 10:8
+    U32                                         :  1;  // Bits 11:11
+    U32 Bit_16                                  :  3;  // Bits 14:12
+    U32                                         :  1;  // Bits 15:15
+    U32 Bit_17                                  :  3;  // Bits 18:16
+    U32                                         :  1;  // Bits 19:19
+    U32 Bit_18                                  :  3;  // Bits 22:20
+    U32                                         :  1;  // Bits 23:23
+    U32 Byte_0                                  :  3;  // Bits 26:24
+    U32                                         :  1;  // Bits 27:27
+    U32 Byte_2                                  :  3;  // Bits 30:28
+    U32                                         :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCMNTS_CR_DESWIZZLE_LOW_STRUCT;
+
+typedef union {
+  struct {
+    U32 Bit_32                                  :  3;  // Bits 2:0
+    U32                                         :  1;  // Bits 3:3
+    U32 Bit_33                                  :  3;  // Bits 6:4
+    U32                                         :  1;  // Bits 7:7
+    U32 Bit_34                                  :  3;  // Bits 10:8
+    U32                                         :  1;  // Bits 11:11
+    U32 Bit_48                                  :  3;  // Bits 14:12
+    U32                                         :  1;  // Bits 15:15
+    U32 Bit_49                                  :  3;  // Bits 18:16
+    U32                                         :  1;  // Bits 19:19
+    U32 Bit_50                                  :  3;  // Bits 22:20
+    U32                                         :  1;  // Bits 23:23
+    U32 Byte_4                                  :  3;  // Bits 26:24
+    U32                                         :  1;  // Bits 27:27
+    U32 Byte_6                                  :  3;  // Bits 30:28
+    U32                                         :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCMNTS_CR_DESWIZZLE_HIGH_STRUCT;
+#endif // ULT_FLAG
+
+typedef union {
+  struct {
+    U32 Ref_Interval                            :  11;  // Bits 10:0
+    U32 Ref_Stagger_En                          :  1;  // Bits 11:11
+    U32 Ref_Stagger_Mode                        :  1;  // Bits 12:12
+    U32 Disable_Stolen_Refresh                  :  1;  // Bits 13:13
+    U32 En_Ref_Type_Display                     :  1;  // Bits 14:14
+    U32                                         :  17;  // Bits 31:15
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCMNTS_CR_MC_REFRESH_STAGGER_STRUCT;
+
+typedef union {
+  struct {
+    U32 ZQCS_period                             :  8;  // Bits 7:0
+    U32 tZQCS                                   :  8;  // Bits 15:8
+    U32                                         :  16;  // Bits 31:16
+  } Bits;
+#ifdef ULT_FLAG
+  struct {
+    U32 ZQCS_period                             :  10;  // Bits 9:0
+    U32 tZQCS                                   :  10;  // Bits 19:10
+    U32                                         :  12;  // Bits 31:20
+  } UltBits;
+#endif // ULT_FLAG
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCMNTS_CR_TC_ZQCAL_STRUCT;
+
+typedef union {
+  struct {
+    U32 OREF_RI                                 :  8;  // Bits 7:0
+    U32 Refresh_HP_WM                           :  4;  // Bits 11:8
+    U32 Refresh_panic_wm                        :  4;  // Bits 15:12
+    U32                                         :  16;  // Bits 31:16
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCMNTS_CR_TC_RFP_STRUCT;
+
+typedef union {
+  struct {
+    U32 tREFI                                   :  16;  // Bits 15:0
+    U32 tRFC                                    :  9;  // Bits 24:16
+    U32 tREFIx9                                 :  7;  // Bits 31:25
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCMNTS_CR_TC_RFTP_STRUCT;
+
+typedef union {
+  struct {
+    U32 MR2_sh_low                              :  6;  // Bits 5:0
+    U32 SRT_avail                               :  2;  // Bits 7:6
+    U32 MR2_sh_high                             :  3;  // Bits 10:8
+    U32                                         :  3;  // Bits 13:11
+    U32 Addr_bit_swizzle                        :  2;  // Bits 15:14
+    U32                                         :  16;  // Bits 31:16
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCMNTS_CR_TC_MR2_SHADDOW_STRUCT;
+
+typedef union {
+  struct {
+    U32 Rank_occupancy                          :  4;  // Bits 3:0
+    U32                                         :  28;  // Bits 31:4
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCMNTS_CR_MC_INIT_STATE_STRUCT;
+
+typedef union {
+  struct {
+    U32 tXSDLL                                  :  12;  // Bits 11:0
+    U32 tXS_offset                              :  4;  // Bits 15:12
+    U32 tZQOPER                                 :  10;  // Bits 25:16
+    U32                                         :  2;  // Bits 27:26
+    U32 tMOD                                    :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCMNTS_CR_TC_SRFTP_STRUCT;
+
+typedef union {
+  struct {
+    U32 VISAByteSel                             :  3;  // Bits 2:0
+    U32                                         :  29;  // Bits 31:3
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCMNTS_CR_WDB_VISA_SEL_STRUCT;
+
+typedef union {
+  struct {
+    U32 FASTADDR                                :  12;  // Bits 11:0
+    U32                                         :  4;  // Bits 15:12
+    U32 ADDREN                                  :  1;  // Bits 16:16
+    U32 SEQEN                                   :  1;  // Bits 17:17
+    U32 POL0                                    :  1;  // Bits 18:18
+    U32 POL1                                    :  1;  // Bits 19:19
+    U32 CMDA                                    :  4;  // Bits 23:20
+    U32 CMDB                                    :  4;  // Bits 27:24
+    U32 CMDC                                    :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCMNTS_CR_DCLK_LDAT_PDAT_STRUCT;
+
+typedef union {
+  struct {
+    U32 BANKSEL                                 :  4;  // Bits 3:0
+    U32                                         :  1;  // Bits 4:4
+    U32 ARRAYSEL                                :  5;  // Bits 9:5
+    U32 CMP                                     :  1;  // Bits 10:10
+    U32 REP                                     :  1;  // Bits 11:11
+    U32 DWORD                                   :  4;  // Bits 15:12
+    U32 MODE                                    :  2;  // Bits 17:16
+    U32 MPMAP                                   :  6;  // Bits 23:18
+    U32 MPBOFFSET                               :  4;  // Bits 27:24
+    U32 STAGE_EN                                :  1;  // Bits 28:28
+    U32 SHADOW                                  :  2;  // Bits 30:29
+    U32                                         :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCMNTS_CR_DCLK_LDAT_SDAT_STRUCT;
+
+typedef union {
+  struct {
+    U32 DATOUT                                  :  32;  // Bits 31:0
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCMNTS_CR_DCLK_LDAT_DATAOUT_STRUCT;
+
+typedef union {
+  struct {
+    U32 DATIN                                   :  32;  // Bits 31:0
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCMNTS_CR_DCLK_LDAT_DATAIN_0_STRUCT;
+
+typedef union {
+  struct {
+    U32 FASTADDR                                :  12;  // Bits 11:0
+    U32                                         :  4;  // Bits 15:12
+    U32 ADDREN                                  :  1;  // Bits 16:16
+    U32 SEQEN                                   :  1;  // Bits 17:17
+    U32 POL0                                    :  1;  // Bits 18:18
+    U32 POL1                                    :  1;  // Bits 19:19
+    U32 CMDA                                    :  4;  // Bits 23:20
+    U32 CMDB                                    :  4;  // Bits 27:24
+    U32 CMDC                                    :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCMNTS_CR_QCLK_LDAT_PDAT_STRUCT;
+
+typedef union {
+  struct {
+    U32 BANKSEL                                 :  4;  // Bits 3:0
+    U32                                         :  1;  // Bits 4:4
+    U32 ARRAYSEL                                :  5;  // Bits 9:5
+    U32 CMP                                     :  1;  // Bits 10:10
+    U32 REP                                     :  1;  // Bits 11:11
+    U32 DWORD                                   :  4;  // Bits 15:12
+    U32 MODE                                    :  2;  // Bits 17:16
+    U32 MPMAP                                   :  6;  // Bits 23:18
+    U32 MPBOFFSET                               :  4;  // Bits 27:24
+    U32 STAGE_EN                                :  1;  // Bits 28:28
+    U32 SHADOW                                  :  2;  // Bits 30:29
+    U32                                         :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCMNTS_CR_QCLK_LDAT_SDAT_STRUCT;
+
+typedef union {
+  struct {
+    U32 DATOUT                                  :  32;  // Bits 31:0
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCMNTS_CR_QCLK_LDAT_DATAOUT_STRUCT;
+
+typedef union {
+  struct {
+    U32 DATIN                                   :  32;  // Bits 31:0
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCMNTS_CR_QCLK_LDAT_DATAIN_0_STRUCT;
+
+typedef union {
+  struct {
+    U32 DATIN                                   :  32;  // Bits 31:0
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCMNTS_CR_QCLK_LDAT_DATAIN_1_STRUCT;
+
+typedef union {
+  struct {
+    U32 RPQ_disable                             :  28;  // Bits 27:0
+    U32                                         :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCMNTS_CR_QUEUE_ENTRY_DISABLE_RPQ_STRUCT;
+
+typedef union {
+  struct {
+    U32 WPQ_disable                             :  32;  // Bits 31:0
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCMNTS_CR_QUEUE_ENTRY_DISABLE_WPQ_STRUCT;
+
+typedef union {
+  struct {
+    U32 DIMM0_IDLE_ENERGY                       :  6;  // Bits 5:0
+    U32                                         :  2;  // Bits 7:6
+    U32 DIMM1_IDLE_ENERGY                       :  6;  // Bits 13:8
+    U32                                         :  18;  // Bits 31:14
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCMNTS_CR_PM_DIMM_IDLE_ENERGY_STRUCT;
+
+typedef union {
+  struct {
+    U32 DIMM0_PD_ENERGY                         :  6;  // Bits 5:0
+    U32                                         :  2;  // Bits 7:6
+    U32 DIMM1_PD_ENERGY                         :  6;  // Bits 13:8
+    U32                                         :  18;  // Bits 31:14
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCMNTS_CR_PM_DIMM_PD_ENERGY_STRUCT;
+
+typedef union {
+  struct {
+    U32 DIMM0_ACT_ENERGY                        :  8;  // Bits 7:0
+    U32 DIMM1_ACT_ENERGY                        :  8;  // Bits 15:8
+    U32                                         :  16;  // Bits 31:16
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCMNTS_CR_PM_DIMM_ACT_ENERGY_STRUCT;
+
+typedef union {
+  struct {
+    U32 DIMM0_RD_ENERGY                         :  8;  // Bits 7:0
+    U32 DIMM1_RD_ENERGY                         :  8;  // Bits 15:8
+    U32                                         :  16;  // Bits 31:16
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCMNTS_CR_PM_DIMM_RD_ENERGY_STRUCT;
+
+typedef union {
+  struct {
+    U32 DIMM0_WR_ENERGY                         :  8;  // Bits 7:0
+    U32 DIMM1_WR_ENERGY                         :  8;  // Bits 15:8
+    U32                                         :  16;  // Bits 31:16
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCMNTS_CR_PM_DIMM_WR_ENERGY_STRUCT;
+
+typedef union {
+  struct {
+    U32 CKE_MIN                                 :  8;  // Bits 7:0
+    U32 CKE_MIN_DEFEATURE                       :  1;  // Bits 8:8
+    U32                                         :  23;  // Bits 31:9
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCMNTS_CR_PM_THRT_CKE_MIN_STRUCT;
+
+typedef union {
+  struct {
+    U32 ODT                                     :  4;  // Bits 3:0
+    U32 Web                                     :  1;  // Bits 4:4
+    U32 CASb                                    :  1;  // Bits 5:5
+    U32 RASb                                    :  1;  // Bits 6:6
+    U32 CSb                                     :  4;  // Bits 10:7
+    U32 CKE                                     :  4;  // Bits 14:11
+    U32 MA                                      :  16;  // Bits 30:15
+    U32                                         :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCMNTS_CR_ODLAT_CMD_MATCH0_STRUCT;
+
+typedef union {
+  struct {
+    U32 ODT                                     :  4;  // Bits 3:0
+    U32 Web                                     :  1;  // Bits 4:4
+    U32 CASb                                    :  1;  // Bits 5:5
+    U32 RASb                                    :  1;  // Bits 6:6
+    U32 CSb                                     :  4;  // Bits 10:7
+    U32 CKE                                     :  4;  // Bits 14:11
+    U32 MA                                      :  16;  // Bits 30:15
+    U32                                         :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCMNTS_CR_ODLAT_CMD_MATCH1_STRUCT;
+
+typedef union {
+  struct {
+    U32 ODT                                     :  4;  // Bits 3:0
+    U32 Web                                     :  1;  // Bits 4:4
+    U32 CASb                                    :  1;  // Bits 5:5
+    U32 RASb                                    :  1;  // Bits 6:6
+    U32 CSb                                     :  4;  // Bits 10:7
+    U32 CKE                                     :  4;  // Bits 14:11
+    U32 MA                                      :  16;  // Bits 30:15
+    U32                                         :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCMNTS_CR_ODLAT_CMD_MATCH2_STRUCT;
+
+typedef union {
+  struct {
+    U32 ODT                                     :  4;  // Bits 3:0
+    U32 Web                                     :  1;  // Bits 4:4
+    U32 CASb                                    :  1;  // Bits 5:5
+    U32 RASb                                    :  1;  // Bits 6:6
+    U32 CSb                                     :  4;  // Bits 10:7
+    U32 CKE                                     :  4;  // Bits 14:11
+    U32 MA                                      :  16;  // Bits 30:15
+    U32                                         :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCMNTS_CR_ODLAT_CMD_MATCH3_STRUCT;
+
+typedef union {
+  struct {
+    U32 ODT                                     :  4;  // Bits 3:0
+    U32 Web                                     :  1;  // Bits 4:4
+    U32 CASb                                    :  1;  // Bits 5:5
+    U32 RASb                                    :  1;  // Bits 6:6
+    U32 CSb                                     :  4;  // Bits 10:7
+    U32 CKE                                     :  4;  // Bits 14:11
+    U32 MA                                      :  16;  // Bits 30:15
+    U32                                         :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCMNTS_CR_ODLAT_CMD_MASK0_STRUCT;
+
+typedef union {
+  struct {
+    U32 ODT                                     :  4;  // Bits 3:0
+    U32 Web                                     :  1;  // Bits 4:4
+    U32 CASb                                    :  1;  // Bits 5:5
+    U32 RASb                                    :  1;  // Bits 6:6
+    U32 CSb                                     :  4;  // Bits 10:7
+    U32 CKE                                     :  4;  // Bits 14:11
+    U32 MA                                      :  16;  // Bits 30:15
+    U32                                         :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCMNTS_CR_ODLAT_CMD_MASK1_STRUCT;
+
+typedef union {
+  struct {
+    U32 ODT                                     :  4;  // Bits 3:0
+    U32 Web                                     :  1;  // Bits 4:4
+    U32 CASb                                    :  1;  // Bits 5:5
+    U32 RASb                                    :  1;  // Bits 6:6
+    U32 CSb                                     :  4;  // Bits 10:7
+    U32 CKE                                     :  4;  // Bits 14:11
+    U32 MA                                      :  16;  // Bits 30:15
+    U32                                         :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCMNTS_CR_ODLAT_CMD_MASK2_STRUCT;
+
+typedef union {
+  struct {
+    U32 ODT                                     :  4;  // Bits 3:0
+    U32 Web                                     :  1;  // Bits 4:4
+    U32 CASb                                    :  1;  // Bits 5:5
+    U32 RASb                                    :  1;  // Bits 6:6
+    U32 CSb                                     :  4;  // Bits 10:7
+    U32 CKE                                     :  4;  // Bits 14:11
+    U32 MA                                      :  16;  // Bits 30:15
+    U32                                         :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCMNTS_CR_ODLAT_CMD_MASK3_STRUCT;
+
+typedef union {
+  struct {
+    U32 BankMatch0                              :  3;  // Bits 2:0
+    U32 BankMatch1                              :  3;  // Bits 5:3
+    U32 BankMatch2                              :  3;  // Bits 8:6
+    U32 BankMatch3                              :  3;  // Bits 11:9
+    U32 BankMask0                               :  3;  // Bits 14:12
+    U32 BankMask1                               :  3;  // Bits 17:15
+    U32 BankMask2                               :  3;  // Bits 20:18
+    U32 BankMask3                               :  3;  // Bits 23:21
+    U32                                         :  8;  // Bits 31:24
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCMNTS_CR_ODLAT_CMD_BANK_STRUCT;
+
+typedef union {
+  struct {
+    U32 InputMatch                              :  4;  // Bits 3:0
+    U32 InputInvert                             :  4;  // Bits 7:4
+    U32 CountMatches                            :  1;  // Bits 8:8
+    U32 CounterThreshold                        :  15;  // Bits 23:9
+    U32 CounterAction                           :  2;  // Bits 25:24
+    U32 CounterNextState                        :  2;  // Bits 27:26
+    U32 MatchAction                             :  2;  // Bits 29:28
+    U32 MatchNextState                          :  2;  // Bits 31:30
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCMNTS_CR_ODLAT_SEQ_LEVEL0_STRUCT;
+
+typedef union {
+  struct {
+    U32 InputMatch                              :  4;  // Bits 3:0
+    U32 InputInvert                             :  4;  // Bits 7:4
+    U32 CountMatches                            :  1;  // Bits 8:8
+    U32 CounterThreshold                        :  15;  // Bits 23:9
+    U32 CounterAction                           :  2;  // Bits 25:24
+    U32 CounterNextState                        :  2;  // Bits 27:26
+    U32 MatchAction                             :  2;  // Bits 29:28
+    U32 MatchNextState                          :  2;  // Bits 31:30
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCMNTS_CR_ODLAT_SEQ_LEVEL1_STRUCT;
+
+typedef union {
+  struct {
+    U32 InputMatch                              :  4;  // Bits 3:0
+    U32 InputInvert                             :  4;  // Bits 7:4
+    U32 CountMatches                            :  1;  // Bits 8:8
+    U32 CounterThreshold                        :  15;  // Bits 23:9
+    U32 CounterAction                           :  2;  // Bits 25:24
+    U32 CounterNextState                        :  2;  // Bits 27:26
+    U32 MatchAction                             :  2;  // Bits 29:28
+    U32 MatchNextState                          :  2;  // Bits 31:30
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCMNTS_CR_ODLAT_SEQ_LEVEL2_STRUCT;
+
+typedef union {
+  struct {
+    U32 InputMatch                              :  4;  // Bits 3:0
+    U32 InputInvert                             :  4;  // Bits 7:4
+    U32 CountMatches                            :  1;  // Bits 8:8
+    U32 CounterThreshold                        :  15;  // Bits 23:9
+    U32 CounterAction                           :  2;  // Bits 25:24
+    U32 CounterNextState                        :  2;  // Bits 27:26
+    U32 MatchAction                             :  2;  // Bits 29:28
+    U32 MatchNextState                          :  2;  // Bits 31:30
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCMNTS_CR_ODLAT_SEQ_LEVEL3_STRUCT;
+
+typedef union {
+  struct {
+    U32 TriggerBlockEnable                      :  1;  // Bits 0:0
+    U32 GlobalCounterThreshold                  :  16;  // Bits 16:1
+    U32                                         :  15;  // Bits 31:17
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCMNTS_CR_ODLAT_SEQ_GLOBAL_STRUCT;
+
+typedef union {
+  struct {
+    U32 WMM_Enter                               :  8;  // Bits 7:0
+    U32 WMM_Exit                                :  8;  // Bits 15:8
+    U32 WPQ_IS                                  :  8;  // Bits 23:16
+    U32 Starve_count                            :  8;  // Bits 31:24
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCMNTS_CR_SC_WDBWM_STRUCT;
+
+typedef union {
+  struct {
+    U32 Data                                    :  18;  // Bits 17:0
+    U32                                         :  13;  // Bits 30:18
+    U32 VORANGE                                 :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCMNTS_CR_VISA_CTL_MCMNTS_STRUCT;
+
+typedef union {
+  struct {
+    U32 CH_A                                    :  2;  // Bits 1:0
+    U32 CH_B                                    :  2;  // Bits 3:2
+    U32 CH_C                                    :  2;  // Bits 5:4
+    U32 STKD_MODE                               :  1;  // Bits 6:6
+    U32 STKD_MODE_CH_BITS                       :  3;  // Bits 9:7
+    U32 LPDDR                                   :  1;  // Bits 10:10
+    U32                                         :  21;  // Bits 31:11
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCDECS_CR_MAD_CHNL_MCMAIN_STRUCT;
+
+typedef union {
+  struct {
+    U32 DIMM_A_Size                             :  8;  // Bits 7:0
+    U32 DIMM_B_Size                             :  8;  // Bits 15:8
+    U32 DAS                                     :  1;  // Bits 16:16
+    U32 DANOR                                   :  1;  // Bits 17:17
+    U32 DBNOR                                   :  1;  // Bits 18:18
+    U32 DAW                                     :  1;  // Bits 19:19
+    U32 DBW                                     :  1;  // Bits 20:20
+    U32 RI                                      :  1;  // Bits 21:21
+    U32 Enh_Interleave                          :  1;  // Bits 22:22
+    U32                                         :  1;  // Bits 23:23
+    U32 ECC                                     :  2;  // Bits 25:24
+    U32 HORI                                    :  1;  // Bits 26:26
+    U32 HORIAddr                                :  3;  // Bits 29:27
+    U32                                         :  2;  // Bits 31:30
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCDECS_CR_MAD_DIMM_CH0_MCMAIN_STRUCT;
+
+typedef union {
+  struct {
+    U32 DIMM_A_Size                             :  8;  // Bits 7:0
+    U32 DIMM_B_Size                             :  8;  // Bits 15:8
+    U32 DAS                                     :  1;  // Bits 16:16
+    U32 DANOR                                   :  1;  // Bits 17:17
+    U32 DBNOR                                   :  1;  // Bits 18:18
+    U32 DAW                                     :  1;  // Bits 19:19
+    U32 DBW                                     :  1;  // Bits 20:20
+    U32 RI                                      :  1;  // Bits 21:21
+    U32 Enh_Interleave                          :  1;  // Bits 22:22
+    U32                                         :  1;  // Bits 23:23
+    U32 ECC                                     :  2;  // Bits 25:24
+    U32 HORI                                    :  1;  // Bits 26:26
+    U32 HORIAddr                                :  3;  // Bits 29:27
+    U32                                         :  2;  // Bits 31:30
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCDECS_CR_MAD_DIMM_CH1_MCMAIN_STRUCT;
+
+typedef union {
+  struct {
+    U32 DIMM_A_Size                             :  8;  // Bits 7:0
+    U32 DIMM_B_Size                             :  8;  // Bits 15:8
+    U32 DAS                                     :  1;  // Bits 16:16
+    U32 DANOR                                   :  1;  // Bits 17:17
+    U32 DBNOR                                   :  1;  // Bits 18:18
+    U32 DAW                                     :  1;  // Bits 19:19
+    U32 DBW                                     :  1;  // Bits 20:20
+    U32 RI                                      :  1;  // Bits 21:21
+    U32 Enh_Interleave                          :  1;  // Bits 22:22
+    U32                                         :  1;  // Bits 23:23
+    U32 ECC                                     :  2;  // Bits 25:24
+    U32 HORI                                    :  1;  // Bits 26:26
+    U32 HORIAddr                                :  3;  // Bits 29:27
+    U32                                         :  2;  // Bits 31:30
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCDECS_CR_MAD_DIMM_CH2_MCMAIN_STRUCT;
+
+typedef union {
+  struct {
+    U32 OneC                                    :  8;  // Bits 7:0
+    U32 ThreeC                                  :  8;  // Bits 15:8
+    U32 TwoBandC                                :  8;  // Bits 23:16
+    U32 BandC                                   :  8;  // Bits 31:24
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCDECS_CR_MAD_ZR_MCMAIN_STRUCT;
+
+typedef union {
+  struct {
+    U32 spare                                   :  23;  // Bits 22:0
+    U32 ovrd_pcu_sr_exit                        :  1;  // Bits 23:23
+    U32 isoch_stall_pattern                     :  8;  // Bits 31:24
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCDECS_CR_MCDECS_MISC_MCMAIN_STRUCT;
+
+typedef union {
+  struct {
+    U32 increase_rcomp                          :  1;  // Bits 0:0
+    U32 noa_on_ecc                              :  1;  // Bits 1:1
+    U32 noa_demux                               :  1;  // Bits 2:2
+    U32 noa_countctrl                           :  1;  // Bits 3:3
+    U32                                         :  4;  // Bits 7:4
+    U32 psmi_freeze_pwm_counters                :  1;  // Bits 8:8
+    U32                                         :  6;  // Bits 14:9
+    U32 dis_lp_prefetch                         :  1;  // Bits 15:15
+    U32                                         :  13;  // Bits 28:16
+    U32 dis_reg_clk_gate                        :  1;  // Bits 29:29
+    U32 dis_msg_clk_gate                        :  1;  // Bits 30:30
+    U32 dis_clk_gate                            :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCDECS_CR_MCDECS_CBIT_MCMAIN_STRUCT;
+
+typedef union {
+  struct {
+    U32 count                                   :  4;  // Bits 3:0
+    U32                                         :  28;  // Bits 31:4
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCDECS_CR_SC_IS_CREDIT_MCMAIN_STRUCT;
+
+typedef union {
+  struct {
+    U32 Mask                                    :  14;  // Bits 13:0
+    U32                                         :  7;  // Bits 20:14
+    U32 LSB_mask_bit                            :  2;  // Bits 22:21
+    U32 Enable                                  :  1;  // Bits 23:23
+    U32                                         :  8;  // Bits 31:24
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCDECS_CR_CHANNEL_HASH_MCMAIN_STRUCT;
+
+typedef union {
+  struct {
+    U32 pu_mrc_done                             :  1;  // Bits 0:0
+    U32 ddr_reset                               :  1;  // Bits 1:1
+    U32                                         :  1;  // Bits 2:2
+    U32 refresh_enable                          :  1;  // Bits 3:3
+    U32                                         :  1;  // Bits 4:4
+    U32 mc_init_done_ack                        :  1;  // Bits 5:5
+    U32                                         :  1;  // Bits 6:6
+    U32 mrc_done                                :  1;  // Bits 7:7
+    U32 safe_sr                                 :  1;  // Bits 8:8
+    U32                                         :  1;  // Bits 9:9
+    U32 HVM_Gate_DDR_Reset                      :  1;  // Bits 10:10
+    U32                                         :  11;  // Bits 21:11
+    U32 dclk_enable                             :  1;  // Bits 22:22
+    U32 reset_io                                :  1;  // Bits 23:23
+    U32                                         :  8;  // Bits 31:24
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCDECS_CR_MC_INIT_STATE_G_MCMAIN_STRUCT;
+
+typedef union {
+  struct {
+    U32 REVISION                                :  32;  // Bits 31:0
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCDECS_CR_MRC_REVISION_MCMAIN_STRUCT;
+
+typedef union {
+  struct {
+    U32 count                                   :  32;  // Bits 31:0
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCDECS_CR_PWM_GT_REQCOUNT_MCMAIN_STRUCT;
+
+typedef union {
+  struct {
+    U32 count                                   :  32;  // Bits 31:0
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCDECS_CR_PWM_IA_REQCOUNT_MCMAIN_STRUCT;
+
+typedef union {
+  struct {
+    U32 count                                   :  32;  // Bits 31:0
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCDECS_CR_PWM_IO_REQCOUNT_MCMAIN_STRUCT;
+
+typedef union {
+  struct {
+    U32 count                                   :  32;  // Bits 31:0
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCDECS_CR_PWM_RDDATA_COUNT_MCMAIN_STRUCT;
+
+typedef union {
+  struct {
+    U32 count                                   :  32;  // Bits 31:0
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCDECS_CR_PWM_WRDATA_COUNT_MCMAIN_STRUCT;
+
+typedef union {
+  struct {
+    U32 count                                   :  32;  // Bits 31:0
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCDECS_CR_PWM_COMMAND_COUNT_MCMAIN_STRUCT;
+
+typedef union {
+  struct {
+    U32 Idle_timer                              :  16;  // Bits 15:0
+    U32 SR_Enable                               :  1;  // Bits 16:16
+    U32                                         :  15;  // Bits 31:17
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCDECS_CR_PM_SREF_CONFIG_MCMAIN_STRUCT;
+
+typedef union {
+  struct {
+    U32 Ch_dir                                  :  4;  // Bits 3:0
+    U32                                         :  4;  // Bits 7:4
+    U32 MCI_clk_div                             :  10;  // Bits 17:8
+    U32                                         :  14;  // Bits 31:18
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCDECS_CR_MCI_CONFIG_MCMAIN_STRUCT;
+
+typedef union {
+  struct {
+    U32 stall_until_drain                       :  1;  // Bits 0:0
+    U32 stall_input                             :  1;  // Bits 1:1
+    U32                                         :  2;  // Bits 3:2
+    U32 mc_drained                              :  1;  // Bits 4:4
+    U32                                         :  3;  // Bits 7:5
+    U32 sr_state                                :  2;  // Bits 9:8
+    U32                                         :  22;  // Bits 31:10
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCDECS_CR_STALL_DRAIN_MCMAIN_STRUCT;
+
+typedef union {
+  struct {
+    U32 RPQ_count                               :  5;  // Bits 4:0
+    U32                                         :  3;  // Bits 7:5
+    U32 WPQ_count                               :  7;  // Bits 14:8
+    U32                                         :  17;  // Bits 31:15
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCDECS_CR_QUEUE_CREDIT_C_MCMAIN_STRUCT;
+
+typedef union {
+  struct {
+    U32 count                                   :  16;  // Bits 15:0
+    U32 First_Rcomp_done                        :  1;  // Bits 16:16
+    U32                                         :  15;  // Bits 31:17
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCDECS_CR_RCOMP_TIMER_MCMAIN_STRUCT;
+
+typedef union {
+  struct {
+    U32 Address                                 :  32;  // Bits 31:0
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCDECS_CR_ECC_INJ_ADDR_COMPARE_MCMAIN_STRUCT;
+
+typedef union {
+  struct {
+    U32 Mask                                    :  32;  // Bits 31:0
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCDECS_CR_ECC_INJ_ADDR_MASK_MCMAIN_STRUCT;
+
+typedef union {
+  struct {
+    U32 Data                                    :  18;  // Bits 17:0
+    U32                                         :  13;  // Bits 30:18
+    U32 VORANGE                                 :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCDECS_CR_VISA_CTL_MCDECS_MCMAIN_STRUCT;
+
+typedef union {
+  struct {
+    U32 Data                                    :  32;  // Bits 31:0
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCDECS_CR_VISA_XBAR_MCDECS_MCMAIN_STRUCT;
+
+typedef union {
+  struct {
+    U32 lock_addr_map                           :  1;  // Bits 0:0
+    U32 lock_mc_config                          :  1;  // Bits 1:1
+    U32 lock_iosav_init                         :  1;  // Bits 2:2
+    U32 lock_pwr_mngment                        :  1;  // Bits 3:3
+    U32                                         :  3;  // Bits 6:4
+    U32 lock_mc_dft                             :  1;  // Bits 7:7
+    U32                                         :  24;  // Bits 31:8
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCDECS_CR_MC_LOCK_MCMAIN_STRUCT;
+
+typedef union {
+  struct {
+    U32 tRCD                                    :  5;  // Bits 4:0
+    U32 tRP                                     :  5;  // Bits 9:5
+    U32 tRAS                                    :  6;  // Bits 15:10
+    U32 tRDPRE                                  :  4;  // Bits 19:16
+    U32 tWRPRE                                  :  6;  // Bits 25:20
+    U32 tRRD                                    :  4;  // Bits 29:26
+    U32 tRPab_ext                               :  2;  // Bits 31:30
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH0_CR_TC_BANK_STRUCT;
+
+typedef union {
+  struct {
+    U32 tCKE                                    :  4;  // Bits 3:0
+    U32 tFAW                                    :  8;  // Bits 11:4
+    U32 tRDRD                                   :  3;  // Bits 14:12
+    U32 tRDRD_dr                                :  4;  // Bits 18:15
+    U32 tRDRD_dd                                :  4;  // Bits 22:19
+    U32 tRDPDEN                                 :  5;  // Bits 27:23
+    U32                                         :  1;  // Bits 28:28
+    U32 CMD_3st                                 :  1;  // Bits 29:29
+    U32 CMD_stretch                             :  2;  // Bits 31:30
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH0_CR_TC_BANK_RANK_A_STRUCT;
+
+typedef union {
+  struct {
+    U32 tWRRD                                   :  6;  // Bits 5:0
+    U32 tWRRD_dr                                :  4;  // Bits 9:6
+    U32 tWRRD_dd                                :  4;  // Bits 13:10
+    U32 tWRWR                                   :  3;  // Bits 16:14
+    U32 tWRWR_dr                                :  4;  // Bits 20:17
+    U32 tWRWR_dd                                :  4;  // Bits 24:21
+    U32 tWRPDEN                                 :  6;  // Bits 30:25
+    U32 Dec_WRD                                 :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH0_CR_TC_BANK_RANK_B_STRUCT;
+
+typedef union {
+  struct {
+    U32 tXPDLL                                  :  6;  // Bits 5:0
+    U32 tXP                                     :  4;  // Bits 9:6
+    U32 TAONPD                                  :  4;  // Bits 13:10
+    U32 tRDWR                                   :  5;  // Bits 18:14
+    U32 tRDWR_dr                                :  5;  // Bits 23:19
+    U32 tRDWR_dd                                :  5;  // Bits 28:24
+    U32                                         :  3;  // Bits 31:29
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH0_CR_TC_BANK_RANK_C_STRUCT;
+
+typedef union {
+  struct {
+    U32 enable_cmd_rate_limit                   :  1;  // Bits 0:0
+    U32 cmd_rate_limit                          :  3;  // Bits 3:1
+    U32 reset_on_command                        :  4;  // Bits 7:4
+    U32 reset_delay                             :  4;  // Bits 11:8
+    U32 ck_to_cke_delay                         :  2;  // Bits 13:12
+    U32 spare                                   :  17;  // Bits 30:14
+    U32 init_mrw_2n_cs                          :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH0_CR_CMD_RATE_STRUCT;
+
+typedef union {
+  struct {
+    U32 tCL                                     :  5;  // Bits 4:0
+    U32 tWCL                                    :  5;  // Bits 9:5
+    U32 tCPDED                                  :  2;  // Bits 11:10
+    U32 tPRPDEN                                 :  2;  // Bits 13:12
+    U32 Odt_Read_Delay                          :  3;  // Bits 16:14
+    U32 Odt_Read_Duration                       :  2;  // Bits 18:17
+    U32 Odt_Write_Duration                      :  2;  // Bits 20:19
+    U32                                         :  11;  // Bits 31:21
+  } Bits;
+#ifdef ULT_FLAG
+  struct {
+    U32 tCL                                     :  5;  // Bits 4:0
+    U32 tWCL                                    :  5;  // Bits 9:5
+    U32 tCPDED                                  :  2;  // Bits 11:10
+    U32 tPRPDEN                                 :  2;  // Bits 13:12
+    U32 Odt_Read_Delay                          :  3;  // Bits 16:14
+    U32 Odt_Read_Duration                       :  2;  // Bits 18:17
+    U32 Odt_Write_Duration                      :  3;  // Bits 21:19
+    U32 Odt_Write_Delay                         :  3;  // Bits 24:22
+    U32 Odt_Always_Rank0                        :  1;  // Bits 25:25
+    U32 cmd_delay                               :  2;  // Bits 27:26
+    U32                                         :  4;  // Bits 31:28
+  } UltBits;
+#endif // ULT_FLAG
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH0_CR_TC_BANK_RANK_D_STRUCT;
+
+typedef union {
+  struct {
+    U32 dis_opp_cas                             :  1;  // Bits 0:0
+    U32 dis_opp_is_cas                          :  1;  // Bits 1:1
+    U32 dis_opp_ras                             :  1;  // Bits 2:2
+    U32 dis_opp_is_ras                          :  1;  // Bits 3:3
+    U32 dis_1c_byp                              :  1;  // Bits 4:4
+    U32 dis_2c_byp                              :  1;  // Bits 5:5
+    U32 dis_deprd_opt                           :  1;  // Bits 6:6
+    U32 dis_pt_it                               :  1;  // Bits 7:7
+    U32 dis_prcnt_ring                          :  1;  // Bits 8:8
+    U32 dis_prcnt_sa                            :  1;  // Bits 9:9
+    U32 dis_blkr_ph                             :  1;  // Bits 10:10
+    U32 dis_blkr_pe                             :  1;  // Bits 11:11
+    U32 dis_blkr_pm                             :  1;  // Bits 12:12
+    U32 dis_odt                                 :  1;  // Bits 13:13
+    U32 OE_alw_off                              :  1;  // Bits 14:14
+    U32                                         :  1;  // Bits 15:15
+    U32 dis_aom                                 :  1;  // Bits 16:16
+    U32 block_rpq                               :  1;  // Bits 17:17
+    U32 block_wpq                               :  1;  // Bits 18:18
+    U32 invert_align                            :  1;  // Bits 19:19
+    U32 dis_write_gap                           :  1;  // Bits 20:20
+    U32 dis_zq                                  :  1;  // Bits 21:21
+    U32 dis_tt                                  :  1;  // Bits 22:22
+    U32 dis_opp_ref                             :  1;  // Bits 23:23
+    U32 Long_ZQ                                 :  1;  // Bits 24:24
+    U32 dis_srx_zq                              :  1;  // Bits 25:25
+    U32 Serialize_ZQ                            :  1;  // Bits 26:26
+    U32 ZQ_fast_exec                            :  1;  // Bits 27:27
+    U32 Dis_DriveNop                            :  1;  // Bits 28:28
+    U32 Pres_WDB_Ent                            :  1;  // Bits 29:29
+    U32 dis_clk_gate                            :  1;  // Bits 30:30
+    U32                                         :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH0_CR_SCHED_CBIT_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lat_R0D0                                :  6;  // Bits 5:0
+    U32                                         :  2;  // Bits 7:6
+    U32 Lat_R1D0                                :  6;  // Bits 13:8
+    U32                                         :  2;  // Bits 15:14
+    U32 Lat_R0D1                                :  6;  // Bits 21:16
+    U32                                         :  2;  // Bits 23:22
+    U32 Lat_R1D1                                :  6;  // Bits 29:24
+    U32                                         :  2;  // Bits 31:30
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH0_CR_SC_ROUNDT_LAT_STRUCT;
+
+typedef union {
+  struct {
+    U32 IOLAT_R0D0                              :  4;  // Bits 3:0
+    U32 IOLAT_R1D0                              :  4;  // Bits 7:4
+    U32 IOLAT_R0D1                              :  4;  // Bits 11:8
+    U32 IOLAT_R1D1                              :  4;  // Bits 15:12
+    U32 RT_IOCOMP                               :  6;  // Bits 21:16
+    U32                                         :  8;  // Bits 29:22
+    U32 three_channels                          :  1;  // Bits 30:30
+    U32 DIS_RT_CLK_GATE                         :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH0_CR_SC_IO_LATENCY_STRUCT;
+
+typedef union {
+  struct {
+    U32 DATA                                    :  32;  // Bits 31:0
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH0_CR_ROUND_TRIP_DFT_DATA_STRUCT;
+
+typedef union {
+  struct {
+    U32 WDAR                                    :  1;  // Bits 0:0
+    U32 safe_mask_sel                           :  3;  // Bits 3:1
+    U32 force_rcv_en                            :  1;  // Bits 4:4
+    U32                                         :  3;  // Bits 7:5
+    U32 DDR_QUAL                                :  2;  // Bits 9:8
+    U32 Qual_length                             :  2;  // Bits 11:10
+    U32 WDB_Block_En                            :  1;  // Bits 12:12
+    U32 RT_DFT_READ_PTR                         :  4;  // Bits 16:13
+    U32 RT_DFT_READ_ENABLE                      :  1;  // Bits 17:17
+    U32 RT_DFT_READ_SEL_ADDR                    :  1;  // Bits 18:18
+    U32                                         :  13;  // Bits 31:19
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH0_CR_DFT_MISC_STRUCT;
+
+typedef union {
+  struct {
+    U32 ECC                                     :  8;  // Bits 7:0
+    U32 RRD_DFT_Mode                            :  2;  // Bits 9:8
+    U32 LFSR_Seed_Index                         :  5;  // Bits 14:10
+    U32 Inversion_Mode                          :  1;  // Bits 15:15
+    U32                                         :  16;  // Bits 31:16
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH0_CR_READ_RETURN_DFT_STRUCT;
+
+typedef union {
+  struct {
+    U32 dis_imph_error                          :  1;  // Bits 0:0
+    U32                                         :  7;  // Bits 7:1
+    U32 dis_async_odt                           :  1;  // Bits 8:8
+    U32                                         :  23;  // Bits 31:9
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH0_CR_SCHED_SECOND_CBIT_STRUCT;
+
+typedef union {
+  struct {
+    U32 Mux0_Control                            :  2;  // Bits 1:0
+    U32                                         :  1;  // Bits 2:2
+    U32 Mux1_Control                            :  2;  // Bits 4:3
+    U32                                         :  1;  // Bits 5:5
+    U32 Mux2_Control                            :  2;  // Bits 7:6
+    U32                                         :  6;  // Bits 13:8
+    U32 ECC_Replace_Byte_Control                :  1;  // Bits 14:14
+    U32 ECC_Data_Source_Sel                     :  1;  // Bits 15:15
+    U32 Save_LFSR_Seed_Rate                     :  6;  // Bits 21:16
+    U32                                         :  2;  // Bits 23:22
+    U32 Reload_LFSR_Seed_Rate                   :  3;  // Bits 26:24
+    U32                                         :  5;  // Bits 31:27
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_STRUCT;
+
+typedef union {
+  struct {
+    U32 WDB_Current_Read_Pointer                :  6;  // Bits 5:0
+    U32                                         :  26;  // Bits 31:6
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_RD_STATUS_STRUCT;
+
+typedef union {
+  struct {
+    U32 Pattern_Buffer                          :  24;  // Bits 23:0
+    U32                                         :  8;  // Bits 31:24
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_0_STRUCT;
+
+typedef union {
+  struct {
+    U32 Pattern_Buffer                          :  24;  // Bits 23:0
+    U32                                         :  8;  // Bits 31:24
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_1_STRUCT;
+
+typedef union {
+  struct {
+    U32 Pattern_Buffer                          :  24;  // Bits 23:0
+    U32                                         :  8;  // Bits 31:24
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_2_STRUCT;
+
+typedef union {
+  struct {
+    U32 Pattern_Buffer                          :  24;  // Bits 23:0
+    U32                                         :  8;  // Bits 31:24
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_0_STRUCT;
+
+typedef union {
+  struct {
+    U32 Pattern_Buffer                          :  24;  // Bits 23:0
+    U32                                         :  8;  // Bits 31:24
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_1_STRUCT;
+
+typedef union {
+  struct {
+    U32 Pattern_Buffer                          :  24;  // Bits 23:0
+    U32                                         :  8;  // Bits 31:24
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_2_STRUCT;
+
+typedef union {
+  struct {
+    U32 Pattern_Buffer                          :  24;  // Bits 23:0
+    U32                                         :  8;  // Bits 31:24
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_0_STRUCT;
+
+typedef union {
+  struct {
+    U32 Pattern_Buffer                          :  24;  // Bits 23:0
+    U32                                         :  8;  // Bits 31:24
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_1_STRUCT;
+
+typedef union {
+  struct {
+    U32 Pattern_Buffer                          :  24;  // Bits 23:0
+    U32                                         :  8;  // Bits 31:24
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_2_STRUCT;
+
+typedef union {
+  struct {
+    U32 Pattern_Buffer                          :  24;  // Bits 23:0
+    U32                                         :  8;  // Bits 31:24
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_0_STRUCT;
+
+typedef union {
+  struct {
+    U32 Pattern_Buffer                          :  24;  // Bits 23:0
+    U32                                         :  8;  // Bits 31:24
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_1_STRUCT;
+
+typedef union {
+  struct {
+    U32 Pattern_Buffer                          :  24;  // Bits 23:0
+    U32                                         :  8;  // Bits 31:24
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_2_STRUCT;
+
+typedef union {
+  struct {
+    U32 L_data_select                           :  1;  // Bits 0:0
+    U32 Enable_Sweep_Frequency                  :  1;  // Bits 1:1
+    U32                                         :  6;  // Bits 7:2
+    U32 L_counter                               :  8;  // Bits 15:8
+    U32 M_counter                               :  8;  // Bits 23:16
+    U32 N_counter                               :  8;  // Bits 31:24
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_STRUCT;
+
+typedef union {
+  struct {
+    U32 ECC_Inv_or_DC_Enable                    :  8;  // Bits 7:0
+    U32                                         :  8;  // Bits 15:8
+    U32 Inv_or_DC_Shift_Rate                    :  4;  // Bits 19:16
+    U32 DC_Polarity_Control                     :  1;  // Bits 20:20
+    U32                                         :  9;  // Bits 29:21
+    U32 Inv_or_DC_Control                       :  1;  // Bits 30:30
+    U32 Inv_or_DC_Shift_Enable                  :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH0_CR_REUT_CH_PAT_WDB_INV_STRUCT;
+
+typedef union {
+  struct {
+    U64 Data_Inv_or_DC_Enable                   :  64;  // Bits 63:0
+  } Bits;
+  U64 Data;
+  U32 Data32[2];
+  U16 Data16[4];
+  U8  Data8[8];
+} MCHBAR_CH0_CR_REUT_CH_PAT_WDB_DATA_INV_STRUCT;
+
+typedef union {
+  struct {
+    U32 Stop_on_Nth_Error                       :  6;  // Bits 5:0
+    U32                                         :  6;  // Bits 11:6
+    U32 Stop_On_Error_Control                   :  2;  // Bits 13:12
+    U32                                         :  2;  // Bits 15:14
+    U32 Selective_Error_Enable_Chunk            :  8;  // Bits 23:16
+    U32 Selective_Error_Enable_Cacheline        :  8;  // Bits 31:24
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH0_CR_REUT_CH_ERR_CTL_STRUCT;
+
+typedef union {
+  struct {
+    U32 ECC_Error_Mask                          :  8;  // Bits 7:0
+    U32                                         :  24;  // Bits 31:8
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH0_CR_REUT_CH_ERR_ECC_MASK_STRUCT;
+
+typedef union {
+  struct {
+    U32 Stretch_mode                            :  2;  // Bits 1:0
+    U32                                         :  2;  // Bits 3:2
+    U32 STF                                     :  3;  // Bits 6:4
+    U32                                         :  25;  // Bits 31:7
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH0_CR_STM_CONFIG_STRUCT;
+
+typedef union {
+  struct {
+    U32 Priority_count_ring                     :  10;  // Bits 9:0
+    U32                                         :  6;  // Bits 15:10
+    U32 Priority_count_SA                       :  10;  // Bits 25:16
+    U32                                         :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH0_CR_SC_PR_CNT_CONFIG_STRUCT;
+
+typedef union {
+  struct {
+    U32 PCIT                                    :  8;  // Bits 7:0
+    U32                                         :  24;  // Bits 31:8
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH0_CR_SC_PCIT_STRUCT;
+
+typedef union {
+  struct {
+    U32 PDWN_idle_counter                       :  12;  // Bits 11:0
+    U32 PDWN_mode                               :  4;  // Bits 15:12
+    U32                                         :  16;  // Bits 31:16
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH0_CR_PM_PDWN_CONFIG_STRUCT;
+
+typedef union {
+  struct {
+    U32 Count                                   :  32;  // Bits 31:0
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH0_CR_ECC_INJECT_COUNT_STRUCT;
+
+typedef union {
+  struct {
+    U32 ECC4ANA_fill                            :  8;  // Bits 7:0
+    U32 ECC4ANA_trigger                         :  2;  // Bits 9:8
+    U32 ECC4ANA_BS                              :  1;  // Bits 10:10
+    U32 ECC_Inject                              :  3;  // Bits 13:11
+    U32 ECC_correction_disable                  :  1;  // Bits 14:14
+    U32 ECC4ANA_Inject                          :  1;  // Bits 15:15
+    U32 DIS_MCA_LOG                             :  1;  // Bits 16:16
+    U32 DIS_PCH_EVENT                           :  1;  // Bits 17:17
+    U32 DIS_PCIE_POISON                         :  1;  // Bits 18:18
+    U32                                         :  13;  // Bits 31:19
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH0_CR_ECC_DFT_STRUCT;
+
+typedef union {
+  struct {
+    U32 Data                                    :  18;  // Bits 17:0
+    U32                                         :  13;  // Bits 30:18
+    U32 VORANGE                                 :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH0_CR_VISA_CTL_MCSCHEDS_STRUCT;
+
+typedef union {
+  struct {
+    U32 Data                                    :  32;  // Bits 31:0
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH0_CR_VISA_XBAR_MCSCHEDS_STRUCT;
+
+typedef union {
+  struct {
+    U32 CERRSTS                                 :  1;  // Bits 0:0
+    U32 MERRSTS                                 :  1;  // Bits 1:1
+    U32                                         :  14;  // Bits 15:2
+    U32 ERRSYND                                 :  8;  // Bits 23:16
+    U32 ERRCHUNK                                :  3;  // Bits 26:24
+    U32 ERRRANK                                 :  2;  // Bits 28:27
+    U32 ERRBANK                                 :  3;  // Bits 31:29
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH0_CR_ECCERRLOG0_STRUCT;
+
+typedef union {
+  struct {
+    U32 ERRROW                                  :  16;  // Bits 15:0
+    U32 ERRCOL                                  :  16;  // Bits 31:16
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH0_CR_ECCERRLOG1_STRUCT;
+
+typedef union {
+  struct {
+    U32 D0R0                                    :  2;  // Bits 1:0
+    U32 D0R1                                    :  2;  // Bits 3:2
+    U32 D1R0                                    :  2;  // Bits 5:4
+    U32 D1R1                                    :  2;  // Bits 7:6
+    U32                                         :  24;  // Bits 31:8
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH0_CR_SC_WR_ADD_DELAY_STRUCT;
+
+typedef union {
+  struct {
+    U32 Dis_Opp_rd                              :  1;  // Bits 0:0
+    U32 ACT_Enable                              :  1;  // Bits 1:1
+    U32 PRE_Enable                              :  1;  // Bits 2:2
+    U32 MAX_RPQ_Cas                             :  4;  // Bits 6:3
+    U32                                         :  25;  // Bits 31:7
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH0_CR_WMM_READ_CONFIG_STRUCT;
+
+typedef union {
+  struct {
+    U64 Data_Error_Mask                         :  64;  // Bits 63:0
+  } Bits;
+  U64 Data;
+  U32 Data32[2];
+  U16 Data16[4];
+  U8  Data8[8];
+} MCHBAR_CH0_CR_REUT_CH_ERR_DATA_MASK_STRUCT;
+
+typedef union {
+  struct {
+    U64 Data_Error_Status                       :  64;  // Bits 63:0
+  } Bits;
+  U64 Data;
+  U32 Data32[2];
+  U16 Data16[4];
+  U8  Data8[8];
+} MCHBAR_CH0_CR_REUT_CH_ERR_DATA_STATUS_STRUCT;
+
+typedef union {
+  struct {
+    U32 ECC_Error_Status                        :  8;  // Bits 7:0
+    U32 Chunk_Error_Status                      :  8;  // Bits 15:8
+    U32 Rank_Error_Status                       :  4;  // Bits 19:16
+    U32                                         :  12;  // Bits 31:20
+    U32 Byte_Group_Error_Status                 :  9;  // Bits 40:32
+    U32                                         :  11;  // Bits 51:41
+    U32 WDB_Rd_Chunk_Num_Status                 :  3;  // Bits 54:52
+    U32                                         :  1;  // Bits 55:55
+    U32 Nth_Error                               :  6;  // Bits 61:56
+    U32                                         :  2;  // Bits 63:62
+  } Bits;
+  U64 Data;
+  U32 Data32[2];
+  U16 Data16[4];
+  U8  Data8[8];
+} MCHBAR_CH0_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_STRUCT;
+
+typedef union {
+  struct {
+    U32 Counter_Pointer                         :  7;  // Bits 6:0
+    U32 Counter_Control                         :  2;  // Bits 8:7
+    U32                                         :  23;  // Bits 31:9
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_0_STRUCT;
+
+typedef union {
+  struct {
+    U32 Counter_Pointer                         :  7;  // Bits 6:0
+    U32 Counter_Control                         :  2;  // Bits 8:7
+    U32                                         :  23;  // Bits 31:9
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_1_STRUCT;
+
+typedef union {
+  struct {
+    U32 Counter_Pointer                         :  7;  // Bits 6:0
+    U32 Counter_Control                         :  2;  // Bits 8:7
+    U32                                         :  23;  // Bits 31:9
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_2_STRUCT;
+
+typedef union {
+  struct {
+    U32 Counter_Pointer                         :  7;  // Bits 6:0
+    U32 Counter_Control                         :  2;  // Bits 8:7
+    U32                                         :  23;  // Bits 31:9
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_3_STRUCT;
+
+typedef union {
+  struct {
+    U32 Counter_Pointer                         :  7;  // Bits 6:0
+    U32 Counter_Control                         :  2;  // Bits 8:7
+    U32                                         :  23;  // Bits 31:9
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_4_STRUCT;
+
+typedef union {
+  struct {
+    U32 Counter_Pointer                         :  7;  // Bits 6:0
+    U32 Counter_Control                         :  2;  // Bits 8:7
+    U32                                         :  23;  // Bits 31:9
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_5_STRUCT;
+
+typedef union {
+  struct {
+    U32 Counter_Pointer                         :  7;  // Bits 6:0
+    U32 Counter_Control                         :  2;  // Bits 8:7
+    U32                                         :  23;  // Bits 31:9
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_6_STRUCT;
+
+typedef union {
+  struct {
+    U32 Counter_Pointer                         :  7;  // Bits 6:0
+    U32 Counter_Control                         :  2;  // Bits 8:7
+    U32                                         :  23;  // Bits 31:9
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_7_STRUCT;
+
+typedef union {
+  struct {
+    U32 Counter_Pointer                         :  7;  // Bits 6:0
+    U32 Counter_Control                         :  2;  // Bits 8:7
+    U32                                         :  23;  // Bits 31:9
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_8_STRUCT;
+
+typedef union {
+  struct {
+    U32 Counter_Status                          :  23;  // Bits 22:0
+    U32                                         :  9;  // Bits 31:23
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_0_STRUCT;
+
+typedef union {
+  struct {
+    U32 Counter_Status                          :  23;  // Bits 22:0
+    U32                                         :  9;  // Bits 31:23
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_1_STRUCT;
+
+typedef union {
+  struct {
+    U32 Counter_Status                          :  23;  // Bits 22:0
+    U32                                         :  9;  // Bits 31:23
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_2_STRUCT;
+
+typedef union {
+  struct {
+    U32 Counter_Status                          :  23;  // Bits 22:0
+    U32                                         :  9;  // Bits 31:23
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_3_STRUCT;
+
+typedef union {
+  struct {
+    U32 Counter_Status                          :  23;  // Bits 22:0
+    U32                                         :  9;  // Bits 31:23
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_4_STRUCT;
+
+typedef union {
+  struct {
+    U32 Counter_Status                          :  23;  // Bits 22:0
+    U32                                         :  9;  // Bits 31:23
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_5_STRUCT;
+
+typedef union {
+  struct {
+    U32 Counter_Status                          :  23;  // Bits 22:0
+    U32                                         :  9;  // Bits 31:23
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_6_STRUCT;
+
+typedef union {
+  struct {
+    U32 Counter_Status                          :  23;  // Bits 22:0
+    U32                                         :  9;  // Bits 31:23
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_7_STRUCT;
+
+typedef union {
+  struct {
+    U32 Counter_Status                          :  23;  // Bits 22:0
+    U32                                         :  9;  // Bits 31:23
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_8_STRUCT;
+
+typedef union {
+  struct {
+    U32 Counter_Overflow_Status                 :  9;  // Bits 8:0
+    U32                                         :  23;  // Bits 31:9
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_OVERFLOW_STATUS_STRUCT;
+
+typedef union {
+  struct {
+    U32 Column_Address                          :  10;  // Bits 9:0
+    U32                                         :  14;  // Bits 23:10
+    U32 Row_Address                             :  16;  // Bits 39:24
+    U32                                         :  8;  // Bits 47:40
+    U32 Bank_Address                            :  3;  // Bits 50:48
+    U32                                         :  5;  // Bits 55:51
+    U32 Rank_Address                            :  2;  // Bits 57:56
+    U32                                         :  6;  // Bits 63:58
+  } Bits;
+  U64 Data;
+  U32 Data32[2];
+  U16 Data16[4];
+  U8  Data8[8];
+} MCHBAR_CH0_CR_REUT_CH_ERROR_ADDR_STRUCT;
+
+typedef union {
+  struct {
+    U32 WDB_Current_Error_Pointer               :  6;  // Bits 5:0
+    U32                                         :  26;  // Bits 31:6
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH0_CR_REUT_CH_ERR_WDB_CAPTURE_STATUS_STRUCT;
+
+typedef union {
+  struct {
+    U32 Enable_WDB_Error_Capture                :  1;  // Bits 0:0
+    U32                                         :  7;  // Bits 7:1
+    U32 WDB_Starting_Error_Pointer              :  6;  // Bits 13:8
+    U32                                         :  2;  // Bits 15:14
+    U32 WDB_Ending_Error_Pointer                :  6;  // Bits 21:16
+    U32                                         :  10;  // Bits 31:22
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH0_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_STRUCT;
+
+typedef union {
+  struct {
+    U32 CKE_Override                            :  4;  // Bits 3:0
+    U32                                         :  4;  // Bits 7:4
+    U32 CKE_En_Start_Test_Sync                  :  1;  // Bits 8:8
+    U32                                         :  7;  // Bits 15:9
+    U32 CKE_On                                  :  4;  // Bits 19:16
+    U32                                         :  12;  // Bits 31:20
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH0_CR_REUT_CH_MISC_CKE_CTRL_STRUCT;
+
+typedef union {
+  struct {
+    U32 ODT_Override                            :  4;  // Bits 3:0
+    U32                                         :  12;  // Bits 15:4
+    U32 ODT_On                                  :  4;  // Bits 19:16
+    U32                                         :  11;  // Bits 30:20
+    U32 MPR_Train_DDR_On                        :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH0_CR_REUT_CH_MISC_ODT_CTRL_STRUCT;
+
+typedef union {
+  struct {
+    U32 Enable_CADB_on_Deselect                 :  1;  // Bits 0:0
+    U32 Enable_CADB_Always_On                   :  1;  // Bits 1:1
+    U32 CMD_Deselect_Start                      :  4;  // Bits 5:2
+    U32 CMD_Deselect_Stop                       :  4;  // Bits 9:6
+    U32 Lane_Deselect_Enable                    :  4;  // Bits 13:10
+    U32 CAS_Select_Enable                       :  2;  // Bits 15:14
+    U32 ACT_Select_Enable                       :  2;  // Bits 17:16
+    U32 PRE_Select_Enable                       :  2;  // Bits 19:18
+    U32 Save_Current_Seed                       :  4;  // Bits 23:20
+    U32 Reload_Starting_Seed                    :  4;  // Bits 27:24
+    U32                                         :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_STRUCT;
+
+typedef union {
+  struct {
+    U32 MRS_Gap                                 :  3;  // Bits 2:0
+    U32                                         :  5;  // Bits 7:3
+    U32 CADB_MRS_Start_Pointer                  :  3;  // Bits 10:8
+    U32                                         :  5;  // Bits 15:11
+    U32 CADB_MRS_End_Pointer                    :  3;  // Bits 18:16
+    U32                                         :  5;  // Bits 23:19
+    U32 CADB_MRS_Current_Pointer                :  3;  // Bits 26:24
+    U32                                         :  5;  // Bits 31:27
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MRS_STRUCT;
+
+typedef union {
+  struct {
+    U32 Mux0_Control                            :  2;  // Bits 1:0
+    U32                                         :  2;  // Bits 3:2
+    U32 Mux1_Control                            :  2;  // Bits 5:4
+    U32                                         :  2;  // Bits 7:6
+    U32 Mux2_Control                            :  2;  // Bits 9:8
+    U32                                         :  6;  // Bits 15:10
+    U32 Select_Mux0_Control                     :  2;  // Bits 17:16
+    U32                                         :  2;  // Bits 19:18
+    U32 Select_Mux1_Control                     :  2;  // Bits 21:20
+    U32                                         :  2;  // Bits 23:22
+    U32 Select_Mux2_Control                     :  2;  // Bits 25:24
+    U32                                         :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_CTRL_STRUCT;
+
+typedef union {
+  struct {
+    U32 Pattern_Buffer                          :  16;  // Bits 15:0
+    U32                                         :  16;  // Bits 31:16
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_PB_0_STRUCT;
+
+typedef union {
+  struct {
+    U32 Pattern_Buffer                          :  16;  // Bits 15:0
+    U32                                         :  16;  // Bits 31:16
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_PB_1_STRUCT;
+
+typedef union {
+  struct {
+    U32 Pattern_Buffer                          :  16;  // Bits 15:0
+    U32                                         :  16;  // Bits 31:16
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_PB_2_STRUCT;
+
+typedef union {
+  struct {
+    U32 L_data_select                           :  1;  // Bits 0:0
+    U32 Enable_Sweep_Frequency                  :  1;  // Bits 1:1
+    U32                                         :  6;  // Bits 7:2
+    U32 L_counter                               :  8;  // Bits 15:8
+    U32 M_counter                               :  8;  // Bits 23:16
+    U32 N_counter                               :  8;  // Bits 31:24
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_STRUCT;
+
+typedef union {
+  struct {
+    U32 CADB_Write_Pointer                      :  3;  // Bits 2:0
+    U32                                         :  29;  // Bits 31:3
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH0_CR_REUT_CH_PAT_CADB_WRITE_POINTER_STRUCT;
+
+typedef union {
+  struct {
+    U32 CADB_Data_Address                       :  16;  // Bits 15:0
+    U32                                         :  8;  // Bits 23:16
+    U32 CADB_Data_Bank                          :  3;  // Bits 26:24
+    U32                                         :  5;  // Bits 31:27
+    U32 CADB_Data_CS                            :  4;  // Bits 35:32
+    U32                                         :  4;  // Bits 39:36
+    U32 CADB_Data_Control                       :  3;  // Bits 42:40
+    U32                                         :  5;  // Bits 47:43
+    U32 CADB_Data_ODT                           :  4;  // Bits 51:48
+    U32                                         :  4;  // Bits 55:52
+    U32 CADB_Data_CKE                           :  4;  // Bits 59:56
+    U32                                         :  4;  // Bits 63:60
+  } Bits;
+  U64 Data;
+  U32 Data32[2];
+  U16 Data16[4];
+  U8  Data8[8];
+} MCHBAR_CH0_CR_REUT_CH_PAT_CADB_PROG_STRUCT;
+
+typedef union {
+  struct {
+    U32 Pattern_Buffer                          :  16;  // Bits 15:0
+    U32                                         :  16;  // Bits 31:16
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH0_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_0_STRUCT;
+
+typedef union {
+  struct {
+    U32 Pattern_Buffer                          :  16;  // Bits 15:0
+    U32                                         :  16;  // Bits 31:16
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH0_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_1_STRUCT;
+
+typedef union {
+  struct {
+    U32 Pattern_Buffer                          :  16;  // Bits 15:0
+    U32                                         :  16;  // Bits 31:16
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH0_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_2_STRUCT;
+
+typedef union {
+  struct {
+    U32 WDB_Increment_Rate                      :  5;  // Bits 4:0
+    U32 WDB_Increment_Scale                     :  1;  // Bits 5:5
+    U32                                         :  2;  // Bits 7:6
+    U32 WDB_Start_Pointer                       :  6;  // Bits 13:8
+    U32                                         :  2;  // Bits 15:14
+    U32 WDB_End_Pointer                         :  6;  // Bits 21:16
+    U32                                         :  10;  // Bits 31:22
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_CTRL_STRUCT;
+
+typedef union {
+  struct {
+    U32 Refresh_Rank_Mask                       :  4;  // Bits 3:0
+    U32                                         :  4;  // Bits 7:4
+    U32 RefZQ_En_Start_Test_Sync                :  1;  // Bits 8:8
+    U32                                         :  22;  // Bits 30:9
+    U32 Panic_Refresh_Only                      :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH0_CR_REUT_CH_MISC_REFRESH_CTRL_STRUCT;
+
+typedef union {
+  struct {
+    U32 ZQ_Rank_Mask                            :  4;  // Bits 3:0
+    U32                                         :  27;  // Bits 30:4
+    U32 Always_Do_ZQ                            :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH0_CR_REUT_CH_MISC_ZQ_CTRL_STRUCT;
+
+#ifdef ULT_FLAG
+typedef union {
+  struct {
+    U32 Rank_0_x32                              :  1;  // Bits 0:0
+    U32 Rank_1_x32                              :  1;  // Bits 1:1
+    U32 Rank_2_x32                              :  1;  // Bits 2:2
+    U32 Rank_3_x32                              :  1;  // Bits 3:3
+    U32 LPDDR2                                  :  1;  // Bits 4:4
+    U32                                         :  3;  // Bits 7:5
+    U32 MR4_PERIOD                              :  16;  // Bits 23:8
+    U32                                         :  8;  // Bits 31:24
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH0_CR_LPDDR_MR_PARAMS_STRUCT;
+
+typedef union {
+  struct {
+    U32 Address                                 :  8;  // Bits 7:0
+    U32 Data                                    :  8;  // Bits 15:8
+    U32 Rank                                    :  2;  // Bits 17:16
+    U32 Write                                   :  1;  // Bits 18:18
+    U32 Init_MRW                                :  1;  // Bits 19:19
+    U32                                         :  11;  // Bits 30:20
+    U32 Busy                                    :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH0_CR_LPDDR_MR_COMMAND_STRUCT;
+
+typedef union {
+  struct {
+    U32 Device_0                                :  8;  // Bits 7:0
+    U32 Device_1                                :  8;  // Bits 15:8
+    U32 Device_2                                :  8;  // Bits 23:16
+    U32 Device_3                                :  8;  // Bits 31:24
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH0_CR_LPDDR_MR_RESULT_STRUCT;
+
+typedef union {
+  struct {
+    U32 Rank_0                                  :  3;  // Bits 2:0
+    U32                                         :  5;  // Bits 7:3
+    U32 Rank_1                                  :  3;  // Bits 10:8
+    U32                                         :  5;  // Bits 15:11
+    U32 Rank_2                                  :  3;  // Bits 18:16
+    U32                                         :  5;  // Bits 23:19
+    U32 Rank_3                                  :  3;  // Bits 26:24
+    U32                                         :  5;  // Bits 31:27
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH0_CR_LPDDR_MR4_RANK_TEMPERATURE_STRUCT;
+
+typedef union {
+  struct {
+    U32 Bit_0                                   :  3;  // Bits 2:0
+    U32                                         :  1;  // Bits 3:3
+    U32 Bit_1                                   :  3;  // Bits 6:4
+    U32                                         :  1;  // Bits 7:7
+    U32 Bit_2                                   :  3;  // Bits 10:8
+    U32                                         :  1;  // Bits 11:11
+    U32 Bit_16                                  :  3;  // Bits 14:12
+    U32                                         :  1;  // Bits 15:15
+    U32 Bit_17                                  :  3;  // Bits 18:16
+    U32                                         :  1;  // Bits 19:19
+    U32 Bit_18                                  :  3;  // Bits 22:20
+    U32                                         :  1;  // Bits 23:23
+    U32 Byte_0                                  :  3;  // Bits 26:24
+    U32                                         :  1;  // Bits 27:27
+    U32 Byte_2                                  :  3;  // Bits 30:28
+    U32                                         :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH0_CR_DESWIZZLE_LOW_STRUCT;
+
+typedef union {
+  struct {
+    U32 Bit_32                                  :  3;  // Bits 2:0
+    U32                                         :  1;  // Bits 3:3
+    U32 Bit_33                                  :  3;  // Bits 6:4
+    U32                                         :  1;  // Bits 7:7
+    U32 Bit_34                                  :  3;  // Bits 10:8
+    U32                                         :  1;  // Bits 11:11
+    U32 Bit_48                                  :  3;  // Bits 14:12
+    U32                                         :  1;  // Bits 15:15
+    U32 Bit_49                                  :  3;  // Bits 18:16
+    U32                                         :  1;  // Bits 19:19
+    U32 Bit_50                                  :  3;  // Bits 22:20
+    U32                                         :  1;  // Bits 23:23
+    U32 Byte_4                                  :  3;  // Bits 26:24
+    U32                                         :  1;  // Bits 27:27
+    U32 Byte_6                                  :  3;  // Bits 30:28
+    U32                                         :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH0_CR_DESWIZZLE_HIGH_STRUCT;
+#endif // ULT_FLAG
+
+typedef union {
+  struct {
+    U32 Ref_Interval                            :  11;  // Bits 10:0
+    U32 Ref_Stagger_En                          :  1;  // Bits 11:11
+    U32 Ref_Stagger_Mode                        :  1;  // Bits 12:12
+    U32 Disable_Stolen_Refresh                  :  1;  // Bits 13:13
+    U32 En_Ref_Type_Display                     :  1;  // Bits 14:14
+    U32                                         :  17;  // Bits 31:15
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH0_CR_MC_REFRESH_STAGGER_STRUCT;
+
+typedef union {
+  struct {
+    U32 ZQCS_period                             :  8;  // Bits 7:0
+    U32 tZQCS                                   :  8;  // Bits 15:8
+    U32                                         :  16;  // Bits 31:16
+  } Bits;
+#ifdef ULT_FLAG
+  struct {
+    U32 ZQCS_period                             :  10;  // Bits 9:0
+    U32 tZQCS                                   :  10;  // Bits 19:10
+    U32                                         :  12;  // Bits 31:20
+  } UltBits;
+#endif // ULT_FLAG
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH0_CR_TC_ZQCAL_STRUCT;
+
+typedef union {
+  struct {
+    U32 OREF_RI                                 :  8;  // Bits 7:0
+    U32 Refresh_HP_WM                           :  4;  // Bits 11:8
+    U32 Refresh_panic_wm                        :  4;  // Bits 15:12
+    U32                                         :  16;  // Bits 31:16
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH0_CR_TC_RFP_STRUCT;
+
+typedef union {
+  struct {
+    U32 tREFI                                   :  16;  // Bits 15:0
+    U32 tRFC                                    :  9;  // Bits 24:16
+    U32 tREFIx9                                 :  7;  // Bits 31:25
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH0_CR_TC_RFTP_STRUCT;
+
+typedef union {
+  struct {
+    U32 MR2_sh_low                              :  6;  // Bits 5:0
+    U32 SRT_avail                               :  2;  // Bits 7:6
+    U32 MR2_sh_high                             :  3;  // Bits 10:8
+    U32                                         :  3;  // Bits 13:11
+    U32 Addr_bit_swizzle                        :  2;  // Bits 15:14
+    U32                                         :  16;  // Bits 31:16
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH0_CR_TC_MR2_SHADDOW_STRUCT;
+
+typedef union {
+  struct {
+    U32 Rank_occupancy                          :  4;  // Bits 3:0
+    U32                                         :  28;  // Bits 31:4
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH0_CR_MC_INIT_STATE_STRUCT;
+
+typedef union {
+  struct {
+    U32 tXSDLL                                  :  12;  // Bits 11:0
+    U32 tXS_offset                              :  4;  // Bits 15:12
+    U32 tZQOPER                                 :  10;  // Bits 25:16
+    U32                                         :  2;  // Bits 27:26
+    U32 tMOD                                    :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH0_CR_TC_SRFTP_STRUCT;
+
+typedef union {
+  struct {
+    U32 VISAByteSel                             :  3;  // Bits 2:0
+    U32                                         :  29;  // Bits 31:3
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH0_CR_WDB_VISA_SEL_STRUCT;
+
+typedef union {
+  struct {
+    U32 FASTADDR                                :  12;  // Bits 11:0
+    U32                                         :  4;  // Bits 15:12
+    U32 ADDREN                                  :  1;  // Bits 16:16
+    U32 SEQEN                                   :  1;  // Bits 17:17
+    U32 POL0                                    :  1;  // Bits 18:18
+    U32 POL1                                    :  1;  // Bits 19:19
+    U32 CMDA                                    :  4;  // Bits 23:20
+    U32 CMDB                                    :  4;  // Bits 27:24
+    U32 CMDC                                    :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH0_CR_DCLK_LDAT_PDAT_STRUCT;
+
+typedef union {
+  struct {
+    U32 BANKSEL                                 :  4;  // Bits 3:0
+    U32                                         :  1;  // Bits 4:4
+    U32 ARRAYSEL                                :  5;  // Bits 9:5
+    U32 CMP                                     :  1;  // Bits 10:10
+    U32 REP                                     :  1;  // Bits 11:11
+    U32 DWORD                                   :  4;  // Bits 15:12
+    U32 MODE                                    :  2;  // Bits 17:16
+    U32 MPMAP                                   :  6;  // Bits 23:18
+    U32 MPBOFFSET                               :  4;  // Bits 27:24
+    U32 STAGE_EN                                :  1;  // Bits 28:28
+    U32 SHADOW                                  :  2;  // Bits 30:29
+    U32                                         :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH0_CR_DCLK_LDAT_SDAT_STRUCT;
+
+typedef union {
+  struct {
+    U32 DATOUT                                  :  32;  // Bits 31:0
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH0_CR_DCLK_LDAT_DATAOUT_STRUCT;
+
+typedef union {
+  struct {
+    U32 DATIN                                   :  32;  // Bits 31:0
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH0_CR_DCLK_LDAT_DATAIN_0_STRUCT;
+
+typedef union {
+  struct {
+    U32 FASTADDR                                :  12;  // Bits 11:0
+    U32                                         :  4;  // Bits 15:12
+    U32 ADDREN                                  :  1;  // Bits 16:16
+    U32 SEQEN                                   :  1;  // Bits 17:17
+    U32 POL0                                    :  1;  // Bits 18:18
+    U32 POL1                                    :  1;  // Bits 19:19
+    U32 CMDA                                    :  4;  // Bits 23:20
+    U32 CMDB                                    :  4;  // Bits 27:24
+    U32 CMDC                                    :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH0_CR_QCLK_LDAT_PDAT_STRUCT;
+
+typedef union {
+  struct {
+    U32 BANKSEL                                 :  4;  // Bits 3:0
+    U32                                         :  1;  // Bits 4:4
+    U32 ARRAYSEL                                :  5;  // Bits 9:5
+    U32 CMP                                     :  1;  // Bits 10:10
+    U32 REP                                     :  1;  // Bits 11:11
+    U32 DWORD                                   :  4;  // Bits 15:12
+    U32 MODE                                    :  2;  // Bits 17:16
+    U32 MPMAP                                   :  6;  // Bits 23:18
+    U32 MPBOFFSET                               :  4;  // Bits 27:24
+    U32 STAGE_EN                                :  1;  // Bits 28:28
+    U32 SHADOW                                  :  2;  // Bits 30:29
+    U32                                         :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH0_CR_QCLK_LDAT_SDAT_STRUCT;
+
+typedef union {
+  struct {
+    U32 DATOUT                                  :  32;  // Bits 31:0
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH0_CR_QCLK_LDAT_DATAOUT_STRUCT;
+
+typedef union {
+  struct {
+    U32 DATIN                                   :  32;  // Bits 31:0
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH0_CR_QCLK_LDAT_DATAIN_0_STRUCT;
+
+typedef union {
+  struct {
+    U32 DATIN                                   :  32;  // Bits 31:0
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH0_CR_QCLK_LDAT_DATAIN_1_STRUCT;
+
+typedef union {
+  struct {
+    U32 RPQ_disable                             :  28;  // Bits 27:0
+    U32                                         :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH0_CR_QUEUE_ENTRY_DISABLE_RPQ_STRUCT;
+
+typedef union {
+  struct {
+    U32 WPQ_disable                             :  32;  // Bits 31:0
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH0_CR_QUEUE_ENTRY_DISABLE_WPQ_STRUCT;
+
+typedef union {
+  struct {
+    U32 DIMM0_IDLE_ENERGY                       :  6;  // Bits 5:0
+    U32                                         :  2;  // Bits 7:6
+    U32 DIMM1_IDLE_ENERGY                       :  6;  // Bits 13:8
+    U32                                         :  18;  // Bits 31:14
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH0_CR_PM_DIMM_IDLE_ENERGY_STRUCT;
+
+typedef union {
+  struct {
+    U32 DIMM0_PD_ENERGY                         :  6;  // Bits 5:0
+    U32                                         :  2;  // Bits 7:6
+    U32 DIMM1_PD_ENERGY                         :  6;  // Bits 13:8
+    U32                                         :  18;  // Bits 31:14
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH0_CR_PM_DIMM_PD_ENERGY_STRUCT;
+
+typedef union {
+  struct {
+    U32 DIMM0_ACT_ENERGY                        :  8;  // Bits 7:0
+    U32 DIMM1_ACT_ENERGY                        :  8;  // Bits 15:8
+    U32                                         :  16;  // Bits 31:16
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH0_CR_PM_DIMM_ACT_ENERGY_STRUCT;
+
+typedef union {
+  struct {
+    U32 DIMM0_RD_ENERGY                         :  8;  // Bits 7:0
+    U32 DIMM1_RD_ENERGY                         :  8;  // Bits 15:8
+    U32                                         :  16;  // Bits 31:16
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH0_CR_PM_DIMM_RD_ENERGY_STRUCT;
+
+typedef union {
+  struct {
+    U32 DIMM0_WR_ENERGY                         :  8;  // Bits 7:0
+    U32 DIMM1_WR_ENERGY                         :  8;  // Bits 15:8
+    U32                                         :  16;  // Bits 31:16
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH0_CR_PM_DIMM_WR_ENERGY_STRUCT;
+
+typedef union {
+  struct {
+    U32 CKE_MIN                                 :  8;  // Bits 7:0
+    U32 CKE_MIN_DEFEATURE                       :  1;  // Bits 8:8
+    U32                                         :  23;  // Bits 31:9
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH0_CR_PM_THRT_CKE_MIN_STRUCT;
+
+typedef union {
+  struct {
+    U32 ODT                                     :  4;  // Bits 3:0
+    U32 Web                                     :  1;  // Bits 4:4
+    U32 CASb                                    :  1;  // Bits 5:5
+    U32 RASb                                    :  1;  // Bits 6:6
+    U32 CSb                                     :  4;  // Bits 10:7
+    U32 CKE                                     :  4;  // Bits 14:11
+    U32 MA                                      :  16;  // Bits 30:15
+    U32                                         :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH0_CR_ODLAT_CMD_MATCH0_STRUCT;
+
+typedef union {
+  struct {
+    U32 ODT                                     :  4;  // Bits 3:0
+    U32 Web                                     :  1;  // Bits 4:4
+    U32 CASb                                    :  1;  // Bits 5:5
+    U32 RASb                                    :  1;  // Bits 6:6
+    U32 CSb                                     :  4;  // Bits 10:7
+    U32 CKE                                     :  4;  // Bits 14:11
+    U32 MA                                      :  16;  // Bits 30:15
+    U32                                         :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH0_CR_ODLAT_CMD_MATCH1_STRUCT;
+
+typedef union {
+  struct {
+    U32 ODT                                     :  4;  // Bits 3:0
+    U32 Web                                     :  1;  // Bits 4:4
+    U32 CASb                                    :  1;  // Bits 5:5
+    U32 RASb                                    :  1;  // Bits 6:6
+    U32 CSb                                     :  4;  // Bits 10:7
+    U32 CKE                                     :  4;  // Bits 14:11
+    U32 MA                                      :  16;  // Bits 30:15
+    U32                                         :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH0_CR_ODLAT_CMD_MATCH2_STRUCT;
+
+typedef union {
+  struct {
+    U32 ODT                                     :  4;  // Bits 3:0
+    U32 Web                                     :  1;  // Bits 4:4
+    U32 CASb                                    :  1;  // Bits 5:5
+    U32 RASb                                    :  1;  // Bits 6:6
+    U32 CSb                                     :  4;  // Bits 10:7
+    U32 CKE                                     :  4;  // Bits 14:11
+    U32 MA                                      :  16;  // Bits 30:15
+    U32                                         :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH0_CR_ODLAT_CMD_MATCH3_STRUCT;
+
+typedef union {
+  struct {
+    U32 ODT                                     :  4;  // Bits 3:0
+    U32 Web                                     :  1;  // Bits 4:4
+    U32 CASb                                    :  1;  // Bits 5:5
+    U32 RASb                                    :  1;  // Bits 6:6
+    U32 CSb                                     :  4;  // Bits 10:7
+    U32 CKE                                     :  4;  // Bits 14:11
+    U32 MA                                      :  16;  // Bits 30:15
+    U32                                         :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH0_CR_ODLAT_CMD_MASK0_STRUCT;
+
+typedef union {
+  struct {
+    U32 ODT                                     :  4;  // Bits 3:0
+    U32 Web                                     :  1;  // Bits 4:4
+    U32 CASb                                    :  1;  // Bits 5:5
+    U32 RASb                                    :  1;  // Bits 6:6
+    U32 CSb                                     :  4;  // Bits 10:7
+    U32 CKE                                     :  4;  // Bits 14:11
+    U32 MA                                      :  16;  // Bits 30:15
+    U32                                         :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH0_CR_ODLAT_CMD_MASK1_STRUCT;
+
+typedef union {
+  struct {
+    U32 ODT                                     :  4;  // Bits 3:0
+    U32 Web                                     :  1;  // Bits 4:4
+    U32 CASb                                    :  1;  // Bits 5:5
+    U32 RASb                                    :  1;  // Bits 6:6
+    U32 CSb                                     :  4;  // Bits 10:7
+    U32 CKE                                     :  4;  // Bits 14:11
+    U32 MA                                      :  16;  // Bits 30:15
+    U32                                         :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH0_CR_ODLAT_CMD_MASK2_STRUCT;
+
+typedef union {
+  struct {
+    U32 ODT                                     :  4;  // Bits 3:0
+    U32 Web                                     :  1;  // Bits 4:4
+    U32 CASb                                    :  1;  // Bits 5:5
+    U32 RASb                                    :  1;  // Bits 6:6
+    U32 CSb                                     :  4;  // Bits 10:7
+    U32 CKE                                     :  4;  // Bits 14:11
+    U32 MA                                      :  16;  // Bits 30:15
+    U32                                         :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH0_CR_ODLAT_CMD_MASK3_STRUCT;
+
+typedef union {
+  struct {
+    U32 BankMatch0                              :  3;  // Bits 2:0
+    U32 BankMatch1                              :  3;  // Bits 5:3
+    U32 BankMatch2                              :  3;  // Bits 8:6
+    U32 BankMatch3                              :  3;  // Bits 11:9
+    U32 BankMask0                               :  3;  // Bits 14:12
+    U32 BankMask1                               :  3;  // Bits 17:15
+    U32 BankMask2                               :  3;  // Bits 20:18
+    U32 BankMask3                               :  3;  // Bits 23:21
+    U32                                         :  8;  // Bits 31:24
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH0_CR_ODLAT_CMD_BANK_STRUCT;
+
+typedef union {
+  struct {
+    U32 InputMatch                              :  4;  // Bits 3:0
+    U32 InputInvert                             :  4;  // Bits 7:4
+    U32 CountMatches                            :  1;  // Bits 8:8
+    U32 CounterThreshold                        :  15;  // Bits 23:9
+    U32 CounterAction                           :  2;  // Bits 25:24
+    U32 CounterNextState                        :  2;  // Bits 27:26
+    U32 MatchAction                             :  2;  // Bits 29:28
+    U32 MatchNextState                          :  2;  // Bits 31:30
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL0_STRUCT;
+
+typedef union {
+  struct {
+    U32 InputMatch                              :  4;  // Bits 3:0
+    U32 InputInvert                             :  4;  // Bits 7:4
+    U32 CountMatches                            :  1;  // Bits 8:8
+    U32 CounterThreshold                        :  15;  // Bits 23:9
+    U32 CounterAction                           :  2;  // Bits 25:24
+    U32 CounterNextState                        :  2;  // Bits 27:26
+    U32 MatchAction                             :  2;  // Bits 29:28
+    U32 MatchNextState                          :  2;  // Bits 31:30
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL1_STRUCT;
+
+typedef union {
+  struct {
+    U32 InputMatch                              :  4;  // Bits 3:0
+    U32 InputInvert                             :  4;  // Bits 7:4
+    U32 CountMatches                            :  1;  // Bits 8:8
+    U32 CounterThreshold                        :  15;  // Bits 23:9
+    U32 CounterAction                           :  2;  // Bits 25:24
+    U32 CounterNextState                        :  2;  // Bits 27:26
+    U32 MatchAction                             :  2;  // Bits 29:28
+    U32 MatchNextState                          :  2;  // Bits 31:30
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL2_STRUCT;
+
+typedef union {
+  struct {
+    U32 InputMatch                              :  4;  // Bits 3:0
+    U32 InputInvert                             :  4;  // Bits 7:4
+    U32 CountMatches                            :  1;  // Bits 8:8
+    U32 CounterThreshold                        :  15;  // Bits 23:9
+    U32 CounterAction                           :  2;  // Bits 25:24
+    U32 CounterNextState                        :  2;  // Bits 27:26
+    U32 MatchAction                             :  2;  // Bits 29:28
+    U32 MatchNextState                          :  2;  // Bits 31:30
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL3_STRUCT;
+
+typedef union {
+  struct {
+    U32 TriggerBlockEnable                      :  1;  // Bits 0:0
+    U32 GlobalCounterThreshold                  :  16;  // Bits 16:1
+    U32                                         :  15;  // Bits 31:17
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH0_CR_ODLAT_SEQ_GLOBAL_STRUCT;
+
+typedef union {
+  struct {
+    U32 WMM_Enter                               :  8;  // Bits 7:0
+    U32 WMM_Exit                                :  8;  // Bits 15:8
+    U32 WPQ_IS                                  :  8;  // Bits 23:16
+    U32 Starve_count                            :  8;  // Bits 31:24
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH0_CR_SC_WDBWM_STRUCT;
+
+typedef union {
+  struct {
+    U32 Data                                    :  18;  // Bits 17:0
+    U32                                         :  13;  // Bits 30:18
+    U32 VORANGE                                 :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH0_CR_VISA_CTL_MCMNTS_STRUCT;
+
+typedef union {
+  struct {
+    U32 tRCD                                    :  5;  // Bits 4:0
+    U32 tRP                                     :  5;  // Bits 9:5
+    U32 tRAS                                    :  6;  // Bits 15:10
+    U32 tRDPRE                                  :  4;  // Bits 19:16
+    U32 tWRPRE                                  :  6;  // Bits 25:20
+    U32 tRRD                                    :  4;  // Bits 29:26
+    U32 tRPab_ext                               :  2;  // Bits 31:30
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH1_CR_TC_BANK_STRUCT;
+
+typedef union {
+  struct {
+    U32 tCKE                                    :  4;  // Bits 3:0
+    U32 tFAW                                    :  8;  // Bits 11:4
+    U32 tRDRD                                   :  3;  // Bits 14:12
+    U32 tRDRD_dr                                :  4;  // Bits 18:15
+    U32 tRDRD_dd                                :  4;  // Bits 22:19
+    U32 tRDPDEN                                 :  5;  // Bits 27:23
+    U32                                         :  1;  // Bits 28:28
+    U32 CMD_3st                                 :  1;  // Bits 29:29
+    U32 CMD_stretch                             :  2;  // Bits 31:30
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH1_CR_TC_BANK_RANK_A_STRUCT;
+
+typedef union {
+  struct {
+    U32 tWRRD                                   :  6;  // Bits 5:0
+    U32 tWRRD_dr                                :  4;  // Bits 9:6
+    U32 tWRRD_dd                                :  4;  // Bits 13:10
+    U32 tWRWR                                   :  3;  // Bits 16:14
+    U32 tWRWR_dr                                :  4;  // Bits 20:17
+    U32 tWRWR_dd                                :  4;  // Bits 24:21
+    U32 tWRPDEN                                 :  6;  // Bits 30:25
+    U32 Dec_WRD                                 :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH1_CR_TC_BANK_RANK_B_STRUCT;
+
+typedef union {
+  struct {
+    U32 tXPDLL                                  :  6;  // Bits 5:0
+    U32 tXP                                     :  4;  // Bits 9:6
+    U32 TAONPD                                  :  4;  // Bits 13:10
+    U32 tRDWR                                   :  5;  // Bits 18:14
+    U32 tRDWR_dr                                :  5;  // Bits 23:19
+    U32 tRDWR_dd                                :  5;  // Bits 28:24
+    U32                                         :  3;  // Bits 31:29
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH1_CR_TC_BANK_RANK_C_STRUCT;
+
+typedef union {
+  struct {
+    U32 enable_cmd_rate_limit                   :  1;  // Bits 0:0
+    U32 cmd_rate_limit                          :  3;  // Bits 3:1
+    U32 reset_on_command                        :  4;  // Bits 7:4
+    U32 reset_delay                             :  4;  // Bits 11:8
+    U32 ck_to_cke_delay                         :  2;  // Bits 13:12
+    U32 spare                                   :  17;  // Bits 30:14
+    U32 init_mrw_2n_cs                          :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH1_CR_CMD_RATE_STRUCT;
+
+typedef union {
+  struct {
+    U32 tCL                                     :  5;  // Bits 4:0
+    U32 tWCL                                    :  5;  // Bits 9:5
+    U32 tCPDED                                  :  2;  // Bits 11:10
+    U32 tPRPDEN                                 :  2;  // Bits 13:12
+    U32 Odt_Read_Delay                          :  3;  // Bits 16:14
+    U32 Odt_Read_Duration                       :  2;  // Bits 18:17
+    U32 Odt_Write_Duration                      :  2;  // Bits 20:19
+    U32                                         :  11;  // Bits 31:21
+  } Bits;
+#ifdef ULT_FLAG
+  struct {
+    U32 tCL                                     :  5;  // Bits 4:0
+    U32 tWCL                                    :  5;  // Bits 9:5
+    U32 tCPDED                                  :  2;  // Bits 11:10
+    U32 tPRPDEN                                 :  2;  // Bits 13:12
+    U32 Odt_Read_Delay                          :  3;  // Bits 16:14
+    U32 Odt_Read_Duration                       :  2;  // Bits 18:17
+    U32 Odt_Write_Duration                      :  3;  // Bits 21:19
+    U32 Odt_Write_Delay                         :  3;  // Bits 24:22
+    U32 Odt_Always_Rank0                        :  1;  // Bits 25:25
+    U32 cmd_delay                               :  2;  // Bits 27:26
+    U32                                         :  4;  // Bits 31:28
+  } UltBits;
+#endif // ULT_FLAG
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH1_CR_TC_BANK_RANK_D_STRUCT;
+
+typedef union {
+  struct {
+    U32 dis_opp_cas                             :  1;  // Bits 0:0
+    U32 dis_opp_is_cas                          :  1;  // Bits 1:1
+    U32 dis_opp_ras                             :  1;  // Bits 2:2
+    U32 dis_opp_is_ras                          :  1;  // Bits 3:3
+    U32 dis_1c_byp                              :  1;  // Bits 4:4
+    U32 dis_2c_byp                              :  1;  // Bits 5:5
+    U32 dis_deprd_opt                           :  1;  // Bits 6:6
+    U32 dis_pt_it                               :  1;  // Bits 7:7
+    U32 dis_prcnt_ring                          :  1;  // Bits 8:8
+    U32 dis_prcnt_sa                            :  1;  // Bits 9:9
+    U32 dis_blkr_ph                             :  1;  // Bits 10:10
+    U32 dis_blkr_pe                             :  1;  // Bits 11:11
+    U32 dis_blkr_pm                             :  1;  // Bits 12:12
+    U32 dis_odt                                 :  1;  // Bits 13:13
+    U32 OE_alw_off                              :  1;  // Bits 14:14
+    U32                                         :  1;  // Bits 15:15
+    U32 dis_aom                                 :  1;  // Bits 16:16
+    U32 block_rpq                               :  1;  // Bits 17:17
+    U32 block_wpq                               :  1;  // Bits 18:18
+    U32 invert_align                            :  1;  // Bits 19:19
+    U32 dis_write_gap                           :  1;  // Bits 20:20
+    U32 dis_zq                                  :  1;  // Bits 21:21
+    U32 dis_tt                                  :  1;  // Bits 22:22
+    U32 dis_opp_ref                             :  1;  // Bits 23:23
+    U32 Long_ZQ                                 :  1;  // Bits 24:24
+    U32 dis_srx_zq                              :  1;  // Bits 25:25
+    U32 Serialize_ZQ                            :  1;  // Bits 26:26
+    U32 ZQ_fast_exec                            :  1;  // Bits 27:27
+    U32 Dis_DriveNop                            :  1;  // Bits 28:28
+    U32 Pres_WDB_Ent                            :  1;  // Bits 29:29
+    U32 dis_clk_gate                            :  1;  // Bits 30:30
+    U32                                         :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH1_CR_SCHED_CBIT_STRUCT;
+
+typedef union {
+  struct {
+    U32 Lat_R0D0                                :  6;  // Bits 5:0
+    U32                                         :  2;  // Bits 7:6
+    U32 Lat_R1D0                                :  6;  // Bits 13:8
+    U32                                         :  2;  // Bits 15:14
+    U32 Lat_R0D1                                :  6;  // Bits 21:16
+    U32                                         :  2;  // Bits 23:22
+    U32 Lat_R1D1                                :  6;  // Bits 29:24
+    U32                                         :  2;  // Bits 31:30
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH1_CR_SC_ROUNDT_LAT_STRUCT;
+
+typedef union {
+  struct {
+    U32 IOLAT_R0D0                              :  4;  // Bits 3:0
+    U32 IOLAT_R1D0                              :  4;  // Bits 7:4
+    U32 IOLAT_R0D1                              :  4;  // Bits 11:8
+    U32 IOLAT_R1D1                              :  4;  // Bits 15:12
+    U32 RT_IOCOMP                               :  6;  // Bits 21:16
+    U32                                         :  8;  // Bits 29:22
+    U32 three_channels                          :  1;  // Bits 30:30
+    U32 DIS_RT_CLK_GATE                         :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH1_CR_SC_IO_LATENCY_STRUCT;
+
+typedef union {
+  struct {
+    U32 DATA                                    :  32;  // Bits 31:0
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH1_CR_ROUND_TRIP_DFT_DATA_STRUCT;
+
+typedef union {
+  struct {
+    U32 WDAR                                    :  1;  // Bits 0:0
+    U32 safe_mask_sel                           :  3;  // Bits 3:1
+    U32 force_rcv_en                            :  1;  // Bits 4:4
+    U32                                         :  3;  // Bits 7:5
+    U32 DDR_QUAL                                :  2;  // Bits 9:8
+    U32 Qual_length                             :  2;  // Bits 11:10
+    U32 WDB_Block_En                            :  1;  // Bits 12:12
+    U32 RT_DFT_READ_PTR                         :  4;  // Bits 16:13
+    U32 RT_DFT_READ_ENABLE                      :  1;  // Bits 17:17
+    U32 RT_DFT_READ_SEL_ADDR                    :  1;  // Bits 18:18
+    U32                                         :  13;  // Bits 31:19
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH1_CR_DFT_MISC_STRUCT;
+
+typedef union {
+  struct {
+    U32 ECC                                     :  8;  // Bits 7:0
+    U32 RRD_DFT_Mode                            :  2;  // Bits 9:8
+    U32 LFSR_Seed_Index                         :  5;  // Bits 14:10
+    U32 Inversion_Mode                          :  1;  // Bits 15:15
+    U32                                         :  16;  // Bits 31:16
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH1_CR_READ_RETURN_DFT_STRUCT;
+
+typedef union {
+  struct {
+    U32 dis_imph_error                          :  1;  // Bits 0:0
+    U32                                         :  7;  // Bits 7:1
+    U32 dis_async_odt                           :  1;  // Bits 8:8
+    U32                                         :  23;  // Bits 31:9
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH1_CR_SCHED_SECOND_CBIT_STRUCT;
+
+typedef union {
+  struct {
+    U32 Mux0_Control                            :  2;  // Bits 1:0
+    U32                                         :  1;  // Bits 2:2
+    U32 Mux1_Control                            :  2;  // Bits 4:3
+    U32                                         :  1;  // Bits 5:5
+    U32 Mux2_Control                            :  2;  // Bits 7:6
+    U32                                         :  6;  // Bits 13:8
+    U32 ECC_Replace_Byte_Control                :  1;  // Bits 14:14
+    U32 ECC_Data_Source_Sel                     :  1;  // Bits 15:15
+    U32 Save_LFSR_Seed_Rate                     :  6;  // Bits 21:16
+    U32                                         :  2;  // Bits 23:22
+    U32 Reload_LFSR_Seed_Rate                   :  3;  // Bits 26:24
+    U32                                         :  5;  // Bits 31:27
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_STRUCT;
+
+typedef union {
+  struct {
+    U32 WDB_Current_Read_Pointer                :  6;  // Bits 5:0
+    U32                                         :  26;  // Bits 31:6
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_RD_STATUS_STRUCT;
+
+typedef union {
+  struct {
+    U32 Pattern_Buffer                          :  24;  // Bits 23:0
+    U32                                         :  8;  // Bits 31:24
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_0_STRUCT;
+
+typedef union {
+  struct {
+    U32 Pattern_Buffer                          :  24;  // Bits 23:0
+    U32                                         :  8;  // Bits 31:24
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_1_STRUCT;
+
+typedef union {
+  struct {
+    U32 Pattern_Buffer                          :  24;  // Bits 23:0
+    U32                                         :  8;  // Bits 31:24
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_2_STRUCT;
+
+typedef union {
+  struct {
+    U32 Pattern_Buffer                          :  24;  // Bits 23:0
+    U32                                         :  8;  // Bits 31:24
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_0_STRUCT;
+
+typedef union {
+  struct {
+    U32 Pattern_Buffer                          :  24;  // Bits 23:0
+    U32                                         :  8;  // Bits 31:24
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_1_STRUCT;
+
+typedef union {
+  struct {
+    U32 Pattern_Buffer                          :  24;  // Bits 23:0
+    U32                                         :  8;  // Bits 31:24
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_2_STRUCT;
+
+typedef union {
+  struct {
+    U32 Pattern_Buffer                          :  24;  // Bits 23:0
+    U32                                         :  8;  // Bits 31:24
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_0_STRUCT;
+
+typedef union {
+  struct {
+    U32 Pattern_Buffer                          :  24;  // Bits 23:0
+    U32                                         :  8;  // Bits 31:24
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_1_STRUCT;
+
+typedef union {
+  struct {
+    U32 Pattern_Buffer                          :  24;  // Bits 23:0
+    U32                                         :  8;  // Bits 31:24
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_2_STRUCT;
+
+typedef union {
+  struct {
+    U32 Pattern_Buffer                          :  24;  // Bits 23:0
+    U32                                         :  8;  // Bits 31:24
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_0_STRUCT;
+
+typedef union {
+  struct {
+    U32 Pattern_Buffer                          :  24;  // Bits 23:0
+    U32                                         :  8;  // Bits 31:24
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_1_STRUCT;
+
+typedef union {
+  struct {
+    U32 Pattern_Buffer                          :  24;  // Bits 23:0
+    U32                                         :  8;  // Bits 31:24
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_2_STRUCT;
+
+typedef union {
+  struct {
+    U32 L_data_select                           :  1;  // Bits 0:0
+    U32 Enable_Sweep_Frequency                  :  1;  // Bits 1:1
+    U32                                         :  6;  // Bits 7:2
+    U32 L_counter                               :  8;  // Bits 15:8
+    U32 M_counter                               :  8;  // Bits 23:16
+    U32 N_counter                               :  8;  // Bits 31:24
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_STRUCT;
+
+typedef union {
+  struct {
+    U32 ECC_Inv_or_DC_Enable                    :  8;  // Bits 7:0
+    U32                                         :  8;  // Bits 15:8
+    U32 Inv_or_DC_Shift_Rate                    :  4;  // Bits 19:16
+    U32 DC_Polarity_Control                     :  1;  // Bits 20:20
+    U32                                         :  9;  // Bits 29:21
+    U32 Inv_or_DC_Control                       :  1;  // Bits 30:30
+    U32 Inv_or_DC_Shift_Enable                  :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH1_CR_REUT_CH_PAT_WDB_INV_STRUCT;
+
+typedef union {
+  struct {
+    U64 Data_Inv_or_DC_Enable                   :  64;  // Bits 63:0
+  } Bits;
+  U64 Data;
+  U32 Data32[2];
+  U16 Data16[4];
+  U8  Data8[8];
+} MCHBAR_CH1_CR_REUT_CH_PAT_WDB_DATA_INV_STRUCT;
+
+typedef union {
+  struct {
+    U32 Stop_on_Nth_Error                       :  6;  // Bits 5:0
+    U32                                         :  6;  // Bits 11:6
+    U32 Stop_On_Error_Control                   :  2;  // Bits 13:12
+    U32                                         :  2;  // Bits 15:14
+    U32 Selective_Error_Enable_Chunk            :  8;  // Bits 23:16
+    U32 Selective_Error_Enable_Cacheline        :  8;  // Bits 31:24
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH1_CR_REUT_CH_ERR_CTL_STRUCT;
+
+typedef union {
+  struct {
+    U32 ECC_Error_Mask                          :  8;  // Bits 7:0
+    U32                                         :  24;  // Bits 31:8
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH1_CR_REUT_CH_ERR_ECC_MASK_STRUCT;
+
+typedef union {
+  struct {
+    U32 Stretch_mode                            :  2;  // Bits 1:0
+    U32                                         :  2;  // Bits 3:2
+    U32 STF                                     :  3;  // Bits 6:4
+    U32                                         :  25;  // Bits 31:7
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH1_CR_STM_CONFIG_STRUCT;
+
+typedef union {
+  struct {
+    U32 Priority_count_ring                     :  10;  // Bits 9:0
+    U32                                         :  6;  // Bits 15:10
+    U32 Priority_count_SA                       :  10;  // Bits 25:16
+    U32                                         :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH1_CR_SC_PR_CNT_CONFIG_STRUCT;
+
+typedef union {
+  struct {
+    U32 PCIT                                    :  8;  // Bits 7:0
+    U32                                         :  24;  // Bits 31:8
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH1_CR_SC_PCIT_STRUCT;
+
+typedef union {
+  struct {
+    U32 PDWN_idle_counter                       :  12;  // Bits 11:0
+    U32 PDWN_mode                               :  4;  // Bits 15:12
+    U32                                         :  16;  // Bits 31:16
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH1_CR_PM_PDWN_CONFIG_STRUCT;
+
+typedef union {
+  struct {
+    U32 Count                                   :  32;  // Bits 31:0
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH1_CR_ECC_INJECT_COUNT_STRUCT;
+
+typedef union {
+  struct {
+    U32 ECC4ANA_fill                            :  8;  // Bits 7:0
+    U32 ECC4ANA_trigger                         :  2;  // Bits 9:8
+    U32 ECC4ANA_BS                              :  1;  // Bits 10:10
+    U32 ECC_Inject                              :  3;  // Bits 13:11
+    U32 ECC_correction_disable                  :  1;  // Bits 14:14
+    U32 ECC4ANA_Inject                          :  1;  // Bits 15:15
+    U32 DIS_MCA_LOG                             :  1;  // Bits 16:16
+    U32 DIS_PCH_EVENT                           :  1;  // Bits 17:17
+    U32 DIS_PCIE_POISON                         :  1;  // Bits 18:18
+    U32                                         :  13;  // Bits 31:19
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH1_CR_ECC_DFT_STRUCT;
+
+typedef union {
+  struct {
+    U32 Data                                    :  18;  // Bits 17:0
+    U32                                         :  13;  // Bits 30:18
+    U32 VORANGE                                 :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH1_CR_VISA_CTL_MCSCHEDS_STRUCT;
+
+typedef union {
+  struct {
+    U32 Data                                    :  32;  // Bits 31:0
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH1_CR_VISA_XBAR_MCSCHEDS_STRUCT;
+
+typedef union {
+  struct {
+    U32 CERRSTS                                 :  1;  // Bits 0:0
+    U32 MERRSTS                                 :  1;  // Bits 1:1
+    U32                                         :  14;  // Bits 15:2
+    U32 ERRSYND                                 :  8;  // Bits 23:16
+    U32 ERRCHUNK                                :  3;  // Bits 26:24
+    U32 ERRRANK                                 :  2;  // Bits 28:27
+    U32 ERRBANK                                 :  3;  // Bits 31:29
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH1_CR_ECCERRLOG0_STRUCT;
+
+typedef union {
+  struct {
+    U32 ERRROW                                  :  16;  // Bits 15:0
+    U32 ERRCOL                                  :  16;  // Bits 31:16
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH1_CR_ECCERRLOG1_STRUCT;
+
+typedef union {
+  struct {
+    U32 D0R0                                    :  2;  // Bits 1:0
+    U32 D0R1                                    :  2;  // Bits 3:2
+    U32 D1R0                                    :  2;  // Bits 5:4
+    U32 D1R1                                    :  2;  // Bits 7:6
+    U32                                         :  24;  // Bits 31:8
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH1_CR_SC_WR_ADD_DELAY_STRUCT;
+
+typedef union {
+  struct {
+    U32 Dis_Opp_rd                              :  1;  // Bits 0:0
+    U32 ACT_Enable                              :  1;  // Bits 1:1
+    U32 PRE_Enable                              :  1;  // Bits 2:2
+    U32 MAX_RPQ_Cas                             :  4;  // Bits 6:3
+    U32                                         :  25;  // Bits 31:7
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH1_CR_WMM_READ_CONFIG_STRUCT;
+
+typedef union {
+  struct {
+    U64 Data_Error_Mask                         :  64;  // Bits 63:0
+  } Bits;
+  U64 Data;
+  U32 Data32[2];
+  U16 Data16[4];
+  U8  Data8[8];
+} MCHBAR_CH1_CR_REUT_CH_ERR_DATA_MASK_STRUCT;
+
+typedef union {
+  struct {
+    U64 Data_Error_Status                       :  64;  // Bits 63:0
+  } Bits;
+  U64 Data;
+  U32 Data32[2];
+  U16 Data16[4];
+  U8  Data8[8];
+} MCHBAR_CH1_CR_REUT_CH_ERR_DATA_STATUS_STRUCT;
+
+typedef union {
+  struct {
+    U32 ECC_Error_Status                        :  8;  // Bits 7:0
+    U32 Chunk_Error_Status                      :  8;  // Bits 15:8
+    U32 Rank_Error_Status                       :  4;  // Bits 19:16
+    U32                                         :  12;  // Bits 31:20
+    U32 Byte_Group_Error_Status                 :  9;  // Bits 40:32
+    U32                                         :  11;  // Bits 51:41
+    U32 WDB_Rd_Chunk_Num_Status                 :  3;  // Bits 54:52
+    U32                                         :  1;  // Bits 55:55
+    U32 Nth_Error                               :  6;  // Bits 61:56
+    U32                                         :  2;  // Bits 63:62
+  } Bits;
+  U64 Data;
+  U32 Data32[2];
+  U16 Data16[4];
+  U8  Data8[8];
+} MCHBAR_CH1_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_STRUCT;
+
+typedef union {
+  struct {
+    U32 Counter_Pointer                         :  7;  // Bits 6:0
+    U32 Counter_Control                         :  2;  // Bits 8:7
+    U32                                         :  23;  // Bits 31:9
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_0_STRUCT;
+
+typedef union {
+  struct {
+    U32 Counter_Pointer                         :  7;  // Bits 6:0
+    U32 Counter_Control                         :  2;  // Bits 8:7
+    U32                                         :  23;  // Bits 31:9
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_1_STRUCT;
+
+typedef union {
+  struct {
+    U32 Counter_Pointer                         :  7;  // Bits 6:0
+    U32 Counter_Control                         :  2;  // Bits 8:7
+    U32                                         :  23;  // Bits 31:9
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_2_STRUCT;
+
+typedef union {
+  struct {
+    U32 Counter_Pointer                         :  7;  // Bits 6:0
+    U32 Counter_Control                         :  2;  // Bits 8:7
+    U32                                         :  23;  // Bits 31:9
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_3_STRUCT;
+
+typedef union {
+  struct {
+    U32 Counter_Pointer                         :  7;  // Bits 6:0
+    U32 Counter_Control                         :  2;  // Bits 8:7
+    U32                                         :  23;  // Bits 31:9
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_4_STRUCT;
+
+typedef union {
+  struct {
+    U32 Counter_Pointer                         :  7;  // Bits 6:0
+    U32 Counter_Control                         :  2;  // Bits 8:7
+    U32                                         :  23;  // Bits 31:9
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_5_STRUCT;
+
+typedef union {
+  struct {
+    U32 Counter_Pointer                         :  7;  // Bits 6:0
+    U32 Counter_Control                         :  2;  // Bits 8:7
+    U32                                         :  23;  // Bits 31:9
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_6_STRUCT;
+
+typedef union {
+  struct {
+    U32 Counter_Pointer                         :  7;  // Bits 6:0
+    U32 Counter_Control                         :  2;  // Bits 8:7
+    U32                                         :  23;  // Bits 31:9
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_7_STRUCT;
+
+typedef union {
+  struct {
+    U32 Counter_Pointer                         :  7;  // Bits 6:0
+    U32 Counter_Control                         :  2;  // Bits 8:7
+    U32                                         :  23;  // Bits 31:9
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_8_STRUCT;
+
+typedef union {
+  struct {
+    U32 Counter_Status                          :  23;  // Bits 22:0
+    U32                                         :  9;  // Bits 31:23
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_0_STRUCT;
+
+typedef union {
+  struct {
+    U32 Counter_Status                          :  23;  // Bits 22:0
+    U32                                         :  9;  // Bits 31:23
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_1_STRUCT;
+
+typedef union {
+  struct {
+    U32 Counter_Status                          :  23;  // Bits 22:0
+    U32                                         :  9;  // Bits 31:23
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_2_STRUCT;
+
+typedef union {
+  struct {
+    U32 Counter_Status                          :  23;  // Bits 22:0
+    U32                                         :  9;  // Bits 31:23
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_3_STRUCT;
+
+typedef union {
+  struct {
+    U32 Counter_Status                          :  23;  // Bits 22:0
+    U32                                         :  9;  // Bits 31:23
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_4_STRUCT;
+
+typedef union {
+  struct {
+    U32 Counter_Status                          :  23;  // Bits 22:0
+    U32                                         :  9;  // Bits 31:23
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_5_STRUCT;
+
+typedef union {
+  struct {
+    U32 Counter_Status                          :  23;  // Bits 22:0
+    U32                                         :  9;  // Bits 31:23
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_6_STRUCT;
+
+typedef union {
+  struct {
+    U32 Counter_Status                          :  23;  // Bits 22:0
+    U32                                         :  9;  // Bits 31:23
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_7_STRUCT;
+
+typedef union {
+  struct {
+    U32 Counter_Status                          :  23;  // Bits 22:0
+    U32                                         :  9;  // Bits 31:23
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_8_STRUCT;
+
+typedef union {
+  struct {
+    U32 Counter_Overflow_Status                 :  9;  // Bits 8:0
+    U32                                         :  23;  // Bits 31:9
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_OVERFLOW_STATUS_STRUCT;
+
+typedef union {
+  struct {
+    U32 Column_Address                          :  10;  // Bits 9:0
+    U32                                         :  14;  // Bits 23:10
+    U32 Row_Address                             :  16;  // Bits 39:24
+    U32                                         :  8;  // Bits 47:40
+    U32 Bank_Address                            :  3;  // Bits 50:48
+    U32                                         :  5;  // Bits 55:51
+    U32 Rank_Address                            :  2;  // Bits 57:56
+    U32                                         :  6;  // Bits 63:58
+  } Bits;
+  U64 Data;
+  U32 Data32[2];
+  U16 Data16[4];
+  U8  Data8[8];
+} MCHBAR_CH1_CR_REUT_CH_ERROR_ADDR_STRUCT;
+
+typedef union {
+  struct {
+    U32 WDB_Current_Error_Pointer               :  6;  // Bits 5:0
+    U32                                         :  26;  // Bits 31:6
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH1_CR_REUT_CH_ERR_WDB_CAPTURE_STATUS_STRUCT;
+
+typedef union {
+  struct {
+    U32 Enable_WDB_Error_Capture                :  1;  // Bits 0:0
+    U32                                         :  7;  // Bits 7:1
+    U32 WDB_Starting_Error_Pointer              :  6;  // Bits 13:8
+    U32                                         :  2;  // Bits 15:14
+    U32 WDB_Ending_Error_Pointer                :  6;  // Bits 21:16
+    U32                                         :  10;  // Bits 31:22
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH1_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_STRUCT;
+
+typedef union {
+  struct {
+    U32 CKE_Override                            :  4;  // Bits 3:0
+    U32                                         :  4;  // Bits 7:4
+    U32 CKE_En_Start_Test_Sync                  :  1;  // Bits 8:8
+    U32                                         :  7;  // Bits 15:9
+    U32 CKE_On                                  :  4;  // Bits 19:16
+    U32                                         :  12;  // Bits 31:20
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH1_CR_REUT_CH_MISC_CKE_CTRL_STRUCT;
+
+typedef union {
+  struct {
+    U32 ODT_Override                            :  4;  // Bits 3:0
+    U32                                         :  12;  // Bits 15:4
+    U32 ODT_On                                  :  4;  // Bits 19:16
+    U32                                         :  11;  // Bits 30:20
+    U32 MPR_Train_DDR_On                        :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH1_CR_REUT_CH_MISC_ODT_CTRL_STRUCT;
+
+typedef union {
+  struct {
+    U32 Enable_CADB_on_Deselect                 :  1;  // Bits 0:0
+    U32 Enable_CADB_Always_On                   :  1;  // Bits 1:1
+    U32 CMD_Deselect_Start                      :  4;  // Bits 5:2
+    U32 CMD_Deselect_Stop                       :  4;  // Bits 9:6
+    U32 Lane_Deselect_Enable                    :  4;  // Bits 13:10
+    U32 CAS_Select_Enable                       :  2;  // Bits 15:14
+    U32 ACT_Select_Enable                       :  2;  // Bits 17:16
+    U32 PRE_Select_Enable                       :  2;  // Bits 19:18
+    U32 Save_Current_Seed                       :  4;  // Bits 23:20
+    U32 Reload_Starting_Seed                    :  4;  // Bits 27:24
+    U32                                         :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_STRUCT;
+
+typedef union {
+  struct {
+    U32 MRS_Gap                                 :  3;  // Bits 2:0
+    U32                                         :  5;  // Bits 7:3
+    U32 CADB_MRS_Start_Pointer                  :  3;  // Bits 10:8
+    U32                                         :  5;  // Bits 15:11
+    U32 CADB_MRS_End_Pointer                    :  3;  // Bits 18:16
+    U32                                         :  5;  // Bits 23:19
+    U32 CADB_MRS_Current_Pointer                :  3;  // Bits 26:24
+    U32                                         :  5;  // Bits 31:27
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MRS_STRUCT;
+
+typedef union {
+  struct {
+    U32 Mux0_Control                            :  2;  // Bits 1:0
+    U32                                         :  2;  // Bits 3:2
+    U32 Mux1_Control                            :  2;  // Bits 5:4
+    U32                                         :  2;  // Bits 7:6
+    U32 Mux2_Control                            :  2;  // Bits 9:8
+    U32                                         :  6;  // Bits 15:10
+    U32 Select_Mux0_Control                     :  2;  // Bits 17:16
+    U32                                         :  2;  // Bits 19:18
+    U32 Select_Mux1_Control                     :  2;  // Bits 21:20
+    U32                                         :  2;  // Bits 23:22
+    U32 Select_Mux2_Control                     :  2;  // Bits 25:24
+    U32                                         :  6;  // Bits 31:26
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_CTRL_STRUCT;
+
+typedef union {
+  struct {
+    U32 Pattern_Buffer                          :  16;  // Bits 15:0
+    U32                                         :  16;  // Bits 31:16
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_PB_0_STRUCT;
+
+typedef union {
+  struct {
+    U32 Pattern_Buffer                          :  16;  // Bits 15:0
+    U32                                         :  16;  // Bits 31:16
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_PB_1_STRUCT;
+
+typedef union {
+  struct {
+    U32 Pattern_Buffer                          :  16;  // Bits 15:0
+    U32                                         :  16;  // Bits 31:16
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_PB_2_STRUCT;
+
+typedef union {
+  struct {
+    U32 L_data_select                           :  1;  // Bits 0:0
+    U32 Enable_Sweep_Frequency                  :  1;  // Bits 1:1
+    U32                                         :  6;  // Bits 7:2
+    U32 L_counter                               :  8;  // Bits 15:8
+    U32 M_counter                               :  8;  // Bits 23:16
+    U32 N_counter                               :  8;  // Bits 31:24
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_STRUCT;
+
+typedef union {
+  struct {
+    U32 CADB_Write_Pointer                      :  3;  // Bits 2:0
+    U32                                         :  29;  // Bits 31:3
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH1_CR_REUT_CH_PAT_CADB_WRITE_POINTER_STRUCT;
+
+typedef union {
+  struct {
+    U32 CADB_Data_Address                       :  16;  // Bits 15:0
+    U32                                         :  8;  // Bits 23:16
+    U32 CADB_Data_Bank                          :  3;  // Bits 26:24
+    U32                                         :  5;  // Bits 31:27
+    U32 CADB_Data_CS                            :  4;  // Bits 35:32
+    U32                                         :  4;  // Bits 39:36
+    U32 CADB_Data_Control                       :  3;  // Bits 42:40
+    U32                                         :  5;  // Bits 47:43
+    U32 CADB_Data_ODT                           :  4;  // Bits 51:48
+    U32                                         :  4;  // Bits 55:52
+    U32 CADB_Data_CKE                           :  4;  // Bits 59:56
+    U32                                         :  4;  // Bits 63:60
+  } Bits;
+  U64 Data;
+  U32 Data32[2];
+  U16 Data16[4];
+  U8  Data8[8];
+} MCHBAR_CH1_CR_REUT_CH_PAT_CADB_PROG_STRUCT;
+
+typedef union {
+  struct {
+    U32 Pattern_Buffer                          :  16;  // Bits 15:0
+    U32                                         :  16;  // Bits 31:16
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH1_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_0_STRUCT;
+
+typedef union {
+  struct {
+    U32 Pattern_Buffer                          :  16;  // Bits 15:0
+    U32                                         :  16;  // Bits 31:16
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH1_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_1_STRUCT;
+
+typedef union {
+  struct {
+    U32 Pattern_Buffer                          :  16;  // Bits 15:0
+    U32                                         :  16;  // Bits 31:16
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH1_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_2_STRUCT;
+
+typedef union {
+  struct {
+    U32 WDB_Increment_Rate                      :  5;  // Bits 4:0
+    U32 WDB_Increment_Scale                     :  1;  // Bits 5:5
+    U32                                         :  2;  // Bits 7:6
+    U32 WDB_Start_Pointer                       :  6;  // Bits 13:8
+    U32                                         :  2;  // Bits 15:14
+    U32 WDB_End_Pointer                         :  6;  // Bits 21:16
+    U32                                         :  10;  // Bits 31:22
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_CTRL_STRUCT;
+
+typedef union {
+  struct {
+    U32 Refresh_Rank_Mask                       :  4;  // Bits 3:0
+    U32                                         :  4;  // Bits 7:4
+    U32 RefZQ_En_Start_Test_Sync                :  1;  // Bits 8:8
+    U32                                         :  22;  // Bits 30:9
+    U32 Panic_Refresh_Only                      :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH1_CR_REUT_CH_MISC_REFRESH_CTRL_STRUCT;
+
+typedef union {
+  struct {
+    U32 ZQ_Rank_Mask                            :  4;  // Bits 3:0
+    U32                                         :  27;  // Bits 30:4
+    U32 Always_Do_ZQ                            :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH1_CR_REUT_CH_MISC_ZQ_CTRL_STRUCT;
+
+#ifdef ULT_FLAG
+typedef union {
+  struct {
+    U32 Rank_0_x32                              :  1;  // Bits 0:0
+    U32 Rank_1_x32                              :  1;  // Bits 1:1
+    U32 Rank_2_x32                              :  1;  // Bits 2:2
+    U32 Rank_3_x32                              :  1;  // Bits 3:3
+    U32 LPDDR2                                  :  1;  // Bits 4:4
+    U32                                         :  3;  // Bits 7:5
+    U32 MR4_PERIOD                              :  16;  // Bits 23:8
+    U32                                         :  8;  // Bits 31:24
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH1_CR_LPDDR_MR_PARAMS_STRUCT;
+
+typedef union {
+  struct {
+    U32 Address                                 :  8;  // Bits 7:0
+    U32 Data                                    :  8;  // Bits 15:8
+    U32 Rank                                    :  2;  // Bits 17:16
+    U32 Write                                   :  1;  // Bits 18:18
+    U32 Init_MRW                                :  1;  // Bits 19:19
+    U32                                         :  11;  // Bits 30:20
+    U32 Busy                                    :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH1_CR_LPDDR_MR_COMMAND_STRUCT;
+
+typedef union {
+  struct {
+    U32 Device_0                                :  8;  // Bits 7:0
+    U32 Device_1                                :  8;  // Bits 15:8
+    U32 Device_2                                :  8;  // Bits 23:16
+    U32 Device_3                                :  8;  // Bits 31:24
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH1_CR_LPDDR_MR_RESULT_STRUCT;
+
+typedef union {
+  struct {
+    U32 Rank_0                                  :  3;  // Bits 2:0
+    U32                                         :  5;  // Bits 7:3
+    U32 Rank_1                                  :  3;  // Bits 10:8
+    U32                                         :  5;  // Bits 15:11
+    U32 Rank_2                                  :  3;  // Bits 18:16
+    U32                                         :  5;  // Bits 23:19
+    U32 Rank_3                                  :  3;  // Bits 26:24
+    U32                                         :  5;  // Bits 31:27
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH1_CR_LPDDR_MR4_RANK_TEMPERATURE_STRUCT;
+
+typedef union {
+  struct {
+    U32 Bit_0                                   :  3;  // Bits 2:0
+    U32                                         :  1;  // Bits 3:3
+    U32 Bit_1                                   :  3;  // Bits 6:4
+    U32                                         :  1;  // Bits 7:7
+    U32 Bit_2                                   :  3;  // Bits 10:8
+    U32                                         :  1;  // Bits 11:11
+    U32 Bit_16                                  :  3;  // Bits 14:12
+    U32                                         :  1;  // Bits 15:15
+    U32 Bit_17                                  :  3;  // Bits 18:16
+    U32                                         :  1;  // Bits 19:19
+    U32 Bit_18                                  :  3;  // Bits 22:20
+    U32                                         :  1;  // Bits 23:23
+    U32 Byte_0                                  :  3;  // Bits 26:24
+    U32                                         :  1;  // Bits 27:27
+    U32 Byte_2                                  :  3;  // Bits 30:28
+    U32                                         :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH1_CR_DESWIZZLE_LOW_STRUCT;
+
+typedef union {
+  struct {
+    U32 Bit_32                                  :  3;  // Bits 2:0
+    U32                                         :  1;  // Bits 3:3
+    U32 Bit_33                                  :  3;  // Bits 6:4
+    U32                                         :  1;  // Bits 7:7
+    U32 Bit_34                                  :  3;  // Bits 10:8
+    U32                                         :  1;  // Bits 11:11
+    U32 Bit_48                                  :  3;  // Bits 14:12
+    U32                                         :  1;  // Bits 15:15
+    U32 Bit_49                                  :  3;  // Bits 18:16
+    U32                                         :  1;  // Bits 19:19
+    U32 Bit_50                                  :  3;  // Bits 22:20
+    U32                                         :  1;  // Bits 23:23
+    U32 Byte_4                                  :  3;  // Bits 26:24
+    U32                                         :  1;  // Bits 27:27
+    U32 Byte_6                                  :  3;  // Bits 30:28
+    U32                                         :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH1_CR_DESWIZZLE_HIGH_STRUCT;
+#endif // ULT_FLAG
+
+typedef union {
+  struct {
+    U32 Ref_Interval                            :  11;  // Bits 10:0
+    U32 Ref_Stagger_En                          :  1;  // Bits 11:11
+    U32 Ref_Stagger_Mode                        :  1;  // Bits 12:12
+    U32 Disable_Stolen_Refresh                  :  1;  // Bits 13:13
+    U32 En_Ref_Type_Display                     :  1;  // Bits 14:14
+    U32                                         :  17;  // Bits 31:15
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH1_CR_MC_REFRESH_STAGGER_STRUCT;
+
+typedef union {
+  struct {
+    U32 ZQCS_period                             :  8;  // Bits 7:0
+    U32 tZQCS                                   :  8;  // Bits 15:8
+    U32                                         :  16;  // Bits 31:16
+  } Bits;
+#ifdef ULT_FLAG
+  struct {
+    U32 ZQCS_period                             :  10;  // Bits 9:0
+    U32 tZQCS                                   :  10;  // Bits 19:10
+    U32                                         :  12;  // Bits 31:20
+  } UltBits;
+#endif //ULT_FLAG
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH1_CR_TC_ZQCAL_STRUCT;
+
+typedef union {
+  struct {
+    U32 OREF_RI                                 :  8;  // Bits 7:0
+    U32 Refresh_HP_WM                           :  4;  // Bits 11:8
+    U32 Refresh_panic_wm                        :  4;  // Bits 15:12
+    U32                                         :  16;  // Bits 31:16
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH1_CR_TC_RFP_STRUCT;
+
+typedef union {
+  struct {
+    U32 tREFI                                   :  16;  // Bits 15:0
+    U32 tRFC                                    :  9;  // Bits 24:16
+    U32 tREFIx9                                 :  7;  // Bits 31:25
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH1_CR_TC_RFTP_STRUCT;
+
+typedef union {
+  struct {
+    U32 MR2_sh_low                              :  6;  // Bits 5:0
+    U32 SRT_avail                               :  2;  // Bits 7:6
+    U32 MR2_sh_high                             :  3;  // Bits 10:8
+    U32                                         :  3;  // Bits 13:11
+    U32 Addr_bit_swizzle                        :  2;  // Bits 15:14
+    U32                                         :  16;  // Bits 31:16
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH1_CR_TC_MR2_SHADDOW_STRUCT;
+
+typedef union {
+  struct {
+    U32 Rank_occupancy                          :  4;  // Bits 3:0
+    U32                                         :  28;  // Bits 31:4
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH1_CR_MC_INIT_STATE_STRUCT;
+
+typedef union {
+  struct {
+    U32 tXSDLL                                  :  12;  // Bits 11:0
+    U32 tXS_offset                              :  4;  // Bits 15:12
+    U32 tZQOPER                                 :  10;  // Bits 25:16
+    U32                                         :  2;  // Bits 27:26
+    U32 tMOD                                    :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH1_CR_TC_SRFTP_STRUCT;
+
+typedef union {
+  struct {
+    U32 VISAByteSel                             :  3;  // Bits 2:0
+    U32                                         :  29;  // Bits 31:3
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH1_CR_WDB_VISA_SEL_STRUCT;
+
+typedef union {
+  struct {
+    U32 FASTADDR                                :  12;  // Bits 11:0
+    U32                                         :  4;  // Bits 15:12
+    U32 ADDREN                                  :  1;  // Bits 16:16
+    U32 SEQEN                                   :  1;  // Bits 17:17
+    U32 POL0                                    :  1;  // Bits 18:18
+    U32 POL1                                    :  1;  // Bits 19:19
+    U32 CMDA                                    :  4;  // Bits 23:20
+    U32 CMDB                                    :  4;  // Bits 27:24
+    U32 CMDC                                    :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH1_CR_DCLK_LDAT_PDAT_STRUCT;
+
+typedef union {
+  struct {
+    U32 BANKSEL                                 :  4;  // Bits 3:0
+    U32                                         :  1;  // Bits 4:4
+    U32 ARRAYSEL                                :  5;  // Bits 9:5
+    U32 CMP                                     :  1;  // Bits 10:10
+    U32 REP                                     :  1;  // Bits 11:11
+    U32 DWORD                                   :  4;  // Bits 15:12
+    U32 MODE                                    :  2;  // Bits 17:16
+    U32 MPMAP                                   :  6;  // Bits 23:18
+    U32 MPBOFFSET                               :  4;  // Bits 27:24
+    U32 STAGE_EN                                :  1;  // Bits 28:28
+    U32 SHADOW                                  :  2;  // Bits 30:29
+    U32                                         :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH1_CR_DCLK_LDAT_SDAT_STRUCT;
+
+typedef union {
+  struct {
+    U32 DATOUT                                  :  32;  // Bits 31:0
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH1_CR_DCLK_LDAT_DATAOUT_STRUCT;
+
+typedef union {
+  struct {
+    U32 DATIN                                   :  32;  // Bits 31:0
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH1_CR_DCLK_LDAT_DATAIN_0_STRUCT;
+
+typedef union {
+  struct {
+    U32 FASTADDR                                :  12;  // Bits 11:0
+    U32                                         :  4;  // Bits 15:12
+    U32 ADDREN                                  :  1;  // Bits 16:16
+    U32 SEQEN                                   :  1;  // Bits 17:17
+    U32 POL0                                    :  1;  // Bits 18:18
+    U32 POL1                                    :  1;  // Bits 19:19
+    U32 CMDA                                    :  4;  // Bits 23:20
+    U32 CMDB                                    :  4;  // Bits 27:24
+    U32 CMDC                                    :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH1_CR_QCLK_LDAT_PDAT_STRUCT;
+
+typedef union {
+  struct {
+    U32 BANKSEL                                 :  4;  // Bits 3:0
+    U32                                         :  1;  // Bits 4:4
+    U32 ARRAYSEL                                :  5;  // Bits 9:5
+    U32 CMP                                     :  1;  // Bits 10:10
+    U32 REP                                     :  1;  // Bits 11:11
+    U32 DWORD                                   :  4;  // Bits 15:12
+    U32 MODE                                    :  2;  // Bits 17:16
+    U32 MPMAP                                   :  6;  // Bits 23:18
+    U32 MPBOFFSET                               :  4;  // Bits 27:24
+    U32 STAGE_EN                                :  1;  // Bits 28:28
+    U32 SHADOW                                  :  2;  // Bits 30:29
+    U32                                         :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH1_CR_QCLK_LDAT_SDAT_STRUCT;
+
+typedef union {
+  struct {
+    U32 DATOUT                                  :  32;  // Bits 31:0
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH1_CR_QCLK_LDAT_DATAOUT_STRUCT;
+
+typedef union {
+  struct {
+    U32 DATIN                                   :  32;  // Bits 31:0
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH1_CR_QCLK_LDAT_DATAIN_0_STRUCT;
+
+typedef union {
+  struct {
+    U32 DATIN                                   :  32;  // Bits 31:0
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH1_CR_QCLK_LDAT_DATAIN_1_STRUCT;
+
+typedef union {
+  struct {
+    U32 RPQ_disable                             :  28;  // Bits 27:0
+    U32                                         :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH1_CR_QUEUE_ENTRY_DISABLE_RPQ_STRUCT;
+
+typedef union {
+  struct {
+    U32 WPQ_disable                             :  32;  // Bits 31:0
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH1_CR_QUEUE_ENTRY_DISABLE_WPQ_STRUCT;
+
+typedef union {
+  struct {
+    U32 DIMM0_IDLE_ENERGY                       :  6;  // Bits 5:0
+    U32                                         :  2;  // Bits 7:6
+    U32 DIMM1_IDLE_ENERGY                       :  6;  // Bits 13:8
+    U32                                         :  18;  // Bits 31:14
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH1_CR_PM_DIMM_IDLE_ENERGY_STRUCT;
+
+typedef union {
+  struct {
+    U32 DIMM0_PD_ENERGY                         :  6;  // Bits 5:0
+    U32                                         :  2;  // Bits 7:6
+    U32 DIMM1_PD_ENERGY                         :  6;  // Bits 13:8
+    U32                                         :  18;  // Bits 31:14
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH1_CR_PM_DIMM_PD_ENERGY_STRUCT;
+
+typedef union {
+  struct {
+    U32 DIMM0_ACT_ENERGY                        :  8;  // Bits 7:0
+    U32 DIMM1_ACT_ENERGY                        :  8;  // Bits 15:8
+    U32                                         :  16;  // Bits 31:16
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH1_CR_PM_DIMM_ACT_ENERGY_STRUCT;
+
+typedef union {
+  struct {
+    U32 DIMM0_RD_ENERGY                         :  8;  // Bits 7:0
+    U32 DIMM1_RD_ENERGY                         :  8;  // Bits 15:8
+    U32                                         :  16;  // Bits 31:16
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH1_CR_PM_DIMM_RD_ENERGY_STRUCT;
+
+typedef union {
+  struct {
+    U32 DIMM0_WR_ENERGY                         :  8;  // Bits 7:0
+    U32 DIMM1_WR_ENERGY                         :  8;  // Bits 15:8
+    U32                                         :  16;  // Bits 31:16
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH1_CR_PM_DIMM_WR_ENERGY_STRUCT;
+
+typedef union {
+  struct {
+    U32 CKE_MIN                                 :  8;  // Bits 7:0
+    U32 CKE_MIN_DEFEATURE                       :  1;  // Bits 8:8
+    U32                                         :  23;  // Bits 31:9
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH1_CR_PM_THRT_CKE_MIN_STRUCT;
+
+typedef union {
+  struct {
+    U32 ODT                                     :  4;  // Bits 3:0
+    U32 Web                                     :  1;  // Bits 4:4
+    U32 CASb                                    :  1;  // Bits 5:5
+    U32 RASb                                    :  1;  // Bits 6:6
+    U32 CSb                                     :  4;  // Bits 10:7
+    U32 CKE                                     :  4;  // Bits 14:11
+    U32 MA                                      :  16;  // Bits 30:15
+    U32                                         :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH1_CR_ODLAT_CMD_MATCH0_STRUCT;
+
+typedef union {
+  struct {
+    U32 ODT                                     :  4;  // Bits 3:0
+    U32 Web                                     :  1;  // Bits 4:4
+    U32 CASb                                    :  1;  // Bits 5:5
+    U32 RASb                                    :  1;  // Bits 6:6
+    U32 CSb                                     :  4;  // Bits 10:7
+    U32 CKE                                     :  4;  // Bits 14:11
+    U32 MA                                      :  16;  // Bits 30:15
+    U32                                         :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH1_CR_ODLAT_CMD_MATCH1_STRUCT;
+
+typedef union {
+  struct {
+    U32 ODT                                     :  4;  // Bits 3:0
+    U32 Web                                     :  1;  // Bits 4:4
+    U32 CASb                                    :  1;  // Bits 5:5
+    U32 RASb                                    :  1;  // Bits 6:6
+    U32 CSb                                     :  4;  // Bits 10:7
+    U32 CKE                                     :  4;  // Bits 14:11
+    U32 MA                                      :  16;  // Bits 30:15
+    U32                                         :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH1_CR_ODLAT_CMD_MATCH2_STRUCT;
+
+typedef union {
+  struct {
+    U32 ODT                                     :  4;  // Bits 3:0
+    U32 Web                                     :  1;  // Bits 4:4
+    U32 CASb                                    :  1;  // Bits 5:5
+    U32 RASb                                    :  1;  // Bits 6:6
+    U32 CSb                                     :  4;  // Bits 10:7
+    U32 CKE                                     :  4;  // Bits 14:11
+    U32 MA                                      :  16;  // Bits 30:15
+    U32                                         :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH1_CR_ODLAT_CMD_MATCH3_STRUCT;
+
+typedef union {
+  struct {
+    U32 ODT                                     :  4;  // Bits 3:0
+    U32 Web                                     :  1;  // Bits 4:4
+    U32 CASb                                    :  1;  // Bits 5:5
+    U32 RASb                                    :  1;  // Bits 6:6
+    U32 CSb                                     :  4;  // Bits 10:7
+    U32 CKE                                     :  4;  // Bits 14:11
+    U32 MA                                      :  16;  // Bits 30:15
+    U32                                         :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH1_CR_ODLAT_CMD_MASK0_STRUCT;
+
+typedef union {
+  struct {
+    U32 ODT                                     :  4;  // Bits 3:0
+    U32 Web                                     :  1;  // Bits 4:4
+    U32 CASb                                    :  1;  // Bits 5:5
+    U32 RASb                                    :  1;  // Bits 6:6
+    U32 CSb                                     :  4;  // Bits 10:7
+    U32 CKE                                     :  4;  // Bits 14:11
+    U32 MA                                      :  16;  // Bits 30:15
+    U32                                         :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH1_CR_ODLAT_CMD_MASK1_STRUCT;
+
+typedef union {
+  struct {
+    U32 ODT                                     :  4;  // Bits 3:0
+    U32 Web                                     :  1;  // Bits 4:4
+    U32 CASb                                    :  1;  // Bits 5:5
+    U32 RASb                                    :  1;  // Bits 6:6
+    U32 CSb                                     :  4;  // Bits 10:7
+    U32 CKE                                     :  4;  // Bits 14:11
+    U32 MA                                      :  16;  // Bits 30:15
+    U32                                         :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH1_CR_ODLAT_CMD_MASK2_STRUCT;
+
+typedef union {
+  struct {
+    U32 ODT                                     :  4;  // Bits 3:0
+    U32 Web                                     :  1;  // Bits 4:4
+    U32 CASb                                    :  1;  // Bits 5:5
+    U32 RASb                                    :  1;  // Bits 6:6
+    U32 CSb                                     :  4;  // Bits 10:7
+    U32 CKE                                     :  4;  // Bits 14:11
+    U32 MA                                      :  16;  // Bits 30:15
+    U32                                         :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH1_CR_ODLAT_CMD_MASK3_STRUCT;
+
+typedef union {
+  struct {
+    U32 BankMatch0                              :  3;  // Bits 2:0
+    U32 BankMatch1                              :  3;  // Bits 5:3
+    U32 BankMatch2                              :  3;  // Bits 8:6
+    U32 BankMatch3                              :  3;  // Bits 11:9
+    U32 BankMask0                               :  3;  // Bits 14:12
+    U32 BankMask1                               :  3;  // Bits 17:15
+    U32 BankMask2                               :  3;  // Bits 20:18
+    U32 BankMask3                               :  3;  // Bits 23:21
+    U32                                         :  8;  // Bits 31:24
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH1_CR_ODLAT_CMD_BANK_STRUCT;
+
+typedef union {
+  struct {
+    U32 InputMatch                              :  4;  // Bits 3:0
+    U32 InputInvert                             :  4;  // Bits 7:4
+    U32 CountMatches                            :  1;  // Bits 8:8
+    U32 CounterThreshold                        :  15;  // Bits 23:9
+    U32 CounterAction                           :  2;  // Bits 25:24
+    U32 CounterNextState                        :  2;  // Bits 27:26
+    U32 MatchAction                             :  2;  // Bits 29:28
+    U32 MatchNextState                          :  2;  // Bits 31:30
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL0_STRUCT;
+
+typedef union {
+  struct {
+    U32 InputMatch                              :  4;  // Bits 3:0
+    U32 InputInvert                             :  4;  // Bits 7:4
+    U32 CountMatches                            :  1;  // Bits 8:8
+    U32 CounterThreshold                        :  15;  // Bits 23:9
+    U32 CounterAction                           :  2;  // Bits 25:24
+    U32 CounterNextState                        :  2;  // Bits 27:26
+    U32 MatchAction                             :  2;  // Bits 29:28
+    U32 MatchNextState                          :  2;  // Bits 31:30
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL1_STRUCT;
+
+typedef union {
+  struct {
+    U32 InputMatch                              :  4;  // Bits 3:0
+    U32 InputInvert                             :  4;  // Bits 7:4
+    U32 CountMatches                            :  1;  // Bits 8:8
+    U32 CounterThreshold                        :  15;  // Bits 23:9
+    U32 CounterAction                           :  2;  // Bits 25:24
+    U32 CounterNextState                        :  2;  // Bits 27:26
+    U32 MatchAction                             :  2;  // Bits 29:28
+    U32 MatchNextState                          :  2;  // Bits 31:30
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL2_STRUCT;
+
+typedef union {
+  struct {
+    U32 InputMatch                              :  4;  // Bits 3:0
+    U32 InputInvert                             :  4;  // Bits 7:4
+    U32 CountMatches                            :  1;  // Bits 8:8
+    U32 CounterThreshold                        :  15;  // Bits 23:9
+    U32 CounterAction                           :  2;  // Bits 25:24
+    U32 CounterNextState                        :  2;  // Bits 27:26
+    U32 MatchAction                             :  2;  // Bits 29:28
+    U32 MatchNextState                          :  2;  // Bits 31:30
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL3_STRUCT;
+
+typedef union {
+  struct {
+    U32 TriggerBlockEnable                      :  1;  // Bits 0:0
+    U32 GlobalCounterThreshold                  :  16;  // Bits 16:1
+    U32                                         :  15;  // Bits 31:17
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH1_CR_ODLAT_SEQ_GLOBAL_STRUCT;
+
+typedef union {
+  struct {
+    U32 WMM_Enter                               :  8;  // Bits 7:0
+    U32 WMM_Exit                                :  8;  // Bits 15:8
+    U32 WPQ_IS                                  :  8;  // Bits 23:16
+    U32 Starve_count                            :  8;  // Bits 31:24
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH1_CR_SC_WDBWM_STRUCT;
+
+typedef union {
+  struct {
+    U32 Data                                    :  18;  // Bits 17:0
+    U32                                         :  13;  // Bits 30:18
+    U32 VORANGE                                 :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MCHBAR_CH1_CR_VISA_CTL_MCMNTS_STRUCT;
+
+#define MCDFXS_CR_REUT_GLOBAL_CTL_MCMAIN_REG                         (0x00004800)
+  #define MCDFXS_CR_REUT_GLOBAL_CTL_MCMAIN_Global_Start_Test_OFF       ( 0)
+  #define MCDFXS_CR_REUT_GLOBAL_CTL_MCMAIN_Global_Start_Test_WID       ( 1)
+  #define MCDFXS_CR_REUT_GLOBAL_CTL_MCMAIN_Global_Start_Test_MSK       (0x00000001)
+  #define MCDFXS_CR_REUT_GLOBAL_CTL_MCMAIN_Global_Start_Test_MAX       (0x00000001)
+  #define MCDFXS_CR_REUT_GLOBAL_CTL_MCMAIN_Global_Start_Test_DEF       (0x00000000)
+  #define MCDFXS_CR_REUT_GLOBAL_CTL_MCMAIN_Global_Stop_Test_OFF        ( 1)
+  #define MCDFXS_CR_REUT_GLOBAL_CTL_MCMAIN_Global_Stop_Test_WID        ( 1)
+  #define MCDFXS_CR_REUT_GLOBAL_CTL_MCMAIN_Global_Stop_Test_MSK        (0x00000002)
+  #define MCDFXS_CR_REUT_GLOBAL_CTL_MCMAIN_Global_Stop_Test_MAX        (0x00000001)
+  #define MCDFXS_CR_REUT_GLOBAL_CTL_MCMAIN_Global_Stop_Test_DEF        (0x00000000)
+  #define MCDFXS_CR_REUT_GLOBAL_CTL_MCMAIN_Global_Clear_Errors_OFF     ( 2)
+  #define MCDFXS_CR_REUT_GLOBAL_CTL_MCMAIN_Global_Clear_Errors_WID     ( 1)
+  #define MCDFXS_CR_REUT_GLOBAL_CTL_MCMAIN_Global_Clear_Errors_MSK     (0x00000004)
+  #define MCDFXS_CR_REUT_GLOBAL_CTL_MCMAIN_Global_Clear_Errors_MAX     (0x00000001)
+  #define MCDFXS_CR_REUT_GLOBAL_CTL_MCMAIN_Global_Clear_Errors_DEF     (0x00000000)
+  #define MCDFXS_CR_REUT_GLOBAL_CTL_MCMAIN_Global_Stop_Test_On_Any_Error_OFF ( 4)
+  #define MCDFXS_CR_REUT_GLOBAL_CTL_MCMAIN_Global_Stop_Test_On_Any_Error_WID ( 1)
+  #define MCDFXS_CR_REUT_GLOBAL_CTL_MCMAIN_Global_Stop_Test_On_Any_Error_MSK (0x00000010)
+  #define MCDFXS_CR_REUT_GLOBAL_CTL_MCMAIN_Global_Stop_Test_On_Any_Error_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_GLOBAL_CTL_MCMAIN_Global_Stop_Test_On_Any_Error_DEF (0x00000000)
+
+#define MCDFXS_CR_REUT_GLOBAL_ERR_MCMAIN_REG                         (0x00004804)
+  #define MCDFXS_CR_REUT_GLOBAL_ERR_MCMAIN_Channel_Error_Status_0_OFF  ( 0)
+  #define MCDFXS_CR_REUT_GLOBAL_ERR_MCMAIN_Channel_Error_Status_0_WID  ( 1)
+  #define MCDFXS_CR_REUT_GLOBAL_ERR_MCMAIN_Channel_Error_Status_0_MSK  (0x00000001)
+  #define MCDFXS_CR_REUT_GLOBAL_ERR_MCMAIN_Channel_Error_Status_0_MAX  (0x00000001)
+  #define MCDFXS_CR_REUT_GLOBAL_ERR_MCMAIN_Channel_Error_Status_0_DEF  (0x00000000)
+  #define MCDFXS_CR_REUT_GLOBAL_ERR_MCMAIN_Channel_Error_Status_1_OFF  ( 1)
+  #define MCDFXS_CR_REUT_GLOBAL_ERR_MCMAIN_Channel_Error_Status_1_WID  ( 1)
+  #define MCDFXS_CR_REUT_GLOBAL_ERR_MCMAIN_Channel_Error_Status_1_MSK  (0x00000002)
+  #define MCDFXS_CR_REUT_GLOBAL_ERR_MCMAIN_Channel_Error_Status_1_MAX  (0x00000001)
+  #define MCDFXS_CR_REUT_GLOBAL_ERR_MCMAIN_Channel_Error_Status_1_DEF  (0x00000000)
+  #define MCDFXS_CR_REUT_GLOBAL_ERR_MCMAIN_Channel_Test_Done_Status_0_OFF (16)
+  #define MCDFXS_CR_REUT_GLOBAL_ERR_MCMAIN_Channel_Test_Done_Status_0_WID ( 1)
+  #define MCDFXS_CR_REUT_GLOBAL_ERR_MCMAIN_Channel_Test_Done_Status_0_MSK (0x00010000)
+  #define MCDFXS_CR_REUT_GLOBAL_ERR_MCMAIN_Channel_Test_Done_Status_0_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_GLOBAL_ERR_MCMAIN_Channel_Test_Done_Status_0_DEF (0x00000001)
+  #define MCDFXS_CR_REUT_GLOBAL_ERR_MCMAIN_Channel_Test_Done_Status_1_OFF (17)
+  #define MCDFXS_CR_REUT_GLOBAL_ERR_MCMAIN_Channel_Test_Done_Status_1_WID ( 1)
+  #define MCDFXS_CR_REUT_GLOBAL_ERR_MCMAIN_Channel_Test_Done_Status_1_MSK (0x00020000)
+  #define MCDFXS_CR_REUT_GLOBAL_ERR_MCMAIN_Channel_Test_Done_Status_1_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_GLOBAL_ERR_MCMAIN_Channel_Test_Done_Status_1_DEF (0x00000001)
+
+#define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_REG                   (0x00004808)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Number_of_Cachelines_OFF ( 0)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Number_of_Cachelines_WID ( 7)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Number_of_Cachelines_MSK (0x0000007F)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Number_of_Cachelines_MAX (0x0000007F)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Number_of_Cachelines_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Number_of_Cachelines_Scale_OFF ( 7)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Number_of_Cachelines_Scale_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Number_of_Cachelines_Scale_MSK (0x00000080)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Number_of_Cachelines_Scale_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Number_of_Cachelines_Scale_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Subsequence_Wait_OFF  ( 8)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Subsequence_Wait_WID  (10)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Subsequence_Wait_MSK  (0x0003FF00)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Subsequence_Wait_MAX  (0x000003FF)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Subsequence_Wait_DEF  (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Subsequence_Type_OFF  (20)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Subsequence_Type_WID  ( 4)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Subsequence_Type_MSK  (0x00F00000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Subsequence_Type_MAX  (0x0000000F)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Subsequence_Type_DEF  (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Save_Current_Base_Address_To_Start_OFF (25)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Save_Current_Base_Address_To_Start_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Save_Current_Base_Address_To_Start_MSK (0x02000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Save_Current_Base_Address_To_Start_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Save_Current_Base_Address_To_Start_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Reset_Current_Base_Address_To_Start_OFF (26)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Reset_Current_Base_Address_To_Start_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Reset_Current_Base_Address_To_Start_MSK (0x04000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Reset_Current_Base_Address_To_Start_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Reset_Current_Base_Address_To_Start_DEF (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Data_and_ECC_Address_Inversion_OFF (27)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Data_and_ECC_Address_Inversion_WID ( 2)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Data_and_ECC_Address_Inversion_MSK (0x18000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Data_and_ECC_Address_Inversion_MAX (0x00000003)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Data_and_ECC_Address_Inversion_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Invert_Data_and_ECC_OFF (30)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Invert_Data_and_ECC_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Invert_Data_and_ECC_MSK (0x40000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Invert_Data_and_ECC_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Invert_Data_and_ECC_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_OFF (31)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_MSK (0x80000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_DEF (0x00000000)
+
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_Number_of_Cachelines_OFF ( 0)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_Number_of_Cachelines_WID ( 7)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_Number_of_Cachelines_MSK (0x0000007F)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_Number_of_Cachelines_MAX (0x0000007F)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_Number_of_Cachelines_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_Number_of_Cachelines_Scale_OFF ( 7)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_Number_of_Cachelines_Scale_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_Number_of_Cachelines_Scale_MSK (0x00000080)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_Number_of_Cachelines_Scale_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_Number_of_Cachelines_Scale_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_Subsequence_Wait_OFF  ( 8)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_Subsequence_Wait_WID  (14)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_Subsequence_Wait_MSK  (0x003FFF00)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_Subsequence_Wait_MAX  (0x00003FFF)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_Subsequence_Wait_DEF  (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_Subsequence_Type_OFF  (22)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_Subsequence_Type_WID  ( 4)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_Subsequence_Type_MSK  (0x03C00000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_Subsequence_Type_MAX  (0x0000000F)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_Subsequence_Type_DEF  (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_Save_Current_Base_Address_To_Start_OFF (26)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_Save_Current_Base_Address_To_Start_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_Save_Current_Base_Address_To_Start_MSK (0x04000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_Save_Current_Base_Address_To_Start_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_Save_Current_Base_Address_To_Start_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_Reset_Current_Base_Address_To_Start_OFF (27)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_Reset_Current_Base_Address_To_Start_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_Reset_Current_Base_Address_To_Start_MSK (0x08000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_Reset_Current_Base_Address_To_Start_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_Reset_Current_Base_Address_To_Start_DEF (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_Data_and_ECC_Address_Inversion_OFF (28)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_Data_and_ECC_Address_Inversion_WID ( 2)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_Data_and_ECC_Address_Inversion_MSK (0x30000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_Data_and_ECC_Address_Inversion_MAX (0x00000003)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_Data_and_ECC_Address_Inversion_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_Invert_Data_and_ECC_OFF (30)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_Invert_Data_and_ECC_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_Invert_Data_and_ECC_MSK (0x40000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_Invert_Data_and_ECC_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_Invert_Data_and_ECC_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_Stop_Base_Subsequence_On_Wrap_Trigger_OFF (31)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_Stop_Base_Subsequence_On_Wrap_Trigger_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_Stop_Base_Subsequence_On_Wrap_Trigger_MSK (0x80000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_Stop_Base_Subsequence_On_Wrap_Trigger_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_Stop_Base_Subsequence_On_Wrap_Trigger_DEF (0x00000000)
+
+#define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_REG                   (0x0000480C)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Number_of_Cachelines_OFF ( 0)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Number_of_Cachelines_WID ( 7)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Number_of_Cachelines_MSK (0x0000007F)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Number_of_Cachelines_MAX (0x0000007F)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Number_of_Cachelines_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Number_of_Cachelines_Scale_OFF ( 7)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Number_of_Cachelines_Scale_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Number_of_Cachelines_Scale_MSK (0x00000080)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Number_of_Cachelines_Scale_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Number_of_Cachelines_Scale_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Subsequence_Wait_OFF  ( 8)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Subsequence_Wait_WID  (10)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Subsequence_Wait_MSK  (0x0003FF00)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Subsequence_Wait_MAX  (0x000003FF)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Subsequence_Wait_DEF  (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Subsequence_Type_OFF  (20)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Subsequence_Type_WID  ( 4)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Subsequence_Type_MSK  (0x00F00000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Subsequence_Type_MAX  (0x0000000F)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Subsequence_Type_DEF  (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Save_Current_Base_Address_To_Start_OFF (25)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Save_Current_Base_Address_To_Start_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Save_Current_Base_Address_To_Start_MSK (0x02000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Save_Current_Base_Address_To_Start_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Save_Current_Base_Address_To_Start_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Reset_Current_Base_Address_To_Start_OFF (26)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Reset_Current_Base_Address_To_Start_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Reset_Current_Base_Address_To_Start_MSK (0x04000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Reset_Current_Base_Address_To_Start_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Reset_Current_Base_Address_To_Start_DEF (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Data_and_ECC_Address_Inversion_OFF (27)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Data_and_ECC_Address_Inversion_WID ( 2)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Data_and_ECC_Address_Inversion_MSK (0x18000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Data_and_ECC_Address_Inversion_MAX (0x00000003)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Data_and_ECC_Address_Inversion_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Invert_Data_and_ECC_OFF (30)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Invert_Data_and_ECC_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Invert_Data_and_ECC_MSK (0x40000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Invert_Data_and_ECC_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Invert_Data_and_ECC_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_OFF (31)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_MSK (0x80000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_DEF (0x00000000)
+
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_Number_of_Cachelines_OFF ( 0)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_Number_of_Cachelines_WID ( 7)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_Number_of_Cachelines_MSK (0x0000007F)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_Number_of_Cachelines_MAX (0x0000007F)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_Number_of_Cachelines_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_Number_of_Cachelines_Scale_OFF ( 7)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_Number_of_Cachelines_Scale_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_Number_of_Cachelines_Scale_MSK (0x00000080)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_Number_of_Cachelines_Scale_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_Number_of_Cachelines_Scale_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_Subsequence_Wait_OFF  ( 8)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_Subsequence_Wait_WID  (14)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_Subsequence_Wait_MSK  (0x003FFF00)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_Subsequence_Wait_MAX  (0x00003FFF)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_Subsequence_Wait_DEF  (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_Subsequence_Type_OFF  (22)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_Subsequence_Type_WID  ( 4)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_Subsequence_Type_MSK  (0x03C00000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_Subsequence_Type_MAX  (0x0000000F)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_Subsequence_Type_DEF  (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_Save_Current_Base_Address_To_Start_OFF (26)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_Save_Current_Base_Address_To_Start_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_Save_Current_Base_Address_To_Start_MSK (0x04000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_Save_Current_Base_Address_To_Start_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_Save_Current_Base_Address_To_Start_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_Reset_Current_Base_Address_To_Start_OFF (27)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_Reset_Current_Base_Address_To_Start_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_Reset_Current_Base_Address_To_Start_MSK (0x08000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_Reset_Current_Base_Address_To_Start_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_Reset_Current_Base_Address_To_Start_DEF (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_Data_and_ECC_Address_Inversion_OFF (28)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_Data_and_ECC_Address_Inversion_WID ( 2)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_Data_and_ECC_Address_Inversion_MSK (0x30000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_Data_and_ECC_Address_Inversion_MAX (0x00000003)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_Data_and_ECC_Address_Inversion_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_Invert_Data_and_ECC_OFF (30)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_Invert_Data_and_ECC_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_Invert_Data_and_ECC_MSK (0x40000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_Invert_Data_and_ECC_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_Invert_Data_and_ECC_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_Stop_Base_Subsequence_On_Wrap_Trigger_OFF (31)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_Stop_Base_Subsequence_On_Wrap_Trigger_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_Stop_Base_Subsequence_On_Wrap_Trigger_MSK (0x80000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_Stop_Base_Subsequence_On_Wrap_Trigger_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_Stop_Base_Subsequence_On_Wrap_Trigger_DEF (0x00000000)
+
+#define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_REG                   (0x00004810)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Number_of_Cachelines_OFF ( 0)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Number_of_Cachelines_WID ( 7)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Number_of_Cachelines_MSK (0x0000007F)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Number_of_Cachelines_MAX (0x0000007F)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Number_of_Cachelines_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Number_of_Cachelines_Scale_OFF ( 7)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Number_of_Cachelines_Scale_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Number_of_Cachelines_Scale_MSK (0x00000080)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Number_of_Cachelines_Scale_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Number_of_Cachelines_Scale_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Subsequence_Wait_OFF  ( 8)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Subsequence_Wait_WID  (10)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Subsequence_Wait_MSK  (0x0003FF00)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Subsequence_Wait_MAX  (0x000003FF)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Subsequence_Wait_DEF  (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Subsequence_Type_OFF  (20)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Subsequence_Type_WID  ( 4)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Subsequence_Type_MSK  (0x00F00000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Subsequence_Type_MAX  (0x0000000F)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Subsequence_Type_DEF  (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Save_Current_Base_Address_To_Start_OFF (25)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Save_Current_Base_Address_To_Start_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Save_Current_Base_Address_To_Start_MSK (0x02000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Save_Current_Base_Address_To_Start_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Save_Current_Base_Address_To_Start_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Reset_Current_Base_Address_To_Start_OFF (26)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Reset_Current_Base_Address_To_Start_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Reset_Current_Base_Address_To_Start_MSK (0x04000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Reset_Current_Base_Address_To_Start_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Reset_Current_Base_Address_To_Start_DEF (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Data_and_ECC_Address_Inversion_OFF (27)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Data_and_ECC_Address_Inversion_WID ( 2)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Data_and_ECC_Address_Inversion_MSK (0x18000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Data_and_ECC_Address_Inversion_MAX (0x00000003)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Data_and_ECC_Address_Inversion_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Invert_Data_and_ECC_OFF (30)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Invert_Data_and_ECC_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Invert_Data_and_ECC_MSK (0x40000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Invert_Data_and_ECC_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Invert_Data_and_ECC_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_OFF (31)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_MSK (0x80000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_DEF (0x00000000)
+
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_Number_of_Cachelines_OFF ( 0)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_Number_of_Cachelines_WID ( 7)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_Number_of_Cachelines_MSK (0x0000007F)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_Number_of_Cachelines_MAX (0x0000007F)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_Number_of_Cachelines_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_Number_of_Cachelines_Scale_OFF ( 7)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_Number_of_Cachelines_Scale_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_Number_of_Cachelines_Scale_MSK (0x00000080)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_Number_of_Cachelines_Scale_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_Number_of_Cachelines_Scale_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_Subsequence_Wait_OFF  ( 8)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_Subsequence_Wait_WID  (14)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_Subsequence_Wait_MSK  (0x003FFF00)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_Subsequence_Wait_MAX  (0x00003FFF)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_Subsequence_Wait_DEF  (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_Subsequence_Type_OFF  (22)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_Subsequence_Type_WID  ( 4)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_Subsequence_Type_MSK  (0x03C00000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_Subsequence_Type_MAX  (0x0000000F)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_Subsequence_Type_DEF  (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_Save_Current_Base_Address_To_Start_OFF (26)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_Save_Current_Base_Address_To_Start_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_Save_Current_Base_Address_To_Start_MSK (0x04000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_Save_Current_Base_Address_To_Start_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_Save_Current_Base_Address_To_Start_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_Reset_Current_Base_Address_To_Start_OFF (27)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_Reset_Current_Base_Address_To_Start_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_Reset_Current_Base_Address_To_Start_MSK (0x08000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_Reset_Current_Base_Address_To_Start_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_Reset_Current_Base_Address_To_Start_DEF (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_Data_and_ECC_Address_Inversion_OFF (28)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_Data_and_ECC_Address_Inversion_WID ( 2)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_Data_and_ECC_Address_Inversion_MSK (0x30000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_Data_and_ECC_Address_Inversion_MAX (0x00000003)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_Data_and_ECC_Address_Inversion_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_Invert_Data_and_ECC_OFF (30)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_Invert_Data_and_ECC_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_Invert_Data_and_ECC_MSK (0x40000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_Invert_Data_and_ECC_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_Invert_Data_and_ECC_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_Stop_Base_Subsequence_On_Wrap_Trigger_OFF (31)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_Stop_Base_Subsequence_On_Wrap_Trigger_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_Stop_Base_Subsequence_On_Wrap_Trigger_MSK (0x80000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_Stop_Base_Subsequence_On_Wrap_Trigger_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_Stop_Base_Subsequence_On_Wrap_Trigger_DEF (0x00000000)
+
+#define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_REG                   (0x00004814)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Number_of_Cachelines_OFF ( 0)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Number_of_Cachelines_WID ( 7)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Number_of_Cachelines_MSK (0x0000007F)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Number_of_Cachelines_MAX (0x0000007F)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Number_of_Cachelines_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Number_of_Cachelines_Scale_OFF ( 7)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Number_of_Cachelines_Scale_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Number_of_Cachelines_Scale_MSK (0x00000080)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Number_of_Cachelines_Scale_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Number_of_Cachelines_Scale_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Subsequence_Wait_OFF  ( 8)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Subsequence_Wait_WID  (10)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Subsequence_Wait_MSK  (0x0003FF00)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Subsequence_Wait_MAX  (0x000003FF)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Subsequence_Wait_DEF  (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Subsequence_Type_OFF  (20)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Subsequence_Type_WID  ( 4)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Subsequence_Type_MSK  (0x00F00000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Subsequence_Type_MAX  (0x0000000F)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Subsequence_Type_DEF  (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Save_Current_Base_Address_To_Start_OFF (25)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Save_Current_Base_Address_To_Start_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Save_Current_Base_Address_To_Start_MSK (0x02000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Save_Current_Base_Address_To_Start_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Save_Current_Base_Address_To_Start_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Reset_Current_Base_Address_To_Start_OFF (26)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Reset_Current_Base_Address_To_Start_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Reset_Current_Base_Address_To_Start_MSK (0x04000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Reset_Current_Base_Address_To_Start_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Reset_Current_Base_Address_To_Start_DEF (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Data_and_ECC_Address_Inversion_OFF (27)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Data_and_ECC_Address_Inversion_WID ( 2)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Data_and_ECC_Address_Inversion_MSK (0x18000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Data_and_ECC_Address_Inversion_MAX (0x00000003)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Data_and_ECC_Address_Inversion_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Invert_Data_and_ECC_OFF (30)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Invert_Data_and_ECC_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Invert_Data_and_ECC_MSK (0x40000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Invert_Data_and_ECC_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Invert_Data_and_ECC_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_OFF (31)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_MSK (0x80000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_DEF (0x00000000)
+
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_Number_of_Cachelines_OFF ( 0)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_Number_of_Cachelines_WID ( 7)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_Number_of_Cachelines_MSK (0x0000007F)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_Number_of_Cachelines_MAX (0x0000007F)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_Number_of_Cachelines_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_Number_of_Cachelines_Scale_OFF ( 7)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_Number_of_Cachelines_Scale_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_Number_of_Cachelines_Scale_MSK (0x00000080)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_Number_of_Cachelines_Scale_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_Number_of_Cachelines_Scale_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_Subsequence_Wait_OFF  ( 8)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_Subsequence_Wait_WID  (14)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_Subsequence_Wait_MSK  (0x003FFF00)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_Subsequence_Wait_MAX  (0x00003FFF)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_Subsequence_Wait_DEF  (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_Subsequence_Type_OFF  (22)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_Subsequence_Type_WID  ( 4)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_Subsequence_Type_MSK  (0x03C00000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_Subsequence_Type_MAX  (0x0000000F)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_Subsequence_Type_DEF  (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_Save_Current_Base_Address_To_Start_OFF (26)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_Save_Current_Base_Address_To_Start_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_Save_Current_Base_Address_To_Start_MSK (0x04000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_Save_Current_Base_Address_To_Start_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_Save_Current_Base_Address_To_Start_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_Reset_Current_Base_Address_To_Start_OFF (27)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_Reset_Current_Base_Address_To_Start_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_Reset_Current_Base_Address_To_Start_MSK (0x08000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_Reset_Current_Base_Address_To_Start_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_Reset_Current_Base_Address_To_Start_DEF (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_Data_and_ECC_Address_Inversion_OFF (28)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_Data_and_ECC_Address_Inversion_WID ( 2)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_Data_and_ECC_Address_Inversion_MSK (0x30000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_Data_and_ECC_Address_Inversion_MAX (0x00000003)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_Data_and_ECC_Address_Inversion_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_Invert_Data_and_ECC_OFF (30)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_Invert_Data_and_ECC_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_Invert_Data_and_ECC_MSK (0x40000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_Invert_Data_and_ECC_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_Invert_Data_and_ECC_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_Stop_Base_Subsequence_On_Wrap_Trigger_OFF (31)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_Stop_Base_Subsequence_On_Wrap_Trigger_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_Stop_Base_Subsequence_On_Wrap_Trigger_MSK (0x80000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_Stop_Base_Subsequence_On_Wrap_Trigger_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_Stop_Base_Subsequence_On_Wrap_Trigger_DEF (0x00000000)
+
+#define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_REG                   (0x00004818)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Number_of_Cachelines_OFF ( 0)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Number_of_Cachelines_WID ( 7)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Number_of_Cachelines_MSK (0x0000007F)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Number_of_Cachelines_MAX (0x0000007F)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Number_of_Cachelines_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Number_of_Cachelines_Scale_OFF ( 7)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Number_of_Cachelines_Scale_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Number_of_Cachelines_Scale_MSK (0x00000080)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Number_of_Cachelines_Scale_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Number_of_Cachelines_Scale_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Subsequence_Wait_OFF  ( 8)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Subsequence_Wait_WID  (10)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Subsequence_Wait_MSK  (0x0003FF00)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Subsequence_Wait_MAX  (0x000003FF)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Subsequence_Wait_DEF  (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Subsequence_Type_OFF  (20)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Subsequence_Type_WID  ( 4)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Subsequence_Type_MSK  (0x00F00000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Subsequence_Type_MAX  (0x0000000F)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Subsequence_Type_DEF  (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Save_Current_Base_Address_To_Start_OFF (25)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Save_Current_Base_Address_To_Start_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Save_Current_Base_Address_To_Start_MSK (0x02000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Save_Current_Base_Address_To_Start_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Save_Current_Base_Address_To_Start_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Reset_Current_Base_Address_To_Start_OFF (26)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Reset_Current_Base_Address_To_Start_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Reset_Current_Base_Address_To_Start_MSK (0x04000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Reset_Current_Base_Address_To_Start_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Reset_Current_Base_Address_To_Start_DEF (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Data_and_ECC_Address_Inversion_OFF (27)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Data_and_ECC_Address_Inversion_WID ( 2)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Data_and_ECC_Address_Inversion_MSK (0x18000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Data_and_ECC_Address_Inversion_MAX (0x00000003)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Data_and_ECC_Address_Inversion_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Invert_Data_and_ECC_OFF (30)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Invert_Data_and_ECC_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Invert_Data_and_ECC_MSK (0x40000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Invert_Data_and_ECC_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Invert_Data_and_ECC_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_OFF (31)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_MSK (0x80000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_DEF (0x00000000)
+
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_Number_of_Cachelines_OFF ( 0)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_Number_of_Cachelines_WID ( 7)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_Number_of_Cachelines_MSK (0x0000007F)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_Number_of_Cachelines_MAX (0x0000007F)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_Number_of_Cachelines_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_Number_of_Cachelines_Scale_OFF ( 7)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_Number_of_Cachelines_Scale_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_Number_of_Cachelines_Scale_MSK (0x00000080)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_Number_of_Cachelines_Scale_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_Number_of_Cachelines_Scale_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_Subsequence_Wait_OFF  ( 8)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_Subsequence_Wait_WID  (14)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_Subsequence_Wait_MSK  (0x003FFF00)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_Subsequence_Wait_MAX  (0x00003FFF)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_Subsequence_Wait_DEF  (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_Subsequence_Type_OFF  (22)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_Subsequence_Type_WID  ( 4)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_Subsequence_Type_MSK  (0x03C00000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_Subsequence_Type_MAX  (0x0000000F)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_Subsequence_Type_DEF  (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_Save_Current_Base_Address_To_Start_OFF (26)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_Save_Current_Base_Address_To_Start_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_Save_Current_Base_Address_To_Start_MSK (0x04000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_Save_Current_Base_Address_To_Start_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_Save_Current_Base_Address_To_Start_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_Reset_Current_Base_Address_To_Start_OFF (27)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_Reset_Current_Base_Address_To_Start_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_Reset_Current_Base_Address_To_Start_MSK (0x08000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_Reset_Current_Base_Address_To_Start_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_Reset_Current_Base_Address_To_Start_DEF (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_Data_and_ECC_Address_Inversion_OFF (28)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_Data_and_ECC_Address_Inversion_WID ( 2)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_Data_and_ECC_Address_Inversion_MSK (0x30000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_Data_and_ECC_Address_Inversion_MAX (0x00000003)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_Data_and_ECC_Address_Inversion_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_Invert_Data_and_ECC_OFF (30)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_Invert_Data_and_ECC_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_Invert_Data_and_ECC_MSK (0x40000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_Invert_Data_and_ECC_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_Invert_Data_and_ECC_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_Stop_Base_Subsequence_On_Wrap_Trigger_OFF (31)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_Stop_Base_Subsequence_On_Wrap_Trigger_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_Stop_Base_Subsequence_On_Wrap_Trigger_MSK (0x80000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_Stop_Base_Subsequence_On_Wrap_Trigger_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_Stop_Base_Subsequence_On_Wrap_Trigger_DEF (0x00000000)
+
+#define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_REG                   (0x0000481C)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Number_of_Cachelines_OFF ( 0)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Number_of_Cachelines_WID ( 7)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Number_of_Cachelines_MSK (0x0000007F)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Number_of_Cachelines_MAX (0x0000007F)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Number_of_Cachelines_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Number_of_Cachelines_Scale_OFF ( 7)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Number_of_Cachelines_Scale_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Number_of_Cachelines_Scale_MSK (0x00000080)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Number_of_Cachelines_Scale_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Number_of_Cachelines_Scale_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Subsequence_Wait_OFF  ( 8)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Subsequence_Wait_WID  (10)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Subsequence_Wait_MSK  (0x0003FF00)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Subsequence_Wait_MAX  (0x000003FF)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Subsequence_Wait_DEF  (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Subsequence_Type_OFF  (20)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Subsequence_Type_WID  ( 4)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Subsequence_Type_MSK  (0x00F00000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Subsequence_Type_MAX  (0x0000000F)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Subsequence_Type_DEF  (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Save_Current_Base_Address_To_Start_OFF (25)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Save_Current_Base_Address_To_Start_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Save_Current_Base_Address_To_Start_MSK (0x02000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Save_Current_Base_Address_To_Start_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Save_Current_Base_Address_To_Start_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Reset_Current_Base_Address_To_Start_OFF (26)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Reset_Current_Base_Address_To_Start_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Reset_Current_Base_Address_To_Start_MSK (0x04000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Reset_Current_Base_Address_To_Start_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Reset_Current_Base_Address_To_Start_DEF (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Data_and_ECC_Address_Inversion_OFF (27)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Data_and_ECC_Address_Inversion_WID ( 2)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Data_and_ECC_Address_Inversion_MSK (0x18000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Data_and_ECC_Address_Inversion_MAX (0x00000003)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Data_and_ECC_Address_Inversion_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Invert_Data_and_ECC_OFF (30)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Invert_Data_and_ECC_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Invert_Data_and_ECC_MSK (0x40000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Invert_Data_and_ECC_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Invert_Data_and_ECC_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_OFF (31)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_MSK (0x80000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_DEF (0x00000000)
+
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_Number_of_Cachelines_OFF ( 0)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_Number_of_Cachelines_WID ( 7)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_Number_of_Cachelines_MSK (0x0000007F)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_Number_of_Cachelines_MAX (0x0000007F)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_Number_of_Cachelines_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_Number_of_Cachelines_Scale_OFF ( 7)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_Number_of_Cachelines_Scale_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_Number_of_Cachelines_Scale_MSK (0x00000080)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_Number_of_Cachelines_Scale_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_Number_of_Cachelines_Scale_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_Subsequence_Wait_OFF  ( 8)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_Subsequence_Wait_WID  (14)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_Subsequence_Wait_MSK  (0x003FFF00)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_Subsequence_Wait_MAX  (0x00003FFF)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_Subsequence_Wait_DEF  (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_Subsequence_Type_OFF  (22)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_Subsequence_Type_WID  ( 4)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_Subsequence_Type_MSK  (0x03C00000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_Subsequence_Type_MAX  (0x0000000F)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_Subsequence_Type_DEF  (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_Save_Current_Base_Address_To_Start_OFF (26)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_Save_Current_Base_Address_To_Start_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_Save_Current_Base_Address_To_Start_MSK (0x04000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_Save_Current_Base_Address_To_Start_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_Save_Current_Base_Address_To_Start_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_Reset_Current_Base_Address_To_Start_OFF (27)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_Reset_Current_Base_Address_To_Start_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_Reset_Current_Base_Address_To_Start_MSK (0x08000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_Reset_Current_Base_Address_To_Start_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_Reset_Current_Base_Address_To_Start_DEF (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_Data_and_ECC_Address_Inversion_OFF (28)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_Data_and_ECC_Address_Inversion_WID ( 2)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_Data_and_ECC_Address_Inversion_MSK (0x30000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_Data_and_ECC_Address_Inversion_MAX (0x00000003)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_Data_and_ECC_Address_Inversion_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_Invert_Data_and_ECC_OFF (30)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_Invert_Data_and_ECC_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_Invert_Data_and_ECC_MSK (0x40000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_Invert_Data_and_ECC_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_Invert_Data_and_ECC_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_Stop_Base_Subsequence_On_Wrap_Trigger_OFF (31)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_Stop_Base_Subsequence_On_Wrap_Trigger_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_Stop_Base_Subsequence_On_Wrap_Trigger_MSK (0x80000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_Stop_Base_Subsequence_On_Wrap_Trigger_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_Stop_Base_Subsequence_On_Wrap_Trigger_DEF (0x00000000)
+
+#define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_REG                   (0x00004820)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Number_of_Cachelines_OFF ( 0)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Number_of_Cachelines_WID ( 7)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Number_of_Cachelines_MSK (0x0000007F)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Number_of_Cachelines_MAX (0x0000007F)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Number_of_Cachelines_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Number_of_Cachelines_Scale_OFF ( 7)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Number_of_Cachelines_Scale_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Number_of_Cachelines_Scale_MSK (0x00000080)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Number_of_Cachelines_Scale_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Number_of_Cachelines_Scale_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Subsequence_Wait_OFF  ( 8)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Subsequence_Wait_WID  (10)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Subsequence_Wait_MSK  (0x0003FF00)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Subsequence_Wait_MAX  (0x000003FF)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Subsequence_Wait_DEF  (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Subsequence_Type_OFF  (20)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Subsequence_Type_WID  ( 4)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Subsequence_Type_MSK  (0x00F00000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Subsequence_Type_MAX  (0x0000000F)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Subsequence_Type_DEF  (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Save_Current_Base_Address_To_Start_OFF (25)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Save_Current_Base_Address_To_Start_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Save_Current_Base_Address_To_Start_MSK (0x02000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Save_Current_Base_Address_To_Start_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Save_Current_Base_Address_To_Start_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Reset_Current_Base_Address_To_Start_OFF (26)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Reset_Current_Base_Address_To_Start_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Reset_Current_Base_Address_To_Start_MSK (0x04000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Reset_Current_Base_Address_To_Start_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Reset_Current_Base_Address_To_Start_DEF (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Data_and_ECC_Address_Inversion_OFF (27)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Data_and_ECC_Address_Inversion_WID ( 2)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Data_and_ECC_Address_Inversion_MSK (0x18000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Data_and_ECC_Address_Inversion_MAX (0x00000003)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Data_and_ECC_Address_Inversion_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Invert_Data_and_ECC_OFF (30)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Invert_Data_and_ECC_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Invert_Data_and_ECC_MSK (0x40000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Invert_Data_and_ECC_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Invert_Data_and_ECC_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_OFF (31)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_MSK (0x80000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_DEF (0x00000000)
+
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_Number_of_Cachelines_OFF ( 0)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_Number_of_Cachelines_WID ( 7)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_Number_of_Cachelines_MSK (0x0000007F)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_Number_of_Cachelines_MAX (0x0000007F)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_Number_of_Cachelines_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_Number_of_Cachelines_Scale_OFF ( 7)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_Number_of_Cachelines_Scale_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_Number_of_Cachelines_Scale_MSK (0x00000080)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_Number_of_Cachelines_Scale_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_Number_of_Cachelines_Scale_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_Subsequence_Wait_OFF  ( 8)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_Subsequence_Wait_WID  (14)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_Subsequence_Wait_MSK  (0x003FFF00)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_Subsequence_Wait_MAX  (0x00003FFF)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_Subsequence_Wait_DEF  (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_Subsequence_Type_OFF  (22)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_Subsequence_Type_WID  ( 4)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_Subsequence_Type_MSK  (0x03C00000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_Subsequence_Type_MAX  (0x0000000F)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_Subsequence_Type_DEF  (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_Save_Current_Base_Address_To_Start_OFF (26)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_Save_Current_Base_Address_To_Start_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_Save_Current_Base_Address_To_Start_MSK (0x04000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_Save_Current_Base_Address_To_Start_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_Save_Current_Base_Address_To_Start_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_Reset_Current_Base_Address_To_Start_OFF (27)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_Reset_Current_Base_Address_To_Start_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_Reset_Current_Base_Address_To_Start_MSK (0x08000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_Reset_Current_Base_Address_To_Start_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_Reset_Current_Base_Address_To_Start_DEF (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_Data_and_ECC_Address_Inversion_OFF (28)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_Data_and_ECC_Address_Inversion_WID ( 2)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_Data_and_ECC_Address_Inversion_MSK (0x30000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_Data_and_ECC_Address_Inversion_MAX (0x00000003)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_Data_and_ECC_Address_Inversion_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_Invert_Data_and_ECC_OFF (30)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_Invert_Data_and_ECC_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_Invert_Data_and_ECC_MSK (0x40000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_Invert_Data_and_ECC_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_Invert_Data_and_ECC_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_Stop_Base_Subsequence_On_Wrap_Trigger_OFF (31)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_Stop_Base_Subsequence_On_Wrap_Trigger_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_Stop_Base_Subsequence_On_Wrap_Trigger_MSK (0x80000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_Stop_Base_Subsequence_On_Wrap_Trigger_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_Stop_Base_Subsequence_On_Wrap_Trigger_DEF (0x00000000)
+
+#define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_REG                   (0x00004824)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Number_of_Cachelines_OFF ( 0)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Number_of_Cachelines_WID ( 7)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Number_of_Cachelines_MSK (0x0000007F)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Number_of_Cachelines_MAX (0x0000007F)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Number_of_Cachelines_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Number_of_Cachelines_Scale_OFF ( 7)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Number_of_Cachelines_Scale_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Number_of_Cachelines_Scale_MSK (0x00000080)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Number_of_Cachelines_Scale_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Number_of_Cachelines_Scale_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Subsequence_Wait_OFF  ( 8)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Subsequence_Wait_WID  (10)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Subsequence_Wait_MSK  (0x0003FF00)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Subsequence_Wait_MAX  (0x000003FF)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Subsequence_Wait_DEF  (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Subsequence_Type_OFF  (20)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Subsequence_Type_WID  ( 4)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Subsequence_Type_MSK  (0x00F00000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Subsequence_Type_MAX  (0x0000000F)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Subsequence_Type_DEF  (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Save_Current_Base_Address_To_Start_OFF (25)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Save_Current_Base_Address_To_Start_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Save_Current_Base_Address_To_Start_MSK (0x02000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Save_Current_Base_Address_To_Start_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Save_Current_Base_Address_To_Start_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Reset_Current_Base_Address_To_Start_OFF (26)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Reset_Current_Base_Address_To_Start_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Reset_Current_Base_Address_To_Start_MSK (0x04000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Reset_Current_Base_Address_To_Start_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Reset_Current_Base_Address_To_Start_DEF (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Data_and_ECC_Address_Inversion_OFF (27)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Data_and_ECC_Address_Inversion_WID ( 2)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Data_and_ECC_Address_Inversion_MSK (0x18000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Data_and_ECC_Address_Inversion_MAX (0x00000003)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Data_and_ECC_Address_Inversion_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Invert_Data_and_ECC_OFF (30)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Invert_Data_and_ECC_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Invert_Data_and_ECC_MSK (0x40000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Invert_Data_and_ECC_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Invert_Data_and_ECC_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_OFF (31)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_MSK (0x80000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_DEF (0x00000000)
+
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_Number_of_Cachelines_OFF ( 0)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_Number_of_Cachelines_WID ( 7)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_Number_of_Cachelines_MSK (0x0000007F)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_Number_of_Cachelines_MAX (0x0000007F)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_Number_of_Cachelines_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_Number_of_Cachelines_Scale_OFF ( 7)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_Number_of_Cachelines_Scale_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_Number_of_Cachelines_Scale_MSK (0x00000080)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_Number_of_Cachelines_Scale_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_Number_of_Cachelines_Scale_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_Subsequence_Wait_OFF  ( 8)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_Subsequence_Wait_WID  (14)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_Subsequence_Wait_MSK  (0x003FFF00)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_Subsequence_Wait_MAX  (0x00003FFF)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_Subsequence_Wait_DEF  (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_Subsequence_Type_OFF  (22)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_Subsequence_Type_WID  ( 4)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_Subsequence_Type_MSK  (0x03C00000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_Subsequence_Type_MAX  (0x0000000F)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_Subsequence_Type_DEF  (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_Save_Current_Base_Address_To_Start_OFF (26)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_Save_Current_Base_Address_To_Start_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_Save_Current_Base_Address_To_Start_MSK (0x04000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_Save_Current_Base_Address_To_Start_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_Save_Current_Base_Address_To_Start_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_Reset_Current_Base_Address_To_Start_OFF (27)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_Reset_Current_Base_Address_To_Start_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_Reset_Current_Base_Address_To_Start_MSK (0x08000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_Reset_Current_Base_Address_To_Start_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_Reset_Current_Base_Address_To_Start_DEF (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_Data_and_ECC_Address_Inversion_OFF (28)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_Data_and_ECC_Address_Inversion_WID ( 2)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_Data_and_ECC_Address_Inversion_MSK (0x30000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_Data_and_ECC_Address_Inversion_MAX (0x00000003)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_Data_and_ECC_Address_Inversion_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_Invert_Data_and_ECC_OFF (30)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_Invert_Data_and_ECC_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_Invert_Data_and_ECC_MSK (0x40000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_Invert_Data_and_ECC_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_Invert_Data_and_ECC_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_Stop_Base_Subsequence_On_Wrap_Trigger_OFF (31)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_Stop_Base_Subsequence_On_Wrap_Trigger_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_Stop_Base_Subsequence_On_Wrap_Trigger_MSK (0x80000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_Stop_Base_Subsequence_On_Wrap_Trigger_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_Stop_Base_Subsequence_On_Wrap_Trigger_DEF (0x00000000)
+
+#define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_REG                   (0x00004830)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Number_of_Cachelines_OFF ( 0)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Number_of_Cachelines_WID ( 7)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Number_of_Cachelines_MSK (0x0000007F)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Number_of_Cachelines_MAX (0x0000007F)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Number_of_Cachelines_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Number_of_Cachelines_Scale_OFF ( 7)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Number_of_Cachelines_Scale_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Number_of_Cachelines_Scale_MSK (0x00000080)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Number_of_Cachelines_Scale_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Number_of_Cachelines_Scale_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Subsequence_Wait_OFF  ( 8)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Subsequence_Wait_WID  ( 8)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Subsequence_Wait_MSK  (0x0000FF00)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Subsequence_Wait_MAX  (0x000000FF)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Subsequence_Wait_DEF  (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Subsequence_Type_OFF  (20)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Subsequence_Type_WID  ( 4)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Subsequence_Type_MSK  (0x00F00000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Subsequence_Type_MAX  (0x0000000F)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Subsequence_Type_DEF  (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Save_Current_Base_Address_To_Start_OFF (25)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Save_Current_Base_Address_To_Start_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Save_Current_Base_Address_To_Start_MSK (0x02000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Save_Current_Base_Address_To_Start_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Save_Current_Base_Address_To_Start_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Reset_Current_Base_Address_To_Start_OFF (26)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Reset_Current_Base_Address_To_Start_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Reset_Current_Base_Address_To_Start_MSK (0x04000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Reset_Current_Base_Address_To_Start_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Reset_Current_Base_Address_To_Start_DEF (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Data_and_ECC_Address_Inversion_OFF (27)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Data_and_ECC_Address_Inversion_WID ( 2)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Data_and_ECC_Address_Inversion_MSK (0x18000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Data_and_ECC_Address_Inversion_MAX (0x00000003)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Data_and_ECC_Address_Inversion_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Invert_Data_and_ECC_OFF (30)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Invert_Data_and_ECC_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Invert_Data_and_ECC_MSK (0x40000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Invert_Data_and_ECC_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Invert_Data_and_ECC_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_OFF (31)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_MSK (0x80000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_DEF (0x00000000)
+
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_Number_of_Cachelines_OFF ( 0)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_Number_of_Cachelines_WID ( 7)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_Number_of_Cachelines_MSK (0x0000007F)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_Number_of_Cachelines_MAX (0x0000007F)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_Number_of_Cachelines_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_Number_of_Cachelines_Scale_OFF ( 7)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_Number_of_Cachelines_Scale_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_Number_of_Cachelines_Scale_MSK (0x00000080)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_Number_of_Cachelines_Scale_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_Number_of_Cachelines_Scale_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_Subsequence_Wait_OFF  ( 8)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_Subsequence_Wait_WID  (14)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_Subsequence_Wait_MSK  (0x003FFF00)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_Subsequence_Wait_MAX  (0x00003FFF)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_Subsequence_Wait_DEF  (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_Subsequence_Type_OFF  (22)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_Subsequence_Type_WID  ( 4)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_Subsequence_Type_MSK  (0x03C00000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_Subsequence_Type_MAX  (0x0000000F)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_Subsequence_Type_DEF  (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_Save_Current_Base_Address_To_Start_OFF (26)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_Save_Current_Base_Address_To_Start_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_Save_Current_Base_Address_To_Start_MSK (0x04000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_Save_Current_Base_Address_To_Start_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_Save_Current_Base_Address_To_Start_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_Reset_Current_Base_Address_To_Start_OFF (27)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_Reset_Current_Base_Address_To_Start_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_Reset_Current_Base_Address_To_Start_MSK (0x08000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_Reset_Current_Base_Address_To_Start_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_Reset_Current_Base_Address_To_Start_DEF (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_Data_and_ECC_Address_Inversion_OFF (28)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_Data_and_ECC_Address_Inversion_WID ( 2)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_Data_and_ECC_Address_Inversion_MSK (0x30000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_Data_and_ECC_Address_Inversion_MAX (0x00000003)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_Data_and_ECC_Address_Inversion_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_Invert_Data_and_ECC_OFF (30)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_Invert_Data_and_ECC_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_Invert_Data_and_ECC_MSK (0x40000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_Invert_Data_and_ECC_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_Invert_Data_and_ECC_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_Stop_Base_Subsequence_On_Wrap_Trigger_OFF (31)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_Stop_Base_Subsequence_On_Wrap_Trigger_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_Stop_Base_Subsequence_On_Wrap_Trigger_MSK (0x80000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_Stop_Base_Subsequence_On_Wrap_Trigger_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_Stop_Base_Subsequence_On_Wrap_Trigger_DEF (0x00000000)
+
+#define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_REG                   (0x00004834)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Number_of_Cachelines_OFF ( 0)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Number_of_Cachelines_WID ( 7)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Number_of_Cachelines_MSK (0x0000007F)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Number_of_Cachelines_MAX (0x0000007F)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Number_of_Cachelines_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Number_of_Cachelines_Scale_OFF ( 7)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Number_of_Cachelines_Scale_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Number_of_Cachelines_Scale_MSK (0x00000080)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Number_of_Cachelines_Scale_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Number_of_Cachelines_Scale_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Subsequence_Wait_OFF  ( 8)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Subsequence_Wait_WID  ( 8)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Subsequence_Wait_MSK  (0x0000FF00)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Subsequence_Wait_MAX  (0x000000FF)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Subsequence_Wait_DEF  (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Subsequence_Type_OFF  (20)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Subsequence_Type_WID  ( 4)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Subsequence_Type_MSK  (0x00F00000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Subsequence_Type_MAX  (0x0000000F)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Subsequence_Type_DEF  (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Save_Current_Base_Address_To_Start_OFF (25)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Save_Current_Base_Address_To_Start_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Save_Current_Base_Address_To_Start_MSK (0x02000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Save_Current_Base_Address_To_Start_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Save_Current_Base_Address_To_Start_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Reset_Current_Base_Address_To_Start_OFF (26)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Reset_Current_Base_Address_To_Start_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Reset_Current_Base_Address_To_Start_MSK (0x04000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Reset_Current_Base_Address_To_Start_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Reset_Current_Base_Address_To_Start_DEF (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Data_and_ECC_Address_Inversion_OFF (27)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Data_and_ECC_Address_Inversion_WID ( 2)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Data_and_ECC_Address_Inversion_MSK (0x18000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Data_and_ECC_Address_Inversion_MAX (0x00000003)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Data_and_ECC_Address_Inversion_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Invert_Data_and_ECC_OFF (30)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Invert_Data_and_ECC_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Invert_Data_and_ECC_MSK (0x40000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Invert_Data_and_ECC_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Invert_Data_and_ECC_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_OFF (31)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_MSK (0x80000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_DEF (0x00000000)
+
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_Number_of_Cachelines_OFF ( 0)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_Number_of_Cachelines_WID ( 7)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_Number_of_Cachelines_MSK (0x0000007F)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_Number_of_Cachelines_MAX (0x0000007F)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_Number_of_Cachelines_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_Number_of_Cachelines_Scale_OFF ( 7)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_Number_of_Cachelines_Scale_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_Number_of_Cachelines_Scale_MSK (0x00000080)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_Number_of_Cachelines_Scale_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_Number_of_Cachelines_Scale_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_Subsequence_Wait_OFF  ( 8)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_Subsequence_Wait_WID  (14)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_Subsequence_Wait_MSK  (0x003FFF00)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_Subsequence_Wait_MAX  (0x00003FFF)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_Subsequence_Wait_DEF  (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_Subsequence_Type_OFF  (22)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_Subsequence_Type_WID  ( 4)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_Subsequence_Type_MSK  (0x03C00000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_Subsequence_Type_MAX  (0x0000000F)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_Subsequence_Type_DEF  (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_Save_Current_Base_Address_To_Start_OFF (26)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_Save_Current_Base_Address_To_Start_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_Save_Current_Base_Address_To_Start_MSK (0x04000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_Save_Current_Base_Address_To_Start_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_Save_Current_Base_Address_To_Start_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_Reset_Current_Base_Address_To_Start_OFF (27)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_Reset_Current_Base_Address_To_Start_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_Reset_Current_Base_Address_To_Start_MSK (0x08000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_Reset_Current_Base_Address_To_Start_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_Reset_Current_Base_Address_To_Start_DEF (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_Data_and_ECC_Address_Inversion_OFF (28)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_Data_and_ECC_Address_Inversion_WID ( 2)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_Data_and_ECC_Address_Inversion_MSK (0x30000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_Data_and_ECC_Address_Inversion_MAX (0x00000003)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_Data_and_ECC_Address_Inversion_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_Invert_Data_and_ECC_OFF (30)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_Invert_Data_and_ECC_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_Invert_Data_and_ECC_MSK (0x40000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_Invert_Data_and_ECC_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_Invert_Data_and_ECC_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_Stop_Base_Subsequence_On_Wrap_Trigger_OFF (31)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_Stop_Base_Subsequence_On_Wrap_Trigger_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_Stop_Base_Subsequence_On_Wrap_Trigger_MSK (0x80000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_Stop_Base_Subsequence_On_Wrap_Trigger_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_Stop_Base_Subsequence_On_Wrap_Trigger_DEF (0x00000000)
+
+#define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_REG                   (0x00004838)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Number_of_Cachelines_OFF ( 0)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Number_of_Cachelines_WID ( 7)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Number_of_Cachelines_MSK (0x0000007F)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Number_of_Cachelines_MAX (0x0000007F)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Number_of_Cachelines_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Number_of_Cachelines_Scale_OFF ( 7)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Number_of_Cachelines_Scale_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Number_of_Cachelines_Scale_MSK (0x00000080)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Number_of_Cachelines_Scale_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Number_of_Cachelines_Scale_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Subsequence_Wait_OFF  ( 8)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Subsequence_Wait_WID  ( 8)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Subsequence_Wait_MSK  (0x0000FF00)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Subsequence_Wait_MAX  (0x000000FF)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Subsequence_Wait_DEF  (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Subsequence_Type_OFF  (20)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Subsequence_Type_WID  ( 4)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Subsequence_Type_MSK  (0x00F00000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Subsequence_Type_MAX  (0x0000000F)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Subsequence_Type_DEF  (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Save_Current_Base_Address_To_Start_OFF (25)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Save_Current_Base_Address_To_Start_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Save_Current_Base_Address_To_Start_MSK (0x02000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Save_Current_Base_Address_To_Start_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Save_Current_Base_Address_To_Start_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Reset_Current_Base_Address_To_Start_OFF (26)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Reset_Current_Base_Address_To_Start_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Reset_Current_Base_Address_To_Start_MSK (0x04000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Reset_Current_Base_Address_To_Start_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Reset_Current_Base_Address_To_Start_DEF (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Data_and_ECC_Address_Inversion_OFF (27)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Data_and_ECC_Address_Inversion_WID ( 2)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Data_and_ECC_Address_Inversion_MSK (0x18000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Data_and_ECC_Address_Inversion_MAX (0x00000003)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Data_and_ECC_Address_Inversion_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Invert_Data_and_ECC_OFF (30)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Invert_Data_and_ECC_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Invert_Data_and_ECC_MSK (0x40000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Invert_Data_and_ECC_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Invert_Data_and_ECC_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_OFF (31)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_MSK (0x80000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_Stop_Base_Subsequence_On_Wrap_Trigger_DEF (0x00000000)
+
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_Number_of_Cachelines_OFF ( 0)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_Number_of_Cachelines_WID ( 7)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_Number_of_Cachelines_MSK (0x0000007F)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_Number_of_Cachelines_MAX (0x0000007F)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_Number_of_Cachelines_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_Number_of_Cachelines_Scale_OFF ( 7)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_Number_of_Cachelines_Scale_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_Number_of_Cachelines_Scale_MSK (0x00000080)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_Number_of_Cachelines_Scale_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_Number_of_Cachelines_Scale_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_Subsequence_Wait_OFF  ( 8)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_Subsequence_Wait_WID  (14)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_Subsequence_Wait_MSK  (0x003FFF00)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_Subsequence_Wait_MAX  (0x00003FFF)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_Subsequence_Wait_DEF  (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_Subsequence_Type_OFF  (22)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_Subsequence_Type_WID  ( 4)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_Subsequence_Type_MSK  (0x03C00000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_Subsequence_Type_MAX  (0x0000000F)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_Subsequence_Type_DEF  (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_Save_Current_Base_Address_To_Start_OFF (26)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_Save_Current_Base_Address_To_Start_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_Save_Current_Base_Address_To_Start_MSK (0x04000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_Save_Current_Base_Address_To_Start_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_Save_Current_Base_Address_To_Start_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_Reset_Current_Base_Address_To_Start_OFF (27)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_Reset_Current_Base_Address_To_Start_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_Reset_Current_Base_Address_To_Start_MSK (0x08000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_Reset_Current_Base_Address_To_Start_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_Reset_Current_Base_Address_To_Start_DEF (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_Data_and_ECC_Address_Inversion_OFF (28)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_Data_and_ECC_Address_Inversion_WID ( 2)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_Data_and_ECC_Address_Inversion_MSK (0x30000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_Data_and_ECC_Address_Inversion_MAX (0x00000003)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_Data_and_ECC_Address_Inversion_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_Invert_Data_and_ECC_OFF (30)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_Invert_Data_and_ECC_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_Invert_Data_and_ECC_MSK (0x40000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_Invert_Data_and_ECC_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_Invert_Data_and_ECC_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_Stop_Base_Subsequence_On_Wrap_Trigger_OFF (31)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_Stop_Base_Subsequence_On_Wrap_Trigger_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_Stop_Base_Subsequence_On_Wrap_Trigger_MSK (0x80000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_Stop_Base_Subsequence_On_Wrap_Trigger_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_Stop_Base_Subsequence_On_Wrap_Trigger_DEF (0x00000000)
+
+#define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_REG                   (0x0000483C)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Number_of_Cachelines_OFF ( 0)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Number_of_Cachelines_WID ( 7)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Number_of_Cachelines_MSK (0x0000007F)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Number_of_Cachelines_MAX (0x0000007F)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Number_of_Cachelines_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Number_of_Cachelines_Scale_OFF ( 7)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Number_of_Cachelines_Scale_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Number_of_Cachelines_Scale_MSK (0x00000080)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Number_of_Cachelines_Scale_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Number_of_Cachelines_Scale_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Subsequence_Wait_OFF  ( 8)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Subsequence_Wait_WID  ( 8)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Subsequence_Wait_MSK  (0x0000FF00)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Subsequence_Wait_MAX  (0x000000FF)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Subsequence_Wait_DEF  (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Subsequence_Type_OFF  (20)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Subsequence_Type_WID  ( 4)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Subsequence_Type_MSK  (0x00F00000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Subsequence_Type_MAX  (0x0000000F)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Subsequence_Type_DEF  (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Save_Current_Base_Address_To_Start_OFF (25)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Save_Current_Base_Address_To_Start_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Save_Current_Base_Address_To_Start_MSK (0x02000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Save_Current_Base_Address_To_Start_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Save_Current_Base_Address_To_Start_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Reset_Current_Base_Address_To_Start_OFF (26)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Reset_Current_Base_Address_To_Start_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Reset_Current_Base_Address_To_Start_MSK (0x04000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Reset_Current_Base_Address_To_Start_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Reset_Current_Base_Address_To_Start_DEF (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Data_and_ECC_Address_Inversion_OFF (27)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Data_and_ECC_Address_Inversion_WID ( 2)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Data_and_ECC_Address_Inversion_MSK (0x18000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Data_and_ECC_Address_Inversion_MAX (0x00000003)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Data_and_ECC_Address_Inversion_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Invert_Data_and_ECC_OFF (30)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Invert_Data_and_ECC_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Invert_Data_and_ECC_MSK (0x40000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Invert_Data_and_ECC_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Invert_Data_and_ECC_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_OFF (31)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_MSK (0x80000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_DEF (0x00000000)
+
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_Number_of_Cachelines_OFF ( 0)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_Number_of_Cachelines_WID ( 7)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_Number_of_Cachelines_MSK (0x0000007F)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_Number_of_Cachelines_MAX (0x0000007F)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_Number_of_Cachelines_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_Number_of_Cachelines_Scale_OFF ( 7)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_Number_of_Cachelines_Scale_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_Number_of_Cachelines_Scale_MSK (0x00000080)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_Number_of_Cachelines_Scale_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_Number_of_Cachelines_Scale_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_Subsequence_Wait_OFF  ( 8)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_Subsequence_Wait_WID  (14)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_Subsequence_Wait_MSK  (0x003FFF00)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_Subsequence_Wait_MAX  (0x00003FFF)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_Subsequence_Wait_DEF  (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_Subsequence_Type_OFF  (22)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_Subsequence_Type_WID  ( 4)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_Subsequence_Type_MSK  (0x03C00000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_Subsequence_Type_MAX  (0x0000000F)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_Subsequence_Type_DEF  (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_Save_Current_Base_Address_To_Start_OFF (26)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_Save_Current_Base_Address_To_Start_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_Save_Current_Base_Address_To_Start_MSK (0x04000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_Save_Current_Base_Address_To_Start_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_Save_Current_Base_Address_To_Start_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_Reset_Current_Base_Address_To_Start_OFF (27)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_Reset_Current_Base_Address_To_Start_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_Reset_Current_Base_Address_To_Start_MSK (0x08000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_Reset_Current_Base_Address_To_Start_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_Reset_Current_Base_Address_To_Start_DEF (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_Data_and_ECC_Address_Inversion_OFF (28)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_Data_and_ECC_Address_Inversion_WID ( 2)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_Data_and_ECC_Address_Inversion_MSK (0x30000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_Data_and_ECC_Address_Inversion_MAX (0x00000003)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_Data_and_ECC_Address_Inversion_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_Invert_Data_and_ECC_OFF (30)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_Invert_Data_and_ECC_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_Invert_Data_and_ECC_MSK (0x40000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_Invert_Data_and_ECC_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_Invert_Data_and_ECC_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_Stop_Base_Subsequence_On_Wrap_Trigger_OFF (31)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_Stop_Base_Subsequence_On_Wrap_Trigger_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_Stop_Base_Subsequence_On_Wrap_Trigger_MSK (0x80000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_Stop_Base_Subsequence_On_Wrap_Trigger_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_Stop_Base_Subsequence_On_Wrap_Trigger_DEF (0x00000000)
+
+#define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_REG                   (0x00004840)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Number_of_Cachelines_OFF ( 0)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Number_of_Cachelines_WID ( 7)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Number_of_Cachelines_MSK (0x0000007F)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Number_of_Cachelines_MAX (0x0000007F)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Number_of_Cachelines_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Number_of_Cachelines_Scale_OFF ( 7)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Number_of_Cachelines_Scale_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Number_of_Cachelines_Scale_MSK (0x00000080)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Number_of_Cachelines_Scale_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Number_of_Cachelines_Scale_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Subsequence_Wait_OFF  ( 8)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Subsequence_Wait_WID  ( 8)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Subsequence_Wait_MSK  (0x0000FF00)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Subsequence_Wait_MAX  (0x000000FF)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Subsequence_Wait_DEF  (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Subsequence_Type_OFF  (20)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Subsequence_Type_WID  ( 4)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Subsequence_Type_MSK  (0x00F00000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Subsequence_Type_MAX  (0x0000000F)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Subsequence_Type_DEF  (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Save_Current_Base_Address_To_Start_OFF (25)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Save_Current_Base_Address_To_Start_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Save_Current_Base_Address_To_Start_MSK (0x02000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Save_Current_Base_Address_To_Start_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Save_Current_Base_Address_To_Start_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Reset_Current_Base_Address_To_Start_OFF (26)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Reset_Current_Base_Address_To_Start_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Reset_Current_Base_Address_To_Start_MSK (0x04000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Reset_Current_Base_Address_To_Start_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Reset_Current_Base_Address_To_Start_DEF (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Data_and_ECC_Address_Inversion_OFF (27)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Data_and_ECC_Address_Inversion_WID ( 2)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Data_and_ECC_Address_Inversion_MSK (0x18000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Data_and_ECC_Address_Inversion_MAX (0x00000003)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Data_and_ECC_Address_Inversion_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Invert_Data_and_ECC_OFF (30)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Invert_Data_and_ECC_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Invert_Data_and_ECC_MSK (0x40000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Invert_Data_and_ECC_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Invert_Data_and_ECC_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_OFF (31)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_MSK (0x80000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_DEF (0x00000000)
+
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_Number_of_Cachelines_OFF ( 0)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_Number_of_Cachelines_WID ( 7)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_Number_of_Cachelines_MSK (0x0000007F)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_Number_of_Cachelines_MAX (0x0000007F)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_Number_of_Cachelines_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_Number_of_Cachelines_Scale_OFF ( 7)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_Number_of_Cachelines_Scale_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_Number_of_Cachelines_Scale_MSK (0x00000080)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_Number_of_Cachelines_Scale_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_Number_of_Cachelines_Scale_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_Subsequence_Wait_OFF  ( 8)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_Subsequence_Wait_WID  (14)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_Subsequence_Wait_MSK  (0x003FFF00)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_Subsequence_Wait_MAX  (0x00003FFF)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_Subsequence_Wait_DEF  (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_Subsequence_Type_OFF  (22)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_Subsequence_Type_WID  ( 4)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_Subsequence_Type_MSK  (0x03C00000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_Subsequence_Type_MAX  (0x0000000F)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_Subsequence_Type_DEF  (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_Save_Current_Base_Address_To_Start_OFF (26)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_Save_Current_Base_Address_To_Start_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_Save_Current_Base_Address_To_Start_MSK (0x04000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_Save_Current_Base_Address_To_Start_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_Save_Current_Base_Address_To_Start_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_Reset_Current_Base_Address_To_Start_OFF (27)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_Reset_Current_Base_Address_To_Start_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_Reset_Current_Base_Address_To_Start_MSK (0x08000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_Reset_Current_Base_Address_To_Start_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_Reset_Current_Base_Address_To_Start_DEF (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_Data_and_ECC_Address_Inversion_OFF (28)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_Data_and_ECC_Address_Inversion_WID ( 2)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_Data_and_ECC_Address_Inversion_MSK (0x30000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_Data_and_ECC_Address_Inversion_MAX (0x00000003)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_Data_and_ECC_Address_Inversion_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_Invert_Data_and_ECC_OFF (30)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_Invert_Data_and_ECC_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_Invert_Data_and_ECC_MSK (0x40000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_Invert_Data_and_ECC_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_Invert_Data_and_ECC_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_Stop_Base_Subsequence_On_Wrap_Trigger_OFF (31)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_Stop_Base_Subsequence_On_Wrap_Trigger_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_Stop_Base_Subsequence_On_Wrap_Trigger_MSK (0x80000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_Stop_Base_Subsequence_On_Wrap_Trigger_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_Stop_Base_Subsequence_On_Wrap_Trigger_DEF (0x00000000)
+
+#define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_REG                   (0x00004844)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Number_of_Cachelines_OFF ( 0)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Number_of_Cachelines_WID ( 7)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Number_of_Cachelines_MSK (0x0000007F)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Number_of_Cachelines_MAX (0x0000007F)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Number_of_Cachelines_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Number_of_Cachelines_Scale_OFF ( 7)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Number_of_Cachelines_Scale_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Number_of_Cachelines_Scale_MSK (0x00000080)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Number_of_Cachelines_Scale_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Number_of_Cachelines_Scale_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Subsequence_Wait_OFF  ( 8)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Subsequence_Wait_WID  ( 8)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Subsequence_Wait_MSK  (0x0000FF00)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Subsequence_Wait_MAX  (0x000000FF)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Subsequence_Wait_DEF  (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Subsequence_Type_OFF  (20)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Subsequence_Type_WID  ( 4)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Subsequence_Type_MSK  (0x00F00000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Subsequence_Type_MAX  (0x0000000F)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Subsequence_Type_DEF  (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Save_Current_Base_Address_To_Start_OFF (25)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Save_Current_Base_Address_To_Start_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Save_Current_Base_Address_To_Start_MSK (0x02000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Save_Current_Base_Address_To_Start_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Save_Current_Base_Address_To_Start_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Reset_Current_Base_Address_To_Start_OFF (26)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Reset_Current_Base_Address_To_Start_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Reset_Current_Base_Address_To_Start_MSK (0x04000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Reset_Current_Base_Address_To_Start_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Reset_Current_Base_Address_To_Start_DEF (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Data_and_ECC_Address_Inversion_OFF (27)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Data_and_ECC_Address_Inversion_WID ( 2)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Data_and_ECC_Address_Inversion_MSK (0x18000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Data_and_ECC_Address_Inversion_MAX (0x00000003)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Data_and_ECC_Address_Inversion_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Invert_Data_and_ECC_OFF (30)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Invert_Data_and_ECC_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Invert_Data_and_ECC_MSK (0x40000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Invert_Data_and_ECC_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Invert_Data_and_ECC_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_OFF (31)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_MSK (0x80000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_DEF (0x00000000)
+
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_Number_of_Cachelines_OFF ( 0)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_Number_of_Cachelines_WID ( 7)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_Number_of_Cachelines_MSK (0x0000007F)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_Number_of_Cachelines_MAX (0x0000007F)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_Number_of_Cachelines_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_Number_of_Cachelines_Scale_OFF ( 7)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_Number_of_Cachelines_Scale_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_Number_of_Cachelines_Scale_MSK (0x00000080)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_Number_of_Cachelines_Scale_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_Number_of_Cachelines_Scale_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_Subsequence_Wait_OFF  ( 8)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_Subsequence_Wait_WID  (14)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_Subsequence_Wait_MSK  (0x003FFF00)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_Subsequence_Wait_MAX  (0x00003FFF)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_Subsequence_Wait_DEF  (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_Subsequence_Type_OFF  (22)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_Subsequence_Type_WID  ( 4)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_Subsequence_Type_MSK  (0x03C00000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_Subsequence_Type_MAX  (0x0000000F)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_Subsequence_Type_DEF  (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_Save_Current_Base_Address_To_Start_OFF (26)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_Save_Current_Base_Address_To_Start_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_Save_Current_Base_Address_To_Start_MSK (0x04000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_Save_Current_Base_Address_To_Start_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_Save_Current_Base_Address_To_Start_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_Reset_Current_Base_Address_To_Start_OFF (27)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_Reset_Current_Base_Address_To_Start_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_Reset_Current_Base_Address_To_Start_MSK (0x08000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_Reset_Current_Base_Address_To_Start_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_Reset_Current_Base_Address_To_Start_DEF (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_Data_and_ECC_Address_Inversion_OFF (28)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_Data_and_ECC_Address_Inversion_WID ( 2)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_Data_and_ECC_Address_Inversion_MSK (0x30000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_Data_and_ECC_Address_Inversion_MAX (0x00000003)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_Data_and_ECC_Address_Inversion_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_Invert_Data_and_ECC_OFF (30)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_Invert_Data_and_ECC_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_Invert_Data_and_ECC_MSK (0x40000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_Invert_Data_and_ECC_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_Invert_Data_and_ECC_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_Stop_Base_Subsequence_On_Wrap_Trigger_OFF (31)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_Stop_Base_Subsequence_On_Wrap_Trigger_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_Stop_Base_Subsequence_On_Wrap_Trigger_MSK (0x80000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_Stop_Base_Subsequence_On_Wrap_Trigger_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_Stop_Base_Subsequence_On_Wrap_Trigger_DEF (0x00000000)
+
+#define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_REG                   (0x00004848)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Number_of_Cachelines_OFF ( 0)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Number_of_Cachelines_WID ( 7)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Number_of_Cachelines_MSK (0x0000007F)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Number_of_Cachelines_MAX (0x0000007F)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Number_of_Cachelines_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Number_of_Cachelines_Scale_OFF ( 7)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Number_of_Cachelines_Scale_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Number_of_Cachelines_Scale_MSK (0x00000080)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Number_of_Cachelines_Scale_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Number_of_Cachelines_Scale_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Subsequence_Wait_OFF  ( 8)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Subsequence_Wait_WID  ( 8)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Subsequence_Wait_MSK  (0x0000FF00)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Subsequence_Wait_MAX  (0x000000FF)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Subsequence_Wait_DEF  (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Subsequence_Type_OFF  (20)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Subsequence_Type_WID  ( 4)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Subsequence_Type_MSK  (0x00F00000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Subsequence_Type_MAX  (0x0000000F)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Subsequence_Type_DEF  (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Save_Current_Base_Address_To_Start_OFF (25)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Save_Current_Base_Address_To_Start_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Save_Current_Base_Address_To_Start_MSK (0x02000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Save_Current_Base_Address_To_Start_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Save_Current_Base_Address_To_Start_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Reset_Current_Base_Address_To_Start_OFF (26)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Reset_Current_Base_Address_To_Start_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Reset_Current_Base_Address_To_Start_MSK (0x04000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Reset_Current_Base_Address_To_Start_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Reset_Current_Base_Address_To_Start_DEF (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Data_and_ECC_Address_Inversion_OFF (27)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Data_and_ECC_Address_Inversion_WID ( 2)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Data_and_ECC_Address_Inversion_MSK (0x18000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Data_and_ECC_Address_Inversion_MAX (0x00000003)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Data_and_ECC_Address_Inversion_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Invert_Data_and_ECC_OFF (30)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Invert_Data_and_ECC_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Invert_Data_and_ECC_MSK (0x40000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Invert_Data_and_ECC_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Invert_Data_and_ECC_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_OFF (31)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_MSK (0x80000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_DEF (0x00000000)
+
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_Number_of_Cachelines_OFF ( 0)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_Number_of_Cachelines_WID ( 7)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_Number_of_Cachelines_MSK (0x0000007F)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_Number_of_Cachelines_MAX (0x0000007F)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_Number_of_Cachelines_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_Number_of_Cachelines_Scale_OFF ( 7)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_Number_of_Cachelines_Scale_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_Number_of_Cachelines_Scale_MSK (0x00000080)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_Number_of_Cachelines_Scale_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_Number_of_Cachelines_Scale_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_Subsequence_Wait_OFF  ( 8)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_Subsequence_Wait_WID  (14)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_Subsequence_Wait_MSK  (0x003FFF00)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_Subsequence_Wait_MAX  (0x00003FFF)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_Subsequence_Wait_DEF  (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_Subsequence_Type_OFF  (22)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_Subsequence_Type_WID  ( 4)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_Subsequence_Type_MSK  (0x03C00000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_Subsequence_Type_MAX  (0x0000000F)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_Subsequence_Type_DEF  (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_Save_Current_Base_Address_To_Start_OFF (26)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_Save_Current_Base_Address_To_Start_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_Save_Current_Base_Address_To_Start_MSK (0x04000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_Save_Current_Base_Address_To_Start_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_Save_Current_Base_Address_To_Start_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_Reset_Current_Base_Address_To_Start_OFF (27)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_Reset_Current_Base_Address_To_Start_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_Reset_Current_Base_Address_To_Start_MSK (0x08000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_Reset_Current_Base_Address_To_Start_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_Reset_Current_Base_Address_To_Start_DEF (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_Data_and_ECC_Address_Inversion_OFF (28)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_Data_and_ECC_Address_Inversion_WID ( 2)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_Data_and_ECC_Address_Inversion_MSK (0x30000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_Data_and_ECC_Address_Inversion_MAX (0x00000003)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_Data_and_ECC_Address_Inversion_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_Invert_Data_and_ECC_OFF (30)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_Invert_Data_and_ECC_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_Invert_Data_and_ECC_MSK (0x40000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_Invert_Data_and_ECC_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_Invert_Data_and_ECC_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_Stop_Base_Subsequence_On_Wrap_Trigger_OFF (31)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_Stop_Base_Subsequence_On_Wrap_Trigger_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_Stop_Base_Subsequence_On_Wrap_Trigger_MSK (0x80000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_Stop_Base_Subsequence_On_Wrap_Trigger_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_Stop_Base_Subsequence_On_Wrap_Trigger_DEF (0x00000000)
+
+#define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_REG                   (0x0000484C)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Number_of_Cachelines_OFF ( 0)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Number_of_Cachelines_WID ( 7)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Number_of_Cachelines_MSK (0x0000007F)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Number_of_Cachelines_MAX (0x0000007F)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Number_of_Cachelines_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Number_of_Cachelines_Scale_OFF ( 7)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Number_of_Cachelines_Scale_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Number_of_Cachelines_Scale_MSK (0x00000080)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Number_of_Cachelines_Scale_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Number_of_Cachelines_Scale_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Subsequence_Wait_OFF  ( 8)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Subsequence_Wait_WID  ( 8)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Subsequence_Wait_MSK  (0x0000FF00)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Subsequence_Wait_MAX  (0x000000FF)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Subsequence_Wait_DEF  (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Subsequence_Type_OFF  (20)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Subsequence_Type_WID  ( 4)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Subsequence_Type_MSK  (0x00F00000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Subsequence_Type_MAX  (0x0000000F)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Subsequence_Type_DEF  (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Save_Current_Base_Address_To_Start_OFF (25)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Save_Current_Base_Address_To_Start_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Save_Current_Base_Address_To_Start_MSK (0x02000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Save_Current_Base_Address_To_Start_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Save_Current_Base_Address_To_Start_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Reset_Current_Base_Address_To_Start_OFF (26)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Reset_Current_Base_Address_To_Start_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Reset_Current_Base_Address_To_Start_MSK (0x04000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Reset_Current_Base_Address_To_Start_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Reset_Current_Base_Address_To_Start_DEF (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Data_and_ECC_Address_Inversion_OFF (27)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Data_and_ECC_Address_Inversion_WID ( 2)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Data_and_ECC_Address_Inversion_MSK (0x18000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Data_and_ECC_Address_Inversion_MAX (0x00000003)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Data_and_ECC_Address_Inversion_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Invert_Data_and_ECC_OFF (30)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Invert_Data_and_ECC_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Invert_Data_and_ECC_MSK (0x40000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Invert_Data_and_ECC_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Invert_Data_and_ECC_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_OFF (31)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_MSK (0x80000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_DEF (0x00000000)
+
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_Number_of_Cachelines_OFF ( 0)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_Number_of_Cachelines_WID ( 7)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_Number_of_Cachelines_MSK (0x0000007F)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_Number_of_Cachelines_MAX (0x0000007F)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_Number_of_Cachelines_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_Number_of_Cachelines_Scale_OFF ( 7)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_Number_of_Cachelines_Scale_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_Number_of_Cachelines_Scale_MSK (0x00000080)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_Number_of_Cachelines_Scale_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_Number_of_Cachelines_Scale_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_Subsequence_Wait_OFF  ( 8)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_Subsequence_Wait_WID  (14)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_Subsequence_Wait_MSK  (0x003FFF00)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_Subsequence_Wait_MAX  (0x00003FFF)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_Subsequence_Wait_DEF  (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_Subsequence_Type_OFF  (22)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_Subsequence_Type_WID  ( 4)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_Subsequence_Type_MSK  (0x03C00000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_Subsequence_Type_MAX  (0x0000000F)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_Subsequence_Type_DEF  (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_Save_Current_Base_Address_To_Start_OFF (26)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_Save_Current_Base_Address_To_Start_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_Save_Current_Base_Address_To_Start_MSK (0x04000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_Save_Current_Base_Address_To_Start_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_Save_Current_Base_Address_To_Start_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_Reset_Current_Base_Address_To_Start_OFF (27)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_Reset_Current_Base_Address_To_Start_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_Reset_Current_Base_Address_To_Start_MSK (0x08000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_Reset_Current_Base_Address_To_Start_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_Reset_Current_Base_Address_To_Start_DEF (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_Data_and_ECC_Address_Inversion_OFF (28)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_Data_and_ECC_Address_Inversion_WID ( 2)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_Data_and_ECC_Address_Inversion_MSK (0x30000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_Data_and_ECC_Address_Inversion_MAX (0x00000003)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_Data_and_ECC_Address_Inversion_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_Invert_Data_and_ECC_OFF (30)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_Invert_Data_and_ECC_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_Invert_Data_and_ECC_MSK (0x40000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_Invert_Data_and_ECC_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_Invert_Data_and_ECC_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_Stop_Base_Subsequence_On_Wrap_Trigger_OFF (31)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_Stop_Base_Subsequence_On_Wrap_Trigger_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_Stop_Base_Subsequence_On_Wrap_Trigger_MSK (0x80000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_Stop_Base_Subsequence_On_Wrap_Trigger_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_Stop_Base_Subsequence_On_Wrap_Trigger_DEF (0x00000000)
+
+#define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_REG            (0x00004858)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_Offset_Address_Update_Rate_OFF ( 0)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_Offset_Address_Update_Rate_WID ( 5)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_Offset_Address_Update_Rate_MSK (0x0000001F)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_Offset_Address_Update_Rate_MAX (0x0000001F)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_Offset_Address_Update_Rate_DEF (0x00000002)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_Base_Subsequence_Repeat_Rate_OFF ( 8)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_Base_Subsequence_Repeat_Rate_WID ( 5)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_Base_Subsequence_Repeat_Rate_MSK (0x00001F00)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_Base_Subsequence_Repeat_Rate_MAX (0x0000001F)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_Base_Subsequence_Repeat_Rate_DEF (0x00000002)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_Column_Offset_Wrap_Trigger_Enable_OFF (15)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_Column_Offset_Wrap_Trigger_Enable_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_Column_Offset_Wrap_Trigger_Enable_MSK (0x00008000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_Column_Offset_Wrap_Trigger_Enable_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_Column_Offset_Wrap_Trigger_Enable_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_Row_Offset_Wrap_Trigger_Enable_OFF (16)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_Row_Offset_Wrap_Trigger_Enable_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_Row_Offset_Wrap_Trigger_Enable_MSK (0x00010000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_Row_Offset_Wrap_Trigger_Enable_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_Row_Offset_Wrap_Trigger_Enable_DEF (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_Base_Subsequence_Type_OFF (20)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_Base_Subsequence_Type_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_Base_Subsequence_Type_MSK (0x00100000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_Base_Subsequence_Type_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_Base_Subsequence_Type_DEF (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_CADB_Deselect_Enable_OFF (21)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_CADB_Deselect_Enable_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_CADB_Deselect_Enable_MSK (0x00200000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_CADB_Deselect_Enable_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_CADB_Deselect_Enable_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_CADB_Select_Enable_OFF (22)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_CADB_Select_Enable_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_CADB_Select_Enable_MSK (0x00400000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_CADB_Select_Enable_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_CADB_Select_Enable_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_CADB_Seeds_Save_Enable_OFF (23)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_CADB_Seeds_Save_Enable_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_CADB_Seeds_Save_Enable_MSK (0x00800000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_CADB_Seeds_Save_Enable_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_CADB_Seeds_Save_Enable_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_Column_Increment_Order_OFF (24)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_Column_Increment_Order_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_Column_Increment_Order_MSK (0x01000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_Column_Increment_Order_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_Column_Increment_Order_DEF (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_Column_Increment_Enable_OFF (26)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_Column_Increment_Enable_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_Column_Increment_Enable_MSK (0x04000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_Column_Increment_Enable_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_Column_Increment_Enable_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_Row_Increment_Order_OFF (27)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_Row_Increment_Order_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_Row_Increment_Order_MSK (0x08000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_Row_Increment_Order_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_Row_Increment_Order_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_Row_Increment_Enable_OFF (29)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_Row_Increment_Enable_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_Row_Increment_Enable_MSK (0x20000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_Row_Increment_Enable_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_Row_Increment_Enable_DEF (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_Base_Invert_Data_and_ECC_OFF (30)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_Base_Invert_Data_and_ECC_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_Base_Invert_Data_and_ECC_MSK (0x40000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_Base_Invert_Data_and_ECC_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_Base_Invert_Data_and_ECC_DEF (0x00000000)
+
+#define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_REG            (0x0000485C)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_Offset_Address_Update_Rate_OFF ( 0)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_Offset_Address_Update_Rate_WID ( 5)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_Offset_Address_Update_Rate_MSK (0x0000001F)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_Offset_Address_Update_Rate_MAX (0x0000001F)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_Offset_Address_Update_Rate_DEF (0x00000002)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_Base_Subsequence_Repeat_Rate_OFF ( 8)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_Base_Subsequence_Repeat_Rate_WID ( 5)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_Base_Subsequence_Repeat_Rate_MSK (0x00001F00)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_Base_Subsequence_Repeat_Rate_MAX (0x0000001F)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_Base_Subsequence_Repeat_Rate_DEF (0x00000002)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_Column_Offset_Wrap_Trigger_Enable_OFF (15)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_Column_Offset_Wrap_Trigger_Enable_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_Column_Offset_Wrap_Trigger_Enable_MSK (0x00008000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_Column_Offset_Wrap_Trigger_Enable_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_Column_Offset_Wrap_Trigger_Enable_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_Row_Offset_Wrap_Trigger_Enable_OFF (16)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_Row_Offset_Wrap_Trigger_Enable_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_Row_Offset_Wrap_Trigger_Enable_MSK (0x00010000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_Row_Offset_Wrap_Trigger_Enable_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_Row_Offset_Wrap_Trigger_Enable_DEF (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_Base_Subsequence_Type_OFF (20)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_Base_Subsequence_Type_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_Base_Subsequence_Type_MSK (0x00100000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_Base_Subsequence_Type_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_Base_Subsequence_Type_DEF (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_CADB_Deselect_Enable_OFF (21)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_CADB_Deselect_Enable_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_CADB_Deselect_Enable_MSK (0x00200000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_CADB_Deselect_Enable_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_CADB_Deselect_Enable_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_CADB_Select_Enable_OFF (22)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_CADB_Select_Enable_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_CADB_Select_Enable_MSK (0x00400000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_CADB_Select_Enable_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_CADB_Select_Enable_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_CADB_Seeds_Save_Enable_OFF (23)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_CADB_Seeds_Save_Enable_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_CADB_Seeds_Save_Enable_MSK (0x00800000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_CADB_Seeds_Save_Enable_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_CADB_Seeds_Save_Enable_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_Column_Increment_Order_OFF (24)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_Column_Increment_Order_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_Column_Increment_Order_MSK (0x01000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_Column_Increment_Order_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_Column_Increment_Order_DEF (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_Column_Increment_Enable_OFF (26)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_Column_Increment_Enable_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_Column_Increment_Enable_MSK (0x04000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_Column_Increment_Enable_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_Column_Increment_Enable_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_Row_Increment_Order_OFF (27)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_Row_Increment_Order_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_Row_Increment_Order_MSK (0x08000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_Row_Increment_Order_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_Row_Increment_Order_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_Row_Increment_Enable_OFF (29)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_Row_Increment_Enable_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_Row_Increment_Enable_MSK (0x20000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_Row_Increment_Enable_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_Row_Increment_Enable_DEF (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_Base_Invert_Data_and_ECC_OFF (30)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_Base_Invert_Data_and_ECC_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_Base_Invert_Data_and_ECC_MSK (0x40000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_Base_Invert_Data_and_ECC_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_Base_Invert_Data_and_ECC_DEF (0x00000000)
+
+#define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_REG            (0x00004860)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_Offset_Address_Update_Rate_OFF ( 0)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_Offset_Address_Update_Rate_WID ( 5)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_Offset_Address_Update_Rate_MSK (0x0000001F)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_Offset_Address_Update_Rate_MAX (0x0000001F)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_Offset_Address_Update_Rate_DEF (0x00000002)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_Base_Subsequence_Repeat_Rate_OFF ( 8)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_Base_Subsequence_Repeat_Rate_WID ( 5)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_Base_Subsequence_Repeat_Rate_MSK (0x00001F00)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_Base_Subsequence_Repeat_Rate_MAX (0x0000001F)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_Base_Subsequence_Repeat_Rate_DEF (0x00000002)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_Column_Offset_Wrap_Trigger_Enable_OFF (15)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_Column_Offset_Wrap_Trigger_Enable_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_Column_Offset_Wrap_Trigger_Enable_MSK (0x00008000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_Column_Offset_Wrap_Trigger_Enable_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_Column_Offset_Wrap_Trigger_Enable_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_Row_Offset_Wrap_Trigger_Enable_OFF (16)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_Row_Offset_Wrap_Trigger_Enable_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_Row_Offset_Wrap_Trigger_Enable_MSK (0x00010000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_Row_Offset_Wrap_Trigger_Enable_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_Row_Offset_Wrap_Trigger_Enable_DEF (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_Base_Subsequence_Type_OFF (20)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_Base_Subsequence_Type_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_Base_Subsequence_Type_MSK (0x00100000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_Base_Subsequence_Type_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_Base_Subsequence_Type_DEF (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_CADB_Deselect_Enable_OFF (21)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_CADB_Deselect_Enable_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_CADB_Deselect_Enable_MSK (0x00200000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_CADB_Deselect_Enable_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_CADB_Deselect_Enable_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_CADB_Select_Enable_OFF (22)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_CADB_Select_Enable_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_CADB_Select_Enable_MSK (0x00400000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_CADB_Select_Enable_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_CADB_Select_Enable_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_CADB_Seeds_Save_Enable_OFF (23)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_CADB_Seeds_Save_Enable_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_CADB_Seeds_Save_Enable_MSK (0x00800000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_CADB_Seeds_Save_Enable_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_CADB_Seeds_Save_Enable_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_Column_Increment_Order_OFF (24)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_Column_Increment_Order_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_Column_Increment_Order_MSK (0x01000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_Column_Increment_Order_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_Column_Increment_Order_DEF (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_Column_Increment_Enable_OFF (26)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_Column_Increment_Enable_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_Column_Increment_Enable_MSK (0x04000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_Column_Increment_Enable_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_Column_Increment_Enable_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_Row_Increment_Order_OFF (27)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_Row_Increment_Order_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_Row_Increment_Order_MSK (0x08000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_Row_Increment_Order_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_Row_Increment_Order_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_Row_Increment_Enable_OFF (29)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_Row_Increment_Enable_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_Row_Increment_Enable_MSK (0x20000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_Row_Increment_Enable_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_Row_Increment_Enable_DEF (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_Base_Invert_Data_and_ECC_OFF (30)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_Base_Invert_Data_and_ECC_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_Base_Invert_Data_and_ECC_MSK (0x40000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_Base_Invert_Data_and_ECC_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_Base_Invert_Data_and_ECC_DEF (0x00000000)
+
+#define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_REG            (0x00004864)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_Offset_Address_Update_Rate_OFF ( 0)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_Offset_Address_Update_Rate_WID ( 5)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_Offset_Address_Update_Rate_MSK (0x0000001F)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_Offset_Address_Update_Rate_MAX (0x0000001F)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_Offset_Address_Update_Rate_DEF (0x00000002)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_Base_Subsequence_Repeat_Rate_OFF ( 8)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_Base_Subsequence_Repeat_Rate_WID ( 5)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_Base_Subsequence_Repeat_Rate_MSK (0x00001F00)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_Base_Subsequence_Repeat_Rate_MAX (0x0000001F)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_Base_Subsequence_Repeat_Rate_DEF (0x00000002)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_Column_Offset_Wrap_Trigger_Enable_OFF (15)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_Column_Offset_Wrap_Trigger_Enable_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_Column_Offset_Wrap_Trigger_Enable_MSK (0x00008000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_Column_Offset_Wrap_Trigger_Enable_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_Column_Offset_Wrap_Trigger_Enable_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_Row_Offset_Wrap_Trigger_Enable_OFF (16)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_Row_Offset_Wrap_Trigger_Enable_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_Row_Offset_Wrap_Trigger_Enable_MSK (0x00010000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_Row_Offset_Wrap_Trigger_Enable_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_Row_Offset_Wrap_Trigger_Enable_DEF (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_Base_Subsequence_Type_OFF (20)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_Base_Subsequence_Type_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_Base_Subsequence_Type_MSK (0x00100000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_Base_Subsequence_Type_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_Base_Subsequence_Type_DEF (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_CADB_Deselect_Enable_OFF (21)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_CADB_Deselect_Enable_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_CADB_Deselect_Enable_MSK (0x00200000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_CADB_Deselect_Enable_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_CADB_Deselect_Enable_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_CADB_Select_Enable_OFF (22)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_CADB_Select_Enable_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_CADB_Select_Enable_MSK (0x00400000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_CADB_Select_Enable_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_CADB_Select_Enable_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_CADB_Seeds_Save_Enable_OFF (23)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_CADB_Seeds_Save_Enable_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_CADB_Seeds_Save_Enable_MSK (0x00800000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_CADB_Seeds_Save_Enable_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_CADB_Seeds_Save_Enable_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_Column_Increment_Order_OFF (24)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_Column_Increment_Order_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_Column_Increment_Order_MSK (0x01000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_Column_Increment_Order_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_Column_Increment_Order_DEF (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_Column_Increment_Enable_OFF (26)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_Column_Increment_Enable_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_Column_Increment_Enable_MSK (0x04000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_Column_Increment_Enable_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_Column_Increment_Enable_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_Row_Increment_Order_OFF (27)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_Row_Increment_Order_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_Row_Increment_Order_MSK (0x08000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_Row_Increment_Order_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_Row_Increment_Order_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_Row_Increment_Enable_OFF (29)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_Row_Increment_Enable_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_Row_Increment_Enable_MSK (0x20000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_Row_Increment_Enable_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_Row_Increment_Enable_DEF (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_Base_Invert_Data_and_ECC_OFF (30)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_Base_Invert_Data_and_ECC_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_Base_Invert_Data_and_ECC_MSK (0x40000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_Base_Invert_Data_and_ECC_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_Base_Invert_Data_and_ECC_DEF (0x00000000)
+
+#define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_REG            (0x00004868)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_Offset_Address_Update_Rate_OFF ( 0)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_Offset_Address_Update_Rate_WID ( 5)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_Offset_Address_Update_Rate_MSK (0x0000001F)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_Offset_Address_Update_Rate_MAX (0x0000001F)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_Offset_Address_Update_Rate_DEF (0x00000002)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_Base_Subsequence_Repeat_Rate_OFF ( 8)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_Base_Subsequence_Repeat_Rate_WID ( 5)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_Base_Subsequence_Repeat_Rate_MSK (0x00001F00)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_Base_Subsequence_Repeat_Rate_MAX (0x0000001F)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_Base_Subsequence_Repeat_Rate_DEF (0x00000002)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_Column_Offset_Wrap_Trigger_Enable_OFF (15)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_Column_Offset_Wrap_Trigger_Enable_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_Column_Offset_Wrap_Trigger_Enable_MSK (0x00008000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_Column_Offset_Wrap_Trigger_Enable_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_Column_Offset_Wrap_Trigger_Enable_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_Row_Offset_Wrap_Trigger_Enable_OFF (16)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_Row_Offset_Wrap_Trigger_Enable_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_Row_Offset_Wrap_Trigger_Enable_MSK (0x00010000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_Row_Offset_Wrap_Trigger_Enable_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_Row_Offset_Wrap_Trigger_Enable_DEF (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_Base_Subsequence_Type_OFF (20)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_Base_Subsequence_Type_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_Base_Subsequence_Type_MSK (0x00100000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_Base_Subsequence_Type_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_Base_Subsequence_Type_DEF (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_CADB_Deselect_Enable_OFF (21)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_CADB_Deselect_Enable_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_CADB_Deselect_Enable_MSK (0x00200000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_CADB_Deselect_Enable_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_CADB_Deselect_Enable_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_CADB_Select_Enable_OFF (22)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_CADB_Select_Enable_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_CADB_Select_Enable_MSK (0x00400000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_CADB_Select_Enable_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_CADB_Select_Enable_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_CADB_Seeds_Save_Enable_OFF (23)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_CADB_Seeds_Save_Enable_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_CADB_Seeds_Save_Enable_MSK (0x00800000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_CADB_Seeds_Save_Enable_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_CADB_Seeds_Save_Enable_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_Column_Increment_Order_OFF (24)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_Column_Increment_Order_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_Column_Increment_Order_MSK (0x01000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_Column_Increment_Order_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_Column_Increment_Order_DEF (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_Column_Increment_Enable_OFF (26)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_Column_Increment_Enable_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_Column_Increment_Enable_MSK (0x04000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_Column_Increment_Enable_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_Column_Increment_Enable_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_Row_Increment_Order_OFF (27)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_Row_Increment_Order_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_Row_Increment_Order_MSK (0x08000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_Row_Increment_Order_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_Row_Increment_Order_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_Row_Increment_Enable_OFF (29)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_Row_Increment_Enable_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_Row_Increment_Enable_MSK (0x20000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_Row_Increment_Enable_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_Row_Increment_Enable_DEF (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_Base_Invert_Data_and_ECC_OFF (30)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_Base_Invert_Data_and_ECC_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_Base_Invert_Data_and_ECC_MSK (0x40000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_Base_Invert_Data_and_ECC_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_Base_Invert_Data_and_ECC_DEF (0x00000000)
+
+#define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_REG            (0x0000486C)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_Offset_Address_Update_Rate_OFF ( 0)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_Offset_Address_Update_Rate_WID ( 5)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_Offset_Address_Update_Rate_MSK (0x0000001F)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_Offset_Address_Update_Rate_MAX (0x0000001F)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_Offset_Address_Update_Rate_DEF (0x00000002)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_Base_Subsequence_Repeat_Rate_OFF ( 8)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_Base_Subsequence_Repeat_Rate_WID ( 5)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_Base_Subsequence_Repeat_Rate_MSK (0x00001F00)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_Base_Subsequence_Repeat_Rate_MAX (0x0000001F)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_Base_Subsequence_Repeat_Rate_DEF (0x00000002)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_Column_Offset_Wrap_Trigger_Enable_OFF (15)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_Column_Offset_Wrap_Trigger_Enable_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_Column_Offset_Wrap_Trigger_Enable_MSK (0x00008000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_Column_Offset_Wrap_Trigger_Enable_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_Column_Offset_Wrap_Trigger_Enable_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_Row_Offset_Wrap_Trigger_Enable_OFF (16)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_Row_Offset_Wrap_Trigger_Enable_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_Row_Offset_Wrap_Trigger_Enable_MSK (0x00010000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_Row_Offset_Wrap_Trigger_Enable_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_Row_Offset_Wrap_Trigger_Enable_DEF (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_Base_Subsequence_Type_OFF (20)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_Base_Subsequence_Type_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_Base_Subsequence_Type_MSK (0x00100000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_Base_Subsequence_Type_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_Base_Subsequence_Type_DEF (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_CADB_Deselect_Enable_OFF (21)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_CADB_Deselect_Enable_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_CADB_Deselect_Enable_MSK (0x00200000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_CADB_Deselect_Enable_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_CADB_Deselect_Enable_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_CADB_Select_Enable_OFF (22)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_CADB_Select_Enable_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_CADB_Select_Enable_MSK (0x00400000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_CADB_Select_Enable_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_CADB_Select_Enable_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_CADB_Seeds_Save_Enable_OFF (23)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_CADB_Seeds_Save_Enable_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_CADB_Seeds_Save_Enable_MSK (0x00800000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_CADB_Seeds_Save_Enable_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_CADB_Seeds_Save_Enable_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_Column_Increment_Order_OFF (24)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_Column_Increment_Order_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_Column_Increment_Order_MSK (0x01000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_Column_Increment_Order_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_Column_Increment_Order_DEF (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_Column_Increment_Enable_OFF (26)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_Column_Increment_Enable_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_Column_Increment_Enable_MSK (0x04000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_Column_Increment_Enable_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_Column_Increment_Enable_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_Row_Increment_Order_OFF (27)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_Row_Increment_Order_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_Row_Increment_Order_MSK (0x08000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_Row_Increment_Order_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_Row_Increment_Order_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_Row_Increment_Enable_OFF (29)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_Row_Increment_Enable_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_Row_Increment_Enable_MSK (0x20000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_Row_Increment_Enable_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_Row_Increment_Enable_DEF (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_Base_Invert_Data_and_ECC_OFF (30)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_Base_Invert_Data_and_ECC_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_Base_Invert_Data_and_ECC_MSK (0x40000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_Base_Invert_Data_and_ECC_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_Base_Invert_Data_and_ECC_DEF (0x00000000)
+
+#define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_REG            (0x00004870)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_Offset_Address_Update_Rate_OFF ( 0)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_Offset_Address_Update_Rate_WID ( 5)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_Offset_Address_Update_Rate_MSK (0x0000001F)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_Offset_Address_Update_Rate_MAX (0x0000001F)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_Offset_Address_Update_Rate_DEF (0x00000002)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_Base_Subsequence_Repeat_Rate_OFF ( 8)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_Base_Subsequence_Repeat_Rate_WID ( 5)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_Base_Subsequence_Repeat_Rate_MSK (0x00001F00)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_Base_Subsequence_Repeat_Rate_MAX (0x0000001F)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_Base_Subsequence_Repeat_Rate_DEF (0x00000002)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_Column_Offset_Wrap_Trigger_Enable_OFF (15)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_Column_Offset_Wrap_Trigger_Enable_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_Column_Offset_Wrap_Trigger_Enable_MSK (0x00008000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_Column_Offset_Wrap_Trigger_Enable_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_Column_Offset_Wrap_Trigger_Enable_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_Row_Offset_Wrap_Trigger_Enable_OFF (16)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_Row_Offset_Wrap_Trigger_Enable_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_Row_Offset_Wrap_Trigger_Enable_MSK (0x00010000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_Row_Offset_Wrap_Trigger_Enable_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_Row_Offset_Wrap_Trigger_Enable_DEF (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_Base_Subsequence_Type_OFF (20)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_Base_Subsequence_Type_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_Base_Subsequence_Type_MSK (0x00100000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_Base_Subsequence_Type_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_Base_Subsequence_Type_DEF (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_CADB_Deselect_Enable_OFF (21)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_CADB_Deselect_Enable_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_CADB_Deselect_Enable_MSK (0x00200000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_CADB_Deselect_Enable_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_CADB_Deselect_Enable_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_CADB_Select_Enable_OFF (22)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_CADB_Select_Enable_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_CADB_Select_Enable_MSK (0x00400000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_CADB_Select_Enable_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_CADB_Select_Enable_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_CADB_Seeds_Save_Enable_OFF (23)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_CADB_Seeds_Save_Enable_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_CADB_Seeds_Save_Enable_MSK (0x00800000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_CADB_Seeds_Save_Enable_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_CADB_Seeds_Save_Enable_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_Column_Increment_Order_OFF (24)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_Column_Increment_Order_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_Column_Increment_Order_MSK (0x01000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_Column_Increment_Order_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_Column_Increment_Order_DEF (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_Column_Increment_Enable_OFF (26)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_Column_Increment_Enable_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_Column_Increment_Enable_MSK (0x04000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_Column_Increment_Enable_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_Column_Increment_Enable_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_Row_Increment_Order_OFF (27)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_Row_Increment_Order_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_Row_Increment_Order_MSK (0x08000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_Row_Increment_Order_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_Row_Increment_Order_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_Row_Increment_Enable_OFF (29)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_Row_Increment_Enable_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_Row_Increment_Enable_MSK (0x20000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_Row_Increment_Enable_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_Row_Increment_Enable_DEF (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_Base_Invert_Data_and_ECC_OFF (30)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_Base_Invert_Data_and_ECC_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_Base_Invert_Data_and_ECC_MSK (0x40000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_Base_Invert_Data_and_ECC_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_Base_Invert_Data_and_ECC_DEF (0x00000000)
+
+#define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_REG            (0x00004874)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_Offset_Address_Update_Rate_OFF ( 0)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_Offset_Address_Update_Rate_WID ( 5)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_Offset_Address_Update_Rate_MSK (0x0000001F)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_Offset_Address_Update_Rate_MAX (0x0000001F)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_Offset_Address_Update_Rate_DEF (0x00000002)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_Base_Subsequence_Repeat_Rate_OFF ( 8)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_Base_Subsequence_Repeat_Rate_WID ( 5)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_Base_Subsequence_Repeat_Rate_MSK (0x00001F00)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_Base_Subsequence_Repeat_Rate_MAX (0x0000001F)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_Base_Subsequence_Repeat_Rate_DEF (0x00000002)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_Column_Offset_Wrap_Trigger_Enable_OFF (15)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_Column_Offset_Wrap_Trigger_Enable_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_Column_Offset_Wrap_Trigger_Enable_MSK (0x00008000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_Column_Offset_Wrap_Trigger_Enable_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_Column_Offset_Wrap_Trigger_Enable_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_Row_Offset_Wrap_Trigger_Enable_OFF (16)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_Row_Offset_Wrap_Trigger_Enable_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_Row_Offset_Wrap_Trigger_Enable_MSK (0x00010000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_Row_Offset_Wrap_Trigger_Enable_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_Row_Offset_Wrap_Trigger_Enable_DEF (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_Base_Subsequence_Type_OFF (20)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_Base_Subsequence_Type_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_Base_Subsequence_Type_MSK (0x00100000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_Base_Subsequence_Type_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_Base_Subsequence_Type_DEF (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_CADB_Deselect_Enable_OFF (21)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_CADB_Deselect_Enable_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_CADB_Deselect_Enable_MSK (0x00200000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_CADB_Deselect_Enable_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_CADB_Deselect_Enable_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_CADB_Select_Enable_OFF (22)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_CADB_Select_Enable_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_CADB_Select_Enable_MSK (0x00400000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_CADB_Select_Enable_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_CADB_Select_Enable_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_CADB_Seeds_Save_Enable_OFF (23)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_CADB_Seeds_Save_Enable_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_CADB_Seeds_Save_Enable_MSK (0x00800000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_CADB_Seeds_Save_Enable_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_CADB_Seeds_Save_Enable_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_Column_Increment_Order_OFF (24)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_Column_Increment_Order_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_Column_Increment_Order_MSK (0x01000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_Column_Increment_Order_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_Column_Increment_Order_DEF (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_Column_Increment_Enable_OFF (26)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_Column_Increment_Enable_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_Column_Increment_Enable_MSK (0x04000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_Column_Increment_Enable_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_Column_Increment_Enable_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_Row_Increment_Order_OFF (27)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_Row_Increment_Order_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_Row_Increment_Order_MSK (0x08000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_Row_Increment_Order_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_Row_Increment_Order_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_Row_Increment_Enable_OFF (29)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_Row_Increment_Enable_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_Row_Increment_Enable_MSK (0x20000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_Row_Increment_Enable_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_Row_Increment_Enable_DEF (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_Base_Invert_Data_and_ECC_OFF (30)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_Base_Invert_Data_and_ECC_WID ( 1)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_Base_Invert_Data_and_ECC_MSK (0x40000000)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_Base_Invert_Data_and_ECC_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_Base_Invert_Data_and_ECC_DEF (0x00000000)
+
+#define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_REG            (0x00004880)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_Offset_Address_Update_Rate_OFF ( 0)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_Offset_Address_Update_Rate_WID ( 5)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_Offset_Address_Update_Rate_MSK (0x0000001F)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_Offset_Address_Update_Rate_MAX (0x0000001F)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_Offset_Address_Update_Rate_DEF (0x00000002)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_Base_Subsequence_Repeat_Rate_OFF ( 8)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_Base_Subsequence_Repeat_Rate_WID ( 5)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_Base_Subsequence_Repeat_Rate_MSK (0x00001F00)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_Base_Subsequence_Repeat_Rate_MAX (0x0000001F)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_Base_Subsequence_Repeat_Rate_DEF (0x00000002)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_Column_Offset_Wrap_Trigger_Enable_OFF (15)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_Column_Offset_Wrap_Trigger_Enable_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_Column_Offset_Wrap_Trigger_Enable_MSK (0x00008000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_Column_Offset_Wrap_Trigger_Enable_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_Column_Offset_Wrap_Trigger_Enable_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_Row_Offset_Wrap_Trigger_Enable_OFF (16)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_Row_Offset_Wrap_Trigger_Enable_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_Row_Offset_Wrap_Trigger_Enable_MSK (0x00010000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_Row_Offset_Wrap_Trigger_Enable_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_Row_Offset_Wrap_Trigger_Enable_DEF (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_Base_Subsequence_Type_OFF (20)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_Base_Subsequence_Type_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_Base_Subsequence_Type_MSK (0x00100000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_Base_Subsequence_Type_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_Base_Subsequence_Type_DEF (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_CADB_Deselect_Enable_OFF (21)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_CADB_Deselect_Enable_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_CADB_Deselect_Enable_MSK (0x00200000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_CADB_Deselect_Enable_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_CADB_Deselect_Enable_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_CADB_Select_Enable_OFF (22)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_CADB_Select_Enable_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_CADB_Select_Enable_MSK (0x00400000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_CADB_Select_Enable_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_CADB_Select_Enable_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_CADB_Seeds_Save_Enable_OFF (23)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_CADB_Seeds_Save_Enable_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_CADB_Seeds_Save_Enable_MSK (0x00800000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_CADB_Seeds_Save_Enable_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_CADB_Seeds_Save_Enable_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_Column_Increment_Order_OFF (24)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_Column_Increment_Order_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_Column_Increment_Order_MSK (0x01000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_Column_Increment_Order_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_Column_Increment_Order_DEF (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_Column_Increment_Enable_OFF (26)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_Column_Increment_Enable_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_Column_Increment_Enable_MSK (0x04000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_Column_Increment_Enable_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_Column_Increment_Enable_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_Row_Increment_Order_OFF (27)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_Row_Increment_Order_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_Row_Increment_Order_MSK (0x08000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_Row_Increment_Order_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_Row_Increment_Order_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_Row_Increment_Enable_OFF (29)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_Row_Increment_Enable_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_Row_Increment_Enable_MSK (0x20000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_Row_Increment_Enable_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_Row_Increment_Enable_DEF (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_Base_Invert_Data_and_ECC_OFF (30)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_Base_Invert_Data_and_ECC_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_Base_Invert_Data_and_ECC_MSK (0x40000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_Base_Invert_Data_and_ECC_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_Base_Invert_Data_and_ECC_DEF (0x00000000)
+
+#define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_REG            (0x00004884)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_Offset_Address_Update_Rate_OFF ( 0)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_Offset_Address_Update_Rate_WID ( 5)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_Offset_Address_Update_Rate_MSK (0x0000001F)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_Offset_Address_Update_Rate_MAX (0x0000001F)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_Offset_Address_Update_Rate_DEF (0x00000002)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_Base_Subsequence_Repeat_Rate_OFF ( 8)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_Base_Subsequence_Repeat_Rate_WID ( 5)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_Base_Subsequence_Repeat_Rate_MSK (0x00001F00)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_Base_Subsequence_Repeat_Rate_MAX (0x0000001F)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_Base_Subsequence_Repeat_Rate_DEF (0x00000002)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_Column_Offset_Wrap_Trigger_Enable_OFF (15)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_Column_Offset_Wrap_Trigger_Enable_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_Column_Offset_Wrap_Trigger_Enable_MSK (0x00008000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_Column_Offset_Wrap_Trigger_Enable_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_Column_Offset_Wrap_Trigger_Enable_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_Row_Offset_Wrap_Trigger_Enable_OFF (16)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_Row_Offset_Wrap_Trigger_Enable_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_Row_Offset_Wrap_Trigger_Enable_MSK (0x00010000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_Row_Offset_Wrap_Trigger_Enable_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_Row_Offset_Wrap_Trigger_Enable_DEF (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_Base_Subsequence_Type_OFF (20)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_Base_Subsequence_Type_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_Base_Subsequence_Type_MSK (0x00100000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_Base_Subsequence_Type_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_Base_Subsequence_Type_DEF (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_CADB_Deselect_Enable_OFF (21)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_CADB_Deselect_Enable_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_CADB_Deselect_Enable_MSK (0x00200000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_CADB_Deselect_Enable_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_CADB_Deselect_Enable_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_CADB_Select_Enable_OFF (22)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_CADB_Select_Enable_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_CADB_Select_Enable_MSK (0x00400000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_CADB_Select_Enable_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_CADB_Select_Enable_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_CADB_Seeds_Save_Enable_OFF (23)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_CADB_Seeds_Save_Enable_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_CADB_Seeds_Save_Enable_MSK (0x00800000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_CADB_Seeds_Save_Enable_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_CADB_Seeds_Save_Enable_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_Column_Increment_Order_OFF (24)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_Column_Increment_Order_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_Column_Increment_Order_MSK (0x01000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_Column_Increment_Order_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_Column_Increment_Order_DEF (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_Column_Increment_Enable_OFF (26)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_Column_Increment_Enable_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_Column_Increment_Enable_MSK (0x04000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_Column_Increment_Enable_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_Column_Increment_Enable_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_Row_Increment_Order_OFF (27)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_Row_Increment_Order_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_Row_Increment_Order_MSK (0x08000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_Row_Increment_Order_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_Row_Increment_Order_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_Row_Increment_Enable_OFF (29)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_Row_Increment_Enable_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_Row_Increment_Enable_MSK (0x20000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_Row_Increment_Enable_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_Row_Increment_Enable_DEF (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_Base_Invert_Data_and_ECC_OFF (30)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_Base_Invert_Data_and_ECC_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_Base_Invert_Data_and_ECC_MSK (0x40000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_Base_Invert_Data_and_ECC_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_Base_Invert_Data_and_ECC_DEF (0x00000000)
+
+#define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_REG            (0x00004888)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_Offset_Address_Update_Rate_OFF ( 0)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_Offset_Address_Update_Rate_WID ( 5)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_Offset_Address_Update_Rate_MSK (0x0000001F)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_Offset_Address_Update_Rate_MAX (0x0000001F)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_Offset_Address_Update_Rate_DEF (0x00000002)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_Base_Subsequence_Repeat_Rate_OFF ( 8)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_Base_Subsequence_Repeat_Rate_WID ( 5)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_Base_Subsequence_Repeat_Rate_MSK (0x00001F00)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_Base_Subsequence_Repeat_Rate_MAX (0x0000001F)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_Base_Subsequence_Repeat_Rate_DEF (0x00000002)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_Column_Offset_Wrap_Trigger_Enable_OFF (15)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_Column_Offset_Wrap_Trigger_Enable_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_Column_Offset_Wrap_Trigger_Enable_MSK (0x00008000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_Column_Offset_Wrap_Trigger_Enable_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_Column_Offset_Wrap_Trigger_Enable_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_Row_Offset_Wrap_Trigger_Enable_OFF (16)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_Row_Offset_Wrap_Trigger_Enable_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_Row_Offset_Wrap_Trigger_Enable_MSK (0x00010000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_Row_Offset_Wrap_Trigger_Enable_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_Row_Offset_Wrap_Trigger_Enable_DEF (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_Base_Subsequence_Type_OFF (20)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_Base_Subsequence_Type_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_Base_Subsequence_Type_MSK (0x00100000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_Base_Subsequence_Type_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_Base_Subsequence_Type_DEF (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_CADB_Deselect_Enable_OFF (21)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_CADB_Deselect_Enable_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_CADB_Deselect_Enable_MSK (0x00200000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_CADB_Deselect_Enable_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_CADB_Deselect_Enable_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_CADB_Select_Enable_OFF (22)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_CADB_Select_Enable_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_CADB_Select_Enable_MSK (0x00400000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_CADB_Select_Enable_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_CADB_Select_Enable_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_CADB_Seeds_Save_Enable_OFF (23)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_CADB_Seeds_Save_Enable_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_CADB_Seeds_Save_Enable_MSK (0x00800000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_CADB_Seeds_Save_Enable_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_CADB_Seeds_Save_Enable_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_Column_Increment_Order_OFF (24)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_Column_Increment_Order_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_Column_Increment_Order_MSK (0x01000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_Column_Increment_Order_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_Column_Increment_Order_DEF (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_Column_Increment_Enable_OFF (26)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_Column_Increment_Enable_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_Column_Increment_Enable_MSK (0x04000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_Column_Increment_Enable_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_Column_Increment_Enable_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_Row_Increment_Order_OFF (27)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_Row_Increment_Order_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_Row_Increment_Order_MSK (0x08000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_Row_Increment_Order_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_Row_Increment_Order_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_Row_Increment_Enable_OFF (29)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_Row_Increment_Enable_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_Row_Increment_Enable_MSK (0x20000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_Row_Increment_Enable_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_Row_Increment_Enable_DEF (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_Base_Invert_Data_and_ECC_OFF (30)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_Base_Invert_Data_and_ECC_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_Base_Invert_Data_and_ECC_MSK (0x40000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_Base_Invert_Data_and_ECC_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_Base_Invert_Data_and_ECC_DEF (0x00000000)
+
+#define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_REG            (0x0000488C)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_Offset_Address_Update_Rate_OFF ( 0)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_Offset_Address_Update_Rate_WID ( 5)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_Offset_Address_Update_Rate_MSK (0x0000001F)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_Offset_Address_Update_Rate_MAX (0x0000001F)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_Offset_Address_Update_Rate_DEF (0x00000002)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_Base_Subsequence_Repeat_Rate_OFF ( 8)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_Base_Subsequence_Repeat_Rate_WID ( 5)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_Base_Subsequence_Repeat_Rate_MSK (0x00001F00)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_Base_Subsequence_Repeat_Rate_MAX (0x0000001F)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_Base_Subsequence_Repeat_Rate_DEF (0x00000002)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_Column_Offset_Wrap_Trigger_Enable_OFF (15)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_Column_Offset_Wrap_Trigger_Enable_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_Column_Offset_Wrap_Trigger_Enable_MSK (0x00008000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_Column_Offset_Wrap_Trigger_Enable_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_Column_Offset_Wrap_Trigger_Enable_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_Row_Offset_Wrap_Trigger_Enable_OFF (16)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_Row_Offset_Wrap_Trigger_Enable_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_Row_Offset_Wrap_Trigger_Enable_MSK (0x00010000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_Row_Offset_Wrap_Trigger_Enable_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_Row_Offset_Wrap_Trigger_Enable_DEF (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_Base_Subsequence_Type_OFF (20)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_Base_Subsequence_Type_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_Base_Subsequence_Type_MSK (0x00100000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_Base_Subsequence_Type_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_Base_Subsequence_Type_DEF (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_CADB_Deselect_Enable_OFF (21)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_CADB_Deselect_Enable_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_CADB_Deselect_Enable_MSK (0x00200000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_CADB_Deselect_Enable_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_CADB_Deselect_Enable_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_CADB_Select_Enable_OFF (22)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_CADB_Select_Enable_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_CADB_Select_Enable_MSK (0x00400000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_CADB_Select_Enable_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_CADB_Select_Enable_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_CADB_Seeds_Save_Enable_OFF (23)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_CADB_Seeds_Save_Enable_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_CADB_Seeds_Save_Enable_MSK (0x00800000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_CADB_Seeds_Save_Enable_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_CADB_Seeds_Save_Enable_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_Column_Increment_Order_OFF (24)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_Column_Increment_Order_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_Column_Increment_Order_MSK (0x01000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_Column_Increment_Order_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_Column_Increment_Order_DEF (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_Column_Increment_Enable_OFF (26)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_Column_Increment_Enable_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_Column_Increment_Enable_MSK (0x04000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_Column_Increment_Enable_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_Column_Increment_Enable_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_Row_Increment_Order_OFF (27)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_Row_Increment_Order_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_Row_Increment_Order_MSK (0x08000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_Row_Increment_Order_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_Row_Increment_Order_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_Row_Increment_Enable_OFF (29)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_Row_Increment_Enable_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_Row_Increment_Enable_MSK (0x20000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_Row_Increment_Enable_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_Row_Increment_Enable_DEF (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_Base_Invert_Data_and_ECC_OFF (30)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_Base_Invert_Data_and_ECC_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_Base_Invert_Data_and_ECC_MSK (0x40000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_Base_Invert_Data_and_ECC_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_Base_Invert_Data_and_ECC_DEF (0x00000000)
+
+#define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_REG            (0x00004890)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_Offset_Address_Update_Rate_OFF ( 0)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_Offset_Address_Update_Rate_WID ( 5)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_Offset_Address_Update_Rate_MSK (0x0000001F)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_Offset_Address_Update_Rate_MAX (0x0000001F)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_Offset_Address_Update_Rate_DEF (0x00000002)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_Base_Subsequence_Repeat_Rate_OFF ( 8)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_Base_Subsequence_Repeat_Rate_WID ( 5)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_Base_Subsequence_Repeat_Rate_MSK (0x00001F00)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_Base_Subsequence_Repeat_Rate_MAX (0x0000001F)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_Base_Subsequence_Repeat_Rate_DEF (0x00000002)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_Column_Offset_Wrap_Trigger_Enable_OFF (15)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_Column_Offset_Wrap_Trigger_Enable_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_Column_Offset_Wrap_Trigger_Enable_MSK (0x00008000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_Column_Offset_Wrap_Trigger_Enable_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_Column_Offset_Wrap_Trigger_Enable_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_Row_Offset_Wrap_Trigger_Enable_OFF (16)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_Row_Offset_Wrap_Trigger_Enable_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_Row_Offset_Wrap_Trigger_Enable_MSK (0x00010000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_Row_Offset_Wrap_Trigger_Enable_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_Row_Offset_Wrap_Trigger_Enable_DEF (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_Base_Subsequence_Type_OFF (20)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_Base_Subsequence_Type_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_Base_Subsequence_Type_MSK (0x00100000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_Base_Subsequence_Type_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_Base_Subsequence_Type_DEF (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_CADB_Deselect_Enable_OFF (21)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_CADB_Deselect_Enable_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_CADB_Deselect_Enable_MSK (0x00200000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_CADB_Deselect_Enable_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_CADB_Deselect_Enable_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_CADB_Select_Enable_OFF (22)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_CADB_Select_Enable_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_CADB_Select_Enable_MSK (0x00400000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_CADB_Select_Enable_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_CADB_Select_Enable_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_CADB_Seeds_Save_Enable_OFF (23)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_CADB_Seeds_Save_Enable_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_CADB_Seeds_Save_Enable_MSK (0x00800000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_CADB_Seeds_Save_Enable_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_CADB_Seeds_Save_Enable_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_Column_Increment_Order_OFF (24)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_Column_Increment_Order_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_Column_Increment_Order_MSK (0x01000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_Column_Increment_Order_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_Column_Increment_Order_DEF (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_Column_Increment_Enable_OFF (26)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_Column_Increment_Enable_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_Column_Increment_Enable_MSK (0x04000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_Column_Increment_Enable_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_Column_Increment_Enable_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_Row_Increment_Order_OFF (27)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_Row_Increment_Order_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_Row_Increment_Order_MSK (0x08000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_Row_Increment_Order_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_Row_Increment_Order_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_Row_Increment_Enable_OFF (29)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_Row_Increment_Enable_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_Row_Increment_Enable_MSK (0x20000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_Row_Increment_Enable_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_Row_Increment_Enable_DEF (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_Base_Invert_Data_and_ECC_OFF (30)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_Base_Invert_Data_and_ECC_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_Base_Invert_Data_and_ECC_MSK (0x40000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_Base_Invert_Data_and_ECC_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_Base_Invert_Data_and_ECC_DEF (0x00000000)
+
+#define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_REG            (0x00004894)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_Offset_Address_Update_Rate_OFF ( 0)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_Offset_Address_Update_Rate_WID ( 5)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_Offset_Address_Update_Rate_MSK (0x0000001F)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_Offset_Address_Update_Rate_MAX (0x0000001F)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_Offset_Address_Update_Rate_DEF (0x00000002)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_Base_Subsequence_Repeat_Rate_OFF ( 8)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_Base_Subsequence_Repeat_Rate_WID ( 5)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_Base_Subsequence_Repeat_Rate_MSK (0x00001F00)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_Base_Subsequence_Repeat_Rate_MAX (0x0000001F)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_Base_Subsequence_Repeat_Rate_DEF (0x00000002)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_Column_Offset_Wrap_Trigger_Enable_OFF (15)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_Column_Offset_Wrap_Trigger_Enable_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_Column_Offset_Wrap_Trigger_Enable_MSK (0x00008000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_Column_Offset_Wrap_Trigger_Enable_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_Column_Offset_Wrap_Trigger_Enable_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_Row_Offset_Wrap_Trigger_Enable_OFF (16)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_Row_Offset_Wrap_Trigger_Enable_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_Row_Offset_Wrap_Trigger_Enable_MSK (0x00010000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_Row_Offset_Wrap_Trigger_Enable_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_Row_Offset_Wrap_Trigger_Enable_DEF (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_Base_Subsequence_Type_OFF (20)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_Base_Subsequence_Type_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_Base_Subsequence_Type_MSK (0x00100000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_Base_Subsequence_Type_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_Base_Subsequence_Type_DEF (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_CADB_Deselect_Enable_OFF (21)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_CADB_Deselect_Enable_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_CADB_Deselect_Enable_MSK (0x00200000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_CADB_Deselect_Enable_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_CADB_Deselect_Enable_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_CADB_Select_Enable_OFF (22)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_CADB_Select_Enable_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_CADB_Select_Enable_MSK (0x00400000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_CADB_Select_Enable_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_CADB_Select_Enable_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_CADB_Seeds_Save_Enable_OFF (23)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_CADB_Seeds_Save_Enable_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_CADB_Seeds_Save_Enable_MSK (0x00800000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_CADB_Seeds_Save_Enable_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_CADB_Seeds_Save_Enable_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_Column_Increment_Order_OFF (24)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_Column_Increment_Order_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_Column_Increment_Order_MSK (0x01000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_Column_Increment_Order_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_Column_Increment_Order_DEF (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_Column_Increment_Enable_OFF (26)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_Column_Increment_Enable_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_Column_Increment_Enable_MSK (0x04000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_Column_Increment_Enable_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_Column_Increment_Enable_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_Row_Increment_Order_OFF (27)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_Row_Increment_Order_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_Row_Increment_Order_MSK (0x08000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_Row_Increment_Order_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_Row_Increment_Order_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_Row_Increment_Enable_OFF (29)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_Row_Increment_Enable_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_Row_Increment_Enable_MSK (0x20000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_Row_Increment_Enable_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_Row_Increment_Enable_DEF (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_Base_Invert_Data_and_ECC_OFF (30)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_Base_Invert_Data_and_ECC_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_Base_Invert_Data_and_ECC_MSK (0x40000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_Base_Invert_Data_and_ECC_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_Base_Invert_Data_and_ECC_DEF (0x00000000)
+
+#define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_REG            (0x00004898)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_Offset_Address_Update_Rate_OFF ( 0)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_Offset_Address_Update_Rate_WID ( 5)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_Offset_Address_Update_Rate_MSK (0x0000001F)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_Offset_Address_Update_Rate_MAX (0x0000001F)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_Offset_Address_Update_Rate_DEF (0x00000002)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_Base_Subsequence_Repeat_Rate_OFF ( 8)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_Base_Subsequence_Repeat_Rate_WID ( 5)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_Base_Subsequence_Repeat_Rate_MSK (0x00001F00)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_Base_Subsequence_Repeat_Rate_MAX (0x0000001F)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_Base_Subsequence_Repeat_Rate_DEF (0x00000002)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_Column_Offset_Wrap_Trigger_Enable_OFF (15)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_Column_Offset_Wrap_Trigger_Enable_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_Column_Offset_Wrap_Trigger_Enable_MSK (0x00008000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_Column_Offset_Wrap_Trigger_Enable_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_Column_Offset_Wrap_Trigger_Enable_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_Row_Offset_Wrap_Trigger_Enable_OFF (16)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_Row_Offset_Wrap_Trigger_Enable_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_Row_Offset_Wrap_Trigger_Enable_MSK (0x00010000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_Row_Offset_Wrap_Trigger_Enable_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_Row_Offset_Wrap_Trigger_Enable_DEF (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_Base_Subsequence_Type_OFF (20)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_Base_Subsequence_Type_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_Base_Subsequence_Type_MSK (0x00100000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_Base_Subsequence_Type_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_Base_Subsequence_Type_DEF (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_CADB_Deselect_Enable_OFF (21)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_CADB_Deselect_Enable_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_CADB_Deselect_Enable_MSK (0x00200000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_CADB_Deselect_Enable_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_CADB_Deselect_Enable_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_CADB_Select_Enable_OFF (22)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_CADB_Select_Enable_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_CADB_Select_Enable_MSK (0x00400000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_CADB_Select_Enable_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_CADB_Select_Enable_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_CADB_Seeds_Save_Enable_OFF (23)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_CADB_Seeds_Save_Enable_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_CADB_Seeds_Save_Enable_MSK (0x00800000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_CADB_Seeds_Save_Enable_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_CADB_Seeds_Save_Enable_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_Column_Increment_Order_OFF (24)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_Column_Increment_Order_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_Column_Increment_Order_MSK (0x01000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_Column_Increment_Order_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_Column_Increment_Order_DEF (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_Column_Increment_Enable_OFF (26)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_Column_Increment_Enable_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_Column_Increment_Enable_MSK (0x04000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_Column_Increment_Enable_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_Column_Increment_Enable_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_Row_Increment_Order_OFF (27)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_Row_Increment_Order_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_Row_Increment_Order_MSK (0x08000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_Row_Increment_Order_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_Row_Increment_Order_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_Row_Increment_Enable_OFF (29)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_Row_Increment_Enable_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_Row_Increment_Enable_MSK (0x20000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_Row_Increment_Enable_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_Row_Increment_Enable_DEF (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_Base_Invert_Data_and_ECC_OFF (30)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_Base_Invert_Data_and_ECC_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_Base_Invert_Data_and_ECC_MSK (0x40000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_Base_Invert_Data_and_ECC_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_Base_Invert_Data_and_ECC_DEF (0x00000000)
+
+#define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_REG            (0x0000489C)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_Offset_Address_Update_Rate_OFF ( 0)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_Offset_Address_Update_Rate_WID ( 5)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_Offset_Address_Update_Rate_MSK (0x0000001F)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_Offset_Address_Update_Rate_MAX (0x0000001F)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_Offset_Address_Update_Rate_DEF (0x00000002)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_Base_Subsequence_Repeat_Rate_OFF ( 8)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_Base_Subsequence_Repeat_Rate_WID ( 5)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_Base_Subsequence_Repeat_Rate_MSK (0x00001F00)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_Base_Subsequence_Repeat_Rate_MAX (0x0000001F)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_Base_Subsequence_Repeat_Rate_DEF (0x00000002)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_Column_Offset_Wrap_Trigger_Enable_OFF (15)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_Column_Offset_Wrap_Trigger_Enable_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_Column_Offset_Wrap_Trigger_Enable_MSK (0x00008000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_Column_Offset_Wrap_Trigger_Enable_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_Column_Offset_Wrap_Trigger_Enable_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_Row_Offset_Wrap_Trigger_Enable_OFF (16)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_Row_Offset_Wrap_Trigger_Enable_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_Row_Offset_Wrap_Trigger_Enable_MSK (0x00010000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_Row_Offset_Wrap_Trigger_Enable_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_Row_Offset_Wrap_Trigger_Enable_DEF (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_Base_Subsequence_Type_OFF (20)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_Base_Subsequence_Type_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_Base_Subsequence_Type_MSK (0x00100000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_Base_Subsequence_Type_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_Base_Subsequence_Type_DEF (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_CADB_Deselect_Enable_OFF (21)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_CADB_Deselect_Enable_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_CADB_Deselect_Enable_MSK (0x00200000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_CADB_Deselect_Enable_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_CADB_Deselect_Enable_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_CADB_Select_Enable_OFF (22)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_CADB_Select_Enable_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_CADB_Select_Enable_MSK (0x00400000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_CADB_Select_Enable_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_CADB_Select_Enable_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_CADB_Seeds_Save_Enable_OFF (23)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_CADB_Seeds_Save_Enable_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_CADB_Seeds_Save_Enable_MSK (0x00800000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_CADB_Seeds_Save_Enable_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_CADB_Seeds_Save_Enable_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_Column_Increment_Order_OFF (24)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_Column_Increment_Order_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_Column_Increment_Order_MSK (0x01000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_Column_Increment_Order_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_Column_Increment_Order_DEF (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_Column_Increment_Enable_OFF (26)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_Column_Increment_Enable_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_Column_Increment_Enable_MSK (0x04000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_Column_Increment_Enable_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_Column_Increment_Enable_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_Row_Increment_Order_OFF (27)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_Row_Increment_Order_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_Row_Increment_Order_MSK (0x08000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_Row_Increment_Order_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_Row_Increment_Order_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_Row_Increment_Enable_OFF (29)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_Row_Increment_Enable_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_Row_Increment_Enable_MSK (0x20000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_Row_Increment_Enable_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_Row_Increment_Enable_DEF (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_Base_Invert_Data_and_ECC_OFF (30)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_Base_Invert_Data_and_ECC_WID ( 1)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_Base_Invert_Data_and_ECC_MSK (0x40000000)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_Base_Invert_Data_and_ECC_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_Base_Invert_Data_and_ECC_DEF (0x00000000)
+
+#define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_REG                       (0x000048A8)
+  #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Stop_Base_Sequence_On_Wrap_Trigger_OFF ( 3)
+  #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Stop_Base_Sequence_On_Wrap_Trigger_WID ( 1)
+  #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Stop_Base_Sequence_On_Wrap_Trigger_MSK (0x00000008)
+  #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Stop_Base_Sequence_On_Wrap_Trigger_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Stop_Base_Sequence_On_Wrap_Trigger_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Address_Update_Rate_Mode_OFF ( 5)
+  #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Address_Update_Rate_Mode_WID ( 1)
+  #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Address_Update_Rate_Mode_MSK (0x00000020)
+  #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Address_Update_Rate_Mode_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Address_Update_Rate_Mode_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Enable_Dummy_Reads_OFF    ( 7)
+  #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Enable_Dummy_Reads_WID    ( 1)
+  #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Enable_Dummy_Reads_MSK    (0x00000080)
+  #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Enable_Dummy_Reads_MAX    (0x00000001)
+  #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Enable_Dummy_Reads_DEF    (0x00000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Enable_Constant_Write_Strobe_OFF (10)
+  #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Enable_Constant_Write_Strobe_WID ( 1)
+  #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Enable_Constant_Write_Strobe_MSK (0x00000400)
+  #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Enable_Constant_Write_Strobe_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Enable_Constant_Write_Strobe_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Global_Control_OFF        (11)
+  #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Global_Control_WID        ( 1)
+  #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Global_Control_MSK        (0x00000800)
+  #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Global_Control_MAX        (0x00000001)
+  #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Global_Control_DEF        (0x00000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Initialization_Mode_OFF   (12)
+  #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Initialization_Mode_WID   ( 2)
+  #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Initialization_Mode_MSK   (0x00003000)
+  #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Initialization_Mode_MAX   (0x00000003)
+  #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Initialization_Mode_DEF   (0x00000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Loopcount_OFF             (16)
+  #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Loopcount_WID             ( 5)
+  #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Loopcount_MSK             (0x001F0000)
+  #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Loopcount_MAX             (0x0000001F)
+  #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Loopcount_DEF             (0x00000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Subsequence_Start_Pointer_OFF (24)
+  #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Subsequence_Start_Pointer_WID ( 3)
+  #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Subsequence_Start_Pointer_MSK (0x07000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Subsequence_Start_Pointer_MAX (0x00000007)
+  #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Subsequence_Start_Pointer_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Subsequence_End_Pointer_OFF (28)
+  #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Subsequence_End_Pointer_WID ( 3)
+  #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Subsequence_End_Pointer_MSK (0x70000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Subsequence_End_Pointer_MAX (0x00000007)
+  #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Subsequence_End_Pointer_DEF (0x00000001)
+  #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Start_Test_Delay_OFF      (32)
+  #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Start_Test_Delay_WID      (10)
+  #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Start_Test_Delay_MSK      (0x3FF00000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Start_Test_Delay_MAX      (0x000003FF)
+  #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Start_Test_Delay_DEF      (0x00000000)
+
+#define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_REG                       (0x000048B0)
+  #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_Stop_Base_Sequence_On_Wrap_Trigger_OFF ( 3)
+  #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_Stop_Base_Sequence_On_Wrap_Trigger_WID ( 1)
+  #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_Stop_Base_Sequence_On_Wrap_Trigger_MSK (0x00000008)
+  #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_Stop_Base_Sequence_On_Wrap_Trigger_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_Stop_Base_Sequence_On_Wrap_Trigger_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_Address_Update_Rate_Mode_OFF ( 5)
+  #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_Address_Update_Rate_Mode_WID ( 1)
+  #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_Address_Update_Rate_Mode_MSK (0x00000020)
+  #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_Address_Update_Rate_Mode_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_Address_Update_Rate_Mode_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_Enable_Dummy_Reads_OFF    ( 7)
+  #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_Enable_Dummy_Reads_WID    ( 1)
+  #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_Enable_Dummy_Reads_MSK    (0x00000080)
+  #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_Enable_Dummy_Reads_MAX    (0x00000001)
+  #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_Enable_Dummy_Reads_DEF    (0x00000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_Enable_Constant_Write_Strobe_OFF (10)
+  #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_Enable_Constant_Write_Strobe_WID ( 1)
+  #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_Enable_Constant_Write_Strobe_MSK (0x00000400)
+  #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_Enable_Constant_Write_Strobe_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_Enable_Constant_Write_Strobe_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_Global_Control_OFF        (11)
+  #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_Global_Control_WID        ( 1)
+  #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_Global_Control_MSK        (0x00000800)
+  #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_Global_Control_MAX        (0x00000001)
+  #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_Global_Control_DEF        (0x00000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_Initialization_Mode_OFF   (12)
+  #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_Initialization_Mode_WID   ( 2)
+  #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_Initialization_Mode_MSK   (0x00003000)
+  #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_Initialization_Mode_MAX   (0x00000003)
+  #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_Initialization_Mode_DEF   (0x00000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_Loopcount_OFF             (16)
+  #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_Loopcount_WID             ( 5)
+  #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_Loopcount_MSK             (0x001F0000)
+  #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_Loopcount_MAX             (0x0000001F)
+  #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_Loopcount_DEF             (0x00000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_Subsequence_Start_Pointer_OFF (24)
+  #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_Subsequence_Start_Pointer_WID ( 3)
+  #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_Subsequence_Start_Pointer_MSK (0x07000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_Subsequence_Start_Pointer_MAX (0x00000007)
+  #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_Subsequence_Start_Pointer_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_Subsequence_End_Pointer_OFF (28)
+  #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_Subsequence_End_Pointer_WID ( 3)
+  #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_Subsequence_End_Pointer_MSK (0x70000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_Subsequence_End_Pointer_MAX (0x00000007)
+  #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_Subsequence_End_Pointer_DEF (0x00000001)
+  #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_Start_Test_Delay_OFF      (32)
+  #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_Start_Test_Delay_WID      (10)
+  #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_Start_Test_Delay_MSK      (0x3FF00000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_Start_Test_Delay_MAX      (0x000003FF)
+  #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_Start_Test_Delay_DEF      (0x00000000)
+
+#define MCDFXS_CR_REUT_CH_SEQ_CTL_MCMAIN_0_REG                       (0x000048B8)
+  #define MCDFXS_CR_REUT_CH_SEQ_CTL_MCMAIN_0_Local_Start_Test_OFF      ( 0)
+  #define MCDFXS_CR_REUT_CH_SEQ_CTL_MCMAIN_0_Local_Start_Test_WID      ( 1)
+  #define MCDFXS_CR_REUT_CH_SEQ_CTL_MCMAIN_0_Local_Start_Test_MSK      (0x00000001)
+  #define MCDFXS_CR_REUT_CH_SEQ_CTL_MCMAIN_0_Local_Start_Test_MAX      (0x00000001)
+  #define MCDFXS_CR_REUT_CH_SEQ_CTL_MCMAIN_0_Local_Start_Test_DEF      (0x00000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_CTL_MCMAIN_0_Local_Stop_Test_OFF       ( 1)
+  #define MCDFXS_CR_REUT_CH_SEQ_CTL_MCMAIN_0_Local_Stop_Test_WID       ( 1)
+  #define MCDFXS_CR_REUT_CH_SEQ_CTL_MCMAIN_0_Local_Stop_Test_MSK       (0x00000002)
+  #define MCDFXS_CR_REUT_CH_SEQ_CTL_MCMAIN_0_Local_Stop_Test_MAX       (0x00000001)
+  #define MCDFXS_CR_REUT_CH_SEQ_CTL_MCMAIN_0_Local_Stop_Test_DEF       (0x00000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_CTL_MCMAIN_0_Local_Clear_Errors_OFF    ( 2)
+  #define MCDFXS_CR_REUT_CH_SEQ_CTL_MCMAIN_0_Local_Clear_Errors_WID    ( 1)
+  #define MCDFXS_CR_REUT_CH_SEQ_CTL_MCMAIN_0_Local_Clear_Errors_MSK    (0x00000004)
+  #define MCDFXS_CR_REUT_CH_SEQ_CTL_MCMAIN_0_Local_Clear_Errors_MAX    (0x00000001)
+  #define MCDFXS_CR_REUT_CH_SEQ_CTL_MCMAIN_0_Local_Clear_Errors_DEF    (0x00000000)
+
+#define MCDFXS_CR_REUT_CH_SEQ_CTL_MCMAIN_1_REG                       (0x000048BC)
+  #define MCDFXS_CR_REUT_CH_SEQ_CTL_MCMAIN_1_Local_Start_Test_OFF      ( 0)
+  #define MCDFXS_CR_REUT_CH_SEQ_CTL_MCMAIN_1_Local_Start_Test_WID      ( 1)
+  #define MCDFXS_CR_REUT_CH_SEQ_CTL_MCMAIN_1_Local_Start_Test_MSK      (0x00000001)
+  #define MCDFXS_CR_REUT_CH_SEQ_CTL_MCMAIN_1_Local_Start_Test_MAX      (0x00000001)
+  #define MCDFXS_CR_REUT_CH_SEQ_CTL_MCMAIN_1_Local_Start_Test_DEF      (0x00000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_CTL_MCMAIN_1_Local_Stop_Test_OFF       ( 1)
+  #define MCDFXS_CR_REUT_CH_SEQ_CTL_MCMAIN_1_Local_Stop_Test_WID       ( 1)
+  #define MCDFXS_CR_REUT_CH_SEQ_CTL_MCMAIN_1_Local_Stop_Test_MSK       (0x00000002)
+  #define MCDFXS_CR_REUT_CH_SEQ_CTL_MCMAIN_1_Local_Stop_Test_MAX       (0x00000001)
+  #define MCDFXS_CR_REUT_CH_SEQ_CTL_MCMAIN_1_Local_Stop_Test_DEF       (0x00000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_CTL_MCMAIN_1_Local_Clear_Errors_OFF    ( 2)
+  #define MCDFXS_CR_REUT_CH_SEQ_CTL_MCMAIN_1_Local_Clear_Errors_WID    ( 1)
+  #define MCDFXS_CR_REUT_CH_SEQ_CTL_MCMAIN_1_Local_Clear_Errors_MSK    (0x00000004)
+  #define MCDFXS_CR_REUT_CH_SEQ_CTL_MCMAIN_1_Local_Clear_Errors_MAX    (0x00000001)
+  #define MCDFXS_CR_REUT_CH_SEQ_CTL_MCMAIN_1_Local_Clear_Errors_DEF    (0x00000000)
+
+#define MCDFXS_CR_REUT_CH_SEQ_LOOPCOUNT_STATUS_MCMAIN_0_REG          (0x000048C0)
+  #define MCDFXS_CR_REUT_CH_SEQ_LOOPCOUNT_STATUS_MCMAIN_0_Current_Loopcount_OFF ( 0)
+  #define MCDFXS_CR_REUT_CH_SEQ_LOOPCOUNT_STATUS_MCMAIN_0_Current_Loopcount_WID (32)
+  #define MCDFXS_CR_REUT_CH_SEQ_LOOPCOUNT_STATUS_MCMAIN_0_Current_Loopcount_MSK (0xFFFFFFFF)
+  #define MCDFXS_CR_REUT_CH_SEQ_LOOPCOUNT_STATUS_MCMAIN_0_Current_Loopcount_MAX (0xFFFFFFFF)
+  #define MCDFXS_CR_REUT_CH_SEQ_LOOPCOUNT_STATUS_MCMAIN_0_Current_Loopcount_DEF (0x00000000)
+
+#define MCDFXS_CR_REUT_CH_SEQ_LOOPCOUNT_STATUS_MCMAIN_1_REG          (0x000048C4)
+  #define MCDFXS_CR_REUT_CH_SEQ_LOOPCOUNT_STATUS_MCMAIN_1_Current_Loopcount_OFF ( 0)
+  #define MCDFXS_CR_REUT_CH_SEQ_LOOPCOUNT_STATUS_MCMAIN_1_Current_Loopcount_WID (32)
+  #define MCDFXS_CR_REUT_CH_SEQ_LOOPCOUNT_STATUS_MCMAIN_1_Current_Loopcount_MSK (0xFFFFFFFF)
+  #define MCDFXS_CR_REUT_CH_SEQ_LOOPCOUNT_STATUS_MCMAIN_1_Current_Loopcount_MAX (0xFFFFFFFF)
+  #define MCDFXS_CR_REUT_CH_SEQ_LOOPCOUNT_STATUS_MCMAIN_1_Current_Loopcount_DEF (0x00000000)
+
+#define MCDFXS_CR_REUT_CH_SEQ_SUBSEQ_PNTR_MCMAIN_0_REG               (0x000048C8)
+  #define MCDFXS_CR_REUT_CH_SEQ_SUBSEQ_PNTR_MCMAIN_0_Current_Subsequence_Pointer_OFF ( 0)
+  #define MCDFXS_CR_REUT_CH_SEQ_SUBSEQ_PNTR_MCMAIN_0_Current_Subsequence_Pointer_WID ( 3)
+  #define MCDFXS_CR_REUT_CH_SEQ_SUBSEQ_PNTR_MCMAIN_0_Current_Subsequence_Pointer_MSK (0x00000007)
+  #define MCDFXS_CR_REUT_CH_SEQ_SUBSEQ_PNTR_MCMAIN_0_Current_Subsequence_Pointer_MAX (0x00000007)
+  #define MCDFXS_CR_REUT_CH_SEQ_SUBSEQ_PNTR_MCMAIN_0_Current_Subsequence_Pointer_DEF (0x00000000)
+
+#define MCDFXS_CR_REUT_CH_SEQ_SUBSEQ_PNTR_MCMAIN_1_REG               (0x000048CC)
+  #define MCDFXS_CR_REUT_CH_SEQ_SUBSEQ_PNTR_MCMAIN_1_Current_Subsequence_Pointer_OFF ( 0)
+  #define MCDFXS_CR_REUT_CH_SEQ_SUBSEQ_PNTR_MCMAIN_1_Current_Subsequence_Pointer_WID ( 3)
+  #define MCDFXS_CR_REUT_CH_SEQ_SUBSEQ_PNTR_MCMAIN_1_Current_Subsequence_Pointer_MSK (0x00000007)
+  #define MCDFXS_CR_REUT_CH_SEQ_SUBSEQ_PNTR_MCMAIN_1_Current_Subsequence_Pointer_MAX (0x00000007)
+  #define MCDFXS_CR_REUT_CH_SEQ_SUBSEQ_PNTR_MCMAIN_1_Current_Subsequence_Pointer_DEF (0x00000000)
+
+#define MCDFXS_CR_REUT_CH_SEQ_CACHELINE_STATUS_MCMAIN_0_REG          (0x000048D0)
+  #define MCDFXS_CR_REUT_CH_SEQ_CACHELINE_STATUS_MCMAIN_0_Current_Cacheline_OFF ( 0)
+  #define MCDFXS_CR_REUT_CH_SEQ_CACHELINE_STATUS_MCMAIN_0_Current_Cacheline_WID (16)
+  #define MCDFXS_CR_REUT_CH_SEQ_CACHELINE_STATUS_MCMAIN_0_Current_Cacheline_MSK (0x0000FFFF)
+  #define MCDFXS_CR_REUT_CH_SEQ_CACHELINE_STATUS_MCMAIN_0_Current_Cacheline_MAX (0x0000FFFF)
+  #define MCDFXS_CR_REUT_CH_SEQ_CACHELINE_STATUS_MCMAIN_0_Current_Cacheline_DEF (0x00000000)
+
+#define MCDFXS_CR_REUT_CH_SEQ_CACHELINE_STATUS_MCMAIN_1_REG          (0x000048D4)
+  #define MCDFXS_CR_REUT_CH_SEQ_CACHELINE_STATUS_MCMAIN_1_Current_Cacheline_OFF ( 0)
+  #define MCDFXS_CR_REUT_CH_SEQ_CACHELINE_STATUS_MCMAIN_1_Current_Cacheline_WID (16)
+  #define MCDFXS_CR_REUT_CH_SEQ_CACHELINE_STATUS_MCMAIN_1_Current_Cacheline_MSK (0x0000FFFF)
+  #define MCDFXS_CR_REUT_CH_SEQ_CACHELINE_STATUS_MCMAIN_1_Current_Cacheline_MAX (0x0000FFFF)
+  #define MCDFXS_CR_REUT_CH_SEQ_CACHELINE_STATUS_MCMAIN_1_Current_Cacheline_DEF (0x00000000)
+
+#define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_0_REG           (0x000048D8)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_0_Column_Address_OFF (3)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_0_Column_Address_WID_A0 (7)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_0_Column_Address_MSK_A0 (0x000003F8)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_0_Column_Address_MAX_A0 (0x0000007F)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_0_Column_Address_WID (8)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_0_Column_Address_MSK (0x000007F8)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_0_Column_Address_MAX (0x000000FF)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_0_Column_Address_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_0_Row_Address_OFF (24)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_0_Row_Address_WID (16)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_0_Row_Address_MSK (0xFFFF000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_0_Row_Address_MAX (0x0000FFFF)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_0_Row_Address_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_0_Bank_Address_OFF (48)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_0_Bank_Address_WID (3)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_0_Bank_Address_MSK (0x7000000000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_0_Bank_Address_MAX (0x00000007)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_0_Bank_Address_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_0_Rank_Address_OFF (56)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_0_Rank_Address_WID (3)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_0_Rank_Address_MSK (0x700000000000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_0_Rank_Address_MAX (0x00000007)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_0_Rank_Address_DEF (0x00000000)
+
+#define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_1_REG           (0x000048E0)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_1_Column_Address_OFF (3)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_1_Column_Address_WID_A0 (7)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_1_Column_Address_MSK_A0 (0x000003F8)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_1_Column_Address_MAX_A0 (0x0000007F)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_1_Column_Address_WID (8)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_1_Column_Address_MSK (0x000007F8)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_1_Column_Address_MAX (0x000000FF)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_1_Column_Address_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_1_Row_Address_OFF (24)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_1_Row_Address_WID (16)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_1_Row_Address_MSK (0xFFFF000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_1_Row_Address_MAX (0x0000FFFF)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_1_Row_Address_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_1_Bank_Address_OFF (48)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_1_Bank_Address_WID (3)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_1_Bank_Address_MSK (0x7000000000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_1_Bank_Address_MAX (0x00000007)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_1_Bank_Address_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_1_Rank_Address_OFF (56)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_1_Rank_Address_WID (3)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_1_Rank_Address_MSK (0x700000000000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_1_Rank_Address_MAX (0x00000007)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_1_Rank_Address_DEF (0x00000000)
+
+#define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_0_REG            (0x000048E8)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_0_Column_Address_OFF (3)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_0_Column_Address_WID_A0 (7)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_0_Column_Address_MSK_A0 (0x000003F8)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_0_Column_Address_MAX_A0 (0x0000007F)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_0_Column_Address_DEF_A0 (0x0000007F)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_0_Column_Address_WID (8)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_0_Column_Address_MSK (0x000007F8)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_0_Column_Address_MAX (0x000000FF)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_0_Column_Address_DEF (0x000000FF)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_0_Row_Address_OFF (24)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_0_Row_Address_WID (16)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_0_Row_Address_MSK (0xFFFF000000ULL)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_0_Row_Address_MAX (0x0000FFFF)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_0_Row_Address_DEF (0x0000FFFF)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_0_Bank_Address_OFF (48)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_0_Bank_Address_WID (3)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_0_Bank_Address_MSK (0x7000000000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_0_Bank_Address_MAX (0x00000007)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_0_Bank_Address_DEF (0x00000007)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_0_Rank_Address_OFF (56)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_0_Rank_Address_WID (3)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_0_Rank_Address_MSK (0x700000000000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_0_Rank_Address_MAX (0x00000007)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_0_Rank_Address_DEF (0x00000007)
+
+#define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_1_REG            (0x000048F0)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_1_Column_Address_OFF (3)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_1_Column_Address_WID_A0 (7)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_1_Column_Address_MSK_A0 (0x000003F8)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_1_Column_Address_MAX_A0 (0x0000007F)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_1_Column_Address_DEF_A0 (0x0000007F)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_1_Column_Address_WID (8)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_1_Column_Address_MSK (0x000007F8)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_1_Column_Address_MAX (0x000000FF)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_1_Column_Address_DEF (0x000000FF)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_1_Row_Address_OFF (24)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_1_Row_Address_WID (16)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_1_Row_Address_MSK (0xFFFF000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_1_Row_Address_MAX (0x0000FFFF)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_1_Row_Address_DEF (0x0000FFFF)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_1_Bank_Address_OFF (48)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_1_Bank_Address_WID (3)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_1_Bank_Address_MSK (0x7000000000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_1_Bank_Address_MAX (0x00000007)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_1_Bank_Address_DEF (0x00000007)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_1_Rank_Address_OFF (56)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_1_Rank_Address_WID (3)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_1_Rank_Address_MSK (0x700000000000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_1_Rank_Address_MAX (0x00000007)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_1_Rank_Address_DEF (0x00000007)
+
+#define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_0_REG         (0x000048F8)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_0_Column_Address_OFF (3)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_0_Column_Address_WID_A0 (7)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_0_Column_Address_MSK_A0 (0x000003F8)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_0_Column_Address_MAX_A0 (0x0000007F)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_0_Column_Address_WID (8)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_0_Column_Address_MSK (0x000007F8)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_0_Column_Address_MAX (0x000000FF)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_0_Column_Address_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_0_Row_Address_OFF (24)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_0_Row_Address_WID (16)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_0_Row_Address_MSK (0xFFFF000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_0_Row_Address_MAX (0x0000FFFF)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_0_Row_Address_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_0_Bank_Address_OFF (48)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_0_Bank_Address_WID (3)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_0_Bank_Address_MSK (0x7000000000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_0_Bank_Address_MAX (0x00000007)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_0_Bank_Address_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_0_Rank_Address_OFF (56)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_0_Rank_Address_WID (3)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_0_Rank_Address_MSK (0x700000000000000ULL)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_0_Rank_Address_MAX (0x00000007)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_0_Rank_Address_DEF (0x00000000)
+
+#define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_1_REG         (0x00004900)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_1_Column_Address_OFF (3)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_1_Column_Address_WID_A0 (7)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_1_Column_Address_MSK_A0 (0x000003F8)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_1_Column_Address_MAX_A0 (0x0000007F)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_1_Column_Address_WID (8)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_1_Column_Address_MSK (0x000007F8)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_1_Column_Address_MAX (0x000000FF)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_1_Column_Address_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_1_Row_Address_OFF (24)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_1_Row_Address_WID (16)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_1_Row_Address_MSK (0xFFFF000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_1_Row_Address_MAX (0x0000FFFF)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_1_Row_Address_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_1_Bank_Address_OFF (48)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_1_Bank_Address_WID (3)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_1_Bank_Address_MSK (0x7000000000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_1_Bank_Address_MAX (0x00000007)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_1_Bank_Address_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_1_Rank_Address_OFF (56)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_1_Rank_Address_WID (3)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_1_Rank_Address_MSK (0x700000000000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_1_Rank_Address_MAX (0x00000007)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_1_Rank_Address_DEF (0x00000000)
+
+#define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_REG (0x00004908)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Base_Column_Address_Order_OFF ( 0)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Base_Column_Address_Order_WID ( 2)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Base_Column_Address_Order_MSK (0x00000003)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Base_Column_Address_Order_MAX (0x00000003)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Base_Column_Address_Order_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Base_Row_Address_Order_OFF ( 2)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Base_Row_Address_Order_WID ( 2)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Base_Row_Address_Order_MSK (0x0000000C)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Base_Row_Address_Order_MAX (0x00000003)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Base_Row_Address_Order_DEF (0x00000001)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Base_Bank_Address_Order_OFF ( 4)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Base_Bank_Address_Order_WID ( 2)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Base_Bank_Address_Order_MSK (0x00000030)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Base_Bank_Address_Order_MAX (0x00000003)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Base_Bank_Address_Order_DEF (0x00000002)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Base_Rank_Address_Order_OFF ( 6)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Base_Rank_Address_Order_WID ( 2)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Base_Rank_Address_Order_MSK (0x000000C0)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Base_Rank_Address_Order_MAX (0x00000003)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Base_Rank_Address_Order_DEF (0x00000003)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Base_Address_Invert_Rate_OFF (13)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Base_Address_Invert_Rate_WID ( 3)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Base_Address_Invert_Rate_MSK (0x0000E000)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Base_Address_Invert_Rate_MAX (0x00000007)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Base_Address_Invert_Rate_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Column_Base_Address_Invert_Enable_OFF (20)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Column_Base_Address_Invert_Enable_WID ( 1)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Column_Base_Address_Invert_Enable_MSK (0x00100000)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Column_Base_Address_Invert_Enable_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Column_Base_Address_Invert_Enable_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Row_Base_Address_Invert_Enable_OFF (21)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Row_Base_Address_Invert_Enable_WID ( 1)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Row_Base_Address_Invert_Enable_MSK (0x00200000)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Row_Base_Address_Invert_Enable_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Row_Base_Address_Invert_Enable_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Bank_Base_Address_Invert_Enable_OFF (22)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Bank_Base_Address_Invert_Enable_WID ( 1)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Bank_Base_Address_Invert_Enable_MSK (0x00400000)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Bank_Base_Address_Invert_Enable_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Bank_Base_Address_Invert_Enable_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Rank_Base_Address_Invert_Enable_OFF (23)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Rank_Base_Address_Invert_Enable_WID ( 1)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Rank_Base_Address_Invert_Enable_MSK (0x00800000)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Rank_Base_Address_Invert_Enable_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Rank_Base_Address_Invert_Enable_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Column_Base_Wrap_Trigger_Enable_OFF (24)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Column_Base_Wrap_Trigger_Enable_WID ( 1)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Column_Base_Wrap_Trigger_Enable_MSK (0x01000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Column_Base_Wrap_Trigger_Enable_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Column_Base_Wrap_Trigger_Enable_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Row_Base_Wrap_Trigger_Enable_OFF (25)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Row_Base_Wrap_Trigger_Enable_WID ( 1)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Row_Base_Wrap_Trigger_Enable_MSK (0x02000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Row_Base_Wrap_Trigger_Enable_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Row_Base_Wrap_Trigger_Enable_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Bank_Base_Wrap_Trigger_Enable_OFF (26)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Bank_Base_Wrap_Trigger_Enable_WID ( 1)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Bank_Base_Wrap_Trigger_Enable_MSK (0x04000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Bank_Base_Wrap_Trigger_Enable_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Bank_Base_Wrap_Trigger_Enable_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Rank_Base_Wrap_Trigger_Enable_OFF (27)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Rank_Base_Wrap_Trigger_Enable_WID ( 1)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Rank_Base_Wrap_Trigger_Enable_MSK (0x08000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Rank_Base_Wrap_Trigger_Enable_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Rank_Base_Wrap_Trigger_Enable_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Column_Base_Wrap_Carry_Enable_OFF (28)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Column_Base_Wrap_Carry_Enable_WID ( 1)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Column_Base_Wrap_Carry_Enable_MSK (0x10000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Column_Base_Wrap_Carry_Enable_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Column_Base_Wrap_Carry_Enable_DEF (0x00000001)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Row_Base_Wrap_Carry_Enable_OFF (29)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Row_Base_Wrap_Carry_Enable_WID ( 1)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Row_Base_Wrap_Carry_Enable_MSK (0x20000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Row_Base_Wrap_Carry_Enable_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Row_Base_Wrap_Carry_Enable_DEF (0x00000001)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Bank_Base_Wrap_Carry_Enable_OFF (30)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Bank_Base_Wrap_Carry_Enable_WID ( 1)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Bank_Base_Wrap_Carry_Enable_MSK (0x40000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Bank_Base_Wrap_Carry_Enable_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Bank_Base_Wrap_Carry_Enable_DEF (0x00000001)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Rank_Base_Wrap_Carry_Enable_OFF (31)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Rank_Base_Wrap_Carry_Enable_WID ( 1)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Rank_Base_Wrap_Carry_Enable_MSK (0x80000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Rank_Base_Wrap_Carry_Enable_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Rank_Base_Wrap_Carry_Enable_DEF (0x00000001)
+
+#define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_REG (0x0000490C)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Base_Column_Address_Order_OFF ( 0)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Base_Column_Address_Order_WID ( 2)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Base_Column_Address_Order_MSK (0x00000003)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Base_Column_Address_Order_MAX (0x00000003)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Base_Column_Address_Order_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Base_Row_Address_Order_OFF ( 2)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Base_Row_Address_Order_WID ( 2)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Base_Row_Address_Order_MSK (0x0000000C)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Base_Row_Address_Order_MAX (0x00000003)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Base_Row_Address_Order_DEF (0x00000001)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Base_Bank_Address_Order_OFF ( 4)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Base_Bank_Address_Order_WID ( 2)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Base_Bank_Address_Order_MSK (0x00000030)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Base_Bank_Address_Order_MAX (0x00000003)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Base_Bank_Address_Order_DEF (0x00000002)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Base_Rank_Address_Order_OFF ( 6)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Base_Rank_Address_Order_WID ( 2)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Base_Rank_Address_Order_MSK (0x000000C0)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Base_Rank_Address_Order_MAX (0x00000003)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Base_Rank_Address_Order_DEF (0x00000003)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Base_Address_Invert_Rate_OFF (13)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Base_Address_Invert_Rate_WID ( 3)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Base_Address_Invert_Rate_MSK (0x0000E000)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Base_Address_Invert_Rate_MAX (0x00000007)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Base_Address_Invert_Rate_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Column_Base_Address_Invert_Enable_OFF (20)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Column_Base_Address_Invert_Enable_WID ( 1)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Column_Base_Address_Invert_Enable_MSK (0x00100000)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Column_Base_Address_Invert_Enable_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Column_Base_Address_Invert_Enable_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Row_Base_Address_Invert_Enable_OFF (21)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Row_Base_Address_Invert_Enable_WID ( 1)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Row_Base_Address_Invert_Enable_MSK (0x00200000)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Row_Base_Address_Invert_Enable_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Row_Base_Address_Invert_Enable_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Bank_Base_Address_Invert_Enable_OFF (22)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Bank_Base_Address_Invert_Enable_WID ( 1)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Bank_Base_Address_Invert_Enable_MSK (0x00400000)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Bank_Base_Address_Invert_Enable_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Bank_Base_Address_Invert_Enable_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Rank_Base_Address_Invert_Enable_OFF (23)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Rank_Base_Address_Invert_Enable_WID ( 1)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Rank_Base_Address_Invert_Enable_MSK (0x00800000)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Rank_Base_Address_Invert_Enable_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Rank_Base_Address_Invert_Enable_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Column_Base_Wrap_Trigger_Enable_OFF (24)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Column_Base_Wrap_Trigger_Enable_WID ( 1)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Column_Base_Wrap_Trigger_Enable_MSK (0x01000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Column_Base_Wrap_Trigger_Enable_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Column_Base_Wrap_Trigger_Enable_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Row_Base_Wrap_Trigger_Enable_OFF (25)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Row_Base_Wrap_Trigger_Enable_WID ( 1)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Row_Base_Wrap_Trigger_Enable_MSK (0x02000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Row_Base_Wrap_Trigger_Enable_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Row_Base_Wrap_Trigger_Enable_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Bank_Base_Wrap_Trigger_Enable_OFF (26)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Bank_Base_Wrap_Trigger_Enable_WID ( 1)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Bank_Base_Wrap_Trigger_Enable_MSK (0x04000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Bank_Base_Wrap_Trigger_Enable_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Bank_Base_Wrap_Trigger_Enable_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Rank_Base_Wrap_Trigger_Enable_OFF (27)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Rank_Base_Wrap_Trigger_Enable_WID ( 1)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Rank_Base_Wrap_Trigger_Enable_MSK (0x08000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Rank_Base_Wrap_Trigger_Enable_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Rank_Base_Wrap_Trigger_Enable_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Column_Base_Wrap_Carry_Enable_OFF (28)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Column_Base_Wrap_Carry_Enable_WID ( 1)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Column_Base_Wrap_Carry_Enable_MSK (0x10000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Column_Base_Wrap_Carry_Enable_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Column_Base_Wrap_Carry_Enable_DEF (0x00000001)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Row_Base_Wrap_Carry_Enable_OFF (29)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Row_Base_Wrap_Carry_Enable_WID ( 1)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Row_Base_Wrap_Carry_Enable_MSK (0x20000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Row_Base_Wrap_Carry_Enable_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Row_Base_Wrap_Carry_Enable_DEF (0x00000001)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Bank_Base_Wrap_Carry_Enable_OFF (30)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Bank_Base_Wrap_Carry_Enable_WID ( 1)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Bank_Base_Wrap_Carry_Enable_MSK (0x40000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Bank_Base_Wrap_Carry_Enable_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Bank_Base_Wrap_Carry_Enable_DEF (0x00000001)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Rank_Base_Wrap_Carry_Enable_OFF (31)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Rank_Base_Wrap_Carry_Enable_WID ( 1)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Rank_Base_Wrap_Carry_Enable_MSK (0x80000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Rank_Base_Wrap_Carry_Enable_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Rank_Base_Wrap_Carry_Enable_DEF (0x00000001)
+
+#define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_REG         (0x00004910)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Column_Base_Address_Increment_OFF (3)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Column_Base_Address_Increment_WID_A0 (7)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Column_Base_Address_Increment_MSK_A0 (0x000003F8)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Column_Base_Address_Increment_MAX_A0 (0x0000007F)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Column_Base_Address_Increment_WID (8)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Column_Base_Address_Increment_MSK (0x000007F8)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Column_Base_Address_Increment_MAX (0x000000FF)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Column_Base_Address_Increment_DEF (0x00000001)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Column_Base_Address_Update_Rate_OFF (12)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Column_Base_Address_Update_Rate_WID (5)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Column_Base_Address_Update_Rate_MSK (0x0001F000)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Column_Base_Address_Update_Rate_MAX (0x0000001F)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Column_Base_Address_Update_Rate_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Column_Base_Address_Update_Scale_OFF (19)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Column_Base_Address_Update_Scale_WID (1)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Column_Base_Address_Update_Scale_MSK (0x00080000)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Column_Base_Address_Update_Scale_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Column_Base_Address_Update_Scale_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Row_Base_Address_Increment_OFF (20)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Row_Base_Address_Increment_WID (12)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Row_Base_Address_Increment_MSK (0xFFF00000)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Row_Base_Address_Increment_MAX (0x00000FFF)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Row_Base_Address_Increment_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Row_Base_Address_Update_Rate_OFF (32)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Row_Base_Address_Update_Rate_WID (4)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Row_Base_Address_Update_Rate_MSK (0xF00000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Row_Base_Address_Update_Rate_MAX (0x0000000F)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Row_Base_Address_Update_Rate_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Row_Base_Address_Update_Scale_OFF (37)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Row_Base_Address_Update_Scale_WID (1)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Row_Base_Address_Update_Scale_MSK (0x2000000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Row_Base_Address_Update_Scale_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Row_Base_Address_Update_Scale_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Bank_Base_Address_Increment_OFF (38)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Bank_Base_Address_Increment_WID (3)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Bank_Base_Address_Increment_MSK (0x1C000000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Bank_Base_Address_Increment_MAX (0x00000007)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Bank_Base_Address_Increment_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Bank_Base_Address_Update_Rate_OFF (44)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Bank_Base_Address_Update_Rate_WID (5)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Bank_Base_Address_Update_Rate_MSK (0x1F00000000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Bank_Base_Address_Update_Rate_MAX (0x0000001F)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Bank_Base_Address_Update_Rate_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Bank_Base_Address_Update_Scale_OFF (51)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Bank_Base_Address_Update_Scale_WID (1)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Bank_Base_Address_Update_Scale_MSK (0x8000000000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Bank_Base_Address_Update_Scale_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Bank_Base_Address_Update_Scale_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Rank_Base_Address_Increment_OFF (52)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Rank_Base_Address_Increment_WID (3)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Rank_Base_Address_Increment_MSK (0x70000000000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Rank_Base_Address_Increment_MAX (0x00000007)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Rank_Base_Address_Increment_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Rank_Base_Address_Update_Rate_OFF (56)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Rank_Base_Address_Update_Rate_WID (5)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Rank_Base_Address_Update_Rate_MSK (0x1F00000000000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Rank_Base_Address_Update_Rate_MAX (0x0000001F)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Rank_Base_Address_Update_Rate_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Rank_Base_Address_Update_Scale_OFF (63)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Rank_Base_Address_Update_Scale_WID (1)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Rank_Base_Address_Update_Scale_MSK (0x8000000000000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Rank_Base_Address_Update_Scale_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Rank_Base_Address_Update_Scale_DEF (0x00000000)
+
+#define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_REG         (0x00004918)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Column_Base_Address_Increment_OFF (3)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Column_Base_Address_Increment_WID_A0 (7)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Column_Base_Address_Increment_MSK_A0 (0x000003F8)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Column_Base_Address_Increment_MAX_A0 (0x0000007F)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Column_Base_Address_Increment_WID (8)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Column_Base_Address_Increment_MSK (0x000007F8)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Column_Base_Address_Increment_MAX (0x000000FF)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Column_Base_Address_Increment_DEF (0x00000001)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Column_Base_Address_Update_Rate_OFF (12)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Column_Base_Address_Update_Rate_WID (5)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Column_Base_Address_Update_Rate_MSK (0x0001F000)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Column_Base_Address_Update_Rate_MAX (0x0000001F)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Column_Base_Address_Update_Rate_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Column_Base_Address_Update_Scale_OFF (19)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Column_Base_Address_Update_Scale_WID (1)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Column_Base_Address_Update_Scale_MSK (0x00080000)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Column_Base_Address_Update_Scale_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Column_Base_Address_Update_Scale_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Row_Base_Address_Increment_OFF (20)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Row_Base_Address_Increment_WID (12)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Row_Base_Address_Increment_MSK (0xFFF00000)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Row_Base_Address_Increment_MAX (0x00000FFF)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Row_Base_Address_Increment_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Row_Base_Address_Update_Rate_OFF (32)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Row_Base_Address_Update_Rate_WID (4)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Row_Base_Address_Update_Rate_MSK (0xF00000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Row_Base_Address_Update_Rate_MAX (0x0000000F)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Row_Base_Address_Update_Rate_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Row_Base_Address_Update_Scale_OFF (37)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Row_Base_Address_Update_Scale_WID (1)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Row_Base_Address_Update_Scale_MSK (0x2000000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Row_Base_Address_Update_Scale_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Row_Base_Address_Update_Scale_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Bank_Base_Address_Increment_OFF (38)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Bank_Base_Address_Increment_WID (3)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Bank_Base_Address_Increment_MSK (0x1C000000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Bank_Base_Address_Increment_MAX (0x00000007)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Bank_Base_Address_Increment_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Bank_Base_Address_Update_Rate_OFF (44)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Bank_Base_Address_Update_Rate_WID (5)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Bank_Base_Address_Update_Rate_MSK (0x1F00000000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Bank_Base_Address_Update_Rate_MAX (0x0000001F)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Bank_Base_Address_Update_Rate_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Bank_Base_Address_Update_Scale_OFF (51)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Bank_Base_Address_Update_Scale_WID (1)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Bank_Base_Address_Update_Scale_MSK (0x8000000000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Bank_Base_Address_Update_Scale_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Bank_Base_Address_Update_Scale_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Rank_Base_Address_Increment_OFF (52)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Rank_Base_Address_Increment_WID (3)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Rank_Base_Address_Increment_MSK (0x70000000000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Rank_Base_Address_Increment_MAX (0x00000007)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Rank_Base_Address_Increment_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Rank_Base_Address_Update_Rate_OFF (56)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Rank_Base_Address_Update_Rate_WID (5)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Rank_Base_Address_Update_Rate_MSK (0x1F00000000000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Rank_Base_Address_Update_Rate_MAX (0x0000001F)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Rank_Base_Address_Update_Rate_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Rank_Base_Address_Update_Scale_OFF (63)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Rank_Base_Address_Update_Scale_WID (1)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Rank_Base_Address_Update_Scale_MSK (0x8000000000000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Rank_Base_Address_Update_Scale_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Rank_Base_Address_Update_Scale_DEF (0x00000000)
+
+#define MCDFXS_CR_REUT_CH_SEQ_OFFSET_ADDR_CURRENT_MCMAIN_0_REG       (0x00004920)
+  #define MCDFXS_CR_REUT_CH_SEQ_OFFSET_ADDR_CURRENT_MCMAIN_0_Column_Address_OFF (3)
+  #define MCDFXS_CR_REUT_CH_SEQ_OFFSET_ADDR_CURRENT_MCMAIN_0_Column_Address_WID_A0 (7)
+  #define MCDFXS_CR_REUT_CH_SEQ_OFFSET_ADDR_CURRENT_MCMAIN_0_Column_Address_MSK_A0 (0x000003F8)
+  #define MCDFXS_CR_REUT_CH_SEQ_OFFSET_ADDR_CURRENT_MCMAIN_0_Column_Address_MAX_A0 (0x0000007F)
+  #define MCDFXS_CR_REUT_CH_SEQ_OFFSET_ADDR_CURRENT_MCMAIN_0_Column_Address_WID (8)
+  #define MCDFXS_CR_REUT_CH_SEQ_OFFSET_ADDR_CURRENT_MCMAIN_0_Column_Address_MSK (0x000007F8)
+  #define MCDFXS_CR_REUT_CH_SEQ_OFFSET_ADDR_CURRENT_MCMAIN_0_Column_Address_MAX (0x000000FF)
+  #define MCDFXS_CR_REUT_CH_SEQ_OFFSET_ADDR_CURRENT_MCMAIN_0_Column_Address_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_OFFSET_ADDR_CURRENT_MCMAIN_0_Row_Address_OFF (24)
+  #define MCDFXS_CR_REUT_CH_SEQ_OFFSET_ADDR_CURRENT_MCMAIN_0_Row_Address_WID (16)
+  #define MCDFXS_CR_REUT_CH_SEQ_OFFSET_ADDR_CURRENT_MCMAIN_0_Row_Address_MSK (0xFFFF000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_OFFSET_ADDR_CURRENT_MCMAIN_0_Row_Address_MAX (0x0000FFFF)
+  #define MCDFXS_CR_REUT_CH_SEQ_OFFSET_ADDR_CURRENT_MCMAIN_0_Row_Address_DEF (0x00000000)
+
+#define MCDFXS_CR_REUT_CH_SEQ_OFFSET_ADDR_CURRENT_MCMAIN_1_REG       (0x00004928)
+  #define MCDFXS_CR_REUT_CH_SEQ_OFFSET_ADDR_CURRENT_MCMAIN_1_Column_Address_OFF (3)
+  #define MCDFXS_CR_REUT_CH_SEQ_OFFSET_ADDR_CURRENT_MCMAIN_1_Column_Address_WID_A0 (7)
+  #define MCDFXS_CR_REUT_CH_SEQ_OFFSET_ADDR_CURRENT_MCMAIN_1_Column_Address_MSK_A0 (0x000003F8)
+  #define MCDFXS_CR_REUT_CH_SEQ_OFFSET_ADDR_CURRENT_MCMAIN_1_Column_Address_MAX_A0 (0x0000007F)
+  #define MCDFXS_CR_REUT_CH_SEQ_OFFSET_ADDR_CURRENT_MCMAIN_1_Column_Address_WID (8)
+  #define MCDFXS_CR_REUT_CH_SEQ_OFFSET_ADDR_CURRENT_MCMAIN_1_Column_Address_MSK (0x000007F8)
+  #define MCDFXS_CR_REUT_CH_SEQ_OFFSET_ADDR_CURRENT_MCMAIN_1_Column_Address_MAX (0x000000FF)
+  #define MCDFXS_CR_REUT_CH_SEQ_OFFSET_ADDR_CURRENT_MCMAIN_1_Column_Address_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_OFFSET_ADDR_CURRENT_MCMAIN_1_Row_Address_OFF (24)
+  #define MCDFXS_CR_REUT_CH_SEQ_OFFSET_ADDR_CURRENT_MCMAIN_1_Row_Address_WID (16)
+  #define MCDFXS_CR_REUT_CH_SEQ_OFFSET_ADDR_CURRENT_MCMAIN_1_Row_Address_MSK (0xFFFF000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_OFFSET_ADDR_CURRENT_MCMAIN_1_Row_Address_MAX (0x0000FFFF)
+  #define MCDFXS_CR_REUT_CH_SEQ_OFFSET_ADDR_CURRENT_MCMAIN_1_Row_Address_DEF (0x00000000)
+
+#define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_0_REG (0x00004930)
+  #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_0_Logical_to_Physical_Rank0_Mapping_OFF ( 0)
+  #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_0_Logical_to_Physical_Rank0_Mapping_WID ( 2)
+  #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_0_Logical_to_Physical_Rank0_Mapping_MSK (0x00000003)
+  #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_0_Logical_to_Physical_Rank0_Mapping_MAX (0x00000003)
+  #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_0_Logical_to_Physical_Rank0_Mapping_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_0_Logical_to_Physical_Rank1_Mapping_OFF ( 4)
+  #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_0_Logical_to_Physical_Rank1_Mapping_WID ( 2)
+  #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_0_Logical_to_Physical_Rank1_Mapping_MSK (0x00000030)
+  #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_0_Logical_to_Physical_Rank1_Mapping_MAX (0x00000003)
+  #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_0_Logical_to_Physical_Rank1_Mapping_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_0_Logical_to_Physical_Rank2_Mapping_OFF ( 8)
+  #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_0_Logical_to_Physical_Rank2_Mapping_WID ( 2)
+  #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_0_Logical_to_Physical_Rank2_Mapping_MSK (0x00000300)
+  #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_0_Logical_to_Physical_Rank2_Mapping_MAX (0x00000003)
+  #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_0_Logical_to_Physical_Rank2_Mapping_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_0_Logical_to_Physical_Rank3_Mapping_OFF (12)
+  #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_0_Logical_to_Physical_Rank3_Mapping_WID ( 2)
+  #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_0_Logical_to_Physical_Rank3_Mapping_MSK (0x00003000)
+  #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_0_Logical_to_Physical_Rank3_Mapping_MAX (0x00000003)
+  #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_0_Logical_to_Physical_Rank3_Mapping_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_0_Logical_to_Physical_Rank4_Mapping_OFF (16)
+  #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_0_Logical_to_Physical_Rank4_Mapping_WID ( 2)
+  #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_0_Logical_to_Physical_Rank4_Mapping_MSK (0x00030000)
+  #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_0_Logical_to_Physical_Rank4_Mapping_MAX (0x00000003)
+  #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_0_Logical_to_Physical_Rank4_Mapping_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_0_Logical_to_Physical_Rank5_Mapping_OFF (20)
+  #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_0_Logical_to_Physical_Rank5_Mapping_WID ( 2)
+  #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_0_Logical_to_Physical_Rank5_Mapping_MSK (0x00300000)
+  #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_0_Logical_to_Physical_Rank5_Mapping_MAX (0x00000003)
+  #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_0_Logical_to_Physical_Rank5_Mapping_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_0_Logical_to_Physical_Rank6_Mapping_OFF (24)
+  #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_0_Logical_to_Physical_Rank6_Mapping_WID ( 2)
+  #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_0_Logical_to_Physical_Rank6_Mapping_MSK (0x03000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_0_Logical_to_Physical_Rank6_Mapping_MAX (0x00000003)
+  #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_0_Logical_to_Physical_Rank6_Mapping_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_0_Logical_to_Physical_Rank7_Mapping_OFF (28)
+  #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_0_Logical_to_Physical_Rank7_Mapping_WID ( 2)
+  #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_0_Logical_to_Physical_Rank7_Mapping_MSK (0x30000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_0_Logical_to_Physical_Rank7_Mapping_MAX (0x00000003)
+  #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_0_Logical_to_Physical_Rank7_Mapping_DEF (0x00000000)
+
+#define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_1_REG (0x00004934)
+  #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_1_Logical_to_Physical_Rank0_Mapping_OFF ( 0)
+  #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_1_Logical_to_Physical_Rank0_Mapping_WID ( 2)
+  #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_1_Logical_to_Physical_Rank0_Mapping_MSK (0x00000003)
+  #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_1_Logical_to_Physical_Rank0_Mapping_MAX (0x00000003)
+  #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_1_Logical_to_Physical_Rank0_Mapping_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_1_Logical_to_Physical_Rank1_Mapping_OFF ( 4)
+  #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_1_Logical_to_Physical_Rank1_Mapping_WID ( 2)
+  #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_1_Logical_to_Physical_Rank1_Mapping_MSK (0x00000030)
+  #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_1_Logical_to_Physical_Rank1_Mapping_MAX (0x00000003)
+  #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_1_Logical_to_Physical_Rank1_Mapping_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_1_Logical_to_Physical_Rank2_Mapping_OFF ( 8)
+  #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_1_Logical_to_Physical_Rank2_Mapping_WID ( 2)
+  #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_1_Logical_to_Physical_Rank2_Mapping_MSK (0x00000300)
+  #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_1_Logical_to_Physical_Rank2_Mapping_MAX (0x00000003)
+  #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_1_Logical_to_Physical_Rank2_Mapping_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_1_Logical_to_Physical_Rank3_Mapping_OFF (12)
+  #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_1_Logical_to_Physical_Rank3_Mapping_WID ( 2)
+  #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_1_Logical_to_Physical_Rank3_Mapping_MSK (0x00003000)
+  #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_1_Logical_to_Physical_Rank3_Mapping_MAX (0x00000003)
+  #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_1_Logical_to_Physical_Rank3_Mapping_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_1_Logical_to_Physical_Rank4_Mapping_OFF (16)
+  #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_1_Logical_to_Physical_Rank4_Mapping_WID ( 2)
+  #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_1_Logical_to_Physical_Rank4_Mapping_MSK (0x00030000)
+  #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_1_Logical_to_Physical_Rank4_Mapping_MAX (0x00000003)
+  #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_1_Logical_to_Physical_Rank4_Mapping_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_1_Logical_to_Physical_Rank5_Mapping_OFF (20)
+  #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_1_Logical_to_Physical_Rank5_Mapping_WID ( 2)
+  #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_1_Logical_to_Physical_Rank5_Mapping_MSK (0x00300000)
+  #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_1_Logical_to_Physical_Rank5_Mapping_MAX (0x00000003)
+  #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_1_Logical_to_Physical_Rank5_Mapping_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_1_Logical_to_Physical_Rank6_Mapping_OFF (24)
+  #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_1_Logical_to_Physical_Rank6_Mapping_WID ( 2)
+  #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_1_Logical_to_Physical_Rank6_Mapping_MSK (0x03000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_1_Logical_to_Physical_Rank6_Mapping_MAX (0x00000003)
+  #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_1_Logical_to_Physical_Rank6_Mapping_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_1_Logical_to_Physical_Rank7_Mapping_OFF (28)
+  #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_1_Logical_to_Physical_Rank7_Mapping_WID ( 2)
+  #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_1_Logical_to_Physical_Rank7_Mapping_MSK (0x30000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_1_Logical_to_Physical_Rank7_Mapping_MAX (0x00000003)
+  #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_1_Logical_to_Physical_Rank7_Mapping_DEF (0x00000000)
+
+#define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_0_REG    (0x00004938)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_0_Logical_to_Physical_Row0_Swizzle_OFF ( 0)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_0_Logical_to_Physical_Row0_Swizzle_WID ( 4)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_0_Logical_to_Physical_Row0_Swizzle_MSK (0x0000000F)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_0_Logical_to_Physical_Row0_Swizzle_MAX (0x0000000F)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_0_Logical_to_Physical_Row0_Swizzle_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_0_Logical_to_Physical_Row1_Swizzle_OFF ( 5)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_0_Logical_to_Physical_Row1_Swizzle_WID ( 4)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_0_Logical_to_Physical_Row1_Swizzle_MSK (0x000001E0)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_0_Logical_to_Physical_Row1_Swizzle_MAX (0x0000000F)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_0_Logical_to_Physical_Row1_Swizzle_DEF (0x00000001)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_0_Logical_to_Physical_Row2_Swizzle_OFF (10)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_0_Logical_to_Physical_Row2_Swizzle_WID ( 4)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_0_Logical_to_Physical_Row2_Swizzle_MSK (0x00003C00)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_0_Logical_to_Physical_Row2_Swizzle_MAX (0x0000000F)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_0_Logical_to_Physical_Row2_Swizzle_DEF (0x00000002)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_0_Logical_to_Physical_Row3_Swizzle_OFF (15)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_0_Logical_to_Physical_Row3_Swizzle_WID ( 4)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_0_Logical_to_Physical_Row3_Swizzle_MSK (0x00078000)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_0_Logical_to_Physical_Row3_Swizzle_MAX (0x0000000F)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_0_Logical_to_Physical_Row3_Swizzle_DEF (0x00000003)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_0_Logical_to_Physical_Row4_Swizzle_OFF (20)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_0_Logical_to_Physical_Row4_Swizzle_WID ( 4)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_0_Logical_to_Physical_Row4_Swizzle_MSK (0x00F00000)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_0_Logical_to_Physical_Row4_Swizzle_MAX (0x0000000F)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_0_Logical_to_Physical_Row4_Swizzle_DEF (0x00000004)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_0_Logical_to_Physical_Row5_Swizzle_OFF (25)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_0_Logical_to_Physical_Row5_Swizzle_WID ( 4)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_0_Logical_to_Physical_Row5_Swizzle_MSK (0x1E000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_0_Logical_to_Physical_Row5_Swizzle_MAX (0x0000000F)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_0_Logical_to_Physical_Row5_Swizzle_DEF (0x00000005)
+
+#define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_1_REG    (0x0000493C)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_1_Logical_to_Physical_Row0_Swizzle_OFF ( 0)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_1_Logical_to_Physical_Row0_Swizzle_WID ( 4)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_1_Logical_to_Physical_Row0_Swizzle_MSK (0x0000000F)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_1_Logical_to_Physical_Row0_Swizzle_MAX (0x0000000F)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_1_Logical_to_Physical_Row0_Swizzle_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_1_Logical_to_Physical_Row1_Swizzle_OFF ( 5)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_1_Logical_to_Physical_Row1_Swizzle_WID ( 4)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_1_Logical_to_Physical_Row1_Swizzle_MSK (0x000001E0)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_1_Logical_to_Physical_Row1_Swizzle_MAX (0x0000000F)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_1_Logical_to_Physical_Row1_Swizzle_DEF (0x00000001)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_1_Logical_to_Physical_Row2_Swizzle_OFF (10)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_1_Logical_to_Physical_Row2_Swizzle_WID ( 4)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_1_Logical_to_Physical_Row2_Swizzle_MSK (0x00003C00)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_1_Logical_to_Physical_Row2_Swizzle_MAX (0x0000000F)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_1_Logical_to_Physical_Row2_Swizzle_DEF (0x00000002)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_1_Logical_to_Physical_Row3_Swizzle_OFF (15)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_1_Logical_to_Physical_Row3_Swizzle_WID ( 4)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_1_Logical_to_Physical_Row3_Swizzle_MSK (0x00078000)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_1_Logical_to_Physical_Row3_Swizzle_MAX (0x0000000F)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_1_Logical_to_Physical_Row3_Swizzle_DEF (0x00000003)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_1_Logical_to_Physical_Row4_Swizzle_OFF (20)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_1_Logical_to_Physical_Row4_Swizzle_WID ( 4)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_1_Logical_to_Physical_Row4_Swizzle_MSK (0x00F00000)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_1_Logical_to_Physical_Row4_Swizzle_MAX (0x0000000F)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_1_Logical_to_Physical_Row4_Swizzle_DEF (0x00000004)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_1_Logical_to_Physical_Row5_Swizzle_OFF (25)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_1_Logical_to_Physical_Row5_Swizzle_WID ( 4)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_1_Logical_to_Physical_Row5_Swizzle_MSK (0x1E000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_1_Logical_to_Physical_Row5_Swizzle_MAX (0x0000000F)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_1_Logical_to_Physical_Row5_Swizzle_DEF (0x00000005)
+
+#define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_REG    (0x00004940)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_Logical_to_Physical_Row6_Swizzle_OFF ( 0)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_Logical_to_Physical_Row6_Swizzle_WID ( 4)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_Logical_to_Physical_Row6_Swizzle_MSK (0x0000000F)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_Logical_to_Physical_Row6_Swizzle_MAX (0x0000000F)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_Logical_to_Physical_Row6_Swizzle_DEF (0x00000006)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_Logical_to_Physical_Row7_Swizzle_OFF ( 5)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_Logical_to_Physical_Row7_Swizzle_WID ( 4)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_Logical_to_Physical_Row7_Swizzle_MSK (0x000001E0)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_Logical_to_Physical_Row7_Swizzle_MAX (0x0000000F)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_Logical_to_Physical_Row7_Swizzle_DEF (0x00000007)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_Logical_to_Physical_Row8_Swizzle_OFF (10)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_Logical_to_Physical_Row8_Swizzle_WID ( 4)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_Logical_to_Physical_Row8_Swizzle_MSK (0x00003C00)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_Logical_to_Physical_Row8_Swizzle_MAX (0x0000000F)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_Logical_to_Physical_Row8_Swizzle_DEF (0x00000008)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_Logical_to_Physical_Row9_Swizzle_OFF (15)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_Logical_to_Physical_Row9_Swizzle_WID ( 4)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_Logical_to_Physical_Row9_Swizzle_MSK (0x00078000)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_Logical_to_Physical_Row9_Swizzle_MAX (0x0000000F)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_Logical_to_Physical_Row9_Swizzle_DEF (0x00000009)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_Logical_to_Physical_Row10_Swizzle_OFF (20)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_Logical_to_Physical_Row10_Swizzle_WID ( 4)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_Logical_to_Physical_Row10_Swizzle_MSK (0x00F00000)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_Logical_to_Physical_Row10_Swizzle_MAX (0x0000000F)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_Logical_to_Physical_Row10_Swizzle_DEF (0x0000000A)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_Logical_to_Physical_Row11_Swizzle_OFF (25)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_Logical_to_Physical_Row11_Swizzle_WID ( 4)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_Logical_to_Physical_Row11_Swizzle_MSK (0x1E000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_Logical_to_Physical_Row11_Swizzle_MAX (0x0000000F)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_Logical_to_Physical_Row11_Swizzle_DEF (0x0000000B)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_Logical_to_Physical_Row12_Swizzle_OFF (30)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_Logical_to_Physical_Row12_Swizzle_WID ( 4)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_Logical_to_Physical_Row12_Swizzle_MSK (0x3C0000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_Logical_to_Physical_Row12_Swizzle_MAX (0x0000000F)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_Logical_to_Physical_Row12_Swizzle_DEF (0x0000000C)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_Logical_to_Physical_Row13_Swizzle_OFF (35)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_Logical_to_Physical_Row13_Swizzle_WID ( 4)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_Logical_to_Physical_Row13_Swizzle_MSK (0x7800000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_Logical_to_Physical_Row13_Swizzle_MAX (0x0000000F)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_Logical_to_Physical_Row13_Swizzle_DEF (0x0000000D)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_Logical_to_Physical_Row14_Swizzle_OFF (40)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_Logical_to_Physical_Row14_Swizzle_WID ( 4)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_Logical_to_Physical_Row14_Swizzle_MSK (0xF0000000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_Logical_to_Physical_Row14_Swizzle_MAX (0x0000000F)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_Logical_to_Physical_Row14_Swizzle_DEF (0x0000000E)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_Logical_to_Physical_Row15_Swizzle_OFF (45)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_Logical_to_Physical_Row15_Swizzle_WID ( 4)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_Logical_to_Physical_Row15_Swizzle_MSK (0x1E00000000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_Logical_to_Physical_Row15_Swizzle_MAX (0x0000000F)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_Logical_to_Physical_Row15_Swizzle_DEF (0x0000000F)
+
+#define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_REG    (0x00004948)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_Logical_to_Physical_Row6_Swizzle_OFF ( 0)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_Logical_to_Physical_Row6_Swizzle_WID ( 4)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_Logical_to_Physical_Row6_Swizzle_MSK (0x0000000F)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_Logical_to_Physical_Row6_Swizzle_MAX (0x0000000F)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_Logical_to_Physical_Row6_Swizzle_DEF (0x00000006)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_Logical_to_Physical_Row7_Swizzle_OFF ( 5)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_Logical_to_Physical_Row7_Swizzle_WID ( 4)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_Logical_to_Physical_Row7_Swizzle_MSK (0x000001E0)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_Logical_to_Physical_Row7_Swizzle_MAX (0x0000000F)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_Logical_to_Physical_Row7_Swizzle_DEF (0x00000007)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_Logical_to_Physical_Row8_Swizzle_OFF (10)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_Logical_to_Physical_Row8_Swizzle_WID ( 4)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_Logical_to_Physical_Row8_Swizzle_MSK (0x00003C00)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_Logical_to_Physical_Row8_Swizzle_MAX (0x0000000F)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_Logical_to_Physical_Row8_Swizzle_DEF (0x00000008)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_Logical_to_Physical_Row9_Swizzle_OFF (15)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_Logical_to_Physical_Row9_Swizzle_WID ( 4)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_Logical_to_Physical_Row9_Swizzle_MSK (0x00078000)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_Logical_to_Physical_Row9_Swizzle_MAX (0x0000000F)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_Logical_to_Physical_Row9_Swizzle_DEF (0x00000009)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_Logical_to_Physical_Row10_Swizzle_OFF (20)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_Logical_to_Physical_Row10_Swizzle_WID ( 4)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_Logical_to_Physical_Row10_Swizzle_MSK (0x00F00000)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_Logical_to_Physical_Row10_Swizzle_MAX (0x0000000F)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_Logical_to_Physical_Row10_Swizzle_DEF (0x0000000A)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_Logical_to_Physical_Row11_Swizzle_OFF (25)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_Logical_to_Physical_Row11_Swizzle_WID ( 4)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_Logical_to_Physical_Row11_Swizzle_MSK (0x1E000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_Logical_to_Physical_Row11_Swizzle_MAX (0x0000000F)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_Logical_to_Physical_Row11_Swizzle_DEF (0x0000000B)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_Logical_to_Physical_Row12_Swizzle_OFF (30)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_Logical_to_Physical_Row12_Swizzle_WID ( 4)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_Logical_to_Physical_Row12_Swizzle_MSK (0x3C0000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_Logical_to_Physical_Row12_Swizzle_MAX (0x0000000F)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_Logical_to_Physical_Row12_Swizzle_DEF (0x0000000C)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_Logical_to_Physical_Row13_Swizzle_OFF (35)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_Logical_to_Physical_Row13_Swizzle_WID ( 4)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_Logical_to_Physical_Row13_Swizzle_MSK (0x7800000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_Logical_to_Physical_Row13_Swizzle_MAX (0x0000000F)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_Logical_to_Physical_Row13_Swizzle_DEF (0x0000000D)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_Logical_to_Physical_Row14_Swizzle_OFF (40)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_Logical_to_Physical_Row14_Swizzle_WID ( 4)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_Logical_to_Physical_Row14_Swizzle_MSK (0xF0000000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_Logical_to_Physical_Row14_Swizzle_MAX (0x0000000F)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_Logical_to_Physical_Row14_Swizzle_DEF (0x0000000E)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_Logical_to_Physical_Row15_Swizzle_OFF (45)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_Logical_to_Physical_Row15_Swizzle_WID ( 4)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_Logical_to_Physical_Row15_Swizzle_MSK (0x1E00000000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_Logical_to_Physical_Row15_Swizzle_MAX (0x0000000F)
+  #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_Logical_to_Physical_Row15_Swizzle_DEF (0x0000000F)
+
+#define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_ADDRESS_MCMAIN_0_REG         (0x00004950)
+  #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_ADDRESS_MCMAIN_0_Dummy_Read_Row_Current_Address_OFF ( 0)
+  #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_ADDRESS_MCMAIN_0_Dummy_Read_Row_Current_Address_WID (16)
+  #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_ADDRESS_MCMAIN_0_Dummy_Read_Row_Current_Address_MSK (0x0000FFFF)
+  #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_ADDRESS_MCMAIN_0_Dummy_Read_Row_Current_Address_MAX (0x0000FFFF)
+  #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_ADDRESS_MCMAIN_0_Dummy_Read_Row_Current_Address_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_ADDRESS_MCMAIN_0_Dummy_Read_Bank_Current_Address_OFF (24)
+  #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_ADDRESS_MCMAIN_0_Dummy_Read_Bank_Current_Address_WID ( 3)
+  #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_ADDRESS_MCMAIN_0_Dummy_Read_Bank_Current_Address_MSK (0x07000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_ADDRESS_MCMAIN_0_Dummy_Read_Bank_Current_Address_MAX (0x00000007)
+  #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_ADDRESS_MCMAIN_0_Dummy_Read_Bank_Current_Address_DEF (0x00000000)
+
+#define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_ADDRESS_MCMAIN_1_REG         (0x00004954)
+  #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_ADDRESS_MCMAIN_1_Dummy_Read_Row_Current_Address_OFF ( 0)
+  #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_ADDRESS_MCMAIN_1_Dummy_Read_Row_Current_Address_WID (16)
+  #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_ADDRESS_MCMAIN_1_Dummy_Read_Row_Current_Address_MSK (0x0000FFFF)
+  #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_ADDRESS_MCMAIN_1_Dummy_Read_Row_Current_Address_MAX (0x0000FFFF)
+  #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_ADDRESS_MCMAIN_1_Dummy_Read_Row_Current_Address_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_ADDRESS_MCMAIN_1_Dummy_Read_Bank_Current_Address_OFF (24)
+  #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_ADDRESS_MCMAIN_1_Dummy_Read_Bank_Current_Address_WID ( 3)
+  #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_ADDRESS_MCMAIN_1_Dummy_Read_Bank_Current_Address_MSK (0x07000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_ADDRESS_MCMAIN_1_Dummy_Read_Bank_Current_Address_MAX (0x00000007)
+  #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_ADDRESS_MCMAIN_1_Dummy_Read_Bank_Current_Address_DEF (0x00000000)
+
+#define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_MASK_MCMAIN_0_REG            (0x00004958)
+  #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_MASK_MCMAIN_0_Dummy_Read_Bank_Mask_OFF ( 0)
+  #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_MASK_MCMAIN_0_Dummy_Read_Bank_Mask_WID ( 8)
+  #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_MASK_MCMAIN_0_Dummy_Read_Bank_Mask_MSK (0x000000FF)
+  #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_MASK_MCMAIN_0_Dummy_Read_Bank_Mask_MAX (0x000000FF)
+  #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_MASK_MCMAIN_0_Dummy_Read_Bank_Mask_DEF (0x00000000)
+
+#define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_MASK_MCMAIN_1_REG            (0x0000495C)
+  #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_MASK_MCMAIN_1_Dummy_Read_Bank_Mask_OFF ( 0)
+  #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_MASK_MCMAIN_1_Dummy_Read_Bank_Mask_WID ( 8)
+  #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_MASK_MCMAIN_1_Dummy_Read_Bank_Mask_MSK (0x000000FF)
+  #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_MASK_MCMAIN_1_Dummy_Read_Bank_Mask_MAX (0x000000FF)
+  #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_MASK_MCMAIN_1_Dummy_Read_Bank_Mask_DEF (0x00000000)
+
+#define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_0_REG             (0x00004960)
+  #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_0_L_DummyRead_Select_OFF ( 0)
+  #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_0_L_DummyRead_Select_WID ( 1)
+  #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_0_L_DummyRead_Select_MSK (0x00000001)
+  #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_0_L_DummyRead_Select_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_0_L_DummyRead_Select_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_0_Enable_Sweep_Frequency_OFF ( 1)
+  #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_0_Enable_Sweep_Frequency_WID ( 1)
+  #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_0_Enable_Sweep_Frequency_MSK (0x00000002)
+  #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_0_Enable_Sweep_Frequency_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_0_Enable_Sweep_Frequency_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_0_L_counter_OFF   ( 8)
+  #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_0_L_counter_WID   ( 8)
+  #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_0_L_counter_MSK   (0x0000FF00)
+  #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_0_L_counter_MAX   (0x000000FF)
+  #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_0_L_counter_DEF   (0x00000001)
+  #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_0_M_counter_OFF   (16)
+  #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_0_M_counter_WID   ( 8)
+  #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_0_M_counter_MSK   (0x00FF0000)
+  #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_0_M_counter_MAX   (0x000000FF)
+  #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_0_M_counter_DEF   (0x00000001)
+  #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_0_N_Counter_OFF   (24)
+  #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_0_N_Counter_WID   ( 8)
+  #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_0_N_Counter_MSK   (0xFF000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_0_N_Counter_MAX   (0x000000FF)
+  #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_0_N_Counter_DEF   (0x00000001)
+
+#define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_1_REG             (0x00004964)
+  #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_1_L_DummyRead_Select_OFF ( 0)
+  #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_1_L_DummyRead_Select_WID ( 1)
+  #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_1_L_DummyRead_Select_MSK (0x00000001)
+  #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_1_L_DummyRead_Select_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_1_L_DummyRead_Select_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_1_Enable_Sweep_Frequency_OFF ( 1)
+  #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_1_Enable_Sweep_Frequency_WID ( 1)
+  #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_1_Enable_Sweep_Frequency_MSK (0x00000002)
+  #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_1_Enable_Sweep_Frequency_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_1_Enable_Sweep_Frequency_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_1_L_counter_OFF   ( 8)
+  #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_1_L_counter_WID   ( 8)
+  #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_1_L_counter_MSK   (0x0000FF00)
+  #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_1_L_counter_MAX   (0x000000FF)
+  #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_1_L_counter_DEF   (0x00000001)
+  #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_1_M_counter_OFF   (16)
+  #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_1_M_counter_WID   ( 8)
+  #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_1_M_counter_MSK   (0x00FF0000)
+  #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_1_M_counter_MAX   (0x000000FF)
+  #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_1_M_counter_DEF   (0x00000001)
+  #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_1_N_Counter_OFF   (24)
+  #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_1_N_Counter_WID   ( 8)
+  #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_1_N_Counter_MSK   (0xFF000000)
+  #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_1_N_Counter_MAX   (0x000000FF)
+  #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_1_N_Counter_DEF   (0x00000001)
+
+#define MCDFXS_CR_VISA_CTL_MCDFXS_MCMAIN_REG                         (0x00004968)
+  #define MCDFXS_CR_VISA_CTL_MCDFXS_MCMAIN_EN_CLK_OFF                  ( 0)
+  #define MCDFXS_CR_VISA_CTL_MCDFXS_MCMAIN_EN_CLK_WID                  ( 1)
+  #define MCDFXS_CR_VISA_CTL_MCDFXS_MCMAIN_EN_CLK_MSK                  (0x00000001)
+  #define MCDFXS_CR_VISA_CTL_MCDFXS_MCMAIN_EN_CLK_MAX                  (0x00000001)
+  #define MCDFXS_CR_VISA_CTL_MCDFXS_MCMAIN_EN_CLK_DEF                  (0x00000000)
+  #define MCDFXS_CR_VISA_CTL_MCDFXS_MCMAIN_L0_DATA_BYTE_SEL_OFF        ( 1)
+  #define MCDFXS_CR_VISA_CTL_MCDFXS_MCMAIN_L0_DATA_BYTE_SEL_WID        ( 7)
+  #define MCDFXS_CR_VISA_CTL_MCDFXS_MCMAIN_L0_DATA_BYTE_SEL_MSK        (0x000000FE)
+  #define MCDFXS_CR_VISA_CTL_MCDFXS_MCMAIN_L0_DATA_BYTE_SEL_MAX        (0x0000007F)
+  #define MCDFXS_CR_VISA_CTL_MCDFXS_MCMAIN_L0_DATA_BYTE_SEL_DEF        (0x00000000)
+  #define MCDFXS_CR_VISA_CTL_MCDFXS_MCMAIN_L0_BYP_SEL_OFF              ( 8)
+  #define MCDFXS_CR_VISA_CTL_MCDFXS_MCMAIN_L0_BYP_SEL_WID              ( 1)
+  #define MCDFXS_CR_VISA_CTL_MCDFXS_MCMAIN_L0_BYP_SEL_MSK              (0x00000100)
+  #define MCDFXS_CR_VISA_CTL_MCDFXS_MCMAIN_L0_BYP_SEL_MAX              (0x00000001)
+  #define MCDFXS_CR_VISA_CTL_MCDFXS_MCMAIN_L0_BYP_SEL_DEF              (0x00000000)
+  #define MCDFXS_CR_VISA_CTL_MCDFXS_MCMAIN_L1_DATA_BYTE_SEL_OFF        ( 9)
+  #define MCDFXS_CR_VISA_CTL_MCDFXS_MCMAIN_L1_DATA_BYTE_SEL_WID        ( 7)
+  #define MCDFXS_CR_VISA_CTL_MCDFXS_MCMAIN_L1_DATA_BYTE_SEL_MSK        (0x0000FE00)
+  #define MCDFXS_CR_VISA_CTL_MCDFXS_MCMAIN_L1_DATA_BYTE_SEL_MAX        (0x0000007F)
+  #define MCDFXS_CR_VISA_CTL_MCDFXS_MCMAIN_L1_DATA_BYTE_SEL_DEF        (0x00000000)
+  #define MCDFXS_CR_VISA_CTL_MCDFXS_MCMAIN_L1_BYP_SEL_OFF              (16)
+  #define MCDFXS_CR_VISA_CTL_MCDFXS_MCMAIN_L1_BYP_SEL_WID              ( 1)
+  #define MCDFXS_CR_VISA_CTL_MCDFXS_MCMAIN_L1_BYP_SEL_MSK              (0x00010000)
+  #define MCDFXS_CR_VISA_CTL_MCDFXS_MCMAIN_L1_BYP_SEL_MAX              (0x00000001)
+  #define MCDFXS_CR_VISA_CTL_MCDFXS_MCMAIN_L1_BYP_SEL_DEF              (0x00000000)
+
+#define MCDFXS_CR_REUT_CH_ERR_TRIGGER_CTL_MCMAIN_REG                 (0x0000496C)
+  #define MCDFXS_CR_REUT_CH_ERR_TRIGGER_CTL_MCMAIN_Trigger_In_Global_Start_OFF ( 0)
+  #define MCDFXS_CR_REUT_CH_ERR_TRIGGER_CTL_MCMAIN_Trigger_In_Global_Start_WID ( 1)
+  #define MCDFXS_CR_REUT_CH_ERR_TRIGGER_CTL_MCMAIN_Trigger_In_Global_Start_MSK (0x00000001)
+  #define MCDFXS_CR_REUT_CH_ERR_TRIGGER_CTL_MCMAIN_Trigger_In_Global_Start_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH_ERR_TRIGGER_CTL_MCMAIN_Trigger_In_Global_Start_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH_ERR_TRIGGER_CTL_MCMAIN_Trigger_Out_Global_Start_OFF ( 1)
+  #define MCDFXS_CR_REUT_CH_ERR_TRIGGER_CTL_MCMAIN_Trigger_Out_Global_Start_WID ( 1)
+  #define MCDFXS_CR_REUT_CH_ERR_TRIGGER_CTL_MCMAIN_Trigger_Out_Global_Start_MSK (0x00000002)
+  #define MCDFXS_CR_REUT_CH_ERR_TRIGGER_CTL_MCMAIN_Trigger_Out_Global_Start_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH_ERR_TRIGGER_CTL_MCMAIN_Trigger_Out_Global_Start_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH_ERR_TRIGGER_CTL_MCMAIN_Trigger_Out_On_Error_0_OFF ( 7)
+  #define MCDFXS_CR_REUT_CH_ERR_TRIGGER_CTL_MCMAIN_Trigger_Out_On_Error_0_WID ( 1)
+  #define MCDFXS_CR_REUT_CH_ERR_TRIGGER_CTL_MCMAIN_Trigger_Out_On_Error_0_MSK (0x00000080)
+  #define MCDFXS_CR_REUT_CH_ERR_TRIGGER_CTL_MCMAIN_Trigger_Out_On_Error_0_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH_ERR_TRIGGER_CTL_MCMAIN_Trigger_Out_On_Error_0_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH_ERR_TRIGGER_CTL_MCMAIN_Trigger_Out_On_Error_1_OFF ( 8)
+  #define MCDFXS_CR_REUT_CH_ERR_TRIGGER_CTL_MCMAIN_Trigger_Out_On_Error_1_WID ( 1)
+  #define MCDFXS_CR_REUT_CH_ERR_TRIGGER_CTL_MCMAIN_Trigger_Out_On_Error_1_MSK (0x00000100)
+  #define MCDFXS_CR_REUT_CH_ERR_TRIGGER_CTL_MCMAIN_Trigger_Out_On_Error_1_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH_ERR_TRIGGER_CTL_MCMAIN_Trigger_Out_On_Error_1_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH_ERR_TRIGGER_CTL_MCMAIN_Trigger_Out_On_Channel_Test_Done_Status_0_OFF (15)
+  #define MCDFXS_CR_REUT_CH_ERR_TRIGGER_CTL_MCMAIN_Trigger_Out_On_Channel_Test_Done_Status_0_WID ( 1)
+  #define MCDFXS_CR_REUT_CH_ERR_TRIGGER_CTL_MCMAIN_Trigger_Out_On_Channel_Test_Done_Status_0_MSK (0x00008000)
+  #define MCDFXS_CR_REUT_CH_ERR_TRIGGER_CTL_MCMAIN_Trigger_Out_On_Channel_Test_Done_Status_0_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH_ERR_TRIGGER_CTL_MCMAIN_Trigger_Out_On_Channel_Test_Done_Status_0_DEF (0x00000000)
+  #define MCDFXS_CR_REUT_CH_ERR_TRIGGER_CTL_MCMAIN_Trigger_Out_On_Channel_Test_Done_Status_1_OFF (16)
+  #define MCDFXS_CR_REUT_CH_ERR_TRIGGER_CTL_MCMAIN_Trigger_Out_On_Channel_Test_Done_Status_1_WID ( 1)
+  #define MCDFXS_CR_REUT_CH_ERR_TRIGGER_CTL_MCMAIN_Trigger_Out_On_Channel_Test_Done_Status_1_MSK (0x00010000)
+  #define MCDFXS_CR_REUT_CH_ERR_TRIGGER_CTL_MCMAIN_Trigger_Out_On_Channel_Test_Done_Status_1_MAX (0x00000001)
+  #define MCDFXS_CR_REUT_CH_ERR_TRIGGER_CTL_MCMAIN_Trigger_Out_On_Channel_Test_Done_Status_1_DEF (0x00000000)
+
+#define MCDFXS_CR_REUT_CH_SEQ_LOOPCOUNT_LIMIT_MCMAIN_0_REG           (0x00004980)
+  #define MCDFXS_CR_REUT_CH_SEQ_LOOPCOUNT_LIMIT_MCMAIN_0_Loopcount_Limit_OFF (0)
+  #define MCDFXS_CR_REUT_CH_SEQ_LOOPCOUNT_LIMIT_MCMAIN_0_Loopcount_Limit_WID (32)
+  #define MCDFXS_CR_REUT_CH_SEQ_LOOPCOUNT_LIMIT_MCMAIN_0_Loopcount_Limit_MSK (0xFFFFFFFF)
+  #define MCDFXS_CR_REUT_CH_SEQ_LOOPCOUNT_LIMIT_MCMAIN_0_Loopcount_Limit_MAX (0xFFFFFFFF)
+  #define MCDFXS_CR_REUT_CH_SEQ_LOOPCOUNT_LIMIT_MCMAIN_0_Loopcount_Limit_DEF (0x00000000)
+
+#define MCDFXS_CR_REUT_CH_SEQ_LOOPCOUNT_LIMIT_MCMAIN_1_REG           (0x00004984)
+  #define MCDFXS_CR_REUT_CH_SEQ_LOOPCOUNT_LIMIT_MCMAIN_1_Loopcount_Limit_OFF (0)
+  #define MCDFXS_CR_REUT_CH_SEQ_LOOPCOUNT_LIMIT_MCMAIN_1_Loopcount_Limit_WID (32)
+  #define MCDFXS_CR_REUT_CH_SEQ_LOOPCOUNT_LIMIT_MCMAIN_1_Loopcount_Limit_MSK (0xFFFFFFFF)
+  #define MCDFXS_CR_REUT_CH_SEQ_LOOPCOUNT_LIMIT_MCMAIN_1_Loopcount_Limit_MAX (0xFFFFFFFF)
+  #define MCDFXS_CR_REUT_CH_SEQ_LOOPCOUNT_LIMIT_MCMAIN_1_Loopcount_Limit_DEF (0x00000000)
+
+#define MCSCHEDS_CR_TC_BANK_REG                                      (0x00004C00)
+  #define MCSCHEDS_CR_TC_BANK_tRCD_OFF                                 ( 0)
+  #define MCSCHEDS_CR_TC_BANK_tRCD_WID                                 ( 5)
+  #define MCSCHEDS_CR_TC_BANK_tRCD_MSK                                 (0x0000001F)
+  #define MCSCHEDS_CR_TC_BANK_tRCD_MAX                                 (0x0000001F)
+  #define MCSCHEDS_CR_TC_BANK_tRCD_DEF                                 (0x00000006)
+  #define MCSCHEDS_CR_TC_BANK_tRP_OFF                                  ( 5)
+  #define MCSCHEDS_CR_TC_BANK_tRP_WID                                  ( 5)
+  #define MCSCHEDS_CR_TC_BANK_tRP_MSK                                  (0x000003E0)
+  #define MCSCHEDS_CR_TC_BANK_tRP_MAX                                  (0x0000001F)
+  #define MCSCHEDS_CR_TC_BANK_tRP_DEF                                  (0x00000006)
+  #define MCSCHEDS_CR_TC_BANK_tRAS_OFF                                 (10)
+  #define MCSCHEDS_CR_TC_BANK_tRAS_WID                                 ( 6)
+  #define MCSCHEDS_CR_TC_BANK_tRAS_MSK                                 (0x0000FC00)
+  #define MCSCHEDS_CR_TC_BANK_tRAS_MAX                                 (0x0000003F)
+  #define MCSCHEDS_CR_TC_BANK_tRAS_DEF                                 (0x00000014)
+  #define MCSCHEDS_CR_TC_BANK_tRDPRE_OFF                               (16)
+  #define MCSCHEDS_CR_TC_BANK_tRDPRE_WID                               ( 4)
+  #define MCSCHEDS_CR_TC_BANK_tRDPRE_MSK                               (0x000F0000)
+  #define MCSCHEDS_CR_TC_BANK_tRDPRE_MAX                               (0x0000000F)
+  #define MCSCHEDS_CR_TC_BANK_tRDPRE_DEF                               (0x00000004)
+  #define MCSCHEDS_CR_TC_BANK_tWRPRE_OFF                               (20)
+  #define MCSCHEDS_CR_TC_BANK_tWRPRE_WID                               ( 6)
+  #define MCSCHEDS_CR_TC_BANK_tWRPRE_MSK                               (0x03F00000)
+  #define MCSCHEDS_CR_TC_BANK_tWRPRE_MAX                               (0x0000003F)
+  #define MCSCHEDS_CR_TC_BANK_tWRPRE_DEF                               (0x00000004)
+  #define MCSCHEDS_CR_TC_BANK_tRRD_OFF                                 (26)
+  #define MCSCHEDS_CR_TC_BANK_tRRD_WID                                 ( 4)
+  #define MCSCHEDS_CR_TC_BANK_tRRD_MSK                                 (0x3C000000)
+  #define MCSCHEDS_CR_TC_BANK_tRRD_MAX                                 (0x0000000F)
+  #define MCSCHEDS_CR_TC_BANK_tRRD_DEF                                 (0x00000004)
+  #define MCSCHEDS_CR_TC_BANK_tRPab_ext_OFF                            (30)
+  #define MCSCHEDS_CR_TC_BANK_tRPab_ext_WID                            ( 2)
+  #define MCSCHEDS_CR_TC_BANK_tRPab_ext_MSK                            (0xC0000000)
+  #define MCSCHEDS_CR_TC_BANK_tRPab_ext_MAX                            (0x00000003)
+  #define MCSCHEDS_CR_TC_BANK_tRPab_ext_DEF                            (0x00000000)
+
+#define MCSCHEDS_CR_TC_BANK_RANK_A_REG                               (0x00004C04)
+  #define MCSCHEDS_CR_TC_BANK_RANK_A_tCKE_OFF                          ( 0)
+  #define MCSCHEDS_CR_TC_BANK_RANK_A_tCKE_WID                          ( 4)
+  #define MCSCHEDS_CR_TC_BANK_RANK_A_tCKE_MSK                          (0x0000000F)
+  #define MCSCHEDS_CR_TC_BANK_RANK_A_tCKE_MAX                          (0x0000000F)
+  #define MCSCHEDS_CR_TC_BANK_RANK_A_tCKE_DEF                          (0x00000003)
+  #define MCSCHEDS_CR_TC_BANK_RANK_A_tFAW_OFF                          ( 4)
+  #define MCSCHEDS_CR_TC_BANK_RANK_A_tFAW_WID                          ( 8)
+  #define MCSCHEDS_CR_TC_BANK_RANK_A_tFAW_MSK                          (0x00000FF0)
+  #define MCSCHEDS_CR_TC_BANK_RANK_A_tFAW_MAX                          (0x000000FF)
+  #define MCSCHEDS_CR_TC_BANK_RANK_A_tFAW_DEF                          (0x00000010)
+  #define MCSCHEDS_CR_TC_BANK_RANK_A_tRDRD_OFF                         (12)
+  #define MCSCHEDS_CR_TC_BANK_RANK_A_tRDRD_WID                         ( 3)
+  #define MCSCHEDS_CR_TC_BANK_RANK_A_tRDRD_MSK                         (0x00007000)
+  #define MCSCHEDS_CR_TC_BANK_RANK_A_tRDRD_MAX                         (0x00000007)
+  #define MCSCHEDS_CR_TC_BANK_RANK_A_tRDRD_DEF                         (0x00000004)
+  #define MCSCHEDS_CR_TC_BANK_RANK_A_tRDRD_dr_OFF                      (15)
+  #define MCSCHEDS_CR_TC_BANK_RANK_A_tRDRD_dr_WID                      ( 4)
+  #define MCSCHEDS_CR_TC_BANK_RANK_A_tRDRD_dr_MSK                      (0x00078000)
+  #define MCSCHEDS_CR_TC_BANK_RANK_A_tRDRD_dr_MAX                      (0x0000000F)
+  #define MCSCHEDS_CR_TC_BANK_RANK_A_tRDRD_dr_DEF                      (0x00000004)
+  #define MCSCHEDS_CR_TC_BANK_RANK_A_tRDRD_dd_OFF                      (19)
+  #define MCSCHEDS_CR_TC_BANK_RANK_A_tRDRD_dd_WID                      ( 4)
+  #define MCSCHEDS_CR_TC_BANK_RANK_A_tRDRD_dd_MSK                      (0x00780000)
+  #define MCSCHEDS_CR_TC_BANK_RANK_A_tRDRD_dd_MAX                      (0x0000000F)
+  #define MCSCHEDS_CR_TC_BANK_RANK_A_tRDRD_dd_DEF                      (0x00000004)
+  #define MCSCHEDS_CR_TC_BANK_RANK_A_tRDPDEN_OFF                       (23)
+  #define MCSCHEDS_CR_TC_BANK_RANK_A_tRDPDEN_WID                       ( 5)
+  #define MCSCHEDS_CR_TC_BANK_RANK_A_tRDPDEN_MSK                       (0x0F800000)
+  #define MCSCHEDS_CR_TC_BANK_RANK_A_tRDPDEN_MAX                       (0x0000001F)
+  #define MCSCHEDS_CR_TC_BANK_RANK_A_tRDPDEN_DEF                       (0x00000004)
+  #define MCSCHEDS_CR_TC_BANK_RANK_A_CMD_3st_OFF                       (29)
+  #define MCSCHEDS_CR_TC_BANK_RANK_A_CMD_3st_WID                       ( 1)
+  #define MCSCHEDS_CR_TC_BANK_RANK_A_CMD_3st_MSK                       (0x20000000)
+  #define MCSCHEDS_CR_TC_BANK_RANK_A_CMD_3st_MAX                       (0x00000001)
+  #define MCSCHEDS_CR_TC_BANK_RANK_A_CMD_3st_DEF                       (0x00000000)
+  #define MCSCHEDS_CR_TC_BANK_RANK_A_CMD_stretch_OFF                   (30)
+  #define MCSCHEDS_CR_TC_BANK_RANK_A_CMD_stretch_WID                   ( 2)
+  #define MCSCHEDS_CR_TC_BANK_RANK_A_CMD_stretch_MSK                   (0xC0000000)
+  #define MCSCHEDS_CR_TC_BANK_RANK_A_CMD_stretch_MAX                   (0x00000003)
+  #define MCSCHEDS_CR_TC_BANK_RANK_A_CMD_stretch_DEF                   (0x00000002)
+
+#define MCSCHEDS_CR_TC_BANK_RANK_B_REG                               (0x00004C08)
+  #define MCSCHEDS_CR_TC_BANK_RANK_B_tWRRD_OFF                         ( 0)
+  #define MCSCHEDS_CR_TC_BANK_RANK_B_tWRRD_WID                         ( 6)
+  #define MCSCHEDS_CR_TC_BANK_RANK_B_tWRRD_MSK                         (0x0000003F)
+  #define MCSCHEDS_CR_TC_BANK_RANK_B_tWRRD_MAX                         (0x0000003F)
+  #define MCSCHEDS_CR_TC_BANK_RANK_B_tWRRD_DEF                         (0x00000005)
+  #define MCSCHEDS_CR_TC_BANK_RANK_B_tWRRD_dr_OFF                      ( 6)
+  #define MCSCHEDS_CR_TC_BANK_RANK_B_tWRRD_dr_WID                      ( 4)
+  #define MCSCHEDS_CR_TC_BANK_RANK_B_tWRRD_dr_MSK                      (0x000003C0)
+  #define MCSCHEDS_CR_TC_BANK_RANK_B_tWRRD_dr_MAX                      (0x0000000F)
+  #define MCSCHEDS_CR_TC_BANK_RANK_B_tWRRD_dr_DEF                      (0x00000005)
+  #define MCSCHEDS_CR_TC_BANK_RANK_B_tWRRD_dd_OFF                      (10)
+  #define MCSCHEDS_CR_TC_BANK_RANK_B_tWRRD_dd_WID                      ( 4)
+  #define MCSCHEDS_CR_TC_BANK_RANK_B_tWRRD_dd_MSK                      (0x00003C00)
+  #define MCSCHEDS_CR_TC_BANK_RANK_B_tWRRD_dd_MAX                      (0x0000000F)
+  #define MCSCHEDS_CR_TC_BANK_RANK_B_tWRRD_dd_DEF                      (0x00000005)
+  #define MCSCHEDS_CR_TC_BANK_RANK_B_tWRWR_OFF                         (14)
+  #define MCSCHEDS_CR_TC_BANK_RANK_B_tWRWR_WID                         ( 3)
+  #define MCSCHEDS_CR_TC_BANK_RANK_B_tWRWR_MSK                         (0x0001C000)
+  #define MCSCHEDS_CR_TC_BANK_RANK_B_tWRWR_MAX                         (0x00000007)
+  #define MCSCHEDS_CR_TC_BANK_RANK_B_tWRWR_DEF                         (0x00000005)
+  #define MCSCHEDS_CR_TC_BANK_RANK_B_tWRWR_dr_OFF                      (17)
+  #define MCSCHEDS_CR_TC_BANK_RANK_B_tWRWR_dr_WID                      ( 4)
+  #define MCSCHEDS_CR_TC_BANK_RANK_B_tWRWR_dr_MSK                      (0x001E0000)
+  #define MCSCHEDS_CR_TC_BANK_RANK_B_tWRWR_dr_MAX                      (0x0000000F)
+  #define MCSCHEDS_CR_TC_BANK_RANK_B_tWRWR_dr_DEF                      (0x00000005)
+  #define MCSCHEDS_CR_TC_BANK_RANK_B_tWRWR_dd_OFF                      (21)
+  #define MCSCHEDS_CR_TC_BANK_RANK_B_tWRWR_dd_WID                      ( 4)
+  #define MCSCHEDS_CR_TC_BANK_RANK_B_tWRWR_dd_MSK                      (0x01E00000)
+  #define MCSCHEDS_CR_TC_BANK_RANK_B_tWRWR_dd_MAX                      (0x0000000F)
+  #define MCSCHEDS_CR_TC_BANK_RANK_B_tWRWR_dd_DEF                      (0x00000005)
+  #define MCSCHEDS_CR_TC_BANK_RANK_B_tWRPDEN_OFF                       (25)
+  #define MCSCHEDS_CR_TC_BANK_RANK_B_tWRPDEN_WID                       ( 6)
+  #define MCSCHEDS_CR_TC_BANK_RANK_B_tWRPDEN_MSK                       (0x7E000000)
+  #define MCSCHEDS_CR_TC_BANK_RANK_B_tWRPDEN_MAX                       (0x0000003F)
+  #define MCSCHEDS_CR_TC_BANK_RANK_B_tWRPDEN_DEF                       (0x00000005)
+  #define MCSCHEDS_CR_TC_BANK_RANK_B_Dec_WRD_OFF                       (31)
+  #define MCSCHEDS_CR_TC_BANK_RANK_B_Dec_WRD_WID                       ( 1)
+  #define MCSCHEDS_CR_TC_BANK_RANK_B_Dec_WRD_MSK                       (0x80000000)
+  #define MCSCHEDS_CR_TC_BANK_RANK_B_Dec_WRD_MAX                       (0x00000001)
+  #define MCSCHEDS_CR_TC_BANK_RANK_B_Dec_WRD_DEF                       (0x00000000)
+
+#define MCSCHEDS_CR_TC_BANK_RANK_C_REG                               (0x00004C0C)
+  #define MCSCHEDS_CR_TC_BANK_RANK_C_tXPDLL_OFF                        ( 0)
+  #define MCSCHEDS_CR_TC_BANK_RANK_C_tXPDLL_WID                        ( 6)
+  #define MCSCHEDS_CR_TC_BANK_RANK_C_tXPDLL_MSK                        (0x0000003F)
+  #define MCSCHEDS_CR_TC_BANK_RANK_C_tXPDLL_MAX                        (0x0000003F)
+  #define MCSCHEDS_CR_TC_BANK_RANK_C_tXPDLL_DEF                        (0x0000000A)
+  #define MCSCHEDS_CR_TC_BANK_RANK_C_tXP_OFF                           ( 6)
+  #define MCSCHEDS_CR_TC_BANK_RANK_C_tXP_WID                           ( 4)
+  #define MCSCHEDS_CR_TC_BANK_RANK_C_tXP_MSK                           (0x000003C0)
+  #define MCSCHEDS_CR_TC_BANK_RANK_C_tXP_MAX                           (0x0000000F)
+  #define MCSCHEDS_CR_TC_BANK_RANK_C_tXP_DEF                           (0x00000003)
+  #define MCSCHEDS_CR_TC_BANK_RANK_C_TAONPD_OFF                        (10)
+  #define MCSCHEDS_CR_TC_BANK_RANK_C_TAONPD_WID                        ( 4)
+  #define MCSCHEDS_CR_TC_BANK_RANK_C_TAONPD_MSK                        (0x00003C00)
+  #define MCSCHEDS_CR_TC_BANK_RANK_C_TAONPD_MAX                        (0x0000000F)
+  #define MCSCHEDS_CR_TC_BANK_RANK_C_TAONPD_DEF                        (0x00000009)
+  #define MCSCHEDS_CR_TC_BANK_RANK_C_tRDWR_OFF                         (14)
+  #define MCSCHEDS_CR_TC_BANK_RANK_C_tRDWR_WID                         ( 5)
+  #define MCSCHEDS_CR_TC_BANK_RANK_C_tRDWR_MSK                         (0x0007C000)
+  #define MCSCHEDS_CR_TC_BANK_RANK_C_tRDWR_MAX                         (0x0000001F)
+  #define MCSCHEDS_CR_TC_BANK_RANK_C_tRDWR_DEF                         (0x00000005)
+  #define MCSCHEDS_CR_TC_BANK_RANK_C_tRDWR_dr_OFF                      (19)
+  #define MCSCHEDS_CR_TC_BANK_RANK_C_tRDWR_dr_WID                      ( 5)
+  #define MCSCHEDS_CR_TC_BANK_RANK_C_tRDWR_dr_MSK                      (0x00F80000)
+  #define MCSCHEDS_CR_TC_BANK_RANK_C_tRDWR_dr_MAX                      (0x0000001F)
+  #define MCSCHEDS_CR_TC_BANK_RANK_C_tRDWR_dr_DEF                      (0x00000005)
+  #define MCSCHEDS_CR_TC_BANK_RANK_C_tRDWR_dd_OFF                      (24)
+  #define MCSCHEDS_CR_TC_BANK_RANK_C_tRDWR_dd_WID                      ( 5)
+  #define MCSCHEDS_CR_TC_BANK_RANK_C_tRDWR_dd_MSK                      (0x1F000000)
+  #define MCSCHEDS_CR_TC_BANK_RANK_C_tRDWR_dd_MAX                      (0x0000001F)
+  #define MCSCHEDS_CR_TC_BANK_RANK_C_tRDWR_dd_DEF                      (0x00000005)
+
+#define MCSCHEDS_CR_CMD_RATE_REG                                     (0x00004C10)
+  #define MCSCHEDS_CR_CMD_RATE_enable_cmd_rate_limit_OFF               ( 0)
+  #define MCSCHEDS_CR_CMD_RATE_enable_cmd_rate_limit_WID               ( 1)
+  #define MCSCHEDS_CR_CMD_RATE_enable_cmd_rate_limit_MSK               (0x00000001)
+  #define MCSCHEDS_CR_CMD_RATE_enable_cmd_rate_limit_MAX               (0x00000001)
+  #define MCSCHEDS_CR_CMD_RATE_enable_cmd_rate_limit_DEF               (0x00000000)
+  #define MCSCHEDS_CR_CMD_RATE_cmd_rate_limit_OFF                      ( 1)
+  #define MCSCHEDS_CR_CMD_RATE_cmd_rate_limit_WID                      ( 3)
+  #define MCSCHEDS_CR_CMD_RATE_cmd_rate_limit_MSK                      (0x0000000E)
+  #define MCSCHEDS_CR_CMD_RATE_cmd_rate_limit_MAX                      (0x00000007)
+  #define MCSCHEDS_CR_CMD_RATE_cmd_rate_limit_DEF                      (0x00000004)
+  #define MCSCHEDS_CR_CMD_RATE_reset_on_command_OFF                    ( 4)
+  #define MCSCHEDS_CR_CMD_RATE_reset_on_command_WID                    ( 4)
+  #define MCSCHEDS_CR_CMD_RATE_reset_on_command_MSK                    (0x000000F0)
+  #define MCSCHEDS_CR_CMD_RATE_reset_on_command_MAX                    (0x0000000F)
+  #define MCSCHEDS_CR_CMD_RATE_reset_on_command_DEF                    (0x00000000)
+  #define MCSCHEDS_CR_CMD_RATE_reset_delay_OFF                         ( 8)
+  #define MCSCHEDS_CR_CMD_RATE_reset_delay_WID                         ( 4)
+  #define MCSCHEDS_CR_CMD_RATE_reset_delay_MSK                         (0x00000F00)
+  #define MCSCHEDS_CR_CMD_RATE_reset_delay_MAX                         (0x0000000F)
+  #define MCSCHEDS_CR_CMD_RATE_reset_delay_DEF                         (0x00000000)
+  #define MCSCHEDS_CR_CMD_RATE_ck_to_cke_delay_OFF                     (12)
+  #define MCSCHEDS_CR_CMD_RATE_ck_to_cke_delay_WID                     ( 2)
+  #define MCSCHEDS_CR_CMD_RATE_ck_to_cke_delay_MSK                     (0x00003000)
+  #define MCSCHEDS_CR_CMD_RATE_ck_to_cke_delay_MAX                     (0x00000003)
+  #define MCSCHEDS_CR_CMD_RATE_ck_to_cke_delay_DEF                     (0x00000001)
+  #define MCSCHEDS_CR_CMD_RATE_spare_OFF                               (14)
+  #define MCSCHEDS_CR_CMD_RATE_spare_WID                               (17)
+  #define MCSCHEDS_CR_CMD_RATE_spare_MSK                               (0x7FFFC000)
+  #define MCSCHEDS_CR_CMD_RATE_spare_MAX                               (0x0001FFFF)
+  #define MCSCHEDS_CR_CMD_RATE_spare_DEF                               (0x00000000)
+  #define MCSCHEDS_CR_CMD_RATE_init_mrw_2n_cs_OFF                      (31)
+  #define MCSCHEDS_CR_CMD_RATE_init_mrw_2n_cs_WID                      ( 1)
+  #define MCSCHEDS_CR_CMD_RATE_init_mrw_2n_cs_MSK                      (0x80000000)
+  #define MCSCHEDS_CR_CMD_RATE_init_mrw_2n_cs_MAX                      (0x00000001)
+  #define MCSCHEDS_CR_CMD_RATE_init_mrw_2n_cs_DEF                      (0x00000000)
+
+#define MCSCHEDS_CR_TC_BANK_RANK_D_REG                               (0x00004C14)
+  #define MCSCHEDS_CR_TC_BANK_RANK_D_tCL_OFF                           ( 0)
+  #define MCSCHEDS_CR_TC_BANK_RANK_D_tCL_WID                           ( 5)
+  #define MCSCHEDS_CR_TC_BANK_RANK_D_tCL_MSK                           (0x0000001F)
+  #define MCSCHEDS_CR_TC_BANK_RANK_D_tCL_MAX                           (0x0000001F)
+  #define MCSCHEDS_CR_TC_BANK_RANK_D_tCL_DEF                           (0x00000006)
+  #define MCSCHEDS_CR_TC_BANK_RANK_D_tWCL_OFF                          ( 5)
+  #define MCSCHEDS_CR_TC_BANK_RANK_D_tWCL_WID                          ( 5)
+  #define MCSCHEDS_CR_TC_BANK_RANK_D_tWCL_MSK                          (0x000003E0)
+  #define MCSCHEDS_CR_TC_BANK_RANK_D_tWCL_MAX                          (0x0000001F)
+  #define MCSCHEDS_CR_TC_BANK_RANK_D_tWCL_DEF                          (0x00000006)
+  #define MCSCHEDS_CR_TC_BANK_RANK_D_tCPDED_OFF                        (10)
+  #define MCSCHEDS_CR_TC_BANK_RANK_D_tCPDED_WID                        ( 2)
+  #define MCSCHEDS_CR_TC_BANK_RANK_D_tCPDED_MSK                        (0x00000C00)
+  #define MCSCHEDS_CR_TC_BANK_RANK_D_tCPDED_MAX                        (0x00000003)
+  #define MCSCHEDS_CR_TC_BANK_RANK_D_tCPDED_DEF                        (0x00000001)
+  #define MCSCHEDS_CR_TC_BANK_RANK_D_tPRPDEN_OFF                       (12)
+  #define MCSCHEDS_CR_TC_BANK_RANK_D_tPRPDEN_WID                       ( 2)
+  #define MCSCHEDS_CR_TC_BANK_RANK_D_tPRPDEN_MSK                       (0x00003000)
+  #define MCSCHEDS_CR_TC_BANK_RANK_D_tPRPDEN_MAX                       (0x00000003)
+  #define MCSCHEDS_CR_TC_BANK_RANK_D_tPRPDEN_DEF                       (0x00000001)
+  #define MCSCHEDS_CR_TC_BANK_RANK_D_Odt_Read_Delay_OFF                (14)
+  #define MCSCHEDS_CR_TC_BANK_RANK_D_Odt_Read_Delay_WID                ( 3)
+  #define MCSCHEDS_CR_TC_BANK_RANK_D_Odt_Read_Delay_MSK                (0x0001C000)
+  #define MCSCHEDS_CR_TC_BANK_RANK_D_Odt_Read_Delay_MAX                (0x00000007)
+  #define MCSCHEDS_CR_TC_BANK_RANK_D_Odt_Read_Delay_DEF                (0x00000000)
+  #define MCSCHEDS_CR_TC_BANK_RANK_D_Odt_Read_Duration_OFF             (17)
+  #define MCSCHEDS_CR_TC_BANK_RANK_D_Odt_Read_Duration_WID             ( 2)
+  #define MCSCHEDS_CR_TC_BANK_RANK_D_Odt_Read_Duration_MSK             (0x00060000)
+  #define MCSCHEDS_CR_TC_BANK_RANK_D_Odt_Read_Duration_MAX             (0x00000003)
+  #define MCSCHEDS_CR_TC_BANK_RANK_D_Odt_Read_Duration_DEF             (0x00000000)
+  #define MCSCHEDS_CR_TC_BANK_RANK_D_Odt_Write_Duration_OFF            (19)
+  #define MCSCHEDS_CR_TC_BANK_RANK_D_Odt_Write_Duration_WID            ( 2)
+  #define MCSCHEDS_CR_TC_BANK_RANK_D_Odt_Write_Duration_MSK            (0x00180000)
+  #define MCSCHEDS_CR_TC_BANK_RANK_D_Odt_Write_Duration_MAX            (0x00000003)
+  #define MCSCHEDS_CR_TC_BANK_RANK_D_Odt_Write_Duration_DEF            (0x00000000)
+  #define MCSCHEDS_CR_TC_BANK_RANK_D_Odt_Write_Duration_Ult_OFF        (19)
+  #define MCSCHEDS_CR_TC_BANK_RANK_D_Odt_Write_Duration_Ult_WID        ( 3)
+  #define MCSCHEDS_CR_TC_BANK_RANK_D_Odt_Write_Duration_Ult_MSK        (0x00380000)
+  #define MCSCHEDS_CR_TC_BANK_RANK_D_Odt_Write_Duration_Ult_MAX        (0x00000007)
+  #define MCSCHEDS_CR_TC_BANK_RANK_D_Odt_Write_Duration_Ult_DEF        (0x00000000)
+  #define MCSCHEDS_CR_TC_BANK_RANK_D_Odt_Write_Delay_Ult_OFF           (22)
+  #define MCSCHEDS_CR_TC_BANK_RANK_D_Odt_Write_Delay_Ult_WID           ( 3)
+  #define MCSCHEDS_CR_TC_BANK_RANK_D_Odt_Write_Delay_Ult_MSK           (0x01C00000)
+  #define MCSCHEDS_CR_TC_BANK_RANK_D_Odt_Write_Delay_Ult_MAX           (0x00000007)
+  #define MCSCHEDS_CR_TC_BANK_RANK_D_Odt_Write_Delay_Ult_DEF           (0x00000000)
+  #define MCSCHEDS_CR_TC_BANK_RANK_D_Odt_Always_Rank0_Ult_OFF          (25)
+  #define MCSCHEDS_CR_TC_BANK_RANK_D_Odt_Always_Rank0_Ult_WID          ( 1)
+  #define MCSCHEDS_CR_TC_BANK_RANK_D_Odt_Always_Rank0_Ult_MSK          (0x02000000)
+  #define MCSCHEDS_CR_TC_BANK_RANK_D_Odt_Always_Rank0_Ult_MAX          (0x00000001)
+  #define MCSCHEDS_CR_TC_BANK_RANK_D_Odt_Always_Rank0_Ult_DEF          (0x00000000)
+  #define MCSCHEDS_CR_TC_BANK_RANK_D_cmd_delay_Ult_OFF                 (26)
+  #define MCSCHEDS_CR_TC_BANK_RANK_D_cmd_delay_Ult_WID                 ( 2)
+  #define MCSCHEDS_CR_TC_BANK_RANK_D_cmd_delay_Ult_MSK                 (0x0C000000)
+  #define MCSCHEDS_CR_TC_BANK_RANK_D_cmd_delay_Ult_MAX                 (0x00000003)
+  #define MCSCHEDS_CR_TC_BANK_RANK_D_cmd_delay_Ult_DEF                 (0x00000000)
+
+#define MCSCHEDS_CR_SCHED_CBIT_REG                                   (0x00004C20)
+  #define MCSCHEDS_CR_SCHED_CBIT_dis_opp_cas_OFF                       ( 0)
+  #define MCSCHEDS_CR_SCHED_CBIT_dis_opp_cas_WID                       ( 1)
+  #define MCSCHEDS_CR_SCHED_CBIT_dis_opp_cas_MSK                       (0x00000001)
+  #define MCSCHEDS_CR_SCHED_CBIT_dis_opp_cas_MAX                       (0x00000001)
+  #define MCSCHEDS_CR_SCHED_CBIT_dis_opp_cas_DEF                       (0x00000001)
+  #define MCSCHEDS_CR_SCHED_CBIT_dis_opp_is_cas_OFF                    ( 1)
+  #define MCSCHEDS_CR_SCHED_CBIT_dis_opp_is_cas_WID                    ( 1)
+  #define MCSCHEDS_CR_SCHED_CBIT_dis_opp_is_cas_MSK                    (0x00000002)
+  #define MCSCHEDS_CR_SCHED_CBIT_dis_opp_is_cas_MAX                    (0x00000001)
+  #define MCSCHEDS_CR_SCHED_CBIT_dis_opp_is_cas_DEF                    (0x00000000)
+  #define MCSCHEDS_CR_SCHED_CBIT_dis_opp_ras_OFF                       ( 2)
+  #define MCSCHEDS_CR_SCHED_CBIT_dis_opp_ras_WID                       ( 1)
+  #define MCSCHEDS_CR_SCHED_CBIT_dis_opp_ras_MSK                       (0x00000004)
+  #define MCSCHEDS_CR_SCHED_CBIT_dis_opp_ras_MAX                       (0x00000001)
+  #define MCSCHEDS_CR_SCHED_CBIT_dis_opp_ras_DEF                       (0x00000001)
+  #define MCSCHEDS_CR_SCHED_CBIT_dis_opp_is_ras_OFF                    ( 3)
+  #define MCSCHEDS_CR_SCHED_CBIT_dis_opp_is_ras_WID                    ( 1)
+  #define MCSCHEDS_CR_SCHED_CBIT_dis_opp_is_ras_MSK                    (0x00000008)
+  #define MCSCHEDS_CR_SCHED_CBIT_dis_opp_is_ras_MAX                    (0x00000001)
+  #define MCSCHEDS_CR_SCHED_CBIT_dis_opp_is_ras_DEF                    (0x00000000)
+  #define MCSCHEDS_CR_SCHED_CBIT_dis_1c_byp_OFF                        ( 4)
+  #define MCSCHEDS_CR_SCHED_CBIT_dis_1c_byp_WID                        ( 1)
+  #define MCSCHEDS_CR_SCHED_CBIT_dis_1c_byp_MSK                        (0x00000010)
+  #define MCSCHEDS_CR_SCHED_CBIT_dis_1c_byp_MAX                        (0x00000001)
+  #define MCSCHEDS_CR_SCHED_CBIT_dis_1c_byp_DEF                        (0x00000001)
+  #define MCSCHEDS_CR_SCHED_CBIT_dis_2c_byp_OFF                        ( 5)
+  #define MCSCHEDS_CR_SCHED_CBIT_dis_2c_byp_WID                        ( 1)
+  #define MCSCHEDS_CR_SCHED_CBIT_dis_2c_byp_MSK                        (0x00000020)
+  #define MCSCHEDS_CR_SCHED_CBIT_dis_2c_byp_MAX                        (0x00000001)
+  #define MCSCHEDS_CR_SCHED_CBIT_dis_2c_byp_DEF                        (0x00000000)
+  #define MCSCHEDS_CR_SCHED_CBIT_dis_deprd_opt_OFF                     ( 6)
+  #define MCSCHEDS_CR_SCHED_CBIT_dis_deprd_opt_WID                     ( 1)
+  #define MCSCHEDS_CR_SCHED_CBIT_dis_deprd_opt_MSK                     (0x00000040)
+  #define MCSCHEDS_CR_SCHED_CBIT_dis_deprd_opt_MAX                     (0x00000001)
+  #define MCSCHEDS_CR_SCHED_CBIT_dis_deprd_opt_DEF                     (0x00000000)
+  #define MCSCHEDS_CR_SCHED_CBIT_dis_pt_it_OFF                         ( 7)
+  #define MCSCHEDS_CR_SCHED_CBIT_dis_pt_it_WID                         ( 1)
+  #define MCSCHEDS_CR_SCHED_CBIT_dis_pt_it_MSK                         (0x00000080)
+  #define MCSCHEDS_CR_SCHED_CBIT_dis_pt_it_MAX                         (0x00000001)
+  #define MCSCHEDS_CR_SCHED_CBIT_dis_pt_it_DEF                         (0x00000000)
+  #define MCSCHEDS_CR_SCHED_CBIT_dis_prcnt_ring_OFF                    ( 8)
+  #define MCSCHEDS_CR_SCHED_CBIT_dis_prcnt_ring_WID                    ( 1)
+  #define MCSCHEDS_CR_SCHED_CBIT_dis_prcnt_ring_MSK                    (0x00000100)
+  #define MCSCHEDS_CR_SCHED_CBIT_dis_prcnt_ring_MAX                    (0x00000001)
+  #define MCSCHEDS_CR_SCHED_CBIT_dis_prcnt_ring_DEF                    (0x00000000)
+  #define MCSCHEDS_CR_SCHED_CBIT_dis_prcnt_sa_OFF                      ( 9)
+  #define MCSCHEDS_CR_SCHED_CBIT_dis_prcnt_sa_WID                      ( 1)
+  #define MCSCHEDS_CR_SCHED_CBIT_dis_prcnt_sa_MSK                      (0x00000200)
+  #define MCSCHEDS_CR_SCHED_CBIT_dis_prcnt_sa_MAX                      (0x00000001)
+  #define MCSCHEDS_CR_SCHED_CBIT_dis_prcnt_sa_DEF                      (0x00000000)
+  #define MCSCHEDS_CR_SCHED_CBIT_dis_blkr_ph_OFF                       (10)
+  #define MCSCHEDS_CR_SCHED_CBIT_dis_blkr_ph_WID                       ( 1)
+  #define MCSCHEDS_CR_SCHED_CBIT_dis_blkr_ph_MSK                       (0x00000400)
+  #define MCSCHEDS_CR_SCHED_CBIT_dis_blkr_ph_MAX                       (0x00000001)
+  #define MCSCHEDS_CR_SCHED_CBIT_dis_blkr_ph_DEF                       (0x00000000)
+  #define MCSCHEDS_CR_SCHED_CBIT_dis_blkr_pe_OFF                       (11)
+  #define MCSCHEDS_CR_SCHED_CBIT_dis_blkr_pe_WID                       ( 1)
+  #define MCSCHEDS_CR_SCHED_CBIT_dis_blkr_pe_MSK                       (0x00000800)
+  #define MCSCHEDS_CR_SCHED_CBIT_dis_blkr_pe_MAX                       (0x00000001)
+  #define MCSCHEDS_CR_SCHED_CBIT_dis_blkr_pe_DEF                       (0x00000000)
+  #define MCSCHEDS_CR_SCHED_CBIT_dis_blkr_pm_OFF                       (12)
+  #define MCSCHEDS_CR_SCHED_CBIT_dis_blkr_pm_WID                       ( 1)
+  #define MCSCHEDS_CR_SCHED_CBIT_dis_blkr_pm_MSK                       (0x00001000)
+  #define MCSCHEDS_CR_SCHED_CBIT_dis_blkr_pm_MAX                       (0x00000001)
+  #define MCSCHEDS_CR_SCHED_CBIT_dis_blkr_pm_DEF                       (0x00000000)
+  #define MCSCHEDS_CR_SCHED_CBIT_dis_odt_OFF                           (13)
+  #define MCSCHEDS_CR_SCHED_CBIT_dis_odt_WID                           ( 1)
+  #define MCSCHEDS_CR_SCHED_CBIT_dis_odt_MSK                           (0x00002000)
+  #define MCSCHEDS_CR_SCHED_CBIT_dis_odt_MAX                           (0x00000001)
+  #define MCSCHEDS_CR_SCHED_CBIT_dis_odt_DEF                           (0x00000000)
+  #define MCSCHEDS_CR_SCHED_CBIT_OE_alw_off_OFF                        (14)
+  #define MCSCHEDS_CR_SCHED_CBIT_OE_alw_off_WID                        ( 1)
+  #define MCSCHEDS_CR_SCHED_CBIT_OE_alw_off_MSK                        (0x00004000)
+  #define MCSCHEDS_CR_SCHED_CBIT_OE_alw_off_MAX                        (0x00000001)
+  #define MCSCHEDS_CR_SCHED_CBIT_OE_alw_off_DEF                        (0x00000000)
+  #define MCSCHEDS_CR_SCHED_CBIT_dis_aom_OFF                           (16)
+  #define MCSCHEDS_CR_SCHED_CBIT_dis_aom_WID                           ( 1)
+  #define MCSCHEDS_CR_SCHED_CBIT_dis_aom_MSK                           (0x00010000)
+  #define MCSCHEDS_CR_SCHED_CBIT_dis_aom_MAX                           (0x00000001)
+  #define MCSCHEDS_CR_SCHED_CBIT_dis_aom_DEF                           (0x00000000)
+  #define MCSCHEDS_CR_SCHED_CBIT_block_rpq_OFF                         (17)
+  #define MCSCHEDS_CR_SCHED_CBIT_block_rpq_WID                         ( 1)
+  #define MCSCHEDS_CR_SCHED_CBIT_block_rpq_MSK                         (0x00020000)
+  #define MCSCHEDS_CR_SCHED_CBIT_block_rpq_MAX                         (0x00000001)
+  #define MCSCHEDS_CR_SCHED_CBIT_block_rpq_DEF                         (0x00000000)
+  #define MCSCHEDS_CR_SCHED_CBIT_block_wpq_OFF                         (18)
+  #define MCSCHEDS_CR_SCHED_CBIT_block_wpq_WID                         ( 1)
+  #define MCSCHEDS_CR_SCHED_CBIT_block_wpq_MSK                         (0x00040000)
+  #define MCSCHEDS_CR_SCHED_CBIT_block_wpq_MAX                         (0x00000001)
+  #define MCSCHEDS_CR_SCHED_CBIT_block_wpq_DEF                         (0x00000000)
+  #define MCSCHEDS_CR_SCHED_CBIT_invert_align_OFF                      (19)
+  #define MCSCHEDS_CR_SCHED_CBIT_invert_align_WID                      ( 1)
+  #define MCSCHEDS_CR_SCHED_CBIT_invert_align_MSK                      (0x00080000)
+  #define MCSCHEDS_CR_SCHED_CBIT_invert_align_MAX                      (0x00000001)
+  #define MCSCHEDS_CR_SCHED_CBIT_invert_align_DEF                      (0x00000000)
+  #define MCSCHEDS_CR_SCHED_CBIT_dis_write_gap_OFF                     (20)
+  #define MCSCHEDS_CR_SCHED_CBIT_dis_write_gap_WID                     ( 1)
+  #define MCSCHEDS_CR_SCHED_CBIT_dis_write_gap_MSK                     (0x00100000)
+  #define MCSCHEDS_CR_SCHED_CBIT_dis_write_gap_MAX                     (0x00000001)
+  #define MCSCHEDS_CR_SCHED_CBIT_dis_write_gap_DEF                     (0x00000001)
+  #define MCSCHEDS_CR_SCHED_CBIT_dis_zq_OFF                            (21)
+  #define MCSCHEDS_CR_SCHED_CBIT_dis_zq_WID                            ( 1)
+  #define MCSCHEDS_CR_SCHED_CBIT_dis_zq_MSK                            (0x00200000)
+  #define MCSCHEDS_CR_SCHED_CBIT_dis_zq_MAX                            (0x00000001)
+  #define MCSCHEDS_CR_SCHED_CBIT_dis_zq_DEF                            (0x00000000)
+  #define MCSCHEDS_CR_SCHED_CBIT_dis_tt_OFF                            (22)
+  #define MCSCHEDS_CR_SCHED_CBIT_dis_tt_WID                            ( 1)
+  #define MCSCHEDS_CR_SCHED_CBIT_dis_tt_MSK                            (0x00400000)
+  #define MCSCHEDS_CR_SCHED_CBIT_dis_tt_MAX                            (0x00000001)
+  #define MCSCHEDS_CR_SCHED_CBIT_dis_tt_DEF                            (0x00000000)
+  #define MCSCHEDS_CR_SCHED_CBIT_dis_opp_ref_OFF                       (23)
+  #define MCSCHEDS_CR_SCHED_CBIT_dis_opp_ref_WID                       ( 1)
+  #define MCSCHEDS_CR_SCHED_CBIT_dis_opp_ref_MSK                       (0x00800000)
+  #define MCSCHEDS_CR_SCHED_CBIT_dis_opp_ref_MAX                       (0x00000001)
+  #define MCSCHEDS_CR_SCHED_CBIT_dis_opp_ref_DEF                       (0x00000000)
+  #define MCSCHEDS_CR_SCHED_CBIT_Long_ZQ_OFF                           (24)
+  #define MCSCHEDS_CR_SCHED_CBIT_Long_ZQ_WID                           ( 1)
+  #define MCSCHEDS_CR_SCHED_CBIT_Long_ZQ_MSK                           (0x01000000)
+  #define MCSCHEDS_CR_SCHED_CBIT_Long_ZQ_MAX                           (0x00000001)
+  #define MCSCHEDS_CR_SCHED_CBIT_Long_ZQ_DEF                           (0x00000000)
+  #define MCSCHEDS_CR_SCHED_CBIT_dis_srx_zq_OFF                        (25)
+  #define MCSCHEDS_CR_SCHED_CBIT_dis_srx_zq_WID                        ( 1)
+  #define MCSCHEDS_CR_SCHED_CBIT_dis_srx_zq_MSK                        (0x02000000)
+  #define MCSCHEDS_CR_SCHED_CBIT_dis_srx_zq_MAX                        (0x00000001)
+  #define MCSCHEDS_CR_SCHED_CBIT_dis_srx_zq_DEF                        (0x00000000)
+  #define MCSCHEDS_CR_SCHED_CBIT_Serialize_ZQ_OFF                      (26)
+  #define MCSCHEDS_CR_SCHED_CBIT_Serialize_ZQ_WID                      ( 1)
+  #define MCSCHEDS_CR_SCHED_CBIT_Serialize_ZQ_MSK                      (0x04000000)
+  #define MCSCHEDS_CR_SCHED_CBIT_Serialize_ZQ_MAX                      (0x00000001)
+  #define MCSCHEDS_CR_SCHED_CBIT_Serialize_ZQ_DEF                      (0x00000000)
+  #define MCSCHEDS_CR_SCHED_CBIT_ZQ_fast_exec_OFF                      (27)
+  #define MCSCHEDS_CR_SCHED_CBIT_ZQ_fast_exec_WID                      ( 1)
+  #define MCSCHEDS_CR_SCHED_CBIT_ZQ_fast_exec_MSK                      (0x08000000)
+  #define MCSCHEDS_CR_SCHED_CBIT_ZQ_fast_exec_MAX                      (0x00000001)
+  #define MCSCHEDS_CR_SCHED_CBIT_ZQ_fast_exec_DEF                      (0x00000000)
+  #define MCSCHEDS_CR_SCHED_CBIT_Dis_DriveNop_OFF                      (28)
+  #define MCSCHEDS_CR_SCHED_CBIT_Dis_DriveNop_WID                      ( 1)
+  #define MCSCHEDS_CR_SCHED_CBIT_Dis_DriveNop_MSK                      (0x10000000)
+  #define MCSCHEDS_CR_SCHED_CBIT_Dis_DriveNop_MAX                      (0x00000001)
+  #define MCSCHEDS_CR_SCHED_CBIT_Dis_DriveNop_DEF                      (0x00000000)
+  #define MCSCHEDS_CR_SCHED_CBIT_Pres_WDB_Ent_OFF                      (29)
+  #define MCSCHEDS_CR_SCHED_CBIT_Pres_WDB_Ent_WID                      ( 1)
+  #define MCSCHEDS_CR_SCHED_CBIT_Pres_WDB_Ent_MSK                      (0x20000000)
+  #define MCSCHEDS_CR_SCHED_CBIT_Pres_WDB_Ent_MAX                      (0x00000001)
+  #define MCSCHEDS_CR_SCHED_CBIT_Pres_WDB_Ent_DEF                      (0x00000000)
+  #define MCSCHEDS_CR_SCHED_CBIT_dis_clk_gate_OFF                      (30)
+  #define MCSCHEDS_CR_SCHED_CBIT_dis_clk_gate_WID                      ( 1)
+  #define MCSCHEDS_CR_SCHED_CBIT_dis_clk_gate_MSK                      (0x40000000)
+  #define MCSCHEDS_CR_SCHED_CBIT_dis_clk_gate_MAX                      (0x00000001)
+  #define MCSCHEDS_CR_SCHED_CBIT_dis_clk_gate_DEF                      (0x00000000)
+
+#define MCSCHEDS_CR_SC_ROUNDT_LAT_REG                                (0x00004C24)
+  #define MCSCHEDS_CR_SC_ROUNDT_LAT_Lat_R0D0_OFF                       ( 0)
+  #define MCSCHEDS_CR_SC_ROUNDT_LAT_Lat_R0D0_WID                       ( 6)
+  #define MCSCHEDS_CR_SC_ROUNDT_LAT_Lat_R0D0_MSK                       (0x0000003F)
+  #define MCSCHEDS_CR_SC_ROUNDT_LAT_Lat_R0D0_MAX                       (0x0000003F)
+  #define MCSCHEDS_CR_SC_ROUNDT_LAT_Lat_R0D0_DEF                       (0x00000020)
+  #define MCSCHEDS_CR_SC_ROUNDT_LAT_Lat_R1D0_OFF                       ( 8)
+  #define MCSCHEDS_CR_SC_ROUNDT_LAT_Lat_R1D0_WID                       ( 6)
+  #define MCSCHEDS_CR_SC_ROUNDT_LAT_Lat_R1D0_MSK                       (0x00003F00)
+  #define MCSCHEDS_CR_SC_ROUNDT_LAT_Lat_R1D0_MAX                       (0x0000003F)
+  #define MCSCHEDS_CR_SC_ROUNDT_LAT_Lat_R1D0_DEF                       (0x00000020)
+  #define MCSCHEDS_CR_SC_ROUNDT_LAT_Lat_R0D1_OFF                       (16)
+  #define MCSCHEDS_CR_SC_ROUNDT_LAT_Lat_R0D1_WID                       ( 6)
+  #define MCSCHEDS_CR_SC_ROUNDT_LAT_Lat_R0D1_MSK                       (0x003F0000)
+  #define MCSCHEDS_CR_SC_ROUNDT_LAT_Lat_R0D1_MAX                       (0x0000003F)
+  #define MCSCHEDS_CR_SC_ROUNDT_LAT_Lat_R0D1_DEF                       (0x00000020)
+  #define MCSCHEDS_CR_SC_ROUNDT_LAT_Lat_R1D1_OFF                       (24)
+  #define MCSCHEDS_CR_SC_ROUNDT_LAT_Lat_R1D1_WID                       ( 6)
+  #define MCSCHEDS_CR_SC_ROUNDT_LAT_Lat_R1D1_MSK                       (0x3F000000)
+  #define MCSCHEDS_CR_SC_ROUNDT_LAT_Lat_R1D1_MAX                       (0x0000003F)
+  #define MCSCHEDS_CR_SC_ROUNDT_LAT_Lat_R1D1_DEF                       (0x00000020)
+
+#define MCSCHEDS_CR_SC_IO_LATENCY_REG                                (0x00004C28)
+  #define MCSCHEDS_CR_SC_IO_LATENCY_IOLAT_R0D0_OFF                     ( 0)
+  #define MCSCHEDS_CR_SC_IO_LATENCY_IOLAT_R0D0_WID                     ( 4)
+  #define MCSCHEDS_CR_SC_IO_LATENCY_IOLAT_R0D0_MSK                     (0x0000000F)
+  #define MCSCHEDS_CR_SC_IO_LATENCY_IOLAT_R0D0_MAX                     (0x0000000F)
+  #define MCSCHEDS_CR_SC_IO_LATENCY_IOLAT_R0D0_DEF                     (0x00000000)
+  #define MCSCHEDS_CR_SC_IO_LATENCY_IOLAT_R1D0_OFF                     ( 4)
+  #define MCSCHEDS_CR_SC_IO_LATENCY_IOLAT_R1D0_WID                     ( 4)
+  #define MCSCHEDS_CR_SC_IO_LATENCY_IOLAT_R1D0_MSK                     (0x000000F0)
+  #define MCSCHEDS_CR_SC_IO_LATENCY_IOLAT_R1D0_MAX                     (0x0000000F)
+  #define MCSCHEDS_CR_SC_IO_LATENCY_IOLAT_R1D0_DEF                     (0x00000000)
+  #define MCSCHEDS_CR_SC_IO_LATENCY_IOLAT_R0D1_OFF                     ( 8)
+  #define MCSCHEDS_CR_SC_IO_LATENCY_IOLAT_R0D1_WID                     ( 4)
+  #define MCSCHEDS_CR_SC_IO_LATENCY_IOLAT_R0D1_MSK                     (0x00000F00)
+  #define MCSCHEDS_CR_SC_IO_LATENCY_IOLAT_R0D1_MAX                     (0x0000000F)
+  #define MCSCHEDS_CR_SC_IO_LATENCY_IOLAT_R0D1_DEF                     (0x00000000)
+  #define MCSCHEDS_CR_SC_IO_LATENCY_IOLAT_R1D1_OFF                     (12)
+  #define MCSCHEDS_CR_SC_IO_LATENCY_IOLAT_R1D1_WID                     ( 4)
+  #define MCSCHEDS_CR_SC_IO_LATENCY_IOLAT_R1D1_MSK                     (0x0000F000)
+  #define MCSCHEDS_CR_SC_IO_LATENCY_IOLAT_R1D1_MAX                     (0x0000000F)
+  #define MCSCHEDS_CR_SC_IO_LATENCY_IOLAT_R1D1_DEF                     (0x00000000)
+  #define MCSCHEDS_CR_SC_IO_LATENCY_RT_IOCOMP_OFF                      (16)
+  #define MCSCHEDS_CR_SC_IO_LATENCY_RT_IOCOMP_WID                      ( 6)
+  #define MCSCHEDS_CR_SC_IO_LATENCY_RT_IOCOMP_MSK                      (0x003F0000)
+  #define MCSCHEDS_CR_SC_IO_LATENCY_RT_IOCOMP_MAX                      (0x0000003F)
+  #define MCSCHEDS_CR_SC_IO_LATENCY_RT_IOCOMP_DEF                      (0x0000000E)
+  #define MCSCHEDS_CR_SC_IO_LATENCY_three_channels_OFF                 (30)
+  #define MCSCHEDS_CR_SC_IO_LATENCY_three_channels_WID                 ( 1)
+  #define MCSCHEDS_CR_SC_IO_LATENCY_three_channels_MSK                 (0x40000000)
+  #define MCSCHEDS_CR_SC_IO_LATENCY_three_channels_MAX                 (0x00000001)
+  #define MCSCHEDS_CR_SC_IO_LATENCY_three_channels_DEF                 (0x00000000)
+  #define MCSCHEDS_CR_SC_IO_LATENCY_DIS_RT_CLK_GATE_OFF                (31)
+  #define MCSCHEDS_CR_SC_IO_LATENCY_DIS_RT_CLK_GATE_WID                ( 1)
+  #define MCSCHEDS_CR_SC_IO_LATENCY_DIS_RT_CLK_GATE_MSK                (0x80000000)
+  #define MCSCHEDS_CR_SC_IO_LATENCY_DIS_RT_CLK_GATE_MAX                (0x00000001)
+  #define MCSCHEDS_CR_SC_IO_LATENCY_DIS_RT_CLK_GATE_DEF                (0x00000000)
+
+#define MCSCHEDS_CR_ROUND_TRIP_DFT_DATA_REG                          (0x00004C2C)
+  #define MCSCHEDS_CR_ROUND_TRIP_DFT_DATA_DATA_OFF                     ( 0)
+  #define MCSCHEDS_CR_ROUND_TRIP_DFT_DATA_DATA_WID                     (32)
+  #define MCSCHEDS_CR_ROUND_TRIP_DFT_DATA_DATA_MSK                     (0xFFFFFFFF)
+  #define MCSCHEDS_CR_ROUND_TRIP_DFT_DATA_DATA_MAX                     (0xFFFFFFFF)
+  #define MCSCHEDS_CR_ROUND_TRIP_DFT_DATA_DATA_DEF                     (0x00000000)
+
+#define MCSCHEDS_CR_DFT_MISC_REG                                     (0x00004C30)
+  #define MCSCHEDS_CR_DFT_MISC_WDAR_OFF                                ( 0)
+  #define MCSCHEDS_CR_DFT_MISC_WDAR_WID                                ( 1)
+  #define MCSCHEDS_CR_DFT_MISC_WDAR_MSK                                (0x00000001)
+  #define MCSCHEDS_CR_DFT_MISC_WDAR_MAX                                (0x00000001)
+  #define MCSCHEDS_CR_DFT_MISC_WDAR_DEF                                (0x00000000)
+  #define MCSCHEDS_CR_DFT_MISC_safe_mask_sel_OFF                       ( 1)
+  #define MCSCHEDS_CR_DFT_MISC_safe_mask_sel_WID                       ( 3)
+  #define MCSCHEDS_CR_DFT_MISC_safe_mask_sel_MSK                       (0x0000000E)
+  #define MCSCHEDS_CR_DFT_MISC_safe_mask_sel_MAX                       (0x00000007)
+  #define MCSCHEDS_CR_DFT_MISC_safe_mask_sel_DEF                       (0x00000000)
+  #define MCSCHEDS_CR_DFT_MISC_force_rcv_en_OFF                        ( 4)
+  #define MCSCHEDS_CR_DFT_MISC_force_rcv_en_WID                        ( 1)
+  #define MCSCHEDS_CR_DFT_MISC_force_rcv_en_MSK                        (0x00000010)
+  #define MCSCHEDS_CR_DFT_MISC_force_rcv_en_MAX                        (0x00000001)
+  #define MCSCHEDS_CR_DFT_MISC_force_rcv_en_DEF                        (0x00000000)
+  #define MCSCHEDS_CR_DFT_MISC_DDR_QUAL_OFF                            ( 8)
+  #define MCSCHEDS_CR_DFT_MISC_DDR_QUAL_WID                            ( 2)
+  #define MCSCHEDS_CR_DFT_MISC_DDR_QUAL_MSK                            (0x00000300)
+  #define MCSCHEDS_CR_DFT_MISC_DDR_QUAL_MAX                            (0x00000003)
+  #define MCSCHEDS_CR_DFT_MISC_DDR_QUAL_DEF                            (0x00000000)
+  #define MCSCHEDS_CR_DFT_MISC_Qual_length_OFF                         (10)
+  #define MCSCHEDS_CR_DFT_MISC_Qual_length_WID                         ( 2)
+  #define MCSCHEDS_CR_DFT_MISC_Qual_length_MSK                         (0x00000C00)
+  #define MCSCHEDS_CR_DFT_MISC_Qual_length_MAX                         (0x00000003)
+  #define MCSCHEDS_CR_DFT_MISC_Qual_length_DEF                         (0x00000000)
+  #define MCSCHEDS_CR_DFT_MISC_WDB_Block_En_OFF                        (12)
+  #define MCSCHEDS_CR_DFT_MISC_WDB_Block_En_WID                        ( 1)
+  #define MCSCHEDS_CR_DFT_MISC_WDB_Block_En_MSK                        (0x00001000)
+  #define MCSCHEDS_CR_DFT_MISC_WDB_Block_En_MAX                        (0x00000001)
+  #define MCSCHEDS_CR_DFT_MISC_WDB_Block_En_DEF                        (0x00000000)
+  #define MCSCHEDS_CR_DFT_MISC_RT_DFT_READ_PTR_OFF                     (13)
+  #define MCSCHEDS_CR_DFT_MISC_RT_DFT_READ_PTR_WID                     ( 4)
+  #define MCSCHEDS_CR_DFT_MISC_RT_DFT_READ_PTR_MSK                     (0x0001E000)
+  #define MCSCHEDS_CR_DFT_MISC_RT_DFT_READ_PTR_MAX                     (0x0000000F)
+  #define MCSCHEDS_CR_DFT_MISC_RT_DFT_READ_PTR_DEF                     (0x00000000)
+  #define MCSCHEDS_CR_DFT_MISC_RT_DFT_READ_ENABLE_OFF                  (17)
+  #define MCSCHEDS_CR_DFT_MISC_RT_DFT_READ_ENABLE_WID                  ( 1)
+  #define MCSCHEDS_CR_DFT_MISC_RT_DFT_READ_ENABLE_MSK                  (0x00020000)
+  #define MCSCHEDS_CR_DFT_MISC_RT_DFT_READ_ENABLE_MAX                  (0x00000001)
+  #define MCSCHEDS_CR_DFT_MISC_RT_DFT_READ_ENABLE_DEF                  (0x00000000)
+  #define MCSCHEDS_CR_DFT_MISC_RT_DFT_READ_SEL_ADDR_OFF                (18)
+  #define MCSCHEDS_CR_DFT_MISC_RT_DFT_READ_SEL_ADDR_WID                ( 1)
+  #define MCSCHEDS_CR_DFT_MISC_RT_DFT_READ_SEL_ADDR_MSK                (0x00040000)
+  #define MCSCHEDS_CR_DFT_MISC_RT_DFT_READ_SEL_ADDR_MAX                (0x00000001)
+  #define MCSCHEDS_CR_DFT_MISC_RT_DFT_READ_SEL_ADDR_DEF                (0x00000000)
+
+#define MCSCHEDS_CR_READ_RETURN_DFT_REG                              (0x00004C34)
+  #define MCSCHEDS_CR_READ_RETURN_DFT_ECC_OFF                          ( 0)
+  #define MCSCHEDS_CR_READ_RETURN_DFT_ECC_WID                          ( 8)
+  #define MCSCHEDS_CR_READ_RETURN_DFT_ECC_MSK                          (0x000000FF)
+  #define MCSCHEDS_CR_READ_RETURN_DFT_ECC_MAX                          (0x000000FF)
+  #define MCSCHEDS_CR_READ_RETURN_DFT_ECC_DEF                          (0x00000000)
+  #define MCSCHEDS_CR_READ_RETURN_DFT_RRD_DFT_Mode_OFF                 ( 8)
+  #define MCSCHEDS_CR_READ_RETURN_DFT_RRD_DFT_Mode_WID                 ( 2)
+  #define MCSCHEDS_CR_READ_RETURN_DFT_RRD_DFT_Mode_MSK                 (0x00000300)
+  #define MCSCHEDS_CR_READ_RETURN_DFT_RRD_DFT_Mode_MAX                 (0x00000003)
+  #define MCSCHEDS_CR_READ_RETURN_DFT_RRD_DFT_Mode_DEF                 (0x00000000)
+  #define MCSCHEDS_CR_READ_RETURN_DFT_LFSR_Seed_Index_OFF              (10)
+  #define MCSCHEDS_CR_READ_RETURN_DFT_LFSR_Seed_Index_WID              ( 5)
+  #define MCSCHEDS_CR_READ_RETURN_DFT_LFSR_Seed_Index_MSK              (0x00007C00)
+  #define MCSCHEDS_CR_READ_RETURN_DFT_LFSR_Seed_Index_MAX              (0x0000001F)
+  #define MCSCHEDS_CR_READ_RETURN_DFT_LFSR_Seed_Index_DEF              (0x00000000)
+  #define MCSCHEDS_CR_READ_RETURN_DFT_Inversion_Mode_OFF               (15)
+  #define MCSCHEDS_CR_READ_RETURN_DFT_Inversion_Mode_WID               ( 1)
+  #define MCSCHEDS_CR_READ_RETURN_DFT_Inversion_Mode_MSK               (0x00008000)
+  #define MCSCHEDS_CR_READ_RETURN_DFT_Inversion_Mode_MAX               (0x00000001)
+  #define MCSCHEDS_CR_READ_RETURN_DFT_Inversion_Mode_DEF               (0x00000000)
+
+#define MCSCHEDS_CR_SCHED_SECOND_CBIT_REG                            (0x00004C38)
+  #define MCSCHEDS_CR_SCHED_SECOND_CBIT_dis_imph_error_OFF             ( 0)
+  #define MCSCHEDS_CR_SCHED_SECOND_CBIT_dis_imph_error_WID             ( 1)
+  #define MCSCHEDS_CR_SCHED_SECOND_CBIT_dis_imph_error_MSK             (0x00000001)
+  #define MCSCHEDS_CR_SCHED_SECOND_CBIT_dis_imph_error_MAX             (0x00000001)
+  #define MCSCHEDS_CR_SCHED_SECOND_CBIT_dis_imph_error_DEF             (0x00000000)
+  #define MCSCHEDS_CR_SCHED_SECOND_CBIT_dis_async_odt_OFF              ( 8)
+  #define MCSCHEDS_CR_SCHED_SECOND_CBIT_dis_async_odt_WID              ( 1)
+  #define MCSCHEDS_CR_SCHED_SECOND_CBIT_dis_async_odt_MSK              (0x00000100)
+  #define MCSCHEDS_CR_SCHED_SECOND_CBIT_dis_async_odt_MAX              (0x00000001)
+  #define MCSCHEDS_CR_SCHED_SECOND_CBIT_dis_async_odt_DEF              (0x00000000)
+
+#define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_REG                   (0x00004C40)
+  #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Mux0_Control_OFF      ( 0)
+  #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Mux0_Control_WID      ( 2)
+  #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Mux0_Control_MSK      (0x00000003)
+  #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Mux0_Control_MAX      (0x00000003)
+  #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Mux0_Control_DEF      (0x00000001)
+  #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Mux1_Control_OFF      ( 3)
+  #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Mux1_Control_WID      ( 2)
+  #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Mux1_Control_MSK      (0x00000018)
+  #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Mux1_Control_MAX      (0x00000003)
+  #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Mux1_Control_DEF      (0x00000001)
+  #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Mux2_Control_OFF      ( 6)
+  #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Mux2_Control_WID      ( 2)
+  #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Mux2_Control_MSK      (0x000000C0)
+  #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Mux2_Control_MAX      (0x00000003)
+  #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Mux2_Control_DEF      (0x00000001)
+  #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_ECC_Replace_Byte_Control_OFF (14)
+  #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_ECC_Replace_Byte_Control_WID ( 1)
+  #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_ECC_Replace_Byte_Control_MSK (0x00004000)
+  #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_ECC_Replace_Byte_Control_MAX (0x00000001)
+  #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_ECC_Replace_Byte_Control_DEF (0x00000001)
+  #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_ECC_Data_Source_Sel_OFF (15)
+  #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_ECC_Data_Source_Sel_WID ( 1)
+  #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_ECC_Data_Source_Sel_MSK (0x00008000)
+  #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_ECC_Data_Source_Sel_MAX (0x00000001)
+  #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_ECC_Data_Source_Sel_DEF (0x00000001)
+  #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Save_LFSR_Seed_Rate_OFF (16)
+  #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Save_LFSR_Seed_Rate_WID ( 6)
+  #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Save_LFSR_Seed_Rate_MSK (0x003F0000)
+  #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Save_LFSR_Seed_Rate_MAX (0x0000003F)
+  #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Save_LFSR_Seed_Rate_DEF (0x00000000)
+  #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Reload_LFSR_Seed_Rate_OFF (24)
+  #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Reload_LFSR_Seed_Rate_WID ( 3)
+  #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Reload_LFSR_Seed_Rate_MSK (0x07000000)
+  #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Reload_LFSR_Seed_Rate_MAX (0x00000007)
+  #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Reload_LFSR_Seed_Rate_DEF (0x00000000)
+
+#define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_RD_STATUS_REG                 (0x00004C44)
+  #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_RD_STATUS_WDB_Current_Read_Pointer_OFF ( 0)
+  #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_RD_STATUS_WDB_Current_Read_Pointer_WID ( 6)
+  #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_RD_STATUS_WDB_Current_Read_Pointer_MSK (0x0000003F)
+  #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_RD_STATUS_WDB_Current_Read_Pointer_MAX (0x0000003F)
+  #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_RD_STATUS_WDB_Current_Read_Pointer_DEF (0x00000000)
+
+#define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_0_REG               (0x00004C48)
+  #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_0_Pattern_Buffer_OFF ( 0)
+  #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_0_Pattern_Buffer_WID (24)
+  #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_0_Pattern_Buffer_MSK (0x00FFFFFF)
+  #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_0_Pattern_Buffer_MAX (0x00FFFFFF)
+
+#define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_1_REG               (0x00004C4C)
+  #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_1_Pattern_Buffer_OFF ( 0)
+  #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_1_Pattern_Buffer_WID (24)
+  #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_1_Pattern_Buffer_MSK (0x00FFFFFF)
+  #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_1_Pattern_Buffer_MAX (0x00FFFFFF)
+
+#define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_2_REG               (0x00004C50)
+  #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_2_Pattern_Buffer_OFF ( 0)
+  #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_2_Pattern_Buffer_WID (24)
+  #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_2_Pattern_Buffer_MSK (0x00FFFFFF)
+  #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_2_Pattern_Buffer_MAX (0x00FFFFFF)
+
+#define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_0_REG               (0x00004C54)
+  #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_0_Pattern_Buffer_OFF ( 0)
+  #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_0_Pattern_Buffer_WID (24)
+  #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_0_Pattern_Buffer_MSK (0x00FFFFFF)
+  #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_0_Pattern_Buffer_MAX (0x00FFFFFF)
+
+#define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_1_REG               (0x00004C58)
+  #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_1_Pattern_Buffer_OFF ( 0)
+  #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_1_Pattern_Buffer_WID (24)
+  #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_1_Pattern_Buffer_MSK (0x00FFFFFF)
+  #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_1_Pattern_Buffer_MAX (0x00FFFFFF)
+
+#define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_2_REG               (0x00004C5C)
+  #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_2_Pattern_Buffer_OFF ( 0)
+  #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_2_Pattern_Buffer_WID (24)
+  #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_2_Pattern_Buffer_MSK (0x00FFFFFF)
+  #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_2_Pattern_Buffer_MAX (0x00FFFFFF)
+
+#define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_0_REG        (0x00004C60)
+  #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_0_Pattern_Buffer_OFF ( 0)
+  #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_0_Pattern_Buffer_WID (24)
+  #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_0_Pattern_Buffer_MSK (0x00FFFFFF)
+  #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_0_Pattern_Buffer_MAX (0x00FFFFFF)
+  #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_0_Pattern_Buffer_DEF (0x00000000)
+
+#define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_1_REG        (0x00004C64)
+  #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_1_Pattern_Buffer_OFF ( 0)
+  #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_1_Pattern_Buffer_WID (24)
+  #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_1_Pattern_Buffer_MSK (0x00FFFFFF)
+  #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_1_Pattern_Buffer_MAX (0x00FFFFFF)
+  #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_1_Pattern_Buffer_DEF (0x00000000)
+
+#define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_2_REG        (0x00004C68)
+  #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_2_Pattern_Buffer_OFF ( 0)
+  #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_2_Pattern_Buffer_WID (24)
+  #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_2_Pattern_Buffer_MSK (0x00FFFFFF)
+  #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_2_Pattern_Buffer_MAX (0x00FFFFFF)
+  #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_2_Pattern_Buffer_DEF (0x00000000)
+
+#define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_0_REG        (0x00004C6C)
+  #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_0_Pattern_Buffer_OFF ( 0)
+  #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_0_Pattern_Buffer_WID (24)
+  #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_0_Pattern_Buffer_MSK (0x00FFFFFF)
+  #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_0_Pattern_Buffer_MAX (0x00FFFFFF)
+  #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_0_Pattern_Buffer_DEF (0x00000000)
+
+#define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_1_REG        (0x00004C70)
+  #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_1_Pattern_Buffer_OFF ( 0)
+  #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_1_Pattern_Buffer_WID (24)
+  #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_1_Pattern_Buffer_MSK (0x00FFFFFF)
+  #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_1_Pattern_Buffer_MAX (0x00FFFFFF)
+  #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_1_Pattern_Buffer_DEF (0x00000000)
+
+#define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_2_REG        (0x00004C74)
+  #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_2_Pattern_Buffer_OFF ( 0)
+  #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_2_Pattern_Buffer_WID (24)
+  #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_2_Pattern_Buffer_MSK (0x00FFFFFF)
+  #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_2_Pattern_Buffer_MAX (0x00FFFFFF)
+  #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_2_Pattern_Buffer_DEF (0x00000000)
+
+#define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_REG                   (0x00004C78)
+  #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_L_data_select_OFF     ( 0)
+  #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_L_data_select_WID     ( 1)
+  #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_L_data_select_MSK     (0x00000001)
+  #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_L_data_select_MAX     (0x00000001)
+  #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_L_data_select_DEF     (0x00000000)
+  #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_Enable_Sweep_Frequency_OFF ( 1)
+  #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_Enable_Sweep_Frequency_WID ( 1)
+  #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_Enable_Sweep_Frequency_MSK (0x00000002)
+  #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_Enable_Sweep_Frequency_MAX (0x00000001)
+  #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_Enable_Sweep_Frequency_DEF (0x00000000)
+  #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_L_counter_OFF         ( 8)
+  #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_L_counter_WID         ( 8)
+  #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_L_counter_MSK         (0x0000FF00)
+  #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_L_counter_MAX         (0x000000FF)
+  #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_L_counter_DEF         (0x00000001)
+  #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_M_counter_OFF         (16)
+  #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_M_counter_WID         ( 8)
+  #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_M_counter_MSK         (0x00FF0000)
+  #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_M_counter_MAX         (0x000000FF)
+  #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_M_counter_DEF         (0x00000001)
+  #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_N_counter_OFF         (24)
+  #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_N_counter_WID         ( 8)
+  #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_N_counter_MSK         (0xFF000000)
+  #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_N_counter_MAX         (0x000000FF)
+  #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_N_counter_DEF         (0x00000001)
+
+#define MCSCHEDS_CR_REUT_CH_PAT_WDB_INV_REG                          (0x00004C84)
+  #define MCSCHEDS_CR_REUT_CH_PAT_WDB_INV_ECC_Inv_or_DC_Enable_OFF     ( 0)
+  #define MCSCHEDS_CR_REUT_CH_PAT_WDB_INV_ECC_Inv_or_DC_Enable_WID     ( 8)
+  #define MCSCHEDS_CR_REUT_CH_PAT_WDB_INV_ECC_Inv_or_DC_Enable_MSK     (0x000000FF)
+  #define MCSCHEDS_CR_REUT_CH_PAT_WDB_INV_ECC_Inv_or_DC_Enable_MAX     (0x000000FF)
+  #define MCSCHEDS_CR_REUT_CH_PAT_WDB_INV_ECC_Inv_or_DC_Enable_DEF     (0x00000000)
+  #define MCSCHEDS_CR_REUT_CH_PAT_WDB_INV_Inv_or_DC_Shift_Rate_OFF     (16)
+  #define MCSCHEDS_CR_REUT_CH_PAT_WDB_INV_Inv_or_DC_Shift_Rate_WID     ( 4)
+  #define MCSCHEDS_CR_REUT_CH_PAT_WDB_INV_Inv_or_DC_Shift_Rate_MSK     (0x000F0000)
+  #define MCSCHEDS_CR_REUT_CH_PAT_WDB_INV_Inv_or_DC_Shift_Rate_MAX     (0x0000000F)
+  #define MCSCHEDS_CR_REUT_CH_PAT_WDB_INV_Inv_or_DC_Shift_Rate_DEF     (0x00000000)
+  #define MCSCHEDS_CR_REUT_CH_PAT_WDB_INV_DC_Polarity_Control_OFF      (20)
+  #define MCSCHEDS_CR_REUT_CH_PAT_WDB_INV_DC_Polarity_Control_WID      ( 1)
+  #define MCSCHEDS_CR_REUT_CH_PAT_WDB_INV_DC_Polarity_Control_MSK      (0x00100000)
+  #define MCSCHEDS_CR_REUT_CH_PAT_WDB_INV_DC_Polarity_Control_MAX      (0x00000001)
+  #define MCSCHEDS_CR_REUT_CH_PAT_WDB_INV_DC_Polarity_Control_DEF      (0x00000000)
+  #define MCSCHEDS_CR_REUT_CH_PAT_WDB_INV_Inv_or_DC_Control_OFF        (30)
+  #define MCSCHEDS_CR_REUT_CH_PAT_WDB_INV_Inv_or_DC_Control_WID        ( 1)
+  #define MCSCHEDS_CR_REUT_CH_PAT_WDB_INV_Inv_or_DC_Control_MSK        (0x40000000)
+  #define MCSCHEDS_CR_REUT_CH_PAT_WDB_INV_Inv_or_DC_Control_MAX        (0x00000001)
+  #define MCSCHEDS_CR_REUT_CH_PAT_WDB_INV_Inv_or_DC_Control_DEF        (0x00000000)
+  #define MCSCHEDS_CR_REUT_CH_PAT_WDB_INV_Inv_or_DC_Shift_Enable_OFF   (31)
+  #define MCSCHEDS_CR_REUT_CH_PAT_WDB_INV_Inv_or_DC_Shift_Enable_WID   ( 1)
+  #define MCSCHEDS_CR_REUT_CH_PAT_WDB_INV_Inv_or_DC_Shift_Enable_MSK   (0x80000000)
+  #define MCSCHEDS_CR_REUT_CH_PAT_WDB_INV_Inv_or_DC_Shift_Enable_MAX   (0x00000001)
+  #define MCSCHEDS_CR_REUT_CH_PAT_WDB_INV_Inv_or_DC_Shift_Enable_DEF   (0x00000000)
+
+#define MCSCHEDS_CR_REUT_CH_PAT_WDB_DATA_INV_REG                     (0x00004C90)
+  #define MCSCHEDS_CR_REUT_CH_PAT_WDB_DATA_INV_Data_Inv_or_DC_Enable_OFF ( 0)
+  #define MCSCHEDS_CR_REUT_CH_PAT_WDB_DATA_INV_Data_Inv_or_DC_Enable_WID (64)
+  #define MCSCHEDS_CR_REUT_CH_PAT_WDB_DATA_INV_Data_Inv_or_DC_Enable_MSK (0xFFFFFFFFFFFFFFFF)
+  #define MCSCHEDS_CR_REUT_CH_PAT_WDB_DATA_INV_Data_Inv_or_DC_Enable_MAX (0xFFFFFFFFFFFFFFFF)
+  #define MCSCHEDS_CR_REUT_CH_PAT_WDB_DATA_INV_Data_Inv_or_DC_Enable_DEF (0x00000000)
+
+#define MCSCHEDS_CR_REUT_CH_ERR_CTL_REG                              (0x00004C98)
+  #define MCSCHEDS_CR_REUT_CH_ERR_CTL_Stop_on_Nth_Error_OFF            ( 0)
+  #define MCSCHEDS_CR_REUT_CH_ERR_CTL_Stop_on_Nth_Error_WID            ( 6)
+  #define MCSCHEDS_CR_REUT_CH_ERR_CTL_Stop_on_Nth_Error_MSK            (0x0000003F)
+  #define MCSCHEDS_CR_REUT_CH_ERR_CTL_Stop_on_Nth_Error_MAX            (0x0000003F)
+  #define MCSCHEDS_CR_REUT_CH_ERR_CTL_Stop_on_Nth_Error_DEF            (0x00000001)
+  #define MCSCHEDS_CR_REUT_CH_ERR_CTL_Stop_On_Error_Control_OFF        (12)
+  #define MCSCHEDS_CR_REUT_CH_ERR_CTL_Stop_On_Error_Control_WID        ( 2)
+  #define MCSCHEDS_CR_REUT_CH_ERR_CTL_Stop_On_Error_Control_MSK        (0x00003000)
+  #define MCSCHEDS_CR_REUT_CH_ERR_CTL_Stop_On_Error_Control_MAX        (0x00000003)
+  #define MCSCHEDS_CR_REUT_CH_ERR_CTL_Stop_On_Error_Control_DEF        (0x00000000)
+  #define MCSCHEDS_CR_REUT_CH_ERR_CTL_Selective_Error_Enable_Chunk_OFF (16)
+  #define MCSCHEDS_CR_REUT_CH_ERR_CTL_Selective_Error_Enable_Chunk_WID ( 8)
+  #define MCSCHEDS_CR_REUT_CH_ERR_CTL_Selective_Error_Enable_Chunk_MSK (0x00FF0000)
+  #define MCSCHEDS_CR_REUT_CH_ERR_CTL_Selective_Error_Enable_Chunk_MAX (0x000000FF)
+  #define MCSCHEDS_CR_REUT_CH_ERR_CTL_Selective_Error_Enable_Chunk_DEF (0x000000FF)
+  #define MCSCHEDS_CR_REUT_CH_ERR_CTL_Selective_Error_Enable_Cacheline_OFF (24)
+  #define MCSCHEDS_CR_REUT_CH_ERR_CTL_Selective_Error_Enable_Cacheline_WID ( 8)
+  #define MCSCHEDS_CR_REUT_CH_ERR_CTL_Selective_Error_Enable_Cacheline_MSK (0xFF000000)
+  #define MCSCHEDS_CR_REUT_CH_ERR_CTL_Selective_Error_Enable_Cacheline_MAX (0x000000FF)
+  #define MCSCHEDS_CR_REUT_CH_ERR_CTL_Selective_Error_Enable_Cacheline_DEF (0x000000FF)
+
+#define MCSCHEDS_CR_REUT_CH_ERR_ECC_MASK_REG                         (0x00004C9C)
+  #define MCSCHEDS_CR_REUT_CH_ERR_ECC_MASK_ECC_Error_Mask_OFF          ( 0)
+  #define MCSCHEDS_CR_REUT_CH_ERR_ECC_MASK_ECC_Error_Mask_WID          ( 8)
+  #define MCSCHEDS_CR_REUT_CH_ERR_ECC_MASK_ECC_Error_Mask_MSK          (0x000000FF)
+  #define MCSCHEDS_CR_REUT_CH_ERR_ECC_MASK_ECC_Error_Mask_MAX          (0x000000FF)
+  #define MCSCHEDS_CR_REUT_CH_ERR_ECC_MASK_ECC_Error_Mask_DEF          (0x00000000)
+
+#define MCSCHEDS_CR_STM_CONFIG_REG                                   (0x00004CA4)
+  #define MCSCHEDS_CR_STM_CONFIG_Stretch_mode_OFF                      ( 0)
+  #define MCSCHEDS_CR_STM_CONFIG_Stretch_mode_WID                      ( 2)
+  #define MCSCHEDS_CR_STM_CONFIG_Stretch_mode_MSK                      (0x00000003)
+  #define MCSCHEDS_CR_STM_CONFIG_Stretch_mode_MAX                      (0x00000003)
+  #define MCSCHEDS_CR_STM_CONFIG_Stretch_mode_DEF                      (0x00000000)
+  #define MCSCHEDS_CR_STM_CONFIG_STF_OFF                               ( 4)
+  #define MCSCHEDS_CR_STM_CONFIG_STF_WID                               ( 3)
+  #define MCSCHEDS_CR_STM_CONFIG_STF_MSK                               (0x00000070)
+  #define MCSCHEDS_CR_STM_CONFIG_STF_MAX                               (0x00000007)
+  #define MCSCHEDS_CR_STM_CONFIG_STF_DEF                               (0x00000000)
+
+#define MCSCHEDS_CR_SC_PR_CNT_CONFIG_REG                             (0x00004CA8)
+  #define MCSCHEDS_CR_SC_PR_CNT_CONFIG_Priority_count_ring_OFF         ( 0)
+  #define MCSCHEDS_CR_SC_PR_CNT_CONFIG_Priority_count_ring_WID         (10)
+  #define MCSCHEDS_CR_SC_PR_CNT_CONFIG_Priority_count_ring_MSK         (0x000003FF)
+  #define MCSCHEDS_CR_SC_PR_CNT_CONFIG_Priority_count_ring_MAX         (0x000003FF)
+  #define MCSCHEDS_CR_SC_PR_CNT_CONFIG_Priority_count_ring_DEF         (0x00000040)
+  #define MCSCHEDS_CR_SC_PR_CNT_CONFIG_Priority_count_SA_OFF           (16)
+  #define MCSCHEDS_CR_SC_PR_CNT_CONFIG_Priority_count_SA_WID           (10)
+  #define MCSCHEDS_CR_SC_PR_CNT_CONFIG_Priority_count_SA_MSK           (0x03FF0000)
+  #define MCSCHEDS_CR_SC_PR_CNT_CONFIG_Priority_count_SA_MAX           (0x000003FF)
+  #define MCSCHEDS_CR_SC_PR_CNT_CONFIG_Priority_count_SA_DEF           (0x00000100)
+
+#define MCSCHEDS_CR_SC_PCIT_REG                                      (0x00004CAC)
+  #define MCSCHEDS_CR_SC_PCIT_PCIT_OFF                                 ( 0)
+  #define MCSCHEDS_CR_SC_PCIT_PCIT_WID                                 ( 8)
+  #define MCSCHEDS_CR_SC_PCIT_PCIT_MSK                                 (0x000000FF)
+  #define MCSCHEDS_CR_SC_PCIT_PCIT_MAX                                 (0x000000FF)
+  #define MCSCHEDS_CR_SC_PCIT_PCIT_DEF                                 (0x00000040)
+
+#define MCSCHEDS_CR_PM_PDWN_CONFIG_REG                               (0x00004CB0)
+  #define MCSCHEDS_CR_PM_PDWN_CONFIG_PDWN_idle_counter_OFF             ( 0)
+  #define MCSCHEDS_CR_PM_PDWN_CONFIG_PDWN_idle_counter_WID             (12)
+  #define MCSCHEDS_CR_PM_PDWN_CONFIG_PDWN_idle_counter_MSK             (0x00000FFF)
+  #define MCSCHEDS_CR_PM_PDWN_CONFIG_PDWN_idle_counter_MAX             (0x00000FFF)
+  #define MCSCHEDS_CR_PM_PDWN_CONFIG_PDWN_idle_counter_DEF             (0x00000000)
+  #define MCSCHEDS_CR_PM_PDWN_CONFIG_PDWN_mode_OFF                     (12)
+  #define MCSCHEDS_CR_PM_PDWN_CONFIG_PDWN_mode_WID                     ( 4)
+  #define MCSCHEDS_CR_PM_PDWN_CONFIG_PDWN_mode_MSK                     (0x0000F000)
+  #define MCSCHEDS_CR_PM_PDWN_CONFIG_PDWN_mode_MAX                     (0x0000000F)
+  #define MCSCHEDS_CR_PM_PDWN_CONFIG_PDWN_mode_DEF                     (0x00000000)
+
+#define MCSCHEDS_CR_ECC_INJECT_COUNT_REG                             (0x00004CB4)
+  #define MCSCHEDS_CR_ECC_INJECT_COUNT_Count_OFF                       ( 0)
+  #define MCSCHEDS_CR_ECC_INJECT_COUNT_Count_WID                       (32)
+  #define MCSCHEDS_CR_ECC_INJECT_COUNT_Count_MSK                       (0xFFFFFFFF)
+  #define MCSCHEDS_CR_ECC_INJECT_COUNT_Count_MAX                       (0xFFFFFFFF)
+  #define MCSCHEDS_CR_ECC_INJECT_COUNT_Count_DEF                       (0xFFFFFFFF)
+
+#define MCSCHEDS_CR_ECC_DFT_REG                                      (0x00004CB8)
+  #define MCSCHEDS_CR_ECC_DFT_ECC4ANA_fill_OFF                         ( 0)
+  #define MCSCHEDS_CR_ECC_DFT_ECC4ANA_fill_WID                         ( 8)
+  #define MCSCHEDS_CR_ECC_DFT_ECC4ANA_fill_MSK                         (0x000000FF)
+  #define MCSCHEDS_CR_ECC_DFT_ECC4ANA_fill_MAX                         (0x000000FF)
+  #define MCSCHEDS_CR_ECC_DFT_ECC4ANA_fill_DEF                         (0x00000000)
+  #define MCSCHEDS_CR_ECC_DFT_ECC4ANA_trigger_OFF                      ( 8)
+  #define MCSCHEDS_CR_ECC_DFT_ECC4ANA_trigger_WID                      ( 2)
+  #define MCSCHEDS_CR_ECC_DFT_ECC4ANA_trigger_MSK                      (0x00000300)
+  #define MCSCHEDS_CR_ECC_DFT_ECC4ANA_trigger_MAX                      (0x00000003)
+  #define MCSCHEDS_CR_ECC_DFT_ECC4ANA_trigger_DEF                      (0x00000000)
+  #define MCSCHEDS_CR_ECC_DFT_ECC4ANA_BS_OFF                           (10)
+  #define MCSCHEDS_CR_ECC_DFT_ECC4ANA_BS_WID                           ( 1)
+  #define MCSCHEDS_CR_ECC_DFT_ECC4ANA_BS_MSK                           (0x00000400)
+  #define MCSCHEDS_CR_ECC_DFT_ECC4ANA_BS_MAX                           (0x00000001)
+  #define MCSCHEDS_CR_ECC_DFT_ECC4ANA_BS_DEF                           (0x00000000)
+  #define MCSCHEDS_CR_ECC_DFT_ECC_Inject_OFF                           (11)
+  #define MCSCHEDS_CR_ECC_DFT_ECC_Inject_WID                           ( 3)
+  #define MCSCHEDS_CR_ECC_DFT_ECC_Inject_MSK                           (0x00003800)
+  #define MCSCHEDS_CR_ECC_DFT_ECC_Inject_MAX                           (0x00000007)
+  #define MCSCHEDS_CR_ECC_DFT_ECC_Inject_DEF                           (0x00000000)
+  #define MCSCHEDS_CR_ECC_DFT_ECC_correction_disable_OFF               (14)
+  #define MCSCHEDS_CR_ECC_DFT_ECC_correction_disable_WID               ( 1)
+  #define MCSCHEDS_CR_ECC_DFT_ECC_correction_disable_MSK               (0x00004000)
+  #define MCSCHEDS_CR_ECC_DFT_ECC_correction_disable_MAX               (0x00000001)
+  #define MCSCHEDS_CR_ECC_DFT_ECC_correction_disable_DEF               (0x00000000)
+  #define MCSCHEDS_CR_ECC_DFT_ECC4ANA_Inject_OFF                       (15)
+  #define MCSCHEDS_CR_ECC_DFT_ECC4ANA_Inject_WID                       ( 1)
+  #define MCSCHEDS_CR_ECC_DFT_ECC4ANA_Inject_MSK                       (0x00008000)
+  #define MCSCHEDS_CR_ECC_DFT_ECC4ANA_Inject_MAX                       (0x00000001)
+  #define MCSCHEDS_CR_ECC_DFT_ECC4ANA_Inject_DEF                       (0x00000000)
+  #define MCSCHEDS_CR_ECC_DFT_DIS_MCA_LOG_OFF                          (16)
+  #define MCSCHEDS_CR_ECC_DFT_DIS_MCA_LOG_WID                          ( 1)
+  #define MCSCHEDS_CR_ECC_DFT_DIS_MCA_LOG_MSK                          (0x00010000)
+  #define MCSCHEDS_CR_ECC_DFT_DIS_MCA_LOG_MAX                          (0x00000001)
+  #define MCSCHEDS_CR_ECC_DFT_DIS_MCA_LOG_DEF                          (0x00000000)
+  #define MCSCHEDS_CR_ECC_DFT_DIS_PCH_EVENT_OFF                        (17)
+  #define MCSCHEDS_CR_ECC_DFT_DIS_PCH_EVENT_WID                        ( 1)
+  #define MCSCHEDS_CR_ECC_DFT_DIS_PCH_EVENT_MSK                        (0x00020000)
+  #define MCSCHEDS_CR_ECC_DFT_DIS_PCH_EVENT_MAX                        (0x00000001)
+  #define MCSCHEDS_CR_ECC_DFT_DIS_PCH_EVENT_DEF                        (0x00000000)
+  #define MCSCHEDS_CR_ECC_DFT_DIS_PCIE_POISON_OFF                      (18)
+  #define MCSCHEDS_CR_ECC_DFT_DIS_PCIE_POISON_WID                      ( 1)
+  #define MCSCHEDS_CR_ECC_DFT_DIS_PCIE_POISON_MSK                      (0x00040000)
+  #define MCSCHEDS_CR_ECC_DFT_DIS_PCIE_POISON_MAX                      (0x00000001)
+  #define MCSCHEDS_CR_ECC_DFT_DIS_PCIE_POISON_DEF                      (0x00000000)
+
+#define MCSCHEDS_CR_VISA_CTL_MCSCHEDS_REG                            (0x00004CC0)
+  #define MCSCHEDS_CR_VISA_CTL_MCSCHEDS_Data_OFF                       ( 0)
+  #define MCSCHEDS_CR_VISA_CTL_MCSCHEDS_Data_WID                       (18)
+  #define MCSCHEDS_CR_VISA_CTL_MCSCHEDS_Data_MSK                       (0x0003FFFF)
+  #define MCSCHEDS_CR_VISA_CTL_MCSCHEDS_Data_MAX                       (0x0003FFFF)
+  #define MCSCHEDS_CR_VISA_CTL_MCSCHEDS_Data_DEF                       (0x00000000)
+  #define MCSCHEDS_CR_VISA_CTL_MCSCHEDS_VORANGE_OFF                    (31)
+  #define MCSCHEDS_CR_VISA_CTL_MCSCHEDS_VORANGE_WID                    ( 1)
+  #define MCSCHEDS_CR_VISA_CTL_MCSCHEDS_VORANGE_MSK                    (0x80000000)
+  #define MCSCHEDS_CR_VISA_CTL_MCSCHEDS_VORANGE_MAX                    (0x00000001)
+  #define MCSCHEDS_CR_VISA_CTL_MCSCHEDS_VORANGE_DEF                    (0x00000000)
+
+#define MCSCHEDS_CR_VISA_XBAR_MCSCHEDS_REG                           (0x00004CC4)
+  #define MCSCHEDS_CR_VISA_XBAR_MCSCHEDS_Data_OFF                      ( 0)
+  #define MCSCHEDS_CR_VISA_XBAR_MCSCHEDS_Data_WID                      (32)
+  #define MCSCHEDS_CR_VISA_XBAR_MCSCHEDS_Data_MSK                      (0xFFFFFFFF)
+  #define MCSCHEDS_CR_VISA_XBAR_MCSCHEDS_Data_MAX                      (0xFFFFFFFF)
+  #define MCSCHEDS_CR_VISA_XBAR_MCSCHEDS_Data_DEF                      (0x76543210)
+
+#define MCSCHEDS_CR_ECCERRLOG0_REG                                   (0x00004CC8)
+  #define MCSCHEDS_CR_ECCERRLOG0_CERRSTS_OFF                           ( 0)
+  #define MCSCHEDS_CR_ECCERRLOG0_CERRSTS_WID                           ( 1)
+  #define MCSCHEDS_CR_ECCERRLOG0_CERRSTS_MSK                           (0x00000001)
+  #define MCSCHEDS_CR_ECCERRLOG0_CERRSTS_MAX                           (0x00000001)
+  #define MCSCHEDS_CR_ECCERRLOG0_CERRSTS_DEF                           (0x00000000)
+  #define MCSCHEDS_CR_ECCERRLOG0_MERRSTS_OFF                           ( 1)
+  #define MCSCHEDS_CR_ECCERRLOG0_MERRSTS_WID                           ( 1)
+  #define MCSCHEDS_CR_ECCERRLOG0_MERRSTS_MSK                           (0x00000002)
+  #define MCSCHEDS_CR_ECCERRLOG0_MERRSTS_MAX                           (0x00000001)
+  #define MCSCHEDS_CR_ECCERRLOG0_MERRSTS_DEF                           (0x00000000)
+  #define MCSCHEDS_CR_ECCERRLOG0_ERRSYND_OFF                           (16)
+  #define MCSCHEDS_CR_ECCERRLOG0_ERRSYND_WID                           ( 8)
+  #define MCSCHEDS_CR_ECCERRLOG0_ERRSYND_MSK                           (0x00FF0000)
+  #define MCSCHEDS_CR_ECCERRLOG0_ERRSYND_MAX                           (0x000000FF)
+  #define MCSCHEDS_CR_ECCERRLOG0_ERRSYND_DEF                           (0x00000000)
+  #define MCSCHEDS_CR_ECCERRLOG0_ERRCHUNK_OFF                          (24)
+  #define MCSCHEDS_CR_ECCERRLOG0_ERRCHUNK_WID                          ( 3)
+  #define MCSCHEDS_CR_ECCERRLOG0_ERRCHUNK_MSK                          (0x07000000)
+  #define MCSCHEDS_CR_ECCERRLOG0_ERRCHUNK_MAX                          (0x00000007)
+  #define MCSCHEDS_CR_ECCERRLOG0_ERRCHUNK_DEF                          (0x00000000)
+  #define MCSCHEDS_CR_ECCERRLOG0_ERRRANK_OFF                           (27)
+  #define MCSCHEDS_CR_ECCERRLOG0_ERRRANK_WID                           ( 2)
+  #define MCSCHEDS_CR_ECCERRLOG0_ERRRANK_MSK                           (0x18000000)
+  #define MCSCHEDS_CR_ECCERRLOG0_ERRRANK_MAX                           (0x00000003)
+  #define MCSCHEDS_CR_ECCERRLOG0_ERRRANK_DEF                           (0x00000000)
+  #define MCSCHEDS_CR_ECCERRLOG0_ERRBANK_OFF                           (29)
+  #define MCSCHEDS_CR_ECCERRLOG0_ERRBANK_WID                           ( 3)
+  #define MCSCHEDS_CR_ECCERRLOG0_ERRBANK_MSK                           (0xE0000000)
+  #define MCSCHEDS_CR_ECCERRLOG0_ERRBANK_MAX                           (0x00000007)
+  #define MCSCHEDS_CR_ECCERRLOG0_ERRBANK_DEF                           (0x00000000)
+
+#define MCSCHEDS_CR_ECCERRLOG1_REG                                   (0x00004CCC)
+  #define MCSCHEDS_CR_ECCERRLOG1_ERRROW_OFF                            ( 0)
+  #define MCSCHEDS_CR_ECCERRLOG1_ERRROW_WID                            (16)
+  #define MCSCHEDS_CR_ECCERRLOG1_ERRROW_MSK                            (0x0000FFFF)
+  #define MCSCHEDS_CR_ECCERRLOG1_ERRROW_MAX                            (0x0000FFFF)
+  #define MCSCHEDS_CR_ECCERRLOG1_ERRROW_DEF                            (0x00000000)
+  #define MCSCHEDS_CR_ECCERRLOG1_ERRCOL_OFF                            (16)
+  #define MCSCHEDS_CR_ECCERRLOG1_ERRCOL_WID                            (16)
+  #define MCSCHEDS_CR_ECCERRLOG1_ERRCOL_MSK                            (0xFFFF0000)
+  #define MCSCHEDS_CR_ECCERRLOG1_ERRCOL_MAX                            (0x0000FFFF)
+  #define MCSCHEDS_CR_ECCERRLOG1_ERRCOL_DEF                            (0x00000000)
+
+#define MCSCHEDS_CR_SC_WR_ADD_DELAY_REG                              (0x00004CD0)
+  #define MCSCHEDS_CR_SC_WR_ADD_DELAY_D0R0_OFF                         ( 0)
+  #define MCSCHEDS_CR_SC_WR_ADD_DELAY_D0R0_WID                         ( 2)
+  #define MCSCHEDS_CR_SC_WR_ADD_DELAY_D0R0_MSK                         (0x00000003)
+  #define MCSCHEDS_CR_SC_WR_ADD_DELAY_D0R0_MAX                         (0x00000003)
+  #define MCSCHEDS_CR_SC_WR_ADD_DELAY_D0R0_DEF                         (0x00000000)
+  #define MCSCHEDS_CR_SC_WR_ADD_DELAY_D0R1_OFF                         ( 2)
+  #define MCSCHEDS_CR_SC_WR_ADD_DELAY_D0R1_WID                         ( 2)
+  #define MCSCHEDS_CR_SC_WR_ADD_DELAY_D0R1_MSK                         (0x0000000C)
+  #define MCSCHEDS_CR_SC_WR_ADD_DELAY_D0R1_MAX                         (0x00000003)
+  #define MCSCHEDS_CR_SC_WR_ADD_DELAY_D0R1_DEF                         (0x00000000)
+  #define MCSCHEDS_CR_SC_WR_ADD_DELAY_D1R0_OFF                         ( 4)
+  #define MCSCHEDS_CR_SC_WR_ADD_DELAY_D1R0_WID                         ( 2)
+  #define MCSCHEDS_CR_SC_WR_ADD_DELAY_D1R0_MSK                         (0x00000030)
+  #define MCSCHEDS_CR_SC_WR_ADD_DELAY_D1R0_MAX                         (0x00000003)
+  #define MCSCHEDS_CR_SC_WR_ADD_DELAY_D1R0_DEF                         (0x00000000)
+  #define MCSCHEDS_CR_SC_WR_ADD_DELAY_D1R1_OFF                         ( 6)
+  #define MCSCHEDS_CR_SC_WR_ADD_DELAY_D1R1_WID                         ( 2)
+  #define MCSCHEDS_CR_SC_WR_ADD_DELAY_D1R1_MSK                         (0x000000C0)
+  #define MCSCHEDS_CR_SC_WR_ADD_DELAY_D1R1_MAX                         (0x00000003)
+  #define MCSCHEDS_CR_SC_WR_ADD_DELAY_D1R1_DEF                         (0x00000000)
+
+#define MCSCHEDS_CR_WMM_READ_CONFIG_REG                              (0x00004CD4)
+  #define MCSCHEDS_CR_WMM_READ_CONFIG_Dis_Opp_rd_OFF                   ( 0)
+  #define MCSCHEDS_CR_WMM_READ_CONFIG_Dis_Opp_rd_WID                   ( 1)
+  #define MCSCHEDS_CR_WMM_READ_CONFIG_Dis_Opp_rd_MSK                   (0x00000001)
+  #define MCSCHEDS_CR_WMM_READ_CONFIG_Dis_Opp_rd_MAX                   (0x00000001)
+  #define MCSCHEDS_CR_WMM_READ_CONFIG_Dis_Opp_rd_DEF                   (0x00000000)
+  #define MCSCHEDS_CR_WMM_READ_CONFIG_ACT_Enable_OFF                   ( 1)
+  #define MCSCHEDS_CR_WMM_READ_CONFIG_ACT_Enable_WID                   ( 1)
+  #define MCSCHEDS_CR_WMM_READ_CONFIG_ACT_Enable_MSK                   (0x00000002)
+  #define MCSCHEDS_CR_WMM_READ_CONFIG_ACT_Enable_MAX                   (0x00000001)
+  #define MCSCHEDS_CR_WMM_READ_CONFIG_ACT_Enable_DEF                   (0x00000001)
+  #define MCSCHEDS_CR_WMM_READ_CONFIG_PRE_Enable_OFF                   ( 2)
+  #define MCSCHEDS_CR_WMM_READ_CONFIG_PRE_Enable_WID                   ( 1)
+  #define MCSCHEDS_CR_WMM_READ_CONFIG_PRE_Enable_MSK                   (0x00000004)
+  #define MCSCHEDS_CR_WMM_READ_CONFIG_PRE_Enable_MAX                   (0x00000001)
+  #define MCSCHEDS_CR_WMM_READ_CONFIG_PRE_Enable_DEF                   (0x00000001)
+  #define MCSCHEDS_CR_WMM_READ_CONFIG_MAX_RPQ_Cas_OFF                  ( 3)
+  #define MCSCHEDS_CR_WMM_READ_CONFIG_MAX_RPQ_Cas_WID                  ( 4)
+  #define MCSCHEDS_CR_WMM_READ_CONFIG_MAX_RPQ_Cas_MSK                  (0x00000078)
+  #define MCSCHEDS_CR_WMM_READ_CONFIG_MAX_RPQ_Cas_MAX                  (0x0000000F)
+  #define MCSCHEDS_CR_WMM_READ_CONFIG_MAX_RPQ_Cas_DEF                  (0x00000008)
+
+#define MCSCHEDS_CR_REUT_CH_ERR_DATA_MASK_REG                        (0x00004CD8)
+  #define MCSCHEDS_CR_REUT_CH_ERR_DATA_MASK_Data_Error_Mask_OFF        ( 0)
+  #define MCSCHEDS_CR_REUT_CH_ERR_DATA_MASK_Data_Error_Mask_WID        (64)
+  #define MCSCHEDS_CR_REUT_CH_ERR_DATA_MASK_Data_Error_Mask_MSK        (0xFFFFFFFFFFFFFFFF)
+  #define MCSCHEDS_CR_REUT_CH_ERR_DATA_MASK_Data_Error_Mask_MAX        (0xFFFFFFFFFFFFFFFF)
+  #define MCSCHEDS_CR_REUT_CH_ERR_DATA_MASK_Data_Error_Mask_DEF        (0x00000000)
+
+#define MCSCHEDS_CR_REUT_CH_ERR_DATA_STATUS_REG                      (0x00004CE0)
+  #define MCSCHEDS_CR_REUT_CH_ERR_DATA_STATUS_Data_Error_Status_OFF    ( 0)
+  #define MCSCHEDS_CR_REUT_CH_ERR_DATA_STATUS_Data_Error_Status_WID    (64)
+  #define MCSCHEDS_CR_REUT_CH_ERR_DATA_STATUS_Data_Error_Status_MSK    (0xFFFFFFFFFFFFFFFF)
+  #define MCSCHEDS_CR_REUT_CH_ERR_DATA_STATUS_Data_Error_Status_MAX    (0xFFFFFFFFFFFFFFFF)
+  #define MCSCHEDS_CR_REUT_CH_ERR_DATA_STATUS_Data_Error_Status_DEF    (0x00000000)
+
+#define MCSCHEDS_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_REG   (0x00004CE8)
+  #define MCSCHEDS_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_ECC_Error_Status_OFF ( 0)
+  #define MCSCHEDS_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_ECC_Error_Status_WID ( 8)
+  #define MCSCHEDS_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_ECC_Error_Status_MSK (0x000000FF)
+  #define MCSCHEDS_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_ECC_Error_Status_MAX (0x000000FF)
+  #define MCSCHEDS_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_ECC_Error_Status_DEF (0x00000000)
+  #define MCSCHEDS_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Chunk_Error_Status_OFF ( 8)
+  #define MCSCHEDS_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Chunk_Error_Status_WID ( 8)
+  #define MCSCHEDS_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Chunk_Error_Status_MSK (0x0000FF00)
+  #define MCSCHEDS_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Chunk_Error_Status_MAX (0x000000FF)
+  #define MCSCHEDS_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Chunk_Error_Status_DEF (0x00000000)
+  #define MCSCHEDS_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Rank_Error_Status_OFF (16)
+  #define MCSCHEDS_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Rank_Error_Status_WID ( 4)
+  #define MCSCHEDS_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Rank_Error_Status_MSK (0x000F0000)
+  #define MCSCHEDS_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Rank_Error_Status_MAX (0x0000000F)
+  #define MCSCHEDS_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Rank_Error_Status_DEF (0x00000000)
+  #define MCSCHEDS_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Byte_Group_Error_Status_OFF (32)
+  #define MCSCHEDS_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Byte_Group_Error_Status_WID ( 9)
+  #define MCSCHEDS_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Byte_Group_Error_Status_MSK (0x1FF00000000)
+  #define MCSCHEDS_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Byte_Group_Error_Status_MAX (0x000001FF)
+  #define MCSCHEDS_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Byte_Group_Error_Status_DEF (0x00000000)
+  #define MCSCHEDS_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_WDB_Rd_Chunk_Num_Status_OFF (52)
+  #define MCSCHEDS_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_WDB_Rd_Chunk_Num_Status_WID ( 3)
+  #define MCSCHEDS_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_WDB_Rd_Chunk_Num_Status_MSK (0x70000000000000)
+  #define MCSCHEDS_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_WDB_Rd_Chunk_Num_Status_MAX (0x00000007)
+  #define MCSCHEDS_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_WDB_Rd_Chunk_Num_Status_DEF (0x00000000)
+  #define MCSCHEDS_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Nth_Error_OFF (56)
+  #define MCSCHEDS_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Nth_Error_WID ( 6)
+  #define MCSCHEDS_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Nth_Error_MSK (0x3F00000000000000)
+  #define MCSCHEDS_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Nth_Error_MAX (0x0000003F)
+  #define MCSCHEDS_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Nth_Error_DEF (0x00000000)
+
+#define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_0_REG                    (0x00004CF0)
+  #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_0_Counter_Pointer_OFF    ( 0)
+  #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_0_Counter_Pointer_WID    ( 7)
+  #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_0_Counter_Pointer_MSK    (0x0000007F)
+  #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_0_Counter_Pointer_MAX    (0x0000007F)
+  #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_0_Counter_Pointer_DEF    (0x0000007F)
+  #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_0_Counter_Control_OFF    ( 7)
+  #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_0_Counter_Control_WID    ( 2)
+  #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_0_Counter_Control_MSK    (0x00000180)
+  #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_0_Counter_Control_MAX    (0x00000003)
+  #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_0_Counter_Control_DEF    (0x00000000)
+
+#define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_1_REG                    (0x00004CF4)
+  #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_1_Counter_Pointer_OFF    ( 0)
+  #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_1_Counter_Pointer_WID    ( 7)
+  #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_1_Counter_Pointer_MSK    (0x0000007F)
+  #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_1_Counter_Pointer_MAX    (0x0000007F)
+  #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_1_Counter_Pointer_DEF    (0x0000007F)
+  #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_1_Counter_Control_OFF    ( 7)
+  #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_1_Counter_Control_WID    ( 2)
+  #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_1_Counter_Control_MSK    (0x00000180)
+  #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_1_Counter_Control_MAX    (0x00000003)
+  #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_1_Counter_Control_DEF    (0x00000000)
+
+#define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_2_REG                    (0x00004CF8)
+  #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_2_Counter_Pointer_OFF    ( 0)
+  #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_2_Counter_Pointer_WID    ( 7)
+  #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_2_Counter_Pointer_MSK    (0x0000007F)
+  #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_2_Counter_Pointer_MAX    (0x0000007F)
+  #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_2_Counter_Pointer_DEF    (0x0000007F)
+  #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_2_Counter_Control_OFF    ( 7)
+  #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_2_Counter_Control_WID    ( 2)
+  #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_2_Counter_Control_MSK    (0x00000180)
+  #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_2_Counter_Control_MAX    (0x00000003)
+  #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_2_Counter_Control_DEF    (0x00000000)
+
+#define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_3_REG                    (0x00004CFC)
+  #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_3_Counter_Pointer_OFF    ( 0)
+  #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_3_Counter_Pointer_WID    ( 7)
+  #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_3_Counter_Pointer_MSK    (0x0000007F)
+  #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_3_Counter_Pointer_MAX    (0x0000007F)
+  #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_3_Counter_Pointer_DEF    (0x0000007F)
+  #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_3_Counter_Control_OFF    ( 7)
+  #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_3_Counter_Control_WID    ( 2)
+  #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_3_Counter_Control_MSK    (0x00000180)
+  #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_3_Counter_Control_MAX    (0x00000003)
+  #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_3_Counter_Control_DEF    (0x00000000)
+
+#define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_4_REG                    (0x00004D00)
+  #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_4_Counter_Pointer_OFF    ( 0)
+  #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_4_Counter_Pointer_WID    ( 7)
+  #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_4_Counter_Pointer_MSK    (0x0000007F)
+  #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_4_Counter_Pointer_MAX    (0x0000007F)
+  #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_4_Counter_Pointer_DEF    (0x0000007F)
+  #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_4_Counter_Control_OFF    ( 7)
+  #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_4_Counter_Control_WID    ( 2)
+  #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_4_Counter_Control_MSK    (0x00000180)
+  #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_4_Counter_Control_MAX    (0x00000003)
+  #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_4_Counter_Control_DEF    (0x00000000)
+
+#define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_5_REG                    (0x00004D04)
+  #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_5_Counter_Pointer_OFF    ( 0)
+  #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_5_Counter_Pointer_WID    ( 7)
+  #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_5_Counter_Pointer_MSK    (0x0000007F)
+  #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_5_Counter_Pointer_MAX    (0x0000007F)
+  #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_5_Counter_Pointer_DEF    (0x0000007F)
+  #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_5_Counter_Control_OFF    ( 7)
+  #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_5_Counter_Control_WID    ( 2)
+  #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_5_Counter_Control_MSK    (0x00000180)
+  #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_5_Counter_Control_MAX    (0x00000003)
+  #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_5_Counter_Control_DEF    (0x00000000)
+
+#define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_6_REG                    (0x00004D08)
+  #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_6_Counter_Pointer_OFF    ( 0)
+  #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_6_Counter_Pointer_WID    ( 7)
+  #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_6_Counter_Pointer_MSK    (0x0000007F)
+  #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_6_Counter_Pointer_MAX    (0x0000007F)
+  #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_6_Counter_Pointer_DEF    (0x0000007F)
+  #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_6_Counter_Control_OFF    ( 7)
+  #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_6_Counter_Control_WID    ( 2)
+  #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_6_Counter_Control_MSK    (0x00000180)
+  #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_6_Counter_Control_MAX    (0x00000003)
+  #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_6_Counter_Control_DEF    (0x00000000)
+
+#define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_7_REG                    (0x00004D0C)
+  #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_7_Counter_Pointer_OFF    ( 0)
+  #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_7_Counter_Pointer_WID    ( 7)
+  #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_7_Counter_Pointer_MSK    (0x0000007F)
+  #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_7_Counter_Pointer_MAX    (0x0000007F)
+  #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_7_Counter_Pointer_DEF    (0x0000007F)
+  #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_7_Counter_Control_OFF    ( 7)
+  #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_7_Counter_Control_WID    ( 2)
+  #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_7_Counter_Control_MSK    (0x00000180)
+  #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_7_Counter_Control_MAX    (0x00000003)
+  #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_7_Counter_Control_DEF    (0x00000000)
+
+#define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_8_REG                    (0x00004D10)
+  #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_8_Counter_Pointer_OFF    ( 0)
+  #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_8_Counter_Pointer_WID    ( 7)
+  #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_8_Counter_Pointer_MSK    (0x0000007F)
+  #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_8_Counter_Pointer_MAX    (0x0000007F)
+  #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_8_Counter_Pointer_DEF    (0x0000007F)
+  #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_8_Counter_Control_OFF    ( 7)
+  #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_8_Counter_Control_WID    ( 2)
+  #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_8_Counter_Control_MSK    (0x00000180)
+  #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_8_Counter_Control_MAX    (0x00000003)
+  #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_8_Counter_Control_DEF    (0x00000000)
+
+#define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_0_REG                 (0x00004D14)
+  #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_0_Counter_Status_OFF  ( 0)
+  #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_0_Counter_Status_WID  (23)
+  #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_0_Counter_Status_MSK  (0x007FFFFF)
+  #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_0_Counter_Status_MAX  (0x007FFFFF)
+  #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_0_Counter_Status_DEF  (0x00000000)
+
+#define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_1_REG                 (0x00004D18)
+  #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_1_Counter_Status_OFF  ( 0)
+  #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_1_Counter_Status_WID  (23)
+  #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_1_Counter_Status_MSK  (0x007FFFFF)
+  #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_1_Counter_Status_MAX  (0x007FFFFF)
+  #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_1_Counter_Status_DEF  (0x00000000)
+
+#define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_2_REG                 (0x00004D1C)
+  #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_2_Counter_Status_OFF  ( 0)
+  #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_2_Counter_Status_WID  (23)
+  #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_2_Counter_Status_MSK  (0x007FFFFF)
+  #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_2_Counter_Status_MAX  (0x007FFFFF)
+  #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_2_Counter_Status_DEF  (0x00000000)
+
+#define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_3_REG                 (0x00004D20)
+  #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_3_Counter_Status_OFF  ( 0)
+  #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_3_Counter_Status_WID  (23)
+  #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_3_Counter_Status_MSK  (0x007FFFFF)
+  #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_3_Counter_Status_MAX  (0x007FFFFF)
+  #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_3_Counter_Status_DEF  (0x00000000)
+
+#define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_4_REG                 (0x00004D24)
+  #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_4_Counter_Status_OFF  ( 0)
+  #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_4_Counter_Status_WID  (23)
+  #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_4_Counter_Status_MSK  (0x007FFFFF)
+  #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_4_Counter_Status_MAX  (0x007FFFFF)
+  #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_4_Counter_Status_DEF  (0x00000000)
+
+#define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_5_REG                 (0x00004D28)
+  #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_5_Counter_Status_OFF  ( 0)
+  #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_5_Counter_Status_WID  (23)
+  #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_5_Counter_Status_MSK  (0x007FFFFF)
+  #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_5_Counter_Status_MAX  (0x007FFFFF)
+  #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_5_Counter_Status_DEF  (0x00000000)
+
+#define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_6_REG                 (0x00004D2C)
+  #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_6_Counter_Status_OFF  ( 0)
+  #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_6_Counter_Status_WID  (23)
+  #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_6_Counter_Status_MSK  (0x007FFFFF)
+  #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_6_Counter_Status_MAX  (0x007FFFFF)
+  #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_6_Counter_Status_DEF  (0x00000000)
+
+#define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_7_REG                 (0x00004D30)
+  #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_7_Counter_Status_OFF  ( 0)
+  #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_7_Counter_Status_WID  (23)
+  #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_7_Counter_Status_MSK  (0x007FFFFF)
+  #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_7_Counter_Status_MAX  (0x007FFFFF)
+  #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_7_Counter_Status_DEF  (0x00000000)
+
+#define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_8_REG                 (0x00004D34)
+  #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_8_Counter_Status_OFF  ( 0)
+  #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_8_Counter_Status_WID  (23)
+  #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_8_Counter_Status_MSK  (0x007FFFFF)
+  #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_8_Counter_Status_MAX  (0x007FFFFF)
+  #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_8_Counter_Status_DEF  (0x00000000)
+
+#define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_OVERFLOW_STATUS_REG          (0x00004D38)
+  #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_OVERFLOW_STATUS_Counter_Overflow_Status_OFF ( 0)
+  #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_OVERFLOW_STATUS_Counter_Overflow_Status_WID ( 9)
+  #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_OVERFLOW_STATUS_Counter_Overflow_Status_MSK (0x000001FF)
+  #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_OVERFLOW_STATUS_Counter_Overflow_Status_MAX (0x000001FF)
+  #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_OVERFLOW_STATUS_Counter_Overflow_Status_DEF (0x00000000)
+
+#define MCSCHEDS_CR_REUT_CH_ERROR_ADDR_REG                           (0x00004D80)
+  #define MCSCHEDS_CR_REUT_CH_ERROR_ADDR_Column_Address_OFF            ( 0)
+  #define MCSCHEDS_CR_REUT_CH_ERROR_ADDR_Column_Address_WID            (10)
+  #define MCSCHEDS_CR_REUT_CH_ERROR_ADDR_Column_Address_MSK            (0x000003FF)
+  #define MCSCHEDS_CR_REUT_CH_ERROR_ADDR_Column_Address_MAX            (0x000003FF)
+  #define MCSCHEDS_CR_REUT_CH_ERROR_ADDR_Column_Address_DEF            (0x00000000)
+  #define MCSCHEDS_CR_REUT_CH_ERROR_ADDR_Row_Address_OFF               (24)
+  #define MCSCHEDS_CR_REUT_CH_ERROR_ADDR_Row_Address_WID               (16)
+  #define MCSCHEDS_CR_REUT_CH_ERROR_ADDR_Row_Address_MSK               (0xFFFF000000)
+  #define MCSCHEDS_CR_REUT_CH_ERROR_ADDR_Row_Address_MAX               (0x0000FFFF)
+  #define MCSCHEDS_CR_REUT_CH_ERROR_ADDR_Row_Address_DEF               (0x00000000)
+  #define MCSCHEDS_CR_REUT_CH_ERROR_ADDR_Bank_Address_OFF              (48)
+  #define MCSCHEDS_CR_REUT_CH_ERROR_ADDR_Bank_Address_WID              ( 3)
+  #define MCSCHEDS_CR_REUT_CH_ERROR_ADDR_Bank_Address_MSK              (0x7000000000000)
+  #define MCSCHEDS_CR_REUT_CH_ERROR_ADDR_Bank_Address_MAX              (0x00000007)
+  #define MCSCHEDS_CR_REUT_CH_ERROR_ADDR_Bank_Address_DEF              (0x00000000)
+  #define MCSCHEDS_CR_REUT_CH_ERROR_ADDR_Rank_Address_OFF              (56)
+  #define MCSCHEDS_CR_REUT_CH_ERROR_ADDR_Rank_Address_WID              ( 2)
+  #define MCSCHEDS_CR_REUT_CH_ERROR_ADDR_Rank_Address_MSK              (0x300000000000000)
+  #define MCSCHEDS_CR_REUT_CH_ERROR_ADDR_Rank_Address_MAX              (0x00000003)
+  #define MCSCHEDS_CR_REUT_CH_ERROR_ADDR_Rank_Address_DEF              (0x00000000)
+
+#define MCSCHEDS_CR_REUT_CH_ERR_WDB_CAPTURE_STATUS_REG               (0x00004D88)
+  #define MCSCHEDS_CR_REUT_CH_ERR_WDB_CAPTURE_STATUS_WDB_Current_Error_Pointer_OFF ( 0)
+  #define MCSCHEDS_CR_REUT_CH_ERR_WDB_CAPTURE_STATUS_WDB_Current_Error_Pointer_WID ( 6)
+  #define MCSCHEDS_CR_REUT_CH_ERR_WDB_CAPTURE_STATUS_WDB_Current_Error_Pointer_MSK (0x0000003F)
+  #define MCSCHEDS_CR_REUT_CH_ERR_WDB_CAPTURE_STATUS_WDB_Current_Error_Pointer_MAX (0x0000003F)
+  #define MCSCHEDS_CR_REUT_CH_ERR_WDB_CAPTURE_STATUS_WDB_Current_Error_Pointer_DEF (0x00000000)
+
+#define MCSCHEDS_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_REG                  (0x00004D8C)
+  #define MCSCHEDS_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_Enable_WDB_Error_Capture_OFF ( 0)
+  #define MCSCHEDS_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_Enable_WDB_Error_Capture_WID ( 1)
+  #define MCSCHEDS_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_Enable_WDB_Error_Capture_MSK (0x00000001)
+  #define MCSCHEDS_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_Enable_WDB_Error_Capture_MAX (0x00000001)
+  #define MCSCHEDS_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_Enable_WDB_Error_Capture_DEF (0x00000000)
+  #define MCSCHEDS_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_WDB_Starting_Error_Pointer_OFF ( 8)
+  #define MCSCHEDS_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_WDB_Starting_Error_Pointer_WID ( 6)
+  #define MCSCHEDS_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_WDB_Starting_Error_Pointer_MSK (0x00003F00)
+  #define MCSCHEDS_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_WDB_Starting_Error_Pointer_MAX (0x0000003F)
+  #define MCSCHEDS_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_WDB_Starting_Error_Pointer_DEF (0x00000000)
+  #define MCSCHEDS_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_WDB_Ending_Error_Pointer_OFF (16)
+  #define MCSCHEDS_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_WDB_Ending_Error_Pointer_WID ( 6)
+  #define MCSCHEDS_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_WDB_Ending_Error_Pointer_MSK (0x003F0000)
+  #define MCSCHEDS_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_WDB_Ending_Error_Pointer_MAX (0x0000003F)
+  #define MCSCHEDS_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_WDB_Ending_Error_Pointer_DEF (0x00000000)
+
+#define MCSCHEDS_CR_REUT_CH_MISC_CKE_CTRL_REG                        (0x00004D90)
+  #define MCSCHEDS_CR_REUT_CH_MISC_CKE_CTRL_CKE_Override_OFF           ( 0)
+  #define MCSCHEDS_CR_REUT_CH_MISC_CKE_CTRL_CKE_Override_WID           ( 4)
+  #define MCSCHEDS_CR_REUT_CH_MISC_CKE_CTRL_CKE_Override_MSK           (0x0000000F)
+  #define MCSCHEDS_CR_REUT_CH_MISC_CKE_CTRL_CKE_Override_MAX           (0x0000000F)
+  #define MCSCHEDS_CR_REUT_CH_MISC_CKE_CTRL_CKE_Override_DEF           (0x0000000F)
+  #define MCSCHEDS_CR_REUT_CH_MISC_CKE_CTRL_CKE_En_Start_Test_Sync_OFF ( 8)
+  #define MCSCHEDS_CR_REUT_CH_MISC_CKE_CTRL_CKE_En_Start_Test_Sync_WID ( 1)
+  #define MCSCHEDS_CR_REUT_CH_MISC_CKE_CTRL_CKE_En_Start_Test_Sync_MSK (0x00000100)
+  #define MCSCHEDS_CR_REUT_CH_MISC_CKE_CTRL_CKE_En_Start_Test_Sync_MAX (0x00000001)
+  #define MCSCHEDS_CR_REUT_CH_MISC_CKE_CTRL_CKE_En_Start_Test_Sync_DEF (0x00000000)
+  #define MCSCHEDS_CR_REUT_CH_MISC_CKE_CTRL_CKE_On_OFF                 (16)
+  #define MCSCHEDS_CR_REUT_CH_MISC_CKE_CTRL_CKE_On_WID                 ( 4)
+  #define MCSCHEDS_CR_REUT_CH_MISC_CKE_CTRL_CKE_On_MSK                 (0x000F0000)
+  #define MCSCHEDS_CR_REUT_CH_MISC_CKE_CTRL_CKE_On_MAX                 (0x0000000F)
+  #define MCSCHEDS_CR_REUT_CH_MISC_CKE_CTRL_CKE_On_DEF                 (0x00000000)
+
+#define MCSCHEDS_CR_REUT_CH_MISC_ODT_CTRL_REG                        (0x00004D94)
+  #define MCSCHEDS_CR_REUT_CH_MISC_ODT_CTRL_ODT_Override_OFF           ( 0)
+  #define MCSCHEDS_CR_REUT_CH_MISC_ODT_CTRL_ODT_Override_WID           ( 4)
+  #define MCSCHEDS_CR_REUT_CH_MISC_ODT_CTRL_ODT_Override_MSK           (0x0000000F)
+  #define MCSCHEDS_CR_REUT_CH_MISC_ODT_CTRL_ODT_Override_MAX           (0x0000000F)
+  #define MCSCHEDS_CR_REUT_CH_MISC_ODT_CTRL_ODT_Override_DEF           (0x0000000F)
+  #define MCSCHEDS_CR_REUT_CH_MISC_ODT_CTRL_ODT_On_OFF                 (16)
+  #define MCSCHEDS_CR_REUT_CH_MISC_ODT_CTRL_ODT_On_WID                 ( 4)
+  #define MCSCHEDS_CR_REUT_CH_MISC_ODT_CTRL_ODT_On_MSK                 (0x000F0000)
+  #define MCSCHEDS_CR_REUT_CH_MISC_ODT_CTRL_ODT_On_MAX                 (0x0000000F)
+  #define MCSCHEDS_CR_REUT_CH_MISC_ODT_CTRL_ODT_On_DEF                 (0x00000000)
+  #define MCSCHEDS_CR_REUT_CH_MISC_ODT_CTRL_MPR_Train_DDR_On_OFF       (31)
+  #define MCSCHEDS_CR_REUT_CH_MISC_ODT_CTRL_MPR_Train_DDR_On_WID       ( 1)
+  #define MCSCHEDS_CR_REUT_CH_MISC_ODT_CTRL_MPR_Train_DDR_On_MSK       (0x80000000)
+  #define MCSCHEDS_CR_REUT_CH_MISC_ODT_CTRL_MPR_Train_DDR_On_MAX       (0x00000001)
+  #define MCSCHEDS_CR_REUT_CH_MISC_ODT_CTRL_MPR_Train_DDR_On_DEF       (0x00000000)
+
+#define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_REG                        (0x00004D98)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_Enable_CADB_on_Deselect_OFF ( 0)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_Enable_CADB_on_Deselect_WID ( 1)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_Enable_CADB_on_Deselect_MSK (0x00000001)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_Enable_CADB_on_Deselect_MAX (0x00000001)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_Enable_CADB_on_Deselect_DEF (0x00000000)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_Enable_CADB_Always_On_OFF  ( 1)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_Enable_CADB_Always_On_WID  ( 1)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_Enable_CADB_Always_On_MSK  (0x00000002)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_Enable_CADB_Always_On_MAX  (0x00000001)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_Enable_CADB_Always_On_DEF  (0x00000000)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_CMD_Deselect_Start_OFF  ( 2)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_CMD_Deselect_Start_WID  ( 4)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_CMD_Deselect_Start_MSK  (0x0000003C)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_CMD_Deselect_Start_MAX  (0x0000000F)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_CMD_Deselect_Start_DEF  (0x00000000)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_CMD_Deselect_Stop_OFF  ( 6)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_CMD_Deselect_Stop_WID  ( 4)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_CMD_Deselect_Stop_MSK  (0x000003C0)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_CMD_Deselect_Stop_MAX  (0x0000000F)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_CMD_Deselect_Stop_DEF  (0x00000000)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_Lane_Deselect_Enable_OFF  ( 10)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_Lane_Deselect_Enable_WID  ( 4)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_Lane_Deselect_Enable_MSK  (0x00003C00)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_Lane_Deselect_Enable_MAX  (0x0000000F)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_Lane_Deselect_Enable_DEF  (0x00000000)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_CAS_Select_Enable_OFF  ( 14)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_CAS_Select_Enable_WID  ( 2)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_CAS_Select_Enable_MSK  (0x0000C000)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_CAS_Select_Enable_MAX  (0x00000003)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_CAS_Select_Enable_DEF  (0x00000000)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_ACT_Select_Enable_OFF  ( 16)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_ACT_Select_Enable_WID  ( 2)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_ACT_Select_Enable_MSK  (0x00030000)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_ACT_Select_Enable_MAX  (0x00000003)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_ACT_Select_Enable_DEF  (0x00000000)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_PRE_Select_Enable_OFF  ( 18)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_PRE_Select_Enable_WID  ( 2)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_PRE_Select_Enable_MSK  (0x000C0000)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_PRE_Select_Enable_MAX  (0x00000003)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_PRE_Select_Enable_DEF  (0x00000000)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_Save_Current_Seed_OFF  ( 20)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_Save_Current_Seed_WID  ( 4)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_Save_Current_Seed_MSK  (0x00F00000)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_Save_Current_Seed_MAX  (0x0000000F)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_Save_Current_Seed_DEF  (0x00000000)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_Reload_Starting_Seed_OFF  ( 24)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_Reload_Starting_Seed_WID  ( 4)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_Reload_Starting_Seed_MSK  (0x0F000000)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_Reload_Starting_Seed_MAX  (0x0000000F)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_Reload_Starting_Seed_DEF  (0x00000000)
+
+#define MCSCHEDS_CR_REUT_CH_PAT_CADB_MRS_REG                         (0x00004D9C)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MRS_MRS_Gap_OFF                 ( 0)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MRS_MRS_Gap_WID                 ( 3)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MRS_MRS_Gap_MSK                 (0x00000007)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MRS_MRS_Gap_MAX                 (0x00000007)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MRS_MRS_Gap_DEF                 (0x00000002)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MRS_CADB_MRS_Start_Pointer_OFF  ( 8)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MRS_CADB_MRS_Start_Pointer_WID  ( 3)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MRS_CADB_MRS_Start_Pointer_MSK  (0x00000700)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MRS_CADB_MRS_Start_Pointer_MAX  (0x00000007)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MRS_CADB_MRS_Start_Pointer_DEF  (0x00000000)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MRS_CADB_MRS_End_Pointer_OFF    (16)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MRS_CADB_MRS_End_Pointer_WID    ( 3)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MRS_CADB_MRS_End_Pointer_MSK    (0x00070000)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MRS_CADB_MRS_End_Pointer_MAX    (0x00000007)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MRS_CADB_MRS_End_Pointer_DEF    (0x00000007)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MRS_CADB_MRS_Current_Pointer_OFF (24)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MRS_CADB_MRS_Current_Pointer_WID ( 3)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MRS_CADB_MRS_Current_Pointer_MSK (0x07000000)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MRS_CADB_MRS_Current_Pointer_MAX (0x00000007)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MRS_CADB_MRS_Current_Pointer_DEF (0x00000000)
+
+#define MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_CTRL_REG                    (0x00004DA0)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_CTRL_Mux0_Control_OFF       ( 0)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_CTRL_Mux0_Control_WID       ( 2)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_CTRL_Mux0_Control_MSK       (0x00000003)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_CTRL_Mux0_Control_MAX       (0x00000003)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_CTRL_Mux0_Control_DEF       (0x00000001)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_CTRL_Mux1_Control_OFF       ( 4)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_CTRL_Mux1_Control_WID       ( 2)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_CTRL_Mux1_Control_MSK       (0x00000030)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_CTRL_Mux1_Control_MAX       (0x00000003)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_CTRL_Mux1_Control_DEF       (0x00000001)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_CTRL_Mux2_Control_OFF       ( 8)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_CTRL_Mux2_Control_WID       ( 2)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_CTRL_Mux2_Control_MSK       (0x00000300)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_CTRL_Mux2_Control_MAX       (0x00000003)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_CTRL_Mux2_Control_DEF       (0x00000001)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_CTRL_Select_Mux0_Control_OFF       ( 16)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_CTRL_Select_Mux0_Control_WID       ( 2)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_CTRL_Select_Mux0_Control_MSK       (0x00030000)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_CTRL_Select_Mux0_Control_MAX       (0x00000003)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_CTRL_Select_Mux0_Control_DEF       (0x00000001)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_CTRL_Select_Mux1_Control_OFF       ( 20)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_CTRL_Select_Mux1_Control_WID       ( 2)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_CTRL_Select_Mux1_Control_MSK       (0x00300000)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_CTRL_Select_Mux1_Control_MAX       (0x00000003)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_CTRL_Select_Mux1_Control_DEF       (0x00000001)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_CTRL_Select_Mux2_Control_OFF       ( 24)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_CTRL_Select_Mux2_Control_WID       ( 2)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_CTRL_Select_Mux2_Control_MSK       (0x03000000)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_CTRL_Select_Mux2_Control_MAX       (0x00000003)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_CTRL_Select_Mux2_Control_DEF       (0x00000001)
+
+#define MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_PB_0_REG                    (0x00004DA4)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_PB_0_Pattern_Buffer_OFF     ( 0)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_PB_0_Pattern_Buffer_WID     (16)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_PB_0_Pattern_Buffer_MSK     (0x0000FFFF)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_PB_0_Pattern_Buffer_MAX     (0x0000FFFF)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_PB_0_Pattern_Buffer_DEF     (0x00000000)
+
+#define MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_PB_1_REG                    (0x00004DA8)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_PB_1_Pattern_Buffer_OFF     ( 0)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_PB_1_Pattern_Buffer_WID     (16)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_PB_1_Pattern_Buffer_MSK     (0x0000FFFF)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_PB_1_Pattern_Buffer_MAX     (0x0000FFFF)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_PB_1_Pattern_Buffer_DEF     (0x00000000)
+
+#define MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_PB_2_REG                    (0x00004DAC)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_PB_2_Pattern_Buffer_OFF     ( 0)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_PB_2_Pattern_Buffer_WID     (16)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_PB_2_Pattern_Buffer_MSK     (0x0000FFFF)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_PB_2_Pattern_Buffer_MAX     (0x0000FFFF)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_PB_2_Pattern_Buffer_DEF     (0x00000000)
+
+#define MCSCHEDS_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_REG                  (0x00004DB0)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_L_data_select_OFF    ( 0)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_L_data_select_WID    ( 1)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_L_data_select_MSK    (0x00000001)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_L_data_select_MAX    (0x00000001)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_L_data_select_DEF    (0x00000000)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_Enable_Sweep_Frequency_OFF ( 1)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_Enable_Sweep_Frequency_WID ( 1)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_Enable_Sweep_Frequency_MSK (0x00000002)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_Enable_Sweep_Frequency_MAX (0x00000001)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_Enable_Sweep_Frequency_DEF (0x00000000)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_L_counter_OFF        ( 8)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_L_counter_WID        ( 8)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_L_counter_MSK        (0x0000FF00)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_L_counter_MAX        (0x000000FF)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_L_counter_DEF        (0x00000001)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_M_counter_OFF        (16)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_M_counter_WID        ( 8)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_M_counter_MSK        (0x00FF0000)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_M_counter_MAX        (0x000000FF)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_M_counter_DEF        (0x00000001)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_N_counter_OFF        (24)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_N_counter_WID        ( 8)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_N_counter_MSK        (0xFF000000)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_N_counter_MAX        (0x000000FF)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_N_counter_DEF        (0x00000001)
+
+#define MCSCHEDS_CR_REUT_CH_PAT_CADB_WRITE_POINTER_REG               (0x00004DBC)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_WRITE_POINTER_CADB_Write_Pointer_OFF ( 0)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_WRITE_POINTER_CADB_Write_Pointer_WID ( 3)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_WRITE_POINTER_CADB_Write_Pointer_MSK (0x00000007)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_WRITE_POINTER_CADB_Write_Pointer_MAX (0x00000007)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_WRITE_POINTER_CADB_Write_Pointer_DEF (0x00000000)
+
+#define MCSCHEDS_CR_REUT_CH_PAT_CADB_PROG_REG                        (0x00004DC0)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_Address_OFF      ( 0)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_Address_WID      (16)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_Address_MSK      (0x0000FFFF)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_Address_MAX      (0x0000FFFF)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_Address_DEF      (0x00000000)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_Bank_OFF         (24)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_Bank_WID         ( 3)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_Bank_MSK         (0x07000000)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_Bank_MAX         (0x00000007)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_Bank_DEF         (0x00000000)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_CS_OFF           (32)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_CS_WID           ( 4)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_CS_MSK           (0xF00000000)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_CS_MAX           (0x0000000F)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_CS_DEF           (0x00000000)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_Control_OFF      (40)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_Control_WID      ( 3)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_Control_MSK      (0x70000000000)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_Control_MAX      (0x00000007)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_Control_DEF      (0x00000000)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_ODT_OFF          (48)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_ODT_WID          ( 4)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_ODT_MSK          (0xF000000000000)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_ODT_MAX          (0x0000000F)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_ODT_DEF          (0x00000000)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_CKE_OFF          (56)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_CKE_WID          ( 4)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_CKE_MSK          (0xF00000000000000)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_CKE_MAX          (0x0000000F)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_CKE_DEF          (0x00000000)
+
+#define MCSCHEDS_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_0_REG                (0x00004DC8)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_0_Pattern_Buffer_OFF ( 0)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_0_Pattern_Buffer_WID (16)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_0_Pattern_Buffer_MSK (0x0000FFFF)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_0_Pattern_Buffer_MAX (0x0000FFFF)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_0_Pattern_Buffer_DEF (0x00000000)
+
+#define MCSCHEDS_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_1_REG                (0x00004DCC)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_1_Pattern_Buffer_OFF ( 0)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_1_Pattern_Buffer_WID (16)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_1_Pattern_Buffer_MSK (0x0000FFFF)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_1_Pattern_Buffer_MAX (0x0000FFFF)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_1_Pattern_Buffer_DEF (0x00000000)
+
+#define MCSCHEDS_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_2_REG                (0x00004DD0)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_2_Pattern_Buffer_OFF ( 0)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_2_Pattern_Buffer_WID (16)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_2_Pattern_Buffer_MSK (0x0000FFFF)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_2_Pattern_Buffer_MAX (0x0000FFFF)
+  #define MCSCHEDS_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_2_Pattern_Buffer_DEF (0x00000000)
+
+#define MCMNTS_CR_REUT_CH_PAT_WDB_CL_CTRL_REG                        (0x00004E00)
+  #define MCMNTS_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_Increment_Rate_OFF     ( 0)
+  #define MCMNTS_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_Increment_Rate_WID     ( 5)
+  #define MCMNTS_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_Increment_Rate_MSK     (0x0000001F)
+  #define MCMNTS_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_Increment_Rate_MAX     (0x0000001F)
+  #define MCMNTS_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_Increment_Rate_DEF     (0x00000000)
+  #define MCMNTS_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_Increment_Scale_OFF    ( 5)
+  #define MCMNTS_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_Increment_Scale_WID    ( 1)
+  #define MCMNTS_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_Increment_Scale_MSK    (0x00000020)
+  #define MCMNTS_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_Increment_Scale_MAX    (0x00000001)
+  #define MCMNTS_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_Increment_Scale_DEF    (0x00000000)
+  #define MCMNTS_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_Start_Pointer_OFF      ( 8)
+  #define MCMNTS_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_Start_Pointer_WID      ( 6)
+  #define MCMNTS_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_Start_Pointer_MSK      (0x00003F00)
+  #define MCMNTS_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_Start_Pointer_MAX      (0x0000003F)
+  #define MCMNTS_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_Start_Pointer_DEF      (0x00000000)
+  #define MCMNTS_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_End_Pointer_OFF        (16)
+  #define MCMNTS_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_End_Pointer_WID        ( 6)
+  #define MCMNTS_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_End_Pointer_MSK        (0x003F0000)
+  #define MCMNTS_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_End_Pointer_MAX        (0x0000003F)
+  #define MCMNTS_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_End_Pointer_DEF        (0x0000003F)
+
+#define MCMNTS_CR_REUT_CH_MISC_REFRESH_CTRL_REG                      (0x00004E04)
+  #define MCMNTS_CR_REUT_CH_MISC_REFRESH_CTRL_Refresh_Rank_Mask_OFF    ( 0)
+  #define MCMNTS_CR_REUT_CH_MISC_REFRESH_CTRL_Refresh_Rank_Mask_WID    ( 4)
+  #define MCMNTS_CR_REUT_CH_MISC_REFRESH_CTRL_Refresh_Rank_Mask_MSK    (0x0000000F)
+  #define MCMNTS_CR_REUT_CH_MISC_REFRESH_CTRL_Refresh_Rank_Mask_MAX    (0x0000000F)
+  #define MCMNTS_CR_REUT_CH_MISC_REFRESH_CTRL_Refresh_Rank_Mask_DEF    (0x00000000)
+  #define MCMNTS_CR_REUT_CH_MISC_REFRESH_CTRL_RefZQ_En_Start_Test_Sync_OFF ( 8)
+  #define MCMNTS_CR_REUT_CH_MISC_REFRESH_CTRL_RefZQ_En_Start_Test_Sync_WID ( 1)
+  #define MCMNTS_CR_REUT_CH_MISC_REFRESH_CTRL_RefZQ_En_Start_Test_Sync_MSK (0x00000100)
+  #define MCMNTS_CR_REUT_CH_MISC_REFRESH_CTRL_RefZQ_En_Start_Test_Sync_MAX (0x00000001)
+  #define MCMNTS_CR_REUT_CH_MISC_REFRESH_CTRL_RefZQ_En_Start_Test_Sync_DEF (0x00000000)
+  #define MCMNTS_CR_REUT_CH_MISC_REFRESH_CTRL_Panic_Refresh_Only_OFF   (31)
+  #define MCMNTS_CR_REUT_CH_MISC_REFRESH_CTRL_Panic_Refresh_Only_WID   ( 1)
+  #define MCMNTS_CR_REUT_CH_MISC_REFRESH_CTRL_Panic_Refresh_Only_MSK   (0x80000000)
+  #define MCMNTS_CR_REUT_CH_MISC_REFRESH_CTRL_Panic_Refresh_Only_MAX   (0x00000001)
+  #define MCMNTS_CR_REUT_CH_MISC_REFRESH_CTRL_Panic_Refresh_Only_DEF   (0x00000000)
+
+#define MCMNTS_CR_REUT_CH_MISC_ZQ_CTRL_REG                           (0x00004E08)
+  #define MCMNTS_CR_REUT_CH_MISC_ZQ_CTRL_ZQ_Rank_Mask_OFF              ( 0)
+  #define MCMNTS_CR_REUT_CH_MISC_ZQ_CTRL_ZQ_Rank_Mask_WID              ( 4)
+  #define MCMNTS_CR_REUT_CH_MISC_ZQ_CTRL_ZQ_Rank_Mask_MSK              (0x0000000F)
+  #define MCMNTS_CR_REUT_CH_MISC_ZQ_CTRL_ZQ_Rank_Mask_MAX              (0x0000000F)
+  #define MCMNTS_CR_REUT_CH_MISC_ZQ_CTRL_ZQ_Rank_Mask_DEF              (0x00000000)
+  #define MCMNTS_CR_REUT_CH_MISC_ZQ_CTRL_Always_Do_ZQ_OFF              (31)
+  #define MCMNTS_CR_REUT_CH_MISC_ZQ_CTRL_Always_Do_ZQ_WID              ( 1)
+  #define MCMNTS_CR_REUT_CH_MISC_ZQ_CTRL_Always_Do_ZQ_MSK              (0x80000000)
+  #define MCMNTS_CR_REUT_CH_MISC_ZQ_CTRL_Always_Do_ZQ_MAX              (0x00000001)
+  #define MCMNTS_CR_REUT_CH_MISC_ZQ_CTRL_Always_Do_ZQ_DEF              (0x00000000)
+
+#define MCMNTS_CR_LPDDR_MR_PARAMS_REG                                (0x00004E10)
+  #define MCMNTS_CR_LPDDR_MR_PARAMS_Rank_0_x32_OFF                     ( 0)
+  #define MCMNTS_CR_LPDDR_MR_PARAMS_Rank_0_x32_WID                     ( 1)
+  #define MCMNTS_CR_LPDDR_MR_PARAMS_Rank_0_x32_MSK                     (0x00000001)
+  #define MCMNTS_CR_LPDDR_MR_PARAMS_Rank_0_x32_MAX                     (0x00000001)
+  #define MCMNTS_CR_LPDDR_MR_PARAMS_Rank_0_x32_DEF                     (0x00000000)
+  #define MCMNTS_CR_LPDDR_MR_PARAMS_Rank_1_x32_OFF                     ( 1)
+  #define MCMNTS_CR_LPDDR_MR_PARAMS_Rank_1_x32_WID                     ( 1)
+  #define MCMNTS_CR_LPDDR_MR_PARAMS_Rank_1_x32_MSK                     (0x00000002)
+  #define MCMNTS_CR_LPDDR_MR_PARAMS_Rank_1_x32_MAX                     (0x00000001)
+  #define MCMNTS_CR_LPDDR_MR_PARAMS_Rank_1_x32_DEF                     (0x00000000)
+  #define MCMNTS_CR_LPDDR_MR_PARAMS_Rank_2_x32_OFF                     ( 2)
+  #define MCMNTS_CR_LPDDR_MR_PARAMS_Rank_2_x32_WID                     ( 1)
+  #define MCMNTS_CR_LPDDR_MR_PARAMS_Rank_2_x32_MSK                     (0x00000004)
+  #define MCMNTS_CR_LPDDR_MR_PARAMS_Rank_2_x32_MAX                     (0x00000001)
+  #define MCMNTS_CR_LPDDR_MR_PARAMS_Rank_2_x32_DEF                     (0x00000000)
+  #define MCMNTS_CR_LPDDR_MR_PARAMS_Rank_3_x32_OFF                     ( 3)
+  #define MCMNTS_CR_LPDDR_MR_PARAMS_Rank_3_x32_WID                     ( 1)
+  #define MCMNTS_CR_LPDDR_MR_PARAMS_Rank_3_x32_MSK                     (0x00000008)
+  #define MCMNTS_CR_LPDDR_MR_PARAMS_Rank_3_x32_MAX                     (0x00000001)
+  #define MCMNTS_CR_LPDDR_MR_PARAMS_Rank_3_x32_DEF                     (0x00000000)
+  #define MCMNTS_CR_LPDDR_MR_PARAMS_LPDDR2_OFF                         ( 4)
+  #define MCMNTS_CR_LPDDR_MR_PARAMS_LPDDR2_WID                         ( 1)
+  #define MCMNTS_CR_LPDDR_MR_PARAMS_LPDDR2_MSK                         (0x00000010)
+  #define MCMNTS_CR_LPDDR_MR_PARAMS_LPDDR2_MAX                         (0x00000001)
+  #define MCMNTS_CR_LPDDR_MR_PARAMS_LPDDR2_DEF                         (0x00000000)
+  #define MCMNTS_CR_LPDDR_MR_PARAMS_MR4_PERIOD_OFF                     ( 8)
+  #define MCMNTS_CR_LPDDR_MR_PARAMS_MR4_PERIOD_WID                     (16)
+  #define MCMNTS_CR_LPDDR_MR_PARAMS_MR4_PERIOD_MSK                     (0x00FFFF00)
+  #define MCMNTS_CR_LPDDR_MR_PARAMS_MR4_PERIOD_MAX                     (0x0000FFFF)
+  #define MCMNTS_CR_LPDDR_MR_PARAMS_MR4_PERIOD_DEF                     (0x00000000)
+
+#define MCMNTS_CR_LPDDR_MR_COMMAND_REG                               (0x00004E14)
+  #define MCMNTS_CR_LPDDR_MR_COMMAND_Address_OFF                       ( 0)
+  #define MCMNTS_CR_LPDDR_MR_COMMAND_Address_WID                       ( 8)
+  #define MCMNTS_CR_LPDDR_MR_COMMAND_Address_MSK                       (0x000000FF)
+  #define MCMNTS_CR_LPDDR_MR_COMMAND_Address_MAX                       (0x000000FF)
+  #define MCMNTS_CR_LPDDR_MR_COMMAND_Address_DEF                       (0x00000000)
+  #define MCMNTS_CR_LPDDR_MR_COMMAND_Data_OFF                          ( 8)
+  #define MCMNTS_CR_LPDDR_MR_COMMAND_Data_WID                          ( 8)
+  #define MCMNTS_CR_LPDDR_MR_COMMAND_Data_MSK                          (0x0000FF00)
+  #define MCMNTS_CR_LPDDR_MR_COMMAND_Data_MAX                          (0x000000FF)
+  #define MCMNTS_CR_LPDDR_MR_COMMAND_Data_DEF                          (0x00000000)
+  #define MCMNTS_CR_LPDDR_MR_COMMAND_Rank_OFF                          (16)
+  #define MCMNTS_CR_LPDDR_MR_COMMAND_Rank_WID                          ( 2)
+  #define MCMNTS_CR_LPDDR_MR_COMMAND_Rank_MSK                          (0x00030000)
+  #define MCMNTS_CR_LPDDR_MR_COMMAND_Rank_MAX                          (0x00000003)
+  #define MCMNTS_CR_LPDDR_MR_COMMAND_Rank_DEF                          (0x00000000)
+  #define MCMNTS_CR_LPDDR_MR_COMMAND_Write_OFF                         (18)
+  #define MCMNTS_CR_LPDDR_MR_COMMAND_Write_WID                         ( 1)
+  #define MCMNTS_CR_LPDDR_MR_COMMAND_Write_MSK                         (0x00040000)
+  #define MCMNTS_CR_LPDDR_MR_COMMAND_Write_MAX                         (0x00000001)
+  #define MCMNTS_CR_LPDDR_MR_COMMAND_Write_DEF                         (0x00000000)
+  #define MCMNTS_CR_LPDDR_MR_COMMAND_Init_MRW_OFF                      (19)
+  #define MCMNTS_CR_LPDDR_MR_COMMAND_Init_MRW_WID                      ( 1)
+  #define MCMNTS_CR_LPDDR_MR_COMMAND_Init_MRW_MSK                      (0x00080000)
+  #define MCMNTS_CR_LPDDR_MR_COMMAND_Init_MRW_MAX                      (0x00000001)
+  #define MCMNTS_CR_LPDDR_MR_COMMAND_Init_MRW_DEF                      (0x00000000)
+  #define MCMNTS_CR_LPDDR_MR_COMMAND_Busy_OFF                          (31)
+  #define MCMNTS_CR_LPDDR_MR_COMMAND_Busy_WID                          ( 1)
+  #define MCMNTS_CR_LPDDR_MR_COMMAND_Busy_MSK                          (0x80000000)
+  #define MCMNTS_CR_LPDDR_MR_COMMAND_Busy_MAX                          (0x00000001)
+  #define MCMNTS_CR_LPDDR_MR_COMMAND_Busy_DEF                          (0x00000000)
+
+#define MCMNTS_CR_LPDDR_MR_RESULT_REG                                (0x00004E18)
+  #define MCMNTS_CR_LPDDR_MR_RESULT_Device_0_OFF                       ( 0)
+  #define MCMNTS_CR_LPDDR_MR_RESULT_Device_0_WID                       ( 8)
+  #define MCMNTS_CR_LPDDR_MR_RESULT_Device_0_MSK                       (0x000000FF)
+  #define MCMNTS_CR_LPDDR_MR_RESULT_Device_0_MAX                       (0x000000FF)
+  #define MCMNTS_CR_LPDDR_MR_RESULT_Device_0_DEF                       (0x00000000)
+  #define MCMNTS_CR_LPDDR_MR_RESULT_Device_1_OFF                       ( 8)
+  #define MCMNTS_CR_LPDDR_MR_RESULT_Device_1_WID                       ( 8)
+  #define MCMNTS_CR_LPDDR_MR_RESULT_Device_1_MSK                       (0x0000FF00)
+  #define MCMNTS_CR_LPDDR_MR_RESULT_Device_1_MAX                       (0x000000FF)
+  #define MCMNTS_CR_LPDDR_MR_RESULT_Device_1_DEF                       (0x00000000)
+  #define MCMNTS_CR_LPDDR_MR_RESULT_Device_2_OFF                       (16)
+  #define MCMNTS_CR_LPDDR_MR_RESULT_Device_2_WID                       ( 8)
+  #define MCMNTS_CR_LPDDR_MR_RESULT_Device_2_MSK                       (0x00FF0000)
+  #define MCMNTS_CR_LPDDR_MR_RESULT_Device_2_MAX                       (0x000000FF)
+  #define MCMNTS_CR_LPDDR_MR_RESULT_Device_2_DEF                       (0x00000000)
+  #define MCMNTS_CR_LPDDR_MR_RESULT_Device_3_OFF                       (24)
+  #define MCMNTS_CR_LPDDR_MR_RESULT_Device_3_WID                       ( 8)
+  #define MCMNTS_CR_LPDDR_MR_RESULT_Device_3_MSK                       (0xFF000000)
+  #define MCMNTS_CR_LPDDR_MR_RESULT_Device_3_MAX                       (0x000000FF)
+  #define MCMNTS_CR_LPDDR_MR_RESULT_Device_3_DEF                       (0x00000000)
+
+#define MCMNTS_CR_LPDDR_MR4_RANK_TEMPERATURE_REG                     (0x00004E1C)
+  #define MCMNTS_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_0_OFF              ( 0)
+  #define MCMNTS_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_0_WID              ( 3)
+  #define MCMNTS_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_0_MSK              (0x00000007)
+  #define MCMNTS_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_0_MAX              (0x00000007)
+  #define MCMNTS_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_0_DEF              (0x00000003)
+  #define MCMNTS_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_1_OFF              ( 8)
+  #define MCMNTS_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_1_WID              ( 3)
+  #define MCMNTS_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_1_MSK              (0x00000700)
+  #define MCMNTS_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_1_MAX              (0x00000007)
+  #define MCMNTS_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_1_DEF              (0x00000003)
+  #define MCMNTS_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_2_OFF              (16)
+  #define MCMNTS_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_2_WID              ( 3)
+  #define MCMNTS_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_2_MSK              (0x00070000)
+  #define MCMNTS_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_2_MAX              (0x00000007)
+  #define MCMNTS_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_2_DEF              (0x00000003)
+  #define MCMNTS_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_3_OFF              (24)
+  #define MCMNTS_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_3_WID              ( 3)
+  #define MCMNTS_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_3_MSK              (0x07000000)
+  #define MCMNTS_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_3_MAX              (0x00000007)
+  #define MCMNTS_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_3_DEF              (0x00000003)
+
+#define MCMNTS_CR_DESWIZZLE_LOW_REG                                  (0x00004E20)
+  #define MCMNTS_CR_DESWIZZLE_LOW_Bit_0_OFF                            ( 0)
+  #define MCMNTS_CR_DESWIZZLE_LOW_Bit_0_WID                            ( 3)
+  #define MCMNTS_CR_DESWIZZLE_LOW_Bit_0_MSK                            (0x00000007)
+  #define MCMNTS_CR_DESWIZZLE_LOW_Bit_0_MAX                            (0x00000007)
+  #define MCMNTS_CR_DESWIZZLE_LOW_Bit_0_DEF                            (0x00000000)
+  #define MCMNTS_CR_DESWIZZLE_LOW_Bit_1_OFF                            ( 4)
+  #define MCMNTS_CR_DESWIZZLE_LOW_Bit_1_WID                            ( 3)
+  #define MCMNTS_CR_DESWIZZLE_LOW_Bit_1_MSK                            (0x00000070)
+  #define MCMNTS_CR_DESWIZZLE_LOW_Bit_1_MAX                            (0x00000007)
+  #define MCMNTS_CR_DESWIZZLE_LOW_Bit_1_DEF                            (0x00000001)
+  #define MCMNTS_CR_DESWIZZLE_LOW_Bit_2_OFF                            ( 8)
+  #define MCMNTS_CR_DESWIZZLE_LOW_Bit_2_WID                            ( 3)
+  #define MCMNTS_CR_DESWIZZLE_LOW_Bit_2_MSK                            (0x00000700)
+  #define MCMNTS_CR_DESWIZZLE_LOW_Bit_2_MAX                            (0x00000007)
+  #define MCMNTS_CR_DESWIZZLE_LOW_Bit_2_DEF                            (0x00000002)
+  #define MCMNTS_CR_DESWIZZLE_LOW_Bit_16_OFF                           (12)
+  #define MCMNTS_CR_DESWIZZLE_LOW_Bit_16_WID                           ( 3)
+  #define MCMNTS_CR_DESWIZZLE_LOW_Bit_16_MSK                           (0x00007000)
+  #define MCMNTS_CR_DESWIZZLE_LOW_Bit_16_MAX                           (0x00000007)
+  #define MCMNTS_CR_DESWIZZLE_LOW_Bit_16_DEF                           (0x00000000)
+  #define MCMNTS_CR_DESWIZZLE_LOW_Bit_17_OFF                           (16)
+  #define MCMNTS_CR_DESWIZZLE_LOW_Bit_17_WID                           ( 3)
+  #define MCMNTS_CR_DESWIZZLE_LOW_Bit_17_MSK                           (0x00070000)
+  #define MCMNTS_CR_DESWIZZLE_LOW_Bit_17_MAX                           (0x00000007)
+  #define MCMNTS_CR_DESWIZZLE_LOW_Bit_17_DEF                           (0x00000001)
+  #define MCMNTS_CR_DESWIZZLE_LOW_Bit_18_OFF                           (20)
+  #define MCMNTS_CR_DESWIZZLE_LOW_Bit_18_WID                           ( 3)
+  #define MCMNTS_CR_DESWIZZLE_LOW_Bit_18_MSK                           (0x00700000)
+  #define MCMNTS_CR_DESWIZZLE_LOW_Bit_18_MAX                           (0x00000007)
+  #define MCMNTS_CR_DESWIZZLE_LOW_Bit_18_DEF                           (0x00000002)
+  #define MCMNTS_CR_DESWIZZLE_LOW_Byte_0_OFF                           (24)
+  #define MCMNTS_CR_DESWIZZLE_LOW_Byte_0_WID                           ( 3)
+  #define MCMNTS_CR_DESWIZZLE_LOW_Byte_0_MSK                           (0x07000000)
+  #define MCMNTS_CR_DESWIZZLE_LOW_Byte_0_MAX                           (0x00000007)
+  #define MCMNTS_CR_DESWIZZLE_LOW_Byte_0_DEF                           (0x00000000)
+  #define MCMNTS_CR_DESWIZZLE_LOW_Byte_2_OFF                           (28)
+  #define MCMNTS_CR_DESWIZZLE_LOW_Byte_2_WID                           ( 3)
+  #define MCMNTS_CR_DESWIZZLE_LOW_Byte_2_MSK                           (0x70000000)
+  #define MCMNTS_CR_DESWIZZLE_LOW_Byte_2_MAX                           (0x00000007)
+  #define MCMNTS_CR_DESWIZZLE_LOW_Byte_2_DEF                           (0x00000002)
+
+#define MCMNTS_CR_DESWIZZLE_HIGH_REG                                 (0x00004E24)
+  #define MCMNTS_CR_DESWIZZLE_HIGH_Bit_32_OFF                          ( 0)
+  #define MCMNTS_CR_DESWIZZLE_HIGH_Bit_32_WID                          ( 3)
+  #define MCMNTS_CR_DESWIZZLE_HIGH_Bit_32_MSK                          (0x00000007)
+  #define MCMNTS_CR_DESWIZZLE_HIGH_Bit_32_MAX                          (0x00000007)
+  #define MCMNTS_CR_DESWIZZLE_HIGH_Bit_32_DEF                          (0x00000000)
+  #define MCMNTS_CR_DESWIZZLE_HIGH_Bit_33_OFF                          ( 4)
+  #define MCMNTS_CR_DESWIZZLE_HIGH_Bit_33_WID                          ( 3)
+  #define MCMNTS_CR_DESWIZZLE_HIGH_Bit_33_MSK                          (0x00000070)
+  #define MCMNTS_CR_DESWIZZLE_HIGH_Bit_33_MAX                          (0x00000007)
+  #define MCMNTS_CR_DESWIZZLE_HIGH_Bit_33_DEF                          (0x00000001)
+  #define MCMNTS_CR_DESWIZZLE_HIGH_Bit_34_OFF                          ( 8)
+  #define MCMNTS_CR_DESWIZZLE_HIGH_Bit_34_WID                          ( 3)
+  #define MCMNTS_CR_DESWIZZLE_HIGH_Bit_34_MSK                          (0x00000700)
+  #define MCMNTS_CR_DESWIZZLE_HIGH_Bit_34_MAX                          (0x00000007)
+  #define MCMNTS_CR_DESWIZZLE_HIGH_Bit_34_DEF                          (0x00000002)
+  #define MCMNTS_CR_DESWIZZLE_HIGH_Bit_48_OFF                          (12)
+  #define MCMNTS_CR_DESWIZZLE_HIGH_Bit_48_WID                          ( 3)
+  #define MCMNTS_CR_DESWIZZLE_HIGH_Bit_48_MSK                          (0x00007000)
+  #define MCMNTS_CR_DESWIZZLE_HIGH_Bit_48_MAX                          (0x00000007)
+  #define MCMNTS_CR_DESWIZZLE_HIGH_Bit_48_DEF                          (0x00000000)
+  #define MCMNTS_CR_DESWIZZLE_HIGH_Bit_49_OFF                          (16)
+  #define MCMNTS_CR_DESWIZZLE_HIGH_Bit_49_WID                          ( 3)
+  #define MCMNTS_CR_DESWIZZLE_HIGH_Bit_49_MSK                          (0x00070000)
+  #define MCMNTS_CR_DESWIZZLE_HIGH_Bit_49_MAX                          (0x00000007)
+  #define MCMNTS_CR_DESWIZZLE_HIGH_Bit_49_DEF                          (0x00000001)
+  #define MCMNTS_CR_DESWIZZLE_HIGH_Bit_50_OFF                          (20)
+  #define MCMNTS_CR_DESWIZZLE_HIGH_Bit_50_WID                          ( 3)
+  #define MCMNTS_CR_DESWIZZLE_HIGH_Bit_50_MSK                          (0x00700000)
+  #define MCMNTS_CR_DESWIZZLE_HIGH_Bit_50_MAX                          (0x00000007)
+  #define MCMNTS_CR_DESWIZZLE_HIGH_Bit_50_DEF                          (0x00000002)
+  #define MCMNTS_CR_DESWIZZLE_HIGH_Byte_4_OFF                          (24)
+  #define MCMNTS_CR_DESWIZZLE_HIGH_Byte_4_WID                          ( 3)
+  #define MCMNTS_CR_DESWIZZLE_HIGH_Byte_4_MSK                          (0x07000000)
+  #define MCMNTS_CR_DESWIZZLE_HIGH_Byte_4_MAX                          (0x00000007)
+  #define MCMNTS_CR_DESWIZZLE_HIGH_Byte_4_DEF                          (0x00000004)
+  #define MCMNTS_CR_DESWIZZLE_HIGH_Byte_6_OFF                          (28)
+  #define MCMNTS_CR_DESWIZZLE_HIGH_Byte_6_WID                          ( 3)
+  #define MCMNTS_CR_DESWIZZLE_HIGH_Byte_6_MSK                          (0x70000000)
+  #define MCMNTS_CR_DESWIZZLE_HIGH_Byte_6_MAX                          (0x00000007)
+  #define MCMNTS_CR_DESWIZZLE_HIGH_Byte_6_DEF                          (0x00000006)
+
+#define MCMNTS_CR_MC_REFRESH_STAGGER_REG                             (0x00004E8C)
+  #define MCMNTS_CR_MC_REFRESH_STAGGER_Ref_Interval_OFF                ( 0)
+  #define MCMNTS_CR_MC_REFRESH_STAGGER_Ref_Interval_WID                (11)
+  #define MCMNTS_CR_MC_REFRESH_STAGGER_Ref_Interval_MSK                (0x000007FF)
+  #define MCMNTS_CR_MC_REFRESH_STAGGER_Ref_Interval_MAX                (0x000007FF)
+  #define MCMNTS_CR_MC_REFRESH_STAGGER_Ref_Interval_DEF                (0x00000000)
+  #define MCMNTS_CR_MC_REFRESH_STAGGER_Ref_Stagger_En_OFF              (11)
+  #define MCMNTS_CR_MC_REFRESH_STAGGER_Ref_Stagger_En_WID              ( 1)
+  #define MCMNTS_CR_MC_REFRESH_STAGGER_Ref_Stagger_En_MSK              (0x00000800)
+  #define MCMNTS_CR_MC_REFRESH_STAGGER_Ref_Stagger_En_MAX              (0x00000001)
+  #define MCMNTS_CR_MC_REFRESH_STAGGER_Ref_Stagger_En_DEF              (0x00000000)
+  #define MCMNTS_CR_MC_REFRESH_STAGGER_Ref_Stagger_Mode_OFF            (12)
+  #define MCMNTS_CR_MC_REFRESH_STAGGER_Ref_Stagger_Mode_WID            ( 1)
+  #define MCMNTS_CR_MC_REFRESH_STAGGER_Ref_Stagger_Mode_MSK            (0x00001000)
+  #define MCMNTS_CR_MC_REFRESH_STAGGER_Ref_Stagger_Mode_MAX            (0x00000001)
+  #define MCMNTS_CR_MC_REFRESH_STAGGER_Ref_Stagger_Mode_DEF            (0x00000000)
+  #define MCMNTS_CR_MC_REFRESH_STAGGER_Disable_Stolen_Refresh_OFF      (13)
+  #define MCMNTS_CR_MC_REFRESH_STAGGER_Disable_Stolen_Refresh_WID      ( 1)
+  #define MCMNTS_CR_MC_REFRESH_STAGGER_Disable_Stolen_Refresh_MSK      (0x00002000)
+  #define MCMNTS_CR_MC_REFRESH_STAGGER_Disable_Stolen_Refresh_MAX      (0x00000001)
+  #define MCMNTS_CR_MC_REFRESH_STAGGER_Disable_Stolen_Refresh_DEF      (0x00000000)
+  #define MCMNTS_CR_MC_REFRESH_STAGGER_En_Ref_Type_Display_OFF         (14)
+  #define MCMNTS_CR_MC_REFRESH_STAGGER_En_Ref_Type_Display_WID         ( 1)
+  #define MCMNTS_CR_MC_REFRESH_STAGGER_En_Ref_Type_Display_MSK         (0x00004000)
+  #define MCMNTS_CR_MC_REFRESH_STAGGER_En_Ref_Type_Display_MAX         (0x00000001)
+  #define MCMNTS_CR_MC_REFRESH_STAGGER_En_Ref_Type_Display_DEF         (0x00000000)
+
+#define MCMNTS_CR_TC_ZQCAL_REG                                       (0x00004E90)
+  #define MCMNTS_CR_TC_ZQCAL_ZQCS_period_OFF                           ( 0)
+  #define MCMNTS_CR_TC_ZQCAL_ZQCS_period_WID                           ( 8)
+  #define MCMNTS_CR_TC_ZQCAL_ZQCS_period_MSK                           (0x000000FF)
+  #define MCMNTS_CR_TC_ZQCAL_ZQCS_period_MAX                           (0x000000FF)
+  #define MCMNTS_CR_TC_ZQCAL_ZQCS_period_DEF                           (0x00000080)
+  #define MCMNTS_CR_TC_ZQCAL_tZQCS_OFF                                 ( 8)
+  #define MCMNTS_CR_TC_ZQCAL_tZQCS_WID                                 ( 8)
+  #define MCMNTS_CR_TC_ZQCAL_tZQCS_MSK                                 (0x0000FF00)
+  #define MCMNTS_CR_TC_ZQCAL_tZQCS_MAX                                 (0x000000FF)
+  #define MCMNTS_CR_TC_ZQCAL_tZQCS_DEF                                 (0x00000040)
+  #define MCMNTS_CR_TC_ZQCAL_ZQCS_period_Ult_OFF                       ( 0)
+  #define MCMNTS_CR_TC_ZQCAL_ZQCS_period_Ult_WID                       (10)
+  #define MCMNTS_CR_TC_ZQCAL_ZQCS_period_Ult_MSK                       (0x000003FF)
+  #define MCMNTS_CR_TC_ZQCAL_ZQCS_period_Ult_MAX                       (0x000003FF)
+  #define MCMNTS_CR_TC_ZQCAL_ZQCS_period_Ult_DEF                       (0x00000080)
+  #define MCMNTS_CR_TC_ZQCAL_tZQCS_Ult_OFF                             (10)
+  #define MCMNTS_CR_TC_ZQCAL_tZQCS_Ult_WID                             (10)
+  #define MCMNTS_CR_TC_ZQCAL_tZQCS_Ult_MSK                             (0x000FFC00)
+  #define MCMNTS_CR_TC_ZQCAL_tZQCS_Ult_MAX                             (0x000003FF)
+  #define MCMNTS_CR_TC_ZQCAL_tZQCS_Ult_DEF                             (0x00000040)
+
+#define MCMNTS_CR_TC_RFP_REG                                         (0x00004E94)
+  #define MCMNTS_CR_TC_RFP_OREF_RI_OFF                                 ( 0)
+  #define MCMNTS_CR_TC_RFP_OREF_RI_WID                                 ( 8)
+  #define MCMNTS_CR_TC_RFP_OREF_RI_MSK                                 (0x000000FF)
+  #define MCMNTS_CR_TC_RFP_OREF_RI_MAX                                 (0x000000FF)
+  #define MCMNTS_CR_TC_RFP_OREF_RI_DEF                                 (0x0000000F)
+  #define MCMNTS_CR_TC_RFP_Refresh_HP_WM_OFF                           ( 8)
+  #define MCMNTS_CR_TC_RFP_Refresh_HP_WM_WID                           ( 4)
+  #define MCMNTS_CR_TC_RFP_Refresh_HP_WM_MSK                           (0x00000F00)
+  #define MCMNTS_CR_TC_RFP_Refresh_HP_WM_MAX                           (0x0000000F)
+  #define MCMNTS_CR_TC_RFP_Refresh_HP_WM_DEF                           (0x00000008)
+  #define MCMNTS_CR_TC_RFP_Refresh_panic_wm_OFF                        (12)
+  #define MCMNTS_CR_TC_RFP_Refresh_panic_wm_WID                        ( 4)
+  #define MCMNTS_CR_TC_RFP_Refresh_panic_wm_MSK                        (0x0000F000)
+  #define MCMNTS_CR_TC_RFP_Refresh_panic_wm_MAX                        (0x0000000F)
+  #define MCMNTS_CR_TC_RFP_Refresh_panic_wm_DEF                        (0x00000009)
+
+#define MCMNTS_CR_TC_RFTP_REG                                        (0x00004E98)
+  #define MCMNTS_CR_TC_RFTP_tREFI_OFF                                  ( 0)
+  #define MCMNTS_CR_TC_RFTP_tREFI_WID                                  (16)
+  #define MCMNTS_CR_TC_RFTP_tREFI_MSK                                  (0x0000FFFF)
+  #define MCMNTS_CR_TC_RFTP_tREFI_MAX                                  (0x0000FFFF)
+  #define MCMNTS_CR_TC_RFTP_tREFI_DEF                                  (0x00001004)
+  #define MCMNTS_CR_TC_RFTP_tRFC_OFF                                   (16)
+  #define MCMNTS_CR_TC_RFTP_tRFC_WID                                   ( 9)
+  #define MCMNTS_CR_TC_RFTP_tRFC_MSK                                   (0x01FF0000)
+  #define MCMNTS_CR_TC_RFTP_tRFC_MAX                                   (0x000001FF)
+  #define MCMNTS_CR_TC_RFTP_tRFC_DEF                                   (0x000000B4)
+  #define MCMNTS_CR_TC_RFTP_tREFIx9_OFF                                (25)
+  #define MCMNTS_CR_TC_RFTP_tREFIx9_WID                                ( 7)
+  #define MCMNTS_CR_TC_RFTP_tREFIx9_MSK                                (0xFE000000)
+  #define MCMNTS_CR_TC_RFTP_tREFIx9_MAX                                (0x0000007F)
+  #define MCMNTS_CR_TC_RFTP_tREFIx9_DEF                                (0x00000023)
+
+#define MCMNTS_CR_TC_MR2_SHADDOW_REG                                 (0x00004E9C)
+  #define MCMNTS_CR_TC_MR2_SHADDOW_MR2_sh_low_OFF                      ( 0)
+  #define MCMNTS_CR_TC_MR2_SHADDOW_MR2_sh_low_WID                      ( 6)
+  #define MCMNTS_CR_TC_MR2_SHADDOW_MR2_sh_low_MSK                      (0x0000003F)
+  #define MCMNTS_CR_TC_MR2_SHADDOW_MR2_sh_low_MAX                      (0x0000003F)
+  #define MCMNTS_CR_TC_MR2_SHADDOW_MR2_sh_low_DEF                      (0x00000000)
+  #define MCMNTS_CR_TC_MR2_SHADDOW_SRT_avail_OFF                       ( 6)
+  #define MCMNTS_CR_TC_MR2_SHADDOW_SRT_avail_WID                       ( 2)
+  #define MCMNTS_CR_TC_MR2_SHADDOW_SRT_avail_MSK                       (0x000000C0)
+  #define MCMNTS_CR_TC_MR2_SHADDOW_SRT_avail_MAX                       (0x00000003)
+  #define MCMNTS_CR_TC_MR2_SHADDOW_SRT_avail_DEF                       (0x00000000)
+  #define MCMNTS_CR_TC_MR2_SHADDOW_MR2_sh_high_OFF                     ( 8)
+  #define MCMNTS_CR_TC_MR2_SHADDOW_MR2_sh_high_WID                     ( 3)
+  #define MCMNTS_CR_TC_MR2_SHADDOW_MR2_sh_high_MSK                     (0x00000700)
+  #define MCMNTS_CR_TC_MR2_SHADDOW_MR2_sh_high_MAX                     (0x00000007)
+  #define MCMNTS_CR_TC_MR2_SHADDOW_MR2_sh_high_DEF                     (0x00000000)
+  #define MCMNTS_CR_TC_MR2_SHADDOW_Addr_bit_swizzle_OFF                (14)
+  #define MCMNTS_CR_TC_MR2_SHADDOW_Addr_bit_swizzle_WID                ( 2)
+  #define MCMNTS_CR_TC_MR2_SHADDOW_Addr_bit_swizzle_MSK                (0x0000C000)
+  #define MCMNTS_CR_TC_MR2_SHADDOW_Addr_bit_swizzle_MAX                (0x00000003)
+  #define MCMNTS_CR_TC_MR2_SHADDOW_Addr_bit_swizzle_DEF                (0x00000000)
+
+#define MCMNTS_CR_MC_INIT_STATE_REG                                  (0x00004EA0)
+  #define MCMNTS_CR_MC_INIT_STATE_Rank_occupancy_OFF                   ( 0)
+  #define MCMNTS_CR_MC_INIT_STATE_Rank_occupancy_WID                   ( 4)
+  #define MCMNTS_CR_MC_INIT_STATE_Rank_occupancy_MSK                   (0x0000000F)
+  #define MCMNTS_CR_MC_INIT_STATE_Rank_occupancy_MAX                   (0x0000000F)
+  #define MCMNTS_CR_MC_INIT_STATE_Rank_occupancy_DEF                   (0x0000000F)
+
+#define MCMNTS_CR_TC_SRFTP_REG                                       (0x00004EA4)
+  #define MCMNTS_CR_TC_SRFTP_tXSDLL_OFF                                ( 0)
+  #define MCMNTS_CR_TC_SRFTP_tXSDLL_WID                                (12)
+  #define MCMNTS_CR_TC_SRFTP_tXSDLL_MSK                                (0x00000FFF)
+  #define MCMNTS_CR_TC_SRFTP_tXSDLL_MAX                                (0x00000FFF)
+  #define MCMNTS_CR_TC_SRFTP_tXSDLL_DEF                                (0x00000200)
+  #define MCMNTS_CR_TC_SRFTP_tXS_offset_OFF                            (12)
+  #define MCMNTS_CR_TC_SRFTP_tXS_offset_WID                            ( 4)
+  #define MCMNTS_CR_TC_SRFTP_tXS_offset_MSK                            (0x0000F000)
+  #define MCMNTS_CR_TC_SRFTP_tXS_offset_MAX                            (0x0000000F)
+  #define MCMNTS_CR_TC_SRFTP_tXS_offset_DEF                            (0x0000000B)
+  #define MCMNTS_CR_TC_SRFTP_tZQOPER_OFF                               (16)
+  #define MCMNTS_CR_TC_SRFTP_tZQOPER_WID                               (10)
+  #define MCMNTS_CR_TC_SRFTP_tZQOPER_MSK                               (0x03FF0000)
+  #define MCMNTS_CR_TC_SRFTP_tZQOPER_MAX                               (0x000003FF)
+  #define MCMNTS_CR_TC_SRFTP_tZQOPER_DEF                               (0x00000100)
+  #define MCMNTS_CR_TC_SRFTP_tMOD_OFF                                  (28)
+  #define MCMNTS_CR_TC_SRFTP_tMOD_WID                                  ( 4)
+  #define MCMNTS_CR_TC_SRFTP_tMOD_MSK                                  (0xF0000000)
+  #define MCMNTS_CR_TC_SRFTP_tMOD_MAX                                  (0x0000000F)
+  #define MCMNTS_CR_TC_SRFTP_tMOD_DEF                                  (0x00000000)
+
+#define MCMNTS_CR_WDB_VISA_SEL_REG                                   (0x00004EA8)
+  #define MCMNTS_CR_WDB_VISA_SEL_VISAByteSel_OFF                       ( 0)
+  #define MCMNTS_CR_WDB_VISA_SEL_VISAByteSel_WID                       ( 3)
+  #define MCMNTS_CR_WDB_VISA_SEL_VISAByteSel_MSK                       (0x00000007)
+  #define MCMNTS_CR_WDB_VISA_SEL_VISAByteSel_MAX                       (0x00000007)
+  #define MCMNTS_CR_WDB_VISA_SEL_VISAByteSel_DEF                       (0x00000000)
+
+#define MCMNTS_CR_DCLK_LDAT_PDAT_REG                                 (0x00004EC0)
+  #define MCMNTS_CR_DCLK_LDAT_PDAT_FASTADDR_OFF                        ( 0)
+  #define MCMNTS_CR_DCLK_LDAT_PDAT_FASTADDR_WID                        (12)
+  #define MCMNTS_CR_DCLK_LDAT_PDAT_FASTADDR_MSK                        (0x00000FFF)
+  #define MCMNTS_CR_DCLK_LDAT_PDAT_FASTADDR_MAX                        (0x00000FFF)
+  #define MCMNTS_CR_DCLK_LDAT_PDAT_FASTADDR_DEF                        (0x00000000)
+  #define MCMNTS_CR_DCLK_LDAT_PDAT_ADDREN_OFF                          (16)
+  #define MCMNTS_CR_DCLK_LDAT_PDAT_ADDREN_WID                          ( 1)
+  #define MCMNTS_CR_DCLK_LDAT_PDAT_ADDREN_MSK                          (0x00010000)
+  #define MCMNTS_CR_DCLK_LDAT_PDAT_ADDREN_MAX                          (0x00000001)
+  #define MCMNTS_CR_DCLK_LDAT_PDAT_ADDREN_DEF                          (0x00000000)
+  #define MCMNTS_CR_DCLK_LDAT_PDAT_SEQEN_OFF                           (17)
+  #define MCMNTS_CR_DCLK_LDAT_PDAT_SEQEN_WID                           ( 1)
+  #define MCMNTS_CR_DCLK_LDAT_PDAT_SEQEN_MSK                           (0x00020000)
+  #define MCMNTS_CR_DCLK_LDAT_PDAT_SEQEN_MAX                           (0x00000001)
+  #define MCMNTS_CR_DCLK_LDAT_PDAT_SEQEN_DEF                           (0x00000000)
+  #define MCMNTS_CR_DCLK_LDAT_PDAT_POL0_OFF                            (18)
+  #define MCMNTS_CR_DCLK_LDAT_PDAT_POL0_WID                            ( 1)
+  #define MCMNTS_CR_DCLK_LDAT_PDAT_POL0_MSK                            (0x00040000)
+  #define MCMNTS_CR_DCLK_LDAT_PDAT_POL0_MAX                            (0x00000001)
+  #define MCMNTS_CR_DCLK_LDAT_PDAT_POL0_DEF                            (0x00000000)
+  #define MCMNTS_CR_DCLK_LDAT_PDAT_POL1_OFF                            (19)
+  #define MCMNTS_CR_DCLK_LDAT_PDAT_POL1_WID                            ( 1)
+  #define MCMNTS_CR_DCLK_LDAT_PDAT_POL1_MSK                            (0x00080000)
+  #define MCMNTS_CR_DCLK_LDAT_PDAT_POL1_MAX                            (0x00000001)
+  #define MCMNTS_CR_DCLK_LDAT_PDAT_POL1_DEF                            (0x00000000)
+  #define MCMNTS_CR_DCLK_LDAT_PDAT_CMDA_OFF                            (20)
+  #define MCMNTS_CR_DCLK_LDAT_PDAT_CMDA_WID                            ( 4)
+  #define MCMNTS_CR_DCLK_LDAT_PDAT_CMDA_MSK                            (0x00F00000)
+  #define MCMNTS_CR_DCLK_LDAT_PDAT_CMDA_MAX                            (0x0000000F)
+  #define MCMNTS_CR_DCLK_LDAT_PDAT_CMDA_DEF                            (0x00000000)
+  #define MCMNTS_CR_DCLK_LDAT_PDAT_CMDB_OFF                            (24)
+  #define MCMNTS_CR_DCLK_LDAT_PDAT_CMDB_WID                            ( 4)
+  #define MCMNTS_CR_DCLK_LDAT_PDAT_CMDB_MSK                            (0x0F000000)
+  #define MCMNTS_CR_DCLK_LDAT_PDAT_CMDB_MAX                            (0x0000000F)
+  #define MCMNTS_CR_DCLK_LDAT_PDAT_CMDB_DEF                            (0x00000000)
+  #define MCMNTS_CR_DCLK_LDAT_PDAT_CMDC_OFF                            (28)
+  #define MCMNTS_CR_DCLK_LDAT_PDAT_CMDC_WID                            ( 4)
+  #define MCMNTS_CR_DCLK_LDAT_PDAT_CMDC_MSK                            (0xF0000000)
+  #define MCMNTS_CR_DCLK_LDAT_PDAT_CMDC_MAX                            (0x0000000F)
+  #define MCMNTS_CR_DCLK_LDAT_PDAT_CMDC_DEF                            (0x00000000)
+
+#define MCMNTS_CR_DCLK_LDAT_SDAT_REG                                 (0x00004EC4)
+  #define MCMNTS_CR_DCLK_LDAT_SDAT_BANKSEL_OFF                         ( 0)
+  #define MCMNTS_CR_DCLK_LDAT_SDAT_BANKSEL_WID                         ( 4)
+  #define MCMNTS_CR_DCLK_LDAT_SDAT_BANKSEL_MSK                         (0x0000000F)
+  #define MCMNTS_CR_DCLK_LDAT_SDAT_BANKSEL_MAX                         (0x0000000F)
+  #define MCMNTS_CR_DCLK_LDAT_SDAT_BANKSEL_DEF                         (0x00000000)
+  #define MCMNTS_CR_DCLK_LDAT_SDAT_ARRAYSEL_OFF                        ( 5)
+  #define MCMNTS_CR_DCLK_LDAT_SDAT_ARRAYSEL_WID                        ( 5)
+  #define MCMNTS_CR_DCLK_LDAT_SDAT_ARRAYSEL_MSK                        (0x000003E0)
+  #define MCMNTS_CR_DCLK_LDAT_SDAT_ARRAYSEL_MAX                        (0x0000001F)
+  #define MCMNTS_CR_DCLK_LDAT_SDAT_ARRAYSEL_DEF                        (0x00000000)
+  #define MCMNTS_CR_DCLK_LDAT_SDAT_CMP_OFF                             (10)
+  #define MCMNTS_CR_DCLK_LDAT_SDAT_CMP_WID                             ( 1)
+  #define MCMNTS_CR_DCLK_LDAT_SDAT_CMP_MSK                             (0x00000400)
+  #define MCMNTS_CR_DCLK_LDAT_SDAT_CMP_MAX                             (0x00000001)
+  #define MCMNTS_CR_DCLK_LDAT_SDAT_CMP_DEF                             (0x00000000)
+  #define MCMNTS_CR_DCLK_LDAT_SDAT_REP_OFF                             (11)
+  #define MCMNTS_CR_DCLK_LDAT_SDAT_REP_WID                             ( 1)
+  #define MCMNTS_CR_DCLK_LDAT_SDAT_REP_MSK                             (0x00000800)
+  #define MCMNTS_CR_DCLK_LDAT_SDAT_REP_MAX                             (0x00000001)
+  #define MCMNTS_CR_DCLK_LDAT_SDAT_REP_DEF                             (0x00000000)
+  #define MCMNTS_CR_DCLK_LDAT_SDAT_DWORD_OFF                           (12)
+  #define MCMNTS_CR_DCLK_LDAT_SDAT_DWORD_WID                           ( 4)
+  #define MCMNTS_CR_DCLK_LDAT_SDAT_DWORD_MSK                           (0x0000F000)
+  #define MCMNTS_CR_DCLK_LDAT_SDAT_DWORD_MAX                           (0x0000000F)
+  #define MCMNTS_CR_DCLK_LDAT_SDAT_DWORD_DEF                           (0x00000000)
+  #define MCMNTS_CR_DCLK_LDAT_SDAT_MODE_OFF                            (16)
+  #define MCMNTS_CR_DCLK_LDAT_SDAT_MODE_WID                            ( 2)
+  #define MCMNTS_CR_DCLK_LDAT_SDAT_MODE_MSK                            (0x00030000)
+  #define MCMNTS_CR_DCLK_LDAT_SDAT_MODE_MAX                            (0x00000003)
+  #define MCMNTS_CR_DCLK_LDAT_SDAT_MODE_DEF                            (0x00000000)
+  #define MCMNTS_CR_DCLK_LDAT_SDAT_MPMAP_OFF                           (18)
+  #define MCMNTS_CR_DCLK_LDAT_SDAT_MPMAP_WID                           ( 6)
+  #define MCMNTS_CR_DCLK_LDAT_SDAT_MPMAP_MSK                           (0x00FC0000)
+  #define MCMNTS_CR_DCLK_LDAT_SDAT_MPMAP_MAX                           (0x0000003F)
+  #define MCMNTS_CR_DCLK_LDAT_SDAT_MPMAP_DEF                           (0x00000000)
+  #define MCMNTS_CR_DCLK_LDAT_SDAT_MPBOFFSET_OFF                       (24)
+  #define MCMNTS_CR_DCLK_LDAT_SDAT_MPBOFFSET_WID                       ( 4)
+  #define MCMNTS_CR_DCLK_LDAT_SDAT_MPBOFFSET_MSK                       (0x0F000000)
+  #define MCMNTS_CR_DCLK_LDAT_SDAT_MPBOFFSET_MAX                       (0x0000000F)
+  #define MCMNTS_CR_DCLK_LDAT_SDAT_MPBOFFSET_DEF                       (0x00000000)
+  #define MCMNTS_CR_DCLK_LDAT_SDAT_STAGE_EN_OFF                        (28)
+  #define MCMNTS_CR_DCLK_LDAT_SDAT_STAGE_EN_WID                        ( 1)
+  #define MCMNTS_CR_DCLK_LDAT_SDAT_STAGE_EN_MSK                        (0x10000000)
+  #define MCMNTS_CR_DCLK_LDAT_SDAT_STAGE_EN_MAX                        (0x00000001)
+  #define MCMNTS_CR_DCLK_LDAT_SDAT_STAGE_EN_DEF                        (0x00000000)
+  #define MCMNTS_CR_DCLK_LDAT_SDAT_SHADOW_OFF                          (29)
+  #define MCMNTS_CR_DCLK_LDAT_SDAT_SHADOW_WID                          ( 2)
+  #define MCMNTS_CR_DCLK_LDAT_SDAT_SHADOW_MSK                          (0x60000000)
+  #define MCMNTS_CR_DCLK_LDAT_SDAT_SHADOW_MAX                          (0x00000003)
+  #define MCMNTS_CR_DCLK_LDAT_SDAT_SHADOW_DEF                          (0x00000000)
+
+#define MCMNTS_CR_DCLK_LDAT_DATAOUT_REG                              (0x00004EC8)
+  #define MCMNTS_CR_DCLK_LDAT_DATAOUT_DATOUT_OFF                       ( 0)
+  #define MCMNTS_CR_DCLK_LDAT_DATAOUT_DATOUT_WID                       (32)
+  #define MCMNTS_CR_DCLK_LDAT_DATAOUT_DATOUT_MSK                       (0xFFFFFFFF)
+  #define MCMNTS_CR_DCLK_LDAT_DATAOUT_DATOUT_MAX                       (0xFFFFFFFF)
+  #define MCMNTS_CR_DCLK_LDAT_DATAOUT_DATOUT_DEF                       (0x00000000)
+
+#define MCMNTS_CR_DCLK_LDAT_DATAIN_0_REG                             (0x00004ECC)
+  #define MCMNTS_CR_DCLK_LDAT_DATAIN_0_DATIN_OFF                       ( 0)
+  #define MCMNTS_CR_DCLK_LDAT_DATAIN_0_DATIN_WID                       (32)
+  #define MCMNTS_CR_DCLK_LDAT_DATAIN_0_DATIN_MSK                       (0xFFFFFFFF)
+  #define MCMNTS_CR_DCLK_LDAT_DATAIN_0_DATIN_MAX                       (0xFFFFFFFF)
+  #define MCMNTS_CR_DCLK_LDAT_DATAIN_0_DATIN_DEF                       (0x00000000)
+
+#define MCMNTS_CR_QCLK_LDAT_PDAT_REG                                 (0x00004ED0)
+  #define MCMNTS_CR_QCLK_LDAT_PDAT_FASTADDR_OFF                        ( 0)
+  #define MCMNTS_CR_QCLK_LDAT_PDAT_FASTADDR_WID                        (12)
+  #define MCMNTS_CR_QCLK_LDAT_PDAT_FASTADDR_MSK                        (0x00000FFF)
+  #define MCMNTS_CR_QCLK_LDAT_PDAT_FASTADDR_MAX                        (0x00000FFF)
+  #define MCMNTS_CR_QCLK_LDAT_PDAT_FASTADDR_DEF                        (0x00000000)
+  #define MCMNTS_CR_QCLK_LDAT_PDAT_ADDREN_OFF                          (16)
+  #define MCMNTS_CR_QCLK_LDAT_PDAT_ADDREN_WID                          ( 1)
+  #define MCMNTS_CR_QCLK_LDAT_PDAT_ADDREN_MSK                          (0x00010000)
+  #define MCMNTS_CR_QCLK_LDAT_PDAT_ADDREN_MAX                          (0x00000001)
+  #define MCMNTS_CR_QCLK_LDAT_PDAT_ADDREN_DEF                          (0x00000000)
+  #define MCMNTS_CR_QCLK_LDAT_PDAT_SEQEN_OFF                           (17)
+  #define MCMNTS_CR_QCLK_LDAT_PDAT_SEQEN_WID                           ( 1)
+  #define MCMNTS_CR_QCLK_LDAT_PDAT_SEQEN_MSK                           (0x00020000)
+  #define MCMNTS_CR_QCLK_LDAT_PDAT_SEQEN_MAX                           (0x00000001)
+  #define MCMNTS_CR_QCLK_LDAT_PDAT_SEQEN_DEF                           (0x00000000)
+  #define MCMNTS_CR_QCLK_LDAT_PDAT_POL0_OFF                            (18)
+  #define MCMNTS_CR_QCLK_LDAT_PDAT_POL0_WID                            ( 1)
+  #define MCMNTS_CR_QCLK_LDAT_PDAT_POL0_MSK                            (0x00040000)
+  #define MCMNTS_CR_QCLK_LDAT_PDAT_POL0_MAX                            (0x00000001)
+  #define MCMNTS_CR_QCLK_LDAT_PDAT_POL0_DEF                            (0x00000000)
+  #define MCMNTS_CR_QCLK_LDAT_PDAT_POL1_OFF                            (19)
+  #define MCMNTS_CR_QCLK_LDAT_PDAT_POL1_WID                            ( 1)
+  #define MCMNTS_CR_QCLK_LDAT_PDAT_POL1_MSK                            (0x00080000)
+  #define MCMNTS_CR_QCLK_LDAT_PDAT_POL1_MAX                            (0x00000001)
+  #define MCMNTS_CR_QCLK_LDAT_PDAT_POL1_DEF                            (0x00000000)
+  #define MCMNTS_CR_QCLK_LDAT_PDAT_CMDA_OFF                            (20)
+  #define MCMNTS_CR_QCLK_LDAT_PDAT_CMDA_WID                            ( 4)
+  #define MCMNTS_CR_QCLK_LDAT_PDAT_CMDA_MSK                            (0x00F00000)
+  #define MCMNTS_CR_QCLK_LDAT_PDAT_CMDA_MAX                            (0x0000000F)
+  #define MCMNTS_CR_QCLK_LDAT_PDAT_CMDA_DEF                            (0x00000000)
+  #define MCMNTS_CR_QCLK_LDAT_PDAT_CMDB_OFF                            (24)
+  #define MCMNTS_CR_QCLK_LDAT_PDAT_CMDB_WID                            ( 4)
+  #define MCMNTS_CR_QCLK_LDAT_PDAT_CMDB_MSK                            (0x0F000000)
+  #define MCMNTS_CR_QCLK_LDAT_PDAT_CMDB_MAX                            (0x0000000F)
+  #define MCMNTS_CR_QCLK_LDAT_PDAT_CMDB_DEF                            (0x00000000)
+  #define MCMNTS_CR_QCLK_LDAT_PDAT_CMDC_OFF                            (28)
+  #define MCMNTS_CR_QCLK_LDAT_PDAT_CMDC_WID                            ( 4)
+  #define MCMNTS_CR_QCLK_LDAT_PDAT_CMDC_MSK                            (0xF0000000)
+  #define MCMNTS_CR_QCLK_LDAT_PDAT_CMDC_MAX                            (0x0000000F)
+  #define MCMNTS_CR_QCLK_LDAT_PDAT_CMDC_DEF                            (0x00000000)
+
+#define MCMNTS_CR_QCLK_LDAT_SDAT_REG                                 (0x00004ED4)
+  #define MCMNTS_CR_QCLK_LDAT_SDAT_BANKSEL_OFF                         ( 0)
+  #define MCMNTS_CR_QCLK_LDAT_SDAT_BANKSEL_WID                         ( 4)
+  #define MCMNTS_CR_QCLK_LDAT_SDAT_BANKSEL_MSK                         (0x0000000F)
+  #define MCMNTS_CR_QCLK_LDAT_SDAT_BANKSEL_MAX                         (0x0000000F)
+  #define MCMNTS_CR_QCLK_LDAT_SDAT_BANKSEL_DEF                         (0x00000000)
+  #define MCMNTS_CR_QCLK_LDAT_SDAT_ARRAYSEL_OFF                        ( 5)
+  #define MCMNTS_CR_QCLK_LDAT_SDAT_ARRAYSEL_WID                        ( 5)
+  #define MCMNTS_CR_QCLK_LDAT_SDAT_ARRAYSEL_MSK                        (0x000003E0)
+  #define MCMNTS_CR_QCLK_LDAT_SDAT_ARRAYSEL_MAX                        (0x0000001F)
+  #define MCMNTS_CR_QCLK_LDAT_SDAT_ARRAYSEL_DEF                        (0x00000000)
+  #define MCMNTS_CR_QCLK_LDAT_SDAT_CMP_OFF                             (10)
+  #define MCMNTS_CR_QCLK_LDAT_SDAT_CMP_WID                             ( 1)
+  #define MCMNTS_CR_QCLK_LDAT_SDAT_CMP_MSK                             (0x00000400)
+  #define MCMNTS_CR_QCLK_LDAT_SDAT_CMP_MAX                             (0x00000001)
+  #define MCMNTS_CR_QCLK_LDAT_SDAT_CMP_DEF                             (0x00000000)
+  #define MCMNTS_CR_QCLK_LDAT_SDAT_REP_OFF                             (11)
+  #define MCMNTS_CR_QCLK_LDAT_SDAT_REP_WID                             ( 1)
+  #define MCMNTS_CR_QCLK_LDAT_SDAT_REP_MSK                             (0x00000800)
+  #define MCMNTS_CR_QCLK_LDAT_SDAT_REP_MAX                             (0x00000001)
+  #define MCMNTS_CR_QCLK_LDAT_SDAT_REP_DEF                             (0x00000000)
+  #define MCMNTS_CR_QCLK_LDAT_SDAT_DWORD_OFF                           (12)
+  #define MCMNTS_CR_QCLK_LDAT_SDAT_DWORD_WID                           ( 4)
+  #define MCMNTS_CR_QCLK_LDAT_SDAT_DWORD_MSK                           (0x0000F000)
+  #define MCMNTS_CR_QCLK_LDAT_SDAT_DWORD_MAX                           (0x0000000F)
+  #define MCMNTS_CR_QCLK_LDAT_SDAT_DWORD_DEF                           (0x00000000)
+  #define MCMNTS_CR_QCLK_LDAT_SDAT_MODE_OFF                            (16)
+  #define MCMNTS_CR_QCLK_LDAT_SDAT_MODE_WID                            ( 2)
+  #define MCMNTS_CR_QCLK_LDAT_SDAT_MODE_MSK                            (0x00030000)
+  #define MCMNTS_CR_QCLK_LDAT_SDAT_MODE_MAX                            (0x00000003)
+  #define MCMNTS_CR_QCLK_LDAT_SDAT_MODE_DEF                            (0x00000000)
+  #define MCMNTS_CR_QCLK_LDAT_SDAT_MPMAP_OFF                           (18)
+  #define MCMNTS_CR_QCLK_LDAT_SDAT_MPMAP_WID                           ( 6)
+  #define MCMNTS_CR_QCLK_LDAT_SDAT_MPMAP_MSK                           (0x00FC0000)
+  #define MCMNTS_CR_QCLK_LDAT_SDAT_MPMAP_MAX                           (0x0000003F)
+  #define MCMNTS_CR_QCLK_LDAT_SDAT_MPMAP_DEF                           (0x00000000)
+  #define MCMNTS_CR_QCLK_LDAT_SDAT_MPBOFFSET_OFF                       (24)
+  #define MCMNTS_CR_QCLK_LDAT_SDAT_MPBOFFSET_WID                       ( 4)
+  #define MCMNTS_CR_QCLK_LDAT_SDAT_MPBOFFSET_MSK                       (0x0F000000)
+  #define MCMNTS_CR_QCLK_LDAT_SDAT_MPBOFFSET_MAX                       (0x0000000F)
+  #define MCMNTS_CR_QCLK_LDAT_SDAT_MPBOFFSET_DEF                       (0x00000000)
+  #define MCMNTS_CR_QCLK_LDAT_SDAT_STAGE_EN_OFF                        (28)
+  #define MCMNTS_CR_QCLK_LDAT_SDAT_STAGE_EN_WID                        ( 1)
+  #define MCMNTS_CR_QCLK_LDAT_SDAT_STAGE_EN_MSK                        (0x10000000)
+  #define MCMNTS_CR_QCLK_LDAT_SDAT_STAGE_EN_MAX                        (0x00000001)
+  #define MCMNTS_CR_QCLK_LDAT_SDAT_STAGE_EN_DEF                        (0x00000000)
+  #define MCMNTS_CR_QCLK_LDAT_SDAT_SHADOW_OFF                          (29)
+  #define MCMNTS_CR_QCLK_LDAT_SDAT_SHADOW_WID                          ( 2)
+  #define MCMNTS_CR_QCLK_LDAT_SDAT_SHADOW_MSK                          (0x60000000)
+  #define MCMNTS_CR_QCLK_LDAT_SDAT_SHADOW_MAX                          (0x00000003)
+  #define MCMNTS_CR_QCLK_LDAT_SDAT_SHADOW_DEF                          (0x00000000)
+
+#define MCMNTS_CR_QCLK_LDAT_DATAOUT_REG                              (0x00004ED8)
+  #define MCMNTS_CR_QCLK_LDAT_DATAOUT_DATOUT_OFF                       ( 0)
+  #define MCMNTS_CR_QCLK_LDAT_DATAOUT_DATOUT_WID                       (32)
+  #define MCMNTS_CR_QCLK_LDAT_DATAOUT_DATOUT_MSK                       (0xFFFFFFFF)
+  #define MCMNTS_CR_QCLK_LDAT_DATAOUT_DATOUT_MAX                       (0xFFFFFFFF)
+  #define MCMNTS_CR_QCLK_LDAT_DATAOUT_DATOUT_DEF                       (0x00000000)
+
+#define MCMNTS_CR_QCLK_LDAT_DATAIN_0_REG                             (0x00004EDC)
+  #define MCMNTS_CR_QCLK_LDAT_DATAIN_0_DATIN_OFF                       ( 0)
+  #define MCMNTS_CR_QCLK_LDAT_DATAIN_0_DATIN_WID                       (32)
+  #define MCMNTS_CR_QCLK_LDAT_DATAIN_0_DATIN_MSK                       (0xFFFFFFFF)
+  #define MCMNTS_CR_QCLK_LDAT_DATAIN_0_DATIN_MAX                       (0xFFFFFFFF)
+  #define MCMNTS_CR_QCLK_LDAT_DATAIN_0_DATIN_DEF                       (0x00000000)
+
+#define MCMNTS_CR_QCLK_LDAT_DATAIN_1_REG                             (0x00004EE0)
+  #define MCMNTS_CR_QCLK_LDAT_DATAIN_1_DATIN_OFF                       ( 0)
+  #define MCMNTS_CR_QCLK_LDAT_DATAIN_1_DATIN_WID                       (32)
+  #define MCMNTS_CR_QCLK_LDAT_DATAIN_1_DATIN_MSK                       (0xFFFFFFFF)
+  #define MCMNTS_CR_QCLK_LDAT_DATAIN_1_DATIN_MAX                       (0xFFFFFFFF)
+  #define MCMNTS_CR_QCLK_LDAT_DATAIN_1_DATIN_DEF                       (0x00000000)
+
+#define MCMNTS_CR_QUEUE_ENTRY_DISABLE_RPQ_REG                        (0x00004EE4)
+  #define MCMNTS_CR_QUEUE_ENTRY_DISABLE_RPQ_RPQ_disable_OFF            ( 0)
+  #define MCMNTS_CR_QUEUE_ENTRY_DISABLE_RPQ_RPQ_disable_WID            (28)
+  #define MCMNTS_CR_QUEUE_ENTRY_DISABLE_RPQ_RPQ_disable_MSK            (0x0FFFFFFF)
+  #define MCMNTS_CR_QUEUE_ENTRY_DISABLE_RPQ_RPQ_disable_MAX            (0x0FFFFFFF)
+  #define MCMNTS_CR_QUEUE_ENTRY_DISABLE_RPQ_RPQ_disable_DEF            (0x00000000)
+
+#define MCMNTS_CR_QUEUE_ENTRY_DISABLE_WPQ_REG                        (0x00004EE8)
+  #define MCMNTS_CR_QUEUE_ENTRY_DISABLE_WPQ_WPQ_disable_OFF            ( 0)
+  #define MCMNTS_CR_QUEUE_ENTRY_DISABLE_WPQ_WPQ_disable_WID            (32)
+  #define MCMNTS_CR_QUEUE_ENTRY_DISABLE_WPQ_WPQ_disable_MSK            (0xFFFFFFFF)
+  #define MCMNTS_CR_QUEUE_ENTRY_DISABLE_WPQ_WPQ_disable_MAX            (0xFFFFFFFF)
+  #define MCMNTS_CR_QUEUE_ENTRY_DISABLE_WPQ_WPQ_disable_DEF            (0x00000000)
+
+#define MCMNTS_CR_PM_DIMM_IDLE_ENERGY_REG                            (0x00004EEC)
+  #define MCMNTS_CR_PM_DIMM_IDLE_ENERGY_DIMM0_IDLE_ENERGY_OFF          ( 0)
+  #define MCMNTS_CR_PM_DIMM_IDLE_ENERGY_DIMM0_IDLE_ENERGY_WID          ( 6)
+  #define MCMNTS_CR_PM_DIMM_IDLE_ENERGY_DIMM0_IDLE_ENERGY_MSK          (0x0000003F)
+  #define MCMNTS_CR_PM_DIMM_IDLE_ENERGY_DIMM0_IDLE_ENERGY_MAX          (0x0000003F)
+  #define MCMNTS_CR_PM_DIMM_IDLE_ENERGY_DIMM0_IDLE_ENERGY_DEF          (0x00000000)
+  #define MCMNTS_CR_PM_DIMM_IDLE_ENERGY_DIMM1_IDLE_ENERGY_OFF          ( 8)
+  #define MCMNTS_CR_PM_DIMM_IDLE_ENERGY_DIMM1_IDLE_ENERGY_WID          ( 6)
+  #define MCMNTS_CR_PM_DIMM_IDLE_ENERGY_DIMM1_IDLE_ENERGY_MSK          (0x00003F00)
+  #define MCMNTS_CR_PM_DIMM_IDLE_ENERGY_DIMM1_IDLE_ENERGY_MAX          (0x0000003F)
+  #define MCMNTS_CR_PM_DIMM_IDLE_ENERGY_DIMM1_IDLE_ENERGY_DEF          (0x00000000)
+
+#define MCMNTS_CR_PM_DIMM_PD_ENERGY_REG                              (0x00004EF0)
+  #define MCMNTS_CR_PM_DIMM_PD_ENERGY_DIMM0_PD_ENERGY_OFF              ( 0)
+  #define MCMNTS_CR_PM_DIMM_PD_ENERGY_DIMM0_PD_ENERGY_WID              ( 6)
+  #define MCMNTS_CR_PM_DIMM_PD_ENERGY_DIMM0_PD_ENERGY_MSK              (0x0000003F)
+  #define MCMNTS_CR_PM_DIMM_PD_ENERGY_DIMM0_PD_ENERGY_MAX              (0x0000003F)
+  #define MCMNTS_CR_PM_DIMM_PD_ENERGY_DIMM0_PD_ENERGY_DEF              (0x00000000)
+  #define MCMNTS_CR_PM_DIMM_PD_ENERGY_DIMM1_PD_ENERGY_OFF              ( 8)
+  #define MCMNTS_CR_PM_DIMM_PD_ENERGY_DIMM1_PD_ENERGY_WID              ( 6)
+  #define MCMNTS_CR_PM_DIMM_PD_ENERGY_DIMM1_PD_ENERGY_MSK              (0x00003F00)
+  #define MCMNTS_CR_PM_DIMM_PD_ENERGY_DIMM1_PD_ENERGY_MAX              (0x0000003F)
+  #define MCMNTS_CR_PM_DIMM_PD_ENERGY_DIMM1_PD_ENERGY_DEF              (0x00000000)
+
+#define MCMNTS_CR_PM_DIMM_ACT_ENERGY_REG                             (0x00004EF4)
+  #define MCMNTS_CR_PM_DIMM_ACT_ENERGY_DIMM0_ACT_ENERGY_OFF            ( 0)
+  #define MCMNTS_CR_PM_DIMM_ACT_ENERGY_DIMM0_ACT_ENERGY_WID            ( 8)
+  #define MCMNTS_CR_PM_DIMM_ACT_ENERGY_DIMM0_ACT_ENERGY_MSK            (0x000000FF)
+  #define MCMNTS_CR_PM_DIMM_ACT_ENERGY_DIMM0_ACT_ENERGY_MAX            (0x000000FF)
+  #define MCMNTS_CR_PM_DIMM_ACT_ENERGY_DIMM0_ACT_ENERGY_DEF            (0x00000000)
+  #define MCMNTS_CR_PM_DIMM_ACT_ENERGY_DIMM1_ACT_ENERGY_OFF            ( 8)
+  #define MCMNTS_CR_PM_DIMM_ACT_ENERGY_DIMM1_ACT_ENERGY_WID            ( 8)
+  #define MCMNTS_CR_PM_DIMM_ACT_ENERGY_DIMM1_ACT_ENERGY_MSK            (0x0000FF00)
+  #define MCMNTS_CR_PM_DIMM_ACT_ENERGY_DIMM1_ACT_ENERGY_MAX            (0x000000FF)
+  #define MCMNTS_CR_PM_DIMM_ACT_ENERGY_DIMM1_ACT_ENERGY_DEF            (0x00000000)
+
+#define MCMNTS_CR_PM_DIMM_RD_ENERGY_REG                              (0x00004EF8)
+  #define MCMNTS_CR_PM_DIMM_RD_ENERGY_DIMM0_RD_ENERGY_OFF              ( 0)
+  #define MCMNTS_CR_PM_DIMM_RD_ENERGY_DIMM0_RD_ENERGY_WID              ( 8)
+  #define MCMNTS_CR_PM_DIMM_RD_ENERGY_DIMM0_RD_ENERGY_MSK              (0x000000FF)
+  #define MCMNTS_CR_PM_DIMM_RD_ENERGY_DIMM0_RD_ENERGY_MAX              (0x000000FF)
+  #define MCMNTS_CR_PM_DIMM_RD_ENERGY_DIMM0_RD_ENERGY_DEF              (0x00000000)
+  #define MCMNTS_CR_PM_DIMM_RD_ENERGY_DIMM1_RD_ENERGY_OFF              ( 8)
+  #define MCMNTS_CR_PM_DIMM_RD_ENERGY_DIMM1_RD_ENERGY_WID              ( 8)
+  #define MCMNTS_CR_PM_DIMM_RD_ENERGY_DIMM1_RD_ENERGY_MSK              (0x0000FF00)
+  #define MCMNTS_CR_PM_DIMM_RD_ENERGY_DIMM1_RD_ENERGY_MAX              (0x000000FF)
+  #define MCMNTS_CR_PM_DIMM_RD_ENERGY_DIMM1_RD_ENERGY_DEF              (0x00000000)
+
+#define MCMNTS_CR_PM_DIMM_WR_ENERGY_REG                              (0x00004EFC)
+  #define MCMNTS_CR_PM_DIMM_WR_ENERGY_DIMM0_WR_ENERGY_OFF              ( 0)
+  #define MCMNTS_CR_PM_DIMM_WR_ENERGY_DIMM0_WR_ENERGY_WID              ( 8)
+  #define MCMNTS_CR_PM_DIMM_WR_ENERGY_DIMM0_WR_ENERGY_MSK              (0x000000FF)
+  #define MCMNTS_CR_PM_DIMM_WR_ENERGY_DIMM0_WR_ENERGY_MAX              (0x000000FF)
+  #define MCMNTS_CR_PM_DIMM_WR_ENERGY_DIMM0_WR_ENERGY_DEF              (0x00000000)
+  #define MCMNTS_CR_PM_DIMM_WR_ENERGY_DIMM1_WR_ENERGY_OFF              ( 8)
+  #define MCMNTS_CR_PM_DIMM_WR_ENERGY_DIMM1_WR_ENERGY_WID              ( 8)
+  #define MCMNTS_CR_PM_DIMM_WR_ENERGY_DIMM1_WR_ENERGY_MSK              (0x0000FF00)
+  #define MCMNTS_CR_PM_DIMM_WR_ENERGY_DIMM1_WR_ENERGY_MAX              (0x000000FF)
+  #define MCMNTS_CR_PM_DIMM_WR_ENERGY_DIMM1_WR_ENERGY_DEF              (0x00000000)
+
+#define MCMNTS_CR_PM_THRT_CKE_MIN_REG                                (0x00004F28)
+  #define MCMNTS_CR_PM_THRT_CKE_MIN_CKE_MIN_OFF                        ( 0)
+  #define MCMNTS_CR_PM_THRT_CKE_MIN_CKE_MIN_WID                        ( 8)
+  #define MCMNTS_CR_PM_THRT_CKE_MIN_CKE_MIN_MSK                        (0x000000FF)
+  #define MCMNTS_CR_PM_THRT_CKE_MIN_CKE_MIN_MAX                        (0x000000FF)
+  #define MCMNTS_CR_PM_THRT_CKE_MIN_CKE_MIN_DEF                        (0x00000000)
+  #define MCMNTS_CR_PM_THRT_CKE_MIN_CKE_MIN_DEFEATURE_OFF              ( 8)
+  #define MCMNTS_CR_PM_THRT_CKE_MIN_CKE_MIN_DEFEATURE_WID              ( 1)
+  #define MCMNTS_CR_PM_THRT_CKE_MIN_CKE_MIN_DEFEATURE_MSK              (0x00000100)
+  #define MCMNTS_CR_PM_THRT_CKE_MIN_CKE_MIN_DEFEATURE_MAX              (0x00000001)
+  #define MCMNTS_CR_PM_THRT_CKE_MIN_CKE_MIN_DEFEATURE_DEF              (0x00000000)
+
+#define MCMNTS_CR_ODLAT_CMD_MATCH0_REG                               (0x00004F40)
+  #define MCMNTS_CR_ODLAT_CMD_MATCH0_ODT_OFF                           ( 0)
+  #define MCMNTS_CR_ODLAT_CMD_MATCH0_ODT_WID                           ( 4)
+  #define MCMNTS_CR_ODLAT_CMD_MATCH0_ODT_MSK                           (0x0000000F)
+  #define MCMNTS_CR_ODLAT_CMD_MATCH0_ODT_MAX                           (0x0000000F)
+  #define MCMNTS_CR_ODLAT_CMD_MATCH0_ODT_DEF                           (0x00000000)
+  #define MCMNTS_CR_ODLAT_CMD_MATCH0_Web_OFF                           ( 4)
+  #define MCMNTS_CR_ODLAT_CMD_MATCH0_Web_WID                           ( 1)
+  #define MCMNTS_CR_ODLAT_CMD_MATCH0_Web_MSK                           (0x00000010)
+  #define MCMNTS_CR_ODLAT_CMD_MATCH0_Web_MAX                           (0x00000001)
+  #define MCMNTS_CR_ODLAT_CMD_MATCH0_Web_DEF                           (0x00000000)
+  #define MCMNTS_CR_ODLAT_CMD_MATCH0_CASb_OFF                          ( 5)
+  #define MCMNTS_CR_ODLAT_CMD_MATCH0_CASb_WID                          ( 1)
+  #define MCMNTS_CR_ODLAT_CMD_MATCH0_CASb_MSK                          (0x00000020)
+  #define MCMNTS_CR_ODLAT_CMD_MATCH0_CASb_MAX                          (0x00000001)
+  #define MCMNTS_CR_ODLAT_CMD_MATCH0_CASb_DEF                          (0x00000000)
+  #define MCMNTS_CR_ODLAT_CMD_MATCH0_RASb_OFF                          ( 6)
+  #define MCMNTS_CR_ODLAT_CMD_MATCH0_RASb_WID                          ( 1)
+  #define MCMNTS_CR_ODLAT_CMD_MATCH0_RASb_MSK                          (0x00000040)
+  #define MCMNTS_CR_ODLAT_CMD_MATCH0_RASb_MAX                          (0x00000001)
+  #define MCMNTS_CR_ODLAT_CMD_MATCH0_RASb_DEF                          (0x00000000)
+  #define MCMNTS_CR_ODLAT_CMD_MATCH0_CSb_OFF                           ( 7)
+  #define MCMNTS_CR_ODLAT_CMD_MATCH0_CSb_WID                           ( 4)
+  #define MCMNTS_CR_ODLAT_CMD_MATCH0_CSb_MSK                           (0x00000780)
+  #define MCMNTS_CR_ODLAT_CMD_MATCH0_CSb_MAX                           (0x0000000F)
+  #define MCMNTS_CR_ODLAT_CMD_MATCH0_CSb_DEF                           (0x00000000)
+  #define MCMNTS_CR_ODLAT_CMD_MATCH0_CKE_OFF                           (11)
+  #define MCMNTS_CR_ODLAT_CMD_MATCH0_CKE_WID                           ( 4)
+  #define MCMNTS_CR_ODLAT_CMD_MATCH0_CKE_MSK                           (0x00007800)
+  #define MCMNTS_CR_ODLAT_CMD_MATCH0_CKE_MAX                           (0x0000000F)
+  #define MCMNTS_CR_ODLAT_CMD_MATCH0_CKE_DEF                           (0x00000000)
+  #define MCMNTS_CR_ODLAT_CMD_MATCH0_MA_OFF                            (15)
+  #define MCMNTS_CR_ODLAT_CMD_MATCH0_MA_WID                            (16)
+  #define MCMNTS_CR_ODLAT_CMD_MATCH0_MA_MSK                            (0x7FFF8000)
+  #define MCMNTS_CR_ODLAT_CMD_MATCH0_MA_MAX                            (0x0000FFFF)
+  #define MCMNTS_CR_ODLAT_CMD_MATCH0_MA_DEF                            (0x00000000)
+
+#define MCMNTS_CR_ODLAT_CMD_MATCH1_REG                               (0x00004F44)
+  #define MCMNTS_CR_ODLAT_CMD_MATCH1_ODT_OFF                           ( 0)
+  #define MCMNTS_CR_ODLAT_CMD_MATCH1_ODT_WID                           ( 4)
+  #define MCMNTS_CR_ODLAT_CMD_MATCH1_ODT_MSK                           (0x0000000F)
+  #define MCMNTS_CR_ODLAT_CMD_MATCH1_ODT_MAX                           (0x0000000F)
+  #define MCMNTS_CR_ODLAT_CMD_MATCH1_ODT_DEF                           (0x00000000)
+  #define MCMNTS_CR_ODLAT_CMD_MATCH1_Web_OFF                           ( 4)
+  #define MCMNTS_CR_ODLAT_CMD_MATCH1_Web_WID                           ( 1)
+  #define MCMNTS_CR_ODLAT_CMD_MATCH1_Web_MSK                           (0x00000010)
+  #define MCMNTS_CR_ODLAT_CMD_MATCH1_Web_MAX                           (0x00000001)
+  #define MCMNTS_CR_ODLAT_CMD_MATCH1_Web_DEF                           (0x00000000)
+  #define MCMNTS_CR_ODLAT_CMD_MATCH1_CASb_OFF                          ( 5)
+  #define MCMNTS_CR_ODLAT_CMD_MATCH1_CASb_WID                          ( 1)
+  #define MCMNTS_CR_ODLAT_CMD_MATCH1_CASb_MSK                          (0x00000020)
+  #define MCMNTS_CR_ODLAT_CMD_MATCH1_CASb_MAX                          (0x00000001)
+  #define MCMNTS_CR_ODLAT_CMD_MATCH1_CASb_DEF                          (0x00000000)
+  #define MCMNTS_CR_ODLAT_CMD_MATCH1_RASb_OFF                          ( 6)
+  #define MCMNTS_CR_ODLAT_CMD_MATCH1_RASb_WID                          ( 1)
+  #define MCMNTS_CR_ODLAT_CMD_MATCH1_RASb_MSK                          (0x00000040)
+  #define MCMNTS_CR_ODLAT_CMD_MATCH1_RASb_MAX                          (0x00000001)
+  #define MCMNTS_CR_ODLAT_CMD_MATCH1_RASb_DEF                          (0x00000000)
+  #define MCMNTS_CR_ODLAT_CMD_MATCH1_CSb_OFF                           ( 7)
+  #define MCMNTS_CR_ODLAT_CMD_MATCH1_CSb_WID                           ( 4)
+  #define MCMNTS_CR_ODLAT_CMD_MATCH1_CSb_MSK                           (0x00000780)
+  #define MCMNTS_CR_ODLAT_CMD_MATCH1_CSb_MAX                           (0x0000000F)
+  #define MCMNTS_CR_ODLAT_CMD_MATCH1_CSb_DEF                           (0x00000000)
+  #define MCMNTS_CR_ODLAT_CMD_MATCH1_CKE_OFF                           (11)
+  #define MCMNTS_CR_ODLAT_CMD_MATCH1_CKE_WID                           ( 4)
+  #define MCMNTS_CR_ODLAT_CMD_MATCH1_CKE_MSK                           (0x00007800)
+  #define MCMNTS_CR_ODLAT_CMD_MATCH1_CKE_MAX                           (0x0000000F)
+  #define MCMNTS_CR_ODLAT_CMD_MATCH1_CKE_DEF                           (0x00000000)
+  #define MCMNTS_CR_ODLAT_CMD_MATCH1_MA_OFF                            (15)
+  #define MCMNTS_CR_ODLAT_CMD_MATCH1_MA_WID                            (16)
+  #define MCMNTS_CR_ODLAT_CMD_MATCH1_MA_MSK                            (0x7FFF8000)
+  #define MCMNTS_CR_ODLAT_CMD_MATCH1_MA_MAX                            (0x0000FFFF)
+  #define MCMNTS_CR_ODLAT_CMD_MATCH1_MA_DEF                            (0x00000000)
+
+#define MCMNTS_CR_ODLAT_CMD_MATCH2_REG                               (0x00004F48)
+  #define MCMNTS_CR_ODLAT_CMD_MATCH2_ODT_OFF                           ( 0)
+  #define MCMNTS_CR_ODLAT_CMD_MATCH2_ODT_WID                           ( 4)
+  #define MCMNTS_CR_ODLAT_CMD_MATCH2_ODT_MSK                           (0x0000000F)
+  #define MCMNTS_CR_ODLAT_CMD_MATCH2_ODT_MAX                           (0x0000000F)
+  #define MCMNTS_CR_ODLAT_CMD_MATCH2_ODT_DEF                           (0x00000000)
+  #define MCMNTS_CR_ODLAT_CMD_MATCH2_Web_OFF                           ( 4)
+  #define MCMNTS_CR_ODLAT_CMD_MATCH2_Web_WID                           ( 1)
+  #define MCMNTS_CR_ODLAT_CMD_MATCH2_Web_MSK                           (0x00000010)
+  #define MCMNTS_CR_ODLAT_CMD_MATCH2_Web_MAX                           (0x00000001)
+  #define MCMNTS_CR_ODLAT_CMD_MATCH2_Web_DEF                           (0x00000000)
+  #define MCMNTS_CR_ODLAT_CMD_MATCH2_CASb_OFF                          ( 5)
+  #define MCMNTS_CR_ODLAT_CMD_MATCH2_CASb_WID                          ( 1)
+  #define MCMNTS_CR_ODLAT_CMD_MATCH2_CASb_MSK                          (0x00000020)
+  #define MCMNTS_CR_ODLAT_CMD_MATCH2_CASb_MAX                          (0x00000001)
+  #define MCMNTS_CR_ODLAT_CMD_MATCH2_CASb_DEF                          (0x00000000)
+  #define MCMNTS_CR_ODLAT_CMD_MATCH2_RASb_OFF                          ( 6)
+  #define MCMNTS_CR_ODLAT_CMD_MATCH2_RASb_WID                          ( 1)
+  #define MCMNTS_CR_ODLAT_CMD_MATCH2_RASb_MSK                          (0x00000040)
+  #define MCMNTS_CR_ODLAT_CMD_MATCH2_RASb_MAX                          (0x00000001)
+  #define MCMNTS_CR_ODLAT_CMD_MATCH2_RASb_DEF                          (0x00000000)
+  #define MCMNTS_CR_ODLAT_CMD_MATCH2_CSb_OFF                           ( 7)
+  #define MCMNTS_CR_ODLAT_CMD_MATCH2_CSb_WID                           ( 4)
+  #define MCMNTS_CR_ODLAT_CMD_MATCH2_CSb_MSK                           (0x00000780)
+  #define MCMNTS_CR_ODLAT_CMD_MATCH2_CSb_MAX                           (0x0000000F)
+  #define MCMNTS_CR_ODLAT_CMD_MATCH2_CSb_DEF                           (0x00000000)
+  #define MCMNTS_CR_ODLAT_CMD_MATCH2_CKE_OFF                           (11)
+  #define MCMNTS_CR_ODLAT_CMD_MATCH2_CKE_WID                           ( 4)
+  #define MCMNTS_CR_ODLAT_CMD_MATCH2_CKE_MSK                           (0x00007800)
+  #define MCMNTS_CR_ODLAT_CMD_MATCH2_CKE_MAX                           (0x0000000F)
+  #define MCMNTS_CR_ODLAT_CMD_MATCH2_CKE_DEF                           (0x00000000)
+  #define MCMNTS_CR_ODLAT_CMD_MATCH2_MA_OFF                            (15)
+  #define MCMNTS_CR_ODLAT_CMD_MATCH2_MA_WID                            (16)
+  #define MCMNTS_CR_ODLAT_CMD_MATCH2_MA_MSK                            (0x7FFF8000)
+  #define MCMNTS_CR_ODLAT_CMD_MATCH2_MA_MAX                            (0x0000FFFF)
+  #define MCMNTS_CR_ODLAT_CMD_MATCH2_MA_DEF                            (0x00000000)
+
+#define MCMNTS_CR_ODLAT_CMD_MATCH3_REG                               (0x00004F4C)
+  #define MCMNTS_CR_ODLAT_CMD_MATCH3_ODT_OFF                           ( 0)
+  #define MCMNTS_CR_ODLAT_CMD_MATCH3_ODT_WID                           ( 4)
+  #define MCMNTS_CR_ODLAT_CMD_MATCH3_ODT_MSK                           (0x0000000F)
+  #define MCMNTS_CR_ODLAT_CMD_MATCH3_ODT_MAX                           (0x0000000F)
+  #define MCMNTS_CR_ODLAT_CMD_MATCH3_ODT_DEF                           (0x00000000)
+  #define MCMNTS_CR_ODLAT_CMD_MATCH3_Web_OFF                           ( 4)
+  #define MCMNTS_CR_ODLAT_CMD_MATCH3_Web_WID                           ( 1)
+  #define MCMNTS_CR_ODLAT_CMD_MATCH3_Web_MSK                           (0x00000010)
+  #define MCMNTS_CR_ODLAT_CMD_MATCH3_Web_MAX                           (0x00000001)
+  #define MCMNTS_CR_ODLAT_CMD_MATCH3_Web_DEF                           (0x00000000)
+  #define MCMNTS_CR_ODLAT_CMD_MATCH3_CASb_OFF                          ( 5)
+  #define MCMNTS_CR_ODLAT_CMD_MATCH3_CASb_WID                          ( 1)
+  #define MCMNTS_CR_ODLAT_CMD_MATCH3_CASb_MSK                          (0x00000020)
+  #define MCMNTS_CR_ODLAT_CMD_MATCH3_CASb_MAX                          (0x00000001)
+  #define MCMNTS_CR_ODLAT_CMD_MATCH3_CASb_DEF                          (0x00000000)
+  #define MCMNTS_CR_ODLAT_CMD_MATCH3_RASb_OFF                          ( 6)
+  #define MCMNTS_CR_ODLAT_CMD_MATCH3_RASb_WID                          ( 1)
+  #define MCMNTS_CR_ODLAT_CMD_MATCH3_RASb_MSK                          (0x00000040)
+  #define MCMNTS_CR_ODLAT_CMD_MATCH3_RASb_MAX                          (0x00000001)
+  #define MCMNTS_CR_ODLAT_CMD_MATCH3_RASb_DEF                          (0x00000000)
+  #define MCMNTS_CR_ODLAT_CMD_MATCH3_CSb_OFF                           ( 7)
+  #define MCMNTS_CR_ODLAT_CMD_MATCH3_CSb_WID                           ( 4)
+  #define MCMNTS_CR_ODLAT_CMD_MATCH3_CSb_MSK                           (0x00000780)
+  #define MCMNTS_CR_ODLAT_CMD_MATCH3_CSb_MAX                           (0x0000000F)
+  #define MCMNTS_CR_ODLAT_CMD_MATCH3_CSb_DEF                           (0x00000000)
+  #define MCMNTS_CR_ODLAT_CMD_MATCH3_CKE_OFF                           (11)
+  #define MCMNTS_CR_ODLAT_CMD_MATCH3_CKE_WID                           ( 4)
+  #define MCMNTS_CR_ODLAT_CMD_MATCH3_CKE_MSK                           (0x00007800)
+  #define MCMNTS_CR_ODLAT_CMD_MATCH3_CKE_MAX                           (0x0000000F)
+  #define MCMNTS_CR_ODLAT_CMD_MATCH3_CKE_DEF                           (0x00000000)
+  #define MCMNTS_CR_ODLAT_CMD_MATCH3_MA_OFF                            (15)
+  #define MCMNTS_CR_ODLAT_CMD_MATCH3_MA_WID                            (16)
+  #define MCMNTS_CR_ODLAT_CMD_MATCH3_MA_MSK                            (0x7FFF8000)
+  #define MCMNTS_CR_ODLAT_CMD_MATCH3_MA_MAX                            (0x0000FFFF)
+  #define MCMNTS_CR_ODLAT_CMD_MATCH3_MA_DEF                            (0x00000000)
+
+#define MCMNTS_CR_ODLAT_CMD_MASK0_REG                                (0x00004F50)
+  #define MCMNTS_CR_ODLAT_CMD_MASK0_ODT_OFF                            ( 0)
+  #define MCMNTS_CR_ODLAT_CMD_MASK0_ODT_WID                            ( 4)
+  #define MCMNTS_CR_ODLAT_CMD_MASK0_ODT_MSK                            (0x0000000F)
+  #define MCMNTS_CR_ODLAT_CMD_MASK0_ODT_MAX                            (0x0000000F)
+  #define MCMNTS_CR_ODLAT_CMD_MASK0_ODT_DEF                            (0x00000000)
+  #define MCMNTS_CR_ODLAT_CMD_MASK0_Web_OFF                            ( 4)
+  #define MCMNTS_CR_ODLAT_CMD_MASK0_Web_WID                            ( 1)
+  #define MCMNTS_CR_ODLAT_CMD_MASK0_Web_MSK                            (0x00000010)
+  #define MCMNTS_CR_ODLAT_CMD_MASK0_Web_MAX                            (0x00000001)
+  #define MCMNTS_CR_ODLAT_CMD_MASK0_Web_DEF                            (0x00000000)
+  #define MCMNTS_CR_ODLAT_CMD_MASK0_CASb_OFF                           ( 5)
+  #define MCMNTS_CR_ODLAT_CMD_MASK0_CASb_WID                           ( 1)
+  #define MCMNTS_CR_ODLAT_CMD_MASK0_CASb_MSK                           (0x00000020)
+  #define MCMNTS_CR_ODLAT_CMD_MASK0_CASb_MAX                           (0x00000001)
+  #define MCMNTS_CR_ODLAT_CMD_MASK0_CASb_DEF                           (0x00000000)
+  #define MCMNTS_CR_ODLAT_CMD_MASK0_RASb_OFF                           ( 6)
+  #define MCMNTS_CR_ODLAT_CMD_MASK0_RASb_WID                           ( 1)
+  #define MCMNTS_CR_ODLAT_CMD_MASK0_RASb_MSK                           (0x00000040)
+  #define MCMNTS_CR_ODLAT_CMD_MASK0_RASb_MAX                           (0x00000001)
+  #define MCMNTS_CR_ODLAT_CMD_MASK0_RASb_DEF                           (0x00000000)
+  #define MCMNTS_CR_ODLAT_CMD_MASK0_CSb_OFF                            ( 7)
+  #define MCMNTS_CR_ODLAT_CMD_MASK0_CSb_WID                            ( 4)
+  #define MCMNTS_CR_ODLAT_CMD_MASK0_CSb_MSK                            (0x00000780)
+  #define MCMNTS_CR_ODLAT_CMD_MASK0_CSb_MAX                            (0x0000000F)
+  #define MCMNTS_CR_ODLAT_CMD_MASK0_CSb_DEF                            (0x00000000)
+  #define MCMNTS_CR_ODLAT_CMD_MASK0_CKE_OFF                            (11)
+  #define MCMNTS_CR_ODLAT_CMD_MASK0_CKE_WID                            ( 4)
+  #define MCMNTS_CR_ODLAT_CMD_MASK0_CKE_MSK                            (0x00007800)
+  #define MCMNTS_CR_ODLAT_CMD_MASK0_CKE_MAX                            (0x0000000F)
+  #define MCMNTS_CR_ODLAT_CMD_MASK0_CKE_DEF                            (0x00000000)
+  #define MCMNTS_CR_ODLAT_CMD_MASK0_MA_OFF                             (15)
+  #define MCMNTS_CR_ODLAT_CMD_MASK0_MA_WID                             (16)
+  #define MCMNTS_CR_ODLAT_CMD_MASK0_MA_MSK                             (0x7FFF8000)
+  #define MCMNTS_CR_ODLAT_CMD_MASK0_MA_MAX                             (0x0000FFFF)
+  #define MCMNTS_CR_ODLAT_CMD_MASK0_MA_DEF                             (0x00000000)
+
+#define MCMNTS_CR_ODLAT_CMD_MASK1_REG                                (0x00004F54)
+  #define MCMNTS_CR_ODLAT_CMD_MASK1_ODT_OFF                            ( 0)
+  #define MCMNTS_CR_ODLAT_CMD_MASK1_ODT_WID                            ( 4)
+  #define MCMNTS_CR_ODLAT_CMD_MASK1_ODT_MSK                            (0x0000000F)
+  #define MCMNTS_CR_ODLAT_CMD_MASK1_ODT_MAX                            (0x0000000F)
+  #define MCMNTS_CR_ODLAT_CMD_MASK1_ODT_DEF                            (0x00000000)
+  #define MCMNTS_CR_ODLAT_CMD_MASK1_Web_OFF                            ( 4)
+  #define MCMNTS_CR_ODLAT_CMD_MASK1_Web_WID                            ( 1)
+  #define MCMNTS_CR_ODLAT_CMD_MASK1_Web_MSK                            (0x00000010)
+  #define MCMNTS_CR_ODLAT_CMD_MASK1_Web_MAX                            (0x00000001)
+  #define MCMNTS_CR_ODLAT_CMD_MASK1_Web_DEF                            (0x00000000)
+  #define MCMNTS_CR_ODLAT_CMD_MASK1_CASb_OFF                           ( 5)
+  #define MCMNTS_CR_ODLAT_CMD_MASK1_CASb_WID                           ( 1)
+  #define MCMNTS_CR_ODLAT_CMD_MASK1_CASb_MSK                           (0x00000020)
+  #define MCMNTS_CR_ODLAT_CMD_MASK1_CASb_MAX                           (0x00000001)
+  #define MCMNTS_CR_ODLAT_CMD_MASK1_CASb_DEF                           (0x00000000)
+  #define MCMNTS_CR_ODLAT_CMD_MASK1_RASb_OFF                           ( 6)
+  #define MCMNTS_CR_ODLAT_CMD_MASK1_RASb_WID                           ( 1)
+  #define MCMNTS_CR_ODLAT_CMD_MASK1_RASb_MSK                           (0x00000040)
+  #define MCMNTS_CR_ODLAT_CMD_MASK1_RASb_MAX                           (0x00000001)
+  #define MCMNTS_CR_ODLAT_CMD_MASK1_RASb_DEF                           (0x00000000)
+  #define MCMNTS_CR_ODLAT_CMD_MASK1_CSb_OFF                            ( 7)
+  #define MCMNTS_CR_ODLAT_CMD_MASK1_CSb_WID                            ( 4)
+  #define MCMNTS_CR_ODLAT_CMD_MASK1_CSb_MSK                            (0x00000780)
+  #define MCMNTS_CR_ODLAT_CMD_MASK1_CSb_MAX                            (0x0000000F)
+  #define MCMNTS_CR_ODLAT_CMD_MASK1_CSb_DEF                            (0x00000000)
+  #define MCMNTS_CR_ODLAT_CMD_MASK1_CKE_OFF                            (11)
+  #define MCMNTS_CR_ODLAT_CMD_MASK1_CKE_WID                            ( 4)
+  #define MCMNTS_CR_ODLAT_CMD_MASK1_CKE_MSK                            (0x00007800)
+  #define MCMNTS_CR_ODLAT_CMD_MASK1_CKE_MAX                            (0x0000000F)
+  #define MCMNTS_CR_ODLAT_CMD_MASK1_CKE_DEF                            (0x00000000)
+  #define MCMNTS_CR_ODLAT_CMD_MASK1_MA_OFF                             (15)
+  #define MCMNTS_CR_ODLAT_CMD_MASK1_MA_WID                             (16)
+  #define MCMNTS_CR_ODLAT_CMD_MASK1_MA_MSK                             (0x7FFF8000)
+  #define MCMNTS_CR_ODLAT_CMD_MASK1_MA_MAX                             (0x0000FFFF)
+  #define MCMNTS_CR_ODLAT_CMD_MASK1_MA_DEF                             (0x00000000)
+
+#define MCMNTS_CR_ODLAT_CMD_MASK2_REG                                (0x00004F58)
+  #define MCMNTS_CR_ODLAT_CMD_MASK2_ODT_OFF                            ( 0)
+  #define MCMNTS_CR_ODLAT_CMD_MASK2_ODT_WID                            ( 4)
+  #define MCMNTS_CR_ODLAT_CMD_MASK2_ODT_MSK                            (0x0000000F)
+  #define MCMNTS_CR_ODLAT_CMD_MASK2_ODT_MAX                            (0x0000000F)
+  #define MCMNTS_CR_ODLAT_CMD_MASK2_ODT_DEF                            (0x00000000)
+  #define MCMNTS_CR_ODLAT_CMD_MASK2_Web_OFF                            ( 4)
+  #define MCMNTS_CR_ODLAT_CMD_MASK2_Web_WID                            ( 1)
+  #define MCMNTS_CR_ODLAT_CMD_MASK2_Web_MSK                            (0x00000010)
+  #define MCMNTS_CR_ODLAT_CMD_MASK2_Web_MAX                            (0x00000001)
+  #define MCMNTS_CR_ODLAT_CMD_MASK2_Web_DEF                            (0x00000000)
+  #define MCMNTS_CR_ODLAT_CMD_MASK2_CASb_OFF                           ( 5)
+  #define MCMNTS_CR_ODLAT_CMD_MASK2_CASb_WID                           ( 1)
+  #define MCMNTS_CR_ODLAT_CMD_MASK2_CASb_MSK                           (0x00000020)
+  #define MCMNTS_CR_ODLAT_CMD_MASK2_CASb_MAX                           (0x00000001)
+  #define MCMNTS_CR_ODLAT_CMD_MASK2_CASb_DEF                           (0x00000000)
+  #define MCMNTS_CR_ODLAT_CMD_MASK2_RASb_OFF                           ( 6)
+  #define MCMNTS_CR_ODLAT_CMD_MASK2_RASb_WID                           ( 1)
+  #define MCMNTS_CR_ODLAT_CMD_MASK2_RASb_MSK                           (0x00000040)
+  #define MCMNTS_CR_ODLAT_CMD_MASK2_RASb_MAX                           (0x00000001)
+  #define MCMNTS_CR_ODLAT_CMD_MASK2_RASb_DEF                           (0x00000000)
+  #define MCMNTS_CR_ODLAT_CMD_MASK2_CSb_OFF                            ( 7)
+  #define MCMNTS_CR_ODLAT_CMD_MASK2_CSb_WID                            ( 4)
+  #define MCMNTS_CR_ODLAT_CMD_MASK2_CSb_MSK                            (0x00000780)
+  #define MCMNTS_CR_ODLAT_CMD_MASK2_CSb_MAX                            (0x0000000F)
+  #define MCMNTS_CR_ODLAT_CMD_MASK2_CSb_DEF                            (0x00000000)
+  #define MCMNTS_CR_ODLAT_CMD_MASK2_CKE_OFF                            (11)
+  #define MCMNTS_CR_ODLAT_CMD_MASK2_CKE_WID                            ( 4)
+  #define MCMNTS_CR_ODLAT_CMD_MASK2_CKE_MSK                            (0x00007800)
+  #define MCMNTS_CR_ODLAT_CMD_MASK2_CKE_MAX                            (0x0000000F)
+  #define MCMNTS_CR_ODLAT_CMD_MASK2_CKE_DEF                            (0x00000000)
+  #define MCMNTS_CR_ODLAT_CMD_MASK2_MA_OFF                             (15)
+  #define MCMNTS_CR_ODLAT_CMD_MASK2_MA_WID                             (16)
+  #define MCMNTS_CR_ODLAT_CMD_MASK2_MA_MSK                             (0x7FFF8000)
+  #define MCMNTS_CR_ODLAT_CMD_MASK2_MA_MAX                             (0x0000FFFF)
+  #define MCMNTS_CR_ODLAT_CMD_MASK2_MA_DEF                             (0x00000000)
+
+#define MCMNTS_CR_ODLAT_CMD_MASK3_REG                                (0x00004F5C)
+  #define MCMNTS_CR_ODLAT_CMD_MASK3_ODT_OFF                            ( 0)
+  #define MCMNTS_CR_ODLAT_CMD_MASK3_ODT_WID                            ( 4)
+  #define MCMNTS_CR_ODLAT_CMD_MASK3_ODT_MSK                            (0x0000000F)
+  #define MCMNTS_CR_ODLAT_CMD_MASK3_ODT_MAX                            (0x0000000F)
+  #define MCMNTS_CR_ODLAT_CMD_MASK3_ODT_DEF                            (0x00000000)
+  #define MCMNTS_CR_ODLAT_CMD_MASK3_Web_OFF                            ( 4)
+  #define MCMNTS_CR_ODLAT_CMD_MASK3_Web_WID                            ( 1)
+  #define MCMNTS_CR_ODLAT_CMD_MASK3_Web_MSK                            (0x00000010)
+  #define MCMNTS_CR_ODLAT_CMD_MASK3_Web_MAX                            (0x00000001)
+  #define MCMNTS_CR_ODLAT_CMD_MASK3_Web_DEF                            (0x00000000)
+  #define MCMNTS_CR_ODLAT_CMD_MASK3_CASb_OFF                           ( 5)
+  #define MCMNTS_CR_ODLAT_CMD_MASK3_CASb_WID                           ( 1)
+  #define MCMNTS_CR_ODLAT_CMD_MASK3_CASb_MSK                           (0x00000020)
+  #define MCMNTS_CR_ODLAT_CMD_MASK3_CASb_MAX                           (0x00000001)
+  #define MCMNTS_CR_ODLAT_CMD_MASK3_CASb_DEF                           (0x00000000)
+  #define MCMNTS_CR_ODLAT_CMD_MASK3_RASb_OFF                           ( 6)
+  #define MCMNTS_CR_ODLAT_CMD_MASK3_RASb_WID                           ( 1)
+  #define MCMNTS_CR_ODLAT_CMD_MASK3_RASb_MSK                           (0x00000040)
+  #define MCMNTS_CR_ODLAT_CMD_MASK3_RASb_MAX                           (0x00000001)
+  #define MCMNTS_CR_ODLAT_CMD_MASK3_RASb_DEF                           (0x00000000)
+  #define MCMNTS_CR_ODLAT_CMD_MASK3_CSb_OFF                            ( 7)
+  #define MCMNTS_CR_ODLAT_CMD_MASK3_CSb_WID                            ( 4)
+  #define MCMNTS_CR_ODLAT_CMD_MASK3_CSb_MSK                            (0x00000780)
+  #define MCMNTS_CR_ODLAT_CMD_MASK3_CSb_MAX                            (0x0000000F)
+  #define MCMNTS_CR_ODLAT_CMD_MASK3_CSb_DEF                            (0x00000000)
+  #define MCMNTS_CR_ODLAT_CMD_MASK3_CKE_OFF                            (11)
+  #define MCMNTS_CR_ODLAT_CMD_MASK3_CKE_WID                            ( 4)
+  #define MCMNTS_CR_ODLAT_CMD_MASK3_CKE_MSK                            (0x00007800)
+  #define MCMNTS_CR_ODLAT_CMD_MASK3_CKE_MAX                            (0x0000000F)
+  #define MCMNTS_CR_ODLAT_CMD_MASK3_CKE_DEF                            (0x00000000)
+  #define MCMNTS_CR_ODLAT_CMD_MASK3_MA_OFF                             (15)
+  #define MCMNTS_CR_ODLAT_CMD_MASK3_MA_WID                             (16)
+  #define MCMNTS_CR_ODLAT_CMD_MASK3_MA_MSK                             (0x7FFF8000)
+  #define MCMNTS_CR_ODLAT_CMD_MASK3_MA_MAX                             (0x0000FFFF)
+  #define MCMNTS_CR_ODLAT_CMD_MASK3_MA_DEF                             (0x00000000)
+
+#define MCMNTS_CR_ODLAT_CMD_BANK_REG                                 (0x00004F60)
+  #define MCMNTS_CR_ODLAT_CMD_BANK_BankMatch0_OFF                      ( 0)
+  #define MCMNTS_CR_ODLAT_CMD_BANK_BankMatch0_WID                      ( 3)
+  #define MCMNTS_CR_ODLAT_CMD_BANK_BankMatch0_MSK                      (0x00000007)
+  #define MCMNTS_CR_ODLAT_CMD_BANK_BankMatch0_MAX                      (0x00000007)
+  #define MCMNTS_CR_ODLAT_CMD_BANK_BankMatch0_DEF                      (0x00000000)
+  #define MCMNTS_CR_ODLAT_CMD_BANK_BankMatch1_OFF                      ( 3)
+  #define MCMNTS_CR_ODLAT_CMD_BANK_BankMatch1_WID                      ( 3)
+  #define MCMNTS_CR_ODLAT_CMD_BANK_BankMatch1_MSK                      (0x00000038)
+  #define MCMNTS_CR_ODLAT_CMD_BANK_BankMatch1_MAX                      (0x00000007)
+  #define MCMNTS_CR_ODLAT_CMD_BANK_BankMatch1_DEF                      (0x00000000)
+  #define MCMNTS_CR_ODLAT_CMD_BANK_BankMatch2_OFF                      ( 6)
+  #define MCMNTS_CR_ODLAT_CMD_BANK_BankMatch2_WID                      ( 3)
+  #define MCMNTS_CR_ODLAT_CMD_BANK_BankMatch2_MSK                      (0x000001C0)
+  #define MCMNTS_CR_ODLAT_CMD_BANK_BankMatch2_MAX                      (0x00000007)
+  #define MCMNTS_CR_ODLAT_CMD_BANK_BankMatch2_DEF                      (0x00000000)
+  #define MCMNTS_CR_ODLAT_CMD_BANK_BankMatch3_OFF                      ( 9)
+  #define MCMNTS_CR_ODLAT_CMD_BANK_BankMatch3_WID                      ( 3)
+  #define MCMNTS_CR_ODLAT_CMD_BANK_BankMatch3_MSK                      (0x00000E00)
+  #define MCMNTS_CR_ODLAT_CMD_BANK_BankMatch3_MAX                      (0x00000007)
+  #define MCMNTS_CR_ODLAT_CMD_BANK_BankMatch3_DEF                      (0x00000000)
+  #define MCMNTS_CR_ODLAT_CMD_BANK_BankMask0_OFF                       (12)
+  #define MCMNTS_CR_ODLAT_CMD_BANK_BankMask0_WID                       ( 3)
+  #define MCMNTS_CR_ODLAT_CMD_BANK_BankMask0_MSK                       (0x00007000)
+  #define MCMNTS_CR_ODLAT_CMD_BANK_BankMask0_MAX                       (0x00000007)
+  #define MCMNTS_CR_ODLAT_CMD_BANK_BankMask0_DEF                       (0x00000000)
+  #define MCMNTS_CR_ODLAT_CMD_BANK_BankMask1_OFF                       (15)
+  #define MCMNTS_CR_ODLAT_CMD_BANK_BankMask1_WID                       ( 3)
+  #define MCMNTS_CR_ODLAT_CMD_BANK_BankMask1_MSK                       (0x00038000)
+  #define MCMNTS_CR_ODLAT_CMD_BANK_BankMask1_MAX                       (0x00000007)
+  #define MCMNTS_CR_ODLAT_CMD_BANK_BankMask1_DEF                       (0x00000000)
+  #define MCMNTS_CR_ODLAT_CMD_BANK_BankMask2_OFF                       (18)
+  #define MCMNTS_CR_ODLAT_CMD_BANK_BankMask2_WID                       ( 3)
+  #define MCMNTS_CR_ODLAT_CMD_BANK_BankMask2_MSK                       (0x001C0000)
+  #define MCMNTS_CR_ODLAT_CMD_BANK_BankMask2_MAX                       (0x00000007)
+  #define MCMNTS_CR_ODLAT_CMD_BANK_BankMask2_DEF                       (0x00000000)
+  #define MCMNTS_CR_ODLAT_CMD_BANK_BankMask3_OFF                       (21)
+  #define MCMNTS_CR_ODLAT_CMD_BANK_BankMask3_WID                       ( 3)
+  #define MCMNTS_CR_ODLAT_CMD_BANK_BankMask3_MSK                       (0x00E00000)
+  #define MCMNTS_CR_ODLAT_CMD_BANK_BankMask3_MAX                       (0x00000007)
+  #define MCMNTS_CR_ODLAT_CMD_BANK_BankMask3_DEF                       (0x00000000)
+
+#define MCMNTS_CR_ODLAT_SEQ_LEVEL0_REG                               (0x00004F64)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL0_InputMatch_OFF                    ( 0)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL0_InputMatch_WID                    ( 4)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL0_InputMatch_MSK                    (0x0000000F)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL0_InputMatch_MAX                    (0x0000000F)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL0_InputMatch_DEF                    (0x00000000)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL0_InputInvert_OFF                   ( 4)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL0_InputInvert_WID                   ( 4)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL0_InputInvert_MSK                   (0x000000F0)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL0_InputInvert_MAX                   (0x0000000F)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL0_InputInvert_DEF                   (0x00000000)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL0_CountMatches_OFF                  ( 8)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL0_CountMatches_WID                  ( 1)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL0_CountMatches_MSK                  (0x00000100)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL0_CountMatches_MAX                  (0x00000001)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL0_CountMatches_DEF                  (0x00000000)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL0_CounterThreshold_OFF              ( 9)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL0_CounterThreshold_WID              (15)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL0_CounterThreshold_MSK              (0x00FFFE00)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL0_CounterThreshold_MAX              (0x00007FFF)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL0_CounterThreshold_DEF              (0x00000000)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL0_CounterAction_OFF                 (24)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL0_CounterAction_WID                 ( 2)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL0_CounterAction_MSK                 (0x03000000)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL0_CounterAction_MAX                 (0x00000003)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL0_CounterAction_DEF                 (0x00000000)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL0_CounterNextState_OFF              (26)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL0_CounterNextState_WID              ( 2)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL0_CounterNextState_MSK              (0x0C000000)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL0_CounterNextState_MAX              (0x00000003)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL0_CounterNextState_DEF              (0x00000000)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL0_MatchAction_OFF                   (28)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL0_MatchAction_WID                   ( 2)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL0_MatchAction_MSK                   (0x30000000)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL0_MatchAction_MAX                   (0x00000003)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL0_MatchAction_DEF                   (0x00000000)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL0_MatchNextState_OFF                (30)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL0_MatchNextState_WID                ( 2)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL0_MatchNextState_MSK                (0xC0000000)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL0_MatchNextState_MAX                (0x00000003)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL0_MatchNextState_DEF                (0x00000000)
+
+#define MCMNTS_CR_ODLAT_SEQ_LEVEL1_REG                               (0x00004F68)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL1_InputMatch_OFF                    ( 0)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL1_InputMatch_WID                    ( 4)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL1_InputMatch_MSK                    (0x0000000F)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL1_InputMatch_MAX                    (0x0000000F)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL1_InputMatch_DEF                    (0x00000000)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL1_InputInvert_OFF                   ( 4)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL1_InputInvert_WID                   ( 4)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL1_InputInvert_MSK                   (0x000000F0)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL1_InputInvert_MAX                   (0x0000000F)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL1_InputInvert_DEF                   (0x00000000)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL1_CountMatches_OFF                  ( 8)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL1_CountMatches_WID                  ( 1)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL1_CountMatches_MSK                  (0x00000100)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL1_CountMatches_MAX                  (0x00000001)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL1_CountMatches_DEF                  (0x00000000)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL1_CounterThreshold_OFF              ( 9)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL1_CounterThreshold_WID              (15)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL1_CounterThreshold_MSK              (0x00FFFE00)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL1_CounterThreshold_MAX              (0x00007FFF)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL1_CounterThreshold_DEF              (0x00000000)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL1_CounterAction_OFF                 (24)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL1_CounterAction_WID                 ( 2)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL1_CounterAction_MSK                 (0x03000000)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL1_CounterAction_MAX                 (0x00000003)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL1_CounterAction_DEF                 (0x00000000)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL1_CounterNextState_OFF              (26)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL1_CounterNextState_WID              ( 2)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL1_CounterNextState_MSK              (0x0C000000)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL1_CounterNextState_MAX              (0x00000003)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL1_CounterNextState_DEF              (0x00000000)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL1_MatchAction_OFF                   (28)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL1_MatchAction_WID                   ( 2)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL1_MatchAction_MSK                   (0x30000000)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL1_MatchAction_MAX                   (0x00000003)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL1_MatchAction_DEF                   (0x00000000)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL1_MatchNextState_OFF                (30)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL1_MatchNextState_WID                ( 2)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL1_MatchNextState_MSK                (0xC0000000)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL1_MatchNextState_MAX                (0x00000003)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL1_MatchNextState_DEF                (0x00000000)
+
+#define MCMNTS_CR_ODLAT_SEQ_LEVEL2_REG                               (0x00004F6C)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL2_InputMatch_OFF                    ( 0)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL2_InputMatch_WID                    ( 4)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL2_InputMatch_MSK                    (0x0000000F)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL2_InputMatch_MAX                    (0x0000000F)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL2_InputMatch_DEF                    (0x00000000)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL2_InputInvert_OFF                   ( 4)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL2_InputInvert_WID                   ( 4)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL2_InputInvert_MSK                   (0x000000F0)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL2_InputInvert_MAX                   (0x0000000F)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL2_InputInvert_DEF                   (0x00000000)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL2_CountMatches_OFF                  ( 8)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL2_CountMatches_WID                  ( 1)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL2_CountMatches_MSK                  (0x00000100)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL2_CountMatches_MAX                  (0x00000001)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL2_CountMatches_DEF                  (0x00000000)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL2_CounterThreshold_OFF              ( 9)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL2_CounterThreshold_WID              (15)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL2_CounterThreshold_MSK              (0x00FFFE00)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL2_CounterThreshold_MAX              (0x00007FFF)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL2_CounterThreshold_DEF              (0x00000000)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL2_CounterAction_OFF                 (24)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL2_CounterAction_WID                 ( 2)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL2_CounterAction_MSK                 (0x03000000)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL2_CounterAction_MAX                 (0x00000003)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL2_CounterAction_DEF                 (0x00000000)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL2_CounterNextState_OFF              (26)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL2_CounterNextState_WID              ( 2)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL2_CounterNextState_MSK              (0x0C000000)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL2_CounterNextState_MAX              (0x00000003)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL2_CounterNextState_DEF              (0x00000000)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL2_MatchAction_OFF                   (28)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL2_MatchAction_WID                   ( 2)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL2_MatchAction_MSK                   (0x30000000)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL2_MatchAction_MAX                   (0x00000003)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL2_MatchAction_DEF                   (0x00000000)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL2_MatchNextState_OFF                (30)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL2_MatchNextState_WID                ( 2)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL2_MatchNextState_MSK                (0xC0000000)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL2_MatchNextState_MAX                (0x00000003)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL2_MatchNextState_DEF                (0x00000000)
+
+#define MCMNTS_CR_ODLAT_SEQ_LEVEL3_REG                               (0x00004F70)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL3_InputMatch_OFF                    ( 0)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL3_InputMatch_WID                    ( 4)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL3_InputMatch_MSK                    (0x0000000F)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL3_InputMatch_MAX                    (0x0000000F)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL3_InputMatch_DEF                    (0x00000000)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL3_InputInvert_OFF                   ( 4)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL3_InputInvert_WID                   ( 4)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL3_InputInvert_MSK                   (0x000000F0)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL3_InputInvert_MAX                   (0x0000000F)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL3_InputInvert_DEF                   (0x00000000)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL3_CountMatches_OFF                  ( 8)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL3_CountMatches_WID                  ( 1)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL3_CountMatches_MSK                  (0x00000100)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL3_CountMatches_MAX                  (0x00000001)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL3_CountMatches_DEF                  (0x00000000)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL3_CounterThreshold_OFF              ( 9)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL3_CounterThreshold_WID              (15)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL3_CounterThreshold_MSK              (0x00FFFE00)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL3_CounterThreshold_MAX              (0x00007FFF)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL3_CounterThreshold_DEF              (0x00000000)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL3_CounterAction_OFF                 (24)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL3_CounterAction_WID                 ( 2)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL3_CounterAction_MSK                 (0x03000000)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL3_CounterAction_MAX                 (0x00000003)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL3_CounterAction_DEF                 (0x00000000)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL3_CounterNextState_OFF              (26)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL3_CounterNextState_WID              ( 2)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL3_CounterNextState_MSK              (0x0C000000)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL3_CounterNextState_MAX              (0x00000003)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL3_CounterNextState_DEF              (0x00000000)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL3_MatchAction_OFF                   (28)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL3_MatchAction_WID                   ( 2)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL3_MatchAction_MSK                   (0x30000000)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL3_MatchAction_MAX                   (0x00000003)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL3_MatchAction_DEF                   (0x00000000)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL3_MatchNextState_OFF                (30)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL3_MatchNextState_WID                ( 2)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL3_MatchNextState_MSK                (0xC0000000)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL3_MatchNextState_MAX                (0x00000003)
+  #define MCMNTS_CR_ODLAT_SEQ_LEVEL3_MatchNextState_DEF                (0x00000000)
+
+#define MCMNTS_CR_ODLAT_SEQ_GLOBAL_REG                               (0x00004F74)
+  #define MCMNTS_CR_ODLAT_SEQ_GLOBAL_TriggerBlockEnable_OFF            ( 0)
+  #define MCMNTS_CR_ODLAT_SEQ_GLOBAL_TriggerBlockEnable_WID            ( 1)
+  #define MCMNTS_CR_ODLAT_SEQ_GLOBAL_TriggerBlockEnable_MSK            (0x00000001)
+  #define MCMNTS_CR_ODLAT_SEQ_GLOBAL_TriggerBlockEnable_MAX            (0x00000001)
+  #define MCMNTS_CR_ODLAT_SEQ_GLOBAL_TriggerBlockEnable_DEF            (0x00000000)
+  #define MCMNTS_CR_ODLAT_SEQ_GLOBAL_GlobalCounterThreshold_OFF        ( 1)
+  #define MCMNTS_CR_ODLAT_SEQ_GLOBAL_GlobalCounterThreshold_WID        (16)
+  #define MCMNTS_CR_ODLAT_SEQ_GLOBAL_GlobalCounterThreshold_MSK        (0x0001FFFE)
+  #define MCMNTS_CR_ODLAT_SEQ_GLOBAL_GlobalCounterThreshold_MAX        (0x0000FFFF)
+  #define MCMNTS_CR_ODLAT_SEQ_GLOBAL_GlobalCounterThreshold_DEF        (0x00000000)
+
+#define MCMNTS_CR_SC_WDBWM_REG                                       (0x00004F8C)
+  #define MCMNTS_CR_SC_WDBWM_WMM_Enter_OFF                             ( 0)
+  #define MCMNTS_CR_SC_WDBWM_WMM_Enter_WID                             ( 8)
+  #define MCMNTS_CR_SC_WDBWM_WMM_Enter_MSK                             (0x000000FF)
+  #define MCMNTS_CR_SC_WDBWM_WMM_Enter_MAX                             (0x000000FF)
+  #define MCMNTS_CR_SC_WDBWM_WMM_Enter_DEF                             (0x00000038)
+  #define MCMNTS_CR_SC_WDBWM_WMM_Exit_OFF                              ( 8)
+  #define MCMNTS_CR_SC_WDBWM_WMM_Exit_WID                              ( 8)
+  #define MCMNTS_CR_SC_WDBWM_WMM_Exit_MSK                              (0x0000FF00)
+  #define MCMNTS_CR_SC_WDBWM_WMM_Exit_MAX                              (0x000000FF)
+  #define MCMNTS_CR_SC_WDBWM_WMM_Exit_DEF                              (0x00000030)
+  #define MCMNTS_CR_SC_WDBWM_WPQ_IS_OFF                                (16)
+  #define MCMNTS_CR_SC_WDBWM_WPQ_IS_WID                                ( 8)
+  #define MCMNTS_CR_SC_WDBWM_WPQ_IS_MSK                                (0x00FF0000)
+  #define MCMNTS_CR_SC_WDBWM_WPQ_IS_MAX                                (0x000000FF)
+  #define MCMNTS_CR_SC_WDBWM_WPQ_IS_DEF                                (0x0000003C)
+  #define MCMNTS_CR_SC_WDBWM_Starve_count_OFF                          (24)
+  #define MCMNTS_CR_SC_WDBWM_Starve_count_WID                          ( 8)
+  #define MCMNTS_CR_SC_WDBWM_Starve_count_MSK                          (0xFF000000)
+  #define MCMNTS_CR_SC_WDBWM_Starve_count_MAX                          (0x000000FF)
+  #define MCMNTS_CR_SC_WDBWM_Starve_count_DEF                          (0x000000FF)
+
+#define MCMNTS_CR_VISA_CTL_MCMNTS_REG                                (0x00004F90)
+  #define MCMNTS_CR_VISA_CTL_MCMNTS_Data_OFF                           ( 0)
+  #define MCMNTS_CR_VISA_CTL_MCMNTS_Data_WID                           (18)
+  #define MCMNTS_CR_VISA_CTL_MCMNTS_Data_MSK                           (0x0003FFFF)
+  #define MCMNTS_CR_VISA_CTL_MCMNTS_Data_MAX                           (0x0003FFFF)
+  #define MCMNTS_CR_VISA_CTL_MCMNTS_Data_DEF                           (0x00000000)
+  #define MCMNTS_CR_VISA_CTL_MCMNTS_VORANGE_OFF                        (31)
+  #define MCMNTS_CR_VISA_CTL_MCMNTS_VORANGE_WID                        ( 1)
+  #define MCMNTS_CR_VISA_CTL_MCMNTS_VORANGE_MSK                        (0x80000000)
+  #define MCMNTS_CR_VISA_CTL_MCMNTS_VORANGE_MAX                        (0x00000001)
+  #define MCMNTS_CR_VISA_CTL_MCMNTS_VORANGE_DEF                        (0x00000000)
+
+#define MCDECS_CR_MAD_CHNL_MCMAIN_REG                                (0x00005000)
+  #define MCDECS_CR_MAD_CHNL_MCMAIN_CH_A_OFF                           ( 0)
+  #define MCDECS_CR_MAD_CHNL_MCMAIN_CH_A_WID                           ( 2)
+  #define MCDECS_CR_MAD_CHNL_MCMAIN_CH_A_MSK                           (0x00000003)
+  #define MCDECS_CR_MAD_CHNL_MCMAIN_CH_A_MAX                           (0x00000003)
+  #define MCDECS_CR_MAD_CHNL_MCMAIN_CH_A_DEF                           (0x00000000)
+  #define MCDECS_CR_MAD_CHNL_MCMAIN_CH_B_OFF                           ( 2)
+  #define MCDECS_CR_MAD_CHNL_MCMAIN_CH_B_WID                           ( 2)
+  #define MCDECS_CR_MAD_CHNL_MCMAIN_CH_B_MSK                           (0x0000000C)
+  #define MCDECS_CR_MAD_CHNL_MCMAIN_CH_B_MAX                           (0x00000003)
+  #define MCDECS_CR_MAD_CHNL_MCMAIN_CH_B_DEF                           (0x00000001)
+  #define MCDECS_CR_MAD_CHNL_MCMAIN_CH_C_OFF                           ( 4)
+  #define MCDECS_CR_MAD_CHNL_MCMAIN_CH_C_WID                           ( 2)
+  #define MCDECS_CR_MAD_CHNL_MCMAIN_CH_C_MSK                           (0x00000030)
+  #define MCDECS_CR_MAD_CHNL_MCMAIN_CH_C_MAX                           (0x00000003)
+  #define MCDECS_CR_MAD_CHNL_MCMAIN_CH_C_DEF                           (0x00000002)
+  #define MCDECS_CR_MAD_CHNL_MCMAIN_STKD_MODE_OFF                      ( 6)
+  #define MCDECS_CR_MAD_CHNL_MCMAIN_STKD_MODE_WID                      ( 1)
+  #define MCDECS_CR_MAD_CHNL_MCMAIN_STKD_MODE_MSK                      (0x00000040)
+  #define MCDECS_CR_MAD_CHNL_MCMAIN_STKD_MODE_MAX                      (0x00000001)
+  #define MCDECS_CR_MAD_CHNL_MCMAIN_STKD_MODE_DEF                      (0x00000000)
+  #define MCDECS_CR_MAD_CHNL_MCMAIN_STKD_MODE_CH_BITS_OFF              ( 7)
+  #define MCDECS_CR_MAD_CHNL_MCMAIN_STKD_MODE_CH_BITS_WID              ( 3)
+  #define MCDECS_CR_MAD_CHNL_MCMAIN_STKD_MODE_CH_BITS_MSK              (0x00000380)
+  #define MCDECS_CR_MAD_CHNL_MCMAIN_STKD_MODE_CH_BITS_MAX              (0x00000007)
+  #define MCDECS_CR_MAD_CHNL_MCMAIN_STKD_MODE_CH_BITS_DEF              (0x00000000)
+  #define MCDECS_CR_MAD_CHNL_MCMAIN_LPDDR_OFF                          (10)
+  #define MCDECS_CR_MAD_CHNL_MCMAIN_LPDDR_WID                          ( 1)
+  #define MCDECS_CR_MAD_CHNL_MCMAIN_LPDDR_MSK                          (0x00000400)
+  #define MCDECS_CR_MAD_CHNL_MCMAIN_LPDDR_MAX                          (0x00000001)
+  #define MCDECS_CR_MAD_CHNL_MCMAIN_LPDDR_DEF                          (0x00000000)
+
+#define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_REG                            (0x00005004)
+  #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_DIMM_A_Size_OFF                ( 0)
+  #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_DIMM_A_Size_WID                ( 8)
+  #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_DIMM_A_Size_MSK                (0x000000FF)
+  #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_DIMM_A_Size_MAX                (0x000000FF)
+  #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_DIMM_A_Size_DEF                (0x00000000)
+  #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_DIMM_B_Size_OFF                ( 8)
+  #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_DIMM_B_Size_WID                ( 8)
+  #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_DIMM_B_Size_MSK                (0x0000FF00)
+  #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_DIMM_B_Size_MAX                (0x000000FF)
+  #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_DIMM_B_Size_DEF                (0x00000000)
+  #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_DAS_OFF                        (16)
+  #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_DAS_WID                        ( 1)
+  #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_DAS_MSK                        (0x00010000)
+  #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_DAS_MAX                        (0x00000001)
+  #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_DAS_DEF                        (0x00000000)
+  #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_DANOR_OFF                      (17)
+  #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_DANOR_WID                      ( 1)
+  #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_DANOR_MSK                      (0x00020000)
+  #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_DANOR_MAX                      (0x00000001)
+  #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_DANOR_DEF                      (0x00000000)
+  #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_DBNOR_OFF                      (18)
+  #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_DBNOR_WID                      ( 1)
+  #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_DBNOR_MSK                      (0x00040000)
+  #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_DBNOR_MAX                      (0x00000001)
+  #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_DBNOR_DEF                      (0x00000000)
+  #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_DAW_OFF                        (19)
+  #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_DAW_WID                        ( 1)
+  #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_DAW_MSK                        (0x00080000)
+  #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_DAW_MAX                        (0x00000001)
+  #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_DAW_DEF                        (0x00000000)
+  #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_DBW_OFF                        (20)
+  #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_DBW_WID                        ( 1)
+  #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_DBW_MSK                        (0x00100000)
+  #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_DBW_MAX                        (0x00000001)
+  #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_DBW_DEF                        (0x00000000)
+  #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_RI_OFF                         (21)
+  #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_RI_WID                         ( 1)
+  #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_RI_MSK                         (0x00200000)
+  #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_RI_MAX                         (0x00000001)
+  #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_RI_DEF                         (0x00000001)
+  #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_Enh_Interleave_OFF             (22)
+  #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_Enh_Interleave_WID             ( 1)
+  #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_Enh_Interleave_MSK             (0x00400000)
+  #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_Enh_Interleave_MAX             (0x00000001)
+  #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_Enh_Interleave_DEF             (0x00000001)
+  #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_ECC_OFF                        (24)
+  #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_ECC_WID                        ( 2)
+  #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_ECC_MSK                        (0x03000000)
+  #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_ECC_MAX                        (0x00000003)
+  #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_ECC_DEF                        (0x00000000)
+  #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_HORI_OFF                       (26)
+  #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_HORI_WID                       ( 1)
+  #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_HORI_MSK                       (0x04000000)
+  #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_HORI_MAX                       (0x00000001)
+  #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_HORI_DEF                       (0x00000000)
+  #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_HORIAddr_OFF                   (27)
+  #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_HORIAddr_WID                   ( 3)
+  #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_HORIAddr_MSK                   (0x38000000)
+  #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_HORIAddr_MAX                   (0x00000007)
+  #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_HORIAddr_DEF                   (0x00000000)
+
+#define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_REG                            (0x00005008)
+  #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_DIMM_A_Size_OFF                ( 0)
+  #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_DIMM_A_Size_WID                ( 8)
+  #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_DIMM_A_Size_MSK                (0x000000FF)
+  #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_DIMM_A_Size_MAX                (0x000000FF)
+  #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_DIMM_A_Size_DEF                (0x00000000)
+  #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_DIMM_B_Size_OFF                ( 8)
+  #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_DIMM_B_Size_WID                ( 8)
+  #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_DIMM_B_Size_MSK                (0x0000FF00)
+  #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_DIMM_B_Size_MAX                (0x000000FF)
+  #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_DIMM_B_Size_DEF                (0x00000000)
+  #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_DAS_OFF                        (16)
+  #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_DAS_WID                        ( 1)
+  #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_DAS_MSK                        (0x00010000)
+  #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_DAS_MAX                        (0x00000001)
+  #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_DAS_DEF                        (0x00000000)
+  #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_DANOR_OFF                      (17)
+  #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_DANOR_WID                      ( 1)
+  #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_DANOR_MSK                      (0x00020000)
+  #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_DANOR_MAX                      (0x00000001)
+  #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_DANOR_DEF                      (0x00000000)
+  #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_DBNOR_OFF                      (18)
+  #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_DBNOR_WID                      ( 1)
+  #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_DBNOR_MSK                      (0x00040000)
+  #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_DBNOR_MAX                      (0x00000001)
+  #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_DBNOR_DEF                      (0x00000000)
+  #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_DAW_OFF                        (19)
+  #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_DAW_WID                        ( 1)
+  #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_DAW_MSK                        (0x00080000)
+  #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_DAW_MAX                        (0x00000001)
+  #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_DAW_DEF                        (0x00000000)
+  #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_DBW_OFF                        (20)
+  #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_DBW_WID                        ( 1)
+  #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_DBW_MSK                        (0x00100000)
+  #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_DBW_MAX                        (0x00000001)
+  #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_DBW_DEF                        (0x00000000)
+  #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_RI_OFF                         (21)
+  #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_RI_WID                         ( 1)
+  #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_RI_MSK                         (0x00200000)
+  #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_RI_MAX                         (0x00000001)
+  #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_RI_DEF                         (0x00000001)
+  #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_Enh_Interleave_OFF             (22)
+  #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_Enh_Interleave_WID             ( 1)
+  #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_Enh_Interleave_MSK             (0x00400000)
+  #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_Enh_Interleave_MAX             (0x00000001)
+  #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_Enh_Interleave_DEF             (0x00000001)
+  #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_ECC_OFF                        (24)
+  #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_ECC_WID                        ( 2)
+  #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_ECC_MSK                        (0x03000000)
+  #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_ECC_MAX                        (0x00000003)
+  #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_ECC_DEF                        (0x00000000)
+  #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_HORI_OFF                       (26)
+  #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_HORI_WID                       ( 1)
+  #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_HORI_MSK                       (0x04000000)
+  #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_HORI_MAX                       (0x00000001)
+  #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_HORI_DEF                       (0x00000000)
+  #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_HORIAddr_OFF                   (27)
+  #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_HORIAddr_WID                   ( 3)
+  #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_HORIAddr_MSK                   (0x38000000)
+  #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_HORIAddr_MAX                   (0x00000007)
+  #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_HORIAddr_DEF                   (0x00000000)
+
+#define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_REG                            (0x0000500C)
+  #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_DIMM_A_Size_OFF                ( 0)
+  #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_DIMM_A_Size_WID                ( 8)
+  #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_DIMM_A_Size_MSK                (0x000000FF)
+  #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_DIMM_A_Size_MAX                (0x000000FF)
+  #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_DIMM_A_Size_DEF                (0x00000000)
+  #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_DIMM_B_Size_OFF                ( 8)
+  #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_DIMM_B_Size_WID                ( 8)
+  #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_DIMM_B_Size_MSK                (0x0000FF00)
+  #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_DIMM_B_Size_MAX                (0x000000FF)
+  #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_DIMM_B_Size_DEF                (0x00000000)
+  #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_DAS_OFF                        (16)
+  #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_DAS_WID                        ( 1)
+  #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_DAS_MSK                        (0x00010000)
+  #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_DAS_MAX                        (0x00000001)
+  #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_DAS_DEF                        (0x00000000)
+  #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_DANOR_OFF                      (17)
+  #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_DANOR_WID                      ( 1)
+  #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_DANOR_MSK                      (0x00020000)
+  #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_DANOR_MAX                      (0x00000001)
+  #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_DANOR_DEF                      (0x00000000)
+  #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_DBNOR_OFF                      (18)
+  #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_DBNOR_WID                      ( 1)
+  #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_DBNOR_MSK                      (0x00040000)
+  #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_DBNOR_MAX                      (0x00000001)
+  #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_DBNOR_DEF                      (0x00000000)
+  #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_DAW_OFF                        (19)
+  #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_DAW_WID                        ( 1)
+  #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_DAW_MSK                        (0x00080000)
+  #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_DAW_MAX                        (0x00000001)
+  #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_DAW_DEF                        (0x00000000)
+  #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_DBW_OFF                        (20)
+  #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_DBW_WID                        ( 1)
+  #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_DBW_MSK                        (0x00100000)
+  #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_DBW_MAX                        (0x00000001)
+  #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_DBW_DEF                        (0x00000000)
+  #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_RI_OFF                         (21)
+  #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_RI_WID                         ( 1)
+  #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_RI_MSK                         (0x00200000)
+  #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_RI_MAX                         (0x00000001)
+  #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_RI_DEF                         (0x00000001)
+  #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_Enh_Interleave_OFF             (22)
+  #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_Enh_Interleave_WID             ( 1)
+  #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_Enh_Interleave_MSK             (0x00400000)
+  #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_Enh_Interleave_MAX             (0x00000001)
+  #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_Enh_Interleave_DEF             (0x00000001)
+  #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_ECC_OFF                        (24)
+  #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_ECC_WID                        ( 2)
+  #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_ECC_MSK                        (0x03000000)
+  #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_ECC_MAX                        (0x00000003)
+  #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_ECC_DEF                        (0x00000000)
+  #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_HORI_OFF                       (26)
+  #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_HORI_WID                       ( 1)
+  #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_HORI_MSK                       (0x04000000)
+  #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_HORI_MAX                       (0x00000001)
+  #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_HORI_DEF                       (0x00000000)
+  #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_HORIAddr_OFF                   (27)
+  #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_HORIAddr_WID                   ( 3)
+  #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_HORIAddr_MSK                   (0x38000000)
+  #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_HORIAddr_MAX                   (0x00000007)
+  #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_HORIAddr_DEF                   (0x00000000)
+
+#define MCDECS_CR_MAD_ZR_MCMAIN_REG                                  (0x00005014)
+  #define MCDECS_CR_MAD_ZR_MCMAIN_OneC_OFF                             ( 0)
+  #define MCDECS_CR_MAD_ZR_MCMAIN_OneC_WID                             ( 8)
+  #define MCDECS_CR_MAD_ZR_MCMAIN_OneC_MSK                             (0x000000FF)
+  #define MCDECS_CR_MAD_ZR_MCMAIN_OneC_MAX                             (0x000000FF)
+  #define MCDECS_CR_MAD_ZR_MCMAIN_OneC_DEF                             (0x00000000)
+  #define MCDECS_CR_MAD_ZR_MCMAIN_ThreeC_OFF                           ( 8)
+  #define MCDECS_CR_MAD_ZR_MCMAIN_ThreeC_WID                           ( 8)
+  #define MCDECS_CR_MAD_ZR_MCMAIN_ThreeC_MSK                           (0x0000FF00)
+  #define MCDECS_CR_MAD_ZR_MCMAIN_ThreeC_MAX                           (0x000000FF)
+  #define MCDECS_CR_MAD_ZR_MCMAIN_ThreeC_DEF                           (0x00000000)
+  #define MCDECS_CR_MAD_ZR_MCMAIN_TwoBandC_OFF                         (16)
+  #define MCDECS_CR_MAD_ZR_MCMAIN_TwoBandC_WID                         ( 8)
+  #define MCDECS_CR_MAD_ZR_MCMAIN_TwoBandC_MSK                         (0x00FF0000)
+  #define MCDECS_CR_MAD_ZR_MCMAIN_TwoBandC_MAX                         (0x000000FF)
+  #define MCDECS_CR_MAD_ZR_MCMAIN_TwoBandC_DEF                         (0x00000000)
+  #define MCDECS_CR_MAD_ZR_MCMAIN_BandC_OFF                            (24)
+  #define MCDECS_CR_MAD_ZR_MCMAIN_BandC_WID                            ( 8)
+  #define MCDECS_CR_MAD_ZR_MCMAIN_BandC_MSK                            (0xFF000000)
+  #define MCDECS_CR_MAD_ZR_MCMAIN_BandC_MAX                            (0x000000FF)
+  #define MCDECS_CR_MAD_ZR_MCMAIN_BandC_DEF                            (0x00000000)
+
+#define MCDECS_CR_MCDECS_MISC_MCMAIN_REG                             (0x00005018)
+  #define MCDECS_CR_MCDECS_MISC_MCMAIN_spare_OFF                       ( 0)
+  #define MCDECS_CR_MCDECS_MISC_MCMAIN_spare_WID                       (23)
+  #define MCDECS_CR_MCDECS_MISC_MCMAIN_spare_MSK                       (0x007FFFFF)
+  #define MCDECS_CR_MCDECS_MISC_MCMAIN_spare_MAX                       (0x007FFFFF)
+  #define MCDECS_CR_MCDECS_MISC_MCMAIN_spare_DEF                       (0x00000000)
+  #define MCDECS_CR_MCDECS_MISC_MCMAIN_ovrd_pcu_sr_exit_OFF            (23)
+  #define MCDECS_CR_MCDECS_MISC_MCMAIN_ovrd_pcu_sr_exit_WID            ( 1)
+  #define MCDECS_CR_MCDECS_MISC_MCMAIN_ovrd_pcu_sr_exit_MSK            (0x00800000)
+  #define MCDECS_CR_MCDECS_MISC_MCMAIN_ovrd_pcu_sr_exit_MAX            (0x00000001)
+  #define MCDECS_CR_MCDECS_MISC_MCMAIN_ovrd_pcu_sr_exit_DEF            (0x00000000)
+  #define MCDECS_CR_MCDECS_MISC_MCMAIN_isoch_stall_pattern_OFF         (24)
+  #define MCDECS_CR_MCDECS_MISC_MCMAIN_isoch_stall_pattern_WID         ( 8)
+  #define MCDECS_CR_MCDECS_MISC_MCMAIN_isoch_stall_pattern_MSK         (0xFF000000)
+  #define MCDECS_CR_MCDECS_MISC_MCMAIN_isoch_stall_pattern_MAX         (0x000000FF)
+  #define MCDECS_CR_MCDECS_MISC_MCMAIN_isoch_stall_pattern_DEF         (0x00000000)
+
+#define MCDECS_CR_MCDECS_CBIT_MCMAIN_REG                             (0x0000501C)
+  #define MCDECS_CR_MCDECS_CBIT_MCMAIN_increase_rcomp_OFF              ( 0)
+  #define MCDECS_CR_MCDECS_CBIT_MCMAIN_increase_rcomp_WID              ( 1)
+  #define MCDECS_CR_MCDECS_CBIT_MCMAIN_increase_rcomp_MSK              (0x00000001)
+  #define MCDECS_CR_MCDECS_CBIT_MCMAIN_increase_rcomp_MAX              (0x00000001)
+  #define MCDECS_CR_MCDECS_CBIT_MCMAIN_increase_rcomp_DEF              (0x00000000)
+  #define MCDECS_CR_MCDECS_CBIT_MCMAIN_noa_on_ecc_OFF                  ( 1)
+  #define MCDECS_CR_MCDECS_CBIT_MCMAIN_noa_on_ecc_WID                  ( 1)
+  #define MCDECS_CR_MCDECS_CBIT_MCMAIN_noa_on_ecc_MSK                  (0x00000002)
+  #define MCDECS_CR_MCDECS_CBIT_MCMAIN_noa_on_ecc_MAX                  (0x00000001)
+  #define MCDECS_CR_MCDECS_CBIT_MCMAIN_noa_on_ecc_DEF                  (0x00000000)
+  #define MCDECS_CR_MCDECS_CBIT_MCMAIN_noa_demux_OFF                   ( 2)
+  #define MCDECS_CR_MCDECS_CBIT_MCMAIN_noa_demux_WID                   ( 1)
+  #define MCDECS_CR_MCDECS_CBIT_MCMAIN_noa_demux_MSK                   (0x00000004)
+  #define MCDECS_CR_MCDECS_CBIT_MCMAIN_noa_demux_MAX                   (0x00000001)
+  #define MCDECS_CR_MCDECS_CBIT_MCMAIN_noa_demux_DEF                   (0x00000000)
+  #define MCDECS_CR_MCDECS_CBIT_MCMAIN_noa_countctrl_OFF               ( 3)
+  #define MCDECS_CR_MCDECS_CBIT_MCMAIN_noa_countctrl_WID               ( 1)
+  #define MCDECS_CR_MCDECS_CBIT_MCMAIN_noa_countctrl_MSK               (0x00000008)
+  #define MCDECS_CR_MCDECS_CBIT_MCMAIN_noa_countctrl_MAX               (0x00000001)
+  #define MCDECS_CR_MCDECS_CBIT_MCMAIN_noa_countctrl_DEF               (0x00000000)
+  #define MCDECS_CR_MCDECS_CBIT_MCMAIN_psmi_freeze_pwm_counters_OFF    ( 8)
+  #define MCDECS_CR_MCDECS_CBIT_MCMAIN_psmi_freeze_pwm_counters_WID    ( 1)
+  #define MCDECS_CR_MCDECS_CBIT_MCMAIN_psmi_freeze_pwm_counters_MSK    (0x00000100)
+  #define MCDECS_CR_MCDECS_CBIT_MCMAIN_psmi_freeze_pwm_counters_MAX    (0x00000001)
+  #define MCDECS_CR_MCDECS_CBIT_MCMAIN_psmi_freeze_pwm_counters_DEF    (0x00000000)
+  #define MCDECS_CR_MCDECS_CBIT_MCMAIN_dis_lp_prefetch_OFF             (15)
+  #define MCDECS_CR_MCDECS_CBIT_MCMAIN_dis_lp_prefetch_WID             ( 1)
+  #define MCDECS_CR_MCDECS_CBIT_MCMAIN_dis_lp_prefetch_MSK             (0x00008000)
+  #define MCDECS_CR_MCDECS_CBIT_MCMAIN_dis_lp_prefetch_MAX             (0x00000001)
+  #define MCDECS_CR_MCDECS_CBIT_MCMAIN_dis_lp_prefetch_DEF             (0x00000000)
+  #define MCDECS_CR_MCDECS_CBIT_MCMAIN_dis_reg_clk_gate_OFF            (29)
+  #define MCDECS_CR_MCDECS_CBIT_MCMAIN_dis_reg_clk_gate_WID            ( 1)
+  #define MCDECS_CR_MCDECS_CBIT_MCMAIN_dis_reg_clk_gate_MSK            (0x20000000)
+  #define MCDECS_CR_MCDECS_CBIT_MCMAIN_dis_reg_clk_gate_MAX            (0x00000001)
+  #define MCDECS_CR_MCDECS_CBIT_MCMAIN_dis_reg_clk_gate_DEF            (0x00000000)
+  #define MCDECS_CR_MCDECS_CBIT_MCMAIN_dis_msg_clk_gate_OFF            (30)
+  #define MCDECS_CR_MCDECS_CBIT_MCMAIN_dis_msg_clk_gate_WID            ( 1)
+  #define MCDECS_CR_MCDECS_CBIT_MCMAIN_dis_msg_clk_gate_MSK            (0x40000000)
+  #define MCDECS_CR_MCDECS_CBIT_MCMAIN_dis_msg_clk_gate_MAX            (0x00000001)
+  #define MCDECS_CR_MCDECS_CBIT_MCMAIN_dis_msg_clk_gate_DEF            (0x00000001)
+  #define MCDECS_CR_MCDECS_CBIT_MCMAIN_dis_clk_gate_OFF                (31)
+  #define MCDECS_CR_MCDECS_CBIT_MCMAIN_dis_clk_gate_WID                ( 1)
+  #define MCDECS_CR_MCDECS_CBIT_MCMAIN_dis_clk_gate_MSK                (0x80000000)
+  #define MCDECS_CR_MCDECS_CBIT_MCMAIN_dis_clk_gate_MAX                (0x00000001)
+  #define MCDECS_CR_MCDECS_CBIT_MCMAIN_dis_clk_gate_DEF                (0x00000000)
+
+#define MCDECS_CR_SC_IS_CREDIT_MCMAIN_REG                            (0x00005020)
+  #define MCDECS_CR_SC_IS_CREDIT_MCMAIN_count_OFF                      ( 0)
+  #define MCDECS_CR_SC_IS_CREDIT_MCMAIN_count_WID                      ( 4)
+  #define MCDECS_CR_SC_IS_CREDIT_MCMAIN_count_MSK                      (0x0000000F)
+  #define MCDECS_CR_SC_IS_CREDIT_MCMAIN_count_MAX                      (0x0000000F)
+  #define MCDECS_CR_SC_IS_CREDIT_MCMAIN_count_DEF                      (0x00000008)
+
+#define MCDECS_CR_CHANNEL_HASH_MCMAIN_REG                            (0x00005024)
+  #define MCDECS_CR_CHANNEL_HASH_MCMAIN_Mask_OFF                       ( 0)
+  #define MCDECS_CR_CHANNEL_HASH_MCMAIN_Mask_WID                       (14)
+  #define MCDECS_CR_CHANNEL_HASH_MCMAIN_Mask_MSK                       (0x00003FFF)
+  #define MCDECS_CR_CHANNEL_HASH_MCMAIN_Mask_MAX                       (0x00003FFF)
+  #define MCDECS_CR_CHANNEL_HASH_MCMAIN_Mask_DEF                       (0x00000000)
+  #define MCDECS_CR_CHANNEL_HASH_MCMAIN_LSB_mask_bit_OFF               (21)
+  #define MCDECS_CR_CHANNEL_HASH_MCMAIN_LSB_mask_bit_WID               ( 2)
+  #define MCDECS_CR_CHANNEL_HASH_MCMAIN_LSB_mask_bit_MSK               (0x00600000)
+  #define MCDECS_CR_CHANNEL_HASH_MCMAIN_LSB_mask_bit_MAX               (0x00000003)
+  #define MCDECS_CR_CHANNEL_HASH_MCMAIN_LSB_mask_bit_DEF               (0x00000000)
+  #define MCDECS_CR_CHANNEL_HASH_MCMAIN_Enable_OFF                     (23)
+  #define MCDECS_CR_CHANNEL_HASH_MCMAIN_Enable_WID                     ( 1)
+  #define MCDECS_CR_CHANNEL_HASH_MCMAIN_Enable_MSK                     (0x00800000)
+  #define MCDECS_CR_CHANNEL_HASH_MCMAIN_Enable_MAX                     (0x00000001)
+  #define MCDECS_CR_CHANNEL_HASH_MCMAIN_Enable_DEF                     (0x00000000)
+
+#define MCDECS_CR_MC_INIT_STATE_G_MCMAIN_REG                         (0x00005030)
+  #define MCDECS_CR_MC_INIT_STATE_G_MCMAIN_pu_mrc_done_OFF             ( 0)
+  #define MCDECS_CR_MC_INIT_STATE_G_MCMAIN_pu_mrc_done_WID             ( 1)
+  #define MCDECS_CR_MC_INIT_STATE_G_MCMAIN_pu_mrc_done_MSK             (0x00000001)
+  #define MCDECS_CR_MC_INIT_STATE_G_MCMAIN_pu_mrc_done_MAX             (0x00000001)
+  #define MCDECS_CR_MC_INIT_STATE_G_MCMAIN_pu_mrc_done_DEF             (0x00000000)
+  #define MCDECS_CR_MC_INIT_STATE_G_MCMAIN_ddr_reset_OFF               ( 1)
+  #define MCDECS_CR_MC_INIT_STATE_G_MCMAIN_ddr_reset_WID               ( 1)
+  #define MCDECS_CR_MC_INIT_STATE_G_MCMAIN_ddr_reset_MSK               (0x00000002)
+  #define MCDECS_CR_MC_INIT_STATE_G_MCMAIN_ddr_reset_MAX               (0x00000001)
+  #define MCDECS_CR_MC_INIT_STATE_G_MCMAIN_ddr_reset_DEF               (0x00000001)
+  #define MCDECS_CR_MC_INIT_STATE_G_MCMAIN_refresh_enable_OFF          ( 3)
+  #define MCDECS_CR_MC_INIT_STATE_G_MCMAIN_refresh_enable_WID          ( 1)
+  #define MCDECS_CR_MC_INIT_STATE_G_MCMAIN_refresh_enable_MSK          (0x00000008)
+  #define MCDECS_CR_MC_INIT_STATE_G_MCMAIN_refresh_enable_MAX          (0x00000001)
+  #define MCDECS_CR_MC_INIT_STATE_G_MCMAIN_refresh_enable_DEF          (0x00000000)
+  #define MCDECS_CR_MC_INIT_STATE_G_MCMAIN_mc_init_done_ack_OFF        ( 5)
+  #define MCDECS_CR_MC_INIT_STATE_G_MCMAIN_mc_init_done_ack_WID        ( 1)
+  #define MCDECS_CR_MC_INIT_STATE_G_MCMAIN_mc_init_done_ack_MSK        (0x00000020)
+  #define MCDECS_CR_MC_INIT_STATE_G_MCMAIN_mc_init_done_ack_MAX        (0x00000001)
+  #define MCDECS_CR_MC_INIT_STATE_G_MCMAIN_mc_init_done_ack_DEF        (0x00000000)
+  #define MCDECS_CR_MC_INIT_STATE_G_MCMAIN_mrc_done_OFF                ( 7)
+  #define MCDECS_CR_MC_INIT_STATE_G_MCMAIN_mrc_done_WID                ( 1)
+  #define MCDECS_CR_MC_INIT_STATE_G_MCMAIN_mrc_done_MSK                (0x00000080)
+  #define MCDECS_CR_MC_INIT_STATE_G_MCMAIN_mrc_done_MAX                (0x00000001)
+  #define MCDECS_CR_MC_INIT_STATE_G_MCMAIN_mrc_done_DEF                (0x00000000)
+  #define MCDECS_CR_MC_INIT_STATE_G_MCMAIN_safe_sr_OFF                 ( 8)
+  #define MCDECS_CR_MC_INIT_STATE_G_MCMAIN_safe_sr_WID                 ( 1)
+  #define MCDECS_CR_MC_INIT_STATE_G_MCMAIN_safe_sr_MSK                 (0x00000100)
+  #define MCDECS_CR_MC_INIT_STATE_G_MCMAIN_safe_sr_MAX                 (0x00000001)
+  #define MCDECS_CR_MC_INIT_STATE_G_MCMAIN_safe_sr_DEF                 (0x00000001)
+  #define MCDECS_CR_MC_INIT_STATE_G_MCMAIN_HVM_Gate_DDR_Reset_OFF      (10)
+  #define MCDECS_CR_MC_INIT_STATE_G_MCMAIN_HVM_Gate_DDR_Reset_WID      ( 1)
+  #define MCDECS_CR_MC_INIT_STATE_G_MCMAIN_HVM_Gate_DDR_Reset_MSK      (0x00000400)
+  #define MCDECS_CR_MC_INIT_STATE_G_MCMAIN_HVM_Gate_DDR_Reset_MAX      (0x00000001)
+  #define MCDECS_CR_MC_INIT_STATE_G_MCMAIN_HVM_Gate_DDR_Reset_DEF      (0x00000000)
+  #define MCDECS_CR_MC_INIT_STATE_G_MCMAIN_dclk_enable_OFF             (22)
+  #define MCDECS_CR_MC_INIT_STATE_G_MCMAIN_dclk_enable_WID             ( 1)
+  #define MCDECS_CR_MC_INIT_STATE_G_MCMAIN_dclk_enable_MSK             (0x00400000)
+  #define MCDECS_CR_MC_INIT_STATE_G_MCMAIN_dclk_enable_MAX             (0x00000001)
+  #define MCDECS_CR_MC_INIT_STATE_G_MCMAIN_dclk_enable_DEF             (0x00000000)
+  #define MCDECS_CR_MC_INIT_STATE_G_MCMAIN_reset_io_OFF                (23)
+  #define MCDECS_CR_MC_INIT_STATE_G_MCMAIN_reset_io_WID                ( 1)
+  #define MCDECS_CR_MC_INIT_STATE_G_MCMAIN_reset_io_MSK                (0x00800000)
+  #define MCDECS_CR_MC_INIT_STATE_G_MCMAIN_reset_io_MAX                (0x00000001)
+  #define MCDECS_CR_MC_INIT_STATE_G_MCMAIN_reset_io_DEF                (0x00000000)
+
+#define MCDECS_CR_MRC_REVISION_MCMAIN_REG                            (0x00005034)
+  #define MCDECS_CR_MRC_REVISION_MCMAIN_REVISION_OFF                   ( 0)
+  #define MCDECS_CR_MRC_REVISION_MCMAIN_REVISION_WID                   (32)
+  #define MCDECS_CR_MRC_REVISION_MCMAIN_REVISION_MSK                   (0xFFFFFFFF)
+  #define MCDECS_CR_MRC_REVISION_MCMAIN_REVISION_MAX                   (0xFFFFFFFF)
+  #define MCDECS_CR_MRC_REVISION_MCMAIN_REVISION_DEF                   (0x00000000)
+
+#define MCDECS_CR_PWM_GT_REQCOUNT_MCMAIN_REG                         (0x00005040)
+  #define MCDECS_CR_PWM_GT_REQCOUNT_MCMAIN_count_OFF                   ( 0)
+  #define MCDECS_CR_PWM_GT_REQCOUNT_MCMAIN_count_WID                   (32)
+  #define MCDECS_CR_PWM_GT_REQCOUNT_MCMAIN_count_MSK                   (0xFFFFFFFF)
+  #define MCDECS_CR_PWM_GT_REQCOUNT_MCMAIN_count_MAX                   (0xFFFFFFFF)
+  #define MCDECS_CR_PWM_GT_REQCOUNT_MCMAIN_count_DEF                   (0x00000000)
+
+#define MCDECS_CR_PWM_IA_REQCOUNT_MCMAIN_REG                         (0x00005044)
+  #define MCDECS_CR_PWM_IA_REQCOUNT_MCMAIN_count_OFF                   ( 0)
+  #define MCDECS_CR_PWM_IA_REQCOUNT_MCMAIN_count_WID                   (32)
+  #define MCDECS_CR_PWM_IA_REQCOUNT_MCMAIN_count_MSK                   (0xFFFFFFFF)
+  #define MCDECS_CR_PWM_IA_REQCOUNT_MCMAIN_count_MAX                   (0xFFFFFFFF)
+  #define MCDECS_CR_PWM_IA_REQCOUNT_MCMAIN_count_DEF                   (0x00000000)
+
+#define MCDECS_CR_PWM_IO_REQCOUNT_MCMAIN_REG                         (0x00005048)
+  #define MCDECS_CR_PWM_IO_REQCOUNT_MCMAIN_count_OFF                   ( 0)
+  #define MCDECS_CR_PWM_IO_REQCOUNT_MCMAIN_count_WID                   (32)
+  #define MCDECS_CR_PWM_IO_REQCOUNT_MCMAIN_count_MSK                   (0xFFFFFFFF)
+  #define MCDECS_CR_PWM_IO_REQCOUNT_MCMAIN_count_MAX                   (0xFFFFFFFF)
+  #define MCDECS_CR_PWM_IO_REQCOUNT_MCMAIN_count_DEF                   (0x00000000)
+
+#define MCDECS_CR_PWM_RDDATA_COUNT_MCMAIN_REG                        (0x00005050)
+  #define MCDECS_CR_PWM_RDDATA_COUNT_MCMAIN_count_OFF                  ( 0)
+  #define MCDECS_CR_PWM_RDDATA_COUNT_MCMAIN_count_WID                  (32)
+  #define MCDECS_CR_PWM_RDDATA_COUNT_MCMAIN_count_MSK                  (0xFFFFFFFF)
+  #define MCDECS_CR_PWM_RDDATA_COUNT_MCMAIN_count_MAX                  (0xFFFFFFFF)
+  #define MCDECS_CR_PWM_RDDATA_COUNT_MCMAIN_count_DEF                  (0x00000000)
+
+#define MCDECS_CR_PWM_WRDATA_COUNT_MCMAIN_REG                        (0x00005054)
+  #define MCDECS_CR_PWM_WRDATA_COUNT_MCMAIN_count_OFF                  ( 0)
+  #define MCDECS_CR_PWM_WRDATA_COUNT_MCMAIN_count_WID                  (32)
+  #define MCDECS_CR_PWM_WRDATA_COUNT_MCMAIN_count_MSK                  (0xFFFFFFFF)
+  #define MCDECS_CR_PWM_WRDATA_COUNT_MCMAIN_count_MAX                  (0xFFFFFFFF)
+  #define MCDECS_CR_PWM_WRDATA_COUNT_MCMAIN_count_DEF                  (0x00000000)
+
+#define MCDECS_CR_PWM_COMMAND_COUNT_MCMAIN_REG                       (0x00005058)
+  #define MCDECS_CR_PWM_COMMAND_COUNT_MCMAIN_count_OFF                 ( 0)
+  #define MCDECS_CR_PWM_COMMAND_COUNT_MCMAIN_count_WID                 (32)
+  #define MCDECS_CR_PWM_COMMAND_COUNT_MCMAIN_count_MSK                 (0xFFFFFFFF)
+  #define MCDECS_CR_PWM_COMMAND_COUNT_MCMAIN_count_MAX                 (0xFFFFFFFF)
+  #define MCDECS_CR_PWM_COMMAND_COUNT_MCMAIN_count_DEF                 (0x00000000)
+
+#define MCDECS_CR_PM_SREF_CONFIG_MCMAIN_REG                          (0x00005060)
+  #define MCDECS_CR_PM_SREF_CONFIG_MCMAIN_Idle_timer_OFF               ( 0)
+  #define MCDECS_CR_PM_SREF_CONFIG_MCMAIN_Idle_timer_WID               (16)
+  #define MCDECS_CR_PM_SREF_CONFIG_MCMAIN_Idle_timer_MSK               (0x0000FFFF)
+  #define MCDECS_CR_PM_SREF_CONFIG_MCMAIN_Idle_timer_MAX               (0x0000FFFF)
+  #define MCDECS_CR_PM_SREF_CONFIG_MCMAIN_Idle_timer_DEF               (0x00000200)
+  #define MCDECS_CR_PM_SREF_CONFIG_MCMAIN_SR_Enable_OFF                (16)
+  #define MCDECS_CR_PM_SREF_CONFIG_MCMAIN_SR_Enable_WID                ( 1)
+  #define MCDECS_CR_PM_SREF_CONFIG_MCMAIN_SR_Enable_MSK                (0x00010000)
+  #define MCDECS_CR_PM_SREF_CONFIG_MCMAIN_SR_Enable_MAX                (0x00000001)
+  #define MCDECS_CR_PM_SREF_CONFIG_MCMAIN_SR_Enable_DEF                (0x00000001)
+
+#define MCDECS_CR_MCI_CONFIG_MCMAIN_REG                              (0x00005070)
+  #define MCDECS_CR_MCI_CONFIG_MCMAIN_Ch_dir_OFF                       ( 0)
+  #define MCDECS_CR_MCI_CONFIG_MCMAIN_Ch_dir_WID                       ( 4)
+  #define MCDECS_CR_MCI_CONFIG_MCMAIN_Ch_dir_MSK                       (0x0000000F)
+  #define MCDECS_CR_MCI_CONFIG_MCMAIN_Ch_dir_MAX                       (0x0000000F)
+  #define MCDECS_CR_MCI_CONFIG_MCMAIN_Ch_dir_DEF                       (0x00000000)
+  #define MCDECS_CR_MCI_CONFIG_MCMAIN_MCI_clk_div_OFF                  ( 8)
+  #define MCDECS_CR_MCI_CONFIG_MCMAIN_MCI_clk_div_WID                  (10)
+  #define MCDECS_CR_MCI_CONFIG_MCMAIN_MCI_clk_div_MSK                  (0x0003FF00)
+  #define MCDECS_CR_MCI_CONFIG_MCMAIN_MCI_clk_div_MAX                  (0x000003FF)
+  #define MCDECS_CR_MCI_CONFIG_MCMAIN_MCI_clk_div_DEF                  (0x00000000)
+
+#define MCDECS_CR_STALL_DRAIN_MCMAIN_REG                             (0x00005074)
+  #define MCDECS_CR_STALL_DRAIN_MCMAIN_stall_until_drain_OFF           ( 0)
+  #define MCDECS_CR_STALL_DRAIN_MCMAIN_stall_until_drain_WID           ( 1)
+  #define MCDECS_CR_STALL_DRAIN_MCMAIN_stall_until_drain_MSK           (0x00000001)
+  #define MCDECS_CR_STALL_DRAIN_MCMAIN_stall_until_drain_MAX           (0x00000001)
+  #define MCDECS_CR_STALL_DRAIN_MCMAIN_stall_until_drain_DEF           (0x00000000)
+  #define MCDECS_CR_STALL_DRAIN_MCMAIN_stall_input_OFF                 ( 1)
+  #define MCDECS_CR_STALL_DRAIN_MCMAIN_stall_input_WID                 ( 1)
+  #define MCDECS_CR_STALL_DRAIN_MCMAIN_stall_input_MSK                 (0x00000002)
+  #define MCDECS_CR_STALL_DRAIN_MCMAIN_stall_input_MAX                 (0x00000001)
+  #define MCDECS_CR_STALL_DRAIN_MCMAIN_stall_input_DEF                 (0x00000000)
+  #define MCDECS_CR_STALL_DRAIN_MCMAIN_mc_drained_OFF                  ( 4)
+  #define MCDECS_CR_STALL_DRAIN_MCMAIN_mc_drained_WID                  ( 1)
+  #define MCDECS_CR_STALL_DRAIN_MCMAIN_mc_drained_MSK                  (0x00000010)
+  #define MCDECS_CR_STALL_DRAIN_MCMAIN_mc_drained_MAX                  (0x00000001)
+  #define MCDECS_CR_STALL_DRAIN_MCMAIN_mc_drained_DEF                  (0x00000000)
+  #define MCDECS_CR_STALL_DRAIN_MCMAIN_sr_state_OFF                    ( 8)
+  #define MCDECS_CR_STALL_DRAIN_MCMAIN_sr_state_WID                    ( 2)
+  #define MCDECS_CR_STALL_DRAIN_MCMAIN_sr_state_MSK                    (0x00000300)
+  #define MCDECS_CR_STALL_DRAIN_MCMAIN_sr_state_MAX                    (0x00000003)
+  #define MCDECS_CR_STALL_DRAIN_MCMAIN_sr_state_DEF                    (0x00000000)
+
+#define MCDECS_CR_QUEUE_CREDIT_C_MCMAIN_REG                          (0x00005080)
+  #define MCDECS_CR_QUEUE_CREDIT_C_MCMAIN_RPQ_count_OFF                ( 0)
+  #define MCDECS_CR_QUEUE_CREDIT_C_MCMAIN_RPQ_count_WID                ( 5)
+  #define MCDECS_CR_QUEUE_CREDIT_C_MCMAIN_RPQ_count_MSK                (0x0000001F)
+  #define MCDECS_CR_QUEUE_CREDIT_C_MCMAIN_RPQ_count_MAX                (0x0000001F)
+  #define MCDECS_CR_QUEUE_CREDIT_C_MCMAIN_RPQ_count_DEF                (0x0000001C)
+  #define MCDECS_CR_QUEUE_CREDIT_C_MCMAIN_WPQ_count_OFF                ( 8)
+  #define MCDECS_CR_QUEUE_CREDIT_C_MCMAIN_WPQ_count_WID                ( 7)
+  #define MCDECS_CR_QUEUE_CREDIT_C_MCMAIN_WPQ_count_MSK                (0x00007F00)
+  #define MCDECS_CR_QUEUE_CREDIT_C_MCMAIN_WPQ_count_MAX                (0x0000007F)
+  #define MCDECS_CR_QUEUE_CREDIT_C_MCMAIN_WPQ_count_DEF                (0x00000040)
+
+#define MCDECS_CR_RCOMP_TIMER_MCMAIN_REG                             (0x00005084)
+  #define MCDECS_CR_RCOMP_TIMER_MCMAIN_count_OFF                       ( 0)
+  #define MCDECS_CR_RCOMP_TIMER_MCMAIN_count_WID                       (16)
+  #define MCDECS_CR_RCOMP_TIMER_MCMAIN_count_MSK                       (0x0000FFFF)
+  #define MCDECS_CR_RCOMP_TIMER_MCMAIN_count_MAX                       (0x0000FFFF)
+  #define MCDECS_CR_RCOMP_TIMER_MCMAIN_count_DEF                       (0x00000CFF)
+  #define MCDECS_CR_RCOMP_TIMER_MCMAIN_First_Rcomp_done_OFF            (16)
+  #define MCDECS_CR_RCOMP_TIMER_MCMAIN_First_Rcomp_done_WID            ( 1)
+  #define MCDECS_CR_RCOMP_TIMER_MCMAIN_First_Rcomp_done_MSK            (0x00010000)
+  #define MCDECS_CR_RCOMP_TIMER_MCMAIN_First_Rcomp_done_MAX            (0x00000001)
+  #define MCDECS_CR_RCOMP_TIMER_MCMAIN_First_Rcomp_done_DEF            (0x00000000)
+
+#define MCDECS_CR_ECC_INJ_ADDR_COMPARE_MCMAIN_REG                    (0x00005090)
+  #define MCDECS_CR_ECC_INJ_ADDR_COMPARE_MCMAIN_Address_OFF            ( 0)
+  #define MCDECS_CR_ECC_INJ_ADDR_COMPARE_MCMAIN_Address_WID            (32)
+  #define MCDECS_CR_ECC_INJ_ADDR_COMPARE_MCMAIN_Address_MSK            (0xFFFFFFFF)
+  #define MCDECS_CR_ECC_INJ_ADDR_COMPARE_MCMAIN_Address_MAX            (0xFFFFFFFF)
+  #define MCDECS_CR_ECC_INJ_ADDR_COMPARE_MCMAIN_Address_DEF            (0x00000000)
+
+#define MCDECS_CR_ECC_INJ_ADDR_MASK_MCMAIN_REG                       (0x00005094)
+  #define MCDECS_CR_ECC_INJ_ADDR_MASK_MCMAIN_Mask_OFF                  ( 0)
+  #define MCDECS_CR_ECC_INJ_ADDR_MASK_MCMAIN_Mask_WID                  (32)
+  #define MCDECS_CR_ECC_INJ_ADDR_MASK_MCMAIN_Mask_MSK                  (0xFFFFFFFF)
+  #define MCDECS_CR_ECC_INJ_ADDR_MASK_MCMAIN_Mask_MAX                  (0xFFFFFFFF)
+  #define MCDECS_CR_ECC_INJ_ADDR_MASK_MCMAIN_Mask_DEF                  (0xFFFFFFFF)
+
+#define MCDECS_CR_VISA_CTL_MCDECS_MCMAIN_REG                         (0x000050A0)
+  #define MCDECS_CR_VISA_CTL_MCDECS_MCMAIN_Data_OFF                    ( 0)
+  #define MCDECS_CR_VISA_CTL_MCDECS_MCMAIN_Data_WID                    (18)
+  #define MCDECS_CR_VISA_CTL_MCDECS_MCMAIN_Data_MSK                    (0x0003FFFF)
+  #define MCDECS_CR_VISA_CTL_MCDECS_MCMAIN_Data_MAX                    (0x0003FFFF)
+  #define MCDECS_CR_VISA_CTL_MCDECS_MCMAIN_Data_DEF                    (0x00000000)
+  #define MCDECS_CR_VISA_CTL_MCDECS_MCMAIN_VORANGE_OFF                 (31)
+  #define MCDECS_CR_VISA_CTL_MCDECS_MCMAIN_VORANGE_WID                 ( 1)
+  #define MCDECS_CR_VISA_CTL_MCDECS_MCMAIN_VORANGE_MSK                 (0x80000000)
+  #define MCDECS_CR_VISA_CTL_MCDECS_MCMAIN_VORANGE_MAX                 (0x00000001)
+  #define MCDECS_CR_VISA_CTL_MCDECS_MCMAIN_VORANGE_DEF                 (0x00000000)
+
+#define MCDECS_CR_VISA_XBAR_MCDECS_MCMAIN_REG                        (0x000050A4)
+  #define MCDECS_CR_VISA_XBAR_MCDECS_MCMAIN_Data_OFF                   ( 0)
+  #define MCDECS_CR_VISA_XBAR_MCDECS_MCMAIN_Data_WID                   (32)
+  #define MCDECS_CR_VISA_XBAR_MCDECS_MCMAIN_Data_MSK                   (0xFFFFFFFF)
+  #define MCDECS_CR_VISA_XBAR_MCDECS_MCMAIN_Data_MAX                   (0xFFFFFFFF)
+  #define MCDECS_CR_VISA_XBAR_MCDECS_MCMAIN_Data_DEF                   (0x76543210)
+
+#define MCDECS_CR_MC_LOCK_MCMAIN_REG                                 (0x000050FC)
+  #define MCDECS_CR_MC_LOCK_MCMAIN_lock_addr_map_OFF                   ( 0)
+  #define MCDECS_CR_MC_LOCK_MCMAIN_lock_addr_map_WID                   ( 1)
+  #define MCDECS_CR_MC_LOCK_MCMAIN_lock_addr_map_MSK                   (0x00000001)
+  #define MCDECS_CR_MC_LOCK_MCMAIN_lock_addr_map_MAX                   (0x00000001)
+  #define MCDECS_CR_MC_LOCK_MCMAIN_lock_addr_map_DEF                   (0x00000000)
+  #define MCDECS_CR_MC_LOCK_MCMAIN_lock_mc_config_OFF                  ( 1)
+  #define MCDECS_CR_MC_LOCK_MCMAIN_lock_mc_config_WID                  ( 1)
+  #define MCDECS_CR_MC_LOCK_MCMAIN_lock_mc_config_MSK                  (0x00000002)
+  #define MCDECS_CR_MC_LOCK_MCMAIN_lock_mc_config_MAX                  (0x00000001)
+  #define MCDECS_CR_MC_LOCK_MCMAIN_lock_mc_config_DEF                  (0x00000000)
+  #define MCDECS_CR_MC_LOCK_MCMAIN_lock_iosav_init_OFF                 ( 2)
+  #define MCDECS_CR_MC_LOCK_MCMAIN_lock_iosav_init_WID                 ( 1)
+  #define MCDECS_CR_MC_LOCK_MCMAIN_lock_iosav_init_MSK                 (0x00000004)
+  #define MCDECS_CR_MC_LOCK_MCMAIN_lock_iosav_init_MAX                 (0x00000001)
+  #define MCDECS_CR_MC_LOCK_MCMAIN_lock_iosav_init_DEF                 (0x00000000)
+  #define MCDECS_CR_MC_LOCK_MCMAIN_lock_pwr_mngment_OFF                ( 3)
+  #define MCDECS_CR_MC_LOCK_MCMAIN_lock_pwr_mngment_WID                ( 1)
+  #define MCDECS_CR_MC_LOCK_MCMAIN_lock_pwr_mngment_MSK                (0x00000008)
+  #define MCDECS_CR_MC_LOCK_MCMAIN_lock_pwr_mngment_MAX                (0x00000001)
+  #define MCDECS_CR_MC_LOCK_MCMAIN_lock_pwr_mngment_DEF                (0x00000000)
+  #define MCDECS_CR_MC_LOCK_MCMAIN_lock_mc_dft_OFF                     ( 7)
+  #define MCDECS_CR_MC_LOCK_MCMAIN_lock_mc_dft_WID                     ( 1)
+  #define MCDECS_CR_MC_LOCK_MCMAIN_lock_mc_dft_MSK                     (0x00000080)
+  #define MCDECS_CR_MC_LOCK_MCMAIN_lock_mc_dft_MAX                     (0x00000001)
+  #define MCDECS_CR_MC_LOCK_MCMAIN_lock_mc_dft_DEF                     (0x00000000)
+
+#define MCHBAR_CH0_CR_TC_BANK_REG                                    (0x00004000)
+  #define MCHBAR_CH0_CR_TC_BANK_tRCD_OFF                               ( 0)
+  #define MCHBAR_CH0_CR_TC_BANK_tRCD_WID                               ( 5)
+  #define MCHBAR_CH0_CR_TC_BANK_tRCD_MSK                               (0x0000001F)
+  #define MCHBAR_CH0_CR_TC_BANK_tRCD_MAX                               (0x0000001F)
+  #define MCHBAR_CH0_CR_TC_BANK_tRCD_DEF                               (0x00000006)
+  #define MCHBAR_CH0_CR_TC_BANK_tRP_OFF                                ( 5)
+  #define MCHBAR_CH0_CR_TC_BANK_tRP_WID                                ( 5)
+  #define MCHBAR_CH0_CR_TC_BANK_tRP_MSK                                (0x000003E0)
+  #define MCHBAR_CH0_CR_TC_BANK_tRP_MAX                                (0x0000001F)
+  #define MCHBAR_CH0_CR_TC_BANK_tRP_DEF                                (0x00000006)
+  #define MCHBAR_CH0_CR_TC_BANK_tRAS_OFF                               (10)
+  #define MCHBAR_CH0_CR_TC_BANK_tRAS_WID                               ( 6)
+  #define MCHBAR_CH0_CR_TC_BANK_tRAS_MSK                               (0x0000FC00)
+  #define MCHBAR_CH0_CR_TC_BANK_tRAS_MAX                               (0x0000003F)
+  #define MCHBAR_CH0_CR_TC_BANK_tRAS_DEF                               (0x00000014)
+  #define MCHBAR_CH0_CR_TC_BANK_tRDPRE_OFF                             (16)
+  #define MCHBAR_CH0_CR_TC_BANK_tRDPRE_WID                             ( 4)
+  #define MCHBAR_CH0_CR_TC_BANK_tRDPRE_MSK                             (0x000F0000)
+  #define MCHBAR_CH0_CR_TC_BANK_tRDPRE_MAX                             (0x0000000F)
+  #define MCHBAR_CH0_CR_TC_BANK_tRDPRE_DEF                             (0x00000004)
+  #define MCHBAR_CH0_CR_TC_BANK_tWRPRE_OFF                             (20)
+  #define MCHBAR_CH0_CR_TC_BANK_tWRPRE_WID                             ( 6)
+  #define MCHBAR_CH0_CR_TC_BANK_tWRPRE_MSK                             (0x03F00000)
+  #define MCHBAR_CH0_CR_TC_BANK_tWRPRE_MAX                             (0x0000003F)
+  #define MCHBAR_CH0_CR_TC_BANK_tWRPRE_DEF                             (0x00000004)
+  #define MCHBAR_CH0_CR_TC_BANK_tRRD_OFF                               (26)
+  #define MCHBAR_CH0_CR_TC_BANK_tRRD_WID                               ( 4)
+  #define MCHBAR_CH0_CR_TC_BANK_tRRD_MSK                               (0x3C000000)
+  #define MCHBAR_CH0_CR_TC_BANK_tRRD_MAX                               (0x0000000F)
+  #define MCHBAR_CH0_CR_TC_BANK_tRRD_DEF                               (0x00000004)
+  #define MCHBAR_CH0_CR_TC_BANK_tRPab_ext_OFF                          (30)
+  #define MCHBAR_CH0_CR_TC_BANK_tRPab_ext_WID                          ( 2)
+  #define MCHBAR_CH0_CR_TC_BANK_tRPab_ext_MSK                          (0xC0000000)
+  #define MCHBAR_CH0_CR_TC_BANK_tRPab_ext_MAX                          (0x00000003)
+  #define MCHBAR_CH0_CR_TC_BANK_tRPab_ext_DEF                          (0x00000000)
+
+#define MCHBAR_CH0_CR_TC_BANK_RANK_A_REG                             (0x00004004)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_A_tCKE_OFF                        ( 0)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_A_tCKE_WID                        ( 4)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_A_tCKE_MSK                        (0x0000000F)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_A_tCKE_MAX                        (0x0000000F)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_A_tCKE_DEF                        (0x00000003)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_A_tFAW_OFF                        ( 4)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_A_tFAW_WID                        ( 8)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_A_tFAW_MSK                        (0x00000FF0)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_A_tFAW_MAX                        (0x000000FF)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_A_tFAW_DEF                        (0x00000010)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_A_tRDRD_OFF                       (12)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_A_tRDRD_WID                       ( 3)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_A_tRDRD_MSK                       (0x00007000)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_A_tRDRD_MAX                       (0x00000007)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_A_tRDRD_DEF                       (0x00000004)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_A_tRDRD_dr_OFF                    (15)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_A_tRDRD_dr_WID                    ( 4)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_A_tRDRD_dr_MSK                    (0x00078000)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_A_tRDRD_dr_MAX                    (0x0000000F)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_A_tRDRD_dr_DEF                    (0x00000004)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_A_tRDRD_dd_OFF                    (19)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_A_tRDRD_dd_WID                    ( 4)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_A_tRDRD_dd_MSK                    (0x00780000)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_A_tRDRD_dd_MAX                    (0x0000000F)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_A_tRDRD_dd_DEF                    (0x00000004)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_A_tRDPDEN_OFF                     (23)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_A_tRDPDEN_WID                     ( 5)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_A_tRDPDEN_MSK                     (0x0F800000)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_A_tRDPDEN_MAX                     (0x0000001F)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_A_tRDPDEN_DEF                     (0x00000004)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_A_CMD_3st_OFF                     (29)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_A_CMD_3st_WID                     ( 1)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_A_CMD_3st_MSK                     (0x20000000)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_A_CMD_3st_MAX                     (0x00000001)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_A_CMD_3st_DEF                     (0x00000000)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_A_CMD_stretch_OFF                 (30)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_A_CMD_stretch_WID                 ( 2)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_A_CMD_stretch_MSK                 (0xC0000000)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_A_CMD_stretch_MAX                 (0x00000003)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_A_CMD_stretch_DEF                 (0x00000002)
+
+#define MCHBAR_CH0_CR_TC_BANK_RANK_B_REG                             (0x00004008)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_B_tWRRD_OFF                       ( 0)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_B_tWRRD_WID                       ( 6)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_B_tWRRD_MSK                       (0x0000003F)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_B_tWRRD_MAX                       (0x0000003F)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_B_tWRRD_DEF                       (0x00000005)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_B_tWRRD_dr_OFF                    ( 6)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_B_tWRRD_dr_WID                    ( 4)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_B_tWRRD_dr_MSK                    (0x000003C0)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_B_tWRRD_dr_MAX                    (0x0000000F)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_B_tWRRD_dr_DEF                    (0x00000005)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_B_tWRRD_dd_OFF                    (10)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_B_tWRRD_dd_WID                    ( 4)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_B_tWRRD_dd_MSK                    (0x00003C00)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_B_tWRRD_dd_MAX                    (0x0000000F)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_B_tWRRD_dd_DEF                    (0x00000005)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_B_tWRWR_OFF                       (14)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_B_tWRWR_WID                       ( 3)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_B_tWRWR_MSK                       (0x0001C000)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_B_tWRWR_MAX                       (0x00000007)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_B_tWRWR_DEF                       (0x00000005)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_B_tWRWR_dr_OFF                    (17)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_B_tWRWR_dr_WID                    ( 4)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_B_tWRWR_dr_MSK                    (0x001E0000)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_B_tWRWR_dr_MAX                    (0x0000000F)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_B_tWRWR_dr_DEF                    (0x00000005)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_B_tWRWR_dd_OFF                    (21)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_B_tWRWR_dd_WID                    ( 4)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_B_tWRWR_dd_MSK                    (0x01E00000)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_B_tWRWR_dd_MAX                    (0x0000000F)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_B_tWRWR_dd_DEF                    (0x00000005)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_B_tWRPDEN_OFF                     (25)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_B_tWRPDEN_WID                     ( 6)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_B_tWRPDEN_MSK                     (0x7E000000)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_B_tWRPDEN_MAX                     (0x0000003F)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_B_tWRPDEN_DEF                     (0x00000005)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_B_Dec_WRD_OFF                     (31)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_B_Dec_WRD_WID                     ( 1)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_B_Dec_WRD_MSK                     (0x80000000)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_B_Dec_WRD_MAX                     (0x00000001)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_B_Dec_WRD_DEF                     (0x00000000)
+
+#define MCHBAR_CH0_CR_TC_BANK_RANK_C_REG                             (0x0000400C)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_C_tXPDLL_OFF                      ( 0)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_C_tXPDLL_WID                      ( 6)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_C_tXPDLL_MSK                      (0x0000003F)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_C_tXPDLL_MAX                      (0x0000003F)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_C_tXPDLL_DEF                      (0x0000000A)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_C_tXP_OFF                         ( 6)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_C_tXP_WID                         ( 4)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_C_tXP_MSK                         (0x000003C0)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_C_tXP_MAX                         (0x0000000F)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_C_tXP_DEF                         (0x00000003)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_C_TAONPD_OFF                      (10)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_C_TAONPD_WID                      ( 4)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_C_TAONPD_MSK                      (0x00003C00)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_C_TAONPD_MAX                      (0x0000000F)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_C_TAONPD_DEF                      (0x00000009)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_C_tRDWR_OFF                       (14)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_C_tRDWR_WID                       ( 5)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_C_tRDWR_MSK                       (0x0007C000)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_C_tRDWR_MAX                       (0x0000001F)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_C_tRDWR_DEF                       (0x00000005)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_C_tRDWR_dr_OFF                    (19)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_C_tRDWR_dr_WID                    ( 5)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_C_tRDWR_dr_MSK                    (0x00F80000)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_C_tRDWR_dr_MAX                    (0x0000001F)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_C_tRDWR_dr_DEF                    (0x00000005)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_C_tRDWR_dd_OFF                    (24)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_C_tRDWR_dd_WID                    ( 5)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_C_tRDWR_dd_MSK                    (0x1F000000)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_C_tRDWR_dd_MAX                    (0x0000001F)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_C_tRDWR_dd_DEF                    (0x00000005)
+
+#define MCHBAR_CH0_CR_CMD_RATE_REG                                   (0x00004010)
+  #define MCHBAR_CH0_CR_CMD_RATE_enable_cmd_rate_limit_OFF             ( 0)
+  #define MCHBAR_CH0_CR_CMD_RATE_enable_cmd_rate_limit_WID             ( 1)
+  #define MCHBAR_CH0_CR_CMD_RATE_enable_cmd_rate_limit_MSK             (0x00000001)
+  #define MCHBAR_CH0_CR_CMD_RATE_enable_cmd_rate_limit_MAX             (0x00000001)
+  #define MCHBAR_CH0_CR_CMD_RATE_enable_cmd_rate_limit_DEF             (0x00000000)
+  #define MCHBAR_CH0_CR_CMD_RATE_cmd_rate_limit_OFF                    ( 1)
+  #define MCHBAR_CH0_CR_CMD_RATE_cmd_rate_limit_WID                    ( 3)
+  #define MCHBAR_CH0_CR_CMD_RATE_cmd_rate_limit_MSK                    (0x0000000E)
+  #define MCHBAR_CH0_CR_CMD_RATE_cmd_rate_limit_MAX                    (0x00000007)
+  #define MCHBAR_CH0_CR_CMD_RATE_cmd_rate_limit_DEF                    (0x00000004)
+  #define MCHBAR_CH0_CR_CMD_RATE_reset_on_command_OFF                  ( 4)
+  #define MCHBAR_CH0_CR_CMD_RATE_reset_on_command_WID                  ( 4)
+  #define MCHBAR_CH0_CR_CMD_RATE_reset_on_command_MSK                  (0x000000F0)
+  #define MCHBAR_CH0_CR_CMD_RATE_reset_on_command_MAX                  (0x0000000F)
+  #define MCHBAR_CH0_CR_CMD_RATE_reset_on_command_DEF                  (0x00000000)
+  #define MCHBAR_CH0_CR_CMD_RATE_reset_delay_OFF                       ( 8)
+  #define MCHBAR_CH0_CR_CMD_RATE_reset_delay_WID                       ( 4)
+  #define MCHBAR_CH0_CR_CMD_RATE_reset_delay_MSK                       (0x00000F00)
+  #define MCHBAR_CH0_CR_CMD_RATE_reset_delay_MAX                       (0x0000000F)
+  #define MCHBAR_CH0_CR_CMD_RATE_reset_delay_DEF                       (0x00000000)
+  #define MCHBAR_CH0_CR_CMD_RATE_ck_to_cke_delay_OFF                   (12)
+  #define MCHBAR_CH0_CR_CMD_RATE_ck_to_cke_delay_WID                   ( 2)
+  #define MCHBAR_CH0_CR_CMD_RATE_ck_to_cke_delay_MSK                   (0x00003000)
+  #define MCHBAR_CH0_CR_CMD_RATE_ck_to_cke_delay_MAX                   (0x00000003)
+  #define MCHBAR_CH0_CR_CMD_RATE_ck_to_cke_delay_DEF                   (0x00000001)
+  #define MCHBAR_CH0_CR_CMD_RATE_spare_OFF                             (14)
+  #define MCHBAR_CH0_CR_CMD_RATE_spare_WID                             (17)
+  #define MCHBAR_CH0_CR_CMD_RATE_spare_MSK                             (0x7FFFC000)
+  #define MCHBAR_CH0_CR_CMD_RATE_spare_MAX                             (0x0001FFFF)
+  #define MCHBAR_CH0_CR_CMD_RATE_spare_DEF                             (0x00000000)
+  #define MCHBAR_CH0_CR_CMD_RATE_init_mrw_2n_cs_OFF                    (31)
+  #define MCHBAR_CH0_CR_CMD_RATE_init_mrw_2n_cs_WID                    ( 1)
+  #define MCHBAR_CH0_CR_CMD_RATE_init_mrw_2n_cs_MSK                    (0x80000000)
+  #define MCHBAR_CH0_CR_CMD_RATE_init_mrw_2n_cs_MAX                    (0x00000001)
+  #define MCHBAR_CH0_CR_CMD_RATE_init_mrw_2n_cs_DEF                    (0x00000000)
+
+#define MCHBAR_CH0_CR_TC_BANK_RANK_D_REG                             (0x00004014)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_D_tCL_OFF                         ( 0)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_D_tCL_WID                         ( 5)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_D_tCL_MSK                         (0x0000001F)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_D_tCL_MAX                         (0x0000001F)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_D_tCL_DEF                         (0x00000006)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_D_tWCL_OFF                        ( 5)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_D_tWCL_WID                        ( 5)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_D_tWCL_MSK                        (0x000003E0)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_D_tWCL_MAX                        (0x0000001F)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_D_tWCL_DEF                        (0x00000006)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_D_tCPDED_OFF                      (10)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_D_tCPDED_WID                      ( 2)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_D_tCPDED_MSK                      (0x00000C00)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_D_tCPDED_MAX                      (0x00000003)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_D_tCPDED_DEF                      (0x00000001)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_D_tPRPDEN_OFF                     (12)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_D_tPRPDEN_WID                     ( 2)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_D_tPRPDEN_MSK                     (0x00003000)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_D_tPRPDEN_MAX                     (0x00000003)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_D_tPRPDEN_DEF                     (0x00000001)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_D_Odt_Read_Delay_OFF              (14)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_D_Odt_Read_Delay_WID              ( 3)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_D_Odt_Read_Delay_MSK              (0x0001C000)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_D_Odt_Read_Delay_MAX              (0x00000007)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_D_Odt_Read_Delay_DEF              (0x00000000)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_D_Odt_Read_Duration_OFF           (17)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_D_Odt_Read_Duration_WID           ( 2)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_D_Odt_Read_Duration_MSK           (0x00060000)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_D_Odt_Read_Duration_MAX           (0x00000003)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_D_Odt_Read_Duration_DEF           (0x00000000)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_D_Odt_Write_Duration_OFF          (19)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_D_Odt_Write_Duration_WID          ( 2)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_D_Odt_Write_Duration_MSK          (0x00180000)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_D_Odt_Write_Duration_MAX          (0x00000003)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_D_Odt_Write_Duration_DEF          (0x00000000)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_D_Odt_Write_Duration_Ult_OFF      (19)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_D_Odt_Write_Duration_Ult_WID      ( 3)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_D_Odt_Write_Duration_Ult_MSK      (0x00380000)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_D_Odt_Write_Duration_Ult_MAX      (0x00000007)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_D_Odt_Write_Duration_Ult_DEF      (0x00000000)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_D_Odt_Write_Delay_Ult_OFF         (22)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_D_Odt_Write_Delay_Ult_WID         ( 3)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_D_Odt_Write_Delay_Ult_MSK         (0x01C00000)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_D_Odt_Write_Delay_Ult_MAX         (0x00000007)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_D_Odt_Write_Delay_Ult_DEF         (0x00000000)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_D_Odt_Always_Rank0_Ult_OFF        (25)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_D_Odt_Always_Rank0_Ult_WID        ( 1)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_D_Odt_Always_Rank0_Ult_MSK        (0x02000000)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_D_Odt_Always_Rank0_Ult_MAX        (0x00000001)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_D_Odt_Always_Rank0_Ult_DEF        (0x00000000)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_D_cmd_delay_Ult_OFF               (26)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_D_cmd_delay_Ult_WID               ( 2)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_D_cmd_delay_Ult_MSK               (0x0C000000)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_D_cmd_delay_Ult_MAX               (0x00000003)
+  #define MCHBAR_CH0_CR_TC_BANK_RANK_D_cmd_delay_Ult_DEF               (0x00000000)
+
+#define MCHBAR_CH0_CR_SCHED_CBIT_REG                                 (0x00004020)
+  #define MCHBAR_CH0_CR_SCHED_CBIT_dis_opp_cas_OFF                     ( 0)
+  #define MCHBAR_CH0_CR_SCHED_CBIT_dis_opp_cas_WID                     ( 1)
+  #define MCHBAR_CH0_CR_SCHED_CBIT_dis_opp_cas_MSK                     (0x00000001)
+  #define MCHBAR_CH0_CR_SCHED_CBIT_dis_opp_cas_MAX                     (0x00000001)
+  #define MCHBAR_CH0_CR_SCHED_CBIT_dis_opp_cas_DEF                     (0x00000001)
+  #define MCHBAR_CH0_CR_SCHED_CBIT_dis_opp_is_cas_OFF                  ( 1)
+  #define MCHBAR_CH0_CR_SCHED_CBIT_dis_opp_is_cas_WID                  ( 1)
+  #define MCHBAR_CH0_CR_SCHED_CBIT_dis_opp_is_cas_MSK                  (0x00000002)
+  #define MCHBAR_CH0_CR_SCHED_CBIT_dis_opp_is_cas_MAX                  (0x00000001)
+  #define MCHBAR_CH0_CR_SCHED_CBIT_dis_opp_is_cas_DEF                  (0x00000000)
+  #define MCHBAR_CH0_CR_SCHED_CBIT_dis_opp_ras_OFF                     ( 2)
+  #define MCHBAR_CH0_CR_SCHED_CBIT_dis_opp_ras_WID                     ( 1)
+  #define MCHBAR_CH0_CR_SCHED_CBIT_dis_opp_ras_MSK                     (0x00000004)
+  #define MCHBAR_CH0_CR_SCHED_CBIT_dis_opp_ras_MAX                     (0x00000001)
+  #define MCHBAR_CH0_CR_SCHED_CBIT_dis_opp_ras_DEF                     (0x00000001)
+  #define MCHBAR_CH0_CR_SCHED_CBIT_dis_opp_is_ras_OFF                  ( 3)
+  #define MCHBAR_CH0_CR_SCHED_CBIT_dis_opp_is_ras_WID                  ( 1)
+  #define MCHBAR_CH0_CR_SCHED_CBIT_dis_opp_is_ras_MSK                  (0x00000008)
+  #define MCHBAR_CH0_CR_SCHED_CBIT_dis_opp_is_ras_MAX                  (0x00000001)
+  #define MCHBAR_CH0_CR_SCHED_CBIT_dis_opp_is_ras_DEF                  (0x00000000)
+  #define MCHBAR_CH0_CR_SCHED_CBIT_dis_1c_byp_OFF                      ( 4)
+  #define MCHBAR_CH0_CR_SCHED_CBIT_dis_1c_byp_WID                      ( 1)
+  #define MCHBAR_CH0_CR_SCHED_CBIT_dis_1c_byp_MSK                      (0x00000010)
+  #define MCHBAR_CH0_CR_SCHED_CBIT_dis_1c_byp_MAX                      (0x00000001)
+  #define MCHBAR_CH0_CR_SCHED_CBIT_dis_1c_byp_DEF                      (0x00000001)
+  #define MCHBAR_CH0_CR_SCHED_CBIT_dis_2c_byp_OFF                      ( 5)
+  #define MCHBAR_CH0_CR_SCHED_CBIT_dis_2c_byp_WID                      ( 1)
+  #define MCHBAR_CH0_CR_SCHED_CBIT_dis_2c_byp_MSK                      (0x00000020)
+  #define MCHBAR_CH0_CR_SCHED_CBIT_dis_2c_byp_MAX                      (0x00000001)
+  #define MCHBAR_CH0_CR_SCHED_CBIT_dis_2c_byp_DEF                      (0x00000000)
+  #define MCHBAR_CH0_CR_SCHED_CBIT_dis_deprd_opt_OFF                   ( 6)
+  #define MCHBAR_CH0_CR_SCHED_CBIT_dis_deprd_opt_WID                   ( 1)
+  #define MCHBAR_CH0_CR_SCHED_CBIT_dis_deprd_opt_MSK                   (0x00000040)
+  #define MCHBAR_CH0_CR_SCHED_CBIT_dis_deprd_opt_MAX                   (0x00000001)
+  #define MCHBAR_CH0_CR_SCHED_CBIT_dis_deprd_opt_DEF                   (0x00000000)
+  #define MCHBAR_CH0_CR_SCHED_CBIT_dis_pt_it_OFF                       ( 7)
+  #define MCHBAR_CH0_CR_SCHED_CBIT_dis_pt_it_WID                       ( 1)
+  #define MCHBAR_CH0_CR_SCHED_CBIT_dis_pt_it_MSK                       (0x00000080)
+  #define MCHBAR_CH0_CR_SCHED_CBIT_dis_pt_it_MAX                       (0x00000001)
+  #define MCHBAR_CH0_CR_SCHED_CBIT_dis_pt_it_DEF                       (0x00000000)
+  #define MCHBAR_CH0_CR_SCHED_CBIT_dis_prcnt_ring_OFF                  ( 8)
+  #define MCHBAR_CH0_CR_SCHED_CBIT_dis_prcnt_ring_WID                  ( 1)
+  #define MCHBAR_CH0_CR_SCHED_CBIT_dis_prcnt_ring_MSK                  (0x00000100)
+  #define MCHBAR_CH0_CR_SCHED_CBIT_dis_prcnt_ring_MAX                  (0x00000001)
+  #define MCHBAR_CH0_CR_SCHED_CBIT_dis_prcnt_ring_DEF                  (0x00000000)
+  #define MCHBAR_CH0_CR_SCHED_CBIT_dis_prcnt_sa_OFF                    ( 9)
+  #define MCHBAR_CH0_CR_SCHED_CBIT_dis_prcnt_sa_WID                    ( 1)
+  #define MCHBAR_CH0_CR_SCHED_CBIT_dis_prcnt_sa_MSK                    (0x00000200)
+  #define MCHBAR_CH0_CR_SCHED_CBIT_dis_prcnt_sa_MAX                    (0x00000001)
+  #define MCHBAR_CH0_CR_SCHED_CBIT_dis_prcnt_sa_DEF                    (0x00000000)
+  #define MCHBAR_CH0_CR_SCHED_CBIT_dis_blkr_ph_OFF                     (10)
+  #define MCHBAR_CH0_CR_SCHED_CBIT_dis_blkr_ph_WID                     ( 1)
+  #define MCHBAR_CH0_CR_SCHED_CBIT_dis_blkr_ph_MSK                     (0x00000400)
+  #define MCHBAR_CH0_CR_SCHED_CBIT_dis_blkr_ph_MAX                     (0x00000001)
+  #define MCHBAR_CH0_CR_SCHED_CBIT_dis_blkr_ph_DEF                     (0x00000000)
+  #define MCHBAR_CH0_CR_SCHED_CBIT_dis_blkr_pe_OFF                     (11)
+  #define MCHBAR_CH0_CR_SCHED_CBIT_dis_blkr_pe_WID                     ( 1)
+  #define MCHBAR_CH0_CR_SCHED_CBIT_dis_blkr_pe_MSK                     (0x00000800)
+  #define MCHBAR_CH0_CR_SCHED_CBIT_dis_blkr_pe_MAX                     (0x00000001)
+  #define MCHBAR_CH0_CR_SCHED_CBIT_dis_blkr_pe_DEF                     (0x00000000)
+  #define MCHBAR_CH0_CR_SCHED_CBIT_dis_blkr_pm_OFF                     (12)
+  #define MCHBAR_CH0_CR_SCHED_CBIT_dis_blkr_pm_WID                     ( 1)
+  #define MCHBAR_CH0_CR_SCHED_CBIT_dis_blkr_pm_MSK                     (0x00001000)
+  #define MCHBAR_CH0_CR_SCHED_CBIT_dis_blkr_pm_MAX                     (0x00000001)
+  #define MCHBAR_CH0_CR_SCHED_CBIT_dis_blkr_pm_DEF                     (0x00000000)
+  #define MCHBAR_CH0_CR_SCHED_CBIT_dis_odt_OFF                         (13)
+  #define MCHBAR_CH0_CR_SCHED_CBIT_dis_odt_WID                         ( 1)
+  #define MCHBAR_CH0_CR_SCHED_CBIT_dis_odt_MSK                         (0x00002000)
+  #define MCHBAR_CH0_CR_SCHED_CBIT_dis_odt_MAX                         (0x00000001)
+  #define MCHBAR_CH0_CR_SCHED_CBIT_dis_odt_DEF                         (0x00000000)
+  #define MCHBAR_CH0_CR_SCHED_CBIT_OE_alw_off_OFF                      (14)
+  #define MCHBAR_CH0_CR_SCHED_CBIT_OE_alw_off_WID                      ( 1)
+  #define MCHBAR_CH0_CR_SCHED_CBIT_OE_alw_off_MSK                      (0x00004000)
+  #define MCHBAR_CH0_CR_SCHED_CBIT_OE_alw_off_MAX                      (0x00000001)
+  #define MCHBAR_CH0_CR_SCHED_CBIT_OE_alw_off_DEF                      (0x00000000)
+  #define MCHBAR_CH0_CR_SCHED_CBIT_dis_aom_OFF                         (16)
+  #define MCHBAR_CH0_CR_SCHED_CBIT_dis_aom_WID                         ( 1)
+  #define MCHBAR_CH0_CR_SCHED_CBIT_dis_aom_MSK                         (0x00010000)
+  #define MCHBAR_CH0_CR_SCHED_CBIT_dis_aom_MAX                         (0x00000001)
+  #define MCHBAR_CH0_CR_SCHED_CBIT_dis_aom_DEF                         (0x00000000)
+  #define MCHBAR_CH0_CR_SCHED_CBIT_block_rpq_OFF                       (17)
+  #define MCHBAR_CH0_CR_SCHED_CBIT_block_rpq_WID                       ( 1)
+  #define MCHBAR_CH0_CR_SCHED_CBIT_block_rpq_MSK                       (0x00020000)
+  #define MCHBAR_CH0_CR_SCHED_CBIT_block_rpq_MAX                       (0x00000001)
+  #define MCHBAR_CH0_CR_SCHED_CBIT_block_rpq_DEF                       (0x00000000)
+  #define MCHBAR_CH0_CR_SCHED_CBIT_block_wpq_OFF                       (18)
+  #define MCHBAR_CH0_CR_SCHED_CBIT_block_wpq_WID                       ( 1)
+  #define MCHBAR_CH0_CR_SCHED_CBIT_block_wpq_MSK                       (0x00040000)
+  #define MCHBAR_CH0_CR_SCHED_CBIT_block_wpq_MAX                       (0x00000001)
+  #define MCHBAR_CH0_CR_SCHED_CBIT_block_wpq_DEF                       (0x00000000)
+  #define MCHBAR_CH0_CR_SCHED_CBIT_invert_align_OFF                    (19)
+  #define MCHBAR_CH0_CR_SCHED_CBIT_invert_align_WID                    ( 1)
+  #define MCHBAR_CH0_CR_SCHED_CBIT_invert_align_MSK                    (0x00080000)
+  #define MCHBAR_CH0_CR_SCHED_CBIT_invert_align_MAX                    (0x00000001)
+  #define MCHBAR_CH0_CR_SCHED_CBIT_invert_align_DEF                    (0x00000000)
+  #define MCHBAR_CH0_CR_SCHED_CBIT_dis_write_gap_OFF                   (20)
+  #define MCHBAR_CH0_CR_SCHED_CBIT_dis_write_gap_WID                   ( 1)
+  #define MCHBAR_CH0_CR_SCHED_CBIT_dis_write_gap_MSK                   (0x00100000)
+  #define MCHBAR_CH0_CR_SCHED_CBIT_dis_write_gap_MAX                   (0x00000001)
+  #define MCHBAR_CH0_CR_SCHED_CBIT_dis_write_gap_DEF                   (0x00000001)
+  #define MCHBAR_CH0_CR_SCHED_CBIT_dis_zq_OFF                          (21)
+  #define MCHBAR_CH0_CR_SCHED_CBIT_dis_zq_WID                          ( 1)
+  #define MCHBAR_CH0_CR_SCHED_CBIT_dis_zq_MSK                          (0x00200000)
+  #define MCHBAR_CH0_CR_SCHED_CBIT_dis_zq_MAX                          (0x00000001)
+  #define MCHBAR_CH0_CR_SCHED_CBIT_dis_zq_DEF                          (0x00000000)
+  #define MCHBAR_CH0_CR_SCHED_CBIT_dis_tt_OFF                          (22)
+  #define MCHBAR_CH0_CR_SCHED_CBIT_dis_tt_WID                          ( 1)
+  #define MCHBAR_CH0_CR_SCHED_CBIT_dis_tt_MSK                          (0x00400000)
+  #define MCHBAR_CH0_CR_SCHED_CBIT_dis_tt_MAX                          (0x00000001)
+  #define MCHBAR_CH0_CR_SCHED_CBIT_dis_tt_DEF                          (0x00000000)
+  #define MCHBAR_CH0_CR_SCHED_CBIT_dis_opp_ref_OFF                     (23)
+  #define MCHBAR_CH0_CR_SCHED_CBIT_dis_opp_ref_WID                     ( 1)
+  #define MCHBAR_CH0_CR_SCHED_CBIT_dis_opp_ref_MSK                     (0x00800000)
+  #define MCHBAR_CH0_CR_SCHED_CBIT_dis_opp_ref_MAX                     (0x00000001)
+  #define MCHBAR_CH0_CR_SCHED_CBIT_dis_opp_ref_DEF                     (0x00000000)
+  #define MCHBAR_CH0_CR_SCHED_CBIT_Long_ZQ_OFF                         (24)
+  #define MCHBAR_CH0_CR_SCHED_CBIT_Long_ZQ_WID                         ( 1)
+  #define MCHBAR_CH0_CR_SCHED_CBIT_Long_ZQ_MSK                         (0x01000000)
+  #define MCHBAR_CH0_CR_SCHED_CBIT_Long_ZQ_MAX                         (0x00000001)
+  #define MCHBAR_CH0_CR_SCHED_CBIT_Long_ZQ_DEF                         (0x00000000)
+  #define MCHBAR_CH0_CR_SCHED_CBIT_dis_srx_zq_OFF                      (25)
+  #define MCHBAR_CH0_CR_SCHED_CBIT_dis_srx_zq_WID                      ( 1)
+  #define MCHBAR_CH0_CR_SCHED_CBIT_dis_srx_zq_MSK                      (0x02000000)
+  #define MCHBAR_CH0_CR_SCHED_CBIT_dis_srx_zq_MAX                      (0x00000001)
+  #define MCHBAR_CH0_CR_SCHED_CBIT_dis_srx_zq_DEF                      (0x00000000)
+  #define MCHBAR_CH0_CR_SCHED_CBIT_Serialize_ZQ_OFF                    (26)
+  #define MCHBAR_CH0_CR_SCHED_CBIT_Serialize_ZQ_WID                    ( 1)
+  #define MCHBAR_CH0_CR_SCHED_CBIT_Serialize_ZQ_MSK                    (0x04000000)
+  #define MCHBAR_CH0_CR_SCHED_CBIT_Serialize_ZQ_MAX                    (0x00000001)
+  #define MCHBAR_CH0_CR_SCHED_CBIT_Serialize_ZQ_DEF                    (0x00000000)
+  #define MCHBAR_CH0_CR_SCHED_CBIT_ZQ_fast_exec_OFF                    (27)
+  #define MCHBAR_CH0_CR_SCHED_CBIT_ZQ_fast_exec_WID                    ( 1)
+  #define MCHBAR_CH0_CR_SCHED_CBIT_ZQ_fast_exec_MSK                    (0x08000000)
+  #define MCHBAR_CH0_CR_SCHED_CBIT_ZQ_fast_exec_MAX                    (0x00000001)
+  #define MCHBAR_CH0_CR_SCHED_CBIT_ZQ_fast_exec_DEF                    (0x00000000)
+  #define MCHBAR_CH0_CR_SCHED_CBIT_Dis_DriveNop_OFF                    (28)
+  #define MCHBAR_CH0_CR_SCHED_CBIT_Dis_DriveNop_WID                    ( 1)
+  #define MCHBAR_CH0_CR_SCHED_CBIT_Dis_DriveNop_MSK                    (0x10000000)
+  #define MCHBAR_CH0_CR_SCHED_CBIT_Dis_DriveNop_MAX                    (0x00000001)
+  #define MCHBAR_CH0_CR_SCHED_CBIT_Dis_DriveNop_DEF                    (0x00000000)
+  #define MCHBAR_CH0_CR_SCHED_CBIT_Pres_WDB_Ent_OFF                    (29)
+  #define MCHBAR_CH0_CR_SCHED_CBIT_Pres_WDB_Ent_WID                    ( 1)
+  #define MCHBAR_CH0_CR_SCHED_CBIT_Pres_WDB_Ent_MSK                    (0x20000000)
+  #define MCHBAR_CH0_CR_SCHED_CBIT_Pres_WDB_Ent_MAX                    (0x00000001)
+  #define MCHBAR_CH0_CR_SCHED_CBIT_Pres_WDB_Ent_DEF                    (0x00000000)
+  #define MCHBAR_CH0_CR_SCHED_CBIT_dis_clk_gate_OFF                    (30)
+  #define MCHBAR_CH0_CR_SCHED_CBIT_dis_clk_gate_WID                    ( 1)
+  #define MCHBAR_CH0_CR_SCHED_CBIT_dis_clk_gate_MSK                    (0x40000000)
+  #define MCHBAR_CH0_CR_SCHED_CBIT_dis_clk_gate_MAX                    (0x00000001)
+  #define MCHBAR_CH0_CR_SCHED_CBIT_dis_clk_gate_DEF                    (0x00000000)
+
+#define MCHBAR_CH0_CR_SC_ROUNDT_LAT_REG                              (0x00004024)
+  #define MCHBAR_CH0_CR_SC_ROUNDT_LAT_Lat_R0D0_OFF                     ( 0)
+  #define MCHBAR_CH0_CR_SC_ROUNDT_LAT_Lat_R0D0_WID                     ( 6)
+  #define MCHBAR_CH0_CR_SC_ROUNDT_LAT_Lat_R0D0_MSK                     (0x0000003F)
+  #define MCHBAR_CH0_CR_SC_ROUNDT_LAT_Lat_R0D0_MAX                     (0x0000003F)
+  #define MCHBAR_CH0_CR_SC_ROUNDT_LAT_Lat_R0D0_DEF                     (0x00000020)
+  #define MCHBAR_CH0_CR_SC_ROUNDT_LAT_Lat_R1D0_OFF                     ( 8)
+  #define MCHBAR_CH0_CR_SC_ROUNDT_LAT_Lat_R1D0_WID                     ( 6)
+  #define MCHBAR_CH0_CR_SC_ROUNDT_LAT_Lat_R1D0_MSK                     (0x00003F00)
+  #define MCHBAR_CH0_CR_SC_ROUNDT_LAT_Lat_R1D0_MAX                     (0x0000003F)
+  #define MCHBAR_CH0_CR_SC_ROUNDT_LAT_Lat_R1D0_DEF                     (0x00000020)
+  #define MCHBAR_CH0_CR_SC_ROUNDT_LAT_Lat_R0D1_OFF                     (16)
+  #define MCHBAR_CH0_CR_SC_ROUNDT_LAT_Lat_R0D1_WID                     ( 6)
+  #define MCHBAR_CH0_CR_SC_ROUNDT_LAT_Lat_R0D1_MSK                     (0x003F0000)
+  #define MCHBAR_CH0_CR_SC_ROUNDT_LAT_Lat_R0D1_MAX                     (0x0000003F)
+  #define MCHBAR_CH0_CR_SC_ROUNDT_LAT_Lat_R0D1_DEF                     (0x00000020)
+  #define MCHBAR_CH0_CR_SC_ROUNDT_LAT_Lat_R1D1_OFF                     (24)
+  #define MCHBAR_CH0_CR_SC_ROUNDT_LAT_Lat_R1D1_WID                     ( 6)
+  #define MCHBAR_CH0_CR_SC_ROUNDT_LAT_Lat_R1D1_MSK                     (0x3F000000)
+  #define MCHBAR_CH0_CR_SC_ROUNDT_LAT_Lat_R1D1_MAX                     (0x0000003F)
+  #define MCHBAR_CH0_CR_SC_ROUNDT_LAT_Lat_R1D1_DEF                     (0x00000020)
+
+#define MCHBAR_CH0_CR_SC_IO_LATENCY_REG                              (0x00004028)
+  #define MCHBAR_CH0_CR_SC_IO_LATENCY_IOLAT_R0D0_OFF                   ( 0)
+  #define MCHBAR_CH0_CR_SC_IO_LATENCY_IOLAT_R0D0_WID                   ( 4)
+  #define MCHBAR_CH0_CR_SC_IO_LATENCY_IOLAT_R0D0_MSK                   (0x0000000F)
+  #define MCHBAR_CH0_CR_SC_IO_LATENCY_IOLAT_R0D0_MAX                   (0x0000000F)
+  #define MCHBAR_CH0_CR_SC_IO_LATENCY_IOLAT_R0D0_DEF                   (0x00000000)
+  #define MCHBAR_CH0_CR_SC_IO_LATENCY_IOLAT_R1D0_OFF                   ( 4)
+  #define MCHBAR_CH0_CR_SC_IO_LATENCY_IOLAT_R1D0_WID                   ( 4)
+  #define MCHBAR_CH0_CR_SC_IO_LATENCY_IOLAT_R1D0_MSK                   (0x000000F0)
+  #define MCHBAR_CH0_CR_SC_IO_LATENCY_IOLAT_R1D0_MAX                   (0x0000000F)
+  #define MCHBAR_CH0_CR_SC_IO_LATENCY_IOLAT_R1D0_DEF                   (0x00000000)
+  #define MCHBAR_CH0_CR_SC_IO_LATENCY_IOLAT_R0D1_OFF                   ( 8)
+  #define MCHBAR_CH0_CR_SC_IO_LATENCY_IOLAT_R0D1_WID                   ( 4)
+  #define MCHBAR_CH0_CR_SC_IO_LATENCY_IOLAT_R0D1_MSK                   (0x00000F00)
+  #define MCHBAR_CH0_CR_SC_IO_LATENCY_IOLAT_R0D1_MAX                   (0x0000000F)
+  #define MCHBAR_CH0_CR_SC_IO_LATENCY_IOLAT_R0D1_DEF                   (0x00000000)
+  #define MCHBAR_CH0_CR_SC_IO_LATENCY_IOLAT_R1D1_OFF                   (12)
+  #define MCHBAR_CH0_CR_SC_IO_LATENCY_IOLAT_R1D1_WID                   ( 4)
+  #define MCHBAR_CH0_CR_SC_IO_LATENCY_IOLAT_R1D1_MSK                   (0x0000F000)
+  #define MCHBAR_CH0_CR_SC_IO_LATENCY_IOLAT_R1D1_MAX                   (0x0000000F)
+  #define MCHBAR_CH0_CR_SC_IO_LATENCY_IOLAT_R1D1_DEF                   (0x00000000)
+  #define MCHBAR_CH0_CR_SC_IO_LATENCY_RT_IOCOMP_OFF                    (16)
+  #define MCHBAR_CH0_CR_SC_IO_LATENCY_RT_IOCOMP_WID                    ( 6)
+  #define MCHBAR_CH0_CR_SC_IO_LATENCY_RT_IOCOMP_MSK                    (0x003F0000)
+  #define MCHBAR_CH0_CR_SC_IO_LATENCY_RT_IOCOMP_MAX                    (0x0000003F)
+  #define MCHBAR_CH0_CR_SC_IO_LATENCY_RT_IOCOMP_DEF                    (0x0000000E)
+  #define MCHBAR_CH0_CR_SC_IO_LATENCY_three_channels_OFF               (30)
+  #define MCHBAR_CH0_CR_SC_IO_LATENCY_three_channels_WID               ( 1)
+  #define MCHBAR_CH0_CR_SC_IO_LATENCY_three_channels_MSK               (0x40000000)
+  #define MCHBAR_CH0_CR_SC_IO_LATENCY_three_channels_MAX               (0x00000001)
+  #define MCHBAR_CH0_CR_SC_IO_LATENCY_three_channels_DEF               (0x00000000)
+  #define MCHBAR_CH0_CR_SC_IO_LATENCY_DIS_RT_CLK_GATE_OFF              (31)
+  #define MCHBAR_CH0_CR_SC_IO_LATENCY_DIS_RT_CLK_GATE_WID              ( 1)
+  #define MCHBAR_CH0_CR_SC_IO_LATENCY_DIS_RT_CLK_GATE_MSK              (0x80000000)
+  #define MCHBAR_CH0_CR_SC_IO_LATENCY_DIS_RT_CLK_GATE_MAX              (0x00000001)
+  #define MCHBAR_CH0_CR_SC_IO_LATENCY_DIS_RT_CLK_GATE_DEF              (0x00000000)
+
+#define MCHBAR_CH0_CR_ROUND_TRIP_DFT_DATA_REG                        (0x0000402C)
+  #define MCHBAR_CH0_CR_ROUND_TRIP_DFT_DATA_DATA_OFF                   ( 0)
+  #define MCHBAR_CH0_CR_ROUND_TRIP_DFT_DATA_DATA_WID                   (32)
+  #define MCHBAR_CH0_CR_ROUND_TRIP_DFT_DATA_DATA_MSK                   (0xFFFFFFFF)
+  #define MCHBAR_CH0_CR_ROUND_TRIP_DFT_DATA_DATA_MAX                   (0xFFFFFFFF)
+  #define MCHBAR_CH0_CR_ROUND_TRIP_DFT_DATA_DATA_DEF                   (0x00000000)
+
+#define MCHBAR_CH0_CR_DFT_MISC_REG                                   (0x00004030)
+  #define MCHBAR_CH0_CR_DFT_MISC_WDAR_OFF                              ( 0)
+  #define MCHBAR_CH0_CR_DFT_MISC_WDAR_WID                              ( 1)
+  #define MCHBAR_CH0_CR_DFT_MISC_WDAR_MSK                              (0x00000001)
+  #define MCHBAR_CH0_CR_DFT_MISC_WDAR_MAX                              (0x00000001)
+  #define MCHBAR_CH0_CR_DFT_MISC_WDAR_DEF                              (0x00000000)
+  #define MCHBAR_CH0_CR_DFT_MISC_safe_mask_sel_OFF                     ( 1)
+  #define MCHBAR_CH0_CR_DFT_MISC_safe_mask_sel_WID                     ( 3)
+  #define MCHBAR_CH0_CR_DFT_MISC_safe_mask_sel_MSK                     (0x0000000E)
+  #define MCHBAR_CH0_CR_DFT_MISC_safe_mask_sel_MAX                     (0x00000007)
+  #define MCHBAR_CH0_CR_DFT_MISC_safe_mask_sel_DEF                     (0x00000000)
+  #define MCHBAR_CH0_CR_DFT_MISC_force_rcv_en_OFF                      ( 4)
+  #define MCHBAR_CH0_CR_DFT_MISC_force_rcv_en_WID                      ( 1)
+  #define MCHBAR_CH0_CR_DFT_MISC_force_rcv_en_MSK                      (0x00000010)
+  #define MCHBAR_CH0_CR_DFT_MISC_force_rcv_en_MAX                      (0x00000001)
+  #define MCHBAR_CH0_CR_DFT_MISC_force_rcv_en_DEF                      (0x00000000)
+  #define MCHBAR_CH0_CR_DFT_MISC_DDR_QUAL_OFF                          ( 8)
+  #define MCHBAR_CH0_CR_DFT_MISC_DDR_QUAL_WID                          ( 2)
+  #define MCHBAR_CH0_CR_DFT_MISC_DDR_QUAL_MSK                          (0x00000300)
+  #define MCHBAR_CH0_CR_DFT_MISC_DDR_QUAL_MAX                          (0x00000003)
+  #define MCHBAR_CH0_CR_DFT_MISC_DDR_QUAL_DEF                          (0x00000000)
+  #define MCHBAR_CH0_CR_DFT_MISC_Qual_length_OFF                       (10)
+  #define MCHBAR_CH0_CR_DFT_MISC_Qual_length_WID                       ( 2)
+  #define MCHBAR_CH0_CR_DFT_MISC_Qual_length_MSK                       (0x00000C00)
+  #define MCHBAR_CH0_CR_DFT_MISC_Qual_length_MAX                       (0x00000003)
+  #define MCHBAR_CH0_CR_DFT_MISC_Qual_length_DEF                       (0x00000000)
+  #define MCHBAR_CH0_CR_DFT_MISC_WDB_Block_En_OFF                      (12)
+  #define MCHBAR_CH0_CR_DFT_MISC_WDB_Block_En_WID                      ( 1)
+  #define MCHBAR_CH0_CR_DFT_MISC_WDB_Block_En_MSK                      (0x00001000)
+  #define MCHBAR_CH0_CR_DFT_MISC_WDB_Block_En_MAX                      (0x00000001)
+  #define MCHBAR_CH0_CR_DFT_MISC_WDB_Block_En_DEF                      (0x00000000)
+  #define MCHBAR_CH0_CR_DFT_MISC_RT_DFT_READ_PTR_OFF                   (13)
+  #define MCHBAR_CH0_CR_DFT_MISC_RT_DFT_READ_PTR_WID                   ( 4)
+  #define MCHBAR_CH0_CR_DFT_MISC_RT_DFT_READ_PTR_MSK                   (0x0001E000)
+  #define MCHBAR_CH0_CR_DFT_MISC_RT_DFT_READ_PTR_MAX                   (0x0000000F)
+  #define MCHBAR_CH0_CR_DFT_MISC_RT_DFT_READ_PTR_DEF                   (0x00000000)
+  #define MCHBAR_CH0_CR_DFT_MISC_RT_DFT_READ_ENABLE_OFF                (17)
+  #define MCHBAR_CH0_CR_DFT_MISC_RT_DFT_READ_ENABLE_WID                ( 1)
+  #define MCHBAR_CH0_CR_DFT_MISC_RT_DFT_READ_ENABLE_MSK                (0x00020000)
+  #define MCHBAR_CH0_CR_DFT_MISC_RT_DFT_READ_ENABLE_MAX                (0x00000001)
+  #define MCHBAR_CH0_CR_DFT_MISC_RT_DFT_READ_ENABLE_DEF                (0x00000000)
+  #define MCHBAR_CH0_CR_DFT_MISC_RT_DFT_READ_SEL_ADDR_OFF              (18)
+  #define MCHBAR_CH0_CR_DFT_MISC_RT_DFT_READ_SEL_ADDR_WID              ( 1)
+  #define MCHBAR_CH0_CR_DFT_MISC_RT_DFT_READ_SEL_ADDR_MSK              (0x00040000)
+  #define MCHBAR_CH0_CR_DFT_MISC_RT_DFT_READ_SEL_ADDR_MAX              (0x00000001)
+  #define MCHBAR_CH0_CR_DFT_MISC_RT_DFT_READ_SEL_ADDR_DEF              (0x00000000)
+
+#define MCHBAR_CH0_CR_READ_RETURN_DFT_REG                            (0x00004034)
+  #define MCHBAR_CH0_CR_READ_RETURN_DFT_ECC_OFF                        ( 0)
+  #define MCHBAR_CH0_CR_READ_RETURN_DFT_ECC_WID                        ( 8)
+  #define MCHBAR_CH0_CR_READ_RETURN_DFT_ECC_MSK                        (0x000000FF)
+  #define MCHBAR_CH0_CR_READ_RETURN_DFT_ECC_MAX                        (0x000000FF)
+  #define MCHBAR_CH0_CR_READ_RETURN_DFT_ECC_DEF                        (0x00000000)
+  #define MCHBAR_CH0_CR_READ_RETURN_DFT_RRD_DFT_Mode_OFF               ( 8)
+  #define MCHBAR_CH0_CR_READ_RETURN_DFT_RRD_DFT_Mode_WID               ( 2)
+  #define MCHBAR_CH0_CR_READ_RETURN_DFT_RRD_DFT_Mode_MSK               (0x00000300)
+  #define MCHBAR_CH0_CR_READ_RETURN_DFT_RRD_DFT_Mode_MAX               (0x00000003)
+  #define MCHBAR_CH0_CR_READ_RETURN_DFT_RRD_DFT_Mode_DEF               (0x00000000)
+  #define MCHBAR_CH0_CR_READ_RETURN_DFT_LFSR_Seed_Index_OFF            (10)
+  #define MCHBAR_CH0_CR_READ_RETURN_DFT_LFSR_Seed_Index_WID            ( 5)
+  #define MCHBAR_CH0_CR_READ_RETURN_DFT_LFSR_Seed_Index_MSK            (0x00007C00)
+  #define MCHBAR_CH0_CR_READ_RETURN_DFT_LFSR_Seed_Index_MAX            (0x0000001F)
+  #define MCHBAR_CH0_CR_READ_RETURN_DFT_LFSR_Seed_Index_DEF            (0x00000000)
+  #define MCHBAR_CH0_CR_READ_RETURN_DFT_Inversion_Mode_OFF             (15)
+  #define MCHBAR_CH0_CR_READ_RETURN_DFT_Inversion_Mode_WID             ( 1)
+  #define MCHBAR_CH0_CR_READ_RETURN_DFT_Inversion_Mode_MSK             (0x00008000)
+  #define MCHBAR_CH0_CR_READ_RETURN_DFT_Inversion_Mode_MAX             (0x00000001)
+  #define MCHBAR_CH0_CR_READ_RETURN_DFT_Inversion_Mode_DEF             (0x00000000)
+
+#define MCHBAR_CH0_CR_SCHED_SECOND_CBIT_REG                          (0x00004038)
+  #define MCHBAR_CH0_CR_SCHED_SECOND_CBIT_dis_imph_error_OFF           ( 0)
+  #define MCHBAR_CH0_CR_SCHED_SECOND_CBIT_dis_imph_error_WID           ( 1)
+  #define MCHBAR_CH0_CR_SCHED_SECOND_CBIT_dis_imph_error_MSK           (0x00000001)
+  #define MCHBAR_CH0_CR_SCHED_SECOND_CBIT_dis_imph_error_MAX           (0x00000001)
+  #define MCHBAR_CH0_CR_SCHED_SECOND_CBIT_dis_imph_error_DEF           (0x00000000)
+  #define MCHBAR_CH0_CR_SCHED_SECOND_CBIT_dis_async_odt_OFF            ( 8)
+  #define MCHBAR_CH0_CR_SCHED_SECOND_CBIT_dis_async_odt_WID            ( 1)
+  #define MCHBAR_CH0_CR_SCHED_SECOND_CBIT_dis_async_odt_MSK            (0x00000100)
+  #define MCHBAR_CH0_CR_SCHED_SECOND_CBIT_dis_async_odt_MAX            (0x00000001)
+  #define MCHBAR_CH0_CR_SCHED_SECOND_CBIT_dis_async_odt_DEF            (0x00000000)
+
+#define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_REG                 (0x00004040)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Mux0_Control_OFF    ( 0)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Mux0_Control_WID    ( 2)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Mux0_Control_MSK    (0x00000003)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Mux0_Control_MAX    (0x00000003)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Mux0_Control_DEF    (0x00000001)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Mux1_Control_OFF    ( 3)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Mux1_Control_WID    ( 2)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Mux1_Control_MSK    (0x00000018)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Mux1_Control_MAX    (0x00000003)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Mux1_Control_DEF    (0x00000001)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Mux2_Control_OFF    ( 6)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Mux2_Control_WID    ( 2)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Mux2_Control_MSK    (0x000000C0)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Mux2_Control_MAX    (0x00000003)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Mux2_Control_DEF    (0x00000001)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_ECC_Replace_Byte_Control_OFF (14)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_ECC_Replace_Byte_Control_WID ( 1)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_ECC_Replace_Byte_Control_MSK (0x00004000)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_ECC_Replace_Byte_Control_MAX (0x00000001)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_ECC_Replace_Byte_Control_DEF (0x00000001)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_ECC_Data_Source_Sel_OFF (15)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_ECC_Data_Source_Sel_WID ( 1)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_ECC_Data_Source_Sel_MSK (0x00008000)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_ECC_Data_Source_Sel_MAX (0x00000001)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_ECC_Data_Source_Sel_DEF (0x00000001)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Save_LFSR_Seed_Rate_OFF (16)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Save_LFSR_Seed_Rate_WID ( 6)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Save_LFSR_Seed_Rate_MSK (0x003F0000)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Save_LFSR_Seed_Rate_MAX (0x0000003F)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Save_LFSR_Seed_Rate_DEF (0x00000000)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Reload_LFSR_Seed_Rate_OFF (24)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Reload_LFSR_Seed_Rate_WID ( 3)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Reload_LFSR_Seed_Rate_MSK (0x07000000)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Reload_LFSR_Seed_Rate_MAX (0x00000007)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Reload_LFSR_Seed_Rate_DEF (0x00000000)
+
+#define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_RD_STATUS_REG               (0x00004044)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_RD_STATUS_WDB_Current_Read_Pointer_OFF ( 0)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_RD_STATUS_WDB_Current_Read_Pointer_WID ( 6)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_RD_STATUS_WDB_Current_Read_Pointer_MSK (0x0000003F)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_RD_STATUS_WDB_Current_Read_Pointer_MAX (0x0000003F)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_RD_STATUS_WDB_Current_Read_Pointer_DEF (0x00000000)
+
+#define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_0_REG             (0x00004048)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_0_Pattern_Buffer_OFF ( 0)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_0_Pattern_Buffer_WID (24)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_0_Pattern_Buffer_MSK (0x00FFFFFF)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_0_Pattern_Buffer_MAX (0x00FFFFFF)
+
+#define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_1_REG             (0x0000404C)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_1_Pattern_Buffer_OFF ( 0)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_1_Pattern_Buffer_WID (24)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_1_Pattern_Buffer_MSK (0x00FFFFFF)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_1_Pattern_Buffer_MAX (0x00FFFFFF)
+
+#define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_2_REG             (0x00004050)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_2_Pattern_Buffer_OFF ( 0)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_2_Pattern_Buffer_WID (24)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_2_Pattern_Buffer_MSK (0x00FFFFFF)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_2_Pattern_Buffer_MAX (0x00FFFFFF)
+
+#define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_0_REG             (0x00004054)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_0_Pattern_Buffer_OFF ( 0)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_0_Pattern_Buffer_WID (24)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_0_Pattern_Buffer_MSK (0x00FFFFFF)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_0_Pattern_Buffer_MAX (0x00FFFFFF)
+
+#define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_1_REG             (0x00004058)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_1_Pattern_Buffer_OFF ( 0)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_1_Pattern_Buffer_WID (24)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_1_Pattern_Buffer_MSK (0x00FFFFFF)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_1_Pattern_Buffer_MAX (0x00FFFFFF)
+
+#define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_2_REG             (0x0000405C)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_2_Pattern_Buffer_OFF ( 0)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_2_Pattern_Buffer_WID (24)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_2_Pattern_Buffer_MSK (0x00FFFFFF)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_2_Pattern_Buffer_MAX (0x00FFFFFF)
+
+#define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_0_REG      (0x00004060)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_0_Pattern_Buffer_OFF ( 0)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_0_Pattern_Buffer_WID (24)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_0_Pattern_Buffer_MSK (0x00FFFFFF)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_0_Pattern_Buffer_MAX (0x00FFFFFF)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_0_Pattern_Buffer_DEF (0x00000000)
+
+#define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_1_REG      (0x00004064)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_1_Pattern_Buffer_OFF ( 0)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_1_Pattern_Buffer_WID (24)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_1_Pattern_Buffer_MSK (0x00FFFFFF)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_1_Pattern_Buffer_MAX (0x00FFFFFF)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_1_Pattern_Buffer_DEF (0x00000000)
+
+#define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_2_REG      (0x00004068)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_2_Pattern_Buffer_OFF ( 0)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_2_Pattern_Buffer_WID (24)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_2_Pattern_Buffer_MSK (0x00FFFFFF)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_2_Pattern_Buffer_MAX (0x00FFFFFF)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_2_Pattern_Buffer_DEF (0x00000000)
+
+#define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_0_REG      (0x0000406C)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_0_Pattern_Buffer_OFF ( 0)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_0_Pattern_Buffer_WID (24)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_0_Pattern_Buffer_MSK (0x00FFFFFF)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_0_Pattern_Buffer_MAX (0x00FFFFFF)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_0_Pattern_Buffer_DEF (0x00000000)
+
+#define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_1_REG      (0x00004070)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_1_Pattern_Buffer_OFF ( 0)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_1_Pattern_Buffer_WID (24)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_1_Pattern_Buffer_MSK (0x00FFFFFF)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_1_Pattern_Buffer_MAX (0x00FFFFFF)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_1_Pattern_Buffer_DEF (0x00000000)
+
+#define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_2_REG      (0x00004074)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_2_Pattern_Buffer_OFF ( 0)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_2_Pattern_Buffer_WID (24)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_2_Pattern_Buffer_MSK (0x00FFFFFF)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_2_Pattern_Buffer_MAX (0x00FFFFFF)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_2_Pattern_Buffer_DEF (0x00000000)
+
+#define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_REG                 (0x00004078)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_L_data_select_OFF   ( 0)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_L_data_select_WID   ( 1)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_L_data_select_MSK   (0x00000001)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_L_data_select_MAX   (0x00000001)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_L_data_select_DEF   (0x00000000)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_Enable_Sweep_Frequency_OFF ( 1)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_Enable_Sweep_Frequency_WID ( 1)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_Enable_Sweep_Frequency_MSK (0x00000002)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_Enable_Sweep_Frequency_MAX (0x00000001)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_Enable_Sweep_Frequency_DEF (0x00000000)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_L_counter_OFF       ( 8)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_L_counter_WID       ( 8)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_L_counter_MSK       (0x0000FF00)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_L_counter_MAX       (0x000000FF)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_L_counter_DEF       (0x00000001)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_M_counter_OFF       (16)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_M_counter_WID       ( 8)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_M_counter_MSK       (0x00FF0000)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_M_counter_MAX       (0x000000FF)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_M_counter_DEF       (0x00000001)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_N_counter_OFF       (24)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_N_counter_WID       ( 8)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_N_counter_MSK       (0xFF000000)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_N_counter_MAX       (0x000000FF)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_N_counter_DEF       (0x00000001)
+
+#define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_INV_REG                        (0x00004084)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_INV_ECC_Inv_or_DC_Enable_OFF   ( 0)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_INV_ECC_Inv_or_DC_Enable_WID   ( 8)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_INV_ECC_Inv_or_DC_Enable_MSK   (0x000000FF)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_INV_ECC_Inv_or_DC_Enable_MAX   (0x000000FF)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_INV_ECC_Inv_or_DC_Enable_DEF   (0x00000000)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_INV_Inv_or_DC_Shift_Rate_OFF   (16)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_INV_Inv_or_DC_Shift_Rate_WID   ( 4)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_INV_Inv_or_DC_Shift_Rate_MSK   (0x000F0000)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_INV_Inv_or_DC_Shift_Rate_MAX   (0x0000000F)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_INV_Inv_or_DC_Shift_Rate_DEF   (0x00000000)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_INV_DC_Polarity_Control_OFF    (20)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_INV_DC_Polarity_Control_WID    ( 1)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_INV_DC_Polarity_Control_MSK    (0x00100000)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_INV_DC_Polarity_Control_MAX    (0x00000001)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_INV_DC_Polarity_Control_DEF    (0x00000000)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_INV_Inv_or_DC_Control_OFF      (30)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_INV_Inv_or_DC_Control_WID      ( 1)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_INV_Inv_or_DC_Control_MSK      (0x40000000)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_INV_Inv_or_DC_Control_MAX      (0x00000001)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_INV_Inv_or_DC_Control_DEF      (0x00000000)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_INV_Inv_or_DC_Shift_Enable_OFF (31)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_INV_Inv_or_DC_Shift_Enable_WID ( 1)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_INV_Inv_or_DC_Shift_Enable_MSK (0x80000000)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_INV_Inv_or_DC_Shift_Enable_MAX (0x00000001)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_INV_Inv_or_DC_Shift_Enable_DEF (0x00000000)
+
+#define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_DATA_INV_REG                   (0x00004090)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_DATA_INV_Data_Inv_or_DC_Enable_OFF ( 0)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_DATA_INV_Data_Inv_or_DC_Enable_WID (64)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_DATA_INV_Data_Inv_or_DC_Enable_MSK (0xFFFFFFFFFFFFFFFF)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_DATA_INV_Data_Inv_or_DC_Enable_MAX (0xFFFFFFFFFFFFFFFF)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_DATA_INV_Data_Inv_or_DC_Enable_DEF (0x00000000)
+
+#define MCHBAR_CH0_CR_REUT_CH_ERR_CTL_REG                            (0x00004098)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_CTL_Stop_on_Nth_Error_OFF          ( 0)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_CTL_Stop_on_Nth_Error_WID          ( 6)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_CTL_Stop_on_Nth_Error_MSK          (0x0000003F)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_CTL_Stop_on_Nth_Error_MAX          (0x0000003F)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_CTL_Stop_on_Nth_Error_DEF          (0x00000001)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_CTL_Stop_On_Error_Control_OFF      (12)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_CTL_Stop_On_Error_Control_WID      ( 2)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_CTL_Stop_On_Error_Control_MSK      (0x00003000)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_CTL_Stop_On_Error_Control_MAX      (0x00000003)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_CTL_Stop_On_Error_Control_DEF      (0x00000000)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_CTL_Selective_Error_Enable_Chunk_OFF (16)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_CTL_Selective_Error_Enable_Chunk_WID ( 8)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_CTL_Selective_Error_Enable_Chunk_MSK (0x00FF0000)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_CTL_Selective_Error_Enable_Chunk_MAX (0x000000FF)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_CTL_Selective_Error_Enable_Chunk_DEF (0x000000FF)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_CTL_Selective_Error_Enable_Cacheline_OFF (24)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_CTL_Selective_Error_Enable_Cacheline_WID ( 8)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_CTL_Selective_Error_Enable_Cacheline_MSK (0xFF000000)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_CTL_Selective_Error_Enable_Cacheline_MAX (0x000000FF)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_CTL_Selective_Error_Enable_Cacheline_DEF (0x000000FF)
+
+#define MCHBAR_CH0_CR_REUT_CH_ERR_ECC_MASK_REG                       (0x0000409C)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_ECC_MASK_ECC_Error_Mask_OFF        ( 0)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_ECC_MASK_ECC_Error_Mask_WID        ( 8)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_ECC_MASK_ECC_Error_Mask_MSK        (0x000000FF)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_ECC_MASK_ECC_Error_Mask_MAX        (0x000000FF)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_ECC_MASK_ECC_Error_Mask_DEF        (0x00000000)
+
+#define MCHBAR_CH0_CR_STM_CONFIG_REG                                 (0x000040A4)
+  #define MCHBAR_CH0_CR_STM_CONFIG_Stretch_mode_OFF                    ( 0)
+  #define MCHBAR_CH0_CR_STM_CONFIG_Stretch_mode_WID                    ( 2)
+  #define MCHBAR_CH0_CR_STM_CONFIG_Stretch_mode_MSK                    (0x00000003)
+  #define MCHBAR_CH0_CR_STM_CONFIG_Stretch_mode_MAX                    (0x00000003)
+  #define MCHBAR_CH0_CR_STM_CONFIG_Stretch_mode_DEF                    (0x00000000)
+  #define MCHBAR_CH0_CR_STM_CONFIG_STF_OFF                             ( 4)
+  #define MCHBAR_CH0_CR_STM_CONFIG_STF_WID                             ( 3)
+  #define MCHBAR_CH0_CR_STM_CONFIG_STF_MSK                             (0x00000070)
+  #define MCHBAR_CH0_CR_STM_CONFIG_STF_MAX                             (0x00000007)
+  #define MCHBAR_CH0_CR_STM_CONFIG_STF_DEF                             (0x00000000)
+
+#define MCHBAR_CH0_CR_SC_PR_CNT_CONFIG_REG                           (0x000040A8)
+  #define MCHBAR_CH0_CR_SC_PR_CNT_CONFIG_Priority_count_ring_OFF       ( 0)
+  #define MCHBAR_CH0_CR_SC_PR_CNT_CONFIG_Priority_count_ring_WID       (10)
+  #define MCHBAR_CH0_CR_SC_PR_CNT_CONFIG_Priority_count_ring_MSK       (0x000003FF)
+  #define MCHBAR_CH0_CR_SC_PR_CNT_CONFIG_Priority_count_ring_MAX       (0x000003FF)
+  #define MCHBAR_CH0_CR_SC_PR_CNT_CONFIG_Priority_count_ring_DEF       (0x00000040)
+  #define MCHBAR_CH0_CR_SC_PR_CNT_CONFIG_Priority_count_SA_OFF         (16)
+  #define MCHBAR_CH0_CR_SC_PR_CNT_CONFIG_Priority_count_SA_WID         (10)
+  #define MCHBAR_CH0_CR_SC_PR_CNT_CONFIG_Priority_count_SA_MSK         (0x03FF0000)
+  #define MCHBAR_CH0_CR_SC_PR_CNT_CONFIG_Priority_count_SA_MAX         (0x000003FF)
+  #define MCHBAR_CH0_CR_SC_PR_CNT_CONFIG_Priority_count_SA_DEF         (0x00000100)
+
+#define MCHBAR_CH0_CR_SC_PCIT_REG                                    (0x000040AC)
+  #define MCHBAR_CH0_CR_SC_PCIT_PCIT_OFF                               ( 0)
+  #define MCHBAR_CH0_CR_SC_PCIT_PCIT_WID                               ( 8)
+  #define MCHBAR_CH0_CR_SC_PCIT_PCIT_MSK                               (0x000000FF)
+  #define MCHBAR_CH0_CR_SC_PCIT_PCIT_MAX                               (0x000000FF)
+  #define MCHBAR_CH0_CR_SC_PCIT_PCIT_DEF                               (0x00000040)
+
+#define MCHBAR_CH0_CR_PM_PDWN_CONFIG_REG                             (0x000040B0)
+  #define MCHBAR_CH0_CR_PM_PDWN_CONFIG_PDWN_idle_counter_OFF           ( 0)
+  #define MCHBAR_CH0_CR_PM_PDWN_CONFIG_PDWN_idle_counter_WID           (12)
+  #define MCHBAR_CH0_CR_PM_PDWN_CONFIG_PDWN_idle_counter_MSK           (0x00000FFF)
+  #define MCHBAR_CH0_CR_PM_PDWN_CONFIG_PDWN_idle_counter_MAX           (0x00000FFF)
+  #define MCHBAR_CH0_CR_PM_PDWN_CONFIG_PDWN_idle_counter_DEF           (0x00000000)
+  #define MCHBAR_CH0_CR_PM_PDWN_CONFIG_PDWN_mode_OFF                   (12)
+  #define MCHBAR_CH0_CR_PM_PDWN_CONFIG_PDWN_mode_WID                   ( 4)
+  #define MCHBAR_CH0_CR_PM_PDWN_CONFIG_PDWN_mode_MSK                   (0x0000F000)
+  #define MCHBAR_CH0_CR_PM_PDWN_CONFIG_PDWN_mode_MAX                   (0x0000000F)
+  #define MCHBAR_CH0_CR_PM_PDWN_CONFIG_PDWN_mode_DEF                   (0x00000000)
+
+#define MCHBAR_CH0_CR_ECC_INJECT_COUNT_REG                           (0x000040B4)
+  #define MCHBAR_CH0_CR_ECC_INJECT_COUNT_Count_OFF                     ( 0)
+  #define MCHBAR_CH0_CR_ECC_INJECT_COUNT_Count_WID                     (32)
+  #define MCHBAR_CH0_CR_ECC_INJECT_COUNT_Count_MSK                     (0xFFFFFFFF)
+  #define MCHBAR_CH0_CR_ECC_INJECT_COUNT_Count_MAX                     (0xFFFFFFFF)
+  #define MCHBAR_CH0_CR_ECC_INJECT_COUNT_Count_DEF                     (0xFFFFFFFF)
+
+#define MCHBAR_CH0_CR_ECC_DFT_REG                                    (0x000040B8)
+  #define MCHBAR_CH0_CR_ECC_DFT_ECC4ANA_fill_OFF                       ( 0)
+  #define MCHBAR_CH0_CR_ECC_DFT_ECC4ANA_fill_WID                       ( 8)
+  #define MCHBAR_CH0_CR_ECC_DFT_ECC4ANA_fill_MSK                       (0x000000FF)
+  #define MCHBAR_CH0_CR_ECC_DFT_ECC4ANA_fill_MAX                       (0x000000FF)
+  #define MCHBAR_CH0_CR_ECC_DFT_ECC4ANA_fill_DEF                       (0x00000000)
+  #define MCHBAR_CH0_CR_ECC_DFT_ECC4ANA_trigger_OFF                    ( 8)
+  #define MCHBAR_CH0_CR_ECC_DFT_ECC4ANA_trigger_WID                    ( 2)
+  #define MCHBAR_CH0_CR_ECC_DFT_ECC4ANA_trigger_MSK                    (0x00000300)
+  #define MCHBAR_CH0_CR_ECC_DFT_ECC4ANA_trigger_MAX                    (0x00000003)
+  #define MCHBAR_CH0_CR_ECC_DFT_ECC4ANA_trigger_DEF                    (0x00000000)
+  #define MCHBAR_CH0_CR_ECC_DFT_ECC4ANA_BS_OFF                         (10)
+  #define MCHBAR_CH0_CR_ECC_DFT_ECC4ANA_BS_WID                         ( 1)
+  #define MCHBAR_CH0_CR_ECC_DFT_ECC4ANA_BS_MSK                         (0x00000400)
+  #define MCHBAR_CH0_CR_ECC_DFT_ECC4ANA_BS_MAX                         (0x00000001)
+  #define MCHBAR_CH0_CR_ECC_DFT_ECC4ANA_BS_DEF                         (0x00000000)
+  #define MCHBAR_CH0_CR_ECC_DFT_ECC_Inject_OFF                         (11)
+  #define MCHBAR_CH0_CR_ECC_DFT_ECC_Inject_WID                         ( 3)
+  #define MCHBAR_CH0_CR_ECC_DFT_ECC_Inject_MSK                         (0x00003800)
+  #define MCHBAR_CH0_CR_ECC_DFT_ECC_Inject_MAX                         (0x00000007)
+  #define MCHBAR_CH0_CR_ECC_DFT_ECC_Inject_DEF                         (0x00000000)
+  #define MCHBAR_CH0_CR_ECC_DFT_ECC_correction_disable_OFF             (14)
+  #define MCHBAR_CH0_CR_ECC_DFT_ECC_correction_disable_WID             ( 1)
+  #define MCHBAR_CH0_CR_ECC_DFT_ECC_correction_disable_MSK             (0x00004000)
+  #define MCHBAR_CH0_CR_ECC_DFT_ECC_correction_disable_MAX             (0x00000001)
+  #define MCHBAR_CH0_CR_ECC_DFT_ECC_correction_disable_DEF             (0x00000000)
+  #define MCHBAR_CH0_CR_ECC_DFT_ECC4ANA_Inject_OFF                     (15)
+  #define MCHBAR_CH0_CR_ECC_DFT_ECC4ANA_Inject_WID                     ( 1)
+  #define MCHBAR_CH0_CR_ECC_DFT_ECC4ANA_Inject_MSK                     (0x00008000)
+  #define MCHBAR_CH0_CR_ECC_DFT_ECC4ANA_Inject_MAX                     (0x00000001)
+  #define MCHBAR_CH0_CR_ECC_DFT_ECC4ANA_Inject_DEF                     (0x00000000)
+  #define MCHBAR_CH0_CR_ECC_DFT_DIS_MCA_LOG_OFF                        (16)
+  #define MCHBAR_CH0_CR_ECC_DFT_DIS_MCA_LOG_WID                        ( 1)
+  #define MCHBAR_CH0_CR_ECC_DFT_DIS_MCA_LOG_MSK                        (0x00010000)
+  #define MCHBAR_CH0_CR_ECC_DFT_DIS_MCA_LOG_MAX                        (0x00000001)
+  #define MCHBAR_CH0_CR_ECC_DFT_DIS_MCA_LOG_DEF                        (0x00000000)
+  #define MCHBAR_CH0_CR_ECC_DFT_DIS_PCH_EVENT_OFF                      (17)
+  #define MCHBAR_CH0_CR_ECC_DFT_DIS_PCH_EVENT_WID                      ( 1)
+  #define MCHBAR_CH0_CR_ECC_DFT_DIS_PCH_EVENT_MSK                      (0x00020000)
+  #define MCHBAR_CH0_CR_ECC_DFT_DIS_PCH_EVENT_MAX                      (0x00000001)
+  #define MCHBAR_CH0_CR_ECC_DFT_DIS_PCH_EVENT_DEF                      (0x00000000)
+  #define MCHBAR_CH0_CR_ECC_DFT_DIS_PCIE_POISON_OFF                    (18)
+  #define MCHBAR_CH0_CR_ECC_DFT_DIS_PCIE_POISON_WID                    ( 1)
+  #define MCHBAR_CH0_CR_ECC_DFT_DIS_PCIE_POISON_MSK                    (0x00040000)
+  #define MCHBAR_CH0_CR_ECC_DFT_DIS_PCIE_POISON_MAX                    (0x00000001)
+  #define MCHBAR_CH0_CR_ECC_DFT_DIS_PCIE_POISON_DEF                    (0x00000000)
+
+#define MCHBAR_CH0_CR_VISA_CTL_MCSCHEDS_REG                          (0x000040C0)
+  #define MCHBAR_CH0_CR_VISA_CTL_MCSCHEDS_Data_OFF                     ( 0)
+  #define MCHBAR_CH0_CR_VISA_CTL_MCSCHEDS_Data_WID                     (18)
+  #define MCHBAR_CH0_CR_VISA_CTL_MCSCHEDS_Data_MSK                     (0x0003FFFF)
+  #define MCHBAR_CH0_CR_VISA_CTL_MCSCHEDS_Data_MAX                     (0x0003FFFF)
+  #define MCHBAR_CH0_CR_VISA_CTL_MCSCHEDS_Data_DEF                     (0x00000000)
+  #define MCHBAR_CH0_CR_VISA_CTL_MCSCHEDS_VORANGE_OFF                  (31)
+  #define MCHBAR_CH0_CR_VISA_CTL_MCSCHEDS_VORANGE_WID                  ( 1)
+  #define MCHBAR_CH0_CR_VISA_CTL_MCSCHEDS_VORANGE_MSK                  (0x80000000)
+  #define MCHBAR_CH0_CR_VISA_CTL_MCSCHEDS_VORANGE_MAX                  (0x00000001)
+  #define MCHBAR_CH0_CR_VISA_CTL_MCSCHEDS_VORANGE_DEF                  (0x00000000)
+
+#define MCHBAR_CH0_CR_VISA_XBAR_MCSCHEDS_REG                         (0x000040C4)
+  #define MCHBAR_CH0_CR_VISA_XBAR_MCSCHEDS_Data_OFF                    ( 0)
+  #define MCHBAR_CH0_CR_VISA_XBAR_MCSCHEDS_Data_WID                    (32)
+  #define MCHBAR_CH0_CR_VISA_XBAR_MCSCHEDS_Data_MSK                    (0xFFFFFFFF)
+  #define MCHBAR_CH0_CR_VISA_XBAR_MCSCHEDS_Data_MAX                    (0xFFFFFFFF)
+  #define MCHBAR_CH0_CR_VISA_XBAR_MCSCHEDS_Data_DEF                    (0x76543210)
+
+#define MCHBAR_CH0_CR_ECCERRLOG0_REG                                 (0x000040C8)
+  #define MCHBAR_CH0_CR_ECCERRLOG0_CERRSTS_OFF                         ( 0)
+  #define MCHBAR_CH0_CR_ECCERRLOG0_CERRSTS_WID                         ( 1)
+  #define MCHBAR_CH0_CR_ECCERRLOG0_CERRSTS_MSK                         (0x00000001)
+  #define MCHBAR_CH0_CR_ECCERRLOG0_CERRSTS_MAX                         (0x00000001)
+  #define MCHBAR_CH0_CR_ECCERRLOG0_CERRSTS_DEF                         (0x00000000)
+  #define MCHBAR_CH0_CR_ECCERRLOG0_MERRSTS_OFF                         ( 1)
+  #define MCHBAR_CH0_CR_ECCERRLOG0_MERRSTS_WID                         ( 1)
+  #define MCHBAR_CH0_CR_ECCERRLOG0_MERRSTS_MSK                         (0x00000002)
+  #define MCHBAR_CH0_CR_ECCERRLOG0_MERRSTS_MAX                         (0x00000001)
+  #define MCHBAR_CH0_CR_ECCERRLOG0_MERRSTS_DEF                         (0x00000000)
+  #define MCHBAR_CH0_CR_ECCERRLOG0_ERRSYND_OFF                         (16)
+  #define MCHBAR_CH0_CR_ECCERRLOG0_ERRSYND_WID                         ( 8)
+  #define MCHBAR_CH0_CR_ECCERRLOG0_ERRSYND_MSK                         (0x00FF0000)
+  #define MCHBAR_CH0_CR_ECCERRLOG0_ERRSYND_MAX                         (0x000000FF)
+  #define MCHBAR_CH0_CR_ECCERRLOG0_ERRSYND_DEF                         (0x00000000)
+  #define MCHBAR_CH0_CR_ECCERRLOG0_ERRCHUNK_OFF                        (24)
+  #define MCHBAR_CH0_CR_ECCERRLOG0_ERRCHUNK_WID                        ( 3)
+  #define MCHBAR_CH0_CR_ECCERRLOG0_ERRCHUNK_MSK                        (0x07000000)
+  #define MCHBAR_CH0_CR_ECCERRLOG0_ERRCHUNK_MAX                        (0x00000007)
+  #define MCHBAR_CH0_CR_ECCERRLOG0_ERRCHUNK_DEF                        (0x00000000)
+  #define MCHBAR_CH0_CR_ECCERRLOG0_ERRRANK_OFF                         (27)
+  #define MCHBAR_CH0_CR_ECCERRLOG0_ERRRANK_WID                         ( 2)
+  #define MCHBAR_CH0_CR_ECCERRLOG0_ERRRANK_MSK                         (0x18000000)
+  #define MCHBAR_CH0_CR_ECCERRLOG0_ERRRANK_MAX                         (0x00000003)
+  #define MCHBAR_CH0_CR_ECCERRLOG0_ERRRANK_DEF                         (0x00000000)
+  #define MCHBAR_CH0_CR_ECCERRLOG0_ERRBANK_OFF                         (29)
+  #define MCHBAR_CH0_CR_ECCERRLOG0_ERRBANK_WID                         ( 3)
+  #define MCHBAR_CH0_CR_ECCERRLOG0_ERRBANK_MSK                         (0xE0000000)
+  #define MCHBAR_CH0_CR_ECCERRLOG0_ERRBANK_MAX                         (0x00000007)
+  #define MCHBAR_CH0_CR_ECCERRLOG0_ERRBANK_DEF                         (0x00000000)
+
+#define MCHBAR_CH0_CR_ECCERRLOG1_REG                                 (0x000040CC)
+  #define MCHBAR_CH0_CR_ECCERRLOG1_ERRROW_OFF                          ( 0)
+  #define MCHBAR_CH0_CR_ECCERRLOG1_ERRROW_WID                          (16)
+  #define MCHBAR_CH0_CR_ECCERRLOG1_ERRROW_MSK                          (0x0000FFFF)
+  #define MCHBAR_CH0_CR_ECCERRLOG1_ERRROW_MAX                          (0x0000FFFF)
+  #define MCHBAR_CH0_CR_ECCERRLOG1_ERRROW_DEF                          (0x00000000)
+  #define MCHBAR_CH0_CR_ECCERRLOG1_ERRCOL_OFF                          (16)
+  #define MCHBAR_CH0_CR_ECCERRLOG1_ERRCOL_WID                          (16)
+  #define MCHBAR_CH0_CR_ECCERRLOG1_ERRCOL_MSK                          (0xFFFF0000)
+  #define MCHBAR_CH0_CR_ECCERRLOG1_ERRCOL_MAX                          (0x0000FFFF)
+  #define MCHBAR_CH0_CR_ECCERRLOG1_ERRCOL_DEF                          (0x00000000)
+
+#define MCHBAR_CH0_CR_SC_WR_ADD_DELAY_REG                            (0x000040D0)
+  #define MCHBAR_CH0_CR_SC_WR_ADD_DELAY_D0R0_OFF                       ( 0)
+  #define MCHBAR_CH0_CR_SC_WR_ADD_DELAY_D0R0_WID                       ( 2)
+  #define MCHBAR_CH0_CR_SC_WR_ADD_DELAY_D0R0_MSK                       (0x00000003)
+  #define MCHBAR_CH0_CR_SC_WR_ADD_DELAY_D0R0_MAX                       (0x00000003)
+  #define MCHBAR_CH0_CR_SC_WR_ADD_DELAY_D0R0_DEF                       (0x00000000)
+  #define MCHBAR_CH0_CR_SC_WR_ADD_DELAY_D0R1_OFF                       ( 2)
+  #define MCHBAR_CH0_CR_SC_WR_ADD_DELAY_D0R1_WID                       ( 2)
+  #define MCHBAR_CH0_CR_SC_WR_ADD_DELAY_D0R1_MSK                       (0x0000000C)
+  #define MCHBAR_CH0_CR_SC_WR_ADD_DELAY_D0R1_MAX                       (0x00000003)
+  #define MCHBAR_CH0_CR_SC_WR_ADD_DELAY_D0R1_DEF                       (0x00000000)
+  #define MCHBAR_CH0_CR_SC_WR_ADD_DELAY_D1R0_OFF                       ( 4)
+  #define MCHBAR_CH0_CR_SC_WR_ADD_DELAY_D1R0_WID                       ( 2)
+  #define MCHBAR_CH0_CR_SC_WR_ADD_DELAY_D1R0_MSK                       (0x00000030)
+  #define MCHBAR_CH0_CR_SC_WR_ADD_DELAY_D1R0_MAX                       (0x00000003)
+  #define MCHBAR_CH0_CR_SC_WR_ADD_DELAY_D1R0_DEF                       (0x00000000)
+  #define MCHBAR_CH0_CR_SC_WR_ADD_DELAY_D1R1_OFF                       ( 6)
+  #define MCHBAR_CH0_CR_SC_WR_ADD_DELAY_D1R1_WID                       ( 2)
+  #define MCHBAR_CH0_CR_SC_WR_ADD_DELAY_D1R1_MSK                       (0x000000C0)
+  #define MCHBAR_CH0_CR_SC_WR_ADD_DELAY_D1R1_MAX                       (0x00000003)
+  #define MCHBAR_CH0_CR_SC_WR_ADD_DELAY_D1R1_DEF                       (0x00000000)
+
+#define MCHBAR_CH0_CR_WMM_READ_CONFIG_REG                            (0x000040D4)
+  #define MCHBAR_CH0_CR_WMM_READ_CONFIG_Dis_Opp_rd_OFF                 ( 0)
+  #define MCHBAR_CH0_CR_WMM_READ_CONFIG_Dis_Opp_rd_WID                 ( 1)
+  #define MCHBAR_CH0_CR_WMM_READ_CONFIG_Dis_Opp_rd_MSK                 (0x00000001)
+  #define MCHBAR_CH0_CR_WMM_READ_CONFIG_Dis_Opp_rd_MAX                 (0x00000001)
+  #define MCHBAR_CH0_CR_WMM_READ_CONFIG_Dis_Opp_rd_DEF                 (0x00000000)
+  #define MCHBAR_CH0_CR_WMM_READ_CONFIG_ACT_Enable_OFF                 ( 1)
+  #define MCHBAR_CH0_CR_WMM_READ_CONFIG_ACT_Enable_WID                 ( 1)
+  #define MCHBAR_CH0_CR_WMM_READ_CONFIG_ACT_Enable_MSK                 (0x00000002)
+  #define MCHBAR_CH0_CR_WMM_READ_CONFIG_ACT_Enable_MAX                 (0x00000001)
+  #define MCHBAR_CH0_CR_WMM_READ_CONFIG_ACT_Enable_DEF                 (0x00000001)
+  #define MCHBAR_CH0_CR_WMM_READ_CONFIG_PRE_Enable_OFF                 ( 2)
+  #define MCHBAR_CH0_CR_WMM_READ_CONFIG_PRE_Enable_WID                 ( 1)
+  #define MCHBAR_CH0_CR_WMM_READ_CONFIG_PRE_Enable_MSK                 (0x00000004)
+  #define MCHBAR_CH0_CR_WMM_READ_CONFIG_PRE_Enable_MAX                 (0x00000001)
+  #define MCHBAR_CH0_CR_WMM_READ_CONFIG_PRE_Enable_DEF                 (0x00000001)
+  #define MCHBAR_CH0_CR_WMM_READ_CONFIG_MAX_RPQ_Cas_OFF                ( 3)
+  #define MCHBAR_CH0_CR_WMM_READ_CONFIG_MAX_RPQ_Cas_WID                ( 4)
+  #define MCHBAR_CH0_CR_WMM_READ_CONFIG_MAX_RPQ_Cas_MSK                (0x00000078)
+  #define MCHBAR_CH0_CR_WMM_READ_CONFIG_MAX_RPQ_Cas_MAX                (0x0000000F)
+  #define MCHBAR_CH0_CR_WMM_READ_CONFIG_MAX_RPQ_Cas_DEF                (0x00000008)
+
+#define MCHBAR_CH0_CR_REUT_CH_ERR_DATA_MASK_REG                      (0x000040D8)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_DATA_MASK_Data_Error_Mask_OFF      ( 0)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_DATA_MASK_Data_Error_Mask_WID      (64)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_DATA_MASK_Data_Error_Mask_MSK      (0xFFFFFFFFFFFFFFFF)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_DATA_MASK_Data_Error_Mask_MAX      (0xFFFFFFFFFFFFFFFF)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_DATA_MASK_Data_Error_Mask_DEF      (0x00000000)
+
+#define MCHBAR_CH0_CR_REUT_CH_ERR_DATA_STATUS_REG                    (0x000040E0)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_DATA_STATUS_Data_Error_Status_OFF  ( 0)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_DATA_STATUS_Data_Error_Status_WID  (64)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_DATA_STATUS_Data_Error_Status_MSK  (0xFFFFFFFFFFFFFFFF)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_DATA_STATUS_Data_Error_Status_MAX  (0xFFFFFFFFFFFFFFFF)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_DATA_STATUS_Data_Error_Status_DEF  (0x00000000)
+
+#define MCHBAR_CH0_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_REG (0x000040E8)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_ECC_Error_Status_OFF ( 0)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_ECC_Error_Status_WID ( 8)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_ECC_Error_Status_MSK (0x000000FF)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_ECC_Error_Status_MAX (0x000000FF)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_ECC_Error_Status_DEF (0x00000000)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Chunk_Error_Status_OFF ( 8)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Chunk_Error_Status_WID ( 8)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Chunk_Error_Status_MSK (0x0000FF00)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Chunk_Error_Status_MAX (0x000000FF)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Chunk_Error_Status_DEF (0x00000000)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Rank_Error_Status_OFF (16)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Rank_Error_Status_WID ( 4)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Rank_Error_Status_MSK (0x000F0000)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Rank_Error_Status_MAX (0x0000000F)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Rank_Error_Status_DEF (0x00000000)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Byte_Group_Error_Status_OFF (32)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Byte_Group_Error_Status_WID ( 9)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Byte_Group_Error_Status_MSK (0x1FF00000000)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Byte_Group_Error_Status_MAX (0x000001FF)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Byte_Group_Error_Status_DEF (0x00000000)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_WDB_Rd_Chunk_Num_Status_OFF (52)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_WDB_Rd_Chunk_Num_Status_WID ( 3)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_WDB_Rd_Chunk_Num_Status_MSK (0x70000000000000)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_WDB_Rd_Chunk_Num_Status_MAX (0x00000007)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_WDB_Rd_Chunk_Num_Status_DEF (0x00000000)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Nth_Error_OFF (56)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Nth_Error_WID ( 6)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Nth_Error_MSK (0x3F00000000000000)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Nth_Error_MAX (0x0000003F)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Nth_Error_DEF (0x00000000)
+
+#define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_0_REG                  (0x000040F0)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_0_Counter_Pointer_OFF  ( 0)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_0_Counter_Pointer_WID  ( 7)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_0_Counter_Pointer_MSK  (0x0000007F)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_0_Counter_Pointer_MAX  (0x0000007F)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_0_Counter_Pointer_DEF  (0x0000007F)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_0_Counter_Control_OFF  ( 7)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_0_Counter_Control_WID  ( 2)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_0_Counter_Control_MSK  (0x00000180)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_0_Counter_Control_MAX  (0x00000003)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_0_Counter_Control_DEF  (0x00000000)
+
+#define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_1_REG                  (0x000040F4)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_1_Counter_Pointer_OFF  ( 0)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_1_Counter_Pointer_WID  ( 7)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_1_Counter_Pointer_MSK  (0x0000007F)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_1_Counter_Pointer_MAX  (0x0000007F)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_1_Counter_Pointer_DEF  (0x0000007F)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_1_Counter_Control_OFF  ( 7)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_1_Counter_Control_WID  ( 2)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_1_Counter_Control_MSK  (0x00000180)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_1_Counter_Control_MAX  (0x00000003)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_1_Counter_Control_DEF  (0x00000000)
+
+#define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_2_REG                  (0x000040F8)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_2_Counter_Pointer_OFF  ( 0)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_2_Counter_Pointer_WID  ( 7)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_2_Counter_Pointer_MSK  (0x0000007F)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_2_Counter_Pointer_MAX  (0x0000007F)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_2_Counter_Pointer_DEF  (0x0000007F)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_2_Counter_Control_OFF  ( 7)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_2_Counter_Control_WID  ( 2)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_2_Counter_Control_MSK  (0x00000180)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_2_Counter_Control_MAX  (0x00000003)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_2_Counter_Control_DEF  (0x00000000)
+
+#define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_3_REG                  (0x000040FC)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_3_Counter_Pointer_OFF  ( 0)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_3_Counter_Pointer_WID  ( 7)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_3_Counter_Pointer_MSK  (0x0000007F)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_3_Counter_Pointer_MAX  (0x0000007F)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_3_Counter_Pointer_DEF  (0x0000007F)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_3_Counter_Control_OFF  ( 7)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_3_Counter_Control_WID  ( 2)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_3_Counter_Control_MSK  (0x00000180)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_3_Counter_Control_MAX  (0x00000003)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_3_Counter_Control_DEF  (0x00000000)
+
+#define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_4_REG                  (0x00004100)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_4_Counter_Pointer_OFF  ( 0)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_4_Counter_Pointer_WID  ( 7)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_4_Counter_Pointer_MSK  (0x0000007F)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_4_Counter_Pointer_MAX  (0x0000007F)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_4_Counter_Pointer_DEF  (0x0000007F)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_4_Counter_Control_OFF  ( 7)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_4_Counter_Control_WID  ( 2)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_4_Counter_Control_MSK  (0x00000180)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_4_Counter_Control_MAX  (0x00000003)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_4_Counter_Control_DEF  (0x00000000)
+
+#define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_5_REG                  (0x00004104)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_5_Counter_Pointer_OFF  ( 0)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_5_Counter_Pointer_WID  ( 7)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_5_Counter_Pointer_MSK  (0x0000007F)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_5_Counter_Pointer_MAX  (0x0000007F)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_5_Counter_Pointer_DEF  (0x0000007F)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_5_Counter_Control_OFF  ( 7)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_5_Counter_Control_WID  ( 2)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_5_Counter_Control_MSK  (0x00000180)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_5_Counter_Control_MAX  (0x00000003)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_5_Counter_Control_DEF  (0x00000000)
+
+#define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_6_REG                  (0x00004108)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_6_Counter_Pointer_OFF  ( 0)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_6_Counter_Pointer_WID  ( 7)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_6_Counter_Pointer_MSK  (0x0000007F)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_6_Counter_Pointer_MAX  (0x0000007F)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_6_Counter_Pointer_DEF  (0x0000007F)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_6_Counter_Control_OFF  ( 7)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_6_Counter_Control_WID  ( 2)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_6_Counter_Control_MSK  (0x00000180)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_6_Counter_Control_MAX  (0x00000003)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_6_Counter_Control_DEF  (0x00000000)
+
+#define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_7_REG                  (0x0000410C)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_7_Counter_Pointer_OFF  ( 0)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_7_Counter_Pointer_WID  ( 7)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_7_Counter_Pointer_MSK  (0x0000007F)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_7_Counter_Pointer_MAX  (0x0000007F)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_7_Counter_Pointer_DEF  (0x0000007F)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_7_Counter_Control_OFF  ( 7)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_7_Counter_Control_WID  ( 2)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_7_Counter_Control_MSK  (0x00000180)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_7_Counter_Control_MAX  (0x00000003)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_7_Counter_Control_DEF  (0x00000000)
+
+#define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_8_REG                  (0x00004110)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_8_Counter_Pointer_OFF  ( 0)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_8_Counter_Pointer_WID  ( 7)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_8_Counter_Pointer_MSK  (0x0000007F)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_8_Counter_Pointer_MAX  (0x0000007F)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_8_Counter_Pointer_DEF  (0x0000007F)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_8_Counter_Control_OFF  ( 7)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_8_Counter_Control_WID  ( 2)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_8_Counter_Control_MSK  (0x00000180)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_8_Counter_Control_MAX  (0x00000003)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_8_Counter_Control_DEF  (0x00000000)
+
+#define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_0_REG               (0x00004114)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_0_Counter_Status_OFF ( 0)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_0_Counter_Status_WID (23)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_0_Counter_Status_MSK (0x007FFFFF)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_0_Counter_Status_MAX (0x007FFFFF)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_0_Counter_Status_DEF (0x00000000)
+
+#define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_1_REG               (0x00004118)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_1_Counter_Status_OFF ( 0)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_1_Counter_Status_WID (23)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_1_Counter_Status_MSK (0x007FFFFF)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_1_Counter_Status_MAX (0x007FFFFF)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_1_Counter_Status_DEF (0x00000000)
+
+#define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_2_REG               (0x0000411C)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_2_Counter_Status_OFF ( 0)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_2_Counter_Status_WID (23)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_2_Counter_Status_MSK (0x007FFFFF)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_2_Counter_Status_MAX (0x007FFFFF)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_2_Counter_Status_DEF (0x00000000)
+
+#define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_3_REG               (0x00004120)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_3_Counter_Status_OFF ( 0)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_3_Counter_Status_WID (23)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_3_Counter_Status_MSK (0x007FFFFF)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_3_Counter_Status_MAX (0x007FFFFF)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_3_Counter_Status_DEF (0x00000000)
+
+#define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_4_REG               (0x00004124)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_4_Counter_Status_OFF ( 0)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_4_Counter_Status_WID (23)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_4_Counter_Status_MSK (0x007FFFFF)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_4_Counter_Status_MAX (0x007FFFFF)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_4_Counter_Status_DEF (0x00000000)
+
+#define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_5_REG               (0x00004128)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_5_Counter_Status_OFF ( 0)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_5_Counter_Status_WID (23)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_5_Counter_Status_MSK (0x007FFFFF)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_5_Counter_Status_MAX (0x007FFFFF)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_5_Counter_Status_DEF (0x00000000)
+
+#define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_6_REG               (0x0000412C)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_6_Counter_Status_OFF ( 0)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_6_Counter_Status_WID (23)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_6_Counter_Status_MSK (0x007FFFFF)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_6_Counter_Status_MAX (0x007FFFFF)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_6_Counter_Status_DEF (0x00000000)
+
+#define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_7_REG               (0x00004130)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_7_Counter_Status_OFF ( 0)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_7_Counter_Status_WID (23)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_7_Counter_Status_MSK (0x007FFFFF)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_7_Counter_Status_MAX (0x007FFFFF)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_7_Counter_Status_DEF (0x00000000)
+
+#define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_8_REG               (0x00004134)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_8_Counter_Status_OFF ( 0)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_8_Counter_Status_WID (23)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_8_Counter_Status_MSK (0x007FFFFF)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_8_Counter_Status_MAX (0x007FFFFF)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_8_Counter_Status_DEF (0x00000000)
+
+#define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_OVERFLOW_STATUS_REG        (0x00004138)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_OVERFLOW_STATUS_Counter_Overflow_Status_OFF ( 0)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_OVERFLOW_STATUS_Counter_Overflow_Status_WID ( 9)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_OVERFLOW_STATUS_Counter_Overflow_Status_MSK (0x000001FF)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_OVERFLOW_STATUS_Counter_Overflow_Status_MAX (0x000001FF)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_OVERFLOW_STATUS_Counter_Overflow_Status_DEF (0x00000000)
+
+#define MCHBAR_CH0_CR_REUT_CH_ERROR_ADDR_REG                         (0x00004180)
+  #define MCHBAR_CH0_CR_REUT_CH_ERROR_ADDR_Column_Address_OFF          ( 0)
+  #define MCHBAR_CH0_CR_REUT_CH_ERROR_ADDR_Column_Address_WID          (10)
+  #define MCHBAR_CH0_CR_REUT_CH_ERROR_ADDR_Column_Address_MSK          (0x000003FF)
+  #define MCHBAR_CH0_CR_REUT_CH_ERROR_ADDR_Column_Address_MAX          (0x000003FF)
+  #define MCHBAR_CH0_CR_REUT_CH_ERROR_ADDR_Column_Address_DEF          (0x00000000)
+  #define MCHBAR_CH0_CR_REUT_CH_ERROR_ADDR_Row_Address_OFF             (24)
+  #define MCHBAR_CH0_CR_REUT_CH_ERROR_ADDR_Row_Address_WID             (16)
+  #define MCHBAR_CH0_CR_REUT_CH_ERROR_ADDR_Row_Address_MSK             (0xFFFF000000)
+  #define MCHBAR_CH0_CR_REUT_CH_ERROR_ADDR_Row_Address_MAX             (0x0000FFFF)
+  #define MCHBAR_CH0_CR_REUT_CH_ERROR_ADDR_Row_Address_DEF             (0x00000000)
+  #define MCHBAR_CH0_CR_REUT_CH_ERROR_ADDR_Bank_Address_OFF            (48)
+  #define MCHBAR_CH0_CR_REUT_CH_ERROR_ADDR_Bank_Address_WID            ( 3)
+  #define MCHBAR_CH0_CR_REUT_CH_ERROR_ADDR_Bank_Address_MSK            (0x7000000000000)
+  #define MCHBAR_CH0_CR_REUT_CH_ERROR_ADDR_Bank_Address_MAX            (0x00000007)
+  #define MCHBAR_CH0_CR_REUT_CH_ERROR_ADDR_Bank_Address_DEF            (0x00000000)
+  #define MCHBAR_CH0_CR_REUT_CH_ERROR_ADDR_Rank_Address_OFF            (56)
+  #define MCHBAR_CH0_CR_REUT_CH_ERROR_ADDR_Rank_Address_WID            ( 2)
+  #define MCHBAR_CH0_CR_REUT_CH_ERROR_ADDR_Rank_Address_MSK            (0x300000000000000)
+  #define MCHBAR_CH0_CR_REUT_CH_ERROR_ADDR_Rank_Address_MAX            (0x00000003)
+  #define MCHBAR_CH0_CR_REUT_CH_ERROR_ADDR_Rank_Address_DEF            (0x00000000)
+
+#define MCHBAR_CH0_CR_REUT_CH_ERR_WDB_CAPTURE_STATUS_REG             (0x00004188)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_WDB_CAPTURE_STATUS_WDB_Current_Error_Pointer_OFF ( 0)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_WDB_CAPTURE_STATUS_WDB_Current_Error_Pointer_WID ( 6)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_WDB_CAPTURE_STATUS_WDB_Current_Error_Pointer_MSK (0x0000003F)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_WDB_CAPTURE_STATUS_WDB_Current_Error_Pointer_MAX (0x0000003F)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_WDB_CAPTURE_STATUS_WDB_Current_Error_Pointer_DEF (0x00000000)
+
+#define MCHBAR_CH0_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_REG                (0x0000418C)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_Enable_WDB_Error_Capture_OFF ( 0)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_Enable_WDB_Error_Capture_WID ( 1)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_Enable_WDB_Error_Capture_MSK (0x00000001)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_Enable_WDB_Error_Capture_MAX (0x00000001)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_Enable_WDB_Error_Capture_DEF (0x00000000)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_WDB_Starting_Error_Pointer_OFF ( 8)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_WDB_Starting_Error_Pointer_WID ( 6)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_WDB_Starting_Error_Pointer_MSK (0x00003F00)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_WDB_Starting_Error_Pointer_MAX (0x0000003F)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_WDB_Starting_Error_Pointer_DEF (0x00000000)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_WDB_Ending_Error_Pointer_OFF (16)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_WDB_Ending_Error_Pointer_WID ( 6)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_WDB_Ending_Error_Pointer_MSK (0x003F0000)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_WDB_Ending_Error_Pointer_MAX (0x0000003F)
+  #define MCHBAR_CH0_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_WDB_Ending_Error_Pointer_DEF (0x00000000)
+
+#define MCHBAR_CH0_CR_REUT_CH_MISC_CKE_CTRL_REG                      (0x00004190)
+  #define MCHBAR_CH0_CR_REUT_CH_MISC_CKE_CTRL_CKE_Override_OFF         ( 0)
+  #define MCHBAR_CH0_CR_REUT_CH_MISC_CKE_CTRL_CKE_Override_WID         ( 4)
+  #define MCHBAR_CH0_CR_REUT_CH_MISC_CKE_CTRL_CKE_Override_MSK         (0x0000000F)
+  #define MCHBAR_CH0_CR_REUT_CH_MISC_CKE_CTRL_CKE_Override_MAX         (0x0000000F)
+  #define MCHBAR_CH0_CR_REUT_CH_MISC_CKE_CTRL_CKE_Override_DEF         (0x0000000F)
+  #define MCHBAR_CH0_CR_REUT_CH_MISC_CKE_CTRL_CKE_En_Start_Test_Sync_OFF ( 8)
+  #define MCHBAR_CH0_CR_REUT_CH_MISC_CKE_CTRL_CKE_En_Start_Test_Sync_WID ( 1)
+  #define MCHBAR_CH0_CR_REUT_CH_MISC_CKE_CTRL_CKE_En_Start_Test_Sync_MSK (0x00000100)
+  #define MCHBAR_CH0_CR_REUT_CH_MISC_CKE_CTRL_CKE_En_Start_Test_Sync_MAX (0x00000001)
+  #define MCHBAR_CH0_CR_REUT_CH_MISC_CKE_CTRL_CKE_En_Start_Test_Sync_DEF (0x00000000)
+  #define MCHBAR_CH0_CR_REUT_CH_MISC_CKE_CTRL_CKE_On_OFF               (16)
+  #define MCHBAR_CH0_CR_REUT_CH_MISC_CKE_CTRL_CKE_On_WID               ( 4)
+  #define MCHBAR_CH0_CR_REUT_CH_MISC_CKE_CTRL_CKE_On_MSK               (0x000F0000)
+  #define MCHBAR_CH0_CR_REUT_CH_MISC_CKE_CTRL_CKE_On_MAX               (0x0000000F)
+  #define MCHBAR_CH0_CR_REUT_CH_MISC_CKE_CTRL_CKE_On_DEF               (0x00000000)
+
+#define MCHBAR_CH0_CR_REUT_CH_MISC_ODT_CTRL_REG                      (0x00004194)
+  #define MCHBAR_CH0_CR_REUT_CH_MISC_ODT_CTRL_ODT_Override_OFF         ( 0)
+  #define MCHBAR_CH0_CR_REUT_CH_MISC_ODT_CTRL_ODT_Override_WID         ( 4)
+  #define MCHBAR_CH0_CR_REUT_CH_MISC_ODT_CTRL_ODT_Override_MSK         (0x0000000F)
+  #define MCHBAR_CH0_CR_REUT_CH_MISC_ODT_CTRL_ODT_Override_MAX         (0x0000000F)
+  #define MCHBAR_CH0_CR_REUT_CH_MISC_ODT_CTRL_ODT_Override_DEF         (0x0000000F)
+  #define MCHBAR_CH0_CR_REUT_CH_MISC_ODT_CTRL_ODT_On_OFF               (16)
+  #define MCHBAR_CH0_CR_REUT_CH_MISC_ODT_CTRL_ODT_On_WID               ( 4)
+  #define MCHBAR_CH0_CR_REUT_CH_MISC_ODT_CTRL_ODT_On_MSK               (0x000F0000)
+  #define MCHBAR_CH0_CR_REUT_CH_MISC_ODT_CTRL_ODT_On_MAX               (0x0000000F)
+  #define MCHBAR_CH0_CR_REUT_CH_MISC_ODT_CTRL_ODT_On_DEF               (0x00000000)
+  #define MCHBAR_CH0_CR_REUT_CH_MISC_ODT_CTRL_MPR_Train_DDR_On_OFF     (31)
+  #define MCHBAR_CH0_CR_REUT_CH_MISC_ODT_CTRL_MPR_Train_DDR_On_WID     ( 1)
+  #define MCHBAR_CH0_CR_REUT_CH_MISC_ODT_CTRL_MPR_Train_DDR_On_MSK     (0x80000000)
+  #define MCHBAR_CH0_CR_REUT_CH_MISC_ODT_CTRL_MPR_Train_DDR_On_MAX     (0x00000001)
+  #define MCHBAR_CH0_CR_REUT_CH_MISC_ODT_CTRL_MPR_Train_DDR_On_DEF     (0x00000000)
+
+#define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_REG                      (0x00004198)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_Enable_CADB_on_Deselect_OFF ( 0)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_Enable_CADB_on_Deselect_WID ( 1)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_Enable_CADB_on_Deselect_MSK (0x00000001)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_Enable_CADB_on_Deselect_MAX (0x00000001)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_Enable_CADB_on_Deselect_DEF (0x00000000)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_Enable_CADB_Always_On_OFF ( 1)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_Enable_CADB_Always_On_WID ( 1)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_Enable_CADB_Always_On_MSK (0x00000002)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_Enable_CADB_Always_On_MAX (0x00000001)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_Enable_CADB_Always_On_DEF (0x00000000)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_CMD_Deselect_Start_OFF  ( 2)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_CMD_Deselect_Start_WID  ( 4)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_CMD_Deselect_Start_MSK  (0x0000003C)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_CMD_Deselect_Start_MAX  (0x0000000F)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_CMD_Deselect_Start_DEF  (0x00000000)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_CMD_Deselect_Stop_OFF  ( 6)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_CMD_Deselect_Stop_WID  ( 4)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_CMD_Deselect_Stop_MSK  (0x000003C0)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_CMD_Deselect_Stop_MAX  (0x0000000F)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_CMD_Deselect_Stop_DEF  (0x00000000)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_Lane_Deselect_Enable_OFF  ( 10)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_Lane_Deselect_Enable_WID  ( 4)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_Lane_Deselect_Enable_MSK  (0x00003C00)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_Lane_Deselect_Enable_MAX  (0x0000000F)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_Lane_Deselect_Enable_DEF  (0x00000000)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_CAS_Select_Enable_OFF  ( 14)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_CAS_Select_Enable_WID  ( 2)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_CAS_Select_Enable_MSK  (0x0000C000)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_CAS_Select_Enable_MAX  (0x00000003)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_CAS_Select_Enable_DEF  (0x00000000)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_ACT_Select_Enable_OFF  ( 16)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_ACT_Select_Enable_WID  ( 2)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_ACT_Select_Enable_MSK  (0x00030000)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_ACT_Select_Enable_MAX  (0x00000003)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_ACT_Select_Enable_DEF  (0x00000000)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_PRE_Select_Enable_OFF  ( 18)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_PRE_Select_Enable_WID  ( 2)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_PRE_Select_Enable_MSK  (0x000C0000)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_PRE_Select_Enable_MAX  (0x00000003)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_PRE_Select_Enable_DEF  (0x00000000)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_Save_Current_Seed_OFF  ( 20)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_Save_Current_Seed_WID  ( 4)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_Save_Current_Seed_MSK  (0x00F00000)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_Save_Current_Seed_MAX  (0x0000000F)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_Save_Current_Seed_DEF  (0x00000000)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_Reload_Starting_Seed_OFF  ( 24)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_Reload_Starting_Seed_WID  ( 4)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_Reload_Starting_Seed_MSK  (0x0F000000)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_Reload_Starting_Seed_MAX  (0x0000000F)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_Reload_Starting_Seed_DEF  (0x00000000)
+
+#define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MRS_REG                       (0x0000419C)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MRS_MRS_Gap_OFF               ( 0)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MRS_MRS_Gap_WID               ( 3)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MRS_MRS_Gap_MSK               (0x00000007)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MRS_MRS_Gap_MAX               (0x00000007)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MRS_MRS_Gap_DEF               (0x00000002)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MRS_CADB_MRS_Start_Pointer_OFF ( 8)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MRS_CADB_MRS_Start_Pointer_WID ( 3)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MRS_CADB_MRS_Start_Pointer_MSK (0x00000700)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MRS_CADB_MRS_Start_Pointer_MAX (0x00000007)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MRS_CADB_MRS_Start_Pointer_DEF (0x00000000)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MRS_CADB_MRS_End_Pointer_OFF  (16)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MRS_CADB_MRS_End_Pointer_WID  ( 3)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MRS_CADB_MRS_End_Pointer_MSK  (0x00070000)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MRS_CADB_MRS_End_Pointer_MAX  (0x00000007)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MRS_CADB_MRS_End_Pointer_DEF  (0x00000007)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MRS_CADB_MRS_Current_Pointer_OFF (24)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MRS_CADB_MRS_Current_Pointer_WID ( 3)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MRS_CADB_MRS_Current_Pointer_MSK (0x07000000)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MRS_CADB_MRS_Current_Pointer_MAX (0x00000007)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MRS_CADB_MRS_Current_Pointer_DEF (0x00000000)
+
+#define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_CTRL_REG                  (0x000041A0)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_CTRL_Mux0_Control_OFF     ( 0)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_CTRL_Mux0_Control_WID     ( 2)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_CTRL_Mux0_Control_MSK     (0x00000003)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_CTRL_Mux0_Control_MAX     (0x00000003)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_CTRL_Mux0_Control_DEF     (0x00000001)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_CTRL_Mux1_Control_OFF     ( 4)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_CTRL_Mux1_Control_WID     ( 2)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_CTRL_Mux1_Control_MSK     (0x00000030)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_CTRL_Mux1_Control_MAX     (0x00000003)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_CTRL_Mux1_Control_DEF     (0x00000001)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_CTRL_Mux2_Control_OFF     ( 8)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_CTRL_Mux2_Control_WID     ( 2)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_CTRL_Mux2_Control_MSK     (0x00000300)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_CTRL_Mux2_Control_MAX     (0x00000003)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_CTRL_Mux2_Control_DEF     (0x00000001)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_CTRL_Select_Mux0_Control_OFF       ( 16)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_CTRL_Select_Mux0_Control_WID       ( 2)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_CTRL_Select_Mux0_Control_MSK       (0x00030000)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_CTRL_Select_Mux0_Control_MAX       (0x00000003)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_CTRL_Select_Mux0_Control_DEF       (0x00000001)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_CTRL_Select_Mux1_Control_OFF       ( 20)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_CTRL_Select_Mux1_Control_WID       ( 2)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_CTRL_Select_Mux1_Control_MSK       (0x00300000)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_CTRL_Select_Mux1_Control_MAX       (0x00000003)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_CTRL_Select_Mux1_Control_DEF       (0x00000001)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_CTRL_Select_Mux2_Control_OFF       ( 24)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_CTRL_Select_Mux2_Control_WID       ( 2)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_CTRL_Select_Mux2_Control_MSK       (0x03000000)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_CTRL_Select_Mux2_Control_MAX       (0x00000003)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_CTRL_Select_Mux2_Control_DEF       (0x00000001)
+
+#define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_PB_0_REG                  (0x000041A4)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_PB_0_Pattern_Buffer_OFF   ( 0)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_PB_0_Pattern_Buffer_WID   (16)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_PB_0_Pattern_Buffer_MSK   (0x0000FFFF)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_PB_0_Pattern_Buffer_MAX   (0x0000FFFF)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_PB_0_Pattern_Buffer_DEF   (0x00000000)
+
+#define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_PB_1_REG                  (0x000041A8)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_PB_1_Pattern_Buffer_OFF   ( 0)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_PB_1_Pattern_Buffer_WID   (16)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_PB_1_Pattern_Buffer_MSK   (0x0000FFFF)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_PB_1_Pattern_Buffer_MAX   (0x0000FFFF)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_PB_1_Pattern_Buffer_DEF   (0x00000000)
+
+#define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_PB_2_REG                  (0x000041AC)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_PB_2_Pattern_Buffer_OFF   ( 0)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_PB_2_Pattern_Buffer_WID   (16)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_PB_2_Pattern_Buffer_MSK   (0x0000FFFF)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_PB_2_Pattern_Buffer_MAX   (0x0000FFFF)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_PB_2_Pattern_Buffer_DEF   (0x00000000)
+
+#define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_REG                (0x000041B0)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_L_data_select_OFF  ( 0)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_L_data_select_WID  ( 1)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_L_data_select_MSK  (0x00000001)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_L_data_select_MAX  (0x00000001)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_L_data_select_DEF  (0x00000000)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_Enable_Sweep_Frequency_OFF ( 1)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_Enable_Sweep_Frequency_WID ( 1)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_Enable_Sweep_Frequency_MSK (0x00000002)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_Enable_Sweep_Frequency_MAX (0x00000001)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_Enable_Sweep_Frequency_DEF (0x00000000)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_L_counter_OFF      ( 8)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_L_counter_WID      ( 8)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_L_counter_MSK      (0x0000FF00)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_L_counter_MAX      (0x000000FF)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_L_counter_DEF      (0x00000001)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_M_counter_OFF      (16)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_M_counter_WID      ( 8)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_M_counter_MSK      (0x00FF0000)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_M_counter_MAX      (0x000000FF)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_M_counter_DEF      (0x00000001)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_N_counter_OFF      (24)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_N_counter_WID      ( 8)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_N_counter_MSK      (0xFF000000)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_N_counter_MAX      (0x000000FF)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_N_counter_DEF      (0x00000001)
+
+#define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_WRITE_POINTER_REG             (0x000041BC)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_WRITE_POINTER_CADB_Write_Pointer_OFF ( 0)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_WRITE_POINTER_CADB_Write_Pointer_WID ( 3)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_WRITE_POINTER_CADB_Write_Pointer_MSK (0x00000007)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_WRITE_POINTER_CADB_Write_Pointer_MAX (0x00000007)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_WRITE_POINTER_CADB_Write_Pointer_DEF (0x00000000)
+
+#define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_0_REG              (0x000041C8)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_0_Pattern_Buffer_OFF ( 0)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_0_Pattern_Buffer_WID (16)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_0_Pattern_Buffer_MSK (0x0000FFFF)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_0_Pattern_Buffer_MAX (0x0000FFFF)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_0_Pattern_Buffer_DEF (0x00000000)
+
+#define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_1_REG              (0x000041CC)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_1_Pattern_Buffer_OFF ( 0)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_1_Pattern_Buffer_WID (16)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_1_Pattern_Buffer_MSK (0x0000FFFF)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_1_Pattern_Buffer_MAX (0x0000FFFF)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_1_Pattern_Buffer_DEF (0x00000000)
+
+#define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_2_REG              (0x000041D0)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_2_Pattern_Buffer_OFF ( 0)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_2_Pattern_Buffer_WID (16)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_2_Pattern_Buffer_MSK (0x0000FFFF)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_2_Pattern_Buffer_MAX (0x0000FFFF)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_2_Pattern_Buffer_DEF (0x00000000)
+
+#define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_PROG_REG                      (0x000041C0)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_Address_OFF    ( 0)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_Address_WID    (16)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_Address_MSK    (0x0000FFFF)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_Address_MAX    (0x0000FFFF)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_Address_DEF    (0x00000000)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_Bank_OFF       (24)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_Bank_WID       ( 3)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_Bank_MSK       (0x07000000)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_Bank_MAX       (0x00000007)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_Bank_DEF       (0x00000000)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_CS_OFF         (32)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_CS_WID         ( 4)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_CS_MSK         (0xF00000000)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_CS_MAX         (0x0000000F)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_CS_DEF         (0x00000000)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_Control_OFF    (40)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_Control_WID    ( 3)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_Control_MSK    (0x70000000000)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_Control_MAX    (0x00000007)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_Control_DEF    (0x00000000)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_ODT_OFF        (48)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_ODT_WID        ( 4)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_ODT_MSK        (0xF000000000000)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_ODT_MAX        (0x0000000F)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_ODT_DEF        (0x00000000)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_CKE_OFF        (56)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_CKE_WID        ( 4)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_CKE_MSK        (0xF00000000000000)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_CKE_MAX        (0x0000000F)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_CKE_DEF        (0x00000000)
+
+#define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_CTRL_REG                    (0x00004200)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_Increment_Rate_OFF ( 0)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_Increment_Rate_WID ( 5)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_Increment_Rate_MSK (0x0000001F)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_Increment_Rate_MAX (0x0000001F)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_Increment_Rate_DEF (0x00000000)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_Increment_Scale_OFF ( 5)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_Increment_Scale_WID ( 1)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_Increment_Scale_MSK (0x00000020)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_Increment_Scale_MAX (0x00000001)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_Increment_Scale_DEF (0x00000000)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_Start_Pointer_OFF  ( 8)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_Start_Pointer_WID  ( 6)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_Start_Pointer_MSK  (0x00003F00)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_Start_Pointer_MAX  (0x0000003F)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_Start_Pointer_DEF  (0x00000000)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_End_Pointer_OFF    (16)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_End_Pointer_WID    ( 6)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_End_Pointer_MSK    (0x003F0000)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_End_Pointer_MAX    (0x0000003F)
+  #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_End_Pointer_DEF    (0x0000003F)
+
+#define MCHBAR_CH0_CR_REUT_CH_MISC_REFRESH_CTRL_REG                  (0x00004204)
+  #define MCHBAR_CH0_CR_REUT_CH_MISC_REFRESH_CTRL_Refresh_Rank_Mask_OFF ( 0)
+  #define MCHBAR_CH0_CR_REUT_CH_MISC_REFRESH_CTRL_Refresh_Rank_Mask_WID ( 4)
+  #define MCHBAR_CH0_CR_REUT_CH_MISC_REFRESH_CTRL_Refresh_Rank_Mask_MSK (0x0000000F)
+  #define MCHBAR_CH0_CR_REUT_CH_MISC_REFRESH_CTRL_Refresh_Rank_Mask_MAX (0x0000000F)
+  #define MCHBAR_CH0_CR_REUT_CH_MISC_REFRESH_CTRL_Refresh_Rank_Mask_DEF (0x00000000)
+  #define MCHBAR_CH0_CR_REUT_CH_MISC_REFRESH_CTRL_RefZQ_En_Start_Test_Sync_OFF ( 8)
+  #define MCHBAR_CH0_CR_REUT_CH_MISC_REFRESH_CTRL_RefZQ_En_Start_Test_Sync_WID ( 1)
+  #define MCHBAR_CH0_CR_REUT_CH_MISC_REFRESH_CTRL_RefZQ_En_Start_Test_Sync_MSK (0x00000100)
+  #define MCHBAR_CH0_CR_REUT_CH_MISC_REFRESH_CTRL_RefZQ_En_Start_Test_Sync_MAX (0x00000001)
+  #define MCHBAR_CH0_CR_REUT_CH_MISC_REFRESH_CTRL_RefZQ_En_Start_Test_Sync_DEF (0x00000000)
+  #define MCHBAR_CH0_CR_REUT_CH_MISC_REFRESH_CTRL_Panic_Refresh_Only_OFF (31)
+  #define MCHBAR_CH0_CR_REUT_CH_MISC_REFRESH_CTRL_Panic_Refresh_Only_WID ( 1)
+  #define MCHBAR_CH0_CR_REUT_CH_MISC_REFRESH_CTRL_Panic_Refresh_Only_MSK (0x80000000)
+  #define MCHBAR_CH0_CR_REUT_CH_MISC_REFRESH_CTRL_Panic_Refresh_Only_MAX (0x00000001)
+  #define MCHBAR_CH0_CR_REUT_CH_MISC_REFRESH_CTRL_Panic_Refresh_Only_DEF (0x00000000)
+
+#define MCHBAR_CH0_CR_REUT_CH_MISC_ZQ_CTRL_REG                       (0x00004208)
+  #define MCHBAR_CH0_CR_REUT_CH_MISC_ZQ_CTRL_ZQ_Rank_Mask_OFF          ( 0)
+  #define MCHBAR_CH0_CR_REUT_CH_MISC_ZQ_CTRL_ZQ_Rank_Mask_WID          ( 4)
+  #define MCHBAR_CH0_CR_REUT_CH_MISC_ZQ_CTRL_ZQ_Rank_Mask_MSK          (0x0000000F)
+  #define MCHBAR_CH0_CR_REUT_CH_MISC_ZQ_CTRL_ZQ_Rank_Mask_MAX          (0x0000000F)
+  #define MCHBAR_CH0_CR_REUT_CH_MISC_ZQ_CTRL_ZQ_Rank_Mask_DEF          (0x00000000)
+  #define MCHBAR_CH0_CR_REUT_CH_MISC_ZQ_CTRL_Always_Do_ZQ_OFF          (31)
+  #define MCHBAR_CH0_CR_REUT_CH_MISC_ZQ_CTRL_Always_Do_ZQ_WID          ( 1)
+  #define MCHBAR_CH0_CR_REUT_CH_MISC_ZQ_CTRL_Always_Do_ZQ_MSK          (0x80000000)
+  #define MCHBAR_CH0_CR_REUT_CH_MISC_ZQ_CTRL_Always_Do_ZQ_MAX          (0x00000001)
+  #define MCHBAR_CH0_CR_REUT_CH_MISC_ZQ_CTRL_Always_Do_ZQ_DEF          (0x00000000)
+
+#define MCHBAR_CH0_CR_LPDDR_MR_PARAMS_REG                            (0x00004210)
+  #define MCHBAR_CH0_CR_LPDDR_MR_PARAMS_Rank_0_x32_OFF                 ( 0)
+  #define MCHBAR_CH0_CR_LPDDR_MR_PARAMS_Rank_0_x32_WID                 ( 1)
+  #define MCHBAR_CH0_CR_LPDDR_MR_PARAMS_Rank_0_x32_MSK                 (0x00000001)
+  #define MCHBAR_CH0_CR_LPDDR_MR_PARAMS_Rank_0_x32_MAX                 (0x00000001)
+  #define MCHBAR_CH0_CR_LPDDR_MR_PARAMS_Rank_0_x32_DEF                 (0x00000000)
+  #define MCHBAR_CH0_CR_LPDDR_MR_PARAMS_Rank_1_x32_OFF                 ( 1)
+  #define MCHBAR_CH0_CR_LPDDR_MR_PARAMS_Rank_1_x32_WID                 ( 1)
+  #define MCHBAR_CH0_CR_LPDDR_MR_PARAMS_Rank_1_x32_MSK                 (0x00000002)
+  #define MCHBAR_CH0_CR_LPDDR_MR_PARAMS_Rank_1_x32_MAX                 (0x00000001)
+  #define MCHBAR_CH0_CR_LPDDR_MR_PARAMS_Rank_1_x32_DEF                 (0x00000000)
+  #define MCHBAR_CH0_CR_LPDDR_MR_PARAMS_Rank_2_x32_OFF                 ( 2)
+  #define MCHBAR_CH0_CR_LPDDR_MR_PARAMS_Rank_2_x32_WID                 ( 1)
+  #define MCHBAR_CH0_CR_LPDDR_MR_PARAMS_Rank_2_x32_MSK                 (0x00000004)
+  #define MCHBAR_CH0_CR_LPDDR_MR_PARAMS_Rank_2_x32_MAX                 (0x00000001)
+  #define MCHBAR_CH0_CR_LPDDR_MR_PARAMS_Rank_2_x32_DEF                 (0x00000000)
+  #define MCHBAR_CH0_CR_LPDDR_MR_PARAMS_Rank_3_x32_OFF                 ( 3)
+  #define MCHBAR_CH0_CR_LPDDR_MR_PARAMS_Rank_3_x32_WID                 ( 1)
+  #define MCHBAR_CH0_CR_LPDDR_MR_PARAMS_Rank_3_x32_MSK                 (0x00000008)
+  #define MCHBAR_CH0_CR_LPDDR_MR_PARAMS_Rank_3_x32_MAX                 (0x00000001)
+  #define MCHBAR_CH0_CR_LPDDR_MR_PARAMS_Rank_3_x32_DEF                 (0x00000000)
+  #define MCHBAR_CH0_CR_LPDDR_MR_PARAMS_LPDDR2_OFF                     ( 4)
+  #define MCHBAR_CH0_CR_LPDDR_MR_PARAMS_LPDDR2_WID                     ( 1)
+  #define MCHBAR_CH0_CR_LPDDR_MR_PARAMS_LPDDR2_MSK                     (0x00000010)
+  #define MCHBAR_CH0_CR_LPDDR_MR_PARAMS_LPDDR2_MAX                     (0x00000001)
+  #define MCHBAR_CH0_CR_LPDDR_MR_PARAMS_LPDDR2_DEF                     (0x00000000)
+  #define MCHBAR_CH0_CR_LPDDR_MR_PARAMS_MR4_PERIOD_OFF                 ( 8)
+  #define MCHBAR_CH0_CR_LPDDR_MR_PARAMS_MR4_PERIOD_WID                 (16)
+  #define MCHBAR_CH0_CR_LPDDR_MR_PARAMS_MR4_PERIOD_MSK                 (0x00FFFF00)
+  #define MCHBAR_CH0_CR_LPDDR_MR_PARAMS_MR4_PERIOD_MAX                 (0x0000FFFF)
+  #define MCHBAR_CH0_CR_LPDDR_MR_PARAMS_MR4_PERIOD_DEF                 (0x00000000)
+
+#define MCHBAR_CH0_CR_LPDDR_MR_COMMAND_REG                           (0x00004214)
+  #define MCHBAR_CH0_CR_LPDDR_MR_COMMAND_Address_OFF                   ( 0)
+  #define MCHBAR_CH0_CR_LPDDR_MR_COMMAND_Address_WID                   ( 8)
+  #define MCHBAR_CH0_CR_LPDDR_MR_COMMAND_Address_MSK                   (0x000000FF)
+  #define MCHBAR_CH0_CR_LPDDR_MR_COMMAND_Address_MAX                   (0x000000FF)
+  #define MCHBAR_CH0_CR_LPDDR_MR_COMMAND_Address_DEF                   (0x00000000)
+  #define MCHBAR_CH0_CR_LPDDR_MR_COMMAND_Data_OFF                      ( 8)
+  #define MCHBAR_CH0_CR_LPDDR_MR_COMMAND_Data_WID                      ( 8)
+  #define MCHBAR_CH0_CR_LPDDR_MR_COMMAND_Data_MSK                      (0x0000FF00)
+  #define MCHBAR_CH0_CR_LPDDR_MR_COMMAND_Data_MAX                      (0x000000FF)
+  #define MCHBAR_CH0_CR_LPDDR_MR_COMMAND_Data_DEF                      (0x00000000)
+  #define MCHBAR_CH0_CR_LPDDR_MR_COMMAND_Rank_OFF                      (16)
+  #define MCHBAR_CH0_CR_LPDDR_MR_COMMAND_Rank_WID                      ( 2)
+  #define MCHBAR_CH0_CR_LPDDR_MR_COMMAND_Rank_MSK                      (0x00030000)
+  #define MCHBAR_CH0_CR_LPDDR_MR_COMMAND_Rank_MAX                      (0x00000003)
+  #define MCHBAR_CH0_CR_LPDDR_MR_COMMAND_Rank_DEF                      (0x00000000)
+  #define MCHBAR_CH0_CR_LPDDR_MR_COMMAND_Write_OFF                     (18)
+  #define MCHBAR_CH0_CR_LPDDR_MR_COMMAND_Write_WID                     ( 1)
+  #define MCHBAR_CH0_CR_LPDDR_MR_COMMAND_Write_MSK                     (0x00040000)
+  #define MCHBAR_CH0_CR_LPDDR_MR_COMMAND_Write_MAX                     (0x00000001)
+  #define MCHBAR_CH0_CR_LPDDR_MR_COMMAND_Write_DEF                     (0x00000000)
+  #define MCHBAR_CH0_CR_LPDDR_MR_COMMAND_Init_MRW_OFF                  (19)
+  #define MCHBAR_CH0_CR_LPDDR_MR_COMMAND_Init_MRW_WID                  ( 1)
+  #define MCHBAR_CH0_CR_LPDDR_MR_COMMAND_Init_MRW_MSK                  (0x00080000)
+  #define MCHBAR_CH0_CR_LPDDR_MR_COMMAND_Init_MRW_MAX                  (0x00000001)
+  #define MCHBAR_CH0_CR_LPDDR_MR_COMMAND_Init_MRW_DEF                  (0x00000000)
+  #define MCHBAR_CH0_CR_LPDDR_MR_COMMAND_Busy_OFF                      (31)
+  #define MCHBAR_CH0_CR_LPDDR_MR_COMMAND_Busy_WID                      ( 1)
+  #define MCHBAR_CH0_CR_LPDDR_MR_COMMAND_Busy_MSK                      (0x80000000)
+  #define MCHBAR_CH0_CR_LPDDR_MR_COMMAND_Busy_MAX                      (0x00000001)
+  #define MCHBAR_CH0_CR_LPDDR_MR_COMMAND_Busy_DEF                      (0x00000000)
+
+#define MCHBAR_CH0_CR_LPDDR_MR_RESULT_REG                            (0x00004218)
+  #define MCHBAR_CH0_CR_LPDDR_MR_RESULT_Device_0_OFF                   ( 0)
+  #define MCHBAR_CH0_CR_LPDDR_MR_RESULT_Device_0_WID                   ( 8)
+  #define MCHBAR_CH0_CR_LPDDR_MR_RESULT_Device_0_MSK                   (0x000000FF)
+  #define MCHBAR_CH0_CR_LPDDR_MR_RESULT_Device_0_MAX                   (0x000000FF)
+  #define MCHBAR_CH0_CR_LPDDR_MR_RESULT_Device_0_DEF                   (0x00000000)
+  #define MCHBAR_CH0_CR_LPDDR_MR_RESULT_Device_1_OFF                   ( 8)
+  #define MCHBAR_CH0_CR_LPDDR_MR_RESULT_Device_1_WID                   ( 8)
+  #define MCHBAR_CH0_CR_LPDDR_MR_RESULT_Device_1_MSK                   (0x0000FF00)
+  #define MCHBAR_CH0_CR_LPDDR_MR_RESULT_Device_1_MAX                   (0x000000FF)
+  #define MCHBAR_CH0_CR_LPDDR_MR_RESULT_Device_1_DEF                   (0x00000000)
+  #define MCHBAR_CH0_CR_LPDDR_MR_RESULT_Device_2_OFF                   (16)
+  #define MCHBAR_CH0_CR_LPDDR_MR_RESULT_Device_2_WID                   ( 8)
+  #define MCHBAR_CH0_CR_LPDDR_MR_RESULT_Device_2_MSK                   (0x00FF0000)
+  #define MCHBAR_CH0_CR_LPDDR_MR_RESULT_Device_2_MAX                   (0x000000FF)
+  #define MCHBAR_CH0_CR_LPDDR_MR_RESULT_Device_2_DEF                   (0x00000000)
+  #define MCHBAR_CH0_CR_LPDDR_MR_RESULT_Device_3_OFF                   (24)
+  #define MCHBAR_CH0_CR_LPDDR_MR_RESULT_Device_3_WID                   ( 8)
+  #define MCHBAR_CH0_CR_LPDDR_MR_RESULT_Device_3_MSK                   (0xFF000000)
+  #define MCHBAR_CH0_CR_LPDDR_MR_RESULT_Device_3_MAX                   (0x000000FF)
+  #define MCHBAR_CH0_CR_LPDDR_MR_RESULT_Device_3_DEF                   (0x00000000)
+
+#define MCHBAR_CH0_CR_LPDDR_MR4_RANK_TEMPERATURE_REG                 (0x0000421C)
+  #define MCHBAR_CH0_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_0_OFF          ( 0)
+  #define MCHBAR_CH0_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_0_WID          ( 3)
+  #define MCHBAR_CH0_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_0_MSK          (0x00000007)
+  #define MCHBAR_CH0_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_0_MAX          (0x00000007)
+  #define MCHBAR_CH0_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_0_DEF          (0x00000003)
+  #define MCHBAR_CH0_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_1_OFF          ( 8)
+  #define MCHBAR_CH0_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_1_WID          ( 3)
+  #define MCHBAR_CH0_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_1_MSK          (0x00000700)
+  #define MCHBAR_CH0_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_1_MAX          (0x00000007)
+  #define MCHBAR_CH0_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_1_DEF          (0x00000003)
+  #define MCHBAR_CH0_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_2_OFF          (16)
+  #define MCHBAR_CH0_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_2_WID          ( 3)
+  #define MCHBAR_CH0_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_2_MSK          (0x00070000)
+  #define MCHBAR_CH0_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_2_MAX          (0x00000007)
+  #define MCHBAR_CH0_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_2_DEF          (0x00000003)
+  #define MCHBAR_CH0_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_3_OFF          (24)
+  #define MCHBAR_CH0_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_3_WID          ( 3)
+  #define MCHBAR_CH0_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_3_MSK          (0x07000000)
+  #define MCHBAR_CH0_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_3_MAX          (0x00000007)
+  #define MCHBAR_CH0_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_3_DEF          (0x00000003)
+
+#define MCHBAR_CH0_CR_DESWIZZLE_LOW_REG                              (0x00004220)
+  #define MCHBAR_CH0_CR_DESWIZZLE_LOW_Bit_0_OFF                        ( 0)
+  #define MCHBAR_CH0_CR_DESWIZZLE_LOW_Bit_0_WID                        ( 3)
+  #define MCHBAR_CH0_CR_DESWIZZLE_LOW_Bit_0_MSK                        (0x00000007)
+  #define MCHBAR_CH0_CR_DESWIZZLE_LOW_Bit_0_MAX                        (0x00000007)
+  #define MCHBAR_CH0_CR_DESWIZZLE_LOW_Bit_0_DEF                        (0x00000000)
+  #define MCHBAR_CH0_CR_DESWIZZLE_LOW_Bit_1_OFF                        ( 4)
+  #define MCHBAR_CH0_CR_DESWIZZLE_LOW_Bit_1_WID                        ( 3)
+  #define MCHBAR_CH0_CR_DESWIZZLE_LOW_Bit_1_MSK                        (0x00000070)
+  #define MCHBAR_CH0_CR_DESWIZZLE_LOW_Bit_1_MAX                        (0x00000007)
+  #define MCHBAR_CH0_CR_DESWIZZLE_LOW_Bit_1_DEF                        (0x00000001)
+  #define MCHBAR_CH0_CR_DESWIZZLE_LOW_Bit_2_OFF                        ( 8)
+  #define MCHBAR_CH0_CR_DESWIZZLE_LOW_Bit_2_WID                        ( 3)
+  #define MCHBAR_CH0_CR_DESWIZZLE_LOW_Bit_2_MSK                        (0x00000700)
+  #define MCHBAR_CH0_CR_DESWIZZLE_LOW_Bit_2_MAX                        (0x00000007)
+  #define MCHBAR_CH0_CR_DESWIZZLE_LOW_Bit_2_DEF                        (0x00000002)
+  #define MCHBAR_CH0_CR_DESWIZZLE_LOW_Bit_16_OFF                       (12)
+  #define MCHBAR_CH0_CR_DESWIZZLE_LOW_Bit_16_WID                       ( 3)
+  #define MCHBAR_CH0_CR_DESWIZZLE_LOW_Bit_16_MSK                       (0x00007000)
+  #define MCHBAR_CH0_CR_DESWIZZLE_LOW_Bit_16_MAX                       (0x00000007)
+  #define MCHBAR_CH0_CR_DESWIZZLE_LOW_Bit_16_DEF                       (0x00000000)
+  #define MCHBAR_CH0_CR_DESWIZZLE_LOW_Bit_17_OFF                       (16)
+  #define MCHBAR_CH0_CR_DESWIZZLE_LOW_Bit_17_WID                       ( 3)
+  #define MCHBAR_CH0_CR_DESWIZZLE_LOW_Bit_17_MSK                       (0x00070000)
+  #define MCHBAR_CH0_CR_DESWIZZLE_LOW_Bit_17_MAX                       (0x00000007)
+  #define MCHBAR_CH0_CR_DESWIZZLE_LOW_Bit_17_DEF                       (0x00000001)
+  #define MCHBAR_CH0_CR_DESWIZZLE_LOW_Bit_18_OFF                       (20)
+  #define MCHBAR_CH0_CR_DESWIZZLE_LOW_Bit_18_WID                       ( 3)
+  #define MCHBAR_CH0_CR_DESWIZZLE_LOW_Bit_18_MSK                       (0x00700000)
+  #define MCHBAR_CH0_CR_DESWIZZLE_LOW_Bit_18_MAX                       (0x00000007)
+  #define MCHBAR_CH0_CR_DESWIZZLE_LOW_Bit_18_DEF                       (0x00000002)
+  #define MCHBAR_CH0_CR_DESWIZZLE_LOW_Byte_0_OFF                       (24)
+  #define MCHBAR_CH0_CR_DESWIZZLE_LOW_Byte_0_WID                       ( 3)
+  #define MCHBAR_CH0_CR_DESWIZZLE_LOW_Byte_0_MSK                       (0x07000000)
+  #define MCHBAR_CH0_CR_DESWIZZLE_LOW_Byte_0_MAX                       (0x00000007)
+  #define MCHBAR_CH0_CR_DESWIZZLE_LOW_Byte_0_DEF                       (0x00000000)
+  #define MCHBAR_CH0_CR_DESWIZZLE_LOW_Byte_2_OFF                       (28)
+  #define MCHBAR_CH0_CR_DESWIZZLE_LOW_Byte_2_WID                       ( 3)
+  #define MCHBAR_CH0_CR_DESWIZZLE_LOW_Byte_2_MSK                       (0x70000000)
+  #define MCHBAR_CH0_CR_DESWIZZLE_LOW_Byte_2_MAX                       (0x00000007)
+  #define MCHBAR_CH0_CR_DESWIZZLE_LOW_Byte_2_DEF                       (0x00000002)
+
+#define MCHBAR_CH0_CR_DESWIZZLE_HIGH_REG                             (0x00004224)
+  #define MCHBAR_CH0_CR_DESWIZZLE_HIGH_Bit_32_OFF                      ( 0)
+  #define MCHBAR_CH0_CR_DESWIZZLE_HIGH_Bit_32_WID                      ( 3)
+  #define MCHBAR_CH0_CR_DESWIZZLE_HIGH_Bit_32_MSK                      (0x00000007)
+  #define MCHBAR_CH0_CR_DESWIZZLE_HIGH_Bit_32_MAX                      (0x00000007)
+  #define MCHBAR_CH0_CR_DESWIZZLE_HIGH_Bit_32_DEF                      (0x00000000)
+  #define MCHBAR_CH0_CR_DESWIZZLE_HIGH_Bit_33_OFF                      ( 4)
+  #define MCHBAR_CH0_CR_DESWIZZLE_HIGH_Bit_33_WID                      ( 3)
+  #define MCHBAR_CH0_CR_DESWIZZLE_HIGH_Bit_33_MSK                      (0x00000070)
+  #define MCHBAR_CH0_CR_DESWIZZLE_HIGH_Bit_33_MAX                      (0x00000007)
+  #define MCHBAR_CH0_CR_DESWIZZLE_HIGH_Bit_33_DEF                      (0x00000001)
+  #define MCHBAR_CH0_CR_DESWIZZLE_HIGH_Bit_34_OFF                      ( 8)
+  #define MCHBAR_CH0_CR_DESWIZZLE_HIGH_Bit_34_WID                      ( 3)
+  #define MCHBAR_CH0_CR_DESWIZZLE_HIGH_Bit_34_MSK                      (0x00000700)
+  #define MCHBAR_CH0_CR_DESWIZZLE_HIGH_Bit_34_MAX                      (0x00000007)
+  #define MCHBAR_CH0_CR_DESWIZZLE_HIGH_Bit_34_DEF                      (0x00000002)
+  #define MCHBAR_CH0_CR_DESWIZZLE_HIGH_Bit_48_OFF                      (12)
+  #define MCHBAR_CH0_CR_DESWIZZLE_HIGH_Bit_48_WID                      ( 3)
+  #define MCHBAR_CH0_CR_DESWIZZLE_HIGH_Bit_48_MSK                      (0x00007000)
+  #define MCHBAR_CH0_CR_DESWIZZLE_HIGH_Bit_48_MAX                      (0x00000007)
+  #define MCHBAR_CH0_CR_DESWIZZLE_HIGH_Bit_48_DEF                      (0x00000000)
+  #define MCHBAR_CH0_CR_DESWIZZLE_HIGH_Bit_49_OFF                      (16)
+  #define MCHBAR_CH0_CR_DESWIZZLE_HIGH_Bit_49_WID                      ( 3)
+  #define MCHBAR_CH0_CR_DESWIZZLE_HIGH_Bit_49_MSK                      (0x00070000)
+  #define MCHBAR_CH0_CR_DESWIZZLE_HIGH_Bit_49_MAX                      (0x00000007)
+  #define MCHBAR_CH0_CR_DESWIZZLE_HIGH_Bit_49_DEF                      (0x00000001)
+  #define MCHBAR_CH0_CR_DESWIZZLE_HIGH_Bit_50_OFF                      (20)
+  #define MCHBAR_CH0_CR_DESWIZZLE_HIGH_Bit_50_WID                      ( 3)
+  #define MCHBAR_CH0_CR_DESWIZZLE_HIGH_Bit_50_MSK                      (0x00700000)
+  #define MCHBAR_CH0_CR_DESWIZZLE_HIGH_Bit_50_MAX                      (0x00000007)
+  #define MCHBAR_CH0_CR_DESWIZZLE_HIGH_Bit_50_DEF                      (0x00000002)
+  #define MCHBAR_CH0_CR_DESWIZZLE_HIGH_Byte_4_OFF                      (24)
+  #define MCHBAR_CH0_CR_DESWIZZLE_HIGH_Byte_4_WID                      ( 3)
+  #define MCHBAR_CH0_CR_DESWIZZLE_HIGH_Byte_4_MSK                      (0x07000000)
+  #define MCHBAR_CH0_CR_DESWIZZLE_HIGH_Byte_4_MAX                      (0x00000007)
+  #define MCHBAR_CH0_CR_DESWIZZLE_HIGH_Byte_4_DEF                      (0x00000004)
+  #define MCHBAR_CH0_CR_DESWIZZLE_HIGH_Byte_6_OFF                      (28)
+  #define MCHBAR_CH0_CR_DESWIZZLE_HIGH_Byte_6_WID                      ( 3)
+  #define MCHBAR_CH0_CR_DESWIZZLE_HIGH_Byte_6_MSK                      (0x70000000)
+  #define MCHBAR_CH0_CR_DESWIZZLE_HIGH_Byte_6_MAX                      (0x00000007)
+  #define MCHBAR_CH0_CR_DESWIZZLE_HIGH_Byte_6_DEF                      (0x00000006)
+
+#define MCHBAR_CH0_CR_MC_REFRESH_STAGGER_REG                         (0x0000428C)
+  #define MCHBAR_CH0_CR_MC_REFRESH_STAGGER_Ref_Interval_OFF            ( 0)
+  #define MCHBAR_CH0_CR_MC_REFRESH_STAGGER_Ref_Interval_WID            (11)
+  #define MCHBAR_CH0_CR_MC_REFRESH_STAGGER_Ref_Interval_MSK            (0x000007FF)
+  #define MCHBAR_CH0_CR_MC_REFRESH_STAGGER_Ref_Interval_MAX            (0x000007FF)
+  #define MCHBAR_CH0_CR_MC_REFRESH_STAGGER_Ref_Interval_DEF            (0x00000000)
+  #define MCHBAR_CH0_CR_MC_REFRESH_STAGGER_Ref_Stagger_En_OFF          (11)
+  #define MCHBAR_CH0_CR_MC_REFRESH_STAGGER_Ref_Stagger_En_WID          ( 1)
+  #define MCHBAR_CH0_CR_MC_REFRESH_STAGGER_Ref_Stagger_En_MSK          (0x00000800)
+  #define MCHBAR_CH0_CR_MC_REFRESH_STAGGER_Ref_Stagger_En_MAX          (0x00000001)
+  #define MCHBAR_CH0_CR_MC_REFRESH_STAGGER_Ref_Stagger_En_DEF          (0x00000000)
+  #define MCHBAR_CH0_CR_MC_REFRESH_STAGGER_Ref_Stagger_Mode_OFF        (12)
+  #define MCHBAR_CH0_CR_MC_REFRESH_STAGGER_Ref_Stagger_Mode_WID        ( 1)
+  #define MCHBAR_CH0_CR_MC_REFRESH_STAGGER_Ref_Stagger_Mode_MSK        (0x00001000)
+  #define MCHBAR_CH0_CR_MC_REFRESH_STAGGER_Ref_Stagger_Mode_MAX        (0x00000001)
+  #define MCHBAR_CH0_CR_MC_REFRESH_STAGGER_Ref_Stagger_Mode_DEF        (0x00000000)
+  #define MCHBAR_CH0_CR_MC_REFRESH_STAGGER_Disable_Stolen_Refresh_OFF  (13)
+  #define MCHBAR_CH0_CR_MC_REFRESH_STAGGER_Disable_Stolen_Refresh_WID  ( 1)
+  #define MCHBAR_CH0_CR_MC_REFRESH_STAGGER_Disable_Stolen_Refresh_MSK  (0x00002000)
+  #define MCHBAR_CH0_CR_MC_REFRESH_STAGGER_Disable_Stolen_Refresh_MAX  (0x00000001)
+  #define MCHBAR_CH0_CR_MC_REFRESH_STAGGER_Disable_Stolen_Refresh_DEF  (0x00000000)
+  #define MCHBAR_CH0_CR_MC_REFRESH_STAGGER_En_Ref_Type_Display_OFF     (14)
+  #define MCHBAR_CH0_CR_MC_REFRESH_STAGGER_En_Ref_Type_Display_WID     ( 1)
+  #define MCHBAR_CH0_CR_MC_REFRESH_STAGGER_En_Ref_Type_Display_MSK     (0x00004000)
+  #define MCHBAR_CH0_CR_MC_REFRESH_STAGGER_En_Ref_Type_Display_MAX     (0x00000001)
+  #define MCHBAR_CH0_CR_MC_REFRESH_STAGGER_En_Ref_Type_Display_DEF     (0x00000000)
+
+#define MCHBAR_CH0_CR_TC_ZQCAL_REG                                   (0x00004290)
+  #define MCHBAR_CH0_CR_TC_ZQCAL_ZQCS_period_OFF                       ( 0)
+  #define MCHBAR_CH0_CR_TC_ZQCAL_ZQCS_period_WID                       ( 8)
+  #define MCHBAR_CH0_CR_TC_ZQCAL_ZQCS_period_MSK                       (0x000000FF)
+  #define MCHBAR_CH0_CR_TC_ZQCAL_ZQCS_period_MAX                       (0x000000FF)
+  #define MCHBAR_CH0_CR_TC_ZQCAL_ZQCS_period_DEF                       (0x00000080)
+  #define MCHBAR_CH0_CR_TC_ZQCAL_tZQCS_OFF                             ( 8)
+  #define MCHBAR_CH0_CR_TC_ZQCAL_tZQCS_WID                             ( 8)
+  #define MCHBAR_CH0_CR_TC_ZQCAL_tZQCS_MSK                             (0x0000FF00)
+  #define MCHBAR_CH0_CR_TC_ZQCAL_tZQCS_MAX                             (0x000000FF)
+  #define MCHBAR_CH0_CR_TC_ZQCAL_tZQCS_DEF                             (0x00000040)
+  #define MCHBAR_CH0_CR_TC_ZQCAL_ZQCS_period_Ult_OFF                   ( 0)
+  #define MCHBAR_CH0_CR_TC_ZQCAL_ZQCS_period_Ult_WID                   (10)
+  #define MCHBAR_CH0_CR_TC_ZQCAL_ZQCS_period_Ult_MSK                   (0x000003FF)
+  #define MCHBAR_CH0_CR_TC_ZQCAL_ZQCS_period_Ult_MAX                   (0x000003FF)
+  #define MCHBAR_CH0_CR_TC_ZQCAL_ZQCS_period_Ult_DEF                   (0x00000080)
+  #define MCHBAR_CH0_CR_TC_ZQCAL_tZQCS_Ult_OFF                         (10)
+  #define MCHBAR_CH0_CR_TC_ZQCAL_tZQCS_Ult_WID                         (10)
+  #define MCHBAR_CH0_CR_TC_ZQCAL_tZQCS_Ult_MSK                         (0x000FFC00)
+  #define MCHBAR_CH0_CR_TC_ZQCAL_tZQCS_Ult_MAX                         (0x000003FF)
+  #define MCHBAR_CH0_CR_TC_ZQCAL_tZQCS_Ult_DEF                         (0x00000040)
+
+#define MCHBAR_CH0_CR_TC_RFP_REG                                     (0x00004294)
+  #define MCHBAR_CH0_CR_TC_RFP_OREF_RI_OFF                             ( 0)
+  #define MCHBAR_CH0_CR_TC_RFP_OREF_RI_WID                             ( 8)
+  #define MCHBAR_CH0_CR_TC_RFP_OREF_RI_MSK                             (0x000000FF)
+  #define MCHBAR_CH0_CR_TC_RFP_OREF_RI_MAX                             (0x000000FF)
+  #define MCHBAR_CH0_CR_TC_RFP_OREF_RI_DEF                             (0x0000000F)
+  #define MCHBAR_CH0_CR_TC_RFP_Refresh_HP_WM_OFF                       ( 8)
+  #define MCHBAR_CH0_CR_TC_RFP_Refresh_HP_WM_WID                       ( 4)
+  #define MCHBAR_CH0_CR_TC_RFP_Refresh_HP_WM_MSK                       (0x00000F00)
+  #define MCHBAR_CH0_CR_TC_RFP_Refresh_HP_WM_MAX                       (0x0000000F)
+  #define MCHBAR_CH0_CR_TC_RFP_Refresh_HP_WM_DEF                       (0x00000008)
+  #define MCHBAR_CH0_CR_TC_RFP_Refresh_panic_wm_OFF                    (12)
+  #define MCHBAR_CH0_CR_TC_RFP_Refresh_panic_wm_WID                    ( 4)
+  #define MCHBAR_CH0_CR_TC_RFP_Refresh_panic_wm_MSK                    (0x0000F000)
+  #define MCHBAR_CH0_CR_TC_RFP_Refresh_panic_wm_MAX                    (0x0000000F)
+  #define MCHBAR_CH0_CR_TC_RFP_Refresh_panic_wm_DEF                    (0x00000009)
+
+#define MCHBAR_CH0_CR_TC_RFTP_REG                                    (0x00004298)
+  #define MCHBAR_CH0_CR_TC_RFTP_tREFI_OFF                              ( 0)
+  #define MCHBAR_CH0_CR_TC_RFTP_tREFI_WID                              (16)
+  #define MCHBAR_CH0_CR_TC_RFTP_tREFI_MSK                              (0x0000FFFF)
+  #define MCHBAR_CH0_CR_TC_RFTP_tREFI_MAX                              (0x0000FFFF)
+  #define MCHBAR_CH0_CR_TC_RFTP_tREFI_DEF                              (0x00001004)
+  #define MCHBAR_CH0_CR_TC_RFTP_tRFC_OFF                               (16)
+  #define MCHBAR_CH0_CR_TC_RFTP_tRFC_WID                               ( 9)
+  #define MCHBAR_CH0_CR_TC_RFTP_tRFC_MSK                               (0x01FF0000)
+  #define MCHBAR_CH0_CR_TC_RFTP_tRFC_MAX                               (0x000001FF)
+  #define MCHBAR_CH0_CR_TC_RFTP_tRFC_DEF                               (0x000000B4)
+  #define MCHBAR_CH0_CR_TC_RFTP_tREFIx9_OFF                            (25)
+  #define MCHBAR_CH0_CR_TC_RFTP_tREFIx9_WID                            ( 7)
+  #define MCHBAR_CH0_CR_TC_RFTP_tREFIx9_MSK                            (0xFE000000)
+  #define MCHBAR_CH0_CR_TC_RFTP_tREFIx9_MAX                            (0x0000007F)
+  #define MCHBAR_CH0_CR_TC_RFTP_tREFIx9_DEF                            (0x00000023)
+
+#define MCHBAR_CH0_CR_TC_MR2_SHADDOW_REG                             (0x0000429C)
+  #define MCHBAR_CH0_CR_TC_MR2_SHADDOW_MR2_sh_low_OFF                  ( 0)
+  #define MCHBAR_CH0_CR_TC_MR2_SHADDOW_MR2_sh_low_WID                  ( 6)
+  #define MCHBAR_CH0_CR_TC_MR2_SHADDOW_MR2_sh_low_MSK                  (0x0000003F)
+  #define MCHBAR_CH0_CR_TC_MR2_SHADDOW_MR2_sh_low_MAX                  (0x0000003F)
+  #define MCHBAR_CH0_CR_TC_MR2_SHADDOW_MR2_sh_low_DEF                  (0x00000000)
+  #define MCHBAR_CH0_CR_TC_MR2_SHADDOW_SRT_avail_OFF                   ( 6)
+  #define MCHBAR_CH0_CR_TC_MR2_SHADDOW_SRT_avail_WID                   ( 2)
+  #define MCHBAR_CH0_CR_TC_MR2_SHADDOW_SRT_avail_MSK                   (0x000000C0)
+  #define MCHBAR_CH0_CR_TC_MR2_SHADDOW_SRT_avail_MAX                   (0x00000003)
+  #define MCHBAR_CH0_CR_TC_MR2_SHADDOW_SRT_avail_DEF                   (0x00000000)
+  #define MCHBAR_CH0_CR_TC_MR2_SHADDOW_MR2_sh_high_OFF                 ( 8)
+  #define MCHBAR_CH0_CR_TC_MR2_SHADDOW_MR2_sh_high_WID                 ( 3)
+  #define MCHBAR_CH0_CR_TC_MR2_SHADDOW_MR2_sh_high_MSK                 (0x00000700)
+  #define MCHBAR_CH0_CR_TC_MR2_SHADDOW_MR2_sh_high_MAX                 (0x00000007)
+  #define MCHBAR_CH0_CR_TC_MR2_SHADDOW_MR2_sh_high_DEF                 (0x00000000)
+  #define MCHBAR_CH0_CR_TC_MR2_SHADDOW_Addr_bit_swizzle_OFF            (14)
+  #define MCHBAR_CH0_CR_TC_MR2_SHADDOW_Addr_bit_swizzle_WID            ( 2)
+  #define MCHBAR_CH0_CR_TC_MR2_SHADDOW_Addr_bit_swizzle_MSK            (0x0000C000)
+  #define MCHBAR_CH0_CR_TC_MR2_SHADDOW_Addr_bit_swizzle_MAX            (0x00000003)
+  #define MCHBAR_CH0_CR_TC_MR2_SHADDOW_Addr_bit_swizzle_DEF            (0x00000000)
+
+#define MCHBAR_CH0_CR_MC_INIT_STATE_REG                              (0x000042A0)
+  #define MCHBAR_CH0_CR_MC_INIT_STATE_Rank_occupancy_OFF               ( 0)
+  #define MCHBAR_CH0_CR_MC_INIT_STATE_Rank_occupancy_WID               ( 4)
+  #define MCHBAR_CH0_CR_MC_INIT_STATE_Rank_occupancy_MSK               (0x0000000F)
+  #define MCHBAR_CH0_CR_MC_INIT_STATE_Rank_occupancy_MAX               (0x0000000F)
+  #define MCHBAR_CH0_CR_MC_INIT_STATE_Rank_occupancy_DEF               (0x0000000F)
+
+#define MCHBAR_CH0_CR_TC_SRFTP_REG                                   (0x000042A4)
+  #define MCHBAR_CH0_CR_TC_SRFTP_tXSDLL_OFF                            ( 0)
+  #define MCHBAR_CH0_CR_TC_SRFTP_tXSDLL_WID                            (12)
+  #define MCHBAR_CH0_CR_TC_SRFTP_tXSDLL_MSK                            (0x00000FFF)
+  #define MCHBAR_CH0_CR_TC_SRFTP_tXSDLL_MAX                            (0x00000FFF)
+  #define MCHBAR_CH0_CR_TC_SRFTP_tXSDLL_DEF                            (0x00000200)
+  #define MCHBAR_CH0_CR_TC_SRFTP_tXS_offset_OFF                        (12)
+  #define MCHBAR_CH0_CR_TC_SRFTP_tXS_offset_WID                        ( 4)
+  #define MCHBAR_CH0_CR_TC_SRFTP_tXS_offset_MSK                        (0x0000F000)
+  #define MCHBAR_CH0_CR_TC_SRFTP_tXS_offset_MAX                        (0x0000000F)
+  #define MCHBAR_CH0_CR_TC_SRFTP_tXS_offset_DEF                        (0x0000000B)
+  #define MCHBAR_CH0_CR_TC_SRFTP_tZQOPER_OFF                           (16)
+  #define MCHBAR_CH0_CR_TC_SRFTP_tZQOPER_WID                           (10)
+  #define MCHBAR_CH0_CR_TC_SRFTP_tZQOPER_MSK                           (0x03FF0000)
+  #define MCHBAR_CH0_CR_TC_SRFTP_tZQOPER_MAX                           (0x000003FF)
+  #define MCHBAR_CH0_CR_TC_SRFTP_tZQOPER_DEF                           (0x00000100)
+  #define MCHBAR_CH0_CR_TC_SRFTP_tMOD_OFF                              (28)
+  #define MCHBAR_CH0_CR_TC_SRFTP_tMOD_WID                              ( 4)
+  #define MCHBAR_CH0_CR_TC_SRFTP_tMOD_MSK                              (0xF0000000)
+  #define MCHBAR_CH0_CR_TC_SRFTP_tMOD_MAX                              (0x0000000F)
+  #define MCHBAR_CH0_CR_TC_SRFTP_tMOD_DEF                              (0x00000000)
+
+#define MCHBAR_CH0_CR_WDB_VISA_SEL_REG                               (0x000042A8)
+  #define MCHBAR_CH0_CR_WDB_VISA_SEL_VISAByteSel_OFF                   ( 0)
+  #define MCHBAR_CH0_CR_WDB_VISA_SEL_VISAByteSel_WID                   ( 3)
+  #define MCHBAR_CH0_CR_WDB_VISA_SEL_VISAByteSel_MSK                   (0x00000007)
+  #define MCHBAR_CH0_CR_WDB_VISA_SEL_VISAByteSel_MAX                   (0x00000007)
+  #define MCHBAR_CH0_CR_WDB_VISA_SEL_VISAByteSel_DEF                   (0x00000000)
+
+#define MCHBAR_CH0_CR_DCLK_LDAT_PDAT_REG                             (0x000042C0)
+  #define MCHBAR_CH0_CR_DCLK_LDAT_PDAT_FASTADDR_OFF                    ( 0)
+  #define MCHBAR_CH0_CR_DCLK_LDAT_PDAT_FASTADDR_WID                    (12)
+  #define MCHBAR_CH0_CR_DCLK_LDAT_PDAT_FASTADDR_MSK                    (0x00000FFF)
+  #define MCHBAR_CH0_CR_DCLK_LDAT_PDAT_FASTADDR_MAX                    (0x00000FFF)
+  #define MCHBAR_CH0_CR_DCLK_LDAT_PDAT_FASTADDR_DEF                    (0x00000000)
+  #define MCHBAR_CH0_CR_DCLK_LDAT_PDAT_ADDREN_OFF                      (16)
+  #define MCHBAR_CH0_CR_DCLK_LDAT_PDAT_ADDREN_WID                      ( 1)
+  #define MCHBAR_CH0_CR_DCLK_LDAT_PDAT_ADDREN_MSK                      (0x00010000)
+  #define MCHBAR_CH0_CR_DCLK_LDAT_PDAT_ADDREN_MAX                      (0x00000001)
+  #define MCHBAR_CH0_CR_DCLK_LDAT_PDAT_ADDREN_DEF                      (0x00000000)
+  #define MCHBAR_CH0_CR_DCLK_LDAT_PDAT_SEQEN_OFF                       (17)
+  #define MCHBAR_CH0_CR_DCLK_LDAT_PDAT_SEQEN_WID                       ( 1)
+  #define MCHBAR_CH0_CR_DCLK_LDAT_PDAT_SEQEN_MSK                       (0x00020000)
+  #define MCHBAR_CH0_CR_DCLK_LDAT_PDAT_SEQEN_MAX                       (0x00000001)
+  #define MCHBAR_CH0_CR_DCLK_LDAT_PDAT_SEQEN_DEF                       (0x00000000)
+  #define MCHBAR_CH0_CR_DCLK_LDAT_PDAT_POL0_OFF                        (18)
+  #define MCHBAR_CH0_CR_DCLK_LDAT_PDAT_POL0_WID                        ( 1)
+  #define MCHBAR_CH0_CR_DCLK_LDAT_PDAT_POL0_MSK                        (0x00040000)
+  #define MCHBAR_CH0_CR_DCLK_LDAT_PDAT_POL0_MAX                        (0x00000001)
+  #define MCHBAR_CH0_CR_DCLK_LDAT_PDAT_POL0_DEF                        (0x00000000)
+  #define MCHBAR_CH0_CR_DCLK_LDAT_PDAT_POL1_OFF                        (19)
+  #define MCHBAR_CH0_CR_DCLK_LDAT_PDAT_POL1_WID                        ( 1)
+  #define MCHBAR_CH0_CR_DCLK_LDAT_PDAT_POL1_MSK                        (0x00080000)
+  #define MCHBAR_CH0_CR_DCLK_LDAT_PDAT_POL1_MAX                        (0x00000001)
+  #define MCHBAR_CH0_CR_DCLK_LDAT_PDAT_POL1_DEF                        (0x00000000)
+  #define MCHBAR_CH0_CR_DCLK_LDAT_PDAT_CMDA_OFF                        (20)
+  #define MCHBAR_CH0_CR_DCLK_LDAT_PDAT_CMDA_WID                        ( 4)
+  #define MCHBAR_CH0_CR_DCLK_LDAT_PDAT_CMDA_MSK                        (0x00F00000)
+  #define MCHBAR_CH0_CR_DCLK_LDAT_PDAT_CMDA_MAX                        (0x0000000F)
+  #define MCHBAR_CH0_CR_DCLK_LDAT_PDAT_CMDA_DEF                        (0x00000000)
+  #define MCHBAR_CH0_CR_DCLK_LDAT_PDAT_CMDB_OFF                        (24)
+  #define MCHBAR_CH0_CR_DCLK_LDAT_PDAT_CMDB_WID                        ( 4)
+  #define MCHBAR_CH0_CR_DCLK_LDAT_PDAT_CMDB_MSK                        (0x0F000000)
+  #define MCHBAR_CH0_CR_DCLK_LDAT_PDAT_CMDB_MAX                        (0x0000000F)
+  #define MCHBAR_CH0_CR_DCLK_LDAT_PDAT_CMDB_DEF                        (0x00000000)
+  #define MCHBAR_CH0_CR_DCLK_LDAT_PDAT_CMDC_OFF                        (28)
+  #define MCHBAR_CH0_CR_DCLK_LDAT_PDAT_CMDC_WID                        ( 4)
+  #define MCHBAR_CH0_CR_DCLK_LDAT_PDAT_CMDC_MSK                        (0xF0000000)
+  #define MCHBAR_CH0_CR_DCLK_LDAT_PDAT_CMDC_MAX                        (0x0000000F)
+  #define MCHBAR_CH0_CR_DCLK_LDAT_PDAT_CMDC_DEF                        (0x00000000)
+
+#define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_REG                             (0x000042C4)
+  #define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_BANKSEL_OFF                     ( 0)
+  #define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_BANKSEL_WID                     ( 4)
+  #define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_BANKSEL_MSK                     (0x0000000F)
+  #define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_BANKSEL_MAX                     (0x0000000F)
+  #define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_BANKSEL_DEF                     (0x00000000)
+  #define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_ARRAYSEL_OFF                    ( 5)
+  #define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_ARRAYSEL_WID                    ( 5)
+  #define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_ARRAYSEL_MSK                    (0x000003E0)
+  #define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_ARRAYSEL_MAX                    (0x0000001F)
+  #define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_ARRAYSEL_DEF                    (0x00000000)
+  #define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_CMP_OFF                         (10)
+  #define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_CMP_WID                         ( 1)
+  #define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_CMP_MSK                         (0x00000400)
+  #define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_CMP_MAX                         (0x00000001)
+  #define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_CMP_DEF                         (0x00000000)
+  #define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_REP_OFF                         (11)
+  #define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_REP_WID                         ( 1)
+  #define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_REP_MSK                         (0x00000800)
+  #define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_REP_MAX                         (0x00000001)
+  #define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_REP_DEF                         (0x00000000)
+  #define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_DWORD_OFF                       (12)
+  #define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_DWORD_WID                       ( 4)
+  #define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_DWORD_MSK                       (0x0000F000)
+  #define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_DWORD_MAX                       (0x0000000F)
+  #define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_DWORD_DEF                       (0x00000000)
+  #define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_MODE_OFF                        (16)
+  #define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_MODE_WID                        ( 2)
+  #define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_MODE_MSK                        (0x00030000)
+  #define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_MODE_MAX                        (0x00000003)
+  #define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_MODE_DEF                        (0x00000000)
+  #define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_MPMAP_OFF                       (18)
+  #define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_MPMAP_WID                       ( 6)
+  #define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_MPMAP_MSK                       (0x00FC0000)
+  #define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_MPMAP_MAX                       (0x0000003F)
+  #define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_MPMAP_DEF                       (0x00000000)
+  #define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_MPBOFFSET_OFF                   (24)
+  #define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_MPBOFFSET_WID                   ( 4)
+  #define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_MPBOFFSET_MSK                   (0x0F000000)
+  #define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_MPBOFFSET_MAX                   (0x0000000F)
+  #define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_MPBOFFSET_DEF                   (0x00000000)
+  #define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_STAGE_EN_OFF                    (28)
+  #define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_STAGE_EN_WID                    ( 1)
+  #define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_STAGE_EN_MSK                    (0x10000000)
+  #define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_STAGE_EN_MAX                    (0x00000001)
+  #define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_STAGE_EN_DEF                    (0x00000000)
+  #define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_SHADOW_OFF                      (29)
+  #define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_SHADOW_WID                      ( 2)
+  #define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_SHADOW_MSK                      (0x60000000)
+  #define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_SHADOW_MAX                      (0x00000003)
+  #define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_SHADOW_DEF                      (0x00000000)
+
+#define MCHBAR_CH0_CR_DCLK_LDAT_DATAOUT_REG                          (0x000042C8)
+  #define MCHBAR_CH0_CR_DCLK_LDAT_DATAOUT_DATOUT_OFF                   ( 0)
+  #define MCHBAR_CH0_CR_DCLK_LDAT_DATAOUT_DATOUT_WID                   (32)
+  #define MCHBAR_CH0_CR_DCLK_LDAT_DATAOUT_DATOUT_MSK                   (0xFFFFFFFF)
+  #define MCHBAR_CH0_CR_DCLK_LDAT_DATAOUT_DATOUT_MAX                   (0xFFFFFFFF)
+  #define MCHBAR_CH0_CR_DCLK_LDAT_DATAOUT_DATOUT_DEF                   (0x00000000)
+
+#define MCHBAR_CH0_CR_DCLK_LDAT_DATAIN_0_REG                         (0x000042CC)
+  #define MCHBAR_CH0_CR_DCLK_LDAT_DATAIN_0_DATIN_OFF                   ( 0)
+  #define MCHBAR_CH0_CR_DCLK_LDAT_DATAIN_0_DATIN_WID                   (32)
+  #define MCHBAR_CH0_CR_DCLK_LDAT_DATAIN_0_DATIN_MSK                   (0xFFFFFFFF)
+  #define MCHBAR_CH0_CR_DCLK_LDAT_DATAIN_0_DATIN_MAX                   (0xFFFFFFFF)
+  #define MCHBAR_CH0_CR_DCLK_LDAT_DATAIN_0_DATIN_DEF                   (0x00000000)
+
+#define MCHBAR_CH0_CR_QCLK_LDAT_PDAT_REG                             (0x000042D0)
+  #define MCHBAR_CH0_CR_QCLK_LDAT_PDAT_FASTADDR_OFF                    ( 0)
+  #define MCHBAR_CH0_CR_QCLK_LDAT_PDAT_FASTADDR_WID                    (12)
+  #define MCHBAR_CH0_CR_QCLK_LDAT_PDAT_FASTADDR_MSK                    (0x00000FFF)
+  #define MCHBAR_CH0_CR_QCLK_LDAT_PDAT_FASTADDR_MAX                    (0x00000FFF)
+  #define MCHBAR_CH0_CR_QCLK_LDAT_PDAT_FASTADDR_DEF                    (0x00000000)
+  #define MCHBAR_CH0_CR_QCLK_LDAT_PDAT_ADDREN_OFF                      (16)
+  #define MCHBAR_CH0_CR_QCLK_LDAT_PDAT_ADDREN_WID                      ( 1)
+  #define MCHBAR_CH0_CR_QCLK_LDAT_PDAT_ADDREN_MSK                      (0x00010000)
+  #define MCHBAR_CH0_CR_QCLK_LDAT_PDAT_ADDREN_MAX                      (0x00000001)
+  #define MCHBAR_CH0_CR_QCLK_LDAT_PDAT_ADDREN_DEF                      (0x00000000)
+  #define MCHBAR_CH0_CR_QCLK_LDAT_PDAT_SEQEN_OFF                       (17)
+  #define MCHBAR_CH0_CR_QCLK_LDAT_PDAT_SEQEN_WID                       ( 1)
+  #define MCHBAR_CH0_CR_QCLK_LDAT_PDAT_SEQEN_MSK                       (0x00020000)
+  #define MCHBAR_CH0_CR_QCLK_LDAT_PDAT_SEQEN_MAX                       (0x00000001)
+  #define MCHBAR_CH0_CR_QCLK_LDAT_PDAT_SEQEN_DEF                       (0x00000000)
+  #define MCHBAR_CH0_CR_QCLK_LDAT_PDAT_POL0_OFF                        (18)
+  #define MCHBAR_CH0_CR_QCLK_LDAT_PDAT_POL0_WID                        ( 1)
+  #define MCHBAR_CH0_CR_QCLK_LDAT_PDAT_POL0_MSK                        (0x00040000)
+  #define MCHBAR_CH0_CR_QCLK_LDAT_PDAT_POL0_MAX                        (0x00000001)
+  #define MCHBAR_CH0_CR_QCLK_LDAT_PDAT_POL0_DEF                        (0x00000000)
+  #define MCHBAR_CH0_CR_QCLK_LDAT_PDAT_POL1_OFF                        (19)
+  #define MCHBAR_CH0_CR_QCLK_LDAT_PDAT_POL1_WID                        ( 1)
+  #define MCHBAR_CH0_CR_QCLK_LDAT_PDAT_POL1_MSK                        (0x00080000)
+  #define MCHBAR_CH0_CR_QCLK_LDAT_PDAT_POL1_MAX                        (0x00000001)
+  #define MCHBAR_CH0_CR_QCLK_LDAT_PDAT_POL1_DEF                        (0x00000000)
+  #define MCHBAR_CH0_CR_QCLK_LDAT_PDAT_CMDA_OFF                        (20)
+  #define MCHBAR_CH0_CR_QCLK_LDAT_PDAT_CMDA_WID                        ( 4)
+  #define MCHBAR_CH0_CR_QCLK_LDAT_PDAT_CMDA_MSK                        (0x00F00000)
+  #define MCHBAR_CH0_CR_QCLK_LDAT_PDAT_CMDA_MAX                        (0x0000000F)
+  #define MCHBAR_CH0_CR_QCLK_LDAT_PDAT_CMDA_DEF                        (0x00000000)
+  #define MCHBAR_CH0_CR_QCLK_LDAT_PDAT_CMDB_OFF                        (24)
+  #define MCHBAR_CH0_CR_QCLK_LDAT_PDAT_CMDB_WID                        ( 4)
+  #define MCHBAR_CH0_CR_QCLK_LDAT_PDAT_CMDB_MSK                        (0x0F000000)
+  #define MCHBAR_CH0_CR_QCLK_LDAT_PDAT_CMDB_MAX                        (0x0000000F)
+  #define MCHBAR_CH0_CR_QCLK_LDAT_PDAT_CMDB_DEF                        (0x00000000)
+  #define MCHBAR_CH0_CR_QCLK_LDAT_PDAT_CMDC_OFF                        (28)
+  #define MCHBAR_CH0_CR_QCLK_LDAT_PDAT_CMDC_WID                        ( 4)
+  #define MCHBAR_CH0_CR_QCLK_LDAT_PDAT_CMDC_MSK                        (0xF0000000)
+  #define MCHBAR_CH0_CR_QCLK_LDAT_PDAT_CMDC_MAX                        (0x0000000F)
+  #define MCHBAR_CH0_CR_QCLK_LDAT_PDAT_CMDC_DEF                        (0x00000000)
+
+#define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_REG                             (0x000042D4)
+  #define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_BANKSEL_OFF                     ( 0)
+  #define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_BANKSEL_WID                     ( 4)
+  #define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_BANKSEL_MSK                     (0x0000000F)
+  #define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_BANKSEL_MAX                     (0x0000000F)
+  #define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_BANKSEL_DEF                     (0x00000000)
+  #define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_ARRAYSEL_OFF                    ( 5)
+  #define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_ARRAYSEL_WID                    ( 5)
+  #define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_ARRAYSEL_MSK                    (0x000003E0)
+  #define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_ARRAYSEL_MAX                    (0x0000001F)
+  #define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_ARRAYSEL_DEF                    (0x00000000)
+  #define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_CMP_OFF                         (10)
+  #define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_CMP_WID                         ( 1)
+  #define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_CMP_MSK                         (0x00000400)
+  #define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_CMP_MAX                         (0x00000001)
+  #define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_CMP_DEF                         (0x00000000)
+  #define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_REP_OFF                         (11)
+  #define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_REP_WID                         ( 1)
+  #define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_REP_MSK                         (0x00000800)
+  #define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_REP_MAX                         (0x00000001)
+  #define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_REP_DEF                         (0x00000000)
+  #define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_DWORD_OFF                       (12)
+  #define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_DWORD_WID                       ( 4)
+  #define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_DWORD_MSK                       (0x0000F000)
+  #define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_DWORD_MAX                       (0x0000000F)
+  #define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_DWORD_DEF                       (0x00000000)
+  #define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_MODE_OFF                        (16)
+  #define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_MODE_WID                        ( 2)
+  #define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_MODE_MSK                        (0x00030000)
+  #define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_MODE_MAX                        (0x00000003)
+  #define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_MODE_DEF                        (0x00000000)
+  #define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_MPMAP_OFF                       (18)
+  #define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_MPMAP_WID                       ( 6)
+  #define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_MPMAP_MSK                       (0x00FC0000)
+  #define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_MPMAP_MAX                       (0x0000003F)
+  #define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_MPMAP_DEF                       (0x00000000)
+  #define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_MPBOFFSET_OFF                   (24)
+  #define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_MPBOFFSET_WID                   ( 4)
+  #define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_MPBOFFSET_MSK                   (0x0F000000)
+  #define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_MPBOFFSET_MAX                   (0x0000000F)
+  #define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_MPBOFFSET_DEF                   (0x00000000)
+  #define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_STAGE_EN_OFF                    (28)
+  #define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_STAGE_EN_WID                    ( 1)
+  #define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_STAGE_EN_MSK                    (0x10000000)
+  #define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_STAGE_EN_MAX                    (0x00000001)
+  #define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_STAGE_EN_DEF                    (0x00000000)
+  #define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_SHADOW_OFF                      (29)
+  #define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_SHADOW_WID                      ( 2)
+  #define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_SHADOW_MSK                      (0x60000000)
+  #define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_SHADOW_MAX                      (0x00000003)
+  #define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_SHADOW_DEF                      (0x00000000)
+
+#define MCHBAR_CH0_CR_QCLK_LDAT_DATAOUT_REG                          (0x000042D8)
+  #define MCHBAR_CH0_CR_QCLK_LDAT_DATAOUT_DATOUT_OFF                   ( 0)
+  #define MCHBAR_CH0_CR_QCLK_LDAT_DATAOUT_DATOUT_WID                   (32)
+  #define MCHBAR_CH0_CR_QCLK_LDAT_DATAOUT_DATOUT_MSK                   (0xFFFFFFFF)
+  #define MCHBAR_CH0_CR_QCLK_LDAT_DATAOUT_DATOUT_MAX                   (0xFFFFFFFF)
+  #define MCHBAR_CH0_CR_QCLK_LDAT_DATAOUT_DATOUT_DEF                   (0x00000000)
+
+#define MCHBAR_CH0_CR_QCLK_LDAT_DATAIN_0_REG                         (0x000042DC)
+  #define MCHBAR_CH0_CR_QCLK_LDAT_DATAIN_0_DATIN_OFF                   ( 0)
+  #define MCHBAR_CH0_CR_QCLK_LDAT_DATAIN_0_DATIN_WID                   (32)
+  #define MCHBAR_CH0_CR_QCLK_LDAT_DATAIN_0_DATIN_MSK                   (0xFFFFFFFF)
+  #define MCHBAR_CH0_CR_QCLK_LDAT_DATAIN_0_DATIN_MAX                   (0xFFFFFFFF)
+  #define MCHBAR_CH0_CR_QCLK_LDAT_DATAIN_0_DATIN_DEF                   (0x00000000)
+
+#define MCHBAR_CH0_CR_QCLK_LDAT_DATAIN_1_REG                         (0x000042E0)
+  #define MCHBAR_CH0_CR_QCLK_LDAT_DATAIN_1_DATIN_OFF                   ( 0)
+  #define MCHBAR_CH0_CR_QCLK_LDAT_DATAIN_1_DATIN_WID                   (32)
+  #define MCHBAR_CH0_CR_QCLK_LDAT_DATAIN_1_DATIN_MSK                   (0xFFFFFFFF)
+  #define MCHBAR_CH0_CR_QCLK_LDAT_DATAIN_1_DATIN_MAX                   (0xFFFFFFFF)
+  #define MCHBAR_CH0_CR_QCLK_LDAT_DATAIN_1_DATIN_DEF                   (0x00000000)
+
+#define MCHBAR_CH0_CR_QUEUE_ENTRY_DISABLE_RPQ_REG                    (0x000042E4)
+  #define MCHBAR_CH0_CR_QUEUE_ENTRY_DISABLE_RPQ_RPQ_disable_OFF        ( 0)
+  #define MCHBAR_CH0_CR_QUEUE_ENTRY_DISABLE_RPQ_RPQ_disable_WID        (28)
+  #define MCHBAR_CH0_CR_QUEUE_ENTRY_DISABLE_RPQ_RPQ_disable_MSK        (0x0FFFFFFF)
+  #define MCHBAR_CH0_CR_QUEUE_ENTRY_DISABLE_RPQ_RPQ_disable_MAX        (0x0FFFFFFF)
+  #define MCHBAR_CH0_CR_QUEUE_ENTRY_DISABLE_RPQ_RPQ_disable_DEF        (0x00000000)
+
+#define MCHBAR_CH0_CR_QUEUE_ENTRY_DISABLE_WPQ_REG                    (0x000042E8)
+  #define MCHBAR_CH0_CR_QUEUE_ENTRY_DISABLE_WPQ_WPQ_disable_OFF        ( 0)
+  #define MCHBAR_CH0_CR_QUEUE_ENTRY_DISABLE_WPQ_WPQ_disable_WID        (32)
+  #define MCHBAR_CH0_CR_QUEUE_ENTRY_DISABLE_WPQ_WPQ_disable_MSK        (0xFFFFFFFF)
+  #define MCHBAR_CH0_CR_QUEUE_ENTRY_DISABLE_WPQ_WPQ_disable_MAX        (0xFFFFFFFF)
+  #define MCHBAR_CH0_CR_QUEUE_ENTRY_DISABLE_WPQ_WPQ_disable_DEF        (0x00000000)
+
+#define MCHBAR_CH0_CR_PM_DIMM_IDLE_ENERGY_REG                        (0x000042EC)
+  #define MCHBAR_CH0_CR_PM_DIMM_IDLE_ENERGY_DIMM0_IDLE_ENERGY_OFF      ( 0)
+  #define MCHBAR_CH0_CR_PM_DIMM_IDLE_ENERGY_DIMM0_IDLE_ENERGY_WID      ( 6)
+  #define MCHBAR_CH0_CR_PM_DIMM_IDLE_ENERGY_DIMM0_IDLE_ENERGY_MSK      (0x0000003F)
+  #define MCHBAR_CH0_CR_PM_DIMM_IDLE_ENERGY_DIMM0_IDLE_ENERGY_MAX      (0x0000003F)
+  #define MCHBAR_CH0_CR_PM_DIMM_IDLE_ENERGY_DIMM0_IDLE_ENERGY_DEF      (0x00000000)
+  #define MCHBAR_CH0_CR_PM_DIMM_IDLE_ENERGY_DIMM1_IDLE_ENERGY_OFF      ( 8)
+  #define MCHBAR_CH0_CR_PM_DIMM_IDLE_ENERGY_DIMM1_IDLE_ENERGY_WID      ( 6)
+  #define MCHBAR_CH0_CR_PM_DIMM_IDLE_ENERGY_DIMM1_IDLE_ENERGY_MSK      (0x00003F00)
+  #define MCHBAR_CH0_CR_PM_DIMM_IDLE_ENERGY_DIMM1_IDLE_ENERGY_MAX      (0x0000003F)
+  #define MCHBAR_CH0_CR_PM_DIMM_IDLE_ENERGY_DIMM1_IDLE_ENERGY_DEF      (0x00000000)
+
+#define MCHBAR_CH0_CR_PM_DIMM_PD_ENERGY_REG                          (0x000042F0)
+  #define MCHBAR_CH0_CR_PM_DIMM_PD_ENERGY_DIMM0_PD_ENERGY_OFF          ( 0)
+  #define MCHBAR_CH0_CR_PM_DIMM_PD_ENERGY_DIMM0_PD_ENERGY_WID          ( 6)
+  #define MCHBAR_CH0_CR_PM_DIMM_PD_ENERGY_DIMM0_PD_ENERGY_MSK          (0x0000003F)
+  #define MCHBAR_CH0_CR_PM_DIMM_PD_ENERGY_DIMM0_PD_ENERGY_MAX          (0x0000003F)
+  #define MCHBAR_CH0_CR_PM_DIMM_PD_ENERGY_DIMM0_PD_ENERGY_DEF          (0x00000000)
+  #define MCHBAR_CH0_CR_PM_DIMM_PD_ENERGY_DIMM1_PD_ENERGY_OFF          ( 8)
+  #define MCHBAR_CH0_CR_PM_DIMM_PD_ENERGY_DIMM1_PD_ENERGY_WID          ( 6)
+  #define MCHBAR_CH0_CR_PM_DIMM_PD_ENERGY_DIMM1_PD_ENERGY_MSK          (0x00003F00)
+  #define MCHBAR_CH0_CR_PM_DIMM_PD_ENERGY_DIMM1_PD_ENERGY_MAX          (0x0000003F)
+  #define MCHBAR_CH0_CR_PM_DIMM_PD_ENERGY_DIMM1_PD_ENERGY_DEF          (0x00000000)
+
+#define MCHBAR_CH0_CR_PM_DIMM_ACT_ENERGY_REG                         (0x000042F4)
+  #define MCHBAR_CH0_CR_PM_DIMM_ACT_ENERGY_DIMM0_ACT_ENERGY_OFF        ( 0)
+  #define MCHBAR_CH0_CR_PM_DIMM_ACT_ENERGY_DIMM0_ACT_ENERGY_WID        ( 8)
+  #define MCHBAR_CH0_CR_PM_DIMM_ACT_ENERGY_DIMM0_ACT_ENERGY_MSK        (0x000000FF)
+  #define MCHBAR_CH0_CR_PM_DIMM_ACT_ENERGY_DIMM0_ACT_ENERGY_MAX        (0x000000FF)
+  #define MCHBAR_CH0_CR_PM_DIMM_ACT_ENERGY_DIMM0_ACT_ENERGY_DEF        (0x00000000)
+  #define MCHBAR_CH0_CR_PM_DIMM_ACT_ENERGY_DIMM1_ACT_ENERGY_OFF        ( 8)
+  #define MCHBAR_CH0_CR_PM_DIMM_ACT_ENERGY_DIMM1_ACT_ENERGY_WID        ( 8)
+  #define MCHBAR_CH0_CR_PM_DIMM_ACT_ENERGY_DIMM1_ACT_ENERGY_MSK        (0x0000FF00)
+  #define MCHBAR_CH0_CR_PM_DIMM_ACT_ENERGY_DIMM1_ACT_ENERGY_MAX        (0x000000FF)
+  #define MCHBAR_CH0_CR_PM_DIMM_ACT_ENERGY_DIMM1_ACT_ENERGY_DEF        (0x00000000)
+
+#define MCHBAR_CH0_CR_PM_DIMM_RD_ENERGY_REG                          (0x000042F8)
+  #define MCHBAR_CH0_CR_PM_DIMM_RD_ENERGY_DIMM0_RD_ENERGY_OFF          ( 0)
+  #define MCHBAR_CH0_CR_PM_DIMM_RD_ENERGY_DIMM0_RD_ENERGY_WID          ( 8)
+  #define MCHBAR_CH0_CR_PM_DIMM_RD_ENERGY_DIMM0_RD_ENERGY_MSK          (0x000000FF)
+  #define MCHBAR_CH0_CR_PM_DIMM_RD_ENERGY_DIMM0_RD_ENERGY_MAX          (0x000000FF)
+  #define MCHBAR_CH0_CR_PM_DIMM_RD_ENERGY_DIMM0_RD_ENERGY_DEF          (0x00000000)
+  #define MCHBAR_CH0_CR_PM_DIMM_RD_ENERGY_DIMM1_RD_ENERGY_OFF          ( 8)
+  #define MCHBAR_CH0_CR_PM_DIMM_RD_ENERGY_DIMM1_RD_ENERGY_WID          ( 8)
+  #define MCHBAR_CH0_CR_PM_DIMM_RD_ENERGY_DIMM1_RD_ENERGY_MSK          (0x0000FF00)
+  #define MCHBAR_CH0_CR_PM_DIMM_RD_ENERGY_DIMM1_RD_ENERGY_MAX          (0x000000FF)
+  #define MCHBAR_CH0_CR_PM_DIMM_RD_ENERGY_DIMM1_RD_ENERGY_DEF          (0x00000000)
+
+#define MCHBAR_CH0_CR_PM_DIMM_WR_ENERGY_REG                          (0x000042FC)
+  #define MCHBAR_CH0_CR_PM_DIMM_WR_ENERGY_DIMM0_WR_ENERGY_OFF          ( 0)
+  #define MCHBAR_CH0_CR_PM_DIMM_WR_ENERGY_DIMM0_WR_ENERGY_WID          ( 8)
+  #define MCHBAR_CH0_CR_PM_DIMM_WR_ENERGY_DIMM0_WR_ENERGY_MSK          (0x000000FF)
+  #define MCHBAR_CH0_CR_PM_DIMM_WR_ENERGY_DIMM0_WR_ENERGY_MAX          (0x000000FF)
+  #define MCHBAR_CH0_CR_PM_DIMM_WR_ENERGY_DIMM0_WR_ENERGY_DEF          (0x00000000)
+  #define MCHBAR_CH0_CR_PM_DIMM_WR_ENERGY_DIMM1_WR_ENERGY_OFF          ( 8)
+  #define MCHBAR_CH0_CR_PM_DIMM_WR_ENERGY_DIMM1_WR_ENERGY_WID          ( 8)
+  #define MCHBAR_CH0_CR_PM_DIMM_WR_ENERGY_DIMM1_WR_ENERGY_MSK          (0x0000FF00)
+  #define MCHBAR_CH0_CR_PM_DIMM_WR_ENERGY_DIMM1_WR_ENERGY_MAX          (0x000000FF)
+  #define MCHBAR_CH0_CR_PM_DIMM_WR_ENERGY_DIMM1_WR_ENERGY_DEF          (0x00000000)
+
+#define MCHBAR_CH0_CR_PM_THRT_CKE_MIN_REG                            (0x00004328)
+  #define MCHBAR_CH0_CR_PM_THRT_CKE_MIN_CKE_MIN_OFF                    ( 0)
+  #define MCHBAR_CH0_CR_PM_THRT_CKE_MIN_CKE_MIN_WID                    ( 8)
+  #define MCHBAR_CH0_CR_PM_THRT_CKE_MIN_CKE_MIN_MSK                    (0x000000FF)
+  #define MCHBAR_CH0_CR_PM_THRT_CKE_MIN_CKE_MIN_MAX                    (0x000000FF)
+  #define MCHBAR_CH0_CR_PM_THRT_CKE_MIN_CKE_MIN_DEF                    (0x00000000)
+  #define MCHBAR_CH0_CR_PM_THRT_CKE_MIN_CKE_MIN_DEFEATURE_OFF          ( 8)
+  #define MCHBAR_CH0_CR_PM_THRT_CKE_MIN_CKE_MIN_DEFEATURE_WID          ( 1)
+  #define MCHBAR_CH0_CR_PM_THRT_CKE_MIN_CKE_MIN_DEFEATURE_MSK          (0x00000100)
+  #define MCHBAR_CH0_CR_PM_THRT_CKE_MIN_CKE_MIN_DEFEATURE_MAX          (0x00000001)
+  #define MCHBAR_CH0_CR_PM_THRT_CKE_MIN_CKE_MIN_DEFEATURE_DEF          (0x00000000)
+
+#define MCHBAR_CH0_CR_ODLAT_CMD_MATCH0_REG                           (0x00004340)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH0_ODT_OFF                       ( 0)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH0_ODT_WID                       ( 4)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH0_ODT_MSK                       (0x0000000F)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH0_ODT_MAX                       (0x0000000F)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH0_ODT_DEF                       (0x00000000)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH0_Web_OFF                       ( 4)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH0_Web_WID                       ( 1)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH0_Web_MSK                       (0x00000010)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH0_Web_MAX                       (0x00000001)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH0_Web_DEF                       (0x00000000)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH0_CASb_OFF                      ( 5)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH0_CASb_WID                      ( 1)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH0_CASb_MSK                      (0x00000020)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH0_CASb_MAX                      (0x00000001)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH0_CASb_DEF                      (0x00000000)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH0_RASb_OFF                      ( 6)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH0_RASb_WID                      ( 1)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH0_RASb_MSK                      (0x00000040)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH0_RASb_MAX                      (0x00000001)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH0_RASb_DEF                      (0x00000000)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH0_CSb_OFF                       ( 7)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH0_CSb_WID                       ( 4)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH0_CSb_MSK                       (0x00000780)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH0_CSb_MAX                       (0x0000000F)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH0_CSb_DEF                       (0x00000000)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH0_CKE_OFF                       (11)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH0_CKE_WID                       ( 4)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH0_CKE_MSK                       (0x00007800)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH0_CKE_MAX                       (0x0000000F)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH0_CKE_DEF                       (0x00000000)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH0_MA_OFF                        (15)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH0_MA_WID                        (16)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH0_MA_MSK                        (0x7FFF8000)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH0_MA_MAX                        (0x0000FFFF)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH0_MA_DEF                        (0x00000000)
+
+#define MCHBAR_CH0_CR_ODLAT_CMD_MATCH1_REG                           (0x00004344)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH1_ODT_OFF                       ( 0)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH1_ODT_WID                       ( 4)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH1_ODT_MSK                       (0x0000000F)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH1_ODT_MAX                       (0x0000000F)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH1_ODT_DEF                       (0x00000000)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH1_Web_OFF                       ( 4)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH1_Web_WID                       ( 1)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH1_Web_MSK                       (0x00000010)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH1_Web_MAX                       (0x00000001)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH1_Web_DEF                       (0x00000000)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH1_CASb_OFF                      ( 5)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH1_CASb_WID                      ( 1)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH1_CASb_MSK                      (0x00000020)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH1_CASb_MAX                      (0x00000001)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH1_CASb_DEF                      (0x00000000)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH1_RASb_OFF                      ( 6)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH1_RASb_WID                      ( 1)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH1_RASb_MSK                      (0x00000040)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH1_RASb_MAX                      (0x00000001)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH1_RASb_DEF                      (0x00000000)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH1_CSb_OFF                       ( 7)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH1_CSb_WID                       ( 4)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH1_CSb_MSK                       (0x00000780)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH1_CSb_MAX                       (0x0000000F)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH1_CSb_DEF                       (0x00000000)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH1_CKE_OFF                       (11)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH1_CKE_WID                       ( 4)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH1_CKE_MSK                       (0x00007800)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH1_CKE_MAX                       (0x0000000F)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH1_CKE_DEF                       (0x00000000)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH1_MA_OFF                        (15)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH1_MA_WID                        (16)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH1_MA_MSK                        (0x7FFF8000)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH1_MA_MAX                        (0x0000FFFF)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH1_MA_DEF                        (0x00000000)
+
+#define MCHBAR_CH0_CR_ODLAT_CMD_MATCH2_REG                           (0x00004348)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH2_ODT_OFF                       ( 0)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH2_ODT_WID                       ( 4)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH2_ODT_MSK                       (0x0000000F)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH2_ODT_MAX                       (0x0000000F)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH2_ODT_DEF                       (0x00000000)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH2_Web_OFF                       ( 4)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH2_Web_WID                       ( 1)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH2_Web_MSK                       (0x00000010)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH2_Web_MAX                       (0x00000001)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH2_Web_DEF                       (0x00000000)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH2_CASb_OFF                      ( 5)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH2_CASb_WID                      ( 1)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH2_CASb_MSK                      (0x00000020)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH2_CASb_MAX                      (0x00000001)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH2_CASb_DEF                      (0x00000000)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH2_RASb_OFF                      ( 6)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH2_RASb_WID                      ( 1)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH2_RASb_MSK                      (0x00000040)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH2_RASb_MAX                      (0x00000001)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH2_RASb_DEF                      (0x00000000)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH2_CSb_OFF                       ( 7)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH2_CSb_WID                       ( 4)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH2_CSb_MSK                       (0x00000780)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH2_CSb_MAX                       (0x0000000F)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH2_CSb_DEF                       (0x00000000)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH2_CKE_OFF                       (11)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH2_CKE_WID                       ( 4)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH2_CKE_MSK                       (0x00007800)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH2_CKE_MAX                       (0x0000000F)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH2_CKE_DEF                       (0x00000000)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH2_MA_OFF                        (15)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH2_MA_WID                        (16)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH2_MA_MSK                        (0x7FFF8000)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH2_MA_MAX                        (0x0000FFFF)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH2_MA_DEF                        (0x00000000)
+
+#define MCHBAR_CH0_CR_ODLAT_CMD_MATCH3_REG                           (0x0000434C)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH3_ODT_OFF                       ( 0)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH3_ODT_WID                       ( 4)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH3_ODT_MSK                       (0x0000000F)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH3_ODT_MAX                       (0x0000000F)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH3_ODT_DEF                       (0x00000000)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH3_Web_OFF                       ( 4)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH3_Web_WID                       ( 1)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH3_Web_MSK                       (0x00000010)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH3_Web_MAX                       (0x00000001)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH3_Web_DEF                       (0x00000000)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH3_CASb_OFF                      ( 5)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH3_CASb_WID                      ( 1)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH3_CASb_MSK                      (0x00000020)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH3_CASb_MAX                      (0x00000001)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH3_CASb_DEF                      (0x00000000)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH3_RASb_OFF                      ( 6)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH3_RASb_WID                      ( 1)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH3_RASb_MSK                      (0x00000040)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH3_RASb_MAX                      (0x00000001)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH3_RASb_DEF                      (0x00000000)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH3_CSb_OFF                       ( 7)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH3_CSb_WID                       ( 4)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH3_CSb_MSK                       (0x00000780)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH3_CSb_MAX                       (0x0000000F)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH3_CSb_DEF                       (0x00000000)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH3_CKE_OFF                       (11)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH3_CKE_WID                       ( 4)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH3_CKE_MSK                       (0x00007800)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH3_CKE_MAX                       (0x0000000F)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH3_CKE_DEF                       (0x00000000)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH3_MA_OFF                        (15)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH3_MA_WID                        (16)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH3_MA_MSK                        (0x7FFF8000)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH3_MA_MAX                        (0x0000FFFF)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH3_MA_DEF                        (0x00000000)
+
+#define MCHBAR_CH0_CR_ODLAT_CMD_MASK0_REG                            (0x00004350)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MASK0_ODT_OFF                        ( 0)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MASK0_ODT_WID                        ( 4)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MASK0_ODT_MSK                        (0x0000000F)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MASK0_ODT_MAX                        (0x0000000F)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MASK0_ODT_DEF                        (0x00000000)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MASK0_Web_OFF                        ( 4)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MASK0_Web_WID                        ( 1)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MASK0_Web_MSK                        (0x00000010)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MASK0_Web_MAX                        (0x00000001)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MASK0_Web_DEF                        (0x00000000)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MASK0_CASb_OFF                       ( 5)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MASK0_CASb_WID                       ( 1)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MASK0_CASb_MSK                       (0x00000020)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MASK0_CASb_MAX                       (0x00000001)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MASK0_CASb_DEF                       (0x00000000)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MASK0_RASb_OFF                       ( 6)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MASK0_RASb_WID                       ( 1)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MASK0_RASb_MSK                       (0x00000040)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MASK0_RASb_MAX                       (0x00000001)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MASK0_RASb_DEF                       (0x00000000)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MASK0_CSb_OFF                        ( 7)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MASK0_CSb_WID                        ( 4)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MASK0_CSb_MSK                        (0x00000780)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MASK0_CSb_MAX                        (0x0000000F)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MASK0_CSb_DEF                        (0x00000000)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MASK0_CKE_OFF                        (11)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MASK0_CKE_WID                        ( 4)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MASK0_CKE_MSK                        (0x00007800)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MASK0_CKE_MAX                        (0x0000000F)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MASK0_CKE_DEF                        (0x00000000)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MASK0_MA_OFF                         (15)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MASK0_MA_WID                         (16)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MASK0_MA_MSK                         (0x7FFF8000)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MASK0_MA_MAX                         (0x0000FFFF)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MASK0_MA_DEF                         (0x00000000)
+
+#define MCHBAR_CH0_CR_ODLAT_CMD_MASK1_REG                            (0x00004354)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MASK1_ODT_OFF                        ( 0)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MASK1_ODT_WID                        ( 4)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MASK1_ODT_MSK                        (0x0000000F)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MASK1_ODT_MAX                        (0x0000000F)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MASK1_ODT_DEF                        (0x00000000)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MASK1_Web_OFF                        ( 4)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MASK1_Web_WID                        ( 1)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MASK1_Web_MSK                        (0x00000010)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MASK1_Web_MAX                        (0x00000001)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MASK1_Web_DEF                        (0x00000000)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MASK1_CASb_OFF                       ( 5)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MASK1_CASb_WID                       ( 1)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MASK1_CASb_MSK                       (0x00000020)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MASK1_CASb_MAX                       (0x00000001)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MASK1_CASb_DEF                       (0x00000000)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MASK1_RASb_OFF                       ( 6)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MASK1_RASb_WID                       ( 1)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MASK1_RASb_MSK                       (0x00000040)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MASK1_RASb_MAX                       (0x00000001)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MASK1_RASb_DEF                       (0x00000000)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MASK1_CSb_OFF                        ( 7)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MASK1_CSb_WID                        ( 4)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MASK1_CSb_MSK                        (0x00000780)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MASK1_CSb_MAX                        (0x0000000F)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MASK1_CSb_DEF                        (0x00000000)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MASK1_CKE_OFF                        (11)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MASK1_CKE_WID                        ( 4)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MASK1_CKE_MSK                        (0x00007800)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MASK1_CKE_MAX                        (0x0000000F)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MASK1_CKE_DEF                        (0x00000000)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MASK1_MA_OFF                         (15)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MASK1_MA_WID                         (16)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MASK1_MA_MSK                         (0x7FFF8000)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MASK1_MA_MAX                         (0x0000FFFF)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MASK1_MA_DEF                         (0x00000000)
+
+#define MCHBAR_CH0_CR_ODLAT_CMD_MASK2_REG                            (0x00004358)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MASK2_ODT_OFF                        ( 0)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MASK2_ODT_WID                        ( 4)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MASK2_ODT_MSK                        (0x0000000F)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MASK2_ODT_MAX                        (0x0000000F)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MASK2_ODT_DEF                        (0x00000000)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MASK2_Web_OFF                        ( 4)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MASK2_Web_WID                        ( 1)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MASK2_Web_MSK                        (0x00000010)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MASK2_Web_MAX                        (0x00000001)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MASK2_Web_DEF                        (0x00000000)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MASK2_CASb_OFF                       ( 5)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MASK2_CASb_WID                       ( 1)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MASK2_CASb_MSK                       (0x00000020)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MASK2_CASb_MAX                       (0x00000001)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MASK2_CASb_DEF                       (0x00000000)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MASK2_RASb_OFF                       ( 6)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MASK2_RASb_WID                       ( 1)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MASK2_RASb_MSK                       (0x00000040)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MASK2_RASb_MAX                       (0x00000001)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MASK2_RASb_DEF                       (0x00000000)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MASK2_CSb_OFF                        ( 7)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MASK2_CSb_WID                        ( 4)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MASK2_CSb_MSK                        (0x00000780)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MASK2_CSb_MAX                        (0x0000000F)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MASK2_CSb_DEF                        (0x00000000)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MASK2_CKE_OFF                        (11)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MASK2_CKE_WID                        ( 4)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MASK2_CKE_MSK                        (0x00007800)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MASK2_CKE_MAX                        (0x0000000F)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MASK2_CKE_DEF                        (0x00000000)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MASK2_MA_OFF                         (15)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MASK2_MA_WID                         (16)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MASK2_MA_MSK                         (0x7FFF8000)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MASK2_MA_MAX                         (0x0000FFFF)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MASK2_MA_DEF                         (0x00000000)
+
+#define MCHBAR_CH0_CR_ODLAT_CMD_MASK3_REG                            (0x0000435C)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MASK3_ODT_OFF                        ( 0)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MASK3_ODT_WID                        ( 4)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MASK3_ODT_MSK                        (0x0000000F)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MASK3_ODT_MAX                        (0x0000000F)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MASK3_ODT_DEF                        (0x00000000)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MASK3_Web_OFF                        ( 4)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MASK3_Web_WID                        ( 1)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MASK3_Web_MSK                        (0x00000010)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MASK3_Web_MAX                        (0x00000001)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MASK3_Web_DEF                        (0x00000000)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MASK3_CASb_OFF                       ( 5)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MASK3_CASb_WID                       ( 1)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MASK3_CASb_MSK                       (0x00000020)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MASK3_CASb_MAX                       (0x00000001)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MASK3_CASb_DEF                       (0x00000000)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MASK3_RASb_OFF                       ( 6)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MASK3_RASb_WID                       ( 1)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MASK3_RASb_MSK                       (0x00000040)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MASK3_RASb_MAX                       (0x00000001)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MASK3_RASb_DEF                       (0x00000000)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MASK3_CSb_OFF                        ( 7)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MASK3_CSb_WID                        ( 4)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MASK3_CSb_MSK                        (0x00000780)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MASK3_CSb_MAX                        (0x0000000F)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MASK3_CSb_DEF                        (0x00000000)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MASK3_CKE_OFF                        (11)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MASK3_CKE_WID                        ( 4)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MASK3_CKE_MSK                        (0x00007800)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MASK3_CKE_MAX                        (0x0000000F)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MASK3_CKE_DEF                        (0x00000000)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MASK3_MA_OFF                         (15)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MASK3_MA_WID                         (16)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MASK3_MA_MSK                         (0x7FFF8000)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MASK3_MA_MAX                         (0x0000FFFF)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_MASK3_MA_DEF                         (0x00000000)
+
+#define MCHBAR_CH0_CR_ODLAT_CMD_BANK_REG                             (0x00004360)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_BANK_BankMatch0_OFF                  ( 0)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_BANK_BankMatch0_WID                  ( 3)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_BANK_BankMatch0_MSK                  (0x00000007)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_BANK_BankMatch0_MAX                  (0x00000007)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_BANK_BankMatch0_DEF                  (0x00000000)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_BANK_BankMatch1_OFF                  ( 3)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_BANK_BankMatch1_WID                  ( 3)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_BANK_BankMatch1_MSK                  (0x00000038)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_BANK_BankMatch1_MAX                  (0x00000007)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_BANK_BankMatch1_DEF                  (0x00000000)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_BANK_BankMatch2_OFF                  ( 6)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_BANK_BankMatch2_WID                  ( 3)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_BANK_BankMatch2_MSK                  (0x000001C0)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_BANK_BankMatch2_MAX                  (0x00000007)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_BANK_BankMatch2_DEF                  (0x00000000)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_BANK_BankMatch3_OFF                  ( 9)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_BANK_BankMatch3_WID                  ( 3)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_BANK_BankMatch3_MSK                  (0x00000E00)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_BANK_BankMatch3_MAX                  (0x00000007)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_BANK_BankMatch3_DEF                  (0x00000000)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_BANK_BankMask0_OFF                   (12)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_BANK_BankMask0_WID                   ( 3)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_BANK_BankMask0_MSK                   (0x00007000)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_BANK_BankMask0_MAX                   (0x00000007)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_BANK_BankMask0_DEF                   (0x00000000)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_BANK_BankMask1_OFF                   (15)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_BANK_BankMask1_WID                   ( 3)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_BANK_BankMask1_MSK                   (0x00038000)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_BANK_BankMask1_MAX                   (0x00000007)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_BANK_BankMask1_DEF                   (0x00000000)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_BANK_BankMask2_OFF                   (18)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_BANK_BankMask2_WID                   ( 3)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_BANK_BankMask2_MSK                   (0x001C0000)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_BANK_BankMask2_MAX                   (0x00000007)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_BANK_BankMask2_DEF                   (0x00000000)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_BANK_BankMask3_OFF                   (21)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_BANK_BankMask3_WID                   ( 3)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_BANK_BankMask3_MSK                   (0x00E00000)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_BANK_BankMask3_MAX                   (0x00000007)
+  #define MCHBAR_CH0_CR_ODLAT_CMD_BANK_BankMask3_DEF                   (0x00000000)
+
+#define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL0_REG                           (0x00004364)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL0_InputMatch_OFF                ( 0)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL0_InputMatch_WID                ( 4)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL0_InputMatch_MSK                (0x0000000F)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL0_InputMatch_MAX                (0x0000000F)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL0_InputMatch_DEF                (0x00000000)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL0_InputInvert_OFF               ( 4)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL0_InputInvert_WID               ( 4)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL0_InputInvert_MSK               (0x000000F0)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL0_InputInvert_MAX               (0x0000000F)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL0_InputInvert_DEF               (0x00000000)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL0_CountMatches_OFF              ( 8)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL0_CountMatches_WID              ( 1)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL0_CountMatches_MSK              (0x00000100)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL0_CountMatches_MAX              (0x00000001)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL0_CountMatches_DEF              (0x00000000)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL0_CounterThreshold_OFF          ( 9)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL0_CounterThreshold_WID          (15)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL0_CounterThreshold_MSK          (0x00FFFE00)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL0_CounterThreshold_MAX          (0x00007FFF)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL0_CounterThreshold_DEF          (0x00000000)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL0_CounterAction_OFF             (24)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL0_CounterAction_WID             ( 2)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL0_CounterAction_MSK             (0x03000000)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL0_CounterAction_MAX             (0x00000003)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL0_CounterAction_DEF             (0x00000000)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL0_CounterNextState_OFF          (26)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL0_CounterNextState_WID          ( 2)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL0_CounterNextState_MSK          (0x0C000000)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL0_CounterNextState_MAX          (0x00000003)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL0_CounterNextState_DEF          (0x00000000)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL0_MatchAction_OFF               (28)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL0_MatchAction_WID               ( 2)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL0_MatchAction_MSK               (0x30000000)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL0_MatchAction_MAX               (0x00000003)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL0_MatchAction_DEF               (0x00000000)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL0_MatchNextState_OFF            (30)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL0_MatchNextState_WID            ( 2)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL0_MatchNextState_MSK            (0xC0000000)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL0_MatchNextState_MAX            (0x00000003)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL0_MatchNextState_DEF            (0x00000000)
+
+#define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL1_REG                           (0x00004368)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL1_InputMatch_OFF                ( 0)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL1_InputMatch_WID                ( 4)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL1_InputMatch_MSK                (0x0000000F)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL1_InputMatch_MAX                (0x0000000F)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL1_InputMatch_DEF                (0x00000000)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL1_InputInvert_OFF               ( 4)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL1_InputInvert_WID               ( 4)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL1_InputInvert_MSK               (0x000000F0)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL1_InputInvert_MAX               (0x0000000F)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL1_InputInvert_DEF               (0x00000000)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL1_CountMatches_OFF              ( 8)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL1_CountMatches_WID              ( 1)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL1_CountMatches_MSK              (0x00000100)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL1_CountMatches_MAX              (0x00000001)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL1_CountMatches_DEF              (0x00000000)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL1_CounterThreshold_OFF          ( 9)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL1_CounterThreshold_WID          (15)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL1_CounterThreshold_MSK          (0x00FFFE00)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL1_CounterThreshold_MAX          (0x00007FFF)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL1_CounterThreshold_DEF          (0x00000000)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL1_CounterAction_OFF             (24)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL1_CounterAction_WID             ( 2)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL1_CounterAction_MSK             (0x03000000)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL1_CounterAction_MAX             (0x00000003)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL1_CounterAction_DEF             (0x00000000)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL1_CounterNextState_OFF          (26)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL1_CounterNextState_WID          ( 2)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL1_CounterNextState_MSK          (0x0C000000)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL1_CounterNextState_MAX          (0x00000003)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL1_CounterNextState_DEF          (0x00000000)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL1_MatchAction_OFF               (28)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL1_MatchAction_WID               ( 2)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL1_MatchAction_MSK               (0x30000000)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL1_MatchAction_MAX               (0x00000003)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL1_MatchAction_DEF               (0x00000000)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL1_MatchNextState_OFF            (30)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL1_MatchNextState_WID            ( 2)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL1_MatchNextState_MSK            (0xC0000000)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL1_MatchNextState_MAX            (0x00000003)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL1_MatchNextState_DEF            (0x00000000)
+
+#define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL2_REG                           (0x0000436C)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL2_InputMatch_OFF                ( 0)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL2_InputMatch_WID                ( 4)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL2_InputMatch_MSK                (0x0000000F)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL2_InputMatch_MAX                (0x0000000F)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL2_InputMatch_DEF                (0x00000000)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL2_InputInvert_OFF               ( 4)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL2_InputInvert_WID               ( 4)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL2_InputInvert_MSK               (0x000000F0)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL2_InputInvert_MAX               (0x0000000F)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL2_InputInvert_DEF               (0x00000000)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL2_CountMatches_OFF              ( 8)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL2_CountMatches_WID              ( 1)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL2_CountMatches_MSK              (0x00000100)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL2_CountMatches_MAX              (0x00000001)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL2_CountMatches_DEF              (0x00000000)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL2_CounterThreshold_OFF          ( 9)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL2_CounterThreshold_WID          (15)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL2_CounterThreshold_MSK          (0x00FFFE00)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL2_CounterThreshold_MAX          (0x00007FFF)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL2_CounterThreshold_DEF          (0x00000000)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL2_CounterAction_OFF             (24)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL2_CounterAction_WID             ( 2)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL2_CounterAction_MSK             (0x03000000)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL2_CounterAction_MAX             (0x00000003)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL2_CounterAction_DEF             (0x00000000)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL2_CounterNextState_OFF          (26)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL2_CounterNextState_WID          ( 2)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL2_CounterNextState_MSK          (0x0C000000)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL2_CounterNextState_MAX          (0x00000003)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL2_CounterNextState_DEF          (0x00000000)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL2_MatchAction_OFF               (28)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL2_MatchAction_WID               ( 2)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL2_MatchAction_MSK               (0x30000000)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL2_MatchAction_MAX               (0x00000003)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL2_MatchAction_DEF               (0x00000000)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL2_MatchNextState_OFF            (30)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL2_MatchNextState_WID            ( 2)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL2_MatchNextState_MSK            (0xC0000000)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL2_MatchNextState_MAX            (0x00000003)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL2_MatchNextState_DEF            (0x00000000)
+
+#define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL3_REG                           (0x00004370)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL3_InputMatch_OFF                ( 0)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL3_InputMatch_WID                ( 4)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL3_InputMatch_MSK                (0x0000000F)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL3_InputMatch_MAX                (0x0000000F)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL3_InputMatch_DEF                (0x00000000)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL3_InputInvert_OFF               ( 4)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL3_InputInvert_WID               ( 4)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL3_InputInvert_MSK               (0x000000F0)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL3_InputInvert_MAX               (0x0000000F)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL3_InputInvert_DEF               (0x00000000)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL3_CountMatches_OFF              ( 8)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL3_CountMatches_WID              ( 1)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL3_CountMatches_MSK              (0x00000100)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL3_CountMatches_MAX              (0x00000001)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL3_CountMatches_DEF              (0x00000000)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL3_CounterThreshold_OFF          ( 9)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL3_CounterThreshold_WID          (15)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL3_CounterThreshold_MSK          (0x00FFFE00)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL3_CounterThreshold_MAX          (0x00007FFF)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL3_CounterThreshold_DEF          (0x00000000)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL3_CounterAction_OFF             (24)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL3_CounterAction_WID             ( 2)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL3_CounterAction_MSK             (0x03000000)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL3_CounterAction_MAX             (0x00000003)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL3_CounterAction_DEF             (0x00000000)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL3_CounterNextState_OFF          (26)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL3_CounterNextState_WID          ( 2)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL3_CounterNextState_MSK          (0x0C000000)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL3_CounterNextState_MAX          (0x00000003)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL3_CounterNextState_DEF          (0x00000000)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL3_MatchAction_OFF               (28)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL3_MatchAction_WID               ( 2)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL3_MatchAction_MSK               (0x30000000)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL3_MatchAction_MAX               (0x00000003)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL3_MatchAction_DEF               (0x00000000)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL3_MatchNextState_OFF            (30)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL3_MatchNextState_WID            ( 2)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL3_MatchNextState_MSK            (0xC0000000)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL3_MatchNextState_MAX            (0x00000003)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL3_MatchNextState_DEF            (0x00000000)
+
+#define MCHBAR_CH0_CR_ODLAT_SEQ_GLOBAL_REG                           (0x00004374)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_GLOBAL_TriggerBlockEnable_OFF        ( 0)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_GLOBAL_TriggerBlockEnable_WID        ( 1)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_GLOBAL_TriggerBlockEnable_MSK        (0x00000001)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_GLOBAL_TriggerBlockEnable_MAX        (0x00000001)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_GLOBAL_TriggerBlockEnable_DEF        (0x00000000)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_GLOBAL_GlobalCounterThreshold_OFF    ( 1)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_GLOBAL_GlobalCounterThreshold_WID    (16)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_GLOBAL_GlobalCounterThreshold_MSK    (0x0001FFFE)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_GLOBAL_GlobalCounterThreshold_MAX    (0x0000FFFF)
+  #define MCHBAR_CH0_CR_ODLAT_SEQ_GLOBAL_GlobalCounterThreshold_DEF    (0x00000000)
+
+#define MCHBAR_CH0_CR_SC_WDBWM_REG                                   (0x0000438C)
+  #define MCHBAR_CH0_CR_SC_WDBWM_WMM_Enter_OFF                         ( 0)
+  #define MCHBAR_CH0_CR_SC_WDBWM_WMM_Enter_WID                         ( 8)
+  #define MCHBAR_CH0_CR_SC_WDBWM_WMM_Enter_MSK                         (0x000000FF)
+  #define MCHBAR_CH0_CR_SC_WDBWM_WMM_Enter_MAX                         (0x000000FF)
+  #define MCHBAR_CH0_CR_SC_WDBWM_WMM_Enter_DEF                         (0x00000038)
+  #define MCHBAR_CH0_CR_SC_WDBWM_WMM_Exit_OFF                          ( 8)
+  #define MCHBAR_CH0_CR_SC_WDBWM_WMM_Exit_WID                          ( 8)
+  #define MCHBAR_CH0_CR_SC_WDBWM_WMM_Exit_MSK                          (0x0000FF00)
+  #define MCHBAR_CH0_CR_SC_WDBWM_WMM_Exit_MAX                          (0x000000FF)
+  #define MCHBAR_CH0_CR_SC_WDBWM_WMM_Exit_DEF                          (0x00000030)
+  #define MCHBAR_CH0_CR_SC_WDBWM_WPQ_IS_OFF                            (16)
+  #define MCHBAR_CH0_CR_SC_WDBWM_WPQ_IS_WID                            ( 8)
+  #define MCHBAR_CH0_CR_SC_WDBWM_WPQ_IS_MSK                            (0x00FF0000)
+  #define MCHBAR_CH0_CR_SC_WDBWM_WPQ_IS_MAX                            (0x000000FF)
+  #define MCHBAR_CH0_CR_SC_WDBWM_WPQ_IS_DEF                            (0x0000003C)
+  #define MCHBAR_CH0_CR_SC_WDBWM_Starve_count_OFF                      (24)
+  #define MCHBAR_CH0_CR_SC_WDBWM_Starve_count_WID                      ( 8)
+  #define MCHBAR_CH0_CR_SC_WDBWM_Starve_count_MSK                      (0xFF000000)
+  #define MCHBAR_CH0_CR_SC_WDBWM_Starve_count_MAX                      (0x000000FF)
+  #define MCHBAR_CH0_CR_SC_WDBWM_Starve_count_DEF                      (0x000000FF)
+
+#define MCHBAR_CH0_CR_VISA_CTL_MCMNTS_REG                            (0x00004390)
+  #define MCHBAR_CH0_CR_VISA_CTL_MCMNTS_Data_OFF                       ( 0)
+  #define MCHBAR_CH0_CR_VISA_CTL_MCMNTS_Data_WID                       (18)
+  #define MCHBAR_CH0_CR_VISA_CTL_MCMNTS_Data_MSK                       (0x0003FFFF)
+  #define MCHBAR_CH0_CR_VISA_CTL_MCMNTS_Data_MAX                       (0x0003FFFF)
+  #define MCHBAR_CH0_CR_VISA_CTL_MCMNTS_Data_DEF                       (0x00000000)
+  #define MCHBAR_CH0_CR_VISA_CTL_MCMNTS_VORANGE_OFF                    (31)
+  #define MCHBAR_CH0_CR_VISA_CTL_MCMNTS_VORANGE_WID                    ( 1)
+  #define MCHBAR_CH0_CR_VISA_CTL_MCMNTS_VORANGE_MSK                    (0x80000000)
+  #define MCHBAR_CH0_CR_VISA_CTL_MCMNTS_VORANGE_MAX                    (0x00000001)
+  #define MCHBAR_CH0_CR_VISA_CTL_MCMNTS_VORANGE_DEF                    (0x00000000)
+
+#define MCHBAR_CH1_CR_TC_BANK_REG                                    (0x00004400)
+  #define MCHBAR_CH1_CR_TC_BANK_tRCD_OFF                               ( 0)
+  #define MCHBAR_CH1_CR_TC_BANK_tRCD_WID                               ( 5)
+  #define MCHBAR_CH1_CR_TC_BANK_tRCD_MSK                               (0x0000001F)
+  #define MCHBAR_CH1_CR_TC_BANK_tRCD_MAX                               (0x0000001F)
+  #define MCHBAR_CH1_CR_TC_BANK_tRCD_DEF                               (0x00000006)
+  #define MCHBAR_CH1_CR_TC_BANK_tRP_OFF                                ( 5)
+  #define MCHBAR_CH1_CR_TC_BANK_tRP_WID                                ( 5)
+  #define MCHBAR_CH1_CR_TC_BANK_tRP_MSK                                (0x000003E0)
+  #define MCHBAR_CH1_CR_TC_BANK_tRP_MAX                                (0x0000001F)
+  #define MCHBAR_CH1_CR_TC_BANK_tRP_DEF                                (0x00000006)
+  #define MCHBAR_CH1_CR_TC_BANK_tRAS_OFF                               (10)
+  #define MCHBAR_CH1_CR_TC_BANK_tRAS_WID                               ( 6)
+  #define MCHBAR_CH1_CR_TC_BANK_tRAS_MSK                               (0x0000FC00)
+  #define MCHBAR_CH1_CR_TC_BANK_tRAS_MAX                               (0x0000003F)
+  #define MCHBAR_CH1_CR_TC_BANK_tRAS_DEF                               (0x00000014)
+  #define MCHBAR_CH1_CR_TC_BANK_tRDPRE_OFF                             (16)
+  #define MCHBAR_CH1_CR_TC_BANK_tRDPRE_WID                             ( 4)
+  #define MCHBAR_CH1_CR_TC_BANK_tRDPRE_MSK                             (0x000F0000)
+  #define MCHBAR_CH1_CR_TC_BANK_tRDPRE_MAX                             (0x0000000F)
+  #define MCHBAR_CH1_CR_TC_BANK_tRDPRE_DEF                             (0x00000004)
+  #define MCHBAR_CH1_CR_TC_BANK_tWRPRE_OFF                             (20)
+  #define MCHBAR_CH1_CR_TC_BANK_tWRPRE_WID                             ( 6)
+  #define MCHBAR_CH1_CR_TC_BANK_tWRPRE_MSK                             (0x03F00000)
+  #define MCHBAR_CH1_CR_TC_BANK_tWRPRE_MAX                             (0x0000003F)
+  #define MCHBAR_CH1_CR_TC_BANK_tWRPRE_DEF                             (0x00000004)
+  #define MCHBAR_CH1_CR_TC_BANK_tRRD_OFF                               (26)
+  #define MCHBAR_CH1_CR_TC_BANK_tRRD_WID                               ( 4)
+  #define MCHBAR_CH1_CR_TC_BANK_tRRD_MSK                               (0x3C000000)
+  #define MCHBAR_CH1_CR_TC_BANK_tRRD_MAX                               (0x0000000F)
+  #define MCHBAR_CH1_CR_TC_BANK_tRRD_DEF                               (0x00000004)
+  #define MCHBAR_CH1_CR_TC_BANK_tRPab_ext_OFF                          (30)
+  #define MCHBAR_CH1_CR_TC_BANK_tRPab_ext_WID                          ( 2)
+  #define MCHBAR_CH1_CR_TC_BANK_tRPab_ext_MSK                          (0xC0000000)
+  #define MCHBAR_CH1_CR_TC_BANK_tRPab_ext_MAX                          (0x00000003)
+  #define MCHBAR_CH1_CR_TC_BANK_tRPab_ext_DEF                          (0x00000000)
+
+#define MCHBAR_CH1_CR_TC_BANK_RANK_A_REG                             (0x00004404)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_A_tCKE_OFF                        ( 0)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_A_tCKE_WID                        ( 4)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_A_tCKE_MSK                        (0x0000000F)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_A_tCKE_MAX                        (0x0000000F)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_A_tCKE_DEF                        (0x00000003)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_A_tFAW_OFF                        ( 4)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_A_tFAW_WID                        ( 8)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_A_tFAW_MSK                        (0x00000FF0)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_A_tFAW_MAX                        (0x000000FF)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_A_tFAW_DEF                        (0x00000010)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_A_tRDRD_OFF                       (12)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_A_tRDRD_WID                       ( 3)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_A_tRDRD_MSK                       (0x00007000)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_A_tRDRD_MAX                       (0x00000007)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_A_tRDRD_DEF                       (0x00000004)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_A_tRDRD_dr_OFF                    (15)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_A_tRDRD_dr_WID                    ( 4)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_A_tRDRD_dr_MSK                    (0x00078000)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_A_tRDRD_dr_MAX                    (0x0000000F)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_A_tRDRD_dr_DEF                    (0x00000004)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_A_tRDRD_dd_OFF                    (19)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_A_tRDRD_dd_WID                    ( 4)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_A_tRDRD_dd_MSK                    (0x00780000)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_A_tRDRD_dd_MAX                    (0x0000000F)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_A_tRDRD_dd_DEF                    (0x00000004)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_A_tRDPDEN_OFF                     (23)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_A_tRDPDEN_WID                     ( 5)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_A_tRDPDEN_MSK                     (0x0F800000)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_A_tRDPDEN_MAX                     (0x0000001F)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_A_tRDPDEN_DEF                     (0x00000004)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_A_CMD_3st_OFF                     (29)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_A_CMD_3st_WID                     ( 1)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_A_CMD_3st_MSK                     (0x20000000)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_A_CMD_3st_MAX                     (0x00000001)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_A_CMD_3st_DEF                     (0x00000000)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_A_CMD_stretch_OFF                 (30)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_A_CMD_stretch_WID                 ( 2)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_A_CMD_stretch_MSK                 (0xC0000000)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_A_CMD_stretch_MAX                 (0x00000003)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_A_CMD_stretch_DEF                 (0x00000002)
+
+#define MCHBAR_CH1_CR_TC_BANK_RANK_B_REG                             (0x00004408)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_B_tWRRD_OFF                       ( 0)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_B_tWRRD_WID                       ( 6)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_B_tWRRD_MSK                       (0x0000003F)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_B_tWRRD_MAX                       (0x0000003F)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_B_tWRRD_DEF                       (0x00000005)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_B_tWRRD_dr_OFF                    ( 6)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_B_tWRRD_dr_WID                    ( 4)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_B_tWRRD_dr_MSK                    (0x000003C0)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_B_tWRRD_dr_MAX                    (0x0000000F)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_B_tWRRD_dr_DEF                    (0x00000005)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_B_tWRRD_dd_OFF                    (10)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_B_tWRRD_dd_WID                    ( 4)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_B_tWRRD_dd_MSK                    (0x00003C00)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_B_tWRRD_dd_MAX                    (0x0000000F)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_B_tWRRD_dd_DEF                    (0x00000005)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_B_tWRWR_OFF                       (14)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_B_tWRWR_WID                       ( 3)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_B_tWRWR_MSK                       (0x0001C000)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_B_tWRWR_MAX                       (0x00000007)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_B_tWRWR_DEF                       (0x00000005)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_B_tWRWR_dr_OFF                    (17)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_B_tWRWR_dr_WID                    ( 4)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_B_tWRWR_dr_MSK                    (0x001E0000)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_B_tWRWR_dr_MAX                    (0x0000000F)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_B_tWRWR_dr_DEF                    (0x00000005)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_B_tWRWR_dd_OFF                    (21)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_B_tWRWR_dd_WID                    ( 4)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_B_tWRWR_dd_MSK                    (0x01E00000)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_B_tWRWR_dd_MAX                    (0x0000000F)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_B_tWRWR_dd_DEF                    (0x00000005)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_B_tWRPDEN_OFF                     (25)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_B_tWRPDEN_WID                     ( 6)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_B_tWRPDEN_MSK                     (0x7E000000)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_B_tWRPDEN_MAX                     (0x0000003F)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_B_tWRPDEN_DEF                     (0x00000005)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_B_Dec_WRD_OFF                     (31)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_B_Dec_WRD_WID                     ( 1)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_B_Dec_WRD_MSK                     (0x80000000)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_B_Dec_WRD_MAX                     (0x00000001)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_B_Dec_WRD_DEF                     (0x00000000)
+
+#define MCHBAR_CH1_CR_TC_BANK_RANK_C_REG                             (0x0000440C)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_C_tXPDLL_OFF                      ( 0)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_C_tXPDLL_WID                      ( 6)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_C_tXPDLL_MSK                      (0x0000003F)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_C_tXPDLL_MAX                      (0x0000003F)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_C_tXPDLL_DEF                      (0x0000000A)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_C_tXP_OFF                         ( 6)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_C_tXP_WID                         ( 4)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_C_tXP_MSK                         (0x000003C0)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_C_tXP_MAX                         (0x0000000F)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_C_tXP_DEF                         (0x00000003)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_C_TAONPD_OFF                      (10)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_C_TAONPD_WID                      ( 4)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_C_TAONPD_MSK                      (0x00003C00)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_C_TAONPD_MAX                      (0x0000000F)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_C_TAONPD_DEF                      (0x00000009)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_C_tRDWR_OFF                       (14)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_C_tRDWR_WID                       ( 5)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_C_tRDWR_MSK                       (0x0007C000)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_C_tRDWR_MAX                       (0x0000001F)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_C_tRDWR_DEF                       (0x00000005)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_C_tRDWR_dr_OFF                    (19)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_C_tRDWR_dr_WID                    ( 5)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_C_tRDWR_dr_MSK                    (0x00F80000)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_C_tRDWR_dr_MAX                    (0x0000001F)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_C_tRDWR_dr_DEF                    (0x00000005)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_C_tRDWR_dd_OFF                    (24)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_C_tRDWR_dd_WID                    ( 5)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_C_tRDWR_dd_MSK                    (0x1F000000)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_C_tRDWR_dd_MAX                    (0x0000001F)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_C_tRDWR_dd_DEF                    (0x00000005)
+
+#define MCHBAR_CH1_CR_CMD_RATE_REG                                   (0x00004410)
+  #define MCHBAR_CH1_CR_CMD_RATE_enable_cmd_rate_limit_OFF             ( 0)
+  #define MCHBAR_CH1_CR_CMD_RATE_enable_cmd_rate_limit_WID             ( 1)
+  #define MCHBAR_CH1_CR_CMD_RATE_enable_cmd_rate_limit_MSK             (0x00000001)
+  #define MCHBAR_CH1_CR_CMD_RATE_enable_cmd_rate_limit_MAX             (0x00000001)
+  #define MCHBAR_CH1_CR_CMD_RATE_enable_cmd_rate_limit_DEF             (0x00000000)
+  #define MCHBAR_CH1_CR_CMD_RATE_cmd_rate_limit_OFF                    ( 1)
+  #define MCHBAR_CH1_CR_CMD_RATE_cmd_rate_limit_WID                    ( 3)
+  #define MCHBAR_CH1_CR_CMD_RATE_cmd_rate_limit_MSK                    (0x0000000E)
+  #define MCHBAR_CH1_CR_CMD_RATE_cmd_rate_limit_MAX                    (0x00000007)
+  #define MCHBAR_CH1_CR_CMD_RATE_cmd_rate_limit_DEF                    (0x00000004)
+  #define MCHBAR_CH1_CR_CMD_RATE_reset_on_command_OFF                  ( 4)
+  #define MCHBAR_CH1_CR_CMD_RATE_reset_on_command_WID                  ( 4)
+  #define MCHBAR_CH1_CR_CMD_RATE_reset_on_command_MSK                  (0x000000F0)
+  #define MCHBAR_CH1_CR_CMD_RATE_reset_on_command_MAX                  (0x0000000F)
+  #define MCHBAR_CH1_CR_CMD_RATE_reset_on_command_DEF                  (0x00000000)
+  #define MCHBAR_CH1_CR_CMD_RATE_reset_delay_OFF                       ( 8)
+  #define MCHBAR_CH1_CR_CMD_RATE_reset_delay_WID                       ( 4)
+  #define MCHBAR_CH1_CR_CMD_RATE_reset_delay_MSK                       (0x00000F00)
+  #define MCHBAR_CH1_CR_CMD_RATE_reset_delay_MAX                       (0x0000000F)
+  #define MCHBAR_CH1_CR_CMD_RATE_reset_delay_DEF                       (0x00000000)
+  #define MCHBAR_CH1_CR_CMD_RATE_ck_to_cke_delay_OFF                   (12)
+  #define MCHBAR_CH1_CR_CMD_RATE_ck_to_cke_delay_WID                   ( 2)
+  #define MCHBAR_CH1_CR_CMD_RATE_ck_to_cke_delay_MSK                   (0x00003000)
+  #define MCHBAR_CH1_CR_CMD_RATE_ck_to_cke_delay_MAX                   (0x00000003)
+  #define MCHBAR_CH1_CR_CMD_RATE_ck_to_cke_delay_DEF                   (0x00000001)
+  #define MCHBAR_CH1_CR_CMD_RATE_spare_OFF                             (14)
+  #define MCHBAR_CH1_CR_CMD_RATE_spare_WID                             (17)
+  #define MCHBAR_CH1_CR_CMD_RATE_spare_MSK                             (0x7FFFC000)
+  #define MCHBAR_CH1_CR_CMD_RATE_spare_MAX                             (0x0001FFFF)
+  #define MCHBAR_CH1_CR_CMD_RATE_spare_DEF                             (0x00000000)
+  #define MCHBAR_CH1_CR_CMD_RATE_init_mrw_2n_cs_OFF                    (31)
+  #define MCHBAR_CH1_CR_CMD_RATE_init_mrw_2n_cs_WID                    ( 1)
+  #define MCHBAR_CH1_CR_CMD_RATE_init_mrw_2n_cs_MSK                    (0x80000000)
+  #define MCHBAR_CH1_CR_CMD_RATE_init_mrw_2n_cs_MAX                    (0x00000001)
+  #define MCHBAR_CH1_CR_CMD_RATE_init_mrw_2n_cs_DEF                    (0x00000000)
+
+#define MCHBAR_CH1_CR_TC_BANK_RANK_D_REG                             (0x00004414)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_D_tCL_OFF                         ( 0)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_D_tCL_WID                         ( 5)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_D_tCL_MSK                         (0x0000001F)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_D_tCL_MAX                         (0x0000001F)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_D_tCL_DEF                         (0x00000006)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_D_tWCL_OFF                        ( 5)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_D_tWCL_WID                        ( 5)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_D_tWCL_MSK                        (0x000003E0)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_D_tWCL_MAX                        (0x0000001F)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_D_tWCL_DEF                        (0x00000006)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_D_tCPDED_OFF                      (10)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_D_tCPDED_WID                      ( 2)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_D_tCPDED_MSK                      (0x00000C00)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_D_tCPDED_MAX                      (0x00000003)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_D_tCPDED_DEF                      (0x00000001)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_D_tPRPDEN_OFF                     (12)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_D_tPRPDEN_WID                     ( 2)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_D_tPRPDEN_MSK                     (0x00003000)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_D_tPRPDEN_MAX                     (0x00000003)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_D_tPRPDEN_DEF                     (0x00000001)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_D_Odt_Read_Delay_OFF              (14)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_D_Odt_Read_Delay_WID              ( 3)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_D_Odt_Read_Delay_MSK              (0x0001C000)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_D_Odt_Read_Delay_MAX              (0x00000007)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_D_Odt_Read_Delay_DEF              (0x00000000)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_D_Odt_Read_Duration_OFF           (17)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_D_Odt_Read_Duration_WID           ( 2)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_D_Odt_Read_Duration_MSK           (0x00060000)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_D_Odt_Read_Duration_MAX           (0x00000003)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_D_Odt_Read_Duration_DEF           (0x00000000)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_D_Odt_Write_Duration_OFF          (19)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_D_Odt_Write_Duration_WID          ( 2)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_D_Odt_Write_Duration_MSK          (0x00180000)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_D_Odt_Write_Duration_MAX          (0x00000003)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_D_Odt_Write_Duration_DEF          (0x00000000)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_D_Odt_Write_Duration_Ult_OFF      (19)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_D_Odt_Write_Duration_Ult_WID      ( 3)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_D_Odt_Write_Duration_Ult_MSK      (0x00380000)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_D_Odt_Write_Duration_Ult_MAX      (0x00000007)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_D_Odt_Write_Duration_Ult_DEF      (0x00000000)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_D_Odt_Write_Delay_Ult_OFF         (22)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_D_Odt_Write_Delay_Ult_WID         ( 3)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_D_Odt_Write_Delay_Ult_MSK         (0x01C00000)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_D_Odt_Write_Delay_Ult_MAX         (0x00000007)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_D_Odt_Write_Delay_Ult_DEF         (0x00000000)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_D_Odt_Always_Rank0_Ult_OFF        (25)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_D_Odt_Always_Rank0_Ult_WID        ( 1)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_D_Odt_Always_Rank0_Ult_MSK        (0x02000000)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_D_Odt_Always_Rank0_Ult_MAX        (0x00000001)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_D_Odt_Always_Rank0_Ult_DEF        (0x00000000)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_D_cmd_delay_Ult_OFF               (26)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_D_cmd_delay_Ult_WID               ( 2)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_D_cmd_delay_Ult_MSK               (0x0C000000)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_D_cmd_delay_Ult_MAX               (0x00000003)
+  #define MCHBAR_CH1_CR_TC_BANK_RANK_D_cmd_delay_Ult_DEF               (0x00000000)
+
+#define MCHBAR_CH1_CR_SCHED_CBIT_REG                                 (0x00004420)
+  #define MCHBAR_CH1_CR_SCHED_CBIT_dis_opp_cas_OFF                     ( 0)
+  #define MCHBAR_CH1_CR_SCHED_CBIT_dis_opp_cas_WID                     ( 1)
+  #define MCHBAR_CH1_CR_SCHED_CBIT_dis_opp_cas_MSK                     (0x00000001)
+  #define MCHBAR_CH1_CR_SCHED_CBIT_dis_opp_cas_MAX                     (0x00000001)
+  #define MCHBAR_CH1_CR_SCHED_CBIT_dis_opp_cas_DEF                     (0x00000001)
+  #define MCHBAR_CH1_CR_SCHED_CBIT_dis_opp_is_cas_OFF                  ( 1)
+  #define MCHBAR_CH1_CR_SCHED_CBIT_dis_opp_is_cas_WID                  ( 1)
+  #define MCHBAR_CH1_CR_SCHED_CBIT_dis_opp_is_cas_MSK                  (0x00000002)
+  #define MCHBAR_CH1_CR_SCHED_CBIT_dis_opp_is_cas_MAX                  (0x00000001)
+  #define MCHBAR_CH1_CR_SCHED_CBIT_dis_opp_is_cas_DEF                  (0x00000000)
+  #define MCHBAR_CH1_CR_SCHED_CBIT_dis_opp_ras_OFF                     ( 2)
+  #define MCHBAR_CH1_CR_SCHED_CBIT_dis_opp_ras_WID                     ( 1)
+  #define MCHBAR_CH1_CR_SCHED_CBIT_dis_opp_ras_MSK                     (0x00000004)
+  #define MCHBAR_CH1_CR_SCHED_CBIT_dis_opp_ras_MAX                     (0x00000001)
+  #define MCHBAR_CH1_CR_SCHED_CBIT_dis_opp_ras_DEF                     (0x00000001)
+  #define MCHBAR_CH1_CR_SCHED_CBIT_dis_opp_is_ras_OFF                  ( 3)
+  #define MCHBAR_CH1_CR_SCHED_CBIT_dis_opp_is_ras_WID                  ( 1)
+  #define MCHBAR_CH1_CR_SCHED_CBIT_dis_opp_is_ras_MSK                  (0x00000008)
+  #define MCHBAR_CH1_CR_SCHED_CBIT_dis_opp_is_ras_MAX                  (0x00000001)
+  #define MCHBAR_CH1_CR_SCHED_CBIT_dis_opp_is_ras_DEF                  (0x00000000)
+  #define MCHBAR_CH1_CR_SCHED_CBIT_dis_1c_byp_OFF                      ( 4)
+  #define MCHBAR_CH1_CR_SCHED_CBIT_dis_1c_byp_WID                      ( 1)
+  #define MCHBAR_CH1_CR_SCHED_CBIT_dis_1c_byp_MSK                      (0x00000010)
+  #define MCHBAR_CH1_CR_SCHED_CBIT_dis_1c_byp_MAX                      (0x00000001)
+  #define MCHBAR_CH1_CR_SCHED_CBIT_dis_1c_byp_DEF                      (0x00000001)
+  #define MCHBAR_CH1_CR_SCHED_CBIT_dis_2c_byp_OFF                      ( 5)
+  #define MCHBAR_CH1_CR_SCHED_CBIT_dis_2c_byp_WID                      ( 1)
+  #define MCHBAR_CH1_CR_SCHED_CBIT_dis_2c_byp_MSK                      (0x00000020)
+  #define MCHBAR_CH1_CR_SCHED_CBIT_dis_2c_byp_MAX                      (0x00000001)
+  #define MCHBAR_CH1_CR_SCHED_CBIT_dis_2c_byp_DEF                      (0x00000000)
+  #define MCHBAR_CH1_CR_SCHED_CBIT_dis_deprd_opt_OFF                   ( 6)
+  #define MCHBAR_CH1_CR_SCHED_CBIT_dis_deprd_opt_WID                   ( 1)
+  #define MCHBAR_CH1_CR_SCHED_CBIT_dis_deprd_opt_MSK                   (0x00000040)
+  #define MCHBAR_CH1_CR_SCHED_CBIT_dis_deprd_opt_MAX                   (0x00000001)
+  #define MCHBAR_CH1_CR_SCHED_CBIT_dis_deprd_opt_DEF                   (0x00000000)
+  #define MCHBAR_CH1_CR_SCHED_CBIT_dis_pt_it_OFF                       ( 7)
+  #define MCHBAR_CH1_CR_SCHED_CBIT_dis_pt_it_WID                       ( 1)
+  #define MCHBAR_CH1_CR_SCHED_CBIT_dis_pt_it_MSK                       (0x00000080)
+  #define MCHBAR_CH1_CR_SCHED_CBIT_dis_pt_it_MAX                       (0x00000001)
+  #define MCHBAR_CH1_CR_SCHED_CBIT_dis_pt_it_DEF                       (0x00000000)
+  #define MCHBAR_CH1_CR_SCHED_CBIT_dis_prcnt_ring_OFF                  ( 8)
+  #define MCHBAR_CH1_CR_SCHED_CBIT_dis_prcnt_ring_WID                  ( 1)
+  #define MCHBAR_CH1_CR_SCHED_CBIT_dis_prcnt_ring_MSK                  (0x00000100)
+  #define MCHBAR_CH1_CR_SCHED_CBIT_dis_prcnt_ring_MAX                  (0x00000001)
+  #define MCHBAR_CH1_CR_SCHED_CBIT_dis_prcnt_ring_DEF                  (0x00000000)
+  #define MCHBAR_CH1_CR_SCHED_CBIT_dis_prcnt_sa_OFF                    ( 9)
+  #define MCHBAR_CH1_CR_SCHED_CBIT_dis_prcnt_sa_WID                    ( 1)
+  #define MCHBAR_CH1_CR_SCHED_CBIT_dis_prcnt_sa_MSK                    (0x00000200)
+  #define MCHBAR_CH1_CR_SCHED_CBIT_dis_prcnt_sa_MAX                    (0x00000001)
+  #define MCHBAR_CH1_CR_SCHED_CBIT_dis_prcnt_sa_DEF                    (0x00000000)
+  #define MCHBAR_CH1_CR_SCHED_CBIT_dis_blkr_ph_OFF                     (10)
+  #define MCHBAR_CH1_CR_SCHED_CBIT_dis_blkr_ph_WID                     ( 1)
+  #define MCHBAR_CH1_CR_SCHED_CBIT_dis_blkr_ph_MSK                     (0x00000400)
+  #define MCHBAR_CH1_CR_SCHED_CBIT_dis_blkr_ph_MAX                     (0x00000001)
+  #define MCHBAR_CH1_CR_SCHED_CBIT_dis_blkr_ph_DEF                     (0x00000000)
+  #define MCHBAR_CH1_CR_SCHED_CBIT_dis_blkr_pe_OFF                     (11)
+  #define MCHBAR_CH1_CR_SCHED_CBIT_dis_blkr_pe_WID                     ( 1)
+  #define MCHBAR_CH1_CR_SCHED_CBIT_dis_blkr_pe_MSK                     (0x00000800)
+  #define MCHBAR_CH1_CR_SCHED_CBIT_dis_blkr_pe_MAX                     (0x00000001)
+  #define MCHBAR_CH1_CR_SCHED_CBIT_dis_blkr_pe_DEF                     (0x00000000)
+  #define MCHBAR_CH1_CR_SCHED_CBIT_dis_blkr_pm_OFF                     (12)
+  #define MCHBAR_CH1_CR_SCHED_CBIT_dis_blkr_pm_WID                     ( 1)
+  #define MCHBAR_CH1_CR_SCHED_CBIT_dis_blkr_pm_MSK                     (0x00001000)
+  #define MCHBAR_CH1_CR_SCHED_CBIT_dis_blkr_pm_MAX                     (0x00000001)
+  #define MCHBAR_CH1_CR_SCHED_CBIT_dis_blkr_pm_DEF                     (0x00000000)
+  #define MCHBAR_CH1_CR_SCHED_CBIT_dis_odt_OFF                         (13)
+  #define MCHBAR_CH1_CR_SCHED_CBIT_dis_odt_WID                         ( 1)
+  #define MCHBAR_CH1_CR_SCHED_CBIT_dis_odt_MSK                         (0x00002000)
+  #define MCHBAR_CH1_CR_SCHED_CBIT_dis_odt_MAX                         (0x00000001)
+  #define MCHBAR_CH1_CR_SCHED_CBIT_dis_odt_DEF                         (0x00000000)
+  #define MCHBAR_CH1_CR_SCHED_CBIT_OE_alw_off_OFF                      (14)
+  #define MCHBAR_CH1_CR_SCHED_CBIT_OE_alw_off_WID                      ( 1)
+  #define MCHBAR_CH1_CR_SCHED_CBIT_OE_alw_off_MSK                      (0x00004000)
+  #define MCHBAR_CH1_CR_SCHED_CBIT_OE_alw_off_MAX                      (0x00000001)
+  #define MCHBAR_CH1_CR_SCHED_CBIT_OE_alw_off_DEF                      (0x00000000)
+  #define MCHBAR_CH1_CR_SCHED_CBIT_dis_aom_OFF                         (16)
+  #define MCHBAR_CH1_CR_SCHED_CBIT_dis_aom_WID                         ( 1)
+  #define MCHBAR_CH1_CR_SCHED_CBIT_dis_aom_MSK                         (0x00010000)
+  #define MCHBAR_CH1_CR_SCHED_CBIT_dis_aom_MAX                         (0x00000001)
+  #define MCHBAR_CH1_CR_SCHED_CBIT_dis_aom_DEF                         (0x00000000)
+  #define MCHBAR_CH1_CR_SCHED_CBIT_block_rpq_OFF                       (17)
+  #define MCHBAR_CH1_CR_SCHED_CBIT_block_rpq_WID                       ( 1)
+  #define MCHBAR_CH1_CR_SCHED_CBIT_block_rpq_MSK                       (0x00020000)
+  #define MCHBAR_CH1_CR_SCHED_CBIT_block_rpq_MAX                       (0x00000001)
+  #define MCHBAR_CH1_CR_SCHED_CBIT_block_rpq_DEF                       (0x00000000)
+  #define MCHBAR_CH1_CR_SCHED_CBIT_block_wpq_OFF                       (18)
+  #define MCHBAR_CH1_CR_SCHED_CBIT_block_wpq_WID                       ( 1)
+  #define MCHBAR_CH1_CR_SCHED_CBIT_block_wpq_MSK                       (0x00040000)
+  #define MCHBAR_CH1_CR_SCHED_CBIT_block_wpq_MAX                       (0x00000001)
+  #define MCHBAR_CH1_CR_SCHED_CBIT_block_wpq_DEF                       (0x00000000)
+  #define MCHBAR_CH1_CR_SCHED_CBIT_invert_align_OFF                    (19)
+  #define MCHBAR_CH1_CR_SCHED_CBIT_invert_align_WID                    ( 1)
+  #define MCHBAR_CH1_CR_SCHED_CBIT_invert_align_MSK                    (0x00080000)
+  #define MCHBAR_CH1_CR_SCHED_CBIT_invert_align_MAX                    (0x00000001)
+  #define MCHBAR_CH1_CR_SCHED_CBIT_invert_align_DEF                    (0x00000000)
+  #define MCHBAR_CH1_CR_SCHED_CBIT_dis_write_gap_OFF                   (20)
+  #define MCHBAR_CH1_CR_SCHED_CBIT_dis_write_gap_WID                   ( 1)
+  #define MCHBAR_CH1_CR_SCHED_CBIT_dis_write_gap_MSK                   (0x00100000)
+  #define MCHBAR_CH1_CR_SCHED_CBIT_dis_write_gap_MAX                   (0x00000001)
+  #define MCHBAR_CH1_CR_SCHED_CBIT_dis_write_gap_DEF                   (0x00000001)
+  #define MCHBAR_CH1_CR_SCHED_CBIT_dis_zq_OFF                          (21)
+  #define MCHBAR_CH1_CR_SCHED_CBIT_dis_zq_WID                          ( 1)
+  #define MCHBAR_CH1_CR_SCHED_CBIT_dis_zq_MSK                          (0x00200000)
+  #define MCHBAR_CH1_CR_SCHED_CBIT_dis_zq_MAX                          (0x00000001)
+  #define MCHBAR_CH1_CR_SCHED_CBIT_dis_zq_DEF                          (0x00000000)
+  #define MCHBAR_CH1_CR_SCHED_CBIT_dis_tt_OFF                          (22)
+  #define MCHBAR_CH1_CR_SCHED_CBIT_dis_tt_WID                          ( 1)
+  #define MCHBAR_CH1_CR_SCHED_CBIT_dis_tt_MSK                          (0x00400000)
+  #define MCHBAR_CH1_CR_SCHED_CBIT_dis_tt_MAX                          (0x00000001)
+  #define MCHBAR_CH1_CR_SCHED_CBIT_dis_tt_DEF                          (0x00000000)
+  #define MCHBAR_CH1_CR_SCHED_CBIT_dis_opp_ref_OFF                     (23)
+  #define MCHBAR_CH1_CR_SCHED_CBIT_dis_opp_ref_WID                     ( 1)
+  #define MCHBAR_CH1_CR_SCHED_CBIT_dis_opp_ref_MSK                     (0x00800000)
+  #define MCHBAR_CH1_CR_SCHED_CBIT_dis_opp_ref_MAX                     (0x00000001)
+  #define MCHBAR_CH1_CR_SCHED_CBIT_dis_opp_ref_DEF                     (0x00000000)
+  #define MCHBAR_CH1_CR_SCHED_CBIT_Long_ZQ_OFF                         (24)
+  #define MCHBAR_CH1_CR_SCHED_CBIT_Long_ZQ_WID                         ( 1)
+  #define MCHBAR_CH1_CR_SCHED_CBIT_Long_ZQ_MSK                         (0x01000000)
+  #define MCHBAR_CH1_CR_SCHED_CBIT_Long_ZQ_MAX                         (0x00000001)
+  #define MCHBAR_CH1_CR_SCHED_CBIT_Long_ZQ_DEF                         (0x00000000)
+  #define MCHBAR_CH1_CR_SCHED_CBIT_dis_srx_zq_OFF                      (25)
+  #define MCHBAR_CH1_CR_SCHED_CBIT_dis_srx_zq_WID                      ( 1)
+  #define MCHBAR_CH1_CR_SCHED_CBIT_dis_srx_zq_MSK                      (0x02000000)
+  #define MCHBAR_CH1_CR_SCHED_CBIT_dis_srx_zq_MAX                      (0x00000001)
+  #define MCHBAR_CH1_CR_SCHED_CBIT_dis_srx_zq_DEF                      (0x00000000)
+  #define MCHBAR_CH1_CR_SCHED_CBIT_Serialize_ZQ_OFF                    (26)
+  #define MCHBAR_CH1_CR_SCHED_CBIT_Serialize_ZQ_WID                    ( 1)
+  #define MCHBAR_CH1_CR_SCHED_CBIT_Serialize_ZQ_MSK                    (0x04000000)
+  #define MCHBAR_CH1_CR_SCHED_CBIT_Serialize_ZQ_MAX                    (0x00000001)
+  #define MCHBAR_CH1_CR_SCHED_CBIT_Serialize_ZQ_DEF                    (0x00000000)
+  #define MCHBAR_CH1_CR_SCHED_CBIT_ZQ_fast_exec_OFF                    (27)
+  #define MCHBAR_CH1_CR_SCHED_CBIT_ZQ_fast_exec_WID                    ( 1)
+  #define MCHBAR_CH1_CR_SCHED_CBIT_ZQ_fast_exec_MSK                    (0x08000000)
+  #define MCHBAR_CH1_CR_SCHED_CBIT_ZQ_fast_exec_MAX                    (0x00000001)
+  #define MCHBAR_CH1_CR_SCHED_CBIT_ZQ_fast_exec_DEF                    (0x00000000)
+  #define MCHBAR_CH1_CR_SCHED_CBIT_Dis_DriveNop_OFF                    (28)
+  #define MCHBAR_CH1_CR_SCHED_CBIT_Dis_DriveNop_WID                    ( 1)
+  #define MCHBAR_CH1_CR_SCHED_CBIT_Dis_DriveNop_MSK                    (0x10000000)
+  #define MCHBAR_CH1_CR_SCHED_CBIT_Dis_DriveNop_MAX                    (0x00000001)
+  #define MCHBAR_CH1_CR_SCHED_CBIT_Dis_DriveNop_DEF                    (0x00000000)
+  #define MCHBAR_CH1_CR_SCHED_CBIT_Pres_WDB_Ent_OFF                    (29)
+  #define MCHBAR_CH1_CR_SCHED_CBIT_Pres_WDB_Ent_WID                    ( 1)
+  #define MCHBAR_CH1_CR_SCHED_CBIT_Pres_WDB_Ent_MSK                    (0x20000000)
+  #define MCHBAR_CH1_CR_SCHED_CBIT_Pres_WDB_Ent_MAX                    (0x00000001)
+  #define MCHBAR_CH1_CR_SCHED_CBIT_Pres_WDB_Ent_DEF                    (0x00000000)
+  #define MCHBAR_CH1_CR_SCHED_CBIT_dis_clk_gate_OFF                    (30)
+  #define MCHBAR_CH1_CR_SCHED_CBIT_dis_clk_gate_WID                    ( 1)
+  #define MCHBAR_CH1_CR_SCHED_CBIT_dis_clk_gate_MSK                    (0x40000000)
+  #define MCHBAR_CH1_CR_SCHED_CBIT_dis_clk_gate_MAX                    (0x00000001)
+  #define MCHBAR_CH1_CR_SCHED_CBIT_dis_clk_gate_DEF                    (0x00000000)
+
+#define MCHBAR_CH1_CR_SC_ROUNDT_LAT_REG                              (0x00004424)
+  #define MCHBAR_CH1_CR_SC_ROUNDT_LAT_Lat_R0D0_OFF                     ( 0)
+  #define MCHBAR_CH1_CR_SC_ROUNDT_LAT_Lat_R0D0_WID                     ( 6)
+  #define MCHBAR_CH1_CR_SC_ROUNDT_LAT_Lat_R0D0_MSK                     (0x0000003F)
+  #define MCHBAR_CH1_CR_SC_ROUNDT_LAT_Lat_R0D0_MAX                     (0x0000003F)
+  #define MCHBAR_CH1_CR_SC_ROUNDT_LAT_Lat_R0D0_DEF                     (0x00000020)
+  #define MCHBAR_CH1_CR_SC_ROUNDT_LAT_Lat_R1D0_OFF                     ( 8)
+  #define MCHBAR_CH1_CR_SC_ROUNDT_LAT_Lat_R1D0_WID                     ( 6)
+  #define MCHBAR_CH1_CR_SC_ROUNDT_LAT_Lat_R1D0_MSK                     (0x00003F00)
+  #define MCHBAR_CH1_CR_SC_ROUNDT_LAT_Lat_R1D0_MAX                     (0x0000003F)
+  #define MCHBAR_CH1_CR_SC_ROUNDT_LAT_Lat_R1D0_DEF                     (0x00000020)
+  #define MCHBAR_CH1_CR_SC_ROUNDT_LAT_Lat_R0D1_OFF                     (16)
+  #define MCHBAR_CH1_CR_SC_ROUNDT_LAT_Lat_R0D1_WID                     ( 6)
+  #define MCHBAR_CH1_CR_SC_ROUNDT_LAT_Lat_R0D1_MSK                     (0x003F0000)
+  #define MCHBAR_CH1_CR_SC_ROUNDT_LAT_Lat_R0D1_MAX                     (0x0000003F)
+  #define MCHBAR_CH1_CR_SC_ROUNDT_LAT_Lat_R0D1_DEF                     (0x00000020)
+  #define MCHBAR_CH1_CR_SC_ROUNDT_LAT_Lat_R1D1_OFF                     (24)
+  #define MCHBAR_CH1_CR_SC_ROUNDT_LAT_Lat_R1D1_WID                     ( 6)
+  #define MCHBAR_CH1_CR_SC_ROUNDT_LAT_Lat_R1D1_MSK                     (0x3F000000)
+  #define MCHBAR_CH1_CR_SC_ROUNDT_LAT_Lat_R1D1_MAX                     (0x0000003F)
+  #define MCHBAR_CH1_CR_SC_ROUNDT_LAT_Lat_R1D1_DEF                     (0x00000020)
+
+#define MCHBAR_CH1_CR_SC_IO_LATENCY_REG                              (0x00004428)
+  #define MCHBAR_CH1_CR_SC_IO_LATENCY_IOLAT_R0D0_OFF                   ( 0)
+  #define MCHBAR_CH1_CR_SC_IO_LATENCY_IOLAT_R0D0_WID                   ( 4)
+  #define MCHBAR_CH1_CR_SC_IO_LATENCY_IOLAT_R0D0_MSK                   (0x0000000F)
+  #define MCHBAR_CH1_CR_SC_IO_LATENCY_IOLAT_R0D0_MAX                   (0x0000000F)
+  #define MCHBAR_CH1_CR_SC_IO_LATENCY_IOLAT_R0D0_DEF                   (0x00000000)
+  #define MCHBAR_CH1_CR_SC_IO_LATENCY_IOLAT_R1D0_OFF                   ( 4)
+  #define MCHBAR_CH1_CR_SC_IO_LATENCY_IOLAT_R1D0_WID                   ( 4)
+  #define MCHBAR_CH1_CR_SC_IO_LATENCY_IOLAT_R1D0_MSK                   (0x000000F0)
+  #define MCHBAR_CH1_CR_SC_IO_LATENCY_IOLAT_R1D0_MAX                   (0x0000000F)
+  #define MCHBAR_CH1_CR_SC_IO_LATENCY_IOLAT_R1D0_DEF                   (0x00000000)
+  #define MCHBAR_CH1_CR_SC_IO_LATENCY_IOLAT_R0D1_OFF                   ( 8)
+  #define MCHBAR_CH1_CR_SC_IO_LATENCY_IOLAT_R0D1_WID                   ( 4)
+  #define MCHBAR_CH1_CR_SC_IO_LATENCY_IOLAT_R0D1_MSK                   (0x00000F00)
+  #define MCHBAR_CH1_CR_SC_IO_LATENCY_IOLAT_R0D1_MAX                   (0x0000000F)
+  #define MCHBAR_CH1_CR_SC_IO_LATENCY_IOLAT_R0D1_DEF                   (0x00000000)
+  #define MCHBAR_CH1_CR_SC_IO_LATENCY_IOLAT_R1D1_OFF                   (12)
+  #define MCHBAR_CH1_CR_SC_IO_LATENCY_IOLAT_R1D1_WID                   ( 4)
+  #define MCHBAR_CH1_CR_SC_IO_LATENCY_IOLAT_R1D1_MSK                   (0x0000F000)
+  #define MCHBAR_CH1_CR_SC_IO_LATENCY_IOLAT_R1D1_MAX                   (0x0000000F)
+  #define MCHBAR_CH1_CR_SC_IO_LATENCY_IOLAT_R1D1_DEF                   (0x00000000)
+  #define MCHBAR_CH1_CR_SC_IO_LATENCY_RT_IOCOMP_OFF                    (16)
+  #define MCHBAR_CH1_CR_SC_IO_LATENCY_RT_IOCOMP_WID                    ( 6)
+  #define MCHBAR_CH1_CR_SC_IO_LATENCY_RT_IOCOMP_MSK                    (0x003F0000)
+  #define MCHBAR_CH1_CR_SC_IO_LATENCY_RT_IOCOMP_MAX                    (0x0000003F)
+  #define MCHBAR_CH1_CR_SC_IO_LATENCY_RT_IOCOMP_DEF                    (0x0000000E)
+  #define MCHBAR_CH1_CR_SC_IO_LATENCY_three_channels_OFF               (30)
+  #define MCHBAR_CH1_CR_SC_IO_LATENCY_three_channels_WID               ( 1)
+  #define MCHBAR_CH1_CR_SC_IO_LATENCY_three_channels_MSK               (0x40000000)
+  #define MCHBAR_CH1_CR_SC_IO_LATENCY_three_channels_MAX               (0x00000001)
+  #define MCHBAR_CH1_CR_SC_IO_LATENCY_three_channels_DEF               (0x00000000)
+  #define MCHBAR_CH1_CR_SC_IO_LATENCY_DIS_RT_CLK_GATE_OFF              (31)
+  #define MCHBAR_CH1_CR_SC_IO_LATENCY_DIS_RT_CLK_GATE_WID              ( 1)
+  #define MCHBAR_CH1_CR_SC_IO_LATENCY_DIS_RT_CLK_GATE_MSK              (0x80000000)
+  #define MCHBAR_CH1_CR_SC_IO_LATENCY_DIS_RT_CLK_GATE_MAX              (0x00000001)
+  #define MCHBAR_CH1_CR_SC_IO_LATENCY_DIS_RT_CLK_GATE_DEF              (0x00000000)
+
+#define MCHBAR_CH1_CR_ROUND_TRIP_DFT_DATA_REG                        (0x0000442C)
+  #define MCHBAR_CH1_CR_ROUND_TRIP_DFT_DATA_DATA_OFF                   ( 0)
+  #define MCHBAR_CH1_CR_ROUND_TRIP_DFT_DATA_DATA_WID                   (32)
+  #define MCHBAR_CH1_CR_ROUND_TRIP_DFT_DATA_DATA_MSK                   (0xFFFFFFFF)
+  #define MCHBAR_CH1_CR_ROUND_TRIP_DFT_DATA_DATA_MAX                   (0xFFFFFFFF)
+  #define MCHBAR_CH1_CR_ROUND_TRIP_DFT_DATA_DATA_DEF                   (0x00000000)
+
+#define MCHBAR_CH1_CR_DFT_MISC_REG                                   (0x00004430)
+  #define MCHBAR_CH1_CR_DFT_MISC_WDAR_OFF                              ( 0)
+  #define MCHBAR_CH1_CR_DFT_MISC_WDAR_WID                              ( 1)
+  #define MCHBAR_CH1_CR_DFT_MISC_WDAR_MSK                              (0x00000001)
+  #define MCHBAR_CH1_CR_DFT_MISC_WDAR_MAX                              (0x00000001)
+  #define MCHBAR_CH1_CR_DFT_MISC_WDAR_DEF                              (0x00000000)
+  #define MCHBAR_CH1_CR_DFT_MISC_safe_mask_sel_OFF                     ( 1)
+  #define MCHBAR_CH1_CR_DFT_MISC_safe_mask_sel_WID                     ( 3)
+  #define MCHBAR_CH1_CR_DFT_MISC_safe_mask_sel_MSK                     (0x0000000E)
+  #define MCHBAR_CH1_CR_DFT_MISC_safe_mask_sel_MAX                     (0x00000007)
+  #define MCHBAR_CH1_CR_DFT_MISC_safe_mask_sel_DEF                     (0x00000000)
+  #define MCHBAR_CH1_CR_DFT_MISC_force_rcv_en_OFF                      ( 4)
+  #define MCHBAR_CH1_CR_DFT_MISC_force_rcv_en_WID                      ( 1)
+  #define MCHBAR_CH1_CR_DFT_MISC_force_rcv_en_MSK                      (0x00000010)
+  #define MCHBAR_CH1_CR_DFT_MISC_force_rcv_en_MAX                      (0x00000001)
+  #define MCHBAR_CH1_CR_DFT_MISC_force_rcv_en_DEF                      (0x00000000)
+  #define MCHBAR_CH1_CR_DFT_MISC_DDR_QUAL_OFF                          ( 8)
+  #define MCHBAR_CH1_CR_DFT_MISC_DDR_QUAL_WID                          ( 2)
+  #define MCHBAR_CH1_CR_DFT_MISC_DDR_QUAL_MSK                          (0x00000300)
+  #define MCHBAR_CH1_CR_DFT_MISC_DDR_QUAL_MAX                          (0x00000003)
+  #define MCHBAR_CH1_CR_DFT_MISC_DDR_QUAL_DEF                          (0x00000000)
+  #define MCHBAR_CH1_CR_DFT_MISC_Qual_length_OFF                       (10)
+  #define MCHBAR_CH1_CR_DFT_MISC_Qual_length_WID                       ( 2)
+  #define MCHBAR_CH1_CR_DFT_MISC_Qual_length_MSK                       (0x00000C00)
+  #define MCHBAR_CH1_CR_DFT_MISC_Qual_length_MAX                       (0x00000003)
+  #define MCHBAR_CH1_CR_DFT_MISC_Qual_length_DEF                       (0x00000000)
+  #define MCHBAR_CH1_CR_DFT_MISC_WDB_Block_En_OFF                      (12)
+  #define MCHBAR_CH1_CR_DFT_MISC_WDB_Block_En_WID                      ( 1)
+  #define MCHBAR_CH1_CR_DFT_MISC_WDB_Block_En_MSK                      (0x00001000)
+  #define MCHBAR_CH1_CR_DFT_MISC_WDB_Block_En_MAX                      (0x00000001)
+  #define MCHBAR_CH1_CR_DFT_MISC_WDB_Block_En_DEF                      (0x00000000)
+  #define MCHBAR_CH1_CR_DFT_MISC_RT_DFT_READ_PTR_OFF                   (13)
+  #define MCHBAR_CH1_CR_DFT_MISC_RT_DFT_READ_PTR_WID                   ( 4)
+  #define MCHBAR_CH1_CR_DFT_MISC_RT_DFT_READ_PTR_MSK                   (0x0001E000)
+  #define MCHBAR_CH1_CR_DFT_MISC_RT_DFT_READ_PTR_MAX                   (0x0000000F)
+  #define MCHBAR_CH1_CR_DFT_MISC_RT_DFT_READ_PTR_DEF                   (0x00000000)
+  #define MCHBAR_CH1_CR_DFT_MISC_RT_DFT_READ_ENABLE_OFF                (17)
+  #define MCHBAR_CH1_CR_DFT_MISC_RT_DFT_READ_ENABLE_WID                ( 1)
+  #define MCHBAR_CH1_CR_DFT_MISC_RT_DFT_READ_ENABLE_MSK                (0x00020000)
+  #define MCHBAR_CH1_CR_DFT_MISC_RT_DFT_READ_ENABLE_MAX                (0x00000001)
+  #define MCHBAR_CH1_CR_DFT_MISC_RT_DFT_READ_ENABLE_DEF                (0x00000000)
+  #define MCHBAR_CH1_CR_DFT_MISC_RT_DFT_READ_SEL_ADDR_OFF              (18)
+  #define MCHBAR_CH1_CR_DFT_MISC_RT_DFT_READ_SEL_ADDR_WID              ( 1)
+  #define MCHBAR_CH1_CR_DFT_MISC_RT_DFT_READ_SEL_ADDR_MSK              (0x00040000)
+  #define MCHBAR_CH1_CR_DFT_MISC_RT_DFT_READ_SEL_ADDR_MAX              (0x00000001)
+  #define MCHBAR_CH1_CR_DFT_MISC_RT_DFT_READ_SEL_ADDR_DEF              (0x00000000)
+
+#define MCHBAR_CH1_CR_READ_RETURN_DFT_REG                            (0x00004434)
+  #define MCHBAR_CH1_CR_READ_RETURN_DFT_ECC_OFF                        ( 0)
+  #define MCHBAR_CH1_CR_READ_RETURN_DFT_ECC_WID                        ( 8)
+  #define MCHBAR_CH1_CR_READ_RETURN_DFT_ECC_MSK                        (0x000000FF)
+  #define MCHBAR_CH1_CR_READ_RETURN_DFT_ECC_MAX                        (0x000000FF)
+  #define MCHBAR_CH1_CR_READ_RETURN_DFT_ECC_DEF                        (0x00000000)
+  #define MCHBAR_CH1_CR_READ_RETURN_DFT_RRD_DFT_Mode_OFF               ( 8)
+  #define MCHBAR_CH1_CR_READ_RETURN_DFT_RRD_DFT_Mode_WID               ( 2)
+  #define MCHBAR_CH1_CR_READ_RETURN_DFT_RRD_DFT_Mode_MSK               (0x00000300)
+  #define MCHBAR_CH1_CR_READ_RETURN_DFT_RRD_DFT_Mode_MAX               (0x00000003)
+  #define MCHBAR_CH1_CR_READ_RETURN_DFT_RRD_DFT_Mode_DEF               (0x00000000)
+  #define MCHBAR_CH1_CR_READ_RETURN_DFT_LFSR_Seed_Index_OFF            (10)
+  #define MCHBAR_CH1_CR_READ_RETURN_DFT_LFSR_Seed_Index_WID            ( 5)
+  #define MCHBAR_CH1_CR_READ_RETURN_DFT_LFSR_Seed_Index_MSK            (0x00007C00)
+  #define MCHBAR_CH1_CR_READ_RETURN_DFT_LFSR_Seed_Index_MAX            (0x0000001F)
+  #define MCHBAR_CH1_CR_READ_RETURN_DFT_LFSR_Seed_Index_DEF            (0x00000000)
+  #define MCHBAR_CH1_CR_READ_RETURN_DFT_Inversion_Mode_OFF             (15)
+  #define MCHBAR_CH1_CR_READ_RETURN_DFT_Inversion_Mode_WID             ( 1)
+  #define MCHBAR_CH1_CR_READ_RETURN_DFT_Inversion_Mode_MSK             (0x00008000)
+  #define MCHBAR_CH1_CR_READ_RETURN_DFT_Inversion_Mode_MAX             (0x00000001)
+  #define MCHBAR_CH1_CR_READ_RETURN_DFT_Inversion_Mode_DEF             (0x00000000)
+
+#define MCHBAR_CH1_CR_SCHED_SECOND_CBIT_REG                          (0x00004438)
+  #define MCHBAR_CH1_CR_SCHED_SECOND_CBIT_dis_imph_error_OFF           ( 0)
+  #define MCHBAR_CH1_CR_SCHED_SECOND_CBIT_dis_imph_error_WID           ( 1)
+  #define MCHBAR_CH1_CR_SCHED_SECOND_CBIT_dis_imph_error_MSK           (0x00000001)
+  #define MCHBAR_CH1_CR_SCHED_SECOND_CBIT_dis_imph_error_MAX           (0x00000001)
+  #define MCHBAR_CH1_CR_SCHED_SECOND_CBIT_dis_imph_error_DEF           (0x00000000)
+  #define MCHBAR_CH1_CR_SCHED_SECOND_CBIT_dis_async_odt_OFF            ( 8)
+  #define MCHBAR_CH1_CR_SCHED_SECOND_CBIT_dis_async_odt_WID            ( 1)
+  #define MCHBAR_CH1_CR_SCHED_SECOND_CBIT_dis_async_odt_MSK            (0x00000100)
+  #define MCHBAR_CH1_CR_SCHED_SECOND_CBIT_dis_async_odt_MAX            (0x00000001)
+  #define MCHBAR_CH1_CR_SCHED_SECOND_CBIT_dis_async_odt_DEF            (0x00000000)
+
+#define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_REG                 (0x00004440)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Mux0_Control_OFF    ( 0)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Mux0_Control_WID    ( 2)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Mux0_Control_MSK    (0x00000003)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Mux0_Control_MAX    (0x00000003)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Mux0_Control_DEF    (0x00000001)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Mux1_Control_OFF    ( 3)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Mux1_Control_WID    ( 2)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Mux1_Control_MSK    (0x00000018)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Mux1_Control_MAX    (0x00000003)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Mux1_Control_DEF    (0x00000001)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Mux2_Control_OFF    ( 6)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Mux2_Control_WID    ( 2)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Mux2_Control_MSK    (0x000000C0)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Mux2_Control_MAX    (0x00000003)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Mux2_Control_DEF    (0x00000001)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_ECC_Replace_Byte_Control_OFF (14)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_ECC_Replace_Byte_Control_WID ( 1)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_ECC_Replace_Byte_Control_MSK (0x00004000)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_ECC_Replace_Byte_Control_MAX (0x00000001)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_ECC_Replace_Byte_Control_DEF (0x00000001)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_ECC_Data_Source_Sel_OFF (15)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_ECC_Data_Source_Sel_WID ( 1)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_ECC_Data_Source_Sel_MSK (0x00008000)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_ECC_Data_Source_Sel_MAX (0x00000001)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_ECC_Data_Source_Sel_DEF (0x00000001)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Save_LFSR_Seed_Rate_OFF (16)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Save_LFSR_Seed_Rate_WID ( 6)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Save_LFSR_Seed_Rate_MSK (0x003F0000)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Save_LFSR_Seed_Rate_MAX (0x0000003F)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Save_LFSR_Seed_Rate_DEF (0x00000000)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Reload_LFSR_Seed_Rate_OFF (24)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Reload_LFSR_Seed_Rate_WID ( 3)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Reload_LFSR_Seed_Rate_MSK (0x07000000)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Reload_LFSR_Seed_Rate_MAX (0x00000007)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Reload_LFSR_Seed_Rate_DEF (0x00000000)
+
+#define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_RD_STATUS_REG               (0x00004444)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_RD_STATUS_WDB_Current_Read_Pointer_OFF ( 0)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_RD_STATUS_WDB_Current_Read_Pointer_WID ( 6)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_RD_STATUS_WDB_Current_Read_Pointer_MSK (0x0000003F)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_RD_STATUS_WDB_Current_Read_Pointer_MAX (0x0000003F)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_RD_STATUS_WDB_Current_Read_Pointer_DEF (0x00000000)
+
+#define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_0_REG             (0x00004448)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_0_Pattern_Buffer_OFF ( 0)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_0_Pattern_Buffer_WID (24)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_0_Pattern_Buffer_MSK (0x00FFFFFF)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_0_Pattern_Buffer_MAX (0x00FFFFFF)
+
+#define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_1_REG             (0x0000444C)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_1_Pattern_Buffer_OFF ( 0)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_1_Pattern_Buffer_WID (24)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_1_Pattern_Buffer_MSK (0x00FFFFFF)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_1_Pattern_Buffer_MAX (0x00FFFFFF)
+
+#define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_2_REG             (0x00004450)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_2_Pattern_Buffer_OFF ( 0)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_2_Pattern_Buffer_WID (24)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_2_Pattern_Buffer_MSK (0x00FFFFFF)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_2_Pattern_Buffer_MAX (0x00FFFFFF)
+
+#define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_0_REG             (0x00004454)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_0_Pattern_Buffer_OFF ( 0)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_0_Pattern_Buffer_WID (24)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_0_Pattern_Buffer_MSK (0x00FFFFFF)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_0_Pattern_Buffer_MAX (0x00FFFFFF)
+
+#define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_1_REG             (0x00004458)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_1_Pattern_Buffer_OFF ( 0)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_1_Pattern_Buffer_WID (24)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_1_Pattern_Buffer_MSK (0x00FFFFFF)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_1_Pattern_Buffer_MAX (0x00FFFFFF)
+
+#define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_2_REG             (0x0000445C)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_2_Pattern_Buffer_OFF ( 0)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_2_Pattern_Buffer_WID (24)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_2_Pattern_Buffer_MSK (0x00FFFFFF)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_2_Pattern_Buffer_MAX (0x00FFFFFF)
+
+#define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_0_REG      (0x00004460)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_0_Pattern_Buffer_OFF ( 0)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_0_Pattern_Buffer_WID (24)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_0_Pattern_Buffer_MSK (0x00FFFFFF)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_0_Pattern_Buffer_MAX (0x00FFFFFF)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_0_Pattern_Buffer_DEF (0x00000000)
+
+#define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_1_REG      (0x00004464)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_1_Pattern_Buffer_OFF ( 0)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_1_Pattern_Buffer_WID (24)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_1_Pattern_Buffer_MSK (0x00FFFFFF)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_1_Pattern_Buffer_MAX (0x00FFFFFF)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_1_Pattern_Buffer_DEF (0x00000000)
+
+#define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_2_REG      (0x00004468)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_2_Pattern_Buffer_OFF ( 0)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_2_Pattern_Buffer_WID (24)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_2_Pattern_Buffer_MSK (0x00FFFFFF)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_2_Pattern_Buffer_MAX (0x00FFFFFF)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_2_Pattern_Buffer_DEF (0x00000000)
+
+#define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_0_REG      (0x0000446C)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_0_Pattern_Buffer_OFF ( 0)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_0_Pattern_Buffer_WID (24)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_0_Pattern_Buffer_MSK (0x00FFFFFF)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_0_Pattern_Buffer_MAX (0x00FFFFFF)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_0_Pattern_Buffer_DEF (0x00000000)
+
+#define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_1_REG      (0x00004470)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_1_Pattern_Buffer_OFF ( 0)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_1_Pattern_Buffer_WID (24)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_1_Pattern_Buffer_MSK (0x00FFFFFF)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_1_Pattern_Buffer_MAX (0x00FFFFFF)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_1_Pattern_Buffer_DEF (0x00000000)
+
+#define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_2_REG      (0x00004474)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_2_Pattern_Buffer_OFF ( 0)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_2_Pattern_Buffer_WID (24)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_2_Pattern_Buffer_MSK (0x00FFFFFF)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_2_Pattern_Buffer_MAX (0x00FFFFFF)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_2_Pattern_Buffer_DEF (0x00000000)
+
+#define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_REG                 (0x00004478)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_L_data_select_OFF   ( 0)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_L_data_select_WID   ( 1)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_L_data_select_MSK   (0x00000001)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_L_data_select_MAX   (0x00000001)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_L_data_select_DEF   (0x00000000)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_Enable_Sweep_Frequency_OFF ( 1)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_Enable_Sweep_Frequency_WID ( 1)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_Enable_Sweep_Frequency_MSK (0x00000002)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_Enable_Sweep_Frequency_MAX (0x00000001)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_Enable_Sweep_Frequency_DEF (0x00000000)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_L_counter_OFF       ( 8)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_L_counter_WID       ( 8)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_L_counter_MSK       (0x0000FF00)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_L_counter_MAX       (0x000000FF)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_L_counter_DEF       (0x00000001)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_M_counter_OFF       (16)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_M_counter_WID       ( 8)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_M_counter_MSK       (0x00FF0000)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_M_counter_MAX       (0x000000FF)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_M_counter_DEF       (0x00000001)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_N_counter_OFF       (24)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_N_counter_WID       ( 8)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_N_counter_MSK       (0xFF000000)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_N_counter_MAX       (0x000000FF)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_N_counter_DEF       (0x00000001)
+
+#define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_INV_REG                        (0x00004484)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_INV_ECC_Inv_or_DC_Enable_OFF   ( 0)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_INV_ECC_Inv_or_DC_Enable_WID   ( 8)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_INV_ECC_Inv_or_DC_Enable_MSK   (0x000000FF)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_INV_ECC_Inv_or_DC_Enable_MAX   (0x000000FF)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_INV_ECC_Inv_or_DC_Enable_DEF   (0x00000000)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_INV_Inv_or_DC_Shift_Rate_OFF   (16)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_INV_Inv_or_DC_Shift_Rate_WID   ( 4)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_INV_Inv_or_DC_Shift_Rate_MSK   (0x000F0000)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_INV_Inv_or_DC_Shift_Rate_MAX   (0x0000000F)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_INV_Inv_or_DC_Shift_Rate_DEF   (0x00000000)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_INV_DC_Polarity_Control_OFF    (20)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_INV_DC_Polarity_Control_WID    ( 1)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_INV_DC_Polarity_Control_MSK    (0x00100000)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_INV_DC_Polarity_Control_MAX    (0x00000001)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_INV_DC_Polarity_Control_DEF    (0x00000000)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_INV_Inv_or_DC_Control_OFF      (30)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_INV_Inv_or_DC_Control_WID      ( 1)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_INV_Inv_or_DC_Control_MSK      (0x40000000)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_INV_Inv_or_DC_Control_MAX      (0x00000001)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_INV_Inv_or_DC_Control_DEF      (0x00000000)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_INV_Inv_or_DC_Shift_Enable_OFF (31)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_INV_Inv_or_DC_Shift_Enable_WID ( 1)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_INV_Inv_or_DC_Shift_Enable_MSK (0x80000000)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_INV_Inv_or_DC_Shift_Enable_MAX (0x00000001)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_INV_Inv_or_DC_Shift_Enable_DEF (0x00000000)
+
+#define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_DATA_INV_REG                   (0x00004490)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_DATA_INV_Data_Inv_or_DC_Enable_OFF ( 0)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_DATA_INV_Data_Inv_or_DC_Enable_WID (64)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_DATA_INV_Data_Inv_or_DC_Enable_MSK (0xFFFFFFFFFFFFFFFF)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_DATA_INV_Data_Inv_or_DC_Enable_MAX (0xFFFFFFFFFFFFFFFF)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_DATA_INV_Data_Inv_or_DC_Enable_DEF (0x00000000)
+
+#define MCHBAR_CH1_CR_REUT_CH_ERR_CTL_REG                            (0x00004498)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_CTL_Stop_on_Nth_Error_OFF          ( 0)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_CTL_Stop_on_Nth_Error_WID          ( 6)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_CTL_Stop_on_Nth_Error_MSK          (0x0000003F)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_CTL_Stop_on_Nth_Error_MAX          (0x0000003F)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_CTL_Stop_on_Nth_Error_DEF          (0x00000001)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_CTL_Stop_On_Error_Control_OFF      (12)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_CTL_Stop_On_Error_Control_WID      ( 2)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_CTL_Stop_On_Error_Control_MSK      (0x00003000)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_CTL_Stop_On_Error_Control_MAX      (0x00000003)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_CTL_Stop_On_Error_Control_DEF      (0x00000000)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_CTL_Selective_Error_Enable_Chunk_OFF (16)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_CTL_Selective_Error_Enable_Chunk_WID ( 8)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_CTL_Selective_Error_Enable_Chunk_MSK (0x00FF0000)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_CTL_Selective_Error_Enable_Chunk_MAX (0x000000FF)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_CTL_Selective_Error_Enable_Chunk_DEF (0x000000FF)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_CTL_Selective_Error_Enable_Cacheline_OFF (24)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_CTL_Selective_Error_Enable_Cacheline_WID ( 8)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_CTL_Selective_Error_Enable_Cacheline_MSK (0xFF000000)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_CTL_Selective_Error_Enable_Cacheline_MAX (0x000000FF)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_CTL_Selective_Error_Enable_Cacheline_DEF (0x000000FF)
+
+#define MCHBAR_CH1_CR_REUT_CH_ERR_ECC_MASK_REG                       (0x0000449C)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_ECC_MASK_ECC_Error_Mask_OFF        ( 0)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_ECC_MASK_ECC_Error_Mask_WID        ( 8)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_ECC_MASK_ECC_Error_Mask_MSK        (0x000000FF)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_ECC_MASK_ECC_Error_Mask_MAX        (0x000000FF)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_ECC_MASK_ECC_Error_Mask_DEF        (0x00000000)
+
+#define MCHBAR_CH1_CR_STM_CONFIG_REG                                 (0x000044A4)
+  #define MCHBAR_CH1_CR_STM_CONFIG_Stretch_mode_OFF                    ( 0)
+  #define MCHBAR_CH1_CR_STM_CONFIG_Stretch_mode_WID                    ( 2)
+  #define MCHBAR_CH1_CR_STM_CONFIG_Stretch_mode_MSK                    (0x00000003)
+  #define MCHBAR_CH1_CR_STM_CONFIG_Stretch_mode_MAX                    (0x00000003)
+  #define MCHBAR_CH1_CR_STM_CONFIG_Stretch_mode_DEF                    (0x00000000)
+  #define MCHBAR_CH1_CR_STM_CONFIG_STF_OFF                             ( 4)
+  #define MCHBAR_CH1_CR_STM_CONFIG_STF_WID                             ( 3)
+  #define MCHBAR_CH1_CR_STM_CONFIG_STF_MSK                             (0x00000070)
+  #define MCHBAR_CH1_CR_STM_CONFIG_STF_MAX                             (0x00000007)
+  #define MCHBAR_CH1_CR_STM_CONFIG_STF_DEF                             (0x00000000)
+
+#define MCHBAR_CH1_CR_SC_PR_CNT_CONFIG_REG                           (0x000044A8)
+  #define MCHBAR_CH1_CR_SC_PR_CNT_CONFIG_Priority_count_ring_OFF       ( 0)
+  #define MCHBAR_CH1_CR_SC_PR_CNT_CONFIG_Priority_count_ring_WID       (10)
+  #define MCHBAR_CH1_CR_SC_PR_CNT_CONFIG_Priority_count_ring_MSK       (0x000003FF)
+  #define MCHBAR_CH1_CR_SC_PR_CNT_CONFIG_Priority_count_ring_MAX       (0x000003FF)
+  #define MCHBAR_CH1_CR_SC_PR_CNT_CONFIG_Priority_count_ring_DEF       (0x00000040)
+  #define MCHBAR_CH1_CR_SC_PR_CNT_CONFIG_Priority_count_SA_OFF         (16)
+  #define MCHBAR_CH1_CR_SC_PR_CNT_CONFIG_Priority_count_SA_WID         (10)
+  #define MCHBAR_CH1_CR_SC_PR_CNT_CONFIG_Priority_count_SA_MSK         (0x03FF0000)
+  #define MCHBAR_CH1_CR_SC_PR_CNT_CONFIG_Priority_count_SA_MAX         (0x000003FF)
+  #define MCHBAR_CH1_CR_SC_PR_CNT_CONFIG_Priority_count_SA_DEF         (0x00000100)
+
+#define MCHBAR_CH1_CR_SC_PCIT_REG                                    (0x000044AC)
+  #define MCHBAR_CH1_CR_SC_PCIT_PCIT_OFF                               ( 0)
+  #define MCHBAR_CH1_CR_SC_PCIT_PCIT_WID                               ( 8)
+  #define MCHBAR_CH1_CR_SC_PCIT_PCIT_MSK                               (0x000000FF)
+  #define MCHBAR_CH1_CR_SC_PCIT_PCIT_MAX                               (0x000000FF)
+  #define MCHBAR_CH1_CR_SC_PCIT_PCIT_DEF                               (0x00000040)
+
+#define MCHBAR_CH1_CR_PM_PDWN_CONFIG_REG                             (0x000044B0)
+  #define MCHBAR_CH1_CR_PM_PDWN_CONFIG_PDWN_idle_counter_OFF           ( 0)
+  #define MCHBAR_CH1_CR_PM_PDWN_CONFIG_PDWN_idle_counter_WID           (12)
+  #define MCHBAR_CH1_CR_PM_PDWN_CONFIG_PDWN_idle_counter_MSK           (0x00000FFF)
+  #define MCHBAR_CH1_CR_PM_PDWN_CONFIG_PDWN_idle_counter_MAX           (0x00000FFF)
+  #define MCHBAR_CH1_CR_PM_PDWN_CONFIG_PDWN_idle_counter_DEF           (0x00000000)
+  #define MCHBAR_CH1_CR_PM_PDWN_CONFIG_PDWN_mode_OFF                   (12)
+  #define MCHBAR_CH1_CR_PM_PDWN_CONFIG_PDWN_mode_WID                   ( 4)
+  #define MCHBAR_CH1_CR_PM_PDWN_CONFIG_PDWN_mode_MSK                   (0x0000F000)
+  #define MCHBAR_CH1_CR_PM_PDWN_CONFIG_PDWN_mode_MAX                   (0x0000000F)
+  #define MCHBAR_CH1_CR_PM_PDWN_CONFIG_PDWN_mode_DEF                   (0x00000000)
+
+#define MCHBAR_CH1_CR_ECC_INJECT_COUNT_REG                           (0x000044B4)
+  #define MCHBAR_CH1_CR_ECC_INJECT_COUNT_Count_OFF                     ( 0)
+  #define MCHBAR_CH1_CR_ECC_INJECT_COUNT_Count_WID                     (32)
+  #define MCHBAR_CH1_CR_ECC_INJECT_COUNT_Count_MSK                     (0xFFFFFFFF)
+  #define MCHBAR_CH1_CR_ECC_INJECT_COUNT_Count_MAX                     (0xFFFFFFFF)
+  #define MCHBAR_CH1_CR_ECC_INJECT_COUNT_Count_DEF                     (0xFFFFFFFF)
+
+#define MCHBAR_CH1_CR_ECC_DFT_REG                                    (0x000044B8)
+  #define MCHBAR_CH1_CR_ECC_DFT_ECC4ANA_fill_OFF                       ( 0)
+  #define MCHBAR_CH1_CR_ECC_DFT_ECC4ANA_fill_WID                       ( 8)
+  #define MCHBAR_CH1_CR_ECC_DFT_ECC4ANA_fill_MSK                       (0x000000FF)
+  #define MCHBAR_CH1_CR_ECC_DFT_ECC4ANA_fill_MAX                       (0x000000FF)
+  #define MCHBAR_CH1_CR_ECC_DFT_ECC4ANA_fill_DEF                       (0x00000000)
+  #define MCHBAR_CH1_CR_ECC_DFT_ECC4ANA_trigger_OFF                    ( 8)
+  #define MCHBAR_CH1_CR_ECC_DFT_ECC4ANA_trigger_WID                    ( 2)
+  #define MCHBAR_CH1_CR_ECC_DFT_ECC4ANA_trigger_MSK                    (0x00000300)
+  #define MCHBAR_CH1_CR_ECC_DFT_ECC4ANA_trigger_MAX                    (0x00000003)
+  #define MCHBAR_CH1_CR_ECC_DFT_ECC4ANA_trigger_DEF                    (0x00000000)
+  #define MCHBAR_CH1_CR_ECC_DFT_ECC4ANA_BS_OFF                         (10)
+  #define MCHBAR_CH1_CR_ECC_DFT_ECC4ANA_BS_WID                         ( 1)
+  #define MCHBAR_CH1_CR_ECC_DFT_ECC4ANA_BS_MSK                         (0x00000400)
+  #define MCHBAR_CH1_CR_ECC_DFT_ECC4ANA_BS_MAX                         (0x00000001)
+  #define MCHBAR_CH1_CR_ECC_DFT_ECC4ANA_BS_DEF                         (0x00000000)
+  #define MCHBAR_CH1_CR_ECC_DFT_ECC_Inject_OFF                         (11)
+  #define MCHBAR_CH1_CR_ECC_DFT_ECC_Inject_WID                         ( 3)
+  #define MCHBAR_CH1_CR_ECC_DFT_ECC_Inject_MSK                         (0x00003800)
+  #define MCHBAR_CH1_CR_ECC_DFT_ECC_Inject_MAX                         (0x00000007)
+  #define MCHBAR_CH1_CR_ECC_DFT_ECC_Inject_DEF                         (0x00000000)
+  #define MCHBAR_CH1_CR_ECC_DFT_ECC_correction_disable_OFF             (14)
+  #define MCHBAR_CH1_CR_ECC_DFT_ECC_correction_disable_WID             ( 1)
+  #define MCHBAR_CH1_CR_ECC_DFT_ECC_correction_disable_MSK             (0x00004000)
+  #define MCHBAR_CH1_CR_ECC_DFT_ECC_correction_disable_MAX             (0x00000001)
+  #define MCHBAR_CH1_CR_ECC_DFT_ECC_correction_disable_DEF             (0x00000000)
+  #define MCHBAR_CH1_CR_ECC_DFT_ECC4ANA_Inject_OFF                     (15)
+  #define MCHBAR_CH1_CR_ECC_DFT_ECC4ANA_Inject_WID                     ( 1)
+  #define MCHBAR_CH1_CR_ECC_DFT_ECC4ANA_Inject_MSK                     (0x00008000)
+  #define MCHBAR_CH1_CR_ECC_DFT_ECC4ANA_Inject_MAX                     (0x00000001)
+  #define MCHBAR_CH1_CR_ECC_DFT_ECC4ANA_Inject_DEF                     (0x00000000)
+  #define MCHBAR_CH1_CR_ECC_DFT_DIS_MCA_LOG_OFF                        (16)
+  #define MCHBAR_CH1_CR_ECC_DFT_DIS_MCA_LOG_WID                        ( 1)
+  #define MCHBAR_CH1_CR_ECC_DFT_DIS_MCA_LOG_MSK                        (0x00010000)
+  #define MCHBAR_CH1_CR_ECC_DFT_DIS_MCA_LOG_MAX                        (0x00000001)
+  #define MCHBAR_CH1_CR_ECC_DFT_DIS_MCA_LOG_DEF                        (0x00000000)
+  #define MCHBAR_CH1_CR_ECC_DFT_DIS_PCH_EVENT_OFF                      (17)
+  #define MCHBAR_CH1_CR_ECC_DFT_DIS_PCH_EVENT_WID                      ( 1)
+  #define MCHBAR_CH1_CR_ECC_DFT_DIS_PCH_EVENT_MSK                      (0x00020000)
+  #define MCHBAR_CH1_CR_ECC_DFT_DIS_PCH_EVENT_MAX                      (0x00000001)
+  #define MCHBAR_CH1_CR_ECC_DFT_DIS_PCH_EVENT_DEF                      (0x00000000)
+  #define MCHBAR_CH1_CR_ECC_DFT_DIS_PCIE_POISON_OFF                    (18)
+  #define MCHBAR_CH1_CR_ECC_DFT_DIS_PCIE_POISON_WID                    ( 1)
+  #define MCHBAR_CH1_CR_ECC_DFT_DIS_PCIE_POISON_MSK                    (0x00040000)
+  #define MCHBAR_CH1_CR_ECC_DFT_DIS_PCIE_POISON_MAX                    (0x00000001)
+  #define MCHBAR_CH1_CR_ECC_DFT_DIS_PCIE_POISON_DEF                    (0x00000000)
+
+#define MCHBAR_CH1_CR_VISA_CTL_MCSCHEDS_REG                          (0x000044C0)
+  #define MCHBAR_CH1_CR_VISA_CTL_MCSCHEDS_Data_OFF                     ( 0)
+  #define MCHBAR_CH1_CR_VISA_CTL_MCSCHEDS_Data_WID                     (18)
+  #define MCHBAR_CH1_CR_VISA_CTL_MCSCHEDS_Data_MSK                     (0x0003FFFF)
+  #define MCHBAR_CH1_CR_VISA_CTL_MCSCHEDS_Data_MAX                     (0x0003FFFF)
+  #define MCHBAR_CH1_CR_VISA_CTL_MCSCHEDS_Data_DEF                     (0x00000000)
+  #define MCHBAR_CH1_CR_VISA_CTL_MCSCHEDS_VORANGE_OFF                  (31)
+  #define MCHBAR_CH1_CR_VISA_CTL_MCSCHEDS_VORANGE_WID                  ( 1)
+  #define MCHBAR_CH1_CR_VISA_CTL_MCSCHEDS_VORANGE_MSK                  (0x80000000)
+  #define MCHBAR_CH1_CR_VISA_CTL_MCSCHEDS_VORANGE_MAX                  (0x00000001)
+  #define MCHBAR_CH1_CR_VISA_CTL_MCSCHEDS_VORANGE_DEF                  (0x00000000)
+
+#define MCHBAR_CH1_CR_VISA_XBAR_MCSCHEDS_REG                         (0x000044C4)
+  #define MCHBAR_CH1_CR_VISA_XBAR_MCSCHEDS_Data_OFF                    ( 0)
+  #define MCHBAR_CH1_CR_VISA_XBAR_MCSCHEDS_Data_WID                    (32)
+  #define MCHBAR_CH1_CR_VISA_XBAR_MCSCHEDS_Data_MSK                    (0xFFFFFFFF)
+  #define MCHBAR_CH1_CR_VISA_XBAR_MCSCHEDS_Data_MAX                    (0xFFFFFFFF)
+  #define MCHBAR_CH1_CR_VISA_XBAR_MCSCHEDS_Data_DEF                    (0x76543210)
+
+#define MCHBAR_CH1_CR_ECCERRLOG0_REG                                 (0x000044C8)
+  #define MCHBAR_CH1_CR_ECCERRLOG0_CERRSTS_OFF                         ( 0)
+  #define MCHBAR_CH1_CR_ECCERRLOG0_CERRSTS_WID                         ( 1)
+  #define MCHBAR_CH1_CR_ECCERRLOG0_CERRSTS_MSK                         (0x00000001)
+  #define MCHBAR_CH1_CR_ECCERRLOG0_CERRSTS_MAX                         (0x00000001)
+  #define MCHBAR_CH1_CR_ECCERRLOG0_CERRSTS_DEF                         (0x00000000)
+  #define MCHBAR_CH1_CR_ECCERRLOG0_MERRSTS_OFF                         ( 1)
+  #define MCHBAR_CH1_CR_ECCERRLOG0_MERRSTS_WID                         ( 1)
+  #define MCHBAR_CH1_CR_ECCERRLOG0_MERRSTS_MSK                         (0x00000002)
+  #define MCHBAR_CH1_CR_ECCERRLOG0_MERRSTS_MAX                         (0x00000001)
+  #define MCHBAR_CH1_CR_ECCERRLOG0_MERRSTS_DEF                         (0x00000000)
+  #define MCHBAR_CH1_CR_ECCERRLOG0_ERRSYND_OFF                         (16)
+  #define MCHBAR_CH1_CR_ECCERRLOG0_ERRSYND_WID                         ( 8)
+  #define MCHBAR_CH1_CR_ECCERRLOG0_ERRSYND_MSK                         (0x00FF0000)
+  #define MCHBAR_CH1_CR_ECCERRLOG0_ERRSYND_MAX                         (0x000000FF)
+  #define MCHBAR_CH1_CR_ECCERRLOG0_ERRSYND_DEF                         (0x00000000)
+  #define MCHBAR_CH1_CR_ECCERRLOG0_ERRCHUNK_OFF                        (24)
+  #define MCHBAR_CH1_CR_ECCERRLOG0_ERRCHUNK_WID                        ( 3)
+  #define MCHBAR_CH1_CR_ECCERRLOG0_ERRCHUNK_MSK                        (0x07000000)
+  #define MCHBAR_CH1_CR_ECCERRLOG0_ERRCHUNK_MAX                        (0x00000007)
+  #define MCHBAR_CH1_CR_ECCERRLOG0_ERRCHUNK_DEF                        (0x00000000)
+  #define MCHBAR_CH1_CR_ECCERRLOG0_ERRRANK_OFF                         (27)
+  #define MCHBAR_CH1_CR_ECCERRLOG0_ERRRANK_WID                         ( 2)
+  #define MCHBAR_CH1_CR_ECCERRLOG0_ERRRANK_MSK                         (0x18000000)
+  #define MCHBAR_CH1_CR_ECCERRLOG0_ERRRANK_MAX                         (0x00000003)
+  #define MCHBAR_CH1_CR_ECCERRLOG0_ERRRANK_DEF                         (0x00000000)
+  #define MCHBAR_CH1_CR_ECCERRLOG0_ERRBANK_OFF                         (29)
+  #define MCHBAR_CH1_CR_ECCERRLOG0_ERRBANK_WID                         ( 3)
+  #define MCHBAR_CH1_CR_ECCERRLOG0_ERRBANK_MSK                         (0xE0000000)
+  #define MCHBAR_CH1_CR_ECCERRLOG0_ERRBANK_MAX                         (0x00000007)
+  #define MCHBAR_CH1_CR_ECCERRLOG0_ERRBANK_DEF                         (0x00000000)
+
+#define MCHBAR_CH1_CR_ECCERRLOG1_REG                                 (0x000044CC)
+  #define MCHBAR_CH1_CR_ECCERRLOG1_ERRROW_OFF                          ( 0)
+  #define MCHBAR_CH1_CR_ECCERRLOG1_ERRROW_WID                          (16)
+  #define MCHBAR_CH1_CR_ECCERRLOG1_ERRROW_MSK                          (0x0000FFFF)
+  #define MCHBAR_CH1_CR_ECCERRLOG1_ERRROW_MAX                          (0x0000FFFF)
+  #define MCHBAR_CH1_CR_ECCERRLOG1_ERRROW_DEF                          (0x00000000)
+  #define MCHBAR_CH1_CR_ECCERRLOG1_ERRCOL_OFF                          (16)
+  #define MCHBAR_CH1_CR_ECCERRLOG1_ERRCOL_WID                          (16)
+  #define MCHBAR_CH1_CR_ECCERRLOG1_ERRCOL_MSK                          (0xFFFF0000)
+  #define MCHBAR_CH1_CR_ECCERRLOG1_ERRCOL_MAX                          (0x0000FFFF)
+  #define MCHBAR_CH1_CR_ECCERRLOG1_ERRCOL_DEF                          (0x00000000)
+
+#define MCHBAR_CH1_CR_SC_WR_ADD_DELAY_REG                            (0x000044D0)
+  #define MCHBAR_CH1_CR_SC_WR_ADD_DELAY_D0R0_OFF                       ( 0)
+  #define MCHBAR_CH1_CR_SC_WR_ADD_DELAY_D0R0_WID                       ( 2)
+  #define MCHBAR_CH1_CR_SC_WR_ADD_DELAY_D0R0_MSK                       (0x00000003)
+  #define MCHBAR_CH1_CR_SC_WR_ADD_DELAY_D0R0_MAX                       (0x00000003)
+  #define MCHBAR_CH1_CR_SC_WR_ADD_DELAY_D0R0_DEF                       (0x00000000)
+  #define MCHBAR_CH1_CR_SC_WR_ADD_DELAY_D0R1_OFF                       ( 2)
+  #define MCHBAR_CH1_CR_SC_WR_ADD_DELAY_D0R1_WID                       ( 2)
+  #define MCHBAR_CH1_CR_SC_WR_ADD_DELAY_D0R1_MSK                       (0x0000000C)
+  #define MCHBAR_CH1_CR_SC_WR_ADD_DELAY_D0R1_MAX                       (0x00000003)
+  #define MCHBAR_CH1_CR_SC_WR_ADD_DELAY_D0R1_DEF                       (0x00000000)
+  #define MCHBAR_CH1_CR_SC_WR_ADD_DELAY_D1R0_OFF                       ( 4)
+  #define MCHBAR_CH1_CR_SC_WR_ADD_DELAY_D1R0_WID                       ( 2)
+  #define MCHBAR_CH1_CR_SC_WR_ADD_DELAY_D1R0_MSK                       (0x00000030)
+  #define MCHBAR_CH1_CR_SC_WR_ADD_DELAY_D1R0_MAX                       (0x00000003)
+  #define MCHBAR_CH1_CR_SC_WR_ADD_DELAY_D1R0_DEF                       (0x00000000)
+  #define MCHBAR_CH1_CR_SC_WR_ADD_DELAY_D1R1_OFF                       ( 6)
+  #define MCHBAR_CH1_CR_SC_WR_ADD_DELAY_D1R1_WID                       ( 2)
+  #define MCHBAR_CH1_CR_SC_WR_ADD_DELAY_D1R1_MSK                       (0x000000C0)
+  #define MCHBAR_CH1_CR_SC_WR_ADD_DELAY_D1R1_MAX                       (0x00000003)
+  #define MCHBAR_CH1_CR_SC_WR_ADD_DELAY_D1R1_DEF                       (0x00000000)
+
+#define MCHBAR_CH1_CR_WMM_READ_CONFIG_REG                            (0x000044D4)
+  #define MCHBAR_CH1_CR_WMM_READ_CONFIG_Dis_Opp_rd_OFF                 ( 0)
+  #define MCHBAR_CH1_CR_WMM_READ_CONFIG_Dis_Opp_rd_WID                 ( 1)
+  #define MCHBAR_CH1_CR_WMM_READ_CONFIG_Dis_Opp_rd_MSK                 (0x00000001)
+  #define MCHBAR_CH1_CR_WMM_READ_CONFIG_Dis_Opp_rd_MAX                 (0x00000001)
+  #define MCHBAR_CH1_CR_WMM_READ_CONFIG_Dis_Opp_rd_DEF                 (0x00000000)
+  #define MCHBAR_CH1_CR_WMM_READ_CONFIG_ACT_Enable_OFF                 ( 1)
+  #define MCHBAR_CH1_CR_WMM_READ_CONFIG_ACT_Enable_WID                 ( 1)
+  #define MCHBAR_CH1_CR_WMM_READ_CONFIG_ACT_Enable_MSK                 (0x00000002)
+  #define MCHBAR_CH1_CR_WMM_READ_CONFIG_ACT_Enable_MAX                 (0x00000001)
+  #define MCHBAR_CH1_CR_WMM_READ_CONFIG_ACT_Enable_DEF                 (0x00000001)
+  #define MCHBAR_CH1_CR_WMM_READ_CONFIG_PRE_Enable_OFF                 ( 2)
+  #define MCHBAR_CH1_CR_WMM_READ_CONFIG_PRE_Enable_WID                 ( 1)
+  #define MCHBAR_CH1_CR_WMM_READ_CONFIG_PRE_Enable_MSK                 (0x00000004)
+  #define MCHBAR_CH1_CR_WMM_READ_CONFIG_PRE_Enable_MAX                 (0x00000001)
+  #define MCHBAR_CH1_CR_WMM_READ_CONFIG_PRE_Enable_DEF                 (0x00000001)
+  #define MCHBAR_CH1_CR_WMM_READ_CONFIG_MAX_RPQ_Cas_OFF                ( 3)
+  #define MCHBAR_CH1_CR_WMM_READ_CONFIG_MAX_RPQ_Cas_WID                ( 4)
+  #define MCHBAR_CH1_CR_WMM_READ_CONFIG_MAX_RPQ_Cas_MSK                (0x00000078)
+  #define MCHBAR_CH1_CR_WMM_READ_CONFIG_MAX_RPQ_Cas_MAX                (0x0000000F)
+  #define MCHBAR_CH1_CR_WMM_READ_CONFIG_MAX_RPQ_Cas_DEF                (0x00000008)
+
+#define MCHBAR_CH1_CR_REUT_CH_ERR_DATA_MASK_REG                      (0x000044D8)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_DATA_MASK_Data_Error_Mask_OFF      ( 0)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_DATA_MASK_Data_Error_Mask_WID      (64)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_DATA_MASK_Data_Error_Mask_MSK      (0xFFFFFFFFFFFFFFFF)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_DATA_MASK_Data_Error_Mask_MAX      (0xFFFFFFFFFFFFFFFF)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_DATA_MASK_Data_Error_Mask_DEF      (0x00000000)
+
+#define MCHBAR_CH1_CR_REUT_CH_ERR_DATA_STATUS_REG                    (0x000044E0)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_DATA_STATUS_Data_Error_Status_OFF  ( 0)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_DATA_STATUS_Data_Error_Status_WID  (64)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_DATA_STATUS_Data_Error_Status_MSK  (0xFFFFFFFFFFFFFFFF)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_DATA_STATUS_Data_Error_Status_MAX  (0xFFFFFFFFFFFFFFFF)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_DATA_STATUS_Data_Error_Status_DEF  (0x00000000)
+
+#define MCHBAR_CH1_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_REG (0x000044E8)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_ECC_Error_Status_OFF ( 0)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_ECC_Error_Status_WID ( 8)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_ECC_Error_Status_MSK (0x000000FF)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_ECC_Error_Status_MAX (0x000000FF)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_ECC_Error_Status_DEF (0x00000000)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Chunk_Error_Status_OFF ( 8)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Chunk_Error_Status_WID ( 8)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Chunk_Error_Status_MSK (0x0000FF00)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Chunk_Error_Status_MAX (0x000000FF)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Chunk_Error_Status_DEF (0x00000000)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Rank_Error_Status_OFF (16)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Rank_Error_Status_WID ( 4)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Rank_Error_Status_MSK (0x000F0000)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Rank_Error_Status_MAX (0x0000000F)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Rank_Error_Status_DEF (0x00000000)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Byte_Group_Error_Status_OFF (32)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Byte_Group_Error_Status_WID ( 9)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Byte_Group_Error_Status_MSK (0x1FF00000000)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Byte_Group_Error_Status_MAX (0x000001FF)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Byte_Group_Error_Status_DEF (0x00000000)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_WDB_Rd_Chunk_Num_Status_OFF (52)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_WDB_Rd_Chunk_Num_Status_WID ( 3)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_WDB_Rd_Chunk_Num_Status_MSK (0x70000000000000)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_WDB_Rd_Chunk_Num_Status_MAX (0x00000007)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_WDB_Rd_Chunk_Num_Status_DEF (0x00000000)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Nth_Error_OFF (56)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Nth_Error_WID ( 6)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Nth_Error_MSK (0x3F00000000000000)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Nth_Error_MAX (0x0000003F)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Nth_Error_DEF (0x00000000)
+
+#define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_0_REG                  (0x000044F0)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_0_Counter_Pointer_OFF  ( 0)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_0_Counter_Pointer_WID  ( 7)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_0_Counter_Pointer_MSK  (0x0000007F)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_0_Counter_Pointer_MAX  (0x0000007F)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_0_Counter_Pointer_DEF  (0x0000007F)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_0_Counter_Control_OFF  ( 7)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_0_Counter_Control_WID  ( 2)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_0_Counter_Control_MSK  (0x00000180)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_0_Counter_Control_MAX  (0x00000003)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_0_Counter_Control_DEF  (0x00000000)
+
+#define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_1_REG                  (0x000044F4)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_1_Counter_Pointer_OFF  ( 0)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_1_Counter_Pointer_WID  ( 7)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_1_Counter_Pointer_MSK  (0x0000007F)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_1_Counter_Pointer_MAX  (0x0000007F)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_1_Counter_Pointer_DEF  (0x0000007F)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_1_Counter_Control_OFF  ( 7)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_1_Counter_Control_WID  ( 2)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_1_Counter_Control_MSK  (0x00000180)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_1_Counter_Control_MAX  (0x00000003)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_1_Counter_Control_DEF  (0x00000000)
+
+#define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_2_REG                  (0x000044F8)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_2_Counter_Pointer_OFF  ( 0)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_2_Counter_Pointer_WID  ( 7)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_2_Counter_Pointer_MSK  (0x0000007F)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_2_Counter_Pointer_MAX  (0x0000007F)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_2_Counter_Pointer_DEF  (0x0000007F)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_2_Counter_Control_OFF  ( 7)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_2_Counter_Control_WID  ( 2)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_2_Counter_Control_MSK  (0x00000180)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_2_Counter_Control_MAX  (0x00000003)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_2_Counter_Control_DEF  (0x00000000)
+
+#define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_3_REG                  (0x000044FC)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_3_Counter_Pointer_OFF  ( 0)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_3_Counter_Pointer_WID  ( 7)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_3_Counter_Pointer_MSK  (0x0000007F)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_3_Counter_Pointer_MAX  (0x0000007F)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_3_Counter_Pointer_DEF  (0x0000007F)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_3_Counter_Control_OFF  ( 7)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_3_Counter_Control_WID  ( 2)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_3_Counter_Control_MSK  (0x00000180)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_3_Counter_Control_MAX  (0x00000003)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_3_Counter_Control_DEF  (0x00000000)
+
+#define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_4_REG                  (0x00004500)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_4_Counter_Pointer_OFF  ( 0)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_4_Counter_Pointer_WID  ( 7)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_4_Counter_Pointer_MSK  (0x0000007F)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_4_Counter_Pointer_MAX  (0x0000007F)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_4_Counter_Pointer_DEF  (0x0000007F)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_4_Counter_Control_OFF  ( 7)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_4_Counter_Control_WID  ( 2)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_4_Counter_Control_MSK  (0x00000180)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_4_Counter_Control_MAX  (0x00000003)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_4_Counter_Control_DEF  (0x00000000)
+
+#define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_5_REG                  (0x00004504)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_5_Counter_Pointer_OFF  ( 0)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_5_Counter_Pointer_WID  ( 7)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_5_Counter_Pointer_MSK  (0x0000007F)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_5_Counter_Pointer_MAX  (0x0000007F)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_5_Counter_Pointer_DEF  (0x0000007F)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_5_Counter_Control_OFF  ( 7)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_5_Counter_Control_WID  ( 2)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_5_Counter_Control_MSK  (0x00000180)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_5_Counter_Control_MAX  (0x00000003)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_5_Counter_Control_DEF  (0x00000000)
+
+#define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_6_REG                  (0x00004508)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_6_Counter_Pointer_OFF  ( 0)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_6_Counter_Pointer_WID  ( 7)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_6_Counter_Pointer_MSK  (0x0000007F)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_6_Counter_Pointer_MAX  (0x0000007F)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_6_Counter_Pointer_DEF  (0x0000007F)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_6_Counter_Control_OFF  ( 7)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_6_Counter_Control_WID  ( 2)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_6_Counter_Control_MSK  (0x00000180)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_6_Counter_Control_MAX  (0x00000003)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_6_Counter_Control_DEF  (0x00000000)
+
+#define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_7_REG                  (0x0000450C)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_7_Counter_Pointer_OFF  ( 0)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_7_Counter_Pointer_WID  ( 7)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_7_Counter_Pointer_MSK  (0x0000007F)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_7_Counter_Pointer_MAX  (0x0000007F)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_7_Counter_Pointer_DEF  (0x0000007F)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_7_Counter_Control_OFF  ( 7)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_7_Counter_Control_WID  ( 2)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_7_Counter_Control_MSK  (0x00000180)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_7_Counter_Control_MAX  (0x00000003)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_7_Counter_Control_DEF  (0x00000000)
+
+#define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_8_REG                  (0x00004510)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_8_Counter_Pointer_OFF  ( 0)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_8_Counter_Pointer_WID  ( 7)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_8_Counter_Pointer_MSK  (0x0000007F)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_8_Counter_Pointer_MAX  (0x0000007F)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_8_Counter_Pointer_DEF  (0x0000007F)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_8_Counter_Control_OFF  ( 7)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_8_Counter_Control_WID  ( 2)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_8_Counter_Control_MSK  (0x00000180)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_8_Counter_Control_MAX  (0x00000003)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_8_Counter_Control_DEF  (0x00000000)
+
+#define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_0_REG               (0x00004514)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_0_Counter_Status_OFF ( 0)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_0_Counter_Status_WID (23)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_0_Counter_Status_MSK (0x007FFFFF)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_0_Counter_Status_MAX (0x007FFFFF)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_0_Counter_Status_DEF (0x00000000)
+
+#define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_1_REG               (0x00004518)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_1_Counter_Status_OFF ( 0)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_1_Counter_Status_WID (23)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_1_Counter_Status_MSK (0x007FFFFF)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_1_Counter_Status_MAX (0x007FFFFF)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_1_Counter_Status_DEF (0x00000000)
+
+#define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_2_REG               (0x0000451C)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_2_Counter_Status_OFF ( 0)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_2_Counter_Status_WID (23)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_2_Counter_Status_MSK (0x007FFFFF)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_2_Counter_Status_MAX (0x007FFFFF)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_2_Counter_Status_DEF (0x00000000)
+
+#define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_3_REG               (0x00004520)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_3_Counter_Status_OFF ( 0)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_3_Counter_Status_WID (23)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_3_Counter_Status_MSK (0x007FFFFF)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_3_Counter_Status_MAX (0x007FFFFF)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_3_Counter_Status_DEF (0x00000000)
+
+#define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_4_REG               (0x00004524)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_4_Counter_Status_OFF ( 0)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_4_Counter_Status_WID (23)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_4_Counter_Status_MSK (0x007FFFFF)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_4_Counter_Status_MAX (0x007FFFFF)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_4_Counter_Status_DEF (0x00000000)
+
+#define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_5_REG               (0x00004528)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_5_Counter_Status_OFF ( 0)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_5_Counter_Status_WID (23)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_5_Counter_Status_MSK (0x007FFFFF)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_5_Counter_Status_MAX (0x007FFFFF)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_5_Counter_Status_DEF (0x00000000)
+
+#define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_6_REG               (0x0000452C)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_6_Counter_Status_OFF ( 0)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_6_Counter_Status_WID (23)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_6_Counter_Status_MSK (0x007FFFFF)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_6_Counter_Status_MAX (0x007FFFFF)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_6_Counter_Status_DEF (0x00000000)
+
+#define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_7_REG               (0x00004530)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_7_Counter_Status_OFF ( 0)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_7_Counter_Status_WID (23)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_7_Counter_Status_MSK (0x007FFFFF)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_7_Counter_Status_MAX (0x007FFFFF)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_7_Counter_Status_DEF (0x00000000)
+
+#define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_8_REG               (0x00004534)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_8_Counter_Status_OFF ( 0)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_8_Counter_Status_WID (23)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_8_Counter_Status_MSK (0x007FFFFF)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_8_Counter_Status_MAX (0x007FFFFF)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_8_Counter_Status_DEF (0x00000000)
+
+#define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_OVERFLOW_STATUS_REG        (0x00004538)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_OVERFLOW_STATUS_Counter_Overflow_Status_OFF ( 0)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_OVERFLOW_STATUS_Counter_Overflow_Status_WID ( 9)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_OVERFLOW_STATUS_Counter_Overflow_Status_MSK (0x000001FF)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_OVERFLOW_STATUS_Counter_Overflow_Status_MAX (0x000001FF)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_OVERFLOW_STATUS_Counter_Overflow_Status_DEF (0x00000000)
+
+#define MCHBAR_CH1_CR_REUT_CH_ERROR_ADDR_REG                         (0x00004580)
+  #define MCHBAR_CH1_CR_REUT_CH_ERROR_ADDR_Column_Address_OFF          ( 0)
+  #define MCHBAR_CH1_CR_REUT_CH_ERROR_ADDR_Column_Address_WID          (10)
+  #define MCHBAR_CH1_CR_REUT_CH_ERROR_ADDR_Column_Address_MSK          (0x000003FF)
+  #define MCHBAR_CH1_CR_REUT_CH_ERROR_ADDR_Column_Address_MAX          (0x000003FF)
+  #define MCHBAR_CH1_CR_REUT_CH_ERROR_ADDR_Column_Address_DEF          (0x00000000)
+  #define MCHBAR_CH1_CR_REUT_CH_ERROR_ADDR_Row_Address_OFF             (24)
+  #define MCHBAR_CH1_CR_REUT_CH_ERROR_ADDR_Row_Address_WID             (16)
+  #define MCHBAR_CH1_CR_REUT_CH_ERROR_ADDR_Row_Address_MSK             (0xFFFF000000)
+  #define MCHBAR_CH1_CR_REUT_CH_ERROR_ADDR_Row_Address_MAX             (0x0000FFFF)
+  #define MCHBAR_CH1_CR_REUT_CH_ERROR_ADDR_Row_Address_DEF             (0x00000000)
+  #define MCHBAR_CH1_CR_REUT_CH_ERROR_ADDR_Bank_Address_OFF            (48)
+  #define MCHBAR_CH1_CR_REUT_CH_ERROR_ADDR_Bank_Address_WID            ( 3)
+  #define MCHBAR_CH1_CR_REUT_CH_ERROR_ADDR_Bank_Address_MSK            (0x7000000000000)
+  #define MCHBAR_CH1_CR_REUT_CH_ERROR_ADDR_Bank_Address_MAX            (0x00000007)
+  #define MCHBAR_CH1_CR_REUT_CH_ERROR_ADDR_Bank_Address_DEF            (0x00000000)
+  #define MCHBAR_CH1_CR_REUT_CH_ERROR_ADDR_Rank_Address_OFF            (56)
+  #define MCHBAR_CH1_CR_REUT_CH_ERROR_ADDR_Rank_Address_WID            ( 2)
+  #define MCHBAR_CH1_CR_REUT_CH_ERROR_ADDR_Rank_Address_MSK            (0x300000000000000)
+  #define MCHBAR_CH1_CR_REUT_CH_ERROR_ADDR_Rank_Address_MAX            (0x00000003)
+  #define MCHBAR_CH1_CR_REUT_CH_ERROR_ADDR_Rank_Address_DEF            (0x00000000)
+
+#define MCHBAR_CH1_CR_REUT_CH_ERR_WDB_CAPTURE_STATUS_REG             (0x00004588)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_WDB_CAPTURE_STATUS_WDB_Current_Error_Pointer_OFF ( 0)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_WDB_CAPTURE_STATUS_WDB_Current_Error_Pointer_WID ( 6)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_WDB_CAPTURE_STATUS_WDB_Current_Error_Pointer_MSK (0x0000003F)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_WDB_CAPTURE_STATUS_WDB_Current_Error_Pointer_MAX (0x0000003F)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_WDB_CAPTURE_STATUS_WDB_Current_Error_Pointer_DEF (0x00000000)
+
+#define MCHBAR_CH1_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_REG                (0x0000458C)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_Enable_WDB_Error_Capture_OFF ( 0)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_Enable_WDB_Error_Capture_WID ( 1)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_Enable_WDB_Error_Capture_MSK (0x00000001)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_Enable_WDB_Error_Capture_MAX (0x00000001)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_Enable_WDB_Error_Capture_DEF (0x00000000)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_WDB_Starting_Error_Pointer_OFF ( 8)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_WDB_Starting_Error_Pointer_WID ( 6)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_WDB_Starting_Error_Pointer_MSK (0x00003F00)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_WDB_Starting_Error_Pointer_MAX (0x0000003F)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_WDB_Starting_Error_Pointer_DEF (0x00000000)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_WDB_Ending_Error_Pointer_OFF (16)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_WDB_Ending_Error_Pointer_WID ( 6)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_WDB_Ending_Error_Pointer_MSK (0x003F0000)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_WDB_Ending_Error_Pointer_MAX (0x0000003F)
+  #define MCHBAR_CH1_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_WDB_Ending_Error_Pointer_DEF (0x00000000)
+
+#define MCHBAR_CH1_CR_REUT_CH_MISC_CKE_CTRL_REG                      (0x00004590)
+  #define MCHBAR_CH1_CR_REUT_CH_MISC_CKE_CTRL_CKE_Override_OFF         ( 0)
+  #define MCHBAR_CH1_CR_REUT_CH_MISC_CKE_CTRL_CKE_Override_WID         ( 4)
+  #define MCHBAR_CH1_CR_REUT_CH_MISC_CKE_CTRL_CKE_Override_MSK         (0x0000000F)
+  #define MCHBAR_CH1_CR_REUT_CH_MISC_CKE_CTRL_CKE_Override_MAX         (0x0000000F)
+  #define MCHBAR_CH1_CR_REUT_CH_MISC_CKE_CTRL_CKE_Override_DEF         (0x0000000F)
+  #define MCHBAR_CH1_CR_REUT_CH_MISC_CKE_CTRL_CKE_En_Start_Test_Sync_OFF ( 8)
+  #define MCHBAR_CH1_CR_REUT_CH_MISC_CKE_CTRL_CKE_En_Start_Test_Sync_WID ( 1)
+  #define MCHBAR_CH1_CR_REUT_CH_MISC_CKE_CTRL_CKE_En_Start_Test_Sync_MSK (0x00000100)
+  #define MCHBAR_CH1_CR_REUT_CH_MISC_CKE_CTRL_CKE_En_Start_Test_Sync_MAX (0x00000001)
+  #define MCHBAR_CH1_CR_REUT_CH_MISC_CKE_CTRL_CKE_En_Start_Test_Sync_DEF (0x00000000)
+  #define MCHBAR_CH1_CR_REUT_CH_MISC_CKE_CTRL_CKE_On_OFF               (16)
+  #define MCHBAR_CH1_CR_REUT_CH_MISC_CKE_CTRL_CKE_On_WID               ( 4)
+  #define MCHBAR_CH1_CR_REUT_CH_MISC_CKE_CTRL_CKE_On_MSK               (0x000F0000)
+  #define MCHBAR_CH1_CR_REUT_CH_MISC_CKE_CTRL_CKE_On_MAX               (0x0000000F)
+  #define MCHBAR_CH1_CR_REUT_CH_MISC_CKE_CTRL_CKE_On_DEF               (0x00000000)
+
+#define MCHBAR_CH1_CR_REUT_CH_MISC_ODT_CTRL_REG                      (0x00004594)
+  #define MCHBAR_CH1_CR_REUT_CH_MISC_ODT_CTRL_ODT_Override_OFF         ( 0)
+  #define MCHBAR_CH1_CR_REUT_CH_MISC_ODT_CTRL_ODT_Override_WID         ( 4)
+  #define MCHBAR_CH1_CR_REUT_CH_MISC_ODT_CTRL_ODT_Override_MSK         (0x0000000F)
+  #define MCHBAR_CH1_CR_REUT_CH_MISC_ODT_CTRL_ODT_Override_MAX         (0x0000000F)
+  #define MCHBAR_CH1_CR_REUT_CH_MISC_ODT_CTRL_ODT_Override_DEF         (0x0000000F)
+  #define MCHBAR_CH1_CR_REUT_CH_MISC_ODT_CTRL_ODT_On_OFF               (16)
+  #define MCHBAR_CH1_CR_REUT_CH_MISC_ODT_CTRL_ODT_On_WID               ( 4)
+  #define MCHBAR_CH1_CR_REUT_CH_MISC_ODT_CTRL_ODT_On_MSK               (0x000F0000)
+  #define MCHBAR_CH1_CR_REUT_CH_MISC_ODT_CTRL_ODT_On_MAX               (0x0000000F)
+  #define MCHBAR_CH1_CR_REUT_CH_MISC_ODT_CTRL_ODT_On_DEF               (0x00000000)
+  #define MCHBAR_CH1_CR_REUT_CH_MISC_ODT_CTRL_MPR_Train_DDR_On_OFF     (31)
+  #define MCHBAR_CH1_CR_REUT_CH_MISC_ODT_CTRL_MPR_Train_DDR_On_WID     ( 1)
+  #define MCHBAR_CH1_CR_REUT_CH_MISC_ODT_CTRL_MPR_Train_DDR_On_MSK     (0x80000000)
+  #define MCHBAR_CH1_CR_REUT_CH_MISC_ODT_CTRL_MPR_Train_DDR_On_MAX     (0x00000001)
+  #define MCHBAR_CH1_CR_REUT_CH_MISC_ODT_CTRL_MPR_Train_DDR_On_DEF     (0x00000000)
+
+#define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_REG                      (0x00004598)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_Enable_CADB_on_Deselect_OFF ( 0)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_Enable_CADB_on_Deselect_WID ( 1)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_Enable_CADB_on_Deselect_MSK (0x00000001)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_Enable_CADB_on_Deselect_MAX (0x00000001)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_Enable_CADB_on_Deselect_DEF (0x00000000)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_Enable_CADB_Always_On_OFF ( 1)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_Enable_CADB_Always_On_WID ( 1)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_Enable_CADB_Always_On_MSK (0x00000002)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_Enable_CADB_Always_On_MAX (0x00000001)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_Enable_CADB_Always_On_DEF (0x00000000)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_CMD_Deselect_Start_OFF  ( 2)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_CMD_Deselect_Start_WID  ( 4)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_CMD_Deselect_Start_MSK  (0x0000003C)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_CMD_Deselect_Start_MAX  (0x0000000F)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_CMD_Deselect_Start_DEF  (0x00000000)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_CMD_Deselect_Stop_OFF  ( 6)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_CMD_Deselect_Stop_WID  ( 4)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_CMD_Deselect_Stop_MSK  (0x000003C0)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_CMD_Deselect_Stop_MAX  (0x0000000F)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_CMD_Deselect_Stop_DEF  (0x00000000)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_Lane_Deselect_Enable_OFF  ( 10)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_Lane_Deselect_Enable_WID  ( 4)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_Lane_Deselect_Enable_MSK  (0x00003C00)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_Lane_Deselect_Enable_MAX  (0x0000000F)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_Lane_Deselect_Enable_DEF  (0x00000000)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_CAS_Select_Enable_OFF  ( 14)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_CAS_Select_Enable_WID  ( 2)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_CAS_Select_Enable_MSK  (0x0000C000)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_CAS_Select_Enable_MAX  (0x00000003)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_CAS_Select_Enable_DEF  (0x00000000)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_ACT_Select_Enable_OFF  ( 16)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_ACT_Select_Enable_WID  ( 2)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_ACT_Select_Enable_MSK  (0x00030000)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_ACT_Select_Enable_MAX  (0x00000003)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_ACT_Select_Enable_DEF  (0x00000000)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_PRE_Select_Enable_OFF  ( 18)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_PRE_Select_Enable_WID  ( 2)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_PRE_Select_Enable_MSK  (0x000C0000)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_PRE_Select_Enable_MAX  (0x00000003)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_PRE_Select_Enable_DEF  (0x00000000)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_Save_Current_Seed_OFF  ( 20)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_Save_Current_Seed_WID  ( 4)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_Save_Current_Seed_MSK  (0x00F00000)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_Save_Current_Seed_MAX  (0x0000000F)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_Save_Current_Seed_DEF  (0x00000000)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_Reload_Starting_Seed_OFF  ( 24)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_Reload_Starting_Seed_WID  ( 4)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_Reload_Starting_Seed_MSK  (0x0F000000)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_Reload_Starting_Seed_MAX  (0x0000000F)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_Reload_Starting_Seed_DEF  (0x00000000)
+
+#define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MRS_REG                       (0x0000459C)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MRS_MRS_Gap_OFF               ( 0)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MRS_MRS_Gap_WID               ( 3)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MRS_MRS_Gap_MSK               (0x00000007)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MRS_MRS_Gap_MAX               (0x00000007)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MRS_MRS_Gap_DEF               (0x00000002)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MRS_CADB_MRS_Start_Pointer_OFF ( 8)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MRS_CADB_MRS_Start_Pointer_WID ( 3)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MRS_CADB_MRS_Start_Pointer_MSK (0x00000700)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MRS_CADB_MRS_Start_Pointer_MAX (0x00000007)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MRS_CADB_MRS_Start_Pointer_DEF (0x00000000)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MRS_CADB_MRS_End_Pointer_OFF  (16)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MRS_CADB_MRS_End_Pointer_WID  ( 3)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MRS_CADB_MRS_End_Pointer_MSK  (0x00070000)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MRS_CADB_MRS_End_Pointer_MAX  (0x00000007)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MRS_CADB_MRS_End_Pointer_DEF  (0x00000007)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MRS_CADB_MRS_Current_Pointer_OFF (24)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MRS_CADB_MRS_Current_Pointer_WID ( 3)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MRS_CADB_MRS_Current_Pointer_MSK (0x07000000)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MRS_CADB_MRS_Current_Pointer_MAX (0x00000007)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MRS_CADB_MRS_Current_Pointer_DEF (0x00000000)
+
+#define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_CTRL_REG                  (0x000045A0)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_CTRL_Mux0_Control_OFF     ( 0)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_CTRL_Mux0_Control_WID     ( 2)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_CTRL_Mux0_Control_MSK     (0x00000003)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_CTRL_Mux0_Control_MAX     (0x00000003)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_CTRL_Mux0_Control_DEF     (0x00000001)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_CTRL_Mux1_Control_OFF     ( 4)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_CTRL_Mux1_Control_WID     ( 2)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_CTRL_Mux1_Control_MSK     (0x00000030)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_CTRL_Mux1_Control_MAX     (0x00000003)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_CTRL_Mux1_Control_DEF     (0x00000001)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_CTRL_Mux2_Control_OFF     ( 8)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_CTRL_Mux2_Control_WID     ( 2)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_CTRL_Mux2_Control_MSK     (0x00000300)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_CTRL_Mux2_Control_MAX     (0x00000003)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_CTRL_Mux2_Control_DEF     (0x00000001)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_CTRL_Select_Mux0_Control_OFF       ( 16)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_CTRL_Select_Mux0_Control_WID       ( 2)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_CTRL_Select_Mux0_Control_MSK       (0x00030000)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_CTRL_Select_Mux0_Control_MAX       (0x00000003)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_CTRL_Select_Mux0_Control_DEF       (0x00000001)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_CTRL_Select_Mux1_Control_OFF       ( 20)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_CTRL_Select_Mux1_Control_WID       ( 2)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_CTRL_Select_Mux1_Control_MSK       (0x00300000)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_CTRL_Select_Mux1_Control_MAX       (0x00000003)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_CTRL_Select_Mux1_Control_DEF       (0x00000001)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_CTRL_Select_Mux2_Control_OFF       ( 24)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_CTRL_Select_Mux2_Control_WID       ( 2)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_CTRL_Select_Mux2_Control_MSK       (0x03000000)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_CTRL_Select_Mux2_Control_MAX       (0x00000003)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_CTRL_Select_Mux2_Control_DEF       (0x00000001)
+
+#define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_PB_0_REG                  (0x000045A4)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_PB_0_Pattern_Buffer_OFF   ( 0)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_PB_0_Pattern_Buffer_WID   (16)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_PB_0_Pattern_Buffer_MSK   (0x0000FFFF)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_PB_0_Pattern_Buffer_MAX   (0x0000FFFF)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_PB_0_Pattern_Buffer_DEF   (0x00000000)
+
+#define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_PB_1_REG                  (0x000045A8)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_PB_1_Pattern_Buffer_OFF   ( 0)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_PB_1_Pattern_Buffer_WID   (16)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_PB_1_Pattern_Buffer_MSK   (0x0000FFFF)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_PB_1_Pattern_Buffer_MAX   (0x0000FFFF)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_PB_1_Pattern_Buffer_DEF   (0x00000000)
+
+#define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_PB_2_REG                  (0x000045AC)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_PB_2_Pattern_Buffer_OFF   ( 0)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_PB_2_Pattern_Buffer_WID   (16)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_PB_2_Pattern_Buffer_MSK   (0x0000FFFF)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_PB_2_Pattern_Buffer_MAX   (0x0000FFFF)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_PB_2_Pattern_Buffer_DEF   (0x00000000)
+
+#define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_REG                (0x000045B0)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_L_data_select_OFF  ( 0)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_L_data_select_WID  ( 1)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_L_data_select_MSK  (0x00000001)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_L_data_select_MAX  (0x00000001)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_L_data_select_DEF  (0x00000000)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_Enable_Sweep_Frequency_OFF ( 1)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_Enable_Sweep_Frequency_WID ( 1)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_Enable_Sweep_Frequency_MSK (0x00000002)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_Enable_Sweep_Frequency_MAX (0x00000001)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_Enable_Sweep_Frequency_DEF (0x00000000)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_L_counter_OFF      ( 8)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_L_counter_WID      ( 8)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_L_counter_MSK      (0x0000FF00)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_L_counter_MAX      (0x000000FF)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_L_counter_DEF      (0x00000001)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_M_counter_OFF      (16)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_M_counter_WID      ( 8)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_M_counter_MSK      (0x00FF0000)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_M_counter_MAX      (0x000000FF)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_M_counter_DEF      (0x00000001)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_N_counter_OFF      (24)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_N_counter_WID      ( 8)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_N_counter_MSK      (0xFF000000)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_N_counter_MAX      (0x000000FF)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_N_counter_DEF      (0x00000001)
+
+#define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_WRITE_POINTER_REG             (0x000045BC)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_WRITE_POINTER_CADB_Write_Pointer_OFF ( 0)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_WRITE_POINTER_CADB_Write_Pointer_WID ( 3)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_WRITE_POINTER_CADB_Write_Pointer_MSK (0x00000007)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_WRITE_POINTER_CADB_Write_Pointer_MAX (0x00000007)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_WRITE_POINTER_CADB_Write_Pointer_DEF (0x00000000)
+
+#define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_PROG_REG                      (0x000045C0)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_Address_OFF    ( 0)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_Address_WID    (16)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_Address_MSK    (0x0000FFFF)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_Address_MAX    (0x0000FFFF)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_Address_DEF    (0x00000000)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_Bank_OFF       (24)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_Bank_WID       ( 3)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_Bank_MSK       (0x07000000)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_Bank_MAX       (0x00000007)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_Bank_DEF       (0x00000000)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_CS_OFF         (32)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_CS_WID         ( 4)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_CS_MSK         (0xF00000000)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_CS_MAX         (0x0000000F)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_CS_DEF         (0x00000000)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_Control_OFF    (40)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_Control_WID    ( 3)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_Control_MSK    (0x70000000000)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_Control_MAX    (0x00000007)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_Control_DEF    (0x00000000)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_ODT_OFF        (48)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_ODT_WID        ( 4)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_ODT_MSK        (0xF000000000000)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_ODT_MAX        (0x0000000F)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_ODT_DEF        (0x00000000)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_CKE_OFF        (56)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_CKE_WID        ( 4)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_CKE_MSK        (0xF00000000000000)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_CKE_MAX        (0x0000000F)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_CKE_DEF        (0x00000000)
+
+#define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_0_REG                (0x000045C8)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_0_Pattern_Buffer_OFF ( 0)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_0_Pattern_Buffer_WID (16)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_0_Pattern_Buffer_MSK (0x0000FFFF)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_0_Pattern_Buffer_MAX (0x0000FFFF)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_0_Pattern_Buffer_DEF (0x00000000)
+
+#define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_1_REG                (0x000045CC)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_1_Pattern_Buffer_OFF ( 0)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_1_Pattern_Buffer_WID (16)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_1_Pattern_Buffer_MSK (0x0000FFFF)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_1_Pattern_Buffer_MAX (0x0000FFFF)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_1_Pattern_Buffer_DEF (0x00000000)
+
+#define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_2_REG                (0x000045D0)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_2_Pattern_Buffer_OFF ( 0)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_2_Pattern_Buffer_WID (16)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_2_Pattern_Buffer_MSK (0x0000FFFF)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_2_Pattern_Buffer_MAX (0x0000FFFF)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_2_Pattern_Buffer_DEF (0x00000000)
+
+#define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_CTRL_REG                    (0x00004600)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_Increment_Rate_OFF ( 0)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_Increment_Rate_WID ( 5)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_Increment_Rate_MSK (0x0000001F)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_Increment_Rate_MAX (0x0000001F)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_Increment_Rate_DEF (0x00000000)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_Increment_Scale_OFF ( 5)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_Increment_Scale_WID ( 1)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_Increment_Scale_MSK (0x00000020)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_Increment_Scale_MAX (0x00000001)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_Increment_Scale_DEF (0x00000000)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_Start_Pointer_OFF  ( 8)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_Start_Pointer_WID  ( 6)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_Start_Pointer_MSK  (0x00003F00)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_Start_Pointer_MAX  (0x0000003F)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_Start_Pointer_DEF  (0x00000000)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_End_Pointer_OFF    (16)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_End_Pointer_WID    ( 6)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_End_Pointer_MSK    (0x003F0000)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_End_Pointer_MAX    (0x0000003F)
+  #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_End_Pointer_DEF    (0x0000003F)
+
+#define MCHBAR_CH1_CR_REUT_CH_MISC_REFRESH_CTRL_REG                  (0x00004604)
+  #define MCHBAR_CH1_CR_REUT_CH_MISC_REFRESH_CTRL_Refresh_Rank_Mask_OFF ( 0)
+  #define MCHBAR_CH1_CR_REUT_CH_MISC_REFRESH_CTRL_Refresh_Rank_Mask_WID ( 4)
+  #define MCHBAR_CH1_CR_REUT_CH_MISC_REFRESH_CTRL_Refresh_Rank_Mask_MSK (0x0000000F)
+  #define MCHBAR_CH1_CR_REUT_CH_MISC_REFRESH_CTRL_Refresh_Rank_Mask_MAX (0x0000000F)
+  #define MCHBAR_CH1_CR_REUT_CH_MISC_REFRESH_CTRL_Refresh_Rank_Mask_DEF (0x00000000)
+  #define MCHBAR_CH1_CR_REUT_CH_MISC_REFRESH_CTRL_RefZQ_En_Start_Test_Sync_OFF ( 8)
+  #define MCHBAR_CH1_CR_REUT_CH_MISC_REFRESH_CTRL_RefZQ_En_Start_Test_Sync_WID ( 1)
+  #define MCHBAR_CH1_CR_REUT_CH_MISC_REFRESH_CTRL_RefZQ_En_Start_Test_Sync_MSK (0x00000100)
+  #define MCHBAR_CH1_CR_REUT_CH_MISC_REFRESH_CTRL_RefZQ_En_Start_Test_Sync_MAX (0x00000001)
+  #define MCHBAR_CH1_CR_REUT_CH_MISC_REFRESH_CTRL_RefZQ_En_Start_Test_Sync_DEF (0x00000000)
+  #define MCHBAR_CH1_CR_REUT_CH_MISC_REFRESH_CTRL_Panic_Refresh_Only_OFF (31)
+  #define MCHBAR_CH1_CR_REUT_CH_MISC_REFRESH_CTRL_Panic_Refresh_Only_WID ( 1)
+  #define MCHBAR_CH1_CR_REUT_CH_MISC_REFRESH_CTRL_Panic_Refresh_Only_MSK (0x80000000)
+  #define MCHBAR_CH1_CR_REUT_CH_MISC_REFRESH_CTRL_Panic_Refresh_Only_MAX (0x00000001)
+  #define MCHBAR_CH1_CR_REUT_CH_MISC_REFRESH_CTRL_Panic_Refresh_Only_DEF (0x00000000)
+
+#define MCHBAR_CH1_CR_REUT_CH_MISC_ZQ_CTRL_REG                       (0x00004608)
+  #define MCHBAR_CH1_CR_REUT_CH_MISC_ZQ_CTRL_ZQ_Rank_Mask_OFF          ( 0)
+  #define MCHBAR_CH1_CR_REUT_CH_MISC_ZQ_CTRL_ZQ_Rank_Mask_WID          ( 4)
+  #define MCHBAR_CH1_CR_REUT_CH_MISC_ZQ_CTRL_ZQ_Rank_Mask_MSK          (0x0000000F)
+  #define MCHBAR_CH1_CR_REUT_CH_MISC_ZQ_CTRL_ZQ_Rank_Mask_MAX          (0x0000000F)
+  #define MCHBAR_CH1_CR_REUT_CH_MISC_ZQ_CTRL_ZQ_Rank_Mask_DEF          (0x00000000)
+  #define MCHBAR_CH1_CR_REUT_CH_MISC_ZQ_CTRL_Always_Do_ZQ_OFF          (31)
+  #define MCHBAR_CH1_CR_REUT_CH_MISC_ZQ_CTRL_Always_Do_ZQ_WID          ( 1)
+  #define MCHBAR_CH1_CR_REUT_CH_MISC_ZQ_CTRL_Always_Do_ZQ_MSK          (0x80000000)
+  #define MCHBAR_CH1_CR_REUT_CH_MISC_ZQ_CTRL_Always_Do_ZQ_MAX          (0x00000001)
+  #define MCHBAR_CH1_CR_REUT_CH_MISC_ZQ_CTRL_Always_Do_ZQ_DEF          (0x00000000)
+
+#define MCHBAR_CH1_CR_LPDDR_MR_PARAMS_REG                            (0x00004610)
+  #define MCHBAR_CH1_CR_LPDDR_MR_PARAMS_Rank_0_x32_OFF                 ( 0)
+  #define MCHBAR_CH1_CR_LPDDR_MR_PARAMS_Rank_0_x32_WID                 ( 1)
+  #define MCHBAR_CH1_CR_LPDDR_MR_PARAMS_Rank_0_x32_MSK                 (0x00000001)
+  #define MCHBAR_CH1_CR_LPDDR_MR_PARAMS_Rank_0_x32_MAX                 (0x00000001)
+  #define MCHBAR_CH1_CR_LPDDR_MR_PARAMS_Rank_0_x32_DEF                 (0x00000000)
+  #define MCHBAR_CH1_CR_LPDDR_MR_PARAMS_Rank_1_x32_OFF                 ( 1)
+  #define MCHBAR_CH1_CR_LPDDR_MR_PARAMS_Rank_1_x32_WID                 ( 1)
+  #define MCHBAR_CH1_CR_LPDDR_MR_PARAMS_Rank_1_x32_MSK                 (0x00000002)
+  #define MCHBAR_CH1_CR_LPDDR_MR_PARAMS_Rank_1_x32_MAX                 (0x00000001)
+  #define MCHBAR_CH1_CR_LPDDR_MR_PARAMS_Rank_1_x32_DEF                 (0x00000000)
+  #define MCHBAR_CH1_CR_LPDDR_MR_PARAMS_Rank_2_x32_OFF                 ( 2)
+  #define MCHBAR_CH1_CR_LPDDR_MR_PARAMS_Rank_2_x32_WID                 ( 1)
+  #define MCHBAR_CH1_CR_LPDDR_MR_PARAMS_Rank_2_x32_MSK                 (0x00000004)
+  #define MCHBAR_CH1_CR_LPDDR_MR_PARAMS_Rank_2_x32_MAX                 (0x00000001)
+  #define MCHBAR_CH1_CR_LPDDR_MR_PARAMS_Rank_2_x32_DEF                 (0x00000000)
+  #define MCHBAR_CH1_CR_LPDDR_MR_PARAMS_Rank_3_x32_OFF                 ( 3)
+  #define MCHBAR_CH1_CR_LPDDR_MR_PARAMS_Rank_3_x32_WID                 ( 1)
+  #define MCHBAR_CH1_CR_LPDDR_MR_PARAMS_Rank_3_x32_MSK                 (0x00000008)
+  #define MCHBAR_CH1_CR_LPDDR_MR_PARAMS_Rank_3_x32_MAX                 (0x00000001)
+  #define MCHBAR_CH1_CR_LPDDR_MR_PARAMS_Rank_3_x32_DEF                 (0x00000000)
+  #define MCHBAR_CH1_CR_LPDDR_MR_PARAMS_LPDDR2_OFF                     ( 4)
+  #define MCHBAR_CH1_CR_LPDDR_MR_PARAMS_LPDDR2_WID                     ( 1)
+  #define MCHBAR_CH1_CR_LPDDR_MR_PARAMS_LPDDR2_MSK                     (0x00000010)
+  #define MCHBAR_CH1_CR_LPDDR_MR_PARAMS_LPDDR2_MAX                     (0x00000001)
+  #define MCHBAR_CH1_CR_LPDDR_MR_PARAMS_LPDDR2_DEF                     (0x00000000)
+  #define MCHBAR_CH1_CR_LPDDR_MR_PARAMS_MR4_PERIOD_OFF                 ( 8)
+  #define MCHBAR_CH1_CR_LPDDR_MR_PARAMS_MR4_PERIOD_WID                 (16)
+  #define MCHBAR_CH1_CR_LPDDR_MR_PARAMS_MR4_PERIOD_MSK                 (0x00FFFF00)
+  #define MCHBAR_CH1_CR_LPDDR_MR_PARAMS_MR4_PERIOD_MAX                 (0x0000FFFF)
+  #define MCHBAR_CH1_CR_LPDDR_MR_PARAMS_MR4_PERIOD_DEF                 (0x00000000)
+
+#define MCHBAR_CH1_CR_LPDDR_MR_COMMAND_REG                           (0x00004614)
+  #define MCHBAR_CH1_CR_LPDDR_MR_COMMAND_Address_OFF                   ( 0)
+  #define MCHBAR_CH1_CR_LPDDR_MR_COMMAND_Address_WID                   ( 8)
+  #define MCHBAR_CH1_CR_LPDDR_MR_COMMAND_Address_MSK                   (0x000000FF)
+  #define MCHBAR_CH1_CR_LPDDR_MR_COMMAND_Address_MAX                   (0x000000FF)
+  #define MCHBAR_CH1_CR_LPDDR_MR_COMMAND_Address_DEF                   (0x00000000)
+  #define MCHBAR_CH1_CR_LPDDR_MR_COMMAND_Data_OFF                      ( 8)
+  #define MCHBAR_CH1_CR_LPDDR_MR_COMMAND_Data_WID                      ( 8)
+  #define MCHBAR_CH1_CR_LPDDR_MR_COMMAND_Data_MSK                      (0x0000FF00)
+  #define MCHBAR_CH1_CR_LPDDR_MR_COMMAND_Data_MAX                      (0x000000FF)
+  #define MCHBAR_CH1_CR_LPDDR_MR_COMMAND_Data_DEF                      (0x00000000)
+  #define MCHBAR_CH1_CR_LPDDR_MR_COMMAND_Rank_OFF                      (16)
+  #define MCHBAR_CH1_CR_LPDDR_MR_COMMAND_Rank_WID                      ( 2)
+  #define MCHBAR_CH1_CR_LPDDR_MR_COMMAND_Rank_MSK                      (0x00030000)
+  #define MCHBAR_CH1_CR_LPDDR_MR_COMMAND_Rank_MAX                      (0x00000003)
+  #define MCHBAR_CH1_CR_LPDDR_MR_COMMAND_Rank_DEF                      (0x00000000)
+  #define MCHBAR_CH1_CR_LPDDR_MR_COMMAND_Write_OFF                     (18)
+  #define MCHBAR_CH1_CR_LPDDR_MR_COMMAND_Write_WID                     ( 1)
+  #define MCHBAR_CH1_CR_LPDDR_MR_COMMAND_Write_MSK                     (0x00040000)
+  #define MCHBAR_CH1_CR_LPDDR_MR_COMMAND_Write_MAX                     (0x00000001)
+  #define MCHBAR_CH1_CR_LPDDR_MR_COMMAND_Write_DEF                     (0x00000000)
+  #define MCHBAR_CH1_CR_LPDDR_MR_COMMAND_Init_MRW_OFF                  (19)
+  #define MCHBAR_CH1_CR_LPDDR_MR_COMMAND_Init_MRW_WID                  ( 1)
+  #define MCHBAR_CH1_CR_LPDDR_MR_COMMAND_Init_MRW_MSK                  (0x00080000)
+  #define MCHBAR_CH1_CR_LPDDR_MR_COMMAND_Init_MRW_MAX                  (0x00000001)
+  #define MCHBAR_CH1_CR_LPDDR_MR_COMMAND_Init_MRW_DEF                  (0x00000000)
+  #define MCHBAR_CH1_CR_LPDDR_MR_COMMAND_Busy_OFF                      (31)
+  #define MCHBAR_CH1_CR_LPDDR_MR_COMMAND_Busy_WID                      ( 1)
+  #define MCHBAR_CH1_CR_LPDDR_MR_COMMAND_Busy_MSK                      (0x80000000)
+  #define MCHBAR_CH1_CR_LPDDR_MR_COMMAND_Busy_MAX                      (0x00000001)
+  #define MCHBAR_CH1_CR_LPDDR_MR_COMMAND_Busy_DEF                      (0x00000000)
+
+#define MCHBAR_CH1_CR_LPDDR_MR_RESULT_REG                            (0x00004618)
+  #define MCHBAR_CH1_CR_LPDDR_MR_RESULT_Device_0_OFF                   ( 0)
+  #define MCHBAR_CH1_CR_LPDDR_MR_RESULT_Device_0_WID                   ( 8)
+  #define MCHBAR_CH1_CR_LPDDR_MR_RESULT_Device_0_MSK                   (0x000000FF)
+  #define MCHBAR_CH1_CR_LPDDR_MR_RESULT_Device_0_MAX                   (0x000000FF)
+  #define MCHBAR_CH1_CR_LPDDR_MR_RESULT_Device_0_DEF                   (0x00000000)
+  #define MCHBAR_CH1_CR_LPDDR_MR_RESULT_Device_1_OFF                   ( 8)
+  #define MCHBAR_CH1_CR_LPDDR_MR_RESULT_Device_1_WID                   ( 8)
+  #define MCHBAR_CH1_CR_LPDDR_MR_RESULT_Device_1_MSK                   (0x0000FF00)
+  #define MCHBAR_CH1_CR_LPDDR_MR_RESULT_Device_1_MAX                   (0x000000FF)
+  #define MCHBAR_CH1_CR_LPDDR_MR_RESULT_Device_1_DEF                   (0x00000000)
+  #define MCHBAR_CH1_CR_LPDDR_MR_RESULT_Device_2_OFF                   (16)
+  #define MCHBAR_CH1_CR_LPDDR_MR_RESULT_Device_2_WID                   ( 8)
+  #define MCHBAR_CH1_CR_LPDDR_MR_RESULT_Device_2_MSK                   (0x00FF0000)
+  #define MCHBAR_CH1_CR_LPDDR_MR_RESULT_Device_2_MAX                   (0x000000FF)
+  #define MCHBAR_CH1_CR_LPDDR_MR_RESULT_Device_2_DEF                   (0x00000000)
+  #define MCHBAR_CH1_CR_LPDDR_MR_RESULT_Device_3_OFF                   (24)
+  #define MCHBAR_CH1_CR_LPDDR_MR_RESULT_Device_3_WID                   ( 8)
+  #define MCHBAR_CH1_CR_LPDDR_MR_RESULT_Device_3_MSK                   (0xFF000000)
+  #define MCHBAR_CH1_CR_LPDDR_MR_RESULT_Device_3_MAX                   (0x000000FF)
+  #define MCHBAR_CH1_CR_LPDDR_MR_RESULT_Device_3_DEF                   (0x00000000)
+
+#define MCHBAR_CH1_CR_LPDDR_MR4_RANK_TEMPERATURE_REG                 (0x0000461C)
+  #define MCHBAR_CH1_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_0_OFF          ( 0)
+  #define MCHBAR_CH1_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_0_WID          ( 3)
+  #define MCHBAR_CH1_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_0_MSK          (0x00000007)
+  #define MCHBAR_CH1_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_0_MAX          (0x00000007)
+  #define MCHBAR_CH1_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_0_DEF          (0x00000003)
+  #define MCHBAR_CH1_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_1_OFF          ( 8)
+  #define MCHBAR_CH1_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_1_WID          ( 3)
+  #define MCHBAR_CH1_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_1_MSK          (0x00000700)
+  #define MCHBAR_CH1_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_1_MAX          (0x00000007)
+  #define MCHBAR_CH1_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_1_DEF          (0x00000003)
+  #define MCHBAR_CH1_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_2_OFF          (16)
+  #define MCHBAR_CH1_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_2_WID          ( 3)
+  #define MCHBAR_CH1_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_2_MSK          (0x00070000)
+  #define MCHBAR_CH1_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_2_MAX          (0x00000007)
+  #define MCHBAR_CH1_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_2_DEF          (0x00000003)
+  #define MCHBAR_CH1_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_3_OFF          (24)
+  #define MCHBAR_CH1_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_3_WID          ( 3)
+  #define MCHBAR_CH1_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_3_MSK          (0x07000000)
+  #define MCHBAR_CH1_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_3_MAX          (0x00000007)
+  #define MCHBAR_CH1_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_3_DEF          (0x00000003)
+
+#define MCHBAR_CH1_CR_DESWIZZLE_LOW_REG                              (0x00004620)
+  #define MCHBAR_CH1_CR_DESWIZZLE_LOW_Bit_0_OFF                        ( 0)
+  #define MCHBAR_CH1_CR_DESWIZZLE_LOW_Bit_0_WID                        ( 3)
+  #define MCHBAR_CH1_CR_DESWIZZLE_LOW_Bit_0_MSK                        (0x00000007)
+  #define MCHBAR_CH1_CR_DESWIZZLE_LOW_Bit_0_MAX                        (0x00000007)
+  #define MCHBAR_CH1_CR_DESWIZZLE_LOW_Bit_0_DEF                        (0x00000000)
+  #define MCHBAR_CH1_CR_DESWIZZLE_LOW_Bit_1_OFF                        ( 4)
+  #define MCHBAR_CH1_CR_DESWIZZLE_LOW_Bit_1_WID                        ( 3)
+  #define MCHBAR_CH1_CR_DESWIZZLE_LOW_Bit_1_MSK                        (0x00000070)
+  #define MCHBAR_CH1_CR_DESWIZZLE_LOW_Bit_1_MAX                        (0x00000007)
+  #define MCHBAR_CH1_CR_DESWIZZLE_LOW_Bit_1_DEF                        (0x00000001)
+  #define MCHBAR_CH1_CR_DESWIZZLE_LOW_Bit_2_OFF                        ( 8)
+  #define MCHBAR_CH1_CR_DESWIZZLE_LOW_Bit_2_WID                        ( 3)
+  #define MCHBAR_CH1_CR_DESWIZZLE_LOW_Bit_2_MSK                        (0x00000700)
+  #define MCHBAR_CH1_CR_DESWIZZLE_LOW_Bit_2_MAX                        (0x00000007)
+  #define MCHBAR_CH1_CR_DESWIZZLE_LOW_Bit_2_DEF                        (0x00000002)
+  #define MCHBAR_CH1_CR_DESWIZZLE_LOW_Bit_16_OFF                       (12)
+  #define MCHBAR_CH1_CR_DESWIZZLE_LOW_Bit_16_WID                       ( 3)
+  #define MCHBAR_CH1_CR_DESWIZZLE_LOW_Bit_16_MSK                       (0x00007000)
+  #define MCHBAR_CH1_CR_DESWIZZLE_LOW_Bit_16_MAX                       (0x00000007)
+  #define MCHBAR_CH1_CR_DESWIZZLE_LOW_Bit_16_DEF                       (0x00000000)
+  #define MCHBAR_CH1_CR_DESWIZZLE_LOW_Bit_17_OFF                       (16)
+  #define MCHBAR_CH1_CR_DESWIZZLE_LOW_Bit_17_WID                       ( 3)
+  #define MCHBAR_CH1_CR_DESWIZZLE_LOW_Bit_17_MSK                       (0x00070000)
+  #define MCHBAR_CH1_CR_DESWIZZLE_LOW_Bit_17_MAX                       (0x00000007)
+  #define MCHBAR_CH1_CR_DESWIZZLE_LOW_Bit_17_DEF                       (0x00000001)
+  #define MCHBAR_CH1_CR_DESWIZZLE_LOW_Bit_18_OFF                       (20)
+  #define MCHBAR_CH1_CR_DESWIZZLE_LOW_Bit_18_WID                       ( 3)
+  #define MCHBAR_CH1_CR_DESWIZZLE_LOW_Bit_18_MSK                       (0x00700000)
+  #define MCHBAR_CH1_CR_DESWIZZLE_LOW_Bit_18_MAX                       (0x00000007)
+  #define MCHBAR_CH1_CR_DESWIZZLE_LOW_Bit_18_DEF                       (0x00000002)
+  #define MCHBAR_CH1_CR_DESWIZZLE_LOW_Byte_0_OFF                       (24)
+  #define MCHBAR_CH1_CR_DESWIZZLE_LOW_Byte_0_WID                       ( 3)
+  #define MCHBAR_CH1_CR_DESWIZZLE_LOW_Byte_0_MSK                       (0x07000000)
+  #define MCHBAR_CH1_CR_DESWIZZLE_LOW_Byte_0_MAX                       (0x00000007)
+  #define MCHBAR_CH1_CR_DESWIZZLE_LOW_Byte_0_DEF                       (0x00000000)
+  #define MCHBAR_CH1_CR_DESWIZZLE_LOW_Byte_2_OFF                       (28)
+  #define MCHBAR_CH1_CR_DESWIZZLE_LOW_Byte_2_WID                       ( 3)
+  #define MCHBAR_CH1_CR_DESWIZZLE_LOW_Byte_2_MSK                       (0x70000000)
+  #define MCHBAR_CH1_CR_DESWIZZLE_LOW_Byte_2_MAX                       (0x00000007)
+  #define MCHBAR_CH1_CR_DESWIZZLE_LOW_Byte_2_DEF                       (0x00000002)
+
+#define MCHBAR_CH1_CR_DESWIZZLE_HIGH_REG                             (0x00004624)
+  #define MCHBAR_CH1_CR_DESWIZZLE_HIGH_Bit_32_OFF                      ( 0)
+  #define MCHBAR_CH1_CR_DESWIZZLE_HIGH_Bit_32_WID                      ( 3)
+  #define MCHBAR_CH1_CR_DESWIZZLE_HIGH_Bit_32_MSK                      (0x00000007)
+  #define MCHBAR_CH1_CR_DESWIZZLE_HIGH_Bit_32_MAX                      (0x00000007)
+  #define MCHBAR_CH1_CR_DESWIZZLE_HIGH_Bit_32_DEF                      (0x00000000)
+  #define MCHBAR_CH1_CR_DESWIZZLE_HIGH_Bit_33_OFF                      ( 4)
+  #define MCHBAR_CH1_CR_DESWIZZLE_HIGH_Bit_33_WID                      ( 3)
+  #define MCHBAR_CH1_CR_DESWIZZLE_HIGH_Bit_33_MSK                      (0x00000070)
+  #define MCHBAR_CH1_CR_DESWIZZLE_HIGH_Bit_33_MAX                      (0x00000007)
+  #define MCHBAR_CH1_CR_DESWIZZLE_HIGH_Bit_33_DEF                      (0x00000001)
+  #define MCHBAR_CH1_CR_DESWIZZLE_HIGH_Bit_34_OFF                      ( 8)
+  #define MCHBAR_CH1_CR_DESWIZZLE_HIGH_Bit_34_WID                      ( 3)
+  #define MCHBAR_CH1_CR_DESWIZZLE_HIGH_Bit_34_MSK                      (0x00000700)
+  #define MCHBAR_CH1_CR_DESWIZZLE_HIGH_Bit_34_MAX                      (0x00000007)
+  #define MCHBAR_CH1_CR_DESWIZZLE_HIGH_Bit_34_DEF                      (0x00000002)
+  #define MCHBAR_CH1_CR_DESWIZZLE_HIGH_Bit_48_OFF                      (12)
+  #define MCHBAR_CH1_CR_DESWIZZLE_HIGH_Bit_48_WID                      ( 3)
+  #define MCHBAR_CH1_CR_DESWIZZLE_HIGH_Bit_48_MSK                      (0x00007000)
+  #define MCHBAR_CH1_CR_DESWIZZLE_HIGH_Bit_48_MAX                      (0x00000007)
+  #define MCHBAR_CH1_CR_DESWIZZLE_HIGH_Bit_48_DEF                      (0x00000000)
+  #define MCHBAR_CH1_CR_DESWIZZLE_HIGH_Bit_49_OFF                      (16)
+  #define MCHBAR_CH1_CR_DESWIZZLE_HIGH_Bit_49_WID                      ( 3)
+  #define MCHBAR_CH1_CR_DESWIZZLE_HIGH_Bit_49_MSK                      (0x00070000)
+  #define MCHBAR_CH1_CR_DESWIZZLE_HIGH_Bit_49_MAX                      (0x00000007)
+  #define MCHBAR_CH1_CR_DESWIZZLE_HIGH_Bit_49_DEF                      (0x00000001)
+  #define MCHBAR_CH1_CR_DESWIZZLE_HIGH_Bit_50_OFF                      (20)
+  #define MCHBAR_CH1_CR_DESWIZZLE_HIGH_Bit_50_WID                      ( 3)
+  #define MCHBAR_CH1_CR_DESWIZZLE_HIGH_Bit_50_MSK                      (0x00700000)
+  #define MCHBAR_CH1_CR_DESWIZZLE_HIGH_Bit_50_MAX                      (0x00000007)
+  #define MCHBAR_CH1_CR_DESWIZZLE_HIGH_Bit_50_DEF                      (0x00000002)
+  #define MCHBAR_CH1_CR_DESWIZZLE_HIGH_Byte_4_OFF                      (24)
+  #define MCHBAR_CH1_CR_DESWIZZLE_HIGH_Byte_4_WID                      ( 3)
+  #define MCHBAR_CH1_CR_DESWIZZLE_HIGH_Byte_4_MSK                      (0x07000000)
+  #define MCHBAR_CH1_CR_DESWIZZLE_HIGH_Byte_4_MAX                      (0x00000007)
+  #define MCHBAR_CH1_CR_DESWIZZLE_HIGH_Byte_4_DEF                      (0x00000004)
+  #define MCHBAR_CH1_CR_DESWIZZLE_HIGH_Byte_6_OFF                      (28)
+  #define MCHBAR_CH1_CR_DESWIZZLE_HIGH_Byte_6_WID                      ( 3)
+  #define MCHBAR_CH1_CR_DESWIZZLE_HIGH_Byte_6_MSK                      (0x70000000)
+  #define MCHBAR_CH1_CR_DESWIZZLE_HIGH_Byte_6_MAX                      (0x00000007)
+  #define MCHBAR_CH1_CR_DESWIZZLE_HIGH_Byte_6_DEF                      (0x00000006)
+
+#define MCHBAR_CH1_CR_MC_REFRESH_STAGGER_REG                         (0x0000468C)
+  #define MCHBAR_CH1_CR_MC_REFRESH_STAGGER_Ref_Interval_OFF            ( 0)
+  #define MCHBAR_CH1_CR_MC_REFRESH_STAGGER_Ref_Interval_WID            (11)
+  #define MCHBAR_CH1_CR_MC_REFRESH_STAGGER_Ref_Interval_MSK            (0x000007FF)
+  #define MCHBAR_CH1_CR_MC_REFRESH_STAGGER_Ref_Interval_MAX            (0x000007FF)
+  #define MCHBAR_CH1_CR_MC_REFRESH_STAGGER_Ref_Interval_DEF            (0x00000000)
+  #define MCHBAR_CH1_CR_MC_REFRESH_STAGGER_Ref_Stagger_En_OFF          (11)
+  #define MCHBAR_CH1_CR_MC_REFRESH_STAGGER_Ref_Stagger_En_WID          ( 1)
+  #define MCHBAR_CH1_CR_MC_REFRESH_STAGGER_Ref_Stagger_En_MSK          (0x00000800)
+  #define MCHBAR_CH1_CR_MC_REFRESH_STAGGER_Ref_Stagger_En_MAX          (0x00000001)
+  #define MCHBAR_CH1_CR_MC_REFRESH_STAGGER_Ref_Stagger_En_DEF          (0x00000000)
+  #define MCHBAR_CH1_CR_MC_REFRESH_STAGGER_Ref_Stagger_Mode_OFF        (12)
+  #define MCHBAR_CH1_CR_MC_REFRESH_STAGGER_Ref_Stagger_Mode_WID        ( 1)
+  #define MCHBAR_CH1_CR_MC_REFRESH_STAGGER_Ref_Stagger_Mode_MSK        (0x00001000)
+  #define MCHBAR_CH1_CR_MC_REFRESH_STAGGER_Ref_Stagger_Mode_MAX        (0x00000001)
+  #define MCHBAR_CH1_CR_MC_REFRESH_STAGGER_Ref_Stagger_Mode_DEF        (0x00000000)
+  #define MCHBAR_CH1_CR_MC_REFRESH_STAGGER_Disable_Stolen_Refresh_OFF  (13)
+  #define MCHBAR_CH1_CR_MC_REFRESH_STAGGER_Disable_Stolen_Refresh_WID  ( 1)
+  #define MCHBAR_CH1_CR_MC_REFRESH_STAGGER_Disable_Stolen_Refresh_MSK  (0x00002000)
+  #define MCHBAR_CH1_CR_MC_REFRESH_STAGGER_Disable_Stolen_Refresh_MAX  (0x00000001)
+  #define MCHBAR_CH1_CR_MC_REFRESH_STAGGER_Disable_Stolen_Refresh_DEF  (0x00000000)
+  #define MCHBAR_CH1_CR_MC_REFRESH_STAGGER_En_Ref_Type_Display_OFF     (14)
+  #define MCHBAR_CH1_CR_MC_REFRESH_STAGGER_En_Ref_Type_Display_WID     ( 1)
+  #define MCHBAR_CH1_CR_MC_REFRESH_STAGGER_En_Ref_Type_Display_MSK     (0x00004000)
+  #define MCHBAR_CH1_CR_MC_REFRESH_STAGGER_En_Ref_Type_Display_MAX     (0x00000001)
+  #define MCHBAR_CH1_CR_MC_REFRESH_STAGGER_En_Ref_Type_Display_DEF     (0x00000000)
+
+#define MCHBAR_CH1_CR_TC_ZQCAL_REG                                   (0x00004690)
+  #define MCHBAR_CH1_CR_TC_ZQCAL_ZQCS_period_OFF                       ( 0)
+  #define MCHBAR_CH1_CR_TC_ZQCAL_ZQCS_period_WID                       ( 8)
+  #define MCHBAR_CH1_CR_TC_ZQCAL_ZQCS_period_MSK                       (0x000000FF)
+  #define MCHBAR_CH1_CR_TC_ZQCAL_ZQCS_period_MAX                       (0x000000FF)
+  #define MCHBAR_CH1_CR_TC_ZQCAL_ZQCS_period_DEF                       (0x00000080)
+  #define MCHBAR_CH1_CR_TC_ZQCAL_tZQCS_OFF                             ( 8)
+  #define MCHBAR_CH1_CR_TC_ZQCAL_tZQCS_WID                             ( 8)
+  #define MCHBAR_CH1_CR_TC_ZQCAL_tZQCS_MSK                             (0x0000FF00)
+  #define MCHBAR_CH1_CR_TC_ZQCAL_tZQCS_MAX                             (0x000000FF)
+  #define MCHBAR_CH1_CR_TC_ZQCAL_tZQCS_DEF                             (0x00000040)
+  #define MCHBAR_CH1_CR_TC_ZQCAL_ZQCS_period_Ult_OFF                   ( 0)
+  #define MCHBAR_CH1_CR_TC_ZQCAL_ZQCS_period_Ult_WID                   (10)
+  #define MCHBAR_CH1_CR_TC_ZQCAL_ZQCS_period_Ult_MSK                   (0x000003FF)
+  #define MCHBAR_CH1_CR_TC_ZQCAL_ZQCS_period_Ult_MAX                   (0x000003FF)
+  #define MCHBAR_CH1_CR_TC_ZQCAL_ZQCS_period_Ult_DEF                   (0x00000080)
+  #define MCHBAR_CH1_CR_TC_ZQCAL_tZQCS_Ult_OFF                         (10)
+  #define MCHBAR_CH1_CR_TC_ZQCAL_tZQCS_Ult_WID                         (10)
+  #define MCHBAR_CH1_CR_TC_ZQCAL_tZQCS_Ult_MSK                         (0x000FFC00)
+  #define MCHBAR_CH1_CR_TC_ZQCAL_tZQCS_Ult_MAX                         (0x000003FF)
+  #define MCHBAR_CH1_CR_TC_ZQCAL_tZQCS_Ult_DEF                         (0x00000040)
+
+#define MCHBAR_CH1_CR_TC_RFP_REG                                     (0x00004694)
+  #define MCHBAR_CH1_CR_TC_RFP_OREF_RI_OFF                             ( 0)
+  #define MCHBAR_CH1_CR_TC_RFP_OREF_RI_WID                             ( 8)
+  #define MCHBAR_CH1_CR_TC_RFP_OREF_RI_MSK                             (0x000000FF)
+  #define MCHBAR_CH1_CR_TC_RFP_OREF_RI_MAX                             (0x000000FF)
+  #define MCHBAR_CH1_CR_TC_RFP_OREF_RI_DEF                             (0x0000000F)
+  #define MCHBAR_CH1_CR_TC_RFP_Refresh_HP_WM_OFF                       ( 8)
+  #define MCHBAR_CH1_CR_TC_RFP_Refresh_HP_WM_WID                       ( 4)
+  #define MCHBAR_CH1_CR_TC_RFP_Refresh_HP_WM_MSK                       (0x00000F00)
+  #define MCHBAR_CH1_CR_TC_RFP_Refresh_HP_WM_MAX                       (0x0000000F)
+  #define MCHBAR_CH1_CR_TC_RFP_Refresh_HP_WM_DEF                       (0x00000008)
+  #define MCHBAR_CH1_CR_TC_RFP_Refresh_panic_wm_OFF                    (12)
+  #define MCHBAR_CH1_CR_TC_RFP_Refresh_panic_wm_WID                    ( 4)
+  #define MCHBAR_CH1_CR_TC_RFP_Refresh_panic_wm_MSK                    (0x0000F000)
+  #define MCHBAR_CH1_CR_TC_RFP_Refresh_panic_wm_MAX                    (0x0000000F)
+  #define MCHBAR_CH1_CR_TC_RFP_Refresh_panic_wm_DEF                    (0x00000009)
+
+#define MCHBAR_CH1_CR_TC_RFTP_REG                                    (0x00004698)
+  #define MCHBAR_CH1_CR_TC_RFTP_tREFI_OFF                              ( 0)
+  #define MCHBAR_CH1_CR_TC_RFTP_tREFI_WID                              (16)
+  #define MCHBAR_CH1_CR_TC_RFTP_tREFI_MSK                              (0x0000FFFF)
+  #define MCHBAR_CH1_CR_TC_RFTP_tREFI_MAX                              (0x0000FFFF)
+  #define MCHBAR_CH1_CR_TC_RFTP_tREFI_DEF                              (0x00001004)
+  #define MCHBAR_CH1_CR_TC_RFTP_tRFC_OFF                               (16)
+  #define MCHBAR_CH1_CR_TC_RFTP_tRFC_WID                               ( 9)
+  #define MCHBAR_CH1_CR_TC_RFTP_tRFC_MSK                               (0x01FF0000)
+  #define MCHBAR_CH1_CR_TC_RFTP_tRFC_MAX                               (0x000001FF)
+  #define MCHBAR_CH1_CR_TC_RFTP_tRFC_DEF                               (0x000000B4)
+  #define MCHBAR_CH1_CR_TC_RFTP_tREFIx9_OFF                            (25)
+  #define MCHBAR_CH1_CR_TC_RFTP_tREFIx9_WID                            ( 7)
+  #define MCHBAR_CH1_CR_TC_RFTP_tREFIx9_MSK                            (0xFE000000)
+  #define MCHBAR_CH1_CR_TC_RFTP_tREFIx9_MAX                            (0x0000007F)
+  #define MCHBAR_CH1_CR_TC_RFTP_tREFIx9_DEF                            (0x00000023)
+
+#define MCHBAR_CH1_CR_TC_MR2_SHADDOW_REG                             (0x0000469C)
+  #define MCHBAR_CH1_CR_TC_MR2_SHADDOW_MR2_sh_low_OFF                  ( 0)
+  #define MCHBAR_CH1_CR_TC_MR2_SHADDOW_MR2_sh_low_WID                  ( 6)
+  #define MCHBAR_CH1_CR_TC_MR2_SHADDOW_MR2_sh_low_MSK                  (0x0000003F)
+  #define MCHBAR_CH1_CR_TC_MR2_SHADDOW_MR2_sh_low_MAX                  (0x0000003F)
+  #define MCHBAR_CH1_CR_TC_MR2_SHADDOW_MR2_sh_low_DEF                  (0x00000000)
+  #define MCHBAR_CH1_CR_TC_MR2_SHADDOW_SRT_avail_OFF                   ( 6)
+  #define MCHBAR_CH1_CR_TC_MR2_SHADDOW_SRT_avail_WID                   ( 2)
+  #define MCHBAR_CH1_CR_TC_MR2_SHADDOW_SRT_avail_MSK                   (0x000000C0)
+  #define MCHBAR_CH1_CR_TC_MR2_SHADDOW_SRT_avail_MAX                   (0x00000003)
+  #define MCHBAR_CH1_CR_TC_MR2_SHADDOW_SRT_avail_DEF                   (0x00000000)
+  #define MCHBAR_CH1_CR_TC_MR2_SHADDOW_MR2_sh_high_OFF                 ( 8)
+  #define MCHBAR_CH1_CR_TC_MR2_SHADDOW_MR2_sh_high_WID                 ( 3)
+  #define MCHBAR_CH1_CR_TC_MR2_SHADDOW_MR2_sh_high_MSK                 (0x00000700)
+  #define MCHBAR_CH1_CR_TC_MR2_SHADDOW_MR2_sh_high_MAX                 (0x00000007)
+  #define MCHBAR_CH1_CR_TC_MR2_SHADDOW_MR2_sh_high_DEF                 (0x00000000)
+  #define MCHBAR_CH1_CR_TC_MR2_SHADDOW_Addr_bit_swizzle_OFF            (14)
+  #define MCHBAR_CH1_CR_TC_MR2_SHADDOW_Addr_bit_swizzle_WID            ( 2)
+  #define MCHBAR_CH1_CR_TC_MR2_SHADDOW_Addr_bit_swizzle_MSK            (0x0000C000)
+  #define MCHBAR_CH1_CR_TC_MR2_SHADDOW_Addr_bit_swizzle_MAX            (0x00000003)
+  #define MCHBAR_CH1_CR_TC_MR2_SHADDOW_Addr_bit_swizzle_DEF            (0x00000000)
+
+#define MCHBAR_CH1_CR_MC_INIT_STATE_REG                              (0x000046A0)
+  #define MCHBAR_CH1_CR_MC_INIT_STATE_Rank_occupancy_OFF               ( 0)
+  #define MCHBAR_CH1_CR_MC_INIT_STATE_Rank_occupancy_WID               ( 4)
+  #define MCHBAR_CH1_CR_MC_INIT_STATE_Rank_occupancy_MSK               (0x0000000F)
+  #define MCHBAR_CH1_CR_MC_INIT_STATE_Rank_occupancy_MAX               (0x0000000F)
+  #define MCHBAR_CH1_CR_MC_INIT_STATE_Rank_occupancy_DEF               (0x0000000F)
+
+#define MCHBAR_CH1_CR_TC_SRFTP_REG                                   (0x000046A4)
+  #define MCHBAR_CH1_CR_TC_SRFTP_tXSDLL_OFF                            ( 0)
+  #define MCHBAR_CH1_CR_TC_SRFTP_tXSDLL_WID                            (12)
+  #define MCHBAR_CH1_CR_TC_SRFTP_tXSDLL_MSK                            (0x00000FFF)
+  #define MCHBAR_CH1_CR_TC_SRFTP_tXSDLL_MAX                            (0x00000FFF)
+  #define MCHBAR_CH1_CR_TC_SRFTP_tXSDLL_DEF                            (0x00000200)
+  #define MCHBAR_CH1_CR_TC_SRFTP_tXS_offset_OFF                        (12)
+  #define MCHBAR_CH1_CR_TC_SRFTP_tXS_offset_WID                        ( 4)
+  #define MCHBAR_CH1_CR_TC_SRFTP_tXS_offset_MSK                        (0x0000F000)
+  #define MCHBAR_CH1_CR_TC_SRFTP_tXS_offset_MAX                        (0x0000000F)
+  #define MCHBAR_CH1_CR_TC_SRFTP_tXS_offset_DEF                        (0x0000000B)
+  #define MCHBAR_CH1_CR_TC_SRFTP_tZQOPER_OFF                           (16)
+  #define MCHBAR_CH1_CR_TC_SRFTP_tZQOPER_WID                           (10)
+  #define MCHBAR_CH1_CR_TC_SRFTP_tZQOPER_MSK                           (0x03FF0000)
+  #define MCHBAR_CH1_CR_TC_SRFTP_tZQOPER_MAX                           (0x000003FF)
+  #define MCHBAR_CH1_CR_TC_SRFTP_tZQOPER_DEF                           (0x00000100)
+  #define MCHBAR_CH1_CR_TC_SRFTP_tMOD_OFF                              (28)
+  #define MCHBAR_CH1_CR_TC_SRFTP_tMOD_WID                              ( 4)
+  #define MCHBAR_CH1_CR_TC_SRFTP_tMOD_MSK                              (0xF0000000)
+  #define MCHBAR_CH1_CR_TC_SRFTP_tMOD_MAX                              (0x0000000F)
+  #define MCHBAR_CH1_CR_TC_SRFTP_tMOD_DEF                              (0x00000000)
+
+#define MCHBAR_CH1_CR_WDB_VISA_SEL_REG                               (0x000046A8)
+  #define MCHBAR_CH1_CR_WDB_VISA_SEL_VISAByteSel_OFF                   ( 0)
+  #define MCHBAR_CH1_CR_WDB_VISA_SEL_VISAByteSel_WID                   ( 3)
+  #define MCHBAR_CH1_CR_WDB_VISA_SEL_VISAByteSel_MSK                   (0x00000007)
+  #define MCHBAR_CH1_CR_WDB_VISA_SEL_VISAByteSel_MAX                   (0x00000007)
+  #define MCHBAR_CH1_CR_WDB_VISA_SEL_VISAByteSel_DEF                   (0x00000000)
+
+#define MCHBAR_CH1_CR_DCLK_LDAT_PDAT_REG                             (0x000046C0)
+  #define MCHBAR_CH1_CR_DCLK_LDAT_PDAT_FASTADDR_OFF                    ( 0)
+  #define MCHBAR_CH1_CR_DCLK_LDAT_PDAT_FASTADDR_WID                    (12)
+  #define MCHBAR_CH1_CR_DCLK_LDAT_PDAT_FASTADDR_MSK                    (0x00000FFF)
+  #define MCHBAR_CH1_CR_DCLK_LDAT_PDAT_FASTADDR_MAX                    (0x00000FFF)
+  #define MCHBAR_CH1_CR_DCLK_LDAT_PDAT_FASTADDR_DEF                    (0x00000000)
+  #define MCHBAR_CH1_CR_DCLK_LDAT_PDAT_ADDREN_OFF                      (16)
+  #define MCHBAR_CH1_CR_DCLK_LDAT_PDAT_ADDREN_WID                      ( 1)
+  #define MCHBAR_CH1_CR_DCLK_LDAT_PDAT_ADDREN_MSK                      (0x00010000)
+  #define MCHBAR_CH1_CR_DCLK_LDAT_PDAT_ADDREN_MAX                      (0x00000001)
+  #define MCHBAR_CH1_CR_DCLK_LDAT_PDAT_ADDREN_DEF                      (0x00000000)
+  #define MCHBAR_CH1_CR_DCLK_LDAT_PDAT_SEQEN_OFF                       (17)
+  #define MCHBAR_CH1_CR_DCLK_LDAT_PDAT_SEQEN_WID                       ( 1)
+  #define MCHBAR_CH1_CR_DCLK_LDAT_PDAT_SEQEN_MSK                       (0x00020000)
+  #define MCHBAR_CH1_CR_DCLK_LDAT_PDAT_SEQEN_MAX                       (0x00000001)
+  #define MCHBAR_CH1_CR_DCLK_LDAT_PDAT_SEQEN_DEF                       (0x00000000)
+  #define MCHBAR_CH1_CR_DCLK_LDAT_PDAT_POL0_OFF                        (18)
+  #define MCHBAR_CH1_CR_DCLK_LDAT_PDAT_POL0_WID                        ( 1)
+  #define MCHBAR_CH1_CR_DCLK_LDAT_PDAT_POL0_MSK                        (0x00040000)
+  #define MCHBAR_CH1_CR_DCLK_LDAT_PDAT_POL0_MAX                        (0x00000001)
+  #define MCHBAR_CH1_CR_DCLK_LDAT_PDAT_POL0_DEF                        (0x00000000)
+  #define MCHBAR_CH1_CR_DCLK_LDAT_PDAT_POL1_OFF                        (19)
+  #define MCHBAR_CH1_CR_DCLK_LDAT_PDAT_POL1_WID                        ( 1)
+  #define MCHBAR_CH1_CR_DCLK_LDAT_PDAT_POL1_MSK                        (0x00080000)
+  #define MCHBAR_CH1_CR_DCLK_LDAT_PDAT_POL1_MAX                        (0x00000001)
+  #define MCHBAR_CH1_CR_DCLK_LDAT_PDAT_POL1_DEF                        (0x00000000)
+  #define MCHBAR_CH1_CR_DCLK_LDAT_PDAT_CMDA_OFF                        (20)
+  #define MCHBAR_CH1_CR_DCLK_LDAT_PDAT_CMDA_WID                        ( 4)
+  #define MCHBAR_CH1_CR_DCLK_LDAT_PDAT_CMDA_MSK                        (0x00F00000)
+  #define MCHBAR_CH1_CR_DCLK_LDAT_PDAT_CMDA_MAX                        (0x0000000F)
+  #define MCHBAR_CH1_CR_DCLK_LDAT_PDAT_CMDA_DEF                        (0x00000000)
+  #define MCHBAR_CH1_CR_DCLK_LDAT_PDAT_CMDB_OFF                        (24)
+  #define MCHBAR_CH1_CR_DCLK_LDAT_PDAT_CMDB_WID                        ( 4)
+  #define MCHBAR_CH1_CR_DCLK_LDAT_PDAT_CMDB_MSK                        (0x0F000000)
+  #define MCHBAR_CH1_CR_DCLK_LDAT_PDAT_CMDB_MAX                        (0x0000000F)
+  #define MCHBAR_CH1_CR_DCLK_LDAT_PDAT_CMDB_DEF                        (0x00000000)
+  #define MCHBAR_CH1_CR_DCLK_LDAT_PDAT_CMDC_OFF                        (28)
+  #define MCHBAR_CH1_CR_DCLK_LDAT_PDAT_CMDC_WID                        ( 4)
+  #define MCHBAR_CH1_CR_DCLK_LDAT_PDAT_CMDC_MSK                        (0xF0000000)
+  #define MCHBAR_CH1_CR_DCLK_LDAT_PDAT_CMDC_MAX                        (0x0000000F)
+  #define MCHBAR_CH1_CR_DCLK_LDAT_PDAT_CMDC_DEF                        (0x00000000)
+
+#define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_REG                             (0x000046C4)
+  #define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_BANKSEL_OFF                     ( 0)
+  #define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_BANKSEL_WID                     ( 4)
+  #define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_BANKSEL_MSK                     (0x0000000F)
+  #define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_BANKSEL_MAX                     (0x0000000F)
+  #define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_BANKSEL_DEF                     (0x00000000)
+  #define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_ARRAYSEL_OFF                    ( 5)
+  #define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_ARRAYSEL_WID                    ( 5)
+  #define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_ARRAYSEL_MSK                    (0x000003E0)
+  #define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_ARRAYSEL_MAX                    (0x0000001F)
+  #define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_ARRAYSEL_DEF                    (0x00000000)
+  #define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_CMP_OFF                         (10)
+  #define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_CMP_WID                         ( 1)
+  #define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_CMP_MSK                         (0x00000400)
+  #define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_CMP_MAX                         (0x00000001)
+  #define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_CMP_DEF                         (0x00000000)
+  #define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_REP_OFF                         (11)
+  #define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_REP_WID                         ( 1)
+  #define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_REP_MSK                         (0x00000800)
+  #define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_REP_MAX                         (0x00000001)
+  #define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_REP_DEF                         (0x00000000)
+  #define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_DWORD_OFF                       (12)
+  #define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_DWORD_WID                       ( 4)
+  #define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_DWORD_MSK                       (0x0000F000)
+  #define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_DWORD_MAX                       (0x0000000F)
+  #define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_DWORD_DEF                       (0x00000000)
+  #define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_MODE_OFF                        (16)
+  #define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_MODE_WID                        ( 2)
+  #define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_MODE_MSK                        (0x00030000)
+  #define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_MODE_MAX                        (0x00000003)
+  #define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_MODE_DEF                        (0x00000000)
+  #define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_MPMAP_OFF                       (18)
+  #define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_MPMAP_WID                       ( 6)
+  #define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_MPMAP_MSK                       (0x00FC0000)
+  #define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_MPMAP_MAX                       (0x0000003F)
+  #define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_MPMAP_DEF                       (0x00000000)
+  #define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_MPBOFFSET_OFF                   (24)
+  #define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_MPBOFFSET_WID                   ( 4)
+  #define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_MPBOFFSET_MSK                   (0x0F000000)
+  #define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_MPBOFFSET_MAX                   (0x0000000F)
+  #define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_MPBOFFSET_DEF                   (0x00000000)
+  #define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_STAGE_EN_OFF                    (28)
+  #define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_STAGE_EN_WID                    ( 1)
+  #define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_STAGE_EN_MSK                    (0x10000000)
+  #define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_STAGE_EN_MAX                    (0x00000001)
+  #define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_STAGE_EN_DEF                    (0x00000000)
+  #define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_SHADOW_OFF                      (29)
+  #define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_SHADOW_WID                      ( 2)
+  #define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_SHADOW_MSK                      (0x60000000)
+  #define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_SHADOW_MAX                      (0x00000003)
+  #define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_SHADOW_DEF                      (0x00000000)
+
+#define MCHBAR_CH1_CR_DCLK_LDAT_DATAOUT_REG                          (0x000046C8)
+  #define MCHBAR_CH1_CR_DCLK_LDAT_DATAOUT_DATOUT_OFF                   ( 0)
+  #define MCHBAR_CH1_CR_DCLK_LDAT_DATAOUT_DATOUT_WID                   (32)
+  #define MCHBAR_CH1_CR_DCLK_LDAT_DATAOUT_DATOUT_MSK                   (0xFFFFFFFF)
+  #define MCHBAR_CH1_CR_DCLK_LDAT_DATAOUT_DATOUT_MAX                   (0xFFFFFFFF)
+  #define MCHBAR_CH1_CR_DCLK_LDAT_DATAOUT_DATOUT_DEF                   (0x00000000)
+
+#define MCHBAR_CH1_CR_DCLK_LDAT_DATAIN_0_REG                         (0x000046CC)
+  #define MCHBAR_CH1_CR_DCLK_LDAT_DATAIN_0_DATIN_OFF                   ( 0)
+  #define MCHBAR_CH1_CR_DCLK_LDAT_DATAIN_0_DATIN_WID                   (32)
+  #define MCHBAR_CH1_CR_DCLK_LDAT_DATAIN_0_DATIN_MSK                   (0xFFFFFFFF)
+  #define MCHBAR_CH1_CR_DCLK_LDAT_DATAIN_0_DATIN_MAX                   (0xFFFFFFFF)
+  #define MCHBAR_CH1_CR_DCLK_LDAT_DATAIN_0_DATIN_DEF                   (0x00000000)
+
+#define MCHBAR_CH1_CR_QCLK_LDAT_PDAT_REG                             (0x000046D0)
+  #define MCHBAR_CH1_CR_QCLK_LDAT_PDAT_FASTADDR_OFF                    ( 0)
+  #define MCHBAR_CH1_CR_QCLK_LDAT_PDAT_FASTADDR_WID                    (12)
+  #define MCHBAR_CH1_CR_QCLK_LDAT_PDAT_FASTADDR_MSK                    (0x00000FFF)
+  #define MCHBAR_CH1_CR_QCLK_LDAT_PDAT_FASTADDR_MAX                    (0x00000FFF)
+  #define MCHBAR_CH1_CR_QCLK_LDAT_PDAT_FASTADDR_DEF                    (0x00000000)
+  #define MCHBAR_CH1_CR_QCLK_LDAT_PDAT_ADDREN_OFF                      (16)
+  #define MCHBAR_CH1_CR_QCLK_LDAT_PDAT_ADDREN_WID                      ( 1)
+  #define MCHBAR_CH1_CR_QCLK_LDAT_PDAT_ADDREN_MSK                      (0x00010000)
+  #define MCHBAR_CH1_CR_QCLK_LDAT_PDAT_ADDREN_MAX                      (0x00000001)
+  #define MCHBAR_CH1_CR_QCLK_LDAT_PDAT_ADDREN_DEF                      (0x00000000)
+  #define MCHBAR_CH1_CR_QCLK_LDAT_PDAT_SEQEN_OFF                       (17)
+  #define MCHBAR_CH1_CR_QCLK_LDAT_PDAT_SEQEN_WID                       ( 1)
+  #define MCHBAR_CH1_CR_QCLK_LDAT_PDAT_SEQEN_MSK                       (0x00020000)
+  #define MCHBAR_CH1_CR_QCLK_LDAT_PDAT_SEQEN_MAX                       (0x00000001)
+  #define MCHBAR_CH1_CR_QCLK_LDAT_PDAT_SEQEN_DEF                       (0x00000000)
+  #define MCHBAR_CH1_CR_QCLK_LDAT_PDAT_POL0_OFF                        (18)
+  #define MCHBAR_CH1_CR_QCLK_LDAT_PDAT_POL0_WID                        ( 1)
+  #define MCHBAR_CH1_CR_QCLK_LDAT_PDAT_POL0_MSK                        (0x00040000)
+  #define MCHBAR_CH1_CR_QCLK_LDAT_PDAT_POL0_MAX                        (0x00000001)
+  #define MCHBAR_CH1_CR_QCLK_LDAT_PDAT_POL0_DEF                        (0x00000000)
+  #define MCHBAR_CH1_CR_QCLK_LDAT_PDAT_POL1_OFF                        (19)
+  #define MCHBAR_CH1_CR_QCLK_LDAT_PDAT_POL1_WID                        ( 1)
+  #define MCHBAR_CH1_CR_QCLK_LDAT_PDAT_POL1_MSK                        (0x00080000)
+  #define MCHBAR_CH1_CR_QCLK_LDAT_PDAT_POL1_MAX                        (0x00000001)
+  #define MCHBAR_CH1_CR_QCLK_LDAT_PDAT_POL1_DEF                        (0x00000000)
+  #define MCHBAR_CH1_CR_QCLK_LDAT_PDAT_CMDA_OFF                        (20)
+  #define MCHBAR_CH1_CR_QCLK_LDAT_PDAT_CMDA_WID                        ( 4)
+  #define MCHBAR_CH1_CR_QCLK_LDAT_PDAT_CMDA_MSK                        (0x00F00000)
+  #define MCHBAR_CH1_CR_QCLK_LDAT_PDAT_CMDA_MAX                        (0x0000000F)
+  #define MCHBAR_CH1_CR_QCLK_LDAT_PDAT_CMDA_DEF                        (0x00000000)
+  #define MCHBAR_CH1_CR_QCLK_LDAT_PDAT_CMDB_OFF                        (24)
+  #define MCHBAR_CH1_CR_QCLK_LDAT_PDAT_CMDB_WID                        ( 4)
+  #define MCHBAR_CH1_CR_QCLK_LDAT_PDAT_CMDB_MSK                        (0x0F000000)
+  #define MCHBAR_CH1_CR_QCLK_LDAT_PDAT_CMDB_MAX                        (0x0000000F)
+  #define MCHBAR_CH1_CR_QCLK_LDAT_PDAT_CMDB_DEF                        (0x00000000)
+  #define MCHBAR_CH1_CR_QCLK_LDAT_PDAT_CMDC_OFF                        (28)
+  #define MCHBAR_CH1_CR_QCLK_LDAT_PDAT_CMDC_WID                        ( 4)
+  #define MCHBAR_CH1_CR_QCLK_LDAT_PDAT_CMDC_MSK                        (0xF0000000)
+  #define MCHBAR_CH1_CR_QCLK_LDAT_PDAT_CMDC_MAX                        (0x0000000F)
+  #define MCHBAR_CH1_CR_QCLK_LDAT_PDAT_CMDC_DEF                        (0x00000000)
+
+#define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_REG                             (0x000046D4)
+  #define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_BANKSEL_OFF                     ( 0)
+  #define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_BANKSEL_WID                     ( 4)
+  #define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_BANKSEL_MSK                     (0x0000000F)
+  #define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_BANKSEL_MAX                     (0x0000000F)
+  #define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_BANKSEL_DEF                     (0x00000000)
+  #define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_ARRAYSEL_OFF                    ( 5)
+  #define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_ARRAYSEL_WID                    ( 5)
+  #define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_ARRAYSEL_MSK                    (0x000003E0)
+  #define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_ARRAYSEL_MAX                    (0x0000001F)
+  #define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_ARRAYSEL_DEF                    (0x00000000)
+  #define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_CMP_OFF                         (10)
+  #define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_CMP_WID                         ( 1)
+  #define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_CMP_MSK                         (0x00000400)
+  #define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_CMP_MAX                         (0x00000001)
+  #define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_CMP_DEF                         (0x00000000)
+  #define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_REP_OFF                         (11)
+  #define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_REP_WID                         ( 1)
+  #define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_REP_MSK                         (0x00000800)
+  #define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_REP_MAX                         (0x00000001)
+  #define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_REP_DEF                         (0x00000000)
+  #define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_DWORD_OFF                       (12)
+  #define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_DWORD_WID                       ( 4)
+  #define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_DWORD_MSK                       (0x0000F000)
+  #define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_DWORD_MAX                       (0x0000000F)
+  #define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_DWORD_DEF                       (0x00000000)
+  #define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_MODE_OFF                        (16)
+  #define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_MODE_WID                        ( 2)
+  #define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_MODE_MSK                        (0x00030000)
+  #define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_MODE_MAX                        (0x00000003)
+  #define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_MODE_DEF                        (0x00000000)
+  #define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_MPMAP_OFF                       (18)
+  #define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_MPMAP_WID                       ( 6)
+  #define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_MPMAP_MSK                       (0x00FC0000)
+  #define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_MPMAP_MAX                       (0x0000003F)
+  #define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_MPMAP_DEF                       (0x00000000)
+  #define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_MPBOFFSET_OFF                   (24)
+  #define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_MPBOFFSET_WID                   ( 4)
+  #define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_MPBOFFSET_MSK                   (0x0F000000)
+  #define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_MPBOFFSET_MAX                   (0x0000000F)
+  #define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_MPBOFFSET_DEF                   (0x00000000)
+  #define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_STAGE_EN_OFF                    (28)
+  #define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_STAGE_EN_WID                    ( 1)
+  #define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_STAGE_EN_MSK                    (0x10000000)
+  #define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_STAGE_EN_MAX                    (0x00000001)
+  #define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_STAGE_EN_DEF                    (0x00000000)
+  #define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_SHADOW_OFF                      (29)
+  #define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_SHADOW_WID                      ( 2)
+  #define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_SHADOW_MSK                      (0x60000000)
+  #define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_SHADOW_MAX                      (0x00000003)
+  #define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_SHADOW_DEF                      (0x00000000)
+
+#define MCHBAR_CH1_CR_QCLK_LDAT_DATAOUT_REG                          (0x000046D8)
+  #define MCHBAR_CH1_CR_QCLK_LDAT_DATAOUT_DATOUT_OFF                   ( 0)
+  #define MCHBAR_CH1_CR_QCLK_LDAT_DATAOUT_DATOUT_WID                   (32)
+  #define MCHBAR_CH1_CR_QCLK_LDAT_DATAOUT_DATOUT_MSK                   (0xFFFFFFFF)
+  #define MCHBAR_CH1_CR_QCLK_LDAT_DATAOUT_DATOUT_MAX                   (0xFFFFFFFF)
+  #define MCHBAR_CH1_CR_QCLK_LDAT_DATAOUT_DATOUT_DEF                   (0x00000000)
+
+#define MCHBAR_CH1_CR_QCLK_LDAT_DATAIN_0_REG                         (0x000046DC)
+  #define MCHBAR_CH1_CR_QCLK_LDAT_DATAIN_0_DATIN_OFF                   ( 0)
+  #define MCHBAR_CH1_CR_QCLK_LDAT_DATAIN_0_DATIN_WID                   (32)
+  #define MCHBAR_CH1_CR_QCLK_LDAT_DATAIN_0_DATIN_MSK                   (0xFFFFFFFF)
+  #define MCHBAR_CH1_CR_QCLK_LDAT_DATAIN_0_DATIN_MAX                   (0xFFFFFFFF)
+  #define MCHBAR_CH1_CR_QCLK_LDAT_DATAIN_0_DATIN_DEF                   (0x00000000)
+
+#define MCHBAR_CH1_CR_QCLK_LDAT_DATAIN_1_REG                         (0x000046E0)
+  #define MCHBAR_CH1_CR_QCLK_LDAT_DATAIN_1_DATIN_OFF                   ( 0)
+  #define MCHBAR_CH1_CR_QCLK_LDAT_DATAIN_1_DATIN_WID                   (32)
+  #define MCHBAR_CH1_CR_QCLK_LDAT_DATAIN_1_DATIN_MSK                   (0xFFFFFFFF)
+  #define MCHBAR_CH1_CR_QCLK_LDAT_DATAIN_1_DATIN_MAX                   (0xFFFFFFFF)
+  #define MCHBAR_CH1_CR_QCLK_LDAT_DATAIN_1_DATIN_DEF                   (0x00000000)
+
+#define MCHBAR_CH1_CR_QUEUE_ENTRY_DISABLE_RPQ_REG                    (0x000046E4)
+  #define MCHBAR_CH1_CR_QUEUE_ENTRY_DISABLE_RPQ_RPQ_disable_OFF        ( 0)
+  #define MCHBAR_CH1_CR_QUEUE_ENTRY_DISABLE_RPQ_RPQ_disable_WID        (28)
+  #define MCHBAR_CH1_CR_QUEUE_ENTRY_DISABLE_RPQ_RPQ_disable_MSK        (0x0FFFFFFF)
+  #define MCHBAR_CH1_CR_QUEUE_ENTRY_DISABLE_RPQ_RPQ_disable_MAX        (0x0FFFFFFF)
+  #define MCHBAR_CH1_CR_QUEUE_ENTRY_DISABLE_RPQ_RPQ_disable_DEF        (0x00000000)
+
+#define MCHBAR_CH1_CR_QUEUE_ENTRY_DISABLE_WPQ_REG                    (0x000046E8)
+  #define MCHBAR_CH1_CR_QUEUE_ENTRY_DISABLE_WPQ_WPQ_disable_OFF        ( 0)
+  #define MCHBAR_CH1_CR_QUEUE_ENTRY_DISABLE_WPQ_WPQ_disable_WID        (32)
+  #define MCHBAR_CH1_CR_QUEUE_ENTRY_DISABLE_WPQ_WPQ_disable_MSK        (0xFFFFFFFF)
+  #define MCHBAR_CH1_CR_QUEUE_ENTRY_DISABLE_WPQ_WPQ_disable_MAX        (0xFFFFFFFF)
+  #define MCHBAR_CH1_CR_QUEUE_ENTRY_DISABLE_WPQ_WPQ_disable_DEF        (0x00000000)
+
+#define MCHBAR_CH1_CR_PM_DIMM_IDLE_ENERGY_REG                        (0x000046EC)
+  #define MCHBAR_CH1_CR_PM_DIMM_IDLE_ENERGY_DIMM0_IDLE_ENERGY_OFF      ( 0)
+  #define MCHBAR_CH1_CR_PM_DIMM_IDLE_ENERGY_DIMM0_IDLE_ENERGY_WID      ( 6)
+  #define MCHBAR_CH1_CR_PM_DIMM_IDLE_ENERGY_DIMM0_IDLE_ENERGY_MSK      (0x0000003F)
+  #define MCHBAR_CH1_CR_PM_DIMM_IDLE_ENERGY_DIMM0_IDLE_ENERGY_MAX      (0x0000003F)
+  #define MCHBAR_CH1_CR_PM_DIMM_IDLE_ENERGY_DIMM0_IDLE_ENERGY_DEF      (0x00000000)
+  #define MCHBAR_CH1_CR_PM_DIMM_IDLE_ENERGY_DIMM1_IDLE_ENERGY_OFF      ( 8)
+  #define MCHBAR_CH1_CR_PM_DIMM_IDLE_ENERGY_DIMM1_IDLE_ENERGY_WID      ( 6)
+  #define MCHBAR_CH1_CR_PM_DIMM_IDLE_ENERGY_DIMM1_IDLE_ENERGY_MSK      (0x00003F00)
+  #define MCHBAR_CH1_CR_PM_DIMM_IDLE_ENERGY_DIMM1_IDLE_ENERGY_MAX      (0x0000003F)
+  #define MCHBAR_CH1_CR_PM_DIMM_IDLE_ENERGY_DIMM1_IDLE_ENERGY_DEF      (0x00000000)
+
+#define MCHBAR_CH1_CR_PM_DIMM_PD_ENERGY_REG                          (0x000046F0)
+  #define MCHBAR_CH1_CR_PM_DIMM_PD_ENERGY_DIMM0_PD_ENERGY_OFF          ( 0)
+  #define MCHBAR_CH1_CR_PM_DIMM_PD_ENERGY_DIMM0_PD_ENERGY_WID          ( 6)
+  #define MCHBAR_CH1_CR_PM_DIMM_PD_ENERGY_DIMM0_PD_ENERGY_MSK          (0x0000003F)
+  #define MCHBAR_CH1_CR_PM_DIMM_PD_ENERGY_DIMM0_PD_ENERGY_MAX          (0x0000003F)
+  #define MCHBAR_CH1_CR_PM_DIMM_PD_ENERGY_DIMM0_PD_ENERGY_DEF          (0x00000000)
+  #define MCHBAR_CH1_CR_PM_DIMM_PD_ENERGY_DIMM1_PD_ENERGY_OFF          ( 8)
+  #define MCHBAR_CH1_CR_PM_DIMM_PD_ENERGY_DIMM1_PD_ENERGY_WID          ( 6)
+  #define MCHBAR_CH1_CR_PM_DIMM_PD_ENERGY_DIMM1_PD_ENERGY_MSK          (0x00003F00)
+  #define MCHBAR_CH1_CR_PM_DIMM_PD_ENERGY_DIMM1_PD_ENERGY_MAX          (0x0000003F)
+  #define MCHBAR_CH1_CR_PM_DIMM_PD_ENERGY_DIMM1_PD_ENERGY_DEF          (0x00000000)
+
+#define MCHBAR_CH1_CR_PM_DIMM_ACT_ENERGY_REG                         (0x000046F4)
+  #define MCHBAR_CH1_CR_PM_DIMM_ACT_ENERGY_DIMM0_ACT_ENERGY_OFF        ( 0)
+  #define MCHBAR_CH1_CR_PM_DIMM_ACT_ENERGY_DIMM0_ACT_ENERGY_WID        ( 8)
+  #define MCHBAR_CH1_CR_PM_DIMM_ACT_ENERGY_DIMM0_ACT_ENERGY_MSK        (0x000000FF)
+  #define MCHBAR_CH1_CR_PM_DIMM_ACT_ENERGY_DIMM0_ACT_ENERGY_MAX        (0x000000FF)
+  #define MCHBAR_CH1_CR_PM_DIMM_ACT_ENERGY_DIMM0_ACT_ENERGY_DEF        (0x00000000)
+  #define MCHBAR_CH1_CR_PM_DIMM_ACT_ENERGY_DIMM1_ACT_ENERGY_OFF        ( 8)
+  #define MCHBAR_CH1_CR_PM_DIMM_ACT_ENERGY_DIMM1_ACT_ENERGY_WID        ( 8)
+  #define MCHBAR_CH1_CR_PM_DIMM_ACT_ENERGY_DIMM1_ACT_ENERGY_MSK        (0x0000FF00)
+  #define MCHBAR_CH1_CR_PM_DIMM_ACT_ENERGY_DIMM1_ACT_ENERGY_MAX        (0x000000FF)
+  #define MCHBAR_CH1_CR_PM_DIMM_ACT_ENERGY_DIMM1_ACT_ENERGY_DEF        (0x00000000)
+
+#define MCHBAR_CH1_CR_PM_DIMM_RD_ENERGY_REG                          (0x000046F8)
+  #define MCHBAR_CH1_CR_PM_DIMM_RD_ENERGY_DIMM0_RD_ENERGY_OFF          ( 0)
+  #define MCHBAR_CH1_CR_PM_DIMM_RD_ENERGY_DIMM0_RD_ENERGY_WID          ( 8)
+  #define MCHBAR_CH1_CR_PM_DIMM_RD_ENERGY_DIMM0_RD_ENERGY_MSK          (0x000000FF)
+  #define MCHBAR_CH1_CR_PM_DIMM_RD_ENERGY_DIMM0_RD_ENERGY_MAX          (0x000000FF)
+  #define MCHBAR_CH1_CR_PM_DIMM_RD_ENERGY_DIMM0_RD_ENERGY_DEF          (0x00000000)
+  #define MCHBAR_CH1_CR_PM_DIMM_RD_ENERGY_DIMM1_RD_ENERGY_OFF          ( 8)
+  #define MCHBAR_CH1_CR_PM_DIMM_RD_ENERGY_DIMM1_RD_ENERGY_WID          ( 8)
+  #define MCHBAR_CH1_CR_PM_DIMM_RD_ENERGY_DIMM1_RD_ENERGY_MSK          (0x0000FF00)
+  #define MCHBAR_CH1_CR_PM_DIMM_RD_ENERGY_DIMM1_RD_ENERGY_MAX          (0x000000FF)
+  #define MCHBAR_CH1_CR_PM_DIMM_RD_ENERGY_DIMM1_RD_ENERGY_DEF          (0x00000000)
+
+#define MCHBAR_CH1_CR_PM_DIMM_WR_ENERGY_REG                          (0x000046FC)
+  #define MCHBAR_CH1_CR_PM_DIMM_WR_ENERGY_DIMM0_WR_ENERGY_OFF          ( 0)
+  #define MCHBAR_CH1_CR_PM_DIMM_WR_ENERGY_DIMM0_WR_ENERGY_WID          ( 8)
+  #define MCHBAR_CH1_CR_PM_DIMM_WR_ENERGY_DIMM0_WR_ENERGY_MSK          (0x000000FF)
+  #define MCHBAR_CH1_CR_PM_DIMM_WR_ENERGY_DIMM0_WR_ENERGY_MAX          (0x000000FF)
+  #define MCHBAR_CH1_CR_PM_DIMM_WR_ENERGY_DIMM0_WR_ENERGY_DEF          (0x00000000)
+  #define MCHBAR_CH1_CR_PM_DIMM_WR_ENERGY_DIMM1_WR_ENERGY_OFF          ( 8)
+  #define MCHBAR_CH1_CR_PM_DIMM_WR_ENERGY_DIMM1_WR_ENERGY_WID          ( 8)
+  #define MCHBAR_CH1_CR_PM_DIMM_WR_ENERGY_DIMM1_WR_ENERGY_MSK          (0x0000FF00)
+  #define MCHBAR_CH1_CR_PM_DIMM_WR_ENERGY_DIMM1_WR_ENERGY_MAX          (0x000000FF)
+  #define MCHBAR_CH1_CR_PM_DIMM_WR_ENERGY_DIMM1_WR_ENERGY_DEF          (0x00000000)
+
+#define MCHBAR_CH1_CR_PM_THRT_CKE_MIN_REG                            (0x00004728)
+  #define MCHBAR_CH1_CR_PM_THRT_CKE_MIN_CKE_MIN_OFF                    ( 0)
+  #define MCHBAR_CH1_CR_PM_THRT_CKE_MIN_CKE_MIN_WID                    ( 8)
+  #define MCHBAR_CH1_CR_PM_THRT_CKE_MIN_CKE_MIN_MSK                    (0x000000FF)
+  #define MCHBAR_CH1_CR_PM_THRT_CKE_MIN_CKE_MIN_MAX                    (0x000000FF)
+  #define MCHBAR_CH1_CR_PM_THRT_CKE_MIN_CKE_MIN_DEF                    (0x00000000)
+  #define MCHBAR_CH1_CR_PM_THRT_CKE_MIN_CKE_MIN_DEFEATURE_OFF          ( 8)
+  #define MCHBAR_CH1_CR_PM_THRT_CKE_MIN_CKE_MIN_DEFEATURE_WID          ( 1)
+  #define MCHBAR_CH1_CR_PM_THRT_CKE_MIN_CKE_MIN_DEFEATURE_MSK          (0x00000100)
+  #define MCHBAR_CH1_CR_PM_THRT_CKE_MIN_CKE_MIN_DEFEATURE_MAX          (0x00000001)
+  #define MCHBAR_CH1_CR_PM_THRT_CKE_MIN_CKE_MIN_DEFEATURE_DEF          (0x00000000)
+
+#define MCHBAR_CH1_CR_ODLAT_CMD_MATCH0_REG                           (0x00004740)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH0_ODT_OFF                       ( 0)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH0_ODT_WID                       ( 4)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH0_ODT_MSK                       (0x0000000F)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH0_ODT_MAX                       (0x0000000F)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH0_ODT_DEF                       (0x00000000)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH0_Web_OFF                       ( 4)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH0_Web_WID                       ( 1)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH0_Web_MSK                       (0x00000010)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH0_Web_MAX                       (0x00000001)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH0_Web_DEF                       (0x00000000)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH0_CASb_OFF                      ( 5)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH0_CASb_WID                      ( 1)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH0_CASb_MSK                      (0x00000020)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH0_CASb_MAX                      (0x00000001)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH0_CASb_DEF                      (0x00000000)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH0_RASb_OFF                      ( 6)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH0_RASb_WID                      ( 1)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH0_RASb_MSK                      (0x00000040)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH0_RASb_MAX                      (0x00000001)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH0_RASb_DEF                      (0x00000000)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH0_CSb_OFF                       ( 7)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH0_CSb_WID                       ( 4)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH0_CSb_MSK                       (0x00000780)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH0_CSb_MAX                       (0x0000000F)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH0_CSb_DEF                       (0x00000000)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH0_CKE_OFF                       (11)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH0_CKE_WID                       ( 4)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH0_CKE_MSK                       (0x00007800)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH0_CKE_MAX                       (0x0000000F)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH0_CKE_DEF                       (0x00000000)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH0_MA_OFF                        (15)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH0_MA_WID                        (16)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH0_MA_MSK                        (0x7FFF8000)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH0_MA_MAX                        (0x0000FFFF)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH0_MA_DEF                        (0x00000000)
+
+#define MCHBAR_CH1_CR_ODLAT_CMD_MATCH1_REG                           (0x00004744)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH1_ODT_OFF                       ( 0)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH1_ODT_WID                       ( 4)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH1_ODT_MSK                       (0x0000000F)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH1_ODT_MAX                       (0x0000000F)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH1_ODT_DEF                       (0x00000000)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH1_Web_OFF                       ( 4)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH1_Web_WID                       ( 1)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH1_Web_MSK                       (0x00000010)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH1_Web_MAX                       (0x00000001)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH1_Web_DEF                       (0x00000000)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH1_CASb_OFF                      ( 5)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH1_CASb_WID                      ( 1)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH1_CASb_MSK                      (0x00000020)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH1_CASb_MAX                      (0x00000001)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH1_CASb_DEF                      (0x00000000)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH1_RASb_OFF                      ( 6)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH1_RASb_WID                      ( 1)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH1_RASb_MSK                      (0x00000040)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH1_RASb_MAX                      (0x00000001)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH1_RASb_DEF                      (0x00000000)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH1_CSb_OFF                       ( 7)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH1_CSb_WID                       ( 4)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH1_CSb_MSK                       (0x00000780)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH1_CSb_MAX                       (0x0000000F)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH1_CSb_DEF                       (0x00000000)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH1_CKE_OFF                       (11)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH1_CKE_WID                       ( 4)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH1_CKE_MSK                       (0x00007800)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH1_CKE_MAX                       (0x0000000F)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH1_CKE_DEF                       (0x00000000)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH1_MA_OFF                        (15)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH1_MA_WID                        (16)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH1_MA_MSK                        (0x7FFF8000)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH1_MA_MAX                        (0x0000FFFF)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH1_MA_DEF                        (0x00000000)
+
+#define MCHBAR_CH1_CR_ODLAT_CMD_MATCH2_REG                           (0x00004748)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH2_ODT_OFF                       ( 0)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH2_ODT_WID                       ( 4)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH2_ODT_MSK                       (0x0000000F)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH2_ODT_MAX                       (0x0000000F)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH2_ODT_DEF                       (0x00000000)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH2_Web_OFF                       ( 4)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH2_Web_WID                       ( 1)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH2_Web_MSK                       (0x00000010)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH2_Web_MAX                       (0x00000001)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH2_Web_DEF                       (0x00000000)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH2_CASb_OFF                      ( 5)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH2_CASb_WID                      ( 1)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH2_CASb_MSK                      (0x00000020)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH2_CASb_MAX                      (0x00000001)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH2_CASb_DEF                      (0x00000000)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH2_RASb_OFF                      ( 6)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH2_RASb_WID                      ( 1)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH2_RASb_MSK                      (0x00000040)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH2_RASb_MAX                      (0x00000001)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH2_RASb_DEF                      (0x00000000)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH2_CSb_OFF                       ( 7)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH2_CSb_WID                       ( 4)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH2_CSb_MSK                       (0x00000780)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH2_CSb_MAX                       (0x0000000F)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH2_CSb_DEF                       (0x00000000)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH2_CKE_OFF                       (11)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH2_CKE_WID                       ( 4)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH2_CKE_MSK                       (0x00007800)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH2_CKE_MAX                       (0x0000000F)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH2_CKE_DEF                       (0x00000000)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH2_MA_OFF                        (15)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH2_MA_WID                        (16)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH2_MA_MSK                        (0x7FFF8000)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH2_MA_MAX                        (0x0000FFFF)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH2_MA_DEF                        (0x00000000)
+
+#define MCHBAR_CH1_CR_ODLAT_CMD_MATCH3_REG                           (0x0000474C)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH3_ODT_OFF                       ( 0)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH3_ODT_WID                       ( 4)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH3_ODT_MSK                       (0x0000000F)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH3_ODT_MAX                       (0x0000000F)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH3_ODT_DEF                       (0x00000000)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH3_Web_OFF                       ( 4)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH3_Web_WID                       ( 1)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH3_Web_MSK                       (0x00000010)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH3_Web_MAX                       (0x00000001)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH3_Web_DEF                       (0x00000000)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH3_CASb_OFF                      ( 5)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH3_CASb_WID                      ( 1)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH3_CASb_MSK                      (0x00000020)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH3_CASb_MAX                      (0x00000001)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH3_CASb_DEF                      (0x00000000)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH3_RASb_OFF                      ( 6)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH3_RASb_WID                      ( 1)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH3_RASb_MSK                      (0x00000040)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH3_RASb_MAX                      (0x00000001)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH3_RASb_DEF                      (0x00000000)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH3_CSb_OFF                       ( 7)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH3_CSb_WID                       ( 4)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH3_CSb_MSK                       (0x00000780)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH3_CSb_MAX                       (0x0000000F)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH3_CSb_DEF                       (0x00000000)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH3_CKE_OFF                       (11)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH3_CKE_WID                       ( 4)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH3_CKE_MSK                       (0x00007800)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH3_CKE_MAX                       (0x0000000F)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH3_CKE_DEF                       (0x00000000)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH3_MA_OFF                        (15)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH3_MA_WID                        (16)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH3_MA_MSK                        (0x7FFF8000)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH3_MA_MAX                        (0x0000FFFF)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH3_MA_DEF                        (0x00000000)
+
+#define MCHBAR_CH1_CR_ODLAT_CMD_MASK0_REG                            (0x00004750)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MASK0_ODT_OFF                        ( 0)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MASK0_ODT_WID                        ( 4)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MASK0_ODT_MSK                        (0x0000000F)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MASK0_ODT_MAX                        (0x0000000F)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MASK0_ODT_DEF                        (0x00000000)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MASK0_Web_OFF                        ( 4)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MASK0_Web_WID                        ( 1)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MASK0_Web_MSK                        (0x00000010)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MASK0_Web_MAX                        (0x00000001)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MASK0_Web_DEF                        (0x00000000)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MASK0_CASb_OFF                       ( 5)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MASK0_CASb_WID                       ( 1)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MASK0_CASb_MSK                       (0x00000020)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MASK0_CASb_MAX                       (0x00000001)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MASK0_CASb_DEF                       (0x00000000)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MASK0_RASb_OFF                       ( 6)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MASK0_RASb_WID                       ( 1)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MASK0_RASb_MSK                       (0x00000040)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MASK0_RASb_MAX                       (0x00000001)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MASK0_RASb_DEF                       (0x00000000)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MASK0_CSb_OFF                        ( 7)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MASK0_CSb_WID                        ( 4)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MASK0_CSb_MSK                        (0x00000780)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MASK0_CSb_MAX                        (0x0000000F)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MASK0_CSb_DEF                        (0x00000000)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MASK0_CKE_OFF                        (11)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MASK0_CKE_WID                        ( 4)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MASK0_CKE_MSK                        (0x00007800)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MASK0_CKE_MAX                        (0x0000000F)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MASK0_CKE_DEF                        (0x00000000)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MASK0_MA_OFF                         (15)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MASK0_MA_WID                         (16)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MASK0_MA_MSK                         (0x7FFF8000)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MASK0_MA_MAX                         (0x0000FFFF)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MASK0_MA_DEF                         (0x00000000)
+
+#define MCHBAR_CH1_CR_ODLAT_CMD_MASK1_REG                            (0x00004754)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MASK1_ODT_OFF                        ( 0)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MASK1_ODT_WID                        ( 4)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MASK1_ODT_MSK                        (0x0000000F)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MASK1_ODT_MAX                        (0x0000000F)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MASK1_ODT_DEF                        (0x00000000)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MASK1_Web_OFF                        ( 4)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MASK1_Web_WID                        ( 1)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MASK1_Web_MSK                        (0x00000010)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MASK1_Web_MAX                        (0x00000001)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MASK1_Web_DEF                        (0x00000000)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MASK1_CASb_OFF                       ( 5)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MASK1_CASb_WID                       ( 1)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MASK1_CASb_MSK                       (0x00000020)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MASK1_CASb_MAX                       (0x00000001)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MASK1_CASb_DEF                       (0x00000000)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MASK1_RASb_OFF                       ( 6)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MASK1_RASb_WID                       ( 1)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MASK1_RASb_MSK                       (0x00000040)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MASK1_RASb_MAX                       (0x00000001)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MASK1_RASb_DEF                       (0x00000000)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MASK1_CSb_OFF                        ( 7)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MASK1_CSb_WID                        ( 4)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MASK1_CSb_MSK                        (0x00000780)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MASK1_CSb_MAX                        (0x0000000F)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MASK1_CSb_DEF                        (0x00000000)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MASK1_CKE_OFF                        (11)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MASK1_CKE_WID                        ( 4)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MASK1_CKE_MSK                        (0x00007800)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MASK1_CKE_MAX                        (0x0000000F)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MASK1_CKE_DEF                        (0x00000000)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MASK1_MA_OFF                         (15)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MASK1_MA_WID                         (16)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MASK1_MA_MSK                         (0x7FFF8000)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MASK1_MA_MAX                         (0x0000FFFF)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MASK1_MA_DEF                         (0x00000000)
+
+#define MCHBAR_CH1_CR_ODLAT_CMD_MASK2_REG                            (0x00004758)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MASK2_ODT_OFF                        ( 0)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MASK2_ODT_WID                        ( 4)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MASK2_ODT_MSK                        (0x0000000F)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MASK2_ODT_MAX                        (0x0000000F)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MASK2_ODT_DEF                        (0x00000000)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MASK2_Web_OFF                        ( 4)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MASK2_Web_WID                        ( 1)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MASK2_Web_MSK                        (0x00000010)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MASK2_Web_MAX                        (0x00000001)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MASK2_Web_DEF                        (0x00000000)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MASK2_CASb_OFF                       ( 5)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MASK2_CASb_WID                       ( 1)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MASK2_CASb_MSK                       (0x00000020)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MASK2_CASb_MAX                       (0x00000001)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MASK2_CASb_DEF                       (0x00000000)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MASK2_RASb_OFF                       ( 6)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MASK2_RASb_WID                       ( 1)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MASK2_RASb_MSK                       (0x00000040)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MASK2_RASb_MAX                       (0x00000001)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MASK2_RASb_DEF                       (0x00000000)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MASK2_CSb_OFF                        ( 7)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MASK2_CSb_WID                        ( 4)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MASK2_CSb_MSK                        (0x00000780)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MASK2_CSb_MAX                        (0x0000000F)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MASK2_CSb_DEF                        (0x00000000)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MASK2_CKE_OFF                        (11)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MASK2_CKE_WID                        ( 4)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MASK2_CKE_MSK                        (0x00007800)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MASK2_CKE_MAX                        (0x0000000F)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MASK2_CKE_DEF                        (0x00000000)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MASK2_MA_OFF                         (15)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MASK2_MA_WID                         (16)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MASK2_MA_MSK                         (0x7FFF8000)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MASK2_MA_MAX                         (0x0000FFFF)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MASK2_MA_DEF                         (0x00000000)
+
+#define MCHBAR_CH1_CR_ODLAT_CMD_MASK3_REG                            (0x0000475C)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MASK3_ODT_OFF                        ( 0)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MASK3_ODT_WID                        ( 4)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MASK3_ODT_MSK                        (0x0000000F)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MASK3_ODT_MAX                        (0x0000000F)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MASK3_ODT_DEF                        (0x00000000)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MASK3_Web_OFF                        ( 4)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MASK3_Web_WID                        ( 1)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MASK3_Web_MSK                        (0x00000010)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MASK3_Web_MAX                        (0x00000001)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MASK3_Web_DEF                        (0x00000000)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MASK3_CASb_OFF                       ( 5)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MASK3_CASb_WID                       ( 1)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MASK3_CASb_MSK                       (0x00000020)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MASK3_CASb_MAX                       (0x00000001)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MASK3_CASb_DEF                       (0x00000000)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MASK3_RASb_OFF                       ( 6)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MASK3_RASb_WID                       ( 1)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MASK3_RASb_MSK                       (0x00000040)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MASK3_RASb_MAX                       (0x00000001)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MASK3_RASb_DEF                       (0x00000000)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MASK3_CSb_OFF                        ( 7)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MASK3_CSb_WID                        ( 4)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MASK3_CSb_MSK                        (0x00000780)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MASK3_CSb_MAX                        (0x0000000F)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MASK3_CSb_DEF                        (0x00000000)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MASK3_CKE_OFF                        (11)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MASK3_CKE_WID                        ( 4)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MASK3_CKE_MSK                        (0x00007800)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MASK3_CKE_MAX                        (0x0000000F)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MASK3_CKE_DEF                        (0x00000000)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MASK3_MA_OFF                         (15)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MASK3_MA_WID                         (16)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MASK3_MA_MSK                         (0x7FFF8000)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MASK3_MA_MAX                         (0x0000FFFF)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_MASK3_MA_DEF                         (0x00000000)
+
+#define MCHBAR_CH1_CR_ODLAT_CMD_BANK_REG                             (0x00004760)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_BANK_BankMatch0_OFF                  ( 0)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_BANK_BankMatch0_WID                  ( 3)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_BANK_BankMatch0_MSK                  (0x00000007)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_BANK_BankMatch0_MAX                  (0x00000007)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_BANK_BankMatch0_DEF                  (0x00000000)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_BANK_BankMatch1_OFF                  ( 3)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_BANK_BankMatch1_WID                  ( 3)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_BANK_BankMatch1_MSK                  (0x00000038)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_BANK_BankMatch1_MAX                  (0x00000007)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_BANK_BankMatch1_DEF                  (0x00000000)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_BANK_BankMatch2_OFF                  ( 6)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_BANK_BankMatch2_WID                  ( 3)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_BANK_BankMatch2_MSK                  (0x000001C0)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_BANK_BankMatch2_MAX                  (0x00000007)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_BANK_BankMatch2_DEF                  (0x00000000)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_BANK_BankMatch3_OFF                  ( 9)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_BANK_BankMatch3_WID                  ( 3)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_BANK_BankMatch3_MSK                  (0x00000E00)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_BANK_BankMatch3_MAX                  (0x00000007)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_BANK_BankMatch3_DEF                  (0x00000000)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_BANK_BankMask0_OFF                   (12)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_BANK_BankMask0_WID                   ( 3)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_BANK_BankMask0_MSK                   (0x00007000)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_BANK_BankMask0_MAX                   (0x00000007)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_BANK_BankMask0_DEF                   (0x00000000)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_BANK_BankMask1_OFF                   (15)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_BANK_BankMask1_WID                   ( 3)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_BANK_BankMask1_MSK                   (0x00038000)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_BANK_BankMask1_MAX                   (0x00000007)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_BANK_BankMask1_DEF                   (0x00000000)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_BANK_BankMask2_OFF                   (18)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_BANK_BankMask2_WID                   ( 3)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_BANK_BankMask2_MSK                   (0x001C0000)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_BANK_BankMask2_MAX                   (0x00000007)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_BANK_BankMask2_DEF                   (0x00000000)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_BANK_BankMask3_OFF                   (21)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_BANK_BankMask3_WID                   ( 3)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_BANK_BankMask3_MSK                   (0x00E00000)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_BANK_BankMask3_MAX                   (0x00000007)
+  #define MCHBAR_CH1_CR_ODLAT_CMD_BANK_BankMask3_DEF                   (0x00000000)
+
+#define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL0_REG                           (0x00004764)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL0_InputMatch_OFF                ( 0)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL0_InputMatch_WID                ( 4)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL0_InputMatch_MSK                (0x0000000F)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL0_InputMatch_MAX                (0x0000000F)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL0_InputMatch_DEF                (0x00000000)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL0_InputInvert_OFF               ( 4)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL0_InputInvert_WID               ( 4)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL0_InputInvert_MSK               (0x000000F0)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL0_InputInvert_MAX               (0x0000000F)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL0_InputInvert_DEF               (0x00000000)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL0_CountMatches_OFF              ( 8)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL0_CountMatches_WID              ( 1)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL0_CountMatches_MSK              (0x00000100)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL0_CountMatches_MAX              (0x00000001)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL0_CountMatches_DEF              (0x00000000)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL0_CounterThreshold_OFF          ( 9)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL0_CounterThreshold_WID          (15)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL0_CounterThreshold_MSK          (0x00FFFE00)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL0_CounterThreshold_MAX          (0x00007FFF)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL0_CounterThreshold_DEF          (0x00000000)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL0_CounterAction_OFF             (24)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL0_CounterAction_WID             ( 2)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL0_CounterAction_MSK             (0x03000000)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL0_CounterAction_MAX             (0x00000003)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL0_CounterAction_DEF             (0x00000000)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL0_CounterNextState_OFF          (26)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL0_CounterNextState_WID          ( 2)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL0_CounterNextState_MSK          (0x0C000000)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL0_CounterNextState_MAX          (0x00000003)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL0_CounterNextState_DEF          (0x00000000)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL0_MatchAction_OFF               (28)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL0_MatchAction_WID               ( 2)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL0_MatchAction_MSK               (0x30000000)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL0_MatchAction_MAX               (0x00000003)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL0_MatchAction_DEF               (0x00000000)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL0_MatchNextState_OFF            (30)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL0_MatchNextState_WID            ( 2)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL0_MatchNextState_MSK            (0xC0000000)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL0_MatchNextState_MAX            (0x00000003)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL0_MatchNextState_DEF            (0x00000000)
+
+#define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL1_REG                           (0x00004768)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL1_InputMatch_OFF                ( 0)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL1_InputMatch_WID                ( 4)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL1_InputMatch_MSK                (0x0000000F)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL1_InputMatch_MAX                (0x0000000F)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL1_InputMatch_DEF                (0x00000000)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL1_InputInvert_OFF               ( 4)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL1_InputInvert_WID               ( 4)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL1_InputInvert_MSK               (0x000000F0)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL1_InputInvert_MAX               (0x0000000F)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL1_InputInvert_DEF               (0x00000000)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL1_CountMatches_OFF              ( 8)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL1_CountMatches_WID              ( 1)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL1_CountMatches_MSK              (0x00000100)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL1_CountMatches_MAX              (0x00000001)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL1_CountMatches_DEF              (0x00000000)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL1_CounterThreshold_OFF          ( 9)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL1_CounterThreshold_WID          (15)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL1_CounterThreshold_MSK          (0x00FFFE00)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL1_CounterThreshold_MAX          (0x00007FFF)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL1_CounterThreshold_DEF          (0x00000000)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL1_CounterAction_OFF             (24)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL1_CounterAction_WID             ( 2)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL1_CounterAction_MSK             (0x03000000)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL1_CounterAction_MAX             (0x00000003)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL1_CounterAction_DEF             (0x00000000)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL1_CounterNextState_OFF          (26)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL1_CounterNextState_WID          ( 2)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL1_CounterNextState_MSK          (0x0C000000)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL1_CounterNextState_MAX          (0x00000003)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL1_CounterNextState_DEF          (0x00000000)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL1_MatchAction_OFF               (28)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL1_MatchAction_WID               ( 2)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL1_MatchAction_MSK               (0x30000000)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL1_MatchAction_MAX               (0x00000003)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL1_MatchAction_DEF               (0x00000000)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL1_MatchNextState_OFF            (30)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL1_MatchNextState_WID            ( 2)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL1_MatchNextState_MSK            (0xC0000000)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL1_MatchNextState_MAX            (0x00000003)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL1_MatchNextState_DEF            (0x00000000)
+
+#define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL2_REG                           (0x0000476C)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL2_InputMatch_OFF                ( 0)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL2_InputMatch_WID                ( 4)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL2_InputMatch_MSK                (0x0000000F)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL2_InputMatch_MAX                (0x0000000F)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL2_InputMatch_DEF                (0x00000000)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL2_InputInvert_OFF               ( 4)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL2_InputInvert_WID               ( 4)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL2_InputInvert_MSK               (0x000000F0)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL2_InputInvert_MAX               (0x0000000F)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL2_InputInvert_DEF               (0x00000000)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL2_CountMatches_OFF              ( 8)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL2_CountMatches_WID              ( 1)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL2_CountMatches_MSK              (0x00000100)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL2_CountMatches_MAX              (0x00000001)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL2_CountMatches_DEF              (0x00000000)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL2_CounterThreshold_OFF          ( 9)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL2_CounterThreshold_WID          (15)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL2_CounterThreshold_MSK          (0x00FFFE00)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL2_CounterThreshold_MAX          (0x00007FFF)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL2_CounterThreshold_DEF          (0x00000000)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL2_CounterAction_OFF             (24)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL2_CounterAction_WID             ( 2)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL2_CounterAction_MSK             (0x03000000)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL2_CounterAction_MAX             (0x00000003)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL2_CounterAction_DEF             (0x00000000)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL2_CounterNextState_OFF          (26)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL2_CounterNextState_WID          ( 2)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL2_CounterNextState_MSK          (0x0C000000)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL2_CounterNextState_MAX          (0x00000003)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL2_CounterNextState_DEF          (0x00000000)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL2_MatchAction_OFF               (28)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL2_MatchAction_WID               ( 2)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL2_MatchAction_MSK               (0x30000000)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL2_MatchAction_MAX               (0x00000003)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL2_MatchAction_DEF               (0x00000000)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL2_MatchNextState_OFF            (30)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL2_MatchNextState_WID            ( 2)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL2_MatchNextState_MSK            (0xC0000000)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL2_MatchNextState_MAX            (0x00000003)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL2_MatchNextState_DEF            (0x00000000)
+
+#define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL3_REG                           (0x00004770)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL3_InputMatch_OFF                ( 0)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL3_InputMatch_WID                ( 4)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL3_InputMatch_MSK                (0x0000000F)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL3_InputMatch_MAX                (0x0000000F)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL3_InputMatch_DEF                (0x00000000)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL3_InputInvert_OFF               ( 4)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL3_InputInvert_WID               ( 4)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL3_InputInvert_MSK               (0x000000F0)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL3_InputInvert_MAX               (0x0000000F)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL3_InputInvert_DEF               (0x00000000)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL3_CountMatches_OFF              ( 8)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL3_CountMatches_WID              ( 1)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL3_CountMatches_MSK              (0x00000100)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL3_CountMatches_MAX              (0x00000001)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL3_CountMatches_DEF              (0x00000000)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL3_CounterThreshold_OFF          ( 9)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL3_CounterThreshold_WID          (15)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL3_CounterThreshold_MSK          (0x00FFFE00)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL3_CounterThreshold_MAX          (0x00007FFF)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL3_CounterThreshold_DEF          (0x00000000)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL3_CounterAction_OFF             (24)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL3_CounterAction_WID             ( 2)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL3_CounterAction_MSK             (0x03000000)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL3_CounterAction_MAX             (0x00000003)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL3_CounterAction_DEF             (0x00000000)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL3_CounterNextState_OFF          (26)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL3_CounterNextState_WID          ( 2)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL3_CounterNextState_MSK          (0x0C000000)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL3_CounterNextState_MAX          (0x00000003)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL3_CounterNextState_DEF          (0x00000000)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL3_MatchAction_OFF               (28)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL3_MatchAction_WID               ( 2)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL3_MatchAction_MSK               (0x30000000)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL3_MatchAction_MAX               (0x00000003)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL3_MatchAction_DEF               (0x00000000)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL3_MatchNextState_OFF            (30)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL3_MatchNextState_WID            ( 2)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL3_MatchNextState_MSK            (0xC0000000)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL3_MatchNextState_MAX            (0x00000003)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL3_MatchNextState_DEF            (0x00000000)
+
+#define MCHBAR_CH1_CR_ODLAT_SEQ_GLOBAL_REG                           (0x00004774)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_GLOBAL_TriggerBlockEnable_OFF        ( 0)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_GLOBAL_TriggerBlockEnable_WID        ( 1)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_GLOBAL_TriggerBlockEnable_MSK        (0x00000001)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_GLOBAL_TriggerBlockEnable_MAX        (0x00000001)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_GLOBAL_TriggerBlockEnable_DEF        (0x00000000)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_GLOBAL_GlobalCounterThreshold_OFF    ( 1)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_GLOBAL_GlobalCounterThreshold_WID    (16)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_GLOBAL_GlobalCounterThreshold_MSK    (0x0001FFFE)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_GLOBAL_GlobalCounterThreshold_MAX    (0x0000FFFF)
+  #define MCHBAR_CH1_CR_ODLAT_SEQ_GLOBAL_GlobalCounterThreshold_DEF    (0x00000000)
+
+#define MCHBAR_CH1_CR_SC_WDBWM_REG                                   (0x0000478C)
+  #define MCHBAR_CH1_CR_SC_WDBWM_WMM_Enter_OFF                         ( 0)
+  #define MCHBAR_CH1_CR_SC_WDBWM_WMM_Enter_WID                         ( 8)
+  #define MCHBAR_CH1_CR_SC_WDBWM_WMM_Enter_MSK                         (0x000000FF)
+  #define MCHBAR_CH1_CR_SC_WDBWM_WMM_Enter_MAX                         (0x000000FF)
+  #define MCHBAR_CH1_CR_SC_WDBWM_WMM_Enter_DEF                         (0x00000038)
+  #define MCHBAR_CH1_CR_SC_WDBWM_WMM_Exit_OFF                          ( 8)
+  #define MCHBAR_CH1_CR_SC_WDBWM_WMM_Exit_WID                          ( 8)
+  #define MCHBAR_CH1_CR_SC_WDBWM_WMM_Exit_MSK                          (0x0000FF00)
+  #define MCHBAR_CH1_CR_SC_WDBWM_WMM_Exit_MAX                          (0x000000FF)
+  #define MCHBAR_CH1_CR_SC_WDBWM_WMM_Exit_DEF                          (0x00000030)
+  #define MCHBAR_CH1_CR_SC_WDBWM_WPQ_IS_OFF                            (16)
+  #define MCHBAR_CH1_CR_SC_WDBWM_WPQ_IS_WID                            ( 8)
+  #define MCHBAR_CH1_CR_SC_WDBWM_WPQ_IS_MSK                            (0x00FF0000)
+  #define MCHBAR_CH1_CR_SC_WDBWM_WPQ_IS_MAX                            (0x000000FF)
+  #define MCHBAR_CH1_CR_SC_WDBWM_WPQ_IS_DEF                            (0x0000003C)
+  #define MCHBAR_CH1_CR_SC_WDBWM_Starve_count_OFF                      (24)
+  #define MCHBAR_CH1_CR_SC_WDBWM_Starve_count_WID                      ( 8)
+  #define MCHBAR_CH1_CR_SC_WDBWM_Starve_count_MSK                      (0xFF000000)
+  #define MCHBAR_CH1_CR_SC_WDBWM_Starve_count_MAX                      (0x000000FF)
+  #define MCHBAR_CH1_CR_SC_WDBWM_Starve_count_DEF                      (0x000000FF)
+
+#define MCHBAR_CH1_CR_VISA_CTL_MCMNTS_REG                            (0x00004790)
+  #define MCHBAR_CH1_CR_VISA_CTL_MCMNTS_Data_OFF                       ( 0)
+  #define MCHBAR_CH1_CR_VISA_CTL_MCMNTS_Data_WID                       (18)
+  #define MCHBAR_CH1_CR_VISA_CTL_MCMNTS_Data_MSK                       (0x0003FFFF)
+  #define MCHBAR_CH1_CR_VISA_CTL_MCMNTS_Data_MAX                       (0x0003FFFF)
+  #define MCHBAR_CH1_CR_VISA_CTL_MCMNTS_Data_DEF                       (0x00000000)
+  #define MCHBAR_CH1_CR_VISA_CTL_MCMNTS_VORANGE_OFF                    (31)
+  #define MCHBAR_CH1_CR_VISA_CTL_MCMNTS_VORANGE_WID                    ( 1)
+  #define MCHBAR_CH1_CR_VISA_CTL_MCMNTS_VORANGE_MSK                    (0x80000000)
+  #define MCHBAR_CH1_CR_VISA_CTL_MCMNTS_VORANGE_MAX                    (0x00000001)
+  #define MCHBAR_CH1_CR_VISA_CTL_MCMNTS_VORANGE_DEF                    (0x00000000)
+
+#pragma pack(pop)
+#endif  // __McMain_h__
diff --git a/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcRegisters/McScramble.h b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcRegisters/McScramble.h
new file mode 100644
index 0000000..a387610
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcRegisters/McScramble.h
@@ -0,0 +1,148 @@
+/** @file
+  This file was automatically generated. Modify at your own risk.
+
+@copyright
+  Copyright (c) 2010 - 2012 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement
+**/
+#ifndef __McScramble_h__
+#define __McScramble_h__
+
+#pragma pack(push, 1)
+#include "MrcTypes.h"
+
+typedef union {
+  struct {
+    U32 ScramEn                                 :  1;  // Bits 0:0
+    U32 ScramKey                                :  16;  // Bits 16:1
+    U32 Spare                                   :  15;  // Bits 31:17
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRSCRAM_CR_DDRSCRAMBLECH0_STRUCT;
+
+typedef union {
+  struct {
+    U32 ScramEn                                 :  1;  // Bits 0:0
+    U32 ScramKey                                :  16;  // Bits 16:1
+    U32 Spare                                   :  15;  // Bits 31:17
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRSCRAM_CR_DDRSCRAMBLECH1_STRUCT;
+
+typedef union {
+  struct {
+    U32 WL_WakeCycles                           :  2;  // Bits 1:0
+    U32 WL_SleepCycles                          :  3;  // Bits 4:2
+    U32 ForceCompUpdate                         :  1;  // Bits 5:5
+    U32 WeakLock_Latency                        :  4;  // Bits 9:6
+    U32 DdrNoChInterleave                       :  1;  // Bits 10:10
+    U32 LPDDR_Mode                              :  1;  // Bits 11:11
+    U32 CKEMappingCh0                           :  4;  // Bits 15:12
+    U32 CKEMappingCh1                           :  4;  // Bits 19:16
+    U32 Spare                                   :  12;  // Bits 31:20
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DDRSCRAM_CR_DDRMISCCONTROL0_STRUCT;
+
+#define DDRSCRAM_CR_DDRSCRAMBLECH0_REG                               (0x00002000)
+  #define DDRSCRAM_CR_DDRSCRAMBLECH0_ScramEn_OFF                       ( 0)
+  #define DDRSCRAM_CR_DDRSCRAMBLECH0_ScramEn_WID                       ( 1)
+  #define DDRSCRAM_CR_DDRSCRAMBLECH0_ScramEn_MSK                       (0x00000001)
+  #define DDRSCRAM_CR_DDRSCRAMBLECH0_ScramEn_MAX                       (0x00000001)
+  #define DDRSCRAM_CR_DDRSCRAMBLECH0_ScramEn_DEF                       (0x00000000)
+  #define DDRSCRAM_CR_DDRSCRAMBLECH0_ScramKey_OFF                      ( 1)
+  #define DDRSCRAM_CR_DDRSCRAMBLECH0_ScramKey_WID                      (16)
+  #define DDRSCRAM_CR_DDRSCRAMBLECH0_ScramKey_MSK                      (0x0001FFFE)
+  #define DDRSCRAM_CR_DDRSCRAMBLECH0_ScramKey_MAX                      (0x0000FFFF)
+  #define DDRSCRAM_CR_DDRSCRAMBLECH0_ScramKey_DEF                      (0x00000000)
+  #define DDRSCRAM_CR_DDRSCRAMBLECH0_Spare_OFF                         (17)
+  #define DDRSCRAM_CR_DDRSCRAMBLECH0_Spare_WID                         (15)
+  #define DDRSCRAM_CR_DDRSCRAMBLECH0_Spare_MSK                         (0xFFFE0000)
+  #define DDRSCRAM_CR_DDRSCRAMBLECH0_Spare_MAX                         (0x00007FFF)
+  #define DDRSCRAM_CR_DDRSCRAMBLECH0_Spare_DEF                         (0x00000000)
+
+#define DDRSCRAM_CR_DDRSCRAMBLECH1_REG                               (0x00002004)
+  #define DDRSCRAM_CR_DDRSCRAMBLECH1_ScramEn_OFF                       ( 0)
+  #define DDRSCRAM_CR_DDRSCRAMBLECH1_ScramEn_WID                       ( 1)
+  #define DDRSCRAM_CR_DDRSCRAMBLECH1_ScramEn_MSK                       (0x00000001)
+  #define DDRSCRAM_CR_DDRSCRAMBLECH1_ScramEn_MAX                       (0x00000001)
+  #define DDRSCRAM_CR_DDRSCRAMBLECH1_ScramEn_DEF                       (0x00000000)
+  #define DDRSCRAM_CR_DDRSCRAMBLECH1_ScramKey_OFF                      ( 1)
+  #define DDRSCRAM_CR_DDRSCRAMBLECH1_ScramKey_WID                      (16)
+  #define DDRSCRAM_CR_DDRSCRAMBLECH1_ScramKey_MSK                      (0x0001FFFE)
+  #define DDRSCRAM_CR_DDRSCRAMBLECH1_ScramKey_MAX                      (0x0000FFFF)
+  #define DDRSCRAM_CR_DDRSCRAMBLECH1_ScramKey_DEF                      (0x00000000)
+  #define DDRSCRAM_CR_DDRSCRAMBLECH1_Spare_OFF                         (17)
+  #define DDRSCRAM_CR_DDRSCRAMBLECH1_Spare_WID                         (15)
+  #define DDRSCRAM_CR_DDRSCRAMBLECH1_Spare_MSK                         (0xFFFE0000)
+  #define DDRSCRAM_CR_DDRSCRAMBLECH1_Spare_MAX                         (0x00007FFF)
+  #define DDRSCRAM_CR_DDRSCRAMBLECH1_Spare_DEF                         (0x00000000)
+
+#define DDRSCRAM_CR_DDRMISCCONTROL0_REG                              (0x00002008)
+  #define DDRSCRAM_CR_DDRMISCCONTROL0_WL_WakeCycles_OFF                ( 0)
+  #define DDRSCRAM_CR_DDRMISCCONTROL0_WL_WakeCycles_WID                ( 2)
+  #define DDRSCRAM_CR_DDRMISCCONTROL0_WL_WakeCycles_MSK                (0x00000003)
+  #define DDRSCRAM_CR_DDRMISCCONTROL0_WL_WakeCycles_MAX                (0x00000003)
+  #define DDRSCRAM_CR_DDRMISCCONTROL0_WL_WakeCycles_DEF                (0x00000000)
+  #define DDRSCRAM_CR_DDRMISCCONTROL0_WL_SleepCycles_OFF               ( 2)
+  #define DDRSCRAM_CR_DDRMISCCONTROL0_WL_SleepCycles_WID               ( 3)
+  #define DDRSCRAM_CR_DDRMISCCONTROL0_WL_SleepCycles_MSK               (0x0000001C)
+  #define DDRSCRAM_CR_DDRMISCCONTROL0_WL_SleepCycles_MAX               (0x00000007)
+  #define DDRSCRAM_CR_DDRMISCCONTROL0_WL_SleepCycles_DEF               (0x00000000)
+  #define DDRSCRAM_CR_DDRMISCCONTROL0_ForceCompUpdate_OFF              ( 5)
+  #define DDRSCRAM_CR_DDRMISCCONTROL0_ForceCompUpdate_WID              ( 1)
+  #define DDRSCRAM_CR_DDRMISCCONTROL0_ForceCompUpdate_MSK              (0x00000020)
+  #define DDRSCRAM_CR_DDRMISCCONTROL0_ForceCompUpdate_MAX              (0x00000001)
+  #define DDRSCRAM_CR_DDRMISCCONTROL0_ForceCompUpdate_DEF              (0x00000000)
+  #define DDRSCRAM_CR_DDRMISCCONTROL0_WeakLock_Latency_OFF             ( 6)
+  #define DDRSCRAM_CR_DDRMISCCONTROL0_WeakLock_Latency_WID             ( 4)
+  #define DDRSCRAM_CR_DDRMISCCONTROL0_WeakLock_Latency_MSK             (0x000003C0)
+  #define DDRSCRAM_CR_DDRMISCCONTROL0_WeakLock_Latency_MAX             (0x0000000F)
+  #define DDRSCRAM_CR_DDRMISCCONTROL0_WeakLock_Latency_DEF             (0x0000000C)
+  #define DDRSCRAM_CR_DDRMISCCONTROL0_DdrNoChInterleave_OFF            (10)
+  #define DDRSCRAM_CR_DDRMISCCONTROL0_DdrNoChInterleave_WID            ( 1)
+  #define DDRSCRAM_CR_DDRMISCCONTROL0_DdrNoChInterleave_MSK            (0x00000400)
+  #define DDRSCRAM_CR_DDRMISCCONTROL0_DdrNoChInterleave_MAX            (0x00000001)
+  #define DDRSCRAM_CR_DDRMISCCONTROL0_DdrNoChInterleave_DEF            (0x00000000)
+  #define DDRSCRAM_CR_DDRMISCCONTROL0_LPDDR_Mode_OFF                   (11)
+  #define DDRSCRAM_CR_DDRMISCCONTROL0_LPDDR_Mode_WID                   ( 1)
+  #define DDRSCRAM_CR_DDRMISCCONTROL0_LPDDR_Mode_MSK                   (0x00000800)
+  #define DDRSCRAM_CR_DDRMISCCONTROL0_LPDDR_Mode_MAX                   (0x00000001)
+  #define DDRSCRAM_CR_DDRMISCCONTROL0_LPDDR_Mode_DEF                   (0x00000000)
+  #define DDRSCRAM_CR_DDRMISCCONTROL0_CKEMappingCh0_OFF                (12)
+  #define DDRSCRAM_CR_DDRMISCCONTROL0_CKEMappingCh0_WID                ( 4)
+  #define DDRSCRAM_CR_DDRMISCCONTROL0_CKEMappingCh0_MSK                (0x0000F000)
+  #define DDRSCRAM_CR_DDRMISCCONTROL0_CKEMappingCh0_MAX                (0x0000000F)
+  #define DDRSCRAM_CR_DDRMISCCONTROL0_CKEMappingCh0_DEF                (0x0000000A)
+  #define DDRSCRAM_CR_DDRMISCCONTROL0_CKEMappingCh1_OFF                (16)
+  #define DDRSCRAM_CR_DDRMISCCONTROL0_CKEMappingCh1_WID                ( 4)
+  #define DDRSCRAM_CR_DDRMISCCONTROL0_CKEMappingCh1_MSK                (0x000F0000)
+  #define DDRSCRAM_CR_DDRMISCCONTROL0_CKEMappingCh1_MAX                (0x0000000F)
+  #define DDRSCRAM_CR_DDRMISCCONTROL0_CKEMappingCh1_DEF                (0x0000000A)
+  #define DDRSCRAM_CR_DDRMISCCONTROL0_Spare_OFF                        (20)
+  #define DDRSCRAM_CR_DDRMISCCONTROL0_Spare_WID                        (12)
+  #define DDRSCRAM_CR_DDRMISCCONTROL0_Spare_MSK                        (0xFFF00000)
+  #define DDRSCRAM_CR_DDRMISCCONTROL0_Spare_MAX                        (0x00000FFF)
+  #define DDRSCRAM_CR_DDRMISCCONTROL0_Spare_DEF                        (0x00000000)
+
+#pragma pack(pop)
+#endif  // __McScramble_h__
diff --git a/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcRegisters/Msa.h b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcRegisters/Msa.h
new file mode 100644
index 0000000..ed8e90d
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcRegisters/Msa.h
@@ -0,0 +1,6827 @@
+/** @file
+  This file was automatically generated. Modify at your own risk.
+
+@copyright
+  Copyright (c) 2010 - 2012 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement
+**/
+#ifndef __Msa_h__
+#define __Msa_h__
+
+#pragma pack(push, 1)
+#include "MrcTypes.h"
+
+typedef union {
+  struct {
+    U32 GFXVTBAREN                              :  1;  // Bits 0:0
+    U32                                         :  11;  // Bits 11:1
+    U32 GFXVTBAR                                :  27;  // Bits 38:12
+    U32                                         :  25;  // Bits 63:39
+  } Bits;
+  U64 Data;
+  U32 Data32[2];
+  U16 Data16[4];
+  U8  Data8[8];
+} NCDECS_CR_GFXVTBAR_NCU_STRUCT;
+
+typedef union {
+  struct {
+    U32 EDRAMBAREN                              :  1;  // Bits 0:0
+    U32                                         :  13;  // Bits 13:1
+    U32 EDRAMBAR                                :  25;  // Bits 38:14
+    U32                                         :  25;  // Bits 63:39
+  } Bits;
+  U64 Data;
+  U32 Data32[2];
+  U16 Data16[4];
+  U8  Data8[8];
+} NCDECS_CR_EDRAMBAR_NCU_STRUCT;
+
+typedef union {
+  struct {
+    U32 VTVC0BAREN                              :  1;  // Bits 0:0
+    U32                                         :  11;  // Bits 11:1
+    U32 VTVC0BAR                                :  27;  // Bits 38:12
+    U32                                         :  25;  // Bits 63:39
+  } Bits;
+  U64 Data;
+  U32 Data32[2];
+  U16 Data16[4];
+  U8  Data8[8];
+} NCDECS_CR_VTDPVC0BAR_NCU_STRUCT;
+
+typedef union {
+  struct {
+    U32 RdrModSel                               :  3;  // Bits 2:0
+    U32 ClastChkSmpMod                          :  1;  // Bits 3:3
+    U32 LogFltClustMod                          :  1;  // Bits 4:4
+    U32 LogFlatClustOvrEn                       :  1;  // Bits 5:5
+    U32 HashModCtr                              :  3;  // Bits 8:6
+    U32                                         :  23;  // Bits 31:9
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} NCDECS_CR_INTRDIRCTL_NCU_STRUCT;
+
+typedef union {
+  struct {
+    U32                                         :  28;  // Bits 27:0
+    U32 PLIM                                    :  3;  // Bits 30:28
+    U32                                         :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} NCDECS_CR_NCUCTL0_NCU_STRUCT;
+
+typedef union {
+  struct {
+    U32 GDXCBAREN                               :  1;  // Bits 0:0
+    U32                                         :  11;  // Bits 11:1
+    U32 GDXCBAR                                 :  27;  // Bits 38:12
+    U32                                         :  25;  // Bits 63:39
+  } Bits;
+  U64 Data;
+  U32 Data32[2];
+  U16 Data16[4];
+  U8  Data8[8];
+} NCDECS_CR_GDXCBAR_NCU_STRUCT;
+
+typedef union {
+  struct {
+    U32 Data                                    :  32;  // Bits 31:0
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} NCDECS_CR_SCRATCHPAD_NCU_0_STRUCT;
+
+typedef union {
+  struct {
+    U32 Data                                    :  32;  // Bits 31:0
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} NCDECS_CR_SCRATCHPAD_NCU_1_STRUCT;
+
+typedef union {
+  struct {
+    U32 Data                                    :  32;  // Bits 31:0
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} NCDECS_CR_SCRATCHPAD_NCU_2_STRUCT;
+
+typedef union {
+  struct {
+    U32 Data                                    :  32;  // Bits 31:0
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} NCDECS_CR_SCRATCHPAD_NCU_3_STRUCT;
+
+typedef union {
+  struct {
+    U32 LOCK                                    :  1;  // Bits 0:0
+    U32                                         :  19;  // Bits 19:1
+    U32 OFFSET                                  :  12;  // Bits 31:20
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} NCDECS_CR_PAVPMSGOFFST_NCU_STRUCT;
+
+typedef union {
+  struct {
+    U32 VCPVTDLIM                               :  3;  // Bits 2:0
+    U32                                         :  29;  // Bits 31:3
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MPVTDTRK_CR_VTDLIM_IMPH_STRUCT;
+
+typedef union {
+  struct {
+    U32                                         :  3;  // Bits 2:0
+    U32 DEVNUM                                  :  5;  // Bits 7:3
+    U32 BUSNUM                                  :  8;  // Bits 15:8
+    U32                                         :  15;  // Bits 30:16
+    U32 HDAUD_EN                                :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MPVTDTRK_CR_HDAUDRID_IMPH_STRUCT;
+
+typedef union {
+  struct {
+    U32                                         :  20;  // Bits 19:0
+    U32 UMAB                                    :  19;  // Bits 38:20
+    U32                                         :  25;  // Bits 63:39
+  } Bits;
+  U64 Data;
+  U32 Data32[2];
+  U16 Data16[4];
+  U8  Data8[8];
+} MPVTDTRK_CR_UMAGFXBASE_IMPH_STRUCT;
+
+typedef union {
+  struct {
+    U32                                         :  20;  // Bits 19:0
+    U32 UMAL                                    :  19;  // Bits 38:20
+    U32                                         :  25;  // Bits 63:39
+  } Bits;
+  U64 Data;
+  U32 Data32[2];
+  U16 Data16[4];
+  U8  Data8[8];
+} MPVTDTRK_CR_UMAGFXLIMIT_IMPH_STRUCT;
+
+typedef union {
+  struct {
+    U32 LCK                                     :  1;  // Bits 0:0
+    U32                                         :  9;  // Bits 9:1
+    U32 PEG10EN                                 :  1;  // Bits 10:10
+    U32 PEG11EN                                 :  1;  // Bits 11:11
+    U32 PEG12EN                                 :  1;  // Bits 12:12
+    U32 DMIEN                                   :  1;  // Bits 13:13
+    U32                                         :  18;  // Bits 31:14
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MPVTDTRK_CR_UMAGFXCTL_IMPH_STRUCT;
+
+typedef union {
+  struct {
+    U32 FUNNUM                                  :  3;  // Bits 2:0
+    U32 DEVNUM                                  :  5;  // Bits 7:3
+    U32 BUSNUM                                  :  8;  // Bits 15:8
+    U32 BARNUM                                  :  3;  // Bits 18:16
+    U32                                         :  13;  // Bits 31:19
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MPVTDTRK_CR_VDMBDFBARKVM_IMPH_STRUCT;
+
+typedef union {
+  struct {
+    U32 FUNNUM                                  :  3;  // Bits 2:0
+    U32 DEVNUM                                  :  5;  // Bits 7:3
+    U32 BUSNUM                                  :  8;  // Bits 15:8
+    U32 BARNUM                                  :  3;  // Bits 18:16
+    U32                                         :  13;  // Bits 31:19
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MPVTDTRK_CR_VDMBDFBARPAVP_IMPH_STRUCT;
+
+typedef union {
+  struct {
+    U32 DATA                                    :  18;  // Bits 17:0
+    U32                                         :  13;  // Bits 30:18
+    U32 VORANGE                                 :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MPVTDTRK_CR_VISA_CTL_MPVTDTLBS_IMPH_STRUCT;
+
+typedef union {
+  struct {
+    U32 DATA                                    :  32;  // Bits 31:0
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MPVTDTRK_CR_VISA_XBAR_MPVTDTLBS_IMPH_STRUCT;
+
+typedef union {
+  struct {
+    U32 DATA                                    :  18;  // Bits 17:0
+    U32                                         :  13;  // Bits 30:18
+    U32 VORANGE                                 :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MPVTDTRK_CR_VISA_CTL_MPVTMISCS_IMPH_STRUCT;
+
+typedef union {
+  struct {
+    U32 DATA                                    :  18;  // Bits 17:0
+    U32                                         :  13;  // Bits 30:18
+    U32 VORANGE                                 :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MPVTDTRK_CR_VISA_CTL_MPVTTRKS_IMPH_STRUCT;
+
+typedef union {
+  struct {
+    U32 VC                                      :  4;  // Bits 3:0
+    U32 FMT_CMDTYPE                             :  6;  // Bits 9:4
+    U32 TC                                      :  4;  // Bits 13:10
+    U32 CHAIN                                   :  1;  // Bits 14:14
+    U32 NS                                      :  1;  // Bits 15:15
+    U32 RO                                      :  1;  // Bits 16:16
+    U32 LENGTH                                  :  5;  // Bits 21:17
+    U32 EP                                      :  1;  // Bits 22:22
+    U32 AT                                      :  2;  // Bits 24:23
+    U32                                         :  7;  // Bits 31:25
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MPVTDTRK_CR_PRIMUP_MASK1_IMPH_STRUCT;
+
+typedef union {
+  struct {
+    U32 RQID                                    :  16;  // Bits 15:0
+    U32 TAG                                     :  8;  // Bits 23:16
+    U32 LBEFBE_MSGTYPE                          :  8;  // Bits 31:24
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MPVTDTRK_CR_PRIMUP_MASK2_IMPH_STRUCT;
+
+typedef union {
+  struct {
+    U32 ADDR_31_0                               :  32;  // Bits 31:0
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MPVTDTRK_CR_PRIMUP_MASK3_IMPH_STRUCT;
+
+typedef union {
+  struct {
+    U32 ADDR_63_32                              :  32;  // Bits 31:0
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MPVTDTRK_CR_PRIMUP_MASK4_IMPH_STRUCT;
+
+typedef union {
+  struct {
+    U32 VC                                      :  4;  // Bits 3:0
+    U32 FMT_CMDTYPE                             :  6;  // Bits 9:4
+    U32 TC                                      :  4;  // Bits 13:10
+    U32 CHAIN                                   :  1;  // Bits 14:14
+    U32 NS                                      :  1;  // Bits 15:15
+    U32 RO                                      :  1;  // Bits 16:16
+    U32 LENGTH                                  :  5;  // Bits 21:17
+    U32 EP                                      :  1;  // Bits 22:22
+    U32 AT                                      :  2;  // Bits 24:23
+    U32                                         :  7;  // Bits 31:25
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MPVTDTRK_CR_PRIMUP_COMP1_IMPH_STRUCT;
+
+typedef union {
+  struct {
+    U32 RQID                                    :  16;  // Bits 15:0
+    U32 TAG                                     :  8;  // Bits 23:16
+    U32 LBEFBE_MSGTYPE                          :  8;  // Bits 31:24
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MPVTDTRK_CR_PRIMUP_COMP2_IMPH_STRUCT;
+
+typedef union {
+  struct {
+    U32 ADDR_31_0                               :  32;  // Bits 31:0
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MPVTDTRK_CR_PRIMUP_COMP3_IMPH_STRUCT;
+
+typedef union {
+  struct {
+    U32 ADDR_63_32                              :  32;  // Bits 31:0
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MPVTDTRK_CR_PRIMUP_COMP4_IMPH_STRUCT;
+
+typedef union {
+  struct {
+    U32 ENABLE                                  :  1;  // Bits 0:0
+    U32 TRIGGERED                               :  1;  // Bits 1:1
+    U32 STALL_DNARB                             :  1;  // Bits 2:2
+    U32 STALL_UPARB                             :  1;  // Bits 3:3
+    U32 STALL_SNPARB                            :  1;  // Bits 4:4
+    U32                                         :  18;  // Bits 22:5
+    U32 STALL_DELAY                             :  9;  // Bits 31:23
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MPVTDTRK_CR_PRIMUP_TRIGGER_IMPH_STRUCT;
+
+typedef union {
+  struct {
+    U32 PEG2DMIDIS                              :  1;  // Bits 0:0
+    U32 EOIB                                    :  1;  // Bits 1:1
+    U32 MSIBYPDIS                               :  1;  // Bits 2:2
+    U32                                         :  1;  // Bits 3:3
+    U32 PHLDDIS                                 :  1;  // Bits 4:4
+    U32                                         :  1;  // Bits 5:5
+    U32 BKSNPDIS                                :  1;  // Bits 6:6
+    U32 FRCVC0SNP                               :  1;  // Bits 7:7
+    U32 FRCVCPSNP                               :  1;  // Bits 8:8
+    U32 PHLDBLKDIS                              :  1;  // Bits 9:9
+    U32 BLKWRPOSTVC1                            :  1;  // Bits 10:10
+    U32 DIS_VLW_PEG                             :  1;  // Bits 11:11
+    U32 SPECRDDIS                               :  1;  // Bits 12:12
+    U32 IR_RSRV_CTL                             :  1;  // Bits 13:13
+    U32 RSVD                                    :  18;  // Bits 31:14
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MPVTDTRK_CR_HCTL0_IMPH_STRUCT;
+
+typedef union {
+  struct {
+    U32                                         :  4;  // Bits 3:0
+    U64 REGBAR                                  :  35;  // Bits 38:4
+    U32                                         :  25;  // Bits 63:39
+  } Bits;
+  U64 Data;
+  U32 Data32[2];
+  U16 Data16[4];
+  U8  Data8[8];
+} MPVTDTRK_CR_REGBAR_IMPH_STRUCT;
+
+typedef union {
+  struct {
+    U32 THERMAL_MONITOR_STATUS                  :  1;  // Bits 0:0
+    U32 THERMAL_MONITOR_LOG                     :  1;  // Bits 1:1
+    U32 PROCHOT_STATUS                          :  1;  // Bits 2:2
+    U32 PROCHOT_LOG                             :  1;  // Bits 3:3
+    U32 OUT_OF_SPEC_STATUS                      :  1;  // Bits 4:4
+    U32 OUT_OF_SPEC_LOG                         :  1;  // Bits 5:5
+    U32 THRESHOLD1_STATUS                       :  1;  // Bits 6:6
+    U32 THRESHOLD1_LOG                          :  1;  // Bits 7:7
+    U32 THRESHOLD2_STATUS                       :  1;  // Bits 8:8
+    U32 THRESHOLD2_LOG                          :  1;  // Bits 9:9
+    U32 POWER_LIMITATION_STATUS                 :  1;  // Bits 10:10
+    U32 POWER_LIMITATION_LOG                    :  1;  // Bits 11:11
+    U32                                         :  4;  // Bits 15:12
+    U32 Temperature                             :  7;  // Bits 22:16
+    U32                                         :  4;  // Bits 26:23
+    U32 Resolution                              :  4;  // Bits 30:27
+    U32 Valid                                   :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_STRUCT;
+
+typedef union {
+  struct {
+    U32 WARM_THRESHOLD_STATUS                   :  1;  // Bits 0:0
+    U32 WARM_THRESHOLD_LOG                      :  1;  // Bits 1:1
+    U32 HOT_THRESHOLD_STATUS                    :  1;  // Bits 2:2
+    U32 HOT_THRESHOLD_LOG                       :  1;  // Bits 3:3
+    U32 REFRESH2X_STATUS                        :  1;  // Bits 4:4
+    U32 REFRESH2X_LOG                           :  1;  // Bits 5:5
+    U32 FORCEMEMPR_STATUS                       :  1;  // Bits 6:6
+    U32 FORCEMEMPR_LOG                          :  1;  // Bits 7:7
+    U32 THRESHOLD1_STATUS                       :  1;  // Bits 8:8
+    U32 THRESHOLD1_LOG                          :  1;  // Bits 9:9
+    U32 THRESHOLD2_STATUS                       :  1;  // Bits 10:10
+    U32 THRESHOLD2_LOG                          :  1;  // Bits 11:11
+    U32                                         :  20;  // Bits 31:12
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MPVTDTRK_CR_DDR_THERM_CAMARILLO_STATUS_IMPH_STRUCT;
+
+typedef union {
+  struct {
+    U32 LOCK                                    :  1;  // Bits 0:0
+    U32                                         :  31;  // Bits 31:1
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MPVTDTRK_CR_VTDTRKLCK_IMPH_STRUCT;
+
+typedef union {
+  struct {
+    U32 RDLIM                                   :  3;  // Bits 2:0
+    U32                                         :  1;  // Bits 3:3
+    U32 WRLIM                                   :  3;  // Bits 6:4
+    U32                                         :  24;  // Bits 30:7
+    U32 LOCK                                    :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MPCBOTRK_CR_REQLIM_IMPH_STRUCT;
+
+typedef union {
+  struct {
+    U32 VCPNPLIM                                :  3;  // Bits 2:0
+    U32                                         :  1;  // Bits 3:3
+    U32 VCPPLIM                                 :  3;  // Bits 6:4
+    U32                                         :  1;  // Bits 7:7
+    U32 VCMNPLIM                                :  3;  // Bits 10:8
+    U32                                         :  1;  // Bits 11:11
+    U32 VCMPLIM                                 :  3;  // Bits 14:12
+    U32                                         :  1;  // Bits 15:15
+    U32 VCPCMPLIM                               :  3;  // Bits 18:16
+    U32                                         :  1;  // Bits 19:19
+    U32 VCMCMPLIM                               :  3;  // Bits 22:20
+    U32                                         :  8;  // Bits 30:23
+    U32 LOCK                                    :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} HUBS_CR_DMIVCLIM_HUBS_STRUCT;
+
+typedef union {
+  struct {
+    U32 P0                                      :  1;  // Bits 0:0
+    U32 P1                                      :  1;  // Bits 1:1
+    U32 P2                                      :  1;  // Bits 2:2
+    U32 P3                                      :  1;  // Bits 3:3
+    U32                                         :  28;  // Bits 31:4
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} HUBS_CR_HUB0_PWRDN_OVRD_HUBS_STRUCT;
+
+typedef union {
+  struct {
+    U32 P0                                      :  1;  // Bits 0:0
+    U32 P1                                      :  1;  // Bits 1:1
+    U32 P2                                      :  1;  // Bits 2:2
+    U32 P3                                      :  1;  // Bits 3:3
+    U32                                         :  28;  // Bits 31:4
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} HUBS_CR_HUB1_PWRDN_OVRD_HUBS_STRUCT;
+
+typedef union {
+  struct {
+    U32 P0                                      :  1;  // Bits 0:0
+    U32 P1                                      :  1;  // Bits 1:1
+    U32 P2                                      :  1;  // Bits 2:2
+    U32 P3                                      :  1;  // Bits 3:3
+    U32                                         :  28;  // Bits 31:4
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} HUBS_CR_HUB2_PWRDN_OVRD_HUBS_STRUCT;
+
+typedef union {
+  struct {
+    U32 BLK_GNT_P0                              :  1;  // Bits 0:0
+    U32 BLK_GNT_P1                              :  1;  // Bits 1:1
+    U32 BLK_GNT_P2                              :  1;  // Bits 2:2
+    U32 BLK_PUT_P0                              :  1;  // Bits 3:3
+    U32 BLK_PUT_P1                              :  1;  // Bits 4:4
+    U32 BLK_PUT_P2                              :  1;  // Bits 5:5
+    U32 BLK_PUT_P3                              :  1;  // Bits 6:6
+    U32 NO_CHAIN_P0                             :  1;  // Bits 7:7
+    U32 NO_CHAIN_P1                             :  1;  // Bits 8:8
+    U32 NO_CHAIN_P2                             :  1;  // Bits 9:9
+    U32 SLOW_UP_P0                              :  1;  // Bits 10:10
+    U32 SLOW_UP_P1                              :  1;  // Bits 11:11
+    U32 SLOW_UP_P2                              :  1;  // Bits 12:12
+    U32 SLOW_DN_P0                              :  1;  // Bits 13:13
+    U32 SLOW_DN_P1                              :  1;  // Bits 14:14
+    U32 SLOW_DN_P2                              :  1;  // Bits 15:15
+    U32 SLOW_DN_P3                              :  1;  // Bits 16:16
+    U32 SLOWER_CMD                              :  1;  // Bits 17:17
+    U32 DMI_NOPUSH                              :  1;  // Bits 18:18
+    U32 RO_PASS_NP                              :  1;  // Bits 19:19
+    U32 RST_CRD_P3                              :  1;  // Bits 20:20
+    U32                                         :  11;  // Bits 31:21
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} HUBS_CR_HUB0_DEFEATURE_HUBS_STRUCT;
+
+typedef union {
+  struct {
+    U32 BLK_GNT_P1                              :  1;  // Bits 0:0
+    U32 BLK_GNT_P2                              :  1;  // Bits 1:1
+    U32 BLK_PUT_P0                              :  1;  // Bits 2:2
+    U32 BLK_PUT_P1                              :  1;  // Bits 3:3
+    U32 BLK_PUT_P2                              :  1;  // Bits 4:4
+    U32 BLK_PUT_P3                              :  1;  // Bits 5:5
+    U32 NO_CHAIN_P1                             :  1;  // Bits 6:6
+    U32 NO_CHAIN_P2                             :  1;  // Bits 7:7
+    U32 SLOW_UP_P0                              :  1;  // Bits 8:8
+    U32 SLOW_UP_P1                              :  1;  // Bits 9:9
+    U32 SLOW_UP_P2                              :  1;  // Bits 10:10
+    U32 SLOW_DN_P1                              :  1;  // Bits 11:11
+    U32 SLOW_DN_P2                              :  1;  // Bits 12:12
+    U32 SLOW_DN_P3                              :  1;  // Bits 13:13
+    U32 SLOWER_CMD                              :  1;  // Bits 14:14
+    U32 RO_PASS_NP                              :  1;  // Bits 15:15
+    U32 RST_CRD_P0                              :  1;  // Bits 16:16
+    U32 RST_CRD_P3                              :  1;  // Bits 17:17
+    U32                                         :  14;  // Bits 31:18
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} HUBS_CR_HUB1_DEFEATURE_HUBS_STRUCT;
+
+typedef union {
+  struct {
+    U32 BLK_GNT_P1                              :  1;  // Bits 0:0
+    U32 BLK_GNT_P2                              :  1;  // Bits 1:1
+    U32 BLK_PUT_P0                              :  1;  // Bits 2:2
+    U32 BLK_PUT_P1                              :  1;  // Bits 3:3
+    U32 BLK_PUT_P2                              :  1;  // Bits 4:4
+    U32 NO_CHAIN_P1                             :  1;  // Bits 5:5
+    U32 NO_CHAIN_P2                             :  1;  // Bits 6:6
+    U32 SLOW_UP_P0                              :  1;  // Bits 7:7
+    U32 SLOW_UP_P1                              :  1;  // Bits 8:8
+    U32 SLOW_UP_P2                              :  1;  // Bits 9:9
+    U32 SLOW_DN_P1                              :  1;  // Bits 10:10
+    U32 SLOW_DN_P2                              :  1;  // Bits 11:11
+    U32 SLOWER_CMD                              :  1;  // Bits 12:12
+    U32 RST_CRD_P0                              :  1;  // Bits 13:13
+    U32                                         :  18;  // Bits 31:14
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} HUBS_CR_HUB2_DEFEATURE_HUBS_STRUCT;
+
+typedef union {
+  struct {
+    U32 PCIPWRGAT                               :  1;  // Bits 0:0
+    U32                                         :  31;  // Bits 31:1
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} HUBS_CR_PEGCTL_HUBS_STRUCT;
+
+typedef union {
+  struct {
+    U32 H0_EMPTY                                :  1;  // Bits 0:0
+    U32 H1_EMPTY                                :  1;  // Bits 1:1
+    U32 H2_EMPTY                                :  1;  // Bits 2:2
+    U32                                         :  29;  // Bits 31:3
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} HUBS_CR_HUB_EMPTY_HUBS_STRUCT;
+
+typedef union {
+  struct {
+    U32 REQ_VLD_P0                              :  1;  // Bits 0:0
+    U32 REQ_VLD_P1                              :  1;  // Bits 1:1
+    U32 REQ_VLD_P2                              :  1;  // Bits 2:2
+    U32 REQ_VLD_P3                              :  1;  // Bits 3:3
+    U32 TNX_VLD_P0                              :  1;  // Bits 4:4
+    U32 TNX_VLD_P1                              :  1;  // Bits 5:5
+    U32 TNX_VLD_P2                              :  1;  // Bits 6:6
+    U32 TNX_VLD_P3                              :  1;  // Bits 7:7
+    U32                                         :  24;  // Bits 31:8
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} HUBS_CR_HUB0_STATUS_HUBS_STRUCT;
+
+typedef union {
+  struct {
+    U32 REQ_VLD_P0                              :  1;  // Bits 0:0
+    U32 REQ_VLD_P1                              :  1;  // Bits 1:1
+    U32 REQ_VLD_P2                              :  1;  // Bits 2:2
+    U32 REQ_VLD_P3                              :  1;  // Bits 3:3
+    U32 TNX_VLD_P0                              :  1;  // Bits 4:4
+    U32 TNX_VLD_P1                              :  1;  // Bits 5:5
+    U32 TNX_VLD_P2                              :  1;  // Bits 6:6
+    U32 TNX_VLD_P3                              :  1;  // Bits 7:7
+    U32                                         :  24;  // Bits 31:8
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} HUBS_CR_HUB1_STATUS_HUBS_STRUCT;
+
+typedef union {
+  struct {
+    U32 REQ_VLD_P0                              :  1;  // Bits 0:0
+    U32 REQ_VLD_P1                              :  1;  // Bits 1:1
+    U32 REQ_VLD_P2                              :  1;  // Bits 2:2
+    U32 REQ_VLD_P3                              :  1;  // Bits 3:3
+    U32 TNX_VLD_P0                              :  1;  // Bits 4:4
+    U32 TNX_VLD_P1                              :  1;  // Bits 5:5
+    U32 TNX_VLD_P2                              :  1;  // Bits 6:6
+    U32 TNX_VLD_P3                              :  1;  // Bits 7:7
+    U32                                         :  24;  // Bits 31:8
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} HUBS_CR_HUB2_STATUS_HUBS_STRUCT;
+
+typedef union {
+  struct {
+    U32 Data                                    :  18;  // Bits 17:0
+    U32                                         :  13;  // Bits 30:18
+    U32 VORANGE                                 :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} HUBS_CR_VISA_CTL_SABHUB0S_HUBS_STRUCT;
+
+typedef union {
+  struct {
+    U32 Data                                    :  18;  // Bits 17:0
+    U32                                         :  13;  // Bits 30:18
+    U32 VORANGE                                 :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} HUBS_CR_VISA_CTL_SABHUB1S_HUBS_STRUCT;
+
+typedef union {
+  struct {
+    U32 Data                                    :  18;  // Bits 17:0
+    U32                                         :  13;  // Bits 30:18
+    U32 VORANGE                                 :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} HUBS_CR_VISA_CTL_SABHUB2S_HUBS_STRUCT;
+
+typedef union {
+  struct {
+    U32 DATA                                    :  32;  // Bits 31:0
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} HUBS_CR_MBOX_WR_DATA_HUBS_STRUCT;
+
+typedef union {
+  struct {
+    U32 DATA                                    :  32;  // Bits 31:0
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} HUBS_CR_MBOX_RD_DATA_HUBS_STRUCT;
+
+typedef union {
+  struct {
+    U32 ADDR                                    :  32;  // Bits 31:0
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} HUBS_CR_MBOX_ADDR_LO_HUBS_STRUCT;
+
+typedef union {
+  struct {
+    U32 ADDR                                    :  32;  // Bits 31:0
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} HUBS_CR_MBOX_ADDR_HI_HUBS_STRUCT;
+
+typedef union {
+  struct {
+    U32 FBE                                     :  4;  // Bits 3:0
+    U32 LBE                                     :  4;  // Bits 7:4
+    U32 TAG                                     :  8;  // Bits 15:8
+    U32 RQID                                    :  16;  // Bits 31:16
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} HUBS_CR_MBOX_CMD_LO_HUBS_STRUCT;
+
+typedef union {
+  struct {
+    U32 AT                                      :  2;  // Bits 1:0
+    U32 POISON                                  :  1;  // Bits 2:2
+    U32 LENGTH                                  :  5;  // Bits 7:3
+    U32 RELAXED                                 :  1;  // Bits 8:8
+    U32 NOSNOOP                                 :  1;  // Bits 9:9
+    U32 CHAIN                                   :  1;  // Bits 10:10
+    U32 CTYPE                                   :  5;  // Bits 15:11
+    U32 FMT                                     :  2;  // Bits 17:16
+    U32 TC                                      :  4;  // Bits 21:18
+    U32 RESERVED                                :  2;  // Bits 23:22
+    U32 DMI_PRIV                                :  1;  // Bits 24:24
+    U32 CHID                                    :  4;  // Bits 28:25
+    U32 RTYPE                                   :  2;  // Bits 30:29
+    U32 START                                   :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} HUBS_CR_MBOX_CMD_HI_HUBS_STRUCT;
+
+typedef union {
+  struct {
+    U32 ENABLE                                  :  1;  // Bits 0:0
+    U32 LOCK_IA                                 :  1;  // Bits 1:1
+    U32 RESET                                   :  1;  // Bits 2:2
+    U32 BLK_CYCLES                              :  6;  // Bits 8:3
+    U32 WR_DWORD_SEL                            :  4;  // Bits 12:9
+    U32 RD_DWORD_SEL                            :  4;  // Bits 16:13
+    U32 RPT_CMD_CNT                             :  6;  // Bits 22:17
+    U32 RPT_NXT_ADDR                            :  1;  // Bits 23:23
+    U32 RPT_NXT_PAGE                            :  1;  // Bits 24:24
+    U32 DIS_CMP_INV                             :  1;  // Bits 25:25
+    U32 FSM_STATE                               :  4;  // Bits 29:26
+    U32 P2P_ALL                                 :  1;  // Bits 30:30
+    U32 SPARE                                   :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} HUBS_CR_MBOX_CFG_HUBS_STRUCT;
+
+typedef union {
+  struct {
+    U32 FSM_STATE                               :  4;  // Bits 3:0
+    U32 RPT_CMD_CNT                             :  6;  // Bits 9:4
+    U32 OPCODE                                  :  7;  // Bits 16:10
+    U32 WR_DWORD_SEL                            :  4;  // Bits 20:17
+    U32 RD_DWORD_SEL                            :  4;  // Bits 24:21
+    U32 P2P_RD_UP                               :  1;  // Bits 25:25
+    U32 P2P_RD_DN                               :  1;  // Bits 26:26
+    U32 SPARE                                   :  5;  // Bits 31:27
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} HUBS_CR_MBOX_STATUS_HUBS_STRUCT;
+
+typedef union {
+  struct {
+    U32 XTM_CHID                                :  9;  // Bits 8:0
+    U32 NP                                      :  1;  // Bits 9:9
+    U32 PC                                      :  1;  // Bits 10:10
+    U32                                         :  21;  // Bits 31:11
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} HUBS_CR_HUB0_BLOCK_UP_HUBS_STRUCT;
+
+typedef union {
+  struct {
+    U32 DMIVC0_PMIN                             :  3;  // Bits 2:0
+    U32 P10VC0_PMIN                             :  3;  // Bits 5:3
+    U32 P11VC0_PMIN                             :  3;  // Bits 8:6
+    U32 P12VC0_PMIN                             :  3;  // Bits 11:9
+    U32 DEVC0_PMIN                              :  3;  // Bits 14:12
+    U32 DMIVCP_PMIN                             :  3;  // Bits 17:15
+    U32 DMIVCM_PMIN                             :  3;  // Bits 20:18
+    U32 DMIVC1_PMIN                             :  3;  // Bits 23:21
+    U32                                         :  8;  // Bits 31:24
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MPRDRTRN_CR_CRDTCTL0_IMPH_STRUCT;
+
+typedef union {
+  struct {
+    U32 DMIVC0_NPMIN                            :  3;  // Bits 2:0
+    U32 P10VC0_NPMIN                            :  3;  // Bits 5:3
+    U32 P11VC0_NPMIN                            :  3;  // Bits 8:6
+    U32 P12VC0_NPMIN                            :  3;  // Bits 11:9
+    U32 DEVC0_NPMIN                             :  3;  // Bits 14:12
+    U32 DMIVCP_NPMIN                            :  3;  // Bits 17:15
+    U32 DMIVCM_NPMIN                            :  3;  // Bits 20:18
+    U32 DMIVC1_NPMIN                            :  3;  // Bits 23:21
+    U32                                         :  8;  // Bits 31:24
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MPRDRTRN_CR_CRDTCTL1_IMPH_STRUCT;
+
+typedef union {
+  struct {
+    U32 DMIVC0_RRMIN                            :  3;  // Bits 2:0
+    U32 P10VC0_RRMIN                            :  3;  // Bits 5:3
+    U32 P11VC0_RRMIN                            :  3;  // Bits 8:6
+    U32 P12VC0_RRMIN                            :  3;  // Bits 11:9
+    U32 DEVC0_RRMIN                             :  3;  // Bits 14:12
+    U32 DMIVCP_RRMIN                            :  3;  // Bits 17:15
+    U32 DMIVCM_RRMIN                            :  3;  // Bits 20:18
+    U32 DMIVC1_RRMIN                            :  3;  // Bits 23:21
+    U32 DEVC1_RRMIN                             :  6;  // Bits 29:24
+    U32                                         :  2;  // Bits 31:30
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MPRDRTRN_CR_CRDTCTL2_IMPH_STRUCT;
+
+typedef union {
+  struct {
+    U32 IOTRK_SHRD                              :  6;  // Bits 5:0
+    U32 RRTRK_SHRD                              :  7;  // Bits 12:6
+    U32                                         :  19;  // Bits 31:13
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MPRDRTRN_CR_CRDTCTL3_IMPH_STRUCT;
+
+typedef union {
+  struct {
+    U32 DMIVC0_PMAX                             :  5;  // Bits 4:0
+    U32 P10VC0_PMAX                             :  5;  // Bits 9:5
+    U32 P11VC0_PMAX                             :  5;  // Bits 14:10
+    U32 P12VC0_PMAX                             :  5;  // Bits 19:15
+    U32 DEVC0_PMAX                              :  5;  // Bits 24:20
+    U32                                         :  7;  // Bits 31:25
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MPRDRTRN_CR_CRDTCTL4_IMPH_STRUCT;
+
+typedef union {
+  struct {
+    U32 DMIVCP_PMAX                             :  5;  // Bits 4:0
+    U32 DMIVCM_PMAX                             :  5;  // Bits 9:5
+    U32 DMIVC1_PMAX                             :  5;  // Bits 14:10
+    U32                                         :  17;  // Bits 31:15
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MPRDRTRN_CR_CRDTCTL5_IMPH_STRUCT;
+
+typedef union {
+  struct {
+    U32 DMIVC0_NPMAX                            :  5;  // Bits 4:0
+    U32 P10VC0_NPMAX                            :  5;  // Bits 9:5
+    U32 P11VC0_NPMAX                            :  5;  // Bits 14:10
+    U32 P12VC0_NPMAX                            :  5;  // Bits 19:15
+    U32 DEVC0_NPMAX                             :  5;  // Bits 24:20
+    U32                                         :  7;  // Bits 31:25
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MPRDRTRN_CR_CRDTCTL6_IMPH_STRUCT;
+
+typedef union {
+  struct {
+    U32 DMIVCP_NPMAX                            :  5;  // Bits 4:0
+    U32 DMIVCM_NPMAX                            :  5;  // Bits 9:5
+    U32 DMIVC1_NPMAX                            :  5;  // Bits 14:10
+    U32                                         :  17;  // Bits 31:15
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MPRDRTRN_CR_CRDTCTL7_IMPH_STRUCT;
+
+typedef union {
+  struct {
+    U32 DATA                                    :  18;  // Bits 17:0
+    U32                                         :  13;  // Bits 30:18
+    U32 VORANGE                                 :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MPRDRTRN_CR_VISA_CTL_MPIORDTRKS_IMPH_STRUCT;
+
+typedef union {
+  struct {
+    U32 DATA                                    :  32;  // Bits 31:0
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MPRDRTRN_CR_VISA_XBAR_MPIORDTRKS_IMPH_STRUCT;
+
+typedef union {
+  struct {
+    U32 DATA                                    :  18;  // Bits 17:0
+    U32                                         :  13;  // Bits 30:18
+    U32 VORANGE                                 :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MPRDRTRN_CR_VISA_CTL_MPIOTRKS_IMPH_STRUCT;
+
+typedef union {
+  struct {
+    U32 VC                                      :  4;  // Bits 3:0
+    U32 FMT_CMDTYPE                             :  6;  // Bits 9:4
+    U32 TC                                      :  4;  // Bits 13:10
+    U32 NS                                      :  1;  // Bits 14:14
+    U32 RO                                      :  1;  // Bits 15:15
+    U32 LENGTH                                  :  5;  // Bits 20:16
+    U32 EP                                      :  1;  // Bits 21:21
+    U32                                         :  10;  // Bits 31:22
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MPRDRTRN_CR_PRIMDN_MASK1_IMPH_STRUCT;
+
+typedef union {
+  struct {
+    U32 RQID                                    :  16;  // Bits 15:0
+    U32 TAG                                     :  8;  // Bits 23:16
+    U32 LBEFBE_MSGTYPE                          :  8;  // Bits 31:24
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MPRDRTRN_CR_PRIMDN_MASK2_IMPH_STRUCT;
+
+typedef union {
+  struct {
+    U32 ADDR_31_0                               :  32;  // Bits 31:0
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MPRDRTRN_CR_PRIMDN_MASK3_IMPH_STRUCT;
+
+typedef union {
+  struct {
+    U32 ADDR_63_32                              :  32;  // Bits 31:0
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MPRDRTRN_CR_PRIMDN_MASK4_IMPH_STRUCT;
+
+typedef union {
+  struct {
+    U32 VC                                      :  4;  // Bits 3:0
+    U32 FMT_CMDTYPE                             :  6;  // Bits 9:4
+    U32 TC                                      :  4;  // Bits 13:10
+    U32 EP                                      :  1;  // Bits 14:14
+    U32 NS                                      :  1;  // Bits 15:15
+    U32 RO                                      :  1;  // Bits 16:16
+    U32 LENGTH                                  :  5;  // Bits 21:17
+    U32                                         :  10;  // Bits 31:22
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MPRDRTRN_CR_PRIMDN_COMP1_IMPH_STRUCT;
+
+typedef union {
+  struct {
+    U32 RQID                                    :  16;  // Bits 15:0
+    U32 TAG                                     :  8;  // Bits 23:16
+    U32 LBEFBE_MSGTYPE                          :  8;  // Bits 31:24
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MPRDRTRN_CR_PRIMDN_COMP2_IMPH_STRUCT;
+
+typedef union {
+  struct {
+    U32 ADDR_31_0                               :  32;  // Bits 31:0
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MPRDRTRN_CR_PRIMDN_COMP3_IMPH_STRUCT;
+
+typedef union {
+  struct {
+    U32 ADDR_63_32                              :  32;  // Bits 31:0
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MPRDRTRN_CR_PRIMDN_COMP4_IMPH_STRUCT;
+
+typedef union {
+  struct {
+    U32 ENABLE                                  :  1;  // Bits 0:0
+    U32 TRIGGERED                               :  1;  // Bits 1:1
+    U32 STALL_DNARB                             :  1;  // Bits 2:2
+    U32                                         :  20;  // Bits 22:3
+    U32 STALL_DELAY                             :  9;  // Bits 31:23
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MPRDRTRN_CR_PRIMDN_TRIGGER_IMPH_STRUCT;
+
+typedef union {
+  struct {
+    U32 DMIVC0_RRMAX                            :  6;  // Bits 5:0
+    U32 P10VC0_RRMAX                            :  6;  // Bits 11:6
+    U32 P11VC0_RRMAX                            :  6;  // Bits 17:12
+    U32 P12VC0_RRMAX                            :  6;  // Bits 23:18
+    U32 DEVC0_RRMAX                             :  6;  // Bits 29:24
+    U32                                         :  2;  // Bits 31:30
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MPRDRTRN_CR_CRDTCTL8_IMPH_STRUCT;
+
+typedef union {
+  struct {
+    U32 DMIVCP_RRMAX                            :  6;  // Bits 5:0
+    U32 DMIVCM_RRMAX                            :  6;  // Bits 11:6
+    U32 DMIVC1_RRMAX                            :  6;  // Bits 17:12
+    U32 DEVC1_RRMAX                             :  6;  // Bits 23:18
+    U32                                         :  8;  // Bits 31:24
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MPRDRTRN_CR_CRDTCTL9_IMPH_STRUCT;
+
+typedef union {
+  struct {
+    U32 LIM                                     :  16;  // Bits 15:0
+    U32 MSK                                     :  3;  // Bits 18:16
+    U32                                         :  13;  // Bits 31:19
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MPRDRTRN_CR_PCIE_POPUP_CTL_IMPH_STRUCT;
+
+typedef union {
+  struct {
+    U32 FUNNUM                                  :  3;  // Bits 2:0
+    U32 DEVNUM                                  :  5;  // Bits 7:3
+    U32 BUSNUM                                  :  8;  // Bits 15:8
+    U32 BARNUM                                  :  3;  // Bits 18:16
+    U32                                         :  13;  // Bits 31:19
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MPRDRTRN_CR_VDMBDFBARSSKU_IMPH_STRUCT;
+
+typedef union {
+  struct {
+    U32 LOCK                                    :  1;  // Bits 0:0
+    U32                                         :  31;  // Bits 31:1
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MPRDRTRN_CR_CRDTLCK_IMPH_STRUCT;
+
+typedef union {
+  struct {
+    U32 VCPNPLIM                                :  3;  // Bits 2:0
+    U32                                         :  1;  // Bits 3:3
+    U32 VCPPLIM                                 :  3;  // Bits 6:4
+    U32                                         :  1;  // Bits 7:7
+    U32 VCMNPLIM                                :  3;  // Bits 10:8
+    U32                                         :  1;  // Bits 11:11
+    U32 VCMPLIM                                 :  3;  // Bits 14:12
+    U32                                         :  1;  // Bits 15:15
+    U32 VC0VTDLIM                               :  3;  // Bits 18:16
+    U32                                         :  1;  // Bits 19:19
+    U32 VCPVTDLIM                               :  3;  // Bits 22:20
+    U32                                         :  9;  // Bits 31:23
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MPMCARB_CR_VCLIM0_IMPH_STRUCT;
+
+typedef union {
+  struct {
+    U32 IARD                                    :  3;  // Bits 2:0
+    U32                                         :  1;  // Bits 3:3
+    U32 IAWR                                    :  3;  // Bits 6:4
+    U32                                         :  1;  // Bits 7:7
+    U32 VTDL3                                   :  3;  // Bits 10:8
+    U32                                         :  1;  // Bits 11:11
+    U32 VTDNL3                                  :  3;  // Bits 14:12
+    U32                                         :  17;  // Bits 31:15
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MPMCARB_CR_VCLIM1_IMPH_STRUCT;
+
+typedef union {
+  struct {
+    U32 VC1_WR_CNFLT                            :  1;  // Bits 0:0
+    U32 VC1_RD_CNFLT                            :  1;  // Bits 1:1
+    U32                                         :  30;  // Bits 31:2
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MPMCARB_CR_ATMC_STS_IMPH_STRUCT;
+
+typedef union {
+  struct {
+    U32 DATA                                    :  18;  // Bits 17:0
+    U32                                         :  13;  // Bits 30:18
+    U32 VORANGE                                 :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MPMCARB_CR_VISA_CTL_MPMCARBS_F_IMPH_STRUCT;
+
+typedef union {
+  struct {
+    U32 DATA                                    :  18;  // Bits 17:0
+    U32                                         :  13;  // Bits 30:18
+    U32 VORANGE                                 :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MPMCARB_CR_VISA_CTL_MPMCARBS_D_IMPH_STRUCT;
+
+typedef union {
+  struct {
+    U32 LOCK                                    :  1;  // Bits 0:0
+    U32                                         :  31;  // Bits 31:1
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MPMCARB_CR_MCARBLCK_IMPH_STRUCT;
+
+typedef union {
+  struct {
+    U32 DATA                                    :  32;  // Bits 31:0
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} PCU_CR_CAMARILLO_MAILBOX_DATA0_PCU_STRUCT;
+
+typedef union {
+  struct {
+    U32 DATA                                    :  32;  // Bits 31:0
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} PCU_CR_CAMARILLO_MAILBOX_DATA1_PCU_STRUCT;
+
+typedef union {
+  struct {
+    U32 COMMAND                                 :  8;  // Bits 7:0
+    U32 ADDR_CNTL                               :  21;  // Bits 28:8
+    U32                                         :  2;  // Bits 30:29
+    U32 RUN_BUSY                                :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} PCU_CR_CAMARILLO_MAILBOX_INTERFACE_PCU_STRUCT;
+
+typedef union {
+  struct {
+    U32 HIGH_TEMP_INT_ENABLE                    :  1;  // Bits 0:0
+    U32 LOW_TEMP_INT_ENABLE                     :  1;  // Bits 1:1
+    U32 PROCHOT_INT_ENABLE                      :  1;  // Bits 2:2
+    U32                                         :  1;  // Bits 3:3
+    U32 OUT_OF_SPEC_INT_ENABLE                  :  1;  // Bits 4:4
+    U32                                         :  3;  // Bits 7:5
+    U32 THRESHOLD_1_REL_TEMP                    :  7;  // Bits 14:8
+    U32 THRESHOLD_1_INT_ENABLE                  :  1;  // Bits 15:15
+    U32 THRESHOLD_2_REL_TEMP                    :  7;  // Bits 22:16
+    U32 THRESHOLD_2_INT_ENABLE                  :  1;  // Bits 23:23
+    U32 POWER_INT_ENABLE                        :  1;  // Bits 24:24
+    U32                                         :  7;  // Bits 31:25
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} PCU_CR_PACKAGE_THERM_CAMARILLO_INTERRUPT_PCU_STRUCT;
+
+typedef union {
+  struct {
+    U32 OLTM_ENABLE                             :  1;  // Bits 0:0
+    U32 CLTM_ENABLE                             :  1;  // Bits 1:1
+    U32 REFRESH_2X_MODE                         :  2;  // Bits 3:2
+    U32 EXTTS_ENABLE                            :  1;  // Bits 4:4
+    U32 LOCK_PTM_REGS_PCU                       :  1;  // Bits 5:5
+    U32 PDWN_CONFIG_CTL                         :  1;  // Bits 6:6
+    U32 DISABLE_DRAM_TS                         :  1;  // Bits 7:7
+    U32                                         :  24;  // Bits 31:8
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} PCU_CR_DDR_PTM_CTL_PCU_STRUCT;
+
+typedef union {
+  struct {
+    U32 SCALEFACTOR                             :  3;  // Bits 2:0
+    U32                                         :  29;  // Bits 31:3
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} PCU_CR_DDR_ENERGY_SCALEFACTOR_PCU_STRUCT;
+
+typedef union {
+  struct {
+    U32 CH0                                     :  8;  // Bits 7:0
+    U32 CH1                                     :  8;  // Bits 15:8
+    U32                                         :  16;  // Bits 31:16
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} PCU_CR_DDR_RAPL_CHANNEL_POWER_FLOOR_PCU_STRUCT;
+
+typedef union {
+  struct {
+    U32 CH0_DIMM0                               :  2;  // Bits 1:0
+    U32 CH0_DIMM1                               :  2;  // Bits 3:2
+    U32                                         :  4;  // Bits 7:4
+    U32 CH1_DIMM0                               :  2;  // Bits 9:8
+    U32 CH1_DIMM1                               :  2;  // Bits 11:10
+    U32                                         :  20;  // Bits 31:12
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} PCU_CR_DDR_THERM_PERDIMM_STATUS_PCU_STRUCT;
+
+typedef union {
+  struct {
+    U32 DIMM0                                   :  8;  // Bits 7:0
+    U32 DIMM1                                   :  8;  // Bits 15:8
+    U32                                         :  16;  // Bits 31:16
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} PCU_CR_DDR_WARM_THRESHOLD_CH0_PCU_STRUCT;
+
+typedef union {
+  struct {
+    U32 DIMM0                                   :  8;  // Bits 7:0
+    U32 DIMM1                                   :  8;  // Bits 15:8
+    U32                                         :  16;  // Bits 31:16
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} PCU_CR_DDR_WARM_THRESHOLD_CH1_PCU_STRUCT;
+
+typedef union {
+  struct {
+    U32 DIMM0                                   :  8;  // Bits 7:0
+    U32 DIMM1                                   :  8;  // Bits 15:8
+    U32                                         :  16;  // Bits 31:16
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} PCU_CR_DDR_HOT_THRESHOLD_CH0_PCU_STRUCT;
+
+typedef union {
+  struct {
+    U32 DIMM0                                   :  8;  // Bits 7:0
+    U32 DIMM1                                   :  8;  // Bits 15:8
+    U32                                         :  16;  // Bits 31:16
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} PCU_CR_DDR_HOT_THRESHOLD_CH1_PCU_STRUCT;
+
+typedef union {
+  struct {
+    U32 ENABLE_WARM_INTERRUPT                   :  1;  // Bits 0:0
+    U32                                         :  1;  // Bits 1:1
+    U32 ENABLE_HOT_INTERRUPT                    :  1;  // Bits 2:2
+    U32                                         :  1;  // Bits 3:3
+    U32 ENABLE_2X_REFRESH_INTERRUPT             :  1;  // Bits 4:4
+    U32                                         :  3;  // Bits 7:5
+    U32 ENABLE_THRESHOLD1_INTERRUPT             :  1;  // Bits 8:8
+    U32                                         :  1;  // Bits 9:9
+    U32 ENABLE_THRESHOLD2_INTERRUPT             :  1;  // Bits 10:10
+    U32                                         :  5;  // Bits 15:11
+    U32 POLICY_FREE_THRESHOLD1                  :  8;  // Bits 23:16
+    U32 POLICY_FREE_THRESHOLD2                  :  8;  // Bits 31:24
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} PCU_CR_DDR_THERM_CAMARILLO_INTERRUPT_PCU_STRUCT;
+
+typedef union {
+  struct {
+    U32 DDR_VOLTAGE                             :  3;  // Bits 2:0
+    U32                                         :  29;  // Bits 31:3
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} PCU_CR_DDR_VOLTAGE_PCU_STRUCT;
+
+typedef union {
+  struct {
+    U32 THERM_MARGIN                            :  16;  // Bits 15:0
+    U32                                         :  16;  // Bits 31:16
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} PCU_CR_PACKAGE_THERM_MARGIN_PCU_STRUCT;
+
+typedef union {
+  struct {
+    U32 DIMM0                                   :  8;  // Bits 7:0
+    U32 DIMM1                                   :  8;  // Bits 15:8
+    U32                                         :  16;  // Bits 31:16
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} PCU_CR_DDR_DIMM_TEMPERATURE_CH0_PCU_STRUCT;
+
+typedef union {
+  struct {
+    U32 DIMM0                                   :  8;  // Bits 7:0
+    U32 DIMM1                                   :  8;  // Bits 15:8
+    U32                                         :  16;  // Bits 31:16
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} PCU_CR_DDR_DIMM_TEMPERATURE_CH1_PCU_STRUCT;
+
+typedef union {
+  struct {
+    U32 TEMPERATURE                             :  8;  // Bits 7:0
+    U32                                         :  24;  // Bits 31:8
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} PCU_CR_DDR_DIMM_HOTTEST_ABSOLUTE_PCU_STRUCT;
+
+typedef union {
+  struct {
+    U32 TEMPERATURE                             :  8;  // Bits 7:0
+    U32                                         :  24;  // Bits 31:8
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} PCU_CR_DDR_DIMM_HOTTEST_RELATIVE_PCU_STRUCT;
+
+typedef union {
+  struct {
+    U32 DIMM0                                   :  16;  // Bits 15:0
+    U32 DIMM1                                   :  16;  // Bits 31:16
+    U32                                         :  32;  // Bits 63:32
+  } Bits;
+  U64 Data;
+  U32 Data32[2];
+  U16 Data16[4];
+  U8  Data8[8];
+} PCU_CR_DDR_THROTTLE_DURATION_CH0_PCU_STRUCT;
+
+typedef union {
+  struct {
+    U32 DIMM0                                   :  16;  // Bits 15:0
+    U32 DIMM1                                   :  16;  // Bits 31:16
+    U32                                         :  32;  // Bits 63:32
+  } Bits;
+  U64 Data;
+  U32 Data32[2];
+  U16 Data16[4];
+  U8  Data8[8];
+} PCU_CR_DDR_THROTTLE_DURATION_CH1_PCU_STRUCT;
+
+typedef union {
+  struct {
+    U32 DIMM0                                   :  8;  // Bits 7:0
+    U32 DIMM1                                   :  8;  // Bits 15:8
+    U32                                         :  16;  // Bits 31:16
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} PCU_CR_DDR_WARM_BUDGET_CH0_PCU_STRUCT;
+
+typedef union {
+  struct {
+    U32 DIMM0                                   :  8;  // Bits 7:0
+    U32 DIMM1                                   :  8;  // Bits 15:8
+    U32                                         :  16;  // Bits 31:16
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} PCU_CR_DDR_WARM_BUDGET_CH1_PCU_STRUCT;
+
+typedef union {
+  struct {
+    U32 DIMM0                                   :  8;  // Bits 7:0
+    U32 DIMM1                                   :  8;  // Bits 15:8
+    U32                                         :  16;  // Bits 31:16
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} PCU_CR_DDR_HOT_BUDGET_CH0_PCU_STRUCT;
+
+typedef union {
+  struct {
+    U32 DIMM0                                   :  8;  // Bits 7:0
+    U32 DIMM1                                   :  8;  // Bits 15:8
+    U32                                         :  16;  // Bits 31:16
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} PCU_CR_DDR_HOT_BUDGET_CH1_PCU_STRUCT;
+
+typedef union {
+  struct {
+    U32 LIMIT1_POWER                            :  15;  // Bits 14:0
+    U32 LIMIT1_ENABLE                           :  1;  // Bits 15:15
+    U32                                         :  1;  // Bits 16:16
+    U32 LIMIT1_TIME_WINDOW_Y                    :  5;  // Bits 21:17
+    U32 LIMIT1_TIME_WINDOW_X                    :  2;  // Bits 23:22
+    U32                                         :  8;  // Bits 31:24
+    U32 LIMIT2_POWER                            :  15;  // Bits 46:32
+    U32 LIMIT2_ENABLE                           :  1;  // Bits 47:47
+    U32                                         :  1;  // Bits 48:48
+    U32 LIMIT2_TIME_WINDOW_Y                    :  5;  // Bits 53:49
+    U32 LIMIT2_TIME_WINDOW_X                    :  2;  // Bits 55:54
+    U32                                         :  7;  // Bits 62:56
+    U32 LOCKED                                  :  1;  // Bits 63:63
+  } Bits;
+  U64 Data;
+  U32 Data32[2];
+  U16 Data16[4];
+  U8  Data8[8];
+} PCU_CR_DDR_RAPL_LIMIT_PCU_STRUCT;
+
+typedef union {
+  struct {
+    U32 JOULES_CONSUMED                         :  32;  // Bits 31:0
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} PCU_CR_DDR_ENERGY_STATUS_PCU_STRUCT;
+
+typedef union {
+  struct {
+    U32 DURATION                                :  32;  // Bits 31:0
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} PCU_CR_DDR_RAPL_PERF_STATUS_PCU_STRUCT;
+
+typedef union {
+  struct {
+    U32 COUNTS                                  :  32;  // Bits 31:0
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} PCU_CR_PACKAGE_RAPL_PERF_STATUS_PCU_STRUCT;
+
+typedef union {
+  struct {
+    U32 IA_MIN_RATIO_REQUEST                    :  8;  // Bits 7:0
+    U32 CLR_MIN_RATIO_REQUEST                   :  8;  // Bits 15:8
+    U32                                         :  16;  // Bits 31:16
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} PCU_CR_GT_RATIOS_OVERRIDE_PCU_STRUCT;
+
+typedef union {
+  struct {
+    U32 DDR_ACCESS_TIME                         :  14;  // Bits 13:0
+    U32 RESERVED                                :  1;  // Bits 14:14
+    U32 CLR_ACCESS_TIME                         :  14;  // Bits 28:15
+    U32 NON_SNOOP_THRESHOLD_RESOLUTION          :  1;  // Bits 29:29
+    U32 SLOW_SNOOP_THRESHOLD_RESOLUTION         :  1;  // Bits 30:30
+    U32 FAST_SNOOP_THRESHOLD_RESOLUTION         :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} PCU_CR_PKGC_LTR_LATENCY_MEASUREMENTS_PCU_STRUCT;
+
+typedef union {
+  struct {
+    U32 PROCHOT_STATUS                          :  1;  // Bits 0:0
+    U32 THERMAL_STATUS                          :  1;  // Bits 1:1
+    U32 SPARE_IA_2                              :  1;  // Bits 2:2
+    U32 PBM_PL1_STATUS                          :  1;  // Bits 3:3
+    U32 PBM_PL2_STATUS                          :  1;  // Bits 4:4
+    U32 PBM_PLIA_STATUS                         :  1;  // Bits 5:5
+    U32 SPARE_IA_6                              :  1;  // Bits 6:6
+    U32 GTDRIVER_STATUS                         :  1;  // Bits 7:7
+    U32 VR_THERMALERT_STATUS                    :  1;  // Bits 8:8
+    U32 FUSE_MAX_TURBO_LIMIT_STATUS             :  1;  // Bits 9:9
+    U32 EDP_ICC_STATUS                          :  1;  // Bits 10:10
+    U32 TURBO_ATTEN_STATUS                      :  1;  // Bits 11:11
+    U32 SPARE_IA_12                             :  1;  // Bits 12:12
+    U32 SPARE_IA_13                             :  1;  // Bits 13:13
+    U32 SPARE_IA_14                             :  1;  // Bits 14:14
+    U32 SPARE_IA_15                             :  1;  // Bits 15:15
+    U32 PROCHOT_LOG                             :  1;  // Bits 16:16
+    U32 THERMAL_LOG                             :  1;  // Bits 17:17
+    U32 SPARE_IA_LOG_2                          :  1;  // Bits 18:18
+    U32 PBM_PL1_LOG                             :  1;  // Bits 19:19
+    U32 PBM_PL2_LOG                             :  1;  // Bits 20:20
+    U32 PBM_PLIA_LOG                            :  1;  // Bits 21:21
+    U32 SPARE_IA_LOG_6                          :  1;  // Bits 22:22
+    U32 GTDRIVER_LOG                            :  1;  // Bits 23:23
+    U32 VR_THERMALERT_LOG                       :  1;  // Bits 24:24
+    U32 FUSE_MAX_TURBO_LIMIT_LOG                :  1;  // Bits 25:25
+    U32 EDP_ICC_LOG                             :  1;  // Bits 26:26
+    U32 TURBO_ATTEN_LOG                         :  1;  // Bits 27:27
+    U32 SPARE_IA_LOG_12                         :  1;  // Bits 28:28
+    U32 SPARE_IA_LOG_13                         :  1;  // Bits 29:29
+    U32 SPARE_IA_LOG_14                         :  1;  // Bits 30:30
+    U32 SPARE_IA_LOG_15                         :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} PCU_CR_IA_PERF_LIMIT_REASONS_PCU_STRUCT;
+
+typedef union {
+  struct {
+    U32 PROCHOT_STATUS                          :  1;  // Bits 0:0
+    U32 THERMAL_STATUS                          :  1;  // Bits 1:1
+    U32 SPARE_GT_2                              :  1;  // Bits 2:2
+    U32 PBM_PL1_STATUS                          :  1;  // Bits 3:3
+    U32 PBM_PL2_STATUS                          :  1;  // Bits 4:4
+    U32 PBM_PLGT_STATUS                         :  1;  // Bits 5:5
+    U32 SPARE_GT_6                              :  1;  // Bits 6:6
+    U32 SPARE_GT_7                              :  1;  // Bits 7:7
+    U32 VR_THERMALERT_STATUS                    :  1;  // Bits 8:8
+    U32 SPARE_GT_9                              :  1;  // Bits 9:9
+    U32 EDP_ICC_STATUS                          :  1;  // Bits 10:10
+    U32 SPARE_GT_11                             :  1;  // Bits 11:11
+    U32 SPARE_GT_12                             :  1;  // Bits 12:12
+    U32 SPARE_GT_13                             :  1;  // Bits 13:13
+    U32 SPARE_GT_14                             :  1;  // Bits 14:14
+    U32 SPARE_GT_15                             :  1;  // Bits 15:15
+    U32 PROCHOT_LOG                             :  1;  // Bits 16:16
+    U32 THERMAL_LOG                             :  1;  // Bits 17:17
+    U32 SPARE_GT_LOG_2                          :  1;  // Bits 18:18
+    U32 PBM_PL1_LOG                             :  1;  // Bits 19:19
+    U32 PBM_PL2_LOG                             :  1;  // Bits 20:20
+    U32 PBM_PLGT_LOG                            :  1;  // Bits 21:21
+    U32 SPARE_GT_LOG_6                          :  1;  // Bits 22:22
+    U32 SPARE_GT_LOG_7                          :  1;  // Bits 23:23
+    U32 VR_THERMALERT_LOG                       :  1;  // Bits 24:24
+    U32 SPARE_GT_LOG_9                          :  1;  // Bits 25:25
+    U32 EDP_ICC_LOG                             :  1;  // Bits 26:26
+    U32 SPARE_GT_LOG_11                         :  1;  // Bits 27:27
+    U32 SPARE_GT_LOG_12                         :  1;  // Bits 28:28
+    U32 SPARE_GT_LOG_13                         :  1;  // Bits 29:29
+    U32 SPARE_GT_LOG_14                         :  1;  // Bits 30:30
+    U32 SPARE_GT_LOG_15                         :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} PCU_CR_GT_PERF_LIMIT_REASONS_PCU_STRUCT;
+
+typedef union {
+  struct {
+    U32 PROCHOT_STATUS                          :  1;  // Bits 0:0
+    U32 THERMAL_STATUS                          :  1;  // Bits 1:1
+    U32 SPARE_CLR_2                             :  1;  // Bits 2:2
+    U32 PBM_PL1_STATUS                          :  1;  // Bits 3:3
+    U32 PBM_PL2_STATUS                          :  1;  // Bits 4:4
+    U32 SPARE_CLR_5                             :  1;  // Bits 5:5
+    U32 SPARE_CLR_6                             :  1;  // Bits 6:6
+    U32 SPARE_CLR_7                             :  1;  // Bits 7:7
+    U32 VR_THERMALERT_STATUS                    :  1;  // Bits 8:8
+    U32 SPARE_CLR_9                             :  1;  // Bits 9:9
+    U32 EDP_ICC_STATUS                          :  1;  // Bits 10:10
+    U32 SPARE_CLR_11                            :  1;  // Bits 11:11
+    U32 SPARE_CLR_12                            :  1;  // Bits 12:12
+    U32 SPARE_CLR_13                            :  1;  // Bits 13:13
+    U32 SPARE_CLR_14                            :  1;  // Bits 14:14
+    U32 SPARE_CLR_15                            :  1;  // Bits 15:15
+    U32 PROCHOT_LOG                             :  1;  // Bits 16:16
+    U32 THERMAL_LOG                             :  1;  // Bits 17:17
+    U32 SPARE_CLR_LOG_2                         :  1;  // Bits 18:18
+    U32 PBM_PL1_LOG                             :  1;  // Bits 19:19
+    U32 PBM_PL2_LOG                             :  1;  // Bits 20:20
+    U32 SPARE_CLR_LOG_5                         :  1;  // Bits 21:21
+    U32 SPARE_CLR_LOG_6                         :  1;  // Bits 22:22
+    U32 SPARE_CLR_LOG_7                         :  1;  // Bits 23:23
+    U32 VR_THERMALERT_LOG                       :  1;  // Bits 24:24
+    U32 SPARE_CLR_LOG_9                         :  1;  // Bits 25:25
+    U32 EDP_ICC_LOG                             :  1;  // Bits 26:26
+    U32 SPARE_CLR_LOG_11                        :  1;  // Bits 27:27
+    U32 SPARE_CLR_LOG_12                        :  1;  // Bits 28:28
+    U32 SPARE_CLR_LOG_13                        :  1;  // Bits 29:29
+    U32 SPARE_CLR_LOG_14                        :  1;  // Bits 30:30
+    U32 SPARE_CLR_LOG_15                        :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_STRUCT;
+
+typedef union {
+  struct {
+    U32 PRIPTP                                  :  5;  // Bits 4:0
+    U32                                         :  27;  // Bits 31:5
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} PCU_CR_PRIP_TURBO_PLCY_PCU_STRUCT;
+
+typedef union {
+  struct {
+    U32 SECPTP                                  :  5;  // Bits 4:0
+    U32                                         :  27;  // Bits 31:5
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} PCU_CR_SECP_TURBO_PLCY_PCU_STRUCT;
+
+typedef union {
+  struct {
+    U32 DATA                                    :  32;  // Bits 31:0
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} PCU_CR_PRIP_NRG_STTS_PCU_STRUCT;
+
+typedef union {
+  struct {
+    U32 DATA                                    :  32;  // Bits 31:0
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} PCU_CR_SECP_NRG_STTS_PCU_STRUCT;
+
+typedef union {
+  struct {
+    U32 PKG_TDP                                 :  15;  // Bits 14:0
+    U32                                         :  1;  // Bits 15:15
+    U32 PKG_MIN_PWR                             :  15;  // Bits 30:16
+    U32                                         :  1;  // Bits 31:31
+    U32 PKG_MAX_PWR                             :  15;  // Bits 46:32
+    U32                                         :  1;  // Bits 47:47
+    U32 PKG_MAX_WIN                             :  7;  // Bits 54:48
+    U32                                         :  9;  // Bits 63:55
+  } Bits;
+  U64 Data;
+  U32 Data32[2];
+  U16 Data16[4];
+  U8  Data8[8];
+} PCU_CR_PACKAGE_POWER_SKU_PCU_STRUCT;
+
+typedef union {
+  struct {
+    U32 PWR_UNIT                                :  4;  // Bits 3:0
+    U32                                         :  4;  // Bits 7:4
+    U32 ENERGY_UNIT                             :  5;  // Bits 12:8
+    U32                                         :  3;  // Bits 15:13
+    U32 TIME_UNIT                               :  4;  // Bits 19:16
+    U32                                         :  12;  // Bits 31:20
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} PCU_CR_PACKAGE_POWER_SKU_UNIT_PCU_STRUCT;
+
+typedef union {
+  struct {
+    U32 DATA                                    :  32;  // Bits 31:0
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} PCU_CR_PACKAGE_ENERGY_STATUS_PCU_STRUCT;
+
+typedef union {
+  struct {
+    U32 DATA                                    :  32;  // Bits 31:0
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} PCU_CR_GT_IO_BUSYNESS_PCU_STRUCT;
+
+typedef union {
+  struct {
+    U32 DATA                                    :  32;  // Bits 31:0
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} PCU_CR_GT_VIDEO_BUSYNESS_PCU_STRUCT;
+
+typedef union {
+  struct {
+    U32 RP_STATE_VOLTAGE                        :  8;  // Bits 7:0
+    U32 RP_STATE_RATIO                          :  8;  // Bits 15:8
+    U32                                         :  16;  // Bits 31:16
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} PCU_CR_GT_PERF_STATUS_PCU_STRUCT;
+
+typedef union {
+  struct {
+    U64                                         :  50;  // Bits 49:0
+    U32 PLATFORMID                              :  3;  // Bits 52:50
+    U32                                         :  11;  // Bits 63:53
+  } Bits;
+  U64 Data;
+  U32 Data32[2];
+  U16 Data16[4];
+  U8  Data8[8];
+} PCU_CR_PLATFORM_ID_PCU_STRUCT;
+
+typedef union {
+  struct {
+    U32                                         :  8;  // Bits 7:0
+    U32 MAX_NON_TURBO_LIM_RATIO                 :  8;  // Bits 15:8
+    U32 SMM_SAVE_CAP                            :  1;  // Bits 16:16
+    U32                                         :  7;  // Bits 23:17
+    U32 OCVOLT_OVRD_AVAIL                       :  1;  // Bits 24:24
+    U32 FIVR_RFI_TUNING_AVAIL                   :  1;  // Bits 25:25
+    U32 DCU_16K_MODE_AVAIL                      :  1;  // Bits 26:26
+    U32 SAMPLE_PART                             :  1;  // Bits 27:27
+    U32 PRG_TURBO_RATIO_EN                      :  1;  // Bits 28:28
+    U32 PRG_TDP_LIM_EN                          :  1;  // Bits 29:29
+    U32 PRG_TJ_OFFSET_EN                        :  1;  // Bits 30:30
+    U32 CPUID_FAULTING_EN                       :  1;  // Bits 31:31
+    U32 LPM_SUPPORT                             :  1;  // Bits 32:32
+    U32 CONFIG_TDP_LEVELS                       :  2;  // Bits 34:33
+    U32 PFAT_ENABLE                             :  1;  // Bits 35:35
+    U32                                         :  1;  // Bits 36:36
+    U32 TIMED_MWAIT_ENABLE                      :  1;  // Bits 37:37
+    U32                                         :  2;  // Bits 39:38
+    U32 MAX_EFFICIENCY_RATIO                    :  8;  // Bits 47:40
+    U32 MIN_OPERATING_RATIO                     :  8;  // Bits 55:48
+    U32                                         :  8;  // Bits 63:56
+  } Bits;
+  U64 Data;
+  U32 Data32[2];
+  U16 Data16[4];
+  U8  Data8[8];
+} PCU_CR_PLATFORM_INFO_PCU_STRUCT;
+
+typedef union {
+  struct {
+    U32 DATA                                    :  32;  // Bits 31:0
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} PCU_CR_PP1_C0_CORE_CLOCK_PCU_STRUCT;
+
+typedef union {
+  struct {
+    U32 DATA                                    :  32;  // Bits 31:0
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} PCU_CR_PP0_ANY_THREAD_ACTIVITY_PCU_STRUCT;
+
+typedef union {
+  struct {
+    U32 DATA                                    :  32;  // Bits 31:0
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} PCU_CR_PP0_EFFICIENT_CYCLES_PCU_STRUCT;
+
+typedef union {
+  struct {
+    U32 DATA                                    :  32;  // Bits 31:0
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} PCU_CR_PP0_THREAD_ACTIVITY_PCU_STRUCT;
+
+typedef union {
+  struct {
+    U32 DATA                                    :  32;  // Bits 31:0
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} PCU_CR_PP1_ANY_THREAD_ACTIVITY_PCU_STRUCT;
+
+typedef union {
+  struct {
+    U32 DATA                                    :  32;  // Bits 31:0
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} PCU_CR_PP1_EFFICIENT_CYCLES_PCU_STRUCT;
+
+typedef union {
+  struct {
+    U32 DATA                                    :  8;  // Bits 7:0
+    U32                                         :  24;  // Bits 31:8
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} PCU_CR_PACKAGE_TEMPERATURE_PCU_STRUCT;
+
+typedef union {
+  struct {
+    U32 DATA                                    :  8;  // Bits 7:0
+    U32                                         :  24;  // Bits 31:8
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} PCU_CR_PP0_TEMPERATURE_PCU_STRUCT;
+
+typedef union {
+  struct {
+    U32 DATA                                    :  8;  // Bits 7:0
+    U32                                         :  24;  // Bits 31:8
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} PCU_CR_PP1_TEMPERATURE_PCU_STRUCT;
+
+typedef union {
+  struct {
+    U32 TIME_VAL                                :  32;  // Bits 31:0
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} PCU_CR_PCU_REFERENCE_CLOCK_PCU_STRUCT;
+
+typedef union {
+  struct {
+    U32 RESERVED                                :  1;  // Bits 0:0
+    U32 VALID                                   :  1;  // Bits 1:1
+    U32 RESERVED_BITS                           :  4;  // Bits 5:2
+    U32 OD                                      :  1;  // Bits 6:6
+    U32 IM                                      :  1;  // Bits 7:7
+    U32 NEXT_DEVICE_ACTIVITY                    :  21;  // Bits 28:8
+    U32                                         :  3;  // Bits 31:29
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} PCU_CR_DEVICE_SHARED_IDLE_DURATION_PCU_STRUCT;
+
+typedef union {
+  struct {
+    U32 USED                                    :  1;  // Bits 0:0
+    U32 VALID                                   :  1;  // Bits 1:1
+    U32 RESERVED_BITS                           :  4;  // Bits 5:2
+    U32 OD                                      :  1;  // Bits 6:6
+    U32 IM                                      :  1;  // Bits 7:7
+    U32 NEXT_DEVICE_ACTIVITY                    :  21;  // Bits 28:8
+    U32                                         :  3;  // Bits 31:29
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} PCU_CR_DEVICE_DEDICATED_IDLE_DURATION_PCU_STRUCT;
+
+typedef union {
+  struct {
+    U32 PSTT_LIM                                :  8;  // Bits 7:0
+    U32 PSTT_MIN                                :  8;  // Bits 15:8
+    U32                                         :  15;  // Bits 30:16
+    U32 LOCK                                    :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} PCU_CR_P_STATE_LIMITS_PCU_STRUCT;
+
+typedef union {
+  struct {
+    U32 RPSTT_LIM                               :  8;  // Bits 7:0
+    U32                                         :  24;  // Bits 31:8
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} PCU_CR_RP_STATE_LIMITS_PCU_STRUCT;
+
+typedef union {
+  struct {
+    U32 RP0_CAP                                 :  8;  // Bits 7:0
+    U32 RP1_CAP                                 :  8;  // Bits 15:8
+    U32 RPN_CAP                                 :  8;  // Bits 23:16
+    U32                                         :  8;  // Bits 31:24
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} PCU_CR_RP_STATE_CAP_PCU_STRUCT;
+
+typedef union {
+  struct {
+    U32                                         :  8;  // Bits 7:0
+    U32 FAN_TEMP_TARGET_OFST                    :  8;  // Bits 15:8
+    U32 REF_TEMP                                :  8;  // Bits 23:16
+    U32 TJ_MAX_TCC_OFFSET                       :  4;  // Bits 27:24
+    U32                                         :  4;  // Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} PCU_CR_TEMPERATURE_TARGET_PCU_STRUCT;
+
+typedef union {
+  struct {
+    U32 PKG_PWR_LIM_1                           :  15;  // Bits 14:0
+    U32 PKG_PWR_LIM_1_EN                        :  1;  // Bits 15:15
+    U32 PKG_CLMP_LIM_1                          :  1;  // Bits 16:16
+    U32 PKG_PWR_LIM_1_TIME                      :  7;  // Bits 23:17
+    U32                                         :  8;  // Bits 31:24
+    U32 PKG_PWR_LIM_2                           :  15;  // Bits 46:32
+    U32 PKG_PWR_LIM_2_EN                        :  1;  // Bits 47:47
+    U32 PKG_CLMP_LIM_2                          :  1;  // Bits 48:48
+    U32 PKG_PWR_LIM_2_TIME                      :  7;  // Bits 55:49
+    U32                                         :  7;  // Bits 62:56
+    U32 PKG_PWR_LIM_LOCK                        :  1;  // Bits 63:63
+  } Bits;
+  U64 Data;
+  U32 Data32[2];
+  U16 Data16[4];
+  U8  Data8[8];
+} PCU_CR_PACKAGE_RAPL_LIMIT_PCU_STRUCT;
+
+typedef union {
+  struct {
+    U32 IA_PP_PWR_LIM                           :  15;  // Bits 14:0
+    U32 PWR_LIM_CTRL_EN                         :  1;  // Bits 15:15
+    U32 PP_CLAMP_LIM                            :  1;  // Bits 16:16
+    U32 CTRL_TIME_WIN                           :  7;  // Bits 23:17
+    U32                                         :  7;  // Bits 30:24
+    U32 PP_PWR_LIM_LOCK                         :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} PCU_CR_PRIP_TURBO_PWR_LIM_PCU_STRUCT;
+
+typedef union {
+  struct {
+    U32 NON_IA_PP_PWR_LIM                       :  15;  // Bits 14:0
+    U32 PWR_LIM_CTRL_EN                         :  1;  // Bits 15:15
+    U32 PP_CLAMP_LIM                            :  1;  // Bits 16:16
+    U32 CTRL_TIME_WIN                           :  7;  // Bits 23:17
+    U32                                         :  7;  // Bits 30:24
+    U32 SP_PWR_LIM_LOCK                         :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} PCU_CR_SECP_TURBO_PWR_LIM_PCU_STRUCT;
+
+typedef union {
+  struct {
+    U32 CURRENT_LIMIT                           :  13;  // Bits 12:0
+    U32                                         :  18;  // Bits 30:13
+    U32 LOCK                                    :  1;  // Bits 31:31
+    U32 PSI1_THRESHOLD                          :  10;  // Bits 41:32
+    U32 PSI2_THRESHOLD                          :  10;  // Bits 51:42
+    U32 PSI3_THRESHOLD                          :  10;  // Bits 61:52
+    U32 RESERVED                                :  2;  // Bits 63:62
+  } Bits;
+  U64 Data;
+  U32 Data32[2];
+  U16 Data16[4];
+  U8  Data8[8];
+} PCU_CR_VR_CURRENT_CONFIG_PCU_STRUCT;
+
+typedef union {
+  struct {
+    U32 MRC_Saving_Rd                           :  8;  // Bits 7:0
+    U32 MRC_Saving_Wt                           :  8;  // Bits 15:8
+    U32 MRC_Saving_Cmd                          :  8;  // Bits 23:16
+    U32 RESERVED                                :  8;  // Bits 31:24
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} PCU_CR_MRC_ODT_POWER_SAVING_PCU_STRUCT;
+
+typedef union {
+  struct {
+    U32 THERMAL_MONITOR_STATUS                  :  1;  // Bits 0:0
+    U32 THERMAL_MONITOR_LOG                     :  1;  // Bits 1:1
+    U32 PROCHOT_STATUS                          :  1;  // Bits 2:2
+    U32 PROCHOT_LOG                             :  1;  // Bits 3:3
+    U32 OUT_OF_SPEC_STATUS                      :  1;  // Bits 4:4
+    U32 OUT_OF_SPEC_LOG                         :  1;  // Bits 5:5
+    U32 THRESHOLD1_STATUS                       :  1;  // Bits 6:6
+    U32 THRESHOLD1_LOG                          :  1;  // Bits 7:7
+    U32 THRESHOLD2_STATUS                       :  1;  // Bits 8:8
+    U32 THRESHOLD2_LOG                          :  1;  // Bits 9:9
+    U32 POWER_LIMITATION_STATUS                 :  1;  // Bits 10:10
+    U32 POWER_LIMITATION_LOG                    :  1;  // Bits 11:11
+    U32                                         :  4;  // Bits 15:12
+    U32 TEMPERATURE                             :  7;  // Bits 22:16
+    U32                                         :  4;  // Bits 26:23
+    U32 RESOLUTION                              :  4;  // Bits 30:27
+    U32 VALID                                   :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} PCU_CR_THERM_STATUS_GT_PCU_STRUCT;
+
+typedef union {
+  struct {
+    U32 HIGH_TEMP_INT_ENABLE                    :  1;  // Bits 0:0
+    U32 LOW_TEMP_INT_ENABLE                     :  1;  // Bits 1:1
+    U32 PROCHOT_INT_ENABLE                      :  1;  // Bits 2:2
+    U32                                         :  1;  // Bits 3:3
+    U32 OUT_OF_SPEC_INT_ENABLE                  :  1;  // Bits 4:4
+    U32                                         :  3;  // Bits 7:5
+    U32 THRESHOLD_1_REL_TEMP                    :  7;  // Bits 14:8
+    U32 THRESHOLD_1_INT_ENABLE                  :  1;  // Bits 15:15
+    U32 THRESHOLD_2_REL_TEMP                    :  7;  // Bits 22:16
+    U32 THRESHOLD_2_INT_ENABLE                  :  1;  // Bits 23:23
+    U32 POWER_INT_ENABLE                        :  1;  // Bits 24:24
+    U32                                         :  7;  // Bits 31:25
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} PCU_CR_THERM_INTERRUPT_GT_PCU_STRUCT;
+
+typedef union {
+  struct {
+    U32 RESERVED                                :  1;  // Bits 0:0
+    U32 VALID                                   :  1;  // Bits 1:1
+    U32 RESERVED_BITS                           :  4;  // Bits 5:2
+    U32 OD                                      :  1;  // Bits 6:6
+    U32 IM                                      :  1;  // Bits 7:7
+    U32 NEXT_DEVICE_ACTIVITY                    :  21;  // Bits 28:8
+    U32 DISABLE_MDID_EVALUATION                 :  1;  // Bits 29:29
+    U32 FORCE_MDID_OVERRIDE                     :  1;  // Bits 30:30
+    U32                                         :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} PCU_CR_DEVICE_IDLE_DURATION_OVERRIDE_PCU_STRUCT;
+
+typedef union {
+  struct {
+    U32 VALUE                                   :  10;  // Bits 9:0
+    U32 MULTIPLIER                              :  3;  // Bits 12:10
+    U32                                         :  2;  // Bits 14:13
+    U32 VALID                                   :  1;  // Bits 15:15
+    U32                                         :  16;  // Bits 31:16
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} PCU_CR_GRAPHICS_INTERRUPT_RESPONSE_TIME_PCU_STRUCT;
+
+typedef union {
+  struct {
+    U32                                         :  4;  // Bits 3:0
+    U32 PECI_CMD                                :  8;  // Bits 11:4
+    U32                                         :  20;  // Bits 31:12
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} PCU_CR_CHAP_CONFIG_PCU_STRUCT;
+
+typedef union {
+  struct {
+    U32 FREQ_TH1                                :  6;  // Bits 5:0
+    U32                                         :  2;  // Bits 7:6
+    U32 FREQ_TH2                                :  6;  // Bits 13:8
+    U32                                         :  2;  // Bits 15:14
+    U32 FREQ_TH3                                :  6;  // Bits 21:16
+    U32                                         :  10;  // Bits 31:22
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} PCU_CR_CHAP_THRESHOLD2_PCU_STRUCT;
+
+typedef union {
+  struct {
+    U32 DEBUG_ENERGY_PP0_VALUE                  :  10;  // Bits 9:0
+    U32 DEBUG_ENERGY_PP1_VALUE                  :  10;  // Bits 19:10
+    U32 DEBUG_ENERGY_SA_VALUE                   :  10;  // Bits 29:20
+    U32                                         :  2;  // Bits 31:30
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} PCU_CR_ENERGY_DEBUG_PCU_STRUCT;
+
+typedef union {
+  struct {
+    U64 SKPD                                    :  64;  // Bits 63:0
+  } Bits;
+  U64 Data;
+  U32 Data32[2];
+  U16 Data16[4];
+  U8  Data8[8];
+} PCU_CR_SSKPD_PCU_STRUCT;
+
+typedef union {
+  struct {
+    U32 PPDN_INIT                               :  12;  // Bits 11:0
+    U32                                         :  20;  // Bits 31:12
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} PCU_CR_C2C3TT_PCU_STRUCT;
+
+typedef union {
+  struct {
+    U32 DDR_TIMER_VALUE                         :  13;  // Bits 12:0
+    U32                                         :  19;  // Bits 31:13
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} PCU_CR_C2_DDR_TT_PCU_STRUCT;
+
+typedef union {
+  struct {
+    U32 NSTL                                    :  10;  // Bits 9:0
+    U32 MULTIPLIER                              :  3;  // Bits 12:10
+    U32                                         :  1;  // Bits 13:13
+    U32 FORCE_NL                                :  1;  // Bits 14:14
+    U32 NL_V                                    :  1;  // Bits 15:15
+    U32 SXL                                     :  10;  // Bits 25:16
+    U32 SXLM                                    :  3;  // Bits 28:26
+    U32                                         :  1;  // Bits 29:29
+    U32 FORCE_SXL                               :  1;  // Bits 30:30
+    U32 SXL_V                                   :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} PCU_CR_PCIE_ILTR_OVRD_PCU_STRUCT;
+
+typedef union {
+  struct {
+    U32 NL_VALUE                                :  10;  // Bits 9:0
+    U32 NL_SCALE                                :  3;  // Bits 12:10
+    U32 NL_RESERVED                             :  2;  // Bits 14:13
+    U32 NL_VALID                                :  1;  // Bits 15:15
+    U32 SXL_VALUE                               :  10;  // Bits 25:16
+    U32 SXL_SCALE                               :  3;  // Bits 28:26
+    U32 SXL_RESERVED                            :  2;  // Bits 30:29
+    U32 SXL_VALID                               :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} PCU_CR_PCIE_ILTR_VAL_PCU_0_STRUCT;
+
+typedef union {
+  struct {
+    U32 NL_VALUE                                :  10;  // Bits 9:0
+    U32 NL_SCALE                                :  3;  // Bits 12:10
+    U32 NL_RESERVED                             :  2;  // Bits 14:13
+    U32 NL_VALID                                :  1;  // Bits 15:15
+    U32 SXL_VALUE                               :  10;  // Bits 25:16
+    U32 SXL_SCALE                               :  3;  // Bits 28:26
+    U32 SXL_RESERVED                            :  2;  // Bits 30:29
+    U32 SXL_VALID                               :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} PCU_CR_PCIE_ILTR_VAL_PCU_1_STRUCT;
+
+typedef union {
+  struct {
+    U32 NL_VALUE                                :  10;  // Bits 9:0
+    U32 NL_SCALE                                :  3;  // Bits 12:10
+    U32 NL_RESERVED                             :  2;  // Bits 14:13
+    U32 NL_VALID                                :  1;  // Bits 15:15
+    U32 SXL_VALUE                               :  10;  // Bits 25:16
+    U32 SXL_SCALE                               :  3;  // Bits 28:26
+    U32 SXL_RESERVED                            :  2;  // Bits 30:29
+    U32 SXL_VALID                               :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} PCU_CR_PCIE_ILTR_VAL_PCU_2_STRUCT;
+
+typedef union {
+  struct {
+    U32 DATA                                    :  18;  // Bits 17:0
+    U32                                         :  13;  // Bits 30:18
+    U32 VORANGE                                 :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} PCU_CR_VISA_CTL_PTPCFSMS_PCU_STRUCT;
+
+typedef union {
+  struct {
+    U32 DATA                                    :  32;  // Bits 31:0
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} PCU_CR_VISA_XBAR_PTPCFSMS_PCU_STRUCT;
+
+typedef union {
+  struct {
+    U32 DATA                                    :  18;  // Bits 17:0
+    U32                                         :  13;  // Bits 30:18
+    U32 VORANGE                                 :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} PCU_CR_VISA_CTL_PTPCIOREGS_PCU_STRUCT;
+
+typedef union {
+  struct {
+    U32 DATA                                    :  32;  // Bits 31:0
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} PCU_CR_BIOS_MAILBOX_DATA_PCU_STRUCT;
+
+typedef union {
+  struct {
+    U32 COMMAND                                 :  8;  // Bits 7:0
+    U32 ADDR                                    :  21;  // Bits 28:8
+    U32                                         :  2;  // Bits 30:29
+    U32 RUN_BUSY                                :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} PCU_CR_BIOS_MAILBOX_INTERFACE_PCU_STRUCT;
+
+typedef union {
+  struct {
+    U32 RST_CPL                                 :  1;  // Bits 0:0
+    U32 PCIE_ENUMERATION_DONE                   :  1;  // Bits 1:1
+    U32 C7_ALLOWED                              :  1;  // Bits 2:2
+    U32                                         :  29;  // Bits 31:3
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} PCU_CR_BIOS_RESET_CPL_PCU_STRUCT;
+
+typedef union {
+  struct {
+    U32 REQ_DATA                                :  4;  // Bits 3:0
+    U32 REQ_TYPE                                :  4;  // Bits 7:4
+    U32                                         :  23;  // Bits 30:8
+    U32 RUN_BUSY                                :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} PCU_CR_MC_BIOS_REQ_PCU_STRUCT;
+
+typedef union {
+  struct {
+    U32 MC_FREQ                                 :  4;  // Bits 3:0
+    U32                                         :  28;  // Bits 31:4
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} PCU_CR_MC_BIOS_DATA_PCU_STRUCT;
+
+typedef union {
+  struct {
+    U32 SACG_ENA                                :  1;  // Bits 0:0
+    U32 MPLL_OFF_ENA                            :  1;  // Bits 1:1
+    U32 PPLL_OFF_ENA                            :  1;  // Bits 2:2
+    U32                                         :  5;  // Bits 7:3
+    U32 SACG_SEN                                :  1;  // Bits 8:8
+    U32 MPLL_OFF_SEN                            :  1;  // Bits 9:9
+    U32 MDLL_OFF_SEN                            :  1;  // Bits 10:10
+    U32 SACG_SREXIT                             :  1;  // Bits 11:11
+    U32 NSWAKE_SREXIT                           :  1;  // Bits 12:12
+    U32 SACG_MPLL                               :  1;  // Bits 13:13
+    U32 MPLL_ON_DE                              :  1;  // Bits 14:14
+    U32 MDLL_ON_DE                              :  1;  // Bits 15:15
+    U32                                         :  16;  // Bits 31:16
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} PCU_CR_SAPMCTL_PCU_STRUCT;
+
+typedef union {
+  struct {
+    U32 COMP_DISABLE                            :  1;  // Bits 0:0
+    U32 COMP_INTERVAL                           :  4;  // Bits 4:1
+    U32                                         :  3;  // Bits 7:5
+    U32 COMP_FORCE                              :  1;  // Bits 8:8
+    U32                                         :  23;  // Bits 31:9
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} PCU_CR_P_COMP_PCU_STRUCT;
+
+typedef union {
+  struct {
+    U32 COMP_DISABLE                            :  1;  // Bits 0:0
+    U32 COMP_INTERVAL                           :  4;  // Bits 4:1
+    U32                                         :  3;  // Bits 7:5
+    U32 COMP_FORCE                              :  1;  // Bits 8:8
+    U32                                         :  23;  // Bits 31:9
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} PCU_CR_M_COMP_PCU_STRUCT;
+
+typedef union {
+  struct {
+    U32 COMP_DISABLE                            :  1;  // Bits 0:0
+    U32 COMP_INTERVAL                           :  4;  // Bits 4:1
+    U32                                         :  3;  // Bits 7:5
+    U32 COMP_FORCE                              :  1;  // Bits 8:8
+    U32                                         :  23;  // Bits 31:9
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} PCU_CR_D_COMP_PCU_STRUCT;
+
+typedef union {
+  struct {
+    U32 TDP_RATIO                               :  8;  // Bits 7:0
+    U32                                         :  24;  // Bits 31:8
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} PCU_CR_CONFIG_TDP_NOMINAL_PCU_STRUCT;
+
+typedef union {
+  struct {
+    U32 PKG_TDP                                 :  15;  // Bits 14:0
+    U32                                         :  1;  // Bits 15:15
+    U32 TDP_RATIO                               :  8;  // Bits 23:16
+    U32                                         :  8;  // Bits 31:24
+    U32 PKG_MAX_PWR                             :  15;  // Bits 46:32
+    U32 PKG_MIN_PWR                             :  16;  // Bits 62:47
+    U32                                         :  1;  // Bits 63:63
+  } Bits;
+  U64 Data;
+  U32 Data32[2];
+  U16 Data16[4];
+  U8  Data8[8];
+} PCU_CR_CONFIG_TDP_LEVEL1_PCU_STRUCT;
+
+typedef union {
+  struct {
+    U32 PKG_TDP                                 :  15;  // Bits 14:0
+    U32                                         :  1;  // Bits 15:15
+    U32 TDP_RATIO                               :  8;  // Bits 23:16
+    U32                                         :  8;  // Bits 31:24
+    U32 PKG_MAX_PWR                             :  15;  // Bits 46:32
+    U32 PKG_MIN_PWR                             :  16;  // Bits 62:47
+    U32                                         :  1;  // Bits 63:63
+  } Bits;
+  U64 Data;
+  U32 Data32[2];
+  U16 Data16[4];
+  U8  Data8[8];
+} PCU_CR_CONFIG_TDP_LEVEL2_PCU_STRUCT;
+
+typedef union {
+  struct {
+    U32 TDP_LEVEL                               :  2;  // Bits 1:0
+    U32                                         :  29;  // Bits 30:2
+    U32 CONFIG_TDP_LOCK                         :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} PCU_CR_CONFIG_TDP_CONTROL_PCU_STRUCT;
+
+typedef union {
+  struct {
+    U32 MAX_NON_TURBO_RATIO                     :  8;  // Bits 7:0
+    U32                                         :  23;  // Bits 30:8
+    U32 TURBO_ACTIVATION_RATIO_LOCK             :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} PCU_CR_TURBO_ACTIVATION_RATIO_PCU_STRUCT;
+
+typedef union {
+  struct {
+    U32 DATA                                    :  18;  // Bits 17:0
+    U32                                         :  13;  // Bits 30:18
+    U32 VORANGE                                 :  1;  // Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} DRNG_CR_VISA_CTL_DRNGCTLS_DRNG_STRUCT;
+
+#define NCDECS_CR_GFXVTBAR_NCU_REG                                   (0x00005400)
+  #define NCDECS_CR_GFXVTBAR_NCU_GFXVTBAREN_OFF                        ( 0)
+  #define NCDECS_CR_GFXVTBAR_NCU_GFXVTBAREN_WID                        ( 1)
+  #define NCDECS_CR_GFXVTBAR_NCU_GFXVTBAREN_MSK                        (0x00000001)
+  #define NCDECS_CR_GFXVTBAR_NCU_GFXVTBAREN_MAX                        (0x00000001)
+  #define NCDECS_CR_GFXVTBAR_NCU_GFXVTBAREN_DEF                        (0x00000000)
+  #define NCDECS_CR_GFXVTBAR_NCU_GFXVTBAR_OFF                          (12)
+  #define NCDECS_CR_GFXVTBAR_NCU_GFXVTBAR_WID                          (27)
+  #define NCDECS_CR_GFXVTBAR_NCU_GFXVTBAR_MSK                          (0x7FFFFFF000)
+  #define NCDECS_CR_GFXVTBAR_NCU_GFXVTBAR_MAX                          (0x07FFFFFF)
+  #define NCDECS_CR_GFXVTBAR_NCU_GFXVTBAR_DEF                          (0x00000000)
+
+#define NCDECS_CR_EDRAMBAR_NCU_REG                                   (0x00005408)
+  #define NCDECS_CR_EDRAMBAR_NCU_EDRAMBAREN_OFF                        ( 0)
+  #define NCDECS_CR_EDRAMBAR_NCU_EDRAMBAREN_WID                        ( 1)
+  #define NCDECS_CR_EDRAMBAR_NCU_EDRAMBAREN_MSK                        (0x00000001)
+  #define NCDECS_CR_EDRAMBAR_NCU_EDRAMBAREN_MAX                        (0x00000001)
+  #define NCDECS_CR_EDRAMBAR_NCU_EDRAMBAREN_DEF                        (0x00000000)
+  #define NCDECS_CR_EDRAMBAR_NCU_EDRAMBAR_OFF                          (14)
+  #define NCDECS_CR_EDRAMBAR_NCU_EDRAMBAR_WID                          (25)
+  #define NCDECS_CR_EDRAMBAR_NCU_EDRAMBAR_MSK                          (0x7FFFFFC000)
+  #define NCDECS_CR_EDRAMBAR_NCU_EDRAMBAR_MAX                          (0x01FFFFFF)
+  #define NCDECS_CR_EDRAMBAR_NCU_EDRAMBAR_DEF                          (0x00000000)
+
+#define NCDECS_CR_VTDPVC0BAR_NCU_REG                                 (0x00005410)
+  #define NCDECS_CR_VTDPVC0BAR_NCU_VTVC0BAREN_OFF                      ( 0)
+  #define NCDECS_CR_VTDPVC0BAR_NCU_VTVC0BAREN_WID                      ( 1)
+  #define NCDECS_CR_VTDPVC0BAR_NCU_VTVC0BAREN_MSK                      (0x00000001)
+  #define NCDECS_CR_VTDPVC0BAR_NCU_VTVC0BAREN_MAX                      (0x00000001)
+  #define NCDECS_CR_VTDPVC0BAR_NCU_VTVC0BAREN_DEF                      (0x00000000)
+  #define NCDECS_CR_VTDPVC0BAR_NCU_VTVC0BAR_OFF                        (12)
+  #define NCDECS_CR_VTDPVC0BAR_NCU_VTVC0BAR_WID                        (27)
+  #define NCDECS_CR_VTDPVC0BAR_NCU_VTVC0BAR_MSK                        (0x7FFFFFF000)
+  #define NCDECS_CR_VTDPVC0BAR_NCU_VTVC0BAR_MAX                        (0x07FFFFFF)
+  #define NCDECS_CR_VTDPVC0BAR_NCU_VTVC0BAR_DEF                        (0x00000000)
+
+#define NCDECS_CR_INTRDIRCTL_NCU_REG                                 (0x00005418)
+  #define NCDECS_CR_INTRDIRCTL_NCU_RdrModSel_OFF                       ( 0)
+  #define NCDECS_CR_INTRDIRCTL_NCU_RdrModSel_WID                       ( 3)
+  #define NCDECS_CR_INTRDIRCTL_NCU_RdrModSel_MSK                       (0x00000007)
+  #define NCDECS_CR_INTRDIRCTL_NCU_RdrModSel_MAX                       (0x00000007)
+  #define NCDECS_CR_INTRDIRCTL_NCU_RdrModSel_DEF                       (0x00000000)
+  #define NCDECS_CR_INTRDIRCTL_NCU_ClastChkSmpMod_OFF                  ( 3)
+  #define NCDECS_CR_INTRDIRCTL_NCU_ClastChkSmpMod_WID                  ( 1)
+  #define NCDECS_CR_INTRDIRCTL_NCU_ClastChkSmpMod_MSK                  (0x00000008)
+  #define NCDECS_CR_INTRDIRCTL_NCU_ClastChkSmpMod_MAX                  (0x00000001)
+  #define NCDECS_CR_INTRDIRCTL_NCU_ClastChkSmpMod_DEF                  (0x00000000)
+  #define NCDECS_CR_INTRDIRCTL_NCU_LogFltClustMod_OFF                  ( 4)
+  #define NCDECS_CR_INTRDIRCTL_NCU_LogFltClustMod_WID                  ( 1)
+  #define NCDECS_CR_INTRDIRCTL_NCU_LogFltClustMod_MSK                  (0x00000010)
+  #define NCDECS_CR_INTRDIRCTL_NCU_LogFltClustMod_MAX                  (0x00000001)
+  #define NCDECS_CR_INTRDIRCTL_NCU_LogFltClustMod_DEF                  (0x00000000)
+  #define NCDECS_CR_INTRDIRCTL_NCU_LogFlatClustOvrEn_OFF               ( 5)
+  #define NCDECS_CR_INTRDIRCTL_NCU_LogFlatClustOvrEn_WID               ( 1)
+  #define NCDECS_CR_INTRDIRCTL_NCU_LogFlatClustOvrEn_MSK               (0x00000020)
+  #define NCDECS_CR_INTRDIRCTL_NCU_LogFlatClustOvrEn_MAX               (0x00000001)
+  #define NCDECS_CR_INTRDIRCTL_NCU_LogFlatClustOvrEn_DEF               (0x00000000)
+  #define NCDECS_CR_INTRDIRCTL_NCU_HashModCtr_OFF                      ( 6)
+  #define NCDECS_CR_INTRDIRCTL_NCU_HashModCtr_WID                      ( 3)
+  #define NCDECS_CR_INTRDIRCTL_NCU_HashModCtr_MSK                      (0x000001C0)
+  #define NCDECS_CR_INTRDIRCTL_NCU_HashModCtr_MAX                      (0x00000007)
+  #define NCDECS_CR_INTRDIRCTL_NCU_HashModCtr_DEF                      (0x00000000)
+
+#define NCDECS_CR_NCUCTL0_NCU_REG                                    (0x0000541C)
+  #define NCDECS_CR_NCUCTL0_NCU_PLIM_OFF                               (28)
+  #define NCDECS_CR_NCUCTL0_NCU_PLIM_WID                               ( 3)
+  #define NCDECS_CR_NCUCTL0_NCU_PLIM_MSK                               (0x70000000)
+  #define NCDECS_CR_NCUCTL0_NCU_PLIM_MAX                               (0x00000007)
+  #define NCDECS_CR_NCUCTL0_NCU_PLIM_DEF                               (0x00000003)
+
+#define NCDECS_CR_GDXCBAR_NCU_REG                                    (0x00005420)
+  #define NCDECS_CR_GDXCBAR_NCU_GDXCBAREN_OFF                          ( 0)
+  #define NCDECS_CR_GDXCBAR_NCU_GDXCBAREN_WID                          ( 1)
+  #define NCDECS_CR_GDXCBAR_NCU_GDXCBAREN_MSK                          (0x00000001)
+  #define NCDECS_CR_GDXCBAR_NCU_GDXCBAREN_MAX                          (0x00000001)
+  #define NCDECS_CR_GDXCBAR_NCU_GDXCBAREN_DEF                          (0x00000000)
+  #define NCDECS_CR_GDXCBAR_NCU_GDXCBAR_OFF                            (12)
+  #define NCDECS_CR_GDXCBAR_NCU_GDXCBAR_WID                            (27)
+  #define NCDECS_CR_GDXCBAR_NCU_GDXCBAR_MSK                            (0x7FFFFFF000)
+  #define NCDECS_CR_GDXCBAR_NCU_GDXCBAR_MAX                            (0x07FFFFFF)
+  #define NCDECS_CR_GDXCBAR_NCU_GDXCBAR_DEF                            (0x00000000)
+
+#define NCDECS_CR_SCRATCHPAD_NCU_0_REG                               (0x00005428)
+  #define NCDECS_CR_SCRATCHPAD_NCU_0_Data_OFF                          ( 0)
+  #define NCDECS_CR_SCRATCHPAD_NCU_0_Data_WID                          (32)
+  #define NCDECS_CR_SCRATCHPAD_NCU_0_Data_MSK                          (0xFFFFFFFF)
+  #define NCDECS_CR_SCRATCHPAD_NCU_0_Data_MAX                          (0xFFFFFFFF)
+  #define NCDECS_CR_SCRATCHPAD_NCU_0_Data_DEF                          (0x00000000)
+
+#define NCDECS_CR_SCRATCHPAD_NCU_1_REG                               (0x0000542C)
+  #define NCDECS_CR_SCRATCHPAD_NCU_1_Data_OFF                          ( 0)
+  #define NCDECS_CR_SCRATCHPAD_NCU_1_Data_WID                          (32)
+  #define NCDECS_CR_SCRATCHPAD_NCU_1_Data_MSK                          (0xFFFFFFFF)
+  #define NCDECS_CR_SCRATCHPAD_NCU_1_Data_MAX                          (0xFFFFFFFF)
+  #define NCDECS_CR_SCRATCHPAD_NCU_1_Data_DEF                          (0x00000000)
+
+#define NCDECS_CR_SCRATCHPAD_NCU_2_REG                               (0x00005430)
+  #define NCDECS_CR_SCRATCHPAD_NCU_2_Data_OFF                          ( 0)
+  #define NCDECS_CR_SCRATCHPAD_NCU_2_Data_WID                          (32)
+  #define NCDECS_CR_SCRATCHPAD_NCU_2_Data_MSK                          (0xFFFFFFFF)
+  #define NCDECS_CR_SCRATCHPAD_NCU_2_Data_MAX                          (0xFFFFFFFF)
+  #define NCDECS_CR_SCRATCHPAD_NCU_2_Data_DEF                          (0x00000000)
+
+#define NCDECS_CR_SCRATCHPAD_NCU_3_REG                               (0x00005434)
+  #define NCDECS_CR_SCRATCHPAD_NCU_3_Data_OFF                          ( 0)
+  #define NCDECS_CR_SCRATCHPAD_NCU_3_Data_WID                          (32)
+  #define NCDECS_CR_SCRATCHPAD_NCU_3_Data_MSK                          (0xFFFFFFFF)
+  #define NCDECS_CR_SCRATCHPAD_NCU_3_Data_MAX                          (0xFFFFFFFF)
+  #define NCDECS_CR_SCRATCHPAD_NCU_3_Data_DEF                          (0x00000000)
+
+#define NCDECS_CR_PAVPMSGOFFST_NCU_REG                               (0x00005500)
+  #define NCDECS_CR_PAVPMSGOFFST_NCU_LOCK_OFF                          ( 0)
+  #define NCDECS_CR_PAVPMSGOFFST_NCU_LOCK_WID                          ( 1)
+  #define NCDECS_CR_PAVPMSGOFFST_NCU_LOCK_MSK                          (0x00000001)
+  #define NCDECS_CR_PAVPMSGOFFST_NCU_LOCK_MAX                          (0x00000001)
+  #define NCDECS_CR_PAVPMSGOFFST_NCU_LOCK_DEF                          (0x00000000)
+  #define NCDECS_CR_PAVPMSGOFFST_NCU_OFFSET_OFF                        (20)
+  #define NCDECS_CR_PAVPMSGOFFST_NCU_OFFSET_WID                        (12)
+  #define NCDECS_CR_PAVPMSGOFFST_NCU_OFFSET_MSK                        (0xFFF00000)
+  #define NCDECS_CR_PAVPMSGOFFST_NCU_OFFSET_MAX                        (0x00000FFF)
+  #define NCDECS_CR_PAVPMSGOFFST_NCU_OFFSET_DEF                        (0x00000000)
+
+#define MPVTDTRK_CR_VTDLIM_IMPH_REG                                  (0x00006000)
+  #define MPVTDTRK_CR_VTDLIM_IMPH_VCPVTDLIM_OFF                        ( 0)
+  #define MPVTDTRK_CR_VTDLIM_IMPH_VCPVTDLIM_WID                        ( 3)
+  #define MPVTDTRK_CR_VTDLIM_IMPH_VCPVTDLIM_MSK                        (0x00000007)
+  #define MPVTDTRK_CR_VTDLIM_IMPH_VCPVTDLIM_MAX                        (0x00000007)
+  #define MPVTDTRK_CR_VTDLIM_IMPH_VCPVTDLIM_DEF                        (0x00000004)
+
+#define MPVTDTRK_CR_HDAUDRID_IMPH_REG                                (0x00006008)
+  #define MPVTDTRK_CR_HDAUDRID_IMPH_DEVNUM_OFF                         ( 3)
+  #define MPVTDTRK_CR_HDAUDRID_IMPH_DEVNUM_WID                         ( 5)
+  #define MPVTDTRK_CR_HDAUDRID_IMPH_DEVNUM_MSK                         (0x000000F8)
+  #define MPVTDTRK_CR_HDAUDRID_IMPH_DEVNUM_MAX                         (0x0000001F)
+  #define MPVTDTRK_CR_HDAUDRID_IMPH_DEVNUM_DEF                         (0x0000001B)
+  #define MPVTDTRK_CR_HDAUDRID_IMPH_BUSNUM_OFF                         ( 8)
+  #define MPVTDTRK_CR_HDAUDRID_IMPH_BUSNUM_WID                         ( 8)
+  #define MPVTDTRK_CR_HDAUDRID_IMPH_BUSNUM_MSK                         (0x0000FF00)
+  #define MPVTDTRK_CR_HDAUDRID_IMPH_BUSNUM_MAX                         (0x000000FF)
+  #define MPVTDTRK_CR_HDAUDRID_IMPH_BUSNUM_DEF                         (0x00000000)
+  #define MPVTDTRK_CR_HDAUDRID_IMPH_HDAUD_EN_OFF                       (31)
+  #define MPVTDTRK_CR_HDAUDRID_IMPH_HDAUD_EN_WID                       ( 1)
+  #define MPVTDTRK_CR_HDAUDRID_IMPH_HDAUD_EN_MSK                       (0x80000000)
+  #define MPVTDTRK_CR_HDAUDRID_IMPH_HDAUD_EN_MAX                       (0x00000001)
+  #define MPVTDTRK_CR_HDAUDRID_IMPH_HDAUD_EN_DEF                       (0x00000001)
+
+#define MPVTDTRK_CR_UMAGFXBASE_IMPH_REG                              (0x00006010)
+  #define MPVTDTRK_CR_UMAGFXBASE_IMPH_UMAB_OFF                         (20)
+  #define MPVTDTRK_CR_UMAGFXBASE_IMPH_UMAB_WID                         (19)
+  #define MPVTDTRK_CR_UMAGFXBASE_IMPH_UMAB_MSK                         (0x7FFFF00000)
+  #define MPVTDTRK_CR_UMAGFXBASE_IMPH_UMAB_MAX                         (0x0007FFFF)
+  #define MPVTDTRK_CR_UMAGFXBASE_IMPH_UMAB_DEF                         (0x0007FFFF)
+
+#define MPVTDTRK_CR_UMAGFXLIMIT_IMPH_REG                             (0x00006018)
+  #define MPVTDTRK_CR_UMAGFXLIMIT_IMPH_UMAL_OFF                        (20)
+  #define MPVTDTRK_CR_UMAGFXLIMIT_IMPH_UMAL_WID                        (19)
+  #define MPVTDTRK_CR_UMAGFXLIMIT_IMPH_UMAL_MSK                        (0x7FFFF00000)
+  #define MPVTDTRK_CR_UMAGFXLIMIT_IMPH_UMAL_MAX                        (0x0007FFFF)
+  #define MPVTDTRK_CR_UMAGFXLIMIT_IMPH_UMAL_DEF                        (0x00000000)
+
+#define MPVTDTRK_CR_UMAGFXCTL_IMPH_REG                               (0x00006020)
+  #define MPVTDTRK_CR_UMAGFXCTL_IMPH_LCK_OFF                           ( 0)
+  #define MPVTDTRK_CR_UMAGFXCTL_IMPH_LCK_WID                           ( 1)
+  #define MPVTDTRK_CR_UMAGFXCTL_IMPH_LCK_MSK                           (0x00000001)
+  #define MPVTDTRK_CR_UMAGFXCTL_IMPH_LCK_MAX                           (0x00000001)
+  #define MPVTDTRK_CR_UMAGFXCTL_IMPH_LCK_DEF                           (0x00000000)
+  #define MPVTDTRK_CR_UMAGFXCTL_IMPH_PEG10EN_OFF                       (10)
+  #define MPVTDTRK_CR_UMAGFXCTL_IMPH_PEG10EN_WID                       ( 1)
+  #define MPVTDTRK_CR_UMAGFXCTL_IMPH_PEG10EN_MSK                       (0x00000400)
+  #define MPVTDTRK_CR_UMAGFXCTL_IMPH_PEG10EN_MAX                       (0x00000001)
+  #define MPVTDTRK_CR_UMAGFXCTL_IMPH_PEG10EN_DEF                       (0x00000000)
+  #define MPVTDTRK_CR_UMAGFXCTL_IMPH_PEG11EN_OFF                       (11)
+  #define MPVTDTRK_CR_UMAGFXCTL_IMPH_PEG11EN_WID                       ( 1)
+  #define MPVTDTRK_CR_UMAGFXCTL_IMPH_PEG11EN_MSK                       (0x00000800)
+  #define MPVTDTRK_CR_UMAGFXCTL_IMPH_PEG11EN_MAX                       (0x00000001)
+  #define MPVTDTRK_CR_UMAGFXCTL_IMPH_PEG11EN_DEF                       (0x00000000)
+  #define MPVTDTRK_CR_UMAGFXCTL_IMPH_PEG12EN_OFF                       (12)
+  #define MPVTDTRK_CR_UMAGFXCTL_IMPH_PEG12EN_WID                       ( 1)
+  #define MPVTDTRK_CR_UMAGFXCTL_IMPH_PEG12EN_MSK                       (0x00001000)
+  #define MPVTDTRK_CR_UMAGFXCTL_IMPH_PEG12EN_MAX                       (0x00000001)
+  #define MPVTDTRK_CR_UMAGFXCTL_IMPH_PEG12EN_DEF                       (0x00000000)
+  #define MPVTDTRK_CR_UMAGFXCTL_IMPH_DMIEN_OFF                         (13)
+  #define MPVTDTRK_CR_UMAGFXCTL_IMPH_DMIEN_WID                         ( 1)
+  #define MPVTDTRK_CR_UMAGFXCTL_IMPH_DMIEN_MSK                         (0x00002000)
+  #define MPVTDTRK_CR_UMAGFXCTL_IMPH_DMIEN_MAX                         (0x00000001)
+  #define MPVTDTRK_CR_UMAGFXCTL_IMPH_DMIEN_DEF                         (0x00000000)
+
+#define MPVTDTRK_CR_VDMBDFBARKVM_IMPH_REG                            (0x00006030)
+  #define MPVTDTRK_CR_VDMBDFBARKVM_IMPH_FUNNUM_OFF                     ( 0)
+  #define MPVTDTRK_CR_VDMBDFBARKVM_IMPH_FUNNUM_WID                     ( 3)
+  #define MPVTDTRK_CR_VDMBDFBARKVM_IMPH_FUNNUM_MSK                     (0x00000007)
+  #define MPVTDTRK_CR_VDMBDFBARKVM_IMPH_FUNNUM_MAX                     (0x00000007)
+  #define MPVTDTRK_CR_VDMBDFBARKVM_IMPH_FUNNUM_DEF                     (0x00000000)
+  #define MPVTDTRK_CR_VDMBDFBARKVM_IMPH_DEVNUM_OFF                     ( 3)
+  #define MPVTDTRK_CR_VDMBDFBARKVM_IMPH_DEVNUM_WID                     ( 5)
+  #define MPVTDTRK_CR_VDMBDFBARKVM_IMPH_DEVNUM_MSK                     (0x000000F8)
+  #define MPVTDTRK_CR_VDMBDFBARKVM_IMPH_DEVNUM_MAX                     (0x0000001F)
+  #define MPVTDTRK_CR_VDMBDFBARKVM_IMPH_DEVNUM_DEF                     (0x00000016)
+  #define MPVTDTRK_CR_VDMBDFBARKVM_IMPH_BUSNUM_OFF                     ( 8)
+  #define MPVTDTRK_CR_VDMBDFBARKVM_IMPH_BUSNUM_WID                     ( 8)
+  #define MPVTDTRK_CR_VDMBDFBARKVM_IMPH_BUSNUM_MSK                     (0x0000FF00)
+  #define MPVTDTRK_CR_VDMBDFBARKVM_IMPH_BUSNUM_MAX                     (0x000000FF)
+  #define MPVTDTRK_CR_VDMBDFBARKVM_IMPH_BUSNUM_DEF                     (0x00000000)
+  #define MPVTDTRK_CR_VDMBDFBARKVM_IMPH_BARNUM_OFF                     (16)
+  #define MPVTDTRK_CR_VDMBDFBARKVM_IMPH_BARNUM_WID                     ( 3)
+  #define MPVTDTRK_CR_VDMBDFBARKVM_IMPH_BARNUM_MSK                     (0x00070000)
+  #define MPVTDTRK_CR_VDMBDFBARKVM_IMPH_BARNUM_MAX                     (0x00000007)
+  #define MPVTDTRK_CR_VDMBDFBARKVM_IMPH_BARNUM_DEF                     (0x00000007)
+
+#define MPVTDTRK_CR_VDMBDFBARPAVP_IMPH_REG                           (0x00006034)
+  #define MPVTDTRK_CR_VDMBDFBARPAVP_IMPH_FUNNUM_OFF                    ( 0)
+  #define MPVTDTRK_CR_VDMBDFBARPAVP_IMPH_FUNNUM_WID                    ( 3)
+  #define MPVTDTRK_CR_VDMBDFBARPAVP_IMPH_FUNNUM_MSK                    (0x00000007)
+  #define MPVTDTRK_CR_VDMBDFBARPAVP_IMPH_FUNNUM_MAX                    (0x00000007)
+  #define MPVTDTRK_CR_VDMBDFBARPAVP_IMPH_FUNNUM_DEF                    (0x00000000)
+  #define MPVTDTRK_CR_VDMBDFBARPAVP_IMPH_DEVNUM_OFF                    ( 3)
+  #define MPVTDTRK_CR_VDMBDFBARPAVP_IMPH_DEVNUM_WID                    ( 5)
+  #define MPVTDTRK_CR_VDMBDFBARPAVP_IMPH_DEVNUM_MSK                    (0x000000F8)
+  #define MPVTDTRK_CR_VDMBDFBARPAVP_IMPH_DEVNUM_MAX                    (0x0000001F)
+  #define MPVTDTRK_CR_VDMBDFBARPAVP_IMPH_DEVNUM_DEF                    (0x00000016)
+  #define MPVTDTRK_CR_VDMBDFBARPAVP_IMPH_BUSNUM_OFF                    ( 8)
+  #define MPVTDTRK_CR_VDMBDFBARPAVP_IMPH_BUSNUM_WID                    ( 8)
+  #define MPVTDTRK_CR_VDMBDFBARPAVP_IMPH_BUSNUM_MSK                    (0x0000FF00)
+  #define MPVTDTRK_CR_VDMBDFBARPAVP_IMPH_BUSNUM_MAX                    (0x000000FF)
+  #define MPVTDTRK_CR_VDMBDFBARPAVP_IMPH_BUSNUM_DEF                    (0x00000000)
+  #define MPVTDTRK_CR_VDMBDFBARPAVP_IMPH_BARNUM_OFF                    (16)
+  #define MPVTDTRK_CR_VDMBDFBARPAVP_IMPH_BARNUM_WID                    ( 3)
+  #define MPVTDTRK_CR_VDMBDFBARPAVP_IMPH_BARNUM_MSK                    (0x00070000)
+  #define MPVTDTRK_CR_VDMBDFBARPAVP_IMPH_BARNUM_MAX                    (0x00000007)
+  #define MPVTDTRK_CR_VDMBDFBARPAVP_IMPH_BARNUM_DEF                    (0x00000007)
+
+#define MPVTDTRK_CR_VISA_CTL_MPVTDTLBS_IMPH_REG                      (0x00006040)
+  #define MPVTDTRK_CR_VISA_CTL_MPVTDTLBS_IMPH_DATA_OFF                 ( 0)
+  #define MPVTDTRK_CR_VISA_CTL_MPVTDTLBS_IMPH_DATA_WID                 (18)
+  #define MPVTDTRK_CR_VISA_CTL_MPVTDTLBS_IMPH_DATA_MSK                 (0x0003FFFF)
+  #define MPVTDTRK_CR_VISA_CTL_MPVTDTLBS_IMPH_DATA_MAX                 (0x0003FFFF)
+  #define MPVTDTRK_CR_VISA_CTL_MPVTDTLBS_IMPH_DATA_DEF                 (0x00000000)
+  #define MPVTDTRK_CR_VISA_CTL_MPVTDTLBS_IMPH_VORANGE_OFF              (31)
+  #define MPVTDTRK_CR_VISA_CTL_MPVTDTLBS_IMPH_VORANGE_WID              ( 1)
+  #define MPVTDTRK_CR_VISA_CTL_MPVTDTLBS_IMPH_VORANGE_MSK              (0x80000000)
+  #define MPVTDTRK_CR_VISA_CTL_MPVTDTLBS_IMPH_VORANGE_MAX              (0x00000001)
+  #define MPVTDTRK_CR_VISA_CTL_MPVTDTLBS_IMPH_VORANGE_DEF              (0x00000000)
+
+#define MPVTDTRK_CR_VISA_XBAR_MPVTDTLBS_IMPH_REG                     (0x00006044)
+  #define MPVTDTRK_CR_VISA_XBAR_MPVTDTLBS_IMPH_DATA_OFF                ( 0)
+  #define MPVTDTRK_CR_VISA_XBAR_MPVTDTLBS_IMPH_DATA_WID                (32)
+  #define MPVTDTRK_CR_VISA_XBAR_MPVTDTLBS_IMPH_DATA_MSK                (0xFFFFFFFF)
+  #define MPVTDTRK_CR_VISA_XBAR_MPVTDTLBS_IMPH_DATA_MAX                (0xFFFFFFFF)
+  #define MPVTDTRK_CR_VISA_XBAR_MPVTDTLBS_IMPH_DATA_DEF                (0x76543210)
+
+#define MPVTDTRK_CR_VISA_CTL_MPVTMISCS_IMPH_REG                      (0x00006048)
+  #define MPVTDTRK_CR_VISA_CTL_MPVTMISCS_IMPH_DATA_OFF                 ( 0)
+  #define MPVTDTRK_CR_VISA_CTL_MPVTMISCS_IMPH_DATA_WID                 (18)
+  #define MPVTDTRK_CR_VISA_CTL_MPVTMISCS_IMPH_DATA_MSK                 (0x0003FFFF)
+  #define MPVTDTRK_CR_VISA_CTL_MPVTMISCS_IMPH_DATA_MAX                 (0x0003FFFF)
+  #define MPVTDTRK_CR_VISA_CTL_MPVTMISCS_IMPH_DATA_DEF                 (0x00000000)
+  #define MPVTDTRK_CR_VISA_CTL_MPVTMISCS_IMPH_VORANGE_OFF              (31)
+  #define MPVTDTRK_CR_VISA_CTL_MPVTMISCS_IMPH_VORANGE_WID              ( 1)
+  #define MPVTDTRK_CR_VISA_CTL_MPVTMISCS_IMPH_VORANGE_MSK              (0x80000000)
+  #define MPVTDTRK_CR_VISA_CTL_MPVTMISCS_IMPH_VORANGE_MAX              (0x00000001)
+  #define MPVTDTRK_CR_VISA_CTL_MPVTMISCS_IMPH_VORANGE_DEF              (0x00000000)
+
+#define MPVTDTRK_CR_VISA_CTL_MPVTTRKS_IMPH_REG                       (0x0000604C)
+  #define MPVTDTRK_CR_VISA_CTL_MPVTTRKS_IMPH_DATA_OFF                  ( 0)
+  #define MPVTDTRK_CR_VISA_CTL_MPVTTRKS_IMPH_DATA_WID                  (18)
+  #define MPVTDTRK_CR_VISA_CTL_MPVTTRKS_IMPH_DATA_MSK                  (0x0003FFFF)
+  #define MPVTDTRK_CR_VISA_CTL_MPVTTRKS_IMPH_DATA_MAX                  (0x0003FFFF)
+  #define MPVTDTRK_CR_VISA_CTL_MPVTTRKS_IMPH_DATA_DEF                  (0x00000000)
+  #define MPVTDTRK_CR_VISA_CTL_MPVTTRKS_IMPH_VORANGE_OFF               (31)
+  #define MPVTDTRK_CR_VISA_CTL_MPVTTRKS_IMPH_VORANGE_WID               ( 1)
+  #define MPVTDTRK_CR_VISA_CTL_MPVTTRKS_IMPH_VORANGE_MSK               (0x80000000)
+  #define MPVTDTRK_CR_VISA_CTL_MPVTTRKS_IMPH_VORANGE_MAX               (0x00000001)
+  #define MPVTDTRK_CR_VISA_CTL_MPVTTRKS_IMPH_VORANGE_DEF               (0x00000000)
+
+#define MPVTDTRK_CR_PRIMUP_MASK1_IMPH_REG                            (0x00006050)
+  #define MPVTDTRK_CR_PRIMUP_MASK1_IMPH_VC_OFF                         ( 0)
+  #define MPVTDTRK_CR_PRIMUP_MASK1_IMPH_VC_WID                         ( 4)
+  #define MPVTDTRK_CR_PRIMUP_MASK1_IMPH_VC_MSK                         (0x0000000F)
+  #define MPVTDTRK_CR_PRIMUP_MASK1_IMPH_VC_MAX                         (0x0000000F)
+  #define MPVTDTRK_CR_PRIMUP_MASK1_IMPH_VC_DEF                         (0x00000000)
+  #define MPVTDTRK_CR_PRIMUP_MASK1_IMPH_FMT_CMDTYPE_OFF                ( 4)
+  #define MPVTDTRK_CR_PRIMUP_MASK1_IMPH_FMT_CMDTYPE_WID                ( 6)
+  #define MPVTDTRK_CR_PRIMUP_MASK1_IMPH_FMT_CMDTYPE_MSK                (0x000003F0)
+  #define MPVTDTRK_CR_PRIMUP_MASK1_IMPH_FMT_CMDTYPE_MAX                (0x0000003F)
+  #define MPVTDTRK_CR_PRIMUP_MASK1_IMPH_FMT_CMDTYPE_DEF                (0x00000000)
+  #define MPVTDTRK_CR_PRIMUP_MASK1_IMPH_TC_OFF                         (10)
+  #define MPVTDTRK_CR_PRIMUP_MASK1_IMPH_TC_WID                         ( 4)
+  #define MPVTDTRK_CR_PRIMUP_MASK1_IMPH_TC_MSK                         (0x00003C00)
+  #define MPVTDTRK_CR_PRIMUP_MASK1_IMPH_TC_MAX                         (0x0000000F)
+  #define MPVTDTRK_CR_PRIMUP_MASK1_IMPH_TC_DEF                         (0x00000000)
+  #define MPVTDTRK_CR_PRIMUP_MASK1_IMPH_CHAIN_OFF                      (14)
+  #define MPVTDTRK_CR_PRIMUP_MASK1_IMPH_CHAIN_WID                      ( 1)
+  #define MPVTDTRK_CR_PRIMUP_MASK1_IMPH_CHAIN_MSK                      (0x00004000)
+  #define MPVTDTRK_CR_PRIMUP_MASK1_IMPH_CHAIN_MAX                      (0x00000001)
+  #define MPVTDTRK_CR_PRIMUP_MASK1_IMPH_CHAIN_DEF                      (0x00000000)
+  #define MPVTDTRK_CR_PRIMUP_MASK1_IMPH_NS_OFF                         (15)
+  #define MPVTDTRK_CR_PRIMUP_MASK1_IMPH_NS_WID                         ( 1)
+  #define MPVTDTRK_CR_PRIMUP_MASK1_IMPH_NS_MSK                         (0x00008000)
+  #define MPVTDTRK_CR_PRIMUP_MASK1_IMPH_NS_MAX                         (0x00000001)
+  #define MPVTDTRK_CR_PRIMUP_MASK1_IMPH_NS_DEF                         (0x00000000)
+  #define MPVTDTRK_CR_PRIMUP_MASK1_IMPH_RO_OFF                         (16)
+  #define MPVTDTRK_CR_PRIMUP_MASK1_IMPH_RO_WID                         ( 1)
+  #define MPVTDTRK_CR_PRIMUP_MASK1_IMPH_RO_MSK                         (0x00010000)
+  #define MPVTDTRK_CR_PRIMUP_MASK1_IMPH_RO_MAX                         (0x00000001)
+  #define MPVTDTRK_CR_PRIMUP_MASK1_IMPH_RO_DEF                         (0x00000000)
+  #define MPVTDTRK_CR_PRIMUP_MASK1_IMPH_LENGTH_OFF                     (17)
+  #define MPVTDTRK_CR_PRIMUP_MASK1_IMPH_LENGTH_WID                     ( 5)
+  #define MPVTDTRK_CR_PRIMUP_MASK1_IMPH_LENGTH_MSK                     (0x003E0000)
+  #define MPVTDTRK_CR_PRIMUP_MASK1_IMPH_LENGTH_MAX                     (0x0000001F)
+  #define MPVTDTRK_CR_PRIMUP_MASK1_IMPH_LENGTH_DEF                     (0x00000000)
+  #define MPVTDTRK_CR_PRIMUP_MASK1_IMPH_EP_OFF                         (22)
+  #define MPVTDTRK_CR_PRIMUP_MASK1_IMPH_EP_WID                         ( 1)
+  #define MPVTDTRK_CR_PRIMUP_MASK1_IMPH_EP_MSK                         (0x00400000)
+  #define MPVTDTRK_CR_PRIMUP_MASK1_IMPH_EP_MAX                         (0x00000001)
+  #define MPVTDTRK_CR_PRIMUP_MASK1_IMPH_EP_DEF                         (0x00000000)
+  #define MPVTDTRK_CR_PRIMUP_MASK1_IMPH_AT_OFF                         (23)
+  #define MPVTDTRK_CR_PRIMUP_MASK1_IMPH_AT_WID                         ( 2)
+  #define MPVTDTRK_CR_PRIMUP_MASK1_IMPH_AT_MSK                         (0x01800000)
+  #define MPVTDTRK_CR_PRIMUP_MASK1_IMPH_AT_MAX                         (0x00000003)
+  #define MPVTDTRK_CR_PRIMUP_MASK1_IMPH_AT_DEF                         (0x00000000)
+
+#define MPVTDTRK_CR_PRIMUP_MASK2_IMPH_REG                            (0x00006054)
+  #define MPVTDTRK_CR_PRIMUP_MASK2_IMPH_RQID_OFF                       ( 0)
+  #define MPVTDTRK_CR_PRIMUP_MASK2_IMPH_RQID_WID                       (16)
+  #define MPVTDTRK_CR_PRIMUP_MASK2_IMPH_RQID_MSK                       (0x0000FFFF)
+  #define MPVTDTRK_CR_PRIMUP_MASK2_IMPH_RQID_MAX                       (0x0000FFFF)
+  #define MPVTDTRK_CR_PRIMUP_MASK2_IMPH_RQID_DEF                       (0x00000000)
+  #define MPVTDTRK_CR_PRIMUP_MASK2_IMPH_TAG_OFF                        (16)
+  #define MPVTDTRK_CR_PRIMUP_MASK2_IMPH_TAG_WID                        ( 8)
+  #define MPVTDTRK_CR_PRIMUP_MASK2_IMPH_TAG_MSK                        (0x00FF0000)
+  #define MPVTDTRK_CR_PRIMUP_MASK2_IMPH_TAG_MAX                        (0x000000FF)
+  #define MPVTDTRK_CR_PRIMUP_MASK2_IMPH_TAG_DEF                        (0x00000000)
+  #define MPVTDTRK_CR_PRIMUP_MASK2_IMPH_LBEFBE_MSGTYPE_OFF             (24)
+  #define MPVTDTRK_CR_PRIMUP_MASK2_IMPH_LBEFBE_MSGTYPE_WID             ( 8)
+  #define MPVTDTRK_CR_PRIMUP_MASK2_IMPH_LBEFBE_MSGTYPE_MSK             (0xFF000000)
+  #define MPVTDTRK_CR_PRIMUP_MASK2_IMPH_LBEFBE_MSGTYPE_MAX             (0x000000FF)
+  #define MPVTDTRK_CR_PRIMUP_MASK2_IMPH_LBEFBE_MSGTYPE_DEF             (0x00000000)
+
+#define MPVTDTRK_CR_PRIMUP_MASK3_IMPH_REG                            (0x00006058)
+  #define MPVTDTRK_CR_PRIMUP_MASK3_IMPH_ADDR_31_0_OFF                  ( 0)
+  #define MPVTDTRK_CR_PRIMUP_MASK3_IMPH_ADDR_31_0_WID                  (32)
+  #define MPVTDTRK_CR_PRIMUP_MASK3_IMPH_ADDR_31_0_MSK                  (0xFFFFFFFF)
+  #define MPVTDTRK_CR_PRIMUP_MASK3_IMPH_ADDR_31_0_MAX                  (0xFFFFFFFF)
+  #define MPVTDTRK_CR_PRIMUP_MASK3_IMPH_ADDR_31_0_DEF                  (0x00000000)
+
+#define MPVTDTRK_CR_PRIMUP_MASK4_IMPH_REG                            (0x0000605C)
+  #define MPVTDTRK_CR_PRIMUP_MASK4_IMPH_ADDR_63_32_OFF                 ( 0)
+  #define MPVTDTRK_CR_PRIMUP_MASK4_IMPH_ADDR_63_32_WID                 (32)
+  #define MPVTDTRK_CR_PRIMUP_MASK4_IMPH_ADDR_63_32_MSK                 (0xFFFFFFFF)
+  #define MPVTDTRK_CR_PRIMUP_MASK4_IMPH_ADDR_63_32_MAX                 (0xFFFFFFFF)
+  #define MPVTDTRK_CR_PRIMUP_MASK4_IMPH_ADDR_63_32_DEF                 (0x00000000)
+
+#define MPVTDTRK_CR_PRIMUP_COMP1_IMPH_REG                            (0x00006060)
+  #define MPVTDTRK_CR_PRIMUP_COMP1_IMPH_VC_OFF                         ( 0)
+  #define MPVTDTRK_CR_PRIMUP_COMP1_IMPH_VC_WID                         ( 4)
+  #define MPVTDTRK_CR_PRIMUP_COMP1_IMPH_VC_MSK                         (0x0000000F)
+  #define MPVTDTRK_CR_PRIMUP_COMP1_IMPH_VC_MAX                         (0x0000000F)
+  #define MPVTDTRK_CR_PRIMUP_COMP1_IMPH_VC_DEF                         (0x00000000)
+  #define MPVTDTRK_CR_PRIMUP_COMP1_IMPH_FMT_CMDTYPE_OFF                ( 4)
+  #define MPVTDTRK_CR_PRIMUP_COMP1_IMPH_FMT_CMDTYPE_WID                ( 6)
+  #define MPVTDTRK_CR_PRIMUP_COMP1_IMPH_FMT_CMDTYPE_MSK                (0x000003F0)
+  #define MPVTDTRK_CR_PRIMUP_COMP1_IMPH_FMT_CMDTYPE_MAX                (0x0000003F)
+  #define MPVTDTRK_CR_PRIMUP_COMP1_IMPH_FMT_CMDTYPE_DEF                (0x00000000)
+  #define MPVTDTRK_CR_PRIMUP_COMP1_IMPH_TC_OFF                         (10)
+  #define MPVTDTRK_CR_PRIMUP_COMP1_IMPH_TC_WID                         ( 4)
+  #define MPVTDTRK_CR_PRIMUP_COMP1_IMPH_TC_MSK                         (0x00003C00)
+  #define MPVTDTRK_CR_PRIMUP_COMP1_IMPH_TC_MAX                         (0x0000000F)
+  #define MPVTDTRK_CR_PRIMUP_COMP1_IMPH_TC_DEF                         (0x00000000)
+  #define MPVTDTRK_CR_PRIMUP_COMP1_IMPH_CHAIN_OFF                      (14)
+  #define MPVTDTRK_CR_PRIMUP_COMP1_IMPH_CHAIN_WID                      ( 1)
+  #define MPVTDTRK_CR_PRIMUP_COMP1_IMPH_CHAIN_MSK                      (0x00004000)
+  #define MPVTDTRK_CR_PRIMUP_COMP1_IMPH_CHAIN_MAX                      (0x00000001)
+  #define MPVTDTRK_CR_PRIMUP_COMP1_IMPH_CHAIN_DEF                      (0x00000000)
+  #define MPVTDTRK_CR_PRIMUP_COMP1_IMPH_NS_OFF                         (15)
+  #define MPVTDTRK_CR_PRIMUP_COMP1_IMPH_NS_WID                         ( 1)
+  #define MPVTDTRK_CR_PRIMUP_COMP1_IMPH_NS_MSK                         (0x00008000)
+  #define MPVTDTRK_CR_PRIMUP_COMP1_IMPH_NS_MAX                         (0x00000001)
+  #define MPVTDTRK_CR_PRIMUP_COMP1_IMPH_NS_DEF                         (0x00000000)
+  #define MPVTDTRK_CR_PRIMUP_COMP1_IMPH_RO_OFF                         (16)
+  #define MPVTDTRK_CR_PRIMUP_COMP1_IMPH_RO_WID                         ( 1)
+  #define MPVTDTRK_CR_PRIMUP_COMP1_IMPH_RO_MSK                         (0x00010000)
+  #define MPVTDTRK_CR_PRIMUP_COMP1_IMPH_RO_MAX                         (0x00000001)
+  #define MPVTDTRK_CR_PRIMUP_COMP1_IMPH_RO_DEF                         (0x00000000)
+  #define MPVTDTRK_CR_PRIMUP_COMP1_IMPH_LENGTH_OFF                     (17)
+  #define MPVTDTRK_CR_PRIMUP_COMP1_IMPH_LENGTH_WID                     ( 5)
+  #define MPVTDTRK_CR_PRIMUP_COMP1_IMPH_LENGTH_MSK                     (0x003E0000)
+  #define MPVTDTRK_CR_PRIMUP_COMP1_IMPH_LENGTH_MAX                     (0x0000001F)
+  #define MPVTDTRK_CR_PRIMUP_COMP1_IMPH_LENGTH_DEF                     (0x00000000)
+  #define MPVTDTRK_CR_PRIMUP_COMP1_IMPH_EP_OFF                         (22)
+  #define MPVTDTRK_CR_PRIMUP_COMP1_IMPH_EP_WID                         ( 1)
+  #define MPVTDTRK_CR_PRIMUP_COMP1_IMPH_EP_MSK                         (0x00400000)
+  #define MPVTDTRK_CR_PRIMUP_COMP1_IMPH_EP_MAX                         (0x00000001)
+  #define MPVTDTRK_CR_PRIMUP_COMP1_IMPH_EP_DEF                         (0x00000000)
+  #define MPVTDTRK_CR_PRIMUP_COMP1_IMPH_AT_OFF                         (23)
+  #define MPVTDTRK_CR_PRIMUP_COMP1_IMPH_AT_WID                         ( 2)
+  #define MPVTDTRK_CR_PRIMUP_COMP1_IMPH_AT_MSK                         (0x01800000)
+  #define MPVTDTRK_CR_PRIMUP_COMP1_IMPH_AT_MAX                         (0x00000003)
+  #define MPVTDTRK_CR_PRIMUP_COMP1_IMPH_AT_DEF                         (0x00000000)
+
+#define MPVTDTRK_CR_PRIMUP_COMP2_IMPH_REG                            (0x00006064)
+  #define MPVTDTRK_CR_PRIMUP_COMP2_IMPH_RQID_OFF                       ( 0)
+  #define MPVTDTRK_CR_PRIMUP_COMP2_IMPH_RQID_WID                       (16)
+  #define MPVTDTRK_CR_PRIMUP_COMP2_IMPH_RQID_MSK                       (0x0000FFFF)
+  #define MPVTDTRK_CR_PRIMUP_COMP2_IMPH_RQID_MAX                       (0x0000FFFF)
+  #define MPVTDTRK_CR_PRIMUP_COMP2_IMPH_RQID_DEF                       (0x00000000)
+  #define MPVTDTRK_CR_PRIMUP_COMP2_IMPH_TAG_OFF                        (16)
+  #define MPVTDTRK_CR_PRIMUP_COMP2_IMPH_TAG_WID                        ( 8)
+  #define MPVTDTRK_CR_PRIMUP_COMP2_IMPH_TAG_MSK                        (0x00FF0000)
+  #define MPVTDTRK_CR_PRIMUP_COMP2_IMPH_TAG_MAX                        (0x000000FF)
+  #define MPVTDTRK_CR_PRIMUP_COMP2_IMPH_TAG_DEF                        (0x00000000)
+  #define MPVTDTRK_CR_PRIMUP_COMP2_IMPH_LBEFBE_MSGTYPE_OFF             (24)
+  #define MPVTDTRK_CR_PRIMUP_COMP2_IMPH_LBEFBE_MSGTYPE_WID             ( 8)
+  #define MPVTDTRK_CR_PRIMUP_COMP2_IMPH_LBEFBE_MSGTYPE_MSK             (0xFF000000)
+  #define MPVTDTRK_CR_PRIMUP_COMP2_IMPH_LBEFBE_MSGTYPE_MAX             (0x000000FF)
+  #define MPVTDTRK_CR_PRIMUP_COMP2_IMPH_LBEFBE_MSGTYPE_DEF             (0x00000000)
+
+#define MPVTDTRK_CR_PRIMUP_COMP3_IMPH_REG                            (0x00006068)
+  #define MPVTDTRK_CR_PRIMUP_COMP3_IMPH_ADDR_31_0_OFF                  ( 0)
+  #define MPVTDTRK_CR_PRIMUP_COMP3_IMPH_ADDR_31_0_WID                  (32)
+  #define MPVTDTRK_CR_PRIMUP_COMP3_IMPH_ADDR_31_0_MSK                  (0xFFFFFFFF)
+  #define MPVTDTRK_CR_PRIMUP_COMP3_IMPH_ADDR_31_0_MAX                  (0xFFFFFFFF)
+  #define MPVTDTRK_CR_PRIMUP_COMP3_IMPH_ADDR_31_0_DEF                  (0x00000000)
+
+#define MPVTDTRK_CR_PRIMUP_COMP4_IMPH_REG                            (0x0000606C)
+  #define MPVTDTRK_CR_PRIMUP_COMP4_IMPH_ADDR_63_32_OFF                 ( 0)
+  #define MPVTDTRK_CR_PRIMUP_COMP4_IMPH_ADDR_63_32_WID                 (32)
+  #define MPVTDTRK_CR_PRIMUP_COMP4_IMPH_ADDR_63_32_MSK                 (0xFFFFFFFF)
+  #define MPVTDTRK_CR_PRIMUP_COMP4_IMPH_ADDR_63_32_MAX                 (0xFFFFFFFF)
+  #define MPVTDTRK_CR_PRIMUP_COMP4_IMPH_ADDR_63_32_DEF                 (0x00000000)
+
+#define MPVTDTRK_CR_PRIMUP_TRIGGER_IMPH_REG                          (0x00006070)
+  #define MPVTDTRK_CR_PRIMUP_TRIGGER_IMPH_ENABLE_OFF                   ( 0)
+  #define MPVTDTRK_CR_PRIMUP_TRIGGER_IMPH_ENABLE_WID                   ( 1)
+  #define MPVTDTRK_CR_PRIMUP_TRIGGER_IMPH_ENABLE_MSK                   (0x00000001)
+  #define MPVTDTRK_CR_PRIMUP_TRIGGER_IMPH_ENABLE_MAX                   (0x00000001)
+  #define MPVTDTRK_CR_PRIMUP_TRIGGER_IMPH_ENABLE_DEF                   (0x00000000)
+  #define MPVTDTRK_CR_PRIMUP_TRIGGER_IMPH_TRIGGERED_OFF                ( 1)
+  #define MPVTDTRK_CR_PRIMUP_TRIGGER_IMPH_TRIGGERED_WID                ( 1)
+  #define MPVTDTRK_CR_PRIMUP_TRIGGER_IMPH_TRIGGERED_MSK                (0x00000002)
+  #define MPVTDTRK_CR_PRIMUP_TRIGGER_IMPH_TRIGGERED_MAX                (0x00000001)
+  #define MPVTDTRK_CR_PRIMUP_TRIGGER_IMPH_TRIGGERED_DEF                (0x00000000)
+  #define MPVTDTRK_CR_PRIMUP_TRIGGER_IMPH_STALL_DNARB_OFF              ( 2)
+  #define MPVTDTRK_CR_PRIMUP_TRIGGER_IMPH_STALL_DNARB_WID              ( 1)
+  #define MPVTDTRK_CR_PRIMUP_TRIGGER_IMPH_STALL_DNARB_MSK              (0x00000004)
+  #define MPVTDTRK_CR_PRIMUP_TRIGGER_IMPH_STALL_DNARB_MAX              (0x00000001)
+  #define MPVTDTRK_CR_PRIMUP_TRIGGER_IMPH_STALL_DNARB_DEF              (0x00000000)
+  #define MPVTDTRK_CR_PRIMUP_TRIGGER_IMPH_STALL_UPARB_OFF              ( 3)
+  #define MPVTDTRK_CR_PRIMUP_TRIGGER_IMPH_STALL_UPARB_WID              ( 1)
+  #define MPVTDTRK_CR_PRIMUP_TRIGGER_IMPH_STALL_UPARB_MSK              (0x00000008)
+  #define MPVTDTRK_CR_PRIMUP_TRIGGER_IMPH_STALL_UPARB_MAX              (0x00000001)
+  #define MPVTDTRK_CR_PRIMUP_TRIGGER_IMPH_STALL_UPARB_DEF              (0x00000000)
+  #define MPVTDTRK_CR_PRIMUP_TRIGGER_IMPH_STALL_SNPARB_OFF             ( 4)
+  #define MPVTDTRK_CR_PRIMUP_TRIGGER_IMPH_STALL_SNPARB_WID             ( 1)
+  #define MPVTDTRK_CR_PRIMUP_TRIGGER_IMPH_STALL_SNPARB_MSK             (0x00000010)
+  #define MPVTDTRK_CR_PRIMUP_TRIGGER_IMPH_STALL_SNPARB_MAX             (0x00000001)
+  #define MPVTDTRK_CR_PRIMUP_TRIGGER_IMPH_STALL_SNPARB_DEF             (0x00000000)
+  #define MPVTDTRK_CR_PRIMUP_TRIGGER_IMPH_STALL_DELAY_OFF              (23)
+  #define MPVTDTRK_CR_PRIMUP_TRIGGER_IMPH_STALL_DELAY_WID              ( 9)
+  #define MPVTDTRK_CR_PRIMUP_TRIGGER_IMPH_STALL_DELAY_MSK              (0xFF800000)
+  #define MPVTDTRK_CR_PRIMUP_TRIGGER_IMPH_STALL_DELAY_MAX              (0x000001FF)
+  #define MPVTDTRK_CR_PRIMUP_TRIGGER_IMPH_STALL_DELAY_DEF              (0x00000000)
+
+#define MPVTDTRK_CR_HCTL0_IMPH_REG                                   (0x00006100)
+  #define MPVTDTRK_CR_HCTL0_IMPH_PEG2DMIDIS_OFF                        ( 0)
+  #define MPVTDTRK_CR_HCTL0_IMPH_PEG2DMIDIS_WID                        ( 1)
+  #define MPVTDTRK_CR_HCTL0_IMPH_PEG2DMIDIS_MSK                        (0x00000001)
+  #define MPVTDTRK_CR_HCTL0_IMPH_PEG2DMIDIS_MAX                        (0x00000001)
+  #define MPVTDTRK_CR_HCTL0_IMPH_PEG2DMIDIS_DEF                        (0x00000000)
+  #define MPVTDTRK_CR_HCTL0_IMPH_EOIB_OFF                              ( 1)
+  #define MPVTDTRK_CR_HCTL0_IMPH_EOIB_WID                              ( 1)
+  #define MPVTDTRK_CR_HCTL0_IMPH_EOIB_MSK                              (0x00000002)
+  #define MPVTDTRK_CR_HCTL0_IMPH_EOIB_MAX                              (0x00000001)
+  #define MPVTDTRK_CR_HCTL0_IMPH_EOIB_DEF                              (0x00000000)
+  #define MPVTDTRK_CR_HCTL0_IMPH_MSIBYPDIS_OFF                         ( 2)
+  #define MPVTDTRK_CR_HCTL0_IMPH_MSIBYPDIS_WID                         ( 1)
+  #define MPVTDTRK_CR_HCTL0_IMPH_MSIBYPDIS_MSK                         (0x00000004)
+  #define MPVTDTRK_CR_HCTL0_IMPH_MSIBYPDIS_MAX                         (0x00000001)
+  #define MPVTDTRK_CR_HCTL0_IMPH_MSIBYPDIS_DEF                         (0x00000000)
+  #define MPVTDTRK_CR_HCTL0_IMPH_PHLDDIS_OFF                           ( 4)
+  #define MPVTDTRK_CR_HCTL0_IMPH_PHLDDIS_WID                           ( 1)
+  #define MPVTDTRK_CR_HCTL0_IMPH_PHLDDIS_MSK                           (0x00000010)
+  #define MPVTDTRK_CR_HCTL0_IMPH_PHLDDIS_MAX                           (0x00000001)
+  #define MPVTDTRK_CR_HCTL0_IMPH_PHLDDIS_DEF                           (0x00000000)
+  #define MPVTDTRK_CR_HCTL0_IMPH_BKSNPDIS_OFF                          ( 6)
+  #define MPVTDTRK_CR_HCTL0_IMPH_BKSNPDIS_WID                          ( 1)
+  #define MPVTDTRK_CR_HCTL0_IMPH_BKSNPDIS_MSK                          (0x00000040)
+  #define MPVTDTRK_CR_HCTL0_IMPH_BKSNPDIS_MAX                          (0x00000001)
+  #define MPVTDTRK_CR_HCTL0_IMPH_BKSNPDIS_DEF                          (0x00000000)
+  #define MPVTDTRK_CR_HCTL0_IMPH_FRCVC0SNP_OFF                         ( 7)
+  #define MPVTDTRK_CR_HCTL0_IMPH_FRCVC0SNP_WID                         ( 1)
+  #define MPVTDTRK_CR_HCTL0_IMPH_FRCVC0SNP_MSK                         (0x00000080)
+  #define MPVTDTRK_CR_HCTL0_IMPH_FRCVC0SNP_MAX                         (0x00000001)
+  #define MPVTDTRK_CR_HCTL0_IMPH_FRCVC0SNP_DEF                         (0x00000000)
+  #define MPVTDTRK_CR_HCTL0_IMPH_FRCVCPSNP_OFF                         ( 8)
+  #define MPVTDTRK_CR_HCTL0_IMPH_FRCVCPSNP_WID                         ( 1)
+  #define MPVTDTRK_CR_HCTL0_IMPH_FRCVCPSNP_MSK                         (0x00000100)
+  #define MPVTDTRK_CR_HCTL0_IMPH_FRCVCPSNP_MAX                         (0x00000001)
+  #define MPVTDTRK_CR_HCTL0_IMPH_FRCVCPSNP_DEF                         (0x00000000)
+  #define MPVTDTRK_CR_HCTL0_IMPH_PHLDBLKDIS_OFF                        ( 9)
+  #define MPVTDTRK_CR_HCTL0_IMPH_PHLDBLKDIS_WID                        ( 1)
+  #define MPVTDTRK_CR_HCTL0_IMPH_PHLDBLKDIS_MSK                        (0x00000200)
+  #define MPVTDTRK_CR_HCTL0_IMPH_PHLDBLKDIS_MAX                        (0x00000001)
+  #define MPVTDTRK_CR_HCTL0_IMPH_PHLDBLKDIS_DEF                        (0x00000000)
+  #define MPVTDTRK_CR_HCTL0_IMPH_BLKWRPOSTVC1_OFF                      (10)
+  #define MPVTDTRK_CR_HCTL0_IMPH_BLKWRPOSTVC1_WID                      ( 1)
+  #define MPVTDTRK_CR_HCTL0_IMPH_BLKWRPOSTVC1_MSK                      (0x00000400)
+  #define MPVTDTRK_CR_HCTL0_IMPH_BLKWRPOSTVC1_MAX                      (0x00000001)
+  #define MPVTDTRK_CR_HCTL0_IMPH_BLKWRPOSTVC1_DEF                      (0x00000000)
+  #define MPVTDTRK_CR_HCTL0_IMPH_DIS_VLW_PEG_OFF                       (11)
+  #define MPVTDTRK_CR_HCTL0_IMPH_DIS_VLW_PEG_WID                       ( 1)
+  #define MPVTDTRK_CR_HCTL0_IMPH_DIS_VLW_PEG_MSK                       (0x00000800)
+  #define MPVTDTRK_CR_HCTL0_IMPH_DIS_VLW_PEG_MAX                       (0x00000001)
+  #define MPVTDTRK_CR_HCTL0_IMPH_DIS_VLW_PEG_DEF                       (0x00000000)
+  #define MPVTDTRK_CR_HCTL0_IMPH_SPECRDDIS_OFF                         (12)
+  #define MPVTDTRK_CR_HCTL0_IMPH_SPECRDDIS_WID                         ( 1)
+  #define MPVTDTRK_CR_HCTL0_IMPH_SPECRDDIS_MSK                         (0x00001000)
+  #define MPVTDTRK_CR_HCTL0_IMPH_SPECRDDIS_MAX                         (0x00000001)
+  #define MPVTDTRK_CR_HCTL0_IMPH_SPECRDDIS_DEF                         (0x00000000)
+  #define MPVTDTRK_CR_HCTL0_IMPH_IR_RSRV_CTL_OFF                       (13)
+  #define MPVTDTRK_CR_HCTL0_IMPH_IR_RSRV_CTL_WID                       ( 1)
+  #define MPVTDTRK_CR_HCTL0_IMPH_IR_RSRV_CTL_MSK                       (0x00002000)
+  #define MPVTDTRK_CR_HCTL0_IMPH_IR_RSRV_CTL_MAX                       (0x00000001)
+  #define MPVTDTRK_CR_HCTL0_IMPH_IR_RSRV_CTL_DEF                       (0x00000000)
+  #define MPVTDTRK_CR_HCTL0_IMPH_RSVD_OFF                              (14)
+  #define MPVTDTRK_CR_HCTL0_IMPH_RSVD_WID                              (18)
+  #define MPVTDTRK_CR_HCTL0_IMPH_RSVD_MSK                              (0xFFFFC000)
+  #define MPVTDTRK_CR_HCTL0_IMPH_RSVD_MAX                              (0x0003FFFF)
+  #define MPVTDTRK_CR_HCTL0_IMPH_RSVD_DEF                              (0x00000000)
+
+#define MPVTDTRK_CR_REGBAR_IMPH_REG                                  (0x00006110)
+  #define MPVTDTRK_CR_REGBAR_IMPH_REGBAR_OFF                           ( 4)
+  #define MPVTDTRK_CR_REGBAR_IMPH_REGBAR_WID                           (35)
+  #define MPVTDTRK_CR_REGBAR_IMPH_REGBAR_MSK                           (0x7FFFFFFFF0)
+  #define MPVTDTRK_CR_REGBAR_IMPH_REGBAR_MAX                           (0x7FFFFFFFF)
+  #define MPVTDTRK_CR_REGBAR_IMPH_REGBAR_DEF                           (0x00000000)
+
+#define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_REG              (0x00006200)
+  #define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_THERMAL_MONITOR_STATUS_OFF ( 0)
+  #define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_THERMAL_MONITOR_STATUS_WID ( 1)
+  #define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_THERMAL_MONITOR_STATUS_MSK (0x00000001)
+  #define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_THERMAL_MONITOR_STATUS_MAX (0x00000001)
+  #define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_THERMAL_MONITOR_STATUS_DEF (0x00000000)
+  #define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_THERMAL_MONITOR_LOG_OFF ( 1)
+  #define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_THERMAL_MONITOR_LOG_WID ( 1)
+  #define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_THERMAL_MONITOR_LOG_MSK (0x00000002)
+  #define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_THERMAL_MONITOR_LOG_MAX (0x00000001)
+  #define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_THERMAL_MONITOR_LOG_DEF (0x00000000)
+  #define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_PROCHOT_STATUS_OFF ( 2)
+  #define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_PROCHOT_STATUS_WID ( 1)
+  #define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_PROCHOT_STATUS_MSK (0x00000004)
+  #define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_PROCHOT_STATUS_MAX (0x00000001)
+  #define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_PROCHOT_STATUS_DEF (0x00000000)
+  #define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_PROCHOT_LOG_OFF  ( 3)
+  #define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_PROCHOT_LOG_WID  ( 1)
+  #define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_PROCHOT_LOG_MSK  (0x00000008)
+  #define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_PROCHOT_LOG_MAX  (0x00000001)
+  #define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_PROCHOT_LOG_DEF  (0x00000000)
+  #define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_OUT_OF_SPEC_STATUS_OFF ( 4)
+  #define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_OUT_OF_SPEC_STATUS_WID ( 1)
+  #define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_OUT_OF_SPEC_STATUS_MSK (0x00000010)
+  #define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_OUT_OF_SPEC_STATUS_MAX (0x00000001)
+  #define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_OUT_OF_SPEC_STATUS_DEF (0x00000000)
+  #define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_OUT_OF_SPEC_LOG_OFF ( 5)
+  #define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_OUT_OF_SPEC_LOG_WID ( 1)
+  #define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_OUT_OF_SPEC_LOG_MSK (0x00000020)
+  #define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_OUT_OF_SPEC_LOG_MAX (0x00000001)
+  #define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_OUT_OF_SPEC_LOG_DEF (0x00000000)
+  #define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_THRESHOLD1_STATUS_OFF ( 6)
+  #define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_THRESHOLD1_STATUS_WID ( 1)
+  #define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_THRESHOLD1_STATUS_MSK (0x00000040)
+  #define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_THRESHOLD1_STATUS_MAX (0x00000001)
+  #define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_THRESHOLD1_STATUS_DEF (0x00000000)
+  #define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_THRESHOLD1_LOG_OFF ( 7)
+  #define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_THRESHOLD1_LOG_WID ( 1)
+  #define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_THRESHOLD1_LOG_MSK (0x00000080)
+  #define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_THRESHOLD1_LOG_MAX (0x00000001)
+  #define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_THRESHOLD1_LOG_DEF (0x00000000)
+  #define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_THRESHOLD2_STATUS_OFF ( 8)
+  #define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_THRESHOLD2_STATUS_WID ( 1)
+  #define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_THRESHOLD2_STATUS_MSK (0x00000100)
+  #define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_THRESHOLD2_STATUS_MAX (0x00000001)
+  #define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_THRESHOLD2_STATUS_DEF (0x00000000)
+  #define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_THRESHOLD2_LOG_OFF ( 9)
+  #define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_THRESHOLD2_LOG_WID ( 1)
+  #define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_THRESHOLD2_LOG_MSK (0x00000200)
+  #define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_THRESHOLD2_LOG_MAX (0x00000001)
+  #define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_THRESHOLD2_LOG_DEF (0x00000000)
+  #define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_POWER_LIMITATION_STATUS_OFF (10)
+  #define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_POWER_LIMITATION_STATUS_WID ( 1)
+  #define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_POWER_LIMITATION_STATUS_MSK (0x00000400)
+  #define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_POWER_LIMITATION_STATUS_MAX (0x00000001)
+  #define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_POWER_LIMITATION_STATUS_DEF (0x00000000)
+  #define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_POWER_LIMITATION_LOG_OFF (11)
+  #define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_POWER_LIMITATION_LOG_WID ( 1)
+  #define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_POWER_LIMITATION_LOG_MSK (0x00000800)
+  #define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_POWER_LIMITATION_LOG_MAX (0x00000001)
+  #define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_POWER_LIMITATION_LOG_DEF (0x00000000)
+  #define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_Temperature_OFF  (16)
+  #define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_Temperature_WID  ( 7)
+  #define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_Temperature_MSK  (0x007F0000)
+  #define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_Temperature_MAX  (0x0000007F)
+  #define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_Temperature_DEF  (0x00000000)
+  #define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_Resolution_OFF   (27)
+  #define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_Resolution_WID   ( 4)
+  #define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_Resolution_MSK   (0x78000000)
+  #define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_Resolution_MAX   (0x0000000F)
+  #define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_Resolution_DEF   (0x00000001)
+  #define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_Valid_OFF        (31)
+  #define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_Valid_WID        ( 1)
+  #define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_Valid_MSK        (0x80000000)
+  #define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_Valid_MAX        (0x00000001)
+  #define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_Valid_DEF        (0x00000000)
+
+#define MPVTDTRK_CR_DDR_THERM_CAMARILLO_STATUS_IMPH_REG              (0x00006204)
+  #define MPVTDTRK_CR_DDR_THERM_CAMARILLO_STATUS_IMPH_WARM_THRESHOLD_STATUS_OFF ( 0)
+  #define MPVTDTRK_CR_DDR_THERM_CAMARILLO_STATUS_IMPH_WARM_THRESHOLD_STATUS_WID ( 1)
+  #define MPVTDTRK_CR_DDR_THERM_CAMARILLO_STATUS_IMPH_WARM_THRESHOLD_STATUS_MSK (0x00000001)
+  #define MPVTDTRK_CR_DDR_THERM_CAMARILLO_STATUS_IMPH_WARM_THRESHOLD_STATUS_MAX (0x00000001)
+  #define MPVTDTRK_CR_DDR_THERM_CAMARILLO_STATUS_IMPH_WARM_THRESHOLD_STATUS_DEF (0x00000000)
+  #define MPVTDTRK_CR_DDR_THERM_CAMARILLO_STATUS_IMPH_WARM_THRESHOLD_LOG_OFF ( 1)
+  #define MPVTDTRK_CR_DDR_THERM_CAMARILLO_STATUS_IMPH_WARM_THRESHOLD_LOG_WID ( 1)
+  #define MPVTDTRK_CR_DDR_THERM_CAMARILLO_STATUS_IMPH_WARM_THRESHOLD_LOG_MSK (0x00000002)
+  #define MPVTDTRK_CR_DDR_THERM_CAMARILLO_STATUS_IMPH_WARM_THRESHOLD_LOG_MAX (0x00000001)
+  #define MPVTDTRK_CR_DDR_THERM_CAMARILLO_STATUS_IMPH_WARM_THRESHOLD_LOG_DEF (0x00000000)
+  #define MPVTDTRK_CR_DDR_THERM_CAMARILLO_STATUS_IMPH_HOT_THRESHOLD_STATUS_OFF ( 2)
+  #define MPVTDTRK_CR_DDR_THERM_CAMARILLO_STATUS_IMPH_HOT_THRESHOLD_STATUS_WID ( 1)
+  #define MPVTDTRK_CR_DDR_THERM_CAMARILLO_STATUS_IMPH_HOT_THRESHOLD_STATUS_MSK (0x00000004)
+  #define MPVTDTRK_CR_DDR_THERM_CAMARILLO_STATUS_IMPH_HOT_THRESHOLD_STATUS_MAX (0x00000001)
+  #define MPVTDTRK_CR_DDR_THERM_CAMARILLO_STATUS_IMPH_HOT_THRESHOLD_STATUS_DEF (0x00000000)
+  #define MPVTDTRK_CR_DDR_THERM_CAMARILLO_STATUS_IMPH_HOT_THRESHOLD_LOG_OFF ( 3)
+  #define MPVTDTRK_CR_DDR_THERM_CAMARILLO_STATUS_IMPH_HOT_THRESHOLD_LOG_WID ( 1)
+  #define MPVTDTRK_CR_DDR_THERM_CAMARILLO_STATUS_IMPH_HOT_THRESHOLD_LOG_MSK (0x00000008)
+  #define MPVTDTRK_CR_DDR_THERM_CAMARILLO_STATUS_IMPH_HOT_THRESHOLD_LOG_MAX (0x00000001)
+  #define MPVTDTRK_CR_DDR_THERM_CAMARILLO_STATUS_IMPH_HOT_THRESHOLD_LOG_DEF (0x00000000)
+  #define MPVTDTRK_CR_DDR_THERM_CAMARILLO_STATUS_IMPH_REFRESH2X_STATUS_OFF ( 4)
+  #define MPVTDTRK_CR_DDR_THERM_CAMARILLO_STATUS_IMPH_REFRESH2X_STATUS_WID ( 1)
+  #define MPVTDTRK_CR_DDR_THERM_CAMARILLO_STATUS_IMPH_REFRESH2X_STATUS_MSK (0x00000010)
+  #define MPVTDTRK_CR_DDR_THERM_CAMARILLO_STATUS_IMPH_REFRESH2X_STATUS_MAX (0x00000001)
+  #define MPVTDTRK_CR_DDR_THERM_CAMARILLO_STATUS_IMPH_REFRESH2X_STATUS_DEF (0x00000000)
+  #define MPVTDTRK_CR_DDR_THERM_CAMARILLO_STATUS_IMPH_REFRESH2X_LOG_OFF ( 5)
+  #define MPVTDTRK_CR_DDR_THERM_CAMARILLO_STATUS_IMPH_REFRESH2X_LOG_WID ( 1)
+  #define MPVTDTRK_CR_DDR_THERM_CAMARILLO_STATUS_IMPH_REFRESH2X_LOG_MSK (0x00000020)
+  #define MPVTDTRK_CR_DDR_THERM_CAMARILLO_STATUS_IMPH_REFRESH2X_LOG_MAX (0x00000001)
+  #define MPVTDTRK_CR_DDR_THERM_CAMARILLO_STATUS_IMPH_REFRESH2X_LOG_DEF (0x00000000)
+  #define MPVTDTRK_CR_DDR_THERM_CAMARILLO_STATUS_IMPH_FORCEMEMPR_STATUS_OFF ( 6)
+  #define MPVTDTRK_CR_DDR_THERM_CAMARILLO_STATUS_IMPH_FORCEMEMPR_STATUS_WID ( 1)
+  #define MPVTDTRK_CR_DDR_THERM_CAMARILLO_STATUS_IMPH_FORCEMEMPR_STATUS_MSK (0x00000040)
+  #define MPVTDTRK_CR_DDR_THERM_CAMARILLO_STATUS_IMPH_FORCEMEMPR_STATUS_MAX (0x00000001)
+  #define MPVTDTRK_CR_DDR_THERM_CAMARILLO_STATUS_IMPH_FORCEMEMPR_STATUS_DEF (0x00000000)
+  #define MPVTDTRK_CR_DDR_THERM_CAMARILLO_STATUS_IMPH_FORCEMEMPR_LOG_OFF ( 7)
+  #define MPVTDTRK_CR_DDR_THERM_CAMARILLO_STATUS_IMPH_FORCEMEMPR_LOG_WID ( 1)
+  #define MPVTDTRK_CR_DDR_THERM_CAMARILLO_STATUS_IMPH_FORCEMEMPR_LOG_MSK (0x00000080)
+  #define MPVTDTRK_CR_DDR_THERM_CAMARILLO_STATUS_IMPH_FORCEMEMPR_LOG_MAX (0x00000001)
+  #define MPVTDTRK_CR_DDR_THERM_CAMARILLO_STATUS_IMPH_FORCEMEMPR_LOG_DEF (0x00000000)
+  #define MPVTDTRK_CR_DDR_THERM_CAMARILLO_STATUS_IMPH_THRESHOLD1_STATUS_OFF ( 8)
+  #define MPVTDTRK_CR_DDR_THERM_CAMARILLO_STATUS_IMPH_THRESHOLD1_STATUS_WID ( 1)
+  #define MPVTDTRK_CR_DDR_THERM_CAMARILLO_STATUS_IMPH_THRESHOLD1_STATUS_MSK (0x00000100)
+  #define MPVTDTRK_CR_DDR_THERM_CAMARILLO_STATUS_IMPH_THRESHOLD1_STATUS_MAX (0x00000001)
+  #define MPVTDTRK_CR_DDR_THERM_CAMARILLO_STATUS_IMPH_THRESHOLD1_STATUS_DEF (0x00000000)
+  #define MPVTDTRK_CR_DDR_THERM_CAMARILLO_STATUS_IMPH_THRESHOLD1_LOG_OFF ( 9)
+  #define MPVTDTRK_CR_DDR_THERM_CAMARILLO_STATUS_IMPH_THRESHOLD1_LOG_WID ( 1)
+  #define MPVTDTRK_CR_DDR_THERM_CAMARILLO_STATUS_IMPH_THRESHOLD1_LOG_MSK (0x00000200)
+  #define MPVTDTRK_CR_DDR_THERM_CAMARILLO_STATUS_IMPH_THRESHOLD1_LOG_MAX (0x00000001)
+  #define MPVTDTRK_CR_DDR_THERM_CAMARILLO_STATUS_IMPH_THRESHOLD1_LOG_DEF (0x00000000)
+  #define MPVTDTRK_CR_DDR_THERM_CAMARILLO_STATUS_IMPH_THRESHOLD2_STATUS_OFF (10)
+  #define MPVTDTRK_CR_DDR_THERM_CAMARILLO_STATUS_IMPH_THRESHOLD2_STATUS_WID ( 1)
+  #define MPVTDTRK_CR_DDR_THERM_CAMARILLO_STATUS_IMPH_THRESHOLD2_STATUS_MSK (0x00000400)
+  #define MPVTDTRK_CR_DDR_THERM_CAMARILLO_STATUS_IMPH_THRESHOLD2_STATUS_MAX (0x00000001)
+  #define MPVTDTRK_CR_DDR_THERM_CAMARILLO_STATUS_IMPH_THRESHOLD2_STATUS_DEF (0x00000000)
+  #define MPVTDTRK_CR_DDR_THERM_CAMARILLO_STATUS_IMPH_THRESHOLD2_LOG_OFF (11)
+  #define MPVTDTRK_CR_DDR_THERM_CAMARILLO_STATUS_IMPH_THRESHOLD2_LOG_WID ( 1)
+  #define MPVTDTRK_CR_DDR_THERM_CAMARILLO_STATUS_IMPH_THRESHOLD2_LOG_MSK (0x00000800)
+  #define MPVTDTRK_CR_DDR_THERM_CAMARILLO_STATUS_IMPH_THRESHOLD2_LOG_MAX (0x00000001)
+  #define MPVTDTRK_CR_DDR_THERM_CAMARILLO_STATUS_IMPH_THRESHOLD2_LOG_DEF (0x00000000)
+
+#define MPVTDTRK_CR_VTDTRKLCK_IMPH_REG                               (0x000063FC)
+  #define MPVTDTRK_CR_VTDTRKLCK_IMPH_LOCK_OFF                          ( 0)
+  #define MPVTDTRK_CR_VTDTRKLCK_IMPH_LOCK_WID                          ( 1)
+  #define MPVTDTRK_CR_VTDTRKLCK_IMPH_LOCK_MSK                          (0x00000001)
+  #define MPVTDTRK_CR_VTDTRKLCK_IMPH_LOCK_MAX                          (0x00000001)
+  #define MPVTDTRK_CR_VTDTRKLCK_IMPH_LOCK_DEF                          (0x00000000)
+
+#define MPCBOTRK_CR_REQLIM_IMPH_REG                                  (0x00006800)
+  #define MPCBOTRK_CR_REQLIM_IMPH_RDLIM_OFF                            ( 0)
+  #define MPCBOTRK_CR_REQLIM_IMPH_RDLIM_WID                            ( 3)
+  #define MPCBOTRK_CR_REQLIM_IMPH_RDLIM_MSK                            (0x00000007)
+  #define MPCBOTRK_CR_REQLIM_IMPH_RDLIM_MAX                            (0x00000007)
+  #define MPCBOTRK_CR_REQLIM_IMPH_RDLIM_DEF                            (0x00000004)
+  #define MPCBOTRK_CR_REQLIM_IMPH_WRLIM_OFF                            ( 4)
+  #define MPCBOTRK_CR_REQLIM_IMPH_WRLIM_WID                            ( 3)
+  #define MPCBOTRK_CR_REQLIM_IMPH_WRLIM_MSK                            (0x00000070)
+  #define MPCBOTRK_CR_REQLIM_IMPH_WRLIM_MAX                            (0x00000007)
+  #define MPCBOTRK_CR_REQLIM_IMPH_WRLIM_DEF                            (0x00000004)
+  #define MPCBOTRK_CR_REQLIM_IMPH_LOCK_OFF                             (31)
+  #define MPCBOTRK_CR_REQLIM_IMPH_LOCK_WID                             ( 1)
+  #define MPCBOTRK_CR_REQLIM_IMPH_LOCK_MSK                             (0x80000000)
+  #define MPCBOTRK_CR_REQLIM_IMPH_LOCK_MAX                             (0x00000001)
+  #define MPCBOTRK_CR_REQLIM_IMPH_LOCK_DEF                             (0x00000000)
+
+#define HUBS_CR_DMIVCLIM_HUBS_REG                                    (0x00007000)
+  #define HUBS_CR_DMIVCLIM_HUBS_VCPNPLIM_OFF                           ( 0)
+  #define HUBS_CR_DMIVCLIM_HUBS_VCPNPLIM_WID                           ( 3)
+  #define HUBS_CR_DMIVCLIM_HUBS_VCPNPLIM_MSK                           (0x00000007)
+  #define HUBS_CR_DMIVCLIM_HUBS_VCPNPLIM_MAX                           (0x00000007)
+  #define HUBS_CR_DMIVCLIM_HUBS_VCPNPLIM_DEF                           (0x00000004)
+  #define HUBS_CR_DMIVCLIM_HUBS_VCPPLIM_OFF                            ( 4)
+  #define HUBS_CR_DMIVCLIM_HUBS_VCPPLIM_WID                            ( 3)
+  #define HUBS_CR_DMIVCLIM_HUBS_VCPPLIM_MSK                            (0x00000070)
+  #define HUBS_CR_DMIVCLIM_HUBS_VCPPLIM_MAX                            (0x00000007)
+  #define HUBS_CR_DMIVCLIM_HUBS_VCPPLIM_DEF                            (0x00000004)
+  #define HUBS_CR_DMIVCLIM_HUBS_VCMNPLIM_OFF                           ( 8)
+  #define HUBS_CR_DMIVCLIM_HUBS_VCMNPLIM_WID                           ( 3)
+  #define HUBS_CR_DMIVCLIM_HUBS_VCMNPLIM_MSK                           (0x00000700)
+  #define HUBS_CR_DMIVCLIM_HUBS_VCMNPLIM_MAX                           (0x00000007)
+  #define HUBS_CR_DMIVCLIM_HUBS_VCMNPLIM_DEF                           (0x00000004)
+  #define HUBS_CR_DMIVCLIM_HUBS_VCMPLIM_OFF                            (12)
+  #define HUBS_CR_DMIVCLIM_HUBS_VCMPLIM_WID                            ( 3)
+  #define HUBS_CR_DMIVCLIM_HUBS_VCMPLIM_MSK                            (0x00007000)
+  #define HUBS_CR_DMIVCLIM_HUBS_VCMPLIM_MAX                            (0x00000007)
+  #define HUBS_CR_DMIVCLIM_HUBS_VCMPLIM_DEF                            (0x00000004)
+  #define HUBS_CR_DMIVCLIM_HUBS_VCPCMPLIM_OFF                          (16)
+  #define HUBS_CR_DMIVCLIM_HUBS_VCPCMPLIM_WID                          ( 3)
+  #define HUBS_CR_DMIVCLIM_HUBS_VCPCMPLIM_MSK                          (0x00070000)
+  #define HUBS_CR_DMIVCLIM_HUBS_VCPCMPLIM_MAX                          (0x00000007)
+  #define HUBS_CR_DMIVCLIM_HUBS_VCPCMPLIM_DEF                          (0x00000004)
+  #define HUBS_CR_DMIVCLIM_HUBS_VCMCMPLIM_OFF                          (20)
+  #define HUBS_CR_DMIVCLIM_HUBS_VCMCMPLIM_WID                          ( 3)
+  #define HUBS_CR_DMIVCLIM_HUBS_VCMCMPLIM_MSK                          (0x00700000)
+  #define HUBS_CR_DMIVCLIM_HUBS_VCMCMPLIM_MAX                          (0x00000007)
+  #define HUBS_CR_DMIVCLIM_HUBS_VCMCMPLIM_DEF                          (0x00000004)
+  #define HUBS_CR_DMIVCLIM_HUBS_LOCK_OFF                               (31)
+  #define HUBS_CR_DMIVCLIM_HUBS_LOCK_WID                               ( 1)
+  #define HUBS_CR_DMIVCLIM_HUBS_LOCK_MSK                               (0x80000000)
+  #define HUBS_CR_DMIVCLIM_HUBS_LOCK_MAX                               (0x00000001)
+  #define HUBS_CR_DMIVCLIM_HUBS_LOCK_DEF                               (0x00000000)
+
+#define HUBS_CR_HUB0_PWRDN_OVRD_HUBS_REG                             (0x00007010)
+  #define HUBS_CR_HUB0_PWRDN_OVRD_HUBS_P0_OFF                          ( 0)
+  #define HUBS_CR_HUB0_PWRDN_OVRD_HUBS_P0_WID                          ( 1)
+  #define HUBS_CR_HUB0_PWRDN_OVRD_HUBS_P0_MSK                          (0x00000001)
+  #define HUBS_CR_HUB0_PWRDN_OVRD_HUBS_P0_MAX                          (0x00000001)
+  #define HUBS_CR_HUB0_PWRDN_OVRD_HUBS_P0_DEF                          (0x00000000)
+  #define HUBS_CR_HUB0_PWRDN_OVRD_HUBS_P1_OFF                          ( 1)
+  #define HUBS_CR_HUB0_PWRDN_OVRD_HUBS_P1_WID                          ( 1)
+  #define HUBS_CR_HUB0_PWRDN_OVRD_HUBS_P1_MSK                          (0x00000002)
+  #define HUBS_CR_HUB0_PWRDN_OVRD_HUBS_P1_MAX                          (0x00000001)
+  #define HUBS_CR_HUB0_PWRDN_OVRD_HUBS_P1_DEF                          (0x00000000)
+  #define HUBS_CR_HUB0_PWRDN_OVRD_HUBS_P2_OFF                          ( 2)
+  #define HUBS_CR_HUB0_PWRDN_OVRD_HUBS_P2_WID                          ( 1)
+  #define HUBS_CR_HUB0_PWRDN_OVRD_HUBS_P2_MSK                          (0x00000004)
+  #define HUBS_CR_HUB0_PWRDN_OVRD_HUBS_P2_MAX                          (0x00000001)
+  #define HUBS_CR_HUB0_PWRDN_OVRD_HUBS_P2_DEF                          (0x00000000)
+  #define HUBS_CR_HUB0_PWRDN_OVRD_HUBS_P3_OFF                          ( 3)
+  #define HUBS_CR_HUB0_PWRDN_OVRD_HUBS_P3_WID                          ( 1)
+  #define HUBS_CR_HUB0_PWRDN_OVRD_HUBS_P3_MSK                          (0x00000008)
+  #define HUBS_CR_HUB0_PWRDN_OVRD_HUBS_P3_MAX                          (0x00000001)
+  #define HUBS_CR_HUB0_PWRDN_OVRD_HUBS_P3_DEF                          (0x00000000)
+
+#define HUBS_CR_HUB1_PWRDN_OVRD_HUBS_REG                             (0x00007014)
+  #define HUBS_CR_HUB1_PWRDN_OVRD_HUBS_P0_OFF                          ( 0)
+  #define HUBS_CR_HUB1_PWRDN_OVRD_HUBS_P0_WID                          ( 1)
+  #define HUBS_CR_HUB1_PWRDN_OVRD_HUBS_P0_MSK                          (0x00000001)
+  #define HUBS_CR_HUB1_PWRDN_OVRD_HUBS_P0_MAX                          (0x00000001)
+  #define HUBS_CR_HUB1_PWRDN_OVRD_HUBS_P0_DEF                          (0x00000000)
+  #define HUBS_CR_HUB1_PWRDN_OVRD_HUBS_P1_OFF                          ( 1)
+  #define HUBS_CR_HUB1_PWRDN_OVRD_HUBS_P1_WID                          ( 1)
+  #define HUBS_CR_HUB1_PWRDN_OVRD_HUBS_P1_MSK                          (0x00000002)
+  #define HUBS_CR_HUB1_PWRDN_OVRD_HUBS_P1_MAX                          (0x00000001)
+  #define HUBS_CR_HUB1_PWRDN_OVRD_HUBS_P1_DEF                          (0x00000000)
+  #define HUBS_CR_HUB1_PWRDN_OVRD_HUBS_P2_OFF                          ( 2)
+  #define HUBS_CR_HUB1_PWRDN_OVRD_HUBS_P2_WID                          ( 1)
+  #define HUBS_CR_HUB1_PWRDN_OVRD_HUBS_P2_MSK                          (0x00000004)
+  #define HUBS_CR_HUB1_PWRDN_OVRD_HUBS_P2_MAX                          (0x00000001)
+  #define HUBS_CR_HUB1_PWRDN_OVRD_HUBS_P2_DEF                          (0x00000000)
+  #define HUBS_CR_HUB1_PWRDN_OVRD_HUBS_P3_OFF                          ( 3)
+  #define HUBS_CR_HUB1_PWRDN_OVRD_HUBS_P3_WID                          ( 1)
+  #define HUBS_CR_HUB1_PWRDN_OVRD_HUBS_P3_MSK                          (0x00000008)
+  #define HUBS_CR_HUB1_PWRDN_OVRD_HUBS_P3_MAX                          (0x00000001)
+  #define HUBS_CR_HUB1_PWRDN_OVRD_HUBS_P3_DEF                          (0x00000000)
+
+#define HUBS_CR_HUB2_PWRDN_OVRD_HUBS_REG                             (0x00007018)
+  #define HUBS_CR_HUB2_PWRDN_OVRD_HUBS_P0_OFF                          ( 0)
+  #define HUBS_CR_HUB2_PWRDN_OVRD_HUBS_P0_WID                          ( 1)
+  #define HUBS_CR_HUB2_PWRDN_OVRD_HUBS_P0_MSK                          (0x00000001)
+  #define HUBS_CR_HUB2_PWRDN_OVRD_HUBS_P0_MAX                          (0x00000001)
+  #define HUBS_CR_HUB2_PWRDN_OVRD_HUBS_P0_DEF                          (0x00000000)
+  #define HUBS_CR_HUB2_PWRDN_OVRD_HUBS_P1_OFF                          ( 1)
+  #define HUBS_CR_HUB2_PWRDN_OVRD_HUBS_P1_WID                          ( 1)
+  #define HUBS_CR_HUB2_PWRDN_OVRD_HUBS_P1_MSK                          (0x00000002)
+  #define HUBS_CR_HUB2_PWRDN_OVRD_HUBS_P1_MAX                          (0x00000001)
+  #define HUBS_CR_HUB2_PWRDN_OVRD_HUBS_P1_DEF                          (0x00000000)
+  #define HUBS_CR_HUB2_PWRDN_OVRD_HUBS_P2_OFF                          ( 2)
+  #define HUBS_CR_HUB2_PWRDN_OVRD_HUBS_P2_WID                          ( 1)
+  #define HUBS_CR_HUB2_PWRDN_OVRD_HUBS_P2_MSK                          (0x00000004)
+  #define HUBS_CR_HUB2_PWRDN_OVRD_HUBS_P2_MAX                          (0x00000001)
+  #define HUBS_CR_HUB2_PWRDN_OVRD_HUBS_P2_DEF                          (0x00000000)
+  #define HUBS_CR_HUB2_PWRDN_OVRD_HUBS_P3_OFF                          ( 3)
+  #define HUBS_CR_HUB2_PWRDN_OVRD_HUBS_P3_WID                          ( 1)
+  #define HUBS_CR_HUB2_PWRDN_OVRD_HUBS_P3_MSK                          (0x00000008)
+  #define HUBS_CR_HUB2_PWRDN_OVRD_HUBS_P3_MAX                          (0x00000001)
+  #define HUBS_CR_HUB2_PWRDN_OVRD_HUBS_P3_DEF                          (0x00000000)
+
+#define HUBS_CR_HUB0_DEFEATURE_HUBS_REG                              (0x0000701C)
+  #define HUBS_CR_HUB0_DEFEATURE_HUBS_BLK_GNT_P0_OFF                   ( 0)
+  #define HUBS_CR_HUB0_DEFEATURE_HUBS_BLK_GNT_P0_WID                   ( 1)
+  #define HUBS_CR_HUB0_DEFEATURE_HUBS_BLK_GNT_P0_MSK                   (0x00000001)
+  #define HUBS_CR_HUB0_DEFEATURE_HUBS_BLK_GNT_P0_MAX                   (0x00000001)
+  #define HUBS_CR_HUB0_DEFEATURE_HUBS_BLK_GNT_P0_DEF                   (0x00000000)
+  #define HUBS_CR_HUB0_DEFEATURE_HUBS_BLK_GNT_P1_OFF                   ( 1)
+  #define HUBS_CR_HUB0_DEFEATURE_HUBS_BLK_GNT_P1_WID                   ( 1)
+  #define HUBS_CR_HUB0_DEFEATURE_HUBS_BLK_GNT_P1_MSK                   (0x00000002)
+  #define HUBS_CR_HUB0_DEFEATURE_HUBS_BLK_GNT_P1_MAX                   (0x00000001)
+  #define HUBS_CR_HUB0_DEFEATURE_HUBS_BLK_GNT_P1_DEF                   (0x00000000)
+  #define HUBS_CR_HUB0_DEFEATURE_HUBS_BLK_GNT_P2_OFF                   ( 2)
+  #define HUBS_CR_HUB0_DEFEATURE_HUBS_BLK_GNT_P2_WID                   ( 1)
+  #define HUBS_CR_HUB0_DEFEATURE_HUBS_BLK_GNT_P2_MSK                   (0x00000004)
+  #define HUBS_CR_HUB0_DEFEATURE_HUBS_BLK_GNT_P2_MAX                   (0x00000001)
+  #define HUBS_CR_HUB0_DEFEATURE_HUBS_BLK_GNT_P2_DEF                   (0x00000000)
+  #define HUBS_CR_HUB0_DEFEATURE_HUBS_BLK_PUT_P0_OFF                   ( 3)
+  #define HUBS_CR_HUB0_DEFEATURE_HUBS_BLK_PUT_P0_WID                   ( 1)
+  #define HUBS_CR_HUB0_DEFEATURE_HUBS_BLK_PUT_P0_MSK                   (0x00000008)
+  #define HUBS_CR_HUB0_DEFEATURE_HUBS_BLK_PUT_P0_MAX                   (0x00000001)
+  #define HUBS_CR_HUB0_DEFEATURE_HUBS_BLK_PUT_P0_DEF                   (0x00000000)
+  #define HUBS_CR_HUB0_DEFEATURE_HUBS_BLK_PUT_P1_OFF                   ( 4)
+  #define HUBS_CR_HUB0_DEFEATURE_HUBS_BLK_PUT_P1_WID                   ( 1)
+  #define HUBS_CR_HUB0_DEFEATURE_HUBS_BLK_PUT_P1_MSK                   (0x00000010)
+  #define HUBS_CR_HUB0_DEFEATURE_HUBS_BLK_PUT_P1_MAX                   (0x00000001)
+  #define HUBS_CR_HUB0_DEFEATURE_HUBS_BLK_PUT_P1_DEF                   (0x00000000)
+  #define HUBS_CR_HUB0_DEFEATURE_HUBS_BLK_PUT_P2_OFF                   ( 5)
+  #define HUBS_CR_HUB0_DEFEATURE_HUBS_BLK_PUT_P2_WID                   ( 1)
+  #define HUBS_CR_HUB0_DEFEATURE_HUBS_BLK_PUT_P2_MSK                   (0x00000020)
+  #define HUBS_CR_HUB0_DEFEATURE_HUBS_BLK_PUT_P2_MAX                   (0x00000001)
+  #define HUBS_CR_HUB0_DEFEATURE_HUBS_BLK_PUT_P2_DEF                   (0x00000000)
+  #define HUBS_CR_HUB0_DEFEATURE_HUBS_BLK_PUT_P3_OFF                   ( 6)
+  #define HUBS_CR_HUB0_DEFEATURE_HUBS_BLK_PUT_P3_WID                   ( 1)
+  #define HUBS_CR_HUB0_DEFEATURE_HUBS_BLK_PUT_P3_MSK                   (0x00000040)
+  #define HUBS_CR_HUB0_DEFEATURE_HUBS_BLK_PUT_P3_MAX                   (0x00000001)
+  #define HUBS_CR_HUB0_DEFEATURE_HUBS_BLK_PUT_P3_DEF                   (0x00000000)
+  #define HUBS_CR_HUB0_DEFEATURE_HUBS_NO_CHAIN_P0_OFF                  ( 7)
+  #define HUBS_CR_HUB0_DEFEATURE_HUBS_NO_CHAIN_P0_WID                  ( 1)
+  #define HUBS_CR_HUB0_DEFEATURE_HUBS_NO_CHAIN_P0_MSK                  (0x00000080)
+  #define HUBS_CR_HUB0_DEFEATURE_HUBS_NO_CHAIN_P0_MAX                  (0x00000001)
+  #define HUBS_CR_HUB0_DEFEATURE_HUBS_NO_CHAIN_P0_DEF                  (0x00000000)
+  #define HUBS_CR_HUB0_DEFEATURE_HUBS_NO_CHAIN_P1_OFF                  ( 8)
+  #define HUBS_CR_HUB0_DEFEATURE_HUBS_NO_CHAIN_P1_WID                  ( 1)
+  #define HUBS_CR_HUB0_DEFEATURE_HUBS_NO_CHAIN_P1_MSK                  (0x00000100)
+  #define HUBS_CR_HUB0_DEFEATURE_HUBS_NO_CHAIN_P1_MAX                  (0x00000001)
+  #define HUBS_CR_HUB0_DEFEATURE_HUBS_NO_CHAIN_P1_DEF                  (0x00000000)
+  #define HUBS_CR_HUB0_DEFEATURE_HUBS_NO_CHAIN_P2_OFF                  ( 9)
+  #define HUBS_CR_HUB0_DEFEATURE_HUBS_NO_CHAIN_P2_WID                  ( 1)
+  #define HUBS_CR_HUB0_DEFEATURE_HUBS_NO_CHAIN_P2_MSK                  (0x00000200)
+  #define HUBS_CR_HUB0_DEFEATURE_HUBS_NO_CHAIN_P2_MAX                  (0x00000001)
+  #define HUBS_CR_HUB0_DEFEATURE_HUBS_NO_CHAIN_P2_DEF                  (0x00000000)
+  #define HUBS_CR_HUB0_DEFEATURE_HUBS_SLOW_UP_P0_OFF                   (10)
+  #define HUBS_CR_HUB0_DEFEATURE_HUBS_SLOW_UP_P0_WID                   ( 1)
+  #define HUBS_CR_HUB0_DEFEATURE_HUBS_SLOW_UP_P0_MSK                   (0x00000400)
+  #define HUBS_CR_HUB0_DEFEATURE_HUBS_SLOW_UP_P0_MAX                   (0x00000001)
+  #define HUBS_CR_HUB0_DEFEATURE_HUBS_SLOW_UP_P0_DEF                   (0x00000000)
+  #define HUBS_CR_HUB0_DEFEATURE_HUBS_SLOW_UP_P1_OFF                   (11)
+  #define HUBS_CR_HUB0_DEFEATURE_HUBS_SLOW_UP_P1_WID                   ( 1)
+  #define HUBS_CR_HUB0_DEFEATURE_HUBS_SLOW_UP_P1_MSK                   (0x00000800)
+  #define HUBS_CR_HUB0_DEFEATURE_HUBS_SLOW_UP_P1_MAX                   (0x00000001)
+  #define HUBS_CR_HUB0_DEFEATURE_HUBS_SLOW_UP_P1_DEF                   (0x00000000)
+  #define HUBS_CR_HUB0_DEFEATURE_HUBS_SLOW_UP_P2_OFF                   (12)
+  #define HUBS_CR_HUB0_DEFEATURE_HUBS_SLOW_UP_P2_WID                   ( 1)
+  #define HUBS_CR_HUB0_DEFEATURE_HUBS_SLOW_UP_P2_MSK                   (0x00001000)
+  #define HUBS_CR_HUB0_DEFEATURE_HUBS_SLOW_UP_P2_MAX                   (0x00000001)
+  #define HUBS_CR_HUB0_DEFEATURE_HUBS_SLOW_UP_P2_DEF                   (0x00000000)
+  #define HUBS_CR_HUB0_DEFEATURE_HUBS_SLOW_DN_P0_OFF                   (13)
+  #define HUBS_CR_HUB0_DEFEATURE_HUBS_SLOW_DN_P0_WID                   ( 1)
+  #define HUBS_CR_HUB0_DEFEATURE_HUBS_SLOW_DN_P0_MSK                   (0x00002000)
+  #define HUBS_CR_HUB0_DEFEATURE_HUBS_SLOW_DN_P0_MAX                   (0x00000001)
+  #define HUBS_CR_HUB0_DEFEATURE_HUBS_SLOW_DN_P0_DEF                   (0x00000000)
+  #define HUBS_CR_HUB0_DEFEATURE_HUBS_SLOW_DN_P1_OFF                   (14)
+  #define HUBS_CR_HUB0_DEFEATURE_HUBS_SLOW_DN_P1_WID                   ( 1)
+  #define HUBS_CR_HUB0_DEFEATURE_HUBS_SLOW_DN_P1_MSK                   (0x00004000)
+  #define HUBS_CR_HUB0_DEFEATURE_HUBS_SLOW_DN_P1_MAX                   (0x00000001)
+  #define HUBS_CR_HUB0_DEFEATURE_HUBS_SLOW_DN_P1_DEF                   (0x00000000)
+  #define HUBS_CR_HUB0_DEFEATURE_HUBS_SLOW_DN_P2_OFF                   (15)
+  #define HUBS_CR_HUB0_DEFEATURE_HUBS_SLOW_DN_P2_WID                   ( 1)
+  #define HUBS_CR_HUB0_DEFEATURE_HUBS_SLOW_DN_P2_MSK                   (0x00008000)
+  #define HUBS_CR_HUB0_DEFEATURE_HUBS_SLOW_DN_P2_MAX                   (0x00000001)
+  #define HUBS_CR_HUB0_DEFEATURE_HUBS_SLOW_DN_P2_DEF                   (0x00000000)
+  #define HUBS_CR_HUB0_DEFEATURE_HUBS_SLOW_DN_P3_OFF                   (16)
+  #define HUBS_CR_HUB0_DEFEATURE_HUBS_SLOW_DN_P3_WID                   ( 1)
+  #define HUBS_CR_HUB0_DEFEATURE_HUBS_SLOW_DN_P3_MSK                   (0x00010000)
+  #define HUBS_CR_HUB0_DEFEATURE_HUBS_SLOW_DN_P3_MAX                   (0x00000001)
+  #define HUBS_CR_HUB0_DEFEATURE_HUBS_SLOW_DN_P3_DEF                   (0x00000000)
+  #define HUBS_CR_HUB0_DEFEATURE_HUBS_SLOWER_CMD_OFF                   (17)
+  #define HUBS_CR_HUB0_DEFEATURE_HUBS_SLOWER_CMD_WID                   ( 1)
+  #define HUBS_CR_HUB0_DEFEATURE_HUBS_SLOWER_CMD_MSK                   (0x00020000)
+  #define HUBS_CR_HUB0_DEFEATURE_HUBS_SLOWER_CMD_MAX                   (0x00000001)
+  #define HUBS_CR_HUB0_DEFEATURE_HUBS_SLOWER_CMD_DEF                   (0x00000000)
+  #define HUBS_CR_HUB0_DEFEATURE_HUBS_DMI_NOPUSH_OFF                   (18)
+  #define HUBS_CR_HUB0_DEFEATURE_HUBS_DMI_NOPUSH_WID                   ( 1)
+  #define HUBS_CR_HUB0_DEFEATURE_HUBS_DMI_NOPUSH_MSK                   (0x00040000)
+  #define HUBS_CR_HUB0_DEFEATURE_HUBS_DMI_NOPUSH_MAX                   (0x00000001)
+  #define HUBS_CR_HUB0_DEFEATURE_HUBS_DMI_NOPUSH_DEF                   (0x00000000)
+  #define HUBS_CR_HUB0_DEFEATURE_HUBS_RO_PASS_NP_OFF                   (19)
+  #define HUBS_CR_HUB0_DEFEATURE_HUBS_RO_PASS_NP_WID                   ( 1)
+  #define HUBS_CR_HUB0_DEFEATURE_HUBS_RO_PASS_NP_MSK                   (0x00080000)
+  #define HUBS_CR_HUB0_DEFEATURE_HUBS_RO_PASS_NP_MAX                   (0x00000001)
+  #define HUBS_CR_HUB0_DEFEATURE_HUBS_RO_PASS_NP_DEF                   (0x00000000)
+  #define HUBS_CR_HUB0_DEFEATURE_HUBS_RST_CRD_P3_OFF                   (20)
+  #define HUBS_CR_HUB0_DEFEATURE_HUBS_RST_CRD_P3_WID                   ( 1)
+  #define HUBS_CR_HUB0_DEFEATURE_HUBS_RST_CRD_P3_MSK                   (0x00100000)
+  #define HUBS_CR_HUB0_DEFEATURE_HUBS_RST_CRD_P3_MAX                   (0x00000001)
+  #define HUBS_CR_HUB0_DEFEATURE_HUBS_RST_CRD_P3_DEF                   (0x00000000)
+
+#define HUBS_CR_HUB1_DEFEATURE_HUBS_REG                              (0x00007020)
+  #define HUBS_CR_HUB1_DEFEATURE_HUBS_BLK_GNT_P1_OFF                   ( 0)
+  #define HUBS_CR_HUB1_DEFEATURE_HUBS_BLK_GNT_P1_WID                   ( 1)
+  #define HUBS_CR_HUB1_DEFEATURE_HUBS_BLK_GNT_P1_MSK                   (0x00000001)
+  #define HUBS_CR_HUB1_DEFEATURE_HUBS_BLK_GNT_P1_MAX                   (0x00000001)
+  #define HUBS_CR_HUB1_DEFEATURE_HUBS_BLK_GNT_P1_DEF                   (0x00000000)
+  #define HUBS_CR_HUB1_DEFEATURE_HUBS_BLK_GNT_P2_OFF                   ( 1)
+  #define HUBS_CR_HUB1_DEFEATURE_HUBS_BLK_GNT_P2_WID                   ( 1)
+  #define HUBS_CR_HUB1_DEFEATURE_HUBS_BLK_GNT_P2_MSK                   (0x00000002)
+  #define HUBS_CR_HUB1_DEFEATURE_HUBS_BLK_GNT_P2_MAX                   (0x00000001)
+  #define HUBS_CR_HUB1_DEFEATURE_HUBS_BLK_GNT_P2_DEF                   (0x00000000)
+  #define HUBS_CR_HUB1_DEFEATURE_HUBS_BLK_PUT_P0_OFF                   ( 2)
+  #define HUBS_CR_HUB1_DEFEATURE_HUBS_BLK_PUT_P0_WID                   ( 1)
+  #define HUBS_CR_HUB1_DEFEATURE_HUBS_BLK_PUT_P0_MSK                   (0x00000004)
+  #define HUBS_CR_HUB1_DEFEATURE_HUBS_BLK_PUT_P0_MAX                   (0x00000001)
+  #define HUBS_CR_HUB1_DEFEATURE_HUBS_BLK_PUT_P0_DEF                   (0x00000000)
+  #define HUBS_CR_HUB1_DEFEATURE_HUBS_BLK_PUT_P1_OFF                   ( 3)
+  #define HUBS_CR_HUB1_DEFEATURE_HUBS_BLK_PUT_P1_WID                   ( 1)
+  #define HUBS_CR_HUB1_DEFEATURE_HUBS_BLK_PUT_P1_MSK                   (0x00000008)
+  #define HUBS_CR_HUB1_DEFEATURE_HUBS_BLK_PUT_P1_MAX                   (0x00000001)
+  #define HUBS_CR_HUB1_DEFEATURE_HUBS_BLK_PUT_P1_DEF                   (0x00000000)
+  #define HUBS_CR_HUB1_DEFEATURE_HUBS_BLK_PUT_P2_OFF                   ( 4)
+  #define HUBS_CR_HUB1_DEFEATURE_HUBS_BLK_PUT_P2_WID                   ( 1)
+  #define HUBS_CR_HUB1_DEFEATURE_HUBS_BLK_PUT_P2_MSK                   (0x00000010)
+  #define HUBS_CR_HUB1_DEFEATURE_HUBS_BLK_PUT_P2_MAX                   (0x00000001)
+  #define HUBS_CR_HUB1_DEFEATURE_HUBS_BLK_PUT_P2_DEF                   (0x00000000)
+  #define HUBS_CR_HUB1_DEFEATURE_HUBS_BLK_PUT_P3_OFF                   ( 5)
+  #define HUBS_CR_HUB1_DEFEATURE_HUBS_BLK_PUT_P3_WID                   ( 1)
+  #define HUBS_CR_HUB1_DEFEATURE_HUBS_BLK_PUT_P3_MSK                   (0x00000020)
+  #define HUBS_CR_HUB1_DEFEATURE_HUBS_BLK_PUT_P3_MAX                   (0x00000001)
+  #define HUBS_CR_HUB1_DEFEATURE_HUBS_BLK_PUT_P3_DEF                   (0x00000000)
+  #define HUBS_CR_HUB1_DEFEATURE_HUBS_NO_CHAIN_P1_OFF                  ( 6)
+  #define HUBS_CR_HUB1_DEFEATURE_HUBS_NO_CHAIN_P1_WID                  ( 1)
+  #define HUBS_CR_HUB1_DEFEATURE_HUBS_NO_CHAIN_P1_MSK                  (0x00000040)
+  #define HUBS_CR_HUB1_DEFEATURE_HUBS_NO_CHAIN_P1_MAX                  (0x00000001)
+  #define HUBS_CR_HUB1_DEFEATURE_HUBS_NO_CHAIN_P1_DEF                  (0x00000000)
+  #define HUBS_CR_HUB1_DEFEATURE_HUBS_NO_CHAIN_P2_OFF                  ( 7)
+  #define HUBS_CR_HUB1_DEFEATURE_HUBS_NO_CHAIN_P2_WID                  ( 1)
+  #define HUBS_CR_HUB1_DEFEATURE_HUBS_NO_CHAIN_P2_MSK                  (0x00000080)
+  #define HUBS_CR_HUB1_DEFEATURE_HUBS_NO_CHAIN_P2_MAX                  (0x00000001)
+  #define HUBS_CR_HUB1_DEFEATURE_HUBS_NO_CHAIN_P2_DEF                  (0x00000000)
+  #define HUBS_CR_HUB1_DEFEATURE_HUBS_SLOW_UP_P0_OFF                   ( 8)
+  #define HUBS_CR_HUB1_DEFEATURE_HUBS_SLOW_UP_P0_WID                   ( 1)
+  #define HUBS_CR_HUB1_DEFEATURE_HUBS_SLOW_UP_P0_MSK                   (0x00000100)
+  #define HUBS_CR_HUB1_DEFEATURE_HUBS_SLOW_UP_P0_MAX                   (0x00000001)
+  #define HUBS_CR_HUB1_DEFEATURE_HUBS_SLOW_UP_P0_DEF                   (0x00000000)
+  #define HUBS_CR_HUB1_DEFEATURE_HUBS_SLOW_UP_P1_OFF                   ( 9)
+  #define HUBS_CR_HUB1_DEFEATURE_HUBS_SLOW_UP_P1_WID                   ( 1)
+  #define HUBS_CR_HUB1_DEFEATURE_HUBS_SLOW_UP_P1_MSK                   (0x00000200)
+  #define HUBS_CR_HUB1_DEFEATURE_HUBS_SLOW_UP_P1_MAX                   (0x00000001)
+  #define HUBS_CR_HUB1_DEFEATURE_HUBS_SLOW_UP_P1_DEF                   (0x00000000)
+  #define HUBS_CR_HUB1_DEFEATURE_HUBS_SLOW_UP_P2_OFF                   (10)
+  #define HUBS_CR_HUB1_DEFEATURE_HUBS_SLOW_UP_P2_WID                   ( 1)
+  #define HUBS_CR_HUB1_DEFEATURE_HUBS_SLOW_UP_P2_MSK                   (0x00000400)
+  #define HUBS_CR_HUB1_DEFEATURE_HUBS_SLOW_UP_P2_MAX                   (0x00000001)
+  #define HUBS_CR_HUB1_DEFEATURE_HUBS_SLOW_UP_P2_DEF                   (0x00000000)
+  #define HUBS_CR_HUB1_DEFEATURE_HUBS_SLOW_DN_P1_OFF                   (11)
+  #define HUBS_CR_HUB1_DEFEATURE_HUBS_SLOW_DN_P1_WID                   ( 1)
+  #define HUBS_CR_HUB1_DEFEATURE_HUBS_SLOW_DN_P1_MSK                   (0x00000800)
+  #define HUBS_CR_HUB1_DEFEATURE_HUBS_SLOW_DN_P1_MAX                   (0x00000001)
+  #define HUBS_CR_HUB1_DEFEATURE_HUBS_SLOW_DN_P1_DEF                   (0x00000000)
+  #define HUBS_CR_HUB1_DEFEATURE_HUBS_SLOW_DN_P2_OFF                   (12)
+  #define HUBS_CR_HUB1_DEFEATURE_HUBS_SLOW_DN_P2_WID                   ( 1)
+  #define HUBS_CR_HUB1_DEFEATURE_HUBS_SLOW_DN_P2_MSK                   (0x00001000)
+  #define HUBS_CR_HUB1_DEFEATURE_HUBS_SLOW_DN_P2_MAX                   (0x00000001)
+  #define HUBS_CR_HUB1_DEFEATURE_HUBS_SLOW_DN_P2_DEF                   (0x00000000)
+  #define HUBS_CR_HUB1_DEFEATURE_HUBS_SLOW_DN_P3_OFF                   (13)
+  #define HUBS_CR_HUB1_DEFEATURE_HUBS_SLOW_DN_P3_WID                   ( 1)
+  #define HUBS_CR_HUB1_DEFEATURE_HUBS_SLOW_DN_P3_MSK                   (0x00002000)
+  #define HUBS_CR_HUB1_DEFEATURE_HUBS_SLOW_DN_P3_MAX                   (0x00000001)
+  #define HUBS_CR_HUB1_DEFEATURE_HUBS_SLOW_DN_P3_DEF                   (0x00000000)
+  #define HUBS_CR_HUB1_DEFEATURE_HUBS_SLOWER_CMD_OFF                   (14)
+  #define HUBS_CR_HUB1_DEFEATURE_HUBS_SLOWER_CMD_WID                   ( 1)
+  #define HUBS_CR_HUB1_DEFEATURE_HUBS_SLOWER_CMD_MSK                   (0x00004000)
+  #define HUBS_CR_HUB1_DEFEATURE_HUBS_SLOWER_CMD_MAX                   (0x00000001)
+  #define HUBS_CR_HUB1_DEFEATURE_HUBS_SLOWER_CMD_DEF                   (0x00000000)
+  #define HUBS_CR_HUB1_DEFEATURE_HUBS_RO_PASS_NP_OFF                   (15)
+  #define HUBS_CR_HUB1_DEFEATURE_HUBS_RO_PASS_NP_WID                   ( 1)
+  #define HUBS_CR_HUB1_DEFEATURE_HUBS_RO_PASS_NP_MSK                   (0x00008000)
+  #define HUBS_CR_HUB1_DEFEATURE_HUBS_RO_PASS_NP_MAX                   (0x00000001)
+  #define HUBS_CR_HUB1_DEFEATURE_HUBS_RO_PASS_NP_DEF                   (0x00000000)
+  #define HUBS_CR_HUB1_DEFEATURE_HUBS_RST_CRD_P0_OFF                   (16)
+  #define HUBS_CR_HUB1_DEFEATURE_HUBS_RST_CRD_P0_WID                   ( 1)
+  #define HUBS_CR_HUB1_DEFEATURE_HUBS_RST_CRD_P0_MSK                   (0x00010000)
+  #define HUBS_CR_HUB1_DEFEATURE_HUBS_RST_CRD_P0_MAX                   (0x00000001)
+  #define HUBS_CR_HUB1_DEFEATURE_HUBS_RST_CRD_P0_DEF                   (0x00000000)
+  #define HUBS_CR_HUB1_DEFEATURE_HUBS_RST_CRD_P3_OFF                   (17)
+  #define HUBS_CR_HUB1_DEFEATURE_HUBS_RST_CRD_P3_WID                   ( 1)
+  #define HUBS_CR_HUB1_DEFEATURE_HUBS_RST_CRD_P3_MSK                   (0x00020000)
+  #define HUBS_CR_HUB1_DEFEATURE_HUBS_RST_CRD_P3_MAX                   (0x00000001)
+  #define HUBS_CR_HUB1_DEFEATURE_HUBS_RST_CRD_P3_DEF                   (0x00000000)
+
+#define HUBS_CR_HUB2_DEFEATURE_HUBS_REG                              (0x00007024)
+  #define HUBS_CR_HUB2_DEFEATURE_HUBS_BLK_GNT_P1_OFF                   ( 0)
+  #define HUBS_CR_HUB2_DEFEATURE_HUBS_BLK_GNT_P1_WID                   ( 1)
+  #define HUBS_CR_HUB2_DEFEATURE_HUBS_BLK_GNT_P1_MSK                   (0x00000001)
+  #define HUBS_CR_HUB2_DEFEATURE_HUBS_BLK_GNT_P1_MAX                   (0x00000001)
+  #define HUBS_CR_HUB2_DEFEATURE_HUBS_BLK_GNT_P1_DEF                   (0x00000000)
+  #define HUBS_CR_HUB2_DEFEATURE_HUBS_BLK_GNT_P2_OFF                   ( 1)
+  #define HUBS_CR_HUB2_DEFEATURE_HUBS_BLK_GNT_P2_WID                   ( 1)
+  #define HUBS_CR_HUB2_DEFEATURE_HUBS_BLK_GNT_P2_MSK                   (0x00000002)
+  #define HUBS_CR_HUB2_DEFEATURE_HUBS_BLK_GNT_P2_MAX                   (0x00000001)
+  #define HUBS_CR_HUB2_DEFEATURE_HUBS_BLK_GNT_P2_DEF                   (0x00000000)
+  #define HUBS_CR_HUB2_DEFEATURE_HUBS_BLK_PUT_P0_OFF                   ( 2)
+  #define HUBS_CR_HUB2_DEFEATURE_HUBS_BLK_PUT_P0_WID                   ( 1)
+  #define HUBS_CR_HUB2_DEFEATURE_HUBS_BLK_PUT_P0_MSK                   (0x00000004)
+  #define HUBS_CR_HUB2_DEFEATURE_HUBS_BLK_PUT_P0_MAX                   (0x00000001)
+  #define HUBS_CR_HUB2_DEFEATURE_HUBS_BLK_PUT_P0_DEF                   (0x00000000)
+  #define HUBS_CR_HUB2_DEFEATURE_HUBS_BLK_PUT_P1_OFF                   ( 3)
+  #define HUBS_CR_HUB2_DEFEATURE_HUBS_BLK_PUT_P1_WID                   ( 1)
+  #define HUBS_CR_HUB2_DEFEATURE_HUBS_BLK_PUT_P1_MSK                   (0x00000008)
+  #define HUBS_CR_HUB2_DEFEATURE_HUBS_BLK_PUT_P1_MAX                   (0x00000001)
+  #define HUBS_CR_HUB2_DEFEATURE_HUBS_BLK_PUT_P1_DEF                   (0x00000000)
+  #define HUBS_CR_HUB2_DEFEATURE_HUBS_BLK_PUT_P2_OFF                   ( 4)
+  #define HUBS_CR_HUB2_DEFEATURE_HUBS_BLK_PUT_P2_WID                   ( 1)
+  #define HUBS_CR_HUB2_DEFEATURE_HUBS_BLK_PUT_P2_MSK                   (0x00000010)
+  #define HUBS_CR_HUB2_DEFEATURE_HUBS_BLK_PUT_P2_MAX                   (0x00000001)
+  #define HUBS_CR_HUB2_DEFEATURE_HUBS_BLK_PUT_P2_DEF                   (0x00000000)
+  #define HUBS_CR_HUB2_DEFEATURE_HUBS_NO_CHAIN_P1_OFF                  ( 5)
+  #define HUBS_CR_HUB2_DEFEATURE_HUBS_NO_CHAIN_P1_WID                  ( 1)
+  #define HUBS_CR_HUB2_DEFEATURE_HUBS_NO_CHAIN_P1_MSK                  (0x00000020)
+  #define HUBS_CR_HUB2_DEFEATURE_HUBS_NO_CHAIN_P1_MAX                  (0x00000001)
+  #define HUBS_CR_HUB2_DEFEATURE_HUBS_NO_CHAIN_P1_DEF                  (0x00000000)
+  #define HUBS_CR_HUB2_DEFEATURE_HUBS_NO_CHAIN_P2_OFF                  ( 6)
+  #define HUBS_CR_HUB2_DEFEATURE_HUBS_NO_CHAIN_P2_WID                  ( 1)
+  #define HUBS_CR_HUB2_DEFEATURE_HUBS_NO_CHAIN_P2_MSK                  (0x00000040)
+  #define HUBS_CR_HUB2_DEFEATURE_HUBS_NO_CHAIN_P2_MAX                  (0x00000001)
+  #define HUBS_CR_HUB2_DEFEATURE_HUBS_NO_CHAIN_P2_DEF                  (0x00000000)
+  #define HUBS_CR_HUB2_DEFEATURE_HUBS_SLOW_UP_P0_OFF                   ( 7)
+  #define HUBS_CR_HUB2_DEFEATURE_HUBS_SLOW_UP_P0_WID                   ( 1)
+  #define HUBS_CR_HUB2_DEFEATURE_HUBS_SLOW_UP_P0_MSK                   (0x00000080)
+  #define HUBS_CR_HUB2_DEFEATURE_HUBS_SLOW_UP_P0_MAX                   (0x00000001)
+  #define HUBS_CR_HUB2_DEFEATURE_HUBS_SLOW_UP_P0_DEF                   (0x00000000)
+  #define HUBS_CR_HUB2_DEFEATURE_HUBS_SLOW_UP_P1_OFF                   ( 8)
+  #define HUBS_CR_HUB2_DEFEATURE_HUBS_SLOW_UP_P1_WID                   ( 1)
+  #define HUBS_CR_HUB2_DEFEATURE_HUBS_SLOW_UP_P1_MSK                   (0x00000100)
+  #define HUBS_CR_HUB2_DEFEATURE_HUBS_SLOW_UP_P1_MAX                   (0x00000001)
+  #define HUBS_CR_HUB2_DEFEATURE_HUBS_SLOW_UP_P1_DEF                   (0x00000000)
+  #define HUBS_CR_HUB2_DEFEATURE_HUBS_SLOW_UP_P2_OFF                   ( 9)
+  #define HUBS_CR_HUB2_DEFEATURE_HUBS_SLOW_UP_P2_WID                   ( 1)
+  #define HUBS_CR_HUB2_DEFEATURE_HUBS_SLOW_UP_P2_MSK                   (0x00000200)
+  #define HUBS_CR_HUB2_DEFEATURE_HUBS_SLOW_UP_P2_MAX                   (0x00000001)
+  #define HUBS_CR_HUB2_DEFEATURE_HUBS_SLOW_UP_P2_DEF                   (0x00000000)
+  #define HUBS_CR_HUB2_DEFEATURE_HUBS_SLOW_DN_P1_OFF                   (10)
+  #define HUBS_CR_HUB2_DEFEATURE_HUBS_SLOW_DN_P1_WID                   ( 1)
+  #define HUBS_CR_HUB2_DEFEATURE_HUBS_SLOW_DN_P1_MSK                   (0x00000400)
+  #define HUBS_CR_HUB2_DEFEATURE_HUBS_SLOW_DN_P1_MAX                   (0x00000001)
+  #define HUBS_CR_HUB2_DEFEATURE_HUBS_SLOW_DN_P1_DEF                   (0x00000000)
+  #define HUBS_CR_HUB2_DEFEATURE_HUBS_SLOW_DN_P2_OFF                   (11)
+  #define HUBS_CR_HUB2_DEFEATURE_HUBS_SLOW_DN_P2_WID                   ( 1)
+  #define HUBS_CR_HUB2_DEFEATURE_HUBS_SLOW_DN_P2_MSK                   (0x00000800)
+  #define HUBS_CR_HUB2_DEFEATURE_HUBS_SLOW_DN_P2_MAX                   (0x00000001)
+  #define HUBS_CR_HUB2_DEFEATURE_HUBS_SLOW_DN_P2_DEF                   (0x00000000)
+  #define HUBS_CR_HUB2_DEFEATURE_HUBS_SLOWER_CMD_OFF                   (12)
+  #define HUBS_CR_HUB2_DEFEATURE_HUBS_SLOWER_CMD_WID                   ( 1)
+  #define HUBS_CR_HUB2_DEFEATURE_HUBS_SLOWER_CMD_MSK                   (0x00001000)
+  #define HUBS_CR_HUB2_DEFEATURE_HUBS_SLOWER_CMD_MAX                   (0x00000001)
+  #define HUBS_CR_HUB2_DEFEATURE_HUBS_SLOWER_CMD_DEF                   (0x00000000)
+  #define HUBS_CR_HUB2_DEFEATURE_HUBS_RST_CRD_P0_OFF                   (13)
+  #define HUBS_CR_HUB2_DEFEATURE_HUBS_RST_CRD_P0_WID                   ( 1)
+  #define HUBS_CR_HUB2_DEFEATURE_HUBS_RST_CRD_P0_MSK                   (0x00002000)
+  #define HUBS_CR_HUB2_DEFEATURE_HUBS_RST_CRD_P0_MAX                   (0x00000001)
+  #define HUBS_CR_HUB2_DEFEATURE_HUBS_RST_CRD_P0_DEF                   (0x00000000)
+
+#define HUBS_CR_PEGCTL_HUBS_REG                                      (0x00007028)
+  #define HUBS_CR_PEGCTL_HUBS_PCIPWRGAT_OFF                            ( 0)
+  #define HUBS_CR_PEGCTL_HUBS_PCIPWRGAT_WID                            ( 1)
+  #define HUBS_CR_PEGCTL_HUBS_PCIPWRGAT_MSK                            (0x00000001)
+  #define HUBS_CR_PEGCTL_HUBS_PCIPWRGAT_MAX                            (0x00000001)
+  #define HUBS_CR_PEGCTL_HUBS_PCIPWRGAT_DEF                            (0x00000000)
+
+#define HUBS_CR_HUB_EMPTY_HUBS_REG                                   (0x0000702C)
+  #define HUBS_CR_HUB_EMPTY_HUBS_H0_EMPTY_OFF                          ( 0)
+  #define HUBS_CR_HUB_EMPTY_HUBS_H0_EMPTY_WID                          ( 1)
+  #define HUBS_CR_HUB_EMPTY_HUBS_H0_EMPTY_MSK                          (0x00000001)
+  #define HUBS_CR_HUB_EMPTY_HUBS_H0_EMPTY_MAX                          (0x00000001)
+  #define HUBS_CR_HUB_EMPTY_HUBS_H0_EMPTY_DEF                          (0x00000001)
+  #define HUBS_CR_HUB_EMPTY_HUBS_H1_EMPTY_OFF                          ( 1)
+  #define HUBS_CR_HUB_EMPTY_HUBS_H1_EMPTY_WID                          ( 1)
+  #define HUBS_CR_HUB_EMPTY_HUBS_H1_EMPTY_MSK                          (0x00000002)
+  #define HUBS_CR_HUB_EMPTY_HUBS_H1_EMPTY_MAX                          (0x00000001)
+  #define HUBS_CR_HUB_EMPTY_HUBS_H1_EMPTY_DEF                          (0x00000001)
+  #define HUBS_CR_HUB_EMPTY_HUBS_H2_EMPTY_OFF                          ( 2)
+  #define HUBS_CR_HUB_EMPTY_HUBS_H2_EMPTY_WID                          ( 1)
+  #define HUBS_CR_HUB_EMPTY_HUBS_H2_EMPTY_MSK                          (0x00000004)
+  #define HUBS_CR_HUB_EMPTY_HUBS_H2_EMPTY_MAX                          (0x00000001)
+  #define HUBS_CR_HUB_EMPTY_HUBS_H2_EMPTY_DEF                          (0x00000001)
+
+#define HUBS_CR_HUB0_STATUS_HUBS_REG                                 (0x00007030)
+  #define HUBS_CR_HUB0_STATUS_HUBS_REQ_VLD_P0_OFF                      ( 0)
+  #define HUBS_CR_HUB0_STATUS_HUBS_REQ_VLD_P0_WID                      ( 1)
+  #define HUBS_CR_HUB0_STATUS_HUBS_REQ_VLD_P0_MSK                      (0x00000001)
+  #define HUBS_CR_HUB0_STATUS_HUBS_REQ_VLD_P0_MAX                      (0x00000001)
+  #define HUBS_CR_HUB0_STATUS_HUBS_REQ_VLD_P0_DEF                      (0x00000000)
+  #define HUBS_CR_HUB0_STATUS_HUBS_REQ_VLD_P1_OFF                      ( 1)
+  #define HUBS_CR_HUB0_STATUS_HUBS_REQ_VLD_P1_WID                      ( 1)
+  #define HUBS_CR_HUB0_STATUS_HUBS_REQ_VLD_P1_MSK                      (0x00000002)
+  #define HUBS_CR_HUB0_STATUS_HUBS_REQ_VLD_P1_MAX                      (0x00000001)
+  #define HUBS_CR_HUB0_STATUS_HUBS_REQ_VLD_P1_DEF                      (0x00000000)
+  #define HUBS_CR_HUB0_STATUS_HUBS_REQ_VLD_P2_OFF                      ( 2)
+  #define HUBS_CR_HUB0_STATUS_HUBS_REQ_VLD_P2_WID                      ( 1)
+  #define HUBS_CR_HUB0_STATUS_HUBS_REQ_VLD_P2_MSK                      (0x00000004)
+  #define HUBS_CR_HUB0_STATUS_HUBS_REQ_VLD_P2_MAX                      (0x00000001)
+  #define HUBS_CR_HUB0_STATUS_HUBS_REQ_VLD_P2_DEF                      (0x00000000)
+  #define HUBS_CR_HUB0_STATUS_HUBS_REQ_VLD_P3_OFF                      ( 3)
+  #define HUBS_CR_HUB0_STATUS_HUBS_REQ_VLD_P3_WID                      ( 1)
+  #define HUBS_CR_HUB0_STATUS_HUBS_REQ_VLD_P3_MSK                      (0x00000008)
+  #define HUBS_CR_HUB0_STATUS_HUBS_REQ_VLD_P3_MAX                      (0x00000001)
+  #define HUBS_CR_HUB0_STATUS_HUBS_REQ_VLD_P3_DEF                      (0x00000000)
+  #define HUBS_CR_HUB0_STATUS_HUBS_TNX_VLD_P0_OFF                      ( 4)
+  #define HUBS_CR_HUB0_STATUS_HUBS_TNX_VLD_P0_WID                      ( 1)
+  #define HUBS_CR_HUB0_STATUS_HUBS_TNX_VLD_P0_MSK                      (0x00000010)
+  #define HUBS_CR_HUB0_STATUS_HUBS_TNX_VLD_P0_MAX                      (0x00000001)
+  #define HUBS_CR_HUB0_STATUS_HUBS_TNX_VLD_P0_DEF                      (0x00000000)
+  #define HUBS_CR_HUB0_STATUS_HUBS_TNX_VLD_P1_OFF                      ( 5)
+  #define HUBS_CR_HUB0_STATUS_HUBS_TNX_VLD_P1_WID                      ( 1)
+  #define HUBS_CR_HUB0_STATUS_HUBS_TNX_VLD_P1_MSK                      (0x00000020)
+  #define HUBS_CR_HUB0_STATUS_HUBS_TNX_VLD_P1_MAX                      (0x00000001)
+  #define HUBS_CR_HUB0_STATUS_HUBS_TNX_VLD_P1_DEF                      (0x00000000)
+  #define HUBS_CR_HUB0_STATUS_HUBS_TNX_VLD_P2_OFF                      ( 6)
+  #define HUBS_CR_HUB0_STATUS_HUBS_TNX_VLD_P2_WID                      ( 1)
+  #define HUBS_CR_HUB0_STATUS_HUBS_TNX_VLD_P2_MSK                      (0x00000040)
+  #define HUBS_CR_HUB0_STATUS_HUBS_TNX_VLD_P2_MAX                      (0x00000001)
+  #define HUBS_CR_HUB0_STATUS_HUBS_TNX_VLD_P2_DEF                      (0x00000000)
+  #define HUBS_CR_HUB0_STATUS_HUBS_TNX_VLD_P3_OFF                      ( 7)
+  #define HUBS_CR_HUB0_STATUS_HUBS_TNX_VLD_P3_WID                      ( 1)
+  #define HUBS_CR_HUB0_STATUS_HUBS_TNX_VLD_P3_MSK                      (0x00000080)
+  #define HUBS_CR_HUB0_STATUS_HUBS_TNX_VLD_P3_MAX                      (0x00000001)
+  #define HUBS_CR_HUB0_STATUS_HUBS_TNX_VLD_P3_DEF                      (0x00000000)
+
+#define HUBS_CR_HUB1_STATUS_HUBS_REG                                 (0x00007034)
+  #define HUBS_CR_HUB1_STATUS_HUBS_REQ_VLD_P0_OFF                      ( 0)
+  #define HUBS_CR_HUB1_STATUS_HUBS_REQ_VLD_P0_WID                      ( 1)
+  #define HUBS_CR_HUB1_STATUS_HUBS_REQ_VLD_P0_MSK                      (0x00000001)
+  #define HUBS_CR_HUB1_STATUS_HUBS_REQ_VLD_P0_MAX                      (0x00000001)
+  #define HUBS_CR_HUB1_STATUS_HUBS_REQ_VLD_P0_DEF                      (0x00000000)
+  #define HUBS_CR_HUB1_STATUS_HUBS_REQ_VLD_P1_OFF                      ( 1)
+  #define HUBS_CR_HUB1_STATUS_HUBS_REQ_VLD_P1_WID                      ( 1)
+  #define HUBS_CR_HUB1_STATUS_HUBS_REQ_VLD_P1_MSK                      (0x00000002)
+  #define HUBS_CR_HUB1_STATUS_HUBS_REQ_VLD_P1_MAX                      (0x00000001)
+  #define HUBS_CR_HUB1_STATUS_HUBS_REQ_VLD_P1_DEF                      (0x00000000)
+  #define HUBS_CR_HUB1_STATUS_HUBS_REQ_VLD_P2_OFF                      ( 2)
+  #define HUBS_CR_HUB1_STATUS_HUBS_REQ_VLD_P2_WID                      ( 1)
+  #define HUBS_CR_HUB1_STATUS_HUBS_REQ_VLD_P2_MSK                      (0x00000004)
+  #define HUBS_CR_HUB1_STATUS_HUBS_REQ_VLD_P2_MAX                      (0x00000001)
+  #define HUBS_CR_HUB1_STATUS_HUBS_REQ_VLD_P2_DEF                      (0x00000000)
+  #define HUBS_CR_HUB1_STATUS_HUBS_REQ_VLD_P3_OFF                      ( 3)
+  #define HUBS_CR_HUB1_STATUS_HUBS_REQ_VLD_P3_WID                      ( 1)
+  #define HUBS_CR_HUB1_STATUS_HUBS_REQ_VLD_P3_MSK                      (0x00000008)
+  #define HUBS_CR_HUB1_STATUS_HUBS_REQ_VLD_P3_MAX                      (0x00000001)
+  #define HUBS_CR_HUB1_STATUS_HUBS_REQ_VLD_P3_DEF                      (0x00000000)
+  #define HUBS_CR_HUB1_STATUS_HUBS_TNX_VLD_P0_OFF                      ( 4)
+  #define HUBS_CR_HUB1_STATUS_HUBS_TNX_VLD_P0_WID                      ( 1)
+  #define HUBS_CR_HUB1_STATUS_HUBS_TNX_VLD_P0_MSK                      (0x00000010)
+  #define HUBS_CR_HUB1_STATUS_HUBS_TNX_VLD_P0_MAX                      (0x00000001)
+  #define HUBS_CR_HUB1_STATUS_HUBS_TNX_VLD_P0_DEF                      (0x00000000)
+  #define HUBS_CR_HUB1_STATUS_HUBS_TNX_VLD_P1_OFF                      ( 5)
+  #define HUBS_CR_HUB1_STATUS_HUBS_TNX_VLD_P1_WID                      ( 1)
+  #define HUBS_CR_HUB1_STATUS_HUBS_TNX_VLD_P1_MSK                      (0x00000020)
+  #define HUBS_CR_HUB1_STATUS_HUBS_TNX_VLD_P1_MAX                      (0x00000001)
+  #define HUBS_CR_HUB1_STATUS_HUBS_TNX_VLD_P1_DEF                      (0x00000000)
+  #define HUBS_CR_HUB1_STATUS_HUBS_TNX_VLD_P2_OFF                      ( 6)
+  #define HUBS_CR_HUB1_STATUS_HUBS_TNX_VLD_P2_WID                      ( 1)
+  #define HUBS_CR_HUB1_STATUS_HUBS_TNX_VLD_P2_MSK                      (0x00000040)
+  #define HUBS_CR_HUB1_STATUS_HUBS_TNX_VLD_P2_MAX                      (0x00000001)
+  #define HUBS_CR_HUB1_STATUS_HUBS_TNX_VLD_P2_DEF                      (0x00000000)
+  #define HUBS_CR_HUB1_STATUS_HUBS_TNX_VLD_P3_OFF                      ( 7)
+  #define HUBS_CR_HUB1_STATUS_HUBS_TNX_VLD_P3_WID                      ( 1)
+  #define HUBS_CR_HUB1_STATUS_HUBS_TNX_VLD_P3_MSK                      (0x00000080)
+  #define HUBS_CR_HUB1_STATUS_HUBS_TNX_VLD_P3_MAX                      (0x00000001)
+  #define HUBS_CR_HUB1_STATUS_HUBS_TNX_VLD_P3_DEF                      (0x00000000)
+
+#define HUBS_CR_HUB2_STATUS_HUBS_REG                                 (0x00007038)
+  #define HUBS_CR_HUB2_STATUS_HUBS_REQ_VLD_P0_OFF                      ( 0)
+  #define HUBS_CR_HUB2_STATUS_HUBS_REQ_VLD_P0_WID                      ( 1)
+  #define HUBS_CR_HUB2_STATUS_HUBS_REQ_VLD_P0_MSK                      (0x00000001)
+  #define HUBS_CR_HUB2_STATUS_HUBS_REQ_VLD_P0_MAX                      (0x00000001)
+  #define HUBS_CR_HUB2_STATUS_HUBS_REQ_VLD_P0_DEF                      (0x00000000)
+  #define HUBS_CR_HUB2_STATUS_HUBS_REQ_VLD_P1_OFF                      ( 1)
+  #define HUBS_CR_HUB2_STATUS_HUBS_REQ_VLD_P1_WID                      ( 1)
+  #define HUBS_CR_HUB2_STATUS_HUBS_REQ_VLD_P1_MSK                      (0x00000002)
+  #define HUBS_CR_HUB2_STATUS_HUBS_REQ_VLD_P1_MAX                      (0x00000001)
+  #define HUBS_CR_HUB2_STATUS_HUBS_REQ_VLD_P1_DEF                      (0x00000000)
+  #define HUBS_CR_HUB2_STATUS_HUBS_REQ_VLD_P2_OFF                      ( 2)
+  #define HUBS_CR_HUB2_STATUS_HUBS_REQ_VLD_P2_WID                      ( 1)
+  #define HUBS_CR_HUB2_STATUS_HUBS_REQ_VLD_P2_MSK                      (0x00000004)
+  #define HUBS_CR_HUB2_STATUS_HUBS_REQ_VLD_P2_MAX                      (0x00000001)
+  #define HUBS_CR_HUB2_STATUS_HUBS_REQ_VLD_P2_DEF                      (0x00000000)
+  #define HUBS_CR_HUB2_STATUS_HUBS_REQ_VLD_P3_OFF                      ( 3)
+  #define HUBS_CR_HUB2_STATUS_HUBS_REQ_VLD_P3_WID                      ( 1)
+  #define HUBS_CR_HUB2_STATUS_HUBS_REQ_VLD_P3_MSK                      (0x00000008)
+  #define HUBS_CR_HUB2_STATUS_HUBS_REQ_VLD_P3_MAX                      (0x00000001)
+  #define HUBS_CR_HUB2_STATUS_HUBS_REQ_VLD_P3_DEF                      (0x00000000)
+  #define HUBS_CR_HUB2_STATUS_HUBS_TNX_VLD_P0_OFF                      ( 4)
+  #define HUBS_CR_HUB2_STATUS_HUBS_TNX_VLD_P0_WID                      ( 1)
+  #define HUBS_CR_HUB2_STATUS_HUBS_TNX_VLD_P0_MSK                      (0x00000010)
+  #define HUBS_CR_HUB2_STATUS_HUBS_TNX_VLD_P0_MAX                      (0x00000001)
+  #define HUBS_CR_HUB2_STATUS_HUBS_TNX_VLD_P0_DEF                      (0x00000000)
+  #define HUBS_CR_HUB2_STATUS_HUBS_TNX_VLD_P1_OFF                      ( 5)
+  #define HUBS_CR_HUB2_STATUS_HUBS_TNX_VLD_P1_WID                      ( 1)
+  #define HUBS_CR_HUB2_STATUS_HUBS_TNX_VLD_P1_MSK                      (0x00000020)
+  #define HUBS_CR_HUB2_STATUS_HUBS_TNX_VLD_P1_MAX                      (0x00000001)
+  #define HUBS_CR_HUB2_STATUS_HUBS_TNX_VLD_P1_DEF                      (0x00000000)
+  #define HUBS_CR_HUB2_STATUS_HUBS_TNX_VLD_P2_OFF                      ( 6)
+  #define HUBS_CR_HUB2_STATUS_HUBS_TNX_VLD_P2_WID                      ( 1)
+  #define HUBS_CR_HUB2_STATUS_HUBS_TNX_VLD_P2_MSK                      (0x00000040)
+  #define HUBS_CR_HUB2_STATUS_HUBS_TNX_VLD_P2_MAX                      (0x00000001)
+  #define HUBS_CR_HUB2_STATUS_HUBS_TNX_VLD_P2_DEF                      (0x00000000)
+  #define HUBS_CR_HUB2_STATUS_HUBS_TNX_VLD_P3_OFF                      ( 7)
+  #define HUBS_CR_HUB2_STATUS_HUBS_TNX_VLD_P3_WID                      ( 1)
+  #define HUBS_CR_HUB2_STATUS_HUBS_TNX_VLD_P3_MSK                      (0x00000080)
+  #define HUBS_CR_HUB2_STATUS_HUBS_TNX_VLD_P3_MAX                      (0x00000001)
+  #define HUBS_CR_HUB2_STATUS_HUBS_TNX_VLD_P3_DEF                      (0x00000000)
+
+#define HUBS_CR_VISA_CTL_SABHUB0S_HUBS_REG                           (0x00007100)
+  #define HUBS_CR_VISA_CTL_SABHUB0S_HUBS_Data_OFF                      ( 0)
+  #define HUBS_CR_VISA_CTL_SABHUB0S_HUBS_Data_WID                      (18)
+  #define HUBS_CR_VISA_CTL_SABHUB0S_HUBS_Data_MSK                      (0x0003FFFF)
+  #define HUBS_CR_VISA_CTL_SABHUB0S_HUBS_Data_MAX                      (0x0003FFFF)
+  #define HUBS_CR_VISA_CTL_SABHUB0S_HUBS_Data_DEF                      (0x00000000)
+  #define HUBS_CR_VISA_CTL_SABHUB0S_HUBS_VORANGE_OFF                   (31)
+  #define HUBS_CR_VISA_CTL_SABHUB0S_HUBS_VORANGE_WID                   ( 1)
+  #define HUBS_CR_VISA_CTL_SABHUB0S_HUBS_VORANGE_MSK                   (0x80000000)
+  #define HUBS_CR_VISA_CTL_SABHUB0S_HUBS_VORANGE_MAX                   (0x00000001)
+  #define HUBS_CR_VISA_CTL_SABHUB0S_HUBS_VORANGE_DEF                   (0x00000000)
+
+#define HUBS_CR_VISA_CTL_SABHUB1S_HUBS_REG                           (0x00007110)
+  #define HUBS_CR_VISA_CTL_SABHUB1S_HUBS_Data_OFF                      ( 0)
+  #define HUBS_CR_VISA_CTL_SABHUB1S_HUBS_Data_WID                      (18)
+  #define HUBS_CR_VISA_CTL_SABHUB1S_HUBS_Data_MSK                      (0x0003FFFF)
+  #define HUBS_CR_VISA_CTL_SABHUB1S_HUBS_Data_MAX                      (0x0003FFFF)
+  #define HUBS_CR_VISA_CTL_SABHUB1S_HUBS_Data_DEF                      (0x00000000)
+  #define HUBS_CR_VISA_CTL_SABHUB1S_HUBS_VORANGE_OFF                   (31)
+  #define HUBS_CR_VISA_CTL_SABHUB1S_HUBS_VORANGE_WID                   ( 1)
+  #define HUBS_CR_VISA_CTL_SABHUB1S_HUBS_VORANGE_MSK                   (0x80000000)
+  #define HUBS_CR_VISA_CTL_SABHUB1S_HUBS_VORANGE_MAX                   (0x00000001)
+  #define HUBS_CR_VISA_CTL_SABHUB1S_HUBS_VORANGE_DEF                   (0x00000000)
+
+#define HUBS_CR_VISA_CTL_SABHUB2S_HUBS_REG                           (0x00007120)
+  #define HUBS_CR_VISA_CTL_SABHUB2S_HUBS_Data_OFF                      ( 0)
+  #define HUBS_CR_VISA_CTL_SABHUB2S_HUBS_Data_WID                      (18)
+  #define HUBS_CR_VISA_CTL_SABHUB2S_HUBS_Data_MSK                      (0x0003FFFF)
+  #define HUBS_CR_VISA_CTL_SABHUB2S_HUBS_Data_MAX                      (0x0003FFFF)
+  #define HUBS_CR_VISA_CTL_SABHUB2S_HUBS_Data_DEF                      (0x00000000)
+  #define HUBS_CR_VISA_CTL_SABHUB2S_HUBS_VORANGE_OFF                   (31)
+  #define HUBS_CR_VISA_CTL_SABHUB2S_HUBS_VORANGE_WID                   ( 1)
+  #define HUBS_CR_VISA_CTL_SABHUB2S_HUBS_VORANGE_MSK                   (0x80000000)
+  #define HUBS_CR_VISA_CTL_SABHUB2S_HUBS_VORANGE_MAX                   (0x00000001)
+  #define HUBS_CR_VISA_CTL_SABHUB2S_HUBS_VORANGE_DEF                   (0x00000000)
+
+#define HUBS_CR_MBOX_WR_DATA_HUBS_REG                                (0x00007124)
+  #define HUBS_CR_MBOX_WR_DATA_HUBS_DATA_OFF                           ( 0)
+  #define HUBS_CR_MBOX_WR_DATA_HUBS_DATA_WID                           (32)
+  #define HUBS_CR_MBOX_WR_DATA_HUBS_DATA_MSK                           (0xFFFFFFFF)
+  #define HUBS_CR_MBOX_WR_DATA_HUBS_DATA_MAX                           (0xFFFFFFFF)
+  #define HUBS_CR_MBOX_WR_DATA_HUBS_DATA_DEF                           (0x00000000)
+
+#define HUBS_CR_MBOX_RD_DATA_HUBS_REG                                (0x00007128)
+  #define HUBS_CR_MBOX_RD_DATA_HUBS_DATA_OFF                           ( 0)
+  #define HUBS_CR_MBOX_RD_DATA_HUBS_DATA_WID                           (32)
+  #define HUBS_CR_MBOX_RD_DATA_HUBS_DATA_MSK                           (0xFFFFFFFF)
+  #define HUBS_CR_MBOX_RD_DATA_HUBS_DATA_MAX                           (0xFFFFFFFF)
+  #define HUBS_CR_MBOX_RD_DATA_HUBS_DATA_DEF                           (0x00000000)
+
+#define HUBS_CR_MBOX_ADDR_LO_HUBS_REG                                (0x0000712C)
+  #define HUBS_CR_MBOX_ADDR_LO_HUBS_ADDR_OFF                           ( 0)
+  #define HUBS_CR_MBOX_ADDR_LO_HUBS_ADDR_WID                           (32)
+  #define HUBS_CR_MBOX_ADDR_LO_HUBS_ADDR_MSK                           (0xFFFFFFFF)
+  #define HUBS_CR_MBOX_ADDR_LO_HUBS_ADDR_MAX                           (0xFFFFFFFF)
+  #define HUBS_CR_MBOX_ADDR_LO_HUBS_ADDR_DEF                           (0x00000000)
+
+#define HUBS_CR_MBOX_ADDR_HI_HUBS_REG                                (0x00007130)
+  #define HUBS_CR_MBOX_ADDR_HI_HUBS_ADDR_OFF                           ( 0)
+  #define HUBS_CR_MBOX_ADDR_HI_HUBS_ADDR_WID                           (32)
+  #define HUBS_CR_MBOX_ADDR_HI_HUBS_ADDR_MSK                           (0xFFFFFFFF)
+  #define HUBS_CR_MBOX_ADDR_HI_HUBS_ADDR_MAX                           (0xFFFFFFFF)
+  #define HUBS_CR_MBOX_ADDR_HI_HUBS_ADDR_DEF                           (0x00000000)
+
+#define HUBS_CR_MBOX_CMD_LO_HUBS_REG                                 (0x00007134)
+  #define HUBS_CR_MBOX_CMD_LO_HUBS_FBE_OFF                             ( 0)
+  #define HUBS_CR_MBOX_CMD_LO_HUBS_FBE_WID                             ( 4)
+  #define HUBS_CR_MBOX_CMD_LO_HUBS_FBE_MSK                             (0x0000000F)
+  #define HUBS_CR_MBOX_CMD_LO_HUBS_FBE_MAX                             (0x0000000F)
+  #define HUBS_CR_MBOX_CMD_LO_HUBS_FBE_DEF                             (0x00000000)
+  #define HUBS_CR_MBOX_CMD_LO_HUBS_LBE_OFF                             ( 4)
+  #define HUBS_CR_MBOX_CMD_LO_HUBS_LBE_WID                             ( 4)
+  #define HUBS_CR_MBOX_CMD_LO_HUBS_LBE_MSK                             (0x000000F0)
+  #define HUBS_CR_MBOX_CMD_LO_HUBS_LBE_MAX                             (0x0000000F)
+  #define HUBS_CR_MBOX_CMD_LO_HUBS_LBE_DEF                             (0x00000000)
+  #define HUBS_CR_MBOX_CMD_LO_HUBS_TAG_OFF                             ( 8)
+  #define HUBS_CR_MBOX_CMD_LO_HUBS_TAG_WID                             ( 8)
+  #define HUBS_CR_MBOX_CMD_LO_HUBS_TAG_MSK                             (0x0000FF00)
+  #define HUBS_CR_MBOX_CMD_LO_HUBS_TAG_MAX                             (0x000000FF)
+  #define HUBS_CR_MBOX_CMD_LO_HUBS_TAG_DEF                             (0x00000000)
+  #define HUBS_CR_MBOX_CMD_LO_HUBS_RQID_OFF                            (16)
+  #define HUBS_CR_MBOX_CMD_LO_HUBS_RQID_WID                            (16)
+  #define HUBS_CR_MBOX_CMD_LO_HUBS_RQID_MSK                            (0xFFFF0000)
+  #define HUBS_CR_MBOX_CMD_LO_HUBS_RQID_MAX                            (0x0000FFFF)
+  #define HUBS_CR_MBOX_CMD_LO_HUBS_RQID_DEF                            (0x00000000)
+
+#define HUBS_CR_MBOX_CMD_HI_HUBS_REG                                 (0x00007138)
+  #define HUBS_CR_MBOX_CMD_HI_HUBS_AT_OFF                              ( 0)
+  #define HUBS_CR_MBOX_CMD_HI_HUBS_AT_WID                              ( 2)
+  #define HUBS_CR_MBOX_CMD_HI_HUBS_AT_MSK                              (0x00000003)
+  #define HUBS_CR_MBOX_CMD_HI_HUBS_AT_MAX                              (0x00000003)
+  #define HUBS_CR_MBOX_CMD_HI_HUBS_AT_DEF                              (0x00000000)
+  #define HUBS_CR_MBOX_CMD_HI_HUBS_POISON_OFF                          ( 2)
+  #define HUBS_CR_MBOX_CMD_HI_HUBS_POISON_WID                          ( 1)
+  #define HUBS_CR_MBOX_CMD_HI_HUBS_POISON_MSK                          (0x00000004)
+  #define HUBS_CR_MBOX_CMD_HI_HUBS_POISON_MAX                          (0x00000001)
+  #define HUBS_CR_MBOX_CMD_HI_HUBS_POISON_DEF                          (0x00000000)
+  #define HUBS_CR_MBOX_CMD_HI_HUBS_LENGTH_OFF                          ( 3)
+  #define HUBS_CR_MBOX_CMD_HI_HUBS_LENGTH_WID                          ( 5)
+  #define HUBS_CR_MBOX_CMD_HI_HUBS_LENGTH_MSK                          (0x000000F8)
+  #define HUBS_CR_MBOX_CMD_HI_HUBS_LENGTH_MAX                          (0x0000001F)
+  #define HUBS_CR_MBOX_CMD_HI_HUBS_LENGTH_DEF                          (0x00000000)
+  #define HUBS_CR_MBOX_CMD_HI_HUBS_RELAXED_OFF                         ( 8)
+  #define HUBS_CR_MBOX_CMD_HI_HUBS_RELAXED_WID                         ( 1)
+  #define HUBS_CR_MBOX_CMD_HI_HUBS_RELAXED_MSK                         (0x00000100)
+  #define HUBS_CR_MBOX_CMD_HI_HUBS_RELAXED_MAX                         (0x00000001)
+  #define HUBS_CR_MBOX_CMD_HI_HUBS_RELAXED_DEF                         (0x00000000)
+  #define HUBS_CR_MBOX_CMD_HI_HUBS_NOSNOOP_OFF                         ( 9)
+  #define HUBS_CR_MBOX_CMD_HI_HUBS_NOSNOOP_WID                         ( 1)
+  #define HUBS_CR_MBOX_CMD_HI_HUBS_NOSNOOP_MSK                         (0x00000200)
+  #define HUBS_CR_MBOX_CMD_HI_HUBS_NOSNOOP_MAX                         (0x00000001)
+  #define HUBS_CR_MBOX_CMD_HI_HUBS_NOSNOOP_DEF                         (0x00000000)
+  #define HUBS_CR_MBOX_CMD_HI_HUBS_CHAIN_OFF                           (10)
+  #define HUBS_CR_MBOX_CMD_HI_HUBS_CHAIN_WID                           ( 1)
+  #define HUBS_CR_MBOX_CMD_HI_HUBS_CHAIN_MSK                           (0x00000400)
+  #define HUBS_CR_MBOX_CMD_HI_HUBS_CHAIN_MAX                           (0x00000001)
+  #define HUBS_CR_MBOX_CMD_HI_HUBS_CHAIN_DEF                           (0x00000000)
+  #define HUBS_CR_MBOX_CMD_HI_HUBS_CTYPE_OFF                           (11)
+  #define HUBS_CR_MBOX_CMD_HI_HUBS_CTYPE_WID                           ( 5)
+  #define HUBS_CR_MBOX_CMD_HI_HUBS_CTYPE_MSK                           (0x0000F800)
+  #define HUBS_CR_MBOX_CMD_HI_HUBS_CTYPE_MAX                           (0x0000001F)
+  #define HUBS_CR_MBOX_CMD_HI_HUBS_CTYPE_DEF                           (0x00000000)
+  #define HUBS_CR_MBOX_CMD_HI_HUBS_FMT_OFF                             (16)
+  #define HUBS_CR_MBOX_CMD_HI_HUBS_FMT_WID                             ( 2)
+  #define HUBS_CR_MBOX_CMD_HI_HUBS_FMT_MSK                             (0x00030000)
+  #define HUBS_CR_MBOX_CMD_HI_HUBS_FMT_MAX                             (0x00000003)
+  #define HUBS_CR_MBOX_CMD_HI_HUBS_FMT_DEF                             (0x00000000)
+  #define HUBS_CR_MBOX_CMD_HI_HUBS_TC_OFF                              (18)
+  #define HUBS_CR_MBOX_CMD_HI_HUBS_TC_WID                              ( 4)
+  #define HUBS_CR_MBOX_CMD_HI_HUBS_TC_MSK                              (0x003C0000)
+  #define HUBS_CR_MBOX_CMD_HI_HUBS_TC_MAX                              (0x0000000F)
+  #define HUBS_CR_MBOX_CMD_HI_HUBS_TC_DEF                              (0x00000000)
+  #define HUBS_CR_MBOX_CMD_HI_HUBS_RESERVED_OFF                        (22)
+  #define HUBS_CR_MBOX_CMD_HI_HUBS_RESERVED_WID                        ( 2)
+  #define HUBS_CR_MBOX_CMD_HI_HUBS_RESERVED_MSK                        (0x00C00000)
+  #define HUBS_CR_MBOX_CMD_HI_HUBS_RESERVED_MAX                        (0x00000003)
+  #define HUBS_CR_MBOX_CMD_HI_HUBS_RESERVED_DEF                        (0x00000000)
+  #define HUBS_CR_MBOX_CMD_HI_HUBS_DMI_PRIV_OFF                        (24)
+  #define HUBS_CR_MBOX_CMD_HI_HUBS_DMI_PRIV_WID                        ( 1)
+  #define HUBS_CR_MBOX_CMD_HI_HUBS_DMI_PRIV_MSK                        (0x01000000)
+  #define HUBS_CR_MBOX_CMD_HI_HUBS_DMI_PRIV_MAX                        (0x00000001)
+  #define HUBS_CR_MBOX_CMD_HI_HUBS_DMI_PRIV_DEF                        (0x00000000)
+  #define HUBS_CR_MBOX_CMD_HI_HUBS_CHID_OFF                            (25)
+  #define HUBS_CR_MBOX_CMD_HI_HUBS_CHID_WID                            ( 4)
+  #define HUBS_CR_MBOX_CMD_HI_HUBS_CHID_MSK                            (0x1E000000)
+  #define HUBS_CR_MBOX_CMD_HI_HUBS_CHID_MAX                            (0x0000000F)
+  #define HUBS_CR_MBOX_CMD_HI_HUBS_CHID_DEF                            (0x00000000)
+  #define HUBS_CR_MBOX_CMD_HI_HUBS_RTYPE_OFF                           (29)
+  #define HUBS_CR_MBOX_CMD_HI_HUBS_RTYPE_WID                           ( 2)
+  #define HUBS_CR_MBOX_CMD_HI_HUBS_RTYPE_MSK                           (0x60000000)
+  #define HUBS_CR_MBOX_CMD_HI_HUBS_RTYPE_MAX                           (0x00000003)
+  #define HUBS_CR_MBOX_CMD_HI_HUBS_RTYPE_DEF                           (0x00000000)
+  #define HUBS_CR_MBOX_CMD_HI_HUBS_START_OFF                           (31)
+  #define HUBS_CR_MBOX_CMD_HI_HUBS_START_WID                           ( 1)
+  #define HUBS_CR_MBOX_CMD_HI_HUBS_START_MSK                           (0x80000000)
+  #define HUBS_CR_MBOX_CMD_HI_HUBS_START_MAX                           (0x00000001)
+  #define HUBS_CR_MBOX_CMD_HI_HUBS_START_DEF                           (0x00000000)
+
+#define HUBS_CR_MBOX_CFG_HUBS_REG                                    (0x0000713C)
+  #define HUBS_CR_MBOX_CFG_HUBS_ENABLE_OFF                             ( 0)
+  #define HUBS_CR_MBOX_CFG_HUBS_ENABLE_WID                             ( 1)
+  #define HUBS_CR_MBOX_CFG_HUBS_ENABLE_MSK                             (0x00000001)
+  #define HUBS_CR_MBOX_CFG_HUBS_ENABLE_MAX                             (0x00000001)
+  #define HUBS_CR_MBOX_CFG_HUBS_ENABLE_DEF                             (0x00000000)
+  #define HUBS_CR_MBOX_CFG_HUBS_LOCK_IA_OFF                            ( 1)
+  #define HUBS_CR_MBOX_CFG_HUBS_LOCK_IA_WID                            ( 1)
+  #define HUBS_CR_MBOX_CFG_HUBS_LOCK_IA_MSK                            (0x00000002)
+  #define HUBS_CR_MBOX_CFG_HUBS_LOCK_IA_MAX                            (0x00000001)
+  #define HUBS_CR_MBOX_CFG_HUBS_LOCK_IA_DEF                            (0x00000001)
+  #define HUBS_CR_MBOX_CFG_HUBS_RESET_OFF                              ( 2)
+  #define HUBS_CR_MBOX_CFG_HUBS_RESET_WID                              ( 1)
+  #define HUBS_CR_MBOX_CFG_HUBS_RESET_MSK                              (0x00000004)
+  #define HUBS_CR_MBOX_CFG_HUBS_RESET_MAX                              (0x00000001)
+  #define HUBS_CR_MBOX_CFG_HUBS_RESET_DEF                              (0x00000000)
+  #define HUBS_CR_MBOX_CFG_HUBS_BLK_CYCLES_OFF                         ( 3)
+  #define HUBS_CR_MBOX_CFG_HUBS_BLK_CYCLES_WID                         ( 6)
+  #define HUBS_CR_MBOX_CFG_HUBS_BLK_CYCLES_MSK                         (0x000001F8)
+  #define HUBS_CR_MBOX_CFG_HUBS_BLK_CYCLES_MAX                         (0x0000003F)
+  #define HUBS_CR_MBOX_CFG_HUBS_BLK_CYCLES_DEF                         (0x00000000)
+  #define HUBS_CR_MBOX_CFG_HUBS_WR_DWORD_SEL_OFF                       ( 9)
+  #define HUBS_CR_MBOX_CFG_HUBS_WR_DWORD_SEL_WID                       ( 4)
+  #define HUBS_CR_MBOX_CFG_HUBS_WR_DWORD_SEL_MSK                       (0x00001E00)
+  #define HUBS_CR_MBOX_CFG_HUBS_WR_DWORD_SEL_MAX                       (0x0000000F)
+  #define HUBS_CR_MBOX_CFG_HUBS_WR_DWORD_SEL_DEF                       (0x00000000)
+  #define HUBS_CR_MBOX_CFG_HUBS_RD_DWORD_SEL_OFF                       (13)
+  #define HUBS_CR_MBOX_CFG_HUBS_RD_DWORD_SEL_WID                       ( 4)
+  #define HUBS_CR_MBOX_CFG_HUBS_RD_DWORD_SEL_MSK                       (0x0001E000)
+  #define HUBS_CR_MBOX_CFG_HUBS_RD_DWORD_SEL_MAX                       (0x0000000F)
+  #define HUBS_CR_MBOX_CFG_HUBS_RD_DWORD_SEL_DEF                       (0x00000000)
+  #define HUBS_CR_MBOX_CFG_HUBS_RPT_CMD_CNT_OFF                        (17)
+  #define HUBS_CR_MBOX_CFG_HUBS_RPT_CMD_CNT_WID                        ( 6)
+  #define HUBS_CR_MBOX_CFG_HUBS_RPT_CMD_CNT_MSK                        (0x007E0000)
+  #define HUBS_CR_MBOX_CFG_HUBS_RPT_CMD_CNT_MAX                        (0x0000003F)
+  #define HUBS_CR_MBOX_CFG_HUBS_RPT_CMD_CNT_DEF                        (0x00000000)
+  #define HUBS_CR_MBOX_CFG_HUBS_RPT_NXT_ADDR_OFF                       (23)
+  #define HUBS_CR_MBOX_CFG_HUBS_RPT_NXT_ADDR_WID                       ( 1)
+  #define HUBS_CR_MBOX_CFG_HUBS_RPT_NXT_ADDR_MSK                       (0x00800000)
+  #define HUBS_CR_MBOX_CFG_HUBS_RPT_NXT_ADDR_MAX                       (0x00000001)
+  #define HUBS_CR_MBOX_CFG_HUBS_RPT_NXT_ADDR_DEF                       (0x00000000)
+  #define HUBS_CR_MBOX_CFG_HUBS_RPT_NXT_PAGE_OFF                       (24)
+  #define HUBS_CR_MBOX_CFG_HUBS_RPT_NXT_PAGE_WID                       ( 1)
+  #define HUBS_CR_MBOX_CFG_HUBS_RPT_NXT_PAGE_MSK                       (0x01000000)
+  #define HUBS_CR_MBOX_CFG_HUBS_RPT_NXT_PAGE_MAX                       (0x00000001)
+  #define HUBS_CR_MBOX_CFG_HUBS_RPT_NXT_PAGE_DEF                       (0x00000000)
+  #define HUBS_CR_MBOX_CFG_HUBS_DIS_CMP_INV_OFF                        (25)
+  #define HUBS_CR_MBOX_CFG_HUBS_DIS_CMP_INV_WID                        ( 1)
+  #define HUBS_CR_MBOX_CFG_HUBS_DIS_CMP_INV_MSK                        (0x02000000)
+  #define HUBS_CR_MBOX_CFG_HUBS_DIS_CMP_INV_MAX                        (0x00000001)
+  #define HUBS_CR_MBOX_CFG_HUBS_DIS_CMP_INV_DEF                        (0x00000000)
+  #define HUBS_CR_MBOX_CFG_HUBS_FSM_STATE_OFF                          (26)
+  #define HUBS_CR_MBOX_CFG_HUBS_FSM_STATE_WID                          ( 4)
+  #define HUBS_CR_MBOX_CFG_HUBS_FSM_STATE_MSK                          (0x3C000000)
+  #define HUBS_CR_MBOX_CFG_HUBS_FSM_STATE_MAX                          (0x0000000F)
+  #define HUBS_CR_MBOX_CFG_HUBS_FSM_STATE_DEF                          (0x00000000)
+  #define HUBS_CR_MBOX_CFG_HUBS_P2P_ALL_OFF                            (30)
+  #define HUBS_CR_MBOX_CFG_HUBS_P2P_ALL_WID                            ( 1)
+  #define HUBS_CR_MBOX_CFG_HUBS_P2P_ALL_MSK                            (0x40000000)
+  #define HUBS_CR_MBOX_CFG_HUBS_P2P_ALL_MAX                            (0x00000001)
+  #define HUBS_CR_MBOX_CFG_HUBS_P2P_ALL_DEF                            (0x00000000)
+  #define HUBS_CR_MBOX_CFG_HUBS_SPARE_OFF                              (31)
+  #define HUBS_CR_MBOX_CFG_HUBS_SPARE_WID                              ( 1)
+  #define HUBS_CR_MBOX_CFG_HUBS_SPARE_MSK                              (0x80000000)
+  #define HUBS_CR_MBOX_CFG_HUBS_SPARE_MAX                              (0x00000001)
+  #define HUBS_CR_MBOX_CFG_HUBS_SPARE_DEF                              (0x00000000)
+
+#define HUBS_CR_MBOX_STATUS_HUBS_REG                                 (0x00007140)
+  #define HUBS_CR_MBOX_STATUS_HUBS_FSM_STATE_OFF                       ( 0)
+  #define HUBS_CR_MBOX_STATUS_HUBS_FSM_STATE_WID                       ( 4)
+  #define HUBS_CR_MBOX_STATUS_HUBS_FSM_STATE_MSK                       (0x0000000F)
+  #define HUBS_CR_MBOX_STATUS_HUBS_FSM_STATE_MAX                       (0x0000000F)
+  #define HUBS_CR_MBOX_STATUS_HUBS_FSM_STATE_DEF                       (0x00000000)
+  #define HUBS_CR_MBOX_STATUS_HUBS_RPT_CMD_CNT_OFF                     ( 4)
+  #define HUBS_CR_MBOX_STATUS_HUBS_RPT_CMD_CNT_WID                     ( 6)
+  #define HUBS_CR_MBOX_STATUS_HUBS_RPT_CMD_CNT_MSK                     (0x000003F0)
+  #define HUBS_CR_MBOX_STATUS_HUBS_RPT_CMD_CNT_MAX                     (0x0000003F)
+  #define HUBS_CR_MBOX_STATUS_HUBS_RPT_CMD_CNT_DEF                     (0x00000000)
+  #define HUBS_CR_MBOX_STATUS_HUBS_OPCODE_OFF                          (10)
+  #define HUBS_CR_MBOX_STATUS_HUBS_OPCODE_WID                          ( 7)
+  #define HUBS_CR_MBOX_STATUS_HUBS_OPCODE_MSK                          (0x0001FC00)
+  #define HUBS_CR_MBOX_STATUS_HUBS_OPCODE_MAX                          (0x0000007F)
+  #define HUBS_CR_MBOX_STATUS_HUBS_OPCODE_DEF                          (0x00000000)
+  #define HUBS_CR_MBOX_STATUS_HUBS_WR_DWORD_SEL_OFF                    (17)
+  #define HUBS_CR_MBOX_STATUS_HUBS_WR_DWORD_SEL_WID                    ( 4)
+  #define HUBS_CR_MBOX_STATUS_HUBS_WR_DWORD_SEL_MSK                    (0x001E0000)
+  #define HUBS_CR_MBOX_STATUS_HUBS_WR_DWORD_SEL_MAX                    (0x0000000F)
+  #define HUBS_CR_MBOX_STATUS_HUBS_WR_DWORD_SEL_DEF                    (0x00000000)
+  #define HUBS_CR_MBOX_STATUS_HUBS_RD_DWORD_SEL_OFF                    (21)
+  #define HUBS_CR_MBOX_STATUS_HUBS_RD_DWORD_SEL_WID                    ( 4)
+  #define HUBS_CR_MBOX_STATUS_HUBS_RD_DWORD_SEL_MSK                    (0x01E00000)
+  #define HUBS_CR_MBOX_STATUS_HUBS_RD_DWORD_SEL_MAX                    (0x0000000F)
+  #define HUBS_CR_MBOX_STATUS_HUBS_RD_DWORD_SEL_DEF                    (0x00000000)
+  #define HUBS_CR_MBOX_STATUS_HUBS_P2P_RD_UP_OFF                       (25)
+  #define HUBS_CR_MBOX_STATUS_HUBS_P2P_RD_UP_WID                       ( 1)
+  #define HUBS_CR_MBOX_STATUS_HUBS_P2P_RD_UP_MSK                       (0x02000000)
+  #define HUBS_CR_MBOX_STATUS_HUBS_P2P_RD_UP_MAX                       (0x00000001)
+  #define HUBS_CR_MBOX_STATUS_HUBS_P2P_RD_UP_DEF                       (0x00000000)
+  #define HUBS_CR_MBOX_STATUS_HUBS_P2P_RD_DN_OFF                       (26)
+  #define HUBS_CR_MBOX_STATUS_HUBS_P2P_RD_DN_WID                       ( 1)
+  #define HUBS_CR_MBOX_STATUS_HUBS_P2P_RD_DN_MSK                       (0x04000000)
+  #define HUBS_CR_MBOX_STATUS_HUBS_P2P_RD_DN_MAX                       (0x00000001)
+  #define HUBS_CR_MBOX_STATUS_HUBS_P2P_RD_DN_DEF                       (0x00000000)
+  #define HUBS_CR_MBOX_STATUS_HUBS_SPARE_OFF                           (27)
+  #define HUBS_CR_MBOX_STATUS_HUBS_SPARE_WID                           ( 5)
+  #define HUBS_CR_MBOX_STATUS_HUBS_SPARE_MSK                           (0xF8000000)
+  #define HUBS_CR_MBOX_STATUS_HUBS_SPARE_MAX                           (0x0000001F)
+  #define HUBS_CR_MBOX_STATUS_HUBS_SPARE_DEF                           (0x00000000)
+
+#define HUBS_CR_HUB0_BLOCK_UP_HUBS_REG                               (0x00007144)
+  #define HUBS_CR_HUB0_BLOCK_UP_HUBS_XTM_CHID_OFF                      ( 0)
+  #define HUBS_CR_HUB0_BLOCK_UP_HUBS_XTM_CHID_WID                      ( 9)
+  #define HUBS_CR_HUB0_BLOCK_UP_HUBS_XTM_CHID_MSK                      (0x000001FF)
+  #define HUBS_CR_HUB0_BLOCK_UP_HUBS_XTM_CHID_MAX                      (0x000001FF)
+  #define HUBS_CR_HUB0_BLOCK_UP_HUBS_XTM_CHID_DEF                      (0x00000000)
+  #define HUBS_CR_HUB0_BLOCK_UP_HUBS_NP_OFF                            ( 9)
+  #define HUBS_CR_HUB0_BLOCK_UP_HUBS_NP_WID                            ( 1)
+  #define HUBS_CR_HUB0_BLOCK_UP_HUBS_NP_MSK                            (0x00000200)
+  #define HUBS_CR_HUB0_BLOCK_UP_HUBS_NP_MAX                            (0x00000001)
+  #define HUBS_CR_HUB0_BLOCK_UP_HUBS_NP_DEF                            (0x00000000)
+  #define HUBS_CR_HUB0_BLOCK_UP_HUBS_PC_OFF                            (10)
+  #define HUBS_CR_HUB0_BLOCK_UP_HUBS_PC_WID                            ( 1)
+  #define HUBS_CR_HUB0_BLOCK_UP_HUBS_PC_MSK                            (0x00000400)
+  #define HUBS_CR_HUB0_BLOCK_UP_HUBS_PC_MAX                            (0x00000001)
+  #define HUBS_CR_HUB0_BLOCK_UP_HUBS_PC_DEF                            (0x00000000)
+
+#define MPRDRTRN_CR_CRDTCTL0_IMPH_REG                                (0x00007400)
+  #define MPRDRTRN_CR_CRDTCTL0_IMPH_DMIVC0_PMIN_OFF                    ( 0)
+  #define MPRDRTRN_CR_CRDTCTL0_IMPH_DMIVC0_PMIN_WID                    ( 3)
+  #define MPRDRTRN_CR_CRDTCTL0_IMPH_DMIVC0_PMIN_MSK                    (0x00000007)
+  #define MPRDRTRN_CR_CRDTCTL0_IMPH_DMIVC0_PMIN_MAX                    (0x00000007)
+  #define MPRDRTRN_CR_CRDTCTL0_IMPH_P10VC0_PMIN_OFF                    ( 3)
+  #define MPRDRTRN_CR_CRDTCTL0_IMPH_P10VC0_PMIN_WID                    ( 3)
+  #define MPRDRTRN_CR_CRDTCTL0_IMPH_P10VC0_PMIN_MSK                    (0x00000038)
+  #define MPRDRTRN_CR_CRDTCTL0_IMPH_P10VC0_PMIN_MAX                    (0x00000007)
+  #define MPRDRTRN_CR_CRDTCTL0_IMPH_P11VC0_PMIN_OFF                    ( 6)
+  #define MPRDRTRN_CR_CRDTCTL0_IMPH_P11VC0_PMIN_WID                    ( 3)
+  #define MPRDRTRN_CR_CRDTCTL0_IMPH_P11VC0_PMIN_MSK                    (0x000001C0)
+  #define MPRDRTRN_CR_CRDTCTL0_IMPH_P11VC0_PMIN_MAX                    (0x00000007)
+  #define MPRDRTRN_CR_CRDTCTL0_IMPH_P12VC0_PMIN_OFF                    ( 9)
+  #define MPRDRTRN_CR_CRDTCTL0_IMPH_P12VC0_PMIN_WID                    ( 3)
+  #define MPRDRTRN_CR_CRDTCTL0_IMPH_P12VC0_PMIN_MSK                    (0x00000E00)
+  #define MPRDRTRN_CR_CRDTCTL0_IMPH_P12VC0_PMIN_MAX                    (0x00000007)
+  #define MPRDRTRN_CR_CRDTCTL0_IMPH_DEVC0_PMIN_OFF                     (12)
+  #define MPRDRTRN_CR_CRDTCTL0_IMPH_DEVC0_PMIN_WID                     ( 3)
+  #define MPRDRTRN_CR_CRDTCTL0_IMPH_DEVC0_PMIN_MSK                     (0x00007000)
+  #define MPRDRTRN_CR_CRDTCTL0_IMPH_DEVC0_PMIN_MAX                     (0x00000007)
+  #define MPRDRTRN_CR_CRDTCTL0_IMPH_DMIVCP_PMIN_OFF                    (15)
+  #define MPRDRTRN_CR_CRDTCTL0_IMPH_DMIVCP_PMIN_WID                    ( 3)
+  #define MPRDRTRN_CR_CRDTCTL0_IMPH_DMIVCP_PMIN_MSK                    (0x00038000)
+  #define MPRDRTRN_CR_CRDTCTL0_IMPH_DMIVCP_PMIN_MAX                    (0x00000007)
+  #define MPRDRTRN_CR_CRDTCTL0_IMPH_DMIVCM_PMIN_OFF                    (18)
+  #define MPRDRTRN_CR_CRDTCTL0_IMPH_DMIVCM_PMIN_WID                    ( 3)
+  #define MPRDRTRN_CR_CRDTCTL0_IMPH_DMIVCM_PMIN_MSK                    (0x001C0000)
+  #define MPRDRTRN_CR_CRDTCTL0_IMPH_DMIVCM_PMIN_MAX                    (0x00000007)
+  #define MPRDRTRN_CR_CRDTCTL0_IMPH_DMIVC1_PMIN_OFF                    (21)
+  #define MPRDRTRN_CR_CRDTCTL0_IMPH_DMIVC1_PMIN_WID                    ( 3)
+  #define MPRDRTRN_CR_CRDTCTL0_IMPH_DMIVC1_PMIN_MSK                    (0x00E00000)
+  #define MPRDRTRN_CR_CRDTCTL0_IMPH_DMIVC1_PMIN_MAX                    (0x00000007)
+
+#define MPRDRTRN_CR_CRDTCTL1_IMPH_REG                                (0x00007404)
+  #define MPRDRTRN_CR_CRDTCTL1_IMPH_DMIVC0_NPMIN_OFF                   ( 0)
+  #define MPRDRTRN_CR_CRDTCTL1_IMPH_DMIVC0_NPMIN_WID                   ( 3)
+  #define MPRDRTRN_CR_CRDTCTL1_IMPH_DMIVC0_NPMIN_MSK                   (0x00000007)
+  #define MPRDRTRN_CR_CRDTCTL1_IMPH_DMIVC0_NPMIN_MAX                   (0x00000007)
+  #define MPRDRTRN_CR_CRDTCTL1_IMPH_P10VC0_NPMIN_OFF                   ( 3)
+  #define MPRDRTRN_CR_CRDTCTL1_IMPH_P10VC0_NPMIN_WID                   ( 3)
+  #define MPRDRTRN_CR_CRDTCTL1_IMPH_P10VC0_NPMIN_MSK                   (0x00000038)
+  #define MPRDRTRN_CR_CRDTCTL1_IMPH_P10VC0_NPMIN_MAX                   (0x00000007)
+  #define MPRDRTRN_CR_CRDTCTL1_IMPH_P11VC0_NPMIN_OFF                   ( 6)
+  #define MPRDRTRN_CR_CRDTCTL1_IMPH_P11VC0_NPMIN_WID                   ( 3)
+  #define MPRDRTRN_CR_CRDTCTL1_IMPH_P11VC0_NPMIN_MSK                   (0x000001C0)
+  #define MPRDRTRN_CR_CRDTCTL1_IMPH_P11VC0_NPMIN_MAX                   (0x00000007)
+  #define MPRDRTRN_CR_CRDTCTL1_IMPH_P12VC0_NPMIN_OFF                   ( 9)
+  #define MPRDRTRN_CR_CRDTCTL1_IMPH_P12VC0_NPMIN_WID                   ( 3)
+  #define MPRDRTRN_CR_CRDTCTL1_IMPH_P12VC0_NPMIN_MSK                   (0x00000E00)
+  #define MPRDRTRN_CR_CRDTCTL1_IMPH_P12VC0_NPMIN_MAX                   (0x00000007)
+  #define MPRDRTRN_CR_CRDTCTL1_IMPH_DEVC0_NPMIN_OFF                    (12)
+  #define MPRDRTRN_CR_CRDTCTL1_IMPH_DEVC0_NPMIN_WID                    ( 3)
+  #define MPRDRTRN_CR_CRDTCTL1_IMPH_DEVC0_NPMIN_MSK                    (0x00007000)
+  #define MPRDRTRN_CR_CRDTCTL1_IMPH_DEVC0_NPMIN_MAX                    (0x00000007)
+  #define MPRDRTRN_CR_CRDTCTL1_IMPH_DMIVCP_NPMIN_OFF                   (15)
+  #define MPRDRTRN_CR_CRDTCTL1_IMPH_DMIVCP_NPMIN_WID                   ( 3)
+  #define MPRDRTRN_CR_CRDTCTL1_IMPH_DMIVCP_NPMIN_MSK                   (0x00038000)
+  #define MPRDRTRN_CR_CRDTCTL1_IMPH_DMIVCP_NPMIN_MAX                   (0x00000007)
+  #define MPRDRTRN_CR_CRDTCTL1_IMPH_DMIVCM_NPMIN_OFF                   (18)
+  #define MPRDRTRN_CR_CRDTCTL1_IMPH_DMIVCM_NPMIN_WID                   ( 3)
+  #define MPRDRTRN_CR_CRDTCTL1_IMPH_DMIVCM_NPMIN_MSK                   (0x001C0000)
+  #define MPRDRTRN_CR_CRDTCTL1_IMPH_DMIVCM_NPMIN_MAX                   (0x00000007)
+  #define MPRDRTRN_CR_CRDTCTL1_IMPH_DMIVC1_NPMIN_OFF                   (21)
+  #define MPRDRTRN_CR_CRDTCTL1_IMPH_DMIVC1_NPMIN_WID                   ( 3)
+  #define MPRDRTRN_CR_CRDTCTL1_IMPH_DMIVC1_NPMIN_MSK                   (0x00E00000)
+  #define MPRDRTRN_CR_CRDTCTL1_IMPH_DMIVC1_NPMIN_MAX                   (0x00000007)
+
+#define MPRDRTRN_CR_CRDTCTL2_IMPH_REG                                (0x00007408)
+  #define MPRDRTRN_CR_CRDTCTL2_IMPH_DMIVC0_RRMIN_OFF                   ( 0)
+  #define MPRDRTRN_CR_CRDTCTL2_IMPH_DMIVC0_RRMIN_WID                   ( 3)
+  #define MPRDRTRN_CR_CRDTCTL2_IMPH_DMIVC0_RRMIN_MSK                   (0x00000007)
+  #define MPRDRTRN_CR_CRDTCTL2_IMPH_DMIVC0_RRMIN_MAX                   (0x00000007)
+  #define MPRDRTRN_CR_CRDTCTL2_IMPH_P10VC0_RRMIN_OFF                   ( 3)
+  #define MPRDRTRN_CR_CRDTCTL2_IMPH_P10VC0_RRMIN_WID                   ( 3)
+  #define MPRDRTRN_CR_CRDTCTL2_IMPH_P10VC0_RRMIN_MSK                   (0x00000038)
+  #define MPRDRTRN_CR_CRDTCTL2_IMPH_P10VC0_RRMIN_MAX                   (0x00000007)
+  #define MPRDRTRN_CR_CRDTCTL2_IMPH_P11VC0_RRMIN_OFF                   ( 6)
+  #define MPRDRTRN_CR_CRDTCTL2_IMPH_P11VC0_RRMIN_WID                   ( 3)
+  #define MPRDRTRN_CR_CRDTCTL2_IMPH_P11VC0_RRMIN_MSK                   (0x000001C0)
+  #define MPRDRTRN_CR_CRDTCTL2_IMPH_P11VC0_RRMIN_MAX                   (0x00000007)
+  #define MPRDRTRN_CR_CRDTCTL2_IMPH_P12VC0_RRMIN_OFF                   ( 9)
+  #define MPRDRTRN_CR_CRDTCTL2_IMPH_P12VC0_RRMIN_WID                   ( 3)
+  #define MPRDRTRN_CR_CRDTCTL2_IMPH_P12VC0_RRMIN_MSK                   (0x00000E00)
+  #define MPRDRTRN_CR_CRDTCTL2_IMPH_P12VC0_RRMIN_MAX                   (0x00000007)
+  #define MPRDRTRN_CR_CRDTCTL2_IMPH_DEVC0_RRMIN_OFF                    (12)
+  #define MPRDRTRN_CR_CRDTCTL2_IMPH_DEVC0_RRMIN_WID                    ( 3)
+  #define MPRDRTRN_CR_CRDTCTL2_IMPH_DEVC0_RRMIN_MSK                    (0x00007000)
+  #define MPRDRTRN_CR_CRDTCTL2_IMPH_DEVC0_RRMIN_MAX                    (0x00000007)
+  #define MPRDRTRN_CR_CRDTCTL2_IMPH_DMIVCP_RRMIN_OFF                   (15)
+  #define MPRDRTRN_CR_CRDTCTL2_IMPH_DMIVCP_RRMIN_WID                   ( 3)
+  #define MPRDRTRN_CR_CRDTCTL2_IMPH_DMIVCP_RRMIN_MSK                   (0x00038000)
+  #define MPRDRTRN_CR_CRDTCTL2_IMPH_DMIVCP_RRMIN_MAX                   (0x00000007)
+  #define MPRDRTRN_CR_CRDTCTL2_IMPH_DMIVCM_RRMIN_OFF                   (18)
+  #define MPRDRTRN_CR_CRDTCTL2_IMPH_DMIVCM_RRMIN_WID                   ( 3)
+  #define MPRDRTRN_CR_CRDTCTL2_IMPH_DMIVCM_RRMIN_MSK                   (0x001C0000)
+  #define MPRDRTRN_CR_CRDTCTL2_IMPH_DMIVCM_RRMIN_MAX                   (0x00000007)
+  #define MPRDRTRN_CR_CRDTCTL2_IMPH_DMIVC1_RRMIN_OFF                   (21)
+  #define MPRDRTRN_CR_CRDTCTL2_IMPH_DMIVC1_RRMIN_WID                   ( 3)
+  #define MPRDRTRN_CR_CRDTCTL2_IMPH_DMIVC1_RRMIN_MSK                   (0x00E00000)
+  #define MPRDRTRN_CR_CRDTCTL2_IMPH_DMIVC1_RRMIN_MAX                   (0x00000007)
+  #define MPRDRTRN_CR_CRDTCTL2_IMPH_DEVC1_RRMIN_OFF                    (24)
+  #define MPRDRTRN_CR_CRDTCTL2_IMPH_DEVC1_RRMIN_WID                    ( 6)
+  #define MPRDRTRN_CR_CRDTCTL2_IMPH_DEVC1_RRMIN_MSK                    (0x3F000000)
+  #define MPRDRTRN_CR_CRDTCTL2_IMPH_DEVC1_RRMIN_MAX                    (0x0000003F)
+
+#define MPRDRTRN_CR_CRDTCTL3_IMPH_REG                                (0x0000740C)
+  #define MPRDRTRN_CR_CRDTCTL3_IMPH_IOTRK_SHRD_OFF                     ( 0)
+  #define MPRDRTRN_CR_CRDTCTL3_IMPH_IOTRK_SHRD_WID                     ( 6)
+  #define MPRDRTRN_CR_CRDTCTL3_IMPH_IOTRK_SHRD_MSK                     (0x0000003F)
+  #define MPRDRTRN_CR_CRDTCTL3_IMPH_IOTRK_SHRD_MAX                     (0x0000003F)
+  #define MPRDRTRN_CR_CRDTCTL3_IMPH_RRTRK_SHRD_OFF                     ( 6)
+  #define MPRDRTRN_CR_CRDTCTL3_IMPH_RRTRK_SHRD_WID                     ( 7)
+  #define MPRDRTRN_CR_CRDTCTL3_IMPH_RRTRK_SHRD_MSK                     (0x00001FC0)
+  #define MPRDRTRN_CR_CRDTCTL3_IMPH_RRTRK_SHRD_MAX                     (0x0000007F)
+
+#define MPRDRTRN_CR_CRDTCTL4_IMPH_REG                                (0x00007410)
+  #define MPRDRTRN_CR_CRDTCTL4_IMPH_DMIVC0_PMAX_OFF                    ( 0)
+  #define MPRDRTRN_CR_CRDTCTL4_IMPH_DMIVC0_PMAX_WID                    ( 5)
+  #define MPRDRTRN_CR_CRDTCTL4_IMPH_DMIVC0_PMAX_MSK                    (0x0000001F)
+  #define MPRDRTRN_CR_CRDTCTL4_IMPH_DMIVC0_PMAX_MAX                    (0x0000001F)
+  #define MPRDRTRN_CR_CRDTCTL4_IMPH_P10VC0_PMAX_OFF                    ( 5)
+  #define MPRDRTRN_CR_CRDTCTL4_IMPH_P10VC0_PMAX_WID                    ( 5)
+  #define MPRDRTRN_CR_CRDTCTL4_IMPH_P10VC0_PMAX_MSK                    (0x000003E0)
+  #define MPRDRTRN_CR_CRDTCTL4_IMPH_P10VC0_PMAX_MAX                    (0x0000001F)
+  #define MPRDRTRN_CR_CRDTCTL4_IMPH_P11VC0_PMAX_OFF                    (10)
+  #define MPRDRTRN_CR_CRDTCTL4_IMPH_P11VC0_PMAX_WID                    ( 5)
+  #define MPRDRTRN_CR_CRDTCTL4_IMPH_P11VC0_PMAX_MSK                    (0x00007C00)
+  #define MPRDRTRN_CR_CRDTCTL4_IMPH_P11VC0_PMAX_MAX                    (0x0000001F)
+  #define MPRDRTRN_CR_CRDTCTL4_IMPH_P12VC0_PMAX_OFF                    (15)
+  #define MPRDRTRN_CR_CRDTCTL4_IMPH_P12VC0_PMAX_WID                    ( 5)
+  #define MPRDRTRN_CR_CRDTCTL4_IMPH_P12VC0_PMAX_MSK                    (0x000F8000)
+  #define MPRDRTRN_CR_CRDTCTL4_IMPH_P12VC0_PMAX_MAX                    (0x0000001F)
+  #define MPRDRTRN_CR_CRDTCTL4_IMPH_DEVC0_PMAX_OFF                     (20)
+  #define MPRDRTRN_CR_CRDTCTL4_IMPH_DEVC0_PMAX_WID                     ( 5)
+  #define MPRDRTRN_CR_CRDTCTL4_IMPH_DEVC0_PMAX_MSK                     (0x01F00000)
+  #define MPRDRTRN_CR_CRDTCTL4_IMPH_DEVC0_PMAX_MAX                     (0x0000001F)
+
+#define MPRDRTRN_CR_CRDTCTL5_IMPH_REG                                (0x00007414)
+  #define MPRDRTRN_CR_CRDTCTL5_IMPH_DMIVCP_PMAX_OFF                    ( 0)
+  #define MPRDRTRN_CR_CRDTCTL5_IMPH_DMIVCP_PMAX_WID                    ( 5)
+  #define MPRDRTRN_CR_CRDTCTL5_IMPH_DMIVCP_PMAX_MSK                    (0x0000001F)
+  #define MPRDRTRN_CR_CRDTCTL5_IMPH_DMIVCP_PMAX_MAX                    (0x0000001F)
+  #define MPRDRTRN_CR_CRDTCTL5_IMPH_DMIVCM_PMAX_OFF                    ( 5)
+  #define MPRDRTRN_CR_CRDTCTL5_IMPH_DMIVCM_PMAX_WID                    ( 5)
+  #define MPRDRTRN_CR_CRDTCTL5_IMPH_DMIVCM_PMAX_MSK                    (0x000003E0)
+  #define MPRDRTRN_CR_CRDTCTL5_IMPH_DMIVCM_PMAX_MAX                    (0x0000001F)
+  #define MPRDRTRN_CR_CRDTCTL5_IMPH_DMIVC1_PMAX_OFF                    (10)
+  #define MPRDRTRN_CR_CRDTCTL5_IMPH_DMIVC1_PMAX_WID                    ( 5)
+  #define MPRDRTRN_CR_CRDTCTL5_IMPH_DMIVC1_PMAX_MSK                    (0x00007C00)
+  #define MPRDRTRN_CR_CRDTCTL5_IMPH_DMIVC1_PMAX_MAX                    (0x0000001F)
+
+#define MPRDRTRN_CR_CRDTCTL6_IMPH_REG                                (0x00007418)
+  #define MPRDRTRN_CR_CRDTCTL6_IMPH_DMIVC0_NPMAX_OFF                   ( 0)
+  #define MPRDRTRN_CR_CRDTCTL6_IMPH_DMIVC0_NPMAX_WID                   ( 5)
+  #define MPRDRTRN_CR_CRDTCTL6_IMPH_DMIVC0_NPMAX_MSK                   (0x0000001F)
+  #define MPRDRTRN_CR_CRDTCTL6_IMPH_DMIVC0_NPMAX_MAX                   (0x0000001F)
+  #define MPRDRTRN_CR_CRDTCTL6_IMPH_P10VC0_NPMAX_OFF                   ( 5)
+  #define MPRDRTRN_CR_CRDTCTL6_IMPH_P10VC0_NPMAX_WID                   ( 5)
+  #define MPRDRTRN_CR_CRDTCTL6_IMPH_P10VC0_NPMAX_MSK                   (0x000003E0)
+  #define MPRDRTRN_CR_CRDTCTL6_IMPH_P10VC0_NPMAX_MAX                   (0x0000001F)
+  #define MPRDRTRN_CR_CRDTCTL6_IMPH_P11VC0_NPMAX_OFF                   (10)
+  #define MPRDRTRN_CR_CRDTCTL6_IMPH_P11VC0_NPMAX_WID                   ( 5)
+  #define MPRDRTRN_CR_CRDTCTL6_IMPH_P11VC0_NPMAX_MSK                   (0x00007C00)
+  #define MPRDRTRN_CR_CRDTCTL6_IMPH_P11VC0_NPMAX_MAX                   (0x0000001F)
+  #define MPRDRTRN_CR_CRDTCTL6_IMPH_P12VC0_NPMAX_OFF                   (15)
+  #define MPRDRTRN_CR_CRDTCTL6_IMPH_P12VC0_NPMAX_WID                   ( 5)
+  #define MPRDRTRN_CR_CRDTCTL6_IMPH_P12VC0_NPMAX_MSK                   (0x000F8000)
+  #define MPRDRTRN_CR_CRDTCTL6_IMPH_P12VC0_NPMAX_MAX                   (0x0000001F)
+  #define MPRDRTRN_CR_CRDTCTL6_IMPH_DEVC0_NPMAX_OFF                    (20)
+  #define MPRDRTRN_CR_CRDTCTL6_IMPH_DEVC0_NPMAX_WID                    ( 5)
+  #define MPRDRTRN_CR_CRDTCTL6_IMPH_DEVC0_NPMAX_MSK                    (0x01F00000)
+  #define MPRDRTRN_CR_CRDTCTL6_IMPH_DEVC0_NPMAX_MAX                    (0x0000001F)
+
+#define MPRDRTRN_CR_CRDTCTL7_IMPH_REG                                (0x0000741C)
+  #define MPRDRTRN_CR_CRDTCTL7_IMPH_DMIVCP_NPMAX_OFF                   ( 0)
+  #define MPRDRTRN_CR_CRDTCTL7_IMPH_DMIVCP_NPMAX_WID                   ( 5)
+  #define MPRDRTRN_CR_CRDTCTL7_IMPH_DMIVCP_NPMAX_MSK                   (0x0000001F)
+  #define MPRDRTRN_CR_CRDTCTL7_IMPH_DMIVCP_NPMAX_MAX                   (0x0000001F)
+  #define MPRDRTRN_CR_CRDTCTL7_IMPH_DMIVCM_NPMAX_OFF                   ( 5)
+  #define MPRDRTRN_CR_CRDTCTL7_IMPH_DMIVCM_NPMAX_WID                   ( 5)
+  #define MPRDRTRN_CR_CRDTCTL7_IMPH_DMIVCM_NPMAX_MSK                   (0x000003E0)
+  #define MPRDRTRN_CR_CRDTCTL7_IMPH_DMIVCM_NPMAX_MAX                   (0x0000001F)
+  #define MPRDRTRN_CR_CRDTCTL7_IMPH_DMIVC1_NPMAX_OFF                   (10)
+  #define MPRDRTRN_CR_CRDTCTL7_IMPH_DMIVC1_NPMAX_WID                   ( 5)
+  #define MPRDRTRN_CR_CRDTCTL7_IMPH_DMIVC1_NPMAX_MSK                   (0x00007C00)
+  #define MPRDRTRN_CR_CRDTCTL7_IMPH_DMIVC1_NPMAX_MAX                   (0x0000001F)
+
+#define MPRDRTRN_CR_VISA_CTL_MPIORDTRKS_IMPH_REG                     (0x00007420)
+  #define MPRDRTRN_CR_VISA_CTL_MPIORDTRKS_IMPH_DATA_OFF                ( 0)
+  #define MPRDRTRN_CR_VISA_CTL_MPIORDTRKS_IMPH_DATA_WID                (18)
+  #define MPRDRTRN_CR_VISA_CTL_MPIORDTRKS_IMPH_DATA_MSK                (0x0003FFFF)
+  #define MPRDRTRN_CR_VISA_CTL_MPIORDTRKS_IMPH_DATA_MAX                (0x0003FFFF)
+  #define MPRDRTRN_CR_VISA_CTL_MPIORDTRKS_IMPH_DATA_DEF                (0x00000000)
+  #define MPRDRTRN_CR_VISA_CTL_MPIORDTRKS_IMPH_VORANGE_OFF             (31)
+  #define MPRDRTRN_CR_VISA_CTL_MPIORDTRKS_IMPH_VORANGE_WID             ( 1)
+  #define MPRDRTRN_CR_VISA_CTL_MPIORDTRKS_IMPH_VORANGE_MSK             (0x80000000)
+  #define MPRDRTRN_CR_VISA_CTL_MPIORDTRKS_IMPH_VORANGE_MAX             (0x00000001)
+  #define MPRDRTRN_CR_VISA_CTL_MPIORDTRKS_IMPH_VORANGE_DEF             (0x00000000)
+
+#define MPRDRTRN_CR_VISA_XBAR_MPIORDTRKS_IMPH_REG                    (0x00007424)
+  #define MPRDRTRN_CR_VISA_XBAR_MPIORDTRKS_IMPH_DATA_OFF               ( 0)
+  #define MPRDRTRN_CR_VISA_XBAR_MPIORDTRKS_IMPH_DATA_WID               (32)
+  #define MPRDRTRN_CR_VISA_XBAR_MPIORDTRKS_IMPH_DATA_MSK               (0xFFFFFFFF)
+  #define MPRDRTRN_CR_VISA_XBAR_MPIORDTRKS_IMPH_DATA_MAX               (0xFFFFFFFF)
+  #define MPRDRTRN_CR_VISA_XBAR_MPIORDTRKS_IMPH_DATA_DEF               (0x76543210)
+
+#define MPRDRTRN_CR_VISA_CTL_MPIOTRKS_IMPH_REG                       (0x00007428)
+  #define MPRDRTRN_CR_VISA_CTL_MPIOTRKS_IMPH_DATA_OFF                  ( 0)
+  #define MPRDRTRN_CR_VISA_CTL_MPIOTRKS_IMPH_DATA_WID                  (18)
+  #define MPRDRTRN_CR_VISA_CTL_MPIOTRKS_IMPH_DATA_MSK                  (0x0003FFFF)
+  #define MPRDRTRN_CR_VISA_CTL_MPIOTRKS_IMPH_DATA_MAX                  (0x0003FFFF)
+  #define MPRDRTRN_CR_VISA_CTL_MPIOTRKS_IMPH_DATA_DEF                  (0x00000000)
+  #define MPRDRTRN_CR_VISA_CTL_MPIOTRKS_IMPH_VORANGE_OFF               (31)
+  #define MPRDRTRN_CR_VISA_CTL_MPIOTRKS_IMPH_VORANGE_WID               ( 1)
+  #define MPRDRTRN_CR_VISA_CTL_MPIOTRKS_IMPH_VORANGE_MSK               (0x80000000)
+  #define MPRDRTRN_CR_VISA_CTL_MPIOTRKS_IMPH_VORANGE_MAX               (0x00000001)
+  #define MPRDRTRN_CR_VISA_CTL_MPIOTRKS_IMPH_VORANGE_DEF               (0x00000000)
+
+#define MPRDRTRN_CR_PRIMDN_MASK1_IMPH_REG                            (0x00007430)
+  #define MPRDRTRN_CR_PRIMDN_MASK1_IMPH_VC_OFF                         ( 0)
+  #define MPRDRTRN_CR_PRIMDN_MASK1_IMPH_VC_WID                         ( 4)
+  #define MPRDRTRN_CR_PRIMDN_MASK1_IMPH_VC_MSK                         (0x0000000F)
+  #define MPRDRTRN_CR_PRIMDN_MASK1_IMPH_VC_MAX                         (0x0000000F)
+  #define MPRDRTRN_CR_PRIMDN_MASK1_IMPH_VC_DEF                         (0x00000000)
+  #define MPRDRTRN_CR_PRIMDN_MASK1_IMPH_FMT_CMDTYPE_OFF                ( 4)
+  #define MPRDRTRN_CR_PRIMDN_MASK1_IMPH_FMT_CMDTYPE_WID                ( 6)
+  #define MPRDRTRN_CR_PRIMDN_MASK1_IMPH_FMT_CMDTYPE_MSK                (0x000003F0)
+  #define MPRDRTRN_CR_PRIMDN_MASK1_IMPH_FMT_CMDTYPE_MAX                (0x0000003F)
+  #define MPRDRTRN_CR_PRIMDN_MASK1_IMPH_FMT_CMDTYPE_DEF                (0x00000000)
+  #define MPRDRTRN_CR_PRIMDN_MASK1_IMPH_TC_OFF                         (10)
+  #define MPRDRTRN_CR_PRIMDN_MASK1_IMPH_TC_WID                         ( 4)
+  #define MPRDRTRN_CR_PRIMDN_MASK1_IMPH_TC_MSK                         (0x00003C00)
+  #define MPRDRTRN_CR_PRIMDN_MASK1_IMPH_TC_MAX                         (0x0000000F)
+  #define MPRDRTRN_CR_PRIMDN_MASK1_IMPH_TC_DEF                         (0x00000000)
+  #define MPRDRTRN_CR_PRIMDN_MASK1_IMPH_NS_OFF                         (14)
+  #define MPRDRTRN_CR_PRIMDN_MASK1_IMPH_NS_WID                         ( 1)
+  #define MPRDRTRN_CR_PRIMDN_MASK1_IMPH_NS_MSK                         (0x00004000)
+  #define MPRDRTRN_CR_PRIMDN_MASK1_IMPH_NS_MAX                         (0x00000001)
+  #define MPRDRTRN_CR_PRIMDN_MASK1_IMPH_NS_DEF                         (0x00000000)
+  #define MPRDRTRN_CR_PRIMDN_MASK1_IMPH_RO_OFF                         (15)
+  #define MPRDRTRN_CR_PRIMDN_MASK1_IMPH_RO_WID                         ( 1)
+  #define MPRDRTRN_CR_PRIMDN_MASK1_IMPH_RO_MSK                         (0x00008000)
+  #define MPRDRTRN_CR_PRIMDN_MASK1_IMPH_RO_MAX                         (0x00000001)
+  #define MPRDRTRN_CR_PRIMDN_MASK1_IMPH_RO_DEF                         (0x00000000)
+  #define MPRDRTRN_CR_PRIMDN_MASK1_IMPH_LENGTH_OFF                     (16)
+  #define MPRDRTRN_CR_PRIMDN_MASK1_IMPH_LENGTH_WID                     ( 5)
+  #define MPRDRTRN_CR_PRIMDN_MASK1_IMPH_LENGTH_MSK                     (0x001F0000)
+  #define MPRDRTRN_CR_PRIMDN_MASK1_IMPH_LENGTH_MAX                     (0x0000001F)
+  #define MPRDRTRN_CR_PRIMDN_MASK1_IMPH_LENGTH_DEF                     (0x00000000)
+  #define MPRDRTRN_CR_PRIMDN_MASK1_IMPH_EP_OFF                         (21)
+  #define MPRDRTRN_CR_PRIMDN_MASK1_IMPH_EP_WID                         ( 1)
+  #define MPRDRTRN_CR_PRIMDN_MASK1_IMPH_EP_MSK                         (0x00200000)
+  #define MPRDRTRN_CR_PRIMDN_MASK1_IMPH_EP_MAX                         (0x00000001)
+  #define MPRDRTRN_CR_PRIMDN_MASK1_IMPH_EP_DEF                         (0x00000000)
+
+#define MPRDRTRN_CR_PRIMDN_MASK2_IMPH_REG                            (0x00007434)
+  #define MPRDRTRN_CR_PRIMDN_MASK2_IMPH_RQID_OFF                       ( 0)
+  #define MPRDRTRN_CR_PRIMDN_MASK2_IMPH_RQID_WID                       (16)
+  #define MPRDRTRN_CR_PRIMDN_MASK2_IMPH_RQID_MSK                       (0x0000FFFF)
+  #define MPRDRTRN_CR_PRIMDN_MASK2_IMPH_RQID_MAX                       (0x0000FFFF)
+  #define MPRDRTRN_CR_PRIMDN_MASK2_IMPH_RQID_DEF                       (0x00000000)
+  #define MPRDRTRN_CR_PRIMDN_MASK2_IMPH_TAG_OFF                        (16)
+  #define MPRDRTRN_CR_PRIMDN_MASK2_IMPH_TAG_WID                        ( 8)
+  #define MPRDRTRN_CR_PRIMDN_MASK2_IMPH_TAG_MSK                        (0x00FF0000)
+  #define MPRDRTRN_CR_PRIMDN_MASK2_IMPH_TAG_MAX                        (0x000000FF)
+  #define MPRDRTRN_CR_PRIMDN_MASK2_IMPH_TAG_DEF                        (0x00000000)
+  #define MPRDRTRN_CR_PRIMDN_MASK2_IMPH_LBEFBE_MSGTYPE_OFF             (24)
+  #define MPRDRTRN_CR_PRIMDN_MASK2_IMPH_LBEFBE_MSGTYPE_WID             ( 8)
+  #define MPRDRTRN_CR_PRIMDN_MASK2_IMPH_LBEFBE_MSGTYPE_MSK             (0xFF000000)
+  #define MPRDRTRN_CR_PRIMDN_MASK2_IMPH_LBEFBE_MSGTYPE_MAX             (0x000000FF)
+  #define MPRDRTRN_CR_PRIMDN_MASK2_IMPH_LBEFBE_MSGTYPE_DEF             (0x00000000)
+
+#define MPRDRTRN_CR_PRIMDN_MASK3_IMPH_REG                            (0x00007438)
+  #define MPRDRTRN_CR_PRIMDN_MASK3_IMPH_ADDR_31_0_OFF                  ( 0)
+  #define MPRDRTRN_CR_PRIMDN_MASK3_IMPH_ADDR_31_0_WID                  (32)
+  #define MPRDRTRN_CR_PRIMDN_MASK3_IMPH_ADDR_31_0_MSK                  (0xFFFFFFFF)
+  #define MPRDRTRN_CR_PRIMDN_MASK3_IMPH_ADDR_31_0_MAX                  (0xFFFFFFFF)
+  #define MPRDRTRN_CR_PRIMDN_MASK3_IMPH_ADDR_31_0_DEF                  (0x00000000)
+
+#define MPRDRTRN_CR_PRIMDN_MASK4_IMPH_REG                            (0x0000743C)
+  #define MPRDRTRN_CR_PRIMDN_MASK4_IMPH_ADDR_63_32_OFF                 ( 0)
+  #define MPRDRTRN_CR_PRIMDN_MASK4_IMPH_ADDR_63_32_WID                 (32)
+  #define MPRDRTRN_CR_PRIMDN_MASK4_IMPH_ADDR_63_32_MSK                 (0xFFFFFFFF)
+  #define MPRDRTRN_CR_PRIMDN_MASK4_IMPH_ADDR_63_32_MAX                 (0xFFFFFFFF)
+  #define MPRDRTRN_CR_PRIMDN_MASK4_IMPH_ADDR_63_32_DEF                 (0x00000000)
+
+#define MPRDRTRN_CR_PRIMDN_COMP1_IMPH_REG                            (0x00007440)
+  #define MPRDRTRN_CR_PRIMDN_COMP1_IMPH_VC_OFF                         ( 0)
+  #define MPRDRTRN_CR_PRIMDN_COMP1_IMPH_VC_WID                         ( 4)
+  #define MPRDRTRN_CR_PRIMDN_COMP1_IMPH_VC_MSK                         (0x0000000F)
+  #define MPRDRTRN_CR_PRIMDN_COMP1_IMPH_VC_MAX                         (0x0000000F)
+  #define MPRDRTRN_CR_PRIMDN_COMP1_IMPH_VC_DEF                         (0x00000000)
+  #define MPRDRTRN_CR_PRIMDN_COMP1_IMPH_FMT_CMDTYPE_OFF                ( 4)
+  #define MPRDRTRN_CR_PRIMDN_COMP1_IMPH_FMT_CMDTYPE_WID                ( 6)
+  #define MPRDRTRN_CR_PRIMDN_COMP1_IMPH_FMT_CMDTYPE_MSK                (0x000003F0)
+  #define MPRDRTRN_CR_PRIMDN_COMP1_IMPH_FMT_CMDTYPE_MAX                (0x0000003F)
+  #define MPRDRTRN_CR_PRIMDN_COMP1_IMPH_FMT_CMDTYPE_DEF                (0x00000000)
+  #define MPRDRTRN_CR_PRIMDN_COMP1_IMPH_TC_OFF                         (10)
+  #define MPRDRTRN_CR_PRIMDN_COMP1_IMPH_TC_WID                         ( 4)
+  #define MPRDRTRN_CR_PRIMDN_COMP1_IMPH_TC_MSK                         (0x00003C00)
+  #define MPRDRTRN_CR_PRIMDN_COMP1_IMPH_TC_MAX                         (0x0000000F)
+  #define MPRDRTRN_CR_PRIMDN_COMP1_IMPH_TC_DEF                         (0x00000000)
+  #define MPRDRTRN_CR_PRIMDN_COMP1_IMPH_EP_OFF                         (14)
+  #define MPRDRTRN_CR_PRIMDN_COMP1_IMPH_EP_WID                         ( 1)
+  #define MPRDRTRN_CR_PRIMDN_COMP1_IMPH_EP_MSK                         (0x00004000)
+  #define MPRDRTRN_CR_PRIMDN_COMP1_IMPH_EP_MAX                         (0x00000001)
+  #define MPRDRTRN_CR_PRIMDN_COMP1_IMPH_EP_DEF                         (0x00000000)
+  #define MPRDRTRN_CR_PRIMDN_COMP1_IMPH_NS_OFF                         (15)
+  #define MPRDRTRN_CR_PRIMDN_COMP1_IMPH_NS_WID                         ( 1)
+  #define MPRDRTRN_CR_PRIMDN_COMP1_IMPH_NS_MSK                         (0x00008000)
+  #define MPRDRTRN_CR_PRIMDN_COMP1_IMPH_NS_MAX                         (0x00000001)
+  #define MPRDRTRN_CR_PRIMDN_COMP1_IMPH_NS_DEF                         (0x00000000)
+  #define MPRDRTRN_CR_PRIMDN_COMP1_IMPH_RO_OFF                         (16)
+  #define MPRDRTRN_CR_PRIMDN_COMP1_IMPH_RO_WID                         ( 1)
+  #define MPRDRTRN_CR_PRIMDN_COMP1_IMPH_RO_MSK                         (0x00010000)
+  #define MPRDRTRN_CR_PRIMDN_COMP1_IMPH_RO_MAX                         (0x00000001)
+  #define MPRDRTRN_CR_PRIMDN_COMP1_IMPH_RO_DEF                         (0x00000000)
+  #define MPRDRTRN_CR_PRIMDN_COMP1_IMPH_LENGTH_OFF                     (17)
+  #define MPRDRTRN_CR_PRIMDN_COMP1_IMPH_LENGTH_WID                     ( 5)
+  #define MPRDRTRN_CR_PRIMDN_COMP1_IMPH_LENGTH_MSK                     (0x003E0000)
+  #define MPRDRTRN_CR_PRIMDN_COMP1_IMPH_LENGTH_MAX                     (0x0000001F)
+  #define MPRDRTRN_CR_PRIMDN_COMP1_IMPH_LENGTH_DEF                     (0x00000000)
+
+#define MPRDRTRN_CR_PRIMDN_COMP2_IMPH_REG                            (0x00007444)
+  #define MPRDRTRN_CR_PRIMDN_COMP2_IMPH_RQID_OFF                       ( 0)
+  #define MPRDRTRN_CR_PRIMDN_COMP2_IMPH_RQID_WID                       (16)
+  #define MPRDRTRN_CR_PRIMDN_COMP2_IMPH_RQID_MSK                       (0x0000FFFF)
+  #define MPRDRTRN_CR_PRIMDN_COMP2_IMPH_RQID_MAX                       (0x0000FFFF)
+  #define MPRDRTRN_CR_PRIMDN_COMP2_IMPH_RQID_DEF                       (0x00000000)
+  #define MPRDRTRN_CR_PRIMDN_COMP2_IMPH_TAG_OFF                        (16)
+  #define MPRDRTRN_CR_PRIMDN_COMP2_IMPH_TAG_WID                        ( 8)
+  #define MPRDRTRN_CR_PRIMDN_COMP2_IMPH_TAG_MSK                        (0x00FF0000)
+  #define MPRDRTRN_CR_PRIMDN_COMP2_IMPH_TAG_MAX                        (0x000000FF)
+  #define MPRDRTRN_CR_PRIMDN_COMP2_IMPH_TAG_DEF                        (0x00000000)
+  #define MPRDRTRN_CR_PRIMDN_COMP2_IMPH_LBEFBE_MSGTYPE_OFF             (24)
+  #define MPRDRTRN_CR_PRIMDN_COMP2_IMPH_LBEFBE_MSGTYPE_WID             ( 8)
+  #define MPRDRTRN_CR_PRIMDN_COMP2_IMPH_LBEFBE_MSGTYPE_MSK             (0xFF000000)
+  #define MPRDRTRN_CR_PRIMDN_COMP2_IMPH_LBEFBE_MSGTYPE_MAX             (0x000000FF)
+  #define MPRDRTRN_CR_PRIMDN_COMP2_IMPH_LBEFBE_MSGTYPE_DEF             (0x00000000)
+
+#define MPRDRTRN_CR_PRIMDN_COMP3_IMPH_REG                            (0x00007448)
+  #define MPRDRTRN_CR_PRIMDN_COMP3_IMPH_ADDR_31_0_OFF                  ( 0)
+  #define MPRDRTRN_CR_PRIMDN_COMP3_IMPH_ADDR_31_0_WID                  (32)
+  #define MPRDRTRN_CR_PRIMDN_COMP3_IMPH_ADDR_31_0_MSK                  (0xFFFFFFFF)
+  #define MPRDRTRN_CR_PRIMDN_COMP3_IMPH_ADDR_31_0_MAX                  (0xFFFFFFFF)
+  #define MPRDRTRN_CR_PRIMDN_COMP3_IMPH_ADDR_31_0_DEF                  (0x00000000)
+
+#define MPRDRTRN_CR_PRIMDN_COMP4_IMPH_REG                            (0x0000744C)
+  #define MPRDRTRN_CR_PRIMDN_COMP4_IMPH_ADDR_63_32_OFF                 ( 0)
+  #define MPRDRTRN_CR_PRIMDN_COMP4_IMPH_ADDR_63_32_WID                 (32)
+  #define MPRDRTRN_CR_PRIMDN_COMP4_IMPH_ADDR_63_32_MSK                 (0xFFFFFFFF)
+  #define MPRDRTRN_CR_PRIMDN_COMP4_IMPH_ADDR_63_32_MAX                 (0xFFFFFFFF)
+  #define MPRDRTRN_CR_PRIMDN_COMP4_IMPH_ADDR_63_32_DEF                 (0x00000000)
+
+#define MPRDRTRN_CR_PRIMDN_TRIGGER_IMPH_REG                          (0x00007450)
+  #define MPRDRTRN_CR_PRIMDN_TRIGGER_IMPH_ENABLE_OFF                   ( 0)
+  #define MPRDRTRN_CR_PRIMDN_TRIGGER_IMPH_ENABLE_WID                   ( 1)
+  #define MPRDRTRN_CR_PRIMDN_TRIGGER_IMPH_ENABLE_MSK                   (0x00000001)
+  #define MPRDRTRN_CR_PRIMDN_TRIGGER_IMPH_ENABLE_MAX                   (0x00000001)
+  #define MPRDRTRN_CR_PRIMDN_TRIGGER_IMPH_ENABLE_DEF                   (0x00000000)
+  #define MPRDRTRN_CR_PRIMDN_TRIGGER_IMPH_TRIGGERED_OFF                ( 1)
+  #define MPRDRTRN_CR_PRIMDN_TRIGGER_IMPH_TRIGGERED_WID                ( 1)
+  #define MPRDRTRN_CR_PRIMDN_TRIGGER_IMPH_TRIGGERED_MSK                (0x00000002)
+  #define MPRDRTRN_CR_PRIMDN_TRIGGER_IMPH_TRIGGERED_MAX                (0x00000001)
+  #define MPRDRTRN_CR_PRIMDN_TRIGGER_IMPH_TRIGGERED_DEF                (0x00000000)
+  #define MPRDRTRN_CR_PRIMDN_TRIGGER_IMPH_STALL_DNARB_OFF              ( 2)
+  #define MPRDRTRN_CR_PRIMDN_TRIGGER_IMPH_STALL_DNARB_WID              ( 1)
+  #define MPRDRTRN_CR_PRIMDN_TRIGGER_IMPH_STALL_DNARB_MSK              (0x00000004)
+  #define MPRDRTRN_CR_PRIMDN_TRIGGER_IMPH_STALL_DNARB_MAX              (0x00000001)
+  #define MPRDRTRN_CR_PRIMDN_TRIGGER_IMPH_STALL_DNARB_DEF              (0x00000000)
+  #define MPRDRTRN_CR_PRIMDN_TRIGGER_IMPH_STALL_DELAY_OFF              (23)
+  #define MPRDRTRN_CR_PRIMDN_TRIGGER_IMPH_STALL_DELAY_WID              ( 9)
+  #define MPRDRTRN_CR_PRIMDN_TRIGGER_IMPH_STALL_DELAY_MSK              (0xFF800000)
+  #define MPRDRTRN_CR_PRIMDN_TRIGGER_IMPH_STALL_DELAY_MAX              (0x000001FF)
+  #define MPRDRTRN_CR_PRIMDN_TRIGGER_IMPH_STALL_DELAY_DEF              (0x00000000)
+
+#define MPRDRTRN_CR_CRDTCTL8_IMPH_REG                                (0x00007454)
+  #define MPRDRTRN_CR_CRDTCTL8_IMPH_DMIVC0_RRMAX_OFF                   ( 0)
+  #define MPRDRTRN_CR_CRDTCTL8_IMPH_DMIVC0_RRMAX_WID                   ( 6)
+  #define MPRDRTRN_CR_CRDTCTL8_IMPH_DMIVC0_RRMAX_MSK                   (0x0000003F)
+  #define MPRDRTRN_CR_CRDTCTL8_IMPH_DMIVC0_RRMAX_MAX                   (0x0000003F)
+  #define MPRDRTRN_CR_CRDTCTL8_IMPH_P10VC0_RRMAX_OFF                   ( 6)
+  #define MPRDRTRN_CR_CRDTCTL8_IMPH_P10VC0_RRMAX_WID                   ( 6)
+  #define MPRDRTRN_CR_CRDTCTL8_IMPH_P10VC0_RRMAX_MSK                   (0x00000FC0)
+  #define MPRDRTRN_CR_CRDTCTL8_IMPH_P10VC0_RRMAX_MAX                   (0x0000003F)
+  #define MPRDRTRN_CR_CRDTCTL8_IMPH_P11VC0_RRMAX_OFF                   (12)
+  #define MPRDRTRN_CR_CRDTCTL8_IMPH_P11VC0_RRMAX_WID                   ( 6)
+  #define MPRDRTRN_CR_CRDTCTL8_IMPH_P11VC0_RRMAX_MSK                   (0x0003F000)
+  #define MPRDRTRN_CR_CRDTCTL8_IMPH_P11VC0_RRMAX_MAX                   (0x0000003F)
+  #define MPRDRTRN_CR_CRDTCTL8_IMPH_P12VC0_RRMAX_OFF                   (18)
+  #define MPRDRTRN_CR_CRDTCTL8_IMPH_P12VC0_RRMAX_WID                   ( 6)
+  #define MPRDRTRN_CR_CRDTCTL8_IMPH_P12VC0_RRMAX_MSK                   (0x00FC0000)
+  #define MPRDRTRN_CR_CRDTCTL8_IMPH_P12VC0_RRMAX_MAX                   (0x0000003F)
+  #define MPRDRTRN_CR_CRDTCTL8_IMPH_DEVC0_RRMAX_OFF                    (24)
+  #define MPRDRTRN_CR_CRDTCTL8_IMPH_DEVC0_RRMAX_WID                    ( 6)
+  #define MPRDRTRN_CR_CRDTCTL8_IMPH_DEVC0_RRMAX_MSK                    (0x3F000000)
+  #define MPRDRTRN_CR_CRDTCTL8_IMPH_DEVC0_RRMAX_MAX                    (0x0000003F)
+
+#define MPRDRTRN_CR_CRDTCTL9_IMPH_REG                                (0x00007458)
+  #define MPRDRTRN_CR_CRDTCTL9_IMPH_DMIVCP_RRMAX_OFF                   ( 0)
+  #define MPRDRTRN_CR_CRDTCTL9_IMPH_DMIVCP_RRMAX_WID                   ( 6)
+  #define MPRDRTRN_CR_CRDTCTL9_IMPH_DMIVCP_RRMAX_MSK                   (0x0000003F)
+  #define MPRDRTRN_CR_CRDTCTL9_IMPH_DMIVCP_RRMAX_MAX                   (0x0000003F)
+  #define MPRDRTRN_CR_CRDTCTL9_IMPH_DMIVCM_RRMAX_OFF                   ( 6)
+  #define MPRDRTRN_CR_CRDTCTL9_IMPH_DMIVCM_RRMAX_WID                   ( 6)
+  #define MPRDRTRN_CR_CRDTCTL9_IMPH_DMIVCM_RRMAX_MSK                   (0x00000FC0)
+  #define MPRDRTRN_CR_CRDTCTL9_IMPH_DMIVCM_RRMAX_MAX                   (0x0000003F)
+  #define MPRDRTRN_CR_CRDTCTL9_IMPH_DMIVC1_RRMAX_OFF                   (12)
+  #define MPRDRTRN_CR_CRDTCTL9_IMPH_DMIVC1_RRMAX_WID                   ( 6)
+  #define MPRDRTRN_CR_CRDTCTL9_IMPH_DMIVC1_RRMAX_MSK                   (0x0003F000)
+  #define MPRDRTRN_CR_CRDTCTL9_IMPH_DMIVC1_RRMAX_MAX                   (0x0000003F)
+  #define MPRDRTRN_CR_CRDTCTL9_IMPH_DEVC1_RRMAX_OFF                    (18)
+  #define MPRDRTRN_CR_CRDTCTL9_IMPH_DEVC1_RRMAX_WID                    ( 6)
+  #define MPRDRTRN_CR_CRDTCTL9_IMPH_DEVC1_RRMAX_MSK                    (0x00FC0000)
+  #define MPRDRTRN_CR_CRDTCTL9_IMPH_DEVC1_RRMAX_MAX                    (0x0000003F)
+
+#define MPRDRTRN_CR_PCIE_POPUP_CTL_IMPH_REG                          (0x00007500)
+  #define MPRDRTRN_CR_PCIE_POPUP_CTL_IMPH_LIM_OFF                      ( 0)
+  #define MPRDRTRN_CR_PCIE_POPUP_CTL_IMPH_LIM_WID                      (16)
+  #define MPRDRTRN_CR_PCIE_POPUP_CTL_IMPH_LIM_MSK                      (0x0000FFFF)
+  #define MPRDRTRN_CR_PCIE_POPUP_CTL_IMPH_LIM_MAX                      (0x0000FFFF)
+  #define MPRDRTRN_CR_PCIE_POPUP_CTL_IMPH_LIM_DEF                      (0x00000000)
+  #define MPRDRTRN_CR_PCIE_POPUP_CTL_IMPH_MSK_OFF                      (16)
+  #define MPRDRTRN_CR_PCIE_POPUP_CTL_IMPH_MSK_WID                      ( 3)
+  #define MPRDRTRN_CR_PCIE_POPUP_CTL_IMPH_MSK_MSK                      (0x00070000)
+  #define MPRDRTRN_CR_PCIE_POPUP_CTL_IMPH_MSK_MAX                      (0x00000007)
+  #define MPRDRTRN_CR_PCIE_POPUP_CTL_IMPH_MSK_DEF                      (0x00000007)
+
+#define MPRDRTRN_CR_VDMBDFBARSSKU_IMPH_REG                           (0x00007504)
+  #define MPRDRTRN_CR_VDMBDFBARSSKU_IMPH_FUNNUM_OFF                    ( 0)
+  #define MPRDRTRN_CR_VDMBDFBARSSKU_IMPH_FUNNUM_WID                    ( 3)
+  #define MPRDRTRN_CR_VDMBDFBARSSKU_IMPH_FUNNUM_MSK                    (0x00000007)
+  #define MPRDRTRN_CR_VDMBDFBARSSKU_IMPH_FUNNUM_MAX                    (0x00000007)
+  #define MPRDRTRN_CR_VDMBDFBARSSKU_IMPH_FUNNUM_DEF                    (0x00000000)
+  #define MPRDRTRN_CR_VDMBDFBARSSKU_IMPH_DEVNUM_OFF                    ( 3)
+  #define MPRDRTRN_CR_VDMBDFBARSSKU_IMPH_DEVNUM_WID                    ( 5)
+  #define MPRDRTRN_CR_VDMBDFBARSSKU_IMPH_DEVNUM_MSK                    (0x000000F8)
+  #define MPRDRTRN_CR_VDMBDFBARSSKU_IMPH_DEVNUM_MAX                    (0x0000001F)
+  #define MPRDRTRN_CR_VDMBDFBARSSKU_IMPH_DEVNUM_DEF                    (0x00000016)
+  #define MPRDRTRN_CR_VDMBDFBARSSKU_IMPH_BUSNUM_OFF                    ( 8)
+  #define MPRDRTRN_CR_VDMBDFBARSSKU_IMPH_BUSNUM_WID                    ( 8)
+  #define MPRDRTRN_CR_VDMBDFBARSSKU_IMPH_BUSNUM_MSK                    (0x0000FF00)
+  #define MPRDRTRN_CR_VDMBDFBARSSKU_IMPH_BUSNUM_MAX                    (0x000000FF)
+  #define MPRDRTRN_CR_VDMBDFBARSSKU_IMPH_BUSNUM_DEF                    (0x00000000)
+  #define MPRDRTRN_CR_VDMBDFBARSSKU_IMPH_BARNUM_OFF                    (16)
+  #define MPRDRTRN_CR_VDMBDFBARSSKU_IMPH_BARNUM_WID                    ( 3)
+  #define MPRDRTRN_CR_VDMBDFBARSSKU_IMPH_BARNUM_MSK                    (0x00070000)
+  #define MPRDRTRN_CR_VDMBDFBARSSKU_IMPH_BARNUM_MAX                    (0x00000007)
+  #define MPRDRTRN_CR_VDMBDFBARSSKU_IMPH_BARNUM_DEF                    (0x00000007)
+
+#define MPRDRTRN_CR_CRDTLCK_IMPH_REG                                 (0x000077FC)
+  #define MPRDRTRN_CR_CRDTLCK_IMPH_LOCK_OFF                            ( 0)
+  #define MPRDRTRN_CR_CRDTLCK_IMPH_LOCK_WID                            ( 1)
+  #define MPRDRTRN_CR_CRDTLCK_IMPH_LOCK_MSK                            (0x00000001)
+  #define MPRDRTRN_CR_CRDTLCK_IMPH_LOCK_MAX                            (0x00000001)
+  #define MPRDRTRN_CR_CRDTLCK_IMPH_LOCK_DEF                            (0x00000000)
+
+#define MPMCARB_CR_VCLIM0_IMPH_REG                                   (0x00007800)
+  #define MPMCARB_CR_VCLIM0_IMPH_VCPNPLIM_OFF                          ( 0)
+  #define MPMCARB_CR_VCLIM0_IMPH_VCPNPLIM_WID                          ( 3)
+  #define MPMCARB_CR_VCLIM0_IMPH_VCPNPLIM_MSK                          (0x00000007)
+  #define MPMCARB_CR_VCLIM0_IMPH_VCPNPLIM_MAX                          (0x00000007)
+  #define MPMCARB_CR_VCLIM0_IMPH_VCPNPLIM_DEF                          (0x00000004)
+  #define MPMCARB_CR_VCLIM0_IMPH_VCPPLIM_OFF                           ( 4)
+  #define MPMCARB_CR_VCLIM0_IMPH_VCPPLIM_WID                           ( 3)
+  #define MPMCARB_CR_VCLIM0_IMPH_VCPPLIM_MSK                           (0x00000070)
+  #define MPMCARB_CR_VCLIM0_IMPH_VCPPLIM_MAX                           (0x00000007)
+  #define MPMCARB_CR_VCLIM0_IMPH_VCPPLIM_DEF                           (0x00000004)
+  #define MPMCARB_CR_VCLIM0_IMPH_VCMNPLIM_OFF                          ( 8)
+  #define MPMCARB_CR_VCLIM0_IMPH_VCMNPLIM_WID                          ( 3)
+  #define MPMCARB_CR_VCLIM0_IMPH_VCMNPLIM_MSK                          (0x00000700)
+  #define MPMCARB_CR_VCLIM0_IMPH_VCMNPLIM_MAX                          (0x00000007)
+  #define MPMCARB_CR_VCLIM0_IMPH_VCMNPLIM_DEF                          (0x00000004)
+  #define MPMCARB_CR_VCLIM0_IMPH_VCMPLIM_OFF                           (12)
+  #define MPMCARB_CR_VCLIM0_IMPH_VCMPLIM_WID                           ( 3)
+  #define MPMCARB_CR_VCLIM0_IMPH_VCMPLIM_MSK                           (0x00007000)
+  #define MPMCARB_CR_VCLIM0_IMPH_VCMPLIM_MAX                           (0x00000007)
+  #define MPMCARB_CR_VCLIM0_IMPH_VCMPLIM_DEF                           (0x00000004)
+  #define MPMCARB_CR_VCLIM0_IMPH_VC0VTDLIM_OFF                         (16)
+  #define MPMCARB_CR_VCLIM0_IMPH_VC0VTDLIM_WID                         ( 3)
+  #define MPMCARB_CR_VCLIM0_IMPH_VC0VTDLIM_MSK                         (0x00070000)
+  #define MPMCARB_CR_VCLIM0_IMPH_VC0VTDLIM_MAX                         (0x00000007)
+  #define MPMCARB_CR_VCLIM0_IMPH_VC0VTDLIM_DEF                         (0x00000004)
+  #define MPMCARB_CR_VCLIM0_IMPH_VCPVTDLIM_OFF                         (20)
+  #define MPMCARB_CR_VCLIM0_IMPH_VCPVTDLIM_WID                         ( 3)
+  #define MPMCARB_CR_VCLIM0_IMPH_VCPVTDLIM_MSK                         (0x00700000)
+  #define MPMCARB_CR_VCLIM0_IMPH_VCPVTDLIM_MAX                         (0x00000007)
+  #define MPMCARB_CR_VCLIM0_IMPH_VCPVTDLIM_DEF                         (0x00000004)
+
+#define MPMCARB_CR_VCLIM1_IMPH_REG                                   (0x00007804)
+  #define MPMCARB_CR_VCLIM1_IMPH_IARD_OFF                              ( 0)
+  #define MPMCARB_CR_VCLIM1_IMPH_IARD_WID                              ( 3)
+  #define MPMCARB_CR_VCLIM1_IMPH_IARD_MSK                              (0x00000007)
+  #define MPMCARB_CR_VCLIM1_IMPH_IARD_MAX                              (0x00000007)
+  #define MPMCARB_CR_VCLIM1_IMPH_IARD_DEF                              (0x00000004)
+  #define MPMCARB_CR_VCLIM1_IMPH_IAWR_OFF                              ( 4)
+  #define MPMCARB_CR_VCLIM1_IMPH_IAWR_WID                              ( 3)
+  #define MPMCARB_CR_VCLIM1_IMPH_IAWR_MSK                              (0x00000070)
+  #define MPMCARB_CR_VCLIM1_IMPH_IAWR_MAX                              (0x00000007)
+  #define MPMCARB_CR_VCLIM1_IMPH_IAWR_DEF                              (0x00000004)
+  #define MPMCARB_CR_VCLIM1_IMPH_VTDL3_OFF                             ( 8)
+  #define MPMCARB_CR_VCLIM1_IMPH_VTDL3_WID                             ( 3)
+  #define MPMCARB_CR_VCLIM1_IMPH_VTDL3_MSK                             (0x00000700)
+  #define MPMCARB_CR_VCLIM1_IMPH_VTDL3_MAX                             (0x00000007)
+  #define MPMCARB_CR_VCLIM1_IMPH_VTDL3_DEF                             (0x00000004)
+  #define MPMCARB_CR_VCLIM1_IMPH_VTDNL3_OFF                            (12)
+  #define MPMCARB_CR_VCLIM1_IMPH_VTDNL3_WID                            ( 3)
+  #define MPMCARB_CR_VCLIM1_IMPH_VTDNL3_MSK                            (0x00007000)
+  #define MPMCARB_CR_VCLIM1_IMPH_VTDNL3_MAX                            (0x00000007)
+  #define MPMCARB_CR_VCLIM1_IMPH_VTDNL3_DEF                            (0x00000004)
+
+#define MPMCARB_CR_ATMC_STS_IMPH_REG                                 (0x00007808)
+  #define MPMCARB_CR_ATMC_STS_IMPH_VC1_WR_CNFLT_OFF                    ( 0)
+  #define MPMCARB_CR_ATMC_STS_IMPH_VC1_WR_CNFLT_WID                    ( 1)
+  #define MPMCARB_CR_ATMC_STS_IMPH_VC1_WR_CNFLT_MSK                    (0x00000001)
+  #define MPMCARB_CR_ATMC_STS_IMPH_VC1_WR_CNFLT_MAX                    (0x00000001)
+  #define MPMCARB_CR_ATMC_STS_IMPH_VC1_WR_CNFLT_DEF                    (0x00000000)
+  #define MPMCARB_CR_ATMC_STS_IMPH_VC1_RD_CNFLT_OFF                    ( 1)
+  #define MPMCARB_CR_ATMC_STS_IMPH_VC1_RD_CNFLT_WID                    ( 1)
+  #define MPMCARB_CR_ATMC_STS_IMPH_VC1_RD_CNFLT_MSK                    (0x00000002)
+  #define MPMCARB_CR_ATMC_STS_IMPH_VC1_RD_CNFLT_MAX                    (0x00000001)
+  #define MPMCARB_CR_ATMC_STS_IMPH_VC1_RD_CNFLT_DEF                    (0x00000000)
+
+#define MPMCARB_CR_VISA_CTL_MPMCARBS_F_IMPH_REG                      (0x00007820)
+  #define MPMCARB_CR_VISA_CTL_MPMCARBS_F_IMPH_DATA_OFF                 ( 0)
+  #define MPMCARB_CR_VISA_CTL_MPMCARBS_F_IMPH_DATA_WID                 (18)
+  #define MPMCARB_CR_VISA_CTL_MPMCARBS_F_IMPH_DATA_MSK                 (0x0003FFFF)
+  #define MPMCARB_CR_VISA_CTL_MPMCARBS_F_IMPH_DATA_MAX                 (0x0003FFFF)
+  #define MPMCARB_CR_VISA_CTL_MPMCARBS_F_IMPH_DATA_DEF                 (0x00000000)
+  #define MPMCARB_CR_VISA_CTL_MPMCARBS_F_IMPH_VORANGE_OFF              (31)
+  #define MPMCARB_CR_VISA_CTL_MPMCARBS_F_IMPH_VORANGE_WID              ( 1)
+  #define MPMCARB_CR_VISA_CTL_MPMCARBS_F_IMPH_VORANGE_MSK              (0x80000000)
+  #define MPMCARB_CR_VISA_CTL_MPMCARBS_F_IMPH_VORANGE_MAX              (0x00000001)
+  #define MPMCARB_CR_VISA_CTL_MPMCARBS_F_IMPH_VORANGE_DEF              (0x00000000)
+
+#define MPMCARB_CR_VISA_CTL_MPMCARBS_D_IMPH_REG                      (0x00007824)
+  #define MPMCARB_CR_VISA_CTL_MPMCARBS_D_IMPH_DATA_OFF                 ( 0)
+  #define MPMCARB_CR_VISA_CTL_MPMCARBS_D_IMPH_DATA_WID                 (18)
+  #define MPMCARB_CR_VISA_CTL_MPMCARBS_D_IMPH_DATA_MSK                 (0x0003FFFF)
+  #define MPMCARB_CR_VISA_CTL_MPMCARBS_D_IMPH_DATA_MAX                 (0x0003FFFF)
+  #define MPMCARB_CR_VISA_CTL_MPMCARBS_D_IMPH_DATA_DEF                 (0x00000000)
+  #define MPMCARB_CR_VISA_CTL_MPMCARBS_D_IMPH_VORANGE_OFF              (31)
+  #define MPMCARB_CR_VISA_CTL_MPMCARBS_D_IMPH_VORANGE_WID              ( 1)
+  #define MPMCARB_CR_VISA_CTL_MPMCARBS_D_IMPH_VORANGE_MSK              (0x80000000)
+  #define MPMCARB_CR_VISA_CTL_MPMCARBS_D_IMPH_VORANGE_MAX              (0x00000001)
+  #define MPMCARB_CR_VISA_CTL_MPMCARBS_D_IMPH_VORANGE_DEF              (0x00000000)
+
+#define MPMCARB_CR_MCARBLCK_IMPH_REG                                 (0x00007FFC)
+  #define MPMCARB_CR_MCARBLCK_IMPH_LOCK_OFF                            ( 0)
+  #define MPMCARB_CR_MCARBLCK_IMPH_LOCK_WID                            ( 1)
+  #define MPMCARB_CR_MCARBLCK_IMPH_LOCK_MSK                            (0x00000001)
+  #define MPMCARB_CR_MCARBLCK_IMPH_LOCK_MAX                            (0x00000001)
+  #define MPMCARB_CR_MCARBLCK_IMPH_LOCK_DEF                            (0x00000000)
+
+#define PCU_CR_CAMARILLO_MAILBOX_DATA0_PCU_REG                       (0x00005810)
+  #define PCU_CR_CAMARILLO_MAILBOX_DATA0_PCU_DATA_OFF                  ( 0)
+  #define PCU_CR_CAMARILLO_MAILBOX_DATA0_PCU_DATA_WID                  (32)
+  #define PCU_CR_CAMARILLO_MAILBOX_DATA0_PCU_DATA_MSK                  (0xFFFFFFFF)
+  #define PCU_CR_CAMARILLO_MAILBOX_DATA0_PCU_DATA_MAX                  (0xFFFFFFFF)
+  #define PCU_CR_CAMARILLO_MAILBOX_DATA0_PCU_DATA_DEF                  (0x00000000)
+
+#define PCU_CR_CAMARILLO_MAILBOX_DATA1_PCU_REG                       (0x00005814)
+  #define PCU_CR_CAMARILLO_MAILBOX_DATA1_PCU_DATA_OFF                  ( 0)
+  #define PCU_CR_CAMARILLO_MAILBOX_DATA1_PCU_DATA_WID                  (32)
+  #define PCU_CR_CAMARILLO_MAILBOX_DATA1_PCU_DATA_MSK                  (0xFFFFFFFF)
+  #define PCU_CR_CAMARILLO_MAILBOX_DATA1_PCU_DATA_MAX                  (0xFFFFFFFF)
+  #define PCU_CR_CAMARILLO_MAILBOX_DATA1_PCU_DATA_DEF                  (0x00000000)
+
+#define PCU_CR_CAMARILLO_MAILBOX_INTERFACE_PCU_REG                   (0x00005818)
+  #define PCU_CR_CAMARILLO_MAILBOX_INTERFACE_PCU_COMMAND_OFF           ( 0)
+  #define PCU_CR_CAMARILLO_MAILBOX_INTERFACE_PCU_COMMAND_WID           ( 8)
+  #define PCU_CR_CAMARILLO_MAILBOX_INTERFACE_PCU_COMMAND_MSK           (0x000000FF)
+  #define PCU_CR_CAMARILLO_MAILBOX_INTERFACE_PCU_COMMAND_MAX           (0x000000FF)
+  #define PCU_CR_CAMARILLO_MAILBOX_INTERFACE_PCU_COMMAND_DEF           (0x00000000)
+  #define PCU_CR_CAMARILLO_MAILBOX_INTERFACE_PCU_ADDR_CNTL_OFF         ( 8)
+  #define PCU_CR_CAMARILLO_MAILBOX_INTERFACE_PCU_ADDR_CNTL_WID         (21)
+  #define PCU_CR_CAMARILLO_MAILBOX_INTERFACE_PCU_ADDR_CNTL_MSK         (0x1FFFFF00)
+  #define PCU_CR_CAMARILLO_MAILBOX_INTERFACE_PCU_ADDR_CNTL_MAX         (0x001FFFFF)
+  #define PCU_CR_CAMARILLO_MAILBOX_INTERFACE_PCU_ADDR_CNTL_DEF         (0x00000000)
+  #define PCU_CR_CAMARILLO_MAILBOX_INTERFACE_PCU_RUN_BUSY_OFF          (31)
+  #define PCU_CR_CAMARILLO_MAILBOX_INTERFACE_PCU_RUN_BUSY_WID          ( 1)
+  #define PCU_CR_CAMARILLO_MAILBOX_INTERFACE_PCU_RUN_BUSY_MSK          (0x80000000)
+  #define PCU_CR_CAMARILLO_MAILBOX_INTERFACE_PCU_RUN_BUSY_MAX          (0x00000001)
+  #define PCU_CR_CAMARILLO_MAILBOX_INTERFACE_PCU_RUN_BUSY_DEF          (0x00000000)
+
+#define PCU_CR_PACKAGE_THERM_CAMARILLO_INTERRUPT_PCU_REG             (0x00005820)
+  #define PCU_CR_PACKAGE_THERM_CAMARILLO_INTERRUPT_PCU_HIGH_TEMP_INT_ENABLE_OFF ( 0)
+  #define PCU_CR_PACKAGE_THERM_CAMARILLO_INTERRUPT_PCU_HIGH_TEMP_INT_ENABLE_WID ( 1)
+  #define PCU_CR_PACKAGE_THERM_CAMARILLO_INTERRUPT_PCU_HIGH_TEMP_INT_ENABLE_MSK (0x00000001)
+  #define PCU_CR_PACKAGE_THERM_CAMARILLO_INTERRUPT_PCU_HIGH_TEMP_INT_ENABLE_MAX (0x00000001)
+  #define PCU_CR_PACKAGE_THERM_CAMARILLO_INTERRUPT_PCU_HIGH_TEMP_INT_ENABLE_DEF (0x00000000)
+  #define PCU_CR_PACKAGE_THERM_CAMARILLO_INTERRUPT_PCU_LOW_TEMP_INT_ENABLE_OFF ( 1)
+  #define PCU_CR_PACKAGE_THERM_CAMARILLO_INTERRUPT_PCU_LOW_TEMP_INT_ENABLE_WID ( 1)
+  #define PCU_CR_PACKAGE_THERM_CAMARILLO_INTERRUPT_PCU_LOW_TEMP_INT_ENABLE_MSK (0x00000002)
+  #define PCU_CR_PACKAGE_THERM_CAMARILLO_INTERRUPT_PCU_LOW_TEMP_INT_ENABLE_MAX (0x00000001)
+  #define PCU_CR_PACKAGE_THERM_CAMARILLO_INTERRUPT_PCU_LOW_TEMP_INT_ENABLE_DEF (0x00000000)
+  #define PCU_CR_PACKAGE_THERM_CAMARILLO_INTERRUPT_PCU_PROCHOT_INT_ENABLE_OFF ( 2)
+  #define PCU_CR_PACKAGE_THERM_CAMARILLO_INTERRUPT_PCU_PROCHOT_INT_ENABLE_WID ( 1)
+  #define PCU_CR_PACKAGE_THERM_CAMARILLO_INTERRUPT_PCU_PROCHOT_INT_ENABLE_MSK (0x00000004)
+  #define PCU_CR_PACKAGE_THERM_CAMARILLO_INTERRUPT_PCU_PROCHOT_INT_ENABLE_MAX (0x00000001)
+  #define PCU_CR_PACKAGE_THERM_CAMARILLO_INTERRUPT_PCU_PROCHOT_INT_ENABLE_DEF (0x00000000)
+  #define PCU_CR_PACKAGE_THERM_CAMARILLO_INTERRUPT_PCU_OUT_OF_SPEC_INT_ENABLE_OFF ( 4)
+  #define PCU_CR_PACKAGE_THERM_CAMARILLO_INTERRUPT_PCU_OUT_OF_SPEC_INT_ENABLE_WID ( 1)
+  #define PCU_CR_PACKAGE_THERM_CAMARILLO_INTERRUPT_PCU_OUT_OF_SPEC_INT_ENABLE_MSK (0x00000010)
+  #define PCU_CR_PACKAGE_THERM_CAMARILLO_INTERRUPT_PCU_OUT_OF_SPEC_INT_ENABLE_MAX (0x00000001)
+  #define PCU_CR_PACKAGE_THERM_CAMARILLO_INTERRUPT_PCU_OUT_OF_SPEC_INT_ENABLE_DEF (0x00000000)
+  #define PCU_CR_PACKAGE_THERM_CAMARILLO_INTERRUPT_PCU_THRESHOLD_1_REL_TEMP_OFF ( 8)
+  #define PCU_CR_PACKAGE_THERM_CAMARILLO_INTERRUPT_PCU_THRESHOLD_1_REL_TEMP_WID ( 7)
+  #define PCU_CR_PACKAGE_THERM_CAMARILLO_INTERRUPT_PCU_THRESHOLD_1_REL_TEMP_MSK (0x00007F00)
+  #define PCU_CR_PACKAGE_THERM_CAMARILLO_INTERRUPT_PCU_THRESHOLD_1_REL_TEMP_MAX (0x0000007F)
+  #define PCU_CR_PACKAGE_THERM_CAMARILLO_INTERRUPT_PCU_THRESHOLD_1_REL_TEMP_DEF (0x00000000)
+  #define PCU_CR_PACKAGE_THERM_CAMARILLO_INTERRUPT_PCU_THRESHOLD_1_INT_ENABLE_OFF (15)
+  #define PCU_CR_PACKAGE_THERM_CAMARILLO_INTERRUPT_PCU_THRESHOLD_1_INT_ENABLE_WID ( 1)
+  #define PCU_CR_PACKAGE_THERM_CAMARILLO_INTERRUPT_PCU_THRESHOLD_1_INT_ENABLE_MSK (0x00008000)
+  #define PCU_CR_PACKAGE_THERM_CAMARILLO_INTERRUPT_PCU_THRESHOLD_1_INT_ENABLE_MAX (0x00000001)
+  #define PCU_CR_PACKAGE_THERM_CAMARILLO_INTERRUPT_PCU_THRESHOLD_1_INT_ENABLE_DEF (0x00000000)
+  #define PCU_CR_PACKAGE_THERM_CAMARILLO_INTERRUPT_PCU_THRESHOLD_2_REL_TEMP_OFF (16)
+  #define PCU_CR_PACKAGE_THERM_CAMARILLO_INTERRUPT_PCU_THRESHOLD_2_REL_TEMP_WID ( 7)
+  #define PCU_CR_PACKAGE_THERM_CAMARILLO_INTERRUPT_PCU_THRESHOLD_2_REL_TEMP_MSK (0x007F0000)
+  #define PCU_CR_PACKAGE_THERM_CAMARILLO_INTERRUPT_PCU_THRESHOLD_2_REL_TEMP_MAX (0x0000007F)
+  #define PCU_CR_PACKAGE_THERM_CAMARILLO_INTERRUPT_PCU_THRESHOLD_2_REL_TEMP_DEF (0x00000000)
+  #define PCU_CR_PACKAGE_THERM_CAMARILLO_INTERRUPT_PCU_THRESHOLD_2_INT_ENABLE_OFF (23)
+  #define PCU_CR_PACKAGE_THERM_CAMARILLO_INTERRUPT_PCU_THRESHOLD_2_INT_ENABLE_WID ( 1)
+  #define PCU_CR_PACKAGE_THERM_CAMARILLO_INTERRUPT_PCU_THRESHOLD_2_INT_ENABLE_MSK (0x00800000)
+  #define PCU_CR_PACKAGE_THERM_CAMARILLO_INTERRUPT_PCU_THRESHOLD_2_INT_ENABLE_MAX (0x00000001)
+  #define PCU_CR_PACKAGE_THERM_CAMARILLO_INTERRUPT_PCU_THRESHOLD_2_INT_ENABLE_DEF (0x00000000)
+  #define PCU_CR_PACKAGE_THERM_CAMARILLO_INTERRUPT_PCU_POWER_INT_ENABLE_OFF (24)
+  #define PCU_CR_PACKAGE_THERM_CAMARILLO_INTERRUPT_PCU_POWER_INT_ENABLE_WID ( 1)
+  #define PCU_CR_PACKAGE_THERM_CAMARILLO_INTERRUPT_PCU_POWER_INT_ENABLE_MSK (0x01000000)
+  #define PCU_CR_PACKAGE_THERM_CAMARILLO_INTERRUPT_PCU_POWER_INT_ENABLE_MAX (0x00000001)
+  #define PCU_CR_PACKAGE_THERM_CAMARILLO_INTERRUPT_PCU_POWER_INT_ENABLE_DEF (0x00000000)
+
+#define PCU_CR_DDR_PTM_CTL_PCU_REG                                   (0x00005880)
+  #define PCU_CR_DDR_PTM_CTL_PCU_OLTM_ENABLE_OFF                       ( 0)
+  #define PCU_CR_DDR_PTM_CTL_PCU_OLTM_ENABLE_WID                       ( 1)
+  #define PCU_CR_DDR_PTM_CTL_PCU_OLTM_ENABLE_MSK                       (0x00000001)
+  #define PCU_CR_DDR_PTM_CTL_PCU_OLTM_ENABLE_MAX                       (0x00000001)
+  #define PCU_CR_DDR_PTM_CTL_PCU_OLTM_ENABLE_DEF                       (0x00000000)
+  #define PCU_CR_DDR_PTM_CTL_PCU_CLTM_ENABLE_OFF                       ( 1)
+  #define PCU_CR_DDR_PTM_CTL_PCU_CLTM_ENABLE_WID                       ( 1)
+  #define PCU_CR_DDR_PTM_CTL_PCU_CLTM_ENABLE_MSK                       (0x00000002)
+  #define PCU_CR_DDR_PTM_CTL_PCU_CLTM_ENABLE_MAX                       (0x00000001)
+  #define PCU_CR_DDR_PTM_CTL_PCU_CLTM_ENABLE_DEF                       (0x00000000)
+  #define PCU_CR_DDR_PTM_CTL_PCU_REFRESH_2X_MODE_OFF                   ( 2)
+  #define PCU_CR_DDR_PTM_CTL_PCU_REFRESH_2X_MODE_WID                   ( 2)
+  #define PCU_CR_DDR_PTM_CTL_PCU_REFRESH_2X_MODE_MSK                   (0x0000000C)
+  #define PCU_CR_DDR_PTM_CTL_PCU_REFRESH_2X_MODE_MAX                   (0x00000003)
+  #define PCU_CR_DDR_PTM_CTL_PCU_REFRESH_2X_MODE_DEF                   (0x00000000)
+  #define PCU_CR_DDR_PTM_CTL_PCU_EXTTS_ENABLE_OFF                      ( 4)
+  #define PCU_CR_DDR_PTM_CTL_PCU_EXTTS_ENABLE_WID                      ( 1)
+  #define PCU_CR_DDR_PTM_CTL_PCU_EXTTS_ENABLE_MSK                      (0x00000010)
+  #define PCU_CR_DDR_PTM_CTL_PCU_EXTTS_ENABLE_MAX                      (0x00000001)
+  #define PCU_CR_DDR_PTM_CTL_PCU_EXTTS_ENABLE_DEF                      (0x00000000)
+  #define PCU_CR_DDR_PTM_CTL_PCU_LOCK_PTM_REGS_PCU_OFF                 ( 5)
+  #define PCU_CR_DDR_PTM_CTL_PCU_LOCK_PTM_REGS_PCU_WID                 ( 1)
+  #define PCU_CR_DDR_PTM_CTL_PCU_LOCK_PTM_REGS_PCU_MSK                 (0x00000020)
+  #define PCU_CR_DDR_PTM_CTL_PCU_LOCK_PTM_REGS_PCU_MAX                 (0x00000001)
+  #define PCU_CR_DDR_PTM_CTL_PCU_LOCK_PTM_REGS_PCU_DEF                 (0x00000000)
+  #define PCU_CR_DDR_PTM_CTL_PCU_PDWN_CONFIG_CTL_OFF                   ( 6)
+  #define PCU_CR_DDR_PTM_CTL_PCU_PDWN_CONFIG_CTL_WID                   ( 1)
+  #define PCU_CR_DDR_PTM_CTL_PCU_PDWN_CONFIG_CTL_MSK                   (0x00000040)
+  #define PCU_CR_DDR_PTM_CTL_PCU_PDWN_CONFIG_CTL_MAX                   (0x00000001)
+  #define PCU_CR_DDR_PTM_CTL_PCU_PDWN_CONFIG_CTL_DEF                   (0x00000000)
+  #define PCU_CR_DDR_PTM_CTL_PCU_DISABLE_DRAM_TS_OFF                   ( 7)
+  #define PCU_CR_DDR_PTM_CTL_PCU_DISABLE_DRAM_TS_WID                   ( 1)
+  #define PCU_CR_DDR_PTM_CTL_PCU_DISABLE_DRAM_TS_MSK                   (0x00000080)
+  #define PCU_CR_DDR_PTM_CTL_PCU_DISABLE_DRAM_TS_MAX                   (0x00000001)
+  #define PCU_CR_DDR_PTM_CTL_PCU_DISABLE_DRAM_TS_DEF                   (0x00000000)
+
+#define PCU_CR_DDR_ENERGY_SCALEFACTOR_PCU_REG                        (0x00005884)
+  #define PCU_CR_DDR_ENERGY_SCALEFACTOR_PCU_SCALEFACTOR_OFF            ( 0)
+  #define PCU_CR_DDR_ENERGY_SCALEFACTOR_PCU_SCALEFACTOR_WID            ( 3)
+  #define PCU_CR_DDR_ENERGY_SCALEFACTOR_PCU_SCALEFACTOR_MSK            (0x00000007)
+  #define PCU_CR_DDR_ENERGY_SCALEFACTOR_PCU_SCALEFACTOR_MAX            (0x00000007)
+  #define PCU_CR_DDR_ENERGY_SCALEFACTOR_PCU_SCALEFACTOR_DEF            (0x00000003)
+
+#define PCU_CR_DDR_RAPL_CHANNEL_POWER_FLOOR_PCU_REG                  (0x00005888)
+  #define PCU_CR_DDR_RAPL_CHANNEL_POWER_FLOOR_PCU_CH0_OFF              ( 0)
+  #define PCU_CR_DDR_RAPL_CHANNEL_POWER_FLOOR_PCU_CH0_WID              ( 8)
+  #define PCU_CR_DDR_RAPL_CHANNEL_POWER_FLOOR_PCU_CH0_MSK              (0x000000FF)
+  #define PCU_CR_DDR_RAPL_CHANNEL_POWER_FLOOR_PCU_CH0_MAX              (0x000000FF)
+  #define PCU_CR_DDR_RAPL_CHANNEL_POWER_FLOOR_PCU_CH0_DEF              (0x00000000)
+  #define PCU_CR_DDR_RAPL_CHANNEL_POWER_FLOOR_PCU_CH1_OFF              ( 8)
+  #define PCU_CR_DDR_RAPL_CHANNEL_POWER_FLOOR_PCU_CH1_WID              ( 8)
+  #define PCU_CR_DDR_RAPL_CHANNEL_POWER_FLOOR_PCU_CH1_MSK              (0x0000FF00)
+  #define PCU_CR_DDR_RAPL_CHANNEL_POWER_FLOOR_PCU_CH1_MAX              (0x000000FF)
+  #define PCU_CR_DDR_RAPL_CHANNEL_POWER_FLOOR_PCU_CH1_DEF              (0x00000000)
+
+#define PCU_CR_DDR_THERM_PERDIMM_STATUS_PCU_REG                      (0x0000588C)
+  #define PCU_CR_DDR_THERM_PERDIMM_STATUS_PCU_CH0_DIMM0_OFF            ( 0)
+  #define PCU_CR_DDR_THERM_PERDIMM_STATUS_PCU_CH0_DIMM0_WID            ( 2)
+  #define PCU_CR_DDR_THERM_PERDIMM_STATUS_PCU_CH0_DIMM0_MSK            (0x00000003)
+  #define PCU_CR_DDR_THERM_PERDIMM_STATUS_PCU_CH0_DIMM0_MAX            (0x00000003)
+  #define PCU_CR_DDR_THERM_PERDIMM_STATUS_PCU_CH0_DIMM0_DEF            (0x00000000)
+  #define PCU_CR_DDR_THERM_PERDIMM_STATUS_PCU_CH0_DIMM1_OFF            ( 2)
+  #define PCU_CR_DDR_THERM_PERDIMM_STATUS_PCU_CH0_DIMM1_WID            ( 2)
+  #define PCU_CR_DDR_THERM_PERDIMM_STATUS_PCU_CH0_DIMM1_MSK            (0x0000000C)
+  #define PCU_CR_DDR_THERM_PERDIMM_STATUS_PCU_CH0_DIMM1_MAX            (0x00000003)
+  #define PCU_CR_DDR_THERM_PERDIMM_STATUS_PCU_CH0_DIMM1_DEF            (0x00000000)
+  #define PCU_CR_DDR_THERM_PERDIMM_STATUS_PCU_CH1_DIMM0_OFF            ( 8)
+  #define PCU_CR_DDR_THERM_PERDIMM_STATUS_PCU_CH1_DIMM0_WID            ( 2)
+  #define PCU_CR_DDR_THERM_PERDIMM_STATUS_PCU_CH1_DIMM0_MSK            (0x00000300)
+  #define PCU_CR_DDR_THERM_PERDIMM_STATUS_PCU_CH1_DIMM0_MAX            (0x00000003)
+  #define PCU_CR_DDR_THERM_PERDIMM_STATUS_PCU_CH1_DIMM0_DEF            (0x00000000)
+  #define PCU_CR_DDR_THERM_PERDIMM_STATUS_PCU_CH1_DIMM1_OFF            (10)
+  #define PCU_CR_DDR_THERM_PERDIMM_STATUS_PCU_CH1_DIMM1_WID            ( 2)
+  #define PCU_CR_DDR_THERM_PERDIMM_STATUS_PCU_CH1_DIMM1_MSK            (0x00000C00)
+  #define PCU_CR_DDR_THERM_PERDIMM_STATUS_PCU_CH1_DIMM1_MAX            (0x00000003)
+  #define PCU_CR_DDR_THERM_PERDIMM_STATUS_PCU_CH1_DIMM1_DEF            (0x00000000)
+
+#define PCU_CR_DDR_WARM_THRESHOLD_CH0_PCU_REG                        (0x00005890)
+  #define PCU_CR_DDR_WARM_THRESHOLD_CH0_PCU_DIMM0_OFF                  ( 0)
+  #define PCU_CR_DDR_WARM_THRESHOLD_CH0_PCU_DIMM0_WID                  ( 8)
+  #define PCU_CR_DDR_WARM_THRESHOLD_CH0_PCU_DIMM0_MSK                  (0x000000FF)
+  #define PCU_CR_DDR_WARM_THRESHOLD_CH0_PCU_DIMM0_MAX                  (0x000000FF)
+  #define PCU_CR_DDR_WARM_THRESHOLD_CH0_PCU_DIMM0_DEF                  (0x000000FF)
+  #define PCU_CR_DDR_WARM_THRESHOLD_CH0_PCU_DIMM1_OFF                  ( 8)
+  #define PCU_CR_DDR_WARM_THRESHOLD_CH0_PCU_DIMM1_WID                  ( 8)
+  #define PCU_CR_DDR_WARM_THRESHOLD_CH0_PCU_DIMM1_MSK                  (0x0000FF00)
+  #define PCU_CR_DDR_WARM_THRESHOLD_CH0_PCU_DIMM1_MAX                  (0x000000FF)
+  #define PCU_CR_DDR_WARM_THRESHOLD_CH0_PCU_DIMM1_DEF                  (0x000000FF)
+
+#define PCU_CR_DDR_WARM_THRESHOLD_CH1_PCU_REG                        (0x00005894)
+  #define PCU_CR_DDR_WARM_THRESHOLD_CH1_PCU_DIMM0_OFF                  ( 0)
+  #define PCU_CR_DDR_WARM_THRESHOLD_CH1_PCU_DIMM0_WID                  ( 8)
+  #define PCU_CR_DDR_WARM_THRESHOLD_CH1_PCU_DIMM0_MSK                  (0x000000FF)
+  #define PCU_CR_DDR_WARM_THRESHOLD_CH1_PCU_DIMM0_MAX                  (0x000000FF)
+  #define PCU_CR_DDR_WARM_THRESHOLD_CH1_PCU_DIMM0_DEF                  (0x000000FF)
+  #define PCU_CR_DDR_WARM_THRESHOLD_CH1_PCU_DIMM1_OFF                  ( 8)
+  #define PCU_CR_DDR_WARM_THRESHOLD_CH1_PCU_DIMM1_WID                  ( 8)
+  #define PCU_CR_DDR_WARM_THRESHOLD_CH1_PCU_DIMM1_MSK                  (0x0000FF00)
+  #define PCU_CR_DDR_WARM_THRESHOLD_CH1_PCU_DIMM1_MAX                  (0x000000FF)
+  #define PCU_CR_DDR_WARM_THRESHOLD_CH1_PCU_DIMM1_DEF                  (0x000000FF)
+
+#define PCU_CR_DDR_HOT_THRESHOLD_CH0_PCU_REG                         (0x00005898)
+  #define PCU_CR_DDR_HOT_THRESHOLD_CH0_PCU_DIMM0_OFF                   ( 0)
+  #define PCU_CR_DDR_HOT_THRESHOLD_CH0_PCU_DIMM0_WID                   ( 8)
+  #define PCU_CR_DDR_HOT_THRESHOLD_CH0_PCU_DIMM0_MSK                   (0x000000FF)
+  #define PCU_CR_DDR_HOT_THRESHOLD_CH0_PCU_DIMM0_MAX                   (0x000000FF)
+  #define PCU_CR_DDR_HOT_THRESHOLD_CH0_PCU_DIMM0_DEF                   (0x000000FF)
+  #define PCU_CR_DDR_HOT_THRESHOLD_CH0_PCU_DIMM1_OFF                   ( 8)
+  #define PCU_CR_DDR_HOT_THRESHOLD_CH0_PCU_DIMM1_WID                   ( 8)
+  #define PCU_CR_DDR_HOT_THRESHOLD_CH0_PCU_DIMM1_MSK                   (0x0000FF00)
+  #define PCU_CR_DDR_HOT_THRESHOLD_CH0_PCU_DIMM1_MAX                   (0x000000FF)
+  #define PCU_CR_DDR_HOT_THRESHOLD_CH0_PCU_DIMM1_DEF                   (0x000000FF)
+
+#define PCU_CR_DDR_HOT_THRESHOLD_CH1_PCU_REG                         (0x0000589C)
+  #define PCU_CR_DDR_HOT_THRESHOLD_CH1_PCU_DIMM0_OFF                   ( 0)
+  #define PCU_CR_DDR_HOT_THRESHOLD_CH1_PCU_DIMM0_WID                   ( 8)
+  #define PCU_CR_DDR_HOT_THRESHOLD_CH1_PCU_DIMM0_MSK                   (0x000000FF)
+  #define PCU_CR_DDR_HOT_THRESHOLD_CH1_PCU_DIMM0_MAX                   (0x000000FF)
+  #define PCU_CR_DDR_HOT_THRESHOLD_CH1_PCU_DIMM0_DEF                   (0x000000FF)
+  #define PCU_CR_DDR_HOT_THRESHOLD_CH1_PCU_DIMM1_OFF                   ( 8)
+  #define PCU_CR_DDR_HOT_THRESHOLD_CH1_PCU_DIMM1_WID                   ( 8)
+  #define PCU_CR_DDR_HOT_THRESHOLD_CH1_PCU_DIMM1_MSK                   (0x0000FF00)
+  #define PCU_CR_DDR_HOT_THRESHOLD_CH1_PCU_DIMM1_MAX                   (0x000000FF)
+  #define PCU_CR_DDR_HOT_THRESHOLD_CH1_PCU_DIMM1_DEF                   (0x000000FF)
+
+#define PCU_CR_DDR_THERM_CAMARILLO_INTERRUPT_PCU_REG                 (0x000058A0)
+  #define PCU_CR_DDR_THERM_CAMARILLO_INTERRUPT_PCU_ENABLE_WARM_INTERRUPT_OFF ( 0)
+  #define PCU_CR_DDR_THERM_CAMARILLO_INTERRUPT_PCU_ENABLE_WARM_INTERRUPT_WID ( 1)
+  #define PCU_CR_DDR_THERM_CAMARILLO_INTERRUPT_PCU_ENABLE_WARM_INTERRUPT_MSK (0x00000001)
+  #define PCU_CR_DDR_THERM_CAMARILLO_INTERRUPT_PCU_ENABLE_WARM_INTERRUPT_MAX (0x00000001)
+  #define PCU_CR_DDR_THERM_CAMARILLO_INTERRUPT_PCU_ENABLE_WARM_INTERRUPT_DEF (0x00000000)
+  #define PCU_CR_DDR_THERM_CAMARILLO_INTERRUPT_PCU_ENABLE_HOT_INTERRUPT_OFF ( 2)
+  #define PCU_CR_DDR_THERM_CAMARILLO_INTERRUPT_PCU_ENABLE_HOT_INTERRUPT_WID ( 1)
+  #define PCU_CR_DDR_THERM_CAMARILLO_INTERRUPT_PCU_ENABLE_HOT_INTERRUPT_MSK (0x00000004)
+  #define PCU_CR_DDR_THERM_CAMARILLO_INTERRUPT_PCU_ENABLE_HOT_INTERRUPT_MAX (0x00000001)
+  #define PCU_CR_DDR_THERM_CAMARILLO_INTERRUPT_PCU_ENABLE_HOT_INTERRUPT_DEF (0x00000000)
+  #define PCU_CR_DDR_THERM_CAMARILLO_INTERRUPT_PCU_ENABLE_2X_REFRESH_INTERRUPT_OFF ( 4)
+  #define PCU_CR_DDR_THERM_CAMARILLO_INTERRUPT_PCU_ENABLE_2X_REFRESH_INTERRUPT_WID ( 1)
+  #define PCU_CR_DDR_THERM_CAMARILLO_INTERRUPT_PCU_ENABLE_2X_REFRESH_INTERRUPT_MSK (0x00000010)
+  #define PCU_CR_DDR_THERM_CAMARILLO_INTERRUPT_PCU_ENABLE_2X_REFRESH_INTERRUPT_MAX (0x00000001)
+  #define PCU_CR_DDR_THERM_CAMARILLO_INTERRUPT_PCU_ENABLE_2X_REFRESH_INTERRUPT_DEF (0x00000000)
+  #define PCU_CR_DDR_THERM_CAMARILLO_INTERRUPT_PCU_ENABLE_THRESHOLD1_INTERRUPT_OFF ( 8)
+  #define PCU_CR_DDR_THERM_CAMARILLO_INTERRUPT_PCU_ENABLE_THRESHOLD1_INTERRUPT_WID ( 1)
+  #define PCU_CR_DDR_THERM_CAMARILLO_INTERRUPT_PCU_ENABLE_THRESHOLD1_INTERRUPT_MSK (0x00000100)
+  #define PCU_CR_DDR_THERM_CAMARILLO_INTERRUPT_PCU_ENABLE_THRESHOLD1_INTERRUPT_MAX (0x00000001)
+  #define PCU_CR_DDR_THERM_CAMARILLO_INTERRUPT_PCU_ENABLE_THRESHOLD1_INTERRUPT_DEF (0x00000000)
+  #define PCU_CR_DDR_THERM_CAMARILLO_INTERRUPT_PCU_ENABLE_THRESHOLD2_INTERRUPT_OFF (10)
+  #define PCU_CR_DDR_THERM_CAMARILLO_INTERRUPT_PCU_ENABLE_THRESHOLD2_INTERRUPT_WID ( 1)
+  #define PCU_CR_DDR_THERM_CAMARILLO_INTERRUPT_PCU_ENABLE_THRESHOLD2_INTERRUPT_MSK (0x00000400)
+  #define PCU_CR_DDR_THERM_CAMARILLO_INTERRUPT_PCU_ENABLE_THRESHOLD2_INTERRUPT_MAX (0x00000001)
+  #define PCU_CR_DDR_THERM_CAMARILLO_INTERRUPT_PCU_ENABLE_THRESHOLD2_INTERRUPT_DEF (0x00000000)
+  #define PCU_CR_DDR_THERM_CAMARILLO_INTERRUPT_PCU_POLICY_FREE_THRESHOLD1_OFF (16)
+  #define PCU_CR_DDR_THERM_CAMARILLO_INTERRUPT_PCU_POLICY_FREE_THRESHOLD1_WID ( 8)
+  #define PCU_CR_DDR_THERM_CAMARILLO_INTERRUPT_PCU_POLICY_FREE_THRESHOLD1_MSK (0x00FF0000)
+  #define PCU_CR_DDR_THERM_CAMARILLO_INTERRUPT_PCU_POLICY_FREE_THRESHOLD1_MAX (0x000000FF)
+  #define PCU_CR_DDR_THERM_CAMARILLO_INTERRUPT_PCU_POLICY_FREE_THRESHOLD1_DEF (0x00000000)
+  #define PCU_CR_DDR_THERM_CAMARILLO_INTERRUPT_PCU_POLICY_FREE_THRESHOLD2_OFF (24)
+  #define PCU_CR_DDR_THERM_CAMARILLO_INTERRUPT_PCU_POLICY_FREE_THRESHOLD2_WID ( 8)
+  #define PCU_CR_DDR_THERM_CAMARILLO_INTERRUPT_PCU_POLICY_FREE_THRESHOLD2_MSK (0xFF000000)
+  #define PCU_CR_DDR_THERM_CAMARILLO_INTERRUPT_PCU_POLICY_FREE_THRESHOLD2_MAX (0x000000FF)
+  #define PCU_CR_DDR_THERM_CAMARILLO_INTERRUPT_PCU_POLICY_FREE_THRESHOLD2_DEF (0x00000000)
+
+#define PCU_CR_DDR_VOLTAGE_PCU_REG                                   (0x000058A4)
+  #define PCU_CR_DDR_VOLTAGE_PCU_DDR_VOLTAGE_OFF                       ( 0)
+  #define PCU_CR_DDR_VOLTAGE_PCU_DDR_VOLTAGE_WID                       ( 3)
+  #define PCU_CR_DDR_VOLTAGE_PCU_DDR_VOLTAGE_MSK                       (0x00000007)
+  #define PCU_CR_DDR_VOLTAGE_PCU_DDR_VOLTAGE_MAX                       (0x00000007)
+  #define PCU_CR_DDR_VOLTAGE_PCU_DDR_VOLTAGE_DEF                       (0x00000000)
+
+#define PCU_CR_PACKAGE_THERM_MARGIN_PCU_REG                          (0x000058A8)
+  #define PCU_CR_PACKAGE_THERM_MARGIN_PCU_THERM_MARGIN_OFF             ( 0)
+  #define PCU_CR_PACKAGE_THERM_MARGIN_PCU_THERM_MARGIN_WID             (16)
+  #define PCU_CR_PACKAGE_THERM_MARGIN_PCU_THERM_MARGIN_MSK             (0x0000FFFF)
+  #define PCU_CR_PACKAGE_THERM_MARGIN_PCU_THERM_MARGIN_MAX             (0x0000FFFF)
+  #define PCU_CR_PACKAGE_THERM_MARGIN_PCU_THERM_MARGIN_DEF             (0x00007F00)
+
+#define PCU_CR_DDR_DIMM_TEMPERATURE_CH0_PCU_REG                      (0x000058B0)
+  #define PCU_CR_DDR_DIMM_TEMPERATURE_CH0_PCU_DIMM0_OFF                ( 0)
+  #define PCU_CR_DDR_DIMM_TEMPERATURE_CH0_PCU_DIMM0_WID                ( 8)
+  #define PCU_CR_DDR_DIMM_TEMPERATURE_CH0_PCU_DIMM0_MSK                (0x000000FF)
+  #define PCU_CR_DDR_DIMM_TEMPERATURE_CH0_PCU_DIMM0_MAX                (0x000000FF)
+  #define PCU_CR_DDR_DIMM_TEMPERATURE_CH0_PCU_DIMM0_DEF                (0x00000000)
+  #define PCU_CR_DDR_DIMM_TEMPERATURE_CH0_PCU_DIMM1_OFF                ( 8)
+  #define PCU_CR_DDR_DIMM_TEMPERATURE_CH0_PCU_DIMM1_WID                ( 8)
+  #define PCU_CR_DDR_DIMM_TEMPERATURE_CH0_PCU_DIMM1_MSK                (0x0000FF00)
+  #define PCU_CR_DDR_DIMM_TEMPERATURE_CH0_PCU_DIMM1_MAX                (0x000000FF)
+  #define PCU_CR_DDR_DIMM_TEMPERATURE_CH0_PCU_DIMM1_DEF                (0x00000000)
+
+#define PCU_CR_DDR_DIMM_TEMPERATURE_CH1_PCU_REG                      (0x000058B4)
+  #define PCU_CR_DDR_DIMM_TEMPERATURE_CH1_PCU_DIMM0_OFF                ( 0)
+  #define PCU_CR_DDR_DIMM_TEMPERATURE_CH1_PCU_DIMM0_WID                ( 8)
+  #define PCU_CR_DDR_DIMM_TEMPERATURE_CH1_PCU_DIMM0_MSK                (0x000000FF)
+  #define PCU_CR_DDR_DIMM_TEMPERATURE_CH1_PCU_DIMM0_MAX                (0x000000FF)
+  #define PCU_CR_DDR_DIMM_TEMPERATURE_CH1_PCU_DIMM0_DEF                (0x00000000)
+  #define PCU_CR_DDR_DIMM_TEMPERATURE_CH1_PCU_DIMM1_OFF                ( 8)
+  #define PCU_CR_DDR_DIMM_TEMPERATURE_CH1_PCU_DIMM1_WID                ( 8)
+  #define PCU_CR_DDR_DIMM_TEMPERATURE_CH1_PCU_DIMM1_MSK                (0x0000FF00)
+  #define PCU_CR_DDR_DIMM_TEMPERATURE_CH1_PCU_DIMM1_MAX                (0x000000FF)
+  #define PCU_CR_DDR_DIMM_TEMPERATURE_CH1_PCU_DIMM1_DEF                (0x00000000)
+
+#define PCU_CR_DDR_DIMM_HOTTEST_ABSOLUTE_PCU_REG                     (0x000058B8)
+  #define PCU_CR_DDR_DIMM_HOTTEST_ABSOLUTE_PCU_TEMPERATURE_OFF         ( 0)
+  #define PCU_CR_DDR_DIMM_HOTTEST_ABSOLUTE_PCU_TEMPERATURE_WID         ( 8)
+  #define PCU_CR_DDR_DIMM_HOTTEST_ABSOLUTE_PCU_TEMPERATURE_MSK         (0x000000FF)
+  #define PCU_CR_DDR_DIMM_HOTTEST_ABSOLUTE_PCU_TEMPERATURE_MAX         (0x000000FF)
+  #define PCU_CR_DDR_DIMM_HOTTEST_ABSOLUTE_PCU_TEMPERATURE_DEF         (0x00000000)
+
+#define PCU_CR_DDR_DIMM_HOTTEST_RELATIVE_PCU_REG                     (0x000058BC)
+  #define PCU_CR_DDR_DIMM_HOTTEST_RELATIVE_PCU_TEMPERATURE_OFF         ( 0)
+  #define PCU_CR_DDR_DIMM_HOTTEST_RELATIVE_PCU_TEMPERATURE_WID         ( 8)
+  #define PCU_CR_DDR_DIMM_HOTTEST_RELATIVE_PCU_TEMPERATURE_MSK         (0x000000FF)
+  #define PCU_CR_DDR_DIMM_HOTTEST_RELATIVE_PCU_TEMPERATURE_MAX         (0x000000FF)
+  #define PCU_CR_DDR_DIMM_HOTTEST_RELATIVE_PCU_TEMPERATURE_DEF         (0x0000007F)
+
+#define PCU_CR_DDR_THROTTLE_DURATION_CH0_PCU_REG                     (0x000058C0)
+  #define PCU_CR_DDR_THROTTLE_DURATION_CH0_PCU_DIMM0_OFF               ( 0)
+  #define PCU_CR_DDR_THROTTLE_DURATION_CH0_PCU_DIMM0_WID               (16)
+  #define PCU_CR_DDR_THROTTLE_DURATION_CH0_PCU_DIMM0_MSK               (0x0000FFFF)
+  #define PCU_CR_DDR_THROTTLE_DURATION_CH0_PCU_DIMM0_MAX               (0x0000FFFF)
+  #define PCU_CR_DDR_THROTTLE_DURATION_CH0_PCU_DIMM0_DEF               (0x00000000)
+  #define PCU_CR_DDR_THROTTLE_DURATION_CH0_PCU_DIMM1_OFF               (16)
+  #define PCU_CR_DDR_THROTTLE_DURATION_CH0_PCU_DIMM1_WID               (16)
+  #define PCU_CR_DDR_THROTTLE_DURATION_CH0_PCU_DIMM1_MSK               (0xFFFF0000)
+  #define PCU_CR_DDR_THROTTLE_DURATION_CH0_PCU_DIMM1_MAX               (0x0000FFFF)
+  #define PCU_CR_DDR_THROTTLE_DURATION_CH0_PCU_DIMM1_DEF               (0x00000000)
+
+#define PCU_CR_DDR_THROTTLE_DURATION_CH1_PCU_REG                     (0x000058C8)
+  #define PCU_CR_DDR_THROTTLE_DURATION_CH1_PCU_DIMM0_OFF               ( 0)
+  #define PCU_CR_DDR_THROTTLE_DURATION_CH1_PCU_DIMM0_WID               (16)
+  #define PCU_CR_DDR_THROTTLE_DURATION_CH1_PCU_DIMM0_MSK               (0x0000FFFF)
+  #define PCU_CR_DDR_THROTTLE_DURATION_CH1_PCU_DIMM0_MAX               (0x0000FFFF)
+  #define PCU_CR_DDR_THROTTLE_DURATION_CH1_PCU_DIMM0_DEF               (0x00000000)
+  #define PCU_CR_DDR_THROTTLE_DURATION_CH1_PCU_DIMM1_OFF               (16)
+  #define PCU_CR_DDR_THROTTLE_DURATION_CH1_PCU_DIMM1_WID               (16)
+  #define PCU_CR_DDR_THROTTLE_DURATION_CH1_PCU_DIMM1_MSK               (0xFFFF0000)
+  #define PCU_CR_DDR_THROTTLE_DURATION_CH1_PCU_DIMM1_MAX               (0x0000FFFF)
+  #define PCU_CR_DDR_THROTTLE_DURATION_CH1_PCU_DIMM1_DEF               (0x00000000)
+
+#define PCU_CR_DDR_WARM_BUDGET_CH0_PCU_REG                           (0x000058D0)
+  #define PCU_CR_DDR_WARM_BUDGET_CH0_PCU_DIMM0_OFF                     ( 0)
+  #define PCU_CR_DDR_WARM_BUDGET_CH0_PCU_DIMM0_WID                     ( 8)
+  #define PCU_CR_DDR_WARM_BUDGET_CH0_PCU_DIMM0_MSK                     (0x000000FF)
+  #define PCU_CR_DDR_WARM_BUDGET_CH0_PCU_DIMM0_MAX                     (0x000000FF)
+  #define PCU_CR_DDR_WARM_BUDGET_CH0_PCU_DIMM0_DEF                     (0x000000FF)
+  #define PCU_CR_DDR_WARM_BUDGET_CH0_PCU_DIMM1_OFF                     ( 8)
+  #define PCU_CR_DDR_WARM_BUDGET_CH0_PCU_DIMM1_WID                     ( 8)
+  #define PCU_CR_DDR_WARM_BUDGET_CH0_PCU_DIMM1_MSK                     (0x0000FF00)
+  #define PCU_CR_DDR_WARM_BUDGET_CH0_PCU_DIMM1_MAX                     (0x000000FF)
+  #define PCU_CR_DDR_WARM_BUDGET_CH0_PCU_DIMM1_DEF                     (0x000000FF)
+
+#define PCU_CR_DDR_WARM_BUDGET_CH1_PCU_REG                           (0x000058D4)
+  #define PCU_CR_DDR_WARM_BUDGET_CH1_PCU_DIMM0_OFF                     ( 0)
+  #define PCU_CR_DDR_WARM_BUDGET_CH1_PCU_DIMM0_WID                     ( 8)
+  #define PCU_CR_DDR_WARM_BUDGET_CH1_PCU_DIMM0_MSK                     (0x000000FF)
+  #define PCU_CR_DDR_WARM_BUDGET_CH1_PCU_DIMM0_MAX                     (0x000000FF)
+  #define PCU_CR_DDR_WARM_BUDGET_CH1_PCU_DIMM0_DEF                     (0x000000FF)
+  #define PCU_CR_DDR_WARM_BUDGET_CH1_PCU_DIMM1_OFF                     ( 8)
+  #define PCU_CR_DDR_WARM_BUDGET_CH1_PCU_DIMM1_WID                     ( 8)
+  #define PCU_CR_DDR_WARM_BUDGET_CH1_PCU_DIMM1_MSK                     (0x0000FF00)
+  #define PCU_CR_DDR_WARM_BUDGET_CH1_PCU_DIMM1_MAX                     (0x000000FF)
+  #define PCU_CR_DDR_WARM_BUDGET_CH1_PCU_DIMM1_DEF                     (0x000000FF)
+
+#define PCU_CR_DDR_HOT_BUDGET_CH0_PCU_REG                            (0x000058D8)
+  #define PCU_CR_DDR_HOT_BUDGET_CH0_PCU_DIMM0_OFF                      ( 0)
+  #define PCU_CR_DDR_HOT_BUDGET_CH0_PCU_DIMM0_WID                      ( 8)
+  #define PCU_CR_DDR_HOT_BUDGET_CH0_PCU_DIMM0_MSK                      (0x000000FF)
+  #define PCU_CR_DDR_HOT_BUDGET_CH0_PCU_DIMM0_MAX                      (0x000000FF)
+  #define PCU_CR_DDR_HOT_BUDGET_CH0_PCU_DIMM0_DEF                      (0x000000FF)
+  #define PCU_CR_DDR_HOT_BUDGET_CH0_PCU_DIMM1_OFF                      ( 8)
+  #define PCU_CR_DDR_HOT_BUDGET_CH0_PCU_DIMM1_WID                      ( 8)
+  #define PCU_CR_DDR_HOT_BUDGET_CH0_PCU_DIMM1_MSK                      (0x0000FF00)
+  #define PCU_CR_DDR_HOT_BUDGET_CH0_PCU_DIMM1_MAX                      (0x000000FF)
+  #define PCU_CR_DDR_HOT_BUDGET_CH0_PCU_DIMM1_DEF                      (0x000000FF)
+
+#define PCU_CR_DDR_HOT_BUDGET_CH1_PCU_REG                            (0x000058DC)
+  #define PCU_CR_DDR_HOT_BUDGET_CH1_PCU_DIMM0_OFF                      ( 0)
+  #define PCU_CR_DDR_HOT_BUDGET_CH1_PCU_DIMM0_WID                      ( 8)
+  #define PCU_CR_DDR_HOT_BUDGET_CH1_PCU_DIMM0_MSK                      (0x000000FF)
+  #define PCU_CR_DDR_HOT_BUDGET_CH1_PCU_DIMM0_MAX                      (0x000000FF)
+  #define PCU_CR_DDR_HOT_BUDGET_CH1_PCU_DIMM0_DEF                      (0x000000FF)
+  #define PCU_CR_DDR_HOT_BUDGET_CH1_PCU_DIMM1_OFF                      ( 8)
+  #define PCU_CR_DDR_HOT_BUDGET_CH1_PCU_DIMM1_WID                      ( 8)
+  #define PCU_CR_DDR_HOT_BUDGET_CH1_PCU_DIMM1_MSK                      (0x0000FF00)
+  #define PCU_CR_DDR_HOT_BUDGET_CH1_PCU_DIMM1_MAX                      (0x000000FF)
+  #define PCU_CR_DDR_HOT_BUDGET_CH1_PCU_DIMM1_DEF                      (0x000000FF)
+
+#define PCU_CR_DDR_RAPL_LIMIT_PCU_REG                                (0x000058E0)
+  #define PCU_CR_DDR_RAPL_LIMIT_PCU_LIMIT1_POWER_OFF                   ( 0)
+  #define PCU_CR_DDR_RAPL_LIMIT_PCU_LIMIT1_POWER_WID                   (15)
+  #define PCU_CR_DDR_RAPL_LIMIT_PCU_LIMIT1_POWER_MSK                   (0x00007FFF)
+  #define PCU_CR_DDR_RAPL_LIMIT_PCU_LIMIT1_POWER_MAX                   (0x00007FFF)
+  #define PCU_CR_DDR_RAPL_LIMIT_PCU_LIMIT1_POWER_DEF                   (0x00000000)
+  #define PCU_CR_DDR_RAPL_LIMIT_PCU_LIMIT1_ENABLE_OFF                  (15)
+  #define PCU_CR_DDR_RAPL_LIMIT_PCU_LIMIT1_ENABLE_WID                  ( 1)
+  #define PCU_CR_DDR_RAPL_LIMIT_PCU_LIMIT1_ENABLE_MSK                  (0x00008000)
+  #define PCU_CR_DDR_RAPL_LIMIT_PCU_LIMIT1_ENABLE_MAX                  (0x00000001)
+  #define PCU_CR_DDR_RAPL_LIMIT_PCU_LIMIT1_ENABLE_DEF                  (0x00000000)
+  #define PCU_CR_DDR_RAPL_LIMIT_PCU_LIMIT1_TIME_WINDOW_Y_OFF           (17)
+  #define PCU_CR_DDR_RAPL_LIMIT_PCU_LIMIT1_TIME_WINDOW_Y_WID           ( 5)
+  #define PCU_CR_DDR_RAPL_LIMIT_PCU_LIMIT1_TIME_WINDOW_Y_MSK           (0x003E0000)
+  #define PCU_CR_DDR_RAPL_LIMIT_PCU_LIMIT1_TIME_WINDOW_Y_MAX           (0x0000001F)
+  #define PCU_CR_DDR_RAPL_LIMIT_PCU_LIMIT1_TIME_WINDOW_Y_DEF           (0x00000000)
+  #define PCU_CR_DDR_RAPL_LIMIT_PCU_LIMIT1_TIME_WINDOW_X_OFF           (22)
+  #define PCU_CR_DDR_RAPL_LIMIT_PCU_LIMIT1_TIME_WINDOW_X_WID           ( 2)
+  #define PCU_CR_DDR_RAPL_LIMIT_PCU_LIMIT1_TIME_WINDOW_X_MSK           (0x00C00000)
+  #define PCU_CR_DDR_RAPL_LIMIT_PCU_LIMIT1_TIME_WINDOW_X_MAX           (0x00000003)
+  #define PCU_CR_DDR_RAPL_LIMIT_PCU_LIMIT1_TIME_WINDOW_X_DEF           (0x00000000)
+  #define PCU_CR_DDR_RAPL_LIMIT_PCU_LIMIT2_POWER_OFF                   (32)
+  #define PCU_CR_DDR_RAPL_LIMIT_PCU_LIMIT2_POWER_WID                   (15)
+  #define PCU_CR_DDR_RAPL_LIMIT_PCU_LIMIT2_POWER_MSK                   (0x7FFF00000000)
+  #define PCU_CR_DDR_RAPL_LIMIT_PCU_LIMIT2_POWER_MAX                   (0x00007FFF)
+  #define PCU_CR_DDR_RAPL_LIMIT_PCU_LIMIT2_POWER_DEF                   (0x00000000)
+  #define PCU_CR_DDR_RAPL_LIMIT_PCU_LIMIT2_ENABLE_OFF                  (47)
+  #define PCU_CR_DDR_RAPL_LIMIT_PCU_LIMIT2_ENABLE_WID                  ( 1)
+  #define PCU_CR_DDR_RAPL_LIMIT_PCU_LIMIT2_ENABLE_MSK                  (0x800000000000)
+  #define PCU_CR_DDR_RAPL_LIMIT_PCU_LIMIT2_ENABLE_MAX                  (0x00000001)
+  #define PCU_CR_DDR_RAPL_LIMIT_PCU_LIMIT2_ENABLE_DEF                  (0x00000000)
+  #define PCU_CR_DDR_RAPL_LIMIT_PCU_LIMIT2_TIME_WINDOW_Y_OFF           (49)
+  #define PCU_CR_DDR_RAPL_LIMIT_PCU_LIMIT2_TIME_WINDOW_Y_WID           ( 5)
+  #define PCU_CR_DDR_RAPL_LIMIT_PCU_LIMIT2_TIME_WINDOW_Y_MSK           (0x3E000000000000)
+  #define PCU_CR_DDR_RAPL_LIMIT_PCU_LIMIT2_TIME_WINDOW_Y_MAX           (0x0000001F)
+  #define PCU_CR_DDR_RAPL_LIMIT_PCU_LIMIT2_TIME_WINDOW_Y_DEF           (0x00000000)
+  #define PCU_CR_DDR_RAPL_LIMIT_PCU_LIMIT2_TIME_WINDOW_X_OFF           (54)
+  #define PCU_CR_DDR_RAPL_LIMIT_PCU_LIMIT2_TIME_WINDOW_X_WID           ( 2)
+  #define PCU_CR_DDR_RAPL_LIMIT_PCU_LIMIT2_TIME_WINDOW_X_MSK           (0xC0000000000000)
+  #define PCU_CR_DDR_RAPL_LIMIT_PCU_LIMIT2_TIME_WINDOW_X_MAX           (0x00000003)
+  #define PCU_CR_DDR_RAPL_LIMIT_PCU_LIMIT2_TIME_WINDOW_X_DEF           (0x00000000)
+  #define PCU_CR_DDR_RAPL_LIMIT_PCU_LOCKED_OFF                         (63)
+  #define PCU_CR_DDR_RAPL_LIMIT_PCU_LOCKED_WID                         ( 1)
+  #define PCU_CR_DDR_RAPL_LIMIT_PCU_LOCKED_MSK                         (0x8000000000000000)
+  #define PCU_CR_DDR_RAPL_LIMIT_PCU_LOCKED_MAX                         (0x00000001)
+  #define PCU_CR_DDR_RAPL_LIMIT_PCU_LOCKED_DEF                         (0x00000000)
+
+#define PCU_CR_DDR_ENERGY_STATUS_PCU_REG                             (0x000058E8)
+  #define PCU_CR_DDR_ENERGY_STATUS_PCU_JOULES_CONSUMED_OFF             ( 0)
+  #define PCU_CR_DDR_ENERGY_STATUS_PCU_JOULES_CONSUMED_WID             (32)
+  #define PCU_CR_DDR_ENERGY_STATUS_PCU_JOULES_CONSUMED_MSK             (0xFFFFFFFF)
+  #define PCU_CR_DDR_ENERGY_STATUS_PCU_JOULES_CONSUMED_MAX             (0xFFFFFFFF)
+  #define PCU_CR_DDR_ENERGY_STATUS_PCU_JOULES_CONSUMED_DEF             (0x00000000)
+
+#define PCU_CR_DDR_RAPL_PERF_STATUS_PCU_REG                          (0x000058EC)
+  #define PCU_CR_DDR_RAPL_PERF_STATUS_PCU_DURATION_OFF                 ( 0)
+  #define PCU_CR_DDR_RAPL_PERF_STATUS_PCU_DURATION_WID                 (32)
+  #define PCU_CR_DDR_RAPL_PERF_STATUS_PCU_DURATION_MSK                 (0xFFFFFFFF)
+  #define PCU_CR_DDR_RAPL_PERF_STATUS_PCU_DURATION_MAX                 (0xFFFFFFFF)
+  #define PCU_CR_DDR_RAPL_PERF_STATUS_PCU_DURATION_DEF                 (0x00000000)
+
+#define PCU_CR_PACKAGE_RAPL_PERF_STATUS_PCU_REG                      (0x000058F0)
+  #define PCU_CR_PACKAGE_RAPL_PERF_STATUS_PCU_COUNTS_OFF               ( 0)
+  #define PCU_CR_PACKAGE_RAPL_PERF_STATUS_PCU_COUNTS_WID               (32)
+  #define PCU_CR_PACKAGE_RAPL_PERF_STATUS_PCU_COUNTS_MSK               (0xFFFFFFFF)
+  #define PCU_CR_PACKAGE_RAPL_PERF_STATUS_PCU_COUNTS_MAX               (0xFFFFFFFF)
+  #define PCU_CR_PACKAGE_RAPL_PERF_STATUS_PCU_COUNTS_DEF               (0x00000000)
+
+#define PCU_CR_GT_RATIOS_OVERRIDE_PCU_REG                            (0x000058F4)
+  #define PCU_CR_GT_RATIOS_OVERRIDE_PCU_IA_MIN_RATIO_REQUEST_OFF       ( 0)
+  #define PCU_CR_GT_RATIOS_OVERRIDE_PCU_IA_MIN_RATIO_REQUEST_WID       ( 8)
+  #define PCU_CR_GT_RATIOS_OVERRIDE_PCU_IA_MIN_RATIO_REQUEST_MSK       (0x000000FF)
+  #define PCU_CR_GT_RATIOS_OVERRIDE_PCU_IA_MIN_RATIO_REQUEST_MAX       (0x000000FF)
+  #define PCU_CR_GT_RATIOS_OVERRIDE_PCU_IA_MIN_RATIO_REQUEST_DEF       (0x00000000)
+  #define PCU_CR_GT_RATIOS_OVERRIDE_PCU_CLR_MIN_RATIO_REQUEST_OFF      ( 8)
+  #define PCU_CR_GT_RATIOS_OVERRIDE_PCU_CLR_MIN_RATIO_REQUEST_WID      ( 8)
+  #define PCU_CR_GT_RATIOS_OVERRIDE_PCU_CLR_MIN_RATIO_REQUEST_MSK      (0x0000FF00)
+  #define PCU_CR_GT_RATIOS_OVERRIDE_PCU_CLR_MIN_RATIO_REQUEST_MAX      (0x000000FF)
+  #define PCU_CR_GT_RATIOS_OVERRIDE_PCU_CLR_MIN_RATIO_REQUEST_DEF      (0x00000000)
+
+#define PCU_CR_PKGC_LTR_LATENCY_MEASUREMENTS_PCU_REG                 (0x000058F8)
+  #define PCU_CR_PKGC_LTR_LATENCY_MEASUREMENTS_PCU_DDR_ACCESS_TIME_OFF ( 0)
+  #define PCU_CR_PKGC_LTR_LATENCY_MEASUREMENTS_PCU_DDR_ACCESS_TIME_WID (14)
+  #define PCU_CR_PKGC_LTR_LATENCY_MEASUREMENTS_PCU_DDR_ACCESS_TIME_MSK (0x00003FFF)
+  #define PCU_CR_PKGC_LTR_LATENCY_MEASUREMENTS_PCU_DDR_ACCESS_TIME_MAX (0x00003FFF)
+  #define PCU_CR_PKGC_LTR_LATENCY_MEASUREMENTS_PCU_DDR_ACCESS_TIME_DEF (0x00000000)
+  #define PCU_CR_PKGC_LTR_LATENCY_MEASUREMENTS_PCU_RESERVED_OFF        (14)
+  #define PCU_CR_PKGC_LTR_LATENCY_MEASUREMENTS_PCU_RESERVED_WID        ( 1)
+  #define PCU_CR_PKGC_LTR_LATENCY_MEASUREMENTS_PCU_RESERVED_MSK        (0x00004000)
+  #define PCU_CR_PKGC_LTR_LATENCY_MEASUREMENTS_PCU_RESERVED_MAX        (0x00000001)
+  #define PCU_CR_PKGC_LTR_LATENCY_MEASUREMENTS_PCU_RESERVED_DEF        (0x00000000)
+  #define PCU_CR_PKGC_LTR_LATENCY_MEASUREMENTS_PCU_CLR_ACCESS_TIME_OFF (15)
+  #define PCU_CR_PKGC_LTR_LATENCY_MEASUREMENTS_PCU_CLR_ACCESS_TIME_WID (14)
+  #define PCU_CR_PKGC_LTR_LATENCY_MEASUREMENTS_PCU_CLR_ACCESS_TIME_MSK (0x1FFF8000)
+  #define PCU_CR_PKGC_LTR_LATENCY_MEASUREMENTS_PCU_CLR_ACCESS_TIME_MAX (0x00003FFF)
+  #define PCU_CR_PKGC_LTR_LATENCY_MEASUREMENTS_PCU_CLR_ACCESS_TIME_DEF (0x00000000)
+  #define PCU_CR_PKGC_LTR_LATENCY_MEASUREMENTS_PCU_NON_SNOOP_THRESHOLD_RESOLUTION_OFF (29)
+  #define PCU_CR_PKGC_LTR_LATENCY_MEASUREMENTS_PCU_NON_SNOOP_THRESHOLD_RESOLUTION_WID ( 1)
+  #define PCU_CR_PKGC_LTR_LATENCY_MEASUREMENTS_PCU_NON_SNOOP_THRESHOLD_RESOLUTION_MSK (0x20000000)
+  #define PCU_CR_PKGC_LTR_LATENCY_MEASUREMENTS_PCU_NON_SNOOP_THRESHOLD_RESOLUTION_MAX (0x00000001)
+  #define PCU_CR_PKGC_LTR_LATENCY_MEASUREMENTS_PCU_NON_SNOOP_THRESHOLD_RESOLUTION_DEF (0x00000000)
+  #define PCU_CR_PKGC_LTR_LATENCY_MEASUREMENTS_PCU_SLOW_SNOOP_THRESHOLD_RESOLUTION_OFF (30)
+  #define PCU_CR_PKGC_LTR_LATENCY_MEASUREMENTS_PCU_SLOW_SNOOP_THRESHOLD_RESOLUTION_WID ( 1)
+  #define PCU_CR_PKGC_LTR_LATENCY_MEASUREMENTS_PCU_SLOW_SNOOP_THRESHOLD_RESOLUTION_MSK (0x40000000)
+  #define PCU_CR_PKGC_LTR_LATENCY_MEASUREMENTS_PCU_SLOW_SNOOP_THRESHOLD_RESOLUTION_MAX (0x00000001)
+  #define PCU_CR_PKGC_LTR_LATENCY_MEASUREMENTS_PCU_SLOW_SNOOP_THRESHOLD_RESOLUTION_DEF (0x00000000)
+  #define PCU_CR_PKGC_LTR_LATENCY_MEASUREMENTS_PCU_FAST_SNOOP_THRESHOLD_RESOLUTION_OFF (31)
+  #define PCU_CR_PKGC_LTR_LATENCY_MEASUREMENTS_PCU_FAST_SNOOP_THRESHOLD_RESOLUTION_WID ( 1)
+  #define PCU_CR_PKGC_LTR_LATENCY_MEASUREMENTS_PCU_FAST_SNOOP_THRESHOLD_RESOLUTION_MSK (0x80000000)
+  #define PCU_CR_PKGC_LTR_LATENCY_MEASUREMENTS_PCU_FAST_SNOOP_THRESHOLD_RESOLUTION_MAX (0x00000001)
+  #define PCU_CR_PKGC_LTR_LATENCY_MEASUREMENTS_PCU_FAST_SNOOP_THRESHOLD_RESOLUTION_DEF (0x00000000)
+
+#define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_REG                         (0x000058FC)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_PROCHOT_STATUS_OFF          ( 0)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_PROCHOT_STATUS_WID          ( 1)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_PROCHOT_STATUS_MSK          (0x00000001)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_PROCHOT_STATUS_MAX          (0x00000001)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_PROCHOT_STATUS_DEF          (0x00000000)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_THERMAL_STATUS_OFF          ( 1)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_THERMAL_STATUS_WID          ( 1)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_THERMAL_STATUS_MSK          (0x00000002)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_THERMAL_STATUS_MAX          (0x00000001)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_THERMAL_STATUS_DEF          (0x00000000)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_SPARE_IA_2_OFF              ( 2)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_SPARE_IA_2_WID              ( 1)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_SPARE_IA_2_MSK              (0x00000004)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_SPARE_IA_2_MAX              (0x00000001)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_SPARE_IA_2_DEF              (0x00000000)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_PBM_PL1_STATUS_OFF          ( 3)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_PBM_PL1_STATUS_WID          ( 1)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_PBM_PL1_STATUS_MSK          (0x00000008)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_PBM_PL1_STATUS_MAX          (0x00000001)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_PBM_PL1_STATUS_DEF          (0x00000000)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_PBM_PL2_STATUS_OFF          ( 4)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_PBM_PL2_STATUS_WID          ( 1)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_PBM_PL2_STATUS_MSK          (0x00000010)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_PBM_PL2_STATUS_MAX          (0x00000001)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_PBM_PL2_STATUS_DEF          (0x00000000)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_PBM_PLIA_STATUS_OFF         ( 5)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_PBM_PLIA_STATUS_WID         ( 1)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_PBM_PLIA_STATUS_MSK         (0x00000020)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_PBM_PLIA_STATUS_MAX         (0x00000001)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_PBM_PLIA_STATUS_DEF         (0x00000000)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_SPARE_IA_6_OFF              ( 6)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_SPARE_IA_6_WID              ( 1)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_SPARE_IA_6_MSK              (0x00000040)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_SPARE_IA_6_MAX              (0x00000001)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_SPARE_IA_6_DEF              (0x00000000)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_GTDRIVER_STATUS_OFF         ( 7)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_GTDRIVER_STATUS_WID         ( 1)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_GTDRIVER_STATUS_MSK         (0x00000080)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_GTDRIVER_STATUS_MAX         (0x00000001)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_GTDRIVER_STATUS_DEF         (0x00000000)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_VR_THERMALERT_STATUS_OFF    ( 8)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_VR_THERMALERT_STATUS_WID    ( 1)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_VR_THERMALERT_STATUS_MSK    (0x00000100)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_VR_THERMALERT_STATUS_MAX    (0x00000001)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_VR_THERMALERT_STATUS_DEF    (0x00000000)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_FUSE_MAX_TURBO_LIMIT_STATUS_OFF ( 9)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_FUSE_MAX_TURBO_LIMIT_STATUS_WID ( 1)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_FUSE_MAX_TURBO_LIMIT_STATUS_MSK (0x00000200)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_FUSE_MAX_TURBO_LIMIT_STATUS_MAX (0x00000001)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_FUSE_MAX_TURBO_LIMIT_STATUS_DEF (0x00000000)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_EDP_ICC_STATUS_OFF          (10)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_EDP_ICC_STATUS_WID          ( 1)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_EDP_ICC_STATUS_MSK          (0x00000400)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_EDP_ICC_STATUS_MAX          (0x00000001)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_EDP_ICC_STATUS_DEF          (0x00000000)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_TURBO_ATTEN_STATUS_OFF      (11)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_TURBO_ATTEN_STATUS_WID      ( 1)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_TURBO_ATTEN_STATUS_MSK      (0x00000800)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_TURBO_ATTEN_STATUS_MAX      (0x00000001)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_TURBO_ATTEN_STATUS_DEF      (0x00000000)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_SPARE_IA_12_OFF             (12)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_SPARE_IA_12_WID             ( 1)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_SPARE_IA_12_MSK             (0x00001000)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_SPARE_IA_12_MAX             (0x00000001)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_SPARE_IA_12_DEF             (0x00000000)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_SPARE_IA_13_OFF             (13)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_SPARE_IA_13_WID             ( 1)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_SPARE_IA_13_MSK             (0x00002000)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_SPARE_IA_13_MAX             (0x00000001)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_SPARE_IA_13_DEF             (0x00000000)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_SPARE_IA_14_OFF             (14)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_SPARE_IA_14_WID             ( 1)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_SPARE_IA_14_MSK             (0x00004000)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_SPARE_IA_14_MAX             (0x00000001)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_SPARE_IA_14_DEF             (0x00000000)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_SPARE_IA_15_OFF             (15)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_SPARE_IA_15_WID             ( 1)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_SPARE_IA_15_MSK             (0x00008000)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_SPARE_IA_15_MAX             (0x00000001)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_SPARE_IA_15_DEF             (0x00000000)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_PROCHOT_LOG_OFF             (16)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_PROCHOT_LOG_WID             ( 1)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_PROCHOT_LOG_MSK             (0x00010000)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_PROCHOT_LOG_MAX             (0x00000001)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_PROCHOT_LOG_DEF             (0x00000000)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_THERMAL_LOG_OFF             (17)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_THERMAL_LOG_WID             ( 1)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_THERMAL_LOG_MSK             (0x00020000)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_THERMAL_LOG_MAX             (0x00000001)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_THERMAL_LOG_DEF             (0x00000000)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_SPARE_IA_LOG_2_OFF          (18)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_SPARE_IA_LOG_2_WID          ( 1)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_SPARE_IA_LOG_2_MSK          (0x00040000)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_SPARE_IA_LOG_2_MAX          (0x00000001)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_SPARE_IA_LOG_2_DEF          (0x00000000)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_PBM_PL1_LOG_OFF             (19)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_PBM_PL1_LOG_WID             ( 1)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_PBM_PL1_LOG_MSK             (0x00080000)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_PBM_PL1_LOG_MAX             (0x00000001)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_PBM_PL1_LOG_DEF             (0x00000000)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_PBM_PL2_LOG_OFF             (20)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_PBM_PL2_LOG_WID             ( 1)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_PBM_PL2_LOG_MSK             (0x00100000)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_PBM_PL2_LOG_MAX             (0x00000001)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_PBM_PL2_LOG_DEF             (0x00000000)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_PBM_PLIA_LOG_OFF            (21)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_PBM_PLIA_LOG_WID            ( 1)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_PBM_PLIA_LOG_MSK            (0x00200000)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_PBM_PLIA_LOG_MAX            (0x00000001)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_PBM_PLIA_LOG_DEF            (0x00000000)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_SPARE_IA_LOG_6_OFF          (22)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_SPARE_IA_LOG_6_WID          ( 1)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_SPARE_IA_LOG_6_MSK          (0x00400000)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_SPARE_IA_LOG_6_MAX          (0x00000001)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_SPARE_IA_LOG_6_DEF          (0x00000000)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_GTDRIVER_LOG_OFF            (23)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_GTDRIVER_LOG_WID            ( 1)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_GTDRIVER_LOG_MSK            (0x00800000)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_GTDRIVER_LOG_MAX            (0x00000001)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_GTDRIVER_LOG_DEF            (0x00000000)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_VR_THERMALERT_LOG_OFF       (24)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_VR_THERMALERT_LOG_WID       ( 1)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_VR_THERMALERT_LOG_MSK       (0x01000000)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_VR_THERMALERT_LOG_MAX       (0x00000001)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_VR_THERMALERT_LOG_DEF       (0x00000000)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_FUSE_MAX_TURBO_LIMIT_LOG_OFF (25)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_FUSE_MAX_TURBO_LIMIT_LOG_WID ( 1)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_FUSE_MAX_TURBO_LIMIT_LOG_MSK (0x02000000)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_FUSE_MAX_TURBO_LIMIT_LOG_MAX (0x00000001)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_FUSE_MAX_TURBO_LIMIT_LOG_DEF (0x00000000)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_EDP_ICC_LOG_OFF             (26)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_EDP_ICC_LOG_WID             ( 1)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_EDP_ICC_LOG_MSK             (0x04000000)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_EDP_ICC_LOG_MAX             (0x00000001)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_EDP_ICC_LOG_DEF             (0x00000000)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_TURBO_ATTEN_LOG_OFF         (27)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_TURBO_ATTEN_LOG_WID         ( 1)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_TURBO_ATTEN_LOG_MSK         (0x08000000)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_TURBO_ATTEN_LOG_MAX         (0x00000001)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_TURBO_ATTEN_LOG_DEF         (0x00000000)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_SPARE_IA_LOG_12_OFF         (28)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_SPARE_IA_LOG_12_WID         ( 1)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_SPARE_IA_LOG_12_MSK         (0x10000000)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_SPARE_IA_LOG_12_MAX         (0x00000001)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_SPARE_IA_LOG_12_DEF         (0x00000000)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_SPARE_IA_LOG_13_OFF         (29)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_SPARE_IA_LOG_13_WID         ( 1)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_SPARE_IA_LOG_13_MSK         (0x20000000)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_SPARE_IA_LOG_13_MAX         (0x00000001)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_SPARE_IA_LOG_13_DEF         (0x00000000)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_SPARE_IA_LOG_14_OFF         (30)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_SPARE_IA_LOG_14_WID         ( 1)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_SPARE_IA_LOG_14_MSK         (0x40000000)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_SPARE_IA_LOG_14_MAX         (0x00000001)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_SPARE_IA_LOG_14_DEF         (0x00000000)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_SPARE_IA_LOG_15_OFF         (31)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_SPARE_IA_LOG_15_WID         ( 1)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_SPARE_IA_LOG_15_MSK         (0x80000000)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_SPARE_IA_LOG_15_MAX         (0x00000001)
+  #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_SPARE_IA_LOG_15_DEF         (0x00000000)
+
+#define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_REG                         (0x00005900)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_PROCHOT_STATUS_OFF          ( 0)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_PROCHOT_STATUS_WID          ( 1)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_PROCHOT_STATUS_MSK          (0x00000001)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_PROCHOT_STATUS_MAX          (0x00000001)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_PROCHOT_STATUS_DEF          (0x00000000)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_THERMAL_STATUS_OFF          ( 1)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_THERMAL_STATUS_WID          ( 1)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_THERMAL_STATUS_MSK          (0x00000002)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_THERMAL_STATUS_MAX          (0x00000001)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_THERMAL_STATUS_DEF          (0x00000000)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_2_OFF              ( 2)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_2_WID              ( 1)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_2_MSK              (0x00000004)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_2_MAX              (0x00000001)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_2_DEF              (0x00000000)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_PBM_PL1_STATUS_OFF          ( 3)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_PBM_PL1_STATUS_WID          ( 1)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_PBM_PL1_STATUS_MSK          (0x00000008)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_PBM_PL1_STATUS_MAX          (0x00000001)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_PBM_PL1_STATUS_DEF          (0x00000000)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_PBM_PL2_STATUS_OFF          ( 4)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_PBM_PL2_STATUS_WID          ( 1)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_PBM_PL2_STATUS_MSK          (0x00000010)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_PBM_PL2_STATUS_MAX          (0x00000001)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_PBM_PL2_STATUS_DEF          (0x00000000)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_PBM_PLGT_STATUS_OFF         ( 5)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_PBM_PLGT_STATUS_WID         ( 1)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_PBM_PLGT_STATUS_MSK         (0x00000020)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_PBM_PLGT_STATUS_MAX         (0x00000001)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_PBM_PLGT_STATUS_DEF         (0x00000000)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_6_OFF              ( 6)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_6_WID              ( 1)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_6_MSK              (0x00000040)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_6_MAX              (0x00000001)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_6_DEF              (0x00000000)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_7_OFF              ( 7)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_7_WID              ( 1)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_7_MSK              (0x00000080)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_7_MAX              (0x00000001)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_7_DEF              (0x00000000)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_VR_THERMALERT_STATUS_OFF    ( 8)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_VR_THERMALERT_STATUS_WID    ( 1)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_VR_THERMALERT_STATUS_MSK    (0x00000100)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_VR_THERMALERT_STATUS_MAX    (0x00000001)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_VR_THERMALERT_STATUS_DEF    (0x00000000)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_9_OFF              ( 9)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_9_WID              ( 1)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_9_MSK              (0x00000200)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_9_MAX              (0x00000001)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_9_DEF              (0x00000000)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_EDP_ICC_STATUS_OFF          (10)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_EDP_ICC_STATUS_WID          ( 1)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_EDP_ICC_STATUS_MSK          (0x00000400)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_EDP_ICC_STATUS_MAX          (0x00000001)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_EDP_ICC_STATUS_DEF          (0x00000000)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_11_OFF             (11)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_11_WID             ( 1)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_11_MSK             (0x00000800)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_11_MAX             (0x00000001)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_11_DEF             (0x00000000)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_12_OFF             (12)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_12_WID             ( 1)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_12_MSK             (0x00001000)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_12_MAX             (0x00000001)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_12_DEF             (0x00000000)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_13_OFF             (13)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_13_WID             ( 1)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_13_MSK             (0x00002000)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_13_MAX             (0x00000001)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_13_DEF             (0x00000000)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_14_OFF             (14)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_14_WID             ( 1)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_14_MSK             (0x00004000)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_14_MAX             (0x00000001)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_14_DEF             (0x00000000)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_15_OFF             (15)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_15_WID             ( 1)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_15_MSK             (0x00008000)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_15_MAX             (0x00000001)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_15_DEF             (0x00000000)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_PROCHOT_LOG_OFF             (16)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_PROCHOT_LOG_WID             ( 1)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_PROCHOT_LOG_MSK             (0x00010000)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_PROCHOT_LOG_MAX             (0x00000001)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_PROCHOT_LOG_DEF             (0x00000000)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_THERMAL_LOG_OFF             (17)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_THERMAL_LOG_WID             ( 1)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_THERMAL_LOG_MSK             (0x00020000)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_THERMAL_LOG_MAX             (0x00000001)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_THERMAL_LOG_DEF             (0x00000000)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_LOG_2_OFF          (18)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_LOG_2_WID          ( 1)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_LOG_2_MSK          (0x00040000)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_LOG_2_MAX          (0x00000001)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_LOG_2_DEF          (0x00000000)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_PBM_PL1_LOG_OFF             (19)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_PBM_PL1_LOG_WID             ( 1)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_PBM_PL1_LOG_MSK             (0x00080000)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_PBM_PL1_LOG_MAX             (0x00000001)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_PBM_PL1_LOG_DEF             (0x00000000)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_PBM_PL2_LOG_OFF             (20)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_PBM_PL2_LOG_WID             ( 1)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_PBM_PL2_LOG_MSK             (0x00100000)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_PBM_PL2_LOG_MAX             (0x00000001)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_PBM_PL2_LOG_DEF             (0x00000000)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_PBM_PLGT_LOG_OFF            (21)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_PBM_PLGT_LOG_WID            ( 1)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_PBM_PLGT_LOG_MSK            (0x00200000)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_PBM_PLGT_LOG_MAX            (0x00000001)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_PBM_PLGT_LOG_DEF            (0x00000000)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_LOG_6_OFF          (22)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_LOG_6_WID          ( 1)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_LOG_6_MSK          (0x00400000)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_LOG_6_MAX          (0x00000001)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_LOG_6_DEF          (0x00000000)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_LOG_7_OFF          (23)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_LOG_7_WID          ( 1)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_LOG_7_MSK          (0x00800000)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_LOG_7_MAX          (0x00000001)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_LOG_7_DEF          (0x00000000)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_VR_THERMALERT_LOG_OFF       (24)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_VR_THERMALERT_LOG_WID       ( 1)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_VR_THERMALERT_LOG_MSK       (0x01000000)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_VR_THERMALERT_LOG_MAX       (0x00000001)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_VR_THERMALERT_LOG_DEF       (0x00000000)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_LOG_9_OFF          (25)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_LOG_9_WID          ( 1)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_LOG_9_MSK          (0x02000000)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_LOG_9_MAX          (0x00000001)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_LOG_9_DEF          (0x00000000)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_EDP_ICC_LOG_OFF             (26)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_EDP_ICC_LOG_WID             ( 1)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_EDP_ICC_LOG_MSK             (0x04000000)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_EDP_ICC_LOG_MAX             (0x00000001)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_EDP_ICC_LOG_DEF             (0x00000000)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_LOG_11_OFF         (27)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_LOG_11_WID         ( 1)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_LOG_11_MSK         (0x08000000)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_LOG_11_MAX         (0x00000001)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_LOG_11_DEF         (0x00000000)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_LOG_12_OFF         (28)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_LOG_12_WID         ( 1)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_LOG_12_MSK         (0x10000000)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_LOG_12_MAX         (0x00000001)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_LOG_12_DEF         (0x00000000)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_LOG_13_OFF         (29)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_LOG_13_WID         ( 1)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_LOG_13_MSK         (0x20000000)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_LOG_13_MAX         (0x00000001)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_LOG_13_DEF         (0x00000000)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_LOG_14_OFF         (30)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_LOG_14_WID         ( 1)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_LOG_14_MSK         (0x40000000)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_LOG_14_MAX         (0x00000001)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_LOG_14_DEF         (0x00000000)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_LOG_15_OFF         (31)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_LOG_15_WID         ( 1)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_LOG_15_MSK         (0x80000000)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_LOG_15_MAX         (0x00000001)
+  #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_LOG_15_DEF         (0x00000000)
+
+#define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_REG                        (0x00005904)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_PROCHOT_STATUS_OFF         ( 0)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_PROCHOT_STATUS_WID         ( 1)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_PROCHOT_STATUS_MSK         (0x00000001)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_PROCHOT_STATUS_MAX         (0x00000001)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_PROCHOT_STATUS_DEF         (0x00000000)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_THERMAL_STATUS_OFF         ( 1)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_THERMAL_STATUS_WID         ( 1)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_THERMAL_STATUS_MSK         (0x00000002)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_THERMAL_STATUS_MAX         (0x00000001)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_THERMAL_STATUS_DEF         (0x00000000)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_2_OFF            ( 2)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_2_WID            ( 1)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_2_MSK            (0x00000004)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_2_MAX            (0x00000001)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_2_DEF            (0x00000000)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_PBM_PL1_STATUS_OFF         ( 3)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_PBM_PL1_STATUS_WID         ( 1)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_PBM_PL1_STATUS_MSK         (0x00000008)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_PBM_PL1_STATUS_MAX         (0x00000001)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_PBM_PL1_STATUS_DEF         (0x00000000)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_PBM_PL2_STATUS_OFF         ( 4)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_PBM_PL2_STATUS_WID         ( 1)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_PBM_PL2_STATUS_MSK         (0x00000010)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_PBM_PL2_STATUS_MAX         (0x00000001)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_PBM_PL2_STATUS_DEF         (0x00000000)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_5_OFF            ( 5)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_5_WID            ( 1)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_5_MSK            (0x00000020)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_5_MAX            (0x00000001)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_5_DEF            (0x00000000)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_6_OFF            ( 6)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_6_WID            ( 1)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_6_MSK            (0x00000040)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_6_MAX            (0x00000001)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_6_DEF            (0x00000000)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_7_OFF            ( 7)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_7_WID            ( 1)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_7_MSK            (0x00000080)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_7_MAX            (0x00000001)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_7_DEF            (0x00000000)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_VR_THERMALERT_STATUS_OFF   ( 8)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_VR_THERMALERT_STATUS_WID   ( 1)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_VR_THERMALERT_STATUS_MSK   (0x00000100)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_VR_THERMALERT_STATUS_MAX   (0x00000001)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_VR_THERMALERT_STATUS_DEF   (0x00000000)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_9_OFF            ( 9)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_9_WID            ( 1)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_9_MSK            (0x00000200)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_9_MAX            (0x00000001)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_9_DEF            (0x00000000)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_EDP_ICC_STATUS_OFF         (10)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_EDP_ICC_STATUS_WID         ( 1)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_EDP_ICC_STATUS_MSK         (0x00000400)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_EDP_ICC_STATUS_MAX         (0x00000001)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_EDP_ICC_STATUS_DEF         (0x00000000)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_11_OFF           (11)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_11_WID           ( 1)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_11_MSK           (0x00000800)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_11_MAX           (0x00000001)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_11_DEF           (0x00000000)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_12_OFF           (12)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_12_WID           ( 1)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_12_MSK           (0x00001000)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_12_MAX           (0x00000001)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_12_DEF           (0x00000000)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_13_OFF           (13)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_13_WID           ( 1)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_13_MSK           (0x00002000)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_13_MAX           (0x00000001)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_13_DEF           (0x00000000)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_14_OFF           (14)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_14_WID           ( 1)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_14_MSK           (0x00004000)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_14_MAX           (0x00000001)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_14_DEF           (0x00000000)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_15_OFF           (15)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_15_WID           ( 1)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_15_MSK           (0x00008000)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_15_MAX           (0x00000001)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_15_DEF           (0x00000000)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_PROCHOT_LOG_OFF            (16)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_PROCHOT_LOG_WID            ( 1)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_PROCHOT_LOG_MSK            (0x00010000)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_PROCHOT_LOG_MAX            (0x00000001)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_PROCHOT_LOG_DEF            (0x00000000)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_THERMAL_LOG_OFF            (17)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_THERMAL_LOG_WID            ( 1)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_THERMAL_LOG_MSK            (0x00020000)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_THERMAL_LOG_MAX            (0x00000001)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_THERMAL_LOG_DEF            (0x00000000)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_LOG_2_OFF        (18)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_LOG_2_WID        ( 1)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_LOG_2_MSK        (0x00040000)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_LOG_2_MAX        (0x00000001)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_LOG_2_DEF        (0x00000000)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_PBM_PL1_LOG_OFF            (19)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_PBM_PL1_LOG_WID            ( 1)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_PBM_PL1_LOG_MSK            (0x00080000)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_PBM_PL1_LOG_MAX            (0x00000001)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_PBM_PL1_LOG_DEF            (0x00000000)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_PBM_PL2_LOG_OFF            (20)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_PBM_PL2_LOG_WID            ( 1)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_PBM_PL2_LOG_MSK            (0x00100000)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_PBM_PL2_LOG_MAX            (0x00000001)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_PBM_PL2_LOG_DEF            (0x00000000)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_LOG_5_OFF        (21)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_LOG_5_WID        ( 1)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_LOG_5_MSK        (0x00200000)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_LOG_5_MAX        (0x00000001)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_LOG_5_DEF        (0x00000000)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_LOG_6_OFF        (22)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_LOG_6_WID        ( 1)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_LOG_6_MSK        (0x00400000)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_LOG_6_MAX        (0x00000001)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_LOG_6_DEF        (0x00000000)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_LOG_7_OFF        (23)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_LOG_7_WID        ( 1)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_LOG_7_MSK        (0x00800000)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_LOG_7_MAX        (0x00000001)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_LOG_7_DEF        (0x00000000)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_VR_THERMALERT_LOG_OFF      (24)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_VR_THERMALERT_LOG_WID      ( 1)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_VR_THERMALERT_LOG_MSK      (0x01000000)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_VR_THERMALERT_LOG_MAX      (0x00000001)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_VR_THERMALERT_LOG_DEF      (0x00000000)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_LOG_9_OFF        (25)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_LOG_9_WID        ( 1)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_LOG_9_MSK        (0x02000000)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_LOG_9_MAX        (0x00000001)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_LOG_9_DEF        (0x00000000)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_EDP_ICC_LOG_OFF            (26)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_EDP_ICC_LOG_WID            ( 1)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_EDP_ICC_LOG_MSK            (0x04000000)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_EDP_ICC_LOG_MAX            (0x00000001)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_EDP_ICC_LOG_DEF            (0x00000000)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_LOG_11_OFF       (27)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_LOG_11_WID       ( 1)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_LOG_11_MSK       (0x08000000)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_LOG_11_MAX       (0x00000001)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_LOG_11_DEF       (0x00000000)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_LOG_12_OFF       (28)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_LOG_12_WID       ( 1)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_LOG_12_MSK       (0x10000000)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_LOG_12_MAX       (0x00000001)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_LOG_12_DEF       (0x00000000)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_LOG_13_OFF       (29)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_LOG_13_WID       ( 1)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_LOG_13_MSK       (0x20000000)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_LOG_13_MAX       (0x00000001)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_LOG_13_DEF       (0x00000000)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_LOG_14_OFF       (30)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_LOG_14_WID       ( 1)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_LOG_14_MSK       (0x40000000)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_LOG_14_MAX       (0x00000001)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_LOG_14_DEF       (0x00000000)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_LOG_15_OFF       (31)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_LOG_15_WID       ( 1)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_LOG_15_MSK       (0x80000000)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_LOG_15_MAX       (0x00000001)
+  #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_LOG_15_DEF       (0x00000000)
+
+#define PCU_CR_PRIP_TURBO_PLCY_PCU_REG                               (0x00005920)
+  #define PCU_CR_PRIP_TURBO_PLCY_PCU_PRIPTP_OFF                        ( 0)
+  #define PCU_CR_PRIP_TURBO_PLCY_PCU_PRIPTP_WID                        ( 5)
+  #define PCU_CR_PRIP_TURBO_PLCY_PCU_PRIPTP_MSK                        (0x0000001F)
+  #define PCU_CR_PRIP_TURBO_PLCY_PCU_PRIPTP_MAX                        (0x0000001F)
+  #define PCU_CR_PRIP_TURBO_PLCY_PCU_PRIPTP_DEF                        (0x00000000)
+
+#define PCU_CR_SECP_TURBO_PLCY_PCU_REG                               (0x00005924)
+  #define PCU_CR_SECP_TURBO_PLCY_PCU_SECPTP_OFF                        ( 0)
+  #define PCU_CR_SECP_TURBO_PLCY_PCU_SECPTP_WID                        ( 5)
+  #define PCU_CR_SECP_TURBO_PLCY_PCU_SECPTP_MSK                        (0x0000001F)
+  #define PCU_CR_SECP_TURBO_PLCY_PCU_SECPTP_MAX                        (0x0000001F)
+  #define PCU_CR_SECP_TURBO_PLCY_PCU_SECPTP_DEF                        (0x00000010)
+
+#define PCU_CR_PRIP_NRG_STTS_PCU_REG                                 (0x00005928)
+  #define PCU_CR_PRIP_NRG_STTS_PCU_DATA_OFF                            ( 0)
+  #define PCU_CR_PRIP_NRG_STTS_PCU_DATA_WID                            (32)
+  #define PCU_CR_PRIP_NRG_STTS_PCU_DATA_MSK                            (0xFFFFFFFF)
+  #define PCU_CR_PRIP_NRG_STTS_PCU_DATA_MAX                            (0xFFFFFFFF)
+  #define PCU_CR_PRIP_NRG_STTS_PCU_DATA_DEF                            (0x00000000)
+
+#define PCU_CR_SECP_NRG_STTS_PCU_REG                                 (0x0000592C)
+  #define PCU_CR_SECP_NRG_STTS_PCU_DATA_OFF                            ( 0)
+  #define PCU_CR_SECP_NRG_STTS_PCU_DATA_WID                            (32)
+  #define PCU_CR_SECP_NRG_STTS_PCU_DATA_MSK                            (0xFFFFFFFF)
+  #define PCU_CR_SECP_NRG_STTS_PCU_DATA_MAX                            (0xFFFFFFFF)
+  #define PCU_CR_SECP_NRG_STTS_PCU_DATA_DEF                            (0x00000000)
+
+#define PCU_CR_PACKAGE_POWER_SKU_PCU_REG                             (0x00005930)
+  #define PCU_CR_PACKAGE_POWER_SKU_PCU_PKG_TDP_OFF                     ( 0)
+  #define PCU_CR_PACKAGE_POWER_SKU_PCU_PKG_TDP_WID                     (15)
+  #define PCU_CR_PACKAGE_POWER_SKU_PCU_PKG_TDP_MSK                     (0x00007FFF)
+  #define PCU_CR_PACKAGE_POWER_SKU_PCU_PKG_TDP_MAX                     (0x00007FFF)
+  #define PCU_CR_PACKAGE_POWER_SKU_PCU_PKG_TDP_DEF                     (0x00000118)
+  #define PCU_CR_PACKAGE_POWER_SKU_PCU_PKG_MIN_PWR_OFF                 (16)
+  #define PCU_CR_PACKAGE_POWER_SKU_PCU_PKG_MIN_PWR_WID                 (15)
+  #define PCU_CR_PACKAGE_POWER_SKU_PCU_PKG_MIN_PWR_MSK                 (0x7FFF0000)
+  #define PCU_CR_PACKAGE_POWER_SKU_PCU_PKG_MIN_PWR_MAX                 (0x00007FFF)
+  #define PCU_CR_PACKAGE_POWER_SKU_PCU_PKG_MIN_PWR_DEF                 (0x00000060)
+  #define PCU_CR_PACKAGE_POWER_SKU_PCU_PKG_MAX_PWR_OFF                 (32)
+  #define PCU_CR_PACKAGE_POWER_SKU_PCU_PKG_MAX_PWR_WID                 (15)
+  #define PCU_CR_PACKAGE_POWER_SKU_PCU_PKG_MAX_PWR_MSK                 (0x7FFF00000000)
+  #define PCU_CR_PACKAGE_POWER_SKU_PCU_PKG_MAX_PWR_MAX                 (0x00007FFF)
+  #define PCU_CR_PACKAGE_POWER_SKU_PCU_PKG_MAX_PWR_DEF                 (0x00000240)
+  #define PCU_CR_PACKAGE_POWER_SKU_PCU_PKG_MAX_WIN_OFF                 (48)
+  #define PCU_CR_PACKAGE_POWER_SKU_PCU_PKG_MAX_WIN_WID                 ( 7)
+  #define PCU_CR_PACKAGE_POWER_SKU_PCU_PKG_MAX_WIN_MSK                 (0x7F000000000000)
+  #define PCU_CR_PACKAGE_POWER_SKU_PCU_PKG_MAX_WIN_MAX                 (0x0000007F)
+  #define PCU_CR_PACKAGE_POWER_SKU_PCU_PKG_MAX_WIN_DEF                 (0x00000012)
+
+#define PCU_CR_PACKAGE_POWER_SKU_UNIT_PCU_REG                        (0x00005938)
+  #define PCU_CR_PACKAGE_POWER_SKU_UNIT_PCU_PWR_UNIT_OFF               ( 0)
+  #define PCU_CR_PACKAGE_POWER_SKU_UNIT_PCU_PWR_UNIT_WID               ( 4)
+  #define PCU_CR_PACKAGE_POWER_SKU_UNIT_PCU_PWR_UNIT_MSK               (0x0000000F)
+  #define PCU_CR_PACKAGE_POWER_SKU_UNIT_PCU_PWR_UNIT_MAX               (0x0000000F)
+  #define PCU_CR_PACKAGE_POWER_SKU_UNIT_PCU_PWR_UNIT_DEF               (0x00000003)
+  #define PCU_CR_PACKAGE_POWER_SKU_UNIT_PCU_ENERGY_UNIT_OFF            ( 8)
+  #define PCU_CR_PACKAGE_POWER_SKU_UNIT_PCU_ENERGY_UNIT_WID            ( 5)
+  #define PCU_CR_PACKAGE_POWER_SKU_UNIT_PCU_ENERGY_UNIT_MSK            (0x00001F00)
+  #define PCU_CR_PACKAGE_POWER_SKU_UNIT_PCU_ENERGY_UNIT_MAX            (0x0000001F)
+  #define PCU_CR_PACKAGE_POWER_SKU_UNIT_PCU_ENERGY_UNIT_DEF            (0x0000000E)
+  #define PCU_CR_PACKAGE_POWER_SKU_UNIT_PCU_TIME_UNIT_OFF              (16)
+  #define PCU_CR_PACKAGE_POWER_SKU_UNIT_PCU_TIME_UNIT_WID              ( 4)
+  #define PCU_CR_PACKAGE_POWER_SKU_UNIT_PCU_TIME_UNIT_MSK              (0x000F0000)
+  #define PCU_CR_PACKAGE_POWER_SKU_UNIT_PCU_TIME_UNIT_MAX              (0x0000000F)
+  #define PCU_CR_PACKAGE_POWER_SKU_UNIT_PCU_TIME_UNIT_DEF              (0x0000000A)
+
+#define PCU_CR_PACKAGE_ENERGY_STATUS_PCU_REG                         (0x0000593C)
+  #define PCU_CR_PACKAGE_ENERGY_STATUS_PCU_DATA_OFF                    ( 0)
+  #define PCU_CR_PACKAGE_ENERGY_STATUS_PCU_DATA_WID                    (32)
+  #define PCU_CR_PACKAGE_ENERGY_STATUS_PCU_DATA_MSK                    (0xFFFFFFFF)
+  #define PCU_CR_PACKAGE_ENERGY_STATUS_PCU_DATA_MAX                    (0xFFFFFFFF)
+  #define PCU_CR_PACKAGE_ENERGY_STATUS_PCU_DATA_DEF                    (0x00000000)
+
+#define PCU_CR_GT_IO_BUSYNESS_PCU_REG                                (0x00005940)
+  #define PCU_CR_GT_IO_BUSYNESS_PCU_DATA_OFF                           ( 0)
+  #define PCU_CR_GT_IO_BUSYNESS_PCU_DATA_WID                           (32)
+  #define PCU_CR_GT_IO_BUSYNESS_PCU_DATA_MSK                           (0xFFFFFFFF)
+  #define PCU_CR_GT_IO_BUSYNESS_PCU_DATA_MAX                           (0xFFFFFFFF)
+  #define PCU_CR_GT_IO_BUSYNESS_PCU_DATA_DEF                           (0x00000000)
+
+#define PCU_CR_GT_VIDEO_BUSYNESS_PCU_REG                             (0x00005944)
+  #define PCU_CR_GT_VIDEO_BUSYNESS_PCU_DATA_OFF                        ( 0)
+  #define PCU_CR_GT_VIDEO_BUSYNESS_PCU_DATA_WID                        (32)
+  #define PCU_CR_GT_VIDEO_BUSYNESS_PCU_DATA_MSK                        (0xFFFFFFFF)
+  #define PCU_CR_GT_VIDEO_BUSYNESS_PCU_DATA_MAX                        (0xFFFFFFFF)
+  #define PCU_CR_GT_VIDEO_BUSYNESS_PCU_DATA_DEF                        (0x00000000)
+
+#define PCU_CR_GT_PERF_STATUS_PCU_REG                                (0x00005948)
+  #define PCU_CR_GT_PERF_STATUS_PCU_RP_STATE_VOLTAGE_OFF               ( 0)
+  #define PCU_CR_GT_PERF_STATUS_PCU_RP_STATE_VOLTAGE_WID               ( 8)
+  #define PCU_CR_GT_PERF_STATUS_PCU_RP_STATE_VOLTAGE_MSK               (0x000000FF)
+  #define PCU_CR_GT_PERF_STATUS_PCU_RP_STATE_VOLTAGE_MAX               (0x000000FF)
+  #define PCU_CR_GT_PERF_STATUS_PCU_RP_STATE_VOLTAGE_DEF               (0x00000000)
+  #define PCU_CR_GT_PERF_STATUS_PCU_RP_STATE_RATIO_OFF                 ( 8)
+  #define PCU_CR_GT_PERF_STATUS_PCU_RP_STATE_RATIO_WID                 ( 8)
+  #define PCU_CR_GT_PERF_STATUS_PCU_RP_STATE_RATIO_MSK                 (0x0000FF00)
+  #define PCU_CR_GT_PERF_STATUS_PCU_RP_STATE_RATIO_MAX                 (0x000000FF)
+  #define PCU_CR_GT_PERF_STATUS_PCU_RP_STATE_RATIO_DEF                 (0x00000000)
+
+#define PCU_CR_PLATFORM_ID_PCU_REG                                   (0x00005950)
+  #define PCU_CR_PLATFORM_ID_PCU_PLATFORMID_OFF                        (50)
+  #define PCU_CR_PLATFORM_ID_PCU_PLATFORMID_WID                        ( 3)
+  #define PCU_CR_PLATFORM_ID_PCU_PLATFORMID_MSK                        (0x1C000000000000)
+  #define PCU_CR_PLATFORM_ID_PCU_PLATFORMID_MAX                        (0x00000007)
+  #define PCU_CR_PLATFORM_ID_PCU_PLATFORMID_DEF                        (0x00000000)
+
+#define PCU_CR_PLATFORM_INFO_PCU_REG                                 (0x00005958)
+  #define PCU_CR_PLATFORM_INFO_PCU_MAX_NON_TURBO_LIM_RATIO_OFF         ( 8)
+  #define PCU_CR_PLATFORM_INFO_PCU_MAX_NON_TURBO_LIM_RATIO_WID         ( 8)
+  #define PCU_CR_PLATFORM_INFO_PCU_MAX_NON_TURBO_LIM_RATIO_MSK         (0x0000FF00)
+  #define PCU_CR_PLATFORM_INFO_PCU_MAX_NON_TURBO_LIM_RATIO_MAX         (0x000000FF)
+  #define PCU_CR_PLATFORM_INFO_PCU_MAX_NON_TURBO_LIM_RATIO_DEF         (0x00000000)
+  #define PCU_CR_PLATFORM_INFO_PCU_SMM_SAVE_CAP_OFF                    (16)
+  #define PCU_CR_PLATFORM_INFO_PCU_SMM_SAVE_CAP_WID                    ( 1)
+  #define PCU_CR_PLATFORM_INFO_PCU_SMM_SAVE_CAP_MSK                    (0x00010000)
+  #define PCU_CR_PLATFORM_INFO_PCU_SMM_SAVE_CAP_MAX                    (0x00000001)
+  #define PCU_CR_PLATFORM_INFO_PCU_SMM_SAVE_CAP_DEF                    (0x00000001)
+  #define PCU_CR_PLATFORM_INFO_PCU_OCVOLT_OVRD_AVAIL_OFF               (24)
+  #define PCU_CR_PLATFORM_INFO_PCU_OCVOLT_OVRD_AVAIL_WID               ( 1)
+  #define PCU_CR_PLATFORM_INFO_PCU_OCVOLT_OVRD_AVAIL_MSK               (0x01000000)
+  #define PCU_CR_PLATFORM_INFO_PCU_OCVOLT_OVRD_AVAIL_MAX               (0x00000001)
+  #define PCU_CR_PLATFORM_INFO_PCU_OCVOLT_OVRD_AVAIL_DEF               (0x00000000)
+  #define PCU_CR_PLATFORM_INFO_PCU_FIVR_RFI_TUNING_AVAIL_OFF           (25)
+  #define PCU_CR_PLATFORM_INFO_PCU_FIVR_RFI_TUNING_AVAIL_WID           ( 1)
+  #define PCU_CR_PLATFORM_INFO_PCU_FIVR_RFI_TUNING_AVAIL_MSK           (0x02000000)
+  #define PCU_CR_PLATFORM_INFO_PCU_FIVR_RFI_TUNING_AVAIL_MAX           (0x00000001)
+  #define PCU_CR_PLATFORM_INFO_PCU_FIVR_RFI_TUNING_AVAIL_DEF           (0x00000000)
+  #define PCU_CR_PLATFORM_INFO_PCU_DCU_16K_MODE_AVAIL_OFF              (26)
+  #define PCU_CR_PLATFORM_INFO_PCU_DCU_16K_MODE_AVAIL_WID              ( 1)
+  #define PCU_CR_PLATFORM_INFO_PCU_DCU_16K_MODE_AVAIL_MSK              (0x04000000)
+  #define PCU_CR_PLATFORM_INFO_PCU_DCU_16K_MODE_AVAIL_MAX              (0x00000001)
+  #define PCU_CR_PLATFORM_INFO_PCU_DCU_16K_MODE_AVAIL_DEF              (0x00000000)
+  #define PCU_CR_PLATFORM_INFO_PCU_SAMPLE_PART_OFF                     (27)
+  #define PCU_CR_PLATFORM_INFO_PCU_SAMPLE_PART_WID                     ( 1)
+  #define PCU_CR_PLATFORM_INFO_PCU_SAMPLE_PART_MSK                     (0x08000000)
+  #define PCU_CR_PLATFORM_INFO_PCU_SAMPLE_PART_MAX                     (0x00000001)
+  #define PCU_CR_PLATFORM_INFO_PCU_SAMPLE_PART_DEF                     (0x00000000)
+  #define PCU_CR_PLATFORM_INFO_PCU_PRG_TURBO_RATIO_EN_OFF              (28)
+  #define PCU_CR_PLATFORM_INFO_PCU_PRG_TURBO_RATIO_EN_WID              ( 1)
+  #define PCU_CR_PLATFORM_INFO_PCU_PRG_TURBO_RATIO_EN_MSK              (0x10000000)
+  #define PCU_CR_PLATFORM_INFO_PCU_PRG_TURBO_RATIO_EN_MAX              (0x00000001)
+  #define PCU_CR_PLATFORM_INFO_PCU_PRG_TURBO_RATIO_EN_DEF              (0x00000001)
+  #define PCU_CR_PLATFORM_INFO_PCU_PRG_TDP_LIM_EN_OFF                  (29)
+  #define PCU_CR_PLATFORM_INFO_PCU_PRG_TDP_LIM_EN_WID                  ( 1)
+  #define PCU_CR_PLATFORM_INFO_PCU_PRG_TDP_LIM_EN_MSK                  (0x20000000)
+  #define PCU_CR_PLATFORM_INFO_PCU_PRG_TDP_LIM_EN_MAX                  (0x00000001)
+  #define PCU_CR_PLATFORM_INFO_PCU_PRG_TDP_LIM_EN_DEF                  (0x00000001)
+  #define PCU_CR_PLATFORM_INFO_PCU_PRG_TJ_OFFSET_EN_OFF                (30)
+  #define PCU_CR_PLATFORM_INFO_PCU_PRG_TJ_OFFSET_EN_WID                ( 1)
+  #define PCU_CR_PLATFORM_INFO_PCU_PRG_TJ_OFFSET_EN_MSK                (0x40000000)
+  #define PCU_CR_PLATFORM_INFO_PCU_PRG_TJ_OFFSET_EN_MAX                (0x00000001)
+  #define PCU_CR_PLATFORM_INFO_PCU_PRG_TJ_OFFSET_EN_DEF                (0x00000001)
+  #define PCU_CR_PLATFORM_INFO_PCU_CPUID_FAULTING_EN_OFF               (31)
+  #define PCU_CR_PLATFORM_INFO_PCU_CPUID_FAULTING_EN_WID               ( 1)
+  #define PCU_CR_PLATFORM_INFO_PCU_CPUID_FAULTING_EN_MSK               (0x80000000)
+  #define PCU_CR_PLATFORM_INFO_PCU_CPUID_FAULTING_EN_MAX               (0x00000001)
+  #define PCU_CR_PLATFORM_INFO_PCU_CPUID_FAULTING_EN_DEF               (0x00000001)
+  #define PCU_CR_PLATFORM_INFO_PCU_LPM_SUPPORT_OFF                     (32)
+  #define PCU_CR_PLATFORM_INFO_PCU_LPM_SUPPORT_WID                     ( 1)
+  #define PCU_CR_PLATFORM_INFO_PCU_LPM_SUPPORT_MSK                     (0x100000000)
+  #define PCU_CR_PLATFORM_INFO_PCU_LPM_SUPPORT_MAX                     (0x00000001)
+  #define PCU_CR_PLATFORM_INFO_PCU_LPM_SUPPORT_DEF                     (0x00000000)
+  #define PCU_CR_PLATFORM_INFO_PCU_CONFIG_TDP_LEVELS_OFF               (33)
+  #define PCU_CR_PLATFORM_INFO_PCU_CONFIG_TDP_LEVELS_WID               ( 2)
+  #define PCU_CR_PLATFORM_INFO_PCU_CONFIG_TDP_LEVELS_MSK               (0x600000000)
+  #define PCU_CR_PLATFORM_INFO_PCU_CONFIG_TDP_LEVELS_MAX               (0x00000003)
+  #define PCU_CR_PLATFORM_INFO_PCU_CONFIG_TDP_LEVELS_DEF               (0x00000000)
+  #define PCU_CR_PLATFORM_INFO_PCU_PFAT_ENABLE_OFF                     (35)
+  #define PCU_CR_PLATFORM_INFO_PCU_PFAT_ENABLE_WID                     ( 1)
+  #define PCU_CR_PLATFORM_INFO_PCU_PFAT_ENABLE_MSK                     (0x800000000)
+  #define PCU_CR_PLATFORM_INFO_PCU_PFAT_ENABLE_MAX                     (0x00000001)
+  #define PCU_CR_PLATFORM_INFO_PCU_PFAT_ENABLE_DEF                     (0x00000000)
+  #define PCU_CR_PLATFORM_INFO_PCU_TIMED_MWAIT_ENABLE_OFF              (37)
+  #define PCU_CR_PLATFORM_INFO_PCU_TIMED_MWAIT_ENABLE_WID              ( 1)
+  #define PCU_CR_PLATFORM_INFO_PCU_TIMED_MWAIT_ENABLE_MSK              (0x2000000000)
+  #define PCU_CR_PLATFORM_INFO_PCU_TIMED_MWAIT_ENABLE_MAX              (0x00000001)
+  #define PCU_CR_PLATFORM_INFO_PCU_TIMED_MWAIT_ENABLE_DEF              (0x00000000)
+  #define PCU_CR_PLATFORM_INFO_PCU_MAX_EFFICIENCY_RATIO_OFF            (40)
+  #define PCU_CR_PLATFORM_INFO_PCU_MAX_EFFICIENCY_RATIO_WID            ( 8)
+  #define PCU_CR_PLATFORM_INFO_PCU_MAX_EFFICIENCY_RATIO_MSK            (0xFF0000000000)
+  #define PCU_CR_PLATFORM_INFO_PCU_MAX_EFFICIENCY_RATIO_MAX            (0x000000FF)
+  #define PCU_CR_PLATFORM_INFO_PCU_MAX_EFFICIENCY_RATIO_DEF            (0x00000000)
+  #define PCU_CR_PLATFORM_INFO_PCU_MIN_OPERATING_RATIO_OFF             (48)
+  #define PCU_CR_PLATFORM_INFO_PCU_MIN_OPERATING_RATIO_WID             ( 8)
+  #define PCU_CR_PLATFORM_INFO_PCU_MIN_OPERATING_RATIO_MSK             (0xFF000000000000)
+  #define PCU_CR_PLATFORM_INFO_PCU_MIN_OPERATING_RATIO_MAX             (0x000000FF)
+  #define PCU_CR_PLATFORM_INFO_PCU_MIN_OPERATING_RATIO_DEF             (0x00000008)
+
+#define PCU_CR_PP1_C0_CORE_CLOCK_PCU_REG                             (0x00005960)
+  #define PCU_CR_PP1_C0_CORE_CLOCK_PCU_DATA_OFF                        ( 0)
+  #define PCU_CR_PP1_C0_CORE_CLOCK_PCU_DATA_WID                        (32)
+  #define PCU_CR_PP1_C0_CORE_CLOCK_PCU_DATA_MSK                        (0xFFFFFFFF)
+  #define PCU_CR_PP1_C0_CORE_CLOCK_PCU_DATA_MAX                        (0xFFFFFFFF)
+  #define PCU_CR_PP1_C0_CORE_CLOCK_PCU_DATA_DEF                        (0x00000000)
+
+#define PCU_CR_PP0_ANY_THREAD_ACTIVITY_PCU_REG                       (0x00005964)
+  #define PCU_CR_PP0_ANY_THREAD_ACTIVITY_PCU_DATA_OFF                  ( 0)
+  #define PCU_CR_PP0_ANY_THREAD_ACTIVITY_PCU_DATA_WID                  (32)
+  #define PCU_CR_PP0_ANY_THREAD_ACTIVITY_PCU_DATA_MSK                  (0xFFFFFFFF)
+  #define PCU_CR_PP0_ANY_THREAD_ACTIVITY_PCU_DATA_MAX                  (0xFFFFFFFF)
+  #define PCU_CR_PP0_ANY_THREAD_ACTIVITY_PCU_DATA_DEF                  (0x00000000)
+
+#define PCU_CR_PP0_EFFICIENT_CYCLES_PCU_REG                          (0x00005968)
+  #define PCU_CR_PP0_EFFICIENT_CYCLES_PCU_DATA_OFF                     ( 0)
+  #define PCU_CR_PP0_EFFICIENT_CYCLES_PCU_DATA_WID                     (32)
+  #define PCU_CR_PP0_EFFICIENT_CYCLES_PCU_DATA_MSK                     (0xFFFFFFFF)
+  #define PCU_CR_PP0_EFFICIENT_CYCLES_PCU_DATA_MAX                     (0xFFFFFFFF)
+  #define PCU_CR_PP0_EFFICIENT_CYCLES_PCU_DATA_DEF                     (0x00000000)
+
+#define PCU_CR_PP0_THREAD_ACTIVITY_PCU_REG                           (0x0000596C)
+  #define PCU_CR_PP0_THREAD_ACTIVITY_PCU_DATA_OFF                      ( 0)
+  #define PCU_CR_PP0_THREAD_ACTIVITY_PCU_DATA_WID                      (32)
+  #define PCU_CR_PP0_THREAD_ACTIVITY_PCU_DATA_MSK                      (0xFFFFFFFF)
+  #define PCU_CR_PP0_THREAD_ACTIVITY_PCU_DATA_MAX                      (0xFFFFFFFF)
+  #define PCU_CR_PP0_THREAD_ACTIVITY_PCU_DATA_DEF                      (0x00000000)
+
+#define PCU_CR_PP1_ANY_THREAD_ACTIVITY_PCU_REG                       (0x00005970)
+  #define PCU_CR_PP1_ANY_THREAD_ACTIVITY_PCU_DATA_OFF                  ( 0)
+  #define PCU_CR_PP1_ANY_THREAD_ACTIVITY_PCU_DATA_WID                  (32)
+  #define PCU_CR_PP1_ANY_THREAD_ACTIVITY_PCU_DATA_MSK                  (0xFFFFFFFF)
+  #define PCU_CR_PP1_ANY_THREAD_ACTIVITY_PCU_DATA_MAX                  (0xFFFFFFFF)
+  #define PCU_CR_PP1_ANY_THREAD_ACTIVITY_PCU_DATA_DEF                  (0x00000000)
+
+#define PCU_CR_PP1_EFFICIENT_CYCLES_PCU_REG                          (0x00005974)
+  #define PCU_CR_PP1_EFFICIENT_CYCLES_PCU_DATA_OFF                     ( 0)
+  #define PCU_CR_PP1_EFFICIENT_CYCLES_PCU_DATA_WID                     (32)
+  #define PCU_CR_PP1_EFFICIENT_CYCLES_PCU_DATA_MSK                     (0xFFFFFFFF)
+  #define PCU_CR_PP1_EFFICIENT_CYCLES_PCU_DATA_MAX                     (0xFFFFFFFF)
+  #define PCU_CR_PP1_EFFICIENT_CYCLES_PCU_DATA_DEF                     (0x00000000)
+
+#define PCU_CR_PACKAGE_TEMPERATURE_PCU_REG                           (0x00005978)
+  #define PCU_CR_PACKAGE_TEMPERATURE_PCU_DATA_OFF                      ( 0)
+  #define PCU_CR_PACKAGE_TEMPERATURE_PCU_DATA_WID                      ( 8)
+  #define PCU_CR_PACKAGE_TEMPERATURE_PCU_DATA_MSK                      (0x000000FF)
+  #define PCU_CR_PACKAGE_TEMPERATURE_PCU_DATA_MAX                      (0x000000FF)
+  #define PCU_CR_PACKAGE_TEMPERATURE_PCU_DATA_DEF                      (0x00000000)
+
+#define PCU_CR_PP0_TEMPERATURE_PCU_REG                               (0x0000597C)
+  #define PCU_CR_PP0_TEMPERATURE_PCU_DATA_OFF                          ( 0)
+  #define PCU_CR_PP0_TEMPERATURE_PCU_DATA_WID                          ( 8)
+  #define PCU_CR_PP0_TEMPERATURE_PCU_DATA_MSK                          (0x000000FF)
+  #define PCU_CR_PP0_TEMPERATURE_PCU_DATA_MAX                          (0x000000FF)
+  #define PCU_CR_PP0_TEMPERATURE_PCU_DATA_DEF                          (0x00000000)
+
+#define PCU_CR_PP1_TEMPERATURE_PCU_REG                               (0x00005980)
+  #define PCU_CR_PP1_TEMPERATURE_PCU_DATA_OFF                          ( 0)
+  #define PCU_CR_PP1_TEMPERATURE_PCU_DATA_WID                          ( 8)
+  #define PCU_CR_PP1_TEMPERATURE_PCU_DATA_MSK                          (0x000000FF)
+  #define PCU_CR_PP1_TEMPERATURE_PCU_DATA_MAX                          (0x000000FF)
+  #define PCU_CR_PP1_TEMPERATURE_PCU_DATA_DEF                          (0x00000000)
+
+#define PCU_CR_PCU_REFERENCE_CLOCK_PCU_REG                           (0x00005984)
+  #define PCU_CR_PCU_REFERENCE_CLOCK_PCU_TIME_VAL_OFF                  ( 0)
+  #define PCU_CR_PCU_REFERENCE_CLOCK_PCU_TIME_VAL_WID                  (32)
+  #define PCU_CR_PCU_REFERENCE_CLOCK_PCU_TIME_VAL_MSK                  (0xFFFFFFFF)
+  #define PCU_CR_PCU_REFERENCE_CLOCK_PCU_TIME_VAL_MAX                  (0xFFFFFFFF)
+  #define PCU_CR_PCU_REFERENCE_CLOCK_PCU_TIME_VAL_DEF                  (0x00000000)
+
+#define PCU_CR_DEVICE_SHARED_IDLE_DURATION_PCU_REG                   (0x00005988)
+  #define PCU_CR_DEVICE_SHARED_IDLE_DURATION_PCU_RESERVED_OFF          ( 0)
+  #define PCU_CR_DEVICE_SHARED_IDLE_DURATION_PCU_RESERVED_WID          ( 1)
+  #define PCU_CR_DEVICE_SHARED_IDLE_DURATION_PCU_RESERVED_MSK          (0x00000001)
+  #define PCU_CR_DEVICE_SHARED_IDLE_DURATION_PCU_RESERVED_MAX          (0x00000001)
+  #define PCU_CR_DEVICE_SHARED_IDLE_DURATION_PCU_RESERVED_DEF          (0x00000000)
+  #define PCU_CR_DEVICE_SHARED_IDLE_DURATION_PCU_VALID_OFF             ( 1)
+  #define PCU_CR_DEVICE_SHARED_IDLE_DURATION_PCU_VALID_WID             ( 1)
+  #define PCU_CR_DEVICE_SHARED_IDLE_DURATION_PCU_VALID_MSK             (0x00000002)
+  #define PCU_CR_DEVICE_SHARED_IDLE_DURATION_PCU_VALID_MAX             (0x00000001)
+  #define PCU_CR_DEVICE_SHARED_IDLE_DURATION_PCU_VALID_DEF             (0x00000000)
+  #define PCU_CR_DEVICE_SHARED_IDLE_DURATION_PCU_RESERVED_BITS_OFF     ( 2)
+  #define PCU_CR_DEVICE_SHARED_IDLE_DURATION_PCU_RESERVED_BITS_WID     ( 4)
+  #define PCU_CR_DEVICE_SHARED_IDLE_DURATION_PCU_RESERVED_BITS_MSK     (0x0000003C)
+  #define PCU_CR_DEVICE_SHARED_IDLE_DURATION_PCU_RESERVED_BITS_MAX     (0x0000000F)
+  #define PCU_CR_DEVICE_SHARED_IDLE_DURATION_PCU_RESERVED_BITS_DEF     (0x00000000)
+  #define PCU_CR_DEVICE_SHARED_IDLE_DURATION_PCU_OD_OFF                ( 6)
+  #define PCU_CR_DEVICE_SHARED_IDLE_DURATION_PCU_OD_WID                ( 1)
+  #define PCU_CR_DEVICE_SHARED_IDLE_DURATION_PCU_OD_MSK                (0x00000040)
+  #define PCU_CR_DEVICE_SHARED_IDLE_DURATION_PCU_OD_MAX                (0x00000001)
+  #define PCU_CR_DEVICE_SHARED_IDLE_DURATION_PCU_OD_DEF                (0x00000000)
+  #define PCU_CR_DEVICE_SHARED_IDLE_DURATION_PCU_IM_OFF                ( 7)
+  #define PCU_CR_DEVICE_SHARED_IDLE_DURATION_PCU_IM_WID                ( 1)
+  #define PCU_CR_DEVICE_SHARED_IDLE_DURATION_PCU_IM_MSK                (0x00000080)
+  #define PCU_CR_DEVICE_SHARED_IDLE_DURATION_PCU_IM_MAX                (0x00000001)
+  #define PCU_CR_DEVICE_SHARED_IDLE_DURATION_PCU_IM_DEF                (0x00000000)
+  #define PCU_CR_DEVICE_SHARED_IDLE_DURATION_PCU_NEXT_DEVICE_ACTIVITY_OFF ( 8)
+  #define PCU_CR_DEVICE_SHARED_IDLE_DURATION_PCU_NEXT_DEVICE_ACTIVITY_WID (21)
+  #define PCU_CR_DEVICE_SHARED_IDLE_DURATION_PCU_NEXT_DEVICE_ACTIVITY_MSK (0x1FFFFF00)
+  #define PCU_CR_DEVICE_SHARED_IDLE_DURATION_PCU_NEXT_DEVICE_ACTIVITY_MAX (0x001FFFFF)
+  #define PCU_CR_DEVICE_SHARED_IDLE_DURATION_PCU_NEXT_DEVICE_ACTIVITY_DEF (0x00000000)
+
+#define PCU_CR_DEVICE_DEDICATED_IDLE_DURATION_PCU_REG                (0x0000598C)
+  #define PCU_CR_DEVICE_DEDICATED_IDLE_DURATION_PCU_USED_OFF           ( 0)
+  #define PCU_CR_DEVICE_DEDICATED_IDLE_DURATION_PCU_USED_WID           ( 1)
+  #define PCU_CR_DEVICE_DEDICATED_IDLE_DURATION_PCU_USED_MSK           (0x00000001)
+  #define PCU_CR_DEVICE_DEDICATED_IDLE_DURATION_PCU_USED_MAX           (0x00000001)
+  #define PCU_CR_DEVICE_DEDICATED_IDLE_DURATION_PCU_USED_DEF           (0x00000000)
+  #define PCU_CR_DEVICE_DEDICATED_IDLE_DURATION_PCU_VALID_OFF          ( 1)
+  #define PCU_CR_DEVICE_DEDICATED_IDLE_DURATION_PCU_VALID_WID          ( 1)
+  #define PCU_CR_DEVICE_DEDICATED_IDLE_DURATION_PCU_VALID_MSK          (0x00000002)
+  #define PCU_CR_DEVICE_DEDICATED_IDLE_DURATION_PCU_VALID_MAX          (0x00000001)
+  #define PCU_CR_DEVICE_DEDICATED_IDLE_DURATION_PCU_VALID_DEF          (0x00000000)
+  #define PCU_CR_DEVICE_DEDICATED_IDLE_DURATION_PCU_RESERVED_BITS_OFF  ( 2)
+  #define PCU_CR_DEVICE_DEDICATED_IDLE_DURATION_PCU_RESERVED_BITS_WID  ( 4)
+  #define PCU_CR_DEVICE_DEDICATED_IDLE_DURATION_PCU_RESERVED_BITS_MSK  (0x0000003C)
+  #define PCU_CR_DEVICE_DEDICATED_IDLE_DURATION_PCU_RESERVED_BITS_MAX  (0x0000000F)
+  #define PCU_CR_DEVICE_DEDICATED_IDLE_DURATION_PCU_RESERVED_BITS_DEF  (0x00000000)
+  #define PCU_CR_DEVICE_DEDICATED_IDLE_DURATION_PCU_OD_OFF             ( 6)
+  #define PCU_CR_DEVICE_DEDICATED_IDLE_DURATION_PCU_OD_WID             ( 1)
+  #define PCU_CR_DEVICE_DEDICATED_IDLE_DURATION_PCU_OD_MSK             (0x00000040)
+  #define PCU_CR_DEVICE_DEDICATED_IDLE_DURATION_PCU_OD_MAX             (0x00000001)
+  #define PCU_CR_DEVICE_DEDICATED_IDLE_DURATION_PCU_OD_DEF             (0x00000000)
+  #define PCU_CR_DEVICE_DEDICATED_IDLE_DURATION_PCU_IM_OFF             ( 7)
+  #define PCU_CR_DEVICE_DEDICATED_IDLE_DURATION_PCU_IM_WID             ( 1)
+  #define PCU_CR_DEVICE_DEDICATED_IDLE_DURATION_PCU_IM_MSK             (0x00000080)
+  #define PCU_CR_DEVICE_DEDICATED_IDLE_DURATION_PCU_IM_MAX             (0x00000001)
+  #define PCU_CR_DEVICE_DEDICATED_IDLE_DURATION_PCU_IM_DEF             (0x00000000)
+  #define PCU_CR_DEVICE_DEDICATED_IDLE_DURATION_PCU_NEXT_DEVICE_ACTIVITY_OFF ( 8)
+  #define PCU_CR_DEVICE_DEDICATED_IDLE_DURATION_PCU_NEXT_DEVICE_ACTIVITY_WID (21)
+  #define PCU_CR_DEVICE_DEDICATED_IDLE_DURATION_PCU_NEXT_DEVICE_ACTIVITY_MSK (0x1FFFFF00)
+  #define PCU_CR_DEVICE_DEDICATED_IDLE_DURATION_PCU_NEXT_DEVICE_ACTIVITY_MAX (0x001FFFFF)
+  #define PCU_CR_DEVICE_DEDICATED_IDLE_DURATION_PCU_NEXT_DEVICE_ACTIVITY_DEF (0x00000000)
+
+#define PCU_CR_P_STATE_LIMITS_PCU_REG                                (0x00005990)
+  #define PCU_CR_P_STATE_LIMITS_PCU_PSTT_LIM_OFF                       ( 0)
+  #define PCU_CR_P_STATE_LIMITS_PCU_PSTT_LIM_WID                       ( 8)
+  #define PCU_CR_P_STATE_LIMITS_PCU_PSTT_LIM_MSK                       (0x000000FF)
+  #define PCU_CR_P_STATE_LIMITS_PCU_PSTT_LIM_MAX                       (0x000000FF)
+  #define PCU_CR_P_STATE_LIMITS_PCU_PSTT_LIM_DEF                       (0x000000FF)
+  #define PCU_CR_P_STATE_LIMITS_PCU_PSTT_MIN_OFF                       ( 8)
+  #define PCU_CR_P_STATE_LIMITS_PCU_PSTT_MIN_WID                       ( 8)
+  #define PCU_CR_P_STATE_LIMITS_PCU_PSTT_MIN_MSK                       (0x0000FF00)
+  #define PCU_CR_P_STATE_LIMITS_PCU_PSTT_MIN_MAX                       (0x000000FF)
+  #define PCU_CR_P_STATE_LIMITS_PCU_PSTT_MIN_DEF                       (0x00000000)
+  #define PCU_CR_P_STATE_LIMITS_PCU_LOCK_OFF                           (31)
+  #define PCU_CR_P_STATE_LIMITS_PCU_LOCK_WID                           ( 1)
+  #define PCU_CR_P_STATE_LIMITS_PCU_LOCK_MSK                           (0x80000000)
+  #define PCU_CR_P_STATE_LIMITS_PCU_LOCK_MAX                           (0x00000001)
+  #define PCU_CR_P_STATE_LIMITS_PCU_LOCK_DEF                           (0x00000000)
+
+#define PCU_CR_RP_STATE_LIMITS_PCU_REG                               (0x00005994)
+  #define PCU_CR_RP_STATE_LIMITS_PCU_RPSTT_LIM_OFF                     ( 0)
+  #define PCU_CR_RP_STATE_LIMITS_PCU_RPSTT_LIM_WID                     ( 8)
+  #define PCU_CR_RP_STATE_LIMITS_PCU_RPSTT_LIM_MSK                     (0x000000FF)
+  #define PCU_CR_RP_STATE_LIMITS_PCU_RPSTT_LIM_MAX                     (0x000000FF)
+  #define PCU_CR_RP_STATE_LIMITS_PCU_RPSTT_LIM_DEF                     (0x000000FF)
+
+#define PCU_CR_RP_STATE_CAP_PCU_REG                                  (0x00005998)
+  #define PCU_CR_RP_STATE_CAP_PCU_RP0_CAP_OFF                          ( 0)
+  #define PCU_CR_RP_STATE_CAP_PCU_RP0_CAP_WID                          ( 8)
+  #define PCU_CR_RP_STATE_CAP_PCU_RP0_CAP_MSK                          (0x000000FF)
+  #define PCU_CR_RP_STATE_CAP_PCU_RP0_CAP_MAX                          (0x000000FF)
+  #define PCU_CR_RP_STATE_CAP_PCU_RP0_CAP_DEF                          (0x00000000)
+  #define PCU_CR_RP_STATE_CAP_PCU_RP1_CAP_OFF                          ( 8)
+  #define PCU_CR_RP_STATE_CAP_PCU_RP1_CAP_WID                          ( 8)
+  #define PCU_CR_RP_STATE_CAP_PCU_RP1_CAP_MSK                          (0x0000FF00)
+  #define PCU_CR_RP_STATE_CAP_PCU_RP1_CAP_MAX                          (0x000000FF)
+  #define PCU_CR_RP_STATE_CAP_PCU_RP1_CAP_DEF                          (0x00000000)
+  #define PCU_CR_RP_STATE_CAP_PCU_RPN_CAP_OFF                          (16)
+  #define PCU_CR_RP_STATE_CAP_PCU_RPN_CAP_WID                          ( 8)
+  #define PCU_CR_RP_STATE_CAP_PCU_RPN_CAP_MSK                          (0x00FF0000)
+  #define PCU_CR_RP_STATE_CAP_PCU_RPN_CAP_MAX                          (0x000000FF)
+  #define PCU_CR_RP_STATE_CAP_PCU_RPN_CAP_DEF                          (0x00000000)
+
+#define PCU_CR_TEMPERATURE_TARGET_PCU_REG                            (0x0000599C)
+  #define PCU_CR_TEMPERATURE_TARGET_PCU_FAN_TEMP_TARGET_OFST_OFF       ( 8)
+  #define PCU_CR_TEMPERATURE_TARGET_PCU_FAN_TEMP_TARGET_OFST_WID       ( 8)
+  #define PCU_CR_TEMPERATURE_TARGET_PCU_FAN_TEMP_TARGET_OFST_MSK       (0x0000FF00)
+  #define PCU_CR_TEMPERATURE_TARGET_PCU_FAN_TEMP_TARGET_OFST_MAX       (0x000000FF)
+  #define PCU_CR_TEMPERATURE_TARGET_PCU_FAN_TEMP_TARGET_OFST_DEF       (0x00000000)
+  #define PCU_CR_TEMPERATURE_TARGET_PCU_REF_TEMP_OFF                   (16)
+  #define PCU_CR_TEMPERATURE_TARGET_PCU_REF_TEMP_WID                   ( 8)
+  #define PCU_CR_TEMPERATURE_TARGET_PCU_REF_TEMP_MSK                   (0x00FF0000)
+  #define PCU_CR_TEMPERATURE_TARGET_PCU_REF_TEMP_MAX                   (0x000000FF)
+  #define PCU_CR_TEMPERATURE_TARGET_PCU_REF_TEMP_DEF                   (0x00000000)
+  #define PCU_CR_TEMPERATURE_TARGET_PCU_TJ_MAX_TCC_OFFSET_OFF          (24)
+  #define PCU_CR_TEMPERATURE_TARGET_PCU_TJ_MAX_TCC_OFFSET_WID          ( 4)
+  #define PCU_CR_TEMPERATURE_TARGET_PCU_TJ_MAX_TCC_OFFSET_MSK          (0x0F000000)
+  #define PCU_CR_TEMPERATURE_TARGET_PCU_TJ_MAX_TCC_OFFSET_MAX          (0x0000000F)
+  #define PCU_CR_TEMPERATURE_TARGET_PCU_TJ_MAX_TCC_OFFSET_DEF          (0x00000000)
+
+#define PCU_CR_PACKAGE_RAPL_LIMIT_PCU_REG                            (0x000059A0)
+  #define PCU_CR_PACKAGE_RAPL_LIMIT_PCU_PKG_PWR_LIM_1_OFF              ( 0)
+  #define PCU_CR_PACKAGE_RAPL_LIMIT_PCU_PKG_PWR_LIM_1_WID              (15)
+  #define PCU_CR_PACKAGE_RAPL_LIMIT_PCU_PKG_PWR_LIM_1_MSK              (0x00007FFF)
+  #define PCU_CR_PACKAGE_RAPL_LIMIT_PCU_PKG_PWR_LIM_1_MAX              (0x00007FFF)
+  #define PCU_CR_PACKAGE_RAPL_LIMIT_PCU_PKG_PWR_LIM_1_DEF              (0x00000000)
+  #define PCU_CR_PACKAGE_RAPL_LIMIT_PCU_PKG_PWR_LIM_1_EN_OFF           (15)
+  #define PCU_CR_PACKAGE_RAPL_LIMIT_PCU_PKG_PWR_LIM_1_EN_WID           ( 1)
+  #define PCU_CR_PACKAGE_RAPL_LIMIT_PCU_PKG_PWR_LIM_1_EN_MSK           (0x00008000)
+  #define PCU_CR_PACKAGE_RAPL_LIMIT_PCU_PKG_PWR_LIM_1_EN_MAX           (0x00000001)
+  #define PCU_CR_PACKAGE_RAPL_LIMIT_PCU_PKG_PWR_LIM_1_EN_DEF           (0x00000000)
+  #define PCU_CR_PACKAGE_RAPL_LIMIT_PCU_PKG_CLMP_LIM_1_OFF             (16)
+  #define PCU_CR_PACKAGE_RAPL_LIMIT_PCU_PKG_CLMP_LIM_1_WID             ( 1)
+  #define PCU_CR_PACKAGE_RAPL_LIMIT_PCU_PKG_CLMP_LIM_1_MSK             (0x00010000)
+  #define PCU_CR_PACKAGE_RAPL_LIMIT_PCU_PKG_CLMP_LIM_1_MAX             (0x00000001)
+  #define PCU_CR_PACKAGE_RAPL_LIMIT_PCU_PKG_CLMP_LIM_1_DEF             (0x00000000)
+  #define PCU_CR_PACKAGE_RAPL_LIMIT_PCU_PKG_PWR_LIM_1_TIME_OFF         (17)
+  #define PCU_CR_PACKAGE_RAPL_LIMIT_PCU_PKG_PWR_LIM_1_TIME_WID         ( 7)
+  #define PCU_CR_PACKAGE_RAPL_LIMIT_PCU_PKG_PWR_LIM_1_TIME_MSK         (0x00FE0000)
+  #define PCU_CR_PACKAGE_RAPL_LIMIT_PCU_PKG_PWR_LIM_1_TIME_MAX         (0x0000007F)
+  #define PCU_CR_PACKAGE_RAPL_LIMIT_PCU_PKG_PWR_LIM_1_TIME_DEF         (0x00000000)
+  #define PCU_CR_PACKAGE_RAPL_LIMIT_PCU_PKG_PWR_LIM_2_OFF              (32)
+  #define PCU_CR_PACKAGE_RAPL_LIMIT_PCU_PKG_PWR_LIM_2_WID              (15)
+  #define PCU_CR_PACKAGE_RAPL_LIMIT_PCU_PKG_PWR_LIM_2_MSK              (0x7FFF00000000)
+  #define PCU_CR_PACKAGE_RAPL_LIMIT_PCU_PKG_PWR_LIM_2_MAX              (0x00007FFF)
+  #define PCU_CR_PACKAGE_RAPL_LIMIT_PCU_PKG_PWR_LIM_2_DEF              (0x00000000)
+  #define PCU_CR_PACKAGE_RAPL_LIMIT_PCU_PKG_PWR_LIM_2_EN_OFF           (47)
+  #define PCU_CR_PACKAGE_RAPL_LIMIT_PCU_PKG_PWR_LIM_2_EN_WID           ( 1)
+  #define PCU_CR_PACKAGE_RAPL_LIMIT_PCU_PKG_PWR_LIM_2_EN_MSK           (0x800000000000)
+  #define PCU_CR_PACKAGE_RAPL_LIMIT_PCU_PKG_PWR_LIM_2_EN_MAX           (0x00000001)
+  #define PCU_CR_PACKAGE_RAPL_LIMIT_PCU_PKG_PWR_LIM_2_EN_DEF           (0x00000000)
+  #define PCU_CR_PACKAGE_RAPL_LIMIT_PCU_PKG_CLMP_LIM_2_OFF             (48)
+  #define PCU_CR_PACKAGE_RAPL_LIMIT_PCU_PKG_CLMP_LIM_2_WID             ( 1)
+  #define PCU_CR_PACKAGE_RAPL_LIMIT_PCU_PKG_CLMP_LIM_2_MSK             (0x1000000000000)
+  #define PCU_CR_PACKAGE_RAPL_LIMIT_PCU_PKG_CLMP_LIM_2_MAX             (0x00000001)
+  #define PCU_CR_PACKAGE_RAPL_LIMIT_PCU_PKG_CLMP_LIM_2_DEF             (0x00000000)
+  #define PCU_CR_PACKAGE_RAPL_LIMIT_PCU_PKG_PWR_LIM_2_TIME_OFF         (49)
+  #define PCU_CR_PACKAGE_RAPL_LIMIT_PCU_PKG_PWR_LIM_2_TIME_WID         ( 7)
+  #define PCU_CR_PACKAGE_RAPL_LIMIT_PCU_PKG_PWR_LIM_2_TIME_MSK         (0xFE000000000000)
+  #define PCU_CR_PACKAGE_RAPL_LIMIT_PCU_PKG_PWR_LIM_2_TIME_MAX         (0x0000007F)
+  #define PCU_CR_PACKAGE_RAPL_LIMIT_PCU_PKG_PWR_LIM_2_TIME_DEF         (0x00000000)
+  #define PCU_CR_PACKAGE_RAPL_LIMIT_PCU_PKG_PWR_LIM_LOCK_OFF           (63)
+  #define PCU_CR_PACKAGE_RAPL_LIMIT_PCU_PKG_PWR_LIM_LOCK_WID           ( 1)
+  #define PCU_CR_PACKAGE_RAPL_LIMIT_PCU_PKG_PWR_LIM_LOCK_MSK           (0x8000000000000000)
+  #define PCU_CR_PACKAGE_RAPL_LIMIT_PCU_PKG_PWR_LIM_LOCK_MAX           (0x00000001)
+  #define PCU_CR_PACKAGE_RAPL_LIMIT_PCU_PKG_PWR_LIM_LOCK_DEF           (0x00000000)
+
+#define PCU_CR_PRIP_TURBO_PWR_LIM_PCU_REG                            (0x000059A8)
+  #define PCU_CR_PRIP_TURBO_PWR_LIM_PCU_IA_PP_PWR_LIM_OFF              ( 0)
+  #define PCU_CR_PRIP_TURBO_PWR_LIM_PCU_IA_PP_PWR_LIM_WID              (15)
+  #define PCU_CR_PRIP_TURBO_PWR_LIM_PCU_IA_PP_PWR_LIM_MSK              (0x00007FFF)
+  #define PCU_CR_PRIP_TURBO_PWR_LIM_PCU_IA_PP_PWR_LIM_MAX              (0x00007FFF)
+  #define PCU_CR_PRIP_TURBO_PWR_LIM_PCU_IA_PP_PWR_LIM_DEF              (0x00000000)
+  #define PCU_CR_PRIP_TURBO_PWR_LIM_PCU_PWR_LIM_CTRL_EN_OFF            (15)
+  #define PCU_CR_PRIP_TURBO_PWR_LIM_PCU_PWR_LIM_CTRL_EN_WID            ( 1)
+  #define PCU_CR_PRIP_TURBO_PWR_LIM_PCU_PWR_LIM_CTRL_EN_MSK            (0x00008000)
+  #define PCU_CR_PRIP_TURBO_PWR_LIM_PCU_PWR_LIM_CTRL_EN_MAX            (0x00000001)
+  #define PCU_CR_PRIP_TURBO_PWR_LIM_PCU_PWR_LIM_CTRL_EN_DEF            (0x00000000)
+  #define PCU_CR_PRIP_TURBO_PWR_LIM_PCU_PP_CLAMP_LIM_OFF               (16)
+  #define PCU_CR_PRIP_TURBO_PWR_LIM_PCU_PP_CLAMP_LIM_WID               ( 1)
+  #define PCU_CR_PRIP_TURBO_PWR_LIM_PCU_PP_CLAMP_LIM_MSK               (0x00010000)
+  #define PCU_CR_PRIP_TURBO_PWR_LIM_PCU_PP_CLAMP_LIM_MAX               (0x00000001)
+  #define PCU_CR_PRIP_TURBO_PWR_LIM_PCU_PP_CLAMP_LIM_DEF               (0x00000000)
+  #define PCU_CR_PRIP_TURBO_PWR_LIM_PCU_CTRL_TIME_WIN_OFF              (17)
+  #define PCU_CR_PRIP_TURBO_PWR_LIM_PCU_CTRL_TIME_WIN_WID              ( 7)
+  #define PCU_CR_PRIP_TURBO_PWR_LIM_PCU_CTRL_TIME_WIN_MSK              (0x00FE0000)
+  #define PCU_CR_PRIP_TURBO_PWR_LIM_PCU_CTRL_TIME_WIN_MAX              (0x0000007F)
+  #define PCU_CR_PRIP_TURBO_PWR_LIM_PCU_CTRL_TIME_WIN_DEF              (0x00000000)
+  #define PCU_CR_PRIP_TURBO_PWR_LIM_PCU_PP_PWR_LIM_LOCK_OFF            (31)
+  #define PCU_CR_PRIP_TURBO_PWR_LIM_PCU_PP_PWR_LIM_LOCK_WID            ( 1)
+  #define PCU_CR_PRIP_TURBO_PWR_LIM_PCU_PP_PWR_LIM_LOCK_MSK            (0x80000000)
+  #define PCU_CR_PRIP_TURBO_PWR_LIM_PCU_PP_PWR_LIM_LOCK_MAX            (0x00000001)
+  #define PCU_CR_PRIP_TURBO_PWR_LIM_PCU_PP_PWR_LIM_LOCK_DEF            (0x00000000)
+
+#define PCU_CR_SECP_TURBO_PWR_LIM_PCU_REG                            (0x000059AC)
+  #define PCU_CR_SECP_TURBO_PWR_LIM_PCU_NON_IA_PP_PWR_LIM_OFF          ( 0)
+  #define PCU_CR_SECP_TURBO_PWR_LIM_PCU_NON_IA_PP_PWR_LIM_WID          (15)
+  #define PCU_CR_SECP_TURBO_PWR_LIM_PCU_NON_IA_PP_PWR_LIM_MSK          (0x00007FFF)
+  #define PCU_CR_SECP_TURBO_PWR_LIM_PCU_NON_IA_PP_PWR_LIM_MAX          (0x00007FFF)
+  #define PCU_CR_SECP_TURBO_PWR_LIM_PCU_NON_IA_PP_PWR_LIM_DEF          (0x00000000)
+  #define PCU_CR_SECP_TURBO_PWR_LIM_PCU_PWR_LIM_CTRL_EN_OFF            (15)
+  #define PCU_CR_SECP_TURBO_PWR_LIM_PCU_PWR_LIM_CTRL_EN_WID            ( 1)
+  #define PCU_CR_SECP_TURBO_PWR_LIM_PCU_PWR_LIM_CTRL_EN_MSK            (0x00008000)
+  #define PCU_CR_SECP_TURBO_PWR_LIM_PCU_PWR_LIM_CTRL_EN_MAX            (0x00000001)
+  #define PCU_CR_SECP_TURBO_PWR_LIM_PCU_PWR_LIM_CTRL_EN_DEF            (0x00000000)
+  #define PCU_CR_SECP_TURBO_PWR_LIM_PCU_PP_CLAMP_LIM_OFF               (16)
+  #define PCU_CR_SECP_TURBO_PWR_LIM_PCU_PP_CLAMP_LIM_WID               ( 1)
+  #define PCU_CR_SECP_TURBO_PWR_LIM_PCU_PP_CLAMP_LIM_MSK               (0x00010000)
+  #define PCU_CR_SECP_TURBO_PWR_LIM_PCU_PP_CLAMP_LIM_MAX               (0x00000001)
+  #define PCU_CR_SECP_TURBO_PWR_LIM_PCU_PP_CLAMP_LIM_DEF               (0x00000000)
+  #define PCU_CR_SECP_TURBO_PWR_LIM_PCU_CTRL_TIME_WIN_OFF              (17)
+  #define PCU_CR_SECP_TURBO_PWR_LIM_PCU_CTRL_TIME_WIN_WID              ( 7)
+  #define PCU_CR_SECP_TURBO_PWR_LIM_PCU_CTRL_TIME_WIN_MSK              (0x00FE0000)
+  #define PCU_CR_SECP_TURBO_PWR_LIM_PCU_CTRL_TIME_WIN_MAX              (0x0000007F)
+  #define PCU_CR_SECP_TURBO_PWR_LIM_PCU_CTRL_TIME_WIN_DEF              (0x00000000)
+  #define PCU_CR_SECP_TURBO_PWR_LIM_PCU_SP_PWR_LIM_LOCK_OFF            (31)
+  #define PCU_CR_SECP_TURBO_PWR_LIM_PCU_SP_PWR_LIM_LOCK_WID            ( 1)
+  #define PCU_CR_SECP_TURBO_PWR_LIM_PCU_SP_PWR_LIM_LOCK_MSK            (0x80000000)
+  #define PCU_CR_SECP_TURBO_PWR_LIM_PCU_SP_PWR_LIM_LOCK_MAX            (0x00000001)
+  #define PCU_CR_SECP_TURBO_PWR_LIM_PCU_SP_PWR_LIM_LOCK_DEF            (0x00000000)
+
+#define PCU_CR_VR_CURRENT_CONFIG_PCU_REG                             (0x000059B0)
+  #define PCU_CR_VR_CURRENT_CONFIG_PCU_CURRENT_LIMIT_OFF               ( 0)
+  #define PCU_CR_VR_CURRENT_CONFIG_PCU_CURRENT_LIMIT_WID               (13)
+  #define PCU_CR_VR_CURRENT_CONFIG_PCU_CURRENT_LIMIT_MSK               (0x00001FFF)
+  #define PCU_CR_VR_CURRENT_CONFIG_PCU_CURRENT_LIMIT_MAX               (0x00001FFF)
+  #define PCU_CR_VR_CURRENT_CONFIG_PCU_CURRENT_LIMIT_DEF               (0x00000190)
+  #define PCU_CR_VR_CURRENT_CONFIG_PCU_LOCK_OFF                        (31)
+  #define PCU_CR_VR_CURRENT_CONFIG_PCU_LOCK_WID                        ( 1)
+  #define PCU_CR_VR_CURRENT_CONFIG_PCU_LOCK_MSK                        (0x80000000)
+  #define PCU_CR_VR_CURRENT_CONFIG_PCU_LOCK_MAX                        (0x00000001)
+  #define PCU_CR_VR_CURRENT_CONFIG_PCU_LOCK_DEF                        (0x00000000)
+  #define PCU_CR_VR_CURRENT_CONFIG_PCU_PSI1_THRESHOLD_OFF              (32)
+  #define PCU_CR_VR_CURRENT_CONFIG_PCU_PSI1_THRESHOLD_WID              (10)
+  #define PCU_CR_VR_CURRENT_CONFIG_PCU_PSI1_THRESHOLD_MSK              (0x3FF00000000)
+  #define PCU_CR_VR_CURRENT_CONFIG_PCU_PSI1_THRESHOLD_MAX              (0x000003FF)
+  #define PCU_CR_VR_CURRENT_CONFIG_PCU_PSI1_THRESHOLD_DEF              (0x00000000)
+  #define PCU_CR_VR_CURRENT_CONFIG_PCU_PSI2_THRESHOLD_OFF              (42)
+  #define PCU_CR_VR_CURRENT_CONFIG_PCU_PSI2_THRESHOLD_WID              (10)
+  #define PCU_CR_VR_CURRENT_CONFIG_PCU_PSI2_THRESHOLD_MSK              (0xFFC0000000000)
+  #define PCU_CR_VR_CURRENT_CONFIG_PCU_PSI2_THRESHOLD_MAX              (0x000003FF)
+  #define PCU_CR_VR_CURRENT_CONFIG_PCU_PSI2_THRESHOLD_DEF              (0x00000000)
+  #define PCU_CR_VR_CURRENT_CONFIG_PCU_PSI3_THRESHOLD_OFF              (52)
+  #define PCU_CR_VR_CURRENT_CONFIG_PCU_PSI3_THRESHOLD_WID              (10)
+  #define PCU_CR_VR_CURRENT_CONFIG_PCU_PSI3_THRESHOLD_MSK              (0x3FF0000000000000)
+  #define PCU_CR_VR_CURRENT_CONFIG_PCU_PSI3_THRESHOLD_MAX              (0x000003FF)
+  #define PCU_CR_VR_CURRENT_CONFIG_PCU_PSI3_THRESHOLD_DEF              (0x00000000)
+  #define PCU_CR_VR_CURRENT_CONFIG_PCU_RESERVED_OFF                    (62)
+  #define PCU_CR_VR_CURRENT_CONFIG_PCU_RESERVED_WID                    ( 2)
+  #define PCU_CR_VR_CURRENT_CONFIG_PCU_RESERVED_MSK                    (0xC000000000000000)
+  #define PCU_CR_VR_CURRENT_CONFIG_PCU_RESERVED_MAX                    (0x00000003)
+  #define PCU_CR_VR_CURRENT_CONFIG_PCU_RESERVED_DEF                    (0x00000000)
+
+#define PCU_CR_MRC_ODT_POWER_SAVING_PCU_REG                          (0x000059B8)
+  #define PCU_CR_MRC_ODT_POWER_SAVING_PCU_MRC_Saving_Rd_OFF            ( 0)
+  #define PCU_CR_MRC_ODT_POWER_SAVING_PCU_MRC_Saving_Rd_WID            ( 8)
+  #define PCU_CR_MRC_ODT_POWER_SAVING_PCU_MRC_Saving_Rd_MSK            (0x000000FF)
+  #define PCU_CR_MRC_ODT_POWER_SAVING_PCU_MRC_Saving_Rd_MAX            (0x000000FF)
+  #define PCU_CR_MRC_ODT_POWER_SAVING_PCU_MRC_Saving_Rd_DEF            (0x00000000)
+  #define PCU_CR_MRC_ODT_POWER_SAVING_PCU_MRC_Saving_Wt_OFF            ( 8)
+  #define PCU_CR_MRC_ODT_POWER_SAVING_PCU_MRC_Saving_Wt_WID            ( 8)
+  #define PCU_CR_MRC_ODT_POWER_SAVING_PCU_MRC_Saving_Wt_MSK            (0x0000FF00)
+  #define PCU_CR_MRC_ODT_POWER_SAVING_PCU_MRC_Saving_Wt_MAX            (0x000000FF)
+  #define PCU_CR_MRC_ODT_POWER_SAVING_PCU_MRC_Saving_Wt_DEF            (0x00000000)
+  #define PCU_CR_MRC_ODT_POWER_SAVING_PCU_MRC_Saving_Cmd_OFF           (16)
+  #define PCU_CR_MRC_ODT_POWER_SAVING_PCU_MRC_Saving_Cmd_WID           ( 8)
+  #define PCU_CR_MRC_ODT_POWER_SAVING_PCU_MRC_Saving_Cmd_MSK           (0x00FF0000)
+  #define PCU_CR_MRC_ODT_POWER_SAVING_PCU_MRC_Saving_Cmd_MAX           (0x000000FF)
+  #define PCU_CR_MRC_ODT_POWER_SAVING_PCU_MRC_Saving_Cmd_DEF           (0x00000000)
+  #define PCU_CR_MRC_ODT_POWER_SAVING_PCU_RESERVED_OFF                 (24)
+  #define PCU_CR_MRC_ODT_POWER_SAVING_PCU_RESERVED_WID                 ( 8)
+  #define PCU_CR_MRC_ODT_POWER_SAVING_PCU_RESERVED_MSK                 (0xFF000000)
+  #define PCU_CR_MRC_ODT_POWER_SAVING_PCU_RESERVED_MAX                 (0x000000FF)
+  #define PCU_CR_MRC_ODT_POWER_SAVING_PCU_RESERVED_DEF                 (0x00000000)
+
+#define PCU_CR_THERM_STATUS_GT_PCU_REG                               (0x000059C0)
+  #define PCU_CR_THERM_STATUS_GT_PCU_THERMAL_MONITOR_STATUS_OFF        ( 0)
+  #define PCU_CR_THERM_STATUS_GT_PCU_THERMAL_MONITOR_STATUS_WID        ( 1)
+  #define PCU_CR_THERM_STATUS_GT_PCU_THERMAL_MONITOR_STATUS_MSK        (0x00000001)
+  #define PCU_CR_THERM_STATUS_GT_PCU_THERMAL_MONITOR_STATUS_MAX        (0x00000001)
+  #define PCU_CR_THERM_STATUS_GT_PCU_THERMAL_MONITOR_STATUS_DEF        (0x00000000)
+  #define PCU_CR_THERM_STATUS_GT_PCU_THERMAL_MONITOR_LOG_OFF           ( 1)
+  #define PCU_CR_THERM_STATUS_GT_PCU_THERMAL_MONITOR_LOG_WID           ( 1)
+  #define PCU_CR_THERM_STATUS_GT_PCU_THERMAL_MONITOR_LOG_MSK           (0x00000002)
+  #define PCU_CR_THERM_STATUS_GT_PCU_THERMAL_MONITOR_LOG_MAX           (0x00000001)
+  #define PCU_CR_THERM_STATUS_GT_PCU_THERMAL_MONITOR_LOG_DEF           (0x00000000)
+  #define PCU_CR_THERM_STATUS_GT_PCU_PROCHOT_STATUS_OFF                ( 2)
+  #define PCU_CR_THERM_STATUS_GT_PCU_PROCHOT_STATUS_WID                ( 1)
+  #define PCU_CR_THERM_STATUS_GT_PCU_PROCHOT_STATUS_MSK                (0x00000004)
+  #define PCU_CR_THERM_STATUS_GT_PCU_PROCHOT_STATUS_MAX                (0x00000001)
+  #define PCU_CR_THERM_STATUS_GT_PCU_PROCHOT_STATUS_DEF                (0x00000000)
+  #define PCU_CR_THERM_STATUS_GT_PCU_PROCHOT_LOG_OFF                   ( 3)
+  #define PCU_CR_THERM_STATUS_GT_PCU_PROCHOT_LOG_WID                   ( 1)
+  #define PCU_CR_THERM_STATUS_GT_PCU_PROCHOT_LOG_MSK                   (0x00000008)
+  #define PCU_CR_THERM_STATUS_GT_PCU_PROCHOT_LOG_MAX                   (0x00000001)
+  #define PCU_CR_THERM_STATUS_GT_PCU_PROCHOT_LOG_DEF                   (0x00000000)
+  #define PCU_CR_THERM_STATUS_GT_PCU_OUT_OF_SPEC_STATUS_OFF            ( 4)
+  #define PCU_CR_THERM_STATUS_GT_PCU_OUT_OF_SPEC_STATUS_WID            ( 1)
+  #define PCU_CR_THERM_STATUS_GT_PCU_OUT_OF_SPEC_STATUS_MSK            (0x00000010)
+  #define PCU_CR_THERM_STATUS_GT_PCU_OUT_OF_SPEC_STATUS_MAX            (0x00000001)
+  #define PCU_CR_THERM_STATUS_GT_PCU_OUT_OF_SPEC_STATUS_DEF            (0x00000000)
+  #define PCU_CR_THERM_STATUS_GT_PCU_OUT_OF_SPEC_LOG_OFF               ( 5)
+  #define PCU_CR_THERM_STATUS_GT_PCU_OUT_OF_SPEC_LOG_WID               ( 1)
+  #define PCU_CR_THERM_STATUS_GT_PCU_OUT_OF_SPEC_LOG_MSK               (0x00000020)
+  #define PCU_CR_THERM_STATUS_GT_PCU_OUT_OF_SPEC_LOG_MAX               (0x00000001)
+  #define PCU_CR_THERM_STATUS_GT_PCU_OUT_OF_SPEC_LOG_DEF               (0x00000000)
+  #define PCU_CR_THERM_STATUS_GT_PCU_THRESHOLD1_STATUS_OFF             ( 6)
+  #define PCU_CR_THERM_STATUS_GT_PCU_THRESHOLD1_STATUS_WID             ( 1)
+  #define PCU_CR_THERM_STATUS_GT_PCU_THRESHOLD1_STATUS_MSK             (0x00000040)
+  #define PCU_CR_THERM_STATUS_GT_PCU_THRESHOLD1_STATUS_MAX             (0x00000001)
+  #define PCU_CR_THERM_STATUS_GT_PCU_THRESHOLD1_STATUS_DEF             (0x00000000)
+  #define PCU_CR_THERM_STATUS_GT_PCU_THRESHOLD1_LOG_OFF                ( 7)
+  #define PCU_CR_THERM_STATUS_GT_PCU_THRESHOLD1_LOG_WID                ( 1)
+  #define PCU_CR_THERM_STATUS_GT_PCU_THRESHOLD1_LOG_MSK                (0x00000080)
+  #define PCU_CR_THERM_STATUS_GT_PCU_THRESHOLD1_LOG_MAX                (0x00000001)
+  #define PCU_CR_THERM_STATUS_GT_PCU_THRESHOLD1_LOG_DEF                (0x00000000)
+  #define PCU_CR_THERM_STATUS_GT_PCU_THRESHOLD2_STATUS_OFF             ( 8)
+  #define PCU_CR_THERM_STATUS_GT_PCU_THRESHOLD2_STATUS_WID             ( 1)
+  #define PCU_CR_THERM_STATUS_GT_PCU_THRESHOLD2_STATUS_MSK             (0x00000100)
+  #define PCU_CR_THERM_STATUS_GT_PCU_THRESHOLD2_STATUS_MAX             (0x00000001)
+  #define PCU_CR_THERM_STATUS_GT_PCU_THRESHOLD2_STATUS_DEF             (0x00000000)
+  #define PCU_CR_THERM_STATUS_GT_PCU_THRESHOLD2_LOG_OFF                ( 9)
+  #define PCU_CR_THERM_STATUS_GT_PCU_THRESHOLD2_LOG_WID                ( 1)
+  #define PCU_CR_THERM_STATUS_GT_PCU_THRESHOLD2_LOG_MSK                (0x00000200)
+  #define PCU_CR_THERM_STATUS_GT_PCU_THRESHOLD2_LOG_MAX                (0x00000001)
+  #define PCU_CR_THERM_STATUS_GT_PCU_THRESHOLD2_LOG_DEF                (0x00000000)
+  #define PCU_CR_THERM_STATUS_GT_PCU_POWER_LIMITATION_STATUS_OFF       (10)
+  #define PCU_CR_THERM_STATUS_GT_PCU_POWER_LIMITATION_STATUS_WID       ( 1)
+  #define PCU_CR_THERM_STATUS_GT_PCU_POWER_LIMITATION_STATUS_MSK       (0x00000400)
+  #define PCU_CR_THERM_STATUS_GT_PCU_POWER_LIMITATION_STATUS_MAX       (0x00000001)
+  #define PCU_CR_THERM_STATUS_GT_PCU_POWER_LIMITATION_STATUS_DEF       (0x00000000)
+  #define PCU_CR_THERM_STATUS_GT_PCU_POWER_LIMITATION_LOG_OFF          (11)
+  #define PCU_CR_THERM_STATUS_GT_PCU_POWER_LIMITATION_LOG_WID          ( 1)
+  #define PCU_CR_THERM_STATUS_GT_PCU_POWER_LIMITATION_LOG_MSK          (0x00000800)
+  #define PCU_CR_THERM_STATUS_GT_PCU_POWER_LIMITATION_LOG_MAX          (0x00000001)
+  #define PCU_CR_THERM_STATUS_GT_PCU_POWER_LIMITATION_LOG_DEF          (0x00000000)
+  #define PCU_CR_THERM_STATUS_GT_PCU_TEMPERATURE_OFF                   (16)
+  #define PCU_CR_THERM_STATUS_GT_PCU_TEMPERATURE_WID                   ( 7)
+  #define PCU_CR_THERM_STATUS_GT_PCU_TEMPERATURE_MSK                   (0x007F0000)
+  #define PCU_CR_THERM_STATUS_GT_PCU_TEMPERATURE_MAX                   (0x0000007F)
+  #define PCU_CR_THERM_STATUS_GT_PCU_TEMPERATURE_DEF                   (0x00000000)
+  #define PCU_CR_THERM_STATUS_GT_PCU_RESOLUTION_OFF                    (27)
+  #define PCU_CR_THERM_STATUS_GT_PCU_RESOLUTION_WID                    ( 4)
+  #define PCU_CR_THERM_STATUS_GT_PCU_RESOLUTION_MSK                    (0x78000000)
+  #define PCU_CR_THERM_STATUS_GT_PCU_RESOLUTION_MAX                    (0x0000000F)
+  #define PCU_CR_THERM_STATUS_GT_PCU_RESOLUTION_DEF                    (0x00000001)
+  #define PCU_CR_THERM_STATUS_GT_PCU_VALID_OFF                         (31)
+  #define PCU_CR_THERM_STATUS_GT_PCU_VALID_WID                         ( 1)
+  #define PCU_CR_THERM_STATUS_GT_PCU_VALID_MSK                         (0x80000000)
+  #define PCU_CR_THERM_STATUS_GT_PCU_VALID_MAX                         (0x00000001)
+  #define PCU_CR_THERM_STATUS_GT_PCU_VALID_DEF                         (0x00000000)
+
+#define PCU_CR_THERM_INTERRUPT_GT_PCU_REG                            (0x000059C4)
+  #define PCU_CR_THERM_INTERRUPT_GT_PCU_HIGH_TEMP_INT_ENABLE_OFF       ( 0)
+  #define PCU_CR_THERM_INTERRUPT_GT_PCU_HIGH_TEMP_INT_ENABLE_WID       ( 1)
+  #define PCU_CR_THERM_INTERRUPT_GT_PCU_HIGH_TEMP_INT_ENABLE_MSK       (0x00000001)
+  #define PCU_CR_THERM_INTERRUPT_GT_PCU_HIGH_TEMP_INT_ENABLE_MAX       (0x00000001)
+  #define PCU_CR_THERM_INTERRUPT_GT_PCU_HIGH_TEMP_INT_ENABLE_DEF       (0x00000000)
+  #define PCU_CR_THERM_INTERRUPT_GT_PCU_LOW_TEMP_INT_ENABLE_OFF        ( 1)
+  #define PCU_CR_THERM_INTERRUPT_GT_PCU_LOW_TEMP_INT_ENABLE_WID        ( 1)
+  #define PCU_CR_THERM_INTERRUPT_GT_PCU_LOW_TEMP_INT_ENABLE_MSK        (0x00000002)
+  #define PCU_CR_THERM_INTERRUPT_GT_PCU_LOW_TEMP_INT_ENABLE_MAX        (0x00000001)
+  #define PCU_CR_THERM_INTERRUPT_GT_PCU_LOW_TEMP_INT_ENABLE_DEF        (0x00000000)
+  #define PCU_CR_THERM_INTERRUPT_GT_PCU_PROCHOT_INT_ENABLE_OFF         ( 2)
+  #define PCU_CR_THERM_INTERRUPT_GT_PCU_PROCHOT_INT_ENABLE_WID         ( 1)
+  #define PCU_CR_THERM_INTERRUPT_GT_PCU_PROCHOT_INT_ENABLE_MSK         (0x00000004)
+  #define PCU_CR_THERM_INTERRUPT_GT_PCU_PROCHOT_INT_ENABLE_MAX         (0x00000001)
+  #define PCU_CR_THERM_INTERRUPT_GT_PCU_PROCHOT_INT_ENABLE_DEF         (0x00000000)
+  #define PCU_CR_THERM_INTERRUPT_GT_PCU_OUT_OF_SPEC_INT_ENABLE_OFF     ( 4)
+  #define PCU_CR_THERM_INTERRUPT_GT_PCU_OUT_OF_SPEC_INT_ENABLE_WID     ( 1)
+  #define PCU_CR_THERM_INTERRUPT_GT_PCU_OUT_OF_SPEC_INT_ENABLE_MSK     (0x00000010)
+  #define PCU_CR_THERM_INTERRUPT_GT_PCU_OUT_OF_SPEC_INT_ENABLE_MAX     (0x00000001)
+  #define PCU_CR_THERM_INTERRUPT_GT_PCU_OUT_OF_SPEC_INT_ENABLE_DEF     (0x00000000)
+  #define PCU_CR_THERM_INTERRUPT_GT_PCU_THRESHOLD_1_REL_TEMP_OFF       ( 8)
+  #define PCU_CR_THERM_INTERRUPT_GT_PCU_THRESHOLD_1_REL_TEMP_WID       ( 7)
+  #define PCU_CR_THERM_INTERRUPT_GT_PCU_THRESHOLD_1_REL_TEMP_MSK       (0x00007F00)
+  #define PCU_CR_THERM_INTERRUPT_GT_PCU_THRESHOLD_1_REL_TEMP_MAX       (0x0000007F)
+  #define PCU_CR_THERM_INTERRUPT_GT_PCU_THRESHOLD_1_REL_TEMP_DEF       (0x00000000)
+  #define PCU_CR_THERM_INTERRUPT_GT_PCU_THRESHOLD_1_INT_ENABLE_OFF     (15)
+  #define PCU_CR_THERM_INTERRUPT_GT_PCU_THRESHOLD_1_INT_ENABLE_WID     ( 1)
+  #define PCU_CR_THERM_INTERRUPT_GT_PCU_THRESHOLD_1_INT_ENABLE_MSK     (0x00008000)
+  #define PCU_CR_THERM_INTERRUPT_GT_PCU_THRESHOLD_1_INT_ENABLE_MAX     (0x00000001)
+  #define PCU_CR_THERM_INTERRUPT_GT_PCU_THRESHOLD_1_INT_ENABLE_DEF     (0x00000000)
+  #define PCU_CR_THERM_INTERRUPT_GT_PCU_THRESHOLD_2_REL_TEMP_OFF       (16)
+  #define PCU_CR_THERM_INTERRUPT_GT_PCU_THRESHOLD_2_REL_TEMP_WID       ( 7)
+  #define PCU_CR_THERM_INTERRUPT_GT_PCU_THRESHOLD_2_REL_TEMP_MSK       (0x007F0000)
+  #define PCU_CR_THERM_INTERRUPT_GT_PCU_THRESHOLD_2_REL_TEMP_MAX       (0x0000007F)
+  #define PCU_CR_THERM_INTERRUPT_GT_PCU_THRESHOLD_2_REL_TEMP_DEF       (0x00000000)
+  #define PCU_CR_THERM_INTERRUPT_GT_PCU_THRESHOLD_2_INT_ENABLE_OFF     (23)
+  #define PCU_CR_THERM_INTERRUPT_GT_PCU_THRESHOLD_2_INT_ENABLE_WID     ( 1)
+  #define PCU_CR_THERM_INTERRUPT_GT_PCU_THRESHOLD_2_INT_ENABLE_MSK     (0x00800000)
+  #define PCU_CR_THERM_INTERRUPT_GT_PCU_THRESHOLD_2_INT_ENABLE_MAX     (0x00000001)
+  #define PCU_CR_THERM_INTERRUPT_GT_PCU_THRESHOLD_2_INT_ENABLE_DEF     (0x00000000)
+  #define PCU_CR_THERM_INTERRUPT_GT_PCU_POWER_INT_ENABLE_OFF           (24)
+  #define PCU_CR_THERM_INTERRUPT_GT_PCU_POWER_INT_ENABLE_WID           ( 1)
+  #define PCU_CR_THERM_INTERRUPT_GT_PCU_POWER_INT_ENABLE_MSK           (0x01000000)
+  #define PCU_CR_THERM_INTERRUPT_GT_PCU_POWER_INT_ENABLE_MAX           (0x00000001)
+  #define PCU_CR_THERM_INTERRUPT_GT_PCU_POWER_INT_ENABLE_DEF           (0x00000000)
+
+#define PCU_CR_DEVICE_IDLE_DURATION_OVERRIDE_PCU_REG                 (0x000059C8)
+  #define PCU_CR_DEVICE_IDLE_DURATION_OVERRIDE_PCU_RESERVED_OFF        ( 0)
+  #define PCU_CR_DEVICE_IDLE_DURATION_OVERRIDE_PCU_RESERVED_WID        ( 1)
+  #define PCU_CR_DEVICE_IDLE_DURATION_OVERRIDE_PCU_RESERVED_MSK        (0x00000001)
+  #define PCU_CR_DEVICE_IDLE_DURATION_OVERRIDE_PCU_RESERVED_MAX        (0x00000001)
+  #define PCU_CR_DEVICE_IDLE_DURATION_OVERRIDE_PCU_RESERVED_DEF        (0x00000000)
+  #define PCU_CR_DEVICE_IDLE_DURATION_OVERRIDE_PCU_VALID_OFF           ( 1)
+  #define PCU_CR_DEVICE_IDLE_DURATION_OVERRIDE_PCU_VALID_WID           ( 1)
+  #define PCU_CR_DEVICE_IDLE_DURATION_OVERRIDE_PCU_VALID_MSK           (0x00000002)
+  #define PCU_CR_DEVICE_IDLE_DURATION_OVERRIDE_PCU_VALID_MAX           (0x00000001)
+  #define PCU_CR_DEVICE_IDLE_DURATION_OVERRIDE_PCU_VALID_DEF           (0x00000000)
+  #define PCU_CR_DEVICE_IDLE_DURATION_OVERRIDE_PCU_RESERVED_BITS_OFF   ( 2)
+  #define PCU_CR_DEVICE_IDLE_DURATION_OVERRIDE_PCU_RESERVED_BITS_WID   ( 4)
+  #define PCU_CR_DEVICE_IDLE_DURATION_OVERRIDE_PCU_RESERVED_BITS_MSK   (0x0000003C)
+  #define PCU_CR_DEVICE_IDLE_DURATION_OVERRIDE_PCU_RESERVED_BITS_MAX   (0x0000000F)
+  #define PCU_CR_DEVICE_IDLE_DURATION_OVERRIDE_PCU_RESERVED_BITS_DEF   (0x00000000)
+  #define PCU_CR_DEVICE_IDLE_DURATION_OVERRIDE_PCU_OD_OFF              ( 6)
+  #define PCU_CR_DEVICE_IDLE_DURATION_OVERRIDE_PCU_OD_WID              ( 1)
+  #define PCU_CR_DEVICE_IDLE_DURATION_OVERRIDE_PCU_OD_MSK              (0x00000040)
+  #define PCU_CR_DEVICE_IDLE_DURATION_OVERRIDE_PCU_OD_MAX              (0x00000001)
+  #define PCU_CR_DEVICE_IDLE_DURATION_OVERRIDE_PCU_OD_DEF              (0x00000000)
+  #define PCU_CR_DEVICE_IDLE_DURATION_OVERRIDE_PCU_IM_OFF              ( 7)
+  #define PCU_CR_DEVICE_IDLE_DURATION_OVERRIDE_PCU_IM_WID              ( 1)
+  #define PCU_CR_DEVICE_IDLE_DURATION_OVERRIDE_PCU_IM_MSK              (0x00000080)
+  #define PCU_CR_DEVICE_IDLE_DURATION_OVERRIDE_PCU_IM_MAX              (0x00000001)
+  #define PCU_CR_DEVICE_IDLE_DURATION_OVERRIDE_PCU_IM_DEF              (0x00000000)
+  #define PCU_CR_DEVICE_IDLE_DURATION_OVERRIDE_PCU_NEXT_DEVICE_ACTIVITY_OFF ( 8)
+  #define PCU_CR_DEVICE_IDLE_DURATION_OVERRIDE_PCU_NEXT_DEVICE_ACTIVITY_WID (21)
+  #define PCU_CR_DEVICE_IDLE_DURATION_OVERRIDE_PCU_NEXT_DEVICE_ACTIVITY_MSK (0x1FFFFF00)
+  #define PCU_CR_DEVICE_IDLE_DURATION_OVERRIDE_PCU_NEXT_DEVICE_ACTIVITY_MAX (0x001FFFFF)
+  #define PCU_CR_DEVICE_IDLE_DURATION_OVERRIDE_PCU_NEXT_DEVICE_ACTIVITY_DEF (0x00000000)
+  #define PCU_CR_DEVICE_IDLE_DURATION_OVERRIDE_PCU_DISABLE_MDID_EVALUATION_OFF (29)
+  #define PCU_CR_DEVICE_IDLE_DURATION_OVERRIDE_PCU_DISABLE_MDID_EVALUATION_WID ( 1)
+  #define PCU_CR_DEVICE_IDLE_DURATION_OVERRIDE_PCU_DISABLE_MDID_EVALUATION_MSK (0x20000000)
+  #define PCU_CR_DEVICE_IDLE_DURATION_OVERRIDE_PCU_DISABLE_MDID_EVALUATION_MAX (0x00000001)
+  #define PCU_CR_DEVICE_IDLE_DURATION_OVERRIDE_PCU_DISABLE_MDID_EVALUATION_DEF (0x00000000)
+  #define PCU_CR_DEVICE_IDLE_DURATION_OVERRIDE_PCU_FORCE_MDID_OVERRIDE_OFF (30)
+  #define PCU_CR_DEVICE_IDLE_DURATION_OVERRIDE_PCU_FORCE_MDID_OVERRIDE_WID ( 1)
+  #define PCU_CR_DEVICE_IDLE_DURATION_OVERRIDE_PCU_FORCE_MDID_OVERRIDE_MSK (0x40000000)
+  #define PCU_CR_DEVICE_IDLE_DURATION_OVERRIDE_PCU_FORCE_MDID_OVERRIDE_MAX (0x00000001)
+  #define PCU_CR_DEVICE_IDLE_DURATION_OVERRIDE_PCU_FORCE_MDID_OVERRIDE_DEF (0x00000000)
+
+#define PCU_CR_GRAPHICS_INTERRUPT_RESPONSE_TIME_PCU_REG              (0x000059D0)
+  #define PCU_CR_GRAPHICS_INTERRUPT_RESPONSE_TIME_PCU_VALUE_OFF        ( 0)
+  #define PCU_CR_GRAPHICS_INTERRUPT_RESPONSE_TIME_PCU_VALUE_WID        (10)
+  #define PCU_CR_GRAPHICS_INTERRUPT_RESPONSE_TIME_PCU_VALUE_MSK        (0x000003FF)
+  #define PCU_CR_GRAPHICS_INTERRUPT_RESPONSE_TIME_PCU_VALUE_MAX        (0x000003FF)
+  #define PCU_CR_GRAPHICS_INTERRUPT_RESPONSE_TIME_PCU_VALUE_DEF        (0x00000000)
+  #define PCU_CR_GRAPHICS_INTERRUPT_RESPONSE_TIME_PCU_MULTIPLIER_OFF   (10)
+  #define PCU_CR_GRAPHICS_INTERRUPT_RESPONSE_TIME_PCU_MULTIPLIER_WID   ( 3)
+  #define PCU_CR_GRAPHICS_INTERRUPT_RESPONSE_TIME_PCU_MULTIPLIER_MSK   (0x00001C00)
+  #define PCU_CR_GRAPHICS_INTERRUPT_RESPONSE_TIME_PCU_MULTIPLIER_MAX   (0x00000007)
+  #define PCU_CR_GRAPHICS_INTERRUPT_RESPONSE_TIME_PCU_MULTIPLIER_DEF   (0x00000000)
+  #define PCU_CR_GRAPHICS_INTERRUPT_RESPONSE_TIME_PCU_VALID_OFF        (15)
+  #define PCU_CR_GRAPHICS_INTERRUPT_RESPONSE_TIME_PCU_VALID_WID        ( 1)
+  #define PCU_CR_GRAPHICS_INTERRUPT_RESPONSE_TIME_PCU_VALID_MSK        (0x00008000)
+  #define PCU_CR_GRAPHICS_INTERRUPT_RESPONSE_TIME_PCU_VALID_MAX        (0x00000001)
+  #define PCU_CR_GRAPHICS_INTERRUPT_RESPONSE_TIME_PCU_VALID_DEF        (0x00000000)
+
+#define PCU_CR_CHAP_CONFIG_PCU_REG                                   (0x00005A00)
+  #define PCU_CR_CHAP_CONFIG_PCU_PECI_CMD_OFF                          ( 4)
+  #define PCU_CR_CHAP_CONFIG_PCU_PECI_CMD_WID                          ( 8)
+  #define PCU_CR_CHAP_CONFIG_PCU_PECI_CMD_MSK                          (0x00000FF0)
+  #define PCU_CR_CHAP_CONFIG_PCU_PECI_CMD_MAX                          (0x000000FF)
+  #define PCU_CR_CHAP_CONFIG_PCU_PECI_CMD_DEF                          (0x00000000)
+
+#define PCU_CR_CHAP_THRESHOLD2_PCU_REG                               (0x00005A08)
+  #define PCU_CR_CHAP_THRESHOLD2_PCU_FREQ_TH1_OFF                      ( 0)
+  #define PCU_CR_CHAP_THRESHOLD2_PCU_FREQ_TH1_WID                      ( 6)
+  #define PCU_CR_CHAP_THRESHOLD2_PCU_FREQ_TH1_MSK                      (0x0000003F)
+  #define PCU_CR_CHAP_THRESHOLD2_PCU_FREQ_TH1_MAX                      (0x0000003F)
+  #define PCU_CR_CHAP_THRESHOLD2_PCU_FREQ_TH1_DEF                      (0x00000000)
+  #define PCU_CR_CHAP_THRESHOLD2_PCU_FREQ_TH2_OFF                      ( 8)
+  #define PCU_CR_CHAP_THRESHOLD2_PCU_FREQ_TH2_WID                      ( 6)
+  #define PCU_CR_CHAP_THRESHOLD2_PCU_FREQ_TH2_MSK                      (0x00003F00)
+  #define PCU_CR_CHAP_THRESHOLD2_PCU_FREQ_TH2_MAX                      (0x0000003F)
+  #define PCU_CR_CHAP_THRESHOLD2_PCU_FREQ_TH2_DEF                      (0x00000000)
+  #define PCU_CR_CHAP_THRESHOLD2_PCU_FREQ_TH3_OFF                      (16)
+  #define PCU_CR_CHAP_THRESHOLD2_PCU_FREQ_TH3_WID                      ( 6)
+  #define PCU_CR_CHAP_THRESHOLD2_PCU_FREQ_TH3_MSK                      (0x003F0000)
+  #define PCU_CR_CHAP_THRESHOLD2_PCU_FREQ_TH3_MAX                      (0x0000003F)
+  #define PCU_CR_CHAP_THRESHOLD2_PCU_FREQ_TH3_DEF                      (0x00000000)
+
+#define PCU_CR_ENERGY_DEBUG_PCU_REG                                  (0x00005B04)
+  #define PCU_CR_ENERGY_DEBUG_PCU_DEBUG_ENERGY_PP0_VALUE_OFF           ( 0)
+  #define PCU_CR_ENERGY_DEBUG_PCU_DEBUG_ENERGY_PP0_VALUE_WID           (10)
+  #define PCU_CR_ENERGY_DEBUG_PCU_DEBUG_ENERGY_PP0_VALUE_MSK           (0x000003FF)
+  #define PCU_CR_ENERGY_DEBUG_PCU_DEBUG_ENERGY_PP0_VALUE_MAX           (0x000003FF)
+  #define PCU_CR_ENERGY_DEBUG_PCU_DEBUG_ENERGY_PP0_VALUE_DEF           (0x00000000)
+  #define PCU_CR_ENERGY_DEBUG_PCU_DEBUG_ENERGY_PP1_VALUE_OFF           (10)
+  #define PCU_CR_ENERGY_DEBUG_PCU_DEBUG_ENERGY_PP1_VALUE_WID           (10)
+  #define PCU_CR_ENERGY_DEBUG_PCU_DEBUG_ENERGY_PP1_VALUE_MSK           (0x000FFC00)
+  #define PCU_CR_ENERGY_DEBUG_PCU_DEBUG_ENERGY_PP1_VALUE_MAX           (0x000003FF)
+  #define PCU_CR_ENERGY_DEBUG_PCU_DEBUG_ENERGY_PP1_VALUE_DEF           (0x00000000)
+  #define PCU_CR_ENERGY_DEBUG_PCU_DEBUG_ENERGY_SA_VALUE_OFF            (20)
+  #define PCU_CR_ENERGY_DEBUG_PCU_DEBUG_ENERGY_SA_VALUE_WID            (10)
+  #define PCU_CR_ENERGY_DEBUG_PCU_DEBUG_ENERGY_SA_VALUE_MSK            (0x3FF00000)
+  #define PCU_CR_ENERGY_DEBUG_PCU_DEBUG_ENERGY_SA_VALUE_MAX            (0x000003FF)
+  #define PCU_CR_ENERGY_DEBUG_PCU_DEBUG_ENERGY_SA_VALUE_DEF            (0x00000000)
+
+#define PCU_CR_SSKPD_PCU_REG                                         (0x00005D10)
+  #define PCU_CR_SSKPD_PCU_SKPD_OFF                                    ( 0)
+  #define PCU_CR_SSKPD_PCU_SKPD_WID                                    (64)
+  #define PCU_CR_SSKPD_PCU_SKPD_MSK                                    (0xFFFFFFFFFFFFFFFF)
+  #define PCU_CR_SSKPD_PCU_SKPD_MAX                                    (0xFFFFFFFFFFFFFFFF)
+  #define PCU_CR_SSKPD_PCU_SKPD_DEF                                    (0x00000000)
+
+#define PCU_CR_C2C3TT_PCU_REG                                        (0x00005D20)
+  #define PCU_CR_C2C3TT_PCU_PPDN_INIT_OFF                              ( 0)
+  #define PCU_CR_C2C3TT_PCU_PPDN_INIT_WID                              (12)
+  #define PCU_CR_C2C3TT_PCU_PPDN_INIT_MSK                              (0x00000FFF)
+  #define PCU_CR_C2C3TT_PCU_PPDN_INIT_MAX                              (0x00000FFF)
+  #define PCU_CR_C2C3TT_PCU_PPDN_INIT_DEF                              (0x00000005)
+
+#define PCU_CR_C2_DDR_TT_PCU_REG                                     (0x00005D24)
+  #define PCU_CR_C2_DDR_TT_PCU_DDR_TIMER_VALUE_OFF                     ( 0)
+  #define PCU_CR_C2_DDR_TT_PCU_DDR_TIMER_VALUE_WID                     (13)
+  #define PCU_CR_C2_DDR_TT_PCU_DDR_TIMER_VALUE_MSK                     (0x00001FFF)
+  #define PCU_CR_C2_DDR_TT_PCU_DDR_TIMER_VALUE_MAX                     (0x00001FFF)
+  #define PCU_CR_C2_DDR_TT_PCU_DDR_TIMER_VALUE_DEF                     (0x000001F4)
+
+#define PCU_CR_PCIE_ILTR_OVRD_PCU_REG                                (0x00005D30)
+  #define PCU_CR_PCIE_ILTR_OVRD_PCU_NSTL_OFF                           ( 0)
+  #define PCU_CR_PCIE_ILTR_OVRD_PCU_NSTL_WID                           (10)
+  #define PCU_CR_PCIE_ILTR_OVRD_PCU_NSTL_MSK                           (0x000003FF)
+  #define PCU_CR_PCIE_ILTR_OVRD_PCU_NSTL_MAX                           (0x000003FF)
+  #define PCU_CR_PCIE_ILTR_OVRD_PCU_NSTL_DEF                           (0x00000000)
+  #define PCU_CR_PCIE_ILTR_OVRD_PCU_MULTIPLIER_OFF                     (10)
+  #define PCU_CR_PCIE_ILTR_OVRD_PCU_MULTIPLIER_WID                     ( 3)
+  #define PCU_CR_PCIE_ILTR_OVRD_PCU_MULTIPLIER_MSK                     (0x00001C00)
+  #define PCU_CR_PCIE_ILTR_OVRD_PCU_MULTIPLIER_MAX                     (0x00000007)
+  #define PCU_CR_PCIE_ILTR_OVRD_PCU_MULTIPLIER_DEF                     (0x00000000)
+  #define PCU_CR_PCIE_ILTR_OVRD_PCU_FORCE_NL_OFF                       (14)
+  #define PCU_CR_PCIE_ILTR_OVRD_PCU_FORCE_NL_WID                       ( 1)
+  #define PCU_CR_PCIE_ILTR_OVRD_PCU_FORCE_NL_MSK                       (0x00004000)
+  #define PCU_CR_PCIE_ILTR_OVRD_PCU_FORCE_NL_MAX                       (0x00000001)
+  #define PCU_CR_PCIE_ILTR_OVRD_PCU_FORCE_NL_DEF                       (0x00000000)
+  #define PCU_CR_PCIE_ILTR_OVRD_PCU_NL_V_OFF                           (15)
+  #define PCU_CR_PCIE_ILTR_OVRD_PCU_NL_V_WID                           ( 1)
+  #define PCU_CR_PCIE_ILTR_OVRD_PCU_NL_V_MSK                           (0x00008000)
+  #define PCU_CR_PCIE_ILTR_OVRD_PCU_NL_V_MAX                           (0x00000001)
+  #define PCU_CR_PCIE_ILTR_OVRD_PCU_NL_V_DEF                           (0x00000000)
+  #define PCU_CR_PCIE_ILTR_OVRD_PCU_SXL_OFF                            (16)
+  #define PCU_CR_PCIE_ILTR_OVRD_PCU_SXL_WID                            (10)
+  #define PCU_CR_PCIE_ILTR_OVRD_PCU_SXL_MSK                            (0x03FF0000)
+  #define PCU_CR_PCIE_ILTR_OVRD_PCU_SXL_MAX                            (0x000003FF)
+  #define PCU_CR_PCIE_ILTR_OVRD_PCU_SXL_DEF                            (0x00000000)
+  #define PCU_CR_PCIE_ILTR_OVRD_PCU_SXLM_OFF                           (26)
+  #define PCU_CR_PCIE_ILTR_OVRD_PCU_SXLM_WID                           ( 3)
+  #define PCU_CR_PCIE_ILTR_OVRD_PCU_SXLM_MSK                           (0x1C000000)
+  #define PCU_CR_PCIE_ILTR_OVRD_PCU_SXLM_MAX                           (0x00000007)
+  #define PCU_CR_PCIE_ILTR_OVRD_PCU_SXLM_DEF                           (0x00000000)
+  #define PCU_CR_PCIE_ILTR_OVRD_PCU_FORCE_SXL_OFF                      (30)
+  #define PCU_CR_PCIE_ILTR_OVRD_PCU_FORCE_SXL_WID                      ( 1)
+  #define PCU_CR_PCIE_ILTR_OVRD_PCU_FORCE_SXL_MSK                      (0x40000000)
+  #define PCU_CR_PCIE_ILTR_OVRD_PCU_FORCE_SXL_MAX                      (0x00000001)
+  #define PCU_CR_PCIE_ILTR_OVRD_PCU_FORCE_SXL_DEF                      (0x00000000)
+  #define PCU_CR_PCIE_ILTR_OVRD_PCU_SXL_V_OFF                          (31)
+  #define PCU_CR_PCIE_ILTR_OVRD_PCU_SXL_V_WID                          ( 1)
+  #define PCU_CR_PCIE_ILTR_OVRD_PCU_SXL_V_MSK                          (0x80000000)
+  #define PCU_CR_PCIE_ILTR_OVRD_PCU_SXL_V_MAX                          (0x00000001)
+  #define PCU_CR_PCIE_ILTR_OVRD_PCU_SXL_V_DEF                          (0x00000000)
+
+#define PCU_CR_PCIE_ILTR_VAL_PCU_0_REG                               (0x00005D34)
+  #define PCU_CR_PCIE_ILTR_VAL_PCU_0_NL_VALUE_OFF                      ( 0)
+  #define PCU_CR_PCIE_ILTR_VAL_PCU_0_NL_VALUE_WID                      (10)
+  #define PCU_CR_PCIE_ILTR_VAL_PCU_0_NL_VALUE_MSK                      (0x000003FF)
+  #define PCU_CR_PCIE_ILTR_VAL_PCU_0_NL_VALUE_MAX                      (0x000003FF)
+  #define PCU_CR_PCIE_ILTR_VAL_PCU_0_NL_VALUE_DEF                      (0x00000000)
+  #define PCU_CR_PCIE_ILTR_VAL_PCU_0_NL_SCALE_OFF                      (10)
+  #define PCU_CR_PCIE_ILTR_VAL_PCU_0_NL_SCALE_WID                      ( 3)
+  #define PCU_CR_PCIE_ILTR_VAL_PCU_0_NL_SCALE_MSK                      (0x00001C00)
+  #define PCU_CR_PCIE_ILTR_VAL_PCU_0_NL_SCALE_MAX                      (0x00000007)
+  #define PCU_CR_PCIE_ILTR_VAL_PCU_0_NL_SCALE_DEF                      (0x00000000)
+  #define PCU_CR_PCIE_ILTR_VAL_PCU_0_NL_RESERVED_OFF                   (13)
+  #define PCU_CR_PCIE_ILTR_VAL_PCU_0_NL_RESERVED_WID                   ( 2)
+  #define PCU_CR_PCIE_ILTR_VAL_PCU_0_NL_RESERVED_MSK                   (0x00006000)
+  #define PCU_CR_PCIE_ILTR_VAL_PCU_0_NL_RESERVED_MAX                   (0x00000003)
+  #define PCU_CR_PCIE_ILTR_VAL_PCU_0_NL_RESERVED_DEF                   (0x00000000)
+  #define PCU_CR_PCIE_ILTR_VAL_PCU_0_NL_VALID_OFF                      (15)
+  #define PCU_CR_PCIE_ILTR_VAL_PCU_0_NL_VALID_WID                      ( 1)
+  #define PCU_CR_PCIE_ILTR_VAL_PCU_0_NL_VALID_MSK                      (0x00008000)
+  #define PCU_CR_PCIE_ILTR_VAL_PCU_0_NL_VALID_MAX                      (0x00000001)
+  #define PCU_CR_PCIE_ILTR_VAL_PCU_0_NL_VALID_DEF                      (0x00000000)
+  #define PCU_CR_PCIE_ILTR_VAL_PCU_0_SXL_VALUE_OFF                     (16)
+  #define PCU_CR_PCIE_ILTR_VAL_PCU_0_SXL_VALUE_WID                     (10)
+  #define PCU_CR_PCIE_ILTR_VAL_PCU_0_SXL_VALUE_MSK                     (0x03FF0000)
+  #define PCU_CR_PCIE_ILTR_VAL_PCU_0_SXL_VALUE_MAX                     (0x000003FF)
+  #define PCU_CR_PCIE_ILTR_VAL_PCU_0_SXL_VALUE_DEF                     (0x00000000)
+  #define PCU_CR_PCIE_ILTR_VAL_PCU_0_SXL_SCALE_OFF                     (26)
+  #define PCU_CR_PCIE_ILTR_VAL_PCU_0_SXL_SCALE_WID                     ( 3)
+  #define PCU_CR_PCIE_ILTR_VAL_PCU_0_SXL_SCALE_MSK                     (0x1C000000)
+  #define PCU_CR_PCIE_ILTR_VAL_PCU_0_SXL_SCALE_MAX                     (0x00000007)
+  #define PCU_CR_PCIE_ILTR_VAL_PCU_0_SXL_SCALE_DEF                     (0x00000000)
+  #define PCU_CR_PCIE_ILTR_VAL_PCU_0_SXL_RESERVED_OFF                  (29)
+  #define PCU_CR_PCIE_ILTR_VAL_PCU_0_SXL_RESERVED_WID                  ( 2)
+  #define PCU_CR_PCIE_ILTR_VAL_PCU_0_SXL_RESERVED_MSK                  (0x60000000)
+  #define PCU_CR_PCIE_ILTR_VAL_PCU_0_SXL_RESERVED_MAX                  (0x00000003)
+  #define PCU_CR_PCIE_ILTR_VAL_PCU_0_SXL_RESERVED_DEF                  (0x00000000)
+  #define PCU_CR_PCIE_ILTR_VAL_PCU_0_SXL_VALID_OFF                     (31)
+  #define PCU_CR_PCIE_ILTR_VAL_PCU_0_SXL_VALID_WID                     ( 1)
+  #define PCU_CR_PCIE_ILTR_VAL_PCU_0_SXL_VALID_MSK                     (0x80000000)
+  #define PCU_CR_PCIE_ILTR_VAL_PCU_0_SXL_VALID_MAX                     (0x00000001)
+  #define PCU_CR_PCIE_ILTR_VAL_PCU_0_SXL_VALID_DEF                     (0x00000000)
+
+#define PCU_CR_PCIE_ILTR_VAL_PCU_1_REG                               (0x00005D38)
+  #define PCU_CR_PCIE_ILTR_VAL_PCU_1_NL_VALUE_OFF                      ( 0)
+  #define PCU_CR_PCIE_ILTR_VAL_PCU_1_NL_VALUE_WID                      (10)
+  #define PCU_CR_PCIE_ILTR_VAL_PCU_1_NL_VALUE_MSK                      (0x000003FF)
+  #define PCU_CR_PCIE_ILTR_VAL_PCU_1_NL_VALUE_MAX                      (0x000003FF)
+  #define PCU_CR_PCIE_ILTR_VAL_PCU_1_NL_VALUE_DEF                      (0x00000000)
+  #define PCU_CR_PCIE_ILTR_VAL_PCU_1_NL_SCALE_OFF                      (10)
+  #define PCU_CR_PCIE_ILTR_VAL_PCU_1_NL_SCALE_WID                      ( 3)
+  #define PCU_CR_PCIE_ILTR_VAL_PCU_1_NL_SCALE_MSK                      (0x00001C00)
+  #define PCU_CR_PCIE_ILTR_VAL_PCU_1_NL_SCALE_MAX                      (0x00000007)
+  #define PCU_CR_PCIE_ILTR_VAL_PCU_1_NL_SCALE_DEF                      (0x00000000)
+  #define PCU_CR_PCIE_ILTR_VAL_PCU_1_NL_RESERVED_OFF                   (13)
+  #define PCU_CR_PCIE_ILTR_VAL_PCU_1_NL_RESERVED_WID                   ( 2)
+  #define PCU_CR_PCIE_ILTR_VAL_PCU_1_NL_RESERVED_MSK                   (0x00006000)
+  #define PCU_CR_PCIE_ILTR_VAL_PCU_1_NL_RESERVED_MAX                   (0x00000003)
+  #define PCU_CR_PCIE_ILTR_VAL_PCU_1_NL_RESERVED_DEF                   (0x00000000)
+  #define PCU_CR_PCIE_ILTR_VAL_PCU_1_NL_VALID_OFF                      (15)
+  #define PCU_CR_PCIE_ILTR_VAL_PCU_1_NL_VALID_WID                      ( 1)
+  #define PCU_CR_PCIE_ILTR_VAL_PCU_1_NL_VALID_MSK                      (0x00008000)
+  #define PCU_CR_PCIE_ILTR_VAL_PCU_1_NL_VALID_MAX                      (0x00000001)
+  #define PCU_CR_PCIE_ILTR_VAL_PCU_1_NL_VALID_DEF                      (0x00000000)
+  #define PCU_CR_PCIE_ILTR_VAL_PCU_1_SXL_VALUE_OFF                     (16)
+  #define PCU_CR_PCIE_ILTR_VAL_PCU_1_SXL_VALUE_WID                     (10)
+  #define PCU_CR_PCIE_ILTR_VAL_PCU_1_SXL_VALUE_MSK                     (0x03FF0000)
+  #define PCU_CR_PCIE_ILTR_VAL_PCU_1_SXL_VALUE_MAX                     (0x000003FF)
+  #define PCU_CR_PCIE_ILTR_VAL_PCU_1_SXL_VALUE_DEF                     (0x00000000)
+  #define PCU_CR_PCIE_ILTR_VAL_PCU_1_SXL_SCALE_OFF                     (26)
+  #define PCU_CR_PCIE_ILTR_VAL_PCU_1_SXL_SCALE_WID                     ( 3)
+  #define PCU_CR_PCIE_ILTR_VAL_PCU_1_SXL_SCALE_MSK                     (0x1C000000)
+  #define PCU_CR_PCIE_ILTR_VAL_PCU_1_SXL_SCALE_MAX                     (0x00000007)
+  #define PCU_CR_PCIE_ILTR_VAL_PCU_1_SXL_SCALE_DEF                     (0x00000000)
+  #define PCU_CR_PCIE_ILTR_VAL_PCU_1_SXL_RESERVED_OFF                  (29)
+  #define PCU_CR_PCIE_ILTR_VAL_PCU_1_SXL_RESERVED_WID                  ( 2)
+  #define PCU_CR_PCIE_ILTR_VAL_PCU_1_SXL_RESERVED_MSK                  (0x60000000)
+  #define PCU_CR_PCIE_ILTR_VAL_PCU_1_SXL_RESERVED_MAX                  (0x00000003)
+  #define PCU_CR_PCIE_ILTR_VAL_PCU_1_SXL_RESERVED_DEF                  (0x00000000)
+  #define PCU_CR_PCIE_ILTR_VAL_PCU_1_SXL_VALID_OFF                     (31)
+  #define PCU_CR_PCIE_ILTR_VAL_PCU_1_SXL_VALID_WID                     ( 1)
+  #define PCU_CR_PCIE_ILTR_VAL_PCU_1_SXL_VALID_MSK                     (0x80000000)
+  #define PCU_CR_PCIE_ILTR_VAL_PCU_1_SXL_VALID_MAX                     (0x00000001)
+  #define PCU_CR_PCIE_ILTR_VAL_PCU_1_SXL_VALID_DEF                     (0x00000000)
+
+#define PCU_CR_PCIE_ILTR_VAL_PCU_2_REG                               (0x00005D3C)
+  #define PCU_CR_PCIE_ILTR_VAL_PCU_2_NL_VALUE_OFF                      ( 0)
+  #define PCU_CR_PCIE_ILTR_VAL_PCU_2_NL_VALUE_WID                      (10)
+  #define PCU_CR_PCIE_ILTR_VAL_PCU_2_NL_VALUE_MSK                      (0x000003FF)
+  #define PCU_CR_PCIE_ILTR_VAL_PCU_2_NL_VALUE_MAX                      (0x000003FF)
+  #define PCU_CR_PCIE_ILTR_VAL_PCU_2_NL_VALUE_DEF                      (0x00000000)
+  #define PCU_CR_PCIE_ILTR_VAL_PCU_2_NL_SCALE_OFF                      (10)
+  #define PCU_CR_PCIE_ILTR_VAL_PCU_2_NL_SCALE_WID                      ( 3)
+  #define PCU_CR_PCIE_ILTR_VAL_PCU_2_NL_SCALE_MSK                      (0x00001C00)
+  #define PCU_CR_PCIE_ILTR_VAL_PCU_2_NL_SCALE_MAX                      (0x00000007)
+  #define PCU_CR_PCIE_ILTR_VAL_PCU_2_NL_SCALE_DEF                      (0x00000000)
+  #define PCU_CR_PCIE_ILTR_VAL_PCU_2_NL_RESERVED_OFF                   (13)
+  #define PCU_CR_PCIE_ILTR_VAL_PCU_2_NL_RESERVED_WID                   ( 2)
+  #define PCU_CR_PCIE_ILTR_VAL_PCU_2_NL_RESERVED_MSK                   (0x00006000)
+  #define PCU_CR_PCIE_ILTR_VAL_PCU_2_NL_RESERVED_MAX                   (0x00000003)
+  #define PCU_CR_PCIE_ILTR_VAL_PCU_2_NL_RESERVED_DEF                   (0x00000000)
+  #define PCU_CR_PCIE_ILTR_VAL_PCU_2_NL_VALID_OFF                      (15)
+  #define PCU_CR_PCIE_ILTR_VAL_PCU_2_NL_VALID_WID                      ( 1)
+  #define PCU_CR_PCIE_ILTR_VAL_PCU_2_NL_VALID_MSK                      (0x00008000)
+  #define PCU_CR_PCIE_ILTR_VAL_PCU_2_NL_VALID_MAX                      (0x00000001)
+  #define PCU_CR_PCIE_ILTR_VAL_PCU_2_NL_VALID_DEF                      (0x00000000)
+  #define PCU_CR_PCIE_ILTR_VAL_PCU_2_SXL_VALUE_OFF                     (16)
+  #define PCU_CR_PCIE_ILTR_VAL_PCU_2_SXL_VALUE_WID                     (10)
+  #define PCU_CR_PCIE_ILTR_VAL_PCU_2_SXL_VALUE_MSK                     (0x03FF0000)
+  #define PCU_CR_PCIE_ILTR_VAL_PCU_2_SXL_VALUE_MAX                     (0x000003FF)
+  #define PCU_CR_PCIE_ILTR_VAL_PCU_2_SXL_VALUE_DEF                     (0x00000000)
+  #define PCU_CR_PCIE_ILTR_VAL_PCU_2_SXL_SCALE_OFF                     (26)
+  #define PCU_CR_PCIE_ILTR_VAL_PCU_2_SXL_SCALE_WID                     ( 3)
+  #define PCU_CR_PCIE_ILTR_VAL_PCU_2_SXL_SCALE_MSK                     (0x1C000000)
+  #define PCU_CR_PCIE_ILTR_VAL_PCU_2_SXL_SCALE_MAX                     (0x00000007)
+  #define PCU_CR_PCIE_ILTR_VAL_PCU_2_SXL_SCALE_DEF                     (0x00000000)
+  #define PCU_CR_PCIE_ILTR_VAL_PCU_2_SXL_RESERVED_OFF                  (29)
+  #define PCU_CR_PCIE_ILTR_VAL_PCU_2_SXL_RESERVED_WID                  ( 2)
+  #define PCU_CR_PCIE_ILTR_VAL_PCU_2_SXL_RESERVED_MSK                  (0x60000000)
+  #define PCU_CR_PCIE_ILTR_VAL_PCU_2_SXL_RESERVED_MAX                  (0x00000003)
+  #define PCU_CR_PCIE_ILTR_VAL_PCU_2_SXL_RESERVED_DEF                  (0x00000000)
+  #define PCU_CR_PCIE_ILTR_VAL_PCU_2_SXL_VALID_OFF                     (31)
+  #define PCU_CR_PCIE_ILTR_VAL_PCU_2_SXL_VALID_WID                     ( 1)
+  #define PCU_CR_PCIE_ILTR_VAL_PCU_2_SXL_VALID_MSK                     (0x80000000)
+  #define PCU_CR_PCIE_ILTR_VAL_PCU_2_SXL_VALID_MAX                     (0x00000001)
+  #define PCU_CR_PCIE_ILTR_VAL_PCU_2_SXL_VALID_DEF                     (0x00000000)
+
+#define PCU_CR_VISA_CTL_PTPCFSMS_PCU_REG                             (0x00005D40)
+  #define PCU_CR_VISA_CTL_PTPCFSMS_PCU_DATA_OFF                        ( 0)
+  #define PCU_CR_VISA_CTL_PTPCFSMS_PCU_DATA_WID                        (18)
+  #define PCU_CR_VISA_CTL_PTPCFSMS_PCU_DATA_MSK                        (0x0003FFFF)
+  #define PCU_CR_VISA_CTL_PTPCFSMS_PCU_DATA_MAX                        (0x0003FFFF)
+  #define PCU_CR_VISA_CTL_PTPCFSMS_PCU_DATA_DEF                        (0x00000000)
+  #define PCU_CR_VISA_CTL_PTPCFSMS_PCU_VORANGE_OFF                     (31)
+  #define PCU_CR_VISA_CTL_PTPCFSMS_PCU_VORANGE_WID                     ( 1)
+  #define PCU_CR_VISA_CTL_PTPCFSMS_PCU_VORANGE_MSK                     (0x80000000)
+  #define PCU_CR_VISA_CTL_PTPCFSMS_PCU_VORANGE_MAX                     (0x00000001)
+  #define PCU_CR_VISA_CTL_PTPCFSMS_PCU_VORANGE_DEF                     (0x00000000)
+
+#define PCU_CR_VISA_XBAR_PTPCFSMS_PCU_REG                            (0x00005D44)
+  #define PCU_CR_VISA_XBAR_PTPCFSMS_PCU_DATA_OFF                       ( 0)
+  #define PCU_CR_VISA_XBAR_PTPCFSMS_PCU_DATA_WID                       (32)
+  #define PCU_CR_VISA_XBAR_PTPCFSMS_PCU_DATA_MSK                       (0xFFFFFFFF)
+  #define PCU_CR_VISA_XBAR_PTPCFSMS_PCU_DATA_MAX                       (0xFFFFFFFF)
+  #define PCU_CR_VISA_XBAR_PTPCFSMS_PCU_DATA_DEF                       (0x76543210)
+
+#define PCU_CR_VISA_CTL_PTPCIOREGS_PCU_REG                           (0x00005D48)
+  #define PCU_CR_VISA_CTL_PTPCIOREGS_PCU_DATA_OFF                      ( 0)
+  #define PCU_CR_VISA_CTL_PTPCIOREGS_PCU_DATA_WID                      (18)
+  #define PCU_CR_VISA_CTL_PTPCIOREGS_PCU_DATA_MSK                      (0x0003FFFF)
+  #define PCU_CR_VISA_CTL_PTPCIOREGS_PCU_DATA_MAX                      (0x0003FFFF)
+  #define PCU_CR_VISA_CTL_PTPCIOREGS_PCU_DATA_DEF                      (0x00000000)
+  #define PCU_CR_VISA_CTL_PTPCIOREGS_PCU_VORANGE_OFF                   (31)
+  #define PCU_CR_VISA_CTL_PTPCIOREGS_PCU_VORANGE_WID                   ( 1)
+  #define PCU_CR_VISA_CTL_PTPCIOREGS_PCU_VORANGE_MSK                   (0x80000000)
+  #define PCU_CR_VISA_CTL_PTPCIOREGS_PCU_VORANGE_MAX                   (0x00000001)
+  #define PCU_CR_VISA_CTL_PTPCIOREGS_PCU_VORANGE_DEF                   (0x00000000)
+
+#define PCU_CR_BIOS_MAILBOX_DATA_PCU_REG                             (0x00005DA0)
+  #define PCU_CR_BIOS_MAILBOX_DATA_PCU_DATA_OFF                        ( 0)
+  #define PCU_CR_BIOS_MAILBOX_DATA_PCU_DATA_WID                        (32)
+  #define PCU_CR_BIOS_MAILBOX_DATA_PCU_DATA_MSK                        (0xFFFFFFFF)
+  #define PCU_CR_BIOS_MAILBOX_DATA_PCU_DATA_MAX                        (0xFFFFFFFF)
+  #define PCU_CR_BIOS_MAILBOX_DATA_PCU_DATA_DEF                        (0x00000000)
+
+#define PCU_CR_BIOS_MAILBOX_INTERFACE_PCU_REG                        (0x00005DA4)
+  #define PCU_CR_BIOS_MAILBOX_INTERFACE_PCU_COMMAND_OFF                ( 0)
+  #define PCU_CR_BIOS_MAILBOX_INTERFACE_PCU_COMMAND_WID                ( 8)
+  #define PCU_CR_BIOS_MAILBOX_INTERFACE_PCU_COMMAND_MSK                (0x000000FF)
+  #define PCU_CR_BIOS_MAILBOX_INTERFACE_PCU_COMMAND_MAX                (0x000000FF)
+  #define PCU_CR_BIOS_MAILBOX_INTERFACE_PCU_COMMAND_DEF                (0x00000000)
+  #define PCU_CR_BIOS_MAILBOX_INTERFACE_PCU_ADDR_OFF                   ( 8)
+  #define PCU_CR_BIOS_MAILBOX_INTERFACE_PCU_ADDR_WID                   (21)
+  #define PCU_CR_BIOS_MAILBOX_INTERFACE_PCU_ADDR_MSK                   (0x1FFFFF00)
+  #define PCU_CR_BIOS_MAILBOX_INTERFACE_PCU_ADDR_MAX                   (0x001FFFFF)
+  #define PCU_CR_BIOS_MAILBOX_INTERFACE_PCU_ADDR_DEF                   (0x00000000)
+  #define PCU_CR_BIOS_MAILBOX_INTERFACE_PCU_RUN_BUSY_OFF               (31)
+  #define PCU_CR_BIOS_MAILBOX_INTERFACE_PCU_RUN_BUSY_WID               ( 1)
+  #define PCU_CR_BIOS_MAILBOX_INTERFACE_PCU_RUN_BUSY_MSK               (0x80000000)
+  #define PCU_CR_BIOS_MAILBOX_INTERFACE_PCU_RUN_BUSY_MAX               (0x00000001)
+  #define PCU_CR_BIOS_MAILBOX_INTERFACE_PCU_RUN_BUSY_DEF               (0x00000000)
+
+#define PCU_CR_BIOS_RESET_CPL_PCU_REG                                (0x00005DA8)
+  #define PCU_CR_BIOS_RESET_CPL_PCU_RST_CPL_OFF                        ( 0)
+  #define PCU_CR_BIOS_RESET_CPL_PCU_RST_CPL_WID                        ( 1)
+  #define PCU_CR_BIOS_RESET_CPL_PCU_RST_CPL_MSK                        (0x00000001)
+  #define PCU_CR_BIOS_RESET_CPL_PCU_RST_CPL_MAX                        (0x00000001)
+  #define PCU_CR_BIOS_RESET_CPL_PCU_RST_CPL_DEF                        (0x00000000)
+  #define PCU_CR_BIOS_RESET_CPL_PCU_PCIE_ENUMERATION_DONE_OFF          ( 1)
+  #define PCU_CR_BIOS_RESET_CPL_PCU_PCIE_ENUMERATION_DONE_WID          ( 1)
+  #define PCU_CR_BIOS_RESET_CPL_PCU_PCIE_ENUMERATION_DONE_MSK          (0x00000002)
+  #define PCU_CR_BIOS_RESET_CPL_PCU_PCIE_ENUMERATION_DONE_MAX          (0x00000001)
+  #define PCU_CR_BIOS_RESET_CPL_PCU_PCIE_ENUMERATION_DONE_DEF          (0x00000000)
+  #define PCU_CR_BIOS_RESET_CPL_PCU_C7_ALLOWED_OFF                     ( 2)
+  #define PCU_CR_BIOS_RESET_CPL_PCU_C7_ALLOWED_WID                     ( 1)
+  #define PCU_CR_BIOS_RESET_CPL_PCU_C7_ALLOWED_MSK                     (0x00000004)
+  #define PCU_CR_BIOS_RESET_CPL_PCU_C7_ALLOWED_MAX                     (0x00000001)
+  #define PCU_CR_BIOS_RESET_CPL_PCU_C7_ALLOWED_DEF                     (0x00000000)
+
+#define PCU_CR_MC_BIOS_REQ_PCU_REG                                   (0x00005E00)
+  #define PCU_CR_MC_BIOS_REQ_PCU_REQ_DATA_OFF                          ( 0)
+  #define PCU_CR_MC_BIOS_REQ_PCU_REQ_DATA_WID                          ( 4)
+  #define PCU_CR_MC_BIOS_REQ_PCU_REQ_DATA_MSK                          (0x0000000F)
+  #define PCU_CR_MC_BIOS_REQ_PCU_REQ_DATA_MAX                          (0x0000000F)
+  #define PCU_CR_MC_BIOS_REQ_PCU_REQ_DATA_DEF                          (0x00000000)
+  #define PCU_CR_MC_BIOS_REQ_PCU_REQ_TYPE_OFF                          ( 4)
+  #define PCU_CR_MC_BIOS_REQ_PCU_REQ_TYPE_WID                          ( 4)
+  #define PCU_CR_MC_BIOS_REQ_PCU_REQ_TYPE_MSK                          (0x000000F0)
+  #define PCU_CR_MC_BIOS_REQ_PCU_REQ_TYPE_MAX                          (0x0000000F)
+  #define PCU_CR_MC_BIOS_REQ_PCU_REQ_TYPE_DEF                          (0x00000000)
+  #define PCU_CR_MC_BIOS_REQ_PCU_RUN_BUSY_OFF                          (31)
+  #define PCU_CR_MC_BIOS_REQ_PCU_RUN_BUSY_WID                          ( 1)
+  #define PCU_CR_MC_BIOS_REQ_PCU_RUN_BUSY_MSK                          (0x80000000)
+  #define PCU_CR_MC_BIOS_REQ_PCU_RUN_BUSY_MAX                          (0x00000001)
+  #define PCU_CR_MC_BIOS_REQ_PCU_RUN_BUSY_DEF                          (0x00000000)
+
+#define PCU_CR_MC_BIOS_DATA_PCU_REG                                  (0x00005E04)
+  #define PCU_CR_MC_BIOS_DATA_PCU_MC_FREQ_OFF                          ( 0)
+  #define PCU_CR_MC_BIOS_DATA_PCU_MC_FREQ_WID                          ( 4)
+  #define PCU_CR_MC_BIOS_DATA_PCU_MC_FREQ_MSK                          (0x0000000F)
+  #define PCU_CR_MC_BIOS_DATA_PCU_MC_FREQ_MAX                          (0x0000000F)
+  #define PCU_CR_MC_BIOS_DATA_PCU_MC_FREQ_DEF                          (0x00000000)
+
+#define PCU_CR_SAPMCTL_PCU_REG                                       (0x00005F00)
+  #define PCU_CR_SAPMCTL_PCU_SACG_ENA_OFF                              ( 0)
+  #define PCU_CR_SAPMCTL_PCU_SACG_ENA_WID                              ( 1)
+  #define PCU_CR_SAPMCTL_PCU_SACG_ENA_MSK                              (0x00000001)
+  #define PCU_CR_SAPMCTL_PCU_SACG_ENA_MAX                              (0x00000001)
+  #define PCU_CR_SAPMCTL_PCU_SACG_ENA_DEF                              (0x00000000)
+  #define PCU_CR_SAPMCTL_PCU_MPLL_OFF_ENA_OFF                          ( 1)
+  #define PCU_CR_SAPMCTL_PCU_MPLL_OFF_ENA_WID                          ( 1)
+  #define PCU_CR_SAPMCTL_PCU_MPLL_OFF_ENA_MSK                          (0x00000002)
+  #define PCU_CR_SAPMCTL_PCU_MPLL_OFF_ENA_MAX                          (0x00000001)
+  #define PCU_CR_SAPMCTL_PCU_MPLL_OFF_ENA_DEF                          (0x00000001)
+  #define PCU_CR_SAPMCTL_PCU_PPLL_OFF_ENA_OFF                          ( 2)
+  #define PCU_CR_SAPMCTL_PCU_PPLL_OFF_ENA_WID                          ( 1)
+  #define PCU_CR_SAPMCTL_PCU_PPLL_OFF_ENA_MSK                          (0x00000004)
+  #define PCU_CR_SAPMCTL_PCU_PPLL_OFF_ENA_MAX                          (0x00000001)
+  #define PCU_CR_SAPMCTL_PCU_PPLL_OFF_ENA_DEF                          (0x00000001)
+  #define PCU_CR_SAPMCTL_PCU_SACG_SEN_OFF                              ( 8)
+  #define PCU_CR_SAPMCTL_PCU_SACG_SEN_WID                              ( 1)
+  #define PCU_CR_SAPMCTL_PCU_SACG_SEN_MSK                              (0x00000100)
+  #define PCU_CR_SAPMCTL_PCU_SACG_SEN_MAX                              (0x00000001)
+  #define PCU_CR_SAPMCTL_PCU_SACG_SEN_DEF                              (0x00000001)
+  #define PCU_CR_SAPMCTL_PCU_MPLL_OFF_SEN_OFF                          ( 9)
+  #define PCU_CR_SAPMCTL_PCU_MPLL_OFF_SEN_WID                          ( 1)
+  #define PCU_CR_SAPMCTL_PCU_MPLL_OFF_SEN_MSK                          (0x00000200)
+  #define PCU_CR_SAPMCTL_PCU_MPLL_OFF_SEN_MAX                          (0x00000001)
+  #define PCU_CR_SAPMCTL_PCU_MPLL_OFF_SEN_DEF                          (0x00000000)
+  #define PCU_CR_SAPMCTL_PCU_MDLL_OFF_SEN_OFF                          (10)
+  #define PCU_CR_SAPMCTL_PCU_MDLL_OFF_SEN_WID                          ( 1)
+  #define PCU_CR_SAPMCTL_PCU_MDLL_OFF_SEN_MSK                          (0x00000400)
+  #define PCU_CR_SAPMCTL_PCU_MDLL_OFF_SEN_MAX                          (0x00000001)
+  #define PCU_CR_SAPMCTL_PCU_MDLL_OFF_SEN_DEF                          (0x00000000)
+  #define PCU_CR_SAPMCTL_PCU_SACG_SREXIT_OFF                           (11)
+  #define PCU_CR_SAPMCTL_PCU_SACG_SREXIT_WID                           ( 1)
+  #define PCU_CR_SAPMCTL_PCU_SACG_SREXIT_MSK                           (0x00000800)
+  #define PCU_CR_SAPMCTL_PCU_SACG_SREXIT_MAX                           (0x00000001)
+  #define PCU_CR_SAPMCTL_PCU_SACG_SREXIT_DEF                           (0x00000000)
+  #define PCU_CR_SAPMCTL_PCU_NSWAKE_SREXIT_OFF                         (12)
+  #define PCU_CR_SAPMCTL_PCU_NSWAKE_SREXIT_WID                         ( 1)
+  #define PCU_CR_SAPMCTL_PCU_NSWAKE_SREXIT_MSK                         (0x00001000)
+  #define PCU_CR_SAPMCTL_PCU_NSWAKE_SREXIT_MAX                         (0x00000001)
+  #define PCU_CR_SAPMCTL_PCU_NSWAKE_SREXIT_DEF                         (0x00000000)
+  #define PCU_CR_SAPMCTL_PCU_SACG_MPLL_OFF                             (13)
+  #define PCU_CR_SAPMCTL_PCU_SACG_MPLL_WID                             ( 1)
+  #define PCU_CR_SAPMCTL_PCU_SACG_MPLL_MSK                             (0x00002000)
+  #define PCU_CR_SAPMCTL_PCU_SACG_MPLL_MAX                             (0x00000001)
+  #define PCU_CR_SAPMCTL_PCU_SACG_MPLL_DEF                             (0x00000001)
+  #define PCU_CR_SAPMCTL_PCU_MPLL_ON_DE_OFF                            (14)
+  #define PCU_CR_SAPMCTL_PCU_MPLL_ON_DE_WID                            ( 1)
+  #define PCU_CR_SAPMCTL_PCU_MPLL_ON_DE_MSK                            (0x00004000)
+  #define PCU_CR_SAPMCTL_PCU_MPLL_ON_DE_MAX                            (0x00000001)
+  #define PCU_CR_SAPMCTL_PCU_MPLL_ON_DE_DEF                            (0x00000000)
+  #define PCU_CR_SAPMCTL_PCU_MDLL_ON_DE_OFF                            (15)
+  #define PCU_CR_SAPMCTL_PCU_MDLL_ON_DE_WID                            ( 1)
+  #define PCU_CR_SAPMCTL_PCU_MDLL_ON_DE_MSK                            (0x00008000)
+  #define PCU_CR_SAPMCTL_PCU_MDLL_ON_DE_MAX                            (0x00000001)
+  #define PCU_CR_SAPMCTL_PCU_MDLL_ON_DE_DEF                            (0x00000000)
+
+#define PCU_CR_P_COMP_PCU_REG                                        (0x00005F04)
+  #define PCU_CR_P_COMP_PCU_COMP_DISABLE_OFF                           ( 0)
+  #define PCU_CR_P_COMP_PCU_COMP_DISABLE_WID                           ( 1)
+  #define PCU_CR_P_COMP_PCU_COMP_DISABLE_MSK                           (0x00000001)
+  #define PCU_CR_P_COMP_PCU_COMP_DISABLE_MAX                           (0x00000001)
+  #define PCU_CR_P_COMP_PCU_COMP_DISABLE_DEF                           (0x00000000)
+  #define PCU_CR_P_COMP_PCU_COMP_INTERVAL_OFF                          ( 1)
+  #define PCU_CR_P_COMP_PCU_COMP_INTERVAL_WID                          ( 4)
+  #define PCU_CR_P_COMP_PCU_COMP_INTERVAL_MSK                          (0x0000001E)
+  #define PCU_CR_P_COMP_PCU_COMP_INTERVAL_MAX                          (0x0000000F)
+  #define PCU_CR_P_COMP_PCU_COMP_INTERVAL_DEF                          (0x00000008)
+  #define PCU_CR_P_COMP_PCU_COMP_FORCE_OFF                             ( 8)
+  #define PCU_CR_P_COMP_PCU_COMP_FORCE_WID                             ( 1)
+  #define PCU_CR_P_COMP_PCU_COMP_FORCE_MSK                             (0x00000100)
+  #define PCU_CR_P_COMP_PCU_COMP_FORCE_MAX                             (0x00000001)
+  #define PCU_CR_P_COMP_PCU_COMP_FORCE_DEF                             (0x00000000)
+
+#define PCU_CR_M_COMP_PCU_REG                                        (0x00005F08)
+  #define PCU_CR_M_COMP_PCU_COMP_DISABLE_OFF                           ( 0)
+  #define PCU_CR_M_COMP_PCU_COMP_DISABLE_WID                           ( 1)
+  #define PCU_CR_M_COMP_PCU_COMP_DISABLE_MSK                           (0x00000001)
+  #define PCU_CR_M_COMP_PCU_COMP_DISABLE_MAX                           (0x00000001)
+  #define PCU_CR_M_COMP_PCU_COMP_DISABLE_DEF                           (0x00000000)
+  #define PCU_CR_M_COMP_PCU_COMP_INTERVAL_OFF                          ( 1)
+  #define PCU_CR_M_COMP_PCU_COMP_INTERVAL_WID                          ( 4)
+  #define PCU_CR_M_COMP_PCU_COMP_INTERVAL_MSK                          (0x0000001E)
+  #define PCU_CR_M_COMP_PCU_COMP_INTERVAL_MAX                          (0x0000000F)
+  #define PCU_CR_M_COMP_PCU_COMP_INTERVAL_DEF                          (0x0000000D)
+  #define PCU_CR_M_COMP_PCU_COMP_FORCE_OFF                             ( 8)
+  #define PCU_CR_M_COMP_PCU_COMP_FORCE_WID                             ( 1)
+  #define PCU_CR_M_COMP_PCU_COMP_FORCE_MSK                             (0x00000100)
+  #define PCU_CR_M_COMP_PCU_COMP_FORCE_MAX                             (0x00000001)
+  #define PCU_CR_M_COMP_PCU_COMP_FORCE_DEF                             (0x00000000)
+
+#define PCU_CR_D_COMP_PCU_REG                                        (0x00005F0C)
+  #define PCU_CR_D_COMP_PCU_COMP_DISABLE_OFF                           ( 0)
+  #define PCU_CR_D_COMP_PCU_COMP_DISABLE_WID                           ( 1)
+  #define PCU_CR_D_COMP_PCU_COMP_DISABLE_MSK                           (0x00000001)
+  #define PCU_CR_D_COMP_PCU_COMP_DISABLE_MAX                           (0x00000001)
+  #define PCU_CR_D_COMP_PCU_COMP_DISABLE_DEF                           (0x00000000)
+  #define PCU_CR_D_COMP_PCU_COMP_INTERVAL_OFF                          ( 1)
+  #define PCU_CR_D_COMP_PCU_COMP_INTERVAL_WID                          ( 4)
+  #define PCU_CR_D_COMP_PCU_COMP_INTERVAL_MSK                          (0x0000001E)
+  #define PCU_CR_D_COMP_PCU_COMP_INTERVAL_MAX                          (0x0000000F)
+  #define PCU_CR_D_COMP_PCU_COMP_INTERVAL_DEF                          (0x00000008)
+  #define PCU_CR_D_COMP_PCU_COMP_FORCE_OFF                             ( 8)
+  #define PCU_CR_D_COMP_PCU_COMP_FORCE_WID                             ( 1)
+  #define PCU_CR_D_COMP_PCU_COMP_FORCE_MSK                             (0x00000100)
+  #define PCU_CR_D_COMP_PCU_COMP_FORCE_MAX                             (0x00000001)
+  #define PCU_CR_D_COMP_PCU_COMP_FORCE_DEF                             (0x00000000)
+
+#define PCU_CR_CONFIG_TDP_NOMINAL_PCU_REG                            (0x00005F3C)
+  #define PCU_CR_CONFIG_TDP_NOMINAL_PCU_TDP_RATIO_OFF                  ( 0)
+  #define PCU_CR_CONFIG_TDP_NOMINAL_PCU_TDP_RATIO_WID                  ( 8)
+  #define PCU_CR_CONFIG_TDP_NOMINAL_PCU_TDP_RATIO_MSK                  (0x000000FF)
+  #define PCU_CR_CONFIG_TDP_NOMINAL_PCU_TDP_RATIO_MAX                  (0x000000FF)
+  #define PCU_CR_CONFIG_TDP_NOMINAL_PCU_TDP_RATIO_DEF                  (0x00000000)
+
+#define PCU_CR_CONFIG_TDP_LEVEL1_PCU_REG                             (0x00005F40)
+  #define PCU_CR_CONFIG_TDP_LEVEL1_PCU_PKG_TDP_OFF                     ( 0)
+  #define PCU_CR_CONFIG_TDP_LEVEL1_PCU_PKG_TDP_WID                     (15)
+  #define PCU_CR_CONFIG_TDP_LEVEL1_PCU_PKG_TDP_MSK                     (0x00007FFF)
+  #define PCU_CR_CONFIG_TDP_LEVEL1_PCU_PKG_TDP_MAX                     (0x00007FFF)
+  #define PCU_CR_CONFIG_TDP_LEVEL1_PCU_PKG_TDP_DEF                     (0x00000000)
+  #define PCU_CR_CONFIG_TDP_LEVEL1_PCU_TDP_RATIO_OFF                   (16)
+  #define PCU_CR_CONFIG_TDP_LEVEL1_PCU_TDP_RATIO_WID                   ( 8)
+  #define PCU_CR_CONFIG_TDP_LEVEL1_PCU_TDP_RATIO_MSK                   (0x00FF0000)
+  #define PCU_CR_CONFIG_TDP_LEVEL1_PCU_TDP_RATIO_MAX                   (0x000000FF)
+  #define PCU_CR_CONFIG_TDP_LEVEL1_PCU_TDP_RATIO_DEF                   (0x00000000)
+  #define PCU_CR_CONFIG_TDP_LEVEL1_PCU_PKG_MAX_PWR_OFF                 (32)
+  #define PCU_CR_CONFIG_TDP_LEVEL1_PCU_PKG_MAX_PWR_WID                 (15)
+  #define PCU_CR_CONFIG_TDP_LEVEL1_PCU_PKG_MAX_PWR_MSK                 (0x7FFF00000000)
+  #define PCU_CR_CONFIG_TDP_LEVEL1_PCU_PKG_MAX_PWR_MAX                 (0x00007FFF)
+  #define PCU_CR_CONFIG_TDP_LEVEL1_PCU_PKG_MAX_PWR_DEF                 (0x00000000)
+  #define PCU_CR_CONFIG_TDP_LEVEL1_PCU_PKG_MIN_PWR_OFF                 (47)
+  #define PCU_CR_CONFIG_TDP_LEVEL1_PCU_PKG_MIN_PWR_WID                 (16)
+  #define PCU_CR_CONFIG_TDP_LEVEL1_PCU_PKG_MIN_PWR_MSK                 (0x7FFF800000000000)
+  #define PCU_CR_CONFIG_TDP_LEVEL1_PCU_PKG_MIN_PWR_MAX                 (0x0000FFFF)
+  #define PCU_CR_CONFIG_TDP_LEVEL1_PCU_PKG_MIN_PWR_DEF                 (0x00000000)
+
+#define PCU_CR_CONFIG_TDP_LEVEL2_PCU_REG                             (0x00005F48)
+  #define PCU_CR_CONFIG_TDP_LEVEL2_PCU_PKG_TDP_OFF                     ( 0)
+  #define PCU_CR_CONFIG_TDP_LEVEL2_PCU_PKG_TDP_WID                     (15)
+  #define PCU_CR_CONFIG_TDP_LEVEL2_PCU_PKG_TDP_MSK                     (0x00007FFF)
+  #define PCU_CR_CONFIG_TDP_LEVEL2_PCU_PKG_TDP_MAX                     (0x00007FFF)
+  #define PCU_CR_CONFIG_TDP_LEVEL2_PCU_PKG_TDP_DEF                     (0x00000000)
+  #define PCU_CR_CONFIG_TDP_LEVEL2_PCU_TDP_RATIO_OFF                   (16)
+  #define PCU_CR_CONFIG_TDP_LEVEL2_PCU_TDP_RATIO_WID                   ( 8)
+  #define PCU_CR_CONFIG_TDP_LEVEL2_PCU_TDP_RATIO_MSK                   (0x00FF0000)
+  #define PCU_CR_CONFIG_TDP_LEVEL2_PCU_TDP_RATIO_MAX                   (0x000000FF)
+  #define PCU_CR_CONFIG_TDP_LEVEL2_PCU_TDP_RATIO_DEF                   (0x00000000)
+  #define PCU_CR_CONFIG_TDP_LEVEL2_PCU_PKG_MAX_PWR_OFF                 (32)
+  #define PCU_CR_CONFIG_TDP_LEVEL2_PCU_PKG_MAX_PWR_WID                 (15)
+  #define PCU_CR_CONFIG_TDP_LEVEL2_PCU_PKG_MAX_PWR_MSK                 (0x7FFF00000000)
+  #define PCU_CR_CONFIG_TDP_LEVEL2_PCU_PKG_MAX_PWR_MAX                 (0x00007FFF)
+  #define PCU_CR_CONFIG_TDP_LEVEL2_PCU_PKG_MAX_PWR_DEF                 (0x00000000)
+  #define PCU_CR_CONFIG_TDP_LEVEL2_PCU_PKG_MIN_PWR_OFF                 (47)
+  #define PCU_CR_CONFIG_TDP_LEVEL2_PCU_PKG_MIN_PWR_WID                 (16)
+  #define PCU_CR_CONFIG_TDP_LEVEL2_PCU_PKG_MIN_PWR_MSK                 (0x7FFF800000000000)
+  #define PCU_CR_CONFIG_TDP_LEVEL2_PCU_PKG_MIN_PWR_MAX                 (0x0000FFFF)
+  #define PCU_CR_CONFIG_TDP_LEVEL2_PCU_PKG_MIN_PWR_DEF                 (0x00000000)
+
+#define PCU_CR_CONFIG_TDP_CONTROL_PCU_REG                            (0x00005F50)
+  #define PCU_CR_CONFIG_TDP_CONTROL_PCU_TDP_LEVEL_OFF                  ( 0)
+  #define PCU_CR_CONFIG_TDP_CONTROL_PCU_TDP_LEVEL_WID                  ( 2)
+  #define PCU_CR_CONFIG_TDP_CONTROL_PCU_TDP_LEVEL_MSK                  (0x00000003)
+  #define PCU_CR_CONFIG_TDP_CONTROL_PCU_TDP_LEVEL_MAX                  (0x00000003)
+  #define PCU_CR_CONFIG_TDP_CONTROL_PCU_TDP_LEVEL_DEF                  (0x00000000)
+  #define PCU_CR_CONFIG_TDP_CONTROL_PCU_CONFIG_TDP_LOCK_OFF            (31)
+  #define PCU_CR_CONFIG_TDP_CONTROL_PCU_CONFIG_TDP_LOCK_WID            ( 1)
+  #define PCU_CR_CONFIG_TDP_CONTROL_PCU_CONFIG_TDP_LOCK_MSK            (0x80000000)
+  #define PCU_CR_CONFIG_TDP_CONTROL_PCU_CONFIG_TDP_LOCK_MAX            (0x00000001)
+  #define PCU_CR_CONFIG_TDP_CONTROL_PCU_CONFIG_TDP_LOCK_DEF            (0x00000000)
+
+#define PCU_CR_TURBO_ACTIVATION_RATIO_PCU_REG                        (0x00005F54)
+  #define PCU_CR_TURBO_ACTIVATION_RATIO_PCU_MAX_NON_TURBO_RATIO_OFF    ( 0)
+  #define PCU_CR_TURBO_ACTIVATION_RATIO_PCU_MAX_NON_TURBO_RATIO_WID    ( 8)
+  #define PCU_CR_TURBO_ACTIVATION_RATIO_PCU_MAX_NON_TURBO_RATIO_MSK    (0x000000FF)
+  #define PCU_CR_TURBO_ACTIVATION_RATIO_PCU_MAX_NON_TURBO_RATIO_MAX    (0x000000FF)
+  #define PCU_CR_TURBO_ACTIVATION_RATIO_PCU_MAX_NON_TURBO_RATIO_DEF    (0x00000000)
+  #define PCU_CR_TURBO_ACTIVATION_RATIO_PCU_TURBO_ACTIVATION_RATIO_LOCK_OFF (31)
+  #define PCU_CR_TURBO_ACTIVATION_RATIO_PCU_TURBO_ACTIVATION_RATIO_LOCK_WID ( 1)
+  #define PCU_CR_TURBO_ACTIVATION_RATIO_PCU_TURBO_ACTIVATION_RATIO_LOCK_MSK (0x80000000)
+  #define PCU_CR_TURBO_ACTIVATION_RATIO_PCU_TURBO_ACTIVATION_RATIO_LOCK_MAX (0x00000001)
+  #define PCU_CR_TURBO_ACTIVATION_RATIO_PCU_TURBO_ACTIVATION_RATIO_LOCK_DEF (0x00000000)
+
+#define DRNG_CR_VISA_CTL_DRNGCTLS_DRNG_REG                           (0x00006680)
+  #define DRNG_CR_VISA_CTL_DRNGCTLS_DRNG_DATA_OFF                      ( 0)
+  #define DRNG_CR_VISA_CTL_DRNGCTLS_DRNG_DATA_WID                      (18)
+  #define DRNG_CR_VISA_CTL_DRNGCTLS_DRNG_DATA_MSK                      (0x0003FFFF)
+  #define DRNG_CR_VISA_CTL_DRNGCTLS_DRNG_DATA_MAX                      (0x0003FFFF)
+  #define DRNG_CR_VISA_CTL_DRNGCTLS_DRNG_DATA_DEF                      (0x00000000)
+  #define DRNG_CR_VISA_CTL_DRNGCTLS_DRNG_VORANGE_OFF                   (31)
+  #define DRNG_CR_VISA_CTL_DRNGCTLS_DRNG_VORANGE_WID                   ( 1)
+  #define DRNG_CR_VISA_CTL_DRNGCTLS_DRNG_VORANGE_MSK                   (0x80000000)
+  #define DRNG_CR_VISA_CTL_DRNGCTLS_DRNG_VORANGE_MAX                   (0x00000001)
+  #define DRNG_CR_VISA_CTL_DRNGCTLS_DRNG_VORANGE_DEF                   (0x00000000)
+
+#pragma pack(pop)
+#endif  // __Msa_h__
diff --git a/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcRegisters/Pci000.h b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcRegisters/Pci000.h
new file mode 100644
index 0000000..050187b
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcRegisters/Pci000.h
@@ -0,0 +1,970 @@
+/*++ @file
+  PCI bus 0, device 0, function 0 register definitions
+
+
+@copyright
+  Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved.
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement.
+--*/
+
+#ifndef _Pci000_h_
+#define _Pci000_h_
+#pragma pack (push, 1)
+#include "MrcTypes.h"
+
+typedef union {
+  struct {
+    U32 Mchbaren : 1;  /// Bits 0:0
+    U32          : 14; /// Bits 14:1
+    U32 Mchbar   : 17; /// Bits 31:15
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MRC_PCI_000_MCHBAR_LOW_STRUCT;
+
+typedef union {
+  struct {
+    U32 Mchbar   : 7;  /// Bits 38:32
+    U32          : 25; /// Bits 63:39
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MRC_PCI_000_MCHBAR_HIGH_STRUCT;
+
+typedef union {
+  struct {
+    U64 Mchbaren : 1;  /// Bits 0:0
+    U64          : 14; /// Bits 14:1
+    U64 Mchbar   : 24; /// Bits 38:15
+    U64          : 25; /// Bits 63:39
+  } Bits;
+  U64 Data;
+  struct {
+    MRC_PCI_000_MCHBAR_LOW_STRUCT  Low;
+    MRC_PCI_000_MCHBAR_HIGH_STRUCT High;
+  } Data32;
+} MRC_PCI_000_MCHBAR_STRUCT;
+
+#define MRC_PCI_000_MCHBAR_REG (0x48)
+  #define MCHBAR_MCHBAREN_OFF  (0)
+  #define MCHBAR_MCHBAREN_WID  (1)
+  #define MCHBAR_MCHBAREN_MSK  (0x1)
+  #define MCHBAR_MCHBAREN_MAX  (0x1)
+  #define MCHBAR_MCHBAREN_DEF  (0x0)
+  #define MCHBAR_MCHBAR_OFF    (15)
+  #define MCHBAR_MCHBAR_WID    (24)
+  #define MCHBAR_MCHBAR_MSK    (0x0000007FFFFF8000)
+  #define MCHBAR_MCHBAR_MAX    (0xFFFFFF)
+  #define MCHBAR_MCHBAR_DEF    (0x0)
+
+typedef union {
+  struct {
+    U32 Ggclck : 1;  /// Bits 0:0
+    U32 Ivd    : 1;  /// Bits 1:1
+    U32        : 1;  /// Bits 2:2
+    U32 Gms    : 5;  /// Bits 7:3
+    U32 Ggms   : 2;  /// Bits 9:8
+    U32        : 4;  /// Bits 13:10
+    U32 Vamen  : 1;  /// Bits 14:14
+    U32        : 17; /// Bits 31:15
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MRC_PCI_000_GGC_STRUCT;
+
+#define MRC_PCI_000_GGC_REG (0x50)
+  #define GGC_GGCLCK_OFF    (0)
+  #define GGC_GGCLCK_WID    (1)
+  #define GGC_GGCLCK_MSK    (0x1)
+  #define GGC_GGCLCK_MAX    (0x1)
+  #define GGC_GGCLCK_DEF    (0x0)
+  #define GGC_IVD_OFF       (1)
+  #define GGC_IVD_WID       (1)
+  #define GGC_IVD_MSK       (0x2)
+  #define GGC_IVD_MAX       (0x1)
+  #define GGC_IVD_DEF       (0x0)
+  #define GGC_GMS_OFF       (3)
+  #define GGC_GMS_WID       (5)
+  #define GGC_GMS_MSK       (0xF8)
+  #define GGC_GMS_MAX       (0x1F)
+  #define GGC_GMS_DEF       (0x5)
+  #define GGC_GGMS_OFF      (8)
+  #define GGC_GGMS_WID      (2)
+  #define GGC_GGMS_MSK      (0x300)
+  #define GGC_GGMS_MAX      (0x3)
+  #define GGC_GGMS_DEF      (0x0)
+  #define GGC_VAMEN_OFF     (0xe)
+  #define GGC_VAMEN_WID     (0x1)
+  #define GGC_VAMEN_MSK     (0x4000)
+  #define GGC_VAMEN_MAX     (0x1)
+  #define GGC_VAMEN_DEF     (0x0)
+
+typedef union {
+  struct {
+    U32 D0EN   : 1;  /// Bits 0:0
+    U32 D1F2EN : 1;  /// Bits 1:1
+    U32 D1F1EN : 1;  /// Bits 2:2
+    U32 D1F0EN : 1;  /// Bits 3:3
+    U32 D2EN   : 1;  /// Bits 4:4
+    U32 D3EN   : 1;  /// Bits 5:5
+    U32        : 1;  /// Bits 6:6
+    U32 D4EN   : 1;  /// Bits 7:7
+    U32        : 6;  /// Bits 13:8
+    U32 D7EN   : 1;  /// Bits 14:14
+    U32        : 17; /// Bits 31:15
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MRC_PCI_000_DEVEN_STRUCT;
+
+#define MRC_PCI_000_DEVEN_REG (0x54)
+  #define DEVEN_D0EN_OFF      (0)
+  #define DEVEN_D0EN_WID      (1)
+  #define DEVEN_D0EN_MSK      (0x1)
+  #define DEVEN_D0EN_MAX      (0x1)
+  #define DEVEN_D0EN_DEF      (0x1)
+  #define DEVEN_D1F2EN_OFF    (1)
+  #define DEVEN_D1F2EN_WID    (1)
+  #define DEVEN_D1F2EN_MSK    (0x2)
+  #define DEVEN_D1F2EN_MAX    (0x1)
+  #define DEVEN_D1F2EN_DEF    (0x1)
+  #define DEVEN_D1F1EN_OFF    (2)
+  #define DEVEN_D1F1EN_WID    (1)
+  #define DEVEN_D1F1EN_MSK    (0x4)
+  #define DEVEN_D1F1EN_MAX    (0x1)
+  #define DEVEN_D1F1EN_DEF    (0x1)
+  #define DEVEN_D1F0EN_OFF    (3)
+  #define DEVEN_D1F0EN_WID    (1)
+  #define DEVEN_D1F0EN_MSK    (0x8)
+  #define DEVEN_D1F0EN_MAX    (0x1)
+  #define DEVEN_D1F0EN_DEF    (0x1)
+  #define DEVEN_D2EN_OFF      (4)
+  #define DEVEN_D2EN_WID      (1)
+  #define DEVEN_D2EN_MSK      (0x10)
+  #define DEVEN_D2EN_MAX      (0x1)
+  #define DEVEN_D2EN_DEF      (0x1)
+  #define DEVEN_D3EN_OFF      (5)
+  #define DEVEN_D3EN_WID      (1)
+  #define DEVEN_D3EN_MSK      (0x20)
+  #define DEVEN_D3EN_MAX      (0x1)
+  #define DEVEN_D3EN_DEF      (0x1)
+  #define DEVEN_D4EN_OFF      (7)
+  #define DEVEN_D4EN_WID      (1)
+  #define DEVEN_D4EN_MSK      (0x80)
+  #define DEVEN_D4EN_MAX      (0x1)
+  #define DEVEN_D4EN_DEF      (0x1)
+  #define DEVEN_D7EN_OFF      (14)
+  #define DEVEN_D7EN_WID      (1)
+  #define DEVEN_D7EN_MSK      (0x4000)
+  #define DEVEN_D7EN_MAX      (0x1)
+  #define DEVEN_D7EN_DEF      (0x0)
+
+typedef union {
+  struct {
+    U32 Pciexbaren : 1;  /// Bits 0:0
+    U32 Length     : 2;  /// Bits 2:1
+    U32            : 23; /// Bits 25:3
+    U32 Admsk64    : 1;  /// Bits 26:26
+    U32 Admsk128   : 1;  /// Bits 27:27
+    U32 Pciexbar   : 4;  /// Bits 31:28
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MRC_PCI_000_PCIEXBAR_LOW_STRUCT;
+
+typedef union {
+  struct {
+    U32 Pciexbar   : 7;  /// Bits 38:32
+    U32            : 25; /// Bits 63:39
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MRC_PCI_000_PCIEXBAR_HIGH_STRUCT;
+
+typedef union {
+  struct {
+    U64 Pciexbaren : 1;  /// Bits 0:0
+    U64 Length     : 2;  /// Bits 2:1
+    U64            : 23; /// Bits 25:3
+    U64 Admsk64    : 1;  /// Bits 26:26
+    U64 Admsk128   : 1;  /// Bits 27:27
+    U64 Pciexbar   : 11; /// Bits 38:28
+    U64            : 25; /// Bits 63:39
+  } Bits;
+  U64 Data;
+  struct {
+    MRC_PCI_000_PCIEXBAR_LOW_STRUCT  Low;
+    MRC_PCI_000_PCIEXBAR_HIGH_STRUCT High;
+  } Data32;
+} MRC_PCI_000_PCIEXBAR_STRUCT;
+
+#define MRC_PCI_000_PCIEXBAR_REG  (0x60)
+  #define PCIEXBAR_PCIEXBAREN_OFF (0)
+  #define PCIEXBAR_PCIEXBAREN_WID (1)
+  #define PCIEXBAR_PCIEXBAREN_MSK (0x1)
+  #define PCIEXBAR_PCIEXBAREN_MAX (0x1)
+  #define PCIEXBAR_PCIEXBAREN_DEF (0x0)
+  #define PCIEXBAR_LENGTH_OFF     (1)
+  #define PCIEXBAR_LENGTH_WID     (2)
+  #define PCIEXBAR_LENGTH_MSK     (0x6)
+  #define PCIEXBAR_LENGTH_MAX     (0x3)
+  #define PCIEXBAR_LENGTH_DEF     (0x0)
+  #define PCIEXBAR_ADMSK64_OFF    (26)
+  #define PCIEXBAR_ADMSK64_WID    (1)
+  #define PCIEXBAR_ADMSK64_MSK    (0x4000000)
+  #define PCIEXBAR_ADMSK64_MAX    (0x1)
+  #define PCIEXBAR_ADMSK64_DEF    (0x1)
+  #define PCIEXBAR_ADMSK128_OFF   (27)
+  #define PCIEXBAR_ADMSK128_WID   (1)
+  #define PCIEXBAR_ADMSK128_MSK   (0x8000000)
+  #define PCIEXBAR_ADMSK128_MAX   (0x1)
+  #define PCIEXBAR_ADMSK128_DEF   (0x1)
+  #define PCIEXBAR_PCIEXBAR_OFF   (28)
+  #define PCIEXBAR_PCIEXBAR_WID   (11)
+  #define PCIEXBAR_PCIEXBAR_MSK   (0x7FF0000000)
+  #define PCIEXBAR_PCIEXBAR_MAX   (0x7FF)
+  #define PCIEXBAR_PCIEXBAR_DEF   (0x0)
+
+typedef union {
+  struct {
+    U32       : 20; /// Bits 19:0
+    U32 Value : 12; /// Bits 31:20
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MRC_PCI_000_MESEG_BASE_LOW_STRUCT;
+
+typedef union {
+  struct {
+    U32 Value : 7;  /// Bits 38:32
+    U32       : 25; /// Bits 63:39
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MRC_PCI_000_MESEG_BASE_HIGH_STRUCT;
+
+typedef union {
+  struct {
+    U64       : 20; /// Bits 19:0
+    U64 Value : 19; /// Bits 38:20
+    U64       : 25; /// Bits 63:39
+  } Bits;
+  U64 Data;
+  struct {
+    MRC_PCI_000_MESEG_BASE_LOW_STRUCT  Low;
+    MRC_PCI_000_MESEG_BASE_HIGH_STRUCT High;
+  } Data32;
+} MRC_PCI_000_MESEG_BASE_STRUCT;
+
+#define MRC_PCI_000_MESEG_BASE_REG  (0x70)
+  #define MESEG_BASE_MEBASE_OFF     (20)
+  #define MESEG_BASE_MEBASE_WID     (19)
+  #define MESEG_BASE_MEBASE_MSK     (0x7FFFF00000)
+  #define MESEG_BASE_MEBASE_MAX     (0x7FFFF)
+  #define MESEG_BASE_MEBASE_DEF     (0x7FFFF)
+
+typedef union {
+  struct {
+    U32        : 10; /// Bits 9:0
+    U32 Lock   : 1;  /// Bits 10:10
+    U32 Enable : 1;  /// Bits 11:11
+    U32        : 8;  /// Bits 19:12
+    U32 Value  : 12; /// Bits 31:20
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MRC_PCI_000_MESEG_MASK_LOW_STRUCT;
+
+typedef union {
+  struct {
+    U32 Value  : 7;  /// Bits 38:32
+    U32        : 25; /// Bits 63:39
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MRC_PCI_000_MESEG_MASK_HIGH_STRUCT;
+
+typedef union {
+  struct {
+    U64        : 10; /// Bits 9:0
+    U64 Lock   : 1;  /// Bits 10:10
+    U64 Enable : 1;  /// Bits 11:11
+    U64        : 8;  /// Bits 19:12
+    U64 Value  : 19; /// Bits 38:20
+    U64        : 25; /// Bits 63:39
+  } Bits;
+  U64 Data;
+  struct {
+    MRC_PCI_000_MESEG_MASK_LOW_STRUCT  Low;
+    MRC_PCI_000_MESEG_MASK_HIGH_STRUCT High;
+  } Data32;
+} MRC_PCI_000_MESEG_MASK_STRUCT;
+
+#define MRC_PCI_000_MESEG_MASK_REG   (0x78)
+  #define MESEG_MASK_MELCK_OFF       (10)
+  #define MESEG_MASK_MELCK_WID       (1)
+  #define MESEG_MASK_MELCK_MSK       (0x400)
+  #define MESEG_MASK_MELCK_MAX       (1)
+  #define MESEG_MASK_MELCK_DEF       (0x0)
+  #define MESEG_MASK_ME_STLEN_EN_OFF (11)
+  #define MESEG_MASK_ME_STLEN_EN_WID (1)
+  #define MESEG_MASK_ME_STLEN_EN_MSK (0x800)
+  #define MESEG_MASK_ME_STLEN_EN_MAX (0x1)
+  #define MESEG_MASK_ME_STLEN_EN_DEF (0x0)
+  #define MESEG_MASK_MEMASK_OFF      (20)
+  #define MESEG_MASK_MEMASK_WID      (19)
+  #define MESEG_MASK_MEMASK_MSK      (0x7FFFF00000)
+  #define MESEG_MASK_MEMASK_MAX      (0x7FFFF)
+  #define MESEG_MASK_MEMASK_DEF      (0x0)
+
+typedef union {
+  struct {
+    U32 Lock  : 1;  /// Bits 0:0
+    U32       : 19; /// Bits 19:1
+    U32 Value : 12; /// Bits 31:20
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MRC_PCI_000_REMAPBASE_LOW_STRUCT;
+
+typedef union {
+  struct {
+    U32 Value : 7;  /// Bits 38:32
+    U32       : 25; /// Bits 63:39
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MRC_PCI_000_REMAPBASE_HIGH_STRUCT;
+
+typedef union {
+  struct {
+    U64 Lock  : 1;  /// Bits 0:0
+    U64       : 19; /// Bits 19:1
+    U64 Value : 19; /// Bits 38:20
+    U64       : 25; /// Bits 63:39
+  } Bits;
+  U64 Data;
+  struct {
+    MRC_PCI_000_REMAPBASE_LOW_STRUCT  Low;
+    MRC_PCI_000_REMAPBASE_HIGH_STRUCT High;
+  } Data32;
+} MRC_PCI_000_REMAPBASE_STRUCT;
+
+#define MRC_PCI_000_REMAPBASE_REG (0x90)
+  #define REMAPBASE_LOCK_OFF      (0)
+  #define REMAPBASE_LOCK_WID      (1)
+  #define REMAPBASE_LOCK_MSK      (0x1)
+  #define REMAPBASE_LOCK_MAX      (0x1)
+  #define REMAPBASE_LOCK_DEF      (0x0)
+  #define REMAPBASE_REMAPBASE_OFF (20)
+  #define REMAPBASE_REMAPBASE_WID (19)
+  #define REMAPBASE_REMAPBASE_MSK (0x7FFFF00000)
+  #define REMAPBASE_REMAPBASE_MAX (0x7FFFF)
+  #define REMAPBASE_REMAPBASE_DEF (0xFFFFF)
+
+typedef union {
+  struct {
+    U32 Lock  : 1;  /// Bits 0:0
+    U32       : 19; /// Bits 19:1
+    U32 Value : 12; /// Bits 31:20
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MRC_PCI_000_REMAPLIMIT_LOW_STRUCT;
+
+typedef union {
+  struct {
+    U32 Value : 7;  /// Bits 38:32
+    U32       : 25; /// Bits 63:39
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MRC_PCI_000_REMAPLIMIT_HIGH_STRUCT;
+
+typedef union {
+  struct {
+    U64 Lock  : 1;  /// Bits 0:0
+    U64       : 19; /// Bits 19:1
+    U64 Value : 19; /// Bits 38:20
+    U64       : 25; /// Bits 63:39
+  } Bits;
+  U64 Data;
+  struct {
+    MRC_PCI_000_REMAPLIMIT_LOW_STRUCT  Low;
+    MRC_PCI_000_REMAPLIMIT_HIGH_STRUCT High;
+  } Data32;
+} MRC_PCI_000_REMAPLIMIT_STRUCT;
+
+#define MRC_PCI_000_REMAPLIMIT_REG (0x98)
+  #define REMAPLIMIT_LOCK_OFF      (0)
+  #define REMAPLIMIT_LOCK_WID      (1)
+  #define REMAPLIMIT_LOCK_MSK      (0x1)
+  #define REMAPLIMIT_LOCK_MAX      (0x1)
+  #define REMAPLIMIT_LOCK_DEF      (0x0)
+  #define REMAPLIMIT_REMAPLMT_OFF  (20)
+  #define REMAPLIMIT_REMAPLMT_WID  (19)
+  #define REMAPLIMIT_REMAPLMT_MSK  (0x7FFFF00000)
+  #define REMAPLIMIT_REMAPLMT_MAX  (0x7FFFF)
+  #define REMAPLIMIT_REMAPLMT_DEF  (0x0)
+
+typedef union {
+  struct {
+    U32 Lock  : 1;  /// Bits 0:0
+    U32       : 19; /// Bits 19:1
+    U32 Value : 12; /// Bits 31:20
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MRC_PCI_000_TOM_LOW_STRUCT;
+
+typedef union {
+  struct {
+    U32 Value : 7;  /// Bits 38:32
+    U32       : 25; /// Bits 63:39
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MRC_PCI_000_TOM_HIGH_STRUCT;
+
+typedef union {
+  struct {
+    U64 Lock  : 1;  /// Bits 0:0
+    U64       : 19; /// Bits 19:1
+    U64 Value : 19; /// Bits 38:20
+    U64       : 25; /// Bits 63:39
+  } Bits;
+  U64 Data;
+  struct {
+    MRC_PCI_000_TOM_LOW_STRUCT  Low;
+    MRC_PCI_000_TOM_HIGH_STRUCT High;
+  } Data32;
+} MRC_PCI_000_TOM_STRUCT;
+
+#define MRC_PCI_000_TOM_REG (0xA0)
+  #define TOM_LOCK_OFF      (0)
+  #define TOM_LOCK_WID      (1)
+  #define TOM_LOCK_MSK      (0x1)
+  #define TOM_LOCK_MAX      (0x1)
+  #define TOM_LOCK_DEF      (0x0)
+  #define TOM_TOM_OFF       (20)
+  #define TOM_TOM_WID       (19)
+  #define TOM_TOM_MSK       (0x7FFFF00000)
+  #define TOM_TOM_MAX       (0x7FFFF)
+  #define TOM_TOM_DEF       (0x7FFFF)
+
+typedef union {
+  struct {
+    U32 Lock  : 1;  /// Bits 0:0
+    U32       : 19; /// Bits 19:1
+    U32 Value : 12; /// Bits 31:20
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MRC_PCI_000_TOUUD_LOW_STRUCT;
+
+typedef union {
+  struct {
+    U32 Value : 7;  /// Bits 38:32
+    U32       : 25; /// Bits 63:39
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MRC_PCI_000_TOUUD_HIGH_STRUCT;
+
+typedef union {
+  struct {
+    U64 Lock  : 1;  /// Bits 0:0
+    U64       : 19; /// Bits 19:1
+    U64 Value : 19; /// Bits 38:20
+    U64       : 25; /// Bits 63:39
+  } Bits;
+  U64 Data;
+  struct {
+    MRC_PCI_000_TOUUD_LOW_STRUCT  Low;
+    MRC_PCI_000_TOUUD_HIGH_STRUCT High;
+  } Data32;
+} MRC_PCI_000_TOUUD_STRUCT;
+
+#define MRC_PCI_000_TOUUD_REG (0xA8)
+  #define TOUUD_LOCK_OFF      (0)
+  #define TOUUD_LOCK_WID      (1)
+  #define TOUUD_LOCK_MSK      (0x1)
+  #define TOUUD_LOCK_MAX      (0x1)
+  #define TOUUD_LOCK_DEF      (0x0)
+  #define TOUUD_TOUUD_OFF     (20)
+  #define TOUUD_TOUUD_WID     (19)
+  #define TOUUD_TOUUD_MSK     (0x7FFFF00000)
+  #define TOUUD_TOUUD_MAX     (0x7FFFF)
+  #define TOUUD_TOUUD_DEF     (0x0)
+
+typedef union {
+  struct {
+    U32 Lock  : 1;  /// Bits 0:0
+    U32       : 19; /// Bits 19:1
+    U32 Value : 12; /// Bits 31:20
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MRC_PCI_000_BDSM_STRUCT;
+
+#define MRC_PCI_000_BDSM_REG (0xB0)
+  #define BDSM_LOCK_OFF      (0)
+  #define BDSM_LOCK_WID      (1)
+  #define BDSM_LOCK_MSK      (0x1)
+  #define BDSM_LOCK_MAX      (0x1)
+  #define BDSM_LOCK_DEF      (0x0)
+  #define BDSM_BDSM_OFF      (20)
+  #define BDSM_BDSM_WID      (12)
+  #define BDSM_BDSM_MSK      (0xFFF00000)
+  #define BDSM_BDSM_MAX      (0xFFF)
+  #define BDSM_BDSM_DEF      (0x0)
+
+typedef union {
+  struct {
+    U32 Lock  : 1;  /// Bits 0:0
+    U32       : 19; /// Bits 19:1
+    U32 Value : 12; /// Bits 31:20
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MRC_PCI_000_BGSM_STRUCT;
+
+#define MRC_PCI_000_BGSM_REG (0xB4)
+  #define BGSM_LOCK_OFF      (0)
+  #define BGSM_LOCK_WID      (1)
+  #define BGSM_LOCK_MSK      (0x1)
+  #define BGSM_LOCK_MAX      (0x1)
+  #define BGSM_LOCK_DEF      (0x0)
+  #define BGSM_BGSM_OFF      (20)
+  #define BGSM_BGSM_WID      (12)
+  #define BGSM_BGSM_MSK      (0xFFF00000)
+  #define BGSM_BGSM_MAX      (0xFFF)
+  #define BGSM_BGSM_DEF      (0x001)
+
+typedef union {
+  struct {
+    U32 Lock  : 1;  /// Bits 0:0
+    U32       : 19; /// Bits 19:1
+    U32 Value : 12; /// Bits 31:20
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MRC_PCI_000_TSEGMB_STRUCT;
+
+#define MRC_PCI_000_TSEGMB_REG (0xB8)
+  #define TSEGMB_LOCK_OFF      (0)
+  #define TSEGMB_LOCK_WID      (1)
+  #define TSEGMB_LOCK_MSK      (0x1)
+  #define TSEGMB_LOCK_MAX      (0x1)
+  #define TSEGMB_LOCK_DEF      (0x0)
+  #define TSEGMB_TSEGMB_OFF    (20)
+  #define TSEGMB_TSEGMB_WID    (12)
+  #define TSEGMB_TSEGMB_MSK    (0xFFF00000)
+  #define TSEGMB_TSEGMB_MAX    (0xFFF)
+  #define TSEGMB_TSEGMB_DEF    (0x0)
+
+typedef union {
+  struct {
+    U32 Lock    : 1;  /// Bits 0:0
+    U32 Prs     : 1;  /// Bits 1:1
+    U32 Epm     : 1;  /// Bits 2:2
+    U32         : 1;  /// Bits 3:3
+    U32 Dprsize : 8;  /// Bits 11:4
+    U32         : 20; /// Bits 31:12
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MRC_PCI_000_DPR_STRUCT;
+
+#define MRC_PCI_000_DPR_REG (0x5c)
+  #define DPR_LOCK_OFF      (0)
+  #define DPR_LOCK_WID      (1)
+  #define DPR_LOCK_MSK      (0x1)
+  #define DPR_LOCK_MAX      (0x1)
+  #define DPR_LOCK_DEF      (0x0)
+  #define DPR_EPM_OFF       (2)
+  #define DPR_EPM_WID       (1)
+  #define DPR_EPM_MSK       (0x4)
+  #define DPR_EPM_MAX       (0x1)
+  #define DPR_EPM_DEF       (0x0)
+
+typedef union {
+  struct {
+    U32 Lock  : 1;  /// Bits 0:0
+    U32       : 19; /// Bits 19:1
+    U32 Value : 12; /// Bits 31:20
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MRC_PCI_000_TOLUD_STRUCT;
+
+#define MRC_PCI_000_TOLUD_REG (0xBC)
+  #define TOLUD_LOCK_OFF      (0)
+  #define TOLUD_LOCK_WID      (1)
+  #define TOLUD_LOCK_MSK      (0x1)
+  #define TOLUD_LOCK_MAX      (0x1)
+  #define TOLUD_LOCK_DEF      (0x0)
+  #define TOLUD_TOLUD_OFF     (20)
+  #define TOLUD_TOLUD_WID     (12)
+  #define TOLUD_TOLUD_MSK     (0xFFF00000)
+  #define TOLUD_TOLUD_MAX     (0xFFF)
+  #define TOLUD_TOLUD_DEF     (0x001)
+
+typedef union {
+  struct {
+    U32 DDR3L_EN        : 1;  /// Bits 0:0
+    U32 DDR_WRTVREF     : 1;  /// Bits 1:1
+    U32 OC_ENABLED_DSKU : 1;  /// Bits 2:2
+    U32 DDR_OVERCLOCK   : 1;  /// Bits 3:3
+    U32 CRID            : 4;  /// Bits 7:4
+    U32 CDID            : 2;  /// Bits 9:8
+    U32 DIDOE           : 1;  /// Bits 10:10
+    U32 IGD             : 1;  /// Bits 11:11
+    U32 PDCD            : 1;  /// Bits 12:12
+    U32 X2APIC_EN       : 1;  /// Bits 13:13
+    U32 DDPCD           : 1;  /// Bits 14:14
+    U32 CDD             : 1;  /// Bits 15:15
+    U32 FUFRD           : 1;  /// Bits 16:16
+    U32 D1NM            : 1;  /// Bits 17:17
+    U32 PCIE_RATIO_DIS  : 1;  /// Bits 18:18
+    U32 DDRSZ           : 2;  /// Bits 20:19
+    U32 PEGG2DIS        : 1;  /// Bits 21:21
+    U32 DMIG2DIS        : 1;  /// Bits 22:22
+    U32 VTDDD           : 1;  /// Bits 23:23
+    U32 FDEE            : 1;  /// Bits 24:24
+    U32 ECCDIS          : 1;  /// Bits 25:25
+    U32 DW              : 1;  /// Bits 26:26
+    U32 PELWUD          : 1;  /// Bits 27:27
+    U32 PEG10D          : 1;  /// Bits 28:28
+    U32 PEG11D          : 1;  /// Bits 29:29
+    U32 PEG12D          : 1;  /// Bits 30:30
+    U32 DHDAD           : 1;  /// Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MRC_PCI_000_CAPID0_A_STRUCT;
+
+#define MRC_PCI_000_CAPID0_REG        (0xE4)
+#define MRC_PCI_000_CAPID0_A_REG      (0xE4)
+  #define CAPID0_A_DDR3L_EN_OFF       (0)
+  #define CAPID0_A_DDR3L_EN_WID       (1)
+  #define CAPID0_A_DDR3L_EN_MSK       (0x1)
+  #define CAPID0_A_DDR3L_EN_MAX       (0x1)
+  #define CAPID0_A_DDR3L_EN_DEF       (0x0)
+  #define CAPID0_A_DDR_WRTVREF_OFF    (0x0)
+  #define CAPID0_A_DDR_WRTVREF_WID    (0x1)
+  #define CAPID0_A_DDR_WRTVREF_MSK    (0x1)
+  #define CAPID0_A_DDR_WRTVREF_MAX    (0x1)
+  #define CAPID0_A_DDR_WRTVREF_DEF    (0x0)
+  #define CAPID0_A_DDR_OVERCLOCK_OFF  (3)
+  #define CAPID0_A_DDR_OVERCLOCK_WID  (1)
+  #define CAPID0_A_DDR_OVERCLOCK_MSK  (0x8)
+  #define CAPID0_A_DDR_OVERCLOCK_MAX  (0x1)
+  #define CAPID0_A_DDR_OVERCLOCK_DEF  (0x0)
+  #define CAPID0_A_CRID_OFF           (4)
+  #define CAPID0_A_CRID_WID           (4)
+  #define CAPID0_A_CRID_MSK           (0xF0)
+  #define CAPID0_A_CRID_MAX           (0xF)
+  #define CAPID0_A_CRID_DEF           (0x0)
+  #define CAPID0_A_CDID_OFF           (8)
+  #define CAPID0_A_CDID_WID           (2)
+  #define CAPID0_A_CDID_MSK           (0x300)
+  #define CAPID0_A_CDID_MAX           (0x3)
+  #define CAPID0_A_CDID_DEF           (0x0)
+  #define CAPID0_A_DIDOE_OFF          (10)
+  #define CAPID0_A_DIDOE_WID          (1)
+  #define CAPID0_A_DIDOE_MSK          (0x400)
+  #define CAPID0_A_DIDOE_MAX          (0x1)
+  #define CAPID0_A_DIDOE_DEF          (0x0)
+  #define CAPID0_A_IGD_OFF            (11)
+  #define CAPID0_A_IGD_WID            (1)
+  #define CAPID0_A_IGD_MSK            (0x800)
+  #define CAPID0_A_IGD_MAX            (0x1)
+  #define CAPID0_A_IGD_DEF            (0x0)
+  #define CAPID0_A_PDCD_OFF           (12)
+  #define CAPID0_A_PDCD_WID           (1)
+  #define CAPID0_A_PDCD_MSK           (0x1000)
+  #define CAPID0_A_PDCD_MAX           (0x1)
+  #define CAPID0_A_PDCD_DEF           (0x0)
+  #define CAPID0_A_X2APIC_EN_OFF      (13)
+  #define CAPID0_A_X2APIC_EN_WID      (1)
+  #define CAPID0_A_X2APIC_EN_MSK      (0x2000)
+  #define CAPID0_A_X2APIC_EN_MAX      (0x1)
+  #define CAPID0_A_X2APIC_EN_DEF      (0x0)
+  #define CAPID0_A_DDPCD_OFF          (14)
+  #define CAPID0_A_DDPCD_WID          (1)
+  #define CAPID0_A_DDPCD_MSK          (0x4000)
+  #define CAPID0_A_DDPCD_MAX          (0x1)
+  #define CAPID0_A_DDPCD_DEF          (0x0)
+  #define CAPID0_A_CDD_OFF            (15)
+  #define CAPID0_A_CDD_WID            (1)
+  #define CAPID0_A_CDD_MSK            (0x8000)
+  #define CAPID0_A_CDD_MAX            (0x1)
+  #define CAPID0_A_CDD_DEF            (0x0)
+  #define CAPID0_A_FUFRD_OFF          (16)
+  #define CAPID0_A_FUFRD_WID          (1)
+  #define CAPID0_A_FUFRD_MSK          (0x10000)
+  #define CAPID0_A_FUFRD_MAX          (0x1)
+  #define CAPID0_A_FUFRD_DEF          (0x0)
+  #define CAPID0_A_D1NM_OFF           (17)
+  #define CAPID0_A_D1NM_WID           (1)
+  #define CAPID0_A_D1NM_MSK           (0x20000)
+  #define CAPID0_A_D1NM_MAX           (0x1)
+  #define CAPID0_A_D1NM_DEF           (0x0)
+  #define CAPID0_A_PEGX16D_OFF        (18)
+  #define CAPID0_A_PEGX16D_WID        (1)
+  #define CAPID0_A_PEGX16D_MSK        (0x40000)
+  #define CAPID0_A_PEGX16D_MAX        (0x1)
+  #define CAPID0_A_PEGX16D_DEF        (0x0)
+  #define CAPID0_A_DDRSZ_OFF          (19)
+  #define CAPID0_A_DDRSZ_WID          (2)
+  #define CAPID0_A_DDRSZ_MSK          (0x180000)
+  #define CAPID0_A_DDRSZ_MAX          (0x3)
+  #define CAPID0_A_DDRSZ_DEF          (0x0)
+  #define CAPID0_A_PEGG2DIS_OFF       (21)
+  #define CAPID0_A_PEGG2DIS_WID       (1)
+  #define CAPID0_A_PEGG2DIS_MSK       (0x200000)
+  #define CAPID0_A_PEGG2DIS_MAX       (0x1)
+  #define CAPID0_A_PEGG2DIS_DEF       (0x0)
+  #define CAPID0_A_DMIG2DIS_OFF       (22)
+  #define CAPID0_A_DMIG2DIS_WID       (1)
+  #define CAPID0_A_DMIG2DIS_MSK       (0x400000)
+  #define CAPID0_A_DMIG2DIS_MAX       (0x1)
+  #define CAPID0_A_DMIG2DIS_DEF       (0x0)
+  #define CAPID0_A_VTDD_OFF           (23)
+  #define CAPID0_A_VTDD_WID           (1)
+  #define CAPID0_A_VTDD_MSK           (0x800000)
+  #define CAPID0_A_VTDD_MAX           (0x1)
+  #define CAPID0_A_VTDD_DEF           (0x0)
+  #define CAPID0_A_FDEE_OFF           (24)
+  #define CAPID0_A_FDEE_WID           (1)
+  #define CAPID0_A_FDEE_MSK           (0x1000000)
+  #define CAPID0_A_FDEE_MAX           (0x1)
+  #define CAPID0_A_FDEE_DEF           (0x0)
+  #define CAPID0_A_ECCDIS_OFF         (25)
+  #define CAPID0_A_ECCDIS_WID         (1)
+  #define CAPID0_A_ECCDIS_MSK         (0x2000000)
+  #define CAPID0_A_ECCDIS_MAX         (0x1)
+  #define CAPID0_A_ECCDIS_DEF         (0x0)
+  #define CAPID0_A_DW_OFF             (26)
+  #define CAPID0_A_DW_WID             (1)
+  #define CAPID0_A_DW_MSK             (0x4000000)
+  #define CAPID0_A_DW_MAX             (0x1)
+  #define CAPID0_A_DW_DEF             (0x0)
+  #define CAPID0_A_PELWUD_OFF         (27)
+  #define CAPID0_A_PELWUD_WID         (1)
+  #define CAPID0_A_PELWUD_MSK         (0x8000000)
+  #define CAPID0_A_PELWUD_MAX         (0x1)
+  #define CAPID0_A_PELWUD_DEF         (0x0)
+  #define CAPID0_A_PEG10D_OFF         (28)
+  #define CAPID0_A_PEG10D_WID         (1)
+  #define CAPID0_A_PEG10D_MSK         (0x10000000)
+  #define CAPID0_A_PEG10D_MAX         (0x1)
+  #define CAPID0_A_PEG10D_DEF         (0x0)
+  #define CAPID0_A_PEG11D_OFF         (29)
+  #define CAPID0_A_PEG11D_WID         (1)
+  #define CAPID0_A_PEG11D_MSK         (0x20000000)
+  #define CAPID0_A_PEG11D_MAX         (0x1)
+  #define CAPID0_A_PEG11D_DEF         (0x0)
+  #define CAPID0_A_PEG12D_OFF         (30)
+  #define CAPID0_A_PEG12D_WID         (1)
+  #define CAPID0_A_PEG12D_MSK         (0x40000000)
+  #define CAPID0_A_PEG12D_MAX         (0x1)
+  #define CAPID0_A_PEG12D_DEF         (0x0)
+
+typedef union {
+  struct {
+    U32 SPEGFX1         : 1;  /// Bits 0:0
+    U32 DPEGFX1         : 1;  /// Bits 1:1
+    U32                 : 2;  /// Bits 3:2
+    U32 DMFC            : 3;  /// Bits 6:4
+    U32 DDD             : 1;  /// Bits 7:7
+    U32                 : 3;  /// Bits 10:8
+    U32 HDCPD           : 1;  /// Bits 11:11
+    U32                 : 4;  /// Bits 15:12
+    U32 PEGX16D         : 1;  /// Bits 16:16
+    U32 ADDGFXCAP       : 1;  /// Bits 17:17
+    U32 ADDGFXEN        : 1;  /// Bits 18:18
+    U32 PKGTYP          : 1;  /// Bits 19:19
+    U32 PEGG3_DIS       : 1;  /// Bits 20:20
+    U32 PLL_REF100_CFG  : 3;  /// Bits 23:21
+    U32 SOFTBIN         : 1;  /// Bits 24:24
+    U32 CACHESZ         : 3;  /// Bits 27:25
+    U32 SMT             : 1;  /// Bits 28:28
+    U32 OC_ENABLED_SSKU : 1;  /// Bits 29:29
+    U32 OC_CTL_SSKU     : 1;  /// Bits 30:30
+    U32                 : 1;  /// Bits 31:31
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} MRC_PCI_000_CAPID0_B_STRUCT;
+
+#define MRC_PCI_000_CAPID0_B_REG        (0xE8)
+  #define CAPID0_B_SPEGFX1_OFF          (0)
+  #define CAPID0_B_SPEGFX1_WID          (1)
+  #define CAPID0_B_SPEGFX1_MSK          (0x1)
+  #define CAPID0_B_SPEGFX1_MAX          (0x1)
+  #define CAPID0_B_SPEGFX1_DEF          (0x0)
+  #define CAPID0_B_DPEGFX1_OFF          (1)
+  #define CAPID0_B_DPEGFX1_WID          (1)
+  #define CAPID0_B_DPEGFX1_MSK          (0x2)
+  #define CAPID0_B_DPEGFX1_MAX          (0x1)
+  #define CAPID0_B_DPEGFX1_DEF          (0x0)
+  #define CAPID0_B_DMFC_OFF             (4)
+  #define CAPID0_B_DMFC_WID             (3)
+  #define CAPID0_B_DMFC_MSK             (0x70)
+  #define CAPID0_B_DMFC_MAX             (0x7)
+  #define CAPID0_B_DMFC_DEF             (0x0)
+  #define CAPID0_B_DDD_OFF              (7)
+  #define CAPID0_B_DDD_WID              (1)
+  #define CAPID0_B_DDD_MSK              (0x80)
+  #define CAPID0_B_DDD_MAX              (0x1)
+  #define CAPID0_B_DDD_DEF              (0x0)
+  #define CAPID0_B_HGKS_OFF             (8)
+  #define CAPID0_B_HGKS_WID             (3)
+  #define CAPID0_B_HGKS_MSK             (0x700)
+  #define CAPID0_B_HGKS_MAX             (0x7)
+  #define CAPID0_B_HGKS_DEF             (0x0)
+  #define CAPID0_B_HDCPD_OFF            (11)
+  #define CAPID0_B_HDCPD_WID            (1)
+  #define CAPID0_B_HDCPD_MSK            (0x800)
+  #define CAPID0_B_HDCPD_MAX            (0x1)
+  #define CAPID0_B_HDCPD_DEF            (0x0)
+  #define CAPID0_B_ADDGFXCAP_OFF        (17)
+  #define CAPID0_B_ADDGFXCAP_WID        (1)
+  #define CAPID0_B_ADDGFXCAP_MSK        (0x20000)
+  #define CAPID0_B_ADDGFXCAP_MAX        (0x1)
+  #define CAPID0_B_ADDGFXCAP_DEF        (0x0)
+  #define CAPID0_B_ADDGFXEN_OFF         (18)
+  #define CAPID0_B_ADDGFXEN_WID         (1)
+  #define CAPID0_B_ADDGFXEN_MSK         (0x40000)
+  #define CAPID0_B_ADDGFXEN_MAX         (0x1)
+  #define CAPID0_B_ADDGFXEN_DEF         (0x0)
+  #define CAPID0_B_PKGTYP_OFF           (19)
+  #define CAPID0_B_PKGTYP_WID           (1)
+  #define CAPID0_B_PKGTYP_MSK           (0x80000)
+  #define CAPID0_B_PKGTYP_MAX           (0x1)
+  #define CAPID0_B_PKGTYP_DEF           (0x0)
+  #define CAPID0_B_PLL_REF100_CFG_OFF   (21)
+  #define CAPID0_B_PLL_REF100_CFG_WID   (3)
+  #define CAPID0_B_PLL_REF100_CFG_MSK   (0xE00000)
+  #define CAPID0_B_PLL_REF100_CFG_MAX   (0x7)
+  #define CAPID0_B_PLL_REF100_CFG_DEF   (0x0)
+  #define CAPID0_B_SOFTBIN_OFF          (24)
+  #define CAPID0_B_SOFTBIN_WID          (1)
+  #define CAPID0_B_SOFTBIN_MSK          (0x1000000)
+  #define CAPID0_B_SOFTBIN_MAX          (0x1)
+  #define CAPID0_B_SOFTBIN_DEF          (0x0)
+  #define CAPID0_B_CACHESZ_OFF          (25)
+  #define CAPID0_B_CACHESZ_WID          (3)
+  #define CAPID0_B_CACHESZ_MSK          (0xe000000)
+  #define CAPID0_B_CACHESZ_MAX          (0x7)
+  #define CAPID0_B_CACHESZ_DEF          (0x0)
+  #define CAPID0_B_SMT_OFF              (28)
+  #define CAPID0_B_SMT_WID              (1)
+  #define CAPID0_B_SMT_MSK              (0x10000000)
+  #define CAPID0_B_SMT_MAX              (0x1)
+  #define CAPID0_B_SMT_DEF              (0x0)
+  #define CAPID0_B_OC_ENABLED_SSKU_OFF  (29)
+  #define CAPID0_B_OC_ENABLED_SSKU_WID  (1)
+  #define CAPID0_B_OC_ENABLED_SSKU_MSK  (0x20000000)
+  #define CAPID0_B_OC_ENABLED_SSKU_MAX  (0x1)
+  #define CAPID0_B_OC_ENABLED_SSKU_DEF  (0x0)
+
+typedef union {
+  struct {
+    U64 DDR3L_EN        : 1;  /// Bits 0:0
+    U64 DDR_WRTVREF     : 1;  /// Bits 1:1
+    U64 OC_ENABLED_DSKU : 1;  /// Bits 2:2
+    U64 DDR_OVERCLOCK   : 1;  /// Bits 3:3
+    U64 CRID            : 4;  /// Bits 7:4
+    U64 CDID            : 2;  /// Bits 9:8
+    U64 DIDOE           : 1;  /// Bits 10:10
+    U64 IGD             : 1;  /// Bits 11:11
+    U64 PDCD            : 1;  /// Bits 12:12
+    U64 X2APIC_EN       : 1;  /// Bits 13:13
+    U64 DDPCD           : 1;  /// Bits 14:14
+    U64 CDD             : 1;  /// Bits 15:15
+    U64 FUFRD           : 1;  /// Bits 16:16
+    U64 D1NM            : 1;  /// Bits 17:17
+    U64 PCIE_RATIO_DIS  : 1;  /// Bits 18:18
+    U64 DDRSZ           : 2;  /// Bits 20:19
+    U64 PEGG2DIS        : 1;  /// Bits 21:21
+    U64 DMIG2DIS        : 1;  /// Bits 22:22
+    U64 VTDDD           : 1;  /// Bits 23:23
+    U64 FDEE            : 1;  /// Bits 24:24
+    U64 ECCDIS          : 1;  /// Bits 25:25
+    U64 DW              : 1;  /// Bits 26:26
+    U64 PELWUD          : 1;  /// Bits 27:27
+    U64 PEG10D          : 1;  /// Bits 28:28
+    U64 PEG11D          : 1;  /// Bits 29:29
+    U64 PEG12D          : 1;  /// Bits 30:30
+    U64 DHDAD           : 1;  /// Bits 31:31
+    U64 SPEGFX1         : 1;  /// Bits 32:32
+    U64 DPEGFX1         : 1;  /// Bits 33:33
+    U64                 : 2;  /// Bits 35:34
+    U64 DMFC            : 3;  /// Bits 38:36
+    U64 DDD             : 1;  /// Bits 39:39
+    U64                 : 3;  /// Bits 42:40
+    U64 HDCPD           : 1;  /// Bits 43:43
+    U64                 : 4;  /// Bits 47:44
+    U64 PEGX16D         : 1;  /// Bits 48:48
+    U64 ADDGFXCAP       : 1;  /// Bits 49:49
+    U64 ADDGFXEN        : 1;  /// Bits 50:50
+    U64 PKGTYP          : 1;  /// Bits 51:51
+    U64 PEGG3_DIS       : 1;  /// Bits 52:52
+    U64 PLL_REF100_CFG  : 3;  /// Bits 55:53
+    U64 SOFTBIN         : 1;  /// Bits 56:56
+    U64 CACHESZ         : 3;  /// Bits 59:57
+    U64 SMT             : 1;  /// Bits 60:60
+    U64 OC_ENABLED_SSKU : 1;  /// Bits 61:61
+    U64 OC_CTL_SSKU     : 1;  /// Bits 62:62
+    U64                 : 1;  /// Bits 63:63
+  } Bits;
+  U64 Data;
+  struct {
+    MRC_PCI_000_CAPID0_A_STRUCT A;
+    MRC_PCI_000_CAPID0_B_STRUCT B;
+  } Data32;
+} MRC_PCI_000_CAPID0_STRUCT;
+
+#pragma pack (pop)
+#endif /// _Pci000_h_
diff --git a/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcRegisters/PttHciRegs.h b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcRegisters/PttHciRegs.h
new file mode 100644
index 0000000..5646768
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcRegisters/PttHciRegs.h
@@ -0,0 +1,101 @@
+/**
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement
+
+@copyright
+  Copyright (c) 2012 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+@file
+  PttHciRegs.h
+
+@brief
+  Register definitions for PTT HCI (Platform Trust Technology - Host Controller Interface).
+
+  Conventions:
+
+  - Prefixes:
+    Definitions beginning with "R_" are registers
+    Definitions beginning with "B_" are bits within registers
+    Definitions beginning with "V_" are meaningful values of bits within the registers
+    Definitions beginning with "S_" are register sizes
+    Definitions beginning with "N_" are the bit position
+**/
+#ifndef _PTT_HCI_REGS_H_
+#define _PTT_HCI_REGS_H_
+
+#ifdef PTT_FLAG
+
+///
+/// FTPM HCI register base address
+///
+#define R_PTT_HCI_BASE_ADDRESS             0xFED70000
+
+///
+/// FTPM HCI Control Area
+///
+#define R_PTT_HCI_CA_RSVD                  0x00
+#define R_PTT_HCI_CA_ERROR                 0x04
+#define R_PTT_HCI_CA_CANCEL                0x08
+#define R_PTT_HCI_CA_START                 0x0C
+#define R_PTT_HCI_CA_INT_RSVD              0x10
+#define R_PTT_HCI_CA_CMD_SZ                0x18
+#define R_PTT_HCI_CA_CMD                   0x1C
+#define R_PTT_HCI_CA_RSP_SZ                0x24
+#define R_PTT_HCI_CA_RSP                   0x28
+
+///
+/// FTPM HCI Private Area
+///
+#define R_PTT_HCI_CMD                      0x40
+#define R_PTT_HCI_STS                      0x44
+
+///
+/// FTPM HCI Command and Response Buffer
+///
+#define R_PTT_HCI_CRB                      0x80
+
+///
+/// R_PTT_HCI_STS Flags
+///
+#define B_PTT_HCI_STS_ENABLED              0x00000001 ///< BIT0
+#define B_PTT_HCI_STS_READY                0x00000002 ///< BIT1
+#define B_PTT_HCI_STS_ACM_AS_CRTM          0x00000004 ///< BIT2
+#define B_PTT_HCI_STS_STARTUP_EXEC         0x00000008 ///< BIT3
+
+///
+/// Value written to R_PTT_HCI_CMD and CA_START
+/// to indicate that a command is available for processing
+///
+#define V_PTT_HCI_COMMAND_AVAILABLE_START  0x00000001
+#define V_PTT_HCI_COMMAND_AVAILABLE_CMD    0x00000000
+#define V_PTT_HCI_BUFFER_ADDRESS_RDY       0x00000003
+
+///
+/// Ignore bit setting mask for WaitRegisterBits
+///
+#define V_PTT_HCI_IGNORE_BITS              0x00000000
+
+///
+/// All bits clear mask for WaitRegisterBits
+///
+#define V_PTT_HCI_ALL_BITS_CLEAR           0xFFFFFFFF
+#define V_PTT_HCI_START_CLEAR              0x00000001
+
+///
+/// Max FTPM command/reponse buffer length
+///
+#define S_PTT_HCI_CRB_LENGTH               3968 ///< 0xFED70080:0xFED70FFF = 3968 Bytes
+
+#endif /// PTT_FLAG
+#endif
diff --git a/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcReset.h b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcReset.h
new file mode 100644
index 0000000..7b95234
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcReset.h
@@ -0,0 +1,127 @@
+/** @file
+  The DDR3 reset sequence definitions.
+
+@copyright
+  Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved.
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement.
+**/
+
+#ifndef _MrcReset_h_
+#define _MrcReset_h_
+
+#include "MrcTypes.h"
+#include "MrcApi.h"
+#include "McAddress.h"
+#include "MrcCommon.h"
+#include "MrcDdr3.h"
+#include "MrcOemPlatform.h"
+
+#include "PchRegsRcrb.h"
+
+/**
+@brief
+  Perform full JEDEC reset and init sequence.
+
+  @param[in] MrcData - Include all MRC global data.
+
+  @retval MrcStatus - mrcSuccess or reason for failure.
+**/
+extern
+MrcStatus
+MrcResetSequence (
+  IN MrcParameters *const MrcData
+  );
+
+/**
+@brief
+  Perform JEDEC DIMM reset sequence.
+
+  @param[in] MrcData - Include all MRC global data.
+
+  @retval - none
+**/
+extern
+void
+MrcJedecReset (
+  IN MrcParameters *const MrcData
+  );
+
+#ifdef ULT_FLAG
+
+/**
+@brief
+  Perform JEDEC LPDDR3 DIMM reset sequence.
+
+  @param[in] MrcData - Include all MRC global data.
+
+  @retval mrcSuccess if succeeded
+**/
+extern
+MrcStatus
+MrcJedecResetLpddr3 (
+  IN MrcParameters *const MrcData
+  );
+
+/**
+@brief
+  Perform JEDEC LPDDR3 DIMM init sequence.
+
+  @param[in] MrcData - Include all MRC global data.
+
+  @retval mrcSuccess if succeeded
+**/
+MrcStatus
+MrcJedecInitLpddr3 (
+  IN MrcParameters *const MrcData
+  );
+
+#endif // ULT_FLAG
+
+/**
+@brief
+  Wait in a loop until the first RCOMP has been completed.
+  MRC should wait until this bit is set before executing any DDR command.
+
+  @param[in] MrcData - Include all MRC global data.
+
+  @retval mrcDeviceBusy - On Rcomp completion timeout.
+  @retval mrcSuccess    - On Rcomp completion.
+**/
+extern
+MrcStatus
+CheckFirstRcompDone (
+  IN MrcParameters *const MrcData
+  );
+
+/**
+@brief
+  Perform the required steps to exit self refresh in S3/Warm reset:
+    Download the Read Reg File for all populated ranks.
+    Assert CKE for all the ranks present to pull Dimms out of Self-Refresh.
+    Issue long ZQ Calibration for all the ranks present in the channel.
+    Set REUT to normal mode for all channels.
+    Set the Power Down Config Register.
+
+  @param[in] MrcData - Include all MRC global data.
+
+  @retval mrcSuccess
+**/
+MrcStatus
+MrcSelfRefreshExit (
+  IN MrcParameters *const MrcData
+  );
+
+#endif // _MrcReset_h_
diff --git a/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcRmtData.h b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcRmtData.h
new file mode 100644
index 0000000..38f1c08
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcRmtData.h
@@ -0,0 +1,226 @@
+/** @file
+  Copies the memory related timing and configuration information into the
+  Compatible BIOS data (BDAT) table.
+
+@copyright
+  Copyright (c) 2010 - 2012 Intel Corporation. All rights reserved.
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement.
+**/
+#ifndef _MrcRmtData_h_
+#define _MrcRmtData_h_
+
+#include "MrcTypes.h"
+#include "MrcApi.h"
+
+#define VDD_1_350             1350                      ///< VDD in millivolts
+#define VDD_1_500             1500                      ///< VDD in millivolts
+#define PI_STEP_BASE          2048                      ///< Magic number from spec
+#define PI_STEP_INTERVAL      128                       ///< tCK is split into this amount of intervals
+#define PI_STEP               ((PI_STEP_BASE) / (PI_STEP_INTERVAL))
+#define VREF_STEP_BASE        100                       ///< Magic number from spec
+#define TX_VREF_STEP          7800                      ///< TX Vref step in microvolts
+#define TX_VREF(VDD)          (((TX_VREF_STEP) * (VREF_STEP_BASE)) / (VDD)) ///< VDD passed in is in millivolts
+#define RX_VREF_STEP          8000                      ///< TX Vref step in microvolts
+#define RX_VREF(VDD)          (((RX_VREF_STEP) * (VREF_STEP_BASE)) / (VDD)) ///< VDD passed in is in millivolts
+#define CA_VREF_STEP          8000                      ///< TX Vref step in microvolts
+#define CA_VREF(VDD)          (((CA_VREF_STEP) * (VREF_STEP_BASE)) / (VDD)) ///< VDD passed in is in millivolts
+#define PRIMARY_OFFSET        0                         ///< Offset into the BDAT header version.
+#define SECONDARY_OFFSET      1                         ///< Offset into the BDAT header version.
+#define RMT_PRIMARY_VERSION   3                         ///< The BDAT structure that is currently supported.
+#define RMT_SECONDARY_VERSION 0                         ///< The BDAT structure that is currently supported.
+#define OEM_OFFSET            0                         ///< The current offset to the OEM data in the BDAT structure.
+#define MAX_SPD_RMT           256                       ///< The maximum amount of data, in bytes, in an SPD structure.
+
+#pragma pack(push, 1)
+
+typedef struct {
+  U8                          BiosDataSignature[CHAR_BITS * sizeof (U8)]; ///< "BDATHEAD"
+  U32                         BiosDataStructSize;       ///< sizeof BDAT_STRUCTURE
+  U16                         Crc16;                    ///< 16-bit CRC of BDAT_STRUCTURE (calculated with 0 in this field)
+  U16                         Reserved;
+  union {
+    U32                       L;
+    U16                       S[2];
+  }                           Version;                  ///< Version, primary then secondary.
+  U32                         OemOffset;                ///< Optional offset to OEM-defined structure
+  U32                         Reserved1;
+  U32                         Reserved2;
+} RmtHeader;
+
+typedef struct {
+  U8                          RxDqLeft;                 ///< Units = piStep
+  U8                          RxDqRight;
+  U8                          TxDqLeft;
+  U8                          TxDqRight;
+  U8                          RxVrefLow;                ///< Units = rxVrefStep
+  U8                          RxVrefHigh;
+  U8                          TxVrefLow;                ///< Units = txVrefStep
+  U8                          TxVrefHigh;
+} RmtDqMargin;
+
+typedef struct {
+  U8                          RxDqLeft;                 ///< Units = piStep
+  U8                          RxDqRight;
+  U8                          TxDqLeft;
+  U8                          TxDqRight;
+  U8                          CmdLeft;
+  U8                          CmdRight;
+  U8                          RecvenLeft;               ///< Units = recvenStep
+  U8                          RecvenRight;
+  U8                          WrLevelLeft;              ///< Units = wrLevelStep
+  U8                          WrLevelRight;
+  U8                          RxVrefLow;                ///< Units = rxVrefStep
+  U8                          RxVrefHigh;
+  U8                          TxVrefLow;                ///< Units = txVrefStep
+  U8                          TxVrefHigh;
+  U8                          CmdVrefLow;               ///< Units = caVrefStep
+  U8                          CmdVrefHigh;
+} RmtRankMargin;
+
+typedef struct {
+  U16                         RecEnDelay[MAX_STROBE];
+  U16                         WlDelay[MAX_STROBE];
+  U8                          RxDqDelay[MAX_STROBE];
+  U8                          TxDqDelay[MAX_STROBE];
+  U8                          ClkDelay;
+  U8                          CtlDelay;
+  U8                          CmdDelay[3];
+  U8                          IoLatency;
+  U8                          Roundtrip;
+} RmtRankTraining;
+
+typedef union {
+  U16                         ModeRegister[MAX_MR_IN_DIMM]; ///< Dimm mode registers MR0 - MR3.
+#if 0
+  struct {
+    struct {
+      U16                     BurstLength     : 2;      ///<   A1:A0 - Burst length
+      U16                     CasLatency0     : 1;      ///<      A2 - CAS latency bit 0
+      U16                     ReadBurstType   : 1;      ///<      A3 - Read burst type
+      U16                     CasLatency      : 3;      ///<   A6:A4 - CAS latency bits 3:1
+      U16                     Mode            : 1;      ///<      A7 - Test/Normal mode
+      U16                     DllReset        : 1;      ///<      A8 - DLL reset
+      U16                     WriteRecovery   : 3;      ///<  A11:A9 - CAS latency bits 3:1
+      U16                     DllPd           : 1;      ///<     A12 - DLL control for precharge power down
+      U16                                     : 3;      ///< A15:A13 - Reserved
+    } Mr0;
+    struct {
+      U16                     DllEnable       : 1;      ///<      A0 - DLL enable
+      U16                     DriverImpCtrl0  : 1;      ///<      A1 - Output driver impedance control bit 0
+      U16                     RttNom0         : 1;      ///<      A2 - Odt Rtt values bit 0
+      U16                     AdditiveLatency : 2;      ///<   A4:A3 - Additive latency
+      U16                     DriverImpCtrl   : 1;      ///<      A5 - Output driver impedance control bit 1
+      U16                     RttNom1         : 1;      ///<      A6 - Odt Rtt values bit 1
+      U16                     WriteLeveling   : 1;      ///<      A7 - Write leveling enable
+      U16                                     : 1;      ///<      A8 - Reserved
+      U16                     RttNom2         : 1;      ///<      A9 - Odt Rtt values bit 2
+      U16                                     : 1;      ///<     A10 - Reserved
+      U16                     TdqsEnable      : 1;      ///<     A11 - Termination data strobe
+      U16                     Qoff            : 1;      ///<     A12 - Output disable
+      U16                                     : 3;      ///< A15:A13 - Reserved
+    } Mr1;
+    struct {
+      U16                     Pasr            : 3;      ///<   A2:A0 - Partial array self refresh
+      U16                     CasWrLatency    : 3;      ///<   A5:A3 - CAS write latency
+      U16                     AutoSelfRefresh : 1;      ///<      A6 - Automatic self refresh
+      U16                     SelfRefreshTemp : 1;      ///<      A7 - Self refresh temperature range
+      U16                                     : 1;      ///<      A8 - Reserved
+      U16                     RttWrite        : 2;      ///<  A10:A9 - Dynamic ODT
+      U16                                     : 5;      ///< A15:A11 - Reserved
+    } Mr2;
+    struct {
+      U16                     MprAddress      : 2;      ///<   A1:A0 - Multi-purpose register address
+      U16                     MprControl      : 1;      ///<      A2 - Multi-purpose register control
+      U16                                     : 13;     ///<  A15:A3 - Reserved
+    } Mr3;
+  } b;
+#endif
+} RmtRankMrs;
+
+typedef struct {
+  U8                          RankEnabled;              ///< 0 = Rank disabled
+  U8                          RankMarginEnabled;        ///< 0 = Rank margin disabled
+  U8                          DqMarginEnabled;          ///< 0 = Dq margin disabled
+  RmtRankMargin               RankMargin;               ///< Rank margin data
+  RmtDqMargin                 DqMargin[MAX_DQ];         ///< Array of Dq margin data per rank
+  RmtRankTraining             RankTraining;             ///< Rank training settings
+  RmtRankMrs                  RankMRS;                  ///< Rank MRS settings
+} RmtRankList;
+
+typedef struct {
+  U8                          SpdValid[MAX_SPD_RMT / (CHAR_BITS * sizeof (U8))]; ///< Each valid bit maps to SPD byte
+  U8                          SpdData[MAX_SPD_RMT];     ///< Array of raw SPD data bytes
+} RmtSpd;
+
+typedef struct {
+  U8                          DimmEnabled;              ///< 0 = DIMM disabled
+  RmtRankList                 RankList[MAX_RANK_IN_DIMM]; ///< Array of ranks per DIMM
+  RmtSpd                      SpdBytes;                 ///< SPD data per DIMM
+} RmtDimmList;
+
+typedef struct {
+  U8                          ChannelEnabled;           ///< 0 = Channel disabled
+  U8                          NumDimmSlot;              ///< Number of slots per channel on the board
+  RmtDimmList                 DimmList[MAX_DIMMS_IN_CHANNEL]; ///< Array of DIMMs per channel
+} RmtChannelList;
+
+typedef struct {
+  U8                          ControllerEnabled;        ///< 0 = MC disabled
+  U16                         ControllerDeviceId;       ///< MC device Id
+  U8                          ControllerRevisionId;     ///< MC revision Id
+  U16                         MemoryFrequency;          ///< Memory frequency in units of MHz / 10
+                                                        ///< e.g. ddrFreq = 13333 for tCK = 1.5 ns
+  U16                         MemoryVoltage;            ///< Memory Vdd in units of mV
+                                                        ///< e.g. ddrVoltage = 1350 for Vdd = 1.35 V
+  U8                          PiStep;                   ///< Step unit = piStep * tCK / 2048
+                                                        ///< e.g. piStep = 16 for step = 11.7 ps (1/128 tCK)
+  U16                         RxVrefStep;               ///< Step unit = rxVrefStep * Vdd / 100
+                                                        ///< e.g. rxVrefStep = 520 for step = 7.02 mV
+  U16                         TxVrefStep;               ///< Step unit = txVrefStep * Vdd / 100
+  U16                         CaVrefStep;               ///< Step unit = caVrefStep * Vdd / 100
+  U8                          RecvenStep;               ///< Step unit = recvenStep * tCK / 2048
+  U8                          WrLevelStep;              ///< Step unit = wrLevelStep * tCK / 2048
+  RmtChannelList              ChannelList[MAX_CHANNEL]; ///< Array of channels per memory controller
+} RmtControllerList;
+
+typedef struct {
+  union {
+    U32                       l;                        ///< MRC version: Major.Minor.Revision.Build
+    struct {
+      U8                      Build;                    ///< MRC version: Build
+      U8                      Revision;                 ///< MRC version: Revision
+      U8                      Minor;                    ///< MRC version: Minor
+      U8                      Major;                    ///< MRC version: Major
+    } c;
+  }                           RefCodeRevision;          ///< Major.Minor.Revision.Build
+  U8                          MaxController;            ///< Max controllers per system, e.g. 1
+  U8                          MaxChannel;               ///< Max channels per memory controller, e.g. 2
+  U8                          MaxDimm;                  ///< Max DIMM per channel, e.g. 2
+  U8                          MaxRankDimm;              ///< Max ranks per DIMM, e.g. 2
+  U8                          MaxStrobe;                ///< Number of Dqs used by the rank, e.g. 18
+  U8                          MaxDq;                    ///< Number of Dq bits used by the rank, e.g. 72
+  U32                         MarginLoopCount;          ///< Units of cache line
+  RmtControllerList           ControllerList[MAX_CONTROLLERS]; ///< Array of memory controllers per system
+} RmtSystem;
+
+typedef struct RmtStruct {
+  RmtHeader                   RmtHeader;
+  RmtSystem                   RmtSystem;
+} RmtData;
+
+#pragma pack (pop)
+
+#endif //_MrcRmtData_h_
diff --git a/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcSpdData.h b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcSpdData.h
new file mode 100644
index 0000000..a2b68d8
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcSpdData.h
@@ -0,0 +1,671 @@
+/** @file
+  SPD data format header file.
+
+@copyright
+  Copyright (c) 2010 - 2012 Intel Corporation. All rights reserved.
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement.
+**/
+
+#ifndef _MrcSpdData_h_
+#define _MrcSpdData_h_
+#pragma pack (push, 1)
+
+#include "MrcTypes.h"
+
+#define MAX_XMP_PROFILES  (2)
+#define SPD3_MANUF_SIZE   (SPD3_MANUF_END - SPD3_MANUF_START + 1) ///< The size of the SPD manufacturing data.
+typedef union {
+  struct {
+    U8  BytesUsed                           :  4; ///< Bits 3:0
+    U8  BytesTotal                          :  3; ///< Bits 6:4
+    U8  CrcCoverage                         :  1; ///< Bits 7:7
+  } Bits;
+  U8  Data;
+} SPD_DEVICE_DESCRIPTION_STRUCT;
+
+typedef union {
+  struct {
+    U8  Minor                               :  4; ///< Bits 3:0
+    U8  Major                               :  4; ///< Bits 7:4
+  } Bits;
+  U8  Data;
+} SPD_REVISION_STRUCT;
+
+typedef union {
+  struct {
+    U8  Type                                :  8; ///< Bits 7:0
+  } Bits;
+  U8  Data;
+} SPD_DRAM_DEVICE_TYPE_STRUCT;
+
+typedef union {
+  struct {
+    U8  ModuleType                          :  4; ///< Bits 3:0
+    U8                                      :  4; ///< Bits 7:4
+  } Bits;
+  U8  Data;
+} SPD_MODULE_TYPE_STRUCT;
+
+typedef union {
+  struct {
+    U8  Density                             :  4; ///< Bits 3:0
+    U8  BankAddress                         :  3; ///< Bits 6:4
+    U8                                      :  1; ///< Bits 7:7
+  } Bits;
+  U8  Data;
+} SPD_SDRAM_DENSITY_BANKS_STRUCT;
+
+typedef union {
+  struct {
+    U8  ColumnAddress                       :  3; ///< Bits 2:0
+    U8  RowAddress                          :  3; ///< Bits 5:3
+    U8                                      :  2; ///< Bits 7:6
+  } Bits;
+  U8  Data;
+} SPD_SDRAM_ADDRESSING_STRUCT;
+
+typedef union {
+  struct {
+    U8  OperationAt1_50                     :  1; ///< Bits 0:0
+    U8  OperationAt1_35                     :  1; ///< Bits 1:1
+    U8  OperationAt1_25                     :  1; ///< Bits 2:2
+    U8                                      :  5; ///< Bits 7:3
+  } Bits;
+  U8  Data;
+} SPD_MODULE_NOMINAL_VOLTAGE_STRUCT;
+
+typedef union {
+  struct {
+    U8  SdramDeviceWidth                    :  3; ///< Bits 2:0
+    U8  RankCount                           :  3; ///< Bits 5:3
+    U8                                      :  2; ///< Bits 7:6
+  } Bits;
+  U8  Data;
+} SPD_MODULE_ORGANIZATION_STRUCT;
+
+typedef union {
+  struct {
+    U8  PrimaryBusWidth                     :  3; ///< Bits 2:0
+    U8  BusWidthExtension                   :  2; ///< Bits 4:3
+    U8                                      :  3; ///< Bits 7:5
+  } Bits;
+  U8  Data;
+} SPD_MODULE_MEMORY_BUS_WIDTH_STRUCT;
+
+typedef union {
+  struct {
+    U8  Divisor                             :  4; ///< Bits 3:0
+    U8  Dividend                            :  4; ///< Bits 7:4
+  } Bits;
+  U8  Data;
+} SPD_FINE_TIMEBASE_STRUCT;
+
+typedef union {
+  struct {
+    U8  Dividend                            :  8; ///< Bits 7:0
+  } Bits;
+  U8  Data;
+} SPD_MEDIUM_TIMEBASE_DIVIDEND_STRUCT;
+
+typedef union {
+  struct {
+    U8  Divisor                             :  8; ///< Bits 7:0
+  } Bits;
+  U8  Data;
+} SPD_MEDIUM_TIMEBASE_DIVISOR_STRUCT;
+
+typedef struct {
+  SPD_MEDIUM_TIMEBASE_DIVIDEND_STRUCT Dividend; ///< Medium Timebase (MTB) Dividend
+  SPD_MEDIUM_TIMEBASE_DIVISOR_STRUCT  Divisor;  ///< Medium Timebase (MTB) Divisor
+} SPD_MEDIUM_TIMEBASE;
+
+typedef union {
+  struct {
+    U8  tCKmin                              :  8; ///< Bits 7:0
+  } Bits;
+  U8  Data;
+} SPD_TCK_MIN_MTB_STRUCT;
+
+typedef union {
+  struct {
+    U16 CL4                                 :  1; ///< Bits 0:0
+    U16 CL5                                 :  1; ///< Bits 1:1
+    U16 CL6                                 :  1; ///< Bits 2:2
+    U16 CL7                                 :  1; ///< Bits 3:3
+    U16 CL8                                 :  1; ///< Bits 4:4
+    U16 CL9                                 :  1; ///< Bits 5:5
+    U16 CL10                                :  1; ///< Bits 6:6
+    U16 CL11                                :  1; ///< Bits 7:7
+    U16 CL12                                :  1; ///< Bits 8:8
+    U16 CL13                                :  1; ///< Bits 9:9
+    U16 CL14                                :  1; ///< Bits 10:10
+    U16 CL15                                :  1; ///< Bits 11:11
+    U16 CL16                                :  1; ///< Bits 12:12
+    U16 CL17                                :  1; ///< Bits 13:13
+    U16 CL18                                :  1; ///< Bits 14:14
+    U16                                     :  1; ///< Bits 15:15
+  } Bits;
+  U16 Data;
+  U8  Data8;
+} SPD_CAS_LATENCIES_SUPPORTED_STRUCT;
+
+typedef union {
+  struct {
+    U8  tAAmin                              :  8; ///< Bits 7:0
+  } Bits;
+  U8  Data;
+} SPD_TAA_MIN_MTB_STRUCT;
+
+typedef union {
+  struct {
+    U8  tWRmin                              :  8; ///< Bits 7:0
+  } Bits;
+  U8  Data;
+} SPD_TWR_MIN_MTB_STRUCT;
+
+typedef union {
+  struct {
+    U8  tRCDmin                             :  8; ///< Bits 7:0
+  } Bits;
+  U8  Data;
+} SPD_TRCD_MIN_MTB_STRUCT;
+
+typedef union {
+  struct {
+    U8  tRRDmin                             :  8; ///< Bits 7:0
+  } Bits;
+  U8  Data;
+} SPD_TRRD_MIN_MTB_STRUCT;
+
+typedef union {
+  struct {
+    U8  tRPmin                              :  8; ///< Bits 7:0
+  } Bits;
+  U8  Data;
+} SPD_TRP_MIN_MTB_STRUCT;
+
+typedef union {
+  struct {
+    U8  tRPab                               :  8; ///< Bits 7:0
+  } Bits;
+  U8  Data;
+} SPD_TRP_AB_MTB_STRUCT;
+
+typedef union {
+  struct {
+    S8  tRPabFine                           :  8; ///< Bits 7:0
+  } Bits;
+  S8  Data;
+} SPD_TRP_AB_FTB_STRUCT;
+
+typedef union {
+  struct {
+    U8  tRASminUpper                        :  4; ///< Bits 3:0
+    U8  tRCminUpper                         :  4; ///< Bits 7:4
+  } Bits;
+  U8  Data;
+} SPD_TRAS_TRC_MIN_MTB_STRUCT;
+
+typedef union {
+  struct {
+    U8  tRASmin                             :  8; ///< Bits 7:0
+  } Bits;
+  U8  Data;
+} SPD_TRAS_MIN_MTB_STRUCT;
+
+typedef union {
+  struct {
+    U8  tRCmin                              :  8; ///< Bits 7:0
+  } Bits;
+  U8  Data;
+} SPD_TRC_MIN_MTB_STRUCT;
+
+typedef union {
+  struct {
+    U16 tRFCmin                             :  16; ///< Bits 15:0
+  } Bits;
+  U16 Data;
+  U8  Data8;
+} SPD_TRFC_MIN_MTB_STRUCT;
+
+typedef union {
+  struct {
+    U8  tWTRmin                             :  8; ///< Bits 7:0
+  } Bits;
+  U8  Data;
+} SPD_TWTR_MIN_MTB_STRUCT;
+
+typedef union {
+  struct {
+    U8  tRTPmin                             :  8; ///< Bits 7:0
+  } Bits;
+  U8  Data;
+} SPD_TRTP_MIN_MTB_STRUCT;
+
+typedef union {
+  struct {
+    U8  tFAWminUpper                        :  4; ///< Bits 3:0
+    U8                                      :  4; ///< Bits 7:4
+  } Bits;
+  U8  Data;
+} SPD_TFAW_MIN_MTB_UPPER_STRUCT;
+
+typedef union {
+  struct {
+    U8  tFAWmin                             :  8; ///< Bits 7:0
+  } Bits;
+  U8  Data;
+} SPD_TFAW_MIN_MTB_STRUCT;
+
+typedef union {
+  struct {
+    U8  tCWLmin                             :  8; ///< Bits 7:0
+  } Bits;
+  U8  Data;
+} SPD_TCWL_MIN_MTB_STRUCT;
+
+typedef union {
+  struct {
+    U8  NMode                               :  8; ///< Bits 7:0
+  } Bits;
+  U8  Data;
+} SPD_SYSTEM_COMMAND_RATE_STRUCT;
+
+typedef union {
+  struct {
+    U16 tREFImin                            :  16; ///< Bits 15:0
+  } Bits;
+  U16 Data;
+  U8  Data8;
+} SPD_TREFI_MIN_MTB_STRUCT;
+
+typedef union {
+  struct {
+    U8  RZQ6                                :  1; ///< Bits 0:0
+    U8  RZQ7                                :  1; ///< Bits 1:1
+    U8                                      :  5; ///< Bits 6:2
+    U8  DllOff                              :  1; ///< Bits 7:7
+  } Bits;
+  U8  Data;
+} SPD_SDRAM_OPTIONAL_FEATURES_STRUCT;
+
+typedef union {
+  struct {
+    U8  ExtendedTemperatureRange            :  1; ///< Bits 0:0
+    U8  ExtendedTemperatureRefreshRate      :  1; ///< Bits 1:1
+    U8  AutoSelfRefresh                     :  1; ///< Bits 2:2
+    U8  OnDieThermalSensor                  :  1; ///< Bits 3:3
+    U8                                      :  3; ///< Bits 6:4
+    U8  PartialArraySelfRefresh             :  1; ///< Bits 7:7
+  } Bits;
+  U8  Data;
+} SPD_SDRAM_THERMAL_REFRESH_STRUCT;
+
+typedef union {
+  struct {
+    U8  ThermalSensorAccuracy               :  7; ///< Bits 6:0
+    U8  ThermalSensorPresence               :  1; ///< Bits 7:7
+  } Bits;
+  U8  Data;
+} SPD_MODULE_THERMAL_SENSOR_STRUCT;
+
+typedef union {
+  struct {
+    U8  NonStandardDeviceDescription        :  7; ///< Bits 6:0
+    U8  SdramDeviceType                     :  1; ///< Bits 7:7
+  } Bits;
+  U8  Data;
+} SPD_SDRAM_DEVICE_TYPE_STRUCT;
+
+typedef union {
+  struct {
+    U8                                      :  8; ///< Bits 7:0
+  } Bits;
+  U8  Data;
+} SPD_AUTO_SELF_REFRESH_PERF_STRUCT;
+
+typedef union {
+  struct {
+    S8  tCKminFine                          :  8; ///< Bits 7:0
+  } Bits;
+  S8  Data;
+} SPD_TCK_MIN_FTB_STRUCT;
+
+typedef union {
+  struct {
+    S8  tAAminFine                          :  8; ///< Bits 7:0
+  } Bits;
+  S8  Data;
+} SPD_TAA_MIN_FTB_STRUCT;
+
+typedef union {
+  struct {
+    S8  tRCDminFine                         :  8; ///< Bits 7:0
+  } Bits;
+  S8  Data;
+} SPD_TRCD_MIN_FTB_STRUCT;
+
+typedef union {
+  struct {
+    S8  tRPminFine                          :  8; ///< Bits 7:0
+  } Bits;
+  S8  Data;
+} SPD_TRP_MIN_FTB_STRUCT;
+
+typedef union {
+  struct {
+    S8  tRCminFine                          :  8; ///< Bits 7:0
+  } Bits;
+  S8  Data;
+} SPD_TRC_MIN_FTB_STRUCT;
+
+typedef union {
+  struct {
+    S8  tRRDminFine                         :  8; ///< Bits 7:0
+  } Bits;
+  S8  Data;
+} SPD_TRRD_MIN_FTB_STRUCT;
+
+typedef union {
+  struct {
+    U8  Height                              :  5; ///< Bits 4:0
+    U8  RawCardExtension                    :  3; ///< Bits 7:5
+  } Bits;
+  U8  Data;
+} SPD_UNBUF_MODULE_NOMINAL_HEIGHT;
+
+typedef union {
+  struct {
+    U8  FrontThickness                      :  4; ///< Bits 3:0
+    U8  BackThickness                       :  4; ///< Bits 7:4
+  } Bits;
+  U8  Data;
+} SPD_UNBUF_MODULE_NOMINAL_THICKNESS;
+
+typedef union {
+  struct {
+    U8  Card                                :  5; ///< Bits 4:0
+    U8  Revision                            :  2; ///< Bits 6:5
+    U8  Extension                           :  1; ///< Bits 7:7
+  } Bits;
+  U8  Data;
+} SPD_UNBUF_REFERENCE_RAW_CARD;
+
+typedef union {
+  struct {
+    U8  MappingRank1                        :  1; ///< Bits 0:0
+    U8                                      :  7; ///< Bits 7:1
+  } Bits;
+  U8  Data;
+} SPD_UNBUF_ADDRESS_MAPPING;
+
+typedef union {
+  struct {
+    U8  Height                              :  5; ///< Bits 4:0
+    U8                                      :  3; ///< Bits 7:5
+  } Bits;
+  U8  Data;
+} SPD_RDIMM_MODULE_NOMINAL_HEIGHT;
+
+typedef union {
+  struct {
+    U8  FrontThickness                      :  4; ///< Bits 3:0
+    U8  BackThickness                       :  4; ///< Bits 7:4
+  } Bits;
+  U8  Data;
+} SPD_RDIMM_MODULE_NOMINAL_THICKNESS;
+
+typedef union {
+  struct {
+    U8  Card                                :  5; ///< Bits 4:0
+    U8  Revision                            :  2; ///< Bits 6:5
+    U8  Extension                           :  1; ///< Bits 7:7
+  } Bits;
+  U8  Data;
+} SPD_RDIMM_REFERENCE_RAW_CARD;
+
+typedef union {
+  struct {
+    U8  RegisterCount                       :  2; ///< Bits 1:0
+    U8  DramRowCount                        :  2; ///< Bits 3:2
+    U8                                      :  4; ///< Bits 7:4
+  } Bits;
+  U8  Data;
+} SPD_RDIMM_MODULE_ATTRIBUTES;
+
+typedef union {
+  struct {
+    U16 ContinuationCount                   :  7; ///< Bits 6:0
+    U16 ContinuationParity                  :  1; ///< Bits 7:7
+    U16 LastNonZeroByte                     :  8; ///< Bits 15:8
+  } Bits;
+  U16 Data;
+  U8  Data8;
+} SPD_MANUFACTURER_ID_CODE;
+
+typedef struct {
+  U8  Year;                                 ///< Year represented in BCD (00h = 2000)
+  U8  Week;                                 ///< Year represented in BCD (47h = week 47)
+} SPD_MANUFACTURING_DATE;
+
+typedef union {
+  U32 Data;
+  U16 SerialNumber16[2];
+  U8  SerialNumber8[4];
+} SPD_MANUFACTURER_SERIAL_NUMBER;
+
+typedef union {
+  U16 Crc[1];
+  U8  Data8[2];
+} SPD_CYCLIC_REDUNDANCY_CODE;
+
+typedef union {
+  struct {
+    U8  ProfileEnable1                :  1;                     ///< Bits 0:0
+    U8  ProfileEnable2                :  1;                     ///< Bits 1:1
+    U8  ProfileConfig1                :  2;                     ///< Bits 3:2
+    U8  ProfileConfig2                :  2;                     ///< Bits 5:4
+    U8                                :  2;                     ///< Bits 7:6
+  } Bits;
+  U8  Data;
+} SPD_XMP_ORG_CONFIG;
+
+typedef struct {
+  U16                                 XmpId;                    ///< 176-177 XMP Identification String
+  SPD_XMP_ORG_CONFIG                  XmpOrgConf;               ///< 178 XMP Organization & Configuration
+  SPD_REVISION_STRUCT                 XmpRevision;              ///< 179 XMP Revision
+  SPD_MEDIUM_TIMEBASE                 MediumTimeBase[MAX_XMP_PROFILES]; ///< 180-183 Medium Timebase (MTB)
+  SPD_FINE_TIMEBASE_STRUCT            FineTimeBase;             ///< 184 Fine Timebase (FTB) Dividend / Divisor
+} SPD_EXTREME_MEMORY_PROFILE_HEADER;
+
+typedef union {
+  struct {
+    U8  Decimal : 5;
+    U8  Integer : 2;
+    U8          : 1;
+  } Bits;
+  U8 Data;
+} SPD_VDD_VOLTAGE_LEVEL_STRUCT;
+
+typedef struct {
+  SPD_VDD_VOLTAGE_LEVEL_STRUCT        Vdd;                      ///< 185, 220 XMP Module VDD Voltage Level
+  SPD_TCK_MIN_MTB_STRUCT              tCKmin;                   ///< 186, 221 XMP SDRAM Minimum Cycle Time (tCKmin)
+  SPD_TAA_MIN_MTB_STRUCT              tAAmin;                   ///< 187, 222 XMP Minimum CAS Latency Time (tAAmin)
+  SPD_CAS_LATENCIES_SUPPORTED_STRUCT  CasLatencies;             ///< 188-189, 223-224 XMP CAS Latencies Supported, Least Significant Byte
+  SPD_TCWL_MIN_MTB_STRUCT             tCWLmin;                  ///< 190, 225 XMP Minimum CAS Write Latency Time (tCWLmin)
+  SPD_TRP_MIN_MTB_STRUCT              tRPmin;                   ///< 191, 226 XMP Minimum Row Precharge Delay Time (tRPmin)
+  SPD_TRCD_MIN_MTB_STRUCT             tRCDmin;                  ///< 192, 227 XMP Minimum RAS# to CAS# Delay Time (tRCDmin)
+  SPD_TWR_MIN_MTB_STRUCT              tWRmin;                   ///< 193, 228 XMP Minimum Write Recovery Time (tWRmin)
+  SPD_TRAS_TRC_MIN_MTB_STRUCT         tRASMintRCMinUpper;       ///< 194, 229 XMP Upper Nibbles for tRAS and tRC
+  SPD_TRAS_MIN_MTB_STRUCT             tRASmin;                  ///< 195, 230 XMP Minimum Active to Precharge Delay Time (tRASmin), Least Significant Byte
+  SPD_TRC_MIN_MTB_STRUCT              tRCmin;                   ///< 196, 231 XMP Minimum Active to Active/Refresh Delay Time (tRCmin), Least Significant Byte
+  SPD_TREFI_MIN_MTB_STRUCT            tREFImin;                 ///< 197-198, 232-233 XMP Maximum tREFI Time (Average Periodic Refresh Interval), Least Significant Byte
+  SPD_TRFC_MIN_MTB_STRUCT             tRFCmin;                  ///< 199-200, 234-235 XMP Minimum Refresh Recovery Delay Time (tRFCmin), Least Significant Byte
+  SPD_TRTP_MIN_MTB_STRUCT             tRTPmin;                  ///< 201, 236 XMP Minimum Internal Read to Precharge Command Delay Time (tRTPmin)
+  SPD_TRRD_MIN_MTB_STRUCT             tRRDmin;                  ///< 202, 237 XMP Minimum Row Active to Row Active Delay Time (tRRDmin)
+  SPD_TFAW_MIN_MTB_UPPER_STRUCT       tFAWMinUpper;             ///< 203, 238 XMP Upper Nibble for tFAW
+  SPD_TFAW_MIN_MTB_STRUCT             tFAWmin;                  ///< 204, 239 XMP Minimum Four Activate Window Delay Time (tFAWmin)
+  SPD_TWTR_MIN_MTB_STRUCT             tWTRmin;                  ///< 205, 240 XMP Minimum Internal Write to Read Command Delay Time (tWTRmin)
+  U8                                  Reserved1[207 - 206 + 1]; ///< 206-207, 241-242 XMP Reserved
+  SPD_SYSTEM_COMMAND_RATE_STRUCT      SystemCmdRate;            ///< 208, 243 XMP System ADD/CMD Rate (1N or 2N mode)
+  SPD_AUTO_SELF_REFRESH_PERF_STRUCT   AsrPerf;                  ///< 209, 244 XMP SDRAM Auto Self Refresh Performance (Sub 1x Refresh and IDD6 impact)
+  U8                                  VoltageLevel;             ///< 210, 245 XMP Memory Controller Voltage Level
+  SPD_TCK_MIN_FTB_STRUCT              tCKminFine;               ///< 211, 246 XMP Fine Offset for SDRAM Minimum Cycle Time (tCKmin)
+  SPD_TAA_MIN_FTB_STRUCT              tAAminFine;               ///< 212, 247 XMP Fine Offset for Minimum CAS Latency Time (tAAmin)
+  SPD_TRP_MIN_FTB_STRUCT              tRPminFine;               ///< 213, 248 XMP Minimum Row Precharge Delay Time (tRPmin)
+  SPD_TRCD_MIN_FTB_STRUCT             tRCDminFine;              ///< 214, 249 XMP Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin)
+  SPD_TRC_MIN_FTB_STRUCT              tRCminFine;               ///< 215, 250 XMP Fine Offset for Minimum Active to Active/Refresh Delay Time (tRCmin)
+  U8                                  Reserved2[218 - 216 + 1]; ///< 216-218, 251-253 XMP Reserved
+  U8                                  VendorPersonality;        ///< 219, 254 XMP Vendor Personality
+} SPD_EXTREME_MEMORY_PROFILE_DATA;
+
+typedef struct {
+  SPD_EXTREME_MEMORY_PROFILE_HEADER   Header;                   ///< 176-184 XMP header
+  SPD_EXTREME_MEMORY_PROFILE_DATA     Data[MAX_XMP_PROFILES];   ///< 185-254 XMP profiles
+} SPD_EXTREME_MEMORY_PROFILE;
+
+typedef struct {
+  SPD_DEVICE_DESCRIPTION_STRUCT       Description;              ///< 0   Number of Serial PD Bytes Written / SPD Device Size / CRC Coverage 1, 2
+  SPD_REVISION_STRUCT                 Revision;                 ///< 1   SPD Revision
+  SPD_DRAM_DEVICE_TYPE_STRUCT         DramDeviceType;           ///< 2   DRAM Device Type
+  SPD_MODULE_TYPE_STRUCT              ModuleType;               ///< 3   Module Type
+  SPD_SDRAM_DENSITY_BANKS_STRUCT      SdramDensityAndBanks;     ///< 4   SDRAM Density and Banks
+  SPD_SDRAM_ADDRESSING_STRUCT         SdramAddressing;          ///< 5   SDRAM Addressing
+  SPD_MODULE_NOMINAL_VOLTAGE_STRUCT   ModuleNominalVoltage;     ///< 6   Module Nominal Voltage, VDD
+  SPD_MODULE_ORGANIZATION_STRUCT      ModuleOrganization;       ///< 7   Module Organization
+  SPD_MODULE_MEMORY_BUS_WIDTH_STRUCT  ModuleMemoryBusWidth;     ///< 8   Module Memory Bus Width
+  SPD_FINE_TIMEBASE_STRUCT            FineTimebase;             ///< 9   Fine Timebase (FTB) Dividend / Divisor
+  SPD_MEDIUM_TIMEBASE                 MediumTimebase;           ///< 10-11 Medium Timebase (MTB) Dividend
+  SPD_TCK_MIN_MTB_STRUCT              tCKmin;                   ///< 12  SDRAM Minimum Cycle Time (tCKmin)
+  U8                                  Reserved1;                ///< 13  Reserved
+  SPD_CAS_LATENCIES_SUPPORTED_STRUCT  CasLatencies;             ///< 14-15 CAS Latencies Supported
+  SPD_TAA_MIN_MTB_STRUCT              tAAmin;                   ///< 16  Minimum CAS Latency Time (tAAmin)
+  SPD_TWR_MIN_MTB_STRUCT              tWRmin;                   ///< 17  Minimum Write Recovery Time (tWRmin)
+  SPD_TRCD_MIN_MTB_STRUCT             tRCDmin;                  ///< 18  Minimum RAS# to CAS# Delay Time (tRCDmin)
+  SPD_TRRD_MIN_MTB_STRUCT             tRRDmin;                  ///< 19  Minimum Row Active to Row Active Delay Time (tRRDmin)
+  SPD_TRP_MIN_MTB_STRUCT              tRPmin;                   ///< 20  Minimum Row Precharge Delay Time (tRPmin)
+  SPD_TRAS_TRC_MIN_MTB_STRUCT         tRASMintRCMinUpper;       ///< 21  Upper Nibbles for tRAS and tRC
+  SPD_TRAS_MIN_MTB_STRUCT             tRASmin;                  ///< 22  Minimum Active to Precharge Delay Time (tRASmin), Least Significant Byte
+  SPD_TRC_MIN_MTB_STRUCT              tRCmin;                   ///< 23  Minimum Active to Active/Refresh Delay Time (tRCmin), Least Significant Byte
+  SPD_TRFC_MIN_MTB_STRUCT             tRFCmin;                  ///< 24-25  Minimum Refresh Recovery Delay Time (tRFCmin)
+  SPD_TWTR_MIN_MTB_STRUCT             tWTRmin;                  ///< 26  Minimum Internal Write to Read Command Delay Time (tWTRmin)
+  SPD_TRTP_MIN_MTB_STRUCT             tRTPmin;                  ///< 27  Minimum Internal Read to Precharge Command Delay Time (tRTPmin)
+  SPD_TFAW_MIN_MTB_UPPER_STRUCT       tFAWMinUpper;             ///< 28  Upper Nibble for tFAW
+  SPD_TFAW_MIN_MTB_STRUCT             tFAWmin;                  ///< 29  Minimum Four Activate Window Delay Time (tFAWmin)
+  SPD_SDRAM_OPTIONAL_FEATURES_STRUCT  SdramOptionalFeatures;    ///< 30  SDRAM Optional Features
+  SPD_SDRAM_THERMAL_REFRESH_STRUCT    ThermalAndRefreshOptions; ///< 31  SDRAMThermalAndRefreshOptions
+  SPD_MODULE_THERMAL_SENSOR_STRUCT    ModuleThermalSensor;      ///< 32  Module Thermal Sensor
+  SPD_SDRAM_DEVICE_TYPE_STRUCT        SdramDeviceType;          ///< 33  SDRAM Device Type
+  SPD_TCK_MIN_FTB_STRUCT              tCKminFine;               ///< 34  Fine Offset for SDRAM Minimum Cycle Time (tCKmin)
+  SPD_TAA_MIN_FTB_STRUCT              tAAminFine;               ///< 35  Fine Offset for Minimum CAS Latency Time (tAAmin)
+  SPD_TRCD_MIN_FTB_STRUCT             tRCDminFine;              ///< 36  Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin)
+  SPD_TRP_MIN_FTB_STRUCT              tRPminFine;               ///< 37  Minimum Row Precharge Delay Time (tRPmin)
+  SPD_TRC_MIN_FTB_STRUCT              tRCminFine;               ///< 38  Fine Offset for Minimum Active to Active/Refresh Delay Time (tRCmin)
+#if (SUPPORT_LPDDR3 == SUPPORT)
+  SPD_TRP_AB_MTB_STRUCT               tRPab;                    ///< 39  Minimum Row Precharge Delay Time for all banks (tRPab)
+  SPD_TRP_AB_FTB_STRUCT               tRPabFine;                ///< 40  Fine Offset for Minimum Row Precharge Delay Time for all banks (tRPab)
+  U8                                  Reserved2[59 - 41 + 1];   ///< 41 - 59 Reserved
+#else
+  U8                                  Reserved2[59 - 39 + 1];   ///< 39 - 59 Reserved
+#endif
+} SPD_GENERAL_SECTION;
+
+typedef struct {
+  SPD_UNBUF_MODULE_NOMINAL_HEIGHT     ModuleNominalHeight;      ///< 60 Module Nominal Height
+  SPD_UNBUF_MODULE_NOMINAL_THICKNESS  ModuleMaximumThickness;   ///< 61 Module Maximum Thickness
+  SPD_UNBUF_REFERENCE_RAW_CARD        ReferenceRawCardUsed;     ///< 62 Reference Raw Card Used
+  SPD_UNBUF_ADDRESS_MAPPING           AddressMappingEdgeConn;   ///< 63 Address Mapping from Edge Connector to DRAM
+  U8                                  Reserved[116 - 64 + 1];   ///< 64-116 Reserved
+} SPD_MODULE_UNBUFFERED;
+
+typedef struct {
+  SPD_RDIMM_MODULE_NOMINAL_HEIGHT     ModuleNominalHeight;      ///< 60 Module Nominal Height
+  SPD_RDIMM_MODULE_NOMINAL_THICKNESS  ModuleMaximumThickness;   ///< 61 Module Maximum Thickness
+  SPD_RDIMM_REFERENCE_RAW_CARD        ReferenceRawCardUsed;     ///< 62 Reference Raw Card Used
+  SPD_RDIMM_MODULE_ATTRIBUTES         DimmModuleAttributes;     ///< 63 DIMM Module Attributes
+  U8                                  Reserved[116 - 64 + 1];   ///< 64-116 Reserved
+} SPD_MODULE_REGISTERED;
+
+typedef union {
+  SPD_MODULE_UNBUFFERED               Unbuffered;
+  SPD_MODULE_REGISTERED               Registered;
+} SPD_MODULE_SPECIFIC;
+
+typedef struct {
+  U8                                  Location;                 ///< 119 Module Manufacturing Location
+} SPD_MANUFACTURING_LOCATION;
+
+typedef struct {
+  SPD_MANUFACTURER_ID_CODE            IdCode;                   ///< 117-118 Module Manufacturer ID Code
+  SPD_MANUFACTURING_LOCATION          Location;                 ///< 119 Module Manufacturing Location
+  SPD_MANUFACTURING_DATE              Date;                     ///< 120-121 Module Manufacturing Year, in BCD (range: 2000-2255)
+  SPD_MANUFACTURER_SERIAL_NUMBER      SerialNumber;             ///< 122-125 Module Serial Number
+} SPD_UNIQUE_MODULE_ID;
+
+typedef struct {
+  U8                          ModulePartNumber[145 - 128 + 1];        ///< 128-145 Module Part Number
+} SPD_MODULE_PART_NUMBER;
+
+typedef struct {
+  U8                          ModuleRevisionCode[147 - 146 + 1];      ///< 146-147 Module Revision Code
+} SPD_MODULE_REVISION_CODE;
+
+typedef struct {
+  U8                          ManufactureSpecificData[175 - 150 + 1]; ///< 150-175 Manufacturer's Specific Data
+} SPD_MANUFACTURE_SPECIFIC;
+
+///
+/// DDR3 Serial Presence Detect structure
+///
+typedef struct {
+  SPD_GENERAL_SECTION         General;                                ///< 0-59 General Section
+  SPD_MODULE_SPECIFIC         Module;                                 ///< 60-116 Module-Specific Section
+  SPD_UNIQUE_MODULE_ID        ModuleId;                               ///< 117-125 Unique Module ID
+  SPD_CYCLIC_REDUNDANCY_CODE  Crc;                                    ///< 126-127 Cyclical Redundancy Code (CRC)
+  SPD_MODULE_PART_NUMBER      ModulePartNumber;                       ///< 128-145 Module Part Number
+  SPD_MODULE_REVISION_CODE    ModuleRevisionCode;                     ///< 146-147 Module Revision Code
+  SPD_MANUFACTURER_ID_CODE    DramIdCode;                             ///< 148-149 Dram Manufacturer ID Code
+  SPD_MANUFACTURE_SPECIFIC    ManufactureSpecificData;                ///< 150-175 Manufacturer's Specific Data
+  SPD_EXTREME_MEMORY_PROFILE  Xmp;                                    ///< 176-254 Intel(r) Extreme Memory Profile support
+  U8                          Reserved;                               ///< 255 Reserved
+} MrcSpdDdr3;
+typedef union {
+  MrcSpdDdr3  Ddr3;
+} MrcSpd;
+
+typedef struct {
+  SPD_MODULE_TYPE_STRUCT              ModuleType;           ///< 3       Module Type
+  SPD_MODULE_MEMORY_BUS_WIDTH_STRUCT  ModuleMemoryBusWidth; ///< 8/14    Module Memory Bus Width
+} SMBIOS_SPD_SAVE;
+
+typedef struct {
+  SPD_UNIQUE_MODULE_ID                ModuleId;             ///< 117-125 Unique Module ID
+  SPD_CYCLIC_REDUNDANCY_CODE          Crc;                  ///< 126-127 Cyclical Redundancy Code (CRC)
+  SPD_MODULE_PART_NUMBER              ModulePartNumber;     ///< 128-145 Module Part Number
+  SPD_MODULE_REVISION_CODE            ModuleRevisionCode;   ///< 146-147 Module Revision Code
+} MANUFACTURING_SPD_SAVE_DDR3;
+
+typedef union {
+  MANUFACTURING_SPD_SAVE_DDR3 Ddr3Data;
+} MANUFACTURING_SPD_SAVE;
+
+typedef struct {
+  SMBIOS_SPD_SAVE         SmbiosData;
+  MANUFACTURING_SPD_SAVE  ManufacturingData;
+} MrcSpdSave;
+
+#pragma pack (pop)
+#endif // _MrcSpdData_h_
diff --git a/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcTypes.h b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcTypes.h
new file mode 100644
index 0000000..e445942
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcTypes.h
@@ -0,0 +1,175 @@
+/** @file
+
+  Include the the general MRC types
+
+@copyright
+  Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement
+**/
+#ifndef _MRC_TYPES_H
+#define _MRC_TYPES_H
+
+//
+// Data Types
+//
+typedef unsigned long long  U64;
+typedef unsigned long       U32;
+typedef unsigned short      U16;
+typedef unsigned char       U8;
+typedef signed long long    S64;
+typedef signed long         S32;
+typedef signed short        S16;
+typedef signed char         S8;
+typedef unsigned char       MrcBool;
+
+#ifndef BOOL
+#undef FALSE
+#undef TRUE
+typedef enum {
+  FALSE = (0 == 1),
+  TRUE  = (1 == 1)
+} BOOL;
+#endif
+
+#ifndef NULL
+#define NULL  ((void *) 0)
+#endif
+
+#ifndef IN
+#define IN
+#endif
+
+#ifndef OPTIONAL
+#define OPTIONAL
+#endif
+
+#ifndef OUT
+#define OUT
+#endif
+
+#define UNSUPPORT 0
+#define SUPPORT   1
+
+typedef enum {
+  mrcSuccess,
+  mrcFail,
+  mrcWrongInputParameter,
+  mrcCasError,
+  mrcTimingError,
+  mrcSenseAmpErr,
+  mrcReadMPRErr,
+  mrcReadLevelingError,
+  mrcWriteLevelingError,
+  mrcDataTimeCentering1DErr,
+  mrcWriteVoltage2DError,
+  mrcReadVoltage2DError,
+  mrcWrError,
+  mrcDimmNotSupport,
+  mrcChannelNotSupport,
+  mrcPiSettingError,
+  mrcDqsPiSettingError,
+  mrcDeviceBusy,
+  mrcFrequencyChange,
+  mrcReutSequenceError,
+  mrcCrcError,
+  mrcFrequencyError,
+  mrcDimmNotExist,
+  mrcColdBootRequired,
+  mrcRoundTripLatencyError,
+  mrcMixedDimmSystem,
+  mrcAliasDetected,
+  mrcRetrain
+} MrcStatus;
+
+//
+// general  macros
+//
+#ifndef MIN
+#define MIN(a, b) (((a) < (b)) ? (a) : (b))
+#endif
+
+#ifndef MAX
+#define MAX(a, b) (((a) > (b)) ? (a) : (b))
+#endif
+
+#ifndef ABS
+#define ABS(x)  (((x) < 0) ? (-(x)) : (x))
+#endif
+//
+//  use for ignore parames
+//
+// #define MRC_IGNORE_PARAM(x) ((x) = (x))
+//
+#if _MSC_EXTENSIONS
+//
+// Disable warning that make it impossible to compile at /W4
+// This only works for Microsoft* tools
+//
+//
+// Disabling bitfield type checking warnings.
+//
+#pragma warning (disable : 4214)
+//
+// Unreferenced formal parameter - We are object oriented, so we pass parameters even
+//  if we don't need them.
+//
+#pragma warning (disable : 4100)
+//
+// ASSERT(FALSE) or while (TRUE) are legal constructs so supress this warning
+//
+#pragma warning(disable : 4127)
+
+#endif // _MSC_EXTENSIONS
+#define MRC_BIT0  0x00000001
+#define MRC_BIT1  0x00000002
+#define MRC_BIT2  0x00000004
+#define MRC_BIT3  0x00000008
+#define MRC_BIT4  0x00000010
+#define MRC_BIT5  0x00000020
+#define MRC_BIT6  0x00000040
+#define MRC_BIT7  0x00000080
+#define MRC_BIT8  0x00000100
+#define MRC_BIT9  0x00000200
+#define MRC_BIT10 0x00000400
+#define MRC_BIT11 0x00000800
+#define MRC_BIT12 0x00001000
+#define MRC_BIT13 0x00002000
+#define MRC_BIT14 0x00004000
+#define MRC_BIT15 0x00008000
+#define MRC_BIT16 0x00010000
+#define MRC_BIT17 0x00020000
+#define MRC_BIT18 0x00040000
+#define MRC_BIT19 0x00080000
+#define MRC_BIT20 0x00100000
+#define MRC_BIT21 0x00200000
+#define MRC_BIT22 0x00400000
+#define MRC_BIT23 0x00800000
+#define MRC_BIT24 0x01000000
+#define MRC_BIT25 0x02000000
+#define MRC_BIT26 0x04000000
+#define MRC_BIT27 0x08000000
+#define MRC_BIT28 0x10000000
+#define MRC_BIT29 0x20000000
+#define MRC_BIT30 0x40000000
+#define MRC_BIT31 0x80000000
+
+#define MRC_DEADLOOP() { volatile int __iii; __iii = 1; while (__iii); }
+
+#ifndef ASM
+#define ASM __asm
+#endif
+
+#endif
diff --git a/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcVersion.h b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcVersion.h
new file mode 100644
index 0000000..fccbf94
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcVersion.h
@@ -0,0 +1,24 @@
+/** @file
+  Include the MRC version
+
+@copyright
+  Copyright (c) 1999 - 2014 Intel Corporation. All rights reserved.
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement
+**/
+
+///  Major minor Rev  build
+///  ----- ----- ---- -----
+      1,    9,   0,   0
diff --git a/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/McConfiguration/MrcAddressDecodeConfiguration.c b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/McConfiguration/MrcAddressDecodeConfiguration.c
new file mode 100644
index 0000000..e4d17ee
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/McConfiguration/MrcAddressDecodeConfiguration.c
@@ -0,0 +1,368 @@
+/** @file
+  This module configures the memory controller address decoder.
+@copyright
+  Copyright (c) 1999 - 2013 Intel Corporation. All rights reserved.
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement.
+
+**/
+#include "MrcAddressDecodeConfiguration.h"
+
+#if (MAX_CHANNEL > 2)
+#error This module only supports a maximum of 2 channels.
+#endif
+#if (MAX_DIMMS_IN_CHANNEL > 2)
+#error This module only supports a maximum of 2 DIMMs per channel.
+#endif
+
+/**
+@brief
+  This function configures the zone configuration registers MAD-CR and MAD-ZR-CR.
+
+  @param[in, out] MrcData - Include all MRC global data.
+
+  @retval Nothing.
+**/
+void
+ZoneConfiguration (
+  IN OUT MrcParameters *const MrcData
+)
+{
+  MrcInput                              *Inputs;
+  MrcOutput                             *Outputs;
+  MrcDebug                              *Debug;
+  MrcControllerOut                      *ControllerOut;
+  MrcChannelOut                         *ChannelOut;
+  MrcChannelOut                         *ChannelOut0;
+  MrcChannelOut                         *ChannelOut1;
+  MCDECS_CR_MAD_CHNL_MCMAIN_STRUCT      MadChnl;
+  MCDECS_CR_MAD_ZR_MCMAIN_STRUCT        MadZr;
+  MCDECS_CR_CHANNEL_HASH_MCMAIN_STRUCT  ChannelHash;
+  U32                                   ChannelSizeMin;
+  U32                                   ChannelSizeBC;
+  U32                                   ChannelSize2BC;
+  U32                                   ChannelSize[MAX_CHANNEL];
+  U8                                    Channel;
+  U8                                    Dimm;
+
+  MadChnl.Data      = 0;
+  MadZr.Data        = 0;
+  ChannelHash.Data  = 0;
+  Inputs            = &MrcData->SysIn.Inputs;
+  Debug             = &Inputs->Debug;
+  Outputs           = &MrcData->SysOut.Outputs;
+  ControllerOut     = &MrcData->SysOut.Outputs.Controller[0];
+
+  //
+  // Add up the amount of memory in each channel.
+  //
+  for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+    ChannelOut            = &ControllerOut->Channel[Channel];
+    ChannelSize[Channel]  = 0;
+    if (ChannelOut->Status == CHANNEL_PRESENT) {
+      for (Dimm = 0; Dimm < MAX_DIMMS_IN_CHANNEL; Dimm++) {
+        if(ChannelOut->Dimm[Dimm].Status == DIMM_PRESENT) {
+        ChannelSize[Channel] += ChannelOut->Dimm[Dimm].DimmCapacity;
+      }
+    }
+  }
+  }
+  //
+  // Define MAD_ZR register:
+  // MAD-ZR-CR [29:24] = channel C size: ch_c_size
+  // MAD-ZR-CR [23:16] = (channel C size) * 3: ch_3c_size
+  // MAD-ZR-CR [15:8]  = (channel B size) * 2 + (channel C size): ch_b_2c_size
+  // MAD-ZR-CR [7:0]   = (channel B size) + (channel C size): ch_b_c_size
+  //
+  ChannelOut0 = &ControllerOut->Channel[cCHANNEL0];
+  ChannelOut1 = &ControllerOut->Channel[cCHANNEL1];
+  if (ChannelSize[cCHANNEL1] <= ChannelSize[cCHANNEL0]) {
+    MadChnl.Bits.CH_A = 0;
+    MadChnl.Bits.CH_B = 1;
+
+    //
+    // Set the virtual channel type according to the address decoding decision.
+    //
+    ChannelOut0->VirtualChannel = vcA;
+    ChannelOut1->VirtualChannel = vcB;
+
+    ChannelSizeMin              = ChannelSize[cCHANNEL1];
+  } else {
+    //
+    //  ChannelSize0 < ChannelSize1
+    //
+    MadChnl.Bits.CH_A = 1;
+    MadChnl.Bits.CH_B = 0;
+
+    //
+    // Set the virtual channel type according to the address decoding decision.
+    //
+    ChannelOut0->VirtualChannel = vcB;
+    ChannelOut1->VirtualChannel = vcA;
+
+    ChannelSizeMin              = ChannelSize[cCHANNEL0];
+  }
+  //
+  // Divided by 256 because the channel size is in 256 MB units.
+  //
+  ChannelSizeBC       = ChannelSizeMin / 256;
+  ChannelSize2BC      = ChannelSizeBC << 1;
+  MadZr.Bits.BandC    = MIN (ChannelSizeBC, MCDECS_CR_MAD_ZR_MCMAIN_BandC_MAX);
+  MadZr.Bits.TwoBandC = MIN (ChannelSize2BC, MCDECS_CR_MAD_ZR_MCMAIN_TwoBandC_MAX);
+  MadChnl.Bits.CH_C   = 2;
+
+#ifdef ULT_FLAG
+  MadChnl.Bits.LPDDR = (Outputs->DdrType == MRC_DDR_TYPE_LPDDR3) ? 1 : 0;
+#endif
+    //
+    // Interleaved mode
+    // Check for any Channel hash support
+    //
+    if (Inputs->ChHashEnable) {
+      ChannelHash.Bits.Mask         = MIN (Inputs->ChHashMask, MCDECS_CR_CHANNEL_HASH_MCMAIN_Mask_MAX);
+      ChannelHash.Bits.LSB_mask_bit = MIN (Inputs->ChHashInterleaveBit, MCDECS_CR_CHANNEL_HASH_MCMAIN_LSB_mask_bit_MAX);
+      ChannelHash.Bits.Enable       = 1;
+      MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Channel HASH Enabled\n");
+    }
+  
+  if (Inputs->MemoryTrace) {
+    if (ChannelSize[cCHANNEL0] == ChannelSize[cCHANNEL1]) {
+      //
+      // Enable the Stacked Mode for memory tracing
+      //
+      MadChnl.Bits.STKD_MODE = 1;
+      MadChnl.Bits.STKD_MODE_CH_BITS = MrcLog2 (ChannelSizeMin) - 9;
+      ChannelHash.Bits.Enable = 1;
+      MRC_DEBUG_MSG (
+        Debug, 
+        MSG_LEVEL_NOTE, 
+        "Enabling Stacked Mode for Memory Trace, Stacked Mode Ch bit = %u (%u MB per channel)\n",
+        MadChnl.Bits.STKD_MODE_CH_BITS + 28,
+        ChannelSizeMin
+        );
+    } else {
+      Inputs->MemoryTrace = 0;
+      MRC_DEBUG_MSG (Debug, MSG_LEVEL_ERROR, "Channels are not equal in size, cannot enable Memory Trace !\n");
+    }
+  }
+  
+  MRC_DEBUG_MSG (
+    Debug,
+    MSG_LEVEL_NOTE,
+    "CHANNEL_HASH = 0x%08X\nMAD_CHNL = 0x%08X\nMAD_ZR = 0x%08X\n",
+    ChannelHash.Data,
+    MadChnl.Data,
+    MadZr.Data
+    );
+  MrcWriteCR (MrcData, MCDECS_CR_CHANNEL_HASH_MCMAIN_REG, ChannelHash.Data);
+  MrcWriteCR (MrcData, MCDECS_CR_MAD_CHNL_MCMAIN_REG, MadChnl.Data);
+  MrcWriteCR (MrcData, MCDECS_CR_MAD_ZR_MCMAIN_REG, MadZr.Data);
+  return;
+}
+
+/**
+@brief
+  This function configures the MAD_DIMM_CH0/1 register.
+
+  @param[in] MrcData      - Include all MRC global data.
+  @param[in] ChannelIndex - Channel index
+
+  @retval Nothing.
+**/
+void
+ChannelAddressDecodeConfiguration (
+  IN MrcParameters *const MrcData,
+  IN const U32            ChannelIndex
+)
+{
+  const MrcInput                        *Inputs;
+  MrcOutput                             *Outputs;
+  MrcChannelOut                         *ChannelOut;
+  MrcDimmOut                            *DimmA;
+  MrcDimmOut                            *DimmB;
+  MCDECS_CR_MAD_DIMM_CH0_MCMAIN_STRUCT  MadDimm;
+  U32                                   DimmCapacity;
+  U32                                   Dimm0Capacity;
+  U32                                   Dimm1Capacity;
+  U32                                   Scratch;
+#ifdef ULT_FLAG
+  MCHBAR_CH0_CR_LPDDR_MR_PARAMS_STRUCT  LpddrMrParams;
+#endif //ULT_FLAG
+
+  Inputs        = &MrcData->SysIn.Inputs;
+  Outputs       = &MrcData->SysOut.Outputs;
+  ChannelOut    = &Outputs->Controller[0].Channel[ChannelIndex];
+  MadDimm.Data  = 0;
+  if (ChannelOut->Dimm[dDIMM0].Status == DIMM_PRESENT) {
+  Dimm0Capacity = ChannelOut->Dimm[dDIMM0].DimmCapacity;
+  } else {
+    Dimm0Capacity = 0;
+  }
+
+  if (ChannelOut->Dimm[dDIMM1].Status == DIMM_PRESENT) {
+  Dimm1Capacity = (MAX_DIMMS_IN_CHANNEL > 1) ? ChannelOut->Dimm[dDIMM1].DimmCapacity : 0;
+  } else {
+    Dimm1Capacity = 0;
+  }
+
+  //
+  // larger dimm will be located to Dimm A and small dimm will be located to dimm B
+  //
+  if (Dimm1Capacity <= Dimm0Capacity) {
+    DimmA = &ChannelOut->Dimm[dDIMM0];
+    DimmB = &ChannelOut->Dimm[dDIMM1];
+    //
+    // larger DIMM in capacity 0 - DIMM 0 or 1 - DIMM 1
+    //
+    MadDimm.Bits.DAS = 0;
+  } else {
+    DimmA = &ChannelOut->Dimm[dDIMM1];
+    DimmB = &ChannelOut->Dimm[dDIMM0];
+    //
+    // larger DIMM in capacity 0 - DIMM 0 or 1 - DIMM 1
+    //
+    MadDimm.Bits.DAS = 1;
+  }
+  //
+  // Dimm A
+  //
+  if ((0 < DimmA->RankInDIMM) && (DimmA->Status == DIMM_PRESENT)) {
+    DimmCapacity              = DimmA->DimmCapacity / 256;
+    MadDimm.Bits.DIMM_A_Size  = MIN (DimmCapacity, MCDECS_CR_MAD_DIMM_CH0_MCMAIN_DIMM_A_Size_MAX);
+    //
+    // RankInDIMM must be 1 or 2, we test the case that the value is 0
+    //
+    Scratch             = DimmA->RankInDIMM - 1;
+    MadDimm.Bits.DANOR  = MIN (Scratch, MCDECS_CR_MAD_DIMM_CH0_MCMAIN_DANOR_MAX);
+    //
+    // SDRAM width x8 or x32 set to 0, x16 set to 1
+    //
+    MadDimm.Bits.DAW = (DimmA->SdramWidth == 16) ? 1 : 0;
+  }
+  //
+  // Dimm B
+  //
+  if ((MAX_DIMMS_IN_CHANNEL > 1) && (0 < DimmB->RankInDIMM) && (DimmB->Status == DIMM_PRESENT)) {
+    DimmCapacity              = DimmB->DimmCapacity / 256;
+    MadDimm.Bits.DIMM_B_Size  = MIN (DimmCapacity, MCDECS_CR_MAD_DIMM_CH0_MCMAIN_DIMM_B_Size_MAX);
+    //
+    // RankInDIMM must be 1 or 2, we test the case that this value is 0.
+    //
+    Scratch             = DimmB->RankInDIMM - 1;
+    MadDimm.Bits.DBNOR  = MIN (Scratch, MCDECS_CR_MAD_DIMM_CH0_MCMAIN_DBNOR_MAX);
+
+    //
+    // SDRAM width x8 or x32 set to 0, x16 set to 1
+    //
+    MadDimm.Bits.DBW = (DimmB->SdramWidth == 16) ? 1 : 0;
+  }
+
+#ifdef ULT_FLAG
+  if (Inputs->CpuModel == cmHSW_ULT) {
+    //
+    // On HSW-ULT only 1DPC is supported, and DBW should have the same value as DAW
+    //
+    MadDimm.Bits.DBW = MadDimm.Bits.DAW;
+  }
+#endif
+
+  if (Inputs->RankInterleave) {
+    MadDimm.Bits.RI = MRC_DIMM_RANK_INTERLEAVE;
+  }
+  if (Inputs->EnhancedInterleave) {
+    MadDimm.Bits.Enh_Interleave = MRC_ENHANCED_INTERLEAVE_MODE;
+  }
+
+  MRC_DEBUG_MSG (&Inputs->Debug, MSG_LEVEL_NOTE, "MAD_DIMM_CH%u = 0x%08X\n", ChannelIndex, MadDimm.Data);
+  MrcWriteCR (
+    MrcData,
+    MCDECS_CR_MAD_DIMM_CH0_MCMAIN_REG +
+    (ChannelIndex * (MCDECS_CR_MAD_DIMM_CH1_MCMAIN_REG - MCDECS_CR_MAD_DIMM_CH0_MCMAIN_REG)),
+    MadDimm.Data
+    );
+
+#ifdef ULT_FLAG
+  if (Outputs->DdrType == MRC_DDR_TYPE_LPDDR3) {
+    LpddrMrParams.Data            = 0;
+    LpddrMrParams.Bits.MR4_PERIOD = 0x200D;
+
+    if (DimmA->SdramWidth == 32) {
+      LpddrMrParams.Bits.Rank_0_x32 = 1;
+      LpddrMrParams.Bits.Rank_1_x32 = 1;
+    }
+
+    MrcWriteCR (
+      MrcData,
+      MCHBAR_CH0_CR_LPDDR_MR_PARAMS_REG +
+      (ChannelIndex * (MCHBAR_CH1_CR_LPDDR_MR_PARAMS_REG - MCHBAR_CH0_CR_LPDDR_MR_PARAMS_REG)),
+      LpddrMrParams.Data
+      );
+  }
+#endif // ULT_FLAG
+  return;
+}
+
+/**
+@brief
+  This function is the main address decoding configuration function.
+
+  @param[in] MrcData - Include all MRC global data.
+
+  @retval Nothing.
+**/
+void
+MrcAdConfiguration (
+  IN MrcParameters *const MrcData
+)
+{
+  MrcOutput         *Outputs;
+  MrcChannelOut     *ChannelOut;
+  MrcControllerOut  *ControllerOut;
+  MrcDimmOut        *DimmOut;
+  U8                Controller;
+  U8                Channel;
+  U8                Dimm;
+
+  ZoneConfiguration (MrcData);
+
+  Outputs = &MrcData->SysOut.Outputs;
+  for (Controller = 0; Controller < MAX_CONTROLLERS; Controller++) {
+    ControllerOut = &Outputs->Controller[Controller];
+    for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+      if (!MrcChannelExist (Outputs, Channel)) {
+        continue;
+      }
+      ChannelOut = &ControllerOut->Channel[Channel];
+
+      ChannelAddressDecodeConfiguration (MrcData, Channel);
+
+      for (Dimm = 0; Dimm < MAX_DIMMS_IN_CHANNEL; ++Dimm) {
+        DimmOut = &ChannelOut->Dimm[Dimm];
+        if (DimmOut->Status == DIMM_PRESENT) {
+          MRC_DEBUG_MSG (
+            &MrcData->SysIn.Inputs.Debug,
+            MSG_LEVEL_NOTE,
+            "Channel: %u, Dimm %d Rank in DIMM is: %u\n",
+            Channel,
+            Dimm,
+            DimmOut->RankInDIMM
+            );
+        }
+      } // for Dimm
+    } // for Channel
+  } // for Controller
+
+  return;
+}
diff --git a/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/McConfiguration/MrcAddressDecodeConfiguration.h b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/McConfiguration/MrcAddressDecodeConfiguration.h
new file mode 100644
index 0000000..b502ec6
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/McConfiguration/MrcAddressDecodeConfiguration.h
@@ -0,0 +1,78 @@
+/** @file
+  This module configures the memory controller address decoder.
+
+@copyright
+  Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved.
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement
+*/
+#ifndef _MrcAddressConfiguration_h_
+#define _MrcAddressConfiguration_h_
+
+#include "MrcTypes.h"
+#include "MrcGlobal.h"
+#include "MrcApi.h"
+#include "McAddress.h"
+#include "MrcCommon.h"
+#include "MrcOem.h"
+#include "MrcCommon.h"
+#include "MrcOemDebugPrint.h"
+
+/**
+@brief
+  This function is the main address decoding configuration function.
+
+  @param[in] MrcData - Include all MRC global data.
+
+  @retval Nothing.
+
+**/
+extern
+void
+MrcAdConfiguration (
+  IN MrcParameters *const MrcData
+  );
+
+/**
+@brief
+  This function configures the zone configuration registers MAD-CR and MAD-ZR-CR.
+
+  @param[in, out] MrcData - Include all MRC global data.
+
+  @retval Nothing.
+**/
+extern
+void
+ZoneConfiguration (
+  IN OUT MrcParameters *const MrcData
+  );
+
+/**
+@brief
+  This function configures the MAD_DIMM_CH0/1 register.
+
+  @param[in] MrcData      - Include all MRC global data.
+  @param[in] ChannelIndex - Channel index
+
+  @retval Nothing.
+**/
+extern
+void
+ChannelAddressDecodeConfiguration (
+  IN MrcParameters *const MrcData,
+  IN const U32            ChannelIndex
+  );
+
+#endif
diff --git a/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/McConfiguration/MrcPowerModes.c b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/McConfiguration/MrcPowerModes.c
new file mode 100644
index 0000000..9c06a65
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/McConfiguration/MrcPowerModes.c
@@ -0,0 +1,1034 @@
+/** @file
+  This module configures the memory controller power modes.
+
+@copyright
+  Copyright (c) 1999 - 2013 Intel Corporation. All rights reserved.
+
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement.
+
+**/
+
+///
+/// Include files
+///
+#include "MrcPowerModes.h"
+#include "MrcOemDebugPrint.h"
+#include "MrcSpdProcessing.h"
+
+const Ddr3PowerWeightEntry Ddr3PowerWeightTable[] = {
+  {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_8,  RANKS_1, DPC_1, FREQ_1067, DENSITY_2, 0}}, 4, 0x6A, 0xCA, 0x82, 0x9, 0x10, 0x08},
+  {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_8,  RANKS_2, DPC_1, FREQ_1067, DENSITY_2, 0}}, 3, 0x34, 0x89, 0x40, 0x5, 0x07, 0x0B},
+  {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_8,  RANKS_1, DPC_1, FREQ_1067, DENSITY_4, 0}}, 4, 0x78, 0xD6, 0x86, 0xB, 0x13, 0x09},
+  {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_8,  RANKS_2, DPC_1, FREQ_1067, DENSITY_4, 0}}, 3, 0x3B, 0x8F, 0x42, 0x6, 0x09, 0x0E},
+  {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_1, DPC_1, FREQ_1067, DENSITY_2, 0}}, 4, 0x5B, 0xB0, 0x7C, 0x5, 0x0B, 0x07},
+  {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_2, DPC_1, FREQ_1067, DENSITY_2, 0}}, 4, 0x58, 0xF7, 0x7A, 0x5, 0x09, 0x09},
+  {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_1, DPC_1, FREQ_1067, DENSITY_4, 0}}, 4, 0x66, 0xB9, 0x81, 0x6, 0x0D, 0x08},
+  {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_2, DPC_1, FREQ_1067, DENSITY_4, 0}}, 3, 0x32, 0x80, 0x40, 0x3, 0x05, 0x09},
+  {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_8,  RANKS_1, DPC_2, FREQ_1067, DENSITY_2, 0}}, 3, 0x9F, 0xCA, 0x40, 0x5, 0x07, 0x11},
+  {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_8,  RANKS_2, DPC_2, FREQ_1067, DENSITY_2, 0}}, 3, 0x9E, 0xCA, 0x3F, 0x5, 0x07, 0x18},
+  {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_8,  RANKS_1, DPC_2, FREQ_1067, DENSITY_4, 0}}, 3, 0xA6, 0xD0, 0x42, 0x6, 0x09, 0x13},
+  {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_8,  RANKS_2, DPC_2, FREQ_1067, DENSITY_4, 0}}, 3, 0xA5, 0xD0, 0x41, 0x6, 0x08, 0x1A},
+  {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_1, DPC_2, FREQ_1067, DENSITY_2, 0}}, 3, 0x98, 0xBD, 0x3D, 0x3, 0x05, 0x0F},
+  {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_2, DPC_2, FREQ_1067, DENSITY_2, 0}}, 3, 0x97, 0xBD, 0x3D, 0x3, 0x04, 0x12},
+  {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_1, DPC_2, FREQ_1067, DENSITY_4, 0}}, 3, 0x9D, 0xC2, 0x40, 0x3, 0x06, 0x10},
+  {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_2, DPC_2, FREQ_1067, DENSITY_4, 0}}, 3, 0x9C, 0xC1, 0x3F, 0x3, 0x05, 0x14},
+  {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_8,  RANKS_1, DPC_1, FREQ_1333, DENSITY_2, 0}}, 4, 0x66, 0xB3, 0x88, 0x8, 0x0E, 0x0A},
+  {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_8,  RANKS_2, DPC_1, FREQ_1333, DENSITY_2, 0}}, 4, 0x64, 0xB1, 0x86, 0x8, 0x0C, 0x0D},
+  {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_8,  RANKS_1, DPC_1, FREQ_1333, DENSITY_4, 0}}, 4, 0x74, 0xBF, 0x8B, 0xA, 0x11, 0x0B},
+  {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_8,  RANKS_2, DPC_1, FREQ_1333, DENSITY_4, 0}}, 4, 0x72, 0xBD, 0x89, 0xA, 0x0F, 0x0F},
+  {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_1, DPC_1, FREQ_1333, DENSITY_2, 0}}, 4, 0x57, 0x9A, 0x7C, 0x4, 0x0A, 0x08},
+  {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_2, DPC_1, FREQ_1333, DENSITY_2, 0}}, 4, 0x55, 0x98, 0x7A, 0x4, 0x08, 0x0A},
+  {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_1, DPC_1, FREQ_1333, DENSITY_4, 0}}, 4, 0x62, 0xA3, 0x80, 0x5, 0x0B, 0x09},
+  {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_2, DPC_1, FREQ_1333, DENSITY_4, 0}}, 4, 0x60, 0xA1, 0x7E, 0x5, 0x09, 0x0B},
+  {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_8,  RANKS_1, DPC_2, FREQ_1333, DENSITY_2, 0}}, 3, 0x88, 0xAB, 0x43, 0x4, 0x07, 0x14},
+  {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_8,  RANKS_2, DPC_2, FREQ_1333, DENSITY_2, 0}}, 3, 0x87, 0xAA, 0x43, 0x4, 0x06, 0x1A},
+  {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_8,  RANKS_1, DPC_2, FREQ_1333, DENSITY_4, 0}}, 3, 0x8F, 0xB1, 0x45, 0x5, 0x08, 0x15},
+  {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_8,  RANKS_2, DPC_2, FREQ_1333, DENSITY_4, 0}}, 3, 0x8F, 0xB0, 0x44, 0x5, 0x07, 0x1D},
+  {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_1, DPC_2, FREQ_1333, DENSITY_2, 0}}, 3, 0x81, 0x9E, 0x3D, 0x2, 0x04, 0x10},
+  {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_2, DPC_2, FREQ_1333, DENSITY_2, 0}}, 3, 0x80, 0x9E, 0x3D, 0x2, 0x04, 0x15},
+  {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_1, DPC_2, FREQ_1333, DENSITY_4, 0}}, 3, 0x86, 0xA3, 0x3F, 0x3, 0x05, 0x11},
+  {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_2, DPC_2, FREQ_1333, DENSITY_4, 0}}, 3, 0x85, 0xA2, 0x3F, 0x3, 0x04, 0x15},
+  {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_8,  RANKS_1, DPC_1, FREQ_1600, DENSITY_2, 0}}, 4, 0x72, 0xFD, 0x90, 0x7, 0x0D, 0x0C},
+  {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_8,  RANKS_2, DPC_1, FREQ_1600, DENSITY_2, 0}}, 4, 0x71, 0xFB, 0x8E, 0x7, 0x0B, 0x0F},
+  {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_8,  RANKS_1, DPC_1, FREQ_1600, DENSITY_4, 0}}, 3, 0x40, 0x85, 0x4A, 0x5, 0x08, 0x0E},
+  {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_8,  RANKS_2, DPC_1, FREQ_1600, DENSITY_4, 0}}, 3, 0x3F, 0x84, 0x49, 0x5, 0x07, 0x12},
+  {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_1, DPC_1, FREQ_1600, DENSITY_2, 0}}, 4, 0x62, 0xE4, 0x7E, 0x4, 0x09, 0x0A},
+  {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_2, DPC_1, FREQ_1600, DENSITY_2, 0}}, 4, 0x61, 0xE3, 0x7C, 0x4, 0x07, 0x0C},
+  {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_1, DPC_1, FREQ_1600, DENSITY_4, 0}}, 4, 0x6C, 0xED, 0x82, 0x5, 0x0A, 0x0B},
+  {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_2, DPC_1, FREQ_1600, DENSITY_4, 0}}, 4, 0x6B, 0xEB, 0x80, 0x5, 0x08, 0x0D},
+  {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_8,  RANKS_1, DPC_2, FREQ_1600, DENSITY_2, 0}}, 3, 0x8E, 0xCE, 0x47, 0x4, 0x06, 0x17},
+  {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_8,  RANKS_2, DPC_2, FREQ_1600, DENSITY_2, 0}}, 3, 0x8E, 0xCD, 0x47, 0x4, 0x06, 0x20},
+  {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_8,  RANKS_1, DPC_2, FREQ_1600, DENSITY_4, 0}}, 3, 0x95, 0xD4, 0x49, 0x5, 0x07, 0x19},
+  {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_8,  RANKS_2, DPC_2, FREQ_1600, DENSITY_4, 0}}, 3, 0x95, 0xD3, 0x48, 0x5, 0x07, 0x23},
+  {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_1, DPC_2, FREQ_1600, DENSITY_2, 0}}, 3, 0x86, 0xC1, 0x3E, 0x2, 0x04, 0x13},
+  {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_2, DPC_2, FREQ_1600, DENSITY_2, 0}}, 3, 0x86, 0xC1, 0x3E, 0x2, 0x03, 0x16},
+  {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_1, DPC_2, FREQ_1600, DENSITY_4, 0}}, 3, 0x8C, 0xC6, 0x40, 0x3, 0x04, 0x14},
+  {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_2, DPC_2, FREQ_1600, DENSITY_4, 0}}, 3, 0x8B, 0xC5, 0x40, 0x3, 0x04, 0x1A},
+  {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_8,  RANKS_1, DPC_1, FREQ_1867, DENSITY_2, 0}}, 4, 0x6F, 0xE6, 0x9C, 0x7, 0x0C, 0x0E},
+  {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_8,  RANKS_2, DPC_1, FREQ_1867, DENSITY_2, 0}}, 4, 0x6D, 0xE4, 0x9B, 0x7, 0x0B, 0x12},
+  {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_8,  RANKS_1, DPC_1, FREQ_1867, DENSITY_4, 0}}, 4, 0x7C, 0xF1, 0x9F, 0x8, 0x0E, 0x0F},
+  {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_8,  RANKS_2, DPC_1, FREQ_1867, DENSITY_4, 0}}, 4, 0x7B, 0xF0, 0x9D, 0x8, 0x0D, 0x14},
+  {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_1, DPC_1, FREQ_1867, DENSITY_2, 0}}, 4, 0x5F, 0xCE, 0x83, 0x4, 0x08, 0x0B},
+  {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_2, DPC_1, FREQ_1867, DENSITY_2, 0}}, 4, 0x5E, 0xCC, 0x82, 0x4, 0x06, 0x0D},
+  {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_1, DPC_1, FREQ_1867, DENSITY_4, 0}}, 4, 0x69, 0xD6, 0x87, 0x5, 0x09, 0x0C},
+  {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_2, DPC_1, FREQ_1867, DENSITY_4, 0}}, 4, 0x68, 0xD5, 0x86, 0x5, 0x07, 0x0E},
+  {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_8,  RANKS_1, DPC_2, FREQ_1867, DENSITY_2, 0}}, 3, 0x81, 0xB7, 0x4E, 0x4, 0x06, 0x1A},
+  {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_8,  RANKS_2, DPC_2, FREQ_1867, DENSITY_2, 0}}, 3, 0x80, 0xB6, 0x4D, 0x4, 0x05, 0x21},
+  {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_8,  RANKS_1, DPC_2, FREQ_1867, DENSITY_4, 0}}, 3, 0x87, 0xBD, 0x4F, 0x4, 0x07, 0x1C},
+  {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_8,  RANKS_2, DPC_2, FREQ_1867, DENSITY_4, 0}}, 3, 0x87, 0xBC, 0x4F, 0x4, 0x06, 0x25},
+  {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_1, DPC_2, FREQ_1867, DENSITY_2, 0}}, 3, 0x79, 0xAB, 0x41, 0x2, 0x04, 0x15},
+  {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_2, DPC_2, FREQ_1867, DENSITY_2, 0}}, 3, 0x78, 0xAA, 0x41, 0x2, 0x03, 0x19},
+  {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_1, DPC_2, FREQ_1867, DENSITY_4, 0}}, 3, 0x7E, 0xAF, 0x43, 0x3, 0x04, 0x16},
+  {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_2, DPC_2, FREQ_1867, DENSITY_4, 0}}, 3, 0x7D, 0xAF, 0x43, 0x3, 0x04, 0x1D},
+  {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_8,  RANKS_1, DPC_1, FREQ_2133, DENSITY_2, 0}}, 4, 0x6C, 0xD4, 0xA6, 0x6, 0x0B, 0x0F},
+  {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_8,  RANKS_2, DPC_1, FREQ_2133, DENSITY_2, 0}}, 4, 0x6B, 0xD3, 0xA4, 0x6, 0x0A, 0x13},
+  {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_8,  RANKS_1, DPC_1, FREQ_2133, DENSITY_4, 0}}, 4, 0x7A, 0xE0, 0xA8, 0x8, 0x0D, 0x11},
+  {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_8,  RANKS_2, DPC_1, FREQ_2133, DENSITY_4, 0}}, 4, 0x79, 0xDE, 0xA7, 0x8, 0x0C, 0x16},
+  {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_1, DPC_1, FREQ_2133, DENSITY_2, 0}}, 4, 0x5C, 0xBD, 0x87, 0x3, 0x07, 0x0C},
+  {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_2, DPC_1, FREQ_2133, DENSITY_2, 0}}, 4, 0x5B, 0xBB, 0x85, 0x3, 0x06, 0x0E},
+  {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_1, DPC_1, FREQ_2133, DENSITY_4, 0}}, 4, 0x66, 0xC5, 0x8A, 0x4, 0x08, 0x0D},
+  {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_2, DPC_1, FREQ_2133, DENSITY_4, 0}}, 4, 0x65, 0xC3, 0x89, 0x4, 0x07, 0x10},
+  {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_8,  RANKS_1, DPC_2, FREQ_2133, DENSITY_2, 0}}, 3, 0x76, 0xA6, 0x52, 0x3, 0x05, 0x1A},
+  {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_8,  RANKS_2, DPC_2, FREQ_2133, DENSITY_2, 0}}, 3, 0x76, 0xA5, 0x52, 0x3, 0x05, 0x24},
+  {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_8,  RANKS_1, DPC_2, FREQ_2133, DENSITY_4, 0}}, 3, 0x7D, 0xAB, 0x54, 0x4, 0x06, 0x1D},
+  {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_8,  RANKS_2, DPC_2, FREQ_2133, DENSITY_4, 0}}, 3, 0x7D, 0xAB, 0x53, 0x4, 0x06, 0x29},
+  {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_1, DPC_2, FREQ_2133, DENSITY_2, 0}}, 3, 0x6E, 0x9A, 0x43, 0x2, 0x03, 0x15},
+  {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_2, DPC_2, FREQ_2133, DENSITY_2, 0}}, 3, 0x6E, 0x9A, 0x43, 0x2, 0x03, 0x1B},
+  {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_1, DPC_2, FREQ_2133, DENSITY_4, 0}}, 3, 0x73, 0x9E, 0x45, 0x2, 0x04, 0x18},
+  {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_2, DPC_2, FREQ_2133, DENSITY_4, 0}}, 3, 0x73, 0x9D, 0x44, 0x2, 0x03, 0x1C},
+  {{{VDD_150, ECC_F, TYPE_UDIMM,  WIDTH_8,  RANKS_1, DPC_1, FREQ_1067, DENSITY_2, 0}}, 4, 0x77, 0xC9, 0x82, 0x9, 0x10, 0x09},
+  {{{VDD_150, ECC_F, TYPE_UDIMM,  WIDTH_8,  RANKS_2, DPC_1, FREQ_1067, DENSITY_2, 0}}, 4, 0x75, 0xC7, 0x7F, 0x9, 0x0E, 0x0C},
+  {{{VDD_150, ECC_F, TYPE_UDIMM,  WIDTH_8,  RANKS_1, DPC_1, FREQ_1067, DENSITY_4, 0}}, 4, 0x85, 0xD6, 0x86, 0xB, 0x13, 0x0A},
+  {{{VDD_150, ECC_F, TYPE_UDIMM,  WIDTH_8,  RANKS_2, DPC_1, FREQ_1067, DENSITY_4, 0}}, 4, 0x83, 0xD3, 0x83, 0xB, 0x11, 0x0D},
+  {{{VDD_150, ECC_F, TYPE_UDIMM,  WIDTH_16, RANKS_1, DPC_1, FREQ_1067, DENSITY_2, 0}}, 4, 0x68, 0xB0, 0x7C, 0x5, 0x0B, 0x07},
+  {{{VDD_150, ECC_F, TYPE_UDIMM,  WIDTH_16, RANKS_2, DPC_1, FREQ_1067, DENSITY_2, 0}}, 4, 0x66, 0xAE, 0x7A, 0x5, 0x09, 0x09},
+  {{{VDD_150, ECC_F, TYPE_UDIMM,  WIDTH_16, RANKS_1, DPC_1, FREQ_1067, DENSITY_4, 0}}, 4, 0x73, 0xB9, 0x81, 0x6, 0x0D, 0x08},
+  {{{VDD_150, ECC_F, TYPE_UDIMM,  WIDTH_16, RANKS_2, DPC_1, FREQ_1067, DENSITY_4, 0}}, 4, 0x71, 0xB7, 0x7E, 0x6, 0x0A, 0x0A},
+  {{{VDD_150, ECC_F, TYPE_UDIMM,  WIDTH_8,  RANKS_1, DPC_2, FREQ_1067, DENSITY_2, 0}}, 3, 0xBD, 0xE8, 0x40, 0x5, 0x07, 0x13},
+  {{{VDD_150, ECC_F, TYPE_UDIMM,  WIDTH_8,  RANKS_2, DPC_2, FREQ_1067, DENSITY_2, 0}}, 3, 0xBD, 0xE8, 0x3F, 0x5, 0x07, 0x1A},
+  {{{VDD_150, ECC_F, TYPE_UDIMM,  WIDTH_8,  RANKS_1, DPC_2, FREQ_1067, DENSITY_4, 0}}, 3, 0xC4, 0xEF, 0x42, 0x6, 0x09, 0x15},
+  {{{VDD_150, ECC_F, TYPE_UDIMM,  WIDTH_8,  RANKS_2, DPC_2, FREQ_1067, DENSITY_4, 0}}, 3, 0xC3, 0xEE, 0x41, 0x6, 0x08, 0x1C},
+  {{{VDD_150, ECC_F, TYPE_UDIMM,  WIDTH_16, RANKS_1, DPC_2, FREQ_1067, DENSITY_2, 0}}, 3, 0xB6, 0xDC, 0x3D, 0x3, 0x05, 0x11},
+  {{{VDD_150, ECC_F, TYPE_UDIMM,  WIDTH_16, RANKS_2, DPC_2, FREQ_1067, DENSITY_2, 0}}, 3, 0xB5, 0xDB, 0x3D, 0x3, 0x04, 0x14},
+  {{{VDD_150, ECC_F, TYPE_UDIMM,  WIDTH_16, RANKS_1, DPC_2, FREQ_1067, DENSITY_4, 0}}, 3, 0xBB, 0xE0, 0x40, 0x3, 0x06, 0x12},
+  {{{VDD_150, ECC_F, TYPE_UDIMM,  WIDTH_16, RANKS_2, DPC_2, FREQ_1067, DENSITY_4, 0}}, 3, 0xBB, 0xDF, 0x3F, 0x3, 0x05, 0x16},
+  {{{VDD_150, ECC_F, TYPE_UDIMM,  WIDTH_8,  RANKS_1, DPC_1, FREQ_1333, DENSITY_2, 0}}, 4, 0x71, 0xB2, 0x88, 0x8, 0x0E, 0x0A},
+  {{{VDD_150, ECC_F, TYPE_UDIMM,  WIDTH_8,  RANKS_2, DPC_1, FREQ_1333, DENSITY_2, 0}}, 4, 0x6F, 0xB1, 0x86, 0x8, 0x0C, 0x0D},
+  {{{VDD_150, ECC_F, TYPE_UDIMM,  WIDTH_8,  RANKS_1, DPC_1, FREQ_1333, DENSITY_4, 0}}, 4, 0x7F, 0xBF, 0x8B, 0xA, 0x11, 0x0B},
+  {{{VDD_150, ECC_F, TYPE_UDIMM,  WIDTH_8,  RANKS_2, DPC_1, FREQ_1333, DENSITY_4, 0}}, 4, 0x7D, 0xBD, 0x89, 0xA, 0x0F, 0x0F},
+  {{{VDD_150, ECC_F, TYPE_UDIMM,  WIDTH_16, RANKS_1, DPC_1, FREQ_1333, DENSITY_2, 0}}, 4, 0x62, 0x9A, 0x7C, 0x4, 0x0A, 0x08},
+  {{{VDD_150, ECC_F, TYPE_UDIMM,  WIDTH_16, RANKS_2, DPC_1, FREQ_1333, DENSITY_2, 0}}, 4, 0x60, 0x98, 0x7A, 0x4, 0x08, 0x0A},
+  {{{VDD_150, ECC_F, TYPE_UDIMM,  WIDTH_16, RANKS_1, DPC_1, FREQ_1333, DENSITY_4, 0}}, 4, 0x6D, 0xA3, 0x80, 0x5, 0x0B, 0x09},
+  {{{VDD_150, ECC_F, TYPE_UDIMM,  WIDTH_16, RANKS_2, DPC_1, FREQ_1333, DENSITY_4, 0}}, 4, 0x6B, 0xA1, 0x7E, 0x5, 0x09, 0x0B},
+  {{{VDD_150, ECC_F, TYPE_UDIMM,  WIDTH_8,  RANKS_1, DPC_2, FREQ_1333, DENSITY_2, 0}}, 3, 0xA0, 0xC3, 0x43, 0x4, 0x07, 0x15},
+  {{{VDD_150, ECC_F, TYPE_UDIMM,  WIDTH_8,  RANKS_2, DPC_2, FREQ_1333, DENSITY_2, 0}}, 3, 0xA0, 0xC2, 0x43, 0x4, 0x06, 0x1C},
+  {{{VDD_150, ECC_F, TYPE_UDIMM,  WIDTH_8,  RANKS_1, DPC_2, FREQ_1333, DENSITY_4, 0}}, 3, 0xA7, 0xC9, 0x45, 0x5, 0x08, 0x17},
+  {{{VDD_150, ECC_F, TYPE_UDIMM,  WIDTH_8,  RANKS_2, DPC_2, FREQ_1333, DENSITY_4, 0}}, 3, 0xA7, 0xC8, 0x44, 0x5, 0x07, 0x1F},
+  {{{VDD_150, ECC_F, TYPE_UDIMM,  WIDTH_16, RANKS_1, DPC_2, FREQ_1333, DENSITY_2, 0}}, 3, 0x99, 0xB6, 0x3D, 0x2, 0x04, 0x11},
+  {{{VDD_150, ECC_F, TYPE_UDIMM,  WIDTH_16, RANKS_2, DPC_2, FREQ_1333, DENSITY_2, 0}}, 3, 0x98, 0xB6, 0x3D, 0x2, 0x04, 0x16},
+  {{{VDD_150, ECC_F, TYPE_UDIMM,  WIDTH_16, RANKS_1, DPC_2, FREQ_1333, DENSITY_4, 0}}, 3, 0x9E, 0xBB, 0x3F, 0x3, 0x05, 0x13},
+  {{{VDD_150, ECC_F, TYPE_UDIMM,  WIDTH_16, RANKS_2, DPC_2, FREQ_1333, DENSITY_4, 0}}, 3, 0x9E, 0xBA, 0x3F, 0x3, 0x04, 0x17},
+  {{{VDD_150, ECC_F, TYPE_UDIMM,  WIDTH_8,  RANKS_1, DPC_1, FREQ_1600, DENSITY_2, 0}}, 4, 0x79, 0xD2, 0x90, 0x7, 0x0D, 0x0C},
+  {{{VDD_150, ECC_F, TYPE_UDIMM,  WIDTH_8,  RANKS_2, DPC_1, FREQ_1600, DENSITY_2, 0}}, 4, 0x77, 0xD0, 0x8E, 0x7, 0x0B, 0x0F},
+  {{{VDD_150, ECC_F, TYPE_UDIMM,  WIDTH_8,  RANKS_1, DPC_1, FREQ_1600, DENSITY_4, 0}}, 4, 0x87, 0xDE, 0x93, 0x9, 0x0F, 0x0D},
+  {{{VDD_150, ECC_F, TYPE_UDIMM,  WIDTH_8,  RANKS_2, DPC_1, FREQ_1600, DENSITY_4, 0}}, 4, 0x85, 0xDC, 0x91, 0x9, 0x0D, 0x11},
+  {{{VDD_150, ECC_F, TYPE_UDIMM,  WIDTH_16, RANKS_1, DPC_1, FREQ_1600, DENSITY_2, 0}}, 4, 0x69, 0xBA, 0x7E, 0x4, 0x08, 0x0A},
+  {{{VDD_150, ECC_F, TYPE_UDIMM,  WIDTH_16, RANKS_2, DPC_1, FREQ_1600, DENSITY_2, 0}}, 4, 0x67, 0xB8, 0x7C, 0x4, 0x07, 0x0C},
+  {{{VDD_150, ECC_F, TYPE_UDIMM,  WIDTH_16, RANKS_1, DPC_1, FREQ_1600, DENSITY_4, 0}}, 4, 0x73, 0xC2, 0x81, 0x5, 0x0A, 0x0B},
+  {{{VDD_150, ECC_F, TYPE_UDIMM,  WIDTH_16, RANKS_2, DPC_1, FREQ_1600, DENSITY_4, 0}}, 4, 0x72, 0xC0, 0x80, 0x5, 0x08, 0x0D},
+  {{{VDD_150, ECC_F, TYPE_UDIMM,  WIDTH_8,  RANKS_1, DPC_2, FREQ_1600, DENSITY_2, 0}}, 3, 0x8E, 0xBA, 0x47, 0x4, 0x06, 0x17},
+  {{{VDD_150, ECC_F, TYPE_UDIMM,  WIDTH_8,  RANKS_2, DPC_2, FREQ_1600, DENSITY_2, 0}}, 3, 0x8E, 0xBA, 0x47, 0x4, 0x06, 0x20},
+  {{{VDD_150, ECC_F, TYPE_UDIMM,  WIDTH_8,  RANKS_1, DPC_2, FREQ_1600, DENSITY_4, 0}}, 3, 0x95, 0xC0, 0x49, 0x5, 0x07, 0x19},
+  {{{VDD_150, ECC_F, TYPE_UDIMM,  WIDTH_8,  RANKS_2, DPC_2, FREQ_1600, DENSITY_4, 0}}, 3, 0x94, 0xC0, 0x48, 0x5, 0x07, 0x23},
+  {{{VDD_150, ECC_F, TYPE_UDIMM,  WIDTH_16, RANKS_1, DPC_2, FREQ_1600, DENSITY_2, 0}}, 3, 0x86, 0xAE, 0x3E, 0x2, 0x04, 0x13},
+  {{{VDD_150, ECC_F, TYPE_UDIMM,  WIDTH_16, RANKS_2, DPC_2, FREQ_1600, DENSITY_2, 0}}, 3, 0x86, 0xAE, 0x3E, 0x2, 0x03, 0x16},
+  {{{VDD_150, ECC_F, TYPE_UDIMM,  WIDTH_16, RANKS_1, DPC_2, FREQ_1600, DENSITY_4, 0}}, 3, 0x8B, 0xB2, 0x40, 0x3, 0x04, 0x14},
+  {{{VDD_150, ECC_F, TYPE_UDIMM,  WIDTH_16, RANKS_2, DPC_2, FREQ_1600, DENSITY_4, 0}}, 3, 0x8B, 0xB2, 0x40, 0x3, 0x04, 0x1A},
+  {{{VDD_150, ECC_F, TYPE_UDIMM,  WIDTH_8,  RANKS_1, DPC_1, FREQ_1867, DENSITY_2, 0}}, 4, 0x75, 0xC1, 0x9C, 0x7, 0x0C, 0x0E},
+  {{{VDD_150, ECC_F, TYPE_UDIMM,  WIDTH_8,  RANKS_2, DPC_1, FREQ_1867, DENSITY_2, 0}}, 4, 0x73, 0xBF, 0x9B, 0x7, 0x0B, 0x12},
+  {{{VDD_150, ECC_F, TYPE_UDIMM,  WIDTH_8,  RANKS_1, DPC_1, FREQ_1867, DENSITY_4, 0}}, 4, 0x82, 0xCC, 0x9F, 0x8, 0x0E, 0x0F},
+  {{{VDD_150, ECC_F, TYPE_UDIMM,  WIDTH_8,  RANKS_2, DPC_1, FREQ_1867, DENSITY_4, 0}}, 4, 0x81, 0xCB, 0x9D, 0x8, 0x0C, 0x14},
+  {{{VDD_150, ECC_F, TYPE_UDIMM,  WIDTH_16, RANKS_1, DPC_1, FREQ_1867, DENSITY_2, 0}}, 4, 0x65, 0xA9, 0x83, 0x4, 0x08, 0x0B},
+  {{{VDD_150, ECC_F, TYPE_UDIMM,  WIDTH_16, RANKS_2, DPC_1, FREQ_1867, DENSITY_2, 0}}, 4, 0x64, 0xA8, 0x82, 0x4, 0x06, 0x0D},
+  {{{VDD_150, ECC_F, TYPE_UDIMM,  WIDTH_16, RANKS_1, DPC_1, FREQ_1867, DENSITY_4, 0}}, 4, 0x6F, 0xB1, 0x87, 0x5, 0x09, 0x0C},
+  {{{VDD_150, ECC_F, TYPE_UDIMM,  WIDTH_16, RANKS_2, DPC_1, FREQ_1867, DENSITY_4, 0}}, 4, 0x6E, 0xB0, 0x86, 0x5, 0x07, 0x0E},
+  {{{VDD_150, ECC_F, TYPE_UDIMM,  WIDTH_8,  RANKS_1, DPC_2, FREQ_1867, DENSITY_2, 0}}, 3, 0x80, 0xA6, 0x4E, 0x4, 0x06, 0x1A},
+  {{{VDD_150, ECC_F, TYPE_UDIMM,  WIDTH_8,  RANKS_2, DPC_2, FREQ_1867, DENSITY_2, 0}}, 3, 0x80, 0xA6, 0x4D, 0x4, 0x05, 0x21},
+  {{{VDD_150, ECC_F, TYPE_UDIMM,  WIDTH_8,  RANKS_1, DPC_2, FREQ_1867, DENSITY_4, 0}}, 3, 0x87, 0xAC, 0x4F, 0x4, 0x07, 0x1C},
+  {{{VDD_150, ECC_F, TYPE_UDIMM,  WIDTH_8,  RANKS_2, DPC_2, FREQ_1867, DENSITY_4, 0}}, 3, 0x87, 0xAB, 0x4F, 0x4, 0x06, 0x25},
+  {{{VDD_150, ECC_F, TYPE_UDIMM,  WIDTH_16, RANKS_1, DPC_2, FREQ_1867, DENSITY_2, 0}}, 3, 0x78, 0x9A, 0x41, 0x2, 0x04, 0x15},
+  {{{VDD_150, ECC_F, TYPE_UDIMM,  WIDTH_16, RANKS_2, DPC_2, FREQ_1867, DENSITY_2, 0}}, 3, 0x78, 0x9A, 0x41, 0x2, 0x03, 0x19},
+  {{{VDD_150, ECC_F, TYPE_UDIMM,  WIDTH_16, RANKS_1, DPC_2, FREQ_1867, DENSITY_4, 0}}, 3, 0x7D, 0x9E, 0x43, 0x3, 0x04, 0x16},
+  {{{VDD_150, ECC_F, TYPE_UDIMM,  WIDTH_16, RANKS_2, DPC_2, FREQ_1867, DENSITY_4, 0}}, 3, 0x7D, 0x9E, 0x43, 0x3, 0x04, 0x1D},
+  {{{VDD_150, ECC_F, TYPE_UDIMM,  WIDTH_8,  RANKS_1, DPC_1, FREQ_2133, DENSITY_2, 0}}, 4, 0x72, 0xB4, 0xA5, 0x6, 0x0B, 0x0F},
+  {{{VDD_150, ECC_F, TYPE_UDIMM,  WIDTH_8,  RANKS_2, DPC_1, FREQ_2133, DENSITY_2, 0}}, 4, 0x70, 0xB3, 0xA4, 0x6, 0x0A, 0x14},
+  {{{VDD_150, ECC_F, TYPE_UDIMM,  WIDTH_8,  RANKS_1, DPC_1, FREQ_2133, DENSITY_4, 0}}, 4, 0x7F, 0xC0, 0xA8, 0x8, 0x0D, 0x11},
+  {{{VDD_150, ECC_F, TYPE_UDIMM,  WIDTH_8,  RANKS_2, DPC_1, FREQ_2133, DENSITY_4, 0}}, 4, 0x7E, 0xBE, 0xA7, 0x8, 0x0C, 0x16},
+  {{{VDD_150, ECC_F, TYPE_UDIMM,  WIDTH_16, RANKS_1, DPC_1, FREQ_2133, DENSITY_2, 0}}, 4, 0x61, 0x9D, 0x87, 0x3, 0x07, 0x0C},
+  {{{VDD_150, ECC_F, TYPE_UDIMM,  WIDTH_16, RANKS_2, DPC_1, FREQ_2133, DENSITY_2, 0}}, 4, 0x60, 0x9B, 0x85, 0x3, 0x06, 0x0E},
+  {{{VDD_150, ECC_F, TYPE_UDIMM,  WIDTH_16, RANKS_1, DPC_1, FREQ_2133, DENSITY_4, 0}}, 4, 0x6B, 0xA4, 0x8A, 0x4, 0x08, 0x0D},
+  {{{VDD_150, ECC_F, TYPE_UDIMM,  WIDTH_16, RANKS_2, DPC_1, FREQ_2133, DENSITY_4, 0}}, 4, 0x6A, 0xA3, 0x89, 0x4, 0x07, 0x10},
+  {{{VDD_150, ECC_F, TYPE_UDIMM,  WIDTH_8,  RANKS_1, DPC_2, FREQ_2133, DENSITY_2, 0}}, 3, 0x76, 0x97, 0x52, 0x3, 0x05, 0x1A},
+  {{{VDD_150, ECC_F, TYPE_UDIMM,  WIDTH_8,  RANKS_2, DPC_2, FREQ_2133, DENSITY_2, 0}}, 3, 0x76, 0x97, 0x52, 0x3, 0x05, 0x24},
+  {{{VDD_150, ECC_F, TYPE_UDIMM,  WIDTH_8,  RANKS_1, DPC_2, FREQ_2133, DENSITY_4, 0}}, 3, 0x7D, 0x9D, 0x54, 0x4, 0x06, 0x1D},
+  {{{VDD_150, ECC_F, TYPE_UDIMM,  WIDTH_8,  RANKS_2, DPC_2, FREQ_2133, DENSITY_4, 0}}, 3, 0x7C, 0x9C, 0x53, 0x4, 0x06, 0x29},
+  {{{VDD_150, ECC_F, TYPE_UDIMM,  WIDTH_16, RANKS_1, DPC_2, FREQ_2133, DENSITY_2, 0}}, 3, 0x6E, 0x8B, 0x43, 0x2, 0x03, 0x15},
+  {{{VDD_150, ECC_F, TYPE_UDIMM,  WIDTH_16, RANKS_2, DPC_2, FREQ_2133, DENSITY_2, 0}}, 3, 0x6D, 0x8B, 0x43, 0x2, 0x03, 0x1B},
+  {{{VDD_150, ECC_F, TYPE_UDIMM,  WIDTH_16, RANKS_1, DPC_2, FREQ_2133, DENSITY_4, 0}}, 3, 0x73, 0x8F, 0x45, 0x2, 0x04, 0x18},
+  {{{VDD_150, ECC_F, TYPE_UDIMM,  WIDTH_16, RANKS_2, DPC_2, FREQ_2133, DENSITY_4, 0}}, 3, 0x72, 0x8F, 0x44, 0x2, 0x03, 0x1C},
+  {{{VDD_150, ECC_T, TYPE_UDIMM,  WIDTH_8,  RANKS_1, DPC_1, FREQ_1067, DENSITY_2, 0}}, 4, 0x85, 0xE2, 0x91, 0xA, 0x12, 0x08},
+  {{{VDD_150, ECC_T, TYPE_UDIMM,  WIDTH_8,  RANKS_2, DPC_1, FREQ_1067, DENSITY_2, 0}}, 4, 0x83, 0xDF, 0x8F, 0xA, 0x0F, 0x0B},
+  {{{VDD_150, ECC_T, TYPE_UDIMM,  WIDTH_8,  RANKS_1, DPC_1, FREQ_1067, DENSITY_4, 0}}, 4, 0x95, 0xF0, 0x96, 0xD, 0x15, 0x09},
+  {{{VDD_150, ECC_T, TYPE_UDIMM,  WIDTH_8,  RANKS_2, DPC_1, FREQ_1067, DENSITY_4, 0}}, 4, 0x92, 0xED, 0x93, 0xD, 0x13, 0x0D},
+  {{{VDD_150, ECC_T, TYPE_UDIMM,  WIDTH_16, RANKS_1, DPC_1, FREQ_1067, DENSITY_2, 0}}, 4, 0x7E, 0xCF, 0x9A, 0x6, 0x0C, 0x06},
+  {{{VDD_150, ECC_T, TYPE_UDIMM,  WIDTH_16, RANKS_2, DPC_1, FREQ_1067, DENSITY_2, 0}}, 4, 0x7B, 0xCC, 0x98, 0x6, 0x0A, 0x08},
+  {{{VDD_150, ECC_T, TYPE_UDIMM,  WIDTH_16, RANKS_1, DPC_1, FREQ_1067, DENSITY_4, 0}}, 4, 0x8B, 0xDA, 0xA0, 0x7, 0x0E, 0x07},
+  {{{VDD_150, ECC_T, TYPE_UDIMM,  WIDTH_16, RANKS_2, DPC_1, FREQ_1067, DENSITY_4, 0}}, 4, 0x89, 0xD7, 0x9D, 0x7, 0x0C, 0x0A},
+  {{{VDD_150, ECC_T, TYPE_UDIMM,  WIDTH_8,  RANKS_1, DPC_2, FREQ_1067, DENSITY_2, 0}}, 2, 0x77, 0x8C, 0x24, 0x3, 0x04, 0x0F},
+  {{{VDD_150, ECC_T, TYPE_UDIMM,  WIDTH_8,  RANKS_2, DPC_2, FREQ_1067, DENSITY_2, 0}}, 2, 0x76, 0x8C, 0x24, 0x3, 0x04, 0x17},
+  {{{VDD_150, ECC_T, TYPE_UDIMM,  WIDTH_8,  RANKS_1, DPC_2, FREQ_1067, DENSITY_4, 0}}, 2, 0x7B, 0x90, 0x25, 0x4, 0x05, 0x11},
+  {{{VDD_150, ECC_T, TYPE_UDIMM,  WIDTH_8,  RANKS_2, DPC_2, FREQ_1067, DENSITY_4, 0}}, 2, 0x7A, 0x8F, 0x25, 0x4, 0x05, 0x1B},
+  {{{VDD_150, ECC_T, TYPE_UDIMM,  WIDTH_16, RANKS_1, DPC_2, FREQ_1067, DENSITY_2, 0}}, 2, 0x75, 0x87, 0x26, 0x2, 0x03, 0x0D},
+  {{{VDD_150, ECC_T, TYPE_UDIMM,  WIDTH_16, RANKS_2, DPC_2, FREQ_1067, DENSITY_2, 0}}, 2, 0x74, 0x87, 0x26, 0x2, 0x03, 0x13},
+  {{{VDD_150, ECC_T, TYPE_UDIMM,  WIDTH_16, RANKS_1, DPC_2, FREQ_1067, DENSITY_4, 0}}, 2, 0x78, 0x8A, 0x28, 0x2, 0x03, 0x0D},
+  {{{VDD_150, ECC_T, TYPE_UDIMM,  WIDTH_16, RANKS_2, DPC_2, FREQ_1067, DENSITY_4, 0}}, 2, 0x78, 0x8A, 0x27, 0x2, 0x03, 0x13},
+  {{{VDD_150, ECC_T, TYPE_UDIMM,  WIDTH_8,  RANKS_1, DPC_1, FREQ_1333, DENSITY_2, 0}}, 4, 0x7E, 0xC8, 0x98, 0x9, 0x10, 0x09},
+  {{{VDD_150, ECC_T, TYPE_UDIMM,  WIDTH_8,  RANKS_2, DPC_1, FREQ_1333, DENSITY_2, 0}}, 4, 0x7C, 0xC6, 0x96, 0x9, 0x0E, 0x0D},
+  {{{VDD_150, ECC_T, TYPE_UDIMM,  WIDTH_8,  RANKS_1, DPC_1, FREQ_1333, DENSITY_4, 0}}, 4, 0x8E, 0xD6, 0x9C, 0xB, 0x12, 0x0A},
+  {{{VDD_150, ECC_T, TYPE_UDIMM,  WIDTH_8,  RANKS_2, DPC_1, FREQ_1333, DENSITY_4, 0}}, 4, 0x8C, 0xD4, 0x9A, 0xB, 0x10, 0x0E},
+  {{{VDD_150, ECC_T, TYPE_UDIMM,  WIDTH_16, RANKS_1, DPC_1, FREQ_1333, DENSITY_2, 0}}, 4, 0x77, 0xB6, 0x9A, 0x5, 0x0B, 0x07},
+  {{{VDD_150, ECC_T, TYPE_UDIMM,  WIDTH_16, RANKS_2, DPC_1, FREQ_1333, DENSITY_2, 0}}, 4, 0x75, 0xB4, 0x98, 0x5, 0x09, 0x0A},
+  {{{VDD_150, ECC_T, TYPE_UDIMM,  WIDTH_16, RANKS_1, DPC_1, FREQ_1333, DENSITY_4, 0}}, 4, 0x84, 0xC0, 0x9F, 0x7, 0x0C, 0x08},
+  {{{VDD_150, ECC_T, TYPE_UDIMM,  WIDTH_16, RANKS_2, DPC_1, FREQ_1333, DENSITY_4, 0}}, 4, 0x82, 0xBE, 0x9D, 0x7, 0x0A, 0x0A},
+  {{{VDD_150, ECC_T, TYPE_UDIMM,  WIDTH_8,  RANKS_1, DPC_2, FREQ_1333, DENSITY_2, 0}}, 2, 0x83, 0x92, 0x26, 0x3, 0x04, 0x13},
+  {{{VDD_150, ECC_T, TYPE_UDIMM,  WIDTH_8,  RANKS_2, DPC_2, FREQ_1333, DENSITY_2, 0}}, 2, 0x82, 0x92, 0x26, 0x3, 0x04, 0x1D},
+  {{{VDD_150, ECC_T, TYPE_UDIMM,  WIDTH_8,  RANKS_1, DPC_2, FREQ_1333, DENSITY_4, 0}}, 2, 0x87, 0x96, 0x27, 0x3, 0x05, 0x16},
+  {{{VDD_150, ECC_T, TYPE_UDIMM,  WIDTH_8,  RANKS_2, DPC_2, FREQ_1333, DENSITY_4, 0}}, 2, 0x86, 0x95, 0x27, 0x3, 0x04, 0x1D},
+  {{{VDD_150, ECC_T, TYPE_UDIMM,  WIDTH_16, RANKS_1, DPC_2, FREQ_1333, DENSITY_2, 0}}, 2, 0x81, 0x8E, 0x26, 0x2, 0x03, 0x11},
+  {{{VDD_150, ECC_T, TYPE_UDIMM,  WIDTH_16, RANKS_2, DPC_2, FREQ_1333, DENSITY_2, 0}}, 2, 0x80, 0x8D, 0x26, 0x2, 0x02, 0x13},
+  {{{VDD_150, ECC_T, TYPE_UDIMM,  WIDTH_16, RANKS_1, DPC_2, FREQ_1333, DENSITY_4, 0}}, 2, 0x84, 0x90, 0x28, 0x2, 0x03, 0x11},
+  {{{VDD_150, ECC_T, TYPE_UDIMM,  WIDTH_16, RANKS_2, DPC_2, FREQ_1333, DENSITY_4, 0}}, 2, 0x84, 0x90, 0x27, 0x2, 0x03, 0x18},
+  {{{VDD_150, ECC_T, TYPE_UDIMM,  WIDTH_8,  RANKS_1, DPC_1, FREQ_1600, DENSITY_2, 0}}, 4, 0x7A, 0xB8, 0xA1, 0x8, 0x0E, 0x0A},
+  {{{VDD_150, ECC_T, TYPE_UDIMM,  WIDTH_8,  RANKS_2, DPC_1, FREQ_1600, DENSITY_2, 0}}, 4, 0x79, 0xB6, 0xA0, 0x8, 0x0C, 0x0E},
+  {{{VDD_150, ECC_T, TYPE_UDIMM,  WIDTH_8,  RANKS_1, DPC_1, FREQ_1600, DENSITY_4, 0}}, 4, 0x8A, 0xC5, 0xA5, 0xA, 0x10, 0x0B},
+  {{{VDD_150, ECC_T, TYPE_UDIMM,  WIDTH_8,  RANKS_2, DPC_1, FREQ_1600, DENSITY_4, 0}}, 4, 0x88, 0xC4, 0xA3, 0xA, 0x0F, 0x10},
+  {{{VDD_150, ECC_T, TYPE_UDIMM,  WIDTH_16, RANKS_1, DPC_1, FREQ_1600, DENSITY_2, 0}}, 4, 0x71, 0xA6, 0x9C, 0x5, 0x0A, 0x08},
+  {{{VDD_150, ECC_T, TYPE_UDIMM,  WIDTH_16, RANKS_2, DPC_1, FREQ_1600, DENSITY_2, 0}}, 4, 0x70, 0xA4, 0x9A, 0x5, 0x08, 0x0B},
+  {{{VDD_150, ECC_T, TYPE_UDIMM,  WIDTH_16, RANKS_1, DPC_1, FREQ_1600, DENSITY_4, 0}}, 4, 0x7E, 0xB0, 0xA1, 0x6, 0x0B, 0x09},
+  {{{VDD_150, ECC_T, TYPE_UDIMM,  WIDTH_16, RANKS_2, DPC_1, FREQ_1600, DENSITY_4, 0}}, 4, 0x7C, 0xAE, 0x9F, 0x6, 0x09, 0x0C},
+  {{{VDD_150, ECC_T, TYPE_UDIMM,  WIDTH_8,  RANKS_1, DPC_2, FREQ_1600, DENSITY_2, 0}}, 3, 0xE2, 0xFC, 0x50, 0x4, 0x07, 0x14},
+  {{{VDD_150, ECC_T, TYPE_UDIMM,  WIDTH_8,  RANKS_2, DPC_2, FREQ_1600, DENSITY_2, 0}}, 3, 0xE1, 0xFB, 0x50, 0x4, 0x06, 0x1C},
+  {{{VDD_150, ECC_T, TYPE_UDIMM,  WIDTH_8,  RANKS_1, DPC_2, FREQ_1600, DENSITY_4, 0}}, 2, 0x75, 0x82, 0x29, 0x3, 0x04, 0x16},
+  {{{VDD_150, ECC_T, TYPE_UDIMM,  WIDTH_8,  RANKS_2, DPC_2, FREQ_1600, DENSITY_4, 0}}, 2, 0x75, 0x81, 0x29, 0x3, 0x04, 0x22},
+  {{{VDD_150, ECC_T, TYPE_UDIMM,  WIDTH_16, RANKS_1, DPC_2, FREQ_1600, DENSITY_2, 0}}, 3, 0xDD, 0xF3, 0x4E, 0x3, 0x04, 0x10},
+  {{{VDD_150, ECC_T, TYPE_UDIMM,  WIDTH_16, RANKS_2, DPC_2, FREQ_1600, DENSITY_2, 0}}, 3, 0xDD, 0xF2, 0x4D, 0x3, 0x04, 0x16},
+  {{{VDD_150, ECC_T, TYPE_UDIMM,  WIDTH_16, RANKS_1, DPC_2, FREQ_1600, DENSITY_4, 0}}, 3, 0xE4, 0xF8, 0x50, 0x3, 0x05, 0x12},
+  {{{VDD_150, ECC_T, TYPE_UDIMM,  WIDTH_16, RANKS_2, DPC_2, FREQ_1600, DENSITY_4, 0}}, 3, 0xE3, 0xF7, 0x50, 0x3, 0x05, 0x19},
+  {{{VDD_150, ECC_T, TYPE_UDIMM,  WIDTH_8,  RANKS_1, DPC_1, FREQ_1867, DENSITY_2, 0}}, 4, 0x77, 0xAC, 0xAF, 0x7, 0x0D, 0x0B},
+  {{{VDD_150, ECC_T, TYPE_UDIMM,  WIDTH_8,  RANKS_2, DPC_1, FREQ_1867, DENSITY_2, 0}}, 4, 0x76, 0xAB, 0xAE, 0x7, 0x0C, 0x10},
+  {{{VDD_150, ECC_T, TYPE_UDIMM,  WIDTH_8,  RANKS_1, DPC_1, FREQ_1867, DENSITY_4, 0}}, 4, 0x86, 0xB9, 0xB2, 0x9, 0x0F, 0x0D},
+  {{{VDD_150, ECC_T, TYPE_UDIMM,  WIDTH_8,  RANKS_2, DPC_1, FREQ_1867, DENSITY_4, 0}}, 4, 0x85, 0xB8, 0xB1, 0x9, 0x0E, 0x12},
+  {{{VDD_150, ECC_T, TYPE_UDIMM,  WIDTH_16, RANKS_1, DPC_1, FREQ_1867, DENSITY_2, 0}}, 4, 0x6F, 0x9A, 0xA3, 0x4, 0x09, 0x09},
+  {{{VDD_150, ECC_T, TYPE_UDIMM,  WIDTH_16, RANKS_2, DPC_1, FREQ_1867, DENSITY_2, 0}}, 4, 0x6D, 0x99, 0xA2, 0x4, 0x07, 0x0C},
+  {{{VDD_150, ECC_T, TYPE_UDIMM,  WIDTH_16, RANKS_1, DPC_1, FREQ_1867, DENSITY_4, 0}}, 4, 0x7B, 0xA5, 0xA8, 0x5, 0x0A, 0x0A},
+  {{{VDD_150, ECC_T, TYPE_UDIMM,  WIDTH_16, RANKS_2, DPC_1, FREQ_1867, DENSITY_4, 0}}, 4, 0x7A, 0xA3, 0xA7, 0x5, 0x09, 0x0E},
+  {{{VDD_150, ECC_T, TYPE_UDIMM,  WIDTH_8,  RANKS_1, DPC_2, FREQ_1867, DENSITY_2, 0}}, 3, 0xC9, 0xDF, 0x57, 0x4, 0x06, 0x15},
+  {{{VDD_150, ECC_T, TYPE_UDIMM,  WIDTH_8,  RANKS_2, DPC_2, FREQ_1867, DENSITY_2, 0}}, 3, 0xC8, 0xDF, 0x57, 0x4, 0x06, 0x20},
+  {{{VDD_150, ECC_T, TYPE_UDIMM,  WIDTH_8,  RANKS_1, DPC_2, FREQ_1867, DENSITY_4, 0}}, 3, 0xD0, 0xE6, 0x59, 0x5, 0x07, 0x17},
+  {{{VDD_150, ECC_T, TYPE_UDIMM,  WIDTH_8,  RANKS_2, DPC_2, FREQ_1867, DENSITY_4, 0}}, 3, 0xD0, 0xE5, 0x58, 0x5, 0x07, 0x24},
+  {{{VDD_150, ECC_T, TYPE_UDIMM,  WIDTH_16, RANKS_1, DPC_2, FREQ_1867, DENSITY_2, 0}}, 3, 0xC5, 0xD6, 0x51, 0x2, 0x04, 0x12},
+  {{{VDD_150, ECC_T, TYPE_UDIMM,  WIDTH_16, RANKS_2, DPC_2, FREQ_1867, DENSITY_2, 0}}, 3, 0xC4, 0xD6, 0x51, 0x2, 0x04, 0x19},
+  {{{VDD_150, ECC_T, TYPE_UDIMM,  WIDTH_16, RANKS_1, DPC_2, FREQ_1867, DENSITY_4, 0}}, 3, 0xCB, 0xDB, 0x54, 0x3, 0x05, 0x14},
+  {{{VDD_150, ECC_T, TYPE_UDIMM,  WIDTH_16, RANKS_2, DPC_2, FREQ_1867, DENSITY_4, 0}}, 3, 0xCB, 0xDB, 0x53, 0x3, 0x04, 0x19},
+  {{{VDD_150, ECC_T, TYPE_UDIMM,  WIDTH_8,  RANKS_1, DPC_1, FREQ_2133, DENSITY_2, 0}}, 4, 0x75, 0xA4, 0xBA, 0x7, 0x0C, 0x0D},
+  {{{VDD_150, ECC_T, TYPE_UDIMM,  WIDTH_8,  RANKS_2, DPC_1, FREQ_2133, DENSITY_2, 0}}, 4, 0x74, 0xA2, 0xB9, 0x7, 0x0B, 0x12},
+  {{{VDD_150, ECC_T, TYPE_UDIMM,  WIDTH_8,  RANKS_1, DPC_1, FREQ_2133, DENSITY_4, 0}}, 4, 0x84, 0xB0, 0xBC, 0x9, 0x0E, 0x0E},
+  {{{VDD_150, ECC_T, TYPE_UDIMM,  WIDTH_8,  RANKS_2, DPC_1, FREQ_2133, DENSITY_4, 0}}, 4, 0x83, 0xAF, 0xBB, 0x9, 0x0D, 0x14},
+  {{{VDD_150, ECC_T, TYPE_UDIMM,  WIDTH_16, RANKS_1, DPC_1, FREQ_2133, DENSITY_2, 0}}, 4, 0x6C, 0x92, 0xA7, 0x4, 0x08, 0x0A},
+  {{{VDD_150, ECC_T, TYPE_UDIMM,  WIDTH_16, RANKS_2, DPC_1, FREQ_2133, DENSITY_2, 0}}, 4, 0x6A, 0x91, 0xA6, 0x4, 0x07, 0x0D},
+  {{{VDD_150, ECC_T, TYPE_UDIMM,  WIDTH_16, RANKS_1, DPC_1, FREQ_2133, DENSITY_4, 0}}, 4, 0x78, 0x9C, 0xAC, 0x5, 0x09, 0x0B},
+  {{{VDD_150, ECC_T, TYPE_UDIMM,  WIDTH_16, RANKS_2, DPC_1, FREQ_2133, DENSITY_4, 0}}, 4, 0x77, 0x9B, 0xAB, 0x5, 0x08, 0x0E},
+  {{{VDD_150, ECC_T, TYPE_UDIMM,  WIDTH_8,  RANKS_1, DPC_2, FREQ_2133, DENSITY_2, 0}}, 3, 0xB6, 0xCA, 0x5D, 0x4, 0x06, 0x18},
+  {{{VDD_150, ECC_T, TYPE_UDIMM,  WIDTH_8,  RANKS_2, DPC_2, FREQ_2133, DENSITY_2, 0}}, 3, 0xB6, 0xC9, 0x5C, 0x4, 0x06, 0x24},
+  {{{VDD_150, ECC_T, TYPE_UDIMM,  WIDTH_8,  RANKS_1, DPC_2, FREQ_2133, DENSITY_4, 0}}, 3, 0xBE, 0xD0, 0x5E, 0x5, 0x07, 0x1A},
+  {{{VDD_150, ECC_T, TYPE_UDIMM,  WIDTH_8,  RANKS_2, DPC_2, FREQ_2133, DENSITY_4, 0}}, 3, 0xBD, 0xD0, 0x5E, 0x5, 0x06, 0x24},
+  {{{VDD_150, ECC_T, TYPE_UDIMM,  WIDTH_16, RANKS_1, DPC_2, FREQ_2133, DENSITY_2, 0}}, 3, 0xB1, 0xC1, 0x53, 0x2, 0x04, 0x13},
+  {{{VDD_150, ECC_T, TYPE_UDIMM,  WIDTH_16, RANKS_2, DPC_2, FREQ_2133, DENSITY_2, 0}}, 3, 0xB1, 0xC1, 0x53, 0x2, 0x03, 0x17},
+  {{{VDD_150, ECC_T, TYPE_UDIMM,  WIDTH_16, RANKS_1, DPC_2, FREQ_2133, DENSITY_4, 0}}, 3, 0xB8, 0xC6, 0x56, 0x3, 0x04, 0x14},
+  {{{VDD_150, ECC_T, TYPE_UDIMM,  WIDTH_16, RANKS_2, DPC_2, FREQ_2133, DENSITY_4, 0}}, 3, 0xB7, 0xC6, 0x55, 0x3, 0x04, 0x1C},
+  {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_8,  RANKS_1, DPC_1, FREQ_1067, DENSITY_2, 0}}, 4, 0x56, 0xA3, 0x69, 0x7, 0x0D, 0x07},
+  {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_8,  RANKS_2, DPC_1, FREQ_1067, DENSITY_2, 0}}, 4, 0x54, 0xDD, 0x67, 0x7, 0x0B, 0x09},
+  {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_8,  RANKS_1, DPC_1, FREQ_1067, DENSITY_4, 0}}, 4, 0x61, 0xAD, 0x6C, 0x9, 0x10, 0x08},
+  {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_8,  RANKS_2, DPC_1, FREQ_1067, DENSITY_4, 0}}, 4, 0x5F, 0xE7, 0x6A, 0x9, 0x0E, 0x0B},
+  {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_1, DPC_1, FREQ_1067, DENSITY_2, 0}}, 4, 0x4A, 0x8F, 0x65, 0x4, 0x09, 0x06},
+  {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_2, DPC_1, FREQ_1067, DENSITY_2, 0}}, 4, 0x48, 0xC9, 0x63, 0x4, 0x07, 0x07},
+  {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_1, DPC_1, FREQ_1067, DENSITY_4, 0}}, 4, 0x53, 0x96, 0x69, 0x5, 0x0A, 0x06},
+  {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_2, DPC_1, FREQ_1067, DENSITY_4, 0}}, 4, 0x51, 0xD0, 0x67, 0x5, 0x08, 0x08},
+  {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_8,  RANKS_1, DPC_2, FREQ_1067, DENSITY_2, 0}}, 3, 0x81, 0xA4, 0x34, 0x4, 0x06, 0x0E},
+  {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_8,  RANKS_2, DPC_2, FREQ_1067, DENSITY_2, 0}}, 3, 0x80, 0xA3, 0x33, 0x4, 0x06, 0x14},
+  {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_8,  RANKS_1, DPC_2, FREQ_1067, DENSITY_4, 0}}, 3, 0x87, 0xA9, 0x36, 0x5, 0x07, 0x10},
+  {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_8,  RANKS_2, DPC_2, FREQ_1067, DENSITY_4, 0}}, 3, 0x86, 0xA8, 0x35, 0x5, 0x07, 0x16},
+  {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_1, DPC_2, FREQ_1067, DENSITY_2, 0}}, 3, 0x7B, 0x9A, 0x32, 0x2, 0x04, 0x0C},
+  {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_2, DPC_2, FREQ_1067, DENSITY_2, 0}}, 3, 0x7A, 0x99, 0x31, 0x2, 0x03, 0x0E},
+  {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_1, DPC_2, FREQ_1067, DENSITY_4, 0}}, 3, 0x7F, 0x9D, 0x34, 0x3, 0x05, 0x0D},
+  {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_2, DPC_2, FREQ_1067, DENSITY_4, 0}}, 3, 0x7F, 0x9D, 0x33, 0x3, 0x04, 0x10},
+  {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_8,  RANKS_1, DPC_1, FREQ_1333, DENSITY_2, 0}}, 4, 0x53, 0x91, 0x6E, 0x6, 0x0C, 0x08},
+  {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_8,  RANKS_2, DPC_1, FREQ_1333, DENSITY_2, 0}}, 4, 0x51, 0x8F, 0x6D, 0x6, 0x0A, 0x0B},
+  {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_8,  RANKS_1, DPC_1, FREQ_1333, DENSITY_4, 0}}, 4, 0x5E, 0x9B, 0x71, 0x8, 0x0E, 0x09},
+  {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_8,  RANKS_2, DPC_1, FREQ_1333, DENSITY_4, 0}}, 4, 0x5C, 0x99, 0x6F, 0x8, 0x0C, 0x0C},
+  {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_1, DPC_1, FREQ_1333, DENSITY_2, 0}}, 5, 0x8D, 0xF9, 0xC9, 0x7, 0x0F, 0x06},
+  {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_2, DPC_1, FREQ_1333, DENSITY_2, 0}}, 5, 0x8A, 0xF6, 0xC5, 0x7, 0x0C, 0x08},
+  {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_1, DPC_1, FREQ_1333, DENSITY_4, 0}}, 4, 0x4F, 0x84, 0x68, 0x4, 0x09, 0x07},
+  {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_2, DPC_1, FREQ_1333, DENSITY_4, 0}}, 4, 0x4E, 0x82, 0x66, 0x4, 0x07, 0x09},
+  {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_8,  RANKS_1, DPC_2, FREQ_1333, DENSITY_2, 0}}, 3, 0x6E, 0x8A, 0x37, 0x3, 0x05, 0x0F},
+  {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_8,  RANKS_2, DPC_2, FREQ_1333, DENSITY_2, 0}}, 3, 0x6E, 0x8A, 0x36, 0x3, 0x05, 0x16},
+  {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_8,  RANKS_1, DPC_2, FREQ_1333, DENSITY_4, 0}}, 3, 0x74, 0x8F, 0x38, 0x4, 0x06, 0x11},
+  {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_8,  RANKS_2, DPC_2, FREQ_1333, DENSITY_4, 0}}, 3, 0x74, 0x8F, 0x38, 0x4, 0x06, 0x18},
+  {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_1, DPC_2, FREQ_1333, DENSITY_2, 0}}, 3, 0x68, 0x80, 0x32, 0x2, 0x04, 0x0E},
+  {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_2, DPC_2, FREQ_1333, DENSITY_2, 0}}, 4, 0xCF, 0xFF, 0x62, 0x4, 0x06, 0x10},
+  {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_1, DPC_2, FREQ_1333, DENSITY_4, 0}}, 3, 0x6D, 0x84, 0x34, 0x2, 0x04, 0x0E},
+  {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_2, DPC_2, FREQ_1333, DENSITY_4, 0}}, 3, 0x6C, 0x83, 0x33, 0x2, 0x04, 0x13},
+  {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_8,  RANKS_1, DPC_1, FREQ_1600, DENSITY_2, 0}}, 4, 0x5D, 0xCD, 0x75, 0x6, 0x0B, 0x0A},
+  {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_8,  RANKS_2, DPC_1, FREQ_1600, DENSITY_2, 0}}, 4, 0x5B, 0xCB, 0x73, 0x6, 0x09, 0x0D},
+  {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_8,  RANKS_1, DPC_1, FREQ_1600, DENSITY_4, 0}}, 4, 0x68, 0xD6, 0x77, 0x7, 0x0C, 0x0B},
+  {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_8,  RANKS_2, DPC_1, FREQ_1600, DENSITY_4, 0}}, 4, 0x66, 0xD5, 0x76, 0x7, 0x0B, 0x0E},
+  {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_1, DPC_1, FREQ_1600, DENSITY_2, 0}}, 4, 0x50, 0xB9, 0x66, 0x3, 0x07, 0x08},
+  {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_2, DPC_1, FREQ_1600, DENSITY_2, 0}}, 4, 0x4E, 0xB8, 0x65, 0x3, 0x06, 0x0A},
+  {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_1, DPC_1, FREQ_1600, DENSITY_4, 0}}, 4, 0x58, 0xC0, 0x69, 0x4, 0x08, 0x09},
+  {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_2, DPC_1, FREQ_1600, DENSITY_4, 0}}, 4, 0x57, 0xBE, 0x68, 0x4, 0x07, 0x0B},
+  {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_8,  RANKS_1, DPC_2, FREQ_1600, DENSITY_2, 0}}, 3, 0x73, 0xA7, 0x3A, 0x3, 0x05, 0x13},
+  {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_8,  RANKS_2, DPC_2, FREQ_1600, DENSITY_2, 0}}, 3, 0x73, 0xA6, 0x3A, 0x3, 0x05, 0x1A},
+  {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_8,  RANKS_1, DPC_2, FREQ_1600, DENSITY_4, 0}}, 3, 0x79, 0xAB, 0x3B, 0x4, 0x06, 0x15},
+  {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_8,  RANKS_2, DPC_2, FREQ_1600, DENSITY_4, 0}}, 3, 0x79, 0xAB, 0x3B, 0x4, 0x05, 0x1B},
+  {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_1, DPC_2, FREQ_1600, DENSITY_2, 0}}, 3, 0x6D, 0x9D, 0x33, 0x2, 0x03, 0x0F},
+  {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_2, DPC_2, FREQ_1600, DENSITY_2, 0}}, 3, 0x6D, 0x9C, 0x32, 0x2, 0x03, 0x14},
+  {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_1, DPC_2, FREQ_1600, DENSITY_4, 0}}, 3, 0x71, 0xA0, 0x34, 0x2, 0x04, 0x11},
+  {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_2, DPC_2, FREQ_1600, DENSITY_4, 0}}, 3, 0x71, 0xA0, 0x34, 0x2, 0x03, 0x14},
+  {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_8,  RANKS_1, DPC_1, FREQ_1867, DENSITY_2, 0}}, 4, 0x5A, 0xBA, 0x7F, 0x5, 0x0A, 0x0B},
+  {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_8,  RANKS_2, DPC_1, FREQ_1867, DENSITY_2, 0}}, 4, 0x59, 0xB9, 0x7E, 0x5, 0x09, 0x0F},
+  {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_8,  RANKS_1, DPC_1, FREQ_1867, DENSITY_4, 0}}, 4, 0x65, 0xC3, 0x81, 0x7, 0x0B, 0x0C},
+  {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_8,  RANKS_2, DPC_1, FREQ_1867, DENSITY_4, 0}}, 4, 0x64, 0xC2, 0x80, 0x7, 0x0A, 0x10},
+  {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_1, DPC_1, FREQ_1867, DENSITY_2, 0}}, 4, 0x4D, 0xA7, 0x6B, 0x3, 0x06, 0x09},
+  {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_2, DPC_1, FREQ_1867, DENSITY_2, 0}}, 4, 0x4C, 0xA6, 0x69, 0x3, 0x05, 0x0A},
+  {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_1, DPC_1, FREQ_1867, DENSITY_4, 0}}, 4, 0x55, 0xAD, 0x6E, 0x4, 0x07, 0x09},
+  {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_2, DPC_1, FREQ_1867, DENSITY_4, 0}}, 4, 0x54, 0xAC, 0x6C, 0x4, 0x06, 0x0C},
+  {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_8,  RANKS_1, DPC_2, FREQ_1867, DENSITY_2, 0}}, 3, 0x68, 0x94, 0x3F, 0x3, 0x05, 0x15},
+  {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_8,  RANKS_2, DPC_2, FREQ_1867, DENSITY_2, 0}}, 3, 0x68, 0x94, 0x3F, 0x3, 0x04, 0x1B},
+  {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_8,  RANKS_1, DPC_2, FREQ_1867, DENSITY_4, 0}}, 3, 0x6E, 0x99, 0x40, 0x4, 0x05, 0x16},
+  {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_8,  RANKS_2, DPC_2, FREQ_1867, DENSITY_4, 0}}, 3, 0x6D, 0x98, 0x40, 0x4, 0x05, 0x1E},
+  {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_1, DPC_2, FREQ_1867, DENSITY_2, 0}}, 3, 0x62, 0x8A, 0x35, 0x2, 0x03, 0x11},
+  {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_2, DPC_2, FREQ_1867, DENSITY_2, 0}}, 3, 0x62, 0x8A, 0x35, 0x2, 0x03, 0x16},
+  {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_1, DPC_2, FREQ_1867, DENSITY_4, 0}}, 3, 0x66, 0x8E, 0x37, 0x2, 0x03, 0x11},
+  {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_2, DPC_2, FREQ_1867, DENSITY_4, 0}}, 3, 0x66, 0x8D, 0x36, 0x2, 0x03, 0x17},
+  {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_8,  RANKS_1, DPC_1, FREQ_2133, DENSITY_2, 0}}, 4, 0x58, 0xAC, 0x86, 0x5, 0x09, 0x0C},
+  {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_8,  RANKS_2, DPC_1, FREQ_2133, DENSITY_2, 0}}, 4, 0x57, 0xAB, 0x85, 0x5, 0x08, 0x10},
+  {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_8,  RANKS_1, DPC_1, FREQ_2133, DENSITY_4, 0}}, 4, 0x63, 0xB5, 0x88, 0x6, 0x0B, 0x0E},
+  {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_8,  RANKS_2, DPC_1, FREQ_2133, DENSITY_4, 0}}, 4, 0x62, 0xB4, 0x87, 0x6, 0x0A, 0x12},
+  {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_1, DPC_1, FREQ_2133, DENSITY_2, 0}}, 4, 0x4A, 0x99, 0x6D, 0x3, 0x06, 0x0A},
+  {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_2, DPC_1, FREQ_2133, DENSITY_2, 0}}, 4, 0x49, 0x98, 0x6C, 0x3, 0x05, 0x0C},
+  {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_1, DPC_1, FREQ_2133, DENSITY_4, 0}}, 4, 0x53, 0x9F, 0x70, 0x4, 0x07, 0x0B},
+  {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_2, DPC_1, FREQ_2133, DENSITY_4, 0}}, 4, 0x52, 0x9E, 0x6F, 0x4, 0x06, 0x0D},
+  {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_8,  RANKS_1, DPC_2, FREQ_2133, DENSITY_2, 0}}, 3, 0x60, 0x86, 0x43, 0x3, 0x04, 0x16},
+  {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_8,  RANKS_2, DPC_2, FREQ_2133, DENSITY_2, 0}}, 3, 0x60, 0x86, 0x43, 0x3, 0x04, 0x1D},
+  {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_8,  RANKS_1, DPC_2, FREQ_2133, DENSITY_4, 0}}, 3, 0x65, 0x8B, 0x44, 0x3, 0x05, 0x18},
+  {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_8,  RANKS_2, DPC_2, FREQ_2133, DENSITY_4, 0}}, 3, 0x65, 0x8B, 0x44, 0x3, 0x05, 0x22},
+  {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_1, DPC_2, FREQ_2133, DENSITY_2, 0}}, 4, 0xB2, 0xF9, 0x6C, 0x3, 0x05, 0x11},
+  {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_2, DPC_2, FREQ_2133, DENSITY_2, 0}}, 4, 0xB1, 0xF8, 0x6C, 0x3, 0x05, 0x16},
+  {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_1, DPC_2, FREQ_2133, DENSITY_4, 0}}, 4, 0xBA, 0xFF, 0x6F, 0x4, 0x06, 0x13},
+  {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_2, DPC_2, FREQ_2133, DENSITY_4, 0}}, 4, 0xB9, 0xFF, 0x6F, 0x4, 0x05, 0x17},
+  {{{VDD_135, ECC_F, TYPE_UDIMM,  WIDTH_8,  RANKS_1, DPC_1, FREQ_1067, DENSITY_2, 0}}, 4, 0x63, 0xA3, 0x69, 0x7, 0x0D, 0x07},
+  {{{VDD_135, ECC_F, TYPE_UDIMM,  WIDTH_8,  RANKS_2, DPC_1, FREQ_1067, DENSITY_2, 0}}, 4, 0x61, 0xA1, 0x67, 0x7, 0x0B, 0x09},
+  {{{VDD_135, ECC_F, TYPE_UDIMM,  WIDTH_8,  RANKS_1, DPC_1, FREQ_1067, DENSITY_4, 0}}, 4, 0x6E, 0xAD, 0x6C, 0x9, 0x10, 0x08},
+  {{{VDD_135, ECC_F, TYPE_UDIMM,  WIDTH_8,  RANKS_2, DPC_1, FREQ_1067, DENSITY_4, 0}}, 4, 0x6C, 0xAB, 0x6A, 0x9, 0x0E, 0x0B},
+  {{{VDD_135, ECC_F, TYPE_UDIMM,  WIDTH_16, RANKS_1, DPC_1, FREQ_1067, DENSITY_2, 0}}, 4, 0x57, 0x8F, 0x65, 0x4, 0x09, 0x06},
+  {{{VDD_135, ECC_F, TYPE_UDIMM,  WIDTH_16, RANKS_2, DPC_1, FREQ_1067, DENSITY_2, 0}}, 4, 0x55, 0x8D, 0x63, 0x4, 0x07, 0x07},
+  {{{VDD_135, ECC_F, TYPE_UDIMM,  WIDTH_16, RANKS_1, DPC_1, FREQ_1067, DENSITY_4, 0}}, 4, 0x5F, 0x96, 0x68, 0x5, 0x0A, 0x06},
+  {{{VDD_135, ECC_F, TYPE_UDIMM,  WIDTH_16, RANKS_2, DPC_1, FREQ_1067, DENSITY_4, 0}}, 4, 0x5D, 0x94, 0x67, 0x5, 0x08, 0x08},
+  {{{VDD_135, ECC_F, TYPE_UDIMM,  WIDTH_8,  RANKS_1, DPC_2, FREQ_1067, DENSITY_2, 0}}, 3, 0x99, 0xBC, 0x34, 0x4, 0x06, 0x10},
+  {{{VDD_135, ECC_F, TYPE_UDIMM,  WIDTH_8,  RANKS_2, DPC_2, FREQ_1067, DENSITY_2, 0}}, 3, 0x99, 0xBC, 0x33, 0x4, 0x06, 0x16},
+  {{{VDD_135, ECC_F, TYPE_UDIMM,  WIDTH_8,  RANKS_1, DPC_2, FREQ_1067, DENSITY_4, 0}}, 3, 0x9F, 0xC1, 0x36, 0x5, 0x07, 0x11},
+  {{{VDD_135, ECC_F, TYPE_UDIMM,  WIDTH_8,  RANKS_2, DPC_2, FREQ_1067, DENSITY_4, 0}}, 3, 0x9E, 0xC1, 0x35, 0x5, 0x07, 0x18},
+  {{{VDD_135, ECC_F, TYPE_UDIMM,  WIDTH_16, RANKS_1, DPC_2, FREQ_1067, DENSITY_2, 0}}, 3, 0x93, 0xB2, 0x32, 0x2, 0x04, 0x0D},
+  {{{VDD_135, ECC_F, TYPE_UDIMM,  WIDTH_16, RANKS_2, DPC_2, FREQ_1067, DENSITY_2, 0}}, 3, 0x93, 0xB1, 0x31, 0x2, 0x03, 0x0F},
+  {{{VDD_135, ECC_F, TYPE_UDIMM,  WIDTH_16, RANKS_1, DPC_2, FREQ_1067, DENSITY_4, 0}}, 3, 0x98, 0xB6, 0x34, 0x3, 0x05, 0x0F},
+  {{{VDD_135, ECC_F, TYPE_UDIMM,  WIDTH_16, RANKS_2, DPC_2, FREQ_1067, DENSITY_4, 0}}, 3, 0x97, 0xB5, 0x33, 0x3, 0x04, 0x12},
+  {{{VDD_135, ECC_F, TYPE_UDIMM,  WIDTH_8,  RANKS_1, DPC_1, FREQ_1333, DENSITY_2, 0}}, 4, 0x5D, 0x91, 0x6E, 0x6, 0x0C, 0x08},
+  {{{VDD_135, ECC_F, TYPE_UDIMM,  WIDTH_8,  RANKS_2, DPC_1, FREQ_1333, DENSITY_2, 0}}, 4, 0x5B, 0x8F, 0x6D, 0x6, 0x0A, 0x0B},
+  {{{VDD_135, ECC_F, TYPE_UDIMM,  WIDTH_8,  RANKS_1, DPC_1, FREQ_1333, DENSITY_4, 0}}, 4, 0x68, 0x9B, 0x71, 0x8, 0x0E, 0x09},
+  {{{VDD_135, ECC_F, TYPE_UDIMM,  WIDTH_8,  RANKS_2, DPC_1, FREQ_1333, DENSITY_4, 0}}, 4, 0x67, 0x99, 0x6F, 0x8, 0x0C, 0x0D},
+  {{{VDD_135, ECC_F, TYPE_UDIMM,  WIDTH_16, RANKS_1, DPC_1, FREQ_1333, DENSITY_2, 0}}, 5, 0xA2, 0xF9, 0xC8, 0x7, 0x0F, 0x07},
+  {{{VDD_135, ECC_F, TYPE_UDIMM,  WIDTH_16, RANKS_2, DPC_1, FREQ_1333, DENSITY_2, 0}}, 5, 0x9E, 0xF6, 0xC5, 0x7, 0x0C, 0x08},
+  {{{VDD_135, ECC_F, TYPE_UDIMM,  WIDTH_16, RANKS_1, DPC_1, FREQ_1333, DENSITY_4, 0}}, 4, 0x5A, 0x84, 0x68, 0x4, 0x09, 0x07},
+  {{{VDD_135, ECC_F, TYPE_UDIMM,  WIDTH_16, RANKS_2, DPC_1, FREQ_1333, DENSITY_4, 0}}, 4, 0x58, 0x82, 0x66, 0x4, 0x07, 0x09},
+  {{{VDD_135, ECC_F, TYPE_UDIMM,  WIDTH_8,  RANKS_1, DPC_2, FREQ_1333, DENSITY_2, 0}}, 3, 0x82, 0x9E, 0x37, 0x3, 0x05, 0x11},
+  {{{VDD_135, ECC_F, TYPE_UDIMM,  WIDTH_8,  RANKS_2, DPC_2, FREQ_1333, DENSITY_2, 0}}, 3, 0x81, 0x9D, 0x36, 0x3, 0x05, 0x17},
+  {{{VDD_135, ECC_F, TYPE_UDIMM,  WIDTH_8,  RANKS_1, DPC_2, FREQ_1333, DENSITY_4, 0}}, 3, 0x88, 0xA3, 0x38, 0x4, 0x06, 0x12},
+  {{{VDD_135, ECC_F, TYPE_UDIMM,  WIDTH_8,  RANKS_2, DPC_2, FREQ_1333, DENSITY_4, 0}}, 3, 0x87, 0xA2, 0x38, 0x4, 0x06, 0x1A},
+  {{{VDD_135, ECC_F, TYPE_UDIMM,  WIDTH_16, RANKS_1, DPC_2, FREQ_1333, DENSITY_2, 0}}, 3, 0x7C, 0x94, 0x32, 0x2, 0x03, 0x0E},
+  {{{VDD_135, ECC_F, TYPE_UDIMM,  WIDTH_16, RANKS_2, DPC_2, FREQ_1333, DENSITY_2, 0}}, 3, 0x7B, 0x93, 0x31, 0x2, 0x03, 0x12},
+  {{{VDD_135, ECC_F, TYPE_UDIMM,  WIDTH_16, RANKS_1, DPC_2, FREQ_1333, DENSITY_4, 0}}, 3, 0x80, 0x97, 0x34, 0x2, 0x04, 0x0F},
+  {{{VDD_135, ECC_F, TYPE_UDIMM,  WIDTH_16, RANKS_2, DPC_2, FREQ_1333, DENSITY_4, 0}}, 3, 0x80, 0x97, 0x33, 0x2, 0x04, 0x14},
+  {{{VDD_135, ECC_F, TYPE_UDIMM,  WIDTH_8,  RANKS_1, DPC_1, FREQ_1600, DENSITY_2, 0}}, 4, 0x63, 0xAA, 0x74, 0x6, 0x0B, 0x0A},
+  {{{VDD_135, ECC_F, TYPE_UDIMM,  WIDTH_8,  RANKS_2, DPC_1, FREQ_1600, DENSITY_2, 0}}, 4, 0x62, 0xA9, 0x73, 0x6, 0x09, 0x0D},
+  {{{VDD_135, ECC_F, TYPE_UDIMM,  WIDTH_8,  RANKS_1, DPC_1, FREQ_1600, DENSITY_4, 0}}, 4, 0x6F, 0xB4, 0x77, 0x7, 0x0C, 0x0B},
+  {{{VDD_135, ECC_F, TYPE_UDIMM,  WIDTH_8,  RANKS_2, DPC_1, FREQ_1600, DENSITY_4, 0}}, 4, 0x6D, 0xB2, 0x76, 0x7, 0x0B, 0x0F},
+  {{{VDD_135, ECC_F, TYPE_UDIMM,  WIDTH_16, RANKS_1, DPC_1, FREQ_1600, DENSITY_2, 0}}, 4, 0x56, 0x96, 0x66, 0x3, 0x07, 0x08},
+  {{{VDD_135, ECC_F, TYPE_UDIMM,  WIDTH_16, RANKS_2, DPC_1, FREQ_1600, DENSITY_2, 0}}, 4, 0x55, 0x95, 0x64, 0x3, 0x06, 0x0A},
+  {{{VDD_135, ECC_F, TYPE_UDIMM,  WIDTH_16, RANKS_1, DPC_1, FREQ_1600, DENSITY_4, 0}}, 4, 0x5F, 0x9D, 0x69, 0x4, 0x08, 0x09},
+  {{{VDD_135, ECC_F, TYPE_UDIMM,  WIDTH_16, RANKS_2, DPC_1, FREQ_1600, DENSITY_4, 0}}, 4, 0x5D, 0x9C, 0x68, 0x4, 0x07, 0x0B},
+  {{{VDD_135, ECC_F, TYPE_UDIMM,  WIDTH_8,  RANKS_1, DPC_2, FREQ_1600, DENSITY_2, 0}}, 3, 0x73, 0x97, 0x3A, 0x3, 0x05, 0x13},
+  {{{VDD_135, ECC_F, TYPE_UDIMM,  WIDTH_8,  RANKS_2, DPC_2, FREQ_1600, DENSITY_2, 0}}, 3, 0x73, 0x96, 0x3A, 0x3, 0x05, 0x1A},
+  {{{VDD_135, ECC_F, TYPE_UDIMM,  WIDTH_8,  RANKS_1, DPC_2, FREQ_1600, DENSITY_4, 0}}, 3, 0x79, 0x9C, 0x3B, 0x4, 0x06, 0x15},
+  {{{VDD_135, ECC_F, TYPE_UDIMM,  WIDTH_8,  RANKS_2, DPC_2, FREQ_1600, DENSITY_4, 0}}, 3, 0x78, 0x9B, 0x3B, 0x4, 0x05, 0x1B},
+  {{{VDD_135, ECC_F, TYPE_UDIMM,  WIDTH_16, RANKS_1, DPC_2, FREQ_1600, DENSITY_2, 0}}, 3, 0x6D, 0x8D, 0x33, 0x2, 0x03, 0x0F},
+  {{{VDD_135, ECC_F, TYPE_UDIMM,  WIDTH_16, RANKS_2, DPC_2, FREQ_1600, DENSITY_2, 0}}, 3, 0x6C, 0x8D, 0x32, 0x2, 0x03, 0x14},
+  {{{VDD_135, ECC_F, TYPE_UDIMM,  WIDTH_16, RANKS_1, DPC_2, FREQ_1600, DENSITY_4, 0}}, 3, 0x71, 0x90, 0x34, 0x2, 0x04, 0x11},
+  {{{VDD_135, ECC_F, TYPE_UDIMM,  WIDTH_16, RANKS_2, DPC_2, FREQ_1600, DENSITY_4, 0}}, 3, 0x70, 0x90, 0x34, 0x2, 0x03, 0x14},
+  {{{VDD_135, ECC_F, TYPE_UDIMM,  WIDTH_8,  RANKS_1, DPC_1, FREQ_1867, DENSITY_2, 0}}, 4, 0x60, 0x9C, 0x7F, 0x5, 0x0A, 0x0B},
+  {{{VDD_135, ECC_F, TYPE_UDIMM,  WIDTH_8,  RANKS_2, DPC_1, FREQ_1867, DENSITY_2, 0}}, 4, 0x5F, 0x9B, 0x7E, 0x5, 0x09, 0x0F},
+  {{{VDD_135, ECC_F, TYPE_UDIMM,  WIDTH_8,  RANKS_1, DPC_1, FREQ_1867, DENSITY_4, 0}}, 4, 0x6B, 0xA6, 0x81, 0x7, 0x0B, 0x0C},
+  {{{VDD_135, ECC_F, TYPE_UDIMM,  WIDTH_8,  RANKS_2, DPC_1, FREQ_1867, DENSITY_4, 0}}, 4, 0x6A, 0xA5, 0x80, 0x7, 0x0A, 0x10},
+  {{{VDD_135, ECC_F, TYPE_UDIMM,  WIDTH_16, RANKS_1, DPC_1, FREQ_1867, DENSITY_2, 0}}, 4, 0x53, 0x89, 0x6A, 0x3, 0x06, 0x09},
+  {{{VDD_135, ECC_F, TYPE_UDIMM,  WIDTH_16, RANKS_2, DPC_1, FREQ_1867, DENSITY_2, 0}}, 4, 0x52, 0x88, 0x69, 0x3, 0x05, 0x0B},
+  {{{VDD_135, ECC_F, TYPE_UDIMM,  WIDTH_16, RANKS_1, DPC_1, FREQ_1867, DENSITY_4, 0}}, 4, 0x5B, 0x90, 0x6D, 0x4, 0x07, 0x0A},
+  {{{VDD_135, ECC_F, TYPE_UDIMM,  WIDTH_16, RANKS_2, DPC_1, FREQ_1867, DENSITY_4, 0}}, 4, 0x5A, 0x8F, 0x6C, 0x4, 0x06, 0x0C},
+  {{{VDD_135, ECC_F, TYPE_UDIMM,  WIDTH_8,  RANKS_1, DPC_2, FREQ_1867, DENSITY_2, 0}}, 3, 0x68, 0x87, 0x3F, 0x3, 0x05, 0x15},
+  {{{VDD_135, ECC_F, TYPE_UDIMM,  WIDTH_8,  RANKS_2, DPC_2, FREQ_1867, DENSITY_2, 0}}, 3, 0x68, 0x86, 0x3F, 0x3, 0x04, 0x1A},
+  {{{VDD_135, ECC_F, TYPE_UDIMM,  WIDTH_8,  RANKS_1, DPC_2, FREQ_1867, DENSITY_4, 0}}, 3, 0x6D, 0x8B, 0x40, 0x4, 0x05, 0x16},
+  {{{VDD_135, ECC_F, TYPE_UDIMM,  WIDTH_8,  RANKS_2, DPC_2, FREQ_1867, DENSITY_4, 0}}, 3, 0x6D, 0x8B, 0x40, 0x4, 0x05, 0x1E},
+  {{{VDD_135, ECC_F, TYPE_UDIMM,  WIDTH_16, RANKS_1, DPC_2, FREQ_1867, DENSITY_2, 0}}, 4, 0xC3, 0xF9, 0x6A, 0x3, 0x05, 0x10},
+  {{{VDD_135, ECC_F, TYPE_UDIMM,  WIDTH_16, RANKS_2, DPC_2, FREQ_1867, DENSITY_2, 0}}, 4, 0xC2, 0xF9, 0x69, 0x3, 0x05, 0x14},
+  {{{VDD_135, ECC_F, TYPE_UDIMM,  WIDTH_16, RANKS_1, DPC_2, FREQ_1867, DENSITY_4, 0}}, 3, 0x66, 0x80, 0x37, 0x2, 0x03, 0x11},
+  {{{VDD_135, ECC_F, TYPE_UDIMM,  WIDTH_16, RANKS_2, DPC_2, FREQ_1867, DENSITY_4, 0}}, 4, 0xCA, 0xFF, 0x6C, 0x4, 0x06, 0x16},
+  {{{VDD_135, ECC_F, TYPE_UDIMM,  WIDTH_8,  RANKS_1, DPC_1, FREQ_2133, DENSITY_2, 0}}, 4, 0x5D, 0x92, 0x86, 0x5, 0x09, 0x0C},
+  {{{VDD_135, ECC_F, TYPE_UDIMM,  WIDTH_8,  RANKS_2, DPC_1, FREQ_2133, DENSITY_2, 0}}, 4, 0x5C, 0x91, 0x85, 0x5, 0x08, 0x10},
+  {{{VDD_135, ECC_F, TYPE_UDIMM,  WIDTH_8,  RANKS_1, DPC_1, FREQ_2133, DENSITY_4, 0}}, 4, 0x68, 0x9B, 0x88, 0x6, 0x0B, 0x0E},
+  {{{VDD_135, ECC_F, TYPE_UDIMM,  WIDTH_8,  RANKS_2, DPC_1, FREQ_2133, DENSITY_4, 0}}, 4, 0x67, 0x9A, 0x87, 0x6, 0x0A, 0x12},
+  {{{VDD_135, ECC_F, TYPE_UDIMM,  WIDTH_16, RANKS_1, DPC_1, FREQ_2133, DENSITY_2, 0}}, 5, 0x9F, 0xFD, 0xDA, 0x5, 0x0B, 0x0A},
+  {{{VDD_135, ECC_F, TYPE_UDIMM,  WIDTH_16, RANKS_2, DPC_1, FREQ_2133, DENSITY_2, 0}}, 5, 0x9D, 0xFB, 0xD8, 0x5, 0x09, 0x0B},
+  {{{VDD_135, ECC_F, TYPE_UDIMM,  WIDTH_16, RANKS_1, DPC_1, FREQ_2133, DENSITY_4, 0}}, 4, 0x58, 0x85, 0x70, 0x4, 0x07, 0x0B},
+  {{{VDD_135, ECC_F, TYPE_UDIMM,  WIDTH_16, RANKS_2, DPC_1, FREQ_2133, DENSITY_4, 0}}, 4, 0x57, 0x84, 0x6F, 0x4, 0x06, 0x0D},
+  {{{VDD_135, ECC_F, TYPE_UDIMM,  WIDTH_8,  RANKS_1, DPC_2, FREQ_2133, DENSITY_2, 0}}, 4, 0xBF, 0xF4, 0x85, 0x5, 0x08, 0x15},
+  {{{VDD_135, ECC_F, TYPE_UDIMM,  WIDTH_8,  RANKS_2, DPC_2, FREQ_2133, DENSITY_2, 0}}, 4, 0xBE, 0xF4, 0x85, 0x5, 0x08, 0x1D},
+  {{{VDD_135, ECC_F, TYPE_UDIMM,  WIDTH_8,  RANKS_1, DPC_2, FREQ_2133, DENSITY_4, 0}}, 4, 0xCA, 0xFE, 0x87, 0x6, 0x0A, 0x18},
+  {{{VDD_135, ECC_F, TYPE_UDIMM,  WIDTH_8,  RANKS_2, DPC_2, FREQ_2133, DENSITY_4, 0}}, 4, 0xC9, 0xFD, 0x87, 0x6, 0x09, 0x20},
+  {{{VDD_135, ECC_F, TYPE_UDIMM,  WIDTH_16, RANKS_1, DPC_2, FREQ_2133, DENSITY_2, 0}}, 4, 0xB1, 0xE1, 0x6C, 0x3, 0x05, 0x11},
+  {{{VDD_135, ECC_F, TYPE_UDIMM,  WIDTH_16, RANKS_2, DPC_2, FREQ_2133, DENSITY_2, 0}}, 4, 0xB1, 0xE1, 0x6C, 0x3, 0x05, 0x16},
+  {{{VDD_135, ECC_F, TYPE_UDIMM,  WIDTH_16, RANKS_1, DPC_2, FREQ_2133, DENSITY_4, 0}}, 4, 0xB9, 0xE8, 0x6F, 0x4, 0x06, 0x13},
+  {{{VDD_135, ECC_F, TYPE_UDIMM,  WIDTH_16, RANKS_2, DPC_2, FREQ_2133, DENSITY_4, 0}}, 4, 0xB9, 0xE7, 0x6F, 0x4, 0x05, 0x17},
+  {{{VDD_135, ECC_T, TYPE_UDIMM,  WIDTH_8,  RANKS_1, DPC_1, FREQ_1067, DENSITY_2, 0}}, 4, 0x6E, 0xB7, 0x76, 0x8, 0x0E, 0x06},
+  {{{VDD_135, ECC_T, TYPE_UDIMM,  WIDTH_8,  RANKS_2, DPC_1, FREQ_1067, DENSITY_2, 0}}, 4, 0x6C, 0xB5, 0x74, 0x8, 0x0C, 0x09},
+  {{{VDD_135, ECC_T, TYPE_UDIMM,  WIDTH_8,  RANKS_1, DPC_1, FREQ_1067, DENSITY_4, 0}}, 4, 0x7B, 0xC2, 0x79, 0xA, 0x11, 0x07},
+  {{{VDD_135, ECC_T, TYPE_UDIMM,  WIDTH_8,  RANKS_2, DPC_1, FREQ_1067, DENSITY_4, 0}}, 4, 0x79, 0xC0, 0x77, 0xA, 0x0F, 0x0A},
+  {{{VDD_135, ECC_T, TYPE_UDIMM,  WIDTH_16, RANKS_1, DPC_1, FREQ_1067, DENSITY_2, 0}}, 4, 0x68, 0xA7, 0x7D, 0x5, 0x0A, 0x05},
+  {{{VDD_135, ECC_T, TYPE_UDIMM,  WIDTH_16, RANKS_2, DPC_1, FREQ_1067, DENSITY_2, 0}}, 4, 0x66, 0xA5, 0x7B, 0x5, 0x08, 0x07},
+  {{{VDD_135, ECC_T, TYPE_UDIMM,  WIDTH_16, RANKS_1, DPC_1, FREQ_1067, DENSITY_4, 0}}, 4, 0x73, 0xB0, 0x81, 0x6, 0x0C, 0x06},
+  {{{VDD_135, ECC_T, TYPE_UDIMM,  WIDTH_16, RANKS_2, DPC_1, FREQ_1067, DENSITY_4, 0}}, 4, 0x71, 0xAF, 0x7F, 0x6, 0x0A, 0x08},
+  {{{VDD_135, ECC_T, TYPE_UDIMM,  WIDTH_8,  RANKS_1, DPC_2, FREQ_1067, DENSITY_2, 0}}, 3, 0xC0, 0xE3, 0x3A, 0x4, 0x07, 0x0D},
+  {{{VDD_135, ECC_T, TYPE_UDIMM,  WIDTH_8,  RANKS_2, DPC_2, FREQ_1067, DENSITY_2, 0}}, 3, 0xBF, 0xE2, 0x3A, 0x4, 0x06, 0x12},
+  {{{VDD_135, ECC_T, TYPE_UDIMM,  WIDTH_8,  RANKS_1, DPC_2, FREQ_1067, DENSITY_4, 0}}, 3, 0xC6, 0xE8, 0x3C, 0x5, 0x08, 0x0E},
+  {{{VDD_135, ECC_T, TYPE_UDIMM,  WIDTH_8,  RANKS_2, DPC_2, FREQ_1067, DENSITY_4, 0}}, 3, 0xC6, 0xE8, 0x3B, 0x5, 0x07, 0x14},
+  {{{VDD_135, ECC_T, TYPE_UDIMM,  WIDTH_16, RANKS_1, DPC_2, FREQ_1067, DENSITY_2, 0}}, 3, 0xBD, 0xDB, 0x3E, 0x3, 0x04, 0x0A},
+  {{{VDD_135, ECC_T, TYPE_UDIMM,  WIDTH_16, RANKS_2, DPC_2, FREQ_1067, DENSITY_2, 0}}, 3, 0xBC, 0xDA, 0x3D, 0x3, 0x04, 0x0E},
+  {{{VDD_135, ECC_T, TYPE_UDIMM,  WIDTH_16, RANKS_1, DPC_2, FREQ_1067, DENSITY_4, 0}}, 3, 0xC2, 0xDF, 0x40, 0x3, 0x05, 0x0B},
+  {{{VDD_135, ECC_T, TYPE_UDIMM,  WIDTH_16, RANKS_2, DPC_2, FREQ_1067, DENSITY_4, 0}}, 3, 0xC2, 0xDF, 0x40, 0x3, 0x05, 0x10},
+  {{{VDD_135, ECC_T, TYPE_UDIMM,  WIDTH_8,  RANKS_1, DPC_1, FREQ_1333, DENSITY_2, 0}}, 4, 0x68, 0xA2, 0x7B, 0x7, 0x0D, 0x07},
+  {{{VDD_135, ECC_T, TYPE_UDIMM,  WIDTH_8,  RANKS_2, DPC_1, FREQ_1333, DENSITY_2, 0}}, 4, 0x66, 0xA1, 0x7A, 0x7, 0x0B, 0x0A},
+  {{{VDD_135, ECC_T, TYPE_UDIMM,  WIDTH_8,  RANKS_1, DPC_1, FREQ_1333, DENSITY_4, 0}}, 4, 0x75, 0xAE, 0x7E, 0x9, 0x0F, 0x08},
+  {{{VDD_135, ECC_T, TYPE_UDIMM,  WIDTH_8,  RANKS_2, DPC_1, FREQ_1333, DENSITY_4, 0}}, 4, 0x73, 0xAC, 0x7D, 0x9, 0x0D, 0x0C},
+  {{{VDD_135, ECC_T, TYPE_UDIMM,  WIDTH_16, RANKS_1, DPC_1, FREQ_1333, DENSITY_2, 0}}, 4, 0x62, 0x93, 0x7D, 0x4, 0x09, 0x06},
+  {{{VDD_135, ECC_T, TYPE_UDIMM,  WIDTH_16, RANKS_2, DPC_1, FREQ_1333, DENSITY_2, 0}}, 4, 0x61, 0x92, 0x7B, 0x4, 0x07, 0x08},
+  {{{VDD_135, ECC_T, TYPE_UDIMM,  WIDTH_16, RANKS_1, DPC_1, FREQ_1333, DENSITY_4, 0}}, 4, 0x6D, 0x9C, 0x81, 0x5, 0x0A, 0x07},
+  {{{VDD_135, ECC_T, TYPE_UDIMM,  WIDTH_16, RANKS_2, DPC_1, FREQ_1333, DENSITY_4, 0}}, 4, 0x6B, 0x9A, 0x7F, 0x5, 0x08, 0x09},
+  {{{VDD_135, ECC_T, TYPE_UDIMM,  WIDTH_8,  RANKS_1, DPC_2, FREQ_1333, DENSITY_2, 0}}, 3, 0xD3, 0xED, 0x3D, 0x4, 0x06, 0x0F},
+  {{{VDD_135, ECC_T, TYPE_UDIMM,  WIDTH_8,  RANKS_2, DPC_2, FREQ_1333, DENSITY_2, 0}}, 3, 0xD3, 0xEC, 0x3D, 0x4, 0x05, 0x14},
+  {{{VDD_135, ECC_T, TYPE_UDIMM,  WIDTH_8,  RANKS_1, DPC_2, FREQ_1333, DENSITY_4, 0}}, 3, 0xDA, 0xF2, 0x3F, 0x5, 0x07, 0x10},
+  {{{VDD_135, ECC_T, TYPE_UDIMM,  WIDTH_8,  RANKS_2, DPC_2, FREQ_1333, DENSITY_4, 0}}, 3, 0xD9, 0xF2, 0x3E, 0x5, 0x07, 0x19},
+  {{{VDD_135, ECC_T, TYPE_UDIMM,  WIDTH_16, RANKS_1, DPC_2, FREQ_1333, DENSITY_2, 0}}, 3, 0xD0, 0xE5, 0x3E, 0x2, 0x04, 0x0D},
+  {{{VDD_135, ECC_T, TYPE_UDIMM,  WIDTH_16, RANKS_2, DPC_2, FREQ_1333, DENSITY_2, 0}}, 3, 0xD0, 0xE5, 0x3D, 0x2, 0x04, 0x11},
+  {{{VDD_135, ECC_T, TYPE_UDIMM,  WIDTH_16, RANKS_1, DPC_2, FREQ_1333, DENSITY_4, 0}}, 3, 0xD6, 0xE9, 0x40, 0x3, 0x05, 0x0E},
+  {{{VDD_135, ECC_T, TYPE_UDIMM,  WIDTH_16, RANKS_2, DPC_2, FREQ_1333, DENSITY_4, 0}}, 3, 0xD5, 0xE9, 0x40, 0x3, 0x04, 0x12},
+  {{{VDD_135, ECC_T, TYPE_UDIMM,  WIDTH_8,  RANKS_1, DPC_1, FREQ_1600, DENSITY_2, 0}}, 4, 0x64, 0x95, 0x83, 0x6, 0x0B, 0x08},
+  {{{VDD_135, ECC_T, TYPE_UDIMM,  WIDTH_8,  RANKS_2, DPC_1, FREQ_1600, DENSITY_2, 0}}, 4, 0x63, 0x94, 0x81, 0x6, 0x0A, 0x0B},
+  {{{VDD_135, ECC_T, TYPE_UDIMM,  WIDTH_8,  RANKS_1, DPC_1, FREQ_1600, DENSITY_4, 0}}, 4, 0x71, 0xA0, 0x85, 0x8, 0x0D, 0x09},
+  {{{VDD_135, ECC_T, TYPE_UDIMM,  WIDTH_8,  RANKS_2, DPC_1, FREQ_1600, DENSITY_4, 0}}, 4, 0x70, 0x9F, 0x84, 0x8, 0x0C, 0x0D},
+  {{{VDD_135, ECC_T, TYPE_UDIMM,  WIDTH_16, RANKS_1, DPC_1, FREQ_1600, DENSITY_2, 0}}, 4, 0x5D, 0x86, 0x7E, 0x4, 0x08, 0x07},
+  {{{VDD_135, ECC_T, TYPE_UDIMM,  WIDTH_16, RANKS_2, DPC_1, FREQ_1600, DENSITY_2, 0}}, 4, 0x5C, 0x85, 0x7D, 0x4, 0x07, 0x09},
+  {{{VDD_135, ECC_T, TYPE_UDIMM,  WIDTH_16, RANKS_1, DPC_1, FREQ_1600, DENSITY_4, 0}}, 4, 0x68, 0x8F, 0x82, 0x5, 0x09, 0x07},
+  {{{VDD_135, ECC_T, TYPE_UDIMM,  WIDTH_16, RANKS_2, DPC_1, FREQ_1600, DENSITY_4, 0}}, 4, 0x66, 0x8D, 0x81, 0x5, 0x08, 0x0A},
+  {{{VDD_135, ECC_T, TYPE_UDIMM,  WIDTH_8,  RANKS_1, DPC_2, FREQ_1600, DENSITY_2, 0}}, 3, 0xB7, 0xCC, 0x41, 0x3, 0x05, 0x10},
+  {{{VDD_135, ECC_T, TYPE_UDIMM,  WIDTH_8,  RANKS_2, DPC_2, FREQ_1600, DENSITY_2, 0}}, 3, 0xB7, 0xCC, 0x41, 0x3, 0x05, 0x17},
+  {{{VDD_135, ECC_T, TYPE_UDIMM,  WIDTH_8,  RANKS_1, DPC_2, FREQ_1600, DENSITY_4, 0}}, 3, 0xBD, 0xD2, 0x42, 0x4, 0x06, 0x11},
+  {{{VDD_135, ECC_T, TYPE_UDIMM,  WIDTH_8,  RANKS_2, DPC_2, FREQ_1600, DENSITY_4, 0}}, 3, 0xBD, 0xD1, 0x42, 0x4, 0x06, 0x1A},
+  {{{VDD_135, ECC_T, TYPE_UDIMM,  WIDTH_16, RANKS_1, DPC_2, FREQ_1600, DENSITY_2, 0}}, 3, 0xB3, 0xC5, 0x3F, 0x2, 0x04, 0x0E},
+  {{{VDD_135, ECC_T, TYPE_UDIMM,  WIDTH_16, RANKS_2, DPC_2, FREQ_1600, DENSITY_2, 0}}, 3, 0xB3, 0xC4, 0x3F, 0x2, 0x03, 0x11},
+  {{{VDD_135, ECC_T, TYPE_UDIMM,  WIDTH_16, RANKS_1, DPC_2, FREQ_1600, DENSITY_4, 0}}, 3, 0xB9, 0xC9, 0x41, 0x3, 0x04, 0x0E},
+  {{{VDD_135, ECC_T, TYPE_UDIMM,  WIDTH_16, RANKS_2, DPC_2, FREQ_1600, DENSITY_4, 0}}, 3, 0xB8, 0xC9, 0x41, 0x3, 0x04, 0x14},
+  {{{VDD_135, ECC_T, TYPE_UDIMM,  WIDTH_8,  RANKS_1, DPC_1, FREQ_1867, DENSITY_2, 0}}, 4, 0x62, 0x8C, 0x8E, 0x6, 0x0B, 0x0A},
+  {{{VDD_135, ECC_T, TYPE_UDIMM,  WIDTH_8,  RANKS_2, DPC_1, FREQ_1867, DENSITY_2, 0}}, 4, 0x61, 0x8A, 0x8D, 0x6, 0x0A, 0x0D},
+  {{{VDD_135, ECC_T, TYPE_UDIMM,  WIDTH_8,  RANKS_1, DPC_1, FREQ_1867, DENSITY_4, 0}}, 4, 0x6E, 0x96, 0x90, 0x8, 0x0C, 0x0A},
+  {{{VDD_135, ECC_T, TYPE_UDIMM,  WIDTH_8,  RANKS_2, DPC_1, FREQ_1867, DENSITY_4, 0}}, 4, 0x6D, 0x95, 0x8F, 0x8, 0x0B, 0x0F},
+  {{{VDD_135, ECC_T, TYPE_UDIMM,  WIDTH_16, RANKS_1, DPC_1, FREQ_1867, DENSITY_2, 0}}, 4, 0x5B, 0x7D, 0x84, 0x4, 0x07, 0x08},
+  {{{VDD_135, ECC_T, TYPE_UDIMM,  WIDTH_16, RANKS_2, DPC_1, FREQ_1867, DENSITY_2, 0}}, 4, 0x5A, 0x7C, 0x83, 0x4, 0x06, 0x0A},
+  {{{VDD_135, ECC_T, TYPE_UDIMM,  WIDTH_16, RANKS_1, DPC_1, FREQ_1867, DENSITY_4, 0}}, 4, 0x65, 0x85, 0x88, 0x5, 0x08, 0x08},
+  {{{VDD_135, ECC_T, TYPE_UDIMM,  WIDTH_16, RANKS_2, DPC_1, FREQ_1867, DENSITY_4, 0}}, 4, 0x64, 0x84, 0x87, 0x5, 0x07, 0x0B},
+  {{{VDD_135, ECC_T, TYPE_UDIMM,  WIDTH_8,  RANKS_1, DPC_2, FREQ_1867, DENSITY_2, 0}}, 3, 0xA3, 0xB5, 0x47, 0x3, 0x05, 0x12},
+  {{{VDD_135, ECC_T, TYPE_UDIMM,  WIDTH_8,  RANKS_2, DPC_2, FREQ_1867, DENSITY_2, 0}}, 3, 0xA2, 0xB5, 0x47, 0x3, 0x05, 0x1A},
+  {{{VDD_135, ECC_T, TYPE_UDIMM,  WIDTH_8,  RANKS_1, DPC_2, FREQ_1867, DENSITY_4, 0}}, 3, 0xA9, 0xBA, 0x48, 0x4, 0x06, 0x14},
+  {{{VDD_135, ECC_T, TYPE_UDIMM,  WIDTH_8,  RANKS_2, DPC_2, FREQ_1867, DENSITY_4, 0}}, 3, 0xA9, 0xBA, 0x48, 0x4, 0x06, 0x1E},
+  {{{VDD_135, ECC_T, TYPE_UDIMM,  WIDTH_16, RANKS_1, DPC_2, FREQ_1867, DENSITY_2, 0}}, 3, 0x9F, 0xAE, 0x42, 0x2, 0x03, 0x0E},
+  {{{VDD_135, ECC_T, TYPE_UDIMM,  WIDTH_16, RANKS_2, DPC_2, FREQ_1867, DENSITY_2, 0}}, 3, 0x9F, 0xAD, 0x42, 0x2, 0x03, 0x13},
+  {{{VDD_135, ECC_T, TYPE_UDIMM,  WIDTH_16, RANKS_1, DPC_2, FREQ_1867, DENSITY_4, 0}}, 3, 0xA4, 0xB2, 0x44, 0x3, 0x04, 0x10},
+  {{{VDD_135, ECC_T, TYPE_UDIMM,  WIDTH_16, RANKS_2, DPC_2, FREQ_1867, DENSITY_4, 0}}, 3, 0xA4, 0xB2, 0x44, 0x3, 0x04, 0x17},
+  {{{VDD_135, ECC_T, TYPE_UDIMM,  WIDTH_8,  RANKS_1, DPC_1, FREQ_2133, DENSITY_2, 0}}, 4, 0x60, 0x85, 0x97, 0x6, 0x0A, 0x0B},
+  {{{VDD_135, ECC_T, TYPE_UDIMM,  WIDTH_8,  RANKS_2, DPC_1, FREQ_2133, DENSITY_2, 0}}, 4, 0x5F, 0x84, 0x96, 0x6, 0x09, 0x0E},
+  {{{VDD_135, ECC_T, TYPE_UDIMM,  WIDTH_8,  RANKS_1, DPC_1, FREQ_2133, DENSITY_4, 0}}, 4, 0x6C, 0x8F, 0x99, 0x7, 0x0C, 0x0C},
+  {{{VDD_135, ECC_T, TYPE_UDIMM,  WIDTH_8,  RANKS_2, DPC_1, FREQ_2133, DENSITY_4, 0}}, 4, 0x6B, 0x8E, 0x98, 0x7, 0x0B, 0x11},
+  {{{VDD_135, ECC_T, TYPE_UDIMM,  WIDTH_16, RANKS_1, DPC_1, FREQ_2133, DENSITY_2, 0}}, 4, 0x58, 0x76, 0x88, 0x3, 0x07, 0x09},
+  {{{VDD_135, ECC_T, TYPE_UDIMM,  WIDTH_16, RANKS_2, DPC_1, FREQ_2133, DENSITY_2, 0}}, 4, 0x57, 0x75, 0x87, 0x3, 0x06, 0x0B},
+  {{{VDD_135, ECC_T, TYPE_UDIMM,  WIDTH_16, RANKS_1, DPC_1, FREQ_2133, DENSITY_4, 0}}, 4, 0x62, 0x7E, 0x8B, 0x4, 0x08, 0x09},
+  {{{VDD_135, ECC_T, TYPE_UDIMM,  WIDTH_16, RANKS_2, DPC_1, FREQ_2133, DENSITY_4, 0}}, 4, 0x61, 0x7D, 0x8A, 0x4, 0x07, 0x0C},
+  {{{VDD_135, ECC_T, TYPE_UDIMM,  WIDTH_8,  RANKS_1, DPC_2, FREQ_2133, DENSITY_2, 0}}, 3, 0x94, 0xA4, 0x4B, 0x3, 0x05, 0x14},
+  {{{VDD_135, ECC_T, TYPE_UDIMM,  WIDTH_8,  RANKS_2, DPC_2, FREQ_2133, DENSITY_2, 0}}, 3, 0x93, 0xA3, 0x4B, 0x3, 0x05, 0x1E},
+  {{{VDD_135, ECC_T, TYPE_UDIMM,  WIDTH_8,  RANKS_1, DPC_2, FREQ_2133, DENSITY_4, 0}}, 3, 0x9A, 0xA9, 0x4C, 0x4, 0x06, 0x16},
+  {{{VDD_135, ECC_T, TYPE_UDIMM,  WIDTH_8,  RANKS_2, DPC_2, FREQ_2133, DENSITY_4, 0}}, 3, 0x99, 0xA8, 0x4C, 0x4, 0x05, 0x1E},
+  {{{VDD_135, ECC_T, TYPE_UDIMM,  WIDTH_16, RANKS_1, DPC_2, FREQ_2133, DENSITY_2, 0}}, 3, 0x90, 0x9C, 0x44, 0x2, 0x03, 0x0F},
+  {{{VDD_135, ECC_T, TYPE_UDIMM,  WIDTH_16, RANKS_2, DPC_2, FREQ_2133, DENSITY_2, 0}}, 3, 0x8F, 0x9C, 0x43, 0x2, 0x03, 0x15},
+  {{{VDD_135, ECC_T, TYPE_UDIMM,  WIDTH_16, RANKS_1, DPC_2, FREQ_2133, DENSITY_4, 0}}, 3, 0x95, 0xA0, 0x45, 0x2, 0x04, 0x11},
+  {{{VDD_135, ECC_T, TYPE_UDIMM,  WIDTH_16, RANKS_2, DPC_2, FREQ_2133, DENSITY_4, 0}}, 3, 0x95, 0xA0, 0x45, 0x2, 0x03, 0x16},
+  {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_8,  RANKS_2, DPC_1, FREQ_1067, DENSITY_1, 0}}, 3, 0x5A, 0xAD, 0xCC, 0x8, 0x0E, 0x17},
+  {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_8,  RANKS_1, DPC_1, FREQ_1067, DENSITY_1, 0}}, 3, 0x5B, 0x8A, 0xCD, 0x8, 0x10, 0x11},
+  {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_8,  RANKS_2, DPC_2, FREQ_1067, DENSITY_1, 0}}, 3, 0xC5, 0xEE, 0xCB, 0x8, 0x0E, 0x2B},
+  {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_8,  RANKS_1, DPC_2, FREQ_1067, DENSITY_1, 0}}, 3, 0xC5, 0xEF, 0xCC, 0x8, 0x0F, 0x1E},
+  {{{VDD_150, ECC_F, TYPE_UDIMM,  WIDTH_8,  RANKS_2, DPC_1, FREQ_1067, DENSITY_1, 0}}, 3, 0x61, 0x88, 0xCC, 0x8, 0x0E, 0x17},
+  {{{VDD_150, ECC_F, TYPE_UDIMM,  WIDTH_8,  RANKS_1, DPC_1, FREQ_1067, DENSITY_1, 0}}, 3, 0x62, 0x8A, 0xCD, 0x8, 0x10, 0x11},
+  {{{VDD_150, ECC_F, TYPE_UDIMM,  WIDTH_8,  RANKS_2, DPC_2, FREQ_1067, DENSITY_1, 0}}, 2, 0x72, 0x86, 0x66, 0x4, 0x07, 0x2C},
+  {{{VDD_150, ECC_F, TYPE_UDIMM,  WIDTH_8,  RANKS_1, DPC_2, FREQ_1067, DENSITY_1, 0}}, 2, 0x72, 0x87, 0x66, 0x4, 0x08, 0x20},
+  {{{VDD_150, ECC_T, TYPE_UDIMM,  WIDTH_8,  RANKS_2, DPC_1, FREQ_1067, DENSITY_1, 0}}, 3, 0x6D, 0x99, 0xE5, 0x9, 0x10, 0x17},
+  {{{VDD_150, ECC_T, TYPE_UDIMM,  WIDTH_8,  RANKS_1, DPC_1, FREQ_1067, DENSITY_1, 0}}, 3, 0x6E, 0x9A, 0xE6, 0x9, 0x11, 0x10},
+  {{{VDD_150, ECC_T, TYPE_UDIMM,  WIDTH_8,  RANKS_2, DPC_2, FREQ_1067, DENSITY_1, 0}}, 2, 0x8C, 0xA0, 0x73, 0x5, 0x08, 0x2B},
+  {{{VDD_150, ECC_T, TYPE_UDIMM,  WIDTH_8,  RANKS_1, DPC_2, FREQ_1067, DENSITY_1, 0}}, 2, 0x8C, 0xA1, 0x73, 0x5, 0x08, 0x1B},
+  {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_2, DPC_1, FREQ_1067, DENSITY_1, 0}}, 3, 0x40, 0x97, 0x62, 0x5, 0x08, 0x0E},
+  {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_1, DPC_1, FREQ_1067, DENSITY_1, 0}}, 4, 0x83, 0xE7, 0xC5, 0x9, 0x12, 0x0A},
+  {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_2, DPC_2, FREQ_1067, DENSITY_1, 0}}, 3, 0xAB, 0xD8, 0x61, 0x5, 0x08, 0x1B},
+  {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_1, DPC_2, FREQ_1067, DENSITY_1, 0}}, 3, 0xAC, 0xD9, 0x62, 0x5, 0x08, 0x14},
+  {{{VDD_150, ECC_F, TYPE_UDIMM,  WIDTH_16, RANKS_2, DPC_1, FREQ_1067, DENSITY_1, 0}}, 4, 0x8E, 0xE4, 0xC3, 0x9, 0x10, 0x0E},
+  {{{VDD_150, ECC_F, TYPE_UDIMM,  WIDTH_16, RANKS_1, DPC_1, FREQ_1067, DENSITY_1, 0}}, 4, 0x90, 0xE6, 0xC5, 0x9, 0x12, 0x0B},
+  {{{VDD_150, ECC_F, TYPE_UDIMM,  WIDTH_16, RANKS_2, DPC_2, FREQ_1067, DENSITY_1, 0}}, 3, 0xC9, 0xF6, 0x61, 0x5, 0x08, 0x1D},
+  {{{VDD_150, ECC_F, TYPE_UDIMM,  WIDTH_16, RANKS_1, DPC_2, FREQ_1067, DENSITY_1, 0}}, 3, 0xCA, 0xF7, 0x62, 0x5, 0x08, 0x15},
+  {{{VDD_150, ECC_T, TYPE_UDIMM,  WIDTH_16, RANKS_2, DPC_1, FREQ_1067, DENSITY_1, 0}}, 3, 0x57, 0x88, 0x7A, 0x6, 0x0A, 0x0F},
+  {{{VDD_150, ECC_T, TYPE_UDIMM,  WIDTH_16, RANKS_1, DPC_1, FREQ_1067, DENSITY_1, 0}}, 3, 0x58, 0x8A, 0x7B, 0x6, 0x0B, 0x0A},
+  {{{VDD_150, ECC_T, TYPE_UDIMM,  WIDTH_16, RANKS_2, DPC_2, FREQ_1067, DENSITY_1, 0}}, 2, 0x81, 0x98, 0x3D, 0x3, 0x05, 0x1C},
+  {{{VDD_150, ECC_T, TYPE_UDIMM,  WIDTH_16, RANKS_1, DPC_2, FREQ_1067, DENSITY_1, 0}}, 2, 0x81, 0x98, 0x3D, 0x3, 0x05, 0x12},
+  {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_8,  RANKS_2, DPC_1, FREQ_1333, DENSITY_1, 0}}, 3, 0x58, 0x76, 0xA8, 0x8, 0x0D, 0x1A},
+  {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_8,  RANKS_1, DPC_1, FREQ_1333, DENSITY_1, 0}}, 3, 0x59, 0x77, 0xA9, 0x8, 0x0E, 0x13},
+  {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_8,  RANKS_2, DPC_2, FREQ_1333, DENSITY_1, 0}}, 3, 0xAD, 0xC8, 0xA8, 0x8, 0x0C, 0x2E},
+  {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_8,  RANKS_1, DPC_2, FREQ_1333, DENSITY_1, 0}}, 3, 0xAD, 0xC8, 0xA9, 0x8, 0x0D, 0x20},
+  {{{VDD_150, ECC_F, TYPE_UDIMM,  WIDTH_8,  RANKS_2, DPC_1, FREQ_1333, DENSITY_1, 0}}, 3, 0x5D, 0x76, 0xA8, 0x8, 0x0D, 0x1A},
+  {{{VDD_150, ECC_F, TYPE_UDIMM,  WIDTH_8,  RANKS_1, DPC_1, FREQ_1333, DENSITY_1, 0}}, 3, 0x5E, 0x77, 0xA9, 0x8, 0x0E, 0x13},
+  {{{VDD_150, ECC_F, TYPE_UDIMM,  WIDTH_8,  RANKS_2, DPC_2, FREQ_1333, DENSITY_1, 0}}, 3, 0xC5, 0xE0, 0xA8, 0x8, 0x0C, 0x2F},
+  {{{VDD_150, ECC_F, TYPE_UDIMM,  WIDTH_8,  RANKS_1, DPC_2, FREQ_1333, DENSITY_1, 0}}, 3, 0xC5, 0xE0, 0xA9, 0x8, 0x0D, 0x22},
+  {{{VDD_150, ECC_T, TYPE_UDIMM,  WIDTH_8,  RANKS_2, DPC_1, FREQ_1333, DENSITY_1, 0}}, 3, 0x68, 0x85, 0xBD, 0x8, 0x0E, 0x19},
+  {{{VDD_150, ECC_T, TYPE_UDIMM,  WIDTH_8,  RANKS_1, DPC_1, FREQ_1333, DENSITY_1, 0}}, 3, 0x69, 0x86, 0xBE, 0x8, 0x0F, 0x11},
+  {{{VDD_150, ECC_T, TYPE_UDIMM,  WIDTH_8,  RANKS_2, DPC_2, FREQ_1333, DENSITY_1, 0}}, 2, 0x97, 0xA3, 0x5F, 0x4, 0x07, 0x30},
+  {{{VDD_150, ECC_T, TYPE_UDIMM,  WIDTH_8,  RANKS_1, DPC_2, FREQ_1333, DENSITY_1, 0}}, 2, 0x98, 0xA3, 0x5F, 0x4, 0x07, 0x1E},
+  {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_2, DPC_1, FREQ_1333, DENSITY_1, 0}}, 4, 0x83, 0xCA, 0xC7, 0x8, 0x0E, 0x10},
+  {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_1, DPC_1, FREQ_1333, DENSITY_1, 0}}, 4, 0x85, 0xCC, 0xC9, 0x8, 0x10, 0x0C},
+  {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_2, DPC_2, FREQ_1333, DENSITY_1, 0}}, 3, 0x97, 0xB6, 0x63, 0x4, 0x07, 0x1E},
+  {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_1, DPC_2, FREQ_1333, DENSITY_1, 0}}, 3, 0x97, 0xB7, 0x64, 0x4, 0x07, 0x16},
+  {{{VDD_150, ECC_F, TYPE_UDIMM,  WIDTH_16, RANKS_2, DPC_1, FREQ_1333, DENSITY_1, 0}}, 4, 0x8E, 0xCA, 0xC7, 0x8, 0x0E, 0x10},
+  {{{VDD_150, ECC_F, TYPE_UDIMM,  WIDTH_16, RANKS_1, DPC_1, FREQ_1333, DENSITY_1, 0}}, 4, 0x8F, 0xCB, 0xC9, 0x8, 0x10, 0x0C},
+  {{{VDD_150, ECC_F, TYPE_UDIMM,  WIDTH_16, RANKS_2, DPC_2, FREQ_1333, DENSITY_1, 0}}, 3, 0xAF, 0xCF, 0x63, 0x4, 0x07, 0x20},
+  {{{VDD_150, ECC_F, TYPE_UDIMM,  WIDTH_16, RANKS_1, DPC_2, FREQ_1333, DENSITY_1, 0}}, 3, 0xB0, 0xCF, 0x64, 0x4, 0x07, 0x17},
+  {{{VDD_150, ECC_T, TYPE_UDIMM,  WIDTH_16, RANKS_2, DPC_1, FREQ_1333, DENSITY_1, 0}}, 4, 0xAE, 0xF2, 0xF8, 0x9, 0x10, 0x10},
+  {{{VDD_150, ECC_T, TYPE_UDIMM,  WIDTH_16, RANKS_1, DPC_1, FREQ_1333, DENSITY_1, 0}}, 4, 0xB0, 0xF4, 0xFA, 0x9, 0x12, 0x0C},
+  {{{VDD_150, ECC_T, TYPE_UDIMM,  WIDTH_16, RANKS_2, DPC_2, FREQ_1333, DENSITY_1, 0}}, 2, 0x8F, 0x9D, 0x3E, 0x3, 0x04, 0x1F},
+  {{{VDD_150, ECC_T, TYPE_UDIMM,  WIDTH_16, RANKS_1, DPC_2, FREQ_1333, DENSITY_1, 0}}, 2, 0x8F, 0x9D, 0x3F, 0x3, 0x05, 0x17},
+  {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_8,  RANKS_2, DPC_1, FREQ_1600, DENSITY_1, 0}}, 3, 0x5D, 0x97, 0x94, 0x6, 0x0B, 0x1C},
+  {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_8,  RANKS_1, DPC_1, FREQ_1600, DENSITY_1, 0}}, 3, 0x5E, 0x98, 0x95, 0x6, 0x0C, 0x15},
+  {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_8,  RANKS_2, DPC_2, FREQ_1600, DENSITY_1, 0}}, 3, 0xB2, 0xE7, 0x93, 0x6, 0x0B, 0x34},
+  {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_8,  RANKS_1, DPC_2, FREQ_1600, DENSITY_1, 0}}, 3, 0xB3, 0xE7, 0x94, 0x6, 0x0B, 0x23},
+  {{{VDD_150, ECC_F, TYPE_UDIMM,  WIDTH_8,  RANKS_2, DPC_1, FREQ_1600, DENSITY_1, 0}}, 3, 0x60, 0x82, 0x94, 0x6, 0x0B, 0x1D},
+  {{{VDD_150, ECC_F, TYPE_UDIMM,  WIDTH_8,  RANKS_1, DPC_1, FREQ_1600, DENSITY_1, 0}}, 3, 0x61, 0x83, 0x95, 0x6, 0x0C, 0x15},
+  {{{VDD_150, ECC_F, TYPE_UDIMM,  WIDTH_8,  RANKS_2, DPC_2, FREQ_1600, DENSITY_1, 0}}, 3, 0xB2, 0xD3, 0x93, 0x6, 0x0B, 0x34},
+  {{{VDD_150, ECC_F, TYPE_UDIMM,  WIDTH_8,  RANKS_1, DPC_2, FREQ_1600, DENSITY_1, 0}}, 3, 0xB2, 0xD4, 0x94, 0x6, 0x0B, 0x23},
+  {{{VDD_150, ECC_T, TYPE_UDIMM,  WIDTH_8,  RANKS_2, DPC_1, FREQ_1600, DENSITY_1, 0}}, 3, 0x65, 0x78, 0xA6, 0x7, 0x0C, 0x1A},
+  {{{VDD_150, ECC_T, TYPE_UDIMM,  WIDTH_8,  RANKS_1, DPC_1, FREQ_1600, DENSITY_1, 0}}, 3, 0x66, 0x79, 0xA7, 0x7, 0x0D, 0x12},
+  {{{VDD_150, ECC_T, TYPE_UDIMM,  WIDTH_8,  RANKS_2, DPC_2, FREQ_1600, DENSITY_1, 0}}, 2, 0x85, 0x8C, 0x53, 0x4, 0x06, 0x31},
+  {{{VDD_150, ECC_T, TYPE_UDIMM,  WIDTH_8,  RANKS_1, DPC_2, FREQ_1600, DENSITY_1, 0}}, 2, 0x86, 0x8C, 0x53, 0x4, 0x06, 0x1F},
+  {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_2, DPC_1, FREQ_1600, DENSITY_1, 0}}, 3, 0x47, 0x88, 0x60, 0x4, 0x06, 0x12},
+  {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_1, DPC_1, FREQ_1600, DENSITY_1, 0}}, 3, 0x48, 0x89, 0x61, 0x4, 0x07, 0x0E},
+  {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_2, DPC_2, FREQ_1600, DENSITY_1, 0}}, 3, 0x9C, 0xD8, 0x60, 0x4, 0x06, 0x22},
+  {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_1, DPC_2, FREQ_1600, DENSITY_1, 0}}, 3, 0x9D, 0xD8, 0x60, 0x4, 0x06, 0x19},
+  {{{VDD_150, ECC_F, TYPE_UDIMM,  WIDTH_16, RANKS_2, DPC_1, FREQ_1600, DENSITY_1, 0}}, 4, 0x94, 0xE5, 0xC0, 0x7, 0x0C, 0x12},
+  {{{VDD_150, ECC_F, TYPE_UDIMM,  WIDTH_16, RANKS_1, DPC_1, FREQ_1600, DENSITY_1, 0}}, 4, 0x96, 0xE7, 0xC1, 0x7, 0x0E, 0x0E},
+  {{{VDD_150, ECC_F, TYPE_UDIMM,  WIDTH_16, RANKS_2, DPC_2, FREQ_1600, DENSITY_1, 0}}, 3, 0x9C, 0xC4, 0x60, 0x4, 0x06, 0x22},
+  {{{VDD_150, ECC_F, TYPE_UDIMM,  WIDTH_16, RANKS_1, DPC_2, FREQ_1600, DENSITY_1, 0}}, 3, 0x9C, 0xC5, 0x60, 0x4, 0x06, 0x19},
+  {{{VDD_150, ECC_T, TYPE_UDIMM,  WIDTH_16, RANKS_2, DPC_1, FREQ_1600, DENSITY_1, 0}}, 4, 0xA7, 0xDD, 0xEF, 0x8, 0x0E, 0x11},
+  {{{VDD_150, ECC_T, TYPE_UDIMM,  WIDTH_16, RANKS_1, DPC_1, FREQ_1600, DENSITY_1, 0}}, 4, 0xA9, 0xDE, 0xF0, 0x8, 0x10, 0x0D},
+  {{{VDD_150, ECC_T, TYPE_UDIMM,  WIDTH_16, RANKS_2, DPC_2, FREQ_1600, DENSITY_1, 0}}, 2, 0x7D, 0x88, 0x3C, 0x2, 0x04, 0x24},
+  {{{VDD_150, ECC_T, TYPE_UDIMM,  WIDTH_16, RANKS_1, DPC_2, FREQ_1600, DENSITY_1, 0}}, 2, 0x7D, 0x88, 0x3C, 0x2, 0x04, 0x18}
+};
+const Ddr3PowerWeightEntry Ddr3WcPowerWeightTable[] = {
+  {{{VDD_135, ECC_F, TYPE_SODIMM, 0       , 0      , 0    , 0        , 0        , 0}}, 3, 0x87, 0xAB, 0x44, 0x5, 0x08, 0x22},
+  {{{VDD_135, ECC_F, TYPE_UDIMM,  0       , 0      , 0    , 0        , 0        , 0}}, 3, 0x9F, 0xC1, 0x44, 0x5, 0x08, 0x20},
+  {{{VDD_135, ECC_T, TYPE_UDIMM,  0       , 0      , 0    , 0        , 0        , 0}}, 3, 0xDA, 0xF2, 0x4D, 0x5, 0x09, 0x1E},
+  {{{VDD_150, ECC_F, TYPE_SODIMM, 0       , 0      , 0    , 0        , 0        , 0}}, 3, 0xC5, 0xEF, 0xCD, 0x8, 0x10, 0x34},
+  {{{VDD_150, ECC_F, TYPE_UDIMM,  0       , 0      , 0    , 0        , 0        , 0}}, 2, 0x72, 0x87, 0x67, 0x4, 0x08, 0x34},
+  {{{VDD_150, ECC_T, TYPE_UDIMM,  0       , 0      , 0    , 0        , 0        , 0}}, 2, 0x98, 0xA3, 0x73, 0x5, 0x09, 0x31},
+  {{{0      , 0    , 0          , 0       , 0      , 0    , 0        , 0        , 0}}, 2, 0x98, 0xA3, 0x73, 0x5, 0x09, 0x34}
+};
+
+const Lpddr3PowerWeightEntry Lpddr3PowerWeightTable[] = {
+  {{{VDD_120, 0, 0, WIDTH_32, RANKS_2, 0, FREQ_1333, DENSITY_4, 0}}, 5, 0xA9, 0x84, 0xEE, 0x2, 0x4, 0x6, 0x3},
+  {{{VDD_120, 0, 0, WIDTH_32, RANKS_1, 0, FREQ_1333, DENSITY_4, 0}}, 5, 0x91, 0x4C, 0xEE, 0x2, 0x4, 0x5, 0x3},
+  {{{VDD_120, 0, 0, WIDTH_32, RANKS_2, 0, FREQ_1600, DENSITY_4, 0}}, 5, 0xA3, 0x79, 0xE9, 0x2, 0x3, 0x7, 0x4},
+  {{{VDD_120, 0, 0, WIDTH_32, RANKS_1, 0, FREQ_1600, DENSITY_4, 0}}, 5, 0x8B, 0x4A, 0xE9, 0x2, 0x3, 0x6, 0x3},
+  {{{VDD_120, 0, 0, WIDTH_16, RANKS_2, 0, FREQ_1333, DENSITY_4, 0}}, 4, 0x6B, 0x56, 0xE0, 0x2, 0x3, 0x9, 0x5},
+  {{{VDD_120, 0, 0, WIDTH_16, RANKS_1, 0, FREQ_1333, DENSITY_4, 0}}, 4, 0x5F, 0x3D, 0xE0, 0x2, 0x3, 0x8, 0x4},
+  {{{VDD_120, 0, 0, WIDTH_16, RANKS_2, 0, FREQ_1600, DENSITY_4, 0}}, 4, 0x67, 0x4F, 0xDB, 0x2, 0x3, 0xA, 0x6},
+  {{{VDD_120, 0, 0, WIDTH_16, RANKS_1, 0, FREQ_1600, DENSITY_4, 0}}, 4, 0x5B, 0x38, 0xDB, 0x2, 0x3, 0x9, 0x5}
+};
+const Lpddr3PowerWeightEntry Lpddr3WcPowerWeightTable[] = {
+  {{{0      , 0, 0, 0       , 0      , 0, 0        , 0        , 0}}, 4, 0x6B, 0x56, 0xE0, 0x2, 0x3, 0xA, 0x6}
+};
+
+/**
+@brief
+  This function configure the MC power register post training after normal mode before PCU start working.
+
+  @param[in, out] MrcData - Include all MRC global data.
+
+  @retval Nothing.
+**/
+void
+MrcPowerModesPostTraining (
+  IN OUT MrcParameters *const MrcData
+  )
+{
+  const MrcInput                      *Inputs;
+  MrcOutput                           *Outputs;
+  MrcControllerOut                    *ControllerOut;
+  MrcChannelOut                       *ChannelOut;
+  MCHBAR_CH0_CR_TC_BANK_RANK_D_STRUCT TcBankRankD;
+  MCDECS_CR_MCDECS_CBIT_MCMAIN_STRUCT McdecsCbit;
+  U32                                 Offset;
+  U8                                  Controller;
+  U8                                  Channel;
+
+  Inputs  = &MrcData->SysIn.Inputs;
+  Outputs = &MrcData->SysOut.Outputs;
+  for (Controller = 0; Controller < MAX_CONTROLLERS; Controller++) {
+    ControllerOut = &Outputs->Controller[Controller];
+    for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+      if (MrcChannelExist (Outputs, Channel)) {
+        ChannelOut = &ControllerOut->Channel[Channel];
+        //
+        // Configure Tcpded and Tprpden
+        //
+        TcBankRankD.Data = ChannelOut->MchbarBANKRANKD;
+        if (Outputs->Frequency >= f1867) {
+          TcBankRankD.Bits.tCPDED = 2;
+        }
+
+        if (Outputs->Frequency >= f2133) {
+          TcBankRankD.Bits.tPRPDEN = 2;
+        }
+
+        Offset = MCHBAR_CH0_CR_TC_BANK_RANK_D_REG +
+          ((MCHBAR_CH1_CR_TC_BANK_RANK_D_REG - MCHBAR_CH0_CR_TC_BANK_RANK_D_REG) * Channel);
+        MrcWriteCR (MrcData, Offset, TcBankRankD.Data);
+
+        //
+        // Save in MrcData structure
+        //
+        ChannelOut->MchbarBANKRANKD = TcBankRankD.Data;
+      }
+    }
+  }
+  //
+  // Configure Power Down CR
+  //
+  MrcPowerDownConfig (MrcData);
+
+  //
+  // Initialize McDecs_CBIT
+  //
+  McdecsCbit.Data = MCDECS_CBIT_DEFAULT;
+  if (!Inputs->WeaklockEn) {
+    McdecsCbit.Bits.dis_msg_clk_gate = 1;
+  }
+  MrcWriteCrMulticast (MrcData, MCDECS_CR_MCDECS_CBIT_MCMAIN_REG, McdecsCbit.Data);
+
+  return;
+}
+
+/**
+@brief
+  This function configures the power down control register.
+
+  @param[in]  - MrcData - The MRC global data.
+
+  @retval - Nothing
+**/
+void
+MrcPowerDownConfig (
+  IN MrcParameters *const MrcData
+  )
+{
+  const MrcInput  *Inputs;
+  MrcOutput       *Outputs;
+  U32             PowerDownMode;
+  MCSCHEDS_CR_PM_PDWN_CONFIG_STRUCT PmPdwnConfig;
+
+  Inputs  = &MrcData->SysIn.Inputs;
+  Outputs = &MrcData->SysOut.Outputs;
+  
+  PmPdwnConfig.Data                   = 0;
+  PmPdwnConfig.Bits.PDWN_idle_counter = PDWN_IDLE_COUNTER;
+
+  if (Inputs->PwdwnIdleCounter) {
+    PmPdwnConfig.Bits.PDWN_idle_counter = Inputs->PwdwnIdleCounter;
+  }
+
+  if ((Inputs->PowerDownMode == pdmNoPowerDown) ||
+      (Inputs->PowerDownMode == pdmAPD) ||
+      (Inputs->PowerDownMode == pdmPPDDLLOFF)
+      ) {
+    PowerDownMode = Inputs->PowerDownMode;
+  } else {
+    PowerDownMode = pdmPPDDLLOFF;
+#ifdef ULT_FLAG
+    if (Outputs->DdrType == MRC_DDR_TYPE_LPDDR3) {
+      PowerDownMode = pdmPPD;
+    }
+#endif // ULT_FLAG
+  }
+
+  PmPdwnConfig.Bits.PDWN_mode = PowerDownMode;
+  MrcWriteCR (MrcData, MCSCHEDS_CR_PM_PDWN_CONFIG_REG, PmPdwnConfig.Data);
+
+  return;
+}
+
+/**
+@brief
+  This functions sets power weight, scale factor and Channel
+  Power Floor values from lookup table based on DIMMs present in
+  the system.
+
+  @param[in] MrcData - Include all MRC global data.
+
+  @retval MrcStatus - mrcSuccess or reason for failure.
+**/
+MrcStatus
+MrcPowerWeight (
+  IN     MrcParameters *const MrcData
+  )
+{
+  const MrcInput               *Inputs;
+  const MrcControllerIn        *ControllerIn;
+  const MrcDimmIn              *DimmIn;
+  const MrcSpd                 *Spd;
+  const MrcDebug               *Debug;
+  MrcOutput                    *Outputs;
+  MrcControllerOut             *ControllerOut;
+  MrcDimmOut                   *DimmOut;
+  U8                           Controller;
+  U8                           Channel;
+  U8                           Dimm;
+  const Ddr3PowerWeightEntry   *Ddr3Pwt[2];
+  const Lpddr3PowerWeightEntry *Lpddr3Pwt[2];
+  U16                          PwtSize[2];
+  PowerWeightInputs            DimmPwt;
+  U8                           i;
+  U16                          j;
+  BOOL                         DimmEntryFound;
+  BOOL                         EnterWc;
+  U8                           SfDiff;
+  U8                           MinScaleFactor;
+  U8                           ScaleFactor[MAX_CHANNEL][MAX_DIMMS_IN_CHANNEL];
+  U8                           ChPwrFloor[MAX_CHANNEL][MAX_DIMMS_IN_CHANNEL];
+  U32                          Offset;
+  MCHBAR_CH0_CR_PM_DIMM_RD_ENERGY_STRUCT         PmDimmRdEnergy[MAX_CHANNEL];
+  MCHBAR_CH0_CR_PM_DIMM_WR_ENERGY_STRUCT         PmDimmWrEnergy[MAX_CHANNEL];
+  MCHBAR_CH0_CR_PM_DIMM_ACT_ENERGY_STRUCT        PmDimmActEnergy[MAX_CHANNEL];
+  MCHBAR_CH0_CR_PM_DIMM_PD_ENERGY_STRUCT         PmDimmPdEnergy[MAX_CHANNEL];
+  MCHBAR_CH0_CR_PM_DIMM_IDLE_ENERGY_STRUCT       PmDimmIdleEnergy[MAX_CHANNEL];
+  PCU_CR_DDR_RAPL_CHANNEL_POWER_FLOOR_PCU_STRUCT DdrRaplChannelPowerFloor;
+
+  Inputs                        = &MrcData->SysIn.Inputs;
+  Debug                         = &MrcData->SysIn.Inputs.Debug;
+  Outputs                       = &MrcData->SysOut.Outputs;
+  MinScaleFactor                = (U8) ~0;
+  Ddr3Pwt[0]                    = Ddr3PowerWeightTable;
+  Ddr3Pwt[1]                    = Ddr3WcPowerWeightTable;
+  Lpddr3Pwt[0]                  = Lpddr3PowerWeightTable;
+  Lpddr3Pwt[1]                  = Lpddr3WcPowerWeightTable;
+  DdrRaplChannelPowerFloor.Data = 0;
+
+  MrcOemMemorySet((U8 *) PmDimmRdEnergy, 0, sizeof (PmDimmRdEnergy));
+  MrcOemMemorySet((U8 *) PmDimmWrEnergy, 0, sizeof (PmDimmWrEnergy));
+  MrcOemMemorySet((U8 *) PmDimmActEnergy, 0, sizeof (PmDimmActEnergy));
+  MrcOemMemorySet((U8 *) PmDimmPdEnergy, 0, sizeof (PmDimmPdEnergy));
+  MrcOemMemorySet((U8 *) PmDimmIdleEnergy, 0, sizeof (PmDimmIdleEnergy));
+  MrcOemMemorySet((U8 *) ScaleFactor, (U32) ~0, sizeof (ScaleFactor));
+  MrcOemMemorySet((U8 *) ChPwrFloor, (U32) 0, sizeof (ChPwrFloor));
+
+  if (Outputs->DdrType == MRC_DDR_TYPE_LPDDR3) {
+    PwtSize[0] = sizeof (Lpddr3PowerWeightTable) / sizeof (Lpddr3PowerWeightEntry);
+    PwtSize[1] = sizeof (Lpddr3WcPowerWeightTable) / sizeof (Lpddr3PowerWeightEntry);
+  } else {
+    PwtSize[0] = sizeof (Ddr3PowerWeightTable) / sizeof (Ddr3PowerWeightEntry);
+    PwtSize[1] = sizeof (Ddr3WcPowerWeightTable) / sizeof (Ddr3PowerWeightEntry);
+  }
+
+  if (Inputs->MemoryProfile != USER_PROFILE) {
+    for (Controller = 0; Controller < MAX_CONTROLLERS; Controller++) {
+      ControllerOut = &Outputs->Controller[Controller];
+      ControllerIn  = &Inputs->Controller[Controller];
+      for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+        if (MrcChannelExist (Outputs, Channel)) {
+          //
+          // Collect Channel level data for lookup
+          //
+          for (Dimm = 0; Dimm < MAX_DIMMS_IN_CHANNEL; Dimm++) {
+            DimmOut = &ControllerOut->Channel[Channel].Dimm[Dimm];
+            DimmIn  = &ControllerIn->Channel[Channel].Dimm[Dimm];
+            if (DimmOut->Status == DIMM_PRESENT) {
+              EnterWc = FALSE;
+              DimmPwt.Data = 0;
+              //
+              // Collect DIMM level data for lookup
+              //
+
+              Spd = &DimmIn->Spd;
+
+              switch (Outputs->VddVoltage[Inputs->MemoryProfile]) {
+                case VDD_1_20:
+                  DimmPwt.Bits.Vddq = VDD_120;
+                  break;
+
+                case VDD_1_35:
+                  DimmPwt.Bits.Vddq = VDD_135;
+                  break;
+
+                case VDD_1_50:
+                  DimmPwt.Bits.Vddq = VDD_150;
+                  break;
+
+                default:
+                  DimmPwt.Bits.Vddq = VDD_OTHER;
+                  EnterWc = TRUE;
+                  break;
+              }
+
+              DimmPwt.Bits.Ecc         = DimmOut->EccSupport;
+              DimmPwt.Bits.DimmType    = DimmOut->ModuleType;
+              DimmPwt.Bits.DeviceWidth = DimmOut->SdramWidthIndex;
+              DimmPwt.Bits.NumOfRanks  = DimmOut->RankInDIMM;
+              DimmPwt.Bits.Dpc         = ControllerOut->Channel[Channel].DimmCount;
+
+              switch (Outputs->Frequency) {
+                case f1067:
+                  DimmPwt.Bits.Frequency = FREQ_1067;
+                  break;
+
+                case f1333:
+                  DimmPwt.Bits.Frequency = FREQ_1333;
+                  break;
+
+                case f1600:
+                  DimmPwt.Bits.Frequency = FREQ_1600;
+                  break;
+
+                case f1867:
+                  DimmPwt.Bits.Frequency = FREQ_1867;
+                  break;
+
+                case f2133:
+                  DimmPwt.Bits.Frequency = FREQ_2133;
+                  break;
+
+                default:
+                  EnterWc = TRUE;
+                  break;
+              }
+
+              DimmPwt.Bits.DramDensity = DimmOut->DensityIndex;
+
+              if (Outputs->DdrType == MRC_DDR_TYPE_LPDDR3) {
+                DimmPwt.Bits.Ecc      = 0;
+                DimmPwt.Bits.DimmType = 0;
+                DimmPwt.Bits.Dpc      = 0;
+              }
+
+              //
+              // Search lookup table for DIMM entry
+              //
+              DimmEntryFound = FALSE;
+              for (i = 0; i < sizeof (PwtSize) / sizeof (PwtSize[0]); i++) {
+                if (i == 0) {
+                  if (EnterWc) {
+                    continue;
+                  }
+                } else if (i == 1) {
+                  if (!DimmEntryFound) {
+                    DimmPwt.Bits.DeviceWidth = 0;
+                    DimmPwt.Bits.NumOfRanks  = 0;
+                    DimmPwt.Bits.Dpc         = 0;
+                    DimmPwt.Bits.Frequency   = 0;
+                    DimmPwt.Bits.DramDensity = 0;
+                  } else {
+                    continue;
+                  }
+                }
+                for (j = 0; j < PwtSize[i]; j++) {
+                  if (Outputs->DdrType == MRC_DDR_TYPE_LPDDR3) {
+                    if (DimmPwt.Data == Lpddr3Pwt[i][j].PwInput.Data ||
+                        (i == 1 && j == PwtSize[i] - 1)) {
+                      PmDimmRdEnergy[Channel].Data8[Dimm]   = Lpddr3Pwt[i][j].RdCr;
+                      PmDimmWrEnergy[Channel].Data8[Dimm]   = Lpddr3Pwt[i][j].WrCr;
+                      PmDimmActEnergy[Channel].Data8[Dimm]  = Lpddr3Pwt[i][j].ActCr;
+                      PmDimmPdEnergy[Channel].Data8[Dimm]   = Lpddr3Pwt[i][j].CkeL;
+                      PmDimmIdleEnergy[Channel].Data8[Dimm] = Lpddr3Pwt[i][j].CkeH;
+                      ScaleFactor[Channel][Dimm]            = Lpddr3Pwt[i][j].ScaleFactor;
+                      ChPwrFloor[Channel][Dimm]             = (ControllerOut->ChannelCount == 1)
+                                                                ? Lpddr3Pwt[i][j].OneChPwrFloor
+                                                                : Lpddr3Pwt[i][j].TwoChPwrFloor;
+                      MinScaleFactor                        = MIN (MinScaleFactor, ScaleFactor[Channel][Dimm]);
+                      DimmEntryFound                        = TRUE;
+                      break;
+                    }
+                  } else {
+                    if (DimmPwt.Data == Ddr3Pwt[i][j].PwInput.Data ||
+                        (i == 1 && j == PwtSize[i] - 1)) {
+                      PmDimmRdEnergy[Channel].Data8[Dimm]   = Ddr3Pwt[i][j].RdCr;
+                      PmDimmWrEnergy[Channel].Data8[Dimm]   = Ddr3Pwt[i][j].WrCr;
+                      PmDimmActEnergy[Channel].Data8[Dimm]  = Ddr3Pwt[i][j].ActCr;
+                      PmDimmPdEnergy[Channel].Data8[Dimm]   = Ddr3Pwt[i][j].CkeL;
+                      PmDimmIdleEnergy[Channel].Data8[Dimm] = Ddr3Pwt[i][j].CkeH;
+                      ScaleFactor[Channel][Dimm]            = Ddr3Pwt[i][j].ScaleFactor;
+                      ChPwrFloor[Channel][Dimm]             = Ddr3Pwt[i][j].ChPwrFloor;
+                      MinScaleFactor                        = MIN (MinScaleFactor, ScaleFactor[Channel][Dimm]);
+                      DimmEntryFound                        = TRUE;
+                      break;
+                    }
+                  }
+                }
+              }
+            }
+          }
+        }
+      }
+    }
+
+    for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+      if (MrcChannelExist (Outputs, Channel)) {
+        for (Dimm = 0; Dimm < MAX_DIMMS_IN_CHANNEL; Dimm++) {
+          DimmOut = &Outputs->Controller->Channel[Channel].Dimm[Dimm];
+          if (DimmOut->Status == DIMM_PRESENT) {
+            //
+            // Set Scale Factor of all DIMMs to lowest Scale Factor and adjust weights accordingly.
+            //
+            if ((SfDiff = ScaleFactor[Channel][Dimm] - MinScaleFactor) > 0) {
+              PmDimmRdEnergy[Channel].Data8[Dimm]   = (PmDimmRdEnergy[Channel].Data8[Dimm] + 1) >> SfDiff;
+              PmDimmWrEnergy[Channel].Data8[Dimm]   = (PmDimmWrEnergy[Channel].Data8[Dimm] + 1) >> SfDiff;
+              PmDimmActEnergy[Channel].Data8[Dimm]  = (PmDimmActEnergy[Channel].Data8[Dimm] + 1) >> SfDiff;
+              PmDimmPdEnergy[Channel].Data8[Dimm]   = (PmDimmPdEnergy[Channel].Data8[Dimm] + 1) >> SfDiff;
+              PmDimmIdleEnergy[Channel].Data8[Dimm] = (PmDimmIdleEnergy[Channel].Data8[Dimm] + 1) >> SfDiff;
+            }
+          }
+        }
+        //
+        // Set RAPL Channel Power Floor to average of DIMMs rounded up to nearest integer multiple of 0.125W (which is
+        // going to be a multiple of 8 for Channel Power Floor Register).
+        //
+        if (Outputs->Controller->Channel[Channel].DimmCount > 1) {
+          if (ChPwrFloor[Channel][0] != ChPwrFloor[Channel][1]) {
+            ChPwrFloor[Channel][0] = (ChPwrFloor[Channel][0] + ChPwrFloor[Channel][1] + 1) / 2;
+            if (ChPwrFloor[Channel][0] < 0xF8) {
+              if ((ChPwrFloor[Channel][0] % 8) != 0) {
+                ChPwrFloor[Channel][0] = ChPwrFloor[Channel][0] + (8 - (ChPwrFloor[Channel][0] % 8));
+              }
+            } else { // No more 8-bit mulitples of 8 after 0xF8, must round down.
+              ChPwrFloor[Channel][0] = 0xF8;
+            }
+          }
+        } else {
+          for (Dimm = 0; Dimm < MAX_DIMMS_IN_CHANNEL; Dimm++) {
+            ChPwrFloor[Channel][0] = MAX (ChPwrFloor[Channel][0], ChPwrFloor[Channel][Dimm]);
+          }
+        }
+
+        //
+        // Apply power weights
+        //
+        Offset = MCHBAR_CH0_CR_PM_DIMM_RD_ENERGY_REG +
+          (MCHBAR_CH1_CR_PM_DIMM_RD_ENERGY_REG - MCHBAR_CH0_CR_PM_DIMM_RD_ENERGY_REG) * Channel;
+        MrcWriteCR (MrcData, Offset, PmDimmRdEnergy[Channel].Data);
+        Offset = MCHBAR_CH0_CR_PM_DIMM_WR_ENERGY_REG +
+          (MCHBAR_CH1_CR_PM_DIMM_WR_ENERGY_REG - MCHBAR_CH0_CR_PM_DIMM_WR_ENERGY_REG) * Channel;
+        MrcWriteCR (MrcData, Offset, PmDimmWrEnergy[Channel].Data);
+        Offset = MCHBAR_CH0_CR_PM_DIMM_ACT_ENERGY_REG +
+          (MCHBAR_CH1_CR_PM_DIMM_ACT_ENERGY_REG - MCHBAR_CH0_CR_PM_DIMM_ACT_ENERGY_REG) * Channel;
+        MrcWriteCR (MrcData, Offset, PmDimmActEnergy[Channel].Data);
+        Offset = MCHBAR_CH0_CR_PM_DIMM_PD_ENERGY_REG +
+          (MCHBAR_CH1_CR_PM_DIMM_PD_ENERGY_REG - MCHBAR_CH0_CR_PM_DIMM_PD_ENERGY_REG) * Channel;
+        MrcWriteCR (MrcData, Offset, PmDimmPdEnergy[Channel].Data);
+        Offset = MCHBAR_CH0_CR_PM_DIMM_IDLE_ENERGY_REG +
+          (MCHBAR_CH1_CR_PM_DIMM_IDLE_ENERGY_REG - MCHBAR_CH0_CR_PM_DIMM_IDLE_ENERGY_REG) * Channel;
+        MrcWriteCR (MrcData, Offset, PmDimmIdleEnergy[Channel].Data);
+      }
+    }
+    DdrRaplChannelPowerFloor.Bits.CH0 = ChPwrFloor[0][0];
+    DdrRaplChannelPowerFloor.Bits.CH1 = ChPwrFloor[1][0];
+    MrcWriteCR (MrcData, PCU_CR_DDR_RAPL_CHANNEL_POWER_FLOOR_PCU_REG, DdrRaplChannelPowerFloor.Data);
+    MrcWriteCR (MrcData, PCU_CR_DDR_ENERGY_SCALEFACTOR_PCU_REG, (U32) MinScaleFactor);
+
+#ifdef MRC_DEBUG_PRINT
+    MRC_DEBUG_MSG (
+      Debug,
+      MSG_LEVEL_NOTE,
+      "Applied Power Weights:\n\tSclFctr\tRdCr\tWrCr\tActCr\tCkeL\tCkeH\tChPwrFloor\n"
+      );
+    for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+      if (MrcChannelExist (Outputs, Channel)) {
+        for (Dimm = 0; Dimm < MAX_DIMMS_IN_CHANNEL; Dimm++) {
+          DimmOut = &Outputs->Controller->Channel[Channel].Dimm[Dimm];
+          if (DimmOut->Status == DIMM_PRESENT) {
+            MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "C%dD%d:\t", Channel, Dimm);
+            MRC_DEBUG_MSG (
+              Debug,
+              MSG_LEVEL_NOTE,
+              "%d\t%2Xh\t%2Xh\t%2Xh\t%Xh\t%2Xh\t%2Xh\n",
+              MinScaleFactor,
+              PmDimmRdEnergy[Channel].Data8[Dimm],
+              PmDimmWrEnergy[Channel].Data8[Dimm],
+              PmDimmActEnergy[Channel].Data8[Dimm],
+              PmDimmPdEnergy[Channel].Data8[Dimm],
+              PmDimmIdleEnergy[Channel].Data8[Dimm],
+              ChPwrFloor[Channel][0]
+              );
+          }
+        }
+      }
+    }
+#endif
+  }
+
+  return mrcSuccess;
+}
diff --git a/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/McConfiguration/MrcPowerModes.h b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/McConfiguration/MrcPowerModes.h
new file mode 100644
index 0000000..1242276
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/McConfiguration/MrcPowerModes.h
@@ -0,0 +1,174 @@
+/** @file
+  This module includes the power modes definitions.
+
+@Copyright
+  Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved.
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement.
+**/
+#ifndef _MrcPowerModes_h_
+#define _MrcPowerModes_h_
+#pragma pack(push, 1)
+
+#include "McAddress.h"
+#include "MrcTypes.h"
+#include "MrcCommon.h"
+#include "MrcGlobal.h"
+
+//
+// Lookup table definitions
+//
+#define GEN_DDR3    1
+#define GEN_DDR4    2
+#define VDD_120     1
+#define VDD_135     2
+#define VDD_150     3
+#define VDD_OTHER   4
+#define ECC_F       0
+#define ECC_T       1
+#define TYPE_SODIMM 3
+#define TYPE_UDIMM  2
+#define WIDTH_8     1
+#define WIDTH_16    2
+#define WIDTH_32    3
+#define RANKS_1     1
+#define RANKS_2     2
+#define DPC_1       1
+#define DPC_2       2
+#define FREQ_800    1
+#define FREQ_1000   2
+#define FREQ_1067   3
+#define FREQ_1200   4
+#define FREQ_1333   5
+#define FREQ_1400   6
+#define FREQ_1600   7
+#define FREQ_1800   8
+#define FREQ_1867   9
+#define FREQ_2000   10
+#define FREQ_2133   11
+#define FREQ_2200   12
+#define FREQ_2400   13
+#define FREQ_2600   14
+#define FREQ_2667   15
+#define DENSITY_1   2
+#define DENSITY_2   3
+#define DENSITY_4   4
+
+typedef enum {
+  tsmNoThermalSensing = 0,  ///< No thermal sensing in MC
+  tsmThermalSensor,         ///< Thermal Sensor (on DIMM) - when set thermal sense is active
+  tsmBwEstimation,          ///< BW estimation - when set, PM_SUM_PC_CxRy of this DIMM accumulates command power estimation
+  tsmBoth                   ///< Both (1) and (2)
+} ThermalSensorModes;
+
+///
+/// Power Down mode
+///
+typedef enum {
+  pdmNoPowerDown      = 0,
+  pdmAPD              = 1,
+  pdmPPD              = 2,
+  pdmPPDDLLOFF        = 6,
+  pdmAuto             = 0xFF,
+} MrcPowerDownMode;
+
+typedef union {
+  struct {
+    U32 Vddq        :  4;
+    U32 Ecc         :  1;
+    U32 DimmType    :  4;
+    U32 DeviceWidth :  3;
+    U32 NumOfRanks  :  3;
+    U32 Dpc         :  2;
+    U32 Frequency   :  4;
+    U32 DramDensity :  3;
+    U32 Spare       :  8;
+  } Bits;
+  U32 Data;
+  U16 Data16[2];
+  U8  Data8[4];
+} PowerWeightInputs;
+
+typedef struct {
+  PowerWeightInputs PwInput;
+  U8                ScaleFactor;
+  U8                RdCr;
+  U8                WrCr;
+  U8                ActCr;
+  U8                CkeL;
+  U8                CkeH;
+  U8                ChPwrFloor;
+} Ddr3PowerWeightEntry;
+
+typedef struct {
+  PowerWeightInputs PwInput;
+  U8                ScaleFactor;
+  U8                RdCr;
+  U8                WrCr;
+  U8                ActCr;
+  U8                CkeL;
+  U8                CkeH;
+  U8                OneChPwrFloor;
+  U8                TwoChPwrFloor;
+} Lpddr3PowerWeightEntry;
+
+#define PDWN_IDLE_COUNTER   (0x80)
+
+#define MCDECS_CBIT_DEFAULT (0x00000000)
+
+/**
+@brief
+  This function configure the MC power register post training after normal mode before PCU start working.
+
+  @param[in, out] MrcData - Include all MRC global data.
+
+  @retval Nothing.
+**/
+extern
+void
+MrcPowerModesPostTraining (
+  IN OUT MrcParameters *const MrcData
+  );
+
+/**
+@brief
+  This function configures the power down control register.
+
+  @param[in]  - MrcData - The MRC global data.
+
+  @retval - Nothing
+**/
+extern
+void
+MrcPowerDownConfig (
+  IN MrcParameters *const MrcData
+  );
+
+/**
+@brief
+  This functions applies power weight values from lookup table to every DIMM in the system.
+
+  @param[in] MrcData - Include all MRC global data.
+
+  @retval MrcStatus - mrcSuccess or reason for failure.
+**/
+extern
+MrcStatus
+MrcPowerWeight (
+  MrcParameters * const MrcData
+);
+
+#pragma pack(pop)
+#endif // _MrcPowerModes_h_
diff --git a/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/McConfiguration/MrcRefreshConfiguration.c b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/McConfiguration/MrcRefreshConfiguration.c
new file mode 100644
index 0000000..ae958d2
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/McConfiguration/MrcRefreshConfiguration.c
@@ -0,0 +1,453 @@
+/** @file
+  This module sets the memory controller refresh parameters.
+
+@copyright
+  Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved.
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement.
+**/
+
+///
+/// Include files
+///
+#include "MrcRefreshConfiguration.h"
+
+/**
+@brief
+  This function returns the tXS offset.
+  tXS-offset: tXS = tRFC+10ns. Setup of tXS-offset is # of cycles for 10 ns.
+
+  @param[in] Frequency - The memory frequency.
+
+  @retval tXS-offset value.
+**/
+static
+U32
+tXsOffset (
+  IN const MrcFrequency Frequency
+  )
+{
+  U32 tXSOffset;
+
+  if (Frequency <= f800) {
+    tXSOffset = Offset_10nsec_800;
+  } else if (Frequency <= f1067) {
+    tXSOffset = Offset_10nsec_1067;
+  } else if (Frequency <= f1333) {
+    tXSOffset = Offset_10nsec_1333;
+  } else if (Frequency <= f1600) {
+    tXSOffset = Offset_10nsec_1600;
+  } else if (Frequency <= f1867) {
+    tXSOffset = Offset_10nsec_1867;
+  } else if (Frequency <= f2133) {
+    tXSOffset = Offset_10nsec_2133;
+  } else if (Frequency <= f2400) {
+    tXSOffset = Offset_10nsec_2400;
+  } else {
+    tXSOffset = Offset_10nsec_2667;
+  }
+
+  return tXSOffset;
+}
+
+/**
+@brief
+  This function configures the TC-RFTP register and its fields 9tREFI, tRFC, tREFI.
+
+  @param[in] MrcData         - Include all MRC global data.
+  @param[in] ChannelIndex    - Channel to work on.
+
+  @retval Nothing.
+**/
+static
+void
+SetTcRftpReg (
+  IN MrcParameters *const MrcData,
+  IN const U32            ChannelIndex
+  )
+{
+  MrcTiming                     *TimingOut;
+  MCHBAR_CH0_CR_TC_RFTP_STRUCT  TcRftp;
+  MrcProfile                    Profile;
+  U32                           tRefix9;
+  U32                           Offset;
+  U16                           tREFI_MAX;
+
+  Profile             = MrcData->SysIn.Inputs.MemoryProfile;
+  TimingOut           = &MrcData->SysOut.Outputs.Controller[0].Channel[ChannelIndex].Timing[Profile];
+  tRefix9             = (TimingOut->tREFI * 89) / (1024 * 10);
+  TcRftp.Data         = 0;
+  tREFI_MAX = MCHBAR_CH0_CR_TC_RFTP_tREFI_MAX;
+  TcRftp.Bits.tREFI   = MIN (tREFI_MAX, TimingOut->tREFI);
+  TcRftp.Bits.tRFC    = MIN (MCHBAR_CH0_CR_TC_RFTP_tRFC_MAX, TimingOut->tRFC);
+  TcRftp.Bits.tREFIx9 = MIN (MCHBAR_CH0_CR_TC_RFTP_tREFIx9_MAX, tRefix9);
+  Offset              = MCHBAR_CH0_CR_TC_RFTP_REG +
+                        ((MCHBAR_CH1_CR_TC_RFTP_REG - MCHBAR_CH0_CR_TC_RFTP_REG) * ChannelIndex);
+  MrcWriteCR (MrcData, Offset, TcRftp.Data);
+  MRC_DEBUG_MSG (
+    &MrcData->SysIn.Inputs.Debug,
+    MSG_LEVEL_NOTE,
+    "TC-RFTP Channel %u register value = %Xh\n",
+    ChannelIndex,
+    TcRftp.Data
+    );
+  return;
+}
+
+/**
+@brief
+  This function configures the TC-SRFTP register and its fields tZQOPER, tXS-offset, tXSDLL.
+
+  @param[in] MrcData         - Include all MRC global data.
+  @param[in] ChannelIndex    - Channel to work on.
+
+  @retval Nothing.
+**/
+static
+void
+SetTcSrftpReg (
+  IN MrcParameters *const MrcData,
+  IN const U32            ChannelIndex
+  )
+{
+  const MrcInput                *Inputs;
+  MrcFrequency                  Frequency;
+  U32                           tZQOPER;
+  U32                           tXS_offset;
+  U32                           tMod;
+  U32                           Offset;
+  MCHBAR_CH0_CR_TC_SRFTP_STRUCT CrTcSrftp;
+
+  Inputs                    = &MrcData->SysIn.Inputs;
+  Frequency                 = MrcData->SysOut.Outputs.Frequency;
+  tZQOPER                   = tZQOPERGet (MrcData, Frequency);
+  tXS_offset                = tXsOffset (Frequency);
+  tMod                      = tMODGet (Frequency) - 8;
+
+  CrTcSrftp.Data            = 0;
+  CrTcSrftp.Bits.tXSDLL     = MIN (MCHBAR_CH0_CR_TC_SRFTP_tXSDLL_MAX, tDLLK_VALUE);
+  CrTcSrftp.Bits.tXS_offset = MIN (MCHBAR_CH0_CR_TC_SRFTP_tXS_offset_MAX, tXS_offset);
+  CrTcSrftp.Bits.tZQOPER    = MIN (MCHBAR_CH0_CR_TC_SRFTP_tZQOPER_MAX, tZQOPER);
+  CrTcSrftp.Bits.tMOD       = MIN (MCHBAR_CH0_CR_TC_SRFTP_tMOD_MAX, tMod);
+  Offset                    = MCHBAR_CH0_CR_TC_SRFTP_REG +
+                              ((MCHBAR_CH1_CR_TC_SRFTP_REG - MCHBAR_CH0_CR_TC_SRFTP_REG) * ChannelIndex);
+  MrcWriteCR (MrcData, Offset, CrTcSrftp.Data);
+  MRC_DEBUG_MSG (
+    &Inputs->Debug,
+    MSG_LEVEL_NOTE,
+    "Ch%u: TC_SRFTP = %Xh\n tXSDLL = %u\n tXS_offset = %u\n tZQOPER = %u\n tMOD = %u\n",
+    ChannelIndex,
+    CrTcSrftp.Data,
+    CrTcSrftp.Bits.tXSDLL,
+    CrTcSrftp.Bits.tXS_offset,
+    CrTcSrftp.Bits.tZQOPER,
+    CrTcSrftp.Bits.tMOD
+    );
+  return;
+}
+
+/**
+@brief
+  This function returns the tZQOPER value.
+  tZQOPER = Defines the period required for ZQCL after SR exit.
+
+  @param[in] MrcData         - Include all MRC global data.
+  @param[in] Frequency       - The memory frequency.
+
+  @retval The tZQOPER value.
+**/
+U32
+tZQOPERGet (
+  IN MrcParameters *const MrcData,
+  IN const MrcFrequency   Frequency
+  )
+{
+  U32             tZQOPER;
+#ifdef ULT_FLAG
+  MrcDdrType      DdrType;
+
+  DdrType = MrcData->SysOut.Outputs.DdrType;
+  if (DdrType == MRC_DDR_TYPE_LPDDR3) {
+    tZQOPER = tZQCL_MIN / (MrcData->SysOut.Outputs.Qclkps * 2);
+  } else
+#endif // ULT_FLAG
+  {
+    if (Frequency <= f1600) {
+      ///
+      /// All frequencies below 1600 uses the same value
+      ///
+      tZQOPER = tZQOPER_1600;
+    } else if (Frequency <= f1867) {
+      tZQOPER = tZQOPER_1867;
+    } else if (Frequency <= f2133) {
+      tZQOPER = tZQOPER_2133;
+    } else if (Frequency <= f2400) {
+      tZQOPER = tZQOPER_2400;
+    } else {
+      tZQOPER = tZQOPER_2667;
+    }
+  }
+
+  return tZQOPER;
+}
+
+/**
+@brief
+  This function returns the tMOD value.
+  tMOD = max(12nCK, 15ns) nCK change by the frequency.
+
+  @param[in] Frequency       - The memory frequency.
+
+  @retval The tMOD value.
+**/
+U32
+tMODGet (
+  IN const MrcFrequency Frequency
+  )
+{
+  U32 tMOD;
+
+  if (Frequency <= f800) {
+    tMOD = tMOD_800;
+  } else if (Frequency <= f1067) {
+    tMOD = tMOD_1067;
+  } else if (Frequency <= f1333) {
+    tMOD = tMOD_1333;
+  } else if (Frequency <= f1600) {
+    tMOD = tMOD_1600;
+  } else if (Frequency <= f1867) {
+    tMOD = tMOD_1867;
+  } else if (Frequency <= f2133) {
+    tMOD = tMOD_2133;
+  } else if (Frequency <= f2400) {
+    tMOD = tMOD_2400;
+  } else {
+    tMOD = tMOD_2667;
+  }
+
+  return tMOD;
+}
+
+/**
+@brief
+  This function configures the TC-ZQCAL register and its fields tZQCS and tZQCS_PERIOD.
+
+  @param[in] MrcData         - Include all MRC global data.
+  @param[in] ChannelIndex    - Channel to work on.
+
+  @retval Nothing.
+**/
+static
+void
+SetTcZqCalReg (
+  IN MrcParameters *const MrcData,
+  IN const U32            ChannelIndex
+  )
+{
+  MCHBAR_CH0_CR_TC_ZQCAL_STRUCT ZqCal;
+  U32                           ZQCS_period;
+  U32                           tZQCS;
+  U32                           Offset;
+  MrcCpuModel                   CpuModel;
+#ifdef ULT_FLAG
+  MrcDdrType                    DdrType;
+#endif // ULT_FLAG
+
+  CpuModel = MrcData->SysIn.Inputs.CpuModel;
+
+  Offset = MCHBAR_CH0_CR_TC_ZQCAL_REG + (MCHBAR_CH1_CR_TC_ZQCAL_REG - MCHBAR_CH0_CR_TC_ZQCAL_REG) * ChannelIndex;
+
+  ZqCal.Data  = 0;
+  tZQCS       = tZQCSGet (MrcData, MrcData->SysOut.Outputs.Frequency);
+  ZQCS_period = ZQCS_PERIOD_DDR3;
+
+#ifdef ULT_FLAG
+  DdrType = MrcData->SysOut.Outputs.DdrType;
+  if (CpuModel == cmHSW_ULT) {
+    if (DdrType == MRC_DDR_TYPE_LPDDR3) {
+      ZQCS_period = ZQCS_PERIOD_LPDDR3;
+    }
+    ZqCal.UltBits.ZQCS_period = MIN (MCHBAR_CH0_CR_TC_ZQCAL_ZQCS_period_Ult_MAX, ZQCS_period);
+    ZqCal.UltBits.tZQCS       = MIN (MCHBAR_CH0_CR_TC_ZQCAL_tZQCS_Ult_MAX, tZQCS);
+  } else
+#endif // ULT_FLAG
+  {
+    ZqCal.Bits.ZQCS_period = MIN (MCHBAR_CH0_CR_TC_ZQCAL_ZQCS_period_MAX, ZQCS_period);
+    ZqCal.Bits.tZQCS       = MIN (MCHBAR_CH0_CR_TC_ZQCAL_tZQCS_MAX, tZQCS);
+  }
+  MrcWriteCR (MrcData, Offset, ZqCal.Data);
+
+#ifdef ULT_FLAG
+  if (CpuModel == cmHSW_ULT) {
+    ZQCS_period = ZqCal.UltBits.ZQCS_period;
+    tZQCS       = ZqCal.UltBits.tZQCS;
+  } else
+#endif //ULT_FLAG
+  {
+    ZQCS_period = ZqCal.Bits.ZQCS_period;
+    tZQCS       = ZqCal.Bits.tZQCS;
+  }
+
+  MRC_DEBUG_MSG (
+    &MrcData->SysIn.Inputs.Debug,
+    MSG_LEVEL_NOTE,
+    "Ch%u: TC_ZQCAL = %Xh\n ZQCS_period = %u\n tZQCS = %u\n",
+    ChannelIndex,
+    ZqCal.Data,
+    ZQCS_period,
+    tZQCS
+    );
+
+  return;
+}
+
+/**
+@brief
+  This function returns the tZQCS value.
+
+  @param[in] MrcData         - Include all MRC global data.
+  @param[in] Frequency       - The memory frequency.
+
+  @retval The tZQCS value.
+**/
+U32
+tZQCSGet (
+  IN MrcParameters *const MrcData,
+  IN const MrcFrequency   Frequency
+  )
+{
+  U32         tZQCS;
+#ifdef ULT_FLAG
+  MrcDdrType  DdrType;
+
+  DdrType = MrcData->SysOut.Outputs.DdrType;
+  if (DdrType == MRC_DDR_TYPE_LPDDR3) {
+    tZQCS = tZQCS_MIN / (MrcData->SysOut.Outputs.Qclkps * 2);
+  } else
+#endif // ULT_FLAG
+  {
+    if (Frequency <= f1600) {
+      //
+      // All frequencies below 1600 uses the same value
+      //
+      tZQCS = tZQCS_1600;
+    } else if (Frequency <= f1867) {
+      tZQCS = tZQCS_1867;
+    } else if (Frequency <= f2133) {
+      tZQCS = tZQCS_2133;
+    } else if (Frequency <= f2400) {
+      tZQCS = tZQCS_2400;
+    } else {
+      tZQCS = tZQCS_2667;
+    }
+  }
+  return tZQCS;
+}
+
+/**
+@brief
+  This function configures the TC_MR2_SHADDOW register and its fields.
+
+  @param[in] MrcData         - Include all MRC global data.
+  @param[in] Channel         - Channel to work on.
+  @param[in] Dimm            - Dimm to work on.
+  @param[in] Mr2Value        - The value of MR2 to setup.
+
+  @retval Nothing.
+**/
+void
+SetTcMr2ShadowReg (
+  IN MrcParameters *const MrcData,
+  IN const U32            Channel,
+  IN const U32            Dimm,
+  IN U32                  Mr2Value
+  )
+{
+  MrcDimmOut                          *DimmOut;
+  MCHBAR_CH0_CR_TC_MR2_SHADDOW_STRUCT TcMr2Shaddow;
+  U32                                 Offset;
+
+  Offset = MCHBAR_CH0_CR_TC_MR2_SHADDOW_REG +
+            ((MCHBAR_CH1_CR_TC_MR2_SHADDOW_REG - MCHBAR_CH0_CR_TC_MR2_SHADDOW_REG) * Channel);
+  TcMr2Shaddow.Data             = MrcReadCR (MrcData, Offset);
+  TcMr2Shaddow.Bits.MR2_sh_high = 0;
+  TcMr2Shaddow.Bits.MR2_sh_low  = 0;
+
+  DimmOut                       = &MrcData->SysOut.Outputs.Controller[0].Channel[Channel].Dimm[Dimm];
+  if ((DimmOut->SelfRefreshTemp) == TRUE) {
+    TcMr2Shaddow.Bits.SRT_avail |= MRC_BIT0 << Dimm;
+  }
+  ((MCHBAR_CH0_CR_TC_MR2_SHADDOW_STRUCT *) (&Mr2Value))->Bits.SRT_avail = 0;
+  TcMr2Shaddow.Data |= Mr2Value;
+
+  //
+  // Set address bit swizzle according to the DIMM number.
+  //
+  if (DimmOut->AddressMirrored == TRUE) {
+    TcMr2Shaddow.Bits.Addr_bit_swizzle |= MRC_BIT0 << Dimm;
+  }
+
+  MrcWriteCR (MrcData, Offset, TcMr2Shaddow.Data);
+  //
+  // MRC_DEBUG_MSG (&MrcData->Inputs.Debug, MSG_LEVEL_NOTE, "TC-MR2_SHADOW Channel %u register value = %Xh\n", Channel, TcMr2Shaddow.Data);
+  //
+  return;
+}
+
+/**
+@brief
+  This function executes the refresh configuration process.
+
+  @param[in] MrcData         - Include all MRC global data.
+
+  @retval Nothing.
+**/
+void
+MrcRefreshConfiguration (
+  IN MrcParameters *const MrcData
+  )
+{
+  MCMNTS_CR_TC_RFP_STRUCT TcRFP;
+  U32                     Offset;  
+  U8  Channel;
+
+  for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+    if (MrcChannelExist (&MrcData->SysOut.Outputs, Channel)) {
+      SetTcRftpReg (MrcData, Channel);
+      SetTcSrftpReg (MrcData, Channel);
+      SetTcZqCalReg (MrcData, Channel);
+
+      //
+      // set LP0 WM and OREF_RI to support high memory BW traffic
+      //
+      Offset = MCHBAR_CH0_CR_TC_RFP_REG +
+        ((MCHBAR_CH1_CR_TC_RFP_REG - MCHBAR_CH0_CR_TC_RFP_REG) * Channel);
+      TcRFP.Data = MrcReadCR (MrcData, Offset);
+      TcRFP.Bits.OREF_RI = 0xFF;
+      MrcWriteCR (MrcData, Offset, TcRFP.Data);
+      TcRFP.Data = MrcReadCR (MrcData, Offset);
+      MRC_DEBUG_MSG (
+        &MrcData->SysIn.Inputs.Debug,
+        MSG_LEVEL_NOTE,
+        "Ch%u: TC_RFP = %Xh\n OREF_RI = %u\n",
+        Channel,
+        TcRFP.Data,
+        TcRFP.Bits.OREF_RI
+        );
+    }
+  }
+
+  return;
+}
diff --git a/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/McConfiguration/MrcRefreshConfiguration.h b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/McConfiguration/MrcRefreshConfiguration.h
new file mode 100644
index 0000000..9909dcd
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/McConfiguration/MrcRefreshConfiguration.h
@@ -0,0 +1,173 @@
+/** @file
+  This module include MRC_RefreshConfiguration external data
+
+@copyright
+  Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved.
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement
+**/
+#ifndef _MrcRefreshConfiguration_h_
+#define _MrcRefreshConfiguration_h_
+
+#include "MrcTypes.h"
+#include "MrcApi.h"
+#include "McAddress.h"
+#include "MrcCommon.h"
+#include "MrcDdr3.h"
+#include "MrcOem.h"
+#include "MrcGlobal.h"
+
+///
+/// tDLLK values
+///
+#define tDLLK_VALUE         512
+
+///
+/// tXSOffset values
+///
+#define Offset_10nsec_800   4
+#define Offset_10nsec_1067  6
+#define Offset_10nsec_1333  7
+#define Offset_10nsec_1600  8
+#define Offset_10nsec_1867  10
+#define Offset_10nsec_2133  11
+#define Offset_10nsec_2400  12
+#define Offset_10nsec_2667  14
+
+///
+/// tMOD values. max(12nCK,15ns)
+///
+#define tMOD_800            12
+#define tMOD_1067           12
+#define tMOD_1333           12
+#define tMOD_1600           12
+#define tMOD_1867           14
+#define tMOD_2133           16
+#define tMOD_2400           18
+#define tMOD_2667           20
+
+///
+/// tZQOPER values.
+///
+#define tZQOPER_1600        256
+#define tZQOPER_1867        299
+#define tZQOPER_2133        342
+#define tZQOPER_2400        384
+#define tZQOPER_2667        427
+
+//
+// ZQCL and ZQCS values for LPDDR3, in [ps]
+//
+#define tZQCL_MIN           360000
+#define tZQCS_MIN           90000
+
+///
+/// tZQCS values.
+///
+#define tZQCS_1600          64
+#define tZQCS_1867          75
+#define tZQCS_2133          86
+#define tZQCS_2400          96
+#define tZQCS_2667          107
+
+//
+// ZQCS period values, in (tREFI * 128) units
+//
+#define ZQCS_PERIOD_DDR3    128   // tREFI * 128 = 7.8 us * 128 = 1ms
+#define ZQCS_PERIOD_LPDDR3  256   // tREFI * 128 = 3.9 us * 128 = 0.5ms
+
+/**
+@brief
+  This function returns the tZQOPER value.
+  tZQOPER = Defines the period required for ZQCL after SR exit.
+
+  @param[in] MrcData         - Include all MRC global data.
+  @param[in] Frequency       - The memory frequency.
+
+  @retval The tZQOPER value.
+**/
+extern
+U32
+tZQOPERGet (
+  IN MrcParameters *const MrcData,
+  IN const MrcFrequency Frequency
+  );
+
+/**
+@brief
+  This function returns the tMOD value.
+  tMOD = max(12nCK, 15ns) nCK change by the frequency.
+
+  @param[in] Frequency       - The memory frequency.
+
+  @retval The tMOD value.
+**/
+extern
+U32
+tMODGet (
+  IN const MrcFrequency Frequency
+  );
+
+/**
+@brief
+  This function returns the tZQCS value.
+
+  @param[in] MrcData         - Include all MRC global data.
+  @param[in] Frequency       - The memory frequency.
+
+  @retval The tZQCS value.
+**/
+extern
+U32
+tZQCSGet (
+  IN MrcParameters *const MrcData,
+  IN const MrcFrequency Frequency
+  );
+
+/**
+@brief
+  This function configures the TC_MR2_SHADDOW register and its fields.
+
+  @param[in] MrcData         - Include all MRC global data.
+  @param[in] Channel         - Channel to work on.
+  @param[in] Dimm            - Dimm to work on.
+  @param[in] Mr2Value        - The value of MR2 to setup.
+
+  @retval Nothing.
+**/
+extern
+void
+SetTcMr2ShadowReg (
+  IN MrcParameters *const MrcData,
+  IN const U32            Channel,
+  IN const U32            Dimm,
+  IN U32                  Mr2Value
+  );
+
+/**
+@brief
+  This function executes the refresh configuration process.
+
+  @param[in] MrcData         - Include all MRC global data.
+
+  @retval Nothing.
+**/
+extern
+void
+MrcRefreshConfiguration (
+  IN MrcParameters *const MrcData
+  );
+
+#endif
diff --git a/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/McConfiguration/MrcSchedulerParameters.c b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/McConfiguration/MrcSchedulerParameters.c
new file mode 100644
index 0000000..58d5e77
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/McConfiguration/MrcSchedulerParameters.c
@@ -0,0 +1,109 @@
+/** @file
+  This module configures the memory controller scheduler.
+
+@copyright
+  Copyright (c) 1999 - 2013 Intel Corporation. All rights reserved.
+
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement.
+**/
+
+//
+// Include files
+//
+#include "MrcSchedulerParameters.h"
+
+/**
+@brief
+  This function configures the memory controller scheduler.
+
+  @param[in] MrcData - Include all MRC global data.
+
+  @retval Nothing.
+**/
+void
+MrcSchedulerParametersConfig (
+  IN MrcParameters *const MrcData
+  )
+{
+  const MrcInput                       *Inputs;
+  MrcOutput                            *Outputs;
+  MCSCHEDS_CR_SCHED_CBIT_STRUCT        SchedCbit;
+  MCSCHEDS_CR_SCHED_SECOND_CBIT_STRUCT SchedSecondCbit;
+  U8                                   Channel;
+  U32                                  Offset;
+#ifdef ULT_FLAG
+  MCHBAR_CH0_CR_CMD_RATE_STRUCT        CmdRate;
+#endif // ULT_FLAG
+
+  Inputs  = &MrcData->SysIn.Inputs;
+  Outputs = &MrcData->SysOut.Outputs;
+  Channel = 0;
+  Offset  = 0;
+  if ((Inputs->CpuModel == cmHSW) && (Inputs->CpuStepping == csHswA0)) {
+    SchedCbit.Data = SCHED_CBIT_DEFAULT;
+  } else {
+    SchedCbit.Data = SCHED_CBIT_DEFAULT_B0;
+  }
+#ifdef ULT_FLAG
+  if (Inputs->CpuModel == cmHSW_ULT) {
+    SchedCbit.Bits.dis_odt = 1;
+    if (Outputs->DdrType == MRC_DDR_TYPE_LPDDR3) {
+      //
+      // LPDDR3 DDP and QDP (multi-die) packages share the same ZQ pin,
+      // so we need to serialize the ZQ calibration for different ranks.
+      //
+      SchedCbit.Bits.Serialize_ZQ = 1;
+
+      if (Inputs->LpddrDramOdt) {
+        //
+        // DRAM ODT is used
+        //
+        SchedCbit.Bits.dis_odt = 0;
+      }
+    }
+  }
+#endif
+
+  MrcWriteCrMulticast (MrcData, MCSCHEDS_CR_SCHED_CBIT_REG, SchedCbit.Data);
+
+  MrcWriteCrMulticast (MrcData, MCMNTS_CR_SC_WDBWM_REG, SC_WDBWM_DEFAULT);
+
+  if (Outputs->AsyncOdtDis) {
+    SchedSecondCbit.Data                = 0;
+    SchedSecondCbit.Bits.dis_async_odt  = 1;
+    MrcWriteCR8 (MrcData, MCSCHEDS_CR_SCHED_SECOND_CBIT_REG + 1, SchedSecondCbit.Data8[1]);
+  }
+
+#ifdef ULT_FLAG
+  //
+  // For LPDDR3, set Command Rate Limit to 3
+  //
+  if (Outputs->DdrType == MRC_DDR_TYPE_LPDDR3) {
+    for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+      if (MrcChannelExist (Outputs, Channel)) {
+        Offset = MCHBAR_CH0_CR_CMD_RATE_REG + ((MCHBAR_CH1_CR_CMD_RATE_REG - MCHBAR_CH0_CR_CMD_RATE_REG) * Channel);
+        CmdRate.Data = MrcReadCR (MrcData, Offset);
+        CmdRate.Bits.enable_cmd_rate_limit  = 1;
+        CmdRate.Bits.cmd_rate_limit         = 3;
+        MrcWriteCR (MrcData, Offset, CmdRate.Data);
+      }
+    }
+  }
+#endif
+
+
+  return;
+}
diff --git a/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/McConfiguration/MrcSchedulerParameters.h b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/McConfiguration/MrcSchedulerParameters.h
new file mode 100644
index 0000000..75dca03
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/McConfiguration/MrcSchedulerParameters.h
@@ -0,0 +1,49 @@
+/** @file
+  This module includes the memory controller scheduler parameters.
+
+@copyright
+  Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved.
+
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement.
+**/
+#ifndef _MrcSchedulerParameters_h_
+#define _MrcSchedulerParameters_h_
+
+#include "McAddress.h"
+#include "MrcTypes.h"
+#include "MrcApi.h"
+#include "MrcCommon.h"
+#include "MrcGlobal.h"
+
+#define SCHED_CBIT_DEFAULT    (0x00100030)
+#define SCHED_CBIT_DEFAULT_B0 (0x00100000)
+
+#define SC_WDBWM_DEFAULT      (0x553C3038)
+
+/**
+@brief
+  This function configures the memory controller scheduler.
+
+  @param[in] MrcData - Include all MRC global data.
+
+  @retval Nothing.
+**/
+void
+MrcSchedulerParametersConfig (
+  IN MrcParameters *const MrcData
+  );
+
+#endif // _MrcSchedulerParameters_h_
diff --git a/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/McConfiguration/MrcTimingConfiguration.c b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/McConfiguration/MrcTimingConfiguration.c
new file mode 100644
index 0000000..8f98dd2
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/McConfiguration/MrcTimingConfiguration.c
@@ -0,0 +1,921 @@
+/** @file
+  This module configures the memory controller timing parameters.
+
+@copyright
+  Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement.
+
+**/
+#include "MrcTimingConfiguration.h"
+
+/**
+@brief
+  This function returns the tCKE value for the specified frequency.
+
+  @param[in] DdrType    - DDR type
+  @param[in] Frequency  - The memory frequency.
+
+  @retval The tCKE value for the specified frequency.
+**/
+static
+U32
+tCKEValue (
+  IN MrcDdrType         DdrType,
+  IN const MrcFrequency Frequency
+  )
+{
+  U32 tCKE;
+
+#if (SUPPORT_LPDDR3 == SUPPORT)
+  if (DdrType == MRC_DDR_TYPE_LPDDR3) {
+    if (Frequency <= f1067) {
+      tCKE = tCKE_LPDDR_1067;
+    } else if (Frequency <= f1333) {
+      tCKE = tCKE_LPDDR_1333;
+    } else {
+      tCKE = tCKE_LPDDR_1600;
+    }
+    return tCKE;
+  }
+#endif // SUPPORT_LPDDR3
+
+  if (Frequency <= f800) {
+    tCKE = TCKE_800;
+  } else if (Frequency <= f1067) {
+    tCKE = TCKE_1067;
+  } else if (Frequency <= f1333) {
+    tCKE = TCKE_1333;
+  } else if (Frequency <= f1600) {
+    tCKE = TCKE_1600;
+  } else if (Frequency <= f1867) {
+    tCKE = TCKE_1867;
+  } else if (Frequency <= f2133) {
+    tCKE = TCKE_2133;
+  } else if (Frequency <= f2400) {
+    tCKE = TCKE_2400;
+  } else {
+    tCKE = TCKE_2667;
+  }
+
+  return tCKE;
+}
+
+/**
+@brief
+  This function returns the tXPDLL value for the specified frequency.
+
+  @param[in] Frequency - The memory frequency.
+
+  @retval The tXPDLL value for the specified frequency.
+**/
+static
+U32
+tXPDLLValue (
+  IN const MrcFrequency Frequency
+  )
+{
+  U32 tXPDLL;
+
+  if (Frequency <= f800) {
+    tXPDLL = TXPDLL_800;
+  } else if (Frequency <= f1067) {
+    tXPDLL = TXPDLL_1067;
+  } else if (Frequency <= f1333) {
+    tXPDLL = TXPDLL_1333;
+  } else if (Frequency <= f1600) {
+    tXPDLL = TXPDLL_1600;
+  } else if (Frequency <= f1867) {
+    tXPDLL = TXPDLL_1867;
+  } else if (Frequency <= f2133) {
+    tXPDLL = TXPDLL_2133;
+  } else if (Frequency <= f2400) {
+    tXPDLL = TXPDLL_2400;
+  } else {
+    tXPDLL = TXPDLL_2667;
+  }
+
+  return tXPDLL;
+}
+
+/**
+@brief
+  This function returns the tXP value for the specified frequency.
+
+  @param[in] DdrType   - DDR type
+  @param[in] Frequency - The memory frequency.
+  @param[in] NMode     - Command mode to lookup.
+
+  @retval The tXP value for the specified frequency.
+**/
+U32
+tXPValue (
+  IN MrcDdrType         DdrType,
+  IN const MrcFrequency Frequency,
+  IN U8                 NMode
+  )
+{
+  U32 tXP;
+
+#if (SUPPORT_LPDDR3 == SUPPORT)
+  if (DdrType == MRC_DDR_TYPE_LPDDR3) {
+    if (Frequency <= f1333) {
+      tXP = tXP_LPDDR_1333;
+    } else {
+      tXP = tXP_LPDDR_1600;
+    }
+  } else
+#endif // SUPPORT_LPDDR3
+  {
+    if (Frequency <= f1600) {
+      tXP = ((MC_tXP_1600_1N - 1) + NMode);
+    } else if (Frequency <= f1867) {
+      tXP = ((NMode <= 2) ? MC_tXP_1867_2N : MC_tXP_1867_3N);
+    } else if (Frequency <= f2133) {
+      tXP = (MC_tXP_2133_1N);
+    } else {
+      tXP = MC_tXP_MAX;
+    }
+  }
+  return (tXP);
+}
+
+/**
+@brief
+  This function returns the tAONPD value for the specified frequency.
+
+  @param[in] Frequency - The memory frequency.
+
+  @retval The tAONPD value for the specified frequency.
+**/
+static
+U32
+tAONPDValue (
+  IN const MrcFrequency Frequency
+  )
+{
+  U32 tAONPD;
+
+  if (Frequency <= f800) {
+    tAONPD = TAONPD_800;
+  } else if (Frequency <= f1067) {
+    tAONPD = TAONPD_1067;
+  } else if (Frequency <= f1333) {
+    tAONPD = TAONPD_1333;
+  } else if (Frequency <= f1600) {
+    tAONPD = TAONPD_1600;
+  } else if (Frequency <= f1867) {
+    tAONPD = TAONPD_1867;
+  } else if (Frequency <= f2133) {
+    tAONPD = TAONPD_2133;
+  } else if (Frequency <= f2400) {
+    tAONPD = TAONPD_2400;
+  } else {
+    tAONPD = TAONPD_2667;
+  }
+
+  return tAONPD;
+}
+
+/**
+@brief
+  This function sets up the TC-BANK register,
+  which includes the tRCD, tRP, tRAS, tRDPRE, tRTP, tWRPRE, and tRRD values.
+
+  @param[in, out] MrcData - Include all MRC global data.
+  @param[in]      Channel - Channel select.
+
+  @retval Nothing.
+**/
+static
+void
+SetTcBankReg (
+  IN OUT MrcParameters *const MrcData,
+  IN     const U32            Channel
+  )
+{
+  const MrcInput                *Inputs;
+  const MrcDebug                *Debug;
+  MrcOutput                     *Outputs;
+  MrcChannelOut                 *ChannelOut;
+  MrcTiming                     *Timing;
+  MCHBAR_CH0_CR_TC_BANK_STRUCT  CrTcBank;
+  U32                           tWRPRE;
+
+  Inputs      = &MrcData->SysIn.Inputs;
+  Debug       = &Inputs->Debug;
+  Outputs     = &MrcData->SysOut.Outputs;
+  ChannelOut  = &Outputs->Controller[0].Channel[Channel];
+  Timing      = &ChannelOut->Timing[Inputs->MemoryProfile];
+
+  //
+  // tWRPRE is = 4tCK + tWR + tWL = 4DCLK + tWR + tWL
+  //
+  tWRPRE                = 4 + Timing->tCWL + Timing->tWR;
+
+  CrTcBank.Data         = 0;
+  CrTcBank.Bits.tRCD    = MIN (MCHBAR_CH0_CR_TC_BANK_tRCD_MAX, Timing->tRCD);
+  CrTcBank.Bits.tRP     = MIN (MCHBAR_CH0_CR_TC_BANK_tRP_MAX, Timing->tRP);
+  CrTcBank.Bits.tRAS    = MIN (MCHBAR_CH0_CR_TC_BANK_tRAS_MAX, Timing->tRAS);
+  CrTcBank.Bits.tRDPRE  = MIN (MCHBAR_CH0_CR_TC_BANK_tRDPRE_MAX, Timing->tRTP);
+  CrTcBank.Bits.tWRPRE  = MIN (MCHBAR_CH0_CR_TC_BANK_tWRPRE_MAX, tWRPRE);
+  CrTcBank.Bits.tRRD    = MIN (MCHBAR_CH0_CR_TC_BANK_tRRD_MAX, Timing->tRRD);
+#ifdef ULT_FLAG
+  if (Outputs->DdrType == MRC_DDR_TYPE_LPDDR3) {
+    CrTcBank.Bits.tRPab_ext = MIN (MCHBAR_CH0_CR_TC_BANK_tRPab_ext_MAX, Timing->tRPab - Timing->tRP);
+  }
+#endif
+  MrcWriteCR (
+    MrcData,
+    MCHBAR_CH0_CR_TC_BANK_REG + ((MCHBAR_CH1_CR_TC_BANK_REG - MCHBAR_CH0_CR_TC_BANK_REG) * Channel),
+    CrTcBank.Data
+    );
+
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Channel %u:\n tRCD = %u\n", Channel, CrTcBank.Bits.tRCD);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, " tRP = %u\n", CrTcBank.Bits.tRP);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, " tRAS = %u\n", CrTcBank.Bits.tRAS);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, " tRDPRE = %u\n", CrTcBank.Bits.tRDPRE);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, " tWRPRE = %u\n", CrTcBank.Bits.tWRPRE);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, " tRRD = %u\n", CrTcBank.Bits.tRRD);
+#ifdef ULT_FLAG
+  if (Outputs->DdrType == MRC_DDR_TYPE_LPDDR3) {
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, " tRPab_ext = %u\n", CrTcBank.Bits.tRPab_ext);
+  }
+#endif
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, " TC_BANK = %Xh\n", CrTcBank.Data);
+
+  //
+  // Save in MrcData structure
+  //
+  ChannelOut->MchbarBANK = CrTcBank.Data;
+
+  return;
+}
+
+/**
+@brief
+  This function sets up the TC_BANK_RANK_D register,
+  which includes the tCL and tWCL values.
+
+  @param[in, out] MrcData - Include all MRC global data.
+  @param[in]      Channel - Channel select.
+
+  @retval Nothing.
+**/
+static
+void
+SetTcBankRankDReg (
+  IN OUT MrcParameters *const MrcData,
+  IN     const U32            Channel
+  )
+{
+  const MrcInput                      *Inputs;
+  const MrcDebug                      *Debug;
+  MrcOutput                           *Outputs;
+  MrcChannelOut                       *ChannelOut;
+  MrcTiming                           *Timing;
+  MCHBAR_CH0_CR_TC_BANK_RANK_D_STRUCT TcBankRankD;
+  U32                                 OdtReadDelay;
+#ifdef ULT_FLAG
+  U32                                 OdtWriteDelay;
+  U32                                 OdtWriteDuration;
+  U32                                 DclkPs;
+#endif // ULT_FLAG
+
+  Inputs      = &MrcData->SysIn.Inputs;
+  Outputs     = &MrcData->SysOut.Outputs;
+  Debug       = &Inputs->Debug;
+  ChannelOut  = &MrcData->SysOut.Outputs.Controller[0].Channel[Channel];
+  Timing      = &ChannelOut->Timing[Inputs->MemoryProfile];
+
+  //
+  // @todo: Need to make sure this value, after power on, follows the restrictions in the XML description.
+  //
+  OdtReadDelay                      = Timing->tCL - Timing->tCWL;
+
+  TcBankRankD.Data                = 0;
+  TcBankRankD.Bits.tWCL           = MIN (MCHBAR_CH0_CR_TC_BANK_RANK_D_tWCL_MAX, Timing->tCWL);
+  TcBankRankD.Bits.tCL            = MIN (MCHBAR_CH0_CR_TC_BANK_RANK_D_tCL_MAX, Timing->tCL);
+  TcBankRankD.Bits.tCPDED         = MCHBAR_CH0_CR_TC_BANK_RANK_D_tCPDED_DEF;
+  TcBankRankD.Bits.tPRPDEN        = MCHBAR_CH0_CR_TC_BANK_RANK_D_tPRPDEN_DEF;
+  TcBankRankD.Bits.Odt_Read_Delay = MIN (MCHBAR_CH0_CR_TC_BANK_RANK_D_Odt_Read_Delay_MAX, OdtReadDelay);
+
+#ifdef ULT_FLAG
+  if (Outputs->DdrType == MRC_DDR_TYPE_LPDDR3) {
+    if (Inputs->LpddrDramOdt) {
+      //
+      // Only ODT[0] is used in ULT, need to use it for both ranks
+      //
+      TcBankRankD.UltBits.Odt_Always_Rank0 = 1;
+    }
+
+    //
+    // Timing->tCWL has 1 extra clock because of tDQSS - subtract it here.
+    //
+    TcBankRankD.Bits.tWCL--;
+
+    //
+    // JEDEC Spec requires tCPDED should be 2 clocks for all LPDDR3 frequencies
+    //
+    TcBankRankD.Bits.tCPDED = 2;
+
+    DclkPs = Outputs->Qclkps * 2;
+
+    //
+    // Odt_Write_Delay = WL - 1 - RU(tODTon(max))
+    //
+    OdtWriteDelay = Timing->tCWL - 1 - (tODT_ON_MAX + DclkPs - 1) / DclkPs;
+
+    //
+    // Odt_Write_Duration = 6 + RU(tODTon(max)-tODToff(min)) - 6 + 1
+    //
+    OdtWriteDuration = 1 + (tODT_ON_MAX - tODT_OFF_MIN + DclkPs - 1) / DclkPs;
+
+    TcBankRankD.UltBits.Odt_Write_Delay    = MIN (MCHBAR_CH0_CR_TC_BANK_RANK_D_Odt_Write_Delay_Ult_MAX, OdtWriteDelay);
+    TcBankRankD.UltBits.Odt_Write_Duration = MIN (MCHBAR_CH0_CR_TC_BANK_RANK_D_Odt_Write_Duration_Ult_MAX, OdtWriteDuration);
+  }
+#endif // ULT_FLAG
+
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Channel %u:\n tCL = %u\n", Channel, TcBankRankD.Bits.tCL);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, " tWCL = %u\n", TcBankRankD.Bits.tWCL);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, " tCPDED = %u\n", TcBankRankD.Bits.tCPDED);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, " tPRPDEN = %u\n", TcBankRankD.Bits.tPRPDEN);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, " Odt_Read_Delay = %u\n", TcBankRankD.Bits.Odt_Read_Delay);
+#ifdef ULT_FLAG
+  if (Outputs->DdrType == MRC_DDR_TYPE_LPDDR3) {
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, " Odt_Write_Delay = %u\n", TcBankRankD.UltBits.Odt_Write_Delay);
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, " Odt_Write_Duration = %u\n", TcBankRankD.UltBits.Odt_Write_Duration);
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, " Odt_Always_Rank0 = %u\n", TcBankRankD.UltBits.Odt_Always_Rank0);
+  }
+#endif // ULT_FLAG
+
+  MrcWriteCR (
+    MrcData,
+    MCHBAR_CH0_CR_TC_BANK_RANK_D_REG + ((MCHBAR_CH1_CR_TC_BANK_RANK_D_REG - MCHBAR_CH0_CR_TC_BANK_RANK_D_REG) * Channel),
+    TcBankRankD.Data
+    );
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, " TC_BANK_RANK_D = %Xh\n", TcBankRankD.Data);
+
+  //
+  // Save in MrcData structure
+  //
+  ChannelOut->MchbarBANKRANKD = TcBankRankD.Data;
+
+  return;
+}
+
+/**
+@brief
+  This function sets up the TC_BANK_RANK_A register.
+  which includes the tCKE, tFAW, tRDRD, tRDRD_dr, tRDRD_dd, tRDPDEN, and command rate mode.
+
+  @param[in, out] MrcData - Include all MRC global data.
+  @param[in]      Channel - Channel select.
+
+  @retval Nothing.
+**/
+static
+void
+SetTcBankRankAReg (
+  IN OUT MrcParameters *const MrcData,
+  IN     const U32            Channel
+  )
+{
+  const MrcInput                      *Inputs;
+  const MrcDebug                      *Debug;
+  MrcOutput                           *Outputs;
+  MrcTiming                           *Timing;
+  MrcDdrType                          DdrType;
+  MCHBAR_CH0_CR_TC_BANK_RANK_A_STRUCT TcBankRankA;
+  U32                                 CRValue;
+
+  Inputs            = &MrcData->SysIn.Inputs;
+  Debug             = &Inputs->Debug;
+  Outputs           = &MrcData->SysOut.Outputs;
+  Timing            = &Outputs->Controller[0].Channel[Channel].Timing[Inputs->MemoryProfile];
+  DdrType           = Outputs->DdrType;
+  TcBankRankA.Data  = 0;
+
+  //
+  // Get the tCKE value.
+  //
+  CRValue               = tCKEValue (DdrType, Outputs->Frequency);
+  TcBankRankA.Bits.tCKE = MIN (MCHBAR_CH1_CR_TC_BANK_RANK_A_tCKE_MAX, CRValue);
+
+  //
+  // Get the command rate mode value.
+  // Use 3N mode during training steps
+  //
+#ifdef ULT_FLAG
+  if (Outputs->DdrType == MRC_DDR_TYPE_LPDDR3) {
+    //
+    // Need to use 1N mode for LPDDR
+    //
+    TcBankRankA.Bits.CMD_stretch = 0;
+  } else
+#endif // ULT_FLAG
+  {
+    TcBankRankA.Bits.CMD_stretch = MIN (MCHBAR_CH1_CR_TC_BANK_RANK_A_CMD_stretch_MAX, 3);
+  }
+  //
+  // Program tFAW value
+  //
+  TcBankRankA.Bits.tFAW = MIN (MCHBAR_CH1_CR_TC_BANK_RANK_A_tFAW_MAX, Timing->tFAW);
+
+  //
+  // Calculate tRDRD
+  //
+  TcBankRankA.Bits.tRDRD = MIN (MCHBAR_CH1_CR_TC_BANK_RANK_A_tRDRD_MAX, TCCD_ALL_FREQ);
+
+  //
+  // Calculate tRDRD_dr = BL/2 + max(tRTR, ODT(R,R,DR)) + tRPRE
+  //
+  CRValue = 4 + 1 + TRPRE_ALL_FREQ;
+
+#ifdef ULT_FLAG
+  if (Outputs->DdrType == MRC_DDR_TYPE_LPDDR3) {
+    //
+    // Increase tRDRD_dr from 6 to 7 DCLKs on LPDDR3
+    //
+    CRValue++;
+  }
+#endif // ULT_FLAG
+
+  TcBankRankA.Bits.tRDRD_dr = MIN (MCHBAR_CH1_CR_TC_BANK_RANK_A_tRDRD_dr_MAX, CRValue);
+
+  //
+  // Calculate tRDRD_dd = BL/2 + max(tRTR, ODT(R,R,DD)) + tRPRE
+  //
+  TcBankRankA.Bits.tRDRD_dd = MIN (MCHBAR_CH1_CR_TC_BANK_RANK_A_tRDRD_dd_MAX, CRValue);
+
+  //
+  // Calculate tRDPDEN = tCL + BL/2 +1
+  //
+  CRValue                   = Timing->tCL + 5;
+  TcBankRankA.Bits.tRDPDEN  = MIN (MCHBAR_CH1_CR_TC_BANK_RANK_A_tRDPDEN_MAX, CRValue);
+
+  //
+  // Disable command tri state before training.
+  //
+  TcBankRankA.Bits.CMD_3st = 1;
+
+  MrcWriteCR (
+    MrcData,
+    MCHBAR_CH0_CR_TC_BANK_RANK_A_REG + ((MCHBAR_CH1_CR_TC_BANK_RANK_A_REG - MCHBAR_CH0_CR_TC_BANK_RANK_A_REG) * Channel),
+    TcBankRankA.Data
+    );
+
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Channel %u:\n tCKE = %u\n", Channel, TcBankRankA.Bits.tCKE);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, " NMode = %u\n", TcBankRankA.Bits.CMD_stretch);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, " tFAW = %u\n", TcBankRankA.Bits.tFAW);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, " tRDRD = %u\n", TcBankRankA.Bits.tRDRD);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, " tRDRD_dr = %u\n", TcBankRankA.Bits.tRDRD_dr);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, " tRDRD_dd = %u\n", TcBankRankA.Bits.tRDRD_dd);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, " tRDPDEN = %u\n", TcBankRankA.Bits.tRDPDEN);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, " CMD_3st = %u\n", TcBankRankA.Bits.CMD_3st);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, " TC_BANK_RANK_A = %Xh\n", TcBankRankA.Data);
+
+  //
+  // Save in MrcData structure
+  //
+  Outputs->Controller[0].Channel[Channel].MchbarBANKRANKA = TcBankRankA.Data;
+
+  return;
+}
+
+/**
+@brief
+  This function sets up the TC_BANK_RANK_B register, which includes
+  Dec_WRD, tWRPDEN, tWRWR_dd, tWRWR_dr, tWRWR, tWRRD_dd, tWRRD_dr and tWRRD.
+
+  @param[in, out] MrcData - Include all MRC global data.
+  @param[in]      Channel - Channel select.
+
+  @retval Nothing.
+**/
+static
+void
+SetTcBankRankBReg (
+  IN OUT MrcParameters *const MrcData,
+  IN     const U32            Channel
+  )
+{
+  const MrcInput                        *Inputs;
+  const MrcDebug                        *Debug;
+  MrcOutput                             *Outputs;
+  MrcTiming                             *Timing;
+  MCHBAR_CH0_CR_TC_BANK_RANK_B_STRUCT   TcBankRankB;
+  MCHBAR_CH0_CR_TC_BANK_RANK_D_STRUCT   TcBankRankD;
+  MCHBAR_CH0_CR_SC_WR_ADD_DELAY_STRUCT  ScWrAddDelay;
+  U32                                   CRValue;
+  U32                                   tWRRD_dr;
+  U32                                   tWRWR_dr;
+  U32                                   Offset;
+
+  Inputs            = &MrcData->SysIn.Inputs;
+  Debug             = &Inputs->Debug;
+  Outputs           = &MrcData->SysOut.Outputs;
+  Timing            = &Outputs->Controller[0].Channel[Channel].Timing[Inputs->MemoryProfile];
+  TcBankRankB.Data  = 0;
+
+  //
+  // Calculate tWRRD = tCCD + tCWL + tWTR + max(tWrCAS2RdCAS_sr,ODT(W,R,SR)).
+  //
+  CRValue                 = TCCD_ALL_FREQ + Timing->tCWL + Timing->tWTR + 2;
+  TcBankRankB.Bits.tWRRD  = MIN (MCHBAR_CH0_CR_TC_BANK_RANK_B_tWRRD_MAX, CRValue);
+
+  //
+  // Calculate tWRRD_dr = tCWL-tCL + BL/2 + max(tWRDRDD,ODT(W,R,DR)) + tRPRE
+  //
+  tWRRD_dr = Timing->tCWL - Timing->tCL + 4 + 2 + TRPRE_ALL_FREQ;
+
+#ifdef ULT_FLAG
+  if (Outputs->DdrType == MRC_DDR_TYPE_LPDDR3) {
+    //
+    // tWRRD_dr is 8 for all LPDDR bins
+    //
+    tWRRD_dr = 8;
+  }
+#endif // ULT_FLAG
+
+  TcBankRankB.Bits.tWRRD_dr = MIN (MCHBAR_CH0_CR_TC_BANK_RANK_B_tWRRD_dr_MAX, tWRRD_dr);
+
+  //
+  // Calculate tWRRD_dd = tCWL-tCL + BL/2 + max(tWRDRDD,ODT(W,R,DR)) + tRPRE
+  //
+  TcBankRankB.Bits.tWRRD_dd = MIN (MCHBAR_CH0_CR_TC_BANK_RANK_B_tWRRD_dd_MAX, tWRRD_dr);
+
+  //
+  // Calculate tWRWR
+  //
+  TcBankRankB.Bits.tWRWR = MIN (MCHBAR_CH0_CR_TC_BANK_RANK_B_tWRWR_MAX, TCCD_ALL_FREQ);
+
+  //
+  // Calculate tWRWR_dr = BL/2 + max(tWWDR,ODT(W,W,DR)) + tWPRE
+  //
+  tWRWR_dr                  = 4 + 2 + TWPRE_ALL_FREQ;
+  TcBankRankB.Bits.tWRWR_dr = MIN (MCHBAR_CH0_CR_TC_BANK_RANK_B_tWRWR_dr_MAX, tWRWR_dr);
+
+  //
+  // Calculate tWRWR_dd = BL/2 + max(tWWDD,ODT(W,W,DR)) + tWPRE
+  //
+  TcBankRankB.Bits.tWRWR_dd = MIN (MCHBAR_CH0_CR_TC_BANK_RANK_B_tWRWR_dd_MAX, tWRWR_dr);
+
+  //
+  // Calculate tWRPDEN = tWR+tWL+BL/2
+  //
+  CRValue                   = Timing->tWR + Timing->tCWL + 4;
+  TcBankRankB.Bits.tWRPDEN  = MIN (MCHBAR_CH0_CR_TC_BANK_RANK_B_tWRPDEN_MAX, CRValue);
+
+  //
+  // Set Dec_WRD.
+  // Can be set to 1 only if tWCL is 6 or more.
+  //
+  Offset = MCHBAR_CH0_CR_TC_BANK_RANK_D_REG +
+    (MCHBAR_CH1_CR_TC_BANK_RANK_D_REG - MCHBAR_CH0_CR_TC_BANK_RANK_D_REG) * Channel;
+  TcBankRankD.Data = MrcReadCR (MrcData, Offset);
+  if (TcBankRankD.Bits.tWCL >= 6) {
+    TcBankRankB.Bits.Dec_WRD = 1;
+  } else {
+    TcBankRankB.Bits.Dec_WRD = 0;
+  }
+
+  MrcWriteCR (
+    MrcData,
+    MCHBAR_CH0_CR_TC_BANK_RANK_B_REG + ((MCHBAR_CH1_CR_TC_BANK_RANK_B_REG - MCHBAR_CH0_CR_TC_BANK_RANK_B_REG) * Channel),
+    TcBankRankB.Data
+    );
+
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Channel %u:\n tWRRD = %u\n", Channel, TcBankRankB.Bits.tWRRD);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, " tWRRD_dr = %u\n", TcBankRankB.Bits.tWRRD_dr);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, " tWRRD_dd = %u\n", TcBankRankB.Bits.tWRRD_dd);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, " tWRWR = %u\n", TcBankRankB.Bits.tWRWR);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, " tWRWR_dr = %u\n", TcBankRankB.Bits.tWRWR_dr);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, " tWRWR_dd = %u\n", TcBankRankB.Bits.tWRWR_dd);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, " tWRPDEN = %u\n", TcBankRankB.Bits.tWRPDEN);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, " Dec_WRD = %u\n", TcBankRankB.Bits.Dec_WRD);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, " TC_BANK_RANK_B = %Xh\n", TcBankRankB.Data);
+
+  //
+  // Save in MrcData structure
+  //
+  Outputs->Controller[0].Channel[Channel].MchbarBANKRANKB = TcBankRankB.Data;
+
+  //
+  // Set sc_wr_add_delay accordingly = 1 + Dec_WRD
+  //
+  CRValue                 = TcBankRankB.Bits.Dec_WRD + 1;
+  ScWrAddDelay.Data       = 0;
+  ScWrAddDelay.Bits.D1R1  = MIN (MCHBAR_CH0_CR_SC_WR_ADD_DELAY_D1R1_MAX, CRValue);
+  ScWrAddDelay.Bits.D1R0  = MIN (MCHBAR_CH0_CR_SC_WR_ADD_DELAY_D1R0_MAX, CRValue);
+  ScWrAddDelay.Bits.D0R1  = MIN (MCHBAR_CH0_CR_SC_WR_ADD_DELAY_D0R1_MAX, CRValue);
+  ScWrAddDelay.Bits.D0R0  = MIN (MCHBAR_CH0_CR_SC_WR_ADD_DELAY_D0R0_MAX, CRValue);
+  MrcWriteCR8 (
+    MrcData,
+    MCHBAR_CH0_CR_SC_WR_ADD_DELAY_REG +
+    ((MCHBAR_CH1_CR_SC_WR_ADD_DELAY_REG - MCHBAR_CH0_CR_SC_WR_ADD_DELAY_REG) * Channel),
+    (U8) ScWrAddDelay.Data
+    );
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, " SC_WR_ADD_Delay = %Xh\n", ScWrAddDelay.Data);
+
+  return;
+}
+
+/**
+@brief
+  This function sets up the TC_BANK_RANK_C register, which includes
+  TAONPD, tXP, tXPDLL, tRDWR, tRDWR_dr, and tRDWR_dd.
+
+  @param[in, out] MrcData - Include all MRC global data.
+  @param[in]      Channel - Channel select.
+
+  @retval Nothing.
+**/
+static
+void
+SetTcBankRankCReg (
+  IN OUT MrcParameters *const MrcData,
+  IN     const U32            Channel
+  )
+{
+  const MrcInput                      *Inputs;
+  const MrcDebug                      *Debug;
+  MrcOutput                           *Outputs;
+  MrcTiming                           *Timing;
+  MrcDdrType                          DdrType;
+  MCHBAR_CH0_CR_TC_BANK_RANK_C_STRUCT TcBankRankC;
+  U32                                 Value;
+  U32                                 DclkPs;
+
+  Inputs            = &MrcData->SysIn.Inputs;
+  Debug             = &Inputs->Debug;
+  Outputs           = &MrcData->SysOut.Outputs;
+  Timing            = &Outputs->Controller[0].Channel[Channel].Timing[Inputs->MemoryProfile];
+  DdrType           = Outputs->DdrType;
+  TcBankRankC.Data  = 0;
+
+  Value                   = tXPDLLValue (Outputs->Frequency);
+  TcBankRankC.Bits.tXPDLL = MIN (MCHBAR_CH0_CR_TC_BANK_RANK_C_tXPDLL_MAX, Value);
+
+  Value                   = tXPValue (DdrType, Outputs->Frequency, 3);
+  TcBankRankC.Bits.tXP    = MIN (MCHBAR_CH0_CR_TC_BANK_RANK_C_tXP_MAX, Value);
+
+  Value                   = tAONPDValue (Outputs->Frequency);
+  TcBankRankC.Bits.TAONPD = MIN (MCHBAR_CH0_CR_TC_BANK_RANK_C_TAONPD_MAX, Value);
+
+  //
+  // Calculate tRDWR = tCL-tCWL+tCCD+tWPRE+max(tRWSR,ODT(R,W,SR))
+  // tWPRE - Write Preamble
+  //
+  Value = Timing->tCL - Timing->tCWL + TCCD_ALL_FREQ + TWPRE_ALL_FREQ + 2;
+  //
+  // Add 1 for frequencies above 1333.
+  //
+  if (Outputs->Frequency > f1333) {
+    Value++;
+  }
+
+  DclkPs = Outputs->Qclkps * 2;
+
+#ifdef ULT_FLAG
+  if (DdrType == MRC_DDR_TYPE_LPDDR3) {
+    //
+    // tRDWR = tCL - tCWL + tDQSCK_max + tCCD + tWPRE + ElectricalTurnaround
+    //
+    Value = Timing->tCL - Timing->tCWL + (tDQSCK_MAX + DclkPs - 1) / DclkPs +
+      TCCD_ALL_FREQ + TWPRE_ALL_FREQ + 1;
+  }
+#endif // ULT_FLAG
+
+  TcBankRankC.Bits.tRDWR = MIN (MCHBAR_CH0_CR_TC_BANK_RANK_C_tRDWR_MAX, Value);
+
+  //
+  // Calculate tRDWR_dr = tCL-tCWL+tCCD+tWPRE+max(tRWSR,ODT(R,W,SR))
+  //
+  TcBankRankC.Bits.tRDWR_dr = MIN (MCHBAR_CH0_CR_TC_BANK_RANK_C_tRDWR_dr_MAX, Value);
+
+  //
+  // Calculate tRDWR_dd = tCL-tCWL+tCCD+tWPRE+max(tRWSR,ODT(R,W,SR))
+  //
+  TcBankRankC.Bits.tRDWR_dd = MIN (MCHBAR_CH0_CR_TC_BANK_RANK_C_tRDWR_dd_MAX, Value);
+
+  MrcWriteCR (
+    MrcData,
+    MCHBAR_CH0_CR_TC_BANK_RANK_C_REG + ((MCHBAR_CH1_CR_TC_BANK_RANK_C_REG - MCHBAR_CH0_CR_TC_BANK_RANK_C_REG) * Channel),
+    TcBankRankC.Data
+    );
+
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Channel %u:\n tXPDLL = %u\n", Channel, TcBankRankC.Bits.tXPDLL);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, " tXP = %u\n", TcBankRankC.Bits.tXP);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, " tAONPD = %u\n", TcBankRankC.Bits.TAONPD);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, " tRDWR = %u\n", TcBankRankC.Bits.tRDWR);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, " tRDWR_dr = %u\n", TcBankRankC.Bits.tRDWR_dr);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, " tRDWR_dd = %u\n", TcBankRankC.Bits.tRDWR_dd);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, " TC_BANK_RANK_C = %Xh\n", TcBankRankC.Data);
+
+  //
+  // Save in MrcData structure
+  //
+  Outputs->Controller[0].Channel[Channel].MchbarBANKRANKC = TcBankRankC.Data;
+
+  return;
+}
+
+/**
+@brief
+  This function configures the memory controller timings.
+
+  @param[in] MrcData - Include all MRC global data.
+
+  @retval Nothing.
+**/
+void
+MrcTimingConfiguration (
+  IN MrcParameters *const MrcData
+  )
+{
+  U8 Channel;
+
+  for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+    if (MrcChannelExist (&MrcData->SysOut.Outputs, Channel)) {
+      //
+      // setup TC-BANK register
+      //
+      SetTcBankReg (MrcData, Channel);
+
+      //
+      // setup TC-BANK_RANK_D register
+      //
+      SetTcBankRankDReg (MrcData, Channel);
+
+      //
+      // setup TC-BANK_RANK_A register
+      //
+      SetTcBankRankAReg (MrcData, Channel);
+
+      //
+      // setup TC-BANK_RANK_B register
+      //
+      SetTcBankRankBReg (MrcData, Channel);
+
+      //
+      // setup TC-BANK_RANK_C register
+      //
+      SetTcBankRankCReg (MrcData, Channel);
+    }
+  }
+
+  //
+  // Check RawCard Types and adjust Read ODT if needed
+  //
+  RdOdtStretch (MrcData);
+
+  return;
+}
+
+/**
+@brief
+  This function sets up the Read ODTD values based on RawCard types and adjusts the tDRRD2RD, tDDRD2RD, tDRRD2WR and tDDRD2WR
+
+  @param[in, out] MrcData - Include all MRC global data.
+
+  @retval Nothing.
+**/
+void
+RdOdtStretch (
+  IN OUT MrcParameters *const MrcData
+  )
+{
+  const MrcDebug        *Debug;
+  const MrcInput        *Inputs;
+  MrcControllerOut      *ControllerOut;
+  MrcChannelOut         *ChannelOut;
+  U8                    Channel;
+  U8                    ChBitMask;
+  U8                    RankMaskCh;
+  S8                    OdtStretch;
+#if SUPPORT_SODIMM == SUPPORT
+  MrcDimmOut            *DimmOut;
+  BOOL                  SoDimm;
+  U8                    Value;
+  U8                    Dimm;
+  U8                    DimmRawCardType[MAX_DIMMS_IN_CHANNEL];
+  MCHBAR_CH0_CR_TC_BANK_RANK_A_STRUCT     TcBankRankA;
+  MCHBAR_CH0_CR_TC_BANK_RANK_C_STRUCT     TcBankRankC;
+#endif //SUPPORT_SODIMM == SUPPORT
+
+  Inputs          = &MrcData->SysIn.Inputs;
+  Debug           = &Inputs->Debug;
+  ControllerOut   = &MrcData->SysOut.Outputs.Controller[0];
+
+  ChBitMask = 0;
+
+  for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+    ChannelOut  = &ControllerOut->Channel[Channel];
+    if (ChannelOut->ValidRankBitMask && (ChannelOut->DimmCount == 2)) {
+      ChBitMask |= (MRC_BIT0 << Channel);
+    }
+  }
+
+  for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+    if (!((MRC_BIT0 << Channel) & ChBitMask)) {
+      //
+      // Skip any channels that do not have 2 DIMMs populated
+      //
+      continue;
+    }
+
+    ChannelOut  = &ControllerOut->Channel[Channel];
+    RankMaskCh  = ChannelOut->ValidRankBitMask;
+    //
+    // Start with the most aggressive setting
+    //
+    OdtStretch = 6;
+
+#if SUPPORT_SODIMM == SUPPORT
+    SoDimm = FALSE;
+    for (Dimm = 0; Dimm < MAX_DIMMS_IN_CHANNEL; Dimm++) {
+      DimmOut = &ChannelOut->Dimm[Dimm];
+      if (((DimmOut->ModuleType == MRC_MODULE_TYPE_SODIMM) || (DimmOut->ModuleType == MRC_MODULE_72B_SO_UDIMM))
+        && (SoDimm == FALSE)) {
+        SoDimm = TRUE;
+      }
+      if (SoDimm) {
+        DimmRawCardType[Dimm] = DimmOut->ReferenceRawCard;
+      }
+    }
+
+    if (SoDimm) {
+      if ((DimmRawCardType[0] == rcF || DimmRawCardType[1] == rcF)
+          && (DimmRawCardType[0] != DimmRawCardType[1])) {
+        OdtStretch = 7;
+        MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE,"Rd Odt Stretch F\n");
+      }
+    }
+#endif //SUPPORT_SODIMM == SUPPORT
+    //
+    // Program Rdodtd value
+    //
+    UpdateTAParamOffset (MrcData, Channel, 0, rdodtd, OdtStretch, 1, 1, RankMaskCh);
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Selected RdOdtD Offset for channel %d is = %d\n", Channel, OdtStretch);
+
+#if SUPPORT_SODIMM == SUPPORT
+    if (OdtStretch > 6) {
+      TcBankRankA.Data = ChannelOut->MchbarBANKRANKA;
+      Value = (U8)(TcBankRankA.Bits.tRDRD_dr);
+      Value += OdtStretch - 6;
+      //
+      // Program Different Rank RD 2 RD value
+      //
+      UpdateTAParamOffset (MrcData, Channel, 0, drrd2rd, Value, 1, 1, RankMaskCh);
+      MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Selected DR RD2RD Offset for channel %d is = %d\n", Channel, Value);
+
+      Value = (U8)(TcBankRankA.Bits.tRDRD_dd);
+      Value += OdtStretch - 6;
+      //
+      // Program Different DIMM RD 2 RD value
+      //
+      UpdateTAParamOffset (MrcData, Channel, 0, ddrd2rd, Value, 1, 1, RankMaskCh);
+      MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Selected DD RD2RD Offset for channel %d is = %d\n", Channel, Value);
+
+      TcBankRankC.Data = ChannelOut->MchbarBANKRANKC;
+      Value = (U8)(TcBankRankC.Bits.tRDWR_dr);
+      Value += OdtStretch - 6;
+      //
+      // Program Different Rank RD 2 WR value
+      //
+      UpdateTAParamOffset (MrcData, Channel, 0, drrd2wr, Value, 1, 1, RankMaskCh);
+      MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Selected DR RD2WR Offset for channel %d is = %d\n", Channel, Value);
+
+      Value = (U8)(TcBankRankC.Bits.tRDWR_dd);
+      Value += OdtStretch - 6;
+      //
+      // Program Different DIMM RD 2 WR value
+      //
+      UpdateTAParamOffset (MrcData, Channel, 0, ddrd2wr, Value, 1, 1, RankMaskCh);
+      MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Selected DD RD2WR Offset for channel %d is = %d\n", Channel, Value);
+
+      Value = (U8)(TcBankRankC.Bits.tRDWR);
+      Value += OdtStretch - 6;
+      //
+      // Program Same Rank RD 2 WR value
+      //
+      UpdateTAParamOffset (MrcData, Channel, 0, srrd2wr, Value, 1, 1, RankMaskCh);
+      MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Selected SR RD2WR Offset for channel %d is = %d\n", Channel, Value);
+    }
+#endif //SUPPORT_SODIMM == SUPPORT
+  }
+
+}
diff --git a/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/McConfiguration/MrcTimingConfiguration.h b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/McConfiguration/MrcTimingConfiguration.h
new file mode 100644
index 0000000..c9bb6c3
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/McConfiguration/MrcTimingConfiguration.h
@@ -0,0 +1,167 @@
+/** @file
+  This module configures the memory controller timing parameters.
+
+@Copyright
+  Copyright (c) 1999 - 2013 Intel Corporation. All rights reserved.
+
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement.
+**/
+#ifndef _MrcTimingConfiguration_h_
+#define _MrcTimingConfiguration_h_
+
+#include "MrcTypes.h"
+#include "MrcApi.h"
+#include "McAddress.h"
+#include "MrcCommon.h"
+#include "MrcDdr3.h"
+#include "MrcGlobal.h"
+#include "MrcOem.h"
+#if SUPPORT_SODIMM == SUPPORT
+#include "MrcSpdProcessing.h"
+#endif //SUPPORT_SODIMM == SUPPORT
+
+///
+/// tCCD values.
+///
+#define TCCD_ALL_FREQ (4) ///< tCCD is = 4 DCLK for all frequencies up to 1600.
+///
+/// tWPRE values.
+///
+#define TWPRE_ALL_FREQ  (1) ///< tWPRE is = 1 DCLK for all frequencies up to 1600.
+///
+/// tRPRE values.
+///
+#define TRPRE_ALL_FREQ  (1) ///< tRPRE is = 1 DCLK for all frequencies up to 1600.
+///
+/// tCKE values.
+///
+#define TCKE_800  (3)
+#define TCKE_1067 (3)
+#define TCKE_1333 (4)
+#define TCKE_1600 (4)
+#define TCKE_1867 (5)
+#define TCKE_2133 (6)
+#define TCKE_2400 (6)
+#define TCKE_2667 (7)
+
+///
+/// tCKE values for LPDDR: max(7.5ns, 3nCK)
+///
+#define tCKE_LPDDR_1067 (4)
+#define tCKE_LPDDR_1333 (5)
+#define tCKE_LPDDR_1600 (6)
+
+///
+/// tXP values for LPDDR: max(7.5ns, 3nCK)
+///
+#define tXP_LPDDR_1333 (5)
+#define tXP_LPDDR_1600 (6)
+
+///
+/// tXPDLL values.
+///
+#define TXPDLL_800  (10)
+#define TXPDLL_1067 (13)
+#define TXPDLL_1333 (16)
+#define TXPDLL_1600 (20)
+#define TXPDLL_1867 (23)
+#define TXPDLL_2133 (26)
+#define TXPDLL_2400 (29)
+#define TXPDLL_2667 (32)
+
+///
+/// tAONPD values.
+///
+#define TAONPD_800  (4)
+#define TAONPD_1067 (5)
+#define TAONPD_1333 (6)
+#define TAONPD_1600 (7) ///< SNB had 8
+#define TAONPD_1867 (8)
+#define TAONPD_2133 (10)
+#define TAONPD_2400 (11)
+#define TAONPD_2667 (12)
+
+#define MC_tXP_1600_1N (5)
+#define MC_tXP_1867_2N (6)
+#define MC_tXP_1867_3N (7)
+#define MC_tXP_2133_1N (7)
+#define MC_tXP_MAX     (8) ///< The maximum value that the MC supports.
+
+///
+/// tODTon / tODToff values, in [ps]
+///
+#define tODT_ON_MIN   1750
+#define tODT_ON_MAX   3500
+#define tODT_OFF_MIN  1750
+#define tODT_OFF_MAX  3500
+
+///
+/// tDQSCK values, in [ps]
+///
+#define tDQSCK_MIN    2500
+#define tDQSCK_MAX    5500
+///
+/// Specified in PI-Ticks.  64 == 1 QClk
+///
+#define tDQSCK_DRIFT  64
+
+/**
+@brief
+  This function configures the memory controller timings.
+
+  @param[in] MrcData - Include all MRC global data.
+
+  @retval Nothing.
+**/
+extern
+void
+MrcTimingConfiguration (
+  IN MrcParameters *const MrcData
+  );
+
+/**
+@brief
+  This function returns the tXP value for the specified frequency.
+
+  @param[in] DdrType   - DDR type
+  @param[in] Frequency - The memory frequency.
+  @param[in] NMode     - Command mode to lookup.
+
+  @retval The tXP value for the specified frequency.
+**/
+extern
+U32
+tXPValue (
+  IN MrcDdrType         DdrType,
+  IN const MrcFrequency Frequency,
+  IN U8                 NMode
+  );
+
+/**
+@brief
+  This function sets up the Read ODTD values based on RawCard types and adjusts the tDRRD2RD, tDDRD2RD, tDRRD2WR and tDDRD2WR
+
+  @param[in, out] MrcData - Include all MRC global data.
+
+  @retval Nothing.
+**/
+extern
+void
+RdOdtStretch (
+  IN OUT MrcParameters *const MrcData
+  );
+
+#endif // _MrcTimingConfiguration_h_
diff --git a/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/ReadTraining/MrcReadDqDqs.c b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/ReadTraining/MrcReadDqDqs.c
new file mode 100644
index 0000000..7403971
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/ReadTraining/MrcReadDqDqs.c
@@ -0,0 +1,1207 @@
+/** @file
+  Once DQS is aligned against the clock in the receive enable training flow,
+  the second stage of the read training is the DQ/DQS training, aligning each
+  strobe with it's byte of data. The DQ/DQS training is once again using the
+  DDR read synchronization mode, in this mode a predetermined pattern is read
+  out of the DDR. The following algorithm is used to align the data sampling
+  to the best sampling point.
+
+@copyright
+  Copyright (c) 1999 - 2013 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement.
+
+**/
+
+//
+// Include files
+//
+#include "MrcReadDqDqs.h"
+
+/**
+  Perform Read MPR Training.
+  Center read DQ-DQS with MPR pattern.
+
+  @param[in, out] MrcData   - Include all MRC global data.
+
+  @retval MrcStatus - mrcSuccess or reason for failure.
+**/
+MrcStatus
+MrcReadMprTraining (
+  IN OUT MrcParameters *const MrcData
+  )
+{
+  const MrcInput                              *Inputs;
+  const MrcDebug                              *Debug;
+  MrcOutput                                   *Outputs;
+  MrcChannelOut                               *ChannelOut;
+  MrcStatus                                   Status;
+  U8                                          Channel;
+  U8                                          Rank;
+  U8                                          Byte;
+  U8                                          ChBitMask;
+  U8                                          RankMask;  // RankBitMask for both channels
+  U8                                          LoopCount;
+  S8                                          MPRCorrectionFactor;
+  S8                                          DqsDelay;
+  S32                                         CurrentPassingStart[MAX_CHANNEL][MAX_SDRAM_IN_DIMM];
+  S32                                         CurrentPassingEnd[MAX_CHANNEL][MAX_SDRAM_IN_DIMM];
+  S32                                         LargestPassingStart[MAX_CHANNEL][MAX_SDRAM_IN_DIMM];
+  S32                                         LargestPassingEnd[MAX_CHANNEL][MAX_SDRAM_IN_DIMM];
+  S32                                         cWidth;
+  S32                                         lWidth;
+  S32                                         Center;
+  S32                                         Center2;
+  BOOL                                        Pass;
+  BOOL                                        Lpddr;
+  U32                                         Offset;
+  U32                                         OdtSampExtendDelay;
+  MCHBAR_CH0_CR_REUT_CH_MISC_ODT_CTRL_STRUCT  ReutChMiscOdtCtrl;
+  MCDFXS_CR_REUT_GLOBAL_CTL_MCMAIN_STRUCT     ReutGlobalCtl;
+  DDRDATACH0_CR_DDRCRDATACONTROL0_STRUCT      DdrCrDataControl0;
+  DDRDATA0CH0_CR_DDRCRDATACONTROL2_STRUCT     DdrCrDataControl2;
+
+  Inputs  = &MrcData->SysIn.Inputs;
+  Debug   = &Inputs->Debug;
+  Outputs = &MrcData->SysOut.Outputs;
+  Status  = mrcSuccess;
+  Lpddr   = (Outputs->DdrType == MRC_DDR_TYPE_LPDDR3);
+
+  LoopCount = 10;
+  OdtSampExtendDelay  = 1 * HPET_MIN;
+
+  //
+  // Use basic addressing mode (open a page on a rank and keep writing/reading to it)
+  // Rotate through all 8 logical ranks
+  // LFSR and LMN disabled.
+  //
+  ChBitMask = Outputs->ValidChBitMask;
+  RankMask  = Outputs->ValidRankMask;
+
+  for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+    if (MrcChannelExist (Outputs, Channel)) {
+      ChannelOut = &Outputs->Controller[0].Channel[Channel];
+
+      //
+      // Set DQS Delay to 32
+      //
+      for (Byte = 0; Byte < Outputs->SdramCount; Byte++) {
+        for (Rank = 0; Rank < MAX_RANK_IN_CHANNEL; Rank++) {
+          if (MrcRankInChannelExist (MrcData, Rank, Channel)) {
+            //
+            // Update RxDqsP & RxDqsN - leave other parameter the same; can we update in the next loop or do it per channel
+            //
+            UpdateRxT (MrcData, Channel, Rank, Byte, 5, 32);
+          }
+        }
+      }
+
+      //
+      // Clear any old state in DataTrain Offset
+      //
+      MrcOemMemorySetDword (&ChannelOut->DataOffsetTrain[0], 0, Outputs->SdramCount);
+    }
+  }
+
+  //
+  // Setup REUT Engine
+  //
+  SetupIOTestMPR (MrcData, ChBitMask, LoopCount, NSOE, 0, 0);
+
+  //
+  /// @todo: Start with 0 for now.
+  //
+  MPRCorrectionFactor = 0;
+
+  for (Rank = 0; Rank < MAX_RANK_IN_CHANNEL; Rank++) {
+    if (!((MRC_BIT0 << Rank) & RankMask)) {
+      continue; // Skip if both channels empty
+    }
+
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Rank = %u\n", Rank);
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Channel\t0                1\nByte\t");
+    MRC_DEBUG_MSG (
+      Debug,
+      MSG_LEVEL_NOTE, (
+      Outputs->SdramCount == (MAX_SDRAM_IN_DIMM)
+      ) ? "0 1 2 3 4 5 6 7 8 0 1 2 3 4 5 6 7 8" : "0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7"
+      );
+
+    //
+    // Program MR3 and Mask RAS/WE to prevent scheduler for issuing non-Read commands
+    //
+    for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+      SelectReutRanks (MrcData, Channel, MRC_BIT0 << Rank, 0);
+      if (MrcRankInChannelExist (MrcData, Rank, Channel)) {
+        if (!Lpddr) {
+          Status = MrcWriteMRS (MrcData, Channel, (MRC_BIT0 << Rank), mrMR3, 0x4);
+        }
+
+        Offset  = MCHBAR_CH0_CR_REUT_CH_MISC_ODT_CTRL_REG +
+          ((MCHBAR_CH1_CR_REUT_CH_MISC_ODT_CTRL_REG - MCHBAR_CH0_CR_REUT_CH_MISC_ODT_CTRL_REG) * Channel);
+        ReutChMiscOdtCtrl.Data                  = MrcReadCR (MrcData, Offset);
+        ReutChMiscOdtCtrl.Bits.MPR_Train_DDR_On = 1;
+        MrcWriteCR (MrcData, Offset, ReutChMiscOdtCtrl.Data);
+      }
+    }
+
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\nDqsDelay");
+    for (DqsDelay = RMPR_DQS_START; DqsDelay < RMPR_DQS_STOP; DqsDelay += RMPR_DQS_STEP) {
+      MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\n% 5d\t", DqsDelay);
+
+      //
+      // Program DQS Delays and download the Reg File for the current rank.
+      //
+      Status = ChangeMargin (MrcData, RdT, DqsDelay, 0, 1, 0, 0, 0, 0, 0, 0, MrcRegFileStart);
+
+      for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+        if (!(MrcRankInChannelExist (MrcData, Rank, Channel))) {
+          MRC_DEBUG_MSG (
+            Debug,
+            MSG_LEVEL_NOTE,
+            (Channel != 0) ? "" : ((Outputs->SdramCount == MAX_SDRAM_IN_DIMM) ? "                  " : "                ")
+            );
+        } else {
+          ChannelOut = &Outputs->Controller[0].Channel[Channel];
+
+          for (Byte = 0; Byte < Outputs->SdramCount; Byte++) {
+            //
+            // Force on SenseAmp
+            //
+            Offset = DDRDATA0CH0_CR_DDRCRDATACONTROL2_REG +
+              ((DDRDATA0CH1_CR_DDRCRDATACONTROL2_REG - DDRDATA0CH0_CR_DDRCRDATACONTROL2_REG) * Channel) +
+              ((DDRDATA1CH0_CR_DDRCRDATACONTROL2_REG - DDRDATA0CH0_CR_DDRCRDATACONTROL2_REG) * Byte);
+            DdrCrDataControl2.Data              = ChannelOut->DqControl2[Byte].Data;
+            DdrCrDataControl2.Bits.ForceBiasOn  = 1;
+            DdrCrDataControl2.Bits.ForceRxOn    = 1;
+            DdrCrDataControl2.Bits.LeakerComp   = 0;
+            MrcWriteCR (MrcData, Offset, DdrCrDataControl2.Data);
+          }
+          //
+          // Enable RX Training mode. Turn on the ODT.
+          //
+          Offset = DDRDATACH0_CR_DDRCRDATACONTROL0_REG +
+            ((DDRDATACH1_CR_DDRCRDATACONTROL0_REG - DDRDATACH0_CR_DDRCRDATACONTROL0_REG) * Channel);
+          DdrCrDataControl0.Data = ChannelOut->DqControl0.Data;
+          if (!Lpddr) {
+            DdrCrDataControl0.Bits.ForceOdtOn = 1;
+          }
+          DdrCrDataControl0.Bits.RxTrainingMode = 1;
+
+          //
+          // Need to disable EnReadPreamble
+          //
+          DdrCrDataControl0.Bits.EnReadPreamble   = 0;
+          MrcWriteCrMulticast (MrcData, Offset, DdrCrDataControl0.Data);
+        }
+      }
+
+      Status = IoReset (MrcData);
+
+
+      //
+      // Start REUT and run for 1uS
+      //
+      ReutGlobalCtl.Data                    = 0;
+      ReutGlobalCtl.Bits.Global_Start_Test  = 1;
+      MrcWriteCR (MrcData, MCDFXS_CR_REUT_GLOBAL_CTL_MCMAIN_REG, ReutGlobalCtl.Data);
+
+      //
+      // Wait for test to start clearing errors.
+      //
+      MrcWait (MrcData, START_TEST_DELAY);
+
+      //
+      // Clear Results for Prior Test and wait to obtain results
+      //
+      Status = IoReset (MrcData);
+      MrcWait (MrcData, IO_RESET_DELAY);
+
+      //
+      // Stop REUT
+      //
+      ReutGlobalCtl.Data                  = 0;
+      ReutGlobalCtl.Bits.Global_Stop_Test = 1;
+      MrcWriteCR (MrcData, MCDFXS_CR_REUT_GLOBAL_CTL_MCMAIN_REG, ReutGlobalCtl.Data);
+
+
+      //
+      // Update results for all ch/bytes
+      //
+      for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+        if (!(MrcRankInChannelExist (MrcData, Rank, Channel))) {
+          continue;
+        }
+
+        for (Byte = 0; Byte < Outputs->SdramCount; Byte++) {
+          Offset = DDRDATA0CH0_CR_DATATRAINFEEDBACK_REG +
+            ((DDRDATA0CH1_CR_DATATRAINFEEDBACK_REG - DDRDATA0CH0_CR_DATATRAINFEEDBACK_REG) * Channel) +
+            ((DDRDATA1CH0_CR_DATATRAINFEEDBACK_REG - DDRDATA0CH0_CR_DATATRAINFEEDBACK_REG) * Byte);
+          Pass = (MrcReadCR (MrcData, Offset) == 1);
+
+          MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, Pass ? ". " : "# ");
+
+          if (DqsDelay == RMPR_DQS_START) {
+            if (Pass) {
+              CurrentPassingStart[Channel][Byte] = CurrentPassingEnd[Channel][Byte] = DqsDelay;
+              LargestPassingStart[Channel][Byte] = LargestPassingEnd[Channel][Byte] = DqsDelay;
+            } else {
+              CurrentPassingStart[Channel][Byte] = CurrentPassingEnd[Channel][Byte] = -33;
+              LargestPassingStart[Channel][Byte] = LargestPassingEnd[Channel][Byte] = -33;
+            }
+          } else {
+            if (Pass) {
+              if (CurrentPassingEnd[Channel][Byte] == (DqsDelay - RMPR_DQS_STEP)) {
+                CurrentPassingEnd[Channel][Byte] = DqsDelay;
+              } else {
+                CurrentPassingStart[Channel][Byte] = CurrentPassingEnd[Channel][Byte] = DqsDelay;
+              }
+              //
+              // Update Largest variables
+              //
+              cWidth  = CurrentPassingEnd[Channel][Byte] - CurrentPassingStart[Channel][Byte];
+              lWidth  = LargestPassingEnd[Channel][Byte] - LargestPassingStart[Channel][Byte];
+              if (cWidth > lWidth) {
+                LargestPassingStart[Channel][Byte]  = CurrentPassingStart[Channel][Byte];
+                LargestPassingEnd[Channel][Byte]    = CurrentPassingEnd[Channel][Byte];
+              }
+            }
+          }
+        }
+      }
+
+      for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+        if (!MrcRankInChannelExist (MrcData, Rank, Channel)) {
+          continue;
+        }
+        ChannelOut = &Outputs->Controller[0].Channel[Channel];
+
+        for (Byte = 0; Byte < Outputs->SdramCount; Byte++) {
+          //
+          // Restore orginal value
+          //
+          Offset = DDRDATA0CH0_CR_DDRCRDATACONTROL2_REG +
+            ((DDRDATA0CH1_CR_DDRCRDATACONTROL2_REG - DDRDATA0CH0_CR_DDRCRDATACONTROL2_REG) * Channel) +
+            ((DDRDATA1CH0_CR_DDRCRDATACONTROL2_REG - DDRDATA0CH0_CR_DDRCRDATACONTROL2_REG) * Byte);
+          MrcWriteCR (MrcData, Offset, ChannelOut->DqControl2[Byte].Data);
+        }
+
+        //
+        // Clear RxTrainingMode
+        //
+        Offset = DDRDATACH0_CR_DDRCRDATACONTROL0_REG +
+          ((DDRDATACH1_CR_DDRCRDATACONTROL0_REG - DDRDATACH0_CR_DDRCRDATACONTROL0_REG) * Channel);
+
+#ifdef ULT_FLAG
+        if (Lpddr) {
+          //
+          // For LPDDR need to disable OdtSampExtendEn before disabling RxTrainingMode,
+          // then re-enable OdtSampExtendEn (from the host struct)
+          //
+          DdrCrDataControl0.Bits.OdtSampExtendEn = 0;
+          MrcWriteCrMulticast (MrcData, Offset, DdrCrDataControl0.Data);
+          MrcWait (MrcData, OdtSampExtendDelay);
+
+          DdrCrDataControl0.Bits.RxTrainingMode = 0;
+          MrcWriteCrMulticast (MrcData, Offset, DdrCrDataControl0.Data);
+          MrcWait (MrcData, OdtSampExtendDelay);
+        }
+#endif // ULT_FLAG
+
+        MrcWriteCrMulticast (MrcData, Offset, ChannelOut->DqControl0.Data);
+      } // for Channel
+
+      Status = IoReset (MrcData);
+    } // for DqsDelay
+
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\n");
+
+    //
+    // Clean Up registers.
+    //
+    for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+      if (MrcRankInChannelExist (MrcData, Rank, Channel)) {
+        ChannelOut = &Outputs->Controller[0].Channel[Channel];
+
+        //
+        // MPR_TRAIN_DDR_ON bit will force a special command so clear it before MRS command
+        //
+        Offset = MCHBAR_CH0_CR_REUT_CH_MISC_ODT_CTRL_REG +
+          ((MCHBAR_CH1_CR_REUT_CH_MISC_ODT_CTRL_REG - MCHBAR_CH0_CR_REUT_CH_MISC_ODT_CTRL_REG) * Channel);
+        ReutChMiscOdtCtrl.Data                  = MrcReadCR (MrcData, Offset);
+        ReutChMiscOdtCtrl.Bits.MPR_Train_DDR_On = 0;
+        MrcWriteCR (MrcData, Offset, ReutChMiscOdtCtrl.Data);
+
+        if (!Lpddr) {
+          Status = MrcWriteMRS (MrcData, Channel, (MRC_BIT0 << Rank), mrMR3, 0x0);
+        }
+        //
+        // Clear up after test
+        //
+        MrcOemMemorySetDword (&ChannelOut->DataOffsetTrain[0], 0, Outputs->SdramCount);
+
+        MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "C%u.R%u: \tLeft\tRight\tWidth\tCenter\tRxDqsPN\n", Channel, Rank);
+        for (Byte = 0; Byte < Outputs->SdramCount; Byte++) {
+          lWidth = LargestPassingEnd[Channel][Byte] - LargestPassingStart[Channel][Byte];
+
+          //
+          // Error Handler if eye not found for all bytes
+          //
+          if (lWidth == 0) {
+            MRC_DEBUG_MSG (
+              Debug,
+              MSG_LEVEL_ERROR,
+              "\nERROR!! NO EYE found for Channel: %u Rank: %u Byte: %u \n",
+              Channel,
+              Rank,
+              Byte
+              );
+            return mrcReadMPRErr;
+          }
+
+          if (lWidth > RMPR_MIN_WIDTH) {
+            Center = LargestPassingStart[Channel][Byte] + lWidth / 2;
+          } else {
+            MRC_DEBUG_MSG (
+              Debug,
+              MSG_LEVEL_WARNING,
+              "\nWARNING!! lWidth <= %u for Channel: %u Rank: %u Byte: %u \n",
+              RMPR_MIN_WIDTH,
+              Channel,
+              Rank,
+              Byte
+              );
+            Center = 0;
+          }
+          //
+          // Based on previous data, the MPR center is not very good; Adjust it with a magical number
+          //
+          Center += MPRCorrectionFactor;
+          Center2                         = 32 + Center;
+          ChannelOut->RxDqsP[Rank][Byte]  = (U8) Center2;
+          ChannelOut->RxDqsN[Rank][Byte]  = (U8) Center2;
+          MRC_DEBUG_MSG (
+            Debug,
+            MSG_LEVEL_NOTE,
+            "  B%u: \t%d\t%d\t%d\t%d\t%d\n",
+            Byte,
+            LargestPassingStart[Channel][Byte],
+            LargestPassingEnd[Channel][Byte],
+            lWidth,
+            Center,
+            ChannelOut->RxDqsP[Rank][Byte]
+            );
+          //
+          //        MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Center = %d, RxDqsPN[%d][%d] = %d\n", Center, Channel, Byte, ChannelOut->RxDqsP[Rank][Byte]);
+          //
+        } // for Byte
+      }
+    } // for Channel
+  } // for Rank
+
+  //
+  // Now program the DQS center values on populated ranks, data is taken from the host struct.
+  // Need to do it after all ranks are trained, because we need to keep the same DQS value on all ranks
+  // during the training.
+  //
+  for (Rank = 0; Rank < MAX_RANK_IN_CHANNEL; Rank++) {
+    for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+      if (MrcRankInChannelExist (MrcData, Rank, Channel)) {
+        for (Byte = 0; Byte < Outputs->SdramCount; Byte++) {
+          UpdateRxT (MrcData, Channel, Rank, Byte, 0xFF, 0);
+        }
+      }
+    }
+  }
+
+  //
+  // Clean up after Test.  Download the Reg file of the last rank used.
+  //
+  Status  = ChangeMargin (MrcData, RdT, 0, 0, 1, 0, 0, 0, 0, 0, 0, MrcRegFileCurrent);
+  Status  = IoReset (MrcData);
+  return Status;
+}
+
+/**
+  Peform Read Timing Centering.
+  Center Rx DQS-DQ using moderate pattern with 1D eye
+
+  @param[in] MrcData         - Include all MRC global data.
+
+  @retval MrcStatus       - if it succeded returns mrcSuccess
+**/
+MrcStatus
+MrcReadTimingCentering (
+  IN     MrcParameters *const MrcData
+  )
+{
+  MrcOutput *Outputs;
+  U8        ResetPerBit;
+  U8        LoopCount;
+
+  Outputs = &MrcData->SysOut.Outputs;
+  ResetPerBit = 1;
+
+  LoopCount   = 10;
+
+  return DQTimeCentering1D (MrcData, Outputs->ValidChBitMask, RdT, ResetPerBit, LoopCount);
+}
+
+/**
+  Peform Read Timing Centering in 2D.
+  Final read timing centering using 2D algorithm and per bit optimization
+
+  @param[in] MrcData         - Include all MRC global data.
+
+  @retval MrcStatus       - if it succeded returns mrcSuccess
+**/
+MrcStatus
+MrcReadTimingCentering2D (
+  IN     MrcParameters *const MrcData
+  )
+{
+  const MrcInput  *Inputs;
+  const MrcDebug  *Debug;
+  MrcOutput       *Outputs;
+  MrcStatus       Status;
+  U8              EnPerBit;
+  U8              EnRxDutyCycle;
+  U8              ResetPerBit;
+  U8              LoopCount;
+  U8              En2D;
+
+  Inputs        = &MrcData->SysIn.Inputs;
+  Debug         = &Inputs->Debug;
+  Outputs       = &MrcData->SysOut.Outputs;
+  EnPerBit      = 1;
+  EnRxDutyCycle = 0;
+  ResetPerBit   = 1;
+  LoopCount     = 15;
+  En2D          = 0;
+
+  MRC_DEBUG_MSG (
+    Debug,
+    MSG_LEVEL_NOTE,
+    "\n\nCalling with EnRxDutyCycle = %d, EnPerBit = %d, ResetPerBit = %d En2D = %d\n",
+    EnRxDutyCycle,
+    EnPerBit,
+    ResetPerBit,
+    En2D
+    );
+
+  Status = DataTimeCentering2D (
+            MrcData,
+            Outputs->MarginResult,
+            Outputs->ValidChBitMask,
+            RdT,
+            EnPerBit,
+            EnRxDutyCycle,
+            ResetPerBit,
+            LoopCount,
+            En2D
+            );
+  if (mrcSuccess == Status) {
+    EnPerBit      = 0;
+    EnRxDutyCycle = 1;
+    ResetPerBit   = 0;
+    En2D          = 1;
+    MRC_DEBUG_MSG (
+      Debug,
+      MSG_LEVEL_NOTE,
+      "\n\nCalling with EnRxDutyCycle = %d, EnPerBit = %d, ResetPerBit = %d En2D = %d\n",
+      EnRxDutyCycle,
+      EnPerBit,
+      ResetPerBit,
+      En2D
+      );
+
+    Status = DataTimeCentering2D (
+              MrcData,
+              Outputs->MarginResult,
+              Outputs->ValidChBitMask,
+              RdT,
+              EnPerBit,
+              EnRxDutyCycle,
+              ResetPerBit,
+              LoopCount,
+              En2D
+              );
+  }
+
+  return Status;
+}
+
+/**
+  Peform Read Voltage Centering in 2D.
+  Note: This function currently only supports param = RdV
+
+  @param[in,out] MrcData     - Include all MRC global data.
+  @param[in,out] MarginByte  - Pointer to Marging Results data structure
+  @param[in]     ChBitMask   - Channel bit mask.
+  @param[in]     Param       - {0:RcvEn, 1:RdT, 2:WrT, 3: WrDqsT, 4:RdV, 5:WrV, 6:WrLevel,
+                                8:WrTBit, 9:RdTBit, 10:RdVBit,
+                                16:RdFan2, 17:WrFan2, 32:RdFan3, 32:WrFan3}
+                                ONLY RdV is allowed in this function
+  @param[in]     EnPerBit    - Option to enable per bit margining
+  @param[in]     ResetPerBit - Option to Reset PerBit Deskew to middle value before byte training
+  @param[in]     LoopCount   - Loop count
+  @param[in]     En2D        - Option to only run center at nominal Vref point
+
+  @retval MrcStatus - If it succeded return mrcSuccess
+**/
+MrcStatus
+ReadVoltageCentering2D (
+  IN OUT MrcParameters *const MrcData,
+  IN OUT U32                  MarginByte[MAX_RESULT_TYPE][MAX_RANK_IN_CHANNEL][MAX_CHANNEL][MAX_SDRAM_IN_DIMM][MAX_EDGES],
+  IN     U8                   ChBitMask,
+  IN     U8                   Param,
+  IN     U8                   EnPerBit,
+  IN     U8                   ResetPerBit,
+  IN     U8                   LoopCount,
+  IN     U8                   En2D
+  )
+{
+  const S8                                TimePoints[] = { 0, -8, 8 };
+  const U8                                EHWeights[sizeof (TimePoints)] = { 1, 1, 1 };
+  const MrcInput                          *Inputs;
+  const MrcDebug                          *Debug;
+  MrcOutput                               *Outputs;
+  MrcChannelOut                           *ChannelOut;
+  MrcStatus                               Status;
+  U8                                      ResultType;
+  U8                                      Channel;
+  U8                                      Byte;
+  U8                                      Rank;
+  U8                                      bit;
+  U8                                      lcloop;
+  U8                                      tim;
+  U8                                      paramB;
+  U8                                      paramT;
+  U8                                      BMap[MAX_SDRAM_IN_DIMM];
+  S8                                      SumEH;
+  S8                                      SumEHSign;
+  U8                                      MaxTscale;
+  U8                                      SaveLC;
+  U16                                     mode;
+  S32                                     center[MAX_CHANNEL][MAX_SDRAM_IN_DIMM];
+  S32                                     value0[MAX_CHANNEL][MAX_SDRAM_IN_DIMM];
+  U32                                     BERStats[4];
+  U32                                     TimScale[MAX_CHANNEL][MAX_SDRAM_IN_DIMM];
+  S32                                     CenterSumByte[MAX_CHANNEL][MAX_SDRAM_IN_DIMM];
+  S32                                     CenterSumBit[MAX_CHANNEL][MAX_SDRAM_IN_DIMM][MAX_BITS];
+  U32                                     marginbit[MAX_CHANNEL][MAX_SDRAM_IN_DIMM][MAX_BITS][MAX_EDGES];
+  U32                                     EyeShape[3][MAX_CHANNEL][MAX_SDRAM_IN_DIMM][MAX_EDGES];
+  U32                                     Offset;
+  MCHBAR_CH0_CR_REUT_CH_ERR_CTL_STRUCT    ReutChErrCtl;
+  DDRDATA0CH0_CR_RXOFFSETVDQ_STRUCT       RxOffsetVdq;
+
+  Inputs    = &MrcData->SysIn.Inputs;
+  Debug     = &Inputs->Debug;
+  Outputs   = &MrcData->SysOut.Outputs;
+  Status    = mrcSuccess;
+  SumEH     = 0;
+  MaxTscale = 12;
+  MrcOemMemorySet ((U8 *) BERStats, 0, sizeof (BERStats));
+  for (lcloop = 0; lcloop < (sizeof (BMap) / sizeof (BMap[0])); lcloop++) {
+    BMap[lcloop] = lcloop;
+  }
+  //
+  // Assume rank0 is always popuplated
+  //
+  if (Param == RdV) {
+    paramB = RdVBit;
+    paramT = RdT;
+  } else {
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_ERROR, "Error Handler: Unknown Margin Parameter\n");
+    Status = mrcReadVoltage2DError;
+    return Status;
+  }
+  //
+  /// @todo: Need to check if we can enable it for A0 or not
+  // Outputs->EnDumRd = 1;
+  // SOE = 10b ( Stop on All Byte Groups Error )
+  //
+  //
+  /// @todo: Will enable the DQ tests instead of basic in the future
+  //  SetupIOTestDQ (MrcData, ChBitMask, LoopCount, ABGSOE, 0, 0);
+  //
+  SetupIOTestBasicVA (MrcData, ChBitMask, LoopCount, ABGSOE, 0, 0, 8);
+  //
+  // Calculate SumEH for use in weighting equations
+  //
+  for (tim = 0; tim < sizeof (TimePoints); tim++) {
+    SumEH += EHWeights[tim];
+
+    //
+    // Loop once at nominal Vref point
+    //
+    if (En2D == 0) {
+      tim = sizeof (TimePoints);
+    }
+  }
+  //
+  // SumEH is used as divisor, make sure is never 0
+  //
+  if (SumEH == 0) {
+    SumEH = 1;
+  }
+  //
+  // Reset PerBit Deskew to middle value before Byte training
+  // Amplifier voltage offset for bit[x] of the DQ Byte.
+  // {0: Most negative offset,... 8: 0 offset, ... 15: Most postive offset}
+  //
+  if (ResetPerBit == 1) {
+    //
+    // EnMultiCast=1, 0,0,0,0, UpdateHost=1, SkipWait=0
+    //
+    Status = ChangeMargin (MrcData, paramB, 0x88888888, 0, 1, 0, 0, 0, 0, 1, 0, MrcRegFileStart);
+  }
+  //
+  // Select rank for REUT test
+  //
+  ChBitMask = 0;
+  for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+    ChannelOut = &Outputs->Controller[0].Channel[Channel];
+    ChBitMask |= SelectReutRanks (MrcData, Channel, ChannelOut->ValidRankBitMask, 0);
+    if (!MrcChannelExist (Outputs, Channel)) {
+      continue;
+    }
+    //
+    // Clear any old state in DataTrain Offset
+    //
+    MrcOemMemorySetDword (&ChannelOut->DataOffsetTrain[0], 0, Outputs->SdramCount);
+  }
+  //
+  // ####################################################
+  // ################  Initialize EW/EH variables  ######
+  // ####################################################
+  //
+  Status      = GetMarginByte (MrcData, Outputs->MarginResult, paramT, 0, 0xF);
+  ResultType  = GetMarginResultType (paramT);
+
+#ifdef MRC_DEBUG_PRINT
+  if (En2D) {
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\n### Measure Eye Height, per BYTE, at ALL (2D) Timing Points\n");
+  } else {
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\n### Measure Eye Height, per BYTE, at NOMINAL Timing\n");
+  }
+
+  for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+    if (!(ChBitMask & (MRC_BIT0 << Channel))) {
+      continue;
+    }
+
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Channel %d", Channel);
+    if (Channel == 0) {
+      for (Byte = 0; Byte < Outputs->SdramCount; Byte++) {
+        MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "        ");
+      }
+    }
+  }
+
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\nByte    ");
+  for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+    if (!(ChBitMask & (MRC_BIT0 << Channel))) {
+      continue;
+    }
+
+    for (Byte = 0; Byte < Outputs->SdramCount; Byte++) {
+      MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%d       ", Byte);
+    }
+  }
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\nTScale\t");
+#endif // MRC_DEBUG_PRINT
+  //
+  // Update TimScale to have the appropriate eye width (read from last saved parameters)
+  //
+  for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+    if (!(ChBitMask & (MRC_BIT0 << Channel))) {
+      continue;
+    }
+
+    ChannelOut = &Outputs->Controller[0].Channel[Channel];
+
+    for (Byte = 0; Byte < Outputs->SdramCount; Byte++) {
+      if (En2D > 0) {
+        TimScale[Channel][Byte] =
+          (
+            MarginByte[ResultType][0][Channel][Byte][0] +
+            MarginByte[ResultType][0][Channel][Byte][1]
+          ) /
+          20;
+      } else {
+        TimScale[Channel][Byte] = 1;
+      }
+      //
+      // It is possible sumT is 0.
+      //
+      if (!(TimScale[Channel][Byte]) || (TimScale[Channel][Byte] > MaxTscale)) {
+        TimScale[Channel][Byte] = MaxTscale;
+      }
+
+      MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%d\t", TimScale[Channel][Byte]);
+    }
+  }
+
+  Status      = GetMarginByte (MrcData, Outputs->MarginResult, Param, 0, 0xF);
+  ResultType  = GetMarginResultType (Param);
+
+  //
+  // ####################################################
+  // ######   Measure Eye Height at all Timing Points  #####
+  // ####################################################
+  //
+  //
+  // Loop through all the Time Points to Test
+  //
+  for (tim = 0; tim < sizeof (TimePoints); tim++) {
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\n\nRdTime\t");
+
+    //
+    // Setup Timing Offset for this point
+    //
+    for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+      if (!(ChBitMask & (MRC_BIT0 << Channel))) {
+        continue;
+      }
+
+      for (Byte = 0; Byte < Outputs->SdramCount; Byte++) {
+        value0[Channel][Byte] = (S32) (TimePoints[tim] * TimScale[Channel][Byte]) / MaxTscale;
+        Status = ChangeMargin (MrcData, paramT, value0[Channel][Byte], 0, 0, Channel, 0, Byte, 0, 1, 0, MrcRegFileCurrent);
+        MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%d\t", value0[Channel][Byte]);
+      }
+    }
+    //
+    // Run Margin Test
+    //
+    mode = 0;
+    Status = MrcGetBERMarginByte (
+              MrcData,
+              Outputs->MarginResult,
+              ChBitMask,
+              0,
+              0xFF,
+              Param,
+              mode,
+              BMap,
+              1,
+              MAX_POSSIBLE_VREF,
+              0,
+              BERStats
+              );
+
+#ifdef MRC_DEBUG_PRINT
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\nLo-Hi\t");
+    for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+      if (!(ChBitMask & (MRC_BIT0 << Channel))) {
+        continue;
+      }
+
+      for (Byte = 0; Byte < Outputs->SdramCount; Byte++) {
+        MRC_DEBUG_MSG (
+          Debug,
+          MSG_LEVEL_NOTE,
+          "%d %d\t",
+          MarginByte[ResultType][0][Channel][Byte][0],
+          MarginByte[ResultType][0][Channel][Byte][1]
+          );
+      }
+    }
+
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\nCenter\t");
+#endif // MRC_DEBUG_PRINT
+    //
+    // Store Results
+    //
+    for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+      if (ChBitMask & (MRC_BIT0 << Channel)) {
+
+        for (Byte = 0; Byte < Outputs->SdramCount; Byte++) {
+          center[Channel][Byte] = (S32)(MarginByte[ResultType][0][Channel][Byte][1] -
+                                        MarginByte[ResultType][0][Channel][Byte][0]);
+          if (tim == 0) {
+            CenterSumByte[Channel][Byte] = 0;
+          }
+          //
+          // Calculate weight for this point
+          //
+          CenterSumByte[Channel][Byte] += EHWeights[tim] * center[Channel][Byte];
+
+          MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%d\t", center[Channel][Byte] / 20);
+
+          //
+          // Record edges for use in per bit margining
+          //
+          EyeShape[tim][Channel][Byte][0] = MarginByte[ResultType][0][Channel][Byte][0];
+          EyeShape[tim][Channel][Byte][1] = MarginByte[ResultType][0][Channel][Byte][1];
+        }
+      }
+    }
+    //
+    // Loop once at nominal Vref point
+    //
+    if (En2D == 0) {
+      tim = sizeof (TimePoints);
+    }
+  }
+
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\n\nWtdCntr\t");
+  //
+  // ####################################################
+  // ###########   Center Results per Byte   ############
+  // ####################################################
+  //
+  for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+    if (!(ChBitMask & (MRC_BIT0 << Channel))) {
+      continue;
+    }
+
+    ChannelOut = &Outputs->Controller[0].Channel[Channel];
+
+    //
+    // Calculate CenterPoint.  Round to Nearest Int
+    //
+    for (Byte = 0; Byte < Outputs->SdramCount; Byte++) {
+      SumEHSign                     = (CenterSumByte[Channel][Byte] < 0) ? (-1) : 1;
+
+      CenterSumByte[Channel][Byte]  = (CenterSumByte[Channel][Byte] + 10 * (SumEHSign * SumEH)) / (20 * SumEH);
+      MRC_DEBUG_MSG(Debug, MSG_LEVEL_NOTE,"%d\t", CenterSumByte[Channel][Byte] / 2);
+
+      //
+      // Apply new centerpoint
+      // step size for RxVref is about 7.8mv AND for RxVrefOffset is about 3.9mv
+      //
+      ChannelOut->RxVref[Byte] = (U8) ((S32) ChannelOut->RxVref[Byte] + (CenterSumByte[Channel][Byte] / 2));
+
+      for (Rank = 0; Rank < MAX_RANK_IN_CHANNEL; Rank++) {
+        if (MrcRankInChannelExist (MrcData, Rank, Channel)) {
+          UpdateRxT (MrcData, Channel, Rank, Byte, 0xFF, 0);
+        }
+      }
+      //
+      // Update the Eye Edges
+      //
+      for (tim = 0; tim < sizeof (TimePoints); tim++) {
+        EyeShape[tim][Channel][Byte][0] = (S32) EyeShape[tim][Channel][Byte][0] + (10 * CenterSumByte[Channel][Byte]);
+        EyeShape[tim][Channel][Byte][1] = (S32) EyeShape[tim][Channel][Byte][1] - (10 * CenterSumByte[Channel][Byte]);
+
+        //
+        // Loop once at nominal Vref point
+        //
+        if (En2D == 0) {
+          tim = sizeof (TimePoints);
+        }
+      }
+      //
+      // Update MrcData for future tests (MarginResult points back to MrcData)
+      // EyeShape for Vref 0 is assumed to have the best shape for future tests.
+      //
+      MarginByte[ResultType][0][Channel][Byte][0] = EyeShape[0][Channel][Byte][0];
+      MarginByte[ResultType][0][Channel][Byte][1] = EyeShape[0][Channel][Byte][1];
+    }
+
+    //
+    // Clear up after test
+    //
+    MrcOemMemorySetDword (&ChannelOut->DataOffsetTrain[0], 0, Outputs->SdramCount);
+
+    //
+    // Propagate new settings from the RegFile to the Pads
+    //
+    MrcDownloadRegFile (MrcData, Channel, 1, 0, MrcRegFileCurrent, 0, 1, 0);
+  }
+
+#ifdef MRC_DEBUG_PRINT
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\nRdVref\t");
+  for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+    if (!(ChBitMask & (MRC_BIT0 << Channel))) {
+      continue;
+    }
+    ChannelOut = &Outputs->Controller[0].Channel[Channel];
+    for (Byte = 0; Byte < Outputs->SdramCount; Byte++) {
+      MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%d\t", (S8) ChannelOut->RxVref[Byte]);
+    }
+  }
+  //
+  // MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\n");
+  // MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\nPerByte Margins after per BYTE Centering\nLo-Hi   ");
+  //
+#endif // MRC_DEBUG_PRINT
+  //
+  // ####################################################
+  // ############    Measure Eye Height Per BIT   ########
+  // ####################################################
+  //
+  if (EnPerBit) {
+
+    MRC_DEBUG_MSG (
+      Debug,
+      MSG_LEVEL_NOTE, (
+      En2D
+      ) ? "\n### Measure Eye Height, per BIT, at ALL (2D) Timing Points\n" :
+      "\n### Measure Eye Height, per BIT, at NOMINAL Timing\n"
+      );
+
+    //
+    // Stop on all lane fail
+    //
+    for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+      if (ChBitMask & (MRC_BIT0 << Channel))
+      {
+#ifdef MRC_DEBUG_PRINT
+        MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Channel      %d", Channel);
+        if (Channel == 0) {
+          for (Byte = 0; Byte < Outputs->SdramCount; Byte++) {
+            MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\t\t\t\t\t\t");
+          }
+        }
+#endif // MRC_DEBUG_PRINT
+        //
+        // SOE = 11b ( Stop on All Lanes Error )
+        //
+        Offset = MCHBAR_CH0_CR_REUT_CH_ERR_CTL_REG + ((MCHBAR_CH1_CR_REUT_CH_ERR_CTL_REG - MCHBAR_CH0_CR_REUT_CH_ERR_CTL_REG) * Channel);
+        ReutChErrCtl.Data = 0;
+
+        ReutChErrCtl.Bits.Selective_Error_Enable_Chunk = MCHBAR_CH0_CR_REUT_CH_ERR_CTL_Selective_Error_Enable_Chunk_MAX;
+        ReutChErrCtl.Bits.Selective_Error_Enable_Cacheline = MCHBAR_CH0_CR_REUT_CH_ERR_CTL_Selective_Error_Enable_Cacheline_MAX;
+        ReutChErrCtl.Bits.Stop_On_Error_Control = ALSOE;
+        ReutChErrCtl.Bits.Stop_on_Nth_Error     = 1;
+        MrcWriteCR (MrcData, Offset, ReutChErrCtl.Data);
+      }
+    }
+
+#ifdef MRC_DEBUG_PRINT
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\n");
+    for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+      if (ChBitMask & (MRC_BIT0 << Channel)) {
+        for (Byte = 0; Byte < Outputs->SdramCount; Byte++) {
+          MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "             Byte % 24d ", Byte);
+        }
+      }
+    }
+
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\n");
+#endif // MRC_DEBUG_PRINT
+    //
+    // Loop through all the Vref Points to Test
+    //
+    SaveLC = Outputs->DQPatLC;
+    for (tim = 0; tim < sizeof (TimePoints); tim++) {
+      //
+      // Setup Timing Offset for this point
+      //
+      for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+        if (ChBitMask & (MRC_BIT0 << Channel)) {
+
+          for (Byte = 0; Byte < Outputs->SdramCount; Byte++) {
+            value0[Channel][Byte] = (S32) (TimePoints[tim] * TimScale[Channel][Byte]) / MaxTscale;
+            Status = ChangeMargin (MrcData, paramT, value0[Channel][Byte], 0, 0, Channel, 0, Byte, 0, 1, 0, MrcRegFileStart);
+
+            //
+            // Amplifier voltage offset for bit[x] of the DQ Byte.
+            // {0: Most negative offset,... 8: 0 offset, ... 15: Most postive offset}
+            //
+            for (bit = 0; bit < MAX_BITS; bit++) {
+              marginbit[Channel][Byte][bit][0] = marginbit[Channel][Byte][bit][1] = 8;
+            }
+          }
+        }
+      }
+      //
+      // Run Margin Test
+      // Loop through 2 times.  Once at low loop count and Once at high loopcount
+      // Improves runtime
+      // @todo: Need 2 loops below if not using BASICVA
+      //
+      for (lcloop = 0; lcloop < 1; lcloop++) {
+        Outputs->DQPatLC  = (lcloop == 0) ? 1 : SaveLC;
+        mode              = 0;
+        Status            = MrcGetMarginBit (MrcData, ChBitMask, 0, marginbit, EyeShape[tim], paramB, mode, 15);
+      }
+      //
+      // Store Results
+      //
+      for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+        if (ChBitMask & (MRC_BIT0 << Channel)) {
+
+          for (Byte = 0; Byte < Outputs->SdramCount; Byte++) {
+            for (bit = 0; bit < MAX_BITS; bit++) {
+              center[Channel][Byte] = ((marginbit[Channel][Byte][bit][1] - 8) - (8 - marginbit[Channel][Byte][bit][0]));
+              if (tim == 0) {
+                CenterSumBit[Channel][Byte][bit] = 0;
+              }
+              //
+              // Calculate weight for this point
+              //
+              CenterSumBit[Channel][Byte][bit] += EHWeights[tim] * center[Channel][Byte];
+            }
+          }
+        }
+      }
+      //
+      // Loop once at nominal Vref point
+      //
+      if (En2D == 0) {
+        tim = sizeof (TimePoints);
+      }
+    } // END OF TIM LOOP
+    //
+    // ####################################################
+    // ############   Center Result Per BIT  ##############
+    // ####################################################
+    //
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\nWgted Center ");
+    for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+      if (!(ChBitMask & (MRC_BIT0 << Channel))) {
+        continue;
+      }
+
+      ChannelOut = &Outputs->Controller[0].Channel[Channel];
+
+      //
+      // Calculate and apply CenterPoint.  Round to Nearest Int
+      //
+      for (Byte = 0; Byte < Outputs->SdramCount; Byte++) {
+        RxOffsetVdq.Data = 0;
+
+        for (bit = 0; bit < MAX_BITS; bit++) {
+          SumEHSign                         = (CenterSumBit[Channel][Byte][bit] < 0) ? (-1) : 1;
+
+          CenterSumBit[Channel][Byte][bit]  = (CenterSumBit[Channel][Byte][bit] + (SumEHSign * SumEH)) / (2 * SumEH);
+
+          //
+          // Centerpoint needs to be added to starting DqPb value
+          //
+          CenterSumBit[Channel][Byte][bit] += (S32) ChannelOut->RxDqVrefPb[0][Byte][bit].Center;
+
+          //
+          // Check for saturation
+          //
+          if (CenterSumBit[Channel][Byte][bit] > 15) {
+            CenterSumBit[Channel][Byte][bit] = 15;
+          } else if (CenterSumBit[Channel][Byte][bit] < 0) {
+            CenterSumBit[Channel][Byte][bit] = 0;
+          }
+
+          MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%x   ", CenterSumBit[Channel][Byte][bit]);
+
+          //
+          // Update MrcData
+          //
+          ChannelOut->RxDqVrefPb[0][Byte][bit].Center = (U8) CenterSumBit[Channel][Byte][bit];
+
+          RxOffsetVdq.Data |= (CenterSumBit[Channel][Byte][bit] << (DDRDATA0CH0_CR_RXOFFSETVDQ_Lane0_WID * bit));
+        }
+        //
+        // Apply and propagate new centerpoint
+        //
+        Status = ChangeMargin (MrcData, RdVBit, RxOffsetVdq.Data, 0, 0, Channel, 0, Byte, 0, 0, 0, MrcRegFileCurrent);
+        MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "           ");
+      }
+      //
+      // Clear up after test
+      //
+      MrcOemMemorySetDword (&ChannelOut->DataOffsetTrain[0], 0, Outputs->SdramCount);
+    }
+  } // END PERBIT LOOP
+
+/// @attention - This is used to determine if the PerBit routines are correct.  Left for sanity.
+/*
+#ifdef MRC_DEBUG_PRINT
+    for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+      if (ChBitMask & (MRC_BIT0 << Channel)) {
+
+        ChannelOut = &Outputs->Channel[Channel];
+
+        for (Byte = 0; Byte < Outputs->SdramCount; Byte++) {
+          Offset = DDRDATA0CH0_CR_RXOFFSETVDQ_REG +
+            ((DDRDATA0CH1_CR_RXOFFSETVDQ_REG - DDRDATA0CH0_CR_RXOFFSETVDQ_REG) * Channel) +
+            ((DDRDATA1CH0_CR_RXOFFSETVDQ_REG - DDRDATA0CH0_CR_RXOFFSETVDQ_REG) * Byte);
+          MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\nRdVref = % 3d   RdVBit = 0x%08X", (S8) ChannelOut->RxVref[Byte],
+                         MrcReadCR (MrcData, Offset));
+        }
+      }
+    }
+#endif // MRC_DEBUG_PRINT
+*/
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\n");
+  //
+  // Clean up after test
+  //
+  Outputs->EnDumRd  = 0;
+  Status            = ChangeMargin (MrcData, paramT, 0, 0, 1, 0, 0, 0, 0, 1, 0, MrcRegFileCurrent);
+
+  return Status;
+}
+
+/**
+  Peform Read Voltage Centering in 2D.
+  Note: This function currently only supports param = RdV
+
+  @param[in] MrcData       - Include all MRC global data.
+
+  @retval MrcStatus       - if it succeded return mrcSuccess
+**/
+MrcStatus
+MrcReadVoltageCentering2D (
+  IN     MrcParameters *const MrcData
+  )
+{
+  MrcOutput *Outputs;
+  MrcStatus Status;
+  U8        EnPerBit;
+  U8        ResetPerBit;
+  U8        LoopCount;
+  U8        En2D;
+
+  Outputs   = &MrcData->SysOut.Outputs;
+
+  EnPerBit    = 1;
+  ResetPerBit = 1;
+  LoopCount   = 15;
+  En2D        = 0;
+  Status = ReadVoltageCentering2D (
+            MrcData,
+            Outputs->MarginResult,
+            Outputs->ValidChBitMask,
+            RdV,
+            EnPerBit,
+            ResetPerBit,
+            LoopCount,
+            En2D
+            );
+
+  if (mrcSuccess == Status) {
+    //
+    // EnPerBit = 0; ResetPerbit = 0; loopcount = 10; En2D=1
+    //
+    EnPerBit    = 0;
+    ResetPerBit = 0;
+    LoopCount   = 15;
+    En2D        = 1;
+    Status = ReadVoltageCentering2D (
+              MrcData,
+              Outputs->MarginResult,
+              Outputs->ValidChBitMask,
+              RdV,
+              EnPerBit,
+              ResetPerBit,
+              LoopCount,
+              En2D
+              );
+  }
+
+  return Status;
+}
diff --git a/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/ReadTraining/MrcReadDqDqs.h b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/ReadTraining/MrcReadDqDqs.h
new file mode 100644
index 0000000..e0c717a
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/ReadTraining/MrcReadDqDqs.h
@@ -0,0 +1,97 @@
+/** @file
+  Read DQ/DQS training definitions.
+
+@copyright
+  Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved.
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement.
+**/
+
+#ifndef _MrcReadDqDqs_h_
+#define _MrcReadDqDqs_h_
+
+#include "McAddress.h"
+#include "MrcTypes.h"
+#include "MrcCommon.h"
+#include "MrcGlobal.h"
+
+#define RMPR_DQS_START (-32)
+#define RMPR_DQS_STOP  (32)
+
+#define RMPR_DQS_STEP  (1)
+
+#define RMPR_MIN_WIDTH (12)
+
+/**
+@brief
+  Perform Read MPR Training.
+  Center read DQ-DQS with MPR pattern.
+
+  @param[in, out] MrcData   - Include all MRC global data.
+
+  @retval MrcStatus - mrcSuccess or reason for failure.
+**/
+extern
+MrcStatus
+MrcReadMprTraining (
+  IN OUT MrcParameters *const MrcData
+  );
+
+/**
+@brief
+  Peform Read Timing Centering.
+  Center Rx DQS-DQ using moderate pattern with 1D eye
+
+  @param[in] MrcData         - Include all MRC global data.
+
+  @retval MrcStatus       - if it succeded returns mrcSuccess
+**/
+extern
+MrcStatus
+MrcReadTimingCentering (
+  IN     MrcParameters *const MrcData
+  );
+
+/**
+@brief
+  Peform Read Timing Centering in 2D.
+  Final read timing centering using 2D algorithm and per bit optimization
+
+  @param[in] MrcData         - Include all MRC global data.
+
+  @retval MrcStatus       - if it succeded returns mrcSuccess
+**/
+extern
+MrcStatus
+MrcReadTimingCentering2D (
+  IN     MrcParameters *const MrcData
+  );
+
+/**
+@brief
+  Peform Read Voltage Centering in 2D.
+  Note: This function currently only supports param = RdV
+
+  @param[in] MrcData       - Include all MRC global data.
+
+  @retval MrcStatus       - if it succeded return mrcSuccess
+**/
+extern
+MrcStatus
+MrcReadVoltageCentering2D (
+  IN     MrcParameters *const MrcData
+  );
+
+#endif // _MrcReadDqDqs_h_
diff --git a/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/ReadTraining/MrcReadReceiveEnable.c b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/ReadTraining/MrcReadReceiveEnable.c
new file mode 100644
index 0000000..3a49188
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/ReadTraining/MrcReadReceiveEnable.c
@@ -0,0 +1,1155 @@
+/** @file
+  Implementation of the receive enable algorithm.
+  Receive enable training is made out of two stages, the first is finding the
+  DQS rising edge for each DRAM device, and the second is determining the
+  roundtrip latency by locating the preamble cycle.
+
+@copyright
+  Copyright (c) 1999 - 2013 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement.
+
+**/
+#include "MrcReadReceiveEnable.h"
+
+///
+/// Local defines
+///
+
+#define RCV_EN_CENTER_LC (17)
+
+/**
+@brief
+  Perform receive enable training.
+  Optimize RcvEn timing with MPR pattern
+
+  @param[in, out] MrcData - Include all MRC global data.
+
+  @retval MrcStatus -  if succeeded, return mrcSuccess
+**/
+MrcStatus
+MrcReadLevelingTraining (
+  IN OUT MrcParameters *const MrcData
+  )
+{
+  const MRC_REUTAddress REUTAddress = {{0, 0, 0, 0},    // Start
+                                       {0, 0, 0, 1023}, // Stop
+                                       {0, 0, 0, 0},    // Order
+                                       {0, 0, 0, 0},    // IncRate
+                                       {0, 0, 0, 1}};   // IncValue
+  const U8              RLStep0 = 8;
+  const MrcInput        *Inputs;
+  const MrcDebug        *Debug;
+  MrcOutput             *Outputs;
+  MrcControllerOut      *ControllerOut;
+  MrcChannelOut         *ChannelOut;
+  MrcStatus             Status;
+  MrcProfile            Profile;
+  U8                    NumSamples;
+  U8                    FineStep;
+  U8                    DumArr[7];
+  U8                    Channel;
+  U8                    Rank;
+  U8                    Byte;
+  U8                    ByteN;     // ByteNumber
+  U8                    ByteNTimes2;
+  U8                    ChBitMask;
+  U8                    RankMask;  // RankBitMask for both channels
+  U8                    Done;
+  U8                    Inc;
+  U16                   RLStart;
+  U16                   RLStop;
+  U16                   RLDelay;
+  U16                   ChResult[MAX_CHANNEL];
+  U16                   ChMask;
+  U32                   CRValue;
+  U32                   Offset;
+  U32                   RtIoComp;
+  U32                   RtLatency;
+  S32                   InitialPassingStart[MAX_CHANNEL][MAX_SDRAM_IN_DIMM];
+  S32                   InitialPassingEnd[MAX_CHANNEL][MAX_SDRAM_IN_DIMM];
+  S32                   CurrentPassingStart[MAX_CHANNEL][MAX_SDRAM_IN_DIMM];
+  S32                   CurrentPassingEnd[MAX_CHANNEL][MAX_SDRAM_IN_DIMM];
+  S32                   LargestPassingStart[MAX_CHANNEL][MAX_SDRAM_IN_DIMM];
+  S32                   LargestPassingEnd[MAX_CHANNEL][MAX_SDRAM_IN_DIMM];
+  S32                   IncPreAmble[MAX_CHANNEL][MAX_SDRAM_IN_DIMM];
+  S32                   iWidth;
+  S32                   cWidth;
+  S32                   lWidth;
+  S32                   Center;
+  S32                   Width;
+  BOOL                  Pass;
+  MRC_WDBPattern        WDBPattern;
+  U8                    Temp;
+  U16                   TDqsCkDrift;
+#ifdef ULT_FLAG
+  U32                   DclkPs;
+#endif // ULT_FLAG
+
+  DDRDATACH0_CR_DDRCRDATACONTROL0_STRUCT  DdrCrDataControl0;
+  DDRDATA0CH0_CR_DDRCRDATACONTROL2_STRUCT DdrCrDataControl2;
+  MCHBAR_CH0_CR_SC_IO_LATENCY_STRUCT      ScIoLatency;
+  DDRDATA0CH0_CR_DATATRAINFEEDBACK_STRUCT DataTrainFeedback;
+
+  WDBPattern.IncRate  = 32;
+  WDBPattern.Start    = 0;
+  WDBPattern.Stop     = 9;
+  WDBPattern.DQPat    = BasicVA;
+  Status              = mrcSuccess;
+  Done                = 0;
+  Inputs              = &MrcData->SysIn.Inputs;
+  Debug               = &Inputs->Debug;
+  Outputs             = &MrcData->SysOut.Outputs;
+  ControllerOut       = &Outputs->Controller[0];
+  ChBitMask           = Outputs->ValidChBitMask;
+  RankMask            = Outputs->ValidRankMask;
+  Profile             = Inputs->MemoryProfile;
+  TDqsCkDrift         = tDQSCK_DRIFT;  // Pull in RcvEna by 1 QClk for Traditional.
+
+#ifdef ULT_FLAG
+#endif
+
+  MrcOemMemorySet (DumArr, 1, sizeof (DumArr));
+
+  NumSamples = 6;
+  FineStep   = 1;
+
+  RtIoComp  = 0;
+  RtLatency = 0;
+
+  switch (Inputs->CpuModel) {
+    case cmCRW:
+      RtIoComp  = MRC_ROUND_TRIP_IO_COMPENSATION_2_CHANNEL_A0;
+      RtLatency = HW_ROUNDT_LAT_DEFAULT_VALUE_A0;
+      break;
+
+    case cmHSW_ULT:
+      RtIoComp  = MRC_ROUND_TRIP_IO_COMPENSATION_2_CHANNEL_ULT_A0;
+      RtLatency = HW_ROUNDT_LAT_DEFAULT_VALUE_ULT_A0;
+      break;
+
+    case cmHSW:
+    default:
+      RtIoComp = (Inputs->CpuStepping > csHswA0) ? MRC_ROUND_TRIP_IO_COMPENSATION_2_CHANNEL_B0 :
+        MRC_ROUND_TRIP_IO_COMPENSATION_2_CHANNEL_A0;
+      RtLatency = (Inputs->CpuStepping > csHswA0) ? HW_ROUNDT_LAT_DEFAULT_VALUE_B0 :
+        HW_ROUNDT_LAT_DEFAULT_VALUE_A0;
+      break;
+  }
+
+  //
+  // CmdPat=PatRd, NumCL=2, LC=7, REUTAddress, SOE=0,
+  // WDBPattern, EnCADB=0, EnCKE=0, SubSeqWait=8
+  //
+  SetupIOTest (MrcData, ChBitMask, PatRd, 2, NumSamples + 1, &REUTAddress, 0, &WDBPattern, 0, 0, 8);
+
+  //
+  // Prepare Channel and Rank bit mask & Enable RLMode, force Odt and SAmp.
+  //
+  for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+    if (!(MrcChannelExist (Outputs, Channel))) {
+      continue;
+    }
+    ChannelOut = &ControllerOut->Channel[Channel];
+
+    //
+    // Enable ReadLeveling Mode and Force On ODT and SenseAmp
+    //
+    for (Byte = 0; Byte < Outputs->SdramCount; Byte++) {
+      Offset = DDRDATA0CH0_CR_DDRCRDATACONTROL2_REG +
+        ((DDRDATA0CH1_CR_DDRCRDATACONTROL2_REG - DDRDATA0CH0_CR_DDRCRDATACONTROL2_REG) * Channel) +
+        ((DDRDATA1CH0_CR_DDRCRDATACONTROL2_REG - DDRDATA0CH0_CR_DDRCRDATACONTROL2_REG) * Byte);
+      DdrCrDataControl2.Data            = ChannelOut->DqControl2[Byte].Data;
+      DdrCrDataControl2.Bits.ForceRxOn  = 1;
+      MrcWriteCR (MrcData, Offset, DdrCrDataControl2.Data);
+    }
+    Offset = DDRDATACH0_CR_DDRCRDATACONTROL0_REG +
+      ((DDRDATACH1_CR_DDRCRDATACONTROL0_REG - DDRDATACH0_CR_DDRCRDATACONTROL0_REG) * Channel);
+    DdrCrDataControl0.Data = ChannelOut->DqControl0.Data;
+
+#ifdef ULT_FLAG
+    if (Outputs->DdrType == MRC_DDR_TYPE_LPDDR3) {
+      //
+      // W/A for b4618574 - @todo: remove for HSW ULT C0
+      // Can't have ForceOdtOn together with Leaker, disable LPDDR mode during this training step
+      // LPDDR_Mode is restored at the end of this function from the host structure.
+      //
+      DdrCrDataControl0.Bits.LPDDR_Mode = 0;
+      MrcWriteCrMulticast (MrcData, Offset, DdrCrDataControl0.Data);
+    }
+#endif // ULT_FLAG
+
+    DdrCrDataControl0.Bits.ForceOdtOn     = 1;
+    DdrCrDataControl0.Bits.RLTrainingMode = 1;
+    MrcWriteCrMulticast (MrcData, Offset, DdrCrDataControl0.Data);
+
+    //
+    // Set initial IO Latency and IO_COMP
+    //
+    Offset = MCHBAR_CH0_CR_SC_IO_LATENCY_REG +
+      ((MCHBAR_CH1_CR_SC_IO_LATENCY_REG - MCHBAR_CH0_CR_SC_IO_LATENCY_REG) * Channel);
+    ScIoLatency.Data = 0;
+    ScIoLatency.Bits.RT_IOCOMP = RtIoComp;
+    MrcWriteCR (MrcData, Offset, ScIoLatency.Data);
+  }
+
+  for (Rank = 0; Rank < MAX_RANK_IN_CHANNEL; Rank++) {
+    if (!((MRC_BIT0 << Rank) & RankMask)) {
+      //
+      // Skip if both channels empty
+      //
+      continue;
+    }
+
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\nRank %d\n", Rank);
+
+    ChBitMask = 0;
+    for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+      ChBitMask |= SelectReutRanks (MrcData, Channel, MRC_BIT0 << Rank, 0);
+      if (!(MrcRankInChannelExist (MrcData, Rank, Channel))) {
+        continue;
+      }
+
+      ChannelOut = &ControllerOut->Channel[Channel];
+
+      ChannelOut->IoLatency[Rank] = 0;
+      //
+      // Set initial Roundtrip Latency values -4 QCLK assumed for worst board layout
+      //
+      // Default ROUNDT_LAT = HW_ROUNDT_LAT_DEFAULT_VALUE + nMode value * 2 + (2 * tCL) + 4QCLK + PI_CLK
+      // LPDDR3 formula:      HW_ROUNDT_LAT_DEFAULT_VALUE + (2 * tCL) + 4QCLK + PI_CLK + tDQSCK_max
+      // NMode = 3 during training mode
+      //
+      Temp = (Outputs->Ratio >= 2) ? Outputs->Ratio : 0;
+
+#ifdef ULT_FLAG
+      if (Outputs->DdrType == MRC_DDR_TYPE_LPDDR3) {
+        DclkPs = Outputs->Qclkps * 2;
+        CRValue = RtLatency + (2 * ChannelOut->Timing[Profile].tCL) + MAX (Temp, 4) + 1 + (tDQSCK_MAX + DclkPs - 1) / DclkPs;
+      } else
+#endif // ULT_FLAG
+      {
+        CRValue = RtLatency + (2 * 2) + (2 * ChannelOut->Timing[Profile].tCL) + MAX (Temp, 4) + 1;
+      }
+      CRValue = MIN (MCHBAR_CH0_CR_SC_ROUNDT_LAT_Lat_R0D0_MAX, CRValue);
+      Offset = MCHBAR_CH0_CR_SC_ROUNDT_LAT_REG +
+        ((MCHBAR_CH1_CR_SC_ROUNDT_LAT_REG - MCHBAR_CH0_CR_SC_ROUNDT_LAT_REG) * Channel) + Rank;
+      MrcWriteCR8 (MrcData, Offset, (U8) CRValue);
+      ChannelOut->RTLatency[Rank] = (U8) CRValue;
+    }
+    //
+    // ******************************************
+    // STEP 1 and 2: Find middle of high region
+    // ******************************************
+    //
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Step 1 and 2 Find Middle of high region\n");
+    RLStart = 256 + 24;
+    RLStop  = 384 + 24;
+
+    for (RLDelay = RLStart; RLDelay < RLStop; RLDelay += RLStep0) {
+      //
+      // Program RL Delays:
+      //
+      for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+        if (!(MrcRankInChannelExist (MrcData, Rank, Channel))) {
+          continue;
+        }
+
+        for (Byte = 0; Byte < Outputs->SdramCount; Byte++) {
+          UpdateRxT (MrcData, Channel, Rank, Byte, 0, RLDelay);
+        }
+      }
+      //
+      // Run Test, Reset FIFOs will be done before running test
+      //
+      RunIOTest (MrcData, ChBitMask, BasicVA, DumArr, 1, 0);
+
+      //
+      // Update results for all Channels/Bytes
+      //
+      for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+        if (!(MrcRankInChannelExist (MrcData, Rank, Channel))) {
+          continue;
+        }
+
+        for (Byte = 0; Byte < Outputs->SdramCount; Byte++) {
+          Offset = DDRDATA0CH0_CR_DATATRAINFEEDBACK_REG +
+            ((DDRDATA0CH1_CR_DATATRAINFEEDBACK_REG - DDRDATA0CH0_CR_DATATRAINFEEDBACK_REG) * Channel) +
+            ((DDRDATA1CH0_CR_DATATRAINFEEDBACK_REG - DDRDATA0CH0_CR_DATATRAINFEEDBACK_REG) * Byte);
+          Pass = (MrcReadCR (MrcData, Offset) >= (U8) (MRC_BIT0 << (NumSamples - 1)));
+          if (RLDelay == RLStart) {
+            if (Pass) {
+              InitialPassingStart[Channel][Byte] = InitialPassingEnd[Channel][Byte]  = RLStart;
+              CurrentPassingStart[Channel][Byte] = CurrentPassingEnd[Channel][Byte]  = RLStart;
+              LargestPassingStart[Channel][Byte] = LargestPassingEnd[Channel][Byte]  = RLStart;
+            } else {
+              InitialPassingStart[Channel][Byte] = InitialPassingEnd[Channel][Byte]  = -RLStep0;
+              CurrentPassingStart[Channel][Byte] = CurrentPassingEnd[Channel][Byte]  = -RLStep0;
+              LargestPassingStart[Channel][Byte] = LargestPassingEnd[Channel][Byte]  = -RLStep0;
+            }
+          } else {
+            if (Pass) {
+              if (InitialPassingEnd[Channel][Byte] == (RLDelay - RLStep0)) {
+                InitialPassingEnd[Channel][Byte] = RLDelay;
+              }
+
+              if (CurrentPassingEnd[Channel][Byte] == (RLDelay - RLStep0)) {
+                CurrentPassingEnd[Channel][Byte] = RLDelay;
+              } else {
+                CurrentPassingStart[Channel][Byte] = CurrentPassingEnd[Channel][Byte] = RLDelay;
+              }
+              //
+              // Special case for last step: Append Initial Passing Region
+              // RLDelay should be considered a continuous range that wraps around 0
+              //
+              if ((RLDelay >= (RLStop - RLStep0)) &&
+                  (InitialPassingStart[Channel][Byte] == RLStart) &&
+                  (InitialPassingEnd[Channel][Byte] != RLDelay)
+                  ) {
+
+                iWidth = (CurrentPassingEnd[Channel][Byte] - CurrentPassingStart[Channel][Byte]);
+                InitialPassingStart[Channel][Byte] -= (RLStep0 + iWidth);
+
+                LargestPassingStart[Channel][Byte]  = InitialPassingStart[Channel][Byte];
+                LargestPassingEnd[Channel][Byte]    = InitialPassingEnd[Channel][Byte];
+                continue;
+              }
+              //
+              // Update Largest variables
+              //
+              cWidth  = CurrentPassingEnd[Channel][Byte] - CurrentPassingStart[Channel][Byte];
+              lWidth  = LargestPassingEnd[Channel][Byte] - LargestPassingStart[Channel][Byte];
+              if (cWidth > lWidth) {
+                LargestPassingStart[Channel][Byte]  = CurrentPassingStart[Channel][Byte];
+                LargestPassingEnd[Channel][Byte]    = CurrentPassingEnd[Channel][Byte];
+              }
+            }
+          }
+        }
+      }
+    }
+    //
+    // Update RcvEn timing to be in the center of the high region.
+    //
+    for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+      if (!(MrcRankInChannelExist (MrcData, Rank, Channel))) {
+        continue;
+      }
+
+      ChannelOut = &ControllerOut->Channel[Channel];
+
+      MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "C%d.R%d:  Left\tRight\tWidth\tCenter\n", Channel, Rank);
+      for (Byte = 0; Byte < Outputs->SdramCount; Byte++) {
+        Center  = (LargestPassingEnd[Channel][Byte] + LargestPassingStart[Channel][Byte]) / 2;
+        Width   = LargestPassingEnd[Channel][Byte] - LargestPassingStart[Channel][Byte];
+
+        MRC_DEBUG_MSG (
+          Debug,
+          MSG_LEVEL_NOTE,
+          "  B%d:   %d     %d     %d     %d\n",
+          Byte,
+          LargestPassingStart[Channel][Byte],
+          LargestPassingEnd[Channel][Byte],
+          Width,
+          Center
+          );
+
+        //
+        // Check if center of High was found
+        //
+        if (Center > RLStop) {
+          MRC_DEBUG_MSG (
+            Debug,
+            MSG_LEVEL_ERROR,
+            "\nERROR! Center of High Higher than expected for Channel: %u Byte: %u\n",
+            Channel,
+            Byte
+            );
+          return mrcReadLevelingError;
+        }
+        //
+        // Check if width is valid
+        //
+        if ((Width <= 32) || (Width >= 96)) {
+          MRC_DEBUG_MSG (
+            Debug,
+            MSG_LEVEL_ERROR,
+            "\nERROR! Width region (%d) outside expected limits for Channel: %u Byte: %u\n",
+            Width,
+            Channel,
+            Byte
+            );
+          return mrcReadLevelingError;
+        }
+
+        ChannelOut->RcvEn[Rank][Byte] = (U16) Center;
+        UpdateRxT (MrcData, Channel, Rank, Byte, 0xFF, 0);
+      }
+    }
+    //
+    // ******************************************************************************
+    // STEP 3: Walk Backwards
+    // ******************************************************************************
+    //
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\nStep 3: Quarter Preamble - Walk Backwards\n");
+
+    if (Outputs->ValidRankMask & (MRC_BIT0 << Rank)) {
+      MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Channel     0                 1\nByte        ");
+      MRC_DEBUG_MSG (
+        Debug,
+        MSG_LEVEL_NOTE, (
+        Outputs->SdramCount == MAX_SDRAM_IN_DIMM
+        ) ? "0 1 2 3 4 5 6 7 8      0 1 2 3 4 5 6 7 8" : "0 1 2 3 4 5 6 7      0 1 2 3 4 5 6 7"
+        );
+    }
+
+    for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+      ChResult[Channel] = 0x1FF;
+    }
+
+    //
+    // 0x1FF or 0xFF
+    //
+    ChMask = (MRC_BIT0 << Outputs->SdramCount) - 1;
+    while ((ChResult[0] != 0) || (ChResult[1] != 0)) {
+      //
+      // Run Test
+      //
+      RunIOTest (MrcData, ChBitMask, BasicVA, DumArr, 1, 0);
+
+      //
+      // Update results for all Channel/Bytes
+      //
+      MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\nIOLAT =");
+
+      for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+        ChResult[Channel] = 0;
+
+        if (!(MrcRankInChannelExist (MrcData, Rank, Channel))) {
+          if (Channel == 0) {
+            MRC_DEBUG_MSG (
+              Debug,
+              MSG_LEVEL_NOTE,
+              (Outputs->SdramCount == MAX_SDRAM_IN_DIMM) ? "                       " : "                     "
+              );
+          }
+
+          continue;
+        }
+
+        ChannelOut = &ControllerOut->Channel[Channel];
+
+        MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "  %u  ", ChannelOut->IoLatency[Rank]);
+
+        for (Byte = 0; Byte < Outputs->SdramCount; Byte++) {
+          Offset = DDRDATA0CH0_CR_DATATRAINFEEDBACK_REG +
+            ((DDRDATA0CH1_CR_DATATRAINFEEDBACK_REG - DDRDATA0CH0_CR_DATATRAINFEEDBACK_REG) * Channel) +
+            ((DDRDATA1CH0_CR_DATATRAINFEEDBACK_REG - DDRDATA0CH0_CR_DATATRAINFEEDBACK_REG) * Byte);
+          DataTrainFeedback.Data  = MrcReadCR (MrcData, Offset);
+          Pass                    = (DataTrainFeedback.Bits.DataTrainFeedback >= (U16) (MRC_BIT0 << (NumSamples - 1)));
+          if (Pass) {
+            ChResult[Channel] |= (MRC_BIT0 << Byte);
+          }
+
+          MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, Pass ? "H " : "L ");
+        }
+        //
+        // Adjust Timing
+        //
+        if ((ChResult[Channel] == ChMask) && (ChannelOut->IoLatency[Rank] < 14)) {
+          //
+          // Adjust Timing globally for all Bytes - Number in Qclks
+          //
+          ChannelOut->IoLatency[Rank] = ((ChannelOut->IoLatency[Rank] + 2) & MCHBAR_CH0_CR_SC_IO_LATENCY_IOLAT_R0D0_MSK);
+
+          //
+          // @todo: Add an error check if we reach IOLAT > 10
+          // Update Value
+          //
+          ByteN       = RANK_TO_DIMM_NUMBER (Rank);
+          ByteNTimes2 = ByteN * 2;
+          CRValue     = (ChannelOut->IoLatency[ByteNTimes2]);
+          CRValue += (ChannelOut->IoLatency[ByteNTimes2 + 1] << MCHBAR_CH0_CR_SC_IO_LATENCY_IOLAT_R0D0_WID);
+          Offset = MCHBAR_CH0_CR_SC_IO_LATENCY_REG +
+            ((MCHBAR_CH1_CR_SC_IO_LATENCY_REG - MCHBAR_CH0_CR_SC_IO_LATENCY_REG) * Channel) + (ByteN);
+          MrcWriteCR8 (MrcData, Offset, (U8) CRValue);
+        } else {
+          for (Byte = 0; Byte < Outputs->SdramCount; Byte++) {
+            if (ChResult[Channel] & (MRC_BIT0 << Byte)) {
+              if (ChannelOut->RcvEn[Rank][Byte] > 127) {
+                ChannelOut->RcvEn[Rank][Byte] -= 128;
+              } else {
+                //
+                // Error Handler
+                //
+                MRC_DEBUG_MSG (
+                  Debug,
+                  MSG_LEVEL_ERROR,
+                  "\nERROR! Channel: %u Rank: %uByte: %u - RcvEn %u/IoLat %u while walking backwards\n",
+                  Channel,
+                  Rank,
+                  Byte,
+                  ChannelOut->RcvEn[Rank][Byte],
+                  ChannelOut->IoLatency[Rank]
+                  );
+                return mrcReadLevelingError;
+              }
+
+              UpdateRxT (MrcData, Channel, Rank, Byte, 0xFF, 0);
+            }
+          }
+        }
+      }
+    }
+
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\n");
+
+    for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+      if (!(MrcRankInChannelExist (MrcData, Rank, Channel))) {
+        continue;
+      }
+      ChannelOut = &ControllerOut->Channel[Channel];
+      MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "C%u:  Preamble\n", Channel);
+
+      for (Byte = 0; Byte < Outputs->SdramCount; Byte++) {
+        MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, " B%u: %u\n", Byte, ChannelOut->RcvEn[Rank][Byte]);
+      }
+    }
+    //
+    // ******************************************
+    // STEP 4: Add 1 qclk
+    // ******************************************
+    //
+    for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+      if (!(MrcRankInChannelExist (MrcData, Rank, Channel))) {
+        continue;
+      }
+
+      ChannelOut = &Outputs->Controller[0].Channel[Channel];
+
+      for (Byte = 0; Byte < Outputs->SdramCount; Byte++) {
+        ChannelOut->RcvEn[Rank][Byte] += 64;
+        UpdateRxT (MrcData, Channel, Rank, Byte, 0xFF, 0);
+      }
+    }
+    //
+    // ******************************************
+    // STEP 5: Walk forward
+    // ******************************************
+    //
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Step 5 Walk forward\n");
+    //
+    // Find Rising Edge
+    //
+    ChResult[0] = 0;
+    ChResult[1] = 0;
+
+    for (Inc = 0; Inc < 64; Inc += FineStep) {
+      //
+      // Run Test
+      //
+      RunIOTest (MrcData, ChBitMask, BasicVA, DumArr, 1, 0);
+
+      //
+      // Update results for all Channel/bytes
+      //
+      Done = 1;
+      for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+        if (!(MrcRankInChannelExist (MrcData, Rank, Channel))) {
+          continue;
+        }
+        ChannelOut = &ControllerOut->Channel[Channel];
+
+        for (Byte = 0; Byte < Outputs->SdramCount; Byte++) {
+          //
+          // Skip Bytes that are already done
+          //
+          if (ChResult[Channel] & (MRC_BIT0 << Byte)) {
+            continue;
+          }
+          //
+          // Check if this byte is done
+          //
+          Offset = DDRDATA0CH0_CR_DATATRAINFEEDBACK_REG +
+            ((DDRDATA0CH1_CR_DATATRAINFEEDBACK_REG - DDRDATA0CH0_CR_DATATRAINFEEDBACK_REG) * Channel) +
+            ((DDRDATA1CH0_CR_DATATRAINFEEDBACK_REG - DDRDATA0CH0_CR_DATATRAINFEEDBACK_REG) * Byte);
+          Pass = (MrcReadCR (MrcData, Offset) >= (U8) (MRC_BIT0 << (NumSamples - 1)));
+          if (Pass) {
+            ChResult[Channel] |= (MRC_BIT0 << Byte);
+          } else {
+            ChannelOut->RcvEn[Rank][Byte] += FineStep;
+            UpdateRxT (MrcData, Channel, Rank, Byte, 0xFF, 0);
+            IncPreAmble[Channel][Byte] = Inc;
+          }
+        }
+
+        if (ChResult[Channel] != ChMask) {
+          Done = 0;
+        }
+      }
+      //
+      // Skip additional testing if all Channel/bytes done
+      //
+      if (Done) {
+        break;
+      }
+    }
+    //
+    // Check if Edge was found for all Bytes in the channels
+    //
+    if (!Done) {
+      MRC_DEBUG_MSG (
+        Debug,
+        MSG_LEVEL_ERROR,
+        "Error! Pre-amble edge not found for all Bytes with following final RcvEn results\n"
+        );
+
+      for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+        if (!(MrcRankInChannelExist (MrcData, Rank, Channel))) {
+          continue;
+        }
+
+        ChannelOut = &ControllerOut->Channel[Channel];
+
+        MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Channel %u Rank %u:  Preamble\n", Channel, Rank);
+        for (Byte = 0; Byte < Outputs->SdramCount; Byte++) {
+          MRC_DEBUG_MSG (
+            Debug,
+            MSG_LEVEL_NOTE,
+            " Byte %u: %u %s\n",
+            Byte,
+            ChannelOut->RcvEn[Rank][Byte],
+            ((ChResult[Channel] ^ ChMask) & (1 << Byte)) ? "" : "*** ERROR! Check This Byte ***"
+            );
+        }
+      }
+
+      return mrcReadLevelingError;
+    }
+    //
+    // ******************************************
+    // STEP 6: Sub 1 qclk and Clean Up Rank
+    // ******************************************
+    //
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Step 6: Mid Preamble\n");
+    for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+      if (!(MrcRankInChannelExist (MrcData, Rank, Channel))) {
+        continue;
+      }
+      ChannelOut = &ControllerOut->Channel[Channel];
+
+      MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "C%u:  Preamble Increment\n", Channel);
+
+      for (Byte = 0; Byte < Outputs->SdramCount; Byte++) {
+        //
+        // For Traditional, pull in RcvEn by 64
+        // For ULT, Take the DQS drift into account to the specified guardband: tDQSCK_DRIFT.
+        //
+        ChannelOut->RcvEn[Rank][Byte] -= TDqsCkDrift;
+
+        UpdateRxT (MrcData, Channel, Rank, Byte, 0xFF, 0);
+
+        MRC_DEBUG_MSG (
+          Debug,
+          MSG_LEVEL_NOTE,
+          " B%u: %u      %u\n",
+          Byte,
+          ChannelOut->RcvEn[Rank][Byte],
+          IncPreAmble[Channel][Byte]
+          );
+      }
+    }
+  } // END OF RANK LOOP
+  //
+  // Clean up after Test
+  //
+  for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+    if (!(MrcChannelExist (Outputs, Channel))) {
+      continue;
+    }
+    ChannelOut = &ControllerOut->Channel[Channel];
+
+    Offset = DDRDATACH0_CR_DDRCRDATACONTROL0_REG +
+      ((DDRDATACH1_CR_DDRCRDATACONTROL0_REG - DDRDATACH0_CR_DDRCRDATACONTROL0_REG) * Channel);
+    DdrCrDataControl0.Data = ChannelOut->DqControl0.Data;
+#ifdef ULT_FLAG
+    if (Outputs->DdrType == MRC_DDR_TYPE_LPDDR3) {
+      //
+      // W/A for b4618574 - @todo: remove for HSW ULT C0
+      // Can't have ForceOdtOn together with Leaker, disable LPDDR mode during this training step
+      // This write will disable ForceOdtOn while still keeping LPDDR_Mode disabled.
+      // Second write will restore LPDDR_Mode.
+      //
+      DdrCrDataControl0.Bits.LPDDR_Mode = 0;
+      MrcWriteCrMulticast (MrcData, Offset, DdrCrDataControl0.Data);
+    }
+#endif // ULT_FLAG
+    MrcWriteCrMulticast (MrcData, Offset, ChannelOut->DqControl0.Data);
+
+    for (Byte = 0; Byte < Outputs->SdramCount; Byte++) {
+    Offset = DDRDATA0CH0_CR_DDRCRDATACONTROL2_REG +
+      ((DDRDATA0CH1_CR_DDRCRDATACONTROL2_REG - DDRDATA0CH0_CR_DDRCRDATACONTROL2_REG) * Channel) +
+      ((DDRDATA1CH0_CR_DDRCRDATACONTROL2_REG - DDRDATA0CH0_CR_DDRCRDATACONTROL2_REG) * Byte);
+      MrcWriteCR (MrcData, Offset, ChannelOut->DqControl2[Byte].Data);
+    }
+  }
+
+  Status = IoReset (MrcData);
+
+  //
+  // Step 7: Try to get IO Lat the same across all ranks per channel
+  //
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Step 7: Sync IO Lat Across Ranks\n");
+  for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+    if (MrcChannelExist (Outputs, Channel)) {
+      Status = MrcChangeRcvEnTiming (
+        MrcData,
+        Channel,
+        RRE_ALL_RANKS_MASK,
+        0,  // ByteMask
+        0,  // Offset
+        RRE_PI_TO_RESERVE
+        );
+    }
+  }
+
+  //
+  // Print IO Latency/RcvEn
+  //
+#ifdef MRC_DEBUG_PRINT
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, " Adjusted Receive Enable and IO Lat Values\n");
+  for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+    if (MrcChannelExist (Outputs, Channel)) {
+      ChannelOut = &ControllerOut->Channel[Channel];
+      Offset = MCHBAR_CH0_CR_SC_IO_LATENCY_REG +
+        ((MCHBAR_CH1_CR_SC_IO_LATENCY_REG - MCHBAR_CH0_CR_SC_IO_LATENCY_REG) * Channel);
+      ScIoLatency.Data  = MrcReadCR (MrcData, Offset);
+      for (Rank = 0; Rank < MAX_RANK_IN_CHANNEL; Rank++) {
+        if ((MrcRankInChannelExist (MrcData, Rank, Channel))) {
+          MRC_DEBUG_MSG (Debug,
+            MSG_LEVEL_NOTE,
+            "  C%d.R%d: IOLAT = %u  RT_IOCOMP = %d\n",
+            Channel,
+            Rank,
+            ChannelOut->IoLatency[Rank],
+            ScIoLatency.Bits.RT_IOCOMP
+            );
+          for (Byte = 0; Byte < Outputs->SdramCount; Byte++) {
+            MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "   B%d:   %u\n", Byte, ChannelOut->RcvEn[Rank][Byte]);
+          }
+        }
+      }
+    }
+  }
+#endif
+
+  return Status;
+}
+
+/**
+@brief
+  Apply an signed offset to all selected bytes/ ranks in a channel to RcvEn timing
+  Robustly handles any carries to/from the IO Latency vs. RcvEn FlyBy
+  PiReserve will reserve a certain number of +/- PI ticks for margin purposes
+  Routine also minimizes the difference in RcvEn settings across ranks
+
+  @param[in,out] MrcData       - MRC Global Data
+  @param[in]     Channel       - The channel to adjust
+  @param[in]     RankMask      - Mask of Ranks to adjust
+  @param[in]     ByteMask      - Mask of Bytes to adjust by the RcvEnOffset
+  @param[in]     RcvEnOffset   - Amount to offset RcvEn
+  @param[in]     PiReserve     - The number of PiTicks to reserve on each edge of RcvEn
+
+  @retval MrcStatus - mrcSuccess if successfull
+                      mrcWrongInputParameter if channel doesnt exist or a RankMask of 0 is provided
+                      mrcReadLevelingError if we over/underflow RT_IOCOMP field.
+**/
+MrcStatus
+MrcChangeRcvEnTiming (
+  IN OUT MrcParameters *const MrcData,
+  IN     const U8             Channel,
+  IN     const U8             RankMask,
+  IN     const U16            ByteMask,
+  IN     const S16            RcvEnOffset,
+  IN     const S16            PiReserve
+  )
+{
+  MrcStatus                          Status;
+  MrcOutput                          *Outputs;
+  MrcDebug                           *Debug;
+  MrcChannelOut                      *ChannelOut;
+  MCHBAR_CH0_CR_SC_IO_LATENCY_STRUCT ScIoLatency;
+  U8                                 Rank;
+  U8                                 Byte;
+  S8                                 CycleOffset;
+  S8                                 IoGlobalOffset;
+  S8                                 IoLatRank[MAX_RANK_IN_CHANNEL];
+  S8                                 IoLatTarget;
+  S8                                 MaxRankLat;
+  S8                                 MinRankLat;
+  S16                                NewRcvEn;
+  S16                                MaxRcvEn;
+  S16                                MinRcvEn;
+  S16                                MaxRcvEnRank[MAX_RANK_IN_CHANNEL];
+  S16                                MinRcvEnRank[MAX_RANK_IN_CHANNEL];
+  U32                                CrOffset;
+
+  //
+  // Init variables with min and max values
+  //
+  Status           = mrcSuccess;
+  Outputs          = &MrcData->SysOut.Outputs;
+  Debug            = &MrcData->SysIn.Inputs.Debug;
+  ChannelOut       = &MrcData->SysOut.Outputs.Controller[0].Channel[Channel];
+  MaxRankLat       = 0;
+  MinRankLat       = 15;
+  MaxRcvEn         = -4096;
+  MinRcvEn         = 4096;
+  IoGlobalOffset   = 0;
+  MrcOemMemorySetWord ((U16*) MaxRcvEnRank, (U16)-4096, MAX_RANK_IN_CHANNEL);
+  MrcOemMemorySetWord ((U16*) MinRcvEnRank, 4096, MAX_RANK_IN_CHANNEL);
+  MrcOemMemorySet ((U8*) IoLatRank, 0, MAX_RANK_IN_CHANNEL);
+
+  //
+  // Quick error check on parameters
+  //
+  if ((!(MrcChannelExist (Outputs, Channel))) || (RankMask == 0)) {
+    return mrcWrongInputParameter;
+  }
+
+  //
+  // Walk through all the ranks/bytes to find Max/Min RcvEn values
+  //
+  for (Rank = 0; Rank < MAX_RANK_IN_CHANNEL; Rank++) {
+    if ((((MRC_BIT0 << Rank) & RankMask) != 0) && ((MrcRankInChannelExist (MrcData, Rank, Channel)))) {
+      //
+      // Find Max/Min for RcvEn across bytes.  RcvEn is the total (RcvEnPi - 64 * IOLat)
+      //
+      for (Byte = 0; Byte < Outputs->SdramCount; Byte++) {
+        NewRcvEn = (S16) ChannelOut->RcvEn[Rank][Byte] - (64 * (S16) ChannelOut->IoLatency[Rank]);
+        if (ByteMask & (MRC_BIT0 << Byte)) {
+          //
+          // Apply an offset for this byte
+          //
+          NewRcvEn += RcvEnOffset;
+        }
+
+        if (MaxRcvEnRank[Rank] < NewRcvEn) {
+          MaxRcvEnRank[Rank] = NewRcvEn;
+        }
+
+        if (MinRcvEnRank[Rank] > NewRcvEn) {
+          MinRcvEnRank[Rank] = NewRcvEn;
+        }
+      }
+      //
+      // Find Max/Min for RcvEn across ranks
+      //
+      if (MaxRcvEn < MaxRcvEnRank[Rank]) {
+        MaxRcvEn = MaxRcvEnRank[Rank];
+      }
+
+      if (MinRcvEn > MinRcvEnRank[Rank]) {
+        MinRcvEn = MinRcvEnRank[Rank];
+      }
+    }
+  }
+
+  //
+  // Determine how far we are from the ideal center point for RcvEn timing.
+  // (PiIdeal - AveRcvEn)/64 is the ideal number of cycles we should have for IOLatency
+  // Command training will reduce this by 64, so plan for that now in the ideal value
+  //
+  IoLatTarget = (S8) ((RRE_PI_IDEAL - ((MaxRcvEn + MinRcvEn) / 2) + 32) / 64); // Rnd to closest int
+
+  //
+  // Walk through all the ranks and calculate new values of IOLat
+  //
+  for (Rank = 0; Rank < MAX_RANK_IN_CHANNEL; Rank++) {
+    if ((((MRC_BIT0 << Rank) & RankMask) != 0) && ((MrcRankInChannelExist (MrcData, Rank, Channel)))) {
+      IoLatRank[Rank] = IoLatTarget;
+
+      //
+      // Check for RcvEn underflow
+      //
+      NewRcvEn = 64 * IoLatRank[Rank] + MinRcvEnRank[Rank];
+      if (NewRcvEn < PiReserve) {
+        IoLatRank[Rank] += (U8) ((PiReserve - NewRcvEn + 63) / 64); // Ceiling
+      }
+
+      //
+      // Check for RcvEn overflow
+      //
+      NewRcvEn = 64 * IoLatRank[Rank] + MaxRcvEnRank[Rank];
+      if (NewRcvEn > (511 - PiReserve)) {
+        IoLatRank[Rank] -= (U8) ((NewRcvEn - (511 - PiReserve) + 63) / 64); // Ceiling
+      }
+      //
+      // Check for IO Latency over/underflow
+      //
+      if ((IoLatRank[Rank] - IoGlobalOffset) > 14) {
+        IoGlobalOffset = IoLatRank[Rank] - 14;
+      }
+      if ((IoLatRank[Rank] - IoGlobalOffset) < 1) {
+        IoGlobalOffset = IoLatRank[Rank] - 1;
+      }
+    //
+    // Update Byte level results
+    //
+      CycleOffset = IoLatRank[Rank] - (S8) ChannelOut->IoLatency[Rank];
+      for (Byte = 0; Byte < Outputs->SdramCount; Byte++) {
+        ChannelOut->RcvEn[Rank][Byte] += 64 * (U16) CycleOffset;
+        if (ByteMask & (MRC_BIT0 << Byte)) {
+          ChannelOut->RcvEn[Rank][Byte] += (U16) RcvEnOffset;
+        }
+        UpdateRxT (MrcData, Channel, Rank, Byte, 0xFF, 0);
+      }
+    }
+  }
+  //
+  // Calculate new IOComp Latency to include over/underflow
+  //
+  CrOffset = MCHBAR_CH0_CR_SC_IO_LATENCY_REG +
+    ((MCHBAR_CH1_CR_SC_IO_LATENCY_REG - MCHBAR_CH0_CR_SC_IO_LATENCY_REG) * Channel);
+  ScIoLatency.Data = MrcReadCR (MrcData, CrOffset);
+
+  //
+  // Check to see if were under/overflowing this field
+  //
+  if ((IoGlobalOffset < 0) && (ScIoLatency.Bits.RT_IOCOMP < (U8) -IoGlobalOffset)) {
+    Status = mrcReadLevelingError;
+  } else if (
+               (IoGlobalOffset > 0) &&
+               ((U8)IoGlobalOffset > (MCSCHEDS_CR_SC_IO_LATENCY_RT_IOCOMP_MAX - ScIoLatency.Bits.RT_IOCOMP))
+             ) {
+    Status = mrcReadLevelingError;
+  }
+
+  if(Status == mrcReadLevelingError) {
+    MRC_DEBUG_MSG (
+      Debug,
+      MSG_LEVEL_ERROR,
+      "MrcChangeRcvEnTiming(): RT_IOCOMP %s\n IoGlobalOffset: %d\n RT_IOCOMP(6'b): %d\n",
+      (IoGlobalOffset < 0) ? "underflowed" : "overflowed",
+      IoGlobalOffset,
+      ScIoLatency.Bits.RT_IOCOMP
+      );
+  }
+  ScIoLatency.Bits.RT_IOCOMP += IoGlobalOffset;
+  ChannelOut->RTIoComp        = ScIoLatency.Bits.RT_IOCOMP;
+
+  //
+  // Walk through all ranks to program new IO Latency values
+  //
+  ScIoLatency.Data &= ~(
+                        MCHBAR_CH0_CR_SC_IO_LATENCY_IOLAT_R0D0_MSK +
+                        MCHBAR_CH0_CR_SC_IO_LATENCY_IOLAT_R1D0_MSK +
+                        MCHBAR_CH0_CR_SC_IO_LATENCY_IOLAT_R0D1_MSK +
+                        MCHBAR_CH0_CR_SC_IO_LATENCY_IOLAT_R1D1_MSK
+                        );
+  for (Rank = 0; Rank < MAX_RANK_IN_CHANNEL; Rank++) {
+    if ((((MRC_BIT0 << Rank) & RankMask) != 0) && ((MrcRankInChannelExist (MrcData, Rank, Channel)))) {
+      ChannelOut->IoLatency[Rank] = IoLatRank[Rank] - IoGlobalOffset;
+    }
+    ScIoLatency.Data |= (
+        (MCHBAR_CH0_CR_SC_IO_LATENCY_IOLAT_R0D0_MSK & (ChannelOut->IoLatency[Rank])) <<
+        (Rank * MCHBAR_CH0_CR_SC_IO_LATENCY_IOLAT_R0D0_WID)
+      );
+  }
+
+  //
+  // Program new IO Latency
+  //
+  MrcWriteCR (MrcData, CrOffset, ScIoLatency.Data);
+
+  return Status;
+}
+
+/**
+@brief
+  Once the DQS high phase has been found (for each DRAM) the next stage is to find out the round trip latency,
+  by locating the preamble cycle. This is achieved by trying smaller and smaller roundtrip
+  values until the strobe sampling is done on the preamble cycle.
+  The following algorithm is used to find the preamble cycle:
+
+  @param[in] MrcData         - all the global data
+
+  @retval Nothing.
+**/
+MrcStatus
+MrcRoundTripLatency (
+  IN     MrcParameters *const MrcData
+  )
+{
+  MrcStatus         Status;
+  MrcOutput         *Outputs;
+  MrcControllerOut  *ControllerOut;
+  MrcChannelOut     *ChannelOut;
+  MrcDebug          *Debug;
+  U8                Channel;
+  U8                Rank;
+  U8                OptParam;
+  U8                RankMask;
+  U8                TestList[1];
+  S8                ClkShifts[1];
+  U8                Start;
+  U8                Stop;
+  U8                LoopCount;
+  U8                Update;
+  U8                MinIoLat;
+  U8                MaxRankRtl;
+  S8                DeltaLimitRtl;
+  U8                DeltaRtl;
+  MCHBAR_CH0_CR_TC_BANK_RANK_A_STRUCT TcBankRankA;
+
+  Status        = mrcSuccess;
+  TestList[0]   = RdT;        // Test based on read eye width
+  ClkShifts[0]  = 25;         // Delay by 25 pi ticks to guardband for delay drift/jitter
+  LoopCount     = 10;
+  Update        = 1;          // Apply the optimal settings
+  MaxRankRtl    = 0;
+  Outputs       = &MrcData->SysOut.Outputs;
+  Debug         = &MrcData->SysIn.Inputs.Debug;
+  ControllerOut = &Outputs->Controller[0];
+  OptParam      = rtl;        // Which parameter to optimize for
+
+  //
+  // Train timing separately for each rank
+  //
+  for (Rank = 0; Rank < MAX_RANK_IN_CHANNEL; Rank++) {
+    RankMask = (MRC_BIT0 << Rank);
+    if (!(RankMask & Outputs->ValidRankMask)) {
+      continue;
+    }
+    //
+    // Pick starting and stopping points
+    //
+    Stop      = 0;
+    Start     = 0;
+    MinIoLat  = 15;
+    for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+      if (!(MrcRankInChannelExist (MrcData, Rank, Channel))) {
+        continue;
+      }
+      ChannelOut = &ControllerOut->Channel[Channel];
+
+      if (Stop < ChannelOut->RTLatency[Rank]) {
+        Stop = ChannelOut->RTLatency[Rank];
+      }
+
+      if (MinIoLat > ChannelOut->IoLatency[Rank]) {
+        MinIoLat = ChannelOut->IoLatency[Rank];
+      }
+
+      Start = Stop - MinIoLat;
+    }
+
+    if ((S8) Start < 0) {
+      Start = 0;
+    }
+    //
+    // Find optimal answer
+    //
+    Status = TrainDDROptParamCliff (
+              MrcData,
+              OptParam,
+              TestList,
+              sizeof (TestList),
+              Start,
+              Stop,
+              LoopCount,
+              Update,
+              Outputs->MarginResult,
+              ClkShifts,
+              sizeof (ClkShifts),
+              Rank,
+              RankMask,
+              0
+              );
+    if (Status == mrcFail) {
+      return mrcRoundTripLatencyError;
+    }
+  }
+
+  //
+  // Limit the RTL delta across the ranks present.
+  //
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\nLimit the delta between Rank's RTL value.\n");
+  for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+    if (MrcChannelExist (Outputs, Channel)) {
+
+      MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Channel %d\n", Channel);
+      ChannelOut = &ControllerOut->Channel[Channel];
+      TcBankRankA.Data = ChannelOut->MchbarBANKRANKA;
+      DeltaLimitRtl = MAX ((S8) TcBankRankA.Bits.tRDRD_dr, (S8) TcBankRankA.Bits.tRDRD_dd);
+      //
+      // TA Times are in dclks.  Must convert to qclks and subtract the burst length.
+      // Ensure we do not underflow the variable.
+      //
+      DeltaLimitRtl = ((2 * DeltaLimitRtl) - 8);
+      DeltaLimitRtl = MAX (DeltaLimitRtl, 0);
+      MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "RTL Delta Limit: %d\n", DeltaLimitRtl);
+
+      for (Rank = 0; Rank < MAX_RANK_IN_CHANNEL; Rank++) {
+        if (MrcRankInChannelExist (MrcData, Rank, Channel)) {
+          MaxRankRtl = MAX (MaxRankRtl, ChannelOut->RTLatency[Rank]);
+          MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, " Rank %u RTL: %u\n", Rank, ChannelOut->RTLatency[Rank]);
+        }
+      }
+      MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "MaxRankRtl: %u\n", MaxRankRtl);
+
+      for (Rank = 0; Rank < MAX_RANK_IN_CHANNEL; Rank++) {
+        if (MrcRankInChannelExist (MrcData, Rank, Channel)) {
+          DeltaRtl = MaxRankRtl - ChannelOut->RTLatency[Rank];
+          MRC_DEBUG_MSG (
+            Debug,
+            MSG_LEVEL_NOTE,
+            "Rank %d: DeltaRtl: %u\tDeltaLimitRtl: %u%s",
+            Rank,
+            DeltaRtl,
+            DeltaLimitRtl,
+            (DeltaRtl > DeltaLimitRtl) ? "\tNew RTL: " : ""
+            );
+          if (DeltaRtl > DeltaLimitRtl) {
+            UpdateTAParamOffset (MrcData, Channel, 0, OptParam, MaxRankRtl - DeltaLimitRtl, 1, 0, 1 << Rank);
+          }
+          MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\n");
+        }
+      }
+    }
+  }
+
+  return Status;
+}
+
+/**
+  Perform Receive Enable Timing Centering.
+  Center Receive Enable using moderate pattern with 1D eye.
+
+  @param[in] MrcData - Include all MRC global data.
+
+  @retval MrcStatus - If successful, returns mrcSuccess.
+**/
+MrcStatus
+MrcReceiveEnTimingCentering (
+  IN MrcParameters *const MrcData
+  )
+{
+  MrcOutput *Outputs;
+
+  Outputs = &MrcData->SysOut.Outputs;
+
+  return DQTimeCentering1D (MrcData, Outputs->ValidChBitMask, RcvEnaX, 0, RCV_EN_CENTER_LC);
+}
\ No newline at end of file
diff --git a/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/ReadTraining/MrcReadReceiveEnable.h b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/ReadTraining/MrcReadReceiveEnable.h
new file mode 100644
index 0000000..4984d2a
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/ReadTraining/MrcReadReceiveEnable.h
@@ -0,0 +1,120 @@
+/** @file
+  Read receive enable training definitions.
+
+@copyright
+  Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved.
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement.
+**/
+
+#ifndef _MrcReadReceiveEnable_h_
+#define _MrcReadReceiveEnable_h_
+
+#include "MrcTypes.h"
+#include "MrcCommon.h"
+#include "MrcCrosser.h"
+#include "MrcGlobal.h"
+
+#define HW_ROUNDT_LAT_DEFAULT_VALUE_A0              (20)  ///< HSW HW specific default value
+#define MRC_ROUND_TRIP_IO_COMPENSATION_2_CHANNEL_A0 (25)  // Roundtrip - IO compensation for 2 channel
+
+#define HW_ROUNDT_LAT_DEFAULT_VALUE_B0              (16)  ///< HSW HW specific default value
+#define MRC_ROUND_TRIP_IO_COMPENSATION_2_CHANNEL_B0 (21)  // Roundtrip - IO compensation for 2 channel
+
+#define HW_ROUNDT_LAT_DEFAULT_VALUE_ULT_A0              (18)  // Roundtrip Latency
+#define MRC_ROUND_TRIP_IO_COMPENSATION_2_CHANNEL_ULT_A0 (23)  // Roundtrip - IO compensation for 2 channel
+
+///
+/// ReadReceiveEnable (RRE) parameters
+/// Command training will reduce this by 64, so plan for that now in the ideal value
+///
+#define RRE_PI_IDEAL       (256 + 64)
+#define RRE_ALL_RANKS_MASK (0x0F)
+#define RRE_PI_TO_RESERVE  (64)
+
+/**
+@brief
+  Perform receive enable training.
+  Optimize RcvEn timing with MPR pattern
+
+  @param[in, out] MrcData - Include all MRC global data.
+
+  @retval MrcStatus -  if succeeded, return mrcSuccess
+**/
+extern
+MrcStatus
+MrcReadLevelingTraining (
+  IN OUT MrcParameters *const MrcData
+  );
+
+/**
+@brief
+  Apply an signed offset to all selected bytes/ ranks in a channel to RcvEn timing
+  Robustly handles any carries to/from the IO Latency vs. RcvEn FlyBy
+  PiReserve will reserve a certain number of +/- PI ticks for margin purposes
+  Routine also minimizes the difference in RcvEn settings across ranks
+
+  @param[in,out] MrcData       - MRC Global Data
+  @param[in]     Channel       - The channel to adjust
+  @param[in]     RankMask      - Mask of Ranks to adjust
+  @param[in]     ByteMask      - Mask of Bytes to adjust by the RcvEnOffset
+  @param[in]     RcvEnOffset   - Amount to offset RcvEn
+  @param[in]     PiReserve     - The number of PiTicks to reserve on each edge of RcvEn
+
+  @retval MrcStatus - mrcSuccess if successfull
+                      mrcWrongInputParameter if channel doesnt exist or a RankMask of 0 is provided
+                      mrcReadLevelingError if we over/underflow RT_IOCOMP field.
+**/
+MrcStatus
+MrcChangeRcvEnTiming (
+  IN OUT MrcParameters *const MrcData,
+  IN     const U8             Channel,
+  IN     const U8             RankMask,
+  IN     const U16            ByteMask,
+  IN     const S16            RcvEnOffset,
+  IN     const S16            PiReserve
+  );
+
+/**
+@brief
+  Once the DQS high phase has been found (for each DRAM) the next stage is to find out the round trip latency,
+  by locating the preamble cycle. This is achieved by trying smaller and smaller roundtrip
+  values until the strobe sampling is done on the preamble cycle.
+  The following algorithm is used to find the preamble cycle:
+
+  @param[in] MrcData         - all the global data
+
+  @retval Nothing.
+**/
+extern
+MrcStatus
+MrcRoundTripLatency (
+  IN     MrcParameters *const MrcData
+  );
+
+/**
+  Perform Receive Enable Timing Centering.
+  Center Receive Enable using moderate pattern with 1D eye
+
+  @param[in] MrcData         - Include all MRC global data.
+
+  @retval MrcStatus       - if it succeded returns mrcSuccess
+**/
+MrcStatus
+MrcReceiveEnTimingCentering (
+  IN MrcParameters *const MrcData
+  );
+
+#endif // _MrcReadReceiveEnable_h_
diff --git a/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Services/MrcCommandTraining.c b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Services/MrcCommandTraining.c
new file mode 100644
index 0000000..3bc5ef6
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Services/MrcCommandTraining.c
@@ -0,0 +1,4743 @@
+/** @file
+  Implementation of the command training algorithm.
+  The algorithm finds the N mode for the current board and also the correct
+  CLK CMD CTL pi setting.
+
+@copyright
+  Copyright (c) 1999 - 2013 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement.
+
+**/
+
+//
+// Include files
+//
+#include "MrcCommandTraining.h"
+
+#define MRC_CADB_PB_LENGTH 16
+
+/**
+@brief
+  This function performs early command training.
+  Center CTL-CLK timing to allow subsequent steps to work
+
+  @param[in] MrcData - Include all MRC global data.
+
+  @retval MrcStatus -  mrcSuccess if it succeeded
+**/
+MrcStatus
+MrcEarlyCommandTraining (
+  IN MrcParameters *const MrcData
+  )
+{
+  const MrcInput                              *Inputs;
+  const MrcDebug                              *Debug;
+  MrcOutput                                   *Outputs;
+  MrcControllerOut                            *ControllerOut;
+  MrcChannelOut                               *ChannelOut;
+  S32                                         *IPStart;
+  S32                                         *IPEnd;
+  S32                                         *CPStart;
+  S32                                         *CPEnd;
+  S32                                         *LPStart;
+  S32                                         *LPEnd;
+  MrcStatus                                   Status;
+  BOOL                                        Pass;
+  BOOL                                        Done;
+  DDRCLK_CR_DDRCRCLKPICODE_STRUCT             DdrCrClkPiCode;
+  MCHBAR_CH0_CR_REUT_CH_MISC_ODT_CTRL_STRUCT  ReutChMiscOdtCtrl;
+  MCDFXS_CR_REUT_GLOBAL_CTL_MCMAIN_STRUCT     ReutGlobalCtl;
+  DDRDATA0CH0_CR_DDRCRDATACONTROL0_STRUCT     DdrCrDataControl0;
+  DDRDATA0CH0_CR_DDRCRDATACONTROL2_STRUCT     DdrCrDataControl2;
+  U32                                         CRValue;
+  S32                                         cWidth;
+  S32                                         lWidth;
+  S32                                         InitialPassingStart[MAX_CHANNEL][MAX_RANK_IN_CHANNEL];
+  S32                                         InitialPassingEnd[MAX_CHANNEL][MAX_RANK_IN_CHANNEL];
+  S32                                         CurrentPassingStart[MAX_CHANNEL][MAX_RANK_IN_CHANNEL];
+  S32                                         CurrentPassingEnd[MAX_CHANNEL][MAX_RANK_IN_CHANNEL];
+  S32                                         LargestPassingStart[MAX_CHANNEL][MAX_RANK_IN_CHANNEL];
+  S32                                         LargestPassingEnd[MAX_CHANNEL][MAX_RANK_IN_CHANNEL];
+  U32                                         DqsDoneMask;
+  U32                                         bytePass[MAX_CHANNEL];
+  U32                                         byteFail[MAX_CHANNEL];
+  U32                                         Offset;
+  U8                                          Channel;
+  U8                                          Rank;
+  U8                                          byte;
+  U8                                          chBitMask;
+  U8                                          RankMask;
+  U8                                          ValidRankMask;
+  U8                                          clkDelay;
+  U8                                          clkDelayArray;
+  U8                                          PiCode;
+  S8                                          DqsDelay;
+  S8                                          LastDqsRan[ECT_CLK_LOOPS][MAX_CHANNEL][MAX_RANK_IN_CHANNEL];
+
+  MrcOemMemorySet ((U8 *) LastDqsRan, ECT_DQS_STOP, sizeof (LastDqsRan));
+
+  Inputs        = &MrcData->SysIn.Inputs;
+  Debug         = &Inputs->Debug;
+  Outputs       = &MrcData->SysOut.Outputs;
+  ControllerOut = &Outputs->Controller[0];
+  //
+  // RankBitMask for both channels
+  //
+  ValidRankMask = Outputs->ValidRankMask;
+  //
+  // Channel bit mask
+  //
+  chBitMask = Outputs->ValidChBitMask;
+
+#ifdef ULT_FLAG
+  //
+  // Check if LPDDR3 memory is used
+  //
+  if (Outputs->DdrType == MRC_DDR_TYPE_LPDDR3) {
+    return EarlyCommandTrainingLpddr (MrcData);
+  }
+#endif // ULT_FLAG
+
+  for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+    if (MrcChannelExist (Outputs, Channel)) {
+      ChannelOut = &ControllerOut->Channel[Channel];
+
+      //
+      // Set DQS Delay to 32
+      //
+      for (byte = 0; byte < Outputs->SdramCount; byte++) {
+        for (Rank = 0; Rank < MAX_RANK_IN_CHANNEL; Rank++) {
+          if ((MrcRankInChannelExist (MrcData, Rank, Channel)) && (Inputs->SetRxDqs32 == TRUE)) {
+            //
+            // Update RxDqsP & RxDqsN - leave other parameter the same; can we update in the next loop or do it per channel
+            //
+            UpdateRxT (MrcData, Channel, Rank, byte, 5, 32);
+          }
+        }
+      }
+      //
+      // Clear any old state in DataTrain Offset
+      //
+      MrcOemMemorySetDword (&ChannelOut->DataOffsetTrain[0], 0, Outputs->SdramCount);
+    }
+  }
+  //
+  // Setup REUT Engine
+  // LC = 10, SOE = 0 (NSOE), EnCADB = 0, EnCKE = 0
+  //
+  SetupIOTestMPR (MrcData, chBitMask, 10, NSOE, 0, 0);
+
+#ifdef MRC_DEBUG_PRINT
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\nChannel\t");
+  for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+    if (MrcChannelExist (Outputs, Channel)) {
+      MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%u\t\t\t\t", Channel);
+    }
+  }
+
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\nRank\t");
+
+  for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+    if (MrcChannelExist (Outputs, Channel)) {
+      for (Rank = 0; Rank < MAX_RANK_IN_CHANNEL; Rank++) {
+        if (MrcRankInChannelExist (MrcData, Rank, Channel)) {
+          MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%u", Rank);
+        }
+
+        MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\t");
+      }
+    }
+  }
+
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\nClock");
+#endif // MRC_DEBUG_PRINT
+  for (clkDelay = ECT_CLK_START; clkDelay < ECT_CLK_STOP; clkDelay += ECT_CLK_STEP) {
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\n% 5u\t", clkDelay);
+    clkDelayArray = clkDelay / ECT_CLK_STEP;
+    //
+    // Program Clock Delays
+    //
+    DdrCrClkPiCode.Data = 0;
+    DdrCrClkPiCode.Bits.PiSettingRank0 =
+    DdrCrClkPiCode.Bits.PiSettingRank1 =
+    DdrCrClkPiCode.Bits.PiSettingRank2 =
+    DdrCrClkPiCode.Bits.PiSettingRank3 = clkDelay;
+    MrcWriteCrMulticast (MrcData, DDRCLK_CR_DDRCRCLKPICODE_REG, DdrCrClkPiCode.Data);
+
+    //
+    // Reset FIFOs and Reset all DIMM/all channels after changing PI codes
+    //
+    Status = MrcResetSequence (MrcData);
+
+    for (Rank = 0; Rank < MAX_RANK_IN_CHANNEL; Rank++) {
+      RankMask = MRC_BIT0 << Rank;
+      //
+      // Skip ranks that are not populated
+      //
+      if ((ValidRankMask & RankMask) == 0) {
+        continue;
+      }
+      //
+      // Program MR3 and Mask RAS/WE to prevent scheduler from issuing non-Read commands
+      //
+      for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+        SelectReutRanks (MrcData, Channel, RankMask, 0);
+        bytePass[Channel] = 0;
+        byteFail[Channel] = 0;
+        if (MrcRankInChannelExist (MrcData, Rank, Channel)) {
+          Status = MrcWriteMRS (MrcData, Channel, RankMask, mrMR3, 4);
+
+          Offset = MCHBAR_CH0_CR_REUT_CH_MISC_ODT_CTRL_REG +
+            ((MCHBAR_CH1_CR_REUT_CH_MISC_ODT_CTRL_REG - MCHBAR_CH0_CR_REUT_CH_MISC_ODT_CTRL_REG) * Channel);
+          ReutChMiscOdtCtrl.Data                  = MrcReadCR (MrcData, Offset);
+          ReutChMiscOdtCtrl.Bits.MPR_Train_DDR_On = 1;
+          MrcWriteCR (MrcData, Offset, ReutChMiscOdtCtrl.Data);
+        }
+      }
+      //
+      // Run ReadDQS Test
+      //
+      DqsDoneMask = (MRC_BIT0 << Outputs->SdramCount) - 1;
+      //
+      // MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\nRank %u DqsDelay for clkDelay = %u", Rank, clkDelay);
+      //
+      for (DqsDelay = ECT_DQS_START; DqsDelay < ECT_DQS_STOP; DqsDelay += ECT_DQS_STEP) {
+        //
+        // MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\n %d\t", DqsDelay);
+        //
+        // Write DqsDelay
+        //
+        Status = ChangeMargin (MrcData, RdT, DqsDelay, 0, 1, 0, 0, 0, 0, 0, 0, MrcRegFileStart);
+
+        for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+          if (!(MrcRankInChannelExist (MrcData, Rank, Channel))) {
+            /*MRC_DEBUG_MSG (
+              Debug,
+              MSG_LEVEL_NOTE,
+              (Channel != 0) ? "" : ((Outputs->SdramCount == MAX_SDRAM_IN_DIMM) ?
+              "                  " : "                ")
+              );*/
+          } else {
+            ChannelOut = &ControllerOut->Channel[Channel];
+
+            for (byte = 0; byte < Outputs->SdramCount; byte++) {
+              //
+              // Force on SenseAmp
+              //
+              Offset = DDRDATA0CH0_CR_DDRCRDATACONTROL2_REG +
+                ((DDRDATA0CH1_CR_DDRCRDATACONTROL2_REG - DDRDATA0CH0_CR_DDRCRDATACONTROL2_REG) * Channel) +
+                ((DDRDATA1CH0_CR_DDRCRDATACONTROL2_REG - DDRDATA0CH0_CR_DDRCRDATACONTROL2_REG) * byte);
+              DdrCrDataControl2.Data             = ChannelOut->DqControl2[byte].Data;
+              DdrCrDataControl2.Bits.ForceBiasOn = DDRDATA0CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_MAX;
+              DdrCrDataControl2.Bits.ForceRxOn   = DDRDATA0CH0_CR_DDRCRDATACONTROL2_ForceRxOn_MAX;
+              MrcWriteCrMulticast (MrcData, Offset, DdrCrDataControl2.Data);
+            }
+            //
+            // Enable RX Training mode.  Turn on Odt
+            //
+            Offset = DDRDATACH0_CR_DDRCRDATACONTROL0_REG +
+              ((DDRDATACH1_CR_DDRCRDATACONTROL0_REG - DDRDATACH0_CR_DDRCRDATACONTROL0_REG) * Channel);
+            DdrCrDataControl0.Data                = ChannelOut->DqControl0.Data;
+            DdrCrDataControl0.Bits.ForceOdtOn     = DDRDATACH0_CR_DDRCRDATACONTROL0_ForceOdtOn_MAX;
+            DdrCrDataControl0.Bits.RxTrainingMode = DDRDATACH0_CR_DDRCRDATACONTROL0_RxTrainingMode_MAX;
+            MrcWriteCR (MrcData, Offset, DdrCrDataControl0.Data);
+          }
+        }
+        //
+        // Clear Results for Prior Test and wait to obtain results
+        //
+        Status = IoReset (MrcData);
+
+        //
+        // Start REUT and run for 1uS
+        //
+        ReutGlobalCtl.Data                     = 0;
+        ReutGlobalCtl.Bits.Global_Clear_Errors = 1;
+        ReutGlobalCtl.Bits.Global_Start_Test   = 1;
+        MrcWriteCR (MrcData, MCDFXS_CR_REUT_GLOBAL_CTL_MCMAIN_REG, ReutGlobalCtl.Data);
+
+        //
+        // Wait for test to start clearing errors.
+        //
+        MrcWait (MrcData, START_TEST_DELAY);
+
+        //
+        // Clear Results for Prior Test and wait to obtain results
+        //
+        Status = IoReset (MrcData);
+        MrcWait (MrcData, IO_RESET_DELAY);
+
+        //
+        // Stop REUT
+        //
+        ReutGlobalCtl.Data                  = 0;
+        ReutGlobalCtl.Bits.Global_Stop_Test = 1;
+        MrcWriteCR (MrcData, MCDFXS_CR_REUT_GLOBAL_CTL_MCMAIN_REG, ReutGlobalCtl.Data);
+
+        //
+        // Get Results for all ch/bytes
+        //
+        for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+          if (MrcRankInChannelExist (MrcData, Rank, Channel)) {
+            for (byte = 0; byte < Outputs->SdramCount; byte++) {
+              Offset = DDRDATA0CH0_CR_DATATRAINFEEDBACK_REG +
+                ((DDRDATA0CH1_CR_DATATRAINFEEDBACK_REG - DDRDATA0CH0_CR_DATATRAINFEEDBACK_REG) * Channel) +
+                ((DDRDATA1CH0_CR_DATATRAINFEEDBACK_REG - DDRDATA0CH0_CR_DATATRAINFEEDBACK_REG) * byte);
+              Pass = (MrcReadCR (MrcData, Offset) == 1);
+              //
+              // MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, Pass ? ". " : "# ");
+              //
+              CRValue = (MRC_BIT0 << byte);
+              if (Pass) {
+                bytePass[Channel] |= CRValue;
+              } else {
+                byteFail[Channel] |= CRValue;
+              }
+            }
+            //
+            // Save DqsDelay where all bytes passed
+            //
+            if ((bytePass[Channel] == DqsDoneMask) && (LastDqsRan[clkDelayArray][Channel][Rank] > DqsDelay)) {
+              LastDqsRan[clkDelayArray][Channel][Rank] = DqsDelay;
+            }
+          }
+        }
+
+        for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+          if (MrcRankInChannelExist (MrcData, Rank, Channel)) {
+            ChannelOut = &ControllerOut->Channel[Channel];
+            for (byte = 0; byte < Outputs->SdramCount; byte++) {
+              //
+              // Restore orginal value
+              //
+              Offset = DDRDATA0CH0_CR_DDRCRDATACONTROL2_REG +
+                ((DDRDATA0CH1_CR_DDRCRDATACONTROL2_REG - DDRDATA0CH0_CR_DDRCRDATACONTROL2_REG) * Channel) +
+                ((DDRDATA1CH0_CR_DDRCRDATACONTROL2_REG - DDRDATA0CH0_CR_DDRCRDATACONTROL2_REG) * byte);
+              MrcWriteCR (MrcData, Offset, ChannelOut->DqControl2[byte].Data);
+            }
+
+            Status = IoReset (MrcData);
+
+            //
+            // Clear RX Mode
+            //
+            Offset = DDRDATACH0_CR_DDRCRDATACONTROL0_REG +
+              ((DDRDATACH1_CR_DDRCRDATACONTROL0_REG - DDRDATACH0_CR_DDRCRDATACONTROL0_REG) * Channel);
+            MrcWriteCrMulticast (MrcData, Offset, ChannelOut->DqControl0.Data);
+          }
+        }
+        //
+        // Are We done yet?
+        //
+        Done = TRUE;
+        for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+          if (MrcRankInChannelExist (MrcData, Rank, Channel)) {
+            if ((bytePass[Channel] != DqsDoneMask) || (byteFail[Channel] != DqsDoneMask)) {
+              Done = FALSE;
+              break;
+            }
+          }
+        }
+        //
+        // If we re done, we passed or failed for all bytes
+        //
+        if (Done == TRUE) {
+          break;
+        }
+      }
+      //
+      // MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\n");
+      //
+      // Update results for all channel at this rank
+      //
+      for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+        if (MrcRankInChannelExist (MrcData, Rank, Channel)) {
+          Pass = ((bytePass[Channel] == DqsDoneMask) && (byteFail[Channel] == DqsDoneMask));
+
+          //
+          // Check if we have a valid pass
+          //
+          if (Pass &&
+              (clkDelay != ECT_CLK_START) &&
+              ((LastDqsRan[clkDelayArray][Channel][Rank] - LastDqsRan[clkDelayArray - 1][Channel][Rank]) > 16)
+              ) {
+            Pass = FALSE;
+          }
+
+          IPStart = &InitialPassingStart[Channel][Rank];
+          IPEnd   = &InitialPassingEnd[Channel][Rank];
+          CPStart = &CurrentPassingStart[Channel][Rank];
+          CPEnd   = &CurrentPassingEnd[Channel][Rank];
+          LPStart = &LargestPassingStart[Channel][Rank];
+          LPEnd   = &LargestPassingEnd[Channel][Rank];
+          if (clkDelay == ECT_CLK_START) {
+            if (Pass) {
+              *IPStart = clkDelay;
+              *IPEnd   = clkDelay;
+              *CPStart = clkDelay;
+              *CPEnd   = clkDelay;
+              *LPStart = clkDelay;
+              *LPEnd   = clkDelay;
+            } else {
+              *IPStart = -ECT_CLK_STEP;
+              *IPEnd   = -ECT_CLK_STEP;
+              *CPStart = -ECT_CLK_STEP;
+              *CPEnd   = -ECT_CLK_STEP;
+              *LPStart = -ECT_CLK_STEP;
+              *LPEnd   = -ECT_CLK_STEP;
+            }
+          } else {
+            if (Pass) {
+              //
+              // Update Initial variables
+              //
+              if (*IPEnd == clkDelay - ECT_CLK_STEP) {
+                *IPEnd = clkDelay;          // In passing region
+              }
+              //
+              // Update Current variables
+              //
+              if (*CPEnd == clkDelay - ECT_CLK_STEP) {
+                *CPEnd = clkDelay;          // In passing region
+              } else {
+                *CPStart = clkDelay;        // New region
+                *CPEnd = clkDelay;
+              }
+              //
+              // Special case for last step: Append Initial Passing Region
+              // clkDelay should be considered a continuous range that wraps around 0
+              //
+              if (clkDelay == 128 - ECT_CLK_STEP && *IPStart == ECT_CLK_START && *IPEnd != clkDelay) {
+                *CPEnd += ECT_CLK_STEP + (*IPEnd -*IPStart);
+              }
+              //
+              // Update Largest variables
+              //
+              cWidth = *CPEnd - *CPStart;
+              lWidth = *LPEnd - *LPStart;
+              if (cWidth > lWidth) {
+                *LPStart  = *CPStart;
+                *LPEnd    = *CPEnd;
+              }
+            }
+          }
+        }
+      }
+      //
+      // Clean up registers.  No need to clear MR3 since DIMM will be reset
+      //
+      for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+        if (MrcRankInChannelExist (MrcData, Rank, Channel)) {
+          Offset = MCHBAR_CH0_CR_REUT_CH_MISC_ODT_CTRL_REG +
+            ((MCHBAR_CH1_CR_REUT_CH_MISC_ODT_CTRL_REG - MCHBAR_CH0_CR_REUT_CH_MISC_ODT_CTRL_REG) * Channel);
+          ReutChMiscOdtCtrl.Data                  = MrcReadCR (MrcData, Offset);
+          ReutChMiscOdtCtrl.Bits.MPR_Train_DDR_On = 0;
+          MrcWriteCR (MrcData, Offset, ReutChMiscOdtCtrl.Data);
+        }
+      }
+    }
+
+#ifdef MRC_DEBUG_PRINT
+    for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+      if (MrcChannelExist (Outputs, Channel)) {
+        for (Rank = 0; Rank < MAX_RANK_IN_CHANNEL; Rank++) {
+          if (MrcRankInChannelExist (MrcData, Rank, Channel)) {
+            CPEnd = &CurrentPassingEnd[Channel][Rank];
+            MRC_DEBUG_MSG (
+              Debug,
+              MSG_LEVEL_NOTE,
+              (LastDqsRan[clkDelayArray][Channel][Rank] < ECT_DQS_STOP) ? ". " : "# "
+              );
+            MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "(% 3d)", LastDqsRan[clkDelayArray][Channel][Rank]);
+          }
+
+          MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\t");
+        }
+      }
+    }
+#endif // MRC_DEBUG_PRINT
+  }
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\n");
+
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\tLeft\tRight\tWidth\tClkDelay\n");
+  //
+  // Find largest passing region and Update PICodes
+  //
+  for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+    if (MrcChannelExist (Outputs, Channel)) {
+      ChannelOut          = &ControllerOut->Channel[Channel];
+      DdrCrClkPiCode.Data = 0;
+      for (Rank = 0; Rank < MAX_RANK_IN_CHANNEL; Rank++) {
+        if (MrcRankInChannelExist (MrcData, Rank, Channel)) {
+          LPStart = &LargestPassingStart[Channel][Rank];
+          LPEnd   = &LargestPassingEnd[Channel][Rank];
+          lWidth  = *LPEnd - *LPStart;
+
+          //
+          // Error Handler if eye not found for all bytes
+          //
+          if (lWidth == 0) {
+            MRC_DEBUG_MSG (Debug, MSG_LEVEL_ERROR, "\nERROR!! NO EYE found for Channel:%u Rank:%u\n", Channel, Rank);
+            MRC_DEBUG_MSG (
+              Debug,
+              MSG_LEVEL_NOTE,
+              "Channel %u Rank %u:\t%d\t%d\t%d\t%d\n",
+              Channel,
+              Rank,
+              *LPStart,
+              *LPEnd,
+              lWidth,
+              0
+              );
+            return mrcReadMPRErr;
+          }
+
+          if (lWidth > ECT_MIN_WIDTH) {
+            PiCode = (U8) (*LPStart + lWidth / 2);
+          } else {
+            MRC_DEBUG_MSG (
+              Debug,
+              MSG_LEVEL_WARNING,
+              "\nWARNING!! lWidth <= %u for Channel %u Rank %u \n",
+              ECT_MIN_WIDTH,
+              Channel,
+              Rank
+              );
+            PiCode = 64;
+          }
+          //
+          // Update Host Structure with new PiCode
+          //
+          switch (Rank) {
+            case 0:
+              DdrCrClkPiCode.Bits.PiSettingRank0 = PiCode;
+              break;
+
+            case 1:
+              DdrCrClkPiCode.Bits.PiSettingRank1 = PiCode;
+              break;
+
+            case 2:
+              DdrCrClkPiCode.Bits.PiSettingRank2 = PiCode;
+              break;
+
+            case 3:
+              DdrCrClkPiCode.Bits.PiSettingRank3 = PiCode;
+              break;
+
+            default:
+              break;
+          }
+
+          MRC_DEBUG_MSG (
+            Debug,
+            MSG_LEVEL_NOTE,
+            "C%u.R%u:\t%d\t%d\t%d\t%d\n",
+            Channel,
+            Rank,
+            *LPStart,
+            *LPEnd,
+            lWidth,
+            PiCode
+            );
+        }
+      }
+
+      Offset = DDRCLKCH0_CR_DDRCRCLKPICODE_REG +
+        ((DDRCLKCH1_CR_DDRCRCLKPICODE_REG - DDRCLKCH0_CR_DDRCRCLKPICODE_REG) * Channel);
+      MrcWriteCR (MrcData, Offset, DdrCrClkPiCode.Data);
+      MrcOemMemorySetDword (&ChannelOut->DataOffsetTrain[0], 0, Outputs->SdramCount);
+    }
+  }
+
+  Status = ChangeMargin (MrcData, RdT, 0, 0, 1, 0, 0, 0, 0, 0, 0, MrcRegFileCurrent);
+  Status = MrcResetSequence (MrcData);
+
+  return Status;
+}
+
+/**
+@brief
+  This function performs Late command training.
+  Center CMD/CTL-CLK timing using complex patterns.
+
+  @param[in] MrcData - Include all MRC global data.
+
+  @retval MrcStatus - If it's a success return mrcSuccess
+**/
+MrcStatus
+MrcLateCommandTraining (
+  MrcParameters *const MrcData
+  )
+{
+  const MrcDebug                      *Debug;
+  MrcOutput                           *Outputs;
+  MrcControllerOut                    *ControllerOut;
+  MrcChannelOut                       *ChannelOut;
+  MrcStatus                           Status;
+  MrcProfile                          Profile;
+  U32                                 MinCode;
+  U32                                 Offset;
+  U8                                  Cmd2N;
+  U8                                  Channel;
+  U8                                  ChBitMask;
+  U8                                  RankMask;
+  U8                                  Rank;
+  U8                                  Ranks;
+  U8                                  CmdPiCode[MAX_CHANNEL];
+  U8                                  CtlPiCode[MAX_CHANNEL];
+#ifdef ULT_FLAG
+  BOOL                                Lpddr;
+  U8                                  MidPointCke[MAX_CHANNEL];
+  U8                                  MidPointCmdN[MAX_CHANNEL];
+  U8                                  MidPointCmdS[MAX_CHANNEL];
+  MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_STRUCT  ReutChSeqBaseAddrOrderCarryInvertCtl;
+  MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_STRUCT ReutChSeqBaseAddrIncCtl;
+  MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_STRUCT              ReutChPatCadbCtrl;
+  MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_0_STRUCT    ReutChSeqBaseAddrWrap;
+#endif //ULT_FLAG
+
+  Debug         = &MrcData->SysIn.Inputs.Debug;
+  Outputs       = &MrcData->SysOut.Outputs;
+  ControllerOut = &Outputs->Controller[0];
+  Profile       = MrcData->SysIn.Inputs.MemoryProfile;
+
+#ifdef ULT_FLAG
+  //
+  // Check if LPDDR3 memory is used
+  //
+  Lpddr = (Outputs->DdrType == MRC_DDR_TYPE_LPDDR3);
+#endif // ULT_FLAG
+
+  ChBitMask     = Outputs->ValidChBitMask;
+  RankMask      = Outputs->ValidRankMask;
+
+#ifdef ULT_FLAG
+  if (Lpddr) {
+    SetupIOTestCADB (MrcData, ChBitMask, 10, NTHSOE, 1, 0); // LC = 10
+  } else
+#endif //ULT_FLAG
+  {
+    Cmd2N = FALSE;
+    for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+      if (MrcChannelExist (Outputs, Channel)) {
+        Cmd2N = (ControllerOut->Channel[Channel].Timing[Profile].NMode == 2) ? TRUE : FALSE; // All channels have same NMode
+        break;
+      }
+    }
+    CmdPiCode[0] = CmdPiCode[1] = (Cmd2N == TRUE) ? 85 : 64;
+    CtlPiCode[0] = CtlPiCode[1] = 64;
+
+    MRC_DEBUG_MSG (
+      Debug,
+      MSG_LEVEL_NOTE,
+      " Cmd2N %d, CmdPiCode %d, ChBitMask = 0x%x\n",
+      Cmd2N,
+      CmdPiCode[0],
+      ChBitMask
+      );
+
+    //
+    // Setup REUT
+    // LC= 10, SOE  = 1 (NTHSOE), EnCADB = 1, EnCKE = 0
+    //
+    SetupIOTestCADB (MrcData, ChBitMask, 10, NTHSOE, 1, 0);
+    for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+      if (!(MrcChannelExist (Outputs, Channel))) {
+        continue;
+      }
+
+      ChannelOut = &ControllerOut->Channel[Channel];
+
+      //
+      // Shift everything to the right.  To get DQ timing right, program Clk to 0
+      //
+      ShiftPIforCmdTraining (
+        MrcData,
+        Channel,
+        MrcIterationClock,
+        ChannelOut->ValidRankBitMask,
+        1,
+        0 - ChannelOut->ClkPiCode[0],
+        1
+        );
+      ShiftPIforCmdTraining (MrcData, Channel, MrcIterationCmdS, ChannelOut->ValidRankBitMask, 1, CmdPiCode[Channel], 1);
+      ShiftPIforCmdTraining (MrcData, Channel, MrcIterationCmdN, ChannelOut->ValidRankBitMask, 1, CmdPiCode[Channel], 1);
+      ShiftPIforCmdTraining (MrcData, Channel, MrcIterationCtl,  ChannelOut->ValidRankBitMask, 1, CtlPiCode[Channel], 1);
+    }
+  }
+
+#ifdef ULT_FLAG
+
+  if (Lpddr) {
+    //
+    // Center Command Timing
+    //
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\n*** ECT results\n");
+    for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+      ChannelOut = &ControllerOut->Channel[Channel];
+      MidPointCke[Channel]  = (U8) ChannelOut->CkeCmdPiCode[0];
+      MidPointCmdS[Channel] = (U8) ChannelOut->CmdsCmdPiCode[0];
+      MRC_DEBUG_MSG (
+        Debug,
+        MSG_LEVEL_NOTE,
+        "C%u: CAA: CKE fub: %d, CmdS fub: %d\n",
+        Channel,
+        MidPointCke[Channel],
+        MidPointCmdS[Channel]
+        );
+    }
+
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\n*** Center CAA[5,6,7,8,9] Timing using CKE fub\n");
+    CmdTimingCentering (MrcData, MrcIterationCke, RankMask, 1, MidPointCke);
+
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\n*** Center CAA[0,1,2,3,4] Timing using CmdS fub\n");
+    CmdTimingCentering (MrcData, MrcIterationCmdS, RankMask, 1, MidPointCmdS);
+
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\n*** ECT results\n");
+    for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+      ChannelOut = &ControllerOut->Channel[Channel];
+      MidPointCmdS[Channel] = (U8)ChannelOut->CmdsCmdPiCode[1];
+      MidPointCmdN[Channel] = (U8)ChannelOut->CmdnCmdPiCode[1];
+      MRC_DEBUG_MSG (
+        Debug,
+        MSG_LEVEL_NOTE,
+        "C%u: CAB: CmdS fub: %d, CmdN fub: %d\n",
+        Channel,
+        MidPointCmdS[Channel],
+        MidPointCmdN[Channel]
+        );
+    }
+
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\n*** Center CAB[5,8] Timing using CmdS fub\n");
+    CmdTimingCentering (MrcData, MrcIterationCmdS, RankMask, 2, MidPointCmdS);
+
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\n*** Center CAB[0,1,2,3,4,6,7,9] Timing using CmdN fub\n");
+    CmdTimingCentering (MrcData, MrcIterationCmdN, RankMask, 2, MidPointCmdN);
+
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\n*** Center Control Timing\n");
+
+    //
+    // @todo Reinitialize registers to CAS-centric training (no CADB) ?
+    //
+
+    //
+    // Modify the differences
+    //
+    for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+      if (!MrcChannelExist (Outputs, Channel)) {
+        continue;
+      }
+      Offset = MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_REG +
+        ((MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_REG - MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_REG) * Channel);
+      ReutChSeqBaseAddrOrderCarryInvertCtl.Data = 0;
+      MrcWriteCR (MrcData, Offset, ReutChSeqBaseAddrOrderCarryInvertCtl.Data);
+      MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "C%d ReutChSeqBaseAddrOrderCarryInvertCtl: 0x%08X\n", Channel, ReutChSeqBaseAddrOrderCarryInvertCtl.Data);
+
+      Offset = MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_REG +
+        ((MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_REG - MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_REG) * Channel);
+      ReutChSeqBaseAddrIncCtl.Data = 0;
+      ReutChSeqBaseAddrIncCtl.Bits.Rank_Base_Address_Update_Scale   = 1;
+      ReutChSeqBaseAddrIncCtl.Bits.Bank_Base_Address_Update_Scale   = 1;
+      ReutChSeqBaseAddrIncCtl.Bits.Row_Base_Address_Update_Scale    = 1;
+      ReutChSeqBaseAddrIncCtl.Bits.Column_Base_Address_Update_Scale = 1;
+      ReutChSeqBaseAddrIncCtl.Bits.Column_Base_Address_Increment    = 1;
+      MrcWriteCR64 (MrcData, Offset, ReutChSeqBaseAddrIncCtl.Data);
+      MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "C%d ReutChSeqBaseAddrIncCtl: 0x%08X%08X\n", Channel, ReutChSeqBaseAddrIncCtl.Data32[1],
+        ReutChSeqBaseAddrIncCtl.Data32[0]);
+
+      Offset = MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_REG +
+        ((MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_REG - MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_REG) * Channel);
+      ReutChPatCadbCtrl.Data = 0;
+      ReutChPatCadbCtrl.Bits.Lane_Deselect_Enable = 0xB; // All, except CMD
+      ReutChPatCadbCtrl.Bits.CMD_Deselect_Start = 2;     // Start on RD
+      MrcWriteCR (MrcData, Offset, ReutChPatCadbCtrl.Data);
+      MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "C%d ReutChPatCadbCtrl: 0x%08X\n", Channel, ReutChPatCadbCtrl.Data);
+
+      Offset = MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_MASK_MCMAIN_0_REG +
+        ((MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_MASK_MCMAIN_1_REG - MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_MASK_MCMAIN_0_REG) * Channel);
+      MrcWriteCR8 (MrcData, Offset, 0xFF);
+      MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "C%d ReutChSeqDummyreadMask Offset:0x%X Value:0x%X\n", Channel, Offset, 0xFF);
+
+      //
+      // Start from logical Rank 0
+      //
+      Offset = MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_0_REG +
+        ((MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_1_REG - MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_0_REG) * Channel);
+      MrcWriteCR64 (MrcData, Offset, 0);
+
+      //
+      // Wrap at column 127
+      // Logical Rank Wrap address will be updated in SelectReutRanks() later on.
+      //
+      Offset = MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_0_REG +
+        ((MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_1_REG - MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_0_REG) * Channel);
+      ReutChSeqBaseAddrWrap.Data = 0;
+      ReutChSeqBaseAddrWrap.Bits.Column_Address = 0x7F;
+      MrcWriteCR64 (MrcData, Offset, ReutChSeqBaseAddrWrap.Data);
+      MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "C%d ReutChSeqBaseAddrWrap: 0x%08X%08X\n", Channel, ReutChSeqBaseAddrWrap.Data32[1],
+        ReutChSeqBaseAddrWrap.Data32[0]);
+    } // for Channel
+
+    for (Rank = 0; Rank < MAX_RANK_IN_CHANNEL; Rank++) {
+      Ranks = (1 << Rank);
+      if ((Ranks & RankMask) == 0) {
+        continue;
+      }
+      MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\n*** ECT results\n");
+      for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+        if (MrcRankInChannelExist (MrcData, Rank, Channel)) {
+          CtlPiCode[Channel] = ControllerOut->Channel[Channel].CtlPiCode[Rank];
+          MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "C%uR%u: CTL: %u\n", Channel, Rank, CtlPiCode[Channel]);
+        } else {
+          CtlPiCode[Channel] = 0;
+        }
+      }
+
+      MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\nCentering CTL on Rank %d\n", Rank);
+      CmdTimingCentering (MrcData, MrcIterationCtl, Ranks, Ranks, CtlPiCode);
+    }
+  } else // not Lpddr
+#endif //ULT_FLAG
+  {
+    //
+    // Center Clock Timing in the global eye
+    //
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\n*** Center Clock Timing in the Global eye\n");
+
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, " ALL Ranks - RankBitMask = %d\n", RankMask);
+    CmdTimingCentering (MrcData, MrcIterationClock, RankMask, 1, NULL);
+
+    //
+    // Center Command Timing
+    //
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\n\n*** Center Command S Timing\n");
+    CmdTimingCentering (MrcData, MrcIterationCmdS, RankMask, 1, CmdPiCode);
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\n\n*** Center Command N Timing\n");
+    CmdTimingCentering (MrcData, MrcIterationCmdN, RankMask, 1, CmdPiCode);
+
+    //
+    // Center Control Timing. For control pins, CKE PI is shared between Rank 2 and 3
+    //
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\n\n*** Center Control Timing. CKE PI is shared between Rank 2 and 3");
+    for (Rank = 0; Rank < (MAX_RANK_IN_CHANNEL - 1); Rank++) {
+      Ranks = (1 << Rank);
+
+      if (Rank == 2) {
+        Ranks = 0xC;
+      }
+
+      Ranks = Ranks & RankMask;
+
+      if (Ranks) {
+        MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\n\n Rank %d\n", Rank);
+        CmdTimingCentering (MrcData, MrcIterationCtl, Ranks, 1, CtlPiCode);
+      }
+    }
+  }
+
+  //
+  // Normalize timing back to 0 to improve performance
+  //
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\n*** Normalize timing back to 0\n");
+  for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+    if (!MrcChannelExist (Outputs, Channel)) {
+      continue;
+    }
+    ChannelOut = &ControllerOut->Channel[Channel];
+
+    //
+    // Find the minimum PI Code across all relevant CMD and CTL fubs
+    //
+    MinCode = ChannelOut->CkeCmdPiCode[0];
+    MinCode = MIN (MinCode, ChannelOut->CmdsCmdPiCode[0]);
+
+#ifdef ULT_FLAG
+    if (Lpddr) {
+      MinCode = MIN (MinCode, ChannelOut->CmdsCmdPiCode[1]);
+      MinCode = MIN (MinCode, ChannelOut->CmdnCmdPiCode[1]);
+    } else
+#endif //ULT_FLAG
+    {
+      MinCode = MIN (MinCode, ChannelOut->CmdnCmdPiCode[0]);
+    }
+
+    for (Rank = 0; Rank < MAX_RANK_IN_CHANNEL; Rank++) {
+      if (MrcRankInChannelExist (MrcData, Rank, Channel)) {
+        MinCode = MIN (MinCode, ChannelOut->CkePiCode[Rank]);
+        MinCode = MIN (MinCode, ChannelOut->CtlPiCode[Rank]);
+      }
+    }
+
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "C%d: shifting all PI settings by Min PI Code = %d\n", Channel, MinCode);
+    ShiftChannelTiming (MrcData, Channel, (-1) * MinCode, 1);
+  } // for Channel
+
+  //
+  // Disable CADB Deselects after Command Training
+  //
+  for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+    if (MrcChannelExist (Outputs, Channel)) {
+      Offset = MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_REG +
+        ((MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_REG - MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_REG) * Channel);
+      MrcWriteCR (MrcData, Offset, 0);
+    }
+  }
+
+  //
+  // Finish Training with JEDEC Reset / Init
+  //
+  Status = MrcResetSequence (MrcData);
+  return Status;
+}
+
+/**
+@brief
+  Perform Command Voltage Centering.
+
+  @param[in, out] MrcData - Include all MRC global data.
+
+  @retval MrcStatus -  if it succeded returns mrcSuccess
+**/
+MrcStatus
+MrcCmdVoltageCentering (
+  IN OUT MrcParameters *const MrcData
+  )
+{
+  const U16      mode = 0;
+  const MrcInput *Inputs;
+  const MrcDebug *Debug;
+  MrcOutput      *Outputs;
+  MrcChannelOut  *ChannelOut;
+  MrcStatus      Status;
+  U32            BERStats[4];
+  U32            Offset;
+  U8             LoopCount;
+  U8             ValidRankMask;
+  U8             Channel;
+  U8             Rank;
+  U8             chBitMask;
+  U8             RankMask;
+  U32            MinChLow;
+  U32            MinChHigh;
+  BOOL           Lpddr;
+#ifdef MRC_DEBUG_PRINT
+  U32            Low;
+  U32            High;
+  U32            Height;
+#endif
+  S32            Center;
+
+  Inputs        = &MrcData->SysIn.Inputs;
+  Debug         = &Inputs->Debug;
+  Outputs       = &MrcData->SysOut.Outputs;
+  ValidRankMask = Outputs->ValidRankMask;
+  Status    = mrcSuccess;
+  MinChLow  = 0xFFFFFFFF;
+  MinChHigh = 0xFFFFFFFF;
+  MrcOemMemorySet ((U8 *) BERStats, 0, sizeof (BERStats));
+
+  //
+  // Check if LPDDR3 memory is used
+  //
+  Lpddr = (Outputs->DdrType == MRC_DDR_TYPE_LPDDR3);
+
+  LoopCount = (Lpddr) ? 6 : 10;
+
+  MRC_DEBUG_MSG (
+    Debug,
+    MSG_LEVEL_NOTE,
+    "Cmd Vref Training with LC = %d\n\nMargin\nParams: CmdV\n\tLow\tHigh\tHeight\tCenter\n",
+    LoopCount
+    );
+
+  //
+  // Use CADB test for Cmd to match Late Command Training
+  //
+  SetupIOTestCADB (MrcData, Outputs->ValidChBitMask, LoopCount, NSOE, 1, 0);
+
+  //
+  // Select rank for REUT test
+  //
+  chBitMask = 0;
+  for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+    ChannelOut = &Outputs->Controller[0].Channel[Channel];
+    chBitMask |= SelectReutRanks (MrcData, Channel, ChannelOut->ValidRankBitMask, 0);
+    if ((MRC_BIT0 << Channel) & chBitMask) {
+      //
+      // Clear any old state in DataTrain Offset
+      //
+      MrcOemMemorySetDword (&ChannelOut->DataOffsetTrain[0], 0, Outputs->SdramCount);
+    }
+  }
+
+  //
+  // Run test for Cmd Voltage
+  //
+  Status = MrcGetBERMarginCh (
+            MrcData,
+            Outputs->MarginResult,
+            chBitMask,
+            0xFF,
+            0,
+            CmdV,
+            mode,
+            0,
+            MAX_POSSIBLE_VREF,
+            0,
+            BERStats
+            );
+  Status = MrcResetSequence (MrcData);
+
+  //
+  // Find center value and update Vref.
+  //
+  for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+    if (MrcChannelExist (Outputs, Channel)) {
+      MinChLow  = MIN (MinChLow, Outputs->MarginResult[LastCmdV][0][Channel][0][0]);
+      MinChHigh = MIN (MinChHigh, Outputs->MarginResult[LastCmdV][0][Channel][0][1]);
+    }
+  }
+  Center = ((S32) (MinChHigh - MinChLow)) / 2;
+  UpdateVrefWaitTilStable (MrcData, 2, 1, Center / 10, 0);
+  Status = MrcResetSequence (MrcData);
+
+#ifdef MRC_DEBUG_PRINT
+  //
+  // Print test results
+  //
+  for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+    if (MrcChannelExist (Outputs, Channel)) {
+      Low  = Outputs->MarginResult[LastCmdV][0][Channel][0][0] / 10;
+      High = Outputs->MarginResult[LastCmdV][0][Channel][0][1] / 10;
+      MRC_DEBUG_MSG (
+        Debug,
+        MSG_LEVEL_NOTE,
+        "C%u:\t%u\t%u\t%u\t%d\n",
+        Channel,
+        Low,
+        High,
+        Low + High,
+        ((S32) (High - Low)) / 2
+        );
+    }
+  }
+  Height = MinChHigh + MinChLow;
+  MRC_DEBUG_MSG (
+    Debug,
+    MSG_LEVEL_NOTE,
+    "Sys:\t%u\t%u\t%u\t%d\n",
+    MinChLow / 10,
+    MinChHigh / 10,
+    Height / 10,
+    Center / 10
+    );
+#endif
+
+  //
+  // Update MrcData for future tests
+  //
+  for (Rank = 0; Rank < MAX_RANK_IN_CHANNEL; Rank++) {
+    RankMask = MRC_BIT0 << Rank;
+    if (!(RankMask & ValidRankMask)) {
+      //
+      // Skip if all channels empty
+      //
+      continue;
+    }
+    Outputs->MarginResult[LastCmdV][Rank][0][0][0] = MinChLow + Center;
+    Outputs->MarginResult[LastCmdV][Rank][0][0][1] = MinChHigh - Center;
+  }
+  //
+  // Disable CADB Deselects
+  //
+  for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+    if (MrcChannelExist (Outputs, Channel)) {
+      Offset = MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_REG +
+        ((MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_REG - MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_REG) * Channel);
+      MrcWriteCR8 (MrcData, Offset, 0);
+    }
+  }
+
+  return Status;
+}
+
+/**
+@brief
+  Centers Command Timing around a MidPoint
+
+  @param[in] MrcData         - Include all MRC global data.
+  @param[in] Iteration       - Determines which PI to shift
+  @param[in] Ranks           - Valid Rank bit mask
+  @param[in] GroupMask       - which LPDDR groups to work on for CMD/CLK/CKE; not used for DDR3
+  @param[in] MidPoint        - The MidPoint to center around (per channel)
+
+  @retval Nothing
+**/
+void
+CmdTimingCentering (
+  IN MrcParameters *const MrcData,
+  IN U8                   Iteration,
+  IN U8                   Ranks,
+  IN U8                   GroupMask,
+  IN U8                   MidPoint[MAX_CHANNEL]
+  )
+{
+  const MrcDebug    *Debug;
+  MrcOutput         *Outputs;
+  MrcControllerOut  *ControllerOut;
+  U8                Ledge[MAX_CHANNEL];
+  U8                Redge[MAX_CHANNEL];
+  U8                Mid[MAX_CHANNEL];
+  U8                Low[MAX_CHANNEL];
+  U8                High[MAX_CHANNEL];
+  U8                MidValue;
+  S8                VrefOffsets[2];
+  U8                Center;
+  U8                ChBitMask;
+  U8                RankMask;
+  U8                Channel;
+  U8                MinWidth;
+  U8                lWidth;
+  BOOL              SkipVref;
+
+  Debug          = &MrcData->SysIn.Inputs.Debug;
+  Outputs        = &MrcData->SysOut.Outputs;
+  ControllerOut  = &Outputs->Controller[0];
+  VrefOffsets[0] = -8;
+  VrefOffsets[1] = 8;
+  MinWidth       = 18;
+  MrcOemMemorySet (Ledge, 0, sizeof (Ledge));
+  MrcOemMemorySet (Redge, 0, sizeof (Redge));
+
+   if ((Outputs->DdrType == MRC_DDR_TYPE_LPDDR3) && (Iteration != MrcIterationClock)) {
+    //
+    // Limit the binary search to +/- 32 PI ticks from the ECT midpoint, for LPDDR3 Command/Control
+    //
+    for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+      MidValue = MidPoint[Channel];
+      Low[Channel]  = (MidValue > 32) ? (MidValue - 32) : 0;
+      High[Channel] = (MidValue < 127 - 32) ? (MidValue + 32) : 127;
+      MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Ch%d: search range is [%d..%d]\n", Channel, Low[Channel], High[Channel]);
+    }
+  } else {
+    //
+    // Binary search will use the full PI range of [0..127] 
+    //
+    MrcOemMemorySet (Low,   0, sizeof (Low));
+    MrcOemMemorySet (High,  127, sizeof (High));
+  }
+
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Channel\t\t\t0 1\n");
+
+  //
+  // Setup REUT Test to iteration through appropriate ranks during test
+  //
+  ChBitMask = 0;
+  for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+    ChBitMask |= SelectReutRanks (MrcData, Channel, Ranks, 0);
+    if (MidPoint != NULL) {
+      Mid[Channel] = MidPoint[Channel];
+    }
+  }
+  //
+  // MRC_DEBUG_MSG (&MrcData->Inputs.Debug, MSG_LEVEL_NOTE, "**** CmdTimingCentering, Iteration = %d, ChBitMask = 0x%x\n", Iteration,ChBitMask);
+  //
+  if (Iteration == MrcIterationClock) {
+    //
+    // Use a linear search to center clock and Update Clock Delay/Host
+    // Allow wrap around since this is clock
+    // CmdLinearFindEdges also programs the new values
+    //
+    SkipVref = FALSE;
+    CmdLinearFindEdges (MrcData, Iteration, ChBitMask, Ranks, GroupMask, Low[0], High[0], 1, VrefOffsets, FALSE, SkipVref);
+  } else {
+    CmdBinaryFindEdge (MrcData, Iteration, ChBitMask, Ranks, GroupMask, Low, Mid, 0, VrefOffsets);
+    Ledge[0] = Mid[0];
+    Ledge[1] = Mid[1];  // CountUp is 0 so return High.
+    if (MidPoint == NULL) {
+      MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Midpoint[] is NULL and MrcIterationClock not selected!\n");
+    } else {
+      Mid[0]   = MidPoint[0];
+      Mid[1]   = MidPoint[1]; //Mid Modified by CmdBinaryFindEdge
+    }
+    CmdBinaryFindEdge (MrcData, Iteration, ChBitMask, Ranks, GroupMask, Mid, High, 1, VrefOffsets);
+    Redge[0] = Mid[0];
+    Redge[1] = Mid[1];  // CountUp is 1 so return Low.
+    //
+    // Update Variables:
+    //
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\nCH\tLeft\tRight\tWidth\tCenter");
+    for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+      if (((1 << Channel) & ChBitMask) == 0) {
+        continue;
+      }
+      RankMask  = Ranks & ControllerOut->Channel[Channel].ValidRankBitMask;
+      lWidth    = Redge[Channel] - Ledge[Channel];
+
+      if ((Redge[Channel] == 127) && (Ledge[Channel] == 0)) {
+        //
+        // No errors found
+        //
+        MRC_DEBUG_MSG (Debug, MSG_LEVEL_WARNING, "\nNo Errors Found for C%u!\n", Channel);
+        Center = MidPoint[Channel];
+      } else {
+        Center = (Ledge[Channel] + Redge[Channel] + 1) / 2;
+        if (lWidth < MinWidth) {
+          MRC_DEBUG_MSG (Debug, MSG_LEVEL_WARNING, "\nEye < %u for C%u!\n", MinWidth, Channel);
+        }
+      }
+
+      ShiftPIforCmdTraining (MrcData, Channel, Iteration, RankMask, GroupMask, Center, 1);
+
+      MRC_DEBUG_MSG (
+        Debug,
+        MSG_LEVEL_NOTE,
+        "\n %d\t%d\t%d\t%d\t%d",
+        Channel,
+        Ledge[Channel],
+        Redge[Channel],
+        lWidth,
+        Center
+        );
+    } // for Channel
+  }
+
+  return;
+}
+
+/**
+@brief
+  Use a linear search to find the edges between Low and High
+  if WrapAround = 0: Look for largest passing region between low and high
+  if WrapAround = 1: Look for largest passing region, including wrapping from high to low
+
+  @param[in, out] MrcData     - Include all MRC global data.
+  @param[in]      Iteration   - Determines which PI to shift
+  @param[in]      chBitMask   - Valid Channel bit mask
+  @param[in]      Ranks       - Valid Rank bit mask
+  @param[in]      GroupMask   - which LPDDR groups to work on for CMD/CLK/CKE; not used for DDR3
+  @param[in]      Low         - Low limit
+  @param[in]      High        - High limit
+  @param[in]      WrapAllowed - Determines the search region
+  @param[in]      VrefOffsets - Array of Vref offsets
+  @param[in]      SkipPrint   - Switch to enable or disable debug printing
+  @param[in]      SkipVref    - Skip changing CMD Vref offsets, only run test once at the current Vref.
+
+  @retval MrcStatus -  If it succeeds return mrcSuccess
+**/
+void
+CmdLinearFindEdges (
+  IN OUT MrcParameters *const MrcData,
+  IN     U8                   Iteration,
+  IN     U8                   chBitMask,
+  IN     U8                   Ranks,
+  IN     U8                   GroupMask,
+  IN     S8                   Low,
+  IN     U8                   High,
+  IN     U8                   WrapAllowed,
+  IN     S8                   *VrefOffsets,
+  IN     BOOL                 SkipPrint,
+  IN     BOOL                 SkipVref
+  )
+{
+  const MrcDebug    *Debug;
+  MrcOutput         *Outputs;
+  MrcControllerOut  *ControllerOut;
+  S32               *IPStart;
+  S32               *IPEnd;
+  S32               *CPStart;
+  S32               *CPEnd;
+  S32               *LPStart;
+  S32               *LPEnd;
+  MrcStatus         Status;
+  BOOL              Pass;
+  BOOL              Lpddr;
+  S32               InitialPassingStart[MAX_CHANNEL];
+  S32               InitialPassingEnd[MAX_CHANNEL];
+  S32               CurrentPassingStart[MAX_CHANNEL];
+  S32               CurrentPassingEnd[MAX_CHANNEL];
+  S32               LargestPassingStart[MAX_CHANNEL];
+  S32               LargestPassingEnd[MAX_CHANNEL];
+  S32               lWidth;
+  S32               iWidth;
+  S32               cWidth;
+  S32               Center;
+  S16               LCTDelay;
+  U8                Channel;
+  U8                ChannelMask;
+  U8                RankMask;
+  U8                Rank;
+  U8                LCTStep;
+  U8                LastStep;
+  U8                Vloop;
+  U8                ChError;
+  U8                DumArr[7];
+  S8                Vref;
+
+  Debug         = &MrcData->SysIn.Inputs.Debug;
+  Outputs       = &MrcData->SysOut.Outputs;
+  ControllerOut = &Outputs->Controller[0];
+  lWidth        = 0;
+  iWidth        = 0;
+  cWidth        = 0;
+  MrcOemMemorySet (DumArr, 1, sizeof (DumArr));
+
+  //
+  // Check if LPDDR3 memory is used
+  //
+  Lpddr = (Outputs->DdrType == MRC_DDR_TYPE_LPDDR3);
+
+  LCTStep = (Lpddr) ? 2 : 6;
+
+  //
+  // MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "**** CmdLinearFindEdges, Iteration = %d, Low = %d, High = %d\n", Iteration, Low, High);
+  //
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, (!SkipPrint) ? "CLkDlay" : "");
+
+  for (LCTDelay = Low; LCTDelay <= High; LCTDelay += LCTStep) {
+    //
+    // Update Timing
+    //
+    for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+      if ((1 << Channel) & chBitMask) {
+        RankMask = Ranks & ControllerOut->Channel[Channel].ValidRankBitMask;
+        ShiftPIforCmdTraining (MrcData, Channel, Iteration, RankMask, GroupMask, LCTDelay, 0);
+      }
+    }
+    //
+    // Reset DDR
+    //
+    Status = MrcResetSequence (MrcData);
+
+    //
+    // Run REUT until both channels fail or we finish all Vref points
+    //
+    if (SkipVref) {
+      ChError = RunIOTest (MrcData, chBitMask, Outputs->DQPat, DumArr, 1, 0);
+    } else {
+      ChError = 0;
+      for (Vloop = 0; Vloop < 2; Vloop++) {
+        Vref = VrefOffsets[Vloop];
+        UpdateVrefWaitTilStable (MrcData, 2, 0, Vref, 0);
+
+        ChError |= RunIOTest (MrcData, chBitMask, Outputs->DQPat, DumArr, 1, 0);
+
+        if (ChError == chBitMask) {
+          break;
+        }
+
+      }
+    }
+
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, (!SkipPrint) ? "\n %d\t\t\t" : "", LCTDelay);
+
+    //
+    // Update Passing Variables
+    //
+    for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+      ChannelMask = MRC_BIT0 << Channel;
+      if (!(ChannelMask & chBitMask)) {
+        MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, (!SkipPrint && (Channel == 0)) ? "  " : "");
+        continue;
+      }
+
+      Pass = !(ChError & ChannelMask);
+
+      MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, (!SkipPrint) ? (Pass ? ". " : "# ") : "");
+
+      IPStart = &InitialPassingStart[Channel];
+      IPEnd   = &InitialPassingEnd[Channel];
+      CPStart = &CurrentPassingStart[Channel];
+      CPEnd   = &CurrentPassingEnd[Channel];
+      LPStart = &LargestPassingStart[Channel];
+      LPEnd   = &LargestPassingEnd[Channel];
+
+      if (LCTDelay == (S16) Low) {
+        if (Pass) {
+          *IPStart = *IPEnd = *CPStart = *CPEnd = *LPStart = *LPEnd = Low;
+        } else {
+          *IPStart = *IPEnd = *CPStart = *CPEnd = *LPStart = *LPEnd = Low - LCTStep;
+        }
+      } else {
+        if (Pass) {
+          //
+          // Update Initial variables
+          //
+          if (*IPEnd == (LCTDelay - LCTStep)) {
+            *IPEnd = LCTDelay; // In passing region
+          }
+          //
+          // Update Current variables
+          //
+          if (*CPEnd == (LCTDelay - LCTStep)) {
+            *CPEnd = LCTDelay; // In passing region
+          } else {
+            *CPStart = *CPEnd = LCTDelay;
+          }
+          //
+          // Special case for last step: Append Initial Passing Region
+          // LCTDelay should be considered a continuous range that wraps around 0
+          //
+          LastStep = High - LCTStep;
+          if ((LCTDelay >= LastStep) && (*IPStart == Low) && WrapAllowed) {
+            iWidth = *IPEnd -*IPStart;
+            *CPEnd += (LCTStep + iWidth);
+          }
+          //
+          // Update Largest variables
+          //
+          cWidth = *CPEnd - *CPStart;
+          lWidth = *LPEnd - *LPStart;
+          if (cWidth > lWidth) {
+            *LPStart = *CPStart;
+            *LPEnd   = *CPEnd;
+          }
+        }
+      }
+    } // for Channel
+
+
+  } // for LCTDelay
+
+  if (!SkipPrint) {
+    //
+    // Update Variables:
+    //
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\nCH\tLeft\tRight\tWidth\tCenter\n");
+  }
+
+  for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+    if ((MRC_BIT0 << Channel) & chBitMask) {
+      LPStart = &LargestPassingStart[Channel];
+      LPEnd   = &LargestPassingEnd[Channel];
+      //
+      // Handle any corner cases
+      //
+      lWidth  = *LPEnd - *LPStart;
+      if ((lWidth < (3 * LCTStep)) || (lWidth >= (High - Low))) {
+        //
+        // @todo: Pass a default center parameter instead of line below.
+        //
+        Center = (Low + High) / 2;
+        MRC_DEBUG_MSG (Debug, MSG_LEVEL_WARNING, "\nError Handler! Found Bad command Eye\n");
+      } else {
+        Center = (*LPEnd + *LPStart) / 2;
+      }
+      RankMask = Ranks & ControllerOut->Channel[Channel].ValidRankBitMask;
+      if (!SkipPrint) {
+        //
+        // Shift Timing
+        //
+        ShiftPIforCmdTraining (MrcData, Channel, Iteration, RankMask, GroupMask, Center, 1);
+
+        MRC_DEBUG_MSG (
+          Debug,
+          MSG_LEVEL_NOTE,
+          " %d\t%d\t%d\t%d\t%d\n",
+          Channel,
+          *LPStart,
+          *LPEnd,
+          lWidth,
+          Center
+          );
+      }
+      //
+      // Determine in which rank to save the margins...
+      //
+      for (Rank = 0; Rank < MAX_RANK_IN_CHANNEL; Rank++) {
+        if ((RankMask >> Rank) & MRC_BIT0) {
+          Outputs->MarginResult[LastCmdT][Rank][Channel][0][0] = 10 * ABS (*LPStart);
+          Outputs->MarginResult[LastCmdT][Rank][Channel][0][1] = 10 * ABS (*LPEnd);
+        }
+      }
+    }
+  }
+  //
+  // Clean Up
+  //
+  if (!SkipVref) {
+    UpdateVrefWaitTilStable (MrcData, 2, 0, 0, 0);
+  }
+
+  Status = MrcResetSequence (MrcData);
+  return;
+}
+
+/**
+@brief
+  Use a binary search to find the edge between Low and High
+  High and Low track passing points
+  if CountUp: Low is a passing point and need to count up to find a failing point
+  if CountDn: High is a passing point and need to count dn to find a failing point
+
+  @param[in]      MrcData     - Include all MRC global data.
+  @param[in]      Iteration   - Determines which PI to shift
+  @param[in]      ChBitMask   - Valid Channel bit mask
+  @param[in]      Ranks       - Valid Rank bit mask
+  @param[in]      GroupMask   - which LPDDR groups to work on for CMD/CLK/CKE; not used for DDR3
+  @param[in, out] Low         - Low limit
+  @param[in, out] High        - High limit
+  @param[in]      CountUp     - The direction to search
+  @param[in]      VrefOffsets - Array of Vref offsets
+
+  @retval Nothing
+**/
+void
+CmdBinaryFindEdge (
+  IN     MrcParameters *const MrcData,
+  IN     U8                   Iteration,
+  IN     U8                   ChBitMask,
+  IN     U8                   Ranks,
+  IN     U8                   GroupMask,
+  IN OUT U8                   *Low,
+  IN OUT U8                   *High,
+  IN     U8                   CountUp,
+  IN     S8                   *VrefOffsets
+  )
+{
+  const MrcDebug    *Debug;
+  MrcOutput         *Outputs;
+  MrcControllerOut  *ControllerOut;
+  MrcStatus         Status;
+  U8                Target[MAX_CHANNEL];
+  U8                Done;
+  U8                ChError;
+  U8                DumArr[7];
+  S8                Vref;
+  U8                Channel;
+  U8                ChannelMask;
+  U8                RankMask;
+  U8                Group;
+  U8                Fail;
+  U8                Vloop;
+
+  Debug         = &MrcData->SysIn.Inputs.Debug;
+  Outputs       = &MrcData->SysOut.Outputs;
+  ControllerOut = &Outputs->Controller[0];
+  Done          = 0;
+  ChError       = 0;
+  MrcOemMemorySet (Target, 0, sizeof (Target));
+  MrcOemMemorySet (DumArr, 1, sizeof (DumArr));
+
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "CmdTgt\nCh0G0\tCh0G1\tCh1G0\tCh1G1\n");
+
+  while (!Done) {
+    //
+    // Update Timing
+    //
+    for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+      if (((1 << Channel) & ChBitMask) == 0) {
+        MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\t");
+      } else {
+        Target[Channel] = (High[Channel] + Low[Channel] + CountUp) / 2;    // CountUp gets rounding correct
+        RankMask = Ranks & ControllerOut->Channel[Channel].ValidRankBitMask;
+        for (Group = 0; Group < 2; Group++) {
+          if (((1 << Group) & GroupMask) == 0) {
+            MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\t");
+          } else {
+            ShiftPIforCmdTraining (MrcData, Channel, Iteration, RankMask, 1 << Group, Target[Channel], 0);
+            MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%d\t", Target[Channel]);
+          }
+        }
+      }
+    }
+
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\t");
+
+    //
+    // Reset DDR
+    //
+    Status = MrcResetSequence (MrcData);
+
+    //
+    // Run REUT until both channels fail or we finish all Vref points
+    //
+    ChError = 0;
+    for (Vloop = 0; Vloop < 2; Vloop++) {
+      Vref = VrefOffsets[Vloop];
+      //
+      // MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "**** Run REUT until both channels fail or we finish all Vref points, Vref = %d\n", Vref);
+      //
+      UpdateVrefWaitTilStable (MrcData, 2, 0, Vref, 0);
+
+      ChError |= RunIOTest (MrcData, ChBitMask, Outputs->DQPat, DumArr, 1, 0);
+      if (ChError == ChBitMask) {
+        break;
+      }
+
+    }
+
+    //
+    // Update High/Low
+    //
+    for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+      ChannelMask = 1 << Channel;
+      if (!(ChannelMask & ChBitMask)) {
+        MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, (Channel == 0) ? "  " : "");
+      } else {
+        Fail = (ChError & ChannelMask);
+
+        MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, Fail ? "# " : ". ");
+
+        //
+        // Skip if this channel is done
+        //
+        if (High[Channel] > Low[Channel]) {
+          if (CountUp) {
+            if (Fail) {
+              High[Channel] = Target[Channel] - 1;
+            } else {
+              Low[Channel] = Target[Channel];
+            }
+          } else {
+            if (Fail) {
+              Low[Channel] = Target[Channel] + 1;
+            } else {
+              High[Channel] = Target[Channel];
+            }
+          }
+        }
+      }
+    }
+    //
+    // Update Done
+    //
+    Done = 1;
+    for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+      if ((1 << Channel) & ChBitMask) {
+        if (High[Channel] > Low[Channel]) {
+          Done = 0;
+        }
+      }
+    }
+
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\n");
+  }
+  //
+  // Clean Up
+  //
+  UpdateVrefWaitTilStable (MrcData, 2, 0, 0, 0);
+  MrcResetSequence (MrcData);
+  return;
+}
+
+/**
+@brief
+  Shift the CLK/CMD/CTL Timing by the given PI setting value
+
+  @param[in] MrcData    - Include all MRC global data.
+  @param[in] Channel    - Channel to shift
+  @param[in] Offset     - Offset to shift by
+  @param[in] UpdateHost - Switch to update the host structure
+
+  @retval Nothing
+**/
+void
+ShiftChannelTiming (
+  IN MrcParameters *const MrcData,
+  IN U8                   Channel,
+  IN S32                  Offset,
+  IN U8                   UpdateHost
+  )
+{
+  const MrcDebug      *Debug;
+  const MrcInput      *Inputs;
+  const MrcChannelIn  *ChannelIn;
+  MrcChannelOut       *ChannelOut;
+  S32                 NewCode;
+  U8                  Rank;
+  U8                  RankBit;
+#ifdef ULT_FLAG
+  U8                  Group;
+  BOOL                Lpddr;
+#endif // ULT_FLAG
+
+  Inputs      = &MrcData->SysIn.Inputs;
+  Debug       = &Inputs->Debug;
+  ChannelIn   = &Inputs->Controller[0].Channel[Channel];
+  ChannelOut  = &MrcData->SysOut.Outputs.Controller[0].Channel[Channel];
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Channel %d:\n", Channel);
+
+#ifdef ULT_FLAG
+  //
+  // Check if LPDDR3 memory is used
+  //
+  Lpddr = (MrcData->SysOut.Outputs.DdrType == MRC_DDR_TYPE_LPDDR3);
+#endif // ULT_FLAG
+
+  //
+  // Shift the CLK/CTL Timing
+  //
+  for (Rank = 0; Rank < MAX_RANK_IN_CHANNEL; Rank++) {
+    if (MrcRankInChannelExist (MrcData, Rank, Channel)) {
+      RankBit = 1 << Rank;
+      NewCode = ChannelOut->ClkPiCode[Rank] + Offset;
+#ifdef ULT_FLAG
+      if (!Lpddr)
+#endif // ULT_FLAG
+      {
+        //
+        // CLK is per Rank in DDR3
+        //
+        ShiftPIforCmdTraining (MrcData, Channel, MrcIterationClock, RankBit, RankBit, Offset, UpdateHost);
+        MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, " R%d New CLK value = %d\n", Rank, NewCode);
+      }
+
+      NewCode = ChannelOut->CtlPiCode[Rank] + Offset;
+      ShiftPIforCmdTraining (MrcData, Channel, MrcIterationCtl, RankBit, 1, NewCode, UpdateHost);
+      MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, " R%d New CTL value = %d\n", Rank, NewCode);
+    }
+  }
+
+  //
+  // Shift the CMD Timing
+  //
+  NewCode = ChannelOut->CmdsCmdPiCode[0] + Offset;
+  ShiftPIforCmdTraining (MrcData, Channel, MrcIterationCmdS, ChannelOut->ValidRankBitMask, 1, NewCode, UpdateHost);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, " New CMDS[0] value = %d\n", NewCode);
+
+#ifdef ULT_FLAG
+  if (Lpddr) {
+    //
+    // CLK is per Group in LPDDR3
+    //
+    for (Group = 0; Group < 2; Group++) {
+      if (ChannelIn->DQByteMap[MrcIterationClock][Group] != 0) {
+        ShiftPIforCmdTraining (MrcData, Channel, MrcIterationClock, 0, 1 << Group, Offset, UpdateHost);
+        MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, " New CLK%d value = %d\n", Group, ChannelOut->ClkPiCode[Group]);
+      }
+    }
+
+    NewCode = ChannelOut->CkeCmdPiCode[0] + Offset;
+    ShiftPIforCmdTraining (MrcData, Channel, MrcIterationCke, ChannelOut->ValidRankBitMask, 1, NewCode, UpdateHost);
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, " New CKE[0] value = %d\n", NewCode);
+
+    NewCode = ChannelOut->CmdsCmdPiCode[1] + Offset;
+    ShiftPIforCmdTraining (MrcData, Channel, MrcIterationCmdS, ChannelOut->ValidRankBitMask, 2, NewCode, UpdateHost);
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, " New CMDS[1] value = %d\n", NewCode);
+
+    NewCode = ChannelOut->CmdnCmdPiCode[1] + Offset;
+    ShiftPIforCmdTraining (MrcData, Channel, MrcIterationCmdN, ChannelOut->ValidRankBitMask, 2, NewCode, UpdateHost);
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, " New CMDN[1] value = %d\n", NewCode);
+  } else
+#endif // ULT_FLAG
+  {
+    NewCode = ChannelOut->CmdnCmdPiCode[0] + Offset;
+    ShiftPIforCmdTraining (MrcData, Channel, MrcIterationCmdN, ChannelOut->ValidRankBitMask, 1, NewCode, UpdateHost);
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, " New CMDN[0] value = %d\n", NewCode);
+  }
+  return;
+}
+
+/**
+@brief
+  This function updtes Command Mode register, tXP and Round trip latency
+
+  @param[in, out] MrcData     - Include all MRC global data.
+  @param[in]      Channel     - Channel to perform update to
+  @param[in]      OldN        - Old N Mode value
+  @param[in]      NewN        - New N mode value
+
+  @retval Nothing
+**/
+void
+UpdateCmdNTiming (
+  IN OUT MrcParameters *const MrcData,
+  IN     U8                   Channel,
+  IN     U8                   OldN,
+  IN     U8                   NewN
+  )
+{
+  const U8 CmdStretch[1 << MCHBAR_CH0_CR_TC_BANK_RANK_A_CMD_stretch_WID] = {
+    0,
+    2,
+    3,
+    MCHBAR_CH0_CR_TC_BANK_RANK_A_CMD_stretch_DEF
+  };
+
+  const MrcDebug                      *Debug;
+  MrcOutput                           *Outputs;
+  MrcChannelOut                       *ChannelOut;
+  U8                                  *RtLatency;
+  MCHBAR_CH0_CR_TC_BANK_RANK_A_STRUCT TcBankRankA;
+  MCHBAR_CH0_CR_TC_BANK_RANK_C_STRUCT TcBankRankC;
+  MCHBAR_CH0_CR_SC_ROUNDT_LAT_STRUCT  ScRoundtLat;
+  MrcProfile                          Profile;
+  U32                                 Offset;
+  U32                                 Scratch;
+  U8                                  Rank;
+  S8                                  Diff;
+
+  Debug      = &MrcData->SysIn.Inputs.Debug;
+  Outputs    = &MrcData->SysOut.Outputs;
+  ChannelOut = &Outputs->Controller[0].Channel[Channel];
+  Profile    = MrcData->SysIn.Inputs.MemoryProfile;
+
+  //
+  // Update CmdN timing
+  //
+  Offset = MCHBAR_CH0_CR_TC_BANK_RANK_A_REG +
+    ((MCHBAR_CH1_CR_TC_BANK_RANK_A_REG - MCHBAR_CH0_CR_TC_BANK_RANK_A_REG) * Channel);
+  TcBankRankA.Data              = MrcReadCR (MrcData, Offset);
+  TcBankRankA.Bits.CMD_stretch  = CmdStretch[ChannelOut->Timing[Profile].NMode - 1];
+  MrcWriteCR (MrcData, Offset, TcBankRankA.Data);
+  ChannelOut->MchbarBANKRANKA = TcBankRankA.Data;
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "C%d_TC_BANK_RANK_A = 0x%x\n", Channel, TcBankRankA.Data);
+
+  //
+  // Adjust tXP value
+  //
+  Offset = MCHBAR_CH0_CR_TC_BANK_RANK_C_REG +
+    ((MCHBAR_CH1_CR_TC_BANK_RANK_C_REG - MCHBAR_CH0_CR_TC_BANK_RANK_C_REG) * Channel);
+  TcBankRankC.Data      = MrcReadCR (MrcData, Offset);
+  Scratch = tXPValue (Outputs->DdrType, Outputs->Frequency, (U8) ChannelOut->Timing[Profile].NMode);
+  TcBankRankC.Bits.tXP  = MIN (Scratch, MCHBAR_CH0_CR_TC_BANK_RANK_C_tXP_MAX);
+  MrcWriteCR (MrcData, Offset, TcBankRankC.Data);
+  ChannelOut->MchbarBANKRANKC = TcBankRankC.Data;
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "C%d_TC_BANK_RANK_C = 0x%x\n", Channel, TcBankRankC.Data);
+
+  //
+  // Adjust RT values to compensate.
+  //
+  Diff              = (NewN - OldN);
+  ScRoundtLat.Data  = 0;
+  for (Rank = 0; Rank < MAX_RANK_IN_CHANNEL; Rank++) {
+    if (MrcRankInChannelExist (MrcData, Rank, Channel)) {
+      RtLatency  = &ChannelOut->RTLatency[Rank];
+      *RtLatency = (U8) (*RtLatency + Diff);
+        switch (Rank) {
+          case 0:
+            ScRoundtLat.Bits.Lat_R0D0 = *RtLatency;
+            break;
+
+          case 1:
+            ScRoundtLat.Bits.Lat_R1D0 = *RtLatency;
+            break;
+
+          case 2:
+            ScRoundtLat.Bits.Lat_R0D1 = *RtLatency;
+            break;
+
+          case 3:
+            ScRoundtLat.Bits.Lat_R1D1 = *RtLatency;
+            break;
+
+          default:
+            break;
+        }
+    }
+  }
+
+  Offset = MCHBAR_CH0_CR_SC_ROUNDT_LAT_REG +
+    ((MCHBAR_CH1_CR_SC_ROUNDT_LAT_REG - MCHBAR_CH0_CR_SC_ROUNDT_LAT_REG) * Channel);
+  MrcWriteCR (MrcData, Offset, ScRoundtLat.Data);
+  return;
+}
+
+#ifdef ULT_FLAG
+
+/**
+@brief
+  Enter / exit LPDDR CA training modes.
+  Main flow:
+  1. Force CKE high.
+  2. Send MRW 41, 48 or 42.
+  3. Force CKE low for MRW 41 or 48
+
+  @param[in] MrcData      - The MRC global data.
+  @param[in] ChBitMask    - channels to work on.
+  @param[in] RankBitMask  - ranks to work on.
+  @param[in] Mode         - CA training mode.
+
+  @retval mrcSuccess if succeeded
+**/
+MrcStatus
+LpddrCommandTrainingMode (
+  IN MrcParameters * const MrcData,
+  IN U8                    ChBitMask,
+  IN U8                    RankBitMask,
+  IN MrcCaTrainingMode     Mode
+  )
+{
+  MrcStatus         Status;
+  MrcOutput         *Outputs;
+  MrcControllerOut  *ControllerOut;
+  U8                Channel;
+  U8                Rank;
+  U32               Offset;
+  U32               Address;
+  U32               Data;
+  BOOL              InitMrw;
+  BOOL              ChipSelect2N;
+  MCHBAR_CH0_CR_REUT_CH_MISC_CKE_CTRL_STRUCT MiscCkeCtrl;
+
+  Outputs       = &MrcData->SysOut.Outputs;
+  ControllerOut = &Outputs->Controller[0];
+
+  InitMrw = TRUE;
+  ChipSelect2N = FALSE;
+
+  switch (Mode) {
+    case CaTrainingMode41:
+      Address = 0x29;
+      Data    = 0xA4;   // Data is selected so that High and Low phases of CA[9:0] are equal
+      break;
+
+    case CaTrainingMode48:
+      Address = 0x30;
+      Data    = 0xC0;
+      break;
+
+    case CaTrainingMode42:
+      Address = 0x2A;
+      Data    = 0xA8;
+      ChipSelect2N = FALSE;
+      break;
+
+    default:
+      return mrcFail;
+  }
+
+  //
+  // Send the MRW41 command to populated ranks
+  //
+  for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+    if (((1 << Channel) & ChBitMask) == 0) {
+      continue;
+    }
+
+    //
+    // Force CKE high
+    //
+    MiscCkeCtrl.Data = 0;
+    MiscCkeCtrl.Bits.CKE_Override = 0x0F;
+    MiscCkeCtrl.Bits.CKE_On       = ControllerOut->Channel[Channel].ValidCkeBitMask;
+    Offset = MCHBAR_CH0_CR_REUT_CH_MISC_CKE_CTRL_REG +
+      (MCHBAR_CH1_CR_REUT_CH_MISC_CKE_CTRL_REG - MCHBAR_CH0_CR_REUT_CH_MISC_CKE_CTRL_REG) * Channel;
+    MrcWriteCR (MrcData, Offset, MiscCkeCtrl.Data);
+
+    //
+    // Wait for CKE to become effective
+    //
+    MrcWait (MrcData, 1 * HPET_MIN);
+
+    for (Rank = 0; Rank < MAX_RANK_IN_CHANNEL; Rank ++) {
+      if (!MrcRankInChannelExist (MrcData, Rank, Channel)) {
+        continue;
+      }
+      if (((1 << Rank) & RankBitMask) != 0) {
+        Status = MrcIssueMrw (MrcData, Channel, Rank, Address, Data, InitMrw, ChipSelect2N);
+        if (Status != mrcSuccess) {
+          return Status;
+        }
+      }
+    }
+
+    //
+    // Force CKE Low for MRW 41 or 48
+    //
+    if (Mode != CaTrainingMode42) {
+      //
+      // Wait tCACKEL = 10 tCK
+      //
+      MrcWait (MrcData, 1 * HPET_MIN);
+
+      //
+      // Force CKE low, tCACKEL after MRW41 issued
+      //
+      MiscCkeCtrl.Bits.CKE_On = 0;
+      MrcWriteCR (MrcData, Offset, MiscCkeCtrl.Data);
+    }
+  }  // for Channel
+  return mrcSuccess;
+}
+
+/**
+  Program CADB Pattern Buffers with given values
+
+  @param[in] MrcData    - The MRC global data.
+  @param[in] Channel    - channel to work on.
+  @param[in] PatBuf0    - Pattern Buffer 0 value
+  @param[in] PatBuf1    - Pattern Buffer 1 value
+  @param[in] PatBuf2    - Pattern Buffer 2 value
+
+  @retval none
+**/
+void
+SetCadbPatternBuffers (
+  IN MrcParameters * const  MrcData,
+  IN U8                     Channel,
+  IN U32                    PatBuf0,
+  IN U32                    PatBuf1,
+  IN U32                    PatBuf2
+  )
+{
+  U32 Offset;
+
+  Offset = MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_PB_0_REG +
+    ((MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_PB_0_REG - MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_PB_0_REG) * Channel);
+  MrcWriteCR (MrcData, Offset, PatBuf0);
+
+  Offset = MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_PB_1_REG +
+    ((MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_PB_1_REG - MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_PB_1_REG) * Channel);
+  MrcWriteCR (MrcData, Offset, PatBuf1);
+
+  Offset = MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_PB_2_REG +
+    ((MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_PB_2_REG - MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_PB_2_REG) * Channel);
+  MrcWriteCR (MrcData, Offset, PatBuf2);
+}
+
+//
+//  Sets up 3 CADB lines that will be used to send out a CS pattern.
+//
+//  -----------------------
+//  CADB  Phase  Phase  CS
+//  Line  High   Low
+//  -----------------------
+//   0    0x000  0x000  Off
+//   1    0x3FF  0x3FF  Off
+//   2    0x2AA  0x2AA  On
+//   3    0x155  0x155  On
+//
+//  The CS pattern uses Pattern Buffer and hence has 16 lines, with CS active for one line only.
+//  This will send a command every 16 DCLKs.
+//
+//  Pattern Buffer details:
+//  The line order is:    0, 0, 2, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+//  or different command: 0, 0, 3, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+//
+//  000
+//  000
+//  000
+//  000
+//
+//  000
+//  000
+//  000
+//  000
+//
+//  000
+//  000
+//  000
+//  000
+//
+//  001
+//  001
+//  010 or 011
+//  000
+//  ----
+//  000  --> PB[0] = 0x3000 or 0x7000
+//  000      PB[1] = 0x4000
+//  000      PB[2] = 0x0000
+//  043 or 047
+//
+CADB_LINE CadbLinesCs[] = {
+  { 0x000, 0x000, 0 },
+  { 0x3FF, 0x3FF, 0 },
+  { 0x2AA, 0x2AA, 1 },
+  { 0x155, 0x155, 1 }
+};
+
+/**
+  Setup the CADB for CS or CA training.
+
+  @param[in] MrcData    - The MRC global data.
+  @param[in] Channel    - channel to work on
+  @param[in] Rank       - rank to work on
+  @param[in] CadbLines  - CADB lines to program
+  @param[in] CadbCount  - Number of CADB lines to program
+  @param[in] PatBuf0    - Pattern Buffer 0 value
+  @param[in] PatBuf1    - Pattern Buffer 1 value
+  @param[in] PatBuf2    - Pattern Buffer 2 value
+  @retval none
+**/
+void
+SetupCaTrainingCadb (
+  IN MrcParameters  * const MrcData,
+  IN U8             Channel,
+  IN U8             Rank,
+  IN CADB_LINE      *CadbLines,
+  IN U32            CadbCount,
+  IN U32            PatBuf0,
+  IN U32            PatBuf1,
+  IN U32            PatBuf2
+)
+{
+  U32 Offset;
+  U32 MA;
+  U32 BA;
+  U32 CMD;
+  U32 i;
+
+  MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_CTRL_STRUCT  ReutChPatCadbMuxCtrl;
+  MCHBAR_CH0_CR_REUT_CH_PAT_CADB_PROG_STRUCT      ReutChPatCadbProg;
+
+  //
+  // Set Mux0/1/2 to Pattern Buffer mode
+  //
+  Offset = MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_CTRL_REG +
+    ((MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_CTRL_REG - MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_CTRL_REG) * Channel);
+  ReutChPatCadbMuxCtrl.Data = MrcReadCR (MrcData, Offset);
+  ReutChPatCadbMuxCtrl.Bits.Mux0_Control = 1;
+  ReutChPatCadbMuxCtrl.Bits.Mux1_Control = 1;
+  ReutChPatCadbMuxCtrl.Bits.Mux2_Control = 1;
+  MrcWriteCR (MrcData, Offset, ReutChPatCadbMuxCtrl.Data);
+
+  //
+  // Program Pattern Buffers for a specific progression over CADB,
+  // according to the given Pattern Buffer values
+  //
+  SetCadbPatternBuffers (MrcData, Channel, PatBuf0, PatBuf1, PatBuf2);
+
+  //
+  // Start writing at CADB row 0
+  //
+  Offset = MCHBAR_CH0_CR_REUT_CH_PAT_CADB_WRITE_POINTER_REG +
+    ((MCHBAR_CH1_CR_REUT_CH_PAT_CADB_WRITE_POINTER_REG - MCHBAR_CH0_CR_REUT_CH_PAT_CADB_WRITE_POINTER_REG) * Channel);
+  MrcWriteCR (MrcData, Offset, 0);
+
+  ReutChPatCadbProg.Data = 0;
+  ReutChPatCadbProg.Bits.CADB_Data_ODT = (0 << Rank);
+  ReutChPatCadbProg.Bits.CADB_Data_CKE = (0 << Rank);
+
+  //
+  // Program the CADB lines
+  //
+  Offset = MCHBAR_CH0_CR_REUT_CH_PAT_CADB_PROG_REG +
+    ((MCHBAR_CH1_CR_REUT_CH_PAT_CADB_PROG_REG - MCHBAR_CH0_CR_REUT_CH_PAT_CADB_PROG_REG) * Channel);
+  for (i = 0; i < CadbCount ; i++) {
+    MrcConvertLpddr2Ddr (CadbLines[i].CaHigh, CadbLines[i].CaLow, &MA, &BA, &CMD);
+    ReutChPatCadbProg.Bits.CADB_Data_Address  = MA;
+    ReutChPatCadbProg.Bits.CADB_Data_Bank     = BA;
+    ReutChPatCadbProg.Bits.CADB_Data_Control  = CMD;
+    ReutChPatCadbProg.Bits.CADB_Data_CS       = 0x0F & ~(CadbLines[i].ChipSelect << Rank);
+
+    //
+    // Write CADB line. It is auto incremented after every write
+    //
+    MrcWriteCR64 (MrcData, Offset, ReutChPatCadbProg.Data);
+  }
+}
+
+/**
+  Program DESWIZZLE_HIGH/LOW registers for MR4 decoding
+
+  @param[in] MrcData - The MRC global data.
+
+  @retval none
+**/
+void
+ProgramDeswizzleRegisters (
+  IN MrcParameters * const  MrcData
+  )
+{
+  MrcInput          *Inputs;
+  MrcDebug          *Debug;
+  MrcOutput         *Outputs;
+  MrcChannelIn      *ChannelIn;
+  MrcChannelOut     *ChannelOut;
+  MrcControllerOut  *ControllerOut;
+  U8                Channel;
+  U32               Byte;
+  U8                Bit;
+  U32               Offset;
+  MCHBAR_CH0_CR_DESWIZZLE_LOW_STRUCT  DeswizzleLow;
+  MCHBAR_CH0_CR_DESWIZZLE_HIGH_STRUCT DeswizzleHigh;
+
+  Inputs  = &MrcData->SysIn.Inputs;
+  Debug   = &Inputs->Debug;
+  Outputs = &MrcData->SysOut.Outputs;
+  ControllerOut = &Outputs->Controller[0];
+
+  for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+    if (!MrcChannelExist (Outputs, Channel)) {
+      continue;
+    }
+    ChannelIn = &Inputs->Controller[0].Channel[Channel];
+    ChannelOut = &ControllerOut->Channel[Channel];
+
+    DeswizzleLow.Data   = 0;
+    DeswizzleHigh.Data  = 0;
+
+    for (Byte = 0; Byte <= 7; Byte++) {
+      //
+      // DqsMapCpu2Dram maps CPU bytes to DRAM, we need to find the reverse mapping here
+      //
+      switch (ChannelIn->DqsMapCpu2Dram[Byte]) {
+        case 0:
+          DeswizzleLow.Bits.Byte_0  = Byte;
+          break;
+        case 2:
+          DeswizzleLow.Bits.Byte_2  = Byte;
+          break;
+        case 4:
+          DeswizzleHigh.Bits.Byte_4 = Byte;
+          break;
+        case 6:
+          DeswizzleHigh.Bits.Byte_6 = Byte;
+          break;
+      }
+    }
+
+    for (Bit = 0; Bit <= 7; Bit++) {
+      //
+      // DqMapCpu2Dram maps CPU DQ pins to DRAM, we need to find the reverse mapping here
+      //
+      Byte = DeswizzleLow.Bits.Byte_0;
+      switch (ChannelIn->DqMapCpu2Dram[Byte][Bit]) {
+        case 0:
+          DeswizzleLow.Bits.Bit_0 = Bit;
+          break;
+        case 1:
+          DeswizzleLow.Bits.Bit_1 = Bit;
+          break;
+        case 2:
+          DeswizzleLow.Bits.Bit_2 = Bit;
+          break;
+      }
+
+      Byte = DeswizzleLow.Bits.Byte_2;
+      switch (ChannelIn->DqMapCpu2Dram[Byte][Bit]) {
+        case 16:
+          DeswizzleLow.Bits.Bit_16 = Bit;
+          break;
+        case 17:
+          DeswizzleLow.Bits.Bit_17 = Bit;
+          break;
+        case 18:
+          DeswizzleLow.Bits.Bit_18 = Bit;
+          break;
+      }
+
+      Byte = DeswizzleHigh.Bits.Byte_4;
+      switch (ChannelIn->DqMapCpu2Dram[Byte][Bit]) {
+        case 32:
+          DeswizzleHigh.Bits.Bit_32 = Bit;
+          break;
+        case 33:
+          DeswizzleHigh.Bits.Bit_33 = Bit;
+          break;
+        case 34:
+          DeswizzleHigh.Bits.Bit_34 = Bit;
+          break;
+      }
+
+      Byte = DeswizzleHigh.Bits.Byte_6;
+      switch (ChannelIn->DqMapCpu2Dram[Byte][Bit]) {
+        case 48:
+          DeswizzleHigh.Bits.Bit_48 = Bit;
+          break;
+        case 49:
+          DeswizzleHigh.Bits.Bit_49 = Bit;
+          break;
+        case 50:
+          DeswizzleHigh.Bits.Bit_50 = Bit;
+          break;
+      }
+    } // for Bit
+
+    if (ChannelOut->Dimm[dDIMM0].SdramWidth == 32) {
+      //
+      // Bytes 2 and 6 (and their bits) are irrelevant for x32 devices - copy from Bytes 0 and 4 instead
+      //
+      DeswizzleLow.Bits.Byte_2 = DeswizzleLow.Bits.Byte_0;
+      DeswizzleLow.Bits.Bit_16 = DeswizzleLow.Bits.Bit_0;
+      DeswizzleLow.Bits.Bit_17 = DeswizzleLow.Bits.Bit_1;
+      DeswizzleLow.Bits.Bit_18 = DeswizzleLow.Bits.Bit_2;
+
+      DeswizzleHigh.Bits.Byte_6 = DeswizzleHigh.Bits.Byte_4;
+      DeswizzleHigh.Bits.Bit_48 = DeswizzleHigh.Bits.Bit_32;
+      DeswizzleHigh.Bits.Bit_49 = DeswizzleHigh.Bits.Bit_33;
+      DeswizzleHigh.Bits.Bit_50 = DeswizzleHigh.Bits.Bit_34;
+    }
+
+    Offset = MCHBAR_CH0_CR_DESWIZZLE_LOW_REG +
+      (MCHBAR_CH1_CR_DESWIZZLE_LOW_REG - MCHBAR_CH0_CR_DESWIZZLE_LOW_REG) * Channel;
+    MrcWriteCR (MrcData, Offset, DeswizzleLow.Data);
+
+    Offset = MCHBAR_CH0_CR_DESWIZZLE_HIGH_REG +
+      (MCHBAR_CH1_CR_DESWIZZLE_HIGH_REG - MCHBAR_CH0_CR_DESWIZZLE_HIGH_REG) * Channel;
+    MrcWriteCR (MrcData, Offset, DeswizzleHigh.Data);
+
+    MRC_DEBUG_MSG (
+      Debug,
+      MSG_LEVEL_NOTE,
+      "Ch%d DESWIZZLE_HIGH=%08X, DESWIZZLE_LOW=%08X\n",
+      Channel,
+      DeswizzleHigh.Data,
+      DeswizzleLow.Data
+      );
+  } // for Channel
+}
+
+/**
+  Sweep both CS and CMD PI and print the feedback.
+
+  @param[in] MrcData - The MRC global data.
+
+  @retval none
+**/
+MrcStatus
+Ca2DMargins (
+  IN MrcParameters * const  MrcData,
+  U8                        Rank
+  )
+{
+  MrcInput          *Inputs;
+  MrcDebug          *Debug;
+  MrcOutput         *Outputs;
+  MrcStatus         Status;
+  U8                Channel;
+  U8                ChannelMask;
+  U8                Byte;
+  U8                CaStart = 32;
+  U8                CaStop = 127;
+  S8                CaStep = 6;
+  U8                CsStart = 0;
+  U8                CsStop = 127;
+  S8                CsStep = 8;
+  U8                CaPiCode;
+  U8                CsPiCode;
+  U32               DelayCadb;
+  U32               Offset;
+  char              PassFail;
+  DDRDATA0CH0_CR_DATATRAINFEEDBACK_STRUCT DataTrainFeedback;
+
+  Status        = mrcSuccess;
+  Inputs        = &MrcData->SysIn.Inputs;
+  Debug         = &Inputs->Debug;
+  Outputs       = &MrcData->SysOut.Outputs;
+
+  DelayCadb = 1 * HPET_1US;
+
+  ChannelMask   = 0;
+  for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+    if (MrcRankInChannelExist (MrcData, Rank, Channel)) {
+      ChannelMask |= (1 << Channel);
+    }
+  }
+
+  for (CsPiCode = CsStart; CsPiCode < CsStop; CsPiCode += CsStep) {
+    for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+      if (!MrcRankInChannelExist (MrcData, Rank, Channel)) {
+        continue;
+      }
+      //
+      // Shift the CS PI on Rank.
+      //
+      ShiftPIforCmdTraining (MrcData, Channel, MrcIterationCtl, 1 << Rank, 1, CsPiCode, 0);
+    }
+
+    for (CaPiCode = CaStart; CaPiCode < CaStop; CaPiCode += CaStep) {
+      MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%d\t%d\t", CsPiCode, CaPiCode);
+      for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+        if (!MrcRankInChannelExist (MrcData, Rank, Channel)) {
+          continue;
+        }
+        //
+        // Shift the Command PI on both CAA and CAB groups
+        //
+        ShiftPIforCmdTraining (MrcData, Channel, MrcIterationCmdN, 1 << Rank, 3, CaPiCode, 0);
+        ShiftPIforCmdTraining (MrcData, Channel, MrcIterationCmdS, 1 << Rank, 3, CaPiCode, 0);
+        ShiftPIforCmdTraining (MrcData, Channel, MrcIterationCke,  1 << Rank, 3, CaPiCode, 0);
+      }
+
+      //
+      // Perform Jedec Reset ONLY
+      //
+      MrcJedecResetLpddr3 (MrcData);
+
+      for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+        if (!MrcRankInChannelExist (MrcData, Rank, Channel)) {
+          continue;
+        }
+        //
+        // Put the current Rank in CA training mode using MRW41.
+        //
+        Status = LpddrCommandTrainingMode (MrcData, 1 << Channel, 1 << Rank, CaTrainingMode41);
+        if (Status != mrcSuccess) {
+          return Status;
+        }
+      }
+
+      //
+      // Run CADB pattern on selected channels at the same time
+      //
+      ShortRunCADB (MrcData, ChannelMask);
+      MrcWait (MrcData, DelayCadb);
+
+      //
+      // Read and process the results
+      //
+      // MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Byte Feedback\n");
+      for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+        for (Byte = 0; Byte < Outputs->SdramCount; Byte++) {
+          Offset = DDRDATA0CH0_CR_DATATRAINFEEDBACK_REG +
+            ((DDRDATA0CH1_CR_DATATRAINFEEDBACK_REG - DDRDATA0CH0_CR_DATATRAINFEEDBACK_REG) * Channel) +
+            ((DDRDATA1CH0_CR_DATATRAINFEEDBACK_REG - DDRDATA0CH0_CR_DATATRAINFEEDBACK_REG) * Byte);
+          DataTrainFeedback.Data = (MrcReadCR (MrcData, Offset) & 0xFF);  // Get only DQ bits, not DQS
+
+          //
+          // If we don't see 4 ones in the byte, then the command was not aligned properly
+          //
+          if (MrcCountBitsEqOne (DataTrainFeedback.Data) != 4) {
+            PassFail = '#';
+          } else {
+            PassFail = '.';
+          }
+          MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%c%02X\t", PassFail, DataTrainFeedback.Data);
+        }  // for Byte
+        MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\t");
+      }  // for Channel
+      MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\n");
+    }
+  }  // while not done
+
+  return Status;
+}
+
+/**
+  Sweep CMD PI up or down and find edges for all bytes.
+  Main flow:
+  1.
+  2.
+  3.
+
+  @param[in] MrcData - The MRC global data.
+
+  @retval none
+**/
+void
+EarlyCaFindEdge (
+  IN MrcParameters * const  MrcData,
+  U8                        Rank,
+  U8                        Start,
+  U8                        Stop,
+  S8                        Step,
+  U8                        Limit[MAX_CHANNEL][MAX_RANK_IN_CHANNEL][MAX_SDRAM_IN_DIMM]
+  )
+{
+  MrcInput          *Inputs;
+  MrcDebug          *Debug;
+  MrcOutput         *Outputs;
+  MrcControllerIn   *ControllerIn;
+  MrcControllerOut  *ControllerOut;
+  MrcChannelIn      *ChannelIn;
+  MrcChannelOut     *ChannelOut;
+  U8                Channel;
+  U8                ChannelMask;
+  U8                Byte;
+  U8                ByteMask;
+  U8                DramByte;
+  U8                ByteDoneMask[MAX_CHANNEL];
+  U8                PiCode;
+  U32               DelayCadb;
+  U32               Offset;
+  BOOL              Done;
+  char              *BytesHeader;
+  char              PassFail;
+  DDRDATA0CH0_CR_DATATRAINFEEDBACK_STRUCT DataTrainFeedback;
+
+  Inputs        = &MrcData->SysIn.Inputs;
+  Debug         = &Inputs->Debug;
+  Outputs       = &MrcData->SysOut.Outputs;
+  ControllerIn  = &Inputs->Controller[0];
+  ControllerOut = &Outputs->Controller[0];
+
+  DelayCadb = 1 * HPET_1US;
+
+  MrcOemMemorySet (ByteDoneMask, 0, sizeof (ByteDoneMask));
+
+  PiCode = Start;
+  Done = FALSE;
+
+  ChannelMask   = 0;
+  for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+    if (MrcRankInChannelExist (MrcData, Rank, Channel)) {
+      ChannelMask |= (1 << Channel);
+    }
+  }
+
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\t Ch0\t\t\t\t   Ch1\n");
+  BytesHeader = "0   1   2   3   4   5   6   7     ";
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "CMD PI\t %s%s\n", BytesHeader, BytesHeader);
+
+  while (!Done) {
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%d: \t", PiCode);
+    for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+      if (!MrcRankInChannelExist (MrcData, Rank, Channel)) {
+        continue;
+      }
+      //
+      // Shift the Command PI on both CAA and CAB groups
+      //
+      ShiftPIforCmdTraining (MrcData, Channel, MrcIterationCmdN, 1 << Rank, 3, PiCode, 0);
+      ShiftPIforCmdTraining (MrcData, Channel, MrcIterationCmdS, 1 << Rank, 3, PiCode, 0);
+      ShiftPIforCmdTraining (MrcData, Channel, MrcIterationCke,  1 << Rank, 3, PiCode, 0);
+    }
+
+    //
+    // Run CADB pattern on selected channels at the same time
+    //
+    ShortRunCADB (MrcData, ChannelMask);
+    MrcWait (MrcData, DelayCadb);
+
+    //
+    // Read and process the results
+    //
+    for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+      if (!MrcRankInChannelExist (MrcData, Rank, Channel)) {
+        ByteDoneMask[Channel] = 0xFF;
+        MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "                                  ");
+        continue;
+      }
+      if (ByteDoneMask[Channel] == 0xFF) { // All bytes failed on this channel, no need to sweep anymore
+        MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "                                  ");
+        continue;
+      }
+      ChannelIn = &ControllerIn->Channel[Channel];
+      ChannelOut = &ControllerOut->Channel[Channel];
+      for (Byte = 0; Byte < Outputs->SdramCount; Byte++) {
+        ByteMask = (1 << Byte);
+        DramByte = ChannelIn->DqsMapCpu2Dram[Byte];
+        if (ChannelOut->Dimm[dDIMM0].SdramWidth == 32) {
+          if ((DramByte & 0x02) != 0) {
+            //
+            // Ignore upper 16 bits on x32 devices in MRW41 feedback - DRAM bytes 2, 3, 6 and 7
+            //
+            ByteDoneMask[Channel] |= ByteMask;
+            MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "    ");
+            continue;
+          }
+        }
+        Offset = DDRDATA0CH0_CR_DATATRAINFEEDBACK_REG +
+          ((DDRDATA0CH1_CR_DATATRAINFEEDBACK_REG - DDRDATA0CH0_CR_DATATRAINFEEDBACK_REG) * Channel) +
+          ((DDRDATA1CH0_CR_DATATRAINFEEDBACK_REG - DDRDATA0CH0_CR_DATATRAINFEEDBACK_REG) * Byte);
+        DataTrainFeedback.Data = (MrcReadCR (MrcData, Offset) & 0xFF);  // Get only DQ bits, not DQS
+
+        PassFail = '#';
+        if ((ByteDoneMask[Channel] & ByteMask) == 0) {
+          //
+          // If we don't see 4 ones in the byte, then the command was not aligned properly
+          //
+          if (MrcCountBitsEqOne (DataTrainFeedback.Data) != 4) {
+            Limit[Channel][Rank][Byte] = PiCode;
+            ByteDoneMask[Channel] |= ByteMask;
+          } else {
+            PassFail = '.';
+          }
+        }
+        MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%c%02X ", PassFail, DataTrainFeedback.Data);
+      }  // for Byte
+      MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "  ");
+    }  // for Channel
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\n");
+    if ((ByteDoneMask[0] == 0xFF) && (ByteDoneMask[1] == 0xFF)) {
+      // Found the limit on all bytes on both channels - no need to sweep Pi any longer
+      break;
+    }
+
+    PiCode += Step;
+    if (Step > 0) {
+      // Sweep up
+      Done = (PiCode > Stop);
+    } else {
+      // Sweep down
+      Done = (((S8) PiCode) < Stop);
+    }
+  }  // while not done
+}
+
+/**
+  Process the results of the early LPDDR3 CMD training and find the best PI settings for CmdS/CmdN/Cke.
+  Flow:
+   1. Find the worst case Right and Left limits for each channel
+   2. Find the Center for each channel
+
+  @param[in]  MrcData     - The MRC global data.
+  @param[in]  LeftLimit   - array of left edge values per channel, rank and CPU byte
+  @param[in]  RightLimit  - array of right edge values per channel, rank and CPU byte
+  @param[out] BestCs      - array of best CMD PI settings, per channel
+
+  @retval mrcSuccess if succeeded
+**/
+MrcStatus
+FindBestCmdPi (
+  IN  MrcParameters * const MrcData,
+  IN  U8                    LeftLimit[MAX_CHANNEL][MAX_RANK_IN_CHANNEL][MAX_SDRAM_IN_DIMM],
+  IN  U8                    RightLimit[MAX_CHANNEL][MAX_RANK_IN_CHANNEL][MAX_SDRAM_IN_DIMM],
+  OUT U8                    BestCmd[MAX_CHANNEL][2]    // per Channel and per group (CAA and CAB)
+  )
+{
+  MrcInput          *Inputs;
+  MrcDebug          *Debug;
+  MrcOutput         *Outputs;
+  MrcStatus         Status;
+  MrcChannelIn      *ChannelIn;
+  MrcControllerIn   *ControllerIn;
+  U8                Channel;
+  U8                Rank;
+  U8                Byte;
+  U8                CaGroup;
+  U8                CmdLeftLimit[MAX_CHANNEL][2];  // Per ch and group
+  U8                CmdRightLimit[MAX_CHANNEL][2]; // Per ch and group
+
+  Inputs        = &MrcData->SysIn.Inputs;
+  Debug         = &Inputs->Debug;
+  Outputs       = &MrcData->SysOut.Outputs;
+  ControllerIn  = &Inputs->Controller[0];
+
+  Status = mrcSuccess;
+
+  MrcOemMemorySet ((U8 *) CmdRightLimit, 127, sizeof (CmdRightLimit));
+  MrcOemMemorySet ((U8 *) CmdLeftLimit, 0, sizeof (CmdLeftLimit));
+
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Finding best CMD PIs:\n");
+  for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+    if (!MrcChannelExist (Outputs, Channel)) {
+      continue;
+    }
+    ChannelIn = &ControllerIn->Channel[Channel];
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Channel: %d\t\tLeft\tRight\tCenter\n", Channel);
+    for (Rank = 0; Rank < MAX_RANK_IN_CHANNEL; Rank++) {
+      if (!MrcRankInChannelExist (MrcData, Rank, Channel)) {
+        continue;
+      }
+      //
+      // Find the worst case Right and Left limits for all ranks, for bytes from the particular CA group
+      //
+      for (Byte = 0; Byte < Outputs->SdramCount; Byte++) {
+        //
+        // CmdS CAA goes to Bytes[3:0], CmdS CAB goes to Byte[7:4]
+        //
+        if ((1 << Byte) & ChannelIn->DQByteMap[MrcIterationCmdS][0]) {
+          CaGroup = 0;
+        } else {
+          CaGroup = 1;
+        }
+        CmdRightLimit[Channel][CaGroup] = MIN (CmdRightLimit[Channel][CaGroup], RightLimit[Channel][Rank][Byte]);
+        CmdLeftLimit[Channel][CaGroup]  = MAX (CmdLeftLimit[Channel][CaGroup], LeftLimit[Channel][Rank][Byte]);
+      }
+    } // for Rank
+
+    //
+    // Find the Center for each group, worst case of all ranks
+    //
+    BestCmd[Channel][0] = (CmdRightLimit[Channel][0] + CmdLeftLimit[Channel][0]) / 2;
+    BestCmd[Channel][1] = (CmdRightLimit[Channel][1] + CmdLeftLimit[Channel][1]) / 2;
+
+    MRC_DEBUG_MSG (
+      Debug,
+      MSG_LEVEL_NOTE,
+      "CA%c\t\t\t%d\t%d\t%d\n",
+      'A',
+      CmdLeftLimit[Channel][0],
+      CmdRightLimit[Channel][0],
+      BestCmd[Channel][0]
+      );
+
+    MRC_DEBUG_MSG (
+      Debug,
+      MSG_LEVEL_NOTE,
+      "CA%c\t\t\t%d\t%d\t%d\n",
+      'B',
+      CmdLeftLimit[Channel][1],
+      CmdRightLimit[Channel][1],
+      BestCmd[Channel][1]
+      );
+  } // for Channel
+
+  return Status;
+}
+
+/**
+  Update DqMapCpu2Dram array
+
+  @param[in] MrcData  - The MRC global data.
+  @param[in] Channel  - the channel to work on
+  @param[in] Feedback - array of DATATRAINFEEDBACK values for all 8 bytes
+  @param[in] Bit      - The DQ bit the should be set in each DRAM byte
+
+  @retval none
+**/
+void
+FillCA2DQMapResult (
+  IN OUT MrcParameters * const  MrcData,
+  IN const U8                   Channel,
+  IN const U8                   Feedback[8],
+  IN const U8                   Bit
+  )
+{
+  MrcInput          *Inputs;
+  const MrcDebug    *Debug;
+  MrcOutput         *Outputs;
+  MrcChannelOut     *ChannelOut;
+  MrcControllerOut  *ControllerOut;
+  MrcControllerIn   *ControllerIn;
+  MrcChannelIn      *ChannelIn;
+  U8                Byte;
+  U8                Temp;
+  U8                CpuBit;
+  S8                BitNumber;
+  BOOL              BitFound;
+
+  Inputs        = &MrcData->SysIn.Inputs;
+  Debug         = &Inputs->Debug;
+  Outputs       = &MrcData->SysOut.Outputs;
+  ControllerOut = &Outputs->Controller[0];
+  ControllerIn  = &Inputs->Controller[0];
+
+  ChannelOut = &ControllerOut->Channel[Channel];
+  ChannelIn  = &ControllerIn->Channel[Channel];
+
+  BitNumber = -1;
+
+  //
+  // Loop on CPU bytes
+  //
+  for (Byte = 0; Byte < Outputs->SdramCount; Byte++) {
+    if (Feedback[Byte] == 0) {
+      continue;
+    }
+    Temp = Feedback[Byte];
+    BitNumber = 0;
+    CpuBit    = 0;
+    BitFound  = FALSE;
+      while (Temp > 0) {
+        if (Temp & 1) {
+          if (!BitFound) {
+              CpuBit = BitNumber;
+              BitFound = TRUE;
+          } else {
+            MRC_DEBUG_MSG (
+              Debug,
+              MSG_LEVEL_NOTE,
+              "Ch%d: ERROR: More than one DQ pin toggled while looking for DQ%d in Byte%d, Feedback=0x%X\n",
+              Channel,
+              Bit,
+              Byte,
+              Feedback[Byte]
+              );
+            break;
+          }
+        }
+        Temp >>= 1;
+        BitNumber++;
+      }
+      ChannelIn->DqMapCpu2Dram[Byte][CpuBit] = ChannelIn->DqsMapCpu2Dram[Byte] * 8 + Bit;
+  } // for Byte
+}
+
+/**
+  Rotate a given number left by a specified number of bits.
+
+  @param[in] Value      - The input value
+  @param[in] BitLength  - How many bits to rotate in the input value.
+  @param[in] RotateBy   - Number of bits to rotate by.
+
+  @retval The rotated number
+**/
+U32
+RotateLeft (
+  IN const U32 Value,
+  IN const U8  BitLength, // should be >1 and <32, tested for 16
+  IN const U8  RotateBy
+  )
+{
+  U32 Mask;
+  U32 Lsb;
+  U32 Result;
+  U8  i;
+
+  Result = Value;
+  Mask = (1 << BitLength) - 1;
+
+  for (i = 0; i < RotateBy; i++) {
+    Lsb = 1 & (((Result) & (1 << (BitLength - 1))) >> (BitLength-1)); // The MSB value needs to move to LSB
+    Result = (Mask & (Result << 1)) | Lsb;                            // Shift Left once and add the new LSB
+  }
+
+  return Result;
+}
+
+/**
+  Calculate 3 Pattern Buffers values for the given CADB sequence.
+
+  @param[in] MrcData             - The MRC global data.
+  @param[in] CadbSequence        - CADB line numbers in the order of transmission.
+                                   Example: 0,1,0,0,...0 for DQ mapping, 0,0,2,1,1,0,0,...0 for CS training
+  @param[out] CadbPatternBuffers - Array of 3 Pattern Buffer values
+
+  @retval none
+**/
+void
+CalculateCadbPB (
+  IN MrcParameters * const  MrcData,
+  IN const U8               CadbSequence[MRC_CADB_PB_LENGTH],
+  OUT U32                   CadbPatternBuffers[3]
+  )
+{
+  MrcInput  *Inputs;
+  MrcDebug  *Debug;
+  U8        i;
+  U8        j;
+
+  Inputs = &MrcData->SysIn.Inputs;
+  Debug  = &Inputs->Debug;
+
+  MrcOemMemorySet ((U8 *) CadbPatternBuffers, 0, 3 * sizeof (CadbPatternBuffers[0]));
+
+  for (i = 0; i < MRC_CADB_PB_LENGTH; i++) {
+    for (j = 0; j < 3; j++) {
+      CadbPatternBuffers[j] = RotateLeft (CadbPatternBuffers[j], MRC_CADB_PB_LENGTH, 1) |
+                                ((CadbSequence[i] & (1 << j)) >> j);
+    }
+  }
+
+  for (j = 0; j < 3; j++) {
+    CadbPatternBuffers[j] = RotateLeft (CadbPatternBuffers[j], MRC_CADB_PB_LENGTH, 1);
+  }
+}
+
+/**
+  Map CA to DQ Pins for CA training and MR4 bit swizzling settings for LPDDR.
+  Main flow:
+  Repeat for each of the 8 bits per DQ byte (total 8 iterations for both channels, for rank0 only):
+    Transmit single CA phase expected to appear on a known DQ pin
+     One CA phase per byte, 2 different CA phases for Even and Odd bytes in parallel
+    Locate the single DQ in each byte based on DATATRAINFEEDBACK
+     Report error if more than one DQ pin toggles
+     Report error if no active DQ pin found
+     Ignore Byte2 and Byte3 for x32 devices if they don't return feedback (only DQ[15:0] must return feedback per JEDEC)
+    Update the DQ mapping data structure.
+
+  Assumption: runs on stable and correct CLK, CS and CA PI settings (either guaranteed by design or pre-trained)
+
+  @param[in] MrcData - The MRC global data.
+
+  @retval mrcSuccess if succeeded
+**/
+MrcStatus
+MapCA2DQPins (
+  IN MrcParameters * const MrcData
+)
+{
+  MrcInput                                    *Inputs;
+  MrcDebug                                    *Debug;
+  MrcOutput                                   *Outputs;
+  MrcControllerIn                             *ControllerIn;
+  MrcControllerOut                            *ControllerOut;
+  MrcChannelIn                                *ChannelIn;
+  MrcChannelOut                               *ChannelOut;
+  MrcStatus                                   Status;
+  U8                                          Channel;
+  U8                                          Rank;
+  U8                                          Byte;
+  U8                                          DramByte;
+  U8                                          Bit;
+  DDRDATACH0_CR_DDRCRDATACONTROL0_STRUCT      DdrCrDataControl0;
+  DDRDATA0CH0_CR_DDRCRDATACONTROL2_STRUCT     DdrCrDataControl2;
+  U32                                         Offset;
+  U32                                         CaPattern;
+  U8                                          Feedback[8];
+  CADB_LINE CadbLinesDqMapping[] = {
+    { 0x000, 0x000, 0 },
+    { 0x001, 0x000, 1 }
+  };
+  U32     CadbPatternBuffers[3];
+  U8      CadbSequence[MRC_CADB_PB_LENGTH];
+#ifdef MRC_DEBUG_PRINT
+  U8                                          DramBit;
+  U8                                          i;
+#endif
+
+  Status = mrcSuccess;
+  Inputs        = &MrcData->SysIn.Inputs;
+  Debug         = &Inputs->Debug;
+  Outputs       = &MrcData->SysOut.Outputs;
+  ControllerIn  = &Inputs->Controller[0];
+  ControllerOut = &Outputs->Controller[0];
+  Rank = 0;
+
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "MapCA2DQPins started\n");
+  if (ControllerOut->Channel[0].Dimm[dDIMM0].SdramWidth == 32) {
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "x32 DRAM devices - skipping Bytes 2,3 in each DRAM!\n");
+  }
+
+  MrcOemMemorySet (CadbSequence, 0, sizeof (CadbSequence));
+  CadbSequence[1] = 1; // The 2nd PB entry is the 2nd CADB line with active CS. The rest are 0.
+
+  //
+  // Calculate the Pattern Buffers values for the given CADB sequence
+  //
+  CalculateCadbPB (MrcData, CadbSequence, CadbPatternBuffers);
+
+  //
+  // Enable the following bits because we will use DATATRAINFEEDBACK to read back CA values on DQ pins:
+  //  DataControl0.SenseampTrainingMode and ForceOdtOn
+  //  DataControl2.ForceRxOn and ForceBiasOn
+  //
+  for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+    if (!MrcRankInChannelExist (MrcData, 0, Channel)) {
+      continue;
+    }
+    ChannelOut = &ControllerOut->Channel[Channel];
+    MrcOemMemorySet (
+      (U8 *) (ControllerIn->Channel[Channel].DqMapCpu2Dram),
+      0xFF,
+      sizeof (ControllerIn->Channel[0].DqMapCpu2Dram)
+      );
+
+    for (Byte = 0; Byte < Outputs->SdramCount; Byte++) {
+      DdrCrDataControl2.Data = ChannelOut->DqControl2[Byte].Data;
+      DdrCrDataControl2.Bits.ForceBiasOn = 1;
+      DdrCrDataControl2.Bits.ForceRxOn   = 1;
+      Offset = DDRDATA0CH0_CR_DDRCRDATACONTROL2_REG +
+        ((DDRDATA0CH1_CR_DDRCRDATACONTROL2_REG - DDRDATA0CH0_CR_DDRCRDATACONTROL2_REG) * Channel) +
+        ((DDRDATA1CH0_CR_DDRCRDATACONTROL2_REG - DDRDATA0CH0_CR_DDRCRDATACONTROL2_REG) * Byte);
+      MrcWriteCR (MrcData, Offset, DdrCrDataControl2.Data);
+    }
+    DdrCrDataControl0.Data = ChannelOut->DqControl0.Data;
+    DdrCrDataControl0.Bits.ForceOdtOn           = 1;
+    DdrCrDataControl0.Bits.SenseampTrainingMode = 1;
+    Offset = DDRDATACH0_CR_DDRCRDATACONTROL0_REG +
+      ((DDRDATACH1_CR_DDRCRDATACONTROL0_REG - DDRDATACH0_CR_DDRCRDATACONTROL0_REG) * Channel);
+    MrcWriteCrMulticast (MrcData, Offset, DdrCrDataControl0.Data);
+
+    //
+    // Put Rank 0 in CA training mode using MRW41.
+    //
+    Status = LpddrCommandTrainingMode (MrcData, 1 << Channel, 1 << Rank, CaTrainingMode41);
+    if (Status != mrcSuccess) {
+      return Status;
+    }
+  }
+
+  for (Bit = 0; Bit < MAX_BITS; Bit++) {
+    //
+    // Create CA patterns for high and low phases,
+    // such that only one DQ bit should toggle on each phase, per DRAM byte
+    //
+    CaPattern = (1 << (Bit / 2)) | (1 << (Bit / 2 + 5));
+    CadbLinesDqMapping[1].CaHigh = ((Bit % 2) == 0) ? CaPattern : 0;
+    CadbLinesDqMapping[1].CaLow  = ((Bit % 2) == 1) ? CaPattern : 0;
+
+#ifdef MRC_DEBUG_PRINT
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\nRunning Bit %d\n", Bit);
+    for (i = 0; i < sizeof (CadbLinesDqMapping) / sizeof (CadbLinesDqMapping[0]); i++) {
+      MRC_DEBUG_MSG (
+        Debug,
+        MSG_LEVEL_NOTE,
+        "\tCADB[%d] CaHigh=0x%03X\tCaLow=0x%03X\tCS=0x%03X\n",
+        i,
+        CadbLinesDqMapping[i].CaHigh,
+        CadbLinesDqMapping[i].CaLow,
+        CadbLinesDqMapping[i].ChipSelect
+        );
+    }
+#endif //MRC_DEBUG_PRINT
+
+    for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+      if (!MrcRankInChannelExist (MrcData, 0, Channel)) {
+        continue;
+      }
+
+      SetupCaTrainingCadb (
+        MrcData,
+        Channel,
+        Rank,
+        CadbLinesDqMapping,
+        sizeof (CadbLinesDqMapping) / sizeof (CadbLinesDqMapping[0]),
+        CadbPatternBuffers[0],
+        CadbPatternBuffers[1],
+        CadbPatternBuffers[2]
+        );
+    }
+
+    //
+    // Run CADB pattern on both channels at the same time
+    //
+    ShortRunCADB (MrcData, 0x3);
+
+    //
+    // Get Results for all ch/bytes
+    //
+    for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+      if (!MrcRankInChannelExist (MrcData, 0, Channel)) {
+        continue;
+      }
+      ChannelOut = &ControllerOut->Channel[Channel];
+      ChannelIn  = &ControllerIn->Channel[Channel];
+
+      for (Byte = 0; Byte < Outputs->SdramCount; Byte++) {
+        DramByte = ChannelIn->DqsMapCpu2Dram[Byte];
+        if (ChannelOut->Dimm[dDIMM0].SdramWidth == 32) {
+          if ((DramByte & 0x02) != 0) {
+            //
+            // Ignore upper 16 bits (in DRAM terms) on x32 devices in MRW41 feedback - DRAM bytes 2, 3, 6 and 7
+            //
+            Feedback[Byte] = 0;
+            continue;
+          }
+        }
+        Offset = DDRDATA0CH0_CR_DATATRAINFEEDBACK_REG +
+          ((DDRDATA0CH1_CR_DATATRAINFEEDBACK_REG - DDRDATA0CH0_CR_DATATRAINFEEDBACK_REG) * Channel) +
+          ((DDRDATA1CH0_CR_DATATRAINFEEDBACK_REG - DDRDATA0CH0_CR_DATATRAINFEEDBACK_REG) * Byte);
+        Feedback[Byte] = (U8) (MrcReadCR (MrcData, Offset) & 0xFF);
+        MRC_DEBUG_MSG (
+          Debug,
+          MSG_LEVEL_NOTE,
+          "\t   Channel %d CPU Byte %d DRAM Byte %d => Feedback = %02X - %s feedback\n",
+          Channel,
+          Byte,
+          DramByte,
+          Feedback[Byte],
+          (MrcCountBitsEqOne (Feedback[Byte]) == 1) ? "Good" : "Bad"
+          );
+      } // for Byte
+      //
+      // Store results in ChannelIn->DqMapCpu2Dram
+      //
+      FillCA2DQMapResult (MrcData, Channel, Feedback, Bit);
+    } // for Channel
+  }  // for Bit
+
+  //
+  // Exit CA training mode on rank 0 on both channels
+  //
+  for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+    if (!MrcRankInChannelExist (MrcData, 0, Channel)) {
+      continue;
+    }
+    Status = LpddrCommandTrainingMode (MrcData, 1 << Channel, 1 << Rank, CaTrainingMode42);
+    if (Status != mrcSuccess) {
+      return Status;
+    }
+  }
+
+#ifdef MRC_DEBUG_PRINT
+  for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+    if (!MrcRankInChannelExist (MrcData, 0, Channel)) {
+      continue;
+    }
+    ChannelOut = &ControllerOut->Channel[Channel];
+    ChannelIn  = &ControllerIn->Channel[Channel];
+    MRC_DEBUG_MSG (
+      Debug,
+      MSG_LEVEL_NOTE,
+      "\nMapCA2DQPins Results for Ch%d (\"-1\" for skipped Bytes, DRAM DQ pins offsets):\n%s",
+      Channel,
+      "CPU Bit: \t[0]\t[1]\t[2]\t[3]\t[4]\t[5]\t[6]\t[7]\n"
+      );
+    for (Byte = 0; Byte < Outputs->SdramCount; Byte++) {
+      MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "CPU Byte%d:", Byte);
+      for (Bit = 0; Bit <  MAX_BITS; Bit++) {
+        DramBit = ChannelIn->DqMapCpu2Dram[Byte][Bit];
+        MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\t%d", (DramBit == 255) ? -1: DramBit);
+      }
+      MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\n");
+    }
+  }
+#endif //MRC_DEBUG_PRINT
+
+  return Status;
+}
+
+/**
+  Sweep the given PI up or down and find the edge.
+
+  @param[in]  MrcData     - The MRC global data.
+  @param[in]  Iteration   - Determines which PI to shift
+  @param[in]  ChannelMask - Valid Channel bit mask
+  @param[in]  RankMask    - Valid Rank bit mask
+  @param[in]  Stop        - End of the PI range
+  @param[in]  Step        - PI step for the sweep
+  @param[out] Limit       - array of edge values (per channel), filled by this function
+  @param[in]  DebugPrint  - Print debug messages or not
+
+  @retval none
+**/
+void
+CaFindEdge (
+  IN  MrcParameters * const  MrcData,
+  IN  U8                     Iteration,
+  IN  U8                     ChannelMask,
+  IN  U8                     RankMask,
+  IN  S16                    Stop,
+  IN  S16                    Step,
+  OUT U8                     Limit[MAX_CHANNEL],
+  IN  BOOL                   DebugPrint
+  )
+{
+  MrcInput          *Inputs;
+  MrcDebug          *Debug;
+  MrcOutput         *Outputs;
+  U8                Channel;
+  U8                ChannelBit;
+  U8                ChError;
+  U8                DumArr[7];
+  S16               PiOffset;
+  BOOL              Pass;
+  BOOL              Done;
+  BOOL              ChannelDone[MAX_CHANNEL];
+
+  Inputs  = &MrcData->SysIn.Inputs;
+  Debug   = &Inputs->Debug;
+  Outputs = &MrcData->SysOut.Outputs;
+
+  PiOffset = 0;
+  Done = FALSE;
+  ChannelDone[0] = ChannelDone[1] = FALSE;
+  MrcOemMemorySet (DumArr, 1, sizeof (DumArr));
+
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, (DebugPrint) ? "\t0 1\n" : "");
+
+  while (!Done) {
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, (DebugPrint) ? "%d:\t" : "", PiOffset);
+    //
+    // Update Timing
+    //
+    for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+      if ((1 << Channel) & ChannelMask) {
+        if (!ChannelDone[Channel]) {
+          ShiftPIforCmdTraining (MrcData, Channel, Iteration, RankMask, 3, PiOffset, 0);
+        }
+      }
+    }
+    //
+    // Reset DDR after changing the CLK PI
+    //
+    MrcResetSequence (MrcData);
+
+    //
+    // Run CPGC test on both channels
+    //
+    ChError = RunIOTest (MrcData, ChannelMask, Outputs->DQPat, DumArr, 1, 0);
+
+    for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+      ChannelBit = (1 << Channel);
+      if (((ChannelBit & ChannelMask) == 0) || (ChannelDone[Channel])) {
+        MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, (DebugPrint && (Channel == 0)) ? "  " : "");
+        continue;
+      }
+
+      Pass = !(ChError & ChannelBit);
+
+      MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, (DebugPrint) ? (Pass ? ". " : "# ") : "");
+
+      if (Pass) {
+        Limit[Channel] = (U8) (ABS (PiOffset));
+      } else {
+        ChannelDone[Channel] = TRUE;
+      }
+    }
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, (DebugPrint) ? "\n" : "");
+
+    PiOffset += Step;
+    if (Step > 0) {
+      // Sweep up
+      Done = (PiOffset > Stop);
+    } else {
+      // Sweep down
+      Done = (PiOffset < Stop);
+    }
+
+    if (ChannelDone[0] && ChannelDone[1]) {
+      // Found the limit on both channels - no need to sweep PI any longer
+      Done = TRUE;
+    }
+  }  // while not done
+}
+
+/**
+@brief
+  Sweep right and left from the current point to find the margins.
+
+  @param[in, out] MrcData     - Include all MRC global data.
+  @param[in]      Iteration   - Determines which PI to shift
+  @param[in]      ChannelMask - Valid Channel bit mask
+  @param[in]      RankMask    - Valid Rank bit mask
+  @param[in]      DebugPrint  - Print debug messages or not
+
+  @retval MrcStatus -  If it succeeds return mrcSuccess
+**/
+void
+CmdLinearFindEdgesLpddr (
+  IN OUT MrcParameters *const MrcData,
+  IN     U8                   Iteration,
+  IN     U8                   ChannelMask,
+  IN     U8                   RankMask,
+  IN     BOOL                 DebugPrint
+  )
+{
+  const MrcDebug    *Debug;
+  MrcOutput         *Outputs;
+  U8                Channel;
+  U8                Rank;
+  S16               PiLow;
+  S16               PiHigh;
+  S16               PiStep;
+  U8                RightLimit[MAX_CHANNEL];
+  U8                LeftLimit[MAX_CHANNEL];
+
+  Debug         = &MrcData->SysIn.Inputs.Debug;
+  Outputs       = &MrcData->SysOut.Outputs;
+
+  //
+  // We are going to sweep clock 32 PI ticks to the left and to the right
+  //
+  PiLow   = -32;
+  PiHigh  = 32;
+
+  PiStep = 1;
+
+  //
+  // Initialize to zero margin
+  //
+  MrcOemMemorySet ((U8 *) RightLimit, 0, sizeof (RightLimit));
+  MrcOemMemorySet ((U8 *) LeftLimit, 0, sizeof (LeftLimit));
+
+  //
+  // Find right and left margins
+  //
+  CaFindEdge (MrcData, Iteration, ChannelMask, RankMask, PiHigh, PiStep, RightLimit, DebugPrint);
+  CaFindEdge (MrcData, Iteration, ChannelMask, RankMask, PiLow, -PiStep, LeftLimit, DebugPrint);
+
+  for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+    if ((1 << Channel) & ChannelMask) {
+      //
+      // Save margins for RMT
+      //
+      for (Rank = 0; Rank < MAX_RANK_IN_CHANNEL; Rank++) {
+        if ((1 << Rank) & RankMask) {
+          Outputs->MarginResult[LastCmdT][Rank][Channel][0][0] = 10 * LeftLimit[Channel];
+          Outputs->MarginResult[LastCmdT][Rank][Channel][0][1] = 10 * RightLimit[Channel];
+        }
+      }
+    }
+  }
+}
+
+/**
+  Early CMD / CLK training for LPDDR.
+
+  @param[in] MrcData - The MRC global data.
+
+  @retval mrcSuccess if succeeded
+**/
+MrcStatus
+EarlyCaTraining (
+  IN MrcParameters * const MrcData
+  )
+{
+  MrcInput                                    *Inputs;
+  MrcDebug                                    *Debug;
+  MrcOutput                                   *Outputs;
+  MrcControllerIn                             *ControllerIn;
+  MrcControllerOut                            *ControllerOut;
+  MrcChannelIn                                *ChannelIn;
+  MrcChannelOut                               *ChannelOut;
+  MrcStatus                                   Status;
+  U8                                          Channel;
+  U8                                          Rank;
+  U8                                          RankBit;
+  U8                                          Byte;
+  U8                                          DramByte;
+  U8                                          RankMask;
+  U32                                         Offset;
+  U8                                          PiLow;
+  U8                                          PiHigh;
+  U8                                          PiMiddle;
+  U8                                          PiStep;
+  U8                                          RightLimit[MAX_CHANNEL][MAX_RANK_IN_CHANNEL][MAX_SDRAM_IN_DIMM];
+  U8                                          LeftLimit[MAX_CHANNEL][MAX_RANK_IN_CHANNEL][MAX_SDRAM_IN_DIMM];
+  U8                                          BestCmd[MAX_CHANNEL][2]; // per Channel and per group (CAA and CAB)
+  DDRDATACH0_CR_DDRCRDATACONTROL0_STRUCT      DdrCrDataControl0;
+  DDRDATA0CH0_CR_DDRCRDATACONTROL2_STRUCT     DdrCrDataControl2;
+
+  Inputs        = &MrcData->SysIn.Inputs;
+  Debug         = &Inputs->Debug;
+  Outputs       = &MrcData->SysOut.Outputs;
+  ControllerIn  = &Inputs->Controller[0];
+  ControllerOut = &Outputs->Controller[0];
+
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "EarlyCaTraining started\n");
+
+  Status = mrcSuccess;
+  RankMask  = Outputs->ValidRankMask;
+
+  PiLow     = 0;
+  PiHigh    = 127;
+  PiMiddle  = 96;
+  PiStep = 2;
+
+  MrcOemMemorySet ((U8 *) RightLimit, PiHigh, sizeof (RightLimit));
+  MrcOemMemorySet ((U8 *) LeftLimit, PiLow, sizeof (LeftLimit));
+
+  //
+  // Enable the following bits because we will use DATATRAINFEEDBACK to read back CA values on DQ pins:
+  //  DataControl0.SenseampTrainingMode and ForceOdtOn
+  //  DataControl2.ForceRxOn and ForceBiasOn
+  //
+  for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+    if (!MrcChannelExist (Outputs, Channel)) {
+      continue;
+    }
+    ChannelOut = &ControllerOut->Channel[Channel];
+    for (Byte = 0; Byte < Outputs->SdramCount; Byte++) {
+      DdrCrDataControl2.Data = ChannelOut->DqControl2[Byte].Data;
+      DdrCrDataControl2.Bits.ForceBiasOn = 1;
+      DdrCrDataControl2.Bits.ForceRxOn   = 1;
+      Offset = DDRDATA0CH0_CR_DDRCRDATACONTROL2_REG +
+        ((DDRDATA0CH1_CR_DDRCRDATACONTROL2_REG - DDRDATA0CH0_CR_DDRCRDATACONTROL2_REG) * Channel) +
+        ((DDRDATA1CH0_CR_DDRCRDATACONTROL2_REG - DDRDATA0CH0_CR_DDRCRDATACONTROL2_REG) * Byte);
+      MrcWriteCR (MrcData, Offset, DdrCrDataControl2.Data);
+    }
+    DdrCrDataControl0.Data = ChannelOut->DqControl0.Data;
+    DdrCrDataControl0.Bits.ForceOdtOn           = 1;
+    DdrCrDataControl0.Bits.SenseampTrainingMode = 1;
+    Offset = DDRDATACH0_CR_DDRCRDATACONTROL0_REG +
+      ((DDRDATACH1_CR_DDRCRDATACONTROL0_REG - DDRDATACH0_CR_DDRCRDATACONTROL0_REG) * Channel);
+    MrcWriteCrMulticast (MrcData, Offset, DdrCrDataControl0.Data);
+  }
+
+  for (Rank = 0; Rank < MAX_RANK_IN_CHANNEL; Rank++) {  // @todo Do we have to do this per rank, or rank 0 is enough ?
+    RankBit = 1 << Rank;
+    if ((RankBit & RankMask) == 0) {
+      continue;
+    }
+
+    for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+      if (!MrcRankInChannelExist (MrcData, Rank, Channel)) {
+        continue;
+      }
+
+      //
+      // Put the current Rank in CA training mode using MRW41.
+      //
+      Status = LpddrCommandTrainingMode (MrcData, 1 << Channel, RankBit, CaTrainingMode41);
+      if (Status != mrcSuccess) {
+        return Status;
+      }
+
+      SetupCaTrainingCadb (
+        MrcData,
+        Channel,
+        Rank,
+        CadbLinesCs,
+        sizeof (CadbLinesCs) / sizeof (CadbLinesCs[0]),
+        0x3000,
+        0x4000,
+        0x0000
+        );
+    }  // for Channel
+
+    //
+    // Sweep CMD PI up and down from the middle, on both channels at the same time
+    //
+//    Ca2DMargins (MrcData, Rank);  // This is used for test
+    EarlyCaFindEdge (MrcData, Rank, PiMiddle, PiHigh, PiStep, RightLimit);
+    EarlyCaFindEdge (MrcData, Rank, PiMiddle, PiLow, -PiStep, LeftLimit);
+
+    for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+      if (!MrcRankInChannelExist (MrcData, Rank, Channel)) {
+        continue;
+      }
+      ChannelIn  = &ControllerIn->Channel[Channel];
+      ChannelOut = &ControllerOut->Channel[Channel];
+      MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "CA training data Ch%d Rank%d\nCPU Byte\tLeft\tRight\n", Channel, Rank);
+      for (Byte = 0; Byte < Outputs->SdramCount; Byte++) {
+        DramByte = ChannelIn->DqsMapCpu2Dram[Byte];
+        if (ChannelOut->Dimm[dDIMM0].SdramWidth == 32) {
+          if ((DramByte & 0x02) != 0) {
+            //
+            // Ignore upper 16 bits on x32 devices in MRW41 feedback - DRAM bytes 2, 3, 6 and 7
+            //
+            continue;
+          }
+        }
+        MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%d\t\t%d\t%d\n",
+          Byte, LeftLimit[Channel][Rank][Byte], RightLimit[Channel][Rank][Byte]);
+      }
+
+      //
+      // Put the CMD PI back to middle for MRW42 command
+      //
+      ShiftPIforCmdTraining (MrcData, Channel, MrcIterationCmdS, RankBit,        3, PiMiddle, 1);
+      ShiftPIforCmdTraining (MrcData, Channel, MrcIterationCke,  RankBit, (1 << 0), PiMiddle, 1);
+      ShiftPIforCmdTraining (MrcData, Channel, MrcIterationCmdN, RankBit, (1 << 1), PiMiddle, 1);
+
+      //
+      // Exit CA training mode on the current rank
+      //
+      Status = LpddrCommandTrainingMode (MrcData, 1 << Channel, RankBit, CaTrainingMode42);
+      if (Status != mrcSuccess) {
+        return Status;
+      }
+    } // for Channel
+  }  // for Rank
+
+  //
+  // Restore original DataControl0 and DataControl2 values
+  //
+  for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+    if (!MrcChannelExist (Outputs, Channel)) {
+      continue;
+    }
+    ChannelOut = &ControllerOut->Channel[Channel];
+    Offset = DDRDATACH0_CR_DDRCRDATACONTROL0_REG +
+      ((DDRDATACH1_CR_DDRCRDATACONTROL0_REG - DDRDATACH0_CR_DDRCRDATACONTROL0_REG) * Channel);
+    MrcWriteCrMulticast (MrcData, Offset, ChannelOut->DqControl0.Data);
+
+    for (Byte = 0; Byte < Outputs->SdramCount; Byte++) {
+      Offset = DDRDATA0CH0_CR_DDRCRDATACONTROL2_REG +
+        ((DDRDATA0CH1_CR_DDRCRDATACONTROL2_REG - DDRDATA0CH0_CR_DDRCRDATACONTROL2_REG) * Channel) +
+        ((DDRDATA1CH0_CR_DDRCRDATACONTROL2_REG - DDRDATA0CH0_CR_DDRCRDATACONTROL2_REG) * Byte);
+      MrcWriteCR (MrcData, Offset, ChannelOut->DqControl2[Byte].Data);
+    }
+  }
+
+  //
+  // Select optimal CMD timings for both channels
+  //
+  FindBestCmdPi (MrcData, LeftLimit, RightLimit, BestCmd);
+
+  //
+  // Apply the new CmdN, CmdS and CKE command PI settings
+  //
+  for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+    if (!MrcChannelExist (Outputs, Channel)) {
+      continue;
+    }
+    ChannelOut = &ControllerOut->Channel[Channel];
+
+    //
+    // CAA is controlled by CMDS.CmdPi0Code and CKE.CmdPi0Code
+    //
+    ShiftPIforCmdTraining (MrcData, Channel, MrcIterationCmdS, RankMask, (1 << 0), BestCmd[Channel][0], 1);
+    ShiftPIforCmdTraining (MrcData, Channel, MrcIterationCke,  RankMask, (1 << 0), BestCmd[Channel][0], 1);
+
+    //
+    // CAB is controlled by CMDS.CmdPi1Code and CMDN.CmdPi1Code
+    //
+    ShiftPIforCmdTraining (MrcData, Channel, MrcIterationCmdS, RankMask, (1 << 1), BestCmd[Channel][1], 1);
+    ShiftPIforCmdTraining (MrcData, Channel, MrcIterationCmdN, RankMask, (1 << 1), BestCmd[Channel][1], 1);
+  } // for Channel
+
+  return Status;
+}
+
+/**
+  Early CA / CS training for LPDDR.
+  Main flow:
+  1. Put DRAMs in CA training mode using MRW41.
+  2. Run CS vs. CLK training.
+  3. Map DQ pins according to the board swizzling.
+  4. Run CA vs. CLK training.
+  5. Select optimal CA timings for each CA bus per rank
+
+  @param[in] MrcData - The MRC global data.
+
+  @retval mrcSuccess if succeeded
+**/
+MrcStatus
+EarlyCommandTrainingLpddr (
+  IN MrcParameters * const MrcData
+)
+{
+  const MrcInput                              *Inputs;
+  const MrcDebug                              *Debug;
+  MrcOutput                                   *Outputs;
+  MrcControllerOut                            *ControllerOut;
+  MrcStatus                                   Status;
+  U8                                          ChannelBitMask;
+  U8                                          ValidRankMask;
+//  DDRCMD_CR_DDRCRCMDPICODING_STRUCT           DdrCrCmdPiCoding;
+
+
+  Inputs        = &MrcData->SysIn.Inputs;
+  Debug         = &Inputs->Debug;
+  Outputs       = &MrcData->SysOut.Outputs;
+  ControllerOut = &Outputs->Controller[0];
+
+  ValidRankMask   = Outputs->ValidRankMask;
+  ChannelBitMask  = Outputs->ValidChBitMask;
+  Status = mrcSuccess;
+
+//  //
+//  // Set initial Pi settings for CLK / CMD / CTL - done in MrcMcConfiguration
+//  //
+//  DdrCrCmdPiCoding.Data = 0;
+//  DdrCrCmdPiCoding.Bits.CmdPi0Code = 96;
+//  DdrCrCmdPiCoding.Bits.CmdPi1Code = 96;
+//  MrcWriteCR (MrcData, DDRCMD_CR_DDRCRCMDPICODING_REG, DdrCrCmdPiCoding.Data);
+
+
+  //
+  // Run CPU-to-DRAM DQ Mapping - Run after 2D CS/CA and/or before CS training
+  //
+  Status = MapCA2DQPins (MrcData);
+  if (Status != mrcSuccess) {
+    return Status;
+  }
+
+  //
+  // Run CS vs. CLK training
+  //
+  Status = EarlyChipSelectTraining (MrcData);
+  if (Status != mrcSuccess) {
+    return Status;
+  }
+
+  //
+  // Run CA vs. CLK training
+  //
+  Status = EarlyCaTraining (MrcData);
+  if (Status != mrcSuccess) {
+    return Status;
+  }
+
+  //
+  // Program DESWIZZLE_HIGH/LOW registers
+  //
+  ProgramDeswizzleRegisters (MrcData);
+
+  //
+  // Set this flag so that MrcResetSequence() will include MrcJedecInitLpddr3() as well.
+  //
+  Outputs->LpddrEctDone = TRUE;
+
+  return Status;
+}
+
+/**
+  Sweep CS Pi up or down and find edges for all bytes.
+  Main flow:
+  1.
+  2.
+  3.
+
+  @param[in]  MrcData - The MRC global data.
+  @param[out] Limit   - array of edge PI values per channel, rank and CPU byte
+
+  @retval none
+**/
+void
+ChipSelectFindEdge (
+  IN MrcParameters * const  MrcData,
+  U8                        Rank,
+  U8                        Start,
+  U8                        Stop,
+  S8                        Step,
+  OUT U8                    Limit[MAX_CHANNEL][MAX_RANK_IN_CHANNEL][MAX_SDRAM_IN_DIMM]
+  )
+{
+  MrcInput          *Inputs;
+  MrcDebug          *Debug;
+  MrcOutput         *Outputs;
+  MrcControllerIn   *ControllerIn;
+  MrcControllerOut  *ControllerOut;
+  MrcChannelIn      *ChannelIn;
+  MrcChannelOut     *ChannelOut;
+  U8                Channel;
+  U8                ChannelMask;
+  U8                Byte;
+  U8                ByteMask;
+  U8                DramByte;
+  U8                ByteDoneMask[MAX_CHANNEL];
+  U8                PiCode;
+  U8                Feedback[MAX_CHANNEL][MAX_SDRAM_IN_DIMM];
+  U32               Pattern;
+  U32               DelayChipSelectCadb;
+  U32               Offset;
+  BOOL              Done;
+  BOOL              Failed;
+  char              *BytesHeader;
+  char              PassFail;
+  DDRDATA0CH0_CR_DATATRAINFEEDBACK_STRUCT DataTrainFeedback;
+
+  Inputs        = &MrcData->SysIn.Inputs;
+  Debug         = &Inputs->Debug;
+  Outputs       = &MrcData->SysOut.Outputs;
+  ControllerIn  = &Inputs->Controller[0];
+  ControllerOut = &Outputs->Controller[0];
+  ChannelMask   = 0;
+
+  DelayChipSelectCadb = 1 * HPET_1US;
+
+  MrcOemMemorySet (ByteDoneMask, 0, sizeof (ByteDoneMask));
+
+  PiCode = Start;
+  Done = FALSE;
+
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\t Ch0 pattern 1\t\t\t   Ch1 pattern 1\t\t     Ch 0 pattern 2\t\t       Ch 1 pattern 2\n");
+  BytesHeader = "0   1   2   3   4   5   6   7     ";
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "CTL PI\t %s%s%s%s\n", BytesHeader, BytesHeader, BytesHeader, BytesHeader);
+
+  while (!Done) {
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%d:\t", PiCode);
+    for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+      if (!MrcRankInChannelExist (MrcData, Rank, Channel)) {
+        continue;
+      }
+      ShiftPIforCmdTraining (MrcData, Channel, MrcIterationCtl, 1 << Rank, 1, PiCode, 0);
+    }
+
+    //
+    // Try two different paterns (0x2AA or 0x155), to see if the command is still decoded correctly
+    //
+    for (Pattern = 0; Pattern <= 1; Pattern++) {
+      for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+        if (!MrcRankInChannelExist (MrcData, Rank, Channel)) {
+          continue;
+        }
+        ChannelMask |= (1 << Channel);
+        SetCadbPatternBuffers (MrcData, Channel, (Pattern == 0) ? 0x3000 : 0x7000, 0x4000, 0x0000);
+      }
+
+      //
+      // Run CADB pattern on selected channels at the same time
+      //
+      ShortRunCADB (MrcData, ChannelMask);
+      MrcWait (MrcData, DelayChipSelectCadb);
+
+      //
+      // Read and process the results
+      //
+      for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+        if (!MrcRankInChannelExist (MrcData, Rank, Channel)) {
+          ByteDoneMask[Channel] = 0xFF;
+          MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "                                  ");
+          continue;
+        }
+        if (ByteDoneMask[Channel] == 0xFF) { // All bytes failed on this channel, no need to sweep anymore
+          MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "                                  ");
+          continue;
+        }
+        ChannelIn  = &ControllerIn->Channel[Channel];
+        ChannelOut = &ControllerOut->Channel[Channel];
+        for (Byte = 0; Byte < Outputs->SdramCount; Byte++) {
+          ByteMask = (1 << Byte);
+          DramByte = ChannelIn->DqsMapCpu2Dram[Byte];
+          if (ChannelOut->Dimm[dDIMM0].SdramWidth == 32) {
+            if ((DramByte & 0x02) != 0) {
+              //
+              // Ignore upper 16 bits on x32 devices in MRW41 feedback - DRAM bytes 2, 3, 6 and 7
+              //
+              ByteDoneMask[Channel] |= ByteMask;
+              MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "    ");
+              continue;
+            }
+          }
+          Offset = DDRDATA0CH0_CR_DATATRAINFEEDBACK_REG +
+            ((DDRDATA0CH1_CR_DATATRAINFEEDBACK_REG - DDRDATA0CH0_CR_DATATRAINFEEDBACK_REG) * Channel) +
+            ((DDRDATA1CH0_CR_DATATRAINFEEDBACK_REG - DDRDATA0CH0_CR_DATATRAINFEEDBACK_REG) * Byte);
+          DataTrainFeedback.Data = (MrcReadCR (MrcData, Offset) & 0xFF);  // Get only DQ bits, not DQS
+          PassFail = '#';
+          if ((ByteDoneMask[Channel] & ByteMask) == 0) {
+            if (Pattern == 0) {
+              //
+              // First pattern
+              //
+              Feedback[Channel][Byte] = (U8) DataTrainFeedback.Data;
+              PassFail = ' ';
+            } else {
+              //
+              // Second Pattern
+              // If still read the same data, then DRAM was not able to decode the new command
+              //
+              Failed = FALSE;
+              if (Feedback[Channel][Byte] == (U8) DataTrainFeedback.Data) {
+                Failed = TRUE;
+              }
+              if (MrcCountBitsEqOne (DataTrainFeedback.Data) != 4) {
+                Failed = TRUE;
+              }
+              if (Failed) {
+                Limit[Channel][Rank][Byte] = PiCode;
+                ByteDoneMask[Channel] |= ByteMask;
+              } else {
+                PassFail = '.';
+              }
+            }
+          }
+          MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%c%02X ", PassFail, DataTrainFeedback.Data);
+        }  // for Byte
+        MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "  ");
+      }  // for Channel
+    } // for Pattern
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\n");
+
+    if ((ByteDoneMask[0] == 0xFF) && (ByteDoneMask[1] == 0xFF)) {
+      // Found the limit on all bytes on both channels - no need to sweep Pi any longer
+      break;
+    }
+
+    PiCode += Step;
+    if (Step > 0) {
+      // Sweep up
+      Done = (PiCode > Stop);
+    } else {
+      // Sweep down
+      Done = (((S8) PiCode) < Stop);
+    }
+  }  // while not done
+}
+
+/**
+  Process the results of the early LPDDR3 CS training and find the best PI settings for CS and CLK.
+  Flow:
+   1. Find the worst case Right and Left limits for each group
+   2. Find the Center for each group
+
+  @param[in]  MrcData     - The MRC global data.
+  @param[in]  LeftLimit   - array of left edge values per channel, rank and CPU byte
+  @param[in]  RightLimit  - array of right edge values per channel, rank and CPU byte
+  @param[out] BestCs      - array of best CS PI settings, per channel and group
+  @param[out] BestClk     - array of best CLK PI settings, per channel and group
+
+  @retval mrcSuccess if succeeded
+**/
+MrcStatus
+FindBestCsClkPi (
+  IN  MrcParameters * const MrcData,
+  IN  U8                    LeftLimit[MAX_CHANNEL][MAX_RANK_IN_CHANNEL][MAX_SDRAM_IN_DIMM],
+  IN  U8                    RightLimit[MAX_CHANNEL][MAX_RANK_IN_CHANNEL][MAX_SDRAM_IN_DIMM],
+  OUT U8                    BestCs[MAX_CHANNEL][2],
+  OUT U8                    BestClk[MAX_CHANNEL][2]
+  )
+{
+  MrcInput          *Inputs;
+  MrcDebug          *Debug;
+  MrcOutput         *Outputs;
+  MrcChannelIn      *ChannelIn;
+  MrcStatus         Status;
+  U8                Channel;
+  U8                Rank;
+  U8                Byte;
+  U8                Group;
+  U8                Count;
+  U8                GroupLeftLimit[MAX_CHANNEL][MAX_RANK_IN_CHANNEL][2];  // Per ch, rank and group
+  U8                GroupRightLimit[MAX_CHANNEL][MAX_RANK_IN_CHANNEL][2]; // Per ch, rank and group
+  U8                GroupCenter[MAX_CHANNEL][MAX_RANK_IN_CHANNEL][2];     // Per ch, rank and group
+  S8                ClkDelta[MAX_RANK_IN_CHANNEL];
+  S8                MeanClkDelta;
+  S8                CsDelta[2];  // Per group
+  S8                MeanCsDelta;
+
+  Inputs        = &MrcData->SysIn.Inputs;
+  Debug         = &Inputs->Debug;
+  Outputs       = &MrcData->SysOut.Outputs;
+
+  Status = mrcSuccess;
+
+  MrcOemMemorySet ((U8 *) GroupRightLimit, 127, sizeof (GroupRightLimit));
+  MrcOemMemorySet ((U8 *) GroupLeftLimit, 0, sizeof (GroupLeftLimit));
+  MrcOemMemorySet ((U8 *) GroupCenter, 0, sizeof (GroupCenter));
+
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Finding best CS/CLK PIs:\n");
+  for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+    if (!MrcChannelExist (Outputs, Channel)) {
+      continue;
+    }
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Channel: %d\tLeft\tRight\tCenter\n", Channel);
+    ChannelIn = &Inputs->Controller[0].Channel[Channel];
+    for (Rank = 0; Rank < MAX_RANK_IN_CHANNEL; Rank++) {
+      if (!MrcRankInChannelExist (MrcData, Rank, Channel)) {
+        continue;
+      }
+      for (Group = 0; Group < 2; Group++) {
+        for (Byte = 0; Byte < Outputs->SdramCount; Byte++) {
+          //
+          // Find the worst case Right and Left limits for each group
+          //
+          if (ChannelIn->DQByteMap[MrcIterationClock][Group] & (1 << Byte)) {
+            if (GroupRightLimit[Channel][Rank][Group] > RightLimit[Channel][Rank][Byte]) {
+              GroupRightLimit[Channel][Rank][Group] = RightLimit[Channel][Rank][Byte];
+            }
+
+            if (GroupLeftLimit[Channel][Rank][Group] < LeftLimit[Channel][Rank][Byte]) {
+              GroupLeftLimit[Channel][Rank][Group] = LeftLimit[Channel][Rank][Byte];
+            }
+          }
+        } // for Byte
+
+        //
+        // Find the Center for each group
+        //
+        GroupCenter[Channel][Rank][Group] =
+          (GroupRightLimit[Channel][Rank][Group] + GroupLeftLimit[Channel][Rank][Group]) / 2;
+
+        MRC_DEBUG_MSG (
+          Debug,
+          MSG_LEVEL_NOTE,
+          "Rank%d CLK%d\t%d\t%d\t%d\n",
+          Rank,
+          Group,
+          GroupLeftLimit[Channel][Rank][Group],
+          GroupRightLimit[Channel][Rank][Group],
+          GroupCenter[Channel][Rank][Group]
+          );
+      } // for Group
+    } // for Rank
+
+    //
+    // Find the CS delta between ranks for each clock group, and then group average
+    //
+    for (Count = 0, Group = 0; Group < 2; Group++) {
+      if (MrcRankInChannelExist (MrcData, 1, Channel)) {
+        CsDelta[Group] = (GroupCenter[Channel][1][Group] - GroupCenter[Channel][0][Group]);
+        Count++;
+      } else {
+        CsDelta[Group] = 0; // Single rank 0 case
+      }
+      MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "CLK%d delta (Rank0-Rank1) = %d  \n", Group, CsDelta[Group]);
+    }
+
+    MeanCsDelta = (Count != 0) ? (CsDelta[0] + CsDelta[1]) / Count : 0;
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Mean CS delta = %d\n", MeanCsDelta);
+
+    //
+    // Find the Clock delta for each rank, and then average between ranks
+    // @todo Add case of single CLK group
+    //
+    for (Count = 0, Rank = 0; Rank < MAX_RANK_IN_CHANNEL; Rank++) {
+      if (MrcRankInChannelExist (MrcData, Rank, Channel)) {
+        ClkDelta[Rank] = (GroupCenter[Channel][Rank][1] - GroupCenter[Channel][Rank][0]);
+        Count++;
+        MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Rank%d delta (CLK1-CLK0) = %d  \n", Rank, ClkDelta[Rank]);
+      } else {
+        ClkDelta[Rank] = 0; // No such rank
+      }
+    }
+    MeanClkDelta = (Count != 0) ? (ClkDelta[0] + ClkDelta[1]) / Count : 0;
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Mean Clock delta = %d\n", MeanClkDelta);
+
+    BestClk[Channel][0] = (U8) (64 - MeanClkDelta / 2);               // CLK0
+    BestClk[Channel][1] = (U8) (BestClk[Channel][0] + MeanClkDelta);  // CLK1
+
+    BestCs[Channel][0] = (GroupCenter[Channel][0][0] + GroupCenter[Channel][0][1]) / 2; // CS0
+    BestCs[Channel][1] = (GroupCenter[Channel][1][0] + GroupCenter[Channel][1][1]) / 2; // CS1
+
+    MRC_DEBUG_MSG (
+      Debug,
+      MSG_LEVEL_NOTE,
+      "Best PI CLK0=%d, CLK1=%d, CS0=%d, CS1=%d\n",
+      BestClk[Channel][0],
+      BestClk[Channel][1],
+      BestCs[Channel][0],
+      BestCs[Channel][1]
+      );
+  } // for Channel
+
+  return Status;
+}
+
+/**
+  Early CS / CLK training for LPDDR.
+  Main flow:
+  1. Setup CADB pattern for CS Training.
+  2. Run CS vs. CLK training.
+  3. Select optimal CS and CLK timings
+
+  @param[in] MrcData - The MRC global data.
+
+  @retval mrcSuccess if succeeded
+**/
+MrcStatus
+EarlyChipSelectTraining (
+  IN MrcParameters * const MrcData
+  )
+{
+  MrcInput                                    *Inputs;
+  MrcDebug                                    *Debug;
+  MrcOutput                                   *Outputs;
+  MrcControllerIn                             *ControllerIn;
+  MrcControllerOut                            *ControllerOut;
+  MrcChannelIn                                *ChannelIn;
+  MrcChannelOut                               *ChannelOut;
+  MrcStatus                                   Status;
+  BOOL                                        ClockPiChanged;
+  U8                                          Channel;
+  U8                                          Rank;
+  U8                                          RankBit;
+  U8                                          Byte;
+  U8                                          DramByte;
+  U8                                          Group;
+  U8                                          RankMask;
+  U32                                         Offset;
+  S32                                         ClkDelta;
+  U8                                          PiLow;
+  U8                                          PiHigh;
+  U8                                          PiMiddle;
+  U8                                          PiStep;
+  U8                                          RightLimit[MAX_CHANNEL][MAX_RANK_IN_CHANNEL][MAX_SDRAM_IN_DIMM];
+  U8                                          LeftLimit[MAX_CHANNEL][MAX_RANK_IN_CHANNEL][MAX_SDRAM_IN_DIMM];
+  U8                                          BestCs[MAX_CHANNEL][2];
+  U8                                          BestClk[MAX_CHANNEL][2];
+  DDRDATACH0_CR_DDRCRDATACONTROL0_STRUCT      DdrCrDataControl0;
+  DDRDATA0CH0_CR_DDRCRDATACONTROL2_STRUCT     DdrCrDataControl2;
+
+  Inputs        = &MrcData->SysIn.Inputs;
+  Debug         = &Inputs->Debug;
+  Outputs       = &MrcData->SysOut.Outputs;
+  ControllerIn  = &Inputs->Controller[0];
+  ControllerOut = &Outputs->Controller[0];
+
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "EarlyChipSelectTraining started\n");
+
+  Status = mrcSuccess;
+  RankMask  = Outputs->ValidRankMask;
+
+  PiLow     = 0;
+  PiHigh    = 127;
+  PiMiddle  = 64;
+  PiStep = 2;
+
+  MrcOemMemorySet ((U8 *) RightLimit, PiHigh, sizeof (RightLimit));
+  MrcOemMemorySet ((U8 *) LeftLimit, PiLow, sizeof (LeftLimit));
+
+  //
+  // Enable the following bits because we will use DATATRAINFEEDBACK to read back CA values on DQ pins:
+  //  DataControl0.SenseampTrainingMode and ForceOdtOn
+  //  DataControl2.ForceRxOn and ForceBiasOn
+  //
+  for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+    if (!MrcChannelExist (Outputs, Channel)) {
+      continue;
+    }
+    ChannelOut = &ControllerOut->Channel[Channel];
+    for (Byte = 0; Byte < Outputs->SdramCount; Byte++) {
+      DdrCrDataControl2.Data = ChannelOut->DqControl2[Byte].Data;
+      DdrCrDataControl2.Bits.ForceBiasOn = 1;
+      DdrCrDataControl2.Bits.ForceRxOn   = 1;
+      Offset = DDRDATA0CH0_CR_DDRCRDATACONTROL2_REG +
+        ((DDRDATA0CH1_CR_DDRCRDATACONTROL2_REG - DDRDATA0CH0_CR_DDRCRDATACONTROL2_REG) * Channel) +
+        ((DDRDATA1CH0_CR_DDRCRDATACONTROL2_REG - DDRDATA0CH0_CR_DDRCRDATACONTROL2_REG) * Byte);
+      MrcWriteCR (MrcData, Offset, DdrCrDataControl2.Data);
+    }
+    DdrCrDataControl0.Data = ChannelOut->DqControl0.Data;
+    DdrCrDataControl0.Bits.ForceOdtOn           = 1;
+    DdrCrDataControl0.Bits.SenseampTrainingMode = 1;
+    Offset = DDRDATACH0_CR_DDRCRDATACONTROL0_REG +
+      ((DDRDATACH1_CR_DDRCRDATACONTROL0_REG - DDRDATACH0_CR_DDRCRDATACONTROL0_REG) * Channel);
+    MrcWriteCrMulticast (MrcData, Offset, DdrCrDataControl0.Data);
+  }
+
+  for (Rank = 0; Rank < MAX_RANK_IN_CHANNEL; Rank++) {
+    RankBit = 1 << Rank;
+    if ((RankBit & RankMask) == 0) {
+      continue;
+    }
+
+    for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+      if (!MrcRankInChannelExist (MrcData, Rank, Channel)) {
+        continue;
+      }
+
+      //
+      // Put the current Rank in CA training mode using MRW41.
+      //
+      Status = LpddrCommandTrainingMode (MrcData, 1 << Channel, RankBit, CaTrainingMode41);
+      if (Status != mrcSuccess) {
+        return Status;
+      }
+
+      SetupCaTrainingCadb (
+        MrcData,
+        Channel,
+        Rank,
+        CadbLinesCs,
+        sizeof (CadbLinesCs) / sizeof (CadbLinesCs[0]),
+        0x3000,
+        0x4000,
+        0x0000
+        );
+    }  // for Channel
+
+    //
+    // Sweep CS Pi up and down from the middle, on both channels at the same time
+    //
+    ChipSelectFindEdge (MrcData, Rank, PiMiddle, PiHigh, PiStep, RightLimit);
+    ChipSelectFindEdge (MrcData, Rank, PiMiddle, PiLow, -PiStep, LeftLimit);
+
+    for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+      if (!MrcRankInChannelExist (MrcData, Rank, Channel)) {
+        continue;
+      }
+      ChannelIn  = &ControllerIn->Channel[Channel];
+      ChannelOut = &ControllerOut->Channel[Channel];
+      MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "CS training data Ch%d Rank%d\nCPU Byte\tLeft\tRight\n", Channel, Rank);
+      for (Byte = 0; Byte < Outputs->SdramCount; Byte++) {
+        DramByte = ChannelIn->DqsMapCpu2Dram[Byte];
+        if (ChannelOut->Dimm[dDIMM0].SdramWidth == 32) {
+          if ((DramByte & 0x02) != 0) {
+            //
+            // Ignore upper 16 bits on x32 devices in MRW41 feedback - DRAM bytes 2, 3, 6 and 7
+            //
+            continue;
+          }
+        }
+        MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%d\t\t%d\t%d\n",
+          Byte, LeftLimit[Channel][Rank][Byte], RightLimit[Channel][Rank][Byte]);
+      }
+
+      //
+      // Put the CTL PI back to middle for MRW42 command
+      //
+      ShiftPIforCmdTraining (MrcData, Channel, MrcIterationCtl, 3, 1, PiMiddle, 1);
+
+      //
+      // Exit CA training mode on the current rank
+      //
+      Status = LpddrCommandTrainingMode (MrcData, 1 << Channel, RankBit, CaTrainingMode42);
+
+      if (Status != mrcSuccess) {
+        return Status;
+      }
+    } // for Channel
+  }  // for Rank
+
+  //
+  // Restore original DataControl0 and DataControl2 values
+  //
+  for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+    if (!MrcChannelExist (Outputs, Channel)) {
+      continue;
+    }
+    ChannelOut = &ControllerOut->Channel[Channel];
+    Offset = DDRDATACH0_CR_DDRCRDATACONTROL0_REG +
+      ((DDRDATACH1_CR_DDRCRDATACONTROL0_REG - DDRDATACH0_CR_DDRCRDATACONTROL0_REG) * Channel);
+    MrcWriteCrMulticast (MrcData, Offset, ChannelOut->DqControl0.Data);
+
+    for (Byte = 0; Byte < Outputs->SdramCount; Byte++) {
+      Offset = DDRDATA0CH0_CR_DDRCRDATACONTROL2_REG +
+        ((DDRDATA0CH1_CR_DDRCRDATACONTROL2_REG - DDRDATA0CH0_CR_DDRCRDATACONTROL2_REG) * Channel) +
+        ((DDRDATA1CH0_CR_DDRCRDATACONTROL2_REG - DDRDATA0CH0_CR_DDRCRDATACONTROL2_REG) * Byte);
+      MrcWriteCR (MrcData, Offset, ChannelOut->DqControl2[Byte].Data);
+    }
+  }
+
+  //
+  // Select optimal CS and CLK timings for both channels
+  //
+  FindBestCsClkPi (MrcData, LeftLimit, RightLimit, BestCs, BestClk);
+
+  //
+  // Apply the new CTL and CLK PI settings
+  //
+  ClockPiChanged = FALSE;
+  for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+    if (!MrcChannelExist (Outputs, Channel)) {
+      continue;
+    }
+    ChannelIn  = &ControllerIn->Channel[Channel];
+    ChannelOut = &ControllerOut->Channel[Channel];
+    for (Rank = 0; Rank < MAX_RANK_IN_CHANNEL; Rank++) {
+      if (!MrcRankInChannelExist (MrcData, Rank, Channel)) {
+        continue;
+      }
+      //
+      // Shift CS per rank
+      //
+      ShiftPIforCmdTraining (
+        MrcData,
+        Channel,
+        MrcIterationCtl,
+        1 << Rank,
+        1,
+        BestCs[Channel][Rank],
+        1            // UpdateHost
+        );
+    }
+    for (Group = 0; Group < 2; Group++) {
+      //
+      // Shift CLK per group, if needed, and update host struct
+      //
+      ClkDelta = (S32) BestClk[Channel][Group] - (S32) ChannelOut->ClkPiCode[Group];
+      if (ClkDelta != 0) {
+        ClockPiChanged = TRUE;
+        ShiftPIforCmdTraining (MrcData, Channel, MrcIterationClock, RankMask, 1 << Group, ClkDelta, 1);
+
+        //
+        // Shift the corresponding CMD PI by the same amount as the CLK
+        //
+        if (ChannelIn->DQByteMap[MrcIterationClock][Group] == ChannelIn->DQByteMap[MrcIterationCmdS][0]) {
+          //
+          // CAA is controlled by CMDS.CmdPi0Code and CKE.CmdPi0Code
+          //
+          ShiftPIforCmdTraining (MrcData, Channel, MrcIterationCmdS, RankMask, (1 << 0),
+            ChannelOut->CmdsCmdPiCode[0] + ClkDelta, 1);
+          ShiftPIforCmdTraining (MrcData, Channel, MrcIterationCke,  RankMask, (1 << 0),
+            ChannelOut->CkeCmdPiCode[0] + ClkDelta, 1);
+        }
+        if (ChannelIn->DQByteMap[MrcIterationClock][Group] == ChannelIn->DQByteMap[MrcIterationCmdS][1]) {
+          //
+          // CAB is controlled by CMDS.CmdPi1Code and CMDN.CmdPi1Code
+          //
+          ShiftPIforCmdTraining (MrcData, Channel, MrcIterationCmdS, RankMask, (1 << 1),
+            ChannelOut->CmdsCmdPiCode[1] + ClkDelta, 1);
+          ShiftPIforCmdTraining (MrcData, Channel, MrcIterationCmdN, RankMask, (1 << 1),
+            ChannelOut->CmdnCmdPiCode[1] + ClkDelta, 1);
+        }
+      }
+    }
+  } // for Channel
+
+  //
+  // Perform IO reset and JEDEC reset if clock PI was changed.
+  //
+  if (ClockPiChanged) {
+    MrcResetSequence (MrcData);
+  }
+
+  return Status;
+}
+
+////
+//// CA to DQ mapping during MRW41
+//// First index is rising edge (0) / falling edge (1)
+//// Second index is CA pin
+////
+//U8 CA2DQMapping[2][9] = {
+//  { 0x00,0x02,0x04,0x06,0x10,0x08,0x0A,0x0C,0x0E },
+//  { 0x01,0x03,0x05,0x07,0x11,0x09,0x0B,0x0D,0x0F }
+//};
+//
+///**
+//
+//  Map byte to group for the given Iteration
+//
+//  @param[in] MrcData - The MRC global data.
+//  @param[in] Iteration
+//  @param[in] Byte
+//
+//  @retval Group
+//
+//**/
+//
+//U8
+//MapByte2Group (
+//  MrcParameters * const MrcData,
+//  U8                    Iteration,
+//  U8                    Channel,
+//  U8                    Byte
+//  )
+//{
+//  MrcInput          *Inputs;
+//  MrcControllerIn   *ControllerIn;
+//  MrcChannelIn      *ChannelIn;
+//  U32               ByteMask;
+//  U32               SafeIteration;
+//  U8                Group;
+//  U8                SafeGroup;
+//  U8                TargetGroup;
+//
+//  Inputs        = &MrcData->SysIn.Inputs;
+//  ControllerIn  = &Inputs->Controller[0];
+//  ChannelIn     = &ControllerIn->Channel[Channel];
+//
+//  SafeIteration = 2;            // CmdS has a mapping for all bytes (uses CAA & CAB)
+//  SafeGroup     = 0;            // This is not true for all iterations
+//  TargetGroup   = 0;            // ex: CmdN and CKE only use one of the CAA/CAB buses
+//  ByteMask      = 0;            // ex: Clk may or may not go to all bytes
+//
+//  for (Group = 0; Group < 2; Group++) {
+//    ByteMask |= ChannelIn->DQByteMap[Iteration][Group];
+//    if (ChannelIn->DQByteMap[Iteration][Group] & (1 << Byte)) {
+//      TargetGroup = Group;
+//    }
+//    if (ChannelIn->DQByteMap[SafeIteration][Group] & (1 << Byte)) {
+//      SafeGroup = Group;
+//    }
+//  }
+//
+//  if (ByteMask == 0xFF) {
+//    return TargetGroup;
+//  } else {
+//    return SafeGroup;
+//  }
+//}
+//
+///**
+//
+//  Update the DRAM to CPU DQ mapping for a given byte based on CA training results.
+//  DQMapping is from CPU to DRAM
+//  Victim is the CA victim bit
+//  ByteFB is an 8 bit value that we received back for a Walking 0 VA pattern
+//  Diff is an 8 bit value with ones in the victim bit positions
+//  Return 0 if everything made sense, otherwise returns (1<<Group) to indicate an error
+//  In the case of an error, DQMapping is not updated
+//
+//  @param[in] MrcData - The MRC global data.
+//
+//  @retval 0            - if a valid mapping was found
+//  @retval (1 << Group) - in case of error
+//
+//**/
+//U8
+//UpdateDQMapping (
+//  IN OUT U8 DQMapping[64],
+//  IN U8 Byte,
+//  IN U8 ByteFeedback,
+//  IN U8 Diff,
+//  IN U8 Victim,
+//  IN U8 Group
+//  )
+//{
+//  U32 BitsHigh;
+//  U8  DramDQHigh;
+//  U8  DramDQLow;
+//  U8  CpuDQHigh;
+//  U8  CpuDQLow;
+//  U8  Bit;
+//  U8  BitValue;
+//
+//  if (Diff == 0) {
+//    return 0;   // No error to look at
+//  }
+//
+//  //
+//  // Should never see an error with these victim lanes since their data returns with MRW 48
+//  // This function is only used with data from MRW 41
+//  if ((Victim == 4) || (Victim == 9)) {
+//    return (1 << Group);
+//  }
+//
+//  //
+//  // Walk through the bits with errors and figure out the mapping
+//  //
+//  BitsHigh    = 0;
+//  DramDQHigh  = 0xFF;
+//  DramDQLow   = 0xFF;
+//  CpuDQHigh   = 0xFF;
+//  CpuDQLow    = 0xFF;
+//
+//  for (Bit = 0; Bit < 8; Bit++) {
+//    BitValue = 1 << Bit;
+//    if ((Diff & BitValue) != 0) {
+//      BitsHigh++;                           // Count number of mismatches.  Should be exactly 2
+//      if ((ByteFeedback & BitValue) != 0) { // 1 on Victim bit during WalkZero indicates low phase
+//        CpuDQLow  = Bit;
+//        DramDQLow = CA2DQMapping[1][Victim] & 0xF;
+//      } else {                              // 0 on Victim bit during WalkZero indicates high phase
+//        CpuDQHigh  = Bit;
+//        DramDQHigh = CA2DQMapping[0][Victim] & 0xF;
+//      }
+//    }
+//  }
+//
+//  if ((BitsHigh == 2) && (CpuDQLow != 0xFF) && (CpuDQHigh != 0xFF)) {
+//    //
+//    // This is a valid feedback that makes sense
+//    //
+//    DQMapping[8 * Byte + CpuDQLow]  = (Group << 4) + DramDQLow;
+//    DQMapping[8 * Byte + CpuDQHigh] = (Group << 4) + DramDQHigh;
+//    return 0;
+//  }
+//
+//  //
+//  // This is not a valid feedback
+//  //
+//  return (1 << Group);
+//}
+//
+///**
+//
+//  Find the DRAM to CPU DQ mapping based on CA training results.
+//  DQMapping is from CPU to DRAM
+//  ByteFB is an 8 bit value that we received back for a Walking 0 VA pattern
+//
+//  @param[in] MrcData    - The MRC global data.
+//  @param[in] ByteFB     - Array of Ch X Byte for WalkZero results (WalkOne will just be the inverse)
+//  @param[in] DQMapping  - Array of Ch x 64 bits for mapping X64 CPU to X16 DRAM
+//  @param[in] X16Count   - Array of Ch x Group that indicates how many X16 words are in a given ch/group
+//                          Usually this is either 0 or 2 (ie: 0 bits or 32 bits)
+//  @param[in] ChError    - Arrray of Ch with a bit mask indicating if this Ch/Group had an error
+//
+//  @retval none
+//
+//**/
+//
+//void
+//FindECTCpu2DramMapping (
+//  MrcParameters * const MrcData,
+//  U8                    ChBitMask,
+//  U8                    Iteration,
+//  U8                    ByteFB[MAX_CHANNEL][8][11],
+//  IN OUT U8             DQMapping[MAX_CHANNEL][64],
+//  IN U8                 X16Count[MAX_CHANNEL][2],
+//  OUT U8                ChError[MAX_CHANNEL],
+//  BOOL                  UpdateDqMapping
+//  )
+//{
+//  MrcOutput         *Outputs;
+//  MrcChannelOut     *ChannelOut;
+//  MrcControllerOut  *ControllerOut;
+//  U8                Channel;
+//  U8                Byte;
+//  U8                Bit;
+//  U8                Group;
+//  U8                Victim;
+//  U8                RefFB;
+//  U8                Diff;
+//  U8                DramDQ;
+//  U8                CountMappings[2][16];
+//
+//  Outputs       = &MrcData->SysOut.Outputs;
+//  ControllerOut = &Outputs->Controller[0];
+//
+//  MrcOemMemorySet ((U8 *) CountMappings, 0, sizeof (CountMappings));
+//
+//  for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+//    if (!MrcChannelExist (Outputs, Channel)) {
+//      continue;
+//    }
+//    if (((1 << Channel) & ChBitMask) == 0) {
+//      continue;
+//    }
+//    ChannelOut = &ControllerOut->Channel[Channel];
+//
+//    //
+//    // Figure out mappings for all lanes by comparing different walking zero results.
+//    // XOR the Victim=10 vs Victim=N results
+//    // During Victim=10, all CA lanes drive 0101
+//    // During Victim<10, all CA lanes drive 0101 except the victim, which drives 1010
+//    // Use this and the mapping of CA2DQ lanes (JEDEC spec) to figure out the mapping.
+//    //
+//    for (Byte = 0; Byte < 8; ++Byte) {
+//      RefFB = ByteFB[Channel][Byte][10];                // All lanes drive WalkZero Agg = 0101
+//      Group = MapByte2Group (MrcData, Iteration, Channel, Byte); // Find Byte-to-Group mapping
+//
+//      for (Victim = 0; Victim < 10; ++Victim) {
+//        Diff = RefFB ^ ByteFB[Channel][Byte][Victim];   // XOR should produce either (0,2) diffs
+//        ChError[Channel] |= UpdateDQMapping (DQMapping[Channel], Byte, ByteFB[Channel][Byte][Victim], Diff, Victim, Group);
+//      }
+//    }
+//
+//    //
+//    // Check results by making sure everybody is mapped exactly the right number of times.
+//    // DQMapping defines the mapping from 64 CPU DQ lanes to 16 DRAM DQ lanes.
+//    // As a result, we should see each DRAM   DQ lane is listed exactly X16Count times.
+//    //
+//    for (Byte = 0; Byte < 8; ++Byte) {
+//      for (Bit = 0; Bit < 8; ++Bit) {
+//        DramDQ =  DQMapping[Channel][8 * Byte + Bit] & 0xF;
+//        Group  = (DQMapping[Channel][8 * Byte + Bit] >> 4) & 1;
+//        CountMappings[Group][DramDQ]++;
+//      }
+//    }
+//
+//    for (Group = 0; Group < 2; ++Group) {
+//      for (Bit = 0; Bit < 16; ++Bit) {
+//        if (CountMappings[Group][Bit] != X16Count[Channel][Group]) {
+//          ChError[Channel] |= (1 << Group);
+//        }
+//      }
+//    }
+//
+//    //
+//    // Update the DQ Mapping in the host structure if needed
+//    //
+//    if (UpdateDqMapping && (ChError[Channel] == 0)) {
+//      for (Byte = 0; Byte < 8; ++Byte) {
+//        for (Bit = 0; Bit < 8; ++Bit) {
+//          ChannelOut->DqMapCpu2Dram[Byte][Bit] = DQMapping[Channel][8 * Byte + Bit] & 0xF;
+//        }
+//      }
+//    }
+//  } // for Channel
+//}
+//
+///**
+//
+//  Check if the CA training test is done (everybody has already failed) or we need to keep running
+//
+//  @param[in] MrcData   - The MRC global data.
+//  @param[in] ChBitMask - channels to work on
+//  @param[in] Iteration -
+//  @param[in] ChError   - Array of error values per channel, each element is a bitmask per group, '1' means error.
+//
+//  @retval TRUE if the test is done, FALSE otherwise
+//
+//**/
+//BOOL
+//CADBLPDDR3TestIsDone (
+//  IN MrcParameters  * const MrcData,
+//  IN U8                     ChBitMask,
+//  IN U8                     Iteration,
+//  IN U8                     ChError[MAX_CHANNEL]
+//  )
+//{
+//  MrcInput          *Inputs;
+//  MrcControllerIn   *ControllerIn;
+//  MrcChannelIn      *ChannelIn;
+//  U8                Channel;
+//  U8                Group;
+//
+//  Inputs        = &MrcData->SysIn.Inputs;
+//  ControllerIn  = &Inputs->Controller[0];
+//
+//  for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+//    if (((1 << Channel) & ChBitMask) == 0) {
+//      continue;
+//    }
+//    ChannelIn  = &ControllerIn->Channel[Channel];
+//    for (Group = 0; Group < 2; ++Group) {
+//      if ((ChannelIn->DQByteMap[Iteration][Group] > 0) && ((ChError[Channel] & (1 << Group)) == 0)) {
+//        //
+//        // Not done if at least 1 valid ch/group is still passing
+//        //
+//        return FALSE;
+//      }
+//    }
+//  }
+//
+//  //
+//  // If we reach this point, we are done
+//  //
+//  return TRUE;
+//}
+//
+///**
+//
+//  Programs the CADB to output either a WalkingOne or WalkingZero pattern on VictimBit.
+//  Each CA[9:0] lane will toggle with a 1010 pattern but the Victim lane will be inverted.
+//  For a WalkingOne pattern, CAHi[Vic] = 1 and CALo[Vic] = 0.
+//  For a WalkingZero pattern, CAHi[Vic] = 0 and CALo[Vic] = 1.
+//  (VictimBit == 10) is a special case where all CAHi/CALo lanes drive ~WalkOne/WalkOne
+//
+//  Sets up 3 CADB lines that will be used to send out a CA pattern.
+//
+//  Example for VictimBit = 0, WalkOne = 0:
+//
+//  -----------------------
+//  CADB  Phase  Phase  CS
+//  Line  High   Low
+//  -----------------------
+//   0    0x000  0x000  Off  // For delay between CA patterns
+//   1    0x3FE  0x001  On   // CA pattern for rank 0
+//   2    0x3FE  0x001  On   // CA pattern for rank 1
+//
+//  The CS pattern uses Pattern Buffer and hence has 16 lines, with CS active for one line only.
+//  This will send command every 16 DCLKs.
+//
+//  Pattern Buffer details:
+//  The line order is:
+//   for rank 0:    1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+//   for rank 1:    2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+//
+//  001 or 010
+//  000
+//  000
+//  000
+//
+//  000
+//  000
+//  000
+//  000
+//
+//  000
+//  000
+//  000
+//  000
+//
+//  000
+//  000
+//  000
+//  000
+//  ----
+//  001 or 010  --> PB[0] = 0x0001 or 0x0000
+//  000             PB[1] = 0x0000 or 0x0001
+//  000             PB[2] = 0x0000
+//  000
+//
+//  @param[in] MrcData   - The MRC global data.
+//  @param[in] ChBitMask - channels to work on
+//  @param[in] VictimBit - The Victim bit
+//  @param[in] WalkOne   - '1': Use WalkinOne pattern, '0': use WalkingZero pattern.
+//
+//  @retval TRUE if the test is done, FALSE otherwise
+//
+//**/
+//void
+//SetupCADBLPDDR3VaPattern (
+//  IN MrcParameters  * const MrcData,
+//  IN U8                     ChBitMask,
+//  IN U8                     VictimBit,
+//  IN U8                     WalkOne
+//  )
+//{
+//  /*
+//  CADB_LINE CadbLinesCs[] = {
+//    { 0x3FF, 0x3FF, 0 },
+//    { 0x000, 0x000, 0 },
+//    { 0x2AA, 0x2AA, 1 },
+//    { 0x155, 0x155, 1 }
+//  };
+//
+//  SetupCaTrainingCadb (
+//        MrcData,
+//        Channel,
+//        Rank,
+//        CadbLinesCs,
+//        sizeof (CadbLinesCs) / sizeof (CadbLinesCs[0]),
+//        0x9FFE,
+//        0x4000,
+//        0x0000
+//        );
+//  */
+//}
+//
+///**
+//
+//  Runs through a VA test on all CH/Ranks for the current CMD PI timing.
+//  Setups the test, walks though a walking one/zero pattern with each lane as a victim .
+//  If UpdateDqMapping, it will also update host.ch[ch].DQMappingCpu2Dram
+//  Returns a pass/fail based on Ch/Group in ChError
+//
+//  Main flow:
+//  1.
+//  2.
+//  3.
+//
+//  @param[in]      MrcData - The MRC global data.
+//  @param[in, out] ChError - Array of error values per channel, each element is a bitmask per group, '1' means error.
+//
+//  @retval mrcSuccess if succeeded
+//
+//**/
+//MrcStatus
+//RunCADBLPDDR3VATest (
+//  IN MrcParameters  * const MrcData,
+//  IN U8                     ChBitMask,
+//  IN U8                     Ranks,
+//  IN U8                     Iteration,
+//  IN OUT U8                 ChError[MAX_CHANNEL],
+//  IN BOOL                   UpdateDqMapping
+//  )
+//{
+//  MrcInput          *Inputs;
+//  MrcDebug          *Debug;
+//  MrcStatus         Status;
+//  MrcOutput         *Outputs;
+//  MrcControllerIn   *ControllerIn;
+//  MrcControllerOut  *ControllerOut;
+//  MrcChannelIn      *ChannelIn;
+//  MrcChannelOut     *ChannelOut;
+//  U32               Offset;
+//  U8                Channel;
+//  U8                Rank;
+//  U8                Group;
+//  U8                BytesPerGroup;
+//  U8                WalkOne;
+//  U8                VictimBit;
+//  U8                ByteFB[MAX_CHANNEL][8][11];
+//  U8                X16Count[MAX_CHANNEL][2];   // How many X16 words for each ch/group
+//  U8                DQMapping[MAX_CHANNEL][64]; // Lower nibble is X64 CPU lane to X16 DRAM lanes
+//                                                // (this does not unswizzle byte/words)
+//                                                // Upper nibble is which group this X64 CPU lane belongs to (0 or 1)
+//  DDRDATACH0_CR_DDRCRDATACONTROL0_STRUCT      DdrCrDataControl0;
+//
+//  Inputs        = &MrcData->SysIn.Inputs;
+//  Debug         = &Inputs->Debug;
+//  Outputs       = &MrcData->SysOut.Outputs;
+//  ControllerOut = &Outputs->Controller[0];
+//  ControllerIn  = &Inputs->Controller[0];
+//
+//  MrcOemMemorySet ((U8 *) ChError, 0, sizeof (ChError));
+//  MrcOemMemorySet ((U8 *) ByteFB, 0, sizeof (ByteFB));
+//  MrcOemMemorySet ((U8 *) X16Count, 0, sizeof (X16Count));
+//  MrcOemMemorySet ((U8 *) DQMapping, 0, sizeof (DQMapping));
+//
+//  //
+//  // Count number of ranks that are being tested
+//  //
+//  if (MrcCountBitsEqOne (Ranks) == 0) {
+//    return mrcSuccess;
+//  }
+//
+//  //
+//  // Count how many X16 devices are associated with each group
+//  // This will be used to determine how many Ones/Zeros are set in each results
+//  //
+//  for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+//    if (((1 << Channel) & ChBitMask) == 0) {
+//      continue;
+//    }
+//    ChannelIn  = &ControllerIn->Channel[Channel];
+//    ChannelOut = &ControllerOut->Channel[Channel];
+//    for (Group = 0; Group < 2; Group++) {
+//      if (ChannelIn->DQByteMap[Iteration][Group] > 0) {
+//        BytesPerGroup = MrcCountBitsEqOne(ChannelIn->DQByteMap[Iteration][Group]);
+//        if ((BytesPerGroup & 1) != 0) {
+//          MRC_DEBUG_MSG (Debug, MSG_LEVEL_ERROR, "ERROR - Cannot have odd number of bytes per group\n");
+//          return mrcFail;
+//        }
+//        X16Count[Channel][Group] = BytesPerGroup / 2;
+//      }
+//    }
+//
+//    //
+//    // Enable DataControl0.SenseampTrainingMode because we will use DATATRAINFEEDBACK to read back CA values on DQ pins.
+//    // Also enable DataControl0.ForceOdtOn
+//    //
+//    DdrCrDataControl0.Data = ChannelOut->DqControl0;
+//    DdrCrDataControl0.Bits.SenseampTrainingMode = 1;
+//    DdrCrDataControl0.Bits.ForceOdtOn           = 1;
+//    Offset = DDRDATACH0_CR_DDRCRDATACONTROL0_REG +
+//      ((DDRDATACH1_CR_DDRCRDATACONTROL0_REG - DDRDATACH0_CR_DDRCRDATACONTROL0_REG) * Channel);
+//    MrcWriteCrMulticast (MrcData, Offset, DdrCrDataControl0.Data);
+//  }
+//
+//  //
+//  // Put DRAM into MRW 41 CA Training mode
+//  //
+//  Status = LpddrCommandTrainingMode (MrcData, ChBitMask, Ranks, CaTrainingMode41);
+//  if (Status != mrcSuccess) {
+//    return Status;
+//  }
+//
+//  //
+//  // Run associated VA tests for MRW 41 (16 out of 20 CA bits)
+//  //
+//  for (WalkOne = 0; WalkOne < 2; WalkOne++) {
+//    for (VictimBit = 0; VictimBit < 11; VictimBit++) {
+//      //
+//      // Are we done ?
+//      //
+//      if (CADBLPDDR3TestIsDone (MrcData, ChBitMask, Iteration, ChError)) {
+//        break;
+//      }
+//
+//      //
+//      // Program VA pattern in the CADB
+//      //
+//      SetupCADBLPDDR3VaPattern (MrcData, ChBitMask, VictimBit, WalkOne);
+//
+//      //
+//      // Run test on 1 rank at a time and read out the results
+//      //
+//      for (Rank = 0; Rank < MAX_RANK_IN_CHANNEL; Rank++) {
+//        if (!MrcRankInChannelExist (MrcData, Rank, Channel)) {
+//          continue;
+//        }
+//        if ((Ranks & (1 << Rank)) == 0) {
+//          continue;
+//        }
+////@todo:        IssueCADBLPDDR3CmdTest (MrcData, ChBitMask, 1 << Rank, 3); // Operation = 3
+//
+///* @todo:        ReadECTLPDDR3Results (
+//          MrcData,
+//          ChBitMask,
+//          Iteration,
+//          WalkOne,
+//          ByteFB,
+//          VictimBit,
+//          DQMapping,
+//          TRUE,       // Using MRW41
+//          X16Count,
+//          ChError
+//          ); */
+//      }
+//    }
+//  }
+//
+//  //
+//  // Figure out DQ Lane Mapping for later steps and to ensure this sampled good data
+//  // If results do not match expectations, updates ChError appropriately
+//  //
+//  FindECTCpu2DramMapping (MrcData, ChBitMask, Iteration, ByteFB, DQMapping, X16Count, ChError, UpdateDqMapping);
+//
+//  //
+//  // Put DRAM into MRW 48 CA Training Mode
+//  //
+//  Status = LpddrCommandTrainingMode (MrcData, ChBitMask, Ranks, CaTrainingMode48);
+//  if (Status != mrcSuccess) {
+//    return Status;
+//  }
+//
+//  //
+//  // Run associated VA tests for MRW 48 (4 out of 20 CA bits)
+//  //
+//  for (WalkOne = 0; WalkOne < 2; WalkOne++) {
+//    for (VictimBit = 0; VictimBit < 11; VictimBit++) {
+//      //
+//      // Are we done ?
+//      //
+//      if (CADBLPDDR3TestIsDone (MrcData, ChBitMask, Iteration, ChError)) {
+//        break;
+//      }
+//
+//      //
+//      // Program VA pattern in the CADB
+//      //
+//      SetupCADBLPDDR3VaPattern (MrcData, ChBitMask, VictimBit, WalkOne);
+//
+//      //
+//      // Run test on 1 rank at a time and read out the results
+//      //
+//      for (Rank = 0; Rank < MAX_RANK_IN_CHANNEL; Rank++) {
+//        if (!MrcRankInChannelExist (MrcData, Rank, Channel)) {
+//          continue;
+//        }
+//        if ((Ranks & (1 << Rank)) == 0) {
+//          continue;
+//        }
+////@todo:        IssueCADBLPDDR3CmdTest (MrcData, ChBitMask, 1 << Rank, 3); // Operation = 3
+//
+///* @todo:        ReadECTLPDDR3Results (
+//          MrcData,
+//          ChBitMask,
+//          Iteration,
+//          WalkOne,
+//          ByteFB,
+//          VictimBit,
+//          DQMapping,
+//          FALSE,       // Using MRW48
+//          X16Count,
+//          ChError
+//          ); */
+//      }
+//    }
+//  }
+//
+//  //
+//  // Exit CA training mode using MRW42
+//  //
+//  Status = LpddrCommandTrainingMode (MrcData, ChBitMask, Ranks, CaTrainingMode42);
+//  if (Status != mrcSuccess) {
+//    return Status;
+//  }
+//
+//  //
+//  // Restore DataControl0
+//  //
+//  for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+//    if (((1 << Channel) & ChBitMask) == 0) {
+//      continue;
+//    }
+//    ChannelOut = &ControllerOut->Channel[Channel];
+//    Offset = DDRDATACH0_CR_DDRCRDATACONTROL0_REG +
+//      ((DDRDATACH1_CR_DDRCRDATACONTROL0_REG - DDRDATACH0_CR_DDRCRDATACONTROL0_REG) * Channel);
+//    MrcWriteCrMulticast (MrcData, Offset, ChannelOut->DqControl0);
+//  }
+//  return Status;
+//}
+
+#endif // ULT_FLAG
+
diff --git a/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Services/MrcCommon.c b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Services/MrcCommon.c
new file mode 100644
index 0000000..9380989
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Services/MrcCommon.c
@@ -0,0 +1,8010 @@
+/** @file
+  This file include all the common tolls for the mrc algo
+
+@copyright
+  Copyright (c) 1999 - 2013 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement.
+**/
+
+//
+// Include files
+//
+#include "MrcCommon.h"
+
+#ifdef MRC_DEBUG_PRINT
+const char  CcdString[] = "Controller, Channel, Dimm";
+const char  RcvEnDelayString[] = "RcvEnDelay";
+const char  DqsDelayString[] = "DqsDelay";
+
+#endif
+
+/**
+  Return the rank mask in channel if rank exist exist.
+
+  @param[in] MrcData - Pointer to MRC global data.
+  @param[in] Channel - Channel to work on.
+  @param[in] Rank    - Rank to check.
+
+  @retval Bit mask of Rank requested if the Rank exists in the system.
+**/
+U8
+MrcRankInChannelExist (
+  IN MrcParameters *const MrcData,
+  IN const U8             Rank,
+  IN const U8             Channel
+  )
+{
+  return (MRC_BIT0 << Rank) & MrcData->SysOut.Outputs.Controller[0].Channel[Channel].ValidRankBitMask;
+}
+
+/**
+  Return the number of ranks in specific dimm.
+
+  @param[in] MrcData - Pointer to MRC global data.
+  @param[in] Channel - Channel to work on.
+  @param[in] Dimm    - Dimm in channel to return.
+
+  @retval The number of ranks in the dimm.
+**/
+U8
+MrcGetRankInDimm (
+  IN MrcParameters *const MrcData,
+  IN const U8             Dimm,
+  IN const U8             Channel
+  )
+{
+  return MrcData->SysOut.Outputs.Controller[0].Channel[Channel].Dimm[Dimm].RankInDIMM;
+}
+
+/**
+  Returns whether Channel is or is not present.
+
+  @param[in] Outputs - Pointer to MRC global Output data.
+  @param[in] Channel - Channel to test.
+
+  @retval TRUE  - if there is at least one enabled DIMM in the channel.
+  @retval FALSE - if there are no enabled DIMMs in the channel.
+**/
+BOOL
+MrcChannelExist (
+  IN const MrcOutput *const Outputs,
+  IN const U8               Channel
+  )
+{
+
+  return (Outputs->Controller[0].Channel[Channel].Status == CHANNEL_PRESENT) ? TRUE : FALSE;
+}
+
+/**
+  This function disable channel parameters.
+  After this function the MRC don't use with the channel.
+
+  @param[in] MrcData           - Include all MRC global data.
+  @param[in] ChannelToDisable  - Channel to disable.
+  @param[in] SkipDimmCapacity  - Switch to skip setting the DimmCapacity to 0 for the dimms in the channel disabled.
+
+  @retval Nothing
+**/
+void
+MrcChannelDisable (
+  IN MrcParameters *const MrcData,
+  IN const U8             ChannelToDisable,
+  IN const U8             SkipDimmCapacity
+  )
+{
+  MrcChannelOut *ChannelOut;
+  MrcDimmOut    *DimmOut;
+  U32           Dimm;
+
+  ChannelOut = &MrcData->SysOut.Outputs.Controller[0].Channel[ChannelToDisable];
+  if (ChannelOut->Status == CHANNEL_PRESENT) {
+    ChannelOut->Status            = CHANNEL_DISABLED;
+    ChannelOut->RankInChannel     = 0;
+    ChannelOut->ValidRankBitMask  = 0;
+    for (Dimm = 0; Dimm < MAX_DIMMS_IN_CHANNEL; Dimm++) {
+      DimmOut = &ChannelOut->Dimm[Dimm];
+      if (DimmOut->Status == DIMM_PRESENT) {
+        DimmOut->Status     = DIMM_DISABLED;
+        DimmOut->RankInDIMM = 0;
+        if (!SkipDimmCapacity) {
+          DimmOut->DimmCapacity = 0;
+        }
+      }
+    }
+  }
+}
+
+/**
+  Convert the given frequency and reference clock to a clock ratio.
+
+  @param[in] MrcData   - Pointer to MRC global data.
+  @param[in] Frequency - The memory frequency.
+  @param[in] RefClk    - The memory reference clock.
+  @param[in] BClk      - The base system reference clock.
+
+  @retval Returns the memory clock ratio.
+**/
+MrcClockRatio
+MrcFrequencyToRatio (
+  IN MrcParameters *const  MrcData,
+  IN const MrcFrequency    Frequency,
+  IN const MrcRefClkSelect RefClk,
+  IN const MrcBClkRef      BClk
+  )
+{
+  U64 Value;
+  U64 FreqValue;
+  U32 RefClkValue;
+  U32 BClkValue;
+
+  BClkValue   = (BClk == 0) ? (BCLK_DEFAULT / 100000) : (BClk / 100000);
+  RefClkValue = (RefClk == MRC_REF_CLOCK_100) ? 200000 : 266667;
+  FreqValue   = MrcOemMemoryMultiplyU64ByU32 (Frequency, 1000000000ULL);
+  Value       = MrcOemMemoryDivideU64ByU64 (FreqValue, (RefClkValue * BClkValue));
+  Value       = ((U32) Value + 500) / 1000;
+  return ((MrcClockRatio) Value);
+}
+
+/**
+  @brief
+  Convert the given ratio and reference clocks to a memory frequency.
+
+  @param[in] MrcData - Pointer to MRC global data.
+  @param[in] Ratio   - The memory ratio.
+  @param[in] RefClk  - The memory reference clock.
+  @param[in] BClk    - The base system reference clock.
+
+  @retval Returns the memory frequency.
+**/
+MrcFrequency
+MrcRatioToFrequency (
+  IN MrcParameters *const  MrcData,
+  IN const MrcClockRatio   Ratio,
+  IN const MrcRefClkSelect RefClk,
+  IN const MrcBClkRef      BClk
+  )
+{
+  U64 Value;
+  U32 BClkValue;
+  U32 RefClkValue;
+
+  BClkValue   = (BClk == 0) ? BCLK_DEFAULT : BClk;
+  RefClkValue = (RefClk == MRC_REF_CLOCK_100) ? 200000000 : 266666667;
+  Value       = MrcOemMemoryMultiplyU64ByU32 (RefClkValue, Ratio * BClkValue);
+  Value      += 50000000000000ULL;
+  Value       = MrcOemMemoryDivideU64ByU64 (Value, 100000000000000ULL);
+  return ((MrcFrequency) Value);
+}
+
+/**
+  Convert the given ratio and reference clocks to a memory clock. 
+
+  @param[in] Ratio  - The memory ratio.
+  @param[in] RefClk - The memory reference clock.
+  @param[in] BClk   - The base system reference clock.
+
+  @retval Returns the memory clock in femtoseconds.
+**/
+U32
+MrcRatioToClock (
+  IN const MrcClockRatio   Ratio,
+  IN const MrcRefClkSelect RefClk,
+  IN const MrcBClkRef      BClk
+  )
+{
+  U32 BClkValue;
+  U32 RefClkValue;
+  U32 Factor;
+  U64 Value;
+
+  BClkValue   = (BClk == 0) ? 100000000UL : BClk;
+  Factor      = BClkValue / 100000UL;
+  RefClkValue = (RefClk == MRC_REF_CLOCK_100) ? 1000000000UL : 1333333333UL;
+  Value       = MrcOemMemoryMultiplyU64ByU32 (Factor, RefClkValue);
+  Value       = MrcOemMemoryMultiplyU64ByU32 (Value, Ratio);
+  return ((Value == 0) ? 0 : (U32) MrcOemMemoryDivideU64ByU64 (10000000000000000000ULL, Value));
+}
+
+/**
+  This function return the DIMM number according to the rank number.
+
+  @param[in] Rank - The requested rank.
+
+  @retval The DIMM number.
+**/
+U8
+MrcGetDimmFromRank (
+  IN const U8 Rank
+  )
+{
+  U8  Dimm;
+
+  if (Rank == rRank0 || Rank == rRank1) {
+    Dimm = dDIMM0;
+  } else {
+    Dimm = dDIMM1;
+  }
+
+  return Dimm;
+}
+
+/**
+  This function sets the memory frequency.
+
+  @param[in] MrcData - Include all MRC global data.
+
+  @retval mrcSuccess on success, mrcFrequencyError on error.
+**/
+MrcStatus
+McFrequencySet (
+  IN MrcParameters *const MrcData
+  )
+{
+  const MrcDebug                *Debug;
+  const MrcInput                *Inputs;
+  MrcOutput                     *Outputs;
+  MrcFrequency                  NewFrequency;
+  MrcClockRatio                 Ratio;
+  MrcRefClkSelect               RefClk;
+  PCU_CR_MC_BIOS_REQ_PCU_STRUCT McBiosReq;
+  U32                           MemoryClock;
+#ifdef MRC_DEBUG_PRINT
+  U8                            Channel;
+#endif // MRC_DEBUG_PRINT
+  U32                           Time;
+
+  Inputs  = &MrcData->SysIn.Inputs;
+  Outputs = &MrcData->SysOut.Outputs;
+  Debug   = &Inputs->Debug;
+
+  NewFrequency = MrcGetCurrentMemoryFrequency (MrcData, &MemoryClock, &Ratio, &RefClk);
+  if (NewFrequency != fNoInit) {
+    Outputs->Frequency   = NewFrequency;
+    Outputs->MemoryClock = MemoryClock;
+    Outputs->RefClk      = RefClk;
+    Outputs->Ratio       = Ratio;
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_WARNING, "WARNING: Memory frequency is already initialized to %u\n", Outputs->Frequency);
+    return mrcSuccess;
+  }
+  //
+  // Set the reference clock, ratio and run_busy bit.
+  if (Outputs->BootMode == bmCold) {
+    if ((Inputs->MemoryProfile == USER_PROFILE) && (Inputs->Ratio > 0)) {
+      Outputs->Ratio = Inputs->Ratio;
+    } else {
+      Outputs->Ratio = MrcFrequencyToRatio (MrcData, Outputs->Frequency, Outputs->RefClk, Inputs->BClkFrequency);
+    }
+  }
+  if ((MEMORY_RATIO_MIN > Outputs->Ratio) || (MEMORY_RATIO_MAX < Outputs->Ratio)) {
+    MRC_DEBUG_MSG (
+      Debug,
+      MSG_LEVEL_ERROR,
+      "Invalid DDR ratio of %u specified, range %u - %u\n",
+      Outputs->Ratio,
+      MEMORY_RATIO_MIN,
+      MEMORY_RATIO_MAX
+      );
+  } else {
+    McBiosReq.Data          = 0;
+    McBiosReq.Bits.REQ_DATA = Outputs->Ratio;
+    McBiosReq.Bits.REQ_TYPE = (Outputs->RefClk == MRC_REF_CLOCK_133) ? 0 : 1;
+    McBiosReq.Bits.RUN_BUSY = 1;
+    MrcWriteCR (MrcData, PCU_CR_MC_BIOS_REQ_PCU_REG, McBiosReq.Data);
+
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Attempting value = 0x%x - Pll busy wait ", McBiosReq.Data);
+    Time = 1000 * (U32) MrcGetCpuTime ();
+    while (McBiosReq.Bits.RUN_BUSY && (MrcGetCpuTime () < Time))
+    {
+      McBiosReq.Data = MrcReadCR (MrcData, PCU_CR_MC_BIOS_REQ_PCU_REG);
+    }
+
+    if (McBiosReq.Bits.RUN_BUSY) {
+      MRC_DEBUG_MSG (Debug, MSG_LEVEL_ERROR, "- NOT DONE. DDR frequency Update FAILED!\n");
+      return mrcFrequencyError;
+    } else
+    {
+      MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "- done\n");
+    }
+    //
+    // Wait on RCOMP Done.  Needed to ensure Rcomp completes on warm reset/S3 before restoring dclk_enable.
+    //
+    if (CheckFirstRcompDone (MrcData) != mrcSuccess) {
+      MRC_DEBUG_MSG (Debug, MSG_LEVEL_ERROR, "RComp did not complete before the timeout in McFrequencySet\n");
+      return mrcDeviceBusy;
+    }
+
+#ifdef MRC_DEBUG_PRINT
+    for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+      MRC_DEBUG_MSG (
+        Debug,
+        MSG_LEVEL_NOTE,
+        "Channel %u post PLL RCOMP REG = %Xh\n",
+        Channel,
+        MrcReadCR (
+          MrcData,
+          DDRCKECH0_CR_DDRCRCMDCOMP_REG + ((DDRCKECH1_CR_DDRCRCMDCOMP_REG - DDRCKECH0_CR_DDRCRCMDCOMP_REG) * Channel))
+          );
+    }
+#endif
+    Outputs->Frequency = MrcGetCurrentMemoryFrequency (MrcData, &MemoryClock, &Ratio, &RefClk);
+    MRC_DEBUG_MSG (
+      Debug,
+      (Ratio == Outputs->Ratio) ? MSG_LEVEL_NOTE : MSG_LEVEL_ERROR,
+      "Requested/actual ratio %u/%u, frequency is %u, BClk %uHz RefClk %uMHz, memory clock %u\n",
+      Outputs->Ratio,
+      Ratio,
+      Outputs->Frequency,
+      Inputs->BClkFrequency,
+      (RefClk == MRC_REF_CLOCK_133) ? 133 : 100,
+      MemoryClock);
+    if (Ratio == Outputs->Ratio) {
+      return mrcSuccess;
+    }
+  }
+  return mrcFrequencyError;
+}
+
+/**
+  Returns the extrapolated margin to a fixed # of errors (logT)
+  vrefpass is 10x the first passing margin (with no errors) (10x used for int math)
+  Errors at vrefpass/10+1 = log1
+  Errors at vrefpass/10+2 = logT
+
+  @param[in]      vrefpass      - 10x the first pass margin (w/no errors) (10x used for int match)
+  @param[in]      errLog_1      - Errors at vrefpass/10+1
+  @param[in]      errLog_2      - Errors at vrefpass/10+2
+  @param[in]      errLog_Target - Error target determines extrapolation vs interpolation
+  @param[in, out] *berStats     - Used to track interpolation vs extrapolation or if the slope is non-monotonic.
+                                  NOTE: target would be Interpolation only
+
+  @retval Interpolated/Extrapolated vref with the scale increased by 10.
+**/
+U32
+interpolateVref (
+  IN     U32  vrefpass,
+  IN     U32  errLog_1,
+  IN     U32  errLog_2,
+  IN     U32  errLog_Target,
+  IN OUT U32  *berStats
+  )
+{
+  U32 vref;
+  U32 slope;
+  U32 ErrLogDiff;
+
+  ErrLogDiff = errLog_2 - errLog_1;
+  if (errLog_2 <= errLog_1) {
+    berStats[3] += 1;                 // non-monotonic case
+    return (vrefpass * 10 + 10);
+  } else if (errLog_2 < errLog_Target) {
+    berStats[2] += 1;                 // error target above errLog_2 -> extrapolation
+  } else if (errLog_1 <= errLog_Target) {
+    berStats[1] += 1;                 // error target between errLog_1 and errLog_2 -> interpolation
+  } else {
+    berStats[0] += 1;                 // error target below errLog_1 -> extrapolation
+  }
+
+  //
+  //extrapolate above errLog_2, max extrapolation is 1 tick (10)
+  //
+  if (errLog_2 < errLog_Target) {
+    vref =  vrefpass * 10 + 20 + MIN (10, (10 * (errLog_Target - errLog_2)) / (ErrLogDiff));
+  } else if ( (errLog_1 <= errLog_Target) && (errLog_Target <= errLog_2) && (ErrLogDiff != 0)) {
+    vref =  vrefpass * 10 + 10 + (10 * (errLog_Target - errLog_1)) / (ErrLogDiff);  //interpolate
+  } else {
+    //
+    //extrapolate below errLog_1
+    //
+    slope = (ErrLogDiff) > errLog_1 ? (ErrLogDiff) : errLog_1;
+    if (slope != 0) {
+      vref = vrefpass * 10 + (10 * errLog_Target) / slope;
+    } else {
+      vref = 0;
+    }
+  }
+
+  return vref;  //returns a (vref * 10) interpolation/extrapolation
+};
+
+/**
+  This function swaps a subfield, within a 32 bit integer value with the specified value.
+
+  @param[in] CurrentValue - 32 bit input value.
+  @param[in] NewValue     - 32 bit New value.
+  @param[in] Start        - Subfield start bit.
+  @param[in] Length       - Subfield length in bits/
+
+  @retval The updated 32 bit value.
+**/
+U32
+MrcBitSwap (
+  IN U32       CurrentValue,
+  IN const U32 NewValue,
+  IN const U8  Start,
+  IN const U8  Length
+  )
+{
+  U32 mask;
+
+  //
+  // Do bitwise replacement:
+  //
+  mask = (MRC_BIT0 << Length) - 1;
+  CurrentValue &= ~(mask << Start);
+  CurrentValue |= ((NewValue & mask) << Start);
+
+  return CurrentValue;
+}
+
+/**
+  This function returns the maximim Rx margin for a given Channel, Rank(s), and byte.
+
+  @param[in] MrcData   - Pointer to MRC global data.
+  @param[in] Channel   - Channel to calculate max Rx margin.
+  @param[in] RankRx    - Rank index.  0xFF causes all ranks to be considered.
+  @param[in] byte      - Byte to check.
+  @param[in] sign      - Sign of the margins (0 - negative/min, 1 - positive/max).
+  @param[in] MaxMargin - Current max margin value.
+
+  @retval The max Rx margin, either MaxMargin or value from stored margins.
+**/
+U8
+MrcCalcMaxRxMargin (
+  IN MrcParameters  *const MrcData,
+  IN const U8              Channel,
+  IN const U8              RankRx,
+  IN const U8              byte,
+  IN const U8              sign,
+  IN U8                    MaxMargin
+  )
+{
+  MrcChannelOut *ChannelOut;
+  U8            RxDqsP;
+  U8            RxDqsN;
+  U8            Start;
+  U8            Stop;
+  U8            rank;
+
+  //
+  // Check for saturation on Rx Timing
+  //
+  if (RankRx == 0xFF) {
+    //
+    // If desired for all ranks
+    //
+    Start = 0;              // Start in rank 0
+    Stop = 4;               // Up to 4 ranks
+  } else {
+    Start = RankRx;
+    Stop  = RankRx + 1;
+  }
+
+  ChannelOut = &MrcData->SysOut.Outputs.Controller[0].Channel[Channel];
+  for (rank = Start; rank < Stop; rank++) {
+    if (MrcRankInChannelExist (MrcData, rank, Channel)) {
+      RxDqsP = ChannelOut->RxDqsP[rank][byte];
+      RxDqsN = ChannelOut->RxDqsN[rank][byte];
+
+      if (sign == 0) {
+        if (MaxMargin > RxDqsP) {
+          MaxMargin = RxDqsP;
+        }
+
+        if (MaxMargin > RxDqsN) {
+          MaxMargin = RxDqsN;
+        }
+      } else {
+        if (MaxMargin > 63 - RxDqsP) {
+          MaxMargin = 63 - RxDqsP;
+        }
+
+        if (MaxMargin > 63 - RxDqsN) {
+          MaxMargin = 63 - RxDqsN;
+        }
+      }
+    }
+  }
+
+  return MaxMargin;
+}
+
+/**
+  This function determines if a bit lane[0-7] has seen a pass and a fail in each byte for all channels populated.
+
+  @param[in] MrcData   - Pointer to MRC global data.
+  @param[in] chBitmask - Bit mask of channels to consider.
+  @param[in] OnePass   - Array of Bit masks marking DQ lanes has had a passing value.
+  @param[in] OneFail   - Array of Bit masks marking DQ lanes has had a failing value.
+
+  @retval The AND result of each Channel/byte for OnePass and OneFail.
+**/
+U8
+MrcAndBytes (
+  IN MrcParameters *const MrcData,
+  IN const U8             chBitmask,
+  IN U8                   OnePass[MAX_CHANNEL][MAX_SDRAM_IN_DIMM],
+  IN U8                   OneFail[MAX_CHANNEL][MAX_SDRAM_IN_DIMM]
+  )
+{
+  U8  Res;
+  U8  Channel;
+  U8  byte;
+
+  Res = 0xFF;
+  for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+    if (((MRC_BIT0 << Channel) & chBitmask) == 0) {
+      continue;
+    }
+
+    for (byte = 0; byte < MrcData->SysOut.Outputs.SdramCount; byte++) {
+      Res &= OnePass[Channel][byte];
+      Res &= OneFail[Channel][byte];
+    }
+  }
+
+  return Res;
+}
+
+/**
+  This function Finds the margin for all channels/all bits. The margin sweep is a parameterized
+  Assume REUT test has already been fully setup to run
+  This will unscale the results such that future tests start at the correct point
+  Uses ChangeMargin function to handle a variety cases (Timing, Voltage, Fan, etc.)
+
+  @param[in]     MrcData    - Include all MRC global data.
+  @param[in]     chBitMask  - Channel BIT mask for Channel(s) to work on
+  @param[in]     Rank       - Rank to work on
+  @param[in,out] marginbit  - used as the return data ( real margin measurement, no 10x)
+                              marginbit[ch,byte,bit,sign] = abs(Margin)
+                              Note: If param == RdTBit/RdVBit/WrVBit, marginbit is also the starting point
+  @param[in,out] marginbyte - provides the starting point on a per byte basis (still 10x)
+  @param[in]     param      - defines the margin type
+  @param[in]     mode       - allows for different types of modes for margining
+                              {Bit0: PhLock (keep all bytes within in ch in phase),
+                               Bit1: Ch2Ch Data out of phase (LFSR seed)
+                               Bits 15:2: Reserved}
+  @param[in]     MaxMargin  - Default Maximum margin
+
+  @retval mrcSuccess if successful, otherwise it returns an error status.
+**/
+MrcStatus
+MrcGetMarginBit (
+  IN     MrcParameters *const MrcData,
+  IN     U8                   chBitMask,
+  IN     U8                   Rank,
+  IN OUT U32                  marginbit[MAX_CHANNEL][MAX_SDRAM_IN_DIMM][MAX_BITS][MAX_EDGES],
+  IN OUT U32                  marginbyte[MAX_CHANNEL][MAX_SDRAM_IN_DIMM][MAX_EDGES],
+  IN     U8                   param,
+  IN     U16                  mode,
+  IN     U8                   MaxMargin
+  )
+{
+  const MrcDebug  *Debug;
+  MrcOutput       *Outputs;
+  MrcStatus       Status;
+  U8              Channel;
+  U8              Byte;
+  U8              bit;
+  U8              sign;
+  S8              realSign;
+  U8              pbyte;
+  BOOL            PerCh;
+  U8              PerBit;
+  U8              SeqLC[4];
+  U8              Points2D;
+  U8              DoneMask;
+  U8              ByteMax;
+  U8              SkipWait;
+  U8              chPass;
+  U8              chFail;
+  U8              NoECC;
+  U8              AllFail;
+  // Set to 1 after ch/byte/bit has a passing point
+  U8              OnePass[MAX_CHANNEL][MAX_SDRAM_IN_DIMM];
+  // Set to 1 after ch/byte/bit has a failing point
+  U8              OneFail[MAX_CHANNEL][MAX_SDRAM_IN_DIMM];
+  U8              ErrByte;
+  U8              ErrECC;
+  U32             ErrLower;
+  U32             ErrUpper;
+  U8              MinMargin;
+  U32             value0;
+  U32             value1;
+  U32             v0;
+  U32             CMargin[MAX_CHANNEL][MAX_SDRAM_IN_DIMM][MAX_BITS];    // Current Margin Point Testing
+  U32             ABMargin[MAX_CHANNEL][MAX_SDRAM_IN_DIMM];             // Average Byte Margin
+  U32             MinTested[MAX_CHANNEL][MAX_SDRAM_IN_DIMM][MAX_BITS];  // Min Margin Point Tested
+  U8              PrintPetByte;
+  S8              RdTAdjust;
+  U32             Offset;
+  U32             BitTimePerBit;
+  U8              BitMask;
+  MCDFXS_CR_REUT_GLOBAL_CTL_MCMAIN_STRUCT ReutGlobalCtl;
+
+  Status    = mrcSuccess;
+  SkipWait  = 0;
+  NoECC     = 0;
+  Debug     = &MrcData->SysIn.Inputs.Debug;
+  Outputs   = &MrcData->SysOut.Outputs;
+
+  //
+  // Define Constants
+  //
+  ByteMax = MaxMargin;
+
+  //
+  // Define the correct loopcount for test
+  //
+  if (Outputs->DQPat == SegmentWDB) {
+    SeqLC[0] = Outputs->DQPatLC;
+    SeqLC[1] = Outputs->DQPatLC;
+    SeqLC[2] = Outputs->DQPatLC + 4;
+    SeqLC[3] = Outputs->DQPatLC + 2;
+  } else {
+    SeqLC[0] = 1;
+    SeqLC[1] = 1;
+    SeqLC[2] = 1;
+    SeqLC[3] = 1;
+  }
+  //
+  // How many points to test
+  //
+  Points2D = 1 + (param / 16);
+
+  //
+  // Define PerByte param for PerBit cases
+  //
+  if (param == RdTBit) {
+    pbyte   = RdT;
+    PerBit  = 1;
+  } else if (param == WrTBit) {
+    pbyte   = WrT;
+    PerBit  = 1;
+  } else if (param == RdVBit) {
+    pbyte   = RdV;
+    PerBit  = 1;
+  } else {
+    pbyte   = 0;
+    PerBit  = 0;
+  }
+  //
+  // Print results PerBit or PerByte
+  //
+  PrintPetByte = (param == RdT || param == WrT || param == RdV);
+  //
+  // Created for debug purpose
+  // Are we using DIMM Vref?  If so, need to use the same Vref across all bytes
+  //
+  PerCh = ((param == WrFan2) || (param == WrFan3) || (param == WrV) || (mode & 0x1)) && (PerBit == 0);
+
+  //
+  // Get Average Byte back to real margin numbers
+  //
+  for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+    if (chBitMask & (MRC_BIT0 << Channel)) {
+      for (Byte = 0; Byte < Outputs->SdramCount; Byte++) {
+        ABMargin[Channel][Byte] = (marginbyte[Channel][Byte][0] + marginbyte[Channel][Byte][1]) / 20;
+      }
+    }
+  }
+  //
+  // Find Left and Right Edges
+  //
+  for (sign = 0; sign < 2; sign++) {
+    realSign = (S8) ((2 * sign) - 1);
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\n+--MrcGetMarginBit, rsign = %d\n", realSign);
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, (PrintPetByte) ? "\nMargin\tBits\n" : "");
+
+    //
+    // Initialize variables
+    //
+    DoneMask = 0xFF;
+    for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+      if (!(chBitMask & (MRC_BIT0 << Channel))) {
+        continue; // This channel is not populated
+      }
+
+      MinMargin = 0x7F; // Start with a huge unsigned number
+      for (Byte = 0; Byte < Outputs->SdramCount; Byte++) {
+        //
+        // Init arrays to 0
+        //
+        OnePass[Channel][Byte] = OneFail[Channel][Byte] = 0;
+
+        //
+        // Find MaxMargin for this byte
+        //
+        ByteMax = MaxMargin;
+        if (param == RdT) {
+          ByteMax = MrcCalcMaxRxMargin (MrcData, Channel, Rank, Byte, sign, MaxMargin);
+        }
+
+        CMargin[Channel][Byte][0] = ABMargin[Channel][Byte] - 2; //start from a definite pass for all bytes/bits
+
+        if ((param == RdTBit) || (param == WrTBit)) {
+          // Special case for PerBit Timing
+          v0 = realSign * (CMargin[Channel][Byte][0] + 0); // Push into failing region
+          Status = ChangeMargin (MrcData, pbyte, v0, 0, 0, Channel, Rank, Byte, 0, 0, 0, MrcRegFileStart);
+        } else if (param == RdVBit) {
+          // Special case for PerBit Voltage
+          v0 = realSign * (CMargin[Channel][Byte][0] + 4); // Push into failing region
+          Status = ChangeMargin (MrcData, pbyte, v0, 0, 0, Channel, Rank, Byte, 0, 0, 0, MrcRegFileStart);
+        }
+        //
+        // Update the variables for PerBit tracking
+        //
+        if (PerBit) {
+          for (bit = 0; bit < MAX_BITS; bit++) {
+            CMargin[Channel][Byte][bit] = marginbit[Channel][Byte][bit][sign];
+            //
+            // Double check saturation limits
+            //
+            if (CMargin[Channel][Byte][bit] > MaxMargin) {
+              CMargin[Channel][Byte][bit] = MaxMargin;
+            }
+          }
+        }
+        //
+        // Find MinMargin to start and set marginbyte for the PerCh case
+        //
+        if (PerCh) {
+          if (CMargin[Channel][Byte][0] < MinMargin) {
+            MinMargin = (U8) CMargin[Channel][Byte][0];
+          }
+
+          CMargin[Channel][Byte][0] = MinMargin;
+        }
+
+        for (bit = 0; bit < MAX_BITS; bit++) {
+          MinTested[Channel][Byte][bit]       = CMargin[Channel][Byte][bit * PerBit];
+          marginbit[Channel][Byte][bit][sign] = CMargin[Channel][Byte][bit * PerBit];
+        }
+      }
+    } // END OF CHANNEL LOOP
+
+    //##########################################################
+    // Search algorithm:
+    // Walk up until everybody fails.  Then Walk down until everybody passes.
+    //##########################################################
+    while (MrcAndBytes (MrcData, chBitMask, OnePass, OneFail) != DoneMask) {
+      //
+      // Walk through all 2D points
+      ReutGlobalCtl.Data = 0;
+      ReutGlobalCtl.Bits.Global_Clear_Errors = 1;
+      MrcWriteCR8 (MrcData, MCDFXS_CR_REUT_GLOBAL_CTL_MCMAIN_REG, (U8) ReutGlobalCtl.Data); // Clear errors
+      for (value1 = 0; value1 < Points2D; value1++) {
+        //
+        // Set Margin level
+        //
+        for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+          if (!(chBitMask & (MRC_BIT0 << Channel))) {
+            continue;
+          }
+
+          SkipWait = (chBitMask >> (Channel + 1)); // Skip if there are more channels
+          for (Byte = 0; Byte < Outputs->SdramCount; Byte++) {
+            if (PerBit) {
+              value0 = 0;
+              for (bit = 0; bit < MAX_BITS; bit++) {
+                //
+                // Per Bit Deskew.  Note: When (sign==1), then CMargin is off by 1.
+                // Suppose RdTBit and Right/Left Edge Last Pass @ CMargin = 12, 9
+                //    Real Right Edge = (15-12)=3,  Right Edge Moved By (8-3)=5
+                //    Real Left Edge = 9,           Left Edge Moved By (9-8) =1
+                // Center Movement = (5-1)/2 = +2
+                // To get correct answer, need to add +1 to CMargin for Right Edge
+                //   ie: Center Moverment = (12+1-9)/2 = +2
+                // This error will be corrected at the edge of the function
+                // For RdTBit we shift data not strobe.Since we shift the opposite signal, sign is inverted
+                //
+                if ((param == RdTBit && sign) || ((param != RdTBit) && (sign == 0))) {
+                  v0 = (MaxMargin - CMargin[Channel][Byte][bit]);
+                } else {
+                  v0 = CMargin[Channel][Byte][bit];
+                }
+
+                if (v0 > MaxMargin) {
+                  v0 = MaxMargin;
+                }
+                value0 |= (v0 << (4 * bit));
+              }
+            } else {
+              value0 = realSign * CMargin[Channel][Byte][0];
+            }
+            //
+            // EnMultiCast=0, ch,rank,byte,0, UpdateHost=0, SkipWait
+            //
+            Status = ChangeMargin (
+                      MrcData,
+                      param,
+                      value0,
+                      value1,
+                      0,
+                      Channel,
+                      Rank,
+                      Byte,
+                      0,
+                      0,
+                      SkipWait,
+                      MrcRegFileStart
+                      );
+          }
+        }
+        //
+        // Run Test
+        //
+        RunIOTest (MrcData, chBitMask, Outputs->DQPat, SeqLC, (value1 == 0), mode);
+
+        //
+        // Check if we have already failed and can stop running
+        //
+        if (value1 < (U32) (Points2D - 1)) {
+          AllFail = 1;
+          NoECC   = (Outputs->EccSupport == FALSE);
+          for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+            if (!(chBitMask & (MRC_BIT0 << Channel))) {
+              continue;
+            }
+            Offset = MCHBAR_CH0_CR_REUT_CH_ERR_DATA_STATUS_REG +
+              (Channel * (MCHBAR_CH1_CR_REUT_CH_ERR_DATA_STATUS_REG - MCHBAR_CH0_CR_REUT_CH_ERR_DATA_STATUS_REG));
+            AllFail &= (MrcReadCR (MrcData, Offset) == 0xFFFFFFFF);
+            AllFail &= (MrcReadCR (MrcData, Offset + 4) == 0xFFFFFFFF);
+            Offset = MCHBAR_CH0_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_REG +
+              (
+                Channel *
+                  (
+                    MCHBAR_CH1_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_REG -
+                    MCHBAR_CH0_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_REG
+                  )
+              );
+            AllFail &= (NoECC || ((U8) MrcReadCR (MrcData, Offset) == 0xFF));
+          }
+
+          if (AllFail) {
+            break;  // break if any error
+          }
+        }
+      }
+      //
+      // Collect results and Update variables for next point to test
+      //
+      for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+        if (!(chBitMask & (MRC_BIT0 << Channel))) {
+          continue;
+        }
+
+        // Read Error Results (Assume all reads are 32 bit access
+        Offset = MCHBAR_CH0_CR_REUT_CH_ERR_DATA_STATUS_REG +
+          (Channel * (MCHBAR_CH1_CR_REUT_CH_ERR_DATA_STATUS_REG - MCHBAR_CH0_CR_REUT_CH_ERR_DATA_STATUS_REG));
+        ErrLower = MrcReadCR (MrcData, Offset); // Lower 32 bits
+        ErrUpper = MrcReadCR (MrcData, Offset + 4); // Upper 32 bits
+        Offset = MCHBAR_CH0_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_REG +
+          (
+            Channel *
+              (
+                MCHBAR_CH1_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_REG -
+                MCHBAR_CH0_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_REG
+              )
+          );
+        ErrECC = (U8) MrcReadCR (MrcData, Offset);
+
+        chPass = 0xFF;
+        chFail = 0xFF;
+
+        for (Byte = 0; Byte < Outputs->SdramCount; Byte++) {
+          //
+          // Extract Errors
+          //
+          if (Byte < 4) {
+            ErrByte = (U8) (ErrLower >> (8 * Byte));
+          } else if (Byte < 8) {
+            ErrByte = (U8) (ErrUpper >> (8 * (Byte - 4)));
+          } else {
+            ErrByte = ErrECC;
+          }
+
+          ErrByte &= DoneMask;
+#ifdef MRC_DEBUG_PRINT
+          if (param == WrTBit) {
+            Offset = DDRDATA0CH0_CR_TXPERBITRANK0_REG +
+              ((DDRDATA0CH1_CR_TXPERBITRANK0_REG - DDRDATA0CH0_CR_TXPERBITRANK0_REG) * Channel) +
+              ((DDRDATA0CH0_CR_TXPERBITRANK1_REG - DDRDATA0CH0_CR_TXPERBITRANK0_REG) * Rank)+
+              ((DDRDATA1CH0_CR_TXPERBITRANK0_REG - DDRDATA0CH0_CR_TXPERBITRANK0_REG) * Byte);
+            MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "0x%08X", MrcReadCR (MrcData, Offset));
+          } else if (param == RdTBit) {
+            Offset = DDRDATA0CH0_CR_RXPERBITRANK0_REG +
+              ((DDRDATA0CH1_CR_RXPERBITRANK0_REG - DDRDATA0CH0_CR_RXPERBITRANK0_REG) * Channel) +
+              ((DDRDATA0CH0_CR_RXPERBITRANK1_REG - DDRDATA0CH0_CR_RXPERBITRANK0_REG) * Rank)+
+              ((DDRDATA1CH0_CR_RXPERBITRANK0_REG - DDRDATA0CH0_CR_RXPERBITRANK0_REG) * Byte);
+            MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "0x%08X", MrcReadCR (MrcData, Offset));
+          } else if (param == RdVBit) {
+            Offset = DDRDATA0CH0_CR_RXOFFSETVDQ_REG +
+              ((DDRDATA0CH1_CR_RXOFFSETVDQ_REG - DDRDATA0CH0_CR_RXOFFSETVDQ_REG) * Channel) +
+              ((DDRDATA1CH0_CR_RXOFFSETVDQ_REG - DDRDATA0CH0_CR_RXOFFSETVDQ_REG) * Byte);
+            MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "0x%08X", MrcReadCR (MrcData, Offset));
+          } else if (param == WrT || param == RdT || param == RdV) {
+            MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "% 2d", CMargin[Channel][Byte][0]);
+          }
+#endif // MRC_DEBUG_PRINT
+
+          for (bit = 0; bit < MAX_BITS; bit++) {
+            BitMask       = MRC_BIT0 << bit;
+            BitTimePerBit = bit * PerBit;
+            //
+            // Skip if this Bit Group is done
+            //
+            if (OnePass[Channel][Byte] & OneFail[Channel][Byte] & (BitMask)) {
+              MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "   $");
+              continue;
+            }
+            //
+            // Update variables for fail
+            //
+            if (ErrByte & (BitMask)) {
+              OneFail[Channel][Byte] |= (BitMask);
+
+              MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "   #");
+
+              //
+              // Handle Speckles
+              //
+              if (marginbit[Channel][Byte][bit][sign] >= CMargin[Channel][Byte][BitTimePerBit]) {
+                marginbit[Channel][Byte][bit][sign] = CMargin[Channel][Byte][BitTimePerBit] - 1;
+                OnePass[Channel][Byte] &= ~(BitMask);
+              }
+              //
+              // Update variables for pass
+              //
+            } else {
+              OnePass[Channel][Byte] |= (BitMask);
+
+              MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "   .");
+
+              if (marginbit[Channel][Byte][bit][sign] < CMargin[Channel][Byte][BitTimePerBit]) {
+                marginbit[Channel][Byte][bit][sign] = CMargin[Channel][Byte][BitTimePerBit];
+              }
+            }
+          }
+          //
+          // FIND MAX Saturation limit
+          //
+          ByteMax = MaxMargin;
+          if (param == RdT) {
+            ByteMax = MrcCalcMaxRxMargin (MrcData, Channel, Rank, Byte, sign, MaxMargin);
+
+          }
+          //
+          // HANDLE Saturation
+          //
+          if (PerBit) {
+            for (bit = 0; bit < MAX_BITS; bit++) {
+              BitMask = MRC_BIT0 << bit;
+              if (CMargin[Channel][Byte][bit] >= ByteMax) {
+                OneFail[Channel][Byte] |= (BitMask);
+              }
+
+              if (CMargin[Channel][Byte][bit] == 0) {
+                OnePass[Channel][Byte] |= (BitMask);
+              }
+            }
+          } else {
+            if (CMargin[Channel][Byte][0] >= ByteMax) {
+              OneFail[Channel][Byte] = DoneMask;
+            }
+
+            if (CMargin[Channel][Byte][0] == 0) {
+              OnePass[Channel][Byte] = DoneMask;
+            }
+          }
+          //
+          // DECIDE WHAT TO TEST NEXT
+          // If PerByte, Do this within the for byte loop
+          //
+          chPass &= OnePass[Channel][Byte];
+          chFail &= OneFail[Channel][Byte];
+
+          if (PerCh == FALSE) {
+            if (PerBit) {
+              for (bit = 0; bit < MAX_BITS; bit++) {
+                BitMask = MRC_BIT0 << bit;
+                //
+                // Skip if this Bit Group is done
+                //
+                if (OnePass[Channel][Byte] & OneFail[Channel][Byte] & (BitMask)) {
+                  continue;
+                }
+
+                if ((OneFail[Channel][Byte] & BitMask) == 0) {
+                  CMargin[Channel][Byte][bit] += 1;
+                } else if ((OnePass[Channel][Byte] & BitMask) == 0) {
+                  MinTested[Channel][Byte][bit] -= 1;
+                  CMargin[Channel][Byte][bit] = MinTested[Channel][Byte][bit];
+                } else {
+                  MRC_DEBUG_MSG (Debug, MSG_LEVEL_WARNING, "WARNING! Can't have both: OnePass and OneFail Not Done\n");
+                }
+              }
+            } else {
+              //
+              // PerCh
+              // Skip if this Byte Group is done
+              //
+              if ((OnePass[Channel][Byte] & OneFail[Channel][Byte]) == DoneMask) {
+                MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, " ");
+                continue;
+              }
+
+              if (OneFail[Channel][Byte] != DoneMask) {
+                CMargin[Channel][Byte][0] += 1;
+              } else if (OnePass[Channel][Byte] != DoneMask) {
+                MinTested[Channel][Byte][0] -= 1;
+                CMargin[Channel][Byte][0] = MinTested[Channel][Byte][0];
+              }
+            }
+          }
+
+          MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, " ");
+        }
+        //
+        // END OF BYTE LOOP
+        // DECIDE WHAT TO TEST NEXT
+        // If PerCh, Do this within the for ch loop
+        //
+        if (PerCh == TRUE) {
+          if ((chPass & chFail) == DoneMask) {
+            continue;
+          }
+
+          if (chFail != DoneMask) {
+            CMargin[Channel][0][0] += 1;
+          } else {
+            MinTested[Channel][0][0] -= 1;
+            CMargin[Channel][0][0] = MinTested[Channel][0][0];
+          }
+          //
+          // All bytes must use the same margin point
+          //
+          for (Byte = 0; Byte < Outputs->SdramCount; Byte++) {
+            CMargin[Channel][Byte][0] = CMargin[Channel][0][0];
+          }
+        }
+      }
+      //
+      // END OF CHANNEL LOOP
+      //
+      MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\n");
+    }
+    //
+    // END OF WHILE LOOP
+    // Update MarginByte to have the correct result
+    //
+    if (PerBit == 0) {
+      for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+        if (chBitMask & (MRC_BIT0 << Channel)) {
+
+          for (Byte = 0; Byte < Outputs->SdramCount; Byte++) {
+            MinMargin = 0x7F; // Start with a huge unsigned number
+            for (bit = 0; bit < MAX_BITS; bit++) {
+              if (MinMargin > marginbit[Channel][Byte][bit][sign]) {
+                MinMargin = (U8) marginbit[Channel][Byte][bit][sign];
+              }
+            }
+
+            marginbyte[Channel][Byte][sign] = MinMargin * 10;
+            //
+            // MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE,"+--marginbyte = MinMargin*10 = %d\n", MinMargin*10);
+            //
+          }
+        }
+      }
+    } else {
+      //
+      // Bit Margins
+      //
+      for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+        if (!(chBitMask & (1 << Channel))) {
+          continue;
+        }
+
+        for (Byte = 0; Byte < Outputs->SdramCount; Byte++) {
+          for (bit = 0; bit < MAX_BITS; bit++) {
+            if ((param == RdTBit && sign) || ((param != RdTBit) && (sign == 0))) {
+              marginbit[Channel][Byte][bit][sign] = MaxMargin - marginbit[Channel][Byte][bit][sign];
+            }
+          }
+        }
+      }
+      //
+      // Cleanup after test
+      //
+      Status = ChangeMargin (MrcData, pbyte, 0, 0, 1, 0, Rank, 0, 0, 0, 0, MrcRegFileCurrent);
+    }
+  }
+  //
+  // END OF SIGN LOOP
+  // Clean up after step
+  // @todo Restore perBit to last saved value
+  //
+  value0 = (PerBit == 1 ? 0x88888888 : 0);
+  Status = ChangeMargin (MrcData, param, value0, 0, 1, 0, Rank, 0, 0, 0, 0, MrcRegFileCurrent);
+
+  //
+  // Correct for 1 tick error in Per Bit Deskew right edge
+  //
+  RdTAdjust = 1;
+#ifdef MRC_DEBUG_PRINT
+  if (PerBit == 1) {
+    if (param == RdTBit) {
+      RdTAdjust = -1;
+    }
+
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\nGains     ");
+    for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+      if (chBitMask & (MRC_BIT0 << Channel)) {
+
+        for (Byte = 0; Byte < Outputs->SdramCount; Byte++) {
+          for (bit = 0; bit < MAX_BITS; bit++) {
+            MRC_DEBUG_MSG (
+              Debug,
+              MSG_LEVEL_NOTE,
+              " %d %d",
+              ((RdTAdjust) * (8 - marginbit[Channel][Byte][bit][0])),
+              ((RdTAdjust) * (marginbit[Channel][Byte][bit][1] - 8))
+              );
+          }
+
+          MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "           ");
+        }
+      }
+    }
+  } else {
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\nCt");
+
+    for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+      if ((chBitMask & (MRC_BIT0 << Channel))) {
+        for (Byte = 0; Byte < Outputs->SdramCount; Byte++) {
+          for (bit = 0; bit < MAX_BITS; bit++) {
+            MRC_DEBUG_MSG (
+              Debug,
+              MSG_LEVEL_NOTE,
+              "%4d",
+              (S8) (marginbit[Channel][Byte][bit][1] - marginbit[Channel][Byte][bit][0]) / 2
+              );
+          }
+
+          MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "   ");
+        }
+      }
+    }
+  }
+
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\n");
+#endif // MRC_DEBUG_PRINT
+
+  return Status;
+}
+
+/**
+  Assume REUT test has already been fully setup to run
+  Finds the margin for all channels/all bytes
+  The margin sweep is parameterized
+  Uses ChangeMargin function to handle a variety of cases (Timing, Voltage, Fan, etc.)
+  mode allows for different types of modes for margining:
+    mode is {Bit0: PhLock (keep all bytes within in ch in phase),
+             Bit1: Ch2Ch Data out of phase (LFSR seed), Bit 15:2: Reserved}
+  marginByte is used as the starting point for the search (10x the actual margin)
+  marginch returns the results (10x the actual margin)
+  Interior: Search inside marginch limits, enabling multiple calls with different setups
+  To reduce repeatibility noise, the returned margins is actually a BER extrapolation
+
+  @param[in]     MrcData    - The global MrcData
+  @param[in,out] marginByte - Data structure with the latest margin results
+  @param[in]     chBitmask  - Bit mask of present channels
+  @param[in]     Rank       - Rank to change margins for
+  @param[in]     RankRx     - Ranks for Rx margin
+  @param[in]     param      - parameter to get margins for
+  @param[in]     mode       - allows for different types of modes for margining:
+  @param[in]     BMap       - Byte mapping to configure error counter control register
+  @param[in]     EnBER      - Enable BER extrapolation calculations
+  @param[in]     MaxMargin  - Max Margin allowed for the parameter
+  @param[in]     Interior   - Search inside marginch limits, enabling multiple calls with different setups
+  @param[in,out] BERStats   - Bit Error Rate Statistics.
+
+  @retval mrcSuccess if successful, otherwise returns an error status.
+**/
+MrcStatus
+MrcGetBERMarginByte (
+  IN     MrcParameters * const MrcData,
+  IN OUT U32             marginByte[MAX_RESULT_TYPE][MAX_RANK_IN_CHANNEL][MAX_CHANNEL][MAX_SDRAM_IN_DIMM][MAX_EDGES],
+  IN     U8              chBitmask,
+  IN     U8              Rank,
+  IN     U8              RankRx,
+  IN     U8              param,
+  IN     U16             mode,
+  IN     U8              *BMap,
+  IN     U8              EnBER,
+  IN     U8              MaxMargin,
+  IN     U8              Interior,
+  IN OUT U32             *BERStats
+  )
+{
+  const MrcDebug   *Debug;
+  MrcOutput        *Outputs;
+  MrcChannelOut    *ChannelOut;
+  MrcControllerOut *ControllerOut;
+  U32              *MarginByteTemp;
+  MrcStatus        Status;
+  U8               ResultType;
+  U8               sign;
+  S8               rSign;
+  U8               SeqLC[4];
+  U8               Points2D;
+  U8               Channel;
+  U8               byte;
+  U8               chByte;
+  U8               SkipWait;
+  U8               byteMax;
+  U8               Margin;
+  U16              DoneMask;
+  // Set to 1 after ch has 2 passing points
+  U16              TwoPass[MAX_CHANNEL];
+  // Set to 1 after ch has 2 failing points
+  U16              TwoFail[MAX_CHANNEL];
+  U16              res;
+  U16              BitMask;
+  S8               Delta;
+  BOOL             Done;
+  BOOL             allFail;
+  BOOL             PerCh;
+  U32              value0;
+  U32              value1;
+  U32              tmp;
+  U32              ErrCount;
+  U8               LastPassVref[MAX_CHANNEL][MAX_SDRAM_IN_DIMM]; // Last passing Vref
+  U32              InitValue[MAX_CHANNEL][MAX_SDRAM_IN_DIMM];    // Initial value from margin byte
+  U8               MaxTested[MAX_CHANNEL][MAX_SDRAM_IN_DIMM];    // Highest Vref Point Tested
+  U8               MinTested[MAX_CHANNEL][MAX_SDRAM_IN_DIMM];    // Lowest Vref Point Tested
+  // Log8(Error count) at different Vref Points. 32 bit number that is broken in 4 bytes
+  // [LastPass+2, LastPass+1, LastPass, LastPass-1]
+  U32              Errors[MAX_CHANNEL][MAX_SDRAM_IN_DIMM];
+  U32              Offset;
+
+  MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_0_STRUCT                  ReutChErrCounterCtl;
+  MCDFXS_CR_REUT_GLOBAL_CTL_MCMAIN_STRUCT                         ReutGlobalCtl;
+  MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_0_STRUCT               ReutChErrCounterStatus;
+  MCHBAR_CH0_CR_SC_IO_LATENCY_STRUCT                              ScIoLatency;
+
+
+  Status        = mrcSuccess;
+  Debug         = &MrcData->SysIn.Inputs.Debug;
+  Outputs       = &MrcData->SysOut.Outputs;
+  ControllerOut = &Outputs->Controller[0];
+  chByte        = 0;
+  Points2D      = (param / RdFan2) + 1;
+  ResultType    = GetMarginResultType (param);
+
+  //
+  // Are we using DIMM Vref?
+  //
+  PerCh = (param == WrFan2 || param == WrFan3 || param == WrV || ((mode & 1) == 1));   // WrFan not defined
+
+  //MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE,"+--->MrcGetBERMarginByte, Points2D: %d, PerCh: %d --\n", Points2D,PerCh);
+
+  DoneMask = (MRC_BIT0 << Outputs->SdramCount) - 1; // 0x1FF or 0xFF
+
+  if (Outputs->DQPat == SegmentWDB) {
+    SeqLC[0] = Outputs->DQPatLC;
+    SeqLC[1] = Outputs->DQPatLC;
+    SeqLC[2] = Outputs->DQPatLC + 4;
+    SeqLC[3] = Outputs->DQPatLC + 2;
+  } else {
+    SeqLC[0] = 1;
+    SeqLC[1] = 1;
+    SeqLC[2] = 1;
+    SeqLC[3] = 1;
+  }
+  //
+  // Run through margin test
+  //
+  for (sign = 0; sign < 2; sign++) {
+    rSign = (S8) ((2 * sign) - 1);
+    //
+    // MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE,"+--MrcGetBERMarginByte, rsign = %d\n", rSign);
+    //
+    MrcOemMemorySet ((U8 *) TwoPass, 0, sizeof (TwoPass));
+    MrcOemMemorySet ((U8 *) TwoFail, 0, sizeof (TwoFail));
+
+    //
+    // Initialize variables
+    //
+    for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+      if (!((MRC_BIT0 << Channel) & chBitmask)) {
+        TwoPass[Channel] = DoneMask;
+        TwoFail[Channel] = DoneMask;
+        continue;
+      }
+
+      MinTested[Channel][0] = 0x7F;
+      for (byte = 0; byte < Outputs->SdramCount; byte++) {
+        LastPassVref[Channel][byte] = 0x7F; // Start with a huge unsigned numer - 128
+        Errors[Channel][byte] = 0;
+
+        //
+        // Find MaxMargin for this byte
+        //
+        byteMax = MaxMargin;
+        if (param == RdT) {
+          byteMax = MrcCalcMaxRxMargin (MrcData, Channel, RankRx, byte, sign, MaxMargin);
+        }
+        //
+        // Scale MarginResult back to real margin numbers.  Set Max/MinTested
+        //
+        MarginByteTemp  = &marginByte[ResultType][Rank][Channel][byte][sign];
+        *MarginByteTemp = *MarginByteTemp / 10;
+        if (*MarginByteTemp > byteMax) {
+          *MarginByteTemp = byteMax;
+        }
+
+        InitValue[Channel][byte] = *MarginByteTemp;
+
+        //
+        // if Per Ch, find MinMargin to start.  Else set margin for that Byte
+        //
+        if (PerCh == TRUE) {
+          if (*MarginByteTemp < MinTested[Channel][0]) {
+            MaxTested[Channel][0] = (U8) *MarginByteTemp;
+            MinTested[Channel][0] = (U8) *MarginByteTemp;
+          }
+        } else {
+          MaxTested[Channel][byte] = (U8) *MarginByteTemp;
+          MinTested[Channel][byte] = (U8) *MarginByteTemp;
+        }
+        //
+        // Setup REUT Error Counters to count errors per byte lane
+        // Count Errors on a particular Byte Group BITS 8:7 = 10b
+        //
+        ReutChErrCounterCtl.Data = 0;
+        ReutChErrCounterCtl.Bits.Counter_Pointer = BMap[byte];
+        ReutChErrCounterCtl.Bits.Counter_Control = 2;
+        Offset = MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_0_REG +
+          ((MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_0_REG - MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_0_REG) * Channel) +
+          ((MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_1_REG - MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_0_REG) * byte);
+        MrcWriteCR (MrcData, Offset, ReutChErrCounterCtl.Data);
+      }
+      //
+      // Set MarginResult for the PerCh case
+      //
+      if (PerCh == TRUE) {
+        for (byte = 0; byte < Outputs->SdramCount; byte++) {
+          marginByte[ResultType][Rank][Channel][byte][sign] = MinTested[Channel][0];
+        }
+      }
+    }
+    //
+    // Search algorithm:
+    // If start with a passing point, walk to hit 2 failing points
+    //    Return as needed to hit a second passing point
+    // If start with a failing point, walk to hit 2 passing points
+    //    Return as needed to hit a second failing point
+    // Keep testing until all ch/bytes find 2 passes and 2 fails
+    //
+    Done = FALSE;
+    do {
+      //
+      // Walk through all 2D points
+      //
+      ReutGlobalCtl.Data = 0;
+      ReutGlobalCtl.Bits.Global_Clear_Errors = 1;
+      MrcWriteCR (MrcData, MCDFXS_CR_REUT_GLOBAL_CTL_MCMAIN_REG, ReutGlobalCtl.Data); // Clear errors
+      for (value1 = 0; value1 < Points2D; value1++) {
+        //
+        // Set Vref level
+        //
+        for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+          if (!((MRC_BIT0 << Channel) & chBitmask)) {
+            continue;
+          }
+
+          SkipWait = (chBitmask >> (Channel + 1)); // Skip if there are more channels
+          for (byte = 0; byte < Outputs->SdramCount; byte++) {
+            value0 = rSign * marginByte[ResultType][Rank][Channel][byte][sign];
+            //
+            // MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE,"+----->Value0 is %d, Value1 is %d\n", (S32)value0, value1);
+            //
+            Status = ChangeMargin (
+                      MrcData,
+                      param,
+                      value0,
+                      value1,
+                      0,
+                      Channel,
+                      Rank,
+                      byte,
+                      0,
+                      0,
+                      SkipWait,
+                      MrcRegFileStart
+                      );
+            if ((PerCh) && ((mode & 1) == 0)) {
+              //
+              // Only Byte 7 on Channel 1 is needed to update Wr DIMM Vref - Taken care of inside ChangeMargin routine
+              //
+              break;
+            }
+          }
+        }
+        //
+        // Run Test
+        //
+        RunIOTest (MrcData, chBitmask, Outputs->DQPat, SeqLC, (value1 == 0), mode);
+
+        //
+        // What is the idea behind this? What if all byte groups failed?
+        //
+        if (EnBER == 0 && value1 < (U32) (Points2D - 1)) {
+          allFail = TRUE;
+          for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+            if (!((MRC_BIT0 << Channel) & chBitmask)) {
+              continue;
+            }
+            //
+            // Read out per byte error results
+            //
+            Offset = 4 + MCHBAR_CH0_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_REG +
+              ((MCHBAR_CH1_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_REG -
+              MCHBAR_CH0_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_REG) * Channel);
+            res = (U16) MrcReadCR (MrcData, Offset);
+            if ((res & DoneMask) != DoneMask) {
+              allFail = FALSE;
+            }
+          }
+
+          if (allFail == TRUE) {
+            break;
+          }
+        }
+      }
+      //
+      // Collect results and Update variables for next point to test
+      //
+      for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+        if (!((MRC_BIT0 << Channel) & chBitmask)) {
+          continue;
+        }
+
+        for (byte = 0; byte < Outputs->SdramCount; byte++) {
+          BitMask = MRC_BIT0 << byte;
+          //
+          // Skip if this Byte Group is done
+          //
+          if ((TwoPass[Channel] & TwoFail[Channel] & (BitMask)) != 0) {
+            continue;
+          }
+          //
+          // Handle PerCh vs. PerByte variable differences
+          //
+          chByte = (PerCh == TRUE ? 0 : byte);
+
+          //
+          // Read Error Count
+          //
+          Offset = MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_0_REG +
+            ((MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_0_REG - MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_0_REG) * Channel) +
+            ((MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_1_REG - MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_0_REG) * byte);
+          ReutChErrCounterStatus.Data = MrcReadCR (MrcData, Offset);
+          ErrCount = ReutChErrCounterStatus.Bits.Counter_Status;
+          Margin = (U8) marginByte[ResultType][Rank][Channel][byte][sign];
+          Delta = (Margin - LastPassVref[Channel][byte]);
+          //MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE,"+----->channel: %d, Error count:%x.\n", Channel, ErrCount);
+          //MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE,"+----->Margin:%d, LastPassVref:%d, delta:%d. sign:%d\n", Margin, LastPassVref[Channel][byte], (S8) Delta, sign);
+
+          // Update Pass/Fail Variables:
+          //
+          if (ErrCount == 0 && Margin == MaxTested[Channel][chByte]) {
+            //
+            // Passing while walking up
+            //
+            if (Delta < 0) {
+              //
+              // First passing point
+              // @todo: Next line should be changed to return failure. Code should never hang.
+              //
+              MRC_ASSERT (
+                MinTested[Channel][chByte] == MaxTested[Channel][chByte],
+                Debug,
+                "Error: MaxTested < LastPass after first point"
+                );
+              LastPassVref[Channel][byte] = Margin;
+            } else if (Delta == 1) {
+              //
+              // Normal, walk to fail
+              //
+              Errors[Channel][byte]       = MrcBitShift (Errors[Channel][byte], -8 * Delta) & BER_ERROR_MASK;
+              LastPassVref[Channel][byte] = Margin;
+              TwoPass[Channel] |= (BitMask);
+            } else if (Delta == 2) {
+              //
+              // Speckling in response, Consider point as error
+              //
+              Errors[Channel][byte] = MrcBitSwap (Errors[Channel][byte], MrcLog8 (ErrCount), 24, 8);
+              TwoFail[Channel] |= (BitMask);
+            } else {
+              //
+              // @todo: Next line should be changed to return failure. Code should never hang.
+              //
+              MRC_ASSERT (
+                FALSE,
+                Debug,
+                "Error: Tested point twice or Tested >2 above LastPass (Passing while walking up)"
+                );
+            }
+          } else if (ErrCount == 0 && Margin == MinTested[Channel][chByte]) {
+            //
+            // Skip if this byte is already done
+            //
+            if ((TwoPass[Channel] & (BitMask)) != 0) {
+              continue;
+            }
+
+            if (Delta == -1) {
+              //
+              // Finding 2nd pass
+              //
+              Errors[Channel][byte] = MrcBitSwap (Errors[Channel][byte], 0, 0, 8);
+              TwoPass[Channel] |= (BitMask);
+            } else {
+              //
+              // 1st passing point
+              // Don't shift Errors.  Fail points already assumed correct LastPass
+              //
+              LastPassVref[Channel][byte] = Margin;
+              TwoPass[Channel] &= ~(BitMask);
+            }
+          } else if (ErrCount > 0 && Margin == MaxTested[Channel][chByte]) {
+            //
+            // Failing while walking up
+            // @todo: Next line should be changed to return failure. Code should never hang.
+            //
+            MRC_ASSERT (Delta <= 2, Debug, "Error: Tested >2 above LastPass (Failing while walking up)");
+            if (Delta < 2) {
+              //
+              // first failing point
+              //
+              Errors[Channel][byte] = MrcBitSwap (Errors[Channel][byte], MrcLog8 (ErrCount), 16, 8);
+              TwoFail[Channel] &= ~(BitMask);
+            } else if (Delta == 2) {
+              //
+              // 2nd failing point
+              //
+              Errors[Channel][byte] = MrcBitSwap (Errors[Channel][byte], MrcLog8 (ErrCount), 24, 8);
+              TwoFail[Channel] |= (BitMask);
+            }
+          } else if (ErrCount > 0 && Margin == MinTested[Channel][chByte]) {
+            //
+            // Failing while walking down
+            //
+            if (LastPassVref[Channel][byte] < 0xFF && Delta <= 0) {
+              //
+              // Adjust LastPassVref and Error count to be below this failure point.
+              //
+              Errors[Channel][byte]       = MrcBitSwap (Errors[Channel][byte], MrcLog8 (ErrCount), 8 * (Delta + 1), 8);
+              Errors[Channel][byte]       = MrcBitShift (Errors[Channel][byte], 8 * (1 - Delta));
+              LastPassVref[Channel][byte] = Margin - 1;
+            } else {
+              tmp                   = ((Errors[Channel][byte] & 0xFF0000) << 8) + MrcLog8 (ErrCount);
+              Errors[Channel][byte] = MrcBitSwap (Errors[Channel][byte], tmp, 16, 16);
+              //MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE,"Unexpected case for channel: %d, delta: %d.\n", Channel, Delta);
+            }
+
+            if (MinTested[Channel][chByte] < MaxTested[Channel][chByte]) {
+              TwoFail[Channel] |= (BitMask);
+            }
+
+            if (Delta <= 0) {
+              TwoPass[Channel] &= ~(BitMask);
+            }
+          } else {
+            //
+            // @todo: Next line should be changed to return failure. Code should never hang.
+            //
+            MRC_ASSERT (FALSE, Debug, "Error: Testing points other than Max/MinTested");
+          }
+          //
+          // FIND MAX Saturation limit
+          //
+          byteMax = MaxMargin;
+          if (param == RdT) {
+            byteMax = MrcCalcMaxRxMargin (MrcData, Channel, RankRx, byte, sign, MaxMargin);
+          }
+
+          if (Interior && InitValue[Channel][byte] == Margin) {
+            byteMax = Margin;
+          }
+          //
+          // HANDLE MAX Saturation
+          //
+          if (Margin == byteMax) {
+            TwoFail[Channel] |= (BitMask);
+          }
+
+          if (ErrCount == 0 && byteMax == LastPassVref[Channel][byte] && (TwoPass[Channel] & (BitMask)) != 0) {
+            Errors[Channel][byte] = MrcBitSwap (Errors[Channel][byte], 0xFFFE, 16, 16);
+          }
+          //
+          // HANDLE MIN Saturation
+          //
+          if (Margin == 0) {
+            TwoPass[Channel] |= (BitMask);
+            if (ErrCount > 0) {
+              TwoFail[Channel] |= (BitMask);
+              LastPassVref[Channel][byte] = 0;
+              Errors[Channel][byte] = MrcBitSwap (
+                                        Errors[Channel][byte],
+                                        (BER_LOG_TARGET << 8) + BER_LOG_TARGET,
+                                        16,
+                                        16
+                                        );
+            }
+          }
+          //
+          // DECIDE WHAT TO TEST NEXT
+          // If In PerByte, Do this within the for byte loop
+          //
+          if (PerCh == FALSE) {
+            //
+            // Skip if this Byte Group is done
+            //
+            if ((TwoPass[Channel] & TwoFail[Channel] & (BitMask)) != 0) {
+              continue;
+            }
+
+            if (ErrCount == 0) {
+              if ((TwoFail[Channel] & (BitMask)) == 0) {
+                //
+                // Count up to find 2 fails
+                //
+                marginByte[ResultType][Rank][Channel][byte][sign] = ++MaxTested[Channel][chByte];
+              } else {
+                //
+                // Count down to find 2 passes
+                //
+                marginByte[ResultType][Rank][Channel][byte][sign] = --MinTested[Channel][chByte];
+              }
+            } else {
+              if ((TwoPass[Channel] & (BitMask)) == 0) {
+                marginByte[ResultType][Rank][Channel][byte][sign] = --MinTested[Channel][chByte];
+              } else {
+                marginByte[ResultType][Rank][Channel][byte][sign] = ++MaxTested[Channel][chByte];
+              }
+            }
+          }
+        }
+        //
+        // DECIDE WHAT TO TEST NEXT
+        // If In PerCh, Do this within the for ch loop
+        //
+        if (PerCh == TRUE) {
+          if ((TwoPass[Channel] & TwoFail[Channel]) == DoneMask) {
+            continue;
+          }
+
+          if (TwoPass[Channel] != DoneMask) {
+            marginByte[ResultType][Rank][Channel][0][sign] = --MinTested[Channel][chByte];
+          } else {
+            marginByte[ResultType][Rank][Channel][0][sign] = ++MaxTested[Channel][chByte];
+          }
+          //
+          // All bytes must use the same margin point
+          //
+          for (byte = 0; byte < Outputs->SdramCount; byte++) {
+            marginByte[ResultType][Rank][Channel][byte][sign] = marginByte[ResultType][Rank][Channel][0][sign];
+          }
+        }
+      }
+      //
+      // check if we are done
+      //
+      Done = TRUE;
+      for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+        if ((TwoPass[Channel] & DoneMask) != DoneMask || (TwoFail[Channel] & DoneMask) != DoneMask) {
+          Done = FALSE;
+          break;
+        }
+      }
+    } while (Done == FALSE);
+
+    //
+    // Calculate the effective margin
+    // Update MarginResult with extroploated BER Margin
+    //
+    for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+      if (((MRC_BIT0 << Channel) & chBitmask) == 0) {
+        continue;
+      }
+
+      for (byte = 0; byte < Outputs->SdramCount; byte++) {
+        //MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE,"+----->marginByte[Ch %d, Byte%d, Sign %d] is: %d\n", Channel, byte, sign,  marginByte[ResultType][Rank][Channel][byte][sign]);
+        if (EnBER) {
+          marginByte[ResultType][Rank][Channel][byte][sign] = interpolateVref (
+                                                                LastPassVref[Channel][byte],
+                                                                (Errors[Channel][byte] >> 16) & 0xFF,
+                                                                (Errors[Channel][byte] >> 24) & 0xFF,
+                                                                BER_LOG_TARGET,
+                                                                BERStats
+                                                                );
+          // MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE,"+----->BERmarginByte[Ch %d, Byte%d, Sign %d] is: %d\n", Channel, byte, sign,  marginByte[ResultType][Rank][Channel][byte][sign]);
+        } else {
+          marginByte[ResultType][Rank][Channel][byte][sign] = 10 * LastPassVref[Channel][byte];
+          //MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE,"+----->marginByte[Ch %d, Byte%d, Sign %d] is: %d\n", Channel, byte, sign,  marginByte[ResultType][Rank][Channel][byte][sign]);
+        }
+      }
+    }
+  }
+  //
+  // Clean up after step
+  //
+  if (param == RcvEnaX) {
+    for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+      if (((MRC_BIT0 << Channel) & chBitmask) == 0) {
+        continue;
+      }
+      ChannelOut  = &ControllerOut->Channel[Channel];
+      for (byte = 0; byte < Outputs->SdramCount; byte++) {
+        UpdateRxT (MrcData, Channel, Rank, byte, 0xff, 0);
+        Offset = MCHBAR_CH0_CR_SC_IO_LATENCY_REG +
+          ((MCHBAR_CH1_CR_SC_IO_LATENCY_REG - MCHBAR_CH0_CR_SC_IO_LATENCY_REG) * Channel);
+        ScIoLatency.Data           = MrcReadCR (MrcData, Offset);
+        ScIoLatency.Bits.RT_IOCOMP = MCHBAR_CH0_CR_SC_IO_LATENCY_RT_IOCOMP_MAX & ChannelOut->RTIoComp;
+        MrcWriteCR (MrcData, Offset, ScIoLatency.Data);
+      }
+    }
+  }
+  Status = ChangeMargin (MrcData, param, 0, 0, 1, 0, 0, 0, 0, 0, 0, MrcRegFileCurrent);
+  for (byte = 0; byte < Outputs->SdramCount; byte++) {
+    Offset = MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_0_REG +
+      ((MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_1_REG - MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_0_REG) * byte);
+    MrcWriteCrMulticast (MrcData, Offset, 0);
+  }
+
+  return Status;
+}
+
+/**
+  Assume REUT test has already been fully setup to run
+  Finds the margin for all channels/all bytes
+  The margin sweep is parameterized
+  Uses ChangeMargin function to handle a variety of cases (Timing, Voltage, Fan, etc.)
+  mode allows for different types of modes for margining:
+  mode is {Bit0: PhLock (keep all bytes within in ch in phase),
+  Bit1: Ch2Ch Data out of phase (LFSR seed), Bit 15:2: Reserved}
+  marginCh is used as the starting point for the search (10x the actual margin)
+  marginch returns the results (10x the actual margin)
+  Interior: Search inside marginch limits, enabling multiple calls with different setups
+  To reduce repeatibility noise, the returned margins is actually a BER extrapolation
+
+  @param[in]     MrcData   - The global MrcData
+  @param[in,out] marginCh  - Data structure with the latest margin results
+  @param[in]     chBitmask - Bit mask of present channels
+  @param[in]     RankRx    - Ranks for Rx margin
+  @param[in]     Rank      - Rank to change margins for
+  @param[in]     param     - parameter to get margins for
+  @param[in]     mode      - allows for different types of modes for margining:
+  @param[in]     EnBER     - Enable BER extrapolation calculations
+  @param[in]     MaxMargin - Max Margin allowed for the parameter
+  @param[in]     Interior  - Search inside marginch limits, enabling multiple calls with different setups
+  @param[in,out] BERStats  - Bit Error Rate Statistics.
+
+  @retval mrcSuccess if successful, otherwise returns an error status.
+**/
+MrcStatus
+MrcGetBERMarginCh (
+  IN     MrcParameters   *MrcData,
+  IN     U32             marginCh[MAX_RESULT_TYPE][MAX_RANK_IN_CHANNEL][MAX_CHANNEL][MAX_SDRAM_IN_DIMM][MAX_EDGES],
+  IN OUT U8              chBitmask,
+  IN     U8              RankRx,
+  IN     U8              Rank,
+  IN     U8              param,
+  IN     U16             mode,
+  IN     U8              EnBER,
+  IN     U8              MaxMargin,
+  IN     U8              Interior,
+  IN OUT U32             *BERStats
+  )
+{
+  const MrcDebug  *Debug;
+  MrcOutput       *Outputs;
+  MrcStatus       Status;
+  U8              ResultType;
+  U8              sign;
+  S8              rSign;
+  U8              SeqLC[4];
+  U8              Points2D;
+  U8              Channel;
+  U8              byte;
+  U8              SkipWait;
+  U8              byteMax[MAX_CHANNEL];
+  U8              Margin;
+  // Set to 1 after ch has 2 passing points
+  U16             TwoPass[MAX_CHANNEL];
+  // Set to 1 after ch has 2 failing points
+  U8              TwoFail[MAX_CHANNEL];
+  S8              Delta;
+  BOOL            Done;
+  BOOL            DimmVrefParam;
+  U32             value0;
+  U32             value1;
+  U32             tmp;
+  U32             chError;
+  U32             ErrCount;
+  U8              LastPassVref[MAX_CHANNEL];  // Last passing Vref
+  U8              MaxTested[MAX_CHANNEL];     // Highest Vref Point Tested
+  U8              MinTested[MAX_CHANNEL];     // Lowest Vref Point Tested
+  // Log8(Error count) at different Vref Points. 32 bit number that is broken in 4 bytes
+  // [LastPass+2, LastPass+1, LastPass, LastPass-1]
+  U32             Errors[MAX_CHANNEL];
+  U32             Offset;
+  BOOL            PerMc;
+  U8              McChannel;
+
+  MCDFXS_CR_REUT_GLOBAL_CTL_MCMAIN_STRUCT           ReutGlobalCtl;
+  MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_0_STRUCT ReutChErrCounterStatus;
+
+  Debug      = &MrcData->SysIn.Inputs.Debug;
+  Outputs    = &MrcData->SysOut.Outputs;
+  Status     = mrcSuccess;
+  ResultType = GetMarginResultType(param);
+  Points2D   = (param / 16) + 1;        // 2 for Fan2 and 3 for Fan3
+  McChannel  = 0;
+
+  if (Outputs->DQPat == SegmentWDB) {
+    SeqLC[0] = Outputs->DQPatLC;
+    SeqLC[1] = Outputs->DQPatLC;
+    SeqLC[2] = Outputs->DQPatLC + 4;
+    SeqLC[3] = Outputs->DQPatLC + 2;
+  } else {
+    SeqLC[0] = 1;
+    SeqLC[1] = 1;
+    SeqLC[2] = 1;
+    SeqLC[3] = 1;
+  }
+  //
+  // Make sure we cover all DIMM Vref cases
+  //
+  DimmVrefParam = (param == WrFan2 || param == WrFan3 || param == WrV );   // WrFan not defined
+  PerMc         = (param == CmdV) && (MrcCountBitsEqOne (chBitmask) >= 2);
+
+  //
+  // Run through margin test
+  //
+  for (sign = 0; sign < 2; sign++) {
+    rSign = (S8) ((2 * sign) - 1);
+    //MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE,"+----->rsign: %d \n", rSign);
+
+    MrcOemMemorySet ((U8 *) TwoPass, 0, sizeof (TwoPass));
+    MrcOemMemorySet ((U8 *) TwoFail, 0, sizeof (TwoFail));
+
+    //
+    // Initialize variables
+    //
+    for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+      //
+      // Set default of all variables
+      //
+      byteMax[Channel]      = MaxMargin;
+      LastPassVref[Channel] = 0x7F;  // Start with a huge unsigned numer - 128
+      Errors[Channel]       = 0;
+      MinTested[Channel]    = 0;
+      MaxTested[Channel]    = 0;
+
+      if (((MRC_BIT0 << Channel) & chBitmask) == 0) {
+        TwoPass[Channel] = 1;
+        TwoFail[Channel] = 1;
+        continue;
+      }
+      //
+      // Find MaxMargin for this channel
+      //
+      if (param == RdT) {
+        for (byte = 0; byte < Outputs->SdramCount; byte++) {
+          byteMax[Channel] = MrcCalcMaxRxMargin (MrcData, Channel, RankRx, byte, sign, byteMax[Channel]);
+        }
+      }
+      //
+      // Scale back variables to normal margins and check saturation
+      //
+      marginCh[ResultType][Rank][Channel][0][sign] = marginCh[ResultType][Rank][Channel][0][sign] / 10;
+      if (marginCh[ResultType][Rank][Channel][0][sign] > byteMax[Channel]) {
+        marginCh[ResultType][Rank][Channel][0][sign] = byteMax[Channel];
+      }
+      //
+      // If PerMC, all channels should start with the lowest margin across all the channel
+      //
+      if (PerMc) {
+        if (marginCh[ResultType][Rank][McChannel][0][sign] > marginCh[ResultType][Rank][Channel][0][sign]) {
+          marginCh[ResultType][Rank][McChannel][0][sign] = marginCh[ResultType][Rank][Channel][0][sign];
+        }
+      }
+
+      MinTested[Channel]  = (U8) marginCh[ResultType][Rank][Channel][0][sign];
+      MaxTested[Channel]  = MinTested[Channel];
+
+      //
+      // Setup REUT Error Counters to count errors per channel
+      //
+      Offset = MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_0_REG +
+        ((MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_0_REG - MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_0_REG) * Channel);
+      MrcWriteCR (MrcData, Offset, 0);
+    }
+    //
+    // If PerMC, set all channels to use margin associated with mcChannel = 0
+    //
+    if (PerMc) {
+      for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+        if (((MRC_BIT0 << Channel) & chBitmask) == 0) {
+          continue;
+        }
+        marginCh[ResultType][Rank][Channel][0][sign] = marginCh[ResultType][Rank][McChannel][0][sign];
+        MinTested[Channel] = (U8) marginCh[ResultType][Rank][McChannel][0][sign];
+        MaxTested[Channel] = MinTested[Channel];
+      }
+    }
+    //
+    // Search algorithm:
+    // If start with a passing point, walk to hit 2 failing points
+    //    Return as needed to hit a second passing point
+    // If start with a failing point, walk to hit 2 passing points
+    //    Return as needed to hit a second failing point
+    // Keep testing until all ch/bytes find 2 passes and 2 fails
+    //
+    Done = FALSE;
+    do {
+      //
+      // Walk through all 2D points
+      //
+      ReutGlobalCtl.Data = 0;
+      ReutGlobalCtl.Bits.Global_Clear_Errors = 1;
+      MrcWriteCR (MrcData, MCDFXS_CR_REUT_GLOBAL_CTL_MCMAIN_REG, ReutGlobalCtl.Data);  // Clear errors
+      chError = 0;
+
+      for (value1 = 0; value1 < Points2D; value1++) {
+        //
+        // Set Vref level
+        //
+        for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+          if (((MRC_BIT0 << Channel) & chBitmask) == 0) {
+            continue;
+          }
+
+          SkipWait = (chBitmask >> (Channel + 1)); // Skip if there are more channels
+          value0 = rSign * marginCh[ResultType][Rank][Channel][0][sign];
+          //MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "+----->Value0 is %d, Value1 is %d\n", (S32) value0, value1);
+
+          if (param == CmdV) {
+            UpdateVrefWaitTilStable (MrcData, 2, 0, value0, 0);
+            MrcResetSequence (MrcData);
+            //MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "+----->Value0 is %d, Value1 is %d\n", (S32) value0, value1);
+            break; // Just update for one channel
+          } else {
+            for (byte = 0; byte < Outputs->SdramCount; byte++) {
+              Status = ChangeMargin (
+                        MrcData,
+                        param,
+                        value0,
+                        value1,
+                        0,
+                        Channel,
+                        RankRx,
+                        byte,
+                        0,
+                        0,
+                        SkipWait,
+                        MrcRegFileStart
+                        );
+              if (DimmVrefParam) {
+                //
+                // Only Byte 7 on Channel 1 is needed to update Wr DIMM Vref - Taken care of inside ChangeMargin routine
+                //
+                break;
+              }
+            }
+          }
+        }
+        //
+        // Run Test
+        //
+        chError |= RunIOTest (MrcData, chBitmask, Outputs->DQPat, SeqLC, (value1 == 0), mode);
+
+        //
+        // check if we have already failed and can stop running
+        //
+        if (EnBER == 0 && value1 < (U32) (Points2D - 1) && chError == chBitmask) {
+          break;
+        }
+        //
+        // Collect results and Update variables for next point to test
+        //
+        for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+          if ((TwoPass[Channel] == 1 && TwoFail[Channel] == 1) || ((MRC_BIT0 << Channel) & chBitmask) == 0) {
+            continue;
+          }
+
+          McChannel = (PerMc) ? 0 : Channel;
+
+          //
+          // Read Error Count
+          //
+          Offset = MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_0_REG +
+            ((MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_0_REG - MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_0_REG) * Channel);
+          ReutChErrCounterStatus.Data = MrcReadCR (MrcData, Offset);
+          ErrCount                    = ReutChErrCounterStatus.Bits.Counter_Status;
+          Margin                      = (U8) marginCh[ResultType][Rank][Channel][0][sign];
+          Delta                       = (Margin - LastPassVref[Channel]);
+
+          //
+          // Update Pass/Fail Variables:
+          //
+          if (ErrCount == 0 && Margin == MaxTested[McChannel]) {
+            //
+            // Passing while walking up
+            //
+            if (Delta < 0) {
+              //
+              // First passing point
+              // @todo: Next line should be changed to return failure. Code should never hang.
+              //
+              MRC_ASSERT (
+                MinTested[McChannel] == MaxTested[McChannel],
+                Debug,
+                "Error: MaxTested < LastPass after first point"
+                );
+              LastPassVref[Channel] = Margin;
+            } else if (Delta == 1) {
+              //
+              // Normal, walk to fail
+              //
+              Errors[Channel]       = MrcBitShift (Errors[Channel], -8 * Delta) & BER_ERROR_MASK;
+              LastPassVref[Channel] = Margin;
+              TwoPass[Channel]      = 1;
+            } else if (Delta == 2) {
+              //
+              // Speckling in response, Consider point as error
+              //
+              Errors[Channel]   = MrcBitSwap (Errors[Channel], MrcLog8 (ErrCount), 24, 8);
+              TwoFail[Channel]  = 1;
+            } else {
+              //
+              // @todo: Next line should be changed to return failure. Code should never hang.
+              //
+              MRC_ASSERT (FALSE, Debug, "Error: Tested point twice or Tested >2 above LastPass");
+            }
+          } else if (ErrCount == 0 && Margin == MinTested[McChannel]) {
+            if (TwoPass[Channel] == 1) {
+              continue; // Skip if this channel is already done
+            }
+            //
+            // Passing while walking down
+            //
+            if (Delta == -1) {
+              Errors[Channel]  = MrcBitSwap (Errors[Channel], 0, 0, 8);
+              TwoPass[Channel] = 1;     // found second pass
+            } else {
+              //
+              // 1st passing point
+              // Don't shift errors.  Fail points already assumed correct
+              //
+              LastPassVref[Channel] = Margin;
+              TwoPass[Channel]      = 0;
+            }
+          } else if (ErrCount > 0 && Margin == MaxTested[McChannel]) {
+            //
+            // Failing while walking up
+            // @todo: Next line should be changed to return failure. Code should never hang.
+            //
+            MRC_ASSERT (Delta <= 2, Debug, "Error: Tested >2 above LastPass");
+            if (Delta < 2) {
+              //
+              // first failing point
+              //
+              Errors[Channel]   = MrcBitSwap (Errors[Channel], MrcLog8 (ErrCount), 16, 8);
+              TwoFail[Channel]  = 0;
+            } else if (Delta == 2) {
+              //
+              // 2nd failing point
+              //
+              Errors[Channel]   = MrcBitSwap (Errors[Channel], MrcLog8 (ErrCount), 24, 8);
+              TwoFail[Channel]  = 1;
+            }
+          } else if (ErrCount > 0 && Margin == MinTested[McChannel]) {
+            //
+            // Failing while walking down
+            //
+            if (LastPassVref[Channel] < 0xFF && Delta <= 0) {
+              //
+              // Adjust LastPassVref and Error count to be below this failure point
+              //
+              Errors[Channel]       = MrcBitSwap (Errors[Channel], MrcLog8 (ErrCount), 8 * (Delta + 1), 8);
+              Errors[Channel]       = MrcBitShift (Errors[Channel], 8 * (1 - Delta));
+              LastPassVref[Channel] = Margin - 1;
+            } else {
+              MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Unexpected case for channel: %d, delta: %d.\n", Channel, Delta);
+              tmp             = ((Errors[Channel] & 0xFF0000) >> 8) + MrcLog8 (ErrCount);
+              Errors[Channel] = MrcBitSwap (Errors[Channel], tmp, 16, 16);
+            }
+
+            if (MinTested[McChannel] < MaxTested[McChannel]) {
+              TwoFail[Channel] = 1;
+            }
+
+            if (Delta <= 0) {
+              TwoPass[Channel] = 0;
+            }
+          } else {
+            //
+            // @todo: Next line should be changed to return failure. Code should never hang.
+            //
+            MRC_ASSERT (FALSE, Debug, "Error: Testing points other than Max/MinTested");
+          }
+          //
+          // Find Max Saturation limit
+          //
+          if (Interior && MaxTested[Channel] == Margin) {
+            byteMax[Channel] = Margin;
+          }
+          //
+          // Handle Max Saturation
+          //
+          if (Margin == byteMax[Channel]) {
+            TwoFail[Channel] = 1;
+          }
+
+          if (ErrCount == 0 && byteMax[Channel] == LastPassVref[Channel] && TwoPass[Channel] == 1) {
+            Errors[Channel] = MrcBitSwap (Errors[Channel], 0xFFFE, 16, 16);
+          }
+          //
+          // Handle Min Saturation
+          //
+          if (Margin == 0) {
+            TwoPass[Channel] = 1;
+            if (ErrCount > 0) {
+              TwoFail[Channel]      = 1;
+              LastPassVref[Channel] = 0;
+              Errors[Channel]       = MrcBitSwap (Errors[Channel], (BER_LOG_TARGET << 8) + BER_LOG_TARGET, 16, 16);
+            }
+          }
+          //
+          // Decide what to test next for PerMC == FALSE
+          //
+          if (!PerMc) {
+            if (TwoPass[Channel] == 1) {
+              if (TwoFail[Channel] == 1) {
+                continue;
+              }
+              //MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE,"++---->MaxTested[Ch] before ++:%d\n", MaxTested[Channel]);////////
+              marginCh[ResultType][Rank][Channel][0][sign] = ++MaxTested[Channel];
+            } else {
+              //            MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE,"++---->MinTested[Ch] before --:%d\n", MinTested[Channel]);////////
+              marginCh[ResultType][Rank][Channel][0][sign] = --MinTested[Channel];
+            }
+          }
+        }
+        //
+        // Decide what to test next for PerMC == TRUE
+        //
+        if (PerMc) {
+          if ((TwoPass[0] == 1) && (TwoPass[1] == 1)) {
+            //
+            // All Channels have 2 passes
+            //
+            if ((TwoFail[0] == 1) && (TwoFail[1] == 1)) {
+              //
+              // All Channels have 2 fails
+              //
+              continue;
+            }
+            //MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE,"++---->MaxTested[Ch] before ++:%d\n", MaxTested[Channel]);////////
+            marginCh[ResultType][Rank][McChannel][0][sign] = ++MaxTested[McChannel];
+          } else {
+            //            MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE,"++---->MinTested[Ch] before --:%d\n", MinTested[Channel]);////////
+            marginCh[ResultType][Rank][McChannel][0][sign] = --MinTested[McChannel];
+          }
+
+          for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+            if (((MRC_BIT0 << Channel) & chBitmask) == 0) {
+              continue;
+            }
+
+            marginCh[ResultType][Rank][Channel][0][sign] = marginCh[ResultType][Rank][McChannel][0][sign];
+            MinTested[Channel] = MinTested[McChannel];
+            MaxTested[Channel] = MaxTested[McChannel];
+          }
+        }
+      }
+      //
+      // check if we are done
+      //
+      Done = TRUE;
+      for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+        if (TwoPass[Channel] == 0 || TwoFail[Channel] == 0) {
+          Done = FALSE;
+          break;
+        }
+      }
+    } while (Done == FALSE);
+
+    //
+    // Calculate the effective margin
+    // Update marginch with extroploated BER Margin
+    //
+    for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+      if (((MRC_BIT0 << Channel) & chBitmask) == 0) {
+        continue;
+      }
+      //MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE,"+----->marginCh[%d,%d] is: %d\n", Channel, sign,  marginCh[ResultType][Rank][Channel][0][sign]);
+      if (EnBER) {
+        marginCh[ResultType][Rank][Channel][0][sign] = interpolateVref (
+                                                        LastPassVref[Channel],
+                                                        (Errors[Channel] >> 16) & 0xFF,
+                                                        (Errors[Channel] >> 24) & 0xFF,
+                                                        BER_LOG_TARGET,
+                                                        BERStats
+                                                        );
+        // MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "+----->BERmarginCh[%d,%d] is: %d, Errors = 0x%x\n", Channel, sign,  marginCh[ResultType][Rank][Channel][0][sign], Errors[Channel]);
+      } else {
+        marginCh[ResultType][Rank][Channel][0][sign] = 10 * LastPassVref[Channel];
+        //MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "+----->marginCh[%d,%d] is: %d\n", Channel, sign,  marginCh[ResultType][Rank][Channel][0][sign]);
+      }
+    }
+  }
+  //
+  // Clean up after step
+  //
+  if (param == CmdV) {
+    UpdateVrefWaitTilStable (MrcData, 2, 0, 0, 0);
+  } else {
+    Status = ChangeMargin (MrcData, param, 0, 0, 1, 0, 0, 0, 0, 0, 0, MrcRegFileCurrent);
+  }
+
+  MrcWriteCrMulticast (MrcData, MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_0_REG, 0);
+
+  return Status;
+}
+
+/**
+  This function shifts a 32 bit int either positive or negative
+
+  @param[in] Value       - Input value to be shifted
+  @param[in] ShiftAmount - Number of bits places to be shifted.
+
+  @retval 0 if ShiftAmount exceeds +/- 31.  Otherwise the updated 32 bit value.
+**/
+U32
+MrcBitShift (
+  IN const U32 Value,
+  IN const S8  ShiftAmount
+  )
+{
+  if ((ShiftAmount > 31) || (ShiftAmount < -31)) {
+    return 0;
+  }
+
+  if (ShiftAmount > 0) {
+    return Value << ShiftAmount;
+  } else {
+    return Value >> (-1 * ShiftAmount);
+  }
+}
+
+/**
+  This function Sign extends OldMSB to NewMSB Bits (Eg: Bit 6 to Bit 7)
+
+  @param[in] CurrentValue - Input value to be shifted
+  @param[in] OldMSB       - The original most significant Bit
+  @param[in] NewMSB       - The new most significant bit.
+
+  @retval The updated 8 bit value.
+**/
+U8
+MrcSE (
+  IN U8        CurrentValue,
+  IN const U8  OldMSB,
+  IN const U8  NewMSB
+  )
+{
+  U8 Scratch;
+
+  Scratch = ((MRC_BIT0 << (NewMSB - OldMSB)) - 1) << OldMSB;
+  if (CurrentValue >> (OldMSB - 1)) {
+    CurrentValue |= Scratch;
+  } else {
+    CurrentValue &= (~Scratch);
+  }
+
+  return CurrentValue;
+}
+
+/**
+  This function calculates the Log base 2 of the value to a maximum of Bits
+
+  @param[in] Value - Input value
+
+  @retval Returns the log base 2 of input value
+**/
+U8
+MrcLog2 (
+  IN const U32 Value
+  )
+{
+  U8  Log;
+  U8  Bit;
+
+  //
+  // Return 0 if value is negative
+  //
+  Log = 0;
+  if ((Value + 1) != 0) {
+    for (Bit = 0; Bit < 32; Bit++) {
+      if (Value & (MRC_BIT0 << Bit)) {
+        Log = (Bit + 1);
+      }
+    }
+  }
+
+  return Log;
+}
+
+/**
+  ***** Has Buffer Overflow for 68-71, 544-575, 4352-4607, ... ****
+  This function calculates the Log base 8 of the Input parameter using integers
+
+  @param[in] Value - Input value
+
+  @retval Returns 10x the log base 8 of input Value
+**/
+U32
+MrcLog8 (
+  IN U32 Value
+  )
+{
+  const U8  Loglook[17] = { 0, 0, 1, 2, 3, 4, 5, 6, 7, 7, 8, 8, 9, 9, 9, 10, 10 };
+  U32       Loga;
+  U32       Rema;
+
+  Loga  = 0;
+  Rema  = 2 * Value;
+  while (Value > 8) {
+    Rema  = Value >> 2;
+    Value = Value >> 3;
+    Loga += 10;
+  };
+
+  return (Loga + Loglook[Rema]); //returns an integer approximation of "log8(a) * 10"
+}
+
+/**
+  This function Sorts Arr from largest to smallest
+
+  @param[in,out] Arr     - Array to be sorted
+  @param[in]     Channel - Channel to sort.
+  @param[in]     lenArr  - Length of the array
+
+  @retval Nothing
+**/
+void
+MrcBsortPerChannel (
+  IN OUT U32      Arr[MAX_CHANNEL][4],
+  IN     const U8 Channel,
+  IN     const U8 lenArr
+  )
+{
+  U8  i;
+  U8  j;
+  U32 temp;
+
+  for (i = 0; i < lenArr - 1; i++) {
+    for (j = 0; j < lenArr - (1 + i); j++) {
+      if (Arr[Channel][j] < Arr[Channel][j + 1]) {
+        temp                = Arr[Channel][j];
+        Arr[Channel][j]     = Arr[Channel][j + 1];
+        Arr[Channel][j + 1] = temp;
+      }
+    }
+  }
+
+  return;
+}
+
+/**
+  This function Sorts Arr from largest to smallest
+
+  @param[in,out] Arr    - Array to be sort
+  @param[in]     lenArr - Lenght of the array
+
+  @retval Nothing
+**/
+void
+MrcBsort (
+  IN OUT U32 *const Arr,
+  IN     const U8   lenArr
+  )
+{
+  U8  i;
+  U8  j;
+  U32 temp;
+
+  for (i = 0; i < lenArr - 1; i++) {
+    for (j = 0; j < lenArr - (1 + i); j++) {
+      if (Arr[j] < Arr[j + 1]) {
+        temp        = Arr[j];
+        Arr[j]      = Arr[j + 1];
+        Arr[j + 1]  = temp;
+      }
+    }
+  }
+
+  return;
+}
+
+/**
+  This function calculates the Natural Log of the Input parameter using integers
+
+  @param[in] Input - 100 times a number to get the Natural log from.
+                      Max Input Number is 40,000 (without 100x)
+
+  @retval 100 times the actual result. Accurate within +/- 2
+**/
+U32
+MrcNaturalLog (
+  U32 Input
+  )
+{
+  U32 Output;
+
+  Output = 0;
+  while (Input > 271) {
+    Input = (Input * 1000) / 2718;
+    Output += 100;
+  }
+
+  Output += ((-16 * Input * Input + 11578 * Input - 978860) / 10000);
+
+  return Output;
+}
+
+/**
+  This function calculates the number of bits set to 1 in a 32-bit value.
+
+  @param[in] Input - The value to work on.
+
+  @retval The number of bits set to 1 in Input.
+**/
+U8
+MrcCountBitsEqOne (
+  IN U32 Input
+  )
+{
+  U8  NumOnes;
+
+  NumOnes = 0;
+  while (Input > 0) {
+    NumOnes++;
+    Input &= (Input - 1);
+  }
+
+  return NumOnes;
+}
+
+/**
+  This function calculates e to the power of of the Input parameter using integers.
+
+  @param[in] Input - 100 times a number to elevate e to.
+
+  @retval 100 times the actual result. Accurate within +/- 2.
+**/
+U32
+Mrceexp (
+  IN U32 Input
+  )
+{
+  U32 Extra100;
+  U32 Output;
+
+  Extra100  = 0;
+  Output    = 1;
+  while (Input > 100) {
+    Input -= 100;
+    Output = (Output * 2718) / 10;
+    if (Extra100) {
+      Output /= 100;
+    }
+
+    Extra100 = 1;
+  }
+
+  Output = ((Output * (8 * Input * Input + 900 * Input + 101000)) / 1000);
+
+  if (Extra100) {
+    Output /= 100;
+  }
+
+  return Output;
+}
+
+/**
+  This function writes a 32 bit register.
+
+  @param[in] MrcData - Include all MRC global data.
+  @param[in] Offset  - Offset of register from MchBar Base Address.
+  @param[in] Value   - Value to write.
+
+  @retval Nothing
+**/
+void
+MrcWriteCrMulticast (
+  IN MrcParameters *const MrcData,
+  IN const U32            Offset,
+  IN const U32            Value
+  )
+{
+  MrcOemMmioWrite (Offset, Value, MrcData->SysIn.Inputs.MchBarBaseAddress);
+#ifdef MRC_DEBUG_PRINT
+  if (MrcData->SysIn.Inputs.Debug.PostCode[0] == MrcData->SysIn.Inputs.Debug.PostCode[1]) {
+    MRC_DEBUG_MSG (
+      &MrcData->SysIn.Inputs.Debug,
+      MSG_LEVEL_NOTE,
+      "%08Xh > %08Xh\n",
+      MrcData->SysIn.Inputs.MchBarBaseAddress + Offset,
+      Value
+      );
+  }
+#endif // MRC_DEBUG_PRINT
+  return;
+}
+
+/**
+  This function writes a 64 bit register.
+
+  @param[in] MrcData - Include all MRC global data.
+  @param[in] Offset  - Offset of register from MchBar Base Address.
+  @param[in] Value   - Value to write.
+
+  @retval Nothing
+**/
+void
+MrcWriteCR64 (
+  IN MrcParameters *const MrcData,
+  IN const U32            Offset,
+  IN const U64            Value
+  )
+{
+  MrcOemMmioWrite64 (Offset, Value, MrcData->SysIn.Inputs.MchBarBaseAddress);
+#ifdef MRC_DEBUG_PRINT
+  if (MrcData->SysIn.Inputs.Debug.PostCode[0] == MrcData->SysIn.Inputs.Debug.PostCode[1]) {
+    MRC_DEBUG_MSG (
+      &MrcData->SysIn.Inputs.Debug,
+      MSG_LEVEL_NOTE,
+      "%08Xh > %016Xh\n",
+      MrcData->SysIn.Inputs.MchBarBaseAddress + Offset,
+      Value
+      );
+  }
+#endif // MRC_DEBUG_PRINT
+  return;
+}
+
+/**
+  This function writes a 32 bit register.
+
+  @param[in] MrcData - Include all MRC global data.
+  @param[in] Offset  - Offset of register from MchBar Base Address.
+  @param[in] Value   - Value to write.
+
+  @retval Nothing
+**/
+void
+MrcWriteCR (
+  IN MrcParameters *const MrcData,
+  IN const U32            Offset,
+  IN const U32            Value
+  )
+{
+  MrcOemMmioWrite (Offset, Value, MrcData->SysIn.Inputs.MchBarBaseAddress);
+#ifdef MRC_DEBUG_PRINT
+  if (MrcData->SysIn.Inputs.Debug.PostCode[0] == MrcData->SysIn.Inputs.Debug.PostCode[1]) {
+    MRC_DEBUG_MSG (
+      &MrcData->SysIn.Inputs.Debug,
+      MSG_LEVEL_NOTE,
+      "%08Xh > %08Xh\n",
+      MrcData->SysIn.Inputs.MchBarBaseAddress + Offset,
+      Value
+      );
+  }
+#endif // MRC_DEBUG_PRINT
+  return;
+}
+
+/**
+  This function writes a 8 bit register.
+
+  @param[in] MrcData - Include all MRC global data.
+  @param[in] Offset  - Offset of register from MchBar Base Address.
+  @param[in] Value   - The value to write.
+
+  @retval Nothing
+**/
+void
+MrcWriteCR8 (
+  IN MrcParameters*const MrcData,
+  IN const U32            Offset,
+  IN const U8             Value
+  )
+{
+  MrcOemMmioWrite8 (Offset, Value, MrcData->SysIn.Inputs.MchBarBaseAddress);
+#ifdef MRC_DEBUG_PRINT
+  if (MrcData->SysIn.Inputs.Debug.PostCode[0] == MrcData->SysIn.Inputs.Debug.PostCode[1]) {
+    MRC_DEBUG_MSG (
+      &MrcData->SysIn.Inputs.Debug,
+      MSG_LEVEL_NOTE,
+      "%08Xh > %02Xh\n",
+      MrcData->SysIn.Inputs.MchBarBaseAddress + Offset,
+      Value
+      );
+  }
+#endif // MRC_DEBUG_PRINT
+  return;
+}
+
+/**
+  This function reads a 64 bit register.
+
+  @param[in] MrcData - Include all MRC global data.
+  @param[in] Offset  - Offset of register from MchBar Base Address.
+
+  @retval Value read from the register.
+**/
+U64
+MrcReadCR64 (
+  IN MrcParameters *const MrcData,
+  IN const U32            Offset
+  )
+{
+  U64 Value;
+
+  MrcOemMmioRead64 (Offset, &Value, MrcData->SysIn.Inputs.MchBarBaseAddress);
+  return Value;
+}
+
+/**
+  This function reads a 32 bit register.
+
+  @param[in] MrcData - Include all MRC global data.
+  @param[in] Offset  - Offset of register from MchBar Base Address.
+
+  @retval Value read from the register
+**/
+U32
+MrcReadCR (
+  IN MrcParameters *const MrcData,
+  IN const U32            Offset
+  )
+{
+  U32 Value;
+
+  MrcOemMmioRead (Offset, &Value, MrcData->SysIn.Inputs.MchBarBaseAddress);
+  return Value;
+}
+
+/**
+  This function blocks the CPU for the duration specified in HPET Delay time.
+
+  @param[in] MrcData   - Include all MRC global data.
+  @param[in] DelayHPET - time to wait in 69.841279ns
+
+  @retval Nothing
+**/
+void
+MrcWait (
+  IN MrcParameters *const MrcData,
+  IN U32                  DelayHPET
+  )
+{
+  const MrcInput  *Inputs;
+  BOOL            Done;
+  U32             Start;
+  volatile U32    Finish;
+  U32             Now;
+
+Inputs = &MrcData->SysIn.Inputs;
+Done   = FALSE;
+
+
+  if (DelayHPET >= (5 * HPET_1US)) {
+    MrcOemMmioRead (0xF0, &Start, Inputs->HpetBaseAddress);
+    Finish = Start + DelayHPET;
+
+    do {
+      MrcOemMmioRead (0xF0, &Now, Inputs->HpetBaseAddress);
+      if (Finish > Start) {
+        if (Now >= Finish) {
+          Done = TRUE;
+        }
+      } else {
+        if ((Now < Start) && (Now >= Finish)) {
+          Done = TRUE;
+        }
+      }
+    } while (Done == FALSE);
+  } else {
+    for (Start = 0; Start < ((DelayHPET + HPET_MIN) / (2 * HPET_MIN)); Start++) {
+      //
+      // Just perform Dummy reads to CPU CR
+      //
+      Finish = MrcReadCR (MrcData, MCSCHEDS_CR_REUT_CH_ERR_DATA_STATUS_REG);
+    }
+  }
+  return;
+}
+
+/**
+  This function forces an RCOMP.
+
+  @param[in] MrcData - Include all MRC global data.
+
+  @retval Nothing
+**/
+void
+ForceRcomp (
+  IN MrcParameters *const MrcData
+  )
+{
+  MrcWriteCR8 (MrcData, PCU_CR_M_COMP_PCU_REG + 1, MRC_BIT0);
+
+  //
+  // 10 - 20 us wait.
+  //
+  MrcWait (MrcData, 10 * HPET_1US);
+  return;
+}
+
+/**
+  This function sets the self refresh idle timer and enables it.
+
+  @param[in] MrcData - Include all MRC global data.
+
+  @retval Nothing
+**/
+void
+EnterSR (
+  IN MrcParameters *const MrcData
+  )
+{
+  MCDECS_CR_PM_SREF_CONFIG_MCMAIN_STRUCT  PmSrefConfig;
+
+  PmSrefConfig.Data             = 0;
+  PmSrefConfig.Bits.SR_Enable   = 1;
+  PmSrefConfig.Bits.Idle_timer  = SELF_REFRESH_IDLE_COUNT;
+  MrcWriteCR (MrcData, MCDECS_CR_PM_SREF_CONFIG_MCMAIN_REG, PmSrefConfig.Data);
+  MrcWait (MrcData, HPET_1US);
+  return;
+}
+
+/**
+  This function sets the self refresh idle timer and disables it.
+
+  @param[in] MrcData - Include all MRC global data.
+
+  @retval Nothing
+**/
+void
+ExitSR (
+  IN MrcParameters *const MrcData
+  )
+{
+  MCDECS_CR_PM_SREF_CONFIG_MCMAIN_STRUCT  PmSrefConfig;
+
+  PmSrefConfig.Data             = 0;
+  PmSrefConfig.Bits.Idle_timer  = SELF_REFRESH_IDLE_COUNT;
+  MrcWriteCR (MrcData, MCDECS_CR_PM_SREF_CONFIG_MCMAIN_REG, PmSrefConfig.Data);
+  MrcWait (MrcData, HPET_1US);
+  return;
+}
+
+/**
+  This function programs the WDB.
+
+  @param[in] MrcData - Include all MRC global data.
+
+  @retval Nothing
+**/
+void
+SetupWDB (
+  IN MrcParameters *const MrcData
+  )
+{
+  U8        a;
+  const U32 vmask    =  0x41041041;
+  const U32 amask[9] = {0x86186186, 0x18618618, 0x30C30C30, 0xA28A28A2, 0x8A28A28A,
+                        0x14514514, 0x28A28A28, 0x92492492, 0x24924924};
+  const U32 seeds[MRC_WDB_NUM_MUX_SEEDS] = {0xA10CA1, 0xEF0D08, 0xAD0A1E};
+  U8        Channel;
+  U32       Offset;
+  MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_STRUCT ReutPatWdbClMuxLmn;
+
+  //
+  // Fill first 8 entries as simple 2 LFSR VA pattern
+  // VicRot=8, Start=0
+  //
+  WriteWDBVAPattern (MrcData, 0, BASIC_VA_PATTERN_SPRED_8, 8, 0);
+
+  //
+  // Fill next 54 entries as 3 LFSR VA pattern
+  //
+  for (a = 0; a < 9; a++) {
+    //
+    // VicRot=6, Start=8+a*6
+    //
+    WriteWDBVAPattern (MrcData, amask[a], vmask, 6, 8 + a * 6);
+  }
+  //
+  // Write the LFSR seeds
+  //
+  MrcProgramLFSR (MrcData, seeds);
+  for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+    if (MrcChannelExist (&MrcData->SysOut.Outputs, Channel)) {
+      ReutPatWdbClMuxLmn.Data                         = 0;
+      ReutPatWdbClMuxLmn.Bits.N_counter               = 10;
+      ReutPatWdbClMuxLmn.Bits.M_counter               = 1;
+      ReutPatWdbClMuxLmn.Bits.L_counter               = 1;
+      ReutPatWdbClMuxLmn.Bits.Enable_Sweep_Frequency  = 1;
+      Offset = MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_REG +
+        ((MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_REG - MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_REG) * Channel);
+      MrcWriteCR (MrcData, Offset, ReutPatWdbClMuxLmn.Data);
+    }
+  }
+
+  return;
+}
+
+/**
+  This function will program all present channels with the 3 seeds passed in.
+
+  @param[in] MrcData - Global MRC data structure
+  @param[in] seeds   - Array of 3 seeds programmed into PAT_WDB_CL_MUX_PB_RD/WR
+
+  @retval - Nothing
+
+**/
+void
+MrcProgramLFSR (
+  IN MrcParameters *const MrcData,
+  IN U32 const            seeds[MRC_WDB_NUM_MUX_SEEDS]
+  )
+{
+  U32 CrOffset;
+  U8  Channel;
+  U8  s;
+
+  for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+    if (MrcChannelExist (&MrcData->SysOut.Outputs, Channel)) {
+      for (s = 0; s < MRC_WDB_NUM_MUX_SEEDS; s++) {
+        CrOffset = MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_0_REG +
+          ((MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_0_REG - MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_0_REG) * Channel) +
+          ((MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_1_REG - MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_0_REG) * s);
+        MrcWriteCR (MrcData, CrOffset, seeds[s]);
+        CrOffset = MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_0_REG +
+          ((MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_0_REG - MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_0_REG) * Channel) +
+          ((MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_1_REG - MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_0_REG) * s);
+        MrcWriteCR (MrcData, CrOffset, seeds[s]);
+      }
+    }
+  }
+}
+
+/**
+  This function Write 1 cacheline worth of data to the WDB
+
+  @param[in] MrcData  - Include all MRC global data.
+  @param[in] Patterns - Array of bytes.  Each bytes represents 8 chunks of the cachelines for 1 lane.
+                         Each entry in Patterns represents a different cacheline for a different lane.
+  @param[in] PMask    - Array of len Spread uint8.  Maps the patterns to the actual DQ lanes.
+                         DQ[0] = Patterns[PMask[0]], ... DQ[Spread-1] = Patterns[PMask[Spread-1]]
+                         DQ[Spread] = DQ[0], ... DQ[2*Spread-1] = DQ[Spread-1]
+  @param[in] Start    - Starting entry in the WDB.
+
+  @retval Nothing
+**/
+void
+WriteWDBFixedPattern (
+  IN MrcParameters *const MrcData,
+  IN U8 *const            Patterns,
+  IN U8 *const            PMask,
+  IN const U8             Spread,
+  IN const U16            Start
+  )
+{
+  MrcOutput                           *Outputs;
+  U8                                  Channel;
+  U8                                  up32;
+  U8                                  chunk;
+  U8                                  b;
+  U8                                  beff;
+  U8                                  burst;
+  U32                                 data;
+  U32                                 pointer;
+  U32                                 Offset;
+  MCHBAR_CH0_CR_QCLK_LDAT_PDAT_STRUCT QclkLdatPdat;
+
+  Outputs = &MrcData->SysOut.Outputs;
+  for (chunk = 0; chunk < 8; chunk++) {
+    //
+    // Program LDAT_DATAIN_*
+    //
+    for (up32 = 0; up32 < 2; up32++) {
+      data = 0;
+      for (b = 0; b < 32; b++) {
+        beff  = (b + 32 * up32) % Spread;
+        burst = Patterns[PMask[beff]];
+        if (burst & (MRC_BIT0 << chunk)) {
+          data |= (MRC_BIT0 << b);
+        }
+      }
+
+      for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+        if (MrcChannelExist (Outputs, Channel)) {
+          Offset = MCHBAR_CH0_CR_QCLK_LDAT_DATAIN_0_REG +
+            ((MCHBAR_CH1_CR_QCLK_LDAT_DATAIN_0_REG - MCHBAR_CH0_CR_QCLK_LDAT_DATAIN_0_REG) * Channel) +
+            ((MCHBAR_CH0_CR_QCLK_LDAT_DATAIN_1_REG - MCHBAR_CH0_CR_QCLK_LDAT_DATAIN_0_REG) * up32);
+          MrcWriteCR (MrcData, Offset, data);
+        }
+      }
+    } // up32
+
+    pointer = MRC_BIT16 + chunk;
+
+    for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+      if (MrcChannelExist (Outputs, Channel)) {
+        //
+        // Set rep = 0 don't want to replicate the data
+        // Set banksel field to the value of the chunk you want to write the 64 bits to.
+        // Set arraysel = 0 ( indicating it is the MC WDB) and mode = 'b01 in the SDAT register
+        //
+        Offset = MCHBAR_CH0_CR_QCLK_LDAT_SDAT_REG +
+          ((MCHBAR_CH1_CR_QCLK_LDAT_SDAT_REG - MCHBAR_CH0_CR_QCLK_LDAT_SDAT_REG) * Channel);
+        MrcWriteCR (MrcData, Offset, pointer);
+
+        //
+        // Finally, write the PDAT register indicating which cacheline of the WDB you want to write to
+        // by setting fastaddr field to one of the 64 cache lines. Also set cmdb in the pdat register to 4'b1000,
+        // indicating that this is a LDAT write
+        //
+        Offset = MCHBAR_CH0_CR_QCLK_LDAT_PDAT_REG +
+          ((MCHBAR_CH1_CR_QCLK_LDAT_PDAT_REG - MCHBAR_CH0_CR_QCLK_LDAT_PDAT_REG) * Channel);
+        QclkLdatPdat.Data = 0;
+        QclkLdatPdat.Bits.CMDB = 8;
+        QclkLdatPdat.Bits.FASTADDR = MIN (Start, MCHBAR_CH0_CR_QCLK_LDAT_PDAT_FASTADDR_MAX);
+        MrcWriteCR (MrcData, Offset, QclkLdatPdat.Data);
+      }
+    }
+  } // chunk
+  //
+  // Turn off LDAT mode after writing to WDB is complete
+  //
+  for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+    if (MrcChannelExist (Outputs, Channel)) {
+      Offset = MCHBAR_CH0_CR_QCLK_LDAT_SDAT_REG +
+        ((MCHBAR_CH1_CR_QCLK_LDAT_SDAT_REG - MCHBAR_CH0_CR_QCLK_LDAT_SDAT_REG) * Channel);
+      MrcWriteCR (MrcData, Offset, 0);
+    }
+  }
+
+  return;
+}
+
+/**
+  This rotine performs the following steps:
+    Step 0: Iterate through all VicRots
+    Step 1: Create a compressed vector for a given 32 byte cacheline
+            Each byte has a value of LFSR0=AA/LFSR1=CC/LFSR2=F0
+    Step 2: Expand compressed vector into chunks and 32 bit segments
+
+  @param[in] MrcData - Include all MRC global data.
+  @param[in] vmask   - 32 bit victim mask.  1 indicates this bit should use LFSR0
+  @param[in] amask   - 32 bit aggressor mask. 0/1 indicates this bit should use LFSR1/2
+  @param[in] VicRot  - Number of times to circular rotate vmask/amask
+  @param[in] Start   - Starting entry in the WDB
+
+  @retval Nothing
+**/
+void
+WriteWDBVAPattern (
+  IN MrcParameters *const MrcData,
+  IN U32                  amask,
+  IN U32                  vmask,
+  IN const U8             VicRot,
+  IN const U16            Start
+  )
+{
+  const U8        VAMask2Compressed[4] = {0xAA, 0xC0, 0xCC, 0xF0};
+  MrcOutput       *Outputs;
+  U8              b;
+  U8              chunk;
+  U8              Channel;
+  U8              cmask;
+  U16             v;
+  U32             Vic;
+  U32             Agg2;
+  U32             data;
+  U32             pointer;
+  U32             msb;
+  U8              Compressed[32];
+  U32             BitMask;
+  U8              Index;
+  U16             Scratch;
+  U32             Offset;
+  MCHBAR_CH0_CR_QCLK_LDAT_PDAT_STRUCT QclkLdatPdat;
+
+  Outputs = &MrcData->SysOut.Outputs;
+  for (v = 0; v < VicRot; v++) {
+    //
+    // Iterate through all 32 bits and create a compressed version of cacheline
+    // AA = Victim (LFSR0), CC = Agg1(LFSR1), F0 = Agg2 (LFSR2)
+    //
+    for (b = 0; b < 32; b++) {
+      BitMask = MRC_BIT0 << b;
+      Vic     = (vmask & BitMask);
+      Agg2    = (amask & BitMask);
+
+      //
+      // Program compressed vector
+      //
+      if (Vic && Agg2) {
+        Index = 1;
+      } else if (Vic && !Agg2) {
+        Index = 0;
+      } else if (!Vic && !Agg2) {
+        Index = 2;
+      } else {
+        Index = 3;
+      }
+
+      Compressed[b] = VAMask2Compressed[Index];
+    }
+
+    for (chunk = 0; chunk < 8; chunk++) {
+      data  = 0;
+      cmask = (MRC_BIT0 << chunk);
+      for (b = 0; b < 32; b++) {
+        if (Compressed[b] & cmask) {
+          data |= (MRC_BIT0 << b);
+        }
+      }
+      //
+      // Set rep = 0 don't want to replicate the data
+      // Set banksel field to the value of the chunk you want to write the 64 bits to.
+      // Set arraysel = 0 ( indicating it is the MC WDB) and mode = 'b01 in the SDAT register
+      //
+      pointer = MRC_BIT16 + chunk;
+      for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+        if (MrcChannelExist (Outputs, Channel)) {
+          Offset = MCHBAR_CH0_CR_QCLK_LDAT_DATAIN_0_REG +
+            ((MCHBAR_CH1_CR_QCLK_LDAT_DATAIN_0_REG - MCHBAR_CH0_CR_QCLK_LDAT_DATAIN_0_REG) * Channel);
+          MrcWriteCR (MrcData, Offset, data);
+          Offset = MCHBAR_CH0_CR_QCLK_LDAT_DATAIN_1_REG +
+            ((MCHBAR_CH1_CR_QCLK_LDAT_DATAIN_1_REG - MCHBAR_CH0_CR_QCLK_LDAT_DATAIN_1_REG) * Channel);
+          MrcWriteCR (MrcData, Offset, data);
+          Offset = MCHBAR_CH0_CR_QCLK_LDAT_SDAT_REG +
+            ((MCHBAR_CH1_CR_QCLK_LDAT_SDAT_REG - MCHBAR_CH0_CR_QCLK_LDAT_SDAT_REG) * Channel);
+          MrcWriteCR (MrcData, Offset, pointer);
+
+          //
+          // Finally, write the PDAT register indicating which cacheline of the WDB you want to write to
+          // by setting fastaddr field to one of the 64 cache lines. Also set cmdb in the pdat register to 4'b1000,
+          // indicating that this is a LDAT write
+          //
+          Scratch = Start + v;
+          Offset = MCHBAR_CH0_CR_QCLK_LDAT_PDAT_REG +
+            ((MCHBAR_CH1_CR_QCLK_LDAT_PDAT_REG - MCHBAR_CH0_CR_QCLK_LDAT_PDAT_REG) * Channel);
+          QclkLdatPdat.Data           = 0;
+          QclkLdatPdat.Bits.CMDB      = 8;
+          QclkLdatPdat.Bits.FASTADDR  = MIN (Scratch, MCHBAR_CH0_CR_QCLK_LDAT_PDAT_FASTADDR_MAX);
+          MrcWriteCR (MrcData, Offset, QclkLdatPdat.Data);
+        }
+      }
+    }
+    //
+    // Circular Rotate Vic/Agg Masks
+    //
+    msb   = (vmask >> 31) & 0x1;
+    vmask = (vmask << 1) | msb;
+    msb   = (amask >> 31) & 0x1;
+    amask = (amask << 1) | msb;
+  }
+  //
+  // Clear LDAT mode
+  //
+  for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+    if (MrcChannelExist (Outputs, Channel)) {
+      Offset = MCHBAR_CH0_CR_QCLK_LDAT_SDAT_REG +
+        ((MCHBAR_CH1_CR_QCLK_LDAT_SDAT_REG - MCHBAR_CH0_CR_QCLK_LDAT_SDAT_REG) * Channel);
+      MrcWriteCR (MrcData, Offset, 0);
+    }
+  }
+
+  return;
+}
+
+/**
+  Write VA pattern in CADB
+  Use basic VA pattern for CADB with 2 LFSRs. Rotation is manual
+  Bit Order is  [CKE[3:0], ODT[3:0], CMD[2:0], CS[3:0], BA[2:0], MA[15:0]]
+  [59:56]  [51:48]  [42:40] [35:32]  [26:24]  [15:0]
+
+  NOTE: CKE, ODT and CS are not used in functional mode and are ignored
+
+  @param[in] MrcData   - Include all MRC global data.
+  @param[in] Channel   - Channel to setup.
+  @param[in] VicSpread - Separation of the Victim Bit.
+  @param[in] VicBit    - The Bit to be the Victim.
+  @param[in] LMNEn     - To enable LMN counter
+
+  @retval Nothing
+**/
+void
+SetupCADB (
+  IN MrcParameters *const MrcData,
+  IN const U8             Channel,
+  IN const U8             VicSpread,
+  IN const U8             VicBit,
+  IN const U8             LMNEn
+  )
+{
+  const U16 seeds[3] = {0xEA1, 0xBEEF, 0xDEAD};
+  U8        Row;
+  U8        bit;
+  U8        lfsr0;
+  U8        lfsr1;
+  U8        bremap;
+  U8        Fine;
+  U32       Offset;
+  MCHBAR_CH0_CR_REUT_CH_PAT_CADB_PROG_STRUCT        ReutChPatCadbProg;
+  MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_CTRL_STRUCT    ReutChPatCadbMuxCtrl;
+  MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_STRUCT  ReutCadbClMuxLmn;
+
+  //
+  // Currently, always start writing at CADB row0.  Could add Start point in future.
+  //
+  Offset = MCHBAR_CH0_CR_REUT_CH_PAT_CADB_WRITE_POINTER_REG +
+    ((MCHBAR_CH1_CR_REUT_CH_PAT_CADB_WRITE_POINTER_REG - MCHBAR_CH0_CR_REUT_CH_PAT_CADB_WRITE_POINTER_REG) * Channel);
+  MrcWriteCR8 (MrcData, Offset, 0);
+
+  //
+  // Plan to use VicSpread of 7 bits
+  // Walk through CADB rows, assigning bit for 1 VA pattern
+  //
+  for (Row = 0; Row < MRC_NUM_CADB_ENTRIES; Row++) {
+
+    lfsr0 = (Row & 0x1);         // 0, 1, 0, 1 0, 1, 0, 1 for r = 0,1, ..., 7
+    lfsr1 = ((Row >> 1) & 0x1);  // 0, 0, 1, 1 0, 0, 1, 1 for r = 0,1, ..., 7
+    //
+    // Assign Victim/Aggressor Bits
+    //
+    ReutChPatCadbProg.Data = 0;
+    for (bit = 0; bit < 22; bit++) {
+      //
+      // b in range(22)
+      //
+      Fine = bit % VicSpread;
+      if (bit >= 19) {
+        bremap = bit + 21; // b = [40-42]
+      } else if (bit >= 16) {
+        bremap = bit + 8; // b = [24-26]
+      } else {
+        bremap = bit; // b = [0-15]
+      }
+
+      if (Fine == VicBit) {
+        ReutChPatCadbProg.Data |= MrcOemMemoryLeftShiftU64 ((U64) lfsr0, bremap);
+      } else {
+        ReutChPatCadbProg.Data |= MrcOemMemoryLeftShiftU64 ((U64) lfsr1, bremap);
+      }
+    }
+    //
+    // Write Row. CADB is auto incremented after every write
+    //
+    Offset = MCHBAR_CH0_CR_REUT_CH_PAT_CADB_PROG_REG +
+      ((MCHBAR_CH1_CR_REUT_CH_PAT_CADB_PROG_REG - MCHBAR_CH0_CR_REUT_CH_PAT_CADB_PROG_REG) * Channel);
+    MrcWriteCR64 (MrcData, Offset, ReutChPatCadbProg.Data);
+  }
+  //
+  // Setup CADB in terms of LFSR selects, LFSR seeds, LMN constants and overall control
+  //
+  Offset = MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_CTRL_REG +
+    ((MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_CTRL_REG - MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_CTRL_REG) * Channel);
+  ReutChPatCadbMuxCtrl.Data               = 0;
+  ReutChPatCadbMuxCtrl.Bits.Mux0_Control  = LMNEn ? 0 : 2;
+  ReutChPatCadbMuxCtrl.Bits.Mux1_Control  = 2;
+  ReutChPatCadbMuxCtrl.Bits.Mux2_Control  = 2;
+  MrcWriteCR (MrcData, Offset, ReutChPatCadbMuxCtrl.Data);
+
+  Offset = MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_REG +
+    ((MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_REG - MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_REG) * Channel);
+  ReutCadbClMuxLmn.Data                         = 0;
+  ReutCadbClMuxLmn.Bits.Enable_Sweep_Frequency  = 1;
+  ReutCadbClMuxLmn.Bits.L_counter               = 1;
+  ReutCadbClMuxLmn.Bits.M_counter               = 1;
+  ReutCadbClMuxLmn.Bits.N_counter               = 6;
+  MrcWriteCR (MrcData, Offset, ReutCadbClMuxLmn.Data);
+
+  Offset = MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_PB_0_REG +
+    ((MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_PB_0_REG - MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_PB_0_REG) * Channel);
+  MrcWriteCR (MrcData, Offset, seeds[0]);
+
+  Offset = MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_PB_1_REG +
+    ((MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_PB_1_REG - MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_PB_1_REG) * Channel);
+  MrcWriteCR (MrcData, Offset, seeds[1]);
+
+  Offset = MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_PB_2_REG +
+    ((MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_PB_2_REG - MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_PB_2_REG) * Channel);
+  MrcWriteCR (MrcData, Offset, seeds[2]);
+
+  return;
+}
+
+/**
+  Program the subsequence type field in a given MCDFXS_CR_REUT_CHx_SUBSEQ_CTL_MCMAIN_x_STRUCT register
+
+  @param[in]      MrcData    - MRC global data
+  @param[in, out] SubSeqCtl  - Address of the MCDFXS_CR_REUT_CHx_SUBSEQ_CTL_MCMAIN_x_STRUCT register
+  @param[in]      Type       - The subsequence type to program
+
+  @retval Nothing.
+**/
+void
+SetSubsequenceType (
+  IN     MrcParameters *const MrcData,
+  IN OUT U32                  *SubSeqCtl,
+  IN     U32                  Type
+  )
+{
+  const MrcInput  *Inputs;
+
+  Inputs = &MrcData->SysIn.Inputs;
+
+  if ((Inputs->CpuModel == cmHSW) && (Inputs->CpuStepping == csHswA0)) {
+    ((MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_STRUCT_HSW_A0 *) (SubSeqCtl))->Bits.Subsequence_Type = Type;
+  } else {
+    ((MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_STRUCT *) (SubSeqCtl))->Bits.Subsequence_Type = Type;
+  }
+}
+
+/**
+  This function handles writing to the REUT Addressing sequence for IO Tests.
+  To not write a certain parameter, pass a NULL pointer to the function.
+
+  @param[in] MrcData       - MRC global data structure.
+  @param[in] Channel       - Specifies the channel to program.
+  @param[in] StartAddr     - Start value for Rank/Bank/Row/Col.
+  @param[in] StopAddr      - Stop value for Rank/Bank/Row/Col.
+  @param[in] FieldOrder    - Relative order for carry propagates of Rank/Bank/Row/Col.
+  @param[in] IncRate       - The number of writes to Rank/Bank/Row/Col before updating the address.
+                              Note: The function will handle linear vs exponential and a value of 0 specifies a rate of 1.
+  @param[in] IncValue      - The amount to increase Rank/Bank/Row/Col address.
+  @param[in] WrapTriggerEn - Enables wrap trigger for Rank/Bank/Row/Col to enable stopping on subsequence and sequence.
+  @param[in] WrapCarryEn   - Enables carry propagation on wrap to the next higest order field
+  @param[in] AddrInvertEn  - Enables inverting the Rank/Bank/Row/Col addresses based on AddrInvertRate.
+  @param[in] AddrIvertRate - Exponential rate of address inversion.  Only updated if AddrInvertEn != NULL.
+  @param[in] EnableDebug   - Enables/Disables debug printing.
+
+  @retval Nothing
+**/
+void
+MrcProgramSequenceAddress (
+  IN MrcParameters *const MrcData,
+  IN const U8             Channel,
+  IN const U16            StartAddr[MrcReutFieldMax],
+  IN const U16            StopAddr[MrcReutFieldMax],
+  IN const U8             FieldOrder[MrcReutFieldMax],
+  IN const U32            IncRate[MrcReutFieldMax],
+  IN const U16            IncValue[MrcReutFieldMax],
+  IN const U8             WrapTriggerEn[MrcReutFieldMax],
+  IN const U8             WrapCarryEn[MrcReutFieldMax],
+  IN const U8             AddrInvertEn[MrcReutFieldMax],
+  IN const U8             AddrInvertRate,
+  IN const BOOL           EnableDebug
+  )
+{
+  MrcInput  *Inputs;
+  U64       RowMask;
+  U32       ColumnMask;
+  U32       CrOffset;
+  U32       IncRateScratch;
+  U16       ColAddrIncMax;
+  MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_0_STRUCT                   ReutChSeqBaseAddrStart;
+  MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_0_STRUCT                    ReutChSeqBaseAddrWrap;
+  MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_STRUCT                 ReutChSeqBaseAddrIncCtl;
+  MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_STRUCT  ReutChSeqBaseAddrOrderCarryInvertCtl;
+#ifdef MRC_DEBUG_PRINT
+  MrcDebug  *Debug;
+  Debug = &MrcData->SysIn.Inputs.Debug;
+#endif
+
+  Inputs = &MrcData->SysIn.Inputs;
+
+  //
+  // @todo: Review next stepping
+  //
+  RowMask = (U64) MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_0_Row_Address_MSK;
+  switch (Inputs->CpuModel) {
+    case cmHSW:
+      if (Inputs->CpuStepping == csHswA0) {
+        ColumnMask = MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_0_Column_Address_MSK_A0;
+        ColAddrIncMax = MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Column_Base_Address_Increment_MAX_A0;
+      } else {
+        ColumnMask = MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_0_Column_Address_MSK;
+        ColAddrIncMax = MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Column_Base_Address_Increment_MAX;
+      }
+      break;
+
+    case cmHSW_ULT:
+    case cmCRW:
+      ColumnMask = MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_0_Column_Address_MSK;
+      ColAddrIncMax = MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Column_Base_Address_Increment_MAX;
+      break;
+
+    default:
+      MRC_DEBUG_MSG (
+        Debug,
+        MSG_LEVEL_NOTE,
+        "Invalid CPU Type in MrcProgramSequenceAddress.  Defaulting to Hsw last stepping: %x.\n",
+        csHswLast
+        );
+      ColumnMask = MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_0_Column_Address_MSK;
+      ColAddrIncMax = MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Column_Base_Address_Increment_MAX;
+  }
+
+#ifdef MRC_DEBUG_PRINT
+  if (EnableDebug) {
+    MRC_DEBUG_MSG (
+      Debug,
+      MSG_LEVEL_NOTE,
+      "Ch.%d Masks: Col - 0x%x\t Row - 0x%08x%08x\tColAddrIncMax: 0x%x\n",
+      Channel,
+      ColumnMask,
+      (U32) MrcOemMemoryRightShiftU64 (RowMask, 32),
+      (U32) RowMask,
+      ColAddrIncMax
+      );
+  }
+#endif
+
+  if (StartAddr != NULL) {
+    ReutChSeqBaseAddrStart.Data = MrcOemMemoryLeftShiftU64 (
+                                    (U64) ((StartAddr[MrcReutFieldRank] << (56 - 32)) + (StartAddr[MrcReutFieldBank] << (48 - 32))),
+                                    32
+                                    );
+    ReutChSeqBaseAddrStart.Data |= MrcOemMemoryLeftShiftU64 ((U64) StartAddr[MrcReutFieldRow], 24) & RowMask;
+    ReutChSeqBaseAddrStart.Data |= StartAddr[MrcReutFieldCol] & ColumnMask;
+
+    CrOffset = MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_0_REG +
+      (
+        (MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_1_REG - MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_0_REG)
+        * Channel
+      );
+    MrcWriteCR64 (MrcData, CrOffset, ReutChSeqBaseAddrStart.Data);
+
+#ifdef MRC_DEBUG_PRINT
+    if (EnableDebug) {
+      MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Start:\n\tField\tInput\t\tStruct\n");
+      MRC_DEBUG_MSG (
+        Debug,
+        MSG_LEVEL_NOTE,
+        "\tCol:\t0x%x\t\t0x%x\n",
+        StartAddr[MrcReutFieldCol],
+        ReutChSeqBaseAddrStart.Data & ColumnMask
+        );
+      MRC_DEBUG_MSG (
+        Debug,
+        MSG_LEVEL_NOTE,
+        "\tRow:\t0x%x\t\t0x%x\n",
+        StartAddr[MrcReutFieldRow],
+        MrcOemMemoryRightShiftU64 (ReutChSeqBaseAddrStart.Data, 24) & MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_0_Row_Address_MAX
+        );
+      MRC_DEBUG_MSG (
+        Debug,
+        MSG_LEVEL_NOTE,
+        "\tBank:\t0x%x\t\t0x%x\n",
+        StartAddr[MrcReutFieldBank],
+        MrcOemMemoryRightShiftU64 (ReutChSeqBaseAddrStart.Data, 48) & MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_0_Bank_Address_MAX
+        );
+      MRC_DEBUG_MSG (
+        Debug,
+        MSG_LEVEL_NOTE,
+        "\tRank:\t0x%x\t\t0x%x\n",
+        StartAddr[MrcReutFieldRank],
+        MrcOemMemoryRightShiftU64 (ReutChSeqBaseAddrStart.Data, 56) & MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_0_Rank_Address_MAX
+        );
+    }
+#endif
+  }
+
+  if (StopAddr != NULL) {
+    ReutChSeqBaseAddrWrap.Data = MrcOemMemoryLeftShiftU64 (
+                                  (U64) ((StopAddr[MrcReutFieldRank] << (56 - 32)) + (StopAddr[MrcReutFieldBank] << (48 - 32))),
+                                  32
+                                  );
+    ReutChSeqBaseAddrWrap.Data |= MrcOemMemoryLeftShiftU64 ((U64) StopAddr[MrcReutFieldRow], 24) & RowMask;
+    ReutChSeqBaseAddrWrap.Data |= StopAddr[MrcReutFieldCol] & ColumnMask;
+
+    CrOffset = MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_0_REG +
+      (
+        (MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_1_REG - MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_0_REG)
+        * Channel
+      );
+    MrcWriteCR64 (MrcData, CrOffset, ReutChSeqBaseAddrWrap.Data);
+
+#ifdef MRC_DEBUG_PRINT
+    if (EnableDebug) {
+      MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Stop:\n\tField\tInput\t\tStruct\n");
+      MRC_DEBUG_MSG (
+        Debug,
+        MSG_LEVEL_NOTE,
+        "\tCol:\t0x%x\t\t0x%x\n",
+        StopAddr[MrcReutFieldCol],
+        ReutChSeqBaseAddrWrap.Data & ColumnMask
+        );
+      MRC_DEBUG_MSG (
+        Debug,
+        MSG_LEVEL_NOTE,
+        "\tRow:\t0x%x\t\t0x%x\n",
+        StopAddr[MrcReutFieldRow],
+        MrcOemMemoryRightShiftU64 (ReutChSeqBaseAddrWrap.Data, 24) & MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_0_Row_Address_MAX
+        );
+      MRC_DEBUG_MSG (
+        Debug,
+        MSG_LEVEL_NOTE,
+        "\tBank:\t0x%x\t\t0x%x\n",
+        StopAddr[MrcReutFieldBank],
+        MrcOemMemoryRightShiftU64 (ReutChSeqBaseAddrWrap.Data, 48) & MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_0_Bank_Address_MAX
+        );
+      MRC_DEBUG_MSG (
+        Debug,
+        MSG_LEVEL_NOTE,
+        "\tRank:\t0x%x\t\t0x%x\n",
+        StopAddr[MrcReutFieldRank],
+        MrcOemMemoryRightShiftU64 (ReutChSeqBaseAddrWrap.Data, 56) & MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_0_Rank_Address_MAX
+        );
+    }
+#endif
+  }
+
+  if (FieldOrder != NULL || WrapTriggerEn != NULL || WrapCarryEn != NULL || AddrInvertEn != NULL) {
+    ReutChSeqBaseAddrOrderCarryInvertCtl.Data = 0;
+
+    CrOffset = MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_REG +
+      (
+        (
+          MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_REG -
+          MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_REG
+        ) * Channel
+      );
+
+    if (FieldOrder == NULL || WrapTriggerEn == NULL || WrapCarryEn == NULL || AddrInvertEn == NULL) {
+      ReutChSeqBaseAddrOrderCarryInvertCtl.Data = MrcReadCR (MrcData, CrOffset);
+    }
+
+    if (FieldOrder != NULL) {
+      ReutChSeqBaseAddrOrderCarryInvertCtl.Bits.Base_Column_Address_Order = FieldOrder[MrcReutFieldCol];
+      ReutChSeqBaseAddrOrderCarryInvertCtl.Bits.Base_Row_Address_Order    = FieldOrder[MrcReutFieldRow];
+      ReutChSeqBaseAddrOrderCarryInvertCtl.Bits.Base_Bank_Address_Order   = FieldOrder[MrcReutFieldBank];
+      ReutChSeqBaseAddrOrderCarryInvertCtl.Bits.Base_Rank_Address_Order   = FieldOrder[MrcReutFieldRank];
+
+#ifdef MRC_DEBUG_PRINT
+      if (EnableDebug) {
+        MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Order:\n\tField\tInput\t\tStruct\t\t\n");
+        MRC_DEBUG_MSG (
+          Debug,
+          MSG_LEVEL_NOTE,
+          "\tCol:\t0x%x\t\t0x%x\t\t\n",
+          FieldOrder[MrcReutFieldCol],
+          ReutChSeqBaseAddrOrderCarryInvertCtl.Bits.Base_Column_Address_Order
+          );
+        MRC_DEBUG_MSG (
+          Debug,
+          MSG_LEVEL_NOTE,
+          "\tRow:\t0x%x\t\t0x%x\t\t\n",
+          FieldOrder[MrcReutFieldRow],
+          ReutChSeqBaseAddrOrderCarryInvertCtl.Bits.Base_Row_Address_Order
+          );
+        MRC_DEBUG_MSG (
+          Debug,
+          MSG_LEVEL_NOTE,
+          "\tBank:\t0x%x\t\t0x%x\t\t\n",
+          FieldOrder[MrcReutFieldBank],
+          ReutChSeqBaseAddrOrderCarryInvertCtl.Bits.Base_Bank_Address_Order
+          );
+        MRC_DEBUG_MSG (
+          Debug,
+          MSG_LEVEL_NOTE,
+          "\tRank:\t0x%x\t\t0x%x\t\t\n",
+          FieldOrder[MrcReutFieldRank],
+          ReutChSeqBaseAddrOrderCarryInvertCtl.Bits.Base_Rank_Address_Order
+          );
+      }
+#endif
+    }
+
+    if (WrapTriggerEn != NULL) {
+      ReutChSeqBaseAddrOrderCarryInvertCtl.Bits.Column_Base_Wrap_Trigger_Enable = WrapTriggerEn[MrcReutFieldCol];
+      ReutChSeqBaseAddrOrderCarryInvertCtl.Bits.Row_Base_Wrap_Trigger_Enable    = WrapTriggerEn[MrcReutFieldRow];
+      ReutChSeqBaseAddrOrderCarryInvertCtl.Bits.Bank_Base_Wrap_Trigger_Enable   = WrapTriggerEn[MrcReutFieldBank];
+      ReutChSeqBaseAddrOrderCarryInvertCtl.Bits.Rank_Base_Wrap_Trigger_Enable   = WrapTriggerEn[MrcReutFieldRank];
+#ifdef MRC_DEBUG_PRINT
+      if (EnableDebug) {
+        MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "WrapT:\n\tField\tInput\t\tStruct\t\t\n");
+        MRC_DEBUG_MSG (
+          Debug,
+          MSG_LEVEL_NOTE,
+          "\tCol:\t0x%x\t\t0x%x\t\t\n",
+          WrapTriggerEn[MrcReutFieldCol],
+          ReutChSeqBaseAddrOrderCarryInvertCtl.Bits.Column_Base_Wrap_Trigger_Enable
+          );
+        MRC_DEBUG_MSG (
+          Debug,
+          MSG_LEVEL_NOTE,
+          "\tRow:\t0x%x\t\t0x%x\t\t\n",
+          WrapTriggerEn[MrcReutFieldRow],
+          ReutChSeqBaseAddrOrderCarryInvertCtl.Bits.Row_Base_Wrap_Trigger_Enable
+          );
+        MRC_DEBUG_MSG (
+          Debug,
+          MSG_LEVEL_NOTE,
+          "\tBank:\t0x%x\t\t0x%x\t\t\n",
+          WrapTriggerEn[MrcReutFieldBank],
+          ReutChSeqBaseAddrOrderCarryInvertCtl.Bits.Bank_Base_Wrap_Trigger_Enable
+          );
+        MRC_DEBUG_MSG (
+          Debug,
+          MSG_LEVEL_NOTE,
+          "\tRank:\t0x%x\t\t0x%x\t\t\n",
+          WrapTriggerEn[MrcReutFieldRank],
+          ReutChSeqBaseAddrOrderCarryInvertCtl.Bits.Rank_Base_Wrap_Trigger_Enable
+          );
+      }
+#endif
+    }
+
+    if (WrapCarryEn != NULL) {
+      ReutChSeqBaseAddrOrderCarryInvertCtl.Bits.Column_Base_Wrap_Carry_Enable = WrapCarryEn[MrcReutFieldCol];
+      ReutChSeqBaseAddrOrderCarryInvertCtl.Bits.Row_Base_Wrap_Carry_Enable    = WrapCarryEn[MrcReutFieldRow];
+      ReutChSeqBaseAddrOrderCarryInvertCtl.Bits.Bank_Base_Wrap_Carry_Enable   = WrapCarryEn[MrcReutFieldBank];
+      ReutChSeqBaseAddrOrderCarryInvertCtl.Bits.Rank_Base_Wrap_Carry_Enable   = WrapCarryEn[MrcReutFieldRank];
+
+#ifdef MRC_DEBUG_PRINT
+      if (EnableDebug) {
+        MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "WrapC:\n\tField\tInput\t\tStruct\t\t\n");
+        MRC_DEBUG_MSG (
+          Debug,
+          MSG_LEVEL_NOTE,
+          "\tCol:\t0x%x\t\t0x%x\t\t\n",
+          WrapCarryEn[MrcReutFieldCol],
+          ReutChSeqBaseAddrOrderCarryInvertCtl.Bits.Column_Base_Wrap_Carry_Enable
+          );
+        MRC_DEBUG_MSG (
+          Debug,
+          MSG_LEVEL_NOTE,
+          "\tRow:\t0x%x\t\t0x%x\t\t\n",
+          WrapCarryEn[MrcReutFieldRow],
+          ReutChSeqBaseAddrOrderCarryInvertCtl.Bits.Row_Base_Wrap_Carry_Enable
+          );
+        MRC_DEBUG_MSG (
+          Debug,
+          MSG_LEVEL_NOTE,
+          "\tBank:\t0x%x\t\t0x%x\t\t\n",
+          WrapCarryEn[MrcReutFieldBank],
+          ReutChSeqBaseAddrOrderCarryInvertCtl.Bits.Bank_Base_Wrap_Carry_Enable
+          );
+        MRC_DEBUG_MSG (
+          Debug,
+          MSG_LEVEL_NOTE,
+          "\tRank:\t0x%x\t\t0x%x\t\t\n",
+          WrapCarryEn[MrcReutFieldRank],
+          ReutChSeqBaseAddrOrderCarryInvertCtl.Bits.Rank_Base_Wrap_Carry_Enable
+          );
+      }
+#endif
+    }
+
+    if (AddrInvertEn != NULL) {
+      ReutChSeqBaseAddrOrderCarryInvertCtl.Bits.Base_Address_Invert_Rate          = AddrInvertRate;
+      ReutChSeqBaseAddrOrderCarryInvertCtl.Bits.Column_Base_Address_Invert_Enable = AddrInvertEn[MrcReutFieldCol];
+      ReutChSeqBaseAddrOrderCarryInvertCtl.Bits.Row_Base_Address_Invert_Enable    = AddrInvertEn[MrcReutFieldRow];
+      ReutChSeqBaseAddrOrderCarryInvertCtl.Bits.Bank_Base_Address_Invert_Enable   = AddrInvertEn[MrcReutFieldBank];
+      ReutChSeqBaseAddrOrderCarryInvertCtl.Bits.Rank_Base_Address_Invert_Enable   = AddrInvertEn[MrcReutFieldRank];
+
+#ifdef MRC_DEBUG_PRINT
+      if (EnableDebug) {
+        MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "InvtEn:\n\tField\tInput\t\tStruct\t\t\n");
+        MRC_DEBUG_MSG (
+          Debug,
+          MSG_LEVEL_NOTE,
+          "\tCol:\t0x%x\t\t0x%x\t\t\n",
+          AddrInvertEn[MrcReutFieldCol],
+          ReutChSeqBaseAddrOrderCarryInvertCtl.Bits.Column_Base_Address_Invert_Enable
+          );
+        MRC_DEBUG_MSG (
+          Debug,
+          MSG_LEVEL_NOTE,
+          "\tRow:\t0x%x\t\t0x%x\t\t\n",
+          AddrInvertEn[MrcReutFieldRow],
+          ReutChSeqBaseAddrOrderCarryInvertCtl.Bits.Row_Base_Address_Invert_Enable
+          );
+        MRC_DEBUG_MSG (
+          Debug,
+          MSG_LEVEL_NOTE,
+          "\tBank:\t0x%x\t\t0x%x\t\t\n",
+          AddrInvertEn[MrcReutFieldBank],
+          ReutChSeqBaseAddrOrderCarryInvertCtl.Bits.Bank_Base_Address_Invert_Enable
+          );
+        MRC_DEBUG_MSG (
+          Debug,
+          MSG_LEVEL_NOTE,
+          "\tRank:\t0x%x\t\t0x%x\t\t\n",
+          AddrInvertEn[MrcReutFieldRank],
+          ReutChSeqBaseAddrOrderCarryInvertCtl.Bits.Rank_Base_Address_Invert_Enable
+          );
+        MRC_DEBUG_MSG (
+          Debug,
+          MSG_LEVEL_NOTE,
+          "\tRate:\t0x%x\t\t0x%x\t\t\n",
+          AddrInvertRate,
+          ReutChSeqBaseAddrOrderCarryInvertCtl.Bits.Base_Address_Invert_Rate
+          );
+      }
+#endif
+    }
+
+    MrcWriteCR (MrcData, CrOffset, ReutChSeqBaseAddrOrderCarryInvertCtl.Data);
+  }
+
+  if (IncRate != 0 || IncValue != 0) {
+    ReutChSeqBaseAddrIncCtl.Data = 0;
+
+    CrOffset = MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_REG +
+      (
+        (MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_REG - MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_REG)
+        * Channel
+      );
+
+    if (IncRate == 0 || IncValue == 0) {
+      ReutChSeqBaseAddrIncCtl.Data = MrcReadCR64 (MrcData, CrOffset);
+    }
+
+    if (IncRate != 0) {
+      //
+      // RANK
+      //
+      IncRateScratch = (IncRate[MrcReutFieldRank] > 31) ? (MrcLog2 (IncRate[MrcReutFieldRank] - 1)) :
+                                                          (128 + IncRate[MrcReutFieldRank]);
+      ReutChSeqBaseAddrIncCtl.Bits.Rank_Base_Address_Update_Rate  = IncRateScratch;
+      ReutChSeqBaseAddrIncCtl.Bits.Rank_Base_Address_Update_Scale = IncRateScratch >> 7;
+      //
+      // BANK
+      //
+      IncRateScratch = (IncRate[MrcReutFieldBank] > 31) ? (MrcLog2 (IncRate[MrcReutFieldBank] - 1)) :
+                                                          (128 + IncRate[MrcReutFieldBank]);
+      ReutChSeqBaseAddrIncCtl.Bits.Bank_Base_Address_Update_Rate  = IncRateScratch;
+      ReutChSeqBaseAddrIncCtl.Bits.Bank_Base_Address_Update_Scale = IncRateScratch >> 7;
+      //
+      // ROW
+      //
+      IncRateScratch = (IncRate[MrcReutFieldRow] > 15) ? (MrcLog2 (IncRate[MrcReutFieldRow] - 1)) :
+                                                         (32 + IncRate[MrcReutFieldRow]);
+      ReutChSeqBaseAddrIncCtl.Bits.Row_Base_Address_Update_Rate   = IncRateScratch;
+      ReutChSeqBaseAddrIncCtl.Bits.Row_Base_Address_Update_Scale  = IncRateScratch >> 5;
+      //
+      // COL
+      //
+      IncRateScratch = (IncRate[MrcReutFieldCol] > 31) ? (MrcLog2 (IncRate[MrcReutFieldCol] - 1)) :
+                                                         (128 + IncRate[MrcReutFieldCol]);
+      ReutChSeqBaseAddrIncCtl.Bits.Column_Base_Address_Update_Rate  = IncRateScratch;
+      ReutChSeqBaseAddrIncCtl.Bits.Column_Base_Address_Update_Scale = IncRateScratch >> 7;
+
+#ifdef MRC_DEBUG_PRINT
+      if (EnableDebug) {
+        MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "IncRate:\n\tField\tInput\t\tStruct\t\tScale\n");
+        MRC_DEBUG_MSG (
+          Debug,
+          MSG_LEVEL_NOTE,
+          "\tCol:\t0x%x\t\t0x%x\t\t0x%x\n",
+          IncRate[MrcReutFieldCol],
+          ReutChSeqBaseAddrIncCtl.Bits.Column_Base_Address_Update_Rate,
+          ReutChSeqBaseAddrIncCtl.Bits.Column_Base_Address_Update_Scale
+          );
+        MRC_DEBUG_MSG (
+          Debug,
+          MSG_LEVEL_NOTE,
+          "\tRow:\t0x%x\t\t0x%x\t\t0x%x\n",
+          IncRate[MrcReutFieldRow],
+          ReutChSeqBaseAddrIncCtl.Bits.Row_Base_Address_Update_Rate,
+          ReutChSeqBaseAddrIncCtl.Bits.Row_Base_Address_Update_Scale
+          );
+        MRC_DEBUG_MSG (
+          Debug,
+          MSG_LEVEL_NOTE,
+          "\tBank:\t0x%x\t\t0x%x\t\t0x%x\n",
+          IncRate[MrcReutFieldBank],
+          ReutChSeqBaseAddrIncCtl.Bits.Bank_Base_Address_Update_Rate,
+          ReutChSeqBaseAddrIncCtl.Bits.Bank_Base_Address_Update_Scale
+          );
+        MRC_DEBUG_MSG (
+          Debug,
+          MSG_LEVEL_NOTE,
+          "\tRank:\t0x%x\t\t0x%x\t\t0x%x\n",
+          IncRate[MrcReutFieldRank],
+          ReutChSeqBaseAddrIncCtl.Bits.Rank_Base_Address_Update_Rate,
+          ReutChSeqBaseAddrIncCtl.Bits.Rank_Base_Address_Update_Scale
+          );
+      }
+#endif
+    }
+
+    if (IncValue != 0) {
+      ReutChSeqBaseAddrIncCtl.Bits.Rank_Base_Address_Increment    = IncValue[MrcReutFieldRank];
+      ReutChSeqBaseAddrIncCtl.Bits.Bank_Base_Address_Increment    = IncValue[MrcReutFieldBank];
+      ReutChSeqBaseAddrIncCtl.Bits.Row_Base_Address_Increment     = IncValue[MrcReutFieldRow];
+      ReutChSeqBaseAddrIncCtl.Bits.Column_Base_Address_Increment  = IncValue[MrcReutFieldCol] & ColAddrIncMax;
+
+#ifdef MRC_DEBUG_PRINT
+      if (EnableDebug) {
+        MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "IncVal:\n\tField\tInput\t\tStruct\t\t\n");
+        MRC_DEBUG_MSG (
+          Debug,
+          MSG_LEVEL_NOTE,
+          "\tCol:\t0x%x\t\t0x%x\t\t\n",
+          IncValue[MrcReutFieldCol],
+          ReutChSeqBaseAddrIncCtl.Bits.Column_Base_Address_Increment
+          );
+        MRC_DEBUG_MSG (
+          Debug,
+          MSG_LEVEL_NOTE,
+          "\tRow:\t0x%x\t\t0x%x\t\t\n",
+          IncValue[MrcReutFieldRow],
+          ReutChSeqBaseAddrIncCtl.Bits.Row_Base_Address_Increment
+          );
+        MRC_DEBUG_MSG (
+          Debug,
+          MSG_LEVEL_NOTE,
+          "\tBank:\t0x%x\t\t0x%x\t\t\n",
+          IncValue[MrcReutFieldBank],
+          ReutChSeqBaseAddrIncCtl.Bits.Bank_Base_Address_Increment
+          );
+        MRC_DEBUG_MSG (
+          Debug,
+          MSG_LEVEL_NOTE,
+          "\tRank:\t0x%x\t\t0x%x\t\t\n",
+          IncValue[MrcReutFieldRank],
+          ReutChSeqBaseAddrIncCtl.Bits.Rank_Base_Address_Increment
+          );
+      }
+#endif
+    }
+
+    MrcWriteCR64 (MrcData, CrOffset, ReutChSeqBaseAddrIncCtl.Data);
+  }
+}
+
+/**
+  Programs all the key registers to define a CPCG test
+
+  @param[in] MrcData     - Include all MRC global data.
+  @param[in] WDBPattern  - Structure that stores start, Stop, IncRate and Dqpat for pattern.
+  @param[in] ChbitMask   - Channel Bit mak for which test should be setup for.
+  @param[in] CmdPat      - [0: PatWrRd (Standard Write/Read Loopback),
+                            1: PatWr (Write Only),
+                            2: PatRd (Read Only),
+                            3: PatRdWrTA (ReadWrite Turnarounds),
+                            4: PatWrRdTA (WriteRead Turnarounds),
+                            5: PatODTTA (ODT Turnaround]
+  @param[in] NumCL       - Number of Cache lines
+  @param[in] LC          - Loop Count exponent
+  @param[in] REUTAddress - Structure that stores start, stop and increment details for address
+  @param[in] SOE         - [0: Never Stop, 1: Stop on Any Lane, 2: Stop on All Byte, 3: Stop on All Lane]
+  @param[in] WDBPattern  - Structure that stores start, Stop, IncRate and Dqpat for pattern.
+  @param[in] EnCADB      - Enable test to write random deselect packages on bus to create xtalk/isi
+  @param[in] EnCKE       - Enable CKE power down by adding 64
+  @param[in] SubSeqWait  - # of Dclks to stall at the end of a sub-sequence
+
+  @retval Nothing
+**/
+void
+SetupIOTest(
+  IN MrcParameters *const         MrcData,
+  IN const U8                     ChbitMask,
+  IN const U8                     CmdPat,
+  IN const U16                    NumCL,
+  IN const U8                     LC,
+  IN const MRC_REUTAddress *const REUTAddress,
+  IN const U8                     SOE,
+  IN MRC_WDBPattern *const        WDBPattern,
+  IN const U8                     EnCADB,
+  IN const U8                     EnCKE,
+  IN U16                          SubSeqWait
+  )
+{
+  const MrcDebug  *Debug;
+  const MrcInput  *Inputs;
+  const U8        WrapCarryEn[MrcReutFieldMax]   = {0, 0, 0, 0}; // Not used in training tests
+  const U8        WrapTriggerEn[MrcReutFieldMax] = {0, 0, 0, 0}; // Not used in training tests
+  const U8        AddrInvertEn[MrcReutFieldMax]  = {0, 0, 0, 0}; // Not used in training tests
+  MrcOutput       *Outputs;
+  U8              Channel;
+  S8              LCeff;
+  U32             LoopCountLinear;
+  U8              Mux0;
+  U8              Reload;
+  U8              Save;
+  U8              NumCLCR;
+  U8              NumCL2CR;
+  U16             Wait;
+  U16             NumCL2;
+  U32             LMNFreq[2];
+  U32             Offset;
+  U8              SubSeqStart;
+  U8              SubSeqEnd;
+  U8              Index;
+  MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_STRUCT              ReutChPatCadbCtrl;
+  MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_STRUCT               ReutChSeqCfg;
+  MCSCHEDS_CR_PM_PDWN_CONFIG_STRUCT                       PmPdwnConfig;
+  MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_STRUCT_HSW_A0    ReutSubSeqCtl0HswA0;
+  MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_STRUCT           ReutSubSeqCtl0;
+  U32                                                     ReutSubSeqCtl0Data;
+  MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_STRUCT           ReutSubSeqCtl1;
+  MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_CTRL_STRUCT            ReutChPatWdbCl;
+  MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_STRUCT         ReutChPatWdbClMuxCfg;
+  MCHBAR_CH0_CR_REUT_CH_ERR_CTL_STRUCT                    ReutChErrCtrl;
+  MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_0_STRUCT     ReutChSeqDummyReadCtl;
+  struct LocalSubSeqCtl {
+    U8  ValidMask;
+    MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_STRUCT Ctl[8];
+  } SubSeq;
+
+  Outputs = &MrcData->SysOut.Outputs;
+  Inputs  = &MrcData->SysIn.Inputs;
+  Debug   = &Inputs->Debug;
+
+  //
+  // Prepare variables needed for both channels
+  //
+  // Check for the cases where this MUST be 1: When we manually walk through SUBSEQ ODT and TAWR
+  //
+  LCeff = LC - MrcLog2 (NumCL - 1) + 1;
+  if ((LCeff < 1) || (CmdPat == PatWrRdTA) || (CmdPat == PatODTTA)) {
+    LCeff = 1;
+  }
+
+  LoopCountLinear = 1 << (LCeff - 1);
+
+  if (NumCL > 127) {
+    NumCLCR = MrcLog2 (NumCL - 1);       // Assume Exponential number
+  } else {
+    NumCLCR = (U8) NumCL + (MRC_BIT0 << 7);  // Set Number of Cache Lines as linear number
+  }
+
+  NumCL2 = 2 * NumCL;
+  if (NumCL2 > 127) {
+    NumCL2CR = MrcLog2 (NumCL2 - 1);    // Assume Exponential number
+  } else {
+    NumCL2CR = (U8) NumCL2 + (MRC_BIT0 << 7); // Set Number of Cache Lines as linear number
+  }
+
+  Reload = MrcLog2 (WDBPattern->IncRate - 1);
+  //
+  // @todo: 'Save' is initialized but never used.
+  //
+  Save = Reload + MrcLog2 ((WDBPattern->Stop - WDBPattern->Start - 1) & 0xFF);
+
+  if (WDBPattern->IncRate > 31) {
+    WDBPattern->IncRate = Reload;
+  } else {
+    WDBPattern->IncRate += 32;
+  }
+
+  if (EnCKE) {
+    //
+    // @todo: Need to check that PDWN is programmed already.
+    //
+    PmPdwnConfig.Data = MrcReadCR (MrcData, MCSCHEDS_CR_PM_PDWN_CONFIG_REG);
+    Wait = (U16) (PmPdwnConfig.Bits.PDWN_idle_counter + 16); // Adding extra DCKs, 16,  to make sure we make it to power down.
+    if (Wait > SubSeqWait) {
+      SubSeqWait = Wait;
+    }
+  }
+
+  if (SubSeqWait > 0xFF) {
+    SubSeqWait = 0xFF;
+  }
+  //
+  // Per channel settings
+  //
+  for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+    if (!((MRC_BIT0 << Channel) & ChbitMask)) {
+      Offset = MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_REG +
+        ((MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_REG - MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_REG) * Channel);
+      MrcWriteCR (MrcData, Offset, 0);   // Clear global control
+      continue;
+    }
+
+    //###########################################################
+    //
+    // Program CADB
+    //
+    //###########################################################
+    Offset = MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_REG +
+      ((MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_REG - MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_REG) * Channel);
+    ReutChPatCadbCtrl.Data = 0;
+    ReutChPatCadbCtrl.Bits.Enable_CADB_on_Deselect = EnCADB;
+    MrcWriteCR8 (MrcData, Offset, (U8) ReutChPatCadbCtrl.Data);
+    if (EnCADB) {
+      SetupCADB (MrcData, Channel, 7, 8, 0);   // LMNEn=0
+    }
+
+    //###########################################################
+    //
+    // Program Sequence
+    //
+    //###########################################################
+    SubSeqStart = SubSeqEnd = 0;
+    switch (CmdPat) {
+      case PatWrRd:
+        SubSeqEnd = 1;
+        break;
+
+      case PatWr:
+        break;
+
+      case PatRd:
+        SubSeqStart = SubSeqEnd = 1;
+        break;
+
+      case PatRdWrTA:
+        break;
+
+      case PatWrRdTA:
+        SubSeqEnd = 7;
+        break;
+
+      case PatODTTA:
+        SubSeqEnd = 3;
+        break;
+
+      default:
+        MRC_DEBUG_MSG (Debug, MSG_LEVEL_ERROR, "SetupIOTest: Unknown value for Pattern\n");
+        break;
+    }
+    ReutChSeqCfg.Data                             = 0;
+    ReutChSeqCfg.Bits.Subsequence_Start_Pointer   = SubSeqStart;
+    ReutChSeqCfg.Bits.Subsequence_End_Pointer     = SubSeqEnd;
+    ReutChSeqCfg.Bits.Initialization_Mode         = REUT_Testing_Mode;
+    ReutChSeqCfg.Bits.Global_Control              = 1;
+    ReutChSeqCfg.Bits.Enable_Dummy_Reads          = MIN (
+                                                      Outputs->EnDumRd,
+                                                      MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Enable_Dummy_Reads_MAX
+                                                      );
+    if (CmdPat == DimmTest) { // Inc address based on LC
+      ReutChSeqCfg.Bits.Address_Update_Rate_Mode  = 1;
+    }
+    ReutChSeqCfg.Bits.Start_Test_Delay            = 2;
+
+    if (
+        (Inputs->CpuModel == cmHSW && Inputs->CpuStepping < csHswC0) ||
+        (Inputs->CpuModel == cmCRW && Inputs->CpuStepping < csCrwC0) ||
+        (Inputs->CpuModel == cmHSW_ULT && Inputs->CpuStepping < csHswUltC0)
+       ) {
+      ReutChSeqCfg.Bits.Loopcount = MIN (LCeff, MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Loopcount_MAX);
+    } else {
+      Offset = MCDFXS_CR_REUT_CH_SEQ_LOOPCOUNT_LIMIT_MCMAIN_0_REG +
+        (
+          (MCDFXS_CR_REUT_CH_SEQ_LOOPCOUNT_LIMIT_MCMAIN_1_REG - MCDFXS_CR_REUT_CH_SEQ_LOOPCOUNT_LIMIT_MCMAIN_0_REG) *
+          Channel
+        );
+      MrcWriteCR (MrcData, Offset, LoopCountLinear);
+    }
+
+    Offset = MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_REG +
+      ((MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_REG - MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_REG) * Channel);
+    MrcWriteCR64 (MrcData, Offset, ReutChSeqCfg.Data);
+    //MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "SetupIOTest: C%d REUT_CH_SEQ_CFG_0 = 0x%X %X\n", Channel, ReutChSeqCfg.Data32[1], ReutChSeqCfg.Data32[0]);
+
+    Offset = MCDFXS_CR_REUT_CH_SEQ_CTL_MCMAIN_0_REG +
+      ((MCDFXS_CR_REUT_CH_SEQ_CTL_MCMAIN_1_REG - MCDFXS_CR_REUT_CH_SEQ_CTL_MCMAIN_0_REG) * Channel);
+    MrcWriteCR8 (MrcData, Offset, MCDFXS_CR_REUT_CH_SEQ_CTL_MCMAIN_0_Local_Clear_Errors_MSK);
+
+    //###########################################################
+    //
+    // Program Sub Sequences
+    //
+    //###########################################################
+    if ((Inputs->CpuModel == cmHSW) && (Inputs->CpuStepping == csHswA0)) {
+      ReutSubSeqCtl0HswA0.Data                                     = 0;
+      ReutSubSeqCtl0HswA0.Bits.Number_of_Cachelines                = NumCLCR;
+      ReutSubSeqCtl0HswA0.Bits.Number_of_Cachelines_Scale          = NumCLCR >> 7;
+      ReutSubSeqCtl0HswA0.Bits.Reset_Current_Base_Address_To_Start = 1;
+      ReutSubSeqCtl0HswA0.Bits.Subsequence_Wait                    = SubSeqWait;
+      ReutSubSeqCtl0Data = ReutSubSeqCtl0HswA0.Data;
+    } else {
+      ReutSubSeqCtl0.Data                                     = 0;
+      ReutSubSeqCtl0.Bits.Number_of_Cachelines                = NumCLCR;
+      ReutSubSeqCtl0.Bits.Number_of_Cachelines_Scale          = NumCLCR >> 7;
+      ReutSubSeqCtl0.Bits.Reset_Current_Base_Address_To_Start = 1;
+      ReutSubSeqCtl0.Bits.Subsequence_Wait                    = SubSeqWait;
+      ReutSubSeqCtl0Data = ReutSubSeqCtl0.Data;
+    }
+
+    ReutSubSeqCtl1.Data                            = ReutSubSeqCtl0Data;
+    ReutSubSeqCtl1.Bits.Number_of_Cachelines       = NumCL2CR;
+    ReutSubSeqCtl1.Bits.Number_of_Cachelines_Scale = NumCL2CR >> 7;
+
+    switch (CmdPat) {
+      case PatWrRdTA:
+        SubSeq.Ctl[0].Data                        = ReutSubSeqCtl0Data;
+        SetSubsequenceType (MrcData, &SubSeq.Ctl[0].Data, BWr);            // Write CMD
+        for (Index = 1; Index <= 6; Index++) {
+          SubSeq.Ctl[Index].Data                  = ReutSubSeqCtl1.Data;
+          SetSubsequenceType (MrcData, &SubSeq.Ctl[Index].Data, BRdWr);    // Read-Write CMD
+        }
+        SubSeq.Ctl[7].Data                        = ReutSubSeqCtl0Data;
+        SetSubsequenceType (MrcData, &SubSeq.Ctl[7].Data, BRd);            // Read CMD
+        SubSeq.ValidMask                          = 0xFF;
+        break;
+
+      case PatRdWrTA:
+        SubSeq.Ctl[0].Data                        = ReutSubSeqCtl1.Data;
+        SetSubsequenceType (MrcData, &SubSeq.Ctl[0].Data, BWrRd);          // Write-Read CMD
+        SubSeq.ValidMask                          = 0x01;
+        break;
+
+      case PatODTTA:
+        SubSeq.Ctl[0].Data                        = ReutSubSeqCtl0Data;
+        SetSubsequenceType (MrcData, &SubSeq.Ctl[0].Data, BWr);            // Write CMD
+
+        SubSeq.Ctl[1].Data                        = ReutSubSeqCtl1.Data;
+        SetSubsequenceType (MrcData, &SubSeq.Ctl[1].Data, BRdWr);          // Read-Write CMD
+
+        SubSeq.Ctl[2].Data                        = ReutSubSeqCtl0Data;
+        SetSubsequenceType (MrcData, &SubSeq.Ctl[2].Data, BRd);            // Read CMD
+
+        SubSeq.Ctl[3].Data                        = ReutSubSeqCtl1.Data;
+        SetSubsequenceType (MrcData, &SubSeq.Ctl[3].Data, BWrRd);          // Write-Read CMD
+
+        SubSeq.ValidMask                          = 0x0F;
+        break;
+
+      default:
+        SubSeq.Ctl[0].Data                        = ReutSubSeqCtl0Data;
+        SetSubsequenceType (MrcData, &SubSeq.Ctl[0].Data, BWr);            // Write CMD
+
+        SubSeq.Ctl[1].Data                        = ReutSubSeqCtl0Data;
+        SetSubsequenceType (MrcData, &SubSeq.Ctl[1].Data, BRd);            // Read CMD
+
+        SubSeq.ValidMask                          = 0x03;
+        break;
+    }
+    Offset = MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_REG +
+      ((MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_REG - MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_REG) * Channel);
+    for (Index = 0; Index < 8; Index++) {
+      if (SubSeq.ValidMask & (MRC_BIT0 << Index)) {
+        MrcWriteCR (MrcData, Offset, SubSeq.Ctl[Index].Data);
+        Offset += MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_REG - MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_REG;
+      } else {
+        break;
+      }
+    }
+
+    //###########################################################
+    //
+    // Program Sequence Address
+    //
+    //###########################################################
+    MrcProgramSequenceAddress (
+      MrcData,
+      Channel,
+      REUTAddress->Start,
+      REUTAddress->Stop,
+      REUTAddress->Order,
+      REUTAddress->IncRate,
+      REUTAddress->IncVal,
+      WrapCarryEn,
+      WrapTriggerEn,
+      AddrInvertEn,
+      0,
+      FALSE
+      );
+
+    //###########################################################
+    //
+    // Program Write Data Buffer Related Entries
+    //
+    //###########################################################
+    ReutChPatWdbCl.Data                     = 0;
+    ReutChPatWdbCl.Bits.WDB_End_Pointer     = WDBPattern->Stop;
+    ReutChPatWdbCl.Bits.WDB_Start_Pointer   = WDBPattern->Start;
+    ReutChPatWdbCl.Bits.WDB_Increment_Rate  = WDBPattern->IncRate;
+    ReutChPatWdbCl.Bits.WDB_Increment_Scale = WDBPattern->IncRate >> MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_Increment_Rate_WID;
+    Offset = MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_CTRL_REG +
+      ((MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_CTRL_REG - MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_CTRL_REG) * Channel);
+    MrcWriteCR (MrcData, Offset, ReutChPatWdbCl.Data);
+
+    ReutChPatWdbClMuxCfg.Data = 0;
+
+    //
+    // Enable LMN in either LMN mode or CADB -to create lots of supply noise
+    //
+    Mux0  = ((WDBPattern->DQPat == LMNVa) || (WDBPattern->DQPat == CADB)) ? LMNMode : LFSRMode;
+
+    ReutChPatWdbClMuxCfg.Bits.ECC_Data_Source_Sel = 1;
+    ReutChPatWdbClMuxCfg.Bits.Mux2_Control        = LFSRMode;
+    ReutChPatWdbClMuxCfg.Bits.Mux1_Control        = LFSRMode;
+    ReutChPatWdbClMuxCfg.Bits.Mux0_Control        = Mux0;      // ECC, Select LFSR
+    //
+    // Program LFSR Save/Restore.  Too complex unless everything is power of 2
+    //
+    if ((CmdPat == PatODTTA) || (CmdPat == PatWrRdTA)) {
+      ReutChPatWdbClMuxCfg.Bits.Reload_LFSR_Seed_Rate = MrcLog2 (NumCL - 1) + 1;
+      ReutChPatWdbClMuxCfg.Bits.Save_LFSR_Seed_Rate   = 1;
+    }
+
+    Offset = MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_REG +
+      ((MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_REG - MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_REG) * Channel);
+    MrcWriteCR (MrcData, Offset, ReutChPatWdbClMuxCfg.Data);
+
+    //
+    // Currently, not planning to use the Inversion Mask
+    //
+    Offset = MCHBAR_CH0_CR_REUT_CH_PAT_WDB_INV_REG + ((MCHBAR_CH1_CR_REUT_CH_PAT_WDB_INV_REG - MCHBAR_CH0_CR_REUT_CH_PAT_WDB_INV_REG) * Channel);
+    MrcWriteCR (MrcData, Offset, 0);
+
+    //###########################################################
+    //
+    // Program Error Checking
+    //
+    //###########################################################
+
+    //
+    // Enable selective_error_enable_chunk and selective_error_enable_cacheline, mask later
+    // the bits we don't want to check.
+    //
+    Offset = MCHBAR_CH0_CR_REUT_CH_ERR_CTL_REG +
+      ((MCHBAR_CH1_CR_REUT_CH_ERR_CTL_REG - MCHBAR_CH0_CR_REUT_CH_ERR_CTL_REG) * Channel);
+    ReutChErrCtrl.Data                                  = 0;
+    ReutChErrCtrl.Bits.Stop_on_Nth_Error                = 1;
+    ReutChErrCtrl.Bits.Stop_On_Error_Control            = SOE;
+    ReutChErrCtrl.Bits.Selective_Error_Enable_Chunk     = MCHBAR_CH0_CR_REUT_CH_ERR_CTL_Selective_Error_Enable_Chunk_MAX;
+    ReutChErrCtrl.Bits.Selective_Error_Enable_Cacheline = MCHBAR_CH0_CR_REUT_CH_ERR_CTL_Selective_Error_Enable_Cacheline_MAX;
+    MrcWriteCR (MrcData, Offset, ReutChErrCtrl.Data);
+
+    Offset = MCHBAR_CH0_CR_REUT_CH_ERR_DATA_MASK_REG +
+      ((MCHBAR_CH1_CR_REUT_CH_ERR_DATA_MASK_REG - MCHBAR_CH0_CR_REUT_CH_ERR_DATA_MASK_REG) * Channel);
+    MrcWriteCR64 (MrcData, Offset, 0);
+
+    Offset = MCHBAR_CH0_CR_REUT_CH_ERR_ECC_MASK_REG +
+      ((MCHBAR_CH1_CR_REUT_CH_ERR_ECC_MASK_REG - MCHBAR_CH0_CR_REUT_CH_ERR_ECC_MASK_REG) * Channel);
+    MrcWriteCR8 (MrcData, Offset, 0);
+
+    //###########################################################
+    //
+    // Program Dummy Read
+    //
+    //###########################################################
+    if (Outputs->EnDumRd) {
+      //
+      // REUT traffic only uses BA[1:0] - Mask BANK that will not be used
+      //
+      Offset = MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_MASK_MCMAIN_0_REG +
+        (
+          (MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_MASK_MCMAIN_1_REG - MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_MASK_MCMAIN_0_REG) *
+          Channel
+        );
+      MrcWriteCR8 (MrcData, Offset, 0xFC);
+
+      //
+      // Rotated from 40nS to 200nS
+      //
+      if (Outputs->Qclkps > 0) {
+        LMNFreq[0] = (40000 / Outputs->Qclkps);
+        LMNFreq[1] = (200000 / Outputs->Qclkps);
+      } else {
+        LMNFreq[0] = LMNFreq[1] = 0xFF;
+      }
+
+      ReutChSeqDummyReadCtl.Data                        = 0;
+      ReutChSeqDummyReadCtl.Bits.L_counter              = LMNFreq[0];
+      ReutChSeqDummyReadCtl.Bits.M_counter              = LMNFreq[0];
+      ReutChSeqDummyReadCtl.Bits.N_Counter              = LMNFreq[1];
+      ReutChSeqDummyReadCtl.Bits.Enable_Sweep_Frequency = 1;
+      //
+      // Chirp Freq from 5 to 25 MHz
+      //
+      Offset = MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_0_REG + (
+          (MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_1_REG - MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_0_REG) * Channel
+        );
+      MrcWriteCR (MrcData, Offset, ReutChSeqDummyReadCtl.Data);
+    }
+  }
+  //
+  // Always do a ZQ Short before the beginning of a test
+  //
+  MrcIssueZQ (MrcData, ChbitMask, MRC_ZQ_SHORT);
+
+  return;
+}
+
+/**
+  This function sets up a test with CADB for the given channel mask.
+
+  @param[in,out] MrcData   - Pointer to MRC global data.
+  @param[in]     ChbitMask - Bit masks of channels to enable for the test.
+  @param[in]     LC        - Exponential umber of loops to run the test.
+  @param[in]     SOE       - Error handling switch for test.
+  @param[in]     EnCADB    - Switch to enable CADB
+  @param[in]     EnCKE     - Switch to enable CKE.
+
+  @retval Nothing
+**/
+void
+SetupIOTestCADB (
+  IN OUT MrcParameters *const MrcData,
+  IN     const U8             ChbitMask,
+  IN     const U8             LC,
+  IN     const U8             SOE,
+  IN     const U8             EnCADB,
+  IN     const U8             EnCKE
+  )
+{
+  const MRC_REUTAddress REUTAddress = {
+    // Rank, Bank, Row, Col
+    {    0,  0,    0,    0 },  // Start
+    {    0,  7, 2047, 1023 },  // Stop
+    {    0,  0,    0,    0 },  // Order
+    {   32,  3,    3,    0 },  // IncRate
+    {    1,  1,   73,   53 }   // IncValue
+  };
+  MRC_WDBPattern  WDBPattern;
+  MrcOutput       *Outputs;
+  U16             NumCL;
+
+  Outputs            = &MrcData->SysOut.Outputs;
+  WDBPattern.IncRate = 4;
+  WDBPattern.Start   = 0;
+  WDBPattern.Stop    = 9;
+  WDBPattern.DQPat   = CADB;
+
+  NumCL = 128;
+
+  SetupIOTest (MrcData, ChbitMask, PatWrRd, NumCL, LC, &REUTAddress, SOE, &WDBPattern, EnCADB, EnCKE, 0);
+
+  Outputs->DQPatLC = LC - 2 - 3 + 1;
+  if (Outputs->DQPatLC < 1) {
+    Outputs->DQPatLC = 1;
+  }
+
+  Outputs->DQPat = CADB;
+  return;
+}
+
+/**
+  This function sets up a basic victim-aggressor test for the given channel mask.
+
+  @param[in,out] MrcData   - Pointer to MRC global data.
+  @param[in]     ChbitMask - Bit masks of channels to enable for the test.
+  @param[in]     LC        - Exponential umber of loops to run the test.
+  @param[in]     SOE       - Error handling switch for test.
+  @param[in]     EnCADB    - Switch to enable CADB
+  @param[in]     EnCKE     - Switch to enable CKE.
+  @param[in]     Spread    - Stopping point of the pattern.
+
+  @retval Nothing
+**/
+void
+SetupIOTestBasicVA (
+  IN OUT MrcParameters *const MrcData,
+  IN     const U8             ChbitMask,
+  IN     const U8             LC,
+  IN     const U8             SOE,
+  IN     const U8             EnCADB,
+  IN     const U8             EnCKE,
+  IN     const U32            Spread
+  )
+{
+  const MRC_REUTAddress REUTAddress = {
+    // Rank, Bank, Row, Col
+    {    0,  0,    0,    0 },  // Start
+    {    0,  0,    0, 1023 },  // Stop
+    {    0,  0,    0,    0 },  // Order
+    {   32,  0,    0,    0 },  // IncRate
+    {    1,  0,    0,    1 }   // IncValue
+  };
+  
+  MRC_WDBPattern        WDBPattern;
+  MrcOutput             *Outputs;
+  U16                   NumCL;
+
+  Outputs            = &MrcData->SysOut.Outputs;
+  WDBPattern.IncRate = 4;
+  WDBPattern.Start   = 0;
+  WDBPattern.Stop    = Spread - 1;
+  WDBPattern.DQPat   = BasicVA;
+
+  NumCL = 128;
+
+  SetupIOTest (MrcData, ChbitMask, PatWrRd, NumCL, LC, &REUTAddress, SOE, &WDBPattern, EnCADB, EnCKE, 0);
+
+  Outputs->DQPatLC = LC - 8 + 1;
+  if (Outputs->DQPatLC < 1) {
+    Outputs->DQPatLC = 1;
+  }
+
+  Outputs->DQPat = BasicVA;
+  return;
+}
+
+/**
+  This function sets up a DQ test for the given channel mask.
+
+  @param[in,out] MrcData   - Pointer to MRC global data.
+  @param[in]     ChbitMask - Bit masks of channels to enable for the test.
+  @param[in]     LC        - Exponential umber of loops to run the test.
+  @param[in]     SOE       - Error handling switch for test.
+  @param[in]     EnCADB    - Switch to enable CADB
+  @param[in]     EnCKE     - Switch to enable CKE.
+
+  @retval Nothing
+**/
+void
+SetupIOTestDQ (
+  IN OUT MrcParameters *const MrcData,
+  IN     const U8             ChbitMask,
+  IN     const U8             LC,
+  IN     const U8             SOE,
+  IN     const U8             EnCADB,
+  IN     const U8             EnCKE
+  )
+{
+  const MRC_REUTAddress REUTAddress = {{0, 0, 0, 0},        // Start
+  {0, 1, 512, 1023},   // Stop
+  {0, 0, 0, 0},        // Order
+  {2047, 255, 255, 0}, // IncRate
+  {1, 1, 512, 1}};     // IncValue
+  MRC_WDBPattern        WDBPattern;
+  MrcOutput             *Outputs;
+  U16                   NumCL;
+
+  Outputs            = &MrcData->SysOut.Outputs;
+  WDBPattern.IncRate = 32;
+  WDBPattern.Start   = 0;
+  WDBPattern.Stop    = 63;
+  WDBPattern.DQPat   = SegmentWDB;
+
+  NumCL = 256;
+
+  SetupIOTest (MrcData, ChbitMask, PatWrRd, NumCL, LC, &REUTAddress, SOE, &WDBPattern, EnCADB, EnCKE, 0);
+
+  Outputs->DQPatLC = LC - 8 - 3 + 1;
+  if (Outputs->DQPatLC < 1) {
+    Outputs->DQPatLC = 1;
+  }
+
+  Outputs->DQPat = SegmentWDB;
+  return;
+}
+
+/**
+  This function sets up a test with CADB for the given channel mask.
+
+  @param[in,out] MrcData   - Pointer to MRC global data.
+  @param[in]     ChbitMask - Bit masks of channels to enable for the test.
+  @param[in]     LC        - Exponential umber of loops to run the test.
+  @param[in]     SOE       - Error handling switch for test.
+  @param[in]     EnCADB    - Switch to enable CADB
+  @param[in]     EnCKE     - Switch to enable CKE.
+
+  @retval Nothing
+**/
+void
+SetupIOTestC2C (
+  IN OUT MrcParameters *const MrcData,
+  IN     const U8             ChbitMask,
+  IN     const U8             LC,
+  IN     const U8             SOE,
+  IN     const U8             EnCADB,
+  IN     const U8             EnCKE
+  )
+{
+  const MRC_REUTAddress REUTAddress = {{0, 0, 0, 0},    // Start
+  {0, 0, 0, 1023}, // Stop
+  {0, 0, 0, 0},    // Order
+  {2047, 0, 0, 0}, // IncRate
+  {1, 0, 0, 1}};   // IncValue
+  MRC_WDBPattern        WDBPattern;
+  MrcOutput             *Outputs;
+
+  Outputs            = &MrcData->SysOut.Outputs;
+  WDBPattern.IncRate = 32;
+  WDBPattern.Start   = 0;
+  WDBPattern.Stop    = 63;
+  WDBPattern.DQPat   = SegmentWDB;
+
+  SetupIOTest (MrcData, ChbitMask, PatWrRd, 32, LC, &REUTAddress, SOE, &WDBPattern, EnCADB, EnCKE, 0);
+
+  Outputs->DQPatLC = LC - 5 + 1;
+  if (Outputs->DQPatLC < 1) {
+    Outputs->DQPatLC = 1;
+  }
+
+  Outputs->DQPat = SegmentWDB;
+  return;
+}
+
+/**
+  This function sets up a MPR test for the given channel mask.
+
+  @param[in,out] MrcData   - Pointer to MRC global data.
+  @param[in]     ChbitMask - Bit masks of channels to enable for the test.
+  @param[in]     LC        - Exponential umber of loops to run the test.
+  @param[in]     SOE       - Error handling switch for test.
+  @param[in]     EnCADB    - Switch to enable CADB
+  @param[in]     EnCKE     - Switch to enable CKE.
+
+  @retval Nothing
+**/
+void
+SetupIOTestMPR (
+  IN OUT MrcParameters *const MrcData,
+  IN     const U8             ChbitMask,
+  IN     const U8             LC,
+  IN     const U8             SOE,
+  IN     const U8             EnCADB,
+  IN     const U8             EnCKE
+  )
+{
+  const MRC_REUTAddress REUTAddress_ddr = {
+    { 0,  0, 0, 0    }, // Start
+    { 0,  0, 0, 1023 }, // Stop
+    { 0,  0, 0, 0    }, // Order
+    { 32, 0, 0, 0    }, // IncRate
+    { 1,  0, 0, 1    }  // IncValue
+  };
+  const MRC_REUTAddress REUTAddress_lpddr = {
+    { 0, 4, 0, 0 },     // Start
+    { 0, 4, 0, 0 },     // Stop
+    { 0, 0, 0, 0 },     // Order
+    { 0, 0, 0, 0 },     // IncRate
+    { 0, 0, 0, 0 }      // IncValue
+  };
+  const MRC_REUTAddress *ReutAddress;
+  MRC_WDBPattern        WDBPattern;
+  MrcOutput             *Outputs;
+  U16                   NumCL;
+
+  Outputs            = &MrcData->SysOut.Outputs;
+  WDBPattern.IncRate = 4;
+  WDBPattern.Start   = 0;
+  WDBPattern.Stop    = 9;
+  WDBPattern.DQPat   = BasicVA;
+
+  NumCL = 128;
+
+  if (Outputs->DdrType == MRC_DDR_TYPE_LPDDR3) {
+    ReutAddress = &REUTAddress_lpddr;
+  } else {
+    ReutAddress = &REUTAddress_ddr;
+  }
+
+  SetupIOTest (MrcData, ChbitMask, PatRd, NumCL, LC, ReutAddress, SOE, &WDBPattern, EnCADB, EnCKE, 0);
+
+  Outputs->DQPatLC = 1;
+  Outputs->DQPat   = BasicVA;
+  return;
+}
+
+/**
+  Runs one or more REUT tests (based on TestType)
+
+  @param[in] MrcData     - Include all MRC global data.
+  @param[in] ChbitMask   - Channel Bit mask for which test should be setup for.
+  @param[in] DQPat       - [0: BasicVA
+                            1: SegmentWDB
+                            2: CADB
+                            3: TurnAround
+                            4: LMNVa
+                            5: TurnAroundWR
+                            6: TurnAroundODT
+                            7: RdRdTA]
+  @param[in] SeqLCs      - An array of one or more loopcounts.
+  @param[in] ClearErrors - Decision to clear or not errors.
+  @param[in] Mode        - Allows for different types of modes for margining
+                           {Bit0: PhLock (keep all bytes within in ch in phase),
+                            Bit1: Ch2Ch Data out of phase (LFSR seed)
+                            Bits 15:2: Reserved}
+
+  @retval Returns ch errors
+**/
+U8
+RunIOTest (
+  IN MrcParameters *const MrcData,
+  IN const U8             ChbitMask,
+  IN const U8             DQPat,
+  IN const U8 *const      SeqLCs,
+  IN const U8             ClearErrors,
+  IN const U16            Mode
+  )
+{
+  const MrcDebug    *Debug;
+  MrcInput          *Inputs;
+  MrcOutput         *Outputs;
+  MrcControllerOut  *ControllerOut;
+  U8                ch;
+  U8                Reload;
+  U8                NumTests;
+  U8                t;
+  U8                IncRate;
+  U8                TestSOE;
+  U8                TestDoneStatus;
+  U8                ErrorStatus;
+  U32               CRValue;
+  U32               TestRand;
+  U32               Offset;
+  U32               LoopCountLinear;
+  U8                tRDRD_dr_Min[MAX_CHANNEL];
+  U8                TurnAroundOffset;
+  // When we segment the WDB, we run a normal 2 LFSR VA pattern on the first 10 entries
+  // The last 54 entries are used for a more complex 3 LFSR pattern
+  // In this mode:
+  // SeqLC is usually [0: host.DQPatLC, 1: host.DQPatLC, 2: host.DQPatLC+4, 3: host.DQPatLC+2]
+  //
+  // Anotherwords:
+  // The first 10 entries of the LFSR are run for twice, each for 2^DQPatLC
+  //   and the WDB is incremented every 25 cachelines
+  //
+  // 25 was chosen since 10 Entry * 25 cachelines = 250.
+  // This is pretty close to 256, a power of 2, which should be roughly uniform coverage across all entries
+  //
+  // The second 54 entries of the LFSR are run twice
+  //            Once with 2^(DQPatLC+4) and the WDB is incremented every 19 cachelines
+  //            Once with 2^(DQPatLC+2) and the WDB is incremented every 10 cachelines
+  //            Again, 19*54 = 1026 and 10*54 = 540 and both of these numbers are close
+  //             to power of 2 and will provide roughly uniform coverage
+  //
+  // Each entry in the first 10 entries is hit 2 ^ (DQPatLC + NumCachelines + 1) / 10
+  //           or 2 ^ (DQPatLC + NumCachelines -2.32)
+  //
+  // Each entry in the second 54 entries is hit 2 ^ (DQPatLC + NumCachelines + 4.32) / 54
+  //           or ~2 ^ (DQPatLC + NumCachelines -1.43)
+  //           or ~2x more than the first 10 entries
+
+  U8 WDBIncRates[8];
+  U8 WDBStart[8];
+  U8 WDBStop[8];
+
+  MCDFXS_CR_REUT_GLOBAL_CTL_MCMAIN_STRUCT                 ReutGlobalCtl;
+  MCDFXS_CR_REUT_GLOBAL_ERR_MCMAIN_STRUCT                 ReutGlobalErr;
+  MCHBAR_CH0_CR_REUT_CH_ERR_CTL_STRUCT                    ReutChErrCtl;
+  MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_CTRL_STRUCT            ReutChPatWdbCl;
+  MCHBAR_CH0_CR_TC_BANK_RANK_A_STRUCT                     TcBankRankA[MAX_CHANNEL];
+
+  TestSOE       = 0;
+  Inputs        = &MrcData->SysIn.Inputs;
+  Outputs       = &MrcData->SysOut.Outputs;
+  ControllerOut = &Outputs->Controller[0];
+  Debug         = &MrcData->SysIn.Inputs.Debug;
+  MrcOemMemorySet (WDBIncRates, 1, sizeof (WDBIncRates));
+  MrcOemMemorySet (WDBStart, 0, sizeof (WDBStart));
+  MrcOemMemorySet (WDBStop, 9, sizeof (WDBStop));
+  MrcOemMemorySetDword ((U32 *) TcBankRankA, 0, sizeof (TcBankRankA) / sizeof (TcBankRankA[0]));
+  ReutGlobalErr.Data  = 0;
+  ErrorStatus         = 0;
+
+  TestRand     = 0xBAD00451;
+  NumTests     = 1;
+  if (DQPat == SegmentWDB) {
+    NumTests = 4;
+    WDBIncRates[3] = 10;
+    WDBIncRates[2] = 19;
+    WDBIncRates[1] = 25;
+    WDBIncRates[0] = 25;
+
+    WDBStart[3]    = 10;
+    WDBStart[2]    = 10;
+    WDBStop[3]     = 63;
+    WDBStop[2]     = 63;
+  } else if (DQPat == CADB) {
+    NumTests = 7;
+  } else if (DQPat == TurnAroundWR) {
+    NumTests = 8;
+  } else if (DQPat == TurnAroundODT) {
+    NumTests = 4;
+  } else if (DQPat == RdRdTA) {
+    NumTests = 2;
+    for (ch = 0; ch < MAX_CHANNEL; ch++) {
+      if (!((MRC_BIT0 << ch) & ChbitMask)) {
+        continue;
+      }
+
+      TcBankRankA[ch].Data = ControllerOut->Channel[ch].MchbarBANKRANKA;
+    }
+  } else if (DQPat == RdRdTA_All) {
+    NumTests = 8;
+    for (ch = 0; ch < MAX_CHANNEL; ch++) {
+      if (((1 << ch) & ChbitMask) == 0) {
+        continue;
+      }
+
+      TcBankRankA[ch].Data = ControllerOut->Channel[ch].MchbarBANKRANKA;
+      tRDRD_dr_Min[ch] = (U8) TcBankRankA[ch].Bits.tRDRD_dr; // save the min value allowed 
+    }
+  }
+
+  for (t = 0; t < NumTests; t++) {
+    //MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "RunIOTest: t = %d\n",t);
+    Reload = MrcLog2 (WDBIncRates[t] - 1);
+    if (WDBIncRates[t] > 31) {
+      WDBIncRates[t] = Reload;
+    } else {
+      WDBIncRates[t] += 32;
+    }
+
+    for (ch = 0; ch < MAX_CHANNEL; ch++) {
+      if (!((MRC_BIT0 << ch) & ChbitMask)) {
+        continue;
+      }
+      //
+      // Check for SOE == NTHSOE, ALSOE
+      // @todo: I still feel we need to exit if we get  errors on any test
+      //
+      TestSOE = 0;
+      Offset = MCHBAR_CH0_CR_REUT_CH_ERR_CTL_REG +
+        ((MCHBAR_CH1_CR_REUT_CH_ERR_CTL_REG - MCHBAR_CH0_CR_REUT_CH_ERR_CTL_REG) * ch);
+      ReutChErrCtl.Data = MrcReadCR (MrcData, Offset);
+      CRValue = ReutChErrCtl.Bits.Stop_On_Error_Control;
+      if ((CRValue == NTHSOE) || (CRValue == ALSOE)) {
+        TestSOE = 1; // SOE bits are set
+      }
+
+      if (DQPat == SegmentWDB) {
+        Offset = MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_CTRL_REG +
+          ((MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_CTRL_REG - MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_CTRL_REG) * ch);
+        ReutChPatWdbCl.Data                     = 0;
+        ReutChPatWdbCl.Bits.WDB_Start_Pointer   = WDBStart[t];
+        ReutChPatWdbCl.Bits.WDB_End_Pointer     = WDBStop[t];
+        ReutChPatWdbCl.Bits.WDB_Increment_Rate  = WDBIncRates[t];
+        ReutChPatWdbCl.Bits.WDB_Increment_Scale = WDBIncRates[t] >> MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_Increment_Rate_WID;
+        MrcWriteCR (MrcData, Offset, ReutChPatWdbCl.Data);
+
+        //
+        // Skip programming LFSR Save/Restore.  Too complex unless power of 2
+        //
+        if (
+            (Inputs->CpuModel == cmHSW && Inputs->CpuStepping < csHswC0) ||
+            (Inputs->CpuModel == cmCRW && Inputs->CpuStepping < csCrwC0) ||
+            (Inputs->CpuModel == cmHSW_ULT && Inputs->CpuStepping < csHswUltC0)
+           ) {
+          //
+          // Program desired loopcount
+          //
+          Offset = MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_REG + 2 +
+            ((MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_REG - MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_REG) * ch);
+          MrcWriteCR8 (MrcData, Offset, (SeqLCs[t] + 1));
+        } else {
+          LoopCountLinear = 1 << SeqLCs[t];
+          Offset = MCDFXS_CR_REUT_CH_SEQ_LOOPCOUNT_LIMIT_MCMAIN_0_REG +
+            (
+              (MCDFXS_CR_REUT_CH_SEQ_LOOPCOUNT_LIMIT_MCMAIN_1_REG - MCDFXS_CR_REUT_CH_SEQ_LOOPCOUNT_LIMIT_MCMAIN_0_REG) *
+              ch
+            );
+          MrcWriteCR (MrcData, Offset, LoopCountLinear);
+        }
+
+      } else if (DQPat == CADB) {
+        SetupCADB (MrcData, ch, NumTests, t, 0);   // LMNEn=0
+      } else if ( (DQPat == TurnAroundWR) || (DQPat == TurnAroundODT) ) {
+        //
+        // Program which subseq to run
+        //
+        Offset = MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_REG + 3 +
+          ((MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_REG - MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_REG) * ch);
+        MrcWriteCR8 (MrcData, Offset, (t << 4) + t);
+
+        //
+        // Program RankInc Rate
+        //
+        IncRate =
+          (
+            ((DQPat == TurnAroundWR) && ((t == 0) || (t == 7))) ||
+            ((DQPat == TurnAroundODT) && ((t == 0) || (t == 2)))
+          ) ? 0 : 1;
+
+        Offset = MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_REG +
+        ((
+          MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_REG - MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_REG
+         ) * ch
+        );
+        MrcWriteCR8 (MrcData, Offset + 7, 128 + IncRate); // 0x80+IncRate
+        CRValue = MrcReadCR (MrcData, Offset);
+        //
+        // Program bit 19, 16:12 to IncRate (assume linear mode)
+        //
+        CRValue = MrcBitSwap (CRValue, (128 + IncRate), 12, 8);
+        MrcWriteCR (MrcData, Offset, CRValue);
+      } else if (DQPat == RdRdTA) {
+        //
+        // Program tRDRD parameter
+        //
+        Offset = MCHBAR_CH0_CR_TC_BANK_RANK_A_REG +
+          ((MCHBAR_CH1_CR_TC_BANK_RANK_A_REG - MCHBAR_CH0_CR_TC_BANK_RANK_A_REG) * ch);
+        TcBankRankA[ch].Bits.tRDRD = (t == 0) ? 4 : 5;
+        MrcWriteCR (MrcData, Offset, TcBankRankA[ch].Data);
+      } else if (DQPat == RdRdTA_All) {
+        //
+        // Program tRDRD for SR and DR
+        //  Run 8 tests, Covering tRDRD_sr = 4,5,6,7 and tRDRD_dr = Min,+1,+2,+3 
+        //
+        TurnAroundOffset = (t % 4);
+        Offset = MCHBAR_CH0_CR_TC_BANK_RANK_A_REG +
+          ((MCHBAR_CH1_CR_TC_BANK_RANK_A_REG - MCHBAR_CH0_CR_TC_BANK_RANK_A_REG) * ch);
+        TcBankRankA[ch].Bits.tRDRD = 4 + TurnAroundOffset;
+        TcBankRankA[ch].Bits.tRDRD_dr = tRDRD_dr_Min[ch] + TurnAroundOffset;
+
+        MrcWriteCR (MrcData, Offset, TcBankRankA[ch].Data);
+        //
+        // Program RankInc Rate
+        //
+        IncRate = (t > 3)? 0 : 31; // this field + 1 
+
+        Offset = MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_REG +
+          (
+            (
+              MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_REG - MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_REG
+            ) * ch
+          );
+        MrcWriteCR8 (MrcData, Offset + 7, IncRate | MRC_BIT7); // Linear Rank Address Update Rate 
+      }
+    }
+
+    //###########################################################
+    //
+    // Start Test and Poll on completion
+    //
+    //###########################################################
+    //
+    // IO Reset neded before starting test.
+    //
+    IoReset (MrcData);
+
+    ReutGlobalCtl.Data                    = 0;
+    ReutGlobalCtl.Bits.Global_Start_Test  = 1;
+    if (ClearErrors && (t == 0)) {
+      ReutGlobalCtl.Bits.Global_Clear_Errors = 1;
+    }
+
+    MrcWriteCR (MrcData, MCDFXS_CR_REUT_GLOBAL_CTL_MCMAIN_REG, ReutGlobalCtl.Data);
+
+    //
+    // Wait until Channel test done status matches ChbitMask
+    //
+    do {
+      ReutGlobalErr.Data = MrcReadCR (MrcData, MCDFXS_CR_REUT_GLOBAL_ERR_MCMAIN_REG);
+      TestDoneStatus = (U8) ((ReutGlobalErr.Bits.Channel_Test_Done_Status_1 << 1) | ReutGlobalErr.Bits.Channel_Test_Done_Status_0);
+    } while ((TestDoneStatus & ChbitMask) != ChbitMask);
+
+    //
+    // Exit if SOE and Channel_Test_Done_Status bits matches ChbitMask
+    //
+    ErrorStatus = (U8) ((ReutGlobalErr.Bits.Channel_Error_Status_1 << 1) | ReutGlobalErr.Bits.Channel_Error_Status_0);
+    if ((ErrorStatus & ChbitMask) && TestSOE) {
+      //MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "ERROR IN RunIOTest: REUT_GLOBAL_CTRL = %Xh, REUT_GLOBAL_ERR %Xh\n", ReutGlobalErr.Data, ErrorStatus);
+      return (ReutGlobalErr.Data & ChbitMask);
+    }
+  }
+
+  if ((DQPat == RdRdTA) || (DQPat == RdRdTA_All)) {
+    //
+    // Restore original tRDRD value
+    //
+    for (ch = 0; ch < MAX_CHANNEL; ch++) {
+      if (!((MRC_BIT0 << ch) & ChbitMask)) {
+        continue;
+      }
+
+      Offset = MCHBAR_CH0_CR_TC_BANK_RANK_A_REG +
+        ((MCHBAR_CH1_CR_TC_BANK_RANK_A_REG - MCHBAR_CH0_CR_TC_BANK_RANK_A_REG) * ch);
+      MrcWriteCR (MrcData, Offset, ControllerOut->Channel[ch].MchbarBANKRANKA);
+    }
+  }
+
+  return (ReutGlobalErr.Data & ChbitMask);
+}
+
+/**
+  Programs REUT to run on the selected physical ranks.
+
+  @param[in] MrcData           - Pointer to MRC global data.
+  @param[in] ch                - Channel to enable.
+  @param[in] RankBitMask       - Bit mask of ranks to enable.
+  @param[in] RankFeatureEnable - RankFeatureEnable is a bit mask that can enable CKE, Refresh or ZQ
+                                 RankFeatureEnable[0] enables Refresh on all non-selected ranks
+                                 RankFeatureEnable[1] enables Refresh on all ranks
+                                 RankFeatureEnable[2] enables ZQ on all non-selected ranks
+                                 RankFeatureEnable[3] enables ZQ on all ranks
+                                 RankFeatureEnable[4] enables CKE on all non-selected ranks
+                                 RankFeatureEnable[5] enables CKE on all ranks
+
+  @retval Bit mask of channel enabled if rank in the channel exists.
+**/
+U8
+SelectReutRanks (
+  IN MrcParameters *const MrcData,
+  IN const U8             ch,
+  IN U8                   RankBitMask,
+  IN const U8             RankFeatureEnable
+  )
+{
+  U32 Offset;
+  U8  En;
+  U8  rank;
+  U8  RankCount;
+  MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_STRUCT       ReutChSeqCfg;
+  MCHBAR_CH0_CR_REUT_CH_MISC_REFRESH_CTRL_STRUCT  ReutChMiscRefreshCtrl;
+  MCHBAR_CH0_CR_REUT_CH_MISC_ZQ_CTRL_STRUCT       ReutChMiscZqCtrl;
+  MCHBAR_CH0_CR_REUT_CH_MISC_CKE_CTRL_STRUCT      ReutChMiscCkeCtrl;
+  MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_0_STRUCT  ReutChSeqRankL2PMapping;
+
+  //
+  // Make sure valid rank bit mask for this channel
+  //
+  RankBitMask &= MrcData->SysOut.Outputs.Controller[0].Channel[ch].ValidRankBitMask;
+
+  //
+  // Check if nothing is selected
+  //
+  if ((RankBitMask & 0xF) == 0) {
+    Offset = MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_0_REG +
+      (
+        (
+          MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_1_REG -
+          MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_0_REG
+        ) * ch
+      );
+    MrcWriteCR (MrcData, Offset, 0);
+
+    //
+    // Disable Channel by clearing global start bit in change config
+    //
+    Offset = MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_REG +
+      ((MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_REG - MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_REG) * ch);
+    ReutChSeqCfg.Data                 = MrcReadCR (MrcData, Offset);
+    ReutChSeqCfg.Bits.Global_Control  = 0;
+    MrcWriteCR (MrcData, Offset, (U32) ReutChSeqCfg.Data);
+
+    return 0;
+
+  } else {
+    //
+    // Normal case
+    // Setup REUT Test to iteration through appropriate ranks during test
+    //
+    ReutChSeqRankL2PMapping.Data  = 0;
+    RankCount                     = 0;
+
+    //
+    // Prepare Rank Mapping and Max Rank
+    //
+    for (rank = 0; rank < MAX_RANK_IN_CHANNEL; rank++) {
+      //
+      // rank in range(4):
+      //
+      if ((MRC_BIT0 << rank) & RankBitMask) {
+        ReutChSeqRankL2PMapping.Data |= (rank << (4 * RankCount));
+        RankCount += 1;
+      }
+    }
+    //
+    // Write New Rank Mapping and Max Rank
+    //
+    Offset = MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_0_REG +
+      (
+        (
+          MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_1_REG -
+          MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_0_REG
+        ) * ch
+      );
+    MrcWriteCR (MrcData, Offset, ReutChSeqRankL2PMapping.Data);
+    Offset = MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_0_REG + 7 +
+      ((MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_1_REG - MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_0_REG) * ch);
+    MrcWriteCR8 (MrcData, Offset, RankCount - 1);
+
+    //
+    // Make sure channel is enabled
+    //
+    Offset = MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_REG + ((MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_REG - MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_REG) * ch);
+    ReutChSeqCfg.Data                 = MrcReadCR (MrcData, Offset);
+    ReutChSeqCfg.Bits.Global_Control  = 1;
+    MrcWriteCR (MrcData, Offset, (U32) ReutChSeqCfg.Data);
+  }
+  //
+  // Need to convert RankFeatureEnable as an input parameter so we don't pass it all the time
+  //
+  if (RankFeatureEnable != 0) {
+    //
+    // Enable Refresh and ZQ - 0's to the the desired ranks
+    //
+    En = RankFeatureEnable & 0x3; // Refresh
+    ReutChMiscRefreshCtrl.Data                    = 0;
+    ReutChMiscRefreshCtrl.Bits.Refresh_Rank_Mask  = MCHBAR_CH0_CR_REUT_CH_MISC_REFRESH_CTRL_Refresh_Rank_Mask_MAX;
+    ReutChMiscRefreshCtrl.Bits.Panic_Refresh_Only = 1;
+
+    if (En == 1) {
+      ReutChMiscRefreshCtrl.Bits.Refresh_Rank_Mask = ~RankBitMask; // Enable all non-selected ranks
+    } else if (En > 1) {
+      ReutChMiscRefreshCtrl.Bits.Refresh_Rank_Mask = 0;           // Enable all ranks
+    }
+    Offset = MCHBAR_CH0_CR_REUT_CH_MISC_REFRESH_CTRL_REG +
+      ((MCHBAR_CH1_CR_REUT_CH_MISC_REFRESH_CTRL_REG - MCHBAR_CH0_CR_REUT_CH_MISC_REFRESH_CTRL_REG) * ch);
+    MrcWriteCR (MrcData, Offset, ReutChMiscRefreshCtrl.Data);
+
+    En = (RankFeatureEnable >> 2) & 0x3; // ZQ
+    ReutChMiscZqCtrl.Data              = 0;
+    ReutChMiscZqCtrl.Bits.ZQ_Rank_Mask = MCHBAR_CH0_CR_REUT_CH_MISC_ZQ_CTRL_ZQ_Rank_Mask_MAX;
+    ReutChMiscZqCtrl.Bits.Always_Do_ZQ = 1;
+    if (En == 1) {
+      ReutChMiscZqCtrl.Bits.ZQ_Rank_Mask = ~RankBitMask;
+    } else if (En > 1) {
+      ReutChMiscZqCtrl.Bits.ZQ_Rank_Mask = 0; // Enable all ranks
+    }
+    Offset =  MCHBAR_CH0_CR_REUT_CH_MISC_ZQ_CTRL_REG +
+      ((MCHBAR_CH1_CR_REUT_CH_MISC_ZQ_CTRL_REG - MCHBAR_CH0_CR_REUT_CH_MISC_ZQ_CTRL_REG) * ch);
+    MrcWriteCR (MrcData, Offset, ReutChMiscZqCtrl.Data);
+
+    //
+    // Enable CKE ranks - 1's to enable desired ranks
+    //
+    En = (RankFeatureEnable >> 4) & 0x3;
+    ReutChMiscCkeCtrl.Data        = 0;
+    ReutChMiscCkeCtrl.Bits.CKE_On = MCHBAR_CH0_CR_REUT_CH_MISC_CKE_CTRL_CKE_On_MAX;
+    if (En == 1) {
+      ReutChMiscCkeCtrl.Bits.CKE_On       = ~RankBitMask;
+      ReutChMiscCkeCtrl.Bits.CKE_Override = ~RankBitMask; // Enable all non-selected ranks
+    } else if (En > 1) {
+      ReutChMiscCkeCtrl.Bits.CKE_On       = MCHBAR_CH0_CR_REUT_CH_MISC_CKE_CTRL_CKE_On_MAX;
+      ReutChMiscCkeCtrl.Bits.CKE_Override = MCHBAR_CH0_CR_REUT_CH_MISC_CKE_CTRL_CKE_Override_MAX; // Enable all ranks.
+    }
+    Offset = MCHBAR_CH0_CR_REUT_CH_MISC_CKE_CTRL_REG +
+      ((MCHBAR_CH1_CR_REUT_CH_MISC_CKE_CTRL_REG - MCHBAR_CH0_CR_REUT_CH_MISC_CKE_CTRL_REG) * ch);
+    MrcWriteCR (MrcData, Offset, ReutChMiscCkeCtrl.Data);
+  }
+
+  return (U8) (MRC_BIT0 << ch);
+}
+
+/**
+  This routine updates RXTRAINRANK register's specific fields defined by the subfield
+  subfield values:
+    0 - Update RcvEn   - leave other parameter the same
+    1 - Update RxDqsP  - leave other parameter the same
+    2 - Update RxEq    - leave other parameter the same
+    3 - Update RxDqsN  - leave other parameter the same
+    4 - Update RxVref  - leave other parameter the same
+    5 - Update RxDqsP & RxDqsN - leave other parameter the same
+    FF - leave all parameter the same
+
+  @param[in] MrcData  - Include all MRC global data.
+  @param[in] Channel  - Defines channel to update
+  @param[in] Rank     - Defines rank to update
+  @param[in] Byte     - Defines byte to update
+  @param[in] Subfield - Defines the register's field or fields to update
+  @param[in] Value    - value to be writen into register fields
+
+  @retval Nothing
+**/
+void
+UpdateRxT (
+  IN MrcParameters *const MrcData,
+  IN const U8             Channel,
+  IN const U8             Rank,
+  IN const U8             Byte,
+  IN const U8             Subfield,
+  IN const U16            Value
+  )
+{
+  MrcChannelOut                       *ChannelOut;
+  U32                                 Offset;
+  DDRDATA0CH0_CR_RXTRAINRANK0_STRUCT  CrRxTrainRank;
+
+  ChannelOut                   = &MrcData->SysOut.Outputs.Controller[0].Channel[Channel];
+  CrRxTrainRank.Data           = 0;
+  CrRxTrainRank.Bits.RxRcvEnPi = (Subfield == 0) ? Value : ChannelOut->RcvEn[Rank][Byte];
+  CrRxTrainRank.Bits.RxDqsPPi  = ((Subfield == 1) || (Subfield == 5)) ? Value : ChannelOut->RxDqsP[Rank][Byte];
+  CrRxTrainRank.Bits.RxEq      = (Subfield == 2) ? Value : ChannelOut->RxEq[Rank][Byte];
+  CrRxTrainRank.Bits.RxDqsNPi  = ((Subfield == 3) || (Subfield == 5)) ? Value : ChannelOut->RxDqsN[Rank][Byte];
+  CrRxTrainRank.Bits.RxVref    = (Subfield == 4) ? Value : ChannelOut->RxVref[Byte];
+
+  Offset = DDRDATA0CH0_CR_RXTRAINRANK0_REG +
+    ((DDRDATA0CH1_CR_RXTRAINRANK0_REG - DDRDATA0CH0_CR_RXTRAINRANK0_REG) * Channel) +
+    ((DDRDATA0CH0_CR_RXTRAINRANK1_REG - DDRDATA0CH0_CR_RXTRAINRANK0_REG) * Rank) +
+    ((DDRDATA1CH0_CR_RXTRAINRANK0_REG - DDRDATA0CH0_CR_RXTRAINRANK0_REG) * Byte);
+  MrcWriteCR (MrcData, Offset, CrRxTrainRank.Data);
+  //
+  // Download new settings from the RegFile to the Pads
+  //
+  MrcDownloadRegFile (MrcData, Channel, 0, Rank, MrcRegFileRank, Byte, 1, 0);
+  return;
+}
+
+/**
+  This routine updates TXTRAINRANK register's specific fields defined by the subfield
+  subfield values:
+    0 - Update TxDq    - leave other parameter the same
+    1 - Update TxDqs   - leave other parameter the same
+    2 - Update TxEq    - leave other parameter the same
+    3 - Update ALL from input value (non from Mrcdata structure)
+
+  @param[in] MrcData  - Include all MRC global data.
+  @param[in] Channel  - Defines channel to update
+  @param[in] Rank     - Defines rank to update
+  @param[in] Byte     - Defines byte to update
+  @param[in] Subfield - Defines the register's field or fields to update
+  @param[in] Value    - value to be writen into register fields
+
+  @retval Nothing
+**/
+void
+UpdateTxT (
+  IN MrcParameters *const MrcData,
+  IN const U8             Channel,
+  IN const U8             Rank,
+  IN const U8             Byte,
+  IN const U8             Subfield,
+  IN const U32            Value
+  )
+{
+  MrcChannelOut                       *ChannelOut;
+  U32                                 Offset;
+  DDRDATA0CH0_CR_TXTRAINRANK0_STRUCT  CrTxTrainRank;
+
+  ChannelOut = &MrcData->SysOut.Outputs.Controller[0].Channel[Channel];
+  if (Subfield == 3) {
+    CrTxTrainRank.Data = Value;
+  } else {
+    CrTxTrainRank.Data                = 0;
+    CrTxTrainRank.Bits.TxDqDelay      = (Subfield == 0) ? Value : ChannelOut->TxDq[Rank][Byte];
+    CrTxTrainRank.Bits.TxDqsDelay     = (Subfield == 1) ? Value : ChannelOut->TxDqs[Rank][Byte];
+    CrTxTrainRank.Bits.TxEqualization = (Subfield == 2) ? Value : ChannelOut->TxEq[Rank][Byte];
+  }
+
+  Offset = DDRDATA0CH0_CR_TXTRAINRANK0_REG +
+    ((DDRDATA0CH1_CR_TXTRAINRANK0_REG - DDRDATA0CH0_CR_TXTRAINRANK0_REG) * Channel) +
+    ((DDRDATA0CH0_CR_TXTRAINRANK1_REG - DDRDATA0CH0_CR_TXTRAINRANK0_REG) * Rank) +
+    ((DDRDATA1CH0_CR_TXTRAINRANK0_REG - DDRDATA0CH0_CR_TXTRAINRANK0_REG) * Byte);
+  MrcWriteCR (MrcData, Offset, CrTxTrainRank.Data);
+  //
+  // Download new settings from the RegFile to the Pads
+  //
+  MrcDownloadRegFile (MrcData, Channel, 0, Rank, MrcRegFileRank, Byte, 0, 1);
+  return;
+}
+
+/**
+  Returns the index into the array MarginResult in the MrcOutput structure.
+
+  @param[in] ParamV - Margin parameter
+
+  @retval One of the following values: LastRxV(0), LastRxT (1), LastTxV(2), LastTxT (3), LastRcvEna (4),
+                                       LastWrLevel (5), LastCmdT (6), LastCmdV (7)
+**/
+U8
+GetMarginResultType (
+  IN const U8  ParamV
+  )
+{
+  switch (ParamV) {
+    case WrV:
+    case WrFan2:
+    case WrFan3:
+      return LastTxV;
+
+    case WrT:
+      return LastTxT;
+
+    case RdV:
+    case RdFan2:
+    case RdFan3:
+      return LastRxV;
+
+    case RdT:
+      return LastRxT;
+
+    case RcvEna:
+    case RcvEnaX:
+      return LastRcvEna;
+
+    case WrLevel:
+      return LastWrLevel;
+
+    case CmdT:
+      return LastCmdT;
+
+    case CmdV:
+      return LastCmdV;
+
+    default:
+      //MRC_DEBUG_MSG (Debug, MSG_LEVEL_ERROR, "GetMarginByte: Unknown Margin Parameter\n");
+      break;
+  }
+
+  return 0; // Return LastRxV to point to the beginning of the array
+}
+
+/*
+1D Margin Types:
+RcvEn:   Shifts just RcvEn.  Only side effect is it may eat into read dq-dqs for first bit of burst
+RdT:     Shifts read DQS timing, changing where DQ is sampled
+WrT:     Shifts write DQ timing, margining DQ-DQS timing
+WrDqsT:  Shifts write DQS timing, margining both DQ-DQS and DQS-CLK timing
+RdV:     Shifts read Vref voltage for DQ only
+WrV:     Shifts write Vref voltage for DQ only
+WrLevel: Shifts write DQ and DQS timing, margining only DQS-CLK timing
+WrTBit:  Shifts write DQ per bit timing.
+RdTBit:  Shifts read DQ per bit timing.
+RdVBit:  Shifts read DQ per bit voltage.
+
+2D Margin Types (Voltage, Time)
+RdFan2:  Margins both RdV and RdT at { (off, -2/3*off),  (off, 2/3*off) }
+WrFan2:  Margins both WrV and WrT at { (off, -2/3*off),  (off, 2/3*off) }
+RdFan3:  Margins both RdV and RdT at { (off, -2/3*off),  (5/4*off, 0),  (off, 2/3*off)  }
+WrFan3:  Margins both WrV and WrT at { (off, -2/3*off),  (5/4*off, 0),  (off, 2/3*off)  }
+*/
+/**
+  This function Reads MrcData structure and finds the minimum last recorded margin for param
+  Searches across all bytes and ranks in RankMask
+
+  @param[in]     MrcData         - Include all MRC global data.
+  @param[in,out] MarginResult    - Data structure with the latest margin results.
+  @param[in]     Param           - Defines the margin type
+  @param[in]     Ranks           - Condenses down the results from multiple ranks
+
+  @retval mrcWrongInputParameter if a bad Param is passed in, otherwise mrcSuccess.
+**/
+MrcStatus
+GetMarginCh (
+  IN     MrcParameters *const MrcData,
+  IN OUT U32                  MarginResult[MAX_RESULT_TYPE][MAX_RANK_IN_CHANNEL][MAX_CHANNEL][MAX_SDRAM_IN_DIMM][MAX_EDGES],
+  IN     const U8             Param,
+  IN     const U8             Ranks
+  )
+{
+  MrcOutput *Outputs;
+  U32       *Margin1;
+  U32       *Margin2;
+  U8        ResultType;
+  U8        Channel;
+  U8        Rank;
+  U8        Byte;
+  U8        Edge;
+  U8        Scale;
+
+  Outputs = &MrcData->SysOut.Outputs;
+  switch (Param) {
+    case WrV:
+    case WrT:
+    case RdV:
+    case RdT:
+      Scale = 10;
+      break;
+
+    case WrFan2:
+    case WrFan3:
+    case RdFan2:
+    case RdFan3:
+      Scale = 21 / 3;
+      break;
+
+    default:
+      MRC_DEBUG_MSG (&MrcData->SysIn.Inputs.Debug, MSG_LEVEL_ERROR, "GetMarginCh: Unknown Margin Parameter\n");
+      return mrcWrongInputParameter;
+  }
+
+  ResultType = GetMarginResultType (Param);
+  for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+    if (MrcChannelExist (Outputs, Channel)) {
+      Margin2 = &MarginResult[ResultType][0][Channel][0][0];
+      for (Byte = 0; Byte < Outputs->SdramCount; Byte++) {
+        for (Rank = 0; Rank < MAX_RANK_IN_CHANNEL; Rank++) {
+          if (MrcRankInChannelExist (MrcData, Rank, Channel) & Ranks) {
+            Margin1 = &MarginResult[ResultType][Rank][Channel][Byte][0];
+            for (Edge = 0; Edge < MAX_EDGES; Edge++, Margin1++) {
+              if (Margin2[Edge] > *Margin1) {
+                Margin2[Edge] = *Margin1;
+              }
+            }
+          }
+        }
+      }
+      //
+      // Scale results as needed
+      //
+      for (Edge = 0; Edge < MAX_EDGES; Edge++, Margin2++) {
+        *Margin2 = (*Margin2 * Scale) / 10;
+      }
+    }
+  }
+
+  return mrcSuccess;
+}
+
+/**
+  Use this function to retrieve the last margin results from MrcData
+
+  @param[in]     MrcData         - Include all MRC global data.
+  @param[in,out] MarginResult    - Data structure with the latest margin results.
+  @param[in]     Param           - Defines the margin type
+  @param[in]     RankIn          - Which rank of the host structure you want the result returned on
+  @param[in]     Ranks           - Condenses down the results from multiple ranks
+
+  @retval MarginResult structure has been updated if MrcStatus returns mrcSuccess.
+  @retval Otherwise, mrcWrongInputParameter is returned if an incorrect Param is passed in.
+**/
+MrcStatus
+GetMarginByte (
+  IN     MrcParameters *const MrcData,
+  IN OUT U32                  MarginResult[MAX_RESULT_TYPE][MAX_RANK_IN_CHANNEL][MAX_CHANNEL][MAX_SDRAM_IN_DIMM][MAX_EDGES],
+  IN     const U8             Param,
+  IN     const U8             RankIn,
+  IN     const U8             Ranks
+  )
+{
+  MrcOutput *Outputs;
+  U32       *Margin1;
+  U32       *Margin2;
+  U8        ResultType;
+  U8        Channel;
+  U8        Rank;
+  U8        Byte;
+  U8        Edge;
+  U8        Scale;
+
+  Outputs = &MrcData->SysOut.Outputs;
+  switch (Param) {
+    case WrV:
+    case WrT:
+    case RdV:
+    case RdT:
+    case RcvEna:
+    case RcvEnaX:
+      Scale = 10;
+      break;
+
+    case WrFan2:
+    case WrFan3:
+    case RdFan2:
+    case RdFan3:
+      Scale = 21 / 3;
+      break;
+
+    default:
+      MRC_DEBUG_MSG (&MrcData->SysIn.Inputs.Debug, MSG_LEVEL_ERROR, "GetMarginByte: Unknown Margin Parameter\n");
+      return mrcWrongInputParameter;
+  }
+
+  ResultType = GetMarginResultType (Param);
+  for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+    if (MrcChannelExist (Outputs, Channel)) {
+      for (Byte = 0; Byte < Outputs->SdramCount; Byte++) {
+        for (Rank = 0; Rank < MAX_RANK_IN_CHANNEL; Rank++) {
+          if (MrcRankInChannelExist (MrcData, Rank, Channel) & Ranks) {
+            Margin1 = &MarginResult[ResultType][RankIn][Channel][Byte][0];
+            Margin2 = &MarginResult[ResultType][Rank][Channel][Byte][0];
+            for (Edge = 0; Edge < MAX_EDGES; Edge++, Margin1++, Margin2++) {
+              if (*Margin1 > *Margin2) {
+                *Margin1 = *Margin2;
+              }
+            }
+          }
+        }
+        //
+        // Scale results as needed
+        //
+        Margin1 = &MarginResult[ResultType][RankIn][Channel][Byte][0];
+        for (Edge = 0; Edge < MAX_EDGES; Edge++, Margin1++) {
+          *Margin1 = (*Margin1 * Scale) / 10;
+        }
+      }
+    }
+  }
+
+  return mrcSuccess;
+}
+
+/**
+  This function is use to "unscale" the MrcData last margin point
+  GetMarginByte will scale the results for FAN margin
+  This will unscale the results such that future tests start at the correct point
+
+  @param[in]     MrcData      - Include all MRC global data.
+  @param[in,out] MarginResult - Input array to be unscaled.
+  @param[in]     Param        - Defines the margin type for proper scale selection.
+  @param[in]     Rank         - Which rank of the host structure to work on
+
+  @retval mrcSuccess
+**/
+MrcStatus
+ScaleMarginByte (
+  IN     MrcParameters *const MrcData,
+  IN OUT U32                  MarginResult[MAX_RESULT_TYPE][MAX_RANK_IN_CHANNEL][MAX_CHANNEL][MAX_SDRAM_IN_DIMM][MAX_EDGES],
+  IN     const U8             Param,
+  IN     const U8             Rank
+  )
+{
+  MrcOutput *Outputs;
+  U32       *Margin;
+  U8        ResultType;
+  U8        Channel;
+  U8        Byte;
+  U8        Edge;
+
+  //
+  // Calculate scale parameter based on param
+  // Leave room for expansion in case other params needed to be scaled
+  //
+  Outputs = &MrcData->SysOut.Outputs;
+  if ((Param == RdFan2) || (Param == RdFan3) || (Param == WrFan2) || (Param == WrFan3)) {
+    ResultType = GetMarginResultType (Param);
+    for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+      if (MrcChannelExist (Outputs, Channel)) {
+        for (Byte = 0; Byte < Outputs->SdramCount; Byte++) {
+          Margin = &MarginResult[ResultType][Rank][Channel][Byte][0];
+          for (Edge = 0; Edge < MAX_EDGES; Edge++, Margin++) {
+            *Margin = (*Margin * 15) / 10;
+          }
+        }
+      }
+    }
+  }
+
+  return mrcSuccess;
+}
+
+/**
+  This function is used by most margin search functions to change te underlying margin parameter.
+  This function allows single search function to be used for different types of margins with minimal impact.
+  It provides multiple different parameters, including 2D parameters like Read or Write FAN.
+  It can work in either MultiCast or single register mode.
+
+  @param[in,out] MrcData       - Include all MRC global data.
+  @param[in]     param         - Includes parameter(s) to change including two dimentional.
+  @param[in]     value0        - Selected value to program margin param to
+  @param[in]     value1        - Selected value to program margin param to in 2D mode (FAN mode)
+  @param[in]     EnMultiCast   - To enable Multicast (broadcast) or single register mode
+  @param[in]     channel       - Desired Channel
+  @param[in]     rankIn        - Desired Rank - only used for the RxTBit and TxTBit settings and to propagate RdVref
+  @param[in]     byte          - Desired byte offset register
+  @param[in]     bitIn         - Desired bit offset Mrc data strucure if UpdateMrcData is 1
+  @param[in]     UpdateMrcData - Used to decide if Mrc host must be updated
+  @param[in]     SkipWait      - Used to skip wait until all channel are done
+  @param[in]     RegFileParam  - Used to determine which Rank to download.  Passed to MrcDownloadRegFile.
+
+  @retval MrcStatus -  if succeeded, return mrcSuccess
+**/
+MrcStatus
+ChangeMargin (
+  IN OUT MrcParameters *const MrcData,
+  IN     const U8             param,
+  IN     const S32            value0,
+  IN     const S32            value1,
+  IN     const U8             EnMultiCast,
+  IN     const U8             channel,
+  IN     const U8             rankIn,
+  IN     const U8             byte,
+  IN     const U8             bitIn,
+  IN     const U8             UpdateMrcData,
+  IN     const U8             SkipWait,
+  IN     const MrcRegFile     RegFileParam
+  )
+{
+  //
+  // Programs margin param to the selected value0
+  // If param is a 2D margin parameter (ex: FAN), then it uses both value0 and value1
+  //    For an N point 2D parameter, value1 can be an interger from 0 to (N-1)
+  //    For per bit timing parameter, value1 is the sign of the shift
+  // param = {0:RcvEna, 1:RdT, 2:WrT, 3: WrDqsT, 4:RdV, 5:WrV, 6:WrLevel,
+  //               7:WrTBox, 8:WrTBit, 9:RdTBit, 10:RdVBit,
+  //              16:RdFan2, 17:WrFan2, 32:RdFan3, 33:WrFan3}
+  // Note: For Write Vref, the trained value and margin register are the same
+  // Note: rank is only used for the RxTBit and TxTBit settings and to propagate RdVref
+  // Note: PerBit Settings (WrTBit, RdTBit, RdVBit) provide all 8 offsets in value0
+
+  const MrcDebug    *Debug;
+  const MrcInput    *Inputs;
+  MrcOutput         *Outputs;
+  MrcControllerOut  *ControllerOut;
+  MrcChannelOut     *ChannelOut;
+  MrcChannelOut     *CurrentChannelOut;
+  MrcStatus         Status;
+  U8                CurrentCh;
+  U8                CurrentByte;
+  U8                Max0;
+  U8                MaxT;
+  U8                MaxV;
+  U8                maskT;
+  U8                rank;
+  U8                bit;
+  U8                ReadRFRd;
+  U8                ReadRFWr;
+  S32               sign;
+  S32               v0;
+  S32               v1;
+  U32               Offset;
+  BOOL              UpdateDataOffset;
+  DDRDATA0CH0_CR_DDRCRDATAOFFSETTRAIN_STRUCT CRValue;
+  MCHBAR_CH0_CR_SC_IO_LATENCY_STRUCT         ScIoLatency;
+
+  Status            = mrcSuccess;
+  UpdateDataOffset  = FALSE;
+  ReadRFRd          = 0;
+  ReadRFWr          = 0;
+  Inputs            = &MrcData->SysIn.Inputs;
+  Debug             = &Inputs->Debug;
+  Outputs           = &MrcData->SysOut.Outputs;
+  ControllerOut     = &Outputs->Controller[0];
+
+  //
+  // Pre-Process the margin numbers
+  //
+  MaxT   = MAX_POSSIBLE_TIME;   // Maximum value for Time
+  MaxV   = MAX_POSSIBLE_VREF;   // Maximum value for Vref
+  maskT  = 0x3F; // 6 bits (2's complement)
+
+  if ((param < RdV) || (param == WrLevel)) {
+    Max0 = MaxT;
+  } else if ((param == WrTBit) || (param == RdTBit) || (param == RdVBit)) {
+    Max0 = 0xFF;
+  } else {
+    Max0 = MaxV; // Vref for RdV, WrV, and FAN modes
+  }
+  //
+  // Pre-Process the margin numbers.  Calculate 2D points based on FAN slopes
+  //
+  v0    = value0;
+  sign  = (2 * value1 - 1);
+
+  //
+  // For Fan3, optimize point orders to minimize Vref changes and # of tests required
+  //
+  if (param >= RdFan3) {
+    sign = ((3 * value1 - 5) * value1) / 2;   // Translates to {0:0, 1:-1, 2:+1}
+    if (value1 == 0) {
+      v0 = (5 * value0) / 4;
+    }
+  }
+
+  v1 = (sign * value0) / 3;
+  if (v0 > Max0) {
+    v0 = Max0;
+  } else if (v0 < (-1 * Max0)) {
+    v0 = (-1 * Max0);
+  }
+
+  if (v1 > MaxT) {
+    v1 = MaxT;
+  } else if (v1 < (0 - MaxT)) {
+    v1 = (0 - MaxT);
+  }
+  //
+  // Rank = -1 sometimes if used to indicate all ranks
+  // Does not make sense here, hence set to 0)
+  //
+  rank          = (rankIn == 0xFF) ? 0 : rankIn;
+
+  ChannelOut    = &ControllerOut->Channel[channel];
+  CRValue.Data  = ChannelOut->DataOffsetTrain[byte];
+  switch (param) {
+    case RcvEna:
+      CRValue.Bits.RcvEnOffset = (U32) v0;
+      UpdateDataOffset         = TRUE;
+      break;
+
+    case RdT:
+      CRValue.Bits.RxDqsOffset = (U32) v0;
+      UpdateDataOffset         = TRUE;
+      break;
+
+    case WrT:
+      CRValue.Bits.TxDqOffset = (U32) v0;
+      UpdateDataOffset        = TRUE;
+      break;
+
+    case WrDqsT:
+      CRValue.Bits.TxDqsOffset = (U32) v0;
+      UpdateDataOffset         = TRUE;
+      break;
+
+    case RdV:
+      CRValue.Bits.VrefOffset = (U32) v0;
+      UpdateDataOffset        = TRUE;
+      break;
+
+    case RcvEnaX:
+      //
+      // Calculate new IOComp Latency to include over/underflow
+      //
+      Offset = MCHBAR_CH0_CR_SC_IO_LATENCY_REG +
+        ((MCHBAR_CH1_CR_SC_IO_LATENCY_REG - MCHBAR_CH0_CR_SC_IO_LATENCY_REG) * channel);
+      ScIoLatency.Data = MrcReadCR (MrcData, Offset);
+      if (v0 > 0) {
+        v0 = v0 * 2 - 16;
+        ScIoLatency.Bits.RT_IOCOMP = (MCHBAR_CH0_CR_SC_IO_LATENCY_RT_IOCOMP_MAX & (ChannelOut->RTIoComp - 1));
+      } else if (v0 < 0) {
+        v0 = v0 * 2 + 16;
+        ScIoLatency.Bits.RT_IOCOMP = (MCHBAR_CH0_CR_SC_IO_LATENCY_RT_IOCOMP_MAX & (ChannelOut->RTIoComp + 1));
+      } else {
+        ScIoLatency.Bits.RT_IOCOMP = (MCHBAR_CH0_CR_SC_IO_LATENCY_RT_IOCOMP_MAX & ChannelOut->RTIoComp);
+      }
+
+      v0 +=  ChannelOut->RcvEn[rank][byte];// the assumption is that we are @ 1 Qclk before edge
+      //
+      // Limit RcvEna 0-511 to prevent under/overflow.
+      //
+      if (v0 < 0) {
+        MRC_DEBUG_MSG (Debug, MSG_LEVEL_WARNING, "WARNING: RcvEn PI wrapped below zero!\n");
+        v0 = 0;
+      } else if (v0 > DDRDATA_CR_RXTRAINRANK0_RxRcvEnPi_MAX) {
+        MRC_DEBUG_MSG (Debug, MSG_LEVEL_WARNING, "WARNING: RcvEn PI wrapped above 9 bits!\n");
+        v0 = DDRDATA_CR_RXTRAINRANK0_RxRcvEnPi_MAX;
+      }
+      UpdateRxT (MrcData, channel, rank, byte, 0,(U16) v0);
+      MrcWriteCR (MrcData, Offset, ScIoLatency.Data);
+      break;
+
+    case WrV:
+    case WrFan2:
+    case WrFan3:
+      for (CurrentCh = 0; CurrentCh < MAX_CHANNEL; CurrentCh++) {
+        if (MrcChannelExist (Outputs, CurrentCh)) {
+          if ((EnMultiCast == 1) || (CurrentCh == channel)) {
+            UpdateVrefWaitTilStable (MrcData, CurrentCh, UpdateMrcData, v0, SkipWait);
+          }
+        }
+      }
+
+      if ((param == WrFan2) || (param == WrFan3)) {
+        CRValue.Data            = ChannelOut->DataOffsetTrain[byte];
+        CRValue.Bits.TxDqOffset = v1; // Update TxDqOffset
+        UpdateDataOffset = TRUE;
+      }
+      break;
+
+    case RdFan2:  // Read margin in FAN modes.
+    case RdFan3:
+      CRValue.Data             = ChannelOut->DataOffsetTrain[byte];
+      CRValue.Bits.VrefOffset  = v0; // Update VrefOffset
+      CRValue.Bits.RxDqsOffset = v1; // Update RxDqsOffset
+      UpdateDataOffset = TRUE;
+      break;
+
+    case WrLevel: // Write DQ and DQS timing, margining only DQS-CLK timing
+      CRValue.Data             = ChannelOut->DataOffsetTrain[byte];
+      CRValue.Bits.TxDqOffset  = v0; // Update TxDqOffset
+      CRValue.Bits.TxDqsOffset = v0; // Update TxDqsOffset
+      UpdateDataOffset = TRUE;
+      break;
+
+    case WrTBit:  // Write DQ per BIT timing
+      ReadRFWr = 1;
+      if (EnMultiCast) {
+        Offset = DDRDATA_CR_TXPERBITRANK0_REG +
+          ((DDRDATA_CR_TXPERBITRANK1_REG - DDRDATA_CR_TXPERBITRANK0_REG) * rank);
+        MrcWriteCrMulticast (MrcData, Offset, value0);
+        for (CurrentCh = 0; CurrentCh < MAX_CHANNEL; CurrentCh++) {
+          CurrentChannelOut = &ControllerOut->Channel[CurrentCh];
+          //
+          // Download new settings from the RegFile to the Pads
+          //
+          MrcDownloadRegFile (MrcData, CurrentCh, 1, rank, RegFileParam, 0, ReadRFRd, ReadRFWr);
+          if (UpdateMrcData) {
+            for (CurrentByte = 0; CurrentByte < Outputs->SdramCount; CurrentByte++) {
+              for (bit = 0; bit < MAX_BITS; bit++) {
+                CurrentChannelOut->TxDqPb[rank][CurrentByte][bit].Center = (value0 >> (4 * bit)) & 0xF;
+              }
+            }
+          }
+        }
+      } else {
+        Offset = DDRDATA0CH0_CR_TXPERBITRANK0_REG +
+          ((DDRDATA0CH0_CR_TXPERBITRANK1_REG - DDRDATA0CH0_CR_TXPERBITRANK0_REG) * rank) +
+          ((DDRDATA1CH0_CR_TXPERBITRANK0_REG - DDRDATA0CH0_CR_TXPERBITRANK0_REG) * byte) +
+          ((DDRDATA0CH1_CR_TXPERBITRANK0_REG - DDRDATA0CH0_CR_TXPERBITRANK0_REG) * channel);
+        MrcWriteCR (MrcData, Offset, value0);
+        //
+        // Download new settings from the RegFile to the Pads
+        //
+        MrcDownloadRegFile (MrcData, channel, 0, rank, RegFileParam, byte, ReadRFRd, ReadRFWr);
+        if (UpdateMrcData) {
+          for (bit = 0; bit < MAX_BITS; bit++) {
+            ChannelOut->TxDqPb[rank][byte][bit].Center = (value0 >> (4 * bit)) & 0xF;
+          }
+        }
+      }
+      break;
+
+    case RdTBit:  // Read DQ per BIT timing
+      ReadRFRd = 1;
+      if (EnMultiCast) {
+        Offset = DDRDATA_CR_RXPERBITRANK0_REG +
+          ((DDRDATA_CR_RXPERBITRANK1_REG - DDRDATA_CR_RXPERBITRANK0_REG) * rank);
+        MrcWriteCrMulticast (MrcData, Offset, value0);
+        for (CurrentCh = 0; CurrentCh < MAX_CHANNEL; CurrentCh++) {
+          CurrentChannelOut = &ControllerOut->Channel[CurrentCh];
+          //
+          // Download new settings from the RegFile to the Pads
+          //
+          MrcDownloadRegFile (MrcData, CurrentCh, 1, rank, RegFileParam, 0, ReadRFRd, ReadRFWr);
+          if (UpdateMrcData) {
+            for (CurrentByte = 0; CurrentByte < Outputs->SdramCount; CurrentByte++) {
+              for (bit = 0; bit < MAX_BITS; bit++) {
+                CurrentChannelOut->RxDqPb[rank][CurrentByte][bit].Center = (value0 >> (4 * bit)) & 0xF;
+              }
+            }
+          }
+        }
+      } else {
+        Offset = DDRDATA0CH0_CR_RXPERBITRANK0_REG +
+          ((DDRDATA0CH0_CR_RXPERBITRANK1_REG - DDRDATA0CH0_CR_RXPERBITRANK0_REG) * rank) +
+          ((DDRDATA1CH0_CR_RXPERBITRANK0_REG - DDRDATA0CH0_CR_RXPERBITRANK0_REG) * byte) +
+          ((DDRDATA0CH1_CR_RXPERBITRANK0_REG - DDRDATA0CH0_CR_RXPERBITRANK0_REG) * channel);
+        MrcWriteCR (MrcData, Offset, value0);
+        //
+        // Download new settings from the RegFile to the Pads
+        //
+        MrcDownloadRegFile (MrcData, channel, 0, rank, RegFileParam, byte, ReadRFRd, ReadRFWr);
+        if (UpdateMrcData) {
+          for (bit = 0; bit < MAX_BITS; bit++) {
+            ChannelOut->RxDqPb[rank][byte][bit].Center = (value0 >> (4 * bit)) & 0xF;
+          }
+        }
+      }
+      break;
+
+    case RdVBit:  // Read DQ per BIT Voltage
+      ReadRFRd = 1;
+      if (EnMultiCast) {
+        MrcWriteCrMulticast (MrcData, DDRDATA_CR_RXOFFSETVDQ_REG, value0);
+        for (CurrentCh = 0; CurrentCh < MAX_CHANNEL; CurrentCh++) {
+          CurrentChannelOut = &ControllerOut->Channel[CurrentCh];
+          //
+          // Download new settings from the RegFile to the Pads
+          //
+          MrcDownloadRegFile (MrcData, CurrentCh, 1, rank, RegFileParam, 0, ReadRFRd, ReadRFWr);
+          if (UpdateMrcData) {
+            for (CurrentByte = 0; CurrentByte < Outputs->SdramCount; CurrentByte++) {
+              for (bit = 0; bit < MAX_BITS; bit++) {
+                CurrentChannelOut->RxDqVrefPb[rank][CurrentByte][bit].Center = (value0 >> (4 * bit)) & 0xF;
+              }
+            }
+          }
+        }
+      } else {
+        Offset = DDRDATA0CH0_CR_RXOFFSETVDQ_REG +
+          ((DDRDATA1CH0_CR_RXOFFSETVDQ_REG - DDRDATA0CH0_CR_RXOFFSETVDQ_REG) * byte) +
+          ((DDRDATA0CH1_CR_RXOFFSETVDQ_REG - DDRDATA0CH0_CR_RXOFFSETVDQ_REG) * channel);
+        MrcWriteCR (MrcData, Offset, value0);
+        //
+        // Download new settings from the RegFile to the Pads
+        //
+        MrcDownloadRegFile (MrcData, channel, 0, rank, RegFileParam, byte, ReadRFRd, ReadRFWr);
+        if (UpdateMrcData) {
+          ChannelOut = &ControllerOut->Channel[channel];
+          for (bit = 0; bit < MAX_BITS; bit++) {
+            ChannelOut->RxDqVrefPb[rank][byte][bit].Center = (value0 >> (4 * bit)) & 0xF;
+          }
+        }
+      }
+
+      break;
+
+    default:
+      MRC_DEBUG_MSG (Debug, MSG_LEVEL_ERROR, "Function ChangeMargin, Invalid parameter %d\n", param);
+      return mrcWrongInputParameter;
+  } // end switch (param)
+
+  if (UpdateDataOffset) {
+    //
+    // Download new settings from the RegFile to the Pads
+    //
+    if ((param == RcvEnaX) ||(param == RcvEna) || (param == RdT) || (param == RdV) || (param == RdFan2) || (param == RdFan3)) {
+      ReadRFRd = 1;
+    } else if ((param == WrT) || (param == WrDqsT) || (param == WrLevel) || (param == WrFan2) || (param == WrFan3)) {
+      ReadRFWr = 1;
+    }
+    //
+    // Write CR
+    //
+    if (EnMultiCast) {
+      MrcWriteCrMulticast (MrcData, DDRDATA_CR_DDRCRDATAOFFSETTRAIN_REG, CRValue.Data);
+      for (CurrentCh = 0; CurrentCh < MAX_CHANNEL; CurrentCh++) {
+        if (MrcChannelExist (Outputs, CurrentCh)) {
+          CurrentChannelOut = &ControllerOut->Channel[CurrentCh];
+          //
+          // Download new settings from the RegFile to the Pads
+          //
+          MrcDownloadRegFile (MrcData, CurrentCh, 1, rank, RegFileParam, 0, ReadRFRd, ReadRFWr);
+          for (CurrentByte = 0; CurrentByte < Outputs->SdramCount; CurrentByte++) {
+            if (UpdateMrcData) {
+              CurrentChannelOut->DataOffsetTrain[CurrentByte] = CRValue.Data;
+            }
+          }
+        }
+      }
+    } else {
+      Offset = DDRDATA0CH0_CR_DDRCRDATAOFFSETTRAIN_REG +
+        ((DDRDATA0CH1_CR_DDRCRDATAOFFSETTRAIN_REG - DDRDATA0CH0_CR_DDRCRDATAOFFSETTRAIN_REG) * channel) +
+        ((DDRDATA1CH0_CR_DDRCRDATAOFFSETTRAIN_REG - DDRDATA0CH0_CR_DDRCRDATAOFFSETTRAIN_REG) * byte);
+      MrcWriteCR (MrcData, Offset, CRValue.Data);
+      //
+      // Download new settings from the RegFile to the Pads
+      //
+      MrcDownloadRegFile (MrcData, channel, 0, rank, RegFileParam, byte, ReadRFRd, ReadRFWr);
+      if (UpdateMrcData) {
+        ChannelOut->DataOffsetTrain[byte] = CRValue.Data;
+      }
+    }
+  }
+
+  return Status;
+}
+
+/**
+  This function triggers the hardware to download the specified RegFile.
+  The setting of ReadRfRd and ReadRfWr must be mutually exclusive.
+  Only 1 (start download) and 0 (do nothing) are valid values for ReadRfXx.
+
+  @param[in] MrcData       - Global MRC Data
+  @param[in] Channel       - The Channel to download target.
+  @param[in] ByteMulticast - Enable Multicasting all bytes on that Channel.
+  @param[in] Rank          - The Rank download target.
+  @param[in] RegFileParam  - Used to determine which Rank to download.
+                              MrcRegFileRank - Uses the Rank Parameter.
+                              MrcRegFileStart    - Uses the Rank in REUT_CH_SEQ_BASE_ADDR_START after decoding logical to physical.
+                              MrcRegFileCurrent  - Uses the Rank in REUT_CH_SEQ_BASE_ADDR_CURRENT after decoding logical to physical.
+  @param[in] Byte          - The Byte download target.
+  @param[in] ReadRfRd      - Download the read RegFile. 1 enables, 0 otherwise
+  @param[in] ReadRfWr      - Download the write RegFile. 1 enables, 0 otherwise
+
+  @retval MrcStatus - If both ReadRfRd and ReadRfWr are set, the functions returns mrcWrongInputParameters.
+                         Otherwise, mrcSuccess.
+**/
+void
+MrcDownloadRegFile (
+  IN MrcParameters *const MrcData,
+  IN const U8             Channel,
+  IN const BOOL           ByteMulticast,
+  IN  U8                  Rank,
+  IN const MrcRegFile     RegFileParam,
+  IN const U8             Byte,
+  IN const BOOL           ReadRfRd,
+  IN const BOOL           ReadRfWr
+  )
+{
+  DDRDATA0CH0_CR_DDRCRDATACONTROL0_STRUCT                                 DdrCrDataControl0;
+  MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_0_STRUCT  ReutChSeqRankL2PMapping;
+  U64                                                                     ReutChSeqBaseAddr;
+  MrcChannelOut                                                           *ChannelOut;
+  U32                                                                     CrOffset;
+  U8                                                                      LogicalRank;
+
+  ChannelOut = &MrcData->SysOut.Outputs.Controller[0].Channel[Channel];
+  //
+  // Determine the rank to download the Reg File
+  //
+  switch (RegFileParam) {
+    case MrcRegFileStart:
+      CrOffset = MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_0_REG +
+      (
+        (MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_1_REG - MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_0_REG) *
+        Channel
+      );
+      break;
+
+    case MrcRegFileCurrent:
+      CrOffset = MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_0_REG +
+        (
+          (MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_1_REG - MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_0_REG) *
+          Channel
+        );
+      break;
+
+    case MrcRegFileRank:
+    default:
+      CrOffset = 0;
+      break;
+  }
+
+  if (CrOffset != 0) {
+    ReutChSeqBaseAddr  = MrcReadCR64 (MrcData, CrOffset);
+    ReutChSeqBaseAddr &= MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_0_Rank_Address_MSK;
+    LogicalRank        = (U8) MrcOemMemoryRightShiftU64 (
+                               ReutChSeqBaseAddr,
+                               MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_0_Rank_Address_OFF
+                               );
+
+    CrOffset = MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_0_REG +
+      (
+        (
+          MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_1_REG -
+          MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_0_REG
+        ) * Channel
+      );
+    ReutChSeqRankL2PMapping.Data = MrcReadCR (MrcData, CrOffset);
+    Rank = (U8)
+      (
+        (ReutChSeqRankL2PMapping.Data >> (LogicalRank * 4)) &
+        MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_0_Logical_to_Physical_Rank0_Mapping_MSK
+      );
+  }
+
+  if (ByteMulticast) {
+    //
+    // Multicast settings on the channel
+    //
+    CrOffset = DDRDATACH0_CR_DDRCRDATACONTROL0_REG +
+      ((DDRDATACH1_CR_DDRCRDATACONTROL0_REG - DDRDATACH0_CR_DDRCRDATACONTROL0_REG) * Channel);
+  } else {
+    CrOffset = DDRDATA0CH0_CR_DDRCRDATACONTROL0_REG +
+      ((DDRDATA0CH1_CR_DDRCRDATACONTROL0_REG - DDRDATA0CH0_CR_DDRCRDATACONTROL0_REG) * Channel) +
+      ((DDRDATA1CH0_CR_DDRCRDATACONTROL0_REG - DDRDATA0CH0_CR_DDRCRDATACONTROL0_REG) * Byte);
+  }
+
+  DdrCrDataControl0.Data            = MrcReadCR (MrcData, CrOffset);
+  DdrCrDataControl0.Bits.ReadRFRd   = ReadRfRd;
+  DdrCrDataControl0.Bits.ReadRFWr   = ReadRfWr;
+  DdrCrDataControl0.Bits.ReadRFRank = Rank;
+  MrcWriteCR (MrcData, CrOffset, DdrCrDataControl0.Data);
+}
+
+/**
+  This procedure is meant to handle basic timing centering, places strobe in the middle of the data eye,
+  for both read and write DQ/DQS using a very robust, linear search algorthim.
+
+  @param[in,out] MrcData     - Include all MRC global data.
+  @param[in]     chBitMaskIn - Channel bit mask.
+  @param[in]     param       - {0:RcvEn, 1:RdT, 2:WrT, 3: WrDqsT, 4:RdV, 5:WrV, 6:WrLevel,
+                                8:WrTBit, 9:RdTBit, 10:RdVBit,
+                                16:RdFan2, 17:WrFan2, 32:RdFan3, 32:WrFan3}
+                                ONLY RdT and WrT are allowed in this function
+  @param[in]     ResetPerBit - Option to Reset PerBit Deskew to middle value before byte training
+  @param[in]     loopcount   - loop count
+
+  @retval MrcStatus -  If succeeded, return mrcSuccess
+**/
+MrcStatus
+DQTimeCentering1D (
+  IN OUT MrcParameters *const MrcData,
+  IN     const U8             chBitMaskIn,
+  IN     const U8             param,
+  IN     const U8             ResetPerBit,
+  IN     const U8             loopcount
+  )
+{
+  const MrcDebug    *Debug;
+  MrcOutput         *Outputs;
+  MrcControllerOut  *ControllerOut;
+  MrcChannelOut     *ChannelOut;
+  S32               *CurrentPS;
+  S32               *CurrentPE;
+  S32               *LargestPS;
+  S32               *LargestPE;
+  U32               *Margin;
+  MrcStatus         Status;
+  BOOL              Pass;
+  U8                Channel;
+  U8                Rank;
+  U8                Byte;
+  U8                Step;
+  U8                MinWidth;
+  U8                chBitMask;
+  U8                DumArr[7];
+  U16               Result;
+  S32               CurrentPassingStart[MAX_CHANNEL][MAX_SDRAM_IN_DIMM];
+  S32               CurrentPassingEnd[MAX_CHANNEL][MAX_SDRAM_IN_DIMM];
+  S32               LargestPassingStart[MAX_CHANNEL][MAX_SDRAM_IN_DIMM];
+  S32               LargestPassingEnd[MAX_CHANNEL][MAX_SDRAM_IN_DIMM];
+  S32               cWidth;
+  S32               lWidth;
+  S32               Center;
+  S32               DqsDelay;
+  U32               Start;
+  U32               End;
+  U32               Offset;
+  MCHBAR_CH0_CR_SC_IO_LATENCY_STRUCT ScIoLatency;
+#ifdef MRC_DEBUG_PRINT
+  U64               BitLaneFailures[MAX_CHANNEL][(MAX_POSSIBLE_TIME * 2) + 1];
+  U8                BitCount;
+  const char       *DelayString;
+#endif
+
+  Debug         = &MrcData->SysIn.Inputs.Debug;
+  Outputs       = &MrcData->SysOut.Outputs;
+  ControllerOut = &Outputs->Controller[0];
+  chBitMask     = chBitMaskIn;
+  Status        = mrcSuccess;
+  Center        = 0;
+  MinWidth      = 8;
+  MrcOemMemorySet (DumArr, 1, sizeof (DumArr));
+
+  if ((param != RdT) && (param != WrT) && (param != RcvEnaX)) {
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_ERROR, "DataTimeCentering1D: Unknown Margin Parameter\n");
+    return mrcWrongInputParameter;
+  }
+
+  Step     = 1;
+  if (param == RcvEnaX) {
+    SetupIOTestBasicVA (MrcData, chBitMask, loopcount - 3, 0, 0, 0, 8);
+    Outputs->DQPat = RdRdTA_All;
+  } else {
+    SetupIOTestBasicVA (MrcData, chBitMask, loopcount, NSOE, 0, 0, 8);
+  }
+
+#ifdef MRC_DEBUG_PRINT
+  DelayString = (param == RcvEnaX) ? RcvEnDelayString : DqsDelayString;
+#endif
+  //
+  // Reset PerBit Deskew to middle value before byte training
+  // Write timing offset for bit[x] of the DQ byte. Linear from 0-15, each step size is tQCLK/64
+  // Read timing offset for bit[x] of the DQ byte. Linear from 0-15, each step size is tQCLK/64
+  //
+  if (ResetPerBit == 1) {
+    //
+    // EnMultiCast, UpdateMrcData
+    //
+    Status = ChangeMargin (
+              MrcData,
+              (param == RdT) ? RdTBit : WrTBit,
+              0x88888888,
+              0,
+              1,
+              0,
+              0,
+              0,
+              0,
+              1,
+              0,
+              MrcRegFileStart
+              );
+  }
+  //
+  // Center all Ranks
+  //
+  for (Rank = 0; Rank < MAX_RANK_IN_CHANNEL; Rank++) {
+
+#ifdef MRC_DEBUG_PRINT
+    if (Outputs->ValidRankMask & (MRC_BIT0 << Rank)) {
+      MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Rank = %d\n", Rank);
+      MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Channel 0                1\nByte\t");
+      MRC_DEBUG_MSG (
+        Debug,
+        MSG_LEVEL_NOTE, (
+        Outputs->SdramCount == MAX_SDRAM_IN_DIMM
+        ) ? "0 1 2 3 4 5 6 7 8 0 1 2 3 4 5 6 7 8 Error Count" : "0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 Error Count"
+        );
+    }
+#endif  // MRC_DEBUG_PRINT
+
+    chBitMask = 0;
+    for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+      chBitMask |= SelectReutRanks (MrcData, Channel, (MRC_BIT0 << Rank), 0);
+      ChannelOut = &ControllerOut->Channel[Channel];
+      if ((MRC_BIT0 << Channel) & chBitMask) {
+        //
+        // Clear out anything left over in DataOffsetTrain
+        // Update rank timing to middle value
+        //
+        for (Byte = 0; (Byte < Outputs->SdramCount) && (param != RcvEnaX); Byte++) {
+          if (param == RdT) {
+            //
+            // Read Dq/Dqs
+            //
+            ChannelOut->RxDqsP[Rank][Byte] = 32;
+            ChannelOut->RxDqsN[Rank][Byte] = 32;
+            UpdateRxT (MrcData, Channel, Rank, Byte, 0xFF, 0);
+          } else if (param == WrT) {
+            //
+            // Write Dq/Dqs
+            //
+            ChannelOut->TxDq[Rank][Byte] = ChannelOut->TxDqs[Rank][Byte] + 32;
+            UpdateTxT (MrcData, Channel, Rank, Byte, 0xFF, 0);
+          }
+        }
+        //
+        // Clear any old state in DataTrain Offset
+        //
+        MrcOemMemorySetDword (&ChannelOut->DataOffsetTrain[0], 0, Outputs->SdramCount);
+
+        //
+        // Setup REUT Error Counters to count errors per channel
+        //
+        Offset = MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_0_REG +
+          ((MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_0_REG - MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_0_REG) * Channel);
+        MrcWriteCR (MrcData, Offset, 0);
+      }
+    }
+    //
+    // Continue if not valid rank on any channel
+    //
+    if (chBitMask == 0) {
+      continue; // This rank does not exist on any of the channels
+    }
+    //
+    // Sweep through values
+    //
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\n%s", DelayString);
+    for (DqsDelay = -MAX_POSSIBLE_TIME; DqsDelay <= MAX_POSSIBLE_TIME; DqsDelay += Step) {
+      //
+      // Program DQS Delays
+      //
+      if (param == RcvEnaX){
+        for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+          if ((MRC_BIT0 << Channel) & chBitMask) {
+            for (Byte = 0; Byte < Outputs->SdramCount; Byte++) {
+              Status = ChangeMargin (MrcData, param, DqsDelay, 0, 0, Channel, Rank, Byte, 0, 0, 0, MrcRegFileStart);
+            }
+          }
+        }
+      } else {
+        Status = ChangeMargin (MrcData, param, DqsDelay, 0, 1, 0, 0, 0, 0, 0, 0, MrcRegFileStart);
+      }
+
+      //
+      // Clear Errors and Run Test
+      //
+      RunIOTest (MrcData, chBitMask, Outputs->DQPat, DumArr, 1, 0);
+
+      MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\n% 5d  \t", DqsDelay);
+
+      //
+      // Update results for all Channel/bytes
+      //
+      for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+        if (!(chBitMask & (MRC_BIT0 << Channel))) {
+          MRC_DEBUG_MSG (
+            Debug,
+            MSG_LEVEL_NOTE,
+            (Channel != 0) ? "" : ((Outputs->SdramCount == MAX_SDRAM_IN_DIMM) ? "                  " : "                ")
+            );
+          continue;
+        }
+
+        //
+        // Read out per byte error results and update limit
+        //
+        Offset = 4 + MCHBAR_CH0_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_REG +
+          (
+            (
+              MCHBAR_CH1_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_REG -
+              MCHBAR_CH0_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_REG
+            ) * Channel
+          );
+        Result = (U16) MrcReadCR (MrcData, Offset);
+
+#ifdef MRC_DEBUG_PRINT
+        Offset = MCHBAR_CH0_CR_REUT_CH_ERR_DATA_STATUS_REG +
+          ((MCHBAR_CH1_CR_REUT_CH_ERR_DATA_STATUS_REG - MCHBAR_CH0_CR_REUT_CH_ERR_DATA_STATUS_REG) * Channel);
+
+        BitLaneFailures[Channel][DqsDelay + MAX_POSSIBLE_TIME] = MrcReadCR64 (MrcData, Offset);
+#endif
+        for (Byte = 0; Byte < Outputs->SdramCount; Byte++) {
+          //
+          // Check for Byte group error status
+          //
+          Pass = ((Result & (MRC_BIT0 << Byte)) == 0);
+
+          MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, Pass ? ". " : "# ");
+
+          CurrentPS = &CurrentPassingStart[Channel][Byte];
+          CurrentPE = &CurrentPassingEnd[Channel][Byte];
+          LargestPS = &LargestPassingStart[Channel][Byte];
+          LargestPE = &LargestPassingEnd[Channel][Byte];
+          if (DqsDelay == -31) {
+            if (Pass) {
+              //
+              // No error on this Byte group
+              //
+              *CurrentPS = *CurrentPE = *LargestPS = *LargestPE = DqsDelay;
+            } else {
+              //
+              // Selected Byte group has accumulated an error during loop back pattern
+              //
+              *CurrentPS = *CurrentPE = *LargestPS = *LargestPE = -33;
+            }
+          } else {
+            if (Pass) {
+              //
+              // No error on this Byte group
+              //
+              if (*CurrentPE != (DqsDelay - Step)) {
+                *CurrentPS = DqsDelay;
+              }
+              *CurrentPE = DqsDelay;
+
+              //
+              // Update Largest variables
+              //
+              cWidth = *CurrentPE - *CurrentPS;
+              lWidth = *LargestPE - *LargestPS;
+              if (cWidth > lWidth) {
+                *LargestPS = *CurrentPS;
+                *LargestPE = *CurrentPE;
+              }
+            }
+          }
+        } // for Byte
+      } // for Channel
+#ifdef MRC_DEBUG_PRINT
+      for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+        if (chBitMask & (MRC_BIT0 << Channel)) {
+          Offset = MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_0_REG +
+            ((MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_0_REG - MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_0_REG) * Channel);
+          MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, " 0x%x\t", MrcReadCR (MrcData, Offset));
+        }
+      }
+#endif  // MRC_DEBUG_PRINT
+    } // for DqsDelay
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_ERROR, "\n");  // End last line of Byte table.
+
+#ifdef MRC_DEBUG_PRINT
+    //
+    // Print out the bit lane failure information
+    //
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Bit Lane Information\n");
+    for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+      if (MrcChannelExist (Outputs, Channel)) {
+        MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Channel %d\nBitLane ", Channel);
+        for (BitCount = 0; BitCount < 7; BitCount++) {
+          MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%u         ", BitCount);
+        }
+
+        MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\n        ");  // End tens number and align ones number
+        for (BitCount = 0; BitCount < 64; BitCount++) {
+          MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%u", BitCount % 10);
+        }
+
+        MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\n%s", DelayString);
+
+        for (DqsDelay = -MAX_POSSIBLE_TIME; DqsDelay <= MAX_POSSIBLE_TIME; DqsDelay += Step) {
+          MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\n% 5d\t", DqsDelay); // Begin with a new line and print the DqsDelay value
+          for (BitCount = 0; BitCount < 64; BitCount++) {
+            MRC_DEBUG_MSG (
+              Debug,
+              MSG_LEVEL_NOTE,
+              (BitLaneFailures[Channel][DqsDelay + MAX_POSSIBLE_TIME] & MrcOemMemoryLeftShiftU64 (1, BitCount)) ? "#" : "."
+              );
+          }
+        }
+
+        MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\n"); // Gap after Channel
+      }
+    }
+#endif
+
+    //
+    // Clean Up for next Rank
+    //
+    Status = ChangeMargin (MrcData, param, 0, 0, 1, 0, 0, 0, 0, 0, 0, MrcRegFileCurrent);
+
+    for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+      if (chBitMask & (MRC_BIT0 << Channel)) {
+        ChannelOut = &ControllerOut->Channel[Channel];
+
+        MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "C%d.R%d:  Left\tRight\tWidth\tCenter\n", Channel, Rank);
+
+        for (Byte = 0; Byte < Outputs->SdramCount; Byte++) {
+          LargestPS = &LargestPassingStart[Channel][Byte];
+          LargestPE = &LargestPassingEnd[Channel][Byte];
+          lWidth    = *LargestPE - *LargestPS;
+          if (lWidth < MinWidth) {
+            MRC_DEBUG_MSG (
+              Debug,
+              MSG_LEVEL_ERROR,
+              "ERROR!! DataTimeCentering1D Eye Too Small Channel: %u, Rank: %u, Byte: %u\n",
+              Channel,
+              Rank,
+              Byte
+              );
+            Status = mrcDataTimeCentering1DErr;
+          } else {
+            Center = *LargestPS + (lWidth / 2);
+          }
+
+          MRC_DEBUG_MSG (
+            Debug,
+            MSG_LEVEL_NOTE,
+            "  B%d:   %d\t%d\t%d\t%d\n",
+            Byte,
+            *LargestPS,
+            *LargestPE,
+            lWidth,
+            Center
+            );
+
+          Start = ABS (10 **LargestPS);
+          End   = ABS (10 **LargestPE);
+          if (param == RdT) {
+            //
+            // read Dq./Dqs
+            //
+            Margin                          = &Outputs->MarginResult[LastRxT][Rank][Channel][Byte][0];
+            *Margin                         = Start;
+            Margin[1]                       = End;
+            ChannelOut->RxDqsP[Rank][Byte]  = (U8) ((S32) ChannelOut->RxDqsP[Rank][Byte] + Center);
+            ChannelOut->RxDqsN[Rank][Byte]  = (U8) ((S32) ChannelOut->RxDqsN[Rank][Byte] + Center);
+            UpdateRxT (MrcData, Channel, Rank, Byte, 0xFF, 0);
+          } else if (param == WrT){
+            //
+            // Write Dq/Dqs
+            //
+            Margin                        = &Outputs->MarginResult[LastTxT][Rank][Channel][Byte][0];
+            *Margin                       = Start;
+            Margin[1]                     = End;
+            ChannelOut->TxDq[Rank][Byte]  = (U16) ((S32) ChannelOut->TxDq[Rank][Byte] + Center);
+            UpdateTxT (MrcData, Channel, Rank, Byte, 0xFF, 0);
+          } else if (param == RcvEnaX){
+            //
+            // Receive Enable
+            //
+            Margin                          = &Outputs->MarginResult[LastRcvEna][Rank][Channel][Byte][0];
+            *Margin                         = Start;
+            Margin[1]                       = End;
+            ChannelOut->RcvEn[Rank][Byte]   = (ChannelOut->RcvEn[Rank][Byte] + (U16) (2 * Center));
+            UpdateRxT (MrcData, Channel, Rank, Byte, 0xFF, 0);
+          }
+        }
+        if (param == RcvEnaX){
+          //
+          // clean up
+          //
+          Offset = MCHBAR_CH0_CR_SC_IO_LATENCY_REG +
+            ((MCHBAR_CH1_CR_SC_IO_LATENCY_REG - MCHBAR_CH0_CR_SC_IO_LATENCY_REG) * Channel);
+          ScIoLatency.Data = MrcReadCR (MrcData, Offset);
+          ScIoLatency.Bits.RT_IOCOMP = MCHBAR_CH0_CR_SC_IO_LATENCY_RT_IOCOMP_MAX & ChannelOut->RTIoComp;
+          MrcWriteCR (MrcData, Offset, ScIoLatency.Data);
+        }
+      }
+    }
+  }
+
+  if (param == RcvEnaX) {
+    IoReset (MrcData);
+  }
+
+  return Status;
+}
+
+/**
+  This procedure is meant to handle much more complex centering that will use a 2D algorithm to optimize asymetical
+  eyes for both timing and voltage margin.
+
+  @param[in,out] MrcData         - Include all MRC global data.
+  @param[in,out] MarginResult    - Margin data from centering
+  @param[in]     ChBitMaskIn     - Channel bit mask.
+  @param[in]     param           - {0:RcvEn, 1:RdT, 2:WrT, 3: WrDqsT, 4:RdV, 5:WrV, 6:WrLevel,
+                                    8:WrTBit, 9:RdTBit, 10:RdVBit,
+                                    16:RdFan2, 17:WrFan2, 32:RdFan3, 32:WrFan3}
+                                    ONLY RdT and WrT are allowed in this function
+  @param[in]     EnPerBit        - Option to enable per bit margining
+  @param[in]     EnRxDutyCycleIn - Phase to center.
+  @param[in]     ResetPerBit     - Option to Reset PerBit Deskew to middle value before byte training
+  @param[in]     LoopCount       - loop count
+  @param[in]     En2D            - Option to only run center at nominal Vref point
+
+  @retval MrcStatus -  If succeeded, return mrcSuccess
+**/
+MrcStatus
+DataTimeCentering2D (
+  IN OUT MrcParameters *const MrcData,
+  IN OUT U32                  MarginResult[MAX_RESULT_TYPE][MAX_RANK_IN_CHANNEL][MAX_CHANNEL][MAX_SDRAM_IN_DIMM][MAX_EDGES],
+  IN     const U8             ChBitMaskIn,
+  IN     const U8             Param,
+  IN     const U8             EnPerBit,
+  IN     const U8             EnRxDutyCycleIn,
+  IN     const U8             ResetPerBit,
+  IN     const U8             LoopCount,
+  IN     const U8             En2D
+  )
+{
+  const U32         EHWeights[]       = {6, 2, 1, 0, 2, 1, 0};
+  const U32         EWWeights[]       = {0, 1, 2, 3, 1, 2, 3};
+  const S32         VrefPointsConst[] = {0, -6, -12, -18, 6, 12, 18};
+  const MrcDebug    *Debug;
+  const MrcInput    *Inputs;
+  MrcOutput         *Outputs;
+  MrcControllerOut  *ControllerOut;
+  MrcChannelOut     *ChannelOut;
+  U8                *RxDqPbCenter;
+  U8                *TxDqPbCenter;
+  U16               centerTiming;
+  U32               *Margin;
+  U32               *Eye;
+  S32               *CenterBit;
+  S32               *CSum;
+  MrcStatus         Status;
+  U8                ResultType;
+  U8                Channel;
+  U8                Rank;
+  U8                Byte;
+  U8                Bit;
+  U8                ParamV;
+  U8                ParamB;
+  U8                MaxVScale;
+  U8                EnPerBitEH;
+  U8                Strobe;
+  U8                Strobes;
+  U8                Vref;
+  U8                SaveLC;
+  U8                LCloop;
+  U8                i;
+  U8                SkipWait;
+  U8                ChBitMask;
+  U8                EnRxDutyCycle;
+  U8                Edge;
+  U8                BMap[9];
+  U8                LoopEnd;
+  U16               Mode;
+  U32               MarginBit[MAX_CHANNEL][MAX_SDRAM_IN_DIMM][MAX_BITS][MAX_EDGES];
+  S32               Center;
+  U32               Weight;
+  S32               VrefPoints[sizeof (VrefPointsConst) / sizeof (VrefPointsConst[0])];
+  U32               SumEH;
+  U32               SumEW;
+  U32               BERStats[4];
+  U32               VrefScale[MAX_CHANNEL][MAX_SDRAM_IN_DIMM];
+  U32               EH[MAX_CHANNEL][MAX_SDRAM_IN_DIMM];
+  U32               EW[MAX_CHANNEL][MAX_SDRAM_IN_DIMM];
+  U32               EyeShape[7][MAX_CHANNEL][MAX_SDRAM_IN_DIMM][MAX_EDGES]; // Store all eye edges for Per Bit
+  U32               StrobeMargin[7][MAX_CHANNEL][MAX_SDRAM_IN_DIMM][2][MAX_EDGES];//Save Edges per Strobe to pass Min (Stobe1, Strobe2)
+  S32               CenterSum[MAX_CHANNEL][MAX_SDRAM_IN_DIMM];
+  S32               DivBy;
+  S8                DivBySign;
+  S32               Value0;
+  U32               Offset;
+  S32               CenterSumBit[MAX_CHANNEL][MAX_SDRAM_IN_DIMM][MAX_BITS];
+  S32               Calc;
+  MCHBAR_CH0_CR_REUT_CH_ERR_CTL_STRUCT  ReutChErrCtl;
+  DDRDATA0CH0_CR_RXPERBITRANK0_STRUCT   CrPerBitRank;
+
+  Inputs = &MrcData->SysIn.Inputs;
+  Debug  = &Inputs->Debug;
+
+  //
+  // 2D Margin Types (Voltage, Time)
+  // RdFan2:  Margins both RdV and RdT at { (off, -2/3*off),  (off, 2/3*off) }
+  // WrFan2:  Margins both WrV and WrT at { (off, -2/3*off),  (off, 2/3*off) }
+  // RdFan3:  Margins both RdV and RdT at { (off, -2/3*off),  (5/4*off, 0),  (off, 2/3*off)  }
+  // WrFan3:  Margins both WrV and WrT at { (off, -2/3*off),  (5/4*off, 0),  (off, 2/3*off)  }
+  //
+  if ((Param != RdT) && (Param != WrT)) {
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_ERROR, "DataTimeCentering2D: Incorrect Margin Parameter %d\n", Param);
+    return mrcWrongInputParameter;
+  }
+
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Parameter = %d (%sT)\n", Param, (Param == RdT) ? "Rd" : "Wr");
+  Outputs       = &MrcData->SysOut.Outputs;
+  ControllerOut = &Outputs->Controller[0];
+  ChBitMask     = ChBitMaskIn;
+  EnRxDutyCycle = EnRxDutyCycleIn;
+  Status        = mrcSuccess;
+  MaxVScale     = 24;
+  Strobes       = 2;
+  Center        = 0;
+  Value0        = 0;
+  MrcOemMemorySet ((U8 *) BERStats, 0, sizeof (BERStats));
+  for (i = 0; i < (sizeof (BMap) / sizeof (BMap[0])); i++) {
+    BMap[i] = i;
+  }
+
+  ResultType = GetMarginResultType (Param);
+
+  EnPerBitEH = 1; // Repeat EH Measurement after byte training, before bit training
+  //
+  // SOE = 10b ( Stop on All Byte Groups Error )
+  //
+  SetupIOTestBasicVA (MrcData, ChBitMask, LoopCount - 1, NSOE, 0, 0, 8);
+  Outputs->DQPat = RdRdTA;
+  //
+  // Duty cycle should be ONLY for Rx
+  //
+  if (Param != RdT) {
+    EnRxDutyCycle = 0;
+  }
+
+  Strobes = 1 + EnRxDutyCycle;
+
+  //
+  // Option to only run center at nominal Vref point
+  //
+  if (En2D == 0) {
+    MrcOemMemorySet ((U8 *) &VrefPoints[0], 0, sizeof (VrefPoints));
+  } else {
+    MrcOemMemoryCpy ((U8 *) &VrefPoints[0], (U8 *) &VrefPointsConst[0], sizeof (VrefPoints));
+  }
+  //
+  // Calculate SumEH / SumEW for use in weighting equations
+  //
+  SumEH = SumEW = 0;
+  for (Vref = 0; Vref < sizeof (VrefPoints) / sizeof (VrefPoints[0]); Vref++) {
+    SumEH += EHWeights[Vref];
+    SumEW += EWWeights[Vref];
+
+    //
+    // Loop once at nominal Vref point
+    //
+    if (En2D == 0) {
+      Vref = 6;
+    }
+  }
+
+  if (Param == RdT) {
+    ParamV = RdV;
+    ParamB = RdTBit;
+  } else {
+    ParamV = WrV;
+    ParamB = WrTBit;
+  }
+  //
+  // Optimize timing per rank
+  //
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Optimization is per rank\n");
+  for (Rank = 0; Rank < MAX_RANK_IN_CHANNEL; Rank++) {
+    ChBitMask = 0;
+    //
+    // Select rank for REUT test
+    //
+    for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+      if ((MRC_BIT0 << Channel) & ChBitMaskIn) {
+        ChBitMask |= SelectReutRanks (MrcData, Channel, (MRC_BIT0 << Rank), 0);
+        if ((MRC_BIT0 << Channel) & ChBitMask) {
+          ChannelOut = &ControllerOut->Channel[Channel];
+          //
+          // Clear any old state in DataTrain Offset
+          //
+          MrcOemMemorySetDword (&ChannelOut->DataOffsetTrain[0], 0, Outputs->SdramCount);
+        }
+      }
+    }
+    //
+    // Continue if not valid rank on any channel
+    //
+    if (ChBitMask == 0) {
+      continue;
+      //
+      // This rank does not exist on any of the channels
+      //
+    }
+    //
+    // Reset PerBit Deskew to middle value before byte training
+    // Write timing offset for bit[x] of the DQ byte. Linear from 0-15, each step size is tQCLK/64
+    // Read timing offset for bit[x] of the DQ byte. Linear from 0-15, each step size is tQCLK/64
+    //
+    if (ResetPerBit == 1) {
+      Status = ChangeMargin (MrcData, ParamB, 0x88888888, 0, 1, 0, Rank, 0, 0, 1, 0, MrcRegFileRank);
+    }
+
+    //####################################################
+    //######   Get EH to scale vref sample point by  #####
+    //####################################################
+    //
+    // Pass the host last edges by reference
+    // Get EH/VrefScale for the use in timing centering
+    //
+    if (En2D > 0) {
+      // MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\nCalling DQTimeCenterEH\n");
+      Status = DQTimeCenterEH (
+                MrcData,
+                ChBitMask,
+                Rank,
+                ParamV,
+                MaxVScale,
+                BMap,
+                EH,
+                VrefScale,
+                BERStats
+                );
+      if (Status != mrcSuccess) {
+        MRC_DEBUG_MSG (Debug, MSG_LEVEL_WARNING, "\nDQTimeCenterEH FAILED - Using VrefScale = %d\n", MaxVScale);
+        for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+          MrcOemMemorySetDword (&VrefScale[Channel][0], MaxVScale, Outputs->SdramCount);
+        }
+      }
+    } else {
+      for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+        MrcOemMemorySetDword (&EH[Channel][0], 1, Outputs->SdramCount);
+        MrcOemMemorySetDword (&VrefScale[Channel][0], 1, Outputs->SdramCount);
+      }
+    }
+
+    Status = GetMarginByte (MrcData, MarginResult, Param, Rank, (MRC_BIT0 << Rank));
+
+#if 0
+#ifdef MRC_DEBUG_PRINT
+    //
+    // Read the margins
+    //
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\nLstSavd Margins ");
+    for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+      if (!((1 << Channel) & ChBitMask)) {
+        continue;
+      }
+
+      for (Byte = 0; Byte < Outputs->SdramCount; Byte++) {
+        MRC_DEBUG_MSG (
+          Debug,
+          MSG_LEVEL_NOTE,
+          "%d %d ",
+          MarginResult[ResultType][Rank][Channel][Byte][0],
+          MarginResult[ResultType][Rank][Channel][Byte][1]
+          );
+      }
+    }
+#endif // MRC_DEBUG_PRINT
+#endif
+
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "### Rank = %d ###\n", Rank);
+    for (Strobe = 0; Strobe < Strobes; Strobe++) {
+      MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\n\n### Strobe = %d ###\n", Strobe);
+      if (Outputs->ValidRankMask & (MRC_BIT0 << Rank)) {
+        MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\nChannel\t\t0\t\t\t\t\t\t\t\t\t 1\nByte\t\t");
+        MRC_DEBUG_MSG (
+          Debug,
+          MSG_LEVEL_NOTE, (
+          Outputs->SdramCount == MAX_SDRAM_IN_DIMM
+          ) ? "0\t1\t2\t3\t4\t\t5\t6\t7\t8\t0\t1\t2\t3\t4\t5\t6\t7\t8\nEdges L/R" :
+          "0\t1\t2\t3\t4\t5\t6\t7\t0\t1\t2\t3\t4\t5\t6\t7\nEdges L/R"
+          );
+      }
+      //####################################################
+      //######   Measure Eye Width at all Vref Points  #####
+      //####################################################
+      //
+      // Program Selective error checking for RX. if strobe = 0 then Check even else Check odd
+      //
+      if (EnRxDutyCycle) {
+        for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+          if (ChBitMask & (MRC_BIT0 << Channel)) {
+            Offset = 2 + MCHBAR_CH0_CR_REUT_CH_ERR_CTL_REG +
+              ((MCHBAR_CH1_CR_REUT_CH_ERR_CTL_REG - MCHBAR_CH0_CR_REUT_CH_ERR_CTL_REG) * Channel);
+            MrcWriteCR8 (MrcData, Offset, (0x55 << Strobe));
+          }
+        }
+      }
+      //
+      // Loop through all the Vref Points to Test
+      //
+      for (Vref = 0; Vref < sizeof (VrefPoints) / sizeof (VrefPoints[0]); Vref++) {
+        //
+        // Setup Vref Voltage for this point
+        //
+        for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+          if (ChBitMask & (MRC_BIT0 << Channel)) {
+            SkipWait = (ChBitMask >> (Channel + 1)); // Skip if there are more channels
+
+            LoopEnd = (U8) ((ParamV == RdV) ? Outputs->SdramCount : 1);
+            for (Byte = 0; Byte < LoopEnd; Byte++) {
+              Value0 = (S32) (VrefPoints[Vref] * VrefScale[Channel][Byte]) / MaxVScale;
+              Status = ChangeMargin (
+                        MrcData,
+                        ParamV,
+                        Value0,
+                        0,
+                        0,
+                        Channel,
+                        Rank,
+                        Byte,
+                        0,
+                        0,
+                        SkipWait,
+                        MrcRegFileRank
+                        );
+            }
+          }
+        }
+
+        MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\nVref = %d:\t", Value0);
+
+        //
+        // Run Margin Test
+        //
+        Mode = 0;
+        Status = MrcGetBERMarginByte (
+                  MrcData,
+                  MarginResult,
+                  ChBitMask,
+                  Rank,
+                  Rank,
+                  Param,
+                  Mode,
+                  BMap,
+                  1,
+                  31,
+                  0,
+                  BERStats
+                  );
+        //
+        // Store Results; Setup Vref Voltage for this point
+        //
+        for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+          if ((ChBitMask & (MRC_BIT0 << Channel))) {
+
+            for (Byte = 0; Byte < Outputs->SdramCount; Byte++) {
+              Margin = &MarginResult[ResultType][Rank][Channel][Byte][0];
+              MRC_DEBUG_MSG (
+                Debug,
+                MSG_LEVEL_NOTE,
+                "%d %d ",
+                MarginResult[ResultType][Rank][Channel][Byte][0],
+                MarginResult[ResultType][Rank][Channel][Byte][1]
+                );
+
+              Center = (S32) (Margin[1] -*Margin);
+              if (Vref == 0) {
+                EW[Channel][Byte]         = (Margin[1] +*Margin) / 10;
+                CenterSum[Channel][Byte]  = 0;
+              }
+              //
+              // Calculate weight for this point
+              //
+              Weight = EHWeights[Vref] * EH[Channel][Byte] + EWWeights[Vref] * EW[Channel][Byte];
+              CenterSum[Channel][Byte] += Weight * Center;
+              //
+              // Store Edges for Per Bit deskew
+              //
+              Eye = &EyeShape[Vref][Channel][Byte][0];
+              for (Edge = 0; Edge < MAX_EDGES; Edge++) {
+                Eye[Edge] = Margin[Edge];
+              }
+              //
+              // RunTime Improvement.  Set margin back to Vref = 0 point when the sign  of the VrefPoint changes
+              //
+              if ((VrefPoints[Vref] < 0) &&
+                  (Vref < (sizeof (VrefPoints) / sizeof (VrefPoints[0]) - 1)) &&
+                  (VrefPoints[Vref + 1] > 0)
+                  ) {
+                Eye = &EyeShape[0][Channel][Byte][0];
+                for (Edge = 0; Edge < MAX_EDGES; Edge++) {
+                  Margin[Edge] = Eye[Edge];
+                }
+              }
+            }
+          }
+        }
+        //
+        // Loop once at nominal Vref point
+        //
+        if (En2D == 0) {
+          Vref = sizeof (VrefPoints) / sizeof (VrefPoints[0]);
+        }
+      }
+
+      //####################################################
+      //############    Center Results per Byte  ###########
+      //####################################################
+      MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\n\nWeighted Center\t");
+
+      for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+        if (ChBitMask & (MRC_BIT0 << Channel)) {
+          ChannelOut = &ControllerOut->Channel[Channel];
+
+          //
+          // Calculate and apply CenterPoint.  Round to Nearest Int
+          //
+          for (Byte = 0; Byte < Outputs->SdramCount; Byte++) {
+            DivBy = (SumEH * EH[Channel][Byte] + SumEW * EW[Channel][Byte]);
+            if (DivBy == 0) {
+              MRC_DEBUG_MSG (Debug, MSG_LEVEL_ERROR, "DataTimeCentering2D: Divide by zero\n");
+              return mrcFail;
+            }
+
+            CSum      = &CenterSum[Channel][Byte];
+            DivBySign = (*CSum < 0) ? (-1) : 1;
+
+            *CSum     = (*CSum + 10 * (DivBySign * DivBy)) / (20 * DivBy);
+            MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%d\t", *CSum);
+
+            //
+            // Apply new centerpoint
+            //
+            if (Param == RdT) {
+              if (Strobe == 0) {
+                ChannelOut->RxDqsP[Rank][Byte] = (U8) ((S32) ChannelOut->RxDqsP[Rank][Byte] +*CSum);
+              }
+
+              if ((!EnRxDutyCycle) || (Strobe == 1)) {
+                ChannelOut->RxDqsN[Rank][Byte] = (U8) ((S32) ChannelOut->RxDqsN[Rank][Byte] +*CSum);
+                UpdateRxT (MrcData, Channel, Rank, Byte, 0xFF, 0);
+              }
+            } else {
+              ChannelOut->TxDq[Rank][Byte] = (U16) ((S32) ChannelOut->TxDq[Rank][Byte] +*CSum);
+              UpdateTxT (MrcData, Channel, Rank, Byte, 0xFF, 0);
+            }
+            //
+            // Update the Eye Edges
+            //
+            for (Vref = 0; Vref < sizeof (VrefPoints) / sizeof (VrefPoints[0]); Vref++) {
+              Calc  = 10 **CSum;
+              Eye   = &EyeShape[Vref][Channel][Byte][0];
+              *Eye += Calc;
+              Eye[1] -= Calc;
+
+              //
+              // Save Per Strobe Edges
+              //
+              for (Edge = 0; Edge < MAX_EDGES; Edge++) {
+                StrobeMargin[Vref][Channel][Byte][Strobe][Edge] = EyeShape[Vref][Channel][Byte][Edge];
+              }
+              //
+              // Loop once at nominal Vref point
+              //
+              if (En2D == 0) {
+                Vref = sizeof (VrefPoints) / sizeof (VrefPoints[0]);
+              }
+            }
+            //
+            // Update MrcData for future tests (MarginResult points back to MrcData)
+            // EyeShape for Vref 0 is assumed to have the best shape for future tests.
+            //
+            for (Edge = 0; Edge < MAX_EDGES; Edge++) {
+              MarginResult[ResultType][Rank][Channel][Byte][Edge] = EyeShape[0][Channel][Byte][Edge];
+            }
+          }
+          //
+          // Clean up after test
+          //
+          MrcOemMemorySetDword (&ChannelOut->DataOffsetTrain[0], 0, Outputs->SdramCount);
+        }
+      }
+
+      centerTiming = 0;
+#ifdef MRC_DEBUG_PRINT
+      MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\nFinal Center\t");
+      for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+        if (ChBitMask & (MRC_BIT0 << Channel)) {
+          ChannelOut = &ControllerOut->Channel[Channel];
+
+          //
+          // Calculate final center point relative to "zero" as in the 1D case
+          //
+          for (Byte = 0; Byte < Outputs->SdramCount; Byte++) {
+            if (Param == RdT) {
+              if (Strobe == 0) {
+                centerTiming = (U8) (ChannelOut->RxDqsP[Rank][Byte] - 32);
+              }
+
+              if ((!EnRxDutyCycle) || (Strobe == 1)) {
+                centerTiming = (U8) (ChannelOut->RxDqsN[Rank][Byte] - 32);
+              }
+            } else {
+              centerTiming = ChannelOut->TxDq[Rank][Byte] - (ChannelOut->TxDqs[Rank][Byte] + 32);
+            }
+
+            MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%d\t", (S8) centerTiming);
+          }
+        }
+      }
+#endif // MRC_DEBUG_PRINT
+    } // End of Byte Centering
+
+    //######################################################
+    //############     Measure Eye Width Per BIT  ##########
+    //######################################################
+
+    if (EnPerBit) {
+#if 0
+#ifdef MRC_DEBUG_PRINT
+      MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\n\nEdges we pass on to GetMarginBit are\n");
+      for (Vref = 0; Vref < sizeof (VrefPoints) / sizeof (VrefPoints[0]); Vref++) {
+        MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\t\t");
+        //
+        // Setup Vref Voltage for this point
+        //
+        for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+          if (ChBitMask & (MRC_BIT0 << Channel)) {
+            for (Byte = 0; Byte < Outputs->SdramCount; Byte++) {
+              for (Edge = 0; Edge < MAX_EDGES; Edge++) {
+                MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%d ", EyeShape[Vref][Channel][Byte][Edge]);
+              }
+            }
+          }
+        }
+
+        MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\n");
+        if (En2D == 0) {
+          Vref = sizeof (VrefPoints) / sizeof (VrefPoints[0]);
+        }
+      }
+#endif // MRC_DEBUG_PRINT
+#endif
+
+      MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\n\n### Measure Eye Width Per BIT\n");
+      //
+      // Recalculate the EH after the Byte Centering
+      //
+      if (EnPerBitEH && (En2D > 0)) {
+        Status = DQTimeCenterEH (
+                  MrcData,
+                  ChBitMask,
+                  Rank,
+                  ParamV,
+                  MaxVScale,
+                  BMap,
+                  EH,
+                  VrefScale,
+                  BERStats
+                  );
+        if (Status != mrcSuccess) {
+          MRC_DEBUG_MSG (Debug, MSG_LEVEL_WARNING, "\nDQTimeCenterEH FAILED - Using VrefScale = %d\n", MaxVScale);
+          for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+            MrcOemMemorySetDword (&VrefScale[Channel][0], MaxVScale, Outputs->SdramCount);
+          }
+        }
+      }
+      //
+      // No stop on error or selective error cheking
+      // Stop on all lane fail
+      //
+      for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+        if (ChBitMask & (MRC_BIT0 << Channel)) {
+#ifdef MRC_DEBUG_PRINT
+          MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Channel      %d", Channel);
+          if (Channel == 0) {
+            for (Byte = 0; Byte < Outputs->SdramCount; Byte++) {
+              MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\t\t\t\t\t\t");
+            }
+          }
+#endif // MRC_DEBUG_PRINT
+          //
+          // SOE = 11b ( Stop on All Lanes Error )
+          //
+          Offset = MCHBAR_CH0_CR_REUT_CH_ERR_CTL_REG +
+            ((MCHBAR_CH1_CR_REUT_CH_ERR_CTL_REG - MCHBAR_CH0_CR_REUT_CH_ERR_CTL_REG) * Channel);
+          ReutChErrCtl.Data                                   = 0;
+          ReutChErrCtl.Bits.Selective_Error_Enable_Cacheline  = MCHBAR_CH0_CR_REUT_CH_ERR_CTL_Selective_Error_Enable_Cacheline_MAX;
+          ReutChErrCtl.Bits.Selective_Error_Enable_Chunk      = MCHBAR_CH0_CR_REUT_CH_ERR_CTL_Selective_Error_Enable_Chunk_MAX;
+          ReutChErrCtl.Bits.Stop_On_Error_Control             = ALSOE;
+          ReutChErrCtl.Bits.Stop_on_Nth_Error                 = 1;
+          MrcWriteCR (MrcData, Offset, ReutChErrCtl.Data);
+        }
+      }
+
+#ifdef MRC_DEBUG_PRINT
+      MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\n");
+      for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+        if (ChBitMask & (MRC_BIT0 << Channel)) {
+          for (Byte = 0; Byte < Outputs->SdramCount; Byte++) {
+            MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "             Byte % 24d ", Byte);
+          }
+        }
+      }
+
+      MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\n");
+#endif // MRC_DEBUG_PRINT
+      //
+      // Loop through all the Vref Points to Test
+      //
+      SaveLC = Outputs->DQPatLC;
+      for (Vref = 0; Vref < sizeof (VrefPoints) / sizeof (VrefPoints[0]); Vref++) {
+        //
+        // Setup Vref Voltage for this point
+        //
+        for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+          if ((ChBitMask & (MRC_BIT0 << Channel))) {
+
+            SkipWait = (ChBitMask >> (Channel + 1)); // Skip if there are more channels
+            //
+            // Change Vref margin
+            //
+            LoopEnd = (U8) ((ParamV == RdV) ? Outputs->SdramCount : 1);
+            for (Byte = 0; Byte < LoopEnd; Byte++) {
+              Value0 = (S32) (VrefPoints[Vref] * VrefScale[Channel][Byte]) / MaxVScale;
+              Status = ChangeMargin (
+                        MrcData,
+                        ParamV,
+                        Value0,
+                        0,
+                        0,
+                        Channel,
+                        Rank,
+                        Byte,
+                        0,
+                        0,
+                        SkipWait,
+                        MrcRegFileRank
+                        );
+            }
+          }
+
+          MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Channel %d Vref = %d\t", Channel, Value0);
+          MrcOemMemorySetDword (&MarginBit[Channel][0][0][0], 8, MAX_SDRAM_IN_DIMM * MAX_BITS * MAX_EDGES);
+        }
+        //
+        // Run Margin Test; Loop through 2 times. Once at low loop count and Once at high loopcount. Improves runtime
+        // @todo: Need loop count of 2 when not using BASICVA
+        //
+        for (LCloop = 0; LCloop < 1; LCloop++) {
+          Outputs->DQPatLC  = (LCloop == 0) ? 1 : SaveLC;
+
+          Mode = 0;
+          Status = MrcGetMarginBit (MrcData, ChBitMask, Rank, MarginBit, EyeShape[Vref], ParamB, Mode, 15);
+        }
+        //
+        // MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\nCSum      ");
+        // Store Results
+        // Setup Vref Voltage for this point
+        //
+        for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+          if (ChBitMask & (MRC_BIT0 << Channel)) {
+
+            for (Byte = 0; Byte < Outputs->SdramCount; Byte++) {
+              //
+              // Calculate weight for this point
+              //
+              Weight = EHWeights[Vref] * EH[Channel][Byte] + EWWeights[Vref] * EW[Channel][Byte];
+              for (Bit = 0; Bit < MAX_BITS; Bit++) {
+                Margin  = &MarginBit[Channel][Byte][Bit][0];
+                CSum    = &CenterSumBit[Channel][Byte][Bit];
+
+                Center = ((Margin[1] - 8) - (8 - *Margin));
+                if (Vref == 0) {
+                  *CSum = 0;
+                }
+
+                *CSum += Weight * Center;
+                //MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "% 4d", *CSum);
+              }
+              //MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, " Weight %d  ", Weight);
+            }
+          }
+        }
+        //
+        // Loop once at nominal Vref point
+        //
+        if (En2D == 0) {
+          Vref = sizeof (VrefPoints) / sizeof (VrefPoints[0]);
+        }
+      }
+
+      //######################################################
+      //#############     Center Result Per BIT  #############
+      //######################################################
+      MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\nWtd Ctr\t  ");
+      for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+        if (ChBitMask & (MRC_BIT0 << Channel)) {
+          ChannelOut = &ControllerOut->Channel[Channel];
+
+          //
+          // Cleanup after test - go back to the per byte setup
+          //
+          ReutChErrCtl.Data                                  = 0;
+          ReutChErrCtl.Bits.Stop_on_Nth_Error                = 1;
+          ReutChErrCtl.Bits.Stop_On_Error_Control            = NSOE;
+          ReutChErrCtl.Bits.Selective_Error_Enable_Chunk     = MCHBAR_CH0_CR_REUT_CH_ERR_CTL_Selective_Error_Enable_Chunk_MAX;
+          ReutChErrCtl.Bits.Selective_Error_Enable_Cacheline = MCHBAR_CH0_CR_REUT_CH_ERR_CTL_Selective_Error_Enable_Cacheline_MAX;
+          Offset = MCHBAR_CH0_CR_REUT_CH_ERR_CTL_REG +
+            ((MCHBAR_CH1_CR_REUT_CH_ERR_CTL_REG - MCHBAR_CH0_CR_REUT_CH_ERR_CTL_REG) * Channel);
+          MrcWriteCR (MrcData, Offset, ReutChErrCtl.Data);
+
+          //
+          // Calculate and apply CenterPoint.  Round to Nearest Int
+          //
+          for (Byte = 0; Byte < Outputs->SdramCount; Byte++) {
+            DivBy = (SumEH * EH[Channel][Byte] + SumEW * EW[Channel][Byte]);
+
+            //
+            // Make sure DivBy is never 0
+            //
+            if (DivBy == 0) {
+              DivBy = 1;
+            }
+
+            CrPerBitRank.Data = 0;
+            for (Bit = 0; Bit < MAX_BITS; Bit++) {
+              CenterBit    = &CenterSumBit[Channel][Byte][Bit];
+              RxDqPbCenter = &ChannelOut->RxDqPb[Rank][Byte][Bit].Center;
+              TxDqPbCenter = &ChannelOut->TxDqPb[Rank][Byte][Bit].Center;
+
+              DivBySign  = (*CenterBit < 0) ? (-1) : 1;
+              *CenterBit = (*CenterBit + (DivBySign * DivBy)) / (2 * DivBy);
+
+              //
+              // Centerpoint needs to be added to starting DqPb value
+              //
+              *CenterBit += (Param == RdT) ? (S32) *RxDqPbCenter : (S32) *TxDqPbCenter;
+
+              //
+              // Check for saturation
+              //
+              if (*CenterBit > DDRDATA0CH0_CR_RXPERBITRANK0_Lane0_MAX) {
+                *CenterBit = DDRDATA0CH0_CR_RXPERBITRANK0_Lane0_MAX;
+              } else if (*CenterBit < 0) {
+                *CenterBit = 0;
+              }
+
+              MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "% 4x", *CenterBit);
+
+              //
+              // Update MrcData
+              //
+              if (Param == RdT) {
+                *RxDqPbCenter = (U8) *CenterBit;
+              } else {
+                *TxDqPbCenter = (U8) *CenterBit;
+              }
+
+              CrPerBitRank.Data |= (*CenterBit << (4 * Bit));
+            }
+            //
+            // Apply new centerpoint
+            // ParamB already has the proper per bit parameter based on Param
+            //
+            Status = ChangeMargin (
+                      MrcData,
+                      ParamB,
+                      CrPerBitRank.Data,
+                      0,
+                      0,
+                      Channel,
+                      Rank,
+                      Byte,
+                      0,
+                      0,
+                      0,
+                      MrcRegFileRank
+                      );
+
+            //MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, " DivBy %d   ", DivBy);
+            MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "           ");
+          }
+          //
+          // Clear any old state in DataTrain Offset
+          //
+          MrcOemMemorySetDword (&ChannelOut->DataOffsetTrain[0], 0, Outputs->SdramCount);
+        }
+      }
+      //
+      // No stop on error or selective error cheking
+      // Stop on all lane fail
+      //
+      for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+        if (ChBitMask & (MRC_BIT0 << Channel)) {
+          //
+          // SOE = 11b ( Stop on All Lanes Error )
+          //
+          ReutChErrCtl.Data                                  = 0;
+          ReutChErrCtl.Bits.Stop_on_Nth_Error                = 1;
+          ReutChErrCtl.Bits.Stop_On_Error_Control            = ALSOE;
+          ReutChErrCtl.Bits.Selective_Error_Enable_Chunk     = MCHBAR_CH0_CR_REUT_CH_ERR_CTL_Selective_Error_Enable_Chunk_MAX;
+          ReutChErrCtl.Bits.Selective_Error_Enable_Cacheline = MCHBAR_CH0_CR_REUT_CH_ERR_CTL_Selective_Error_Enable_Cacheline_MAX;
+          Offset = MCHBAR_CH0_CR_REUT_CH_ERR_CTL_REG +
+            ((MCHBAR_CH1_CR_REUT_CH_ERR_CTL_REG - MCHBAR_CH0_CR_REUT_CH_ERR_CTL_REG) * Channel);
+          MrcWriteCR (MrcData, Offset, ReutChErrCtl.Data);
+        }
+      }
+
+#if 0  // This code is for debug purposes ONLY if we want to know the perbyte margins after calling the perbit centering
+#ifdef MRC_DEBUG_PRINT
+      MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\n\nEdges\t");
+      for (Vref = 0; Vref < (sizeof (VrefPoints) / sizeof (VrefPoints[0])); Vref++) {
+        for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+          if (ChBitMask & (MRC_BIT0 << Channel)) {
+            for (Byte = 0; Byte < Outputs->SdramCount; Byte++) {
+              for (Edge = 0; Edge < MAX_EDGES; Edge++) {
+                MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%d ", EyeShape[Vref][Channel][Byte][Edge]);
+              }
+            }
+          }
+        }
+
+        MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\n");
+        if (En2D == 0) {
+          Vref = sizeof (VrefPoints) / sizeof (VrefPoints[0]);
+        }
+      }
+
+      MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\nCalling GetMarginBit with per Byte Timing\nByte\n");
+      for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+        if (ChBitMask & (1 << Channel)) {
+          for (Byte = 0; Byte < Outputs->SdramCount; Byte++) {
+            MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%d\t\t\t\t\t", Byte);
+          }
+        }
+      }
+
+      for (Vref = 0; Vref < (sizeof (VrefPoints) / sizeof (VrefPoints[0])); Vref++) {
+        Mode    = 0;
+        Status  = MrcGetMarginBit (MrcData, ChBitMask, Rank, MarginBit, EyeShape[Vref], Param, Mode, 31);
+        //
+        // Loop once at nominal Vref point
+        //
+        if (En2D == 0) {
+          Vref = sizeof (VrefPoints) / sizeof (VrefPoints[0]);
+        }
+      }
+
+      MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\nPerByte Margins after Bit Centering\nLeft\tRight\tCenter\n");
+      for (Vref = 0; Vref < (sizeof (VrefPoints) / sizeof (VrefPoints[0])); Vref++) {
+        for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+          if (ChBitMask & (MRC_BIT0 << Channel)) {
+            MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Channel %d\n", Channel);
+            for (Byte = 0; Byte < Outputs->SdramCount; Byte++) {
+              MRC_DEBUG_MSG (
+                Debug,
+                MSG_LEVEL_NOTE,
+                "%d\t%d\t%d\n",
+                EyeShape[Vref][Channel][Byte][0],
+                EyeShape[Vref][Channel][Byte][1],
+                (((S32) EyeShape[Vref][Channel][Byte][1] - (S32) EyeShape[Vref][Channel][Byte][0]) / (2 * 10))
+                );
+            }
+          }
+        }
+
+        MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\n");
+        if (En2D == 0) {
+          Vref = sizeof (VrefPoints) / sizeof (VrefPoints[0]);
+        }
+      }
+#endif // MRC_DEBUG_PRINT
+#endif
+
+      for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+        if (ChBitMask & (MRC_BIT0 << Channel)) {
+          //
+          // Cleanup after test
+          //
+          ReutChErrCtl.Data                                  = 0;
+          ReutChErrCtl.Bits.Stop_on_Nth_Error                = 1;
+          ReutChErrCtl.Bits.Stop_On_Error_Control            = NSOE;
+          ReutChErrCtl.Bits.Selective_Error_Enable_Chunk     = MCHBAR_CH0_CR_REUT_CH_ERR_CTL_Selective_Error_Enable_Chunk_MAX;
+          ReutChErrCtl.Bits.Selective_Error_Enable_Cacheline = MCHBAR_CH0_CR_REUT_CH_ERR_CTL_Selective_Error_Enable_Cacheline_MAX;
+          Offset = MCHBAR_CH0_CR_REUT_CH_ERR_CTL_REG +
+            ((MCHBAR_CH1_CR_REUT_CH_ERR_CTL_REG - MCHBAR_CH0_CR_REUT_CH_ERR_CTL_REG) * Channel);
+          MrcWriteCR (MrcData, Offset, ReutChErrCtl.Data);
+        }
+      }
+    }
+
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\n");
+  } //End of Rank
+  //
+  // Clean Up after test
+  //
+  Outputs->EnDumRd  = 0;
+  Status            = ChangeMargin (MrcData, ParamV, 0, 0, 1, 0, 0, 0, 0, 0, 0, MrcRegFileCurrent);
+  return Status;
+}
+
+/**
+  Subfunction of 2D Timing Centering
+  Measures paramV margin across ch/bytes and updates the EH/VrefScale variables
+
+  @param[in]     MrcData   - Include all MRC global data.
+  @param[in]     ChBitMask - Channel Bit mak for which test should be setup for.
+  @param[in]     rank      - Defines rank to used for MrcData
+  @param[in]     ParamV    - Margin parameter
+  @param[in]     MaxVScale - Maximum Voltage Scale to use
+  @param[in]     BMap      - Byte mapping to configure error counter control register
+  @param[in,out] EH        - Structure that stores start, stop and increment details for address
+  @param[in,out] VrefScale - Parameter to be updated
+  @param[in,out] BERStats  - Bit Error Rate Statistics.
+
+  @retval mrcSuccess if successful, otherwise the function returns an error status.
+**/
+MrcStatus
+DQTimeCenterEH (
+  IN     MrcParameters * const MrcData,
+  IN     const U8              ChBitMask,
+  IN     const U8              rank,
+  IN     const U8              ParamV,
+  IN     const U8              MaxVScale,
+  IN     U8 * const            BMap,
+  IN OUT U32                   EH[MAX_CHANNEL][MAX_SDRAM_IN_DIMM],
+  IN OUT U32                   VrefScale[MAX_CHANNEL][MAX_SDRAM_IN_DIMM],
+  IN OUT U32 * const           BERStats
+  )
+{
+  const MrcDebug  *Debug;
+  MrcOutput       *Outputs;
+  U32             *MarginResult;
+  U32             *VrefS;
+  MrcStatus       Status;
+  U8              ResultType;
+  U8              Channel;
+  U8              Byte;
+  U32             MinVrefScale;
+  U16             Mode;
+
+  Debug   = &MrcData->SysIn.Inputs.Debug;
+  Outputs = &MrcData->SysOut.Outputs;
+  //
+  // MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "DQTimeCenterEH:\n");
+  // Run Margin Test
+  //
+  Mode    = 0;
+  Status  = GetMarginByte (MrcData, Outputs->MarginResult, ParamV, rank, (MRC_BIT0 << rank));
+  if (mrcSuccess == Status) {
+    Status = MrcGetBERMarginByte (
+              MrcData,
+              Outputs->MarginResult,
+              ChBitMask,
+              rank,
+              rank,
+              ParamV,
+              Mode,
+              BMap,
+              1,
+              MAX_POSSIBLE_VREF,
+              0,
+              BERStats
+              );
+    if (mrcSuccess == Status) {
+      Status = ScaleMarginByte (MrcData, Outputs->MarginResult, ParamV, rank);
+      if (mrcSuccess == Status) {
+        ResultType = GetMarginResultType (ParamV);
+
+        //
+        // Update VrefScale with results
+        //
+        for (Channel = 0; (Channel < MAX_CHANNEL) && (mrcSuccess == Status); Channel++) {
+          if (ChBitMask & (MRC_BIT0 << Channel)) {
+            //
+            // Calculate EH and VrefScale
+            //
+            MinVrefScale = MaxVScale;
+            for (Byte = 0; Byte < Outputs->SdramCount; Byte++) {
+              MarginResult      = &Outputs->MarginResult[ResultType][rank][Channel][Byte][0];
+              VrefS             = &VrefScale[Channel][Byte];
+              EH[Channel][Byte] = (*MarginResult + *(MarginResult + 1)) / 10;
+              *VrefS            = EH[Channel][Byte] / 2;
+
+              if (*VrefS > MaxVScale) {
+                *VrefS = MaxVScale;
+              }
+
+              if (MinVrefScale > *VrefS) {
+                MinVrefScale = *VrefS;
+              }
+              //
+              // Scale host back to correct values
+              //
+              Status = ScaleMarginByte (MrcData, Outputs->MarginResult, ParamV, rank);
+              if (mrcSuccess != Status) {
+                break;
+              }
+              //
+              // For Tx, use the same Vref limit for all bytes. Store result in byte0
+              //
+              if (ParamV == WrV) {
+                MrcOemMemorySetDword (&VrefScale[Channel][0], MinVrefScale, Outputs->SdramCount);
+              }
+            }
+          }
+        }
+      }
+    }
+  }
+  //
+  // Updates EH and VrefScale
+  //
+  return Status;
+}
+
+/**
+  Update the Vref value
+  if VrefType = 0     Updates Ch0 Vref_Dq
+  if VrefType = 1     Updates Ch1 Vref_Dq
+  if VrefType = 2     Updates Vref_CA
+
+  @param[in,out] MrcData       - Include all MRC global data.
+  @param[in]     VrefType      - Determines the Vref to change
+  @param[in]     UpdateMrcData - Used to decide if Mrc host must be updated
+  @param[in]     Offset        - Vref value
+  @param[in]     SkipWait      - Determines if we will wait for vref to settle after writing to register
+
+  @retval Nothing
+**/
+void
+UpdateVrefWaitTilStable (
+  IN OUT MrcParameters *const MrcData,
+  IN     const U8             VrefType,
+  IN     const U8             UpdateMrcData,
+  IN     S32                  Offset,
+  IN     U8                   SkipWait
+  )
+{
+  const MrcDebug                          *Debug;
+  MrcInput                                *Inputs;
+  MrcOutput                               *Outputs;
+  U32                                     CheckMask;
+  U8                                      OffH;
+  U8                                      Count;
+  DDRDATA7CH1_CR_DDRCRVREFADJUST1_STRUCT  DdrCrVrefAdjust;
+
+  Inputs  = &MrcData->SysIn.Inputs;
+  Debug   = &Inputs->Debug;
+  Outputs = &MrcData->SysOut.Outputs;
+
+  //
+  // Calculate and write the new Vref offset value.
+  //
+  switch (VrefType) {
+    case 0:
+      OffH = (U8) (((DDRDATA7CH1_CR_DDRCRVREFADJUST1_STRUCT *) (&Outputs->DimmVref))->Bits.Ch0VrefCtl);
+      break;
+
+    case 1:
+      OffH = (U8) (((DDRDATA7CH1_CR_DDRCRVREFADJUST1_STRUCT *) (&Outputs->DimmVref))->Bits.Ch1VrefCtl);
+      break;
+
+    case 2:
+      OffH = (U8) (((DDRDATA7CH1_CR_DDRCRVREFADJUST1_STRUCT *) (&Outputs->DimmVref))->Bits.CAVrefCtl);
+      break;
+
+    default:
+      MRC_DEBUG_MSG (Debug, MSG_LEVEL_ERROR, "UpdateVrefWaitTilStable called with an incorrect value!\n");
+      return;
+  }
+
+  Offset = Offset + (S8) MrcSE (OffH, 7, 8); // Get offset from host. SE = Sign Extend number 7->8 bits
+  if (Offset > MAX_POSSIBLE_VREF) {
+    Offset = MAX_POSSIBLE_VREF;
+  } else if (Offset < (-1 * MAX_POSSIBLE_VREF)) {
+    Offset = -1 * MAX_POSSIBLE_VREF;
+  }
+
+  if (UpdateMrcData) {
+    switch (VrefType) {
+      case 0:
+        (((DDRDATA7CH1_CR_DDRCRVREFADJUST1_STRUCT *) (&Outputs->DimmVref))->Bits.Ch0VrefCtl) = Offset;
+        break;
+
+      case 1:
+        (((DDRDATA7CH1_CR_DDRCRVREFADJUST1_STRUCT *) (&Outputs->DimmVref))->Bits.Ch1VrefCtl) = Offset;
+        break;
+
+      case 2:
+        (((DDRDATA7CH1_CR_DDRCRVREFADJUST1_STRUCT *) (&Outputs->DimmVref))->Bits.CAVrefCtl) = Offset;
+        break;
+
+      default:
+        MRC_DEBUG_MSG (Debug, MSG_LEVEL_ERROR, "UpdateVrefWaitTilStable called with an incorrect value!\n");
+        return;
+    }
+  }
+
+  DdrCrVrefAdjust.Data = MrcReadCR (MrcData, DDRDATA7CH1_CR_DDRCRVREFADJUST1_REG);
+  switch (VrefType) {
+    case 0:
+      DdrCrVrefAdjust.Bits.Ch0VrefCtl = Offset;
+      CheckMask                       = DDRDATA7CH1_CR_DDRCRVREFADJUST1_ch0SlowBW_MSK;
+      break;
+
+    case 1:
+      DdrCrVrefAdjust.Bits.Ch1VrefCtl = Offset;
+      CheckMask                       = DDRDATA7CH1_CR_DDRCRVREFADJUST1_ch1SlowBW_MSK;
+      break;
+
+    case 2:
+      DdrCrVrefAdjust.Bits.CAVrefCtl = Offset;
+      CheckMask                      = DDRDATA7CH1_CR_DDRCRVREFADJUST1_caSlowBW_MSK;
+      break;
+
+    default:
+      MRC_DEBUG_MSG (Debug, MSG_LEVEL_ERROR, "UpdateVrefWaitTilStable called with an incorrect value!\n");
+      return;
+  }
+
+  MrcWriteCrMulticast (MrcData, DDRDATA7CH1_CR_DDRCRVREFADJUST1_REG, DdrCrVrefAdjust.Data);
+
+  //
+  // Wait for Vref to settle.  Note VrefCA needs longer to settle.
+  //
+  if (!SkipWait) {
+    Count = 0;
+    while (Count < 50) {
+      //
+      // Don't wait more than 50uS
+      //
+      if ((MrcReadCR (MrcData, DDRDATA7CH1_CR_DDRCRVREFADJUST1_REG) & CheckMask) == CheckMask) {
+        break;
+      }
+
+      MrcWait (MrcData, 1 * HPET_1US);
+      Count += 1;
+    }
+
+    if (Count >= 50) {
+      MRC_DEBUG_MSG (Debug, MSG_LEVEL_WARNING, "CAVref circuit failed to converge, \n");
+    }
+
+    MrcWait (MrcData, 5 * HPET_1US); // Add 5us to make sure everything is done
+  }
+}
+
+/**
+  This function is used to move CMD/CTL/CLK/CKE PIs during training
+
+  @param[in,out] MrcData    - Include all MRC global data.
+  @param[in]     Channel    - Channel to shift PI for
+  @param[in]     Iteration  - Determines which PI to shift:
+                              MrcIterationClock = 0
+                              MrcIterationCmdN  = 1
+                              MrcIterationCmdS  = 2
+                              MrcIterationCke   = 3
+                              MrcIterationCtl   = 4
+                              MrcIterationCmdV  = 5
+  @param[in]     RankMask   - Ranks to work on
+  @param[in]     GroupMask  - which LPDDR groups to work on for CMD/CLK/CKE; not used for DDR3
+  @param[in]     NewValue   - value to shift in case of CLK Iteration, New value for all other cases
+  @param[in]     UpdateHost - Determines if MrcData structure is updated
+
+  @retval Nothing
+**/
+void
+ShiftPIforCmdTraining (
+  IN OUT MrcParameters *const MrcData,
+  IN     const U8             Channel,
+  IN     const U8             Iteration,
+  IN     const U8             RankMask,
+  IN     const U8             GroupMask,
+  IN     S32                  NewValue,
+  IN     const U8             UpdateHost
+  )
+{
+  const MrcInput                        *Inputs;
+  const MrcDebug                        *Debug;
+  const MrcChannelIn                    *ChannelIn;
+  MrcChannelOut                         *ChannelOut;
+  MrcOutput                             *Outputs;
+  U32                                   Offset;
+  U32                                   ByteMask;
+  U32                                   BitOffset;
+  U8                                    Rank;
+#ifdef ULT_FLAG
+  U8                                    Group;
+  U32                                   Cke;
+  U32                                   CkeRankMapping;
+#endif // ULT_FLAG
+  S8                                    Shift;
+  BOOL                                  Lpddr;
+  DDRCLKCH0_CR_DDRCRCLKPICODE_STRUCT    ClkPiCode;
+  DDRCKECH0_CR_DDRCRCMDPICODING_STRUCT  CkeCmdPiCoding;
+  DDRCMDSCH0_CR_DDRCRCMDPICODING_STRUCT CmdSPiCoding;
+  DDRCMDNCH0_CR_DDRCRCMDPICODING_STRUCT CmdNPiCoding;
+  DDRCTLCH0_CR_DDRCRCTLPICODING_STRUCT  CtlPiCoding;
+
+  Inputs     = &MrcData->SysIn.Inputs;
+  Outputs    = &MrcData->SysOut.Outputs;
+  Debug      = &MrcData->SysIn.Inputs.Debug;
+  ChannelIn  = &Inputs->Controller[0].Channel[Channel];
+  ChannelOut = &Outputs->Controller[0].Channel[Channel];
+  Lpddr      = (Outputs->DdrType == MRC_DDR_TYPE_LPDDR3);
+
+  if (Iteration != MrcIterationClock) {
+    if (NewValue < 0) {
+      NewValue = 0;
+    } else if (NewValue > 127) {
+      NewValue = 127;
+    }
+  }
+
+  //MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\nShiftPIforCmdTraining: Iteration: %d, Channel: %d, RankMask: %d, GroupMask: %d, NewValue = 0x%x\n", Iteration, Channel, RankMask, GroupMask, NewValue);
+
+  switch (Iteration) {
+    case MrcIterationClock: // SHIFT CLOCK
+      ClkPiCode.Data = 0;
+      ByteMask  = 0x1FF;    // Shift DQ PI on all 9 bytes by default on DDR3
+
+#ifdef ULT_FLAG
+      if (Lpddr) {
+        //
+        // In LPDDR clocks are per group, not per rank
+        //
+        for (Group = 0; Group < 2; Group++) {
+          BitOffset = DDRCLKCH0_CR_DDRCRCLKPICODE_PiSettingRank0_WID * Group;
+          if (GroupMask & (1 << Group)) {
+            Shift = (ChannelOut->ClkPiCode[Group] + NewValue) % 128;
+            if (Shift < 0) {
+              Shift = (128 - ABS (Shift));
+            }
+
+            Shift &= DDRCLKCH0_CR_DDRCRCLKPICODE_PiSettingRank0_MSK;
+            if (UpdateHost) {
+              ChannelOut->ClkPiCode[Group] = Shift;
+            }
+
+            ClkPiCode.Data += (Shift << BitOffset);
+            //
+            // Each clock spans all ranks, so need to shift DQ PIs on all ranks, for bytes in this group only
+            //
+            ByteMask = ChannelIn->DQByteMap[MrcIterationClock][Group];
+            for (Rank = 0; Rank < MAX_RANK_IN_CHANNEL; Rank++) {
+              if (MrcRankInChannelExist (MrcData, Rank, Channel)) {
+                ShiftDQPIs (MrcData, Channel, Rank, ByteMask, (S8) NewValue, UpdateHost, 0);
+              }
+            }
+          } else {
+            ClkPiCode.Data += (ChannelOut->ClkPiCode[Group] << BitOffset);
+          }
+        } // for Group
+      } else
+#endif // ULT_FLAG
+      {
+        for (Rank = 0; Rank < MAX_RANK_IN_CHANNEL; Rank++) {
+          BitOffset = DDRCLKCH0_CR_DDRCRCLKPICODE_PiSettingRank0_WID * Rank;
+          if (RankMask & (1 << Rank)) {
+            Shift = (ChannelOut->ClkPiCode[Rank] + NewValue) % 128;
+            if (Shift < 0) {
+              Shift = (128 - ABS (Shift));
+            }
+
+            Shift &= DDRCLKCH0_CR_DDRCRCLKPICODE_PiSettingRank0_MSK;
+            if (UpdateHost) {
+              ChannelOut->ClkPiCode[Rank] = Shift;
+            }
+
+            ClkPiCode.Data += (Shift << BitOffset);
+            ShiftDQPIs (MrcData, Channel, Rank, ByteMask, (S8) NewValue, UpdateHost, 0);
+          } else {
+            ClkPiCode.Data += (ChannelOut->ClkPiCode[Rank] << BitOffset);
+          }
+        }
+      }
+
+      Offset = DDRCLKCH0_CR_DDRCRCLKPICODE_REG + ((DDRCLKCH1_CR_DDRCRCLKPICODE_REG - DDRCLKCH0_CR_DDRCRCLKPICODE_REG) * Channel);
+      MrcWriteCR (MrcData, Offset, ClkPiCode.Data);
+      //MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "**** ShiftPIforCmdTraining, Iteration = %d, CRValue = 0x%x ****\n", Iteration,CRValue);
+      break;
+
+    case MrcIterationCmdN: // SHIFT COMMAND NORTH
+      CmdNPiCoding.Data = 0;
+      NewValue = MIN (NewValue, DDRCMDNCH0_CR_DDRCRCMDPICODING_CmdPi0Code_MAX);
+      //
+      // HSW ULT LPDDR3: CMDN.CmdPi1Code controls CAB
+      // HSW ULT DDR3L:  Both CmdPi0Code and CmdPi1Code should have the same value
+      // HSW TRAD DDR3L: No harm setting CmdPi1Code same as CmdPi0Code
+      //
+      CmdNPiCoding.Bits.CmdPi0Code = NewValue;
+      CmdNPiCoding.Bits.CmdPi1Code = NewValue;
+      Offset = DDRCMDNCH0_CR_DDRCRCMDPICODING_REG +
+        ((DDRCMDNCH1_CR_DDRCRCMDPICODING_REG - DDRCMDNCH0_CR_DDRCRCMDPICODING_REG) * Channel);
+      MrcWriteCR (MrcData, Offset, CmdNPiCoding.Data);
+      if (UpdateHost) {
+        ChannelOut->CmdnCmdPiCode[0] = NewValue;
+        ChannelOut->CmdnCmdPiCode[1] = NewValue;
+      }
+      break;
+
+    case MrcIterationCmdS: // SHIFT COMMAND SOUTH
+      CmdSPiCoding.Data = 0;
+      NewValue = MIN (NewValue, DDRCMDSCH0_CR_DDRCRCMDPICODING_CmdPi0Code_MAX);
+      //
+      // HSW ULT LPDDR3: CMDS.CmdPi0Code controls CAA, CMDS.CmdPi1Code controls CAB
+      // HSW ULT DDR3L:  Both CmdPi0Code and CmdPi1Code should have the same value, also program CKE fub
+      // HSW TRAD DDR3L: No harm setting CmdPi1Code same as CmdPi0Code, also program CKE fub
+      //
+#ifdef ULT_FLAG
+      if (Lpddr) {
+        CmdSPiCoding.Bits.CmdPi0Code = (GroupMask & 1) ? (U32) NewValue : ChannelOut->CmdsCmdPiCode[0]; // CAA
+        CmdSPiCoding.Bits.CmdPi1Code = (GroupMask & 2) ? (U32) NewValue : ChannelOut->CmdsCmdPiCode[1]; // CAB
+      } else
+#endif // ULT_FLAG
+      {
+        CmdSPiCoding.Bits.CmdPi0Code = NewValue;
+        CmdSPiCoding.Bits.CmdPi1Code = NewValue;
+
+        CkeCmdPiCoding.Data             = 0;
+        NewValue                        = MIN (NewValue, DDRCKECH0_CR_DDRCRCMDPICODING_CmdPi0Code_MAX);
+        CkeCmdPiCoding.Bits.CmdPi0Code  = NewValue;
+        CkeCmdPiCoding.Bits.CmdPi1Code  = NewValue;
+        Offset = DDRCKECH0_CR_DDRCRCMDPICODING_REG +
+          ((DDRCKECH1_CR_DDRCRCMDPICODING_REG - DDRCKECH0_CR_DDRCRCMDPICODING_REG) * Channel);
+        MrcWriteCR (MrcData, Offset, CkeCmdPiCoding.Data);
+        if (UpdateHost) {
+          ChannelOut->CkeCmdPiCode[0] = NewValue;
+          ChannelOut->CkeCmdPiCode[1] = NewValue;
+        }
+      }
+
+      if (UpdateHost) {
+        ChannelOut->CmdsCmdPiCode[0] = CmdSPiCoding.Bits.CmdPi0Code;
+        ChannelOut->CmdsCmdPiCode[1] = CmdSPiCoding.Bits.CmdPi1Code;
+      }
+
+      Offset = DDRCMDSCH0_CR_DDRCRCMDPICODING_REG +
+        ((DDRCMDSCH1_CR_DDRCRCMDPICODING_REG - DDRCMDSCH0_CR_DDRCRCMDPICODING_REG) * Channel);
+      MrcWriteCR (MrcData, Offset, CmdSPiCoding.Data);
+      break;
+
+    case MrcIterationCke: // Shift CKE command
+      CkeCmdPiCoding.Data = 0;
+      NewValue            = MIN (NewValue, DDRCKECH0_CR_DDRCRCMDPICODING_CmdPi0Code_MAX);
+      //
+      // HSW ULT LPDDR3: CKE.CmdPi0Code controls CAA
+      // HSW ULT DDR3L:  Both CmdPi0Code and CmdPi1Code should have the same value
+      // HSW TRAD DDR3L: No harm setting CmdPi1Code same as CmdPi0Code
+      //
+      CkeCmdPiCoding.Bits.CmdPi0Code = NewValue;
+      CkeCmdPiCoding.Bits.CmdPi1Code = NewValue;
+      Offset = DDRCKECH0_CR_DDRCRCMDPICODING_REG +
+        ((DDRCKECH1_CR_DDRCRCMDPICODING_REG - DDRCKECH0_CR_DDRCRCMDPICODING_REG) * Channel);
+      MrcWriteCR (MrcData, Offset, CkeCmdPiCoding.Data);
+      if (UpdateHost) {
+        ChannelOut->CkeCmdPiCode[0] = NewValue;
+        ChannelOut->CkeCmdPiCode[1] = NewValue;
+      }
+      break;
+
+    case MrcIterationCtl: // Shift CS/ODT and CKE.Control
+      CtlPiCoding.Data = 0;
+      NewValue         = MIN (NewValue, DDRCTLCH0_CR_DDRCRCTLPICODING_CtlPiCode0_MAX);
+      for (Rank = 0; Rank < MAX_RANK_IN_CHANNEL; Rank++) {
+        if (RankMask & (1 << Rank)) {
+          CtlPiCoding.Data += (NewValue << (DDRCTLCH0_CR_DDRCRCTLPICODING_CtlPiCode0_WID * Rank));
+          if (UpdateHost) {
+            ChannelOut->CtlPiCode[Rank] = (U8) NewValue;
+            ChannelOut->CkePiCode[Rank] = (U8) NewValue;
+          }
+        } else {
+          CtlPiCoding.Data += (ChannelOut->CtlPiCode[Rank] << (DDRCTLCH0_CR_DDRCRCTLPICODING_CtlPiCode0_WID * Rank));
+        }
+      }
+
+#ifdef ULT_FLAG
+      if (Lpddr && Inputs->LpddrDramOdt) {
+        //
+        // ODT[0] (equal to CS[0] PI setting) goes in to CTL.CtlPiCode2
+        //
+        CtlPiCoding.Bits.CtlPiCode2 = ChannelOut->CtlPiCode[0];
+      }
+#endif // ULT_FLAG
+      Offset = DDRCTLCH0_CR_DDRCRCTLPICODING_REG +
+        ((DDRCTLCH1_CR_DDRCRCTLPICODING_REG - DDRCTLCH0_CR_DDRCRCTLPICODING_REG) * Channel);
+      MrcWriteCR (MrcData, Offset, CtlPiCoding.Data);
+
+#ifdef ULT_FLAG
+      if (Lpddr) {
+        CtlPiCoding.Data = 0;
+        //
+        // Use CKE-to-Rank mapping: [3:0] - Channel 0, [7:4] - Channel 1
+        //
+        CkeRankMapping = (Inputs->CkeRankMapping >> (Channel * 4)) & 0x0F;
+        for (Rank = 0; Rank < MAX_RANK_IN_CHANNEL; Rank++) {
+          for (Cke = 0; Cke <= 3; Cke++) {
+            if (((CkeRankMapping >> Cke) & 1) == Rank) {
+              //
+              // This CKE pin is connected to this Rank
+              //
+              CtlPiCoding.Data += (ChannelOut->CkePiCode[Rank] << (DDRCKECH0_CR_DDRCRCTLPICODING_CtlPiCode0_WID * Cke));
+            }
+          }
+        }
+        //
+        // Put average of CKE2 and CKE3 into CKE2 PI setting.
+        //
+        CtlPiCoding.Bits.CtlPiCode2 = (CtlPiCoding.Bits.CtlPiCode2 + CtlPiCoding.Bits.CtlPiCode3) / 2;
+      }
+#endif // ULT_FLAG
+      Offset = DDRCKECH0_CR_DDRCRCTLPICODING_REG +
+        ((DDRCKECH1_CR_DDRCRCTLPICODING_REG - DDRCKECH0_CR_DDRCRCTLPICODING_REG) * Channel);
+      CtlPiCoding.Bits.CtlPiCode3 = 0;  // Do not write PiCode3
+      MrcWriteCR (MrcData, Offset, CtlPiCoding.Data);
+      break;
+
+    default:
+      MRC_DEBUG_MSG (Debug, MSG_LEVEL_WARNING, "WARNING...Unknown parameter to shift\n");
+      break;
+  }
+
+  return;
+}
+
+/**
+  Shifts RcvEn, WriteLevel and WriteDQS timing for all bytes
+  Usually used when moving the clocks on a channel
+
+  @param[in,out] MrcData    - Include all MRC global data.
+  @param[in]     Channel    - Channel to update
+  @param[in]     Rank       - Rank to update
+  @param[in]     ByteMask   - Bytes to update
+  @param[in]     Offset     - value to shift
+  @param[in]     UpdateHost - Determines if MrcData structure is updated
+  @param[in]     SkipTx     - Determines if TX update should be skipped
+
+  @retval Nothing
+**/
+void
+ShiftDQPIs (
+  IN OUT MrcParameters *const MrcData,
+  IN     const U8             Channel,
+  IN     const U8             Rank,
+  IN     const U32            ByteMask,
+  IN     const S8             Offset,
+  IN     const U8             UpdateHost,
+  IN     const U8             SkipTx
+  )
+{
+  MrcOutput                           *Outputs;
+  MrcChannelOut                       *ChannelOut;
+  U8                                  Byte;
+  S8                                  OffTx;
+  U16                                 RcvEnValue;
+  DDRDATA0CH0_CR_TXTRAINRANK0_STRUCT  CrTxTrainRank;
+
+  const MrcDebug                      *Debug;
+
+  Debug       = &MrcData->SysIn.Inputs.Debug;
+  Outputs     = &MrcData->SysOut.Outputs;
+  ChannelOut  = &Outputs->Controller[0].Channel[Channel];
+  OffTx       = SkipTx ? 0 : Offset;
+
+  for (Byte = 0; Byte < Outputs->SdramCount; Byte++) {
+    if (((1 << Byte) & ByteMask) == 0) {
+      continue;
+    }
+
+    RcvEnValue = ChannelOut->RcvEn[Rank][Byte] + Offset;
+    if ((S16) RcvEnValue < 0) {
+      MRC_DEBUG_MSG (Debug, MSG_LEVEL_WARNING, "WARNING: RcvEn PI wrapped below zero!\n");
+      RcvEnValue = 0;   // Don't go below zero
+    } else if (RcvEnValue > DDRDATA_CR_RXTRAINRANK0_RxRcvEnPi_MAX) {
+      MRC_DEBUG_MSG (Debug, MSG_LEVEL_WARNING, "WARNING: RcvEn PI wrapped above 9 bits!\n");
+      RcvEnValue = DDRDATA_CR_RXTRAINRANK0_RxRcvEnPi_MAX;   // Don't go above max
+    }
+
+    UpdateRxT (MrcData, Channel, Rank, Byte, 0, RcvEnValue);
+
+    CrTxTrainRank.Data                = 0;
+    CrTxTrainRank.Bits.TxEqualization = ChannelOut->TxEq[Rank][Byte];
+    CrTxTrainRank.Bits.TxDqsDelay     = ChannelOut->TxDqs[Rank][Byte] + OffTx;
+    CrTxTrainRank.Bits.TxDqDelay      = ChannelOut->TxDq[Rank][Byte] + OffTx;
+    UpdateTxT (MrcData, Channel, Rank, Byte, 3, CrTxTrainRank.Data);
+
+    if (UpdateHost) {
+      ChannelOut->RcvEn[Rank][Byte]  = RcvEnValue;
+      ChannelOut->TxDqs[Rank][Byte] += OffTx;
+      ChannelOut->TxDq[Rank][Byte]  += OffTx;
+    }
+  }
+
+  return;
+}
+
+/**
+  Retrieve the current memory frequency and clock from the memory controller.
+
+  @param[in]      MrcData     - Include all MRC global data.
+  @param[in, out] MemoryClock - The current memory clock.
+  @param[in, out] Ratio       - The current memory ratio setting.
+  @param[in, out] RefClk      - The current memory reference clock.
+
+  @retval: The current memory frequency.
+**/
+MrcFrequency
+MrcGetCurrentMemoryFrequency (
+  MrcParameters * const   MrcData,
+  U32 * const             MemoryClock,
+  MrcClockRatio * const   Ratio,
+  MrcRefClkSelect * const RefClk
+  )
+{
+  const MrcInput                 *Inputs;
+  const MrcOutput                *Outputs;
+  PCU_CR_MC_BIOS_DATA_PCU_STRUCT McBiosData;
+  PCU_CR_MC_BIOS_REQ_PCU_STRUCT  McBiosReqPcu;
+
+  Inputs  = &MrcData->SysIn.Inputs;
+  Outputs = &MrcData->SysOut.Outputs;
+  McBiosReqPcu.Data = MrcReadCR (MrcData, PCU_CR_MC_BIOS_REQ_PCU_REG);
+  McBiosData.Data   = MrcReadCR (MrcData, PCU_CR_MC_BIOS_DATA_PCU_REG);
+  if (MemoryClock != NULL) {
+    *MemoryClock = MrcRatioToClock ((MrcClockRatio) McBiosData.Bits.MC_FREQ, McBiosReqPcu.Bits.REQ_TYPE, Inputs->BClkFrequency);
+  }
+  if (Ratio != NULL) {
+    *Ratio = (MrcClockRatio) McBiosData.Bits.MC_FREQ;
+  }
+  if (RefClk != NULL) {
+    *RefClk = (MrcRefClkSelect) McBiosReqPcu.Bits.REQ_TYPE;
+  }
+  return MrcRatioToFrequency (
+          MrcData,
+          (MrcClockRatio) McBiosData.Bits.MC_FREQ,
+          McBiosReqPcu.Bits.REQ_TYPE,
+          Inputs->BClkFrequency
+          );
+}
+
+#ifdef ULT_FLAG
+
+/**
+  Translate LPDDR command from CA[9:0] high and low phase to DDR3 MA/BA/CMD.
+  This is needed to program CADB.
+
+  @param[in]  CaHigh - CA[9:0] value on the rising clock
+  @param[in]  CaLow  - CA[9:0] value on the falling clock
+  @param[out] MA     - Translated value of MA[15:0]
+  @param[out] BA     - Translated value of BA[2:0]
+  @param[out] CMD    - Translated value of CMD[2:0] = [RASb, CASb, WEb]
+
+  @retval none
+**/
+void
+MrcConvertLpddr2Ddr (
+  IN  U32 const CaHigh,
+  IN  U32 const CaLow,
+  OUT U32       *MA,
+  OUT U32       *BA,
+  OUT U32       *CMD
+  )
+{
+  *MA  = MRC_BIT15;   // MA[15] should be 1
+  *BA  = 0;
+  *CMD = MRC_BIT2;    // RASb should be 1
+
+  //
+  // Translation table
+  //
+  // Command  High phase Low phase
+  //-----------------------------
+  // CA[0]    CASb       MA[0]
+  // CA[1]    WEb        MA[1]
+  // CA[2]    MA[8]      MA[2]
+  // CA[3]    MA[9]      MA[3]
+  // CA[4]    MA[10]     MA[4]
+  // CA[5]    MA[11]     MA[5]
+  // CA[6]    MA[12]     MA[6]
+  // CA[7]    BA[0]      MA[7]
+  // CA[8]    BA[1]      MA[13]
+  // CA[9]    BA[2]      MA[14]
+
+  *MA  |= (CaLow & 0xFF);          // MA[7:0]
+  *MA  |= ((CaHigh & 0x7C) << 6);  // MA[12:8]
+  *MA  |= ((CaLow & 0x300) << 5);  // MA[14:13]
+
+  *BA  |= ((CaHigh & 0x380) >> 7); // BA[2:0]
+
+  *CMD |= ((CaHigh & 0x02) >> 1);  // CMD[0] = WEb
+  *CMD |= ((CaHigh & 0x01) << 1);  // CMD[1] = CASb
+}
+
+/**
+  Run a short CADB sequence on selected channels
+
+  @param[in] MrcData   - The MRC global data.
+  @param[in] ChBitMask - channels to work on.
+
+  @retval none
+**/
+void
+ShortRunCADB (
+  IN MrcParameters *const  MrcData,
+  IN U8                    ChBitMask
+  )
+{
+  U32   Channel;
+  U32   Offset;
+  MCDFXS_CR_REUT_GLOBAL_CTL_MCMAIN_STRUCT   ReutGlobalCtl;
+  MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_STRUCT  ReutChPatCadbCtrl;
+  MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_STRUCT ReutChSeqCfg;
+
+  //
+  // Enable REUT mode and Global Control on selected channels
+  //
+  for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+    Offset = MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_REG +
+      ((MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_REG - MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_REG) * Channel);
+    ReutChSeqCfg.Data = MrcReadCR64 (MrcData, Offset);
+    if (((1 << Channel) & ChBitMask) != 0) {
+      ReutChSeqCfg.Bits.Initialization_Mode = REUT_Testing_Mode;
+      ReutChSeqCfg.Bits.Global_Control      = 1;
+    } else {
+      ReutChSeqCfg.Bits.Global_Control = 0;
+    }
+
+    MrcWriteCR64 (MrcData, Offset, ReutChSeqCfg.Data);
+  }
+  //
+  // Enable CADB Always On mode
+  //
+  ReutChPatCadbCtrl.Data                        = 0;
+  ReutChPatCadbCtrl.Bits.Enable_CADB_Always_On  = 1;
+  MrcWriteCR (MrcData, MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_REG, ReutChPatCadbCtrl.Data);
+
+  //
+  // Start CADB
+  //
+  ReutGlobalCtl.Data                    = 0;
+  ReutGlobalCtl.Bits.Global_Start_Test  = 1;
+  MrcWriteCR (MrcData, MCDFXS_CR_REUT_GLOBAL_CTL_MCMAIN_REG, ReutGlobalCtl.Data);
+
+  //
+  // It's enough to read from this register, no need for an extra delay
+  //
+  ReutGlobalCtl.Data = MrcReadCR (MrcData, MCDFXS_CR_REUT_GLOBAL_CTL_MCMAIN_REG);
+  //
+  // Disable CADB Always On mode
+  //
+  ReutChPatCadbCtrl.Bits.Enable_CADB_Always_On = 0;
+  MrcWriteCR (MrcData, MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_REG, ReutChPatCadbCtrl.Data);
+
+  //
+  // Stop CADB
+  //
+  ReutGlobalCtl.Bits.Global_Start_Test  = 0;
+  ReutGlobalCtl.Bits.Global_Stop_Test   = 1;
+  MrcWriteCR (MrcData, MCDFXS_CR_REUT_GLOBAL_CTL_MCMAIN_REG, ReutGlobalCtl.Data);
+
+  //
+  // Read back
+  //
+  ReutGlobalCtl.Data = MrcReadCR (MrcData, MCDFXS_CR_REUT_GLOBAL_CTL_MCMAIN_REG);
+
+  //
+  // Disable Global Control on selected channels
+  //
+  for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+    if (((1 << Channel) & ChBitMask) != 0) {
+      Offset = MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_REG +
+        ((MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_REG - MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_REG) * Channel);
+      ReutChSeqCfg.Data                 = MrcReadCR64 (MrcData, Offset);
+      ReutChSeqCfg.Bits.Global_Control  = 0;
+      MrcWriteCR64 (MrcData, Offset, ReutChSeqCfg.Data);
+    }
+  }
+}
+
+#endif // ULT_FLAG
+
+/**
+  Get the Rx Bias values
+
+  @param[in, out] MrcData    - Include all MRC global data.
+  @param[in, out] RxFselect  - Location to save RxFselect.
+  @param[in, out] RxCBSelect - Location to save RxCBSelect.
+
+  @retval none
+**/
+void
+GetRxFselect (
+  IN MrcParameters *const MrcData,
+  IN OUT S8            *RxFselect,
+  IN OUT U8            *RxCBSelect
+  )
+{
+  MrcOutput                    *Outputs;
+  DDRCLK_CR_DDRCBSTATUS_STRUCT DdrCbStatus;
+
+  Outputs          = &MrcData->SysOut.Outputs;
+  DdrCbStatus.Data = MrcReadCR (MrcData, DDRCLK_CR_DDRCBSTATUS_REG);
+  *RxCBSelect      = (U8) DdrCbStatus.Bits.DllCB;
+  *RxFselect       = (Outputs->Ratio - ((Outputs->RefClk == MRC_REF_CLOCK_133) ? RXF_SELECT_RC_133 : RXF_SELECT_RC_100));
+
+  //
+  // Limit ratios for 1067, 1333, 1600, 1867 & 2133 MHz
+  //
+  *RxFselect = MIN (*RxFselect, RXF_SELECT_MAX);  // Maximum 2133 MHz
+  *RxFselect = MAX (*RxFselect, RXF_SELECT_MIN);  // Minimum 1067 MHz
+  return;
+}
diff --git a/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Services/MrcCrosser.c b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Services/MrcCrosser.c
new file mode 100644
index 0000000..4086802
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Services/MrcCrosser.c
@@ -0,0 +1,9860 @@
+/** @file
+  These functions implement the crosser training algorithm.
+
+@copyright
+  Copyright (c) 1999 - 2013 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement.
+
+**/
+
+//
+// Include files
+//
+#include "MrcCrosser.h"
+#if SUPPORT_SODIMM == SUPPORT
+#include "MrcSpdProcessing.h"
+#endif //SUPPORT_SODIMM == SUPPORT
+
+///
+/// Module Definitions
+///
+#define BIT_TX_XTALK_SWEEP_START  (-3)
+#define BIT_TX_XTALK_SWEEP_STOP   (3)
+#define BIT_TX_XTALK_SWEEP_LEN    (BIT_TX_XTALK_SWEEP_STOP - BIT_TX_XTALK_SWEEP_START + 1)
+#define BIT_TX_XTALK_RANGE        (16)
+
+#define DIMM_ODT_DIMM_MASK_SHIFT  (4)
+
+///
+/// Power optimizations Global Parameters
+///
+#define OPT_PARAM_LOOP_COUNT (15)
+#define OPT_PARAM_1D_LC      (15)
+
+///
+/// UPM/PWR increment value if margins are at or below the retrain limit.
+///
+#define MRC_UPM_PWR_INC_VAL (40)
+
+//
+// Module Globals
+//
+const MrcUpmPwrRetrainLimits  InitialLimits[MRC_NUMBER_UPM_PWR_RETRAIN_MARGINS] = {
+  //
+  //           UPM,     PWR      Retrain
+  //
+  {RdT,       {240,     320,     90 }},
+  {WrT,       {220,     280,     90 }},
+  {RdV,       {400,     520,     160}},
+  // For ULT DDR3L rcF the values are increased by 20 ticks, see UpmPwrLimitValue()
+  {WrV,       {400,     520,     160}},
+  {RdFan2,    {240,     480,     0  }},
+  {WrFan2,    {240,     480,     0  }},
+  {RdFan3,    {240*4/5, 480*4/5, 0  }},
+  {WrFan3,    {240*4/5, 480*4/5, 0  }},
+  // {650ps,750ps} * 64 pi ticks * 2 (for width) = 134 PI Ticks.  ~1.3nsec for UPM,~1.5nsec for PWR
+  // We must subtract out the built in margin of 96 when shifting IO Lat.
+  // Margin function works in steps of 2, so we divide the margin by 2.
+  // Margin numbers are scaled by 10.
+  {RcvEnaX,  {(((134 - 96) / 2) * 10), (((154 - 96) / 2) * 10), 0}}
+};
+
+const U8    ActualDimmOdt[6] = { 0, 120, 60, 40, 30, 20 };
+
+#ifdef MRC_DEBUG_PRINT
+const char  *TOptParamOffsetString[] = {
+  "OptWrDS",
+  "OptRdOdt",
+  "OptSComp",
+  "OptTComp",
+  "OptTxEq",
+  "OptRxEq",
+  "OptRxBias",
+  "OptDimmOdt",
+  "OptDimmOdtWr",
+  "OptDimmRon",
+  "OptDefault"
+};
+
+const char  *MarginTypesString[] = {
+  "RcvEna",
+  "RdT",
+  "WrT",
+  "WrDqsT",
+  "RdV",
+  "WrV",
+  "WrLevel",
+  "WrTBox",
+  "WrTBit",
+  "RdTBit",
+  "RdVBit",
+  "RcvEnaX",
+  "CmdT",
+  "CmdV"
+};
+
+///
+/// These strings match the OptResultPerByteDbgStr enum for indexing
+/// the switch PrintCalcResultTableCh and PrintODTResultTable.
+///
+const char *OptResultDbgStrings[] = {
+  "Best",
+  "GrdBnd",
+  "OffSel",
+  "Scale",
+  "Signal",
+  "Noise",
+  "Ratio",
+  "MaxPost",
+  "MinPost",
+  "Ticks",
+  "SNRTot."
+};
+
+#endif // MRC_DEBUG_PRINT
+
+/**
+  This function implements Sense Amp Offset training.
+  SenseAmp/ODT offset cancellation
+  Find the best "average" point for Vref Control
+  Test Vref point with SampOffset=-7 and Test Vref Point with SampOffset=+7
+  Find Vref on per ch/byte basis where -7 samples all 1 and +7 samples all 0
+
+  @param[in,out] MrcData - Include all MRC global data.
+
+  @retval MrcStatus - if it succeded return mrcSuccess
+**/
+MrcStatus
+MrcSenseAmpOffsetTraining (
+  IN OUT MrcParameters *const MrcData
+  )
+{
+  const MrcInput                          *Inputs;
+  const MrcDebug                          *Debug;
+  MrcOutput                               *Outputs;
+  MrcControllerOut                        *ControllerOut;
+  MrcChannelOut                           *ChannelOut;
+  MrcStatus                               Status;
+  U32                                     Offset;
+  S8                                      sumBits[MAX_CHANNEL][MAX_SDRAM_IN_DIMM];
+  S8                                      FirstBestPoint[MAX_CHANNEL][MAX_SDRAM_IN_DIMM];
+  S8                                      LastBestPoint[MAX_CHANNEL][MAX_SDRAM_IN_DIMM];
+  //
+  // additional bit for DQS per each byte
+  //
+  S8                                      firstZero[MAX_CHANNEL][MAX_SDRAM_IN_DIMM][MAX_BITS_FOR_OFFSET_TRAINING];
+  //
+  // additional bit for DQS per each byte
+  //
+  S8                                      lastOne[MAX_CHANNEL][MAX_SDRAM_IN_DIMM][MAX_BITS_FOR_OFFSET_TRAINING];
+  S8                                      sampOffset;
+  S8                                      vref;
+  S8                                      VrefWidth;
+  U8                                      HighMask[MAX_CHANNEL][MAX_SDRAM_IN_DIMM];
+  U8                                      LowMask[MAX_CHANNEL][MAX_SDRAM_IN_DIMM];
+  U8                                      Channel;
+  U8                                      Rank;
+  U8                                      byte;
+  U8                                      bit;
+  U8                                      MaxBits;
+  BOOL                                    Lpddr;
+  DDRDATACH0_CR_DDRCRDATACONTROL0_STRUCT  DdrCrDataControl0;
+  DDRDATA0CH0_CR_DDRCRDATACONTROL2_STRUCT DdrCrDataControl2;
+  DDRDATA0CH0_CR_DATATRAINFEEDBACK_STRUCT DataTrainFeedback;
+  DDRDATA_CR_RXOFFSETVDQ_STRUCT           RxOffsetVdq;
+
+  Inputs        = &MrcData->SysIn.Inputs;
+  Debug         = &Inputs->Debug;
+  Outputs       = &MrcData->SysOut.Outputs;
+  ControllerOut = &Outputs->Controller[0];
+  Status        = mrcSuccess;
+  Lpddr         = (Outputs->DdrType == MRC_DDR_TYPE_LPDDR3);
+
+  //
+  // Init LastBestPoint to 0, FirstBestPoint to -8, LowMask to 0xff and HighMask to 0
+  //
+  MrcOemMemorySet ((U8 *) LastBestPoint, 0, sizeof (LastBestPoint));
+  MrcOemMemorySet ((U8 *) FirstBestPoint, (U32) (-8), sizeof (FirstBestPoint));
+  MrcOemMemorySet ((U8 *) LowMask, (U32) (-1), sizeof (LowMask));
+  MrcOemMemorySet ((U8 *) HighMask, 0, sizeof (LowMask));
+
+  MRC_DEBUG_MSG (
+    Debug,
+    MSG_LEVEL_NOTE,
+    "Stage 1: Vref Offset Training\nPlot Of SumOfBits across Vref settings\nChannel\t0                1\nByte\t"
+    );
+  MRC_DEBUG_MSG (
+    Debug,
+    MSG_LEVEL_NOTE,
+    (Outputs->SdramCount == MAX_SDRAM_IN_DIMM) ? "0 1 2 3 4 5 6 7 8 0 1 2 3 4 5 6 7 8" : "0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7"
+    );
+
+  for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+    if (MrcChannelExist (Outputs, Channel)) {
+      ChannelOut = &ControllerOut->Channel[Channel];
+      //
+      // Force RXAmp and Bias on -MUST use Per byte as preious DqControl2 values depended on byte number
+      //
+      for (byte = 0; byte < Outputs->SdramCount; byte++) {
+        DdrCrDataControl2.Data              = ChannelOut->DqControl2[byte].Data;
+        DdrCrDataControl2.Bits.ForceBiasOn  = 1;
+        DdrCrDataControl2.Bits.ForceRxOn    = 1;
+        Offset = DDRDATA0CH0_CR_DDRCRDATACONTROL2_REG +
+          ((DDRDATA0CH1_CR_DDRCRDATACONTROL2_REG - DDRDATA0CH0_CR_DDRCRDATACONTROL2_REG) * Channel) +
+            ((DDRDATA1CH0_CR_DDRCRDATACONTROL2_REG - DDRDATA0CH0_CR_DDRCRDATACONTROL2_REG) * byte);
+        MrcWriteCR (MrcData, Offset, DdrCrDataControl2.Data);
+      }
+    }
+  }
+  //
+  // Sweep through vref settings and find point SampOffset of +/- 7 passes
+  //
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\n1/2 Vref");
+  for (vref = -8; vref <= 8; vref++) {
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\n% 5d\t", vref);
+
+    //
+    // Run Test and Record Results.
+    //
+    Status = ChangeMargin (MrcData, RdV, vref, 0, 1, 0, 0, 0, 0, 0, 0, MrcRegFileRank);
+
+    //
+    // Program settings for Vref and SampOffset = 7
+    //
+    MrcWriteCrMulticast (MrcData, DDRDATA_CR_RXOFFSETVDQ_REG, 0xFFFFFFFF); // (8+7)
+    //
+    // To run test, enable Offset Cancel mode and Enable ODT
+    // Check Results and Update variables.  Ideal result is all 0
+    // Clear Offset Cancel mode at end test to enable writing RX_OffsetV
+    //
+    for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+      if (MrcChannelExist (Outputs, Channel)) {
+        ChannelOut = &ControllerOut->Channel[Channel];
+
+        //
+        // Propagate delay values (without a read command)
+        //
+        DdrCrDataControl0.Data                      = ChannelOut->DqControl0.Data;
+        DdrCrDataControl0.Bits.ReadRFRd             = 1;
+        DdrCrDataControl0.Bits.ReadRFWr             = 0;
+        DdrCrDataControl0.Bits.ReadRFRank           = 0;
+        DdrCrDataControl0.Bits.ForceOdtOn           = 1;
+        DdrCrDataControl0.Bits.SenseampTrainingMode = 1;
+        Offset = DDRDATACH0_CR_DDRCRDATACONTROL0_REG +
+          ((DDRDATACH1_CR_DDRCRDATACONTROL0_REG - DDRDATACH0_CR_DDRCRDATACONTROL0_REG) * Channel);
+        MrcWriteCrMulticast (MrcData, Offset, DdrCrDataControl0.Data);
+
+        MrcWait (MrcData, HPET_1US);
+
+        for (byte = 0; byte < Outputs->SdramCount; byte++) {
+          Offset = DDRDATA0CH0_CR_DATATRAINFEEDBACK_REG +
+            ((DDRDATA0CH1_CR_DATATRAINFEEDBACK_REG - DDRDATA0CH0_CR_DATATRAINFEEDBACK_REG) * Channel) +
+            ((DDRDATA1CH0_CR_DATATRAINFEEDBACK_REG - DDRDATA0CH0_CR_DATATRAINFEEDBACK_REG) * byte);
+          DataTrainFeedback.Data  = (U8) MrcReadCR (MrcData, Offset);
+          sumBits[Channel][byte]  = -(MrcCountBitsEqOne (DataTrainFeedback.Bits.DataTrainFeedback));
+          LowMask[Channel][byte] &= (U8) DataTrainFeedback.Bits.DataTrainFeedback;
+        }
+
+        DdrCrDataControl0.Bits.SenseampTrainingMode = 0;
+        Offset = DDRDATACH0_CR_DDRCRDATACONTROL0_REG +
+          ((DDRDATACH1_CR_DDRCRDATACONTROL0_REG - DDRDATACH0_CR_DDRCRDATACONTROL0_REG) * Channel);
+        MrcWriteCrMulticast (MrcData, Offset, DdrCrDataControl0.Data);
+      }
+    }
+    //
+    // Program settings for SampOffset = -7
+    //
+    MrcWriteCrMulticast (MrcData, DDRDATA_CR_RXOFFSETVDQ_REG, 0x11111111); // (8-7)
+    for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+      if (!(MrcChannelExist (Outputs, Channel))) {
+        MRC_DEBUG_MSG (
+          Debug,
+          MSG_LEVEL_NOTE,
+          (Channel != 0) ? "" : ((Outputs->SdramCount == MAX_SDRAM_IN_DIMM) ? "                  " : "                ")
+          );
+      } else {
+        ChannelOut = &ControllerOut->Channel[Channel];
+
+        //
+        // Propagate delay values (without a read command)
+        //
+        DdrCrDataControl0.Data                      = ChannelOut->DqControl0.Data;
+        DdrCrDataControl0.Bits.ReadRFRd             = 1;
+        DdrCrDataControl0.Bits.ReadRFWr             = 0;
+        DdrCrDataControl0.Bits.ReadRFRank           = 0;
+        DdrCrDataControl0.Bits.ForceOdtOn           = 1;
+        DdrCrDataControl0.Bits.SenseampTrainingMode = 1;
+        Offset = DDRDATACH0_CR_DDRCRDATACONTROL0_REG +
+          ((DDRDATACH1_CR_DDRCRDATACONTROL0_REG - DDRDATACH0_CR_DDRCRDATACONTROL0_REG) * Channel);
+        MrcWriteCrMulticast (MrcData, Offset, DdrCrDataControl0.Data);
+
+        MrcWait (MrcData, HPET_1US);
+        for (byte = 0; byte < Outputs->SdramCount; byte++) {
+          Offset = DDRDATA0CH0_CR_DATATRAINFEEDBACK_REG +
+            ((DDRDATA0CH1_CR_DATATRAINFEEDBACK_REG - DDRDATA0CH0_CR_DATATRAINFEEDBACK_REG) * Channel) +
+            ((DDRDATA1CH0_CR_DATATRAINFEEDBACK_REG - DDRDATA0CH0_CR_DATATRAINFEEDBACK_REG) * byte);
+          DataTrainFeedback.Data = (U8) MrcReadCR (MrcData, Offset);
+          sumBits[Channel][byte] += MrcCountBitsEqOne (DataTrainFeedback.Bits.DataTrainFeedback);
+          HighMask[Channel][byte] |= DataTrainFeedback.Bits.DataTrainFeedback;
+
+          //
+          // Check if this point is better
+          //
+          if (sumBits[Channel][byte] > FirstBestPoint[Channel][byte]) {
+            FirstBestPoint[Channel][byte] = sumBits[Channel][byte];
+            LastBestPoint[Channel][byte]  = vref;
+            ChannelOut->RxVref[byte]      = vref;
+          } else if (sumBits[Channel][byte] == FirstBestPoint[Channel][byte]) {
+            LastBestPoint[Channel][byte] = vref;
+          }
+
+          MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%d ", sumBits[Channel][byte]);
+        }
+
+        DdrCrDataControl0.Bits.SenseampTrainingMode = 0;
+        Offset = DDRDATACH0_CR_DDRCRDATACONTROL0_REG +
+          ((DDRDATACH1_CR_DDRCRDATACONTROL0_REG - DDRDATACH0_CR_DDRCRDATACONTROL0_REG) * Channel);
+        MrcWriteCrMulticast (MrcData, Offset, DdrCrDataControl0.Data);
+      }
+    }
+  }
+
+#ifdef MRC_DEBUG_PRINT
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_ERROR, "\nHi-Lo\t");
+  for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+    if (MrcChannelExist (Outputs, Channel)) {
+      for (byte = 0; byte < Outputs->SdramCount; byte++) {
+        MRC_DEBUG_MSG (Debug, MSG_LEVEL_ERROR, "0x%x 0x%x ", HighMask[Channel][byte], LowMask[Channel][byte]);
+        //
+        // Exit with error if any bit did not change
+        //
+        if ((HighMask[Channel][byte] ^ LowMask[Channel][byte]) != 0xFF) {
+          MRC_DEBUG_MSG (
+            Debug,
+            MSG_LEVEL_ERROR,
+            "\nERROR! At least one bit with unexpected results for Channel %u Byte %u\n",
+            Channel,
+            byte
+            );
+          MRC_DEBUG_MSG (
+            Debug,
+            MSG_LEVEL_ERROR,
+            "A '0' in the following BitMask value represents the failing Bit(s) 0x%x\n",
+            (HighMask[Channel][byte] ^ LowMask[Channel][byte])
+            );
+          return mrcSenseAmpErr;
+        }
+      }
+    }
+  }
+
+  //
+  // Display the selected Read Vref per byte
+  //
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\nRdVref\t");
+#endif // MRC_DEBUG_PRINT
+  //
+  // Clear RdV offset
+  //
+  Status = ChangeMargin (MrcData, RdV, 0, 0, 1, 0, 0, 0, 0, 0, 0, MrcRegFileRank);
+
+  for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+    if (MrcChannelExist (Outputs, Channel)) {
+      ChannelOut = &ControllerOut->Channel[Channel];
+      //
+      // Upate RxVref delay center
+      //
+      for (byte = 0; byte < Outputs->SdramCount; byte++) {
+        VrefWidth = (S8) (LastBestPoint[Channel][byte] - ChannelOut->RxVref[byte]);
+        vref      = (S8) (ChannelOut->RxVref[byte] + (VrefWidth / 2));
+
+        //
+        // Add 1 to Round Up and find the center
+        //
+        if (vref < 0) {
+          vref--;
+        } else {
+          vref++;
+        }
+        //
+        // step size for RxVref is about 7.8mv AND for RxVrefOffset is about 3.9mv
+        //
+        ChannelOut->RxVref[byte] = vref / 2;
+
+        for (Rank = 0; Rank < MAX_RANK_IN_CHANNEL; Rank++) {
+          if (MrcRankInChannelExist (MrcData, Rank, Channel)) {
+            UpdateRxT (MrcData, Channel, Rank, byte, 0xFF, 0);
+          }
+        }
+
+        MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%d ", (S8) ChannelOut->RxVref[byte]);
+      }
+    }
+  }
+  //
+  // init firstZero and lastOne to 0
+  //
+  MrcOemMemorySet ((U8 *) firstZero, 0, sizeof (firstZero));
+  MrcOemMemorySet ((U8 *) lastOne, 0, sizeof (lastOne));
+
+  MaxBits = MAX_BITS_FOR_OFFSET_TRAINING - 1;
+#ifdef ULT_FLAG
+  if (Lpddr) {
+    MaxBits++;  // for ULT offset training done for 8 bits + DQS bit
+  }
+#endif //ULT_FLAG
+
+#ifdef MRC_DEBUG_PRINT
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\n\nStage 2: SampOffset Training\n");
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Channel 0\t\t\t\t\t\t\t\t\t %s1\nByte    ", Lpddr ? "\t" : "");
+  for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+    for (byte = 0; byte < Outputs->SdramCount; byte++) {
+      MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%d        %s", byte, Lpddr ? " " : "");
+    }
+  }
+
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\nBits    ");
+  for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+    for (byte = 0; byte < Outputs->SdramCount; byte++) {
+      MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "01234567%s ", Lpddr ? "S" : "");
+    }
+  }
+
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\n SAmp");
+#endif // MRC_DEBUG_PRINT
+
+  for (sampOffset = 1; sampOffset <= 15; sampOffset++) {
+    //
+    // Display per Byte Feedback from REUT Registers
+    //
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\n% 5d\t", sampOffset);
+
+    //
+    // Program Offset and Propagate new value from RF
+    //
+    RxOffsetVdq.Data = 0;
+    for (bit = 0; bit < MAX_BITS; bit++) {
+      RxOffsetVdq.Data += (sampOffset & DDRDATA_CR_RXOFFSETVDQ_Lane0_MSK) << (DDRDATA_CR_RXOFFSETVDQ_Lane0_WID * bit);
+    }
+
+    MrcWriteCrMulticast (MrcData, DDRDATA_CR_RXOFFSETVDQ_REG, RxOffsetVdq.Data);
+
+    for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+      if (!MrcChannelExist (Outputs, Channel)) {
+        MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\t\t\t\t\t\t\t\t\t%s", Lpddr ? "\t" : "");
+        continue;
+      }
+
+      ChannelOut = &ControllerOut->Channel[Channel];
+#ifdef ULT_FLAG
+      if (Lpddr) {
+        //
+        // write DQS offset to control2 reg sampOffset
+        //
+        for (byte = 0; byte < Outputs->SdramCount; byte++) {
+          DdrCrDataControl2.Data                = ChannelOut->DqControl2[byte].Data;
+
+          DdrCrDataControl2.Bits.RxDqsAmpOffset = sampOffset;
+          DdrCrDataControl2.Bits.ForceBiasOn    = 1;
+          DdrCrDataControl2.Bits.ForceRxOn      = 1;
+          DdrCrDataControl2.Bits.LeakerComp     = 0;
+
+          Offset = DDRDATA0CH0_CR_DDRCRDATACONTROL2_REG +
+            ((DDRDATA0CH1_CR_DDRCRDATACONTROL2_REG - DDRDATA0CH0_CR_DDRCRDATACONTROL2_REG) * Channel) +
+              ((DDRDATA1CH0_CR_DDRCRDATACONTROL2_REG - DDRDATA0CH0_CR_DDRCRDATACONTROL2_REG) * byte);
+          MrcWriteCR (MrcData, Offset, DdrCrDataControl2.Data);
+        }
+      }
+#endif //ULT_FLAG
+      //
+      // Propagate delay values (without a read command)
+      //
+      DdrCrDataControl0.Data                      = ChannelOut->DqControl0.Data;
+      DdrCrDataControl0.Bits.ReadRFRd             = 1;
+      DdrCrDataControl0.Bits.ReadRFWr             = 0;
+      DdrCrDataControl0.Bits.ReadRFRank           = 0;
+      DdrCrDataControl0.Bits.ForceOdtOn           = 1;
+      DdrCrDataControl0.Bits.SenseampTrainingMode = 1;
+      Offset = DDRDATACH0_CR_DDRCRDATACONTROL0_REG +
+        ((DDRDATACH1_CR_DDRCRDATACONTROL0_REG - DDRDATACH0_CR_DDRCRDATACONTROL0_REG) * Channel);
+      MrcWriteCrMulticast (MrcData, Offset, DdrCrDataControl0.Data);
+
+      MrcWait (MrcData, HPET_1US);
+
+      for (byte = 0; byte < Outputs->SdramCount; byte++) {
+        Offset = DDRDATA0CH0_CR_DATATRAINFEEDBACK_REG +
+          ((DDRDATA0CH1_CR_DATATRAINFEEDBACK_REG - DDRDATA0CH0_CR_DATATRAINFEEDBACK_REG) * Channel) +
+          ((DDRDATA1CH0_CR_DATATRAINFEEDBACK_REG - DDRDATA0CH0_CR_DATATRAINFEEDBACK_REG) * byte);
+        DataTrainFeedback.Data = MrcReadCR (MrcData, Offset);
+        //MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "DataTrainFeedback = 0x%x, sampOffset = %d\n", DataTrainFeedback.Data, sampOffset);
+
+        for (bit = 0; bit < MaxBits; bit++) {
+          if (DataTrainFeedback.Bits.DataTrainFeedback & (MRC_BIT0 << bit)) {
+            lastOne[Channel][byte][bit] = sampOffset;
+          } else {
+            if (firstZero[Channel][byte][bit] == 0) {
+              firstZero[Channel][byte][bit] = sampOffset;
+            }
+          }
+          //
+          // Display in bits
+          //
+          MRC_DEBUG_MSG (
+            Debug,
+            MSG_LEVEL_NOTE,
+            ((MRC_BIT0 << bit) & DataTrainFeedback.Bits.DataTrainFeedback) ? "1" : "0"
+            );
+        }
+
+        MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, " ");
+      }
+
+      DdrCrDataControl0.Bits.SenseampTrainingMode = 0;
+      Offset = DDRDATACH0_CR_DDRCRDATACONTROL0_REG +
+        ((DDRDATACH1_CR_DDRCRDATACONTROL0_REG - DDRDATACH0_CR_DDRCRDATACONTROL0_REG) * Channel);
+      MrcWriteCrMulticast (MrcData, Offset, DdrCrDataControl0.Data);
+    } // for Channel
+  } // for sampOffset
+
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\nBitSAmp ");
+
+  //
+  // Calculate and Program Offsets and display per bit SenseAmp Offset
+  //
+  for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+    if (MrcChannelExist (Outputs, Channel)) {
+      ChannelOut = &ControllerOut->Channel[Channel];
+      for (byte = 0; byte < Outputs->SdramCount; byte++) {
+        RxOffsetVdq.Data = 0;
+        for (bit = 0; bit < MaxBits; bit++) {
+          //
+          // Find vref center, add 1 for Round Up
+          //
+          vref = (firstZero[Channel][byte][bit] + lastOne[Channel][byte][bit]) / 2;
+
+          //
+          // Check for saturation conditions
+          // to make sure we are as close as possible to vdd/2 (750mv)
+          //
+          if (firstZero[Channel][byte][bit] == 0) {
+            vref = 15;
+          }
+
+          if (lastOne[Channel][byte][bit] == 0) {
+            vref = 0;
+          }
+
+          MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%X", vref);
+#ifdef ULT_FLAG
+          if (Lpddr) {
+            if (bit == 8) {
+              //
+              // Write the DQS sense amp offset value to the host struct.
+              // It will be written to the HW at the end of this routine.
+              //
+              // Add 8 to the center value, to better suppress DQS reflections before the read preamble.
+              //
+              ChannelOut->DqControl2[byte].Bits.RxDqsAmpOffset = MIN (vref + 8, DDRDATA_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_MAX);
+              break;
+            }
+          }
+#endif   // ULT_FLAG
+
+          RxOffsetVdq.Data += (vref & DDRDATA0CH0_CR_RXOFFSETVDQ_Lane0_MSK) << (DDRDATA0CH0_CR_RXOFFSETVDQ_Lane0_WID * bit);
+          ChannelOut->RxDqVrefPb[0][byte][bit].Center = vref;
+        }
+
+        Offset = DDRDATA0CH0_CR_RXOFFSETVDQ_REG +
+          ((DDRDATA0CH1_CR_RXOFFSETVDQ_REG - DDRDATA0CH0_CR_RXOFFSETVDQ_REG) * Channel) +
+          ((DDRDATA1CH0_CR_RXOFFSETVDQ_REG - DDRDATA0CH0_CR_RXOFFSETVDQ_REG) * byte);
+        MrcWriteCR (MrcData, Offset, RxOffsetVdq.Data);
+        MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, " ");
+
+        //
+        // Propagate delay values (without a read command)
+        //
+        MrcDownloadRegFile (MrcData, Channel, 1, 0, MrcRegFileRank, 0, 1, 0);
+      }
+    }
+#ifdef MRC_DEBUG_PRINT
+    else {
+      MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\t\t\t\t\t\t\t\t\t%s", Lpddr ? "\t" : ""); // Line up Channel 1
+    }
+#endif
+  }
+  //
+  // Clean up after test
+  //
+  for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+    if (MrcChannelExist (Outputs, Channel)) {
+      ChannelOut = &ControllerOut->Channel[Channel];
+
+      //
+      // Restore DataControl2
+      //
+      for (byte = 0; byte < Outputs->SdramCount; byte++) {
+        Offset = DDRDATA0CH0_CR_DDRCRDATACONTROL2_REG +
+          ((DDRDATA0CH1_CR_DDRCRDATACONTROL2_REG - DDRDATA0CH0_CR_DDRCRDATACONTROL2_REG) * Channel) +
+          ((DDRDATA1CH0_CR_DDRCRDATACONTROL2_REG - DDRDATA0CH0_CR_DDRCRDATACONTROL2_REG) * byte);
+        MrcWriteCR (MrcData, Offset, ChannelOut->DqControl2[byte].Data);
+      }
+      //
+      // Restore DataControl0
+      //
+      Offset = DDRDATACH0_CR_DDRCRDATACONTROL0_REG +
+        ((DDRDATACH1_CR_DDRCRDATACONTROL0_REG - DDRDATACH0_CR_DDRCRDATACONTROL0_REG) * Channel);
+      MrcWriteCrMulticast (MrcData, Offset, ChannelOut->DqControl0.Data);
+    }
+  }
+
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\n");
+
+  Status = IoReset (MrcData);
+
+  return Status;
+}
+
+/**
+  This function looks at the margin values stored in the global data structure and checks
+  WrT, WrV, RdT, and RdV to see if they are above the minimum margin required.
+
+  @param[in, out] MrcData - MRC global data.
+
+  @retval mrcSuccess if margins are acceptable.
+  @retval Otherwise, mrcRetrain.
+**/
+MrcStatus
+MrcRetrainMarginCheck (
+  IN OUT MrcParameters *const MrcData
+  )
+{
+  MrcDebug const          *Debug;
+  MrcOutput               *Outputs;
+  MrcControllerOut        *ControllerOut;
+  MrcUpmPwrRetrainLimits  *UpmPwrRetrainLimits;
+  MRC_MarginTypes         MarginParam;
+  MrcMarginResult         LastResultParam;
+  MrcStatus               Status;
+  MRC_MARGIN_LIMIT_TYPE   MarginLimitType;
+  U32                     (*LastMargins)[MAX_RANK_IN_CHANNEL][MAX_CHANNEL][MAX_SDRAM_IN_DIMM][MAX_EDGES];
+  U32                     BERStats[4];
+  U16                     MinEdgeMargin[MAX_EDGES];
+  U16                     RetrainMarginLimit;
+  U16                     CurrentMargin;
+  U8                      Channel;
+  U8                      ChannelMask;
+  U8                      Rank;
+  U8                      RankMask;
+  U8                      Edge;
+  U8                      Loopcount;
+  U8                      MaxMargin;
+  BOOL                    RdWrMarginFail[2];
+
+  Debug               = &MrcData->SysIn.Inputs.Debug;
+  Outputs             = &MrcData->SysOut.Outputs;
+  ControllerOut       = &Outputs->Controller[0];
+  LastMargins         = Outputs->MarginResult;
+  UpmPwrRetrainLimits = Outputs->UpmPwrRetrainLimits.Pointer;
+  Status              = mrcSuccess;
+  Loopcount           = 17;
+  MrcOemMemorySet ((U8 *) BERStats, 0, sizeof (BERStats));
+  RdWrMarginFail[0] = FALSE;
+  RdWrMarginFail[1] = FALSE;
+
+
+  //
+  // Loop is dependent on the order of MRC_MarginTypes.  If this changes, pleas ensure functionality
+  // stays the same.
+  //
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Loopcount: %d\n", Loopcount);
+  SetupIOTestBasicVA (MrcData, Outputs->ValidChBitMask, Loopcount, NSOE, 0, 0, 8);
+  for (Rank = 0; Rank < MAX_RANK_IN_CHANNEL; Rank++) {
+    RankMask    = 1 << Rank;
+    ChannelMask = 0;
+    for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+      ChannelMask |= SelectReutRanks (MrcData, Channel, RankMask, 0);
+      if ((1 << Channel) & ChannelMask) {
+        MrcOemMemorySetDword (&ControllerOut->Channel[Channel].DataOffsetTrain[0], 0, Outputs->SdramCount);
+      }
+    }
+
+    if (ChannelMask == 0) {
+      continue;
+    }
+
+    for (MarginParam = RdT; MarginParam <= WrV; MarginParam++) {
+      if (MarginParam == WrDqsT) {
+        continue;
+      }
+
+      if (MarginParam == RdT) {
+        Outputs->DQPat = RdRdTA;
+      } else if (MarginParam == RdV) {
+        Outputs->DQPat = BasicVA;
+      }
+
+      MaxMargin = ((MarginParam == RdV) || (MarginParam == WrV)) ? MAX_POSSIBLE_VREF : MAX_POSSIBLE_TIME;
+
+      Status = MrcGetBERMarginCh (
+        MrcData,
+        LastMargins,
+        ChannelMask,
+        0xFF,
+        Rank,
+        MarginParam,
+        0,
+        1,
+        MaxMargin,
+        0,
+        BERStats
+        );
+    }
+  }
+
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Margins\nParams: RdT\tWrT\tRdV\tWrV\n\tLft Rgt Lft Rgt Low Hi  Low Hi");
+  for (Rank = 0; Rank < MAX_RANK_IN_CHANNEL; Rank++) {
+    for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+      if (!MrcRankInChannelExist (MrcData, Rank, Channel)) {
+        continue;
+      }
+
+      MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\nC%dR%d\t", Channel, Rank);
+      for (MarginParam = RdT; MarginParam <= WrV; MarginParam++) {
+        if (MarginParam == WrDqsT) {
+          continue;
+        }
+
+        LastResultParam     = GetMarginResultType (MarginParam);
+        RetrainMarginLimit  = UpmPwrLimitValue (MrcData, MarginParam, RetrainLimit) / 10;
+        MrcOemMemorySetWord (MinEdgeMargin, (U16) (~0), MAX_EDGES);
+
+
+        for (Edge = 0; Edge < MAX_EDGES; Edge++) {
+          CurrentMargin       = (U16) LastMargins[LastResultParam][Rank][Channel][0][Edge] / 10;
+          MinEdgeMargin[Edge] = MIN (MinEdgeMargin[Edge], CurrentMargin);
+          if ((CurrentMargin <= RetrainMarginLimit)) {
+            Status =  mrcRetrain;
+            if ((MarginParam == RdT) || (MarginParam == RdV)) {
+              RdWrMarginFail[0] = TRUE;
+            } else if ((MarginParam == WrT) || (MarginParam == WrV)) {
+              RdWrMarginFail[1] = TRUE;
+            }
+          }
+        }
+        MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%2d  %2d\t", MinEdgeMargin[0], MinEdgeMargin[1]);
+        if ((RdWrMarginFail[0] == TRUE) && (RdWrMarginFail[1] == TRUE)) {
+          Rank    = MAX_RANK_IN_CHANNEL;
+          Channel = MAX_CHANNEL;
+          break;
+        }
+      }
+    }
+  }
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\n");  // End of table
+
+  if (Status == mrcRetrain) {
+    //
+    // Loop is dependent on the order of MRC_MarginTypes.  If this changes, please ensure functionality
+    // stays the same.
+    //
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "*** Margin Limit Check Failed! ***\nNew Limits:\nParam\tUPM\tPWR");
+    for (MarginParam = RdT; MarginParam <= WrV; MarginParam++) {
+      if (((RdWrMarginFail[0] == FALSE) && ((MarginParam == RdT) || (MarginParam == RdV))) ||
+          ((RdWrMarginFail[1] == FALSE) && ((MarginParam == WrT) || (MarginParam == WrV))) ||
+          (MarginParam == WrDqsT)) {
+        continue;
+      }
+      MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\n%s", MarginTypesString[MarginParam]);
+      for (MarginLimitType = UpmLimit; MarginLimitType < RetrainLimit; MarginLimitType++) {
+        RetrainMarginLimit = MrcUpdateUpmPwrLimits (MrcData, MarginParam, MarginLimitType, MRC_UPM_PWR_INC_VAL);
+        MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\t%d", RetrainMarginLimit);
+      }
+    }
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\n");  // End of table.
+  }
+
+  return Status;
+}
+
+
+/**
+  This function implements DIMM ODT training.
+  Adjust DIMM RTT_NOM/RTT_WR value to maximize read/write voltage/timing
+
+  RdOdtPriority Needs to be an input parameter
+  option to prioritize the ReadODT setting and attempt to optimize that value first,
+  reducing CPU TDP power (as opposed to system power for the DRAM).
+  For this case, the base value for ReadODT is changed at the compensation block
+  by looking at the following values:
+     RdOdt Global: (50, 64, 84, 110)
+
+  In the case of 2 dpc, the flow will first optimizing RttNom, while keeping RttWr fixed
+  at 60 Ohms (60 Ohms usually gives the best results).  It will then try to reduce RttWr
+  to 120 Ohms if possible.
+
+  In the case of 1 dpc, only RttNom is used and only a single pass is required.
+  However, it is important to note that the two channels are completely independent
+  and can have different numbers of dimms populated.
+
+  @param[in] MrcData         - Include all MRC global data.
+
+  @retval MrcStatus      - if it succeed return mrcSuccess
+**/
+MrcStatus
+MrcDimmODTTraining (
+  IN MrcParameters *const MrcData
+  )
+{
+  const MrcDebug    *Debug;
+  const MrcInput    *Inputs;
+  MrcOutput         *Outputs;
+  MrcControllerOut  *ControllerOut;
+  MrcChannelOut     *ChannelOut;
+  MrcStatus         Status;
+  U8                Channel;
+  U8                byte;
+  U32               NumBytes;
+  U8                NumCh;
+  U8                RankMask;
+  U8                LocalRanks[MAX_CHANNEL];
+  U8                ChMask;
+  U8                RttNomPoints;
+  U8                RdOdtPoints;
+  S8                GRdOdt;
+  U8                RttWr0;
+  U8                Dimm;
+  U8                RttWr[MAX_CHANNEL][MAX_DIMMS_IN_CHANNEL];
+  U8                RttNom[MAX_CHANNEL][MAX_DIMMS_IN_CHANNEL];
+  S8                RttNom0;
+  S8                RttNom1;
+  U8                BestRttNom[MAX_CHANNEL][MAX_DIMMS_IN_CHANNEL];
+  U8                BestRttWr[MAX_CHANNEL][MAX_DIMMS_IN_CHANNEL];
+  S8                BestRdOdt[MAX_CHANNEL];
+  U8                offset;
+  U8                test;
+  U8                *TestList;
+  U8                TestListSize;
+  S32               RdOdtCodes[2]; // Store Comp Codes associated with each RdOdt
+  S8                RttNom1Off;
+  BOOL              any2DPC;
+  BOOL              any1DPC;
+  BOOL              Lpddr;
+  S8                BestGRdOdt;
+  U8                RttOffset;
+  U8                OffsetPoints;
+  U8                loopcount; // for centering
+  S8                GRdOdtStep;
+  BOOL              IncEnds;
+  BOOL              SubPwrLimits;
+  BOOL              skipSubOpt;
+  BOOL              skipOptPrint;
+  BOOL              ReCenterPoints;
+  U8                TestListTradRd[] = { OptRxBias };
+  U8                TestListWr[]  = { OptWrDS, OptTxEq };
+  U8                TestListRdWr[] = { OptRxBias, OptWrDS, OptTxEq };
+  U8                ScaleTest[] = { 1, 1, 1, 1, 1 }; // must specify scale=0 to unpopulated slots !!
+  U8                ScaleTest1DPC[] = { 1, 1, 1, 0, 0 }; // must specify scale=0 to unpopulated slots !!
+  U8                *Scale;
+  U16               PwrLimits[] = { 3000, 3000, 0, 0, 0 };
+  S16               Best;
+  DimmOptPoint      DimmOptPoints[MaxOptOff];
+  U16               Points2calc[5][MaxOptOff];
+  U8                PWRTrendSlope2D;
+  U8                NumTests;
+  U8                ArrayLength;
+  U8                localChMask;
+  U8                OdtTrainingDimmMask;
+  S32               OdtOff;
+  BOOL              ForceCenter;
+  S8                GRdOdtOff;
+  U32               BestGRdOdtCode;
+  S8                Average;
+  OptResultsPerByte BestOff;
+#ifdef ULT_FLAG
+  U8                TestListUltRd[]  = { OptRxBias, OptRxEq };
+  BOOL              UltCpu;
+#endif
+
+  Inputs              = &MrcData->SysIn.Inputs;
+  Debug               = &Inputs->Debug;
+  Outputs             = &MrcData->SysOut.Outputs;
+  ControllerOut       = &Outputs->Controller[0];
+  Status              = mrcSuccess;
+  loopcount           = 15;
+  GRdOdtStep          = 16;
+  IncEnds             = 1;
+  SubPwrLimits        = 0;
+  skipSubOpt          = 0;
+  skipOptPrint        = 1;
+  ReCenterPoints      = 0;
+  NumTests            = 5;
+  OdtTrainingDimmMask = 0;
+  PWRTrendSlope2D     = 65;
+  NumBytes            = Outputs->SdramCount;
+  ArrayLength         = sizeof (Points2calc) / sizeof (U16) / NumTests;
+#ifdef ULT_FLAG
+  UltCpu             = (Inputs->CpuModel == cmHSW_ULT);
+#endif
+
+  //
+  // Check if LPDDR3 memory is used
+  //
+  Lpddr = (Outputs->DdrType == MRC_DDR_TYPE_LPDDR3);
+
+  MrcOemMemorySet ((U8 *) &BestOff, 0, sizeof (BestOff));
+  MrcOemMemorySet ((U8 *) DimmOptPoints, 0, sizeof (DimmOptPoints));
+  MrcOemMemorySet ((U8 *) Points2calc, 0, sizeof (Points2calc));
+  MrcOemMemorySet ((U8 *) LocalRanks, 0, sizeof (LocalRanks));
+  MrcOemMemorySet ((U8 *) RdOdtCodes, 0, sizeof (RdOdtCodes));
+
+  TestList      = TestListRdWr;
+  TestListSize  = sizeof (TestListRdWr);
+  Scale         = ScaleTest;
+
+  //
+  // GOdt : [150,110, 84, 64, 50]
+  // 1 dpc: Search [Off, 120, 60]
+  // 2 dpc: Search [120, 60, 40]
+  //      Dimm0/1 = [40/40, 40/30, 30/40, 30/30, 30/20, 20/30, 20/20]
+  //
+  ChMask    = 0x3;
+  RankMask  = 0xf;
+
+  //
+  // Possible RttNom values to pick
+  //
+#ifdef ULT_FLAG
+  if (UltCpu) {
+    RttOffset = 0; //In ULT no Rtt nom by definition
+  } else
+#endif
+  {
+    RttOffset   = 1;
+  }
+  RttNomPoints  = 2;  //[120, 60]
+  RdOdtPoints   = 2;  //[150,110]
+  ChMask &= Outputs->ValidChBitMask;
+  RankMask &= Outputs->ValidRankMask;
+
+  any2DPC = FALSE;
+  any1DPC = FALSE;
+  //
+  // set channel and rank population
+  //
+  for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+    if (!((MRC_BIT0 << Channel) & ChMask)) {
+      continue;
+    }
+
+    ChannelOut = &ControllerOut->Channel[Channel];
+    //
+    // Setup Dimm Masks for CalcPowerTrend so we don't access a Dimm that isn't present.
+    //
+    if (ChannelOut->DimmCount == 2) {
+      any2DPC |= 1;
+      OdtTrainingDimmMask |= 0x3 << (DIMM_ODT_DIMM_MASK_SHIFT * Channel);
+    } else {
+      any1DPC |= 1;
+      OdtTrainingDimmMask |= 0x1 << (DIMM_ODT_DIMM_MASK_SHIFT * Channel);
+    }
+
+    LocalRanks[Channel] = RankMask & ChannelOut->ValidRankBitMask;
+    for (Dimm = 0; Dimm < MAX_DIMMS_IN_CHANNEL; Dimm++) {
+      //
+      // start with 60 Ohm by default
+      //
+#ifdef ULT_FLAG
+      if (MrcData->SysOut.Outputs.DdrType == MRC_DDR_TYPE_LPDDR3) {
+        RttWr[Channel][Dimm] = 0;
+      } else
+#endif
+      {
+        RttWr[Channel][Dimm] = 2;
+      }
+    }
+  }
+
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "apply 2DPC optimization to ChMask %d\n", ChMask);
+
+  //
+  // *** Read flow ***
+  // if both ch 1DPC RttNomPoints=1 and RttNom1Off=0 i.e. only GRdOdt loop
+  //
+  if (any2DPC == 0) {
+    //
+    // if no 2DPC ch
+    //
+    RttNomPoints  = 1;
+#ifdef ULT_FLAG
+    if (UltCpu && Inputs->TrainingEnables.RDEQT) {
+      TestList      = TestListUltRd;
+      TestListSize  = sizeof (TestListUltRd);
+    } else
+#endif
+    {
+      TestList      = TestListTradRd;
+      TestListSize  = sizeof (TestListTradRd);
+    }
+    Scale         = ScaleTest1DPC;
+  }
+
+  OffsetPoints = 0;
+  //
+  // Walk Through RttNOM Settings - going from negative to positive
+  //
+  for (GRdOdt = 0; GRdOdt < RdOdtPoints; GRdOdt++) {
+    GRdOdtOff = -16 + GRdOdt * GRdOdtStep;
+    //
+    // MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "CalcRdOdt = %d, GRdOdt = %d GRdOdtOff=%d\n",CalcRdOdt(GRdOdt),GRdOdt,GRdOdtOff);
+    //
+    for (RttNom0 = RttOffset; RttNom0 < (RttNomPoints + RttOffset); RttNom0++) {
+      //
+      // Dimm0 RttNom Value
+      //
+      for (RttNom1Off = -1; RttNom1Off < 2; RttNom1Off++) {
+        //
+        // Dimm1 RttNom Value
+        // Calculate RttNom1 and check if out of range
+        //
+        RttNom1 = RttNom0 + RttNom1Off;
+        //
+        // MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "RttNom0 = %d, RttNom1 = %d, RttNom1Off = %d\n",RttNom0,RttNom1,RttNom1Off);
+        //
+        if ((RttNom1 == (RttNomPoints + RttOffset)) || (RttNom1 < RttOffset)) {
+          continue;
+        }
+        //
+        // if RttNom == 120ohm run recenter timing
+        //
+        if (((RttNom0 == 1) || (RttNom1 == 1)) && (any2DPC)) {
+          ForceCenter = 1;
+        } else {
+          ForceCenter = 0;
+        }
+
+        for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+          //
+          // set default opt params offset
+          //
+          if (!((MRC_BIT0 << Channel) & ChMask)) {
+            continue; // check if the ch exist
+          }
+
+          RttNom[Channel][0]  = RttNom0;
+          RttNom[Channel][1]  = RttNom1;
+          for (byte = 0; byte < NumBytes; byte++) {
+            UpdateOptParamOffset (MrcData, Channel, 0, byte, OptWrDS, 0, 1);
+            UpdateOptParamOffset (
+              MrcData,
+              Channel,
+              LocalRanks[Channel],
+              byte,
+              OptTxEq,
+              (S16) (3 * (TXEQFULLDRV >> 4) + 3),
+              1
+              );
+          }
+        }
+        //
+        // Apply new settings and optimize various parameters
+        // MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "TrainDimmOdtSetting:  GRdOdt = %d, RdOdtOff = %d, RttNom0= %d, RttNom1= %d \n",GRdOdt,RdOdtOffsets[GRdOdt], RttNom0, RttNom1);
+        //
+        if (OffsetPoints < MaxOptOff) {
+          TrainDimmOdtSetting (
+            MrcData,
+            &DimmOptPoints[OffsetPoints],
+            ChMask,
+            RankMask,
+            0,
+            RttNom,
+            RttWr,
+            GRdOdtOff,
+            TestList,
+            TestListSize,
+            SubPwrLimits,
+            skipSubOpt,
+            skipOptPrint,
+            ReCenterPoints | ForceCenter,
+            ReCenterPoints,
+            Points2calc,
+            ArrayLength,
+            OffsetPoints
+            );
+          OffsetPoints++;
+        } else {
+          MRC_DEBUG_MSG (
+            Debug,
+            MSG_LEVEL_NOTE,
+            "Error: DimmOptPoints array out of bounds! %d > %d\n",
+            OffsetPoints,
+            MaxOptOff - 1
+            );
+        }
+      }
+    }
+  }
+  //
+  // for each channel apply Power Trend and find best point
+  //
+  for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+    BestRdOdt[Channel] = 0;
+    if (!((MRC_BIT0 << Channel) & ChMask)) {
+      continue; // check if the ch exist in this ch
+    }
+
+    for (offset = 0; offset < OffsetPoints; offset++) {
+      //
+      // copy point for the FindOptTradeOff routing
+      //
+      for (test = 0; test < (DimmOptPoints->NumTests); test++) {
+        Points2calc[test][offset] = DimmOptPoints[offset].Points2Trade[test][Channel];
+        //
+        // MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "read channel=%d Points2calc[test=%d][offset=%d]=%d\n",Channel,test,offset,Points2calc[test][offset]);
+        //
+      }
+    }
+    //
+    // MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "FindOptimalTradeOff read\n");
+    // LenMargin,TestList,TestListSize,noPwrCalc
+    //
+    CalcPowerTrend (
+      MrcData,
+      Channel,
+      (OdtTrainingDimmMask >> (DIMM_ODT_DIMM_MASK_SHIFT * Channel)),
+      DimmOptPoints,
+      Points2calc,
+      MaxOptOff,
+      OffsetPoints,
+      DimmOptPoints->TestList,
+      Scale,
+      DimmOptPoints->NumTests,
+      0,
+      PWRTrendSlope2D
+      );
+    //
+    // senSq=0,AveN=1,caleM=1,powerOpHigh=0
+    //
+    FindOptimalTradeOff (
+      MrcData,
+      &BestOff,
+      Points2calc,
+      ArrayLength,
+      OffsetPoints,
+      Scale,
+      0,
+      1,
+      IncEnds,
+      1,
+      PwrLimits,
+      0,
+      0           // GuardBand
+      );
+    Best = BestOff.Best + BestOff.GuardBand;
+    UpdateOdtsValues (
+      MrcData,
+      MRC_BIT0 << Channel,
+      &DimmOptPoints[Best],
+      0,
+      0,
+      skipSubOpt,
+      1
+      );
+    //
+    // MrcWait (MrcData, 10 * HPET_1MS);
+    // MrcResetSequence (MrcData);
+    //
+    for (Dimm = 0; Dimm < MAX_DIMMS_IN_CHANNEL; Dimm++) {
+      BestRttNom[Channel][Dimm]  = DimmOptPoints[Best].ODTSet.RttNom[Channel][Dimm];
+    }
+
+    BestRdOdt[Channel]  = DimmOptPoints[Best].ODTSet.GRdOdt;
+    RdOdtCodes[Channel] = DimmOptPoints[Best].ODTSet.GRdOdtCode;
+
+#ifdef MRC_DEBUG_PRINT
+    //
+    // printing the results
+    //
+    PrintODTResultTable (
+      MrcData,
+      &BestOff,
+      DimmOptPoints,
+      OffsetPoints,
+      0,
+      1,
+      OptDimmOdt,
+      Channel,
+      LocalRanks[Channel],
+      1,
+      0,
+      1
+      );
+    //
+    // PrintODTResultTable(*MrcData,calcResultSummary,*TestList,NumTest,NumOffsets,MidPoint,IncEnds,OptParam,Channel,Ranks,TrendLine,Nibble,perCh);
+    //
+#endif // MRC_DEBUG_PRINT
+  } // end ch loop
+  //
+  // Find Best "Average" value for Global RdOdt Offset
+  //
+  NumCh   = 0;
+  Average = 0;
+  for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+    if (!((MRC_BIT0 << Channel) & ChMask)) {
+      continue;
+    }
+
+    NumCh += 1;
+    Average += BestRdOdt[Channel];
+    //
+    // RdOdtChOffset[Channel] = RdOdtCodes[BestRdOdt[Channel]]; //set comp code associated comp offset per ch
+    //
+  }
+
+  BestGRdOdt      = (NumCh != 0) ? (Average / NumCh) : Average;
+  //
+  // update average rdOdt offset (both ch)
+  //
+  BestGRdOdtCode  = UpdateCompGlobalOffset (MrcData, RdOdt, (U8) BestGRdOdt, 1);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_ERROR, "Calculated Average (both ch) GRdOdt is %d\n", BestGRdOdt);
+
+  if (NumCh > 1) {
+    //
+    // adjust RdOdt to per channel/byte
+    //
+    for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+      if (!((MRC_BIT0 << Channel) & ChMask)) {
+        continue;
+      }
+
+      RdOdtCodes[Channel] -= BestGRdOdtCode;
+      for (byte = 0; byte < Outputs->SdramCount; byte++) {
+        //
+        // Apply Best RdOdt in case we didnt run Godt.
+        //
+        OdtOff = RdOdtCodes[Channel] + ((Outputs->Controller[0].Channel[Channel].DataCompOffset[byte] >> 12) & 0x1f);
+        UpdateOptParamOffset (MrcData, Channel, 0xF, byte, OptRdOdt, (S16) OdtOff, 1);
+      }
+    }
+  }
+
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_ERROR, "Re-center Read Voltage\n");
+  Status = ReadVoltageCentering2D (
+             MrcData,
+             Outputs->MarginResult,
+             ChMask,
+             RdV,
+             0,
+             0,
+             loopcount,
+             0
+             );
+
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_ERROR, "Re-center Read Timing\n");
+  Status = DataTimeCentering2D (
+             MrcData,
+             Outputs->MarginResult, // prev. margin results
+             ChMask,
+             RdT,
+             0, // EnPerBit,
+             0, // EnRxDutyCycle
+             0, // ResetPerBit
+             loopcount,
+             0  // En2D
+             );
+  
+  if (!Lpddr) {
+    //
+    // DIMM ODT is disabled by default on LPDDR, so skip this section
+    //
+    
+    //
+    // *** Write flow ***//
+    //
+    RttOffset = (Inputs->MaxRttWr < 0x2) ? (Inputs->MaxRttWr) : (0x1); // Get user input for MaxRttWr, 0 = off, 1 = 120 ohms
+    if (any2DPC) {
+      //
+      // At least one 2DPC ch
+      //
+      if (!any1DPC) {
+        RttOffset = 1; // Start with 120ohm
+      }
+    }
+
+    TestList      = TestListWr;
+    TestListSize  = sizeof (TestListWr);
+    Scale         = ScaleTest1DPC;
+
+    //
+    // option 1: Keep RttWr the same for both DIMMs (ie: train per Ch for both RttWr & WrDrv)
+    // option 2: Allow different RttWr for each DIMM and break WrDrv out of this optimization (ie: do it later).
+    //
+    for (Dimm = 0; Dimm < MAX_DIMMS_IN_CHANNEL; Dimm++) {
+      //
+      // check if dimm exist in any channel
+      //
+      OdtTrainingDimmMask = (0x3 << (Dimm * 2));
+      if (!(Outputs->ValidRankMask & OdtTrainingDimmMask)) {
+        continue;
+      }
+  
+      localChMask = 0;
+      for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+        if (OdtTrainingDimmMask & LocalRanks[Channel]) {
+          localChMask |= MRC_BIT0 << Channel; // can run 1 or 2 ch
+        }
+      }
+  
+      localChMask &= ChMask;
+      MRC_DEBUG_MSG (Debug, MSG_LEVEL_ERROR, "write odt train localChMask=%x\n", localChMask);
+  
+      OffsetPoints = 0;
+      for (RttWr0 = RttOffset; RttWr0 < 3; RttWr0++) {
+        for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+          RttWr[Channel][Dimm] = RttWr0; // start with 60 Ohm by default
+          if (!((MRC_BIT0 << Channel) & localChMask)) {
+            continue; // skip if the ch doesn't exist
+          }
+        }
+  
+        if ((RttWr0 == 0) && (any1DPC)) {
+          ForceCenter = 1;
+        } else {
+          ForceCenter = 0;
+        }
+  
+        TrainDimmOdtSetting (
+          MrcData,
+          &DimmOptPoints[OffsetPoints],
+          localChMask,
+          OdtTrainingDimmMask,
+          1,
+          BestRttNom,
+          RttWr,
+          BestGRdOdt,
+          TestList,
+          TestListSize,
+          SubPwrLimits,
+          skipSubOpt,
+          skipOptPrint,
+          ReCenterPoints,
+          ReCenterPoints | ForceCenter,
+          Points2calc,
+          ArrayLength,
+          OffsetPoints
+          );
+        OffsetPoints++;
+      }
+      //
+      // for each channel apply Power Trend and find best point
+      //
+      for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+        if (!((MRC_BIT0 << Channel) & localChMask)) {
+          continue; // check if the ch exist
+        }
+  
+        for (offset = 0; offset < OffsetPoints; offset++) {
+          //
+          // copy point for the FindOptTradeOff routing
+          //
+          for (test = 0; test < (DimmOptPoints->NumTests); test++) {
+            Points2calc[test][offset] = DimmOptPoints[offset].Points2Trade[test][Channel];
+            //
+            // MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Write channel=%d Points2calc[test=%d][offset=%d]=%d\n",Channel,test,offset,Points2calc[test][offset]);
+            //
+          }
+        }
+        //
+        // MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "FindOptimalTradeOff write\n");
+        // LenMargin,TestList,TestListSize,noPwrCalc
+        //
+        CalcPowerTrend (
+          MrcData,
+          Channel,
+          MRC_BIT0 << Dimm,
+          DimmOptPoints,
+          Points2calc,
+          MaxOptOff,
+          OffsetPoints,
+          DimmOptPoints->TestList,
+          Scale,
+          DimmOptPoints->NumTests,
+          0,
+          PWRTrendSlope2D
+          );
+        //
+        // senSq=0,AveN=1,caleM=1,powerOpHigh=0
+        //
+        FindOptimalTradeOff (
+          MrcData,
+          &BestOff,
+          Points2calc,
+          ArrayLength,
+          OffsetPoints,
+          Scale,
+          0,
+          1,
+          IncEnds,
+          1,
+          PwrLimits,
+          0,
+          0               // GuardBand
+          );
+        Best = BestOff.Best + BestOff.GuardBand;
+        //
+        // MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "===============> BestOff=%d\n",BestOff.Best);
+        // skipGRdOdt=1 SkipDimmOdts=0, SkipBestOffsets,updateHost
+        //
+        UpdateOdtsValues (MrcData, MRC_BIT0 << Channel, &DimmOptPoints[Best], 1, 0, skipSubOpt, 1);
+        RttWr[Channel][Dimm]      = DimmOptPoints[Best].ODTSet.RttWr[Channel][Dimm];
+        BestRttWr[Channel][Dimm]  = DimmOptPoints[Best].ODTSet.RttWr[Channel][Dimm]; // delete?
+  #ifdef MRC_DEBUG_PRINT // printing the results
+        PrintODTResultTable (
+          MrcData,
+          &BestOff,
+          DimmOptPoints,
+          OffsetPoints,
+          0,
+          1,
+          OptDimmOdtWr,
+          Channel,
+          OdtTrainingDimmMask,
+          1,
+          0,
+          1
+          );
+        //
+        // PrintODTResultTable(*MrcData,calcResultSummary,*TestList,NumTest,NumOffsets,MidPoint,IncEnds,OptParam,Channel,Ranks,TrendLine,Nibble,perCh);
+        //
+  #endif // MRC_DEBUG_PRINT
+      } // end of channel loop
+    } // end dimm loop
+    //
+    //set equal TxEq for all bytes  before DS
+    //
+    for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+      if (!((MRC_BIT0 << Channel) & Outputs->ValidChBitMask)) {
+        continue; // skip if the ch doesn't exist
+      }
+  
+      for (byte = 0; byte < NumBytes; byte++) {
+        UpdateOptParamOffset (
+          MrcData,
+          Channel,
+          LocalRanks[Channel],
+          byte,
+          OptTxEq,
+          (S16) (3 * (TXEQFULLDRV >> 4) + 3),
+          1
+          );
+      }
+    }
+  } // if (!Lpddr)
+  
+  //
+  // run WriteDS
+  //
+  Status = TrainWriteDriveStrength (MrcData, Outputs->ValidChBitMask, 0, OPT_PARAM_1D_LC, 0);
+
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_ERROR, "Re-center Write Vref\n");
+  Status = MrcWriteVoltageCentering2D (MrcData);
+
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_ERROR, "Re-center Write Timing\n");
+  Status = DataTimeCentering2D (
+             MrcData,
+             Outputs->MarginResult, // prev. margin results
+             Outputs->ValidChBitMask,
+             WrT,
+             0, // EnPerBit,
+             0, // EnRxDutyCycle
+             0, // ResetPerBit
+             loopcount,
+             0  // En2D
+             );
+
+  return Status;
+}
+
+/**
+  This function implements Read Equalization training.
+
+  @param[in] MrcData - Include all MRC global data.
+
+  @retval MrcStatus - if it succeeds return mrcSuccess
+**/
+MrcStatus
+MrcReadEQTraining (
+  IN MrcParameters *const MrcData
+  )
+{
+#ifdef ULT_FLAG
+  U8              RankMask;
+  U8              TestList[]  = { RdV, RdT };
+  U8              Scale[]     = { 1, 2, 1, 0, 0 };
+  U16             PwrLimits[] = { 1280, 1280, 0, 0, 0 };
+  U16             GlobalPwrLimit;
+  OptOffsetChByte BestOff;
+
+  if (MrcData->SysIn.Inputs.CpuModel == cmHSW_ULT) {
+    GlobalPwrLimit  = UpmPwrLimitValue (MrcData, TestList[0], PowerLimit);
+    PwrLimits[0]    = MAX (PwrLimits[0], GlobalPwrLimit);
+    GlobalPwrLimit  = UpmPwrLimitValue (MrcData, TestList[1], PowerLimit);
+    PwrLimits[1]    = MAX (PwrLimits[1], GlobalPwrLimit);
+
+    //
+    // Function Call for RxEQ Training
+    //
+    for (RankMask = 1; RankMask < (MRC_BIT0 << MAX_RANK_IN_CHANNEL); RankMask <<= 1) {
+      if (RankMask & MrcData->SysOut.Outputs.ValidRankMask) {
+        TrainDDROptParam (
+          MrcData,
+          &BestOff,
+          0x3,
+          RankMask,
+          OptRxEq,
+          TestList,
+          sizeof (TestList),
+          Scale,
+          PwrLimits,
+          0,  // Start
+          7,  // Stop
+          OPT_PARAM_1D_LC,
+          1,  // Repeats
+          0,  // NoPrint
+          0,  // SkipOptUpdate
+          0,  // RdRd2Test
+          0   // GuardBand
+          );
+      }
+    }
+  }
+#endif
+
+  return mrcSuccess;
+}
+
+/**
+  This function implements Write (Transmitter) Equalization training.
+
+  @param[in] MrcData - Include all MRC global data.
+
+  @retval MrcStatus - if it succeeds return mrcSuccess
+**/
+MrcStatus
+MrcWriteEQTraining (
+  IN MrcParameters *const MrcData
+  )
+{
+  MrcStatus       Status;
+  U8              Rank;
+  U8              RankMask;
+  U8              TestList[]  = { WrV, WrT };
+  U8              Scale[]     = { 1, 2, 1, 0, 0 }; // must specify scale=0 to unpopulate slots !!
+  U16             PwrLimits[5];
+  OptOffsetChByte BestOff;
+
+  MrcOemMemorySetWord (PwrLimits, 0, sizeof (PwrLimits) / sizeof (PwrLimits[0]));
+  PwrLimits[0] = UpmPwrLimitValue (MrcData, TestList[0], PowerLimit);
+  PwrLimits[1] = UpmPwrLimitValue (MrcData, TestList[1], PowerLimit);
+
+  //
+  // Function Call for RxEQ Training
+  //
+  for (Rank = 0; Rank < MAX_RANK_IN_CHANNEL; Rank++) {
+    RankMask = MRC_BIT0 << Rank;
+    if (RankMask & MrcData->SysOut.Outputs.ValidRankMask) {
+      TrainDDROptParam (
+        MrcData,
+        &BestOff,
+        0x3,
+        RankMask,
+        OptTxEq,
+        TestList,
+        sizeof (TestList),
+        Scale,
+        PwrLimits,
+        0,              // Start
+        11,             // Stop
+        OPT_PARAM_1D_LC,
+        1,              // Repeats
+        0,              // NoPrint
+        0,              // SkipOdtUpdate
+        0,              // RdRd2Test
+        2               // GuardBand
+        );
+    }
+  }
+
+  DataTimeCentering2D (
+    MrcData,
+    MrcData->SysOut.Outputs.MarginResult, // prev. margin results
+    0x3,
+    WrT,
+    0, // EnPerBit,
+    0, // EnRxDutyCycle
+    0, // ResetPerBit
+    OPT_PARAM_1D_LC,
+    0  // En2D
+    );
+
+  Status = mrcSuccess;
+  return Status;
+}
+
+/**
+  This function implements Read Amplifier Power training.
+
+  @param[in] MrcData - Include all MRC global data.
+
+  @retval MrcStatus - If it succeeds return mrcSuccess
+**/
+MrcStatus
+MrcReadAmplifierPower (
+  IN MrcParameters *const MrcData
+  )
+{
+  MrcStatus       Status;
+  MrcOutput       *Outputs;
+  const MrcDebug  *Debug;
+  U8              TestList[]  = { RdV, RdT };
+  U8              Scale[]     = { 1, 2, 1, 0, 0 }; // must specify scale=0 to unpopulate slots !!
+  U16             PwrLimits[5];
+  OptOffsetChByte BestOff;
+  BOOL            RdCenter;
+  U8              RecenterLC;
+
+  RdCenter    = 1;
+  RecenterLC  = 15;
+  Status      = mrcSuccess;
+  Outputs     = &MrcData->SysOut.Outputs;
+  Debug       = &MrcData->SysIn.Inputs.Debug;
+
+  MrcOemMemorySetWord (PwrLimits, 0, sizeof (PwrLimits) / sizeof (PwrLimits[0]));
+  PwrLimits[0] = UpmPwrLimitValue (MrcData, TestList[0], PowerLimit);
+  PwrLimits[1] = UpmPwrLimitValue (MrcData, TestList[1], PowerLimit);
+
+  //
+  // Function Call for RxBias
+  //
+  TrainDDROptParam (
+    MrcData,
+    &BestOff,
+    0x3,
+    0xF,
+    OptRxBias,
+    TestList,
+    sizeof (TestList),
+    Scale,
+    PwrLimits,
+    0,              // Start
+    7,              // Stop
+    OPT_PARAM_1D_LC,
+    1,              // Repeats
+    0,              // NoPrint
+    0,              // SkipOdtUpdate
+    0,              // RdRd2Test
+    0               // GuardBand
+    );
+
+  if (RdCenter) {
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_ERROR, "Re-center Read Timing\n");
+    Status = DataTimeCentering2D (
+              MrcData,
+              Outputs->MarginResult, // prev. margin results
+              0x3,
+              RdT,
+              0, // EnPerBit,
+              0, // EnRxDutyCycle
+              0, // ResetPerBit
+              RecenterLC,
+              0  // En2D
+              );
+  }
+
+  return Status;
+}
+
+/**
+  This function implements Dimm Ron training.
+
+  @param[in] MrcData - Include all MRC global data.
+
+  @retval MrcStatus -  if it succeeds return mrcSuccess
+**/
+MrcStatus
+MrcDimmRonTraining (
+  IN MrcParameters *const MrcData
+  )
+{
+#ifdef ULT_FLAG
+  OptOffsetChByte BestOff;
+  U8              TestList[]  = { RdV, RdT };
+  U8              Scale[]     = { 1, 2, 1, 0, 0 }; // must specify scale=0 to unpopulate slots !!
+  U16             PwrLimits[5];
+
+  MrcOemMemorySetWord (PwrLimits, 0, sizeof (PwrLimits) / sizeof (PwrLimits[0]));
+  PwrLimits[0] = UpmPwrLimitValue (MrcData, TestList[0], PowerLimit);
+  PwrLimits[1] = UpmPwrLimitValue (MrcData, TestList[1], PowerLimit);
+
+  //
+  // Check if LPDDR3 memory is used
+  //
+  if (MrcData->SysOut.Outputs.DdrType == MRC_DDR_TYPE_LPDDR3) {
+    //
+    // Function Call for RxBias
+    //
+    TrainDDROptParam (
+      MrcData,
+      &BestOff,
+      0x3,         // Channels
+      0xF,         // Ranks
+      OptDimmRon,
+      TestList,
+      sizeof (TestList),
+      Scale,
+      PwrLimits,
+      0,               // Start
+      2,               // Stop
+      OPT_PARAM_1D_LC, // Loopcount
+      1,               // Repeats
+      0,               // NoPrint
+      0,               // SkipOdtUpdate
+      0,               // RdRd2Test
+      0                // GuardBand
+      );
+  }
+#endif // ULT_FLAG
+
+  return mrcSuccess;
+
+}
+
+/**
+  This function implements Read ODT training and Write DS.
+  Optimize Read ODT strength for performance & power.
+
+  @param[in,out] MrcData         - Include all MRC global data.
+  @param[in,out] BestOff         - Structure containg the best offest and margins for th Opt param.
+  @param[in]     ChannelMask     - Channels to train
+  @param[in]     RankMask        - Condenses down the results from multiple ranks
+  @param[in]     OptParam        - Defines the OptParam Offsets.
+                               Supported OptParam = [0: WrDS, 1: RdODT, 2: SComp, 3: TComp, 3: TxEq, 4: RxEq,
+                                                     5: RxBias, 6: DimmOdt, 7: DimmOdtWr]
+  @param[in]     TestList        - List of margin params that will be tested (up to 4)
+  @param[in]     NumTests        - The length of TestList
+  @param[in]     Scale           - List of the relative importance between the 4 tests
+  @param[in]     PwrLimitsABC    - List of the values for each test margin, above which margin is "adequate"
+  @param[in]     Start           - Start point of sweeping the Comp values
+  @param[in]     Stop            - Stop point of sweeping the Comp values
+  @param[in]     LoopCount       - The number of loops to run in IO tests.
+  @param[in]     Repeats         - Number of times to repeat the test to average out any noise
+  @param[in]     NoPrint         - Switch to disable printing.
+  @param[in]     SkipOptUpdate   - Switch to train but not update Opt settings.
+  @param[in]     RdRd2Test       - Switch to run with different TA times: possible values are [0, RdRdTA, RdRdTA_All]
+  @param[in]     GuardBand       - Signed offset to apply to the Opt param best value.
+
+  @retval Nothing
+**/
+void
+TrainDDROptParam (
+  IN OUT MrcParameters *const MrcData,
+  IN OUT OptOffsetChByte      *BestOff,
+  IN     U8                   ChannelMask,
+  IN     U8                   RankMask,
+  IN     U8                   OptParam,
+  IN     U8                   *TestList,
+  IN     U8                   NumTests,
+  IN     U8                   *Scale,
+  IN     U16                  *PwrLimitsABC,
+  IN     S8                   Start,
+  IN     S8                   Stop,
+  IN     U8                   LoopCount,
+  IN     U8                   Repeats,
+  IN     BOOL                 NoPrint,
+  IN     BOOL                 SkipOptUpdate,
+  IN     U8                   RdRd2Test,
+  IN     S8                   GuardBand
+  )
+{
+  const MrcDebug    *Debug;
+  MrcOutput         *Outputs;
+  MrcChannelOut     *ChannelOut;
+  MrcControllerOut  *ControllerOut;
+  MrcStatus         Status;
+  U32               (*MarginByte)[MAX_RESULT_TYPE][MAX_RANK_IN_CHANNEL][MAX_CHANNEL][MAX_SDRAM_IN_DIMM][MAX_EDGES];
+  //
+  // TestParam X 24 Points X Ch X Byte X Hi/Lo
+  //
+  U32                                 BERStats[4];
+  U16                                 SaveMargin[4][24][MAX_CHANNEL][MAX_SDRAM_IN_DIMM][MAX_EDGES];
+  U16                                 Test;
+  U16                                 MinEdge;
+  U16                                 Margins[5][24]; // TestParam X 24 Comp Points
+  U16                                 Mode;
+  S16                                 Best;
+  U8                                  ResultType;
+  U8                                  AveN;
+  U8                                  ChBitMask;
+  U8                                  Channel;
+  U8                                  Byte;
+  U8                                  Rank;
+  U8                                  Edge;
+  U8                                  FirstRank;
+  U8                                  OdtValue;
+  U8                                  NumBytes;
+  U8                                  BMap[9]; // Need by GetBERMarginByte
+  U8                                  Param;
+  U8                                  MaxMargin;
+  U8                                  localR[MAX_CHANNEL];
+  U8                                  Rep;
+  void                                *NullPtr;
+  S8                                  CurrentComp;
+  S8                                  ReservedComp;
+  S8                                  MaxComp;
+  U16                                 OptPower[24];
+  U8                                  PWRTrendSlope1D;
+  S8                                  Delta;
+  S8                                  Index;
+  S8                                  Off;
+  S8                                  LenMargin;
+  S8                                  Shift;
+  U16                                 NoiseTicks;
+  BOOL                                NoSignal;
+  BOOL                                IncEnds;
+  BOOL                                IncEndsForPrint;
+  BOOL                                CPUComp;
+  BOOL                                printPerCh;
+  DDRCOMP_CR_DDRCRDATACOMP0_STRUCT    DdrCrDataComp0;
+  DDRCOMP_CR_DDRCRDATACOMP1_STRUCT    DdrCrDataComp1;
+  DDRSCRAM_CR_DDRMISCCONTROL0_STRUCT  DdrMiscControl0;
+  DDRCOMP_CR_DDRCRCOMPCTL0_STRUCT     DdrCrCompCtl0;
+  DDR3_MODE_REGISTER_1_STRUCT         Ddr3ModeRegister1;
+  //
+  // result print summary: 5 columns per byte
+  //
+  OptResultsPerByte                   calcResultSummary[MAX_CHANNEL][MAX_SDRAM_IN_DIMM];
+
+  MaxComp             = 63;
+  PWRTrendSlope1D     = 65;
+  ResultType          = 0;
+  NullPtr             = 0;
+  CurrentComp         = 0;
+  IncEnds             = 0;
+  IncEndsForPrint     = 0;
+  printPerCh          = 0;
+  Debug               = &MrcData->SysIn.Inputs.Debug;
+  Outputs             = &MrcData->SysOut.Outputs;
+  ControllerOut       = &Outputs->Controller[0];
+  DdrCrCompCtl0.Data  = Outputs->CompCtl0;
+  MarginByte          = &Outputs->MarginResult;
+  ChannelMask        &= Outputs->ValidChBitMask;
+  RankMask           &= Outputs->ValidRankMask;
+  MrcOemMemorySet ((U8 *) calcResultSummary, 0, sizeof (calcResultSummary));
+  MrcOemMemorySet ((U8 *) BestOff, 0xffff, sizeof (OptOffsetChByte));
+  MrcOemMemorySet ((U8 *) Margins, 0, sizeof (Margins));
+  MrcOemMemorySet ((U8 *) OptPower, 0, sizeof (OptPower));
+  MrcOemMemorySet ((U8 *) localR, 0, sizeof (localR));
+  MrcOemMemorySet ((U8 *) BERStats, 0, sizeof (BERStats));
+  for (Byte = 0; Byte < (sizeof (BMap) / sizeof (BMap[0])); Byte++) {
+    BMap[Byte] = Byte;
+  }
+  Outputs->EnDumRd = 0;
+
+  if (RdRd2Test == RdRdTA) {
+    LoopCount -= 1;  // 2 TA tests, so cut the loop count in half
+  } else if (RdRd2Test == RdRdTA_All) {
+    LoopCount -= 3;  // 8 TA tests, so divide the loop count by 8
+  }
+
+  SetupIOTestBasicVA (MrcData, ChannelMask, LoopCount, 0, 0, 0, 8); // set test to all channels
+
+  if (RdRd2Test != 0) {
+    Outputs->DQPat = RdRd2Test;
+  }
+  //
+  // Select All Ranks for REUT test
+  //
+  ChBitMask = 0;
+  for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+    if (!((MRC_BIT0 << Channel) & ChannelMask)) {
+      continue;
+    }
+
+    ChannelOut      = &ControllerOut->Channel[Channel];
+    localR[Channel] = ChannelOut->ValidRankBitMask & RankMask;
+    //
+    // use ChBitMask from here down - if ch is set that mean at least 1 rank for testing, also remove ch w/o active ranks
+    //
+    ChBitMask |= SelectReutRanks (MrcData, Channel, localR[Channel], 0);
+    //
+    // MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "reut ranks ChBitMask %x Local ranks=%x\n", ChBitMask,localR[Channel]);
+    // Clear any old state in DataTrain Offset
+    //
+    MrcOemMemorySet ((U8 *) &ChannelOut->DataOffsetTrain[0], 0, Outputs->SdramCount);
+  }
+
+  if (ChBitMask == 0) {
+    return ;
+  }
+  //
+  // Find the first selected rank
+  //
+  FirstRank = 0;
+  for (Rank = 0; Rank < MAX_RANK_IN_CHANNEL; Rank++) {
+    if ((MRC_BIT0 << Rank) & RankMask) {
+      FirstRank = Rank; // could be in any channel
+      break;
+    }
+  }
+  //
+  // Store margin results for
+  //
+  NumBytes = (U8) Outputs->SdramCount;
+
+  if ((OptParam == OptDimmOdt) || (OptParam == OptDimmOdtWr) || (OptParam == OptDimmRon)) {
+    NumBytes = 1;
+  }
+  //
+  // Calculate Start/Stop Point for Comp Optimization
+  //
+  CPUComp = ((OptParam == OptWrDS) || (OptParam == OptRdOdt) || (OptParam == OptTComp) || (OptParam == OptSComp));
+  if (CPUComp) {
+    DdrCrDataComp0.Data = DdrCrDataComp1.Data = 0;
+    if (OptParam == OptRdOdt) {
+      DdrCrDataComp1.Data = MrcReadCR (MrcData, DDRCOMP_CR_DDRCRDATACOMP1_REG);
+    } else {
+      DdrCrDataComp0.Data = MrcReadCR (MrcData, DDRCOMP_CR_DDRCRDATACOMP0_REG);
+    }
+
+    switch (OptParam) {
+    case OptWrDS:
+      CurrentComp = (S8) DdrCrDataComp0.Bits.RcompDrvUp;
+      break;
+
+    case OptRdOdt:
+      CurrentComp = (S8) DdrCrDataComp1.Bits.RcompOdtUp;
+      break;
+
+    case OptSComp:
+      CurrentComp = (S8) DdrCrDataComp0.Bits.SlewRateComp;
+      //
+      // For SCOMP we have a 5-bit register with the max value of 31.
+      // All other COMPs have 6-bit registers with the max value of 63
+      //
+      MaxComp = 31;
+      break;
+
+    case OptTComp:
+      CurrentComp = (S8) DdrCrDataComp0.Bits.TcoComp;
+      break;
+
+    default:
+      CurrentComp = 0;
+      break;
+    }
+
+    ReservedComp = 3; // Reserve 3 comp codes for adjustment range
+    Delta = CurrentComp - ReservedComp + Start;
+    if (Delta < 0) {
+      MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "------------> warning offset range is clipped by %d\n", Delta);
+      Start -= Delta;
+    }
+
+    Delta = MaxComp - CurrentComp - ReservedComp - Stop;
+    if (Delta < 0) {
+      MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "------------> warning offset range is clipped by %d\n", Delta);
+      Stop += Delta;
+    }
+
+    if (Stop < Start) {
+      Stop = Start;
+    }
+    //
+    // MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "CurrentComp = %d, Start = %d, Stop = %d, Delta = %d\n", CurrentComp, Start, Stop, Delta);
+    //
+  }
+  //
+  // Loop through all Test Params and Measure Margin
+  //
+  for (Test = 0; Test < NumTests; Test++) {
+    Param = TestList[Test]; // tl[0]=4 tl[1]=1
+    ResultType = GetMarginResultType (Param); // rxv=0 rxt=1
+    //
+    // Assign to last pass margin results by reference
+    // get lowest margin from all ch/rankS/byte save in FirstRank
+    //
+    Status = GetMarginByte (MrcData, Outputs->MarginResult, Param, FirstRank, RankMask);
+    //
+    // MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\n--- FirstRank = %d ResultType=%d Param=%d ranks=0x%x\n", FirstRank,ResultType,Param,RankMask);
+    // Calculate the MaxMargin for this test
+    //
+    MaxMargin = MAX_POSSIBLE_TIME;
+    if ((Param == RdV) ||
+        (Param == RdFan2) ||
+        (Param == RdFan3) ||
+        (Param == WrV) ||
+        (Param == WrFan2) ||
+        (Param == WrFan3)
+        ) {
+      MaxMargin = MAX_POSSIBLE_VREF;
+    }
+    //
+    // No need to search too far
+    //
+    if (MaxMargin > (PwrLimitsABC[Test] / 20)) {
+      MaxMargin = (U8) (PwrLimitsABC[Test] / 20);
+    }
+    //
+    // Loop Through all Comp Codes
+    //
+    for (Off = Start; Off < Stop + 1; Off++) {
+      Index = Off - Start;
+      //
+      // Apply Code
+      //
+      for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+        if (!((MRC_BIT0 << Channel) & ChBitMask)) {
+          continue;
+        }
+
+        ChannelOut = &ControllerOut->Channel[Channel];
+        //
+        // For DIMM ODT 2dpc, Start sweeping with RttNom = 40 and RttWr fixed at 60
+        // For DIMM ODT 1dpc, Start sweeping with RttNom = Off and RttWr fixed at Off
+        //
+        if ((OptParam == OptDimmOdt) && (ChannelOut->DimmCount == 2)) {
+          Shift = 0x20;
+        } else {
+          Shift = 0;
+        }
+
+        for (Byte = 0; Byte < NumBytes; Byte++) {
+          if (!SkipOptUpdate) {
+            //
+            // change OpParam offset for all ch/byte/LocalR
+            //
+            UpdateOptParamOffset (MrcData, Channel, localR[Channel], Byte, OptParam, (S16) (Off + Shift), 0);
+          }
+          //
+          // MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\n--Channel=%d, localR[Channel]=%x Byte=%d OffsetComp=%d Off=%d\n",Channel,localR[Channel],Byte,OffsetComp,Off);
+          //
+        } // some are limited in range inside e.g: RdOdt +15:-16
+      }
+
+      for (Rep = 0; Rep < Repeats; Rep++) {
+        //
+        // Run Margin Test - margin_1d with chosen param
+        // run on all ranks but change param only for firstRank??
+        //
+        Mode = 0;
+        //
+        // MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, " start MrcGetBERMarginByte \n");
+        //
+        Status = MrcGetBERMarginByte (
+                  MrcData,
+                  Outputs->MarginResult,
+                  ChBitMask,
+                  FirstRank,
+                  FirstRank,
+                  Param,
+                  Mode,
+                  BMap,
+                  1,
+                  MaxMargin,
+                  0,
+                  BERStats
+                  );
+        //
+        // MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, " finish MrcGetBERMarginByte \n");
+        // Record Results
+        //
+        for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+          if (!((MRC_BIT0 << Channel) & ChBitMask)) {
+            continue;
+          }
+
+          for (Edge = 0; Edge < MAX_EDGES; Edge++) {
+            MinEdge = 0xFFFF;
+            for (Byte = 0; Byte < Outputs->SdramCount; Byte++) {
+              if (Rep == 0) {
+                SaveMargin[Test][Index][Channel][Byte][Edge] = 0;
+              }
+
+              SaveMargin[Test][Index][Channel][Byte][Edge] +=
+                (U16) (*MarginByte)[ResultType][FirstRank][Channel][Byte][Edge];
+              if (MinEdge > SaveMargin[Test][Index][Channel][Byte][Edge]) {
+                MinEdge = SaveMargin[Test][Index][Channel][Byte][Edge];
+              }
+            }
+
+            if (NumBytes == 1) {
+              SaveMargin[Test][Index][Channel][0][Edge] = MinEdge; // Todo:change Byte->0
+            }
+          }
+        }
+      }
+    } // end of offset
+#ifdef MRC_DEBUG_PRINT
+    PrintResultTableByte4by24 (
+      MrcData,
+      ChBitMask,
+      SaveMargin,
+      Test,
+      Stop - Start + 1,
+      -Start,
+      2,
+      OptParam,
+      TestList[Test],
+      PwrLimitsABC,
+      NoPrint
+      );
+#endif // MRC_DEBUG_PRINT
+  } // end of test list
+  //
+  // Calculate the best value for every byte
+  //
+  // MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\n start calculate the the best margin \n");
+  //
+  LenMargin = (Stop - Start) + 1;
+  for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+    if (!((MRC_BIT0 << Channel) & ChBitMask)) {
+      continue;
+    }
+
+    ChannelOut = &ControllerOut->Channel[Channel];
+    for (Byte = 0; Byte < NumBytes; Byte++) {
+      //
+      // Populate Margins array and asymetric penalty
+      //
+      for (Test = 0; Test < NumTests; Test++) {
+        for (Off = Start; Off < Stop + 1; Off++) {
+          Index = Off - Start; // 0:..
+          //
+          // for now just get EW
+          //
+          if ((TestList[Test] == RdV) ||
+              (TestList[Test] == WrV) ||
+              (TestList[Test] == WrFan3) ||
+              (TestList[Test] == RdFan3)
+              ) {
+            Margins[Test][Index] = EffectiveMargin (
+                                    Scale[Test] * SaveMargin[Test][Index][Channel][Byte][0],
+                                    Scale[Test] * SaveMargin[Test][Index][Channel][Byte][1]
+                                    );
+          } else {
+            Margins[Test][Index] = Scale[Test] *
+              (SaveMargin[Test][Index][Channel][Byte][0] + SaveMargin[Test][Index][Channel][Byte][1]);
+          }
+        }
+      }
+      //
+      // Special Cases for Running Average Filter
+      //
+      if ((OptParam == OptDimmOdt) || (OptParam == OptDimmOdtWr) || (OptParam == OptDimmRon)) {
+        AveN = 1;
+      } else if (OptParam == OptRxBias) {
+        AveN = 3;
+      } else if (OptParam == OptRxEq) {
+        //
+        // Use special, 2D running average for RxEq
+        //
+        AveN = 1;
+        RunningAverage2D (Margins, 0, Stop - Start + 1, 5, 2, 1);
+        RunningAverage2D (Margins, 1, Stop - Start + 1, 5, 2, 1); // try Cscale=1 first.
+      } else {
+        AveN = 7;
+        if (LenMargin < AveN) {
+          AveN = LenMargin - 1;
+        }
+      }
+      //
+      // Use one of the Margin Arrays for fine grain power tradeoffs. This is only used if Scale[NumTests] is not 0
+      //
+      for (Off = 0; Off < LenMargin; Off++) {
+        OptPower[Off]          = (U16) CalcOptPower (MrcData, Channel, 0, Byte, OptParam, Off + Start, CurrentComp, 0);
+        Margins[NumTests][Off] = OptPower[Off];
+        if ((OptParam == OptDimmRon) || (OptParam == OptWrDS) || (OptParam == OptRdOdt)) {
+          //
+          // convert from Ohm to mW to pass for T-line calc : = (Vdd/2)^2/R ~ 562 / R
+          //
+          Margins[NumTests][Off] = 562 / Margins[NumTests][Off];
+        }
+
+        if ((OptParam == OptTxEq) && (ChannelOut->DimmCount == 1)) {
+          //
+          // find first rank: 0 or 2
+          //
+          for (Rank = 0; Rank < MAX_RANK_IN_CHANNEL; Rank++) {
+            if ((MRC_BIT0 << Rank) & ChannelOut->ValidRankBitMask) {
+              FirstRank = Rank; // could be in any channel
+              break;
+            }
+          }
+
+          if (Outputs->DdrType == MRC_DDR_TYPE_LPDDR3) {
+            OdtValue = 0;
+          } else {
+            Ddr3ModeRegister1.Data = ChannelOut->Dimm[FirstRank / 2].Rank[FirstRank % 2].MR[mrMR1];
+            OdtValue = (U8)
+              (
+                (Ddr3ModeRegister1.Bits.OdtRttValueHigh << 2) |
+                (Ddr3ModeRegister1.Bits.OdtRttValueMid << 1) |
+                Ddr3ModeRegister1.Bits.OdtRttValueLow
+              );
+          }
+
+          if (OdtValue == 0) {
+            Margins[NumTests][Off] = 1;//no power consideration
+          }
+        }
+      }
+      //
+      // need to provide set of power numbers depending on the OffsetComp codes (per byte)for trend line .
+      //
+      CalcPowerTrend (
+        MrcData,
+        Channel,
+        localR[Channel],
+        NullPtr,
+        Margins,
+        24,
+        LenMargin,
+        TestList,
+        Scale,
+        NumTests,
+        1,
+        PWRTrendSlope1D
+        );
+      //
+      // Use that value to create Margin Results based on power.
+      // Creates a smooth, linear function that goes from MaxSum to N/(N-1)*MaxSum
+      // RatioNum = FinePwrRatio[OptParam] * LenMargin; //e.g FinePwrRatio[RdOdt]=5
+      // Find the Best Overall Setting
+      // senSq=0,caleM=1,powerOpHigh=0
+      //
+      FindOptimalTradeOff (
+        MrcData,
+        &calcResultSummary[Channel][Byte],
+        Margins,
+        24,
+        LenMargin,
+        Scale,
+        0,
+        AveN,
+        IncEnds,
+        1,
+        PwrLimitsABC,
+        0,
+        GuardBand
+        );
+      //
+      // Get the best index considering the GuardBand
+      //
+      Best       = calcResultSummary[Channel][Byte].Best + calcResultSummary[Channel][Byte].GuardBand;
+      NoiseTicks = 3;
+      NoSignal   = FALSE;
+      for (Test = 0; Test < NumTests; Test++) {
+        if ((calcResultSummary[Channel][Byte].Ticks[Test] / 10) > NoiseTicks) {
+          NoSignal = FALSE;
+          //
+          // MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\n NumTests = %d Best =%d ch=%d byte=%d calcResultSummary[Channel][Byte].Ticks[Test]=%d NoiseTicks=%d\n",NumTests,Best,Channel,Byte,calcResultSummary[Channel][Byte].Ticks[Test],NoiseTicks);
+          //
+          break;
+        }
+      }
+
+      if (NoSignal) {
+        Best = 0;//set to min
+        calcResultSummary[Channel][Byte].Best = 0;
+      }
+      //
+      // MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\n Best =%d ch=%d byte=%d \n",Best,Channel,Byte);
+      // Update CR
+      //
+      if ((OptParam == OptDimmOdt) && (ChannelOut->DimmCount == 2)) {
+        Shift = 0x20;
+      } else {
+        Shift = 0;
+      }
+      //
+      // Best += (Shift - Start);
+      //
+      Best -= (Shift - Start); // update take offset
+      if (!SkipOptUpdate) {
+        UpdateOptParamOffset (MrcData, Channel, localR[Channel], Byte, OptParam, Best, 1);
+      }
+      //
+      // MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, " localR[Channel]=%x Best =%d ch=%d byte=%d \n",localR[Channel],Best,Channel,Byte);
+      //
+      BestOff->Offset[Channel][Byte] = Best;
+    } // end byte
+  } // End of Calculating best value (ch)
+#ifdef MRC_DEBUG_PRINT
+  //
+  // printing the results
+  //
+  for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+    if ((MrcChannelExist (Outputs, Channel))) {
+      if (!((MRC_BIT0 << Channel) & ChBitMask)) {
+        continue;
+      }
+
+      ChannelOut = &ControllerOut->Channel[Channel];
+      if (!(ChannelOut->ValidRankBitMask & localR[Channel])) {
+        continue;
+      }
+
+      IncEndsForPrint =
+        (
+          OptParam == OptDimmOdt ||
+          OptParam == OptDimmOdtWr ||
+          OptParam == OptDimmRon ||
+          OptParam == OptRxEq ||
+          IncEnds
+        );
+      printPerCh = (OptParam == OptDimmOdt || OptParam == OptDimmOdtWr || OptParam == OptDimmRon);
+      //
+      // lower bytes
+      //
+      PrintCalcResultTableCh (
+        MrcData,
+        calcResultSummary,
+        TestList,
+        NumTests,
+        Stop - Start + 1,
+        -Start,
+        IncEndsForPrint,
+        OptParam,
+        OptPower,
+        Channel,
+        localR[Channel],
+        Scale[NumTests],
+        0,
+        printPerCh,
+        NoPrint
+        );
+      //
+      // higher bytes
+      //
+      if (!printPerCh) {
+        PrintCalcResultTableCh (
+          MrcData,
+          calcResultSummary,
+          TestList,
+          NumTests,
+          Stop - Start + 1,
+          -Start,
+          IncEndsForPrint,
+          OptParam,
+          OptPower,
+          Channel,
+          localR[Channel],
+          Scale[NumTests],
+          1,
+          printPerCh,
+          NoPrint
+          );
+      }
+    }
+  }
+#endif // MRC_DEBUG_PRINT
+  //
+  // Propgate new CR setting
+  //
+  // @todo: redundant :there is one inside updateComps
+  //
+  if (CPUComp) {
+    DdrMiscControl0.Data                  = Outputs->MiscControl0;
+    DdrMiscControl0.Bits.ForceCompUpdate  = 1;
+    MrcWriteCR (MrcData, DDRSCRAM_CR_DDRMISCCONTROL0_REG, DdrMiscControl0.Data);
+  }
+  //
+  // Update the LastPass points in host
+  //
+  for (Test = 0; Test < NumTests; Test++) {
+    for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+      if (!((MRC_BIT0 << Channel) & ChBitMask)) {
+        continue;
+      }
+
+      ResultType = GetMarginResultType (TestList[Test]);
+      for (Byte = 0; Byte < NumBytes; Byte++) {
+        //
+        // save the margins in best offset point for each byte/ch in  rank 0/1
+        //
+        (*MarginByte)[ResultType][0][Channel][Byte][0] =
+          SaveMargin[Test][BestOff->Offset[Channel][Byte] - Start][Channel][Byte][0];
+        (*MarginByte)[ResultType][0][Channel][Byte][1] =
+          SaveMargin[Test][BestOff->Offset[Channel][Byte] - Start][Channel][Byte][1];
+        //
+        // MRC_DEBUG_MSG (Debug, MSG_LEVEL_ERROR, "best offset= %d ;byte=%d ;(*MarginByte)[ResultType][0][Channel][Byte][0] -%d (*MarginByte)[ResultType][0][Channel][Byte][1] -%d add=%d\n",BestOff->Offset[Channel][Byte],Byte,(U16) (*MarginByte)[ResultType][0][Channel][Byte][0] , (*MarginByte)[ResultType][0][Channel][Byte][1],((U16) (*MarginByte)[ResultType][0][Channel][Byte][0] + (U16)(*MarginByte)[ResultType][0][Channel][Byte][1]));
+        //
+      }
+    }
+
+    Status = ScaleMarginByte (MrcData, Outputs->MarginResult, TestList[Test], 0);
+  }
+
+  BestOff->NumTests = sizeof (TestList);
+  for (Test = 0; Test < NumTests; Test++) {
+    ResultType = GetMarginResultType (TestList[Test]);
+    for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+      if (!((MRC_BIT0 << Channel) & ChBitMask)) {
+        continue;
+      }
+      //
+      // track minimum eye width per ch
+      //
+      for (Byte = 0; Byte < NumBytes; Byte++) {
+        if (Byte == 0) {
+          BestOff->Margins[Test][Channel] = (U16) ((*MarginByte)[ResultType][0][Channel][0][0] +
+            (*MarginByte)[ResultType][0][Channel][0][1]);
+        } else if (BestOff->Margins[Test][Channel] >
+                   ((*MarginByte)[ResultType][0][Channel][Byte][0] + (*MarginByte)[ResultType][0][Channel][Byte][1])
+                  ) {
+          BestOff->Margins[Test][Channel] = (U16) ((*MarginByte)[ResultType][0][Channel][Byte][0] +
+            (*MarginByte)[ResultType][0][Channel][Byte][1]);
+        }
+      }
+
+      BestOff->TestList[Test][Channel] = TestList[Test];
+
+      //
+      // Normalize margins
+      // BestOff->Margins[Test][Channel] *= Scale[Test]; //Scale??
+      // MRC_DEBUG_MSG (Debug, MSG_LEVEL_ERROR, "after scale - BestOff->Margins[ch=%d][%s]= %d \n",Channel,MarginTypesString[TestList[Test]],BestOff->Margins[Test][Channel]);
+      //
+    }
+    //
+    // if (BestOff->Margins[Test][Channel]<=20) {//set OptParam to max in case off no eye
+    //   for (Byte = 0; Byte < NumBytes; Byte++) {
+    //     if(OptParam == OptRxBias) UpdateOptParamOffset (MrcData, Channel, 0, Byte, OptRxBias, 15, 1);
+    //     if(OptParam == OptWrDS) UpdateOptParamOffset (MrcData, Channel, 0, Byte, OptWrDS, 7, 1);
+    //   }
+    // }
+    //
+  }
+  //
+  // Clean up
+  //
+  Outputs->EnDumRd = 0;
+
+  return;
+
+}
+
+/**
+  This function implements Read ODT training.
+  Optimize Read ODT strength for performance & power
+
+  @param[in] MrcData - Include all MRC global data.
+
+  @retval MrcStatus - If it succeded return mrcSuccess
+**/
+MrcStatus
+MrcReadODTTraining (
+  IN MrcParameters *const MrcData
+  )
+{
+  MrcStatus                         Status;
+  const MrcInput                   *Inputs;
+  const MrcDebug                   *Debug;
+  MrcOutput                         *Outputs;
+  MrcCpuModel                       CpuModel;
+  U8                                *TestList;
+  U8                                TestListDdr3[]  = { RdV, RdT };
+  U8                                TestListSize;
+  U8                                ScaleDdr3[]     = { 1, 2, 1, 0, 0 };
+  U8                                *Scale;
+  U16                               PwrLimits[5]; // Eye width/height
+  S8                                Start;
+  S8                                Stop;
+  S16                               OffLimit;
+  S16                               OffLimitDn;
+  U16                               OdtLimit;
+  U8                                OdtLimitDn;
+  U16                               Rleg;
+  S8                                StatLegs;
+  U8                                OdtLegsDis;
+  S8                                CurrentVref;
+  S8                                CurrentComp;
+  OptOffsetChByte                   BestOff;
+  BOOL                              RdCenter;
+  U8                                RecenterLC;
+  DDRCOMP_CR_DDRCRCOMPCTL0_STRUCT   DdrCrCompCtl0;
+  DDRCOMP_CR_DDRCRDATACOMP1_STRUCT  DdrCrDataComp1;
+  U8                                RdTATestType;
+  U8                                Index;
+#ifdef ULT_FLAG
+  U8                                TestListLpddr[] = { RdV, RdT, RcvEnaX };
+  U8                                ScaleLpddr[]    = { 1, 2, 2, 1, 0 };
+  BOOL                              Lpddr;
+#endif
+
+  Inputs      = &MrcData->SysIn.Inputs;
+  Outputs     = &MrcData->SysOut.Outputs;
+  Debug       = &Inputs->Debug;
+  CpuModel    = Inputs->CpuModel;
+  Status      = mrcSuccess;
+  RdCenter    = 1;
+  RecenterLC  = 17;
+  Start       = -16;
+  MrcOemMemorySetWord (PwrLimits, 0, sizeof (PwrLimits) / sizeof (PwrLimits[0]));
+
+  //
+  // find a start offset where we below 180ohm to protect against OS/US
+  //
+  DdrCrDataComp1.Data = MrcReadCR (MrcData, DDRCOMP_CR_DDRCRDATACOMP1_REG);
+  CurrentComp         = (S8) DdrCrDataComp1.Bits.RcompOdtUp;
+  OdtLimitDn          = 30; //ohm
+  TestList            = TestListDdr3;
+  TestListSize        = sizeof (TestListDdr3);
+  Scale               = ScaleDdr3;
+  RdTATestType        = RdRdTA;
+
+#ifdef ULT_FLAG
+  Lpddr = (Outputs->DdrType == MRC_DDR_TYPE_LPDDR3);
+  if (CpuModel == cmHSW_ULT) {
+    OdtLimit = 230;
+    if (Lpddr) {
+      RdTATestType = RdRdTA_All;
+      OdtLimitDn   = 80; //ohm
+      TestList     = TestListLpddr;
+      Scale        = ScaleLpddr;
+      TestListSize = sizeof (TestListLpddr);
+    }
+  } else
+#endif //ULT_FLAG
+  {
+    OdtLimit = 180;
+  }
+
+  for (Index = 0; Index < TestListSize; Index++) {
+    PwrLimits[Index] = UpmPwrLimitValue (MrcData, TestList[Index], PowerLimit);
+  }
+
+  DdrCrCompCtl0.Data  = Outputs->CompCtl0;
+  OdtLegsDis          = (U8) DdrCrCompCtl0.Bits.DisableOdtStatic;
+  CurrentVref         = (S8) DdrCrCompCtl0.Bits.DqOdtVref;
+  StatLegs            = 4 * 4; // we enable only 1/3 segment for odt
+  if (CurrentVref & 0x10) {
+    CurrentVref -= 0x20; // 2's complement
+  }
+
+  Rleg      = CalcRdOdt (MrcData, CurrentVref) * (StatLegs * (!OdtLegsDis) + CurrentComp);
+  OffLimit  = (Rleg / OdtLimit) - StatLegs * (!OdtLegsDis) - CurrentComp;
+
+  //
+  // Find max ODT offset 
+  //
+  OffLimitDn  = (Rleg / OdtLimitDn) - StatLegs * (!OdtLegsDis) - CurrentComp;
+  Stop        = (U8) OffLimitDn;
+
+  MRC_DEBUG_MSG (
+    Debug,
+    MSG_LEVEL_ERROR,
+    " current code = %d OdtLegsDis = %d Rleg = %d CurrentVref = %d OffLimit = %d Start = %d stop = %d\n",
+    CurrentComp,
+    OdtLegsDis,
+    Rleg,
+    CurrentVref,
+    OffLimit,
+    Start,
+    Stop
+    );
+
+  if (OffLimit > Start) {
+    Start = (S8) OffLimit;
+  }
+
+  if (Stop > (23 + Start)) {
+    Stop = (S8) (23 + Start); // Only 24 offsets in the margin array.
+  }
+  if (Stop > 15) {
+    Stop = 15;
+  }
+
+  //
+  // Function Call for RdODT
+  //
+  TrainDDROptParam (
+    MrcData,
+    &BestOff,
+    0x3,
+    0xF,
+    OptRdOdt,
+    TestList,
+    TestListSize,
+    Scale,
+    PwrLimits,
+    Start,
+    Stop,           // Stop
+    17,             // Loopcount increased from 15 to better match RMT margins
+    1,              // Repeats
+    0,              // NoPrint
+    0,              // SkipOptUpdate
+    RdTATestType,   // RdRd2Test
+    0               // GuardBand
+    );
+
+  if (RdCenter) {
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_ERROR, "Re-center Read Timing\n");
+    Status = DataTimeCentering2D (
+              MrcData,
+              Outputs->MarginResult, // prev. margin results
+              0x3,
+              RdT,
+              0, // EnPerBit,
+              0, // EnRxDutyCycle
+              0, // ResetPerBit
+              RecenterLC,
+              0  // En2D
+              );
+  }
+
+  return Status;
+}
+
+/**
+  This function implements Dimm Odt training.
+  Optimize Dimm Odt value for performance/power
+
+  @param[in] MrcData - Include all MRC global data.
+
+  @retval MrcStatus - If it succeded return mrcSuccess
+**/
+MrcStatus
+MrcDimmODT1dTraining (
+  IN MrcParameters *const MrcData
+  )
+{
+  MrcStatus       Status;
+  MrcOutput       *Outputs;
+  U8              TestList[] = { RdV, RdT, WrV, WrT }; // ie 4,1
+  U8              TestListWr[] = { WrV, WrT }; // ie 4,1
+  U8              Scale[]     = { 1, 2, 1, 2, 0 };
+  U8              ScaleWr[]   = { 1, 2, 0, 0, 0 };
+  U16             PwrLimits[] = { 2480, 2240, 2480, 2240, 0 }; // just margin consideration
+  U8              dimm;
+  U8              Channel;
+  U8              ChannelMask;
+  OptOffsetChByte BestOff;
+
+  Outputs = &MrcData->SysOut.Outputs;
+
+  for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+    if ((MrcChannelExist (Outputs, Channel))) {
+      ChannelMask = MRC_BIT0 << Channel;
+      if (Outputs->Controller[0].Channel[Channel].DimmCount == 2) {
+        //
+        // DimmODT Rtt Nom - 120,60,40,30
+        // run Rtt nom with the Rtt write 0x20=60 ohm
+        //
+        TrainDDROptParam (
+          MrcData,
+          &BestOff,
+          ChannelMask,
+          0xF,
+          OptDimmOdt,
+          TestList,
+          sizeof (TestList),
+          Scale,
+          PwrLimits,
+          1,  // Start
+          4,  // Stop
+          OPT_PARAM_1D_LC,
+          1,  // Repeats
+          0,  // NoPrint
+          0,  // SkipOdtUpdate
+          0,  // RdRd2Test
+          0   // GuardBand
+          );
+        for (dimm = 0; dimm < 2; dimm++) {
+          //
+          // Function Call for DimmODT Write - 120,60
+          //
+          TrainDDROptParam (
+            MrcData,
+            &BestOff,
+            ChannelMask,
+            0x3 << (dimm * 2),
+            OptDimmOdtWr,
+            TestListWr,
+            sizeof (TestListWr),
+            ScaleWr,
+            PwrLimits,
+            1,  // Start
+            2,  // Stop
+            OPT_PARAM_1D_LC,
+            1,  // Repeats
+            0,  // NoPrint
+            0,  // SkipOdtUpdate
+            0,  // RdRd2Test
+            0   // GuardBand
+            );
+        }
+      } else {
+        //
+        // 1DPC (only write) - off,120,60
+        //
+        TrainDDROptParam (
+          MrcData,
+          &BestOff,
+          ChannelMask,
+          0xF,
+          OptDimmOdt,
+          TestListWr,
+          sizeof (TestListWr),
+          ScaleWr,
+          PwrLimits,
+          0,  // Start
+          2,  // Stop
+          OPT_PARAM_1D_LC,
+          1,  // Repeats
+          0,  // NoPrint
+          0,  // SkipOdtUpdate
+          0,  // RdRd2Test
+          0   // GuardBand
+          );
+      }
+    }
+  }
+
+  Status = mrcSuccess;
+
+  return Status;
+}
+
+/**
+  This function is the Write Drive Strength training entry point.
+  This step will optimize write drive strength for performance & power.
+
+  @param[in] MrcData - Include all MRC global data.
+
+  @retval MrcStatus - If it succeeds return mrcSuccess
+**/
+MrcStatus
+MrcWriteDriveStrength (
+  IN MrcParameters *const MrcData
+  )
+{
+  MrcStatus Status;
+  U8        OptParamLC;
+  U8        RecenterLC;
+  BOOL      Recenter;
+
+  Status      = mrcSuccess;
+  OptParamLC  = OPT_PARAM_LOOP_COUNT;
+  RecenterLC  = OPT_PARAM_1D_LC;
+  Recenter    = 1;
+
+  Status      = TrainWriteDriveStrength (MrcData, 0x3, RecenterLC, OptParamLC, Recenter);
+
+  return Status;
+}
+
+/**
+  This function implements the Write Drive Strength optimization for performance and power.
+
+  @param[in] MrcData    - Include all MRC global data.
+  @param[in] ChBitMask  - Channel mask to perform training on the Opt Param test list.
+  @param[in] RecenterLC - The loopcount for Write Time recentering.
+  @param[in] OptParamLC - The loopcount for training the Opt Param test list.
+  @param[in] Recenter   - Switch which determines if the step recenters Write Timing.
+
+  @retval If it succeeds return mrcSuccess
+**/
+MrcStatus
+TrainWriteDriveStrength (
+  IN MrcParameters *const MrcData,
+  IN const U8             ChBitMask,
+  IN const U8             RecenterLC,
+  IN const U8             OptParamLC,
+  IN const BOOL           Recenter
+  )
+{
+  MrcStatus       Status;
+  MrcOutput       *Outputs;
+  const MrcDebug  *Debug;
+  U8              TestList[]  = { WrV, WrT };
+  U8              Scale[]     = { 1, 2, 1, 0, 0 };
+  U16             PwrLimits[5];
+  OptOffsetChByte BestOff;
+
+  Status  = mrcSuccess;
+  Outputs = &MrcData->SysOut.Outputs;
+  Debug   = &MrcData->SysIn.Inputs.Debug;
+
+  MrcOemMemorySetWord (PwrLimits, 0, sizeof (PwrLimits) / sizeof (PwrLimits[0]));
+  PwrLimits[0] = UpmPwrLimitValue (MrcData, TestList[0], PowerLimit);
+  PwrLimits[1] = UpmPwrLimitValue (MrcData, TestList[1], PowerLimit);
+
+  TrainDDROptParam (
+    MrcData,
+    &BestOff,
+    ChBitMask,
+    0xf,
+    OptWrDS,
+    TestList,
+    sizeof (TestList),
+    Scale,
+    PwrLimits,
+    -13,        // Start
+    10,         // Stop
+    OptParamLC,
+    1,          // Repeats
+    0,          // NoPrint
+    0,          // SkipOdtUpdate
+    0,          // RdRd2Test
+    1           // GuardBand
+    );
+
+  if (Recenter) {
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_ERROR, "Re-center Write Timing\n");
+    Status = DataTimeCentering2D (
+              MrcData,
+              Outputs->MarginResult,  // prev. margin results
+              0x3,
+              WrT,
+              0,                      // EnPerBit,
+              0,                      // EnRxDutyCycle
+              0,                      // ResetPerBit
+              RecenterLC,
+              0                       // En2D
+              );
+  }
+
+  return Status;
+}
+
+/**
+  This function implements Write Slew Rate training.
+  Optimize Write Slew Rate for performance & power
+
+  @param[in] MrcData - Include all MRC global data.
+
+  @retval mrcSuccess
+**/
+MrcStatus
+MrcWriteSlewRate (
+  IN MrcParameters *const MrcData
+  )
+{
+#ifdef ULT_FLAG
+  U8              TestList[]  = { WrV, WrT };
+  U8              Scale[]     = { 1, 2, 0, 0, 0 };
+  U16             PwrLimits[] = { 2480, 2240, 0, 0, 0 }; // no power consideration
+  U16             GlobalPwrLimit;
+  OptOffsetChByte BestOff;
+
+  if (MrcData->SysIn.Inputs.CpuModel == cmHSW_ULT) {
+    GlobalPwrLimit  = UpmPwrLimitValue (MrcData, TestList[0], PowerLimit);
+    PwrLimits[0]    = MAX (PwrLimits[0], GlobalPwrLimit);
+    GlobalPwrLimit  = UpmPwrLimitValue (MrcData, TestList[1], PowerLimit);
+    PwrLimits[1]    = MAX (PwrLimits[1], GlobalPwrLimit);
+
+    TrainDDROptParam (
+      MrcData,
+      &BestOff,
+      0x3,
+      0xf,
+      OptSComp,
+      TestList,
+      sizeof (TestList),
+      Scale,
+      PwrLimits,
+      -15,  // Start
+      8,    // Stop
+      OPT_PARAM_1D_LC,
+      1,    // Repeats
+      0,    // NoPrint
+      0,    // SkipOdtUpdate
+      0,    // RdRd2Test
+      0     // GuardBand
+      );
+  }
+#endif
+
+  return mrcSuccess;
+}
+
+/**
+  Updates a given ch/Rank/byte combination with a new value for OptParam
+  OptParam can be: WrDS, RdOdt, TComp, SComp, RxEq, TxEq, RxBias or DimmOdt
+  OptParam == OptDefault restore values from Host except Dimms Odt's
+  @param[in,out] MrcData         - Include all MRC global data.
+  @param[in]     Channel         - Channel index to work on.
+  @param[in]     Ranks           - Condenses down the results from multiple ranks
+  @param[in]     Byte            - Byte index to work on.
+  @param[in]     OptParam        - Defines the OptParam Offsets.
+                                   Supported OptParam = [0: WrDS, 1: RdODT, 2: SComp, 3: TComp, 4: TxEq,
+                                                         5: RxEq, 6: RxBias, 7: DimmOdt, 8: DimmOdtWr]
+  @param[in]     Off             - Offset
+  @param[in]     UpdateHost      - Desides if MrcData has to be updated
+
+  @retval Nothing
+**/
+void
+UpdateOptParamOffset (
+  IN OUT MrcParameters *const MrcData,
+  IN     const U8             Channel,
+  IN     const U8             Ranks,
+  IN     const U8             Byte,
+  IN     const U8             OptParam,
+  IN     S16                  Off,
+  IN     const U8             UpdateHost
+  )
+{
+  const U16       RttNomMRSEncodingConst[] = {0x00, 0x10, 0x01, 0x11, 0x81, 0x80}; // RttNom Off,120,60,40,30,20 Ohms
+  const U16       RttWrMRSEncodingConst[]  = {0x00, 0x02, 0x01};                // RttWr  RttNom,120,60 Ohms
+  const U16       RttDimmRonEncodingConst[]  = {0x00, 0x02};                // Dimm Ron  240/6,240/7 Oms
+  const MrcDebug  *Debug;
+#ifdef ULT_FLAG
+  const U8        LpddrRonEnc[] = {0x1,0x2,0x3}; //{34,40,48};
+  const U8        LpddrOdtEnc[] = {0x0,0x2,0x3}; //{0,120,240};
+  BOOL            Lpddr;
+#endif // ULT_FLAG
+  MrcOutput       *Outputs;
+  MrcChannelOut   *ChannelOut;
+  U16             *MrReg;
+  MrcStatus       Status;
+  BOOL            Type;
+  U8              Rank;
+  U8              RankMask;
+  U8              Value;
+  U8              Index;
+  U16             MRValue;
+  U16             RttNomMRSEncoding[sizeof (RttNomMRSEncodingConst) / sizeof (RttNomMRSEncodingConst[0])];
+  U16             RttWrMRSEncoding[sizeof (RttWrMRSEncodingConst) / sizeof (RttWrMRSEncodingConst[0])];
+  U16             RttWr, RttNom, RttNomMask;
+  U16             DimmRon;
+  U16             RttWrMask;
+  U16             DimmRonMask;
+  U32             Offset;
+  S16             OffCode;
+  S16             OffMin;
+  S16             OffMax;
+  DDRDATA0CH0_CR_DDRCRDATAOFFSETCOMP_STRUCT DdrCrDataOffsetComp;
+  DDRSCRAM_CR_DDRMISCCONTROL0_STRUCT        DdrMiscControl0;
+  DDRDATA0CH0_CR_DDRCRDATACONTROL1_STRUCT   DdrCrDataControl1;
+
+  Debug       = &MrcData->SysIn.Inputs.Debug;
+  Outputs     = &MrcData->SysOut.Outputs;
+  ChannelOut  = &Outputs->Controller[0].Channel[Channel];
+  MrcOemMemoryCpy ((U8 *) RttNomMRSEncoding, (U8 *) RttNomMRSEncodingConst, sizeof (RttNomMRSEncoding));
+  MrcOemMemoryCpy ((U8 *) RttWrMRSEncoding, (U8 *) RttWrMRSEncodingConst, sizeof (RttWrMRSEncoding));
+#ifdef ULT_FLAG
+  //
+  // Check if LPDDR3 memory is used
+  //
+  Lpddr = (Outputs->DdrType == MRC_DDR_TYPE_LPDDR3);
+#endif // ULT_FLAG
+
+  //
+  // Compensation Offsets
+  //
+  Type =
+    (
+      (OptParam == OptWrDS) ||
+      (OptParam == OptRdOdt) ||
+      (OptParam == OptTComp) ||
+      (OptParam == OptSComp) ||
+      (OptParam == OptDefault)
+    );
+  if (Type) {
+    if (OptParam == OptWrDS) {
+      OffMin = -32;
+      OffMax = 31;
+    } else {
+      OffMin = -16;
+      OffMax = 15;
+    }
+
+    if (Off > OffMax) {
+      Off = OffMax;
+    } else if (Off < OffMin) {
+      Off = OffMin;
+    }
+
+    DdrCrDataOffsetComp.Data = ChannelOut->DataCompOffset[Byte];
+
+    if (OptParam == OptWrDS) {
+      DdrCrDataOffsetComp.Bits.DqDrvUpCompOffset    = Off;
+      DdrCrDataOffsetComp.Bits.DqDrvDownCompOffset  = Off;
+    } else if (OptParam == OptRdOdt) {
+      DdrCrDataOffsetComp.Bits.DqOdtUpCompOffset    = Off;
+      DdrCrDataOffsetComp.Bits.DqOdtDownCompOffset  = Off;
+    } else if (OptParam == OptTComp) {
+      DdrCrDataOffsetComp.Bits.DqTcoCompOffset = Off;
+    } else if (OptParam == OptSComp) {
+      DdrCrDataOffsetComp.Bits.DqSlewRateCompOffset = Off;
+    }
+
+    Offset = DDRDATA0CH0_CR_DDRCRDATAOFFSETCOMP_REG +
+      ((DDRDATA1CH0_CR_DDRCRDATAOFFSETCOMP_REG - DDRDATA0CH0_CR_DDRCRDATAOFFSETCOMP_REG) * Byte) +
+      ((DDRDATA0CH1_CR_DDRCRDATAOFFSETCOMP_REG - DDRDATA0CH0_CR_DDRCRDATAOFFSETCOMP_REG) * Channel);
+    MrcWriteCR (MrcData, Offset, DdrCrDataOffsetComp.Data);
+    if (UpdateHost) {
+      ChannelOut->DataCompOffset[Byte] = DdrCrDataOffsetComp.Data;
+    }
+    //
+    // Propagate new value and force comp update
+    //
+    DdrMiscControl0.Data                  = Outputs->MiscControl0;
+    DdrMiscControl0.Bits.ForceCompUpdate  = 1;
+    MrcWriteCR (MrcData, DDRSCRAM_CR_DDRMISCCONTROL0_REG, DdrMiscControl0.Data);
+  }
+  //
+  // Equalization Settings
+  //
+  Type = ((OptParam == OptTxEq) || (OptParam == OptRxEq) || (OptParam == OptDefault));
+  if (Type) {
+    for (Rank = 0; Rank < MAX_RANK_IN_CHANNEL; Rank++) {
+      if ((MrcRankInChannelExist (MrcData, Rank, Channel)) && ((Ranks & (MRC_BIT0 << Rank)))) {
+        //
+        // TxEq[5:4] = Emphasize   = [3, 6, 9, 12] legs
+        // TxEq[3:0] = Deemphasize = [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 4*Rsvd] legs
+        //
+        if (OptParam == OptTxEq) {
+          if (Off > 11) {
+            Off = 11;
+          }
+
+          if (Off < 0) {
+            Off = 0;
+          }
+
+          OffCode = Off | TXEQFULLDRV; // Use 12 Emphasize legs (not trained)
+          //MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Channel=%d,Rank= %d update to %x \n",Channel,Rank,OffCode);
+          UpdateTxT (MrcData, Channel, Rank, Byte, 2, OffCode);
+          if (UpdateHost) {
+            ChannelOut->TxEq[Rank][Byte] = (S8) OffCode;
+          }
+        }
+        //
+        // RxEQ[4:0] CR Decoding (pF/kOhm)
+        //            [2:0]
+        //  [4:3]     0        1        2        3        4        5-7
+        //     0      0.5/.02  0.5/1.0  0.5/.50  0.5/.25  0.5/.12  rsvd
+        //     1      1.0/.02  1.0/1.0  1.0/.50  1.0/.25  1.0/.12  rsvd
+        //     2      1.5/.02  1.5/1.0  1.5/.50  1.5/.25  1.5/.12  rsvd
+        //     3      2.0/.02  2.0/1.0  2.0/.50  2.0/.25  2.0/.12  rsvd
+        // Sweep = 0-19        [4:3] = (Sweep/5)  [2:0] = (Sweep%5)
+        //
+        if (OptParam == OptRxEq) {
+          if (Off > 19) {
+            Off = 19;
+          }
+
+          if (Off < 0) {
+            Off = 0;
+          }
+
+          Value = (U8) (((Off / 5) << 3) + (Off % 5));
+          UpdateRxT (MrcData, Channel, Rank, Byte, 2, Value);
+          if (UpdateHost) {
+            ChannelOut->RxEq[Rank][Byte] = Value;
+          }
+        }
+
+        if (OptParam == OptDefault) {
+          UpdateTxT (MrcData, Channel, Rank, Byte, 0xff, 0);
+          UpdateRxT (MrcData, Channel, Rank, Byte, 0xff, 0);
+        }
+      }
+    }
+  }
+  //
+  // RX Amplifier BIAS
+  //
+  if ((OptParam == OptRxBias) || (OptParam == OptDefault)) {
+    if (Off > 7) {
+      Off = 7;
+    }
+
+    if (Off < 0) {
+      Off = 0;
+    }
+    //
+    // Mapping: [0: 0.44, 1: 0.66, 2: 0.88, 3: 1.00, 4: 1.33, 5: 1.66, 6: 2.00, 7: 2.33]
+    //
+    DdrCrDataControl1.Data = ChannelOut->DqControl1[Byte].Data;
+    if (OptParam == OptRxBias) {
+      DdrCrDataControl1.Bits.RxBiasCtl = Off;
+    }
+
+    Offset = DDRDATA0CH0_CR_DDRCRDATACONTROL1_REG +
+      ((DDRDATA1CH0_CR_DDRCRDATACONTROL1_REG - DDRDATA0CH0_CR_DDRCRDATACONTROL1_REG) * Byte) +
+      ((DDRDATA0CH1_CR_DDRCRDATACONTROL1_REG - DDRDATA0CH0_CR_DDRCRDATACONTROL1_REG) * Channel);
+    MrcWriteCR (MrcData, Offset, DdrCrDataControl1.Data);
+    if (UpdateHost) {
+      ChannelOut->DqControl1[Byte].Data = DdrCrDataControl1.Data;
+    }
+  }
+  //
+  // Update Dimm Ron value
+  //
+  if ((OptParam == OptDimmRon)) {
+#ifdef ULT_FLAG
+    //
+    // Check if LPDDR3 memory is used
+    //
+    if (Lpddr) {
+      DimmRonMask = (U16)~(MRC_BIT3 | MRC_BIT2 | MRC_BIT1 | MRC_BIT0);
+      Index       = (U8) Off;
+      Index       = MIN (Index, sizeof (LpddrRonEnc) / sizeof (LpddrRonEnc[0]) - 1);
+      for (Rank = 0; Rank < MAX_RANK_IN_CHANNEL; Rank++) {
+        RankMask = MRC_BIT0 << Rank;
+        if ((MrcRankInChannelExist (MrcData, Rank, Channel)) && (Ranks & RankMask)) {
+          MrReg = &ChannelOut->Dimm[Rank / 2].Rank[(Rank % 2)].MR[mrMR0];
+          //
+          // Program Dimm Ron
+          //
+          DimmRon = LpddrRonEnc[Index];
+          MRValue = (MrReg[mrMR3] & DimmRonMask) | DimmRon;
+          Status = MrcIssueMrw (
+                    MrcData,
+                    Channel,
+                    Rank,
+                    mrMR3,
+                    MRValue,
+                    FALSE,  // InitMrw
+                    FALSE   // ChipSelect2N
+                    );
+          if (UpdateHost) {
+            MrReg[mrMR3] = MRValue;
+          }
+        }
+      }
+    } else
+#endif // ULT_FLAG
+    {
+      //
+      // DIMM Ron Encoding   RttNom[A5,A1]
+      //
+      DimmRonMask = (U16)~(MRC_BIT5 | MRC_BIT1);
+      Index       = (U8) Off;
+      Index       = MIN (Index, 1);
+      //
+      // can be 0 or 1
+      //
+      DimmRon = RttDimmRonEncodingConst[Index];
+      for (Rank = 0; Rank < MAX_RANK_IN_CHANNEL; Rank++) {
+        RankMask = MRC_BIT0 << Rank;
+        if ((MrcRankInChannelExist (MrcData, Rank, Channel)) && (Ranks & RankMask)) {
+          MrReg = &ChannelOut->Dimm[Rank / 2].Rank[(Rank % 2)].MR[mrMR0];
+          //
+          // Program Dimm Ron
+          //
+          MRValue = (MrReg[mrMR1] & DimmRonMask) | DimmRon;
+          Status  = MrcWriteMRS (MrcData, Channel, RankMask, mrMR1, MRValue);
+          if (UpdateHost) {
+            MrReg[mrMR1] = MRValue;
+          }
+        }
+      }
+    }
+  }
+  //
+  // DIMM ODT Values
+  //
+  if ((OptParam == OptDimmOdt) || (OptParam == OptDimmOdtWr)) {
+#ifdef ULT_FLAG
+    if (Lpddr) {
+      //
+      // We have only Odt write
+      //
+      RttWrMask = (U16)~(MRC_BIT1 | MRC_BIT0);
+      Index     = (U8) Off;
+      Index     = MIN (Index, sizeof (LpddrOdtEnc) / sizeof (LpddrOdtEnc[0]) - 1);
+      for (Rank = 0; Rank < MAX_RANK_IN_CHANNEL; Rank++) {
+        RankMask = MRC_BIT0 << Rank;
+        if ((MrcRankInChannelExist (MrcData, Rank, Channel)) && (Ranks & RankMask)) {
+          MrReg   = &ChannelOut->Dimm[Rank / 2].Rank[Rank % 2].MR11;
+          MRValue = *MrReg;
+          //
+          // Program Dimm DS
+          //
+          RttWr   = LpddrOdtEnc[Index];
+          MRValue = (MRValue & RttWrMask) | RttWr;
+          Status = MrcIssueMrw (
+                    MrcData,
+                    Channel,
+                    Rank,
+                    mrMR11,
+                    MRValue,
+                    FALSE,  // InitMrw
+                    FALSE   // ChipSelect2N
+                    );
+          if (UpdateHost) {
+            *MrReg = MRValue;
+          }
+        }
+      }
+
+      return;
+    }
+#endif
+    //
+    // DIMM ODT Encoding   RttNom[A9,A6,A2]   RttWr[A10, A9]
+    //
+    RttNomMask  = (U16)~(MRC_BIT9 | MRC_BIT6 | MRC_BIT2);
+    RttWrMask   = (U16)~(MRC_BIT10 | MRC_BIT9);
+
+    for (Rank = 0; Rank < MAX_RANK_IN_CHANNEL; Rank++) {
+      RankMask = MRC_BIT0 << Rank;
+      if ((MrcRankInChannelExist (MrcData, Rank, Channel)) && (Ranks & RankMask)) {
+        MrReg = &ChannelOut->Dimm[Rank / 2].Rank[(Rank % 2)].MR[mrMR0];
+
+        //
+        // Program RTT WR
+        //
+        Index   = (U8) ((OptParam == OptDimmOdt) ? (Off >> 4) : Off);
+        Index   = MIN (Index, 2);
+        RttWr   = RttWrMRSEncoding[Index] << 9;
+        MRValue = (MrReg[mrMR2] & RttWrMask) | RttWr;
+        Status  = MrcWriteMRS (MrcData, Channel, RankMask, mrMR2, MRValue);
+        if (UpdateHost) {
+          MrReg[mrMR2] = MRValue;
+        }
+        //
+        // Program RTT NOM
+        //
+        if (OptParam == OptDimmOdtWr) {
+          continue;
+        }
+
+        Index = ((U8) Off & 0xF);
+        if (Index > 5) {
+          Index = 5;
+        }
+
+        RttNom  = RttNomMRSEncoding[Index] << 2;
+        MRValue = (MrReg[mrMR1] & RttNomMask) | RttNom;
+        Status  = MrcWriteMRS (MrcData, Channel, RankMask, mrMR1, MRValue);
+        if (UpdateHost) {
+          MrReg[mrMR1] = MRValue;
+        }
+      }
+    }
+  }
+
+  return;
+}
+
+/**
+  Slightly penalize any Asymmetry in margin
+
+  @param[in] NegEdge - Negative edge of the margin
+  @param[in] PosEdge - Positive edge of the margin
+
+  @retval p2p - Width/Height reduced by the asymmetric difference in margin.
+**/
+U16
+EffectiveMargin (
+  IN const U16 NegEdge,
+  IN const U16 PosEdge
+  )
+{
+  S16 p2p;
+  U16 p2pDiff;
+
+  p2p     = 2 * (PosEdge + NegEdge);
+  p2pDiff = PosEdge - NegEdge;
+
+  if (PosEdge > NegEdge) {
+    p2p -= p2pDiff;
+  } else {
+    p2p += p2pDiff;
+  }
+
+  return p2p / 2;
+}
+
+/**
+  This function does a running average on Margins in two dimentional fashion.
+
+  @param[in,out] Margins - Margins to average
+  @param[in]     Test    - Selects the Margins to average
+  @param[in]     MLen    - Determines the Y-Dimension lengths
+  @param[in]     XDim    - Determines the X-Dimension lengths
+  @param[in]     XMin    - Used to skip the first elements in the Margin when averaging.
+  @param[in]     CScale  - Used to place more weight on the center point.
+
+  @retval Nothing
+**/
+void
+RunningAverage2D (
+  IN OUT U16       Margins[2][24],
+  IN     const U8  Test,
+  IN     const U8  MLen,
+  IN     const U8  XDim,
+  IN     const U8  XMin,
+  IN     const U8  CScale
+)
+
+{
+  U8  XMax;
+  U8  YMax;
+  U16 TMargins[24];
+  U8  i;
+  U8  x;
+  U8  y;
+  U8  xo;
+  U8  yo;
+  U8  XOff;
+  S8  YOff;
+
+  XMax  = XDim - 1;
+  YMax  = ((MLen + XDim - 1) / XDim) - 1; // Ceiling to int in case the matrix is not fully populated
+
+  for (i = 0; i < MLen; i++) {
+    x = (i % XDim);
+    y = (i / XDim);
+
+    //
+    // Center Point
+    //
+    TMargins[i] = Margins[Test][i] * (CScale - 1); // Also add margin at the centerpoint below
+    //
+    // Sum up surrounding results
+    //
+    for (xo = 0; xo < 3; xo++) {
+      XOff = x + xo - 1;
+      //
+      // Avoid negative numbers on XOff
+      //
+      if ((x == 0) && (xo == 0)) {
+        XOff = 0;
+      }
+      //
+      // (x < XMin) allows averaging across points (1;0) and (2;0)
+      //
+      if ((XOff < XMin) && (x < XMin)) {
+        XOff = x; // RxEq special case.  Skip averaging on Col0/Col1
+      }
+
+      if (XOff > XMax) {
+        XOff = XMax;
+      }
+
+      for (yo = 0; yo < 3; yo++) {
+        YOff = y + yo - 1;
+        if (YOff < 0) {
+          YOff = 0;
+        }
+
+        if (YOff > YMax) {
+          YOff = YMax;
+        }
+        //
+        // Avoid averaging with unpopulated matrix elements when dealing with partially populated matrices
+        //
+        if ((XDim * YOff + XOff) > (MLen - 1)) {
+          YOff = YOff - 1;
+        }
+
+        TMargins[i] += Margins[Test][XDim * YOff + XOff];
+      }
+    }
+  }
+  //
+  // Copy TempMargins back over to real margins
+  //
+  for (i = 0; i < MLen; i++) {
+    Margins[Test][i] = TMargins[i] / (8 + CScale); // Added div to maintain margin scaling
+  }
+
+  return;
+}
+
+/**
+    Updates a given ch/Rank/byte combination with a new value for OptParam
+    OptParam can be: WrDS, RdOdt, TComp, SComp, RxEq, TxEq, RxBias or DimmOdt
+
+    # Margins: Upto 4 arrays that contain lenMargin elements
+    # Index to the array represents some arbitrary parameter value that we are optimizing
+    # Scale is 4 element array that scales the relative importance on Margins[0] vs. [1] ...
+    #    ex: To make Margins[0] twice as important, set Scale = [1, 2, 2, 2]
+    #    Since the search optimizes the lowest margin, increasing 1/2/3 makes 0 more important
+    #    This function can be used to optimize only Margin[0] by setting Scale = [1, 0, 0, 0]
+    # EnSq = 1 uses a squared function to make the tradeoff between 0/1/2/3 steeper
+    # If AveN > 0, pre-processes the results with a N point running average filter
+    # IncEnds: By setting to 1, the running average will also include the end points
+    # ScaleM:  Allows the middle point of the running average to be scaled up
+    #
+    # In addition to optimizing for margin, this function can also optimize for power
+    # PwrLimit is a 4 element array that sets level where pwr is more important than margin
+    # Find any points where ((Margin[0]>PwrLimit[0]) & (Margin[1]>PwrLimit[1]) & ... )
+    # If such points exists and PwrOptHigh = 1, returns point with the highest X value
+    # If such points exists and PwrOptHigh = 0, returns point with the lowest X value
+    # If you don't want to optimize for power, set PwrLimitA and PwrLimitB to large number
+    # Power Optimize still uses the running average filter
+    #
+    # To avoid overflow, this function will automatic scale margins to fit in uint32
+
+  @param[in]     MrcData       - The global MRC data structure.
+  @param[in,out] OptResByte    - Structure containing the optimized results.
+  @param[in]     inputMargins  - Margins we are optimizing
+  @param[in]     MarginsLength - The length of inputMargins
+  @param[in]     LenMargin     - The length of inputMargins we are optimizing (0 - LenMargin -1).
+  @param[in]     Scale         - Controls the scaling of the input margin: 1-1, 1-2, ... and so on.
+  @param[in]     EnSq          - Enables the square root term in the optimization functions.
+  @param[in]     AveN          - The number of points used for the averaging filter.
+  @param[in]     IncEnds       - Controls if the endpoints are to be included.
+  @param[in]     ScaleM        - Controls the scaling of the middle point in 1-D average filter.
+  @param[in]     PwrLimit      - The power limit above which we only trade-off for power and not margin.
+  @param[in]     PwrOptHigh    - Controls returning the highest or lowest optimization point.
+  @param[in]     GuardBand     - Signed offest to check if margin drop is acceptable.  Save good guardband
+                                 in OptResByte.
+
+  @retval Nothing.
+**/
+void
+FindOptimalTradeOff (
+  IN     MrcParameters      *const MrcData,
+  IN OUT OptResultsPerByte         *OptResByte,
+  IN     void                      *inputMargins,
+  IN     U8                        MarginsLength,
+  IN     S8                        LenMargin,
+  IN     U8                        *Scale,
+  IN     U8                        EnSq,
+  IN     U8                        AveN,
+  IN     U8                        IncEnds,
+  IN     U8                        ScaleM,
+  IN     U16                       *PwrLimit,
+  IN     U8                        PwrOptHigh,
+  IN     S8                        GuardBand
+  )
+
+{
+  const MrcDebug    *Debug;
+  U8                NumArr;  // Arrays to keep track of results
+  U32               PostMar[5][MaxOptOff];  // Margin array after scaling & averaging
+  U32               MaxPost[5];  // Variables for Results
+  U32               SMaxPost[5];
+  U32               MinPost[5];
+  U32               Signal[5];
+  U32               Noise[5];
+  U32               Ratio[5];
+  U16               PwrLimitPost[5];
+  U32               ScaleMin;
+  U8                Nby2;
+  U8                EqOrder;
+  U8                xArr;
+  U8                yArr;
+  U8                x;
+  U8                i;
+  U8                Off;
+  S8                xEff;
+  S32               n;
+  U8                NumBits;
+  U32               localY;
+  U8                Shift;
+  U8                Adder;
+  U8                Start;
+  U8                Stop;
+  U64               Result;
+  U64               rlocal;
+  U64               MaxR;
+  U64               MinR;
+  U64               SNRTotal;
+  U64               MarginLimit;
+  U8                BestX;
+  U8                PowerX;
+  U8                FoundPwrOpt;
+  U8                NumCalcArr;
+  S8                StepSize;
+  U8                MarginDropPercent;
+  U32               MinPost1;
+  BOOL              GoodPower;
+  U16               *Margins;
+  OptResultsPerByte *calcResults;
+
+  MarginDropPercent = 10;  // 10% loss of margin is a bad guardband offset.
+  NumArr            = 5;
+  Result            = 0;
+  rlocal            = 0;
+  MaxR              = 0;
+  MinR              = 0;
+  SNRTotal          = 0;
+  Debug             = &MrcData->SysIn.Inputs.Debug;
+  MrcOemMemorySetDword (MaxPost, 1, sizeof (MaxPost) / sizeof (U32));
+  MrcOemMemorySetDword (SMaxPost, 1, sizeof (SMaxPost) / sizeof (U32));
+  MrcOemMemorySetDword (MinPost, 0xFFFFFFFF, sizeof (MinPost) / sizeof (U32));
+  MrcOemMemorySetDword (Signal, 0, sizeof (Signal) / sizeof (U32));
+  MrcOemMemorySetDword (Noise, 0, sizeof (Noise) / sizeof (U32));
+  MrcOemMemorySetDword (Ratio, 0, sizeof (Ratio) / sizeof (U32));
+  MrcOemMemorySetWord (PwrLimitPost, 0, sizeof (PwrLimitPost) / sizeof (U16));
+
+  //
+  // Initialize PostMar with zeroes
+  //
+  MrcOemMemorySet ((U8 *) PostMar, 0, sizeof (PostMar));
+
+  calcResults = OptResByte;
+  Margins     = (U16 *) inputMargins;
+  MrcOemMemorySet ((U8 *) calcResults, 0, sizeof (OptResultsPerByte));
+  //
+  // Avoid division by zero.
+  //
+  if (AveN == 0) {
+    AveN = 1;
+  }
+  Nby2    = (AveN >> 1);
+  EqOrder = 0; // Is the optimization equation: X^1, X^2, X^5
+
+  //
+  // Process Raw Margins Results
+  //
+  for (xArr = 0; xArr < NumArr; xArr++) {
+    //
+    // Scale PwrLimit to match PostMar results
+    //
+    PwrLimitPost[xArr] = PwrLimit[xArr] * (AveN + ScaleM - 1) * Scale[xArr];
+
+    for (x = 0; x < LenMargin; x++) {
+      //
+      // Calculate the Running Average Filter
+      //
+      if (Scale[xArr] == 0) {
+        //
+        // not in the game
+        //
+        MinPost[xArr] = PostMar[xArr][x] = 1;
+      } else {
+        if (x == 0) {
+          //
+          // update EqOrder once for each xArr value with a non-zero scale factor e.g.:so for {RdT,RdV,0,0} it will be =2
+          //
+          EqOrder += 1;
+        }
+
+        for (Off = 0; Off < AveN; Off++) {
+          xEff = x + Off - Nby2;
+          if (xEff < 0) {
+            PostMar[xArr][x] += *(Margins + xArr * MarginsLength + 0);  // Margins[xArr][0];
+          } else if (xEff >= LenMargin) {
+            PostMar[xArr][x] += *(Margins + xArr * MarginsLength + LenMargin - 1);
+          } else if (x == xEff) {
+            PostMar[xArr][x] += ScaleM * *(Margins + xArr * MarginsLength + xEff);
+          } else {
+            PostMar[xArr][x] += *(Margins + xArr * MarginsLength + xEff);
+          }
+        }
+
+        if (MaxPost[xArr] < PostMar[xArr][x]) {
+          MaxPost[xArr] = PostMar[xArr][x];
+        }
+
+        if (MinPost[xArr] > PostMar[xArr][x]) {
+          MinPost[xArr] = PostMar[xArr][x];
+        }
+        //
+        // signal delta pre/post average filter
+        //
+        n = (PostMar[xArr][x] -*(Margins + xArr * MarginsLength + x) * (AveN + ScaleM - 1));
+        Noise[xArr] += (n * n);
+      }
+
+      calcResults->Margins[xArr][x].EW = PostMar[xArr][x] / (AveN + ScaleM - 1);
+      //
+      // MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Margins[%d][%d] =%d\n",xArr,x,calcResults->Margins[xArr][x].EW);
+      //
+    }
+
+    if (Scale[xArr] == 0) {
+      continue;
+    }
+    //
+    // Calculate SNR for this margin result
+    // For stdev, need sqrt function.  Use log domain to change exponential to mult
+    // Make both Signal and Noise a % of (Max+Min)/2
+    // *100 for signal&noise = not go to zero
+    //
+    Signal[xArr] = ((MaxPost[xArr] - MinPost[xArr]) * 200 * 100) / (MaxPost[xArr] + MinPost[xArr]);
+    Noise[xArr] /= LenMargin;
+    if (Noise[xArr] != 0) {
+      Noise[xArr] = Mrceexp (MrcNaturalLog (100 * Noise[xArr]) / 2);  // result is 100x
+    }
+
+    Noise[xArr] = (Noise[xArr] * 2 * 100) / (MaxPost[xArr] + MinPost[xArr]);
+
+    if (Noise[xArr] == 0) {
+      Ratio[xArr] = (Signal[xArr] * 1000);
+    } else {
+      Ratio[xArr] = (Signal[xArr] * 1000) / Noise[xArr];
+    }
+
+    SMaxPost[xArr] = MaxPost[xArr];
+
+    //
+    // update global results
+    //
+    calcResults->Scale[xArr]    = Scale[xArr];
+    calcResults->Signal[xArr]   = Signal[xArr];
+    calcResults->Noise[xArr]    = Noise[xArr];
+    calcResults->Ratio[xArr]    = Ratio[xArr];
+    calcResults->MaxPost[xArr]  = MaxPost[xArr] / (AveN + ScaleM - 1);
+    calcResults->MinPost[xArr]  = MinPost[xArr] / (AveN + ScaleM - 1);
+    //
+    // 10x the tick diff.
+    //
+    calcResults->Ticks[xArr] = (U16) (MaxPost[xArr] - MinPost[xArr]) / (AveN + ScaleM - 1) / (Scale[xArr]);
+  }
+  //
+  // Sort Array
+  //
+  MrcBsort (SMaxPost, NumArr);
+
+  //
+  // Calculate Number of Bits Required to represent this number. Make sure to handle care of EnSq
+  //
+  NumBits = 0;
+
+  for (xArr = 0; xArr < NumArr; xArr++) {
+    if (xArr < (NumArr - 1)) {
+      //
+      // if EnSq we do Max^2 so the num get twice the bits...
+      //
+      localY = SMaxPost[xArr];
+      if (EnSq) {
+        localY = (localY * localY);
+      }
+
+      NumBits += MrcLog2 ((U32) localY);
+    } else {
+      NumBits += MrcLog2 ((U32) SMaxPost[xArr]);
+    }
+  }
+
+  NumBits += 11; // reserved another 10 bits for division in order to format for printing ; 3 for adding - up to 8
+  //
+  // EqOrder for square terms
+  //
+  if (EnSq) {
+    EqOrder = (EqOrder + (EqOrder - 1));
+  }
+  //
+  // Handle Potential Saturation
+  //
+  if (NumBits > 64) {
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Warning number of bits exceeds 64 bit : %d \n", NumBits);
+    //
+    // Shift all numbers to reduce final result to be less than 32 bits.  Round Up
+    //
+    Shift = (NumBits - 64 + EqOrder - 1) / EqOrder;
+    //
+    // RoundUp Adder
+    //
+    Adder = (1 << (Shift - 1));
+    //
+    // Divide by (1<<Shift) and Round Up
+    //
+    for (xArr = 0; xArr < NumArr; xArr++) {
+      MaxPost[xArr]       = (MaxPost[xArr] + Adder) >> Shift;
+      PwrLimitPost[xArr]  = (PwrLimitPost[xArr] + Adder) >> Shift;
+      for (x = 0; x < LenMargin; x++) {
+        //
+        // MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE,  "PostMar[%d][%d] before Shift : %d Adder : %d Shift : %d\n",xArr,x,PostMar[xArr][x],Shift,Adder);
+        //
+        PostMar[xArr][x] = (PostMar[xArr][x] + Adder) >> Shift;
+        //
+        // MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE,  "after: %d\n",PostMar[xArr][x]);
+        //
+      }
+    }
+  }
+  //
+  // Calculate Square terms:
+  //
+  if (EnSq) {
+    for (xArr = 0; xArr < NumArr; xArr++) {
+      MaxPost[xArr] = MaxPost[xArr] * MaxPost[xArr];
+    }
+  }
+  //
+  // Set Limits for Search
+  //
+  Start = 0;
+  Stop  = LenMargin;
+  if ((IncEnds == 0) && (LenMargin > AveN)) {
+    //
+    // most commonly
+    //
+    if (Nby2 > 0) {
+      Start++;
+      Stop--;
+    }
+  }
+  //
+  // Find the Best Point to Use
+  //
+  Result      = 0;
+  MaxR        = 0;
+  MinR        = ~(0ULL);
+  BestX       = 0;
+  PowerX      = 0;
+  FoundPwrOpt = 0;
+
+  for (x = Start; x < Stop; x++) {
+    //
+    // Find Optimal Point from Margin Point of View
+    // Combine the points using the formula:
+    //   Max0*Max1*Max2*Post3 + Max1*Max2*Max3*Post0 + Max2*Max3*Max0*Post1 +
+    //   Max3*Max0*Max1*Post2 + Scale*min(Post0,Post1,Post2,Post3)^EqOrder
+    //   Scale = 1 + (10*(SMaxPost[0]-SMaxPost[1]))/SMaxPost[NumArr-1]
+    //
+    Result    = 0;
+    MinPost1  = 0xFFFFFFFF;
+    GoodPower = 1;
+    for (xArr = 0; xArr < NumArr; xArr++) {
+      if (Scale[xArr] == 0) {
+        continue; // not need to calculate those
+      }
+      //
+      // Find Min of all PostMar at offset x
+      // Does this point meet the min power Margin requirements?
+      //
+      if (Scale[xArr] > 0) {
+        if (MinPost1 > PostMar[xArr][x]) {
+          MinPost1 = PostMar[xArr][x];
+        }
+
+        if (PostMar[xArr][x] < PwrLimitPost[xArr]) {
+          GoodPower = 0; // not ! //@todo: delete this power limit for this routing
+        }
+      }
+      //
+      // Calculate this portion of result
+      //
+      rlocal = 1;
+      for (yArr = 0; yArr < NumArr; yArr++) {
+        if (Scale[yArr] == 0) {
+          continue; // not need to calculate those
+        }
+
+        if (xArr == yArr) {
+          continue;
+        } else {
+          rlocal = MrcOemMemoryMultiplyU64ByU32 (rlocal, MaxPost[yArr]);
+        }
+      }
+
+      Result += MrcOemMemoryMultiplyU64ByU32 (rlocal, PostMar[xArr][x]);
+    }
+
+    NumCalcArr = 0;
+    for (xArr = 0; xArr < NumArr; xArr++) {
+      //
+      // required for following step.
+      //
+      if (Scale[xArr] != 0) {
+        NumCalcArr++;
+      }
+    }
+    //
+    // Add in (MinPost ^ EqOrder)
+    // If NumCalcArr is 0, set it to 1 so that it still in the range of array size.
+    //
+    if (NumCalcArr == 0) {
+      MRC_DEBUG_MSG (
+        Debug,
+        MSG_LEVEL_NOTE,
+        "Error: wrong input parameter caused NumCalcArr = 0 when calling FindOptimalTradeOff()\n"
+        );
+      NumCalcArr = 1;
+    }
+
+    ScaleMin = 1 + (10 * (SMaxPost[0] - SMaxPost[1])) / SMaxPost[NumCalcArr - 1];
+    if (ScaleMin > 5) {
+      ScaleMin = 5;
+    }
+
+    ScaleMin  = 1;
+    rlocal    = ScaleMin;
+    for (i = 0; i < EqOrder; i++) {
+      rlocal = MrcOemMemoryMultiplyU64ByU32 (rlocal, MinPost1);
+    }
+
+    Result += rlocal;
+
+    if (Result < MinR) {
+      MinR = Result;
+    }
+
+    if (Result > MaxR) {
+      MaxR  = Result;
+      BestX = x; // save first highest function result offset
+    }
+
+    calcResults->Result[x] = Result;
+    //
+    // Find Optimal Point from Power Point of View
+    //
+    if (GoodPower) {
+      //
+      // are all the point meet margins requirements for all Tests ?
+      //
+      if (FoundPwrOpt == 0) {
+        FoundPwrOpt = 1; // power optimization is possible
+        PowerX = x; // first point passing to power limits
+      } else {
+        if ((PwrOptHigh == 1) && (x > PowerX)) {
+          PowerX = x; // we take the less power save point
+        }
+
+        if ((PwrOptHigh == 0) && (x < PowerX)) {
+          PowerX = x; // @todo: how can it be ? x is alwaye increasing
+        }
+      }
+    }
+  } // end shmoo offsets
+  if ((MaxR + MinR) == 0) {
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "warninig : MaxR+MinR are Zero !!!\n");
+  }
+  //
+  // Record for debug purposes.
+  // more simple: 1000*(max-min)/((max+min)/2)
+  //
+  SNRTotal = MrcOemMemoryDivideU64ByU64 (MrcOemMemoryMultiplyU64ByU32 ((MaxR - MinR), 2000), (MaxR + MinR + 1));
+  //
+  // Are we optimizing for Power or Margin?
+  //
+  if (FoundPwrOpt) {
+    if ((PwrOptHigh == 1) && (BestX < PowerX)) {
+      BestX = PowerX;
+    }
+    //
+    // if ((PwrOptHigh==0) && (BestX>PowerX)) BestX = PowerX;//give the more power saving offset that meet power limits
+    //
+  }
+
+  calcResults->Best     = BestX;
+  calcResults->SNRTotal = SNRTotal;
+  calcResults->MaxR     = MaxR;
+  calcResults->MinR     = MinR;
+  //
+  // Apply a guard band to the best setting, clamped at edges of the search.
+  //
+  if (GuardBand != 0) {
+    //
+    // Determine step direction and limit to the search edge.
+    //
+    if (GuardBand < 0) {
+      StepSize = 1;
+      Off = ((BestX + GuardBand) < Start) ? Start : (BestX + GuardBand);
+    } else {
+      StepSize = -1;
+      Off = ((BestX + GuardBand) >= Stop) ? (Stop - 1) : (BestX + GuardBand);
+    }
+    //
+    // Check each test for margin drop of MarginDropPercent.
+    // If any test fails, we step towards the original selection.
+    //
+    MarginLimit = MrcOemMemoryMultiplyU64ByU32 (calcResults->Result[BestX], (100 - MarginDropPercent));
+    MarginLimit = MrcOemMemoryDivideU64ByU64 (MarginLimit, 100);
+    for(; (Off != BestX); Off += StepSize) {
+      if (calcResults->Result[Off] > MarginLimit) {
+        break;
+      }
+    }
+
+    calcResults->GuardBand = Off - (S8) BestX;
+  }
+
+  return;
+}
+
+/**
+  This function implements Turn Around Timing training.
+  Optimize TA ODT Delay and Duration
+
+  @param[in] MrcData - Include all MRC global data.
+
+  @retval MrcStatus - If it succeeds return mrcSuccess.
+**/
+MrcStatus
+MrcTurnAroundTiming (
+  IN MrcParameters *const MrcData
+  )
+{
+  const MrcDebug    *Debug;
+  MrcOutput         *Outputs;
+  MrcInput          *Inputs;
+  MrcControllerOut  *ControllerOut;
+  MrcChannelOut     *ChannelOut;
+  MrcStatus         Status;
+  U8                Channel;
+  U8                RankMaskCh;
+  U8                RankMask;
+  BOOL              RunDD;
+  BOOL              RunDR;
+  U8                ParamList[4]; // List of parameters to margin
+  U8                TestListRd[2];
+  U8                TestListWr[2];
+  U8                GuardBand;
+  U8                NomWR2RD;
+  U8                Update;
+  U8                LoopCount;
+  S8                ClkShifts[2];
+  U32               Offset;
+
+  Status        = mrcSuccess;
+  RankMaskCh    = 0;
+  Update        = 1;
+  LoopCount     = 12;
+  RunDD         = FALSE;
+  RunDR         = FALSE;
+  NomWR2RD      = 0;
+  RankMask      = 0xF;
+  ParamList[0]  = RdV;
+  ParamList[1]  = RdT;
+  ParamList[2]  = WrV;
+  ParamList[3]  = WrT;
+  TestListRd[0] = RdV;
+  TestListRd[1] = RdT;
+  TestListWr[0] = WrV;
+  TestListWr[1] = WrT;
+  ClkShifts[0]  = -7;
+  ClkShifts[1]  = 7;
+
+  Debug         = &MrcData->SysIn.Inputs.Debug;
+  Outputs       = &MrcData->SysOut.Outputs;
+  ControllerOut = &Outputs->Controller[0];
+  Inputs        = &MrcData->SysIn.Inputs;
+
+  for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+    ChannelOut = &ControllerOut->Channel[Channel];
+    if (!ChannelOut->ValidRankBitMask) {
+      continue;
+    }
+
+    RankMaskCh  = ChannelOut->ValidRankBitMask;
+    RunDD       = RunDD || (ChannelOut->DimmCount == 2);
+    RunDR       = RunDR || ((RankMaskCh & 0xC) == 0xC) || ((RankMaskCh & 0x3) == 0x3);
+    MRC_DEBUG_MSG (
+      Debug,
+      MSG_LEVEL_NOTE,
+      "Channel %d: RunDR = 0x%x, RunDD = 0x%x, RankMaskCh = 0x%x\n",
+      Channel,
+      RunDR,
+      RunDD,
+      RankMaskCh
+      );
+
+    //
+    // Use nominal values (previuosly programmed) +1 an -1 to test.
+    //
+    NomWR2RD = (U8)
+      (
+        (ChannelOut->MchbarBANKRANKB & MCHBAR_CH0_CR_TC_BANK_RANK_B_tWRRD_dr_MSK) >>
+        MCHBAR_CH0_CR_TC_BANK_RANK_B_tWRRD_dr_OFF
+      );
+  }
+  //
+  // Program SAFE values for ODT and SAmp
+  //
+  GuardBand = 1;
+  UpdateSampOdtTiming (MrcData, GuardBand);
+
+  //
+  // Sweep ODT values but do not apply optimized value yet (Data Collection Only)
+  //
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\n ##### Running mcodts\n");
+  Status = TrainDDROptParamCliff (
+            MrcData,
+            mcodts,
+            TestListRd,
+            sizeof (TestListRd),
+            0,
+            2 + GuardBand,
+            LoopCount,
+            Update,
+            Outputs->MarginResult,
+            ClkShifts,
+            sizeof (ClkShifts),
+            0,
+            RankMask,
+            GuardBand
+            );
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\n ##### Running mcodtd\n");
+  Status = TrainDDROptParamCliff (
+            MrcData,
+            mcodtd,
+            TestListRd,
+            sizeof (TestListRd),
+            (-1 - GuardBand),
+            0,
+            LoopCount,
+            Update,
+            Outputs->MarginResult,
+            ClkShifts,
+            sizeof (ClkShifts),
+            0,
+            RankMask,
+            GuardBand
+            );
+
+  //
+  // Restore SAFE values when ONLY collecting data
+  //
+  if (Update == 0) {
+    UpdateSampOdtTiming (MrcData, GuardBand);
+
+    for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+      ChannelOut = &ControllerOut->Channel[Channel];
+      if (!ChannelOut->ValidRankBitMask) {
+        continue;
+      }
+      Offset = MCHBAR_CH0_CR_TC_BANK_RANK_D_REG +
+        ((MCHBAR_CH1_CR_TC_BANK_RANK_D_REG - MCHBAR_CH0_CR_TC_BANK_RANK_D_REG) * Channel);
+      MrcWriteCR (MrcData, Offset, ChannelOut->MchbarBANKRANKD);
+    }
+  }
+  //
+  // Sweep DD Timing but do not apply optimized value yet (Data Collection Only)
+  //
+  if (RunDD) {
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\n ##### Running DDRD2RD\n");
+    Status = TrainDDROptParamCliff (
+              MrcData,
+              ddrd2rd,
+              TestListRd,
+              sizeof (TestListRd),
+              6,
+              7,
+              LoopCount,
+              Update,
+              Outputs->MarginResult,
+              ClkShifts,
+              sizeof (ClkShifts),
+              0,
+              RankMask,
+              0
+              );
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\n ##### Running DDWR2WR\n");
+    Status = TrainDDROptParamCliff (
+              MrcData,
+              ddwr2wr,
+              TestListWr,
+              sizeof (TestListWr),
+              7,
+              8,
+              LoopCount,
+              Update,
+              Outputs->MarginResult,
+              ClkShifts,
+              sizeof (ClkShifts),
+              0,
+              RankMask,
+              0
+              );
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\n ##### Running DDWR2RD\n");
+    Status = TrainDDROptParamCliff (
+              MrcData,
+              ddwr2rd,
+              ParamList,
+              sizeof (ParamList),
+              NomWR2RD - 1,
+              NomWR2RD + 1,
+              LoopCount,
+              Update,
+              Outputs->MarginResult,
+              ClkShifts,
+              sizeof (ClkShifts),
+              0,
+              RankMask,
+              0
+              );
+  }
+  //
+  // Sweep DR Timing but do not apply optimized value yet (Data Collection Only)
+  //
+  if (RunDR) {
+
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\n ##### Running DRRD2RD\n");
+    Status = TrainDDROptParamCliff (
+              MrcData,
+              drrd2rd,
+              TestListRd,
+              sizeof (TestListRd),
+              6,
+              7,
+              LoopCount,
+              Update,
+              Outputs->MarginResult,
+              ClkShifts,
+              sizeof (ClkShifts),
+              0,
+              RankMask,
+              0
+              );
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\n ##### Running DRWR2WR\n");
+    Status = TrainDDROptParamCliff (
+              MrcData,
+              drwr2wr,
+              TestListWr,
+              sizeof (TestListWr),
+              7,
+              8,
+              LoopCount,
+              Update,
+              Outputs->MarginResult,
+              ClkShifts,
+              sizeof (ClkShifts),
+              0,
+              RankMask,
+              0
+              );
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\n ##### Running DRWR2RD\n");
+    Status = TrainDDROptParamCliff (
+              MrcData,
+              drwr2rd,
+              ParamList,
+              sizeof (ParamList),
+              NomWR2RD - 1,
+              NomWR2RD + 1,
+              LoopCount,
+              Update,
+              Outputs->MarginResult,
+              ClkShifts,
+              sizeof (ClkShifts),
+              0,
+              RankMask,
+              0
+              );
+  }
+  //
+  // Restore SAFE values when ONLY collecting data
+  //
+  if (Update == 0) {
+    for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+      ChannelOut = &ControllerOut->Channel[Channel];
+      if (ChannelOut->ValidRankBitMask) {
+        Offset = MCHBAR_CH0_CR_TC_BANK_RANK_A_REG +
+          ((MCHBAR_CH1_CR_TC_BANK_RANK_A_REG - MCHBAR_CH0_CR_TC_BANK_RANK_A_REG) * Channel);
+        MrcWriteCR (MrcData, Offset, ChannelOut->MchbarBANKRANKA);
+
+        Offset = MCHBAR_CH0_CR_TC_BANK_RANK_B_REG +
+          ((MCHBAR_CH1_CR_TC_BANK_RANK_B_REG - MCHBAR_CH0_CR_TC_BANK_RANK_B_REG) * Channel);
+        MrcWriteCR (MrcData, Offset, ChannelOut->MchbarBANKRANKB);
+
+      }
+    }
+  }
+
+  return Status;
+}
+
+/**
+  General purpose function to optimize an abritray value, OptParam (see list above)
+    OptParam is generally some timing number that impacts performance or power
+    Expects that as OptParam gets smaller*, margins are flat until we hit a cliff
+    This procedure defines a cliff as a reducution of 4 ticks in eye height/width
+    * In the case of mcodts, higher values are actually worst
+    To stress out the timing, xxDDR_CLK is shifted by +/- 15 PI ticks
+
+  @param[in] MrcData         - Include all MRC global data.
+  @param[in] OptParam        - Supports Turnaround Timings and ODT Start / Duration
+  @param[in] TestList        - List of margin param to check to make sure timing are okay.
+  @param[in] NumTests        - The size of TestList
+  @param[in] Start           - Start point for this turn around time setting.
+  @param[in] Stop            - Stop point for this turnaround time setting.
+                                 Note that the Start/Stop values are the real values, not the encoded value
+  @param[in] LoopCount       - Length of a given test
+  @param[in] Update          - Update the CRs and host structure with ideal values
+  @param[in] ClkShifts       - Array of Pi clocks to be shifted
+  @param[in] MarginByte      - Byte level margins
+  @param[in] NumR2RPhases    - Number of PI clock phases
+  @param[in] rank            - rank to work on
+  @param[in] RankMask        - RankMask to be optimized
+  @param[in] GuardBand       - GuardBand to be added to last pass value (to be a bit conservative).
+
+  @retval MrcStatus      - If it succeeds return mrcSuccess
+**/
+MrcStatus
+TrainDDROptParamCliff (
+  IN MrcParameters *const MrcData,
+  IN U8                   OptParam,
+  IN U8                   TestList[],
+  IN U8                   NumTests,
+  IN S8                   Start,
+  IN S8                   Stop,
+  IN U8                   LoopCount,
+  IN U8                   Update,
+  IN U32                  MarginByte[MAX_RESULT_TYPE][MAX_RANK_IN_CHANNEL][MAX_CHANNEL][MAX_SDRAM_IN_DIMM][MAX_EDGES],
+  IN S8                   *ClkShifts,
+  IN U8                   NumR2RPhases,
+  IN U8                   rank,
+  IN U8                   RankMask,
+  IN U8                   GuardBand
+  )
+{
+  const MRC_REUTAddress REUTAddressConst = {
+    {0, 0, 0, 0},       // Start
+    {7, 0, 0, 1023},    // Stop
+    {0, 0, 0, 0},       // Order
+    {0, 0, 0, 0},       // IncRate
+    {1, 0, 0, 1}};      // IncValue
+  const U8          OptParamDDType[13] = {1, 2, 1, 2, 1, 2, 1, 2, 3, 3, 3, 3, 0}; // Does this test run dr, dd or both?
+  const U8          RankMapping[16] = {15, 15, 15, 4, 15, 3, 15, 1, 15, 15, 15, 15, 5, 2, 15, 0};
+    // Order of rank turnarounds for dr & dd.
+  const U32         RankOrder[2][6] = {{0x32320101, 0x20101010, 0x23232320, 0x20, 0x10, 0x23}, // RankOrder[0]: drsd - same DIMM
+                                       {0x21303120, 0x2120, 0x3020, 0x20, 0, 0}};              // RankOrder[1]: drdd - diff DIMM
+  const MrcDebug    *Debug;
+  MrcOutput         *Outputs;
+  MrcControllerOut  *ControllerOut;
+  MrcChannelOut     *ChannelOut;
+  MrcStatus         Status;
+  MRC_REUTAddress   REUTAddress;
+  MRC_WDBPattern    WDBPattern;                   // For 8 bit VA, this walks through each WDB pointer ~ 2X
+  BOOL              IsDual;
+  BOOL              ODT;
+  BOOL              PerByte;
+  BOOL              NotRankTraining;
+  BOOL              Lpddr;
+  BOOL              FindFirstPass;
+  U32               BERStats[4];                                  // Track BER results
+  U32               RankList;
+  U32               Offset;
+  U32               CRValue;
+  U16               Margins[4][2][2][MAX_CHANNEL][MAX_SDRAM_IN_DIMM];  // Tests X DR/DD x ClkPhases x Ch X Byte
+  U16               NumCL;                                        // Number of cachelines per SubSeq
+  U16               m;
+  U16               SeqLC;
+  U16               MinMarginLimit;
+  U8                ShiftValue;
+  U8                Channel;
+  U8                ChannelMask;
+  U8                Byte;
+  U16               ByteMask;
+  U8                Rank;
+  U8                ChBitMask;
+  U8                RankCount;
+  U8                ChBitMaskdd;
+  U8                RankMaskCh;
+  U8                drddPresent[2];                               // [0]: ChBitMask for dr, [1]: ChBitMask for dd
+  U8                CmdPat;
+  U8                BMap[9];                                      // Needed for GetBERMarginByte function
+  U8                MarginLimit;                                  // Need to change it to 20%of eye heigth
+  U8                ResetDDR;
+  U8                SelfRefresh;
+  U8                RankInc;                                      // Increment every cacheline (HW adds +1 automatically)
+  U16               ByteFailMask[MAX_CHANNEL];                    // Per ch mask indicating which bytes have failed
+  U8                offs[MAX_CHANNEL];
+  U8                Param;
+  U8                iparam;
+  U16               ByteDone;
+  U8                dd;
+  U8                test0;
+  U8                v0;
+  U8                Mode;
+  U8                RankOrderIndex;
+  U8                UpdateHostMargin;
+  U8                Done;
+  U8                MaxMargin;
+  U8                ResultType;
+  U8                WDBIncRate;                                   // Number of cachelines between incrementing WDB.
+  U8                LoopEnd;
+  S8                Inc;
+  S8                Off;
+  S8                Index;
+  S8                LastPass[MAX_CHANNEL][MAX_SDRAM_IN_DIMM];     // Lass Pass Value for off
+  S8                Begin;
+  S8                End;
+  S8                ChLastPass;
+  S8                ActualGuardBand;
+#ifdef MRC_DEBUG_PRINT
+  S8                ChLastPass1[MAX_CHANNEL];
+#endif // MRC_DEBUG_PRINT
+  MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_0_STRUCT  ReutChSeqRankL2PMapping;
+
+  Status          = mrcSuccess;
+  Done            = 0;
+  Rank            = 0;
+  drddPresent[0]  = 0;
+  drddPresent[1]  = 0;
+  MarginLimit     = (rtl == OptParam) ? 10 : 20;  // Drop of X% in margin means failure
+  ResetDDR        = 1;
+  SelfRefresh     = 0;
+  WDBIncRate      = 13;
+  NumCL           = 128;
+  //
+  // For {8,5,4,3,2} ranks, this covers each rank ~ {3,5,6,8,12}X
+  // For 8 bit VA, this walks through each WDB pointer ~ 2X
+  //
+  WDBPattern.IncRate  = 0;
+  WDBPattern.Start    = 0;
+  WDBPattern.Stop     = 7;
+  WDBPattern.DQPat    = 0;
+  MrcOemMemorySetWord (ByteFailMask, 0, sizeof (ByteFailMask) / sizeof(ByteFailMask[0]));
+  MrcOemMemorySet (offs, 0, sizeof (offs));
+  MrcOemMemorySet ((U8 *) BERStats, 0, sizeof (BERStats));
+  MrcOemMemoryCpy ((U8 *) &REUTAddress, (U8 *) &REUTAddressConst, sizeof (REUTAddress));
+  for (Byte = 0; Byte < (sizeof (BMap) / sizeof (BMap[0])); Byte++) {
+    BMap[Byte] = Byte;
+  }
+
+  Debug           = &MrcData->SysIn.Inputs.Debug;
+  Outputs         = &MrcData->SysOut.Outputs;
+  ControllerOut   = &Outputs->Controller[0];
+
+  Lpddr = (Outputs->DdrType == MRC_DDR_TYPE_LPDDR3);
+
+  NotRankTraining = (OptParam == rtl);
+  FindFirstPass   = (OptParam == rtl);  // FindFirstPass logic only works for RTL!
+  ODT             = (OptParam == rdodtd) || (OptParam == wrodtd) || (OptParam == mcodtd) || (OptParam == mcodts);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_ERROR, "\nNotRankTraining = %u, ODT = %d\n", NotRankTraining, ODT);
+
+  //
+  // Decide which channels need to be run and program NumCachelines
+  //
+  for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+    ChannelOut = &ControllerOut->Channel[Channel];
+    if (ChannelOut->ValidRankBitMask) {
+      ChannelMask = MRC_BIT0 << Channel;
+      RankMaskCh  = ChannelOut->ValidRankBitMask;
+      IsDual      = ((RankMaskCh & 0xC) == 0xC) || ((RankMaskCh & 0x3) == 0x3);
+
+      //
+      // Continue if no ranks in this channel
+      //
+      if ((RankMaskCh & RankMask) == 0) {
+        continue;
+      }
+
+      if ((OptParamDDType[OptParam] & 0x2) && (ChannelOut->DimmCount == 2)) {
+        drddPresent[1] |= ChannelMask; // dd parameter and channel has 2 DIMMs
+      }
+
+      if (((OptParamDDType[OptParam] & 0x1) && IsDual) || NotRankTraining) {
+        drddPresent[0] |= ChannelMask; // dr parameter and channel has a dual rank
+      }
+
+      if (ODT && ((drddPresent[0] & (1 << Channel)) == 0)) {
+        //
+        // ODT matters when Single rank
+        // dr parameter and channel has a dual rank
+        //
+        drddPresent[0] |= ChannelMask;
+      }
+    }
+  }
+
+  ChBitMask = drddPresent[1] | drddPresent[0]; // Chanel is present if it has either a dr or dd
+  MRC_DEBUG_MSG (
+    Debug,
+    MSG_LEVEL_NOTE,
+    "drddPresent[0] = 0x%x, drddPresent[1] = 0x%x, ChBitMask = 0x%x\n",
+    drddPresent[0],
+    drddPresent[1],
+    ChBitMask
+    );
+
+  //
+  // There is nothing to optimize for this parameter
+  //
+  if ((ChBitMask == 0) || (Stop <= Start)) {
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "ChBitMask = %d, Start = 0x%x, Stop = 0x%x\n", ChBitMask, Start, Stop);
+
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_ERROR, "No need to optimized TA, OptParam = %d\n", OptParam);
+    return mrcFail;
+  }
+  //
+  // Setup the REUT Test
+  //
+  SeqLC           = LoopCount;
+  RankInc         = 0;
+  Outputs->DQPat  = TurnAround;
+  if ((OptParam == ddwr2rd) || (OptParam == drwr2rd)) {
+    CmdPat          = PatWrRdTA;
+    Outputs->DQPat  = TurnAroundWR;
+    RankInc         = 1;
+  } else if (ODT) {
+    CmdPat          = PatODTTA;
+    Outputs->DQPat  = TurnAroundODT;
+    RankInc         = 1;
+  } else if (OptParam == rtl) {
+    CmdPat = PatWrRd;
+    //
+    // Less optimistic values since we are updating values and RMT fails
+    //
+    WDBIncRate  = 16;
+    NumCL       = 4;
+  } else {
+    CmdPat = PatWrRd;
+  }
+
+  WDBPattern.DQPat        = Outputs->DQPat;
+  WDBPattern.IncRate      = WDBIncRate;
+  REUTAddress.IncRate[0]  = RankInc;
+  REUTAddress.IncRate[3]  = RankInc;
+
+  //
+  // SOE=0, EnCADB=0, EnCKE=0, SubSeqWait=0
+  //
+  SetupIOTest (MrcData, ChBitMask, CmdPat, NumCL, (U8) SeqLC, &REUTAddress, NSOE, &WDBPattern, 0, 0, 0);
+
+  Outputs->DQPatLC = MRC_BIT0 << (LoopCount - MrcLog2 ((U32) (NumCL - 1)));
+  if (Outputs->DQPatLC < 1) {
+    Outputs->DQPatLC = 1;
+  }
+  //
+  // Optimize parameter per byte.  Everything else is per channel
+  //
+  PerByte = (OptParam == mcodts) || (OptParam == mcodtd);
+
+  //
+  // Keep track of which bytes have failed and are we done yet
+  //
+  ByteDone = (1 << Outputs->SdramCount) - 1;
+
+  //
+  // ###########################################################
+  // ####  Loop through OptParam X DD X ClkPhases X Params and measure margin #####
+  // ###########################################################
+  //
+  if (OptParam == mcodts) {
+    //
+    // In the case of mcodts, higher values are actually worst.
+    //
+    Begin = Start;
+    End   = Stop;
+    Inc   = 1;
+  } else {
+    Begin = Stop;
+    End   = Start;
+    Inc   = -1;
+  }
+
+  ActualGuardBand = (Inc * GuardBand);
+
+  MRC_DEBUG_MSG (
+    Debug,
+    MSG_LEVEL_NOTE,
+    "Start = %d, Stop = %d, Begin = %d, End = %d, Inc = %d\n",
+    Start,
+    Stop,
+    Begin,
+    End,
+    Inc
+    );
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, (OptParam == rtl) ? "Rank = %d\n" : "", rank);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Channel 0\t\t\t\t\t\t\t\t1\nByte\t");
+  MRC_DEBUG_MSG (
+    Debug,
+    MSG_LEVEL_NOTE, (
+    Outputs->SdramCount == MAX_SDRAM_IN_DIMM
+    ) ? "0\t1\t2\t3\t4\t\t5\t6\t7\t8\t0\t1\t2\t3\t4\t5\t6\t7\t8\n" :
+    "0\t1\t2\t3\t4\t5\t6\t7\t0\t1\t2\t3\t4\t5\t6\t7\n"
+    );
+
+  //
+  // Init Variables
+  //
+  for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+    if (MrcChannelExist (Outputs, Channel)) {
+      for (Byte = 0; Byte < Outputs->SdramCount; Byte++) {
+        LastPass[Channel][Byte] = Begin - ActualGuardBand;
+        for (iparam = 0; iparam < NumTests; iparam++) {
+          for (dd = 0; dd < 2; dd++) {
+            for (test0 = 0; test0 < NumR2RPhases; test0++) {
+              Margins[iparam][dd][test0][Channel][Byte] = 1280;
+            }
+          }
+        }
+      }
+    }
+  }
+  //
+  // Walk through different OptParam values
+  //
+  for (Off = (S8) Begin; Off != (S8) (End + Inc); Off += Inc) {
+    if (Done) {
+      break;
+    }
+    Index = (Off - Begin) * Inc; // Index = 0, 1, 2..
+    //
+    // Inc can only take a value of +/- 1.
+    //
+    if ((Index == 1) && (TRUE == FindFirstPass)) {
+      Inc  *= -1;
+      Off   = End;
+      End   = Begin - Inc;  // One Inc less since we have already done Index 0.
+      Begin = Off - Inc;    // One Inc less to get us starting at Index 1
+      MRC_DEBUG_MSG (
+        Debug,
+        MSG_LEVEL_NOTE,
+        "Find First Pass - Walking backwards.\n Off = %d, Begin = %d, End = %d, Inc = %d, Index = %d\n",
+        Off,
+        Begin,
+        End,
+        Inc,
+        (Off - Begin) * Inc
+        );
+    }
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Param^ Offset-> %d\n   Actl\t", Off);
+
+    for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+      ChannelOut  = &ControllerOut->Channel[Channel];
+      RankMaskCh  = ChannelOut->ValidRankBitMask & RankMask;
+      //
+      // if nothing for this channel OR No Ranks in this channel
+      //
+      if (!((MRC_BIT0 << Channel) & ChBitMask) || (RankMaskCh == 0)) {
+#ifdef MRC_DEBUG_PRINT
+        if (Channel == 0) {
+          if (Outputs->SdramCount == (MAX_SDRAM_IN_DIMM - 1)) {
+            MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\t\t\t\t\t\t\t\t");
+          } else {
+            MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\t\t\t\t\t\t\t\t\t");
+          }
+        }
+#endif // MRC_DEBUG_PRINT
+        continue;
+      }
+      //
+      // For debug purposes program Row start stop to OptParam + Offset value
+      // OptParam in upper BYTE
+      //
+      Offset = 4 + MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_0_REG +
+        (
+          (MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_1_REG - MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_0_REG) *
+          Channel
+        );
+      CRValue = MrcReadCR (MrcData, Offset);
+      //MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "upper SEQ_BASE_ADDR_START BEFORE = 0x%x ", CRValue);
+      CRValue = MrcBitSwap (CRValue, OptParam, 0, 8);
+      //MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "After = 0x%x\n", CRValue);
+      MrcWriteCR (MrcData, Offset, CRValue);
+      //
+      // Offset in Lower BYTE
+      //
+      Offset -= 4;
+      CRValue = MrcReadCR (MrcData, Offset);
+      //MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "lower SEQ_BASE_ADDR_START BEFORE = 0x%x ", CRValue);
+      CRValue = MrcBitSwap (CRValue, Off, 24, 8);
+      //MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "After = 0x%x\n", CRValue);
+      MrcWriteCR (MrcData, Offset, CRValue);
+
+      //
+      // OptParam in upper BYTE
+      //
+      Offset = 4 + MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_0_REG +
+        (
+          (MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_1_REG - MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_0_REG) *
+          Channel
+        );
+      CRValue = MrcReadCR (MrcData, Offset);
+      //MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "upper SEQ_BASE_ADDR_WRAP BEFORE = 0x%x ", CRValue);
+      CRValue = MrcBitSwap (CRValue, OptParam, 0, 8);
+      //MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "After = 0x%x\n", CRValue);
+      MrcWriteCR (MrcData, Offset, CRValue);
+      //
+      // Offset in Lower BYTE
+      //
+      Offset -= 4;
+      CRValue = MrcReadCR (MrcData, Offset);
+      //MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "lower SEQ_BASE_ADDR_WRAP BEFORE = 0x%x ", CRValue);
+      CRValue = MrcBitSwap (CRValue, Off, 24, 8);
+      //MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "After = 0x%x\n", CRValue);
+      MrcWriteCR (MrcData, Offset, CRValue);
+
+      //
+      // No need to update MrcData host during this step even if not collecting data
+      //
+      LoopEnd = (U8) ((PerByte) ? Outputs->SdramCount : 1);
+      for (Byte = 0; Byte < LoopEnd; Byte++) {
+        UpdateTAParamOffset (MrcData, Channel, Byte, OptParam, Off, 0, 0, RankMaskCh);
+      }
+    }
+
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\n");
+
+    //
+    // Test both: different dr and dd as required
+    //
+    for (dd = 0; dd < 2; dd++) {
+      if (Done) {
+        break;
+      }
+      //
+      // Check if this test type should be run
+      //
+      ChBitMaskdd = drddPresent[dd];
+      if (ChBitMaskdd == 0) {
+        continue;
+      }
+
+      MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, (dd == 0) ? "Dual Rank\n" : "Dual Dimm\n");
+      //
+      // Select Ranks in the correct order based on the test type
+      // Need to re-order the ranks based on the value of ddw2r
+      //
+      for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+        if (!(ChBitMaskdd & (MRC_BIT0 << Channel))) {
+          continue;
+        }
+
+        ChannelOut  = &ControllerOut->Channel[Channel];
+        RankMaskCh  = ChannelOut->ValidRankBitMask & RankMask;
+        if (RankMaskCh == 0) {
+          continue; // No Ranks in this channel
+        }
+        //
+        // Initialize variables and read out ordered rank list
+        //
+        ReutChSeqRankL2PMapping.Data  = 0;
+        RankCount                     = 0;
+
+        if (NotRankTraining) {
+          RankList = 0x00003210;
+        } else {
+          RankOrderIndex = RankMapping[RankMaskCh];
+          if (RankOrderIndex == 15) {
+            RankList = 0x00003210;
+          } else {
+            RankList = RankOrder[dd][RankOrderIndex];
+          }
+        }
+
+        while (RankList > 0) {
+          Rank = (RankList & 0xF); // Nibble by Nibble
+          RankList = (RankList >> 4);
+          if (!(RankMaskCh & (MRC_BIT0 << Rank))) {
+            continue;
+          }
+
+          ShiftValue = RankCount *
+            MRC_BIT0 <<
+            MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_0_Logical_to_Physical_Rank0_Mapping_WID;
+          ReutChSeqRankL2PMapping.Data |= (Rank << ShiftValue);
+          RankCount++;
+        }
+
+        Offset = MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_0_REG +
+          (
+            (
+              MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_1_REG -
+              MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_0_REG
+            ) * Channel
+          );
+        MrcWriteCR (MrcData, Offset, ReutChSeqRankL2PMapping.Data);
+        Offset = MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_0_REG +
+          (
+            (MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_1_REG - MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_0_REG) *
+            Channel
+          ) + 7;
+        MrcWriteCR8 (MrcData, Offset, RankCount - 1);
+      }
+      //
+      // ###################################################
+      // ### Walk through different sets of rank2rank timings  ###
+      // ###################################################
+      //
+      for (test0 = 0; test0 < NumR2RPhases; test0++) {
+        if (Done) {
+          break;
+        }
+
+        v0 = ClkShifts[test0];
+
+        //
+        // Program rank offsets differently for dd vs. dr
+        //
+        if (NotRankTraining) {
+          for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+            if (!(ChBitMaskdd & (MRC_BIT0 << Channel))) {
+              offs[Channel] = 0;
+            } else {
+              //
+              // Shift all signals in the channel(Clk/Ctl/Cmd/Dq) by v0
+              //
+              offs[Channel] = v0;
+            }
+          }
+          //
+          // UpdateHost=0, SkipTx=0
+          //
+          ShiftCh2Ch (MrcData, RankMask, offs, ResetDDR, SelfRefresh, 0, 0);
+        } else if (dd == 1) {
+          //
+          // For DD
+          // Shift Clk/DQ on one DIMM by v0 and Clk/DQ on other DIMM by -v0
+          // @todo: CTL picode should be optionally shifted to improve margins
+          //
+          SetCmdMargin (MrcData, ChBitMaskdd, 0x3, WrT, v0, 0, ResetDDR, SelfRefresh);
+          SetCmdMargin (MrcData, ChBitMaskdd, 0xC, WrT, -v0, 0, ResetDDR, SelfRefresh);
+        } else {
+          //
+          // For DR
+          // Shift Clk/DQ on front side by v0 and Clk/DQ on backside by -v0
+          // @todo: CTL picode should be optionally shifted to improve margins
+          //
+          SetCmdMargin (MrcData, ChBitMaskdd, 0x5, WrT, v0, 0, ResetDDR, SelfRefresh);
+          SetCmdMargin (MrcData, ChBitMaskdd, 0xA, WrT, -v0, 0, ResetDDR, SelfRefresh);
+        }
+        //
+        // Test different margin param
+        //
+        for (iparam = 0; iparam < NumTests; iparam++) {
+          Param = TestList[iparam];
+          MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%s ", MarginTypesString[Param]);
+          if (Param == 0) {
+            MRC_DEBUG_MSG (Debug, MSG_LEVEL_WARNING, " WARNING! UNNECESSARY LOOPS. Param = %d \n", Param);
+            return mrcFail;
+          }
+
+          ResultType = GetMarginResultType (Param);
+
+          //
+          // Get the width/height limit for the parameter
+          //
+          MinMarginLimit = UpmPwrLimitValue (MrcData, Param, UpmLimit);
+          //
+          // MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%d ", MinMarginLimit);
+          // Calculate MaxMargin and Starting Point for margin search
+          //
+          MaxMargin = MAX_POSSIBLE_TIME;
+          if ((Param == RdV) ||
+              (Param == RdFan2) ||
+              (Param == RdFan3) ||
+              (Param == WrV) ||
+              (Param == WrFan2) ||
+              (Param == WrFan3)
+              ) {
+            MaxMargin = MAX_POSSIBLE_VREF;
+          }
+          //
+          // Are we done yet or should we keep testing?
+          //
+          Done = 1;
+          for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+            if (!(ChBitMaskdd & (MRC_BIT0 << Channel))) {
+              continue;
+            }
+
+            ChannelOut  = &ControllerOut->Channel[Channel];
+            RankMaskCh  = ChannelOut->ValidRankBitMask & RankMask;
+            if (RankMaskCh == 0) {
+              continue; // No Ranks in this channel
+            }
+
+            //
+            // When FindFirstPass is used, all Bytes have to have passed before we stop.
+            // We uses ByteFailMask[] to track the passing bytes in this case.
+            //
+            if (PerByte || FindFirstPass) {
+              if (ByteFailMask[Channel] != ByteDone) {
+                Done = 0;
+              }
+            } else {
+              if (ByteFailMask[Channel] == 0) {
+                Done = 0;
+              }
+            }
+          }
+
+          if (Done) {
+            break;
+          }
+
+          Status = GetMarginByte (MrcData, Outputs->MarginResult, Param, 0, 0xF);
+          if (Status != mrcSuccess) {
+            return Status;
+          }
+
+          MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "% 3d\t", (S8) v0);
+
+          Mode = 0;
+          Status = MrcGetBERMarginByte (
+                    MrcData,
+                    Outputs->MarginResult,
+                    ChBitMaskdd,
+                    rank,
+                    0xFF,
+                    Param,
+                    Mode,
+                    BMap,
+                    1,
+                    MaxMargin,
+                    0,
+                    BERStats
+                    );
+          if (Status != mrcSuccess) {
+            return Status;
+          }
+          //
+          // Record Results
+          //
+          UpdateHostMargin = 1;
+
+          for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+            ChannelOut  = &ControllerOut->Channel[Channel];
+            RankMaskCh  = ChannelOut->ValidRankBitMask & RankMask;
+            //
+            // if nothing for this channel OR No Ranks in this channel
+            //
+            if (!((MRC_BIT0 << Channel) & ChBitMaskdd) || (RankMaskCh == 0)) {
+#ifdef MRC_DEBUG_PRINT
+              if (Channel == 0) {
+                if (Outputs->SdramCount == (MAX_SDRAM_IN_DIMM - 1)) {
+                  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\t\t\t\t\t\t\t\t");
+                } else {
+                  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\t\t\t\t\t\t\t\t\t");
+                }
+              }
+#endif // MRC_DEBUG_PRINT
+              continue;
+            }
+
+            for (Byte = 0; Byte < Outputs->SdramCount; Byte++) {
+              //
+              // For this optimization, it makes more sense to look at the full sum
+              //
+              ByteMask = MRC_BIT0 << Byte;
+              m = EffectiveMargin (
+                    (U16) MarginByte[ResultType][rank][Channel][Byte][0],
+                    (U16) MarginByte[ResultType][rank][Channel][Byte][1]
+                    );
+              MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%d", m);
+
+              //
+              // If previously failed, this is also a failure unless we are looking for
+              // the first passing offset.
+              //
+              if ((ByteFailMask[Channel] & ByteMask) && (FALSE == FindFirstPass)) {
+                MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "#\t");
+                continue;
+              }
+              //
+              // Byte fails if margin is below MinMarginLimit at any time
+              //
+              if (m < MinMarginLimit) {
+                //
+                // If we are looking for pass, continue and do not update LastPass
+                //
+                if (TRUE == FindFirstPass) {
+                  if (Index == 0) {
+                    //
+                    // When training from the most aggressive setting to the conservative setting,
+                    // if we fail the first setting we stop.
+                    //
+                    ByteFailMask[Channel] = ByteDone;
+                  }
+                  UpdateHostMargin = 0;
+                } else {
+                  ByteFailMask[Channel] |= ByteMask;
+                  LastPass[Channel][Byte] = Off - Inc - ActualGuardBand;
+                }
+                MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "#\t");
+                continue;
+              }
+
+              if (Index == 0) {
+                //
+                // Get the smallest marging at Index 0
+                //
+                if (Margins[iparam][dd][test0][Channel][Byte] > m) {
+                  Margins[iparam][dd][test0][Channel][Byte] = m;
+                }
+              } else {
+                //
+                // Check if we dropped more than the percent allowed
+                //
+                if (m < ((Margins[iparam][dd][test0][Channel][Byte] * (100 - MarginLimit)) / 100)) {
+                  if (FALSE == FindFirstPass) {
+                    ByteFailMask[Channel] |= ByteMask;
+                    LastPass[Channel][Byte] = Off - Inc - ActualGuardBand;
+                  }
+                  UpdateHostMargin = 0;
+                  MRC_DEBUG_MSG (
+                    Debug,
+                    MSG_LEVEL_NOTE,
+                    "#-%d\t",
+                    (ABS (m - Margins[iparam][dd][test0][Channel][Byte]) * 100) / Margins[iparam][dd][test0][Channel][Byte]
+                    );
+                  continue;
+                } else {
+                  if (TRUE == FindFirstPass) {
+                    if ((ByteFailMask[Channel] & ByteMask) != ByteMask) {
+                      LastPass[Channel][Byte] = Off - ActualGuardBand;
+                      ByteFailMask[Channel] |= ByteMask;
+                    }
+                  } else {
+                    LastPass[Channel][Byte] = Off - ActualGuardBand;
+                  }
+                }
+              }
+
+              MRC_DEBUG_MSG (
+                Debug,
+                MSG_LEVEL_NOTE,
+                ".%c%d\t",
+                (m > Margins[iparam][dd][test0][Channel][Byte]) ? '+' : '-',
+                (ABS(m - Margins[iparam][dd][test0][Channel][Byte]) * 100) / Margins[iparam][dd][test0][Channel][Byte]
+                );
+            }
+          }
+
+          if (UpdateHostMargin) {
+            Status = ScaleMarginByte (MrcData, Outputs->MarginResult, Param, rank);
+          }
+
+          MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\n");
+        }
+
+        MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\n");
+
+        //
+        // Clean up
+        //
+        if (NotRankTraining) {
+          for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+            offs[Channel] = 0;
+          }
+          //
+          // UpdateHost=0, SkipTx=0
+          //
+          ShiftCh2Ch (MrcData, RankMask, offs, ResetDDR, SelfRefresh, 0, 0);
+        } else {
+          SetCmdMargin (MrcData, ChBitMaskdd, RankMask, WrT, 0, 0, ResetDDR, SelfRefresh);
+        }
+      }
+
+      MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\n");
+    }
+  }
+
+  //
+  // If we are sweeping agressive settings to conservative settings, we
+  // need to restore original Inc, Begin, and End values to select the 
+  // proper offset if bytes have varying offsets values for a parameter
+  // that is NOT specified per Byte.
+  //
+  if (TRUE == FindFirstPass) {
+    Off   = End;         // Temp storage for swap
+    End   = Begin + Inc;
+    Begin = Off + Inc;
+    Inc  *= -1;
+    MRC_DEBUG_MSG (
+      Debug,
+      MSG_LEVEL_NOTE,
+      "Find First Pass - Reverting Inc, Begin, and End\n Begin = %d, End = %d, Inc = %d,\n",
+      Begin,
+      End,
+      Inc
+      );
+  }
+
+#ifdef MRC_DEBUG_PRINT
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Optimal offset per Byte\n\t");
+  //
+  // Print OPTIMAL value
+  //
+  for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+    ChannelOut            = &ControllerOut->Channel[Channel];
+    RankMaskCh            = ChannelOut->ValidRankBitMask & RankMask;
+    ChLastPass1[Channel]  = End;
+    //
+    // if nothing for this channel OR No Ranks in this channel
+    //
+    if (!((MRC_BIT0 << Channel) & ChBitMask) || (RankMaskCh == 0)) {
+      if (Channel == 0) {
+        if (Outputs->SdramCount == (MAX_SDRAM_IN_DIMM - 1)) {
+          MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\t\t\t\t\t\t\t\t");
+        } else {
+          MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\t\t\t\t\t\t\t\t\t");
+        }
+      }
+
+      continue;
+    }
+
+    for (Byte = 0; Byte < Outputs->SdramCount; Byte++) {
+      MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%d\t", LastPass[Channel][Byte]);
+      if ((Inc == 1) && (ChLastPass1[Channel] > LastPass[Channel][Byte])) {
+        ChLastPass1[Channel] = LastPass[Channel][Byte];
+      }
+
+      if ((Inc == -1) && (ChLastPass1[Channel] < LastPass[Channel][Byte])) {
+        ChLastPass1[Channel] = LastPass[Channel][Byte];
+      }
+    }
+  }
+
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\n");
+  for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+    ChannelOut  = &ControllerOut->Channel[Channel];
+    RankMaskCh  = ChannelOut->ValidRankBitMask & RankMask;
+    //
+    // if nothing for this channel OR No Ranks in this channel
+    //
+    if (!((MRC_BIT0 << Channel) & ChBitMask) || (RankMaskCh == 0)) {
+      continue;
+    }
+
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Optimal offset Channel %d = %d\n", Channel, ChLastPass1[Channel]);
+  }
+#endif // MRC_DEBUG_PRINT
+  //
+  // Program new value
+  //
+  for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+    if (!((MRC_BIT0 << Channel) & ChBitMask)) {
+      continue;
+    }
+
+    ChannelOut  = &ControllerOut->Channel[Channel];
+    RankMaskCh  = ChannelOut->ValidRankBitMask & RankMask;
+    if (RankMaskCh == 0) {
+      continue; // No Ranks in this channel
+    }
+    //
+    // Start with the most aggressive setting
+    //
+    ChLastPass = End;
+    for (Byte = 0; Byte < Outputs->SdramCount; Byte++) {
+      if (Update == 0) {
+        LastPass[Channel][Byte] = Begin;
+      }
+
+      if ((Inc == 1) && (ChLastPass > LastPass[Channel][Byte])) {
+        ChLastPass = LastPass[Channel][Byte];
+      }
+
+      if ((Inc == -1) && (ChLastPass < LastPass[Channel][Byte])) {
+        ChLastPass = LastPass[Channel][Byte];
+      }
+
+      if (PerByte) {
+        UpdateTAParamOffset (MrcData, Channel, Byte, OptParam, LastPass[Channel][Byte], Update, 1, RankMaskCh);
+      }
+    }
+
+    if (PerByte == 0) {
+      UpdateTAParamOffset (MrcData, Channel, 0, OptParam, ChLastPass, Update, 1, RankMaskCh);
+    }
+
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Selected Offset for channel %d is = %d\n", Channel, ChLastPass);
+  }
+
+  return Status;
+}
+
+/**
+  Sets commnad margins when moving WrT, WrTBox, or WrV
+  NOTE: ONLY one, ResetDDR or SelfRefresh can be set inside this function
+
+  @param[in] MrcData         - Include all MRC global data.
+  @param[in] ChBitMask       - Bit mask of populated channels
+  @param[in] Ranks           - Bit Mask of populated ranks
+  @param[in] Param           - Input parameter to update
+  @param[in] Value0          - value to be added
+  @param[in] Value1          - value to be added
+  @param[in] ResetDDR        - Do we reset DDR?
+  @param[in] SelfRefresh     - Do we perform Self refresh?
+
+  @retval MrcStatus      - If it succeeds return mrcSuccess
+**/
+void
+SetCmdMargin (
+  IN MrcParameters *const MrcData,
+  IN const U8             ChBitMask,
+  IN const U8             Ranks,
+  IN const U8             Param,
+  IN const U8             Value0,
+  IN const U8             Value1,
+  IN U8                   ResetDDR,
+  IN const U8             SelfRefresh
+  )
+{
+  MrcControllerOut  *ControllerOut;
+  U8                Channel;
+  U8                RankMaskCh;
+  U8                Offset;
+
+  ControllerOut = &MrcData->SysOut.Outputs.Controller[0];
+  Offset        = 0;
+  if (SelfRefresh && ResetDDR) {
+    MRC_DEBUG_MSG (
+      &MrcData->SysIn.Inputs.Debug,
+      MSG_LEVEL_ERROR,
+      "WARNING SelfRefresh OR ResetDDR can be set at once...performing SelfRefresh\n"
+      );
+    ResetDDR = 0;
+  }
+
+  if (SelfRefresh) {
+    EnterSR (MrcData);
+  }
+  //
+  // Change Clock Timing
+  //
+  if ((Param == WrT) || (Param == WrTBox)) {
+    //
+    // Walk though all chs and ranks
+    //
+    for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+      if (ChBitMask & (MRC_BIT0 << Channel)) {
+        //
+        // determine which ranks from parameter "Ranks" exist in this channel
+        //
+        RankMaskCh = Ranks & ControllerOut->Channel[Channel].ValidRankBitMask;
+        if (RankMaskCh == 0) {
+          continue; // No Ranks in this channel
+        }
+
+        ShiftPIforCmdTraining (MrcData, Channel, MrcIterationClock, RankMaskCh, 3, Value0, 0);
+      }
+    }
+  }
+
+  if ((Param == WrV) || (Param == (WrTBox))) {
+    if (Param == WrV) {
+      Offset = Value0;
+    } else {
+      if (Param == WrTBox) {
+        Offset = ((2 * Value1) - 1) * 8;
+      }
+    }
+
+    UpdateVrefWaitTilStable (MrcData, 2, 0, Offset, 0);
+  }
+
+  if (ResetDDR) {
+    MrcResetSequence (MrcData);
+  } else if (SelfRefresh) {
+    ExitSR (MrcData);
+  }
+
+  return;
+}
+
+/**
+  Updates the value for following OptParamCliff variables:
+  drrd2rd=0, ddrd2rd=1, drwr2wr=2, ddwr2wr=3, drrd2wr=4, ddrd2wr=5, drwr2rd=6, ddwr2rd=7,
+  rdodtd=8, wrodtd=9, mcodts=10, mcodtd=11, rtl=12}
+
+  @param[in,out] MrcData    - Include all MRC global data.
+  @param[in]     Channel    - Channel to update the specificed parameter.
+  @param[in]     Byte       - Byte to update the specified parameter.
+  @param[in]     OptParam   - Parameter to update.
+  @param[in]     Off        - Value to offset the current setting.
+  @param[in]     UpdateHost - Switch to update the host structure with the new value.
+  @param[in]     SkipPrint  - Switch to skip debug prints.
+  @param[in]     RankMask   - Bit mask of Ranks to update.
+
+  @retval Nothing
+**/
+void
+UpdateTAParamOffset (
+  IN OUT MrcParameters *const MrcData,
+  IN     const U8             Channel,
+  IN     const U8             Byte,
+  IN     const U8             OptParam,
+  IN     const U8             Off,
+  IN     const U8             UpdateHost,
+  IN     const U8             SkipPrint,
+  IN     const U8             RankMask
+  )
+{
+  const MrcDebug                          *Debug;
+  MrcOutput                               *Outputs;
+  MrcChannelOut                           *ChannelOut;
+  U8                                      Rank;
+  U8                                      IOLat;
+  S8                                      New;
+  U32                                     Offset1;
+  U32                                     Offset2;
+  MCHBAR_CH0_CR_TC_BANK_RANK_A_STRUCT     TcBankRankA;
+  MCHBAR_CH0_CR_TC_BANK_RANK_B_STRUCT     TcBankRankB;
+  MCHBAR_CH0_CR_TC_BANK_RANK_C_STRUCT     TcBankRankC;
+  MCHBAR_CH0_CR_TC_BANK_RANK_D_STRUCT     TcBankRankD;
+  DDRDATA0CH0_CR_DDRCRDATACONTROL1_STRUCT DdrDataControl1;
+  MCHBAR_CH0_CR_SC_IO_LATENCY_STRUCT      ScIoLatency;
+  MCHBAR_CH0_CR_SC_ROUNDT_LAT_STRUCT      ScRoundtLat;
+
+  Debug       = &MrcData->SysIn.Inputs.Debug;
+  Outputs     = &MrcData->SysOut.Outputs;
+  ChannelOut  = &Outputs->Controller[0].Channel[Channel];
+
+  switch (OptParam) {
+  case drrd2rd:
+    //
+    // dr RD 2 RD Turn Around offsets
+    //
+    TcBankRankA.Data          = ChannelOut->MchbarBANKRANKA;
+    TcBankRankA.Bits.tRDRD_dr = Off;
+    Offset1 = MCHBAR_CH0_CR_TC_BANK_RANK_A_REG + ((MCHBAR_CH1_CR_TC_BANK_RANK_A_REG - MCHBAR_CH0_CR_TC_BANK_RANK_A_REG) * Channel);
+    MrcWriteCR (MrcData, Offset1, TcBankRankA.Data);
+    if (UpdateHost) {
+      ChannelOut->MchbarBANKRANKA = TcBankRankA.Data;
+    }
+    break;
+
+  case ddrd2rd:
+    //
+    // dd RD 2 RD Turn Around offsets
+    //
+    TcBankRankA.Data          = ChannelOut->MchbarBANKRANKA;
+    TcBankRankA.Bits.tRDRD_dd = Off;
+    Offset1 = MCHBAR_CH0_CR_TC_BANK_RANK_A_REG +
+      ((MCHBAR_CH1_CR_TC_BANK_RANK_A_REG - MCHBAR_CH0_CR_TC_BANK_RANK_A_REG) * Channel);
+    MrcWriteCR (MrcData, Offset1, TcBankRankA.Data);
+    if (UpdateHost) {
+      ChannelOut->MchbarBANKRANKA = TcBankRankA.Data;
+    }
+    break;
+
+  case drwr2wr:
+    //
+    // dr WR 2 WR Turn Around offsets
+    //
+    TcBankRankB.Data          = ChannelOut->MchbarBANKRANKB;
+    TcBankRankB.Bits.tWRWR_dr = Off;
+    Offset1 = MCHBAR_CH0_CR_TC_BANK_RANK_B_REG +
+      ((MCHBAR_CH1_CR_TC_BANK_RANK_B_REG - MCHBAR_CH0_CR_TC_BANK_RANK_B_REG) * Channel);
+    MrcWriteCR (MrcData, Offset1, TcBankRankB.Data);
+    if (UpdateHost) {
+      ChannelOut->MchbarBANKRANKB = TcBankRankB.Data;
+    }
+    break;
+
+  case ddwr2wr:
+    //
+    // dd WR 2 WR Turn Around offsets
+    //
+    TcBankRankB.Data          = ChannelOut->MchbarBANKRANKB;
+    TcBankRankB.Bits.tWRWR_dd = Off;
+    Offset1 = MCHBAR_CH0_CR_TC_BANK_RANK_B_REG +
+      ((MCHBAR_CH1_CR_TC_BANK_RANK_B_REG - MCHBAR_CH0_CR_TC_BANK_RANK_B_REG) * Channel);
+    MrcWriteCR (MrcData, Offset1, TcBankRankB.Data);
+    if (UpdateHost) {
+      ChannelOut->MchbarBANKRANKB = TcBankRankB.Data;
+    }
+    break;
+
+  case drrd2wr:
+    //
+    // dr RD 2 WR Turn Around offsets
+    //
+    TcBankRankC.Data          = ChannelOut->MchbarBANKRANKC;
+    TcBankRankC.Bits.tRDWR_dr = Off;
+    Offset1 = MCHBAR_CH0_CR_TC_BANK_RANK_C_REG +
+      ((MCHBAR_CH1_CR_TC_BANK_RANK_C_REG - MCHBAR_CH0_CR_TC_BANK_RANK_C_REG) * Channel);
+    MrcWriteCR (MrcData, Offset1, TcBankRankC.Data);
+    if (UpdateHost) {
+      ChannelOut->MchbarBANKRANKC = TcBankRankC.Data;
+    }
+    break;
+
+  case ddrd2wr:
+    //
+    // dd RD 2 WR Turn Around offsets
+    //
+    TcBankRankC.Data          = ChannelOut->MchbarBANKRANKC;
+    TcBankRankC.Bits.tRDWR_dd = Off;
+    Offset1 = MCHBAR_CH0_CR_TC_BANK_RANK_C_REG +
+      ((MCHBAR_CH1_CR_TC_BANK_RANK_C_REG - MCHBAR_CH0_CR_TC_BANK_RANK_C_REG) * Channel);
+    MrcWriteCR (MrcData, Offset1, TcBankRankC.Data);
+    if (UpdateHost) {
+      ChannelOut->MchbarBANKRANKC = TcBankRankC.Data;
+    }
+    break;
+
+  case drwr2rd:
+    //
+    // dr WR 2 RD Turn Around offsets
+    //
+    TcBankRankB.Data          = ChannelOut->MchbarBANKRANKB;
+    TcBankRankB.Bits.tWRRD_dr = Off;
+    Offset1 = MCHBAR_CH0_CR_TC_BANK_RANK_B_REG +
+      ((MCHBAR_CH1_CR_TC_BANK_RANK_B_REG - MCHBAR_CH0_CR_TC_BANK_RANK_B_REG) * Channel);
+    MrcWriteCR (MrcData, Offset1, TcBankRankB.Data);
+    if (UpdateHost) {
+      ChannelOut->MchbarBANKRANKB = TcBankRankB.Data;
+    }
+    break;
+
+  case ddwr2rd:
+    //
+    // dd WR 2 RD Turn Around offsets
+    //
+    TcBankRankB.Data          = ChannelOut->MchbarBANKRANKB;
+    TcBankRankB.Bits.tWRRD_dd = Off;
+    Offset1 = MCHBAR_CH0_CR_TC_BANK_RANK_B_REG +
+      ((MCHBAR_CH1_CR_TC_BANK_RANK_B_REG - MCHBAR_CH0_CR_TC_BANK_RANK_B_REG) * Channel);
+    MrcWriteCR (MrcData, Offset1, TcBankRankB.Data);
+    if (UpdateHost) {
+      ChannelOut->MchbarBANKRANKB = TcBankRankB.Data;
+    }
+    break;
+
+  case rdodtd:
+    TcBankRankD.Data                    = ChannelOut->MchbarBANKRANKD;
+    TcBankRankD.Bits.Odt_Read_Duration  = Off - 6; // Convert into Register values. 2'b00 = BL/2 + 2 (6 DCLKs
+    Offset1 = MCHBAR_CH0_CR_TC_BANK_RANK_D_REG +
+      ((MCHBAR_CH1_CR_TC_BANK_RANK_D_REG - MCHBAR_CH0_CR_TC_BANK_RANK_D_REG) * Channel);
+    MrcWriteCR (MrcData, Offset1, TcBankRankD.Data);
+    if (UpdateHost) {
+      ChannelOut->MchbarBANKRANKD = TcBankRankD.Data;
+    }
+    break;
+
+  case wrodtd:
+    TcBankRankD.Data = ChannelOut->MchbarBANKRANKD;
+#ifdef ULT_FLAG
+    if (Outputs->DdrType == MRC_DDR_TYPE_LPDDR3) {
+      TcBankRankD.UltBits.Odt_Write_Duration = Off - 6; // Convert into Register values. 2'b00 = BL/2 + 2 (6 DCLKs
+    } else
+#endif // ULT_FLAG
+    {
+      TcBankRankD.Bits.Odt_Write_Duration = Off - 6; // Convert into Register values. 2'b00 = BL/2 + 2 (6 DCLKs
+    }
+    Offset1 = MCHBAR_CH0_CR_TC_BANK_RANK_D_REG +
+      ((MCHBAR_CH1_CR_TC_BANK_RANK_D_REG - MCHBAR_CH0_CR_TC_BANK_RANK_D_REG) * Channel);
+    MrcWriteCR (MrcData, Offset1, TcBankRankD.Data);
+    if (UpdateHost) {
+      ChannelOut->MchbarBANKRANKD = TcBankRankD.Data;
+    }
+    break;
+
+  case mcodts:
+    //
+    // MC ODT delay
+    //
+    DdrDataControl1.Data  = ChannelOut->DqControl1[Byte].Data;
+    New                   = MrcSE ((U8) DdrDataControl1.Bits.OdtDelay, 4, 8) + Off; // SignExtend
+    if (New < -4) {
+      New = -4; // RcvEnPi[8:6] - 5 qclk Min
+    } else if (New > 6) {
+      New = 6; // RcvEnPi[8:6] + 5 qclk Max
+    }
+
+    DdrDataControl1.Bits.OdtDelay       = New;
+    DdrDataControl1.Bits.SenseAmpDelay  = New;
+    Offset1 = DDRDATA0CH0_CR_DDRCRDATACONTROL1_REG +
+      ((DDRDATA0CH1_CR_DDRCRDATACONTROL1_REG - DDRDATA0CH0_CR_DDRCRDATACONTROL1_REG) * Channel) +
+      ((DDRDATA1CH0_CR_DDRCRDATACONTROL1_REG - DDRDATA0CH0_CR_DDRCRDATACONTROL1_REG) * Byte);
+    MrcWriteCR (MrcData, Offset1, DdrDataControl1.Data);
+    if (UpdateHost) {
+      ChannelOut->DqControl1[Byte].Data = DdrDataControl1.Data;
+    }
+
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, (SkipPrint) ? "" : "%d\t", New);
+    break;
+
+  case mcodtd:
+    //
+    // Duration
+    //
+    DdrDataControl1.Data  = ChannelOut->DqControl1[Byte].Data;
+    New                   = (U8) DdrDataControl1.Bits.OdtDuration + Off;
+    if (New < 0) {
+      New = 0; // 11 tQCK Min
+    } else if (New > DDRDATA0CH0_CR_DDRCRDATACONTROL1_OdtDuration_MAX) {
+      New = DDRDATA0CH0_CR_DDRCRDATACONTROL1_OdtDuration_MAX; // 18 tQCK Max
+    }
+
+    DdrDataControl1.Bits.OdtDuration      = New;
+    DdrDataControl1.Bits.SenseAmpDuration = New;
+    //
+    // MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "mcodtd CRValue = 0x%x\n", DdrDataControl1.Bits.OdtDuration);
+    //
+    Offset1 = DDRDATA0CH0_CR_DDRCRDATACONTROL1_REG +
+      ((DDRDATA0CH1_CR_DDRCRDATACONTROL1_REG - DDRDATA0CH0_CR_DDRCRDATACONTROL1_REG) * Channel) +
+      ((DDRDATA1CH0_CR_DDRCRDATACONTROL1_REG - DDRDATA0CH0_CR_DDRCRDATACONTROL1_REG) * Byte);
+    MrcWriteCR (MrcData, Offset1, DdrDataControl1.Data);
+    if (UpdateHost) {
+      ChannelOut->DqControl1[Byte].Data = DdrDataControl1.Data;
+    }
+
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, (SkipPrint) ? "" : "%d\t", DdrDataControl1.Bits.OdtDuration);
+    break;
+
+  case rtl:
+    for (Rank = 0; Rank < MAX_RANK_IN_CHANNEL; Rank++) {
+      if (RankMask & (MRC_BIT0 << Rank)) {
+        //
+        // Update IO Latency & RoundTrip
+        //
+        IOLat = ChannelOut->IoLatency[Rank] - (ChannelOut->RTLatency[Rank] - Off);
+        if ((S8) IOLat < 0) {
+          MRC_DEBUG_MSG (Debug, MSG_LEVEL_WARNING, "IOLatency reached the Saturation point \n");
+        } else {
+          Offset1 = MCHBAR_CH0_CR_SC_IO_LATENCY_REG +
+            ((MCHBAR_CH1_CR_SC_IO_LATENCY_REG - MCHBAR_CH0_CR_SC_IO_LATENCY_REG) * Channel);
+          ScIoLatency.Data = MrcReadCR (MrcData, Offset1);
+          Offset2 = MCHBAR_CH0_CR_SC_ROUNDT_LAT_REG +
+            ((MCHBAR_CH1_CR_SC_ROUNDT_LAT_REG - MCHBAR_CH0_CR_SC_ROUNDT_LAT_REG) * Channel);
+          ScRoundtLat.Data = MrcReadCR (MrcData, Offset2);
+          switch (Rank) {
+          case 0:
+            ScIoLatency.Bits.IOLAT_R0D0 = IOLat;
+            ScRoundtLat.Bits.Lat_R0D0   = Off;
+            break;
+
+          case 1:
+            ScIoLatency.Bits.IOLAT_R1D0 = IOLat;
+            ScRoundtLat.Bits.Lat_R1D0   = Off;
+            break;
+
+          case 2:
+            ScIoLatency.Bits.IOLAT_R0D1 = IOLat;
+            ScRoundtLat.Bits.Lat_R0D1   = Off;
+            break;
+
+          case 3:
+            ScIoLatency.Bits.IOLAT_R1D1 = IOLat;
+            ScRoundtLat.Bits.Lat_R1D1   = Off;
+            break;
+
+          default:
+            break;
+          }
+
+          MrcWriteCR (MrcData, Offset1, ScIoLatency.Data);
+          MrcWriteCR (MrcData, Offset2, ScRoundtLat.Data);
+
+          //
+          // Update host
+          //
+          if (UpdateHost) {
+            ChannelOut->RTLatency[Rank] = Off;
+            ChannelOut->IoLatency[Rank] = IOLat;
+          }
+        }
+      }
+    }
+    break;
+
+  case srrd2rd:
+    //
+    // sr RD 2 RD Turn Around offsets
+    //
+    TcBankRankA.Data          = ChannelOut->MchbarBANKRANKA;
+    TcBankRankA.Bits.tRDRD    = Off;
+    Offset1 = MCHBAR_CH0_CR_TC_BANK_RANK_A_REG + ((MCHBAR_CH1_CR_TC_BANK_RANK_A_REG - MCHBAR_CH0_CR_TC_BANK_RANK_A_REG) * Channel);
+    MrcWriteCR (MrcData, Offset1, TcBankRankA.Data);
+    if (UpdateHost) {
+      ChannelOut->MchbarBANKRANKA = TcBankRankA.Data;
+    }
+    break;
+
+  case srrd2wr:
+    //
+    // sr RD 2 WR Turn Around offsets
+    //
+    TcBankRankC.Data          = ChannelOut->MchbarBANKRANKC;
+    TcBankRankC.Bits.tRDWR    = Off;
+    Offset1 = MCHBAR_CH0_CR_TC_BANK_RANK_C_REG +
+      ((MCHBAR_CH1_CR_TC_BANK_RANK_C_REG - MCHBAR_CH0_CR_TC_BANK_RANK_C_REG) * Channel);
+    MrcWriteCR (MrcData, Offset1, TcBankRankC.Data);
+    if (UpdateHost) {
+      ChannelOut->MchbarBANKRANKC = TcBankRankC.Data;
+    }
+    break;
+
+  default:
+    break;
+  }
+
+  MRC_DEBUG_MSG (
+    Debug,
+    MSG_LEVEL_NOTE,
+    ((OptParam != mcodtd) && (OptParam != mcodts) && (!SkipPrint)) ? "%d\t" : "",
+    Off
+    );
+
+  return;
+}
+
+/**
+  This function applies the new DRAM ODT settings
+  Walks through various optimizations to get the best result with new ODT values
+  This includes WrDS, RdODT, Eq, etc.
+  Updates Best* variables if this point if better than the prior points
+  chDone is both an input and output.  Reports which channels have a good enough value
+  if SkipRd is high, it will skip the read related functions (RdODT, RdEq, RdTiming)
+
+  @param[in]     MrcData              - Include all MRC global data.
+  @param[in,out] DimmOptPoints        - Structure of all the DIMM ODT optimal settings.
+  @param[in]     ChMask               - Channel to work on.
+  @param[in]     RankMask             - Rank to work on.
+  @param[in]     skipGRdOdt           - Used to skip RdODT.
+  @param[in]     RttNom               - Rtt_Nom value for each DIMM.
+  @param[in]     RttWr                - Rtt_Wr value for each DIMM.
+  @param[in]     GRdOdt               - CPU Global Read ODT.
+  @param[in]     OptParamTestList     - List of Opt test(Drive Strength, RxBias, TxEq, RxEq) to run.
+  @param[in]     OptParamTestListSize - Size of OptParamTestList.
+  @param[in]     SubPwrLimits         - Switch to apply power limits to the suboptimization.
+  @param[in]     skipOptTests         - Skips the suboptimization.
+  @param[in]     skipOptPrint         - Skip printing of the suboptimization steps.
+  @param[in]     RdCenter             - Switch to recenter read.
+  @param[in]     WrCenter             - Switch to recenter write.
+  @param[in]     inputBestMargin      - Array of the best margin for each test.
+  @param[in]     MarginsLength        - Length of inputBestMargin.
+  @param[in]     OffsetPoint          - Index inside inputBestMargin to start.
+
+  @retval Nothing.
+**/
+void
+TrainDimmOdtSetting (
+  IN     MrcParameters *const MrcData,
+  IN OUT DimmOptPoint         *DimmOptPoints,
+  IN     U8                   ChMask,
+  IN     U8                   RankMask,
+  IN     U8                   skipGRdOdt,
+  IN     U8                   RttNom[MAX_CHANNEL][MAX_DIMMS_IN_CHANNEL],
+  IN     U8                   RttWr[MAX_CHANNEL][MAX_DIMMS_IN_CHANNEL],
+  IN     S8                   GRdOdt,
+  IN     U8                   *OptParamTestList,
+  IN     U8                   OptParamTestListSize,
+  IN     BOOL                 SubPwrLimits,
+  IN     BOOL                 skipOptTests,
+  IN     BOOL                 skipOptPrint,
+  IN     BOOL                 RdCenter,
+  IN     BOOL                 WrCenter,
+  IN     void                *inputBestMargin,
+  IN     U8                   MarginsLength,
+  IN     U8                   OffsetPoint
+  )
+{
+  const MrcDebug    *Debug;
+  MrcOutput         *Outputs;
+  MrcControllerOut  *ControllerOut;
+  DimmOptPoint      *PointResults;
+  OptOffsetChByte   BestOffArr[SizeOfTCompOffset][MAX_RANK_IN_CHANNEL];
+  TCompOffset       OffsetType;
+  U8                dimm;
+  U8                rank;
+  U8                ValidRankMask;
+  U8                LocalRanks[MAX_CHANNEL];
+  U8                ChBitMask;
+  U8                Channel;
+  U8                ParamList[] = { RdV, RdT, WrV, WrT }; // List of parameters to margin
+  U8                TestListRd[]  = { RdV, RdT };
+  U8                TestListWr[]  = { WrV, WrT };
+  U8                *TestList;
+  U8                TestListSize;
+  U8                TScale[]      = { 1, 2, 1, 0, 0 };
+  U8                GScale[]      = { 1, 2, 0, 0, 0 };
+  U16               GPwrLimits[]  = { 520, 280, 0, 0, 0 };
+  U16               noPwrLimits[] = { 2480, 2240, 0, 0, 0 };
+  U8                *Scale;
+  U16               *PwrLimits;
+  S8                start;
+  S8                stop;
+  U8                i;
+  U8                t;
+  U8                ResultType;
+  U8                RecenterLC;
+  U8                OptParamLC;
+  BOOL              clipPowerLmt;
+  U16               *BestMargin;
+  U8                TestResultType[4] = { 0, 0, 0, 0 };
+
+  TestListSize                        = 0;
+  RecenterLC                          = 15;
+  OptParamLC                          = OPT_PARAM_LOOP_COUNT;
+  clipPowerLmt                        = 1;
+  Outputs       = &MrcData->SysOut.Outputs;
+  Debug         = &MrcData->SysIn.Inputs.Debug;
+  ControllerOut = &Outputs->Controller[0];
+
+  PointResults  = DimmOptPoints;
+  BestMargin    = (U16 *) inputBestMargin;
+  MrcOemMemorySet ((U8 *) BestOffArr, 0xffff, sizeof (BestOffArr));
+  MrcOemMemorySet ((U8 *) PointResults, 0xffff, sizeof (DimmOptPoint));
+  OffsetType = 0;
+
+  if (SubPwrLimits) {
+    //
+    // Use power limits and Trendline
+    //
+    Scale     = TScale;
+    PwrLimits = GPwrLimits;
+  } else {
+    //
+    //  No power limits and no TrendLine
+    //
+    Scale     = GScale;
+    PwrLimits = noPwrLimits;
+  }
+  //
+  // TrainDDROptParam already check the valid against host chRankBit mask
+  // Walk through channels, check if this point is redundant, set RttNom
+  //
+  ChMask &= Outputs->ValidChBitMask;
+  RankMask &= Outputs->ValidRankMask;
+  ValidRankMask = 0;
+  ChBitMask     = 0;
+  for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+    LocalRanks[Channel] = 0;
+    if (((MRC_BIT0 << Channel) & ChMask)) {
+      LocalRanks[Channel] = RankMask & ControllerOut->Channel[Channel].ValidRankBitMask;
+      if (LocalRanks[Channel]) {
+        ChBitMask |= MRC_BIT0 << Channel; // remove ch with no "active" ranks
+      }
+    }
+  }
+
+  for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+    for (dimm = 0; dimm < MAX_DIMMS_IN_CHANNEL; dimm++) {
+      PointResults->ODTSet.RttNom[Channel][dimm]  = RttNom[Channel][dimm];
+      PointResults->ODTSet.RttWr[Channel][dimm]   = RttWr[Channel][dimm];
+    }
+  }
+
+  PointResults->ODTSet.GRdOdt = GRdOdt;
+  UpdateOdtsValues (MrcData, ChBitMask, PointResults, skipGRdOdt, 0, 1, 1);
+  //
+  // update only DimmOdt and GROdt if not skipped.
+  // Recenter Timing
+  //
+  if (RdCenter) {
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_ERROR, "Re-center Read Vref\n");
+    ReadVoltageCentering2D (
+      MrcData,
+      Outputs->MarginResult,
+      ChBitMask,
+      RdV,
+      0,
+      0,
+      RecenterLC,
+      0
+      );
+    //
+    // We can add if status fail go to next point
+    //
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_ERROR, "Re-center Read Timing ChBitMask=%x\n", ChBitMask);
+    DataTimeCentering2D (
+      MrcData,
+      Outputs->MarginResult, // prev. margin results
+      ChBitMask,
+      RdT,
+      0, // EnPerBit,
+      0, // EnRxDutyCycle
+      0, // ResetPerBit
+      RecenterLC,
+      0  // En2D
+      );
+  }
+
+  if (WrCenter) {
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_ERROR, "Re-center Write Vref\n");
+    MrcWriteVoltageCentering2D (MrcData);
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_ERROR, "Re-center Write Timing ChBitMask=%x\n", ChBitMask);
+    DataTimeCentering2D (
+      MrcData,
+      Outputs->MarginResult, // prev. margin results
+      ChBitMask,
+      WrT,
+      0, // EnPerBit,
+      0, // EnRxDutyCycle
+      0, // ResetPerBit
+      RecenterLC,
+      0  // En2D
+      );
+  }
+  //
+  // @todo: we could check here if we have some reasonable amount of margin to play with
+  //
+  TestList  = ParamList;
+  PointResults->OptParamTestListSize = OptParamTestListSize;
+  for (t = 0; t < OptParamTestListSize; t++) {
+    //
+    // also apply the best offset to hw and host and inside also best offset related margin is saved in host struct
+    //
+    PointResults->OptParamTestList[t] = OptParamTestList[t];
+    // MRC_DEBUG_MSG (Debug, MSG_LEVEL_ERROR, "OptParamTestList[%d]=%d , %s\n",t,OptParamTestList[t],TOptParamOffsetString[OptParamTestList[t]]);
+    // MRC_DEBUG_MSG (Debug, MSG_LEVEL_ERROR, "OptParamTestList[%d]=%d OptParamTestListSize=%d\n",t,OptParamTestList[t],OptParamTestListSize);
+    switch (OptParamTestList[t]) {
+    case (OptWrDS):
+      start = -11;
+      stop  = 12;
+      TrainDDROptParam (
+        MrcData,
+        &BestOffArr[WrDSOfft][0],
+        ChBitMask,
+        RankMask,
+        OptWrDS,
+        TestListWr,
+        sizeof (TestListWr),
+        Scale,
+        PwrLimits,
+        start,
+        stop,
+        OptParamLC,
+        1,  // Repeats
+        skipOptPrint,
+        skipOptTests,
+        0,  // RdRd2Test
+        1   // GuardBand
+        );
+      TestList = TestListWr;
+      TestListSize = sizeof (TestListWr);
+      OffsetType = WrDSOfft;
+      PointResults->BestOptOff[WrDSOfft][0] = BestOffArr[WrDSOfft][0];
+      break;
+
+    case (OptRdOdt):
+      start = -10;
+      stop  = 6;
+      TrainDDROptParam (
+        MrcData,
+        &BestOffArr[RdOdtOfft][0],
+        ChBitMask,
+        RankMask,
+        OptRdOdt,
+        TestListRd,
+        sizeof (TestListRd),
+        Scale,
+        PwrLimits,
+        start,
+        stop,
+        OptParamLC,
+        1,            // Repeats
+        skipOptPrint,
+        skipOptTests,
+        RdRdTA,       // RdRd2Test
+        0             // GuardBand
+        );
+      TestList      = TestListRd;
+      TestListSize  = sizeof (TestListRd);
+      OffsetType    = RdOdtOfft;
+      PointResults->BestOptOff[RdOdtOfft][0] = BestOffArr[RdOdtOfft][0];
+      break;
+
+    case (OptSComp):
+    case (OptTComp):
+      break;
+
+    case (OptTxEq):
+      start = 0;
+      stop  = 11;
+      for (rank = 0; rank < MAX_RANK_IN_CHANNEL; rank++) {
+        if (!((MRC_BIT0 << rank) & RankMask)) {
+          continue; // check if rank at least on one channel
+        }
+
+        TrainDDROptParam (
+          MrcData,
+          &BestOffArr[TxEqOfft][rank],
+          ChBitMask,
+          (MRC_BIT0 << rank),
+          OptTxEq,
+          TestListWr,
+          sizeof (TestListWr),
+          Scale,
+          PwrLimits,
+          start,
+          stop,
+          OptParamLC,
+          1,            // Repeats
+          skipOptPrint,
+          skipOptTests,
+          0,            // RdRd2Test
+          2             // GuardBand
+          );
+        PointResults->BestOptOff[TxEqOfft][rank] = BestOffArr[TxEqOfft][rank];
+        for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+          if (!((MRC_BIT0 << rank) & LocalRanks[Channel])) {
+            continue;
+            //
+            // check if the rank exist in this ch
+            //
+          }
+
+          for (i = 0; i < sizeof (TestListWr); i++) {
+            //
+            // track min margin per ch
+            //
+            if (BestOffArr[TxEqOfft][rank].Margins[i][Channel] < BestOffArr[TxEqOfft][0].Margins[i][Channel]) {
+              BestOffArr[TxEqOfft][0].Margins[i][Channel] = BestOffArr[TxEqOfft][rank].Margins[i][Channel];
+            }
+          }
+        }
+      }
+
+      TestList      = TestListWr;
+      TestListSize  = sizeof (TestListWr);
+      OffsetType    = TxEqOfft;
+      break;
+
+    case (OptRxEq):
+      start = 0;
+      stop  = 14;
+      for (rank = 0; rank < MAX_RANK_IN_CHANNEL; rank++) {
+        if (!((MRC_BIT0 << rank) & RankMask)) {
+          continue; // check if rank at least on one channel
+        }
+
+        TrainDDROptParam (
+          MrcData,
+          &BestOffArr[RxEqOfft][rank],
+          ChBitMask,
+          (MRC_BIT0 << rank),
+          OptRxEq,
+          TestListRd,
+          sizeof (TestListRd),
+          Scale,
+          noPwrLimits,
+          start,
+          stop,
+          OptParamLC,
+          1,       // Repeats
+          skipOptPrint,
+          skipOptTests,
+          RdRdTA,  // RdRd2Test
+          0        // GuardBand
+          );
+        PointResults->BestOptOff[RxEqOfft][rank] = BestOffArr[RxEqOfft][rank];
+        for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+          if (!((1 << rank) & LocalRanks[Channel])) {
+            continue; // check if the rank exist in this ch
+          }
+
+          for (i = 0; i < sizeof (TestListRd); i++) {
+            //
+            // track min margin per ch and asign to rank0
+            //
+            if (BestOffArr[RxEqOfft][rank].Margins[i][Channel] < BestOffArr[RxEqOfft][0].Margins[i][Channel]) {
+              BestOffArr[RxEqOfft][0].Margins[i][Channel] = BestOffArr[RxEqOfft][rank].Margins[i][Channel];
+            }
+          }
+        }
+      }
+
+      TestList      = TestListRd;
+      TestListSize  = sizeof (TestListRd);
+      OffsetType    = RxEqOfft;
+      break;
+
+    case (OptRxBias):
+      start = 0;
+      stop  = 7;
+      TrainDDROptParam (
+        MrcData,
+        &BestOffArr[RdSAmpOfft][0],
+        ChBitMask,
+        RankMask,
+        OptRxBias,
+        TestListRd,
+        sizeof (TestListRd),
+        Scale,
+        PwrLimits,
+        start,
+        stop,
+        OptParamLC,
+        1,       // Repeats
+        skipOptPrint,
+        skipOptTests,
+        RdRdTA,  // RdRd2Test
+        0        // GuardBand
+        );
+      TestList      = TestListRd;
+      TestListSize  = sizeof (TestListRd);
+      OffsetType    = RdSAmpOfft;
+      PointResults->BestOptOff[RdSAmpOfft][0] = BestOffArr[RdSAmpOfft][0];
+      break;
+
+    case (OptDimmOdt):
+      break;
+
+    case (OptDimmOdtWr):
+      break;
+
+    default:
+      MRC_DEBUG_MSG (Debug, MSG_LEVEL_ERROR, "OptParam Test not valid\n");
+
+    }
+
+    for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+      if (!(LocalRanks[Channel])) {
+        continue; // check if the active rank run this ch
+      }
+      //
+      // run through all BestOff[optParam][0] and track min[RdV,RdT,WrV,WrT]
+      //
+      for (i = 0; i < TestListSize; i++) {
+        ResultType                  = GetMarginResultType (TestList[i]);
+        TestResultType[ResultType]  = TestList[i]; // indicate which test we run and create the reverse dic
+        //
+        //we need to update only last results
+        //
+        PointResults->Test[ResultType][Channel] = BestOffArr[OffsetType][0].Margins[i][Channel];
+      }
+    }
+  } // end for OptParamTest
+  //
+  // assign the point for passing to the FindOptimalTradeOff function
+  //
+  i                       = 0;
+  PointResults->NumTests  = 0;
+  for (t = 0; t < 4; t++) {
+    //
+    // ResultType=GetMarginResultType(TestList[i]);
+    //
+    if (TestResultType[t] == 0) {
+      continue; // can only be 1,2,4,5
+    } else {
+      PointResults->TestList[i] = TestResultType[t];
+      PointResults->NumTests++;
+      //
+      // *(BestMargin+i*MarginsLength+OffsetPoint)=PointResults->Test[t][Channel];
+      // sorting test for TradeOff
+      //
+      for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+        if (!(LocalRanks[Channel])) {
+          continue; // check if the active rank run this ch
+        }
+
+        if (clipPowerLmt) {
+          if (PointResults->Test[t][Channel] > UpmPwrLimitValue (MrcData, TestResultType[t], PowerLimit)) {
+            PointResults->Points2Trade[i][Channel] = UpmPwrLimitValue (MrcData, TestResultType[t], PowerLimit);
+          } else {
+            PointResults->Points2Trade[i][Channel] = PointResults->Test[t][Channel];
+          }
+        } else {
+          PointResults->Points2Trade[i][Channel] = PointResults->Test[t][Channel];
+        }
+        //
+        // MRC_DEBUG_MSG (Debug, MSG_LEVEL_ERROR, "PointResults->TestList[%d]=%d PointResults->Test[test index=%d][channel=%d] =%d\n",i,PointResults->TestList[i],t,Channel,PointResults->Test[t][Channel]);
+        //
+      }
+
+      i++;
+    }
+  }
+  //
+  // MRC_DEBUG_MSG (Debug, MSG_LEVEL_ERROR, "PointResults->NumTests =%d\n",PointResults->NumTests);
+  //
+  return;
+}
+
+/**
+  This function applies an offset to the global compensation logic.
+  Reruns Compensation and returns the new comp value
+
+  @param[in,out] MrcData         - Include all MRC global data.
+  @param[in]     param           - Parameter defining the desired global compensation logic
+  @param[in]     offset          - Value to apply
+  @param[in]     UpdateHost      - Desides if MrcData has to be updated
+
+  @retval Returns the new comp value.
+**/
+U32
+UpdateCompGlobalOffset (
+  IN OUT MrcParameters *const MrcData,
+  IN     const U8             param,
+  IN     const U32            offset,
+  IN     const U8             UpdateHost
+  )
+{
+  const MrcDebug                          *Debug;
+  MrcOutput                               *Outputs;
+  MrcControllerOut                        *ControllerOut;
+  MrcChannelOut                           *ChannelOut;
+  DDRCOMP_CR_DDRCRCOMPCTL0_STRUCT         DdrCrCompCtl0;
+  DDRCOMP_CR_DDRCRCOMPCTL1_STRUCT         DdrCrCompCtl1;
+  PCU_CR_M_COMP_PCU_STRUCT                PcuCrMComp;
+  DDRCOMP_CR_DDRCRDATACOMP0_STRUCT        DdrCrDataComp0;
+  DDRCOMP_CR_DDRCRDATACOMP1_STRUCT        DdrCrDataComp1;
+  DDRCOMP_CR_DDRCRCMDCOMP_STRUCT          DdrCrCmdComp;
+  DDRCOMP_CR_DDRCRCTLCOMP_STRUCT          DdrCrCtlComp;
+  DDRCOMP_CR_DDRCRCLKCOMP_STRUCT          DdrCrClkComp;
+  DDRDATACH0_CR_DDRCRDATACONTROL0_STRUCT  DdrCrDataControl0;
+  DDRCOMP_CR_DDRCRCOMPCTL0_STRUCT         DdrCrCompCtl0_Temp;
+  U32                                     RegOffset;
+  U8                                      Channel;
+
+  Outputs                 = &MrcData->SysOut.Outputs;
+  ControllerOut           = &Outputs->Controller[0];
+  Debug                   = &MrcData->SysIn.Inputs.Debug;
+  DdrCrCompCtl0.Data      = Outputs->CompCtl0;
+  DdrCrCompCtl1.Data      = Outputs->CompCtl1;
+  DdrCrDataControl0.Data  = 0;
+
+  //
+  // Update offset in local CR variable
+  //
+  switch (param) {
+  case RdOdt:
+    //
+    // Disable FixOdt feature before changing this param
+    //
+    DdrCrCompCtl0.Bits.FixOdtD = 0;
+    //
+    // Apply Comp Offset to RdOdt
+    //
+    DdrCrCompCtl0.Bits.DqOdtVref = offset;
+    break;
+
+  case WrDS:
+    //
+    // Apply Comp Offset to WrDS-DQ
+    //
+    DdrCrCompCtl0.Bits.DqDrvVref = offset;
+    break;
+
+  case WrDSCmd:
+    //
+    // Apply Comp Offset to WrDS-CMD
+    //
+    DdrCrCompCtl0.Bits.CmdDrvVref = offset;
+    break;
+
+  case WrDSCtl:
+    //
+    // Apply Comp Offset to WrDS-CTL
+    //
+    DdrCrCompCtl0.Bits.CtlDrvVref = offset;
+    break;
+
+  case WrDSClk:
+    //
+    // Apply Comp Offset to WrDS-CLK
+    //
+    DdrCrCompCtl0.Bits.ClkDrvVref = offset;
+    break;
+
+  case SCompDq:
+    //
+    // Apply Comp Offset to Scomp-DQ
+    //
+    DdrCrCompCtl1.Bits.DqScompCells = offset;
+    DdrCrCompCtl1.Bits.DqScompPC    = offset >> 4;
+    break;
+
+  case SCompCmd:
+    //
+    // Apply Comp Offset to Scomp-CMD
+    //
+    DdrCrCompCtl1.Bits.CmdScompCells  = offset;
+    DdrCrCompCtl1.Bits.CmdScompPC     = offset >> 4;
+    break;
+
+  case SCompCtl:
+    //
+    // Apply Comp Offset to Scomp-CTL
+    //
+    DdrCrCompCtl1.Bits.CtlScompCells  = offset;
+    DdrCrCompCtl1.Bits.CtlScompPC     = offset >> 4;
+    break;
+
+  case SCompClk:
+    //
+    // Apply Comp Offset to Scomp-CLK
+    //
+    DdrCrCompCtl1.Bits.ClkScompCells  = offset;
+    DdrCrCompCtl1.Bits.ClkScompPC     = offset >> 4;
+    break;
+
+  case DisOdtStatic:
+    //
+    // disable static read Otd legs
+    //
+    DdrCrCompCtl0.Bits.DisableOdtStatic = offset;
+    for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+      ChannelOut = &ControllerOut->Channel[Channel];
+      DdrCrDataControl0.Data = ChannelOut->DqControl0.Data;
+      DdrCrDataControl0.Bits.DisableOdtStatic = offset; // apply to bytes fubs
+      RegOffset = DDRDATACH0_CR_DDRCRDATACONTROL0_REG +
+        ((DDRDATACH1_CR_DDRCRDATACONTROL0_REG - DDRDATACH0_CR_DDRCRDATACONTROL0_REG) * Channel);
+      MrcWriteCrMulticast (MrcData, RegOffset, DdrCrDataControl0.Data);
+      if (UpdateHost) {
+        ChannelOut->DqControl0.Data = DdrCrDataControl0.Data;
+      }
+    }
+    break;
+
+  default:
+    break;
+  }
+  //
+  // Update the Comp Offsets and Host Structure
+  //
+  MrcWriteCR (MrcData, DDRCOMP_CR_DDRCRCOMPCTL0_REG, DdrCrCompCtl0.Data);
+  MrcWriteCR (MrcData, DDRCOMP_CR_DDRCRCOMPCTL1_REG, DdrCrCompCtl1.Data);
+  if (UpdateHost) {
+    Outputs->CompCtl0 = DdrCrCompCtl0.Data;
+    Outputs->CompCtl1 = DdrCrCompCtl1.Data;
+  }
+  //
+  // Run Compensation
+  // Start Comp Engine
+  //
+  PcuCrMComp.Data               = 0;
+  PcuCrMComp.Bits.COMP_FORCE    = 1;
+  PcuCrMComp.Bits.COMP_INTERVAL = MIN (COMP_INT, PCU_CR_M_COMP_PCU_COMP_INTERVAL_MAX);
+  PcuCrMComp.Bits.COMP_DISABLE  = 1;
+  MrcWriteCR (MrcData, PCU_CR_M_COMP_PCU_REG, PcuCrMComp.Data);
+  MrcWait (MrcData, 8 * HPET_1US); // Wait for Comp to Complete
+  if (param == RdOdt) {
+    //
+    // we check if we close to saturation and try dis/en the static legs
+    //
+    DdrCrDataComp1.Data = MrcReadCR (MrcData, DDRCOMP_CR_DDRCRDATACOMP1_REG);
+    if ((DdrCrDataComp1.Bits.RcompOdtUp < 16) || (DdrCrDataComp1.Bits.RcompOdtUp > 48)) {
+      //
+      // disable/enable  static read Otd legs
+      //
+      if (DdrCrDataComp1.Bits.RcompOdtUp < 16) {
+        DdrCrCompCtl0.Bits.DisableOdtStatic = 1;
+      } else {
+        DdrCrCompCtl0.Bits.DisableOdtStatic = 0;
+      }
+      //
+      // Update the Comp Offsets and Host Structure
+      //
+      for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+        ChannelOut  = &ControllerOut->Channel[Channel];
+        ChannelOut->DqControl0.Bits.DisableOdtStatic = DdrCrCompCtl0.Bits.DisableOdtStatic; // apply to bytes fubs
+        RegOffset = DDRDATACH0_CR_DDRCRDATACONTROL0_REG +
+          ((DDRDATACH1_CR_DDRCRDATACONTROL0_REG - DDRDATACH0_CR_DDRCRDATACONTROL0_REG) * Channel);
+        //
+        // MRC_DEBUG_MSG (Debug, MSG_LEVEL_ERROR, "DdrCrDataControl0.Bits.DisableOdtStatic=%d\n",DdrCrDataControl0.Bits.DisableOdtStatic);
+        //
+        MrcWriteCrMulticast (MrcData, RegOffset, ChannelOut->DqControl0.Data);
+      }
+
+      MrcWriteCR (MrcData, DDRCOMP_CR_DDRCRCOMPCTL0_REG, DdrCrCompCtl0.Data);
+      //
+      // host need to always be updated with static state
+      //
+      DdrCrCompCtl0_Temp.Data                  = Outputs->CompCtl0;
+      DdrCrCompCtl0_Temp.Bits.DisableOdtStatic = DdrCrCompCtl0.Bits.DisableOdtStatic;
+      Outputs->CompCtl0                        = DdrCrCompCtl0_Temp.Data;
+      //
+      // Run Compensation
+      // Start Comp Engine
+      //
+      MrcWriteCR (MrcData, PCU_CR_M_COMP_PCU_REG, PcuCrMComp.Data);
+      MrcWait (MrcData, 8 * HPET_1US); // Wait for Comp to Complete
+    }
+
+  }
+  //
+  // Return the new comp code
+  //
+  switch (param) {
+  case DisOdtStatic:
+  case RdOdt:
+    DdrCrDataComp1.Data = MrcReadCR (MrcData, DDRCOMP_CR_DDRCRDATACOMP1_REG);
+    //
+    // re-Enable FixOdt feature after changing this param
+    //
+    DdrCrCompCtl0.Bits.DqOdtUpDnOff = DdrCrDataComp1.Bits.RcompOdtDown - DdrCrDataComp1.Bits.RcompOdtUp;
+    DdrCrCompCtl0.Bits.FixOdtD      = 1;
+    MrcWriteCR (MrcData, DDRCOMP_CR_DDRCRCOMPCTL0_REG, DdrCrCompCtl0.Data);
+    if (UpdateHost) {
+      Outputs->CompCtl0 = DdrCrCompCtl0.Data;
+    }
+    return DdrCrDataComp1.Bits.RcompOdtUp;
+
+  case WrDS:
+  case SCompDq:
+    DdrCrDataComp0.Data = MrcReadCR (MrcData, DDRCOMP_CR_DDRCRDATACOMP0_REG);
+    return (param == WrDS) ? DdrCrDataComp0.Bits.RcompDrvUp : DdrCrDataComp0.Bits.SlewRateComp;
+
+  case WrDSCmd:
+  case SCompCmd:
+    DdrCrCmdComp.Data = MrcReadCR (MrcData, DDRCOMP_CR_DDRCRCMDCOMP_REG);
+    return (param == WrDSCmd) ? DdrCrCmdComp.Bits.RcompDrvUp : DdrCrCmdComp.Bits.Scomp;
+
+  case WrDSCtl:
+  case SCompCtl:
+    DdrCrCtlComp.Data = MrcReadCR (MrcData, DDRCOMP_CR_DDRCRCTLCOMP_REG);
+    return (param == WrDSCtl) ? DdrCrCtlComp.Bits.RcompDrvUp : DdrCrCtlComp.Bits.Scomp;
+
+  case WrDSClk:
+  case SCompClk:
+    DdrCrClkComp.Data = MrcReadCR (MrcData, DDRCOMP_CR_DDRCRCLKCOMP_REG);
+    return (param == WrDSClk) ? DdrCrClkComp.Bits.RcompDrvUp : DdrCrClkComp.Bits.Scomp;
+
+  default:
+    break;
+  }
+
+  return 0;
+}
+
+/**
+  Programs Delay/Duration for the SenseAmp and MCODT based on RcvEn timing
+  Provide GuardBand > 0 if needed to be more conservative in timing
+  Main goal is to optimize power
+
+  @param[in,out] MrcData   - Include all MRC global data.
+  @param[in]     GuardBand - Input parameter with more conservative value
+
+  @retval Nothing
+**/
+void
+UpdateSampOdtTiming (
+  IN OUT MrcParameters *const MrcData,
+  IN     const U8             GuardBand
+  )
+
+{
+  MrcOutput                               *Outputs;
+  MrcDebug                                *Debug;
+  MrcControllerOut                        *ControllerOut;
+  MrcChannelOut                           *ChannelOut;
+  U16                                     *CurRcvEn;
+  U8                                      Channel;
+  U8                                      Byte;
+  U8                                      rank;
+  U16                                     MaxRcvEn;
+  U16                                     MinRcvEn;
+  U32                                     Offset;
+  U32                                     SWakeUp;
+  U32                                     SAWakeUppS;  // Round up to nearest Qclk
+  S8                                      SOn;         // SenseAmpDelay
+  S8                                      OOn;         // OdtDelay
+  S32                                     SOff;        // SenseAmpDuration
+  S32                                     OOff;        // OdtDuration
+  DDRDATA0CH0_CR_DDRCRDATACONTROL1_STRUCT *DqControl1;
+
+  SAWakeUppS    = 1250;
+  Outputs       = &MrcData->SysOut.Outputs;
+  Debug         = &MrcData->SysIn.Inputs.Debug;
+  ControllerOut = &Outputs->Controller[0];
+
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "UpdateSampOdtTiming: GuardBand = %d\n", GuardBand);
+  
+  for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+    if (MrcChannelExist (Outputs, Channel)) {
+      ChannelOut = &ControllerOut->Channel[Channel];
+      MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Ch %d\tOdtOn\tOdtOff\tSAmpOn\tSAmpOff\n", Channel);
+
+      for (Byte = 0; Byte < Outputs->SdramCount; Byte++) {
+        MaxRcvEn  = 0;
+        MinRcvEn  = 512;
+
+        for (rank = 0; rank < MAX_RANK_IN_CHANNEL; rank++) {
+          if (MrcRankInChannelExist (MrcData, rank, Channel)) {
+            CurRcvEn = &ChannelOut->RcvEn[rank][Byte];
+            if (MaxRcvEn < *CurRcvEn) {
+              MaxRcvEn = *CurRcvEn;
+            }
+
+            if (MinRcvEn > *CurRcvEn) {
+              MinRcvEn = *CurRcvEn;
+            }
+          }
+        }
+        //
+        // Round Max to nearest cycle
+        //
+        MaxRcvEn = (MaxRcvEn >> 6) + 1;
+
+        //
+        // SENSE AMP CAN ONLY BE ON WHEN ODT IS ON FOR EOS REASONS.
+        // SWakeUp = (U32)( (SAWakeUppS + Outputs->Qclkps - 1) / Outputs->Qclkps );
+        // SOn = MinRcvEn - SWakeUp - GuardBand;
+        // OOn = MinRcvEn - 2 - GuardBand;
+        //
+        SWakeUp = (U32) ((64 * SAWakeUppS) / Outputs->Qclkps); // Convert to PI codes
+        //
+        // Turn On ODT & Samp at least 2 Qclks before earlier RcvEn Rise
+        //
+        if (SWakeUp < 128) {
+          SWakeUp = 128; // at least 2-Qclks
+        }
+
+        OOn = SOn = (S8) ((MinRcvEn - SWakeUp) >> 6) - GuardBand;
+        //
+        // SenseAmp Delay
+        //
+        if (SOn < -4) {
+          SOn = -4; // RcvEnPi[8:6] - 5 qclk
+        } else if (SOn > 6) {
+          SOn = 6; // RcvEnPi[8:6] + 5 qclk
+        }
+        //
+        // OdtDelay
+        //
+        if (OOn < -4) {
+          OOn = -4; // RcvEnPi[8:6] - 5 qclk
+        } else if (OOn > 6) {
+          OOn = 6; // RcvEnPi[8:6] + 5 qclk
+        }
+        //
+        // Turn Off Samp 1 qclk after postamble
+        // Turn Off ODT 1 qclk after postamble
+        // Program the duration to leave Odt/Samp On
+        //      OnBeforeRcvEn   BL+Post  AfterPost   CR Encoding
+        //
+        SOff  = (MaxRcvEn - SOn) + (8 + 1) + 1 + GuardBand - 11;
+        OOff  = (MaxRcvEn - OOn) + (8 + 1) + 1 + GuardBand - 11;
+
+        if (SOff < 0) {
+          SOff = 0; // 11 tQCK Min
+        } else if (SOff > 7) {
+          SOff = 7; // 18 tQCK Max
+        }
+
+        if (OOff < 0) {
+          OOff = 0;  // 11 tQCK Min
+        } else if (OOff > 7) {
+          OOff = 7;  // 18 tQCK mAx
+        }
+
+        DqControl1 = &ChannelOut->DqControl1[Byte];
+        DqControl1->Bits.OdtDelay         = OOn;
+        DqControl1->Bits.OdtDuration      = OOff;
+        DqControl1->Bits.SenseAmpDelay    = SOn;
+        DqControl1->Bits.SenseAmpDuration = SOff;
+        Offset = DDRDATA0CH0_CR_DDRCRDATACONTROL1_REG +
+          ((DDRDATA1CH0_CR_DDRCRDATACONTROL1_REG - DDRDATA0CH0_CR_DDRCRDATACONTROL1_REG) * Byte) +
+          ((DDRDATA0CH1_CR_DDRCRDATACONTROL1_REG - DDRDATA0CH0_CR_DDRCRDATACONTROL1_REG) * Channel);
+        MrcWriteCR (MrcData, Offset, DqControl1->Data);
+        
+        MRC_DEBUG_MSG (
+          Debug,
+          MSG_LEVEL_NOTE,
+          "%d:\t%d\t%d\t%d\t%d\n",
+          Byte,
+          DqControl1->Bits.OdtDelay,
+          DqControl1->Bits.OdtDuration,
+          DqControl1->Bits.SenseAmpDelay,
+          DqControl1->Bits.SenseAmpDuration
+        );
+      }
+    }
+  }
+
+  return;
+}
+
+/**
+  Turns off unused portions of the slave DLL to save power
+
+  @param[in,out] MrcData - Include all MRC global data.
+
+  @retval Nothing
+**/
+void
+UpdateSlaveDLLLength (
+  IN OUT MrcParameters *const MrcData
+  )
+{
+  MrcOutput         *Outputs;
+  MrcControllerOut  *ControllerOut;
+  MrcChannelOut     *ChannelOut;
+  U8                *CurRxDqs;
+  U32               Offset;
+  U8                Channel;
+  U8                byte;
+  U8                rank;
+  U8                MaxPi;
+
+  Outputs       = &MrcData->SysOut.Outputs;
+  ControllerOut = &Outputs->Controller[0];
+  for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+    if (MrcChannelExist (Outputs, Channel)) {
+      ChannelOut = &ControllerOut->Channel[Channel];
+      for (byte = 0; byte < Outputs->SdramCount; byte++) {
+        MaxPi = 0;
+        for (rank = 0; rank < MAX_RANK_IN_CHANNEL; rank++) {
+          if (MrcRankInChannelExist (MrcData, rank, Channel)) {
+            CurRxDqs = &ChannelOut->RxDqsP[rank][byte];
+            if (MaxPi < *CurRxDqs) {
+              MaxPi = *CurRxDqs;
+            }
+
+            CurRxDqs = &ChannelOut->RxDqsN[rank][byte];
+            if (MaxPi < *CurRxDqs) {
+              MaxPi = *CurRxDqs;
+            }
+          }
+        }
+        //
+        // Update SlaveDLL Length for power Savings
+        // Calculate which segments to turn off:
+        // NEW (OFF: 0, PI<48: 0x2, PI<32: 0x4, PI<16: 0x6)
+        // results are:   0, 2 , 4 or 6
+        //
+        ChannelOut->DqControl1[byte].Bits.SdllSegmentDisable = ((7 - (MaxPi >> 3)) &~MRC_BIT0);
+        Offset = DDRDATA0CH0_CR_DDRCRDATACONTROL1_REG +
+          ((DDRDATA1CH0_CR_DDRCRDATACONTROL1_REG - DDRDATA0CH0_CR_DDRCRDATACONTROL1_REG) * byte) +
+          ((DDRDATA0CH1_CR_DDRCRDATACONTROL1_REG - DDRDATA0CH0_CR_DDRCRDATACONTROL1_REG) * Channel);
+        MrcWriteCR (MrcData, Offset, ChannelOut->DqControl1[byte].Data);
+      }
+    }
+  }
+
+  return;
+}
+
+#ifdef TRAD_FLAG
+/**
+  Update Internal clocks on setting if needed.
+
+  @param[in,out] MrcData - Include all MRC global data.
+
+  @retval Nothing
+**/
+void
+UpdateInternalClksOn (
+  IN OUT MrcParameters *const MrcData
+  )
+{
+  const MrcDebug    *Debug;
+  MrcOutput         *Outputs;
+  MrcControllerOut  *ControllerOut;
+  MrcChannelOut     *ChannelOut;
+  U32               Offset;
+  U8                Channel;
+  U8                Byte;
+  S8                SOn;  // SenseAmpDelay
+  S8                OOn;  // OdtDelay
+  S32               SOff; // SenseAmpDuration
+  S32               OOff; // OdtDuration
+  U8                InternalClkOn;
+
+  Debug         = &MrcData->SysIn.Inputs.Debug;
+  Outputs       = &MrcData->SysOut.Outputs;
+  ControllerOut = &Outputs->Controller[0];
+  for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+    if (MrcChannelExist (Outputs, Channel)) {
+      InternalClkOn = 0;
+      ChannelOut    = &ControllerOut->Channel[Channel];
+      for (Byte = 0; Byte < Outputs->SdramCount; Byte++) {
+        OOn   = MrcSE ((U8) ChannelOut->DqControl1[Byte].Bits.OdtDelay, 4, 8);
+        OOff  = ChannelOut->DqControl1[Byte].Bits.OdtDuration;
+        SOn   = MrcSE ((U8) ChannelOut->DqControl1[Byte].Bits.SenseAmpDelay, 4, 8);
+        SOff  = ChannelOut->DqControl1[Byte].Bits.SenseAmpDuration;
+
+        //
+        // Check if OdtDelay + OdtDuration >= 7 or if SADelay + SADuration >= 7
+        //
+        if (((OOn + OOff) >= 7) || ((SOn + SOff) >= 7)) {
+          InternalClkOn = 1;
+          MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "ODTOn = %d, ODTOff = %d\n", OOn, OOff);
+          MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "SAOn  = %d, SAOff  = %d\n", SOn, SOff);
+          break;
+        }
+      }
+
+      ChannelOut->DqControl0.Bits.InternalClocksOn = InternalClkOn;
+      Offset = DDRDATACH0_CR_DDRCRDATACONTROL0_REG +
+        ((DDRDATACH1_CR_DDRCRDATACONTROL0_REG - DDRDATACH0_CR_DDRCRDATACONTROL0_REG) * Channel);
+      MrcWriteCrMulticast (MrcData, Offset, ChannelOut->DqControl0.Data);
+      MRC_DEBUG_MSG (
+        Debug,
+        MSG_LEVEL_NOTE,
+        "C%dDdrCrDataControl0.Data  = 0x%x\n",
+        Channel,
+        ChannelOut->DqControl0.Data
+        );
+    }
+  }
+
+  return;
+}
+#endif // TRAD_FLAG
+
+/**
+  This function Shifts the CMD timing.
+  NOTE: ONLY one, ResetDDR or SelfRefresh can be set inside this function
+
+  @param[in,out] MrcData     - Include all MRC global data.
+  @param[in]     Ranks       - Parameter defining the desired global compensation logic
+  @param[in]     offset      - per channel Value to shift picode for
+  @param[in]     ResetDDR    - Do we reset DDR?
+  @param[in]     SelfRefresh - Do we perform Self refresh?
+  @param[in]     UpdateHost  - Determines if MrcData has to be updated
+  @param[in]     SkipTx      - Determines if TX update should be skipped
+                               @todo: SkipTx is NOT USED at this time and we don't skip it anyway
+
+  @retval MrcStatus       - If it succeeds return mrcSuccess
+**/
+MrcStatus
+ShiftCh2Ch (
+  IN OUT MrcParameters *const MrcData,
+  IN     const U8             Ranks,
+  IN     const U8 *const      offset,
+  IN     U8                   ResetDDR,
+  IN     const U8             SelfRefresh,
+  IN     const U8             UpdateHost,
+  IN     const U8             SkipTx
+  )
+{
+  const MrcDebug    *Debug;
+  MrcOutput         *Outputs;
+  MrcControllerOut  *ControllerOut;
+  MrcChannelOut     *ChannelOut;
+  MrcStatus         Status;
+  U8                Channel;
+  U8                Rank;
+  U8                RankMaskCh;
+  S32               NewValue;
+  S32               Offset;
+  BOOL              Lpddr;
+
+  Status        = mrcSuccess;
+  Debug         = &MrcData->SysIn.Inputs.Debug;
+  Outputs       = &MrcData->SysOut.Outputs;
+  ControllerOut = &Outputs->Controller[0];
+  Lpddr         = (Outputs->DdrType == MRC_DDR_TYPE_LPDDR3);
+
+  if (SelfRefresh && ResetDDR) {
+    MRC_DEBUG_MSG (
+      Debug,
+      MSG_LEVEL_ERROR,
+      "WARNING SelfRefresh OR ResetDDR can be set at once...performing SelfRefresh\n"
+      );
+    ResetDDR = 0;
+  }
+
+  if (SelfRefresh) {
+    EnterSR (MrcData);
+  }
+
+  for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+    if (!MrcChannelExist (Outputs, Channel)) {
+      continue;
+    }
+
+    ChannelOut = &ControllerOut->Channel[Channel];
+    RankMaskCh = Ranks & ChannelOut->ValidRankBitMask;
+
+    if (RankMaskCh == 0) {
+      continue;
+    }
+
+    Offset = offset[Channel];
+
+    //
+    // Shift CLK (this will shift DQ PIs as well)
+    //
+    ShiftPIforCmdTraining (MrcData, Channel, MrcIterationClock, RankMaskCh, 3, Offset, UpdateHost);
+
+    //
+    // Shift CTL
+    //
+    NewValue = 0;
+    for (Rank = 0; Rank < MAX_RANK_IN_CHANNEL; Rank++) {
+      if (RankMaskCh & (1 << Rank)) {
+        NewValue = ChannelOut->CtlPiCode[Rank] + Offset;
+        break;
+      }
+    }
+
+    ShiftPIforCmdTraining (MrcData, Channel, MrcIterationCtl, RankMaskCh, 1, NewValue, UpdateHost);
+
+    //
+    // Shift CmdS
+    //
+    ShiftPIforCmdTraining (
+      MrcData,
+      Channel,
+      MrcIterationCmdS,
+      RankMaskCh,
+      1,
+      ChannelOut->CmdsCmdPiCode[0] + Offset,
+      UpdateHost
+      );
+
+    //
+    // Shift CmdN
+    //
+    ShiftPIforCmdTraining (
+      MrcData,
+      Channel,
+      MrcIterationCmdN,
+      RankMaskCh,
+      1,
+      ChannelOut->CmdnCmdPiCode[0] + Offset,
+      UpdateHost
+      );
+
+#ifdef ULT_FLAG
+    if (Lpddr) {
+      //
+      // For LPDDR need to shift CmdS PiCode[1] separately.
+      // Host struct is not updated, so update PiCode[0] manually, and then restore back.
+      //
+      ChannelOut->CmdsCmdPiCode[0] = ChannelOut->CmdsCmdPiCode[0] + Offset;
+      ShiftPIforCmdTraining (
+        MrcData,
+        Channel,
+        MrcIterationCmdS,
+        RankMaskCh,
+        2,
+        ChannelOut->CmdsCmdPiCode[1] + Offset,
+        UpdateHost
+        );
+      ChannelOut->CmdsCmdPiCode[0] = ChannelOut->CmdsCmdPiCode[0] - Offset;
+    }
+#endif // ULT_FLAG
+    //
+    // Shift CKE
+    //
+    ShiftPIforCmdTraining (
+      MrcData,
+      Channel,
+      MrcIterationCke,
+      RankMaskCh,
+      1,
+      ChannelOut->CkeCmdPiCode[0] + Offset,
+      UpdateHost
+      );
+  } // for Channel
+  //
+  // Reset DDR is required
+  //
+  if (ResetDDR) {
+    Status = MrcResetSequence (MrcData);
+  } else if (SelfRefresh) {
+    ExitSR (MrcData);
+  }
+
+  return Status;
+}
+
+/**
+  Returns the index into the array OptResult in the MrcOutput structure.
+
+  @param[in] OptParam - Margin parameter
+
+  @retval One of the following values: RdSAmpOfft(0), WrDSOfft (1), RxEqOfft(2), TxEqOfft (3), RdOdtOfft(4)
+**/
+U8
+GetOptResultType (
+  IN U8 OptParam
+  )
+{
+  switch (OptParam) {
+  case OptRxBias:
+    return RdSAmpOfft;
+
+  case OptWrDS:
+    return WrDSOfft;
+
+  case OptRxEq:
+    return RxEqOfft;
+
+  case OptTxEq:
+    return TxEqOfft;
+
+  case OptRdOdt:
+    return RdOdtOfft;
+
+  default:
+    return 0; // Return RdSAmpOfft to point to the beginning of the array
+  }
+}
+
+/**
+  Program DimmOptPoint values on CPU and DIMM sides, such as DIMM ODT, CPU ODT, Ron, Slew Rate, Equalization.
+
+  @param[in,out] MrcData          - Include all MRC global data.
+  @param[in]     ChMask           - Channel to work on.
+  @param[in,out] BestDimmOptPoint - Best DIMM Opt settings used to update hardware
+  @param[in]     SkipGRdOdt       - Switch to skip updating CPU ODT
+  @param[in]     SkipDimmOdts     - Switch to skip updating DIMM ODT
+  @param[in]     SkipBestOffsets  - Switch to skip updating Opt settings
+  @param[in]     UpdateHost       - Switch to skip updating MRC host structure
+
+  @retval Nothing
+**/
+void
+UpdateOdtsValues (
+  IN OUT MrcParameters *const MrcData,
+  IN     U8                   ChMask,
+  IN OUT DimmOptPoint         *BestDimmOptPoint,
+  IN     BOOL                 SkipGRdOdt,
+  IN     BOOL                 SkipDimmOdts,
+  IN     BOOL                 SkipBestOffsets,
+  IN     BOOL                 UpdateHost
+  )
+{
+  MrcOutput       *Outputs;
+  U8              byte;
+  U8              rank;
+  U8              Channel;
+  U8              offset;
+  U8              Dimm;
+  U8              test;
+  U8              TestArray[5];
+  BOOL            DebugPrint;
+  U8              OptParam;
+  U8              NumTests;
+  const MrcDebug  *Debug;
+
+  Outputs     = &MrcData->SysOut.Outputs;
+  Debug       = &MrcData->SysIn.Inputs.Debug;
+  NumTests    = BestDimmOptPoint->OptParamTestListSize;
+  DebugPrint  = 0;
+
+  MrcOemMemorySet (TestArray, 0, sizeof (TestArray));
+  if (SkipBestOffsets) {
+    NumTests = 0;
+  }
+  //
+  // build tests array to update RdSAmpOfft(0), WrDSOfft (1), RxEqOfft(2), TxEqOfft (3), RdOdtOfft(4)
+  //
+  for (test = 0; test < NumTests; test++) {
+    OptParam  = BestDimmOptPoint->OptParamTestList[test];
+    TestArray[GetOptResultType (OptParam)] = 1;
+    MRC_DEBUG_MSG (
+      Debug,
+      MSG_LEVEL_NOTE,
+      "Test - %s : %d ,UpdateHost: %d\n",
+      TOptParamOffsetString[OptParam],
+      test,
+      UpdateHost
+      );
+  }
+
+  if (!SkipGRdOdt) {
+    //
+    // update GRdOdt
+    //
+    BestDimmOptPoint->ODTSet.GRdOdtCode = UpdateCompGlobalOffset (
+                                            MrcData,
+                                            RdOdt,
+                                            (U8) BestDimmOptPoint->ODTSet.GRdOdt,
+                                            UpdateHost
+                                            );
+    if (DebugPrint) {
+      MRC_DEBUG_MSG (
+        Debug,
+        MSG_LEVEL_NOTE,
+        "best GRdODT aplly is : %d \n",
+        CalcRdOdt (MrcData, BestDimmOptPoint->ODTSet.GRdOdt)
+        );
+    }
+  }
+
+  for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+    if (!(MrcChannelExist (Outputs, Channel))) {
+      continue; // Not valid channel
+    }
+
+    if (!((MRC_BIT0 << Channel) & ChMask)) {
+      continue;
+    }
+
+    offset = 1;
+    if ((Outputs->Controller[0].Channel[Channel].DimmCount == 1)) {
+      offset = 0; // disable dynamic odt
+      for (Dimm = 0; Dimm < MAX_DIMMS_IN_CHANNEL; Dimm++) {
+        //
+        // set RttNom=write and RttWr=0
+        //
+        BestDimmOptPoint->ODTSet.RttNom[Channel][Dimm] = BestDimmOptPoint->ODTSet.RttWr[Channel][Dimm];
+      }
+    }
+#ifdef ULT_FLAG
+    if (MrcData->SysIn.Inputs.CpuModel == cmHSW_ULT) {
+      //
+      // On ULT (1DPC) DIMM ODT is connected to Vdd, so RttNom must be disabled
+      //
+      offset = 1;
+      BestDimmOptPoint->ODTSet.RttNom[Channel][0] = 0;
+      BestDimmOptPoint->ODTSet.RttNom[Channel][1] = 0;
+      BestDimmOptPoint->ODTSet.RttWr[Channel][1] = 0;
+    }
+#endif //ULT_FLAG
+
+    //
+    // Apply Best RTT Points
+    //
+    if (!SkipDimmOdts) {
+      UpdateOptParamOffset (
+        MrcData,
+        Channel,
+        0x3,
+        0,
+        OptDimmOdt,
+        (S16)
+        (
+        ((offset * BestDimmOptPoint->ODTSet.RttWr[Channel][0]) << 4) +
+        (BestDimmOptPoint->ODTSet.RttNom[Channel][0])
+        ),
+        UpdateHost
+        );
+      UpdateOptParamOffset (
+        MrcData,
+        Channel,
+        0xC,
+        0,
+        OptDimmOdt,
+        (S16)
+        (
+        ((offset * BestDimmOptPoint->ODTSet.RttWr[Channel][1]) << 4) +
+        (BestDimmOptPoint->ODTSet.RttNom[Channel][1])
+        ),
+        UpdateHost
+        );
+      if (DebugPrint) {
+        MRC_DEBUG_MSG (
+          Debug,
+          MSG_LEVEL_NOTE,
+          "best RttNom0 aplly is : %d\t\n",
+          ActualDimmOdt[BestDimmOptPoint->ODTSet.RttNom[Channel][0]]
+          );
+        MRC_DEBUG_MSG (
+          Debug,
+          MSG_LEVEL_NOTE,
+          "best RttNom1 aplly is : %d\t\n",
+          ActualDimmOdt[BestDimmOptPoint->ODTSet.RttNom[Channel][1]]
+          );
+        MRC_DEBUG_MSG (
+          Debug,
+          MSG_LEVEL_NOTE,
+          "best RttWr0 aplly is : %d\t\n",
+          ActualDimmOdt[BestDimmOptPoint->ODTSet.RttWr[Channel][0]]
+          );
+        MRC_DEBUG_MSG (
+          Debug,
+          MSG_LEVEL_NOTE,
+          "best RttWr1 aplly is : %d\t\n",
+          ActualDimmOdt[BestDimmOptPoint->ODTSet.RttWr[Channel][1]]
+          );
+      }
+    }
+
+    if (NumTests) {
+      for (byte = 0; byte < Outputs->SdramCount; byte++) {
+        //
+        // Apply Best RdOdt and WrDS
+        // OdtOff = Off[RdOdtOfft][0][Channel][byte] + RdOdtChOffset[Channel];
+        //
+        if (TestArray[RdSAmpOfft]) {
+          //
+          // OptRdOdt->OptRxBias
+          //
+          UpdateOptParamOffset (
+            MrcData,
+            Channel,
+            0xF,
+            byte,
+            OptRxBias,
+            BestDimmOptPoint->BestOptOff[RdSAmpOfft][0].Offset[Channel][byte],
+            UpdateHost
+            );
+        }
+
+        if (TestArray[WrDSOfft]) {
+          UpdateOptParamOffset (
+            MrcData,
+            Channel,
+            0xF,
+            byte,
+            OptWrDS,
+            BestDimmOptPoint->BestOptOff[WrDSOfft][0].Offset[Channel][byte],
+            UpdateHost
+            );
+        }
+
+        if (DebugPrint) {
+          MRC_DEBUG_MSG (
+            Debug,
+            MSG_LEVEL_NOTE,
+            "enable=%d best WrDSOfft byte %d is : %d\t\n",
+            TestArray[WrDSOfft],
+            byte,
+            BestDimmOptPoint->BestOptOff[WrDSOfft][0].Offset[Channel][byte]
+            );
+          MRC_DEBUG_MSG (
+            Debug,
+            MSG_LEVEL_NOTE,
+            "enable=%d best RdSAmpOfft byte %d is : %d\t\n",
+            TestArray[RdSAmpOfft],
+            byte,
+            BestDimmOptPoint->BestOptOff[RdSAmpOfft][0].Offset[Channel][byte]
+            );
+        }
+
+        for (rank = 0; rank < MAX_RANK_IN_CHANNEL; rank++) {
+          if (!MrcRankInChannelExist (MrcData, rank, Channel)) {
+            continue;
+          }
+          //
+          // Apply Best Tx/Rx EQ Codes
+          //
+          if (TestArray[RxEqOfft]) {
+            UpdateOptParamOffset (
+              MrcData,
+              Channel,
+              (MRC_BIT0 << rank),
+              byte,
+              OptRxEq,
+              BestDimmOptPoint->BestOptOff[RxEqOfft][rank].Offset[Channel][byte],
+              UpdateHost
+              );
+          }
+
+          if (TestArray[TxEqOfft]) {
+            UpdateOptParamOffset (
+              MrcData,
+              Channel,
+              (MRC_BIT0 << rank),
+              byte,
+              OptTxEq,
+              BestDimmOptPoint->BestOptOff[TxEqOfft][rank].Offset[Channel][byte],
+              UpdateHost
+              );
+          }
+
+          if (DebugPrint) {
+            MRC_DEBUG_MSG (
+              Debug,
+              MSG_LEVEL_NOTE,
+              "enable=%d best OptRxEq rank%d byte %d is : %d\t\n",
+              TestArray[RxEqOfft],
+              rank,
+              byte,
+              BestDimmOptPoint->BestOptOff[RxEqOfft][rank].Offset[Channel][byte]
+              );
+            MRC_DEBUG_MSG (
+              Debug,
+              MSG_LEVEL_NOTE,
+              "enable=%d best OptTxEq rank%d byte %d is : %d\t\n",
+              TestArray[TxEqOfft],
+              rank,
+              byte,
+              BestDimmOptPoint->BestOptOff[TxEqOfft][rank].Offset[Channel][byte]
+              );
+          }
+        }
+      }
+    }
+  }
+}
+
+/**
+  Calculate Power based on Ron and Rodt
+  Includes both static power from Ron/Rodt and dynamic power from Cpad/Cline
+  The power results here are not absolutely correct but give a reasonable estimate (ie: within 2x) with the proper trends
+  Getting absolutely correct power numbers with simple calculations is fairly difficult given the transmission line nature of the system
+  Driver power is calculated as the amount of power drawn from the CPU pin (do we want this to be thermal power instead?) based on the Ron and ODTeff
+              ODTeff is calculated as both the real, resistive ODT on the bus in parallel with the effective impendence of the cap on the line
+              This effective impedance is how AC power is included in the measurements
+              This better models the real system behavior where the power consumed due to dynamic power reduces as termination strength increases
+  ODT power is calculated as a purely DC term based on Ron and Rodt
+  The final power reported back is a scaled version of the CPU and DRAM power
+  This allows one to weight the CPU vs. DRAM power differently in the optimization function based on what is more important
+              CPU power is generally more important since it can be translated into additional performance
+
+  @param[in]  MrcData  - Include all MRC global data.
+  @param[out] Results  - Results of the Power power calculations
+  @param[in]  RonCpu   - RON CPU value (ohm)
+  @param[in]  RonDimm  - RON DIMM value (ohm)
+  @param[in]  Rodtcpu  - RODT CPU value
+  @param[in]  Rodtdram - RODT DRAM value
+  @param[in]  Wodtdram - WODT DRAM value
+
+  @retval Nothing
+**/
+void
+CalcPower (
+  IN  MrcParameters *MrcData,
+  OUT MrcPower      *Results,
+  IN  U16           RonCpu,
+  IN  U8            RonDimm,
+  IN  U16           Rodtcpu,
+  IN  U16           Rodtdram,
+  IN  U16           Wodtdram
+  )
+{
+  const MrcInput  *Inputs;
+  const MrcDebug  *Debug;
+  MrcOutput       *Outputs;
+  U16             CapTotal;
+  U32             CapOdt;
+  U32             Rodt;
+  U32             Vx;
+  U32             Vy;
+  U32             Ix;
+  U32             Iy;
+  U32             DrvPwr;
+  U32             ACPowerRd;
+  U32             ACPowerWr;
+  //
+  // Power Results;
+  //
+  U16             ScaleCpuPwr;
+  U16             ScaleDramPwr;
+  U16             LineLength; // cm
+  U16             Cpad; // pF
+  U32             Derating;
+  U32             ACPower;
+  U32             Vswing;
+  U16             CapPerLength; // pF/cm
+  U16             Freq; // Ghz
+  U16             FreqEff;
+  U16             Pi; // 3.14;
+  U16             Vdd; // 1.5; mV
+  U16             SRDimm; // 15ohm serial resistance
+  U16             NormFactor;
+
+  Vx            = 0;
+  Vy            = 0;
+  Ix            = 0;
+  Iy            = 0;
+  ScaleCpuPwr   = 1;
+  ScaleDramPwr  = 1;
+  LineLength    = 10;
+  Cpad          = 4;
+  CapPerLength  = 2;
+  Pi            = 3;
+  SRDimm        = 15;
+  NormFactor    = 100; // if 1000 we get mW
+  Inputs        = &MrcData->SysIn.Inputs;
+  Debug         = &Inputs->Debug;
+  Outputs       = &MrcData->SysOut.Outputs;
+  Vdd           = Outputs->VddVoltage[Inputs->MemoryProfile];
+  Freq = (U16) (Outputs->Frequency);
+  Freq /= 100; // in 10xGhz
+  //
+  // capacitance for AC power
+  // Cut real cap in half and add 10pF offset to better match curves - results x100 pf
+  // Fixed frequency at 500 MHz(~Data Rate/4 assuming random 1100 type data) - resutls is 100x Ghz
+  // In general, most of the simulations show fairly flat AC power vs. frequency
+  //
+  CapTotal = (Cpad + LineLength * CapPerLength) * 45;
+  FreqEff  = 50;
+  CapOdt   = 10000000 / (2 * Pi * CapTotal * FreqEff);  // Scale Up by 2.5x to better match curves
+  //
+  // MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "RonDimm=%d Rodtcpu=%d Wodtdram=%d  Rodtdram=%d RonCpu=%d CapOdt=%d\n",RonDimm,Rodtcpu,Wodtdram,Rodtdram,RonCpu,CapOdt);
+  // for read
+  //
+  Rodt = (Rodtcpu * (Rodtdram + SRDimm)) / (Rodtcpu + (Rodtdram + SRDimm));
+  //
+  // MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "(Rodtdram+SRDimm)=%d Rodtcpu=%d  Rodt=%d \n",(Rodtdram+SRDimm),Rodtcpu,Rodt);
+  Derating = 1000 * Rodt / (Rodt + CapOdt); // Derate ACPower based on ratio of Real ODT vs. "0DT" due to cap
+  Ix = Vdd / 2 / (RonDimm + SRDimm + Rodt); // mA
+  Vx = Vdd - Ix * (RonDimm + SRDimm); // voltage after dimm driver+15ohm
+  DrvPwr = Ix * Ix * (RonDimm + SRDimm) / NormFactor; // dimm Ron static power
+  Vswing = 2 * Vx - Vdd; // for ACpower= Vh-Vl
+  //
+  // Calculate power associated with swing that cap - mV/1000*pf/100*Ghz/100000
+  //
+  ACPower = Vswing * Vswing / 1000 * CapTotal * FreqEff / 100 / 100 / NormFactor;
+  ACPowerRd = ACPower * Derating / 1000; // mW
+  //MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "read ACPowerRd=%d ACPower=%d Derating=%d  Vswing=%d Rodt=%d Ix=%d,Vx=%d,PwrDrv=%d,FreqEff=%d CapOdt=%d Rodt=%d ,DrvPwr=%d\n",ACPowerRd,ACPower,Derating,Vswing,Rodt,Ix,Vx,DrvPwr,FreqEff,CapOdt,Rodt,DrvPwr);
+  Results->CpuPwrRd = ((Vdd - Vx) * (Vdd - Vx) + Vx * Vx) / (2 * Rodtcpu * NormFactor); // mW  @todo:add RxBias?
+  Iy = (Vx - Vdd / 2) / (Rodtdram + SRDimm); // current in to the NT dimm
+  Vy = Vx - Iy * (SRDimm); // voltage after 15 ohm inside the dimm
+  Results->DimmPwrRd = Iy *
+    Iy *
+    SRDimm /
+    NormFactor +
+    ((Vdd - Vy) * (Vdd - Vy) + Vy * Vy) /
+    (2 * Rodtdram * NormFactor) +
+    DrvPwr;  // mW
+  //
+  // for write
+  //
+  Rodt      = (Wodtdram + SRDimm) * (Rodtdram + SRDimm) / ((Wodtdram + SRDimm) + (Rodtdram + SRDimm));
+  Derating  = 1000 * Rodt / (Rodt + CapOdt); // De-rate ACPower based on ratio of Real ODT vs. "0DT" due to cap
+  // MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Rodt=%d Derating=%d ",Rodt,Derating);
+  Ix = Vdd / 2 / (RonCpu + Rodt); // mA
+  Vx = Vdd - Ix * (RonCpu);  // voltage after cpu driver
+  DrvPwr = Ix * Ix * (RonCpu) / NormFactor; // cpu Ron static power
+  Vswing = 2 * Vx - Vdd;  // for ACpower
+  //
+  // Calculate power associated with swing that cap
+  //
+  ACPower = Vswing * Vswing / 1000 * CapTotal * FreqEff / 100 / 100 / NormFactor;
+  ACPowerWr = ACPower * Derating / 1000; // mW
+  //MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "write ACPowerWr=%d ACPower=%d Derating=%d  Vswing=%d Rodt=%d Ix=%d,Vx=%d,PwrDrv=%d,FreqEff=%d CapOdt=%d Rodt=%d ,DrvPwr=%d\n",ACPowerWr,ACPower,Derating,Vswing,Rodt,Ix,Vx,DrvPwr,FreqEff,CapOdt,Rodt,DrvPwr);
+  Results->CpuPwrWr = DrvPwr; // mW
+  Iy = (Vx - Vdd / 2) / (Wodtdram + SRDimm); // current in to the T dimm
+  Vy = Vx - Iy * (SRDimm); // voltage after 15 ohm inside the dimm
+  Results->DimmPwrWrT = Iy * Iy * SRDimm / NormFactor + ((Vdd - Vy) * (Vdd - Vy) + Vy * Vy) / (2 * Wodtdram * NormFactor); // mW
+  Iy = (Vx - Vdd / 2) / (Rodtdram + SRDimm);  // current in to the NT dimm
+  Vy = Vx - Iy * (SRDimm);  // voltage after 15 ohm inside the dimm
+  Results->DimmPwrWrNT = Iy * Iy * SRDimm / NormFactor + ((Vdd - Vy) * (Vdd - Vy) + Vy * Vy) / (2 * Rodtdram * NormFactor);  // mW
+
+  //
+  // ScaleCpuPwr and ScaleDramPwr allows one to tradeoff CPU vs. DRAM power
+  //
+  Results->ACPowerRd  = ACPowerRd;
+  Results->ACPowerWr  = ACPowerWr;
+  Results->TotPwr = (U16)
+    (
+      60 * (Results->CpuPwrRd * ScaleCpuPwr + Results->DimmPwrRd * ScaleDramPwr + ACPowerRd * ScaleDramPwr) + 40 *
+      (
+        (Results->DimmPwrWrT + Results->DimmPwrWrNT) *
+        ScaleDramPwr +
+        Results->CpuPwrWr *
+        ScaleCpuPwr +
+        ACPowerWr *
+        ScaleCpuPwr
+      )
+    ) / 100;
+  Results->ACPower = (60 * ACPowerRd + 40 * ACPowerWr) / 100;
+  Results->CpuPower = (U16)
+    (
+      60 * (Results->CpuPwrRd * ScaleCpuPwr ) + 40 *
+      (
+        Results->CpuPwrWr *
+        ScaleCpuPwr +
+        ACPowerWr *
+        ScaleCpuPwr
+      )
+    ) / 100;
+
+  Results->DimmPwr = (U16)
+    (
+      60 * (Results->DimmPwrRd * ScaleDramPwr + ACPowerRd * ScaleDramPwr) + 40 *
+      (
+        (Results->DimmPwrWrT + Results->DimmPwrWrNT) *
+        ScaleDramPwr
+      )
+    ) / 100;
+  // MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, " PwrTotal=%d DimmPwrR=%d DimmPwrWrT=%d DimmPwrWrNT=%d PwrDrvR=%d Rodt=%d  PwrDrvW=%d\n",Results->TotPwr,Results->DimmPwrRd,Results->DimmPwrWrT,Results->DimmPwrWrNT,ACPowerRd,Rodt,ACPowerWr);
+  return;
+}
+
+/**
+  Calculate Power Trend line based on Cpu and Dimms Ron and Odt's
+
+  @param[in]     MrcData       - Include all MRC global data.
+  @param[in]     Channel       - Channel to work on.
+  @param[in]     DimmMask      - DIMMs to work on.
+  @param[in,out] DimmOptPoints - Structure of all the DIMM ODT optimal settings.
+  @param[in]     Points2calc   - Data to build the trendline on.
+  @param[in]     ArrayLength   - Array length of Points2calc.
+  @param[in]     LenMargin     - The length of inputMargins we are optimizing (0 - LenMargin -1).
+  @param[in]     TestList      - TestList index in Points2cal: WrVref, RdVref, WrT, RdT
+  @param[in]     Scale         - Scale to apply per test to Points2calc
+  @param[in]     TestListSize  - Size of TestList/Scale
+  @param[in]     PwrCalc1d     - Determines if the power test is 1-D or 2-D.
+  @param[in]     PWRTrendSlope - Determines how aggressive the T-line will be.(0%-100%)
+
+  @retval Nothing
+**/
+void
+CalcPowerTrend (
+  IN     MrcParameters   *MrcData,
+  IN     U8              Channel,
+  IN     U8              DimmMask,
+  IN OUT void            *DimmOptPoints,
+  IN     void            *Points2calc,
+  IN     U8              ArrayLength,
+  IN     U8              LenMargin,
+  IN     U8              *TestList,
+  IN     U8              *Scale,
+  IN     U8              TestListSize,
+  IN     BOOL            PwrCalc1d,
+  IN     U8              PWRTrendSlope
+  )
+{
+  const MrcDebug  *Debug;
+  MrcChannelOut   *ChannelOut;
+  U16             MaxPoints[4];
+  U16             MinPoints[4];
+  U16             MaxPwr;
+  U16             MinPwr;
+  U8              off;
+  U8              test;
+  U8              dimm;
+  U8              TestParam;
+  MrcPower        PwrRes;
+  U16             AveOfMax;
+  U16             X;
+  S16             MinRatio;
+  S16             Ratio;
+  U16             Slope;
+  U16             SlopeOver100;
+  U16             Rodtcpu;
+  U8              RonDimm;
+  U8              RonCpu;
+  U16             Rodtdram;
+  U16             Wodtdram;
+  U16             *Points;
+  U16             *PointsElement;
+  DimmOptPoint    *DimmPoints;
+  U8              dimmcount;
+  BOOL            is1DPC;
+  U16             AvgROdt;
+
+  ChannelOut  = &MrcData->SysOut.Outputs.Controller[0].Channel[Channel];
+  Debug       = &MrcData->SysIn.Inputs.Debug;
+  Points      = (U16 *) Points2calc;
+  is1DPC      = (ChannelOut->DimmCount == 1);
+  MaxPwr      = 0;
+  MinPwr      = 0xffff;
+  Wodtdram    = 0;
+
+  MrcOemMemorySet ((U8 *) &PwrRes, 0, sizeof (PwrRes));
+  MrcOemMemorySetWord (MaxPoints, 0, sizeof (MaxPoints) / sizeof (U16));
+  MrcOemMemorySetWord (MinPoints, 0xFFFF, sizeof (MinPoints) / sizeof (U16));
+
+  //
+  // MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "TestListSize=%d\n",TestListSize);
+  //
+  for (off = 0; off < LenMargin; off++) {
+    //
+    // sorting the min max power points
+    //
+    for (test = 0; test < TestListSize; test++) {
+      //
+      // sorting the min max margin points for each test
+      //
+      PointsElement = (Points + ArrayLength * test + off);
+      if (MaxPoints[test] < *PointsElement) {
+        MaxPoints[test] = *PointsElement;
+      }
+
+      if (MinPoints[test] > *PointsElement) {
+        MinPoints[test] = *PointsElement;
+      }
+      //
+      // MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "*(Points+ArrayLength*test+off)=%d (Points+ArrayLength*test+off)=%x\n",*(Points+ArrayLength*test+off),(Points+ArrayLength*test+off));
+      //
+    }
+
+    if (!PwrCalc1d) {
+      DimmPoints  = (DimmOptPoint *) DimmOptPoints;
+      RonDimm     = 0;
+      RonCpu      = 30;
+      Rodtcpu     = CalcRdOdt (MrcData, (DimmPoints + off)->ODTSet.GRdOdt);
+      dimmcount   = 0;
+      AvgROdt     = 0;
+      for (dimm = 0; dimm < MAX_DIMMS_IN_CHANNEL; dimm++) {
+        if (!((MRC_BIT0 << dimm) & DimmMask)) {
+          continue;
+        }
+        //
+        // read from MR1 the DimmRon
+        //
+        RonDimm  += (U8) CalcOptPower (MrcData, Channel, 2 * dimm, 0, OptDimmRon, 0, 0, 1);
+        Rodtdram  = ActualDimmOdt[(DimmPoints + off)->ODTSet.RttNom[Channel][dimm]];
+        Wodtdram  = ActualDimmOdt[(DimmPoints + off)->ODTSet.RttWr[Channel][dimm]];
+        if (is1DPC) {           // in 1DPC channel always use only one of the terminations
+          if (Wodtdram == 0) {
+            Wodtdram  = Rodtdram;
+          }
+          Rodtdram  = 0x3fff; // put 8k ohm as infinity
+        }
+
+        if (Rodtdram == 0) {
+          Rodtdram = 0x3fff;
+        }
+
+        if (Wodtdram == 0) {
+          Wodtdram = Rodtdram; // in 2DPC with RttW=0
+        }
+
+        AvgROdt += Rodtdram;
+        dimmcount++;
+      }
+
+      AvgROdt = (dimmcount != 0) ? AvgROdt / dimmcount : AvgROdt;
+      RonDimm = (dimmcount != 0) ? RonDimm / dimmcount : RonDimm;
+      if ((120 < AvgROdt) && (AvgROdt < 0x3fff)) {
+        Rodtdram = 240; // the mix case of one open and one not
+      } else {
+        Rodtdram = AvgROdt; // for write average not needed because its by dimm
+      }
+      //
+      // MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "input for power calc Wodtdram=%d Rodtdram=%d RonDimm=%d \n",Wodtdram,Rodtdram,RonDimm);
+      //
+      PointsElement = (Points + ArrayLength * TestListSize + off);
+      CalcPower (MrcData, &PwrRes, RonCpu, RonDimm, Rodtcpu, Rodtdram, Wodtdram);
+      *PointsElement                = PwrRes.TotPwr;
+      (DimmPoints + off)->PowerCalc = PwrRes;
+
+      //
+      // MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Rodtcpu=%d  Wodtdram=%d EqRodtdram=%d Calcpower=%d\n",Rodtcpu,Wodtdram,Rodtdram,*(Points+ArrayLength*test+off));
+      //
+    } else {
+      PointsElement = (Points + ArrayLength * TestListSize + off);
+    }
+
+    if (MaxPwr < *PointsElement) {
+      MaxPwr = *PointsElement;
+    }
+
+    if (MinPwr > *PointsElement) {
+      MinPwr = *PointsElement;
+    }
+
+    if (LenMargin == 1) {
+      MaxPwr  = *PointsElement;
+      MinPwr  = 0;
+    }
+  }
+  //
+  // MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "MaxPwr=%d MinPwr=%d\n",MaxPwr,MinPwr);
+  //
+  AveOfMax  = 0;
+  MinRatio  = 0x7fff;
+  for (test = 0; test < TestListSize; test++) {
+    AveOfMax += MaxPoints[test];
+    //
+    // map Test to TestParam
+    //
+    TestParam = TestList[test];
+    Ratio = (100 * (MaxPoints[test] / Scale[test] - UpmPwrLimitValue (MrcData, TestParam, UpmLimit))) /
+            (UpmPwrLimitValue (MrcData, TestParam, PowerLimit) - UpmPwrLimitValue (MrcData, TestParam, UpmLimit));
+    if (MinRatio > Ratio) {
+      MinRatio = Ratio;
+    }
+    //
+    // MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "AveOfMax=%d MinRatio=%d MaxPoints[%d]=%d Scale[%d]=%d \n",AveOfMax,MinRatio,test,MaxPoints[test],test,Scale[test]);
+    //
+  }
+
+  AveOfMax = AveOfMax / TestListSize;
+  //
+  // if MaxPoint > UPM Limit:          PwrTrend should be flat
+  // if MaxPoints == PwrLimit:         PwrTrend should have slope going from AveOfMax to (1-PWRTrendSlope/100)*AveOfMax
+  // PwrTrend will be a linear slope going from (MinPwr, (1- PWRTrendSlope/100)*AveOfMax) to (MaxPwr, AveOfMax)
+  //
+  Slope         = (PWRTrendSlope * MinRatio) / 100;
+  SlopeOver100  = 0;
+  if (Slope > 100) {
+    //
+    // could only happen if no power limits
+    //
+    SlopeOver100  = Slope - 100;
+    Slope         = 100;
+  }
+
+  for (off = 0; off < LenMargin; off++) {
+    PointsElement = (Points + ArrayLength * TestListSize + off);
+    if (MinRatio < 0) {
+      *PointsElement = 1;
+    } else {
+      if (MaxPwr == MinPwr) {
+        X = 0; // no power consideration and not divide by zero
+      } else {
+        //
+        // % of where you are between Min and Max Pwr. X=0 should be MaxPwr and 100 should be MinPwr
+        //
+        X = 100 - 100 * (*PointsElement - MinPwr) / (MaxPwr);
+      }
+      //
+      // Create a linear line based on Power from (1 - PWRTrendSlope / 100) * AveOfMax to AveOfMax
+      // Adding a specicial case for TX XTalk: If PWRTrendSlope = 0 and ArrayLength = BIT_TX_XTALK_RANGE
+      // just multiply power numbers by AveOfMax.
+      //
+      if ((PWRTrendSlope == 0) && (ArrayLength == BIT_TX_XTALK_RANGE)) {
+        *PointsElement = *PointsElement * AveOfMax / 100;
+      } else {
+        *PointsElement = AveOfMax * (100 - Slope + (((Slope + SlopeOver100) * X) / 100)) / 100;
+      }
+      //
+      // MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "power trend Points[%d][%d]=%d\n",TestListSize,off,*(Points+ArrayLength*TestListSize+off));
+      //
+    }
+  }
+}
+
+#ifdef MRC_DEBUG_PRINT
+
+#if 0 // This function is not used right now
+/**
+  Prints OptParam values from CRs and Host structure for all ch/Rank/byte as well as
+  the Best optimization value (if requested)
+  OptWrDS = 0
+  OptRdOd = 1
+  OptSCom = 2
+  OptTComp = 3
+  OptTxEq = 4
+  OptRxEq = 5
+  OptRxBias = 6
+  OptDimmOdt = 7
+  OptDimmOdtWr = 8
+  OptDimmRon = 9
+  OptDefault = 10
+
+  @param[in] MrcData   - Include all MRC global data.
+  @param[in] ChMask    - Channel Mask to print the summary for
+  @param[in] RankMask  - Rank Mask to print the summary for (in case Rank is not applicable set RankMask = 0xF)
+  @param[in] OptParam  - Defines the OptParam Offsets. OptDefault reports all parameters
+  @param[in] OptOff    - Structure containg the best offest and margins for the OptParam.
+                         If OptOffsetChByte is not available, NullPtr needs to be passed (void  *NullPtr)
+  @param[in] OptResult - True/False: Whether to print the Best optimization value
+
+  @retval Nothing
+**/
+void
+ReadOptParamOffsetSum (
+  IN MrcParameters *const MrcData,
+  IN U8                   ChMask,
+  IN U8                   RankMask,
+  IN const U8             OptParam,
+  IN OptOffsetChByte      *OptOff,
+  IN BOOL                 OptResult
+  )
+{
+  const MrcDebug  *Debug;
+  MrcOutput       *Outputs;
+  U8              Channel;
+  U8              Rank;
+  U8              Byte;
+  U8              Param;
+  U8              NumBytes;
+  U8              ChannelMask;
+  S16             OffArr[2];
+  S16             Best;
+  BOOL            PerRank;
+  BOOL            SkipByte;
+
+  Outputs     = &MrcData->SysOut.Outputs;
+  Debug       = &MrcData->SysIn.Inputs.Debug;
+  ChannelMask = Outputs->ValidChBitMask & ChMask;
+  NumBytes    = (U8) Outputs->SdramCount;
+  MrcOemMemorySetWord ((U16 *) OffArr, (U16) 0, sizeof (OffArr) / sizeof (OffArr[0]));
+
+  for (Param = OptWrDS; Param < OptDefault; Param++) {
+    if (OptParam == Param || OptParam == OptDefault) {
+
+      MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\nOffsets for Optimization Parameter %s\n", TOptParamOffsetString[Param]);
+      PerRank =
+        (
+          Param == OptTxEq ||
+          Param == OptRxEq ||
+          Param == OptDimmOdt ||
+          Param == OptDimmOdtWr ||
+          Param == OptDimmRon
+        );
+      SkipByte = (Param == OptDimmRon || Param == OptDimmOdt || Param == OptDimmOdtWr);
+
+      for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+        if (!((MRC_BIT0 << Channel) & ChannelMask)) {
+          continue;
+        }
+
+        MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Channel %d\n", Channel);
+        for (Rank = 0; Rank < MAX_RANK_IN_CHANNEL; Rank++) {
+          if ((MRC_BIT0 << Rank) & RankMask) {
+            if (!(MrcRankInChannelExist (MrcData, Rank, Channel))) {
+              continue;
+            }
+
+            if (PerRank) {
+              MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Rank %d\n", Rank);
+            } else if (Rank > 0) {
+              continue;
+            }
+
+            if (!SkipByte) {
+              MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Byte\t");
+              for (Byte = 0; Byte < NumBytes; Byte++) {
+                MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%d\t", Byte);
+              }
+
+              MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\n");
+            }
+
+            if (OptResult) {
+              MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Opt/CR/Host\t");
+            } else {
+              MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "CR/Host\t");
+            }
+
+            if (!SkipByte) {
+              for (Byte = 0; Byte < NumBytes; Byte++) {
+                ReadOptParamOffset (MrcData, &OffArr[0], Channel, Rank, Byte, Param);
+
+                if (OptResult) {
+                  Best = OptOff->Offset[Channel][Byte];
+                  if (Best != OffArr[0] || Best != OffArr[1]) {
+                    MRC_DEBUG_MSG (
+                      Debug,
+                      MSG_LEVEL_NOTE,
+                      "\nError: Mismatch in Param %s in Channel %d Rank %d Byte %d is found: Best=%d CR=%d Host=%d\n",
+                      TOptParamOffsetString[Param],
+                      Channel,
+                      Rank,
+                      Byte,
+                      Best,
+                      OffArr[0],
+                      OffArr[1]
+                      );
+                  }
+
+                  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%d/%d/%d\t", Best, OffArr[0], OffArr[1]);
+                } else {
+                  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%d/%d\t", OffArr[0], OffArr[1]);
+                }
+              }
+            } else {
+              ReadOptParamOffset (MrcData, &OffArr[0], Channel, Rank, 0, Param);
+
+              if (Param == OptDimmRon || Param == OptDimmOdtWr) {
+                if (OptResult) {
+                  Best = OptOff->Offset[Channel][0];
+                  if (Best != OffArr[1]) {
+                    MRC_DEBUG_MSG (
+                      Debug,
+                      MSG_LEVEL_NOTE,
+                      "\nError: Mismatch in Param %s in Channel %d Rank %d is found: Best=%d Host=%d\n",
+                      TOptParamOffsetString[Param],
+                      Channel,
+                      Rank,
+                      Best,
+                      OffArr[1]
+                      );
+                  }
+
+                  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%d/NA/%d", Best, OffArr[1]);
+                } else {
+                  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "NA/%d", OffArr[1]);
+                }
+              } else if (Param == OptDimmOdt) {
+                if (OptResult) {
+                  Best = OptOff->Offset[Channel][0];
+                  if (Best != OffArr[0]) {
+                    MRC_DEBUG_MSG (
+                      Debug,
+                      MSG_LEVEL_NOTE,
+                      "\nError: Mismatch in Param %s in Channel %d Rank %d is found: Best=%d Host=%d\n",
+                      TOptParamOffsetString[Param],
+                      Channel,
+                      Rank,
+                      Best,
+                      OffArr[0]
+                      );
+                  }
+
+                  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%d/NA/%d", Best, OffArr[0]);
+                } else {
+                  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "NA/%d", OffArr[0]);
+                }
+              }
+            }
+
+            MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\n");
+          }
+        }
+      }
+    }
+  }
+}
+
+/**
+  Reads OptParam value from CRs and Host structure for a given ch/Rank/byte combination
+  OptParam can be: WrDS, RdOdt, TComp, SComp, RxEq, TxEq, RxBias, DIMM Ron, DIMM RttNom or DIMM RttWr
+
+  @param[in]  MrcData  - Include all MRC global data.
+  @param[out] FinalVal - Pointer to the array consisting of CR value and Host value for a particular
+                         OptParam and given ch/Rank/byte combination.
+  @param[in]  Channel  - Channel index to work on.
+  @param[in]  Rank     - Rank index to work on (valid only for TxEq and RxEq, for others is ignored)
+  @param[in]  Byte     - Byte index to work on.
+  @param[in]  OptParam - Defines the OptParam Offsets. Supported OptParam =
+                         [0: WrDS, 1: RdODT, 2: SComp, 3: TComp, 3: TxEq,
+                          4: RxEq, 5: RxBias, 6: DimmOdt, 7: DimmOdtWr]
+
+  @retval Nothing
+**/
+void
+ReadOptParamOffset (
+  IN  MrcParameters *const MrcData,
+  OUT S16                  *FinalVal,
+  IN  const U8             Channel,
+  IN  const U8             Rank,
+  IN  const U8             Byte,
+  IN  const U8             OptParam
+  )
+{
+  const U16       RttNomMRSEncodingConst[] = {0x00, 0x10, 0x01, 0x11, 0x81, 0x80}; // RttNom Off,120,60,40,30,20 Ohms
+  const U16       RttWrMRSEncodingConst[]  = {0x00, 0x02, 0x01};                // RttWr  RttNom,120,60 Ohms
+  const MrcDebug  *Debug;
+#ifdef ULT_FLAG
+  const U8        LpddrRonEnc[] = {0x1,0x2,0x3}; //{34,40,48};
+  const U8        LpddrOdtEnc[] = {0x0,0x2,0x3}; //{0,120,240};
+  BOOL            Lpddr;
+  U16             DimmRonMask;
+#endif // ULT_FLAG
+  MrcOutput       *Outputs;
+  MrcChannelOut   *ChannelOut;
+  U16             *MrReg;
+  BOOL            Type;
+  U8              Index;
+  U16             MRValue;
+  U16             RttNomMRSEncoding[sizeof (RttNomMRSEncodingConst) / sizeof (RttNomMRSEncodingConst[0])];
+  U16             RttWrMRSEncoding[sizeof (RttWrMRSEncodingConst) / sizeof (RttWrMRSEncodingConst[0])];
+  U16             RttWr;
+  U16             RttNom;
+  U16             RttNomMask;
+  U16             RttWrMask;
+  U32             Offset;
+  S16             UpOff;
+  S16             DnOff;
+  DDRDATA0CH0_CR_DDRCRDATAOFFSETCOMP_STRUCT DdrCrDataOffsetCompCr;
+  DDRDATA0CH0_CR_DDRCRDATAOFFSETCOMP_STRUCT DdrCrDataOffsetCompHost;
+  DDRDATA0CH0_CR_TXTRAINRANK0_STRUCT        CrTxTrainRank;
+  DDRDATA0CH0_CR_RXTRAINRANK0_STRUCT        CrRxTrainRank;
+  DDRDATA0CH0_CR_DDRCRDATACONTROL1_STRUCT   DdrCrDataControl1Cr;
+  DDRDATA0CH0_CR_DDRCRDATACONTROL1_STRUCT   DdrCrDataControl1Host;
+
+  Debug       = &MrcData->SysIn.Inputs.Debug;
+  Outputs     = &MrcData->SysOut.Outputs;
+  ChannelOut  = &Outputs->Controller[0].Channel[Channel];
+  MrcOemMemoryCpy ((U8 *) RttNomMRSEncoding, (U8 *) RttNomMRSEncodingConst, sizeof (RttNomMRSEncoding));
+  MrcOemMemoryCpy ((U8 *) RttWrMRSEncoding, (U8 *) RttWrMRSEncodingConst, sizeof (RttWrMRSEncoding));
+
+#ifdef ULT_FLAG
+  Lpddr = Outputs->DdrType == MRC_DDR_TYPE_LPDDR3;
+#endif
+  //
+  // Compensation Offsets
+  //
+  Type = ((OptParam == OptWrDS) || (OptParam == OptRdOdt) || (OptParam == OptTComp) || (OptParam == OptSComp));
+  if (Type) {
+
+    Offset = DDRDATA0CH0_CR_DDRCRDATAOFFSETCOMP_REG +
+      ((DDRDATA1CH0_CR_DDRCRDATAOFFSETCOMP_REG - DDRDATA0CH0_CR_DDRCRDATAOFFSETCOMP_REG) * Byte) +
+      ((DDRDATA0CH1_CR_DDRCRDATAOFFSETCOMP_REG - DDRDATA0CH0_CR_DDRCRDATAOFFSETCOMP_REG) * Channel);
+    DdrCrDataOffsetCompCr.Data   = MrcReadCR (MrcData, Offset);
+    DdrCrDataOffsetCompHost.Data = ChannelOut->DataCompOffset[Byte];
+
+    if (OptParam == OptWrDS) {
+      UpOff = (S16) (S32) DdrCrDataOffsetCompCr.Bits.DqDrvUpCompOffset;
+      DnOff = (S16) (S32) DdrCrDataOffsetCompCr.Bits.DqDrvDownCompOffset;
+      if (UpOff != DnOff) {
+        MRC_DEBUG_MSG (
+          Debug,
+          MSG_LEVEL_NOTE,
+          "DqDrvUpCompOffset %d is not equal to DqDrvDownCompOffset for Channel=%d, Byte=%d\n",
+          UpOff,
+          DnOff,
+          Channel,
+          Byte
+          );
+      }
+
+      FinalVal[0] = UpOff;
+      UpOff = (S16) (S32) DdrCrDataOffsetCompHost.Bits.DqDrvUpCompOffset;
+      DnOff = (S16) (S32) DdrCrDataOffsetCompHost.Bits.DqDrvDownCompOffset;
+      if (UpOff != DnOff) {
+        MRC_DEBUG_MSG (
+          Debug,
+          MSG_LEVEL_NOTE,
+          "DqDrvUpCompOffset %d is not equal to DqDrvDownCompOffset for Channel=%d, Byte=%d in Host Structure\n",
+          UpOff,
+          DnOff,
+          Channel,
+          Byte
+          );
+      }
+
+      FinalVal[1] = UpOff;
+
+      if (FinalVal[0] & 0x20) {     // 6-bit 2's complement
+        FinalVal[0] -= 0x40;
+      }
+      if (FinalVal[1] & 0x20) {     // 6-bit 2's complement
+        FinalVal[1] -= 0x40;
+      }
+    } else if (OptParam == OptRdOdt) {
+      UpOff = (S16) (S32) DdrCrDataOffsetCompCr.Bits.DqOdtUpCompOffset;
+      DnOff = (S16) (S32) DdrCrDataOffsetCompCr.Bits.DqOdtDownCompOffset;
+      if (UpOff != DnOff) {
+        MRC_DEBUG_MSG (
+          Debug,
+          MSG_LEVEL_NOTE,
+          "DqOdtUpCompOffset %d is not equal to DqOdtDownCompOffset for Channel=%d, Byte=%d\n",
+          UpOff,
+          DnOff,
+          Channel,
+          Byte
+          );
+      }
+
+      FinalVal[0] = UpOff;
+      UpOff = (S16) (S32) DdrCrDataOffsetCompHost.Bits.DqOdtUpCompOffset;
+      DnOff = (S16) (S32) DdrCrDataOffsetCompHost.Bits.DqOdtDownCompOffset;
+      if (UpOff != DnOff) {
+        MRC_DEBUG_MSG (
+          Debug,
+          MSG_LEVEL_NOTE,
+          "DqOdtUpCompOffset %d is not equal to DqOdtDownCompOffset for Channel=%d, Byte=%d in Host Structure\n",
+          UpOff,
+          DnOff,
+          Channel,
+          Byte
+          );
+      }
+
+      FinalVal[1] = UpOff;
+
+      if (FinalVal[0] & 0x10) {     // 5-bit 2's complement
+        FinalVal[0] -= 0x20;
+      }
+      if (FinalVal[1] & 0x10) {     // 5-bit 2's complement
+        FinalVal[1] -= 0x20;
+      }
+    } else if (OptParam == OptTComp) {
+      FinalVal[0] = (S16) (S32) DdrCrDataOffsetCompCr.Bits.DqTcoCompOffset;
+      FinalVal[1] = (S16) (S32) DdrCrDataOffsetCompHost.Bits.DqTcoCompOffset;
+
+      if (FinalVal[0] & 0x10) {     // 5-bit 2's complement
+        FinalVal[0] -= 0x20;
+      }
+      if (FinalVal[1] & 0x10) {     // 5-bit 2's complement
+        FinalVal[1] -= 0x20;
+      }
+    } else if (OptParam == OptSComp) {
+      FinalVal[0] = (S16) (S32) DdrCrDataOffsetCompCr.Bits.DqSlewRateCompOffset;
+      FinalVal[1] = (S16) (S32) DdrCrDataOffsetCompHost.Bits.DqSlewRateCompOffset;
+
+      if (FinalVal[0] & 0x10) {     // 5-bit 2's complement
+        FinalVal[0] -= 0x20;
+      }
+      if (FinalVal[1] & 0x10) {     // 5-bit 2's complement
+        FinalVal[1] -= 0x20;
+      }
+    }
+
+    if (FinalVal[0] != FinalVal[1]) {
+      MRC_DEBUG_MSG (
+        Debug,
+        MSG_LEVEL_NOTE,
+        "Error: Param %s: CR value %d doesn't match Host value %d for Channel=%d, Byte=%d\n",
+        TOptParamOffsetString[OptParam],
+        FinalVal[0],
+        FinalVal[1],
+        Channel,
+        Byte
+        );
+    }
+  }
+  //
+  // Equalization Settings
+  //
+  Type = ((OptParam == OptTxEq) || (OptParam == OptRxEq));
+  if (Type) {
+    //
+    // TxEq[5:4] = Emphasize   = [3, 6, 9, 12] legs
+    // TxEq[3:0] = Deemphasize = [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 4*Rsvd] legs
+    //
+    if (OptParam == OptTxEq) {
+
+     Offset = DDRDATA0CH0_CR_TXTRAINRANK0_REG +
+      ((DDRDATA0CH1_CR_TXTRAINRANK0_REG - DDRDATA0CH0_CR_TXTRAINRANK0_REG) * Channel) +
+      ((DDRDATA0CH0_CR_TXTRAINRANK1_REG - DDRDATA0CH0_CR_TXTRAINRANK0_REG) * Rank) +
+      ((DDRDATA1CH0_CR_TXTRAINRANK0_REG - DDRDATA0CH0_CR_TXTRAINRANK0_REG) * Byte);
+
+      CrTxTrainRank.Data  = MrcReadCR (MrcData, Offset);
+      FinalVal[0]         = (S16) (S32) CrTxTrainRank.Bits.TxEqualization;
+      FinalVal[1]         = (S16) (S32) ChannelOut->TxEq[Rank][Byte];
+      FinalVal[0]        &= 0xF;  // Read Deemphasize portion only
+      FinalVal[1]        &= 0xF;  // Read Deemphasize portion only
+    }
+    //
+    // RxEQ[4:0] CR Decoding (pF/kOhm)
+    //            [2:0]
+    //  [4:3]     0        1        2        3        4        5-7
+    //     0      0.5/.02  0.5/1.0  0.5/.50  0.5/.25  0.5/.12  rsvd
+    //     1      1.0/.02  1.0/1.0  1.0/.50  1.0/.25  1.0/.12  rsvd
+    //     2      1.5/.02  1.5/1.0  1.5/.50  1.5/.25  1.5/.12  rsvd
+    //     3      2.0/.02  2.0/1.0  2.0/.50  2.0/.25  2.0/.12  rsvd
+    // Sweep = 0-19        [4:3] = (Sweep/5)  [2:0] = (Sweep%5)
+    //
+    if (OptParam == OptRxEq) {
+      Offset = DDRDATA0CH0_CR_RXTRAINRANK0_REG +
+        ((DDRDATA0CH1_CR_RXTRAINRANK0_REG - DDRDATA0CH0_CR_RXTRAINRANK0_REG) * Channel) +
+        ((DDRDATA0CH0_CR_RXTRAINRANK1_REG - DDRDATA0CH0_CR_RXTRAINRANK0_REG) * Rank) +
+        ((DDRDATA1CH0_CR_RXTRAINRANK0_REG - DDRDATA0CH0_CR_RXTRAINRANK0_REG) * Byte);
+
+      CrRxTrainRank.Data = MrcReadCR (MrcData, Offset);
+      FinalVal[0] = (S16) (S32) CrRxTrainRank.Bits.RxEq;
+      FinalVal[1] = (S16) (S32) ChannelOut->RxEq[Rank][Byte];
+      FinalVal[0] = ((FinalVal[0] >> 3) * 5) + (FinalVal[0] & 0x7);  // Multiply Cap portion by 5 and add Res portion
+      FinalVal[1] = ((FinalVal[1] >> 3) * 5) + (FinalVal[1] & 0x7);  // Multiply Cap portion by 5 and add Res portion
+    }
+
+    if (FinalVal[0] != FinalVal[1]) {
+      MRC_DEBUG_MSG (
+        Debug,
+        MSG_LEVEL_NOTE,
+        "Error: Param %s: CR value %d doesn't match Host value %d for Channel=%d, Rank=%d, Byte=%d\n",
+        TOptParamOffsetString[OptParam],
+        FinalVal[0],
+        FinalVal[1],
+        Channel,
+        Rank,
+        Byte
+        );
+    }
+  }
+  //
+  // RX Amplifier BIAS
+  //
+  if ((OptParam == OptRxBias)) {
+    //
+    // Mapping: [0: 0.44, 1: 0.66, 2: 0.88, 3: 1.00, 4: 1.33, 5: 1.66, 6: 2.00, 7: 2.33]
+    //
+    Offset = DDRDATA0CH0_CR_DDRCRDATACONTROL1_REG +
+      ((DDRDATA1CH0_CR_DDRCRDATACONTROL1_REG - DDRDATA0CH0_CR_DDRCRDATACONTROL1_REG) * Byte) +
+      ((DDRDATA0CH1_CR_DDRCRDATACONTROL1_REG - DDRDATA0CH0_CR_DDRCRDATACONTROL1_REG) * Channel);
+
+    DdrCrDataControl1Cr.Data    = MrcReadCR (MrcData, Offset);
+    DdrCrDataControl1Host.Data  = ChannelOut->DqControl1[Byte].Data;
+    FinalVal[0]                 = (S16) (S32) DdrCrDataControl1Cr.Bits.RxBiasCtl;
+    FinalVal[1]                 = (S16) (S32) DdrCrDataControl1Host.Bits.RxBiasCtl;
+
+    if (FinalVal[0] != FinalVal[1]) {
+      MRC_DEBUG_MSG (
+        Debug,
+        MSG_LEVEL_NOTE,
+        "Error: Param %s: CR value %d doesn't match Host value %d for Channel=%d, Byte=%d\n",
+        TOptParamOffsetString[OptParam],
+        FinalVal[0],
+        FinalVal[1],
+        Channel,
+        Byte
+        );
+    }
+  }
+  //
+  // Dimm Ron value
+  //
+  if ((OptParam == OptDimmRon)) {
+    //
+    // DIMM Ron Encoding   DriverImpCtrl[A5,A1]
+    //
+    if (MrcRankInChannelExist (MrcData, Rank, Channel)) {
+      MrReg = &ChannelOut->Dimm[Rank / 2].Rank[(Rank % 2)].MR[mrMR0];
+#ifdef ULT_FLAG
+      if (Lpddr) {
+        DimmRonMask = (MRC_BIT3 | MRC_BIT2 | MRC_BIT1 | MRC_BIT0);
+        MRValue     = (MrReg[mrMR3] & DimmRonMask);
+
+        for (Index = 0; Index < (sizeof (LpddrRonEnc) / sizeof (LpddrRonEnc[0])); Index++) {
+          if (MRValue == LpddrRonEnc[Index]) {
+            FinalVal[1] = (S16) (S8) Index;
+          }
+        }
+      } else
+#endif
+      {
+        MRValue     = MrReg[mrMR1];
+        FinalVal[1] = (S16) ((MRValue >> 1) & 0x1);
+      }
+    }
+  }
+  //
+  // DIMM ODT Values
+  //
+  if ((OptParam == OptDimmOdt) || (OptParam == OptDimmOdtWr)) {
+    //
+    // DIMM ODT Encoding   RttNom[A9,A6,A2]   RttWr[A10, A9] LPDDR - No RttNom
+    //
+    if (MrcRankInChannelExist (MrcData, Rank, Channel)) {
+#ifdef ULT_FLAG
+      if (Lpddr) {
+        RttWrMask = (MRC_BIT1 | MRC_BIT0);
+        MRValue   = (ChannelOut->Dimm[Rank / 2].Rank[Rank % 2].MR11 & RttWrMask);
+
+        for (Index = 0; Index < (sizeof (LpddrOdtEnc) / sizeof (LpddrOdtEnc[0])); Index++) {
+          if (MRValue == LpddrOdtEnc[Index]) {
+            FinalVal[1] = (S16) (S8) Index;
+          }
+        }
+
+        FinalVal[0] = 0;
+      } else
+#endif
+      {
+        MrReg       = &ChannelOut->Dimm[Rank / 2].Rank[Rank % 2].MR[mrMR0];
+        RttNomMask  = (MRC_BIT9 + MRC_BIT6 + MRC_BIT2);
+        RttWrMask   = (MRC_BIT10 + MRC_BIT9);
+        RttWr       = (MrReg[mrMR2] & RttWrMask) >> 9;
+        RttNom      = (MrReg[mrMR1] & RttNomMask) >> 2;
+
+        for (Index = 0; Index < sizeof (RttNomMRSEncodingConst) / sizeof (RttNomMRSEncodingConst[0]); Index++) {
+          if (RttNom == RttNomMRSEncoding[Index]) {
+            FinalVal[0] = (S16) (S8) Index;
+          }
+        }
+
+        for (Index = 0; Index < sizeof (RttWrMRSEncodingConst) / sizeof (RttWrMRSEncodingConst[0]); Index++) {
+          if (RttWr == RttWrMRSEncoding[Index]) {
+            FinalVal[1] = (S16) (S8) Index;
+          }
+        }
+      }
+    }
+  }
+}
+
+/**
+  This function will print out the last margin data collected of the Param passed in.
+  It will print both edges of all the requested bytes, Ranks and Channels.
+  NOTE: The function will not check to see if the Rank/Channel exists.  It will print out the
+  values stored in the margin array regardless of population status.
+
+  @param[in]  MrcData     - Global MRC data.
+  @param[in]  Param       - Parameter of MRC_MarginTypes of which to print the margin.
+  @param[in]  ChannelMask - Bit mask of channels to print.
+  @param[in]  RankMask    - Bit mask of ranks to print.
+  @param[in]  ByteMask    - Bit mask of bytes to print.
+
+  @retval Nothing.
+**/
+void
+MrcPrintLastMargins (
+  IN MrcParameters *const MrcData,
+  IN const U8             Param,
+  IN const U8             ChannelMask,
+  IN const U8             RankMask,
+  IN const U16            ByteMask
+  )
+{
+  MrcDebug const  *Debug;
+  MrcOutput       *Outputs;
+  char            *EdgeString;
+  MrcMarginResult LastResultParam;
+  U32             (*LastMargins)[MAX_RANK_IN_CHANNEL][MAX_CHANNEL][MAX_SDRAM_IN_DIMM][MAX_EDGES];
+  U8              Channel;
+  U8              Rank;
+  U8              Byte;
+  U8              Edge;
+
+  LastResultParam = GetMarginResultType (Param);
+  Debug           = &MrcData->SysIn.Inputs.Debug;
+  Outputs         = &MrcData->SysOut.Outputs;
+  LastMargins     = Outputs->MarginResult;
+
+  MRC_DEBUG_MSG (
+    Debug,
+    MSG_LEVEL_NOTE,
+    "%s Last Margins:\n",
+    MarginTypesString[Param]
+    );
+
+  EdgeString = ((Param == RdV) || (Param == WrV)) ? "H" : "R";
+
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Byte\t");
+  for (Byte = 0; Byte < Outputs->SdramCount; Byte++) {
+    if ((1 << Byte) & ByteMask) {
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "% 10d", Byte);
+    }
+  }
+
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\nEdge\t");
+  for (Byte = 0; Byte < Outputs->SdramCount; Byte++) {
+    if ((1 << Byte) & ByteMask) {
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "    L    %s", EdgeString);
+    }
+  }
+
+  for (Rank = 0; Rank < MAX_RANK_IN_CHANNEL; Rank++) {
+    if ((1 << Rank) & RankMask) {
+      for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+        if ((1 << Channel) & ChannelMask) {
+          MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\nR%d.C%d\t", Rank, Channel);
+          for(Byte = 0; Byte < Outputs->SdramCount; Byte++) {
+            if ((1 << Byte) & ByteMask) {
+              for (Edge = 0; Edge < MAX_EDGES; Edge++) {
+                MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "% 5d", LastMargins[LastResultParam][Rank][Channel][Byte][Edge]);
+              }
+            }
+          }
+        }
+      }
+    }
+  }
+
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\n");  // End of table
+}
+#endif // #if 0
+
+/**
+  This function implements switch to print the correct format and data for the 
+  OptResultsPerByte struct members.
+
+  @param[in] Debug     - Debug pointer for printing.
+  @param[in] Data      - Pointer to OptResultsPerByte struct.
+  @param[in] TypeIndex - Member of OptResultsPerByte to print.
+  @param[in] TestIndex - Some parameters store multiple test results to be printed.
+  @param[in] MidPoint  - Used to convert from zero-based indexing to the selected value
+
+  @retval Nothing.
+**/
+void
+MrcOptResultsPerBytePrint (
+  IN const MrcDebug *const Debug,
+  IN OptResultsPerByte      *Data,
+  IN U8                     TypeIndex,
+  IN U8                     TestIndex,
+  IN S8                     MidPoint
+  )
+{
+  switch (TypeIndex) {
+    case (MrcOptResultBest):
+      (TestIndex == 0) ? MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "=== %d ===", Data->Best - MidPoint) :
+                         MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\t");
+      break;
+
+    case (MrcOptResultGrdBnd):
+      (TestIndex == 0) ? MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "*** %d ***", Data->GuardBand) :
+                         MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\t");
+      break;
+
+    case(MrcOptResultOffSel):
+      (TestIndex == 0) ? MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "--> %d <--", Data->Best - MidPoint + Data->GuardBand) :
+                         MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\t");
+      break;
+
+    case (MrcOptResultScale):
+      MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%d\t", Data->Scale[TestIndex]);
+      break;
+
+    case (MrcOptResultSignal):
+      MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%d.%d%s\t", Data->Signal[TestIndex] / 100, Data->Signal[TestIndex] % 100 / 10, "%");
+      break;
+
+    case (MrcOptResultNoise):
+      MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%d.%d%s\t", Data->Noise[TestIndex] / 100, Data->Noise[TestIndex] % 100 / 10, "%");
+      break;
+
+    case (MrcOptResultRatio):
+      MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%d.%d\t", Data->Ratio[TestIndex] / 1000, Data->Ratio[TestIndex] % 1000 / 100);
+      break;
+
+    case (MrcOptResultMaxPost):
+      MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%d\t", Data->MaxPost[TestIndex]);
+      break;
+
+    case (MrcOptResultMinPost):
+      MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%d\t", Data->MinPost[TestIndex]);
+      break;
+
+    case (MrcOptResultTicks):
+      MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%d.%d\t", Data->Ticks[TestIndex] / 10, Data->Ticks[TestIndex] % 10);
+      break;
+
+    case (MrcOptResultSnrTot):
+      (TestIndex == 0) ? MRC_DEBUG_MSG (
+                  Debug,
+                  MSG_LEVEL_NOTE,
+                  " %d.%d%s\t",
+                  (U32) Data->SNRTotal / 100,
+                  (U32) Data->SNRTotal % 100 / 10,
+                  "%"
+                  ) : MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\t");
+      break; // assuming we dont exceed 32 bits
+
+    default:
+      MRC_DEBUG_MSG (Debug, MSG_LEVEL_ERROR, "OptResultPerByteDbgStr Switch exceeded number of cases defined\n");
+  }
+}
+
+
+/**
+  This function prints the Optimize margin result table
+  e.g: calcResultSummary[MAX_CHANNEL][MAX_SDRAM_IN_DIMM]
+
+  @param[in] MrcData           - MRC data structure
+  @param[in] calcResultSummary - The data array [MAX_CHANNEL][MAX_SDRAM_IN_DIMM]
+  @param[in] TestList          - Test list
+  @param[in] NumTest           - Number of test
+  @param[in] NumOffsets        - Number of offsets
+  @param[in] MidPoint          - Middle point
+  @param[in] IncEnds           - Print ends points
+  @param[in] OptParam          - Used to convert to the Opt param string for printing
+  @param[in] OptPower          - Opt Power values to be printed
+  @param[in] Channel           - Channel to print
+  @param[in] Ranks             - Ranks to print
+  @param[in] TrendLine         - Switch to print the trend line
+  @param[in] Nibble            - take low/high bytes
+  @param[in] perCh             - Switch to only print 1 Byte of data
+  @param[in] noPrint           - Boolean used to disable printing of results
+
+  @retval Nothing
+**/
+void
+PrintCalcResultTableCh (
+  IN MrcParameters *const MrcData,
+  IN OptResultsPerByte    calcResultSummary[MAX_CHANNEL][MAX_SDRAM_IN_DIMM],
+  IN U8                   *TestList,
+  IN U8                   NumTest,
+  IN U8                   NumOffsets,
+  IN S8                   MidPoint,
+  IN BOOL                 IncEnds,
+  IN U8                   OptParam,
+  IN U16                  *OptPower,
+  IN U8                   Channel,
+  IN U8                   Ranks,
+  IN BOOL                 TrendLine,
+  IN U8                   Nibble,
+  IN BOOL                 perCh,
+  IN BOOL                 noPrint
+  )
+{
+  const MrcDebug    *Debug;
+  OptResultsPerByte *data;
+  S8                Off;
+  S8                Start;
+  S8                Stop;
+  U8                i;
+  U8                j;
+  U8                b;
+  U8                FirstByte;
+  U8                NumBytes;
+  U8                NumTestPlus;
+  U32               Result;
+  BOOL              Format64Results;
+  U8                Param;
+
+  Format64Results = 1;
+  //
+  // Display result in %/Delta , 0-displat raw 64bit result in HEX
+  //
+  Debug = &MrcData->SysIn.Inputs.Debug;
+  Start = (!IncEnds);
+  Stop  = NumOffsets - (!IncEnds);
+  if (noPrint) {
+    return ;
+
+  }
+
+  FirstByte = (Nibble) ? 4 : 0;
+  NumBytes  = FirstByte + 4 + Nibble * MrcData->SysOut.Outputs.SdramCount % 8;
+  if (perCh) {
+    NumBytes = 1;
+  }
+
+  NumTestPlus = (TrendLine) ? NumTest + 1 : NumTest;
+
+  MRC_DEBUG_MSG (
+    Debug,
+    MSG_LEVEL_NOTE,
+    "\n<======== optimize %s ========>Plot results ",
+    TOptParamOffsetString[OptParam]
+    );
+  MRC_DEBUG_MSG (
+    Debug,
+    MSG_LEVEL_NOTE,
+    "<Channel=%d><rank/s=0x%x><Nibble=%s> across settings :(Start=%d,Stop=%d)\n",
+    Channel,
+    Ranks,
+    (Nibble) ? "High" : "Low",
+    Start - MidPoint,
+    Stop - MidPoint - 1
+    );
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Bytes\t");
+  for (b = FirstByte; b < NumBytes; b++) {
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%d\t", b);
+    for (i = 0; i < NumTestPlus + 1; i++) {
+      MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\t"); // tab insertion
+    }
+  }
+
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\n"); // row end here !
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Offset\t"); // row starts here !
+  if (OptPower[Stop - 1] != 0) {//WA: need to add param to enable this print
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%s\t", 3 + TOptParamOffsetString[OptParam]);
+  }
+
+  for (b = FirstByte; b < NumBytes; b++) {
+    for (i = 0; i < NumTest; i++) {
+      //
+      // Test types header
+      //
+      Param = TestList[i];
+      if (Param > CmdV) {
+        Param = (Param % 16) + 4;
+      }
+
+      MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%s\t", MarginTypesString[Param]);
+    }
+
+    if (TrendLine) {
+      MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%s\t", "T.line");
+    }
+
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Opt.func\t"); // more header..
+  }
+
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\n\n"); // row end here !
+  for (Off = Start; Off < Stop; Off++) {
+    //
+    // row starts here !
+    //
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%d\t", Off - MidPoint);
+    if (OptPower[Stop - 1] != 0) {
+      MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%d\t", OptPower[Off]);
+    }
+
+    for (b = FirstByte; b < NumBytes; b++) {
+      if (b < MAX_SDRAM_IN_DIMM) {
+        data = &calcResultSummary[Channel][b];
+      } else {
+        MRC_DEBUG_MSG (
+          Debug,
+          MSG_LEVEL_NOTE,
+          "Error: calcResultSummary array out of bounds! %d > %d \n",
+          b,
+          MAX_SDRAM_IN_DIMM - 1
+          );
+        return;
+      }
+
+      for (i = 0; i < NumTestPlus; i++) {
+        MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%d\t", data->Margins[i][Off].EW);
+      }
+
+      if (Format64Results) {
+        Result = (U32) (MrcOemMemoryDivideU64ByU64 (MrcOemMemoryMultiplyU64ByU32 (data->Result[Off], 200), data->MaxR));
+        Result /= 2;
+        MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%d\t\t", Result);
+      }
+
+      if (!Format64Results) {
+        MRC_DEBUG_MSG (
+          Debug,
+          MSG_LEVEL_NOTE,
+          "%08x-%08x\t\t",
+          (U32) MrcOemMemoryRightShiftU64 (data->Result[Off],
+                32),
+          (U32) (data->Result[Off])
+          );
+      }
+    }
+
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\n"); // row end here !
+  }
+
+  for (i = 0; i < (sizeof (OptResultDbgStrings) / sizeof (*OptResultDbgStrings)); i++) {
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%s\t", OptResultDbgStrings[i]);
+    for (b = FirstByte; b < NumBytes; b++) {
+      if (b < MAX_SDRAM_IN_DIMM) {
+        data = &calcResultSummary[Channel][b];
+      } else {
+        MRC_DEBUG_MSG (
+          Debug,
+          MSG_LEVEL_NOTE,
+          "Error: calcResultSummary array out of bounds! %d > %d \n",
+          b,
+          MAX_SDRAM_IN_DIMM - 1
+          );
+        return;
+      }
+
+      for (j = 0; j < NumTestPlus; j++) {
+        MrcOptResultsPerBytePrint (Debug, data, i, j, MidPoint);
+      }
+
+      MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\t\t"); // tab insertion
+    }
+
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\n");
+  } // row end here !
+  return;
+}
+
+/**
+  This function prints the Optimize margin result table
+  e.g: calcResultSummary[MAX_CHANNEL][MAX_SDRAM_IN_DIMM]
+
+  @param[in] MrcData           - MRC data structure
+  @param[in] calcResultSummary - The data array [MAX_CHANNEL][MAX_SDRAM_IN_DIMM]
+  @param[in] DimmOptPoints     - add argument and description to function comment
+  @param[in] TestList          - Test list
+  @param[in] NumTest           - Number of test
+  @param[in] NumOffsets        - Number of offsets
+  @param[in] MidPoint          - Middle point
+  @param[in] IncEnds           - Print ends points
+  @param[in] OptParam          - Used to convert to the Opt param string for printing
+  @param[in] Channel           - Channel to print
+  @param[in] Ranks             - Ranks to print
+  @param[in] TrendLine         - Switch to print the trend line
+  @param[in] Nibble            - take low/high bytes
+  @param[in] perCh             - Switch to only print 1 Byte of data
+
+  @retval Nothing
+**/
+void
+PrintODTResultTable (
+  IN MrcParameters *const MrcData,
+  IN OptResultsPerByte    *calcResultSummary,
+  IN DimmOptPoint         *DimmOptPoints,
+  IN U8                   NumOffsets,
+  IN S8                   MidPoint,
+  IN BOOL                 IncEnds,
+  IN U8                   OptParam,
+  IN U8                   Channel,
+  IN U8                   Ranks,
+  IN BOOL                 TrendLine,
+  IN U8                   Nibble,
+  IN BOOL                 perCh
+  )
+{
+  const char        *OdtStrings[] = {
+    "RttNom0",
+    "RttNom1",
+    "RttWr0",
+    "RttWr1",
+    "RdOdt",
+    "Pwr[mW]",
+    "Cpu Rd",
+    "Dim Rd",
+    "Cpu Wr",
+    "DimW-T",
+    "DimW-NT",
+    "ACPower"
+  };
+  const MrcDebug    *Debug;
+  MrcOutput         *Outputs;
+  OptResultsPerByte *data;
+  S8                Off;
+  S8                Start;
+  S8                Stop;
+  U8                i;
+  U8                j;
+  U8                b;
+  U8                r;
+  U8                FirstByte;
+  U8                NumBytes;
+  U8                NumTestPlus;
+  U8                *TestList;
+  U8                Param;
+  U32               Result;
+  U8                OptResultType;
+  BOOL              Format64Results; // Display result in %/MaxR , 0-display raw 64bit result in HEX
+  BOOL              printOptSetting;
+  U64               delta;
+
+  Format64Results = 1;
+  printOptSetting = 1;
+  Debug           = &MrcData->SysIn.Inputs.Debug;
+  Outputs         = &MrcData->SysOut.Outputs;
+  Start           = (!IncEnds);
+  Stop            = NumOffsets - (!IncEnds);
+  TestList        = DimmOptPoints[0].TestList;
+  FirstByte       = (Nibble) ? 4 : 0;
+  NumBytes        = FirstByte + 4 + Nibble * MrcData->SysOut.Outputs.SdramCount % 8;
+  Ranks          &= Outputs->Controller[0].Channel[Channel].ValidRankBitMask;
+
+  if (perCh) {
+    NumBytes = 1;
+  }
+
+  NumTestPlus = (TrendLine) ? DimmOptPoints[0].NumTests + 1 : DimmOptPoints[0].NumTests;
+  //
+  // RttNomOffset = (MrcData->Outputs.Channel[Channel].DimmCount == 1) ? 0 : RttOffset; // if 2DPC - RttNom 40,30,20 Ohms
+  //
+  MRC_DEBUG_MSG (
+    Debug,
+    MSG_LEVEL_NOTE,
+    "\n<======== optimize %s ========>Plot results ",
+    TOptParamOffsetString[OptParam]
+    );
+  MRC_DEBUG_MSG (
+    Debug,
+    MSG_LEVEL_NOTE,
+    "<Channel=%d><rank/s=0x%x> across settings :(Start=%d,Stop=%d)\n",
+    Channel,
+    Ranks,
+    Start - MidPoint,
+    Stop - MidPoint - 1
+    );
+  //
+  // MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "ODT\t");
+  // for (b = 0; b < (sizeof(OdtStrings)/sizeof(*OdtStrings)); b++) {
+  //  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%s\t",OdtStrings[b] );
+  //  for (i = 0; i < NumTestPlus+1; i++) MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\t");//tab insertion
+  // }
+  // MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\n");//row end here!
+  //
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Offset\t"); // row starts here!
+  for (b = 0; b < (sizeof (OdtStrings) / sizeof (*OdtStrings)); b++) {
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%s\t", OdtStrings[b]);
+  }
+
+  for (i = 0; i < DimmOptPoints[0].NumTests; i++) {
+    //
+    // Test types header
+    //
+    Param = TestList[i];
+    if (Param > CmdV) {
+      Param = (Param % 16) + 4;
+    }
+
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%s\t", MarginTypesString[Param]);
+  }
+
+  if (TrendLine) {
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%s\t", "T.line");
+  }
+
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Opt.func\t"); // more header
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\n\n");
+
+  for (Off = Start; Off < Stop; Off++) {
+    //
+    // row starts here !
+    //
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%d\t", Off - MidPoint);
+    for (b = 0; b < (sizeof (OdtStrings) / sizeof (*OdtStrings)); b++) {
+      if (b == 0) {
+        MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%d\t", ActualDimmOdt[DimmOptPoints[Off].ODTSet.RttNom[Channel][0]]);
+      }
+
+      if (b == 1) {
+        MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%d\t", ActualDimmOdt[DimmOptPoints[Off].ODTSet.RttNom[Channel][1]]);
+      }
+
+      if (b == 2) {
+        MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%d\t", ActualDimmOdt[DimmOptPoints[Off].ODTSet.RttWr[Channel][0]]);
+      }
+
+      if (b == 3) {
+        MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%d\t", ActualDimmOdt[DimmOptPoints[Off].ODTSet.RttWr[Channel][1]]);
+      }
+
+      if (b == 4) {
+        MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%d\t", CalcRdOdt (MrcData, DimmOptPoints[Off].ODTSet.GRdOdt));
+      }
+
+      if (b == 5) {
+        MRC_DEBUG_MSG (
+          Debug,
+          MSG_LEVEL_NOTE,
+          "%d.%d\t",
+          DimmOptPoints[Off].PowerCalc.TotPwr / 10,
+          DimmOptPoints[Off].PowerCalc.TotPwr % 10
+          );
+      }
+
+      if (b == 6) {
+        MRC_DEBUG_MSG (
+          Debug,
+          MSG_LEVEL_NOTE,
+          "%d.%d\t",
+          DimmOptPoints[Off].PowerCalc.CpuPwrRd / 10,
+          DimmOptPoints[Off].PowerCalc.CpuPwrRd % 10
+          );
+      }
+
+      if (b == 7) {
+        MRC_DEBUG_MSG (
+          Debug,
+          MSG_LEVEL_NOTE,
+          "%d.%d\t",
+          DimmOptPoints[Off].PowerCalc.DimmPwrRd / 10,
+          DimmOptPoints[Off].PowerCalc.DimmPwrRd % 10
+          );
+      }
+
+      if (b == 8) {
+        MRC_DEBUG_MSG (
+          Debug,
+          MSG_LEVEL_NOTE,
+          "%d.%d\t",
+          DimmOptPoints[Off].PowerCalc.CpuPwrWr / 10,
+          DimmOptPoints[Off].PowerCalc.CpuPwrWr % 10
+          );
+      }
+
+      if (b == 9) {
+        MRC_DEBUG_MSG (
+          Debug,
+          MSG_LEVEL_NOTE,
+          "%d.%d\t",
+          DimmOptPoints[Off].PowerCalc.DimmPwrWrT / 10,
+          DimmOptPoints[Off].PowerCalc.DimmPwrWrT % 10
+          );
+      }
+
+      if (b == 10) {
+        MRC_DEBUG_MSG (
+          Debug,
+          MSG_LEVEL_NOTE,
+          "%d.%d\t",
+          DimmOptPoints[Off].PowerCalc.DimmPwrWrNT / 10,
+          DimmOptPoints[Off].PowerCalc.DimmPwrWrNT % 10
+          );
+      }
+
+      if (b == 11) {
+        MRC_DEBUG_MSG (
+          Debug,
+          MSG_LEVEL_NOTE,
+          "%d.%d\t",
+          DimmOptPoints[Off].PowerCalc.ACPower / 10,
+          DimmOptPoints[Off].PowerCalc.ACPower % 10
+          );
+      }
+    }
+
+    data = calcResultSummary;
+    for (i = 0; i < NumTestPlus; i++) {
+      MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%d\t", data->Margins[i][Off].EW);
+    }
+
+    delta = data->MaxR - data->MinR + 1; // +1 to not divide by 0
+    if (Format64Results) {
+      Result = (U32) (MrcOemMemoryDivideU64ByU64 (MrcOemMemoryMultiplyU64ByU32 (data->Result[Off], 200), data->MaxR));
+      Result /= 2;
+      MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%d\t\t", Result);
+    } else {
+      MRC_DEBUG_MSG (
+        Debug,
+        MSG_LEVEL_NOTE,
+        "%08x-%08x\t\t",
+        (U32) MrcOemMemoryRightShiftU64 (data->Result[Off],
+              32),
+        (U32) (data->Result[Off])
+        );
+    }
+
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\n"); // row end here !
+    if (printOptSetting) {
+      for (i = 0; i < DimmOptPoints[0].OptParamTestListSize; i++) {
+        OptResultType = GetOptResultType (DimmOptPoints[0].OptParamTestList[i]);
+        MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%s  \t", TOptParamOffsetString[DimmOptPoints[0].OptParamTestList[i]]);
+        if ((OptResultType == RxEqOfft) || (OptResultType == TxEqOfft)) {
+          //
+          // MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\n");
+          //
+          for (r = 0; r < MAX_RANK_IN_CHANNEL; r++) {
+            if (!(Ranks & (0x1 << r))) {
+              continue;
+            }
+
+            MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "<Rank %d>|", r);
+            for (b = 0; b < Outputs->SdramCount; b++) {
+              MRC_DEBUG_MSG (
+                Debug,
+                MSG_LEVEL_NOTE,
+                "%02d|",
+                DimmOptPoints[Off].BestOptOff[OptResultType][r].Offset[Channel][b]
+                );
+            }
+
+            MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\t");
+          }
+        } else {
+          for (b = 0; b < Outputs->SdramCount; b++) {
+            MRC_DEBUG_MSG (
+              Debug,
+              MSG_LEVEL_NOTE,
+              "%d|",
+              DimmOptPoints[Off].BestOptOff[OptResultType][0].Offset[Channel][b]
+              );
+          }
+        }
+
+        MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\n"); // row end here !
+      }
+    }
+
+  }
+
+  for (i = 0; i < (sizeof (OptResultDbgStrings) / sizeof (*OptResultDbgStrings)); i++) {
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%s\t", OptResultDbgStrings[i]);
+    for (b = FirstByte; b < NumBytes; b++) {
+      data = calcResultSummary;
+      for (j = 0; j < NumTestPlus; j++) {
+        MrcOptResultsPerBytePrint (Debug, data, i, j, MidPoint);
+      }
+
+      MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\t\t");  // tab insertion
+    }
+
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\n");
+  } // row end here !
+}
+
+/**
+  This function prints the Optimize margin result table
+  e.g: MarginResult[Test][Offset][Channel][Byte][sign]
+
+  @param[in] MrcData     - MRC data structure
+  @param[in] ChMask      - Channels to print
+  @param[in] ResultArray - Array with saved margin results
+  @param[in] TestNum     - Test index
+  @param[in] OffsetsNum  - number of offsets
+  @param[in] MidPoint    - Zero point
+  @param[in] Edges       - 1 edge or 2 edge
+  @param[in] OptParam    - Used to convert to the Opt param string for printing
+  @param[in] Param       - Margin type to be printed.
+  @param[in] PowerLimits - Power limits to print.
+  @param[in] noPrint     - Used to skip printing.
+
+  @retval Nothing
+**/
+void
+PrintResultTableByte4by24 (
+  IN MrcParameters   *MrcData,
+  IN U8              ChMask,
+  IN U16             ResultArray[4][24][MAX_CHANNEL][MAX_SDRAM_IN_DIMM][MAX_EDGES],
+  IN U16             TestNum,
+  IN U8              OffsetsNum,
+  IN U8              MidPoint,
+  IN U8              Edges,
+  IN U8              OptParam,
+  IN U8              Param,
+  IN U16             *PowerLimits,
+  IN BOOL            noPrint
+  )
+{
+  const MrcDebug  *Debug;
+  MrcOutput       *Outputs;
+  U8              Channel;
+  U8              Byte;
+  S8              Off;
+  S8              Start;
+  S8              Stop;
+
+  Debug   = &MrcData->SysIn.Inputs.Debug;
+  Outputs = &MrcData->SysOut.Outputs;
+  Start   = -MidPoint;
+  Stop    = OffsetsNum - MidPoint - 1;
+  if (Param > CmdV) {
+    Param = (Param % 16) + 4;
+  }
+
+  if (noPrint) {
+    return;
+
+  }
+
+  MRC_DEBUG_MSG (
+    Debug,
+    MSG_LEVEL_NOTE,
+    "\nTest number : %d - %s ,Plot results across OptParam=%s settings:(Start=%d,Stop=%d) w/ power limits(width): %d \nChannel\t0                1\nByte\t",
+    TestNum,
+    MarginTypesString[Param],
+    TOptParamOffsetString[OptParam],
+    Start,
+    Stop,
+    PowerLimits[TestNum]
+    );
+  if (Outputs->SdramCount == 8) {
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "0\t1\t2\t3\t4\t5\t6\t7\t0\t1\t2\t3\t4\t5\t6\t7");
+  } else if (Outputs->SdramCount == 9) {
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "0\t1\t2\t3\t4\t5\t6\t7\t0\t1\t2\t3\t4\t5\t6\t7\t8");
+  }
+  //
+  // Sweep through OpParam settings
+  //
+  for (Off = Start; Off < Stop + 1; Off++) {
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\n  %d:\t", Off);
+    for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+      //
+      // spaces for non populated channel
+      //
+      if (!((0x1 << Channel) & ChMask)) {
+        if (Channel == 0) {
+          if (Outputs->SdramCount == 8) {
+            MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\t\t\t\t\t\t\t\t");
+          } else {
+            MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "                  ");
+          }
+        }
+
+        continue;
+      }
+
+      for (Byte = 0; Byte < Outputs->SdramCount; Byte++) {
+        if (Edges > 1) {
+          if (Byte < MAX_SDRAM_IN_DIMM) {
+            MRC_DEBUG_MSG (
+              Debug,
+              MSG_LEVEL_NOTE,
+              "%d-%d\t",
+              ResultArray[TestNum][Off - Start][Channel][Byte][0],
+              ResultArray[TestNum][Off - Start][Channel][Byte][1]
+              );
+          }
+        } else {
+          if (Byte < MAX_SDRAM_IN_DIMM) {
+            MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%d\t", ResultArray[TestNum][Off - Start][Channel][Byte][0]);
+          }
+        }
+      }
+    }
+  }
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\n");  // New line after the end of the table
+
+  return;
+}
+#endif // MRC_DEBUG_PRINT
+
+/**
+  This function returns the UPM or PWR limit value for the specified parameter
+
+  @param[in] MrcData   - Pointer to MRC global data.
+  @param[in] Param     - Margin type
+  @param[in] LimitType - Type of limit: UpmLimit or PowerLimit
+
+  @retval Returns the UPM or PWR limit
+**/
+U16
+UpmPwrLimitValue (
+  IN MrcParameters *const MrcData,
+  IN U8                   Param,
+  IN U8                   LimitType
+  )
+{
+  MrcOutput              *Outputs;
+  MrcUpmPwrRetrainLimits *MrcLimits;
+  U32                    Index;
+  U16                    Limit;
+#ifdef ULT_FLAG
+  U8                     Channel;
+#endif // ULT_FLAG
+
+  Limit     = 0;
+  Outputs   = &MrcData->SysOut.Outputs;
+  MrcLimits = Outputs->UpmPwrRetrainLimits.Pointer;
+
+  for (Index = 0; Index < MRC_NUMBER_UPM_PWR_RETRAIN_MARGINS; Index++) {
+    if (Param == MrcLimits[Index].Param) {
+      Limit = MrcLimits[Index].ParamLimit[LimitType];
+      break;
+    }
+  }
+
+#ifdef ULT_FLAG
+  if ((MrcData->SysIn.Inputs.CpuModel == cmHSW_ULT) && 
+      (Outputs->DdrType == MRC_DDR_TYPE_DDR3) &&
+      (Param == WrV) &&
+      (LimitType != RetrainLimit)
+      ) {
+    for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+      if (MrcChannelExist (Outputs, Channel)) {
+        if (Outputs->Controller[0].Channel[Channel].Dimm[0].ReferenceRawCard == rcF) {
+          Limit += 200;  // Add 20 ticks for WrV on HSW ULT with DDR3L and raw card F
+          break;
+        }
+      }
+    }
+  }
+#endif // ULT_FLAG
+
+  return Limit;
+}
+
+/**
+  This function will adjust the requested Limit Type of the margin parameter by the signed offset passed in.
+
+  @param[in]  MrcData   - MRC global data.
+  @param[in]  Param     - Margin parameter type to adjust.
+  @param[in]  LimitType - MRC_MARGIN_LIMIT_TYPE to adjust.
+  @param[in]  Offset    - The adjustment value.
+
+  @retval U16 - The new value of Param[MRC_MARGIN_LIMIT_TYPE]
+**/
+U16
+MrcUpdateUpmPwrLimits (
+  IN OUT MrcParameters * const  MrcData,
+  IN U8                         Param,
+  IN U8                         LimitType,
+  IN S8                         Offset
+  )
+{
+  MrcUpmPwrRetrainLimits  *MrcLimits;
+  U32                     Index;
+  S32                     UpdatedValue;
+
+  MrcLimits     = MrcData->SysOut.Outputs.UpmPwrRetrainLimits.Pointer;
+  UpdatedValue  = 0;
+
+  for (Index = 0; Index < MRC_NUMBER_UPM_PWR_RETRAIN_MARGINS; Index++) {
+    if (Param == MrcLimits[Index].Param) {
+      UpdatedValue = MrcLimits[Index].ParamLimit[LimitType];
+      break;
+    }
+  }
+
+  UpdatedValue += Offset;
+  UpdatedValue = MAX (UpdatedValue, 0);
+  UpdatedValue = MIN (UpdatedValue, 0xFFFF);
+
+  MrcLimits[Index].ParamLimit[LimitType] = (U16) UpdatedValue;
+
+  return (U16) UpdatedValue;
+}
+
+/**
+  This function returns the Actual Cpu Driver Impedance (1 segment) in ohm.
+
+  @param[in] MrcData - Pointer to MRC global data.
+  @param[in] Offset  - Vref Offset (+-8).
+
+  @retval Returns the CPU driver impedance value (for 1 segment)
+**/
+U16
+CalcDrvImp (
+  IN MrcParameters *const MrcData,
+  IN S8              Offset
+  )
+{
+  U16 Result;
+  U8  Rext;
+
+  Rext = 75;
+
+#ifdef ULT_FLAG
+  if (MrcData->SysIn.Inputs.CpuModel == cmHSW_ULT) {
+    Rext = 120;  // RCOMP1 resistor is 120 Ohm on HSW-ULT boards
+  }
+#endif // ULT_FLAG
+
+  //
+  // If Offset == -32, return 0;
+  //
+  if (Offset == -32) {
+    Result = 0;
+  } else {
+    Result = Rext * (32 - Offset) / (32 + Offset);
+  }
+
+  return Result;
+}
+
+/**
+  This function returns the Actual Cpu Odt termination in ohm.
+
+  @param[in] MrcData - Pointer to MRC global data.
+  @param[in] Offset  - Vref Offset (+-16).
+
+  @retval Returns the Odt termination value.
+**/
+U16
+CalcRdOdt (
+  IN MrcParameters *const MrcData,
+  IN S8                   Offset
+  )
+{
+  U16 Result;
+  U8  Rext;
+
+#ifdef ULT_FLAG
+  if (MrcData->SysIn.Inputs.CpuModel == cmHSW_ULT) {
+    Rext = 100; // 200 / 2
+  } else
+#endif //ULT_FLAG
+  {
+    Rext = 50; // 100 / 2
+  }
+
+  Result = (Rext * 96 / (Offset + 48) - Rext);
+
+  return Result;
+}
+
+/**
+  Calculate Power for the selected Opt param based on
+
+  @param[in] MrcData     - Include all MRC global data.
+  @param[in] Channel     - Channel to work on
+  @param[in] Rank        - Rank to work on
+  @param[in] Byte        - Byte to work on
+  @param[in] OptParam    - The Opt Parameter to work on
+  @param[in] Offset      - The Offset to work on
+  @param[in] CurrentComp - The current Comp code for OptParam
+  @param[in] ReadHost    - Switch to read current offset and CompCode from Host structure.
+
+  @retval Calc power in mW
+**/
+U32
+CalcOptPower (
+  IN MrcParameters   *MrcData,
+  IN U8              Channel,
+  IN U8              Rank,
+  IN U8              Byte,
+  IN U8              OptParam,
+  IN S8              Offset,
+  IN S8              CurrentComp,
+  IN BOOL            ReadHost
+  )
+{
+  U32                                       Power;
+  U16                                       Rleg;
+  S8                                        StatLegs;
+  U8                                        OdtLegsDis;
+  S8                                        CurrentVref;
+  U8                                        RxVselect;
+  U8                                        RxCBSelect;
+  S8                                        RxFselect;
+  U8                                        RxDefault;
+  extern const U8                           RxBiasTable[2][5][4];
+  U8                                        RxPowerScale[] = { 33, 66, 88, 100, 133, 166, 200, 233 };
+  U32                                       Vcc;
+  U32                                       CPURXPower;
+  MrcVddSelect                              Vdd;
+  MrcOutput                                 *Outputs;
+  MrcChannelOut                             *ChannelOut;
+  const MrcInput                            *Inputs;
+  const MrcDebug                            *Debug;
+  DDRCOMP_CR_DDRCRCOMPCTL0_STRUCT           DdrCrCompCtl0;
+  DDRDATA0CH0_CR_DDRCRDATAOFFSETCOMP_STRUCT DdrCrDataOffsetComp;
+  DDR3_MODE_REGISTER_1_STRUCT               Ddr3ModeRegister1;
+  DDRCOMP_CR_DDRCRDATACOMP0_STRUCT          DdrCrDataComp0;
+  DDRCOMP_CR_DDRCRDATACOMP1_STRUCT          DdrCrDataComp1;
+#ifdef ULT_FLAG
+  BOOL                                      Lpddr;
+  U16                                       DimmRon;
+  extern const U8                           RxBiasTableUlt[2][3][4];
+
+  Lpddr = (MrcData->SysOut.Outputs.DdrType == MRC_DDR_TYPE_LPDDR3);
+#endif //ULT_FLAG
+
+  Inputs                   = &MrcData->SysIn.Inputs;
+  Debug                    = &Inputs->Debug;
+  Outputs                  = &MrcData->SysOut.Outputs;
+  ChannelOut               = &Outputs->Controller[0].Channel[Channel];
+  DdrCrDataComp0.Data      = 0;
+  DdrCrDataComp1.Data      = 0;
+  DdrCrDataOffsetComp.Data = 0;
+  Power                    = 0;
+  Vdd                      = Outputs->VddVoltage[Inputs->MemoryProfile];
+
+  if ((OptParam == OptWrDS) || (OptParam == OptRdOdt) || (OptParam == OptSComp)) {
+    DdrCrDataOffsetComp.Data = ChannelOut->DataCompOffset[Byte];
+    if (OptParam == OptRdOdt) {
+      DdrCrDataComp1.Data = MrcReadCR (MrcData, DDRCOMP_CR_DDRCRDATACOMP1_REG);
+    } else {
+      DdrCrDataComp0.Data = MrcReadCR (MrcData, DDRCOMP_CR_DDRCRDATACOMP0_REG);
+    }
+  }
+
+  if (OptParam == OptWrDS) {
+    DdrCrCompCtl0.Data = Outputs->CompCtl0;
+    //
+    // Added Driver RCOMP Vref for driver impedance calculation
+    //
+    CurrentVref = (S8) DdrCrCompCtl0.Bits.DqDrvVref;
+    if (CurrentVref & 0x8) {
+      CurrentVref -= 0x10;  // 2's complement
+    }
+
+    if (ReadHost) {
+      CurrentComp = (S8) DdrCrDataComp0.Bits.RcompDrvUp;
+      Offset      = (S8) DdrCrDataOffsetComp.Bits.DqDrvUpCompOffset;
+
+      if (Offset & 0x20) {
+        Offset-= 0x40; // 2's complement
+      }
+    }
+
+    StatLegs = 3 * 4 * 4; // seg*legs*4 - for calc set to 48
+    Rleg  = CalcDrvImp (MrcData, CurrentVref) / 3 * (StatLegs + 3 * CurrentComp); // RCOMP Vref added to Rleg calculation
+    Power = Rleg / (StatLegs + 3 * (CurrentComp + (Offset))); // in ohm
+  }
+
+  if (OptParam == OptRdOdt) {
+    DdrCrCompCtl0.Data  = Outputs->CompCtl0;
+    OdtLegsDis          = (U8) DdrCrCompCtl0.Bits.DisableOdtStatic;
+    CurrentVref         = (S8) DdrCrCompCtl0.Bits.DqOdtVref;
+    StatLegs            = 4 * 4;  // we enable only 1/3 segment for odt 4 legs time 4
+
+    if (CurrentVref & 0x10) {
+      CurrentVref -= 0x20;  // 2's complement
+    }
+
+    if (ReadHost) {
+      CurrentComp = (S8) DdrCrDataComp1.Bits.RcompOdtUp;
+      Offset      = (S8) DdrCrDataOffsetComp.Bits.DqOdtUpCompOffset;
+      if (Offset & 0x10) {
+        Offset-= 0x20; // 2's complement
+      }
+    }
+    //
+    // Avoid division by zero.
+    //
+    if (CurrentComp == 0) {
+      CurrentComp = 1;
+    }
+    Rleg  = CalcRdOdt (MrcData, CurrentVref) * (StatLegs * (!OdtLegsDis) + CurrentComp);
+    Power = Rleg / (StatLegs * (!OdtLegsDis) + (CurrentComp + (Offset)));  // in ohm
+  }
+
+  if (OptParam == OptSComp) {
+    if (ReadHost) {
+      Offset = (S8) DdrCrDataOffsetComp.Bits.DqSlewRateCompOffset;
+      if (Offset & 0x10) {
+        Offset -= 0x20; // 2's complement
+      }
+    }
+    Power = 50 + Offset; // simple linear T-line
+  }
+
+  if (OptParam == OptTxEq) {
+    Power = Offset; // simple linear T-line
+  }
+
+  if (OptParam == OptRxEq) {
+    Power = 100 + (5 * (Offset / 5)); // modulo 5 T-line
+  }
+
+  if (OptParam == OptDimmRon) {
+    //
+    // calc the DimmRon [ohm]
+    //
+    if (ReadHost) {
+      if (Rank < MAX_RANK_IN_CHANNEL) {
+#ifdef ULT_FLAG
+        if (Lpddr) {
+          DimmRon = ChannelOut->Dimm[Rank / 2].Rank[Rank % 2].MR[mrMR3];
+          Offset  = (U8) 0xF & (DimmRon - 1); //{0x1,0x2,0x3}; //{34,40,48};
+        } else
+#endif //ULT_FLAG
+        {
+          Ddr3ModeRegister1.Data  = ChannelOut->Dimm[Rank / 2].Rank[Rank % 2].MR[mrMR1];
+          Offset                  = (U8) Ddr3ModeRegister1.Bits.ODImpedanceLow;
+        }
+      } else {
+        MRC_DEBUG_MSG (
+          Debug,
+          MSG_LEVEL_NOTE,
+          "Error: ChannelOut->Dimm array out of bounds! %d > %d\n",
+          Rank / 2,
+          MAX_DIMMS_IN_CHANNEL - 1
+          );
+        return 0;
+      }
+    }
+
+#ifdef ULT_FLAG
+    if (Lpddr) {
+      if (Offset > 6) {
+        MRC_DEBUG_MSG (
+          Debug,
+          MSG_LEVEL_NOTE,
+          "Offset %d causes negative unsigned number or divide by 0.  Dividing by 1.\n",
+          Offset
+          );
+        Offset = 6;
+      }
+
+      Power = 240 / (7 - Offset);
+    } else
+#endif //ULT_FLAG
+    {
+      if (Offset < -5) {
+        MRC_DEBUG_MSG (
+          Debug,
+          MSG_LEVEL_NOTE,
+          "Offset %d causes negative unsigned number or divide by 0.  Dividing by 1.\n",
+          Offset
+          );
+        Offset = -5;
+      }
+
+      Power = 240 / (6 + Offset);
+    }
+  }
+
+  if (OptParam == OptRxBias) {
+    //
+    // RX BIAS calculations
+    //
+    Vcc       = 1050;
+    RxVselect = 0;
+    if (Vdd > VDD_1_35) {
+      RxVselect = 1;  // Set HiVdd bit if Vdd is over 1.35v
+    }
+    //
+    // RX BIAS calculations
+    //
+    GetRxFselect (MrcData, &RxFselect, &RxCBSelect);
+
+#ifdef ULT_FLAG
+    if (MrcData->SysIn.Inputs.CpuModel == cmHSW_ULT) {
+      RxFselect = MIN (RxFselect, RXF_SELECT_MAX_ULT);              // Maximum 1600 MHz
+      RxDefault = RxBiasTableUlt[RxVselect][RxFselect][RxCBSelect]; // Read setting from array lookup table
+    } else
+#endif // ULT_FLAG
+    {
+      RxDefault = RxBiasTable[RxVselect][RxFselect][RxCBSelect];  // Read setting from array lookup table
+    }
+
+    CPURXPower = Vdd * 1200 / 1000 + Vcc * 1250 / 1000; // mW
+    CPURXPower /= 1000;
+    if (ReadHost) {
+      Offset = (U8) ChannelOut->DqControl1[Byte].Bits.RxBiasCtl;
+    }
+
+    CPURXPower  = (RxPowerScale[Offset] * CPURXPower) / RxPowerScale[RxDefault];
+    Power       = (U16) CPURXPower;
+  }
+
+  return Power;
+}
+
+/**
+  This function prints out the Margin eye diagram for ParamT/ParamV.
+
+
+  @param[in] MrcData - Include all MRC global data.
+  @param[in] Channel - Channel to margin.
+  @param[in] Ranks   - Bit mask of Ranks to margin.
+  @param[in] ParamT  - Time parameter to margin.
+  @param[in] ParamV  - Voltage parameter to margin.
+  @param[in] Start   - Starting point for margining.
+  @param[in] Stop    - Stopping point for margining.
+  @param[in] Repeats - Number of times to repeat the test to average out any noise.
+  @param[in] NoPrint - Switch to skip printing.
+
+  @retval Nothing
+**/
+void
+EyeMargin (
+  IN MrcParameters *const MrcData,
+  IN U8                   Channel,
+  IN U8                   Ranks,
+  IN U8                   ParamT,
+  IN U8                   ParamV,
+  IN S8                   Start,
+  IN S8                   Stop,
+  IN U16                  SearchLimits,
+  IN U8                   LoopCount,
+  IN U8                   Repeats,
+  IN BOOL                 NoPrint
+  )
+{
+  const MrcDebug    *Debug;
+  MrcOutput         *Outputs;
+  MrcChannelOut     *ChannelOut;
+  MrcControllerOut  *ControllerOut;
+  MrcStatus         Status;
+  U32               (*MarginByte)[MAX_RESULT_TYPE][MAX_RANK_IN_CHANNEL][MAX_CHANNEL][MAX_SDRAM_IN_DIMM][MAX_EDGES];
+  U32               BERStats[4];
+  U16               SaveMargin[63][MAX_CHANNEL][MAX_SDRAM_IN_DIMM][MAX_EDGES]; //40 Points X Ch X Byte X Hi/Lo
+  BOOL              Eye[63][108];
+  BOOL              Lines[108];
+  U8                MaxH=108;
+  U8                MaxW=63;
+  U8                i,j;
+  U16               MinEdge;
+  U16               Mode;
+  U8                ResultTypeV = 0;
+  U8                ChBitMask;
+  U8                Byte;
+  U8                Rank;
+  U8                Edge;
+  U8                FirstRank;
+  U8                NumBytes;
+  U8                BMap[9];  // Need by GetBERMarginByte
+  U8                MaxMarginV;
+  U8                localR[MAX_CHANNEL];
+  U8                Rep;
+  S8                Index;
+  U8                IndexOff;
+  S8                Off;
+  U8                byteMax[MAX_CHANNEL];
+  U32               Offset;
+  U64               CrValue64;
+
+  Debug         = &MrcData->SysIn.Inputs.Debug;
+  Outputs       = &MrcData->SysOut.Outputs;
+  MarginByte    = &Outputs->MarginResult;
+  Ranks        &= Outputs->ValidRankMask;
+  ControllerOut = &Outputs->Controller[0];
+  IndexOff      = 0;
+  CrValue64     = 0x0ULL; //64 bit Data bit mask
+
+  MrcOemMemorySet ((U8 *) localR, 0, sizeof(localR));
+  MrcOemMemorySet ((U8 *) Eye, 0, sizeof(Eye));
+  MrcOemMemorySet ((U8 *) Lines, 0, sizeof(Lines));
+  MrcOemMemorySet ((U8 *) SaveMargin, 0, sizeof(SaveMargin));
+  MrcOemMemorySetDword (BERStats, 0, sizeof(BERStats) / sizeof (U32));
+  for (Byte = 0; Byte < sizeof (BMap) / sizeof (BMap[0]); Byte++) {
+    BMap[Byte] = Byte;
+  }
+
+  Outputs->EnDumRd = 0;
+  SetupIOTestBasicVA(MrcData, 1<<Channel, LoopCount, 0, 0, 0,8);  //set test to all channels
+  //
+  // Select All Ranks for REUT test
+  //
+  ChannelOut      = &ControllerOut->Channel[Channel];
+  localR[Channel] = ChannelOut->ValidRankBitMask & Ranks;
+  //
+  // use ChBitMask from here down - if ch is set that mean at least 1 rank for testing, also remove ch w/o active ranks
+  //
+  ChBitMask = SelectReutRanks (MrcData, Channel, localR[Channel], 0);
+
+  if (ChBitMask == 0) {
+    return ;
+  }
+
+  for (Byte = 0; Byte < Outputs->SdramCount; Byte++) {
+    ChannelOut->DataOffsetTrain[Byte] = 0;
+  }
+  //
+  // Find the first selected rank
+  //
+  FirstRank = 0;
+  for (Rank = 0; Rank < MAX_RANK_IN_CHANNEL; Rank++) {
+    if ((1 << Rank) & localR[Channel]) {
+      FirstRank = Rank;  // could be in any channel
+      break;
+    }
+  }
+  //
+  // Store margin results for
+  //
+  NumBytes = (U8) Outputs->SdramCount;
+
+  //
+  // Loop through all Test Params and Measure Margin
+  // Find MaxMargin for this channel
+  //
+  byteMax[Channel] = Stop;
+  if (ParamT == RdT) {
+    for (Byte = 0; Byte < Outputs->SdramCount; Byte++) {
+      byteMax[Channel] = MrcCalcMaxRxMargin (MrcData, Channel, Ranks, Byte, 0, byteMax[Channel]);
+    }
+  }
+
+  Offset = MCHBAR_CH0_CR_REUT_CH_ERR_DATA_MASK_REG +
+    ((MCHBAR_CH1_CR_REUT_CH_ERR_DATA_MASK_REG - MCHBAR_CH0_CR_REUT_CH_ERR_DATA_MASK_REG) * Channel);
+
+  MrcWriteCR64 (MrcData, Offset, CrValue64);
+  MaxMarginV = MAX_POSSIBLE_VREF;
+  if (MAX_POSSIBLE_TIME < Stop) {
+    Stop = MAX_POSSIBLE_TIME;
+  }
+
+  if (-MAX_POSSIBLE_TIME > Start) {
+    Start = -MAX_POSSIBLE_TIME;
+  }
+
+  IndexOff = MaxW / 2 + Start;
+  //
+  // No need to search too far
+  //
+  if (MaxMarginV > SearchLimits) {
+    MaxMarginV = (U8) (SearchLimits);
+  }
+
+  for (Off = Start; Off < Stop + 1; Off++) {
+    Index = Off - Start;
+    //
+    // change margin ParamT
+    //
+    for (Byte = 0; Byte < Outputs->SdramCount; Byte++) {
+      Status = ChangeMargin (MrcData, ParamT, Off, 0, 0, Channel, localR[Channel], Byte, 0, 1, 0, MrcRegFileStart);
+    }
+    ResultTypeV = GetMarginResultType (ParamV); // rxv=0 rxt=1
+    //
+    // Assign to last pass margin results by reference
+    // get lowest margin from all ch/rankS/byte save in FirstRank
+    //
+    Status = GetMarginByte (
+              MrcData,
+              Outputs->MarginResult,
+              ParamV,
+              FirstRank,
+              Ranks
+              );
+    for (Rep = 0; Rep < Repeats; Rep++) {
+      //
+      // Run Margin Test - margin_1d with chosen param
+      // run on all ranks but change param only for firstRank??
+      //
+      Mode = 0;
+      Status = MrcGetBERMarginByte (
+                MrcData,
+                Outputs->MarginResult,
+                ChBitMask,
+                FirstRank,
+                FirstRank,
+                ParamV,
+                Mode,
+                BMap,
+                1,
+                MaxMarginV,
+                0,
+                BERStats
+                );
+      //
+      // Record Results
+      //
+      for (Edge = 0; Edge < MAX_EDGES; Edge++) {
+        for (Byte = 0; Byte < Outputs->SdramCount; Byte++) {
+          if ((Index > 62) || (Index < 0)) {
+            MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Error: SaveMargin array out of bounds! %d", Index);
+            return;
+          }
+
+          if (Rep == 0) {
+            SaveMargin[Index][Channel][Byte][Edge] = 0;
+          }
+
+          SaveMargin[Index][Channel][Byte][Edge] += (U16) (*MarginByte)[ResultTypeV][FirstRank][Channel][Byte][Edge];
+        }
+      }
+    }
+
+    for (Edge = 0; Edge < MAX_EDGES; Edge++) {
+      MinEdge = 0xFFFF;
+      for (Byte = 0; Byte < Outputs->SdramCount; Byte++) {
+        if ((Index > 62) || (Index < 0)) {
+          MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Error: SaveMargin array out of bounds! %d", Index);
+          return;
+        }
+
+        SaveMargin[Index][Channel][Byte][Edge] /= Repeats;
+        if (MinEdge > SaveMargin[Index][Channel][Byte][Edge]) {
+          MinEdge = SaveMargin[Index][Channel][Byte][Edge];
+        }
+      }
+
+      if (((Index + IndexOff) > 62) ||
+          ((Index + IndexOff) < 0) ||
+          ((MaxH / 2 - (MinEdge - 1) / 10) > 107) ||
+          ((MaxH / 2 - (MinEdge - 1) / 10) < 0) ||
+          ((MaxH / 2 + (MinEdge - 1) / 10) > 107) ||
+          ((MaxH / 2 + (MinEdge - 1) / 10) < 0)
+          ) {
+        MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Error: Eye or Lines array out of bounds!\n");
+        return;
+      }
+
+      if (Edge) {
+        Eye[Index + IndexOff][MaxH / 2 - (MinEdge - 1) / 10]  = 1;
+        Lines[MaxH / 2 - (MinEdge - 1) / 10]                  = 1;
+      } else {
+        Eye[Index + IndexOff][MaxH / 2 + (MinEdge - 1) / 10]  = 1;
+        Lines[MaxH / 2 + (MinEdge - 1) / 10]                  = 1;
+      }
+    }
+  }//end of offset
+  //
+  // Print the box
+  //
+  MRC_DEBUG_MSG (
+    Debug,
+    MSG_LEVEL_NOTE,
+    "Plot Eye across ParamT = %s ParamV = %s settings:(Start=%d,Stop=%d) LC = %d  Channel = %d Ranks = 0x%x\n",
+    MarginTypesString[ParamT],
+    MarginTypesString[ParamV],
+    Start,
+    Stop,
+    LoopCount,
+    Channel,
+    Ranks
+    );
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\t------------------------------- +++++++++++++++++++++++++++++++\n");
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\t332222222222111111111100000000000000000001111111111222222222233\n");
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Vref\t109876543210987654321098765432101234567890123456789012345678901\n");
+  for (i = 0; i < MaxH; i++) {
+    if (Lines[i]) {
+      //
+      // print only fail lines
+      //
+      MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%3d:\t", MaxH / 2 - i); // per ch
+      for (j = 0; j < MaxW; j++) {
+        if (Eye[j][i]) {
+          MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%s", "#"); // per ch
+        } else {
+          MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%s", ((j == (MaxW) / 2) || (i == (MaxH) / 2)) ? "+" : " "); // per ch
+        }
+      }
+      MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\n");//per ch
+    }
+  }
+  //
+  // Clean up after test
+  //
+  ChannelOut = &ControllerOut->Channel[Channel];
+  MrcOemMemorySetDword (&ChannelOut->DataOffsetTrain[0], 0, Outputs->SdramCount);
+  Status = ChangeMargin (MrcData, ParamT, 0, 0, 1, 0, 0, 0, 0, 0, 0, MrcRegFileCurrent);
+
+}
+
+/**
+  This function fill the input array (e.g array[ch][rank]) with the power calculation
+  per rank/ch for current sys. setting.
+
+  @param[in]     MrcData   - MRC data struct;
+  @param[in,out] PwrChRank - Array to fill;
+
+  @retval Nothing
+**/
+void
+CalcSysPower (
+  IN     MrcParameters *const MrcData,
+  IN OUT MrcPower             PwrChRank[MAX_CHANNEL][MAX_RANK_IN_CHANNEL]
+  )
+{
+  const MrcDebug              *Debug;
+  MrcChannelOut               *ChannelOut;
+  MrcOutput                   *Outputs;
+  MrcOdtPowerSaving           *OdtPowerSaving;
+  U8                          Rank;
+  U8                          Byte;
+  U8                          Channel;
+  BOOL                        is1DPC;
+  BOOL                        ChCalcDone;
+  U16                         ROdtCpu;
+  U8                          RonDimm;
+  U16                         RonCpu;
+  U16                         Rodtdram;
+  U16                         Wodtdram;
+  U16                         RxBiasPwr;
+  U8                          TotalRankCount;
+  U32                         PwrAvgRd;
+  U32                         PwrAvgWr;
+  const U8                    RttNomDic[6] = {0,60,120,40,20,30}; //accordingly to DDR3 spec
+  const U8                    RttWrDic[3]  = {0,60,120};          //accordingly to DDR3 spec
+  DDR3_MODE_REGISTER_1_STRUCT Ddr3ModeRegister1;
+  DDR3_MODE_REGISTER_2_STRUCT Ddr3ModeRegister2;
+#ifdef ULT_FLAG
+  U16                         LpddrMr3; //dimm DS
+  U16                         LpddrMr11; //dimm ODT
+  const U8                    LpddrRonDic[4] = {0,34,40,48};
+  const U8                    LpddrOdtDic[4] = {0,0,120,240};
+#endif // ULT_FLAG
+
+  Outputs         = &MrcData->SysOut.Outputs;
+  OdtPowerSaving  = &Outputs->OdtPowerSavingData;
+  Debug           = &MrcData->SysIn.Inputs.Debug;
+  RxBiasPwr       = 0;
+  TotalRankCount  = 0;
+  PwrAvgRd        = 0;
+  PwrAvgWr        = 0;
+  for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+    ChCalcDone  = 0;
+    RonCpu      = 0;
+    ROdtCpu     = 0;
+    RxBiasPwr   = 0;
+    for (Rank = 0; Rank < MAX_RANK_IN_CHANNEL; Rank++) {
+      ChannelOut  = &Outputs->Controller[0].Channel[Channel];
+      is1DPC      = (ChannelOut->DimmCount == 1);
+      if (MrcRankInChannelExist (MrcData, Rank, Channel)) {
+#ifdef ULT_FLAG
+        if (MrcData->SysOut.Outputs.DdrType == MRC_DDR_TYPE_LPDDR3) {
+          if (Rank >= MAX_RANK_IN_DIMM) {
+            MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Error: ChannelOut array out of bounds!\n");
+            return ;
+          }
+
+          LpddrMr3  = ChannelOut->Dimm[0].Rank[Rank].MR[mrMR3];
+          LpddrMr11 = ChannelOut->Dimm[0].Rank[Rank].MR11;
+          RonDimm   = LpddrRonDic[0x3 & LpddrMr3];
+          Wodtdram  = LpddrOdtDic[0x3 & LpddrMr11];
+          Rodtdram  = 0x3FFF; // put 8k ohm as infinity - in lpddr there is no nomOdt
+        } else
+#endif // ULT_FLAG
+        {
+          Ddr3ModeRegister1.Data  = ChannelOut->Dimm[Rank / 2].Rank[Rank % 2].MR[mrMR1];
+          Ddr3ModeRegister2.Data  = ChannelOut->Dimm[Rank / 2].Rank[Rank % 2].MR[mrMR2];
+          RonDimm                 = 240 / (6 + (U8) Ddr3ModeRegister1.Bits.ODImpedanceLow);
+          Rodtdram = RttNomDic[(Ddr3ModeRegister1.Bits.OdtRttValueHigh << 2) |
+                               (Ddr3ModeRegister1.Bits.OdtRttValueMid << 1) |
+                                Ddr3ModeRegister1.Bits.OdtRttValueLow];
+          Wodtdram = RttWrDic[Ddr3ModeRegister2.Bits.DynamicOdt];
+        }
+        if (!ChCalcDone){
+           //
+           //Ron CPU - take average all bytes only per ch
+           //
+           for (Byte = 0; Byte < Outputs->SdramCount; Byte++){
+             RonCpu    += (U16) CalcOptPower (MrcData, Channel, 0, Byte, OptWrDS, 0, 0, 1);//read from host
+             ROdtCpu   += (U16) CalcOptPower (MrcData, Channel, 0, Byte, OptRdOdt, 0, 0, 1);//read from host
+             RxBiasPwr += (U16) CalcOptPower (MrcData, Channel, 0, Byte, OptRxBias, 0, 0, 1);//read from host
+           }
+           RonCpu    /= (U16) Outputs->SdramCount;
+           ROdtCpu   /= (U16) Outputs->SdramCount;
+           RxBiasPwr /= (U16) Outputs->SdramCount;
+           ChCalcDone = 1;
+        }
+
+        if (is1DPC) {
+          //
+          // in 1DPC channel always use only one of the terminations
+          //
+          if (Wodtdram == 0) {
+            Wodtdram  = Rodtdram;
+            Rodtdram  = 0x3FFF; // put 8k ohm as infinity
+          } else {
+            Rodtdram  = 0x3FFF; // put 8k ohm as infinity
+          }
+        }
+
+        if (Rodtdram == 0) {
+          Rodtdram = 0x3FFF;
+        }
+
+        if (Wodtdram == 0) {
+          Wodtdram = Rodtdram; // in 2DPC where RttW=0
+        }
+
+        CalcPower (MrcData, &PwrChRank[Channel][Rank], RonCpu, RonDimm, ROdtCpu, Rodtdram, Wodtdram);
+        //
+        // add RxBias to CPU and Total
+        //
+        PwrChRank[Channel][Rank].CpuPower += RxBiasPwr;
+        PwrChRank[Channel][Rank].TotPwr   += RxBiasPwr;
+        PwrAvgRd += PwrChRank[Channel][Rank].CpuPwrRd + PwrChRank[Channel][Rank].DimmPwrRd +
+                    PwrChRank[Channel][Rank].ACPowerRd;
+        PwrAvgWr += PwrChRank[Channel][Rank].CpuPwrWr + PwrChRank[Channel][Rank].DimmPwrWrT +
+                    PwrChRank[Channel][Rank].DimmPwrWrNT + PwrChRank[Channel][Rank].ACPowerWr;
+        TotalRankCount++;
+      }
+    }
+  }
+
+  if (TotalRankCount == 0) {
+    TotalRankCount = 1;  // Prevent divide by 0
+  }
+
+  PwrAvgRd /= TotalRankCount;
+  PwrAvgRd += RxBiasPwr;
+  PwrAvgWr /= TotalRankCount;
+  //
+  // update Mrc struct with Base line numbers
+  //
+  if (OdtPowerSaving->BaseFlag == FALSE) {
+    OdtPowerSaving->BaseSavingRd  = (U16) PwrAvgRd;
+    OdtPowerSaving->BaseSavingWr  = (U16) PwrAvgWr;
+    OdtPowerSaving->BaseSavingCmd = 0; // currently no power train for CMD
+  } else {
+    OdtPowerSaving->MrcSavingRd  = (U16) PwrAvgRd;
+    OdtPowerSaving->MrcSavingWr  = (U16) PwrAvgWr;
+    OdtPowerSaving->MrcSavingCmd = 0; // currently no power train for CMD
+  }
+
+  return;
+}
+
+/**
+  This function optimize the digital offsets by reducing the digital
+  offset and apply the difference to the global one.
+
+  @param[in] MrcData    - Include all MRC global data.
+  @param[in] Param      - Parameter defining the desired digital compensation offset.
+  @param[in] UpdateHost - Decides if MrcData is to be updated.
+
+  @retval The new comp value.
+**/
+U32
+OptimizeCompOffset (
+  IN MrcParameters *const MrcData,
+  IN const U8             Param,
+  IN const U8             UpdateHost
+  )
+{
+  const MrcDebug                            *Debug;
+  MrcOutput                                 *Outputs;
+  MrcControllerOut                          *ControllerOut;
+  MrcChannelOut                             *ChannelOut;
+  DDRCOMP_CR_DDRCRDATACOMP0_STRUCT          DdrCrDataComp0;
+  DDRCOMP_CR_DDRCRDATACOMP1_STRUCT          DdrCrDataComp1;
+  DDRCOMP_CR_DDRCRCOMPCTL0_STRUCT           DdrCrCompCtl0;
+  DDRCOMP_CR_DDRCRCOMPCTL1_STRUCT           DdrCrCompCtl1;
+  DDRDATA0CH0_CR_DDRCRDATAOFFSETCOMP_STRUCT DdrCrDataOffsetComp;
+  U8                                        GlobalParam;
+  U8                                        CurrCompVref;
+  S8                                        NewCompVref;
+  U8                                        CurrentComp;
+  U8                                        NewComp;
+  S8                                        Sign;
+  U8                                        Done;
+  S16                                       AvgOffset;
+  U8                                        Offset;
+  U8                                        StartDelta;
+  U8                                        CurrDelta;
+  U8                                        MinDelta;
+  U8                                        Off;
+  U8                                        BestVrefOff;
+  U8                                        SignBit;
+  U8                                        Byte;
+  U8                                        Channel;
+  U8                                        NumCh;
+  U8                                        ReservedCodes;
+  S8                                        MaxCompVref;
+  S8                                        MinCompVref;
+  U8                                        DqSCompPC;
+  U8                                        CurrDqSCompPC;
+  U8                                        CompCodes[MAX_CHANNEL][MAX_SDRAM_IN_DIMM];
+
+  Outputs                   = &MrcData->SysOut.Outputs;
+  ControllerOut             = &Outputs->Controller[0];
+  Debug                     = &MrcData->SysIn.Inputs.Debug;
+  DdrCrCompCtl0.Data        = Outputs->CompCtl0;
+  DdrCrCompCtl1.Data        = Outputs->CompCtl1;
+
+  DdrCrDataOffsetComp.Data  = 0;
+  ReservedCodes             = 3;
+  NewComp                   = 0;
+  Offset                    = 0;
+  SignBit                   = 0;
+  DqSCompPC                 = 0;
+  CurrDqSCompPC             = 0;
+
+  switch (Param) {
+  case OptWrDS:
+    DdrCrDataComp0.Data = MrcReadCR (MrcData, DDRCOMP_CR_DDRCRDATACOMP0_REG);
+    CurrentComp         = (U8) DdrCrDataComp0.Bits.RcompDrvUp;
+    CurrCompVref        = MrcSE ((U8) DdrCrCompCtl0.Bits.DqDrvVref, 4, 8);
+    MaxCompVref         = (1 << (DDRCOMP_CR_DDRCRCOMPCTL0_DqDrvVref_WID - 1)) - 1;
+    MinCompVref         = (-1) * 1 << (DDRCOMP_CR_DDRCRCOMPCTL0_DqDrvVref_WID - 1);
+    GlobalParam         = WrDS;
+    break;
+
+  case OptRdOdt:
+    DdrCrDataComp1.Data = MrcReadCR (MrcData, DDRCOMP_CR_DDRCRDATACOMP1_REG);
+    CurrentComp         = (U8) DdrCrDataComp1.Bits.RcompOdtUp;
+    CurrCompVref        = MrcSE ((U8) DdrCrCompCtl0.Bits.DqOdtVref, 5, 8);
+    MaxCompVref         = (1 << (DDRCOMP_CR_DDRCRCOMPCTL0_DqOdtVref_WID - 1)) - 1;
+    MinCompVref         = (-1) * 1 << (DDRCOMP_CR_DDRCRCOMPCTL0_DqOdtVref_WID - 1);
+    GlobalParam         = RdOdt;
+    break;
+
+  case OptSComp:
+    DdrCrDataComp0.Data = MrcReadCR (MrcData, DDRCOMP_CR_DDRCRDATACOMP0_REG);
+    CurrentComp         = (U8) DdrCrDataComp0.Bits.SlewRateComp;
+    CurrDqSCompPC       = (U8) DdrCrCompCtl1.Bits.DqScompPC;
+    CurrCompVref        = (U8) DdrCrCompCtl1.Bits.DqScompCells;
+    MaxCompVref         = (1 << (DDRCOMP_CR_DDRCRCOMPCTL1_DqScompCells_WID)) - 1;
+    MinCompVref         = 4;
+    GlobalParam         = SCompDq;
+    break;
+
+  default:
+    CurrentComp   = 0;
+    CurrCompVref  = 0;
+    MaxCompVref   = 0;
+    MinCompVref   = 0;
+    GlobalParam   = 0;
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_ERROR, "Invalid Param : %d", Param);
+    break;
+  }
+
+  AvgOffset = 0;
+  NumCh     = 0;
+  for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+    if ((MrcChannelExist (Outputs, Channel))) {
+      ChannelOut = &MrcData->SysOut.Outputs.Controller[0].Channel[Channel];
+      for (Byte = 0; Byte < Outputs->SdramCount; Byte++) {
+        DdrCrDataOffsetComp.Data = ChannelOut->DataCompOffset[Byte];
+        if (Param == OptWrDS) {
+          Offset  = (U8) DdrCrDataOffsetComp.Bits.DqDrvUpCompOffset;
+          SignBit = 6;
+        }
+
+        if (Param == OptRdOdt) {
+          Offset  = (U8) DdrCrDataOffsetComp.Bits.DqOdtUpCompOffset;
+          SignBit = 5;
+        }
+
+        if (Param == OptSComp) {
+          Offset  = (U8) DdrCrDataOffsetComp.Bits.DqSlewRateCompOffset;
+          SignBit = 5;
+        }
+
+        AvgOffset += (S8) MrcSE (Offset, SignBit, 8);
+        CompCodes[Channel][Byte] = CurrentComp + MrcSE (Offset, SignBit, 8);
+      }
+
+      NumCh++;
+    }
+  }
+
+  Sign = (AvgOffset < 0) ? -1 : 1;
+  //
+  // Calculate the average offset and round to the nearest integer.
+  //
+  AvgOffset = (AvgOffset + Sign * NumCh * ((U8) Outputs->SdramCount) / 2) / (NumCh * ((U8) Outputs->SdramCount));
+
+  if (AvgOffset == 0) {
+    return CurrentComp;
+  }
+  //
+  // Find the CompVref minimum of the delta between (CurrentComp + AvgOffset) to NewComp.
+  // Take care of keeping 3 code reserved.
+  // Exit if no vref range left.
+  //
+  Done        = 0;
+  Off         = 1;
+  BestVrefOff = CurrCompVref;
+  NewComp     = CurrentComp;
+  DqSCompPC   = CurrDqSCompPC;
+  StartDelta  = ABS ((S8) AvgOffset);
+  MinDelta    = StartDelta;
+  if (Param == OptSComp) {
+    Sign *= -1;
+  }
+
+  while (!Done) {
+    NewCompVref = CurrCompVref + (Sign * Off);
+    if ((MinCompVref > NewCompVref) || (NewCompVref > MaxCompVref)) {
+      Done = 1;
+    }
+    //
+    // Reserve 3 comp codes
+    //
+    if ((ReservedCodes > NewComp) || (NewComp > (63 - ReservedCodes))) {
+      Done = 1;
+    }
+
+    if (Param == OptSComp) {
+      if ((NewCompVref + 1) > 16) {
+        DqSCompPC = 0;
+      }
+
+      NewCompVref = (DqSCompPC << 4) + NewCompVref;
+    }
+
+    if (!Done) {
+      NewComp   = (U8) UpdateCompGlobalOffset (MrcData, GlobalParam, NewCompVref, 0);
+      CurrDelta = ABS (CurrentComp + (S8) AvgOffset - NewComp);
+      if (CurrDelta < StartDelta) {
+        if (CurrDelta < MinDelta) {
+          MinDelta    = CurrDelta;
+          BestVrefOff = NewCompVref;
+          if (MinDelta == 0) {
+            Done = 1;
+          }
+        }
+      } else {
+        Done = 1;
+      }
+    }
+
+    Off++;
+  }
+  //
+  // update new compVref setting
+  //
+  if (BestVrefOff != CurrCompVref) {
+    NewComp = (U8) UpdateCompGlobalOffset (MrcData, GlobalParam, BestVrefOff, UpdateHost);
+    //
+    // Update all bytes with new offset: Offset + code - newcode = +newoffset
+    //
+    for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+      ChannelOut = &MrcData->SysOut.Outputs.Controller[0].Channel[Channel];
+      if ((MrcChannelExist (Outputs, Channel))) {
+        for (Byte = 0; Byte < Outputs->SdramCount; Byte++) {
+          UpdateOptParamOffset (MrcData, Channel, 0, Byte, Param, CompCodes[Channel][Byte] - NewComp, UpdateHost);
+        }
+      }
+    }
+  } else {
+    //
+    // Restore CompVref
+    //
+    if (Param == OptSComp) {
+      NewCompVref = (CurrDqSCompPC << 4) + CurrCompVref;
+    }
+
+    NewComp = (U8) UpdateCompGlobalOffset (MrcData, GlobalParam, CurrCompVref, UpdateHost);
+  }
+
+  return NewComp;
+}
+
+/**
+  This step performs Comp Offset optimization on the param list defined in this function.
+
+  @param[in] MrcData - Include all MRC global data.
+
+  @retval MrcStatus - mrcSuccess
+**/
+MrcStatus
+MrcOptimizeComp (
+  IN MrcParameters *const MrcData
+  )
+{
+  const U8  ParamList[] = { OptWrDS, OptRdOdt, OptSComp };
+  U8        Param;
+
+  for (Param = 0; Param < sizeof (ParamList); Param++) {
+    OptimizeCompOffset (MrcData, ParamList[Param], 1);
+  }
+
+  return mrcSuccess;
+}
+
+/**
+  This function calculates the percent of power saving from the power optimization steps and
+  updates the proper registers in the PCU.  To get the correct base line for this calculation,
+  this routing needs to run first time early in the training in order to update the MrcStruct
+  with the base line.  After the power training steps, it will run again to get the actual
+  percent of power saving.
+
+  @param[in] MrcData - Include all MRC global data.
+
+  @retval MrcStatus - mrcSuccess
+
+**/
+MrcStatus
+MrcPowerSavingMeter (
+  IN MrcParameters *const MrcData
+  )
+{
+  MrcDebug const                          *Debug;
+  MrcPower                                PwrChRank[MAX_CHANNEL][MAX_RANK_IN_CHANNEL];
+  MrcOdtPowerSaving                       *OdtPowerSaving;
+  U8                                      PercentRd;
+  U8                                      PercentWr;
+  U8                                      PercentCmd;
+  PCU_CR_MRC_ODT_POWER_SAVING_PCU_STRUCT  CrMrcOdtPowerSavingPcu;
+
+  Debug           = &MrcData->SysIn.Inputs.Debug;
+  OdtPowerSaving  = &MrcData->SysOut.Outputs.OdtPowerSavingData;
+  CalcSysPower (MrcData, PwrChRank);
+  MRC_DEBUG_MSG (
+    Debug,
+    MSG_LEVEL_NOTE,
+    "\tBaseLine\tMrcSaving\nAvgRd\t%d\t\t%d\nAvgWr\t%d\t\t%d\n",
+    OdtPowerSaving->BaseSavingRd,
+    OdtPowerSaving->MrcSavingRd,
+    OdtPowerSaving->BaseSavingWr,
+    OdtPowerSaving->MrcSavingWr
+    );
+
+  if (OdtPowerSaving->BaseFlag) {
+    //
+    // Calculate power saving and update PCU regs
+    //
+    if (OdtPowerSaving->BaseSavingRd > OdtPowerSaving->MrcSavingRd) {
+      PercentRd = (U8) (((U32) (OdtPowerSaving->BaseSavingRd - OdtPowerSaving->MrcSavingRd) * 256) / OdtPowerSaving->BaseSavingRd);
+    } else {
+      PercentRd = 0;
+    }
+
+    if (OdtPowerSaving->BaseSavingWr > OdtPowerSaving->MrcSavingWr) {
+      PercentWr = (U8) (((U32) (OdtPowerSaving->BaseSavingWr - OdtPowerSaving->MrcSavingWr) * 256) / OdtPowerSaving->BaseSavingWr);
+    } else {
+      PercentWr = 0;
+    }
+
+    if (OdtPowerSaving->BaseSavingCmd > OdtPowerSaving->MrcSavingCmd) {
+      PercentCmd = (U8) (((U32) (OdtPowerSaving->BaseSavingCmd - OdtPowerSaving->MrcSavingCmd) * 256) / OdtPowerSaving->BaseSavingCmd);
+    } else {
+      PercentCmd = 0;
+    }
+
+    CrMrcOdtPowerSavingPcu.Bits.MRC_Saving_Rd   = PercentRd;
+    CrMrcOdtPowerSavingPcu.Bits.MRC_Saving_Wt   = PercentWr;
+    CrMrcOdtPowerSavingPcu.Bits.MRC_Saving_Cmd  = PercentCmd;
+
+    MrcWriteCR (MrcData, PCU_CR_MRC_ODT_POWER_SAVING_PCU_REG, CrMrcOdtPowerSavingPcu.Data);
+  } else {
+    OdtPowerSaving->BaseFlag = TRUE;
+  }
+
+  return mrcSuccess;
+}
diff --git a/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Services/MrcDdr3.c b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Services/MrcDdr3.c
new file mode 100644
index 0000000..654a332
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Services/MrcDdr3.c
@@ -0,0 +1,1572 @@
+/** @file
+  This file includes all the DDR3 specific characteristic functions.
+
+@copyright
+  Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement.
+
+**/
+
+//
+// Include files
+//
+#include "MrcDdr3.h"
+
+#ifdef ULT_FLAG
+///
+/// Only 1DPC is supported on HSW-ULT
+///
+const TOdtValue MbUltOdtTable[MAX_DIMMS_IN_CHANNEL][2] = {
+/// 1DPC 1R,  1DPC 2R
+  {{120,0},  {120,0}},
+};
+
+const TOdtValue User1UltOdtTable[MAX_DIMMS_IN_CHANNEL][2] = {
+/// 1DPC 1R,  1DPC 2R
+  {{120,0},  {120,0}},
+};
+
+#endif //ULT_FLAG
+
+#ifdef TRAD_FLAG
+const TOdtValue MbTradOdtTable[MAX_DIMMS_IN_CHANNEL][oiNotValid] = {
+/// 1DPC 1R,  1DPC 2R,  2DPC 1R 1R,  2DPC 1R 2R,  2DPC 2R 1R,  2DPC 2R 2R
+  {{00,40},  {00,40},  {60,30},    {60,30},    {60,30},    {60,30}},
+  {{00,40},  {00,40},  {60,30},    {60,30},    {60,30},    {60,30}}
+};
+
+const TOdtValue DtTradOdtTable[MAX_DIMMS_IN_CHANNEL][oiNotValid] = {
+/// 1DPC 1R,  1DPC 2R,  2DPC 1R 1R,  2DPC 1R 2R,  2DPC 2R 1R,  2DPC 2R 2R
+  {{60,00},  {60,00},  {60,30},    {60,30},    {60,30},    {60,30}},
+  {{60,00},  {60,00},  {60,30},    {60,30},    {60,30},    {60,30}}
+};
+
+const TOdtValue User1TradOdtTable[MAX_DIMMS_IN_CHANNEL][oiNotValid] = {
+/// 1DPC 1R,  1DPC 2R,  2DPC 1R 1R,  2DPC 1R 2R,  2DPC 2R 1R,  2DPC 2R 2R
+  {{60,60},  {60,60},  {60,30},    {60,30},    {60,30},    {60,30}},
+  {{60,60},  {60,60},  {60,30},    {60,30},    {60,30},    {60,30}}
+};
+
+const TOdtValue User2TradOdtTable[MAX_DIMMS_IN_CHANNEL][oiNotValid] = {
+/// 1DPC 1R,  1DPC 2R,  2DPC 1R 1R,  2DPC 1R 2R,  2DPC 2R 1R,  2DPC 2R 2R
+  {{60,60},  {60,60},  {60,40},    {60,40},    {60,40},    {60,40}},
+  {{60,60},  {60,60},  {60,40},    {60,40},    {60,40},    {60,40}}
+};
+#endif // TRAD_FLAG
+
+//
+// Module external functions
+//
+/**
+@brief
+  this function reverses MA and BA bits for Rank1
+
+  @param[in] BA              - MRS command to be sent
+  @param[in] MA              - Value to be sent
+
+  @retval Proper MA and BA BITS.
+**/
+U32
+MrcMirror (
+  IN U8              BA,
+  IN U16             MA
+  )
+{
+  U16 ma357;
+  U16 ma468;
+
+  //
+  // UDIMM/SODIMM reverses the following bits on Rank1
+  // A3 - 4, A5 - 6, A7 - 8
+  // BA0 - 1
+  //
+  ma357 = 0xA8 & MA;
+  ma468 = 0x150 & MA;
+  MA    = (0xFE07 & MA) | (ma357 << 1) | (ma468 >> 1);
+  BA    = (0x4 & BA) | ((0x2 & BA) >> 1) | ((0x1 & BA) << 1);
+
+  return (BA << 24) + MA;
+}
+
+/**
+@brief
+  this function writes to CADB
+
+  @param[in] MrcData         - include all the MRC data
+  @param[in] Channel         - Channel to send command to
+  @param[in] RankMask        - Rank mask for which command will be sent to.
+  @param[in] CMD             - 0: MRS, 1: REF, 2: PRE, 3: ACT, 4: WR, 5: RD, 6: ZQ, 7: NOP
+  @param[in] BA              - MRS command to be sent
+  @param[in] MA              - Value to be sent
+  @param[in] Delay           - Delay in Dclocks
+
+  @retval MrcStatus
+**/
+MrcStatus
+MrcWriteCADBCmd (
+  IN MrcParameters *const MrcData,
+  IN const U8             Channel,
+  IN const U8             RankMask,
+  IN const U8             CMD,
+  IN const U8             BA,
+  IN const U16 *const     MA,
+  IN const U8             Delay
+  )
+{
+  const MrcInput                              *Inputs;
+  MrcOutput                                   *Outputs;
+  MrcChannelOut                               *ChannelOut;
+  MrcStatus                                   Status;
+  U32                                         Offset;
+  U8                                          Stop;
+  U8                                          Dimm;
+  U8                                          Rank;
+  U8                                          AddressMirrored; // bitMask
+  MCHBAR_CH0_CR_REUT_CH_PAT_CADB_PROG_STRUCT  ReutChPatCadbProg;
+  MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MRS_STRUCT   ReutChPatCadbMrs;
+  MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_STRUCT   ReutChSeqCfg;
+  MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_STRUCT   ReutChSeqCfgSave;
+  MCDFXS_CR_REUT_CH_SEQ_CTL_MCMAIN_0_STRUCT   ReutChSeqCtl;
+  MCDFXS_CR_REUT_GLOBAL_ERR_MCMAIN_STRUCT     ReutGlobalErr;
+  MrcDebug                                    *Debug;
+
+  Debug           = &MrcData->SysIn.Inputs.Debug;
+  Inputs          = &MrcData->SysIn.Inputs;
+  Outputs         = &MrcData->SysOut.Outputs;
+  ChannelOut      = &Outputs->Controller[0].Channel[Channel];
+  Status          = mrcSuccess;
+  Stop            = 0;
+  AddressMirrored = 0;
+
+  //
+  // Clear DDR qualifier during reset sequence
+  //
+  MrcWriteCR8 (MrcData, MCSCHEDS_CR_DFT_MISC_REG + 1, 0);
+
+  //
+  // Check for AddressMirrored on each DIMM present
+  //
+  for (Dimm = 0; Dimm < MAX_DIMMS_IN_CHANNEL; Dimm++) {
+    if (ChannelOut->Dimm[Dimm].AddressMirrored == TRUE) {
+      AddressMirrored |= (MRC_BIT0 << Dimm);
+    }
+  }
+  //
+  // Pointer will be dynamically incremented after a write to CADB_PROG register
+  //
+  Offset = MCHBAR_CH0_CR_REUT_CH_PAT_CADB_WRITE_POINTER_REG +
+    ((MCHBAR_CH1_CR_REUT_CH_PAT_CADB_WRITE_POINTER_REG - MCHBAR_CH0_CR_REUT_CH_PAT_CADB_WRITE_POINTER_REG) * Channel);
+  MrcWriteCR8 (MrcData, Offset, 0);
+
+  for (Rank = 0; Rank < MAX_RANK_IN_CHANNEL; Rank++) {
+    if (MrcRankInChannelExist (MrcData, Rank, Channel) & RankMask) {
+
+      ReutChPatCadbProg.Data                   = 0;
+      ReutChPatCadbProg.Bits.CADB_Data_Bank    = BA;
+      ReutChPatCadbProg.Bits.CADB_Data_Address = MA[RANK_TO_DIMM_NUMBER (Rank)];
+
+      //
+      // Check if Rank 1 and if DIMM requires AddressMirrored
+      //
+      if ((Rank % 2) && (AddressMirrored & ((Rank / 2) + 1))) {
+        //
+        // Remainder is 1 only for Rank1 of each DIMM
+        //
+        ReutChPatCadbProg.Data = MrcMirror (BA, MA[RANK_TO_DIMM_NUMBER (Rank)]);
+      }
+
+      ReutChPatCadbProg.Bits.CADB_Data_CKE     = 0xF;
+      ReutChPatCadbProg.Bits.CADB_Data_Control = CMD;
+      ReutChPatCadbProg.Bits.CADB_Data_CS      = ~(MRC_BIT0 << Rank);
+
+      Offset = MCHBAR_CH0_CR_REUT_CH_PAT_CADB_PROG_REG +
+        ((MCHBAR_CH1_CR_REUT_CH_PAT_CADB_PROG_REG - MCHBAR_CH0_CR_REUT_CH_PAT_CADB_PROG_REG) * Channel);
+      MrcWriteCR64 (MrcData, Offset, ReutChPatCadbProg.Data);
+
+      //MRC_DEBUG_MSG (Debug, MSG_LEVEL_ERROR, "CH%d Rank %d ReutChPatCadbProg: 0x%08X%08X\n", Channel, Rank, ReutChPatCadbProg.Data32[1], ReutChPatCadbProg.Data32[0]);
+
+      Stop += 1;
+    }
+  }
+
+  if (Stop == 0) {
+    MRC_DEBUG_MSG (
+      Debug,
+      MSG_LEVEL_ERROR,
+      "MrcWriteCADBCmd: Channel %d Ranks %d ValidRankBitMask 0x%X\n",
+      Channel,
+      RankMask,
+      ChannelOut->ValidRankBitMask
+      );
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_ERROR, "MrcWriteCADBCmd: Not a valid Rank in RankBitMask\n");
+    Status = mrcFail;
+    return Status;
+  }
+  //
+  // Execute MRS Mode
+  //
+  Offset = MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MRS_REG +
+    ((MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MRS_REG - MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MRS_REG) * Channel);
+  ReutChPatCadbMrs.Data                      = 0;
+  ReutChPatCadbMrs.Bits.MRS_Gap              = (Delay == 0) ? 3 : Delay;
+  ReutChPatCadbMrs.Bits.CADB_MRS_End_Pointer = Stop - 1;
+  MrcWriteCR (MrcData, Offset, ReutChPatCadbMrs.Data);
+
+  //
+  // Save before MR command
+  //
+  Offset = MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_REG +
+    ((MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_REG - MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_REG) * Channel);
+  ReutChSeqCfgSave.Data = MrcReadCR (MrcData, Offset);
+
+  //
+  // Prepare for MRS command
+  //
+  ReutChSeqCfg.Data                     = ReutChSeqCfgSave.Data;
+  ReutChSeqCfg.Bits.Global_Control      = 0;
+  ReutChSeqCfg.Bits.Initialization_Mode = MRS_Mode;
+  MrcWriteCR (MrcData, Offset, (U32) ReutChSeqCfg.Data); // Set MRS Mode w/o Global control
+
+  //
+  // Start test and clear errors
+  //
+  Offset = MCDFXS_CR_REUT_CH_SEQ_CTL_MCMAIN_0_REG +
+    ((MCDFXS_CR_REUT_CH_SEQ_CTL_MCMAIN_1_REG - MCDFXS_CR_REUT_CH_SEQ_CTL_MCMAIN_0_REG) * Channel);
+  ReutChSeqCtl.Data                    = 0;
+  ReutChSeqCtl.Bits.Local_Clear_Errors = 1;
+  ReutChSeqCtl.Bits.Local_Start_Test   = 1;
+  MrcWriteCR8 (MrcData, Offset, (U8) ReutChSeqCtl.Data);
+
+  //
+  // Wait for Channel_Test_Done_Status for the channel.
+  //
+  // @todo: Infinite loop possible, need timer.
+  //
+  do {
+    ReutGlobalErr.Data = MrcReadCR (MrcData, MCDFXS_CR_REUT_GLOBAL_ERR_MCMAIN_REG);
+    if (1 == ((Channel == 0) ? ReutGlobalErr.Bits.Channel_Error_Status_0 : ReutGlobalErr.Bits.Channel_Error_Status_1)) {
+      MRC_DEBUG_MSG (Debug, MSG_LEVEL_ERROR, "ERROR IN MrcWriteCADBCmd: REUT_GLOBAL_ERR 0x%X\n", ReutGlobalErr.Data);
+      return mrcFail;
+    }
+  } while (0 == ((Channel == 0) ? ReutGlobalErr.Bits.Channel_Test_Done_Status_0 : ReutGlobalErr.Bits.Channel_Test_Done_Status_1));
+
+  //
+  // Restore after MR command
+  //
+  Offset = MCDFXS_CR_REUT_CH_SEQ_CTL_MCMAIN_0_REG +
+    ((MCDFXS_CR_REUT_CH_SEQ_CTL_MCMAIN_1_REG - MCDFXS_CR_REUT_CH_SEQ_CTL_MCMAIN_0_REG) * Channel);
+  ReutChSeqCtl.Data                    = 0;
+  ReutChSeqCtl.Bits.Local_Clear_Errors = 1;
+  MrcWriteCR8 (MrcData, Offset, (U8) ReutChSeqCtl.Data);
+
+  Offset = MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_REG +
+    ((MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_REG - MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_REG) * Channel);
+  MrcWriteCR (MrcData, Offset, (U32) ReutChSeqCfgSave.Data);
+  return Status;
+}
+
+/**
+@brief
+  This function sends the proper MRS command for specific ranks as indicated by RankMask
+
+  @param[in] MrcData         - include all the MRC data
+  @param[in] Channel         - Channel to send command to
+  @param[in] RankMask        - Rank mask for which command will be sent to
+  @param[in] MR              - MRS command to be sent
+  @param[in] DimmValue       - Dimm Values to be sent
+
+  @retval MrcStatus
+**/
+MrcStatus
+MrcWriteMRSAll (
+  IN MrcParameters *const MrcData,
+  IN const U8             Channel,
+  IN const U8             RankMask,
+  IN const U8             MR,
+  IN const U16 *const     DimmValue
+  )
+{
+  //
+  // CMD = [0: MRS, 1: REF, 2: PRE, 3: ACT, 4: WR, 5: RD, 6: ZQ, 7: NOP]
+  //
+  return MrcWriteCADBCmd (MrcData, Channel, RankMask, MRS_CMD, MR, DimmValue, 0);
+}
+
+/**
+@brief
+  This function sends the proper MRS command for specific ranks as indicated by RankMask
+
+  @param[in] MrcData         - Include all the MRC data
+  @param[in] Channel         - Channel to send command to
+  @param[in] RankMask        - Rank mask for which command will be sent to
+  @param[in] MR              - MRS command to be sent
+  @param[in] Value           - Value to be sent
+
+  @retval MrcStatus
+**/
+MrcStatus
+MrcWriteMRS (
+  IN MrcParameters  *const MrcData,
+  IN const U8              Channel,
+  IN const U8              RankMask,
+  IN const U8              MR,
+  IN const U16             Value
+  )
+{
+  MrcStatus Status;
+  U16       DimmValue[MAX_DIMMS_IN_CHANNEL];
+
+  //
+  // Update proper Dimm Values based on Ranks (rank bit mask)
+  //
+  if (RankMask <= 3) {
+    //
+    // For DIMM 0
+    //
+    DimmValue[0] = Value;
+#if MAX_DIMMS_IN_CHANNEL > 1
+    DimmValue[1] = 0;
+#endif
+  } else {
+    //
+    // DIMM 1
+    //
+    DimmValue[0] = 0;
+#if MAX_DIMMS_IN_CHANNEL > 1
+    DimmValue[1] = Value;
+#endif
+  }
+  //
+  // CMD = [0: MRS, 1: REF, 2: PRE, 3: ACT, 4: WR, 5: RD, 6: ZQ, 7: NOP]
+  //
+  Status = MrcWriteCADBCmd (MrcData, Channel, RankMask, MRS_CMD, MR, DimmValue, 0);
+
+  return Status;
+}
+
+/**
+@brief
+  Issue ZQ calibration command on all ranks.
+  When done, wait appropriate delay depending on the ZQ type.
+
+  @param[in] MrcData         - include all the MRC data
+  @param[in] chBitMask       - Channel bit mask to be sent to.
+  @param[in] ZqType          - Type of ZQ Calibration: see MrcZqType enum
+
+  @retval MrcStatus - mrcSuccess if passes, otherwise an error status
+**/
+MrcStatus
+MrcIssueZQ (
+  IN MrcParameters *const MrcData,
+  IN const U8             chBitMask,
+  IN const MrcZqType      ZqType
+  )
+{
+  MrcOutput *Outputs;
+  MrcStatus Status;
+  MrcDebug  *Debug;
+  U8        Channel;
+  U8        Dimm;
+  U8        Delay;
+  U16       MaValue;
+  U16       DimmValue[MAX_DIMMS_IN_CHANNEL];
+  U32       OpCode;
+#ifdef MRC_DEBUG_PRINT
+  char      *StrZqType;
+#endif // MRC_DEBUG_PRINT
+#ifdef ULT_FLAG
+  U8        Rank;
+  BOOL      Lpddr;
+#endif // ULT_FLAG
+  Debug   = &MrcData->SysIn.Inputs.Debug;
+  Outputs = &MrcData->SysOut.Outputs;
+  Status  = mrcSuccess;
+  Delay   = 1;
+
+#ifdef ULT_FLAG
+  //
+  // Check if LPDDR3 memory is used
+  //
+  Lpddr = (Outputs->DdrType == MRC_DDR_TYPE_LPDDR3);
+#endif //ULT_FLAG
+  MaValue = 0;
+
+  switch (ZqType) {
+    case MRC_ZQ_INIT:
+#ifdef MRC_DEBUG_PRINT
+      StrZqType = "INIT";
+#endif
+      MaValue = MRC_BIT10;
+      OpCode  = 0xFF;
+      break;
+
+    case MRC_ZQ_LONG:
+#ifdef MRC_DEBUG_PRINT
+      StrZqType = "LONG";
+#endif
+      MaValue = MRC_BIT10;
+      OpCode  = 0xAB;
+      break;
+
+    case MRC_ZQ_SHORT:
+#ifdef MRC_DEBUG_PRINT
+      StrZqType = "SHORT";
+#endif
+      OpCode  = 0x56;
+      break;
+
+    case MRC_ZQ_RESET:
+#ifdef MRC_DEBUG_PRINT
+      StrZqType = "RESET";
+#endif
+      OpCode  = 0xC3;
+      break;
+
+    default:
+      MRC_DEBUG_MSG (Debug, MSG_LEVEL_ERROR, "Wrong ZQ type: %d\n", ZqType);
+      return mrcWrongInputParameter;
+  }
+
+  //
+  // Program MA value for all DIMMs
+  //
+  for (Dimm = 0; Dimm < (sizeof (DimmValue) / sizeof (DimmValue[0])); Dimm++) {
+    DimmValue[Dimm] = MaValue;
+  }
+
+  for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+    if (MrcChannelExist (Outputs, Channel)) {
+      if ((MRC_BIT0 << Channel) & chBitMask) {
+        if (!(MRC_BIT0 << (Channel + 1) & chBitMask) && (ZqType == MRC_ZQ_SHORT)) {
+          Delay = 7;
+        }
+        //
+        // Issue ZQ calibration command on all ranks of this channel
+        //
+#ifdef ULT_FLAG
+        if (Lpddr) {
+          for (Rank = 0; Rank < MAX_RANK_IN_CHANNEL; Rank++) {
+            if (MrcRankInChannelExist (MrcData, Rank, Channel)) {
+              //
+              // MR10, ZQ calibration
+              //
+              if (!Outputs->LpddrJedecInitDone) {
+                MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "LPDDR: Issue ZQ %s on ch %d rank %d\n", StrZqType, Channel, Rank);
+              }
+              Status = MrcIssueMrw (MrcData, Channel, Rank, 10, OpCode, FALSE, FALSE);
+            }
+          }
+        } else
+#endif // ULT_FLAG
+        {
+          //
+          //          MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "DDR3: Issue ZQ %s on ch %d\n", StrZqType, Channel);
+          //
+          Status = MrcWriteCADBCmd (MrcData, Channel, 0x0F, ZQ_CMD, 0, DimmValue, Delay);
+        }
+      }
+    }
+  }
+
+  if ((ZqType == MRC_ZQ_INIT) || (ZqType == MRC_ZQ_LONG)) {
+    MrcWait (MrcData, 1 * HPET_1US);
+  }
+
+  return Status;
+}
+
+/**
+@brief
+  This function writes the MR2 register for all the ranks and channels
+
+  @param[in, out] MrcData    - general data
+  @param[in]      Pasr       - Partial array self refresh bit A0-A2
+
+  @retval MrcStatus - mrcSuccess if passes, otherwise an error status
+**/
+MrcStatus
+MrcSetMR2 (
+  IN OUT MrcParameters *const MrcData,
+  IN     const U8             Pasr
+  )
+{
+  const MrcInput    *Inputs;
+  const MrcDebug    *Debug;
+  MrcOutput         *Outputs;
+  MrcControllerOut  *ControllerOut;
+  MrcChannelOut     *ChannelOut;
+  TOdtValue         *OdtTableIndex;
+  MrcProfile        Profile;
+  U8                Channel;
+  U8                Rank;
+  U8                RankMod2;
+  U8                AutoSelfRefresh;
+  U8                SelfRefreshTemp;
+  U16               DimmValue[MAX_DIMMS_IN_CHANNEL];
+  MrcStatus         Status;
+  DDR3_MODE_REGISTER_2_STRUCT Ddr3ModeRegister;
+
+  Inputs        = &MrcData->SysIn.Inputs;
+  Outputs       = &MrcData->SysOut.Outputs;
+  ControllerOut = &Outputs->Controller[0];
+  Debug         = &Inputs->Debug;
+  Status        = mrcSuccess;
+  Profile       = Inputs->MemoryProfile;
+
+  for (Channel = 0; (Channel < MAX_CHANNEL) && (Status == mrcSuccess); Channel++) {
+    if (MrcChannelExist (Outputs, Channel)) {
+      ChannelOut                            = &ControllerOut->Channel[Channel];
+      Ddr3ModeRegister.Data                 = 0;
+      Ddr3ModeRegister.Bits.PartialArraySR  = Pasr;
+      //
+      // Subtract 5 because of jedec mr2 CWL table 0 = 5 1=6 2=7 ...
+      //
+      Ddr3ModeRegister.Bits.CasWriteLatency = ChannelOut->Timing[Profile].tCWL - 5;
+
+      for (Rank = 0; Rank < MAX_RANK_IN_CHANNEL; Rank += MAX_RANK_IN_DIMM) {
+        //
+        // loop only for each DIMM
+        //
+        if (MrcRankInChannelExist (MrcData, Rank, Channel)) {
+          if (Outputs->RestoreMRs) {
+            RankMod2              = Rank % 2;
+            Ddr3ModeRegister.Data = ChannelOut->Dimm[RANK_TO_DIMM_NUMBER (Rank)].Rank[RankMod2].MR[mrMR2];
+          } else {
+            //
+            // ASR: Set if both bits 0 and 2 of byte 31 in SPD are set.
+            //
+            // @todo: Need to check and see if we need to set DDR3_MODE_REGISTER_2_STR_OFF based on EXTENDED_TEMP support
+            //           If ASR need BIT6 set, else if EXTENDED_TEMP set BIT7.
+            //           Need to understand the policy here or should we follow NHM's approach for LFD/CFD.
+            //
+            if (
+                (ChannelOut->Dimm[RANK_TO_DIMM_NUMBER (Rank)].AutoSelfRefresh == TRUE) &&
+                ((Inputs->RefreshRate2x == FALSE) || (Outputs->AutoSelfRefresh == TRUE))
+               ) {
+              AutoSelfRefresh = 1;
+              SelfRefreshTemp = 0;
+            } else if (ChannelOut->Dimm[RANK_TO_DIMM_NUMBER (Rank)].SelfRefreshTemp == TRUE) {
+              AutoSelfRefresh = 0;
+              SelfRefreshTemp = 1;
+            } else {
+              AutoSelfRefresh = 0;
+              SelfRefreshTemp = 0;
+            }
+
+            Ddr3ModeRegister.Bits.AutoSelfRefresh = AutoSelfRefresh;
+            Ddr3ModeRegister.Bits.SelfRefreshTemp = SelfRefreshTemp;
+
+            OdtTableIndex = GetOdtTableIndex (MrcData, Channel, RANK_TO_DIMM_NUMBER (Rank));
+            if (OdtTableIndex == NULL) {
+              return mrcFail;
+            }
+
+            Ddr3ModeRegister = UpdateRttWrValue (MrcData, OdtTableIndex->RttWr, Ddr3ModeRegister);
+
+            //
+            // *** must be before the MRC command because of address swizzling bits in SODIMM/UDIMM
+            //
+            SetTcMr2ShadowReg (MrcData, Channel, RANK_TO_DIMM_NUMBER (Rank), Ddr3ModeRegister.Data);
+
+            //
+            // save MR2 for later validation usage
+            //
+            RankMod2 = Rank % 2;
+            ChannelOut->Dimm[RANK_TO_DIMM_NUMBER (Rank)].Rank[RankMod2].MR[mrMR2]     = Ddr3ModeRegister.Data;
+            ChannelOut->Dimm[RANK_TO_DIMM_NUMBER (Rank)].Rank[RankMod2 + 1].MR[mrMR2] = Ddr3ModeRegister.Data;
+            //
+            // MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE,  "MrcSetMR2  Channel %u Dimm %u Rank %u = 0x%X\n",
+            //                Channel, RANK_TO_DIMM_NUMBER (Rank), Rank, Ddr3ModeRegister.Data);
+            //
+          }
+          //
+          // Update proper DIMM value
+          //
+          DimmValue[RANK_TO_DIMM_NUMBER (Rank)] = Ddr3ModeRegister.Data;
+        }
+      }
+      //
+      // 3rd parameter is really a rank mask of which ranks to send command to.
+      // If need it for all possible and present ranks, it should be 0xF.
+      //
+      Status = MrcWriteMRSAll (MrcData, Channel, 0x0F, mrMR2, DimmValue);
+    }
+  }
+
+  return Status;
+}
+
+/**
+@brief
+  This function writes the MR3 register for all the ranks and channels
+
+  @param[in] MrcData         - include all the MRC data
+  @param[in] MPRLoc          - MPR Location bit A0-A1
+  @param[in] Mpr             - MPR bit A2
+
+  @retval MrcStatus - mrcSuccess if passes, otherwise an error status
+**/
+MrcStatus
+MrcSetMR3 (
+  IN MrcParameters *const MrcData,
+  IN const U8             MPRLoc,
+  IN const U8             Mpr
+  )
+{
+  const MrcInput              *Inputs;
+  const MrcDebug              *Debug;
+  MrcOutput                   *Outputs;
+  U16                         DimmValue[MAX_DIMMS_IN_CHANNEL];
+  U8                          Channel;
+  U8                          Dimm;
+  MrcStatus                   Status;
+  DDR3_MODE_REGISTER_3_STRUCT Ddr3ModeRegister;
+
+  Inputs  = &MrcData->SysIn.Inputs;
+  Outputs = &MrcData->SysOut.Outputs;
+  Debug   = &Inputs->Debug;
+  Status  = mrcSuccess;
+
+  //
+  // Independent channel data
+  //
+  Ddr3ModeRegister.Data              = 0;
+  Ddr3ModeRegister.Bits.MprLocation  = MPRLoc;
+  Ddr3ModeRegister.Bits.MprOperation = Mpr;
+
+  for (Channel = 0; (Channel < MAX_CHANNEL) && (Status == mrcSuccess); Channel++) {
+    if (MrcChannelExist (Outputs, Channel)) {
+      for (Dimm = 0; Dimm < (sizeof (DimmValue) / sizeof (DimmValue[0])); Dimm++) {
+        DimmValue[Dimm] = Ddr3ModeRegister.Data;
+      }
+      //
+      // 3rd parameter is really a rank mask of which ranks to send command to.
+      // If need it for all possible and present ranks, it should be 0xF.
+      //
+      Status = MrcWriteMRSAll (MrcData, Channel, 0x0F, mrMR3, DimmValue);
+    }
+  }
+
+  return Status;
+}
+
+/**
+@brief
+  This function writes the MR1 register for all the ranks and channels
+
+  @param[in, out] MrcData         - include all the MRC data
+  @param[in]      DLLEnable       - DLL enable bit A0
+  @param[in]      Odic            - Output driver impedance control A5, A1
+  @param[in]      AdditiveLatency - Additive latency bit A3-A4
+  @param[in]      WlEnable        - Write leveling enable bit A7
+  @param[in]      Tdqs            - TDQS enable bit A11
+  @param[in]      Qoff            - Qoff bit A12
+
+  @retval MrcStatus - mrcSuccess if passes, otherwise an error status
+**/
+MrcStatus
+MrcSetMR1 (
+  IN OUT MrcParameters *const MrcData,
+  IN     const U8             DLLEnable,
+  IN     const U8             Odic,
+  IN     const U8             AdditiveLatency,
+  IN     const U8             WlEnable,
+  IN     const U8             Tdqs,
+  IN     const U8             Qoff
+  )
+{
+  const MrcInput              *Inputs;
+  const MrcDebug              *Debug;
+  MrcOutput                   *Outputs;
+  MrcControllerOut            *ControllerOut;
+  MrcChannelOut               *ChannelOut;
+  TOdtValue                   *OdtTableIndex;
+  U16                         DimmValue[MAX_DIMMS_IN_CHANNEL];
+  U8                          Channel;
+  U8                          Rank;
+  U8                          RankMod2;
+  U8                          RttNom;
+  MrcStatus                   Status;
+  DDR3_MODE_REGISTER_1_STRUCT Ddr3ModeRegister;
+
+  Inputs        = &MrcData->SysIn.Inputs;
+  Outputs       = &MrcData->SysOut.Outputs;
+  ControllerOut = &Outputs->Controller[0];
+  Debug         = &Inputs->Debug;
+  Status        = mrcSuccess;
+  OdtTableIndex = NULL;
+
+  for (Channel = 0; (Channel < MAX_CHANNEL) && (Status == mrcSuccess); Channel++) {
+    if (MrcChannelExist (Outputs, Channel)) {
+
+      ChannelOut = &ControllerOut->Channel[Channel];
+      //
+      // independent channel data
+      //
+      Ddr3ModeRegister.Data                 = 0;
+      Ddr3ModeRegister.Bits.DllEnable       = DLLEnable;
+      Ddr3ModeRegister.Bits.ODImpedanceLow  = Odic & 1;
+      Ddr3ModeRegister.Bits.ODImpedanceHigh = (Odic & 2) >> 1;
+      Ddr3ModeRegister.Bits.AdditiveLatency = AdditiveLatency;
+      Ddr3ModeRegister.Bits.WriteLeveling   = WlEnable;
+      Ddr3ModeRegister.Bits.Tdqs            = Tdqs; // @todo: We used to set Tdqs if the DIMM is X8.
+      Ddr3ModeRegister.Bits.Qoff            = Qoff;
+
+      for (Rank = 0; Rank < MAX_RANK_IN_CHANNEL; Rank += 2) {
+        //
+        // loop only for each DIMM
+        //
+        if (MrcRankInChannelExist (MrcData, Rank, Channel)) {
+          if (Outputs->RestoreMRs) {
+            RankMod2              = Rank % 2;
+            Ddr3ModeRegister.Data = ChannelOut->Dimm[RANK_TO_DIMM_NUMBER (Rank)].Rank[RankMod2].MR[mrMR1];
+          } else {
+            //
+            // Get the ODT table index.
+            //
+            OdtTableIndex = GetOdtTableIndex (MrcData, Channel, RANK_TO_DIMM_NUMBER (Rank));
+            if (OdtTableIndex == NULL) {
+              MRC_DEBUG_MSG (Debug, MSG_LEVEL_ERROR, "ERROR: Un support board type\n");
+              return mrcFail;
+            }
+            //
+            // Set the RttNom value
+            //
+#ifdef ULT_FLAG
+            if (Inputs->CpuModel == cmHSW_ULT && Outputs->DdrType == MRC_DDR_TYPE_DDR3) {
+              RttNom = 0;   // ODT disabled on DDR3 ULT
+            } else
+#endif // ULT_FLAG
+            {
+              RttNom = OdtTableIndex->RttNom;
+            }
+
+            Ddr3ModeRegister = UpdateRttNomValue (MrcData, RttNom, Ddr3ModeRegister);
+
+            //
+            // save MR1 for later validation usage
+            //
+            RankMod2 = Rank % 2;
+            ChannelOut->Dimm[RANK_TO_DIMM_NUMBER (Rank)].Rank[RankMod2].MR[mrMR1]     = Ddr3ModeRegister.Data;
+            ChannelOut->Dimm[RANK_TO_DIMM_NUMBER (Rank)].Rank[RankMod2 + 1].MR[mrMR1] = Ddr3ModeRegister.Data;
+            //
+            // MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "MrcSetMR1  Channel %u Dimm %u Rank %u = 0x%X\n",
+            //                Channel, RANK_TO_DIMM_NUMBER (Rank), Rank, Ddr3ModeRegister.Data);
+            //
+          }
+          //
+          // Update proper DIMM value
+          //
+          DimmValue[RANK_TO_DIMM_NUMBER (Rank)] = Ddr3ModeRegister.Data;
+        }
+      }
+      //
+      // 3rd parameter is really a rank mask of which ranks to send command to.
+      // If need it for all possible and present ranks, it should be 0xF.
+      //
+      Status = MrcWriteMRSAll (MrcData, Channel, 0x0F, mrMR1, DimmValue);
+    }
+  }
+
+  return Status;
+}
+
+/**
+@brief
+  This function writes the MR0 register for all the ranks
+
+  @param[in, out] MrcData         - include all the MRC data
+  @param[in]      CommandControl  - include the command control params
+  @param[in]      BurstLength     - Burst length bit A0-A1
+  @param[in]      ReadBurstType   - Read burst type bit A3
+  @param[in]      TestMode        - Test mode type bit A7
+  @param[in]      DllReset        - DLL reset bit A8
+
+  @retval MrcStatus - mrcSuccess if passes, otherwise an error status
+**/
+MrcStatus
+MrcSetMR0 (
+  IN OUT MrcParameters *const MrcData,
+  IN     const U8             BurstLength,
+  IN     const U8             ReadBurstType,
+  IN     const U8             TestMode,
+  IN     const U8             DllReset
+  )
+{
+  /*
+  CAS Latency
+  A6 A5 A4 A2 CAS Latency
+  0  0  0  0  Reserved
+  0  0  1  0  5
+  0  1  0  0  6
+  0  1  1  0  7
+  1  0  0  0  8
+  1  0  1  0  9
+  1  1  0  0  10
+  1  1  1  0  11(Optional for DDR3-1600)
+  CAS = (CAS - 4) <<1
+
+  Write recovery
+  A11 A10 A9 WR(cycles)
+  0   0   0  16*2
+  0   0   1   5*2
+  0   1   0   6*2
+  0   1   1   7*2
+  1   0   0   8*2
+  1   0   1   10*2
+  1   1   0   12*2
+  1   1   1   14*2
+  Wr = Wr - 5
+*/
+  const U8                    WrTable[] = {1, 2, 3, 4, 0, 5, 0, 6, 0, 7, 0, 0};
+  const MrcInput              *Inputs;
+  const MrcDebug              *Debug;
+  MrcOutput                   *Outputs;
+  MrcControllerOut            *ControllerOut;
+  MrcChannelOut               *ChannelOut;
+  MrcProfile                  Profile;
+  U16                         DimmValue[MAX_DIMMS_IN_CHANNEL];
+  U16                         Cas;
+  U16                         Wr;
+  U16                         Offset;
+  U16                         Cl_A2;
+  U8                          Channel;
+  U8                          Rank;
+  U8                          RankMod2;
+  MrcStatus                   Status;
+  DDR3_MODE_REGISTER_0_STRUCT Ddr3ModeRegister;
+
+  Inputs        = &MrcData->SysIn.Inputs;
+  Outputs       = &MrcData->SysOut.Outputs;
+  ControllerOut = &Outputs->Controller[0];
+  Debug         = &Inputs->Debug;
+  Status        = mrcSuccess;
+  Profile       = Inputs->MemoryProfile;
+
+  //
+  // independent channel data
+  //
+  Ddr3ModeRegister.Data               = 0;
+  Ddr3ModeRegister.Bits.BurstLength   = BurstLength;
+  Ddr3ModeRegister.Bits.ReadBurstType = ReadBurstType;
+  Ddr3ModeRegister.Bits.TestMode      = TestMode;
+  Ddr3ModeRegister.Bits.DllReset      = DllReset;
+
+  for (Channel = 0; (Channel < MAX_CHANNEL) && (Status == mrcSuccess); Channel++) {
+    if (MrcChannelExist (Outputs, Channel)) {
+
+      ChannelOut  = &ControllerOut->Channel[Channel];
+
+      Cas         = ChannelOut->Timing[Profile].tCL;
+      Wr          = ChannelOut->Timing[Profile].tWR;
+
+      //
+      // find the new cas value from the CAS table
+      //
+      if (Cas < 5 || Cas > 16) {
+        MRC_DEBUG_MSG (Debug, MSG_LEVEL_ERROR, "ERROR: CAS value %d is not valid \n", Cas);
+        Status = mrcCasError;
+      }
+
+      if ((Wr < 5) || (Wr > 8 && Wr != 10 && Wr != 12 && Wr != 14 && Wr != 16)) {
+        MRC_DEBUG_MSG (Debug, MSG_LEVEL_ERROR, "ERROR: Write recovery Wr value %d is not valid \n", Wr);
+        return mrcWrError;
+      }
+      //
+      // convert CAS to jedec ddr3 values
+      //
+      if (Cas <= 11) {
+        Offset  = 4;
+        Cl_A2   = 0;
+      } else {
+        Offset  = 12;
+        Cl_A2   = 1;
+      }
+
+      Ddr3ModeRegister.Bits.CasLatencyLow   = Cl_A2;
+      Ddr3ModeRegister.Bits.CasLatencyHigh  = Cas - Offset;
+
+      //
+      // convert Wr to jedec ddr3 values
+      //
+      Ddr3ModeRegister.Bits.WriteRecovery = WrTable[Wr - 5];
+
+      //
+      // calculate the Ppd
+      // DLL control for PPD: slow (0) for mobile, fast (1) for desktop, open for external input
+      // Note - PM_PDWN_CONFIG_C# should be aligned with this. For slow exit use DLL_off. Otherwise use all others.
+      //
+      Ddr3ModeRegister.Bits.PrechargePdDll =
+        (
+          Inputs->PowerDownMode == pdmNoPowerDown ||
+          Inputs->PowerDownMode == pdmAPD
+        ) ? 1 : 0;
+      if ((Inputs->PowerDownMode != pdmNoPowerDown && Inputs->PowerDownMode != pdmAPD) &&
+          (Inputs->PowerDownMode != pdmPPDDLLOFF)
+          ) {
+        Ddr3ModeRegister.Bits.PrechargePdDll = 0;
+      }
+      for (Rank = 0; Rank < MAX_RANK_IN_CHANNEL; Rank += 2) {
+        //
+        // loop only for each DIMM
+        //
+        if (MrcRankInChannelExist (MrcData, Rank, Channel)) {
+          if (Outputs->RestoreMRs) {
+            RankMod2              = Rank % 2;
+            Ddr3ModeRegister.Data = ChannelOut->Dimm[RANK_TO_DIMM_NUMBER (Rank)].Rank[RankMod2].MR[mrMR0];
+          } else {
+            //
+            // save MR0 for later validation usage
+            //
+            RankMod2  = Rank % 2;
+            ChannelOut->Dimm[RANK_TO_DIMM_NUMBER (Rank)].Rank[RankMod2].MR[mrMR0]     = Ddr3ModeRegister.Data;
+            ChannelOut->Dimm[RANK_TO_DIMM_NUMBER (Rank)].Rank[RankMod2 + 1].MR[mrMR0] = Ddr3ModeRegister.Data;
+            //
+            // MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE,  "MrcSetMR0  Channel %u Dimm %u Rank %u = 0x%X\n",
+            //               Channel, RANK_TO_DIMM_NUMBER (Rank), Rank, Ddr3ModeRegister.Data);
+            //
+          }
+          //
+          // Update proper DIMM value
+          //
+          DimmValue[RANK_TO_DIMM_NUMBER (Rank)] = Ddr3ModeRegister.Data;
+        }
+      }
+      //
+      // 3rd parameter is really a rank mask of which ranks to send command to.
+      // If need it for all possible and present ranks, it should be 0xF.
+      //
+      Status = MrcWriteMRSAll (MrcData, Channel, 0x0F, mrMR0, DimmValue);
+    }
+  }
+
+  return Status;
+}
+
+/**
+@brief
+  This function return tWLO time. this time is Write leveling output delay.
+
+  @param[in] Frequency       - MC frequency.
+
+  @retval tWLO timein nCK.
+**/
+U32
+GetTwloTime (
+  IN const MrcFrequency  Frequency
+  )
+{
+  U32 tWLO;
+
+  switch (Frequency) {
+    case f2133:
+    case f1867:
+      tWLO = 8;
+      break;
+
+    case f1600:
+    case f1333:
+      tWLO = 6;
+      break;
+
+    case f1067:
+      tWLO = 5;
+      break;
+
+    case f800:
+      tWLO = 4;
+      break;
+
+    default:
+      tWLO = 0;
+  }
+
+  return tWLO;
+}
+
+/**
+@brief
+  This funtion returns the odt table index for the given Dimm/Channel.
+
+  @param[in] MrcData         - Include all the mrc global data.
+  @param[in] Channel         - Channel to work on.
+  @param[in] Dimm            - Rank to work on.
+
+  @retval OdtValue - iThe pointer to the relevant Odt values.
+**/
+TOdtValue *
+GetOdtTableIndex (
+  IN MrcParameters *const MrcData,
+  IN const U8             Channel,
+  IN const U8             Dimm
+  )
+{
+  MrcDebug      *Debug;
+  MrcChannelOut *ChannelOut;
+  MrcDimmOut    *DimmOut;
+  TOdtIndex     OdtIndex;
+
+  Debug       = &MrcData->SysIn.Inputs.Debug;
+  ChannelOut  = &MrcData->SysOut.Outputs.Controller[0].Channel[Channel];
+  DimmOut     = &ChannelOut->Dimm[dDIMM0];
+  OdtIndex    = oiNotValid;
+
+  switch (ChannelOut->DimmCount) {
+#ifdef TRAD_FLAG
+    case 2:
+      //
+      // Two dimms per channel.
+      //
+      if ((DimmOut[dDIMM0].RankInDIMM == 1) && (DimmOut[dDIMM1].RankInDIMM == 1)) {
+        OdtIndex = oi2DPC1R1R;
+      } else if ((DimmOut[dDIMM0].RankInDIMM == 1) && (DimmOut[dDIMM1].RankInDIMM == 2)) {
+        OdtIndex = oi2DPC1R2R;
+      } else if ((DimmOut[dDIMM0].RankInDIMM == 2) && (DimmOut[dDIMM1].RankInDIMM == 1)) {
+        OdtIndex = oi2DPC2R1R;
+      } else if ((DimmOut[dDIMM0].RankInDIMM == 2) && (DimmOut[dDIMM1].RankInDIMM == 2)) {
+        OdtIndex = oi2DPC2R2R;
+      } else {
+        MRC_DEBUG_MSG (Debug, MSG_LEVEL_ERROR, "ERROR: Invalid 2DPC rank mode\n");
+      }
+      break;
+#endif // TRAD_FLAG
+
+    case 1:
+      //
+      // One dimm per channel.
+      //
+      if ((DimmOut[dDIMM0].RankInDIMM == 1) ||
+          ((DimmOut[dDIMM1].RankInDIMM == 1) && (MAX_DIMMS_IN_CHANNEL > 1))
+         ) {
+          OdtIndex = oi1DPC1R;
+      } else if ((DimmOut[dDIMM0].RankInDIMM == 2) ||
+                 ((DimmOut[dDIMM1].RankInDIMM == 2) && (MAX_DIMMS_IN_CHANNEL > 1))
+                ) {
+          OdtIndex = oi1DPC2R;
+      } else {
+        MRC_DEBUG_MSG (Debug, MSG_LEVEL_ERROR, "ERROR: Invalid 1DPC rank mode\n");
+      }
+      break;
+
+    default:
+      break;
+  }
+
+  return (OdtIndex == oiNotValid) ? NULL : SelectTable (MrcData, Dimm, OdtIndex);
+}
+
+/**
+@brief
+  This funtion takes the MR1 register value and updates the odt value
+ inside the register.
+
+  @param[in] MrcData          - Include all the MRC general data.
+  @param[in] OdtValue         - Selected odt index.
+  @param[in] Ddr3ModeRegister - Register to update.
+
+  @retval Ddr3ModeRegister  - Updated register
+**/
+DDR3_MODE_REGISTER_1_STRUCT
+UpdateRttNomValue (
+  IN MrcParameters *const        MrcData,
+  IN const U8                    OdtValue,
+  IN DDR3_MODE_REGISTER_1_STRUCT Ddr3ModeRegister
+  )
+{
+  const MrcDebug  *Debug;
+  U8              A2Value;
+  U8              A6Value;
+  U8              A9Value;
+
+  Debug = &MrcData->SysIn.Inputs.Debug;
+  if (OdtValue == 0) {
+    //
+    // rtt_nom is disable
+    //
+    A2Value = 0;
+    A6Value = 0;
+    A9Value = 0;
+  } else if (OdtValue == 60) {
+    //
+    // RZQ/4
+    //
+    A2Value = 1;
+    A6Value = 0;
+    A9Value = 0;
+  } else if (OdtValue == 120) {
+    //
+    // RZQ/2
+    //
+    A2Value = 0;
+    A6Value = 1;
+    A9Value = 0;
+  } else if (OdtValue == 40) {
+    //
+    // RZQ/6
+    //
+    A2Value = 1;
+    A6Value = 1;
+    A9Value = 0;
+  } else if (OdtValue == 20) {
+    //
+    // RZQ/12
+    //
+    A2Value = 0;
+    A6Value = 0;
+    A9Value = 1;
+  } else if (OdtValue == 30) {
+    //
+    // RZQ/8
+    //
+    A2Value = 1;
+    A6Value = 0;
+    A9Value = 1;
+  } else {
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_ERROR, "ERROR: unsupported odt RttNom value\n");
+    A2Value = 1;
+    A6Value = 1;
+    A9Value = 1;
+  }
+
+  Ddr3ModeRegister.Bits.OdtRttValueLow  = A2Value;
+  Ddr3ModeRegister.Bits.OdtRttValueMid  = A6Value;
+  Ddr3ModeRegister.Bits.OdtRttValueHigh = A9Value;
+  return Ddr3ModeRegister;
+}
+
+/**
+@brief
+  This function updates the Rtt value in the MR2 value passed in.
+
+  @param[in] MrcData          - Include all the MRC general data.
+  @param[in] OdtValue         - Selected odt index.
+  @param[in] Ddr3ModeRegister - Register to update.
+
+  @retval Ddr3ModeRegister - Updated MR2 register
+**/
+DDR3_MODE_REGISTER_2_STRUCT
+UpdateRttWrValue (
+  MrcParameters *const        MrcData,
+  const U8                    OdtValue,
+  DDR3_MODE_REGISTER_2_STRUCT Ddr3ModeRegister
+  )
+{
+  U8  RttValue;
+
+  if ((OdtValue > 120) || ((OdtValue % 60) != 0)) {
+    MRC_DEBUG_MSG (
+      &MrcData->SysIn.Inputs.Debug,
+      MSG_LEVEL_ERROR,
+      "ERROR: unsupported odt RttWr value of %u\n",
+      OdtValue
+      );
+    RttValue = 0;
+  } else {
+    RttValue = OdtValue / 60;
+  }
+
+  Ddr3ModeRegister.Bits.DynamicOdt = RttValue;
+  return Ddr3ModeRegister;
+}
+
+/**
+@brief
+  this funtion select the ODT table according OEM/USER decision.
+  In the MRC have 4 table type Mb,Dt,User1,User2.
+  User1,User2 use as internal usage.
+
+  @param[in] MrcData         - Include all the MRC general data.
+  @param[in] Dimm            - selected DIMM.
+  @param[in] OdtIndex        - selected odt index.
+
+  @retval TOdtValue * - Pointer to the relevant table.
+                        The return value is NULL if the table could
+                        not be found
+**/
+TOdtValue *
+SelectTable (
+  IN MrcParameters *const MrcData,
+  IN const U8             Dimm,
+  IN const TOdtIndex      OdtIndex
+  )
+{
+  const MrcInput *Inputs;
+  TOdtValue      *OdtTable;
+  const MrcDebug          *Debug;
+
+  Inputs = &MrcData->SysIn.Inputs;
+  Debug         = &Inputs->Debug;
+  OdtTable = NULL;
+  switch (Inputs->BoardType) {
+  case btCRBMB:
+  case btCRBEMB:
+#ifdef ULT_FLAG
+    if (Inputs->CpuModel == cmHSW_ULT) {
+      if (OdtIndex >= 2) {
+        MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Error: MbUltOdtTable array out of bounds!\n");
+        return NULL;
+      }
+      OdtTable = (TOdtValue *) &MbUltOdtTable[Dimm][OdtIndex];
+    }
+#endif // ULT_FLAG
+#ifdef TRAD_FLAG
+    if ((Inputs->CpuModel == cmHSW) || (Inputs->CpuModel == cmCRW)) {
+      OdtTable = (TOdtValue *) &MbTradOdtTable[Dimm][OdtIndex];
+    }
+#endif //TRAD_FLAG
+    break;
+
+  case btCRBDT:
+#ifdef TRAD_FLAG
+    if ((Inputs->CpuModel == cmHSW) || (Inputs->CpuModel == cmCRW)) {
+      OdtTable = (TOdtValue *) &DtTradOdtTable[Dimm][OdtIndex];
+    }
+#endif //TRAD_FLAG
+    break;
+
+  case btUser1:
+#ifdef ULT_FLAG
+    if (Inputs->CpuModel == cmHSW_ULT) {
+      if (OdtIndex >= 2) {
+        MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Error: User1UltOdtTable array out of bounds!\n");
+        return NULL;
+      }
+      OdtTable = (TOdtValue *) &User1UltOdtTable[Dimm][OdtIndex];
+    }
+#endif // ULT_FLAG
+#ifdef TRAD_FLAG
+    if ((Inputs->CpuModel == cmHSW) || (Inputs->CpuModel == cmCRW)) {
+      OdtTable = (TOdtValue *) &User1TradOdtTable[Dimm][OdtIndex];
+    }
+#endif //TRAD_FLAG
+    break;
+
+  case btUser2:
+#ifdef TRAD_FLAG
+    if ((Inputs->CpuModel == cmHSW) || (Inputs->CpuModel == cmCRW)) {
+      OdtTable = (TOdtValue *) &User2TradOdtTable[Dimm][OdtIndex];
+    }
+#endif //TRAD_FLAG
+    break;
+
+  case btUser4:
+    //
+    // @todo: Need to Port ODT table for Ult
+    //
+#ifdef ULT_FLAG
+    if (Inputs->CpuModel == cmHSW_ULT) {
+      if (OdtIndex >= 2) {
+        MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Error: MbUltOdtTable array out of bounds!\n");
+        return NULL;
+      }
+      OdtTable = (TOdtValue *) &MbUltOdtTable[Dimm][OdtIndex];
+    }
+#endif // ULT_FLAG
+#ifdef TRAD_FLAG
+    if ((Inputs->CpuModel == cmHSW) || (Inputs->CpuModel == cmCRW)) {
+      OdtTable = (TOdtValue *) &MbTradOdtTable[Dimm][OdtIndex];
+    }
+#endif //TRAD_FLAG
+    break;
+
+  default:
+    OdtTable = NULL;
+    break;
+  }
+
+  return OdtTable;
+}
+
+#ifdef ULT_FLAG
+
+/**
+@brief
+  Issue LPDDR MRW (Mode Register Write) command using MRH (Mode Register Handler).
+
+  @param[in] MrcData - Include all MRC global data.
+  @param[in] Channel - the channel to work on
+  @param[in] Rank    - the rank to work on
+  @param[in] Address - MRW address
+  @param[in] Data    - MRW Data
+  @param[in] InitMrw - when TRUE, command is stretched (used before CA training is done)
+  @param[in] ChipSelect2N - when TRUE, use 2N stretch mode for CS (used before CA training is done)
+
+  @retval mrcSuccess    - MRW was sent successfully
+  @retval mrcDeviceBusy - timed out waiting for MRH
+**/
+MrcStatus
+MrcIssueMrw (
+  IN MrcParameters *const MrcData,
+  IN U32                  Channel,
+  IN U32                  Rank,
+  IN U32                  Address,
+  IN U32                  Data,
+  IN BOOL                 InitMrw,
+  IN BOOL                 ChipSelect2N
+  )
+{
+  const MrcDebug                        *Debug;
+  MrcOutput                             *Outputs;
+  U32                                   OffsetMrCommand;
+  U32                                   OffsetCmdRate;
+  MCHBAR_CH0_CR_LPDDR_MR_COMMAND_STRUCT MrCommand;
+  MCHBAR_CH0_CR_CMD_RATE_STRUCT         CmdRate;
+  BOOL                                  Busy;
+  U32                                   Timeout;
+
+  Timeout = (U32) MrcGetCpuTime () + 10000;   // 10 seconds timeout
+
+  Debug   = &MrcData->SysIn.Inputs.Debug;
+  Outputs = &MrcData->SysOut.Outputs;
+
+  OffsetMrCommand = MCHBAR_CH0_CR_LPDDR_MR_COMMAND_REG +
+    ((MCHBAR_CH1_CR_LPDDR_MR_COMMAND_REG - MCHBAR_CH0_CR_LPDDR_MR_COMMAND_REG) * Channel);
+
+  //
+  // Make sure MRH is not busy
+  //
+  do {
+    MrCommand.Data = MrcReadCR (MrcData, OffsetMrCommand);
+    Busy           = (MrCommand.Bits.Busy == 1);
+  } while (Busy && ((U32) MrcGetCpuTime () < Timeout));
+  if (Busy) {
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_ERROR, "Timed out waiting for previous MRH command to finish!\n");
+    return mrcDeviceBusy;
+  }
+
+  OffsetCmdRate = MCHBAR_CH0_CR_CMD_RATE_REG + ((MCHBAR_CH1_CR_CMD_RATE_REG - MCHBAR_CH0_CR_CMD_RATE_REG) * Channel);
+  if (ChipSelect2N) {
+    //
+    // Enable 2N stretch mode for CS
+    //
+    CmdRate.Data                = MrcReadCR(MrcData, OffsetCmdRate);
+    CmdRate.Bits.init_mrw_2n_cs = 1;
+    MrcWriteCR (MrcData, OffsetCmdRate, CmdRate.Data);
+  }
+  //
+  // Send the MRW
+  //
+  MrCommand.Bits.Address  = Address;
+  MrCommand.Bits.Data     = Data;
+  MrCommand.Bits.Write    = 1;
+  MrCommand.Bits.Init_MRW = InitMrw;
+  MrCommand.Bits.Rank     = Rank;
+  MrCommand.Bits.Busy     = 1;
+
+  if (!Outputs->LpddrJedecInitDone) {
+    MRC_DEBUG_MSG (
+      Debug, MSG_LEVEL_NOTE,
+      "MrcIssueMrw on ch %d rank %d: MR%d, Opcode=0x%02X, InitMrw=%d, 2N_CS=%d\n",
+      Channel, Rank, Address, Data, InitMrw, ChipSelect2N
+      );
+  }
+  MrcWriteCR (MrcData, OffsetMrCommand, MrCommand.Data);
+
+  //
+  // Wait till MRH is done sending the command
+  //
+  Timeout = (U32) MrcGetCpuTime () + 10000;   // 10 seconds timeout
+  do {
+    MrCommand.Data = MrcReadCR (MrcData, OffsetMrCommand);
+    Busy           = (MrCommand.Bits.Busy == 1);
+  } while (Busy && ((U32) MrcGetCpuTime () < Timeout));
+
+  if (Busy) {
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_ERROR, "Timed out sending MRH command!\n");
+    return mrcDeviceBusy;
+  }
+
+  if (ChipSelect2N) {
+    //
+    // Disable 2N stretch mode for CS
+    //
+    CmdRate.Bits.init_mrw_2n_cs = 0;
+    MrcWriteCR (MrcData, OffsetCmdRate, CmdRate.Data);
+  }
+
+  return mrcSuccess;
+}
+
+/**
+@brief
+  Issue LPDDR MRR (Mode Register Read) command using MRH (Mode Register Handler).
+  Use DQ mapping array to deswizzle the MR data.
+
+  @param[in]  MrcData - Include all MRC global data.
+  @param[in]  Channel - the channel to work on
+  @param[in]  Rank    - the rank to work on
+  @param[in]  Address - MRR address
+  @param[out] Data    - MRR Data array per SDRAM device
+
+  @retval mrcSuccess    - MRR was executed successfully
+  @retval mrcDeviceBusy - timed out waiting for MRH
+**/
+MrcStatus
+MrcIssueMrr (
+  IN MrcParameters *const MrcData,
+  IN U32                  Channel,
+  IN U32                  Rank,
+  IN U32                  Address,
+  OUT U8                  Data[4]
+  )
+{
+  MrcInput          *Inputs;
+  MrcDebug          *Debug;
+  MrcOutput         *Outputs;
+  MrcControllerIn   *ControllerIn;
+  MrcControllerOut  *ControllerOut;
+  MrcChannelIn      *ChannelIn;
+  MrcChannelOut     *ChannelOut;
+  U32               OffsetMrCommand;
+  U32               OffsetMrrResult;
+  BOOL              Busy;
+  U32               CurrCpuBit;
+  U32               CurrCpuByte;
+  U32               CpuByteCnt;
+  U32               DeviceCnt;
+  U32               CurrDramBit;
+  U32               BitVal;
+  MCHBAR_CH0_CR_LPDDR_MR_RESULT_STRUCT  MrResult;
+  MCHBAR_CH0_CR_LPDDR_MR_COMMAND_STRUCT MrCommand;
+  U32               Timeout;
+  Timeout = (U32) MrcGetCpuTime () + 10000;   // 10 seconds timeout
+
+  Inputs        = &MrcData->SysIn.Inputs;
+  Debug         = &Inputs->Debug;
+  Outputs       = &MrcData->SysOut.Outputs;
+  ControllerIn  = &Inputs->Controller[0];
+  ControllerOut = &Outputs->Controller[0];
+  ChannelOut    = &ControllerOut->Channel[Channel];
+  ChannelIn     = &ControllerIn->Channel[Channel];
+  CurrCpuByte   = 0;
+  MrcOemMemorySet (Data, 0, 4 * sizeof (Data[0]));
+
+  OffsetMrCommand = MCHBAR_CH0_CR_LPDDR_MR_COMMAND_REG +
+    ((MCHBAR_CH1_CR_LPDDR_MR_COMMAND_REG - MCHBAR_CH0_CR_LPDDR_MR_COMMAND_REG) * Channel);
+
+  OffsetMrrResult= MCHBAR_CH0_CR_LPDDR_MR_RESULT_REG +
+    ((MCHBAR_CH1_CR_LPDDR_MR_RESULT_REG - MCHBAR_CH0_CR_LPDDR_MR_RESULT_REG) * Channel);
+
+  //
+  // Make sure MRH is not busy
+  //
+  do {
+    MrCommand.Data = MrcReadCR (MrcData, OffsetMrCommand);
+    Busy           = (MrCommand.Bits.Busy == 1);
+  } while (Busy && ((U32) MrcGetCpuTime () < Timeout));
+  if (Busy) {
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_ERROR, "Timed out waiting for previous MRH command to finish!\n");
+    return mrcDeviceBusy;
+  }
+
+  //
+  // Send the MRR
+  //
+  MrCommand.Bits.Address  = Address;
+  MrCommand.Bits.Data     = 0; // Reading from DRAM
+  MrCommand.Bits.Write    = 0; // MRR
+  MrCommand.Bits.Init_MRW = 0; // MRR doesn't support Init_MRW
+  MrCommand.Bits.Rank     = Rank;
+  MrCommand.Bits.Busy     = 1;
+
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "MrcIssueMrr on ch %d rank %d: MR%d\n", Channel, Rank, Address);
+  MrcWriteCR (MrcData, OffsetMrCommand, MrCommand.Data);
+
+  //
+  // Wait till MRH is done sending the command and getting the result
+  //
+  Timeout = (U32) MrcGetCpuTime () + 10000;   // 10 seconds timeout
+  do {
+    MrCommand.Data = MrcReadCR (MrcData, OffsetMrCommand);
+    Busy           = (MrCommand.Bits.Busy == 1);
+  } while (Busy && ((U32) MrcGetCpuTime () < Timeout));
+
+  if (Busy) {
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_ERROR, "Timed out sending MRH command!\n");
+    return mrcDeviceBusy;
+  }
+
+  MrResult.Data = MrcReadCR (MrcData, OffsetMrrResult);
+
+  for (DeviceCnt = 0; DeviceCnt < 4; DeviceCnt++) {
+    if ((ChannelOut->Dimm[dDIMM0].SdramWidth == 32) && (1 == (DeviceCnt & 1))) {
+      //
+      // We only know DQ mapping for the lower 16 bits of the x32 devices
+      // So we'll copy their MRR feedback to the upper bytes' place
+      // Hence, we skip the odd dies for x32
+      //
+      Data[DeviceCnt] = Data[DeviceCnt - 1];
+      continue;
+    }
+
+    //
+    // Find which CPU byte is mapped to the relevant DRAM byte
+    //
+    for (CpuByteCnt = 0; CpuByteCnt < Outputs->SdramCount; CpuByteCnt++) {
+      if ((DeviceCnt * 2) == ChannelIn->DqsMapCpu2Dram[CpuByteCnt]) {
+        CurrCpuByte = CpuByteCnt;
+        break;
+      }
+    }
+
+    for (CurrCpuBit = 0; CurrCpuBit < MAX_BITS; CurrCpuBit++) {
+      //
+      // The actual DRAM bit that is connected to the current CPU DQ pin
+      //
+      CurrDramBit = ChannelIn->DqMapCpu2Dram[CurrCpuByte][CurrCpuBit] - 8 * (DeviceCnt * 2); // Subtract 8xDramByte
+
+      BitVal = (MrResult.Data8[DeviceCnt] >> CurrCpuBit) & 1; // The 0/1 value that came from the DRAM bit
+      Data[DeviceCnt] |= (BitVal << CurrDramBit);             // Putting the value in the correct place
+    }
+  }  // for DeviceCnt
+
+  return mrcSuccess;
+}
+
+/**
+@brief
+  Issue LPDDR PRECHARGE ALL command using CADB.
+
+  @param[in]  MrcData   - Include all MRC global data.
+  @param[in]  Channel   - The channel to work on
+  @param[in]  RankMask  - The rank(s) to work on
+
+  @retval none
+**/
+void
+MrcIssuePrechargeAll (
+  IN MrcParameters *const MrcData,
+  IN const U8             Channel,
+  IN const U8             RankMask
+  )
+{
+  U32 CaHigh;
+  U32 CaLow;
+  U32 CMD;
+  U32 BA;
+  U32 MA;
+
+  CaHigh = 0x1B;
+  CaLow  = 0;
+
+  MrcConvertLpddr2Ddr (CaHigh, CaLow, &MA, &BA, &CMD);
+
+//  MRC_DEBUG_MSG (&MrcData->SysIn.Inputs.Debug, MSG_LEVEL_ERROR, "MA: 0x%X, BA: 0x%X, CMD: 0x%X\n", MA, BA, CMD);
+
+  MrcWriteCADBCmd (MrcData, Channel, RankMask, (U8) CMD, (U8) BA, (U16 *) &MA, 0);
+}
+
+#endif // ULT_FLAG
diff --git a/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Services/MrcIoControl.c b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Services/MrcIoControl.c
new file mode 100644
index 0000000..dc6fc11
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Services/MrcIoControl.c
@@ -0,0 +1,62 @@
+/** @file
+  This file is used as a driver to all memory controller IO registers.
+  It includes all the functions that the MRC needs to configure the IO and do the training.
+
+@copyright
+  Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved.
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement.
+**/
+
+//
+// Include files
+//
+#include "MrcIoControl.h"
+
+/**
+@brief
+  Reset the MC IO module. The MC hardware will handle creating the 20 dclk pulse
+  after the bit is set and will also clear the bit.
+
+  @param[in] MrcData - Include all MRC global data.
+
+  @retval mrcSuccess    - IO Reset was done successfully
+  @retval mrcDeviceBusy - Timed out waiting for the IO to clear the bit
+**/
+MrcStatus
+IoReset (
+  IN MrcParameters *const MrcData
+  )
+{
+  MCDECS_CR_MC_INIT_STATE_G_MCMAIN_STRUCT McInitStateG;
+  BOOL                                    Busy;
+  U32                                     Timeout;
+
+  Timeout = (U32) MrcGetCpuTime () + 10000;   // 10 seconds timeout
+
+  McInitStateG.Data          = MrcReadCR (MrcData, MCDECS_CR_MC_INIT_STATE_G_MCMAIN_REG);
+  McInitStateG.Bits.reset_io = 1;
+  MrcWriteCR (MrcData, MCDECS_CR_MC_INIT_STATE_G_MCMAIN_REG, McInitStateG.Data);
+
+  //
+  // Wait until the bit is cleared by hardware
+  //
+  do {
+    McInitStateG.Data = MrcReadCR (MrcData, MCDECS_CR_MC_INIT_STATE_G_MCMAIN_REG);
+    Busy              = (McInitStateG.Bits.reset_io == 1);
+  } while (Busy && ((U32) MrcGetCpuTime () < Timeout));
+
+  return (Busy ? mrcDeviceBusy : mrcSuccess);
+}
diff --git a/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Services/MrcMcConfiguration.c b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Services/MrcMcConfiguration.c
new file mode 100644
index 0000000..914491a
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Services/MrcMcConfiguration.c
@@ -0,0 +1,1405 @@
+/** @file
+  The functions in this file implement the memory controller registers that
+  are not training specific. After these functions are executed, the
+  memory controller will be ready to execute the timing training sequences.
+
+@copyright
+  Copyright (c) 1999 - 2013 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement.
+
+**/
+
+//
+// Include files
+//
+#include "MrcMcConfiguration.h"
+
+const U8 RxBiasTable[2][5][4] = {
+  /// Vdd low
+  ///    1067 Mhz,     1333 Mhz,     1600 MHz,     1867 MHz,     2133 Mhz
+  { {4, 3, 3, 2}, {4, 4, 3, 2}, {5, 4, 3, 3}, {5, 4, 4, 3}, {5, 4, 4, 3} },
+  /// Vdd hi
+  ///    1067 Mhz,     1333 Mhz,     1600 MHz,     1867 MHz,     2133 Mhz
+  { {4, 3, 3, 2}, {4, 4, 3, 2}, {5, 4, 3, 3}, {5, 4, 4, 3}, {4, 4, 3, 3} }
+};
+
+#ifdef ULT_FLAG
+const U8 RxBiasTableUlt[2][3][4] = {
+  /// Vdd low
+  ///  1067 Mhz,     1333 Mhz,     1600 MHz
+  { {5, 6, 6, 5}, {5, 6, 6, 5}, {4, 6, 6, 6} },
+  /// Vdd hi
+  ///  1067 Mhz,     1333 Mhz,     1600 MHz
+  { {7, 6, 6, 5}, {7, 6, 6, 5}, {7, 6, 6, 6} }
+};
+#endif // ULT_FLAG
+
+/**
+@brief
+  This function calculates the two numbers that get you closest to the slope.
+
+  @param[in] Slope - targeted slope (multiplied by 100 for int match)
+
+  @retval Returns the Slope Index to be programmed for VtSlope.
+**/
+U8
+MrcCalcVtSlopeCode (
+  IN const U16 Slope
+  )
+{
+  const S16 Coding[] = {0, -125, -62, -31, 250, 125, 62, 31};
+  S16       Error;
+  S16       BestError;
+  U8        BestI;
+  U8        BestJ;
+  U8        i;
+  U8        j;
+
+  BestError = 1000;
+  BestI     = 0;
+  BestJ     = 0;
+  for (i = 0; i < (sizeof (Coding) / sizeof (Coding[0])); i++) {
+    for (j = 0; j < (sizeof (Coding) / sizeof (Coding[0])); j++) {
+      Error = Slope - (Coding[i] + Coding[j]);
+      if (Error < 0) {
+        Error = -Error;
+      }
+
+      if (BestError > Error) {
+        BestError = Error;
+        BestI     = i;
+        BestJ     = j;
+      }
+    }
+  }
+
+  return (BestI << 3) + BestJ;
+}
+
+/**
+@brief
+  This function performs the memory controller configuration non training sequence.
+
+  @param[in, out] MrcData - Include all MRC global data.
+
+  @retval MrcStatus - mrcSuccess if successful or an error status
+**/
+MrcStatus
+MrcMcConfiguration (
+  IN OUT MrcParameters *const MrcData
+  )
+{
+  const U8          StdCASLat[] = {7, 9, 11, 13, 14};             // 1067, 1333, 1600, 1867 & 2133 MHz
+  const U8          ByteStagger[] = {0, 4, 1, 5, 2, 6, 3, 7, 8};
+  const U8          StepSize[]    = {64, 96, 64, 64, 64};         // From Design
+  U8                ReferenceR[]  = {25, 50, 20, 20, 25};         // Reference resistors on motherboard (+0 Ohm Rstray)
+  const U8          MinCycleStageDelay[] = {46, 70, 70, 46};      // Avoid corner case
+  const U8          TargetRcompConst[] = {33, 50, 20, 20, 29};    // Target values
+  const U8          BufferStageDelayPSConst[] = {59, 53, 53, 53}; // Slew = 1V / (# Stages * StageDelayPS * Derating)
+  const MrcDebug    *Debug;
+  MrcStatus         Status;
+  MrcInput          *Inputs;
+  MrcOutput         *Outputs;
+  MrcChannelIn      *ChannelIn;
+  MrcChannelOut     *ChannelOut;
+  MrcControllerOut  *ControllerOut;
+  MrcDimmOut        *DimmOut;
+  MrcCpuModel       CpuModel;
+  MrcCpuStepping    CpuStepping;
+  MrcProfile        Profile;
+  MrcVddSelect      Vdd;
+  BOOL              Cmd2N;
+  BOOL              AutoSelfRefresh;
+  U32               vrefup;
+  U32               Offset;
+  U32               Data32;
+  U32               DisableOdtStatic;
+  S16               CompVref;
+  U16               VssHiSwingTarget;
+  U16               vpanic;
+  U16               SAFE;
+  U16               NS;
+  U16               VssHi;                                        // Target VssHi Voltage
+  U16               Target;
+  U16               Slope;
+  U16               NumStages;
+  U16               lndown;
+  U16               Rdown;
+  U16               vrefdown;
+  U16               vsshiu;
+  U16               vsshid;
+  U16               lnup;
+  U16               Rup;
+  U16               RefiReduction;
+  S8                RxFselect;
+  U8                delta;
+  U8                Controller;
+  U8                Channel;
+  U8                Dimm;
+  U8                Rank;
+  U8                Byte;
+  U8                VddHi;
+  U8                OverClock;
+  U8                MinLatency;
+  U8                Latency[MAX_CHANNEL];
+  U8                ChannelLatency;
+  U8                RxCBSelect;
+  U8                RxB;
+  U8                stagger;
+  U8                Any2dpc;
+  U8                TargetRcomp[sizeof (TargetRcompConst) / sizeof (TargetRcompConst[0])];
+  U8                BufferStageDelayPS[sizeof (BufferStageDelayPSConst) / sizeof (BufferStageDelayPSConst[0])];
+  U8                i;
+  DDRDATA_CR_RXTRAINRANK0_STRUCT                RxTrainRank;
+  DDRDATA_CR_TXTRAINRANK0_STRUCT                TxTrainRank;
+  DDRDATA_CR_DDRCRDATACONTROL0_STRUCT           DdrCrDataControl0;
+  DDRDATA_CR_DDRCRDATACONTROL1_STRUCT           DdrCrDataControl1;
+  DDRDATA0CH0_CR_DDRCRDATACONTROL2_STRUCT       DdrCrDataControl2;
+#ifdef ULT_FLAG
+  BOOL                                          Lpddr;
+  U32                                           Group;
+  U32                                           Cke;
+  U32                                           CkeRankMapping;
+  DDRDATA_CR_DDRCRVSSHICONTROL_STRUCT           DdrCrVssHiControl;
+  DDRDATA7CH1_CR_DDRCRVREFCONTROL_STRUCT        DdrCrVrefControl;
+  PCU_CR_DDR_PTM_CTL_PCU_STRUCT                 DdrPtmCtl;
+#endif // ULT_FLAG
+#ifdef TRAD_FLAG
+  DDRDATACH0_CR_DDRCRVSSHIORVREFCONTROL_STRUCT  DdrCrVssHiOrVrefControl;
+#endif // TRAD_FLAG
+  DDRCOMP_CR_DDRCRCOMPVSSHICONTROL_STRUCT       DdrCrCompVssHiControl;
+  DDRDATA_CR_DDRCRVREFADJUST1_STRUCT            DdrCrVrefAdjust;
+  DDRCLKCH0_CR_DDRCRCLKCONTROLS_STRUCT          DdrCrClkControls;
+  DDRCMDCH0_CR_DDRCRCMDCONTROLS_STRUCT          DdrCrCmdControls;
+  DDRCKECH0_CR_DDRCRCTLCONTROLS_STRUCT          DdrCrCkeControls;
+  DDRCTLCH0_CR_DDRCRCTLCONTROLS_STRUCT          DdrCrCtlControls;
+  DDRCKECTLCH0_CR_DDRCRCTLPICODING_STRUCT       DdrCrCtlPiCoding;
+  DDRCLKCH0_CR_DDRCRCLKRANKSUSED_STRUCT         DdrCrClkRanksUsed;
+  DDRCTLCH0_CR_DDRCRCTLRANKSUSED_STRUCT         CtlDdrCrCtlRanksUsed;
+  DDRCKECH0_CR_DDRCRCTLRANKSUSED_STRUCT         CkeDdrCrCtlRanksUsed;
+  DDRCOMP_CR_DDRCRCOMPVSSHI_STRUCT              DdrCrCompVssHi;
+  DDRSCRAM_CR_DDRMISCCONTROL0_STRUCT            DdrMiscControl;
+  PCU_CR_M_COMP_PCU_STRUCT                      CrMCompPcu;
+  DDRDATA_CR_RCOMPDATA1_STRUCT                  DataRCompData;
+  DDRCMD_CR_DDRCRCMDCOMP_STRUCT                 CmdDdrCrCmdComp;
+  DDRCKECTL_CR_DDRCRCTLCOMP_STRUCT              CkeCtlDdrCrCtlComp;
+  DDRCLK_CR_DDRCRCLKCOMP_STRUCT                 ClkDdrCrClkComp;
+  DDRCOMP_CR_DDRCRDATACOMP1_STRUCT              CompDdrCrDataComp;
+  DDRCOMP_CR_DDRCRCMDCOMP_STRUCT                CompDdrCrCmdComp;
+  DDRCOMP_CR_DDRCRCTLCOMP_STRUCT                CompDdrCrCtlComp;
+  DDRCOMP_CR_DDRCRCLKCOMP_STRUCT                CompDdrCrClkComp;
+  DDRCOMP_CR_DDRCRCOMPOVR_STRUCT                CompDdrCrCompOvr;
+  DDRCOMP_CR_DDRCRCOMPCTL0_STRUCT               CompDdrCrCompCtl0;
+  DDRCOMP_CR_DDRCRCOMPCTL1_STRUCT               CompDdrCrCompCtl1;
+
+  Inputs            = &MrcData->SysIn.Inputs;
+  Debug             = &Inputs->Debug;
+  Outputs           = &MrcData->SysOut.Outputs;
+  ControllerOut     = &Outputs->Controller[0];
+  Profile           = Inputs->MemoryProfile;
+  Status            = mrcSuccess;
+  CpuModel          = Inputs->CpuModel;
+  CpuStepping       = Inputs->CpuStepping;
+  Vdd               = Outputs->VddVoltage[Inputs->MemoryProfile];
+  VddHi             = 0;
+  OverClock         = 0;
+  MinLatency        = 24;
+  SAFE              = 0;
+  VssHiSwingTarget  = 950;  // VssHi target voltage in mV
+  vpanic            = 24;   // Panic Treshold at 24 mV
+  delta             = 15;   // VssHi change voltage during panic: 15mV
+  RefiReduction     = 100;  // Init to 100% for no reduction.
+  DisableOdtStatic  = DISABLE_ODT_STATIC;
+
+  MrcOemMemorySet (Latency, 0, sizeof (Latency));
+  MrcOemMemoryCpy (TargetRcomp, (U8 *) TargetRcompConst, sizeof (TargetRcomp) / sizeof (TargetRcomp[0]));
+  MrcOemMemoryCpy (
+    BufferStageDelayPS,
+    (U8 *) BufferStageDelayPSConst,
+    sizeof (BufferStageDelayPS) / sizeof (BufferStageDelayPS[0])
+    );
+
+  for (Controller = 0; Controller < MAX_CONTROLLERS; Controller++) {
+    ControllerOut = &Outputs->Controller[Controller];
+    ControllerOut->DeviceId   = (U16) (MrcOemPciRead32 (HOST_BRIDGE_BUS, HOST_BRIDGE_DEVICE, HOST_BRIDGE_FUNCTION, HOST_BRIDGE_DEVID) >> 16);
+    ControllerOut->RevisionId = (U8)  (MrcOemPciRead32 (HOST_BRIDGE_BUS, HOST_BRIDGE_DEVICE, HOST_BRIDGE_FUNCTION, HOST_BRIDGE_REVID));
+  }
+
+#ifdef TRAD_FLAG
+  if ((CpuModel == cmHSW) || (CpuModel == cmCRW)) {
+    //
+    // Make sure tCL-tCWL <= 4
+    // This is needed to support ODT properly for 2DPC case
+    //
+    for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+      if (MrcChannelExist (Outputs, Channel)) {
+        ChannelOut = &ControllerOut->Channel[Channel];
+        if ((ChannelOut->Timing[Profile].tCL - ChannelOut->Timing[Profile].tCWL) > 4) {
+          ChannelOut->Timing[Profile].tCWL = ChannelOut->Timing[Profile].tCL - 4;
+          MRC_DEBUG_MSG (
+            Debug,
+            MSG_LEVEL_NOTE,
+            "(tCL-tCWL) > 4, CH %u - tCWL has been updated to %u\n",
+            Channel,
+            ChannelOut->Timing[Profile].tCWL
+            );
+        }
+      }
+    }
+  }
+#endif // TRAD_FLAG
+
+  //
+  // Set memory controller frequency
+  //
+  if (MrcOemCheckPoint (MrcData, OemFrequencySet, NULL) == mrcSuccess) {
+    Status = McFrequencySet (MrcData);
+    if (Status != mrcSuccess) {
+      return Status;
+    }
+  }
+#ifdef SSA_FLAG
+  MrcOemCheckPoint (MrcData, OemFrequencySetDone, NULL);
+#endif // SSA_FLAG
+  Outputs->Qclkps = (U16) (Outputs->MemoryClock / (2 * 1000)); // QCLK period in pico seconds.
+
+#ifdef ULT_FLAG
+  //
+  // Check if LPDDR3 memory is used
+  //
+  Lpddr = (Outputs->DdrType == MRC_DDR_TYPE_LPDDR3);
+
+  if (CpuModel == cmHSW_ULT) {
+    //
+    // Select the interleaving mode of DQ/DQS pins
+    // This must be the first DDR IO register to be programmed on ULT
+    //
+    DdrMiscControl.Data                   = 0;
+    DdrMiscControl.Bits.DdrNoChInterleave = (Inputs->DqPinsInterleaved) ? 0 : 1;
+    if (Lpddr) {
+      DdrMiscControl.Bits.LPDDR_Mode = 1;
+
+      //
+      // Initialize the CKE-to-rank mapping for LPDDR
+      //
+      DdrMiscControl.Bits.CKEMappingCh0 = Inputs->CkeRankMapping & 0x0F;
+      DdrMiscControl.Bits.CKEMappingCh1 = (Inputs->CkeRankMapping >> 4) & 0x0F;
+    }
+    MrcWriteCR (MrcData, DDRSCRAM_CR_DDRMISCCONTROL0_REG, DdrMiscControl.Data);
+    DisableOdtStatic = 1;
+  }
+#endif // ULT_FLAG
+  //
+  // Save MRC Version into CR
+  //
+  MrcSetMrcVersion (MrcData);
+
+  Any2dpc = 0;
+  if (Vdd > VDD_1_35) {
+    VddHi = 1;                                  // Set HiVdd bit if Vdd is over 1.35v
+  }
+
+  NS        = ~SAFE;
+
+  //
+  // RX BIAS calculations
+  //
+  GetRxFselect (MrcData, &RxFselect, &RxCBSelect);
+
+#ifdef ULT_FLAG
+  if (CpuModel == cmHSW_ULT) {
+    RxFselect = MIN (RxFselect, RXF_SELECT_MAX_ULT);    // Maximum 1600 MHz
+    RxB = RxBiasTableUlt[VddHi][RxFselect][RxCBSelect]; // Read setting from array lookup table
+  } else
+#endif // ULT_FLAG
+  {
+    RxB = RxBiasTable[VddHi][RxFselect][RxCBSelect]; // Read setting from array lookup table
+  }
+
+  //
+  // Determine Overclocking
+  //
+  for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+    if (MrcChannelExist (Outputs, Channel)) {
+      ChannelOut       = &ControllerOut->Channel[Channel];
+      Latency[Channel] = (U8) ChannelOut->Timing[Profile].tCL;
+      if (Latency[Channel] < MinLatency) {
+        MinLatency = Latency[Channel];
+      }
+    }
+  }
+
+  if ((Outputs->Frequency > 2133) || (MinLatency < StdCASLat[RxFselect])) {
+    OverClock = 1;
+  }
+  //
+  // Initialize ValidChBitMask and ValidRankMask used during all training steps
+  //
+  for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+    if (!MrcChannelExist (Outputs, Channel)) {
+      continue;
+    }
+    ChannelOut = &ControllerOut->Channel[Channel];
+    ChannelIn = &Inputs->Controller[0].Channel[Channel];
+
+    if (ChannelOut->DimmCount == 2) {
+      Any2dpc++;
+    }
+
+    Outputs->ValidChBitMask |= (1 << Channel);
+    Outputs->ValidRankMask  |= ChannelOut->ValidRankBitMask;
+    MRC_DEBUG_MSG (
+      Debug,
+      MSG_LEVEL_NOTE,
+      "C%uValidRankBitMask / ValidRankMask - 0x%x / 0x%x\n",
+      Channel,
+      ChannelOut->ValidRankBitMask,
+      Outputs->ValidRankMask
+      );
+
+    //
+    // Initialize RanksUsed in CLK fub
+    //
+    DdrCrClkRanksUsed.Data = 0;
+    DdrCrClkRanksUsed.Bits.RankEn = ChannelOut->ValidRankBitMask;
+#ifdef ULT_FLAG
+    if (Lpddr) {
+      //
+      // On LPDDR the CLK RanksUsed goes by CLK group instead of by Rank
+      //
+      DdrCrClkRanksUsed.Bits.RankEn = 0;
+      for (Group = 0; Group < 2; Group++) {
+        if (ChannelIn->DQByteMap[MrcIterationClock][Group] != 0) {
+          DdrCrClkRanksUsed.Bits.RankEn |= (1 << Group);
+        }
+      }
+    }
+#endif // ULT_FLAG
+    Offset = DDRCLKCH0_CR_DDRCRCLKRANKSUSED_REG +
+      ((DDRCLKCH1_CR_DDRCRCLKRANKSUSED_REG - DDRCLKCH0_CR_DDRCRCLKRANKSUSED_REG) * Channel);
+    MrcWriteCR (MrcData, Offset, DdrCrClkRanksUsed.Data);
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "DDRCLKCH%d_CR_DDRCRCTLRANKSUSED = 0x%X\n", Channel, DdrCrClkRanksUsed.Data);
+
+    //
+    // Initialize RanksUsed in CTL fub - CS (and ODT for LPDDR)
+    //
+    CtlDdrCrCtlRanksUsed.Data = 0;
+    CtlDdrCrCtlRanksUsed.Bits.RankEn = ChannelOut->ValidRankBitMask;
+#ifdef ULT_FLAG
+    if (CpuModel == cmHSW_ULT) {
+      if (Lpddr && Inputs->LpddrDramOdt) {
+        //
+        // ODT is used on rank 0
+        //
+        CtlDdrCrCtlRanksUsed.Bits.OdtDisable = 2;
+      } else {
+        CtlDdrCrCtlRanksUsed.Bits.OdtDisable = 3;
+      }
+    }
+#endif // ULT_FLAG
+    Offset = DDRCTLCH0_CR_DDRCRCTLRANKSUSED_REG +
+      ((DDRCTLCH1_CR_DDRCRCTLRANKSUSED_REG - DDRCTLCH0_CR_DDRCRCTLRANKSUSED_REG) * Channel);
+    MrcWriteCR (MrcData, Offset, CtlDdrCrCtlRanksUsed.Data);
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "DDRCTLCH%d_CR_DDRCRCTLRANKSUSED = 0x%X\n", Channel, CtlDdrCrCtlRanksUsed.Data);
+
+    //
+    // Initialize RanksUsed in CKE fub
+    //
+    CkeDdrCrCtlRanksUsed.Data = 0;
+    CkeDdrCrCtlRanksUsed.Bits.RankEn = ChannelOut->ValidRankBitMask;
+#ifdef ULT_FLAG
+    if (Lpddr) {
+      CkeDdrCrCtlRanksUsed.Bits.RankEn = 0;
+      //
+      // Use CKE-to-Rank mapping: [3:0] - Channel 0, [7:4] - Channel 1
+      //
+      CkeRankMapping = (Inputs->CkeRankMapping >> (Channel * 4)) & 0x0F;
+      for (Rank = 0; Rank < MAX_RANK_IN_CHANNEL; Rank++) {
+        for (Cke = 0; Cke <= 3; Cke++) {
+          if (((CkeRankMapping >> Cke) & 1) == Rank) {
+            //
+            // This CKE pin is connected to this Rank...
+            //
+            if (ChannelOut->ValidRankBitMask & (1 << Rank)) {
+              //
+              // ...and this rank is enabled
+              //
+              CkeDdrCrCtlRanksUsed.Bits.RankEn |= (1 << Cke);
+            }
+          }
+        }
+      }
+    }
+#endif // ULT_FLAG
+    Offset = DDRCKECH0_CR_DDRCRCTLRANKSUSED_REG +
+      ((DDRCKECH1_CR_DDRCRCTLRANKSUSED_REG - DDRCKECH0_CR_DDRCRCTLRANKSUSED_REG) * Channel);
+    MrcWriteCR (MrcData, Offset, CkeDdrCrCtlRanksUsed.Data);
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "DDRCKECH%d_CR_DDRCRCTLRANKSUSED = 0x%X\n", Channel, CkeDdrCrCtlRanksUsed.Data);
+    //
+    // Save for future use in JEDEC Reset, etc.
+    //
+    ChannelOut->ValidCkeBitMask = (U8) CkeDdrCrCtlRanksUsed.Bits.RankEn;
+  }  //  for Channel
+
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Init Data CRs\n");
+
+
+  //
+  // Initialize Rx and Tx Data CRs
+  //
+  for (Rank = 0; Rank < MAX_RANK_IN_CHANNEL; Rank++) {
+    if (((1 << Rank) & Outputs->ValidRankMask) == 0) {
+      continue;
+    }
+    //
+    // RxDqsN/P_Pi = 32, RcvEn = 64, RxEq = 1
+    //
+    RxTrainRank.Data           = 0;
+    RxTrainRank.Bits.RxRcvEnPi = 64;
+    RxTrainRank.Bits.RxDqsPPi  = 32;
+    RxTrainRank.Bits.RxDqsNPi  = 32;
+    RxTrainRank.Bits.RxEq      = 1;
+    //
+    // RxGroup - Broadcast all channels
+    //
+    Offset = DDRDATA_CR_RXTRAINRANK0_REG + ((DDRDATA_CR_RXTRAINRANK1_REG - DDRDATA_CR_RXTRAINRANK0_REG) * Rank);
+    MrcWriteCrMulticast (MrcData, Offset, RxTrainRank.Data);
+
+    //
+    // Rx per bit offset - Middle value. Train later.
+    //
+    Offset = DDRDATA_CR_RXPERBITRANK0_REG + ((DDRDATA_CR_RXPERBITRANK1_REG - DDRDATA_CR_RXPERBITRANK0_REG) * Rank);
+    Data32 = 0x88888888;
+    MrcWriteCrMulticast (MrcData, Offset, Data32);
+
+    //
+    // Set TxEq to full strength, TxDqs = 0 and TxDq = 32,
+    //
+    TxTrainRank.Data                = 0;
+    TxTrainRank.Bits.TxEqualization = TXEQFULLDRV | 0x0B;
+    TxTrainRank.Bits.TxDqDelay      = 96;
+    TxTrainRank.Bits.TxDqsDelay     = 64;
+    Offset = DDRDATA_CR_TXTRAINRANK0_REG + ((DDRDATA_CR_TXTRAINRANK1_REG - DDRDATA_CR_TXTRAINRANK0_REG) * Rank);
+    MrcWriteCrMulticast (MrcData, Offset, TxTrainRank.Data);
+    //
+    // Middle value. Train later.
+    //
+    Offset = DDRDATA_CR_TXPERBITRANK0_REG + ((DDRDATA_CR_TXPERBITRANK1_REG - DDRDATA_CR_TXPERBITRANK0_REG) * Rank);
+    MrcWriteCrMulticast (MrcData, Offset, 0x88888888);
+
+    //
+    // Save in MrcData
+    //
+    for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+      ChannelOut = &ControllerOut->Channel[Channel];
+      for (Byte = 0; Byte < MAX_SDRAM_IN_DIMM; Byte++) {
+        ChannelOut->TxDq[Rank][Byte]    = (U16) (TxTrainRank.Bits.TxDqDelay);
+        ChannelOut->TxDqs[Rank][Byte]   = (U16) (TxTrainRank.Bits.TxDqsDelay);
+        ChannelOut->TxEq[Rank][Byte]    = (U8) (TxTrainRank.Bits.TxEqualization);
+
+        ChannelOut->RcvEn[Rank][Byte]   = (U16) (RxTrainRank.Bits.RxRcvEnPi);
+        ChannelOut->RxDqsP[Rank][Byte]  = (U8) (RxTrainRank.Bits.RxDqsPPi);
+        ChannelOut->RxDqsN[Rank][Byte]  = (U8) (RxTrainRank.Bits.RxDqsNPi);
+        ChannelOut->RxEq[Rank][Byte]    = (U8) (RxTrainRank.Bits.RxEq);
+      }
+    }
+  }
+  //
+  // Initial value to corresponding 0.
+  //
+  MrcWriteCrMulticast (MrcData, DDRDATA_CR_TXXTALK_REG, 0x0);
+  //
+  // Amplifier voltage offset {0: Most negative offset,... 8: 0 offset, ... 15: Most postive offset}
+  //
+  MrcWriteCrMulticast (MrcData, DDRDATA_CR_RXOFFSETVDQ_REG, 0x88888888);
+  MrcWriteCrMulticast (MrcData, DDRDATA_CR_DDRCRDATAOFFSETTRAIN_REG, 0x0);
+  MrcWriteCrMulticast (MrcData, DDRDATA_CR_DDRCRDATAOFFSETCOMP_REG, 0x0);
+
+  //
+  // Disable ODT Static Leg, set Vdd
+  //
+  DdrCrDataControl0.Data                  = 0;
+  DdrCrDataControl0.Bits.DataVccddqHi     = VddHi;
+  DdrCrDataControl0.Bits.DisableOdtStatic = DisableOdtStatic;
+#ifdef ULT_FLAG
+  if (Lpddr) {
+    DdrCrDataControl0.Bits.LPDDR_Mode       = 1;
+    //
+    // If C0 or greater, enable EarlyRleak.  Otherwise, no Read Conditioning.
+    //
+    if ((CpuModel == cmHSW_ULT) && (CpuStepping >= csHswUltC0)) {
+      DdrCrDataControl0.Bits.EarlyRleakEn     = 1;  // Mutually exclusive with DdrCrDataControl0.EnReadPreamble
+    }
+    DdrCrDataControl0.Bits.OdtSampExtendEn  = 1;
+  }
+#endif // ULT_FLAG
+#ifdef TRAD_FLAG
+  if ((CpuModel == cmHSW) || (CpuModel == cmCRW)) {
+    DdrCrDataControl0.Bits.InternalClocksOn = 1;
+  }
+#endif // TRAD_FLAG
+  MrcWriteCrMulticast (MrcData, DDRDATA_CR_DDRCRDATACONTROL0_REG, DdrCrDataControl0.Data);
+  DdrCrDataControl1.Data = 0;
+  if (Inputs->WeaklockEn) {
+    DdrCrDataControl1.Bits.DllWeakLock = NS; // Enable DLL WeakLock
+  }
+
+  DdrCrDataControl1.Bits.DllMask          = 1;                                                 // 2 qclk DLL mask
+  DdrCrDataControl1.Bits.OdtDelay         = 0xE;                                               // Signed value of (-2) has been converted to hex
+  DdrCrDataControl1.Bits.SenseAmpDelay    = 0xE;                                               // Signed value of (-2) has been converted to hex
+  DdrCrDataControl1.Bits.SenseAmpDuration = DDRDATA_CR_DDRCRDATACONTROL1_SenseAmpDuration_MAX; // Max Samp Duration.
+  DdrCrDataControl1.Bits.OdtDuration      = DDRDATA_CR_DDRCRDATACONTROL1_OdtDuration_MAX;      // Max Odt Duration.
+  DdrCrDataControl1.Bits.RxBiasCtl        = RxB;                                               // RxBias uses LUT.
+
+#ifdef ULT_FLAG
+#endif // ULT_FLAG
+
+  MrcWriteCrMulticast (MrcData, DDRDATA_CR_DDRCRDATACONTROL1_REG, DdrCrDataControl1.Data);
+
+  DdrCrDataControl2.Data = 0;       // Define DQControl2
+
+#ifdef ULT_FLAG
+  if (CpuModel == cmHSW_ULT) {
+    DdrCrDataControl2.Bits.RxDqsAmpOffset = DDRDATA0CH0_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_DEF;
+    DdrCrDataControl2.Bits.RxClkStgNum    = DDRDATA0CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_MAX;
+    if (Lpddr) {
+      DdrCrDataControl2.Bits.LeakerComp = 3;
+    }
+  }
+#endif // ULT_FLAG
+
+  for (Channel = 0; Channel < MAX_CHANNEL; Channel++){
+    if (MrcChannelExist (Outputs, Channel)) {
+      ChannelOut                   = &ControllerOut->Channel[Channel];
+
+      ChannelOut->DqControl0.Data  = DdrCrDataControl0.Data;
+      ChannelLatency               = 2 * Latency[Channel] - 6;
+      for (Byte = 0; Byte < Outputs->SdramCount; Byte++) {
+        //
+        // These CRs do a lot of RMW.
+        //
+        ChannelOut->DataOffsetTrain[Byte] = 0;    // Faster to store the value in host
+        ChannelOut->DataCompOffset[Byte]  = 0;
+        ChannelOut->DqControl1[Byte].Data = DdrCrDataControl1.Data;
+
+        //
+        // Stagger byte turnon to reduce dI/dT. In safe mode, turn off stagger feature
+        //
+        stagger = (SAFE) ? 0 : ((ChannelLatency * ByteStagger[Byte]) / (U8) Outputs->SdramCount) & 0x1F;
+        Offset = DDRDATA0CH0_CR_DDRCRDATACONTROL2_REG +
+          ((DDRDATA0CH1_CR_DDRCRDATACONTROL2_REG - DDRDATA0CH0_CR_DDRCRDATACONTROL2_REG) * Channel) +
+          ((DDRDATA1CH0_CR_DDRCRDATACONTROL2_REG - DDRDATA0CH0_CR_DDRCRDATACONTROL2_REG) * Byte);
+        DdrCrDataControl2.Bits.RxStaggerCtl = stagger;
+        MrcWriteCR (MrcData, Offset, DdrCrDataControl2.Data);
+        ChannelOut->DqControl2[Byte].Data = DdrCrDataControl2.Data;
+      }
+    }
+  }
+
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Init Data VssHi CRs\n");
+  //
+  // Initialize VssHi CRs
+  //
+  // @todo: Need to verify as I don't have bit definitions for VssHi mode
+  //
+  VssHi = ((U16) Vdd - VssHiSwingTarget);   // VssHiSwingTarget = 950 mV, VddmV=1500 mV
+  Target = (VssHi * 192) / (U16) Vdd - 20;  // Sets target for VssHi.
+
+  DdrCrCompVssHiControl.Data = 0;
+#ifdef ULT_FLAG
+  if (CpuModel == cmHSW_ULT) {
+    DdrCrVssHiControl.Data = (SAFE) ?                           // SAFE: Panic at 7*8=56mV, !SAFE: Panic at 24mV, GainBoost.
+      (7 << 18) + (2 << 14) + (2 << 8) + (2 << 6) :             // Set BwError and *BWDivider to safe values
+      (1 << 22) + (3 << 18) + (2 << 14) + (1 << 8) + (1 << 6);  // Normal values for BwError/*BWDivider
+    DdrCrVssHiControl.Data += (1 << 16);                        // Enable Panic Driver
+    DdrCrVssHiControl.Data += Target + (0 << 10);               // Set loop sample frequency at max
+    MrcWriteCrMulticast (MrcData, DDRDATA_CR_DDRCRVSSHICONTROL_REG, DdrCrVssHiControl.Data); // Multicast to both channels
+    //
+    // Set COMP VssHi the same
+    //
+    DdrCrCompVssHiControl.Data = DdrCrVssHiControl.Data;
+  }
+#endif // ULT_FLAG
+#ifdef TRAD_FLAG
+  if ((CpuModel == cmHSW) || (CpuModel == cmCRW)) {
+    DdrCrVssHiOrVrefControl.Data = (SAFE) ?                     // SAFE: Panic at 7*8=56mV, !SAFE: Panic at 24mV, GainBoost.
+      (7 << 18) + (2 << 14) + (2 << 8) + (2 << 6) :             // Set BwError and *BWDivider to safe values
+      (1 << 22) + (3 << 18) + (2 << 14) + (1 << 8) + (1 << 6);  // Normal values for BwError/*BWDivider
+    DdrCrVssHiOrVrefControl.Data += (1 << 16);                  // Enable Panic Driver
+    DdrCrVssHiOrVrefControl.Data += Target + (0 << 10);         // Set loop sample frequency at max
+    MrcWriteCrMulticast (MrcData, DDRDATACH0_CR_DDRCRVSSHIORVREFCONTROL_REG, DdrCrVssHiOrVrefControl.Data);
+
+    //
+    // Set COMP VssHi the same
+    //
+    DdrCrCompVssHiControl.Data = DdrCrVssHiOrVrefControl.Data;
+  }
+#endif // TRAD_FLAG
+
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Init Comp VssHi CRs\n");
+  MrcWriteCrMulticast (MrcData, DDRCOMP_CR_DDRCRCOMPVSSHICONTROL_REG, DdrCrCompVssHiControl.Data);
+
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Init Dimm Vref CRs\n");
+  //
+  // Initialize Dimm Vref CRs - Use CH1 BYTE 7
+  //
+  // Ideal Slope EQN = (192/128*VccIo/Vdd-1)
+  //
+  Slope = (U16) ((1000 * 192 * Inputs->VccIomV) / (128 * (U16) Vdd) - 1000);
+  Slope = MrcCalcVtSlopeCode (Slope);             // Translate ideal slope in CR value
+
+#ifdef ULT_FLAG
+  if (CpuModel == cmHSW_ULT) {
+    //
+    // No Offset.  Apply Slope adjustment VT Slope A = 4, VT Slope B = 0, Set SlowBWError = 1
+    //
+    DdrCrVrefControl.Data = (0 << 18) + (0x20 << 12) + (1 << 8);
+    //
+    // Enable HiBW mode, Set Loop Frequency
+    //
+    DdrCrVrefControl.Data += (1 << 10) + (1 << 4);
+    //
+    // Set LoBWDiv, HiBWDiv
+    //
+    DdrCrVrefControl.Data += (3 << 2) + (0 << 0);
+    //
+    // Program DimmVref Control Values
+    //
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "DdrCrVrefControl: 0x%X\n", DdrCrVrefControl.Data);
+    MrcWriteCR (MrcData, DDRDATA7CH1_CR_DDRCRVREFCONTROL_REG, DdrCrVrefControl.Data);
+  }
+#endif // ULT_FLAG
+#ifdef TRAD_FLAG
+  if ((CpuModel == cmHSW) || (CpuModel == cmCRW)) {
+    //
+    // No Offset.  Apply Slope adjustment, Set SlowBWError = 1
+    //
+    DdrCrVssHiOrVrefControl.Data = (0 << 18) + (Slope << 12) + (1 << 8);
+    //
+    // Enable HiBW mode, Set Loop Frequency
+    //
+    DdrCrVssHiOrVrefControl.Data += (1 << 10) + (3 << 4);
+    //
+    // Set LoBWDiv, HiBWDiv
+    //
+    DdrCrVssHiOrVrefControl.Data += (3 << 2) + (3 << 0);
+    //
+    // Program DimmVref Control Values
+    //
+    MrcWriteCR (MrcData, DDRDATA7CH1_CR_DDRCRVSSHIORVREFCONTROL_REG, DdrCrVssHiOrVrefControl.Data);
+  }
+#endif // TRAD_FLAG
+
+  //
+  // Enable all DimmVref and VddHi based on VddVoltage
+  //
+  DdrCrVrefAdjust.Data               = 0;
+  DdrCrVrefAdjust.Bits.EnDimmVrefCA  = 1;
+  DdrCrVrefAdjust.Bits.EnDimmVrefCh0 = 1;
+  DdrCrVrefAdjust.Bits.EnDimmVrefCh1 = 1;
+  DdrCrVrefAdjust.Bits.VccddqHiQnnnH = VddHi;
+  DdrCrVrefAdjust.Bits.HiZTimerCtrl  = DDRDATA_CR_DDRCRVREFADJUST1_HiZTimerCtrl_MAX;
+  //
+  // Enable DimmVref Drivers with Vref = 0
+  //
+  MrcWriteCrMulticast (MrcData, DDRDATA_CR_DDRCRVREFADJUST1_REG, DdrCrVrefAdjust.Data);
+  Outputs->DimmVref = DdrCrVrefAdjust.Data;
+
+  for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+    if (MrcChannelExist (Outputs, Channel)) {
+
+      ChannelOut = &ControllerOut->Channel[Channel];
+
+      MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Init CLK CRs\n");
+      //
+      // Initialize Clock CRs
+      //
+      DdrCrClkControls.Data          = 0;
+      DdrCrClkControls.Bits.DllMask  = 1;                 // Set 2 qclk DLL mask
+      DdrCrClkControls.Bits.VccddqHi = VddHi;             // Set Vdd
+#ifdef ULT_FLAG
+      if (Lpddr) {
+        DdrCrClkControls.Bits.LPDDR_Mode = 1;
+      }
+#endif // ULT_FLAG
+      Offset = DDRCLKCH0_CR_DDRCRCLKCONTROLS_REG +
+        ((DDRCLKCH1_CR_DDRCRCLKCONTROLS_REG - DDRCLKCH0_CR_DDRCRCLKCONTROLS_REG) * Channel);
+      MrcWriteCR (MrcData, Offset, DdrCrClkControls.Data);
+
+      DdrCrCmdControls.Data = DdrCrClkControls.Data;
+      DdrCrCtlControls.Data = DdrCrClkControls.Data;
+      // Determine if weaklock can or can not be enabled
+      //
+      if (Inputs->WeaklockEn) {
+        DdrCrCmdControls.Bits.DllWeakLock = NS;
+        DdrCrCtlControls.Bits.DllWeakLock = NS;
+      }
+      MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Init CMD N and P CRs\n");
+      //
+      // Initialize CmdN/CmdS CRx
+      //
+      DdrCrCmdControls.Bits.EarlyWeakDrive  = 3;
+      DdrCrCmdControls.Bits.CmdTxEq         = NS & 1; // Enable Early Warning and Cmd DeEmphasis
+      MrcWriteCR (MrcData, DDRCMDCH0_CR_DDRCRCMDCONTROLS_REG +
+        ((DDRCMDCH1_CR_DDRCRCMDCONTROLS_REG - DDRCMDCH0_CR_DDRCRCMDCONTROLS_REG) * Channel), DdrCrCmdControls.Data);
+
+      MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Init CKE CRs\n");
+      //
+      // Initialize CKE CRs
+      //
+      // @todo: DONE Either CKE and CTL must be set the same or we have to be using the per channel defines and not a Multicast.
+      //
+      DdrCrCkeControls.Data           = DdrCrCmdControls.Data;
+      DdrCrCkeControls.Bits.CtlSRDrv  = NS & 2;
+      DdrCrCkeControls.Bits.CtlTxEq   = NS & 1; // Enable Weak CKE in SR and Cke DeEmphasis
+      MrcWriteCR (
+        MrcData,
+        DDRCKECH0_CR_DDRCRCTLCONTROLS_REG +
+        ((DDRCKECH1_CR_DDRCRCTLCONTROLS_REG - DDRCKECH0_CR_DDRCRCTLCONTROLS_REG) * Channel),
+        DdrCrCkeControls.Data
+        );
+
+      MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Init CTL CRs\n");
+      //
+      // Initialize CTL CRs
+      //
+      DdrCrCtlControls.Bits.CtlTxEq  = (NS & 1);  // Enable Weak CKE in SR and Cke DeEmphasis
+      DdrCrCtlControls.Bits.CtlSRDrv = (NS & 2);  // Enable Weak CKE in SR and Cke DeEmphasis
+      DdrCrCtlControls.Bits.LaDrvEnOvrd = 1;
+      MrcWriteCR (
+        MrcData,
+        DDRCTLCH0_CR_DDRCRCTLCONTROLS_REG +
+        ((DDRCTLCH1_CR_DDRCRCTLCONTROLS_REG - DDRCTLCH0_CR_DDRCRCTLCONTROLS_REG) * Channel),
+        DdrCrCtlControls.Data
+        );
+      //
+      // Initialize CRs shared between CKE/CTL/CMD/CLK
+      //
+      // PI setting must match value written for TxDQs above.
+      // There are no shared registers for CLK, only CKE/CTL but only CTLPICODING and CTLCOMPOFFSET
+      // Set CTL/CLK PI to 64, and CMD to 96 (64 + 1/2 QCLK), for ideal initial command centering.
+      //
+      DdrCrCtlPiCoding.Data            = 0;
+      DdrCrCtlPiCoding.Bits.CtlPiCode0 =
+      DdrCrCtlPiCoding.Bits.CtlPiCode1 =
+      DdrCrCtlPiCoding.Bits.CtlPiCode2 =
+      DdrCrCtlPiCoding.Bits.CtlPiCode3 = 96;
+
+      Offset = DDRCMDCH0_CR_DDRCRCMDPICODING_REG +
+        ((DDRCMDCH1_CR_DDRCRCMDPICODING_REG - DDRCMDCH0_CR_DDRCRCMDPICODING_REG) * Channel);
+#ifdef ULT_FLAG
+      if (CpuModel == cmHSW_ULT) {
+        //
+        // On ULT we have DdrCrCmdPiCoding.CmdPi0Code and CmdPi1Code
+        //
+        MrcWriteCR (MrcData, Offset, DdrCrCtlPiCoding.Data);
+      }
+#endif // ULT_FLAG
+#ifdef TRAD_FLAG
+      if ((CpuModel == cmHSW) || (CpuModel == cmCRW)) {
+        MrcWriteCR8 (MrcData, Offset, (U8) DdrCrCtlPiCoding.Bits.CtlPiCode0);
+      }
+#endif // TRAD_FLAG
+
+      Offset = DDRCKECH0_CR_DDRCRCMDPICODING_REG +
+        ((DDRCKECH1_CR_DDRCRCMDPICODING_REG - DDRCKECH0_CR_DDRCRCMDPICODING_REG) * Channel);
+      MrcWriteCR (MrcData, Offset, DdrCrCtlPiCoding.Data);
+
+      DdrCrCtlPiCoding.Bits.CtlPiCode0 =
+      DdrCrCtlPiCoding.Bits.CtlPiCode1 =
+      DdrCrCtlPiCoding.Bits.CtlPiCode2 =
+      DdrCrCtlPiCoding.Bits.CtlPiCode3 = 64;
+
+      Offset = DDRCKECTLCH0_CR_DDRCRCTLPICODING_REG +
+        ((DDRCKECTLCH1_CR_DDRCRCTLPICODING_REG - DDRCKECTLCH0_CR_DDRCRCTLPICODING_REG) * Channel);
+      MrcWriteCR (MrcData, Offset, DdrCrCtlPiCoding.Data);
+
+      Offset = DDRCLKCH0_CR_DDRCRCLKPICODE_REG +
+        ((DDRCLKCH1_CR_DDRCRCLKPICODE_REG - DDRCLKCH0_CR_DDRCRCLKPICODE_REG) * Channel);
+      MrcWriteCR (MrcData, Offset, DdrCrCtlPiCoding.Data);
+
+      for (Rank = 0; Rank < MAX_RANK_IN_CHANNEL; Rank++) {
+        ChannelOut->ClkPiCode[Rank] = (U8) DdrCrCtlPiCoding.Bits.CtlPiCode0;
+      }
+
+      Offset = DDRCMDCH0_CR_DDRCRCMDCOMPOFFSET_REG +
+        ((DDRCMDCH1_CR_DDRCRCMDCOMPOFFSET_REG - DDRCMDCH0_CR_DDRCRCMDCOMPOFFSET_REG) * Channel);
+      MrcWriteCR (MrcData, Offset, 0x0);     // Zero for now. May offset comp in future
+
+      Offset = DDRCKECTLCH0_CR_DDRCRCTLCOMPOFFSET_REG +
+        ((DDRCKECTLCH1_CR_DDRCRCTLCOMPOFFSET_REG - DDRCKECTLCH0_CR_DDRCRCTLCOMPOFFSET_REG) * Channel);
+      MrcWriteCR (MrcData, Offset, 0x0);  // Zero for now. May offset comp in future
+
+      Offset = DDRCLKCH0_CR_DDRCRCLKCOMPOFFSET_REG +
+        ((DDRCLKCH1_CR_DDRCRCLKCOMPOFFSET_REG - DDRCLKCH0_CR_DDRCRCLKCOMPOFFSET_REG) * Channel);
+      MrcWriteCR (MrcData, Offset, 0x0);     // Zero for now. May offset comp in future
+    }
+  } // End of for Channel...
+
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Init COMP CRs\n");
+  //
+  // Initialize COMP CRs
+  //
+  // 14:11 DqDrv  19:15 DqOdt  23:20 CmdDrv  27:24 CtlDrv  31:28 ClkDrv
+  //
+  Outputs->CompCtl0 = (DisableOdtStatic << 3); // Disable ODT Static Leg
+
+  if ((Any2dpc) && (Inputs->BoardType == btCRBDT)) {
+    TargetRcomp[1] = 60;
+  }
+
+#ifdef ULT_FLAG
+  if (CpuModel == cmHSW_ULT) {
+    //
+    // RCOMP1 resistor is 120 Ohm on ULT boards
+    // This is used for DQ/CLK Ron (drive strength)
+    //
+    ReferenceR[0]  = 40;
+    TargetRcomp[0] = 40;
+
+    ReferenceR[4]  = 40;
+  }
+#endif // ULT_FLAG
+
+  for (i = 0; i < 5; i++) {
+    CompVref = (StepSize[i] * (ReferenceR[i] - TargetRcomp[i])) / (2 * (ReferenceR[i] + TargetRcomp[i]));
+    if (i == 1) {
+      //
+      // DqOdt is 5 bits
+      //
+      if (CompVref > 15) {
+        CompVref = 15;
+      } else if (CompVref < -16) {
+        CompVref = -16;
+      }
+
+      Outputs->CompCtl0 |= (CompVref & 0x1F) << (15);
+    } else {
+      if (CompVref > 7) {
+        CompVref = 7;
+      } else if (CompVref < -8) {
+        CompVref = -8;
+      }
+
+      if (i == 0) {
+        Outputs->CompCtl0 |= (CompVref & 0xF) << (11);
+      } else {
+        Outputs->CompCtl0 |= (CompVref & 0xF) << (12 + 4 * i);
+      }
+    }
+    //
+    //    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "CompVref[%d] = 0x%x\n", i, CompVref);
+    //
+  }
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "CompCtl0 = 0x%08X\n", Outputs->CompCtl0);
+  MrcWriteCR (MrcData, DDRCOMP_CR_DDRCRCOMPCTL0_REG, Outputs->CompCtl0);
+
+  CompDdrCrCompCtl1.Data           = 0;
+  CompDdrCrCompCtl1.Bits.VccddqHi  = VddHi;            // Set Vdd, 2 qclk DLL mask
+  CompDdrCrCompCtl1.Bits.CompClkOn = SAFE;             // Override PwrDn in Safe Mode
+
+  Cmd2N = FALSE;
+  for (Controller = 0; Controller < MAX_CONTROLLERS; Controller++) {
+    for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+      if (Outputs->Controller[Controller].Channel[Channel].Timing[Profile].NMode == 2)
+        Cmd2N = TRUE;
+      if (Cmd2N) {
+        break;
+      }
+    }
+    for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+      Outputs->Controller[Controller].Channel[Channel].Timing[Profile].NMode = (Cmd2N == TRUE) ? 2 : 1;
+    }
+  }
+
+  //
+  // Calculate how to program the slew rate targets
+  // Buffer Type         DQ  CMD  CTL  CLK
+  // Num Stages           3    5    5    3
+  // Slew Rate          4.5  3.0  3.0  5.0
+  // Derating            .8   .8   .8   .8
+  //
+
+/*
+  U8  BufferStageDelayPS[4] = {92, 83, 83, 83}; // Slew = 1V(in mv) / (# Stages * StageDelayPS * Derating)
+  U8  MinCycleStageDelay[4] = {46, 70, 70, 46}; // Avoid corner case
+  U8  i;
+  U16  NumStages;
+*/
+  if (Cmd2N == TRUE) {
+    BufferStageDelayPS[1] = 89; // CMD Slew Rate  = 1.8  for 2N
+  }
+
+#ifdef ULT_FLAG
+  if (Lpddr) {
+    BufferStageDelayPS[1] = 63; // CMD Slew Rate  = 4 V/ns for double-pumped CMD bus
+  }
+#endif // ULT_FLAG
+
+  for (i = 0; i < 4; i++) {
+    //
+    // Calculate DQ, CMD, CTL, CLK
+    // Number of Stages in DLL, rounded to nearest integer
+    // MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "BufferStageDelayPS[%d] = %d\n", i, BufferStageDelayPS[i]);
+    //
+    NumStages = (Outputs->Qclkps + BufferStageDelayPS[i] / 2) / BufferStageDelayPS[i];
+    if (NumStages < 5) {
+      NumStages = 5;  // Minimum setting > 3
+    }
+    //
+    // Lock DLL ....
+    //
+    Offset = i * (DDRCOMP_CR_DDRCRCOMPCTL1_DqScompCells_WID + DDRCOMP_CR_DDRCRCOMPCTL1_DqScompPC_WID);
+    if ((NumStages > 16) || (BufferStageDelayPS[i] < MinCycleStageDelay[i])) {
+      CompDdrCrCompCtl1.Data += ((NumStages / 2 - 1) << Offset); // ... to a phase
+    } else {
+      CompDdrCrCompCtl1.Data += (16 + NumStages - 1) << Offset;  // ... to a cycle
+    }
+    //
+    // MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Qclkps = %d, NumStages = %d\n",Outputs->Qclkps, NumStages);
+    //
+  }
+
+  MrcWriteCR (MrcData, DDRCOMP_CR_DDRCRCOMPCTL1_REG, CompDdrCrCompCtl1.Data);
+  Outputs->CompCtl1 = CompDdrCrCompCtl1.Data;
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "CompCtl1 = 0x%x\n", CompDdrCrCompCtl1.Data);
+
+  //
+  // Calculate Target Values for VssHi Panic Driver
+  //
+  // Rtarget = Tperiod / Cdie / ln( VssHi / (VssHi - Delta) )
+  //
+
+/*
+  U8  delta = 15;                               // VssHi change voltage during panic: 15mV
+  U16 lndown;
+  U16 Rdown;
+  U16 vrefdown;
+  U16 vsshiu, vsshid;
+  U16 vpanic = 24;  // Panic Treshold at 24 mV
+  U16 lnup;
+  U16 Rup;
+  U32 vrefup;
+*/
+  vsshid = VssHi + vpanic;
+  //
+  //MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "vsshid = %d  VssHi = %d  vpanic = %d  \n", vsshid, VssHi, vpanic);
+  // Calculate log to backsolve exp. RC decay
+  // Input should be 100x.  Output is 100x
+  //
+  lndown = (U16) MrcNaturalLog ((100 * vsshid) / (vsshid - delta));
+  Rdown = (Outputs->Qclkps * 2000) / (CDIEVSSHI * lndown); // Rdown is 10x.
+  vrefdown = (128 * Rdown) / (Rdown + 10 * RCMDREF);  // Multiple RcmdRef by 10x to match Rdown
+  //
+  //MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "vrefdown = %d  Rdown = %d  lndown = %d  \n", vrefdown, Rdown, lndown);
+  //
+  vsshiu = (Inputs->VccIomV - VssHi - vpanic);  // if VccIO == 1v then VccmV = 1000
+  lnup = (U16) MrcNaturalLog ((100 * vsshiu) / (vsshiu - delta));
+  Rup = (Outputs->Qclkps * 2000) / (CDIEVSSHI * lnup);
+  vrefup = (128 * 10 * RCMDREF) / (10 * RCMDREF + Rup) - 64;
+  //
+  //MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "vrefup = %d  Rup = %d  lnup = %d  vsshiu = %d\n", vrefup, Rup, lnup, vsshiu);
+  //
+  DdrCrCompVssHi.Data          = 0;
+  DdrCrCompVssHi.Bits.VtSlopeA = 4;                   // Apply slope correction of 1.5 to VtComp
+  DdrCrCompVssHi.Bits.VtOffset = (128 * 450 / Inputs->VccIomV / 2); // Apply offset correction to VtComp
+  DdrCrCompVssHi.Bits.PanicDrvUpVref = vrefup;        // Apply Calculated Vref Values
+  DdrCrCompVssHi.Bits.PanicDrvDnVref = vrefdown;
+  MrcWriteCR (MrcData, DDRCOMP_CR_DDRCRCOMPVSSHI_REG, DdrCrCompVssHi.Data);
+  //
+  // MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "DdrCrCompVssHi = 0x%x\n", DdrCrCompVssHi.Data);
+  //
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Init MISC CRs\n");
+  //
+  // Initialize MISC CRs
+  //
+
+  DdrMiscControl.Data                  = MrcReadCR (MrcData, DDRSCRAM_CR_DDRMISCCONTROL0_REG);
+  DdrMiscControl.Bits.WeakLock_Latency = 12;
+  DdrMiscControl.Bits.WL_SleepCycles   = 5;
+  DdrMiscControl.Bits.WL_WakeCycles    = 2;
+  Outputs->MiscControl0                = DdrMiscControl.Data;
+  MrcWriteCR (MrcData, DDRSCRAM_CR_DDRMISCCONTROL0_REG, DdrMiscControl.Data);
+
+  for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+    Offset = DDRSCRAM_CR_DDRSCRAMBLECH0_REG +
+      ((DDRSCRAM_CR_DDRSCRAMBLECH1_REG - DDRSCRAM_CR_DDRSCRAMBLECH0_REG) * Channel);
+    MrcWriteCR (MrcData, Offset, 0);// Keep scrambling disabled for training
+  }
+
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Init KEY MC CRs\n");
+  //
+  // Initialize some key MC CRs
+  //
+  for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+    ChannelOut = &ControllerOut->Channel[Channel];
+
+    //
+    // set the valid rank - Either clear or set only populated so no check for vaid channel
+    //
+    Offset = MCHBAR_CH0_CR_MC_INIT_STATE_REG +
+      ((MCHBAR_CH1_CR_MC_INIT_STATE_REG - MCHBAR_CH0_CR_MC_INIT_STATE_REG) * Channel);
+    MrcWriteCR8 (MrcData, Offset, ChannelOut->ValidRankBitMask);
+  }
+
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Update LS COMP CRs\n");
+
+  //
+  // 1st Disable Perioid Comp and wait for 10us
+  // Set periodic comp = (10uS * 2^COMP_INT)
+  //
+  CrMCompPcu.Data               = 0;
+  CrMCompPcu.Bits.COMP_DISABLE  = 1;
+  CrMCompPcu.Bits.COMP_FORCE    = 1;
+  CrMCompPcu.Bits.COMP_INTERVAL = COMP_INT;  // Set COMP_INT to happen every 10mS
+  MrcWriteCR (MrcData, PCU_CR_M_COMP_PCU_REG, CrMCompPcu.Data);
+  MrcWait (MrcData, 10 * HPET_1US);
+
+  //
+  // Override LevelShifter Compensation to 0x4 (From Hua, 3 is not a valid value)
+  //
+  DataRCompData.Data                  = MrcReadCR (MrcData, DDRDATA_CR_RCOMPDATA1_REG);
+  DataRCompData.Bits.LevelShifterComp = 2;
+  MrcWriteCrMulticast (MrcData, DDRDATA_CR_RCOMPDATA1_REG, DataRCompData.Data);
+  CmdDdrCrCmdComp.Data        = MrcReadCR (MrcData, DDRCMD_CR_DDRCRCMDCOMP_REG);
+  CmdDdrCrCmdComp.Bits.LsComp = 2;
+  MrcWriteCrMulticast (MrcData, DDRCMD_CR_DDRCRCMDCOMP_REG, CmdDdrCrCmdComp.Data);
+  CkeCtlDdrCrCtlComp.Data        = MrcReadCR (MrcData, DDRCKECTL_CR_DDRCRCTLCOMP_REG);
+  CkeCtlDdrCrCtlComp.Bits.LsComp = 2;
+  MrcWriteCrMulticast (MrcData, DDRCKECTL_CR_DDRCRCTLCOMP_REG, CkeCtlDdrCrCtlComp.Data);
+  ClkDdrCrClkComp.Data        = MrcReadCR (MrcData, DDRCLK_CR_DDRCRCLKCOMP_REG);
+  ClkDdrCrClkComp.Bits.LsComp = 2;
+  MrcWriteCrMulticast (MrcData, DDRCLK_CR_DDRCRCLKCOMP_REG, ClkDdrCrClkComp.Data);
+  CompDdrCrDataComp.Data                  = MrcReadCR (MrcData, DDRCOMP_CR_DDRCRDATACOMP1_REG);
+  CompDdrCrDataComp.Bits.LevelShifterComp = 2;
+  MrcWriteCR (MrcData, DDRCOMP_CR_DDRCRDATACOMP1_REG, CompDdrCrDataComp.Data);
+  CompDdrCrCmdComp.Data        = MrcReadCR (MrcData, DDRCOMP_CR_DDRCRCMDCOMP_REG);
+  CompDdrCrCmdComp.Bits.LsComp = 2;
+  MrcWriteCR (MrcData, DDRCOMP_CR_DDRCRCMDCOMP_REG, CompDdrCrCmdComp.Data);
+  CompDdrCrCtlComp.Data        = MrcReadCR (MrcData, DDRCOMP_CR_DDRCRCTLCOMP_REG);
+  CompDdrCrCtlComp.Bits.LsComp = 2;
+  MrcWriteCR (MrcData, DDRCOMP_CR_DDRCRCTLCOMP_REG, CompDdrCrCtlComp.Data);
+  CompDdrCrClkComp.Data        = MrcReadCR (MrcData, DDRCOMP_CR_DDRCRCLKCOMP_REG);
+  CompDdrCrClkComp.Bits.LsComp = 2;
+  MrcWriteCR (MrcData, DDRCOMP_CR_DDRCRCLKCOMP_REG, CompDdrCrClkComp.Data);
+  CompDdrCrCompOvr.Data        = MrcReadCR (MrcData, DDRCOMP_CR_DDRCRCOMPOVR_REG);
+  CompDdrCrCompOvr.Bits.LsComp = 2;
+  MrcWriteCR (MrcData, DDRCOMP_CR_DDRCRCOMPOVR_REG, CompDdrCrCompOvr.Data);
+
+  //
+  // Manually update the comp values
+  //
+  DdrMiscControl.Data                 = Outputs->MiscControl0;
+  DdrMiscControl.Bits.ForceCompUpdate = 1;
+  MrcWriteCR (MrcData, DDRSCRAM_CR_DDRMISCCONTROL0_REG, DdrMiscControl.Data);
+
+  //
+  // Fix Offset between ODT Up/Dn
+  //
+  CompDdrCrDataComp.Data              = MrcReadCR (MrcData, DDRCOMP_CR_DDRCRDATACOMP1_REG);
+  CompDdrCrCompCtl0.Data              = Outputs->CompCtl0;
+  //
+  // Calculate (OdtDn - OdtUp) - Will be BITS 9:4
+  //
+  CompDdrCrCompCtl0.Bits.DqOdtUpDnOff = CompDdrCrDataComp.Bits.RcompOdtDown - CompDdrCrDataComp.Bits.RcompOdtUp;
+  CompDdrCrCompCtl0.Bits.FixOdtD      = 1;  // Enable Fixed Offset between OdtUp/Dn - Will be BIT10
+  Outputs->CompCtl0                   = CompDdrCrCompCtl0.Data;
+  MrcWriteCR (MrcData, DDRCOMP_CR_DDRCRCOMPCTL0_REG, CompDdrCrCompCtl0.Data);
+
+  //
+  // 2X Refresh
+  //
+  if (
+       (Inputs->RefreshRate2x == TRUE) &&
+       (
+         ((CpuModel == cmHSW) && (CpuStepping >= csHswC0)) ||
+         ((CpuModel == cmCRW) && (CpuStepping >= csCrwC0)) ||
+         ((CpuModel == cmHSW_ULT) && (CpuStepping >= csHswUltC0))
+       )
+     ) {
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "*** Enabling 2x Refresh ***\n");
+    AutoSelfRefresh = Outputs->AutoSelfRefresh;
+
+    if ((AutoSelfRefresh == FALSE)
+#ifdef ULT_FLAG
+        || (Lpddr == TRUE)
+#endif
+       ){
+      MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Enabling Mailbox 2x Refresh\n");
+      MrcOemEnable2xRefresh (MrcData);
+    }
+
+    //
+    // Percentage reduction of tREFI needed for ASR and LPDDR cases (Mutually Exclusive).
+    //
+    if (AutoSelfRefresh == TRUE) {
+      RefiReduction = 50;
+    }
+#ifdef ULT_FLAG
+    if (Lpddr == TRUE) {
+      DdrPtmCtl.Data                 = MrcReadCR (MrcData, PCU_CR_DDR_PTM_CTL_PCU_REG);
+      DdrPtmCtl.Bits.DISABLE_DRAM_TS = 0;
+      MrcWriteCR (MrcData, PCU_CR_DDR_PTM_CTL_PCU_REG, DdrPtmCtl.Data);
+      RefiReduction                  = 97;
+    }
+#endif
+
+    if ((Inputs->BootMode == bmCold) && ((AutoSelfRefresh == TRUE)
+#ifdef ULT_FLAG
+        || (Lpddr == TRUE)
+#endif
+       )) {
+      MRC_DEBUG_MSG (
+        Debug,
+        MSG_LEVEL_NOTE,
+        "%s Detected, Reducing tREFI by %u percent.\n",
+        (AutoSelfRefresh == TRUE) ? "Auto Self Refresh" : "LPDDR",
+        RefiReduction
+        );
+      for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+        if (MrcChannelExist (Outputs, Channel)) {
+          ChannelOut = &ControllerOut->Channel[Channel];
+          ChannelOut->Timing[STD_PROFILE].tREFI = (ChannelOut->Timing[STD_PROFILE].tREFI * RefiReduction) / 100;
+          MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "  C(%d).tREFI = 0x%x\n", Channel, ChannelOut->Timing[STD_PROFILE].tREFI);
+          for (Dimm = 0; Dimm < MAX_DIMMS_IN_CHANNEL; Dimm++) {
+            DimmOut = &ChannelOut->Dimm[Dimm];
+            if (DimmOut->Status == DIMM_PRESENT) {
+              DimmOut->Timing[STD_PROFILE].tREFI = (DimmOut->Timing[STD_PROFILE].tREFI * RefiReduction) / 100;
+              MRC_DEBUG_MSG (
+                Debug,
+                MSG_LEVEL_NOTE,
+                "  C(%d).D(%d).tREFI = 0x%x\n",
+                Channel,
+                Dimm,
+                DimmOut->Timing[STD_PROFILE].tREFI
+                );
+            }
+          }
+        }
+      }
+    }
+  }
+
+  //
+  // Set the DDR voltage in PCU
+  //
+  MrcSetPcuDdrVoltage (MrcData, Vdd);
+
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Timing Config\n");
+  MrcTimingConfiguration (MrcData);
+
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Refresh Config\n");
+  MrcRefreshConfiguration (MrcData);
+
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Scheduler parameters\n");
+  MrcSchedulerParametersConfig (MrcData);
+
+  //
+  // this function must be in the end.
+  // if one of the function close channel the function execute this close.
+  //
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Address Decoding Config\n");
+  MrcAdConfiguration (MrcData);
+
+  return Status;
+}
+
+/**
+@brief
+  This function init all the necessary registers for the training.
+
+  @param[in] MrcData - Include all MRC global data.
+
+  @retval mrcSuccess
+**/
+MrcStatus
+MrcPreTraining (
+  IN MrcParameters *const MrcData
+  )
+{
+  MrcOutput                             *Outputs;
+  MrcControllerOut                      *ControllerOut;
+  MrcChannelOut                         *ChannelOut;
+  U32                                   Offset;
+  U8                                    Channel;
+  U8                                    Rank;
+  U8                                    RankMod2;
+  MCDECS_CR_MAD_DIMM_CH0_MCMAIN_STRUCT  CrMadDimmCh;
+  const MrcDebug                        *Debug;
+
+  Debug         = &MrcData->SysIn.Inputs.Debug;
+  Outputs       = &MrcData->SysOut.Outputs;
+  ControllerOut = &Outputs->Controller[0];
+
+  for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+    if (!MrcChannelExist (Outputs, Channel)) {
+      continue;
+    }
+
+    //
+    // Dump the MR registers for DDR3
+    // LPDDR Jedec Init is done after Early Command Training
+    //
+    if (Outputs->DdrType != MRC_DDR_TYPE_LPDDR3) {
+      ChannelOut = &ControllerOut->Channel[Channel];
+
+      for (Rank = 0; Rank < MAX_RANK_IN_CHANNEL; Rank++) {
+        if (!(MrcRankInChannelExist (MrcData, Rank, Channel))) {
+          continue;
+        }
+
+        RankMod2 = Rank % 2;
+        MRC_DEBUG_MSG (
+          Debug,
+          MSG_LEVEL_NOTE,
+          "MrcSetMR0  Channel %u Rank %u = 0x%X\n",
+          Channel,
+          Rank,
+          ChannelOut->Dimm[RANK_TO_DIMM_NUMBER (Rank)].Rank[RankMod2].MR[mrMR0]
+          );
+
+        MRC_DEBUG_MSG (
+          Debug,
+          MSG_LEVEL_NOTE,
+          "MrcSetMR1  Channel %u Rank %u = 0x%X\n",
+          Channel,
+          Rank,
+          ChannelOut->Dimm[RANK_TO_DIMM_NUMBER (Rank)].Rank[RankMod2].MR[mrMR1]
+          );
+
+        MRC_DEBUG_MSG (
+          Debug,
+          MSG_LEVEL_NOTE,
+          "MrcSetMR2  Channel %u Rank %u = 0x%X\n",
+          Channel,
+          Rank,
+          ChannelOut->Dimm[RANK_TO_DIMM_NUMBER (Rank)].Rank[RankMod2].MR[mrMR2]
+          );
+
+        MRC_DEBUG_MSG (
+          Debug,
+          MSG_LEVEL_NOTE,
+          "MrcSetMR3  Channel %u Rank %u = 0x%X\n",
+          Channel,
+          Rank,
+          ChannelOut->Dimm[RANK_TO_DIMM_NUMBER (Rank)].Rank[RankMod2].MR[mrMR3]
+          );
+      }
+    }
+
+    if (Outputs->EccSupport == TRUE) {
+      Offset = MCDECS_CR_MAD_DIMM_CH0_MCMAIN_REG +
+        ((MCDECS_CR_MAD_DIMM_CH1_MCMAIN_REG - MCDECS_CR_MAD_DIMM_CH0_MCMAIN_REG) * Channel);
+      CrMadDimmCh.Data = MrcReadCR (MrcData, Offset);
+      //
+      // set ECC IO ACTIVE ONLY - NOT IO
+      //
+      CrMadDimmCh.Bits.ECC = emEccIoActive;
+      MrcWriteCR (MrcData, Offset, CrMadDimmCh.Data);
+      //
+      // Wait 4 usec after enabling the ECC IO, needed by HW
+      //
+      MrcWait (MrcData, 4 * HPET_1US);
+    }
+  } // for Channel
+
+  //
+  // Set up Write data Buffer before training steps
+  //
+  SetupWDB (MrcData);
+
+  return mrcSuccess;
+}
+
+/**
+
+@brief
+
+  This function initializes all the necessary registers after main training steps but before LCT.
+
+  @param[in] MrcData - Include all MRC global data.
+
+  @retval mrcSuccess
+
+**/
+MrcStatus
+MrcPostTraining (
+  IN MrcParameters *const MrcData
+  )
+{
+  MrcOutput         *Outputs;
+  MrcControllerOut  *ControllerOut;
+  MrcProfile        Profile;
+  U8                Channel;
+
+  Outputs       = &MrcData->SysOut.Outputs;
+  ControllerOut = &Outputs->Controller[0];
+  Profile       = MrcData->SysIn.Inputs.MemoryProfile;
+
+  for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+    if (MrcChannelExist (Outputs, Channel)) {
+      //
+      // Update CmdN timing, Round Trip Latency and tXP
+      // OldN=3, NewN=2*Cmd2N
+      //
+      UpdateCmdNTiming (MrcData, Channel, 2 * 2, (ControllerOut->Channel[Channel].Timing[Profile].NMode == 2) ? 2 : 0);
+    }
+  }
+
+  return mrcSuccess;
+}
+
+/**
+@brief
+  Program PCU_CR_DDR_VOLTAGE register.
+
+  @param[in] MrcData    - Include all MRC global data.
+  @param[in] VddVoltage - Current DDR voltage.
+
+  @retval none
+**/
+void
+MrcSetPcuDdrVoltage (
+  IN OUT MrcParameters *MrcData,
+  IN     MrcVddSelect  VddVoltage
+  )
+{
+  MrcInput                      *Inputs;
+  MrcOutput                     *Outputs;
+  U8                            Data8;
+  PCU_CR_DDR_VOLTAGE_PCU_STRUCT DdrVoltage;
+
+  Inputs  = &MrcData->SysIn.Inputs;
+  Outputs = &MrcData->SysOut.Outputs;
+
+  switch (VddVoltage) {
+    case VDD_1_35:
+      Data8 = 1;
+      break;
+
+    case VDD_1_20:
+      Data8 = 3;  // @todo For single CA bus set this to 2
+      break;
+
+    default:
+      Data8 = 0;
+  }
+
+  MRC_DEBUG_MSG (&Inputs->Debug, MSG_LEVEL_NOTE, "PCU_CR_DDR_VOLTAGE = 0x%02X\n", Data8);
+  DdrVoltage.Data = 0;
+  DdrVoltage.Bits.DDR_VOLTAGE = Data8;
+  MrcWriteCR (MrcData, PCU_CR_DDR_VOLTAGE_PCU_REG, DdrVoltage.Data);
+}
diff --git a/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Services/MrcMemoryMap.c b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Services/MrcMemoryMap.c
new file mode 100644
index 0000000..2fd1310
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Services/MrcMemoryMap.c
@@ -0,0 +1,528 @@
+/** @file
+  The functions in this file initializes the physical memory map.
+
+@copyright
+  Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement.
+
+**/
+
+//
+// Include files
+//
+#include "MrcMemoryMap.h"
+#include "PttHciRegs.h"
+
+/**
+@brief
+  After BIOS determines the total physical memory size.
+  Determines TOM which is defined by the total physical memory size.
+  Determines TOM minus the ME memory size. The ME memory size is calculated from MESEG_BASE and MESEG_MASK.
+  Determines MMIO allocation, which is system configuration dependent.
+
+  Determines TOLUD which is the minimum value by comparing between "4GB minus MMIO size" and "TOM minus ME size".
+  Determines Graphics Stolen Base, BDSM by subtracting the graphics data stolen memory size from TOLUD.
+  Graphics Data Stolen Memory size is given by GMS field in GGC register.  It must be define before this stage.
+  Determines Graphics GTT Stolen Base, BGSM by subtracting the GTT graphics stolen memory size from BDSM.
+  GTT Stolen Memory size is given by GGMS field in GGC register.  It must be define before this stage.
+  Determines TSEG Base, TSEGMB by subtracting TSEG size from BGSM.
+  TSEG should be defined.
+  Remove the memory hole caused by aligning TSEG to a 8MB boundary.
+  Determine whether Memory Reclaim is available.  If "TOM minus ME Stolem Memory Size" is greater than the value of TOLUD, then memory reclaim is available to enable.
+  Determine REMAPBASE if reclaim is enabled.  This is the maximum value by comparing between 4GB and "TOM minus ME size".
+  Determine REMAPLIMIT () if reclaim is enabled.  This is the value of REMAPBASE plus "the difference between the value in TOLUD register and the lower of either 4GB or 'TOM minus ME Stolen memory size", and then minus 1 boundary.
+  Determine TOUUD. TOUUD indicates the address one byte above the maximum DRAM.  If relcaim is disabled, this value is calculated by "TOM minus ME stolen size".  Otherwise, this value is set to REMAPLIMIT plus 1MB.
+
+  @param[in, out] MrcData - Include all MRC global data. include also the memory map data.
+
+  @retval MrcStatus -  if the reset is succeded.
+**/
+MrcStatus
+MrcSetMemoryMap (
+  IN OUT MrcParameters *const MrcData
+  )
+{
+  const MrcDebug          *Debug;
+  const MrcInput          *Inputs;
+  MrcOutput               *Outputs;
+  MrcMemoryMap            *MemoryMap;
+  MRC_PCI_000_GGC_STRUCT  Ggc;
+  U32                     Offset;
+  U32                     TsegBaseOrg;
+  U32                     TsegBaseDelta;
+  U32                     GdxcTop;
+  U32                     FtpmTop;
+  U32                     MmioSize;
+#ifdef PTT_FLAG
+  U32                     PttSts;
+#endif
+
+  Inputs    = &MrcData->SysIn.Inputs;
+  Debug     = &Inputs->Debug;
+  Outputs   = &MrcData->SysOut.Outputs;
+  MemoryMap = &Outputs->MemoryMapData;
+
+  //
+  // Find the total memory size
+  //
+  MrcTotalMemory (MrcData);
+  
+  //
+  // Set TOM register
+  //
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "TOM (Total physical memory size) = %u MB\n", MemoryMap->TotalPhysicalMemorySize);
+
+  //
+  // Find the TOM minus ME size only for internal calculations
+  //
+  MemoryMap->TomMinusMe = MemoryMap->TotalPhysicalMemorySize - Inputs->MeStolenSize;
+
+  MmioSize = Inputs->MmioSize;
+  if (Inputs->MemoryTrace) {
+    if (MemoryMap->TotalPhysicalMemorySize <= MEM_4GB) {
+      MmioSize = MAX (MmioSize, MEM_4GB - MemoryMap->TotalPhysicalMemorySize / 2);
+      MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Adjusted MmioSize = %Xh\n", MmioSize);
+    }
+  }
+  
+  //
+  // Find and set TOLUD.
+  // TOLUD which is the minimum value by comparing between "4GB minus MMIO size" and "TOM minus ME size"
+  //
+  MemoryMap->ToludBase = MIN (MemoryMap->TomMinusMe, MEM_4GB - MmioSize);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "TOLUD base = %Xh\n", MemoryMap->ToludBase);
+
+  //
+  // Find and set BDSM Graphics Stolen Base.
+  // Graphics Stolen Base, BDSM by subtracting the graphics data stolen memory size from TOLUD.
+  //
+  MemoryMap->BdsmBase = MemoryMap->ToludBase - Outputs->GraphicsStolenSize;
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "BDSM base = %Xh\n", MemoryMap->BdsmBase);
+
+  //
+  // Graphics GTT Stolen Base
+  // Graphics GTT Stolen Base, BGSM by subtracting the GTT graphics stolen memory size from BDSM.
+  //
+  MemoryMap->GttBase = MemoryMap->BdsmBase - Outputs->GraphicsGttSize;
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "GTT base = %Xh\n", MemoryMap->GttBase);
+
+  //
+  // Graphics size register init.
+  //
+  Offset = MrcOemGetPcieDeviceAddress (0, 0, 0, MRC_PCI_000_GGC_REG);
+  MrcOemMmioRead (Offset, &Ggc.Data, Inputs->PciEBaseAddress);
+  Ggc.Bits.Vamen  = (Inputs->GfxIsVersatileAcceleration == TRUE) ? 1 : 0;
+  Ggc.Bits.Ggms   = MIN (GGC_GGMS_MAX, Outputs->GraphicsGttSize);
+  //
+  // GMS limitation is 5 bits
+  //
+  if (Outputs->GraphicsStolenSize == 1024) {
+    Ggc.Bits.Gms = 17;
+  } else {
+    Ggc.Bits.Gms = MIN (GGC_GMS_MAX, (Outputs->GraphicsStolenSize / 32));
+  }
+
+  MemoryMap->GraphicsControlRegister = Ggc.Data;
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "GGC value = %Xh\n", MemoryMap->GraphicsControlRegister);
+
+  //
+  // TSEG Base
+  // TSEGMB by subtracting TSEG size from BGSM.
+  //
+  MemoryMap->TsegBase = MemoryMap->GttBase - Inputs->TsegSize;
+  TsegBaseOrg         = MemoryMap->TsegBase;
+
+  //
+  // Dpr size to program DPR register in update MemoryMap
+  //
+  MemoryMap->DprSize = Inputs->DprSize;
+
+  //
+  // SMRR must be aligned at 8MB boundary.
+  // according to this TSEG base need to be also aligned to 8MB boundary.
+  // Round it down to the nearest 8MB boundary.
+  //
+  MemoryMap->TsegBase &= ~(Inputs->TsegSize - 1);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "TSEG base = %Xh\n", MemoryMap->TsegBase);
+
+  //
+  // Remove the hole between top of aligned TSEG and GTT Base:
+  //  1. Calculate Delta = TsegMB - aligned_TsegMB
+  //  2. Walk backwards and adjust BGSM_new = BGSM - DELTA, TOLUD_new = TOLUD - DELTA
+  //
+  TsegBaseDelta = TsegBaseOrg - MemoryMap->TsegBase;
+  if (TsegBaseDelta != 0) {
+    MemoryMap->GttBase   = MemoryMap->GttBase - TsegBaseDelta;
+    MemoryMap->BdsmBase  = MemoryMap->BdsmBase - TsegBaseDelta;
+    MemoryMap->ToludBase = MemoryMap->ToludBase - TsegBaseDelta;
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "GTT base = %Xh\n", MemoryMap->GttBase);
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "BDSM base = %Xh\n", MemoryMap->BdsmBase);
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "TOLUD base = %Xh\n", MemoryMap->ToludBase);
+  }
+  //
+  // test if Reclaim is available
+  // If "TOM minus ME Stolem Memory Size" is greater than the value of TOLUD, then memory reclaim is available to enable
+  //
+  if (Inputs->RemapEnable && (MemoryMap->TomMinusMe > MemoryMap->ToludBase)) {
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Reclaim Enable\n");
+    MemoryMap->ReclaimEnable = TRUE;
+    //
+    // Remap Base
+    // This is the maximum value by comparing between 4GB and "TOM minus ME size".
+    //
+    MemoryMap->RemapBase = MAX (MEM_4GB, MemoryMap->TomMinusMe);
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Remap Base %Xh\n", MemoryMap->RemapBase);
+    //
+    // Remap Limit
+    // This is the value of REMAPBASE plus "the difference between the value in TOLUD register and the lower of either 4GB or 'TOM minus ME Stolen memory size", and then minus 1MB boundary.
+    //
+    MemoryMap->RemapLimit = MemoryMap->RemapBase + (MIN (MEM_4GB, MemoryMap->TomMinusMe) - MemoryMap->ToludBase);
+
+    MemoryMap->TouudBase = MemoryMap->RemapLimit;
+
+    if (!((Inputs->CpuModel == cmHSW) && (Inputs->CpuStepping == csHswA0))) {
+      MemoryMap->RemapLimit -= 0x1;
+    }
+
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Remap Limit %Xh\n", MemoryMap->RemapLimit);
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "TOUUD Base %Xh\n", MemoryMap->TouudBase);
+  } else {
+    MemoryMap->ReclaimEnable = FALSE;
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Reclaim disable \n");
+    //
+    // TOUUD Base
+    // If relcaim is disabled, this value is calculated by "TOM minus ME stolen size".
+    //
+    MemoryMap->TouudBase = MemoryMap->TomMinusMe;
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "TOUUD Base %Xh\n", MemoryMap->TouudBase);
+  }
+  //
+  // GDXC must be aligned to 8MB boundary. But PSMI must be 16MB alligned
+  // GdxcBase by subtracting Gdxc from BGSM.
+  // @todo: GDXC is below DPRBASE if TXT is enabled, which is below TSEG. Maybe it will be required to be placed anywhere below TOLUD.
+  //
+  if (Outputs->Gdxc.GdxcEnable) {
+    if (Inputs->MemoryTrace) {
+      //
+      // Put GDXC at the top of the second channel
+      //
+      if (MemoryMap->TotalPhysicalMemorySize <= MEM_4GB) {
+        GdxcTop = MemoryMap->TouudBase;
+      } else {
+        GdxcTop = MemoryMap->TomMinusMe;
+      }
+    } else {
+      //
+      // Put GDXC below DPR stolen region.
+      //
+      GdxcTop = MemoryMap->TsegBase - Inputs->DprSize;
+    }
+    //
+    // @todo For C-step we can remove the "minus 1MB" W/A
+    //
+    MemoryMap->GdxcMotSize = Outputs->Gdxc.GdxcMotSize << (23 - 20); // In MB
+    MemoryMap->GdxcMotBase = GdxcTop - MemoryMap->GdxcMotSize - 1; // Minus 1 MB - WA for MOT overflow.
+    MemoryMap->GdxcMotBase &= ~(MRC_BIT4 - 1);  // Round down to 16MB boundary
+    
+    MemoryMap->GdxcIotSize = Outputs->Gdxc.GdxcIotSize << (23 - 20); // In MB
+    MemoryMap->GdxcIotBase = MemoryMap->GdxcMotBase - MemoryMap->GdxcIotSize;
+    MemoryMap->GdxcIotBase -= 16; // 16MB for PSMI
+    MRC_DEBUG_MSG (
+      Debug,
+      MSG_LEVEL_NOTE,
+      "GDXC MOT base %Xh, size %d (%Xh) MB\n",
+      MemoryMap->GdxcMotBase,
+      MemoryMap->GdxcMotSize,
+      MemoryMap->GdxcMotSize
+      );
+    MRC_DEBUG_MSG (
+      Debug,
+      MSG_LEVEL_NOTE,
+      "GDXC IOT base %Xh, size %d (%Xh) MB\n",
+      MemoryMap->GdxcIotBase,
+      MemoryMap->GdxcIotSize,
+      MemoryMap->GdxcIotSize
+      );
+    if (Inputs->MemoryTrace) {
+      //
+      // Put fTPM below DPR
+      //
+      FtpmTop = MemoryMap->TsegBase - Inputs->DprSize;
+    } else {
+      //
+      // Put fTPM below GDXC.
+      //
+      FtpmTop = MemoryMap->GdxcIotBase;
+    }
+  } else {
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "GDXC DISABLED\n");
+    FtpmTop = MemoryMap->TsegBase - Inputs->DprSize;
+  }
+  
+#ifdef PTT_FLAG
+  if (Inputs->CpuModel == cmHSW_ULT) {
+    MrcOemMmioRead (R_PTT_HCI_STS, (U32 *) &PttSts, R_PTT_HCI_BASE_ADDRESS);
+    if ((PttSts & B_PTT_HCI_STS_ENABLED) == B_PTT_HCI_STS_ENABLED) {
+      //
+      // fTPM Stolen size is 4KB
+      //
+      MemoryMap->FtpmStolenBase = (FtpmTop << 20) - 0x1000;
+      MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Ftpm Stolen base = %Xh\n", MemoryMap->FtpmStolenBase);
+    }
+  }
+#endif // PTT_FLAG
+
+  MemoryMap->MeStolenBase = MemoryMap->TomMinusMe;
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "ME stolen base %Xh\n", MemoryMap->MeStolenBase);
+
+  MemoryMap->MeStolenSize = Inputs->MeStolenSize;
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "ME stolen size %Xh\n", MemoryMap->MeStolenSize);
+
+  UpdateMemoryMapRegisters (Inputs->PciEBaseAddress, Inputs->GdxcBaseAddress, MemoryMap);
+  return mrcSuccess;
+}
+
+/**
+@brief
+  This function find the total memory in the system.
+  and write it to TotalPhysicalMemorySize in MrcData structure.
+
+  @param[in, out] MrcData - Include all MRC global data.
+
+  @retval Nothing
+**/
+void
+MrcTotalMemory (
+  IN OUT MrcParameters *const MrcData
+  )
+{
+  MrcOutput         *Outputs;
+  MrcControllerOut  *ControllerOut;
+  MrcChannelOut     *ChannelOut;
+  MrcDimmOut        *DimmOut;
+  U8                Controller;
+  U8                Channel;
+  U8                Dimm;
+
+  Outputs = &MrcData->SysOut.Outputs;
+  Outputs->MemoryMapData.TotalPhysicalMemorySize = 0;
+  for (Controller = 0; Controller < MAX_CONTROLLERS; Controller++) {
+    ControllerOut = &Outputs->Controller[Controller];
+    for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+      ChannelOut           = &ControllerOut->Channel[Channel];
+      ChannelOut->Capacity = 0;
+      if (MrcChannelExist (Outputs, Channel)) {
+        for (Dimm = 0; Dimm < MAX_DIMMS_IN_CHANNEL; Dimm++) {
+          DimmOut = &ChannelOut->Dimm[Dimm];
+          if (DimmOut->Status == DIMM_PRESENT) {
+            ChannelOut->Capacity += DimmOut->DimmCapacity;
+          }
+        }
+
+        ChannelOut->Capacity = MIN (ChannelOut->Capacity, Outputs->MrcTotalChannelLimit);
+        Outputs->MemoryMapData.TotalPhysicalMemorySize += ChannelOut->Capacity;
+      }
+    }
+  }
+
+  return;
+}
+
+/**
+@brief
+  this function write to the memory init registers.
+
+  @param[in] PciEBaseAddress - Address of the PCI Express BAR
+  @param[in] GdxcBaseAddress - Address of the GDXC BAR
+  @param[in] MemoryMap       - Include all the memory map definitions
+
+  @retval Nothing
+**/
+void
+UpdateMemoryMapRegisters (
+  IN const U32                 PciEBaseAddress,
+  IN const U32                 GdxcBaseAddress,
+  IN const MrcMemoryMap *const MemoryMap
+  )
+{
+  MRC_PCI_000_TOM_STRUCT        Tom;
+  MRC_PCI_000_TOLUD_STRUCT      Tolud;
+  MRC_PCI_000_TOUUD_STRUCT      Touud;
+  MRC_PCI_000_REMAPBASE_STRUCT  RemapBase;
+  MRC_PCI_000_REMAPLIMIT_STRUCT RemapLimit;
+  MRC_PCI_000_TSEGMB_STRUCT     Tsegmb;
+  MRC_PCI_000_BDSM_STRUCT       Bdsm;
+  MRC_PCI_000_BGSM_STRUCT       Bgsm;
+  MRC_PCI_000_MESEG_BASE_STRUCT MeSegBase;
+  MRC_PCI_000_MESEG_MASK_STRUCT MeSegMask;
+  MRC_PCI_000_DPR_STRUCT        Dpr;
+  U32                           Offset;
+
+  //
+  // Write TOM register
+  //
+  Tom.Data                   = 0;
+  Tom.Data32.Low.Bits.Value  = MemoryMap->TotalPhysicalMemorySize;
+  Tom.Data32.High.Bits.Value = MemoryMap->TotalPhysicalMemorySize >> (32 - TOM_TOM_OFF);
+  Offset                     = MrcOemGetPcieDeviceAddress (0, 0, 0, MRC_PCI_000_TOM_REG);
+  MrcOemMmioWrite (Offset, Tom.Data32.Low.Data, PciEBaseAddress);
+  MrcOemMmioWrite (Offset + 4, Tom.Data32.High.Data, PciEBaseAddress);
+
+  //
+  // Write TOLUD register
+  //
+  Tolud.Data       = 0;
+  Tolud.Bits.Value = MemoryMap->ToludBase;
+  Offset           = MrcOemGetPcieDeviceAddress (0, 0, 0, MRC_PCI_000_TOLUD_REG);
+  MrcOemMmioWrite (Offset, Tolud.Data, PciEBaseAddress);
+
+  //
+  // Write TOUUD register
+  //
+  Touud.Data                   = 0;
+  Touud.Data32.Low.Bits.Value  = MemoryMap->TouudBase;
+  Touud.Data32.High.Bits.Value = MemoryMap->TouudBase >> (32 - TOUUD_TOUUD_OFF);
+  Offset                       = MrcOemGetPcieDeviceAddress (0, 0, 0, MRC_PCI_000_TOUUD_REG);
+  MrcOemMmioWrite (Offset, Touud.Data32.Low.Data, PciEBaseAddress);
+  MrcOemMmioWrite (Offset + 4, Touud.Data32.High.Data, PciEBaseAddress);
+
+  if (MemoryMap->ReclaimEnable) {
+    //
+    // Write REMAPBASE register.
+    //
+    RemapBase.Data                   = 0;
+    RemapBase.Data32.Low.Bits.Value  = MemoryMap->RemapBase;
+    RemapBase.Data32.High.Bits.Value = MemoryMap->RemapBase >> (32 - REMAPBASE_REMAPBASE_OFF);
+    Offset                           = MrcOemGetPcieDeviceAddress (0, 0, 0, MRC_PCI_000_REMAPBASE_REG);
+    MrcOemMmioWrite (Offset, RemapBase.Data32.Low.Data, PciEBaseAddress);
+    MrcOemMmioWrite (Offset + 4, RemapBase.Data32.High.Data, PciEBaseAddress);
+
+    //
+    // Write REMAPLIMIT register.
+    //
+    RemapLimit.Data                   = 0;
+    RemapLimit.Data32.Low.Bits.Value  = MemoryMap->RemapLimit;
+    RemapLimit.Data32.High.Bits.Value = MemoryMap->RemapLimit >> (32 - REMAPLIMIT_REMAPLMT_OFF);
+    Offset                            = MrcOemGetPcieDeviceAddress (0, 0, 0, MRC_PCI_000_REMAPLIMIT_REG);
+    MrcOemMmioWrite (Offset, RemapLimit.Data32.Low.Data, PciEBaseAddress);
+    MrcOemMmioWrite (Offset + 4, RemapLimit.Data32.High.Data, PciEBaseAddress);
+  }
+  //
+  // Write TSEGMB register
+  //
+  Offset            = MrcOemGetPcieDeviceAddress (0, 0, 0, MRC_PCI_000_TSEGMB_REG);
+  Tsegmb.Data       = 0;
+  Tsegmb.Bits.Value = MemoryMap->TsegBase;
+  MrcOemMmioWrite (Offset, Tsegmb.Data, PciEBaseAddress);
+
+  //
+  // Program DPR Register with DPR size & DMA Protection Enabled
+  //
+  if(MemoryMap->DprSize != 0){
+    Offset = MrcOemGetPcieDeviceAddress (0, 0, 0, MRC_PCI_000_DPR_REG);
+    MrcOemMmioRead (Offset, &Dpr.Data, PciEBaseAddress);
+    Dpr.Bits.Dprsize = MemoryMap->DprSize;
+    Dpr.Bits.Epm     = 1;
+    MrcOemMmioWrite (Offset, Dpr.Data, PciEBaseAddress);
+  }
+  //
+  // Write BDSM register
+  //
+  Offset          = MrcOemGetPcieDeviceAddress (0, 0, 0, MRC_PCI_000_BDSM_REG);
+  Bdsm.Data       = 0;
+  Bdsm.Bits.Value = MemoryMap->BdsmBase;
+  MrcOemMmioWrite (Offset, Bdsm.Data, PciEBaseAddress);
+
+  //
+  // Write BGSM register
+  //
+  Offset          = MrcOemGetPcieDeviceAddress (0, 0, 0, MRC_PCI_000_BGSM_REG);
+  Bgsm.Data       = 0;
+  Bgsm.Bits.Value = MemoryMap->GttBase;
+  MrcOemMmioWrite (Offset, Bgsm.Data, PciEBaseAddress);
+
+  //
+  // Enable ME Stolen Memory if the size is not zero
+  //
+  if (MemoryMap->MeStolenSize != 0) {
+    //
+    // Write MESEG_MASK register. Must be written before MESEG_BASE.
+    //
+    MeSegMask.Data                   = 0;
+    MeSegMask.Data32.Low.Bits.Enable = 1;
+    Offset                           = 0x80000 - MemoryMap->MeStolenSize;
+    MeSegMask.Data32.Low.Bits.Value  = Offset;
+    MeSegMask.Data32.High.Bits.Value = Offset >> (32 - MESEG_MASK_MEMASK_OFF);
+    Offset                           = MrcOemGetPcieDeviceAddress (0, 0, 0, MRC_PCI_000_MESEG_MASK_REG);
+    MrcOemMmioWrite (Offset, MeSegMask.Data32.Low.Data, PciEBaseAddress);
+    MrcOemMmioWrite (Offset + 4, MeSegMask.Data32.High.Data, PciEBaseAddress);
+
+    //
+    // Write MESEG_BASE register
+    //
+    MeSegBase.Data                   = 0;
+    MeSegBase.Data32.Low.Bits.Value  = MemoryMap->MeStolenBase;
+    MeSegBase.Data32.High.Bits.Value = MemoryMap->MeStolenBase >> (32 - MESEG_BASE_MEBASE_OFF);
+    Offset                           = MrcOemGetPcieDeviceAddress (0, 0, 0, MRC_PCI_000_MESEG_BASE_REG);
+    MrcOemMmioWrite (Offset, MeSegBase.Data32.Low.Data, PciEBaseAddress);
+    MrcOemMmioWrite (Offset + 4, MeSegBase.Data32.High.Data, PciEBaseAddress);
+  }
+  //
+  // Write graphics control register
+  //
+  Offset = MrcOemGetPcieDeviceAddress (0, 0, 0, MRC_PCI_000_GGC_REG);
+  MrcOemMmioWrite (Offset, MemoryMap->GraphicsControlRegister, PciEBaseAddress);
+
+  //
+  // Program GDXC Registers
+  // 1st MOT: 0x10, 0x14 and 0x18 (Address Low, Address High and Region)
+  // 2nd IOT: 0x20, 0x24 and 0x28 (Address Low, Address High and Region)
+  //
+  MrcOemMmioWrite (
+    MPCOHTRK_CR_GDXC_MOT_ADDRESS_LO_REG,
+    MemoryMap->GdxcMotBase << 14,   // (GdxcMotBase << 20) >> 6, Current Pointer in cache line units
+    GdxcBaseAddress
+    );
+  MrcOemMmioWrite (
+    MPCOHTRK_CR_GDXC_MOT_ADDRESS_HI_REG,
+    (MemoryMap->GdxcMotBase & MRC_BIT18) >> 18, // Bit [18] will be bit [32], so it goes to MOT_ADDRESS_HI.MEM_PTR
+    GdxcBaseAddress
+    );
+  MrcOemMmioWrite (
+    MPCOHTRK_CR_GDXC_MOT_REGION_REG,
+    MemoryMap->GdxcMotBase >> 3 |  // (GdxcMotBase << 20) >> 23, MOT_REGION.START_ADDRESS is bits [38:23]
+    (((MemoryMap->GdxcMotBase + MemoryMap->GdxcMotSize) >> 3) << 16),
+    GdxcBaseAddress
+    );
+    
+  MrcOemMmioWrite (
+    MPCOHTRK_CR_GDXC_OCLA_ADDRESS_LO_REG,
+    MemoryMap->GdxcIotBase << 14,   // (GdxcIotBase << 20) >> 6, Current Pointer in cache line units
+    GdxcBaseAddress
+    );
+  MrcOemMmioWrite (
+    MPCOHTRK_CR_GDXC_OCLA_ADDRESS_HI_REG,
+    MPCOHTRK_CR_GDXC_OCLA_ADDRESS_HI_LOCK_MSK | (MemoryMap->GdxcIotBase & MRC_BIT18) >> 18, // Bit [18] will be bit [32], goes to IOT_ADDRESS_HI.MEM_PTR
+    GdxcBaseAddress
+    );
+  MrcOemMmioWrite (
+    MPCOHTRK_CR_GDXC_OCLA_REGION_REG,
+    MemoryMap->GdxcIotBase >> 3 |  // (GdxcIotBase << 20) >> 23, OCLA_REGION.START_ADDRESS is bits [38:23]
+    (((MemoryMap->GdxcIotBase + MemoryMap->GdxcIotSize) >> 3) << 16),
+    GdxcBaseAddress
+    );
+  return;
+}
diff --git a/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Services/MrcReset.c b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Services/MrcReset.c
new file mode 100644
index 0000000..b51b6f3
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Services/MrcReset.c
@@ -0,0 +1,629 @@
+/** @file
+  The functions in this file implement the DDR3 reset sequence.
+
+@copyright
+  Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement.
+
+**/
+
+//
+// Include files
+//
+#include "MrcReset.h"
+
+/**
+@brief
+  Perform full JEDEC reset and init sequence.
+
+  @param[in] MrcData - Include all MRC global data.
+
+  @retval MrcStatus - mrcSuccess or reason for failure.
+**/
+MrcStatus
+MrcResetSequence (
+  IN MrcParameters *const MrcData
+  )
+{
+  MrcStatus Status;
+  MrcOutput *Outputs;
+#ifdef ULT_FLAG
+  BOOL      Lpddr;
+#endif //ULT_FLAG
+
+  Outputs = &MrcData->SysOut.Outputs;
+
+  //
+  // Start with an IO reset
+  //
+  Status = IoReset (MrcData);
+  if (mrcSuccess == Status) {
+    //
+    // Check if rcomp is done and the ddr ready to use
+    //
+    Status = CheckFirstRcompDone (MrcData);
+    if (mrcSuccess == Status) {
+      //
+      // Perform jedec reset.
+      //
+      // If RTT_NOM is to be enabled in MR1, the ODT input signal must be statically held LOW
+      // in our system RTT_NOM is always enable.
+      // Force ODT low
+      //
+      MrcWriteCR (MrcData, MCSCHEDS_CR_REUT_CH_MISC_ODT_CTRL_REG, MCSCHEDS_CR_REUT_CH_MISC_ODT_CTRL_ODT_Override_MAX);
+
+#ifdef ULT_FLAG
+      //
+      // Check if LPDDR3 memory is used
+      //
+      Lpddr = (MrcData->SysOut.Outputs.DdrType == MRC_DDR_TYPE_LPDDR3);
+
+      if (Lpddr) {
+        Status = MrcJedecResetLpddr3 (MrcData);
+        //
+        // The rest of JEDEC init will be done in a separate step after Early Command Training,
+        // and ECT will set the LpddrEctDone flag.
+        //
+        if (Outputs->LpddrEctDone) {
+          Status = MrcJedecInitLpddr3 (MrcData);
+        }
+        return Status;
+      }
+#endif // ULT_FLAG
+      MrcJedecReset (MrcData);
+
+      //
+      // Initialize the DIMM MRS registers.
+      //
+      //
+      // Step 6 - Set the MR2 for each rank
+      //
+      Status = MrcSetMR2 (MrcData, 0);
+      if (Status == mrcSuccess) {
+        //
+        // Step 7 - Set the MR3 for each rank
+        //
+        Status = MrcSetMR3 (MrcData, 0, 0);
+        if (Status == mrcSuccess) {
+          //
+          // Step 8 - Set the MR1 for each rank
+          //
+          Status = MrcSetMR1 (MrcData, 0, DIMMRON, 0, 0, 0, 0);
+          if (Status == mrcSuccess) {
+            //
+            // Step 9 - Set the MR0 for each rank
+            //
+            Status = MrcSetMR0 (MrcData, 0, 0, 0, 1);
+            if (Status == mrcSuccess) {
+              //
+              // Step 10 - Issue ZQCL command to start ZQ calibration
+              //
+              Status = MrcIssueZQ (MrcData, 0x3, MRC_ZQ_INIT);
+              if (Status == mrcSuccess) {
+                //
+                // If RTT_NOM is to be enabled in MR1, the ODT input signal must be statically held LOW
+                // in our system RTT_NOM is always enable.
+                // Force ODT low
+                //
+                MrcWriteCR (MrcData, MCSCHEDS_CR_REUT_CH_MISC_ODT_CTRL_REG, 0);
+              }
+            }
+          }
+        }
+      }
+    }
+  }
+  //
+  // Set flag to restore from host structure instead from look-up table
+  //
+  Outputs->RestoreMRs = TRUE;
+
+  return Status;
+}
+
+/**
+@brief
+  Perform JEDEC DIMM reset sequence.
+
+  @param[in] MrcData - Include all MRC global data.
+
+  @retval - none
+**/
+void
+MrcJedecReset (
+  IN MrcParameters *const MrcData
+  )
+{
+  MrcInput                                *Inputs;
+  MrcOutput                               *Outputs;
+  MrcControllerOut                        *ControllerOut;
+  U32                                     Offset;
+  U32                                     VddSettleWaitTime;
+  U8                                      Channel;
+  MCDECS_CR_MC_INIT_STATE_G_MCMAIN_STRUCT McInitStateG;
+#ifdef ULT_FLAG
+  U32                                     Rcba;
+  U32                                     PmCfg2;
+#endif // ULT_FLAG
+
+  Inputs            = &MrcData->SysIn.Inputs;
+  Outputs           = &MrcData->SysOut.Outputs;
+  ControllerOut     = &Outputs->Controller[0];
+  VddSettleWaitTime = 200; // 200us is the minimum w/o the delay needed to allow for DDR3L Change
+
+#ifdef ULT_FLAG
+  //
+  // Get the PCH RCBA from 0:1F:0:F0, and clear the Enable bit
+  //
+  Offset = MrcOemGetPcieDeviceAddress (0, 0x1F, 0, 0xF0);
+  MrcOemMmioRead (Offset, &Rcba, Inputs->PciEBaseAddress);
+  Rcba &= (~1);
+
+  if (Inputs->CpuModel == cmHSW_ULT) {
+    //
+    // Deassert DRAM RESET# via PCH regsiter on ULT
+    //
+    MrcOemMmioRead (R_PCH_RCRB_PM_CFG2, &PmCfg2, Rcba);
+    PmCfg2 |= B_PCH_RCRB_PM_CFG2_DRAM_RESET_CTL;
+    MrcOemMmioWrite (R_PCH_RCRB_PM_CFG2, PmCfg2, Rcba);
+  }
+#endif // ULT_FLAG
+
+  McInitStateG.Data                     = 0;
+  McInitStateG.Bits.pu_mrc_done         = MCDECS_CR_MC_INIT_STATE_G_MCMAIN_pu_mrc_done_DEF;
+  McInitStateG.Bits.ddr_reset           = MCDECS_CR_MC_INIT_STATE_G_MCMAIN_ddr_reset_DEF;
+  McInitStateG.Bits.refresh_enable      = MCDECS_CR_MC_INIT_STATE_G_MCMAIN_refresh_enable_DEF;
+  McInitStateG.Bits.mc_init_done_ack    = MCDECS_CR_MC_INIT_STATE_G_MCMAIN_mc_init_done_ack_DEF;
+  McInitStateG.Bits.mrc_done            = MCDECS_CR_MC_INIT_STATE_G_MCMAIN_mrc_done_DEF;
+  McInitStateG.Bits.safe_sr             = MCDECS_CR_MC_INIT_STATE_G_MCMAIN_safe_sr_DEF;
+  McInitStateG.Bits.HVM_Gate_DDR_Reset  = MCDECS_CR_MC_INIT_STATE_G_MCMAIN_HVM_Gate_DDR_Reset_DEF;
+  McInitStateG.Bits.dclk_enable         = MCDECS_CR_MC_INIT_STATE_G_MCMAIN_dclk_enable_DEF;
+  McInitStateG.Bits.reset_io            = MCDECS_CR_MC_INIT_STATE_G_MCMAIN_reset_io_DEF;
+
+  MrcWriteCR (MrcData, MCDECS_CR_MC_INIT_STATE_G_MCMAIN_REG, McInitStateG.Data);
+
+  //
+  // Force CKE low
+  //
+  MrcWriteCR (MrcData, MCSCHEDS_CR_REUT_CH_MISC_CKE_CTRL_REG, MCSCHEDS_CR_REUT_CH_MISC_CKE_CTRL_CKE_Override_MAX);
+
+  //
+  // Assert DIMM reset signal - step 1
+  //
+#ifdef ULT_FLAG
+  if (Inputs->CpuModel == cmHSW_ULT) {
+    PmCfg2 &= ~(B_PCH_RCRB_PM_CFG2_DRAM_RESET_CTL);
+    MrcOemMmioWrite (R_PCH_RCRB_PM_CFG2, PmCfg2, Rcba);
+  } else
+#endif // ULT_FLAG
+  {
+    McInitStateG.Data = MrcReadCR (MrcData, MCDECS_CR_MC_INIT_STATE_G_MCMAIN_REG);  // Read 'MC_Init_State_G' register.
+    McInitStateG.Bits.ddr_reset = 0;
+    MrcWriteCR (MrcData, MCDECS_CR_MC_INIT_STATE_G_MCMAIN_REG, McInitStateG.Data);  // Assert DIMM reset
+  }
+
+  //
+  // Check and Switch DDR3 voltage
+  //
+  if ((Outputs->VddVoltage[Inputs->MemoryProfile] != VDD_INVALID) && (Outputs->VddVoltageDone == FALSE)) {
+    MrcOemVDDVoltageCheckAndSwitch (MrcData, Outputs->VddVoltage[Inputs->MemoryProfile], &VddSettleWaitTime);
+  }
+  //
+  // delay 200 micro sec as jedec ask
+  //
+  MrcWait (MrcData, VddSettleWaitTime * HPET_1US);
+
+  //
+  // De-asserted DIMM reset signal - step 2
+  //
+#ifdef ULT_FLAG
+  if (Inputs->CpuModel == cmHSW_ULT) {
+    PmCfg2 |= B_PCH_RCRB_PM_CFG2_DRAM_RESET_CTL;
+    MrcOemMmioWrite (R_PCH_RCRB_PM_CFG2, PmCfg2, Rcba);
+  } else
+#endif // ULT_FLAG
+  {
+    McInitStateG.Bits.ddr_reset = 1;
+    MrcWriteCR (MrcData, MCDECS_CR_MC_INIT_STATE_G_MCMAIN_REG, McInitStateG.Data);  // De-assert DIMM reset
+  }
+
+  //
+  // delay 500 micro sec as jedec ask
+  //
+  MrcWait (MrcData, 500 * HPET_1US);
+
+  //
+  // Enable the DCLK - step 3
+  //
+  McInitStateG.Bits.dclk_enable = 1;
+  MrcWriteCR (MrcData, MCDECS_CR_MC_INIT_STATE_G_MCMAIN_REG, McInitStateG.Data);
+
+  //
+  // wait the 20 nano sec tCKSRX .
+  //
+  MrcWait (MrcData, 1 * HPET_MIN);  // Minimum is 69.84 ns
+
+  for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+    if (MrcChannelExist (Outputs, Channel)) {
+
+      //
+      // Set the Valid CKE - step 4
+      //
+      Offset = 2 + MCHBAR_CH0_CR_REUT_CH_MISC_CKE_CTRL_REG +
+        ((MCHBAR_CH1_CR_REUT_CH_MISC_CKE_CTRL_REG - MCHBAR_CH0_CR_REUT_CH_MISC_CKE_CTRL_REG) * Channel);
+      MrcWriteCR8 (MrcData, Offset, ControllerOut->Channel[Channel].ValidRankBitMask);
+    }
+  }
+  //
+  // wait minimum of Reset CKE Exit time, tXPR - Step 5
+  //
+  // Spec says max (tXS, 5 tCK). 5 tCK is 10 nsec and minimum using HPET is 69.64ns
+  //
+  MrcWait (MrcData, 1 * HPET_MIN); // Minimum is 69.84 ns
+
+  return;
+}
+
+#ifdef ULT_FLAG
+/**
+@brief
+  Perform JEDEC LPDDR3 DIMM reset sequence.
+
+  @param[in] MrcData - Include all MRC global data.
+
+  @retval mrcSuccess if succeeded
+**/
+MrcStatus
+MrcJedecResetLpddr3 (
+  IN MrcParameters *const MrcData
+  )
+{
+  MrcStatus                               Status;
+  MrcOutput                               *Outputs;
+  MrcControllerOut                        *ControllerOut;
+  U32                                     Offset;
+  U8                                      Channel;
+  U8                                      Rank;
+  MCDECS_CR_MC_INIT_STATE_G_MCMAIN_STRUCT McInitStateG;
+
+  Outputs       = &MrcData->SysOut.Outputs;
+  ControllerOut = &Outputs->Controller[0];
+
+  //
+  // Force CKE low
+  //
+  MrcWriteCR (MrcData, MCSCHEDS_CR_REUT_CH_MISC_CKE_CTRL_REG, MCSCHEDS_CR_REUT_CH_MISC_CKE_CTRL_CKE_Override_MAX);
+
+  //
+  // Wait till voltages are stable
+  //
+  // @todo
+  //  if ((Outputs->VddVoltage[Inputs->MemoryProfile] != VDD_INVALID) && (Outputs->VddVoltageDone == FALSE)) {
+  //    MrcOemVDDVoltageCheckAndSwitch (MrcData, Outputs->VddVoltage[Inputs->MemoryProfile], VddSettleWaitTime);
+  //  }
+  //
+  // Enable the DCLK
+  //
+  McInitStateG.Data             = MrcReadCR (MrcData, MCDECS_CR_MC_INIT_STATE_G_MCMAIN_REG);
+  McInitStateG.Bits.dclk_enable = 1;
+  MrcWriteCR (MrcData, MCDECS_CR_MC_INIT_STATE_G_MCMAIN_REG, McInitStateG.Data);
+
+  //
+  // Wait 20ns before CKE goes high
+  //
+  MrcWait (MrcData, 1 * HPET_MIN);  // Minimum is 69.84 ns
+
+  //
+  // Force CKE high on populated ranks
+  //
+  for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+    if (MrcChannelExist (Outputs, Channel)) {
+
+      //
+      // Set the Valid CKE
+      //
+      Offset = 2 + MCHBAR_CH0_CR_REUT_CH_MISC_CKE_CTRL_REG +
+        ((MCHBAR_CH1_CR_REUT_CH_MISC_CKE_CTRL_REG - MCHBAR_CH0_CR_REUT_CH_MISC_CKE_CTRL_REG) * Channel);
+      MrcWriteCR8 (MrcData, Offset, ControllerOut->Channel[Channel].ValidCkeBitMask);
+    }
+  }
+  //
+  // Delay 200 micro sec per JEDEC requirement
+  // tINIT3 - minimum idle time after first CKE assertion
+  //
+  MrcWait (MrcData, 200 * HPET_1US);
+
+  //
+  // Send the RESET MRW command to populated ranks
+  //
+  for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+    if (MrcChannelExist (Outputs, Channel)) {
+      for (Rank = 0; Rank < MAX_RANK_IN_CHANNEL; Rank++) {
+        if (MrcRankInChannelExist (MrcData, Rank, Channel)) {
+          if (Outputs->LpddrEctDone) {
+            //
+            // Issue a PRECHARGE ALL command to put all banks to idle state.
+            // MRW can only be issued when all banks are idle.
+            //
+            MrcIssuePrechargeAll (MrcData, Channel, 1 << Rank);
+            MrcWait (MrcData, 1 * HPET_1US);
+          }
+
+          Status = MrcIssueMrw (
+                    MrcData,
+                    Channel,
+                    Rank,
+                    0x3F, // Address = 63
+                    0xFC, // Data is selected so that High and Low phases of CA[9:0] are equal
+                    TRUE, // InitMrw
+                    TRUE  // ChipSelect2N
+                    );
+          if (Status != mrcSuccess) {
+            return Status;
+          }
+        }
+      }
+    }
+  }
+  //
+  // tINIT5 - Maximum duration of device auto initialization = 10 us
+  //
+  MrcWait (MrcData, 10 * HPET_1US);
+
+  return mrcSuccess;
+}
+
+typedef struct _MRC_LPDDR_MR_DATA {
+  U8 Address;
+  U8 Data;
+} MRC_LPDDR_MR_DATA;
+
+/**
+@brief
+  Perform JEDEC LPDDR3 DIMM init sequence.
+  1. ZQ Calibration
+  2. Program MR2, MR1, MR3, MR11
+
+  @param[in] MrcData - Include all MRC global data.
+
+  @retval mrcSuccess if succeeded
+**/
+MrcStatus
+MrcJedecInitLpddr3 (
+  IN MrcParameters *const MrcData
+  )
+{
+  MrcStatus         Status;
+  MrcInput          *Inputs;
+  MrcOutput         *Outputs;
+  MrcDebug          *Debug;
+  MrcControllerOut  *ControllerOut;
+  MrcChannelOut     *ChannelOut;
+  U8                Channel;
+  U8                Rank;
+  U32               MrIndex;
+  U8                MrData;
+  U32               Index;
+  MRC_LPDDR_MR_DATA MrTable[] = {
+    {  2, 0x40 }, // MR2:  nWRE = 1, RL & WL depend on frequency
+    {  1, 0x43 }, // MR1:  BL = BL8, nWR = 12
+    {  3, 0x01 }, // MR3:  DS = 34.3 Ohm
+    { 11, 0x00 }  // MR11: ODT
+  };
+
+  Outputs       = &MrcData->SysOut.Outputs;
+  Inputs        = &MrcData->SysIn.Inputs;
+  Debug         = &Inputs->Debug;
+  ControllerOut = &Outputs->Controller[0];
+
+  //
+  // Issue ZQ Init calibration on all channels / ranks
+  //
+  Status = MrcIssueZQ (MrcData, 0x3, MRC_ZQ_INIT);
+  if (Status != mrcSuccess) {
+    return Status;
+  }
+
+  if (Outputs->Frequency <= f800) {
+      MrData = 0x14;
+  } else if (Outputs->Frequency <= f1067) {
+      MrData = 0x16;
+  } else if (Outputs->Frequency <= f1200) {
+      MrData = 0x17;
+  } else if (Outputs->Frequency <= f1333) {
+      MrData = 0x18;
+  } else if (Outputs->Frequency <= f1600) {
+      MrData = 0x1A;
+  } else {
+      MRC_DEBUG_MSG (Debug, MSG_LEVEL_ERROR, "MrcJedecInitLpddr3: Invalid LPDDR frequency!\n");
+      return mrcFrequencyError;
+  }
+
+  MrTable[0].Data = MrData;  // MR2
+
+  for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+    if (!MrcChannelExist (Outputs, Channel)) {
+      continue;
+    }
+
+    ChannelOut = &ControllerOut->Channel[Channel];
+    for (Rank = 0; Rank < MAX_RANK_IN_CHANNEL; Rank++) {
+      if (MrcRankInChannelExist (MrcData, Rank, Channel) == 0) {
+        continue;
+      }
+
+      if ((Rank == 0) && Inputs->LpddrDramOdt) {
+        //
+        // Enable PD Control on Rank 0 only if we have 2 ranks and ODT is used
+        //
+        if (MrcRankInChannelExist (MrcData, 1, Channel)) {
+          MrTable[3].Data = 0x06;  // MR11, ODT Enabled, PD Control = 1
+        } else {
+          MrTable[3].Data = 0x02;  // MR11, ODT Enabled, PD Control = 0
+        }
+      } else {
+        MrTable[3].Data = 0;       // MR11, ODT Disabled
+      }
+
+      //
+      // Send out all the MR commands from the table
+      //
+      for (Index = 0; Index < sizeof (MrTable) / sizeof (MrTable[0]); ++Index) {
+        MrIndex = MrTable[Index].Address;
+
+        if (Outputs->RestoreMRs) {
+          if (MrIndex < MAX_MR_IN_DIMM) {
+            MrData = (U8) ChannelOut->Dimm[0].Rank[Rank % 2].MR[MrIndex];
+          } else {
+            MrData = (U8) ChannelOut->Dimm[0].Rank[Rank % 2].MR11;
+          }
+        } else {
+          //
+          // Save the MR value in the global struct
+          //
+          MrData  = MrTable[Index].Data;
+
+          if (MrIndex < MAX_MR_IN_DIMM) {
+            ChannelOut->Dimm[0].Rank[Rank % 2].MR[MrIndex] = MrData;
+          } else if (MrIndex == mrMR11) {
+            ChannelOut->Dimm[0].Rank[Rank % 2].MR11 = MrData;
+          }
+        }
+
+        Status = MrcIssueMrw (
+                  MrcData,
+                  Channel,
+                  Rank,
+                  MrIndex,
+                  MrData,
+                  FALSE,  // InitMrw
+                  FALSE   // ChipSelect2N
+                  );
+        if (Status != mrcSuccess) {
+          return Status;
+        }
+      }
+      //
+      // @todo: Read MR8 (compare to SPD values) - optional step
+      //
+    }  // for Rank
+  } // for Channel
+
+  Outputs->LpddrJedecInitDone = TRUE;
+  Outputs->RestoreMRs         = TRUE;
+  return Status;
+}
+
+#endif // ULT_FLAG
+
+/**
+@brief
+  Wait in a loop until the first RCOMP has been completed.
+  MRC should wait until this bit is set before executing any DDR command.
+
+  @param[in] MrcData - Include all MRC global data.
+
+  @retval mrcDeviceBusy - On Rcomp completion timeout.
+  @retval mrcSuccess    - On Rcomp completion.
+**/
+MrcStatus
+CheckFirstRcompDone (
+  IN MrcParameters *const MrcData
+  )
+{
+  MCDECS_CR_RCOMP_TIMER_MCMAIN_STRUCT CrRcompTimer;
+  BOOL                                Busy;
+  U32                                 Timeout;
+
+  Timeout = (U32) MrcGetCpuTime () + 10000; // 10 seconds timeout
+
+  do {
+    CrRcompTimer.Data = MrcReadCR (MrcData, MCDECS_CR_RCOMP_TIMER_MCMAIN_REG);
+    Busy              = (0 == CrRcompTimer.Bits.First_Rcomp_done) ? TRUE : FALSE;
+  } while (Busy && ((U32) MrcGetCpuTime () < Timeout));
+
+  return ((Busy) ? mrcDeviceBusy : mrcSuccess);
+}
+
+/**
+@brief
+  Perform the required steps to exit self refresh in S3/Warm reset:
+    Download the Read Reg File for all populated ranks.
+    Assert CKE for all the ranks present to pull DIMMs out of Self-Refresh.
+    Issue long ZQ Calibration for all the ranks present in the channel.
+    Set REUT to normal mode for all channels.
+    Set the Power Down Config Register.
+
+  @param[in] MrcData - Include all MRC global data.
+
+  @retval mrcSuccess
+**/
+MrcStatus
+MrcSelfRefreshExit (
+  IN MrcParameters *const MrcData
+  )
+{
+  const MrcOutput *Outputs;
+  U32             Offset;
+  U8              Channel;
+  U8              Rank;
+  DDRDATACH0_CR_DDRCRDATACONTROL0_STRUCT DdrCrDataControl0;
+
+  Outputs = &MrcData->SysOut.Outputs;
+  //
+  // Download Read Reg File for all populated ranks per channel
+  //
+  for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+    if (MrcChannelExist (Outputs, Channel)) {
+      Offset = DDRDATA0CH0_CR_DDRCRDATACONTROL0_REG +
+        ((DDRDATA0CH1_CR_DDRCRDATACONTROL0_REG - DDRDATA0CH0_CR_DDRCRDATACONTROL0_REG) * Channel);
+      DdrCrDataControl0.Data = MrcReadCR (MrcData, Offset);
+
+      Offset = DDRDATACH0_CR_DDRCRDATACONTROL0_REG +
+        ((DDRDATACH1_CR_DDRCRDATACONTROL0_REG - DDRDATACH0_CR_DDRCRDATACONTROL0_REG) * Channel);
+      DdrCrDataControl0.Bits.ReadRFRd = 1;
+      for (Rank = 0; Rank < MAX_RANK_IN_CHANNEL; Rank++) {
+        if (MrcRankInChannelExist (MrcData, Rank, Channel)) {
+          DdrCrDataControl0.Bits.ReadRFRank = Rank;
+          MrcWriteCrMulticast (MrcData, Offset, DdrCrDataControl0.Data);
+        }
+      }
+    }
+  }
+
+  //
+  // Pull the DIMMs out of self refresh by asserting CKE high.
+  // The time needed to stabilize the DCLK (~6uS) should be covered
+  // by the last 43 MC CR restores after restoring MC_INIT_STATE
+  // in MrcRestoreTrainingValues().
+  //
+  for (Channel = 0; Channel < MAX_CHANNEL; Channel++){
+    if (MrcChannelExist (&MrcData->SysOut.Outputs, Channel)) {
+      Offset = 2 + MCHBAR_CH0_CR_REUT_CH_MISC_CKE_CTRL_REG +
+        ((MCHBAR_CH1_CR_REUT_CH_MISC_CKE_CTRL_REG - MCHBAR_CH0_CR_REUT_CH_MISC_CKE_CTRL_REG) * Channel);
+      MrcWriteCR8 (MrcData, Offset, Outputs->Controller[0].Channel[Channel].ValidRankBitMask);
+    }
+  }
+
+  //
+  // Issue ZQ Long on both channels / all ranks
+  //
+  if (MrcIssueZQ (MrcData, 0x3, MRC_ZQ_LONG) != mrcSuccess) {
+    MRC_DEBUG_MSG (&MrcData->SysIn.Inputs.Debug, MSG_LEVEL_WARNING, "\nZQ Long failed during S3/warm reset\n");
+  }
+
+  return mrcSuccess;
+}
diff --git a/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/SpdProcessing/MrcSpdProcessing.c b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/SpdProcessing/MrcSpdProcessing.c
new file mode 100644
index 0000000..1717d48
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/SpdProcessing/MrcSpdProcessing.c
@@ -0,0 +1,4275 @@
+/** @file
+  By passing in a SPD data structure and platform support values, an output
+  structure is populated with DIMM configuration information.
+
+@copyright
+  Copyright (c) 1999 - 2013 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement.
+
+**/
+
+#include "MrcSpdProcessing.h"
+
+#ifdef MRC_DEBUG_PRINT
+const char        UnknownString[]  = "unknown";
+const char        Ddr3String[]     = "DDR3";
+const char        Ddr4String[]     = "DDR4";
+const char        RdimmString[]    = "RDIMM";
+const char        UdimmString[]    = "UDIMM";
+const char        SodimmString[]   = "SO-DIMM";
+const char        Sodimm72String[] = "72 bit SO-DIMM";
+const char        StdString[]      = "Standard";
+#if (SUPPORT_XMP == SUPPORT)
+const char        Xmp1String[]     = "XMP1";
+const char        Xmp2String[]     = "XMP2";
+const char        XpString[]       = "  XMP profile %u is %sabled and recommended channel config: %u DIMM per channel\n";
+#endif // SUPPORT_XMP
+const char        ErrorString[]    = "ERROR: Unsupported ";
+const char        SpdValString[]   = "SPD value: ";
+const char        IsSupString[]    = " is supported";
+const char        NotSupString[]   = " is not supported";
+const char        TimeBaseString[] = "Timebase (MTB/FTB)";
+const char        tAAString[]      = "CAS Latency Time (tAAmin)";
+const char        tCKString[]      = "SDRAM Cycle Time (tCKmin)";
+const char        tWRString[]      = "Write recovery time (tWRmin)";
+const char        tRCDString[]     = "RAS# to CAS# delay time (tRCDmin)";
+const char        tRRDString[]     = "Row active to row active delay time (tRRDmin)";
+const char        tRPString[]      = "Row precharge delay time (tRPmin)";
+#if (SUPPORT_LPDDR3 == SUPPORT)
+const char        Lpddr3String[]   = "LPDDR3";
+const char        tRPabString[]    = "Row precharge delay time for all banks (tRPab)";
+#endif // SUPPORT_LPDDRn
+const char        tRASString[]     = "Active to precharge delay time (tRASmin)";
+const char        tRCString[]      = "Active to active/refresh delay time (tRCmin)";
+const char        tRFCString[]     = "Refresh recovery delay time (tRFCmin)";
+const char        tWTRString[]     = "Internal write to read command delay time (tWTRmin)";
+const char        tRTPString[]     = "Internal read to precharge delay time (tRTPmin)";
+const char        tFAWString[]     = "Active to active/refresh delay time (tFAWmin)";
+const char        tREFIString[]    = "Average Periodic Refresh Interval (tREFImin)";
+const char        tCWLString[]     = "CAS Write Latency (tCWLmin)";
+const char        NmodeString[]    = "Command rate mode (Nmode)";
+const char        VddString[]      = "Module voltage VDD (mVolts)";
+const char        BestCaseString[] = "Best case value for profiles 0-";
+const char        ProfileString[]  = "Profile";
+const char        HeaderString[]   = "Profile Controller Channel Dimm Value";
+const char        RrcString[][3]   = {
+                                     " A", " B", " C", " D", " E", " F", " G", " H", " J", " K",
+                                     " L", " M", " N", " P", " R", " T", " U", " V", " W", " Y",
+                                     "AA", "AB", "AC", "AD", "AE", "AF", "AG", "AH", "AJ", "AK",
+                                     "AL", "ZZ", "AM", "AN", "AP", "AR", "AT", "AU", "AV", "AW",
+                                     "AY", "BA", "BB", "BC", "BD", "BE", "BF", "BG", "BH", "BJ",
+                                     "BK", "BL", "BM", "BN", "BP", "BR", "BT", "BU", "BV", "BW",
+                                     "BY", "CA", "CB", "ZZ"};
+#endif // MRC_DEBUG_PRINT
+
+const TRangeTable Range[] = {
+  { 0xFFFFFFFF,            fUnSupport, (0 << MRC_REF_CLOCK_133) | (0 << MRC_REF_CLOCK_100) },
+  { MRC_DDR3_800_TCK_MIN,  f800,       (1 << MRC_REF_CLOCK_133) | (1 << MRC_REF_CLOCK_100) },
+  { MRC_DDR3_1000_TCK_MIN, f1000,      (0 << MRC_REF_CLOCK_133) | (1 << MRC_REF_CLOCK_100) },
+  { MRC_DDR3_1067_TCK_MIN, f1067,      (1 << MRC_REF_CLOCK_133) | (0 << MRC_REF_CLOCK_100) },
+  { MRC_DDR3_1200_TCK_MIN, f1200,      (0 << MRC_REF_CLOCK_133) | (1 << MRC_REF_CLOCK_100) },
+  { MRC_DDR3_1333_TCK_MIN, f1333,      (1 << MRC_REF_CLOCK_133) | (0 << MRC_REF_CLOCK_100) },
+  { MRC_DDR3_1400_TCK_MIN, f1400,      (0 << MRC_REF_CLOCK_133) | (1 << MRC_REF_CLOCK_100) },
+  { MRC_DDR3_1600_TCK_MIN, f1600,      (1 << MRC_REF_CLOCK_133) | (1 << MRC_REF_CLOCK_100) },
+  { MRC_DDR3_1800_TCK_MIN, f1800,      (0 << MRC_REF_CLOCK_133) | (1 << MRC_REF_CLOCK_100) },
+  { MRC_DDR3_1867_TCK_MIN, f1867,      (1 << MRC_REF_CLOCK_133) | (0 << MRC_REF_CLOCK_100) },
+  { MRC_DDR3_2000_TCK_MIN, f2000,      (0 << MRC_REF_CLOCK_133) | (1 << MRC_REF_CLOCK_100) },
+  { MRC_DDR3_2133_TCK_MIN, f2133,      (1 << MRC_REF_CLOCK_133) | (0 << MRC_REF_CLOCK_100) },
+  { MRC_DDR3_2200_TCK_MIN, f2200,      (0 << MRC_REF_CLOCK_133) | (1 << MRC_REF_CLOCK_100) },
+  { MRC_DDR3_2400_TCK_MIN, f2400,      (1 << MRC_REF_CLOCK_133) | (1 << MRC_REF_CLOCK_100) },
+  { MRC_DDR3_2600_TCK_MIN, f2600,      (0 << MRC_REF_CLOCK_133) | (1 << MRC_REF_CLOCK_100) },
+  { MRC_DDR3_2667_TCK_MIN, f2667,      (1 << MRC_REF_CLOCK_133) | (0 << MRC_REF_CLOCK_100) },
+  { 0,                     fNoInit,    (0 << MRC_REF_CLOCK_133) | (0 << MRC_REF_CLOCK_100) }
+};
+
+const SupportTable PlatformSupport = {
+  {TRAD_SUPPORT_LPDDR3,    ULT_SUPPORT_LPDDR3   },
+  {TRAD_SUPPORT_COLUMN_10, ULT_SUPPORT_COLUMN_10},
+  {TRAD_SUPPORT_COLUMN_11, ULT_SUPPORT_COLUMN_11},
+  {TRAD_SUPPORT_COLUMN_12, ULT_SUPPORT_COLUMN_12},
+  {TRAD_VDDMINPOSSIBLE,    ULT_VDDMINPOSSIBLE   },
+  {TRAD_VDDMAXPOSSIBLE,    ULT_VDDMAXPOSSIBLE   }
+};
+
+/**
+  @brief
+    Calculate the memory clock value from the current memory frequency.
+
+    @param[in, out] MrcData     - Pointer to MrcData data structure.
+    @param[in]      Frequency   - Memory frequency to convert.
+    @param[out]     tCKminIndex - Pointer to the chosen table index.
+
+    @retval Returns the tCK value for the given frequency.
+**/
+U32
+ConvertFreq2Clock (
+  IN OUT MrcParameters *const MrcData,
+  IN     const MrcFrequency   Frequency,
+  OUT    S32           *const tCKminIndex
+  )
+{
+  U32 tCKminActual;
+  S32 Index;
+
+  tCKminActual = MRC_DDR3_800_TCK_MIN;
+  for (Index = 0; (U32) Index < (sizeof (Range) / sizeof (TRangeTable)); Index++) {
+    if (Frequency == Range[Index].Frequency) {
+      tCKminActual = Range[Index].tCK;
+      break;
+    }
+  }
+  if (tCKminIndex != NULL) {
+    *tCKminIndex = Index;
+  }
+  return (tCKminActual);
+}
+
+/**
+  @brief
+  Calculate the memory frequency from the memory clock value.
+
+    @param[in, out] MrcData     - Pointer to MrcData data structure.
+    @param[in]      RefClk      - The memory reference clock.
+    @param[in]      tCKmin      - The tCKmin value to convert.
+    @param[out]     tCKminIndex - Pointer to the chosen table index.
+
+    @retval Returns the tCK value for the given frequency.
+**/
+static
+U32
+ConvertClock2Freq (
+  IN OUT MrcParameters *const  MrcData,
+  IN     const MrcRefClkSelect RefClk,
+  IN     const U32             tCKmin,
+  OUT    S32           *const  tCKminIndex
+  )
+{
+  MrcOutput     *Outputs;
+  MrcFrequency  Frequency;
+  U32           Index;
+
+  Outputs = &MrcData->SysOut.Outputs;
+
+  //
+  // Convert tCK value to the nearest frequency value.
+  // Then find slowest valid frequency for the given reference clock.
+  //
+  Frequency = fNoInit;
+  for (Index = 0; Index < (sizeof (Range) / sizeof (TRangeTable)) - 1; Index++) {
+    if ((tCKmin <= Range[Index].tCK) && (tCKmin > Range[Index + 1].tCK)) {
+      Frequency = Range[Index].Frequency;
+      break;
+    }
+  }
+
+  while (Index) {
+    if ((Range[Index].RefClkFlag & (1 << RefClk)) == 0) {
+      Frequency = Range[--Index].Frequency;
+    } else {
+      break;
+    }
+  }
+  if (tCKminIndex != NULL) {
+    *tCKminIndex = Index;
+  }
+  return (Frequency);
+}
+
+/**
+  @brief
+  Determine if the DIMM slot is filled.
+    If the SPD structure is all zero's, then DIMM is not present.
+
+    @param[in] MrcData - Pointer to MrcData data structure.
+    @param[in] Spd     - Pointer to Spd data structure.
+    @param[in] Size    - Amount of data, in bytes.
+
+    @retval TRUE on valid value, otherwise FALSE and the value is set to zero.
+**/
+static
+MrcDimmSts
+DimmPresence (
+  IN const MrcParameters *const MrcData,
+  IN const MrcSpd        *const Spd,
+  IN const U32                  Size
+  )
+{
+
+  const U8        *p;
+  U32             count;
+  const MrcDebug  *Debug;
+
+  Debug = &MrcData->SysIn.Inputs.Debug;
+
+  p     = (const U8 *) Spd;
+  count = Size;
+  while (count--) {
+    if (0 != *p++) {
+      return DIMM_PRESENT;
+    }
+  }
+
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_WARNING, "  Warning: No DIMM detected in slot\n");
+  return DIMM_NOT_PRESENT;
+}
+
+/**
+  @brief
+  Determine if the DIMM is valid and supported.
+
+    @param[in, out] MrcData - Pointer to MrcData data structure.
+    @param[in]      Spd     - Pointer to Spd data structure.
+    @param[in, out] DimmOut - Pointer to structure containing DIMM information.
+
+    @retval TRUE on valid value, otherwise FALSE.
+**/
+static
+BOOL
+ValidDimm (
+  IN OUT MrcParameters *const MrcData,
+  IN     const MrcSpd  *const Spd,
+  IN OUT MrcDimmOut    *const DimmOut
+  )
+{
+  const SPD_EXTREME_MEMORY_PROFILE  *Xmp;
+  BOOL                              Status;
+  U8                                DeviceType;
+  MrcCpuModel                       CpuModel;
+  SpdVddFlag                        VddFlag;
+#ifdef MRC_DEBUG_PRINT
+  const U16                         BytesUsedConst[] = {0, 128, 176, 256};
+  const MrcDebug                    *Debug;
+  const char                        *DramTypeString;
+  const char                        *ModuleTypeString;
+  const char                        *ProfileString;
+  SPD_REVISION_STRUCT               Revision;
+  U16                               BytesUsed;
+  U16                               BytesTotal;
+  U16                               CrcCoverage;
+
+  Debug    = &MrcData->SysIn.Inputs.Debug;
+#endif // MRC_DEBUG_PRINT
+
+  Status   = TRUE;
+  CpuModel = MrcData->SysIn.Inputs.CpuModel;
+
+  DeviceType = Spd->Ddr3.General.DramDeviceType.Bits.Type;
+
+  VddFlag.Bits.Vdd1_35 = Spd->Ddr3.General.ModuleNominalVoltage.Bits.OperationAt1_35;
+
+  switch (DeviceType) {
+#if (SUPPORT_DDR3 == SUPPORT)
+  case MRC_SPD_DDR3_SDRAM_TYPE_NUMBER:
+    DimmOut->DdrType    = MRC_DDR_TYPE_DDR3;
+    DimmOut->ModuleType = Spd->Ddr3.General.ModuleType.Bits.ModuleType;
+    Xmp                 = &Spd->Ddr3.Xmp;
+    if ((CpuModel == cmHSW_ULT) && (VddFlag.Bits.Vdd1_35 == 0)) {
+      Status = FALSE;
+#ifdef MRC_DEBUG_PRINT
+      MRC_DEBUG_MSG (Debug, MSG_LEVEL_ERROR, "  DDR3 memory does not support 1.35V operation\n");
+#endif // MRC_DEBUG_PRINT
+    }
+    break;
+#endif // SUPPORT_DDR3
+
+#if (SUPPORT_LPDDR3 == SUPPORT)
+  case MRC_SPD_LPDDR3_SDRAM_TYPE_NUMBER:
+    if ((CpuModel == cmHSW_ULT && PlatformSupport.Lpddr3.UltSupport) ||
+        ((CpuModel == cmHSW || CpuModel == cmCRW) && PlatformSupport.Lpddr3.TradSupport)) {
+      DimmOut->DdrType    = MRC_DDR_TYPE_LPDDR3;
+      DimmOut->ModuleType = Spd->Ddr3.General.ModuleType.Bits.ModuleType;
+      Xmp                 = &Spd->Ddr3.Xmp;
+      break;
+    }
+    // no break;
+#endif // SUPPORT_LPDDR3
+
+
+  default:
+    DimmOut->DdrType    = MRC_DDR_TYPE_UNKNOWN;
+    DimmOut->ModuleType = 0;
+    Xmp                 = NULL;
+    Status              = FALSE;
+    break;
+  }
+
+  if (Status) {
+    switch (DimmOut->ModuleType) {
+#if (SUPPORT_RDIMM == SUPPORT)
+      case MRC_MODULE_TYPE_RDIMM:
+        break;
+#endif
+
+#if (SUPPORT_UDIMM == SUPPORT)
+      case MRC_MODULE_TYPE_UDIMM:
+        break;
+#endif
+
+#if (SUPPORT_SODIMM == SUPPORT)
+      case MRC_MODULE_TYPE_SODIMM:
+      case MRC_MODULE_72B_SO_UDIMM:
+        break;
+#endif
+
+      default:
+        Status = FALSE;
+        break;
+    }
+  }
+
+#if (SUPPORT_XMP == SUPPORT)
+  DimmOut->XmpSupport = 0;
+  if (Status) {
+    if ((XMP_ID_STRING != Xmp->Header.XmpId) ||
+      (0x12 != (Xmp->Header.XmpRevision.Data & 0xFE)) ||
+      ((MrcData->SysIn.Inputs.MemoryProfile == XMP_PROFILE1) && (Xmp->Header.XmpOrgConf.Bits.ProfileEnable1 == 0)) ||
+      ((MrcData->SysIn.Inputs.MemoryProfile == XMP_PROFILE2) && (Xmp->Header.XmpOrgConf.Bits.ProfileEnable2 == 0))) {
+        if ((MrcData->SysIn.Inputs.MemoryProfile == XMP_PROFILE1) || (MrcData->SysIn.Inputs.MemoryProfile == XMP_PROFILE2)) {
+          Status = FALSE;
+        }
+    } else {
+      MrcData->SysOut.Outputs.XmpProfileEnable |= 1;
+    }
+    if (XMP_ID_STRING == Xmp->Header.XmpId) {
+      if (0x12 == (Xmp->Header.XmpRevision.Data & 0xFE)) {
+        DimmOut->XmpRevision = Xmp->Header.XmpRevision.Data;
+      }
+      if (Xmp->Header.XmpOrgConf.Bits.ProfileEnable1 != 0) {
+        DimmOut->XmpSupport |= 1;
+      }
+      if (Xmp->Header.XmpOrgConf.Bits.ProfileEnable2 != 0) {
+        DimmOut->XmpSupport |= 2;
+      }
+    }
+  }
+#endif // SUPPORT_XMP
+
+#ifdef MRC_DEBUG_PRINT
+  switch (MrcData->SysIn.Inputs.MemoryProfile) {
+      case STD_PROFILE:
+      case USER_PROFILE:
+      default:
+        ProfileString = StdString;
+        break;
+#if (SUPPORT_XMP == SUPPORT)
+      case XMP_PROFILE1:
+        ProfileString = Xmp1String;
+        break;
+      case XMP_PROFILE2:
+        ProfileString = Xmp2String;
+        break;
+#endif // SUPPORT_XMP
+  }
+
+  switch (DeviceType) {
+#if (SUPPORT_DDR3 == SUPPORT)
+  case MRC_SPD_DDR3_SDRAM_TYPE_NUMBER:
+    DramTypeString = Ddr3String;
+    BytesTotal    = 256 * Spd->Ddr3.General.Description.Bits.BytesTotal;
+    BytesUsed     = BytesUsedConst[Spd->Ddr3.General.Description.Bits.BytesUsed & 3];
+    CrcCoverage   = 125 - (9 * Spd->Ddr3.General.Description.Bits.CrcCoverage);
+    Revision.Data = Spd->Ddr3.General.Revision.Data;
+    break;
+#endif // SUPPORT_DDR3
+
+#if (SUPPORT_LPDDR3 == SUPPORT)
+  case MRC_SPD_LPDDR3_SDRAM_TYPE_NUMBER:
+    if ((CpuModel == cmHSW_ULT && PlatformSupport.Lpddr3.UltSupport) ||
+        ((CpuModel == cmHSW || CpuModel == cmCRW) && PlatformSupport.Lpddr3.TradSupport)) {
+      DramTypeString = Lpddr3String;
+      BytesTotal    = 256 * Spd->Ddr3.General.Description.Bits.BytesTotal;
+      BytesUsed     = BytesUsedConst[Spd->Ddr3.General.Description.Bits.BytesUsed & 3];
+      CrcCoverage   = 125 - (9 * Spd->Ddr3.General.Description.Bits.CrcCoverage);
+      Revision.Data = Spd->Ddr3.General.Revision.Data;
+      break;
+    }
+    // no break;
+#endif // SUPPORT_LPDDR3
+
+
+  default:
+    DramTypeString = UnknownString;
+    BytesTotal     = 0;
+    BytesUsed      = 0;
+    CrcCoverage    = 0;
+    Revision.Data  = 0;
+    break;
+  }
+
+  switch (DimmOut->ModuleType) {
+#if (SUPPORT_RDIMM == SUPPORT)
+    case MRC_MODULE_TYPE_RDIMM:
+      ModuleTypeString = RdimmString;
+      break;
+#endif // SUPPORT_RDIMM
+
+#if (SUPPORT_UDIMM == SUPPORT)
+    case MRC_MODULE_TYPE_UDIMM:
+      ModuleTypeString = UdimmString;
+      break;
+#endif // SUPPORT_UDIMM
+
+#if (SUPPORT_SODIMM == SUPPORT)
+    case MRC_MODULE_TYPE_SODIMM:
+      ModuleTypeString = SodimmString;
+      break;
+
+    case MRC_MODULE_72B_SO_UDIMM:
+      ModuleTypeString = SodimmString;
+      break;
+#endif // SUPPORT_SODIMM
+
+    default:
+      ModuleTypeString = UnknownString;
+      break;
+  }
+
+  if (Status) {
+    MRC_DEBUG_MSG (
+      Debug,
+      MSG_LEVEL_NOTE,
+      "  %s %s detected, Rev: %u.%u, Size: %u used/%u total, CRC coverage: 0 - %u\n",
+      DramTypeString,
+      ModuleTypeString,
+      Revision.Bits.Major,
+      Revision.Bits.Minor,
+      BytesUsed,
+      BytesTotal,
+      CrcCoverage
+      );
+  } else {
+    MRC_DEBUG_MSG (
+      Debug,
+      MSG_LEVEL_ERROR,
+      "  %s %s detected, SPD Dram type %Xh, module type %Xh\n",
+      DramTypeString,
+      ModuleTypeString,
+      DeviceType,
+      DimmOut->ModuleType
+      );
+  }
+
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "  DIMM profile %s selected\n", ProfileString);
+#if (SUPPORT_XMP == SUPPORT)
+  if (Xmp == NULL) {
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, " Xmp structure is NULL!\n\n");
+  } else {
+    MRC_DEBUG_MSG (
+      Debug,
+      MSG_LEVEL_NOTE,
+      "  XMP String: %Xh, Rev: %u.%u\n",
+      Xmp->Header.XmpId,
+      Xmp->Header.XmpRevision.Bits.Major,
+      Xmp->Header.XmpRevision.Bits.Minor
+    );
+    MRC_DEBUG_MSG (
+      Debug,
+      MSG_LEVEL_NOTE,
+      XpString,
+      1,
+      Xmp->Header.XmpOrgConf.Bits.ProfileEnable1 ? "en" : "dis",
+      Xmp->Header.XmpOrgConf.Bits.ProfileConfig1 + 1
+    );
+    MRC_DEBUG_MSG (
+      Debug,
+      MSG_LEVEL_NOTE,
+      XpString,
+      2,
+      Xmp->Header.XmpOrgConf.Bits.ProfileEnable2 ? "en" : "dis",
+      Xmp->Header.XmpOrgConf.Bits.ProfileConfig2 + 1
+    );
+  }
+#endif // SUPPORT_XMP
+
+#endif // MRC_DEBUG_PRINT
+
+  return Status;
+}
+
+/**
+  @brief
+  Determine if the DIMM SDRAM device width is valid and return the value.
+
+    @param[in, out] MrcData - Pointer to MrcData data structure.
+    @param[in]      Spd     - Pointer to Spd data structure.
+    @param[in, out] DimmOut - Pointer to structure containing DIMM information.
+
+    @retval TRUE on valid value, otherwise FALSE and the value is set to zero.
+**/
+static
+BOOL
+ValidSdramDeviceWidth (
+  IN OUT MrcParameters   *const MrcData,
+  IN const MrcSpd        *const Spd,
+  IN OUT MrcDimmOut      *const DimmOut
+  )
+{
+  const MrcDebug  *Debug;
+
+  Debug = &MrcData->SysIn.Inputs.Debug;
+
+    DimmOut->SdramWidthIndex = Spd->Ddr3.General.ModuleOrganization.Bits.SdramDeviceWidth;
+
+  switch (DimmOut->SdramWidthIndex) {
+#if (SUPPORT_DEVWIDTH_4 == SUPPORT)
+
+  case MRC_SPD_SDRAM_DEVICE_WIDTH_4:
+    DimmOut->SdramWidth = 4;
+    break;
+#endif
+#if (SUPPORT_DEVWIDTH_8 == SUPPORT)
+
+  case MRC_SPD_SDRAM_DEVICE_WIDTH_8:
+    DimmOut->SdramWidth = 8;
+    break;
+#endif
+#if (SUPPORT_DEVWIDTH_16 == SUPPORT)
+
+  case MRC_SPD_SDRAM_DEVICE_WIDTH_16:
+    DimmOut->SdramWidth = 16;
+    break;
+#endif
+#if (SUPPORT_DEVWIDTH_32 == SUPPORT)
+
+  case MRC_SPD_SDRAM_DEVICE_WIDTH_32:
+    DimmOut->SdramWidth = 32;
+    break;
+#endif
+
+  default:
+    DimmOut->SdramWidth = 0;
+    MRC_DEBUG_MSG (Debug,
+      MSG_LEVEL_ERROR,
+      "%sSDRAM device width, %s%Xh\n",
+      ErrorString,
+      SpdValString,
+      DimmOut->SdramWidthIndex
+      );
+    return FALSE;
+  }
+
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "  SDRAM device width: %u\n", DimmOut->SdramWidth);
+  return TRUE;
+}
+
+/**
+  @brief
+  Determine if the DIMM SDRAM row address size is valid and return the value.
+
+    @param[in, out] MrcData - Pointer to MrcData data structure.
+    @param[in]      Spd     - Pointer to Spd data structure.
+    @param[in, out] DimmOut - Pointer to structure containing DIMM information.
+
+    @retval TRUE if the row address size is valid, otherwise FALSE and the value is set to zero.
+**/
+static
+BOOL
+ValidRowSize (
+  IN OUT MrcParameters   *const MrcData,
+  IN const MrcSpd        *const Spd,
+  IN OUT MrcDimmOut      *const DimmOut
+  )
+{
+  U8              RowBits;
+  U8              RowAddress;
+  const MrcDebug  *Debug;
+
+  Debug = &MrcData->SysIn.Inputs.Debug;
+
+    RowAddress = Spd->Ddr3.General.SdramAddressing.Bits.RowAddress;
+
+  switch (RowAddress) {
+#if (SUPPORT_ROW_12 == SUPPORT)
+
+  case MRC_SPD_SDRAM_ROW_12:
+    DimmOut->RowSize = MRC_BIT12;
+    RowBits          = 12;
+    break;
+#endif
+#if (SUPPORT_ROW_13 == SUPPORT)
+
+  case MRC_SPD_SDRAM_ROW_13:
+    DimmOut->RowSize = MRC_BIT13;
+    RowBits          = 13;
+    break;
+#endif
+#if (SUPPORT_ROW_14 == SUPPORT)
+
+  case MRC_SPD_SDRAM_ROW_14:
+    DimmOut->RowSize = MRC_BIT14;
+    RowBits          = 14;
+    break;
+#endif
+#if (SUPPORT_ROW_15 == SUPPORT)
+
+  case MRC_SPD_SDRAM_ROW_15:
+    DimmOut->RowSize = MRC_BIT15;
+    RowBits          = 15;
+    break;
+#endif
+#if (SUPPORT_ROW_16 == SUPPORT)
+
+  case MRC_SPD_SDRAM_ROW_16:
+    DimmOut->RowSize = MRC_BIT16;
+    RowBits          = 16;
+    break;
+#endif
+  default:
+    DimmOut->RowSize = 0;
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_ERROR, "%sSDRAM row size, %s%Xh\n", ErrorString, SpdValString, RowAddress);
+    return FALSE;
+  }
+
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "  Row bits: %u\n", RowBits);
+  return TRUE;
+}
+
+/**
+  @brief
+  Determine if the DIMM SDRAM column address size is valid and return the value.
+
+    @param[in, out] MrcData - Pointer to MrcData data structure.
+    @param[in]      Spd     - Pointer to Spd data structure.
+    @param[in, out] DimmOut - Pointer to structure containing DIMM information.
+
+    @retval TRUE if the column address size is valid, otherwise FALSE and the value is set to zero.
+**/
+static
+BOOL
+ValidColumnSize (
+  IN OUT MrcParameters   *const MrcData,
+  IN const MrcSpd        *const Spd,
+  IN OUT MrcDimmOut      *const DimmOut
+  )
+{
+  const MrcDebug  *Debug;
+  U8              ColumnBits;
+  U8              ColumnAddress;
+  MrcCpuModel     CpuModel;
+
+  Debug    = &MrcData->SysIn.Inputs.Debug;
+  CpuModel = MrcData->SysIn.Inputs.CpuModel;
+
+    ColumnAddress = Spd->Ddr3.General.SdramAddressing.Bits.ColumnAddress;
+
+  switch (ColumnAddress) {
+#if (SUPPORT_COLUMN_9 == SUPPORT)
+  case MRC_SPD_SDRAM_COLUMN_9:
+    DimmOut->ColumnSize = MRC_BIT9;
+    ColumnBits          = 9;
+    break;
+#endif
+
+#if (SUPPORT_COLUMN_10 == SUPPORT)
+  case MRC_SPD_SDRAM_COLUMN_10:
+    if ((CpuModel == cmHSW_ULT && PlatformSupport.Column10.UltSupport) ||
+        ((CpuModel == cmHSW || CpuModel == cmCRW) && PlatformSupport.Column10.TradSupport)) {
+      DimmOut->ColumnSize = MRC_BIT10;
+      ColumnBits          = 10;
+      break;
+    }
+    // no break;
+#endif
+
+#if (SUPPORT_COLUMN_11 == SUPPORT)
+  case MRC_SPD_SDRAM_COLUMN_11:
+    if ((CpuModel == cmHSW_ULT && PlatformSupport.Column11.UltSupport) ||
+        ((CpuModel == cmHSW || CpuModel == cmCRW) && PlatformSupport.Column11.TradSupport)) {
+      DimmOut->ColumnSize = MRC_BIT11;
+      ColumnBits          = 11;
+      break;
+    }
+    // no break;
+#endif
+
+#if (SUPPORT_COLUMN_12 == SUPPORT)
+  case MRC_SPD_SDRAM_COLUMN_12:
+    if ((CpuModel == cmHSW_ULT && PlatformSupport.Column12.UltSupport) ||
+        ((CpuModel == cmHSW || CpuModel == cmCRW) && PlatformSupport.Column12.TradSupport)) {
+      DimmOut->ColumnSize = MRC_BIT12;
+      ColumnBits          = 12;
+      break;
+    }
+    // no break;
+#endif
+
+  default:
+    DimmOut->ColumnSize = 0;
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_ERROR, "%sSDRAM column size, %s%Xh\n", ErrorString, SpdValString, ColumnAddress);
+    return FALSE;
+  }
+
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "  Column bits: %u\n", ColumnBits);
+  return TRUE;
+}
+
+/**
+  @brief
+  Determine if the DIMM SDRAM primary bus width is valid and return the value.
+
+    @param[in, out] MrcData - Pointer to MrcData data structure.
+    @param[in]      Spd     - Pointer to Spd data structure.
+    @param[in, out] DimmOut - Pointer to structure containing DIMM information.
+
+    @retval TRUE on valid value, otherwise FALSE and the value is set to zero.
+**/
+static
+BOOL
+ValidPrimaryWidth (
+  IN OUT MrcParameters   *const MrcData,
+  IN const MrcSpd        *const Spd,
+  IN OUT MrcDimmOut      *const DimmOut
+  )
+{
+  U8              Width;
+  const MrcDebug  *Debug;
+
+  Debug = &MrcData->SysIn.Inputs.Debug;
+
+    Width = Spd->Ddr3.General.ModuleMemoryBusWidth.Bits.PrimaryBusWidth;
+
+  switch (Width) {
+#if (SUPPORT_PRIWIDTH_8 == SUPPORT)
+
+  case MRC_SPD_PRIMARY_BUS_WIDTH_8:
+    DimmOut->PrimaryBusWidth = 8;
+    break;
+#endif
+#if (SUPPORT_PRIWIDTH_16 == SUPPORT)
+
+  case MRC_SPD_PRIMARY_BUS_WIDTH_16:
+    DimmOut->PrimaryBusWidth = 16;
+    break;
+#endif
+#if (SUPPORT_PRIWIDTH_32 == SUPPORT)
+
+  case MRC_SPD_PRIMARY_BUS_WIDTH_32:
+    DimmOut->PrimaryBusWidth = 32;
+    break;
+#endif
+#if (SUPPORT_PRIWIDTH_64 == SUPPORT)
+
+  case MRC_SPD_PRIMARY_BUS_WIDTH_64:
+    DimmOut->PrimaryBusWidth = 64;
+    break;
+#endif
+
+  default:
+    DimmOut->PrimaryBusWidth = 0;
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_ERROR, "%sSDRAM primary bus width, %s%Xh\n", ErrorString, SpdValString, Width);
+    return FALSE;
+    break;
+  }
+
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "  Primary bus width: %u\n", DimmOut->PrimaryBusWidth);
+  return TRUE;
+}
+
+/**
+  Determines if the number of Bank are valid.
+
+    @param[in, out] MrcData - Pointer to MrcData data structure.
+    @param[in]      Spd     - Pointer to Spd data structure.
+    @param[in, out] DimmOut - Pointer to structure containing DIMM information.
+
+    @retval TRUE on valid value, otherwise FALSE.
+**/
+static
+BOOL
+ValidBank (
+  IN OUT MrcParameters  *const MrcData,
+  IN const MrcSpd       *const Spd,
+  IN OUT MrcDimmOut     *const DimmOut
+  )
+{
+  const MrcDebug  *Debug;
+  U8              BankAddress;
+  U8              BankGroup;
+  U8              ValidCheck;
+
+  Debug       = &MrcData->SysIn.Inputs.Debug;
+  ValidCheck  = TRUE;
+      DimmOut->DensityIndex = Spd->Ddr3.General.SdramDensityAndBanks.Bits.Density;
+      BankAddress           = Spd->Ddr3.General.SdramDensityAndBanks.Bits.BankAddress;
+      BankGroup             = 0;
+      switch (BankAddress) {
+#if (SUPPORT_BANK_8 == SUPPORT)
+        case MRC_SPD_DDR3_SDRAM_BANK_8:
+#endif
+#if (SUPPORT_BANK_16 == SUPPORT)
+        case MRC_SPD_DDR3_SDRAM_BANK_16:
+#endif
+#if (SUPPORT_BANK_32 == SUPPORT)
+        case MRC_SPD_DDR3_SDRAM_BANK_32:
+#endif
+#if (SUPPORT_BANK_64 == SUPPORT)
+        case MRC_SPD_DDR3_SDRAM_BANK_64:
+#endif
+#if ((SUPPORT_BANK_8 == SUPPORT) || (SUPPORT_BANK_16 == SUPPORT) || (SUPPORT_BANK_32 == SUPPORT) || (SUPPORT_BANK_64 == SUPPORT))
+          DimmOut->Banks      = MRC_BIT3 << BankAddress;;
+          DimmOut->BankGroups = BankGroup;
+          break;
+#endif
+
+        default:
+          MRC_DEBUG_MSG (
+            Debug,
+            MSG_LEVEL_ERROR,
+            "%sSDRAM number of banks, %s%Xh\n",
+            ErrorString,
+            SpdValString,
+            BankAddress
+            );
+          ValidCheck = FALSE;
+      }
+
+  MRC_DEBUG_MSG (
+    Debug,
+    MSG_LEVEL_NOTE,
+    (TRUE == ValidCheck) ? "  %u Banks in %u groups\n" : "",
+    DimmOut->Banks,
+    DimmOut->BankGroups
+    );
+
+  return ValidCheck;
+}
+
+/**
+  @brief
+  Determine if the number of ranks in the DIMM is valid and return the value.
+
+    @param[in, out] MrcData - Pointer to MrcData data structure.
+    @param[in]      Spd     - Pointer to Spd data structure.
+    @param[in, out] DimmOut - Pointer to structure containing DIMM information.
+
+    @retval TRUE on valid value, otherwise FALSE and the value is set to zero.
+**/
+static
+BOOL
+GetRankCount (
+  IN OUT MrcParameters   *const MrcData,
+  IN const MrcSpd        *const Spd,
+  IN OUT MrcDimmOut      *const DimmOut
+  )
+{
+  const MrcDebug  *Debug;
+  U8              RankCount;
+
+  Debug       = &MrcData->SysIn.Inputs.Debug;
+
+    RankCount = Spd->Ddr3.General.ModuleOrganization.Bits.RankCount;
+
+  DimmOut->RankInDIMM = RankCount + 1;
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "  Ranks: %u\n", DimmOut->RankInDIMM);
+  if (DimmOut->RankInDIMM > MAX_RANK_IN_DIMM) {
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_ERROR, "%snumber of ranks, %s%Xh\n", ErrorString, SpdValString, RankCount);
+    DimmOut->RankInDIMM = 0;
+    return FALSE;
+  }
+
+  return TRUE;
+}
+
+/**
+  @brief
+  Calculate the size of the DIMM, in MBytes.
+
+    @param[in, out] MrcData - Pointer to MrcData data structure.
+    @param[in]      Spd     - Pointer to Spd data structure.
+    @param[in, out] DimmOut - Pointer to structure containing DIMM information.
+
+    @retval TRUE on valid value, otherwise FALSE and the value is set to zero.
+**/
+static
+BOOL
+GetDimmSize (
+  IN OUT MrcParameters   *const MrcData,
+  IN const MrcSpd        *const Spd,
+  IN OUT MrcDimmOut      *const DimmOut
+  )
+{
+  const U32       SdramCapacityTable[] = {
+                  (256 / 8), (512 / 8), (1024 / 8), (2048 / 8),
+                  (4096 / 8), (8192 / 8), (16384 / 8), (32768 / 8)
+                  };
+  U32             DimmSize;
+  const MrcDebug  *Debug;
+
+  Debug = &MrcData->SysIn.Inputs.Debug;
+
+  if ((DimmOut->SdramWidth > 0) && (DimmOut->DensityIndex < (sizeof (SdramCapacityTable) / sizeof (SdramCapacityTable[0])))) {
+    DimmSize = (((SdramCapacityTable[DimmOut->DensityIndex] * DimmOut->PrimaryBusWidth) / DimmOut->SdramWidth) * DimmOut->RankInDIMM);
+    if ((DimmSize >= DIMMSIZEMIN) && (DimmSize <= DIMMSIZEMAX)) {
+      DimmOut->DimmCapacity = DimmSize;
+      MRC_DEBUG_MSG (
+        Debug,
+        MSG_LEVEL_NOTE,
+        "  DIMM size: %u MByte\n",
+        DimmSize
+        );
+      return TRUE;
+    }
+  }
+
+  MRC_DEBUG_MSG (
+    Debug,
+    MSG_LEVEL_ERROR,
+    "%sDIMM size, valid range %u - %u. ",
+    ErrorString,
+    DIMMSIZEMIN,
+    DIMMSIZEMAX
+    );
+  MRC_DEBUG_MSG (
+    Debug,
+    MSG_LEVEL_ERROR,
+    "SDRAM capacity %s%Xh\n",
+    SpdValString,
+    DimmOut->DensityIndex
+    );
+  DimmOut->DimmCapacity = 0;
+  return FALSE;
+}
+
+/**
+  @brief
+  Obtain ECC support Status for this DIMM.
+
+    @param[in, out] MrcData - Pointer to MrcData data structure.
+    @param[in]      Spd     - Pointer to Spd data structure.
+    @param[in, out] DimmOut - Pointer to structure containing DIMM information.
+
+    @retval Returns TRUE.
+**/
+static
+BOOL
+ValidEccSupport (
+  IN OUT MrcParameters   *const MrcData,
+  IN const MrcSpd        *const Spd,
+  IN OUT MrcDimmOut      *const DimmOut
+  )
+{
+#if (SUPPORT_ECC == SUPPORT)
+  U8              BusWidthExtension;
+#endif // SUPPORT_ECC
+  const MrcDebug  *Debug;
+
+  Debug = &MrcData->SysIn.Inputs.Debug;
+
+#if (SUPPORT_ECC == SUPPORT)
+    BusWidthExtension = Spd->Ddr3.General.ModuleMemoryBusWidth.Bits.BusWidthExtension;
+
+  if (MRC_SPD_BUS_WIDTH_EXTENSION_8 == BusWidthExtension) {
+    DimmOut->EccSupport = TRUE;
+  } else
+#endif // SUPPORT_ECC
+  {
+    DimmOut->EccSupport = FALSE;
+  }
+
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "  ECC is %ssupported\n", (DimmOut->EccSupport == FALSE) ? "not " : "");
+  return TRUE;
+}
+
+/**
+  @brief
+  Obtain address mirroring Status for this DIMM.
+
+    @param[in, out] MrcData - Pointer to MrcData data structure.
+    @param[in]      Spd     - Pointer to Spd data structure.
+    @param[in, out] DimmOut - Pointer to structure containing DIMM information.
+
+    @retval Returns TRUE.
+**/
+static
+BOOL
+GetAddressMirror (
+  IN OUT MrcParameters   *const MrcData,
+  IN const MrcSpd        *const Spd,
+  IN OUT MrcDimmOut      *const DimmOut
+  )
+{
+  const MrcDebug  *Debug;
+  U8              MappingRank1;
+
+  Debug             = &MrcData->SysIn.Inputs.Debug;
+
+    MappingRank1 = Spd->Ddr3.Module.Unbuffered.AddressMappingEdgeConn.Bits.MappingRank1;
+  DimmOut->AddressMirrored = (MappingRank1 != 0) ? TRUE : FALSE;
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "  DIMM has %saddress mirroring\n", (DimmOut->AddressMirrored == FALSE) ? "no " : "");
+  return TRUE;
+}
+
+/**
+  @brief
+  Obtain thermal and refresh support for this DIMM.
+
+    @param[in, out] MrcData - Pointer to MrcData data structure.
+    @param[in]      Spd     - Pointer to Spd data structure.
+    @param[in, out] DimmOut - Pointer to structure containing DIMM information.
+
+    @retval Returns TRUE.
+**/
+static
+BOOL
+GetThermalRefreshSupport (
+  IN OUT MrcParameters   *const MrcData,
+  IN const MrcSpd        *const Spd,
+  IN OUT MrcDimmOut      *const DimmOut
+  )
+{
+  const MrcDebug  *Debug;
+  const MrcInput  *Inputs;
+
+  Inputs = &MrcData->SysIn.Inputs;
+  Debug  = &Inputs->Debug;
+    DimmOut->PartialSelfRefresh    = Spd->Ddr3.General.ThermalAndRefreshOptions.Bits.PartialArraySelfRefresh;
+    DimmOut->OnDieThermalSensor    = Spd->Ddr3.General.ThermalAndRefreshOptions.Bits.OnDieThermalSensor;
+    DimmOut->AutoSelfRefresh       = Spd->Ddr3.General.ThermalAndRefreshOptions.Bits.AutoSelfRefresh && Inputs->AutoSelfRefreshSupport;
+    DimmOut->ExtendedTemperRefresh = Spd->Ddr3.General.ThermalAndRefreshOptions.Bits.ExtendedTemperatureRefreshRate;
+    DimmOut->ExtendedTemperRange   = Spd->Ddr3.General.ThermalAndRefreshOptions.Bits.ExtendedTemperatureRange;
+
+  DimmOut->SelfRefreshTemp = ((!DimmOut->AutoSelfRefresh) && (DimmOut->ExtendedTemperRange) && (Inputs->ExtTemperatureSupport)) ? TRUE : FALSE;
+
+  MRC_DEBUG_MSG (Debug,
+    MSG_LEVEL_NOTE,
+    "  Partial Array Self Refresh%s\n",
+    DimmOut->PartialSelfRefresh ? IsSupString : NotSupString);
+  MRC_DEBUG_MSG (Debug,
+    MSG_LEVEL_NOTE,
+    "  On-Die Thermal Sensor Readout%s\n",
+    DimmOut->OnDieThermalSensor ? IsSupString : NotSupString);
+  MRC_DEBUG_MSG (Debug,
+    MSG_LEVEL_NOTE,
+    "  Auto Self Refresh%s\n",
+    DimmOut->AutoSelfRefresh ? IsSupString : NotSupString);
+  MRC_DEBUG_MSG (Debug,
+    MSG_LEVEL_NOTE,
+    "  Extended Temperature Refresh Rate%s\n",
+    DimmOut->ExtendedTemperRefresh ? IsSupString : NotSupString);
+  MRC_DEBUG_MSG (Debug,
+    MSG_LEVEL_NOTE,
+    "  Extended Temperature Range%s\n",
+    DimmOut->ExtendedTemperRange ? IsSupString : NotSupString);
+  return TRUE;
+}
+
+/**
+  @brief
+  Obtain which JEDEC reference design raw card was used as the basis for the DIMM assembly.
+
+    @param[in, out] MrcData - Pointer to MrcData data structure.
+    @param[in]      Spd     - Pointer to Spd data structure.
+    @param[in, out] DimmOut - Pointer to structure containing DIMM information.
+
+    @retval Returns TRUE.
+**/
+static
+BOOL
+GetReferenceRawCardSupport (
+  IN OUT MrcParameters   *const MrcData,
+  IN const MrcSpd        *const Spd,
+  IN OUT MrcDimmOut      *const DimmOut
+  )
+{
+  const MrcDebug  *Debug;
+
+  Debug = &MrcData->SysIn.Inputs.Debug;
+
+  DimmOut->ReferenceRawCard = (Spd->Ddr3.Module.Unbuffered.ReferenceRawCardUsed.Bits.Extension << MRC_SPD_REF_RAW_CARD_SIZE) |
+    Spd->Ddr3.Module.Unbuffered.ReferenceRawCardUsed.Bits.Card;
+
+  MRC_DEBUG_MSG (
+    Debug,
+    MSG_LEVEL_NOTE,
+    "  Reference raw card: %u '%s'\n",
+    DimmOut->ReferenceRawCard,
+    (DimmOut->ReferenceRawCard < (sizeof (RrcString) / sizeof (RrcString[0][0]))) ?
+    RrcString[DimmOut->ReferenceRawCard] : UnknownString
+  );
+  return TRUE;
+}
+
+/**
+  @brief
+  Calculate the CRC16 of the provided SPD data. CRC16 formula is the same
+    one that is used for calculating the CRC16 stored at SPD bytes 126-127.
+    This can be used to detect DIMM change.
+
+    @param[in]  Buffer - Pointer to the start of the data.
+    @param[in]  Size   - Amount of data in the buffer, in bytes.
+    @param[out] Crc    - Pointer to location to write the calculated CRC16 value.
+
+    @retval Returns TRUE.
+**/
+BOOL
+GetDimmCrc (
+  IN  const U8  *const Buffer,
+  IN  const U32        Size,
+  OUT U16       *const Crc
+  )
+{
+  const U8  *Data;
+  U32       Value;
+  U32       Byte;
+  U8        Bit;
+
+  Data  = Buffer;
+  Value = CRC_SEED;
+  for (Byte = 0; Byte < Size; Byte++) {
+    Value ^= (U32) *Data++ << 8;
+    for (Bit = 0; Bit < 8; Bit++) {
+      Value = (Value & MRC_BIT15) ? (Value << 1) ^ CRC_XOR_MASK : Value << 1;
+    }
+  }
+
+  *Crc = (U16) Value;
+  return TRUE;
+}
+
+/**
+  @brief
+  Calculate the medium and fine timebases, using integer math.
+
+    @param[in, out] MrcData - Pointer to MrcData data structure.
+
+    @retval TRUE if medium timebase is valid, otherwise FALSE.
+**/
+static
+BOOL
+GetChannelDimmTimeBase (
+  IN OUT MrcParameters  *const MrcData
+  )
+{
+  const MrcInput        *Inputs;
+  const MrcControllerIn *ControllerIn;
+  const MrcChannelIn    *ChannelIn;
+  const MrcDimmIn       *DimmIn;
+  const MrcSpd          *Spd;
+  const MrcDebug        *Debug;
+  MrcOutput             *Outputs;
+  MrcControllerOut      *ControllerOut;
+  MrcChannelOut         *ChannelOut;
+  MrcDimmOut            *DimmOut;
+  MrcTimeBase           *TimeBase;
+  MrcProfile            Profile;
+  U8                    Controller;
+  U8                    Channel;
+  U8                    Dimm;
+#if ((SUPPORT_XMP == SUPPORT) || (SUPPORT_DDR3 == SUPPORT) || (SUPPORT_LPDDR3 == SUPPORT))
+  U8                        SpdMtbDividend;
+  U8                        SpdMtbDivisor;
+  U8                        SpdFtbDividend;
+  U8                        SpdFtbDivisor;
+#endif
+#if (SUPPORT_XMP == SUPPORT)
+  const SPD_MEDIUM_TIMEBASE *XmpMtb;
+  U32                       Index;
+
+#endif // SUPPORT_XMP
+  Inputs  = &MrcData->SysIn.Inputs;
+  Outputs = &MrcData->SysOut.Outputs;
+  Debug   = &Inputs->Debug;
+
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "  %s:\n  %s\n", TimeBaseString, HeaderString);
+
+  //
+  // Find the smallest timing value for all the given DIMMs, for all the profiles.
+  //
+  for (Profile = STD_PROFILE; Profile < MAX_PROFILE; Profile++) {
+    if (((Profile == XMP_PROFILE1) || (Profile == XMP_PROFILE2)) && (!(Outputs->XmpProfileEnable))) {
+      continue;
+    }
+    for (Controller = 0; Controller < MAX_CONTROLLERS; Controller++) {
+      ControllerIn  = &Inputs->Controller[Controller];
+      ControllerOut = &Outputs->Controller[Controller];
+      for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+        ChannelIn   = &ControllerIn->Channel[Channel];
+        ChannelOut  = &ControllerOut->Channel[Channel];
+        for (Dimm = 0; Dimm < MAX_DIMMS_IN_CHANNEL; Dimm++) {
+          DimmIn  = &ChannelIn->Dimm[Dimm];
+          DimmOut = &ChannelOut->Dimm[Dimm];
+          if (DIMM_PRESENT == DimmOut->Status) {
+            Spd      = &DimmIn->Spd;
+            TimeBase = &ChannelOut->TimeBase[Dimm][Profile];
+            switch (Profile) {
+              case XMP_PROFILE1:
+              case XMP_PROFILE2:
+#if (SUPPORT_XMP == SUPPORT)
+                if (((Profile == XMP_PROFILE1) && ((DimmOut->XmpSupport & 1) != 0)) ||
+                    ((Profile == XMP_PROFILE2) && ((DimmOut->XmpSupport & 2) != 0))) {
+                  Index = Profile - XMP_PROFILE1;
+                    SpdFtbDividend = Spd->Ddr3.Xmp.Header.FineTimeBase.Bits.Dividend;
+                    SpdFtbDivisor  = Spd->Ddr3.Xmp.Header.FineTimeBase.Bits.Divisor;
+                    XmpMtb         = &Spd->Ddr3.Xmp.Header.MediumTimeBase[Index];
+                  SpdMtbDividend = XmpMtb->Dividend.Bits.Dividend;
+                  SpdMtbDivisor  = XmpMtb->Divisor.Bits.Divisor;
+                  TimeBase->Ftb  = ((DimmOut->XmpRevision == 0x12) || (SpdFtbDivisor == 0)) ? 0 : (SpdFtbDividend * MRC_FREQUENCY_FTB_OFFSET) / SpdFtbDivisor;
+                  TimeBase->Mtb  = (SpdMtbDivisor == 0) ? 0 : (SpdMtbDividend * MRC_FREQUENCY_MTB_OFFSET) / SpdMtbDivisor;
+                } else {
+                  TimeBase->Ftb = 0;
+                  TimeBase->Mtb = 0;
+                }
+#endif //SUPPORT_XMP
+                break;
+              case USER_PROFILE:
+              case STD_PROFILE:
+              default:
+                  SpdFtbDividend  = Spd->Ddr3.General.FineTimebase.Bits.Dividend;
+                  SpdFtbDivisor   = Spd->Ddr3.General.FineTimebase.Bits.Divisor;
+                  SpdMtbDividend  = Spd->Ddr3.General.MediumTimebase.Dividend.Bits.Dividend;
+                  SpdMtbDivisor   = Spd->Ddr3.General.MediumTimebase.Divisor.Bits.Divisor;
+                  TimeBase->Ftb = (SpdFtbDivisor == 0) ? 0 : (SpdFtbDividend * MRC_FREQUENCY_FTB_OFFSET) / SpdFtbDivisor;
+                  TimeBase->Mtb = (SpdMtbDivisor == 0) ? 0 : (SpdMtbDividend * MRC_FREQUENCY_MTB_OFFSET) / SpdMtbDivisor;
+                break;
+            } //switch
+
+            MRC_DEBUG_MSG (
+              Debug,
+              MSG_LEVEL_NOTE,
+              "  % 7u % 10u % 8u % 5u % 6u %u\n",
+              Profile,
+              Controller,
+              Channel,
+              Dimm,
+              TimeBase->Mtb,
+              TimeBase->Ftb
+            );
+          } //DimmOut->Status
+        } //Dimm
+      } //Channel
+    } //Controller
+  } //Profile
+
+  return TRUE;
+}
+
+/**
+  @brief
+  Calculate the SDRAM minimum cycle time (tCKmin) that this DIMM supports.
+    Then use the lookup table to obtain the frequency closest to the clock multiple.
+
+    @param[in, out] MrcData - Pointer to MrcData data structure.
+
+    @retval TRUE if the DIMM frequency is supported, otherwise FALSE and the frequency is set to fUnSupport.
+**/
+static
+BOOL
+GetChannelDimmtCK (
+  IN OUT MrcParameters  *const MrcData
+  )
+{
+  const MrcInput        *Inputs;
+  const MrcControllerIn *ControllerIn;
+  const MrcChannelIn    *ChannelIn;
+  const MrcDimmIn       *DimmIn;
+  const MrcSpd          *Spd;
+  const MrcDebug        *Debug;
+  MrcOutput             *Outputs;
+  MrcControllerOut      *ControllerOut;
+  MrcChannelOut         *ChannelOut;
+  MrcDimmOut            *DimmOut;
+  MrcTimeBase           *TimeBase;
+  MrcProfile            Profile;
+  U8                    Controller;
+  U8                    Channel;
+  U8                    Dimm;
+  S32                   MediumTimebase;
+  S32                   FineTimebase;
+  S32                   tCKminMtb;
+  S32                   tCKminFine;
+  U32                   Actual[MAX_PROFILE];
+  U32                   Calculated;
+#if (SUPPORT_XMP == SUPPORT)
+  const SPD_EXTREME_MEMORY_PROFILE_DATA *Data;
+#endif
+
+  Inputs  = &MrcData->SysIn.Inputs;
+  Outputs = &MrcData->SysOut.Outputs;
+  Debug   = &Inputs->Debug;
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "  %s:\n  %s (fs)\n", tCKString, HeaderString);
+
+  //
+  // Find the smallest timing value for all the given DIMMs, for all the profiles.
+  //
+  for (Profile = STD_PROFILE; Profile < MAX_PROFILE; Profile++) {
+    if (((Profile == XMP_PROFILE1) || (Profile == XMP_PROFILE2)) && (!(Outputs->XmpProfileEnable))) {
+      continue;
+    }
+    Actual[Profile] = fNoInit;
+    for (Controller = 0; Controller < MAX_CONTROLLERS; Controller++) {
+      ControllerIn  = &Inputs->Controller[Controller];
+      ControllerOut = &Outputs->Controller[Controller];
+      for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+        ChannelIn   = &ControllerIn->Channel[Channel];
+        ChannelOut  = &ControllerOut->Channel[Channel];
+        for (Dimm = 0; Dimm < MAX_DIMMS_IN_CHANNEL; Dimm++) {
+          DimmIn  = &ChannelIn->Dimm[Dimm];
+          DimmOut = &ChannelOut->Dimm[Dimm];
+          if (DIMM_PRESENT == DimmOut->Status) {
+            Spd            = &DimmIn->Spd;
+            TimeBase       = &ChannelOut->TimeBase[Dimm][Profile];
+            MediumTimebase = TimeBase->Mtb;
+            FineTimebase   = TimeBase->Ftb;
+            Calculated     = 0;
+            switch (Profile) {
+              case XMP_PROFILE1:
+              case XMP_PROFILE2:
+#if (SUPPORT_XMP == SUPPORT)
+                if (((Profile == XMP_PROFILE1) && ((DimmOut->XmpSupport & 1) != 0)) ||
+                    ((Profile == XMP_PROFILE2) && ((DimmOut->XmpSupport & 2) != 0))) {
+                    Data = &Spd->Ddr3.Xmp.Data[Profile - XMP_PROFILE1];
+
+                  tCKminMtb  = Data->tCKmin.Bits.tCKmin;
+                  tCKminFine = (DimmOut->XmpRevision == 0x13) ? Data->tCKminFine.Bits.tCKminFine : 0;
+                  Calculated = (MediumTimebase * tCKminMtb) + (FineTimebase * tCKminFine);
+                  Calculated = MAX (Outputs->MemoryClockMax, Calculated);
+                } else {
+                  Calculated = 0;
+                }
+#endif // SUPPORT_XMP
+                break;
+              case USER_PROFILE:
+                if (Inputs->Ratio > 0) {
+                  Calculated  = MrcRatioToClock (Inputs->Ratio, Outputs->RefClk, Inputs->BClkFrequency);
+                  Calculated = MAX (Outputs->MemoryClockMax, Calculated);
+                  break;
+                } else {
+                  // In AUTO mode, so no break.
+                }
+              case STD_PROFILE:
+              default:
+                    tCKminMtb   = Spd->Ddr3.General.tCKmin.Bits.tCKmin;
+                    tCKminFine  = Spd->Ddr3.General.tCKminFine.Bits.tCKminFine;
+
+                  Calculated = (MediumTimebase * tCKminMtb) + (FineTimebase * tCKminFine);
+                  Calculated = MAX (Outputs->MemoryClockMax, Calculated);
+                break;
+            } //switch
+            Actual[Profile] = MAX (Actual[Profile], Calculated);
+            MRC_DEBUG_MSG (
+              Debug,
+              MSG_LEVEL_NOTE,
+              "  % 7u % 10u % 8u % 5u % 6u\n",
+              Profile,
+              Controller,
+              Channel,
+              Dimm,
+              Calculated
+            );
+          } //DimmOut->Status
+        } //Dimm
+      } //Channel
+    } //Controller
+  } //Profile
+
+  //
+  // Set the best case timing for all controllers/channels/dimms, for each profile.
+  //
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "    %s%u:", BestCaseString, MAX_PROFILE - 1);
+  for (Profile = STD_PROFILE; Profile < MAX_PROFILE; Profile++) {
+    if (((Profile == XMP_PROFILE1) || (Profile == XMP_PROFILE2)) && (!(Outputs->XmpProfileEnable))) {
+      continue;
+    }
+    for (Controller = 0; Controller < MAX_CONTROLLERS; Controller++) {
+      ControllerOut = &Outputs->Controller[Controller];
+      for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+        ChannelOut = &ControllerOut->Channel[Channel];
+        for (Dimm = 0; Dimm < MAX_DIMMS_IN_CHANNEL; Dimm++) {
+          DimmOut = &ChannelOut->Dimm[Dimm];
+          DimmOut->Timing[Profile].tCK    = Actual[Profile];
+          ChannelOut->Timing[Profile].tCK = Actual[Profile];
+        }
+      }
+    }
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, " %u", Actual[Profile]);
+  }
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\n");
+
+  Outputs->MemoryClock = Actual[Inputs->MemoryProfile];
+
+  return TRUE;
+}
+
+/**
+  @brief
+  Calculate the Minimum CAS Latency Time (tAAmin) for the given DIMMs.
+      Step 1: Determine the common set of supported CAS Latency values for all modules
+              on the memory channel using the CAS Latencies Supported in SPD.
+      Step 2: Determine tAAmin(all) which is the largest tAAmin value for all modules on the memory channel.
+      Step 3: Determine tCKmin(all) which is the largest tCKmin value for all
+              the modules on the memory channel (Done in function GetChannelDimmtCK).
+      Step 4: For a proposed tCK value between tCKmin and tCKmax, determine the desired CAS Latency.
+              If tCKproposed is not a standard JEDEC value then tCKproposed must be adjusted to the
+              next lower standard tCK value for calculating CLdesired.
+      Step 5: Chose an actual CAS Latency that is greater than or equal to CLdesired and is
+              supported by all modules on the memory channel as determined in step 1. If no such value exists,
+              choose a higher tCKproposed value and repeat steps 4 and 5 until a solution is found.
+      Step 6: Once the calculation of CLactual is completed, the BIOS must also verify that this CAS
+              Latency value does not exceed tAAmax, which is 20 ns for all DDR3 speed grades.
+              If not, choose a lower CL value and repeat steps 5 and 6 until a solution is found.
+
+    @param[in, out] MrcData - Pointer to MrcData data structure.
+
+    @retval TRUE if the CAS latency has been calculated, otherwise FALSE and the returned value is set to zero.
+**/
+static
+BOOL
+GetChannelDimmtAA (
+  IN OUT MrcParameters  *const MrcData
+  )
+{
+  const MrcInput        *Inputs;
+  const MrcControllerIn *ControllerIn;
+  const MrcChannelIn    *ChannelIn;
+  const MrcDimmIn       *DimmIn;
+  const MrcSpd          *Spd;
+  const MrcDebug        *Debug;
+  MrcOutput             *Outputs;
+  MrcControllerOut      *ControllerOut;
+  MrcChannelOut         *ChannelOut;
+  MrcDimmOut            *DimmOut;
+  MrcProfile            Profile;
+  MrcBool               Found[MAX_PROFILE];
+  MrcBool               UserProfile;
+  MrcBool               tCLOverride;
+  BOOL                  Status;
+  S32                   MediumTimeBase;
+  S32                   FineTimeBase;
+  S32                   tCKminIndex;
+  S32                   tCKmin100;
+  S32                   tCKminIndexSave;
+  S32                   TimingFTB;
+  U32                   TimingMTB;
+  U32                   tCKmin;
+  U32                   CommonCasMask[MAX_PROFILE];
+  U32                   CasMask;
+  U32                   Actual[MAX_PROFILE];
+  U32                   Calculated;
+  U32                   tCLLimitMin;
+  U32                   tCLLimitMax;
+  U8                    Controller;
+  U8                    Channel;
+  U8                    Dimm;
+#if (SUPPORT_XMP == SUPPORT)
+  const SPD_EXTREME_MEMORY_PROFILE_DATA *Data;
+  U32                                   Index;
+#endif
+
+  Inputs         = &MrcData->SysIn.Inputs;
+  Outputs        = &MrcData->SysOut.Outputs;
+  Debug          = &Inputs->Debug;
+  tCKmin         = 0;
+  Calculated     = 0;
+  Status         = FALSE;
+  tCLOverride    = FALSE;
+  MediumTimeBase = 0;
+  FineTimeBase   = 0;
+  TimingMTB      = 0;
+  TimingFTB      = 0;
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "  %s:\n  %s tCL Mask\n", tAAString, HeaderString);
+
+  for (Profile = STD_PROFILE; Profile < MAX_PROFILE; Profile++) {
+    if (((Profile == XMP_PROFILE1) || (Profile == XMP_PROFILE2)) && (!(Outputs->XmpProfileEnable))) {
+      continue;
+    }
+    UserProfile            = (Profile == USER_PROFILE) && (Inputs->MemoryProfile == USER_PROFILE);
+    CommonCasMask[Profile] = ~(0UL);
+    Actual[Profile]        = 0;
+    tCLLimitMin            = 4;
+    tCLLimitMax            = 18;
+    for (Controller = 0; Controller < MAX_CONTROLLERS; Controller++) {
+      ControllerIn  = &Inputs->Controller[Controller];
+      ControllerOut = &Outputs->Controller[Controller];
+      for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+        ChannelIn   = &ControllerIn->Channel[Channel];
+        ChannelOut  = &ControllerOut->Channel[Channel];
+        for (Dimm = 0; Dimm < MAX_DIMMS_IN_CHANNEL; Dimm++) {
+          DimmIn  = &ChannelIn->Dimm[Dimm];
+          DimmOut = &ChannelOut->Dimm[Dimm];
+          if (DIMM_PRESENT == DimmOut->Status) {
+            Spd            = &DimmIn->Spd;
+            tCKmin         = ChannelOut->Dimm[Dimm].Timing[Profile].tCK;
+            MediumTimeBase = ChannelOut->TimeBase[Dimm][Profile].Mtb;
+            FineTimeBase   = ChannelOut->TimeBase[Dimm][Profile].Ftb;
+            CasMask        = 0;
+            switch (Profile) {
+              case XMP_PROFILE1:
+              case XMP_PROFILE2:
+#if (SUPPORT_XMP == SUPPORT)
+                if (((Profile == XMP_PROFILE1) && ((DimmOut->XmpSupport & 1) != 0)) ||
+                    ((Profile == XMP_PROFILE2) && ((DimmOut->XmpSupport & 2) != 0))) {
+                  Index = Profile - XMP_PROFILE1;
+                    Data        = &Spd->Ddr3.Xmp.Data[Index];
+                    tCLLimitMin = 4;
+                    tCLLimitMax = 18;
+                  TimingMTB       = Data->tAAmin.Bits.tAAmin;
+                  TimingFTB       = (DimmOut->XmpRevision == 0x13) ? Data->tAAminFine.Bits.tAAminFine : 0;
+                  CasMask         = Data->CasLatencies.Data & MRC_SPD_CL_SUPPORTED_MASK;
+                  Calculated      = (tCKmin == 0) ? 0 : ((MediumTimeBase * TimingMTB) + (FineTimeBase * TimingFTB) + (tCKmin - 1)) / tCKmin;
+                  Actual[Profile] = MAX (Actual[Profile], Calculated);
+                } else {
+                  Calculated      = 0;
+                }
+#endif // SUPPORT_XMP
+                break;
+
+              case USER_PROFILE:
+                if (DimmIn->Timing.tCL > 0) {
+                  CasMask         = ~(0UL);
+                  Calculated      = DimmIn->Timing.tCL;
+                  Actual[Profile] = MAX (Actual[Profile], Calculated);
+                  tCLOverride     = TRUE;
+                  break;
+                } else {
+                  // In AUTO mode, so no break.
+                }
+
+              case STD_PROFILE:
+              default:
+                  tCLLimitMin = 4;
+                  tCLLimitMax = 18;
+                  TimingMTB   = Spd->Ddr3.General.tAAmin.Bits.tAAmin;
+                  TimingFTB   = Spd->Ddr3.General.tAAminFine.Bits.tAAminFine;
+                  CasMask     = Spd->Ddr3.General.CasLatencies.Data & MRC_SPD_CL_SUPPORTED_MASK;
+                Calculated      = (tCKmin == 0) ? 0 : ((MediumTimeBase * TimingMTB) + (FineTimeBase * TimingFTB) + (tCKmin - 1)) / tCKmin;
+                Actual[Profile] = MAX (Actual[Profile], Calculated);
+                break;
+            } //end switch
+
+            CommonCasMask[Profile] &= CasMask;
+            MRC_DEBUG_MSG (
+              Debug,
+              MSG_LEVEL_NOTE,
+              "  % 7u % 10u % 8u % 5u %6u % 8Xh\n",
+              Profile,
+              Controller,
+              Channel,
+              Dimm,
+              Calculated,
+              CasMask
+              );
+          } //if DimmOut->Status
+        } //for Dimm
+      } //for Channel
+    } //for Controller
+
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "  Profile %u common set of supported CAS Latency values = %Xh\n", Profile, CommonCasMask[Profile]);
+
+    if ((Profile >= XMP_PROFILE1) && (tCKmin == 0)) {
+      continue;
+    }
+
+    Found[Profile] = FALSE;
+    ConvertClock2Freq (MrcData, Outputs->RefClk, tCKmin, &tCKminIndex);
+    if ((Profile >= XMP_PROFILE1) && (Outputs->RefClk == MRC_REF_CLOCK_133) && (Outputs->Capable100)) {
+      ConvertClock2Freq (MrcData, MRC_REF_CLOCK_100, tCKmin, &tCKmin100);
+      if (tCKmin100 > tCKminIndex) {
+        tCKminIndex = tCKmin100;
+        if (Inputs->MemoryProfile == Profile) {
+          Outputs->RefClk = MRC_REF_CLOCK_100;
+        }
+        MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "  Profile%u is RefClk 100 capable, switching to RefClk 100\n", Profile);
+      }
+    }
+    do {
+      for (; !Found[Profile] && (Actual[Profile] <= tCLLimitMax); Actual[Profile]++) {
+        if ((UserProfile) ||
+          ((MRC_BIT0 == ((CommonCasMask[Profile] >> (Actual[Profile] - tCLLimitMin)) & MRC_BIT0)) &&
+          ((Actual[Profile] * tCKmin) <= MRC_TaaMAX))) {
+            Found[Profile] = TRUE;
+            if (Profile == Inputs->MemoryProfile) {
+              Outputs->MemoryClock = tCKmin;
+              Status = TRUE;
+            }
+            for (Controller = 0; Controller < MAX_CONTROLLERS; Controller++) {
+              ControllerOut = &Outputs->Controller[Controller];
+              for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+                ChannelOut = &ControllerOut->Channel[Channel];
+                for (Dimm = 0; Dimm < MAX_DIMMS_IN_CHANNEL; Dimm++) {
+                  DimmOut = &ChannelOut->Dimm[Dimm];
+                  if (DIMM_PRESENT == DimmOut->Status) {
+                    DimmOut->Timing[Profile].tCL    = (U16) Actual[Profile];
+                    ChannelOut->Timing[Profile].tCL = (U16) Actual[Profile];
+                    DimmOut->Timing[Profile].tCK    = tCKmin;
+                    ChannelOut->Timing[Profile].tCK = tCKmin;
+                  } //if
+                } //for Dimm
+              } //for Channel
+            } //for Controller
+            break;
+        } //if
+      } //for Actual[Profile]
+      if (!Found[Profile]) {
+        if (UserProfile && ((Inputs->Ratio > 0) || (tCLOverride == TRUE))) {
+          break;
+        } else {
+          tCKminIndexSave = tCKminIndex;
+          while (--tCKminIndex > 0) {
+            if ((Range[tCKminIndex].RefClkFlag == 3) ||
+               ((Range[tCKminIndex].RefClkFlag == 1) && (Outputs->RefClk == MRC_REF_CLOCK_133)) ||
+               ((Range[tCKminIndex].RefClkFlag == 2) && (Outputs->RefClk == MRC_REF_CLOCK_100))) {
+              tCKmin = Range[tCKminIndex].tCK;
+              ConvertClock2Freq (MrcData, Outputs->RefClk, tCKmin, &tCKminIndex);
+              Actual[Profile] = (tCKmin == 0) ? 0 : ((MediumTimeBase * TimingMTB) + (FineTimeBase * TimingFTB) + (tCKmin - 1)) / tCKmin;
+              MRC_DEBUG_MSG (Debug,
+                MSG_LEVEL_WARNING,
+                "Warning: The memory frequency is being downgraded on profile %u, from %u to %u and the new tCL is %u\n",
+                Profile,
+                Range[tCKminIndexSave].Frequency,
+                Range[tCKminIndex].Frequency,
+                Actual[Profile]);
+              break;
+            }
+          }
+        }
+      }
+    } while (!Found[Profile] && (tCKminIndex > 0));
+  } //for Profile
+
+  Outputs->Frequency = ConvertClock2Freq (MrcData, Outputs->RefClk, Outputs->MemoryClock, NULL);
+
+#ifdef MRC_DEBUG_PRINT
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "    %s%u:", BestCaseString, MAX_PROFILE - 1);
+  for (Profile = STD_PROFILE; Profile < MAX_PROFILE; Profile++) {
+    if (((Profile == XMP_PROFILE1) || (Profile == XMP_PROFILE2)) && (!(Outputs->XmpProfileEnable))) {
+      continue;
+    }
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, " %u", Found[Profile] ? Actual[Profile] : 0);
+  }
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\n  Memory clock = %ufs\n", Outputs->MemoryClock);
+#endif
+
+  return (Status);
+}
+
+/**
+  @brief
+  Calculate the minimum tCWL timing value for the given memory frequency.
+    We calculate timings for all profiles so that this information can be passed out of MRC.
+
+    @param[in, out] MrcData - Pointer to MrcData data structure.
+
+    @retval TRUE if there are DIMMs present, otherwise FALSE.
+**/
+static
+BOOL
+GetChannelDimmtCWL (
+  IN OUT MrcParameters *const MrcData
+  )
+{
+  const MrcInput        *Inputs;
+  const MrcControllerIn *ControllerIn;
+  const MrcChannelIn    *ChannelIn;
+  const MrcDimmIn       *DimmIn;
+  const MrcSpd          *Spd;
+  const MrcDebug        *Debug;
+  MrcOutput             *Outputs;
+  MrcControllerOut      *ControllerOut;
+  MrcChannelOut         *ChannelOut;
+  MrcDimmOut            *DimmOut;
+  MrcTimeBase           *TimeBase;
+  MrcProfile            Profile;
+  U8                    Controller;
+  U8                    Channel;
+  U8                    Dimm;
+  U32                   tCKmin;
+  S32                   MediumTimebase;
+  S32                   FineTimebase;
+  U32                   Actual[MAX_PROFILE];
+  U32                   Calculated;
+  U32                   MaxPossible;
+  U32                   TimingMTB;
+
+  Inputs      = &MrcData->SysIn.Inputs;
+  Outputs     = &MrcData->SysOut.Outputs;
+  Debug       = &Inputs->Debug;
+  MaxPossible = TCWLMAXPOSSIBLE;
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "  %s:\n  %s\n", tCWLString, HeaderString);
+
+  //
+  // Find the smallest timing value for all the given DIMMs, for all the profiles.
+  //
+  for (Profile = STD_PROFILE; Profile < MAX_PROFILE; Profile++) {
+    if (((Profile == XMP_PROFILE1) || (Profile == XMP_PROFILE2)) && (!(Outputs->XmpProfileEnable))) {
+      continue;
+    }
+    Actual[Profile] = 0;
+    for (Controller = 0; Controller < MAX_CONTROLLERS; Controller++) {
+      ControllerIn  = &Inputs->Controller[Controller];
+      ControllerOut = &Outputs->Controller[Controller];
+      for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+        ChannelIn   = &ControllerIn->Channel[Channel];
+        ChannelOut  = &ControllerOut->Channel[Channel];
+        for (Dimm = 0; Dimm < MAX_DIMMS_IN_CHANNEL; Dimm++) {
+          DimmIn  = &ChannelIn->Dimm[Dimm];
+          DimmOut = &ChannelOut->Dimm[Dimm];
+          if (DIMM_PRESENT == DimmOut->Status) {
+            Spd            = &DimmIn->Spd;
+            tCKmin         = DimmOut->Timing[Profile].tCK;
+            TimeBase       = &ChannelOut->TimeBase[Dimm][Profile];
+            MediumTimebase = TimeBase->Mtb;
+            FineTimebase   = TimeBase->Ftb;
+            Calculated     = 0;
+            switch (Profile) {
+              case XMP_PROFILE1:
+              case XMP_PROFILE2:
+#if (SUPPORT_XMP == SUPPORT)
+                if (((Profile == XMP_PROFILE1) && ((DimmOut->XmpSupport & 1) != 0)) ||
+                    ((Profile == XMP_PROFILE2) && ((DimmOut->XmpSupport & 2) != 0))) {
+                      TimingMTB = Spd->Ddr3.Xmp.Data[Profile - XMP_PROFILE1].tCWLmin.Bits.tCWLmin;
+                    Calculated = (tCKmin == 0) ? 0 : ((MediumTimebase * TimingMTB) + (tCKmin - 1)) / tCKmin;
+                } else {
+                  Calculated = 0;
+                }
+#endif // SUPPORT_XMP
+                break;
+              case USER_PROFILE:
+                if (DimmIn->Timing.tCWL > 0) {
+                  Calculated = DimmIn->Timing.tCWL;
+                  break;
+                } else {
+                  // In AUTO mode, so no break.
+                }
+              case STD_PROFILE:
+              default:
+                TimingMTB = 0;
+#if (SUPPORT_LPDDR3 == SUPPORT)
+                if (DimmOut->DdrType == MRC_DDR_TYPE_LPDDR3) {
+                  //
+                  // WL Set A from MR2 spec, adding 1 to take tDQSS into account.
+                  // We will subtract this 1 when programming TC_BANK_RANK_D.tWCL
+                  //
+                  if (tCKmin <= MRC_DDR3_1333_TCK_MIN) {
+                    Calculated = 7;
+                  } else if (tCKmin <= MRC_DDR3_1067_TCK_MIN) {
+                    Calculated = 5;
+                  } else if (tCKmin <= MRC_DDR3_800_TCK_MIN) {
+                    Calculated = 4;
+                  }
+                } else
+#endif // SUPPORT_LPDDR3
+                {
+                  if (tCKmin <= MRC_DDR3_2133_TCK_MIN) {
+                    Calculated = 10;
+                  } else if (tCKmin <= MRC_DDR3_1867_TCK_MIN) {
+                    Calculated = 9;
+                  } else if (tCKmin <= MRC_DDR3_1600_TCK_MIN) {
+                    Calculated = 8;
+                  } else if (tCKmin <= MRC_DDR3_1333_TCK_MIN) {
+                    Calculated = 7;
+                  } else if (tCKmin <= MRC_DDR3_1067_TCK_MIN) {
+                    Calculated = 6;
+                  } else if (tCKmin <= MRC_DDR3_800_TCK_MIN) {
+                    Calculated = 5;
+                  }
+                }
+                break;
+            } //switch
+
+            Calculated = MIN (Calculated, MaxPossible);
+            Actual[Profile] = MAX (Actual[Profile], Calculated);
+            MRC_DEBUG_MSG (
+              Debug,
+              MSG_LEVEL_NOTE,
+              "  % 7u % 10u % 8u % 5u %6u\n",
+              Profile,
+              Controller,
+              Channel,
+              Dimm,
+              Calculated
+            );
+          } //DimmOut->Status
+        } //Dimm
+      } //Channel
+    } //Controller
+  } //Profile
+
+  //
+  // Set the best case timing for all controllers/channels/dimms, for each profile.
+  //
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "    %s%u:", BestCaseString, MAX_PROFILE - 1);
+  for (Profile = STD_PROFILE; Profile < MAX_PROFILE; Profile++) {
+    if (((Profile == XMP_PROFILE1) || (Profile == XMP_PROFILE2)) && (!(Outputs->XmpProfileEnable))) {
+      continue;
+    }
+    for (Controller = 0; Controller < MAX_CONTROLLERS; Controller++) {
+      ControllerOut = &Outputs->Controller[Controller];
+      for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+        ChannelOut = &ControllerOut->Channel[Channel];
+        for (Dimm = 0; Dimm < MAX_DIMMS_IN_CHANNEL; Dimm++) {
+          DimmOut = &ChannelOut->Dimm[Dimm];
+          DimmOut->Timing[Profile].tCWL    = (U16) Actual[Profile];
+          ChannelOut->Timing[Profile].tCWL = (U16) Actual[Profile];
+        }
+      }
+    }
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, " %u", Actual[Profile]);
+  }
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\n");
+
+  return TRUE;
+}
+
+#if (MRC_DDR3_LPDDR_SUPPORTED)
+/**
+  @brief
+  Calculate the minimum tFAW timing value for the given memory frequency.
+
+    @param[in, out] MrcData - Pointer to MrcData data structure.
+
+    @retval TRUE if there are DIMMs present, otherwise FALSE.
+**/
+static
+BOOL
+GetChannelDimmtFAW (
+  IN OUT MrcParameters *const MrcData
+  )
+{
+  const MrcInput        *Inputs;
+  const MrcControllerIn *ControllerIn;
+  const MrcChannelIn    *ChannelIn;
+  const MrcDimmIn       *DimmIn;
+  const MrcSpd          *Spd;
+  const MrcDebug        *Debug;
+  MrcOutput             *Outputs;
+  MrcControllerOut      *ControllerOut;
+  MrcChannelOut         *ChannelOut;
+  MrcDimmOut            *DimmOut;
+  MrcTimeBase           *TimeBase;
+  MrcProfile            Profile;
+  U8                    Controller;
+  U8                    Channel;
+  U8                    Dimm;
+  U32                   tCKmin;
+  U32                   TimingMTB;
+  S32                   MediumTimebase;
+  S32                   FineTimebase;
+  U32                   Actual[MAX_PROFILE];
+  U32                   Calculated;
+#if (SUPPORT_XMP == SUPPORT)
+  const SPD_EXTREME_MEMORY_PROFILE_DATA *Data;
+#endif
+
+  Inputs  = &MrcData->SysIn.Inputs;
+  Outputs = &MrcData->SysOut.Outputs;
+  Debug   = &Inputs->Debug;
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "  %s:\n  %s\n", tFAWString, HeaderString);
+
+  //
+  // Find the smallest timing value for all the given DIMMs, for all the profiles.
+  //
+  for (Profile = STD_PROFILE; Profile < MAX_PROFILE; Profile++) {
+    if (((Profile == XMP_PROFILE1) || (Profile == XMP_PROFILE2)) && (!(Outputs->XmpProfileEnable))) {
+      continue;
+    }
+    Actual[Profile] = 0;
+    for (Controller = 0; Controller < MAX_CONTROLLERS; Controller++) {
+      ControllerIn  = &Inputs->Controller[Controller];
+      ControllerOut = &Outputs->Controller[Controller];
+      for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+        ChannelIn   = &ControllerIn->Channel[Channel];
+        ChannelOut  = &ControllerOut->Channel[Channel];
+        for (Dimm = 0; Dimm < MAX_DIMMS_IN_CHANNEL; Dimm++) {
+          DimmIn  = &ChannelIn->Dimm[Dimm];
+          DimmOut = &ChannelOut->Dimm[Dimm];
+          if (DIMM_PRESENT == DimmOut->Status) {
+            Spd            = &DimmIn->Spd;
+            Calculated     = 0;
+            tCKmin         = DimmOut->Timing[Profile].tCK;
+            TimeBase       = &ChannelOut->TimeBase[Dimm][Profile];
+            MediumTimebase = TimeBase->Mtb;
+            FineTimebase   = TimeBase->Ftb;
+            switch (Profile) {
+              case XMP_PROFILE1:
+              case XMP_PROFILE2:
+#if (SUPPORT_XMP == SUPPORT)
+                if (((Profile == XMP_PROFILE1) && ((DimmOut->XmpSupport & 1) != 0)) ||
+                    ((Profile == XMP_PROFILE2) && ((DimmOut->XmpSupport & 2) != 0))) {
+                  Data       = &Spd->Ddr3.Xmp.Data[Profile - XMP_PROFILE1];
+                  TimingMTB  = ((U32) (Data->tFAWMinUpper.Bits.tFAWminUpper) << 8) | (U32) (Data->tFAWmin.Bits.tFAWmin);
+                  Calculated = (tCKmin == 0) ? 0 : ((MediumTimebase * TimingMTB) + (tCKmin - 1)) / tCKmin;
+                } else {
+                  Calculated = 0;
+                }
+#endif //SUPPORT_XMP
+                break;
+              case USER_PROFILE:
+                if (DimmIn->Timing.tFAW > 0) {
+                  Calculated = DimmIn->Timing.tFAW;
+                  break;
+                } else {
+                  // In AUTO mode, so no break.
+                }
+              case STD_PROFILE:
+              default:
+                if (tCKmin > 0) {
+                    TimingMTB = ((U32) (Spd->Ddr3.General.tFAWMinUpper.Bits.tFAWminUpper) << 8) | (U32) (Spd->Ddr3.General.tFAWmin.Bits.tFAWmin);
+                  Calculated = (tCKmin == 0) ? 0 : ((MediumTimebase * TimingMTB) + (tCKmin - 1)) / tCKmin;
+                }
+                break;
+            } //switch
+
+            Calculated = MIN (Calculated, TFAWMAXPOSSIBLE);
+            Actual[Profile] = MAX (Actual[Profile], Calculated);
+            MRC_DEBUG_MSG (
+              Debug,
+              MSG_LEVEL_NOTE,
+              "  % 7u % 10u % 8u % 5u %6u\n",
+              Profile,
+              Controller,
+              Channel,
+              Dimm,
+              Calculated
+            );
+          } //DimmOut->Status
+        } //Dimm
+      } //Channel
+    } //Controller
+  } //Profile
+
+  //
+  // Set the best case timing for all controllers/channels/dimms, for each profile.
+  //
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "    %s%u:", BestCaseString, MAX_PROFILE - 1);
+  for (Profile = STD_PROFILE; Profile < MAX_PROFILE; Profile++) {
+    if (((Profile == XMP_PROFILE1) || (Profile == XMP_PROFILE2)) && (!(Outputs->XmpProfileEnable))) {
+      continue;
+    }
+    for (Controller = 0; Controller < MAX_CONTROLLERS; Controller++) {
+      ControllerOut = &Outputs->Controller[Controller];
+      for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+        ChannelOut = &ControllerOut->Channel[Channel];
+        for (Dimm = 0; Dimm < MAX_DIMMS_IN_CHANNEL; Dimm++) {
+          DimmOut = &ChannelOut->Dimm[Dimm];
+          DimmOut->Timing[Profile].tFAW    = (U16) Actual[Profile];
+          ChannelOut->Timing[Profile].tFAW = (U16) Actual[Profile];
+        }
+      }
+    }
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, " %u", Actual[Profile]);
+  }
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\n");
+
+  return TRUE;
+}
+#endif
+
+/**
+  @brief
+  Calculate the minimum tRAS timing value for the given memory frequency.
+
+    @param[in, out] MrcData - Pointer to MrcData data structure.
+
+    @retval TRUE if there are DIMMs present, otherwise FALSE.
+**/
+static
+BOOL
+GetChannelDimmtRAS (
+  IN OUT MrcParameters *const MrcData
+  )
+{
+  const MrcInput        *Inputs;
+  const MrcControllerIn *ControllerIn;
+  const MrcChannelIn    *ChannelIn;
+  const MrcDimmIn       *DimmIn;
+  const MrcSpd          *Spd;
+  const MrcDebug        *Debug;
+  MrcOutput             *Outputs;
+  MrcControllerOut      *ControllerOut;
+  MrcChannelOut         *ChannelOut;
+  MrcDimmOut            *DimmOut;
+  MrcTimeBase           *TimeBase;
+  MrcProfile            Profile;
+  U8                    Controller;
+  U8                    Channel;
+  U8                    Dimm;
+  U32                   tCKmin;
+  U32                   TimingMTB;
+  S32                   MediumTimebase;
+  S32                   FineTimebase;
+  U32                   Actual[MAX_PROFILE];
+  U32                   Calculated;
+#if (SUPPORT_XMP == SUPPORT)
+  const SPD_EXTREME_MEMORY_PROFILE_DATA *Data;
+  U32                                   Index;
+#endif
+
+  Inputs  = &MrcData->SysIn.Inputs;
+  Outputs = &MrcData->SysOut.Outputs;
+  Debug   = &Inputs->Debug;
+
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "  %s:\n  %s\n", tRASString, HeaderString);
+
+  //
+  // Find the smallest timing value for all the given DIMMs, for all the profiles.
+  //
+  for (Profile = STD_PROFILE; Profile < MAX_PROFILE; Profile++) {
+    if (((Profile == XMP_PROFILE1) || (Profile == XMP_PROFILE2)) && (!(Outputs->XmpProfileEnable))) {
+      continue;
+    }
+    Actual[Profile] = 0;
+    for (Controller = 0; Controller < MAX_CONTROLLERS; Controller++) {
+      ControllerIn  = &Inputs->Controller[Controller];
+      ControllerOut = &Outputs->Controller[Controller];
+      for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+        ChannelIn   = &ControllerIn->Channel[Channel];
+        ChannelOut  = &ControllerOut->Channel[Channel];
+        for (Dimm = 0; Dimm < MAX_DIMMS_IN_CHANNEL; Dimm++) {
+          DimmIn  = &ChannelIn->Dimm[Dimm];
+          DimmOut = &ChannelOut->Dimm[Dimm];
+          if (DIMM_PRESENT == DimmOut->Status) {
+            Spd            = &DimmIn->Spd;
+            Calculated     = 0;
+            tCKmin         = DimmOut->Timing[Profile].tCK;
+            TimeBase       = &ChannelOut->TimeBase[Dimm][Profile];
+            MediumTimebase = TimeBase->Mtb;
+            FineTimebase   = TimeBase->Ftb;
+            switch (Profile) {
+              case XMP_PROFILE1:
+              case XMP_PROFILE2:
+#if (SUPPORT_XMP == SUPPORT)
+                if (((Profile == XMP_PROFILE1) && ((DimmOut->XmpSupport & 1) != 0)) ||
+                    ((Profile == XMP_PROFILE2) && ((DimmOut->XmpSupport & 2) != 0))) {
+                  Index = Profile - XMP_PROFILE1;
+                    Data = &Spd->Ddr3.Xmp.Data[Index];
+                  TimingMTB = ((U32) (Data->tRASMintRCMinUpper.Bits.tRASminUpper) << 8) | (U32) (Data->tRASmin.Bits.tRASmin);
+                  Calculated = (tCKmin == 0) ? 0 : ((MediumTimebase * TimingMTB) + (tCKmin - 1)) / tCKmin;
+                } else {
+                  Calculated = 0;
+                }
+#endif //SUPPORT_XMP
+                break;
+              case USER_PROFILE:
+                if (DimmIn->Timing.tRAS > 0) {
+                  Calculated = DimmIn->Timing.tRAS;
+                  break;
+                } else {
+                  // In AUTO mode, so no break.
+                }
+              case STD_PROFILE:
+              default:
+                if (tCKmin > 0) {
+                    TimingMTB = ((U32) (Spd->Ddr3.General.tRASMintRCMinUpper.Bits.tRASminUpper) << 8) | (U32) (Spd->Ddr3.General.tRASmin.Bits.tRASmin);
+                  Calculated = (tCKmin == 0) ? 0 : ((MediumTimebase * TimingMTB) + (tCKmin - 1)) / tCKmin;
+                }
+                break;
+            } //switch
+
+            Calculated = MIN (Calculated, TRASMAXPOSSIBLE);
+            Actual[Profile] = MAX (Actual[Profile], Calculated);
+            MRC_DEBUG_MSG (
+              Debug,
+              MSG_LEVEL_NOTE,
+              "  % 7u % 10u % 8u % 5u %6u\n",
+              Profile,
+              Controller,
+              Channel,
+              Dimm,
+              Calculated
+            );
+          } //DimmOut->Status
+        } //Dimm
+      } //Channel
+    } //Controller
+  } //Profile
+
+  //
+  // Set the best case timing for all controllers/channels/dimms, for each profile.
+  //
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "    %s%u:", BestCaseString, MAX_PROFILE - 1);
+  for (Profile = STD_PROFILE; Profile < MAX_PROFILE; Profile++) {
+    if (((Profile == XMP_PROFILE1) || (Profile == XMP_PROFILE2)) && (!(Outputs->XmpProfileEnable))) {
+      continue;
+    }
+    for (Controller = 0; Controller < MAX_CONTROLLERS; Controller++) {
+      ControllerOut = &Outputs->Controller[Controller];
+      for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+        ChannelOut = &ControllerOut->Channel[Channel];
+        for (Dimm = 0; Dimm < MAX_DIMMS_IN_CHANNEL; Dimm++) {
+          DimmOut = &ChannelOut->Dimm[Dimm];
+          DimmOut->Timing[Profile].tRAS    = (U16) Actual[Profile];
+          ChannelOut->Timing[Profile].tRAS = (U16) Actual[Profile];
+        }
+      }
+    }
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, " %u", Actual[Profile]);
+  }
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\n");
+
+  return TRUE;
+}
+
+/**
+  @brief
+  Calculate the minimum tRC timing value for the given memory frequency.
+
+    @param[in, out] MrcData - Pointer to MrcData data structure.
+
+    @retval TRUE if there are DIMMs present, otherwise FALSE.
+**/
+static
+BOOL
+GetChannelDimmtRC (
+  IN OUT MrcParameters *const MrcData
+  )
+{
+  const MrcInput        *Inputs;
+  const MrcControllerIn *ControllerIn;
+  const MrcChannelIn    *ChannelIn;
+  const MrcDimmIn       *DimmIn;
+  const MrcSpd          *Spd;
+  const MrcDebug        *Debug;
+  MrcOutput             *Outputs;
+  MrcControllerOut      *ControllerOut;
+  MrcChannelOut         *ChannelOut;
+  MrcDimmOut            *DimmOut;
+  MrcTimeBase           *TimeBase;
+  MrcProfile            Profile;
+  U8                    Controller;
+  U8                    Channel;
+  U8                    Dimm;
+  U32                   tCKmin;
+  U32                   TimingMTB;
+  S32                   TimingFTB;
+  S32                   MediumTimebase;
+  S32                   FineTimebase;
+  U32                   Actual[MAX_PROFILE];
+  U32                   Calculated;
+#if (SUPPORT_XMP == SUPPORT)
+  const SPD_EXTREME_MEMORY_PROFILE_DATA *Data;
+  U32                                   Index;
+#endif
+
+  Inputs  = &MrcData->SysIn.Inputs;
+  Outputs = &MrcData->SysOut.Outputs;
+  Debug   = &Inputs->Debug;
+
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "  %s:\n  %s\n", tRCString, HeaderString);
+
+  //
+  // Find the smallest timing value for all the given DIMMs, for all the profiles.
+  //
+  for (Profile = STD_PROFILE; Profile < MAX_PROFILE; Profile++) {
+    if (((Profile == XMP_PROFILE1) || (Profile == XMP_PROFILE2)) && (!(Outputs->XmpProfileEnable))) {
+      continue;
+    }
+    Actual[Profile] = 0;
+    for (Controller = 0; Controller < MAX_CONTROLLERS; Controller++) {
+      ControllerIn  = &Inputs->Controller[Controller];
+      ControllerOut = &Outputs->Controller[Controller];
+      for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+        ChannelIn   = &ControllerIn->Channel[Channel];
+        ChannelOut  = &ControllerOut->Channel[Channel];
+        for (Dimm = 0; Dimm < MAX_DIMMS_IN_CHANNEL; Dimm++) {
+          DimmIn  = &ChannelIn->Dimm[Dimm];
+          DimmOut = &ChannelOut->Dimm[Dimm];
+          if (DIMM_PRESENT == DimmOut->Status) {
+            Spd            = &DimmIn->Spd;
+            Calculated     = 0;
+            tCKmin         = DimmOut->Timing[Profile].tCK;
+            TimeBase       = &ChannelOut->TimeBase[Dimm][Profile];
+            MediumTimebase = TimeBase->Mtb;
+            FineTimebase   = TimeBase->Ftb;
+            switch (Profile) {
+              case XMP_PROFILE1:
+              case XMP_PROFILE2:
+#if (SUPPORT_XMP == SUPPORT)
+                if (((Profile == XMP_PROFILE1) && ((DimmOut->XmpSupport & 1) != 0)) ||
+                    ((Profile == XMP_PROFILE2) && ((DimmOut->XmpSupport & 2) != 0))) {
+                  Index = Profile - XMP_PROFILE1;
+                    Data = &Spd->Ddr3.Xmp.Data[Index];
+                  TimingMTB = ((U32) (Data->tRASMintRCMinUpper.Bits.tRCminUpper) << 8) | (U32) (Data->tRCmin.Bits.tRCmin);
+                  TimingFTB = (DimmOut->XmpRevision == 0x13) ? Data->tRCminFine.Bits.tRCminFine : 0;
+                  Calculated = (tCKmin == 0) ? 0 : ((MediumTimebase * TimingMTB) + (FineTimebase * TimingFTB) + (tCKmin - 1)) / tCKmin;
+                } else {
+                  Calculated = 0;
+                }
+#endif //SUPPORT_XMP
+                break;
+              case USER_PROFILE:
+                if (DimmIn->Timing.tRC > 0) {
+                  Calculated = DimmIn->Timing.tRC;
+                  break;
+                } else {
+                  // In AUTO mode, so no break.
+                }
+              case STD_PROFILE:
+              default:
+                if (tCKmin > 0) {
+                    TimingMTB = ((U32) (Spd->Ddr3.General.tRASMintRCMinUpper.Bits.tRCminUpper) << 8) | (U32) (Spd->Ddr3.General.tRCmin.Bits.tRCmin);
+                    TimingFTB = Spd->Ddr3.General.tRCminFine.Bits.tRCminFine;
+                  Calculated = (tCKmin == 0) ? 0 : ((MediumTimebase * TimingMTB) + (FineTimebase * TimingFTB) + (tCKmin - 1)) / tCKmin;
+                }
+                break;
+            } //switch
+
+            Calculated = MIN (Calculated, TRCMAXPOSSIBLE);
+            Actual[Profile] = MAX (Actual[Profile], Calculated);
+            MRC_DEBUG_MSG (
+              Debug,
+              MSG_LEVEL_NOTE,
+              "  % 7u % 10u % 8u % 5u %6u\n",
+              Profile,
+              Controller,
+              Channel,
+              Dimm,
+              Calculated
+            );
+          } //DimmOut->Status
+        } //Dimm
+      } //Channel
+    } //Controller
+  } //Profile
+
+  //
+  // Set the best case timing for all controllers/channels/dimms, for each profile.
+  //
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "    %s%u:", BestCaseString, MAX_PROFILE - 1);
+  for (Profile = STD_PROFILE; Profile < MAX_PROFILE; Profile++) {
+    if (((Profile == XMP_PROFILE1) || (Profile == XMP_PROFILE2)) && (!(Outputs->XmpProfileEnable))) {
+      continue;
+    }
+    for (Controller = 0; Controller < MAX_CONTROLLERS; Controller++) {
+      ControllerOut = &Outputs->Controller[Controller];
+      for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+        ChannelOut = &ControllerOut->Channel[Channel];
+        for (Dimm = 0; Dimm < MAX_DIMMS_IN_CHANNEL; Dimm++) {
+          DimmOut = &ChannelOut->Dimm[Dimm];
+          DimmOut->Timing[Profile].tRC    = (U16) Actual[Profile];
+          ChannelOut->Timing[Profile].tRC = (U16) Actual[Profile];
+        }
+      }
+    }
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, " %u", Actual[Profile]);
+  }
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\n");
+
+  return TRUE;
+}
+
+/**
+  @brief
+  Calculate the minimum tRCD timing value for the given memory frequency.
+
+    @param[in, out] MrcData - Pointer to MrcData data structure.
+
+    @retval TRUE if there are DIMMs present, otherwise FALSE.
+**/
+static
+BOOL
+GetChannelDimmtRCD (
+  IN OUT MrcParameters *const MrcData
+  )
+{
+  const MrcInput        *Inputs;
+  const MrcControllerIn *ControllerIn;
+  const MrcChannelIn    *ChannelIn;
+  const MrcDimmIn       *DimmIn;
+  const MrcSpd          *Spd;
+  const MrcDebug        *Debug;
+  MrcOutput             *Outputs;
+  MrcControllerOut      *ControllerOut;
+  MrcChannelOut         *ChannelOut;
+  MrcDimmOut            *DimmOut;
+  MrcTimeBase           *TimeBase;
+  MrcProfile            Profile;
+  U8                    Controller;
+  U8                    Channel;
+  U8                    Dimm;
+  U32                   tCKmin;
+  U32                   TimingMTB;
+  S32                   TimingFTB;
+  S32                   MediumTimebase;
+  S32                   FineTimebase;
+  U32                   Actual[MAX_PROFILE];
+  U32                   Calculated;
+#if (SUPPORT_XMP == SUPPORT)
+  const SPD_EXTREME_MEMORY_PROFILE_DATA *Data;
+  U32                                   Index;
+#endif
+
+  Inputs  = &MrcData->SysIn.Inputs;
+  Outputs = &MrcData->SysOut.Outputs;
+  Debug   = &Inputs->Debug;
+
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "  %s:\n  %s\n", tRCDString, HeaderString);
+
+  //
+  // Find the smallest timing value for all the given DIMMs, for all the profiles.
+  //
+  for (Profile = STD_PROFILE; Profile < MAX_PROFILE; Profile++) {
+    if (((Profile == XMP_PROFILE1) || (Profile == XMP_PROFILE2)) && (!(Outputs->XmpProfileEnable))) {
+      continue;
+    }
+    Actual[Profile] = 0;
+    for (Controller = 0; Controller < MAX_CONTROLLERS; Controller++) {
+      ControllerIn  = &Inputs->Controller[Controller];
+      ControllerOut = &Outputs->Controller[Controller];
+      for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+        ChannelIn   = &ControllerIn->Channel[Channel];
+        ChannelOut  = &ControllerOut->Channel[Channel];
+        for (Dimm = 0; Dimm < MAX_DIMMS_IN_CHANNEL; Dimm++) {
+          DimmIn  = &ChannelIn->Dimm[Dimm];
+          DimmOut = &ChannelOut->Dimm[Dimm];
+          if (DIMM_PRESENT == DimmOut->Status) {
+            Spd            = &DimmIn->Spd;
+            Calculated     = 0;
+            tCKmin         = DimmOut->Timing[Profile].tCK;
+            TimeBase       = &ChannelOut->TimeBase[Dimm][Profile];
+            MediumTimebase = TimeBase->Mtb;
+            FineTimebase   = TimeBase->Ftb;
+            switch (Profile) {
+              case XMP_PROFILE1:
+              case XMP_PROFILE2:
+#if (SUPPORT_XMP == SUPPORT)
+                if (((Profile == XMP_PROFILE1) && ((DimmOut->XmpSupport & 1) != 0)) ||
+                    ((Profile == XMP_PROFILE2) && ((DimmOut->XmpSupport & 2) != 0))) {
+                  Index = Profile - XMP_PROFILE1;
+                    Data = &Spd->Ddr3.Xmp.Data[Index];
+                  TimingMTB = Data->tRCDmin.Bits.tRCDmin;
+                  TimingFTB = (DimmOut->XmpRevision == 0x13) ? Data->tRCDminFine.Bits.tRCDminFine : 0;
+                  Calculated = (tCKmin == 0) ? 0 : ((MediumTimebase * TimingMTB) + (FineTimebase * TimingFTB) + (tCKmin - 1)) / tCKmin;
+                } else {
+                  Calculated = 0;
+                }
+#endif //SUPPORT_XMP
+                break;
+              case USER_PROFILE:
+                if (DimmIn->Timing.tRCD > 0) {
+                  Calculated = DimmIn->Timing.tRCD;
+                  break;
+                } else {
+                  // In AUTO mode, so no break.
+                }
+              case STD_PROFILE:
+              default:
+                if (tCKmin > 0) {
+                    TimingMTB = Spd->Ddr3.General.tRCDmin.Bits.tRCDmin;
+                    TimingFTB = Spd->Ddr3.General.tRCDminFine.Bits.tRCDminFine;
+                  Calculated = (tCKmin == 0) ? 0 : ((MediumTimebase * TimingMTB) + (FineTimebase * TimingFTB) + (tCKmin - 1)) / tCKmin;
+                }
+                break;
+            } //switch
+
+            Calculated = MIN (Calculated, TRCDMAXPOSSIBLE);
+            Actual[Profile] = MAX (Actual[Profile], Calculated);
+            MRC_DEBUG_MSG (
+              Debug,
+              MSG_LEVEL_NOTE,
+              "  % 7u % 10u % 8u % 5u %6u\n",
+              Profile,
+              Controller,
+              Channel,
+              Dimm,
+              Calculated
+            );
+          } //DimmOut->Status
+        } //Dimm
+      } //Channel
+    } //Controller
+  } //Profile
+
+  //
+  // Set the best case timing for all controllers/channels/dimms, for each profile.
+  //
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "    %s%u:", BestCaseString, MAX_PROFILE - 1);
+  for (Profile = STD_PROFILE; Profile < MAX_PROFILE; Profile++) {
+    if (((Profile == XMP_PROFILE1) || (Profile == XMP_PROFILE2)) && (!(Outputs->XmpProfileEnable))) {
+      continue;
+    }
+    for (Controller = 0; Controller < MAX_CONTROLLERS; Controller++) {
+      ControllerOut = &Outputs->Controller[Controller];
+      for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+        ChannelOut = &ControllerOut->Channel[Channel];
+        for (Dimm = 0; Dimm < MAX_DIMMS_IN_CHANNEL; Dimm++) {
+          DimmOut = &ChannelOut->Dimm[Dimm];
+          DimmOut->Timing[Profile].tRCD    = (U16) Actual[Profile];
+          ChannelOut->Timing[Profile].tRCD = (U16) Actual[Profile];
+        }
+      }
+    }
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, " %u", Actual[Profile]);
+  }
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\n");
+
+  return TRUE;
+}
+
+/**
+  @brief
+  Calculate the minimum tREFI timing value for the given memory frequency.
+
+    @param[in, out] MrcData - Pointer to MrcData data structure.
+
+    @retval TRUE if there are DIMMs present, otherwise FALSE.
+**/
+static
+BOOL
+GetChannelDimmtREFI (
+  IN OUT MrcParameters *const MrcData
+  )
+{
+  const MrcInput        *Inputs;
+  const MrcControllerIn *ControllerIn;
+  const MrcChannelIn    *ChannelIn;
+  const MrcDimmIn       *DimmIn;
+  const MrcSpd          *Spd;
+  const MrcDebug        *Debug;
+  MrcOutput             *Outputs;
+  MrcControllerOut      *ControllerOut;
+  MrcChannelOut         *ChannelOut;
+  MrcDimmOut            *DimmOut;
+  MrcTimeBase           *TimeBase;
+  MrcProfile            Profile;
+  U8                    Controller;
+  U8                    Channel;
+  U8                    Dimm;
+  U32                   tCKmin;
+  S32                   MediumTimebase;
+  S32                   FineTimebase;
+  U32                   Actual[MAX_PROFILE];
+  U32                   Calculated;
+  U32                   TimingMTB;
+#if (SUPPORT_XMP == SUPPORT)
+  U32                   Index;
+#endif
+
+  Inputs  = &MrcData->SysIn.Inputs;
+  Outputs = &MrcData->SysOut.Outputs;
+  Debug   = &Inputs->Debug;
+
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "  %s:\n  %s\n", tREFIString, HeaderString);
+
+  //
+  // Find the smallest timing value for all the given DIMMs, for all the profiles.
+  //
+  for (Profile = STD_PROFILE; Profile < MAX_PROFILE; Profile++) {
+    if (((Profile == XMP_PROFILE1) || (Profile == XMP_PROFILE2)) && (!(Outputs->XmpProfileEnable))) {
+      continue;
+    }
+    Actual[Profile] = 0;
+    for (Controller = 0; Controller < MAX_CONTROLLERS; Controller++) {
+      ControllerIn  = &Inputs->Controller[Controller];
+      ControllerOut = &Outputs->Controller[Controller];
+      for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+        ChannelIn   = &ControllerIn->Channel[Channel];
+        ChannelOut  = &ControllerOut->Channel[Channel];
+        for (Dimm = 0; Dimm < MAX_DIMMS_IN_CHANNEL; Dimm++) {
+          DimmIn  = &ChannelIn->Dimm[Dimm];
+          DimmOut = &ChannelOut->Dimm[Dimm];
+          if (DIMM_PRESENT == DimmOut->Status) {
+            Spd            = &DimmIn->Spd;
+            Calculated     = 0;
+            tCKmin         = DimmOut->Timing[Profile].tCK;
+            TimeBase       = &ChannelOut->TimeBase[Dimm][Profile];
+            MediumTimebase = TimeBase->Mtb;
+            FineTimebase   = TimeBase->Ftb;
+            switch (Profile) {
+              case XMP_PROFILE1:
+              case XMP_PROFILE2:
+#if (SUPPORT_XMP == SUPPORT)
+                if (((Profile == XMP_PROFILE1) && ((DimmOut->XmpSupport & 1) != 0)) ||
+                    ((Profile == XMP_PROFILE2) && ((DimmOut->XmpSupport & 2) != 0))) {
+                  Index = Profile - XMP_PROFILE1;
+                    TimingMTB = Spd->Ddr3.Xmp.Data[Index].tREFImin.Bits.tREFImin;
+                  Calculated = (tCKmin == 0) ? 0 : (U32) (MrcOemMemoryDivideU64ByU64 (
+                    ((MrcOemMemoryMultiplyU64ByU32 (MediumTimebase, TimingMTB * TREFIMULTIPLIER)) + (tCKmin - 1)),
+                    tCKmin));
+                } else {
+                  Calculated = 0;
+                }
+#endif //SUPPORT_XMP
+                break;
+              case USER_PROFILE:
+                if (DimmIn->Timing.tREFI > 0) {
+                  Calculated = DimmIn->Timing.tREFI;
+                  break;
+                } else {
+                  // In AUTO mode, so no break.
+                }
+              case STD_PROFILE:
+              default:
+                if (tCKmin > 0) {
+                  switch (DimmOut->DdrType)
+                  {
+#if (MRC_DDR3_LPDDR_SUPPORTED)
+              case MRC_DDR_TYPE_DDR3:
+                TimingMTB = TREFIMIN_DDR3;
+                break;
+#endif
+#if (SUPPORT_LPDDR3 == SUPPORT)
+              case MRC_DDR_TYPE_LPDDR3:
+                TimingMTB = TREFIMIN_LPDDR3;
+                break;
+#endif
+              default:
+                TimingMTB = TREFIMIN_DDR3;
+                break;
+                  }
+
+                  Calculated = (tCKmin == 0) ? 0 : ((TimingMTB + ((tCKmin / 1000) - 1)) / (tCKmin / 1000));
+                }
+                break;
+            } //switch
+
+            Calculated = MIN (Calculated, TREFIMAXPOSSIBLE);
+            Actual[Profile] = MAX (Actual[Profile], Calculated);
+            MRC_DEBUG_MSG (
+              Debug,
+              MSG_LEVEL_NOTE,
+              "  % 7u % 10u % 8u % 5u %6u\n",
+              Profile,
+              Controller,
+              Channel,
+              Dimm,
+              Calculated
+            );
+          } //DimmOut->Status
+        } //Dimm
+      } //Channel
+    } //Controller
+  } //Profile
+
+  //
+  // Set the best case timing for all controllers/channels/dimms, for each profile.
+  //
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "    %s%u:", BestCaseString, MAX_PROFILE - 1);
+  for (Profile = STD_PROFILE; Profile < MAX_PROFILE; Profile++) {
+    if (((Profile == XMP_PROFILE1) || (Profile == XMP_PROFILE2)) && (!(Outputs->XmpProfileEnable))) {
+      continue;
+    }
+    for (Controller = 0; Controller < MAX_CONTROLLERS; Controller++) {
+      ControllerOut = &Outputs->Controller[Controller];
+      for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+        ChannelOut = &ControllerOut->Channel[Channel];
+        for (Dimm = 0; Dimm < MAX_DIMMS_IN_CHANNEL; Dimm++) {
+          DimmOut = &ChannelOut->Dimm[Dimm];
+          DimmOut->Timing[Profile].tREFI    = (U16) Actual[Profile];
+          ChannelOut->Timing[Profile].tREFI = (U16) Actual[Profile];
+        }
+      }
+    }
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, " %u", Actual[Profile]);
+  }
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\n");
+
+  return TRUE;
+}
+
+/**
+  @brief
+  Calculate the minimum tRFC timing value for the given memory frequency.
+
+    @param[in, out] MrcData - Pointer to MrcData data structure.
+
+    @retval TRUE if there are DIMMs present, otherwise FALSE.
+**/
+static
+BOOL
+GetChannelDimmtRFC (
+  IN OUT MrcParameters *const MrcData
+  )
+{
+  const MrcInput        *Inputs;
+  const MrcControllerIn *ControllerIn;
+  const MrcChannelIn    *ChannelIn;
+  const MrcDimmIn       *DimmIn;
+  const MrcSpd          *Spd;
+  const MrcDebug        *Debug;
+  MrcOutput             *Outputs;
+  MrcControllerOut      *ControllerOut;
+  MrcChannelOut         *ChannelOut;
+  MrcDimmOut            *DimmOut;
+  MrcTimeBase           *TimeBase;
+  MrcProfile            Profile;
+  U8                    Controller;
+  U8                    Channel;
+  U8                    Dimm;
+  U32                   tCKmin;
+  U32                   TimingMTB;
+  S32                   MediumTimebase;
+  S32                   FineTimebase;
+  U32                   Actual[MAX_PROFILE];
+  U32                   Calculated;
+#if (SUPPORT_XMP == SUPPORT)
+  U32                   Index;
+#endif
+
+  Inputs  = &MrcData->SysIn.Inputs;
+  Outputs = &MrcData->SysOut.Outputs;
+  Debug   = &Inputs->Debug;
+
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "  %s:\n  %s\n", tRFCString, HeaderString);
+
+  //
+  // Find the smallest timing value for all the given DIMMs.
+  //
+  for (Profile = STD_PROFILE; Profile < MAX_PROFILE; Profile++) {
+    if (((Profile == XMP_PROFILE1) || (Profile == XMP_PROFILE2)) && (!(Outputs->XmpProfileEnable))) {
+      continue;
+    }
+    Actual[Profile] = 0;
+    for (Controller = 0; Controller < MAX_CONTROLLERS; Controller++) {
+      ControllerIn  = &Inputs->Controller[Controller];
+      ControllerOut = &Outputs->Controller[Controller];
+      for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+        ChannelIn   = &ControllerIn->Channel[Channel];
+        ChannelOut  = &ControllerOut->Channel[Channel];
+        for (Dimm = 0; Dimm < MAX_DIMMS_IN_CHANNEL; Dimm++) {
+          DimmIn  = &ChannelIn->Dimm[Dimm];
+          DimmOut = &ChannelOut->Dimm[Dimm];
+          if (DIMM_PRESENT == DimmOut->Status) {
+            Spd            = &DimmIn->Spd;
+            Calculated     = 0;
+            tCKmin         = DimmOut->Timing[Profile].tCK;
+            TimeBase       = &ChannelOut->TimeBase[Dimm][Profile];
+            MediumTimebase = TimeBase->Mtb;
+            FineTimebase   = TimeBase->Ftb;
+            switch (Profile) {
+              case XMP_PROFILE1:
+              case XMP_PROFILE2:
+#if (SUPPORT_XMP == SUPPORT)
+                if (((Profile == XMP_PROFILE1) && ((DimmOut->XmpSupport & 1) != 0)) ||
+                    ((Profile == XMP_PROFILE2) && ((DimmOut->XmpSupport & 2) != 0))) {
+                  Index = Profile - XMP_PROFILE1;
+                    TimingMTB = Spd->Ddr3.Xmp.Data[Index].tRFCmin.Bits.tRFCmin;
+                  Calculated = (tCKmin == 0) ? 0 : ((MediumTimebase * TimingMTB) + (tCKmin - 1)) / tCKmin;
+                } else {
+                  Calculated = 0;
+                }
+#endif //SUPPORT_XMP
+                break;
+              case USER_PROFILE:
+                if (DimmIn->Timing.tRFC > 0) {
+                  Calculated = DimmIn->Timing.tRFC;
+                  break;
+                } else {
+                  // In AUTO mode, so no break.
+                }
+              case STD_PROFILE:
+              default:
+                if (tCKmin > 0) {
+                    TimingMTB = Spd->Ddr3.General.tRFCmin.Bits.tRFCmin;
+                    //
+                    // @todo: Temp w/a for 8GB dimms
+                    // if ((DimmOut->DimmCapacity == 8192) && (TimingMTB != 2400)) {
+                    //   MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%s %u/%u/%u tRFC MTB = %u .., W/A - changing it to 2400\n", CcdString, Controller, Channel, Dimm, TimingMTB);
+                    //   TimingMTB = 2400;
+                    // }
+                    //
+
+                  Calculated = (tCKmin == 0) ? 0 : ((MediumTimebase * TimingMTB) + (tCKmin - 1)) / tCKmin;
+                }
+                break;
+            } //switch
+
+            Calculated = MIN (Calculated, TRFCMAXPOSSIBLE);
+            Actual[Profile] = MAX (Actual[Profile], Calculated);
+            MRC_DEBUG_MSG (
+              Debug,
+              MSG_LEVEL_NOTE,
+              "  % 7u % 10u % 8u % 5u %6u\n",
+              Profile,
+              Controller,
+              Channel,
+              Dimm,
+              Calculated
+            );
+          } //DimmOut->Status
+        } //Dimm
+      } //Channel
+    } //Controller
+  } //Profile
+
+  //
+  // Set the best case timing for all controllers/channels/dimms, for each profile.
+  //
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "    %s%u:", BestCaseString, MAX_PROFILE - 1);
+  for (Profile = STD_PROFILE; Profile < MAX_PROFILE; Profile++) {
+    if (((Profile == XMP_PROFILE1) || (Profile == XMP_PROFILE2)) && (!(Outputs->XmpProfileEnable))) {
+      continue;
+    }
+    for (Controller = 0; Controller < MAX_CONTROLLERS; Controller++) {
+      ControllerOut = &Outputs->Controller[Controller];
+      for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+        ChannelOut = &ControllerOut->Channel[Channel];
+        for (Dimm = 0; Dimm < MAX_DIMMS_IN_CHANNEL; Dimm++) {
+          DimmOut = &ChannelOut->Dimm[Dimm];
+          DimmOut->Timing[Profile].tRFC    = (U16) Actual[Profile];
+          ChannelOut->Timing[Profile].tRFC = (U16) Actual[Profile];
+        }
+      }
+    }
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, " %u", Actual[Profile]);
+  }
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\n");
+
+  return TRUE;
+}
+
+
+/**
+  @brief
+  Calculate the minimum tRP timing value for the given memory frequency.
+
+    @param[in, out] MrcData - Pointer to MrcData data structure.
+
+    @retval TRUE if there are DIMMs present, otherwise FALSE.
+**/
+static
+BOOL
+GetChannelDimmtRP (
+  IN OUT MrcParameters *const MrcData
+  )
+{
+  const MrcInput        *Inputs;
+  const MrcControllerIn *ControllerIn;
+  const MrcChannelIn    *ChannelIn;
+  const MrcDimmIn       *DimmIn;
+  const MrcSpd          *Spd;
+  const MrcDebug        *Debug;
+  MrcOutput             *Outputs;
+  MrcControllerOut      *ControllerOut;
+  MrcChannelOut         *ChannelOut;
+  MrcDimmOut            *DimmOut;
+  MrcTimeBase           *TimeBase;
+  MrcProfile            Profile;
+  U8                    Controller;
+  U8                    Channel;
+  U8                    Dimm;
+  U32                   tCKmin;
+  S32                   MediumTimebase;
+  S32                   FineTimebase;
+  U32                   TimingMTB;
+  S32                   TimingFTB;
+  U32                   Actual[MAX_PROFILE];
+  U32                   Calculated;
+#if (SUPPORT_XMP == SUPPORT)
+  U32                                   Index;
+  const SPD_EXTREME_MEMORY_PROFILE_DATA *Data;
+#endif
+
+  Inputs  = &MrcData->SysIn.Inputs;
+  Outputs = &MrcData->SysOut.Outputs;
+  Debug   = &Inputs->Debug;
+
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "  %s:\n  %s\n", tRPString, HeaderString);
+
+  //
+  // Find the smallest timing value for all the given DIMMs, for all the profiles.
+  //
+  for (Profile = STD_PROFILE; Profile < MAX_PROFILE; Profile++) {
+    if (((Profile == XMP_PROFILE1) || (Profile == XMP_PROFILE2)) && (!(Outputs->XmpProfileEnable))) {
+      continue;
+    }
+    Actual[Profile] = 0;
+    for (Controller = 0; Controller < MAX_CONTROLLERS; Controller++) {
+      ControllerIn  = &Inputs->Controller[Controller];
+      ControllerOut = &Outputs->Controller[Controller];
+      for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+        ChannelIn   = &ControllerIn->Channel[Channel];
+        ChannelOut  = &ControllerOut->Channel[Channel];
+        for (Dimm = 0; Dimm < MAX_DIMMS_IN_CHANNEL; Dimm++) {
+          DimmIn  = &ChannelIn->Dimm[Dimm];
+          DimmOut = &ChannelOut->Dimm[Dimm];
+          if (DIMM_PRESENT == DimmOut->Status) {
+            Spd            = &DimmIn->Spd;
+            Calculated     = 0;
+            tCKmin         = DimmOut->Timing[Profile].tCK;
+            TimeBase       = &ChannelOut->TimeBase[Dimm][Profile];
+            MediumTimebase = TimeBase->Mtb;
+            FineTimebase   = TimeBase->Ftb;
+            switch (Profile) {
+              case XMP_PROFILE1:
+              case XMP_PROFILE2:
+#if (SUPPORT_XMP == SUPPORT)
+                if (((Profile == XMP_PROFILE1) && ((DimmOut->XmpSupport & 1) != 0)) ||
+                    ((Profile == XMP_PROFILE2) && ((DimmOut->XmpSupport & 2) != 0))) {
+                  Index = Profile - XMP_PROFILE1;
+                    Data = &Spd->Ddr3.Xmp.Data[Index];
+                  TimingMTB = Data->tRPmin.Bits.tRPmin;
+                  TimingFTB = (DimmOut->XmpRevision == 0x13) ? Data->tRPminFine.Bits.tRPminFine : 0;
+                  Calculated = (tCKmin == 0) ? 0 : ((MediumTimebase * TimingMTB) + (FineTimebase * TimingFTB) + (tCKmin - 1)) / tCKmin;
+                } else {
+                  Calculated = 0;
+                }
+#endif //SUPPORT_XMP
+                break;
+              case USER_PROFILE:
+                if (DimmIn->Timing.tRP > 0) {
+                  Calculated = DimmIn->Timing.tRP;
+                  break;
+                } else {
+                  // In AUTO mode, so no break.
+                }
+              case STD_PROFILE:
+              default:
+                if (tCKmin > 0) {
+                    TimingMTB = Spd->Ddr3.General.tRPmin.Bits.tRPmin;
+                    TimingFTB = Spd->Ddr3.General.tRPminFine.Bits.tRPminFine;
+                  Calculated = (tCKmin == 0) ? 0 : ((MediumTimebase * TimingMTB) + (FineTimebase * TimingFTB) + (tCKmin - 1)) / tCKmin;
+                }
+                break;
+            } //switch
+
+            Calculated = MIN (Calculated, TRPMAXPOSSIBLE);
+            Actual[Profile] = MAX (Actual[Profile], Calculated);
+            MRC_DEBUG_MSG (
+              Debug,
+              MSG_LEVEL_NOTE,
+              "  % 7u % 10u % 8u % 5u %6u\n",
+              Profile,
+              Controller,
+              Channel,
+              Dimm,
+              Calculated
+            );
+          } //DimmOut->Status
+        } //Dimm
+      } //Channel
+    } //Controller
+  } //Profile
+
+  //
+  // Set the best case timing for all controllers/channels/dimms, for each profile.
+  //
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "    %s%u:", BestCaseString, MAX_PROFILE - 1);
+  for (Profile = STD_PROFILE; Profile < MAX_PROFILE; Profile++) {
+    if (((Profile == XMP_PROFILE1) || (Profile == XMP_PROFILE2)) && (!(Outputs->XmpProfileEnable))) {
+      continue;
+    }
+    for (Controller = 0; Controller < MAX_CONTROLLERS; Controller++) {
+      ControllerOut = &Outputs->Controller[Controller];
+      for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+        ChannelOut = &ControllerOut->Channel[Channel];
+        for (Dimm = 0; Dimm < MAX_DIMMS_IN_CHANNEL; Dimm++) {
+          DimmOut = &ChannelOut->Dimm[Dimm];
+          DimmOut->Timing[Profile].tRP    = (U16) Actual[Profile];
+          ChannelOut->Timing[Profile].tRP = (U16) Actual[Profile];
+        }
+      }
+    }
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, " %u", Actual[Profile]);
+  }
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\n");
+
+  return TRUE;
+}
+
+#if (SUPPORT_LPDDR3 == SUPPORT)
+/**
+  @brief
+  Calculate the minimum tRPab timing value for the given memory frequency.
+
+    @param[in, out] MrcData - Pointer to MrcData data structure.
+
+    @retval TRUE if there are DIMMs present, otherwise FALSE.
+**/
+static
+BOOL
+GetChannelDimmtRPab (
+  IN OUT MrcParameters *const MrcData
+  )
+{
+  const MrcInput        *Inputs;
+  const MrcControllerIn *ControllerIn;
+  const MrcChannelIn    *ChannelIn;
+  const MrcDimmIn       *DimmIn;
+  const MrcSpd          *Spd;
+  const MrcDebug        *Debug;
+  MrcOutput             *Outputs;
+  MrcControllerOut      *ControllerOut;
+  MrcChannelOut         *ChannelOut;
+  MrcDimmOut            *DimmOut;
+  MrcTimeBase           *TimeBase;
+  MrcProfile            Profile;
+  MrcBool               Flag;
+  U8                    Controller;
+  U8                    Channel;
+  U8                    Dimm;
+  U32                   tCKmin;
+  S32                   MediumTimebase;
+  S32                   FineTimebase;
+  U32                   TimingMTB;
+  S32                   TimingFTB;
+  U32                   Actual[MAX_PROFILE];
+  U32                   Calculated;
+
+  Inputs  = &MrcData->SysIn.Inputs;
+  Outputs = &MrcData->SysOut.Outputs;
+  Debug   = &Inputs->Debug;
+  Flag    = FALSE;
+
+  //
+  // Find the smallest timing value for all the given DIMMs, for all the profiles.
+  //
+  for (Profile = STD_PROFILE; Profile < MAX_PROFILE; Profile++) {
+    if (((Profile == XMP_PROFILE1) || (Profile == XMP_PROFILE2)) && (!(Outputs->XmpProfileEnable))) {
+      continue;
+    }
+    Actual[Profile] = 0;
+    for (Controller = 0; Controller < MAX_CONTROLLERS; Controller++) {
+      ControllerIn  = &Inputs->Controller[Controller];
+      ControllerOut = &Outputs->Controller[Controller];
+      for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+        ChannelIn   = &ControllerIn->Channel[Channel];
+        ChannelOut  = &ControllerOut->Channel[Channel];
+        for (Dimm = 0; Dimm < MAX_DIMMS_IN_CHANNEL; Dimm++) {
+          DimmIn  = &ChannelIn->Dimm[Dimm];
+          DimmOut = &ChannelOut->Dimm[Dimm];
+          if ((DIMM_PRESENT == DimmOut->Status) && (DimmOut->DdrType == MRC_DDR_TYPE_LPDDR3)) {
+            Spd            = &DimmIn->Spd;
+            Calculated     = 0;
+            tCKmin         = DimmOut->Timing[Profile].tCK;
+            TimeBase       = &ChannelOut->TimeBase[Dimm][Profile];
+            MediumTimebase = TimeBase->Mtb;
+            FineTimebase   = TimeBase->Ftb;
+            switch (Profile) {
+              case USER_PROFILE:
+                if (DimmIn->Timing.tRPab > 0) {
+                  Calculated = DimmIn->Timing.tRPab;
+                  break;
+                } else {
+                  // In AUTO mode, so no break.
+                }
+              case STD_PROFILE:
+              case XMP_PROFILE1:
+              case XMP_PROFILE2:
+              default:
+                if (tCKmin > 0) {
+                  TimingMTB  = Spd->Ddr3.General.tRPab.Bits.tRPab;
+                  TimingFTB  = Spd->Ddr3.General.tRPabFine.Bits.tRPabFine;
+                  Calculated = (tCKmin == 0) ? 0 : ((MediumTimebase * TimingMTB) + (FineTimebase * TimingFTB) + (tCKmin - 1)) / tCKmin;
+                }
+                break;
+            } //switch
+
+            if ((Calculated >= TRPABMINPOSSIBLE) && ((Calculated - DimmOut->Timing[Profile].tRP) <= 3)) {
+              Actual[Profile] = MAX (Actual[Profile], Calculated);
+            }
+            if (!Flag) {
+              Flag = TRUE;
+              MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "  %s:\n  %s\n", tRPabString, HeaderString);
+              MRC_DEBUG_MSG (
+                Debug,
+                MSG_LEVEL_NOTE,
+                "  % 7u % 10u % 8u % 5u %6u\n",
+                Profile,
+                Controller,
+                Channel,
+                Dimm,
+                Calculated
+                );
+            } //Flag
+          } //DimmOut->Status
+        } //Dimm
+      } //Channel
+    } //Controller
+  } //Profile
+
+  if (Flag ) {
+    //
+    // Set the best case timing for all controllers/channels/dimms, for each profile.
+    //
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "    %s%u:", BestCaseString, MAX_PROFILE - 1);
+    for (Profile = STD_PROFILE; Profile < MAX_PROFILE; Profile++) {
+      if (((Profile == XMP_PROFILE1) || (Profile == XMP_PROFILE2)) && (!(Outputs->XmpProfileEnable))) {
+        continue;
+      }
+      for (Controller = 0; Controller < MAX_CONTROLLERS; Controller++) {
+        ControllerOut = &Outputs->Controller[Controller];
+        for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+          ChannelOut = &ControllerOut->Channel[Channel];
+          for (Dimm = 0; Dimm < MAX_DIMMS_IN_CHANNEL; Dimm++) {
+            DimmOut = &ChannelOut->Dimm[Dimm];
+            DimmOut->Timing[Profile].tRPab    = (U16) Actual[Profile];
+            ChannelOut->Timing[Profile].tRPab = (U16) Actual[Profile];
+          }
+        }
+      }
+      MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, " %u", Actual[Profile]);
+    }
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\n");
+  }
+
+  return TRUE;
+
+}
+#endif
+
+#if (MRC_DDR3_LPDDR_SUPPORTED)
+/**
+  @brief
+  Calculate the minimum tRRD timing value for the given memory frequency.
+    MRC should not set tRRD below 4nCK for all frequencies.
+
+    @param[in, out] MrcData - Pointer to MrcData data structure.
+
+    @retval TRUE
+**/
+static
+BOOL
+GetChannelDimmtRRD (
+  IN OUT MrcParameters *const MrcData
+  )
+{
+  const MrcInput        *Inputs;
+  const MrcControllerIn *ControllerIn;
+  const MrcChannelIn    *ChannelIn;
+  const MrcDimmIn       *DimmIn;
+  const MrcSpd          *Spd;
+  const MrcDebug        *Debug;
+  MrcOutput             *Outputs;
+  MrcControllerOut      *ControllerOut;
+  MrcChannelOut         *ChannelOut;
+  MrcDimmOut            *DimmOut;
+  MrcTimeBase           *TimeBase;
+  MrcProfile            Profile;
+  U8                    Controller;
+  U8                    Channel;
+  U8                    Dimm;
+  U32                   tCKmin;
+  U32                   TimingMTB;
+  S32                   MediumTimebase;
+  S32                   FineTimebase;
+  U32                   Actual[MAX_PROFILE];
+  U32                   Calculated;
+#if (SUPPORT_XMP == SUPPORT)
+  U32                   Index;
+#endif
+
+  Inputs  = &MrcData->SysIn.Inputs;
+  Outputs = &MrcData->SysOut.Outputs;
+  Debug   = &Inputs->Debug;
+
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "  %s:\n  %s\n", tRRDString, HeaderString);
+
+  //
+  // Find the smallest timing value for all the given DIMMs, for all the profiles.
+  //
+  for (Profile = STD_PROFILE; Profile < MAX_PROFILE; Profile++) {
+    if (((Profile == XMP_PROFILE1) || (Profile == XMP_PROFILE2)) && (!(Outputs->XmpProfileEnable))) {
+      continue;
+    }
+    Actual[Profile] = 0;
+    for (Controller = 0; Controller < MAX_CONTROLLERS; Controller++) {
+      ControllerIn  = &Inputs->Controller[Controller];
+      ControllerOut = &Outputs->Controller[Controller];
+      for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+        ChannelIn   = &ControllerIn->Channel[Channel];
+        ChannelOut  = &ControllerOut->Channel[Channel];
+        for (Dimm = 0; Dimm < MAX_DIMMS_IN_CHANNEL; Dimm++) {
+          DimmIn  = &ChannelIn->Dimm[Dimm];
+          DimmOut = &ChannelOut->Dimm[Dimm];
+          if (DIMM_PRESENT == DimmOut->Status) {
+            Spd            = &DimmIn->Spd;
+            Calculated     = 0;
+            tCKmin         = DimmOut->Timing[Profile].tCK;
+            TimeBase       = &ChannelOut->TimeBase[Dimm][Profile];
+            MediumTimebase = TimeBase->Mtb;
+            FineTimebase   = TimeBase->Ftb;
+            switch (Profile) {
+              case XMP_PROFILE1:
+              case XMP_PROFILE2:
+#if (SUPPORT_XMP == SUPPORT)
+                if (((Profile == XMP_PROFILE1) && ((DimmOut->XmpSupport & 1) != 0)) ||
+                    ((Profile == XMP_PROFILE2) && ((DimmOut->XmpSupport & 2) != 0))) {
+                  Index = Profile - XMP_PROFILE1;
+                  TimingMTB = Spd->Ddr3.Xmp.Data[Index].tRRDmin.Bits.tRRDmin;
+                  Calculated = (tCKmin == 0) ? 0 : ((MediumTimebase * TimingMTB) + (tCKmin - 1)) / tCKmin;
+                } else {
+                  Calculated = 0;
+                }
+#endif //SUPPORT_XMP
+                break;
+              case USER_PROFILE:
+                if (DimmIn->Timing.tRRD > 0) {
+                  Calculated = DimmIn->Timing.tRRD;
+                  break;
+                } else {
+                  // In AUTO mode, so no break.
+                }
+              case STD_PROFILE:
+              default:
+                if (tCKmin > 0) {
+                  TimingMTB = Spd->Ddr3.General.tRRDmin.Bits.tRRDmin;
+                  Calculated = (tCKmin == 0) ? 0 : ((MediumTimebase * TimingMTB) + (tCKmin - 1)) / tCKmin;
+                }
+                break;
+            } //switch
+
+            Calculated = MAX (Calculated, TRRDMINPOSSIBLE);  // Make sure tRRD is at least 4 tCK
+            Actual[Profile] = MAX (Actual[Profile], Calculated);
+            MRC_DEBUG_MSG (
+              Debug,
+              MSG_LEVEL_NOTE,
+              "  % 7u % 10u % 8u % 5u %6u\n",
+              Profile,
+              Controller,
+              Channel,
+              Dimm,
+              Calculated
+            );
+          } //DimmOut->Status
+        } //Dimm
+      } //Channel
+    } //Controller
+  } //Profile
+
+  //
+  // Set the best case timing for all controllers/channels/dimms, for each profile.
+  //
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "    %s%u:", BestCaseString, MAX_PROFILE - 1);
+  for (Profile = STD_PROFILE; Profile < MAX_PROFILE; Profile++) {
+    if (((Profile == XMP_PROFILE1) || (Profile == XMP_PROFILE2)) && (!(Outputs->XmpProfileEnable))) {
+      continue;
+    }
+    for (Controller = 0; Controller < MAX_CONTROLLERS; Controller++) {
+      ControllerOut = &Outputs->Controller[Controller];
+      for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+        ChannelOut = &ControllerOut->Channel[Channel];
+        for (Dimm = 0; Dimm < MAX_DIMMS_IN_CHANNEL; Dimm++) {
+          DimmOut = &ChannelOut->Dimm[Dimm];
+          DimmOut->Timing[Profile].tRRD    = (U16) Actual[Profile];
+          ChannelOut->Timing[Profile].tRRD = (U16) Actual[Profile];
+        }
+      }
+    }
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, " %u", Actual[Profile]);
+  }
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\n");
+
+  return TRUE;
+}
+#endif
+
+
+#if (MRC_DDR3_LPDDR_SUPPORTED)
+/**
+  @brief
+  Calculate the minimum tRTP timing value for the given memory frequency.
+
+    @param[in, out] MrcData - Pointer to MrcData data structure.
+
+    @retval TRUE if there are DIMMs present, otherwise FALSE.
+**/
+static
+BOOL
+GetChannelDimmtRTP (
+  IN OUT MrcParameters *const MrcData
+  )
+{
+  const MrcInput        *Inputs;
+  const MrcControllerIn *ControllerIn;
+  const MrcChannelIn    *ChannelIn;
+  const MrcDimmIn       *DimmIn;
+  const MrcSpd          *Spd;
+  const MrcDebug        *Debug;
+  MrcOutput             *Outputs;
+  MrcControllerOut      *ControllerOut;
+  MrcChannelOut         *ChannelOut;
+  MrcDimmOut            *DimmOut;
+  MrcTimeBase           *TimeBase;
+  MrcProfile            Profile;
+  U8                    Controller;
+  U8                    Channel;
+  U8                    Dimm;
+  U32                   tCKmin;
+  U32                   TimingMTB;
+  S32                   MediumTimebase;
+  S32                   FineTimebase;
+  U32                   Actual[MAX_PROFILE];
+  U32                   Calculated;
+  U32                   MaxPossible;
+#if (SUPPORT_XMP == SUPPORT)
+  U32                   Index;
+#endif
+
+  Inputs      = &MrcData->SysIn.Inputs;
+  Outputs     = &MrcData->SysOut.Outputs;
+  Debug       = &Inputs->Debug;
+  MaxPossible = TRTPMAXPOSSIBLE;
+
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "  %s:\n  %s\n", tRTPString, HeaderString);
+
+  //
+  // Find the smallest timing value for all the given DIMMs, for all the profiles.
+  //
+  for (Profile = STD_PROFILE; Profile < MAX_PROFILE; Profile++) {
+    if (((Profile == XMP_PROFILE1) || (Profile == XMP_PROFILE2)) && (!(Outputs->XmpProfileEnable))) {
+      continue;
+    }
+    Actual[Profile] = 0;
+    for (Controller = 0; Controller < MAX_CONTROLLERS; Controller++) {
+      ControllerIn  = &Inputs->Controller[Controller];
+      ControllerOut = &Outputs->Controller[Controller];
+      for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+        ChannelIn   = &ControllerIn->Channel[Channel];
+        ChannelOut  = &ControllerOut->Channel[Channel];
+        for (Dimm = 0; Dimm < MAX_DIMMS_IN_CHANNEL; Dimm++) {
+          DimmIn  = &ChannelIn->Dimm[Dimm];
+          DimmOut = &ChannelOut->Dimm[Dimm];
+          if (DIMM_PRESENT == DimmOut->Status) {
+            Spd            = &DimmIn->Spd;
+            Calculated     = 0;
+            tCKmin         = DimmOut->Timing[Profile].tCK;
+            TimeBase       = &ChannelOut->TimeBase[Dimm][Profile];
+            MediumTimebase = TimeBase->Mtb;
+            FineTimebase   = TimeBase->Ftb;
+            switch (Profile) {
+              case XMP_PROFILE1:
+              case XMP_PROFILE2:
+#if (SUPPORT_XMP == SUPPORT)
+                if (((Profile == XMP_PROFILE1) && ((DimmOut->XmpSupport & 1) != 0)) ||
+                    ((Profile == XMP_PROFILE2) && ((DimmOut->XmpSupport & 2) != 0))) {
+                  Index = Profile - XMP_PROFILE1;
+                  TimingMTB = Spd->Ddr3.Xmp.Data[Index].tRTPmin.Bits.tRTPmin;
+                  Calculated = (tCKmin == 0) ? 0 : ((MediumTimebase * TimingMTB) + (tCKmin - 1)) / tCKmin;
+                } else {
+                  Calculated = 0;
+                }
+#endif //SUPPORT_XMP
+                break;
+              case USER_PROFILE:
+                if (DimmIn->Timing.tRTP > 0) {
+                  Calculated = DimmIn->Timing.tRTP;
+                  break;
+                } else {
+                  // In AUTO mode, so no break.
+                }
+              case STD_PROFILE:
+              default:
+                if (tCKmin > 0) {
+                  TimingMTB = Spd->Ddr3.General.tRTPmin.Bits.tRTPmin;
+                  Calculated = (tCKmin == 0) ? 0 : ((MediumTimebase * TimingMTB) + (tCKmin - 1)) / tCKmin;
+                }
+                break;
+            } //switch
+
+            Calculated = MIN (Calculated, MaxPossible);
+            Actual[Profile] = MAX (Actual[Profile], Calculated);
+            MRC_DEBUG_MSG (
+              Debug,
+              MSG_LEVEL_NOTE,
+              "  % 7u % 10u % 8u % 5u %6u\n",
+              Profile,
+              Controller,
+              Channel,
+              Dimm,
+              Calculated
+            );
+          } //DimmOut->Status
+        } //Dimm
+      } //Channel
+    } //Controller
+  } //Profile
+
+  //
+  // Set the best case timing for all controllers/channels/dimms, for each profile.
+  //
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "    %s%u:", BestCaseString, MAX_PROFILE - 1);
+  for (Profile = STD_PROFILE; Profile < MAX_PROFILE; Profile++) {
+    if (((Profile == XMP_PROFILE1) || (Profile == XMP_PROFILE2)) && (!(Outputs->XmpProfileEnable))) {
+      continue;
+    }
+    for (Controller = 0; Controller < MAX_CONTROLLERS; Controller++) {
+      ControllerOut = &Outputs->Controller[Controller];
+      for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+        ChannelOut = &ControllerOut->Channel[Channel];
+        for (Dimm = 0; Dimm < MAX_DIMMS_IN_CHANNEL; Dimm++) {
+          DimmOut = &ChannelOut->Dimm[Dimm];
+          DimmOut->Timing[Profile].tRTP    = (U16) Actual[Profile];
+          ChannelOut->Timing[Profile].tRTP = (U16) Actual[Profile];
+        }
+      }
+    }
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, " %u", Actual[Profile]);
+  }
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\n");
+
+  return TRUE;
+}
+#endif
+
+#if (MRC_DDR3_LPDDR_SUPPORTED)
+/**
+  @brief
+  Calculate the minimum tWR timing value for the given memory frequency.
+
+    @param[in, out] MrcData - Pointer to MrcData data structure.
+
+    @retval TRUE if there are DIMMs present, otherwise FALSE.
+**/
+static
+BOOL
+GetChannelDimmtWR (
+  IN OUT MrcParameters *const MrcData
+  )
+{
+  const MrcInput        *Inputs;
+  const MrcControllerIn *ControllerIn;
+  const MrcChannelIn    *ChannelIn;
+  const MrcDimmIn       *DimmIn;
+  const MrcSpd          *Spd;
+  const MrcDebug        *Debug;
+  MrcOutput             *Outputs;
+  MrcControllerOut      *ControllerOut;
+  MrcChannelOut         *ChannelOut;
+  MrcDimmOut            *DimmOut;
+  MrcTimeBase           *TimeBase;
+  MrcProfile            Profile;
+  U8                    Controller;
+  U8                    Channel;
+  U8                    Dimm;
+  U32                   tCKmin;
+  U32                   TimingMTB;
+  S32                   MediumTimebase;
+  S32                   FineTimebase;
+  U32                   Actual[MAX_PROFILE];
+  U32                   Calculated;
+  U32                   MaxPossible;
+#if (SUPPORT_XMP == SUPPORT)
+  U32                   Index;
+#endif
+
+  Inputs      = &MrcData->SysIn.Inputs;
+  Outputs     = &MrcData->SysOut.Outputs;
+  Debug       = &Inputs->Debug;
+  MaxPossible = TWRMAXPOSSIBLE;
+
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "  %s:\n  %s\n", tWRString, HeaderString);
+
+  //
+  // Find the smallest timing value for all the given DIMMs, for all the profiles.
+  //
+  for (Profile = STD_PROFILE; Profile < MAX_PROFILE; Profile++) {
+    if (((Profile == XMP_PROFILE1) || (Profile == XMP_PROFILE2)) && (!(Outputs->XmpProfileEnable))) {
+      continue;
+    }
+    Actual[Profile] = 0;
+    for (Controller = 0; Controller < MAX_CONTROLLERS; Controller++) {
+      ControllerIn  = &Inputs->Controller[Controller];
+      ControllerOut = &Outputs->Controller[Controller];
+      for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+        ChannelIn   = &ControllerIn->Channel[Channel];
+        ChannelOut  = &ControllerOut->Channel[Channel];
+        for (Dimm = 0; Dimm < MAX_DIMMS_IN_CHANNEL; Dimm++) {
+          DimmIn  = &ChannelIn->Dimm[Dimm];
+          DimmOut = &ChannelOut->Dimm[Dimm];
+          if (DIMM_PRESENT == DimmOut->Status) {
+            Spd            = &DimmIn->Spd;
+            Calculated     = 0;
+            tCKmin         = DimmOut->Timing[Profile].tCK;
+            TimeBase       = &ChannelOut->TimeBase[Dimm][Profile];
+            MediumTimebase = TimeBase->Mtb;
+            FineTimebase   = TimeBase->Ftb;
+            switch (Profile) {
+              case XMP_PROFILE1:
+              case XMP_PROFILE2:
+#if (SUPPORT_XMP == SUPPORT)
+                if (((Profile == XMP_PROFILE1) && ((DimmOut->XmpSupport & 1) != 0)) ||
+                    ((Profile == XMP_PROFILE2) && ((DimmOut->XmpSupport & 2) != 0))) {
+                  Index = Profile - XMP_PROFILE1;
+                  TimingMTB = Spd->Ddr3.Xmp.Data[Index].tWRmin.Bits.tWRmin;
+                  Calculated = (tCKmin == 0) ? 0 : ((MediumTimebase * TimingMTB) + (tCKmin - 1)) / tCKmin;
+                } else {
+                  Calculated = 0;
+                }
+#endif //SUPPORT_XMP
+                break;
+              case USER_PROFILE:
+                if (DimmIn->Timing.tWR > 0) {
+                  Calculated = DimmIn->Timing.tWR;
+                  break;
+                } else {
+                  // In AUTO mode, so no break.
+                }
+              case STD_PROFILE:
+              default:
+                if (tCKmin > 0) {
+                  TimingMTB = Spd->Ddr3.General.tWRmin.Bits.tWRmin;
+                  Calculated = (tCKmin == 0) ? 0 : ((MediumTimebase * TimingMTB) + (tCKmin - 1)) / tCKmin;
+                }
+                break;
+            } //switch
+
+            //
+            // Special case, tWRmin values of 9, 11, 13, and 15 are not supported by DDR3 Mode Register 0 (MR0).
+            // If we see one of these values, then add one clock to it in order to make it valid.
+            //
+            if ((9 == Calculated) || (11 == Calculated) || (13 == Calculated) || (15 == Calculated)) {
+              Calculated++;
+            } else {
+              Calculated = MIN (Calculated, MaxPossible);
+            }
+            Actual[Profile] = MAX (Actual[Profile], Calculated);
+            MRC_DEBUG_MSG (
+              Debug,
+              MSG_LEVEL_NOTE,
+              "  % 7u % 10u % 8u % 5u %6u\n",
+              Profile,
+              Controller,
+              Channel,
+              Dimm,
+              Calculated
+            );
+          } //DimmOut->Status
+        } //Dimm
+      } //Channel
+    } //Controller
+  } //Profile
+
+  //
+  // Set the best case timing for all controllers/channels/dimms, for each profile.
+  //
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "    %s%u:", BestCaseString, MAX_PROFILE - 1);
+  for (Profile = STD_PROFILE; Profile < MAX_PROFILE; Profile++) {
+    if (((Profile == XMP_PROFILE1) || (Profile == XMP_PROFILE2)) && (!(Outputs->XmpProfileEnable))) {
+      continue;
+    }
+    for (Controller = 0; Controller < MAX_CONTROLLERS; Controller++) {
+      ControllerOut = &Outputs->Controller[Controller];
+      for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+        ChannelOut = &ControllerOut->Channel[Channel];
+        for (Dimm = 0; Dimm < MAX_DIMMS_IN_CHANNEL; Dimm++) {
+          DimmOut = &ChannelOut->Dimm[Dimm];
+          DimmOut->Timing[Profile].tWR    = (U16) Actual[Profile];
+          ChannelOut->Timing[Profile].tWR = (U16) Actual[Profile];
+        }
+      }
+    }
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, " %u", Actual[Profile]);
+  }
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\n");
+
+  return TRUE;
+}
+#endif
+
+#if (MRC_DDR3_LPDDR_SUPPORTED)
+/**
+  @brief
+  Calculate the minimum tWTR timing value for the given memory frequency.
+
+    @param[in, out] MrcData - Pointer to MrcData data structure.
+
+    @retval TRUE if there are DIMMs present, otherwise FALSE.
+**/
+static
+BOOL
+GetChannelDimmtWTR (
+  IN OUT MrcParameters *const MrcData
+  )
+{
+  const MrcInput        *Inputs;
+  const MrcControllerIn *ControllerIn;
+  const MrcChannelIn    *ChannelIn;
+  const MrcDimmIn       *DimmIn;
+  const MrcSpd          *Spd;
+  const MrcDebug        *Debug;
+  MrcOutput             *Outputs;
+  MrcControllerOut      *ControllerOut;
+  MrcChannelOut         *ChannelOut;
+  MrcDimmOut            *DimmOut;
+  MrcTimeBase           *TimeBase;
+  MrcProfile            Profile;
+  U8                    Controller;
+  U8                    Channel;
+  U8                    Dimm;
+  U32                   tCKmin;
+  U32                   TimingMTB;
+  S32                   MediumTimebase;
+  S32                   FineTimebase;
+  U32                   Actual[MAX_PROFILE];
+  U32                   Calculated;
+#if (SUPPORT_XMP == SUPPORT)
+  U32                   Index;
+#endif
+
+  Inputs  = &MrcData->SysIn.Inputs;
+  Outputs = &MrcData->SysOut.Outputs;
+  Debug   = &Inputs->Debug;
+
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "  %s:\n  %s\n", tWTRString, HeaderString);
+
+  //
+  // Find the smallest timing value for all the given DIMMs, for all the profiles.
+  //
+  for (Profile = STD_PROFILE; Profile < MAX_PROFILE; Profile++) {
+    if (((Profile == XMP_PROFILE1) || (Profile == XMP_PROFILE2)) && (!(Outputs->XmpProfileEnable))) {
+      continue;
+    }
+    Actual[Profile] = 0;
+    for (Controller = 0; Controller < MAX_CONTROLLERS; Controller++) {
+      ControllerIn  = &Inputs->Controller[Controller];
+      ControllerOut = &Outputs->Controller[Controller];
+      for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+        ChannelIn   = &ControllerIn->Channel[Channel];
+        ChannelOut  = &ControllerOut->Channel[Channel];
+        for (Dimm = 0; Dimm < MAX_DIMMS_IN_CHANNEL; Dimm++) {
+          DimmIn  = &ChannelIn->Dimm[Dimm];
+          DimmOut = &ChannelOut->Dimm[Dimm];
+          if (DIMM_PRESENT == DimmOut->Status) {
+            Spd            = &DimmIn->Spd;
+            Calculated     = 0;
+            tCKmin         = DimmOut->Timing[Profile].tCK;
+            TimeBase       = &ChannelOut->TimeBase[Dimm][Profile];
+            MediumTimebase = TimeBase->Mtb;
+            FineTimebase   = TimeBase->Ftb;
+            switch (Profile) {
+              case XMP_PROFILE1:
+              case XMP_PROFILE2:
+#if (SUPPORT_XMP == SUPPORT)
+                if (((Profile == XMP_PROFILE1) && ((DimmOut->XmpSupport & 1) != 0)) ||
+                    ((Profile == XMP_PROFILE2) && ((DimmOut->XmpSupport & 2) != 0))) {
+                  Index = Profile - XMP_PROFILE1;
+                  TimingMTB = Spd->Ddr3.Xmp.Data[Index].tWTRmin.Bits.tWTRmin;
+                  Calculated = (tCKmin == 0) ? 0 : ((MediumTimebase * TimingMTB) + (tCKmin - 1)) / tCKmin;
+                } else {
+                  Calculated = 0;
+                }
+#endif //SUPPORT_XMP
+                break;
+              case USER_PROFILE:
+                if (DimmIn->Timing.tWTR > 0) {
+                  Calculated = DimmIn->Timing.tWTR;
+                  break;
+                } else {
+                  // In AUTO mode, so no break.
+                }
+              case STD_PROFILE:
+              default:
+                if (tCKmin > 0) {
+                  TimingMTB = Spd->Ddr3.General.tWTRmin.Bits.tWTRmin;
+                  Calculated = (tCKmin == 0) ? 0 : ((MediumTimebase * TimingMTB) + (tCKmin - 1)) / tCKmin;
+                }
+                break;
+            } //switch
+
+            Calculated = MIN (Calculated, TWTRMAXPOSSIBLE);
+            Actual[Profile] = MAX (Actual[Profile], Calculated);
+            MRC_DEBUG_MSG (
+              Debug,
+              MSG_LEVEL_NOTE,
+              "  % 7u % 10u % 8u % 5u %6u\n",
+              Profile,
+              Controller,
+              Channel,
+              Dimm,
+              Calculated
+            );
+          } //DimmOut->Status
+        } //Dimm
+      } //Channel
+    } //Controller
+  } //Profile
+
+  //
+  // Set the best case timing for all controllers/channels/dimms, for each profile.
+  //
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "    %s%u:", BestCaseString, MAX_PROFILE - 1);
+  for (Profile = STD_PROFILE; Profile < MAX_PROFILE; Profile++) {
+    if (((Profile == XMP_PROFILE1) || (Profile == XMP_PROFILE2)) && (!(Outputs->XmpProfileEnable))) {
+      continue;
+    }
+    for (Controller = 0; Controller < MAX_CONTROLLERS; Controller++) {
+      ControllerOut = &Outputs->Controller[Controller];
+      for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+        ChannelOut = &ControllerOut->Channel[Channel];
+        for (Dimm = 0; Dimm < MAX_DIMMS_IN_CHANNEL; Dimm++) {
+          DimmOut = &ChannelOut->Dimm[Dimm];
+          DimmOut->Timing[Profile].tWTR    = (U16) Actual[Profile];
+          ChannelOut->Timing[Profile].tWTR = (U16) Actual[Profile];
+        }
+      }
+    }
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, " %u", Actual[Profile]);
+  }
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\n");
+
+  return TRUE;
+}
+#endif
+
+/**
+  @brief
+  Calculate the minimum command rate mode value for the given channel.
+
+    @param[in, out] MrcData - Pointer to MrcData data structure.
+
+    @retval TRUE if there are DIMMs present, otherwise FALSE.
+**/
+static
+BOOL
+GetChannelDimmNmode (
+  IN OUT MrcParameters *const MrcData
+  )
+{
+  const MrcInput        *Inputs;
+  const MrcControllerIn *ControllerIn;
+  const MrcChannelIn    *ChannelIn;
+  const MrcDimmIn       *DimmIn;
+  const MrcSpd          *Spd;
+  const MrcDebug        *Debug;
+  MrcOutput             *Outputs;
+  MrcControllerOut      *ControllerOut;
+  MrcChannelOut         *ChannelOut;
+  MrcDimmOut            *DimmOut;
+  MrcTimeBase           *TimeBase;
+  MrcProfile            Profile;
+  U8                    Controller;
+  U8                    Channel;
+  U8                    Dimm;
+  U32                   tCKmin;
+  S32                   MediumTimebase;
+  S32                   FineTimebase;
+  U32                   Actual[MAX_PROFILE];
+  U32                   Calculated;
+#if (SUPPORT_XMP == SUPPORT)
+  U32                   Index;
+  U32                   TimingMTB;
+#endif
+
+  Inputs  = &MrcData->SysIn.Inputs;
+  Outputs = &MrcData->SysOut.Outputs;
+  Debug   = &Inputs->Debug;
+
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "  %s:\n  %s\n", NmodeString, HeaderString);
+
+  //
+  // Find the smallest timing value for all the given DIMMs, for all the profiles.
+  //
+  for (Profile = STD_PROFILE; Profile < MAX_PROFILE; Profile++) {
+    if (((Profile == XMP_PROFILE1) || (Profile == XMP_PROFILE2)) && (!(Outputs->XmpProfileEnable))) {
+      continue;
+    }
+    Actual[Profile] = (Profile < XMP_PROFILE1) ? NMODEMINPOSSIBLE : 0;
+    for (Controller = 0; Controller < MAX_CONTROLLERS; Controller++) {
+      ControllerIn  = &Inputs->Controller[Controller];
+      ControllerOut = &Outputs->Controller[Controller];
+      for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+        ChannelIn   = &ControllerIn->Channel[Channel];
+        ChannelOut  = &ControllerOut->Channel[Channel];
+        for (Dimm = 0; Dimm < MAX_DIMMS_IN_CHANNEL; Dimm++) {
+          DimmIn  = &ChannelIn->Dimm[Dimm];
+          DimmOut = &ChannelOut->Dimm[Dimm];
+          if (DIMM_PRESENT == DimmOut->Status) {
+            Spd            = &DimmIn->Spd;
+            Calculated     = 2;
+            tCKmin         = DimmOut->Timing[Profile].tCK;
+            TimeBase       = &ChannelOut->TimeBase[Dimm][Profile];
+            MediumTimebase = TimeBase->Mtb;
+            FineTimebase   = TimeBase->Ftb;
+            switch (Profile) {
+              case XMP_PROFILE1:
+              case XMP_PROFILE2:
+#if (SUPPORT_XMP == SUPPORT)
+                if (((Profile == XMP_PROFILE1) && ((DimmOut->XmpSupport & 1) != 0)) ||
+                    ((Profile == XMP_PROFILE2) && ((DimmOut->XmpSupport & 2) != 0))) {
+                  Index = Profile - XMP_PROFILE1;
+                    TimingMTB = Spd->Ddr3.Xmp.Data[Index].SystemCmdRate.Bits.NMode;
+                  if (tCKmin == 0) {
+                    Calculated = 0;
+                  } else {
+                    Calculated = ((MediumTimebase * TimingMTB) + (tCKmin - 1)) / tCKmin;
+                    if (Calculated == 0) {
+                      Calculated = 2;
+                    }
+                  }
+                } else {
+                  Calculated = 0;
+                }
+#endif //SUPPORT_XMP
+                break;
+              case USER_PROFILE:
+                if (DimmIn->Timing.NMode > 0) {
+                  Calculated = DimmIn->Timing.NMode;
+                  break;
+                } else {
+                  // In AUTO mode, so no break.
+                }
+              case STD_PROFILE:
+              default:
+                Calculated = NMODEMINPOSSIBLE;
+                break;
+            } //switch
+
+            Actual[Profile] = MAX (Actual[Profile], Calculated);
+            MRC_DEBUG_MSG (
+              Debug,
+              MSG_LEVEL_NOTE,
+              "  % 7u % 10u % 8u % 5u %6u\n",
+              Profile,
+              Controller,
+              Channel,
+              Dimm,
+              Calculated
+            );
+          } //DimmOut->Status
+        } //Dimm
+      } //Channel
+    } //Controller
+  } //Profile
+
+  //
+  // Set the best case timing for all controllers/channels/dimms, for each profile.
+  //
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "    %s%u:", BestCaseString, MAX_PROFILE - 1);
+  for (Profile = STD_PROFILE; Profile < MAX_PROFILE; Profile++) {
+    if (((Profile == XMP_PROFILE1) || (Profile == XMP_PROFILE2)) && (!(Outputs->XmpProfileEnable))) {
+      continue;
+    }
+    for (Controller = 0; Controller < MAX_CONTROLLERS; Controller++) {
+      ControllerOut = &Outputs->Controller[Controller];
+      for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+        ChannelOut = &ControllerOut->Channel[Channel];
+        for (Dimm = 0; Dimm < MAX_DIMMS_IN_CHANNEL; Dimm++) {
+          DimmOut = &ChannelOut->Dimm[Dimm];
+          DimmOut->Timing[Profile].NMode    = (U16) Actual[Profile];
+          ChannelOut->Timing[Profile].NMode = (U16) Actual[Profile];
+        }
+      }
+    }
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, " %u", Actual[Profile]);
+  }
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\n");
+
+  return TRUE;
+}
+
+/**
+  @brief
+  Calculate the VDD voltage value for the given channel.
+
+    @param[in, out] MrcData - Pointer to MrcData data structure.
+
+    @retval TRUE if there are DIMMs present, otherwise FALSE.
+**/
+static
+BOOL
+GetChannelDimmVdd (
+  IN OUT MrcParameters *const MrcData
+  )
+{
+  const MrcInput                        *Inputs;
+  const MrcControllerIn                 *ControllerIn;
+  const MrcChannelIn                    *ChannelIn;
+  const MrcDimmIn                       *DimmIn;
+  const MrcSpd                          *Spd;
+  const MrcDebug                        *Debug;
+  const SPD_EXTREME_MEMORY_PROFILE_DATA *Xmp;
+  MrcOutput                             *Outputs;
+  MrcControllerOut                      *ControllerOut;
+  MrcChannelOut                         *ChannelOut;
+  MrcDimmOut                            *DimmOut;
+  MrcProfile                            Profile;
+  SpdVddFlag                            VddFlag;
+  MrcCpuModel                           CpuModel;
+  U32                                   Actual[MAX_PROFILE];
+  U32                                   Calculated;
+  U8                                    Controller;
+  U8                                    Channel;
+  U8                                    Dimm;
+#if (SUPPORT_XMP == SUPPORT)
+  U32                                   Index;
+#endif
+
+  Inputs   = &MrcData->SysIn.Inputs;
+  Outputs  = &MrcData->SysOut.Outputs;
+  Debug    = &Inputs->Debug;
+  CpuModel = MrcData->SysIn.Inputs.CpuModel;
+
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "  %s:\n  %s\n", VddString, HeaderString);
+
+  //
+  // Find the best case voltage value for all the given DIMMs, for all the profiles.
+  //
+  for (Profile = STD_PROFILE; Profile < MAX_PROFILE; Profile++) {
+    if (((Profile == XMP_PROFILE1) || (Profile == XMP_PROFILE2)) && (!(Outputs->XmpProfileEnable))) {
+      continue;
+    }
+    Actual[Profile] = (Profile < XMP_PROFILE1) ? VDD_1_20 : 0;
+    for (Controller = 0; Controller < MAX_CONTROLLERS; Controller++) {
+      ControllerIn  = &Inputs->Controller[Controller];
+      ControllerOut = &Outputs->Controller[Controller];
+      for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+        ChannelIn   = &ControllerIn->Channel[Channel];
+        ChannelOut  = &ControllerOut->Channel[Channel];
+        for (Dimm = 0; Dimm < MAX_DIMMS_IN_CHANNEL; Dimm++) {
+          DimmIn  = &ChannelIn->Dimm[Dimm];
+          DimmOut = &ChannelOut->Dimm[Dimm];
+          if (DIMM_PRESENT == DimmOut->Status) {
+            Spd        = &DimmIn->Spd;
+            Calculated = VDD_1_50;
+            switch (Profile) {
+              case XMP_PROFILE1:
+              case XMP_PROFILE2:
+#if (SUPPORT_XMP == SUPPORT)
+                if (((Profile == XMP_PROFILE1) && ((DimmOut->XmpSupport & 1) != 0)) ||
+                    ((Profile == XMP_PROFILE2) && ((DimmOut->XmpSupport & 2) != 0))) {
+                  Index = Profile - XMP_PROFILE1;
+                    Xmp = &Spd->Ddr3.Xmp.Data[Index];
+                  Calculated  = XMP_VDD_INCREMENT * Xmp->Vdd.Bits.Decimal;
+                  Calculated  = MIN (Calculated, XMP_VDD_INTEGER - 1);
+                  Calculated += (XMP_VDD_INTEGER * Xmp->Vdd.Bits.Integer);
+                  Calculated  = MAX (Calculated, XMP_VDD_MIN_POSSIBLE);
+                  Calculated  = MIN (Calculated, XMP_VDD_MAX_POSSIBLE);
+                } else {
+                  Calculated = 0;
+                }
+#endif //SUPPORT_XMP
+                break;
+              case USER_PROFILE:
+                if (Inputs->VddVoltage > 0) {
+                  Calculated = Inputs->VddVoltage;
+                  break;
+                } else {
+                  // In AUTO mode, so no break.
+                }
+              case STD_PROFILE:
+              default:
+                  VddFlag.Bits.Vdd1_50 = ~(Spd->Ddr3.General.ModuleNominalVoltage.Bits.OperationAt1_50);
+                  VddFlag.Bits.Vdd1_35 = Spd->Ddr3.General.ModuleNominalVoltage.Bits.OperationAt1_35;
+                  VddFlag.Bits.Vdd1_25 = Spd->Ddr3.General.ModuleNominalVoltage.Bits.OperationAt1_25;
+#if (VDDMINPOSSIBLE <= 1350)
+                  if ((CpuModel == cmHSW_ULT && PlatformSupport.VddMin.UltSupport <= 1350) ||
+                    ((CpuModel == cmHSW || CpuModel == cmCRW) && PlatformSupport.VddMin.TradSupport <= 1350 )) {
+                      if (VddFlag.Bits.Vdd1_35) {
+                        Calculated = VDD_1_35;
+                      }
+                  }
+#endif // VDDMINPOSSIBLE
+#if (VDDMINPOSSIBLE <= 1200)
+                  if ((CpuModel == cmHSW_ULT && PlatformSupport.VddMin.UltSupport <= 1200) ||
+                    ((CpuModel == cmHSW || CpuModel == cmCRW) && PlatformSupport.VddMin.TradSupport <= 1200 )) {
+                      if (VddFlag.Bits.Vdd1_25) {
+                        Calculated = VDD_1_20;
+                      }
+                  }
+#endif // VDDMINPOSSIBLE
+                  if ((Profile == STD_PROFILE) && (Inputs->BoardType == btCRBDT)) {
+                    Calculated = VDD_1_50;
+                  }
+                break;
+            } //switch
+
+            Actual[Profile] = MAX (Actual[Profile], Calculated);
+            MRC_DEBUG_MSG (
+              Debug,
+              MSG_LEVEL_NOTE,
+              "  % 7u % 10u % 8u % 5u %4u\n",
+              Profile,
+              Controller,
+              Channel,
+              Dimm,
+              Calculated
+            );
+          } //DimmOut->Status
+        } //Dimm
+      } //Channel
+    } //Controller
+  } //Profile
+
+  //
+  // Set the best case voltage for all controllers/channels/dimms, for each profile.
+  //
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "    %s%u:", BestCaseString, MAX_PROFILE - 1);
+  for (Profile = STD_PROFILE; Profile < MAX_PROFILE; Profile++) {
+    if (((Profile == XMP_PROFILE1) || (Profile == XMP_PROFILE2)) && (!(Outputs->XmpProfileEnable))) {
+      continue;
+    }
+    for (Controller = 0; Controller < MAX_CONTROLLERS; Controller++) {
+      ControllerOut = &Outputs->Controller[Controller];
+      for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+        ChannelOut = &ControllerOut->Channel[Channel];
+        for (Dimm = 0; Dimm < MAX_DIMMS_IN_CHANNEL; Dimm++) {
+          DimmOut = &ChannelOut->Dimm[Dimm];
+          Outputs->VddVoltage[Profile] = (MrcVddSelect) Actual[Profile];
+          DimmOut->VddVoltage[Profile] = (MrcVddSelect) Actual[Profile];
+        }
+      }
+    }
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, " %u", Actual[Profile]);
+  }
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\n");
+
+  return TRUE;
+}
+
+/**
+  @brief
+  Analyze the given DIMM SPD data to determine DIMM presence and configuration.
+
+    @param[in, out] MrcData - Pointer to MRC global data structure.
+    @param[in] Controller   - Current controller number.
+    @param[in] Channel      - Current channel number.
+    @param[in] Dimm         - Current DIMM number.
+
+    @retval mrcSuccess if DIMM is present otherwise mrcDimmNotExist.
+**/
+static
+MrcStatus
+SpdDimmRecognition (
+  IN OUT MrcParameters *const MrcData,
+  IN  const U8                Controller,
+  IN  U8                      Channel,
+  IN  U8                      Dimm
+  )
+{
+    const SpdRecogCallTable CallTable[] = {
+    {ValidDimm},
+    {ValidSdramDeviceWidth},
+    {ValidPrimaryWidth},
+    {GetRankCount},
+    {ValidBank},
+    {GetDimmSize},
+    {ValidRowSize},
+    {ValidColumnSize},
+    {ValidEccSupport},
+    {GetAddressMirror},
+    {GetThermalRefreshSupport},
+    {GetReferenceRawCardSupport}
+  };
+  const MrcSpd    *Spd;
+  const U8        *CrcStart;
+  MrcDimmOut      *DimmOut;
+  MrcDimmIn       *DimmIn;
+  BOOL            Status;
+  U32             CrcSize;
+  U8              Index;
+
+  Spd     = &MrcData->SysIn.Inputs.Controller[Controller].Channel[Channel].Dimm[Dimm].Spd;
+  DimmIn  = &MrcData->SysIn.Inputs.Controller[Controller].Channel[Channel].Dimm[Dimm];
+  DimmOut = &MrcData->SysOut.Outputs.Controller[Controller].Channel[Channel].Dimm[Dimm];
+  DimmOut->Status = DIMM_NOT_PRESENT;
+  if (DIMM_PRESENT == DimmPresence (MrcData, Spd, sizeof (MrcSpd))) {
+    Status = TRUE;
+    for (Index = 0; (Status == TRUE) && (Index < (sizeof (CallTable) / sizeof (CallTable[0]))); Index++) {
+      Status &= CallTable[Index].mrc_task (MrcData, Spd, DimmOut);
+    }
+    if (Status == FALSE) {
+      DimmOut->Status = DIMM_DISABLED;
+      return mrcDimmNotExist;
+    }
+    DimmOut->Status = DIMM_PRESENT;
+    CrcStart = MrcSpdCrcArea (MrcData, Controller, Channel, Dimm, &CrcSize);
+    GetDimmCrc ((const U8 *const) CrcStart, CrcSize, &DimmOut->Crc);
+  } else {
+    return mrcDimmNotExist;
+  }
+
+  if (DIMM_DISABLED == DimmIn->Status) {
+    DimmOut->Status = DIMM_DISABLED;
+  }
+
+  return mrcSuccess;
+}
+
+/**
+  @brief
+  Calculate the timing of all DIMMs on all channels.
+
+    @param[in, out] MrcData - The MRC "global data".
+
+    @retval mrcSuccess on success, mrcDimmNotExist if no DIMMs found.
+**/
+static
+MrcStatus
+SpdTimingCalculation (
+  IN OUT MrcParameters *const MrcData
+  )
+{
+  const SpdTimeCallTable CallTable[] = {
+    {GetChannelDimmTimeBase}, // Note: This must be done first as all other calculations are based on this.
+    {GetChannelDimmtCK},      // Note: This must be done second as all other calculations are based on this.
+    {GetChannelDimmtAA},
+    {GetChannelDimmtCWL},
+    {GetChannelDimmtRAS},
+    {GetChannelDimmtRC},
+    {GetChannelDimmtRCD},
+    {GetChannelDimmtREFI},
+    {GetChannelDimmtRFC},
+    {GetChannelDimmtRP},
+#if (SUPPORT_LPDDR3 == SUPPORT)
+    {GetChannelDimmtRPab},    // Note: This must be done after GetChannelDimmtRP
+#endif
+#if (MRC_DDR3_LPDDR_SUPPORTED)
+    {GetChannelDimmtFAW},
+    {GetChannelDimmtRRD},
+    {GetChannelDimmtRTP},
+    {GetChannelDimmtWR},
+    {GetChannelDimmtWTR},
+#endif
+    {GetChannelDimmNmode},
+    {GetChannelDimmVdd}
+  };
+  BOOL          Status;
+  U8            Index;
+#if (SUPPORT_FORCE == SUPPORT)
+  MrcChannelOut *ChannelOut;
+  MrcDimmOut    *DimmOut;
+  U16           Value;
+  U8            Controller;
+  U8            Channel;
+  U8            Dimm;
+#endif
+
+  //
+  // Find the "least common denominator" timing across the DIMMs.
+  // tAA must be done first before any other timings are calculated.
+  //
+  Status = TRUE;
+  for (Index = 0; (Status == TRUE) && (Index < (sizeof (CallTable) / sizeof (SpdTimeCallTable))); Index++) {
+    Status &= CallTable[Index].mrc_task (MrcData);
+  }
+
+#if (SUPPORT_FORCE == SUPPORT)
+  if (Status == TRUE) {
+    //
+    // Force tCLmin, tRCDmin, tRPmin to be the same "least common denominator" value.
+    //
+    Value = 0;
+    for (Controller = 0; Controller < MAX_CONTROLLERS; Controller++) {
+      for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+        for (Dimm = 0; Dimm < MAX_DIMMS_IN_CHANNEL; Dimm++) {
+          DimmOut = &Outputs->Controller[Controller].Channel[Channel].Dimm[Dimm];
+          if (DIMM_PRESENT == DimmOut->Status) {
+            Value = MAX (Value, DimmOut->Timing.tRCD);
+            Value = MAX (Value, DimmOut->Timing.tRP);
+            Value = MAX (Value, DimmOut->Timing.tCL);
+          }
+        }
+      }
+    }
+
+    for (Controller = 0; Controller < MAX_CONTROLLERS; Controller++) {
+      for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+        ChannelOut = &Outputs->Controller[Controller].Channel[Channel];
+        for (Dimm = 0; Dimm < MAX_DIMMS_IN_CHANNEL; Dimm++) {
+          DimmOut = &ChannelOut->Dimm[Dimm];
+          if (DIMM_PRESENT == DimmOut->Status) {
+            ChannelOut->Timing.tRCD = Value;
+            ChannelOut->Timing.tRP  = Value;
+            ChannelOut->Timing.tCL  = Value;
+            DimmOut->Timing.tRCD    = Value;
+            DimmOut->Timing.tRP     = Value;
+            DimmOut->Timing.tCL     = Value;
+          }
+        }
+      }
+    }
+  }
+#endif
+  return (Status == FALSE) ? mrcDimmNotExist : mrcSuccess;
+}
+
+/**
+  @brief
+  Determine the starting address and size of the SPD area to generate a CRC.
+
+    @param[in, out] MrcData    - The MRC "global data".
+    @param[in]      Controller - Controller index.
+    @param[in]      Channel    - Channel index.
+    @param[in]      Dimm       - Dimm index.
+    @param[out]     CrcSize    - Location to write CRC block size.
+
+    @retval The starting address of the CRC block.
+**/
+const U8 *
+MrcSpdCrcArea (
+  IN OUT MrcParameters *const MrcData,
+  IN     U8                   Controller,
+  IN     U8                   Channel,
+  IN     U8                   Dimm,
+  OUT    U32           *const CrcSize
+  )
+{
+  const MrcDimmIn *DimmIn;
+  MrcDimmOut      *DimmOut;
+  const U8        *CrcStart;
+
+  DimmIn   = &MrcData->SysIn.Inputs.Controller[Controller].Channel[Channel].Dimm[Dimm];
+  DimmOut  = &MrcData->SysOut.Outputs.Controller[Controller].Channel[Channel].Dimm[Dimm];
+  CrcStart = NULL;
+
+    CrcStart = (const U8 *) &DimmIn->Spd.Ddr3.ModuleId;
+    *CrcSize = SPD3_MANUF_SIZE;
+  return (CrcStart);
+}
+
+/**
+  @brief
+  Process the SPD information for all DIMMs on all channels.
+
+    @param[in, out] MrcData - The MRC "global data".
+
+    @retval mrcSuccess on success, mrcDimmNotExist if no DIMMs found.
+**/
+MrcStatus
+MrcSpdProcessing (
+  IN OUT MrcParameters *const MrcData
+  )
+{
+  const MrcDebug        *Debug;
+  const MrcInput        *Inputs;
+  const MrcControllerIn *ControllerIn;
+  const MrcChannelIn    *ChannelIn;
+  const MrcDimmIn       *DimmIn;
+  MrcStatus             Status;
+  MrcOutput             *Outputs;
+  MrcControllerOut      *ControllerOut;
+  MrcChannelOut         *ChannelOut;
+  MrcDimmOut            *DimmOut;
+  MrcModuleType         ModuleType;
+  U8                    Controller;
+  U8                    Channel;
+  U8                    Dimm;
+  U32                   DimmCount;
+  U8                    ValidRankBitMask;
+
+  Inputs  = &MrcData->SysIn.Inputs;
+  Debug   = &Inputs->Debug;
+  Outputs = &MrcData->SysOut.Outputs;
+  Status  = mrcDimmNotExist;
+
+  //
+  // Scan thru each DIMM to see if it is a valid DIMM and to get its configuration.
+  //
+  ModuleType = MRC_MODULE_TYPE_UNKNOWN;
+  DimmCount  = 0;
+  for (Controller = 0; Controller < MAX_CONTROLLERS; Controller++) {
+    ControllerIn  = &Inputs->Controller[Controller];
+    ControllerOut = &Outputs->Controller[Controller];
+    for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+      ChannelIn   = &ControllerIn->Channel[Channel];
+      ChannelOut  = &ControllerOut->Channel[Channel];
+      for (Dimm = 0; Dimm < MAX_DIMMS_IN_CHANNEL; Dimm++) {
+        DimmIn  = &ChannelIn->Dimm[Dimm];
+        DimmOut = &ChannelOut->Dimm[Dimm];
+        if (DimmIn->Status == DIMM_ENABLED || DimmIn->Status == DIMM_DISABLED) {
+          MRC_DEBUG_MSG (
+            Debug,
+            MSG_LEVEL_NOTE,
+            "SPD Dimm recognition, %s %u/%u/%u\n",
+            CcdString,
+            Controller,
+            Channel,
+            Dimm
+            );
+          if (mrcSuccess == SpdDimmRecognition (MrcData, Controller, Channel, Dimm)) {
+            DimmCount++;
+            if (MRC_DDR_TYPE_UNKNOWN == Outputs->DdrType) {
+              Outputs->DdrType = DimmOut->DdrType;
+            } else if (Outputs->DdrType != DimmOut->DdrType) {
+              Status = mrcMixedDimmSystem;
+            }
+            if (MRC_MODULE_TYPE_UNKNOWN == ModuleType) {
+              ModuleType = DimmOut->ModuleType;
+            } else if (ModuleType != DimmOut->ModuleType) {
+              Status = mrcMixedDimmSystem;
+            }
+            if (Status == mrcMixedDimmSystem) {
+              MRC_DEBUG_MSG (
+                Debug,
+                MSG_LEVEL_ERROR,
+                "%s configuration, system contains a mix of memory types\n",
+                ErrorString
+                );
+              return (Status);
+            }
+          }
+        }
+      }
+    }
+  }
+
+  if (DimmCount > 0) {
+    //
+    // Scan thru each channel to see if it is a valid channel and to get its configuration.
+    //
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "SPD Dimm timing calculation\n");
+    if (mrcSuccess == SpdTimingCalculation (MrcData)) {
+      Outputs->EccSupport = TRUE;
+
+      //
+      // Count up the number of valid DIMMs.
+      //
+      ControllerOut = &Outputs->Controller[0];
+      for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+        ChannelOut              = &ControllerOut->Channel[Channel];
+        ChannelOut->EccSupport  = TRUE;
+        for (Dimm = 0; Dimm < MAX_DIMMS_IN_CHANNEL; Dimm++) {
+          DimmOut = &ChannelOut->Dimm[Dimm];
+          if ((DIMM_PRESENT == DimmOut->Status) || (DIMM_DISABLED == DimmOut->Status)) {
+            ChannelOut->DimmCount++;
+          }
+          if (DIMM_PRESENT == DimmOut->Status) {
+#if (MAX_RANK_IN_CHANNEL > 8)
+#error The next switch statement and ValidRankBitMask needs updated to support additional ranks.
+#endif
+            switch (DimmOut->RankInDIMM) {
+              case 1:
+                ValidRankBitMask = 1;
+                break;
+#if (MAX_RANK_IN_DIMM > 1)
+
+              case 2:
+                ValidRankBitMask = 3;
+                break;
+#endif
+#if (MAX_RANK_IN_DIMM > 2)
+
+              case 3:
+                ValidRankBitMask = 7;
+                break;
+#endif
+#if (MAX_RANK_IN_DIMM > 3)
+
+              case 4:
+                ValidRankBitMask = 15;
+                break;
+#endif
+
+              default:
+                ValidRankBitMask = 0;
+                break;
+            }
+
+            ChannelOut->ValidRankBitMask |= ValidRankBitMask << (Dimm * MAX_RANK_IN_DIMM);
+
+            ChannelOut->EccSupport &= DimmOut->EccSupport;
+            Outputs->EccSupport &= DimmOut->EccSupport;
+          }
+        }
+
+        if ((ChannelOut->DimmCount > 0) && (ChannelOut->ValidRankBitMask > 0)) {
+          ControllerOut->ChannelCount++;
+          ControllerOut->Channel[Channel].Status = CHANNEL_PRESENT;
+        }
+      }
+
+      for (Controller = 0; Controller < MAX_CONTROLLERS; Controller++) {
+        ControllerOut = &Outputs->Controller[Controller];
+        if (ControllerOut->ChannelCount > 0) {
+          ControllerOut->Status = CONTROLLER_PRESENT;
+          Status                = mrcSuccess;
+        }
+      }
+    }
+  }
+
+  return Status;
+}
diff --git a/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/SpdProcessing/MrcSpdProcessing.h b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/SpdProcessing/MrcSpdProcessing.h
new file mode 100644
index 0000000..402530e
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/SpdProcessing/MrcSpdProcessing.h
@@ -0,0 +1,231 @@
+/** @file
+  SPD processing header file.
+
+@copyright
+  Copyright (c) 2010 - 2012 Intel Corporation. All rights reserved.
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement.
+**/
+
+#ifndef _MrcSpdProcessing_h_
+#define _MrcSpdProcessing_h_
+
+#include "MrcTypes.h"
+#include "MrcApi.h"
+#include "MrcGlobal.h"
+#include "MrcCommon.h"
+#include "MrcOemDebugPrint.h"
+
+#pragma pack (push, 1)
+
+///
+/// Local definitions
+///
+#define CRC_SEED                  0
+#define CRC_XOR_MASK              0x1021
+#define TREFIMIN_DDR3             7800000   /// Average periodic refresh interval, in picoseconds (7.8 us for DDR3)
+#define TREFIMIN_LPDDR3           3900000   /// Average periodic refresh interval, in picoseconds (3.9 us for LPDDR3)
+#define TREFIMULTIPLIER           1000      /// tREFI value defined in XMP 1.3 spec is actually in thousands of MTB units.
+#define MRC_TaaMAX                20000000  /// TaaMax is 20ns
+#define MRC_FREQUENCY_MTB_OFFSET  1000000
+#define MRC_FREQUENCY_FTB_OFFSET  1000
+#define MRC_DDR3_800_TCK_MIN      2500000   /// 1/(800/2) femtoseconds
+#define MRC_DDR3_1000_TCK_MIN     2000000   /// 1/(1000/2) femtoseconds
+#define MRC_DDR3_1067_TCK_MIN     1875000   /// 1/(1067/2) femtoseconds
+#define MRC_DDR3_1200_TCK_MIN     1666666   /// 1/(1200/2) femtoseconds
+#define MRC_DDR3_1333_TCK_MIN     1500000   /// 1/(1333/2) femtoseconds
+#define MRC_DDR3_1400_TCK_MIN     1428571   /// 1/(1400/2) femtoseconds
+#define MRC_DDR3_1600_TCK_MIN     1250000   /// 1/(1600/2) femtoseconds
+#define MRC_DDR3_1800_TCK_MIN     1111111   /// 1/(1800/2) femtoseconds
+#define MRC_DDR3_1867_TCK_MIN     1071428   /// 1/(1867/2) femtoseconds
+#define MRC_DDR3_2000_TCK_MIN     1000000   /// 1/(2000/2) femtoseconds
+#define MRC_DDR3_2133_TCK_MIN     937500    /// 1/(2133/2) femtoseconds
+#define MRC_DDR3_2200_TCK_MIN     909090    /// 1/(2200/2) femtoseconds
+#define MRC_DDR3_2400_TCK_MIN     833333    /// 1/(2400/2) femtoseconds
+#define MRC_DDR3_2600_TCK_MIN     769230    /// 1/(2600/2) femtoseconds
+#define MRC_DDR3_2667_TCK_MIN     750000    /// 1/(2667/2) femtoseconds
+#define MRC_DDR3_2800_TCK_MIN     714285    /// 1/(2800/2) femtoseconds
+
+///
+/// SPD field definitions
+///
+#define MRC_SPD_DDR3_SDRAM_TYPE_NUMBER      (0x0B)
+#define MRC_SPD_LPDDR3_SDRAM_TYPE_NUMBER    (0xF1)
+
+#define MRC_SPD_RDIMM_TYPE_NUMBER           (0x01)
+#define MRC_SPD_UDIMM_TYPE_NUMBER           (0x02)
+#define MRC_SPD_SODIMM_TYPE_NUMBER          (0x03)
+
+#define MRC_SPD_DDR3_SDRAM_BANK_8           (0x00)
+#define MRC_SPD_DDR3_SDRAM_BANK_16          (0x01)
+#define MRC_SPD_DDR3_SDRAM_BANK_32          (0x02)
+#define MRC_SPD_DDR3_SDRAM_BANK_64          (0x03)
+
+#define MRC_SPD_SDRAM_DENSITY_12            (0x00)
+#define MRC_SPD_SDRAM_DENSITY_13            (0x01)
+#define MRC_SPD_SDRAM_DENSITY_14            (0x02)
+#define MRC_SPD_SDRAM_DENSITY_15            (0x03)
+#define MRC_SPD_SDRAM_DENSITY_16            (0x04)
+
+#define MRC_SPD_SDRAM_ROW_12                (0x00)
+#define MRC_SPD_SDRAM_ROW_13                (0x01)
+#define MRC_SPD_SDRAM_ROW_14                (0x02)
+#define MRC_SPD_SDRAM_ROW_15                (0x03)
+#define MRC_SPD_SDRAM_ROW_16                (0x04)
+
+#define MRC_SPD_SDRAM_COLUMN_9              (0x00)
+#define MRC_SPD_SDRAM_COLUMN_10             (0x01)
+#define MRC_SPD_SDRAM_COLUMN_11             (0x02)
+#define MRC_SPD_SDRAM_COLUMN_12             (0x03)
+
+#define MRC_SPD_SDRAM_DEVICE_WIDTH_4        (0x00)
+#define MRC_SPD_SDRAM_DEVICE_WIDTH_8        (0x01)
+#define MRC_SPD_SDRAM_DEVICE_WIDTH_16       (0x02)
+#define MRC_SPD_SDRAM_DEVICE_WIDTH_32       (0x03)
+
+#define MRC_SPD_PRIMARY_BUS_WIDTH_8         (0x00)
+#define MRC_SPD_PRIMARY_BUS_WIDTH_16        (0x01)
+#define MRC_SPD_PRIMARY_BUS_WIDTH_32        (0x02)
+#define MRC_SPD_PRIMARY_BUS_WIDTH_64        (0x03)
+
+#define MRC_SPD_BUS_WIDTH_EXTENSION_0       (0x00)
+#define MRC_SPD_BUS_WIDTH_EXTENSION_8       (0x01)
+
+#define MRC_SPD_CL_SUPPORTED_MASK           (0x7FFF)
+
+#define XMP_VDD_INTEGER                     (1000)
+#define XMP_VDD_INCREMENT                   (50)
+#define XMP_VDD_MIN_POSSIBLE                (1200)
+#define XMP_VDD_MAX_POSSIBLE                (1650)
+
+#define MRC_SPD_REF_RAW_CARD_SIZE           (5)
+#define MRC_SPD_REF_RAW_CARD_EXT_OFFSET     (7)
+
+#define XMP_ID_STRING                       (0x4A0C)
+
+typedef struct {
+  U32           tCK;
+  MrcFrequency  Frequency;
+  U8            RefClkFlag;  // 0 = invalid freq. 1 = valid only at 133 RefClk, 2 = valid only at 100 RefClk, 3 = valid at both.
+} TRangeTable;
+
+typedef struct {
+  BOOL (*mrc_task) (MrcParameters * const MrcData);
+} SpdTimeCallTable;
+
+typedef struct {
+  BOOL (*mrc_task) (MrcParameters * const MrcData, const MrcSpd * const Spd, MrcDimmOut * const DimmOut);
+} SpdRecogCallTable;
+
+typedef union {
+  struct {
+    U8  Vdd1_20 : 1;
+    U8  Vdd1_25 : 1;
+    U8  Vdd1_35 : 1;
+    U8  Vdd1_50 : 1;
+    U8          : 4;
+  } Bits;
+  U8 Data;
+} SpdVddFlag;
+
+  typedef struct {
+    BOOL TradSupport;
+    BOOL UltSupport;
+  } SupportEntry;
+
+  typedef struct {
+    SupportEntry Lpddr3;
+    SupportEntry Column10;
+    SupportEntry Column11;
+    SupportEntry Column12;
+    SupportEntry VddMin;
+    SupportEntry VddMax;
+  } SupportTable;
+
+/**
+  @brief
+    Calculate the memory clock value from the current memory frequency.
+
+    @param[in, out] MrcData     - Pointer to MrcData data structure.
+    @param[in]      Frequency   - Memory frequency to convert.
+    @param[out]     tCKminIndex - Pointer to the chosen table index.
+
+    @retval Returns the tCK value for the given frequency.
+**/
+extern
+U32
+ConvertFreq2Clock (
+  IN OUT MrcParameters *const MrcData,
+  IN     const MrcFrequency   Frequency,
+  OUT    S32           *const tCKminIndex
+);
+
+/**
+@brief
+  Calculate the CRC16 of the provided SPD data. CRC16 formula is the same
+  one that is used for calculating the CRC16 stored at SPD bytes 126-127.
+  This can be used to detect DIMM change.
+
+  @param[in]  Buffer - Pointer to the start of the data.
+  @param[in]  Size   - Amount of data in the buffer, in bytes.
+  @param[out] Crc    - Pointer to location to write the calculated CRC16 value.
+
+  @retval Returns TRUE.
+**/
+extern
+BOOL
+GetDimmCrc (
+  IN  const U8  *const Buffer,
+  IN  const U32        Size,
+  OUT U16       *const Crc
+  );
+
+/**
+  @brief
+  Determine the starting address and size of the SPD area to generate a CRC.
+
+    @param[in, out] MrcData    - The MRC "global data".
+    @param[in]      Controller - Controller index.
+    @param[in]      Channel    - Channel index.
+    @param[in]      Dimm       - Dimm index.
+    @param[out]     CrcSize    - Location to write CRC block size.
+
+    @retval The starting address of the CRC block.
+**/
+const U8 *
+MrcSpdCrcArea (
+  IN OUT MrcParameters *const MrcData,
+  IN     U8                   Controller,
+  IN     U8                   Channel,
+  IN     U8                   Dimm,
+  OUT    U32           *const CrcSize
+  );
+
+/**
+@brief
+  Process the SPD information for all DIMMs on all channels.
+
+  @param[in, out] MrcData - The MRC "global data".
+
+  @retval mrcSuccess on success, mrcDimmNotExist if no DIMMs found.
+**/
+extern
+MrcStatus
+MrcSpdProcessing (
+  IN OUT MrcParameters *const MrcData
+  );
+
+#pragma pack (pop)
+#endif // _MrcSpdProcessing_h_
diff --git a/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/WriteTraining/MrcWriteDqDqs.c b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/WriteTraining/MrcWriteDqDqs.c
new file mode 100644
index 0000000..49b35e4
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/WriteTraining/MrcWriteDqDqs.c
@@ -0,0 +1,703 @@
+/** @file
+  The third stage of the write training is determining the PI setting for
+  each byte strobe to make sure that data is sent at the optimal location.
+  In order to do that a pattern of alternating zeros and ones is written to
+  a block of the memory, and then read out.  By identifying the location
+  where it is farthest away from where errors are shown the DQS will be
+  aligned to the center of the eye.
+
+@copyright
+  Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement.
+
+**/
+
+//
+// Include files
+//
+#include "MrcWriteDqDqs.h"
+
+/**
+@brief
+  this function executes the write timing centering.
+  Center Tx DQS-DQ using moderate pattern with 1D eye.
+
+  @param[in] MrcData         - Include all MRC global data.
+
+  @retval MrcStatus      - if it succeded returns mrcSuccess
+**/
+MrcStatus
+MrcWriteTimingCentering (
+  IN     MrcParameters *const MrcData
+  )
+{
+  MrcOutput *Outputs;
+  U8        ResetPerbit;
+  U8        LoopCount;
+
+  Outputs = &MrcData->SysOut.Outputs;
+  ResetPerbit = 1;
+
+  LoopCount   = 10;
+
+  return DQTimeCentering1D (MrcData, Outputs->ValidChBitMask, WrT, ResetPerbit, LoopCount);
+}
+
+/**
+  @brief
+  this function executes the write timing centering in 2D.
+    Final write timing centering using 2D algorithm and per bit optimization.
+
+    @param[in] MrcData - Include all MRC global data.
+
+    @retval MrcStatus -  if it succeded returns mrcSuccess
+
+  **/
+MrcStatus
+MrcWriteTimingCentering2D (
+  IN     MrcParameters *const MrcData
+  )
+{
+  const MrcDebug  *Debug;
+  MrcOutput       *Outputs;
+  MrcStatus       Status;
+  U8              EnPerBit;
+  U8              EnRxDutyCycle;
+  U8              ResetPerBit;
+  U8              LoopCount;
+  U8              En2D;
+
+  Debug         = &MrcData->SysIn.Inputs.Debug;
+  Outputs       = &MrcData->SysOut.Outputs;
+  EnPerBit      = 1;
+  EnRxDutyCycle = 0;
+  ResetPerBit   = 1;
+  LoopCount     = 15;
+  En2D          = 0;
+
+  MRC_DEBUG_MSG (
+    Debug,
+    MSG_LEVEL_NOTE,
+    "\n\nCalling with EnRxDutyCycle = %d, EnPerBit = %d, ResetPerBit = %d En2D = %d\n",
+    EnRxDutyCycle,
+    EnPerBit,
+    ResetPerBit,
+    En2D
+    );
+
+  Status = DataTimeCentering2D (
+            MrcData,
+            Outputs->MarginResult,
+            Outputs->ValidChBitMask,
+            WrT,
+            EnPerBit,
+            EnRxDutyCycle,
+            ResetPerBit,
+            LoopCount,
+            En2D
+            );
+
+  if (mrcSuccess == Status) {
+    EnPerBit    = 0;
+    ResetPerBit = 0;
+    En2D        = 1;
+    MRC_DEBUG_MSG (
+      Debug,
+      MSG_LEVEL_NOTE,
+      "\n\nCalling with EnRxDutyCycle = %d, EnPerBit = %d, ResetPerBit = %d En2D = %d\n",
+      EnRxDutyCycle,
+      EnPerBit,
+      ResetPerBit,
+      En2D
+      );
+
+    Status = DataTimeCentering2D (
+              MrcData,
+              Outputs->MarginResult,
+              Outputs->ValidChBitMask,
+              WrT,
+              EnPerBit,
+              EnRxDutyCycle,
+              ResetPerBit,
+              LoopCount,
+              En2D
+              );
+  }
+
+  return Status;
+}
+
+/**
+@brief
+  Rank Margin Tool - Measure margins across various parameters
+
+  @param[in, out] MrcData - Include all MRC global data.
+
+  @retval MrcStatus -  mrcSuccess if succeded
+**/
+MrcStatus
+MrcRankMarginTool (
+  IN OUT MrcParameters *const MrcData
+  )
+{
+  const U16                           mode = 0;
+  const MrcInput                      *Inputs;
+  const MrcDebug                      *Debug;
+  MrcOutput                           *Outputs;
+  MrcControllerOut                    *ControllerOut;
+  MrcChannelOut                       *ChannelOut;
+  MrcCommandMargin                    *CommandOut;
+  MrcRecvEnMargin                     *RecvEnOut;
+  MrcWrLevelMargin                    *WrLevelOut;
+  MrcStatus                           Status;
+  U32                                 BERStats[4];
+  U32                                 Offset;
+  U8                                  Rank;
+  U8                                  Param;
+  U8                                  RankMask;
+  U8                                  Controller;
+  U8                                  Channel;
+  U8                                  byte;
+  U8                                  bit;
+  U8                                  chBitMask;
+  U8                                  MaxMargin;
+  U8                                  DqLoopCount;
+  U8                                  CmdLoopCount;
+  S8                                  VrefOffsets[2];
+  BOOL                                Lpddr;
+  BOOL                                SkipVref;
+  BOOL                                SkipPrint;
+  MrcPower                            PwrChRank[MAX_CHANNEL][MAX_RANK_IN_CHANNEL];
+  Inputs  = &MrcData->SysIn.Inputs;
+  Debug   = &Inputs->Debug;
+  Outputs = &MrcData->SysOut.Outputs;
+  Status  = mrcSuccess;
+  MrcOemMemorySet ((U8 *) BERStats, 0, sizeof (BERStats));
+  MrcOemMemorySet ((U8 *) VrefOffsets, 0, sizeof (VrefOffsets));
+  MrcOemMemorySet ((U8 *) PwrChRank, 0, sizeof (PwrChRank));
+
+  //
+  // Check if LPDDR3 memory is used
+  //
+  Lpddr = (Outputs->DdrType == MRC_DDR_TYPE_LPDDR3);
+
+
+  DqLoopCount = 17;
+  CmdLoopCount = (Lpddr) ? 10 : 17;
+
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Rank Margin Testing: DQ LC = %d, Cmd LC = %d\n\n", DqLoopCount, CmdLoopCount);
+  MRC_DEBUG_MSG (
+    Debug,
+    MSG_LEVEL_NOTE,
+    "Margin\nParams: RcvEna\tWrLevel\tRdT\tWrT\tRdV\tWrV\tCmdT\tCmdV\tDimmPwr\tCpuPwr\tTotPwr\n"
+    );
+  MRC_DEBUG_MSG (
+    Debug,
+    MSG_LEVEL_NOTE,
+    "\tLft Rgt Lft Rgt Lft Rgt Lft Rgt Low Hi  Low Hi  Lft Rgt Low Hi\t[mW]\t[mW]\t[mW]\n"
+    );
+  for (Rank = 0; Rank < MAX_RANK_IN_CHANNEL; Rank++) {
+    //
+    // Select rank for REUT test
+    //
+    RankMask  = 1 << Rank;
+    chBitMask = 0;
+    for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+      chBitMask |= SelectReutRanks (MrcData, Channel, RankMask, 0);
+      if ((MRC_BIT0 << Channel) & chBitMask) {
+        ChannelOut = &Outputs->Controller[0].Channel[Channel];
+        //
+        // Clear any old state in DataOffsetTrain
+        //
+        MrcOemMemorySetDword (&ChannelOut->DataOffsetTrain[0], 0, Outputs->SdramCount);
+      }
+    }
+    //
+    // Continue with next rank if this rank is not present on any channel
+    //
+    if (!(chBitMask)) {
+      continue;
+    }
+    //
+    // Setup Test
+    // SOE=1, EnCADB=0, EnCKE=0 SOE=1 sets bit12 of REUT_CH_ERR_CTL
+    //
+    SetupIOTestBasicVA (MrcData, chBitMask, DqLoopCount, NSOE, 0, 0, 8);
+    for (Param = RcvEna; Param <= WrLevel; Param++) {
+      if (Param == WrDqsT) {
+        continue;
+      }
+
+      //
+      // For Write/Read timing margining, we want to run traffic with Rd->Rd turnaround times of 4 and 5.
+      // This statement depends on the order of MRC_MarginTypes.  If this enum's order changes, this
+      // statement must change.
+      //
+      if (Param == RdT) {
+        Outputs->DQPat = RdRdTA;
+      } else if (Param == RdV) {
+        Outputs->DQPat = BasicVA;
+      }
+
+      MaxMargin = ((Param == RdV) || (Param == WrV)) ? MAX_POSSIBLE_VREF : MAX_POSSIBLE_TIME;
+
+      //
+      // Run test for different Params
+      //
+      Status = MrcGetBERMarginCh (
+                MrcData,
+                Outputs->MarginResult,
+                chBitMask,
+                0xFF,
+                Rank,
+                Param,
+                mode,
+                1,
+                MaxMargin,
+                0,
+                BERStats
+                );
+    }
+
+    //
+    // Use CADB test for Cmd to match Late Command Training
+    //
+    SetupIOTestCADB (MrcData, chBitMask, CmdLoopCount, NSOE, 1, 0);
+
+    //
+    // Run test for Cmd Timing
+    //
+    SkipVref  = TRUE;
+    SkipPrint = TRUE;
+
+#ifdef ULT_FLAG
+    if (Lpddr) {
+      CmdLinearFindEdgesLpddr (MrcData, MrcIterationClock, chBitMask, RankMask, !SkipPrint);
+    } else
+#endif // ULT_FLAG
+    {
+      CmdLinearFindEdges (
+        MrcData,
+        MrcIterationClock,
+        chBitMask,
+        0xFF,
+        3,
+        -64,
+        64,
+        1,
+        VrefOffsets,
+        SkipPrint,
+        SkipVref
+        );
+    }
+
+    //
+    // Restore centered value
+    //
+    for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+      ShiftPIforCmdTraining (MrcData, Channel, MrcIterationClock, 0xFF, 3, 0, 0);
+    }
+
+    Status = MrcResetSequence (MrcData);
+
+    //
+    // Run test for Cmd Voltage
+    //
+    Status = MrcGetBERMarginCh (
+              MrcData,
+              Outputs->MarginResult,
+              chBitMask,
+              0xFF,
+              Rank,
+              CmdV,
+              mode,
+              0,
+              MAX_POSSIBLE_VREF,
+              0,
+              BERStats
+              );
+    Status = MrcResetSequence (MrcData);
+
+    CalcSysPower(MrcData, PwrChRank);
+
+#ifdef MRC_DEBUG_PRINT
+    //
+    // Print test results
+    //
+    for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+      if (MrcRankInChannelExist (MrcData, Rank, Channel)) {
+        MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "C%dR%d:\t", Channel, Rank);
+        MRC_DEBUG_MSG (
+          Debug,
+          MSG_LEVEL_NOTE,
+          "%2d  %2d\t%2d  %2d\t%2d  %2d\t%2d  %2d\t%2d  %2d\t%2d  %2d\t%2d  %2d\t%2d  %2d\t%2d.%d\t%2d.%d\t%2d.%d\n",
+          Outputs->MarginResult[LastRcvEna][Rank][Channel][0][0] / 10,
+          Outputs->MarginResult[LastRcvEna][Rank][Channel][0][1] / 10,
+          Outputs->MarginResult[LastWrLevel][Rank][Channel][0][0] / 10,
+          Outputs->MarginResult[LastWrLevel][Rank][Channel][0][1] / 10,
+          Outputs->MarginResult[LastRxT][Rank][Channel][0][0] / 10,
+          Outputs->MarginResult[LastRxT][Rank][Channel][0][1] / 10,
+          Outputs->MarginResult[LastTxT][Rank][Channel][0][0] / 10,
+          Outputs->MarginResult[LastTxT][Rank][Channel][0][1] / 10,
+          Outputs->MarginResult[LastRxV][Rank][Channel][0][0] / 10,
+          Outputs->MarginResult[LastRxV][Rank][Channel][0][1] / 10,
+          Outputs->MarginResult[LastTxV][Rank][Channel][0][0] / 10,
+          Outputs->MarginResult[LastTxV][Rank][Channel][0][1] / 10,
+          Outputs->MarginResult[LastCmdT][Rank][Channel][0][0] / 10,
+          Outputs->MarginResult[LastCmdT][Rank][Channel][0][1] / 10,
+          Outputs->MarginResult[LastCmdV][Rank][Channel][0][0] / 10,
+          Outputs->MarginResult[LastCmdV][Rank][Channel][0][1] / 10,
+          PwrChRank[Channel][Rank].DimmPwr / 10,
+          PwrChRank[Channel][Rank].DimmPwr % 10,
+          PwrChRank[Channel][Rank].CpuPower / 10,
+          PwrChRank[Channel][Rank].CpuPower % 10,
+          PwrChRank[Channel][Rank].TotPwr / 10,
+          PwrChRank[Channel][Rank].TotPwr % 10
+          );
+      }
+    }
+#endif
+    for (Controller = 0; Controller < MAX_CONTROLLERS; Controller++) {
+      ControllerOut = &Outputs->Controller[Controller];
+      for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+        if (MrcRankInChannelExist (MrcData, Rank, Channel)) {
+          ChannelOut        = &ControllerOut->Channel[Channel];
+          CommandOut        = &ChannelOut->Command[Rank];
+          CommandOut->Left  = (U8) (Outputs->MarginResult[LastCmdT][Rank][Channel][0][0] / 10);
+          CommandOut->Right = (U8) (Outputs->MarginResult[LastCmdT][Rank][Channel][0][1] / 10);
+          CommandOut->Low   = (U8) (Outputs->MarginResult[LastCmdV][Rank][Channel][0][0] / 10);
+          CommandOut->High  = (U8) (Outputs->MarginResult[LastCmdV][Rank][Channel][0][1] / 10);
+          RecvEnOut         = &ChannelOut->ReceiveEnable[Rank];
+          RecvEnOut->Left   = (U8) (Outputs->MarginResult[LastRcvEna][Rank][Channel][0][0] / 10);
+          RecvEnOut->Right  = (U8) (Outputs->MarginResult[LastRcvEna][Rank][Channel][0][1] / 10);
+          WrLevelOut        = &ChannelOut->WriteLevel[Rank];
+          WrLevelOut->Left  = (U8) (Outputs->MarginResult[LastWrLevel][Rank][Channel][0][0] / 10);
+          WrLevelOut->Right = (U8) (Outputs->MarginResult[LastWrLevel][Rank][Channel][0][1] / 10);
+          for (byte = 0; byte < Outputs->SdramCount; byte++) {
+            for (bit = 0; bit < MAX_BITS; bit++) {
+              ChannelOut->RxDqPb[Rank][byte][bit].Left      = (U8) (Outputs->MarginResult[LastRxT][Rank][Channel][0][0] / 10);
+              ChannelOut->RxDqPb[Rank][byte][bit].Right     = (U8) (Outputs->MarginResult[LastRxT][Rank][Channel][0][1] / 10);
+              ChannelOut->TxDqPb[Rank][byte][bit].Left      = (U8) (Outputs->MarginResult[LastTxT][Rank][Channel][0][0] / 10);
+              ChannelOut->TxDqPb[Rank][byte][bit].Right     = (U8) (Outputs->MarginResult[LastTxT][Rank][Channel][0][1] / 10);
+              ChannelOut->RxDqVrefPb[Rank][byte][bit].Low   = (U8) (Outputs->MarginResult[LastRxV][Rank][Channel][0][0] / 10);
+              ChannelOut->RxDqVrefPb[Rank][byte][bit].High  = (U8) (Outputs->MarginResult[LastRxV][Rank][Channel][0][1] / 10);
+              ChannelOut->TxDqVrefPb[Rank][byte][bit].Low   = (U8) (Outputs->MarginResult[LastTxV][Rank][Channel][0][0] / 10);
+              ChannelOut->TxDqVrefPb[Rank][byte][bit].High  = (U8) (Outputs->MarginResult[LastTxV][Rank][Channel][0][1] / 10);
+            }
+          }
+        }
+      }
+    }
+  } // for Rank
+
+  //
+  // Disable CADB Deselects after RMT
+  //
+  for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+    if (MrcChannelExist (Outputs, Channel)) {
+      Offset = MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_REG +
+        ((MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_REG - MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_REG) * Channel);
+      MrcWriteCR8 (MrcData, Offset, 0);
+    }
+  }
+  return Status;
+}
+
+/**
+@brief
+  Peform Read Voltage Centering in 2D.
+  Note: This function currently only supports param = WrV
+
+  @param[in, out] MrcData       - Include all MRC global data.
+
+  @retval MrcStatus -    if t succeded return mrcSuccess
+  @todo - Need option for loopcount
+**/
+MrcStatus
+MrcWriteVoltageCentering2D (
+  IN OUT MrcParameters *const MrcData
+  )
+{
+  const MrcDebug  *Debug;
+  const MrcInput  *Inputs;
+  MrcOutput       *Outputs;
+  MrcChannelOut   *ChannelOut;
+  MrcStatus       Status;
+  U32 (*marginch)[MAX_RESULT_TYPE][MAX_RANK_IN_CHANNEL][MAX_CHANNEL][MAX_SDRAM_IN_DIMM][MAX_EDGES];
+
+  U8  ResultType;
+  U8  ResultTypeT;
+  U8  loopcount;
+  U8  param;
+  U8  paramT;
+  U8  Channel;
+  U8  byte;
+  U8  tim;
+  U8  chBitMask;
+  U8  MaxTscale;
+  U8  SkipWait;
+  S8  SumEH;
+  S8  SumEHSign;
+  S8  TimePoints[3];
+  U8  EHWeights[sizeof (TimePoints)];
+  U16 mode;
+  S32 center;
+  S32 height;
+  U32 value0[MAX_CHANNEL];
+  U32 BERStats[4];
+  U32 TimScale[MAX_CHANNEL];
+  S32 centersum[MAX_CHANNEL];
+
+  Inputs    = &MrcData->SysIn.Inputs;
+  Outputs   = &MrcData->SysOut.Outputs;
+  Debug     = &Inputs->Debug;
+  marginch  = &Outputs->MarginResult;
+  Status    = mrcSuccess;
+  loopcount = 17;
+  MaxTscale = 12;
+  SumEH     = 0;
+  MrcOemMemorySet ((U8 *) BERStats, 0, sizeof (BERStats));
+  MrcOemMemorySet ((U8 *) EHWeights, 1, sizeof (EHWeights));
+  TimePoints[0] = -4;
+  TimePoints[1] = 0;
+  TimePoints[2] = 4;
+
+  //
+  // No input for param so set it to RdV
+  //
+  param = WrV;
+
+  //
+  // Assume rank0 is always popuplated
+  //
+  if (param == WrV) {
+    paramT = WrT;
+  } else {
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_ERROR, "Error Handler: Unknown Margin Parameter\n");
+    Status = mrcFail;
+    return Status;
+  }
+
+  ResultType  = GetMarginResultType (param);
+  ResultTypeT = GetMarginResultType (paramT);
+
+  //
+  /// @todo: Need to check if we can enable it for A0 or not
+  // Outputs->EnDumRd = 1;
+  // SOE = 00b(No Stop on error), EnCADB=0, EnCKE=0
+  //
+  //
+  /// @todo: Will enable the DQ tests instead of basic in the future
+  //  SetupIOTestDQ (MrcData,Outputs->ValidChBitMask, loopcount, NSOE, 0, 0);
+  //
+  SetupIOTestBasicVA (MrcData, Outputs->ValidChBitMask, loopcount, NSOE, 0, 0, 8);
+
+  //
+  // Calculate SumEH for use in weighting equations
+  //
+  for (tim = 0; tim < sizeof (TimePoints); tim++) {
+    SumEH += EHWeights[tim];
+  }
+  //
+  // Select rank for REUT test
+  //
+  chBitMask = 0;
+  for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+    if (!MrcChannelExist (Outputs, Channel)) {
+      continue;
+    }
+
+    ChannelOut = &Outputs->Controller[0].Channel[Channel];
+    chBitMask |= SelectReutRanks (MrcData, Channel, ChannelOut->ValidRankBitMask, 0);
+
+    //
+    // Clear any old state in DataTrain Offset
+    //
+    MrcOemMemorySetDword (&ChannelOut->DataOffsetTrain[0], 0, Outputs->SdramCount);
+  }
+  //
+  // ####################################################
+  // #############  Initialize EW/EH variables   ########
+  // ####################################################
+  //
+  Status = GetMarginCh (MrcData, Outputs->MarginResult, paramT, 0xF);
+
+  //
+  // Update TimScale with results
+  //
+  for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+    TimScale[Channel] = 0;
+    if (!(chBitMask & (1 << Channel))) {
+      continue;
+    }
+
+    TimScale[Channel] = ((*marginch)[ResultTypeT][0][Channel][0][0] + (*marginch)[ResultTypeT][0][Channel][0][1]) / 20;
+    //
+    // It is possible TimScale[Channel] is 0.
+    //
+    if (!TimScale[Channel] || (TimScale[Channel] > MaxTscale)) {
+      TimScale[Channel] = MaxTscale;
+    }
+  }
+
+  Status = GetMarginCh (MrcData, Outputs->MarginResult, param, 0xF);
+
+  //
+  // ####################################################
+  // ######   Measure Eye Height at all Timing Points  #####
+  // ####################################################
+  //
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "TimScale{0] is %d, TimScale{1] is %d\n", TimScale[0], TimScale[1]);
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Channel\t0\t\t\t\t1\n");
+
+  for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "WrTime\tLow\tHigh\tHeight\tCenter\t");
+  }
+  //
+  // Initialize parameters to 0
+  //
+  for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+    centersum[Channel] = 0;
+    value0[Channel]    = 0;
+  }
+  //
+  // Loop through all the Time Points to Test
+  //
+  for (tim = 0; tim < sizeof (TimePoints); tim++) {
+    //
+    // Setup Timing Offset for this point
+    //
+    for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+      if (!(chBitMask & (1 << Channel))) {
+        continue;
+      }
+
+      value0[Channel] = (S32) (TimePoints[tim] * TimScale[Channel]) / MaxTscale;
+
+      //
+      // There is no multicast per channel...
+      //
+      for (byte = 0; byte < Outputs->SdramCount; byte++) {
+        Status = ChangeMargin (MrcData, paramT, value0[Channel], 0, 0, Channel, 0, byte, 0, 1, 0, MrcRegFileStart);
+      }
+    }
+    //
+    // Run Margin Test
+    //
+    mode = 0;
+    Status = MrcGetBERMarginCh (
+              MrcData,
+              Outputs->MarginResult,
+              chBitMask,
+              0xFF,
+              0,
+              param,
+              mode,
+              1,
+              MAX_POSSIBLE_VREF,
+              0,
+              BERStats
+              );
+
+    //
+    // Store Results
+    //
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\n");
+    for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+      if (!(chBitMask & (1 << Channel))) {
+        MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\t\t\t\t\t");
+        continue;
+      }
+
+      MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%d\t", value0[Channel]);
+
+      height  = ((*marginch)[ResultType][0][Channel][0][1] + (*marginch)[ResultType][0][Channel][0][0]) / 10;
+      center  = (S32) ((*marginch)[ResultType][0][Channel][0][1] - (*marginch)[ResultType][0][Channel][0][0]);
+      MRC_DEBUG_MSG (
+        Debug,
+        MSG_LEVEL_NOTE,
+        "%d\t%d\t%d\t%d\t",
+        (*marginch)[ResultType][0][Channel][0][0] / 10,
+        (*marginch)[ResultType][0][Channel][0][1] / 10,
+        height,
+        center / 20
+        );
+      if (tim == 0) {
+        centersum[Channel] = 0;
+      }
+      //
+      // Calculate weight for this point
+      //
+      centersum[Channel] += EHWeights[tim] * center;
+      //
+      // MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "+----->centersum[%d] = %d, \n", Channel, centersum[Channel]);
+      //
+    }
+  }
+
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\nWtdCntr\t");
+  //
+  // ####################################################
+  // ###########   Center Results per Ch    #############
+  // ####################################################
+  //
+  for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+    if (!(chBitMask & (1 << Channel))) {
+      MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\t\t\t\t\t");
+      continue;
+    }
+
+    ChannelOut = &Outputs->Controller[0].Channel[Channel];
+
+    //
+    // Calculate CenterPoint.  Round to Nearest Int
+    //
+    SumEHSign           = (centersum[Channel] < 0) ? (-1) : 1;
+
+    centersum[Channel]  = (centersum[Channel] + 10 * SumEH * SumEHSign) / (20 * SumEH);
+
+    //
+    // Apply new centerpoint
+    // Only Byte 7 on Channel 1 is needed to update DIMM Vref
+    // Skip if there are more channels
+    //
+    SkipWait = (chBitMask >> (Channel + 1));
+    Status = ChangeMargin (MrcData, param, centersum[Channel], 0, 0, Channel, 0, 7, 0, 1, SkipWait, MrcRegFileCurrent);
+
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "%d\t\t\t\t", centersum[Channel]);
+
+    //
+    // Update MrcData for future tests
+    //
+    (*marginch)[ResultType][0][Channel][0][0] = (S32) ((*marginch)[ResultType][0][Channel][0][0]) + (10 * (centersum[Channel]));
+    (*marginch)[ResultType][0][Channel][0][1] = (S32) ((*marginch)[ResultType][0][Channel][0][1]) - (10 * (centersum[Channel]));
+
+    //
+    // Clean up after test
+    //
+    MrcOemMemorySetDword (&ChannelOut->DataOffsetTrain[0], 0, Outputs->SdramCount);
+  }
+
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\n");
+
+  //
+  // Clean up
+  //
+  Status            = ChangeMargin (MrcData, paramT, 0, 0, 1, 0, 0, 0, 0, 1, 0, MrcRegFileCurrent);
+
+  Outputs->EnDumRd  = 0;
+  return Status;
+}
diff --git a/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/WriteTraining/MrcWriteDqDqs.h b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/WriteTraining/MrcWriteDqDqs.h
new file mode 100644
index 0000000..d021aed
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/WriteTraining/MrcWriteDqDqs.h
@@ -0,0 +1,108 @@
+/** @file
+  The third stage of the write training is determining the PI setting for each
+  byte strobe to make sure that data is sent at the optimal location.
+  In order to do that a pattern of alternating zeros and ones is written to a block of the memory, and then read out.
+  By identifying the location where it is farthest away from where errors are shown the DQS will be aligned to the
+  center of the eye.
+
+@copyright
+  Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement.
+**/
+
+#ifndef _MrcWriteDqDqs_h_
+#define _MrcWriteDqDqs_h_
+
+#include "MrcTypes.h"
+#include "McAddress.h"
+#include "MrcApi.h"
+#include "MrcCommandTraining.h"
+#include "MrcCommon.h"
+#include "MrcGlobal.h"
+#include "MrcReset.h"
+
+/**
+  @brief
+  this function executes the write timing centering in 2D.
+    Final write timing centering using 2D algorithm and per bit optimization.
+
+    @param[in] MrcData - Include all MRC global data.
+
+    @retval MrcStatus -  if it succeded returns mrcSuccess
+
+  **/
+extern
+MrcStatus
+MrcWriteTimingCentering (
+  IN     MrcParameters *const MrcData
+  );
+
+/**
+  @brief
+  this function executes the write timing centering in 2D.
+    Final write timing centering using 2D algorithm and per bit optimization.
+
+    @param[in] MrcData - Include all MRC global data.
+
+    @retval MrcStatus -  if it succeded returns mrcSuccess
+
+  **/
+extern
+MrcStatus
+MrcWriteTimingCentering2D (
+  IN     MrcParameters *const MrcData
+  );
+
+/**
+@brief
+  Rank Margin Tool - Measure margins across various parameters
+
+  @param[in, out] MrcData - Include all MRC global data.
+
+  @retval MrcStatus -  mrcSuccess if succeded
+**/
+extern
+MrcStatus
+MrcRankMarginTool (
+  IN OUT MrcParameters *const MrcData
+  );
+
+/**
+@brief
+  this function execute the write timing centering in 2D.
+  Final write timing centering using 2D algorithm and per bit optimization
+
+  @param[in, out] MrcData - Include all MRC global data.
+
+  @retval MrcStatus -  if it succeded returns mrcSuccess
+**/
+/**
+@brief
+  Peform Read Voltage Centering in 2D.
+  Note: This function currently only supports param = WrV
+
+  @param[in, out] MrcData       - Include all MRC global data.
+
+  @retval MrcStatus -    if it succeded return mrcSuccess
+  @todo - Need option for loopcount
+**/
+extern
+MrcStatus
+MrcWriteVoltageCentering2D (
+  IN OUT MrcParameters *const MrcData
+  );
+
+#endif // _MrcWriteDqDqs_h_
diff --git a/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/WriteTraining/MrcWriteLeveling.c b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/WriteTraining/MrcWriteLeveling.c
new file mode 100644
index 0000000..8b71620
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/WriteTraining/MrcWriteLeveling.c
@@ -0,0 +1,1079 @@
+/** @file
+  The write leveling flow is the first part of the write training.
+  In this stage the memory controller needs to synchronize its DQS sending
+  with the clock for each DRAM.  The DRAM can be put in a mode where for a
+  write command it responds by sampling the clock using DQS and sending it
+  back as the data.  The IO can receive this and tune the DQS alignment so
+  it will appear in sync with the clock at the DRAM side.
+  The following algorithm is used for the write leveling flow:
+
+@copyright
+  Copyright (c) 1999 - 2013 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement.
+
+**/
+#include "MrcWriteLeveling.h"
+
+/**
+@brief
+  this function execute the Jedec write leveling Cleanup.
+  Center TxDQS-CLK timing
+
+  @param[in, out] MrcData - Include all MRC global data.
+
+  @retval MrcStatus -  if it succeded return mrcSuccess
+**/
+MrcStatus
+MrcJedecWriteLevelingCleanUp (
+  IN OUT MrcParameters *const MrcData
+  )
+{
+  const MRC_REUTAddress REUTAddress = {{0, 0, 0, 0},    // Start
+                                       {0, 0, 0, 1023}, // Stop
+                                       {0, 0, 0, 0},    // Order
+                                       {0, 0, 0, 0},    // IncRate
+                                       {0, 0, 0, 1}};   // IncValue
+  const U8          DumArr[7] = {1, 1, 1, 1, 1, 1, 1};
+  const U8          DqOffsetMax = 7;
+  const S8          DqOffsets[7] = {0, -10, 10, -5, 5, -15, 15};
+  const S8          Offsets[5] = {0, 1, -1, 2, 3};
+  const U8          PMaskConst[8] = {0, 0, 1, 1, 1, 1, 0, 0};
+  const U32         CleanUpSeeds[MRC_WDB_NUM_MUX_SEEDS] = {0xAAAAAA, 0xCCCCCC, 0xF0F0F0};
+  const U32         NormalSeeds[MRC_WDB_NUM_MUX_SEEDS] = {0xA10CA1, 0xEF0D08, 0xAD0A1E};
+  const MrcInput    *Inputs;
+  const MrcDebug    *Debug;
+  MrcOutput         *Outputs;
+  MrcControllerOut  *ControllerOut;
+  MrcChannelOut     *ChannelOut;
+  MrcStatus         Status;
+  U8                Channel;
+  U8                Rank;
+  U8                Byte;
+  U8                offset;
+  U8                ChBitMask;
+  U8                RankMask;  // RankBitMask for both channels
+  U8                ValidRankMask;
+  U8                Pattern[4][2];
+  U8                PMask[sizeof (PMaskConst)];
+  U8                AllGood;
+  U8                AllGoodLoops;
+  U8                DqOffset;
+  U8                RankDouble;
+  U8                RankHalf;
+  U8                RankMod2;
+  U8                Start;
+  S8                ByteOff[MAX_CHANNEL][MAX_SDRAM_IN_DIMM]; // Passing offset for each ch/byte.
+  S8                ByteSum[MAX_CHANNEL]; // Sum of passing offsets for a ch
+  S8                TargetOffset;
+  U16               ByteMask;
+  U16               ValidByteMask;
+  U16               Result;
+  U16               SkipMe;
+  U16               BytePass[MAX_CHANNEL]; // Bit mask indicating which ch/byte has passed
+  S16               GlobalByteOff;
+  U32               CRValue;
+  U32               Offset;
+  U32               CRAddDelay[MAX_CHANNEL];
+  S32               LocalOffset;
+  BOOL              Done;
+#ifdef ULT_FLAG
+  BOOL              Lpddr;
+#endif //ULT_FLAG
+  MRC_WDBPattern    WDBPattern;
+
+  MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_STRUCT                 ReutChPatWdbClMuxCfg;
+  DDRDATA0CH0_CR_TXTRAINRANK0_STRUCT                              CrTxTrainRank;
+#ifdef MRC_DEBUG_PRINT
+  U32               ErrLower[MAX_CHANNEL];
+  U32               ErrUpper[MAX_CHANNEL];
+#endif // MRC_DEBUG_PRINT
+
+  //
+  // Setup REUT Pattern
+  // Use 0x00FFC33C pattern to keep DQ-DQS simple but detect any failures
+  // Same Pattern as NHM/WSM
+  //
+  Inputs              = &MrcData->SysIn.Inputs;
+  Outputs             = &MrcData->SysOut.Outputs;
+  ControllerOut       = &Outputs->Controller[0];
+  Debug               = &Inputs->Debug;
+  Status              = mrcSuccess;
+  LocalOffset         = 0;
+  Done                = TRUE;
+  Pattern[0][0]       = 0x00;
+  Pattern[0][1]       = 0xFF;
+  Pattern[1][0]       = 0xFF;
+  Pattern[1][1]       = 0x00;
+  Pattern[2][0]       = 0xC3;
+  Pattern[2][1]       = 0x3C;
+  Pattern[3][0]       = 0x3C;
+  Pattern[3][1]       = 0xC3;
+  WDBPattern.IncRate  = 1;
+  WDBPattern.Start    = 0;
+  WDBPattern.Stop     = 3;
+  WDBPattern.DQPat    = BasicVA;
+  MrcOemMemoryCpy (PMask, (U8 *) PMaskConst, sizeof (PMask));
+  MrcOemMemorySet ((U8 *) CRAddDelay, 0, sizeof (CRAddDelay));
+#ifdef MRC_DEBUG_PRINT
+  MrcOemMemorySet ((U8 *) ErrLower, 0, sizeof (ErrLower));
+  MrcOemMemorySet ((U8 *) ErrUpper, 0, sizeof (ErrUpper));
+#endif // MRC_DEBUG_PRINT
+
+#ifdef ULT_FLAG
+  //
+  // Check if LPDDR3 memory is used
+  //
+  Lpddr = (Outputs->DdrType == MRC_DDR_TYPE_LPDDR3);
+#endif // ULT_FLAG
+  //
+  // Spread = 8, Start = 0, 1, 2 and 3
+  //
+  for (Start = 0; Start < (sizeof (Pattern) / sizeof (Pattern[0])); Start++) {
+    WriteWDBFixedPattern (MrcData, Pattern[Start], PMask, 8, Start);
+  }
+
+  //
+  // Set LSFR Seed to be sequential
+  //
+  MrcProgramLFSR (MrcData, CleanUpSeeds);
+
+  //
+  // Set Channel and Rank bit masks
+  //
+  ChBitMask     = Outputs->ValidChBitMask;
+  ValidRankMask = Outputs->ValidRankMask;
+  ValidByteMask = (MRC_BIT0 << Outputs->SdramCount) - 1; // 0x1FF or 0xFF
+  //
+  // Setip IO test CmdPat=PatWrRd, NumCL=4, LC=4, REUTAddress, SOE=3,
+  // WDBPattern, EnCADB=0, EnCKE=0, SubSeqWait=0 )
+  //
+  SetupIOTest (MrcData, ChBitMask, PatWrRd, 2, 4, &REUTAddress, NSOE, &WDBPattern, 0, 0, 0);
+
+  //
+  // Progam BITBUFFER for JWLT
+  //
+  ReutChPatWdbClMuxCfg.Data                     = 0;
+  ReutChPatWdbClMuxCfg.Bits.Mux0_Control        = BTBUFFER;
+  ReutChPatWdbClMuxCfg.Bits.Mux1_Control        = BTBUFFER;
+  ReutChPatWdbClMuxCfg.Bits.Mux2_Control        = BTBUFFER;
+  ReutChPatWdbClMuxCfg.Bits.ECC_Data_Source_Sel = 1;
+  for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+    if (MrcChannelExist (Outputs, Channel)) {
+      Offset = MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_REG +
+        ((MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_REG - MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_REG) * Channel);
+      MrcWriteCR (MrcData, Offset, ReutChPatWdbClMuxCfg.Data);
+    }
+  }
+
+  for (Rank = 0; Rank < MAX_RANK_IN_CHANNEL; Rank++) {
+    //
+    // Select Rank for REUT test
+    //
+    ChBitMask   = 0;
+    RankMask    = MRC_BIT0 << Rank;
+    RankDouble  = Rank * 2;
+    RankHalf    = Rank / 2;
+    RankMod2    = Rank % 2;
+    for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+      ChBitMask |= SelectReutRanks (MrcData, Channel, (RankMask), 0);
+      BytePass[Channel] = ByteSum[Channel] = 0;
+    }
+    //
+    // Skip if both channels empty
+    //
+    if (!(RankMask & ValidRankMask)) {
+      continue;
+    }
+
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\nRank %d\n", Rank);
+
+    //
+    // *************************************************
+    // Sweep through the cycle offsets until we find a value that passes
+    // *************************************************
+    //
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Sweep through the cycle offsets until we find a value that passes\n");
+
+    if (RankMask & ValidRankMask) {
+      MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Channel                 0                1\nDelay  DqOffset   Byte \t");
+      MRC_DEBUG_MSG (
+        Debug,
+        MSG_LEVEL_NOTE, (
+        Outputs->SdramCount == MAX_SDRAM_IN_DIMM
+        ) ? "0 1 2 3 4 5 6 7 8 0 1 2 3 4 5 6 7 8" : "0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7"
+        );
+    }
+
+    for (offset = 0; offset < sizeof (Offsets); offset++) {
+      //
+      // Program new delay offsets to DQ/DQS timing:
+      //
+      /// @todo - Address debuging switches or remove.
+      // MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Program new delay offsets to DQ/DQS timing %d\n", Offsets[offset]);
+      //
+      for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+        if (!(MrcRankInChannelExist (MrcData, Rank, Channel))) {
+          continue;
+        }
+
+        ChannelOut = &ControllerOut->Channel[Channel];
+
+        //
+        // Calculate offsets
+        //
+        GlobalByteOff = 0;
+        if (Offsets[offset] > MAX_ADD_DELAY) {
+          CRAddDelay[Channel] = MrcBitSwap (CRAddDelay[Channel], MAX_ADD_DELAY, RankDouble, 2);
+          GlobalByteOff       = 128 * (Offsets[offset] - MAX_ADD_DELAY);
+        } else if (Offsets[offset] < 0) {
+          CRAddDelay[Channel] = MrcBitSwap (CRAddDelay[Channel], 0, RankDouble, 2);
+          GlobalByteOff       = 128 * Offsets[offset];
+        } else {
+          CRAddDelay[Channel] = MrcBitSwap (CRAddDelay[Channel], Offsets[offset], RankDouble, 2);
+        }
+        //
+        // Write Tx DQ/DQS Flyby delays
+        // MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Add GlobalByteOff = %d to TxDQS Flyby delay: Ch %d \n", GlobalByteOff, Channel);
+        //
+        for (Byte = 0; Byte < Outputs->SdramCount; Byte++) {
+          CRValue                       = ChannelOut->TxDqs[Rank][Byte] + GlobalByteOff;
+          CrTxTrainRank.Data            = 0;
+          CrTxTrainRank.Bits.TxDqDelay  = CRValue + 32;
+          CrTxTrainRank.Bits.TxDqsDelay = CRValue;
+          CrTxTrainRank.Bits.TxEqualization = ChannelOut->TxEq[Rank][Byte];
+          UpdateTxT (MrcData, Channel, Rank, Byte, 0x3, CrTxTrainRank.Data);
+          //
+          /// @todo - Address debuging switches or remove.
+          // MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "CRValue = 0x%x \n", CrTxTrainRank.Data);
+          //
+        }
+        //
+        // Write Wr ADD Delays
+        //
+        Offset = MCHBAR_CH0_CR_SC_WR_ADD_DELAY_REG + ((MCHBAR_CH1_CR_SC_WR_ADD_DELAY_REG - MCHBAR_CH0_CR_SC_WR_ADD_DELAY_REG) * Channel);
+        MrcWriteCR (MrcData, Offset, CRAddDelay[Channel]);
+        //
+        /// @todo - Address debuging switches or remove.
+        // MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "CRAddDelay[%d] = 0x%x \n", Channel, CRAddDelay[Channel]);
+        //
+      }
+
+#ifdef ULT_FLAG
+      if (!Lpddr) {
+#endif // ULT_FLAG
+        //
+        // Reset FIFOs & Reset DRAM DLL (Micron WorkAround). Wait 1uS for test to complete
+        //
+        Status = IoReset (MrcData);
+
+        for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+          if (MrcRankInChannelExist (MrcData, Rank, Channel)) {
+            ChannelOut = &ControllerOut->Channel[Channel];
+            Status = MrcWriteMRS (
+                      MrcData,
+                      Channel,
+                      RankMask,
+                      mrMR0,
+                      ChannelOut->Dimm[RankHalf].Rank[RankMod2].MR[mrMR0] | (MRC_BIT0 << 8)
+                      );
+          }
+        }
+
+        MrcWait (MrcData, (1 * HPET_1US));
+#ifdef ULT_FLAG
+      }
+#endif // ULT_FLAG
+
+      //
+      // Run Test across all DqOffsets points
+      //
+      for (DqOffset = 0; DqOffset < DqOffsetMax; DqOffset++) {
+        //
+        // Update Offset
+        //
+        ChangeMargin (MrcData, WrT, DqOffsets[DqOffset], 0, 1, 0, Rank, 0, 0, 0, 0, MrcRegFileRank);
+
+        //
+        // Run Test
+        // DQPat = BasicVA, DumArr, ClearErrors = 1, mode = 0
+        //
+        RunIOTest (MrcData, ChBitMask, BasicVA, DumArr, 1, 0);
+
+        //
+        // Update results for all ch/bytes
+        //
+        Done = TRUE;
+
+        MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\n% 3d\t% 3d\t       \t", Offsets[offset], DqOffsets[DqOffset]);
+
+        //
+        // Update results for all ch/bytes
+        //
+        for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+          if (!(MrcRankInChannelExist (MrcData, Rank, Channel))) {
+            if (Channel == 0) {
+              MRC_DEBUG_MSG (
+                Debug,
+                MSG_LEVEL_NOTE,
+                (Outputs->SdramCount == MAX_SDRAM_IN_DIMM) ? "                 " : "                "
+                );
+            }
+
+            continue;
+          }
+          //
+          // Read out per byte error results and check for any byte error
+          //
+          Offset = 4 + MCHBAR_CH0_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_REG +
+            (
+              (
+                MCHBAR_CH1_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_REG -
+                MCHBAR_CH0_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_REG
+              ) * Channel
+            );
+          Result = (U16) MrcReadCR (MrcData, Offset);
+          SkipMe = (Result & ValidByteMask) | BytePass[Channel];
+
+#ifdef MRC_DEBUG_PRINT
+          Offset = MCHBAR_CH0_CR_REUT_CH_ERR_DATA_STATUS_REG + ((MCHBAR_CH1_CR_REUT_CH_ERR_DATA_STATUS_REG - MCHBAR_CH0_CR_REUT_CH_ERR_DATA_STATUS_REG) * Channel);
+          ErrLower[Channel] = MrcReadCR (MrcData, Offset);
+          //
+          // Lower 32 bits
+          //
+          ErrUpper[Channel] = MrcReadCR (MrcData, Offset + 4);
+          //
+          // Upper 32 bits
+          //
+#endif // MRC_DEBUG_PRINT
+          for (Byte = 0; Byte < Outputs->SdramCount; Byte++) {
+            ByteMask = MRC_BIT0 << Byte;
+            MRC_DEBUG_MSG (
+              Debug,
+              MSG_LEVEL_NOTE,
+              ((Result & ValidByteMask) & ByteMask) ?
+                "# " : //Fail
+                ". " // Pass
+              );
+            //
+            // If this byte has failed or previously passed, nothing to do
+            //
+            if (SkipMe & ByteMask) {
+              continue;
+            }
+
+            BytePass[Channel] |= ByteMask;
+            ByteOff[Channel][Byte] = Offsets[offset];
+            ByteSum[Channel] += Offsets[offset];
+          }
+          //
+          /// @todo - Address debuging switches or remove.
+          // MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "For DqOffsets %d: BytePass[%d] = 0x%X, Result = 0x%x, SkipMe = 0x%x\n", DqOffsets[DqOffset], Channel, BytePass[Channel], Result, SkipMe);
+          //
+          if (BytePass[Channel] != ValidByteMask) {
+            Done = FALSE;
+          }
+        }
+
+#ifdef MRC_DEBUG_PRINT
+        for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+          if (MrcRankInChannelExist (MrcData, Rank, Channel)) {
+            MRC_DEBUG_MSG (
+              Debug,
+              MSG_LEVEL_NOTE,
+              "0x%08x%08x ",
+              ErrUpper[Channel],
+              ErrLower[Channel]
+              );
+          }
+        }
+#endif // MRC_DEBUG_PRINT
+        //
+        // Jump out of the for DqOffset loop if everybody is passing
+        //
+        if (Done == TRUE) {
+          break;
+        }
+      }
+      //
+      // Jump out of the for offset loop if everybody is passing
+      //
+      if (Done == TRUE) {
+        break;
+      }
+    }
+
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_ERROR, "\n");
+
+    //
+    // Walk through and find the correct value for each ch/byte
+    //
+    for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+      if (!(MrcRankInChannelExist (MrcData, Rank, Channel))) {
+        continue;
+      }
+
+      ChannelOut = &ControllerOut->Channel[Channel];
+
+      if (Done == FALSE) {
+        MRC_DEBUG_MSG (
+          Debug,
+          MSG_LEVEL_ERROR,
+          "Error! Write Leveling CleanUp - Couldn't find a passing value for all bytes on Channel %u Rank %u:\nBytes - ",
+          Channel,
+          Rank
+          );
+#ifdef MRC_DEBUG_PRINT
+        for (Byte = 0; Byte < Outputs->SdramCount; Byte++) {
+          MRC_DEBUG_MSG (Debug, MSG_LEVEL_ERROR, ((BytePass[Channel] ^ ValidByteMask) & (1 << Byte)) ? "%d " : "", Byte);
+        }
+        MRC_DEBUG_MSG (Debug, MSG_LEVEL_ERROR, "\n");
+#endif
+        return mrcWriteLevelingError;
+      }
+      //
+      // Calculate the average offset, rounding up
+      // Apply that offset to the global MC CRAddDelay register
+      //
+      TargetOffset = (ByteSum[Channel] + (S8) (Outputs->SdramCount / 2)) / (S8) Outputs->SdramCount;
+      //
+      /// @todo - Address debuging switches or remove.
+      // MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "TargetOffset = 0x%x, ByteSum[%d] = 0x%x \n", TargetOffset, Channel, ByteSum[Channel]);
+      //
+      AllGood       = 0;
+      AllGoodLoops  = 0;
+      GlobalByteOff = 0;
+      while (AllGood == 0) {
+        //
+        // Update CRAddDelay and GlobalByteOff
+        //
+        GlobalByteOff = 0;
+        if (TargetOffset > MAX_ADD_DELAY) {
+          CRAddDelay[Channel] = MrcBitSwap (CRAddDelay[Channel], MAX_ADD_DELAY, RankDouble, 2);
+          GlobalByteOff       = 128 * (TargetOffset - MAX_ADD_DELAY);
+        } else if (TargetOffset < 0) {
+          CRAddDelay[Channel] = MrcBitSwap (CRAddDelay[Channel], 0, RankDouble, 2);
+          GlobalByteOff       = 128 * TargetOffset;
+        } else {
+          CRAddDelay[Channel] = MrcBitSwap (CRAddDelay[Channel], TargetOffset, RankDouble, 2);
+        }
+        //
+        /// @todo - Address debuging switches or remove.
+        // MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "GlobalByteOff = 0x%x, CRAddDelay[%d] = 0x%x \n", GlobalByteOff, Channel, CRAddDelay[Channel]);
+        // Refine TargetOffset to make sure it works for all byte lanes
+        //
+        AllGood = 1;
+        for (Byte = 0; Byte < Outputs->SdramCount; Byte++) {
+          LocalOffset = GlobalByteOff + 128 * (ByteOff[Channel][Byte] - TargetOffset);
+          if ((ChannelOut->TxDq[Rank][Byte] + LocalOffset) > (511 - 64)) {
+            AllGood = 0;
+            AllGoodLoops += 1;
+            TargetOffset += 1;
+            break;
+          }
+
+          if ((ChannelOut->TxDqs[Rank][Byte] + LocalOffset) < 96) {
+            AllGood = 0;
+            AllGoodLoops += 1;
+            TargetOffset -= 1;
+            break;
+          }
+          //
+          /// @todo - Address debuging switches or remove.
+          // MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "TargetOffset = 0x%x, ByteOff[%d][%d] = 0x%x \n", TargetOffset, Channel, Byte, ByteOff[Channel][Byte]);
+          //
+        }
+        //
+        // Avoid an infinite loop
+        //
+        if (AllGoodLoops > 3) {
+          MRC_DEBUG_MSG (Debug, MSG_LEVEL_ERROR, "Error Handler1: JWL CleanUp - TargetOffset refining failed \n");
+          return mrcFail;
+        }
+      }
+
+      MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "C%d.R%d:  Offset\tFinalEdge\n", Channel, Rank);
+      //
+      // Program the final settings to the DQ bytes and update MrcData
+      //
+      for (Byte = 0; Byte < Outputs->SdramCount; Byte++) {
+        LocalOffset = GlobalByteOff + 128 * (ByteOff[Channel][Byte] - TargetOffset);
+        ChannelOut->TxDq[Rank][Byte]  += (S16) LocalOffset;
+        ChannelOut->TxDqs[Rank][Byte] += (S16) LocalOffset;
+        UpdateTxT (MrcData, Channel, Rank, Byte, 0xFF, 0);
+        MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "  B%d:   %d\t%d\n", Byte, LocalOffset, ChannelOut->TxDqs[Rank][Byte]);
+      }
+      //
+      /// @todo - Address debuging switches or remove.
+      // MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "LocalOffset = 0x%x \n", LocalOffset);
+      // Update MC Delay
+      //
+      Offset = MCHBAR_CH0_CR_SC_WR_ADD_DELAY_REG + ((MCHBAR_CH1_CR_SC_WR_ADD_DELAY_REG - MCHBAR_CH0_CR_SC_WR_ADD_DELAY_REG) * Channel);
+      MrcWriteCR (MrcData, Offset, CRAddDelay[Channel]);
+      MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "CRAddDelay[%d] = 0x%x \n", Channel, CRAddDelay[Channel]);
+
+#ifdef ULT_FLAG
+      if (!Lpddr) {
+#endif // ULT_FLAG
+        //
+        // Clean up after Test
+        //
+        Status = MrcWriteMRS (
+                  MrcData,
+                  Channel,
+                  RankMask,
+                  mrMR0,
+                  ChannelOut->Dimm[RankHalf].Rank[RankMod2].MR[mrMR0] | (MRC_BIT0 << 8)
+                  );
+        MrcWait (MrcData, (1 * HPET_1US));
+#ifdef ULT_FLAG
+      }
+#endif // ULT_FLAG
+    }
+  }
+  //
+  // Clean up after Test
+  // Restore WDB - VicRot=8, Start=0 and restore default seed
+  //
+  WriteWDBVAPattern (MrcData, 0, BASIC_VA_PATTERN_SPRED_8, 8, 0);
+  MrcProgramLFSR (MrcData, NormalSeeds);
+
+  MrcWriteCrMulticast (MrcData, DDRDATA_CR_DDRCRDATAOFFSETTRAIN_REG, 0);
+  Status = IoReset (MrcData);
+
+  return Status;
+}
+
+/**
+@brief
+  this function execute the Jedec write leveling training.
+  Center TxDQS-CLK timing
+
+  @param[in, out] MrcData - Include all MRC global data.
+
+  @retval MrcStatus -  if it succedes return mrcSuccess
+**/
+MrcStatus
+MrcJedecWriteLevelingTraining (
+  IN OUT MrcParameters *const MrcData
+  )
+{
+  const MrcInput    *Inputs;
+  const MrcDebug    *Debug;
+  MrcOutput         *Outputs;
+  MrcControllerOut  *ControllerOut;
+  MrcChannelOut     *ChannelOut;
+  TOdtValue         *OdtTableIndex;
+  MrcStatus         Status;
+  U8                Channel;
+  U8                Rank;
+  U8                RankDouble;
+  U8                RankHalf;
+  U8                RankMod2;
+  U8                Byte;
+  U8                refbyte;
+  U8                ChBitMask;
+  U8                RankMask;  // RankBitMask for both channels
+  U8                ValidRankMask;
+  U8                OtherDimm;
+  U8                OdtMatrix;
+  U16               WLStart;
+  U16               WLStop;
+  U16               WLDelay;
+  U8                WLStep;
+  U32               WaitTime;
+  U32               CRValue;
+  U32               Offset;
+  U32               DqsToggleTime;
+  S32               InitialPassingStart[MAX_CHANNEL][MAX_SDRAM_IN_DIMM];
+  S32               InitialPassingEnd[MAX_CHANNEL][MAX_SDRAM_IN_DIMM];
+  S32               CurrentPassingStart[MAX_CHANNEL][MAX_SDRAM_IN_DIMM];
+  S32               CurrentPassingEnd[MAX_CHANNEL][MAX_SDRAM_IN_DIMM];
+  S32               LargestPassingStart[MAX_CHANNEL][MAX_SDRAM_IN_DIMM];
+  S32               LargestPassingEnd[MAX_CHANNEL][MAX_SDRAM_IN_DIMM];
+  S32               iWidth;
+  S32               cWidth;
+  S32               lWidth;
+  S32               ByteWidth;
+  BOOL              Pass;
+  BOOL              RankIsx16;
+  BOOL              SavedRestoreMRS;
+#ifdef ULT_FLAG
+  BOOL              Lpddr;
+#endif //ULT_FLAG
+
+  DDR3_MODE_REGISTER_1_STRUCT                 Ddr3ModeRegister1;
+  DDRDATACH0_CR_DDRCRDATACONTROL0_STRUCT      DdrCrDataControl0;
+  DDRDATA0CH0_CR_DDRCRDATACONTROL2_STRUCT     DdrCrDataControl2;
+  MCHBAR_CH0_CR_REUT_CH_MISC_ODT_CTRL_STRUCT  ReutChMiscOdtCtrl;
+  DDRDATA0CH0_CR_DDRCRDATACONTROL0_STRUCT     DdrCrData0Control0;
+  DDRDATA0CH0_CR_DATATRAINFEEDBACK_STRUCT     DataTrainFeedback;
+
+  Inputs        = &MrcData->SysIn.Inputs;
+  Outputs       = &MrcData->SysOut.Outputs;
+  ControllerOut = &Outputs->Controller[0];
+  Debug         = &Inputs->Debug;
+  Status        = mrcSuccess;
+  OdtTableIndex = NULL;
+  CRValue       = 0;
+  ChBitMask     = Outputs->ValidChBitMask;
+  ValidRankMask = Outputs->ValidRankMask;
+
+  // Save the flag and force MRS recalculation
+  SavedRestoreMRS = Outputs->RestoreMRs;
+  Outputs->RestoreMRs = FALSE;
+
+  DqsToggleTime = 1024;
+#ifdef ULT_FLAG
+  //
+  // Check if LPDDR3 memory is used
+  //
+  Lpddr = (Outputs->DdrType == MRC_DDR_TYPE_LPDDR3);
+
+  if (Lpddr) {
+    DqsToggleTime = 2048;
+  }
+#endif // ULT_FLAG
+
+  //
+  // Enabling WLmode causes DQS to toggle for 1024 qclk.  Wait for this to stop
+  // Round up to nearest uS
+  //
+
+  WaitTime = (Outputs->Qclkps * DqsToggleTime + 500000) / 1000000;
+  //
+  // Propagate delay values (without a write command) and Set Qoff on all ranks.
+  //
+  for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+    if (MrcChannelExist (Outputs, Channel)) {
+      ChannelOut = &ControllerOut->Channel[Channel];
+
+      //
+      // Propagate delay values from rank 0 to prevent assertion failures in RTL
+      //
+      DdrCrDataControl0.Data            = ChannelOut->DqControl0.Data;
+      DdrCrDataControl0.Bits.ReadRFRd   = 0;
+      DdrCrDataControl0.Bits.ReadRFWr   = 1;
+      DdrCrDataControl0.Bits.ReadRFRank = 0;
+      Offset = DDRDATACH0_CR_DDRCRDATACONTROL0_REG + ((DDRDATACH1_CR_DDRCRDATACONTROL0_REG - DDRDATACH0_CR_DDRCRDATACONTROL0_REG) * Channel);
+      MrcWriteCrMulticast (MrcData, Offset, DdrCrDataControl0.Data);
+
+      //
+      // Set ForceBiasOn and make sure ForceRxAmpOn is cleared
+      //
+      for (Byte = 0; Byte < Outputs->SdramCount; Byte++) {
+        DdrCrDataControl2.Data              = ChannelOut->DqControl2[Byte].Data;
+        DdrCrDataControl2.Bits.ForceBiasOn  = 1;
+        DdrCrDataControl2.Bits.ForceRxOn    = 0;
+#ifdef ULT_FLAG
+        if (Lpddr) {
+          DdrCrDataControl2.Bits.WlLongDelEn  = 1;
+        }
+#endif // ULT_FLAG
+        Offset = DDRDATA0CH0_CR_DDRCRDATACONTROL2_REG +
+          ((DDRDATA0CH1_CR_DDRCRDATACONTROL2_REG - DDRDATA0CH0_CR_DDRCRDATACONTROL2_REG) * Channel) +
+          ((DDRDATA1CH0_CR_DDRCRDATACONTROL2_REG - DDRDATA0CH0_CR_DDRCRDATACONTROL2_REG) * Byte);
+        MrcWriteCR (MrcData, Offset, DdrCrDataControl2.Data);
+      }
+    }
+  }
+
+  for (Rank = 0; Rank < MAX_RANK_IN_CHANNEL; Rank++) {
+    RankMask = MRC_BIT0 << Rank;
+    if (!(RankMask & ValidRankMask)) {
+      //
+      // Skip if all channels empty
+      //
+      continue;
+    }
+
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\nRank %d\n", Rank);
+    RankDouble  = Rank * 2;
+    RankHalf    = Rank / 2;
+    RankMod2    = Rank % 2;
+    //
+    // Program MR1: Set A7 to enter Write Leveling mode
+    // Write MaskRasWe to prevent scheduler from issuing non-Read commands
+    //
+    for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+      if (MrcRankInChannelExist (MrcData, Rank, Channel)) {
+
+        ChannelOut = &ControllerOut->Channel[Channel];
+
+#ifdef ULT_FLAG
+        //
+        // Enable WL mode in MR2[7]
+        //
+        if (Lpddr) {
+          CRValue = (ChannelOut->Dimm[RankHalf].Rank[RankMod2].MR[mrMR2]);
+          Status  = MrcIssueMrw (MrcData, Channel, Rank, mrMR2, (CRValue | MRC_BIT7), FALSE, FALSE);
+        } else
+#endif // ULT_FLAG
+        {
+          Ddr3ModeRegister1.Data = ChannelOut->Dimm[RankHalf].Rank[RankMod2].MR[mrMR1];
+          Ddr3ModeRegister1.Bits.WriteLeveling = 1;
+
+          OdtTableIndex = GetOdtTableIndex (MrcData, Channel, RANK_TO_DIMM_NUMBER (Rank));
+          if (OdtTableIndex == NULL) {
+            MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Error: OdtTableIndex is NULL!\n");
+            return mrcFail;
+          }
+#ifdef ULT_FLAG
+          if (Inputs->CpuModel == cmHSW_ULT) {  // DDR3L case
+            Ddr3ModeRegister1 = UpdateRttNomValue (MrcData, OdtTableIndex->RttWr, Ddr3ModeRegister1);
+          }
+#endif // ULT_FLAG
+
+          //
+          // In write leveling mode Rtt_Nom = Rtt_Wr ONLY for 2DPC
+          //
+          if (ChannelOut->DimmCount == 2) {
+            Ddr3ModeRegister1 = UpdateRttNomValue (MrcData, OdtTableIndex->RttWr, Ddr3ModeRegister1);
+          }
+          Status = MrcWriteMRS (MrcData, Channel, RankMask, mrMR1, (U16) Ddr3ModeRegister1.Data);
+        }
+
+        //
+        // Assert ODT for myself
+        //
+        OdtMatrix = RankMask;
+        if (ChannelOut->DimmCount == 2) {
+          //
+          // Calculate non-target DIMM
+          //
+          OtherDimm = ((Rank + 2) / 2) & MRC_BIT0;
+          //
+          // Assert ODT for non-target DIMM
+          //
+          OdtMatrix |= 1 << (2 * OtherDimm);
+        }
+
+        ReutChMiscOdtCtrl.Data = 0;
+#ifdef ULT_FLAG
+        if (Lpddr) {
+          //
+          // Only one ODT pin for ULT
+          //
+          ReutChMiscOdtCtrl.Bits.ODT_On       = 1;
+          ReutChMiscOdtCtrl.Bits.ODT_Override = 1;
+        }
+#endif // ULT_FLAG
+#ifdef TRAD_FLAG
+        if ((Inputs->CpuModel == cmHSW) || (Inputs->CpuModel == cmCRW)) {
+          ReutChMiscOdtCtrl.Bits.ODT_On       = OdtMatrix;
+          ReutChMiscOdtCtrl.Bits.ODT_Override = MCHBAR_CH0_CR_REUT_CH_MISC_ODT_CTRL_ODT_Override_MAX;
+        }
+#endif // TRAD_FLAG
+        Offset = MCHBAR_CH0_CR_REUT_CH_MISC_ODT_CTRL_REG +
+          ((MCHBAR_CH1_CR_REUT_CH_MISC_ODT_CTRL_REG - MCHBAR_CH0_CR_REUT_CH_MISC_ODT_CTRL_REG) * Channel);
+        MrcWriteCR (MrcData, Offset, ReutChMiscOdtCtrl.Data);
+      }
+    }  // for Channel
+
+    //
+    // ******************************************
+    // STEP 1 and 2: Find middle of high region
+    // ******************************************
+    //
+    WLStart = 192;
+    WLStop  = 320;
+    WLStep  = 2;
+
+    MRC_DEBUG_MSG (
+      Debug,
+      MSG_LEVEL_NOTE,
+      "\n\tCh0\t\t\t\t\t\t\t\t%sCh1\n",
+      (Outputs->SdramCount == MAX_SDRAM_IN_DIMM) ? "\t" : ""
+      );
+
+    MRC_DEBUG_MSG (
+      Debug,
+      MSG_LEVEL_NOTE,
+      "WLDelay%s%s",
+      (Outputs->SdramCount == MAX_SDRAM_IN_DIMM) ? "\t0\t1\t2\t3\t4\t5\t6\t7\t8" : "\t0\t1\t2\t3\t4\t5\t6\t7",
+      (Outputs->SdramCount == MAX_SDRAM_IN_DIMM) ? "\t0\t1\t2\t3\t4\t5\t6\t7\t8" : "\t0\t1\t2\t3\t4\t5\t6\t7"
+      );
+
+    for (WLDelay = WLStart; WLDelay < WLStop; WLDelay += WLStep) {
+      MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\n %d:", WLDelay);
+      //
+      // Program WL DQS Delays:
+      //
+      for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+        if (MrcRankInChannelExist (MrcData, Rank, Channel)) {
+
+          ChannelOut = &ControllerOut->Channel[Channel];
+
+          //
+          // Enable Write Level Mode in DDR and Propagate delay values (without a write command).
+          // Stay in WLMode.
+          //
+          DdrCrData0Control0.Data                 = ChannelOut->DqControl0.Data;
+          DdrCrData0Control0.Bits.WLTrainingMode  = 1;
+          DdrCrData0Control0.Bits.TxPiOn          = 1;
+          DdrCrData0Control0.Bits.ReadRFRd        = 0;
+          DdrCrData0Control0.Bits.ReadRFWr        = 1;
+          DdrCrData0Control0.Bits.ReadRFRank      = Rank;
+          for (Byte = 0; Byte < Outputs->SdramCount; Byte++) {
+            UpdateTxT (MrcData, Channel, Rank, Byte, 1, WLDelay);
+
+            Offset = DDRDATA0CH0_CR_DDRCRDATACONTROL0_REG +
+              ((DDRDATA0CH1_CR_DDRCRDATACONTROL0_REG - DDRDATA0CH0_CR_DDRCRDATACONTROL0_REG) * Channel) +
+              ((DDRDATA1CH0_CR_DDRCRDATACONTROL0_REG - DDRDATA0CH0_CR_DDRCRDATACONTROL0_REG) * Byte);
+            MrcWriteCR (MrcData, Offset, DdrCrData0Control0.Data);
+          }
+        }
+      }
+
+      if (WLDelay == WLStart) {
+        MrcWait (MrcData, (WaitTime * HPET_1US));  // Wait for the first burst to finish
+      }
+
+      Status = IoReset (MrcData);
+
+      MrcWait (MrcData, (WaitTime * HPET_1US));
+
+      //
+      // Update results for all Channels/Bytes
+      //
+      for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+        if (!MrcRankInChannelExist (MrcData, Rank, Channel)) {
+          MRC_DEBUG_MSG (
+            Debug,
+            MSG_LEVEL_NOTE,
+            "\t\t\t\t\t\t\t\t%s",
+            (Outputs->SdramCount == MAX_SDRAM_IN_DIMM) ? "\t" : ""
+            );
+          continue;
+        }
+        for (Byte = 0; Byte < Outputs->SdramCount; Byte++) {
+          Offset = DDRDATA0CH0_CR_DATATRAINFEEDBACK_REG +
+            ((DDRDATA0CH1_CR_DATATRAINFEEDBACK_REG - DDRDATA0CH0_CR_DATATRAINFEEDBACK_REG) * Channel) +
+            ((DDRDATA1CH0_CR_DATATRAINFEEDBACK_REG - DDRDATA0CH0_CR_DATATRAINFEEDBACK_REG) * Byte);
+          DataTrainFeedback.Data  = MrcReadCR (MrcData, Offset);
+          Pass                    = (DataTrainFeedback.Bits.DataTrainFeedback >= 16);
+          MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\t%c%d", Pass ? '.' : '#', DataTrainFeedback.Data);
+          if (WLDelay == WLStart) {
+            if (Pass) {
+              InitialPassingStart[Channel][Byte] = InitialPassingEnd[Channel][Byte]  = WLStart;
+              CurrentPassingStart[Channel][Byte] = CurrentPassingEnd[Channel][Byte]  = WLStart;
+              LargestPassingStart[Channel][Byte] = LargestPassingEnd[Channel][Byte]  = WLStart;
+            } else {
+              InitialPassingStart[Channel][Byte] = InitialPassingEnd[Channel][Byte]  = -WLStep;
+              CurrentPassingStart[Channel][Byte] = CurrentPassingEnd[Channel][Byte]  = -WLStep;
+              LargestPassingStart[Channel][Byte] = LargestPassingEnd[Channel][Byte]  = -WLStep;
+            }
+          } else {
+            if (Pass) {
+              if (InitialPassingEnd[Channel][Byte] == (WLDelay - WLStep)) {
+                InitialPassingEnd[Channel][Byte] = WLDelay;
+              }
+
+              if (CurrentPassingEnd[Channel][Byte] == (WLDelay - WLStep)) {
+                CurrentPassingEnd[Channel][Byte] = WLDelay;
+              } else {
+                CurrentPassingStart[Channel][Byte] = CurrentPassingEnd[Channel][Byte] = WLDelay;
+              }
+              //
+              // Special case for last step: Append Initial Passing Region
+              // WLDelay should be considered a continuous range that wraps around 0
+              //
+              if ((WLDelay >= (WLStop - WLStep)) && (InitialPassingStart[Channel][Byte] == WLStart)) {
+                iWidth = (InitialPassingEnd[Channel][Byte] - InitialPassingStart[Channel][Byte]);
+                CurrentPassingEnd[Channel][Byte] += (WLStep + iWidth);
+              }
+              //
+              // Update Largest variables
+              //
+              cWidth  = CurrentPassingEnd[Channel][Byte] - CurrentPassingStart[Channel][Byte];
+              lWidth  = LargestPassingEnd[Channel][Byte] - LargestPassingStart[Channel][Byte];
+              if (cWidth > lWidth) {
+                LargestPassingStart[Channel][Byte]  = CurrentPassingStart[Channel][Byte];
+                LargestPassingEnd[Channel][Byte]    = CurrentPassingEnd[Channel][Byte];
+              }
+            }
+          }
+        } // for Byte
+      } // for Channel
+    } // for WLDelay
+
+#ifdef MRC_DEBUG_PRINT
+    MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\n\tInitPassSt\tInitPassEn\tCurrPassSt\tCurrPassEn\tLargPassSt\tLargPassEn\n");
+
+    for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+      if (MrcRankInChannelExist (MrcData, Rank, Channel)) {
+        MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "C%d\n", Channel);
+        for (Byte = 0; Byte < Outputs->SdramCount; Byte++) {
+          MRC_DEBUG_MSG (
+            Debug,
+            MSG_LEVEL_NOTE,
+            "   B%d:\t\t%d\t\t%d\t\t%d\t\t%d\t\t%d\t\t%d\n",
+            Byte,
+            InitialPassingStart[Channel][Byte],
+            InitialPassingEnd[Channel][Byte],
+            CurrentPassingStart[Channel][Byte],
+            CurrentPassingEnd[Channel][Byte],
+            LargestPassingStart[Channel][Byte],
+            LargestPassingEnd[Channel][Byte]
+            );
+      }
+    }
+  }
+#endif // MRC_DEBUG_PRINT
+
+    //
+    // Clean up after step
+    // Very coarsely adjust for any cycle errors
+    // Program values for TxDQS
+    //
+    for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+      if (MrcRankInChannelExist (MrcData, Rank, Channel)) {
+
+        ChannelOut = &ControllerOut->Channel[Channel];
+
+        //
+        // Check if rank is a x16
+        //
+        RankIsx16 = (ChannelOut->Dimm[RankHalf].SdramWidth == 16 ? TRUE : FALSE);
+
+        //
+        // Clear ODT before MRS (JEDEC Spec)
+        //
+        Offset = MCHBAR_CH0_CR_REUT_CH_MISC_ODT_CTRL_REG +
+          ((MCHBAR_CH1_CR_REUT_CH_MISC_ODT_CTRL_REG - MCHBAR_CH0_CR_REUT_CH_MISC_ODT_CTRL_REG) * Channel);
+        MrcWriteCR (MrcData, Offset, 0);
+
+#ifdef ULT_FLAG
+        //
+        // Restore MR2 values
+        //
+        if (Lpddr) {
+          CRValue = (ChannelOut->Dimm[RankHalf].Rank[RankMod2].MR[mrMR2]);
+          Status  = MrcIssueMrw (MrcData, Channel, Rank, mrMR2, CRValue, FALSE, FALSE);
+        } else
+#endif // ULT_FLAG
+        {
+          //
+          // Restore Write Leveling mode and Rtt_Nom for this rank
+          //
+          CRValue = (ChannelOut->Dimm[RankHalf].Rank[RankMod2].MR[mrMR1]);
+          Status  = MrcWriteMRS (MrcData, Channel, RankMask, mrMR1, (U16) CRValue);
+        }
+
+        MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "C%d.R%d:  LftEdge Width\n", Channel, Rank);
+        for (Byte = 0; Byte < Outputs->SdramCount; Byte++) {
+          ByteWidth = LargestPassingEnd[Channel][Byte] - LargestPassingStart[Channel][Byte];
+          MRC_DEBUG_MSG (
+            Debug,
+            MSG_LEVEL_NOTE,
+            "  B%d:   %d\t%d\n",
+            Byte,
+            LargestPassingStart[Channel][Byte],
+            ByteWidth
+            );
+
+          //
+          // Check if width is valid
+          //
+          if ((ByteWidth <= 32) || (ByteWidth >= 96)) {
+            MRC_DEBUG_MSG (
+              Debug,
+              MSG_LEVEL_ERROR,
+              "\nERROR! Width region outside expected limits for Channel: %u Rank %u Byte: %u\n",
+              Channel,
+              Rank,
+              Byte
+              );
+            return mrcWriteLevelingError;
+          }
+          //
+          // Align byte pairs if DIMM is x16
+          //
+          if (RankIsx16 && (Byte & MRC_BIT0)) {
+            //
+            // If odd byte number (1, 3, 5 or 7)
+            //
+            refbyte = Byte - 1;
+            if (LargestPassingStart[Channel][Byte] > (LargestPassingStart[Channel][refbyte] + 64)) {
+              LargestPassingStart[Channel][Byte] -= 128;
+            }
+
+            if (LargestPassingStart[Channel][Byte] < (LargestPassingStart[Channel][refbyte] - 64)) {
+              LargestPassingStart[Channel][Byte] += 128;
+            }
+          }
+
+#ifdef ULT_FLAG
+          if (Inputs->CpuModel == cmHSW_ULT) {
+            //
+            // Fix for b4618067 - need to add 1 QCLK to DqsPi
+            //
+            LargestPassingStart[Channel][Byte] += 64;
+          }
+#endif // ULT_FLAG
+
+          ChannelOut->TxDqs[Rank][Byte] = (U16) LargestPassingStart[Channel][Byte];
+          ChannelOut->TxDq[Rank][Byte]  = (U16) (LargestPassingStart[Channel][Byte] + 32);
+          UpdateTxT (MrcData, Channel, Rank, Byte, 0xFF, 0);
+        }
+      }
+    }
+  }
+  //
+  // Clean up after Test
+  //
+  for (Channel = 0; Channel < MAX_CHANNEL; Channel++) {
+    if (MrcChannelExist (Outputs, Channel)) {
+
+      ChannelOut = &ControllerOut->Channel[Channel];
+
+      Offset = DDRDATACH0_CR_DDRCRDATACONTROL0_REG +
+        ((DDRDATACH1_CR_DDRCRDATACONTROL0_REG - DDRDATACH0_CR_DDRCRDATACONTROL0_REG) * Channel);
+      MrcWriteCrMulticast (MrcData, Offset, ChannelOut->DqControl0.Data);
+
+      //
+      // Restore DqControl2 values.
+      //
+      for (Byte = 0; Byte < Outputs->SdramCount; Byte++) {
+        Offset = DDRDATA0CH0_CR_DDRCRDATACONTROL2_REG +
+          ((DDRDATA0CH1_CR_DDRCRDATACONTROL2_REG - DDRDATA0CH0_CR_DDRCRDATACONTROL2_REG) * Channel) +
+          ((DDRDATA1CH0_CR_DDRCRDATACONTROL2_REG - DDRDATA0CH0_CR_DDRCRDATACONTROL2_REG) * Byte);
+        MrcWriteCR (MrcData, Offset, ChannelOut->DqControl2[Byte].Data);
+      }
+    }
+  }
+
+#ifdef ULT_FLAG
+  if (!Lpddr)
+#endif // ULT_FLAG
+  {
+    //
+    // DLLEnable=0, Dic=0, Al=0, Level=0, Tdqs=0, Qoff=0
+    //
+    Status = MrcSetMR1 (MrcData, 0, DIMMRON, 0, 0, 0, 0);
+    if (Status != mrcSuccess) {
+      MRC_DEBUG_MSG (Debug, MSG_LEVEL_ERROR, "ERROR: RESET FAIL - WLT\n");
+      return Status;
+    }
+  }
+
+  // Restore flag
+  Outputs->RestoreMRs = SavedRestoreMRS;
+
+  MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "\nJedec Write Leveling CLEANUP\n");
+  Status = MrcJedecWriteLevelingCleanUp (MrcData);
+
+  return Status;
+}
diff --git a/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/WriteTraining/MrcWriteLeveling.h b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/WriteTraining/MrcWriteLeveling.h
new file mode 100644
index 0000000..bbb6ceb
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/WriteTraining/MrcWriteLeveling.h
@@ -0,0 +1,85 @@
+/** @file
+  The write leveling training algorithm definitions.
+
+@copyright
+  Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved.
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement.
+**/
+
+#ifndef _MrcWriteLeveling_h_
+#define _MrcWriteLeveling_h_
+
+#include "MrcTypes.h"
+#include "MrcApi.h"
+#include "McAddress.h"
+#include "MrcCommon.h"
+#include "MrcReset.h"
+#include "MrcDdr3.h"
+#include "MrcIoControl.h"
+#include "MrcReadReceiveEnable.h"
+#include "MrcOem.h"
+
+///
+/// This defines the maximum ADD delay that can be programmed to the register. It may change in the future
+///
+#define MAX_ADD_DELAY (2)
+
+/**
+@brief
+  this function execute the Jedec write leveling Cleanup.
+  Center TxDQS-CLK timing
+
+  @param[in, out] MrcData - Include all MRC global data.
+
+  @retval MrcStatus -  if it succeded return mrcSuccess
+**/
+extern
+MrcStatus
+MrcJedecWriteLevelingCleanUp (
+  IN OUT MrcParameters *const MrcData
+  );
+
+/**
+@brief
+  this function execute the functional write leveling training.
+  Center TxDQS-CLK timing
+
+  @param[in, out] MrcData - Include all MRC global data.
+
+  @retval MrcStatus -  if it succeded return mrcSuccess
+**/
+extern
+MrcStatus
+MrcWriteLevelingTraining (
+  IN OUT MrcParameters *const MrcData
+  );
+
+/**
+@brief
+  this function execute the Jedec write leveling training.
+  Center TxDQS-CLK timing
+
+  @param[in, out] MrcData - Include all MRC global data.
+
+  @retval MrcStatus -  if it succedes return mrcSuccess
+**/
+extern
+MrcStatus
+MrcJedecWriteLevelingTraining (
+  IN OUT MrcParameters *const MrcData
+  );
+
+#endif // _MrcWriteLeveling_h_
diff --git a/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/SsaCallbackPeim.h b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/SsaCallbackPeim.h
new file mode 100644
index 0000000..11bdcd6
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/SsaCallbackPeim.h
@@ -0,0 +1,56 @@
+/**
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement
+**/
+
+/**
+
+Copyright (c)  2012 - 2012 Intel Corporation. All rights reserved
+This software and associated documentation (if any) is furnished
+under a license and may only be used or copied in accordance
+with the terms of the license. Except as permitted by such
+license, no part of this software or documentation may be
+reproduced, stored in a retrieval system, or transmitted in any
+form or by any means without the express written consent of
+Intel Corporation.
+
+@file
+  SsaCallbackPeim.h
+
+@brief
+  Header file for the SSA BIOS Callback Init PEIM
+**/
+#ifndef _SSA_CALLBACK_PEIM_H_
+#define _SSA_CALLBACK_PEIM_H_
+
+#include "EdkIIGluePeim.h"
+#include "MrcTypes.h"
+#include "MrcDebugHook.h"
+#include "MrcGlobal.h"
+
+struct _SSA_BIOS_CALLBACKS_PPI;
+
+extern EFI_GUID gSsaBiosCallBacksPpiGuid;
+typedef int MRC_OEM_STATUS_COMMAND;
+
+typedef 
+MrcStatus
+(EFIAPI * MRC_CHECKPOINT) (
+  EFI_PEI_SERVICES                 **PeiServices,
+  struct _SSA_BIOS_CALLBACKS_PPI   *SsaBiosCallBacksPpi,
+  MRC_OEM_STATUS_COMMAND           StatusCommand,
+  VOID                             *CheckpointData
+  );
+
+typedef struct _SSA_BIOS_CALLBACKS_PPI {
+  UINT32                      Revision;
+  MRC_CHECKPOINT              MrcCheckpoint;
+  VOID                        *ModuleState;
+} SSA_BIOS_CALLBACKS_PPI;
+
+
+#endif
diff --git a/ReferenceCode/Chipset/SystemAgent/PciHostBridge/Dxe/PciHostBridge.c b/ReferenceCode/Chipset/SystemAgent/PciHostBridge/Dxe/PciHostBridge.c
new file mode 100644
index 0000000..e660935
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/PciHostBridge/Dxe/PciHostBridge.c
@@ -0,0 +1,1414 @@
+/** @file
+  Provides the basic interfaces to abstract a PCI Host Bridge Resource Allocation
+
+@copyright
+  Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement
+
+**/
+#include "Token.h"   // <<< AMI_OVERRIDE
+#include "PciHostBridge.h"
+#include "PciRootBridge.h"
+#include "PchAccess.h" 			// <<< AMI_OVERRIDE - EIP# 42483 - Support for Multi-Monitor	>>>
+#ifndef GUID_VARIABLE_DECLARATION // AMI_OVERRIDE ... EIP#42483: MemCeiling support	<<>>
+#define GUID_VARIABLE_DECLARATION(Variable, Guid) extern EFI_GUID Variable
+#endif
+#include <Protocol\NBMemInfo.h> // AMI_OVERRIDE ... EIP#42483: MemCeiling support	<<>>
+///
+/// Support 64 K IO space
+/// Moving RES_IO_BASE due to new ACPI Base address 0x1800
+///
+#define RES_IO_BASE   0x2000
+#define RES_IO_LIMIT  0xFFFF
+
+///
+/// Support 4G address space
+///
+#define RES_MEM_LIMIT_1 ((UINTN) MmPciAddress (0,0,0,0,0) - 1)
+
+///
+/// Hard code: Root Bridge Number within the host bridge
+///            Root Bridge's attribute
+///            Root Bridge's device path
+///            Root Bridge's resource aperture
+///
+static UINTN                              RootBridgeNumber[1] = { 1 };
+///
+/// Hard code EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM  0 to support prefetchable memory allocation
+///
+#ifdef AMI_COMBINE_MEM_PMEM_FLAG
+static UINT64                             RootBridgeAttribute[1][1] = { EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM };
+#else // AMI_COMBINE_MEM_PMEM_FLAG
+static UINT64                             RootBridgeAttribute[1][1] = { 0 };
+#endif // AMI_COMBINE_MEM_PMEM_FLAG
+static EFI_PCI_ROOT_BRIDGE_DEVICE_PATH    mEfiPciRootBridgeDevicePath[1][1] = {
+  {
+    ACPI_DEVICE_PATH,
+    ACPI_DP,
+    (UINT8) (sizeof (ACPI_HID_DEVICE_PATH)),
+    (UINT8) ((sizeof (ACPI_HID_DEVICE_PATH)) >> 8),
+    EISA_PNP_ID(0x0A03),
+    0,
+    END_DEVICE_PATH_TYPE,
+    END_ENTIRE_DEVICE_PATH_SUBTYPE,
+    END_DEVICE_PATH_LENGTH,
+    0
+  }
+};
+
+static PCI_ROOT_BRIDGE_RESOURCE_APERTURE  mResAperture[1][1] = { { 0, ((UINT8)((PCIEX_LENGTH >> 20) - 1)), 0, 0xffffffff, 0, 1 << 16 } }; // <<< AMI_OVERRIDE
+static EFI_HANDLE                         mDriverImageHandle;
+CHAR16 gMemoryCeilingVariable[]     = L"MemCeil.";			// AMI_OVERRIDE ... EIP#42483: MemCeiling support	<<>>
+EFI_GUID gEfiNbMrcS3DataGuid = EFI_NB_MRC_S3_DATA_GUID; // AMI_OVERRIDE ... EIP#42483: MemCeiling support	<<>>
+
+// AMI_OVERRIDE ... Fixed GenericSio use 0x0 ~ 0xfff issue start.
+// It will Override CoreAllocateIoSpace.
+static EFI_ALLOCATE_IO_SPACE   gAmiCoreAllocateIoSpace;
+
+EFI_STATUS
+NbCspOverrideCoreAllocateIoSpace (
+  IN     EFI_GCD_ALLOCATE_TYPE  GcdAllocateType,
+  IN     EFI_GCD_IO_TYPE        GcdIoType,
+  IN     UINTN                  Alignment,
+  IN     UINT64                 Length,
+  IN OUT EFI_PHYSICAL_ADDRESS   *BaseAddress,
+  IN     EFI_HANDLE             ImageHandle,
+  IN     EFI_HANDLE             DeviceHandle OPTIONAL
+  )
+{
+  EFI_STATUS	Status;
+  EFI_GCD_IO_SPACE_DESCRIPTOR  IoDescriptor;
+
+  if (GcdIoType == EfiGcdIoTypeIo && *BaseAddress < RES_IO_BASE)
+  {
+     if(GcdAllocateType == EfiGcdAllocateAddress)
+     {
+         Status = gDS->GetIoSpaceDescriptor(*BaseAddress, &IoDescriptor);
+         if(!EFI_ERROR(Status))
+         {
+            if(IoDescriptor.GcdIoType == EfiGcdIoTypeNonExistent)
+            {
+               Status = gDS->AddIoSpace (
+                         EfiGcdIoTypeIo,
+                         *BaseAddress,
+                         Length
+                         );
+//               ASSERT_EFI_ERROR (Status);
+            }
+         }
+     }
+  }
+
+  return gAmiCoreAllocateIoSpace (
+                 GcdAllocateType,
+                 GcdIoType,
+                 Alignment,
+                 Length,
+                 BaseAddress,
+                 ImageHandle,
+                 DeviceHandle
+                 );
+}
+// AMI_OVERRIDE ... Fixed GenericSio use 0x0 ~ 0xfff issue end.
+
+//AMI_OVERRIDE START     // AMI_OVERRIDE ... EIP#42483: MemCeiling support   ...Start...
+EFI_STATUS
+HbCspAdjustMemoryMmioOverlap (
+    PCI_ROOT_BRIDGE_INSTANCE          *RootBridgeInstance
+ )
+{
+	EFI_STATUS	Status;
+    EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap;
+    UINTN           NumberOfDescriptors;
+	PCI_RES_NODE	res;
+    UINTN           i;
+    EFI_PHYSICAL_ADDRESS Highest4GMem    = 0;
+    EFI_PHYSICAL_ADDRESS LowestMMIO      = 0xffffffff;
+    EFI_PHYSICAL_ADDRESS LowestAllocMMIO = 0xffffffff;
+	UINTN	        MemoryCeiling = 0;      //Init to zero incase variable doesn't exist.
+    UINTN           NewMemoryCeiling = 0xffffffff;
+    UINTN	        DataSize = sizeof(UINT32);
+    EFI_PHYSICAL_ADDRESS NeededBottomMmio;
+    UINT32          Attributes = 0;             // [ EIP167027 ]
+
+//------------------------------------
+    //Status = gRT->GetVariable (               // [ EIP167027 ]
+    //                 gMemoryCeilingVariable,
+    //                 &gEfiNbMrcS3DataGuid,
+    //                 NULL,
+    //                 &DataSize,
+    //                 &MemoryCeiling );
+    Status = gRT->GetVariable (
+                     gMemoryCeilingVariable,
+                     &gEfiNbMrcS3DataGuid,
+                     &Attributes,
+                     &DataSize,
+                     &MemoryCeiling );
+
+    DEBUG((-1, "OEM trace - GetVariable MemCeil Status = %r\n", Status));
+
+    if (EFI_ERROR(Status))
+        Attributes = EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS;
+
+    if (Status == EFI_NOT_FOUND) {
+      //Status = gRT->GetVariable (             // [ EIP167027 ]
+      //                 gMemoryCeilingVariable,
+      //                 &gEfiGlobalVariableGuid,
+      //                 NULL,
+      //                 &DataSize,
+      //                 &MemoryCeiling
+      //         );
+      Status = gRT->GetVariable (
+                       gMemoryCeilingVariable,
+                       &gEfiGlobalVariableGuid,
+                       &Attributes,
+                       &DataSize,
+                       &MemoryCeiling
+               );
+
+      if (!EFI_ERROR(Status)) {
+        //gRT->SetVariable (                    // [ EIP167027 ]
+        //        gMemoryCeilingVariable,
+        //        &gEfiNbMrcS3DataGuid,
+        //        EFI_VARIABLE_NON_VOLATILE
+        //                + EFI_VARIABLE_BOOTSERVICE_ACCESS
+        //                + EFI_VARIABLE_RUNTIME_ACCESS,
+        //        DataSize,
+        //        &MemoryCeiling
+        //);
+        gRT->SetVariable (
+                gMemoryCeilingVariable,
+                &gEfiNbMrcS3DataGuid,
+                Attributes,
+                DataSize,
+                &MemoryCeiling
+        );
+      }
+      else
+        Attributes = EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS;
+    }
+
+    //Memory sizing uses memory ceiling to set top of memory.
+
+    Status = gDS->GetMemorySpaceMap(&NumberOfDescriptors, &MemorySpaceMap);
+    ASSERT_EFI_ERROR(Status);
+
+    //Find the lowest MMIO and lowest allocated MMIO in GCD.
+    for(i = 0; i < NumberOfDescriptors; ++i) {
+        EFI_GCD_MEMORY_SPACE_DESCRIPTOR *Descr = &MemorySpaceMap[i];
+        EFI_PHYSICAL_ADDRESS Base = Descr->BaseAddress;
+        //Find highest system below 4GB memory.
+        //Treat any non MMIO as system memory. Not all system memory is reported as system memory,
+        //such as SMM.
+        if (Descr->GcdMemoryType != EfiGcdMemoryTypeMemoryMappedIo && Base < LowestMMIO) {
+            EFI_PHYSICAL_ADDRESS EndMem = Base + Descr->Length - 1;
+            if (EndMem > Highest4GMem && EndMem <= 0xffffffff) Highest4GMem = EndMem;
+
+        //Find Lowest mmio above system memory.
+        } else if (Descr->GcdMemoryType == EfiGcdMemoryTypeMemoryMappedIo) {
+            if (Base >= 0x100000) {
+                if (Base < LowestMMIO) LowestMMIO = Base;
+                //If ImageHandle, then MMIO is allocated.
+                if (Base < LowestAllocMMIO && Descr->ImageHandle) LowestAllocMMIO = Base;
+            }
+        }
+    }
+
+    (gBS->FreePool)(MemorySpaceMap);
+
+    if (Highest4GMem + 1 != LowestMMIO) {
+        DEBUG((-1, "PciHostCSHooks: System Memory and MMIO are not consequitive.\n  Top of Below 4G Memory: %lX\n   Bottom of MMIO: %x%x\n",
+            Highest4GMem, LowestMMIO ));
+    }
+
+    //Find any MMIO that could not be allocated due to small of MMIO region.
+    NeededBottomMmio = LowestAllocMMIO;
+	for(i = 0; i < TypeMax; ++i) {
+
+		res=RootBridgeInstance->ResAllocNode[i];
+        if ((res.Type == TypeMem32 && (res.Status != ResNone) && (res.Status != ResAllocated)) ||
+                (res.Type == TypePMem32 && (res.Status != ResNone) && (res.Status != ResAllocated))) {
+            //Determine new memory ceiling variable needed to allocate this memory.
+            NeededBottomMmio = NeededBottomMmio - res.Length;
+            NeededBottomMmio &= ~(res.Alignment);
+            if (NeededBottomMmio < NewMemoryCeiling) NewMemoryCeiling = (UINTN) NeededBottomMmio;
+        }
+    }
+
+    if (NewMemoryCeiling < 0xffffffff) {    //Check if a NewMemory Ceiling is needed.
+
+        // Adjust the granularity
+        NewMemoryCeiling &= (~(TOP_LOW_MEM_GRANULARITY - 1));
+
+        if (MemoryCeiling == NewMemoryCeiling) return EFI_SUCCESS;  //No change in system configuration. Nothing more to do. Just exit.
+
+        // Change in system config, so MMIO requirement changed. Update MemCeil and do reset.
+		// Set memory ceiling variable.
+		//gRT->SetVariable(                     // [ EIP167027 ]
+		//	gMemoryCeilingVariable,
+		//	&gEfiNbMrcS3DataGuid,
+		//	EFI_VARIABLE_NON_VOLATILE
+		//		+ EFI_VARIABLE_BOOTSERVICE_ACCESS
+		//		+ EFI_VARIABLE_RUNTIME_ACCESS,
+		//	DataSize,
+		//	&NewMemoryCeiling
+		//);
+		gRT->SetVariable(
+			gMemoryCeilingVariable,
+			&gEfiNbMrcS3DataGuid,
+			Attributes,
+			DataSize,
+			&NewMemoryCeiling
+		);
+
+        DEBUG((-1, "Adjusting maximum top of RAM.\n Resetting System.\n"));
+
+#if (NV_SIMULATION != 1)
+        //Reset only needed of type of physical memory overlaps with MMIO.
+	gRT->ResetSystem (EfiResetCold, EFI_SUCCESS, 0, NULL);
+#endif
+
+    }
+
+	return Status;
+}
+//AMI_OVERRIDE   ... // AMI_OVERRIDE ... EIP#42483: MemCeiling support ...END...
+
+EFI_DRIVER_ENTRY_POINT (PciHostBridgeEntryPoint)
+///
+/// Implementation
+///
+/**
+  Entry point of this driver
+
+  @param[in] ImageHandle -
+  @param[in] SystemTable -
+
+  @retval EFI_SUCCESS       - Driver Start OK
+  @retval EFI_DEVICE_ERROR  - Fail to install PCI_ROOT_BRIDGE_IO protocol.
+**/
+EFI_STATUS
+EFIAPI
+PciHostBridgeEntryPoint (
+  IN EFI_HANDLE       ImageHandle,
+  IN EFI_SYSTEM_TABLE *SystemTable
+  )
+{
+  EFI_STATUS                Status;
+  UINTN                     Loop1;
+  UINTN                     Loop2;
+  PCI_HOST_BRIDGE_INSTANCE  *HostBridge;
+  PCI_ROOT_BRIDGE_INSTANCE  *PrivateData;
+  EFI_PHYSICAL_ADDRESS      PciBaseAddress;
+  EFI_PHYSICAL_ADDRESS      RemapBase;
+  EFI_PHYSICAL_ADDRESS      RemapLimit;
+  EFI_PHYSICAL_ADDRESS      MeSegMask;
+  EFI_PHYSICAL_ADDRESS      MeStolenSize;
+  BOOLEAN                   MeStolenEnable;
+  UINT32                    Tolud;
+  UINT64                    Length;
+  EFI_PHYSICAL_ADDRESS      BaseAddress;
+  CPU_FAMILY                CpuFamilyId;
+  CPU_STEPPING              CpuSteppingId;
+#ifndef AMI_OVERRIDE_FOR_REMAP_DISABLED
+  EFI_PHYSICAL_ADDRESS      MeStolenBase;
+#endif // AMI_OVERRIDE_FOR_REMAP_DISABLED
+
+  INITIALIZE_SCRIPT (ImageHandle, SystemTable);
+
+  mDriverImageHandle = ImageHandle;
+
+  ///
+  /// This system has one Host Bridge (one Root Bridge in this Host Bridge)
+  ///
+  ///
+  /// Create Host Bridge Device Handle
+  ///
+  for (Loop1 = 0; Loop1 < HOST_BRIDGE_NUMBER; Loop1++) {
+    Status = (gBS->AllocatePool) (EfiBootServicesData, sizeof (PCI_HOST_BRIDGE_INSTANCE), (VOID **) &HostBridge);
+    ASSERT (!EFI_ERROR (Status));
+
+    HostBridge->Signature         = PCI_HOST_BRIDGE_SIGNATURE;
+    HostBridge->RootBridgeNumber  = RootBridgeNumber[Loop1];
+    HostBridge->ResourceSubmited  = FALSE;
+    HostBridge->CanRestarted      = TRUE;
+
+    ///
+    /// InitializeListHead (&HostBridge->Head);
+    ///
+    HostBridge->ResAlloc.NotifyPhase          = NotifyPhase;
+    HostBridge->ResAlloc.GetNextRootBridge    = GetNextRootBridge;
+    HostBridge->ResAlloc.GetAllocAttributes   = GetAttributes;
+    HostBridge->ResAlloc.StartBusEnumeration  = StartBusEnumeration;
+    HostBridge->ResAlloc.SetBusNumbers        = SetBusNumbers;
+    HostBridge->ResAlloc.SubmitResources      = SubmitResources;
+    HostBridge->ResAlloc.GetProposedResources = GetProposedResources;
+    HostBridge->ResAlloc.PreprocessController = PreprocessController;
+    HostBridge->HostBridgeHandle              = NULL;
+    Status = gBS->InstallProtocolInterface (
+                    &HostBridge->HostBridgeHandle,
+                    &gEfiPciHostBridgeResourceAllocationProtocolGuid,
+                    EFI_NATIVE_INTERFACE,
+                    &HostBridge->ResAlloc
+                    );
+    if (EFI_ERROR (Status)) {
+      (gBS->FreePool) (HostBridge);
+      return EFI_DEVICE_ERROR;
+    }
+    ///
+    /// Create Root Bridge Device Handle in this Host Bridge
+    ///
+    InitializeListHead (&HostBridge->Head);
+    for (Loop2 = 0; Loop2 < HostBridge->RootBridgeNumber; Loop2++) {
+      Status = (gBS->AllocatePool) (EfiBootServicesData, sizeof (PCI_ROOT_BRIDGE_INSTANCE), (VOID **) &PrivateData);
+      ASSERT (!EFI_ERROR (Status));
+
+      PrivateData->Signature  = PCI_ROOT_BRIDGE_SIGNATURE;
+      PrivateData->DevicePath = (EFI_DEVICE_PATH_PROTOCOL *) &mEfiPciRootBridgeDevicePath[Loop1][Loop2];
+      RootBridgeConstructor (
+        &PrivateData->Io,
+        HostBridge->HostBridgeHandle,
+        RootBridgeAttribute[Loop1][Loop2],
+        &mResAperture[Loop1][Loop2]
+        );
+      PrivateData->Handle = NULL;
+      Status = gBS->InstallMultipleProtocolInterfaces (
+                      &PrivateData->Handle,
+                      &gEfiDevicePathProtocolGuid,
+                      PrivateData->DevicePath,
+                      &gEfiPciRootBridgeIoProtocolGuid,
+                      &PrivateData->Io,
+                      NULL
+                      );
+      if (EFI_ERROR (Status)) {
+        (gBS->FreePool) (PrivateData);
+        return EFI_DEVICE_ERROR;
+      }
+
+      InsertTailList (&HostBridge->Head, &PrivateData->Link);
+    }
+  }
+  ///
+  /// Allocate 60 KB of I/O space [0x1000..0xFFFF]
+  ///
+  Status = gDS->AddIoSpace (
+                  EfiGcdIoTypeIo,
+                  RES_IO_BASE,
+                  RES_IO_LIMIT - RES_IO_BASE + 1
+                  );
+  ASSERT_EFI_ERROR (Status);
+
+  // AMI_OVERRIDE ... Fixed GenericSio use 0x0 ~ 0xfff issue start.
+  // It will Override CoreAllocateIoSpace.
+  gAmiCoreAllocateIoSpace = gDS->AllocateIoSpace;
+  gDS->AllocateIoSpace = NbCspOverrideCoreAllocateIoSpace;
+  // AMI_OVERRIDE ... Fixed GenericSio use 0x0 ~ 0xfff issue end.
+
+  ///
+  /// Allocate PCI memory space.
+  ///
+  ///
+  /// Read memory map registers
+  ///
+  RemapBase       = McD0PciCfg64 (R_SA_REMAPBASE) & B_SA_REMAPBASE_REMAPBASE_MASK;
+  RemapLimit      = McD0PciCfg64 (R_SA_REMAPLIMIT) & B_SA_REMAPLIMIT_REMAPLMT_MASK;
+  Tolud           = McD0PciCfg32 (R_SA_TOLUD) & B_SA_TOLUD_TOLUD_MASK;
+  PciBaseAddress  = Tolud;
+  MeSegMask       = McD0PciCfg64 (R_SA_MESEG_MASK);
+  MeStolenEnable  = (BOOLEAN) ((MeSegMask & B_SA_MESEG_MASK_ME_STLEN_EN_MASK) != 0);
+
+  ///
+  /// First check if memory remap is used
+  ///
+  if ((RemapBase > RemapLimit) && (MeStolenEnable)) {
+    MeStolenSize = MeSegMask & B_SA_MESEG_MASK_MEMASK_MASK;
+    if (MeStolenSize != 0) {
+      MeStolenSize = 0x8000000000L - MeStolenSize;
+#ifndef AMI_OVERRIDE_FOR_REMAP_DISABLED
+      // Remap is disabled -> if Me Stolen Base on PCI resume, PCI resume - MeStolenSize.
+      MeStolenBase    = McD0PciCfg64 (R_SA_MESEG_BASE);
+      if(MeStolenBase < RES_MEM_LIMIT_1) {
+         //
+         // Remap is disabled -> PCI starts at TOLUD + ME Stolen size
+         //
+         PciBaseAddress += MeStolenSize;
+      }
+#endif // AMI_OVERRIDE_FOR_REMAP_DISABLED
+    }
+    ///
+    /// Remap is disabled -> PCI starts at TOLUD + ME Stolen size
+    ///
+#ifdef AMI_OVERRIDE_FOR_REMAP_DISABLED
+    PciBaseAddress += MeStolenSize;
+#endif // AMI_OVERRIDE_FOR_REMAP_DISABLED
+  }
+
+  Length = RES_MEM_LIMIT_1 - PciBaseAddress + 1;
+
+  if (Length != 0) {
+    DEBUG (
+      (
+      EFI_D_INFO, " Allocating PCI space from 0x%X to 0x%X\n", (UINT32) PciBaseAddress, (UINT32)
+      (PciBaseAddress + Length - 1)
+      )
+      );
+    Status = gDS->AddMemorySpace (
+                    EfiGcdMemoryTypeMemoryMappedIo,
+                    PciBaseAddress,
+                    Length,
+                    0
+                    );
+    ASSERT_EFI_ERROR (Status);
+  }
+  ///
+  /// Get CPU Family and Stepping ID
+  ///
+  CpuFamilyId = GetCpuFamily();
+  CpuSteppingId = GetCpuStepping();
+
+  ///
+  /// WA for HSW A0. To exclude the ranges 20000000-201FFFFF (2MB) and 0x40004000-0x40004FFF (4KB).
+  ///
+  if ((CpuFamilyId == EnumCpuHsw) && (CpuSteppingId == EnumHswA0)) {
+    if (McD0PciCfg32 (R_SA_DEVEN) & B_SA_DEVEN_D2EN_MASK) {
+      BaseAddress = 0x20000000;
+      Status = (gBS->AllocatePages) (AllocateAddress, EfiReservedMemoryType, EFI_SIZE_TO_PAGES (0x00200000), &BaseAddress);
+
+      BaseAddress = 0x40004000;
+      Status = (gBS->AllocatePages) (AllocateAddress, EfiReservedMemoryType, EFI_SIZE_TO_PAGES (0x00001000), &BaseAddress);
+    }
+  }
+
+  return EFI_SUCCESS;
+}
+
+/**
+  Enter a certain phase of the PCI enumeration process
+
+  @param[in] This  - The EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL instance
+  @param[in] Phase - The phase during enumeration
+
+  @retval EFI_SUCCESS            -  Succeed.
+  @retval EFI_INVALID_PARAMETER  -  Wrong phase parameter passed in.
+  @retval EFI_NOT_READY          -  Resources have not been submitted yet.
+**/
+EFI_STATUS
+EFIAPI
+NotifyPhase (
+  IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
+  IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE    Phase
+  )
+{
+  PCI_HOST_BRIDGE_INSTANCE  *HostBridgeInstance;
+  PCI_ROOT_BRIDGE_INSTANCE  *RootBridgeInstance;
+  PCI_RESOURCE_TYPE         Index;
+  LIST_ENTRY                *List;
+  EFI_PHYSICAL_ADDRESS      BaseAddress;
+  UINT64                    AddrLen;
+  UINTN                     BitsOfAlignment;
+  UINT64                    Alignment;
+  EFI_STATUS                Status;
+  EFI_STATUS                ReturnStatus;
+
+  HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This);
+  switch (Phase) {
+  case EfiPciHostBridgeBeginEnumeration:
+    if (HostBridgeInstance->CanRestarted) {
+      ///
+      /// Reset the Each Root Bridge
+      ///
+      List = HostBridgeInstance->Head.ForwardLink;
+      while (List != &HostBridgeInstance->Head) {
+        RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);
+        for (Index = TypeIo; Index < TypeMax; Index++) {
+          RootBridgeInstance->ResAllocNode[Index].Type    = Index;
+          RootBridgeInstance->ResAllocNode[Index].Base    = 0;
+          RootBridgeInstance->ResAllocNode[Index].Length  = 0;
+          RootBridgeInstance->ResAllocNode[Index].Status  = ResNone;
+        }
+
+        List = List->ForwardLink;
+      }
+
+      HostBridgeInstance->ResourceSubmited  = FALSE;
+      HostBridgeInstance->CanRestarted      = TRUE;
+    } else {
+      ///
+      /// Can not restart
+      ///
+      return EFI_NOT_READY;
+    }
+    break;
+
+  case EfiPciHostBridgeBeginBusAllocation:
+    ///
+    /// No specific action is required here, can perform any chipset specific programing
+    ///
+    HostBridgeInstance->CanRestarted = FALSE;
+    return EFI_SUCCESS;
+    break;
+
+  case EfiPciHostBridgeEndBusAllocation:
+    ///
+    /// No specific action is required here, can perform any chipset specific programing
+    ///
+    return EFI_SUCCESS;
+    break;
+
+  case EfiPciHostBridgeBeginResourceAllocation:
+    ///
+    /// No specific action is required here, can perform any chipset specific programing
+    ///
+    return EFI_SUCCESS;
+    break;
+
+  case EfiPciHostBridgeAllocateResources:
+    ReturnStatus = EFI_SUCCESS;
+    if (HostBridgeInstance->ResourceSubmited) {
+      ///
+      /// Take care of the resource dependencies between the root bridges
+      ///
+      List = HostBridgeInstance->Head.ForwardLink;
+      while (List != &HostBridgeInstance->Head) {
+        RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);
+
+        Status = HbCspAdjustMemoryMmioOverlap(RootBridgeInstance);        //  <<< AMI_OVERRIDE - EIP# 42483 - Support for Multi-Monitor	>>>
+
+        for (Index = TypeIo; Index < TypeBus; Index++) {
+          if (RootBridgeInstance->ResAllocNode[Index].Status != ResNone) {
+            AddrLen   = RootBridgeInstance->ResAllocNode[Index].Length;
+            Alignment = RootBridgeInstance->ResAllocNode[Index].Alignment;
+
+            ///
+            /// Get the number of '1' in Alignment.
+            ///
+            for (BitsOfAlignment = 0; Alignment != 0; BitsOfAlignment++) {
+              Alignment = RShiftU64 (Alignment, 1);
+            }
+
+            switch (Index) {
+            case TypeIo:
+              ///
+              /// It is impossible for this chipset to align 0xFFFF for IO16
+              /// So clear it
+              ///
+              if (BitsOfAlignment >= 16) {
+                BitsOfAlignment = 0;
+              }
+
+#ifndef AMI_ORIGINAL_FOR_MMIO_4G_TOLUD
+              // Support MaxAddressSearchTopDown for Gcd Io
+              BaseAddress = 0xFFFF;
+#endif // AMI_ORIGINAL_FOR_MMIO_4G_TOLUD
+
+              Status = gDS->AllocateIoSpace (
+#ifdef AMI_ORIGINAL_FOR_MMIO_4G_TOLUD
+                              EfiGcdAllocateAnySearchBottomUp,
+#else // AMI_ORIGINAL_FOR_MMIO_4G_TOLUD
+                              EfiGcdAllocateMaxAddressSearchTopDown,
+#endif // AMI_ORIGINAL_FOR_MMIO_4G_TOLUD
+                              EfiGcdIoTypeIo,
+                              BitsOfAlignment,
+                              AddrLen,
+                              &BaseAddress,
+                              mDriverImageHandle,
+                              NULL
+                              );
+              if (!EFI_ERROR (Status)) {
+                RootBridgeInstance->ResAllocNode[Index].Base    = (UINTN) BaseAddress;
+                RootBridgeInstance->ResAllocNode[Index].Status  = ResAllocated;
+              } else {
+                ///
+                /// Not able to allocate enough I/O memory - critical stop
+                ///
+                DEBUG ((EFI_D_ERROR, "Out of I/O space! AllocateIoSpace() returned %r\n", Status));
+                DEBUG ((EFI_D_ERROR, "Size requested: 0x%lX bytes\n", AddrLen));
+                ReturnStatus = Status;
+              }
+              break;
+
+            case TypeMem32:
+            case TypePMem32:
+              ///
+              /// It is impossible for this chipset to align 0xFFFFFFFF for Mem32
+              /// So clear it
+              ///
+              if (BitsOfAlignment >= 32) {
+                BitsOfAlignment = 0;
+              }
+
+#ifndef AMI_ORIGINAL_FOR_MMIO_4G_TOLUD
+              // Support MMIO 4G to Tolud for EfiGcdAllocateMaxAddressSearchTopDown
+			  BaseAddress = 0xFFFFFFFF;
+#endif // AMI_ORIGINAL_FOR_MMIO_4G_TOLUD
+            ///
+            /// Fall through to TypeMem64 / TypePMem64...
+            ///
+            case TypeMem64:
+            case TypePMem64:
+              Status = gDS->AllocateMemorySpace (
+#ifdef AMI_ORIGINAL_FOR_MMIO_4G_TOLUD
+                              EfiGcdAllocateAnySearchBottomUp,
+#else // AMI_ORIGINAL_FOR_MMIO_4G_TOLUD
+                              EfiGcdAllocateMaxAddressSearchTopDown,
+#endif // AMI_ORIGINAL_FOR_MMIO_4G_TOLUD
+                              EfiGcdMemoryTypeMemoryMappedIo,
+                              BitsOfAlignment,
+                              AddrLen,
+                              &BaseAddress,
+                              mDriverImageHandle,
+                              NULL
+                              );
+              if (!EFI_ERROR (Status)) {
+                ///
+                /// We were able to allocate the PCI memory
+                ///
+                RootBridgeInstance->ResAllocNode[Index].Base    = (UINTN) BaseAddress;
+                RootBridgeInstance->ResAllocNode[Index].Status  = ResAllocated;
+              } else {
+                ///
+                /// Not able to allocate enough PCI memory - critical stop
+                ///
+                DEBUG ((EFI_D_ERROR, "Out of PCI memory! AllocateMemorySpace() returned %r\n", Status));
+                DEBUG ((EFI_D_ERROR, "Size requested: 0x%lX bytes\n", AddrLen));
+                ReturnStatus = Status;
+              }
+              break;
+            default:
+              break;
+            }
+            ///
+            /// end switch
+            ///
+          }
+        }
+
+        List = List->ForwardLink;
+      }
+
+      return ReturnStatus;
+    } else {
+      return EFI_NOT_READY;
+    }
+    break;
+
+  case EfiPciHostBridgeSetResources:
+    break;
+
+  case EfiPciHostBridgeFreeResources:
+    ReturnStatus  = EFI_SUCCESS;
+
+    List          = HostBridgeInstance->Head.ForwardLink;
+    while (List != &HostBridgeInstance->Head) {
+      RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);
+      for (Index = TypeIo; Index < TypeBus; Index++) {
+        if (RootBridgeInstance->ResAllocNode[Index].Status == ResAllocated) {
+          AddrLen     = RootBridgeInstance->ResAllocNode[Index].Length;
+          BaseAddress = RootBridgeInstance->ResAllocNode[Index].Base;
+          switch (Index) {
+          case TypeIo:
+            Status = gDS->FreeIoSpace (BaseAddress, AddrLen);
+            break;
+
+          case TypeMem32:
+          case TypePMem32:
+          case TypeMem64:
+          case TypePMem64:
+            Status = gDS->FreeMemorySpace (BaseAddress, AddrLen);
+            break;
+
+          default:
+            Status = EFI_INVALID_PARAMETER;
+
+          }
+
+          if (EFI_ERROR (Status)) {
+            ReturnStatus = Status;
+          }
+          ///
+          /// end switch
+          ///
+          RootBridgeInstance->ResAllocNode[Index].Type    = Index;
+          RootBridgeInstance->ResAllocNode[Index].Base    = 0;
+          RootBridgeInstance->ResAllocNode[Index].Length  = 0;
+          RootBridgeInstance->ResAllocNode[Index].Status  = ResNone;
+        }
+      }
+
+      List = List->ForwardLink;
+    }
+
+    HostBridgeInstance->ResourceSubmited  = FALSE;
+    HostBridgeInstance->CanRestarted      = TRUE;
+    return ReturnStatus;
+    break;
+
+  case EfiPciHostBridgeEndResourceAllocation:
+    HostBridgeInstance->CanRestarted = FALSE;
+    break;
+
+  default:
+    return EFI_INVALID_PARAMETER;
+  }
+  ///
+  /// end switch
+  ///
+  return EFI_SUCCESS;
+}
+
+/**
+  Return the device handle of the next PCI root bridge that is associated with
+  this Host Bridge
+
+  @param[in] This              - The EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ PROTOCOL instance
+  @param[in] RootBridgeHandle  - Returns the device handle of the next PCI Root Bridge.
+                      On input, it holds the RootBridgeHandle returned by the most
+                      recent call to GetNextRootBridge().The handle for the first
+                      PCI Root Bridge is returned if RootBridgeHandle is NULL on input
+
+  @retval EFI_SUCCESS            -  Succeed.
+  @retval EFI_NOT_FOUND          -  Next PCI root bridge not found.
+  @retval EFI_INVALID_PARAMETER  -  Wrong parameter passed in.
+**/
+EFI_STATUS
+EFIAPI
+GetNextRootBridge (
+  IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
+  IN OUT EFI_HANDLE                                   *RootBridgeHandle
+  )
+{
+  BOOLEAN                   NoRootBridge;
+  LIST_ENTRY                *List;
+  PCI_HOST_BRIDGE_INSTANCE  *HostBridgeInstance;
+  PCI_ROOT_BRIDGE_INSTANCE  *RootBridgeInstance;
+
+  NoRootBridge        = TRUE;
+  HostBridgeInstance  = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This);
+  List                = HostBridgeInstance->Head.ForwardLink;
+
+  while (List != &HostBridgeInstance->Head) {
+    NoRootBridge        = FALSE;
+    RootBridgeInstance  = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);
+    if (*RootBridgeHandle == NULL) {
+      ///
+      /// Return the first Root Bridge Handle of the Host Bridge
+      ///
+      *RootBridgeHandle = RootBridgeInstance->Handle;
+      return EFI_SUCCESS;
+    } else {
+      if (*RootBridgeHandle == RootBridgeInstance->Handle) {
+        ///
+        /// Get next if have
+        ///
+        List = List->ForwardLink;
+        if (List != &HostBridgeInstance->Head) {
+          RootBridgeInstance  = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);
+          *RootBridgeHandle   = RootBridgeInstance->Handle;
+          return EFI_SUCCESS;
+        } else {
+          return EFI_NOT_FOUND;
+        }
+      }
+    }
+
+    List = List->ForwardLink;
+  }
+  ///
+  /// end while
+  ///
+  if (NoRootBridge) {
+    return EFI_NOT_FOUND;
+  } else {
+    return EFI_INVALID_PARAMETER;
+  }
+}
+
+/**
+  Returns the attributes of a PCI Root Bridge.
+
+  @param[in] This              - The EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ PROTOCOL instance.
+  @param[in] RootBridgeHandle  - The device handle of the PCI Root Bridge
+                      that the caller is interested in
+  @param[in] Attributes        - The pointer to attributes of the PCI Root Bridge
+
+  @retval EFI_SUCCESS            -  Succeed.
+  @retval EFI_INVALID_PARAMETER  -  Attributes parameter passed in is NULL or
+                            RootBridgeHandle is not an EFI_HANDLE
+                            that was returned on a previous call to
+                            GetNextRootBridge().
+**/
+EFI_STATUS
+EFIAPI
+GetAttributes (
+  IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
+  IN EFI_HANDLE                                       RootBridgeHandle,
+  OUT UINT64                                          *Attributes
+  )
+{
+  LIST_ENTRY                *List;
+  PCI_HOST_BRIDGE_INSTANCE  *HostBridgeInstance;
+  PCI_ROOT_BRIDGE_INSTANCE  *RootBridgeInstance;
+
+  if (Attributes == NULL) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  HostBridgeInstance  = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This);
+  List                = HostBridgeInstance->Head.ForwardLink;
+  while (List != &HostBridgeInstance->Head) {
+    RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);
+    if (RootBridgeHandle == RootBridgeInstance->Handle) {
+      *Attributes = RootBridgeInstance->RootBridgeAttrib;
+      return EFI_SUCCESS;
+    }
+
+    List = List->ForwardLink;
+  }
+  ///
+  /// RootBridgeHandle is not an EFI_HANDLE
+  /// that was returned on a previous call to GetNextRootBridge()
+  ///
+  return EFI_INVALID_PARAMETER;
+}
+
+/**
+  This is the request from the PCI enumerator to set up
+  the specified PCI Root Bridge for bus enumeration process.
+
+  @param[in] This              - The EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ PROTOCOL instance.
+  @param[in] RootBridgeHandle  - The PCI Root Bridge to be set up.
+  @param[in] Configuration     - Pointer to the pointer to the PCI bus resource descriptor.
+
+  @retval EFI_SUCCESS            -  Succeed.
+  @retval EFI_OUT_OF_RESOURCES   -  Not enough pool to be allocated.
+  @retval EFI_INVALID_PARAMETER  -  RootBridgeHandle is not a valid handle.
+**/
+EFI_STATUS
+EFIAPI
+StartBusEnumeration (
+  IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
+  IN EFI_HANDLE                                       RootBridgeHandle,
+  OUT VOID                                            **Configuration
+  )
+{
+  LIST_ENTRY                *List;
+  PCI_HOST_BRIDGE_INSTANCE  *HostBridgeInstance;
+  PCI_ROOT_BRIDGE_INSTANCE  *RootBridgeInstance;
+  VOID                      *Buffer;
+  UINT8                     *Temp;
+  EFI_STATUS                Status;
+  UINT64                    BusStart;
+  UINT64                    BusEnd;
+
+  HostBridgeInstance  = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This);
+  List                = HostBridgeInstance->Head.ForwardLink;
+
+  while (List != &HostBridgeInstance->Head) {
+    RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);
+    if (RootBridgeHandle == RootBridgeInstance->Handle) {
+      ///
+      /// Set up the Root Bridge for Bus Enumeration
+      ///
+      BusStart  = RootBridgeInstance->BusBase;
+      BusEnd    = RootBridgeInstance->BusLimit;
+
+      ///
+      /// Program the Hardware(if needed) if error return EFI_DEVICE_ERROR
+      ///
+      Status = (gBS->AllocatePool) (
+          EfiBootServicesData, sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR), &Buffer
+        );
+      if (EFI_ERROR (Status)) {
+        return EFI_OUT_OF_RESOURCES;
+      }
+
+      Temp  = (UINT8 *) Buffer;
+      ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Temp)->Desc                  = ACPI_ADDRESS_SPACE_DESCRIPTOR;
+      ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Temp)->Len                   = 0x2B;
+      ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Temp)->ResType               = ACPI_ADDRESS_SPACE_TYPE_BUS;
+      ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Temp)->GenFlag               = 0;
+      ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Temp)->SpecificFlag          = 0;
+      ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Temp)->AddrSpaceGranularity  = 0;
+      ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Temp)->AddrRangeMin          = BusStart;
+      ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Temp)->AddrRangeMax          = 0;
+      ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Temp)->AddrTranslationOffset = 0;
+      ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Temp)->AddrLen               = BusEnd - BusStart + 1;
+
+      Temp = Temp + sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR);
+
+      ((EFI_ACPI_END_TAG_DESCRIPTOR *) Temp)->Desc = ACPI_END_TAG_DESCRIPTOR;
+      ((EFI_ACPI_END_TAG_DESCRIPTOR *) Temp)->Checksum = 0x0;
+      *Configuration = Buffer;
+      return EFI_SUCCESS;
+    }
+
+    List = List->ForwardLink;
+  }
+
+  return EFI_INVALID_PARAMETER;
+}
+
+/**
+  This function programs the PCI Root Bridge hardware so that
+  it decodes the specified PCI bus range
+
+  @param[in] This              - The EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ PROTOCOL instance
+  @param[in] RootBridgeHandle  - The PCI Root Bridge whose bus range is to be programmed
+  @param[in] Configuration     - The pointer to the PCI bus resource descriptor
+
+  @retval EFI_SUCCESS            -  Succeed.
+  @retval EFI_INVALID_PARAMETER  -  Wrong parameters passed in.
+**/
+EFI_STATUS
+EFIAPI
+SetBusNumbers (
+  IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
+  IN EFI_HANDLE                                       RootBridgeHandle,
+  IN VOID                                             *Configuration
+  )
+{
+  LIST_ENTRY                *List;
+  PCI_HOST_BRIDGE_INSTANCE  *HostBridgeInstance;
+  PCI_ROOT_BRIDGE_INSTANCE  *RootBridgeInstance;
+  UINT8                     *Ptr;
+  UINTN                     BusStart;
+  UINTN                     BusEnd;
+  UINTN                     BusLen;
+
+  if (Configuration == NULL) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  Ptr = Configuration;
+
+  ///
+  /// Check the Configuration is valid
+  ///
+  if (*Ptr != ACPI_ADDRESS_SPACE_DESCRIPTOR) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  if (((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Ptr)->ResType != ACPI_ADDRESS_SPACE_TYPE_BUS) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  Ptr += sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR);
+  if (*Ptr != ACPI_END_TAG_DESCRIPTOR) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  HostBridgeInstance  = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This);
+  List                = HostBridgeInstance->Head.ForwardLink;
+  Ptr                 = Configuration;
+  while (List != &HostBridgeInstance->Head) {
+    RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);
+    if (RootBridgeHandle == RootBridgeInstance->Handle) {
+      BusStart  = (UINTN) ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Ptr)->AddrRangeMin;
+      BusLen    = (UINTN) ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Ptr)->AddrLen;
+      BusEnd    = BusStart + BusLen - 1;
+      if (BusStart > BusEnd) {
+        return EFI_INVALID_PARAMETER;
+      }
+
+      if ((BusStart < RootBridgeInstance->BusBase) || (BusEnd > RootBridgeInstance->BusLimit)) {
+        return EFI_INVALID_PARAMETER;
+      }
+      ///
+      /// Update the Bus Range
+      ///
+      RootBridgeInstance->ResAllocNode[TypeBus].Base    = BusStart;
+      RootBridgeInstance->ResAllocNode[TypeBus].Length  = BusLen;
+      RootBridgeInstance->ResAllocNode[TypeBus].Status  = ResAllocated;
+
+      ///
+      /// Program the Root Bridge Hardware
+      ///
+      return EFI_SUCCESS;
+    }
+
+    List = List->ForwardLink;
+  }
+
+  return EFI_INVALID_PARAMETER;
+}
+
+/**
+  Submits the I/O and memory resource requirements for the specified PCI Root Bridge
+
+  @param[in] This              - The EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ PROTOCOL instance
+  @param[in] RootBridgeHandle  - The PCI Root Bridge whose I/O and memory resource requirements
+                      are being submitted
+  @param[in] Configuration     - The pointer to the PCI I/O and PCI memory resource descriptor
+
+  @retval EFI_SUCCESS            -  Succeed.
+  @retval EFI_INVALID_PARAMETER  -  Wrong parameters passed in.
+**/
+EFI_STATUS
+EFIAPI
+SubmitResources (
+  IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
+  IN EFI_HANDLE                                       RootBridgeHandle,
+  IN VOID                                             *Configuration
+  )
+{
+  LIST_ENTRY                        *List;
+  PCI_HOST_BRIDGE_INSTANCE          *HostBridgeInstance;
+  PCI_ROOT_BRIDGE_INSTANCE          *RootBridgeInstance;
+  UINT8                             *Temp;
+  EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *ptr;
+  UINT64                            AddrLen;
+  UINT64                            Alignment;
+
+  ///
+  /// Check the input parameter: Configuration
+  ///
+  if (Configuration == NULL) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  HostBridgeInstance  = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This);
+  List                = HostBridgeInstance->Head.ForwardLink;
+  Temp                = (UINT8 *) Configuration;
+  while (*Temp == ACPI_ADDRESS_SPACE_DESCRIPTOR) {
+    Temp += sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR);
+  }
+
+  if (*Temp != ACPI_END_TAG_DESCRIPTOR) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  Temp = (UINT8 *) Configuration;
+  while (List != &HostBridgeInstance->Head) {
+    RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);
+    if (RootBridgeHandle == RootBridgeInstance->Handle) {
+      while (*Temp == ACPI_ADDRESS_SPACE_DESCRIPTOR) {
+        ptr = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Temp;
+
+        ///
+        /// Check address range alignment
+        ///
+        if (ptr->AddrRangeMax >= (UINT64) 0xffffffff ||
+            ptr->AddrRangeMax != (Power2MaxMemory (ptr->AddrRangeMax + 1) - 1)
+            ) {
+          return EFI_INVALID_PARAMETER;
+        }
+
+        switch (ptr->ResType) {
+        case ACPI_ADDRESS_SPACE_TYPE_MEM:
+          ///
+          /// check the memory resource request is supported by PCI root bridge
+          ///
+          /// Hard code EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM  0 to support prefetchable memory allocation
+          ///
+          if (RootBridgeInstance->RootBridgeAttrib == 0 && ptr->SpecificFlag == 0x06) {
+            return EFI_INVALID_PARAMETER;
+          }
+
+          AddrLen   = (UINT64) ptr->AddrLen;
+          Alignment = (UINT64) ptr->AddrRangeMax;
+          if (ptr->AddrSpaceGranularity == 32) {
+            if ((ptr->SpecificFlag & 0x06) == 0x06) {
+              ///
+              /// Apply from GCD
+              ///
+              RootBridgeInstance->ResAllocNode[TypePMem32].Length     = AddrLen;
+              RootBridgeInstance->ResAllocNode[TypePMem32].Alignment  = Alignment;
+              RootBridgeInstance->ResAllocNode[TypePMem32].Status     = ResRequested;
+              HostBridgeInstance->ResourceSubmited                    = TRUE;
+
+            } else {
+              RootBridgeInstance->ResAllocNode[TypeMem32].Length    = AddrLen;
+              RootBridgeInstance->ResAllocNode[TypeMem32].Alignment = Alignment;
+              RootBridgeInstance->ResAllocNode[TypeMem32].Status    = ResRequested;
+              HostBridgeInstance->ResourceSubmited                  = TRUE;
+            }
+          }
+
+          if (ptr->AddrSpaceGranularity == 64) {
+            if ((ptr->SpecificFlag & 0x06) == 0x06) {
+              RootBridgeInstance->ResAllocNode[TypePMem64].Length     = AddrLen;
+              RootBridgeInstance->ResAllocNode[TypePMem64].Alignment  = Alignment;
+              RootBridgeInstance->ResAllocNode[TypePMem64].Status     = ResSubmitted;
+              HostBridgeInstance->ResourceSubmited                    = TRUE;
+
+            } else {
+              RootBridgeInstance->ResAllocNode[TypeMem64].Length    = AddrLen;
+              RootBridgeInstance->ResAllocNode[TypeMem64].Alignment = Alignment;
+              RootBridgeInstance->ResAllocNode[TypeMem64].Status    = ResSubmitted;
+              HostBridgeInstance->ResourceSubmited                  = TRUE;
+            }
+          }
+          break;
+
+        case ACPI_ADDRESS_SPACE_TYPE_IO:
+          AddrLen   = (UINT64) ptr->AddrLen;
+          Alignment = (UINT64) ptr->AddrRangeMax;
+          RootBridgeInstance->ResAllocNode[TypeIo].Length     = AddrLen;
+          RootBridgeInstance->ResAllocNode[TypeIo].Alignment  = Alignment;
+          RootBridgeInstance->ResAllocNode[TypeIo].Status     = ResRequested;
+          HostBridgeInstance->ResourceSubmited                = TRUE;
+          break;
+
+        default:
+          break;
+        }
+
+        Temp += sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR);
+      }
+
+      return EFI_SUCCESS;
+    }
+
+    List = List->ForwardLink;
+  }
+
+  return EFI_INVALID_PARAMETER;
+}
+
+/**
+  This function returns the proposed resource settings for the specified
+  PCI Root Bridge
+
+  @param[in] This              - The EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ PROTOCOL instance
+  @param[in] RootBridgeHandle  - The PCI Root Bridge handle
+  @param[in] Configuration     - The pointer to the pointer to the PCI I/O
+                      and memory resource descriptor
+
+  @retval EFI_SUCCESS            -  Succeed.
+  @retval EFI_OUT_OF_RESOURCES   -  Not enough pool to be allocated.
+  @retval EFI_INVALID_PARAMETER  -  RootBridgeHandle is not a valid handle.
+**/
+EFI_STATUS
+EFIAPI
+GetProposedResources (
+  IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
+  IN EFI_HANDLE                                       RootBridgeHandle,
+  OUT VOID                                            **Configuration
+  )
+{
+  LIST_ENTRY                        *List;
+  PCI_HOST_BRIDGE_INSTANCE          *HostBridgeInstance;
+  PCI_ROOT_BRIDGE_INSTANCE          *RootBridgeInstance;
+  UINTN                             Index;
+  UINTN                             Number;
+  VOID                              *Buffer;
+  UINT8                             *Temp;
+  EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *ptr;
+  EFI_STATUS                        Status;
+  UINT64                            ResStatus;
+
+  Buffer  = NULL;
+  Number  = 0;
+
+  ///
+  /// Get the Host Bridge Instance from the resource allocation protocol
+  ///
+  HostBridgeInstance  = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This);
+  List                = HostBridgeInstance->Head.ForwardLink;
+
+  ///
+  /// Enumerate the root bridges in this host bridge
+  ///
+  while (List != &HostBridgeInstance->Head) {
+    RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);
+    if (RootBridgeHandle == RootBridgeInstance->Handle) {
+      for (Index = 0; Index < TypeBus; Index++) {
+        if (RootBridgeInstance->ResAllocNode[Index].Status != ResNone) {
+          Number++;
+        }
+      }
+
+      if (Number > 0) {
+        Status = (gBS->AllocatePool)
+          (
+            EfiBootServicesData, Number * sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) +
+            sizeof (EFI_ACPI_END_TAG_DESCRIPTOR), &Buffer
+          );
+        if (EFI_ERROR (Status)) {
+          return EFI_OUT_OF_RESOURCES;
+        }
+
+        ZeroMem (Buffer, sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) * Number + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR));
+
+        Temp = Buffer;
+        for (Index = 0; Index < TypeBus; Index++) {
+          if (RootBridgeInstance->ResAllocNode[Index].Status != ResNone) {
+            ptr       = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Temp;
+            ResStatus = RootBridgeInstance->ResAllocNode[Index].Status;
+            switch (Index) {
+            case TypeIo:
+              ///
+              /// Io
+              ///
+              ptr->Desc                   = 0x8A;
+              ptr->Len                    = 0x2B;
+              ptr->ResType                = 1;
+              ptr->GenFlag                = 0;
+              ptr->SpecificFlag           = 0;
+              ptr->AddrRangeMin           = RootBridgeInstance->ResAllocNode[Index].Base;
+              ptr->AddrRangeMax           = 0;
+              ptr->AddrTranslationOffset  = (ResStatus == ResAllocated) ? EFI_RESOURCE_SATISFIED : EFI_RESOURCE_LESS;
+              ptr->AddrLen                = RootBridgeInstance->ResAllocNode[Index].Length;
+              break;
+
+            case TypeMem32:
+              ///
+              /// Memory 32
+              ///
+              ptr->Desc                   = 0x8A;
+              ptr->Len                    = 0x2B;
+              ptr->ResType                = 0;
+              ptr->GenFlag                = 0;
+              ptr->SpecificFlag           = 0;
+              ptr->AddrSpaceGranularity   = 32;
+              ptr->AddrRangeMin           = RootBridgeInstance->ResAllocNode[Index].Base;
+              ptr->AddrRangeMax           = 0;
+              ptr->AddrTranslationOffset  = (ResStatus == ResAllocated) ? EFI_RESOURCE_SATISFIED : EFI_RESOURCE_LESS;
+              ptr->AddrLen                = RootBridgeInstance->ResAllocNode[Index].Length;
+              break;
+
+            case TypePMem32:
+              ///
+              /// Prefetch memory 32
+              ///
+              ptr->Desc                   = 0x8A;
+              ptr->Len                    = 0x2B;
+              ptr->ResType                = 0;
+              ptr->GenFlag                = 0;
+              ptr->SpecificFlag           = 6;
+              ptr->AddrSpaceGranularity   = 32;
+              ptr->AddrRangeMin           = 0;
+              ptr->AddrRangeMax           = 0;
+              ptr->AddrTranslationOffset  = (ResStatus == ResAllocated) ? EFI_RESOURCE_SATISFIED : EFI_RESOURCE_LESS;
+              ptr->AddrLen                = RootBridgeInstance->ResAllocNode[Index].Length;
+              break;
+
+            case TypeMem64:
+              ///
+              /// Memory 64
+              ///
+              ptr->Desc                   = 0x8A;
+              ptr->Len                    = 0x2B;
+              ptr->ResType                = 0;
+              ptr->GenFlag                = 0;
+              ptr->SpecificFlag           = 0;
+              ptr->AddrSpaceGranularity   = 64;
+              ptr->AddrRangeMin           = 0;
+              ptr->AddrRangeMax           = 0;
+              ptr->AddrTranslationOffset  = (ResStatus == ResAllocated) ? EFI_RESOURCE_SATISFIED : EFI_RESOURCE_LESS;
+              ptr->AddrLen                = RootBridgeInstance->ResAllocNode[Index].Length;
+              break;
+
+            case TypePMem64:
+              ///
+              /// Prefetch memory 64
+              ///
+              ptr->Desc                   = 0x8A;
+              ptr->Len                    = 0x2B;
+              ptr->ResType                = 0;
+              ptr->GenFlag                = 0;
+              ptr->SpecificFlag           = 6;
+              ptr->AddrSpaceGranularity   = 64;
+              ptr->AddrRangeMin           = 0;
+              ptr->AddrRangeMax           = 0;
+              ptr->AddrTranslationOffset  = (ResStatus == ResAllocated) ? EFI_RESOURCE_SATISFIED : EFI_RESOURCE_LESS;
+              ptr->AddrLen                = RootBridgeInstance->ResAllocNode[Index].Length;
+              break;
+            }
+
+            Temp += sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR);
+          }
+        }
+
+        ((EFI_ACPI_END_TAG_DESCRIPTOR *) Temp)->Desc      = 0x79;
+        ((EFI_ACPI_END_TAG_DESCRIPTOR *) Temp)->Checksum  = 0x0;
+        *Configuration = Buffer;
+      }
+
+      return EFI_SUCCESS;
+    }
+
+    List = List->ForwardLink;
+  }
+
+  return EFI_INVALID_PARAMETER;
+}
+
+/**
+  This function is called for all the PCI controllers that the PCI
+  bus driver finds. Can be used to Preprogram the controller.
+
+  @param[in] This              - The EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ PROTOCOL instance
+  @param[in] RootBridgeHandle  - The PCI Root Bridge handle
+  @param[in] PciAddress        - Address of the controller on the PCI bus
+  @param[in] Phase             - The Phase during resource allocation
+
+  @retval EFI_SUCCESS            -  Succeed.
+  @retval EFI_INVALID_PARAMETER  -  RootBridgeHandle is not a valid handle.
+**/
+EFI_STATUS
+EFIAPI
+PreprocessController (
+  IN  EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL          *This,
+  IN  EFI_HANDLE                                                RootBridgeHandle,
+  IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS               PciAddress,
+  IN  EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE              Phase
+  )
+{
+  PCI_HOST_BRIDGE_INSTANCE  *HostBridgeInstance;
+  PCI_ROOT_BRIDGE_INSTANCE  *RootBridgeInstance;
+  LIST_ENTRY                *List;
+
+  HostBridgeInstance  = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This);
+  List                = HostBridgeInstance->Head.ForwardLink;
+
+  ///
+  /// Enumerate the root bridges in this host bridge
+  ///
+  while (List != &HostBridgeInstance->Head) {
+    RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);
+    if (RootBridgeHandle == RootBridgeInstance->Handle) {
+      return EFI_SUCCESS;
+    }
+
+    List = List->ForwardLink;
+  }
+
+  return EFI_INVALID_PARAMETER;
+}
+
+/**
+  Calculate max memory of power 2
+
+  @param[in] MemoryLength  -  Input memory length.
+
+  @retval Returned Maximum length.
+**/
+UINT64
+Power2MaxMemory (
+  IN UINT64                     MemoryLength
+  )
+{
+  UINT64  Result;
+
+  if (RShiftU64 (MemoryLength, 32)) {
+    Result = LShiftU64 ((UINT64) GetPowerOfTwo64 (RShiftU64 (MemoryLength, 32)), 32);
+  } else {
+    Result = (UINT64) GetPowerOfTwo64 (MemoryLength);
+  }
+
+  return Result;
+}
diff --git a/ReferenceCode/Chipset/SystemAgent/PciHostBridge/Dxe/PciHostBridge.cif b/ReferenceCode/Chipset/SystemAgent/PciHostBridge/Dxe/PciHostBridge.cif
new file mode 100644
index 0000000..55f38b5
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/PciHostBridge/Dxe/PciHostBridge.cif
@@ -0,0 +1,15 @@
+<component>
+	name = "PciHostBridge"
+	category = ModulePart
+	LocalRoot = "ReferenceCode\Chipset\SystemAgent\PciHostBridge\Dxe\"
+	RefName = "PciHostBridge"
+[files]
+"PciHostBridge.sdl"	
+"PciHostBridge.mak"	
+"PciHostBridge.c"	
+"PciHostBridge.h"	
+"PciHostBridge.dxs"	
+"PciRootBridgeIo.c"	
+"PciRootBridge.h"
+"PciHostBridge.inf"	
+<endComponent>
diff --git a/ReferenceCode/Chipset/SystemAgent/PciHostBridge/Dxe/PciHostBridge.dxs b/ReferenceCode/Chipset/SystemAgent/PciHostBridge/Dxe/PciHostBridge.dxs
new file mode 100644
index 0000000..87cf509
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/PciHostBridge/Dxe/PciHostBridge.dxs
@@ -0,0 +1,43 @@
+/** @file
+  Dependency expression source file.
+
+@copyright
+  Copyright (c)  1999 - 2012 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains a 'Sample Driver' and is licensed as such
+  under the terms of your license agreement with Intel or your
+  vendor.  This file may be modified by the user, subject to
+  the additional terms of the license agreement
+
+**/
+
+
+//
+// Common for R8 and R9 codebase
+//
+#include "AutoGen.h"
+#include "DxeDepex.h"
+
+//
+// BUILD_WITH_GLUELIB and BUILD_WITH_EDKII_GLUE_LIB are both "defined" in R8 codebase;
+// BUILD_WITH_EDKII_GLUE_LIB is defined in Edk-Dev-Snapshot-20070228 and later version
+// BUILD_WITH_GLUELIB and BUILD_WITH_EDKII_GLUE_LIB are "not defined" in R9 codebase.
+//
+#if defined (BUILD_WITH_GLUELIB) || defined (BUILD_WITH_EDKII_GLUE_LIB)
+#include "EfiDepex.h"
+
+#include EFI_PROTOCOL_DEFINITION (CpuIo)
+#include EFI_ARCH_PROTOCOL_DEFINITION (Metronome)
+#endif 
+
+DEPENDENCY_START
+  EFI_CPU_IO_PROTOCOL_GUID AND 
+  EFI_METRONOME_ARCH_PROTOCOL_GUID 
+DEPENDENCY_END
diff --git a/ReferenceCode/Chipset/SystemAgent/PciHostBridge/Dxe/PciHostBridge.h b/ReferenceCode/Chipset/SystemAgent/PciHostBridge/Dxe/PciHostBridge.h
new file mode 100644
index 0000000..d94ff48
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/PciHostBridge/Dxe/PciHostBridge.h
@@ -0,0 +1,234 @@
+/** @file
+  The Header file of the Pci Host Bridge Driver
+
+@copyright
+  Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement
+
+**/
+#ifndef _PCI_HOST_BRIDGE_H_
+#define _PCI_HOST_BRIDGE_H_
+
+#include "EdkIIGlueDxe.h"
+#include "CpuRegs.h"
+#include "CpuPlatformLib.h"
+
+#include EFI_PROTOCOL_DEFINITION (PciHostBridgeResourceAllocation)
+
+///
+/// Hard code the host bridge number in the platform.
+/// In this chipset, there is only one host bridge.
+///
+#define HOST_BRIDGE_NUMBER        1
+
+#define PCI_HOST_BRIDGE_SIGNATURE EFI_SIGNATURE_32 ('e', 'h', 's', 't')
+typedef struct {
+  UINTN                                             Signature;
+  EFI_HANDLE                                        HostBridgeHandle;
+  UINTN                                             RootBridgeNumber;
+  LIST_ENTRY                                        Head;
+  BOOLEAN                                           ResourceSubmited;
+  BOOLEAN                                           CanRestarted;
+  EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL  ResAlloc;
+} PCI_HOST_BRIDGE_INSTANCE;
+
+#define INSTANCE_FROM_RESOURCE_ALLOCATION_THIS(a) CR (a, PCI_HOST_BRIDGE_INSTANCE, ResAlloc, PCI_HOST_BRIDGE_SIGNATURE)
+
+///
+///  HostBridge Resource Allocation interface
+///
+/**
+  Enter a certain phase of the PCI enumeration process
+
+  @param[in] This  - The EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL instance
+  @param[in] Phase - The phase during enumeration
+
+  @retval EFI_SUCCESS            -  Succeed.
+  @retval EFI_INVALID_PARAMETER  -  Wrong phase parameter passed in.
+  @retval EFI_NOT_READY          -  Resources have not been submitted yet.
+**/
+EFI_STATUS
+EFIAPI
+NotifyPhase (
+  IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
+  IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE    Phase
+  )
+;
+
+/**
+  Return the device handle of the next PCI root bridge that is associated with
+  this Host Bridge
+
+  @param[in] This              - The EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ PROTOCOL instance
+  @param[in] RootBridgeHandle  - Returns the device handle of the next PCI Root Bridge.
+                                 On input, it holds the RootBridgeHandle returned by the most
+                                 recent call to GetNextRootBridge().The handle for the first
+                                 PCI Root Bridge is returned if RootBridgeHandle is NULL on input
+
+  @retval EFI_SUCCESS            -  Succeed.
+  @retval EFI_NOT_FOUND          -  Next PCI root bridge not found.
+  @retval EFI_INVALID_PARAMETER  -  Wrong parameter passed in.
+**/
+EFI_STATUS
+EFIAPI
+GetNextRootBridge (
+  IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
+  IN OUT EFI_HANDLE                                   *RootBridgeHandle
+  )
+;
+
+/**
+  Returns the attributes of a PCI Root Bridge.
+
+  @param[in] This              - The EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ PROTOCOL instance.
+  @param[in] RootBridgeHandle  - The device handle of the PCI Root Bridge
+                                 that the caller is interested in
+  @param[in] Attributes        - The pointer to attributes of the PCI Root Bridge
+
+  @retval EFI_SUCCESS            -  Succeed.
+  @retval EFI_INVALID_PARAMETER  -  Attributes parameter passed in is NULL or
+                                    RootBridgeHandle is not an EFI_HANDLE
+                                    that was returned on a previous call to
+                                    GetNextRootBridge().
+**/
+EFI_STATUS
+EFIAPI
+GetAttributes (
+  IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
+  IN EFI_HANDLE                                       RootBridgeHandle,
+  OUT UINT64                                          *Attributes
+  )
+;
+
+/**
+  This is the request from the PCI enumerator to set up
+  the specified PCI Root Bridge for bus enumeration process.
+
+  @param[in] This              - The EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ PROTOCOL instance.
+  @param[in] RootBridgeHandle  - The PCI Root Bridge to be set up.
+  @param[in] Configuration     - Pointer to the pointer to the PCI bus resource descriptor.
+
+  @retval EFI_SUCCESS            -  Succeed.
+  @retval EFI_OUT_OF_RESOURCES   -  Not enough pool to be allocated.
+  @retval EFI_INVALID_PARAMETER  -  RootBridgeHandle is not a valid handle.
+**/
+EFI_STATUS
+EFIAPI
+StartBusEnumeration (
+  IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
+  IN EFI_HANDLE                                       RootBridgeHandle,
+  OUT VOID                                            **Configuration
+  )
+;
+
+/**
+  This function programs the PCI Root Bridge hardware so that
+  it decodes the specified PCI bus range
+
+  @param[in] This              - The EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ PROTOCOL instance
+  @param[in] RootBridgeHandle  - The PCI Root Bridge whose bus range is to be programmed
+  @param[in] Configuration     - The pointer to the PCI bus resource descriptor
+
+  @retval EFI_SUCCESS            -  Succeed.
+  @retval EFI_INVALID_PARAMETER  -  Wrong parameters passed in.
+**/
+EFI_STATUS
+EFIAPI
+SetBusNumbers (
+  IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
+  IN EFI_HANDLE                                       RootBridgeHandle,
+  IN VOID                                             *Configuration
+  )
+;
+
+/**
+  Submits the I/O and memory resource requirements for the specified PCI Root Bridge
+
+  @param[in] This              - The EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ PROTOCOL instance
+  @param[in] RootBridgeHandle  - The PCI Root Bridge whose I/O and memory resource requirements
+                      are being submitted
+  @param[in] Configuration     - The pointer to the PCI I/O and PCI memory resource descriptor
+
+  @retval EFI_SUCCESS            -  Succeed.
+  @retval EFI_INVALID_PARAMETER  -  Wrong parameters passed in.
+**/
+EFI_STATUS
+EFIAPI
+SubmitResources (
+  IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
+  IN EFI_HANDLE                                       RootBridgeHandle,
+  IN VOID                                             *Configuration
+  )
+;
+
+/**
+  This function returns the proposed resource settings for the specified
+  PCI Root Bridge
+
+  @param[in] This              - The EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ PROTOCOL instance
+  @param[in] RootBridgeHandle  - The PCI Root Bridge handle
+  @param[in] Configuration     - The pointer to the pointer to the PCI I/O
+                      and memory resource descriptor
+
+  @retval EFI_SUCCESS            -  Succeed.
+  @retval EFI_OUT_OF_RESOURCES   -  Not enough pool to be allocated.
+  @retval EFI_INVALID_PARAMETER  -  RootBridgeHandle is not a valid handle.
+**/
+EFI_STATUS
+EFIAPI
+GetProposedResources (
+  IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
+  IN EFI_HANDLE                                       RootBridgeHandle,
+  OUT VOID                                            **Configuration
+  )
+;
+
+/**
+  This function is called for all the PCI controllers that the PCI
+  bus driver finds. Can be used to Preprogram the controller.
+
+  @param[in] This              - The EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ PROTOCOL instance
+  @param[in] RootBridgeHandle  - The PCI Root Bridge handle
+  @param[in] PciAddress        - Address of the controller on the PCI bus
+  @param[in] Phase             - The Phase during resource allocation
+
+  @retval EFI_SUCCESS            -  Succeed.
+  @retval EFI_INVALID_PARAMETER  -  RootBridgeHandle is not a valid handle.
+**/
+EFI_STATUS
+EFIAPI
+PreprocessController (
+  IN  struct _EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL  *This,
+  IN  EFI_HANDLE                                                RootBridgeHandle,
+  IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS               PciAddress,
+  IN  EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE              Phase
+  )
+;
+
+/**
+  Calculate max memory of power 2
+
+  @param[in] MemoryLength  -  Input memory length.
+
+  @retval Returned Maximum length.
+**/
+UINT64
+Power2MaxMemory (
+  IN UINT64                     MemoryLength
+  )
+;
+
+#endif
diff --git a/ReferenceCode/Chipset/SystemAgent/PciHostBridge/Dxe/PciHostBridge.inf b/ReferenceCode/Chipset/SystemAgent/PciHostBridge/Dxe/PciHostBridge.inf
new file mode 100644
index 0000000..0c4561c
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/PciHostBridge/Dxe/PciHostBridge.inf
@@ -0,0 +1,86 @@
+## @file
+#  Component description file for PciHostBridge module
+#    {8D6756B9-E55E-4d6a-A3A5-5E4D72DDF772}
+#    0x8d6756b9, 0xee5e, 0x4d6a, 0xa3, 0xa5, 0x5e, 0x4d, 0x72, 0xdd, 0xf7, 0x72
+#
+#@copyright
+#  Copyright (c)  1999 - 2012 Intel Corporation. All rights reserved
+#  This software and associated documentation (if any) is furnished
+#  under a license and may only be used or copied in accordance
+#  with the terms of the license. Except as permitted by such
+#  license, no part of this software or documentation may be
+#  reproduced, stored in a retrieval system, or transmitted in any
+#  form or by any means without the express written consent of
+#  Intel Corporation.
+#
+#  This file contains a 'Sample Driver' and is licensed as such
+#  under the terms of your license agreement with Intel or your
+#  vendor.  This file may be modified by the user, subject to
+#  the additional terms of the license agreement
+#
+
+[defines]
+BASE_NAME            = PciHostBridge
+FILE_GUID            = 8D6756B9-E55E-4d6a-A3A5-5E4D72DDF772
+COMPONENT_TYPE       = BS_DRIVER
+
+[sources.common]
+  PciHostBridge.h
+  PciHostBridge.c
+  PciRootBridge.h
+  PciRootBridgeIo.c
+#
+# Edk II Glue Driver Entry Point
+#
+  EdkIIGlueDxeDriverEntryPoint.c
+
+[includes.common]
+  $(EDK_SOURCE)/Foundation/Efi
+  $(EDK_SOURCE)/Foundation
+  $(EDK_SOURCE)/Foundation/Framework
+  $(EDK_SOURCE)/Foundation/Include
+  $(EDK_SOURCE)/Foundation/Efi/Include
+  $(EDK_SOURCE)/Foundation/Framework/Include
+  $(EDK_SOURCE)/Foundation/Include/IndustryStandard
+  $(EFI_SOURCE)
+  $(EDK_SOURCE)/Foundation/Core/Dxe
+  $(EDK_SOURCE)/Foundation/Library/Dxe/Include
+  $(EFI_SOURCE)/$(PROJECT_SA_ROOT)
+  $(EFI_SOURCE)/$(PROJECT_SA_ROOT)/Include
+  $(EDK_SOURCE)/Foundation/Library/EdkIIGlueLib/Include
+  $(EDK_SOURCE)/Foundation/Cpu/Pentium/Include
+  $(EFI_SOURCE)/$(PROJECT_CPU_ROOT)
+  $(EFI_SOURCE)/$(PROJECT_CPU_ROOT)/Include
+  $(EFI_SOURCE)/$(PROJECT_CPU_ROOT)/Include/Library
+
+[libraries.common]
+  ArchProtocolLib
+  EdkFrameworkProtocolLib
+  EfiScriptLib
+  EdkIIGlueBaseLib
+  EdkIIGlueBaseIoLibIntrinsic
+  EdkIIGlueDxeDebugLibReportStatusCode
+  EdkIIGlueDxeReportStatusCodeLib
+  EdkIIGlueUefiBootServicesTableLib
+  EdkIIGlueUefiRuntimeServicesTableLib
+  EdkIIGlueDxeServicesTableLib
+  EdkIIGlueUefiLib
+  CPUIA32LIB
+  EdkIIGlueDxeMemoryAllocationLib
+  EdkProtocolLib
+  CpuPlatformLib
+
+[nmake.common]
+  IMAGE_ENTRY_POINT = _ModuleEntryPoint
+  DPX_SOURCE        = PciHostBridge.dxs
+  C_FLAGS = $(C_FLAGS) -D __EDKII_GLUE_MODULE_ENTRY_POINT__=PciHostBridgeEntryPoint \
+                         -D __EDKII_GLUE_BASE_LIB__ \
+                         -D __EDKII_GLUE_BASE_IO_LIB_INTRINSIC__ \
+                         -D __EDKII_GLUE_DXE_REPORT_STATUS_CODE_LIB__ \
+                         -D __EDKII_GLUE_DXE_SERVICES_TABLE_LIB__ \
+                         -D __EDKII_GLUE_DXE_DEBUG_LIB_REPORT_STATUS_CODE__ \
+                         -D __EDKII_GLUE_UEFI_BOOT_SERVICES_TABLE_LIB__ \
+                         -D __EDKII_GLUE_UEFI_RUNTIME_SERVICES_TABLE_LIB__ \
+                         -D __EDKII_GLUE_UEFI_LIB__\
+                         -D __EDKII_GLUE_DXE_MEMORY_ALLOCATION_LIB__ \
+
diff --git a/ReferenceCode/Chipset/SystemAgent/PciHostBridge/Dxe/PciHostBridge.mak b/ReferenceCode/Chipset/SystemAgent/PciHostBridge/Dxe/PciHostBridge.mak
new file mode 100644
index 0000000..fe3614c
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/PciHostBridge/Dxe/PciHostBridge.mak
@@ -0,0 +1,67 @@
+#---------------------------------------------------------------------------
+#		Create PCI Host Bridge DXE Component
+#---------------------------------------------------------------------------
+EDK : PciHostBridge
+
+PciHostBridge : $(BUILD_DIR)\PciHostBridge.mak PciHostBridgeBin
+
+$(BUILD_DIR)\PciHostBridge.mak : $(PciHostBridge_DIR)\PciHostBridge.cif $(BUILD_RULES)
+	$(CIF2MAK) $(PciHostBridge_DIR)\PciHostBridge.cif $(CIF2MAK_DEFAULTS)
+
+PciHostBridge_INCLUDES=\
+  $(EdkIIGlueLib_INCLUDES)\
+  $(EDK_INCLUDES)\
+  $(PROJECT_CPU_INCLUDES)\
+  $(INTEL_MCH_INCLUDES)\
+  $(INTEL_PCH_INCLUDES)\
+  /IInclude
+
+PciHostBridge_DEFINES =$(MY_DEFINES)\
+  /D "__EDKII_GLUE_MODULE_ENTRY_POINT__=PciHostBridgeEntryPoint" \
+  /D __EDKII_GLUE_BASE_LIB__ \
+  /D __EDKII_GLUE_BASE_IO_LIB_INTRINSIC__ \
+  /D __EDKII_GLUE_DXE_REPORT_STATUS_CODE_LIB__ \
+  /D __EDKII_GLUE_DXE_SERVICES_TABLE_LIB__ \
+  /D __EDKII_GLUE_DXE_DEBUG_LIB_REPORT_STATUS_CODE__ \
+  /D __EDKII_GLUE_UEFI_LIB__\
+  /D __EDKII_GLUE_DXE_MEMORY_ALLOCATION_LIB__ \
+  /D __EDKII_GLUE_UEFI_BOOT_SERVICES_TABLE_LIB__ \
+  /D __EDKII_GLUE_UEFI_RUNTIME_SERVICES_TABLE_LIB__ \
+
+PciHostBridge_LIB_LINKS =\
+    $(ArchProtocolLib)\
+    $(EFISCRIPTLIB)\
+    $(EDKFRAMEWORKPROTOCOLLIB)\
+    $(EdkIIGlueBaseIoLibIntrinsic_LIB)\
+    $(EdkIIGlueBaseLib_LIB)\
+!IF "$(x64_BUILD)"=="1"
+    $(EdkIIGlueBaseLibX64_LIB)\
+!ELSE
+    $(EdkIIGlueBaseLibIA32_LIB)\
+!ENDIF
+    $(EdkIIGlueDxeReportStatusCodeLib_LIB)\
+    $(EdkIIGlueDxeServicesTableLib_LIB)\
+    $(EdkIIGlueDxeDebugLibReportStatusCode_LIB)\
+    $(EdkIIGlueUefiBootServicesTableLib_LIB)\
+    $(EdkIIGlueUefiLib_LIB)\
+    $(EdkIIGlueDxeMemoryAllocationLib_LIB)\
+    $(EdkIIGlueUefiBootServicesTableLib_LIB)\
+    $(EdkIIGlueUefiRuntimeServicesTableLib_LIB)\
+    $(EdkIIGlueBasePciLibPciExpress_LIB)\
+    $(EDKPROTOCOLLIB)\
+    $(EFIDRIVERLIB)\
+    $(CpuPlatformLib_LIB)\
+    $(PchPlatformDxeLib_LIB)
+
+PciHostBridgeBin :  $(PciHostBridge_LIB_LINKS)
+                        $(MAKE) /$(MAKEFLAGS) $(EDKIIGLUE_DEFAULTS)\
+                        /f $(BUILD_DIR)\PciHostBridge.mak all\
+                        GUID=8D6756B9-E55E-4d6a-A3A5-5E4D72DDF772 \
+                        ENTRY_POINT=_ModuleEntryPoint \
+                        "MY_DEFINES=$(PciHostBridge_DEFINES)"\
+                        "MY_INCLUDES=$(PciHostBridge_INCLUDES)"\
+                        TYPE=BS_DRIVER \
+                        EDKIIModule=DXEDRIVER\
+                        DEPEX1=$(PciHostBridge_DIR)\PciHostBridge.dxs\
+                        DEPEX1_TYPE=EFI_SECTION_DXE_DEPEX\
+                        COMPRESS=1
diff --git a/ReferenceCode/Chipset/SystemAgent/PciHostBridge/Dxe/PciHostBridge.sdl b/ReferenceCode/Chipset/SystemAgent/PciHostBridge/Dxe/PciHostBridge.sdl
new file mode 100644
index 0000000..9e2b5b3
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/PciHostBridge/Dxe/PciHostBridge.sdl
@@ -0,0 +1,41 @@
+TOKEN
+	Name  = "PciHostBridge_SUPPORT"
+	Value  = "1"
+	TokenType = Boolean
+	TargetEQU = Yes
+	TargetMAK = Yes
+	TargetH = Yes
+	Master = Yes
+	Help  = "Main switch to enable PciHostBridge support in Project"
+	Token = "AMI_ROOT_BRIDGE_SUPPORT" "=" "0"
+End
+
+TOKEN
+	Name  = "TOP_LOW_MEM_GRANULARITY"
+	Value  = "0x10000000"
+	Help  = "Adjust the MMIO granularity size 256MB."
+	TokenType = Integer
+	TargetH = Yes
+End
+
+MODULE
+	Help  = "Includes PciHostBridge.mak to Project"
+	File  = "PciHostBridge.mak"
+End
+
+PATH
+	Name  = "PciHostBridge_DIR"
+End
+
+ELINK
+	Name  = "$(BUILD_DIR)\PciHostBridge.ffs"
+	Parent  = "FV_MAIN"
+	InvokeOrder = AfterParent
+End
+
+ELINK
+	Name  = "/D AMI_COMBINE_MEM_PMEM_FLAG"
+	Parent  = "GLOBAL_DEFINES"
+	InvokeOrder = AfterParent
+	Token = "COMBINE_MEM_PMEM" "=" "1"
+End
\ No newline at end of file
diff --git a/ReferenceCode/Chipset/SystemAgent/PciHostBridge/Dxe/PciRootBridge.h b/ReferenceCode/Chipset/SystemAgent/PciHostBridge/Dxe/PciRootBridge.h
new file mode 100644
index 0000000..557755e
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/PciHostBridge/Dxe/PciRootBridge.h
@@ -0,0 +1,156 @@
+/** @file
+  The driver for the host to pci bridge (root bridge).
+
+@copyright
+  Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement
+**/
+#ifndef _PCI_ROOT_BRIDGE_H_
+#define _PCI_ROOT_BRIDGE_H_
+
+#include "EdkIIGlueDxe.h"
+#include "Acpi.h"
+#include "EfiScriptLib.h"
+#include "SaAccess.h"
+
+///
+/// Driver Consumed Protocol Prototypes
+///
+#include EFI_ARCH_PROTOCOL_DEFINITION (Metronome)
+#include EFI_PROTOCOL_CONSUMER (CpuIo)
+
+///
+/// Driver Produced Protocol Prototypes
+///
+#include EFI_PROTOCOL_DEFINITION (DevicePath)
+#include EFI_PROTOCOL_DEFINITION (PciRootBridgeIo)
+
+///
+/// Define resource status constant
+///
+#define EFI_RESOURCE_NONEXISTENT  0xFFFFFFFFFFFFFFFF
+#define EFI_RESOURCE_LESS         0xFFFFFFFFFFFFFFFE
+#define EFI_RESOURCE_SATISFIED    0x0000000000000000
+
+///
+/// Driver Instance Data Prototypes
+///
+typedef struct {
+  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION Operation;
+  UINTN                                     NumberOfBytes;
+  UINTN                                     NumberOfPages;
+  EFI_PHYSICAL_ADDRESS                      HostAddress;
+  EFI_PHYSICAL_ADDRESS                      MappedHostAddress;
+} MAP_INFO;
+
+typedef struct {
+  ACPI_HID_DEVICE_PATH      AcpiDevicePath;
+  EFI_DEVICE_PATH_PROTOCOL  EndDevicePath;
+} EFI_PCI_ROOT_BRIDGE_DEVICE_PATH;
+
+typedef struct {
+  UINT64  BusBase;
+  UINT64  BusLimit;
+  UINT64  MemBase;
+  UINT64  MemLimit;
+  UINT64  IoBase;
+  UINT64  IoLimit;
+} PCI_ROOT_BRIDGE_RESOURCE_APERTURE;
+
+typedef enum {
+  TypeIo    = 0,
+  TypeMem32,
+  TypePMem32,
+  TypeMem64,
+  TypePMem64,
+  TypeBus,
+  TypeMax
+} PCI_RESOURCE_TYPE;
+
+typedef enum {
+  ResNone     = 0,
+  ResSubmitted,
+  ResRequested,
+  ResAllocated,
+  ResStatusMax
+} RES_STATUS;
+
+typedef struct {
+  PCI_RESOURCE_TYPE Type;
+  UINT64            Base;
+  UINT64            Length;
+  UINT64            Alignment;
+  RES_STATUS        Status;
+} PCI_RES_NODE;
+
+#define PCI_ROOT_BRIDGE_SIGNATURE EFI_SIGNATURE_32 ('e', '2', 'p', 'b')
+
+typedef struct {
+  UINT32                          Signature;
+  LIST_ENTRY                      Link;
+  EFI_HANDLE                      Handle;
+  UINT64                          RootBridgeAttrib;
+  UINT64                          Attributes;
+  UINT64                          Supports;
+
+  ///
+  /// Specific for this memory controller: Bus, I/O, Mem
+  ///
+  PCI_RES_NODE                    ResAllocNode[6];
+
+  ///
+  /// Addressing for Memory and I/O and Bus arrange
+  ///
+  UINT64                          BusBase;
+  UINT64                          MemBase;
+  UINT64                          IoBase;
+  UINT64                          BusLimit;
+  UINT64                          MemLimit;
+  UINT64                          IoLimit;
+  EFI_LOCK                        PciLock;
+  UINTN                           PciAddress;
+  UINTN                           PciData;
+  EFI_DEVICE_PATH_PROTOCOL        *DevicePath;
+  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL Io;
+} PCI_ROOT_BRIDGE_INSTANCE;
+
+///
+/// Driver Instance Data Macros
+///
+#define DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS(a) CR (a, PCI_ROOT_BRIDGE_INSTANCE, Io, PCI_ROOT_BRIDGE_SIGNATURE)
+
+#define DRIVER_INSTANCE_FROM_LIST_ENTRY(a)              CR (a, PCI_ROOT_BRIDGE_INSTANCE, Link, PCI_ROOT_BRIDGE_SIGNATURE)
+
+/**
+  Construct the Pci Root Bridge Io protocol
+
+  @param[in] Protocol         - Point to protocol instance
+  @param[in] HostBridgeHandle - Handle of host bridge
+  @param[in] Attri            - Attribute of host bridge
+  @param[in] ResAperture      - ResourceAperture for host bridge
+
+  @retval EFI_SUCCESS     - Success to initialize the Pci Root Bridge.
+**/
+EFI_STATUS
+RootBridgeConstructor (
+  IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL    *Protocol,
+  IN EFI_HANDLE                         HostBridgeHandle,
+  IN UINT64                             Attri,
+  IN PCI_ROOT_BRIDGE_RESOURCE_APERTURE  *ResAperture
+  )
+;
+
+#endif
diff --git a/ReferenceCode/Chipset/SystemAgent/PciHostBridge/Dxe/PciRootBridgeIo.c b/ReferenceCode/Chipset/SystemAgent/PciHostBridge/Dxe/PciRootBridgeIo.c
new file mode 100644
index 0000000..a3a0447
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/PciHostBridge/Dxe/PciRootBridgeIo.c
@@ -0,0 +1,1515 @@
+/** @file
+  EFI Memory Controller PCI Root Bridge Io Protocol
+
+@copyright
+  Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement
+
+**/
+#include "PciRootBridge.h"
+#include "Pci22.h"
+
+typedef struct {
+  EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR SpaceDesp[TypeMax];
+  EFI_ACPI_END_TAG_DESCRIPTOR       EndDesp;
+} RESOURCE_CONFIGURATION;
+
+RESOURCE_CONFIGURATION  Configuration = {
+  {
+    {
+      0x8A,
+      0x2B,
+      1,
+      0,
+      0,
+      0,
+      0,
+      0,
+      0,
+      0
+    },
+    {
+      0x8A,
+      0x2B,
+      0,
+      0,
+      0,
+      32,
+      0,
+      0,
+      0,
+      0
+    },
+    {
+      0x8A,
+      0x2B,
+      0,
+      0,
+      6,
+      32,
+      0,
+      0,
+      0,
+      0
+    },
+    {
+      0x8A,
+      0x2B,
+      0,
+      0,
+      0,
+      64,
+      0,
+      0,
+      0,
+      0
+    },
+    {
+      0x8A,
+      0x2B,
+      0,
+      0,
+      6,
+      64,
+      0,
+      0,
+      0,
+      0
+    },
+    {
+      0x8A,
+      0x2B,
+      2,
+      0,
+      0,
+      0,
+      0,
+      0,
+      0,
+      0
+    }
+  },
+  {
+    0x79,
+    0
+  }
+};
+
+///
+/// Protocol Member Function Prototypes
+///
+EFI_STATUS
+EFIAPI
+RootBridgeIoPollMem (
+  IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *This,
+  IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,
+  IN  UINT64                                 Address,
+  IN  UINT64                                 Mask,
+  IN  UINT64                                 Value,
+  IN  UINT64                                 Delay,
+  OUT UINT64                                 *Result
+  );
+
+EFI_STATUS
+EFIAPI
+RootBridgeIoPollIo (
+  IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *This,
+  IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,
+  IN  UINT64                                 Address,
+  IN  UINT64                                 Mask,
+  IN  UINT64                                 Value,
+  IN  UINT64                                 Delay,
+  OUT UINT64                                 *Result
+  );
+
+EFI_STATUS
+EFIAPI
+RootBridgeIoMemRead (
+  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *This,
+  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,
+  IN     UINT64                                 Address,
+  IN     UINTN                                  Count,
+  IN OUT VOID                                   *Buffer
+  );
+
+EFI_STATUS
+EFIAPI
+RootBridgeIoMemWrite (
+  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *This,
+  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,
+  IN     UINT64                                 Address,
+  IN     UINTN                                  Count,
+  IN OUT VOID                                   *Buffer
+  );
+
+EFI_STATUS
+EFIAPI
+RootBridgeIoIoRead (
+  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *This,
+  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,
+  IN     UINT64                                 UserAddress,
+  IN     UINTN                                  Count,
+  IN OUT VOID                                   *UserBuffer
+  );
+
+EFI_STATUS
+EFIAPI
+RootBridgeIoIoWrite (
+  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *This,
+  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,
+  IN     UINT64                                 UserAddress,
+  IN     UINTN                                  Count,
+  IN OUT VOID                                   *UserBuffer
+  );
+
+EFI_STATUS
+EFIAPI
+RootBridgeIoCopyMem (
+  IN     struct _EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL  *This,
+  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH    Width,
+  IN     UINT64                                   DestAddress,
+  IN     UINT64                                   SrcAddress,
+  IN     UINTN                                    Count
+  );
+
+EFI_STATUS
+EFIAPI
+RootBridgeIoPciRead (
+  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *This,
+  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,
+  IN     UINT64                                 Address,
+  IN     UINTN                                  Count,
+  IN OUT VOID                                   *Buffer
+  );
+
+EFI_STATUS
+EFIAPI
+RootBridgeIoPciWrite (
+  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *This,
+  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,
+  IN     UINT64                                 Address,
+  IN     UINTN                                  Count,
+  IN OUT VOID                                   *Buffer
+  );
+
+EFI_STATUS
+EFIAPI
+RootBridgeIoMap (
+  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL            *This,
+  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION  Operation,
+  IN     VOID                                       *HostAddress,
+  IN OUT UINTN                                      *NumberOfBytes,
+  OUT    EFI_PHYSICAL_ADDRESS                       *DeviceAddress,
+  OUT    VOID                                       **Mapping
+  );
+
+EFI_STATUS
+EFIAPI
+RootBridgeIoUnmap (
+  IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL  *This,
+  IN  VOID                             *Mapping
+  );
+
+EFI_STATUS
+EFIAPI
+RootBridgeIoAllocateBuffer (
+  IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL  *This,
+  IN  EFI_ALLOCATE_TYPE                Type,
+  IN  EFI_MEMORY_TYPE                  MemoryType,
+  IN  UINTN                            Pages,
+  OUT VOID                             **HostAddress,
+  IN  UINT64                           Attributes
+  );
+
+EFI_STATUS
+EFIAPI
+RootBridgeIoFreeBuffer (
+  IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL  *This,
+  IN  UINTN                            Pages,
+  OUT VOID                             *HostAddress
+  );
+
+EFI_STATUS
+EFIAPI
+RootBridgeIoFlush (
+  IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL  *This
+  );
+
+EFI_STATUS
+EFIAPI
+RootBridgeIoGetAttributes (
+  IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL  *This,
+  OUT UINT64                           *Supported,
+  OUT UINT64                           *Attributes
+  );
+
+EFI_STATUS
+EFIAPI
+RootBridgeIoSetAttributes (
+  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL  *This,
+  IN     UINT64                           Attributes,
+  IN OUT UINT64                           *ResourceBase,
+  IN OUT UINT64                           *ResourceLength
+  );
+
+EFI_STATUS
+EFIAPI
+RootBridgeIoConfiguration (
+  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL  *This,
+  OUT    VOID                             **Resources
+  );
+
+///
+/// Sub Function Prototypes
+///
+typedef union {
+  UINT8 VOLATILE  *buf;
+  UINT8 VOLATILE  *ui8;
+  UINT16 VOLATILE *ui16;
+  UINT32 VOLATILE *ui32;
+  UINT64 VOLATILE *ui64;
+  UINTN VOLATILE  ui;
+} PTR;
+
+STATIC
+EFI_STATUS
+RootBridgeIoPciRW (
+  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *This,
+  IN     BOOLEAN                                Write,
+  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,
+  IN     UINT64                                 UserAddress,
+  IN     UINTN                                  Count,
+  IN OUT VOID                                   *UserBuffer
+  );
+
+///
+/// Memory Controller Pci Root Bridge Io Module Variables
+///
+EFI_METRONOME_ARCH_PROTOCOL *mMetronome;
+EFI_CPU_IO_PROTOCOL         *mCpuIo;
+
+/**
+  Construct the Pci Root Bridge Io protocol
+
+  @param Protocol         - Point to protocol instance
+  @param HostBridgeHandle - Handle of host bridge
+  @param Attri            - Attribute of host bridge
+  @param ResAperture      - ResourceAperture for host bridge
+
+  @retval EFI_SUCCESS     - Success to initialize the Pci Root Bridge.
+**/
+EFI_STATUS
+RootBridgeConstructor (
+  IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL    *Protocol,
+  IN EFI_HANDLE                         HostBridgeHandle,
+  IN UINT64                             Attri,
+  IN PCI_ROOT_BRIDGE_RESOURCE_APERTURE  *ResAperture
+  )
+{
+  EFI_STATUS                Status;
+  PCI_ROOT_BRIDGE_INSTANCE  *PrivateData;
+  PCI_RESOURCE_TYPE         Index;
+
+  PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (Protocol);
+
+  ///
+  /// The host to pci bridge, the host memory and io addresses are
+  /// direct mapped to pci addresses, so no need translate, set bases to 0.
+  ///
+  PrivateData->MemBase  = ResAperture->MemBase;
+  PrivateData->IoBase   = ResAperture->IoBase;
+
+  ///
+  /// The host bridge only supports 32bit addressing for memory
+  /// and standard IA32 16bit io
+  ///
+  PrivateData->MemLimit = ResAperture->MemLimit;
+  PrivateData->IoLimit  = ResAperture->IoLimit;
+
+  ///
+  /// Bus Aperture for this Root Bridge (Possible Range)
+  ///
+  PrivateData->BusBase  = ResAperture->BusBase;
+  PrivateData->BusLimit = ResAperture->BusLimit;
+
+  ///
+  /// Specific for this chipset
+  ///
+  for (Index = TypeIo; Index < TypeMax; Index++) {
+    PrivateData->ResAllocNode[Index].Type   = Index;
+    PrivateData->ResAllocNode[Index].Base   = 0;
+    PrivateData->ResAllocNode[Index].Length = 0;
+    PrivateData->ResAllocNode[Index].Status = ResNone;
+  }
+
+  EfiInitializeLock (&PrivateData->PciLock, EFI_TPL_HIGH_LEVEL);
+  PrivateData->PciAddress       = 0xCF8;
+  PrivateData->PciData          = 0xCFC;
+  PrivateData->RootBridgeAttrib = Attri;
+  PrivateData->Attributes       = 0;
+  ///
+  /// Set both ISA_IO and ISA_IO_16 / VGA_IO and VGA_IO_16 to co-work
+  /// with EDK and EDK2 PCI bus driver.
+  ///
+  PrivateData->Supports = EFI_PCI_ATTRIBUTE_ISA_MOTHERBOARD_IO |
+    EFI_PCI_ATTRIBUTE_IDE_PRIMARY_IO |
+    EFI_PCI_ATTRIBUTE_ISA_IO |
+    EFI_PCI_ATTRIBUTE_ISA_IO_16 |
+    EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO |
+    EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16 |
+    EFI_PCI_ATTRIBUTE_VGA_MEMORY |
+    EFI_PCI_ATTRIBUTE_VGA_IO |
+    EFI_PCI_ATTRIBUTE_VGA_IO_16;
+  Protocol->ParentHandle    = HostBridgeHandle;
+  Protocol->PollMem         = RootBridgeIoPollMem;
+  Protocol->PollIo          = RootBridgeIoPollIo;
+  Protocol->Mem.Read        = RootBridgeIoMemRead;
+  Protocol->Mem.Write       = RootBridgeIoMemWrite;
+  Protocol->Io.Read         = RootBridgeIoIoRead;
+  Protocol->Io.Write        = RootBridgeIoIoWrite;
+  Protocol->CopyMem         = RootBridgeIoCopyMem;
+  Protocol->Pci.Read        = RootBridgeIoPciRead;
+  Protocol->Pci.Write       = RootBridgeIoPciWrite;
+  Protocol->Map             = RootBridgeIoMap;
+  Protocol->Unmap           = RootBridgeIoUnmap;
+  Protocol->AllocateBuffer  = RootBridgeIoAllocateBuffer;
+  Protocol->FreeBuffer      = RootBridgeIoFreeBuffer;
+  Protocol->Flush           = RootBridgeIoFlush;
+  Protocol->GetAttributes   = RootBridgeIoGetAttributes;
+  Protocol->SetAttributes   = RootBridgeIoSetAttributes;
+  Protocol->Configuration   = RootBridgeIoConfiguration;
+  Protocol->SegmentNumber   = 0;
+  Status                    = gBS->LocateProtocol (&gEfiMetronomeArchProtocolGuid, NULL, (VOID **) &mMetronome);
+  ASSERT_EFI_ERROR (Status);
+
+  Status = gBS->LocateProtocol (&gEfiCpuIoProtocolGuid, NULL, (VOID **) &mCpuIo);
+  ASSERT_EFI_ERROR (Status);
+
+  return EFI_SUCCESS;
+}
+
+/**
+   Polls an address in memory mapped I/O space until an exit condition is met, or
+   a timeout occurs.
+
+   @param[in]   This      - A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
+   @param[in]   Width     - Signifies the width of the memory operations.
+   @param[in]   Address   - The base address of the memory operations. The caller is
+                            responsible for aligning Address if required.
+   @param[in]   Mask      - Mask used for the polling criteria. Bytes above Width in Mask
+                            are ignored. The bits in the bytes below Width which are zero in
+                            Mask are ignored when polling the memory address.
+   @param[in]   Value     - The comparison value used for the polling exit criteria.
+   @param[in]   Delay     - The number of 100 ns units to poll. Note that timer available may
+                            be of poorer granularity.
+   @param[out]  Result    - Pointer to the last value read from the memory location.
+
+   @retval EFI_SUCCESS            - The last data returned from the access matched the poll exit criteria.
+   @retval EFI_INVALID_PARAMETER  - Width is invalid or Result is NULL..
+   @retval EFI_TIMEOUT            - Delay expired before a match occurred.
+**/
+EFI_STATUS
+EFIAPI
+RootBridgeIoPollMem (
+  IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *This,
+  IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,
+  IN  UINT64                                 Address,
+  IN  UINT64                                 Mask,
+  IN  UINT64                                 Value,
+  IN  UINT64                                 Delay,
+  OUT UINT64                                 *Result
+  )
+{
+  EFI_STATUS  Status;
+  UINT64      NumberOfTicks;
+  UINT32      Remainder;
+
+  if (Result == NULL) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  if (Width < 0 || Width > EfiPciWidthUint64) {
+    return EFI_INVALID_PARAMETER;
+  }
+  ///
+  /// No matter what, always do a single poll.
+  ///
+  Status = This->Mem.Read (This, Width, Address, 1, Result);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+
+  if ((*Result & Mask) == Value) {
+    return EFI_SUCCESS;
+  }
+
+  if (Delay == 0) {
+    return EFI_SUCCESS;
+  } else {
+    ///
+    /// Determine the proper # of metronome ticks to wait for polling the
+    /// location.  The nuber of ticks is Roundup (Delay / mMetronome->TickPeriod)+1
+    /// The "+1" to account for the possibility of the first tick being short
+    /// because we started in the middle of a tick.
+    ///
+    NumberOfTicks = DivU64x32Remainder (Delay, (UINT32) mMetronome->TickPeriod, &Remainder);
+    if (Remainder != 0) {
+      NumberOfTicks += 1;
+    }
+
+    NumberOfTicks += 1;
+    while (NumberOfTicks) {
+      mMetronome->WaitForTick (mMetronome, 1);
+      Status = This->Mem.Read (This, Width, Address, 1, Result);
+      if (EFI_ERROR (Status)) {
+        return Status;
+      }
+
+      if ((*Result & Mask) == Value) {
+        return EFI_SUCCESS;
+      }
+
+      NumberOfTicks -= 1;
+    }
+  }
+
+  return EFI_TIMEOUT;
+}
+
+/**
+   Reads from the I/O space of a PCI Root Bridge. Returns when either the polling exit criteria is
+   satisfied or after a defined duration.
+
+   @param[in] This      - A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
+   @param[in] Width     - Signifies the width of the I/O operations.
+   @param[in] Address   - The base address of the I/O operations. The caller is responsible
+                          for aligning Address if required.
+   @param[in] Mask      - Mask used for the polling criteria. Bytes above Width in Mask
+                          are ignored. The bits in the bytes below Width which are zero in
+                          Mask are ignored when polling the I/O address.
+   @param[in] Value     - The comparison value used for the polling exit criteria.
+   @param[in] Delay     - The number of 100 ns units to poll. Note that timer available may
+                          be of poorer granularity.
+   @param[out] Result   - Pointer to the last value read from the memory location.
+
+   @retval EFI_SUCCESS            - The last data returned from the access matched the poll exit criteria.
+   @retval EFI_INVALID_PARAMETER  - Width is invalid or Result is NULL.
+   @retval EFI_TIMEOUT            - Delay expired before a match occurred.
+**/
+EFI_STATUS
+EFIAPI
+RootBridgeIoPollIo (
+  IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *This,
+  IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,
+  IN  UINT64                                 Address,
+  IN  UINT64                                 Mask,
+  IN  UINT64                                 Value,
+  IN  UINT64                                 Delay,
+  OUT UINT64                                 *Result
+  )
+{
+  EFI_STATUS  Status;
+  UINT64      NumberOfTicks;
+  UINT32      Remainder;
+
+  ///
+  /// No matter what, always do a single poll.
+  ///
+  if (Result == NULL) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  if (Width < 0 || Width > EfiPciWidthUint64) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  Status = This->Io.Read (This, Width, Address, 1, Result);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+
+  if ((*Result & Mask) == Value) {
+    return EFI_SUCCESS;
+  }
+
+  if (Delay == 0) {
+    return EFI_SUCCESS;
+  } else {
+    ///
+    /// Determine the proper # of metronome ticks to wait for polling the
+    /// location.  The number of ticks is Roundup (Delay / mMetronome->TickPeriod)+1
+    /// The "+1" to account for the possibility of the first tick being short
+    /// because we started in the middle of a tick.
+    ///
+    NumberOfTicks = DivU64x32Remainder (Delay, (UINT32) mMetronome->TickPeriod, &Remainder);
+    if (Remainder != 0) {
+      NumberOfTicks += 1;
+    }
+
+    NumberOfTicks += 1;
+    while (NumberOfTicks) {
+      mMetronome->WaitForTick (mMetronome, 1);
+      Status = This->Io.Read (This, Width, Address, 1, Result);
+      if (EFI_ERROR (Status)) {
+        return Status;
+      }
+
+      if ((*Result & Mask) == Value) {
+        return EFI_SUCCESS;
+      }
+
+      NumberOfTicks -= 1;
+    }
+  }
+
+  return EFI_TIMEOUT;
+}
+
+/**
+   Enables a PCI driver to access PCI controller registers in the PCI root bridge memory space.
+
+   @param[in]   This      - A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
+   @param[in]   Width     - Signifies the width of the memory operation.
+   @param[in]   Address   - The base address of the memory operation. The caller is
+                            responsible for aligning the Address if required.
+   @param[in]   Count     - The number of memory operations to perform. Bytes moved is
+                            Width size * Count, starting at Address.
+   @param[in, out] Buffer - For read operations, the destination buffer to store the results. For
+                            write operations, the source buffer to write data from.
+
+   @retval EFI_SUCCESS            - The data was read from or written to the PCI root bridge.
+   @retval EFI_INVALID_PARAMETER  - Width is invalid for this PCI root bridge or Buffer is NULL.
+**/
+EFI_STATUS
+EFIAPI
+RootBridgeIoMemRead (
+  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *This,
+  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,
+  IN     UINT64                                 Address,
+  IN     UINTN                                  Count,
+  IN OUT VOID                                   *Buffer
+  )
+{
+  PCI_ROOT_BRIDGE_INSTANCE              *PrivateData;
+  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH OldWidth;
+  UINTN                                 OldCount;
+
+  if (Buffer == NULL) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  if (Width < 0 || Width >= EfiPciWidthMaximum) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+// AMI_OVERRIDE (EIP#106042+)>>
+  // Fix Fpt.efi not work, accessing Rom decode region could cause AEL bit 
+  // be set, and, Pci Resource should not be inside rom decode region.
+  if ((Address >= 0xff000000) && (Address <= 0xffffffff)) {
+    return EFI_INVALID_PARAMETER;
+  }
+// AMI_OVERRIDE <<
+
+  PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (This);
+
+  ///
+  /// Check memory access limit
+  ///
+  if (Address < PrivateData->MemBase) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  OldWidth  = Width;
+  OldCount  = Count;
+  if (Width >= EfiPciWidthFifoUint8 && Width <= EfiPciWidthFifoUint64) {
+    Count = 1;
+  }
+
+  Width &= 0x03;
+  if (Address + MultU64x32 (LShiftU64 (1, Width), (UINT32) Count) - 1 > PrivateData->MemLimit) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  return mCpuIo->Mem.Read (
+                      mCpuIo,
+                      (EFI_CPU_IO_PROTOCOL_WIDTH) OldWidth,
+                      Address,
+                      OldCount,
+                      Buffer
+                      );
+}
+
+/**
+   Enables a PCI driver to access PCI controller registers in the PCI root bridge memory space.
+
+   @param[in]   This      - A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
+   @param[in]   Width     - Signifies the width of the memory operation.
+   @param[in]   Address   - The base address of the memory operation. The caller is
+                            responsible for aligning the Address if required.
+   @param[in]   Count     - The number of memory operations to perform. Bytes moved is
+                            Width size * Count, starting at Address.
+   @param[in, out] Buffer - For read operations, the destination buffer to store the results. For
+                            write operations, the source buffer to write data from.
+
+   @retval EFI_SUCCESS            - The data was read from or written to the PCI root bridge.
+   @retval EFI_INVALID_PARAMETER  - Width is invalid for this PCI root bridge or Buffer is NULL.
+**/
+EFI_STATUS
+EFIAPI
+RootBridgeIoMemWrite (
+  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *This,
+  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,
+  IN     UINT64                                 Address,
+  IN     UINTN                                  Count,
+  IN OUT VOID                                   *Buffer
+  )
+{
+  PCI_ROOT_BRIDGE_INSTANCE              *PrivateData;
+  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH OldWidth;
+  UINTN                                 OldCount;
+
+  if (Buffer == NULL) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  if (Width < 0 || Width >= EfiPciWidthMaximum) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (This);
+
+  ///
+  /// Check memory access limit
+  ///
+  if (Address < PrivateData->MemBase) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  OldWidth  = Width;
+  OldCount  = Count;
+  if (Width >= EfiPciWidthFifoUint8 && Width <= EfiPciWidthFifoUint64) {
+    Count = 1;
+  }
+
+  Width &= 0x03;
+  if (Address + MultU64x32 (LShiftU64 (1, Width), (UINT32) Count) - 1 > PrivateData->MemLimit) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  return mCpuIo->Mem.Write (
+                      mCpuIo,
+                      (EFI_CPU_IO_PROTOCOL_WIDTH) OldWidth,
+                      Address,
+                      OldCount,
+                      Buffer
+                      );
+}
+
+/**
+   Enables a PCI driver to access PCI controller registers in the PCI root bridge I/O space.
+
+   @param[in]   This        - A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
+   @param[in]   Width       - Signifies the width of the memory operations.
+   @param[in]   UserAddress - The base address of the I/O operation. The caller is responsible for
+                              aligning the Address if required.
+   @param[in]   Count       - The number of I/O operations to perform. Bytes moved is Width
+                              size * Count, starting at Address.
+   @param[in, out] UserBuffer - For read operations, the destination buffer to store the results. For
+                              write operations, the source buffer to write data from.
+
+   @retval EFI_SUCCESS              - The data was read from or written to the PCI root bridge.
+   @retval EFI_INVALID_PARAMETER    - Width is invalid for this PCI root bridge or Buffer is NULL.
+**/
+EFI_STATUS
+EFIAPI
+RootBridgeIoIoRead (
+  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *This,
+  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,
+  IN     UINT64                                 Address,
+  IN     UINTN                                  Count,
+  IN OUT VOID                                   *Buffer
+  )
+{
+
+  UINTN                                 AlignMask;
+  PCI_ROOT_BRIDGE_INSTANCE              *PrivateData;
+  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH OldWidth;
+  UINTN                                 OldCount;
+
+  if (Buffer == NULL) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  if (Width < 0 || Width >= EfiPciWidthMaximum) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (This);
+
+  ///
+  /// AlignMask = (1 << Width) - 1;
+  ///
+  AlignMask = (1 << (Width & 0x03)) - 1;
+
+  ///
+  /// Check Io access limit
+  ///
+  if (Address < PrivateData->IoBase) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  OldWidth  = Width;
+  OldCount  = Count;
+  if (Width >= EfiPciWidthFifoUint8 && Width <= EfiPciWidthFifoUint64) {
+    Count = 1;
+  }
+
+  Width &= 0x03;
+  if (Address + MultU64x32 (LShiftU64 (1, Width), (UINT32) Count) - 1 >= PrivateData->IoLimit) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  if (Address & AlignMask) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  return mCpuIo->Io.Read (
+                      mCpuIo,
+                      (EFI_CPU_IO_PROTOCOL_WIDTH) OldWidth,
+                      Address,
+                      OldCount,
+                      Buffer
+                      );
+}
+
+/**
+   Enables a PCI driver to access PCI controller registers in the PCI root bridge I/O space.
+
+   @param[in]   This        - A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
+   @param[in]   Width       - Signifies the width of the memory operations.
+   @param[in]   UserAddress - The base address of the I/O operation. The caller is responsible for
+                              aligning the Address if required.
+   @param[in]   Count       - The number of I/O operations to perform. Bytes moved is Width
+                              size * Count, starting at Address.
+   @param[in, out] UserBuffer - For read operations, the destination buffer to store the results. For
+                              write operations, the source buffer to write data from.
+
+   @retval EFI_SUCCESS              - The data was read from or written to the PCI root bridge.
+   @retval EFI_INVALID_PARAMETER    - Width is invalid for this PCI root bridge or Buffer is NULL.
+**/
+EFI_STATUS
+EFIAPI
+RootBridgeIoIoWrite (
+  IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL         *This,
+  IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH   Width,
+  IN UINT64                                  Address,
+  IN UINTN                                   Count,
+  IN OUT VOID                                *Buffer
+  )
+{
+  UINTN                                 AlignMask;
+  PCI_ROOT_BRIDGE_INSTANCE              *PrivateData;
+  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH OldWidth;
+  UINTN                                 OldCount;
+
+  if (Buffer == NULL) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  if (Width < 0 || Width >= EfiPciWidthMaximum) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (This);
+
+  ///
+  /// AlignMask = (1 << Width) - 1;
+  ///
+  AlignMask = (1 << (Width & 0x03)) - 1;
+
+  ///
+  /// Check Io access limit
+  ///
+  if (Address < PrivateData->IoBase) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  OldWidth  = Width;
+  OldCount  = Count;
+  if (Width >= EfiPciWidthFifoUint8 && Width <= EfiPciWidthFifoUint64) {
+    Count = 1;
+  }
+
+  Width &= 0x03;
+  if (Address + MultU64x32 (LShiftU64 (1, Width), (UINT32) Count) - 1 >= PrivateData->IoLimit) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  if (Address & AlignMask) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  return mCpuIo->Io.Write (
+                      mCpuIo,
+                      (EFI_CPU_IO_PROTOCOL_WIDTH) OldWidth,
+                      Address,
+                      OldCount,
+                      Buffer
+                      );
+}
+
+/**
+   Enables a PCI driver to copy one region of PCI root bridge memory space to another region of PCI
+   root bridge memory space.
+
+   @param[in] This        - A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL instance.
+   @param[in] Width       - Signifies the width of the memory operations.
+   @param[in] DestAddress - The destination address of the memory operation. The caller is
+                            responsible for aligning the DestAddress if required.
+   @param[in] SrcAddress  - The source address of the memory operation. The caller is
+                            responsible for aligning the SrcAddress if required.
+   @param[in] Count       - The number of memory operations to perform. Bytes moved is
+                            Width size * Count, starting at DestAddress and SrcAddress.
+
+   @retval  EFI_SUCCESS             - The data was copied from one memory region to another memory region.
+   @retval  EFI_INVALID_PARAMETER   - Width is invalid for this PCI root bridge.
+**/
+EFI_STATUS
+EFIAPI
+RootBridgeIoCopyMem (
+  IN     struct _EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL  *This,
+  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH    Width,
+  IN     UINT64                                   DestAddress,
+  IN     UINT64                                   SrcAddress,
+  IN     UINTN                                    Count
+  )
+{
+  EFI_STATUS  Status;
+  BOOLEAN     Direction;
+  UINTN       Stride;
+  UINTN       Index;
+  UINT64      Result;
+
+  if (Width < 0 || Width > EfiPciWidthUint64) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  if (DestAddress == SrcAddress) {
+    return EFI_SUCCESS;
+  }
+
+  Stride    = (UINTN) (LShiftU64 (1, Width));
+  Direction = TRUE;
+  if ((DestAddress > SrcAddress) && (DestAddress < (SrcAddress + Count * Stride))) {
+    Direction   = FALSE;
+    SrcAddress  = SrcAddress + (Count - 1) * Stride;
+    DestAddress = DestAddress + (Count - 1) * Stride;
+  }
+
+  for (Index = 0; Index < Count; Index++) {
+    Status = RootBridgeIoMemRead (
+              This,
+              Width,
+              SrcAddress,
+              1,
+              &Result
+              );
+    if (EFI_ERROR (Status)) {
+      return Status;
+    }
+
+    Status = RootBridgeIoMemWrite (
+              This,
+              Width,
+              DestAddress,
+              1,
+              &Result
+              );
+    if (EFI_ERROR (Status)) {
+      return Status;
+    }
+
+    if (Direction) {
+      SrcAddress += Stride;
+      DestAddress += Stride;
+    } else {
+      SrcAddress -= Stride;
+      DestAddress -= Stride;
+    }
+  }
+
+  return EFI_SUCCESS;
+}
+
+/**
+   Enables a PCI driver to access PCI controller registers in a PCI root bridge's configuration space.
+
+   @param[in]   This      - A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
+   @param[in]   Width     - Signifies the width of the memory operations.
+   @param[in]   Address   - The address within the PCI configuration space for the PCI controller.
+   @param[in]   Count     - The number of PCI configuration operations to perform. Bytes
+                            moved is Width size * Count, starting at Address.
+   @param[in, out] Buffer - For read operations, the destination buffer to store the results. For
+                            write operations, the source buffer to write data from.
+
+   @retval EFI_SUCCESS            - The data was read from or written to the PCI root bridge.
+   @retval EFI_INVALID_PARAMETER  - Width is invalid for this PCI root bridge or Buffer is NULL.
+**/
+EFI_STATUS
+EFIAPI
+RootBridgeIoPciRead (
+  IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *This,
+  IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,
+  IN UINT64                                 Address,
+  IN UINTN                                  Count,
+  IN OUT VOID                               *Buffer
+  )
+{
+  if (Buffer == NULL) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  if (Width < 0 || Width >= EfiPciWidthMaximum) {
+    return EFI_INVALID_PARAMETER;
+  }
+  ///
+  /// Read Pci configuration space
+  ///
+  return RootBridgeIoPciRW (This, FALSE, Width, Address, Count, Buffer);
+}
+
+/**
+   Enables a PCI driver to access PCI controller registers in a PCI root bridge's configuration space.
+
+   @param[in]   This      - A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
+   @param[in]   Width     - Signifies the width of the memory operations.
+   @param[in]   Address   - The address within the PCI configuration space for the PCI controller.
+   @param[in]   Count     - The number of PCI configuration operations to perform. Bytes
+                            moved is Width size * Count, starting at Address.
+   @param[in, out] Buffer - For read operations, the destination buffer to store the results. For
+                            write operations, the source buffer to write data from.
+
+   @retval EFI_SUCCESS            - The data was read from or written to the PCI root bridge.
+   @retval EFI_INVALID_PARAMETER  - Width is invalid for this PCI root bridge or Buffer is NULL.
+**/
+EFI_STATUS
+EFIAPI
+RootBridgeIoPciWrite (
+  IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *This,
+  IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,
+  IN UINT64                                 Address,
+  IN UINTN                                  Count,
+  IN OUT VOID                               *Buffer
+  )
+{
+
+  if (Buffer == NULL) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  if (Width < 0 || Width >= EfiPciWidthMaximum) {
+    return EFI_INVALID_PARAMETER;
+  }
+  ///
+  /// Write Pci configuration space
+  ///
+  return RootBridgeIoPciRW (This, TRUE, Width, Address, Count, Buffer);
+}
+
+/**
+   Provides the PCI controller-specific addresses required to access system memory from a
+   DMA bus master.
+
+   @param[in]       This            - A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
+   @param[in]       Operation       - Indicates if the bus master is going to read or write to system memory.
+   @param[in]       HostAddress     - The system memory address to map to the PCI controller.
+   @param[in, out]  NumberOfBytes   - On input the number of bytes to map. On output the number of bytes that were mapped.
+   @param[out]      DeviceAddress   - The resulting map address for the bus master PCI controller to use
+                                      to access the system memory's HostAddress.
+   @param[out]      Mapping         - The value to pass to Unmap() when the bus master DMA operation is complete.
+
+   @retval EFI_SUCCESS            - The range was mapped for the returned NumberOfBytes.
+   @retval EFI_INVALID_PARAMETER  - Operation is invalid.
+   @retval EFI_INVALID_PARAMETER  - HostAddress or NumberOfBytes or DeviceAddress or Mapping is NULL.
+   @retval EFI_UNSUPPORTED        - The HostAddress cannot be mapped as a common buffer.
+**/
+EFI_STATUS
+EFIAPI
+RootBridgeIoMap (
+  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL            *This,
+  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION  Operation,
+  IN     VOID                                       *HostAddress,
+  IN OUT UINTN                                      *NumberOfBytes,
+  OUT    EFI_PHYSICAL_ADDRESS                       *DeviceAddress,
+  OUT    VOID                                       **Mapping
+  )
+{
+  EFI_STATUS            Status;
+  EFI_PHYSICAL_ADDRESS  PhysicalAddress;
+  MAP_INFO              *MapInfo;
+
+  if (HostAddress == NULL || NumberOfBytes == NULL || DeviceAddress == NULL || Mapping == NULL) {
+    return EFI_INVALID_PARAMETER;
+  }
+  ///
+  /// Initialize the return values to their defaults
+  ///
+  *Mapping = NULL;
+
+  ///
+  /// Make sure that Operation is valid
+  ///
+  if (Operation < 0 || Operation >= EfiPciOperationMaximum) {
+    return EFI_INVALID_PARAMETER;
+  }
+  ///
+  /// Most PCAT like chipsets can not handle performing DMA above 4GB.
+  /// If any part of the DMA transfer being mapped is above 4GB, then
+  /// map the DMA transfer to a buffer below 4GB.
+  ///
+  PhysicalAddress = (EFI_PHYSICAL_ADDRESS) (UINTN) HostAddress;
+  if ((PhysicalAddress +*NumberOfBytes) > 0x100000000) {
+    ///
+    /// Common Buffer operations can not be remapped.  If the common buffer
+    /// if above 4GB, then it is not possible to generate a mapping, so return
+    /// an error.
+    ///
+    if (Operation == EfiPciOperationBusMasterCommonBuffer || Operation == EfiPciOperationBusMasterCommonBuffer64) {
+      return EFI_UNSUPPORTED;
+    }
+    ///
+    /// Allocate a MAP_INFO structure to remember the mapping when Unmap() is
+    /// called later.
+    ///
+    Status = (gBS->AllocatePool) (EfiBootServicesData, sizeof (MAP_INFO), (VOID **) &MapInfo);
+    if (EFI_ERROR (Status)) {
+      *NumberOfBytes = 0;
+      return Status;
+    }
+    ///
+    /// Return a pointer to the MAP_INFO structure in Mapping
+    ///
+    *Mapping = MapInfo;
+
+    ///
+    /// Initialize the MAP_INFO structure
+    ///
+    MapInfo->Operation          = Operation;
+    MapInfo->NumberOfBytes      = *NumberOfBytes;
+    MapInfo->NumberOfPages      = EFI_SIZE_TO_PAGES (*NumberOfBytes);
+    MapInfo->HostAddress        = PhysicalAddress;
+    MapInfo->MappedHostAddress  = 0x00000000ffffffff;
+
+    ///
+    /// Allocate a buffer below 4GB to map the transfer to.
+    ///
+    Status = (gBS->AllocatePages) (AllocateMaxAddress, EfiBootServicesData, MapInfo->NumberOfPages, &MapInfo->MappedHostAddress);
+    if (EFI_ERROR (Status)) {
+      (gBS->FreePool) (MapInfo);
+      *NumberOfBytes = 0;
+      return Status;
+    }
+    ///
+    /// If this is a read operation from the Bus Master's point of view,
+    /// then copy the contents of the real buffer into the mapped buffer
+    /// so the Bus Master can read the contents of the real buffer.
+    ///
+    if (Operation == EfiPciOperationBusMasterRead || Operation == EfiPciOperationBusMasterRead64) {
+      CopyMem (
+        (VOID *) (UINTN) MapInfo->MappedHostAddress,
+        (VOID *) (UINTN) MapInfo->HostAddress,
+        MapInfo->NumberOfBytes
+        );
+    }
+    ///
+    /// The DeviceAddress is the address of the maped buffer below 4GB
+    ///
+    *DeviceAddress = MapInfo->MappedHostAddress;
+  } else {
+    ///
+    /// The transfer is below 4GB, so the DeviceAddress is simply the HostAddress
+    ///
+    *DeviceAddress = PhysicalAddress;
+  }
+
+  return EFI_SUCCESS;
+}
+
+/**
+   Completes the Map() operation and releases any corresponding resources.
+
+   @param[in] This      - A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
+   @param[in] Mapping   - The mapping value returned from Map().
+
+   @retval EFI_SUCCESS            - The range was unmapped.
+   @retval EFI_INVALID_PARAMETER  - Mapping is not a value that was returned by Map().
+**/
+EFI_STATUS
+EFIAPI
+RootBridgeIoUnmap (
+  IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL  *This,
+  IN VOID                             *Mapping
+  )
+{
+  MAP_INFO  *MapInfo;
+
+  ///
+  /// See if the Map() operation associated with this Unmap() required a mapping buffer.
+  /// If a mapping buffer was not required, then this function simply returns EFI_SUCCESS.
+  ///
+  if (Mapping != NULL) {
+    ///
+    /// Get the MAP_INFO structure from Mapping
+    ///
+    MapInfo = (MAP_INFO *) Mapping;
+
+    ///
+    /// If this is a write operation from the Bus Master's point of view,
+    /// then copy the contents of the mapped buffer into the real buffer
+    /// so the processor can read the contents of the real buffer.
+    ///
+    if (MapInfo->Operation == EfiPciOperationBusMasterWrite || MapInfo->Operation == EfiPciOperationBusMasterWrite64) {
+      CopyMem (
+        (VOID *) (UINTN) MapInfo->HostAddress,
+        (VOID *) (UINTN) MapInfo->MappedHostAddress,
+        MapInfo->NumberOfBytes
+        );
+    }
+    ///
+    /// Free the mapped buffer and the MAP_INFO structure.
+    ///
+    (gBS->FreePages) (MapInfo->MappedHostAddress, MapInfo->NumberOfPages);
+    (gBS->FreePool) (Mapping);
+  }
+
+  return EFI_SUCCESS;
+}
+
+/**
+   Allocates pages that are suitable for an EfiPciOperationBusMasterCommonBuffer or
+   EfiPciOperationBusMasterCommonBuffer64 mapping.
+
+   @param This        - A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
+   @param Type        - This parameter is not used and must be ignored.
+   @param MemoryType  - The type of memory to allocate, EfiBootServicesData or EfiRuntimeServicesData.
+   @param Pages       - The number of pages to allocate.
+   @param HostAddress - A pointer to store the base system memory address of the allocated range.
+   @param Attributes  - The requested bit mask of attributes for the allocated range. Only
+                        the attributes EFI_PCI_ATTRIBUTE_MEMORY_WRITE_COMBINE, EFI_PCI_ATTRIBUTE_MEMORY_CACHED,
+                        and EFI_PCI_ATTRIBUTE_DUAL_ADDRESS_CYCLE may be used with this function.
+
+   @retval EFI_SUCCESS            - The requested memory pages were allocated.
+   @retval EFI_INVALID_PARAMETER  - MemoryType is invalid or HostAddress is NULL.
+   @retval EFI_UNSUPPORTED        - Attributes is unsupported. The only legal attribute bits are
+                                    MEMORY_WRITE_COMBINE, MEMORY_CACHED, and DUAL_ADDRESS_CYCLE.
+**/
+EFI_STATUS
+EFIAPI
+RootBridgeIoAllocateBuffer (
+  IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL  *This,
+  IN  EFI_ALLOCATE_TYPE                Type,
+  IN  EFI_MEMORY_TYPE                  MemoryType,
+  IN  UINTN                            Pages,
+  OUT VOID                             **HostAddress,
+  IN  UINT64                           Attributes
+  )
+{
+  EFI_STATUS            Status;
+  EFI_PHYSICAL_ADDRESS  PhysicalAddress;
+
+  ///
+  /// Validate Attributes
+  ///
+  if (Attributes & EFI_PCI_ATTRIBUTE_INVALID_FOR_ALLOCATE_BUFFER) {
+    return EFI_UNSUPPORTED;
+  }
+  ///
+  /// Check for invalid inputs
+  ///
+  if (HostAddress == NULL) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  ///
+  /// The only valid memory types are EfiBootServicesData and EfiRuntimeServicesData
+  ///
+  if (MemoryType != EfiBootServicesData && MemoryType != EfiRuntimeServicesData) {
+    return EFI_INVALID_PARAMETER;
+  }
+  ///
+  /// Limit allocations to memory below 4GB
+  ///
+  PhysicalAddress = (EFI_PHYSICAL_ADDRESS) (0xffffffff);
+  Status          = (gBS->AllocatePages) (AllocateMaxAddress, MemoryType, Pages, &PhysicalAddress);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+
+  *HostAddress = (VOID *) (UINTN) PhysicalAddress;
+  return EFI_SUCCESS;
+}
+
+/**
+   Frees memory that was allocated with AllocateBuffer().
+
+   The FreeBuffer() function frees memory that was allocated with AllocateBuffer().
+
+   @param This        - A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
+   @param Pages       - The number of pages to free.
+   @param HostAddress - The base system memory address of the allocated range.
+
+   @retval EFI_SUCCESS            - The requested memory pages were freed.
+   @retval EFI_INVALID_PARAMETER  - The memory range specified by HostAddress and Pages
+                                    was not allocated with AllocateBuffer().
+**/
+EFI_STATUS
+EFIAPI
+RootBridgeIoFreeBuffer (
+  IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL  *This,
+  IN  UINTN                            Pages,
+  OUT VOID                             *HostAddress
+  )
+{
+  return (gBS->FreePages) ((EFI_PHYSICAL_ADDRESS) (UINTN) HostAddress, Pages);
+}
+
+/**
+  Flushes all PCI posted write transactions from a PCI host bridge to system memory.
+
+  @param This        - A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
+
+  @retval EFI_SUCCESS        - The PCI posted write transactions were flushed from the PCI host
+                               bridge to system memory.
+**/
+EFI_STATUS
+EFIAPI
+RootBridgeIoFlush (
+  IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL           *This
+  )
+{
+  ///
+  /// not supported yet
+  ///
+  return EFI_SUCCESS;
+}
+
+/**
+  Gets the attributes that a PCI root bridge supports setting with SetAttributes(), and the
+  attributes that a PCI root bridge is currently using.
+
+  @param This        - A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
+  @param Supported   - A pointer to the mask of attributes that this PCI root bridge
+                       supports setting with SetAttributes().
+  @param Attributes  - A pointer to the mask of attributes that this PCI root bridge is
+                       currently using.
+
+  @retval  EFI_SUCCESS           - If Supports is not NULL, then the attributes that the PCI root
+                                   bridge supports is returned in Supports. If Attributes is
+                                   not NULL, then the attributes that the PCI root bridge is currently
+                                   using is returned in Attributes.
+  @retval  EFI_INVALID_PARAMETER - Both Supports and Attributes are NULL.
+**/
+EFI_STATUS
+EFIAPI
+RootBridgeIoGetAttributes (
+  IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL  *This,
+  OUT UINT64                           *Supported,
+  OUT UINT64                           *Attributes
+  )
+{
+  PCI_ROOT_BRIDGE_INSTANCE  *PrivateData;
+
+  PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (This);
+  if (Attributes == NULL && Supported == NULL) {
+    return EFI_INVALID_PARAMETER;
+  }
+  ///
+  /// Set the return value for Supported and Attributes
+  ///
+  if (Supported) {
+    *Supported = PrivateData->Supports;
+  }
+
+  if (Attributes) {
+    *Attributes = PrivateData->Attributes;
+  }
+
+  return EFI_SUCCESS;
+}
+
+/**
+  Sets attributes for a resource range on a PCI root bridge.
+
+  @param[in]       This            - A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
+  @param[in]       Attributes      - The mask of attributes to set. If the attribute bit
+                                     MEMORY_WRITE_COMBINE, MEMORY_CACHED, or
+                                     MEMORY_DISABLE is set, then the resource range is specified by
+                                     ResourceBase and ResourceLength. If
+                                     MEMORY_WRITE_COMBINE, MEMORY_CACHED, and
+                                     MEMORY_DISABLE are not set, then ResourceBase and
+                                     ResourceLength are ignored, and may be NULL.
+  @param[in, out]  ResourceBase    - A pointer to the base address of the resource range to be modified
+                                     by the attributes specified by Attributes.
+  @param[in, out]  ResourceLength  - A pointer to the length of the resource range to be modified by the
+                                     attributes specified by Attributes.
+
+  @retval  EFI_SUCCESS     - The current configuration of this PCI root bridge was returned in Resources.
+  @retval  EFI_UNSUPPORTED - The current configuration of this PCI root bridge could not be retrieved.
+**/
+EFI_STATUS
+EFIAPI
+RootBridgeIoSetAttributes (
+  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL  *This,
+  IN     UINT64                           Attributes,
+  IN OUT UINT64                           *ResourceBase,
+  IN OUT UINT64                           *ResourceLength
+  )
+{
+  PCI_ROOT_BRIDGE_INSTANCE  *PrivateData;
+
+  PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (This);
+  if (Attributes) {
+    if ((Attributes & (~(PrivateData->Supports))) != 0) {
+      return EFI_UNSUPPORTED;
+    }
+  }
+
+  if (Attributes == PrivateData->Attributes) {
+    return EFI_SUCCESS;
+  }
+  ///
+  /// It is just a trick for some attribute can only be enabled or disabled
+  /// otherwise it can impact on other devices
+  ///
+  PrivateData->Attributes = Attributes;
+  return EFI_SUCCESS;
+}
+
+/**
+  Retrieves the current resource settings of this PCI root bridge in the form of a set of ACPI 2.0
+  resource descriptors.
+
+  @param[in]   This        - A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
+  @param[out]  Resources   - A pointer to the ACPI 2.0 resource descriptors that describe the
+                             current configuration of this PCI root bridge. The storage for the
+                             ACPI 2.0 resource descriptors is allocated by this function. The
+                             caller must treat the return buffer as read-only data, and the buffer
+                             must not be freed by the caller.
+
+  @retval  EFI_SUCCESS     - The current configuration of this PCI root bridge was returned in Resources.
+**/
+EFI_STATUS
+EFIAPI
+RootBridgeIoConfiguration (
+  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL  *This,
+  OUT    VOID                             **Resources
+  )
+{
+  PCI_ROOT_BRIDGE_INSTANCE  *PrivateData;
+  UINTN                     Index;
+
+  PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (This);
+  for (Index = 0; Index < TypeMax; Index++) {
+    if (PrivateData->ResAllocNode[Index].Status == ResAllocated) {
+      Configuration.SpaceDesp[Index].AddrRangeMin = PrivateData->ResAllocNode[Index].Base;
+      Configuration.SpaceDesp[Index].AddrRangeMax = PrivateData->ResAllocNode[Index].Base +
+        PrivateData->ResAllocNode[Index].Length -
+        1;
+      Configuration.SpaceDesp[Index].AddrLen = PrivateData->ResAllocNode[Index].Length;
+    }
+  }
+
+  *Resources = &Configuration;
+  return EFI_SUCCESS;
+}
+
+/**
+  Internal help function for read and write PCI configuration space.
+
+  @param[in]   This          - A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
+  @param[in]   Write         - Switch value for Read or Write.
+  @param[in]   Width         - Signifies the width of the memory operations.
+  @param[in]   UserAddress   - The address within the PCI configuration space for the PCI controller.
+  @param[in]   Count         - The number of PCI configuration operations to perform. Bytes
+                               moved is Width size * Count, starting at Address.
+  @param[in, out] UserBuffer - For read operations, the destination buffer to store the results. For
+                               write operations, the source buffer to write data from.
+
+  @retval EFI_SUCCESS            - The data was read from or written to the PCI root bridge.
+  @retval EFI_INVALID_PARAMETER  - Width is invalid for this PCI root bridge or Buffer is NULL.
+**/
+STATIC
+EFI_STATUS
+RootBridgeIoPciRW (
+  IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *This,
+  IN BOOLEAN                                Write,
+  IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,
+  IN UINT64                                 UserAddress,
+  IN UINTN                                  Count,
+  IN OUT VOID                               *UserBuffer
+  )
+{
+  UINT32                                      InStride;
+  UINT32                                      OutStride;
+  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS *PciRbAddr;
+  UINT8                                       *PcieRegAddr;
+
+  if ((Width & 0x03) >= EfiPciWidthUint64) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  InStride  = 1 << (Width & 0x03);
+  OutStride = InStride;
+  if (Width >= EfiCpuIoWidthFifoUint8 && Width <= EfiCpuIoWidthFifoUint64) {
+    InStride = 0;
+  }
+
+  if (Width >= EfiCpuIoWidthFillUint8 && Width <= EfiCpuIoWidthFillUint64) {
+    OutStride = 0;
+  }
+
+  PciRbAddr = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS *) &UserAddress;
+  PcieRegAddr = (UINT8 *) MmPciAddress (
+                            0,  /// No segment support
+                            PciRbAddr->Bus,
+                            PciRbAddr->Device,
+                            PciRbAddr->Function,
+                            0   /// Register is added next
+                            );
+
+  ///
+  /// Add the register offset to the address
+  ///
+  if (PciRbAddr->ExtendedRegister != 0) {
+    PcieRegAddr += PciRbAddr->ExtendedRegister;
+  } else {
+    PcieRegAddr += PciRbAddr->Register;
+  }
+
+  while (Count) {
+    if (Write) {
+      This->Mem.Write (This, Width, (UINTN) PcieRegAddr, 1, UserBuffer);
+    } else {
+      This->Mem.Read (This, Width, (UINTN) PcieRegAddr, 1, UserBuffer);
+    }
+
+    UserBuffer = ((UINT8 *) UserBuffer) + OutStride;
+    PcieRegAddr += InStride;
+    Count -= 1;
+  }
+
+  return EFI_SUCCESS;
+}
diff --git a/ReferenceCode/Chipset/SystemAgent/Ppi/IntelSaPpiLib.inf b/ReferenceCode/Chipset/SystemAgent/Ppi/IntelSaPpiLib.inf
new file mode 100644
index 0000000..4b3fb06
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/Ppi/IntelSaPpiLib.inf
@@ -0,0 +1,53 @@
+## @file
+#  Component description file for the PEI protocol library
+#
+#@copyright
+#  Copyright (c)  1999 - 2012 Intel Corporation. All rights reserved
+#  This software and associated documentation (if any) is furnished
+#  under a license and may only be used or copied in accordance
+#  with the terms of the license. Except as permitted by such
+#  license, no part of this software or documentation may be
+#  reproduced, stored in a retrieval system, or transmitted in any
+#  form or by any means without the express written consent of
+#  Intel Corporation.
+#
+#  This file contains a 'Sample Driver' and is licensed as such
+#  under the terms of your license agreement with Intel or your
+#  vendor.  This file may be modified by the user, subject to
+#  the additional terms of the license agreement
+#
+
+
+[defines]
+BASE_NAME       = IntelSaPpiLib
+COMPONENT_TYPE  = LIBRARY
+
+[sources.common]
+  SsaPeiInit/SsaPeiInit.c
+  SsaPeiInit/SsaPeiInit.h
+  SaPlatformPolicy/SaPlatformPolicy.c
+  SaPlatformPolicy/SaPlatformPolicy.h
+  SaPeiInit/SaPeiInit.c
+  SaPeiInit/SaPeiInit.h
+
+[includes.common]
+  $(EFI_SOURCE)
+  $(EDK_SOURCE)/Foundation
+  $(EDK_SOURCE)/Foundation/Efi
+  $(EDK_SOURCE)/Foundation/Efi/Include
+  $(EDK_SOURCE)/Foundation/Framework
+  $(EDK_SOURCE)/Foundation/Framework/Include
+  $(EDK_SOURCE)/Foundation/Include
+  $(EDK_SOURCE)/Foundation/Include/IndustryStandard
+  $(EDK_SOURCE)/Foundation/Include/Pei
+  $(EDK_SOURCE)/Foundation/Library/Pei/Include
+  $(EDK_SOURCE)/Foundation/Library/Dxe/Include
+  $(EFI_SOURCE)/$(PROJECT_SA_ROOT)
+  $(EDK_SOURCE)/Foundation/Library/EdkIIGlueLib/Include
+  $(EFI_SOURCE)/$(PROJECT_SA_ROOT)/$(PROJECT_SA_MRC)/Pei/Source/Api
+  $(EFI_SOURCE)/$(PROJECT_SA_ROOT)/$(PROJECT_SA_MRC)/Pei/Source/Include
+  $(EFI_SOURCE)/$(PROJECT_SA_ROOT)/$(PROJECT_SA_MRC)/Pei/Source/Include/MrcRegisters
+  $(EFI_SOURCE)/$(PROJECT_SA_ROOT)/Include
+
+[nmake.common]
+C_STD_INCLUDE=
diff --git a/ReferenceCode/Chipset/SystemAgent/Ppi/SaPeiInit/SaPeiInit.c b/ReferenceCode/Chipset/SystemAgent/Ppi/SaPeiInit/SaPeiInit.c
new file mode 100644
index 0000000..50530ed
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/Ppi/SaPeiInit/SaPeiInit.c
@@ -0,0 +1,40 @@
+/** @file
+  Interface definition between MRC and SaInitPeim driver.
+
+@copyright
+  Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement
+**/
+
+///
+/// External include files do NOT need to be explicitly specified in real EDKII
+/// environment
+///
+#if !defined(EDK_RELEASE_VERSION) || (EDK_RELEASE_VERSION < 0x00020000)
+#include "EdkIIGluePeim.h"
+#endif
+
+#include "SaPeiInit.h"
+
+///
+/// PPI GUID definition
+///
+EFI_GUID  gSaPeiInitPpiGuid = SA_PEI_INIT_PPI_GUID;
+
+///
+/// PPI description
+///
+EFI_GUID_STRING(&gSaPeiInitPpiGuid, "SA PEI Init PPI", "SA PEI Initialization PPI");
diff --git a/ReferenceCode/Chipset/SystemAgent/Ppi/SaPeiInit/SaPeiInit.h b/ReferenceCode/Chipset/SystemAgent/Ppi/SaPeiInit/SaPeiInit.h
new file mode 100644
index 0000000..b82348c
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/Ppi/SaPeiInit/SaPeiInit.h
@@ -0,0 +1,37 @@
+/** @file
+  Interface definition between MRC and SaInitPeim driver.
+
+@copyright
+  Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement
+**/
+#ifndef _SA_PEI_INIT_H_
+#define _SA_PEI_INIT_H_
+
+///
+/// Define the SA PEI Init PPI GUID
+///
+#define SA_PEI_INIT_PPI_GUID \
+  { \
+    0x9ea8911, 0xbe0d, 0x4230, 0xa0, 0x3, 0xed, 0xc6, 0x93, 0xb4, 0x8e, 0x11 \
+  }
+
+///
+/// Extern the GUID for PPI users.
+///
+extern EFI_GUID gSaPeiInitPpiGuid;
+
+#endif
diff --git a/ReferenceCode/Chipset/SystemAgent/Ppi/SaPlatformPolicy/SaPlatformPolicy.c b/ReferenceCode/Chipset/SystemAgent/Ppi/SaPlatformPolicy/SaPlatformPolicy.c
new file mode 100644
index 0000000..34dc03f
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/Ppi/SaPlatformPolicy/SaPlatformPolicy.c
@@ -0,0 +1,32 @@
+/** @file
+  Interface definition details between MRC and platform drivers during PEI phase.
+
+@copyright
+  Copyright (c) 2010 - 2012 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement
+**/
+#include "Tiano.h"
+#include "SaPlatformPolicy.h"
+
+///
+/// PPI GUID definition
+///
+EFI_GUID  gSaPlatformPolicyPpiGuid = SA_PLATFORM_POLICY_PPI_GUID;
+
+///
+/// PPI description
+///
+EFI_GUID_STRING(&gSaPlatformPolicyPpiGuid, "SaPlatformPolicy", "System Agent Platform Policy PPI");
diff --git a/ReferenceCode/Chipset/SystemAgent/Ppi/SaPlatformPolicy/SaPlatformPolicy.h b/ReferenceCode/Chipset/SystemAgent/Ppi/SaPlatformPolicy/SaPlatformPolicy.h
new file mode 100644
index 0000000..d70d5da
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/Ppi/SaPlatformPolicy/SaPlatformPolicy.h
@@ -0,0 +1,698 @@
+/** @file
+  Interface definition details between MRC and platform drivers during PEI phase.
+
+@copyright
+  Copyright (c) 2010 - 2013 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement
+**/
+#ifndef _SA_PLATFORM_POLICY_PPI_H_
+#define _SA_PLATFORM_POLICY_PPI_H_
+
+#include "MrcApi.h"
+#include "SaAccess.h"
+
+///
+/// SA Platform Policy for PEI phase {573EAF99-F445-46b5-A5D5-BC4A933598F3}
+///
+#define SA_PLATFORM_POLICY_PPI_GUID \
+  { \
+    0x573eaf99, 0xf445, 0x46b5, 0xa5, 0xd5, 0xbc, 0x4a, 0x93, 0x35, 0x98, 0xf3 \
+  }
+
+///
+/// Extern the GUID for protocol users.
+///
+extern EFI_GUID gSaPlatformPolicyPpiGuid;
+
+///
+/// PPI revision number
+/// Any backwards compatible changes to this PPI will result in an update in the revision number
+/// Major changes will require publication of a new PPI
+///
+/// Revision 1: Initial version.
+///             Included in SA RC 0.5.0.0
+///
+#define SA_PLATFORM_POLICY_PPI_REVISION   1
+///
+/// Revision 2: Added PCIE_CONFIGURATION.PegGen3PresetSearchVoltageMarginSteps
+///                   PCIE_CONFIGURATION.PegGen3PresetSearchVoltageStartMargin
+///                   PCIE_CONFIGURATION.PegGen3PresetSearchFavorTiming
+///                   PCIE_CONFIGURATION.PegDataPtr
+///                   PCIE_CONFIGURATION.PegGen3ForcePresetSearch
+///                   PCIE_CONFIGURATION.InitPcieAspmAfterOprom
+///                   PCIE_CONFIGURATION.SaIotrapSmiAddress
+///             Added MEMORY_CONFIGURATION.DqPinsInterleaved
+///                   MEMORY_CONFIGURATION.DIMMODTT1D
+///                   MEMORY_CONFIGURATION.WRSRT
+///                   MEMORY_CONFIGURATION.DIMMRONT
+///
+#define SA_PLATFORM_POLICY_PPI_REVISION_2 2
+///
+/// Revision 3: Added SA_PLATFORM_DATA.SgMode
+///                   SA_PLATFORM_DATA.SgSubSystemId
+///             Added SA_PLATFORM_POLICY_PPI.SgGpioData
+///                   PCIE_CONFIGURATION.PegGpioData
+///                   PCIE_CONFIGURATION.PegGen3PresetSearchErrorTarget
+///                   PCIE_CONFIGURATION.RxCEMLoopback
+///                   PCIE_CONFIGURATION.RxCEMLoopbackLane
+///                   PCIE_CONFIGURATION.Gen3RxCtleP[SA_PEG_MAX_LANE >> 1]
+///             Obsoleted PCIE_CONFIGURATION.PegGen3PresetSearchMarginSteps
+///                       PCIE_CONFIGURATION.PegGen3PresetSearchVoltageMarginSteps
+///                       PCIE_CONFIGURATION.PegGen3PresetSearchFavorTiming
+///                       MEMORY_CONFIGURATION.ForceColdReset
+///             Added OVERCLOCKING_CONFIGURATION.GtVoltageMode
+///                   OVERCLOCKING_CONFIGURATION.OcSupport
+///                   MEMORY_CONFIGURATION.MrcUltPoSafeConfig
+///
+#define SA_PLATFORM_POLICY_PPI_REVISION_3 3
+///
+/// Revision 4: Added MEMORY_CONFIGURATION.CMDVC
+///                   MEMORY_CONFIGURATION.PowerDownMode
+///                   MEMORY_CONFIGURATION.PwdwnIdleCounter
+///                   MEMORY_CONFIGURATION.RankInterleave
+///                   MEMORY_CONFIGURATION.EnhancedInterleave
+///                   MEMORY_CONFIGURATION.WeaklockEn;
+///                   MEMORY_CONFIGURATION.EnCmdRate
+///                   MEMORY_CONFIGURATION.CmdTriStateDis
+///
+#define SA_PLATFORM_POLICY_PPI_REVISION_4 4
+///
+/// Revision 5: Added MEMORY_CONFIGURATION.BClkFrequency
+///                   OVERCLOCKING_CONFIGURATION.IoaVoltageOffset
+///                   OVERCLOCKING_CONFIGURATION.IodVoltageOffset
+///
+#define SA_PLATFORM_POLICY_PPI_REVISION_5 5
+///
+/// Revision 6: Added MEMORY_CONFIGURATION.tRPab
+///                   MEMORY_CONFIGURATION.ALIASCHK
+///             Obsoleted MEMORY_CONFIGURATION.WRXTCT
+///                       PCIE_CONFIGURATION.PegGen3EqualizationPhase2
+///             Added GT_CONFIGURATION.GttMmAdr
+///
+#define SA_PLATFORM_POLICY_PPI_REVISION_6 6
+///
+/// Revision 7: Obsoleted MEMORY_CONFIGURATION.B2BXTT
+///                       MEMORY_CONFIGURATION.C2CXTT
+///             Added     MEMORY_CONFIGURATION.MemoryTrace
+///
+#define SA_PLATFORM_POLICY_PPI_REVISION_7 7
+///
+/// Revision 8: Added PCIE_CONFIGURATION.PowerDownUnusedBundles[SA_PEG_MAX_FUN]
+///
+#define SA_PLATFORM_POLICY_PPI_REVISION_8 8
+///
+/// Revision 9: Added SA_PLATFORM_DATA.IedSize
+///                   MEMORY_CONFIGURATION.RefreshRate2x
+///                   MEMORY_CONFIGURATION.ChHashEnable
+///                   MEMORY_CONFIGURATION.ChHashMask
+///                   MEMORY_CONFIGURATION.ChHashInterleaveBit
+///
+#define SA_PLATFORM_POLICY_PPI_REVISION_9 9
+///
+/// Revision 10: Added MEMORY_CONFIGURATION.EnableExtts
+///                    MEMORY_CONFIGURATION.EnableCltm
+///                    MEMORY_CONFIGURATION.EnableOltm
+///                    MEMORY_CONFIGURATION.EnablePwrDn
+///                    MEMORY_CONFIGURATION.EnablePwrDnLpddr
+///                    MEMORY_CONFIGURATION.Refresh2X
+///                    MEMORY_CONFIGURATION.LpddrThermalSensor
+///                    MEMORY_CONFIGURATION.LockPTMregs
+///                    MEMORY_CONFIGURATION.UserPowerWeightsEn
+///                    MEMORY_CONFIGURATION.EnergyScaleFact
+///                    MEMORY_CONFIGURATION.RaplPwrFlCh1
+///                    MEMORY_CONFIGURATION.RaplPwrFlCh0
+///                    MEMORY_CONFIGURATION.RaplLim2Lock
+///                    MEMORY_CONFIGURATION.RaplLim2WindX
+///                    MEMORY_CONFIGURATION.RaplLim2WindY
+///                    MEMORY_CONFIGURATION.RaplLim2Ena
+///                    MEMORY_CONFIGURATION.RaplLim2Pwr
+///                    MEMORY_CONFIGURATION.RaplLim1WindX
+///                    MEMORY_CONFIGURATION.RaplLim1WindY
+///                    MEMORY_CONFIGURATION.RaplLim1Ena
+///                    MEMORY_CONFIGURATION.RaplLim1Pwr
+///                    MEMORY_CONFIGURATION.WarmThresholdCh0Dimm0
+///                    MEMORY_CONFIGURATION.WarmThresholdCh0Dimm1
+///                    MEMORY_CONFIGURATION.WarmThresholdCh1Dimm0
+///                    MEMORY_CONFIGURATION.WarmThresholdCh1Dimm1
+///                    MEMORY_CONFIGURATION.HotThresholdCh0Dimm0
+///                    MEMORY_CONFIGURATION.HotThresholdCh0Dimm1
+///                    MEMORY_CONFIGURATION.HotThresholdCh1Dimm0
+///                    MEMORY_CONFIGURATION.HotThresholdCh1Dimm1
+///                    MEMORY_CONFIGURATION.WarmBudgetCh0Dimm0
+///                    MEMORY_CONFIGURATION.WarmBudgetCh0Dimm1
+///                    MEMORY_CONFIGURATION.WarmBudgetCh1Dimm0
+///                    MEMORY_CONFIGURATION.WarmBudgetCh1Dimm1
+///                    MEMORY_CONFIGURATION.HotBudgetCh0Dimm0
+///                    MEMORY_CONFIGURATION.HotBudgetCh0Dimm1
+///                    MEMORY_CONFIGURATION.HotBudgetCh1Dimm0
+///                    MEMORY_CONFIGURATION.HotBudgetCh1Dimm1
+///                    MEMORY_CONFIGURATION.IdleEnergyCh0Dimm1
+///                    MEMORY_CONFIGURATION.IdleEnergyCh0Dimm0
+///                    MEMORY_CONFIGURATION.PdEnergyCh0Dimm1
+///                    MEMORY_CONFIGURATION.PdEnergyCh0Dimm0
+///                    MEMORY_CONFIGURATION.ActEnergyCh0Dimm1
+///                    MEMORY_CONFIGURATION.ActEnergyCh0Dimm0
+///                    MEMORY_CONFIGURATION.RdEnergyCh0Dimm1
+///                    MEMORY_CONFIGURATION.RdEnergyCh0Dimm0
+///                    MEMORY_CONFIGURATION.WrEnergyCh0Dimm1
+///                    MEMORY_CONFIGURATION.WrEnergyCh0Dimm0
+///                    MEMORY_CONFIGURATION.IdleEnergyCh1Dimm1
+///                    MEMORY_CONFIGURATION.IdleEnergyCh1Dimm0
+///                    MEMORY_CONFIGURATION.PdEnergyCh1Dimm1
+///                    MEMORY_CONFIGURATION.PdEnergyCh1Dimm0
+///                    MEMORY_CONFIGURATION.ActEnergyCh1Dimm1
+///                    MEMORY_CONFIGURATION.ActEnergyCh1Dimm0
+///                    MEMORY_CONFIGURATION.RdEnergyCh1Dimm1
+///                    MEMORY_CONFIGURATION.RdEnergyCh1Dimm0
+///                    MEMORY_CONFIGURATION.WrEnergyCh1Dimm1
+///                    MEMORY_CONFIGURATION.WrEnergyCh1Dimm0
+///                    MEMORY_CONFIGURATION.SrefCfgEna
+///                    MEMORY_CONFIGURATION.SrefCfgIdleTmr
+///                    MEMORY_CONFIGURATION.ThrtCkeMinDefeat
+///                    MEMORY_CONFIGURATION.ThrtCkeMinTmr
+///                    MEMORY_CONFIGURATION.ThrtCkeMinDefeatLpddr
+///                    MEMORY_CONFIGURATION.ThrtCkeMinTmrLpddr
+#define SA_PLATFORM_POLICY_PPI_REVISION_10 10
+///
+/// Revision 11: Added MEMORY_CONFIGURATION.CAVrefCtlOffset
+///                    MEMORY_CONFIGURATION.Ch0VrefCtlOffset
+///                    MEMORY_CONFIGURATION.Ch1VrefCtlOffset
+///                    MEMORY_CONFIGURATION.Ch0ClkPiCodeOffset
+///                    MEMORY_CONFIGURATION.Ch1ClkPiCodeOffset
+///                    MEMORY_CONFIGURATION.Ch0RcvEnOffset
+///                    MEMORY_CONFIGURATION.Ch0RxDqsOffset
+///                    MEMORY_CONFIGURATION.Ch0TxDqOffset
+///                    MEMORY_CONFIGURATION.Ch0TxDqsOffset
+///                    MEMORY_CONFIGURATION.Ch0VrefOffset
+///                    MEMORY_CONFIGURATION.Ch1RcvEnOffset
+///                    MEMORY_CONFIGURATION.Ch1RxDqsOffset
+///                    MEMORY_CONFIGURATION.Ch1TxDqOffset
+///                    MEMORY_CONFIGURATION.Ch1TxDqsOffset
+///                    MEMORY_CONFIGURATION.Ch1VrefOffset
+///                    PCIE_CONFIGURATION.PegComplianceTestingMode
+///                    MEMORY_CONFIGURATION.MaxRttWr
+#define SA_PLATFORM_POLICY_PPI_REVISION_11 11
+///
+/// Revision 12: Added MEMORY_CONFIGURATION.RCVENC1D
+///
+#define SA_PLATFORM_POLICY_PPI_REVISION_12 12
+///
+/// Revision 13: Added MEMORY_CONFIGURATION.MCREGOFFSET
+///
+#define SA_PLATFORM_POLICY_PPI_REVISION_13 13
+///
+/// Revision 14: Added GT_CONFIGURATION.PanelPowerEnable
+///          Obsoleted MEMORY_CONFIGURATION.CAVrefCtlOffset
+///                    MEMORY_CONFIGURATION.Ch0VrefCtlOffset
+///                    MEMORY_CONFIGURATION.Ch1VrefCtlOffset
+///                    MEMORY_CONFIGURATION.Ch0ClkPiCodeOffset
+///                    MEMORY_CONFIGURATION.Ch1ClkPiCodeOffset
+///                    MEMORY_CONFIGURATION.Ch0RcvEnOffset
+///                    MEMORY_CONFIGURATION.Ch0RxDqsOffset
+///                    MEMORY_CONFIGURATION.Ch0TxDqOffset
+///                    MEMORY_CONFIGURATION.Ch0TxDqsOffset
+///                    MEMORY_CONFIGURATION.Ch0VrefOffset
+///                    MEMORY_CONFIGURATION.Ch1RcvEnOffset
+///                    MEMORY_CONFIGURATION.Ch1RxDqsOffset
+///                    MEMORY_CONFIGURATION.Ch1TxDqOffset
+///                    MEMORY_CONFIGURATION.Ch1TxDqsOffset
+///                    MEMORY_CONFIGURATION.Ch1VrefOffset
+///                    MEMORY_CONFIGURATION.MCREGOFFSET
+///
+#define SA_PLATFORM_POLICY_PPI_REVISION_14 14
+///
+/// Revision 15: Added: MEMORY_CONFIGURATION.RMC
+///
+#define SA_PLATFORM_POLICY_PPI_REVISION_15 15
+
+#ifndef SA_MC_MAX_SOCKETS
+#define SA_MC_MAX_SOCKETS 4
+#endif
+
+#define S3_TIMING_DATA_LEN          9
+#define S3_READ_TRAINING_DATA_LEN   16
+#define S3_WRITE_TRAINING_DATA_LEN  12
+#define SAVE_PRESET_SEARCH_DATA_LEN 3
+
+#ifndef S3_RESTORE_DATA_LEN
+#define S3_RESTORE_DATA_LEN (S3_TIMING_DATA_LEN + S3_READ_TRAINING_DATA_LEN + S3_WRITE_TRAINING_DATA_LEN)
+#endif // S3_RESTORE_DATA_LEN
+
+#pragma pack(1)
+///
+/// SA Platform Data Structure
+///
+typedef struct {
+  UINT8   SpdAddressTable[SA_MC_MAX_SOCKETS];///< Memory DIMMs' SPD address for reading SPD data
+  UINT32  MchBar;                            ///< Address of System Agent MCHBAR
+  UINT32  DmiBar;                            ///< Address of System Agent DMIBAR
+  UINT32  EpBar;                             ///< Address of System Agent EPBAR
+  UINT32  PciExpressBar;                     ///< Address of System Agent PCI EXPRESS BAR
+  UINT32  SmbusBar;                          ///< Address of System Agent SMBUS BAR
+  UINT32  GdxcBar;                           ///< Address of System Agent GDXCBAR
+  UINT32  TsegSize;                          ///< Size of TSEG in bytes
+  UINT8   UserBd;                            ///< Mobile - 0; Desktop/UpServer - 1
+  UINT8   FastBoot;                          ///< FastBoot option: enable or disable MRC FastBoot feature
+  UINT32  EdramBar;                          ///< Address of System Agent EDRAMBAR. Default of 0xfed80000
+  UINT16  BoardId;                           ///< Platform Board ID
+  UINT8   SgMode;                            ///< SgMode (0=Disabled, 1=SG Muxed, 2=SG Muxless, 3=PEG)
+  UINT16  SgSubSystemId;                     ///< Switchable Graphics Subsystem ID
+  UINT32  IedSize;                           ///< Size of IED region in bytes
+//AMI_OVERRIDE >> 
+  UINT8 PXFixedDynamicMode;
+//AMI_OVERRIDE <<
+} SA_PLATFORM_DATA;
+
+///
+/// GT Configuration
+///
+typedef struct {
+  UINT16  MmioSize;           ///< Reserved MMIO space for Graphics
+  UINT16  GttSize;            ///< Gtt Memory size of IGD
+  UINT8   IgdDvmt50PreAlloc;  ///< Pre-allocated memory for IGD
+  UINT8   InternalGraphics;   ///< Control for enabling/disabling iGfx device
+  UINT8   PrimaryDisplay;     ///< Selection of the primary display device (iGFX, External PCIe or PCI Graphics)
+  UINT8   ApertureSize;       ///< Graphics aperture size
+  UINT32  GttMmAdr;           ///< Address of System Agent GTTMMADR
+  UINT8   PanelPowerEnable;   ///< Control for enabling/disabling VDD force bit (Required only for early enabling of eDP panel)
+} GT_CONFIGURATION;
+
+///
+/// SA_SPD
+///
+typedef enum {
+  Default,        ///< 0, Default SPD
+  UserDefined,    ///< 1, User Defined profile
+  XMPProfile1,    ///< 2, XMP Profile 1
+  XMPProfile2     ///< 3, XMP Profile 2
+} SA_SPD;
+
+///
+/// Memory Configuration
+///
+typedef struct {
+  UINT8   EccSupport;             ///< Ecc Support option - for Desktop only
+  UINT16  DdrFreqLimit;           ///< Memory Frequency setting
+  UINT8   MaxTolud;               ///< Maximum top of memory size below 4G
+  SA_SPD  SpdProfileSelected;     ///< SPD XMP profile selection - for XMP supported DIMM
+  UINT16  tCL;                    ///< User defined Memory Timing tCL value, it's valid when SpdProfileSelected is CUSTOM_PROFILE
+  UINT16  tRCD;                   ///< User defined Memory Timing tRCD value, it's valid when SpdProfileSelected is CUSTOM_PROFILE
+  UINT16  tRP;                    ///< User defined Memory Timing tRP value, it's valid when SpdProfileSelected is CUSTOM_PROFILE
+  UINT16  tRAS;                   ///< User defined Memory Timing tRAS value, it's valid when SpdProfileSelected is CUSTOM_PROFILE
+  UINT8   NModeSupport;           ///< Memory N Mode Support - Enable user to select Auto, 1N or 2N
+  UINT8   ScramblerSupport;       ///< Memory scrambler support
+  UINT16  tWR;                    ///< User defined Memory Timing tWR value, it's valid when SpdProfileSelected is CUSTOM_PROFILE
+  UINT16  tRFC;                   ///< User defined Memory Timing tRFC value, it's valid when SpdProfileSelected is CUSTOM_PROFILE
+  UINT16  tRRD;                   ///< User defined Memory Timing tRRD value, it's valid when SpdProfileSelected is CUSTOM_PROFILE
+  UINT16  tWTR;                   ///< User defined Memory Timing tWTR value, it's valid when SpdProfileSelected is CUSTOM_PROFILE
+  UINT16  tRTP;                   ///< User defined Memory Timing tRP value, it's valid when SpdProfileSelected is CUSTOM_PROFILE
+  UINT16  tRC;                    ///< User defined Memory Timing tRC value, it's valid when SpdProfileSelected is CUSTOM_PROFILE
+  UINT16  tFAW;                   ///< User defined Memory Timing tFAW value, it's valid when SpdProfileSelected is CUSTOM_PROFILE
+  UINT16  tCWL;                   ///< User defined Memory Timing tCWL value, it's valid when SpdProfileSelected is CUSTOM_PROFILE
+  UINT16  tREFI;                  ///< User defined Memory Timing tREFI value, it's valid when SpdProfileSelected is CUSTOM_PROFILE
+  //
+  // Thermal Management
+  //
+  UINT8   ThermalManagement;      ///< Memory Thermal Management Support - Enable/Disable
+  UINT8   PeciInjectedTemp;       ///< Enable/Disable memory temperatures to be injected to the processor via PECI
+  UINT8   ExttsViaTsOnBoard;      ///< Enable/Disable routing TS-on-Board's ALERT# and THERM# to EXTTS# pins on the PCH
+  UINT8   ExttsViaTsOnDimm;       ///< Enable/Disable routing TS-on-DIMM's ALERT# to EXTTS# pin on the PCH
+  UINT8   VirtualTempSensor;      ///< Enable/Disable Virtual Temperature Sensor (VTS)
+  BOOLEAN ForceColdReset;         ///< @deprecated since revision 3
+  ///
+  /// Disables a DIMM slot in the channel even if a DIMM is present. Array index represents
+  /// the channel number (0 = channel 0, 1 = channel 1). 0x0 = DIMM 0 and DIMM 1 enabled.
+  ///
+  ///   0x1 = DIMM 0 disabled, DIMM 1 enabled.
+  ///   0x2 = DIMM 0 enabled, DIMM 1 disabled.
+  ///   0x3 = DIMM 0 and DIMM 1 disabled (will disable the whole channel)
+  ///
+  UINT8   DisableDimmChannel[SA_MC_MAX_CHANNELS];
+  BOOLEAN RemapEnable;             ///< This option is used to control whether to enable/disable memory remap above 4GB
+  ///
+  /// Sets the serial debug message level.
+  ///   0x00 = Disabled
+  ///   0x01 = Errors only.
+  ///   0x02 = Errors and Warnings
+  ///   0x03 = Errors, Warnings, and Info
+  ///   0x04 = Errors, Warnings, Info, and Events
+  ///   0x05 = Displays Memory Init Execution Time Summary only.
+  ///
+  UINT8   SerialDebug;
+
+  UINT8   McLock;                    ///< Enable/Disable memory configuration register locking.
+  UINT8   GdxcEnable;                ///< Enable/Disable GDXC debug support feature.
+  UINT8   GdxcIotSize;               ///< GDXC IOT Size in 8MB granularity
+  UINT8   GdxcMotSize;               ///< GDXC MOT Size in 8MB granularity
+  //
+  // Training Algorithms
+  //
+  UINT8   ECT;                       ///< Enable/Disable Early Command Training. Note it is not recommended to change this setting from the default value
+  UINT8   SOT;                       ///< Enable/Disable Sense Amp Offset Training. Note it is not recommended to change this setting from the default value
+  UINT8   RDMPRT;                    ///< Enable/Disable Read MPR Training. Note it is not recommended to change this setting from the default value
+  UINT8   RCVET;                     ///< Enable/Disable Receive Enable Training. Note it is not recommended to change this setting from the default value
+  UINT8   JWRL;                      ///< Enable/Disable JEDEC Write Leveling Training. Note it is not recommended to change this setting from the default value
+  UINT8   FWRL;                      ///< Enable/Disable Functional Write Leveling Training. Note it is not recommended to change this setting from the default value
+  UINT8   WRTC1D;                    ///< Enable/Disable 1D Write Timing Centering Training. Note it is not recommended to change this setting from the default value
+  UINT8   RDTC1D;                    ///< Enable/Disable 1D Read Timing Centering Training. Note it is not recommended to change this setting from the default value
+  UINT8   DIMMODTT;                  ///< Enable/Disable DIMM ODT Training. Note it is not recommended to change this setting from the default value
+  UINT8   WRDST;                     ///< Enable/Disable Write Drive Strength Training. Note it is not recommended to change this setting from the default value
+  UINT8   WREQT;                     ///< Enable/Disable Write Equalization Training. Note it is not recommended to change this setting from the default value
+  UINT8   WRXTCT;                    ///< @deprecated since revision 6
+  UINT8   RDODTT;                    ///< Enable/Disable Read ODT Training. Note it is not recommended to change this setting from the default value
+  UINT8   RDEQT;                     ///< Enable/Disable Read Equalization Training. Note it is not recommended to change this setting from the default value
+  UINT8   RDAPT;                     ///< Enable/Disable Read Amplifier Power Training. Note it is not recommended to change this setting from the default value
+  UINT8   WRTC2D;                    ///< Enable/Disable 2D Write Timing Centering Training. Note it is not recommended to change this setting from the default value
+  UINT8   RDTC2D;                    ///< Enable/Disable 2D Read Timing Centering Training. Note it is not recommended to change this setting from the default value
+  UINT8   WRVC2D;                    ///< Enable/Disable 2D Write Voltage Centering Training. Note it is not recommended to change this setting from the default value
+  UINT8   RDVC2D;                    ///< Enable/Disable 2D Read Voltage Centering Training. Note it is not recommended to change this setting from the default value
+  UINT8   B2BXTT;                    ///< @deprecated since revision 7
+  UINT8   C2CXTT;                    ///< @deprecated since revision 7
+  UINT8   LCT;                       ///< Enable/Disable Late Command Training. Note it is not recommended to change this setting from the default value
+  UINT8   RTL;                       ///< Enable/Disable Round Trip Latency function. Note it is not recommended to change this setting from the default value
+  UINT8   TAT;                       ///< Enable/Disable Turn Around Time function. Note it is not recommended to change this setting from the default value
+  UINT8   RMT;                       ///< Enable/Disable Rank Margin Tool function
+  UINT8   MEMTST;                    ///< Enable/Disable Memory Test function
+
+  UINT16  DDR3Voltage;               ///< Indicates if platform supports DDR3L DIMMs
+  UINT32  DDR3VoltageWaitTime;       ///< Amount of time in microseconds to wait for the DDR3 voltage to change from 1.5V to 1.35V
+
+  BOOLEAN RmtBdatEnable;             ///< Enable/Disable creating the BIOS DATA ACPI tables and populating with the RMT data
+  ///
+  /// Selects the DDR base reference clock.
+  ///   0x00 = Auto
+  ///   0x01 = 133MHz
+  ///   0x02 = 100MHz
+  ///
+  UINT8   RefClk;
+  ///
+  /// Selects the ratio to multiply the reference clock by for the DDR frequency.
+  ///   0x00 = Auto
+  ///   0x03 through 0x0A are valid values, all others are invalid.
+  ///
+  UINT8   Ratio;
+  UINT8   MrcTimeMeasure;        ///< Enables serial debug level to display the MRC execution times only
+  UINT8   MrcFastBoot;           ///< Enables the MRC fast boot path for faster cold boot execution
+  BOOLEAN DqPinsInterleaved;     ///< Interleaving mode of DQ/DQS pins for HSW_ULT which depends on board routing
+  UINT8   DIMMODTT1D;            ///< DIMM ODT 1D training switch
+  UINT8   WRSRT;                 ///< Write Slew Rate traning switch
+  UINT8   DIMMRONT;              ///< DIMM RON training switch
+  BOOLEAN MrcUltPoSafeConfig;    ///< MRC ULT PO Safe Mode
+  UINT8   CMDVC;                 ///< Command Vref Centering
+  UINT8   PowerDownMode;         ///< REVISION_4 - Power Down Mode
+  UINT8   PwdwnIdleCounter;      ///< REVISION_4 - Power Down Mode Idle Counter
+  UINT8   RankInterleave;        ///< REVISION_4 - Rank Interleave Mode
+  UINT8   EnhancedInterleave;    ///< REVISION_4 - Enhanced Interleave Mode
+  UINT8   WeaklockEn;            ///< REVISION_4 - Weak Lock Enable
+  UINT8   EnCmdRate;             ///< REVISION_4 - CMD Rate Enable
+  UINT8   CmdTriStateDis;        ///< REVISION_4 - CMD Tri-State Disable
+  UINT32  BClkFrequency;         ///< REVISION_5 - Base reference clock value, in Hertz.
+  UINT16  tRPab;                 ///< REVISION_6 - User defined Memory Timing tRPab value, it's valid when SpdProfileSelected is CUSTOM_PROFILE
+  UINT8   ALIASCHK;              ///< REVISION_6 - DIMM SPD Alias Check Switch
+  UINT8   MemoryTrace;           ///< REVISION_7 - Memory Trace to second DDR channel using Stacked Mode
+  BOOLEAN RefreshRate2x;         ///< REVISION_9 - 2x Refresh Rate Enable
+  UINT8   ChHashEnable;          ///< REVISION_9 - Channel Hash Enable
+  UINT16  ChHashMask;            ///< REVISION_9 - Channel Hash Mask
+  UINT8   ChHashInterleaveBit;   ///< REVISION_9 - Channel Hash Enable
+  UINT8   EnableExtts;           ///< REVISION_10 - Enable Extts
+  UINT8   EnableCltm;            ///< REVISION_10 - Enable Closed Loop Thermal Management
+  UINT8   EnableOltm;            ///< REVISION_10 - Enable Open Loop Thermal Management
+  UINT8   EnablePwrDn;           ///< REVISION_10 - Enable Power Down
+  UINT8   EnablePwrDnLpddr;      ///< REVISION_10 - Enable Power Down for LPDDR
+  UINT8   Refresh2X;             ///< REVISION_10 - Refresh 2x
+  UINT8   LpddrThermalSensor;    ///< REVISION_10 - Lpddr Thermal Sensore
+  UINT8   LockPTMregs;           ///< REVISION_10 - Lock PCU Thermal Management registers
+  UINT8   UserPowerWeightsEn;    ///< REVISION_10 - Allows user to explicitly set power weight, scale factor, and channel power floor values
+  UINT8   EnergyScaleFact;       ///< REVISION_10 - Energy Scale Factor
+  UINT8   RaplPwrFlCh1;          ///< REVISION_10 - Power Channel 1 Floor value
+  UINT8   RaplPwrFlCh0;          ///< REVISION_10 - Power Channel 0 Floor value
+  UINT8   RaplLim2Lock;          ///< REVISION_10 - Lock DDR_RAPL_LIMIT register
+  UINT8   RaplLim2WindX;         ///< REVISION_10 - Power Limit 2 Time Window X value
+  UINT8   RaplLim2WindY;         ///< REVISION_10 - Power Limit 2 Time Window Y value
+  UINT8   RaplLim2Ena;           ///< REVISION_10 - Enable Power Limit 2
+  UINT16  RaplLim2Pwr;           ///< REVISION_10 - Power Limit 2
+  UINT8   RaplLim1WindX;         ///< REVISION_10 - Power Limit 1 Time Window X value
+  UINT8   RaplLim1WindY;         ///< REVISION_10 - Power Limit 1 Time Window Y value
+  UINT8   RaplLim1Ena;           ///< REVISION_10 - Enable Power Limit 1
+  UINT16  RaplLim1Pwr;           ///< REVISION_10 - Power Limit 1
+  UINT8   WarmThresholdCh0Dimm0; ///< REVISION_10 - Warm Threshold (Channel 0, Dimm 0)
+  UINT8   WarmThresholdCh0Dimm1; ///< REVISION_10 - Warm Threshold (Channel 0, Dimm 1)
+  UINT8   WarmThresholdCh1Dimm0; ///< REVISION_10 - Warm Threshold (Channel 1, Dimm 0)
+  UINT8   WarmThresholdCh1Dimm1; ///< REVISION_10 - Warm Threshold (Channel 1, Dimm 1)
+  UINT8   HotThresholdCh0Dimm0;  ///< REVISION_10 - Hot Threshold (Channel 0, Dimm 0)
+  UINT8   HotThresholdCh0Dimm1;  ///< REVISION_10 - Hot Threshold (Channel 0, Dimm 1)
+  UINT8   HotThresholdCh1Dimm0;  ///< REVISION_10 - Hot Threshold (Channel 1, Dimm 0)
+  UINT8   HotThresholdCh1Dimm1;  ///< REVISION_10 - Hot Threshold (Channel 1, Dimm 1)
+  UINT8   WarmBudgetCh0Dimm0;    ///< REVISION_10 - Warm Budget (Channel 0, Dimm 0)
+  UINT8   WarmBudgetCh0Dimm1;    ///< REVISION_10 - Warm Budget (Channel 0, Dimm 1)
+  UINT8   WarmBudgetCh1Dimm0;    ///< REVISION_10 - Warm Budget (Channel 1, Dimm 0)
+  UINT8   WarmBudgetCh1Dimm1;    ///< REVISION_10 - Warm Budget (Channel 1, Dimm 1)
+  UINT8   HotBudgetCh0Dimm0;     ///< REVISION_10 - Hot Budget (Channel 0, Dimm 0)
+  UINT8   HotBudgetCh0Dimm1;     ///< REVISION_10 - Hot Budget (Channel 0, Dimm 1)
+  UINT8   HotBudgetCh1Dimm0;     ///< REVISION_10 - Hot Budget (Channel 1, Dimm 0)
+  UINT8   HotBudgetCh1Dimm1;     ///< REVISION_10 - Hot Budget (Channel 1, Dimm 1)
+  UINT8   IdleEnergyCh0Dimm1;    ///< REVISION_10 - Idle Energy (Channel 0, Dimm 1)
+  UINT8   IdleEnergyCh0Dimm0;    ///< REVISION_10 - Idle Energy (Channel 0, Dimm 0)
+  UINT8   PdEnergyCh0Dimm1;      ///< REVISION_10 - Power Down Energy (Channel 0, Dimm 1)
+  UINT8   PdEnergyCh0Dimm0;      ///< REVISION_10 - Power Down Energy (Channel 0, Dimm 0)
+  UINT8   ActEnergyCh0Dimm1;     ///< REVISION_10 - Activation Energy (Channel 0, Dimm 1)
+  UINT8   ActEnergyCh0Dimm0;     ///< REVISION_10 - Activation Energy (Channel 0, Dimm 0)
+  UINT8   RdEnergyCh0Dimm1;      ///< REVISION_10 - Read Energy (Channel 0, Dimm 1)
+  UINT8   RdEnergyCh0Dimm0;      ///< REVISION_10 - Read Energy (Channel 0, Dimm 0)
+  UINT8   WrEnergyCh0Dimm1;      ///< REVISION_10 - Write Energy (Channel 0, Dimm 1)
+  UINT8   WrEnergyCh0Dimm0;      ///< REVISION_10 - Write Energy (Channel 0, Dimm 0)
+  UINT8   IdleEnergyCh1Dimm1;    ///< REVISION_10 - Idle Energy (Channel 1, Dimm 1)
+  UINT8   IdleEnergyCh1Dimm0;    ///< REVISION_10 - Idle Energy (Channel 1, Dimm 0)
+  UINT8   PdEnergyCh1Dimm1;      ///< REVISION_10 - Power Down Energy (Channel 1, Dimm 1)
+  UINT8   PdEnergyCh1Dimm0;      ///< REVISION_10 - Power Down Energy (Channel 1, Dimm 0)
+  UINT8   ActEnergyCh1Dimm1;     ///< REVISION_10 - Activation Energy (Channel 1, Dimm 1)
+  UINT8   ActEnergyCh1Dimm0;     ///< REVISION_10 - Activation Energy (Channel 1, Dimm 0)
+  UINT8   RdEnergyCh1Dimm1;      ///< REVISION_10 - Read Energy (Channel 1, Dimm 1)
+  UINT8   RdEnergyCh1Dimm0;      ///< REVISION_10 - Read Energy (Channel 1, Dimm 0)
+  UINT8   WrEnergyCh1Dimm1;      ///< REVISION_10 - Write Energy (Channel 1, Dimm 1)
+  UINT8   WrEnergyCh1Dimm0;      ///< REVISION_10 - Write Energy (Channel 1, Dimm 0)
+  UINT8   SrefCfgEna;            ///< REVISION_10 - Enable Self Refresh
+  UINT16  SrefCfgIdleTmr;        ///< REVISION_10 - Self Refresh idle timer
+  UINT8   ThrtCkeMinDefeat;      ///< REVISION_10 - Throttler CKE min defeature
+  UINT8   ThrtCkeMinTmr;         ///< REVISION_10 - Throttler CKE min timer
+  UINT8   ThrtCkeMinDefeatLpddr; ///< REVISION_10 - Throttler CKE min defeature for LPDDR
+  UINT8   ThrtCkeMinTmrLpddr;    ///< REVISION_10 - Throttler CKE min timer for LPDDR
+  UINT8   CAVrefCtlOffset;       ///< @deprecated since revision 14
+  UINT8   Ch0VrefCtlOffset;      ///< @deprecated since revision 14
+  UINT8   Ch1VrefCtlOffset;      ///< @deprecated since revision 14
+  UINT8   Ch0ClkPiCodeOffset;    ///< @deprecated since revision 14
+  UINT8   Ch1ClkPiCodeOffset;    ///< @deprecated since revision 14
+  UINT8   Ch0RcvEnOffset;        ///< @deprecated since revision 14
+  UINT8   Ch0RxDqsOffset;        ///< @deprecated since revision 14
+  UINT8   Ch0TxDqOffset;         ///< @deprecated since revision 14
+  UINT8   Ch0TxDqsOffset;        ///< @deprecated since revision 14
+  UINT8   Ch0VrefOffset;         ///< @deprecated since revision 14
+  UINT8   Ch1RcvEnOffset;        ///< @deprecated since revision 14
+  UINT8   Ch1RxDqsOffset;        ///< @deprecated since revision 14
+  UINT8   Ch1TxDqOffset;         ///< @deprecated since revision 14
+  UINT8   Ch1TxDqsOffset;        ///< @deprecated since revision 14
+  UINT8   Ch1VrefOffset;         ///< @deprecated since revision 14
+  BOOLEAN AutoSelfRefreshSupport;///< REVISION_11 - FALSE = No auto self refresh support, TRUE = auto self refresh support.
+  BOOLEAN ExtTemperatureSupport; ///< REVISION_11 - FALSE = No extended temperature support, TRUE = extended temperature support.
+  UINT8   MaxRttWr;              ///< REVISION_11 - Maximum DIMM RTT_WR to use in power training 0 = Off, 1 = 120 ohms
+  UINT8   RCVENC1D;              ///< REVISION_12 - Receive Enable Centering Training.  LPDDR Only.
+  UINT8   MCREGOFFSET;           ///< @deprecated since revision 14
+  UINT8   RMC;                   ///< REVISION_15 - Retrain Margin Check Enable/Disable
+} MEMORY_CONFIGURATION;
+
+typedef struct {
+  UINTN   CpuId;
+  UINTN   CapIda;
+  UINTN   CapIdb;
+  UINT16  Peg0VenId;
+  UINT16  Peg0DevId;
+  UINT16  Peg1VenId;
+  UINT16  Peg1DevId;
+  UINT16  Peg2VenId;
+  UINT16  Peg2DevId;
+} PRESET_SEARCH_SIGNATURE;
+
+///
+/// SA GPIO Data Structure
+///
+typedef struct {
+  UINT8   Value;  ///< GPIO Value
+  BOOLEAN Active; ///< 0=Active Low; 1=Active High
+} SA_GPIO_INFO;
+
+///
+/// SA Board PEG GPIO Info
+///
+typedef struct {
+  BOOLEAN       GpioSupport;  ///< 1=Supported; 0=Not Supported
+  SA_GPIO_INFO  *SaPegReset;  ///< PEG PERST# GPIO assigned
+} PEG_GPIO_DATA;
+
+///
+/// Information for PCI Express controller configuration and DMI VC enable/disable control
+///
+typedef struct {
+  UINT8             DmiVc1;                                ///< DMI Virtual channel 1 control (enable or disable)
+  UINT8             DmiVcp;                                ///< DMI Virtual channel P control (enable or disable)
+  UINT8             DmiVcm;                                ///< DMI Virtual channel M control (enable or disable)
+  UINT8             DmiGen2;                               ///< DMI Gen2 support control (enable or disable)
+  UINT8             AlwaysEnablePeg;                       ///< Force PEG controllers to always be enabled
+  UINT8             PegGenx[SA_PEG_MAX_FUN];               ///< PEG Port PCIE GenX control (Gen1, Gen2 or Gen3)
+  UINT8             PegGen3Equalization;                   ///< Enable PEG Gen3 static Presets programming. 0=Disable and 1=Enable (Default)
+  UINT8             Gen3RootPortPreset[SA_PEG_MAX_LANE];   ///< Used for programming PEG Gen3 preset values per lane. Range: 0 to 9, 8 is default for each lane
+  UINT8             Gen3EndPointPreset[SA_PEG_MAX_LANE];   ///< Used for programming PEG Gen3 preset values per lane. Range: 0 to 9, 7 is default for each lane
+  UINT8             Gen3EndPointHint[SA_PEG_MAX_LANE];     ///< Hint value per lane for GEN3 end point device. Range: 0 to 6, 2 is default for each lane
+  UINT8             PegSamplerCalibrate;                   ///< Enable/Disable PEG Sampler Calibration. 0=Disable (Default) and 1=Enable
+  UINT8             PegGen3EqualizationPhase2;             ///< @deprecated since revision 6
+  ///
+  /// Note: An attack on the PresetSearch policies could result in an apparent hang,
+  ///   but the system will eventually boot.  These variables should be protected.
+  ///
+  UINT8             PegGen3PresetSearch;                   ///< Enable/Disable PEG Gen3 Preset Search algorithm which improves GEN3 link quality. 0=Disable and 1=Enable (Default)
+  UINT16            PegGen3PresetSearchDwellTime;          ///< Used for PEG Gen3 Preset Search algorithm. Range: 0 to 65535, default is 1000
+  UINT8             PegGen3PresetSearchMarginSteps;        ///< @deprecated since revision 3
+  UINT8             PegGen3PresetSearchStartMargin;        ///< Used for PEG Gen3 Preset Search algorithm. Range: 4 to 255, default is 15
+  UINT8             PegSwingControl;                       ///< Used for PEG Swing Control in PCIe Recipe steps. 1=Half and 2=Full (Default)
+  UINT8             PegGen3PresetSearchVoltageMarginSteps; ///< @deprecated since revision 3
+  UINT8             PegGen3PresetSearchVoltageStartMargin; ///< The starting value for the Gen3 preset search voltage backward margin search. Range: 4 to 255, default is 20
+  UINT8             PegGen3PresetSearchFavorTiming;        ///< @deprecated since revision 3
+  ///
+  /// This is a memory data pointer for saved preset search results. The reference code will store
+  ///   the Gen3 Preset Search results in the SaDataHob's PegData structure. In order to skip the Gen3
+  ///   preset search on boots where the PEG card configuration has not changed since the previous boot,
+  ///   platform code can save the contents of the SaDataHob's PegData structure in DXE and provide a
+  ///   pointer to a restored copy of that data. Default value is NULL, which results in a full
+  ///   preset search every boot.
+  ///
+  /// Note: An attack on this policy could prevent the PEG display from working until a boot when
+  ///   PegDataPtr is NULL or PegGen3ForcePresetSearch is enabled.  The variable used to save the
+  ///   preset search results should be protected in a way that it can only be modified by the
+  ///   platform manufacturer.
+  ///
+  VOID              *PegDataPtr;
+  ///
+  /// When enabled, Gen3 preset search will be executed each boot. Otherwise, it will be skipped
+  ///   and the previous Preset value will be re-used in the following boot. 0=Disable (Default)
+  ///   and 1=Enable
+  ///
+  BOOLEAN           PegGen3ForcePresetSearch;
+  ///
+  /// Set to 1 to do the PCIe ASPM programming after Oprom. This will require one SMM IO Trap handler
+  ///   implemented so ensure the build flag "SA_PCIE_ASPM_IN_SMM=1" is defined in compiling parameter.
+  ///   Set to 0 to do the PCIe ASPM programming before Oprom. ("SA_PCIE_ASPM_IN_DXE=1" should be
+  ///   defined in compiling parameter)
+  ///
+  /// Note:  Platform designer may include both SMM and DXE implementation (both build switch defined
+  ///   as 1) and provide a setup option to support different scenarios by this policy. It is required
+  ///   to have at least one implementation (either DXE or SMM implementation) included and working
+  ///   on platform or it may have security concern.
+  ///
+  BOOLEAN           InitPcieAspmAfterOprom;
+  ///
+  /// This IO Trap address is required to support PCIe ASPM programming after Oprom. When build switch
+  ///   "SA_PCIE_ASPM_IN_SMM=1" defined in compiling parameter this IO Trap address must be provided
+  ///   and should not conflict with any other IO address used by platform
+  ///
+  UINT16            SaIotrapSmiAddress;
+  ///
+  /// This is a memory data pointer to PCIe PERST# GPIO information.  This structure is required
+  ///   for PCIe Gen3 operation. The reference code will use the information in this structure in
+  ///   order to reset PCIe Gen3 devices during equalization, if necessary.  Refer to the Platform
+  ///   Developer's Guide (PDG) for additional details.  The default value of NULL is only valid
+  ///   for systems without PCIe Gen3 devices connected to the PEG controllers.
+  ///
+  PEG_GPIO_DATA     *PegGpioData;
+  UINT16            PegGen3PresetSearchErrorTarget;        ///< Used for PEG Gen3 Preset Search algorithm. Range: 0 to 65535, default is 4
+  BOOLEAN           RxCEMLoopback;                         ///< Enable/Disable RxCEMLoopback Test Mode. 0=Disable (default) and 1=Enable
+  UINT8             RxCEMLoopbackLane;                     ///< When RxCEMLoopback Test Mode enabled, a lane (0 ~ 15) has to be specified by this policy. Default is lane0 (0)
+  ///
+  /// PCIe Gen3 RxCTLEp per-Bundle control support. The range of the setting is (0~15). This setting
+  ///   has to be specified based upon platform design and must follow the guideline. Default is 12.
+  ///
+  UINT8             Gen3RxCtleP[SA_PEG_MAX_BUNDLE];
+  ///
+  /// PCIe power down unused bundles support. It has 3 policies.
+  ///   Disabled (0x0)     : No power saving.
+  ///   Auto (0xFF)        : Bios will decide unused bundles to power down [if the controller max-linkwidth is greater than the endpoint max-linkwidth
+  ///                        then bios will calculate the unused bundles to power down].
+  ///   1-n bundles (0x1-n): Number of bundles to power down via user selection [n depends on HW configuration].
+  ///
+  UINT8             PowerDownUnusedBundles[SA_PEG_MAX_FUN];
+  ///
+  /// PCIe compliance testing mode. Set this bit to when running a PCIe compliance test. Leave disabled during normal operation.
+  ///  - Disabled (0x0)     : Normal Operation          - Disable PCIe compliance testing
+  ///  - Enabled  (0x1)     : PCIe Compliance Test Mode - PEG controller is in compliance testing mode, should only be set when doing PCIe compliance testing
+  /// @since Added in revision 11
+  UINT8             PegComplianceTestingMode;
+} PCIE_CONFIGURATION;
+
+///
+/// Defines the overclocking configuration parameters for System Agent.
+///
+typedef struct {
+  INT16   GtVoltageOffset;      ///< The voltage offset applied to GT. Valid range from -1000mv to 1000mv
+  UINT16  GtVoltageOverride;    ///< The GT voltage override which is applied to the entire range of GT frequencies
+  UINT16  GtExtraTurboVoltage;  ///< The adaptive voltage applied during turbo frequencies. Valid range from 0 to 2000mV
+  UINT16  GtMaxOcTurboRatio;    ///< Maximum GT turbo ratio override
+  INT16   SaVoltageOffset;      ///< The voltage offset applied to the SA. Valid range from -1000mv to 1000mv
+  UINT8   GtVoltageMode;        ///< Specifies whether GT voltage is operating in Adaptive or Override mode - 0: Adaptive, 1: Override
+  UINT8   OcSupport;            ///< Enable disable of SA overclocking mailbox commands
+  INT16   IoaVoltageOffset;     ///< The voltage offset applied to the IOA domain. Valid Range -1000mv to 1000mv
+  INT16   IodVoltageOffset;     ///< The voltage offset applied to the IOD domain. Valid Range -1000mv to 1000mv
+} OVERCLOCKING_CONFIGURATION;
+
+///
+/// Defines the Switchable Graphics configuration parameters for System Agent.
+///
+typedef struct {
+  BOOLEAN       GpioSupport;        ///< 1=Supported; 0=Not Supported
+  SA_GPIO_INFO  *SgDgpuPwrOK;       ///< This field contain dGPU PWROK GPIO value and Level information
+  SA_GPIO_INFO  *SgDgpuHoldRst;     ///< This field contain dGPU HLD RESET GPIO value and level information
+  SA_GPIO_INFO  *SgDgpuPwrEnable;   ///< This field contain dGPU_PWR Enable GPIO value and level information
+  SA_GPIO_INFO  *SgDgpuPrsnt;       ///< This field contain dGPU_PRSNT# GPIO value and level information
+} SG_GPIO_DATA;
+
+///
+/// SA Platform Policy PPI
+///
+/// Note: User must initialize the policy "UserBd" based on the customer platform
+/// (Mobile - 0; Desktop/UpServer - 1) in customer BIOS before executing MRC. This policy
+/// isn't initialized in the Sample Code.
+///
+typedef struct _SA_PLATFORM_POLICY_PPI {
+  ///
+  /// This field specifies the revision of the PPI.  The PPI is expected to change in a
+  /// backwards compatible manner as the chipset configuration options are added or removed.
+  /// Major changes will result in new PPI definitions/GUID.  The PPI producer must update this
+  /// field at build time.
+  ///
+  /// Please ensure to use SA_PLATFORM_POLICY_PPI_REVISION macro to define the protocol revision
+  /// as input for this version
+  ///
+  UINT8                       Revision;
+  SA_PLATFORM_DATA            *PlatformData;             ///< Platform specific data
+  GT_CONFIGURATION            *GtConfig;                 ///< Contains the information for Graphic configurations
+  MEMORY_CONFIGURATION        *MemConfig;                ///< Contains the information for Memory configurations
+  PCIE_CONFIGURATION          *PcieConfig;               ///< Contains the information for PCI Express controller configurations
+  OVERCLOCKING_CONFIGURATION  *OcConfig;                 ///< Contains the information for Overclocking configurations
+  VOID                        *S3DataPtr;                ///< Memory data save pointer for S3 resume. The memory space should be allocated and filled with proper S3 resume data on a resume path
+  UINT8                       ScramblerSeedCmosLocation; ///< @deprecated since revision 2
+  SG_GPIO_DATA                *SgGpioData;               ///< Switchable Graphics GPIO data (REVISION_3)
+} SA_PLATFORM_POLICY_PPI;
+
+#pragma pack()
+
+#endif // _SA_PLATFORM_POLICY_PPI_H_
diff --git a/ReferenceCode/Chipset/SystemAgent/Ppi/SaPpiLib.cif b/ReferenceCode/Chipset/SystemAgent/Ppi/SaPpiLib.cif
new file mode 100644
index 0000000..5a7ad60
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/Ppi/SaPpiLib.cif
@@ -0,0 +1,16 @@
+<component>
+	name = "SaPpiLib"
+	category = ModulePart
+	LocalRoot = "ReferenceCode\Chipset\SystemAgent\Ppi\"
+	RefName = "SaPpiLib"
+[files]
+"SaPpiLib.sdl"	
+"SaPpiLib.mak"	
+"IntelSaPpiLib.inf"	
+"SsaPeiInit\SsaPeiInit.c"	
+"SsaPeiInit\SsaPeiInit.h"	
+"SaPlatformPolicy\SaPlatformPolicy.c"	
+"SaPlatformPolicy\SaPlatformPolicy.h"	
+"SaPeiInit\SaPeiInit.h"	
+"SaPeiInit\SaPeiInit.c"	
+<endComponent>
diff --git a/ReferenceCode/Chipset/SystemAgent/Ppi/SaPpiLib.mak b/ReferenceCode/Chipset/SystemAgent/Ppi/SaPpiLib.mak
new file mode 100644
index 0000000..bf21b86
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/Ppi/SaPpiLib.mak
@@ -0,0 +1,20 @@
+# MAK file for the ModulePart:IntelSaPpiLib
+all : IntelSaPpiLib
+
+$(BUILD_DIR)\IntelSaPpiLib.lib : IntelSaPpiLib
+
+IntelSaPpiLib : $(BUILD_DIR)\SaPpiLib.mak IntelSaPpiLibBin
+
+$(BUILD_DIR)\SaPpiLib.mak : $(INTEL_SA_PPI_LIB_DIR)\$(@B).cif $(INTEL_SA_PPI_LIB_DIR)\$(@B).mak $(BUILD_RULES)
+  $(CIF2MAK) $(INTEL_SA_PPI_LIB_DIR)\$(@B).cif $(CIF2MAK_DEFAULTS)
+
+IntelSaPpiLib_INCLUDES =\
+    $(EDK_INCLUDES) \
+    $(INTEL_MCH_INCLUDES)
+
+IntelSaPpiLibBin : 
+    $(MAKE) /$(MAKEFLAGS) $(EDKIIGLUE_DEFAULTS)\
+    /f $(BUILD_DIR)\SaPpiLib.mak all\
+    "MY_INCLUDES=$(IntelSaPpiLib_INCLUDES)" \
+    TYPE=PEI_LIBRARY \
+    LIBRARY_NAME=$(BUILD_DIR)\IntelSaPpiLib.lib
\ No newline at end of file
diff --git a/ReferenceCode/Chipset/SystemAgent/Ppi/SaPpiLib.sdl b/ReferenceCode/Chipset/SystemAgent/Ppi/SaPpiLib.sdl
new file mode 100644
index 0000000..d2d8eaa
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/Ppi/SaPpiLib.sdl
@@ -0,0 +1,42 @@
+TOKEN
+  Name  = SaPpiLib_SUPPORT
+  Value  = 1
+  TokenType = Boolean
+  TargetEQU = Yes
+  TargetMAK = Yes
+  Master = Yes
+  Help  = "Main switch to enable SaPpiLib support in Project"
+End
+
+MODULE
+  Help  = "Includes SaPpiLib.mak to Project"
+  File  = "SaPpiLib.mak"
+End
+
+ELINK
+  Name  = "INTEL_SA_PPI_LIB"
+  InvokeOrder = ReplaceParent
+End
+
+ELINK
+  Name  = "$(BUILD_DIR)\IntelSaPpiLib.lib"
+  Parent  = "INTEL_SA_PPI_LIB"
+  InvokeOrder = AfterParent
+End
+
+PATH
+  Name  = "INTEL_SA_PPI_LIB_DIR"
+End
+
+ELINK
+	Name  = "/I$(INTEL_SA_PPI_LIB_DIR)"
+	Parent  = "INTEL_MCH_INCLUDES"
+	InvokeOrder = AfterParent
+End
+
+ELINK
+	Name  = "/I$(INTEL_SA_PPI_LIB_DIR)\SsaPeiInit"
+	Parent  = "INTEL_MCH_INCLUDES"
+	InvokeOrder = AfterParent
+End
+
diff --git a/ReferenceCode/Chipset/SystemAgent/Ppi/SsaPeiInit/SsaPeiInit.c b/ReferenceCode/Chipset/SystemAgent/Ppi/SsaPeiInit/SsaPeiInit.c
new file mode 100644
index 0000000..a7eed72
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/Ppi/SsaPeiInit/SsaPeiInit.c
@@ -0,0 +1,47 @@
+/**
+This file contains an 'Intel Peripheral Driver' and uniquely
+identified as "Intel Reference Module" and is
+licensed for Intel CPUs and chipsets under the terms of your
+license agreement with Intel or your vendor.  This file may
+be modified by the user, subject to additional terms of the
+license agreement
+
+@copyright
+Copyright (c) 2012 Intel Corporation. All rights reserved
+This software and associated documentation (if any) is furnished
+under a license and may only be used or copied in accordance
+with the terms of the license. Except as permitted by such
+license, no part of this software or documentation may be
+reproduced, stored in a retrieval system, or transmitted in any
+form or by any means without the express written consent of
+Intel Corporation.
+
+@file
+  SsaPeiInit.c
+
+@brief
+  Interface definition between MRC and SsaInitPeim driver.
+**/
+
+///
+/// External include files do NOT need to be explicitly specified in real EDKII
+/// environment
+///
+#if !defined(EDK_RELEASE_VERSION) || (EDK_RELEASE_VERSION < 0x00020000)
+#include "EdkIIGluePeim.h"
+#endif
+
+#include "SsaPeiInit.h"
+
+///
+/// PPI GUID definition
+///
+EFI_GUID  gSsaBiosCallBacksPpiGuid = SSA_BIOS_CALLBACKS_PPI_GUID;
+EFI_GUID  gSsaBiosServicesPpiGuid  = SSA_BIOS_SERVICES_PPI_GUID;
+
+///
+/// PPI description
+///
+EFI_GUID_STRING (&gSsaBiosCallBacksPpiGuid, "SsaBiosCallback", "SSA Bios Callback PPI");
+EFI_GUID_STRING (&gSsaBiosServicesPpiGuid, "SsaBiosServices", "SSA Bios Services PPI");
+
diff --git a/ReferenceCode/Chipset/SystemAgent/Ppi/SsaPeiInit/SsaPeiInit.h b/ReferenceCode/Chipset/SystemAgent/Ppi/SsaPeiInit/SsaPeiInit.h
new file mode 100644
index 0000000..6a0ab1d
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/Ppi/SsaPeiInit/SsaPeiInit.h
@@ -0,0 +1,40 @@
+/**
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement
+
+@copyright
+  Copyright (c) 2012 - 2012 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+@file
+  SsaPeiInit.h
+
+@brief
+  Interface definition between MRC and SsaInitPeim driver.
+**/
+#ifndef _SSA_PEI_INIT_H_
+#define _SSA_PEI_INIT_H_
+
+///
+/// Define the SSA PEI Init PPI GUID
+///
+#define SSA_BIOS_CALLBACKS_PPI_GUID {0x99B56126, 0xE16C, 0x4D9B, 0xBB, 0x71, 0xAA, 0x35, 0x46, 0x1A, 0x70, 0x2F}
+#define SSA_BIOS_SERVICES_PPI_GUID  {0x55750D10, 0x6D3D, 0x4BF5, 0x89, 0xD8, 0xE3, 0x5E, 0xF0, 0xB0, 0x90, 0xF4}
+
+///
+/// Extern the GUID for PPI users.
+///
+extern EFI_GUID gSsaBiosCallBacksPpiGuid;
+extern EFI_GUID gSsaBiosServicesPpiGuid;
+
+#endif
diff --git a/ReferenceCode/Chipset/SystemAgent/Protocol/BdatAccess/BdatAccess.c b/ReferenceCode/Chipset/SystemAgent/Protocol/BdatAccess/BdatAccess.c
new file mode 100644
index 0000000..ec43597
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/Protocol/BdatAccess/BdatAccess.c
@@ -0,0 +1,29 @@
+/** @file
+  Bdat Access Handler Protocol
+
+@copyright
+  Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement
+**/
+
+#if !defined(EDK_RELEASE_VERSION) || (EDK_RELEASE_VERSION < 0x00020000)
+#include "EdkIIGlueDxe.h"
+#endif
+#include EFI_PROTOCOL_DEFINITION (BdatAccess)
+
+EFI_GUID  gBdatAccessGuid = EFI_BDAT_ACCESS_GUID;
+
+EFI_GUID_STRING(&gBdatAccessGuid, "BDAT ACCESS", "BDAT ACCESS");
diff --git a/ReferenceCode/Chipset/SystemAgent/Protocol/BdatAccess/BdatAccess.h b/ReferenceCode/Chipset/SystemAgent/Protocol/BdatAccess/BdatAccess.h
new file mode 100644
index 0000000..1d49638
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/Protocol/BdatAccess/BdatAccess.h
@@ -0,0 +1,36 @@
+/** @file
+  This file abstracts Bdat Access Handler Protocol.
+
+@copyright
+  Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement
+**/
+
+#ifndef _BDAT_ACCESS_PROTOCOL_H_
+#define _BDAT_ACCESS_PROTOCOL_H_
+
+#define EFI_BDAT_ACCESS_GUID \
+  { \
+    0xb979746a, 0x8c1f, 0x4a2b, 0x97, 0xe4, 0x78, 0xe9, 0x3a, 0x71, 0xa7, 0xa \
+  }
+
+typedef struct _BDAT_ACCESS_PROTOCOL {
+  UINTN bdat;
+} BDAT_ACCESS_PROTOCOL;
+
+extern EFI_GUID gBdatAccessGuid;
+
+#endif
diff --git a/ReferenceCode/Chipset/SystemAgent/Protocol/GopComponentName2/GopComponentName2.c b/ReferenceCode/Chipset/SystemAgent/Protocol/GopComponentName2/GopComponentName2.c
new file mode 100644
index 0000000..f430cf3
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/Protocol/GopComponentName2/GopComponentName2.c
@@ -0,0 +1,37 @@
+/** @file
+  Protocol to retrieve the GOP driver version
+
+@copyright
+  Copyright (c) 1999 - 2013 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement
+**/
+#include "Tiano.h"
+
+///
+/// Include the protocol header file
+///
+#include "GopComponentName2.h"
+
+///
+/// Protocol GUID definition
+///
+EFI_GUID  gGopComponentName2ProtocolGuid  = GOP_COMPONENT_NAME2_PROTOCOL_GUID
+
+///
+/// Protocol description
+///
+EFI_GUID_STRING
+  (&gGopComponentName2ProtocolGuid, "ComponentName2 Protocol", "Intel(R) DXE Phase Gop Component Name 2 Protocol");
diff --git a/ReferenceCode/Chipset/SystemAgent/Protocol/GopComponentName2/GopComponentName2.h b/ReferenceCode/Chipset/SystemAgent/Protocol/GopComponentName2/GopComponentName2.h
new file mode 100644
index 0000000..51ff044
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/Protocol/GopComponentName2/GopComponentName2.h
@@ -0,0 +1,72 @@
+/** @file
+  Protocol to retrieve the GOP driver version
+
+@copyright
+  Copyright (c) 1999 - 2013 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement
+**/
+
+#ifndef _GOP_COMPONENT_NAME2_H_
+#define _GOP_COMPONENT_NAME2_H_
+//
+// Global ID for the Component Name Protocol
+//
+#define GOP_COMPONENT_NAME2_PROTOCOL_GUID \
+  { \
+    0x651b7ebd, 0xce13, 0x41d0, 0x82, 0xe5, 0xa0, 0x63, 0xab, 0xbe, 0x9b, 0xb6 \
+  }
+
+EFI_FORWARD_DECLARATION (GOP_COMPONENT_NAME2_PROTOCOL);
+
+
+typedef struct _GOP_COMPONENT_NAME2_PROTOCOL  GOP_COMPONENT_NAME2_PROTOCOL;
+
+typedef
+EFI_STATUS
+(EFIAPI *GOP_COMPONENT_NAME2_GET_DRIVER_NAME) (
+  IN  GOP_COMPONENT_NAME2_PROTOCOL * This,
+  IN  CHAR8                           *Language,
+  OUT CHAR16                          **DriverName
+  );
+
+typedef
+EFI_STATUS
+(EFIAPI *GOP_COMPONENT_NAME2_GET_CONTROLLER_NAME) (
+  IN  GOP_COMPONENT_NAME2_PROTOCOL          * This,
+  IN  EFI_HANDLE                               ControllerHandle,
+  IN  EFI_HANDLE                               ChildHandle OPTIONAL,
+  IN  CHAR8                                    *Language,
+  OUT CHAR16                                   **ControllerName
+  );
+
+typedef
+EFI_STATUS
+(EFIAPI *GOP_COMPONENT_NAME2_GET_DRIVER_VERSION) (
+  IN  GOP_COMPONENT_NAME2_PROTOCOL          * This,
+  IN  CHAR8                                    *Language,
+  OUT CHAR16                                   **DriverVersion
+  );
+
+struct _GOP_COMPONENT_NAME2_PROTOCOL {
+  GOP_COMPONENT_NAME2_GET_DRIVER_NAME      GetDriverName;
+  GOP_COMPONENT_NAME2_GET_DRIVER_VERSION   GetDriverVersion;
+  GOP_COMPONENT_NAME2_GET_CONTROLLER_NAME  GetControllerName;
+  CHAR8                                       *SupportedLanguages;
+};
+
+extern EFI_GUID gGopComponentName2ProtocolGuid;
+
+#endif
diff --git a/ReferenceCode/Chipset/SystemAgent/Protocol/IgdOpRegion/IgdOpRegion.c b/ReferenceCode/Chipset/SystemAgent/Protocol/IgdOpRegion/IgdOpRegion.c
new file mode 100644
index 0000000..596c9f5
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/Protocol/IgdOpRegion/IgdOpRegion.c
@@ -0,0 +1,35 @@
+/** @file
+  This file is part of the IGD OpRegion Implementation.  The IGD OpRegion is
+  an interface between system BIOS, ASL code, and Graphics drivers.  The code
+  in this file will implement a protocol allowing access to the
+  OpRegion from ASL code.
+
+  Supporting Specifiction: IGD OpRegion/Software SCI BIOS SPEC
+
+@copyright
+  Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement
+**/
+#include "Tiano.h"
+#include "IgdOpRegion.h"
+
+EFI_GUID  gIgdOpRegionProtocolGuid = IGD_OPREGION_PROTOCOL_GUID;
+
+EFI_GUID_STRING
+  (
+    &gIgdOpRegionProtocolGuid, "IGD OpRegion/Software SCI",
+      "Communication interface between Graphics drivers, ASL code, and system BIOS"
+  );
diff --git a/ReferenceCode/Chipset/SystemAgent/Protocol/IgdOpRegion/IgdOpRegion.h b/ReferenceCode/Chipset/SystemAgent/Protocol/IgdOpRegion/IgdOpRegion.h
new file mode 100644
index 0000000..c0b5c06
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/Protocol/IgdOpRegion/IgdOpRegion.h
@@ -0,0 +1,210 @@
+/** @file
+  This file is part of the IGD OpRegion Implementation.  The IGD OpRegion is
+  an interface between system BIOS, ASL code, and Graphics drivers.
+
+  Supporting Specifiction: IGD OpRegion/Software SCI SPEC
+
+  Note:  Data structures defined in this protocol are packed not naturally
+    aligned.
+
+  GUID forms:
+    {CDC5DDDF-E79D-41ec-A9B0-6565490DB9D3}
+    (0xcdc5dddf, 0xe79d, 0x41ec, 0xa9, 0xb0, 0x65, 0x65, 0x49, 0xd, 0xb9, 0xd3);
+
+  Acronyms:
+    NVS:        ACPI Non Volatile Storage
+    OpRegion:   ACPI Operational Region
+    VBT:        Video BIOS Table (OEM customizable data)
+
+@copyright
+  Copyright (c) 1999 - 2013 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement
+**/
+#ifndef _IGD_OPREGION_PROTOCOL_H_
+#define _IGD_OPREGION_PROTOCOL_H_
+
+///
+/// Include files
+///
+#include "Tiano.h"
+
+///
+/// IGD OpRegion protocol GUID
+///
+#define IGD_OPREGION_PROTOCOL_GUID \
+  { \
+    0xcdc5dddf, 0xe79d, 0x41ec, 0xa9, 0xb0, 0x65, 0x65, 0x49, 0xd, 0xb9, 0xd3 \
+  }
+
+///
+/// Extern the GUID for protocol users.
+///
+extern EFI_GUID gIgdOpRegionProtocolGuid;
+
+///
+/// Forward reference for pure ANSI compatability
+///
+EFI_FORWARD_DECLARATION (IGD_OPREGION_PROTOCOL);
+
+//
+// Protocol data definitions
+//
+///
+/// OpRegion structures:
+/// Sub-structures define the different parts of the OpRegion followed by the
+/// main structure representing the entire OpRegion.
+///
+/// Note: These structures are packed to 1 byte offsets because the exact
+/// data location is requred by the supporting design specification due to
+/// the fact that the data is used by ASL and Graphics driver code compiled
+/// separatly.
+///
+///
+/// OpRegion header (mailbox 0) structure and #defines.
+///
+#pragma pack(1)
+typedef struct {
+  CHAR8   SIGN[0x10]; ///< 0    OpRegion signature
+  UINT32  SIZE;       ///< 16   OpRegion size
+  UINT32  OVER;       ///< 20   OpRegion structure version
+  UINT8   SVER[0x20]; ///< 24   System BIOS build version
+  UINT8   VVER[0x10]; ///< 56   Video BIOS build version
+  UINT8   GVER[0x10]; ///< 72   Graphic driver build version
+  UINT32  MBOX;       ///< 88   Mailboxes supported
+  UINT32  DMOD;       ///< 92   Driver Model
+  UINT32  PCON;       ///< 96   Platform Capabilities
+  CHAR16  DVER[0x10]; ///< 100  GOP Version
+  UINT8   RHD1[0x7C]; ///< 132  Reserved
+} OPREGION_HEADER;
+#pragma pack()
+///
+/// OpRegion mailbox 1 (public ACPI Methods).
+///
+#pragma pack(1)
+typedef struct {
+  UINT32  DRDY;       ///< 0    Driver readiness
+  UINT32  CSTS;       ///< 4    Status
+  UINT32  CEVT;       ///< 8    Current event
+  UINT8   RM11[0x14]; ///< 12   Reserved
+  UINT32  DIDL;       ///< 32   Supported display devices list
+  UINT32  DDL2;       ///<  8 Devices.
+  UINT32  DDL3;
+  UINT32  DDL4;
+  UINT32  DDL5;
+  UINT32  DDL6;
+  UINT32  DDL7;
+  UINT32  DDL8;
+  UINT32  CPDL;       ///< 64   Currently present display devices list
+  UINT32  CPL2;       ///<  8 Devices.
+  UINT32  CPL3;
+  UINT32  CPL4;
+  UINT32  CPL5;
+  UINT32  CPL6;
+  UINT32  CPL7;
+  UINT32  CPL8;
+  UINT32  CADL;       ///< 96   Currently active display devices list
+  UINT32  CAL2;       ///<  8 Devices.
+  UINT32  CAL3;
+  UINT32  CAL4;
+  UINT32  CAL5;
+  UINT32  CAL6;
+  UINT32  CAL7;
+  UINT32  CAL8;
+  UINT32  NADL;       ///< 128  Next active device list
+  UINT32  NDL2;       ///<   8 Devices.
+  UINT32  NDL3;
+  UINT32  NDL4;
+  UINT32  NDL5;
+  UINT32  NDL6;
+  UINT32  NDL7;
+  UINT32  NDL8;
+  UINT32  ASLP;       ///< 160  ASL sleep timeout
+  UINT32  TIDX;       ///< 164  Toggle table index
+  UINT32  CHPD;       ///< 168  Current hot plug enable indicator
+  UINT32  CLID;       ///< 172  Current lid state indicator
+  UINT32  CDCK;       ///< 176  Current docking state indicator
+  UINT32  SXSW;       ///< 180  Display Switch notification on Sx State resume
+  UINT32  EVTS;       ///< 184  Events supported by ASL
+  UINT32  CNOT;       ///< 188  Current OS Notification
+  UINT32  NRDY;       ///< 192  Reasons for DRDY = 0
+  UINT8   RM12[0x3C]; ///< 196  Reserved
+} OPREGION_MBOX1;
+#pragma pack()
+///
+/// OpRegion mailbox 2 (Software SCI Interface).
+///
+#pragma pack(1)
+typedef struct {
+  UINT32  SCIC;       ///< 0    Software SCI function number parameters
+  UINT32  PARM;       ///< 4    Software SCI additional parameters
+  UINT32  DSLP;       ///< 8    Driver sleep timeout
+  UINT8   RM21[0xF4]; ///< 12   Reserved
+} OPREGION_MBOX2;
+#pragma pack()
+///
+/// OpRegion mailbox 3 (Power Conservation).
+///
+#pragma pack(1)
+typedef struct {
+  UINT32  ARDY;       ///< 0    Driver readiness
+  UINT32  ASLC;       ///< 4    ASLE interrupt command / status
+  UINT32  TCHE;       ///< 8    Technology enabled indicator
+  UINT32  ALSI;       ///< 12   Current ALS illuminance reading
+  UINT32  BCLP;       ///< 16   Backlight britness to set
+  UINT32  PFIT;       ///< 20   Panel fitting Request
+  UINT32  CBLV;       ///< 24   Brightness Current State
+  UINT16  BCLM[0x14]; ///< 28   Backlight Brightness Level Duty Cycle Mapping Table
+  UINT32  CPFM;       ///< 68   Panel Fitting Current Mode
+  UINT32  EPFM;       ///< 72   Enabled Panel Fitting Modes
+  UINT8   PLUT[0x4A]; ///< 76   Panel Look Up Table
+  UINT32  PFMB;       ///< 150  PWM Frequency and Minimum Brightness
+  UINT32  CCDV;       ///< 154  Color Correction Default Values
+  UINT32  PCFT;       ///< 158  Power Conservation Features
+  UINT32  SROT;       ///< 162  Supported Rotation angle
+  UINT32  IUER;       ///< 166  Intel Ultrabook Event Register
+  UINT64  FDSP;       ///< 170  FFS Display Physical address
+  UINT32  FDSS;       ///< 178  FFS Display Size
+  UINT8   RM32[0x4A]; ///< 182  Reserved
+} OPREGION_MBOX3;
+#pragma pack()
+///
+/// OpRegion mailbox 4 (VBT).
+///
+#pragma pack(1)
+typedef struct {
+  UINT8 GVD1[0x1C00]; ///< Reserved
+} OPREGION_VBT;
+#pragma pack()
+///
+/// Entire OpRegion
+///
+#pragma pack(1)
+typedef struct {
+  OPREGION_HEADER Header; ///< OpRegion header
+  OPREGION_MBOX1  MBox1;  ///< Mailbox 1: Public ACPI Methods
+  OPREGION_MBOX2  MBox2;  ///< Mailbox 2: Software SCI Inteface
+  OPREGION_MBOX3  MBox3;  ///< Mailbox 3: Power Conservation
+  OPREGION_VBT    VBT;    ///< VBT: Video BIOS Table (OEM customizable data)
+} IGD_OPREGION_STRUC;
+#pragma pack()
+///
+/// Protocol data structure definition
+///
+struct _IGD_OPREGION_PROTOCOL {
+  IGD_OPREGION_STRUC  *OpRegion;
+};
+
+#endif
diff --git a/ReferenceCode/Chipset/SystemAgent/Protocol/IntelSaProtocolLib.inf b/ReferenceCode/Chipset/SystemAgent/Protocol/IntelSaProtocolLib.inf
new file mode 100644
index 0000000..594e48b
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/Protocol/IntelSaProtocolLib.inf
@@ -0,0 +1,59 @@
+## @file
+#  Component description file for the SA protocol library
+#
+#@copyright
+#  Copyright (c)  2010 - 2013 Intel Corporation. All rights reserved
+#  This software and associated documentation (if any) is furnished
+#  under a license and may only be used or copied in accordance
+#  with the terms of the license. Except as permitted by such
+#  license, no part of this software or documentation may be
+#  reproduced, stored in a retrieval system, or transmitted in any
+#  form or by any means without the express written consent of
+#  Intel Corporation.
+#
+#  This file contains a 'Sample Driver' and is licensed as such
+#  under the terms of your license agreement with Intel or your
+#  vendor.  This file may be modified by the user, subject to
+#  the additional terms of the license agreement
+#
+
+
+[defines]
+BASE_NAME       =   IntelSaProtocolLib
+COMPONENT_TYPE  =   LIBRARY
+
+[sources.common]
+  MemInfo/MemInfo.h
+  MemInfo/MemInfo.c
+  IgdOpRegion/IgdOpRegion.h
+  IgdOpRegion/IgdOpRegion.c
+  SaPlatformPolicy/SaPlatformPolicy.h
+  SaPlatformPolicy/SaPlatformPolicy.c
+  SaInfo/SaInfo.h
+  SaInfo/SaInfo.c
+  BdatAccess/BdatAccess.h
+  BdatAccess/BdatAccess.c
+  SaGlobalNvsArea/SaGlobalNvsArea.c
+  SaGlobalNvsArea/SaGlobalNvsArea.h
+  PlatformGopPolicy/PlatformGopPolicy.h
+  PlatformGopPolicy/PlatformGopPolicy.c
+  GopComponentName2/GopComponentName2.h
+  GopComponentName2/GopComponentName2.c
+
+[includes.common]
+  .
+  $(EDK_SOURCE)/Foundation
+  $(EDK_SOURCE)/Foundation/Framework
+  $(EDK_SOURCE)/Foundation/Efi
+  $(EDK_SOURCE)/Foundation/Include
+  $(EDK_SOURCE)/Foundation/Efi/Include
+  $(EDK_SOURCE)/Foundation/Framework/Include
+  $(EDK_SOURCE)/Foundation/Include/IndustryStandard
+  $(EDK_SOURCE)/Foundation/Core/Dxe
+  $(EDK_SOURCE)/Foundation/Library/Dxe/Include
+  $(EDK_SOURCE)/Foundation/Library/EdkIIGlueLib/Include
+  $(EFI_SOURCE)/$(PROJECT_SA_ROOT)
+  $(EFI_SOURCE)/$(PROJECT_SA_ROOT)/Include
+
+[nmake.common]
+C_STD_INCLUDE=
diff --git a/ReferenceCode/Chipset/SystemAgent/Protocol/MemInfo/MemInfo.c b/ReferenceCode/Chipset/SystemAgent/Protocol/MemInfo/MemInfo.c
new file mode 100644
index 0000000..09e400c
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/Protocol/MemInfo/MemInfo.c
@@ -0,0 +1,33 @@
+/** @file
+  This file defines global GUID variables for the MemInfo Protocol
+
+@copyright
+  Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement
+**/
+#include "Tiano.h"
+#include "MemInfo.h"
+
+///
+/// Protocol GUID definition
+///
+EFI_GUID  gMemInfoProtocolGuid = MEM_INFO_PROTOCOL_GUID;
+
+///
+/// Protocol description
+///
+EFI_GUID_STRING
+  (&gMemInfoProtocolGuid, "Memory Information Protocol", "The MemInfo Protocol returns memory information Data.");
diff --git a/ReferenceCode/Chipset/SystemAgent/Protocol/MemInfo/MemInfo.h b/ReferenceCode/Chipset/SystemAgent/Protocol/MemInfo/MemInfo.h
new file mode 100644
index 0000000..6f0c662
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/Protocol/MemInfo/MemInfo.h
@@ -0,0 +1,99 @@
+/** @file
+  This protocol provides the memory information data, such as
+  total physical memory size, memory frequency, memory size
+  of each dimm and rank.
+
+@copyright
+  Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement
+**/
+#ifndef _MEM_INFO_PROTOCOL_H_
+#define _MEM_INFO_PROTOCOL_H_
+
+///
+/// Define the  protocol GUID
+///
+#define MEM_INFO_PROTOCOL_GUID \
+  { \
+    0x6f20f7c8, 0xe5ef, 0x4f21, 0x8d, 0x19, 0xed, 0xc5, 0xf0, 0xc4, 0x96, 0xae \
+  }
+
+///
+/// Extern the GUID for protocol users.
+///
+extern EFI_GUID                   gMemInfoProtocolGuid;
+
+//
+// Forward reference for ANSI C compatibility
+//
+typedef struct _MEM_INFO_PROTOCOL MEM_INFO_PROTOCOL;
+
+//
+// Protocol definitions
+//
+#define NODE_NUM  1
+#define CH_NUM    2
+#define DIMM_NUM  2
+#define RANK_NUM  2
+#define PROFILE_NUM 4 // number of memory profiles supported
+
+#pragma pack(1)
+typedef struct {
+  UINT32 tCK;    ///< Memory cycle time, in femtoseconds.
+  UINT16 NMode;  ///< Number of tCK cycles for the channel DIMM's command rate mode.
+  UINT16 tCL;    ///< Number of tCK cycles for the channel DIMM's CAS latency.
+  UINT16 tCWL;   ///< Number of tCK cycles for the channel DIMM's minimum CAS write latency time.
+  UINT16 tFAW;   ///< Number of tCK cycles for the channel DIMM's minimum four activate window delay time.
+  UINT16 tRAS;   ///< Number of tCK cycles for the channel DIMM's minimum active to precharge delay time.
+  UINT16 tRC;    ///< Number of tCK cycles for the channel DIMM's minimum active to active/refresh delay time.
+  UINT16 tRCD;   ///< Number of tCK cycles for the channel DIMM's minimum RAS# to CAS# delay time.
+  UINT16 tREFI;  ///< Number of tCK cycles for the channel DIMM's minimum Average Periodic Refresh Interval.
+  UINT16 tRFC;   ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
+  UINT16 tRP;    ///< Number of tCK cycles for the channel DIMM's minimum row precharge delay time.
+  UINT16 tRPab;  ///< Number of tCK cycles for the channel DIMM's minimum row precharge delay time for all banks.
+  UINT16 tRRD;   ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time.
+  UINT16 tRTP;   ///< Number of tCK cycles for the channel DIMM's minimum internal read to precharge command delay time.
+  UINT16 tWR;    ///< Number of tCK cycles for the channel DIMM's minimum write recovery time.
+  UINT16 tWTR;   ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time.
+} MEMORY_TIMING;
+
+typedef struct {
+  UINT32  memSize;                                  ///< Total physical memory size
+  UINT16  ddrFreq;                                  ///< DDR Frequency
+  UINT16  ddrFreqMax;
+  UINT8   RefClk;
+  UINT8   Ratio;
+  BOOLEAN EccSupport;                               ///< ECC Support
+  UINT16  dimmSize[NODE_NUM * CH_NUM * DIMM_NUM];   ///< Dimm Size
+  BOOLEAN DimmExist[NODE_NUM * CH_NUM * DIMM_NUM];  ///< Dimm Present or not
+  UINT8   RankInDimm[NODE_NUM * CH_NUM * DIMM_NUM]; ///< No. of ranks in a dimm
+  UINT8   Reserved[24];
+  UINT8   *DimmsSpdData[NODE_NUM * CH_NUM * DIMM_NUM];
+  UINT16  VddVoltage[PROFILE_NUM];
+  MEMORY_TIMING Timing[PROFILE_NUM];
+  UINT8   Profile;                                  ///< Currently running memory profile
+  UINT8   XmpProfileEnable;                         ///< 0 = no XMP DIMMs in system
+} MEMORY_INFO_DATA;
+#pragma pack()
+
+///
+/// Protocol definition
+///
+struct _MEM_INFO_PROTOCOL {
+  MEMORY_INFO_DATA  MemInfoData;
+};
+
+#endif
diff --git a/ReferenceCode/Chipset/SystemAgent/Protocol/PlatformGopPolicy/PlatformGopPolicy.c b/ReferenceCode/Chipset/SystemAgent/Protocol/PlatformGopPolicy/PlatformGopPolicy.c
new file mode 100644
index 0000000..7fa5b6f
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/Protocol/PlatformGopPolicy/PlatformGopPolicy.c
@@ -0,0 +1,36 @@
+/** @file
+  Interface definition for PlatformGopPolicy Protocol.
+
+@copyright
+  Copyright (c) 2011 - 2012 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement
+**/
+#include "Tiano.h"
+
+///
+/// Include the protocol header file
+///
+#include "PlatformGopPolicy.h"
+
+///
+/// Protocol GUID definition
+///
+EFI_GUID  gPlatformGopPolicyProtocolGuid = EFI_PLATFORM_GOP_POLICY_PROTOCOL_GUID;
+
+///
+/// Protocol description
+///
+EFI_GUID_STRING(&gPlatformGopPolicyProtocolGuid, "PlatformGopPolicy Protocol", "Intel(R) GOP Platform Policy Protocol");
diff --git a/ReferenceCode/Chipset/SystemAgent/Protocol/PlatformGopPolicy/PlatformGopPolicy.h b/ReferenceCode/Chipset/SystemAgent/Protocol/PlatformGopPolicy/PlatformGopPolicy.h
new file mode 100644
index 0000000..d6c493b
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/Protocol/PlatformGopPolicy/PlatformGopPolicy.h
@@ -0,0 +1,58 @@
+/** @file
+  Interface definition for PlatformGopPolicy Protocol.
+
+@copyright
+  Copyright (c) 2011 - 2012 Intel Corporation. All rights reserved.
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement
+**/
+#ifndef _PLATFORM_GOP_POLICY_PROTOCOL_H_
+#define _PLATFORM_GOP_POLICY_PROTOCOL_H_
+
+#define EFI_PLATFORM_GOP_POLICY_PROTOCOL_GUID \
+  { \
+    0xec2e931b, 0x3281, 0x48a5, 0x81, 0x7, 0xdf, 0x8a, 0x8b, 0xed, 0x3c, 0x5d \
+  }
+
+#define PLATFORM_GOP_POLICY_PROTOCOL_REVISION_01  0x01
+
+typedef enum {
+  LidClosed,
+  LidOpen,
+  LidStatusMax
+} LID_STATUS;
+
+typedef
+EFI_STATUS
+(EFIAPI *GET_PLATFORM_LID_STATUS) (
+  OUT LID_STATUS * CurrentLidStatus
+  );
+
+typedef
+EFI_STATUS
+(EFIAPI *GET_VBT_DATA) (
+  OUT EFI_PHYSICAL_ADDRESS * VbtAddress,
+  OUT UINT32               *VbtSize
+  );
+
+typedef struct _PLATFORM_GOP_POLICY_PROTOCOL {
+  UINT32                  Revision;
+  GET_PLATFORM_LID_STATUS GetPlatformLidStatus;
+  GET_VBT_DATA            GetVbtData;
+} PLATFORM_GOP_POLICY_PROTOCOL;
+
+extern EFI_GUID gPlatformGopPolicyProtocolGuid;
+
+#endif
diff --git a/ReferenceCode/Chipset/SystemAgent/Protocol/SaGlobalNvsArea/SaGlobalNvsArea.c b/ReferenceCode/Chipset/SystemAgent/Protocol/SaGlobalNvsArea/SaGlobalNvsArea.c
new file mode 100644
index 0000000..2f0725d
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/Protocol/SaGlobalNvsArea/SaGlobalNvsArea.c
@@ -0,0 +1,31 @@
+/** @file
+  System Agent Global NVS Area description protocol implementation.
+
+@copyright
+  Copyright (c) 2012 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Mobile Silicon Support Module" and is
+  licensed for Intel Mobile CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement
+**/
+#include "EdkIIGlueDxe.h"
+
+#include "SaGlobalNvsArea.h"
+
+EFI_GUID  gSaGlobalNvsAreaProtocolGuid = SYSTEM_AGENT_GLOBAL_NVS_AREA_PROTOCOL_GUID;
+
+EFI_GUID_STRING
+  (
+    &gSaGlobalNvsAreaProtocolGuid, "System Agent Global NVS Area Protocol",
+      "Protocol describing System Agent ACPI NVS memory region used by ACPI subsystem."
+  );
diff --git a/ReferenceCode/Chipset/SystemAgent/Protocol/SaGlobalNvsArea/SaGlobalNvsArea.h b/ReferenceCode/Chipset/SystemAgent/Protocol/SaGlobalNvsArea/SaGlobalNvsArea.h
new file mode 100644
index 0000000..bc38e5e
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/Protocol/SaGlobalNvsArea/SaGlobalNvsArea.h
@@ -0,0 +1,197 @@
+/** @file
+  Definition of the System Agent global NVS area protocol.  This protocol
+  publishes the address and format of a global ACPI NVS buffer used as a communications
+  buffer between SMM/DXE/PEI code and ASL code.
+  @todo The format is derived from the ACPI reference code, version 0.95.
+
+  Note:  Data structures defined in this protocol are not naturally aligned.
+
+@copyright
+  Copyright (c) 2012 - 2013 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains a 'Sample Driver' and is licensed as such
+  under the terms of your license agreement with Intel or your
+  vendor.  This file may be modified by the user, subject to
+  the additional terms of the license agreement
+**/
+#ifndef _SYSTEM_AGENT_GLOBAL_NVS_AREA_H_
+#define _SYSTEM_AGENT_GLOBAL_NVS_AREA_H_
+
+///
+/// Includes
+///
+///
+/// Forward reference for pure ANSI compatability
+///
+EFI_FORWARD_DECLARATION (SYSTEM_AGENT_GLOBAL_NVS_AREA_PROTOCOL);
+
+///
+/// SA Global NVS Area Protocol GUID
+///
+#define SYSTEM_AGENT_GLOBAL_NVS_AREA_PROTOCOL_GUID \
+  { \
+    0x5bd3336f, 0x5406, 0x48a0, 0xb8, 0x58, 0xd5, 0x0f, 0x72, 0x1c, 0x83, 0x57 \
+  }
+
+///
+/// Extern the GUID for protocol users.
+///
+extern EFI_GUID gSaGlobalNvsAreaProtocolGuid;
+
+///
+/// Global NVS Area definition
+///
+#pragma pack(1)
+typedef struct {
+  UINT32      SaRcRevision;                  ///< 000 SA RC Revision
+  ///
+  /// IGFX relevant fields
+  ///
+  UINT32      IgdOpRegionAddress;            ///< 004 IGD OpRegion Starting Address
+  UINT8       GfxTurboIMON;                  ///< 008 IMON Current Value
+  UINT8       IgdState;                      ///< 009 IGD State (Primary Display = 1)
+  UINT8       CurrentDeviceList;             ///< 010 Current Attached Device List
+  UINT8       PreviousDeviceList;            ///< 011 Previous Attached Device List
+  UINT16      CurrentDisplayState;           ///< 012 Current Display State
+  UINT16      NextDisplayState;              ///< 014 Next Display State
+  UINT32      DeviceId9;                     ///< 016 Device ID 9
+  UINT32      DeviceId10;                    ///< 020 Device ID 10
+  UINT32      DeviceId11;                    ///< 024 Device ID 11
+  UINT8       IgdBootType;                   ///< 028 IGD Boot Type CMOS option
+  UINT8       IgdPanelType;                  ///< 029 IGD Panel Type CMOs option
+  UINT8       IgdPanelScaling;               ///< 030 IGD Panel Scaling
+  UINT8       IgdBlcConfig;                  ///< 031 IGD BLC Configuration
+  UINT8       IgdBiaConfig;                  ///< 032 IGD BIA Configuration
+  UINT8       IgdSscConfig;                  ///< 033 IGD SSC Configuration
+  UINT8       IgdPowerConservation;          ///< 034 IGD Power Conservation Feature Flag
+  UINT8       IgdDvmtMemSize;                ///< 035 IGD DVMT Memory Size
+  UINT8       IgdFunc1Enable;                ///< 036 IGD Function 1 Enable
+  UINT8       IgdHpllVco;                    ///< 037 HPLL VCO
+  UINT32      NextStateDid1;                 ///< 038 Next state DID1 for _DGS
+  UINT32      NextStateDid2;                 ///< 042 Next state DID2 for _DGS
+  UINT32      NextStateDid3;                 ///< 046 Next state DID3 for _DGS
+  UINT32      NextStateDid4;                 ///< 050 Next state DID4 for _DGS
+  UINT32      NextStateDid5;                 ///< 054 Next state DID5 for _DGS
+  UINT32      NextStateDid6;                 ///< 058 Next state DID6 for _DGS
+  UINT32      NextStateDid7;                 ///< 062 Next state DID7 for _DGS
+  UINT32      NextStateDid8;                 ///< 066 Next state DID8 for _DGS
+  UINT8       IgdSciSmiMode;                 ///< 070 GMCH SMI/SCI mode (0=SCI)
+  UINT8       IgdPAVP;                       ///< 071 IGD PAVP data
+  UINT8       LidState;                      ///< 072 Open = 1
+  UINT32      AKsv0;                         ///< 073 First four bytes of AKSV (manufacturing mode)
+  UINT8       AKsv1;                         ///< 077 Fifth byte of AKSV (manufacturing mode)
+  UINT32      IgfxD3F0BarBaseAddress;        ///< 078 IGFX Audio D3F0 BAR Base Address
+  ///
+  /// Backlight Control Values
+  ///
+  UINT8       BacklightControlSupport;       ///< 082 Backlight Control Support
+  UINT8       BrightnessPercentage;          ///< 083 Brightness Level Percentage
+  ///
+  /// Ambient Light Sensor Values
+  ///
+  UINT8       AlsEnable;                     ///< 084 Ambient Light Sensor Enable
+  UINT8       AlsAdjustmentFactor;           ///< 085 Ambient Light Adjusment Factor
+  UINT8       LuxLowValue;                   ///< 086 LUX Low Value
+  UINT8       LuxHighValue;                  ///< 087 LUX High Value
+  UINT8       ActiveLFP;                     ///< 088 Active LFP
+  UINT32      AudioWaA;                      ///< 089 Audio MMIO WA 1
+  UINT32      AudioWaB;                      ///< 093 Audio MMIO WA 2
+  UINT32      AudioWaC;                      ///< 097 Audio MMIO WA 3
+  UINT32      DeviceId12;                    ///< 101 Device ID 12
+  UINT32      DeviceId13;                    ///< 105 Device ID 13
+  UINT32      DeviceId14;                    ///< 109 Device ID 14
+  UINT32      DeviceId15;                    ///< 113 Device ID 15
+  UINT32      AudioCodecSaveAddress;         ///< 117 Codec Save Address
+  UINT32      AudioCodecSaveCount;           ///< 121 Codec Save Count
+  ///
+  /// Add any IGFX relevant fields here and reduce reserved bytes
+  ///
+  UINT8       ReservedIgd[75];              ///< 125:199
+
+  ///
+  /// Switchable Graphics Info
+  ///
+  UINT8       SgMode;                        ///< 200 SG Mode (0=Disabled, 1=SG Muxed, 2=SG Muxless, 3=DGPU Only)
+  UINT8       SgFeatureList;                 ///< 201 SG Feature list
+  UINT8       SgDgpuPwrOK;                   ///< 202 dGPU PWROK GPIO assigned
+  UINT8       SgDgpuHoldRst;                 ///< 203 dGPU HLD RST GPIO assigned
+  UINT8       SgDgpuPwrEnable;               ///< 204 dGPU PWR Enable GPIO assigned
+  UINT8       SgDgpuPrsnt;                   ///< 205 dGPU Present Detect GPIO assigned
+  UINT32      CapStrPresence;                ///< 206 PEG Endpoint Capability Structure Presence
+  UINT8       EndpointPcieCapOffset;         ///< 210 PEG Endpoint PCIe Capability Structure Offset
+  UINT16      EndpointVcCapOffset;           ///< 211 PEG Endpoint Virtual Channel Capability Structure Offset
+  UINT32      XPcieCfgBaseAddress;           ///< 213 Any Device's PCIe Config Space Base Address
+  UINT16      GpioBaseAddress;               ///< 217 GPIO Base Address 
+  UINT8       SgGPIOSupport;                 ///< 219 SG GPIO
+  UINT32      NvIgOpRegionAddress;           ///< 220 NVIG support
+  UINT32      NvHmOpRegionAddress;           ///< 224 NVHM support
+  UINT32      ApXmOpRegionAddress;           ///< 228 AMDA support
+  UINT8       NumberOfValidDeviceId;         ///< 232 Number of Valid Device IDs
+  UINT32      DeviceId1;                     ///< 233 Device ID 1
+  UINT32      DeviceId2;                     ///< 237 Device ID 2
+  UINT32      DeviceId3;                     ///< 241 Device ID 3
+  UINT32      DeviceId4;                     ///< 245 Device ID 4
+  UINT32      DeviceId5;                     ///< 249 Device ID 5
+  UINT32      DeviceId6;                     ///< 253 Device ID 6
+  UINT32      DeviceId7;                     ///< 257 Device ID 7
+  UINT32      DeviceId8;                     ///< 261 Device ID 8
+  UINT32      OccupiedBuses1;                ///< 265 Occupied Buses from 0 to 31
+  UINT32      OccupiedBuses2;                ///< 269 Occupied Buses from 32 to 63
+  UINT32      OccupiedBuses3;                ///< 273 Occupied Buses from 64 to 95
+  UINT32      OccupiedBuses4;                ///< 277 Occupied Buses from 96 to 127
+  UINT32      OccupiedBuses5;                ///< 281 Occupied Buses from 128 to 159
+  UINT32      OccupiedBuses6;                ///< 285 Occupied Buses from 160 to 191
+  UINT32      OccupiedBuses7;                ///< 289 Occupied Buses from 192 to 223
+  UINT32      OccupiedBuses8;                ///< 293 Occupied Buses from 224 to 255
+  UINT8       Peg0LtrEnable;                 ///< 297 Latency Tolerance Reporting Control for PEG(0:1:0)
+  UINT8       Peg0ObffEnable;                ///< 298 Optimized Buffer Flush and Fill for PEG(0:1:0)
+  UINT8       Peg1LtrEnable;                 ///< 299 Latency Tolerance Reporting Control for PEG(0:1:1)
+  UINT8       Peg1ObffEnable;                ///< 300 Optimized Buffer Flush and Fill for PEG(0:1:1)
+  UINT8       Peg2LtrEnable;                 ///< 301 Latency Tolerance Reporting Control for PEG(0:1:2)
+  UINT8       Peg2ObffEnable;                ///< 302 Optimized Buffer Flush and Fill for PEG(0:1:2)
+  UINT16      PegLtrMaxSnoopLatency;         ///< 303 SA Peg Latency Tolerance Reporting Control
+  UINT16      PegLtrMaxNoSnoopLatency;       ///< 305 SA Peg Latency Tolerance Reporting Control
+  UINT8       Peg0PowerDownUnusedBundles;    ///< 307 Peg0 Unused Bundle Control
+  UINT8       Peg1PowerDownUnusedBundles;    ///< 308 Peg1 Unused Bundle Control
+  UINT8       Peg2PowerDownUnusedBundles;    ///< 309 Peg2 Unused Bundle Control
+  UINT8       EdpValid;                      ///< 310 Check for eDP display device
+  UINT32      NextStateDidEdp;               ///< 311 Next state DID for eDP
+  UINT32      DeviceIdX;                     ///< 315 Device ID for eDP device
+  UINT8       PackageCstateLimit;            ///< 319 The lowest C-state for the package
+  UINT8       C7Allowed;                     ///< 316 Run-time C7 Allowed feature (0=Disabled, 1=Enabled)
+  //
+  // Add any other HG Board Info or anything else here
+  //
+// AMI_OVERRIDE...
+  UINT8       SgDgpuDisplaySel;              ///< 319 dGPU Display Select GPIO assigned
+  UINT8       SgDgpuEdidSel;                 ///< 320 dGPU EDID Select GPIO assigned
+  UINT8       SgDgpuPwmSel;                  ///< 321 dGPU PWM Select GPIO assigned
+  UINT32      SgMuxDid1;                     ///< 322 DID1 Mux Setting
+  UINT32      SgMuxDid2;                     ///< 326 DID2 Mux Setting
+  UINT32      SgMuxDid3;                     ///< 330 DID3 Mux Setting
+  UINT32      SgMuxDid4;                     ///< 334 DID4 Mux Setting
+  UINT32      SgMuxDid5;                     ///< 338 DID5 Mux Setting
+  UINT32      SgMuxDid6;                     ///< 342 DID6 Mux Setting
+  UINT32      SgMuxDid7;                     ///< 346 DID7 Mux Setting
+  UINT32      SgMuxDid8;                     ///< 350 DID8 Mux Setting
+  UINT8       PXFixedDynamicMode;            ///< 354 ATI 5.0 Fixed/Dynamic ATI 5.0 Fixed/Dynamic
+  UINT32      EndpointBaseAddress;           ///< 355 Endpoint PCIe Base Address
+  UINT32      DgpuSsid;                      ///< 359 dGPU SSID for MSHyBrid restore
+// AMI_OVERRIDE...end
+} SYSTEM_AGENT_GLOBAL_NVS_AREA;
+#pragma pack()
+///
+/// System Agent Global NVS Area Protocol
+///
+typedef struct _SYSTEM_AGENT_GLOBAL_NVS_AREA_PROTOCOL {
+  SYSTEM_AGENT_GLOBAL_NVS_AREA *Area;
+} SYSTEM_AGENT_GLOBAL_NVS_AREA_PROTOCOL;
+
+#endif
diff --git a/ReferenceCode/Chipset/SystemAgent/Protocol/SaInfo/SaInfo.c b/ReferenceCode/Chipset/SystemAgent/Protocol/SaInfo/SaInfo.c
new file mode 100644
index 0000000..4ca46f3
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/Protocol/SaInfo/SaInfo.c
@@ -0,0 +1,41 @@
+/** @file
+  This file defines the Sa Info Protocol.
+
+@copyright
+  Copyright (c) 2010 - 2012 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains a 'Sample Driver' and is licensed as such
+  under the terms of your license agreement with Intel or your
+  vendor.  This file may be modified by the user, subject to
+  the additional terms of the license agreement
+**/
+
+///
+/// Statements that include other files
+///
+///
+/// External include files do NOT need to be explicitly specified in real EDKII
+/// environment
+///
+#if !defined(EDK_RELEASE_VERSION) || (EDK_RELEASE_VERSION < 0x00020000)
+#include "EdkIIGlueDxe.h"
+#endif
+
+#include "SaInfo.h"
+
+///
+/// Protocol GUID definition
+///
+EFI_GUID  gEfiSaInfoProtocolGuid = EFI_SA_INFO_PROTOCOL_GUID;
+
+///
+/// Protocol description
+///
+EFI_GUID_STRING(&gEfiSaInfoProtocolGuid, "Sa Info Protocol", "Sa Information Protocol");
diff --git a/ReferenceCode/Chipset/SystemAgent/Protocol/SaInfo/SaInfo.h b/ReferenceCode/Chipset/SystemAgent/Protocol/SaInfo/SaInfo.h
new file mode 100644
index 0000000..7469119
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/Protocol/SaInfo/SaInfo.h
@@ -0,0 +1,70 @@
+/** @file
+  This file defines the SA Info Protocol.
+
+@copyright
+  Copyright (c) 2011 - 2014 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains a 'Sample Driver' and is licensed as such
+  under the terms of your license agreement with Intel or your
+  vendor.  This file may be modified by the user, subject to
+  the additional terms of the license agreement
+**/
+#ifndef _SA_INFO_H_
+#define _SA_INFO_H_
+
+///
+/// Define SA INFO protocol GUID
+///
+/// EDK and EDKII have different GUID formats
+///
+#if !defined(EDK_RELEASE_VERSION) || (EDK_RELEASE_VERSION < 0x00020000)
+#define EFI_SA_INFO_PROTOCOL_GUID \
+  { \
+    0x493b5bac, 0xbb9e, 0x4bf5, 0x83, 0x79, 0x20, 0xe2, 0xac, 0xa9, 0x85, 0x41 \
+  }
+
+#else
+#define EFI_SA_INFO_PROTOCOL_GUID \
+  { \
+    0x493b5bac, 0xbb9e, 0x4bf5, \
+    { \
+      0x83, 0x79, 0x20, 0xe2, 0xac, 0xa9, 0x85, 0x41 \
+    } \
+  }
+#endif
+///
+/// Extern the GUID for protocol users.
+///
+extern EFI_GUID                       gEfiSaInfoProtocolGuid;
+
+//
+// Forward reference for ANSI C compatibility
+//
+typedef struct _EFI_SA_INFO_PROTOCOL  EFI_SA_INFO_PROTOCOL;
+
+///
+/// Protocol revision number
+/// Any backwards compatible changes to this protocol will result in an update in the revision number
+/// Major changes will require publication of a new protocol
+///
+/// Revision 1:  Original version
+///
+#define SA_INFO_PROTOCOL_REVISION_1 1
+#define SA_RC_VERSION               0x01090000
+
+///
+/// Protocol definition
+///
+struct _EFI_SA_INFO_PROTOCOL {
+  UINT8   Revision;
+  UINT32  RCVersion;
+};
+
+#endif
diff --git a/ReferenceCode/Chipset/SystemAgent/Protocol/SaPlatformPolicy/SaPlatformPolicy.c b/ReferenceCode/Chipset/SystemAgent/Protocol/SaPlatformPolicy/SaPlatformPolicy.c
new file mode 100644
index 0000000..b843e48
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/Protocol/SaPlatformPolicy/SaPlatformPolicy.c
@@ -0,0 +1,37 @@
+/** @file
+  Interface definition details between SystemAgent and platform drivers during DXE phase.
+
+@copyright
+  Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement
+**/
+#include "Tiano.h"
+
+///
+/// Include the protocol header file
+///
+#include "SaPlatformPolicy.h"
+
+///
+/// Protocol GUID definition
+///
+EFI_GUID  gDxePlatformSaPolicyGuid = DXE_PLATFORM_SA_POLICY_GUID;
+
+///
+/// Protocol description
+///
+EFI_GUID_STRING
+  (&gDxePlatformSaPolicyGuid, "SaPlatformPolicy Protocol", "Intel(R) DXE Phase SA Platform Policy Protocol");
diff --git a/ReferenceCode/Chipset/SystemAgent/Protocol/SaPlatformPolicy/SaPlatformPolicy.h b/ReferenceCode/Chipset/SystemAgent/Protocol/SaPlatformPolicy/SaPlatformPolicy.h
new file mode 100644
index 0000000..5b6793f
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/Protocol/SaPlatformPolicy/SaPlatformPolicy.h
@@ -0,0 +1,366 @@
+/** @file
+  Interface definition details between System Agent and platform drivers during DXE phase.
+
+@copyright
+  Copyright (c) 1999 - 2013 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement
+
+**/
+#ifndef _SA_PLATFORM_POLICY_H_
+#define _SA_PLATFORM_POLICY_H_
+
+#include "SaAccess.h"
+
+///
+/// SA Policy provided by platform for DXE phase {912A2913-42A8-45b0-822F-A94D1EAE9965}
+///
+#define DXE_PLATFORM_SA_POLICY_GUID \
+  { \
+    0x912a2913, 0x42a8, 0x45b0, 0x82, 0x2f, 0xa9, 0x4d, 0x1e, 0xae, 0x99, 0x65 \
+  }
+
+///
+/// Extern the GUID for protocol users.
+///
+extern EFI_GUID gDxePlatformSaPolicyGuid;
+
+///
+/// Protocol revision number
+/// Any backwards compatible changes to this protocol will result in an update in the revision number
+/// Major changes will require publication of a new protocol
+///
+/// Don't change the original DXE_MCH_PLATFORM_POLICY_PROTOCOL_REVISION macro, external
+/// modules maybe have consumed this macro in their source code.  Directly
+/// update the DXE_MCH_PLATFORM_POLICY_PROTOCOL_REVISION version number may cause those
+/// external modules to auto mark themselves wrong version info.
+/// Always create new version macro for new PlatformMchPolicy protocol interface.
+///
+/// DXE_SA_PLATFORM_POLICY_PROTOCOL_REVISION
+///   First version
+///
+#define DXE_SA_PLATFORM_POLICY_PROTOCOL_REVISION    1
+///
+/// DXE_SA_PLATFORM_POLICY_PROTOCOL_REVISION_2
+///   Moved PcieDevsOverride to SampleCode as part of SA_PCIE_CONFIGURATION structure
+///   Added SA_PCIE_CONFIGURATION.PcieLtrDevsOverride
+///
+#define DXE_SA_PLATFORM_POLICY_PROTOCOL_REVISION_2  2
+///
+/// DXE_SA_PLATFORM_POLICY_PROTOCOL_REVISION_3
+///   Added DXE_PLATFORM_SA_POLICY_PROTOCOL.VbiosConfig
+///         SA_IGD_CONFIGURATION.VbtAddress
+///         SA_IGD_CONFIGURATION.Size
+///
+#define DXE_SA_PLATFORM_POLICY_PROTOCOL_REVISION_3  3
+///
+/// DXE_SA_PLATFORM_POLICY_PROTOCOL_REVISION_4
+///   Added SA_IGD_CONFIGURATION.CdClk
+///         SA_IGD_CONFIGURATION.CdClkVar
+///
+#define DXE_SA_PLATFORM_POLICY_PROTOCOL_REVISION_4  4
+///
+/// DXE_SA_PLATFORM_POLICY_PROTOCOL_REVISION_5
+///   Added SA_IGD_CONFIGURATION.PlatformConfig
+///
+#define DXE_SA_PLATFORM_POLICY_PROTOCOL_REVISION_5  5
+///
+/// DXE_SA_PLATFORM_POLICY_PROTOCOL_REVISION_6
+///   Added SA_IGD_CONFIGURATION.IuerStatusVal
+///   Added SA_MISC_CONFIGURATION.SaHdaVerbTableNum
+///         SA_MISC_CONFIGURATION.*SaHdaVerbTable
+///
+#define DXE_SA_PLATFORM_POLICY_PROTOCOL_REVISION_6  6
+///
+/// DXE_SA_PLATFORM_POLICY_PROTOCOL_REVISION_7
+///   Added SA_IGD_CONFIGURATION.GopVersion
+///   Added SA_PCIE_CONFIGURATION.PegPwrOpt[SA_PEG_MAX_FUN]
+///
+#define DXE_SA_PLATFORM_POLICY_PROTOCOL_REVISION_7  7
+///
+/// DXE_SA_PLATFORM_POLICY_PROTOCOL_REVISION_8
+///   Added SA_PCIE_CONFIGURATION.C7Allowed
+///
+#define DXE_SA_PLATFORM_POLICY_PROTOCOL_REVISION_8  8
+
+#define SA_VTD_ENGINE_NUMBER                        2
+#define SA_PCIE_DEV_END_OF_TABLE                    0xFFFF
+///
+/// The data elements should be initialized by a Platform Module.  The data structure is for
+/// VT-d driver initialization
+///
+typedef struct {
+  BOOLEAN               VtdEnable;                         ///< This field is used to describe whether or not the VT-d function should be enabled
+  EFI_PHYSICAL_ADDRESS  *RmrrUsbBaseAddress;               ///< The field is used to describe the platform USB Reserved memory for Intel VT-d support. Platform code should provide this information for Intel VT-d DXE driver use
+  UINT32                BaseAddress[SA_VTD_ENGINE_NUMBER]; ///< This field is used to describe the base addresses for VT-d function
+} SA_VTD_CONFIGURATION;
+
+///
+/// The Memory Configuration includes DIMM SPD address Map and DIMM Slot Mechanical present bit map.
+///
+/// The data elements should be initialized by a Platform Module.  Refer to
+/// $(PROJECT_SA_ROOT)\SmbiosMemory\Dxe\SmbiosMemory.c for the usage.
+///
+typedef struct {
+/**
+  Dimm SPD address
+  Only Server support 2 channels * 3 slots per channel = 6 sockets totally
+  The Desktop and mobile only support 2 channels * 2 slots per channel = 4 sockets totally
+  So there is mapping rule here for Desktop and mobile that there are no more 4 DIMMS totally in a system:
+    Channel A/ Slot 0 --> Dimm 0 --> SpdAddressTable[0]
+    Channel A/ Slot 1 --> Dimm 1 --> SpdAddressTable[1]
+    Channel B/ Slot 0 --> Dimm 2 --> SpdAddressTable[2]
+    Channel B/ Slot 1 --> Dimm 3 --> SpdAddressTable[3]
+  Refer to $(PROJECT_SA_ROOT)\SmbiosMemory\Dxe\SmbiosMemory.c for use
+  If change the mapping rule, please update the Revision number.
+**/
+  UINT8 *SpdAddressTable;
+/**
+  Channel A DIMM Slot Mechanical present bit map, bit 0 -> DIMM 0, bit 1 -> DIMM1, ...
+  if the bit is 1, the related DIMM slot is present.
+  E.g. if channel A has 2 DIMMs,  ChannelASlotMap = 0x03;
+  E.g. if channel A has only 1 DIMMs,  ChannelASlotMap = 0x01;
+  Refer to $(PROJECT_SA_ROOT)\SmbiosMemory\Dxe\SmbiosMemory.c
+**/
+  UINT8 ChannelASlotMap;
+/**
+  Channel B DIMM Slot Mechanical present bit map, bit 0 -> DIMM 0, bit 1 -> DIMM1, ...
+  if the bit is 1, the related DIMM slot is present.
+  E.g. if channel B has 2 DIMMs,  ChannelBSlotMap = 0x03;
+  E.g. if channel B has only 1 DIMMs,  ChannelBSlotMap = 0x01;
+  Refer to $(PROJECT_SA_ROOT)\SmbiosMemory\Dxe\SmbiosMemory.c
+**/
+  UINT8 ChannelBSlotMap;
+  UINT8 RmtBdatEnable;    ///< This flag is used by the MRC for DDR3 channel training (default is false). Please refer to the MRC documentation for more details
+  UINT8 MrcTimeMeasure;   ///< Time measure
+  UINT8 MrcFastBoot;      ///< Fast boot
+} SA_MEMORY_CONFIGURATION;
+
+///
+/// The value before AutoConfig match the setting of PCI Express Base Specification 1.1, please be careful for adding new feature
+///
+typedef enum {
+  PcieAspmDisabled,
+  PcieAspmL0s,
+  PcieAspmL1,
+  PcieAspmL0sL1,
+  PcieAspmAutoConfig,
+  PcieAspmMax
+} SA_PCIE_ASPM_CONFIG;
+
+///
+/// Device List Structure
+///
+typedef struct {
+  UINT16  VendorId; ///< PCI Configuration space offset 0
+  UINT16  DeviceId; ///< PCI Configuration space offset 2
+  UINT8   RevId;    ///< PCI Configuration space offset 8; 0xFF means all steppings
+  UINT8   RootApmcMask;
+  UINT8   EndpointApmcMask;
+} PCIE_ASPM_DEV_INFO;
+
+typedef struct {
+  UINT16  VendorId; ///< PCI Config space offset 0
+  UINT16  DeviceId; ///< PCI Config space offset 2
+  UINT8   RevId;    ///< PCI Config space offset 8; 0xFF means all steppings
+/**
+  SnoopLatency bit definition
+  Note: All Reserved bits must be set to 0
+
+  BIT[15]     - When set to 1b, indicates that the values in bits 9:0 are valid
+                When clear values in bits 9:0 will be ignored
+  BIT[14]     - Should be set to 0b
+  BIT[13]     - Reserved
+  BITS[12:10] - Value in bits 9:0 will be multiplied with the scale in these bits
+                000b - 1 ns
+                001b - 32 ns
+                010b - 1024 ns
+                011b - 32,768 ns
+                100b - 1,048,576 ns
+                101b - 33,554,432 ns
+                110b - Reserved
+                111b - Reserved
+  BITS[9:0]   - Snoop Latency Value. The value in these bits will be multiplied with
+                the scale in bits 12:10
+**/
+  UINT16  SnoopLatency;
+/**
+  NonSnoopLatency bit definition
+  Note: All Reserved bits must be set to 0
+
+  BIT[15]     - When set to 1b, indicates that the values in bits 9:0 are valid
+                When clear values in bits 9:0 will be ignored
+  BIT[14]     - Should be set to 0b
+  BIT[13]     - Reserved
+  BITS[12:10] - Value in bits 9:0 will be multiplied with the scale in these bits
+                000b - 1 ns
+                001b - 32 ns
+                010b - 1024 ns
+                011b - 32,768 ns
+                100b - 1,048,576 ns
+                101b - 33,554,432 ns
+                110b - Reserved
+                111b - Reserved
+  BITS[9:0]   - Non Snoop Latency Value. The value in these bits will be multiplied with
+                the scale in bits 12:10
+**/
+  UINT16  NonSnoopLatency;
+} PCIE_LTR_DEV_INFO;
+
+///
+/// PCIE Power Optimizer config
+///
+typedef struct {
+  UINT8   LtrEnable;
+  UINT16  LtrMaxSnoopLatency;
+  UINT16  LtrMaxNoSnoopLatency;
+  UINT8   ObffEnable;
+} SA_PCIE_PWR_OPT;
+
+
+///
+/// The PCI Express Configuration info includes PCI Resources Range Base and Limits and the control
+/// for PEG ASPM.
+///
+/// The data elements should be initialized by a Platform Module.  For the data structure for PCI IO
+/// and PCI Memory address range info refer to $(PROJECT_SA_ROOT)\PciHostBridge\Dxe\PciHostBridge.c
+/// for the usage.
+///
+typedef struct {
+  SA_PCIE_ASPM_CONFIG DmiAspm;                       ///< This field is used to describe the ASPM control for DMI
+  SA_PCIE_ASPM_CONFIG PegAspm[SA_PEG_MAX_FUN];       ///< This field is used to describe the ASPM control for PEG Ports
+  UINT8               PegAspmL0s[SA_PEG_MAX_FUN];    ///< This field is used to describe the PEG L0s advanced control
+  UINT8               PegDeEmphasis[SA_PEG_MAX_FUN]; ///< This field is used to describe the DeEmphasis control for PEG (-6 dB and -3.5 dB are the options)
+  BOOLEAN             DmiExtSync;                    ///< This field is used to describe the DMI Extended Sync enable/disable control
+  UINT8               DmiDeEmphasis;                 ///< This field is used to describe the DeEmphasis control for DMI (-6 dB and -3.5 dB are the options)
+  BOOLEAN             DmiIot;                        ///< This field is used to describe the IOT control for DMI, default is 0
+  UINT8               C7Allowed;                     ///< Enable/Disable C7 allowed for PEG Ports [Run-time control]. 0=Disable (default) and 1=Enable
+  ///
+  /// This field is used as a pointer to the ASPM device override table, default points to an
+  /// existing table, mPcieAspmDevsOverride, in the sample code. Refer to
+  /// $(PROJECT_SA_ROOT)\Protocol\SaPlatformPolicy\SaPlatformPolicy.h and
+  /// $(PROJECT_SA_ROOT)\SampleCode\SaPolicyInit\Dxe\SaDxePolicyInit.c for the usage.
+  ///
+  /// Note:  This exclusion list helps avoid potential system hangs.
+  ///
+  PCIE_ASPM_DEV_INFO  *PcieAspmDevsOverride;
+  ///
+  /// This field is used as a pointer to the LTR device override table, default points to an existing
+  /// table, mPcieLtrDevsOverride, in the sample code. Refer to
+  /// $(PROJECT_SA_ROOT)\Protocol\SaPlatformPolicy\SaPlatformPolicy.h and
+  /// $(PROJECT_SA_ROOT)\SampleCode\SaPolicyInit\Dxe\SaDxePolicyInit.c for the usage.
+  ///
+  PCIE_LTR_DEV_INFO   *PcieLtrDevsOverride;
+  SA_PCIE_PWR_OPT     PegPwrOpt[SA_PEG_MAX_FUN];     ///< This field is used to describe the PCIe LTR/OBFF relevant settings
+} SA_PCIE_CONFIGURATION;
+
+///
+/// Audio Codec Verb Table
+///
+typedef struct {
+  UINT32  VendorDeviceId;
+  UINT16  SubSystemId;
+  UINT8   RevisionId; ///< 0xFF applies to all steppings
+  UINT8   FrontPanelSupport;
+  UINT16  NumberOfRearJacks;
+  UINT16  NumberOfFrontJacks;
+} SA_HDA_VERB_TABLE_HEADER;
+
+typedef struct {
+  SA_HDA_VERB_TABLE_HEADER  VerbTableHeader;
+  UINT32                    *VerbTableData;
+} SA_HDA_VERB_TABLE;
+
+///
+/// This data structure includes IGD related configuration Variables. The data elements should
+/// be initialized by a Platform Module.
+///
+typedef struct {
+  UINT8                 RenderStandby;     ///< This field is used to enable or disable RC6 (Render Standby)
+  UINT8                 DeepRenderStandby; ///< @deprecated
+  EFI_PHYSICAL_ADDRESS  VbtAddress;        ///< This field points to the GOP VBT data buffer
+  UINT32                Size;              ///< This field gives the size of the GOP VBT Data buffer
+  UINT8                 CdClk;             ///< This field is used to control the Cd Clock Frequency by the user. 0: 337.5Mhz, 1: 450Mhz, 2: 540Mhz
+  UINT8                 CdClkVar;          ///< This field gives the Cd Clock Frequencies supported by the system.
+  UINT8                 PlatformConfig;    ///< This field gives the Platform Configuration Information (0 = Platform is S0ix Capable for ULT SKUs only, 1 = Platform is not S0ix Capable, 2 = Force Platform is S0ix Capable for All SKUs)
+  UINT32                IuerStatusVal;     ///< This field holds the current status of all the supported Ultrabook events (Intel(R) Ultrabook Event Status bits)
+  CHAR16                GopVersion[0x10];  ///< This field holds the GOP Driver Version. It is an Output Protocol and updated by the RC
+
+} SA_IGD_CONFIGURATION;
+
+///
+/// Subsystem Vendor ID / Subsystem ID
+///
+typedef struct {
+  UINT16  SubSystemVendorId;
+  UINT16  SubSystemId;
+} SA_DEFAULT_SVID_SID;
+
+///
+/// This data structure includes miscellaneous configuration variables such SA thermal device
+/// control. The data elements should be initialized by a Platform Module.
+///
+typedef struct {
+  BOOLEAN             ChapDeviceEnable; ///< This field is used to control enable or disable System Agent device (0,7,0)
+  BOOLEAN             Device4Enable;    ///< This field is used to control enable or disable System Agent device (0,4,0)
+  SA_DEFAULT_SVID_SID *DefaultSvidSid;  ///< This field contains the Subsystem VendorID and Subsystem ID values to program to SA devices
+  BOOLEAN             CridEnable;       ///< This field is used to control enable or disable HSW CRID control (to support Intel(R) SIPP)
+  BOOLEAN             AudioEnable;      ///< This field is used to control enable or disable System Agent device (0,3,0)
+  BOOLEAN             FviReport;        ///< This field is used to control enable or disable of Firmware Version Info (FVI) reporting. 0: Disable; 1: Enable
+  UINT8               FviSmbiosType;    ///< This field is used to control the FVI type reported
+  UINT8               SaHdaVerbTableNum;///< This field gives the number of HD Audio verb tables that are loaded
+  SA_HDA_VERB_TABLE   *SaHdaVerbTable;  ///< This field points to the current HD Audio verb table
+} SA_MISC_CONFIGURATION;
+
+///
+/// This data structure includes Switchable Graphics VBIOS configuration. The data elements
+/// should be initialized by a Platform Module.
+///
+typedef struct {
+  UINT8 LoadVbios    : 1; ///< This field is used to describe if the dGPU VBIOS needs to be loaded
+  UINT8 ExecuteVbios : 1; ///< This field is used to describe if the dGPU VBIOD need to be executed
+  UINT8 VbiosSource  : 1; ///< This field is used to identify the source location of dGPU VBIOS
+  UINT8 Reserved     : 5;
+} SA_SG_VBIOS_CONFIGURATION;
+
+///
+/// SA DXE Platform Policy
+///
+/// The DXE_PLATFORM_SA_POLICY_PROTOCOL producer drvier is recommended to
+/// set all the DXE_PLATFORM_SA_POLICY_PROTOCOL size buffer zero before init any member parameter,
+/// this clear step can make sure no random value for those unknow new version parameters.
+///
+/// Make sure to update the Revision if any change to the protocol, including the existing
+/// internal structure definations
+///
+typedef struct _DXE_PLATFORM_SA_POLICY_PROTOCOL {
+  /// This field specifies the revision of the protocol.  The protocol is expected to change in
+  /// a backwards compatible manner as the chipset configuration options are added or removed.
+  /// Major changes will result in new protocol definitions/GUID.  The protocol producer must update
+  /// this field at build time.
+  ///
+  /// Please ensure to use DXE_SA_PLATFORM_POLICY_PROTOCOL_REVISION macro to define the protocol
+  /// revision as input for this version.
+  ///
+  UINT8                      Revision;
+  SA_VTD_CONFIGURATION       *Vtd;          ///< This field is used to describe the configuration of VT-d function used by System Agent Reference code
+  SA_PCIE_CONFIGURATION      *PcieConfig;   ///< This field is used to describe the PCIE configuration used by System Agent Reference code
+  SA_MEMORY_CONFIGURATION    *MemoryConfig; ///< This field is used to describe the Memory configuration used by System Agent Reference code
+  SA_IGD_CONFIGURATION       *IgdConfig;    ///< This field is used to describe the IGD configuration used by System Agent Reference code
+  SA_MISC_CONFIGURATION      *MiscConfig;   ///< This field is used to describe some miscellaneous configuration used by System Agent Reference code, such as device enable/disable, CRID support, etc
+  SA_SG_VBIOS_CONFIGURATION  *VbiosConfig;  ///< This field is used to describe Switchable Graphics configuration used by System Agent Reference Code
+} DXE_PLATFORM_SA_POLICY_PROTOCOL;
+
+#endif
diff --git a/ReferenceCode/Chipset/SystemAgent/Protocol/SaProtocolLib.cif b/ReferenceCode/Chipset/SystemAgent/Protocol/SaProtocolLib.cif
new file mode 100644
index 0000000..22c0c36
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/Protocol/SaProtocolLib.cif
@@ -0,0 +1,26 @@
+<component>
+	name = "SaProtocolLib"
+	category = ModulePart
+	LocalRoot = "ReferenceCode\Chipset\SystemAgent\Protocol\"
+	RefName = "SaProtocolLib"
+[files]
+"SaProtocolLib.sdl"	
+"SaProtocolLib.mak"	
+"MemInfo\MemInfo.c"	
+"MemInfo\MemInfo.h"	
+"IgdOpRegion\IgdOpRegion.c"	
+"IgdOpRegion\IgdOpRegion.h"	
+"IntelSaProtocolLib.inf"	
+"SaPlatformPolicy\SaPlatformPolicy.c"	
+"SaPlatformPolicy\SaPlatformPolicy.h"	
+"SaInfo\SaInfo.h"	
+"SaInfo\SaInfo.c"	
+"BdatAccess\BdatAccess.h"	
+"BdatAccess\BdatAccess.c"	
+"PlatformGopPolicy\PlatformGopPolicy.c"	
+"PlatformGopPolicy\PlatformGopPolicy.h"	
+"SaGlobalNvsArea\SaGlobalNvsArea.c"	
+"SaGlobalNvsArea\SaGlobalNvsArea.h"	
+"GopComponentName2\GopComponentName2.c"	
+"GopComponentName2\GopComponentName2.h"	
+<endComponent>
diff --git a/ReferenceCode/Chipset/SystemAgent/Protocol/SaProtocolLib.mak b/ReferenceCode/Chipset/SystemAgent/Protocol/SaProtocolLib.mak
new file mode 100644
index 0000000..f858243
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/Protocol/SaProtocolLib.mak
@@ -0,0 +1,20 @@
+# MAK file for the ModulePart:IntelSaProtocolLib
+all : IntelSaProtocolLib
+
+$(BUILD_DIR)\IntelSaProtocolLib.lib : IntelSaProtocolLib
+
+IntelSaProtocolLib : $(BUILD_DIR)\SaProtocolLib.mak IntelSaProtocolLibBin
+
+$(BUILD_DIR)\SaProtocolLib.mak : $(INTEL_SA_PROTOCOL_LIB_DIR)\$(@B).cif $(INTEL_SA_PROTOCOL_LIB_DIR)\$(@B).mak $(BUILD_RULES)
+  $(CIF2MAK) $(INTEL_SA_PROTOCOL_LIB_DIR)\$(@B).cif $(CIF2MAK_DEFAULTS)
+
+IntelSaProtocolLib_INCLUDES =\
+    $(EDK_INCLUDES) \
+    $(INTEL_MCH_INCLUDES)
+
+IntelSaProtocolLibBin : 
+    $(MAKE) /$(MAKEFLAGS) $(EDKIIGLUE_DEFAULTS)\
+    /f $(BUILD_DIR)\SaProtocolLib.mak all\
+    "MY_INCLUDES=$(IntelSaProtocolLib_INCLUDES)" \
+    TYPE=LIBRARY \
+    LIBRARY_NAME=$(BUILD_DIR)\IntelSaProtocolLib.lib
\ No newline at end of file
diff --git a/ReferenceCode/Chipset/SystemAgent/Protocol/SaProtocolLib.sdl b/ReferenceCode/Chipset/SystemAgent/Protocol/SaProtocolLib.sdl
new file mode 100644
index 0000000..b5ad7b2
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/Protocol/SaProtocolLib.sdl
@@ -0,0 +1,35 @@
+TOKEN
+  Name  = SaProtocolLib_SUPPORT
+  Value  = 1
+  TokenType = Boolean
+  TargetEQU = Yes
+  TargetMAK = Yes
+  Master = Yes
+  Help  = "Main switch to enable SaProtocolLib support in Project"
+End
+
+MODULE
+  Help  = "Includes SaProtocolLib.mak to Project"
+  File  = "SaProtocolLib.mak"
+End
+
+PATH
+  Name  = "INTEL_SA_PROTOCOL_LIB_DIR"
+End
+
+ELINK
+	Name  = "/I$(INTEL_SA_PROTOCOL_LIB_DIR)"
+	Parent  = "INTEL_MCH_INCLUDES"
+	InvokeOrder = AfterParent
+End
+
+ELINK
+  Name  = "INTEL_SA_PROTOCOL_LIB"
+  InvokeOrder = ReplaceParent
+End
+
+ELINK
+  Name  = "$(BUILD_DIR)\IntelSaProtocolLib.lib"
+  Parent  = "INTEL_SA_PROTOCOL_LIB"
+  InvokeOrder = AfterParent
+End
\ No newline at end of file
diff --git a/ReferenceCode/Chipset/SystemAgent/SaInit/Dxe/AudioInit.c b/ReferenceCode/Chipset/SystemAgent/SaInit/Dxe/AudioInit.c
new file mode 100644
index 0000000..a55603a
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/SaInit/Dxe/AudioInit.c
@@ -0,0 +1,849 @@
+/** @file
+  This is the driver that initializes the CPU Audio device.
+
+@copyright
+  Copyright (c) 1999 - 2013 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement
+
+**/
+
+#include "AudioInit.h"
+
+extern SYSTEM_AGENT_GLOBAL_NVS_AREA_PROTOCOL  mSaGlobalNvsAreaProtocol;
+
+///
+/// Global variables
+///
+UINT32            *mVerbCodecSaveAddress = NULL;
+UINT8             mVerbCount = 0;
+
+UINT32            mSaHdaVerbTableDataDefault[] = {
+  ///
+  /// Audio Verb Table - 0x80862807
+  ///
+  ///
+  /// Pin Widget 5 - PORT B
+  ///
+  0x00571C10,
+  0x00571D00,
+  0x00571E56,
+  0x00571F18,
+  ///
+  /// Pin Widget 6 - PORT C
+  ///
+  0x00671C20,
+  0x00671D00,
+  0x00671E56,
+  0x00671F18,
+  ///
+  /// Pin Widget 7 - PORT D
+  ///
+  0x00771C30,
+  0x00771D00,
+  0x00771E56,
+  0x00771F18
+};
+
+SA_HDA_VERB_TABLE mSaHdaVerbTableDefault[] = {
+  {
+    ///
+    ///  VerbTable:
+    ///  Revision ID = 0xFF
+    ///  Codec Vendor: 0x80862807
+    ///
+    {
+      0x80862807, ///< Vendor ID/Device ID
+      0x0000,     ///< SubSystem ID
+      0xFF,       ///< Revision ID
+      0x02,       ///< Front panel support (1=yes, 2=no)
+      0x0003,     ///< Number of Rear Jacks
+      0x0000      ///< Number of Front Jacks
+    },
+    0             ///< Pointer to verb table data, need to be inited in the code.
+  }
+};
+
+/**
+  Polling the Status bit
+
+  @param[in] StatusReg               The regsiter address to read the status
+  @param[in] PollingBitMap           The bit mapping for polling
+  @param[in] PollingData             The Data for polling
+
+  @retval EFI_SUCCESS                The function completed successfully
+  @retval EFI_TIMEOUT                Polling the bit map time out
+**/
+EFI_STATUS
+StatusPolling (
+  IN      UINT32          StatusReg,
+  IN      UINT16          PollingBitMap,
+  IN      UINT16          PollingData
+  )
+{
+  UINT32  LoopTime;
+
+  for (LoopTime = 0; LoopTime < SA_HDA_MAX_LOOP_TIME; LoopTime++) {
+    if ((MmioRead16 (StatusReg) & PollingBitMap) == PollingData) {
+      break;
+    } else {
+      PchPmTimerStall (SA_HDA_WAIT_PERIOD);
+    }
+  }
+
+  if (LoopTime >= SA_HDA_MAX_LOOP_TIME) {
+    DEBUG ((EFI_D_ERROR, "Polling StatusReg 0x%X BitMap 0x%x TimeOut\n", StatusReg, PollingBitMap));
+    return EFI_TIMEOUT;
+  }
+
+  return EFI_SUCCESS;
+}
+
+/**
+  Send the command to the codec via the Immediate Command mechanism is written
+  to the IC register
+
+  @param[in] HdaBar                  Base address of Intel HD Audio memory mapped configuration registers
+  @param[in, out] CodecCommandData   The Codec Command to be sent to the codec
+  @param[in] ReadBack                Whether to get the response received from the codec
+
+  @exception EFI_DEVICE_ERROR        Device status error, operation failed
+  @retval EFI_SUCCESS                The function completed successfully
+**/
+EFI_STATUS
+SendCodecCommand (
+  IN      UINT32          HdaBar,
+  IN OUT  UINT32          *CodecCommandData,
+  IN      BOOLEAN         ReadBack
+  )
+{
+  EFI_STATUS  Status;
+
+  ///
+  /// Wait for Command Busy (ICB) bit to be cleared
+  ///
+  Status = StatusPolling (HdaBar + R_HDA_IRS, (UINT16) B_HDA_IRS_ICB, (UINT16) 0);
+  if (EFI_ERROR (Status)) {
+    DEBUG ((EFI_D_ERROR, "ICB bit is not zero before SendCodecCommand! \n"));
+    return EFI_DEVICE_ERROR;
+  }
+  ///
+  /// Clear Result Valid (IRV) bit (by writing a one to it) before issuing a new command
+  ///
+  MmioOr16 ((UINTN) (HdaBar + R_HDA_IRS), (UINT16) (B_HDA_IRS_IRV));
+  ///
+  /// Send command to codec
+  ///
+  MmioWrite32 (HdaBar + R_HDA_IC, *CodecCommandData);
+  ///
+  /// Set ICB bit to issue the command currently stored in IC to the codec. 
+  ///
+  MmioOr16 ((UINTN) (HdaBar + R_HDA_IRS), (UINT16) (B_HDA_IRS_ICB));
+  ///
+  /// Wait for Command Busy (ICB) bit to be cleared
+  ///
+  Status = StatusPolling (HdaBar + R_HDA_IRS, (UINT16) B_HDA_IRS_ICB, (UINT16) 0);
+  if (EFI_ERROR (Status)) {
+    MmioAnd16 ((UINTN) (HdaBar + R_HDA_IRS), (UINT16)~(B_HDA_IRS_ICB));
+    return Status;
+  }
+
+  ///
+  /// Save Codec command for runtime code
+  ///
+  if (mVerbCodecSaveAddress != NULL) {
+    if ((mVerbCount * 4) < AUDIO_CODEC_MAX_SIZE) {
+      *(mVerbCodecSaveAddress + mVerbCount) = *CodecCommandData;
+      mVerbCount++;
+      DEBUG ((EFI_D_ERROR, "SendCodecCommand(0x%x): 0x%x \n",(mVerbCodecSaveAddress + (mVerbCount)), *CodecCommandData));
+    } else {
+      DEBUG ((EFI_D_ERROR, "Codec Command Save Area Overflow max value of %d\n", AUDIO_CODEC_MAX_SIZE));
+    }
+  }
+
+  if (ReadBack == TRUE) {
+    if ((MmioRead16 (HdaBar + R_HDA_IRS) & B_HDA_IRS_IRV) != 0) {
+      *CodecCommandData = MmioRead32 (HdaBar + R_HDA_IR);
+    } else {
+      DEBUG ((EFI_D_ERROR, "SendCodecCommand: ReadBack fail! \n"));
+      return EFI_DEVICE_ERROR;
+    }
+  }
+
+  return EFI_SUCCESS;
+}
+
+/**
+  Set a "Send Codec Command" S3 dispatch item
+
+  @param[in] HdaBar                  Base address of Intel HD Audio memory mapped configuration registers
+
+  @retval EFI_SUCCESS                The function completed successfully
+**/
+EFI_STATUS
+SendCodecCommandS3Item (
+  IN      UINT32          HdaBar
+  )
+{
+  UINT16  BitMask;
+  UINT16  BitValue;
+  UINT16  Data16And;
+  UINT16  Data16Or;
+
+  ///
+  /// Wait for Command Busy (ICB) bit to be cleared
+  ///
+  BitMask   = (UINT16) B_HDA_IRS_ICB;
+  BitValue  = (UINT16) 0;
+  SCRIPT_MEM_POLL (
+    EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+    EfiBootScriptWidthUint16,
+    HdaBar + R_HDA_IRS,
+    &BitMask,
+    &BitValue,
+    SA_HDA_WAIT_PERIOD,
+    SA_HDA_MAX_LOOP_TIME
+    );
+  ///
+  /// Clear Result Valid (IRV) bit (by writing a one to it) before issuing a new command
+  ///
+    Data16And = 0xFFFF;
+    Data16Or  = (UINT16) (B_HDA_IRS_IRV);
+    SCRIPT_MEM_READ_WRITE (
+      EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+      EfiBootScriptWidthUint16,
+      (UINTN) (HdaBar + R_HDA_IRS),
+      &Data16Or,  /// Data to be ORed
+      &Data16And  /// Data to be ANDed
+      );
+
+  ///
+  /// Send command to codec
+  ///
+  SCRIPT_MEM_WRITE (
+    EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+    EfiBootScriptWidthUint32,
+    (UINTN) (HdaBar + R_HDA_IC),
+    1,
+    (VOID *) (UINTN) (HdaBar + R_HDA_IC)
+    );
+
+  ///
+  /// Set ICB bit to issue the command currently stored in IC to the codec. 
+  ///
+  Data16And = 0xFFFF;
+  Data16Or  = (UINT16) (B_HDA_IRS_ICB );
+  SCRIPT_MEM_READ_WRITE (
+    EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+    EfiBootScriptWidthUint16,
+    (UINTN) (HdaBar + R_HDA_IRS),
+    &Data16Or,  /// Data to be ORed
+    &Data16And  /// Data to be ANDed
+    );
+
+  ///
+  /// Wait for Command Busy (ICB) bit to be cleared
+  ///
+  SCRIPT_MEM_POLL (
+    EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+    EfiBootScriptWidthUint16,
+    HdaBar + R_HDA_IRS,
+    &BitMask,
+    &BitValue,
+    SA_HDA_WAIT_PERIOD,
+    SA_HDA_MAX_LOOP_TIME
+    );
+
+  return EFI_SUCCESS;
+}
+
+/**
+  Detect And Initialize SA Audio Codec
+
+  @param[in] ImageHandle             Handle for the image of this driver
+  @param[in] DxePlatformSaPolicy     SA DxePlatformPolicy protocol
+
+  @retval EFI_SUCCESS - Legacy Region protocol installed
+  @retval Other       - No protocol installed, unload driver.
+**/
+EFI_STATUS
+DetectAndInitializeCodec (
+  IN EFI_HANDLE                      mImageHandle,
+  IN DXE_PLATFORM_SA_POLICY_PROTOCOL *DxePlatformSaPolicy
+  )
+{
+  EFI_STATUS                Status;
+  UINT32                    Index;
+  UINT32                    VendorDeviceId;
+  UINT32                    RevisionId;
+  UINT8                     ByteReg;
+  UINTN                     AudioBase;
+  UINT8                     AudioSDINo;
+  UINT32                    HdaBar;
+  UINT32                    *VerbTable;
+  UINT32                    LoopTime;
+  SA_HDA_VERB_TABLE_HEADER  *VerbHeaderTable;
+  EFI_PHYSICAL_ADDRESS      BaseAddressBarMem;
+  UINT8                     VerbTableNum;
+  UINT32                    Data32And;
+  UINT32                    Data32Or;
+  UINT32                    Data32;
+  UINT32                    CodecCmdData;
+  UINT16                    AudioDeviceId;
+  UINT16                    Data16;
+  UINT16                    BitMask;
+  UINT16                    BitValue;
+  CPU_STEPPING              CpuSteppingId;
+  CPU_FAMILY                CpuFamilyId;
+  UINT16                    IsUlx;
+
+  CpuFamilyId   = GetCpuFamily();
+  CpuSteppingId = GetCpuStepping();
+
+  AudioBase     = MmPciAddress (0, SA_HDA_BUS_NUM, SA_HDA_DEV_NUM, SA_HDA_FUN_NUM, 0);
+  AudioDeviceId = MmioRead16 (AudioBase + PCI_DEVICE_ID_OFFSET);
+
+  ///
+  /// Allocate resource for HDBAR
+  ///
+  BaseAddressBarMem = 0x0FFFFFFFF;
+  Status = gDS->AllocateMemorySpace (
+                  EfiGcdAllocateMaxAddressSearchBottomUp,
+                  EfiGcdMemoryTypeMemoryMappedIo,
+                  14,
+                  SA_HDA_HDBAR_SIZE,
+                  &BaseAddressBarMem,
+                  mImageHandle,
+                  NULL
+                  );
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+  ///
+  /// System BIOS should ensure that the High Definition Audio HDBAR D27:F0:Reg 10-17h contains a valid address value
+  /// and is enabled by setting D3:F0:Reg 04h[1].
+  ///
+  HdaBar = (UINT32) BaseAddressBarMem;
+  MmioWrite32 (AudioBase + SA_HDA_HDBARL, HdaBar);
+  SCRIPT_MEM_WRITE (
+    EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+    EfiBootScriptWidthUint32,
+    (UINTN) (AudioBase + SA_HDA_HDBARL),
+    1,
+    (VOID *) (UINTN) (AudioBase + SA_HDA_HDBARL)
+    );
+
+  MmioWrite32 (AudioBase + SA_HDA_HDBARU, 0);
+  SCRIPT_MEM_WRITE (
+    EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+    EfiBootScriptWidthUint32,
+    (UINTN) (AudioBase + SA_HDA_HDBARU),
+    1,
+    (VOID *) (UINTN) (AudioBase + SA_HDA_HDBARU)
+    );
+
+  MmioOr16 ((UINTN) (AudioBase + PCI_COMMAND_OFFSET), (UINT16) BIT1);
+  SCRIPT_MEM_WRITE (
+    EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+    EfiBootScriptWidthUint16,
+    (UINTN) (AudioBase + PCI_COMMAND_OFFSET),
+    1,
+    (VOID *) (UINTN) (AudioBase + PCI_COMMAND_OFFSET)
+    );
+
+  ///
+  /// AudioWA: Apply until C0, program Chicken bit: set Dev3 mmio 101C bit 29
+  ///
+  if (((CpuFamilyId == EnumCpuHsw) && (CpuSteppingId < EnumHswC0)) ||
+      ((CpuFamilyId == EnumCpuCrw) && (CpuSteppingId < EnumCrwC0))) {
+    Data32And = 0xFFFFFFFF;
+    Data32Or  = (UINT32) (BIT29);
+    MmioOr32 ((UINTN) (HdaBar + 0x101C), Data32Or);
+    SCRIPT_MEM_READ_WRITE (
+      EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+      EfiBootScriptWidthUint32,
+      (UINTN) (HdaBar + 0x101C),
+      &Data32Or,  /// Data to be ORed
+      &Data32And  /// Data to be ANDed
+      );
+  }
+  if (DxePlatformSaPolicy->Revision >=4) {
+    IsUlx = 0;
+    Data16 = McD2PciCfg16 (0x2);
+    if ((Data16 == 0xA0E) || (Data16 == 0xA1E)) {
+      IsUlx = 1;
+    }
+    Data32Or = 4;
+    Data32 = 75;
+    if (DxePlatformSaPolicy->IgdConfig->CdClkVar != 0) {
+      if (DxePlatformSaPolicy->IgdConfig->CdClk == 0) {
+        Data32Or = 16;
+        Data32 = 225;
+      }
+      if (DxePlatformSaPolicy->IgdConfig->CdClk == 2) {
+        Data32Or = 4;
+        Data32 = 90;
+      }
+    }
+    if(IsUlx == 1) {
+      Data32Or = 16;
+      Data32 = 225;
+    }
+    ///
+    /// Program Dev3 EM4 and EM5 MMIO registers [17:00] based on Cd Clk frequency
+    ///
+    Data32And = 0xFFFC0000;
+    Mmio32AndThenOr ((UINTN) HdaBar, 0x100c, Data32And, Data32Or);
+    SCRIPT_MEM_READ_WRITE (
+      EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+      EfiBootScriptWidthUint32,
+      (UINTN) (HdaBar + 0x100c),
+      &Data32Or,  /// Data to be ORed
+      &Data32And  /// Data to be ANDed
+      );
+
+    Data32And = 0xFFFC0000;
+    Data32Or  = Data32;
+    Mmio32AndThenOr ((UINTN) HdaBar, 0x1010, Data32And, Data32Or);
+    SCRIPT_MEM_READ_WRITE (
+      EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+      EfiBootScriptWidthUint32,
+      (UINTN) (HdaBar + 0x1010),
+      &Data32Or,  /// Data to be ORed
+      &Data32And  /// Data to be ANDed
+      );
+  }
+
+  mSaGlobalNvsAreaProtocol.Area->AudioWaA = MmioRead32(HdaBar + 0x1010);
+  mSaGlobalNvsAreaProtocol.Area->AudioWaB = MmioRead32(HdaBar + 0x101C);
+  mSaGlobalNvsAreaProtocol.Area->AudioWaC = MmioRead32(HdaBar + 0x100C);
+
+  ///
+  /// Allocate an ACPI NVS memory buffer for Saving Codec value for Adapter Power on restore
+  /// , zero initialize, and set the pointer in the SA NVS area structure.
+  ///
+  Status = (gBS->AllocatePool) (EfiACPIMemoryNVS, AUDIO_CODEC_MAX_SIZE, (VOID **) &mVerbCodecSaveAddress);
+  if (EFI_ERROR(Status)) {
+	mSaGlobalNvsAreaProtocol.Area->AudioCodecSaveAddress = 0;
+    ASSERT_EFI_ERROR (Status);  
+  } else {
+	ZeroMem ((VOID *) mVerbCodecSaveAddress, AUDIO_CODEC_MAX_SIZE);
+    mSaGlobalNvsAreaProtocol.Area->AudioCodecSaveAddress = (UINT32) (UINTN) (mVerbCodecSaveAddress);
+  }
+  
+  ///
+  /// Codec Initialization Programming Sequence
+  /// System BIOS should also ensure that the Controller Reset# bit of Global Control register
+  /// in memory-mapped space (HDBAR+08h[0]) is set to 1 and read back as 1.
+  /// Deassert the HDA controller RESET# to start up the link
+  ///
+  DEBUG ((EFI_D_INFO, "Codec Initialization...\n"));
+  Data32And = 0xFFFFFFFF;
+  Data32Or  = (UINT32) (B_HDA_GCTL_CRST);
+  MmioOr32 ((UINTN) (HdaBar + R_HDA_GCTL), Data32Or);
+  SCRIPT_MEM_READ_WRITE (
+    EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+    EfiBootScriptWidthUint32,
+    (UINTN) (HdaBar + R_HDA_GCTL),
+    &Data32Or,  /// Data to be ORed
+    &Data32And  /// Data to be ANDed
+    );
+
+  BitMask   = (UINT16) B_HDA_GCTL_CRST;
+  BitValue  = (UINT16) B_HDA_GCTL_CRST;
+  Status    = StatusPolling (HdaBar + R_HDA_GCTL, BitMask, BitValue);
+  SCRIPT_MEM_POLL (
+    EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+    EfiBootScriptWidthUint16,
+    HdaBar + R_HDA_GCTL,
+    &BitMask,
+    &BitValue,
+    SA_HDA_WAIT_PERIOD,
+    SA_HDA_MAX_LOOP_TIME
+    );
+
+  if (EFI_ERROR (Status)) {
+    DEBUG ((EFI_D_ERROR, "Reset SA dHDA Codec - Set Controller Reset# bit and Poll: Time Out - 0! \n"));
+    goto ExitInitAudio;
+  }
+  ///
+  /// Read GCAP and write the same value back to the register once after Controller Reset# bit is set
+  ///
+  Data16 = MmioRead16 (HdaBar + R_HDA_GCAP);
+  MmioWrite16 (HdaBar + R_HDA_GCAP, Data16);
+  SCRIPT_MEM_WRITE (
+    EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+    EfiBootScriptWidthUint16,
+    (UINTN) (HdaBar + R_HDA_GCAP),
+    1,
+    (VOID *) (UINTN) (HdaBar + R_HDA_GCAP)
+    );
+  ///
+  /// Clear the "State Change Status Register" STATESTS bits for
+  /// each of the "SDIN Stat Change Status Flag"
+  ///
+  MmioOr8 ((UINTN) (HdaBar + R_HDA_STATESTS), (UINT8) (SA_HDA_MAX_SID_MASK));
+  SCRIPT_MEM_WRITE (
+    EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+    EfiBootScriptWidthUint8,
+    (UINTN) (HdaBar + R_HDA_STATESTS),
+    1,
+    (VOID *) (UINTN) (HdaBar + R_HDA_STATESTS)
+    );
+  ///
+  /// Turn off the link and poll RESET# bit until it reads back as 0 to get hardware reset report
+  ///
+  Data32And = (UINT32) (~B_HDA_GCTL_CRST);
+  Data32Or  = (UINT32) 0;
+  MmioAnd32 ((UINTN) (HdaBar + R_HDA_GCTL), Data32And);
+  SCRIPT_MEM_READ_WRITE (
+    EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+    EfiBootScriptWidthUint32,
+    (UINTN) (HdaBar + R_HDA_GCTL),
+    &Data32Or,  /// Data to be ORed
+    &Data32And  /// Data to be ANDed
+    );
+
+  BitMask   = (UINT16) B_HDA_GCTL_CRST;
+  BitValue  = 0;
+  Status    = StatusPolling (HdaBar + R_HDA_GCTL, BitMask, BitValue);
+  SCRIPT_MEM_POLL (
+    EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+    EfiBootScriptWidthUint16,
+    HdaBar + R_HDA_GCTL,
+    &BitMask,
+    &BitValue,
+    SA_HDA_WAIT_PERIOD,
+    SA_HDA_MAX_LOOP_TIME
+    );
+
+  if (EFI_ERROR (Status)) {
+    DEBUG ((EFI_D_ERROR, "Reset SA dHDA Codec - Turn off the link and Poll: Time Out - 1! \n"));
+    goto ExitInitAudio;
+  }
+  ///
+  /// Turn on the link and poll RESET# bit until it reads back as 1
+  ///
+  Data32And = 0xFFFFFFFF;
+  Data32Or  = (UINT32) (B_HDA_GCTL_CRST);
+  MmioOr32 ((UINTN) (HdaBar + R_HDA_GCTL), Data32Or);
+  SCRIPT_MEM_READ_WRITE (
+    EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+    EfiBootScriptWidthUint32,
+    (UINTN) (HdaBar + R_HDA_GCTL),
+    &Data32Or,  /// Data to be ORed
+    &Data32And  /// Data to be ANDed
+    );
+  ///
+  /// For some combo card that will need this delay because each codec has different latency to come out from RESET.
+  /// This delay can make sure all codecs be recognized by BIOS after RESET sequence.
+  /// Additional delay might be required to allow codec coming out of reset prior to subsequent operations,
+  /// please contact your codec vendor for detail. When clearing this bit and setting it afterward,
+  /// BIOS must ensure that minimum link timing requirements (minimum RESET# assertion time, etc.) are met..
+  ///
+  PchPmTimerStall (SA_HDA_WAIT_PERIOD);
+  SCRIPT_STALL (EFI_ACPI_S3_RESUME_SCRIPT_TABLE, 300 * STALL_ONE_MICRO_SECOND);
+
+  BitMask   = (UINT16) B_HDA_GCTL_CRST;
+  BitValue  = (UINT16) B_HDA_GCTL_CRST;
+  Status    = StatusPolling (HdaBar + R_HDA_GCTL, BitMask, BitValue);
+  SCRIPT_MEM_POLL (
+    EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+    EfiBootScriptWidthUint16,
+    HdaBar + R_HDA_GCTL,
+    &BitMask,
+    &BitValue,
+    SA_HDA_WAIT_PERIOD,
+    SA_HDA_MAX_LOOP_TIME
+    );
+
+  if (EFI_ERROR (Status)) {
+    DEBUG ((EFI_D_ERROR, "Reset SA dHDA Codec - Turn on the link and Poll: Time Out - 2! \n"));
+    goto ExitInitAudio;
+  }
+  ///
+  /// Read the "State Change Status Register" STATESTS bits twice to find out if any SDIN is connected
+  /// to a codec.
+  ///
+  for (LoopTime = 0, ByteReg = 0, AudioSDINo = 0; LoopTime < SA_HDA_MAX_LOOP_TIME; LoopTime++) {
+    ByteReg = MmioRead8 (HdaBar + R_HDA_STATESTS) & SA_HDA_MAX_SID_MASK;
+    if (ByteReg != 0 && (ByteReg == AudioSDINo)) {
+      break;
+    } else {
+      AudioSDINo = ByteReg;
+    }
+
+    PchPmTimerStall (SA_HDA_WAIT_PERIOD);
+  }
+  ///
+  /// BIT3(1000) -- SDI3
+  /// BIT2(0100) -- SDI2
+  /// BIT1(0010) -- SDI1
+  /// BIT0(0001) -- SDI0
+  ///
+  if (ByteReg == 0) {
+    ///
+    /// No Codec Detected, Turn off the link
+    ///
+    DEBUG ((EFI_D_INFO, "No Codec device is detected.\n"));
+    Data32And = (UINT32) (~B_HDA_GCTL_CRST);
+    Data32Or  = (UINT32) 0;
+    MmioAnd32 ((UINTN) (HdaBar + R_HDA_GCTL), Data32And);
+    SCRIPT_MEM_READ_WRITE (
+      EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+      EfiBootScriptWidthUint32,
+      (UINTN) (HdaBar + R_HDA_GCTL),
+      &Data32Or,  /// Data to be ORed
+      &Data32And  /// Data to be ANDed
+      );
+    Status = EFI_DEVICE_ERROR;
+    goto ExitInitAudio;
+  }
+
+  for (AudioSDINo = 0; AudioSDINo < SA_HDA_MAX_SID_NUMBER; AudioSDINo++, ByteReg >>= 1) {
+    if ((ByteReg & 0x1) == 0) {
+      ///
+      /// SDIx has no Codec Device
+      ///
+      DEBUG ((EFI_D_INFO, "SDI%d has no Codec device.\n", AudioSDINo));
+      continue;
+    }
+    ///
+    /// Verb:  31~28   27  26~20                   19~0
+    ///         CAd    1    NID   Verb Command and data
+    ///       0/1/2
+    ///
+    /// Read the Vendor ID/Device ID pair from the attached codec
+    ///
+    VendorDeviceId  = 0x000F0000 | (AudioSDINo << 28);
+    Status          = SendCodecCommand (HdaBar, &VendorDeviceId, TRUE);
+    if (EFI_ERROR (Status)) {
+      DEBUG ((EFI_D_ERROR, "Read the Codec Vendor ID/Device ID fail! \n"));
+      goto ExitInitAudio;
+    }
+    ///
+    /// Read the Revision ID from the attached codec
+    ///
+    RevisionId  = 0x000F0002 | (AudioSDINo << 28);
+    Status      = SendCodecCommand (HdaBar, &RevisionId, TRUE);
+    if (EFI_ERROR (Status)) {
+      DEBUG ((EFI_D_ERROR, "Read the Codec Revision ID fail! \n"));
+      goto ExitInitAudio;
+    }
+
+    RevisionId = (RevisionId >> 8) & 0xFF;
+
+    ///
+    /// Get the match codec verb table, RevID of 0xFF applies to all steppings.
+    ///
+    if (DxePlatformSaPolicy->MiscConfig->SaHdaVerbTableNum == 0) {
+      ///
+      /// Init Verb Table Data
+      ///
+      DxePlatformSaPolicy->MiscConfig->SaHdaVerbTable[0].VerbTableData = mSaHdaVerbTableDataDefault;
+      DxePlatformSaPolicy->MiscConfig->SaHdaVerbTableNum   = sizeof (mSaHdaVerbTableDefault) / sizeof (SA_HDA_VERB_TABLE);
+    }
+    for (VerbTableNum = 0, VerbHeaderTable = NULL, VerbTable = NULL;
+         VerbTableNum < DxePlatformSaPolicy->MiscConfig->SaHdaVerbTableNum;
+         VerbTableNum++
+        ) {
+      if ((VendorDeviceId == DxePlatformSaPolicy->MiscConfig->SaHdaVerbTable[VerbTableNum].VerbTableHeader.VendorDeviceId) &&
+          (
+            (DxePlatformSaPolicy->MiscConfig->SaHdaVerbTable[VerbTableNum].VerbTableHeader.RevisionId == 0xFF) ||
+          (RevisionId == DxePlatformSaPolicy->MiscConfig->SaHdaVerbTable[VerbTableNum].VerbTableHeader.RevisionId)
+        )
+          ) {
+        VerbHeaderTable = &(DxePlatformSaPolicy->MiscConfig->SaHdaVerbTable[VerbTableNum].VerbTableHeader);
+        VerbTable       = DxePlatformSaPolicy->MiscConfig->SaHdaVerbTable[VerbTableNum].VerbTableData;
+        if (VerbTable == 0) {
+          DEBUG ((EFI_D_ERROR, "VerbTableData of VendorID:0x%X is null.\n", VendorDeviceId));
+          Status = EFI_INVALID_PARAMETER;
+          goto ExitInitAudio;
+        }
+
+        DEBUG ((EFI_D_INFO, "Detected SA HDA Codec with verb table, VendorID = 0x%X", VendorDeviceId));
+        DEBUG ((EFI_D_INFO, " on SDI%d, revision = 0x%0x.\n", AudioSDINo, RevisionId));
+        ///
+        /// Enable 3rd Pin and Converter Widget
+        /// Clear CAd Field
+        ///
+        CodecCmdData = SA_HDA_ENABLE_3RD_PIN_WIDGET;
+        ///
+        /// Program CAd Field per the SDI number got during codec detection
+        ///
+        CodecCmdData |= (UINT32) (AudioSDINo << 28);
+        Status = SendCodecCommand (HdaBar, &CodecCmdData, FALSE);
+        if (EFI_ERROR (Status)) {
+          DEBUG ((EFI_D_ERROR, "Error occurs at loading Verb 0x00878101"));
+          ///
+          /// Skip the verb table loading when find the verb table content is not
+          /// properly matched with the HDA hardware, though IDs match.
+          ///
+          DEBUG (
+            (EFI_D_ERROR,
+            "Detected Codec of VendorID:0x%X, error occurs during loading verb table.\n",
+            VendorDeviceId)
+            );
+          goto ExitInitAudio;
+        }
+
+        SendCodecCommandS3Item (HdaBar);
+        ///
+        /// Send the entire list of verbs in the matching verb table one by one to the codec
+        ///
+        for (Index = 0; Index < (UINT32) ((VerbHeaderTable->NumberOfFrontJacks + VerbHeaderTable->NumberOfRearJacks) * 4); Index++) {
+          ///
+          /// Clear CAd Field
+          ///
+          CodecCmdData = VerbTable[Index] & (UINT32)~(BIT31 | BIT30 | BIT29 | BIT28);
+          ///
+          /// Program CAd Field per the SDI number got during codec detection
+          ///
+          CodecCmdData |= (UINT32) (AudioSDINo << 28);
+          Status = SendCodecCommand (HdaBar, &CodecCmdData, FALSE);
+          if (EFI_ERROR (Status)) {
+            DEBUG ((EFI_D_ERROR, "Error occurs at loading Command Index:%x\n", Index));
+            ///
+            /// Skip the verb table loading when find the verb table content is not
+            /// properly matched with the HDA hardware, though IDs match.
+            ///
+            DEBUG (
+              (EFI_D_ERROR,
+              "Detected Codec of VendorID:0x%X, error occurs during loading verb table.\n",
+              VendorDeviceId)
+              );
+            goto ExitInitAudio;
+          }
+
+          SendCodecCommandS3Item (HdaBar);
+        }
+        ///
+        /// Disable 3rd Pin and Converter Widget
+        /// Clear CAd Field
+        ///
+        CodecCmdData = SA_HDA_DISABLE_3RD_PIN_WIDGET;
+        ///
+        /// Program CAd Field per the SDI number got during codec detection
+        ///
+        CodecCmdData |= (UINT32) (AudioSDINo << 28);
+        Status = SendCodecCommand (HdaBar, &CodecCmdData, FALSE);
+        if (EFI_ERROR (Status)) {
+          DEBUG ((EFI_D_ERROR, "Error occurs at loading verb 0x00878100"));
+          ///
+          /// Skip the verb table loading when find the verb table content is not
+          /// properly matched with the HDA hardware, though IDs match.
+          ///
+          DEBUG (
+            (EFI_D_ERROR,
+            "Detected Codec of VendorID:0x%X, error occurs during loading verb table.\n",
+            VendorDeviceId)
+            );
+          goto ExitInitAudio;
+        }
+
+        SendCodecCommandS3Item (HdaBar);
+
+        DEBUG ((EFI_D_INFO, "Verb Table loading complete to Codec on SDI%d\n", AudioSDINo));
+        break;
+      }
+    }
+
+    if (VerbTableNum >= DxePlatformSaPolicy->MiscConfig->SaHdaVerbTableNum) {
+      DEBUG (
+        (EFI_D_INFO,
+        "Detected SA High Definition Audio Codec, VendorID = 0x%08x on SDI%d,",
+        VendorDeviceId,
+        AudioSDINo)
+        );
+      DEBUG ((EFI_D_INFO, " but no matching verb table found.\n"));
+    }
+  } // end of for
+  Status = EFI_SUCCESS;
+
+ExitInitAudio:
+  ///
+  /// Clear HdaBar and disable memory map access
+  ///
+  MmioAnd16 ((UINTN) (AudioBase + PCI_COMMAND_OFFSET), (UINT16) (~BIT1));
+  SCRIPT_MEM_WRITE (
+    EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+    EfiBootScriptWidthUint16,
+    (UINTN) (AudioBase + PCI_COMMAND_OFFSET),
+    1,
+    (VOID *) (UINTN) (AudioBase + PCI_COMMAND_OFFSET)
+    );
+
+  MmioWrite32 (AudioBase + SA_HDA_HDBARL, 0);
+  SCRIPT_MEM_WRITE (
+    EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+    EfiBootScriptWidthUint32,
+    (UINTN) (AudioBase + SA_HDA_HDBARL),
+    1,
+    (VOID *) (UINTN) (AudioBase + SA_HDA_HDBARL)
+    );
+
+  MmioWrite32 (AudioBase + SA_HDA_HDBARU, 0);
+  SCRIPT_MEM_WRITE (
+    EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+    EfiBootScriptWidthUint32,
+    (UINTN) (AudioBase + SA_HDA_HDBARU),
+    1,
+    (VOID *) (UINTN) (AudioBase + SA_HDA_HDBARU)
+    );
+
+  gDS->FreeMemorySpace (
+        BaseAddressBarMem,
+        SA_HDA_HDBAR_SIZE
+        );
+  ///
+  /// Save the final count of Audio Codec Save data in SA NVS
+  ///
+  mSaGlobalNvsAreaProtocol.Area->AudioCodecSaveCount = mVerbCount;
+
+  return Status;
+}
+
+/**
+  Initialize SystemAgent Audio Device/Codec.
+
+  @param[in] ImageHandle             Handle for the image of this driver
+  @param[in] DxePlatformSaPolicy     SA DxePlatformPolicy protocol
+
+  @retval EFI_SUCCESS - Audio/Codec initialization done
+**/
+EFI_STATUS
+AudioInit (
+  IN EFI_HANDLE                      ImageHandle,
+  IN DXE_PLATFORM_SA_POLICY_PROTOCOL *DxePlatformSaPolicy
+  )
+{
+  EFI_STATUS  Status;
+
+  if ((DxePlatformSaPolicy->MiscConfig->AudioEnable == 0) || (McD2PciCfg16 (R_SA_IGD_VID) == 0xFFFF)) {
+    DEBUG ((
+      EFI_D_INFO, "Skip Audio Initialization when BIOS option set to disable Or iGfx is not enabled.\n"
+      )
+      );
+    return EFI_SUCCESS;
+  }
+
+  Status = DetectAndInitializeCodec (ImageHandle, DxePlatformSaPolicy);
+  if (EFI_ERROR (Status)) {
+    DEBUG ((EFI_D_ERROR, "SA Audio Codec initialization failure!\n"));
+  }
+
+  DEBUG ((EFI_D_INFO, "AudioInit() End\n"));
+  return EFI_SUCCESS;
+}
diff --git a/ReferenceCode/Chipset/SystemAgent/SaInit/Dxe/AudioInit.h b/ReferenceCode/Chipset/SystemAgent/SaInit/Dxe/AudioInit.h
new file mode 100644
index 0000000..cd7bc33
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/SaInit/Dxe/AudioInit.h
@@ -0,0 +1,66 @@
+/** @file
+  Header file for initialization of CPU Audio device.
+
+@copyright
+  Copyright (c) 1999 - 2013 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement
+**/
+#ifndef _AUDIO_INIT_H_
+#define _AUDIO_INIT_H_
+
+#include "EdkIIGlueDxe.h"
+#include "Pci22.h"
+#include "SaAccess.h"
+#include "PchAccess.h"
+#include "PchPlatformLib.h"
+#include "EfiScriptLib.h"
+#include "CpuRegs.h"
+#include "CpuPlatformLib.h"
+
+#include EFI_PROTOCOL_DEPENDENCY (BootScriptSave)
+#include EFI_PROTOCOL_DEFINITION (SaPlatformPolicy)
+#include EFI_PROTOCOL_DEFINITION (PciHostBridgeResourceAllocation)
+#include EFI_PROTOCOL_DEPENDENCY (SaGlobalNvsArea)
+
+#define SA_HDA_MAX_LOOP_TIME  10
+#define SA_HDA_WAIT_PERIOD    100
+#define SA_HDA_MAX_SID_NUMBER 4
+#define SA_HDA_MAX_SID_MASK   ((1 << SA_HDA_MAX_SID_NUMBER) - 1)
+
+#define AUDIO_CODEC_MAX_SIZE  0x80
+
+#define SA_HDA_ENABLE_3RD_PIN_WIDGET  0x00878101
+#define SA_HDA_DISABLE_3RD_PIN_WIDGET 0x00878100
+
+///
+/// Functions
+///
+/**
+  Initialize SystemAgent Audio Device/Codec.
+
+  @param[in] ImageHandle             Handle for the image of this driver
+  @param[in] DxePlatformSaPolicy     SA DxePlatformPolicy protocol
+
+  @retval EFI_SUCCESS - Audio/Codec initialization Done.
+**/
+EFI_STATUS
+AudioInit (
+  IN EFI_HANDLE                      ImageHandle,
+  IN DXE_PLATFORM_SA_POLICY_PROTOCOL *DxePlatformSaPolicy
+  )
+;
+
+#endif
diff --git a/ReferenceCode/Chipset/SystemAgent/SaInit/Dxe/LegacyRegion.c b/ReferenceCode/Chipset/SystemAgent/SaInit/Dxe/LegacyRegion.c
new file mode 100644
index 0000000..5c91336
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/SaInit/Dxe/LegacyRegion.c
@@ -0,0 +1,368 @@
+/** @file
+  This code provides a private implementation of the Legacy Region protocol.
+
+@copyright
+  Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement
+
+**/
+#include "LegacyRegion.h"
+
+///
+/// Module Global:
+///   Since this driver will only ever produce one instance of the Private Data
+///   protocol you are not required to dynamically allocate the PrivateData.
+///
+LEGACY_REGION_INSTANCE        mPrivateData;
+
+UINT8                         mRomData[16] = {
+  0x00,
+  0x00,
+  0x00,
+  0x00,
+  0x00,
+  0x00,
+  0x00,
+  0x00,
+  0x00,
+  0x00,
+  0x00,
+  0x00,
+  0x00,
+  0x00,
+  0x00,
+  0x00
+};
+
+UINT8                         mLockData[16] = {
+  0x01,
+  0x10,
+  0x01,
+  0x10,
+  0x01,
+  0x10,
+  0x01,
+  0x10,
+  0x01,
+  0x10,
+  0x01,
+  0x10, /// it was: 0x03, 0x30, 0x03, 0x30, <-- why ??
+  0x10,
+  0x10,
+  0x10,
+  0x10
+};
+
+UINT8                         mUnlockData[16] = {
+  0x03,
+  0x30,
+  0x03,
+  0x30,
+  0x03,
+  0x30,
+  0x03,
+  0x30,
+  0x03,
+  0x30,
+  0x03,
+  0x30,
+  0x30,
+  0x30,
+  0x30,
+  0x30
+};
+
+UINT8                         mMaskData[16] = {
+  0x30,
+  0x03,
+  0x30,
+  0x03,
+  0x30,
+  0x03,
+  0x30,
+  0x03,
+  0x30,
+  0x03,
+  0x30,
+  0x03,
+  0x00,
+  0x00,
+  0x00,
+  0x00
+};
+
+UINT8                         mReg[16] = {
+  R_SA_PAM1,
+  R_SA_PAM1,
+  R_SA_PAM2,
+  R_SA_PAM2,
+  R_SA_PAM3,
+  R_SA_PAM3,
+  R_SA_PAM4,
+  R_SA_PAM4,
+  R_SA_PAM5,
+  R_SA_PAM5,
+  R_SA_PAM6,
+  R_SA_PAM6,
+  R_SA_PAM0,
+  R_SA_PAM0,
+  R_SA_PAM0,
+  R_SA_PAM0
+};
+
+EFI_STATUS
+LegacyRegionManipulation (
+  IN  EFI_LEGACY_REGION_PROTOCOL  * This,
+  IN  UINT32                      Start,
+  IN  UINT32                      Length,
+  IN  UINT32                      Mode,
+  OUT UINT32                      *Granularity OPTIONAL
+  )
+/**
+  Modify PAM registers for region specified to MODE state.
+
+  @param[in] This    - Pointer to EFI_LEGACY_REGION_PROTOCOL instance.
+  @param[in] Start   - Starting address of a memory region covered by PAM registers (C0000h - FFFFFh).
+  @param[in] Length  - Memory region length.
+  @param[in] Mode    - Action to perform on a PAM region: UNLOCK, LOCK or BOOTLOCK.
+  @param[out] Granularity - Granularity of region in bytes.
+
+  @retval EFI_SUCCESS - PAM region(s) state modified as requested.
+  @retval EFI_INVALID_PARAMETER - parameter out of boundary
+**/
+{
+  UINT8                           Index;
+  UINT8                           Data;
+  UINT8                           TempData;
+  UINT32                          TempAddr;
+  UINT32                          NewStartAddr;
+  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *Pci;
+  EFI_CPU_ARCH_PROTOCOL           *CpuArch;
+  UINT64                          PciAddress;
+  UINT64                          Attributes;
+  EFI_STATUS                      Status;
+
+  Pci                     = mPrivateData.PciRootBridgeIo;
+  if ((Start  < 0xC0000) ||
+      (Start  > 0xFFFFF) ||
+      (Length > 0x40000) ||
+      ((Start + Length - 1) > 0xFFFFF)) {
+    return EFI_INVALID_PARAMETER;
+  }
+  TempAddr                = Start;
+  Index                   = (UINT8) ((TempAddr - 0xC0000) / PAM_GRANULARITY);
+  NewStartAddr            = TempAddr = (TempAddr / PAM_GRANULARITY) * PAM_GRANULARITY;
+  while (TempAddr <= (Start + Length - 1)) {
+    if (Index >= 16) {
+      return EFI_INVALID_PARAMETER;
+    }
+    if ((Mode == LOCK) || (Mode == BOOTLOCK)) {
+      Data = mLockData[Index];
+    } else {
+      if (Mode == UNLOCK) {
+        Data = mUnlockData[Index];
+      } else {
+        Data = mRomData[Index];
+      }
+    }
+
+    PciAddress = EFI_PCI_ADDRESS (0, 0, 0, mReg[Index]);
+    Pci->Pci.Read (Pci, EfiPciWidthUint8, PciAddress, 1, &TempData);
+    TempData = (UINT8) ((TempData & mMaskData[Index]) | Data);
+    Pci->Pci.Write (Pci, EfiPciWidthUint8, PciAddress, 1, &TempData);
+    TempAddr += PAM_GRANULARITY;
+    Index++;
+  }
+
+  if (Granularity != NULL) {
+    *Granularity = PAM_GRANULARITY;
+  }
+  ///
+  ///  Program the MTRRs
+  ///
+  switch (Mode) {
+
+  case UNLOCK:
+    Attributes = EFI_MEMORY_WT;
+    break;
+
+  case LOCK:
+    Attributes = EFI_MEMORY_WP;
+    break;
+
+  case BOOTLOCK:
+    Attributes = EFI_MEMORY_WP;
+    break;
+
+  default:
+    Attributes = EFI_MEMORY_UC;
+
+  }
+
+  Status = gBS->LocateProtocol (
+                  &gEfiCpuArchProtocolGuid,
+                  NULL,
+                  (VOID **) &CpuArch
+                  );
+  ASSERT_EFI_ERROR (Status);
+  Status = CpuArch->SetMemoryAttributes (
+                      CpuArch,
+                      NewStartAddr,
+                      TempAddr - NewStartAddr,
+                      Attributes
+                      );
+  ASSERT_EFI_ERROR (Status);
+
+  return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EFIAPI
+LegacyRegionDecode (
+  IN  EFI_LEGACY_REGION_PROTOCOL   *This,
+  IN  UINT32                       Start,
+  IN  UINT32                       Length,
+  IN  BOOLEAN                      *On
+  )
+/**
+  Enable/Disable decoding of the given region
+
+  @param[in] This    - Pointer to EFI_LEGACY_REGION_PROTOCOL instance.
+  @param[in] Start  - Starting address of region.
+  @param[in] Length - Length of region in bytes.
+  @param[in] On     - 0 = Disable decoding, 1 = Enable decoding.
+
+  @retval EFI_SUCCESS - Decoding change affected.
+**/
+{
+  UINT32  Granularity;
+  if (*On) {
+    return LegacyRegionManipulation (This, Start, Length, UNLOCK, &Granularity);
+  } else {
+    return LegacyRegionManipulation (This, Start, Length, LEGACY_REGION_DECODE_ROM, &Granularity);
+  }
+}
+
+EFI_STATUS
+EFIAPI
+LegacyRegionBootLock (
+  IN  EFI_LEGACY_REGION_PROTOCOL   * This,
+  IN  UINT32                       Start,
+  IN  UINT32                       Length,
+  OUT UINT32                       *Granularity OPTIONAL
+  )
+/**
+  Make the indicated region read from RAM / write to ROM.
+
+  @param[in] This        - Pointer to EFI_LEGACY_REGION_PROTOCOL instance.
+  @param[in] Start       - Starting address of region.
+  @param[in] Length      - Length of region in bytes.
+  @param[out] Granularity - Granularity of region in bytes.
+
+  @retval EFI_SUCCESS - Region locked or made R/O.
+**/
+{
+  return LegacyRegionManipulation (This, Start, Length, BOOTLOCK, Granularity);
+}
+
+EFI_STATUS
+EFIAPI
+LegacyRegionLock (
+  IN  EFI_LEGACY_REGION_PROTOCOL   * This,
+  IN  UINT32                       Start,
+  IN  UINT32                       Length,
+  OUT UINT32                       *Granularity OPTIONAL
+  )
+/**
+  Make the indicated region read from RAM / write to ROM.
+
+  @param[in] This    - Pointer to EFI_LEGACY_REGION_PROTOCOL instance.
+  @param[in] Start       - Starting address of region.
+  @param[in] Length      - Length of region in bytes.
+  @param[out] Granularity - Granularity of region in bytes.
+
+  @retval EFI_SUCCESS - Region locked or made R/O.
+**/
+{
+  return LegacyRegionManipulation (This, Start, Length, LOCK, Granularity);
+}
+
+EFI_STATUS
+EFIAPI
+LegacyRegionUnlock (
+  IN  EFI_LEGACY_REGION_PROTOCOL   * This,
+  IN  UINT32                       Start,
+  IN  UINT32                       Length,
+  OUT UINT32                       *Granularity OPTIONAL
+  )
+/**
+  Make the indicated region read from RAM / write to RAM.
+
+  @param[in] This    - Pointer to EFI_LEGACY_REGION_PROTOCOL instance.
+  @param[in] Start       - Starting address of region.
+  @param[in] Length      - Length of region in bytes.
+  @param[out] Granularity - Granularity of region in bytes.
+
+  @retval EFI_SUCCESS - Region unlocked or made R/W.
+**/
+{
+  return LegacyRegionManipulation (This, Start, Length, UNLOCK, Granularity);
+}
+
+EFI_STATUS
+LegacyRegionInstall (
+  IN EFI_HANDLE           ImageHandle
+  )
+/**
+  Install Driver to produce Legacy Region protocol.
+
+  @param[in] ImageHandle             Handle for the image of this driver
+
+  @retval EFI_SUCCESS - Legacy Region protocol installed
+  @retval Other       - No protocol installed, unload driver.
+**/
+{
+  EFI_STATUS              Status;
+  LEGACY_REGION_INSTANCE  *Private;
+  Private = &mPrivateData;
+
+  ///
+  /// Grab a copy of all the protocols we depend on. Any error would
+  /// be a dispatcher bug!.
+  ///
+  Status = gBS->LocateProtocol (
+                  &gEfiPciRootBridgeIoProtocolGuid,
+                  NULL,
+                  (VOID **) &Private->PciRootBridgeIo
+                  );
+  Private->Signature              = LEGACY_REGION_INSTANCE_SIGNATURE;
+  Private->LegacyRegion.Decode    = LegacyRegionDecode;
+  Private->LegacyRegion.Lock      = LegacyRegionLock;
+  Private->LegacyRegion.BootLock  = LegacyRegionBootLock;
+  Private->LegacyRegion.UnLock    = LegacyRegionUnlock;
+  Private->ImageHandle            = ImageHandle;
+
+  ///
+  /// Make a new handle and install the protocol
+  ///
+  Private->Handle = NULL;
+  return gBS->InstallProtocolInterface (
+                &Private->Handle,
+                &gEfiLegacyRegionProtocolGuid,
+                EFI_NATIVE_INTERFACE,
+                &Private->LegacyRegion
+                );
+}
diff --git a/ReferenceCode/Chipset/SystemAgent/SaInit/Dxe/LegacyRegion.h b/ReferenceCode/Chipset/SystemAgent/SaInit/Dxe/LegacyRegion.h
new file mode 100644
index 0000000..d2e9b2d
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/SaInit/Dxe/LegacyRegion.h
@@ -0,0 +1,76 @@
+/** @file
+  This code supports a private implementation of the Legacy Region protocol.
+
+@copyright
+  Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement
+**/
+#ifndef _LEGACY_REGION_H_
+#define _LEGACY_REGION_H_
+
+#include "EdkIIGlueDxe.h"
+#include "Pci22.h"
+
+#include EFI_PROTOCOL_PRODUCER (LegacyRegion)
+#include EFI_PROTOCOL_DEFINITION (PciRootBridgeIo)
+#define LEGACY_REGION_INSTANCE_SIGNATURE  EFI_SIGNATURE_32 ('R', 'E', 'G', 'N')
+
+#include EFI_ARCH_PROTOCOL_CONSUMER (Cpu)
+#define LEGACY_REGION_DECODE_ROM  3
+
+#include "SaAccess.h"
+
+///
+/// PAM registers granularity is 16 KB
+///
+#define PAM_GRANULARITY 0x4000
+#define UNLOCK          0x0000
+#define LOCK            0x0001
+#define BOOTLOCK        0x0002
+
+typedef struct {
+  UINT32                          Signature;
+  EFI_HANDLE                      Handle;
+  EFI_LEGACY_REGION_PROTOCOL      LegacyRegion;
+  EFI_HANDLE                      ImageHandle;
+
+  ///
+  /// Protocol for PAM register access
+  ///
+  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;
+} LEGACY_REGION_INSTANCE;
+
+#define LEGACY_REGION_INSTANCE_FROM_THIS  (this) CR (this, \
+                                                     LEGACY_REGION_INSTANCE, \
+                                                     LegacyRegion, \
+                                                     LEGACY_REGION_INSTANCE_SIGNATURE \
+        )
+
+/**
+  Install Driver to produce Legacy Region protocol.
+
+  @param[in] ImageHandle             Handle for the image of this driver
+
+  @retval EFI_SUCCESS - Legacy Region protocol installed
+  @retval Other       - No protocol installed, unload driver.
+**/
+EFI_STATUS
+LegacyRegionInstall (
+  IN EFI_HANDLE           ImageHandle
+  )
+;
+
+#endif
diff --git a/ReferenceCode/Chipset/SystemAgent/SaInit/Dxe/PciExpressInit.c b/ReferenceCode/Chipset/SystemAgent/SaInit/Dxe/PciExpressInit.c
new file mode 100644
index 0000000..921ae94
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/SaInit/Dxe/PciExpressInit.c
@@ -0,0 +1,483 @@
+/** @file
+  This driver does SA PCI Express initialization.
+
+@copyright
+  Copyright (c) 1999 - 2013 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement
+
+**/
+#include "PciExpressInit.h"
+
+extern SYSTEM_AGENT_GLOBAL_NVS_AREA_PROTOCOL  mSaGlobalNvsAreaProtocol;
+
+EFI_STATUS
+PciExpressInit (
+  IN DXE_PLATFORM_SA_POLICY_PROTOCOL *DxePlatformSaPolicy
+  )
+/**
+  PCI Express Dxe Initialization.
+  Run before PCI Bus Init, where assignment of Bus, Memory,
+    and I/O Resources are assigned.
+
+  @param[in] DxePlatformSaPolicy -     SA DxePlatformPolicy protocol
+
+  @retval EFI_SUCCESS     - Pci Express successfully started and ready to be used
+  @exception EFI_UNSUPPORTED - Pci Express can't be initialized
+**/
+{
+  EFI_STATUS  Status;
+  UINT64      EgressPortBar;
+  UINT64      MchBar;
+  UINT64      PciExpressBar;
+  UINT64      DmiBar;
+  UINT32      PchRootComplexBar;
+  CPU_FAMILY  CpuFamilyId;
+  CPU_STEPPING CpuSteppingId;
+
+  CpuFamilyId = GetCpuFamily();
+  CpuSteppingId = GetCpuStepping();
+
+  ///
+  /// The SA Represents Component ID 1 (CID1), while the PCH represents
+  /// Component ID 2 (CID2).  This code will completely configure both Components
+  /// CID1 Integrated Ports:
+  ///    Egress Port = Port 0
+  ///    DMI Port    = Port 1
+  ///    Peg Port10  = Port 2
+  ///    Peg Port11  = Port 3
+  ///    Peg Port12  = Port 4
+  /// CID2 Integated Ports:
+  ///    Egress Port = Port 0
+  ///    Root Port 1 = Port 1
+  ///    Root Port 2 = Port 2
+  ///    Root Port 3 = Port 3
+  ///    Root Port 4 = Port 4
+  ///    Azalia      = Port 5
+  ///
+  ///
+  /// Get BAR registers
+  ///
+  PchRootComplexBar = MmPci32 (0, 0, 31, 0, 0xF0) &~BIT0;
+  PciExpressBar     = McD0PciCfg64 (R_SA_PCIEXBAR) & (B_SA_PCIEXBAR_PCIEXBAR_MASK | B_SA_PCIEXBAR_ADMSK128_MASK | B_SA_PCIEXBAR_ADMSK64_MASK);
+  EgressPortBar     = McD0PciCfg64 (R_SA_PXPEPBAR) &~BIT0;
+  MchBar            = McD0PciCfg64 (R_SA_MCHBAR) &~BIT0;
+  DmiBar            = McD0PciCfg64 (R_SA_DMIBAR) &~BIT0;
+
+  ///
+  /// Configure the Egress Port (0) in CID1
+  ///
+  Status = Cid1EgressPort0Init (EgressPortBar);
+
+#ifdef PEG_FLAG
+  if ((CpuFamilyId == EnumCpuHsw) || (CpuFamilyId == EnumCpuCrw)) {
+    ///
+    /// Configure the PEG Ports in CID1
+    ///
+    Status = Cid1PegPortInit (DxePlatformSaPolicy);
+  }
+#endif // PEG_FLAG
+
+  ///
+  /// Configure the SA DMI Port (1) in CID1 and the PCH DMI Port (0) in CID2.
+  /// Note that both links must be fully configured before the link
+  /// should be checked for negotiation between the 2 CIDs.
+  ///
+  DEBUG ((EFI_D_INFO, " Going to call Cid1Cid2DmiPortInit\n"));
+  Status = Cid1Cid2DmiPortInit (DmiBar, DxePlatformSaPolicy);
+
+  ///
+  /// Configure the RootComplex Topology in CID1.
+  ///
+  DEBUG ((EFI_D_INFO, " Going to call Cid1TopologyInit\n"));
+  Status = Cid1TopologyInit (EgressPortBar, DmiBar, PchRootComplexBar);
+
+  ///
+  /// Configure the RootComplex Topology in CID2.
+  ///
+  DEBUG ((EFI_D_INFO, " Going to call Cid2TopologyInit\n"));
+  Status = Cid2TopologyInit (PchRootComplexBar, DmiBar);
+
+  if (((CpuFamilyId == EnumCpuHsw) && (CpuSteppingId >= EnumHswC0)) ||
+      ((CpuFamilyId == EnumCpuCrw) && (CpuSteppingId >= EnumCrwC0))) {
+    if (DxePlatformSaPolicy->Revision >= DXE_SA_PLATFORM_POLICY_PROTOCOL_REVISION_7) {
+      mSaGlobalNvsAreaProtocol.Area->C7Allowed  = DxePlatformSaPolicy->PcieConfig->C7Allowed; //Update the Run-time C7 Allowed for ASL usage
+    }
+  }
+
+  mSaGlobalNvsAreaProtocol.Area->PackageCstateLimit  = (UINT8)(AsmReadMsr64(MSR_PMG_CST_CONFIG) & B_PACKAGE_C_STATE_LIMIT);
+
+
+  return Status;
+}
+
+UINT32
+PcieFindCapId (
+  IN UINT8   Bus,
+  IN UINT8   Device,
+  IN UINT8   Function,
+  IN UINT8   CapId
+  )
+/**
+  Find the Offset to a given Capabilities ID
+  CAPID list:
+    0x01 = PCI Power Management Interface
+    0x04 = Slot Identification
+    0x05 = MSI Capability
+    0x10 = PCI Express Capability
+
+  @param[in] Bus       -   Pci Bus Number
+  @param[in] Device    -   Pci Device Number
+  @param[in] Function  -   Pci Function Number
+  @param[in] CapId     -   CAPID to search for
+
+  @retval 0       - CAPID not found
+  @retval Other   - CAPID found, Offset of desired CAPID
+**/
+{
+  UINT8 CapHeader;
+
+  ///
+  /// Always start at Offset 0x34
+  ///
+  CapHeader = MmPci8 (0, Bus, Device, Function, PCI_CAPP);
+  if (CapHeader == 0xFF) {
+    return 0;
+  }
+
+  while (CapHeader != 0) {
+    ///
+    /// Bottom 2 bits of the pointers are reserved per PCI Local Bus Spec 2.2
+    ///
+    CapHeader &= ~(BIT1 + BIT0);
+    ///
+    /// Search for desired CapID
+    ///
+    if (MmPci8 (0, Bus, Device, Function, CapHeader) == CapId) {
+      return CapHeader;
+    }
+
+    CapHeader = MmPci8 (0, Bus, Device, Function, CapHeader + 1);
+  }
+
+  return 0;
+}
+
+UINT32
+PcieFindExtendedCapId (
+  IN UINT8   Bus,
+  IN UINT8   Device,
+  IN UINT8   Function,
+  IN UINT16  CapId
+  )
+/**
+  Search and return the offset of desired Pci Express Capability ID
+  CAPID list:
+    0x0001 = Advanced Error Rreporting Capability
+    0x0002 = Virtual Channel Capability
+    0x0003 = Device Serial Number Capability
+    0x0004 = Power Budgeting Capability
+
+  @param[in] Bus       -   Pci Bus Number
+  @param[in] Device    -   Pci Device Number
+  @param[in] Function  -   Pci Function Number
+  @param[in] CapId     -   Extended CAPID to search for
+
+  @retval 0       - CAPID not found
+  @retval Other   - CAPID found, Offset of desired CAPID
+**/
+{
+  UINT16  CapHeaderOffset;
+  UINT16  CapHeaderId;
+
+  ///
+  /// Start to search at Offset 0x100
+  /// Get Capability Header
+  ///
+  CapHeaderId     = 0;
+  CapHeaderOffset = 0x100;
+
+  while (CapHeaderOffset != 0 && CapHeaderId != 0xFFFF) {
+    ///
+    /// Search for desired CapID
+    ///
+    CapHeaderId = MmPci16 (0, Bus, Device, Function, CapHeaderOffset);
+    if (CapHeaderId == CapId) {
+      return CapHeaderOffset;
+    }
+
+    CapHeaderOffset = (MmPci16 (0, Bus, Device, Function, CapHeaderOffset + 2) >> 4);
+  }
+
+  return 0;
+}
+
+VOID
+PcieSetClkreq (
+  IN  UINT8   Bus,
+  IN  UINT8   Device
+  )
+/**
+  This function enables the CLKREQ# PM on all the end point functions
+
+  @param[in] Bus       -   Pci Bus Number
+  @param[in] Device    -   Pci Device Number
+**/
+{
+  UINT8   Function;
+  UINT32  CapOffset;
+
+  ///
+  /// Parse through all the functions of the endpoint and find the PCIe Cap ID (offset 10h) and if
+  /// exists then enable the CLKREQ# bit (BIT8) on that function
+  ///
+  for (Function = 0; Function < 8; Function++) {
+    ///
+    /// Find the PCIe Cap Id (offset 10h)
+    ///
+    CapOffset = PcieFindCapId (Bus, Device, Function, EFI_PCI_CAPABILITY_ID_PCIEXP);
+    if (CapOffset == 0) {
+      continue;
+    }
+    ///
+    /// Check if CLKREQ# is supported by the endpoints
+    ///
+    if ((MmPci32 (0, Bus, Device, Function, (CapOffset + 0x0C)) & BIT18) != BIT18) {
+      ///
+      /// CLKREQ# is not supported so dont do anything
+      ///
+      return ;
+    }
+  }
+  ///
+  /// Now enable the CLKREQ#
+  ///
+  for (Function = 0; Function < 8; Function++) {
+    ///
+    /// Find the PCIe Cap Id (offset 10h)
+    ///
+    CapOffset = PcieFindCapId (Bus, Device, Function, EFI_PCI_CAPABILITY_ID_PCIEXP);
+    if (CapOffset == 0) {
+      continue;
+    }
+
+    MmPci16Or (0, Bus, Device, Function, (CapOffset + 0x010), BIT8);
+  }
+}
+
+VOID
+AdditionalDMIProgramStepsBeforeASPM (
+  IN UINT64                          DmiBar,
+  IN DXE_PLATFORM_SA_POLICY_PROTOCOL *DxePlatformSaPolicy
+  )
+/**
+  Additional DMI Programming Steps as in SA BIOS spec
+
+  @param[in] DmiBar              - DMIBAR Address
+  @param[in] DxePlatformSaPolicy - SA DxePlatformPolicy protocol
+**/
+{
+  UINT32             Data32And;
+  UINT32             Data32Or;
+
+  ///
+  /// Configure the De-emphasis control on DMI
+  ///
+  Data32And = (UINT32) ~BIT6;
+  Data32Or  = (UINT32) ((DxePlatformSaPolicy->PcieConfig->DmiDeEmphasis & 0x1) << 6);
+  Mmio32AndThenOr (DmiBar, R_SA_DMIBAR_LCTL2_OFFSET, Data32And, Data32Or);
+
+  SCRIPT_MEM_READ_WRITE (
+    EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+    EfiBootScriptWidthUint32,
+    (UINTN) (DmiBar + R_SA_DMIBAR_LCTL2_OFFSET),
+    &Data32Or,  ///< Data to be ORed
+    &Data32And  ///< Data to be ANDed
+    );
+
+  ///
+  /// Set 0x22C[31] to 1 before enabling ASPM
+  ///
+  Data32And = (UINT32) ~(BIT31);
+  Data32Or  = (UINT32)   BIT31;
+  Mmio32AndThenOr (DmiBar, R_SA_DMIBAR_L0SLAT_OFFSET, Data32And, Data32Or);
+
+  SCRIPT_MEM_READ_WRITE (
+    EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+    EfiBootScriptWidthUint32,
+    (UINTN) (DmiBar + R_SA_DMIBAR_L0SLAT_OFFSET),
+    &Data32Or,  ///< Data to be ORed
+    &Data32And  ///< Data to be ANDed
+    );
+
+  ///
+  /// Set 0x238 bit29 for DMI before enabling ASPM
+  ///
+  Data32And = 0xFFFFFFFF;
+  Data32Or  = BIT29;
+  Mmio32Or (DmiBar, 0x238, Data32Or);
+
+  SCRIPT_MEM_READ_WRITE (
+    EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+    EfiBootScriptWidthUint32,
+    (UINTN) (DmiBar + 0x238),
+    &Data32Or,  ///< Data to be ORed
+    &Data32And  ///< Data to be ANDed
+    );
+
+  ///
+  /// Set DMI Offset 0xC28 [4:0]
+  ///
+  Data32And = 0xFFFFFFE0;
+  Data32Or  = 0x13;
+  Mmio32AndThenOr (DmiBar, R_SA_PEG_AFE_PM_TMR_OFFSET, Data32And, Data32Or);
+
+  SCRIPT_MEM_READ_WRITE (
+    EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+    EfiBootScriptWidthUint32,
+    (UINTN) (DmiBar + R_SA_PEG_AFE_PM_TMR_OFFSET),
+    &Data32Or,  ///< Data to be ORed
+    &Data32And  ///< Data to be ANDed
+    );
+}
+
+VOID
+AdditionalPEGProgramStepsBeforeASPM (
+  IN  UINT8                          Bus,
+  IN  UINT8                          pegDev,
+  IN  UINT8                          pegFn,
+  IN DXE_PLATFORM_SA_POLICY_PROTOCOL *DxePlatformSaPolicy
+  )
+/**
+  Additional PEG Programming Steps as in SA BIOS spec
+
+  @param[in] Bus         - Pci Bus Number
+  @param[in] pegDev      - Pci Device Number
+  @param[in] pegFn       - Pci Func Number
+  @param[in] DxePlatformSaPolicy - SA DxePlatformPolicy protocol
+**/
+{
+  UINT32             Data32Or;
+  UINT32             Data32And;
+  UINT32             PegBaseAddress;
+
+  PegBaseAddress = (UINT32) MmPciAddress (0x0, Bus, pegDev, pegFn, 0x0);
+
+  ///
+  /// Permanently set PEGUESEV[CTS](0x1CC bit14) to 1b during BIOS boot for all the PEG controllers
+  ///
+  Data32And = 0xFFFFFFFF;
+  Data32Or  = BIT14;
+  Mmio32Or (PegBaseAddress, 0x1CC, Data32Or);
+
+  SCRIPT_MEM_READ_WRITE (
+    EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+    EfiBootScriptWidthUint32,
+    (UINTN) (PegBaseAddress + 0x1CC),
+    &Data32Or,  ///< Data to be ORed
+    &Data32And  ///< Data to be ANDed
+    );
+
+  ///
+  /// Configure the De-emphasis control on PEG
+  ///
+  Data32And = (UINT32)~BIT6;
+  Data32Or  = (DxePlatformSaPolicy->PcieConfig->PegDeEmphasis[pegFn] & BIT0) << 6;
+  Mmio32AndThenOr (PegBaseAddress, R_SA_PEG_LCTL2_OFFSET, Data32And, Data32Or);
+
+  SCRIPT_MEM_READ_WRITE (
+    EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+    EfiBootScriptWidthUint32,
+    (UINTN) (PegBaseAddress + R_SA_PEG_LCTL2_OFFSET),
+    &Data32Or,  ///< Data to be ORed
+    &Data32And  ///< Data to be ANDed
+    );
+
+  ///
+  /// Set 0x22C[31] to 1 before enabling ASPM
+  ///
+  Data32And = (UINT32) ~(BIT31);
+  Data32Or  = (UINT32)   BIT31;
+  Mmio32AndThenOr (PegBaseAddress, R_SA_PEG_L0SLAT_OFFSET, Data32And, Data32Or);
+
+  SCRIPT_MEM_READ_WRITE (
+    EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+    EfiBootScriptWidthUint32,
+    (UINTN) (PegBaseAddress + R_SA_PEG_L0SLAT_OFFSET),
+    &Data32Or,  ///< Data to be ORed
+    &Data32And  ///< Data to be ANDed
+    );
+
+  ///
+  /// Program 0x250 bit[22:20] to 010b for all the PEG controllers before enabling ASPM
+  ///
+  Data32And = (UINT32)~(BIT22 + BIT21 + BIT20);
+  Data32Or  = 0x02 << 20;
+  Mmio32AndThenOr (PegBaseAddress, 0x250, Data32And, Data32Or);
+
+  SCRIPT_MEM_READ_WRITE (
+    EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+    EfiBootScriptWidthUint32,
+    (UINTN) (PegBaseAddress + 0x250),
+    &Data32Or,  ///< Data to be ORed
+    &Data32And  ///< Data to be ANDed
+    );
+
+  ///
+  /// Set 0x238 bit29 for PEG controller before enabling ASPM
+  ///
+  Data32And = 0xFFFFFFFF;
+  Data32Or  = BIT29;
+  Mmio32Or (PegBaseAddress, 0x238, Data32Or);
+
+  SCRIPT_MEM_READ_WRITE (
+    EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+    EfiBootScriptWidthUint32,
+    (UINTN) (PegBaseAddress + 0x238),
+    &Data32Or,  ///< Data to be ORed
+    &Data32And  ///< Data to be ANDed
+    );
+
+  ///
+  /// Set PEG Offset 0x1F8 bit16
+  ///
+  Data32And = 0xFFFFFFFF;
+  Data32Or  = BIT16;
+  Mmio32Or (PegBaseAddress, 0x1F8, Data32Or);
+
+  SCRIPT_MEM_READ_WRITE (
+    EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+    EfiBootScriptWidthUint32,
+    (UINTN) (PegBaseAddress + 0x1F8),
+    &Data32Or,  ///< Data to be ORed
+    &Data32And  ///< Data to be ANDed
+    );
+
+  ///
+  /// Set PEG Offset 0xC28 [4:0]
+  ///
+  Data32And = 0xFFFFFFE0;
+  Data32Or  = 0x13;
+  Mmio32AndThenOr (PegBaseAddress, R_SA_PEG_AFE_PM_TMR_OFFSET, Data32And, Data32Or);
+
+  SCRIPT_MEM_READ_WRITE (
+    EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+    EfiBootScriptWidthUint32,
+    (UINTN) (PegBaseAddress + R_SA_PEG_AFE_PM_TMR_OFFSET),
+    &Data32Or,  ///< Data to be ORed
+    &Data32And  ///< Data to be ANDed
+    );
+}
+
diff --git a/ReferenceCode/Chipset/SystemAgent/SaInit/Dxe/PciExpressInit.h b/ReferenceCode/Chipset/SystemAgent/SaInit/Dxe/PciExpressInit.h
new file mode 100644
index 0000000..05037b9
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/SaInit/Dxe/PciExpressInit.h
@@ -0,0 +1,224 @@
+/** @file
+  Header file for PciExpress Initialization Driver.
+
+@copyright
+  Copyright (c) 1999 - 2013 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement
+**/
+#ifndef _PCIEXPRESS_INITIALIZATION_DRIVER_H_
+#define _PCIEXPRESS_INITIALIZATION_DRIVER_H_
+
+#include "EdkIIGlueDxe.h"
+#include "SaAccess.h"
+#include "PchAccess.h"
+#include "pci23.h"
+#include "EfiScriptLib.h"
+#include "CpuRegs.h"
+#include "CpuPlatformLib.h"
+#include "cpu.h"
+
+#include EFI_PROTOCOL_CONSUMER (ExitPmAuth)
+#include EFI_PROTOCOL_DEPENDENCY (BootScriptSave)
+#include EFI_PROTOCOL_CONSUMER (SaPlatformPolicy)
+#include EFI_PROTOCOL_DEPENDENCY (SaGlobalNvsArea)
+
+#define DISABLED  0
+#define AUTO      1
+#define ENABLED   1
+
+#define GEN1      1
+#define GEN2      2
+
+typedef struct {
+  UINT8 Bus;
+  UINT8 Device;
+  UINT8 Function;
+  UINT8 Slot;
+  UINT8 Bus2;
+  UINT8 Device2;
+  UINT8 Function2;
+} PEG_PORT_DEVICE;
+
+///
+/// Function prototypes
+///
+/**
+  PCI Express Dxe Initialization.
+  Run before PCI Bus Init, where assignment of Bus, Memory,
+    and I/O Resources are assigned.
+
+  @param[in] DxePlatformSaPolicy -     SA DxePlatformPolicy protocol
+
+  @retval EFI_SUCCESS     - Pci Express successfully started and ready to be used
+  @exception EFI_UNSUPPORTED - Pci Express can't be initialized
+**/
+EFI_STATUS
+PciExpressInit (
+  IN DXE_PLATFORM_SA_POLICY_PROTOCOL *DxePlatformSaPolicy
+  )
+;
+
+/**
+  Find the Offset to a given Capabilities ID
+
+  @param[in] Bus       -   Pci Bus Number
+  @param[in] Device    -   Pci Device Number
+  @param[in] Function  -   Pci Function Number
+  @param[in] CapId     -   CAPID to search fo
+
+  @retval 0       - CAPID not found
+  @retval Other   - CAPID found, Offset of desired CAPID
+**/
+UINT32
+PcieFindCapId (
+  IN UINT8   Bus,
+  IN UINT8   Device,
+  IN UINT8   Function,
+  IN UINT8   CapId
+  )
+;
+
+/**
+  Search and return the offset of desired Pci Express Capability ID
+
+  @param[in] Bus       -   Pci Bus Number
+  @param[in] Device    -   Pci Device Number
+  @param[in] Function  -   Pci Function Number
+  @param[in] CapId     -   Extended CAPID to search for
+
+  @retval 0       - CAPID not found
+  @retval Other   - CAPID found, Offset of desired CAPID
+**/
+UINT32
+PcieFindExtendedCapId (
+  IN UINT8   Bus,
+  IN UINT8   Device,
+  IN UINT8   Function,
+  IN UINT16  CapId
+  )
+;
+
+/**
+  This function enables the CLKREQ# PM on all the end point functions
+
+  @param[in] Bus       -   Pci Bus Number
+  @param[in] Device    -   Pci Device Number
+**/
+VOID
+PcieSetClkreq (
+  IN  UINT8   Bus,
+  IN  UINT8   Device
+  )
+;
+
+/**
+  Perform Egress Port 0 Initialization.
+
+  @param[in] EgressPortBar   - EPBAR Address
+**/
+EFI_STATUS
+Cid1EgressPort0Init (
+  IN  UINT64      EgressPortBar
+  )
+;
+
+#ifdef PEG_FLAG
+/**
+  Conditionally perform PEG Port Initialization.
+  bugbug: organize this code in a way that can utilize the
+  PchS3ItemTypeInitPcieRootPortDownstream EFI_PCH_S3_DISPATCH_ITEM_TYPE
+
+  @param[in] DxePlatformSaPolicy - SA DxePlatformPolicy protocol
+**/
+EFI_STATUS
+Cid1PegPortInit (
+  IN DXE_PLATFORM_SA_POLICY_PROTOCOL *DxePlatformSaPolicy
+  )
+;
+#endif // PEG_FLAG
+
+/**
+  DMI Port Initialization for both CID1 (Port 1 in MCH) and CID2 (Port 0 in ICH).
+
+  @param[in] DmiBar              - DMIBAR Address
+  @param[in] DxePlatformSaPolicy - SA DxePlatformPolicy protocol
+**/
+EFI_STATUS
+Cid1Cid2DmiPortInit (
+  IN  UINT64                         DmiBar,
+  IN DXE_PLATFORM_SA_POLICY_PROTOCOL *DxePlatformSaPolicy
+  )
+;
+
+/**
+  Perform Root Complex Topology Initialization for CID1.
+
+  @param[in] EgressPortBar     - EPBAR Address
+  @param[in] DmiBar            - DMIBAR Address
+  @param[in] PchRootComplexBar - ICH RCBA Address
+**/
+EFI_STATUS
+Cid1TopologyInit (
+  IN UINT64        EgressPortBar,
+  IN  UINT64       DmiBar,
+  IN  UINT32       PchRootComplexBar
+  )
+;
+
+/**
+  Perform Root Complex Topology Initialization for CID2.
+
+  @param[in] DmiBar            - DMIBAR Address
+  @param[in] PchRootComplexBar - ICH RCBA Address
+**/
+EFI_STATUS
+Cid2TopologyInit (
+  IN UINT32   PchRootComplexBar,
+  IN UINT64   DmiBar
+  )
+;
+
+/**
+  Additional PEG Programming Steps as in SA BIOS spec
+
+  @param[in] Bus         - Bus Number of PEG device
+  @param[in] pegDev      - Dev Number of PEG device
+  @param[in] pegFn       - Func Number of PEG device
+  @param[in] DxePlatformSaPolicy - SA DxePlatformPolicy protocol
+**/
+VOID
+AdditionalPEGProgramStepsBeforeASPM (
+  IN  UINT8                          Bus,
+  IN  UINT8                          pegDev,
+  IN  UINT8                          pegFn,
+  IN DXE_PLATFORM_SA_POLICY_PROTOCOL *DxePlatformSaPolicy
+  )
+;
+
+/**
+  Additional DMI Programming Steps as in SA BIOS spec
+
+  @param[in] DmiBar              - DMIBAR Address
+  @param[in] DxePlatformSaPolicy - SA DxePlatformPolicy protocol
+**/
+VOID
+AdditionalDMIProgramStepsBeforeASPM (
+  IN UINT64                          DmiBar,
+  IN DXE_PLATFORM_SA_POLICY_PROTOCOL *DxePlatformSaPolicy
+  )
+;
+
+#endif
diff --git a/ReferenceCode/Chipset/SystemAgent/SaInit/Dxe/PcieComplex.c b/ReferenceCode/Chipset/SystemAgent/SaInit/Dxe/PcieComplex.c
new file mode 100644
index 0000000..bf4b367
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/SaInit/Dxe/PcieComplex.c
@@ -0,0 +1,1371 @@
+/** @file
+  This file will perform SA PCIE Root Complex initialization.
+
+@copyright
+  Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement
+
+**/
+#include "SaBuildFlags.h"
+#include "PciExpressInit.h"
+#include "EdkIIGluePcdPciExpressLib.h"
+#include "SaPcieLib.h"
+#include "PcieComplex.h"
+#include <Token.h>
+///
+/// Global variables
+///
+UINT8                                  HwStrap;
+extern UINT16                          mSaIotrapSmiAddress;
+extern BOOLEAN                         mInitPcieAspmAfterOprom;
+extern DXE_PLATFORM_SA_POLICY_PROTOCOL *mDxePlatformSaPolicy;
+
+#ifdef PEG_FLAG
+PEG_PORT_DEVICE PegDeviceTable[] = {
+  ///
+  ///          Bus,           Device,         Function, Slot, Bus2, Device2, Function2
+  ///
+  { SA_PEG_BUS_NUM, SA_PEG10_DEV_NUM, SA_PEG10_FUN_NUM,    1,    2,       0,         0 }
+// AMI_OVERRID >>  
+#if RC_PEG_1 == 1
+  ,{ SA_PEG_BUS_NUM, SA_PEG11_DEV_NUM, SA_PEG11_FUN_NUM,    2,    3,       0,         0 }
+#endif
+#if RC_PEG_2 == 1
+  ,{ SA_PEG_BUS_NUM, SA_PEG12_DEV_NUM, SA_PEG12_FUN_NUM,    3,    4,       0,         0 }
+#endif
+// AMI_OVERRID <<
+};
+#endif // PEG_FLAG
+
+///
+/// Functions
+///
+VOID
+EFIAPI
+SaLateInitSmiCallback (
+  IN EFI_EVENT    Event,
+  IN VOID         *Context
+  )
+/**
+    This function gets registered as a callback to perform all SA late initialization
+
+    @param[in] Event     - A pointer to the Event that triggered the callback.
+    @param[in] Context   - A pointer to private data registered with the callback function.
+**/
+{
+  if (mSaIotrapSmiAddress != 0) {
+    DEBUG ((EFI_D_INFO, "[SA] Issue IOTRAP SMI %X\n", mSaIotrapSmiAddress));
+    IoWrite8 (mSaIotrapSmiAddress, 0);
+  }
+  if (Event != NULL) {
+    gBS->CloseEvent(Event);
+  }
+  return;
+}
+
+EFI_STATUS
+Cid1EgressPort0Init (
+  IN  UINT64      EgressPortBar
+  )
+/**
+    Perform Egress Port 0 Initialization.
+
+    @param[in] EgressPortBar   - EPBAR Address
+
+    @retval EFI_SUCCESS        - Egress Port 0 initialization successed.
+**/
+{
+  UINT32  Data32And;
+  UINT32  Data32Or;
+  UINT8   Data8And;
+  UINT8   Data8Or;
+  UINT8   BitMask;
+  UINT8   BitValue;
+
+  ///
+  /// Egress Port Configuration
+  ///
+  /// Egress Port Virtual Channel 0 Configuration
+  ///   System BIOS must insure that only TC0 is mapped to VC0.
+  ///   a. Set the Egress Port Register EPBAR offset 014h[7:1]=0000000b
+  ///
+  Data32And = BIT0;
+  Data32Or  = 0;
+  Mmio32And (EgressPortBar, 0x14, Data32And);
+  SCRIPT_MEM_READ_WRITE (
+    EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+    EfiBootScriptWidthUint32,
+    (UINTN) (EgressPortBar + 0x14),
+    &Data32Or,
+    &Data32And
+    );
+
+  ///
+  /// System BIOS must program the extended VC count field.
+  ///   b. Set the Egress Port Register EPBAR offset 004h[2:0]=001b
+  ///
+  Data8And  = (UINT8)~(0x07);
+  Data8Or   = BIT0;
+  Mmio8AndThenOr (EgressPortBar, 0x4, Data8And, Data8Or);
+  SCRIPT_MEM_READ_WRITE (
+    EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+    EfiBootScriptWidthUint8,
+    (UINTN) (EgressPortBar + 0x4),
+    &Data8Or,
+    &Data8And
+    );
+
+  ///
+  /// Egress Port VC1 Configuration
+  ///   a. Assign Virtual Channel ID 1 to VC1: by programming PXEPBAR Offset 020[26:24] = '001b'
+  ///   b. Select and map TC1 to VC1: by programming PXPEPBAR Offset 020h[7:1] = '0000001b'
+  ///
+  Data32And = (UINT32)~(0x070000FE);
+  Data32Or  = ((0x01 << 24) + BIT1);
+  Mmio32AndThenOr (EgressPortBar, 0x20, Data32And, Data32Or);
+  SCRIPT_MEM_READ_WRITE (
+    EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+    EfiBootScriptWidthUint32,
+    (UINTN) (EgressPortBar + 0x20),
+    &Data32Or,
+    &Data32And
+    );
+
+  ///
+  /// c. Enable VC1 (no hardware behind this bit, s/w compatibility flag only) BIT31
+  ///    Program EXPEPBAR Offset 020h[31]=1
+  ///
+  Data32And = 0xFFFFFFFF;
+  Data32Or  = BIT31;
+  Mmio32Or (EgressPortBar, 0x20, Data32Or);
+  SCRIPT_MEM_READ_WRITE (
+    EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+    EfiBootScriptWidthUint32,
+    (UINTN) (EgressPortBar + 0x20),
+    &Data32Or,
+    &Data32And
+    );
+
+  ///
+  /// d. Poll the VC1 Negotiation Pending bit until it reads 0:
+  ///    Read the Egress Port Register EPBAR Offset 026h until [1]==0
+  ///
+  BitMask   = (UINT8) BIT1;
+  BitValue  = 0;
+  while ((Mmio8 (EgressPortBar, 0x26) & BitMask) != BitValue) {
+  };
+  SCRIPT_MEM_POLL (
+    EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+    EfiBootScriptWidthUint8,
+    (UINTN) (EgressPortBar + 0x26),
+    &BitMask,
+    &BitValue,
+    50,
+    200000
+    );
+
+  return EFI_SUCCESS;
+}
+
+#ifdef PEG_FLAG
+EFI_STATUS
+Cid1PegPortInit (
+  IN DXE_PLATFORM_SA_POLICY_PROTOCOL *DxePlatformSaPolicy
+  )
+/**
+    Conditionally perform PEG Port Initialization.
+    bugbug: organize this code in a way that can utilize the
+    PchS3ItemTypeInitPcieRootPortDownstream EFI_PCH_S3_DISPATCH_ITEM_TYPE
+
+    @param[in] DxePlatformSaPolicy - SA DxePlatformPolicy protocol
+
+    @retval EFI_SUCCESS            - PEG Port initialization successed.
+**/
+{
+  UINT32              Data32;
+  UINT32              Data32Or;
+  UINT32              Data32And;
+  UINT16              Data16Or;
+  UINT16              Data16And;
+  UINT8               Data8;
+  UINT32              PegBaseAddress;
+  UINT8               Bus;
+  UINT8               Dev;
+  UINT8               Func;
+  UINT8               Slot;
+  UINT8               Bus2;
+  UINT8               Dev2;
+  UINT8               Func2;
+  UINT8               PegComplete;
+  CPU_FAMILY          CpuFamilyId;
+  CPU_STEPPING        CpuSteppingId;
+
+  CpuFamilyId   = GetCpuFamily();
+  CpuSteppingId = GetCpuStepping();
+
+  ///
+  /// Read HwStrap Register - PEG1CFGSEL D1.R 504h [17:16]
+  ///
+  HwStrap = (UINT8) ((McD1PciCfg32 (R_SA_PEG_FUSESCMN_OFFSET) & (BIT17 + BIT16)) >> 16);
+
+  ///
+  /// HSW - Scan/initialize PEG devices based on HW strapping.
+  ///
+  for (PegComplete = 0; PegComplete < ((sizeof (PegDeviceTable)) / (sizeof (PEG_PORT_DEVICE))); PegComplete++) {
+    ///
+    /// Get Peg Device BDF, Slot# and EndPoint(Temporary)
+    ///
+    Bus             = PegDeviceTable[PegComplete].Bus;
+    Dev             = PegDeviceTable[PegComplete].Device;
+    Func            = PegDeviceTable[PegComplete].Function;
+    Slot            = PegDeviceTable[PegComplete].Slot;
+    Bus2            = PegDeviceTable[PegComplete].Bus2;
+    Dev2            = PegDeviceTable[PegComplete].Device2;
+    Func2           = PegDeviceTable[PegComplete].Function2;
+
+    PegBaseAddress  = (UINT32) MmPciAddress (0, Bus, Dev, Func, 0);
+    ///
+    /// Check if the PEG is Enabled. Since Graphics initialization has already
+    /// occurred, simply check for PEG presence.
+    /// bugbug: need to make sure this dependency is captured in the integration guide
+    ///
+    if (McDevFunPciCfg16 (Bus, Dev, Func, PCI_VID) != 0xFFFF) {
+      ///
+      /// PEG port enable and visible
+      ///
+      ///
+      /// Initialize Slot Implemented for PCI Express Port
+      ///
+      Data16And = 0xFFFF;
+      Data16Or  = BIT8;
+
+      McDevFunPciCfg16Or (Bus, Dev, Func, R_SA_PEG_CAP_OFFSET, Data16Or);
+      SCRIPT_MEM_READ_WRITE (
+        EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+        EfiBootScriptWidthUint16,
+        (UINTN) (PegBaseAddress + R_SA_PEG_CAP_OFFSET),
+        &Data16Or,
+        &Data16And
+        );
+
+      ///
+      /// Initialize "Physical Slot Number" for PCI Express Port
+      ///
+      Data32 = McDevFunPciCfg32 (Bus, Dev, Func, R_SA_PEG_SLOTCAP_OFFSET);
+      Data32 &= 0x0007FFFF;
+      ///
+      /// Set [31:19] - Slot # based on Peg Port
+      ///
+      Data32 |= (Slot << 19);
+
+      ///
+      /// Initialize Slot Power Limit for PCI Express Port and Power Limit Scale.
+      /// Note: this register is a write once.
+      ///
+      /// Set [14:7] - 75 Watts (Default)
+      ///
+      Data32 &= 0xFFFE007F;
+      Data32 |= (75 << 7);
+      ///
+      /// [16:15] - 1.0 Watt Scale
+      ///
+      Data32 |= (0 << 15);
+
+      McDevFunPciCfg32 (Bus, Dev, Func, R_SA_PEG_SLOTCAP_OFFSET) = Data32;
+      SCRIPT_MEM_WRITE (
+        EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+        EfiBootScriptWidthUint32,
+        (UINTN) (PegBaseAddress + R_SA_PEG_SLOTCAP_OFFSET),
+        1,
+        &Data32
+        );
+
+      ///
+      /// Additional Programming Steps
+      ///
+      /// Set PEG D.F.R 006h [15:0] = 0FFFFh
+      ///
+      Data32And = ~(0xFFFF0000);
+      Data32Or  = 0xFFFF0000;
+
+      McDevFunPciCfg32AndThenOr (Bus, Dev, Func, 0x4, Data32And, Data32Or);
+      SCRIPT_MEM_READ_WRITE (
+        EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+        EfiBootScriptWidthUint32,
+        (UINTN) (PegBaseAddress + 0x4),
+        &Data32Or,
+        &Data32And
+        );
+
+      ///
+      /// Set PEG D.F.R 01Eh [15:0] = 0FFFFh
+      ///
+      Data32And = ~(0xFFFF0000);
+      Data32Or  = 0xFFFF0000;
+
+      McDevFunPciCfg32AndThenOr (Bus, Dev, Func, 0x1C, Data32And, Data32Or);
+      SCRIPT_MEM_READ_WRITE (
+        EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+        EfiBootScriptWidthUint32,
+        (UINTN) (PegBaseAddress + 0x1C),
+        &Data32Or,
+        &Data32And
+        );
+
+      ///
+      /// Set PEG D.F.R 0AAh [15:0] = 0FFFFh
+      ///
+      Data32And = 0xFFFF;
+      Data32Or  = 0xFFFF;
+
+      McDevFunPciCfg16Or (Bus, Dev, Func, 0xAA, Data32Or);
+      SCRIPT_MEM_READ_WRITE (
+        EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+        EfiBootScriptWidthUint16,
+        (UINTN) (PegBaseAddress + 0xAA),
+        &Data32Or,
+        &Data32And
+        );
+
+      ///
+      /// Set PEG D.F.R 1C4h [31:0] = 0FFFFFFFFh
+      ///
+      Data32 = 0xFFFFFFFF;
+
+      McDevFunPciCfg32Or (Bus, Dev, Func, R_SA_PEG_PEGUESTS_OFFSET, Data32);
+      SCRIPT_MEM_WRITE (
+        EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+        EfiBootScriptWidthUint32,
+        (UINTN) (PegBaseAddress + R_SA_PEG_PEGUESTS_OFFSET),
+        1,
+        &Data32
+        );
+
+      ///
+      /// Set PEG D.F.R 1D0h [31:0] = 0FFFFFFFFh
+      ///
+      Data32 = 0xFFFFFFFF;
+
+      McDevFunPciCfg32Or (Bus, Dev, Func, R_SA_PEG_PEGCESTS_OFFSET, Data32);
+      SCRIPT_MEM_WRITE (
+        EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+        EfiBootScriptWidthUint32,
+        (UINTN) (PegBaseAddress + R_SA_PEG_PEGCESTS_OFFSET),
+        1,
+        &Data32
+        );
+
+      ///
+      /// Set PEG D.F.R 1F0h [31:0] = 0FFFFFFFFh
+      ///
+      Data32 = 0xFFFFFFFF;
+
+      McDevFunPciCfg32Or (Bus, Dev, Func, 0x1F0, Data32);
+      SCRIPT_MEM_WRITE (
+        EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+        EfiBootScriptWidthUint32,
+        (UINTN) (PegBaseAddress + 0x1F0),
+        1,
+        &Data32
+        );
+      ///
+      /// If HSW CPU steppingId >= B0 or CRW, set BIT19 of DCAP2 register of the PEG port,to enable OBFF support using WAKE# signaling
+      ///
+      if (((CpuFamilyId == EnumCpuHsw) && (CpuSteppingId >= EnumHswB0)) ||
+           (CpuFamilyId == EnumCpuCrw)) {
+        Data32 = (UINT32) BIT19;
+        McDevFunPciCfg32Or (Bus, Dev, Func, R_SA_PEG_DCAP2_OFFSET, Data32);
+        SCRIPT_MEM_WRITE (
+          EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+          EfiBootScriptWidthUint32,
+          (UINTN) (PegBaseAddress + R_SA_PEG_DCAP2_OFFSET),
+          1,
+          &Data32
+        );
+      }
+      ///
+      /// Complete Common Port and Endpoint Configuration
+      ///
+      ///
+      /// Virtual Channel Configuration of PCI Express Port
+      /// Set the VC0RCTL register D1:F0 Offset 114h [7:1] = 7Fh
+      ///
+      Data32And = 0xFFFFFF01;
+      Data32Or  = BIT7 | BIT6 | BIT5 | BIT4 | BIT3 | BIT2 | BIT1;
+
+      McDevFunPciCfg32AndThenOr (Bus, Dev, Func, R_SA_PEG_VC0RCTL0_OFFSET, Data32And, Data32Or);
+      SCRIPT_MEM_READ_WRITE (
+        EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+        EfiBootScriptWidthUint32,
+        (UINTN) (PegBaseAddress + R_SA_PEG_VC0RCTL0_OFFSET),
+        &Data32Or,
+        &Data32And
+        );
+      ///
+      /// 6.8 Additional Programming Steps before Enabling ASPM for PEG device
+      ///
+      AdditionalPEGProgramStepsBeforeASPM (Bus, Dev, Func, DxePlatformSaPolicy);
+
+      ///
+      /// 6.10 Interrupt Routing for PCI Express*
+      /// It is recommened to re-route the legacy interrupts (INTA -> INTB,C,D)
+      /// to avoid overcrowded INTA. ACPI PRT needs update.
+      /// The ACPI _PRT() methods for PEG controllers must match the legacy interrupt routing.
+      ///
+      if ((Dev == 1) && (Func == 1)) {
+        Data32And = (UINT32)~(BIT25 | BIT24);
+        Data32Or  = BIT24 | BIT25;
+        McDevFunPciCfg32AndThenOr (Bus, Dev, Func, R_SA_PEG_CFG4_OFFSET, Data32And, Data32Or);
+        SCRIPT_MEM_READ_WRITE (
+          EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+          EfiBootScriptWidthUint32,
+          (UINTN) (PegBaseAddress + R_SA_PEG_CFG4_OFFSET),
+          &Data32Or,
+          &Data32And
+          );
+      }
+
+      if ((Dev == 1) && (Func == 2)) {
+        Data32And = (UINT32)~(BIT25 | BIT24);
+        Data32Or  = BIT25;
+        McDevFunPciCfg32AndThenOr (Bus, Dev, Func, R_SA_PEG_CFG4_OFFSET, Data32And, Data32Or);
+        SCRIPT_MEM_READ_WRITE (
+          EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+          EfiBootScriptWidthUint32,
+          (UINTN) (PegBaseAddress + R_SA_PEG_CFG4_OFFSET),
+          &Data32Or,
+          &Data32And
+          );
+      }
+    }
+
+    ///
+    /// Lock offset 3Dh for Interrupt Pin
+    ///
+    Data8 = McDevFunPciCfg8 (Bus, Dev, Func, PCI_INTPIN);
+    McDevFunPciCfg8 (Bus, Dev, Func, PCI_INTPIN) = Data8;
+    SCRIPT_MEM_WRITE (
+      EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+      EfiBootScriptWidthUint8,
+      (UINTN) (PegBaseAddress + PCI_INTPIN),
+      1,
+      &Data8
+      );
+
+    ///
+    /// Lock DCAP register
+    ///
+    Data32 = McDevFunPciCfg32 (Bus, Dev, Func, R_SA_PEG_DCAP_OFFSET);
+    McDevFunPciCfg32 (Bus, Dev, Func, R_SA_PEG_DCAP_OFFSET) = Data32;
+    SCRIPT_MEM_WRITE (
+      EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+      EfiBootScriptWidthUint32,
+      (UINTN) (PegBaseAddress + R_SA_PEG_DCAP_OFFSET),
+      1,
+      &Data32
+      );
+
+    if ((CpuFamilyId == EnumCpuHsw) || (CpuFamilyId == EnumCpuCrw)
+        ){
+      if ((Bus == 0) && (Dev == 1) && (Func == 0)) {
+        Data32  = McDevFunPciCfg32 (Bus, Dev, Func, 0xCD0);
+        Data32 |= BIT11;
+        McDevFunPciCfg32 (Bus, Dev, Func, 0xCD0) = Data32;
+        SCRIPT_MEM_WRITE (
+          EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+          EfiBootScriptWidthUint32,
+          (UINTN) (PegBaseAddress + 0xCD0),
+          1,
+          &Data32
+          );
+       }
+    }
+
+    if ((HwStrap == SA_PEG_x16_x0_x0) && (PegComplete == 0)) {
+      break;
+    }
+    if ((HwStrap == SA_PEG_x8_x8_x0) && (PegComplete == 1)) {
+      break;
+    }
+    if ((HwStrap == SA_PEG_x8_x4_x4) && (PegComplete == 2)) {
+      break;
+    }
+  }
+
+  return EFI_SUCCESS;
+}
+#endif // PEG_FLAG
+
+EFI_STATUS
+Cid1Cid2DmiPortInit (
+  IN  UINT64                         DmiBar,
+  IN DXE_PLATFORM_SA_POLICY_PROTOCOL *DxePlatformSaPolicy
+  )
+/**
+    DMI Port Initialization for both CID1 (Port 1 in MCH) and CID2 (Port 0 in PCH).
+
+    @param[in] DmiBar              - DMIBAR Address
+    @param[in] DxePlatformSaPolicy - SA DxePlatformPolicy protocol
+
+    @retval EFI_SUCCESS            - DMI Port initialization successed.
+**/
+{
+  UINT32     Data32Or;
+#ifdef DMI_FLAG
+  UINT8      Data8And;
+  UINT8      Data8Or;
+  CPU_FAMILY CpuFamilyId;
+
+  CpuFamilyId = GetCpuFamily();
+#endif // DMI_FLAG
+
+#ifdef DMI_FLAG
+  if ((CpuFamilyId == EnumCpuHsw) || (CpuFamilyId == EnumCpuCrw)) {
+    ///
+    /// Additional Programming Steps
+    ///
+    AdditionalDMIProgramStepsBeforeASPM (DmiBar, DxePlatformSaPolicy);
+  }
+#endif // DMI_FLAG
+
+  ///
+  /// Set DMIBAR Offset 1C4h [31:0] = 0FFFFFFFFh
+  ///
+  Data32Or                = 0xFFFFFFFF;
+  Mmio32 (DmiBar, 0x1C4)  = 0xFFFFFFFF;
+  SCRIPT_MEM_WRITE (
+    EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+    EfiBootScriptWidthUint32,
+    (UINTN) (DmiBar + 0x1C4),
+    1,
+    &Data32Or
+    );
+
+  ///
+  /// Set DMIBAR Offset 1D0h [31:0] = 0FFFFFFFFh
+  ///
+  Data32Or                = 0xFFFFFFFF;
+  Mmio32 (DmiBar, 0x1D0)  = 0xFFFFFFFF;
+  SCRIPT_MEM_WRITE (
+    EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+    EfiBootScriptWidthUint32,
+    (UINTN) (DmiBar + 0x1D0),
+    1,
+    &Data32Or
+    );
+
+#ifdef DMI_FLAG
+  if ((CpuFamilyId == EnumCpuHsw) || (CpuFamilyId == EnumCpuCrw)) {
+    ///
+    /// Enable `Active State PM'. DMILCTL register at DMIBAR 088h [1:0] = '11b'.
+    /// Based on the policy:
+    ///
+    if (DxePlatformSaPolicy->PcieConfig->DmiAspm == PcieAspmAutoConfig ||
+        DxePlatformSaPolicy->PcieConfig->DmiAspm == PcieAspmL0sL1
+        ) {
+      ///
+      /// Enable ASPM = L0s and L1 Entry
+      ///
+      Data8And  = 0xFC;
+      Data8Or   = 0x03;
+      Mmio8Or (DmiBar, 0x88, Data8Or);
+      SCRIPT_MEM_READ_WRITE (
+        EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+        EfiBootScriptWidthUint8,
+        (UINTN) (DmiBar + 0x088),
+        &Data8Or,
+        &Data8And
+        );
+    } else if (DxePlatformSaPolicy->PcieConfig->DmiAspm == PcieAspmL0s) {
+      ///
+      /// Enable ASPM = L0s
+      ///
+      Data8And  = 0xFC;
+      Data8Or   = 0x01;
+      Mmio8Or (DmiBar, 0x88, Data8Or);
+      SCRIPT_MEM_READ_WRITE (
+        EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+        EfiBootScriptWidthUint8,
+        (UINTN) (DmiBar + 0x088),
+        &Data8Or,
+        &Data8And
+        );
+    } else if (DxePlatformSaPolicy->PcieConfig->DmiAspm == PcieAspmL1) {
+      ///
+      /// Enable ASPM = L1
+      ///
+      Data8And  = 0xFC;
+      Data8Or   = 0x02;
+      Mmio8Or (DmiBar, 0x88, Data8Or);
+      SCRIPT_MEM_READ_WRITE (
+        EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+        EfiBootScriptWidthUint8,
+        (UINTN) (DmiBar + 0x088),
+        &Data8Or,
+        &Data8And
+        );
+    }
+
+    if (DxePlatformSaPolicy->PcieConfig->DmiExtSync == ENABLED) {
+      ///
+      /// Enable Extended Synch
+      ///
+      Data8And  = 0xFF;
+      Data8Or   = 0x10;
+      Mmio8Or (DmiBar, 0x88, Data8Or);
+      SCRIPT_MEM_READ_WRITE (
+        EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+        EfiBootScriptWidthUint8,
+        (UINTN) (DmiBar + 0x088),
+        &Data8Or,
+        &Data8And
+        );
+    }
+
+    if (DxePlatformSaPolicy->PcieConfig->DmiIot == ENABLED) {
+      ///
+      /// if DMI Iot is enabled, set DMIBAR offset 0xD34 = 0x44
+      ///
+      Data8Or               = 0x44;
+      Mmio8 (DmiBar, 0xD34) = 0x44;
+      SCRIPT_MEM_WRITE (
+        EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+        EfiBootScriptWidthUint8,
+        (UINTN) (DmiBar + 0xD34),
+        1,
+        (VOID *) (UINTN) (DmiBar + 0xD34)
+        );
+    }
+  }
+#endif // DMI_FLAG
+
+  return EFI_SUCCESS;
+}
+
+EFI_STATUS
+Cid1TopologyInit (
+  IN UINT64        EgressPortBar,
+  IN  UINT64       DmiBar,
+  IN  UINT32       PchRootComplexBar
+  )
+/**
+    Perform Root Complex Topology Initialization for CID1.
+
+    @param[in] EgressPortBar     - EPBAR Address
+    @param[in] DmiBar            - DMIBAR Address
+    @param[in] PchRootComplexBar - PCH RCBA Address
+
+    @retval EFI_SUCCESS          - Root Complex topology initialization for CID1 successed.
+**/
+{
+  UINT32  Data32;
+  UINT32  Data32And;
+  UINT32  Data32Or;
+  UINT32  DwordReg;
+  UINT64  McD1Base;
+  UINT64  McD1F1Base;
+  UINT64  McD1F2Base;
+
+  McD1Base    = MmPciAddress (0, 0, 1, 0, 0);
+  McD1F1Base  = MmPciAddress (0, 0, 1, 1, 0);
+  McD1F2Base  = MmPciAddress (0, 0, 1, 2, 0);
+
+  ///
+  /// Set the CID1 Egress Port 0 Topology
+  ///
+  ///
+  /// Step 1, Set the SA Component ID = 1.
+  ///
+  Data32And = 0xFF00FFFF;
+  Data32Or  = BIT16;
+  Mmio32AndThenOr (EgressPortBar, 0x44, Data32And, Data32Or);
+  SCRIPT_MEM_READ_WRITE (
+    EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+    EfiBootScriptWidthUint32,
+    (UINTN) (EgressPortBar + 0x44),
+    &Data32Or,
+    &Data32And
+    );
+
+  ///
+  /// Step 2, Set link 1 Target Component ID and valid (Bit 0 = 1b).
+  /// Set the Link 1 TCID = 1 (Bits 23:16 = 01h).
+  ///
+  Data32And = 0xFF00FFFF;
+  Data32Or  = (BIT16 | BIT0);
+  Mmio32AndThenOr (EgressPortBar, 0x50, Data32And, Data32Or);
+  SCRIPT_MEM_READ_WRITE (
+    EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+    EfiBootScriptWidthUint32,
+    (UINTN) (EgressPortBar + 0x50),
+    &Data32Or,
+    &Data32And
+    );
+
+  ///
+  /// Step 3, Set Link 1 to Reference the DMI RCRB (Bits 31:0 = DMI Base).
+  ///
+  Data32 = (UINT32) DmiBar;
+  MmioWrite32 ((UINTN) EgressPortBar + 0x58, Data32);
+  SCRIPT_MEM_WRITE (
+    EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+    EfiBootScriptWidthUint32,
+    (UINTN) (EgressPortBar + 0x58),
+    1,
+    &Data32
+    );
+  Data32 = (UINT32) 0x00;
+  MmioWrite32 ((UINTN) EgressPortBar + 0x58 + 4, Data32);
+  SCRIPT_MEM_WRITE (
+    EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+    EfiBootScriptWidthUint32,
+    (UINTN) (EgressPortBar + 0x58 + 4),
+    1,
+    &Data32
+    );
+
+#ifdef PEG_FLAG
+  ///
+  /// CID1 Egress port Root Topology and PciExpress Port (PEG Ports) Topology
+  /// Programming only if PEG devices are enabled.
+  ///
+  /// Step 1 PCI Express Enabled Check
+  /// Check and Configure CID1 root and Device 1 function 0
+  ///
+  if (McD1PciCfg16 (PCI_VID) != 0xFFFF) {
+    ///
+    /// Step 4, Set Link 2 to Reference the Device 1 function 0.
+    ///
+    Data32 = (UINT32) 0x8000;
+    MmioWrite32 ((UINTN) EgressPortBar + 0x68, Data32);
+    SCRIPT_MEM_WRITE (
+      EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+      EfiBootScriptWidthUint32,
+      (UINTN) (EgressPortBar + 0x68),
+      1,
+      &Data32
+      );
+    Data32 = (UINT32) 0x00;
+    MmioWrite32 ((UINTN) EgressPortBar + 0x68 + 4, Data32);
+    SCRIPT_MEM_WRITE (
+      EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+      EfiBootScriptWidthUint32,
+      (UINTN) (EgressPortBar + 0x68 + 4),
+      1,
+      &Data32
+      );
+
+    ///
+    /// Step 5, Set link 2 Target Component ID and valid bit(Offset 60h, Bit 0 = 1b)
+    /// Set the Link 2 TCID = 1 (Bits 23:16 = 01h).
+    ///
+    Data32And = 0xFF00FFFF;
+    Data32Or  = (BIT16 | BIT0);
+    Mmio32AndThenOr (EgressPortBar, 0x60, Data32And, Data32Or);
+    SCRIPT_MEM_READ_WRITE (
+      EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+      EfiBootScriptWidthUint32,
+      (UINTN) (EgressPortBar + 0x60),
+      &Data32Or,
+      &Data32And
+      );
+
+    ///
+    /// Set the CID1 PCI Express* Port Root Topology
+    ///
+    /// Step 2 Set the Link 1 CID = 1 144h(23:16 = 01h).
+    ///
+    Data32And = 0xFF00FFFF;
+    Data32Or  = BIT16;
+    MmioAndThenOr32 ((UINTN) McD1Base + 0x144, Data32And, Data32Or);
+    SCRIPT_MEM_READ_WRITE (
+      EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+      EfiBootScriptWidthUint32,
+      (UINTN) (McD1Base + 0x144),
+      &Data32Or,
+      &Data32And
+      );
+
+    ///
+    /// Step 3. Set Link 1 to Reference the SA EP RCRB (Bits 31:0 = EPBAR).
+    ///
+    Data32 = (UINT32) EgressPortBar;
+    MmioWrite32 ((UINTN) McD1Base + 0x158, Data32);
+    SCRIPT_MEM_WRITE (
+      EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+      EfiBootScriptWidthUint32,
+      (UINTN) (McD1Base + 0x158),
+      1,
+      &Data32
+      );
+    Data32 = (UINT32) 0x00;
+    MmioWrite32 ((UINTN) McD1Base + 0x158 + 4, Data32);
+    SCRIPT_MEM_WRITE (
+      EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+      EfiBootScriptWidthUint32,
+      (UINTN) (McD1Base + 0x158 + 4),
+      1,
+      &Data32
+      );
+
+    ///
+    /// Step 4 Set link 1 Target Component ID and valid bit(Offset 150h, Bit 0 = 1b)
+    /// Set the Link 1 TCID = 1 (Bits 23:16 = 01h).
+    ///
+    Data32And = 0xFF00FFFF;
+    Data32Or  = (BIT16 | BIT0);
+    MmioAndThenOr32 ((UINTN) McD1Base + 0x150, Data32And, Data32Or);
+    SCRIPT_MEM_READ_WRITE (
+      EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+      EfiBootScriptWidthUint32,
+      (UINTN) (McD1Base + 0x150),
+      &Data32Or,
+      &Data32And
+      );
+
+    ///
+    /// Step 5 Program Read-Only Write-Once Registers
+    /// D1.F0.R 0C4h [31:0]
+    ///
+    Data32And             = 0xFFFFFFFF;
+    Data32Or              = (UINT32) 0x00;
+    Data32                = McD1PciCfg32 (0xC4);
+    McD1PciCfg32 (0xC4)   = Data32;
+    SCRIPT_MEM_READ_WRITE (
+      EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+      EfiBootScriptWidthUint32,
+      (UINTN) (McD1Base + 0xC4),
+      &Data32Or,
+      &Data32And
+      );
+  }
+  ///
+  /// Check and Configure CID1 root and Device 1 function 1
+  ///
+  if (McD1F1PciCfg16 (PCI_VID) != 0xFFFF) {
+    ///
+    /// Step 6, Set Link 3 to Reference the Device 1 function 1.
+    ///
+    Data32 = (UINT32) 0x9000;
+    MmioWrite32 ((UINTN) EgressPortBar + 0x78, Data32);
+    SCRIPT_MEM_WRITE (
+      EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+      EfiBootScriptWidthUint32,
+      (UINTN) (EgressPortBar + 0x78),
+      1,
+      &Data32
+      );
+    Data32 = (UINT32) 0x00;
+    MmioWrite32 ((UINTN) EgressPortBar + 0x78 + 4, Data32);
+    SCRIPT_MEM_WRITE (
+      EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+      EfiBootScriptWidthUint32,
+      (UINTN) (EgressPortBar + 0x78 + 4),
+      1,
+      &Data32
+      );
+
+    ///
+    /// Step 7. Set the Link 3 Target Component ID and Valid Bit 70h [0]
+    ///
+    Data32And = 0xFF00FFFF;
+    Data32Or  = (BIT16 | BIT0);
+    Mmio32AndThenOr (EgressPortBar, 0x70, Data32And, Data32Or);
+    SCRIPT_MEM_READ_WRITE (
+      EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+      EfiBootScriptWidthUint32,
+      (UINTN) (EgressPortBar + 0x70),
+      &Data32Or,
+      &Data32And
+      );
+
+    ///
+    /// Step 2 Set the Link 1 CID = 1 144h(23:16 = 01h).
+    ///
+    Data32And = 0xFF00FFFF;
+    Data32Or  = BIT16;
+    MmioAndThenOr32 ((UINTN) McD1F1Base + 0x144, Data32And, Data32Or);
+    SCRIPT_MEM_READ_WRITE (
+      EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+      EfiBootScriptWidthUint32,
+      (UINTN) (McD1F1Base + 0x144),
+      &Data32Or,
+      &Data32And
+      );
+
+    ///
+    /// Step 3 Set Link 1 to Reference the IMC EP RCRB (Bits 31:0 = EPBAR).
+    ///
+    Data32 = (UINT32) EgressPortBar;
+    MmioWrite32 ((UINTN) McD1F1Base + 0x158, Data32);
+    SCRIPT_MEM_WRITE (
+      EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+      EfiBootScriptWidthUint32,
+      (UINTN) (McD1F1Base + 0x158),
+      1,
+      &Data32
+      );
+    Data32 = (UINT32) 0x00;
+    MmioWrite32 ((UINTN) McD1F1Base + 0x158 + 4, Data32);
+    SCRIPT_MEM_WRITE (
+      EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+      EfiBootScriptWidthUint32,
+      (UINTN) (McD1F1Base + 0x158 + 4),
+      1,
+      &Data32
+      );
+
+    ///
+    /// Step 4 Set link 1 Target Component ID and valid bit(Offset 150h, Bit 0 = 1b)
+    /// Set the Link 1 TCID = 1 (Bits 23:16 = 01h).
+    ///
+    Data32And = 0xFF00FFFF;
+    Data32Or  = (BIT16 | BIT0);
+    MmioAndThenOr32 ((UINTN) McD1F1Base + 0x150, Data32And, Data32Or);
+    SCRIPT_MEM_READ_WRITE (
+      EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+      EfiBootScriptWidthUint32,
+      (UINTN) (McD1F1Base + 0x150),
+      &Data32Or,
+      &Data32And
+      );
+
+    ///
+    /// Step 5 Program Read-Only Write-Once Registers
+    ///
+    Data32And               = 0xFFFFFFFF;
+    Data32Or                = (UINT32) 0x00;
+    Data32                  = McD1F1PciCfg32 (0xC4);
+    McD1F1PciCfg32 (0xC4)   = Data32;
+    SCRIPT_MEM_READ_WRITE (
+      EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+      EfiBootScriptWidthUint32,
+      (UINTN) (McD1F1Base + 0xC4),
+      &Data32Or,
+      &Data32And
+      );
+  }
+  ///
+  /// Check and Configure CID1 root and Device 1 function 2
+  ///
+  if (McD1F2PciCfg16 (PCI_VID) != 0xFFFF) {
+    ///
+    /// Step 8, Set Link 4 to Reference the Device 1 function 2.
+    ///
+    Data32 = (UINT32) 0xA000;
+    MmioWrite32 ((UINTN) EgressPortBar + 0x88, Data32);
+    SCRIPT_MEM_WRITE (
+      EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+      EfiBootScriptWidthUint32,
+      (UINTN) (EgressPortBar + 0x88),
+      1,
+      &Data32
+      );
+    Data32 = (UINT32) 0x00;
+    MmioWrite32 ((UINTN) EgressPortBar + 0x88 + 4, Data32);
+    SCRIPT_MEM_WRITE (
+      EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+      EfiBootScriptWidthUint32,
+      (UINTN) (EgressPortBar + 0x88 + 4),
+      1,
+      &Data32
+      );
+
+    ///
+    /// Step 9, Set the Link 4 Target Component ID and Valid Bit 80h [0]
+    ///
+    Data32And = 0xFF00FFFF;
+    Data32Or  = (BIT16 | BIT0);
+    Mmio32AndThenOr (EgressPortBar, 0x80, Data32And, Data32Or);
+    SCRIPT_MEM_READ_WRITE (
+      EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+      EfiBootScriptWidthUint32,
+      (UINTN) (EgressPortBar + 0x80),
+      &Data32Or,
+      &Data32And
+      );
+
+    ///
+    /// Step 2. Set the Link 1 CID = 1 144h(23:16 = 01h).
+    ///
+    Data32And = 0xFF00FFFF;
+    Data32Or  = BIT16;
+    MmioAndThenOr32 ((UINTN) McD1F2Base + 0x144, Data32And, Data32Or);
+    SCRIPT_MEM_READ_WRITE (
+      EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+      EfiBootScriptWidthUint32,
+      (UINTN) (McD1F2Base + 0x144),
+      &Data32Or,
+      &Data32And
+      );
+
+    ///
+    /// Step 3. Set Link 1 to Reference the IMC EP RCRB (Bits 31:0 = EPBAR).
+    ///
+    Data32 = (UINT32) EgressPortBar;
+    MmioWrite32 ((UINTN) McD1F2Base + 0x158, Data32);
+    SCRIPT_MEM_WRITE (
+      EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+      EfiBootScriptWidthUint32,
+      (UINTN) (McD1F2Base + 0x158),
+      1,
+      &Data32
+      );
+    Data32 = (UINT32) 0x00;
+    MmioWrite32 ((UINTN) McD1F2Base + 0x158 + 4, Data32);
+    SCRIPT_MEM_WRITE (
+      EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+      EfiBootScriptWidthUint32,
+      (UINTN) (McD1F2Base + 0x158 + 4),
+      1,
+      &Data32
+      );
+
+    ///
+    /// Step 4. Set link 1 Target Component ID and valid bit(Offset 150h, Bit 0 = 1b)
+    /// Set the Link 1 TCID = 1 (Bits 23:16 = 01h).
+    ///
+    Data32And = 0xFF00FFFF;
+    Data32Or  = (BIT16 | BIT0);
+    MmioAndThenOr32 ((UINTN) McD1F2Base + 0x150, Data32And, Data32Or);
+    SCRIPT_MEM_READ_WRITE (
+      EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+      EfiBootScriptWidthUint32,
+      (UINTN) (McD1F2Base + 0x150),
+      &Data32Or,
+      &Data32And
+      );
+
+    ///
+    /// Step 5. Program Read-Only Write-Once Registers
+    ///
+    Data32And               = 0xFFFFFFFF;
+    Data32Or                = (UINT32) 0x00;
+    Data32                  = McD1F2PciCfg32 (0xC4);
+    McD1F2PciCfg32 (0xC4)   = Data32;
+    SCRIPT_MEM_READ_WRITE (
+      EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+      EfiBootScriptWidthUint32,
+      (UINTN) (McD1F2Base + 0xC4),
+      &Data32Or,
+      &Data32And
+      );
+  }
+#endif // PEG_FLAG
+
+  ///
+  /// Set the CID1 DMI Port Root Topology
+  ///
+  /// Step 1 Set the CID = 1 ( Bits 23:16 = 01h).
+  ///
+  Data32And = 0xFF00FFFF;
+  Data32Or  = BIT16;
+  Mmio32AndThenOr (DmiBar, 0x44, Data32And, Data32Or);
+  SCRIPT_MEM_READ_WRITE (
+    EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+    EfiBootScriptWidthUint32,
+    (UINTN) (DmiBar + 0x44),
+    &Data32Or,
+    &Data32And
+    );
+
+  ///
+  /// Step 2.  Set Link 1 Target Port Number = 0 (Bits 31:24 = 00h).
+  /// Step 3.  Set Link 1 TCID = 2 (Bits 23:16 = 02h).
+  /// Step 4.  Set Link 1 as valid (Bit 0 = 1b).
+  ///
+  Data32And = 0x0000FFFF;
+  Data32Or  = (BIT17 + BIT0);
+  Mmio32AndThenOr (DmiBar, 0x50, Data32And, Data32Or);
+  SCRIPT_MEM_READ_WRITE (
+    EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+    EfiBootScriptWidthUint32,
+    (UINTN) (DmiBar + 0x50),
+    &Data32Or,
+    &Data32And
+    );
+
+  ///
+  /// Step 5, Set Link 1 to Reference the PCH RCRB
+  ///
+  Data32                  = PchRootComplexBar;
+  Mmio32 (DmiBar, 0x58)   = PchRootComplexBar;
+  SCRIPT_MEM_WRITE (
+    EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+    EfiBootScriptWidthUint32,
+    (UINTN) (DmiBar + 0x58),
+    1,
+    &Data32
+    );
+  Data32                      = (UINT32) 0x00;
+  Mmio32 (DmiBar, 0x58 + 4)   = Data32;
+  SCRIPT_MEM_WRITE (
+    EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+    EfiBootScriptWidthUint32,
+    (UINTN) (DmiBar + 0x58 + 4),
+    1,
+    &Data32
+    );
+
+  ///
+  /// Step 6, Set Link 2 to Reference the IMC EP (Bits 31:0 = EP).
+  ///
+  Data32 = (UINT32) EgressPortBar;
+  MmioWrite32 ((UINTN) DmiBar + 0x68, Data32);
+  SCRIPT_MEM_WRITE (
+    EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+    EfiBootScriptWidthUint32,
+    (UINTN) (DmiBar + 0x68),
+    1,
+    &Data32
+    );
+  Data32 = (UINT32) 0x00;
+  MmioWrite32 ((UINTN) DmiBar + 0x68 + 4, Data32);
+  SCRIPT_MEM_WRITE (
+    EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+    EfiBootScriptWidthUint32,
+    (UINTN) (DmiBar + 0x68 + 4),
+    1,
+    &Data32
+    );
+
+  ///
+  /// Step 7, Set link 2 Target Component ID and valid Bit(Bit 0 = 1b)
+  /// Set the Link 2 TCID = 1 (Bits 23:16 = 01h).
+  ///
+  Data32And = 0xFF00FFFF;
+  Data32Or  = (BIT16 | BIT0);
+  Mmio32AndThenOr (DmiBar, 0x60, Data32And, Data32Or);
+  SCRIPT_MEM_READ_WRITE (
+    EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+    EfiBootScriptWidthUint32,
+    (UINTN) (DmiBar + 0x60),
+    &Data32Or,
+    &Data32And
+    );
+
+  ///
+  /// Step 8. Program RO and Write-Once Registers
+  /// DMIBAR Offset 004h [31:0]
+  /// DMIBAR Offset 084h [31:0]
+  ///
+  DwordReg                = Mmio32 (DmiBar, 0x4);
+  Mmio32 (DmiBar, 0x4)    = DwordReg;
+
+  DwordReg                = Mmio32 (DmiBar, 0x84);
+  Mmio32 (DmiBar, 0x84)   = DwordReg;
+
+  return EFI_SUCCESS;
+}
+
+EFI_STATUS
+Cid2TopologyInit (
+  IN UINT32   PchRootComplexBar,
+  IN UINT64   DmiBar
+  )
+/**
+  Perform Root Complex Topology Initialization for CID2.
+  Note: This sequence follows PCH BIOS specification Ver 0.5 section 8.3
+        Root Complex Topology Programming
+
+  @param[in] PchRootComplexBar - PCH RCBA Address
+  @param[in] DmiBar            - DMIBAR Address
+
+  @retval EFI_SUCCESS          - Root Complex topology initialization for CID2 successed.
+**/
+{
+  UINT32  Data32;
+  UINT32  Data32And;
+  UINT32  Data32Or;
+
+  ///
+  /// PCH BIOS specification Ver 0.5 section 8.3 Note 1,2
+  /// program a value into this Component ID field to determine the Component ID of
+  /// ICH8, and this value must be different from the Component ID value of the MCH.
+  /// Set the CID = 2 (Offset 104h, Bits 23:16 = 02h).
+  ///
+  Data32And = 0xFF00FFFF;
+  Data32Or  = BIT17;
+  MmioAndThenOr32 (PchRootComplexBar + 0x104, Data32And, Data32Or);
+  SCRIPT_MEM_READ_WRITE (
+    EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+    EfiBootScriptWidthUint32,
+    (UINTN) (PchRootComplexBar + 0x104),
+    &Data32Or,
+    &Data32And
+    );
+
+  ///
+  /// PCH BIOS specification Ver 0.5 section 8.3 Note 3,4
+  /// Note 3: This Target Port # field must be filled in by System BIOS with the Port
+  /// # of the RCRB DMI link in the MCH.
+  /// Note 4: This Target CID field must be filled in by System BIOS with the
+  /// Component ID of the MCH.
+  /// Set the Link 1 Target Port Number = 1 (Offset 110h, bits 31:24 = 01h).
+  /// Set the Link 1 Target Component ID = 1 (Offset 110h, bits 23:16 = 01h).
+  ///
+  Data32And = 0x0000FFFF;
+  Data32Or  = (BIT24 | BIT16);
+  MmioAndThenOr32 (PchRootComplexBar + 0x110, Data32And, Data32Or);
+  SCRIPT_MEM_READ_WRITE (
+    EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+    EfiBootScriptWidthUint32,
+    (UINTN) (PchRootComplexBar + 0x110),
+    &Data32Or,
+    &Data32And
+    );
+
+  ///
+  /// PCH BIOS specification Ver 0.5 section 8.3 Note 5
+  /// Fill the Base Address field with the same base address of the RCRB DMI link in
+  /// the MCH, This register field is located at RCBA+ 0118h[63:0],
+  /// and will be locked once written until the next reset.
+  ///
+  Data32 = (UINT32) DmiBar;
+  MmioWrite32 (PchRootComplexBar + 0x118, Data32);
+  SCRIPT_MEM_WRITE (
+    EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+    EfiBootScriptWidthUint32,
+    (UINTN) (PchRootComplexBar + 0x118),
+    1,
+    &Data32
+    );
+
+  Data32 = *((UINT32 *) (&DmiBar) + 1);
+  MmioWrite32 (PchRootComplexBar + 0x118 + 4, Data32);
+  SCRIPT_MEM_WRITE (
+    EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+    EfiBootScriptWidthUint8,
+    (UINTN) (PchRootComplexBar + 0x118 + 4),
+    1,
+    &Data32
+    );
+
+  return EFI_SUCCESS;
+}
+
+EFI_STATUS
+PegInitBeforeExitPmAuth (
+  VOID
+  )
+/**
+  This function performs Peg initialization before ExitPmAuth.
+
+  @retval EFI_SUCCESS   - Always.
+**/
+{
+#if SA_PCIE_ASPM_IN_SMM == 1
+  EFI_EVENT                       ReadyToBoot;
+  EFI_STATUS                      Status;
+#endif
+  BOOLEAN                         AspmHasBeenHandled;
+
+  DEBUG ((EFI_D_ERROR, "[SA] Pcie before ExitPmAuth callback.\n"));
+  AspmHasBeenHandled = FALSE;
+  ///
+  /// SMM mode ASPM handling
+  /// Check if supported and enabled
+  ///
+#if SA_PCIE_ASPM_IN_SMM == 1
+  if ((mInitPcieAspmAfterOprom == 1) && (mSaIotrapSmiAddress != 0)) {
+    ///
+    /// Do the Phase 1 SMI callback
+    /// This will enumerate PCIe downstream devices
+    ///
+    SaLateInitSmiCallback (NULL, NULL);
+
+    ///
+    /// Create an ReadyToBoot call back event to do the Phase 3 SMI callback
+    /// This will handle PEG ASPM programming after OROM execution
+    ///
+    Status = EfiCreateEventReadyToBootEx (
+               EFI_TPL_NOTIFY,
+               SaLateInitSmiCallback,
+               NULL,
+               &ReadyToBoot
+               );
+    ASSERT_EFI_ERROR (Status);
+    AspmHasBeenHandled = TRUE;
+  }
+#endif
+
+  ///
+  /// DXE mode ASPM handling
+  /// Check if SMM mode already taken care all things
+  /// TRUE to skip DXE mode task. Otherwise do DXE mode ASPM initialization
+  ///
+#if SA_PCIE_ASPM_IN_DXE == 1
+  if (AspmHasBeenHandled == FALSE) {
+    ///
+    /// Initialize ASPM before OpROM, S3 Save script supported
+    /// First initialize all policy settings
+    /// Initialize module global variables - Stepping ID and Platform Policy
+    ///
+    SaPcieInitPolicy (mDxePlatformSaPolicy);
+    ///
+    /// Do initialization
+    ///
+    SaPcieEnumCallback ();
+    SaPcieConfigAfterOpRom ();
+  }
+#endif
+
+  return EFI_SUCCESS;
+}
+
+EFI_STATUS
+SaSecurityInit (
+  VOID
+  )
+/**
+  This function performs SA Security locking in ExitPmAuth callback
+
+  @retval EFI_SUCCESS     - Security lock has done
+  @retval EFI_UNSUPPORTED - Security lock not done successfully
+**/
+{
+  BOOLEAN                         SecurityHasBeenHandled;
+  SecurityHasBeenHandled = FALSE;
+#if SA_PCIE_ASPM_IN_SMM == 1
+  if ((mInitPcieAspmAfterOprom == 1) && (mSaIotrapSmiAddress != 0)) {
+    ///
+    /// Generate the Phase 2 of SA SMI to do security lock
+    ///
+    SaLateInitSmiCallback (NULL, NULL);
+
+    SecurityHasBeenHandled = TRUE;
+  }
+#endif
+
+  ///
+  /// Check if SMM mode already taken care this task
+  ///
+#if SA_PCIE_ASPM_IN_DXE == 1
+  if (SecurityHasBeenHandled == FALSE) {
+    SaSaveRestorePlatform (TRUE);
+    SaSecurityLock ();
+    SecurityHasBeenHandled = TRUE;
+  }
+#endif
+  ///
+  /// Security locking is important so fail to do this will be an ERROR.
+  ///
+  if (SecurityHasBeenHandled == TRUE) {
+    return EFI_SUCCESS;
+  } else {
+    return EFI_UNSUPPORTED;
+  }
+}
diff --git a/ReferenceCode/Chipset/SystemAgent/SaInit/Dxe/PcieComplex.h b/ReferenceCode/Chipset/SystemAgent/SaInit/Dxe/PcieComplex.h
new file mode 100644
index 0000000..8a52de9
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/SaInit/Dxe/PcieComplex.h
@@ -0,0 +1,43 @@
+/** @file
+  This is header file for SA PCIE Root Complex initialization.
+
+@copyright
+  Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement
+**/
+
+EFI_STATUS
+PegInitBeforeExitPmAuth (
+  VOID
+  )
+/**
+  This function performs Peg initialization before ExitPmAuth.
+
+  @retval EFI_SUCCESS   - Always.
+**/
+;
+
+EFI_STATUS
+SaSecurityInit (
+  VOID
+  )
+/**
+  This function performs SA Security locking in ExitPmAuth callback
+
+  @retval EFI_SUCCESS     - Security lock has done
+  @retval EFI_UNSUPPORTED - Security lock not done successfully
+**/
+;
diff --git a/ReferenceCode/Chipset/SystemAgent/SaInit/Dxe/SaFvi.c b/ReferenceCode/Chipset/SystemAgent/SaInit/Dxe/SaFvi.c
new file mode 100644
index 0000000..d88a5e7
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/SaInit/Dxe/SaFvi.c
@@ -0,0 +1,105 @@
+/** @file
+  SA Firmware Version Info implementation.
+
+@copyright
+  Copyright (c) 2011 - 2012 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement
+**/
+#include "SaInit.h"
+
+FVI_ELEMENT_AND_FUNCTION      mSaFviElementsData[] = {
+  {
+    DEFAULT_FVI_ELEMENT_DATA(SA),
+    NULL
+  },
+  {
+    {
+      1,
+      0,
+      MEM_RC_VERSION,
+      MEM_FVI_STRING,
+      {
+        0
+      },
+    },
+    NULL
+  },
+  {
+    {
+      1,
+      0,
+      PCIE_RC_VERSION,
+      PCIE_FVI_STRING,
+      {
+        0
+      },
+    },
+    NULL
+  },
+  {
+    {
+      1,
+      2,
+      SA_CRID_VERSION,
+      SA_CRID_STATUS,
+      SA_CRID_DISABLED,
+    },
+    NULL
+  },
+  {
+    {
+      1,
+      0,
+      SA_CRID_VERSION,
+      SA_CRID_ORIGINAL_VALUE,
+      {
+        0
+      },
+    },
+    NULL
+  },
+  {
+    {
+      1,
+      0,
+      SA_CRID_VERSION,
+      SA_CRID_NEW_VALUE,
+      {
+        0
+      },
+    },
+    NULL
+  },
+  {
+    {
+      1,
+      0,
+      VBIOS_RC_VERSION,
+      VBIOS_FVI_STRING,
+      {
+        0
+      },
+    },
+    NULL
+  }
+};
+
+FVI_DATA_HUB_CALLBACK_CONTEXT mSaFviVersionData = {
+  MISC_SUBCLASS_FVI_HEADER_ENTRY(SA),
+  mSaFviElementsData,
+};
+
+UINTN                         mSaFviElements = sizeof (mSaFviElementsData) / sizeof (FVI_ELEMENT_AND_FUNCTION);
diff --git a/ReferenceCode/Chipset/SystemAgent/SaInit/Dxe/SaInit.c b/ReferenceCode/Chipset/SystemAgent/SaInit/Dxe/SaInit.c
new file mode 100644
index 0000000..af4d45a
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/SaInit/Dxe/SaInit.c
@@ -0,0 +1,842 @@
+/** @file
+  This is the driver that initializes the Intel System Agent.
+
+@copyright
+  Copyright (c) 1999 - 2013 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement
+
+**/
+#include "SaInit.h"
+#include EFI_GUID_DEFINITION (SaDataHob)
+#include <Protocol/PciEnumerationComplete.h>
+#include EFI_PROTOCOL_DEPENDENCY (SaGlobalNvsArea)
+#include EFI_GUID_DEFINITION (SaSsdtTableStorage)
+
+///
+/// Global Variables
+///
+SYSTEM_AGENT_GLOBAL_NVS_AREA_PROTOCOL  mSaGlobalNvsAreaProtocol;
+DXE_PLATFORM_SA_POLICY_PROTOCOL        *mDxePlatformSaPolicy;
+UINT16                                 mSaIotrapSmiAddress;
+BOOLEAN                                mInitPcieAspmAfterOprom;
+EFI_GUID                               gEfiPciEnumerationCompleteProtocolGuid = EFI_PCI_ENUMERATION_COMPLETE_GUID;
+
+EFI_STATUS
+InitializeSaSsdtAcpiTables (
+  VOID
+  )
+/**
+@brief
+  Initialize System Agent SSDT ACPI tables
+
+  @retval EFI_SUCCESS    ACPI tables are initialized successfully
+  @retval EFI_NOT_FOUND  ACPI tables not found
+**/
+{
+  EFI_STATUS                    Status;
+  EFI_HANDLE                    *HandleBuffer;
+  UINTN                         NumberOfHandles;
+  EFI_FV_FILETYPE               FileType;
+  UINT32                        FvStatus;
+  EFI_FV_FILE_ATTRIBUTES        Attributes;
+  UINTN                         Size;
+  UINTN                         i;
+  EFI_FIRMWARE_VOLUME_PROTOCOL  *FwVol;
+  INTN                          Instance;
+  EFI_ACPI_COMMON_HEADER        *CurrentTable;
+  UINTN                         AcpiTableKey;
+  UINT8                         *CurrPtr;
+  UINT8                         *EndPtr;
+  UINT32                        *Signature;
+  EFI_ACPI_DESCRIPTION_HEADER   *SaAcpiTable;
+  EFI_ACPI_TABLE_PROTOCOL       *AcpiTable;
+
+  FwVol               = NULL;
+  SaAcpiTable = NULL;
+
+  ///
+  /// Locate ACPI Table protocol
+  ///
+  DEBUG ((EFI_D_INFO, "Init SA SSDT table\n"));
+  Status = gBS->LocateProtocol (&gEfiAcpiTableProtocolGuid, NULL, &AcpiTable);
+  if (Status != EFI_SUCCESS) {
+    DEBUG ((EFI_D_ERROR, "Fail to locate EfiAcpiTableProtocol.\n"));
+    return EFI_NOT_FOUND;
+  }
+
+  ///
+  /// Locate protocol.
+  /// There is little chance we can't find an FV protocol
+  ///
+  Status = gBS->LocateHandleBuffer (
+                  ByProtocol,
+                  &gEfiFirmwareVolumeProtocolGuid,
+                  NULL,
+                  &NumberOfHandles,
+                  &HandleBuffer
+                  );
+  ASSERT_EFI_ERROR (Status);
+  ///
+  /// Looking for FV with ACPI storage file
+  ///
+  for (i = 0; i < NumberOfHandles; i++) {
+    ///
+    /// Get the protocol on this handle
+    /// This should not fail because of LocateHandleBuffer
+    ///
+    Status = gBS->HandleProtocol (
+                    HandleBuffer[i],
+                    &gEfiFirmwareVolumeProtocolGuid,
+                    &FwVol
+                    );
+    ASSERT_EFI_ERROR (Status);
+
+    ///
+    /// See if it has the ACPI storage file
+    ///
+    Size      = 0;
+    FvStatus  = 0;
+    Status = FwVol->ReadFile (
+                      FwVol,
+                      &gSaSsdtAcpiTableStorageGuid,
+                      NULL,
+                      &Size,
+                      &FileType,
+                      &Attributes,
+                      &FvStatus
+                      );
+
+    ///
+    /// If we found it, then we are done
+    ///
+    if (Status == EFI_SUCCESS) {
+      break;
+    }
+  }
+  ///
+  /// Free any allocated buffers
+  ///
+  FreePool (HandleBuffer);
+
+  ///
+  /// Sanity check that we found our data file
+  ///
+  ASSERT (FwVol != NULL);
+  if (FwVol == NULL) {
+    DEBUG ((EFI_D_INFO, "SA Global NVS table not found\n"));
+    return EFI_NOT_FOUND;
+  }
+  ///
+  /// Our exit status is determined by the success of the previous operations
+  /// If the protocol was found, Instance already points to it.
+  /// Read tables from the storage file.
+  ///
+  Instance      = 0;
+  CurrentTable  = NULL;
+  while (Status == EFI_SUCCESS) {
+    Status = FwVol->ReadSection (
+                      FwVol,
+                      &gSaSsdtAcpiTableStorageGuid,
+                      EFI_SECTION_RAW,
+                      Instance,
+                      &CurrentTable,
+                      &Size,
+                      &FvStatus
+                      );
+
+    if (!EFI_ERROR (Status)) {
+      ///
+      /// Check the table ID to modify the table
+      ///
+      if (((EFI_ACPI_DESCRIPTION_HEADER *) CurrentTable)->OemTableId == EFI_SIGNATURE_64 ('S', 'a', 'S', 's', 'd', 't', ' ', 0)) {
+        SaAcpiTable = (EFI_ACPI_DESCRIPTION_HEADER *) CurrentTable;
+        ///
+        /// Locate the SSDT package
+        ///
+        CurrPtr = (UINT8 *) SaAcpiTable;
+        EndPtr  = CurrPtr + SaAcpiTable->Length;
+
+        for (; CurrPtr <= EndPtr; CurrPtr++) {
+          Signature = (UINT32 *) (CurrPtr + 3);
+          if (*Signature == EFI_SIGNATURE_32 ('S', 'A', 'N', 'V')) {
+            ASSERT_EFI_ERROR (*(UINT32 *) (CurrPtr + 3 + sizeof (*Signature) + 2) == 0xFFFF0000);
+            ASSERT_EFI_ERROR (*(UINT16 *) (CurrPtr + 3 + sizeof (*Signature) + 2 + sizeof (UINT32) + 1) == 0xAA55);
+            ///
+            /// SA Global NVS Area address
+            ///
+            *(UINT32 *) (CurrPtr + 3 + sizeof (*Signature) + 2) = (UINT32) (UINTN) mSaGlobalNvsAreaProtocol.Area;
+            ///
+            /// SA Global NVS Area size
+            ///
+            *(UINT16 *) (CurrPtr + 3 + sizeof (*Signature) + 2 + sizeof (UINT32) + 1) =
+            sizeof (SYSTEM_AGENT_GLOBAL_NVS_AREA);
+
+            AcpiTableKey = 0;
+            Status = AcpiTable->InstallAcpiTable (
+                                  AcpiTable,
+                                  SaAcpiTable,
+                                  SaAcpiTable->Length,
+                                  &AcpiTableKey
+                                  );
+            ASSERT_EFI_ERROR (Status);
+            return EFI_SUCCESS;
+          }
+        }
+      }
+      ///
+      /// Increment the instance
+      ///
+      Instance++;
+      CurrentTable = NULL;
+    }
+  }
+
+  return Status;
+
+}
+
+EFI_STATUS
+EFIAPI
+SaInitEntryPoint (
+  IN EFI_HANDLE         ImageHandle,
+  IN EFI_SYSTEM_TABLE   *SystemTable
+  )
+/**
+  SystemAgent DXE Initialization.
+
+  @param[in] ImageHandle             Handle for the image of this driver
+  @param[in] SystemTable             Pointer to the EFI System Table
+
+  @retval EFI_SUCCESS             The function completed successfully
+  @retval EFI_OUT_OF_RESOURCES    No enough buffer to allocate
+**/
+{
+  EFI_STATUS                Status;
+  VOID                      *Registration;
+  SA_INSTANCE_PRIVATE_DATA  *SaInstance;
+  UINTN                     MCHBAR_BASE;
+  SA_DATA_HOB               *SaDataHob;
+
+  DEBUG ((EFI_D_INFO, "SaInitDxe Start\n"));
+
+  INITIALIZE_SCRIPT (ImageHandle, SystemTable);
+  SaInstance  = NULL;
+
+  MCHBAR_BASE = McD0PciCfg64 (R_SA_MCHBAR) &~BIT0;
+
+  ///
+  /// Get the platform setup policy.
+  ///
+  Status = gBS->LocateProtocol (&gDxePlatformSaPolicyGuid, NULL, (VOID **) &mDxePlatformSaPolicy);
+  ASSERT_EFI_ERROR (Status);
+
+  ///
+  /// Dump SA Platform Policy
+  ///
+  SaDxePolicyDump (mDxePlatformSaPolicy);
+
+  ///
+  /// Get SaDataHob HOB and see if ASPM should be programmed before or after OpROM.
+  ///
+  mSaIotrapSmiAddress    = 0;
+  mInitPcieAspmAfterOprom = 0;
+  SaDataHob              = NULL;
+  SaDataHob              = (SA_DATA_HOB *)GetFirstGuidHob (&gSaDataHobGuid);
+  if (SaDataHob != NULL) {
+    mSaIotrapSmiAddress    = SaDataHob->SaIotrapSmiAddress;
+    mInitPcieAspmAfterOprom = SaDataHob->InitPcieAspmAfterOprom;
+  }
+
+  ///
+  /// If there was no DXE ASPM code, always executes SMM code
+  ///
+#if SA_PCIE_ASPM_IN_DXE == 0
+  mInitPcieAspmAfterOprom = 1;
+#endif
+  ///
+  /// If there was no SMM mode supported, always enable DXE mode
+  ///
+#if SA_PCIE_ASPM_IN_SMM == 0
+  mInitPcieAspmAfterOprom = 0;
+#endif
+
+  ///
+  /// Install System Agent Global NVS protocol
+  ///
+  DEBUG ((EFI_D_INFO, "Install SA GNVS protocol\n"));
+  Status = (gBS->AllocatePool) (EfiACPIMemoryNVS, sizeof (SYSTEM_AGENT_GLOBAL_NVS_AREA), &mSaGlobalNvsAreaProtocol.Area);
+  ASSERT_EFI_ERROR (Status);
+  ZeroMem ((VOID *) mSaGlobalNvsAreaProtocol.Area, sizeof (SYSTEM_AGENT_GLOBAL_NVS_AREA));
+  mSaGlobalNvsAreaProtocol.Area->SaRcRevision = SA_RC_VERSION;
+  mSaGlobalNvsAreaProtocol.Area->XPcieCfgBaseAddress  = (UINT32) (MmPciAddress (0, 0, 0, 0, 0x0));
+
+  Status = gBS->InstallMultipleProtocolInterfaces (
+                  &ImageHandle,
+                  &gSaGlobalNvsAreaProtocolGuid,
+                  &mSaGlobalNvsAreaProtocol,
+                  NULL
+                  );
+  ASSERT_EFI_ERROR (Status);
+
+  ///
+  /// PciExpress Dxe Initialization
+  ///
+  DEBUG ((EFI_D_INFO, "Initializing PciExpress (Dxe)\n"));
+  PciExpressInit (mDxePlatformSaPolicy);
+
+  ///
+  /// Internal devices and Misc configurations.
+  ///
+  DEBUG ((EFI_D_INFO, "Internal Device and Misc Configurations\n"));
+  DeviceConfigure (mDxePlatformSaPolicy);
+  ProgramSvidSid (mDxePlatformSaPolicy);
+
+  ///
+  /// LegacyRegion Driver
+  ///
+  DEBUG ((EFI_D_INFO, "Initializing Legacy Region\n"));
+  LegacyRegionInstall (ImageHandle);
+
+  ///
+  /// GtPostInit Initialization
+  ///
+  DEBUG ((EFI_D_INFO, "Initializing GT PowerManagement and other GT POST related\n"));
+  GraphicsInit (ImageHandle, mDxePlatformSaPolicy);
+
+  ///
+  /// Audio (dHDA) Initialization
+  ///
+  DEBUG ((EFI_D_INFO, "Initializing CPU Audio (dHDA) device\n"));
+  AudioInit (ImageHandle, mDxePlatformSaPolicy);
+
+  //
+  // @todo remove this VP SKIP and prepare for PO settings to skip this code.
+  //
+  ///
+  /// Vtd Initialization
+  ///
+  DEBUG ((EFI_D_INFO, "Initializing VT-d\n"));
+  VtdInit (mDxePlatformSaPolicy);
+
+  ///
+  /// IgdOpRegion Install Initialization
+  ///
+  DEBUG ((EFI_D_INFO, "Initializing IGD OpRegion\n"));
+  IgdOpRegionInit ();
+
+
+  ///
+  /// Create PCI Enumeration Completed callback for SA
+  ///
+  EfiCreateProtocolNotifyEvent (
+    &gEfiPciEnumerationCompleteProtocolGuid,
+    EFI_TPL_CALLBACK,
+    SaPciEnumCompleteCallback,
+    NULL,
+    &Registration
+    );
+
+  ///
+  /// Create ExitPmAuth callback for SA
+  ///
+  EfiCreateProtocolNotifyEvent (
+    &gExitPmAuthProtocolGuid,
+    EFI_TPL_CALLBACK,
+    SaExitPmAuthCallback,
+    NULL,
+    &Registration
+    );
+
+  ///
+  /// Install SA_INFO_PROTOCOL
+  ///
+  SaInstance = AllocateZeroPool (sizeof (SA_INSTANCE_PRIVATE_DATA));
+  if (SaInstance == NULL) {
+    ASSERT (FALSE);
+    return EFI_OUT_OF_RESOURCES;
+  }
+
+  SaInstance->SaInfo.Revision = SA_INFO_PROTOCOL_REVISION_1;
+  ///
+  /// RCVersion[31:0] is the release number.
+  /// For example:
+  /// SaFramework 0.6.0.01 should be 00 06 00 01 (0x00060001)
+  /// SaFramework 0.6.2    should be 00 06 02 00 (0x00060200)
+  ///
+  SaInstance->SaInfo.RCVersion = SA_RC_VERSION;
+
+  Status = gBS->InstallMultipleProtocolInterfaces (
+                  &ImageHandle,
+                  &gEfiSaInfoProtocolGuid,
+                  &(SaInstance->SaInfo),
+                  NULL
+                  );
+
+  ///
+  /// Install System Agent Global NVS ACPI table
+  ///
+#ifndef Remove_SaSsdt_Data_To_Dsdt 
+  Status = InitializeSaSsdtAcpiTables ();
+#endif //AMI_OVERRIDE
+
+#ifdef SG_SUPPORT
+
+  DEBUG ((EFI_D_INFO, "Initializing Switchable Graphics (Dxe)\n"));
+  SwitchableGraphicsInit (ImageHandle, SystemTable, mDxePlatformSaPolicy);
+
+#endif
+
+  DEBUG ((EFI_D_INFO, "SaInitDxe End\n"));
+
+  return EFI_SUCCESS;
+}
+
+VOID
+DeviceConfigure (
+  IN DXE_PLATFORM_SA_POLICY_PROTOCOL *DxePlatformSaPolicy
+  )
+/**
+  Initialize GT Post Routines.
+
+    @param[in] ImageHandle         -     Handle for the image of this driver
+    @param[in] DxePlatformSaPolicy -     SA DxePlatformPolicy protocol
+**/
+{
+  UINT64  MchBar;
+
+  MchBar = McD0PciCfg64 (R_SA_MCHBAR) &~BIT0;
+
+  ///
+  /// Enable/Disable CHAP device (B0,D7,F0).
+  ///
+  if (DxePlatformSaPolicy->MiscConfig->ChapDeviceEnable) {
+    McD0PciCfg32Or (R_SA_DEVEN, B_SA_DEVEN_D7EN_MASK);
+  } else {
+    McD0PciCfg32And (R_SA_DEVEN, ~(B_SA_DEVEN_D7EN_MASK));
+  }
+  ///
+  /// Enable/Disable Thermal device (B0,D4,F0).
+  ///
+  if (DxePlatformSaPolicy->MiscConfig->Device4Enable) {
+    McD0PciCfg32Or (R_SA_DEVEN, B_SA_DEVEN_D4EN_MASK);
+  } else {
+    McD0PciCfg32And (R_SA_DEVEN, ~(B_SA_DEVEN_D4EN_MASK));
+  }
+  ///
+  /// Enable/Disable Audio device (B0,D3,F0).
+  ///
+  if ((DxePlatformSaPolicy->MiscConfig->AudioEnable) && (McD2PciCfg16 (R_SA_IGD_VID) != 0xFFFF)) {
+    McD0PciCfg32Or (R_SA_DEVEN, B_SA_DEVEN_D3EN_MASK);
+  } else {
+    McD0PciCfg32And (R_SA_DEVEN, ~(B_SA_DEVEN_D3EN_MASK));
+  }
+
+  return ;
+}
+
+VOID
+ProgramSvidSid (
+  IN DXE_PLATFORM_SA_POLICY_PROTOCOL *DxePlatformSaPolicy
+  )
+/**
+    Program SA devices Subsystem Vendor Identifier (SVID) and Subsystem Identifier (SID).
+
+    @param[in] DxePlatformSaPolicy   The SAPlatform Policy protocol instance
+**/
+{
+  UINT8                         Index;
+  UINT8                         BusNumber;
+  UINTN                         PciEAddressBase;
+  UINT8                         DeviceNumber;
+  UINT8                         FunctionNumber;
+  UINT8                         SvidRegOffset;
+  UINT16                        Data16;
+  STATIC SA_SVID_SID_INIT_ENTRY SvidSidInitTable[] = {
+    {
+      0,
+      0,
+      PCI_SVID_OFFSET
+    },
+    {
+      1,
+      0,
+      R_SA_PEG_SS_OFFSET
+    },
+    {
+      1,
+      1,
+      R_SA_PEG_SS_OFFSET
+    },
+    {
+      1,
+      2,
+      R_SA_PEG_SS_OFFSET
+    },
+    {
+      2,
+      0,
+      PCI_SVID_OFFSET
+    },
+    {
+      3,
+      0,
+      PCI_SVID_OFFSET
+    },
+    {
+      4,
+      0,
+      PCI_SVID_OFFSET
+    },
+    {
+      7,
+      0,
+      PCI_SVID_OFFSET
+    }
+  };
+
+  if ((DxePlatformSaPolicy->MiscConfig->DefaultSvidSid->SubSystemVendorId != 0) ||
+      (DxePlatformSaPolicy->MiscConfig->DefaultSvidSid->SubSystemId != 0)
+      ) {
+    for (Index = 0; Index < (sizeof (SvidSidInitTable) / sizeof (SA_SVID_SID_INIT_ENTRY)); Index++) {
+      BusNumber       = 0;
+      DeviceNumber    = SvidSidInitTable[Index].DeviceNumber;
+      FunctionNumber  = SvidSidInitTable[Index].FunctionNumber;
+      SvidRegOffset   = SvidSidInitTable[Index].SvidRegOffset;
+      PciEAddressBase = (UINT32) MmPciAddress (0, BusNumber, DeviceNumber, FunctionNumber, 0);
+      ///
+      /// Skip if the device is disabled
+      ///
+      if (MmioRead16 (PciEAddressBase + PCI_VID) == 0xFFFF) {
+        continue;
+      }
+      ///
+      /// Program SA devices Subsystem Vendor Identifier (SVID)
+      ///
+      Data16 = DxePlatformSaPolicy->MiscConfig->DefaultSvidSid->SubSystemVendorId;
+      MmioWrite16 (
+        (UINTN) (PciEAddressBase + SvidRegOffset),
+        Data16
+        );
+      SCRIPT_MEM_WRITE (
+        EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+        EfiBootScriptWidthUint16,
+        (UINTN) (PciEAddressBase + SvidRegOffset),
+        1,
+        (VOID *) (UINTN) (PciEAddressBase + SvidRegOffset)
+        );
+
+      ///
+      /// Program SA devices Subsystem Identifier (SID)
+      ///
+      Data16 = DxePlatformSaPolicy->MiscConfig->DefaultSvidSid->SubSystemId;
+      MmioWrite16 (
+        (UINTN) (PciEAddressBase + SvidRegOffset + 2),
+        Data16
+        );
+      SCRIPT_MEM_WRITE (
+        EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+        EfiBootScriptWidthUint16,
+        (UINTN) (PciEAddressBase + SvidRegOffset + 2),
+        1,
+        (VOID *) (UINTN) (PciEAddressBase + SvidRegOffset + 2)
+        );
+    }
+  }
+
+  return;
+}
+
+VOID
+SaFviExitPmAuth(
+  VOID
+  )
+/**
+  This function populates the SA FVI version numbers
+**/
+{
+  const UINT8               StrEnabled[sizeof (SA_CRID_ENABLED)]    = SA_CRID_ENABLED;
+  const UINT8               StrDisabled[sizeof (SA_CRID_DISABLED)]  = SA_CRID_DISABLED;
+  const CodeVersion         PcieRcVersion = {
+#include "SaPcieVersion.h"
+  };
+  const CodeVersion         MemRcVersion = {
+#include "MrcVersion.h"
+  };
+  EFI_STATUS                Status;
+  EFI_IA32_REGISTER_SET     RegSet;
+  UINT16                    VbiosBuildNum;
+  EFI_LEGACY_BIOS_PROTOCOL  *LegacyBios;
+
+  if (mDxePlatformSaPolicy->MiscConfig->FviReport) {
+    InitFviDataHubCbContext (
+      mDxePlatformSaPolicy->MiscConfig->FviSmbiosType,
+      (UINT8) mSaFviElements,
+      &mSaFviVersionData
+      );
+    mSaFviElementsData[MEM_RC_VER].Element.Version.MajorVersion = (UINT8) MemRcVersion.Major;
+    mSaFviElementsData[MEM_RC_VER].Element.Version.MinorVersion = (UINT8) MemRcVersion.Minor;
+    mSaFviElementsData[MEM_RC_VER].Element.Version.Revision     = (UINT8) MemRcVersion.Rev;
+    mSaFviElementsData[MEM_RC_VER].Element.Version.BuildNum     = (UINT16) MemRcVersion.Build;
+    mSaFviElementsData[PCIE_VER].Element.Version.MajorVersion   = (UINT8) PcieRcVersion.Major;
+    mSaFviElementsData[PCIE_VER].Element.Version.MinorVersion   = (UINT8) PcieRcVersion.Minor;
+    mSaFviElementsData[PCIE_VER].Element.Version.Revision       = (UINT8) PcieRcVersion.Rev;
+    mSaFviElementsData[PCIE_VER].Element.Version.BuildNum       = (UINT16) PcieRcVersion.Build;
+    mSaFviElementsData[CRID_ORIGINAL].Element.Version.BuildNum  = (UINT16) McD0PciCfg8 (PCI_REVISION_ID_OFFSET);
+
+    if (mDxePlatformSaPolicy->MiscConfig->CridEnable == TRUE) {
+      CopyMem (mSaFviElementsData[CRID_STATUS].Element.VerString, StrEnabled, sizeof (StrEnabled));
+    } else {
+      CopyMem (mSaFviElementsData[CRID_STATUS].Element.VerString, StrDisabled, sizeof (StrDisabled));
+    }
+
+    mSaFviElementsData[CRID_NEW].Element.Version.BuildNum = (UINT16) McD0PciCfg8 (PCI_REVISION_ID_OFFSET);
+    //
+    // Check IGFX device
+    //
+    VbiosBuildNum = 0xFFFF;
+    Status = gBS->LocateProtocol (&gEfiLegacyBiosProtocolGuid, NULL, (void **) &LegacyBios);
+    if (Status == EFI_SUCCESS) {
+      RegSet.X.AX   = 0x5f01;
+      Status        = LegacyBios->Int86 (LegacyBios, 0x15, &RegSet);
+      VbiosBuildNum = (((RegSet.X.DX & 0x0F00) << 4) | ((RegSet.X.DX & 0x000F) << 8) | ((RegSet.X.BX & 0x0F00) >> 4) | (RegSet.X.BX & 0x000F));
+    }
+    mSaFviElementsData[VBIOS_VER].Element.Version.BuildNum = VbiosBuildNum;
+
+    CreateRcFviDatahub (&mSaFviVersionData);
+  }
+}
+
+VOID
+EFIAPI
+SaPciEnumCompleteCallback (
+  IN EFI_EVENT    Event,
+  IN VOID         *Context
+  )
+/**
+  This function gets registered as a callback to perform SA initialization before ExitPmAuth
+
+  @param[in] Event     - A pointer to the Event that triggered the callback.
+  @param[in] Context   - A pointer to private data registered with the callback function.
+**/
+{
+  EFI_STATUS          Status;
+  VOID                *ProtocolPointer;
+
+  ///
+  /// Check if this is first time called by EfiCreateProtocolNotifyEvent() or not,
+  /// if it is, we will skip it until real event is triggered
+  ///
+  Status = gBS->LocateProtocol (&gEfiPciEnumerationCompleteProtocolGuid, NULL, &ProtocolPointer);
+  if (EFI_SUCCESS != Status) {
+     return;
+  }
+
+  gBS->CloseEvent (Event);
+
+  Status = PegInitBeforeExitPmAuth ();
+  if (EFI_SUCCESS != Status) {
+    DEBUG ((EFI_D_ERROR, "[SA] Pcie initialization before ExitPmAuth Error, Status = %x \n", Status));
+    ASSERT_EFI_ERROR (Status);
+  }
+}
+
+VOID
+EFIAPI
+SaExitPmAuthCallback (
+  IN EFI_EVENT    Event,
+  IN VOID         *Context
+  )
+/**
+  This function gets registered as a callback to perform SA configuration security lock
+
+  @param[in] Event     - A pointer to the Event that triggered the callback.
+  @param[in] Context   - A pointer to private data registered with the callback function.
+**/
+{
+  EFI_STATUS          Status;
+  VOID                *ProtocolPointer;
+
+  ///
+  /// Check if this is first time called by EfiCreateProtocolNotifyEvent() or not,
+  /// if it is, we will skip it until real event is triggered
+  ///
+  Status = gBS->LocateProtocol (&gExitPmAuthProtocolGuid, NULL, &ProtocolPointer);
+  if (EFI_SUCCESS != Status) {
+     return;
+  }
+
+  gBS->CloseEvent (Event);
+
+  if (McD2PciCfg16 (R_SA_IGD_VID) != 0xFFFF) {
+    Status = PostPmInitExitPmAuth();
+    if (EFI_SUCCESS != Status) {
+      DEBUG ((EFI_D_ERROR, "[SA] ExitPmAuth GraphicsInit Error, Status = %x \n", Status));
+      ASSERT_EFI_ERROR (Status);
+    }
+  }
+
+  UpdateDmarExitPmAuth();
+
+  if (McD2PciCfg16 (R_SA_IGD_VID) != 0xFFFF) {
+    Status = GetVBiosVbtExitPmAuth();
+    if (EFI_SUCCESS != Status) {
+      DEBUG ((EFI_D_ERROR, "[SA] ExitPmAuth Op Region Error, Status = %x \n", Status));
+    }
+
+    Status = UpdateIgdOpRegionExitPmAuth();
+    if (EFI_SUCCESS != Status) {
+      DEBUG ((EFI_D_ERROR, "[SA] ExitPmAuth Update Op Region Error, Status = %x \n", Status));
+    }
+  }
+
+  SaFviExitPmAuth();
+
+  Status = SaSecurityInit ();
+  if (EFI_SUCCESS != Status) {
+    DEBUG ((EFI_D_ERROR, "[SA] Security lock Error, Status = %x \n", Status));
+    ASSERT_EFI_ERROR (Status);
+  }
+  return;
+}
+
+VOID
+SaDxePolicyDump (
+  IN DXE_PLATFORM_SA_POLICY_PROTOCOL *mDxePlatformSaPolicy
+  )
+/**
+  This function prints the DXE phase platform policy.
+
+  @param[in] mDxePlatformSaPolicy - SA DxePlatformPolicy protocol
+**/
+{
+#ifdef EFI_DEBUG
+  INTN  i;
+
+  DEBUG ((EFI_D_INFO, "\n------------------------ SA Platform Policy (DXE) dump BEGIN -----------------\n"));
+  DEBUG ((EFI_D_INFO, "Revision : %x\n", mDxePlatformSaPolicy->Revision));
+  DEBUG ((EFI_D_INFO, "------------------------ SA_VTD_CONFIGURATION -----------------\n"));
+  DEBUG ((EFI_D_INFO, " VtdEnable : %x\n", mDxePlatformSaPolicy->Vtd->VtdEnable));
+  DEBUG ((EFI_D_INFO, " RmrrUsbBaseAddress : %x\n", mDxePlatformSaPolicy->Vtd->RmrrUsbBaseAddress));
+
+  DEBUG ((EFI_D_INFO, " VtdBaseAddress[%d] :", SA_VTD_ENGINE_NUMBER));
+  for (i = 0; i < SA_VTD_ENGINE_NUMBER; i++) {
+    DEBUG ((EFI_D_INFO, " %x", mDxePlatformSaPolicy->Vtd->BaseAddress[i]));
+  }
+  DEBUG ((EFI_D_INFO, "\n"));
+
+  DEBUG ((EFI_D_INFO, "------------------------ SA_MEMORY_CONFIGURATION -----------------\n"));
+  DEBUG ((EFI_D_INFO, " SpdAddressTable[%d] :", SA_MC_MAX_SOCKETS));
+  for (i = 0; i < SA_MC_MAX_SOCKETS; i++) {
+    DEBUG ((EFI_D_INFO, " %x", mDxePlatformSaPolicy->MemoryConfig->SpdAddressTable[i]));
+  }
+  DEBUG ((EFI_D_INFO, "\n"));
+
+  DEBUG ((EFI_D_INFO, " ChannelASlotMap : %x\n", mDxePlatformSaPolicy->MemoryConfig->ChannelASlotMap));
+  DEBUG ((EFI_D_INFO, " ChannelBSlotMap : %x\n", mDxePlatformSaPolicy->MemoryConfig->ChannelBSlotMap));
+  DEBUG ((EFI_D_INFO, " RmtBdatEnable : %x\n", mDxePlatformSaPolicy->MemoryConfig->RmtBdatEnable));
+  DEBUG ((EFI_D_INFO, " MrcTimeMeasure : %x\n", mDxePlatformSaPolicy->MemoryConfig->MrcTimeMeasure));
+  DEBUG ((EFI_D_INFO, " MrcFastBoot : %x\n", mDxePlatformSaPolicy->MemoryConfig->MrcFastBoot));
+
+  DEBUG ((EFI_D_INFO, "------------------------ SA_PCIE_CONFIGURATION -----------------\n"));
+  DEBUG ((EFI_D_INFO, " DmiAspm : %x\n", mDxePlatformSaPolicy->PcieConfig->DmiAspm));
+
+  DEBUG ((EFI_D_INFO, " PegAspm[%d] :", SA_PEG_MAX_FUN));
+  for (i = 0; i < SA_PEG_MAX_FUN; i++) {
+    DEBUG ((EFI_D_INFO, " %x", mDxePlatformSaPolicy->PcieConfig->PegAspm[i]));
+  }
+  DEBUG ((EFI_D_INFO, "\n"));
+
+  DEBUG ((EFI_D_INFO, " PegAspmL0s[%d] :", SA_PEG_MAX_FUN));
+  for (i = 0; i < SA_PEG_MAX_FUN; i++) {
+    DEBUG ((EFI_D_INFO, " %x", mDxePlatformSaPolicy->PcieConfig->PegAspmL0s[i]));
+  }
+  DEBUG ((EFI_D_INFO, "\n"));
+
+  DEBUG ((EFI_D_INFO, " PegDeEmphasis[%d] :", SA_PEG_MAX_FUN));
+  for (i = 0; i < SA_PEG_MAX_FUN; i++) {
+    DEBUG ((EFI_D_INFO, " %x", mDxePlatformSaPolicy->PcieConfig->PegDeEmphasis[i]));
+  }
+  DEBUG ((EFI_D_INFO, "\n"));
+
+  DEBUG ((EFI_D_INFO, " DmiExtSync : %x\n", mDxePlatformSaPolicy->PcieConfig->DmiExtSync));
+  DEBUG ((EFI_D_INFO, " DmiDeEmphasis : %x\n", mDxePlatformSaPolicy->PcieConfig->DmiDeEmphasis));
+  DEBUG ((EFI_D_INFO, " DmiIot : %x\n", mDxePlatformSaPolicy->PcieConfig->DmiIot));
+
+  if (mDxePlatformSaPolicy->Revision >= DXE_SA_PLATFORM_POLICY_PROTOCOL_REVISION_2) {
+    if (mDxePlatformSaPolicy->PcieConfig->PcieAspmDevsOverride != NULL) {
+      DEBUG ((EFI_D_INFO, "------------------------ PCIE_ASPM_DEV_INFO -----------------\n"));
+      DEBUG ((EFI_D_INFO, " VendorId DeviceId RevId RootApmcMask EndpointApmcMask\n"));
+      i = 0;
+      while ((mDxePlatformSaPolicy->PcieConfig->PcieAspmDevsOverride[i].VendorId != SA_PCIE_DEV_END_OF_TABLE) &&
+             (i < MAX_PCIE_ASPM_OVERRIDE)) {
+        DEBUG ((EFI_D_INFO, " %04x     %04x     %02x    %01x            %01x\n",
+          mDxePlatformSaPolicy->PcieConfig->PcieAspmDevsOverride[i].VendorId,
+          mDxePlatformSaPolicy->PcieConfig->PcieAspmDevsOverride[i].DeviceId,
+          mDxePlatformSaPolicy->PcieConfig->PcieAspmDevsOverride[i].RevId,
+          mDxePlatformSaPolicy->PcieConfig->PcieAspmDevsOverride[i].RootApmcMask,
+          mDxePlatformSaPolicy->PcieConfig->PcieAspmDevsOverride[i].EndpointApmcMask));
+        i++;
+      }
+      DEBUG ((EFI_D_INFO, "------------------------ END_OF_TABLE -----------------------\n"));
+    }
+    if (mDxePlatformSaPolicy->PcieConfig->PcieLtrDevsOverride != NULL) {
+      DEBUG ((EFI_D_INFO, "------------------------ PCIE_LTR_DEV_INFO -----------------\n"));
+      DEBUG ((EFI_D_INFO, " VendorId DeviceId RevId SnoopLatency NonSnoopLatency\n"));
+      i = 0;
+      while ((mDxePlatformSaPolicy->PcieConfig->PcieLtrDevsOverride[i].VendorId != SA_PCIE_DEV_END_OF_TABLE) &&
+             (i < MAX_PCIE_LTR_OVERRIDE)) {
+        DEBUG ((EFI_D_INFO, " %04x     %04x     %02x    %01x            %01x\n",
+          mDxePlatformSaPolicy->PcieConfig->PcieLtrDevsOverride[i].VendorId,
+          mDxePlatformSaPolicy->PcieConfig->PcieLtrDevsOverride[i].DeviceId,
+          mDxePlatformSaPolicy->PcieConfig->PcieLtrDevsOverride[i].RevId,
+          mDxePlatformSaPolicy->PcieConfig->PcieLtrDevsOverride[i].SnoopLatency,
+          mDxePlatformSaPolicy->PcieConfig->PcieLtrDevsOverride[i].NonSnoopLatency));
+        i++;
+      }
+      DEBUG ((EFI_D_INFO, "------------------------ END_OF_TABLE ----------------------\n"));
+    }
+  }
+
+  for (i = 0; i < SA_PEG_MAX_FUN; i++) {
+    DEBUG ((EFI_D_INFO, " PegPwrOpt[%d].LtrEnable            : %x\n", i, mDxePlatformSaPolicy->PcieConfig->PegPwrOpt[i].LtrEnable));
+    DEBUG ((EFI_D_INFO, " PegPwrOpt[%d].LtrMaxSnoopLatency   : %x\n", i, mDxePlatformSaPolicy->PcieConfig->PegPwrOpt[i].LtrMaxSnoopLatency));
+    DEBUG ((EFI_D_INFO, " PegPwrOpt[%d].ObffEnable           : %x\n", i, mDxePlatformSaPolicy->PcieConfig->PegPwrOpt[i].ObffEnable));
+    DEBUG ((EFI_D_INFO, " PegPwrOpt[%d].LtrMaxNoSnoopLatency : %x\n", i, mDxePlatformSaPolicy->PcieConfig->PegPwrOpt[i].LtrMaxNoSnoopLatency));
+  }
+
+  if (mDxePlatformSaPolicy->Revision >= DXE_SA_PLATFORM_POLICY_PROTOCOL_REVISION_3) {
+    DEBUG ((EFI_D_INFO, "------------------------ SA_SG_VBIOS_CONFIGURATION -----------------\n"));
+    DEBUG ((EFI_D_INFO, " LoadVbios : %x\n", mDxePlatformSaPolicy->VbiosConfig->LoadVbios));
+    DEBUG ((EFI_D_INFO, " ExecuteVbios : %x\n", mDxePlatformSaPolicy->VbiosConfig->ExecuteVbios));
+    DEBUG ((EFI_D_INFO, " VbiosSource : %x\n", mDxePlatformSaPolicy->VbiosConfig->VbiosSource));
+  }
+
+
+  DEBUG ((EFI_D_INFO, "------------------------ SA_IGD_CONFIGURATION -----------------\n"));
+  DEBUG ((EFI_D_INFO, " RenderStandby : %x\n", mDxePlatformSaPolicy->IgdConfig->RenderStandby));
+  DEBUG ((EFI_D_INFO, "------------------------ SA_MISC_CONFIGURATION -----------------\n"));
+  DEBUG ((EFI_D_INFO, " ChapDeviceEnable : %x\n", mDxePlatformSaPolicy->MiscConfig->ChapDeviceEnable));
+  DEBUG ((EFI_D_INFO, " Device4Enable : %x\n", mDxePlatformSaPolicy->MiscConfig->Device4Enable));
+  DEBUG ((EFI_D_INFO, " SubSystemVendorId : %x\n", mDxePlatformSaPolicy->MiscConfig->DefaultSvidSid->SubSystemVendorId));
+  DEBUG ((EFI_D_INFO, " SubSystemId : %x\n", mDxePlatformSaPolicy->MiscConfig->DefaultSvidSid->SubSystemId));
+  DEBUG ((EFI_D_INFO, " CridEnable : %x\n", mDxePlatformSaPolicy->MiscConfig->CridEnable));
+  DEBUG ((EFI_D_INFO, " AudioEnable : %x\n", mDxePlatformSaPolicy->MiscConfig->AudioEnable));
+  DEBUG ((EFI_D_INFO, " FviReport : %x\n", mDxePlatformSaPolicy->MiscConfig->FviReport));
+  DEBUG ((EFI_D_INFO, " FviSmbiosType : %x\n", mDxePlatformSaPolicy->MiscConfig->FviSmbiosType));
+  DEBUG ((EFI_D_INFO, "\n------------------------ SA Platform Policy (DXE) dump END -----------------\n"));
+#endif
+  return;
+}
diff --git a/ReferenceCode/Chipset/SystemAgent/SaInit/Dxe/SaInit.dxs b/ReferenceCode/Chipset/SystemAgent/SaInit/Dxe/SaInit.dxs
new file mode 100644
index 0000000..03c23ef
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/SaInit/Dxe/SaInit.dxs
@@ -0,0 +1,65 @@
+/** @file
+  @todo ADD DESCRIPTION
+
+@copyright
+  Copyright (c)  1999 - 2012 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains a 'Sample Driver' and is licensed as such
+  under the terms of your license agreement with Intel or your
+  vendor.  This file may be modified by the user, subject to
+  the additional terms of the license agreement
+
+**/
+
+//
+// Common for R8 and R9 codebase
+//
+#include "AutoGen.h"
+#include "DxeDepex.h"
+//
+// BUILD_WITH_GLUELIB and BUILD_WITH_EDKII_GLUE_LIB are both "defined" in R8 codebase;
+// BUILD_WITH_EDKII_GLUE_LIB is defined in Edk-Dev-Snapshot-20070228 and later version
+// BUILD_WITH_GLUELIB and BUILD_WITH_EDKII_GLUE_LIB are "not defined" in R9 codebase.
+//
+#if defined (BUILD_WITH_GLUELIB) || defined (BUILD_WITH_EDKII_GLUE_LIB)
+#include "EfiDepex.h"
+#endif
+
+#include EFI_PROTOCOL_DEPENDENCY      (SaPlatformPolicy)
+#include EFI_PROTOCOL_DEPENDENCY      (PciRootBridgeIo)
+#include EFI_PROTOCOL_DEPENDENCY      (BootScriptSave)
+#include EFI_PROTOCOL_DEPENDENCY      (AcpiSupport)
+#include EFI_PROTOCOL_DEPENDENCY      (PciHostBridgeResourceAllocation)
+#include EFI_PROTOCOL_DEPENDENCY      (CpuIo)
+#include EFI_PROTOCOL_DEPENDENCY      (DataHub)
+#include EFI_PROTOCOL_DEPENDENCY      (PowerMgmtInitDone)
+#if (EFI_SPECIFICATION_VERSION >= 0x0002000A)
+#include EFI_PROTOCOL_DEPENDENCY      (HiiDatabase)
+#else
+#include EFI_PROTOCOL_DEPENDENCY      (HII)
+#endif
+#include EFI_PROTOCOL_DEPENDENCY (FirmwareVolume)
+
+DEPENDENCY_START
+  EFI_ACPI_SUPPORT_GUID                                 AND
+  EFI_DATA_HUB_PROTOCOL_GUID                            AND
+  EFI_POWER_MGMT_INIT_DONE_PROTOCOL_GUID                AND
+  EFI_FIRMWARE_VOLUME_PROTOCOL_GUID                     AND
+  DXE_PLATFORM_SA_POLICY_GUID                           AND
+  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_GUID                  AND
+  EFI_BOOT_SCRIPT_SAVE_PROTOCOL_GUID                    AND
+  EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL_GUID AND
+  EFI_CPU_IO_PROTOCOL_GUID                              AND
+#if (EFI_SPECIFICATION_VERSION >= 0x0002000A)
+    EFI_HII_DATABASE_PROTOCOL_GUID
+#else
+    EFI_HII_PROTOCOL_GUID
+#endif
+DEPENDENCY_END
diff --git a/ReferenceCode/Chipset/SystemAgent/SaInit/Dxe/SaInit.h b/ReferenceCode/Chipset/SystemAgent/SaInit/Dxe/SaInit.h
new file mode 100644
index 0000000..a8c2b8f
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/SaInit/Dxe/SaInit.h
@@ -0,0 +1,194 @@
+/** @file
+  Header file for SA Initialization Driver.
+
+@copyright
+  Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement
+**/
+#ifndef _SA_INITIALIZATION_DRIVER_H_
+#define _SA_INITIALIZATION_DRIVER_H_
+
+///
+/// External include files do NOT need to be explicitly specified in real EDKII
+/// environment
+///
+#if !defined(EDK_RELEASE_VERSION) || (EDK_RELEASE_VERSION < 0x00020000)
+#include "EdkIIGlueDxe.h"
+#include "EfiScriptLib.h"
+#include "SaBuildFlags.h"
+#include "LegacyRegion.h"
+#include "Vtd.h"
+#include "GraphicsInit.h"
+#include "IgdOpregion.h"
+#include "PciExpressInit.h"
+#include "AudioInit.h"
+#include "RcFviDxeLib.h"
+#include "CpuRegs.h"
+#include "CpuPlatformLib.h"
+#include "PcieComplex.h"
+#include "VTd.h"
+#include "SwitchableGraphicsInit.h"
+
+///
+/// Driver Consumed Protocol Prototypes
+///
+#include EFI_PROTOCOL_DEFINITION (SaPlatformPolicy)
+#include EFI_PROTOCOL_PRODUCER (SaInfo)
+#endif
+///
+/// Data definitions
+///
+#define CRID_DATA 0x69
+#define CRID_LOCK 0x17
+
+typedef struct {
+  UINT64  BaseAddr;
+  UINT32  Offset;
+  UINT32  AndMask;
+  UINT32  OrMask;
+} BOOT_SCRIPT_REGISTER_SETTING;
+
+typedef struct {
+  UINT64                Address;
+  EFI_BOOT_SCRIPT_WIDTH Width;
+  UINT32                Value;
+} BOOT_SCRIPT_PCI_REGISTER_SAVE;
+
+typedef struct {
+  EFI_SA_INFO_PROTOCOL  SaInfo;
+} SA_INSTANCE_PRIVATE_DATA;
+
+typedef struct {
+  UINT8 DeviceNumber;
+  UINT8 FunctionNumber;
+  UINT8 SvidRegOffset;
+} SA_SVID_SID_INIT_ENTRY;
+
+#define SA_FVI_STRING          "Reference Code - SA - System Agent"
+#define SA_FVI_SMBIOS_TYPE     0xDD  ///< Default value
+#define SA_FVI_SMBIOS_INSTANCE 0x06
+#define MEM_FVI_STRING         "Reference Code - MRC"
+#define MEM_RC_VERSION \
+  { \
+    0xFF, 0xFF, 0xFF, 0xFFFF \
+  }
+#define PCIE_FVI_STRING "SA - PCIe Version"
+#define PCIE_RC_VERSION \
+  { \
+    0xFF, 0xFF, 0xFF, 0xFFFF \
+  }
+#define SA_CRID_STATUS          "SA-CRID Status"
+#define SA_CRID_ORIGINAL_VALUE  "SA-CRID Original Value"
+#define SA_CRID_NEW_VALUE       "SA-CRID New Value"
+#define SA_CRID_ENABLED         "Enabled "
+#define SA_CRID_DISABLED        "Disabled"
+#define SA_CRID_VERSION \
+  { \
+    0xFF, 0xFF, 0xFF, 0xFFFF \
+  }
+#define VBIOS_FVI_STRING        "OPROM - VBIOS"
+#define VBIOS_RC_VERSION \
+  { \
+    0xFF, 0xFF, 0xFF, 0xFFFF \
+  }
+
+enum {
+  SA_RC_VER     = 0,
+  MEM_RC_VER,
+  PCIE_VER,
+  CRID_STATUS,
+  CRID_ORIGINAL,
+  CRID_NEW,
+  VBIOS_VER
+} SA_FVI_INDEX;
+
+extern FVI_ELEMENT_AND_FUNCTION       mSaFviElementsData[];
+extern FVI_DATA_HUB_CALLBACK_CONTEXT  mSaFviVersionData;
+extern UINTN                          mSaFviElements;
+
+///
+/// Function Prototype
+///
+VOID
+EFIAPI
+SaPciEnumCompleteCallback (
+  IN EFI_EVENT Event,
+  IN VOID      *Context
+  )
+/**
+  This function gets registered as a callback to perform SA initialization before ExitPmAuth
+
+  @param[in] Event     - A pointer to the Event that triggered the callback.
+  @param[in] Context   - A pointer to private data registered with the callback function.
+
+  @retval EFI_SUCCESS   - Always.
+
+  **/
+;
+
+VOID
+EFIAPI
+SaExitPmAuthCallback (
+  IN EFI_EVENT Event,
+  IN VOID      *Context
+  )
+/**
+  This function gets registered as a callback to perform SA configuration security lock
+
+  @param[in] Event     - A pointer to the Event that triggered the callback.
+  @param[in] Context   - A pointer to private data registered with the callback function.
+
+  @retval EFI_SUCCESS   - Always.
+
+  **/
+;
+
+VOID
+DeviceConfigure (
+  IN DXE_PLATFORM_SA_POLICY_PROTOCOL *DxePlatformSaPolicy
+  )
+/**
+  This function performs SA internal devices enabling/disabling
+
+  @param[in] DxePlatformSaPolicy - SA DxePlatformPolicy protocol
+
+  **/
+;
+
+VOID
+ProgramSvidSid (
+  IN DXE_PLATFORM_SA_POLICY_PROTOCOL *DxePlatformSaPolicy
+  )
+/**
+    Program SA devices Subsystem Vendor Identifier (SVID) and Subsystem Identifier (SID).
+
+    @param[in] DxePlatformSaPolicy   The SAPlatform Policy protocol instance
+**/
+;
+
+VOID
+SaDxePolicyDump (
+  IN DXE_PLATFORM_SA_POLICY_PROTOCOL *mDxePlatformSaPolicy
+  )
+/**
+  This function prints the DXE phase platform policy.
+
+  @param[in] mDxePlatformSaPolicy - SA DxePlatformPolicy protocol
+
+  **/
+;
+
+#endif
diff --git a/ReferenceCode/Chipset/SystemAgent/SaInit/Dxe/SaInit.inf b/ReferenceCode/Chipset/SystemAgent/SaInit/Dxe/SaInit.inf
new file mode 100644
index 0000000..638f6da
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/SaInit/Dxe/SaInit.inf
@@ -0,0 +1,137 @@
+## @file
+#  Component description file for SystemAgent Initialization driver
+#
+#@copyright
+#  Copyright (c)  1999 - 2013 Intel Corporation. All rights reserved
+#  This software and associated documentation (if any) is furnished
+#  under a license and may only be used or copied in accordance
+#  with the terms of the license. Except as permitted by such
+#  license, no part of this software or documentation may be
+#  reproduced, stored in a retrieval system, or transmitted in any
+#  form or by any means without the express written consent of
+#  Intel Corporation.
+#
+#  This file contains a 'Sample Driver' and is licensed as such
+#  under the terms of your license agreement with Intel or your
+#  vendor.  This file may be modified by the user, subject to
+#  the additional terms of the license agreement
+#
+##
+
+[defines]
+BASE_NAME            = SaInit
+FILE_GUID            = DE23ACEE-CF55-4fb6-AA77-984AB53DE811
+COMPONENT_TYPE       = BS_DRIVER
+
+[sources.common]
+  SaInit.h
+  SaInit.c
+  LegacyRegion.h
+  LegacyRegion.c
+  Vtd.c
+  Vtd.h
+  IgdOpRegion.h
+  IgdOpRegion.c
+  GraphicsInit.h
+  GraphicsInit.c
+  PciExpressInit.h
+  PciExpressInit.c
+  PcieComplex.c
+  PcieComplex.h
+  AudioInit.c
+  AudioInit.h
+  SaFvi.c
+  SwitchableGraphicsInit.c
+  SwitchableGraphicsInit.h
+
+#
+# Edk II Glue Driver Entry Point
+#
+  EdkIIGlueDxeDriverEntryPoint.c
+
+[includes.common]
+  .
+  ../Common
+  $(EDK_SOURCE)/Foundation
+  $(EDK_SOURCE)/Foundation/Efi
+  $(EDK_SOURCE)/Foundation/Library
+  $(EDK_SOURCE)/Foundation/Efi/Include
+  $(EDK_SOURCE)/Foundation/core/Dxe
+  $(EDK_SOURCE)/Foundation/Include
+  $(EDK_SOURCE)/Foundation/Include/IndustryStandard
+  $(EDK_SOURCE)/Foundation/Framework
+  $(EDK_SOURCE)/Foundation/Framework/Include
+  $(EDK_SOURCE)/Foundation/Library/EdkIIGlueLib/Include
+  $(EDK_SOURCE)/Foundation/Library/EdkIIGlueLib/Include/pcd
+  $(EDK_SOURCE)/Foundation/Library/Dxe/Include
+  $(EDK_SOURCE)/Foundation/Cpu/Pentium/Include
+  $(EDK_SOURCE)/Foundation/Library/Dxe/UefiEfiIfrSupportLib
+  $(EFI_SOURCE)/$(PROJECT_SA_ROOT)
+  $(EFI_SOURCE)/$(PROJECT_PCH_ROOT)
+  $(EFI_SOURCE)/$(PROJECT_SA_ROOT)/Include
+  $(EFI_SOURCE)/$(PROJECT_SA_ROOT)/Protocol
+  $(EFI_SOURCE)/$(PROJECT_SA_ROOT)/$(PROJECT_SA_MRC)/Pei/Source/Include
+  $(EFI_SOURCE)/$(PROJECT_SA_ROOT)/Library/SaPcieLib/Common
+  $(EFI_SOURCE)/$(PROJECT_PCH_ROOT)/Include
+  $(EFI_SOURCE)/$(PROJECT_PCH_ROOT)/Include/Library
+  $(EFI_SOURCE)/$(PROJECT_PCH_ROOT)/Protocol
+  $(EFI_SOURCE)/$(PROJECT_CPU_ROOT)
+  $(EFI_SOURCE)/$(PROJECT_CPU_ROOT)/Include
+  $(EFI_SOURCE)/$(PROJECT_CPU_ROOT)/Include/Library
+  $(EFI_SOURCE)
+  $(EFI_SOURCE)/../MdePkg/Include
+
+#
+# Typically, the sample code referenced will be available in the code base already.
+# So, keep this include at the end to defer to the source base definition
+# and only use the sample code definition if source base does not include these files.
+#
+  $(EFI_SOURCE)/$(PROJECT_SA_ROOT)/SampleCode
+  $(EFI_SOURCE)/$(PROJECT_SA_ROOT)/SampleCode/Include
+
+[libraries.common]
+  EfiProtocolLib
+  EdkGuidLib
+  EfiCommonLib
+  EfiScriptLib
+  EdkIIGlueBaseLib
+  EdkIIGlueBaseIoLibIntrinsic
+  EdkIIGlueBaseMemoryLib
+  EdkIIGlueBasePciExpressLib
+  EdkIIGlueDxeReportStatusCodeLib
+  EdkIIGlueDxeDebugLibReportStatusCode
+  EdkIIGlueUefiBootServicesTableLib
+  EdkIIGlueUefiRuntimeServicesTableLib
+  EdkIIGlueDxeServicesTableLib
+  EdkIIGlueDxeHobLib
+  EdkIIGlueUefiLib
+  EdkIIGlueBasePciLibPciExpress
+  $(PROJECT_SA_FAMILY)ProtocolLib
+  $(PROJECT_PCH_FAMILY)ProtocolLib
+  RcFviDxeLib
+  PchPlatformLib
+  UefiEfiIfrSupportLib
+  SaGuidLib
+  EdkProtocolLib
+  CpuPlatformLib
+#
+# Comment out SaPcieDxeLib if ASPM initialization in DXE phase was not supported
+#
+  SaPcieDxeLib
+
+[nmake.common]
+  IMAGE_ENTRY_POINT = _ModuleEntryPoint
+  DPX_SOURCE = SaInit.dxs
+
+  C_FLAGS = $(C_FLAGS)  -D"__EDKII_GLUE_MODULE_ENTRY_POINT__=SaInitEntryPoint" \
+                        -D __EDKII_GLUE_BASE_IO_LIB_INTRINSIC__ \
+                        -D __EDKII_GLUE_BASE_LIB__ \
+                        -D __EDKII_GLUE_BASE_MEMORY_LIB__ \
+                        -D __EDKII_GLUE_DXE_REPORT_STATUS_CODE_LIB__ \
+                        -D __EDKII_GLUE_DXE_SERVICES_TABLE_LIB__ \
+                        -D __EDKII_GLUE_DXE_DEBUG_LIB_REPORT_STATUS_CODE__ \
+                        -D __EDKII_GLUE_UEFI_BOOT_SERVICES_TABLE_LIB__\
+                        -D __EDKII_GLUE_UEFI_RUNTIME_SERVICES_TABLE_LIB__ \
+                        -D __EDKII_GLUE_DXE_HOB_LIB__ \
+                        -D __EDKII_GLUE_BASE_PCI_LIB_PCI_EXPRESS__ \
+                        -D __EDKII_GLUE_UEFI_LIB__
diff --git a/ReferenceCode/Chipset/SystemAgent/SaInit/Dxe/SaInitDxe.cif b/ReferenceCode/Chipset/SystemAgent/SaInit/Dxe/SaInitDxe.cif
new file mode 100644
index 0000000..f705e96
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/SaInit/Dxe/SaInitDxe.cif
@@ -0,0 +1,30 @@
+<component>
+	name = "SaInitDxe"
+	category = ModulePart
+	LocalRoot = "ReferenceCode\Chipset\SystemAgent\SaInit\Dxe"
+	RefName = "SaInitDxe"
+[files]
+"SaInitDxe.sdl"	
+"SaInitDxe.mak"	
+"SaInit.c"
+"SaInit.dxs"
+"SaInit.h"
+"SaInit.inf"
+"graphicsinit.c"
+"graphicsinit.h"
+"igdopregion.c"
+"igdopregion.h"
+"LegacyRegion.c"
+"LegacyRegion.h"
+"PcieComplex.c"
+"PcieComplex.h"
+"PciExpressInit.c"
+"PciExpressInit.h"
+"VTd.c"
+"VTd.h"
+"AudioInit.c"
+"AudioInit.h"
+"SaFvi.c"
+"SwitchableGraphicsInit.c"
+"SwitchableGraphicsInit.h"
+<endComponent>
diff --git a/ReferenceCode/Chipset/SystemAgent/SaInit/Dxe/SaInitDxe.mak b/ReferenceCode/Chipset/SystemAgent/SaInit/Dxe/SaInitDxe.mak
new file mode 100644
index 0000000..809ba05
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/SaInit/Dxe/SaInitDxe.mak
@@ -0,0 +1,86 @@
+#---------------------------------------------------------------------------
+#   Create SaInitDxe Driver
+#---------------------------------------------------------------------------
+EDK : SaInitDxe
+
+SaInitDxe: $(BUILD_DIR)\SaInitDxe.mak SaInitDxeBin
+
+$(BUILD_DIR)\SaInitDxe.mak : $(SaInitDxe_DIR)\$(@B).cif $(SaInitDxe_DIR)\$(@B).mak $(BUILD_RULES)
+  $(CIF2MAK) $(SaInitDxe_DIR)\$(@B).cif $(CIF2MAK_DEFAULTS)
+
+SaInitDxe_INCLUDES=\
+  $(EdkIIGlueLib_INCLUDES)\
+  $(INTEL_MCH_INCLUDES) \
+  $(INTEL_PCH_INCLUDES)\
+  $(IndustryStandard_INCLUDES)\
+  $(INTEL_PLATFORM_PROTOCOL_INCLUDES)\
+  $(PROJECT_CPU_INCLUDES)\
+  /I$(INTEL_SYSTEM_AGENT_DIR)\Library\SaPcieLib\Common\
+  /I$(INTEL_SYSTEM_AGENT_DIR)\SampleCode\
+
+SaInitDxe_DEFINES =$(MY_DEFINES)\
+  /D "__EDKII_GLUE_MODULE_ENTRY_POINT__=SaInitEntryPoint" \
+  /D __EDKII_GLUE_BASE_IO_LIB_INTRINSIC__ \
+  /D __EDKII_GLUE_BASE_LIB__ \
+  /D __EDKII_GLUE_BASE_MEMORY_LIB__ \
+  /D __EDKII_GLUE_DXE_REPORT_STATUS_CODE_LIB__ \
+  /D __EDKII_GLUE_DXE_SERVICES_TABLE_LIB__ \
+  /D __EDKII_GLUE_DXE_DEBUG_LIB_REPORT_STATUS_CODE__ \
+  /D __EDKII_GLUE_UEFI_BOOT_SERVICES_TABLE_LIB__\
+  /D __EDKII_GLUE_DXE_HOB_LIB__ \
+  /D __EDKII_GLUE_UEFI_LIB__\
+  /D __EDKII_GLUE_UEFI_RUNTIME_SERVICES_TABLE_LIB__ \
+  /D __EDKII_GLUE_BASE_PCI_LIB_PCI_EXPRESS__ \
+
+SaInitDxe_LIB_LINKS =\
+    $(EFIPROTOCOLLIB)\
+    $(EDKGUIDLIB)\
+    $(EFICOMMONLIB)\
+    $(EFISCRIPTLIB)\
+    $(EdkIIGlueBaseLib_LIB)\
+!IF "$(x64_BUILD)"=="1"
+    $(EdkIIGlueBaseLibX64_LIB)\
+!ELSE
+    $(EdkIIGlueBaseLibIA32_LIB)\
+!ENDIF
+    $(EdkIIGlueBaseIoLibIntrinsic_LIB)\
+    $(EdkIIGlueBaseMemoryLib_LIB)\
+    $(EdkIIGlueDxeReportStatusCodeLib_LIB)\
+    $(EdkIIGlueDxeDebugLibReportStatusCode_LIB)\
+    $(EdkIIGlueUefiBootServicesTableLib_LIB)\
+    $(EdkIIGlueDxeServicesTableLib_LIB)\
+    $(EdkIIGlueDxeHobLib_LIB)\
+    $(EdkIIGlueUefiLib_LIB)\
+    $(INTEL_SA_PROTOCOL_LIB)\
+    $(INTEL_PCH_PROTOCOL_LIB)\
+    $(IntelPlatformProtocolLib_LIB)\
+!IF $(EFI_SPECIFICATION_VERSION) >= 0x0002000A
+    $(UEFIEFIIFRSUPPORTLIB)\
+!ELSE
+    $(EFIIFRSUPPORTLIB) \
+!ENDIF
+    $(SaGuidLib_LIB)\
+  	$(EdkIIGlueBasePciExpressLib_LIB)\
+    $(EdkIIGlueUefiRuntimeServicesTableLib_LIB)\
+    $(EdkIIGlueBasePciLibPciExpress_LIB)\
+    $(EDKPROTOCOLLIB)\
+    $(RcFviDxeLib_LIB)\
+    $(PchPlatformDxeLib_LIB)\
+    $(CpuPlatformLib_LIB)\
+#
+# Comment out SaPcieDxeLib if ASPM initialization in DXE phase was not supported
+#
+    $(SaPcieDxeLib_LIB)\
+
+SaInitDxeBin: $(SaInitDxe_LIB_LINKS)
+    $(MAKE) /$(MAKEFLAGS) $(EDKIIGLUE_DEFAULTS)\
+    /f $(BUILD_DIR)\SaInitDxe.mak all \
+    "MY_INCLUDES=$(SaInitDxe_INCLUDES)"\
+    "MY_DEFINES=$(SaInitDxe_DEFINES)"\
+    GUID=DE23ACEE-CF55-4fb6-AA77-984AB53DE811\
+    ENTRY_POINT=_ModuleEntryPoint \
+    TYPE=BS_DRIVER\
+    EDKIIModule=DXEDRIVER\
+    DEPEX1=$(SaInitDxe_DIR)\SaInit.dxs\
+    DEPEX1_TYPE=EFI_SECTION_DXE_DEPEX\
+    COMPRESS=1
diff --git a/ReferenceCode/Chipset/SystemAgent/SaInit/Dxe/SaInitDxe.sdl b/ReferenceCode/Chipset/SystemAgent/SaInit/Dxe/SaInitDxe.sdl
new file mode 100644
index 0000000..e4a95b4
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/SaInit/Dxe/SaInitDxe.sdl
@@ -0,0 +1,24 @@
+TOKEN
+  Name  = "SaInitDxe_SUPPORT"
+  Value  = "1"
+  Help  = "Main switch to enable SaInitDxe support in Project"
+  TokenType = Boolean
+  TargetEQU = Yes
+  TargetMAK = Yes
+  Master = Yes
+End
+
+PATH
+  Name  = "SaInitDxe_DIR"
+End
+
+MODULE
+  File  = "SaInitDxe.mak"
+  Help  = "Includes SaInitDxe.mak to Project"
+End
+
+ELINK
+  Name  = "$(BUILD_DIR)\SaInitDxe.ffs"
+  Parent  = "FV_MAIN"
+  InvokeOrder = AfterParent
+End
\ No newline at end of file
diff --git a/ReferenceCode/Chipset/SystemAgent/SaInit/Dxe/SwitchableGraphicsInit.c b/ReferenceCode/Chipset/SystemAgent/SaInit/Dxe/SwitchableGraphicsInit.c
new file mode 100644
index 0000000..599a01a
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/SaInit/Dxe/SwitchableGraphicsInit.c
@@ -0,0 +1,958 @@
+/** @file
+  SwitchableGraphics Dxe driver.
+  This DXE driver loads SwitchableGraphics acpi tables
+  for the platform.
+
+@copyright
+  Copyright (c) 2010 - 2013 Intel Corporation. All rights reserved.
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement
+
+**/
+
+#include "SwitchableGraphicsInit.h"
+#include EFI_PROTOCOL_CONSUMER (ExitPmAuth)
+#include <Token.h>  //<< AMI_OVERRIDE >>
+
+extern DXE_PLATFORM_SA_POLICY_PROTOCOL *mDxePlatformSaPolicy;
+
+EFI_BOOT_SERVICES     *gBS;
+SA_DATA_HOB           *SaDataHob;
+
+EFI_GUID              gSaDataHobGuid = SA_DATA_HOB_GUID;
+EFI_GUID              gSgAcpiTableStorageGuid = SG_ACPI_TABLE_STORAGE_GUID;
+EFI_GUID              gSgAcpiTablePchStorageGuid = SG_ACPI_TABLE_PCH_STORAGE_GUID;
+
+VOID                  *VbiosAddress = NULL;
+BOOLEAN               DgpuOpRomCopied;
+UINT32                VbiosSize;
+
+UINT8                 EndpointBus;
+UINT16                GpioBaseAddress;
+UINT8                 GpioSupport;
+
+UINT8                 RootPortDev;
+UINT8                 RootPortFun;
+
+CPU_FAMILY            CpuFamilyId;
+
+// AMI MODIFY BEGIN
+EFI_STATUS
+LoadTpvAcpiTables(
+  VOID
+  );
+// AMI MODIFY END
+
+/**
+  Initialize the SwitchableGraphics support (DXE).
+
+  @param[in] ImageHandle         - Handle for the image of this driver
+  @param[in] DxePlatformSaPolicy - SA DxePlatformPolicy protocol
+
+  @retval EFI_SUCCESS         - SwitchableGraphics initialization complete
+  @retval EFI_OUT_OF_RESOURCES - Unable to allocated memory
+  @retval EFI_NOT_FOUND        - SA DataHob not found
+  @retval EFI_DEVICE_ERROR     - Error Accessing SG GPIO
+**/
+EFI_STATUS
+SwitchableGraphicsInit (
+  IN EFI_HANDLE                      ImageHandle,
+  IN EFI_SYSTEM_TABLE                *SystemTable,
+  IN DXE_PLATFORM_SA_POLICY_PROTOCOL *DxePlatformSaPolicy
+  )
+{
+  EFI_STATUS  Status;
+  VOID        *Registration;
+  UINTN       PciD31F0RegBase;
+  UINT32      RootComplexBar;
+  UINT32      RpFn;
+
+  CpuFamilyId = GetCpuFamily();
+
+  if (CpuFamilyId == EnumCpuHswUlt) {
+      /// For SwitchableGraphics support the dGPU is present on PCH RootPort
+      RootPortDev = PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORTS;
+    //AMI override begin
+      RootPortFun = SG_ULT_PORT_FUNC;
+	//RootPortFun = PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_5;
+    //AMI override end
+
+      PciD31F0RegBase = MmPciAddress (
+                          0,
+                          DEFAULT_PCI_BUS_NUMBER_PCH,
+                          PCI_DEVICE_NUMBER_PCH_LPC,
+                          PCI_FUNCTION_NUMBER_PCH_LPC,
+                          0
+                          );
+      RootComplexBar  = MmioRead32 (PciD31F0RegBase + R_PCH_LPC_RCBA) & B_PCH_LPC_RCBA_BAR;
+      RpFn = MmioRead32 (RootComplexBar + R_PCH_RCRB_RPFN);
+      /// dGPU sits on Root Port 5 [1-based]
+      /// Root Port 5 Function Number (RP5FN) = RPFN[18:16]
+      //AMI override begin
+      //RootPortFun = (UINT8) ((RpFn >> (4 * S_PCH_RCRB_PRFN_RP_FIELD)) & B_PCH_RCRB_RPFN_RP1FN);
+      RootPortFun = (UINT8) ((RpFn >> (RootPortFun * S_PCH_RCRB_PRFN_RP_FIELD)) & B_PCH_RCRB_RPFN_RP1FN);
+      ////AMI override end
+  } else {
+      /// Assume: For SwitchableGraphics support the dGPU is present on PEG RootPort by default
+      RootPortDev = SA_PEG10_DEV_NUM;
+      RootPortFun = SA_PEG10_FUN_NUM;
+  }
+
+  DEBUG ((EFI_D_INFO, "dGPU Rootport info[B/D/F] : [0x00/0x%x/0x%x]\n", RootPortDev, RootPortFun));
+
+  gBS = SystemTable->BootServices;
+
+  ///
+  /// Get SG GPIO info from SA HOB.
+  ///
+  Status = EfiGetSystemConfigurationTable (&gEfiHobListGuid, (VOID **) &SaDataHob);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+
+  SaDataHob = GetNextGuidHob (&gSaDataHobGuid, SaDataHob);
+  if (SaDataHob == NULL) {
+    return EFI_NOT_FOUND;
+  }
+
+  GpioSupport = SaDataHob->SgInfo.SgGpioSupport;
+
+  ///
+  /// Read GPIO base
+  ///
+  GpioBaseAddress = McDevFunPciCfg16 (0, PCI_DEVICE_NUMBER_PCH_LPC, 0, R_PCH_LPC_GPIO_BASE) &~BIT0;
+  if (GpioBaseAddress == 0) {
+    return EFI_DEVICE_ERROR;
+  }
+
+  ///
+  /// Update GlobalNvs data for runtime usage
+  ///
+  Status = UpdateGlobalNvsData (SaDataHob->SgInfo, DxePlatformSaPolicy);
+// AMI MODIFY BEGIN
+  DEBUG ((EFI_D_INFO, "SG:: OEM SSDT start"));
+#if SGOEMSSDT_SUPPORT
+     // Load OEM SSDT 
+  if (SaDataHob->SgInfo.SgMode == SgModeDgpu) { // In PEG mode
+
+  DEBUG ((EFI_D_INFO, "SG:: OEM SSDT start1"));
+    Status = LoadAndExecuteDgpuVbios (mDxePlatformSaPolicy->VbiosConfig);
+      return Status;
+   }
+#endif
+// AMI MODIFY END
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+
+  ///
+  /// Load Intel SG SSDT tables
+  ///
+  Status = LoadAcpiTables ();
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+
+  ///
+  /// Check to see if Switchable Graphics Mode is enabled
+  ///
+  if (SaDataHob->SgInfo.SgMode == SgModeMuxless) {
+  ///
+  /// Create ReadyToBoot callback for SG
+  ///
+  EfiCreateProtocolNotifyEvent (
+    &gExitPmAuthProtocolGuid,
+    EFI_TPL_CALLBACK,
+    SgExitPmAuthCallback,
+    NULL,
+    &Registration
+    );
+  }
+
+  return Status;
+}
+
+/**
+  Initialize the runtime SwitchableGraphics support data for ACPI tables in GlobalNvs.
+
+  @param[in] SaDataHob->SgInfo   - Pointer to Hob for SG system details.
+  @param[in] DxePlatformSaPolicy - Pointer to the loaded image protocol for this driver.
+
+  @retval EFI_SUCCESS - The data updated successfully.
+**/
+EFI_STATUS
+UpdateGlobalNvsData (
+  IN SG_INFO_HOB                     SgInfo,
+  IN DXE_PLATFORM_SA_POLICY_PROTOCOL *DxePlatformSaPolicy
+  )
+{
+  SYSTEM_AGENT_GLOBAL_NVS_AREA_PROTOCOL  *SaGlobalNvsArea;
+  UINT8                                  CapOffset;
+  UINT16                                 ExtendedCapOffset;
+  EFI_STATUS                             Status;
+  UINT32                                 Data32;
+
+  ///
+  ///  Locate the SA Global NVS Protocol.
+  ///
+  Status = gBS->LocateProtocol (
+                  &gSaGlobalNvsAreaProtocolGuid,
+                  NULL,
+                  (VOID **) &SaGlobalNvsArea
+                  );
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+  ///
+  /// SG Mode for ASL usage
+  ///
+  SaGlobalNvsArea->Area->SgMode               |= SaDataHob->SgInfo.SgMode;
+
+  SaGlobalNvsArea->Area->PXFixedDynamicMode   = SaDataHob->SgInfo.PXFixedDynamicMode; // AMI_OVERRIDE_FOR ATI 5.0 Fixed/Dynamic
+
+  SaGlobalNvsArea->Area->GpioBaseAddress      = GpioBaseAddress;
+
+  SaGlobalNvsArea->Area->SgGPIOSupport = SaDataHob->SgInfo.SgGpioSupport;
+
+  DEBUG ((EFI_D_INFO, "SG:: Switchable Graphics Mode : 0x%x\n", SaDataHob->SgInfo.SgMode));
+
+  if (SaDataHob->SgInfo.SgMode == SgModeMuxless) {
+    ///
+    /// SG Feature List for ASL usage
+    ///
+    //SaGlobalNvsArea->Area->SgFeatureList |= DxePlatformSaPolicy->FeatureList->WirelessDisplay;
+
+    if (SaDataHob->SgInfo.SgGpioSupport) {
+      ///
+      /// GPIO Assignment for ASL usage
+      ///
+      SaGlobalNvsArea->Area->SgDgpuPwrOK      = SaDataHob->SgInfo.SgDgpuPwrOK;
+      SaGlobalNvsArea->Area->SgDgpuHoldRst    = SaDataHob->SgInfo.SgDgpuHoldRst;
+      SaGlobalNvsArea->Area->SgDgpuPwrEnable  = SaDataHob->SgInfo.SgDgpuPwrEnable;
+      SaGlobalNvsArea->Area->SgDgpuPrsnt      = SaDataHob->SgInfo.SgDgpuPrsnt;
+
+      DEBUG ((EFI_D_INFO, "SG:: dGPU_PWROK GPIO   GPIO assigned = %d\n", SaDataHob->SgInfo.SgDgpuPwrOK & 0x7f));
+      DEBUG ((EFI_D_INFO, "SG:: dGPU_HOLD_RST#    GPIO assigned = %d\n", SaDataHob->SgInfo.SgDgpuHoldRst & 0x7f));
+      DEBUG ((EFI_D_INFO, "SG:: dGPU_PWR_EN#      GPIO assigned = %d\n", SaDataHob->SgInfo.SgDgpuPwrEnable & 0x7f));
+      DEBUG ((EFI_D_INFO, "SG:: dGPU_PRSNT#       GPIO assigned = %d\n", SaDataHob->SgInfo.SgDgpuPrsnt & 0x7f));
+    }
+
+    DEBUG ((EFI_D_INFO, "SG:: VBIOS Configurations:\n"));
+    DEBUG (
+      (
+      EFI_D_INFO, "SG:: Load VBIOS    (0=No Vbios;1=Load VBIOS)         =%d\n", DxePlatformSaPolicy->VbiosConfig->
+      LoadVbios
+      )
+      );
+    DEBUG (
+      (
+      EFI_D_INFO, "SG:: Execute VBIOS (0=Do not execute;1=Execute Vbios)  =%d\n", DxePlatformSaPolicy->VbiosConfig->
+      ExecuteVbios
+      )
+      );
+    DEBUG (
+      (
+      EFI_D_INFO, "SG:: VBIOS Source  (0=PCIE Card;1=FW Volume)         =%d\n", DxePlatformSaPolicy->VbiosConfig->
+      VbiosSource
+      )
+      );
+
+    ///
+    /// PEG Endpoint Base Addresses and Capability Structure Offsets for ASL usage
+    ///
+
+    ///
+    /// Save bus numbers on the PEG/PCH bridge.
+    ///
+    Data32 = MmPci32 (0, 0, RootPortDev, RootPortFun, PCI_PBUS);
+    Data32 &= 0x00FFFF00;
+
+    ///
+    /// Set PEG/PCH PortBus = 1 to Read Endpoint.
+    ///
+    MmPci32AndThenOr (0, 0, RootPortDev, RootPortFun, PCI_PBUS, 0xFF0000FF, 0x00010100);
+
+    ///
+    /// A config write is required in order for the device to re-capture the Bus number,
+    /// according to PCI Express Base Specification, 2.2.6.2
+    /// Write to a read-only register VendorID to not cause any side effects.
+    ///
+    McDevFunPciCfg16 (1, 0, 0, PCI_VID) = 0;
+
+    EndpointBus = MmPci8 (0, 0, RootPortDev, RootPortFun, PCI_SBUS);
+
+    if (EndpointBus != 0xFF) {
+      //AMI override begin
+      SaGlobalNvsArea->Area->EndpointBaseAddress = (UINT32) (MmPciAddress (0, EndpointBus, 0, 0, 0x0));
+      //AMI override end
+      SaGlobalNvsArea->Area->CapStrPresence = 0;
+
+      CapOffset = (UINT8) PcieFindCapId (EndpointBus, 0, 0, PEG_CAP_ID);
+      SaGlobalNvsArea->Area->EndpointPcieCapOffset = CapOffset;
+      DEBUG ((EFI_D_INFO, "SG:: Endpoint PCI Express Capability Offset : 0x%x\n", SaGlobalNvsArea->Area->EndpointPcieCapOffset));
+
+      ExtendedCapOffset = (UINT16) PcieFindExtendedCapId (EndpointBus, 0, 0, PEG_CAP_VER);
+      if (ExtendedCapOffset != 0) {
+        SaGlobalNvsArea->Area->CapStrPresence |= BIT0;
+        SaGlobalNvsArea->Area->EndpointVcCapOffset = ExtendedCapOffset;
+        DEBUG ((EFI_D_INFO, "SG:: Endpoint Virtual Channel Capability Offset : 0x%x\n", SaGlobalNvsArea->Area->EndpointVcCapOffset));
+      }
+   }
+
+    ///
+    /// Restore bus numbers on the PEG/PCH bridge.
+    ///
+    MmPci32AndThenOr (0, 0, RootPortDev, RootPortFun, PCI_PBUS, 0xFF0000FF, Data32);
+  } else {
+    DEBUG ((EFI_D_ERROR, "SG:: Switchable Graphics Mode disabled!!!\n"));
+    Status = EFI_LOAD_ERROR;
+  }
+
+  return Status;
+}
+
+/**
+  Load and execute the dGPU VBIOS.
+
+  @param[in] VbiosConfig - Pointer to VbiosConfig policy for Load/Execute and VBIOS Source.
+      LoadVbios    - 0 = Do Not Load   ; 1 = Load VBIOS
+      ExecuteVbios - 0 = Do Not Execute; 1 = Execute VBIOS
+      VbiosSource  - 0 = PCIE Device   ; 1 = FirmwareVolume => TBD
+
+  @retval EFI_SUCCESS     - Load and execute successful.
+  @exception EFI_UNSUPPORTED - Secondary VBIOS not loaded.
+**/
+EFI_STATUS
+LoadAndExecuteDgpuVbios (
+  IN SA_SG_VBIOS_CONFIGURATION    *VbiosConfig
+  )
+{
+  EFI_HANDLE                *HandleBuffer;
+  UINTN                     HandleCount;
+  UINTN                     Index;
+  VBIOS_PCIR_STRUCTURE      *PcirBlockPtr;
+  EFI_STATUS                Status;
+  EFI_PCI_IO_PROTOCOL       *PciIo;
+  VBIOS_OPTION_ROM_HEADER   *VBiosRomImage;
+  EFI_LEGACY_BIOS_PROTOCOL  *LegacyBios;
+  EFI_IA32_REGISTER_SET     RegSet;
+  EFI_PHYSICAL_ADDRESS      ImageLocation;
+  UINTN                     Offset;
+
+  HandleBuffer = NULL;
+  DgpuOpRomCopied = FALSE;
+
+  DEBUG ((EFI_D_INFO, "SG:: LoadAndExecuteDgpuVbios\n"));
+
+  ///
+  /// Endpoint Device Bus#
+  ///
+  EndpointBus = MmPci8 (0, 0, RootPortDev, RootPortFun, PCI_SBUS);
+
+  ///
+  ///  Endpoint Device Not found
+  ///
+  if (EndpointBus == 0xFF) {
+    DEBUG ((EFI_D_ERROR, "SG:: 0x00/0x%x/0x%x Rootport's Endpoint Device Not found\n", RootPortDev, RootPortFun));
+    return EFI_UNSUPPORTED;
+  }
+
+  ///
+  /// Check Policy setting for loading VBIOS
+  ///
+  if (VbiosConfig->LoadVbios != 0) {
+
+    DEBUG ((EFI_D_INFO, "SG:: Start to load dGPU VBIOS if available\n"));
+
+    ///
+    /// Set as if an umcompressed video BIOS image was not obtainable.
+    ///
+    VBiosRomImage = NULL;
+
+    ///
+    /// Get all PCI IO protocols
+    ///
+    Status = gBS->LocateHandleBuffer (
+                    ByProtocol,
+                    &gEfiPciIoProtocolGuid,
+                    NULL,
+                    &HandleCount,
+                    &HandleBuffer
+                    );
+    if (EFI_ERROR (Status)) {
+      return Status;
+    }
+
+    ///
+    /// Find the video BIOS by checking each PCI IO handle for DGPU video
+    /// BIOS OPROM.
+    ///
+    for (Index = 0; Index < HandleCount; Index++) {
+      Status = gBS->HandleProtocol (
+                      HandleBuffer[Index],
+                      &gEfiPciIoProtocolGuid,
+                      (VOID **) &PciIo
+                      );
+      if (EFI_ERROR (Status) || (PciIo->RomImage == NULL)) {
+        ///
+        /// If this PCI device doesn't have a ROM image, skip to the next device.
+        ///
+        continue;
+      }
+
+      VBiosRomImage = PciIo->RomImage;
+
+      ///
+      /// Get pointer to PCIR structure
+      ///
+      PcirBlockPtr = (VBIOS_PCIR_STRUCTURE *) ((UINTN) VBiosRomImage + VBiosRomImage->PcirOffset);
+      //AMI override begin
+      if (( PcirBlockPtr->VendorId != 0x10DE) && (PcirBlockPtr->VendorId != 0x1002)){
+        continue;
+      }
+      //AMI override end
+      ///
+      /// Check if we have an video BIOS OPROM for DGPU.
+      ///
+      if ((VBiosRomImage->Signature == OPTION_ROM_SIGNATURE) &&
+          (McDevFunPciCfg16 (EndpointBus, 0, 0, PCI_VID) == PcirBlockPtr->VendorId) &&
+          (PcirBlockPtr->ClassCode[2] == 0x03)
+          ) {
+
+        DEBUG ((EFI_D_INFO, "SG:: Loading dGPU VBIOS...\n"));
+
+        ///
+        /// Allocate space for copying Oprom
+        ///
+        VbiosSize = (PcirBlockPtr->ImageLength) * 512;
+        Status    = (gBS->AllocatePool) (EfiBootServicesData, VbiosSize, &VbiosAddress);
+        if (EFI_ERROR (Status)) {
+          break;
+        }
+	  
+        ///
+        /// Execute VBIOS based on Policy setting
+        ///
+        if (VbiosConfig->ExecuteVbios) {
+          DEBUG ((EFI_D_INFO, "SG:: Execute dGPU VBIOS...\n"));
+          ///
+          /// Memory IO Bus Master needs to be enabled when we execute the vbios
+          ///
+          ///
+          /// Enable Memory Access, IO Access Bus Master enable on PEG/PCH ROOT PORT
+          ///
+          MmPci16Or (0, 0, RootPortDev, RootPortFun, PCI_CMD, BIT0 + BIT1 + BIT2);
+
+          ///
+          /// Enable Memory Access, IO Access Bus Master enable and Rom Enable on Peg/PCH Endpoint device
+          ///
+          McDevFunPciCfg16Or (EndpointBus, 0, 0, PCI_CMD, BIT0 + BIT1 + BIT2);
+
+          ///
+          /// Allocate 64kb under 1MB memory region
+          ///
+          Status = AllocateLegacyMemory (
+                    AllocateMaxAddress,
+                    CONVENTIONAL_MEMORY_TOP,
+                    (BIN_FILE_SIZE_MAX / 4096),
+                    &ImageLocation
+                    );
+          if (!EFI_ERROR (Status)) {
+            (gBS->SetMem) ((VOID *) (UINTN) ImageLocation, BIN_FILE_SIZE_MAX, 0);
+
+            ///
+            /// After allocation copy VBIOS to buffer
+            ///
+            (gBS->CopyMem) ((VOID *) (UINTN) ImageLocation, PciIo->RomImage, VbiosSize);
+
+            Status = gBS->LocateProtocol (
+                            &gEfiLegacyBiosProtocolGuid,
+                            NULL,
+                            (VOID **) &LegacyBios
+                            );
+            if (!EFI_ERROR (Status)) {
+              (gBS->SetMem) (&RegSet, sizeof (EFI_IA32_REGISTER_SET), 0);
+
+              RegSet.H.AH = MmPci8 (0, 0, RootPortDev, RootPortFun, PCI_SBUS);
+              Offset      = MemoryRead16 ((UINTN) ImageLocation + 0x40);
+              LegacyBios->FarCall86 (
+                            LegacyBios,
+                            ((UINT16) RShiftU64 ((ImageLocation & 0x000FFFF0),
+                          4)),
+                            ((UINT16) Offset),
+                            &RegSet,
+                            NULL,
+                            0
+                            );
+
+              Offset = MemoryRead16 ((UINTN) ImageLocation + 0x42) + (UINTN) ImageLocation;
+              if (MemoryRead16 ((UINTN) ImageLocation + 0x44) == 0x0) {
+                VbiosSize = MemoryRead8 ((UINTN) ImageLocation + 0x2) * 512;
+              } else {
+                VbiosSize = MemoryRead16 ((UINTN) ImageLocation + 0x44) * 512;
+              }
+              ///
+              /// Copy Oprom to allocated space for the following scenario:
+              /// # Load vbios and Execute vbios policy setting
+              ///
+              DEBUG ((EFI_D_INFO, "Copy Oprom to allocated space: Load & Execute policy satisfied\n"));
+              (gBS->CopyMem) (VbiosAddress, (VOID *) Offset, VbiosSize);
+              DgpuOpRomCopied = TRUE;
+              (gBS->SetMem) ((VOID *) (UINTN) ImageLocation, BIN_FILE_SIZE_MAX, 0);
+            }
+            (gBS->FreePages) (ImageLocation, (BIN_FILE_SIZE_MAX / 4096));
+          }
+
+          ///
+          /// Disable Memory Access, IO Access Bus Master enable and Rom Enable on PEG/PCH Endpoint device
+          ///
+          McDevFunPciCfg16And (EndpointBus, 0, 0, PCI_CMD, ~(BIT0 + BIT1 + BIT2));
+
+          ///
+          /// Disable Memory Access, IO Access Bus Master enable on PEG/PCH Root Port
+          ///
+          MmPci16And (0, 0, RootPortDev, RootPortFun, PCI_CMD, ~(BIT0 + BIT1 + BIT2));
+        } 
+		
+        ///
+        /// Copy Oprom to allocated space  for the following scenario:
+        /// # Load vbios and Execute vbios policy setting in which dGPU execution is not called
+        /// # Load vbios but don't Execute vbios policy setting
+        ///
+        if ((VbiosAddress!=NULL) && (!DgpuOpRomCopied)) {
+          DEBUG ((EFI_D_INFO, "Copy Oprom to allocated space: Load policy satisfied\n"));
+          (gBS->CopyMem) (VbiosAddress, PciIo->RomImage, VbiosSize);
+          DgpuOpRomCopied = TRUE;
+        }
+
+    // AMI MODIFY BEGIN
+    //
+    //
+#ifdef AMI_SgTpv_SUPPORT
+    if (!EFI_ERROR (Status)) {
+      Status = LoadTpvAcpiTables ();
+    }
+#endif // AMI_SgTpv_SUPPORT
+    //
+    // AMI MODIFY ENDS
+    //
+        break;
+      }
+    }
+
+  }
+  
+
+  if (VbiosAddress!=NULL) {
+    (gBS->FreePool) (VbiosAddress);
+  }
+
+  if (HandleBuffer!=NULL) {
+    (gBS->FreePool) (HandleBuffer);
+  }
+
+  return EFI_SUCCESS;
+}
+
+/**
+  Read SG GPIO value
+
+  @param[in] Value - PCH GPIO number and Active value
+      Bit0 to Bit7    - PCH GPIO Number
+      Bit8            - GPIO Active value (0 = Active Low; 1 = Active High)
+
+  @retval GPIO read value.
+**/
+BOOLEAN
+GpioRead (
+  IN UINT8 Value
+  )
+{
+  BOOLEAN Active;
+  UINT32  Data;
+  UINT16  BitOffset=0;
+  UINT16  Offset=0;
+
+  ///
+  /// Check if SG GPIOs are supported
+  ///
+  if (GpioSupport == 0) {
+    return FALSE;
+  }
+  ///
+  /// Extract GPIO number and Active value
+  ///
+  Active = (BOOLEAN) (Value >> 7);
+  Value &= 0x7F;
+
+  if (CpuFamilyId == EnumCpuHswUlt) {
+      Offset    = R_PCH_GP_N_CONFIG0 + (Value * 0x08);
+      BitOffset = 30; //GPI_LVL
+  } else {
+    if (Value < 0x20) {
+      Offset    = R_PCH_GPIO_LVL;
+      BitOffset = Value;
+    } else if (Value < 0x40) {
+      Offset    = R_PCH_GPIO_LVL2;
+      BitOffset = Value - 0x20;
+    } else {
+      Offset    = R_PCH_GPIO_LVL3;
+      BitOffset = Value - 0x40;
+    }
+  }
+
+  ///
+  /// Read specified value GPIO
+  ///
+  Data = IoRead32 (GpioBaseAddress + Offset);
+  Data >>= BitOffset;
+
+  if (Active == 0) {
+    Data = ~Data;
+  }
+
+  return (BOOLEAN) (Data & 0x1);
+}
+
+/**
+  Write SG GPIO value
+
+  @param[in] Value - PCH GPIO number and Active value
+      Bit0 to Bit7    - PCH GPIO Number
+      Bit8            - GPIO Active value (0 = Active Low; 1 = Active High)
+  @param[in] Level - Write data (0 = Disable; 1 = Enable)
+**/
+VOID
+GpioWrite (
+  IN UINT8   Value,
+  IN BOOLEAN Level
+  )
+{
+  BOOLEAN Active;
+  UINT32  Data;
+  UINT16  BitOffset=0;
+  UINT16  Offset=0;
+
+  ///
+  /// Check if SG GPIOs are supported
+  ///
+  if (GpioSupport == 0) {
+    return ;
+  }
+
+  Active = (BOOLEAN) (Value >> 7);
+  Value &= 0x7F;
+
+  if (Active == 0) {
+    Level = (~Level) & 0x1;
+  }
+
+  if (CpuFamilyId == EnumCpuHswUlt) {
+      Offset    = R_PCH_GP_N_CONFIG0 + (Value * 0x08);
+      BitOffset = 31; //GPO_LVL
+  } else {
+    if (Value < 0x20) {
+      Offset    = R_PCH_GPIO_LVL;
+      BitOffset = Value;
+    } else if (Value < 0x40) {
+      Offset    = R_PCH_GPIO_LVL2;
+      BitOffset = Value - 0x20;
+    } else {
+      Offset    = R_PCH_GPIO_LVL3;
+      BitOffset = Value - 0x40;
+    }
+  }
+
+  Data = IoRead32 (GpioBaseAddress + Offset);
+  Data &= ~(0x1 << BitOffset);
+  Data |= (Level << BitOffset);
+  IoWrite32 (GpioBaseAddress + Offset, Data);
+
+  return ;
+}
+
+/**
+  Do an AllocatePages () of type AllocateMaxAddress for EfiBootServicesCode
+  memory.
+
+  @param[in] AllocateType     - Allocated Legacy Memory Type
+  @param[in] StartPageAddress - Start address of range
+  @param[in] Pages            - Number of pages to allocate
+  @param[in, out] Result      - Result of allocation
+
+  @retval EFI_SUCCESS - Legacy16 code loaded
+  @retval Other       - No protocol installed, unload driver.
+**/
+EFI_STATUS
+AllocateLegacyMemory (
+  IN  EFI_ALLOCATE_TYPE         AllocateType,
+  IN  EFI_PHYSICAL_ADDRESS      StartPageAddress,
+  IN  UINTN                     Pages,
+  IN OUT  EFI_PHYSICAL_ADDRESS  *Result
+  )
+{
+  EFI_STATUS            Status;
+  EFI_PHYSICAL_ADDRESS  MemPage;
+
+  ///
+  /// Allocate Pages of memory less <= StartPageAddress
+  ///
+  MemPage = (EFI_PHYSICAL_ADDRESS) (UINTN) StartPageAddress;
+  Status  = (gBS->AllocatePages) (AllocateType, EfiBootServicesCode, Pages, &MemPage);
+
+  ///
+  /// Do not ASSERT on Status error but let caller decide since some cases
+  /// memory is already taken but that is ok.
+  ///
+  if (!EFI_ERROR (Status)) {
+    *Result = (EFI_PHYSICAL_ADDRESS) (UINTN) MemPage;
+  }
+
+  return Status;
+}
+
+/**
+  Load Intel SG SSDT Tables
+
+  @param[in] None
+
+  @retval EFI_SUCCESS - SG SSDT Table load successful.
+**/
+EFI_STATUS
+LoadAcpiTables (
+  VOID
+  )
+{
+  EFI_STATUS                    Status;
+  EFI_HANDLE                    *HandleBuffer;
+  BOOLEAN                       LoadTable;
+  UINTN                         NumberOfHandles;
+  UINTN                         Index;
+  INTN                          Instance;
+  UINTN                         Size;
+  UINT32                        FvStatus;
+  UINTN                         TableHandle;
+  EFI_GUID                      AcpiTableGuid;
+  EFI_FV_FILETYPE               FileType;
+  EFI_FV_FILE_ATTRIBUTES        Attributes;
+  EFI_FIRMWARE_VOLUME_PROTOCOL  *FwVol;
+  EFI_ACPI_TABLE_PROTOCOL       *AcpiTable;
+  EFI_ACPI_TABLE_VERSION        Version;
+  EFI_ACPI_DESCRIPTION_HEADER   *TableHeader;
+  EFI_ACPI_COMMON_HEADER        *Table;
+
+  FwVol         = NULL;
+  Table         = NULL;
+
+  AcpiTableGuid = gSgAcpiTableStorageGuid;
+  if (CpuFamilyId == EnumCpuHswUlt) {
+    AcpiTableGuid = gSgAcpiTablePchStorageGuid;
+  }
+
+  DEBUG ((EFI_D_INFO, "SG:: Loading ACPI Tables...\n"));
+
+  ///
+  /// Locate FV protocol.
+  ///
+  Status = gBS->LocateHandleBuffer (
+                  ByProtocol,
+                  &gEfiFirmwareVolumeProtocolGuid,
+                  NULL,
+                  &NumberOfHandles,
+                  &HandleBuffer
+                  );
+  ASSERT_EFI_ERROR (Status);
+
+  ///
+  /// Look for FV with ACPI storage file
+  ///
+  for (Index = 0; Index < NumberOfHandles; Index++) {
+    ///
+    /// Get the protocol on this handle
+    /// This should not fail because of LocateHandleBuffer
+    ///
+    Status = gBS->HandleProtocol (
+                    HandleBuffer[Index],
+                    &gEfiFirmwareVolumeProtocolGuid,
+                    (VOID **) &FwVol
+                    );
+    ASSERT_EFI_ERROR (Status);
+    if (FwVol == NULL) {
+      return EFI_NOT_FOUND;
+    }
+    ///
+    /// See if it has the ACPI storage file
+    ///
+    Size      = 0;
+    FvStatus  = 0;
+    Status = FwVol->ReadFile (
+                      FwVol,
+                      &AcpiTableGuid,
+                      NULL,
+                      &Size,
+                      &FileType,
+                      &Attributes,
+                      &FvStatus
+                      );
+
+    ///
+    /// If we found it, then we are done
+    ///
+    if (!EFI_ERROR (Status)) {
+      break;
+    }
+  }
+  ///
+  /// Our exit status is determined by the success of the previous operations
+  /// If the protocol was found, Instance already points to it.
+  ///
+  ///
+  /// Free any allocated buffers
+  ///
+  (gBS->FreePool) (HandleBuffer);
+
+  ///
+  /// Sanity check that we found our data file
+  ///
+  ASSERT (FwVol);
+
+  ///
+  /// By default, a table belongs in all ACPI table versions published.
+  ///
+  Version = EFI_ACPI_TABLE_VERSION_1_0B | EFI_ACPI_TABLE_VERSION_2_0 | EFI_ACPI_TABLE_VERSION_3_0;
+
+  ///
+  /// Locate ACPI tables
+  ///
+  Status = gBS->LocateProtocol (&gEfiAcpiTableProtocolGuid, NULL, (VOID **) &AcpiTable);
+
+  ///
+  /// Read tables from the storage file.
+  ///
+  if (FwVol == NULL) {
+    ASSERT_EFI_ERROR (EFI_NOT_FOUND);
+    return EFI_NOT_FOUND;
+  }
+  Instance = 0;
+
+  while (Status == EFI_SUCCESS) {
+    ///
+    /// Read the ACPI tables
+    ///
+    Status = FwVol->ReadSection (
+                      FwVol,
+                      &AcpiTableGuid,
+                      EFI_SECTION_RAW,
+                      Instance,
+                      (VOID **) &Table,
+                      &Size,
+                      &FvStatus
+                      );
+    if (!EFI_ERROR (Status)) {
+      ///
+      /// check and load SwitchableGraphics SSDT table
+      ///
+      LoadTable   = FALSE;
+      TableHeader = (EFI_ACPI_DESCRIPTION_HEADER *) Table;
+
+      if (((EFI_ACPI_DESCRIPTION_HEADER *) TableHeader)->OemTableId == EFI_SIGNATURE_64 (
+          'S',
+          'g',
+          'P',
+          'e',
+          'g',
+          0,
+          0,
+          0
+          )
+          ) {
+        ///
+        /// This is SG SSDT [dGPU is present on PEG RootPort]
+        ///
+        DEBUG ((EFI_D_INFO, "SG:: ---- SG SSDT ----\n"));
+        DEBUG ((EFI_D_INFO, "SG:: Found out SSDT:SgPeg [SgSsdt.asl]. dGPU is present on PEG RootPort.\n"));
+        LoadTable = TRUE;
+      } 
+	  
+	  if (((EFI_ACPI_DESCRIPTION_HEADER *) TableHeader)->OemTableId == EFI_SIGNATURE_64 (
+          'S',
+          'g',
+          'P',
+          'c',
+          'h',
+          0,
+          0,
+          0
+          )
+          ) {
+        ///
+        /// This is SG SSDT [dGPU is present on PCH RootPort]
+        ///
+        DEBUG ((EFI_D_INFO, "SG:: ---- SG SSDT ----\n"));
+        DEBUG ((EFI_D_INFO, "SG:: Found out SSDT:SgPch [SgSsdtPch.asl]. dGPU is present on PCH RootPort.\n"));
+        LoadTable = TRUE;
+      }
+
+      ///
+      /// Add the table
+      ///
+      if (LoadTable) {
+        TableHandle = 0;
+        Status = AcpiTable->InstallAcpiTable (
+                                  AcpiTable,
+                                  TableHeader,
+                                  TableHeader->Length,
+                                  &TableHandle
+                                  );
+      }
+      ///
+      /// Increment the instance
+      ///
+      Instance++;
+      Table = NULL;
+    }
+  }
+
+  return EFI_SUCCESS;
+}
+
+
+VOID
+EFIAPI
+SgExitPmAuthCallback (
+  IN EFI_EVENT Event,
+  IN VOID      *Context
+  )
+{
+  EFI_STATUS  Status;
+  VOID        *ProtocolPointer;
+
+  ///
+  /// Check if this is first time called by EfiCreateProtocolNotifyEvent() or not,
+  /// if it is, we will skip it until real event is triggered
+  ///
+  Status = gBS->LocateProtocol (&gExitPmAuthProtocolGuid, NULL, &ProtocolPointer);
+  if (EFI_SUCCESS != Status) {
+     return;
+  }
+
+  gBS->CloseEvent (Event);
+
+  DEBUG ((EFI_D_INFO, "SG:: ExitPmAuth Callback\n"));
+  ///
+  /// Load and Execute dGPU VBIOS
+  ///
+  Status = LoadAndExecuteDgpuVbios (mDxePlatformSaPolicy->VbiosConfig);
+}
diff --git a/ReferenceCode/Chipset/SystemAgent/SaInit/Dxe/SwitchableGraphicsInit.h b/ReferenceCode/Chipset/SystemAgent/SaInit/Dxe/SwitchableGraphicsInit.h
new file mode 100644
index 0000000..4d32f8f
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/SaInit/Dxe/SwitchableGraphicsInit.h
@@ -0,0 +1,267 @@
+/** @file
+  Header file for the SwitchableGraphics Dxe driver.
+  This driver loads SwitchableGraphics ACPI tables.
+
+@copyright
+  Copyright (c) 2010 - 2012 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement
+
+**/
+
+#ifndef _SWITCHABLE_GRAPHICS_DXE_H_
+#define _SWITCHABLE_GRAPHICS_DXE_H_
+
+//
+// External include files do NOT need to be explicitly specified in real EDKII
+// environment
+//
+#if !defined(EDK_RELEASE_VERSION) || (EDK_RELEASE_VERSION < 0x00020000)
+#include "EdkIIGlueDxe.h"
+#include "EfiScriptLib.h"
+#endif
+
+#include "CpuRegs.h"
+#include "CpuPlatformLib.h"
+
+#include "PchAccess.h"
+#include "Acpi3_0.h"
+#include "SaAccess.h"
+
+#include EFI_PROTOCOL_DEPENDENCY (PciIo)
+#include EFI_PROTOCOL_DEPENDENCY (AcpiTable)
+#include EFI_PROTOCOL_DEPENDENCY (FirmwareVolume)
+#include EFI_PROTOCOL_DEPENDENCY (SaGlobalNvsArea)
+#include EFI_GUID_DEFINITION (SaDataHob)
+#include EFI_PROTOCOL_DEFINITION (SaPlatformPolicy)
+
+///
+/// SG ACPI table data storage file
+///
+#include EFI_GUID_DEFINITION (SgAcpiTableStorage)
+
+///
+/// Switchable Graphics defines.
+///
+#define CONVENTIONAL_MEMORY_TOP 0xA0000 ///< 640 KB
+#define BIN_FILE_SIZE_MAX       0x10000
+
+#define OPTION_ROM_SIGNATURE    0xAA55
+
+#define MemoryRead16(Address)   * (UINT16 *) (Address)
+#define MemoryRead8(Address)    * (UINT8 *) (Address)
+
+///
+/// PEG Capability Equates
+///
+#define PEG_CAP_ID  0x10
+#define PEG_CAP_VER 0x2
+
+#pragma pack(1)
+typedef struct {
+  UINT16  Signature;  ///< 0xAA55
+  UINT8   Reserved[22];
+  UINT16  PcirOffset;
+} VBIOS_OPTION_ROM_HEADER;
+#pragma pack()
+
+#pragma pack(1)
+typedef struct {
+  UINT32  Signature;  ///< "PCIR"
+  UINT16  VendorId;
+  UINT16  DeviceId;
+  UINT16  Reserved0;
+  UINT16  Length;
+  UINT8   Revision;
+  UINT8   ClassCode[3];
+  UINT16  ImageLength;
+  UINT16  CodeRevision;
+  UINT8   CodeType;
+  UINT8   Indicator;
+  UINT16  Reserved1;
+} VBIOS_PCIR_STRUCTURE;
+#pragma pack()
+
+/**
+  Initialize the SwitchableGraphics support.
+
+  @param[in] ImageHandle         - Handle for the image of this driver
+  @param[in] DxePlatformSaPolicy - SA DxePlatformPolicy protocol
+
+  @retval EFI_SUCCESS         - SwitchableGraphics initialization complete
+  @retval EFI_OUT_OF_RESOURCES - Unable to allocated memory
+**/
+EFI_STATUS
+SwitchableGraphicsInit (
+  IN EFI_HANDLE                      ImageHandle,
+  IN EFI_SYSTEM_TABLE                *SystemTable,
+  IN DXE_PLATFORM_SA_POLICY_PROTOCOL *DxePlatformSaPolicy
+  )
+;
+
+/**
+  Load and execute the dGPU VBIOS.
+
+  @param[in] VbiosData - Pointer to VbiosData policy for Load/Execute and VBIOS Source.
+      LoadVbios    - 0 = Do Not Load   ; 1 = Load VBIOS
+      ExecuteVbios - 0 = Do Not Execute; 1 = Execute VBIOS
+      VbiosSource  - 0 = PCIE Device   ; 1 = FirmwareVolume => TBD
+
+  @retval EFI_SUCCESS     - Load and execute successful.
+  @exception EFI_UNSUPPORTED - Secondary VBIOS not loaded.
+**/
+EFI_STATUS
+LoadAndExecuteDgpuVbios (
+  IN SA_SG_VBIOS_CONFIGURATION  *VbiosConfig
+  )
+;
+
+/**
+  Initialize the runtime SwitchableGraphics support data for ACPI tables in GlobalNvs.
+  @param[in] SgInfoDataHob   - Pointer to Hob for SG system details.
+  @param[in] DxePlatformSgPolicy - Pointer to the loaded image protocol for this driver.
+
+  @retval EFI_SUCCESS - The data updated successfully.
+**/
+EFI_STATUS
+UpdateGlobalNvsData (
+  IN SG_INFO_HOB                     SgInfo,
+  IN DXE_PLATFORM_SA_POLICY_PROTOCOL *DxePlatformSaPolicy
+  )
+;
+
+/**
+  Do an AllocatePages () of type AllocateMaxAddress for EfiBootServicesCode
+  memory.
+
+  @param[in] AllocateType     - Allocated Legacy Memory Type
+  @param[in] StartPageAddress - Start address of range
+  @param[in] Pages            - Number of pages to allocate
+  @param[in, out] Result      - Result of allocation
+
+  @retval EFI_SUCCESS - Legacy16 code loaded
+  @retval Other       - No protocol installed, unload driver.
+**/
+EFI_STATUS
+AllocateLegacyMemory (
+  IN  EFI_ALLOCATE_TYPE         AllocateType,
+  IN  EFI_PHYSICAL_ADDRESS      StartPageAddress,
+  IN  UINTN                     Pages,
+  IN OUT  EFI_PHYSICAL_ADDRESS  *Result
+  )
+;
+
+/**
+  Search and return the offset of desired Pci Express Capability ID
+    CAPID list:
+      0x0001 = Advanced Error Rreporting Capability
+      0x0002 = Virtual Channel Capability
+      0x0003 = Device Serial Number Capability
+      0x0004 = Power Budgeting Capability
+
+    @param[in] Bus       -   Pci Bus Number
+    @param[in] Device    -   Pci Device Number
+    @param[in] Function  -   Pci Function Number
+    @param[in] CapId     -   Extended CAPID to search for
+
+    @retval 0       - CAPID not found
+    @retval Other   - CAPID found, Offset of desired CAPID
+**/
+UINT32
+PcieFindExtendedCapId (
+  IN UINT8  Bus,
+  IN UINT8  Device,
+  IN UINT8  Function,
+  IN UINT16 CapId
+  )
+;
+
+/**
+  Find the Offset to a given Capabilities ID
+    CAPID list:
+      0x01 = PCI Power Management Interface
+      0x04 = Slot Identification
+      0x05 = MSI Capability
+      0x10 = PCI Express Capability
+
+    @param[in] Bus       -   Pci Bus Number
+    @param[in] Device    -   Pci Device Number
+    @param[in] Function  -   Pci Function Number
+    @param[in] CapId     -   CAPID to search for
+
+    @retval 0       - CAPID not found
+    @retval Other   - CAPID found, Offset of desired CAPID
+**/
+UINT32
+PcieFindCapId (
+  IN UINT8 Bus,
+  IN UINT8 Device,
+  IN UINT8 Function,
+  IN UINT8 CapId
+  )
+;
+
+/**
+  Read SG GPIO value
+
+  @param[in] Value - PCH GPIO number and Active value
+      Bit0 to Bit7    - PCH GPIO Number
+      Bit8            - GPIO Active value (0 = Active Low; 1 = Active High)
+
+  @retval GPIO read value.
+**/
+BOOLEAN
+GpioRead (
+  IN UINT8 Value
+  )
+;
+
+/**
+  Write SG GPIO value
+
+  @param[in] Value - PCH GPIO number and Active value
+      Bit0 to Bit7    - PCH GPIO Number
+      Bit8            - GPIO Active value (0 = Active Low; 1 = Active High)
+  @param[in] Level - Write data (0 = Disable; 1 = Enable)
+**/
+VOID
+GpioWrite (
+  IN UINT8   Value,
+  IN BOOLEAN Level
+  )
+;
+
+/**
+  Load Intel SG SSDT Tables
+
+  @param[in] None
+
+  @retval EFI_SUCCESS - SG SSDT Table load successful.
+**/
+EFI_STATUS
+LoadAcpiTables (
+  VOID
+  )
+;
+
+
+VOID
+EFIAPI
+SgExitPmAuthCallback (
+  IN EFI_EVENT  Event,
+  IN VOID       *Context
+  );
+
+#endif
diff --git a/ReferenceCode/Chipset/SystemAgent/SaInit/Dxe/VTd.c b/ReferenceCode/Chipset/SystemAgent/SaInit/Dxe/VTd.c
new file mode 100644
index 0000000..1dea621
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/SaInit/Dxe/VTd.c
@@ -0,0 +1,934 @@
+/** @file
+  This code provides a initialization of intel VT-d (Virtualization Technology for Directed I/O).
+
+@copyright
+  Copyright (c) 1999 - 2013 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement
+
+@todo assumption is ANDD table will use device path to be loaded dynamically, need to use pchplatformpolicy if assumption is incorrect.
+**/
+#include "SaInit.h"
+#include "VTd.h"
+
+UINT32                           mPchRootComplexBar;
+DXE_PLATFORM_SA_POLICY_PROTOCOL  *mDxePlatformSaPolicy;
+DXE_PCH_PLATFORM_POLICY_PROTOCOL *mDxePlatformPchPolicy;
+PCH_SERIES                       mPchSeries;
+
+/**
+For device that specified by Device Num and Function Num,
+mDevEnMap is used to check device presence.
+  0x80 means use Device ID to detemine presence
+
+ The structure is used to check if device scope is valid when update DMAR table
+**/
+UINT16  mDevEnMap[][2] = {
+  {
+    0x0200,
+    0x80
+  },  ///< D2F0
+  {
+    0x1D00,
+    0x80
+  },  ///< D29F0
+  {
+    0x1A00,
+    0x80
+  },  ///< D26F0
+  {
+    0x1400,
+    0x80
+  }   ///< D20F0
+};
+
+BOOLEAN mInterruptRemappingSupport;
+
+UINT16
+GetFunDisableBit (
+  UINT8 DevNum,
+  UINT8 FunNum
+  )
+/**
+    Get the corresponding device Enable/Disable bit according DevNum and FunNum
+
+    @param[in] DevNum  - Device Number
+    @param[in] FunNum  - Function Number
+
+    @retval If the device is found, return disable/Enable bit in FD/Deven reigster
+    @retval If not found return 0xFF
+**/
+{
+  UINTN Index;
+
+  for (Index = 0; Index < sizeof (mDevEnMap) / 4; Index++) {
+    if (mDevEnMap[Index][0] == ((DevNum << 0x08) | FunNum)) {
+      return mDevEnMap[Index][1];
+    }
+  }
+
+  return 0xFF;
+}
+
+VOID
+UpdateDRHD (
+  IN OUT VOID *DrhdEnginePtr
+  )
+/**
+    Update the DRHD structure
+
+    @param[in, out] DrhdEnginePtr       - A pointer to DRHD structure
+**/
+{
+  UINT16                        Length;
+  UINT16                        DisableBit;
+  UINTN                         DeviceScopeNum;
+  BOOLEAN                       NeedRemove;
+  EFI_ACPI_DRHD_ENGINE1_STRUCT  *DrhdEngine;
+
+  //
+  // Convert DrhdEnginePtr to EFI_ACPI_DRHD_ENGINE1_STRUCT Pointer
+  //
+  DrhdEngine      = (EFI_ACPI_DRHD_ENGINE1_STRUCT *) DrhdEnginePtr;
+
+  Length          = DrhdEngine->Length;
+  DeviceScopeNum  = (DrhdEngine->Length - EFI_ACPI_DRHD_ENGINE_HEADER_LENGTH) / sizeof (EFI_ACPI_DEV_SCOPE_STRUCTURE);
+  DisableBit = GetFunDisableBit (
+                DrhdEngine->DeviceScope[0].PciPath[0],
+                DrhdEngine->DeviceScope[0].PciPath[1]
+                );
+  NeedRemove = FALSE;
+  if ((DisableBit == 0xFF) ||
+      (DrhdEngine->RegisterBaseAddress == 0) ||
+      ((DisableBit == 0x80) &&
+      (MmPci32 (0, 0, DrhdEngine->DeviceScope[0].PciPath[0], DrhdEngine->DeviceScope[0].PciPath[1], 0x00) == 0xFFFFFFFF))
+      ){
+        NeedRemove = TRUE;
+  }
+  if (NeedRemove) {
+    Length -= sizeof (EFI_ACPI_DEV_SCOPE_STRUCTURE);
+  }
+  ///
+  /// If no devicescope is left, we set the structure length as 0x00
+  ///
+  if ((Length > EFI_ACPI_DRHD_ENGINE_HEADER_LENGTH) || (DrhdEngine->Flags == 0x01)) {
+    DrhdEngine->Length = Length;
+  } else {
+    DrhdEngine->Length = 0;
+  }
+}
+
+UINT8
+GetIoApicID (
+  VOID
+  )
+/**
+    Get IOAPIC ID from LPC
+
+    @retval APIC ID
+**/
+{
+  UINT8 VOLATILE  *IoapicIndex;
+  UINT32 VOLATILE *IoapicData;
+  UINT32          Data32;
+
+  ///
+  /// Get IOAPIC base
+  ///
+  IoapicIndex = (UINT8 *) (UINTN) (R_PCH_IO_APIC_INDEX + ((PchMmRcrb16 (R_PCH_RCRB_OIC) & 0x0ff) << 12));
+  IoapicData  = (UINT32 *) (UINTN) (R_PCH_IO_APIC_DATA + ((PchMmRcrb16 (R_PCH_RCRB_OIC) & 0x0ff) << 12));
+
+  ///
+  /// Get APIC ID from Identification Register (Index 0)
+  ///
+  *IoapicIndex  = 0;
+  Data32        = (*IoapicData & 0x0F000000) >> 24;
+
+  return (UINT8) Data32;
+}
+
+VOID
+UpdateDRHD2 (
+  IN OUT VOID *DrhdEnginePtr
+  )
+/**
+    Update the second DRHD structure
+
+    @param[in, out] DrhdEnginePtr       - A pointer to DRHD structure
+**/
+{
+  UINT16                        Length;
+  UINTN                         DeviceScopeNum;
+  UINTN                         ValidDeviceScopeNum;
+  UINT16                        Data16;
+  UINT16                        HpetReg;
+  UINT16                        Index;
+  UINT8                         Bus;
+  UINT8                         Path[2] = { 0, 0 };
+  BOOLEAN                       NeedRemove;
+  EFI_ACPI_DRHD_ENGINE2_STRUCT  *DrhdEngine;
+
+  ///
+  /// Convert DrhdEnginePtr to EFI_ACPI_DRHD_ENGINE2_STRUCT Pointer
+  ///
+  DrhdEngine      = (EFI_ACPI_DRHD_ENGINE2_STRUCT *) DrhdEnginePtr;
+
+  Length          = DrhdEngine->Length;
+  DeviceScopeNum  = (DrhdEngine->Length - EFI_ACPI_DRHD_ENGINE_HEADER_LENGTH) / sizeof (EFI_ACPI_DEV_SCOPE_STRUCTURE);
+  Data16          = 0;
+  Bus             = 0;
+  HpetReg         = R_PCH_LPC_HPET0;
+  ValidDeviceScopeNum = 0;
+
+  for (Index = 0; Index < DeviceScopeNum; Index++) {
+    NeedRemove = FALSE;
+    /**
+      For HPET and APIC, update device scope if Interrupt remapping is supported. remove device scope
+      if interrupt remapping is not supported.
+      - Index = 0 - IOAPIC
+      - Index = 1 - HPET
+      For Serial IO devices, they do not appear in PCI space, use platform policy to determine existence, also remove if PCH not LP
+      - Index = 2 - I2C0
+      - Index = 3 - I2C1
+      - Index = 4 - SPI0
+      - Index = 5 - SPI1
+      - Index = 6 - UART0
+      - Index = 7 - UART1
+      - Index = 8 - SDIO
+    **/
+    if (mInterruptRemappingSupport) {
+      if (Index == 0) {
+        ///
+        /// Update source id for IoApic's device scope entry
+        ///
+        Data16  = PchLpcPciCfg16 (R_PCH_LPC_IOXAPIC);
+        Bus     = (UINT8) (Data16 >> 8);
+        if (Bus != 0x00) {
+          Path[0] = (UINT8) ((Data16 & 0xff) >> 3);
+          Path[1] = (UINT8) (Data16 & 0x7);
+        } else {
+          //
+          // BUGBUG: Here we just hardcode, because in this version, R_PCH_LPC_IOXAPIC is initialized AFTER Vtd run.  We can NOT get proper setting from PCH
+          // We can NOT get proper setting from PCH
+          /// @todo check if code still needed
+          //
+          DEBUG ((EFI_D_WARN, "BUGBUG: UpdateApicHpet use hardcode value - To be fixed!\n"));
+          Bus     = 0xF0;
+          Path[0] = 0x1F;
+          Path[1] = 0x0;
+        }
+        DrhdEngine->DeviceScope[Index].StartBusNumber = Bus;
+        //
+        // Update APIC ID
+        //
+        DrhdEngine->DeviceScope[Index].EnumId = GetIoApicID ();
+      }
+      if (Index == 1) {
+        ///
+        /// Update source id for HPET's device scope entry
+        ///
+        Data16  = PchLpcPciCfg16 (HpetReg);
+        Bus     = (UINT8) (Data16 >> 8);
+        Path[0] = (UINT8) ((Data16 & 0xFF) >> 3);
+        Path[1] = (UINT8) (Data16 & 0x7);
+        DrhdEngine->DeviceScope[Index].StartBusNumber = Bus;
+      }
+    } else {
+      if ((Index == 0) || (Index == 1)) {
+        NeedRemove = TRUE;
+      }
+    }
+    /*
+    Pch removed device from PCI space and it is visible by ACPI only, we use platform policy to check
+    if device is present. If Pch is 2 chip, remove all serialio devices.
+    */
+#ifdef SERIAL_IO_FLAG
+    if (mPchSeries == PchLp){
+      if (Index == 2){
+        if (mDxePlatformPchPolicy->DeviceEnabling->SerialIoI2c0 == 0){
+          NeedRemove = TRUE;
+        }
+      }
+      if (Index == 3){
+        if (mDxePlatformPchPolicy->DeviceEnabling->SerialIoI2c1 == 0){
+          NeedRemove = TRUE;
+        }
+      }
+      if (Index == 4){
+        if (mDxePlatformPchPolicy->DeviceEnabling->SerialIoSpi0 == 0){
+          NeedRemove = TRUE;
+        }
+      }
+      if (Index == 5){
+        if (mDxePlatformPchPolicy->DeviceEnabling->SerialIoSpi1 == 0){
+          NeedRemove = TRUE;
+        }
+      }
+      if (Index == 6){
+        if (mDxePlatformPchPolicy->DeviceEnabling->SerialIoUart0 == 0){
+          NeedRemove = TRUE;
+        }
+      }
+      if (Index == 7){
+        if (mDxePlatformPchPolicy->DeviceEnabling->SerialIoUart1 == 0){
+          NeedRemove = TRUE;
+        }
+      }
+      if (Index == 8){
+        if (mDxePlatformPchPolicy->DeviceEnabling->SerialIoSdio == 0){
+          NeedRemove = TRUE;
+        }
+      }
+    } else {
+#endif
+      if ((Index >= 2) && (Index <= 8)){
+        NeedRemove = TRUE;
+      }
+#ifdef SERIAL_IO_FLAG
+    }
+#endif
+    CopyMem (
+      &DrhdEngine->DeviceScope[ValidDeviceScopeNum],
+      &DrhdEngine->DeviceScope[Index],
+      sizeof (EFI_ACPI_DEV_SCOPE_STRUCTURE)
+      );
+    if (NeedRemove) {
+      Length -= sizeof (EFI_ACPI_DEV_SCOPE_STRUCTURE);
+    } else {
+      ValidDeviceScopeNum++;
+    }
+  }
+  ///
+  /// If no devicescope is left, we set the structure length as 0x00
+  ///
+  if ((Length > EFI_ACPI_DRHD_ENGINE_HEADER_LENGTH) || (DrhdEngine->Flags == 0x01)) {
+    DrhdEngine->Length = Length;
+  } else {
+    DrhdEngine->Length = 0;
+  }
+}
+
+VOID
+UpdateRMRR (
+  IN OUT VOID *RmrrPtr
+  )
+/**
+    Update the RMRR structure
+
+    @param[in, out] RmrrPtr             - A pointer to RMRR structure
+**/
+{
+  UINT16                  Length;
+  UINT16                  DisableBit;
+  UINTN                   DeviceScopeNum;
+  UINTN                   ValidDeviceScopeNum;
+  UINTN                   Index;
+  BOOLEAN                 NeedRemove;
+  EFI_ACPI_RMRR_USB_STRUC *Rmrr;
+
+  ///
+  /// To make sure all devicescope can be checked,
+  /// we convert the RmrrPtr to EFI_ACPI_RMRR_USB_STRUC pointer
+  ///
+  Rmrr                = (EFI_ACPI_RMRR_USB_STRUC *) RmrrPtr;
+  Length              = Rmrr->Length;
+  ValidDeviceScopeNum = 0;
+  DeviceScopeNum      = (Rmrr->Length - EFI_ACPI_RMRR_HEADER_LENGTH) / sizeof (EFI_ACPI_DEV_SCOPE_STRUCTURE);
+  for (Index = 0; Index < DeviceScopeNum; Index++) {
+    ///
+    /// here we assume Device will exist on PCH if Device Number is greater than 0x0F
+    ///
+    DisableBit = GetFunDisableBit (
+                  Rmrr->DeviceScope[Index].PciPath[0],
+                  Rmrr->DeviceScope[Index].PciPath[1]
+                  );
+    NeedRemove = FALSE;
+    if ((DisableBit == 0xFF) ||
+        ((DisableBit == 0x80) &&
+        (MmPci32 (0, 0, Rmrr->DeviceScope[Index].PciPath[0], Rmrr->DeviceScope[Index].PciPath[1], 0x00) == 0xFFFFFFFF))
+        ){
+      NeedRemove = TRUE;
+    }
+    CopyMem (
+      &Rmrr->DeviceScope[ValidDeviceScopeNum],
+      &Rmrr->DeviceScope[Index],
+      sizeof (EFI_ACPI_DEV_SCOPE_STRUCTURE)
+      );
+    if (NeedRemove) {
+      Length -= sizeof (EFI_ACPI_DEV_SCOPE_STRUCTURE);
+    } else {
+      ValidDeviceScopeNum++;
+    }
+  }
+  ///
+  /// If No deviceScope is left, set length as 0x00
+  ///
+  if (Length > EFI_ACPI_RMRR_HEADER_LENGTH) {
+    Rmrr->Length = Length;
+  } else {
+    Rmrr->Length = 0;
+  }
+}
+
+VOID
+DmarTableUpdate (
+  IN OUT   EFI_ACPI_DESCRIPTION_HEADER       *TableHeader,
+  IN OUT   EFI_ACPI_TABLE_VERSION            *Version
+  )
+/**
+  Update the DMAR table
+
+  @param[in, out] TableHeader         - The table to be set
+  @param[in, out] Version             - Version to publish
+**/
+{
+  EFI_ACPI_DMAR_TABLE *DmarTable;
+  EFI_ACPI_DMAR_TABLE TempDmarTable;
+  UINTN               Offset;
+  UINTN               StructureLen;
+  UINT16              IgdMode;
+  UINT16              GttMode;
+  UINT32              IgdMemSize;
+  UINT32              GttMemSize;
+
+  IgdMemSize  = 0;
+  GttMemSize  = 0;
+  DmarTable = (EFI_ACPI_DMAR_TABLE *) TableHeader;
+
+  if (mInterruptRemappingSupport) {
+    DmarTable->Flags |= BIT0; ///< Set INTR_REMAP bit (BIT 0) if interrupt remapping is supported
+  }
+  ///
+  /// Find IGD memsize
+  ///
+  IgdMode = (McD0PciCfg16 (R_SA_GGC) & B_SA_GGC_GMS_MASK) >> 3;
+  if (IgdMode <= V_SA_GGC_GMS_512MB) {
+    IgdMemSize = IgdMode * 32 * (1024) * (1024);
+  } else {
+    IgdMemSize = 0;
+  }
+  ///
+  /// Find GTT mem size
+  ///
+  GttMode = (McD0PciCfg16 (R_SA_GGC) & B_SA_GGC_GGMS_MASK) >> 8;
+  if (GttMode <= V_SA_GGC_GGMS_2MB) {
+    GttMemSize = GttMode * (1024) * (1024);
+  } else {
+    GttMemSize = 0;
+  }
+
+  DmarTable->RmrrIgd.RmrBaseAddress   = (McD0PciCfg32 (R_SA_TOLUD) &~(0x01)) - IgdMemSize - GttMemSize;
+  DmarTable->RmrrIgd.RmrLimitAddress  = DmarTable->RmrrIgd.RmrBaseAddress + IgdMemSize + GttMemSize - 1;
+  DEBUG ((EFI_D_INFO, "RMRR Base  address IGD %016lX\n", DmarTable->RmrrIgd.RmrBaseAddress));
+  DEBUG ((EFI_D_INFO, "RMRR Limit address IGD %016lX\n", DmarTable->RmrrIgd.RmrLimitAddress));
+
+  DmarTable->RmrrUsb.RmrBaseAddress   = mDxePlatformSaPolicy->Vtd->RmrrUsbBaseAddress[0];
+  DmarTable->RmrrUsb.RmrLimitAddress  = mDxePlatformSaPolicy->Vtd->RmrrUsbBaseAddress[1];
+
+  ///
+  /// Convert to 4KB alignment.
+  ///
+  DmarTable->RmrrUsb.RmrBaseAddress &= ~0xFFF;
+  DmarTable->RmrrUsb.RmrLimitAddress &= ~0xFFF;
+  DmarTable->RmrrUsb.RmrLimitAddress += 0x1000 - 1;
+
+  DEBUG ((EFI_D_INFO, "RMRR Base  address USB %016lX\n", DmarTable->RmrrUsb.RmrBaseAddress));
+  DEBUG ((EFI_D_INFO, "RMRR Limit address USB %016lX\n", DmarTable->RmrrUsb.RmrLimitAddress));
+
+  ///
+  /// @todo check if this check is still needed.
+  ///
+  if (DmarTable->RmrrUsb.RmrBaseAddress == 0) {
+    DEBUG ((EFI_D_WARN, "BUGBUG:  RmrrUsb.RmrBaseAddress is 0 - To be fixed\n"));
+  }
+  ///
+  /// Update DRHD structures of DmarTable
+  ///
+  DmarTable->DrhdEngine1.RegisterBaseAddress = (McMmio32 (R_SA_MCHBAR_VTD1_OFFSET) &~1);
+  DmarTable->DrhdEngine2.RegisterBaseAddress = (McMmio32 (R_SA_MCHBAR_VTD2_OFFSET) &~1);
+
+  DEBUG ((EFI_D_INFO, "VTD base address1 %x\n", DmarTable->DrhdEngine1.RegisterBaseAddress));
+  DEBUG ((EFI_D_INFO, "VTD base address2 %x\n", DmarTable->DrhdEngine2.RegisterBaseAddress));
+  ///
+  /// copy DmarTable to TempDmarTable to be processed
+  ///
+  CopyMem (&TempDmarTable, DmarTable, sizeof (EFI_ACPI_DMAR_TABLE));
+
+  ///
+  /// Update DRHD structures of temp DMAR table
+  ///
+  UpdateDRHD (&TempDmarTable.DrhdEngine1);
+  UpdateDRHD2 (&TempDmarTable.DrhdEngine2);
+
+  ///
+  /// Update RMRR structures of temp DMAR table
+  ///
+  UpdateRMRR ((VOID *) &TempDmarTable.RmrrUsb);
+  UpdateRMRR ((VOID *) &TempDmarTable.RmrrIgd);
+
+  ///
+  /// Remove unused device scope or entire DRHD structures
+  ///
+  Offset = (UINTN) (&TempDmarTable.DrhdEngine1);
+  if (TempDmarTable.DrhdEngine1.Length != 0) {
+    Offset += TempDmarTable.DrhdEngine1.Length;
+  }
+  if (TempDmarTable.DrhdEngine2.Length != 0) {
+    StructureLen = TempDmarTable.DrhdEngine2.Length;
+    CopyMem ((VOID *) Offset, (VOID *) &TempDmarTable.DrhdEngine2, TempDmarTable.DrhdEngine2.Length);
+    Offset += StructureLen;
+  }
+  ///
+  /// Remove unused device scope or entire RMRR structures
+  ///
+  if (TempDmarTable.RmrrUsb.Length != 0) {
+    StructureLen = TempDmarTable.RmrrUsb.Length;
+    CopyMem ((VOID *) Offset, (VOID *) &TempDmarTable.RmrrUsb, TempDmarTable.RmrrUsb.Length);
+    Offset += StructureLen;
+  }
+  if (TempDmarTable.RmrrIgd.Length != 0) {
+    StructureLen = TempDmarTable.RmrrIgd.Length;
+    CopyMem ((VOID *) Offset, (VOID *) &TempDmarTable.RmrrIgd, TempDmarTable.RmrrIgd.Length);
+    Offset += StructureLen;
+  }
+#ifdef SERIAL_IO_FLAG
+  ///
+  /// Include necessary ANDD structures. If not PchLp, remove all ANDD.
+  ///
+  if (mPchSeries == PchLp){
+    if (mDxePlatformPchPolicy->DeviceEnabling->SerialIoI2c0 != 0) {
+      StructureLen = TempDmarTable.AnddI2C0.Length;
+      CopyMem ((VOID *) Offset, (VOID *) &TempDmarTable.AnddI2C0, TempDmarTable.AnddI2C0.Length);
+      Offset += StructureLen;
+    }
+    if (mDxePlatformPchPolicy->DeviceEnabling->SerialIoI2c1 != 0) {
+      StructureLen = TempDmarTable.AnddI2C1.Length;
+      CopyMem ((VOID *) Offset, (VOID *) &TempDmarTable.AnddI2C1, TempDmarTable.AnddI2C1.Length);
+      Offset += StructureLen;
+    }
+    if (mDxePlatformPchPolicy->DeviceEnabling->SerialIoSpi0 != 0) {
+      StructureLen = TempDmarTable.AnddSpi0.Length;
+      CopyMem ((VOID *) Offset, (VOID *) &TempDmarTable.AnddSpi0, TempDmarTable.AnddSpi0.Length);
+      Offset += StructureLen;
+    }
+    if (mDxePlatformPchPolicy->DeviceEnabling->SerialIoSpi1 != 0) {
+      StructureLen = TempDmarTable.AnddSpi1.Length;
+      CopyMem ((VOID *) Offset, (VOID *) &TempDmarTable.AnddSpi1, TempDmarTable.AnddSpi1.Length);
+      Offset += StructureLen;
+    }
+    if (mDxePlatformPchPolicy->DeviceEnabling->SerialIoUart0 != 0) {
+      StructureLen = TempDmarTable.AnddUa00.Length;
+      CopyMem ((VOID *) Offset, (VOID *) &TempDmarTable.AnddUa00, TempDmarTable.AnddUa00.Length);
+      Offset += StructureLen;
+    }
+    if (mDxePlatformPchPolicy->DeviceEnabling->SerialIoUart1 != 0) {
+      StructureLen = TempDmarTable.AnddUa01.Length;
+      CopyMem ((VOID *) Offset, (VOID *) &TempDmarTable.AnddUa01, TempDmarTable.AnddUa01.Length);
+      Offset += StructureLen;
+    }
+    if (mDxePlatformPchPolicy->DeviceEnabling->SerialIoSdio != 0) {
+      StructureLen = TempDmarTable.AnddSdhc.Length;
+      CopyMem ((VOID *) Offset, (VOID *) &TempDmarTable.AnddSdhc, TempDmarTable.AnddSdhc.Length);
+      Offset += StructureLen;
+    }
+  }
+#endif
+  Offset = Offset - (UINTN) &TempDmarTable;
+  TempDmarTable.Header.Checksum = (UINT8) (TempDmarTable.Header.Checksum + TempDmarTable.Header.Length - Offset);
+  TempDmarTable.Header.Length = (UINT32) Offset;
+  ///
+  /// Replace DMAR table with rebuilt table TempDmarTable
+  ///
+  CopyMem ((VOID *) DmarTable, (VOID *) &TempDmarTable, TempDmarTable.Header.Length);
+}
+
+EFI_STATUS
+WaForVc0RemappingEngine (
+  UINT64                      MchBar
+  )
+/**
+  Workaround for VC0 remapping engine
+
+  @param[in] MchBar             - MCHBAR address
+
+  @retval EFI_SUCCESS           - successed.
+**/
+{
+  UINT16              DeviceId;
+  UINT32              Vc0RemapEngineBase;
+  UINT32              Data32Or;
+  UINT32              Data32And;
+
+  DeviceId  = PchLpcPciCfg16(R_PCH_LPC_DEVICE_ID);
+  Vc0RemapEngineBase = Mmio32(MchBar, R_SA_MCHBAR_VTD2_OFFSET) & 0xFFFFFFFE;
+
+  ///
+  /// Disable VTD SuperPage policy when iGfx is enabled
+  ///
+  if (McD2PciCfg16(R_SA_IGD_VID) != 0xFFFF) {
+    Data32And = (UINT32)~(BIT25);
+    Data32Or  = 0;
+    Mmio32And(Vc0RemapEngineBase, 0xFF0, Data32And);
+    SCRIPT_MEM_READ_WRITE
+      (
+        EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+        EfiBootScriptWidthUint32,
+        (UINTN) (Vc0RemapEngineBase + 0xFF0),
+        &Data32Or,  ///< Data to be ORed
+        &Data32And  ///< Data to be ANDed
+      );
+  }
+
+  return EFI_SUCCESS;
+}
+
+VOID
+UpdateDmarExitPmAuth (
+  VOID
+  )
+/**
+  ExitPmAuth routine for update DMAR
+**/
+{
+  EFI_STATUS                      Status;
+  EFI_HANDLE                      *HandleBuffer;
+  UINTN                           NumberOfHandles;
+  EFI_FV_FILETYPE                 FileType;
+  UINT32                          FvStatus;
+  EFI_FV_FILE_ATTRIBUTES          Attributes;
+  UINTN                           Size;
+  UINTN                           i;
+  INTN                            Instance;
+  EFI_ACPI_TABLE_VERSION          Version;
+  EFI_ACPI_COMMON_HEADER          *CurrentTable;
+  UINTN                           AcpiTableHandle;
+  EFI_FIRMWARE_VOLUME_PROTOCOL    *FwVol;
+  EFI_ACPI_TABLE_PROTOCOL         *AcpiTable;
+  EFI_ACPI_DESCRIPTION_HEADER     *VtdAcpiTable;
+  STATIC BOOLEAN                  Triggered = FALSE;
+
+  if (Triggered) {
+    return;
+  }
+
+  Triggered     = TRUE;
+
+  FwVol         = NULL;
+  AcpiTable     = NULL;
+  VtdAcpiTable  = NULL;
+
+  ///
+  /// Locate PCH platform policy protocol and PCH series to support feature enabling/disabling
+  ///
+  Status = gBS->LocateProtocol (
+                  &gDxePchPlatformPolicyProtocolGuid,
+                  NULL,
+                  (VOID**) &mDxePlatformPchPolicy
+                  );
+  ASSERT_EFI_ERROR (Status);
+  mPchSeries  = GetPchSeries();
+
+  if ((!mDxePlatformSaPolicy->Vtd->VtdEnable) || (McD0PciCfg32 (R_SA_MC_CAPID0_A_OFFSET) & BIT23)) {
+      DEBUG ((EFI_D_INFO, "Vtd Disabled, skip DMAR Table install\n"));
+
+      return;
+  }
+
+  ///
+  /// Locate ACPI support protocol
+  ///
+  Status = gBS->LocateProtocol (&gEfiAcpiTableProtocolGuid, NULL, (VOID **) &AcpiTable);
+
+  ///
+  /// Locate protocol.
+  /// There is little chance we can't find an FV protocol
+  ///
+  Status = gBS->LocateHandleBuffer (
+                  ByProtocol,
+                  &gEfiFirmwareVolumeProtocolGuid,
+                  NULL,
+                  &NumberOfHandles,
+                  &HandleBuffer
+                  );
+  ASSERT_EFI_ERROR (Status);
+
+  ///
+  /// Looking for FV with ACPI storage file
+  ///
+  for (i = 0; i < NumberOfHandles; i++) {
+    ///
+    /// Get the protocol on this handle
+    /// This should not fail because of LocateHandleBuffer
+    ///
+    Status = gBS->HandleProtocol (
+                    HandleBuffer[i],
+                    &gEfiFirmwareVolumeProtocolGuid,
+                    (VOID **) &FwVol
+                    );
+    ASSERT_EFI_ERROR (Status);
+
+    ///
+    /// See if it has the ACPI storage file
+    ///
+    Size      = 0;
+    FvStatus  = 0;
+    Status = FwVol->ReadFile (
+                      FwVol,
+                      &gSaAcpiTableStorageGuid,
+                      NULL,
+                      &Size,
+                      &FileType,
+                      &Attributes,
+                      &FvStatus
+                      );
+
+    ///
+    /// If we found it, then we are done
+    ///
+    if (Status == EFI_SUCCESS) {
+      break;
+    }
+  }
+  ///
+  /// Our exit status is determined by the success of the previous operations
+  /// If the protocol was found, Instance already points to it.
+  ///
+  ///
+  /// Free any allocated buffers
+  ///
+  FreePool (HandleBuffer);
+
+  ///
+  /// Sanity check that we found our data file
+  ///
+  ASSERT (FwVol);
+  if (FwVol == NULL) {
+    return ;
+  }
+  ///
+  /// By default, a table belongs in all ACPI table versions published.
+  ///
+  Version = EFI_ACPI_TABLE_VERSION_1_0B | EFI_ACPI_TABLE_VERSION_2_0 | EFI_ACPI_TABLE_VERSION_3_0;
+
+  ///
+  /// Read tables from the storage file.
+  ///
+  Instance      = 0;
+  CurrentTable  = NULL;
+
+  while (Status == EFI_SUCCESS) {
+    Status = FwVol->ReadSection (
+                      FwVol,
+                      &gSaAcpiTableStorageGuid,
+                      EFI_SECTION_RAW,
+                      Instance,
+                      (VOID **) &CurrentTable,
+                      &Size,
+                      &FvStatus
+                      );
+
+    if (!EFI_ERROR (Status)) {
+      ///
+      /// Check the Signature ID to modify the table
+      ///
+      switch (((EFI_ACPI_DESCRIPTION_HEADER *) CurrentTable)->Signature) {
+
+      case EFI_ACPI_VTD_DMAR_TABLE_SIGNATURE:
+        VtdAcpiTable = (EFI_ACPI_DESCRIPTION_HEADER *) CurrentTable;
+        DmarTableUpdate (VtdAcpiTable, &Version);
+        break;
+
+      default:
+        break;
+      }
+      ///
+      /// Increment the instance
+      ///
+      Instance++;
+      CurrentTable = NULL;
+    }
+  }
+  ///
+  /// Update the VTD table in the ACPI tables.
+  ///
+  AcpiTableHandle = 0;
+  if (VtdAcpiTable != NULL) {
+    Status = AcpiTable->InstallAcpiTable (
+                          AcpiTable,
+                          VtdAcpiTable,
+                          VtdAcpiTable->Length,
+                          &AcpiTableHandle
+                          );
+  }
+}
+
+EFI_STATUS
+VtdInit (
+  IN  DXE_PLATFORM_SA_POLICY_PROTOCOL    *DxePlatformSaPolicy
+  )
+/**
+@brief
+  Locate the VT-d ACPI tables data file and read ACPI SSDT tables.
+  Publish the appropriate SSDT based on current configuration and capabilities.
+
+  @param[in] DxePlatformSaPolicy  -  SA DxePlatformPolicy protocol
+
+  @retval EFI_SUCCESS     - Vtd initialization complete
+  @exception EFI_UNSUPPORTED - Vtd is not enabled by policy
+**/
+{
+  EFI_STATUS   Status;
+  UINTN        i;
+  UINT64       MchBar;
+  UINT32       Data32Or;
+  UINT32       Data32And;
+  UINT32       VtdBase;
+  UINT32       VtBarReg [SA_VTD_ENGINE_NUMBER];
+  CPU_FAMILY   CpuFamilyId;
+  CPU_STEPPING CpuStepping;
+
+  mInterruptRemappingSupport  = FALSE;
+  mPchRootComplexBar          = MmPci32 (0, 0, 31, 0, 0xF0) &~BIT0;
+  MchBar                      = McD0PciCfg64 (R_SA_MCHBAR) &~BIT0;
+
+  VtBarReg[0]                 = R_SA_MCHBAR_VTD1_OFFSET;
+  VtBarReg[1]                 = R_SA_MCHBAR_VTD2_OFFSET;
+  mDxePlatformSaPolicy        = DxePlatformSaPolicy;
+
+  ///
+  /// Check SA supports VTD and VTD is enabled in setup menu
+  ///
+  if ((!mDxePlatformSaPolicy->Vtd->VtdEnable) || (McD0PciCfg32 (R_SA_MC_CAPID0_A_OFFSET) & BIT23)) {
+    DEBUG ((EFI_D_WARN, "VTd disabled or no capability!\n"));
+    return EFI_UNSUPPORTED;
+  }
+  DEBUG ((EFI_D_INFO, "VTd enabled\n"));
+
+  ///
+  /// 14.1 Program Remap Engine Base Address
+  /// Configure VTD1 BAR
+  ///
+  i = 0;
+
+  ///
+  /// Skip GFXVTBAR if IGD is disabled
+  ///
+  if (McD2PciCfg16 (R_SA_IGD_VID) != 0xFFFF) {
+    Data32Or = mDxePlatformSaPolicy->Vtd->BaseAddress[i];
+    Data32Or |= 0x1;
+    Mmio32 (MchBar, R_SA_MCHBAR_VTD1_OFFSET) = Data32Or;
+    SCRIPT_MEM_WRITE (
+      EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+      EfiBootScriptWidthUint32,
+      (UINTN) (MchBar + R_SA_MCHBAR_VTD1_OFFSET),
+      1,
+      &Data32Or
+      );
+    i++;
+  }
+
+  ///
+  /// Configure VTD2 BAR
+  ///
+  Data32Or = mDxePlatformSaPolicy->Vtd->BaseAddress[i];
+  Data32Or |= 0x1;
+  Mmio32 (MchBar, R_SA_MCHBAR_VTD2_OFFSET) = Data32Or;
+  SCRIPT_MEM_WRITE (
+    EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+    EfiBootScriptWidthUint32,
+    (UINTN) (MchBar + R_SA_MCHBAR_VTD2_OFFSET),
+    1,
+    &Data32Or
+    );
+
+  ///
+  /// Workaround for VC0 remapping engine
+  ///
+  Status = WaForVc0RemappingEngine (MchBar);
+  ASSERT_EFI_ERROR (Status);
+
+  for (i = 0; i < SA_VTD_ENGINE_NUMBER; i++) {
+    VtdBase = Mmio32 (MchBar, VtBarReg[i]) & 0xfffffffe;
+
+    ///
+    /// skip if the VT bar is 0
+    ///
+    if (VtdBase == 0) {
+      continue;
+    }
+
+    CpuFamilyId = GetCpuFamily();
+    CpuStepping = GetCpuStepping();
+
+    if ((CpuFamilyId == EnumCpuHsw) || (CpuFamilyId == EnumCpuHswUlt) || (CpuFamilyId == EnumCpuCrw)
+        ) {
+      Data32And = (UINT32) ~(BIT15+BIT16+BIT17+BIT18+BIT19); ///< mask out 19:15
+      Data32Or  = BIT15;
+      if (i == 1) {
+        Mmio32AndThenOr (VtdBase, 0xF04, Data32And, Data32Or);
+        SCRIPT_MEM_READ_WRITE (
+          EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+          EfiBootScriptWidthUint32,
+          (UINTN) (VtdBase + 0xF04),
+          &Data32Or,  ///< Data to be ORed
+          &Data32And  ///< Data to be ANDed
+        );
+      }
+    }
+    ///
+    /// 14.2 Set the remap engine policy bits
+    ///
+    Data32And = 0x0; ///< mask out all bits
+    Data32Or  = 0;
+
+
+    if ((CpuFamilyId == EnumCpuHsw) || (CpuFamilyId == EnumCpuHswUlt) || (CpuFamilyId == EnumCpuCrw)) {
+      if (i == 0) {
+        Data32Or |= 0x02100000;
+      }
+      if (i == 1) {
+        if (McD2PciCfg16 (R_SA_IGD_VID) != 0xFFFF) {
+          Data32Or |= 0x000A5003;
+        } else {
+          Data32Or |= 0x020A5003;
+        }
+      }
+    }
+
+    ///
+    /// Set lock bit
+    ///
+    Data32Or |= BIT31;
+
+
+    Mmio32AndThenOr (VtdBase, 0xFF0, Data32And, Data32Or);
+    SCRIPT_MEM_READ_WRITE (
+      EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+      EfiBootScriptWidthUint32,
+      (UINTN) (VtdBase + 0xFF0),
+      &Data32Or,  ///< Data to be ORed
+      &Data32And  ///< Data to be ANDed
+      );
+
+    ///
+    /// Check IR status
+    ///
+    if ((Mmio32 (VtdBase, VTD_ECAP_REG) & IR) && !(mInterruptRemappingSupport)) {
+      mInterruptRemappingSupport = TRUE;
+    }
+  }
+
+  return EFI_SUCCESS;
+}
diff --git a/ReferenceCode/Chipset/SystemAgent/SaInit/Dxe/VTd.h b/ReferenceCode/Chipset/SystemAgent/SaInit/Dxe/VTd.h
new file mode 100644
index 0000000..2d9daa4
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/SaInit/Dxe/VTd.h
@@ -0,0 +1,70 @@
+/** @file
+  This code provides a initialization of intel VT-d (Virtualization Technology for Directed I/O).
+
+@copyright
+  Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement
+**/
+#ifndef _VT_D_H_
+#define _VT_D_H_
+
+///
+/// Include files
+///
+#include "DmaRemappingTable.h"
+#include "SaAccess.h"
+#include "PchAccess.h"
+
+#include EFI_PROTOCOL_DEPENDENCY (AcpiTable)
+#include EFI_PROTOCOL_DEFINITION (SaPlatformPolicy)
+#include EFI_PROTOCOL_DEFINITION (PchPlatformPolicy)
+
+///
+/// SA ACPI table data storage file
+///
+#include EFI_GUID_DEFINITION (SaAcpiTableStorage)
+
+#define VTD_ECAP_REG  0x10
+#define IR            BIT3
+
+#define VTD_GCMD_REG  0x18
+#define QIE           BIT26
+#define IRE           BIT25
+
+EFI_STATUS
+VtdInit (
+  IN  DXE_PLATFORM_SA_POLICY_PROTOCOL    *DxePlatformSaPolicy
+  )
+/**
+  Locate the VT-d ACPI tables data file and read ACPI SSDT tables.
+  Publish the appropriate SSDT based on current configuration and capabilities.
+
+  @param[in] DxePlatformSaPolicy            SA DxePlatformPolicy protocol
+
+  @retval EFI_SUCCESS - Vtd initialization complete
+  @retval Other       - No Vtd function initiated
+**/
+;
+
+VOID
+UpdateDmarExitPmAuth (
+  VOID
+  )
+/**
+  ExitPmAuth routine for update DMAR
+**/
+;
+#endif
diff --git a/ReferenceCode/Chipset/SystemAgent/SaInit/Dxe/graphicsinit.c b/ReferenceCode/Chipset/SystemAgent/SaInit/Dxe/graphicsinit.c
new file mode 100644
index 0000000..2b1af13
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/SaInit/Dxe/graphicsinit.c
@@ -0,0 +1,1094 @@
+/** @file
+  DXE driver for Initializing SystemAgent Graphics initialization.
+
+@copyright
+  Copyright (c) 1999 - 2013 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement
+
+**/
+#include "GraphicsInit.h"
+#include EFI_PROTOCOL_DEFINITION (LegacyBios)
+#include EFI_PROTOCOL_DEFINITION (GopComponentName2)
+#ifndef AMI_OVERRIDE_FOR_INTEL_GOP_SUPPORT
+#if (defined(IntelSaGopDriver_SUPPORT) && (IntelSaGopDriver_SUPPORT == 1))
+#include "Include\Protocol\IntelSaGopDriver.h"
+#endif
+#endif
+UINT64                          GTTMMADR;
+UINTN                           MCHBAR_BASE;
+UINT8                           rP1GraphicsFreq;
+EFI_EVENT                       mExitPmAuthEvent;
+
+DXE_PLATFORM_SA_POLICY_PROTOCOL *mDxePlatformSaPolicy;
+GOP_COMPONENT_NAME2_PROTOCOL *GopComponentName2Protocol = NULL;
+
+///
+/// RC6 Settings
+///
+BOOT_SCRIPT_REGISTER_SETTING  gSaGtRC6Registers[] = {
+  0x0,
+  0xA090,
+  0xFFFFFFFF,
+  0x0,
+  ///
+  /// RC1e - RC6/6p - RC6pp Wake Rate Limits
+  ///
+  0x0,
+  0xA098,
+  0xFFFFFFFF,
+  0x3E80000,
+  0x0,
+  0xA09C,
+  0xFFFFFFFF,
+  0x00280000,
+  0x0,
+  0xA0A8,
+  0xFFFFFFFF,
+  0x1E848,
+  0x0,
+  0xA0AC,
+  0xFFFFFFFF,
+  0x19,
+  ///
+  /// Render/Video/Blitter Idle Max Count
+  ///
+  0x0,
+  0x2054,
+  0x0,
+  0xA,
+  0x0,
+  0x12054,
+  0x0,
+  0xA,
+  0x0,
+  0x22054,
+  0x0,
+  0xA,
+  0x0,
+  0x1a054,
+  0x0,
+  0xA,
+  ///
+  /// RC Sleep / RCx Thresholds
+  ///
+  0x0,
+  0xA0B0,
+  0xFFFFFFFF,
+  0,
+  0x0,
+  0xA0B4,
+  0xFFFFFFFF,
+  0x3E8,
+  0x0,
+  0xA0B8,
+  0xFFFFFFFF,
+  0xC350,
+  ///
+  /// RP Settings
+  ///
+  0x0,
+  0xA010,
+  0xFFFFFFFF,
+  0xF4240,
+  0x0,
+  0xA014,
+  0xFFFFFFFF,
+  0x12060000,
+  0x0,
+  0xA02C,
+  0xFFFFFFFF,
+  0x0000E808,
+  0x0,
+  0xA030,
+  0xFFFFFFFF,
+  0x0003BD08,
+  0x0,
+  0xA068,
+  0xFFFFFFFF,
+  0x000101D0,
+  0x0,
+  0xA06C,
+  0xFFFFFFFF,
+  0x00055730,
+  0x0,
+  0xA070,
+  0xFFFFFFFF,
+  0xA
+};
+
+///
+/// PM Lock Settings
+///
+BOOT_SCRIPT_REGISTER_SETTING  gSaGtPmLockBits[] = {
+  0x0,
+  0xA248,
+  0xFFFFFFFF,
+  BIT31,
+  0x0,
+  0xA004,
+  0xFFFFFFFF,
+  BIT4,
+  0x0,
+  0xA080,
+  0xFFFFFFFF,
+  BIT2,
+  0x0,
+  0xA180,
+  0xFFFFFFFF,
+  BIT31
+};
+
+EFI_STATUS
+PmInit (
+  IN EFI_HANDLE                      ImageHandle,
+  IN DXE_PLATFORM_SA_POLICY_PROTOCOL *DxePlatformSaPolicy
+  )
+/**
+  Initialize GT PowerManagement of SystemAgent.
+
+  @param[in] ImageHandle         - Handle for the image of this driver
+  @param[in] DxePlatformSaPolicy - SA DxePlatformPolicy protocol
+
+  @retval EFI_SUCCESS       - GT Power Management initialization complete
+**/
+{
+  UINT8             i;
+  UINT32            RegOffset;
+  UINT32            Data32;
+  UINT32            Data32And;
+  UINT32            Data32Or;
+  UINT32            Data32Mask;
+  UINT32            Result;
+  CPU_STEPPING      CpuSteppingId;
+  CPU_FAMILY        CpuFamilyId;
+
+  CpuFamilyId   = GetCpuFamily();
+  CpuSteppingId = GetCpuStepping();
+
+      ///
+      /// Multi Threaded Force Wake
+      ///
+      RegOffset                     = 0xA180;
+      Data32                        = BIT5;
+      Mmio32 (GTTMMADR, RegOffset)  = Data32;
+      SCRIPT_MEM_WRITE (
+        EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+        EfiBootScriptWidthUint32,
+        (UINTN) (GTTMMADR + RegOffset),
+        1,
+        &Data32
+        );
+
+      RegOffset                     = 0xA188;
+      Data32                        = 0x00010001;
+      Mmio32 (GTTMMADR, RegOffset)  = Data32;
+      SCRIPT_MEM_WRITE (
+        EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+        EfiBootScriptWidthUint32,
+        (UINTN) (GTTMMADR + RegOffset),
+        1,
+        &Data32
+        );
+      ///
+      /// Force Wake Acknowledge Bit
+      ///
+      RegOffset                     = 0x130044;
+      Data32Mask                    = BIT0;
+      Result                        = 1;
+      PollGtReady (GTTMMADR, RegOffset, Data32Mask, Result);
+      SCRIPT_MEM_POLL (
+        EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+        EfiBootScriptWidthUint32,
+        (UINTN) (GTTMMADR + RegOffset),
+        &Data32Mask,
+        &Result,
+        50,
+        200000
+        );
+
+    ///
+    /// Enable counters except Power Meter
+    ///
+    Data32And = 0xFFFFFFFF;
+    Data32Or  = 0x16;
+    Mmio32AndThenOr (GTTMMADR, 0xA248, Data32And, Data32Or);
+    SCRIPT_MEM_READ_WRITE (
+      EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+      EfiBootScriptWidthUint32,
+      (UINTN) (GTTMMADR + 0xA248),
+      &Data32Or,  /// Data to be ORed
+      &Data32And  /// Data to be ANDed
+      );
+
+      ///
+      /// GFXPAUSE Settings
+      ///
+      Data32 = 0x70020;
+
+
+      if (((CpuFamilyId == EnumCpuHsw)    && (CpuSteppingId < EnumHswC0)   ) ||
+          ((CpuFamilyId == EnumCpuHswUlt) && (CpuSteppingId < EnumHswUltC0)) ||
+          ((CpuFamilyId == EnumCpuCrw)    && (CpuSteppingId < EnumCrwC0)   )) {
+        Data32 |= 0xFFFF;
+      }
+
+      Mmio32 (GTTMMADR, 0xA000) = Data32;
+
+      SCRIPT_MEM_WRITE (
+        EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+        EfiBootScriptWidthUint32,
+        (UINTN) (GTTMMADR + 0xA000),
+        1,
+        &Data32
+        );
+
+
+    ///
+    /// ECO Settings
+    /// BIT28 = 1 GFX will be blocked from accessing memory (go=0) during CPD enter
+    /// BIT26 = 1 indicates to PCU that we are doing a fifo block due to RC6 and not CPD
+    /// BIT[24:22] = 100 RC6 Control
+    ///
+    RegOffset = 0xA180;
+    Data32And = 0xFFFFFFFF;
+    Data32Or  = BIT28 + BIT26;
+    if (DxePlatformSaPolicy->IgdConfig->RenderStandby) {
+      Data32And = (UINT32)~(BIT23 + BIT22);
+      Data32Or |= BIT24;
+    }
+
+    ///
+    /// Force CPD Non-IA. for steppings less than C0 for HSW/CRW
+    ///
+    if (((CpuFamilyId == EnumCpuHsw) && (CpuSteppingId < EnumHswC0)) ||
+        ((CpuFamilyId == EnumCpuCrw) && (CpuSteppingId < EnumCrwC0))) {
+        Data32Or |= BIT30;
+    }
+    ///
+    /// Force CPD Block memory bits. for stepping less than C0 for HSW/ULT/CRW
+    ///
+    if (((CpuFamilyId == EnumCpuHsw)    && (CpuSteppingId < EnumHswC0)   ) ||
+        ((CpuFamilyId == EnumCpuHswUlt) && (CpuSteppingId < EnumHswUltC0)) ||
+        ((CpuFamilyId == EnumCpuCrw)    && (CpuSteppingId < EnumCrwC0)   )) {
+        Data32And &= (UINT32)~(BIT28);
+        Data32Or  &= (UINT32)~(BIT28);
+    }
+
+    Mmio32AndThenOr (GTTMMADR, RegOffset, Data32And, Data32Or);
+    SCRIPT_MEM_READ_WRITE (
+      EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+      EfiBootScriptWidthUint32,
+      (UINTN) (GTTMMADR + RegOffset),
+      &Data32Or,  /// Data to be ORed
+      &Data32And  /// Data to be ANDed
+      );
+
+    ///
+    /// Clock Gating Settings
+    ///
+    Data32 = 0x3FD;
+    Mmio32 (GTTMMADR, 0x9424) = Data32;
+    SCRIPT_MEM_WRITE (
+      EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+      EfiBootScriptWidthUint32,
+      (UINTN) (GTTMMADR + 0x9424),
+      1,
+      &Data32
+      );
+
+    ///
+    /// Enable Unit Level Clock Gates
+    ///
+    Data32 = 0x80;
+    Mmio32 (GTTMMADR, 0x9400) = Data32;
+    SCRIPT_MEM_WRITE (
+      EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+      EfiBootScriptWidthUint32,
+      (UINTN) (GTTMMADR + 0x9400),
+      1,
+      &Data32
+      );
+
+    Data32 = 0x40401000;
+    Mmio32 (GTTMMADR, 0x9404) = Data32;
+    SCRIPT_MEM_WRITE (
+      EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+      EfiBootScriptWidthUint32,
+      (UINTN) (GTTMMADR + 0x9404),
+      1,
+      &Data32
+      );
+
+    Data32 = 0;
+    Mmio32 (GTTMMADR, 0x9408) = Data32;
+    SCRIPT_MEM_WRITE (
+      EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+      EfiBootScriptWidthUint32,
+      (UINTN) (GTTMMADR + 0x9408),
+      1,
+      &Data32
+      );
+
+    Data32 = 0x02000001;
+    Mmio32 (GTTMMADR, 0x940c) = Data32;
+    SCRIPT_MEM_WRITE (
+      EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+      EfiBootScriptWidthUint32,
+      (UINTN) (GTTMMADR + 0x940c),
+      1,
+      &Data32
+      );
+
+    Data32 = 0x08000000;
+    Mmio32 (GTTMMADR, 0xA008) = Data32;
+
+    SCRIPT_MEM_WRITE (
+      EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+      EfiBootScriptWidthUint32,
+      (UINTN) (GTTMMADR + 0xA008),
+      1,
+      &Data32
+      );
+    ///
+    /// RC6 Settings
+    ///
+    for (i = 0; i < sizeof (gSaGtRC6Registers) / sizeof (BOOT_SCRIPT_REGISTER_SETTING); ++i) {
+      RegOffset                     = gSaGtRC6Registers[i].Offset;
+      Data32And                     = gSaGtRC6Registers[i].AndMask;
+      Data32Or                      = gSaGtRC6Registers[i].OrMask;
+
+      Mmio32AndThenOr (GTTMMADR, RegOffset, Data32And, Data32Or);
+
+    SCRIPT_MEM_READ_WRITE (
+      EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+      EfiBootScriptWidthUint32,
+      (UINTN) (GTTMMADR + RegOffset),
+      &Data32Or,  /// Data to be ORed
+      &Data32And  /// Data to be ANDed
+      );
+    }
+
+    ///
+    /// RP Control
+    ///
+    Data32                    = 0xB92;
+    Mmio32 (GTTMMADR, 0xA024) = Data32;
+
+    SCRIPT_MEM_WRITE (
+      EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+      EfiBootScriptWidthUint32,
+      (UINTN) (GTTMMADR + 0xA024),
+      1,
+      &Data32
+      );
+
+    ///
+    /// HW RC6 Control Settings
+    ///
+    Data32 = 0;
+
+    if (DxePlatformSaPolicy->IgdConfig->RenderStandby) {
+      Data32 = 0x88040000;
+    }
+
+    Mmio32 (GTTMMADR, 0xA090) = Data32;
+
+    SCRIPT_MEM_WRITE (
+      EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+      EfiBootScriptWidthUint32,
+      (UINTN) (GTTMMADR + 0xA090),
+      1,
+      &Data32
+      );
+
+    ///
+    /// Video frequency request
+    ///
+    Data32  = 0x08000000;
+    Mmio32 (GTTMMADR, 0xA00C) = Data32;
+    SCRIPT_MEM_WRITE (
+      EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+      EfiBootScriptWidthUint32,
+      (UINTN) (GTTMMADR + 0xA00C),
+      1,
+      &Data32
+      );
+
+    ///
+    /// RC6 Settings
+    ///
+    ///
+    /// Wait for Mailbox ready
+    ///
+    Data32Mask  = BIT31;
+    Result      = 0;
+
+    PollGtReady (GTTMMADR, 0x138124, Data32Mask, Result);
+
+    SCRIPT_MEM_POLL (
+      EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+      EfiBootScriptWidthUint32,
+      (UINTN) (GTTMMADR + 0x138124),
+      &Data32Mask,
+      &Result,
+      50,
+      200000
+      );
+
+    ///
+    /// Mailbox Data  - RC6 VIDS
+    ///
+    Data32 = 0x0;
+    Mmio32 (GTTMMADR, 0x138128) = Data32;
+
+    SCRIPT_MEM_WRITE (
+      EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+      EfiBootScriptWidthUint32,
+      (UINTN) (GTTMMADR + 0x138128),
+      1,
+      &Data32
+      );
+
+    ///
+    /// Mailbox Command
+    ///
+    Data32                      = 0x80000004;
+    Mmio32 (GTTMMADR, 0x138124) = Data32;
+
+    SCRIPT_MEM_WRITE (
+      EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+      EfiBootScriptWidthUint32,
+      (UINTN) (GTTMMADR + 0x138124),
+      1,
+      &Data32
+      );
+
+    ///
+    /// Wait for Mailbox ready
+    ///
+    Data32Mask  = BIT31;
+    Result      = 0;
+
+    PollGtReady (GTTMMADR, 0x138124, Data32Mask, Result);
+
+    SCRIPT_MEM_POLL (
+      EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+      EfiBootScriptWidthUint32,
+      (UINTN) (GTTMMADR + 0x138124),
+      &Data32Mask,
+      &Result,
+      50,
+      200000
+      );
+
+    ///
+    /// Enable PM Interrupts
+    ///
+    Data32                      = 0x3000076;
+    Mmio32 (GTTMMADR, 0x4402C)  = Data32;
+
+    SCRIPT_MEM_WRITE (
+      EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+      EfiBootScriptWidthUint32,
+      (UINTN) (GTTMMADR + 0x4402C),
+      1,
+      &Data32
+      );
+
+    ///
+    /// RC6 setting
+    ///
+    if (mDxePlatformSaPolicy->IgdConfig->RenderStandby) {
+      ///
+      /// Software RC state - RC6
+      ///
+      Data32                    = 0x40000;
+      Mmio32 (GTTMMADR, 0xA094) = Data32;
+      SCRIPT_MEM_WRITE (
+        EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+        EfiBootScriptWidthUint8,
+        (UINTN) (GTTMMADR + 0xA094),
+        1,
+        &Data32
+        );
+    }
+
+      ///
+      /// PM Lock Settings
+      ///
+      for (i = 0; i < sizeof (gSaGtPmLockBits) / sizeof (BOOT_SCRIPT_REGISTER_SETTING); ++i) {
+        RegOffset = gSaGtPmLockBits[i].Offset;
+        Data32And = gSaGtPmLockBits[i].AndMask;
+        Data32Or  = gSaGtPmLockBits[i].OrMask;
+
+        Mmio32AndThenOr (GTTMMADR, RegOffset, Data32And, Data32Or);
+
+        SCRIPT_MEM_READ_WRITE (
+          EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+          EfiBootScriptWidthUint32,
+          (UINTN) (GTTMMADR + RegOffset),
+          &Data32Or,  /// Data to be ORed
+          &Data32And  /// Data to be ANDed
+          );
+      }
+  return EFI_SUCCESS;
+}
+
+EFI_STATUS
+PavpInit (
+  IN EFI_HANDLE                      ImageHandle,
+  IN DXE_PLATFORM_SA_POLICY_PROTOCOL *DxePlatformSaPolicy
+  )
+/**
+  Initialize PAVP feature of SystemAgent.
+
+  @param[in] ImageHandle         - Handle for the image of this driver
+  @param[in] DxePlatformSaPolicy - SA DxePlatformPolicy protocol
+
+  @retval EFI_SUCCESS - PAVP initialization complete
+**/
+{
+
+  UINT32  DwordData;
+  UINT32  PcmBase;
+  CPU_STEPPING      CpuSteppingId;
+  CPU_FAMILY        CpuFamilyId;
+
+  CpuFamilyId   = GetCpuFamily();
+  CpuSteppingId = GetCpuStepping();
+
+    McD0PciCfg32And (R_SA_PAVPC, ~(B_SA_PAVPC_HVYMODSEL_MASK | B_SA_PAVPC_PCMBASE_MASK | B_SA_PAVPC_PAVPE_MASK | B_SA_PAVPC_PCME_MASK));
+    McD0PciCfg16Or (R_SA_PAVPC, B_SA_PAVPC_PCME_MASK | B_SA_PAVPC_PAVPE_MASK);
+    PcmBase = ((UINT32) RShiftU64 ((McD0PciCfg32 (R_SA_TOLUD)), 20)) - PAVP_PCM_SIZE_1_MB;
+    McD0PciCfg32Or (R_SA_PAVPC, (UINT32) LShiftU64 (PcmBase, 20));
+
+    if ((CpuFamilyId == EnumCpuHsw) ||
+        (CpuFamilyId == EnumCpuHswUlt) ||
+        (CpuFamilyId == EnumCpuCrw)
+    ){
+      McD0PciCfg32Or (R_SA_PAVPC, (BIT4));
+    }
+
+  DwordData = McD0PciCfg32 (R_SA_PAVPC);
+  SCRIPT_MEM_WRITE (
+    EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+    EfiBootScriptWidthUint32,
+    (UINTN) (MmPciAddress (0,
+            0,
+            0,
+            0,
+            R_SA_PAVPC)),
+    1,
+    &DwordData
+    );
+
+  return EFI_SUCCESS;
+}
+
+EFI_STATUS
+PostPmInitExitPmAuth (
+  VOID
+  )
+/**
+    Do Post GT PM Init Steps after VBIOS Initialization.
+
+  @retval EFI_SUCCESS          Succeed.
+**/
+{
+  UINT32                    RegOffset;
+  UINT32                    Data32;
+  EFI_STATUS                Status;
+  UINT32                    Data32Mask;
+  UINT32                    Result;
+  UINT16                    Data16;
+  CHAR16                    *DriverVersion;
+  UINTN                     Index;
+  EFI_LEGACY_BIOS_PROTOCOL  *LegacyBios = NULL;
+
+  ///
+  /// Get the platform setup policy.
+  ///
+  Status = gBS->LocateProtocol (&gDxePlatformSaPolicyGuid, NULL, (VOID **) &mDxePlatformSaPolicy);
+  ASSERT_EFI_ERROR (Status);
+
+  ///
+  /// only 32bit read/write is legal for device 0:2:0
+  ///
+  GTTMMADR  = (UINT64) (McD2PciCfg32 (R_SA_IGD_GTTMMADR));
+  GTTMMADR  = LShiftU64 ((UINT64) McD2PciCfg32 (R_SA_IGD_GTTMMADR + 4), 32) | (GTTMMADR);
+
+  ///
+  /// Save the current GTMMADR value into S3 resume script before other S3 resume items in this function.
+  /// GTTMMADR may have been modified by the PCI enumeration code at this point,
+  /// but not saved into the S3 resume script yet.
+  ///
+  ///
+  /// only 32bit read/write is legal for device 0:2:0
+  ///
+  SCRIPT_MEM_WRITE (
+    EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+    EfiBootScriptWidthUint32,
+    (UINTN) (MmPciAddress (0,
+            0,
+            2,
+            0,
+            R_SA_IGD_GTTMMADR)),
+    1,
+    &GTTMMADR
+    );
+
+  ///
+  /// only 32bit read/write is legal for device 0:2:0
+  ///
+  SCRIPT_MEM_WRITE (
+    EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+    EfiBootScriptWidthUint32,
+    (UINTN) (MmPciAddress (0,
+            0,
+            2,
+            0,
+            R_SA_IGD_GTTMMADR + 4)),
+    1,
+    (&(UINT32) GTTMMADR) + 1
+    );
+
+  GTTMMADR = GTTMMADR &~(BIT2 | BIT1);
+
+  ///
+  /// Enable Bus Master, I/O and Memory access on 0:2:0
+  ///
+  McD2PciCfg16Or (R_SA_IGD_CMD, (BIT2 | BIT1));
+  Data16 = McD2PciCfg16(R_SA_IGD_CMD);
+  SCRIPT_MEM_WRITE (
+    EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+    EfiBootScriptWidthUint16,
+    (UINTN) (MmPciAddress (0, 0, 2, 0, R_SA_IGD_CMD)),
+    1,
+    &Data16
+    );
+
+      ///
+      /// Deassert Force Wake
+      RegOffset                     = 0xA188;
+      Data32                        = 0x00010000;
+      Mmio32 (GTTMMADR, RegOffset)  = Data32;
+
+      SCRIPT_MEM_WRITE (
+        EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+        EfiBootScriptWidthUint32,
+        (UINTN) (GTTMMADR + RegOffset),
+        1,
+        &Data32
+        );
+
+      RegOffset                     = 0x130044;
+      Data32Mask                    = BIT0;
+      Result                        = 0;
+      PollGtReady (GTTMMADR, RegOffset, Data32Mask, Result);
+
+      SCRIPT_MEM_POLL (
+        EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+        EfiBootScriptWidthUint32,
+        (UINTN) (GTTMMADR + RegOffset),
+        &Data32Mask,
+        &Result,
+        50,
+        200000
+        );
+
+      RegOffset                     = 0xA188;
+      Data32                        = 0x00000001;
+      Mmio32 (GTTMMADR, RegOffset)  = Data32;
+      SCRIPT_MEM_WRITE (
+        EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+        EfiBootScriptWidthUint32,
+        (UINTN) (GTTMMADR + RegOffset),
+        1,
+        &Data32
+        );
+
+
+  Status = gBS->LocateProtocol (
+                  &gEfiLegacyBiosProtocolGuid,
+                  NULL,
+                  (VOID **) &LegacyBios
+                  );
+
+
+#ifndef AMI_OVERRIDE_FOR_INTEL_GOP_SUPPORT
+#if (defined(IntelSaGopDriver_SUPPORT) && (IntelSaGopDriver_SUPPORT == 1))
+{
+  EFI_PHYSICAL_ADDRESS          VbtAddress;
+  UINT32                        VbtSize;
+  PLATFORM_GOP_POLICY_PROTOCOL  *PlatformGOPPolicy;
+  EFI_GUID PlatformGOPPolicyGuid = EFI_PLATFORM_GOP_POLICY_PROTOCOL_GUID;
+  EFI_STATUS                    Status2 = EFI_SUCCESS;
+  //
+  // Locate Platform GOP policy protocol
+  //
+  Status = gBS->LocateProtocol (&PlatformGOPPolicyGuid, NULL, &PlatformGOPPolicy);
+  if (!EFI_ERROR(Status)) {
+    Status2 = PlatformGOPPolicy->GetVbtData(&VbtAddress, &VbtSize);
+    if (!EFI_ERROR(Status2)) LegacyBios = NULL;
+  }
+}
+#endif
+#endif // AMI_OVERRIDE_FOR_INTEL_GOP_SUPPORT
+
+  if (!LegacyBios) {
+    Status = gBS->LocateProtocol (&gGopComponentName2ProtocolGuid, NULL, (VOID **)&GopComponentName2Protocol);
+    if (!EFI_ERROR (Status)) {
+      Status = GopComponentName2Protocol->GetDriverVersion (
+                                    GopComponentName2Protocol,
+                                    "en-US",
+                                    &DriverVersion
+                                    );
+      if (!EFI_ERROR (Status)) {
+        for (Index = 0; (DriverVersion[Index] != '\0'); Index++) {
+        }
+        Index = (Index+1)*2;
+        CopyMem(mDxePlatformSaPolicy->IgdConfig->GopVersion, DriverVersion, Index);
+      }
+    }
+  }
+
+  ///
+  /// Return final status
+  ///
+  return EFI_SUCCESS;
+}
+
+EFI_STATUS
+GraphicsInit (
+  IN EFI_HANDLE                      ImageHandle,
+  IN DXE_PLATFORM_SA_POLICY_PROTOCOL *DxePlatformSaPolicy
+  )
+/**
+Initialize GT Post Routines.
+
+  @param[in] ImageHandle         -     Handle for the image of this driver
+  @param[in] DxePlatformSaPolicy -     SA DxePlatformPolicy protocol
+
+  @retval EFI_SUCCESS   - GT POST initialization complete
+  @retval EFI_NOT_FOUND - Dxe System Table not found.
+**/
+{
+  EFI_PHYSICAL_ADDRESS  MemBaseAddress;
+  UINT32                LoGTBaseAddress;
+  UINT32                HiGTBaseAddress;
+  UINT32                Data32And;
+  UINT32                Data32Or;
+  EFI_STATUS            Status;
+  UINTN                 DwordData;
+  UINT32                Data32Mask;
+  UINT32                Result;
+  UINT16                Data16;
+  CPU_FAMILY            CpuFamilyId;
+  UINT8                 CpuSteppingId;
+  UINT32                Data32;
+  UINT16                IsUlx;
+
+  CpuFamilyId   = GetCpuFamily();
+  CpuSteppingId = GetCpuStepping();
+
+  GTTMMADR    = 0;
+  Status      = EFI_SUCCESS;
+  MCHBAR_BASE = McD0PciCfg64 (0x48) &~BIT0;
+
+  ///
+  /// Read the RP1 Graphics Frequency
+  ///
+  rP1GraphicsFreq = (UINT8) ((Mmio32 (MCHBAR_BASE, 0x5998) >> 8) & 0xFF);
+
+  ///
+  /// If device 0:2:0 (Internal Graphics Device, or GT) is enabled, then Program GTTMMADR,
+  ///
+  if (McD2PciCfg16 (R_SA_IGD_VID) != 0xFFFF) {
+    gDS     = NULL;
+    Status  = EfiGetSystemConfigurationTable (&gEfiDxeServicesTableGuid, (VOID **) &gDS);
+    ASSERT_EFI_ERROR (Status);
+    ASSERT(gDS != NULL);
+    if (gDS == NULL) {
+      return EFI_NOT_FOUND;
+    }
+
+    ///
+    /// Means Allocate 4MB for GTTMADDR
+    ///
+    MemBaseAddress = 0x0ffffffffffffffff;
+
+    Status = gDS->AllocateMemorySpace (
+                    EfiGcdAllocateAnySearchBottomUp,
+                    EfiGcdMemoryTypeMemoryMappedIo,
+                    GTT_MEM_ALIGN,
+                    GTTMMADR_SIZE_4MB,
+                    &MemBaseAddress,
+                    ImageHandle,
+                    NULL
+                    );
+    ASSERT_EFI_ERROR (Status);
+
+    ///
+    /// Program GT PM Settings if GTTMMADR allocation is Successful
+    ///
+    GTTMMADR                          = (UINTN) MemBaseAddress;
+
+    LoGTBaseAddress                   = (UINT32) (MemBaseAddress & 0xFFFFFFFF);
+    HiGTBaseAddress                   = (UINT32) RShiftU64 ((MemBaseAddress & 0xFFFFFFFF00000000), 32);
+    McD2PciCfg32 (R_SA_IGD_GTTMMADR)     = LoGTBaseAddress | BIT2;
+    McD2PciCfg32 (R_SA_IGD_GTTMMADR + 4) = HiGTBaseAddress;
+
+    DwordData                         = McD2PciCfg32 (R_SA_IGD_GTTMMADR);
+    SCRIPT_MEM_WRITE (
+      EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+      EfiBootScriptWidthUint32,
+      (UINTN) (MmPciAddress (0,
+              0,
+              2,
+              0,
+              R_SA_IGD_GTTMMADR)),
+      1,
+      &DwordData
+      );
+
+    DwordData = McD2PciCfg32 (R_SA_IGD_GTTMMADR + 4);
+    SCRIPT_MEM_WRITE (
+      EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+      EfiBootScriptWidthUint32,
+      (UINTN) (MmPciAddress (0,
+              0,
+              2,
+              0,
+              R_SA_IGD_GTTMMADR + 4)),
+      1,
+      &DwordData
+      );
+
+    ///
+    /// Enable Bus Master, I/O and Memory access on 0:2:0
+    ///
+    McD2PciCfg16Or (R_SA_IGD_CMD, (BIT2 | BIT1));
+    Data16 = McD2PciCfg16 (R_SA_IGD_CMD);
+    SCRIPT_MEM_WRITE (
+      EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+      EfiBootScriptWidthUint16,
+      (UINTN) (MmPciAddress (0, 0, 2, 0, R_SA_IGD_CMD)),
+      1,
+      &Data16
+      );
+
+    ///
+    /// PAVP Initialization
+    ///
+      DEBUG ((EFI_D_INFO, "Initializing PAVP\n"));
+      PavpInit (ImageHandle, DxePlatformSaPolicy);
+    ///
+    /// PmInit Initialization
+    ///
+    DEBUG ((EFI_D_INFO, "Initializing GT PowerManagement\n"));
+    PmInit (ImageHandle, DxePlatformSaPolicy);
+
+    ///
+    /// Enable PowerWell for DP and Audio: set Dev2 mmio 45400 bit 31 and poll bit30 (1 means enabled)
+    ///
+    Data32And = 0xFFFFFFFF;
+    Data32Or  = (UINT32) (BIT31);
+    Mmio32Or (GTTMMADR, 0x45400, Data32Or);
+    SCRIPT_MEM_READ_WRITE (
+      EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+      EfiBootScriptWidthUint32,
+      (UINTN) (GTTMMADR + 0x45400),
+      &Data32Or,  /// Data to be ORed
+      &Data32And  /// Data to be ANDed
+      );
+
+    Data32Mask  = BIT30;
+    Result      = BIT30;
+    PollGtReady (GTTMMADR, 0x45400, Data32Mask, Result);
+    SCRIPT_MEM_POLL (
+      EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+      EfiBootScriptWidthUint32,
+      (UINTN) (GTTMMADR + 0x45400),
+      &Data32Mask,
+      &Result,
+      50,
+      200000
+      );
+
+    if (DxePlatformSaPolicy->Revision >=4) {
+      IsUlx = 0;
+      Data16 = McD2PciCfg16 (0x2);
+      if ((Data16 == 0xA0E) || (Data16 == 0xA1E)) {
+        IsUlx = 1;
+      }
+      ///
+      /// BIOS to get supported CD frequency
+      ///
+      if (((MmioRead32 (GTTMMADR + 0x42014) & 0x1000000) != 0) || (IsUlx == 1) || (CpuFamilyId == EnumCpuHswUlt)) {
+        ///fixed frequency
+        mDxePlatformSaPolicy->IgdConfig->CdClkVar = 0;
+      } else {
+        ///choice of varying frequency
+        mDxePlatformSaPolicy->IgdConfig->CdClkVar = 2;
+      }
+
+      if (IsUlx == 1) {
+        Data32And = 0xF7FFFFFF;
+        Data32Or  = 0x4000000;
+      } else {
+        if ((mDxePlatformSaPolicy->IgdConfig->CdClk) != 1) {
+          if ((mDxePlatformSaPolicy->IgdConfig->CdClkVar != 0)) {
+            ///540 or 337.5Mhz
+            Data32And = 0xF7FFFFFF;
+            Data32Or  = 0x4000000;
+          }
+        } else {
+          ///450 Mhz
+          Data32And = 0xF3FFFFFF;
+          Data32Or  = 0;
+        }
+      }
+      Mmio32AndThenOr (GTTMMADR, 0x130040, Data32And, Data32Or);
+      SCRIPT_MEM_READ_WRITE (
+        EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+        EfiBootScriptWidthUint32,
+        (UINTN) (GTTMMADR + 0x130040),
+        &Data32Or,  /// Data to be ORed
+        &Data32And  /// Data to be ANDed
+        );
+
+      if ((CpuFamilyId == EnumCpuHswUlt)||(IsUlx == 1)) {
+        Data32 = 1;
+        if (((mDxePlatformSaPolicy->IgdConfig->CdClk) == 1) && (IsUlx == 0)) {
+          Data32 = 0;
+        }
+
+        Mmio32 (GTTMMADR, 0x138128) = Data32;
+        SCRIPT_MEM_WRITE (
+          EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+          EfiBootScriptWidthUint32,
+          (UINTN) (GTTMMADR + 0x138128),
+          1,
+          &Data32
+          );
+
+        Data32                      = 0x0;
+        Mmio32 (GTTMMADR, 0x13812c) = Data32;
+        SCRIPT_MEM_WRITE (
+          EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+          EfiBootScriptWidthUint32,
+          (UINTN) (GTTMMADR + 0x13812c),
+          1,
+          &Data32
+          );
+
+        Data32                      = 0x80000017;
+        Mmio32 (GTTMMADR, 0x138124) = Data32;
+        SCRIPT_MEM_WRITE (
+          EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+          EfiBootScriptWidthUint32,
+          (UINTN) (GTTMMADR + 0x138124),
+          1,
+          &Data32
+          );
+      }
+    }
+
+    McD2PciCfg16And (R_SA_IGD_CMD, ~(BIT2 | BIT1));
+    Data16 = McD2PciCfg16(R_SA_IGD_CMD);
+    SCRIPT_MEM_WRITE (
+      EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+      EfiBootScriptWidthUint16,
+      (UINTN) (MmPciAddress (0, 0, 2, 0, R_SA_IGD_CMD)),
+      1,
+      &Data16
+      );
+
+    McD2PciCfg64 (R_SA_IGD_GTTMMADR) = 0;
+    DwordData = McD2PciCfg64(R_SA_IGD_GTTMMADR);
+    SCRIPT_MEM_WRITE (
+      EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+      EfiBootScriptWidthUint32,
+      (UINTN) (MmPciAddress (0, 0, 2, 0, R_SA_IGD_GTTMMADR)),
+      1,
+      &DwordData
+      );
+
+    ///
+    /// Free allocated resources
+    ///
+    gDS->FreeMemorySpace (MemBaseAddress, GTTMMADR_SIZE_4MB);
+  }
+
+  ///
+  /// Lock PAVPC Register
+  ///
+  McD0PciCfg32Or (R_SA_PAVPC, B_SA_PAVPC_PAVPLCK_MASK);
+
+  DwordData = McD0PciCfg32 (R_SA_PAVPC);
+  SCRIPT_MEM_WRITE (
+    EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+    EfiBootScriptWidthUint32,
+    (UINTN) (MmPciAddress (0,
+                           0,
+                           0,
+                           0,
+                           R_SA_PAVPC)),
+    1,
+    &DwordData
+    );
+
+  return EFI_SUCCESS;
+}
+
+VOID
+PollGtReady (
+  UINT64 Base,
+  UINT32 Offset,
+  UINT32 Mask,
+  UINT32 Result
+  )
+/**
+  "Poll Status" for GT Readiness
+
+  @param[in] Base            - Base address of MMIO
+  @param[in] Offset          - MMIO Offset
+  @param[in] Mask            - Mask
+  @param[in] Result          - Value to wait for
+**/
+{
+  UINT32  GtStatus;
+  UINT16  StallCount;
+
+  StallCount = 0;
+
+  ///
+  /// Register read
+  ///
+  GtStatus = Mmio32 (Base, Offset);
+
+  while (((GtStatus & Mask) != Result) && (StallCount < GT_WAIT_TIMEOUT)) {
+
+    GtStatus = Mmio32 (Base, Offset);
+    ///
+    /// 1mSec wait
+    ///
+    gBS->Stall (1000);
+    StallCount = StallCount + 1;
+  }
+
+  ASSERT ((StallCount != GT_WAIT_TIMEOUT));
+}
diff --git a/ReferenceCode/Chipset/SystemAgent/SaInit/Dxe/graphicsinit.h b/ReferenceCode/Chipset/SystemAgent/SaInit/Dxe/graphicsinit.h
new file mode 100644
index 0000000..d5696e3
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/SaInit/Dxe/graphicsinit.h
@@ -0,0 +1,132 @@
+/** @file
+  Header file for initialization of GT PowerManagement
+
+@copyright
+  Copyright (c) 1999 - 2013 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement
+**/
+#ifndef _GRAPHICS_INIT_H_
+#define _GRAPHICS_INIT_H_
+
+#include "EdkIIGlueDxe.h"
+#include "SaAccess.h"
+#include "EfiScriptLib.h"
+#include EFI_PROTOCOL_DEFINITION (SaPlatformPolicy)
+#include EFI_PROTOCOL_DEFINITION (PciHostBridgeResourceAllocation)
+#include EFI_PROTOCOL_CONSUMER (ExitPmAuth)
+#include "SaInit.h"
+#include "PchAccess.h"
+#include "CpuRegs.h"
+#include "CpuPlatformLib.h"
+
+///
+/// Data definitions
+///
+///
+/// GT RELATED EQUATES
+///
+#define GTT_MEM_ALIGN     22
+#define GTTMMADR_SIZE_4MB 0x400000
+#define GT_WAIT_TIMEOUT   3000     ///< ~3 seconds
+
+///
+/// PAVP Modes
+///
+#define PAVP_LITE_MODE      1
+#define PAVP_SERPENT_MODE   2
+#define PAVP_PCM_SIZE_1_MB  1
+
+EFI_STATUS
+PavpInit (
+  IN EFI_HANDLE                      ImageHandle,
+  IN DXE_PLATFORM_SA_POLICY_PROTOCOL *DxePlatformSaPolicy
+  )
+/**
+  Initialize PAVP feature of SystemAgent.
+
+  @param[in] ImageHandle         - Handle for the image of this driver
+  @param[in] DxePlatformSaPolicy - SA DxePlatformPolicy protocol
+
+  @retval EFI_SUCCESS         - PAVP initialization complete
+**/
+;
+
+/**
+  Initialize PAVP.
+
+  @param[in] ImageHandle         - Handle for the image of this driver
+  @param[in] DxePlatformSaPolicy - SA DxePlatformPolicy protocol
+
+  @retval EFI_SUCCESS - PAVP initialization complete
+**/
+EFI_STATUS
+PmInit (
+  IN EFI_HANDLE                      ImageHandle,
+  IN DXE_PLATFORM_SA_POLICY_PROTOCOL *DxePlatformSaPolicy
+  )
+/**
+  Initialize GT PowerManagement of SystemAgent.
+
+  @param[in] ImageHandle         - Handle for the image of this driver
+  @param[in] DxePlatformSaPolicy - SA DxePlatformPolicy protocol
+
+  @retval EFI_SUCCESS         - GT Power Management initialization complete
+**/
+;
+
+EFI_STATUS
+GraphicsInit (
+  IN EFI_HANDLE                      ImageHandle,
+  IN DXE_PLATFORM_SA_POLICY_PROTOCOL *DxePlatformSaPolicy
+  )
+/**
+  Initialize GT PowerManagement of SystemAgent.
+
+  @param[in] ImageHandle         - Handle for the image of this driver
+  @param[in] DxePlatformSaPolicy - SA DxePlatformPolicy protocol
+
+  @retval EFI_SUCCESS         - GT Power Management initialization complete
+**/
+;
+
+VOID
+PollGtReady (
+  UINT64 Base,
+  UINT32 Offset,
+  UINT32 Mask,
+  UINT32 Result
+  )
+/**
+  "Poll Status" for GT Readiness
+
+  @param[in] Base            - Base address of MMIO
+  @param[in] Offset          - MMIO Offset
+  @param[in] Mask            - Mask
+  @param[in] Result          - Value to wait for
+**/
+;
+
+EFI_STATUS
+PostPmInitExitPmAuth (
+  VOID
+  )
+/**
+  Do Post GT PM Init Steps after VBIOS Initialization.
+
+  @retval EFI_SUCCESS          Succeed.
+**/
+;
+#endif
diff --git a/ReferenceCode/Chipset/SystemAgent/SaInit/Dxe/igdopregion.c b/ReferenceCode/Chipset/SystemAgent/SaInit/Dxe/igdopregion.c
new file mode 100644
index 0000000..0774807
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/SaInit/Dxe/igdopregion.c
@@ -0,0 +1,955 @@
+/** @file
+  This is part of the implementation of an Intel Graphics drivers OpRegion /
+  Software SCI interface between system BIOS, ASL code, and Graphics drivers.
+  The code in this file will load the driver and initialize the interface
+
+  Supporting Specifiction: OpRegion / Software SCI SPEC 0.70
+
+  Acronyms:
+    IGD:        Internal Graphics Device
+    NVS:        ACPI Non Volatile Storage
+    OpRegion:   ACPI Operational Region
+    VBT:        Video BIOS Table (OEM customizable data)
+
+@copyright
+  Copyright (c) 1999 - 2013 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement
+
+**/
+
+///
+/// Include files
+///
+#include "IgdOpRegion.h"
+#include "CpuIA32.h"
+#include "CpuRegs.h"
+#include "CpuPlatformLib.h"
+#include <Protocol\SaPlatformPolicy\SaPlatformPolicy.h>
+#ifndef AMI_OVERRIDE_FOR_INTEL_GOP_SUPPORT
+#include "Token.h"
+#if (defined(IntelSaGopDriver_SUPPORT) && (IntelSaGopDriver_SUPPORT == 1))
+#include "Include\Protocol\IntelSaGopDriver.h"
+#endif
+#endif
+
+///
+/// Global variables
+///
+IGD_OPREGION_PROTOCOL                  mIgdOpRegion;
+EFI_GUID                               mMiscSubClass = EFI_MISC_SUBCLASS_GUID;
+EFI_EVENT                              mExitPmAuthEvent;
+BOOLEAN                                mRunExitPmAuthRoutine;
+SYSTEM_AGENT_GLOBAL_NVS_AREA_PROTOCOL  *mSaGlobalNvsArea;
+DXE_PLATFORM_SA_POLICY_PROTOCOL        *mDxePlatformSaPolicy;
+
+///
+/// Function implementations.
+///
+EFI_STATUS
+GetIntegratedIntelVbtPtr (
+  OUT VBIOS_VBT_STRUCTURE **VbtFileBuffer
+  )
+/**
+  Get VBT data using SaPlaformPolicy
+
+  @param[in] VbtFileBuffer    Pointer to VBT data buffer.
+
+  @retval EFI_SUCCESS      VBT data was returned.
+  @retval EFI_NOT_FOUND    VBT data not found.
+  @exception EFI_UNSUPPORTED  Invalid signature in VBT data.
+**/
+{
+  EFI_STATUS                    Status;
+  EFI_PHYSICAL_ADDRESS          VbtAddress;
+  UINT32                        Size;
+
+  ///
+  /// Get the platform SA policy.
+  ///
+  Status = gBS->LocateProtocol (
+                  &gDxePlatformSaPolicyGuid,
+                  NULL,
+                  (VOID **) &mDxePlatformSaPolicy
+                  );
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+
+  VbtAddress = mDxePlatformSaPolicy->IgdConfig->VbtAddress;
+  Size       = mDxePlatformSaPolicy->IgdConfig->Size ;
+
+  if (VbtAddress == 0x00000000) {
+    return EFI_NOT_FOUND;
+  } else {
+    ///
+    /// Check VBT signature
+    ///
+    *VbtFileBuffer  = NULL;
+    *VbtFileBuffer = (VBIOS_VBT_STRUCTURE *) (UINTN) VbtAddress;
+    if ((*((UINT32 *) ((*VbtFileBuffer)->HeaderSignature))) != VBT_SIGNATURE) {
+      FreePool (*VbtFileBuffer);
+      *VbtFileBuffer = NULL;
+      return EFI_UNSUPPORTED;
+    }
+  }
+  if (Size == 0) {
+    return EFI_NOT_FOUND;
+  } else {
+    ///
+    /// Check VBT size
+    ///
+    if ((*VbtFileBuffer)->HeaderVbtSize > Size) {
+      (*VbtFileBuffer)->HeaderVbtSize = (UINT16) Size;
+    }
+  }
+  return EFI_SUCCESS;
+}
+
+EFI_STATUS
+GetIntegratedIntelVBiosPtr (
+  OUT INTEL_VBIOS_OPTION_ROM_HEADER **VBiosImage
+  )
+/**
+  Get a pointer to an uncompressed image of the Intel video BIOS.
+
+  Note: This function would only be called if the video BIOS at 0xC000 is
+        missing or not an Intel video BIOS.  It may not be an Intel video BIOS
+        if the Intel graphic contoller is considered a secondary adapter.
+
+  @param[in] VBiosImage   - Pointer to an uncompressed Intel video BIOS.  This pointer must
+                            be set to NULL if an uncompressed image of the Intel Video BIOS
+                            is not obtainable.
+
+  @retval EFI_SUCCESS        - VBiosPtr is updated.
+  @exception EFI_UNSUPPORTED - No Intel video BIOS found.
+**/
+
+{
+  EFI_HANDLE                    *HandleBuffer;
+  UINTN                         HandleCount;
+  UINTN                         Index;
+  INTEL_VBIOS_PCIR_STRUCTURE    *PcirBlockPtr;
+  EFI_STATUS                    Status;
+  EFI_PCI_IO_PROTOCOL           *PciIo;
+  INTEL_VBIOS_OPTION_ROM_HEADER *VBiosRomImage;
+  ///
+  /// Set as if an umcompressed Intel video BIOS image was not obtainable.
+  ///
+  VBiosRomImage = NULL;
+
+  ///
+  /// Get all PCI IO protocols
+  ///
+  Status = gBS->LocateHandleBuffer (
+                  ByProtocol,
+                  &gEfiPciIoProtocolGuid,
+                  NULL,
+                  &HandleCount,
+                  &HandleBuffer
+                  );
+  ASSERT_EFI_ERROR (Status);
+
+  ///
+  /// Find the video BIOS by checking each PCI IO handle for an Intel video
+  /// BIOS OPROM.
+  ///
+  for (Index = 0; Index < HandleCount; Index++) {
+    Status = gBS->HandleProtocol (
+                    HandleBuffer[Index],
+                    &gEfiPciIoProtocolGuid,
+                    (VOID **) &PciIo
+                    );
+    ASSERT_EFI_ERROR (Status);
+
+    VBiosRomImage = PciIo->RomImage;
+
+    ///
+    /// If this PCI device doesn't have a ROM image, skip to the next device.
+    ///
+    if (!VBiosRomImage) {
+      continue;
+    }
+    ///
+    /// Get pointer to PCIR structure
+    ///
+    PcirBlockPtr = (INTEL_VBIOS_PCIR_STRUCTURE *) ((UINT8 *) VBiosRomImage + VBiosRomImage->PcirOffset);
+
+    ///
+    /// Check if we have an Intel video BIOS OPROM.
+    ///
+    if ((VBiosRomImage->Signature == OPTION_ROM_SIGNATURE) &&
+        (PcirBlockPtr->VendorId == V_SA_MC_VID) &&
+        (PcirBlockPtr->ClassCode[0] == 0x00) &&
+        (PcirBlockPtr->ClassCode[1] == 0x00) &&
+        (PcirBlockPtr->ClassCode[2] == 0x03)
+        ) {
+      ///
+      /// Found Intel video BIOS.
+      ///
+      *VBiosImage = VBiosRomImage;
+      return EFI_SUCCESS;
+    }
+  }
+  ///
+  /// No Intel video BIOS found.
+  ///
+  ///
+  /// Free any allocated buffers
+  ///
+  FreePool (HandleBuffer);
+  return EFI_UNSUPPORTED;
+}
+
+EFI_STATUS
+GetVBiosVbtExitPmAuth (
+  VOID
+  )
+/**
+  Get Intel video BIOS VBT information (i.e. Pointer to VBT and VBT size).
+  The VBT (Video BIOS Table) is a block of customizable data that is built
+  within the video BIOS and edited by customers.
+
+  @retval EFI_SUCCESS            - Video BIOS VBT information returned.
+  @exception EFI_UNSUPPORTED     - Could not find VBT information (*VBiosVbtPtr = NULL).
+**/
+{
+  INTEL_VBIOS_PCIR_STRUCTURE    *PcirBlockPtr;
+  UINT16                        PciVenderId;
+  INTEL_VBIOS_OPTION_ROM_HEADER *VBiosPtr;
+  VBIOS_VBT_STRUCTURE           *VBiosVbtPtr;
+  EFI_LEGACY_BIOS_PROTOCOL      *LegacyBios;
+  EFI_STATUS                    Status;
+  VBIOS_VBT_STRUCTURE           *VbtFileBuffer;
+  UINTN                         Index;
+#ifndef AMI_OVERRIDE_FOR_INTEL_GOP_SUPPORT
+#if (defined(IntelSaGopDriver_SUPPORT) && (IntelSaGopDriver_SUPPORT == 1))
+  EFI_PHYSICAL_ADDRESS          VbtAddress;
+  UINT32                        VbtSize;
+  PLATFORM_GOP_POLICY_PROTOCOL  *PlatformGOPPolicy;
+  EFI_GUID PlatformGOPPolicyGuid = EFI_PLATFORM_GOP_POLICY_PROTOCOL_GUID;
+  EFI_STATUS                    Status2 = EFI_SUCCESS;
+#endif
+#endif // AMI_OVERRIDE_FOR_INTEL_GOP_SUPPORT
+
+  if (!mRunExitPmAuthRoutine) {
+    return EFI_SUCCESS;
+  }
+
+  ///
+  /// Get the platform SA policy.
+  ///
+  Status = gBS->LocateProtocol (
+                  &gDxePlatformSaPolicyGuid,
+                  NULL,
+                  (VOID **) &mDxePlatformSaPolicy
+                  );
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+
+  LegacyBios = NULL;
+  VBiosPtr = NULL;
+
+  Status = gBS->LocateProtocol (&gEfiLegacyBiosProtocolGuid, NULL, (VOID **) &LegacyBios);
+
+#ifndef AMI_OVERRIDE_FOR_INTEL_GOP_SUPPORT
+#if (defined(IntelSaGopDriver_SUPPORT) && (IntelSaGopDriver_SUPPORT == 1))
+  //
+  // Locate Platform GOP policy protocol
+  //
+  Status = gBS->LocateProtocol (&PlatformGOPPolicyGuid, NULL, &PlatformGOPPolicy);
+  if (!EFI_ERROR(Status)) {
+    Status2 = PlatformGOPPolicy->GetVbtData(&VbtAddress, &VbtSize);
+    if (!EFI_ERROR(Status2)) LegacyBios = NULL;
+  }
+#endif
+#endif // AMI_OVERRIDE_FOR_INTEL_GOP_SUPPORT
+
+  if (LegacyBios) {
+    VBiosPtr      = (INTEL_VBIOS_OPTION_ROM_HEADER *) (UINTN) (VBIOS_LOCATION_PRIMARY);
+    PcirBlockPtr  = (INTEL_VBIOS_PCIR_STRUCTURE *) ((UINT8 *) VBiosPtr + VBiosPtr->PcirOffset);
+    PciVenderId   = PcirBlockPtr->VendorId;
+    ///
+    /// If the video BIOS is not at 0xC0000 or it is not an Intel video BIOS get
+    /// the integrated Intel video BIOS (must be uncompressed).
+    ///
+    if ((VBiosPtr->Signature != OPTION_ROM_SIGNATURE) || (PciVenderId != V_SA_MC_VID)) {
+      GetIntegratedIntelVBiosPtr (&VBiosPtr);
+      if (VBiosPtr != NULL) {
+        ///
+        /// Video BIOS found.
+        ///
+        PcirBlockPtr  = (INTEL_VBIOS_PCIR_STRUCTURE *) ((UINT8 *) VBiosPtr + VBiosPtr->PcirOffset);
+        PciVenderId   = PcirBlockPtr->VendorId;
+
+        if ((VBiosPtr->Signature != OPTION_ROM_SIGNATURE) || (PciVenderId != V_SA_MC_VID)) {
+          ///
+          /// Intel video BIOS not found.
+          ///
+          VBiosVbtPtr = NULL;
+          return EFI_UNSUPPORTED;
+        }
+      }
+    }
+  } else {
+    ///
+    /// No Video BIOS found, try to get VBT from FV.
+    ///
+    GetIntegratedIntelVbtPtr (&VbtFileBuffer);
+    if (VbtFileBuffer != NULL) {
+      ///
+      /// Video BIOS not found, use VBT from SaPlatformPolicy
+      ///
+      DEBUG ((EFI_D_INFO, "VBT data found\n"));
+      for (Index = 0; (mDxePlatformSaPolicy->IgdConfig->GopVersion[Index] != '\0'); Index++) {
+      }
+      Index = (Index+1)*2;
+      CopyMem (mIgdOpRegion.OpRegion->Header.DVER, mDxePlatformSaPolicy->IgdConfig->GopVersion, Index);
+      (gBS->CopyMem) (mIgdOpRegion.OpRegion->VBT.GVD1, VbtFileBuffer, VbtFileBuffer->HeaderVbtSize);
+      FreePool (VbtFileBuffer);
+      return EFI_SUCCESS;
+    }
+  }
+
+  if (VBiosPtr == NULL) {
+    return EFI_UNSUPPORTED;
+  }
+
+  DEBUG ((EFI_D_INFO, "VBIOS found at 0x%X\n", VBiosPtr));
+  VBiosVbtPtr = (VBIOS_VBT_STRUCTURE *) ((UINT8 *) VBiosPtr + VBiosPtr->VbtOffset);
+
+  if ((*((UINT32 *) (VBiosVbtPtr->HeaderSignature))) != VBT_SIGNATURE) {
+    return EFI_UNSUPPORTED;
+  }
+  ///
+  /// No PlatformGopPolicy.h in EDK II code
+  ///
+#if 0
+  GetSVER (mIgdOpRegion.OpRegion->Header.SVER);
+#endif
+  DEBUG ((EFI_D_INFO, "System BIOS ID is %a\n", mIgdOpRegion.OpRegion->Header.SVER));
+
+  ///
+  /// Initialize Video BIOS version with its build number.
+  ///
+  mIgdOpRegion.OpRegion->Header.VVER[0] = VBiosVbtPtr->CoreBlockBiosBuild[0];
+  mIgdOpRegion.OpRegion->Header.VVER[1] = VBiosVbtPtr->CoreBlockBiosBuild[1];
+  mIgdOpRegion.OpRegion->Header.VVER[2] = VBiosVbtPtr->CoreBlockBiosBuild[2];
+  mIgdOpRegion.OpRegion->Header.VVER[3] = VBiosVbtPtr->CoreBlockBiosBuild[3];
+  (gBS->CopyMem) (mIgdOpRegion.OpRegion->VBT.GVD1, VBiosVbtPtr, VBiosVbtPtr->HeaderVbtSize);
+
+  ///
+  /// Return final status
+  ///
+  return EFI_SUCCESS;
+}
+///
+/// No PlatformGopPolicy.h in EDK II code
+///
+#if 0
+EFI_STATUS
+GetSVER (
+  OUT UINT8 *SVER
+  )
+/**
+  Set the SVER (system BIOS ID) string with the system BIOS build number.
+
+  @param[in] SVER  String to populate with system BIOS build number.
+
+  @retval EFI_SUCCESS     The SVER string is populated.
+  @exception EFI_UNSUPPORTED The SVER string is not populated.
+**/
+{
+  EFI_SUBCLASS_TYPE1_HEADER *DataHeader;
+  EFI_DATA_HUB_PROTOCOL     *DataHub;
+  EFI_MISC_BIOS_VENDOR      *BiosVendor;
+  UINTN                     Length;
+  UINT64                    MonotonicCount;
+  CHAR16                    *NewString;
+  EFI_DATA_RECORD_HEADER    *Record;
+  EFI_STATUS                Status;
+
+  ///
+  ///  Locate the data hub protocol.
+  ///
+  Status = gBS->LocateProtocol (
+                  &gEfiDataHubProtocolGuid,
+                  NULL,
+                  &DataHub
+                  );
+  ASSERT_EFI_ERROR (Status);
+
+  ///
+  ///  Get the BIOS ID from the data hub.
+  ///
+  MonotonicCount  = 0;
+  Record          = NULL;
+
+  do {
+    ///
+    /// Check each data class record
+    ///
+    Status = DataHub->GetNextRecord (DataHub, &MonotonicCount, NULL, &Record);
+    if (Record->DataRecordClass == EFI_DATA_RECORD_CLASS_DATA) {
+      ///
+      /// Check for BIOS vendor information
+      ///
+      DataHeader = (EFI_SUBCLASS_TYPE1_HEADER *) (Record + 1);
+      if (CompareGuid (&Record->DataRecordGuid, &mMiscSubClass) &&
+          (DataHeader->RecordType == EFI_MISC_BIOS_VENDOR_RECORD_NUMBER)
+          ) {
+        BiosVendor = (EFI_MISC_BIOS_VENDOR *) (DataHeader + 1);
+
+        ///
+        /// Get the BIOS ID string from the HII database
+        ///
+        Status = GetStringFromToken (&Record->ProducerName, BiosVendor->BiosVersion, &NewString);
+        ASSERT_EFI_ERROR (Status);
+
+        ///
+        /// Convert from Unicode to ASCII
+        ///
+        if (NewString != NULL) {
+          Length = StrLen (NewString);
+          ASSERT (Length <= SVER_SIZE);
+          ASPrint (SVER, Length, "%s", NewString);
+          return EFI_SUCCESS;
+        }
+      }
+    }
+  } while ((!EFI_ERROR (Status)) && (MonotonicCount != 0));
+
+  ///
+  /// We assume BIOS ID is present and required.
+  /// If this is not the case, BIOS ID will need to be determined in another way.
+  ///
+  ASSERT_EFI_ERROR (EFI_UNSUPPORTED);
+  return EFI_UNSUPPORTED;
+}
+
+#if (EFI_SPECIFICATION_VERSION < 0x0002000A)
+EFI_STATUS
+GetStringFromToken (
+  IN      EFI_GUID                  *ProducerGuid,
+  IN      STRING_REF                Token,
+  OUT     CHAR16                    **String
+  )
+/**
+  Acquire the string associated with the ProducerGuid and return it.
+
+  @param[in] ProducerGuid - The Guid to search the HII database for
+  @param[in] Token - The token value of the string to extract
+  @param[in] String - The string that is extracted
+
+  @retval EFI_SUCCESS       The function completed successfully
+  @retval EFI_NOT_FOUND     The requested string was not found
+**/
+{
+  EFI_STATUS        Status;
+  UINT16            HandleBufferLength;
+  EFI_HII_HANDLE    *HiiHandleBuffer;
+  UINTN             StringBufferLength;
+  UINTN             NumberOfHiiHandles;
+  UINTN             Index;
+  UINT16            Length;
+  EFI_GUID          HiiGuid;
+  EFI_HII_PROTOCOL  *Hii;
+
+  HandleBufferLength  = 0x1000;
+  HiiHandleBuffer     = NULL;
+
+  ///
+  /// Locate HII protocol
+  ///
+  Status = gBS->LocateProtocol (&gEfiHiiProtocolGuid, NULL, &Hii);
+  ASSERT_EFI_ERROR (Status);
+
+  ///
+  /// Get all the Hii handles
+  ///
+  HiiHandleBuffer = AllocateZeroPool (HandleBufferLength);
+
+  Status          = Hii->FindHandles (Hii, &HandleBufferLength, HiiHandleBuffer);
+  ASSERT_EFI_ERROR (Status);
+
+  ///
+  /// Get the Hii Handle that matches the StructureNode->ProducerName
+  ///
+  NumberOfHiiHandles = HandleBufferLength / sizeof (EFI_HII_HANDLE);
+  for (Index = 0; Index < NumberOfHiiHandles; Index++) {
+    Length = 0;
+    Status = ExtractDataFromHiiHandle (
+              HiiHandleBuffer[Index],
+              &Length,
+              NULL,
+              &HiiGuid
+              );
+    if (CompareGuid (ProducerGuid, &HiiGuid)) {
+      break;
+    }
+  }
+  ///
+  /// Find the string based on the current language
+  ///
+  StringBufferLength  = 0x100;
+  *String             = AllocateZeroPool (0x100);
+  Status = Hii->GetString (
+                  Hii,
+                  HiiHandleBuffer[Index],
+                  Token,
+                  FALSE,
+                  NULL,
+                  &StringBufferLength,
+                  *String
+                  );
+
+  (gBS->FreePool) (HiiHandleBuffer);
+
+  if (EFI_ERROR (Status)) {
+    (gBS->FreePool) (*String);
+    return EFI_NOT_FOUND;
+  }
+
+  return EFI_SUCCESS;
+}
+#endif
+#endif
+
+EFI_STATUS
+IgdOpRegionInit (
+  VOID
+  )
+/**
+  Graphics OpRegion / Software SCI driver installation function.
+
+  @param[in] void         - None
+  @retval EFI_SUCCESS     - The driver installed without error.
+  @retval EFI_ABORTED     - The driver encountered an error and could not complete
+                            installation of the ACPI tables.
+**/
+
+{
+  EFI_HANDLE                    Handle;
+  EFI_STATUS                    Status;
+  ///
+  ///  VBIOS_VBT_STRUCTURE           *VBiosVbtPtr;
+  ///
+  UINT32                        DwordData;
+  EFI_CPU_IO_PROTOCOL           *CpuIo;
+  UINT16                        Data16;
+  UINT32                        Data32;
+  UINT16                        PchAcpiBaseAddress;
+  UINT16                        DeviceId;
+  PCH_SERIES                    PchSeries;
+  CPU_FAMILY                    CpuFamilyId;
+  EFI_GUID                      DxePlatformSaPolicyGuid = DXE_PLATFORM_SA_POLICY_GUID;
+  DXE_PLATFORM_SA_POLICY_PROTOCOL  *DxePlatformSaPolicy;
+
+  CpuFamilyId = GetCpuFamily();
+
+  ///
+  /// Get the platform SA policy.
+  ///
+  Status = gBS->LocateProtocol (
+                  &gDxePlatformSaPolicyGuid,
+                  NULL,
+                  (VOID **) &mDxePlatformSaPolicy
+                  );
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+  ///
+  ///  Locate the SA Global NVS Protocol.
+  ///
+  Status = gBS->LocateProtocol (
+                  &gSaGlobalNvsAreaProtocolGuid,
+                  NULL,
+                  (VOID **) &mSaGlobalNvsArea
+                  );
+  ASSERT_EFI_ERROR (Status);
+
+  ///
+  /// Allocate an ACPI NVS memory buffer as the IGD OpRegion, zero initialize
+  /// the first 1K, and set the IGD OpRegion pointer in the Global NVS
+  /// area structure.
+  ///
+  Status = (gBS->AllocatePool) (EfiACPIMemoryNVS, sizeof (IGD_OPREGION_STRUC), (VOID **) &mIgdOpRegion.OpRegion);
+  ASSERT_EFI_ERROR (Status);
+
+  (gBS->SetMem) (mIgdOpRegion.OpRegion, 0x2000, 0);
+  mSaGlobalNvsArea->Area->IgdOpRegionAddress = (UINT32) (UINTN) (mIgdOpRegion.OpRegion);
+
+  ///
+  /// If IGD is disabled return
+  ///
+  mRunExitPmAuthRoutine = TRUE;
+  if (IgdMmPci32 (0) == 0xFFFFFFFF) {
+    mRunExitPmAuthRoutine = FALSE;
+    return EFI_SUCCESS;
+  }
+
+  PchSeries = GetPchSeries();
+  ///
+  /// Initialize OpRegion Header
+  ///
+  (gBS->CopyMem) (mIgdOpRegion.OpRegion->Header.SIGN, HEADER_SIGNATURE, sizeof (HEADER_SIGNATURE));
+  ///
+  /// Set OpRegion Size in KBs
+  ///
+  mIgdOpRegion.OpRegion->Header.SIZE = HEADER_SIZE / 1024;
+  mIgdOpRegion.OpRegion->Header.OVER = (UINT32) (LShiftU64 (HEADER_OPREGION_VER, 16) + LShiftU64 (HEADER_OPREGION_REV, 8));
+
+  ///
+  /// Get CPU Flavor by reading System Agent's Device ID (B0:D1F:F0:R02)
+  ///
+  DeviceId = McD0PciCfg16 (R_SA_MC_DEVICE_ID);
+  if (IS_SA_DEVICE_ID_MOBILE (DeviceId)) {
+    ///
+    /// For Mobile, all Mailbox are supported.
+    ///
+    mIgdOpRegion.OpRegion->Header.MBOX = HEADER_MBOX_SUPPORT_MOBILE;
+  } else if (IS_SA_DEVICE_ID_DESKTOP (DeviceId) || IS_SA_DEVICE_ID_SERVER (DeviceId)) {
+    ///
+    /// For Desktop and Server, Mailbox 1/3/5 are not supported.
+    ///
+    mIgdOpRegion.OpRegion->Header.MBOX = HEADER_MBOX_SUPPORT_DESKTOP;
+  } else {
+    DEBUG ((EFI_D_ERROR, "Hang if unknown System Agent\n"));
+    ASSERT (FALSE);
+    ///
+    /// Hang if unknown System Agent
+    ///
+  }
+  ///
+  /// Initialize OpRegion Mailbox 1 (Public ACPI Methods).
+  ///
+  /// @todo:  The initial setting of mailbox 1 fields is implementation specific.
+  /// Adjust them as needed many even coming from user setting in setup.
+  ///
+  ///
+  /// Initialize OpRegion Mailbox 3 (ASLE Interrupt and Power Conservation).
+  ///
+  /// @todo:  The initial setting of mailbox 3 fields is implementation specific.
+  /// Adjust them as needed many even coming from user setting in setup.
+  ///
+  ///
+  /// Do not initialize TCHE. This field is written by the graphics driver only.
+  ///
+  ///
+  /// The ALSI field is generally initialized by ASL code by reading the embedded controller.
+  ///
+  if (mDxePlatformSaPolicy->Revision >= 5) {
+    mIgdOpRegion.OpRegion->Header.PCON = mDxePlatformSaPolicy->IgdConfig->PlatformConfig;
+    if (CpuFamilyId == EnumCpuHswUlt) {
+      mIgdOpRegion.OpRegion->Header.PCON = mIgdOpRegion.OpRegion->Header.PCON | 0x2;
+    }
+  }
+  mIgdOpRegion.OpRegion->MBox3.BCLP = BACKLIGHT_BRIGHTNESS;
+
+  mIgdOpRegion.OpRegion->MBox3.PFIT = (FIELD_VALID_BIT | PFIT_STRETCH);
+
+  ///
+  /// Reporting to driver for VR IMON Calibration. Bits [5-1] values supported 14A to 31A.
+  ///
+  mIgdOpRegion.OpRegion->MBox3.PCFT = (mSaGlobalNvsArea->Area->GfxTurboIMON << 1) & 0x003E;
+
+  ///
+  /// Set Initial current Brightness
+  ///
+  mIgdOpRegion.OpRegion->MBox3.CBLV = (INIT_BRIGHT_LEVEL | FIELD_VALID_BIT);
+
+  ///
+  /// <EXAMPLE> Create a static Backlight Brightness Level Duty cycle Mapping Table
+  /// Possible 20 entries (example used 10), each 16 bits as follows:
+  /// [15] = Field Valid bit, [14:08] = Level in Percentage (0-64h), [07:00] = Desired duty cycle (0 - FFh).
+  ///
+  mIgdOpRegion.OpRegion->MBox3.BCLM[0] = (0x0000 + WORD_FIELD_VALID_BIT);  ///< 0%
+  ///
+  mIgdOpRegion.OpRegion->MBox3.BCLM[1] = (0x0A19 + WORD_FIELD_VALID_BIT);  ///< 10%
+  mIgdOpRegion.OpRegion->MBox3.BCLM[2] = (0x1433 + WORD_FIELD_VALID_BIT);  ///< 20%
+  mIgdOpRegion.OpRegion->MBox3.BCLM[3] = (0x1E4C + WORD_FIELD_VALID_BIT);  ///< 30%
+  mIgdOpRegion.OpRegion->MBox3.BCLM[4] = (0x2866 + WORD_FIELD_VALID_BIT);  ///< 40%
+  mIgdOpRegion.OpRegion->MBox3.BCLM[5] = (0x327F + WORD_FIELD_VALID_BIT);  ///< 50%
+  mIgdOpRegion.OpRegion->MBox3.BCLM[6] = (0x3C99 + WORD_FIELD_VALID_BIT);  ///< 60%
+  mIgdOpRegion.OpRegion->MBox3.BCLM[7] = (0x46B2 + WORD_FIELD_VALID_BIT);  ///< 70%
+  mIgdOpRegion.OpRegion->MBox3.BCLM[8] = (0x50CC + WORD_FIELD_VALID_BIT);  ///< 80%
+  mIgdOpRegion.OpRegion->MBox3.BCLM[9] = (0x5AE5 + WORD_FIELD_VALID_BIT);  ///< 90%
+  mIgdOpRegion.OpRegion->MBox3.BCLM[10] = (0x64FF + WORD_FIELD_VALID_BIT);  ///< 100%
+
+  mIgdOpRegion.OpRegion->MBox3.IUER = 0x00;
+
+  Status = gBS->LocateProtocol (&DxePlatformSaPolicyGuid, NULL, &DxePlatformSaPolicy);
+ 
+  if (!EFI_ERROR(Status)) {
+    mIgdOpRegion.OpRegion->MBox3.IUER =  DxePlatformSaPolicy->IgdConfig->IuerStatusVal;
+  }
+
+  ///
+  /// Initialize hardware state:
+  ///   Set ASLS Register to the OpRegion physical memory address.
+  ///   Set SWSCI register bit 15 to a "1" to activate SCI interrupts.
+  ///
+  IgdMmPci32 (R_SA_IGD_ASLS_OFFSET) = (UINT32) (UINTN) (mIgdOpRegion.OpRegion);
+  IgdMmPci16AndThenOr (R_SA_IGD_SWSCI_OFFSET, ~(BIT0), BIT15);
+
+  DwordData = IgdMmPci32 (R_SA_IGD_ASLS_OFFSET);
+  SCRIPT_MEM_WRITE (
+    EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+    EfiBootScriptWidthUint32,
+    (UINTN) (MmPciAddress (0x0,
+            SA_IGD_BUS,
+            SA_IGD_DEV,
+            SA_IGD_FUN_0,
+            R_SA_IGD_ASLS_OFFSET)),
+    1,
+    &DwordData
+    );
+  DwordData = IgdMmPci32 (R_SA_IGD_SWSCI_OFFSET);
+  SCRIPT_MEM_WRITE (
+    EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+    EfiBootScriptWidthUint32,
+    (UINTN) (MmPciAddress (0x0,
+            SA_IGD_BUS,
+            SA_IGD_DEV,
+            SA_IGD_FUN_0,
+            R_SA_IGD_SWSCI_OFFSET)),
+    1,
+    &DwordData
+    );
+  PchAcpiBaseAddress = MmPci16 (
+                        0,
+                        DEFAULT_PCI_BUS_NUMBER_PCH,
+                        PCI_DEVICE_NUMBER_PCH_LPC,
+                        PCI_FUNCTION_NUMBER_PCH_LPC,
+                        R_PCH_LPC_ACPI_BASE
+                        ) &~BIT0;
+
+  ///
+  /// Find the CPU I/O Protocol.  ASSERT if not found.
+  ///
+  Status = gBS->LocateProtocol (
+                  &gEfiCpuIoProtocolGuid,
+                  NULL,
+                  (VOID **) &CpuIo
+                  );
+  ASSERT_EFI_ERROR (Status);
+
+  CpuIo->Io.Read (
+              CpuIo,
+              EfiCpuIoWidthUint16,
+              PchAcpiBaseAddress + PCH_TCO_BASE + R_PCH_TCO1_STS,
+              1,
+              &Data16
+              );
+  ///
+  /// Clear the B_DMISCI_STS bit in R_TCO1_STS by writing a '1'.
+  ///
+  Data16 &= B_PCH_TCO1_STS_DMISCI;
+
+  CpuIo->Io.Write (
+              CpuIo,
+              EfiCpuIoWidthUint16,
+              PchAcpiBaseAddress + PCH_TCO_BASE + R_PCH_TCO1_STS,
+              1,
+              &Data16
+              );
+
+  if (PchSeries == PchLp) {
+    ///
+    /// Clear the ACPI TCO status.
+    ///
+    Data32 = B_PCH_ACPI_GPE0_STS_127_96_TC0SCI;
+    CpuIo->Io.Write (
+                CpuIo,
+                EfiCpuIoWidthUint32,
+                (UINT64) (PchAcpiBaseAddress + R_PCH_ACPI_GPE0_STS_127_96),
+                1,
+                &Data32
+                );
+
+    ///
+    /// Enable ACPI TCO SCI's.
+    ///
+    CpuIo->Io.Read (
+                CpuIo,
+                EfiCpuIoWidthUint16,
+                (UINT64) (PchAcpiBaseAddress + R_PCH_ACPI_GPE0_EN_127_96),
+                1,
+                &Data16
+                );
+    Data16 |= B_PCH_ACPI_GPE0_EN_127_96_TC0SCI;
+    CpuIo->Io.Write (
+                CpuIo,
+                EfiCpuIoWidthUint16,
+                (UINT64) (PchAcpiBaseAddress + R_PCH_ACPI_GPE0_EN_127_96),
+                1,
+                &Data16
+                );
+  } else if (PchSeries == PchH) {
+    ///
+    /// Clear the ACPI TCO status.
+    ///
+    Data32 = B_PCH_ACPI_GPE0a_STS_TC0SCI;
+    CpuIo->Io.Write (
+                CpuIo,
+                EfiCpuIoWidthUint32,
+                (UINT64) (PchAcpiBaseAddress + R_PCH_ACPI_GPE0a_STS),
+                1,
+                &Data32
+                );
+
+    ///
+    /// Enable ACPI TCO SCI's.
+    ///
+    CpuIo->Io.Read (
+                CpuIo,
+                EfiCpuIoWidthUint16,
+                (UINT64) (PchAcpiBaseAddress + R_PCH_ACPI_GPE0a_EN),
+                1,
+                &Data16
+                );
+    Data16 |= B_PCH_ACPI_GPE0a_EN_TC0SCI;
+    CpuIo->Io.Write (
+                CpuIo,
+                EfiCpuIoWidthUint16,
+                (UINT64) (PchAcpiBaseAddress + R_PCH_ACPI_GPE0a_EN),
+                1,
+                &Data16
+                );
+  }
+
+  ///
+  /// Install OpRegion / Software SCI protocol
+  ///
+  Handle = NULL;
+  Status = gBS->InstallMultipleProtocolInterfaces (
+                  &Handle,
+                  &gIgdOpRegionProtocolGuid,
+                  &mIgdOpRegion,
+                  NULL
+                  );
+  ASSERT_EFI_ERROR (Status);
+
+  ///
+  /// Return final status
+  ///
+  return EFI_SUCCESS;
+}
+
+
+EFI_STATUS
+UpdateIgdOpRegionExitPmAuth (
+  VOID
+  )
+/**
+  Update Graphics OpRegion after PCI enumeration.
+
+  @param[in] void         - None
+  @retval EFI_SUCCESS     - The function completed successfully.
+**/
+{
+  EFI_STATUS                    Status;
+  UINTN                         HandleCount;
+  EFI_HANDLE                    *HandleBuffer;
+  UINTN                         Index;
+  EFI_PCI_IO_PROTOCOL           *PciIo;
+  PCI_TYPE00                    Pci;
+  UINTN                         Segment;
+  UINTN                         Bus;
+  UINTN                         Device;
+  UINTN                         Function;
+
+  Bus      = 0;
+  Device   = 0;
+  Function = 0;
+
+  DEBUG ((EFI_D_INFO, "UpdateIgdOpRegionExitPmAuth\n"));
+
+  mIgdOpRegion.OpRegion->Header.PCON |= BIT8; //Set External Gfx Adapter field is valid
+  mIgdOpRegion.OpRegion->Header.PCON &= (UINT32) (~BIT7); //Assume No External Gfx Adapter 
+
+  ///
+  /// Get all PCI IO protocols handles
+  ///
+  Status = gBS->LocateHandleBuffer (
+                  ByProtocol,
+                  &gEfiPciIoProtocolGuid,
+                  NULL,
+                  &HandleCount,
+                  &HandleBuffer
+                  );
+
+  if (!EFI_ERROR (Status)) {
+    for (Index = 0; Index < HandleCount; Index++) {
+      ///
+      /// Get the PCI IO Protocol Interface corresponding to each handle
+      ///
+      Status = gBS->HandleProtocol (
+                      HandleBuffer[Index],
+                      &gEfiPciIoProtocolGuid,
+                      (VOID **) &PciIo
+                      );
+
+      if (!EFI_ERROR (Status)) {
+        ///
+        /// Read the PCI configuration space
+        ///
+        Status = PciIo->Pci.Read (
+                          PciIo,
+                          EfiPciIoWidthUint32,
+                          0,
+                          sizeof (Pci) / sizeof (UINT32),
+                          &Pci
+                          );
+
+        ///
+        /// Find the display controllers devices
+        ///
+        if (!EFI_ERROR (Status) && IS_PCI_DISPLAY (&Pci)) {
+          Status = PciIo->GetLocation (
+                            PciIo,
+                            &Segment,
+                            &Bus,
+                            &Device,
+                            &Function
+                            );
+
+          //
+          // Assumption: Onboard devices will be sits on Bus no 0, while external devices will be sits on Bus no > 0
+          //
+          if (!EFI_ERROR (Status) && (Bus > 0)) {
+            //External Gfx Adapter Detected and Available
+            DEBUG ((EFI_D_INFO, "PCON - External Gfx Adapter Detected and Available\n"));
+            mIgdOpRegion.OpRegion->Header.PCON |= BIT7;
+            break;
+		  }
+        }
+      }
+    }
+  }
+
+  ///
+  /// Free any allocated buffers
+  ///
+  if (HandleBuffer != NULL) {
+    FreePool (HandleBuffer);
+  }
+
+  ///
+  /// Return final status
+  ///
+  return Status;
+}
\ No newline at end of file
diff --git a/ReferenceCode/Chipset/SystemAgent/SaInit/Dxe/igdopregion.h b/ReferenceCode/Chipset/SystemAgent/SaInit/Dxe/igdopregion.h
new file mode 100644
index 0000000..085c665
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/SaInit/Dxe/igdopregion.h
@@ -0,0 +1,281 @@
+/** @file
+  This is part of the implementation of an Intel Graphics drivers OpRegion /
+  Software SCI interface between system BIOS, ASL code, and Graphics drivers.
+
+  Supporting Specifiction: OpRegion / Software SCI SPEC 0.70
+
+  Acronyms:
+    IGD:        Internal Graphics Device
+    NVS:        ACPI Non Volatile Storage
+    OpRegion:   ACPI Operational Region
+    VBT:        Video BIOS Table (OEM customizable data)
+
+@copyright
+  Copyright (c) 1999 - 2013 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement
+**/
+#ifndef _IGD_OPREGION_H_
+#define _IGD_OPREGION_H_
+
+///
+/// Statements that include other header files.
+///
+#include "EdkIIGlueDxe.h"
+#include "EfiScriptLib.h"
+#include "PchAccess.h"
+#include "PchPlatformLib.h"
+#include "SaAccess.h"
+#include "EfiMgmtModeRuntimeLib.h"
+#include "EfiApi.h"
+#include "pci22.h"
+
+///
+/// Driver Consumed Protocol Prototypes
+///
+#include EFI_GUID_DEFINITION (DataHubRecords)
+#include EFI_PROTOCOL_DEFINITION (SaPlatformPolicy)
+
+#include EFI_PROTOCOL_CONSUMER (PciIo)
+#include EFI_PROTOCOL_CONSUMER (PciRootBridgeIo)
+
+#include EFI_PROTOCOL_DEPENDENCY (CpuIo)
+#include EFI_PROTOCOL_DEPENDENCY (DataHub)
+#include EFI_PROTOCOL_DEPENDENCY (SaGlobalNvsArea)
+#include EFI_PROTOCOL_CONSUMER (ExitPmAuth)
+
+///
+/// Driver Produced Protocol Prototypes
+///
+#include EFI_PROTOCOL_PRODUCER (IgdOpRegion)
+
+///
+///
+/// OpRegion (Miscellaneous) #defines.
+///
+/// OpRegion Header #defines.
+///
+#define HEADER_SIGNATURE            "IntelGraphicsMem"
+#define HEADER_SIZE                 0x2000
+#define HEADER_OPREGION_VER         0x0200
+#define HEADER_OPREGION_REV         0x00
+#define HEADER_MBOX_SUPPORT         (HD_MBOX5 + HD_MBOX4 + HD_MBOX3 + HD_MBOX2 + HD_MBOX1)
+#define HEADER_MBOX_SUPPORT_MOBILE  HEADER_MBOX_SUPPORT
+#define HEADER_MBOX_SUPPORT_DESKTOP HEADER_MBOX_SUPPORT
+#define HD_MBOX1                    BIT0
+#define HD_MBOX2                    BIT1
+#define HD_MBOX3                    BIT2
+#define HD_MBOX4                    BIT3
+#define HD_MBOX5                    BIT4
+#define SVER_SIZE                   32
+
+///
+/// OpRegion Mailbox 1 EQUates.
+///
+/// OpRegion Mailbox 3 EQUates.
+///
+#define ALS_ENABLE            BIT0
+#define BLC_ENABLE            BIT1
+#define BACKLIGHT_BRIGHTNESS  0xFF
+#define FIELD_VALID_BIT       BIT31
+#define WORD_FIELD_VALID_BIT  BIT15
+#define PFIT_ENABLE           BIT2
+#define PFIT_OPRN_AUTO        0x00000000
+#define PFIT_OPRN_SCALING     0x00000007
+#define PFIT_OPRN_OFF         0x00000000
+#define PFIT_SETUP_AUTO       0
+#define PFIT_SETUP_SCALING    1
+#define PFIT_SETUP_OFF        2
+#define INIT_BRIGHT_LEVEL     0x64
+#define PFIT_STRETCH          6
+
+///
+/// GMCH PCI register access #defines.
+///
+#define IgdMmPci32(Register)            MmPci32 (0, SA_IGD_BUS, SA_IGD_DEV, SA_IGD_FUN_0, Register)
+#define IgdMmPci16Or(Register, OrData)  MmPci16Or (0, SA_IGD_BUS, SA_IGD_DEV, SA_IGD_FUN_0, Register, OrData)
+#define IgdMmPci16AndThenOr(Register, AndData, OrData) \
+  MmPci16AndThenOr ( \
+  0, \
+  SA_IGD_BUS, \
+  SA_IGD_DEV, \
+  SA_IGD_FUN_0, \
+  Register, \
+  AndData, \
+  OrData \
+  )
+
+///
+/// Video BIOS / VBT #defines
+///
+#define OPTION_ROM_SIGNATURE    0xAA55
+#define VBIOS_LOCATION_PRIMARY  0xC0000
+
+#define VBT_SIGNATURE           EFI_SIGNATURE_32 ('$', 'V', 'B', 'T')
+///
+/// Typedef stuctures
+///
+#pragma pack(1)
+typedef struct {
+  UINT16  Signature;  /// 0xAA55
+  UINT8   Size512;
+  UINT8   Reserved[21];
+  UINT16  PcirOffset;
+  UINT16  VbtOffset;
+} INTEL_VBIOS_OPTION_ROM_HEADER;
+#pragma pack()
+
+#pragma pack(1)
+typedef struct {
+  UINT32  Signature;  /// "PCIR"
+  UINT16  VendorId;   /// 0x8086
+  UINT16  DeviceId;
+  UINT16  Reserved0;
+  UINT16  Length;
+  UINT8   Revision;
+  UINT8   ClassCode[3];
+  UINT16  ImageLength;
+  UINT16  CodeRevision;
+  UINT8   CodeType;
+  UINT8   Indicator;
+  UINT16  Reserved1;
+} INTEL_VBIOS_PCIR_STRUCTURE;
+#pragma pack()
+
+#pragma pack(1)
+typedef struct {
+  UINT8   HeaderSignature[20];
+  UINT16  HeaderVersion;
+  UINT16  HeaderSize;
+  UINT16  HeaderVbtSize;
+  UINT8   HeaderVbtCheckSum;
+  UINT8   HeaderReserved;
+  UINT32  HeaderOffsetVbtDataBlock;
+  UINT32  HeaderOffsetAim1;
+  UINT32  HeaderOffsetAim2;
+  UINT32  HeaderOffsetAim3;
+  UINT32  HeaderOffsetAim4;
+  UINT8   DataHeaderSignature[16];
+  UINT16  DataHeaderVersion;
+  UINT16  DataHeaderSize;
+  UINT16  DataHeaderDataBlockSize;
+  UINT8   CoreBlockId;
+  UINT16  CoreBlockSize;
+  UINT16  CoreBlockBiosSize;
+  UINT8   CoreBlockBiosType;
+  UINT8   CoreBlockReleaseStatus;
+  UINT8   CoreBlockHWSupported;
+  UINT8   CoreBlockIntegratedHW;
+  UINT8   CoreBlockBiosBuild[4];
+  UINT8   CoreBlockBiosSignOn[155];
+} VBIOS_VBT_STRUCTURE;
+#pragma pack()
+///
+/// Driver Private Function definitions
+///
+EFI_STATUS
+GetSVER (
+  OUT UINT8 *SVER
+  )
+/**
+  Set the SVER (system BIOS ID) string with the system BIOS build number.
+
+  @param[in] SVER  String to populate with system BIOS build number.
+
+  @retval EFI_SUCCESS     The SVER string is populated.
+  @exception EFI_UNSUPPORTED The SVER string is not populated.
+**/
+;
+
+EFI_STATUS
+GetStringFromToken (
+  IN      EFI_GUID                  *ProducerGuid,
+  IN      STRING_REF                Token,
+  OUT     CHAR16                    **String
+  )
+/**
+  Acquire the string associated with the ProducerGuid and return it.
+
+  @param[in] ProducerGuid - The Guid to search the HII database for
+  @param[in] Token - The token value of the string to extract
+  @param[in] String - The string that is extracted
+
+  @retval EFI_SUCCESS       The function completed successfully
+  @retval EFI_NOT_FOUND     The requested string was not found
+**/
+;
+
+EFI_STATUS
+IgdOpRegionInit (
+  void
+  )
+/**
+  Graphics OpRegion / Software SCI driver installation function.
+
+  @param[in] void         - None
+  @retval EFI_SUCCESS     - The driver installed without error.
+  @retval EFI_ABORTED     - The driver encountered an error and could not complete
+                            installation of the ACPI tables.
+**/
+;
+
+EFI_STATUS
+ExtractDataFromHiiHandle (
+  IN      EFI_HII_HANDLE      HiiHandle,
+  IN OUT  UINT16              *ImageLength,
+  OUT     UINT8               *DefaultImage,
+  OUT     EFI_GUID            *Guid
+  )
+/**
+  Extract information pertaining to the HiiHandle
+
+  @param[in] HiiHandle       - Hii handle
+  @param[in] ImageLength     - For input, length of DefaultImage;
+                    For output, length of actually required
+  @param[in] DefaultImage    - Image buffer prepared by caller
+  @param[in] Guid            - Guid information about the form
+
+  @retval EFI_OUT_OF_RESOURCES    - No enough buffer to allocate
+  @retval EFI_BUFFER_TOO_SMALL    - DefualtImage has no enough ImageLength
+  @retval EFI_SUCCESS             - Successfully extract data from Hii database.
+**/
+;
+
+EFI_STATUS
+GetVBiosVbtExitPmAuth (
+  VOID
+  )
+/**
+  Get Intel video BIOS VBT information (i.e. Pointer to VBT and VBT size).
+  The VBT (Video BIOS Table) is a block of customizable data that is built
+  within the video BIOS and edited by customers.
+
+  @retval EFI_SUCCESS            - Video BIOS VBT information returned.
+  @exception EFI_UNSUPPORTED     - Could not find VBT information (*VBiosVbtPtr = NULL).
+**/
+;
+
+EFI_STATUS
+UpdateIgdOpRegionExitPmAuth (
+  VOID
+  )
+/**
+  Update Graphics OpRegion after PCI enumeration.
+
+  @param[in] void         - None
+  @retval EFI_SUCCESS     - The function completed successfully.
+**/
+;
+#endif
diff --git a/ReferenceCode/Chipset/SystemAgent/SaInit/Pei/GraphicsInit.c b/ReferenceCode/Chipset/SystemAgent/SaInit/Pei/GraphicsInit.c
new file mode 100644
index 0000000..ab08eb3
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/SaInit/Pei/GraphicsInit.c
@@ -0,0 +1,929 @@
+/** @file
+  PEIM to initialize both IGD, PEG and PCI graphics card.
+
+@copyright
+  Copyright (c) 1999 - 2013 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement
+
+**/
+#include "GraphicsInit.h"
+#include "CpuIA32.h"
+#include <Token.h>
+#define IGD_ENABLE  1
+#define IGD_DISABLE 0
+
+/**
+  GraphicsInit: Initialize the IGD if no other external graphics is present
+
+  @param[in] PeiServices          - Pointer to the PEI services table
+  @param[in] SaPlatformPolicyPpi  - SaPlatformPolicyPpi to access the GtConfig related information
+**/
+VOID
+GraphicsInit (
+  IN EFI_PEI_SERVICES                **PeiServices,
+  IN SA_PLATFORM_POLICY_PPI          *SaPlatformPolicyPpi
+  )
+{
+  DISPLAY_DEVICE  PrimaryDisplay;
+  UINT8           GMSData;
+  UINT32          PciMmioLength;
+  UINT32          PchPcieMmioLength;
+  UINT32          PegMmioLength;
+  UINT32          IGfxMmioLength;
+  UINT32          TotalMmioLength;
+  BOOLEAN         IGfxSupported;
+  UINT32          LoGTBaseAddress;
+  UINT32          HiGTBaseAddress;
+  UINT32          RegOffset;
+  UINT32          Data32And;
+  UINT32          Data32Or;
+  UINT32          Data32Mask;
+  UINT32          Result;
+  PEI_STALL_PPI   *StallPpi;
+  EFI_STATUS      Status;
+  UINT64          GttMmAdr;
+  UINTN           MchBarBase;
+  CPU_FAMILY      CpuFamilyId;
+
+  PciMmioLength     = 0;
+  PchPcieMmioLength = 0;
+  PegMmioLength     = 0;
+  IGfxMmioLength    = 0;
+  GttMmAdr          = 0;
+  MchBarBase        = McD0PciCfg32 (0x48) &~BIT0;
+  CpuFamilyId       = GetCpuFamily();
+
+  ///
+  /// Set the VGA Decode bits to a good known starting point where both PEG and
+  /// IGD VGA Decode Bits are both disabled.
+  ///
+  McD0PciCfg16Or (R_SA_GGC, B_SA_GGC_IVD_MASK);
+  PrimaryDisplay = IGD;
+
+  ///
+  /// Check if IGfx is supported
+  ///
+  IGfxSupported = (BOOLEAN) (McD2PciCfg16 (R_SA_IGD_VID) != 0xFFFF);
+
+  ///
+  /// Check external VGA devices
+  ///
+  CheckOffboardPcieVga (PeiServices, &PchPcieMmioLength, &PrimaryDisplay);
+  CheckAndInitializePegVga (
+    PeiServices,
+    SaPlatformPolicyPpi->PcieConfig->AlwaysEnablePeg,
+    &PrimaryDisplay,
+    SaPlatformPolicyPpi->GtConfig->PrimaryDisplay,
+    &PegMmioLength
+    );
+
+  ///
+  /// Temporarily program GttMmAdr
+  ///
+  GttMmAdr = SaPlatformPolicyPpi->GtConfig->GttMmAdr;
+  
+  ///
+  /// Program GttMmAdr 
+  ///
+  LoGTBaseAddress = (UINT32) (GttMmAdr & 0xFFFFFFFF);
+  HiGTBaseAddress = (UINT32) RShiftU64 ((GttMmAdr & 0xFFFFFFFF00000000), 32);
+  McD2PciCfg32 (R_SA_IGD_GTTMMADR)     = LoGTBaseAddress | BIT2;
+  McD2PciCfg32 (R_SA_IGD_GTTMMADR + 4) = HiGTBaseAddress;
+
+  ///
+  /// Enable Bus Master and Memory access on 0:2:0
+  ///
+  McD2PciCfg16Or (R_SA_IGD_CMD, (BIT2 | BIT1));
+
+  ///
+  /// If primary display device is IGD or no other display detected then enable IGD
+  ///
+  if (IGfxSupported &&
+      (
+        (
+        ((PrimaryDisplay == IGD) || (SaPlatformPolicyPpi->GtConfig->PrimaryDisplay == IGD)) &&
+      (SaPlatformPolicyPpi->GtConfig->InternalGraphics != IGD_DISABLE)
+    ) || (SaPlatformPolicyPpi->GtConfig->InternalGraphics == IGD_ENABLE)
+    )
+      ) {
+
+    DEBUG ((EFI_D_INFO, "IGD enabled.\n"));
+
+    ///
+    /// Program GFX Memory by setting D0.F0.R 050h [7:3]
+    ///
+    McD0PciCfg16And (R_SA_GGC, ~(B_SA_GGC_GMS_MASK));
+
+    GMSData = SaPlatformPolicyPpi->GtConfig->IgdDvmt50PreAlloc;
+
+    McD0PciCfg8Or (R_SA_GGC, (GMSData << N_SA_GGC_GMS_OFFSET));
+
+    ///
+    /// Program Graphics GTT Memory D0:F0:R50h[9:8] = 10b => 2MB of GTT
+    ///
+    McD0PciCfg16AndThenOr (R_SA_GGC, ~(B_SA_GGC_GGMS_MASK), 1 << (N_SA_GGC_GGMS_OFFSET + 1));
+
+    ///
+    /// Set register D2.F0.R 062h [2:1] = `01b' to set a 256MByte aperture.
+    /// This must be done before Device 2 registers are enumerated.
+    ///
+    if (SaPlatformPolicyPpi->GtConfig->ApertureSize == APERTURE_SIZE_128MB) {
+      McD2PciCfg8And (R_SA_IGD_MSAC_OFFSET, ~(BIT2 + BIT1));
+    } else if (SaPlatformPolicyPpi->GtConfig->ApertureSize == APERTURE_SIZE_256MB) {
+      McD2PciCfg8AndThenOr (R_SA_IGD_MSAC_OFFSET, ~(BIT2 + BIT1), BIT1);
+    } else {
+      McD2PciCfg8Or (R_SA_IGD_MSAC_OFFSET, (BIT2 + BIT1));
+    }
+    ///
+    /// Enable IGD VGA Decode.  This is needed so the Class Code will
+    /// be correct for the IGD Device when determining which device
+    /// should be primary.  If disabled, IGD will show up as a non VGA device.
+    ///
+    if ((SaPlatformPolicyPpi->GtConfig->PrimaryDisplay != IGD) && (PrimaryDisplay != IGD)) {
+      ///
+      /// If IGD is forced to be enabled, but is a secondary display, disable IGD VGA Decode
+      ///
+      McD0PciCfg16Or (R_SA_GGC, B_SA_GGC_IVD_MASK);
+      DEBUG ((EFI_D_INFO, "IGD VGA Decode is disabled because it's not a primary display.\n"));
+    } else {
+      McD0PciCfg16And (R_SA_GGC, ~(B_SA_GGC_IVD_MASK));
+    }
+
+    FindPciDeviceMmioLength (0, 2, 0, &IGfxMmioLength);
+
+    if ((SaPlatformPolicyPpi->Revision >= SA_PLATFORM_POLICY_PPI_REVISION_12) && (SaPlatformPolicyPpi->GtConfig->PanelPowerEnable == 1)) {
+      ///
+      /// Panel Enable VDD bit
+      ///
+      Mmio32Or (GttMmAdr, 0xc7204, 0x8);
+    }
+  } else {
+
+    Status = (*PeiServices)->LocatePpi (PeiServices, &gPeiStallPpiGuid, 0, NULL, &StallPpi);
+    ASSERT_PEI_ERROR (PeiServices, Status);
+
+    if (CpuFamilyId == EnumCpuHswUlt) {
+      ///
+      /// For HSW ULT, Disable LCPLL
+      /// Set LCPLL_CTL (GTTMMADR Offset 0x130040) PLL_disable (Bit 31) to 1b to disable LCPLL.
+      /// Poll for LCPLL_CTL PLL_lock (Bit 30) = 0b to indicate LCPLL lost lock.Timeout and continue after 1 ms.
+      /// Set D_COMP COMP_DISABLE (MCHBAR offset 0x5F0C Bit 0)to 1b.
+      /// Wait > 100 ns for write to complete.
+      /// Poll for D_COMP RCOMP_IN_PROGRESS Bit 9 = 0b.Timeout and continue after 1 ms.
+      ///
+
+      RegOffset = 0x130040;
+      Data32And = 0xFFFFFFFF;
+      Data32Or  = BIT31;
+      Mmio32AndThenOr (GttMmAdr, RegOffset, Data32And, Data32Or);
+
+      if (IGfxSupported) {
+        Data32Mask = BIT30;
+        Result     = 0;
+        PollGtReady (PeiServices, StallPpi, GttMmAdr, RegOffset, Data32Mask, Result);
+      }
+
+      RegOffset = 0x5F0C;
+      Data32And = 0xFFFFFFFF;
+      Data32Or  = BIT0;
+      Mmio32AndThenOr (MchBarBase, RegOffset, Data32And, Data32Or);
+
+      ///
+      /// 1uSec wait
+      ///
+      StallPpi->Stall (PeiServices, StallPpi, 1);
+
+      if (IGfxSupported) {
+        Data32Mask = BIT9;
+        Result     = 0;
+        PollGtReady (PeiServices, StallPpi, MchBarBase, RegOffset, Data32Mask, Result);
+      }
+    }
+
+    DEBUG ((EFI_D_INFO, "Disable IGD Device.\n"));
+    ///
+    /// Disable IGD device
+    ///
+    /// Register D0:F0 Offset 50h [7:3] = '00000b'.
+    /// This prevents UMA memory from being pre-allocated to IGD.
+    /// Set D0:F0 Offset 50h [9:8] = '00b'.
+    /// GTT Graphics Memory Size to 0
+    /// Set VGA Disable (IVD) in D0:F0 Offset 50h [1] = '1b'.
+    ///
+    McD0PciCfg16AndThenOr (R_SA_GGC, ~(B_SA_GGC_GGMS_MASK | B_SA_GGC_GMS_MASK), B_SA_GGC_IVD_MASK);
+    SaPlatformPolicyPpi->GtConfig->GttSize            = 0;
+    SaPlatformPolicyPpi->GtConfig->IgdDvmt50PreAlloc  = 0;
+
+    ///
+    /// Disable IGD. D0.F0.R 054h [4] = '0b'.
+    ///
+    McD0PciCfg8And (R_SA_DEVEN, ~(B_SA_DEVEN_D2EN_MASK));
+  }
+
+  TotalMmioLength = PciMmioLength + PchPcieMmioLength + PegMmioLength + IGfxMmioLength;
+  DEBUG ((EFI_D_INFO, "TotalMmioLength:   0x%08X bytes\n", TotalMmioLength));
+
+  ///
+  /// Disable Bus Master and Memory access on 0:2:0 and clear GTTMMADR
+  ///
+  McD2PciCfg16And (R_SA_IGD_CMD, ~(BIT2 | BIT1));
+  McD2PciCfg32And (R_SA_IGD_GTTMMADR, 0x0);
+  McD2PciCfg32And (R_SA_IGD_GTTMMADR + 0x4, 0x0);
+
+  ///
+  /// Determine MMIO Size for Dynamic Tolud
+  ///
+  if (SaPlatformPolicyPpi->MemConfig->MaxTolud == 0x00) {
+    ///
+    /// if total MMIO need 1GB or over
+    ///
+    if (TotalMmioLength >= 0x40000000) {
+      SaPlatformPolicyPpi->GtConfig->MmioSize = 0x800;
+    }
+    ///
+    /// if total MMIO need 728MB~1GB
+    ///
+    else if (TotalMmioLength >= 0x30000000) {
+      SaPlatformPolicyPpi->GtConfig->MmioSize = 0x700;
+    }
+    ///
+    /// if total MMIO need 512MB~728MB
+    ///
+    else if (TotalMmioLength >= 0x20000000) {
+      SaPlatformPolicyPpi->GtConfig->MmioSize = 0x600;
+    }
+    ///
+    /// if total MMIO need 256MB~512MB
+    ///
+    else if (TotalMmioLength >= 0x10000000) {
+      SaPlatformPolicyPpi->GtConfig->MmioSize = 0x500;
+    }
+    ///
+    /// if total MMIO need less than 256MB
+    ///
+    else {
+      SaPlatformPolicyPpi->GtConfig->MmioSize = 0x400;
+    }
+  }
+}
+
+/**
+  CheckAndInitializePegVga:  Check if PEG card is present and configure accordingly
+
+  @param[in] PeiServices             - Pointer to the PEI services table
+  @param[in] AlwaysEnablePeg         - 0 - Peg is not always enabled.
+  @param[in, out] PrimaryDisplay     - Primary Display - default is IGD
+  @param[in] PrimaryDisplaySelection - Primary display selection from BIOS Setup
+  @param[in, out] PegMmioLength      - Total PEG MMIO length on all PEG ports
+**/
+VOID
+CheckAndInitializePegVga (
+  IN     EFI_PEI_SERVICES                   **PeiServices,
+  IN     UINT8                              AlwaysEnablePeg,
+  IN OUT DISPLAY_DEVICE                     *PrimaryDisplay,
+  IN     UINT8                              PrimaryDisplaySelection,
+  IN OUT UINT32                             *PegMmioLength
+  )
+{
+  UINT8     ClassCode;
+  BOOLEAN   IgdPresent;
+  UINT8     PegBus;
+  UINT8     PegDev;
+  UINT8     PegFunc;
+  UINT16    PegDevenReg;
+  UINT8     PegComplete;
+  UINT16    PegEnable;
+  BOOLEAN   CardDetect;
+  UINT32    MmioLength;
+  UINT8     Func;
+  UINT8     MaxFunction;
+  UINT8     HeaderType;
+  UINT8     PegVgaFunc;
+
+  PEG_DEVEN PegDevenTable[] = {
+    ///
+    ///  Bus, Device, Function, DevenMask
+    ///
+    {
+      SA_PEG_BUS_NUM,
+      SA_PEG10_DEV_NUM,
+      SA_PEG10_FUN_NUM,
+      BIT3
+    }
+// AMI_OVERRID >>
+#if RC_PEG_1 == 1
+,
+    {
+      SA_PEG_BUS_NUM,
+      SA_PEG11_DEV_NUM,
+      SA_PEG11_FUN_NUM,
+      BIT2
+    }
+#endif
+#if RC_PEG_2 == 1
+,
+    {
+      SA_PEG_BUS_NUM,
+      SA_PEG12_DEV_NUM,
+      SA_PEG12_FUN_NUM,
+      BIT1
+    }
+#endif
+// AMI_OVERRID <<
+  };
+
+  MmioLength = 0;
+  CardDetect = FALSE;
+  PegVgaFunc = 0xFF;
+
+  ///
+  /// Read the DEVEN register for PEG0/1/2 controllers configuration
+  ///
+  PegDevenReg = MmPci16 (0, SA_MC_BUS, 0, 0, R_SA_DEVEN) & (BIT3 + BIT2 + BIT1);
+
+  ///
+  /// If IGD is disabled
+  /// or not present IgdPresent is set to false
+  ///
+  if (McD2PciCfg16 (PCI_VID) == 0xFFFF) {
+    IgdPresent = FALSE;
+  } else {
+    IgdPresent = TRUE;
+  }
+  ///
+  /// Scan PEG device vs DEVEN register for PEG controllers configuration
+  ///
+  for (PegComplete = 0; PegComplete < ((sizeof (PegDevenTable)) / (sizeof (PEG_DEVEN))); PegComplete++) {
+
+    PegBus    = PegDevenTable[PegComplete].Bus;
+    PegDev    = PegDevenTable[PegComplete].Device;
+    PegFunc   = PegDevenTable[PegComplete].Function;
+    PegEnable = PegDevenTable[PegComplete].DevenMask;
+
+    if ((PegDevenReg & PegEnable) == 0) {
+      continue;
+    }
+    ///
+    /// Check for a card presence in the PEG slot.
+    /// We don't know if it's a graphics card yet.
+    ///
+    if ((MmPci8 (0, PegBus, PegDev, PegFunc, R_SA_PEG_SLOTSTS_OFFSET) & BIT6) == 0) {
+      continue;
+    }
+    ///
+    /// Set PEG PortBus = 1 to Read Endpoint.
+    ///
+    MmPci32AndThenOr (0, PegBus, PegDev, PegFunc, PCI_PBUS, 0xFF0000FF, 0x00010100);
+
+    ///
+    /// A config write is required in order for the device to re-capture the Bus number,
+    /// according to PCI Express Base Specification, 2.2.6.2
+    /// Write to a read-only register VendorID to not cause any side effects.
+    ///
+    MmPci16 (0, 1, 0, 0, PCI_VID) = 0;
+
+    ///
+    /// Read Vendor ID to check if endpoint exists
+    /// if no device exists, then check next device
+    ///
+    if (MmPci16 (0, 1, 0, 0, PCI_VID) == 0xFFFF) {
+      continue;
+    }
+    ///
+    /// Check for a multifunction device
+    ///
+    HeaderType = MmPci8 (0, 1, 0, 0, PCI_HEADER_TYPE_OFFSET);
+    if ((HeaderType & HEADER_TYPE_MULTI_FUNCTION) != 0) {
+      MaxFunction = 7;
+    } else {
+      MaxFunction = 0;
+    }
+    ///
+    /// Calculate total PEG MMIO length on all functions of the endpoint
+    ///
+    for (Func = 0; Func <= MaxFunction; Func++) {
+      if (MmPci16 (0, 1, 0, Func, PCI_VID) == 0xFFFF) {
+        continue;
+      }
+
+      FindPciDeviceMmioLength (1, 0, Func, &MmioLength);
+      *PegMmioLength += MmioLength;
+    }
+    ///
+    /// Perform PEG Endpoint Class Code Check.  If the Endpoint Class Code is
+    /// not GFX, then the Port is being used as a standard PCI Express Port.
+    ///
+    ClassCode = MmPci8 (0, 1, 0, 0, PCI_BCC);
+    if (ClassCode == 0x03) {
+      ///
+      /// Disable PEG if IGD or PCI VGA take precedence.
+      ///
+      if (AlwaysEnablePeg == 0) {
+        ///
+        /// If IGD is present and selected as primary, skip the PEG VGA enabling
+        ///
+        if (IgdPresent && (PrimaryDisplaySelection == IGD)) {
+          MmPci32And (0, PegBus, PegDev, PegFunc, PCI_PBUS, 0xFF0000FF);
+          continue;
+        }
+        ///
+        /// If PCI video card was detected, skip the PEG VGA enabling
+        ///
+        if (*PrimaryDisplay == PCI) {
+          MmPci32And (0, PegBus, PegDev, PegFunc, PCI_PBUS, 0xFF0000FF);
+          continue;
+        }
+      }
+      ///
+      /// Enable PEG video and Execute 16-bit address decodes on VGA I/O accesses
+      ///
+      /// Check if PEG VGA already detected
+      ///
+      if (*PrimaryDisplay != PEG) {
+        MmPci16Or (0, PegBus, PegDev, PegFunc, R_SA_PEG_BCTRL_OFFSET, (BIT3 + BIT4));
+        *PrimaryDisplay = PEG;
+        PegVgaFunc = PegFunc;
+        DEBUG ((EFI_D_INFO, "PCIe card on PEG%x%x (%x:%x:%x) enabled as VGA.\n", PegDev, PegFunc, PegBus, PegDev, PegFunc));
+      }
+    }
+
+    if (ClassCode == 0x06) {
+      CardDetect = EnumerateBridgeDevice (PegBus, PegDev, PegFunc, PegMmioLength);
+      if (CardDetect == TRUE) {
+        ///
+        /// Check if PEG VGA already detected
+        ///
+        if (*PrimaryDisplay != PEG) {
+          MmPci16Or (0, PegBus, PegDev, PegFunc, R_SA_PEG_BCTRL_OFFSET, (BIT3 + BIT4));
+          *PrimaryDisplay = PEG;
+          PegVgaFunc = PegFunc;
+          DEBUG ((EFI_D_INFO, "PCIe card on PEG%x%x (%x:%x:%x) enabled as VGA.\n", PegDev, PegFunc, PegBus, PegDev, PegFunc));
+        }
+      }
+    }
+    ///
+    /// Restore bus numbers on the PEG bridge.
+    ///
+    MmPci32And (0, PegBus, PegDev, PegFunc, PCI_PBUS, 0xFF0000FF);
+  } // End of the for Loop
+
+  ///
+  /// If a PEG device is used for primary graphics, set the ISAEN bit on all other PEG ports.
+  ///
+  if (PegVgaFunc != 0xFF) {
+    for (PegComplete = 0; PegComplete < ((sizeof (PegDevenTable)) / (sizeof (PEG_DEVEN))); PegComplete++) {
+      if (PegVgaFunc == PegComplete) {
+        continue;
+      }
+      PegBus    = PegDevenTable[PegComplete].Bus;
+      PegDev    = PegDevenTable[PegComplete].Device;
+      PegFunc   = PegDevenTable[PegComplete].Function;
+      MmPci16Or (0, PegBus, PegDev, PegFunc, R_SA_PEG_BCTRL_OFFSET, BIT2);
+      DEBUG ((EFI_D_INFO, "PEG%x%x (%x:%x:%x) ISAEN has been set.\n", PegDev, PegFunc, PegBus, PegDev, PegFunc));
+    }
+  }
+}
+
+/**
+  Find the MMIO size that a given PCI device requires
+
+  @param[in] BusNum     - Bus number of the device
+  @param[in] DevNum     - device Number of the device
+  @param[in] FunNum     - Function number of the device
+  @param[out] MmioLength - MMIO Length in bytes
+**/
+VOID
+FindPciDeviceMmioLength (
+  IN UINT32  BusNum,
+  IN UINT32  DevNum,
+  IN UINT32  FunNum,
+  OUT UINT32 *MmioLength
+  )
+{
+  UINT32  CurrentMmioLength;
+  UINT32  SavedBAR;
+  UINT32  i;
+  UINT64  BarAlign;
+  UINT8   ClassCode;
+
+  *MmioLength = 0;
+  BarAlign    = PCI_BAR_OLD_ALIGN;
+
+  ClassCode   = MmPci8 (0, BusNum, DevNum, FunNum, PCI_BCC);
+  if (ClassCode == PCI_CLASS_BRIDGE) {
+    return ;
+  }
+
+  for (i = PCI_BAR0; i <= PCI_BAR5; i += 4) {
+    SavedBAR = MmPci32 (0, BusNum, DevNum, FunNum, i);
+    ///
+    /// Check BAR is read-only or not
+    ///
+    MmPci32And (0, BusNum, DevNum, FunNum, i, (UINT32) PCI_BAR_NOCHANGE);
+    MmPci32Or (0, BusNum, DevNum, FunNum, i, BarAlign);
+    if (SavedBAR == MmPci32 (0, BusNum, DevNum, FunNum, i)) {
+      ///
+      /// Restore BAR as original value
+      ///
+      MmPci32 (0, BusNum, DevNum, FunNum, i) = SavedBAR;
+      continue;
+    }
+    ///
+    /// If BAR is not memory map, skip it
+    ///
+    if ((SavedBAR & BIT0) != 0) {
+      ///
+      /// Restore BAR as original value
+      ///
+      MmPci32 (0, BusNum, DevNum, FunNum, i) = SavedBAR;
+      continue;
+    }
+    ///
+    /// Calculate the MMIO length through BAR
+    ///
+    CurrentMmioLength = ~(MmPci32 (0, BusNum, DevNum, FunNum, i) &~0xF) + 1;
+    *MmioLength += CurrentMmioLength;
+
+    ///
+    /// Restore BAR as original value
+    ///
+    MmPci32 (0, BusNum, DevNum, FunNum, i) = SavedBAR;
+    ///
+    /// Skip next index if BAR is 64bit address
+    ///
+    if ((SavedBAR & (BIT1 + BIT2)) == 0x4) {
+      i += 4;
+    }
+  }
+}
+
+/**
+  CheckOffboardPcieVga: Check if off board PCIe graphics Card is present
+
+  @param[in] PeiServices             - Pointer to the PEI services table
+  @param[in, out] PchPcieMmioLength  - Total PCIe MMIO length on all PCH root ports
+  @param[in, out] PrimaryDisplay     - Primary Display - default is IGD
+**/
+VOID
+CheckOffboardPcieVga (
+  IN     EFI_PEI_SERVICES     **PeiServices,
+  IN OUT UINT32               *PchPcieMmioLength,
+  IN OUT DISPLAY_DEVICE       *PrimaryDisplay
+  )
+{
+  UINT8   PortNo;
+  UINT32  PcieBusNum;
+  UINT8   Bus;
+  UINT8   Dev;
+  UINT8   Func;
+  UINT8   MaxFunction;
+  UINT8   SubBusNum;
+  UINT8   HeaderType;
+  UINT16  Buffer16;
+  BOOLEAN CardDetect;
+  UINT32  MmioLength;
+
+  MmioLength = 0;
+
+  ///
+  /// Initialize Secondary and Subordinate bus number for first Pcie root port
+  ///
+  PcieBusNum  = 0x00010100;
+
+  SubBusNum   = 0;
+
+  CardDetect  = FALSE;
+
+  for (PortNo = 0; PortNo < GetPchMaxPciePortNum (); PortNo++) {
+    ///
+    /// Check if root port exists
+    ///
+    if (MmPci16 (0, 0, 0x1C, PortNo, PCI_VID) == 0xFFFF) {
+      continue;
+    }
+
+    MmPci32 (0, 0, 0x1c, PortNo, PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET)  = PcieBusNum;
+    Bus = MmPci8 (0, 0, 0x1c, PortNo, PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET);
+
+    ///
+    /// Assign temporary subordinate bus number so that device this bridge can be seen
+    ///
+    MmPci8 (0, 0, 0x1c, PortNo, PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET) = 0xFF;
+
+    ///
+    /// A config write is required in order for the device to re-capture the Bus number,
+    /// according to PCI Express Base Specification, 2.2.6.2
+    /// Write to a read-only register VendorID to not cause any side effects.
+    ///
+    MmPci16 (0, Bus, 0, 0, PCI_VID) = 0;
+
+    SubBusNum                       = EnumerateDownstream (Bus);
+    ///
+    /// Update the actual subordinate bus number
+    ///
+    MmPci8 (0, 0, 0x1c, PortNo, PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET) = SubBusNum;
+    PcieBusNum = (SubBusNum + 1) << 8;
+  }
+
+  for (Bus = 1; Bus <= SubBusNum; Bus++) {
+    for (Dev = 0; Dev < 32; Dev++) {
+      ///
+      /// Read Vendor ID to check if device exists
+      /// if no device exists, then check next device
+      ///
+      if (MmPci16 (0, Bus, Dev, 0, PCI_VID) == 0xFFFF) {
+        continue;
+      }
+      ///
+      /// Check for a multifunction device
+      ///
+      HeaderType = MmPci8 (0, Bus, Dev, 0, PCI_HDR);
+      if ((HeaderType & HEADER_TYPE_MULTI_FUNCTION) != 0) {
+        MaxFunction = 7;
+      } else {
+        MaxFunction = 0;
+      }
+
+      for (Func = 0; Func <= MaxFunction; Func++) {
+        if (MmPci16 (0, Bus, Dev, Func, PCI_VID) == 0xFFFF) {
+          continue;
+        }
+
+        FindPciDeviceMmioLength (Bus, Dev, Func, &MmioLength);
+        *PchPcieMmioLength += MmioLength;
+
+        ///
+        /// Video cards can have Base Class 0 with Sub-class 1
+        /// or Base Class 3.
+        ///
+        if (MmPci16 (0, Bus, Dev, Func, PCI_SCC) == 0x0300) {
+          if (CardDetect != TRUE) {
+            *PrimaryDisplay = PCI;
+            DEBUG ((EFI_D_INFO, "PCH PCIe Graphics Card enabled.\n"));
+            CardDetect = TRUE;
+          }
+        }
+      }
+    }
+  }
+  ///
+  /// Clear bus number on all the bridges that we have opened so far.
+  /// We have to do it in the reverse Bus number order.
+  ///
+  for (Bus = SubBusNum; Bus >= 1; Bus--) {
+    for (Dev = 0; Dev < 32; Dev++) {
+      ///
+      /// Read Vendor ID to check if device exists
+      /// if no device exists, then check next device
+      ///
+      if (MmPci16 (0, Bus, Dev, 0, PCI_VID) == 0xFFFF) {
+        continue;
+      }
+
+      Buffer16 = MmPci16 (0, Bus, Dev, 0, PCI_SCC);
+      ///
+      /// Clear Bus Number for PCI/PCI Bridge Device
+      ///
+      if (Buffer16 == 0x0604) {
+        MmPci32 (0, Bus, Dev, 0, PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET) = 0;
+      }
+    }
+  }
+
+  for (PortNo = 0; PortNo < GetPchMaxPciePortNum (); PortNo++) {
+    ///
+    /// Clear bus numbers so that PCIe slots are hidden
+    ///
+    MmPci32 (0, 0, 0x1c, PortNo, PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET) = 0;
+  }
+}
+
+/**
+  This function enumerate all downstream bridge.
+
+  @param[in] BusNum  - Primary bus number of current bridge.
+
+  @retval BusNum: return current bus number if current bus is an enpoint device.
+  @retval SubBus: return subordinate bus number if current bus is a bridge.
+**/
+UINT8
+EnumerateDownstream (
+  IN UINT8  BusNum
+  )
+{
+  UINT8   DevNum;
+  UINT16  Buffer16;
+  UINT8   SubBus;
+  UINT8   SecBus;
+
+  SubBus  = 0;
+
+  SecBus  = BusNum;
+
+  for (DevNum = 0; DevNum < 32; DevNum++) {
+    ///
+    /// Read Vendor ID to check if device exists
+    /// if no device exists, then check next device
+    ///
+    if (MmPci16 (0, BusNum, DevNum, 0, PCI_VID) == 0xFFFF) {
+      continue;
+    }
+
+    Buffer16 = MmPci16 (0, BusNum, DevNum, 0, PCI_SCC);
+    ///
+    /// Check for PCI/PCI Bridge Device Base Class 6 with subclass 4
+    ///
+    if (Buffer16 == 0x0604) {
+      SecBus++;
+      MmPci8 (0, BusNum, DevNum, 0, PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET)   = BusNum;
+      MmPci8 (0, BusNum, DevNum, 0, PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET) = SecBus;
+      ///
+      /// Assign temporary subordinate bus number so that device behind this bridge can be seen
+      ///
+      MmPci8 (0, BusNum, DevNum, 0, PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET) = 0xFF;
+
+      ///
+      /// A config write is required in order for the device to re-capture the Bus number,
+      /// according to PCI Express Base Specification, 2.2.6.2
+      /// Write to a read-only register VendorID to not cause any side effects.
+      ///
+      MmPci16 (0, SecBus, 0, 0, PCI_VID) = 0;
+
+      ///
+      /// Enumerate bus behind this bridge by calling this funstion recursively
+      ///
+      SubBus = EnumerateDownstream (SecBus);
+      ///
+      /// Update the correct subordinate bus number
+      ///
+      MmPci8 (0, BusNum, DevNum, 0, PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET) = SubBus;
+      SecBus = SubBus;
+    }
+  }
+
+  if (SubBus == 0) {
+    return BusNum;
+  } else {
+    return SubBus;
+  }
+}
+
+/**
+  This function enumerate the bridge on the device
+
+  @param[in] PegBus  - Particular Bus number
+  @param[in] PegDev  - Particular Device number
+  @param[in] PegFunc  - Particular Func number
+  @param[in, out] PegMmioLength - PEG MMIO length
+
+  @retval CardDetect : TRUE if current bridge device has a Graphics card.
+  @retval CardDetect : FALSE if current bridge device has no Graphics card.
+**/
+BOOLEAN
+EnumerateBridgeDevice (
+  IN UINT8      PegBus,
+  IN UINT8      PegDev,
+  IN UINT8      PegFunc,
+  IN OUT UINT32 *PegMmioLength
+  )
+{
+
+  UINT8   Bus;
+  UINT8   Dev;
+  UINT8   SubBusNum;
+  UINT16  Buffer16;
+  BOOLEAN CardDetect;
+
+  CardDetect = FALSE;
+
+  ///
+  /// Temporarily program the secondary and subordinate bus numbers
+  /// of PEG bridge to (1, 0xFF) so that devices behind the bridge can be seen
+  ///
+  Bus = 1;
+  MmPci8 (0, PegBus, PegDev, PegFunc, PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET)   = Bus;
+  MmPci8 (0, PegBus, PegDev, PegFunc, PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET) = 0xFF;
+
+  ///
+  /// A config write is required in order for the device to re-capture the Bus number,
+  /// according to PCI Express Base Specification, 2.2.6.2
+  /// Write to a read-only register VendorID to not cause any side effects.
+  ///
+  MmPci16 (0, Bus, 0, 0, PCI_VID) = 0;
+
+  SubBusNum                       = EnumerateDownstream (Bus);
+
+  for (Bus = 1; Bus <= SubBusNum; Bus++) {
+    for (Dev = 0; Dev < 32; Dev++) {
+      ///
+      /// Read Vendor ID to check if device exists
+      /// if no device exists, then check next device
+      ///
+      if (MmPci16 (0, Bus, Dev, 0, PCI_VID) == 0xFFFF) {
+        continue;
+
+      }
+      ///
+      /// Video cards can have Base Class 0 with Sub-class 1
+      /// or Base Class 3.
+      ///
+      if (MmPci16 (0, Bus, Dev, 0, PCI_SCC) == 0x0300) {
+        FindPciDeviceMmioLength (Bus, Dev, 0, PegMmioLength);
+        CardDetect = TRUE;
+        break;
+      }
+    }
+
+    if (CardDetect == TRUE) {
+      break;
+    }
+  }
+  ///
+  /// Clear bus number on all the bridges that we have opened so far.
+  /// We have to do it in the reverse Bus number order.
+  ///
+  for (Bus = SubBusNum; Bus >= 1; Bus--) {
+    for (Dev = 0; Dev < 32; Dev++) {
+      ///
+      /// Read Vendor ID to check if device exists
+      /// if no device exists, then check next device
+      ///
+      if (MmPci16 (0, Bus, Dev, 0, PCI_VID) == 0xFFFF) {
+        continue;
+      }
+
+      Buffer16 = MmPci16 (0, Bus, Dev, 0, PCI_SCC);
+      ///
+      /// Clear Bus Number for PCI/PCI Bridge Device
+      ///
+      if (Buffer16 == 0x0604) {
+        MmPci32 (0, Bus, Dev, 0, PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET) = 0;
+      }
+    }
+  }
+  ///
+  /// Clear the bus numbers on the PEG bridge
+  ///
+  MmPci32 (0, PegBus, PegDev, PegFunc, PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET) = 0;
+
+  return CardDetect;
+}
+
+/**
+
+  "Poll Status" for GT Readiness
+
+  @param[in] PeiServices     - Pointer to the PEI services table
+  @param[in] StallPpi        - Pointer to Stall PPI
+  @param[in] Base            - Base address of MMIO
+  @param[in] Offset          - MMIO Offset
+  @param[in] Mask            - Mask
+  @param[in] Result          - Value to wait for
+
+
+**/
+VOID
+PollGtReady (
+  IN EFI_PEI_SERVICES     **PeiServices,
+  IN PEI_STALL_PPI        *StallPpi,
+  UINT64 Base,
+  UINT32 Offset,
+  UINT32 Mask,
+  UINT32 Result
+  )
+{
+  UINT32  GtStatus;
+  UINT16  StallCount;
+
+  StallCount = 0;
+
+  ///
+  /// Register read
+  ///
+  GtStatus = Mmio32 (Base, Offset);
+
+  while (((GtStatus & Mask) != Result) && (StallCount < GT_WAIT_TIMEOUT)) {
+
+    GtStatus = Mmio32 (Base, Offset);
+    ///
+    /// 1mSec wait
+    ///
+    StallPpi->Stall (PeiServices, StallPpi, 1000);
+    StallCount = StallCount + 1;
+  }
+
+  ASSERT ((StallCount != GT_WAIT_TIMEOUT));
+}
diff --git a/ReferenceCode/Chipset/SystemAgent/SaInit/Pei/GraphicsInit.h b/ReferenceCode/Chipset/SystemAgent/SaInit/Pei/GraphicsInit.h
new file mode 100644
index 0000000..6d060cb
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/SaInit/Pei/GraphicsInit.h
@@ -0,0 +1,219 @@
+/** @file
+  Graphics header file
+
+@copyright
+  Copyright (c) 1999 - 2013 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement
+**/
+#ifndef _GRAPHICS_INIT_H_
+#define _GRAPHICS_INIT_H_
+
+#include "EdkIIGluePeim.h"
+#include "SaAccess.h"
+#include "PchAccess.h"
+#include "EdkIIGluePcdPciExpressLib.h"
+#include "EdkIIGlueConfig.h"
+#include "Pci22.h"
+#include "PchPlatformLib.h"
+#include "CpuRegs.h"
+#include "CpuPlatformLib.h"
+
+///
+/// Driver Consumed PPI Prototypes
+///
+#include EFI_PPI_DEPENDENCY (SaPlatformPolicy)
+
+typedef struct {
+  UINT8   Bus;
+  UINT8   Device;
+  UINT8   Function;
+  UINT16  DevenMask;
+} PEG_DEVEN;
+
+typedef enum {
+  IGD               = 0,
+  PEG,
+  PCI,
+  DISPLAY_DEVICE_MAX
+} DISPLAY_DEVICE;
+
+typedef enum {
+  VBIOS_DEFAULT     = 0,
+  CRT,
+  LFP,
+  CRT_LFP,
+  TV,
+  LFPSDVO,
+  EFP,
+  TVSDVO,
+  CRT_LFPSDVO,
+  CRT_EFP,
+  IGD_BOOT_TYPE_MAX
+} IGD_BOOT_TYPE;
+
+typedef enum {
+  GMS_FIXED         = 0,
+  GMS_DVMT,
+  GMS_FIXED_DVMT,
+  GMS_MAX
+} GRAPHICS_MEMORY_SELECTION;
+
+typedef enum {
+  GM_32M            = 1,
+  GM_64M            = 2,
+  GM_128M           = 4,
+  GM_MAX
+} STOLEN_MEMORY;
+
+typedef enum {
+  PAVP_DISABLED     = 0,
+  PAVP_LITE,
+  PAVP_HIGH
+} PAVP_MODE;
+
+#define GTTMMADR_SIZE_4MB   0x400000
+#define GTT_SIZE_2MB        2
+#define GT_WAIT_TIMEOUT     3000     ///< ~3 seconds
+
+#define APERTURE_SIZE_128MB 1
+#define APERTURE_SIZE_256MB 2
+#define APERTURE_SIZE_512MB 3
+
+/**
+  CheckAndInitializePegVga:  Check if PEG card is present and configure accordingly
+
+  @param[in] PeiServices             - Pointer to the PEI services table
+  @param[in] AlwaysEnablePeg         - 0 - Peg is not always enabled.
+  @param[in, out] PrimaryDisplay     - Primary Display - default is IGD
+  @param[in] PrimaryDisplaySelection - Primary display selection from BIOS Setup
+  @param[in, out] PegMmioLength      - Total PEG MMIO length on all PEG ports
+**/
+VOID
+CheckAndInitializePegVga (
+  IN     EFI_PEI_SERVICES                   **PeiServices,
+  IN     UINT8                              AlwaysEnablePeg,
+  IN OUT DISPLAY_DEVICE                     *PrimaryDisplay,
+  IN     UINT8                              PrimaryDisplaySelection,
+  IN OUT UINT32                             *PegMmioLength
+  )
+;
+
+/**
+  CheckOffboardPciVga: Check if off board PCI graphics Card is present
+
+  @param[in] PeiServices          - Pointer to the PEI services table
+  @param[in, out] PciMmioLength   - PCI MMIO length
+  @param[in, out] PrimaryDisplay  - Primary Display - default is IGD
+**/
+VOID
+CheckOffboardPciVga (
+  IN     EFI_PEI_SERVICES                   **PeiServices,
+  IN OUT UINT32                             *PciMmioLength,
+  IN OUT DISPLAY_DEVICE                     *PrimaryDisplay
+  )
+;
+
+/**
+  CheckOffboardPcieVga: Check if off board PCIe graphics Card is present
+
+  @param[in] PeiServices             - Pointer to the PEI services table
+  @param[in, out] PchPcieMmioLength  - Total PCIe MMIO length on all PCH root ports
+  @param[in, out] PrimaryDisplay     - Primary Display - default is IGD
+**/
+VOID
+CheckOffboardPcieVga (
+  IN     EFI_PEI_SERVICES     **PeiServices,
+  IN OUT UINT32               *PchPcieMmioLength,
+  IN OUT DISPLAY_DEVICE       *PrimaryDisplay
+  )
+;
+
+/**
+  Find the MMIO size that a given PCI device requires
+
+  @param[in] BusNum      - Bus number of the device
+  @param[in] DevNum      - device Number of the device
+  @param[in] FunNum      - Function number of the device
+  @param[out] MmioLength - MMIO Length in bytes
+**/
+VOID
+FindPciDeviceMmioLength (
+  IN UINT32  BusNum,
+  IN UINT32  DevNum,
+  IN UINT32  FunNum,
+  OUT UINT32 *MmioLength
+  )
+;
+
+/**
+  This function enumerate all downstream bridge.
+
+  @param[in] BusNum  - Primary bus number of current bridge
+
+  @retval Current bus number: if current bus is an enpoint device
+  @retval subordinate bus number: if current bus is a bridge
+**/
+UINT8
+EnumerateDownstream (
+  IN UINT8 BusNum
+  )
+;
+
+/**
+  This function enumerate the bridge on the device
+
+  @param[in] PegBus             - Particular Bus number
+  @param[in] PegDev             - Particular Device number
+  @param[in] PegFunc            - Particular Func number
+  @param[in, out] PegMmioLength - PEG MMIO length
+
+  @retval CardDetect : TRUE if current bridge device has a Graphics card.
+  @retval CardDetect : FALSE if current bridge device has no Graphics card.
+**/
+BOOLEAN
+EnumerateBridgeDevice (
+  IN UINT8                                  PegBus,
+  IN UINT8                                  PegDev,
+  IN UINT8                                  PegFunc,
+  IN OUT UINT32                             *PegMmioLength
+  )
+;
+
+/**
+
+  "Poll Status" for GT Readiness
+
+  @param[in] PeiServices     - Pointer to the PEI services table
+  @param[in] StallPpi        - Pointer to Stall PPI
+  @param[in] Base            - Base address of MMIO
+  @param[in] Offset          - MMIO Offset
+  @param[in] Mask            - Mask
+  @param[in] Result          - Value to wait for
+
+
+**/
+VOID
+PollGtReady (
+  IN EFI_PEI_SERVICES     **PeiServices,
+  IN PEI_STALL_PPI        *StallPpi,
+  UINT64 Base,
+  UINT32 Offset,
+  UINT32 Mask,
+  UINT32 Result
+  )
+;
+
+#endif
diff --git a/ReferenceCode/Chipset/SystemAgent/SaInit/Pei/PciExpressInit.c b/ReferenceCode/Chipset/SystemAgent/SaInit/Pei/PciExpressInit.c
new file mode 100644
index 0000000..bead6ce
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/SaInit/Pei/PciExpressInit.c
@@ -0,0 +1,2987 @@
+/** @file
+  PEI Function to initialize SA PciExpress.
+
+@copyright
+  Copyright (c) 1999 - 2014 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement
+
+**/
+
+#include "PciExpressInit.h"
+#include "PcieTraining.h"
+#include "PchPlatformLib.h"
+
+#include <Token.h> //AMI_OVERRIDE
+
+#ifdef PEG_FLAG
+#include EFI_GUID_DEFINITION (SaDataHob)
+
+#define SA_PEG_VMARGIN_UP   0
+#define SA_PEG_VMARGIN_DOWN 1
+
+#define SA_PEG_LINK_DISABLE_MAXWAIT 100*10
+
+VOID
+ReportPcieLinkStatus (
+  IN UINT8             PegBus,
+  IN UINT8             PegDev,
+  IN UINT8             PegFunc
+)
+/**
+ This function reports a PEG controller's link status
+
+  @param[in] PegBus       - Peg Bus
+  @param[in] PegDev       - Peg Device
+  @param[in] PegFunc      - Peg Function
+
+  @retval None
+**/
+{
+  UINT32 Deven;
+  UINT16 LinkStatus;
+  UINT8  LinkWidth;
+  UINT8  LinkSpeed;
+  UINT16 Vc0Pending;
+
+  Deven  = MmPci32 (0, SA_MC_BUS, SA_MC_DEV, SA_MC_FUN, R_SA_DEVEN);
+  Deven = (Deven >> 1) & 0x7;
+  DEBUG ((EFI_D_INFO, "PEG%x%x (%x:%x:%x) - ", PegDev, PegFunc, PegBus, PegDev, PegFunc));
+  if (((Deven >> (SA_PEG_MAX_FUN - 1 - PegFunc)) & 0x1) == 0x1) {
+    LinkStatus = MmPci16 (0, PegBus, PegDev, PegFunc, R_SA_PEG_LSTS_OFFSET);
+    LinkWidth  = (LinkStatus >> 4) & 0x3F;
+    LinkSpeed  = LinkStatus & 0xF;
+    Vc0Pending = ((MmPci16 (0, PegBus, PegDev, PegFunc, R_SA_PEG_VC0RSTS_OFFSET)) >> 1) & 0x1;
+    DEBUG ((EFI_D_INFO, "Trained to x%d at Gen%d.", LinkWidth, LinkSpeed));
+    DEBUG ((EFI_D_INFO, " VC0 Negotiation Pending = %d.", Vc0Pending));
+    DEBUG ((EFI_D_INFO, "\n"));
+  } else {
+    DEBUG ((EFI_D_INFO, "Disabled.\n"));
+  }
+}
+
+VOID
+WaitForVc0Negotiation (
+  IN EFI_PEI_SERVICES  **PeiServices,
+  IN PEI_STALL_PPI     *StallPpi,
+  IN UINT8             PegBus,
+  IN UINT8             PegDev,
+  IN UINT8             PegFunc
+)
+/**
+  This function prints the time required for VC0 Negotiation Pending to be cleared. Quits after 100 msec.
+
+  @param[in] PeiServices  - Pointer to the PEI services table
+  @param[in] StallPpi     - Pointer to PEI_STALL_PPI
+  @param[in] PegBus       - Peg Bus
+  @param[in] PegDev       - Peg Device
+  @param[in] PegFunc      - Peg Function
+
+  @retval None
+**/
+{
+  UINT32 Deven;
+  UINT32 MsecWait;
+  UINT16 Vc0Pending;
+
+  Deven  = MmPci32 (0, SA_MC_BUS, SA_MC_DEV, SA_MC_FUN, R_SA_DEVEN);
+  Deven = (Deven >> 1) & 0x7;
+  if (((Deven >> (SA_PEG_MAX_FUN - 1 - PegFunc)) & 0x1) == 0x1) {
+    MsecWait = 0;
+    Vc0Pending = ((MmPci16 (0, PegBus, PegDev, PegFunc, R_SA_PEG_VC0RSTS_OFFSET)) >> 1) & 0x1;
+
+    while (Vc0Pending && (MsecWait < 100)) {
+      MsecWait++;
+      StallPpi->Stall (PeiServices, StallPpi, STALL_ONE_MILLI_SECOND);
+      Vc0Pending = ((MmPci16 (0, PegBus, PegDev, PegFunc, R_SA_PEG_VC0RSTS_OFFSET)) >> 1) & 0x1;
+    }
+    DEBUG ((EFI_D_INFO, "PEG%x%x (%x:%x:%x) - VC0 Negotiation Pending = %x after %d msec.\n",
+      PegDev, PegFunc, PegBus, PegDev, PegFunc, Vc0Pending, MsecWait));
+  }
+}
+
+VOID
+GracefulLinkStatusStall (
+  IN EFI_PEI_SERVICES                   **PeiServices,
+  IN PEI_STALL_PPI                      *StallPpi,
+  IN SA_PLATFORM_POLICY_PPI             *SaPlatformPolicyPpi,
+  IN SA_DATA_HOB                        *SaDataHob,
+  IN UINT8                              HwStrap
+  )
+/**
+  If we have a record of links that did not train from last boot, then do not stall for them
+  For links that did train last boot, stall until they train or 100ms pass
+
+  @param[in] PeiServices         - Pointer to the PEI services table
+  @param[in] StallPpi            - Pointer to PEI_STALL_PPI
+  @param[in] SaPlatformPolicyPpi - Pointer to SA_PLATFORM_POLICY_PPI
+  @param[in] SaDataHob           - Pointer to SA_DATA_HOB
+  @param[in] HwStrap             - HwStrap configuration from FUSESCMN
+
+  @retval None
+**/
+{
+  UINT8          LinkStatusGood;
+  UINT8          PegLinkFailMask;
+  UINT8          i;
+  UINT8          PegDev;
+  UINT8          PegFunc;
+  UINT8          CurrentPegFuncBit;
+  UINT8          SkipFuncMask;
+  EFI_STATUS     Status;
+  EFI_BOOT_MODE  BootMode;
+
+  PegLinkFailMask = 0;
+  ///
+  /// If this is S3 Resume or Warm Boot, check if PEG delay can be skipped when no PEG devices populated.
+  ///
+  Status = (*PeiServices)->GetBootMode (PeiServices, &BootMode);
+  ASSERT_EFI_ERROR (Status);
+  if ((BootMode == BOOT_ON_S3_RESUME) || (GetPchPmStatus (WarmBoot) == TRUE)) {
+    if ((SaDataHob != NULL) && (SaDataHob->PegDataValid)) {
+      if (SaDataHob->PegData.PegLinkFailMask != 0) {
+        PegLinkFailMask = SaDataHob->PegData.PegLinkFailMask;
+        DEBUG ((EFI_D_INFO, "Previous Link Training Fail Mask 0x%2.2X\n", SaDataHob->PegData.PegLinkFailMask));
+      } else {
+        PegLinkFailMask = 0xFF;
+        for (i = 0; i < SA_PEG_MAX_FUN; i++) {
+          PegLinkFailMask &= (UINT8) ~(0x1 << i);
+        }
+      }
+    }
+  }
+  DEBUG ((EFI_D_INFO, "New Link Training Fail Mask 0x%2.2X\n", PegLinkFailMask));
+
+  switch (HwStrap) {
+    case SA_PEG_x16_x0_x0:
+      SkipFuncMask = BIT2 | BIT1;
+      break;
+
+    case SA_PEG_x8_x8_x0:
+      SkipFuncMask = BIT2;
+      break;
+
+    default:
+    case SA_PEG_x8_x4_x4:
+      SkipFuncMask = 0;
+      break;
+  }
+
+  LinkStatusGood = 0;
+  PegDev = 1;
+  for (i = 0; i < 100; i++) {
+    ///
+    /// Poll endpoints
+    /// Skip endpoints that failed last boot
+    /// Skip endpoints that trained good this boot
+    /// Loop in 1-ms increments until all endpoints are:
+    ///  reported bad from last boot, or
+    ///  have trained good on this boot
+    ///
+    for (PegFunc = 0, CurrentPegFuncBit = 1; PegFunc < SA_PEG_MAX_FUN; PegFunc++, CurrentPegFuncBit <<= 1) {
+      if (CurrentPegFuncBit == (CurrentPegFuncBit & SkipFuncMask)) {
+        if (i == 0) {
+          DEBUG ((EFI_D_INFO, " PEG%x%x (%x:%x:%x) - skipping due to furcation\n", PegDev, PegFunc, SA_PEG_BUS_NUM, PegDev, PegFunc));
+        }
+        continue;
+      }
+      ///
+      /// If configuration change, then break out of loop.
+      /// Test if current PEG is neither in fail mask nor previously tested good.
+      ///
+      if (CurrentPegFuncBit != (CurrentPegFuncBit & (UINT8) (PegLinkFailMask | LinkStatusGood))) {
+        DEBUG ((EFI_D_INFO, " PEG%x%x (%x:%x:%x) - checking\n", PegDev, PegFunc, SA_PEG_BUS_NUM, PegDev, PegFunc));
+        ///
+        /// VC negotiation is complete
+        ///
+        if ((BIT1 & MmPci16(0, SA_PEG_BUS_NUM, PegDev, PegFunc, R_SA_PEG_VC0RSTS_OFFSET)) != BIT1) {
+          DEBUG ((EFI_D_INFO, "  VC negotiation is complete\n"));
+          ///
+          /// Record as a good link
+          ///
+          LinkStatusGood |= CurrentPegFuncBit;
+        }
+      }
+    }
+    ///
+    /// If all links accounted for, then exit.
+    ///
+    if (((UINT8) (LinkStatusGood | PegLinkFailMask | SkipFuncMask)) == 0xFF) {
+      break;
+    }
+    StallPpi->Stall (PeiServices, StallPpi, STALL_ONE_MILLI_SECOND);
+  } ///< End of stall loop
+
+  DEBUG ((EFI_D_INFO, "Total Stall: %d msec\n", i));
+  if (SaDataHob != NULL) {
+    SaDataHob->PegData.PegLinkFailMask = (UINT8) ~LinkStatusGood;
+    DEBUG ((EFI_D_INFO, "Returned PegLinkFailMask 0x%2.2X\n", SaDataHob->PegData.PegLinkFailMask));
+  }
+
+}
+
+UINT32
+PcieFindCapId (
+  IN UINT8   Bus,
+  IN UINT8   Device,
+  IN UINT8   PegFunc,
+  IN UINT8   CapId
+  )
+/**
+  Find the Offset to a given Capabilities ID
+  CAPID list:
+    0x01 = PCI Power Management Interface
+    0x04 = Slot Identification
+    0x05 = MSI Capability
+    0x10 = PCI Express Capability
+
+  @param[in] Bus       -   Pci Bus Number
+  @param[in] Device    -   Pci Device Number
+  @param[in] PegFunc   -   Pci Function Number
+  @param[in] CapId     -   CAPID to search for
+
+  @retval 0       - CAPID not found
+  @retval Other   - CAPID found, Offset of desired CAPID
+**/
+{
+  UINT8 CapHeader;
+
+  ///
+  /// Always start at Offset 0x34
+  ///
+  CapHeader = MmPci8 (0, Bus, Device, PegFunc, PCI_CAPBILITY_POINTER_OFFSET);
+  if (CapHeader == 0xFF) {
+    return 0;
+  }
+
+  while (CapHeader != 0) {
+    ///
+    /// Bottom 2 bits of the pointers are reserved per PCI Local Bus Spec 2.2
+    ///
+    CapHeader &= ~(BIT1 | BIT0);
+    ///
+    /// Search for desired CapID
+    ///
+    if (MmPci8 (0, Bus, Device, PegFunc, CapHeader) == CapId) {
+      return CapHeader;
+    }
+
+    CapHeader = MmPci8 (0, Bus, Device, PegFunc, CapHeader + 1);
+  }
+
+  return 0;
+}
+
+
+VOID
+SetLoadBus (
+  IN UINT32 DmiBar,
+  IN UINTN  Dev,
+  IN UINTN  Lane,
+  IN UINT32 LoadSel,
+  IN UINT32 LoadData,
+  IN UINT8  CpuSteppingId
+  )
+/**
+  Set Load Bus
+
+  @param[in] DmiBar        - DMIBAR address
+  @param[in] Dev           - Device Number
+  @param[in] Lane          - Number of Lane
+  @param[in] LoadSel       - Load selection value
+  @param[in] LoadData      - Load Data
+  @param[in] CpuSteppingId - CPUID.1.EAX[3:0], CPU stepping ID
+
+  @retval None
+**/
+{
+  UINT32  lbcvalue;
+  UINT32  lbcdata;
+  UINT32  lbclnsel;
+  UINT32  lbcldsel;
+  UINT32  lbcaddr;
+
+  lbcaddr   = R_SA_PEG_LOADBUSCTL0_OFFSET + BUNDLE_STEP * (Lane >> 1);
+  lbcvalue  = 0x70000000;
+
+  lbclnsel  = ((Lane & 1) == 0) ? 0x80000 : 0x100000;
+  lbcldsel  = (LoadSel & 0x3f) << 21;
+  lbcdata   = (LoadData << 1) & 0x7FFF;
+
+  lbcvalue  = lbcvalue | lbclnsel | lbcldsel | lbcdata;
+
+  if (Dev == 0) {
+    Mmio32 (DmiBar, lbcaddr) = lbcvalue;
+  } else {
+    MmPci32 (0, SA_PEG_BUS_NUM, Dev, SA_PEG10_FUN_NUM, lbcaddr) = lbcvalue;
+  }
+
+  return;
+}
+
+UINT32
+GetMonBus (
+  IN UINT32 DmiBar,
+  IN UINTN  Dev,
+  IN UINTN  Lane,
+  IN UINT32 LoadSel,
+  IN UINT8  CpuSteppingId
+  )
+/**
+  Get monitor bus from the lane selected
+
+  @param[in] DmiBar        - DMIBAR address
+  @param[in] Dev           - Device number
+  @param[in] Lane          - Number of Lane
+  @param[in] LoadSel       - Load selection value
+  @param[in] LoadData      - Load selecttion data
+  @param[in] CpuSteppingId - CPUID.1.EAX[3:0], CPU stepping ID
+
+  @retval UINT32 - Load bus address
+**/
+{
+  UINT32  monvalue;
+  UINT32  prevalue;
+  UINT32  lbclnsel;
+  UINT32  lbcldsel;
+  UINT32  lbcaddr;
+  UINT32  Result;
+
+  lbcaddr   = R_SA_PEG_LOADBUSCTL0_OFFSET + BUNDLE_STEP * (Lane >> 1);
+  monvalue  = 0x068008000;
+
+  if (Dev == 0) {
+    prevalue = Mmio32 (DmiBar, lbcaddr);
+  } else {
+    prevalue = MmPci32 (0, SA_PEG_BUS_NUM, Dev, SA_PEG10_FUN_NUM, lbcaddr);
+  }
+  monvalue  = monvalue | (prevalue & 0x7FFE);
+
+  lbclnsel  = ((Lane & 1) == 0) ? 0x80000 : 0x100000;
+  lbcldsel  = (LoadSel & 0x3f) << 21;
+  monvalue  = monvalue | lbclnsel | lbcldsel;
+
+  if (Dev == 0) {
+    Mmio32 (DmiBar, lbcaddr)  = monvalue;
+    Result                    = Mmio32 (DmiBar, lbcaddr);
+  } else {
+    MmPci32 (0, SA_PEG_BUS_NUM, Dev, SA_PEG10_FUN_NUM, lbcaddr) = monvalue;
+    Result = MmPci32 (0, SA_PEG_BUS_NUM, Dev, SA_PEG10_FUN_NUM, lbcaddr);
+  }
+
+  return (Result >> 1) & 0x3FFF;
+}
+
+VOID
+ProgramPreset (
+  IN UINT8  Direction,
+  IN UINT8  PresetValue,
+  IN UINT8  PegFunc,
+  IN UINT8  Lane
+  )
+/**
+  Program PEG Gen3 preset value
+
+  @param[in] Direction     - 0 = Root Port, 1 = End Point
+  @param[in] PresetValue   - Preset value to program
+  @param[in] PegFunc       - Peg function number to be configured
+  @param[in] Lane          - Lane to be configured
+
+  @retval None
+**/
+{
+  UINT32  Data32Or;
+  UINT32  Data32And;
+  UINT8   OriginalLane;
+
+  OriginalLane = Lane;
+  switch (PegFunc) {
+    case 1:
+      if (Lane < 8) {
+        DEBUG ((EFI_D_WARN, "Invalid input to ProgramPreset() function!  PegFunc=%d, Lane=%d\n", PegFunc, Lane));
+        return;
+      } else {
+        Lane -= 8;
+      }
+      break;
+    case 2:
+      if (Lane < 12) {
+        DEBUG ((EFI_D_WARN, "Invalid input to ProgramPreset() function!  PegFunc=%d, Lane=%d\n", PegFunc, Lane));
+        return;
+      } else {
+        Lane -= 12;
+      }
+      break;
+    default:
+      break;
+  }
+  ///
+  /// RP preset goes to bits [3:0]  for even lane and [19:16] for odd lane
+  /// EP preset goes to bits [11:8] for even lane and [27:24] for odd lane
+  ///
+  if (Direction != 0) {
+    if ((Lane % 2) == 0) {
+      Data32And = 0xFFFFF0FF;
+      Data32Or  = PresetValue << 8;
+    } else {
+      Data32And = 0xF0FFFFFF;
+      Data32Or  = PresetValue << 24;
+    }
+  } else {
+    if (OriginalLane >= 8) {
+      if ((Lane % 2) == 0) {
+        Data32And = 0xFFF0FFFF;
+        Data32Or  = PresetValue << 16;
+      } else {
+            Data32And = 0xFFFFFFF0;
+            Data32Or  = PresetValue;
+      }
+    } else {
+      if ((Lane % 2) == 0) {
+        Data32And = 0xFFFFFFF0;
+        Data32Or  = PresetValue;
+      } else {
+        Data32And = 0xFFF0FFFF;
+        Data32Or  = PresetValue << 16;
+      }
+    }
+  }
+
+  MmPci32AndThenOr (0, SA_PEG_BUS_NUM, SA_PEG_DEV_NUM, PegFunc, R_SA_PEG_EQCTL0_1_OFFSET + (Lane / 2) * 4, Data32And, Data32Or);
+
+  return;
+}
+
+VOID
+ProgramPresetPerLane (
+  IN UINT8  *RootPortPreset,
+  IN UINT8  *EndPointPreset,
+  IN UINT8  *EndPointHint,
+  IN UINTN  HwStrap
+  )
+/**
+  Program PEG Gen3 preset values per lane
+
+  @param[in] RootPortPreset  - Array of root port preset values to program
+  @param[in] EndPointPreset  - Array of end point preset values to program
+  @param[in] EndPointHint    - Array of end point hint value to program
+  @param[in] HwStrap         - HwStrap configuration from FUSESCMN
+
+  @retval None
+**/
+{
+  UINTN i;
+
+  for (i = 0; i < SA_PEG_MAX_LANE; i++) {
+    if (RootPortPreset[i] > 9) {
+      RootPortPreset[i] = 8;
+    }
+    if (EndPointPreset[i] > 9) {
+      EndPointPreset[i] = 7;
+    }
+    if (EndPointHint[i] > 6) {
+      EndPointHint[i] = 2;
+    }
+  }
+
+  ///
+  /// RP preset goes to bits [3:0]   and [19:16]
+  /// EP preset goes to bits [11:8]  and [27:24]
+  /// EP hint   goes to bits [14:12] and [30:28]
+  ///
+  switch (HwStrap) {
+    case SA_PEG_x16_x0_x0:
+      ///
+      /// PEG10 x16
+      ///
+
+      for (i = 0; i < 4; ++i) {
+        McD1PciCfg32AndThenOr (R_SA_PEG_EQCTL0_1_OFFSET + i * 4, 0x80F080F0,
+          RootPortPreset[2 * i] | (EndPointPreset[2 * i] << 8) | (EndPointHint[2 * i] << 12) | (RootPortPreset[2 * i + 1] << 16) | (EndPointPreset[2 * i + 1] << 24) | (EndPointHint[2 * i + 1] << 28));
+      }
+      for (i = 4; i < 8; ++i) {
+        McD1PciCfg32AndThenOr (R_SA_PEG_EQCTL0_1_OFFSET + i * 4, 0x80F080F0,
+          RootPortPreset[2 * i + 1] | (EndPointPreset[2 * i] << 8) | (EndPointHint[2 * i] << 12) | (RootPortPreset[2 * i] << 16) | (EndPointPreset[2 * i + 1] << 24) | (EndPointHint[2 * i + 1] << 28));
+      }
+      break;
+
+    case SA_PEG_x8_x8_x0:
+      ///
+      /// PEG10 x8 / PEG11 x8
+      ///
+      for (i = 0; i < 4; ++i) {
+        McD1PciCfg32AndThenOr (R_SA_PEG_EQCTL0_1_OFFSET + i * 4, 0x80F080F0,
+          RootPortPreset[2 * i] | (EndPointPreset[2 * i] << 8) | (EndPointHint[2 * i] << 12) | (RootPortPreset[2 * i + 1] << 16) | (EndPointPreset[2 * i + 1] << 24) | (EndPointHint[2 * i + 1] << 28));
+        McD1F1PciCfg32AndThenOr (R_SA_PEG_EQCTL0_1_OFFSET + i * 4, 0x80F080F0,
+          RootPortPreset[8 + 2 * i + 1] | (EndPointPreset[8 + 2 * i] << 8) | (EndPointHint[8 + 2 * i] << 12) | (RootPortPreset[8 + 2 * i] << 16) | (EndPointPreset[8 + 2 * i + 1] << 24) | (EndPointHint[8 + 2 * i + 1] << 28));
+      }
+      break;
+
+    case SA_PEG_x8_x4_x4:
+      ///
+      /// PEG10 x8 / PEG11 x4 / PEG12 x4
+      ///
+      for (i = 0; i < 4; ++i) {
+        McD1PciCfg32AndThenOr (R_SA_PEG_EQCTL0_1_OFFSET + i * 4, 0x80F080F0,
+          RootPortPreset[2 * i] | (EndPointPreset[2 * i] << 8) | (EndPointHint[2 * i] << 12) | (RootPortPreset[2 * i + 1] << 16) | (EndPointPreset[2 * i + 1] << 24) | (EndPointHint[2 * i + 1] << 28));
+      }
+      for (i = 0; i < 2; ++i) {
+        McD1F1PciCfg32AndThenOr (R_SA_PEG_EQCTL0_1_OFFSET + i * 4, 0x80F080F0,
+          RootPortPreset[8 + 2 * i + 1] | (EndPointPreset[8 + 2 * i] << 8) | (EndPointHint[8 + 2 * i] << 12) | (RootPortPreset[8 + 2 * i] << 16) | (EndPointPreset[8 + 2 * i + 1] << 24) | (EndPointHint[8 + 2 * i + 1] << 28));
+        McD1F2PciCfg32AndThenOr (R_SA_PEG_EQCTL0_1_OFFSET + i * 4, 0x80F080F0,
+          RootPortPreset[12 + 2 * i + 1] | (EndPointPreset[12 + 2 * i] << 8) | (EndPointHint[12 + 2 * i] << 12) | (RootPortPreset[12 + 2 * i] << 16) | (EndPointPreset[12 + 2 * i + 1] << 24) | (EndPointHint[12 + 2 * i + 1] << 28));
+      }
+      break;
+
+    default:
+      break;
+  }
+
+  return;
+}
+
+VOID
+PegGen3Equalization (
+  IN SA_PLATFORM_POLICY_PPI  *SaPlatformPolicyPpi,
+  IN UINT8                   CpuSteppingId,
+  IN UINTN                   HwStrap
+  )
+/**
+  Perform PEG Gen3 Equalization steps
+
+  @param[in] SaPlatformPolicyPpi - pointer to SA_PLATFORM_POLICY_PPI
+  @param[in] CpuSteppingId       - CPUID.1.EAX[3:0], CPU stepping ID
+  @param[in] HwStrap             - HwStrap configuration from FUSESCMN
+
+  @retval None
+**/
+{
+  UINT8               *RootPortPreset;
+  UINT8               *EndPointPreset;
+  UINT8               *EndPointHint;
+
+  ///
+  /// Apply static presets for root port and endpoint
+  ///
+  RootPortPreset = SaPlatformPolicyPpi->PcieConfig->Gen3RootPortPreset;
+  EndPointPreset = SaPlatformPolicyPpi->PcieConfig->Gen3EndPointPreset;
+  EndPointHint   = SaPlatformPolicyPpi->PcieConfig->Gen3EndPointHint;
+
+  ProgramPresetPerLane (RootPortPreset, EndPointPreset, EndPointHint, HwStrap);
+
+  return;
+}
+
+#endif // PEG_FLAG
+
+#if defined(DMI_FLAG) || defined(PEG_FLAG)
+VOID
+PegDmiRecipe (
+  IN SA_PLATFORM_POLICY_PPI *SaPlatformPolicyPpi,
+  IN UINT32                 MchBar,
+  IN UINT32                 DmiBar,
+  IN UINTN                  Dev,
+  IN UINT8                  SwingControl
+  )
+/**
+  Perform PEG/DMI PCIe Recipe steps
+
+  @param[in] SaPlatformPolicyPpi - Pointer to SA_PLATFORM_POLICY_PPI
+  @param[in] MchBar              - MCHBAR or zero if called for PEG
+  @param[in] DmiBar              - DMIBAR or zero if called for PEG
+  @param[in] Dev                 - PEG device number: 1 for PEG10, 0 if called for DMI.
+  @param[in] SwingControl        - 1 = Half, 2 = Full
+
+  @retval None
+**/
+{
+  UINTN             i;
+  UINTN             BundlesCount;
+  UINTN             LanesCount;
+  UINT32            Data32;
+  UINT32            Data32And;
+  UINT32            Data32Or;
+  UINT32            VcuAddress;
+  UINT8             VcuReadOp;
+  UINT8             VcuWriteOp;
+  CPU_FAMILY        CpuFamilyId;
+  CPU_STEPPING      CpuSteppingId;
+  BOOLEAN           IsSingleCall;
+
+  CpuFamilyId   = GetCpuFamily();
+  CpuSteppingId = GetCpuStepping();
+
+  ///
+  /// With both DMI_FLAG and PEG_FLAG defined, this function is called twice: once for DMI and once for PEG.
+  /// Some registers are shared between DMI and PEG, so they are only programmed during one of the calls.
+  /// If only one flag is defined, this function will only be called once, so the shared registers need to be
+  /// programmed during the first/only call.
+  ///
+  IsSingleCall = TRUE;
+#if defined(DMI_FLAG) && defined(PEG_FLAG)
+  IsSingleCall = FALSE;
+#endif
+
+  if (Dev == SA_PEG_DEV_NUM) {
+    ///
+    /// PEG10
+    ///
+    LanesCount = SA_PEG_MAX_LANE;
+  } else {
+    ///
+    /// DMI
+    ///
+    LanesCount = SA_DMI_MAX_LANE;
+  }
+
+  BundlesCount = LanesCount >> 1;
+
+  ///
+  /// g23rxvref = 0xC (DMI & PEG)
+  ///
+  Data32And = (UINT32) ~(BIT4 | BIT3 | BIT2 | BIT1 | BIT0);
+  Data32Or  = 0xC;
+  for (i = 0; i < LanesCount; i++) {
+    SaMmio32AndThenOr (DmiBar, Dev, R_SA_PEG_AFELN0CFG0_OFFSET + i * LANE_STEP, Data32And, Data32Or);
+  }
+  ///
+  /// CDRPDDATMODE = 0x1 (DMI & PEG)
+  ///
+  if ((CpuFamilyId == EnumCpuHsw) && (CpuSteppingId == EnumHswA0)) {
+    for (i = 0; i < LanesCount; i++) {
+      SaMmio32AndThenOr (DmiBar, Dev, R_SA_PEG_AFELN0CFG1_OFFSET + i * LANE_STEP, 0xFFFFFFFF, BIT11);
+    }
+  }
+  ///
+  /// irefctl = 0x2 (PEG only)
+  ///
+  if (DmiBar == 0) {
+    ///
+    /// Switch on
+    /// SwingControl 1 == Half
+    ///              2 == Full (Default)
+    ///
+    switch (SwingControl) {
+      case SA_SWING_HALF:
+        Data32Or = 0x0C;
+        break;
+
+      default:
+      case SA_SWING_FULL:
+        Data32Or = 0x02;
+        break;
+    }
+
+    for (i = 0; i < BundlesCount; i++) {
+      SaMmio32AndThenOr (DmiBar, Dev, R_SA_PEG_AFEBND0CFG1_OFFSET + i * BUNDLE_STEP, (UINT32) ~(0x1F), Data32Or);
+    }
+  }
+  ///
+  /// txvrefsel = 0x3 (PEG only)
+  ///
+  if (DmiBar == 0) {
+    ///
+    /// Switch on
+    /// SwingControl 1 == Half
+    ///              2 == Full (Default)
+    ///
+    switch (SwingControl) {
+      case SA_SWING_HALF:
+        Data32Or = 0x0E;
+        break;
+
+      default:
+      case SA_SWING_FULL:
+        Data32Or = 0x03;
+        break;
+    }
+
+    for (i = 0; i < BundlesCount; i++) {
+      SaMmio32AndThenOr (DmiBar, Dev, R_SA_PEG_AFEBND0CFG1_OFFSET + i * BUNDLE_STEP, (UINT32) ~(0x1F << 5), Data32Or << 5);
+    }
+  }
+  ///
+  /// igacq = 0x0 (HSW A0: DMI & PEG)
+  ///
+  if ((CpuFamilyId == EnumCpuHsw) && (CpuSteppingId == EnumHswA0)) {
+    for (i = 0; i < BundlesCount; i++) {
+      SaMmio32AndThenOr (DmiBar, Dev, R_SA_PEG_AFEBND0CFG1_OFFSET + i * BUNDLE_STEP, (UINT32) ~(7 << 22), 0);
+    }
+  }
+  ///
+  /// dfegainacq = 0x1 (HSW A0: DMI & PEG)
+  ///
+  if ((CpuFamilyId == EnumCpuHsw) && (CpuSteppingId == EnumHswA0)) {
+    for (i = 0; i < BundlesCount; i++) {
+      SaMmio32AndThenOr (DmiBar, Dev, R_SA_PEG_AFEBND0CFG1_OFFSET + i * BUNDLE_STEP, (UINT32) ~(3 << 29), 1 << 29);
+    }
+  }
+  ///
+  /// PGTRK = 0x9 (DMI & PEG)
+  ///
+  Data32And = (UINT32) ~(BIT10 | BIT9 | BIT8 | BIT7 | BIT6 | BIT5);
+  Data32Or  = 0x9 << 5;
+  for (i = 0; i < BundlesCount; i++) {
+    SaMmio32AndThenOr (DmiBar, Dev, R_SA_PEG_AFEBND0CFG3_OFFSET + i * BUNDLE_STEP, Data32And, Data32Or);
+  }
+  ///
+  /// igtrk = 0x0 (HSW A0: DMI & PEG)
+  ///
+  if ((CpuFamilyId == EnumCpuHsw) && (CpuSteppingId == EnumHswA0)) {
+    for (i = 0; i < BundlesCount; i++) {
+      SaMmio32AndThenOr (DmiBar, Dev, R_SA_PEG_AFEBND0CFG3_OFFSET + i * BUNDLE_STEP, (UINT32) ~(7 << 17), 0);
+    }
+  }
+  ///
+  /// RXRTBIN = 0x5 (PEG only)
+  ///
+  if (DmiBar == 0) {
+    Data32And = (UINT32) ~(BIT24 | BIT23 | BIT22 | BIT21);
+    Data32Or  = 0x5 << 21;
+    for (i = 0; i < BundlesCount; i++) {
+      SaMmio32AndThenOr (DmiBar, Dev, R_SA_PEG_AFEBND0CFG3_OFFSET + i * BUNDLE_STEP, Data32And, Data32Or);
+    }
+  }
+  ///
+  /// G3RXCTLEPEAK = 0x8 (PEG only)
+  ///
+  if (DmiBar == 0) {
+    Data32And = (UINT32) ~(BIT9 | BIT8 | BIT7 | BIT6);
+    for (i = 0; i < BundlesCount; i++) {
+      if (SaPlatformPolicyPpi->Revision >= SA_PLATFORM_POLICY_PPI_REVISION_3) {
+        Data32Or = SaPlatformPolicyPpi->PcieConfig->Gen3RxCtleP[i] << 6;
+      } else {
+        Data32Or  = 8 << 6;
+      }
+      SaMmio32AndThenOr (DmiBar, Dev, R_SA_PEG_AFEBND0CFG4_OFFSET + i * BUNDLE_STEP, Data32And, Data32Or);
+    }
+  }
+  ///
+  /// g2rxctlepeak = 0x0 (DMI & PEG)
+  ///
+  for (i = 0; i < BundlesCount; i++) {
+    SaMmio32AndThenOr (DmiBar, Dev, R_SA_PEG_AFEBND0CFG4_OFFSET + i * BUNDLE_STEP, (UINT32) ~(0xF << 10), 0);
+  }
+  ///
+  /// AFEBNDSPARE[uneqmm] = 0x4 (HSW == A0: DMI & PEG)
+  ///
+  if ((CpuFamilyId == EnumCpuHsw) && (CpuSteppingId == EnumHswA0)) {
+    for (i = 0; i < BundlesCount; i++) {
+      SaMmio32AndThenOr (DmiBar, Dev, R_SA_PEG_AFEBND0CFG4_OFFSET + i * BUNDLE_STEP, (UINT32) ~(7 << 29), 4 << 29);
+    }
+  }
+  ///
+  /// AGCACQLEN = 0x2 (HSW == A0: DMI & PEG)
+  ///
+  if ((CpuFamilyId == EnumCpuHsw) && (CpuSteppingId == EnumHswA0)) {
+    for (i = 0; i < BundlesCount; i++) {
+      SaMmio32AndThenOr (DmiBar, Dev, R_SA_PEG_AFEBND0CFG5_OFFSET + i * BUNDLE_STEP, (UINT32) ~(3 << 7), 2 << 7);
+    }
+  }
+  ///
+  /// G2DFEC1CTL = 0x0 (HSW == A0: DMI & PEG)
+  ///
+  if ((CpuFamilyId == EnumCpuHsw) && (CpuSteppingId == EnumHswA0)) {
+    for (i = 0; i < BundlesCount; i++) {
+      SaMmio32AndThenOr (DmiBar, Dev, R_SA_PEG_AFEBND0CFG5_OFFSET + i * BUNDLE_STEP, (UINT32) ~(3 << 12), 0);
+    }
+  }
+  ///
+  /// RXSQEXCTL = 0x0 (DMI & PEG)
+  ///
+  Data32And = (UINT32) ~(BIT20 | BIT19 | BIT18);
+  Data32Or  = 0;
+  for (i = 0; i < BundlesCount; i++) {
+    SaMmio32AndThenOr (DmiBar, Dev, R_SA_PEG_AFEBND0CFG5_OFFSET + i * BUNDLE_STEP, Data32And, Data32Or);
+  }
+  ///
+  /// dfemfc = 0x3 (HSW == A0: DMI & PEG)
+  ///
+  if ((CpuFamilyId == EnumCpuHsw) && (CpuSteppingId == EnumHswA0)) {
+    for (i = 0; i < BundlesCount; i++) {
+      SaMmio32AndThenOr (DmiBar, Dev, R_SA_PEG_AFEBND0CFG5_OFFSET + i * BUNDLE_STEP, (UINT32) ~(3 << 21), 3 << 21);
+    }
+  }
+
+  ///
+  /// ICOMPGAIN = 0x6 (HSW == A0: DMI & PEG)
+  ///
+  if ((CpuFamilyId == EnumCpuHsw) && (CpuSteppingId == EnumHswA0)) {
+    VcuAddress = R_SA_VCU_AFECMNCFG0_ADDRESS_REV1;
+    VcuReadOp  = V_SA_VCU_OPCODE_READ_MMIO_REV1;
+    VcuWriteOp = V_SA_VCU_OPCODE_WRITE_MMIO_REV1;
+  } else {
+    VcuAddress = R_SA_VCU_AFECMNCFG0_ADDRESS_REV2;
+    VcuReadOp  = V_SA_VCU_OPCODE_READ_MMIO_REV2;
+    VcuWriteOp = V_SA_VCU_OPCODE_WRITE_MMIO_REV2;
+  }
+
+  if ((CpuFamilyId == EnumCpuHsw) && (CpuSteppingId == EnumHswA0)) {
+    if ((DmiBar != 0) || (IsSingleCall)) {
+      Data32  = SendVcuApiSequence (MchBar, VcuAddress, VcuReadOp, 0);
+      Data32 &= (UINT32) ~(BIT12 | BIT11 | BIT10 | BIT9);
+      Data32 |= 0x6 << 9;
+      SendVcuApiSequence (MchBar, VcuAddress, VcuWriteOp, Data32);
+    }
+  }
+
+  ///
+  /// PEGVCMSEL = 0x3 (PEG only)
+  ///
+  if (DmiBar == 0) {
+    Data32  = SendVcuApiSequence (MchBar, VcuAddress, VcuReadOp, 0);
+    Data32 &= (UINT32) ~(BIT29 | BIT28 | BIT27 | BIT26 | BIT25);
+    ///
+    /// Switch on
+    /// SwingControl 1 == Half
+    ///              2 == Full (Default)
+    ///
+    switch (SwingControl) {
+      case SA_SWING_HALF:
+        Data32 |= (UINT32) (0x0E << 25);
+        break;
+
+      default:
+      case SA_SWING_FULL:
+        Data32 |= (UINT32) (0x03 << 25);
+        break;
+    }
+    SendVcuApiSequence (MchBar, VcuAddress, VcuWriteOp, Data32);
+  }
+
+  ///
+  /// PH3EQFFEKNOBS = 0x8 (DMI & PEG)
+  ///
+  if ((CpuFamilyId == EnumCpuHsw) && (CpuSteppingId == EnumHswA0)) {
+    VcuAddress = R_SA_VCU_AFECMNCFG2_ADDRESS_REV1;
+  } else {
+    VcuAddress = R_SA_VCU_AFECMNCFG2_ADDRESS_REV2;
+  }
+
+  if ((CpuFamilyId == EnumCpuHsw) && (CpuSteppingId == EnumHswA0)) {
+    if ((DmiBar != 0) || (IsSingleCall)) {
+      Data32  = SendVcuApiSequence (MchBar, VcuAddress, VcuReadOp, 0);
+      Data32 &= (UINT32) ~(BIT30 | BIT29 | BIT28 | BIT27 | BIT26 | BIT25);
+      Data32 |= 0x8 << 25;
+      SendVcuApiSequence (MchBar, VcuAddress, VcuWriteOp, Data32);
+    }
+  }
+
+  ///
+  /// FIXUNCORRDATA = 0x0 (DMI & PEG)
+  ///
+  if ((CpuFamilyId == EnumCpuHsw) && (CpuSteppingId == EnumHswA0)) {
+    VcuAddress = R_SA_VCU_AFECMNCFG3_ADDRESS_REV1;
+  } else {
+    VcuAddress = R_SA_VCU_AFECMNCFG3_ADDRESS_REV2;
+  }
+
+  if ((CpuFamilyId == EnumCpuHsw) && (CpuSteppingId == EnumHswA0)) {
+    if ((DmiBar != 0) || (IsSingleCall)) {
+      Data32  = SendVcuApiSequence (MchBar, VcuAddress, VcuReadOp, 0);
+      Data32 &= (UINT32) ~(BIT20);
+      Data32 |= 0;
+      SendVcuApiSequence (MchBar, VcuAddress, VcuWriteOp, Data32);
+    }
+  }
+  ///
+  /// BLEGCTL = 0x0 (DMI & PEG)
+  ///
+  if ((DmiBar != 0) || (IsSingleCall)) {
+    Data32  = SendVcuApiSequence (MchBar, VcuAddress, VcuReadOp, 0);
+    Data32 &= (UINT32) ~(BIT28 | BIT27 | BIT26 | BIT25 | BIT24 | BIT23);
+    Data32 |= 0;
+    SendVcuApiSequence (MchBar, VcuAddress, VcuWriteOp, Data32);
+  }
+  if (((CpuFamilyId == EnumCpuHsw) && (CpuSteppingId == EnumHswA0)) &&
+      ((DmiBar      != 0)          || (IsSingleCall)              )) {
+    VcuAddress = R_SA_VCU_AFECMNCFG7_ADDRESS_REV1;
+    VcuReadOp  = V_SA_VCU_OPCODE_READ_CSR_REV1;
+    VcuWriteOp = V_SA_VCU_OPCODE_WRITE_CSR_REV1;
+
+    Data32 = SendVcuApiSequence (MchBar, VcuAddress, VcuReadOp, 0);
+    ///
+    /// VREFRXDET = 0x19 (PEG only)
+    ///
+    if ((CpuFamilyId == EnumCpuHsw) && (CpuSteppingId == EnumHswA0)) {
+      Data32 &= (UINT32) ~(BIT18 | BIT17 | BIT16 | BIT15 | BIT14);
+      Data32 |= 0x19 << 14;
+    }
+    ///
+    /// DFEFIX = 0x4 (PEG only)
+    ///
+    if ((CpuFamilyId == EnumCpuHsw) && (CpuSteppingId == EnumHswA0)) {
+      Data32 &= (UINT32) ~(BIT30 | BIT29 | BIT28);
+      Data32 |= 0x4 << 28;
+    }
+    SendVcuApiSequence (MchBar, VcuAddress, VcuWriteOp, Data32);
+  }
+
+
+  ///
+  /// RXDETECT_SAMPLE_TIME = 0x4 (PEG only)
+  ///
+  if ((CpuFamilyId == EnumCpuHsw) && (CpuSteppingId == EnumHswA0)) {
+    if (DmiBar == 0) {
+      Data32And = (UINT32) ~(BIT14 | BIT13 | BIT12 | BIT11 | BIT10 | BIT9 | BIT8 | BIT7);
+      Data32Or  = 0x4 << 7;
+      SaMmio32AndThenOr (DmiBar, Dev, R_SA_PEG_AFE_PWRON_OFFSET, Data32And, Data32Or);
+    }
+  }
+
+  ///
+  /// RXL0S_ENTRY_EXIT_TIMER = 0x00 (HSW == A0: DMI & PEG)
+  ///                        = 0x13 (HSW >= B0: DMI & PEG)
+  ///
+  Data32And = (UINT32) ~(BIT4 | BIT3 | BIT2 | BIT1 | BIT0);
+  if ((CpuFamilyId == EnumCpuHsw) && (CpuSteppingId == EnumHswA0)) {
+    Data32Or = 0x00;
+  } else {
+    Data32Or = 0x13;
+  }
+  SaMmio32AndThenOr (DmiBar, Dev, R_SA_PEG_AFE_PM_TMR_OFFSET, Data32And, Data32Or);
+
+  ///
+  /// Set 0xC38[6] = 0x1 (HSW == A0), 0x0 (HSW >= B0) (DMI & PEG)
+  ///
+  Data32And = (UINT32) ~(BIT6);
+  if ((CpuFamilyId == EnumCpuHsw) && (CpuSteppingId == EnumHswA0)) {
+    Data32Or = 0x1 << 6;
+  } else {
+    Data32Or = 0x0 << 6;
+  }
+  if (DmiBar == 0) {
+    McD1PciCfg16AndThenOr   (R_SA_PEG_CMNSPARE_OFFSET, Data32And, Data32Or);
+    McD1F1PciCfg16AndThenOr (R_SA_PEG_CMNSPARE_OFFSET, Data32And, Data32Or);
+    McD1F2PciCfg16AndThenOr (R_SA_PEG_CMNSPARE_OFFSET, Data32And, Data32Or);
+  } else {
+    Mmio32AndThenOr (DmiBar, R_SA_DMIBAR_CMNSPARE_OFFSET, Data32And, Data32Or);
+  }
+
+  ///
+  /// Set 0x260[1:0] = '10b' (DMI & PEG)
+  ///
+  Data32And = (UINT32) ~(BIT1 | BIT0);
+  Data32Or  = 0x2;
+  if (DmiBar == 0) {
+    McD1PciCfg16AndThenOr   (R_SA_PEG_CFG6_OFFSET, Data32And, Data32Or);
+    McD1F1PciCfg16AndThenOr (R_SA_PEG_CFG6_OFFSET, Data32And, Data32Or);
+    McD1F2PciCfg16AndThenOr (R_SA_PEG_CFG6_OFFSET, Data32And, Data32Or);
+  } else {
+    Mmio32AndThenOr (DmiBar, R_SA_DMIBAR_CFG6_OFFSET, Data32And, Data32Or);
+  }
+
+  ///
+  /// setdfelsbsel = 0
+  ///
+  for (i = 0; i < BundlesCount; i++) {
+    SaMmio32AndThenOr (DmiBar, Dev, R_SA_PEG_AFEBND0CFG0_OFFSET + i * BUNDLE_STEP, (UINT32) ~(3 << 26), 0);
+  }
+  ///
+  /// OFFCORGAIN = 0x3 (HSW >= A0)
+  ///
+  for (i = 0; i < BundlesCount; i++) {
+    SaMmio32AndThenOr (DmiBar, Dev, R_SA_PEG_AFEBND0CFG1_OFFSET + i * BUNDLE_STEP, (UINT32) ~(3 << 10), 3 << 10);
+  }
+
+  ///
+  /// fixtxrtermoffset = -3; (PEG only)
+  ///
+  if (DmiBar == 0) {
+    for (i = 0; i < BundlesCount; i++) {
+      SaMmio32AndThenOr (DmiBar, Dev, R_SA_PEG_AFEBND0CFG3_OFFSET + i * BUNDLE_STEP, (UINT32) ~(0x1F << 25), ((0x03 << 1) | 0x01) << 25);
+    }
+  }
+
+  ///
+  /// Set BND0SPARE[29:27] = '101b' (PEG)
+  ///
+  Data32And = (UINT32) ~(BIT29 | BIT28 | BIT27);
+  Data32Or  = (UINT32) 0x28000000;
+  for (i = 0; i < BundlesCount; i++) {
+    MmPci32AndThenOr (
+      0,
+      SA_PEG_BUS_NUM,
+      SA_PEG10_DEV_NUM,
+      SA_PEG10_FUN_NUM,
+      R_SA_PEG_BND0SPARE_OFFSET + (i * BUNDLE_STEP),
+      Data32And,
+      Data32Or
+      );
+  }
+  return;
+}
+#endif // DMI_FLAG || PEG_FLAG
+
+#ifdef PEG_FLAG
+VOID
+BubbleSort (
+  IN OUT DATA_SAMPLE Array[]
+  )
+/**
+  Bubble sort from DATA_SAMPLE
+
+  @param[in, out] - Array[]: array of DATA_SAMPLE
+
+  @retval None
+**/
+{
+  UINTN       n;
+  UINTN       i;
+  UINTN       j;
+  DATA_SAMPLE Temp;
+
+  n = (UINTN) Array[0].Count;
+
+  for (i = 1; i <= n; i++) {
+    for (j = n; j > i; j--) {
+      if (Array[j - 1].Data > Array[j].Data) {
+        Temp          = Array[j - 1];
+        Array[j - 1]  = Array[j];
+        Array[j]      = Temp;
+      }
+    }
+  }
+
+  return;
+}
+
+UINT32
+GetMiddleValue (
+  IN OUT DATA_SAMPLE Array[]
+  )
+/**
+  Get Middle Value from DATA_SAMPLE
+
+  @param[in, out] - Array[]: array of DATA_SAMPLE
+
+  @retval UINT32 : Middle Value of DATA_SAMPLE
+**/
+{
+  UINT32  n;
+
+  n = Array[0].Count;
+
+  return Array[n / 2 + 1].Data;
+}
+
+#ifdef EFI_DEBUG
+VOID
+DumpSamplerValues (
+  IN UINT32 DmiBar,
+  IN UINT8  CpuSteppingId,
+  IN UINTN  Dev,
+  IN UINTN  LanesCount
+  )
+/**
+  Dump Sampler Values
+
+  @param[in] DmiBar        - DMIBAR address
+  @param[in] CpuSteppingId - CPUID.1.EAX[3:0], CPU stepping ID
+  @param[in] Dev           - Device number
+  @param[in] LanesCount    - Value of Lanes
+
+  @retval None
+**/
+{
+  UINTN   Lane;
+  UINT32  Sampler;
+  UINT8   SampleData;
+
+  DEBUG ((EFI_D_INFO, "Lane DS0  DS1  ESP0 ESP1 ESM0 ESM1\n"));
+  for (Lane = 0; Lane < LanesCount; Lane++) {
+    DEBUG ((EFI_D_INFO, "%2d:  ", Lane));
+    for (Sampler = 0; Sampler < 6; Sampler++) {
+      SampleData = GetMonBus (DmiBar, Dev, Lane, 0x31 + Sampler, CpuSteppingId) & 0x3F;
+      DEBUG ((EFI_D_INFO, "%02X   ", SampleData));
+    }
+
+    DEBUG ((EFI_D_INFO, "\n"));
+  }
+
+  return;
+}
+#endif // EFI_DEBUG
+
+VOID
+SamplerCalibratePegPort (
+  IN EFI_PEI_SERVICES       **PeiServices,
+  IN PEI_STALL_PPI          *StallPpi,
+  IN UINT8                  CpuSteppingId,
+  IN UINTN                  Dev,
+  IN UINTN                  LanesCount,
+  IN UINTN                  HwStrap
+  )
+/**
+ This function performs the PEG Sampler Calibration for HSW on a given PEG controller
+ It also calls the Step 2 of PEG Recipe routine.
+
+  @param[in] PeiServices         - Pointer to the PEI services table
+  @param[in] StallPpi            - pointer to PEI_STALL_PPI
+  @param[in] CpuSteppingId       - CPUID.1.EAX[3:0], CPU stepping ID
+  @param[in] Dev                 - Device number
+  @param[in] LanesCount          - Value of Lanes
+  @param[in] HwStrap             - HwStrap configuration from FUSESCMN
+
+  @retval None
+**/
+{
+  UINTN       Iteration;
+  UINTN       PegSamplerIterations;
+  UINTN       Lane;
+  UINTN       i;
+  BOOLEAN     Peg11Present;
+  BOOLEAN     Peg12Present;
+  BOOLEAN     EarlyExit;
+  BOOLEAN     CodeFound;
+  UINT8       SampleData;
+  UINT32      Sampler;
+  UINT16      CodesFound;
+  UINT32      MiddleCode;
+  UINTN       OcDelay;
+
+  ///
+  /// Array of sampling data - 16 lanes max, 6 samplers per lane, up to MAX_CODES per sampler
+  /// Size is 3 * 16 * 6 * 11 = 3168 bytes
+  ///
+  DATA_SAMPLE SampleArray[16][6][MAX_CODES + 1];
+
+  PegSamplerIterations  = SA_PEG_SAMPLER_ITERATIONS;
+  Peg11Present          = FALSE;
+  Peg12Present          = FALSE;
+
+  if (LanesCount == 16) {
+    OcDelay = 10;
+  } else {
+    OcDelay = 20;
+  }
+
+  ZeroMem (&SampleArray, sizeof (SampleArray));
+
+  if (HwStrap == SA_PEG_x8_x8_x0) {
+    Peg11Present = TRUE;
+  }
+
+
+  if (HwStrap == SA_PEG_x8_x4_x4) {
+    Peg11Present  = TRUE;
+    Peg12Present  = TRUE;
+  }
+  ///
+  /// Dump the Sampler values before calibration
+  ///
+  DEBUG ((EFI_D_INFO, "--- Sampler values before calibration ---\n"));
+#ifdef EFI_DEBUG
+  DumpSamplerValues (0, CpuSteppingId, Dev, LanesCount);
+#endif // EFI_DEBUG
+  ///
+  /// Disable the link
+  ///
+  MmPci16Or   (0, SA_PEG_BUS_NUM, Dev, 0, R_SA_PEG_LCTL_OFFSET, BIT4);
+  if (Peg11Present) {
+    MmPci16Or (0, SA_PEG_BUS_NUM, Dev, 1, R_SA_PEG_LCTL_OFFSET, BIT4);
+  }
+  if (Peg12Present) {
+    MmPci16Or (0, SA_PEG_BUS_NUM, Dev, 2, R_SA_PEG_LCTL_OFFSET, BIT4);
+  }
+
+  ///
+  /// Delay 10 ms after link disable
+  ///
+  StallPpi->Stall (PeiServices, StallPpi, 10 * STALL_ONE_MILLI_SECOND);
+
+  ///
+  /// Override L0s and L1 - set bits 11, 13 & 15 of AFEOVR
+  ///
+  MmPci32Or   (0, SA_PEG_BUS_NUM, Dev, 0, R_SA_PEG_AFEOVR_OFFSET, 0xA800);
+  if (Peg11Present) {
+    MmPci32Or (0, SA_PEG_BUS_NUM, Dev, 1, R_SA_PEG_AFEOVR_OFFSET, 0xA800);
+  }
+  if (Peg12Present) {
+    MmPci32Or (0, SA_PEG_BUS_NUM, Dev, 2, R_SA_PEG_AFEOVR_OFFSET, 0xA800);
+  }
+
+  for (Iteration = 0; Iteration < PegSamplerIterations; Iteration++) {
+    PostCode ((UINT8) (Iteration / 100));
+    ///
+    /// First trigger OC on each lane
+    ///
+    for (Lane = 0; Lane < LanesCount; Lane++) {
+      SetLoadBus (0, Dev, Lane, 0x39, 0x1, CpuSteppingId);
+      SetLoadBus (0, Dev, Lane, 0x3A, 0xC, CpuSteppingId);
+    }
+    ///
+    /// Delay to give the OC time to complete
+    ///
+    StallPpi->Stall (PeiServices, StallPpi, OcDelay * STALL_ONE_MICRO_SECOND);
+
+    for (Lane = 0; Lane < LanesCount; Lane++) {
+      for (Sampler = 0; Sampler < 6; Sampler++) {
+        SampleData = GetMonBus (0, Dev, Lane, 0x31 + Sampler, CpuSteppingId) & 0x3F;
+
+        ///
+        /// SampleArray[Lane][Sampler][0].Count holds the number of distinct codes found so far
+        ///
+        CodeFound = FALSE;
+        for (i = 1; i <= SampleArray[Lane][Sampler][0].Count; ++i) {
+          if (SampleArray[Lane][Sampler][i].Data == SampleData) {
+            CodeFound = TRUE;
+            SampleArray[Lane][Sampler][i].Count++;
+            break;
+          }
+        }
+
+        if (!CodeFound) {
+          if (i > MAX_CODES) {
+            DEBUG ((EFI_D_ERROR, "ERROR: PEG dev=%d, lane=%d, sampler=%d, iteration=%d, found more than %d distinct codes!!!\n", Dev, Lane, Sampler, Iteration, MAX_CODES));
+            if (LanesCount == 16) {
+              PostCode ((UINT8) (ERROR_BY_16 >> 8));
+            } else {
+              PostCode ((UINT8) (ERROR_NOT_BY_16 >> 8));
+            }
+
+            EFI_DEADLOOP ();
+          }
+          ///
+          /// Increment the number of distinct codes found for this sampler
+          ///
+          SampleArray[Lane][Sampler][0].Count++;
+
+          ///
+          /// Save the new code
+          ///
+          SampleArray[Lane][Sampler][i].Data  = SampleData;
+          SampleArray[Lane][Sampler][i].Count = 1;
+        }
+      }
+    }
+    ///
+    /// Exit early if all the sampled lanes have more than 5 codes,
+    /// and we covered at least 20% of iterations.
+    /// Ignore the inactive lanes, these will only show one code.
+    ///
+    if (Iteration > PegSamplerIterations / 5) {
+      EarlyExit = TRUE;
+      for (Lane = 0; Lane < LanesCount; Lane++) {
+        for (Sampler = 0; Sampler < 6; Sampler++) {
+          CodesFound = SampleArray[Lane][Sampler][0].Count;
+          if ((CodesFound > 1) && (CodesFound < 5)) {
+            EarlyExit = FALSE;
+            break;
+          }
+        }
+
+        if (!EarlyExit) {
+          break;
+        }
+      }
+
+      if (EarlyExit) {
+        break;
+      }
+    }
+  }
+  ///
+  /// Iteration
+  ///
+  for (Lane = 0; Lane < LanesCount; Lane++) {
+    for (Sampler = 0; Sampler < 6; Sampler++) {
+      ///
+      /// Sort the codes for this Lane / Sampler
+      ///
+      BubbleSort (SampleArray[Lane][Sampler]);
+      ///
+      /// Find the middle value
+      ///
+      MiddleCode = GetMiddleValue (SampleArray[Lane][Sampler]);
+      ///
+      /// Set the middle calibration code
+      ///
+      SetLoadBus (0, Dev, Lane, 0x31 + Sampler, MiddleCode, CpuSteppingId);
+    }
+  }
+  ///
+  /// Restore AFEOVR
+  ///
+  MmPci32   (0, SA_PEG_BUS_NUM, Dev, 0, R_SA_PEG_AFEOVR_OFFSET) = 0;
+  if (Peg11Present) {
+    MmPci32 (0, SA_PEG_BUS_NUM, Dev, 1, R_SA_PEG_AFEOVR_OFFSET) = 0;
+  }
+  if (Peg12Present) {
+    MmPci32 (0, SA_PEG_BUS_NUM, Dev, 2, R_SA_PEG_AFEOVR_OFFSET) = 0;
+  }
+  ///
+  /// Delay 1 ms before link enable
+  ///
+  StallPpi->Stall (PeiServices, StallPpi, STALL_ONE_MILLI_SECOND);
+
+  ///
+  /// Enable the link
+  ///
+  MmPci16And   (0, SA_PEG_BUS_NUM, Dev, 0, R_SA_PEG_LCTL_OFFSET, ~BIT4);
+  if (Peg11Present) {
+    MmPci16And (0, SA_PEG_BUS_NUM, Dev, 1, R_SA_PEG_LCTL_OFFSET, ~BIT4);
+  }
+  if (Peg12Present) {
+    MmPci16And (0, SA_PEG_BUS_NUM, Dev, 2, R_SA_PEG_LCTL_OFFSET, ~BIT4);
+  }
+  ///
+  /// Dump the Sampler values after calibration
+  ///
+  DEBUG ((EFI_D_INFO, "--- Sampler values after calibration ---\n"));
+#ifdef EFI_DEBUG
+  DumpSamplerValues (0, CpuSteppingId, Dev, LanesCount);
+#endif // EFI_DEBUG
+  return;
+}
+
+VOID
+PegSamplerCalibration (
+  IN EFI_PEI_SERVICES       **PeiServices,
+  IN SA_PLATFORM_POLICY_PPI *SaPlatformPolicyPpi,
+  IN PEI_STALL_PPI          *StallPpi,
+  IN UINT8                  CpuSteppingId,
+  IN UINT8                  HwStrap
+  )
+/**
+ This function performs the PEG Sampler Calibration
+
+  @param[in] PeiServices         - Pointer to the PEI services table
+  @param[in] SaPlatformPolicyPpi - pointer to SA_PLATFORM_POLICY_PPI
+  @param[in] StallPpi            - pointer to PEI_STALL_PPI
+  @param[in] CpuSteppingId       - CPUID.1.EAX[3:0], CPU stepping ID
+  @param[in] HwStrap             - HwStrap configuration from FUSESCMN
+
+  @retval None
+**/
+{
+  UINT32  Data32;
+
+  ///
+  /// Calibrate PEG10/PEG11/PEG12 - 16 lanes total
+  ///
+  if (MmPci16 (0, 0, 1, 0, PCI_VID) != 0xFFFF) {
+    Data32 = MmPci32 (0, 0, 1, 0, R_SA_PEG_PEGSTS_OFFSET);
+    if (((Data32 & 0xFFFF) != 0) && (((Data32 >> 16) & 0x0F) >= 7)) {
+      SamplerCalibratePegPort (PeiServices, StallPpi, CpuSteppingId, SA_PEG10_DEV_NUM, 16, HwStrap);
+    }
+  }
+
+  return;
+}
+
+VOID
+PegGen2AutoSpeedDisable (
+  IN EFI_PEI_SERVICES                   **PeiServices,
+  IN SA_PLATFORM_POLICY_PPI             *SaPlatformPolicyPpi,
+  IN PEI_STALL_PPI                      *StallPpi,
+  IN SA_DATA_HOB                        *SaDataHob,
+  IN PEG_PORT                           *PegPortTable,
+  IN UINTN                              PegPortTableSize,
+  IN UINT8                              HwStrap
+  )
+/**
+ This function performs the PEG GEN2 Auto Speed Disable
+
+  @param[in] PeiServices         - Pointer to the PEI services table
+  @param[in] SaPlatformPolicyPpi - Pointer to SA_PLATFORM_POLICY_PPI
+  @param[in] StallPpi            - Pointer to PEI_STALL_PPI
+  @param[in] SaDataHob           - Pointer to SA_DATA_HOB
+  @param[in] PegPortTable        - Pointer to PEG Port Table
+  @param[in] PegPortTableSize    - Size of PEG Port Table
+  @param[in] HwStrap             - Furcation HW Strap Value
+
+  @retval None
+**/
+{
+  UINTN          PortIndex;
+  EFI_STATUS     Status;
+  EFI_BOOT_MODE  BootMode;
+  UINT8          DisableAutoSpeedUp;
+  UINT8          PegBus;
+  UINT8          PegDev;
+  UINT8          PegFunc;
+
+  DisableAutoSpeedUp = 0;
+  Status = (*PeiServices)->GetBootMode (PeiServices, &BootMode);
+  ASSERT_EFI_ERROR (Status);
+
+  for (PortIndex = 0; PortIndex < PegPortTableSize; PortIndex++) {
+    PegBus  = PegPortTable[PortIndex].Bus;
+    PegDev  = PegPortTable[PortIndex].Device;
+    PegFunc = PegPortTable[PortIndex].Function;
+
+    ///
+    /// If VC0 is still pending
+    /// And presence of an endpoint was detected, enable GEN2 auto speed disable
+    ///
+    if ((MmPci16 (0, PegBus, PegDev, PegFunc, PCI_VID                        ) != 0xFFFF) &&
+       ((MmPci16 (0, PegBus, PegDev, PegFunc, R_SA_PEG_VC0RSTS_OFFSET) & BIT1) != 0)      &&
+       ((MmPci16 (0, PegBus, PegDev, PegFunc, R_SA_PEG_SLOTSTS_OFFSET) & BIT6) != 0)) {
+      DisableAutoSpeedUp |= 1 << PegFunc;
+      MmPci16Or  (0, PegBus, PegDev, PegFunc, R_SA_PEG_LCTL_OFFSET, BIT4);
+      MmPci32Or  (0, PegBus, PegDev, PegFunc, R_SA_PEG_CFG5_OFFSET, BIT9);
+      MmPci16And (0, PegBus, PegDev, PegFunc, R_SA_PEG_LCTL_OFFSET, (UINT16)~(BIT4));
+    }
+  }
+  ///
+  /// If needed, reinitialize link after disable
+  ///
+  if (DisableAutoSpeedUp != 0) {
+    if ((BootMode == BOOT_ON_S3_RESUME) || (GetPchPmStatus (WarmBoot) == TRUE)) {
+      if ((SaDataHob != NULL) && (SaDataHob->PegDataValid)) {
+        if (SaDataHob->PegData.PegLinkFailMask != 0) {
+          ///
+          /// Even on warm boot/S3 resume, we still want to force checking of VC0 status
+          ///
+          SaDataHob->PegData.PegLinkFailMask = 0;
+        }
+      }
+    }
+    GracefulLinkStatusStall (PeiServices, StallPpi, SaPlatformPolicyPpi, SaDataHob, HwStrap);
+    for (PortIndex = 0; PortIndex < PegPortTableSize; PortIndex++) {
+      PegBus  = PegPortTable[PortIndex].Bus;
+      PegDev  = PegPortTable[PortIndex].Device;
+      PegFunc = PegPortTable[PortIndex].Function;
+      if (((DisableAutoSpeedUp >> PegFunc) & 1) == 1) {
+        ///
+        /// Retrain to allow link to reach GEN2
+        ///
+        MmPci16Or (0, PegBus, PegDev, PegFunc, R_SA_PEG_LCTL_OFFSET, BIT5);
+      }
+    }
+    ///
+    /// Ensure all links are now ready
+    ///
+    if ((BootMode == BOOT_ON_S3_RESUME) || (GetPchPmStatus (WarmBoot) == TRUE)) {
+      if ((SaDataHob != NULL) && (SaDataHob->PegDataValid)) {
+        if (SaDataHob->PegData.PegLinkFailMask != 0) {
+          ///
+          /// Even on warm boot/S3 resume, we still want to force checking of VC0 status
+          ///
+          SaDataHob->PegData.PegLinkFailMask = 0;
+        }
+      }
+    }
+    GracefulLinkStatusStall (PeiServices, StallPpi, SaPlatformPolicyPpi, SaDataHob, HwStrap);
+    DEBUG ((EFI_D_INFO, "PEG Link Status after auto speed disable:\n"));
+    for (PortIndex = 0; PortIndex < PegPortTableSize; PortIndex++) {
+      PegBus  = PegPortTable[PortIndex].Bus;
+      PegDev  = PegPortTable[PortIndex].Device;
+      PegFunc = PegPortTable[PortIndex].Function;
+      ReportPcieLinkStatus (PegBus, PegDev, PegFunc);
+    }
+  }
+}
+
+VOID
+PciExpressInit (
+  IN EFI_PEI_SERVICES                   **PeiServices,
+  IN SA_PLATFORM_POLICY_PPI             *SaPlatformPolicyPpi
+  )
+/**
+  Initialize the SA PciExpress in PEI
+
+  @param[in] PeiServices          - Pointer to the PEI services table
+  @param[in] SaPlatformPolicyPpi  - SaPlatformPolicyPpi to access the GtConfig related information
+**/
+{
+  UINT8               PegBus;
+  UINT8               PegDev;
+  UINT8               PegFunc;
+  UINT8               PegIndex;
+  UINT8               HwStrap;
+  UINT64              MchBar;
+  UINT64              DmiBar;
+  BOOLEAN             DisableFun0;
+  BOOLEAN             DisableFun1;
+  BOOLEAN             DisableFun2;
+  BOOLEAN             DisableLinkFunc0;
+  EFI_STATUS          Status;
+  CPU_FAMILY          CpuFamilyId;
+  CPU_STEPPING        CpuSteppingId;
+  UINTN               PegComplete;
+  UINT16              Peg10Speed;
+  UINT16              Peg11Speed;
+  UINT16              Peg12Speed;
+  UINT8               SwingControl;
+  UINT8               Gen3Capable;
+  UINT8               i;
+  PEI_STALL_PPI       *StallPpi;
+  UINT32              Data32;
+  UINT32              CapOffset;
+  BOOLEAN             AnyGen3Endpoint;
+  UINT8               FullSwing;
+  UINT8               PreCursor;
+  UINT8               Cursor;
+  UINT8               PostCursor;
+
+  PEG_PORT            PegPortTable[] = {
+    ///
+    ///  Bus, Device, Function, Index, PresenceDetect, MaxLinkWidth, EndpointMaxLinkSpeed
+    ///
+    { SA_PEG_BUS_NUM, SA_PEG10_DEV_NUM, SA_PEG10_FUN_NUM, 0, FALSE, 16, 0}
+//AMI_OVERRIDE>>
+#if RC_PEG_1 == 1
+    ,{ SA_PEG_BUS_NUM, SA_PEG11_DEV_NUM, SA_PEG11_FUN_NUM, 1, FALSE,  8, 0}
+#endif
+#if RC_PEG_2 == 1
+    ,{ SA_PEG_BUS_NUM, SA_PEG12_DEV_NUM, SA_PEG12_FUN_NUM, 2, FALSE,  4, 0}
+#endif
+//AMI_OVERRIDE<<
+  };
+  SA_DATA_HOB         *SaDataHob;
+  BOOLEAN             S3Flow;
+  UINT8               LinkStatusGood;
+  BOOLEAN             FunctionExists;
+  UINT8               UnusedLanes;
+  UINT8               CtrlMaxLinkWidth;
+  UINT8               EpMaxLinkWidth;
+  UINT16              LoopCount;
+  UINT8               MaxBndlPwrdnCount;
+  UINT8               BndlPwrdnCount;
+  UINT8               PwrDnUnusedBundlesSetupData;
+
+  HwStrap                     = SA_PEG_x16_x0_x0;
+  DisableFun0                 = FALSE;
+  DisableFun1                 = FALSE;
+  DisableFun2                 = FALSE;
+  DisableLinkFunc0            = FALSE;
+  MchBar                      = McD0PciCfg64 (R_SA_MCHBAR) &~BIT0;
+  DmiBar                      = McD0PciCfg64 (R_SA_DMIBAR) &~BIT0;
+  PegDev                      = 0x1;
+
+  Peg10Speed                  = 0;
+  Peg11Speed                  = 0;
+  Peg12Speed                  = 0;
+  SwingControl                = SaPlatformPolicyPpi->PcieConfig->PegSwingControl;
+  SaDataHob                   = NULL;
+  S3Flow                      = FALSE;
+  Gen3Capable                 = TRUE;
+  AnyGen3Endpoint             = FALSE;
+  FullSwing                   = 0;
+  CtrlMaxLinkWidth            = 0;
+  EpMaxLinkWidth              = 0;
+  UnusedLanes                 = 0;
+  LoopCount                   = 0;
+  MaxBndlPwrdnCount           = 0;
+  BndlPwrdnCount              = 0;
+  PwrDnUnusedBundlesSetupData = 0xFF;
+
+  ///
+  /// Check to see if PEG exists and leave initialization function if non-existant
+  ///
+  if (McD1PciCfg16 (PCI_VID) == 0xFFFF) {
+    DEBUG ((EFI_D_INFO, "PEG controller not detected\n"));
+    return;
+  }
+
+  ///
+  /// Read the HW straps - Bus 0, Device 1, Fun 0, Reg 0x504 BIT17,16
+  /// Fun 1 & 2 disabled = Pcie 1x16, Fun 2 disabled = Pcie 2x8
+  /// Fun 1 & 2 enabled = Pcie 1x8 + (2+4)
+  ///
+  HwStrap = (UINT8) ((MmPci32 (0, SA_MC_BUS, PegDev, 0, R_SA_PEG_FUSESCMN_OFFSET) >> 16) & 0x03);
+  DEBUG ((EFI_D_INFO, "PEG HW Strap value %x\n", HwStrap));
+
+  Status = (*PeiServices)->LocatePpi (PeiServices, &gPeiStallPpiGuid, 0, NULL, &StallPpi);
+  ASSERT_EFI_ERROR (Status);
+
+  ///
+  /// Update PEG LCAP.MLW based on PEG port Split configuration.
+  /// This is Write-Once field, so keep the values in the structure,
+  /// and write later together with LCAP.MLS.
+  ///
+  switch (HwStrap) {
+    case SA_PEG_x8_x4_x4:
+      ///
+      /// 0x0: Device 1 functions 1 and 2 enabled
+      /// PEG10: x16->x8, PEG11: x8->x4, PEG12: x4
+      ///
+      PegPortTable[0].MaxLinkWidth  = 8;
+//AMI_OVERRIDE >>
+#if RC_PEG_1 == 1
+      PegPortTable[1].MaxLinkWidth  = 4;
+#endif
+//AMI_OVERRIDE <<
+      break;
+
+
+    case SA_PEG_x8_x8_x0:
+      ///
+      /// 0x2: Device 1 function 1 enabled; function 2 disabled
+      /// PEG10: x16->x8, PEG11: x8, PEG12: N/A
+      ///
+      PegPortTable[0].MaxLinkWidth = 8;
+      break;
+
+    default:
+    case SA_PEG_x16_x0_x0:
+      break;
+  }
+
+  CpuFamilyId   = GetCpuFamily();
+  CpuSteppingId = GetCpuStepping();
+
+  ///
+  /// Read PEG Gen3 Fuse to see if it should override programming
+  ///
+  if (MmPci32 (0, SA_MC_BUS, SA_MC_DEV, SA_MC_FUN, R_SA_MC_CAPID0_B) & BIT20) {
+    Gen3Capable = FALSE;
+    DEBUG ((EFI_D_INFO, "PEG Gen3 Fused off\n"));
+  }
+
+  ///
+  /// Gen3 Preset Search: 0 = Disabled, 1 = Enabled (default)
+  ///
+  if (SaPlatformPolicyPpi->PcieConfig->PegGen3PresetSearch == 2) {
+    SaPlatformPolicyPpi->PcieConfig->PegGen3PresetSearch = 1;
+  }
+
+  ///
+  /// Restore SA Data HOB's PEG data
+  ///
+  if (SaPlatformPolicyPpi->Revision >= SA_PLATFORM_POLICY_PPI_REVISION_2) {
+    SaDataHob = (SA_DATA_HOB *) GetFirstGuidHob (&gSaDataHobGuid);
+
+    if (SaDataHob != NULL) {
+      if (SaPlatformPolicyPpi->PcieConfig->PegDataPtr != NULL) {
+        DEBUG ((EFI_D_INFO, "\nRestore SA PEG DATA from previous boot: Size=%X\n", sizeof (SA_PEG_DATA)));
+        CopyMem (&(SaDataHob->PegData), SaPlatformPolicyPpi->PcieConfig->PegDataPtr, sizeof (SA_PEG_DATA));
+        SaDataHob->PegDataValid = TRUE;
+        if ((SaDataHob->PegData.PegGen3PresetSearch != SaPlatformPolicyPpi->PcieConfig->PegGen3PresetSearch) && (SaPlatformPolicyPpi->PcieConfig->PegGen3PresetSearch != 1)) {
+          ///
+          /// Zero out previous boot GEN3 Preset data so old data won't be re-used when PegGen3PresetSearch re-enabled later
+          ///
+          DEBUG ((EFI_D_INFO, "\nPegGen3PresetSearch is disabled, Clear old Preset data\n"));
+          for (PegIndex = 0; PegIndex < SA_PEG_MAX_FUN; PegIndex++) {
+            SaDataHob->PegData.EndPointVendorIdDeviceId[PegIndex] = 0;
+            for (i = 0; i < SA_PEG_MAX_LANE; i++) {
+              SaDataHob->PegData.BestPreset[i] = 0;
+            }
+          }
+        }
+      }
+      SaDataHob->PegData.PegGen3PresetSearch = SaPlatformPolicyPpi->PcieConfig->PegGen3PresetSearch;
+    }
+  }
+
+  ///
+  /// Perform PEG Pre-Detection steps
+  ///
+  for (PegComplete = 0; PegComplete < ((sizeof (PegPortTable)) / (sizeof (PEG_PORT))); PegComplete++) {
+    PegBus  = PegPortTable[PegComplete].Bus;
+    PegDev  = PegPortTable[PegComplete].Device;
+    PegFunc = PegPortTable[PegComplete].Function;
+    PegPreDetectionSteps (PegBus, PegDev, PegFunc, SaPlatformPolicyPpi);
+  }
+
+  ///
+  /// Perform PEG Recipe steps
+  ///
+  DEBUG ((EFI_D_INFO, "PEG Recipe...\n"));
+  PegDmiRecipe (SaPlatformPolicyPpi, (UINT32) MchBar, 0, SA_PEG10_DEV_NUM, SwingControl);
+
+  ///
+  /// Perform PEG Gen3 Equalization steps and load preset values
+  ///
+  if (Gen3Capable == TRUE) {
+    if (SaPlatformPolicyPpi->PcieConfig->PegGen3Equalization != 0) {
+      DEBUG ((EFI_D_INFO, "PEG Gen3 Equalization...\n"));
+      PegGen3Equalization (SaPlatformPolicyPpi, CpuSteppingId, HwStrap);
+    }
+  }
+
+  ///
+  /// PEG Sampler Calibration: 0 = Disabled (default), 1 = Enabled
+  ///
+  if (SaPlatformPolicyPpi->PcieConfig->PegSamplerCalibrate == 2) {
+    SaPlatformPolicyPpi->PcieConfig->PegSamplerCalibrate = 0;
+  }
+
+  if (SaPlatformPolicyPpi->PcieConfig->PegSamplerCalibrate == 1) {
+    ///
+    /// Back up the current PEG speed in LCTL2.TLS[3:0]
+    ///
+    Peg10Speed = McD1PciCfg16   (R_SA_PEG_LCTL2_OFFSET) & 0x0F;
+    Peg11Speed = McD1F1PciCfg16 (R_SA_PEG_LCTL2_OFFSET) & 0x0F;
+    Peg12Speed = McD1F2PciCfg16 (R_SA_PEG_LCTL2_OFFSET) & 0x0F;
+    ///
+    /// Set the PEG speed in LCTL2.TLS[3:0] to Gen1 before clearing DEFER_OC,
+    /// in order to run Sampler Calibration at Gen1.
+    ///
+    McD1PciCfg16AndThenOr   (R_SA_PEG_LCTL2_OFFSET, 0xFFF0, 1);
+    McD1F1PciCfg16AndThenOr (R_SA_PEG_LCTL2_OFFSET, 0xFFF0, 1);
+    McD1F2PciCfg16AndThenOr (R_SA_PEG_LCTL2_OFFSET, 0xFFF0, 1);
+  }
+
+  for (PegComplete = 0; PegComplete < ((sizeof (PegPortTable)) / (sizeof (PEG_PORT))); PegComplete++) {
+    ///
+    /// Program the PEG speed according to Setup options: Auto/Gen1/2/3
+    /// We have to do it before endpoint enumeration, so that uncompliant card
+    /// can train at a lower speed.
+    ///
+    ConfigurePegGenX (
+      PeiServices,
+      StallPpi,
+      SaPlatformPolicyPpi,
+      PegPortTable,
+      PegComplete,
+      CpuSteppingId,
+      Gen3Capable
+      );
+  }
+
+  ///
+  /// RxCEM Loopback (LPBK) Mode
+  ///
+  if ((SaPlatformPolicyPpi->Revision >= SA_PLATFORM_POLICY_PPI_REVISION_3) && (SaPlatformPolicyPpi->PcieConfig->RxCEMLoopback == 1)) {
+    McD1PciCfg32AndThenOr (R_SA_PEG_PEGTST_OFFSET, ~(BIT19|BIT18|BIT17|BIT16), (SaPlatformPolicyPpi->PcieConfig->RxCEMLoopbackLane & 0xF) << 16);
+    for (i = 0; i < SA_PEG_MAX_LANE; i++) {
+      if (i == SaPlatformPolicyPpi->PcieConfig->RxCEMLoopbackLane) {
+        McD1PciCfg32And (R_SA_PEG_AFELN0CFG0_OFFSET + LANE_STEP * i, ~BIT9);
+      } else {
+        McD1PciCfg32Or (R_SA_PEG_AFELN0CFG0_OFFSET + LANE_STEP * i, BIT9);
+      }
+    }
+  }
+
+  ///
+  /// Enable 3-OC retry for PEG(0/1/2). HSW/CRW earlier than C0.
+  ///
+  if (((CpuFamilyId == EnumCpuHsw) && (CpuSteppingId < EnumHswC0)) ||
+      ((CpuFamilyId == EnumCpuCrw) && (CpuSteppingId < EnumCrwC0))) {
+    McD1PciCfg32Or    (R_SA_PEG_AFE_PWRON_OFFSET, BIT5);
+    McD1F1PciCfg32Or  (R_SA_PEG_AFE_PWRON_OFFSET, BIT5);
+    McD1F2PciCfg32Or  (R_SA_PEG_AFE_PWRON_OFFSET, BIT5);
+  }
+
+  ///
+  /// Bypass phase2
+  ///
+  Data32  = McD1PciCfg32 (R_SA_PEG_EQCFG_OFFSET);
+  Data32 |= BIT15 | BIT1;
+  McD1PciCfg32 (R_SA_PEG_EQCFG_OFFSET) = Data32;
+
+  ///
+  /// Clear DEFER_OC in offset 0xC24[16] on all PEG controllers to start the PEG training
+  ///
+  McD1PciCfg32And   (R_SA_PEG_AFE_PWRON_OFFSET, ~BIT16);
+  McD1F1PciCfg32And (R_SA_PEG_AFE_PWRON_OFFSET, ~BIT16);
+  McD1F2PciCfg32And (R_SA_PEG_AFE_PWRON_OFFSET, ~BIT16);
+
+  ///
+  /// Delay for 100ms to meet the timing requirements of the PCI Express Base
+  /// Specification, Revision 1.0A, Section 6.6 ("...software must wait at least
+  /// 100 ms from the end of reset of one or more device before it is permitted
+  /// to issue Configuration Requests to those devices").
+  ///
+  GracefulLinkStatusStall (PeiServices, StallPpi, SaPlatformPolicyPpi, SaDataHob, HwStrap);
+
+  PegGen2AutoSpeedDisable (PeiServices,
+                           SaPlatformPolicyPpi,
+                           StallPpi,
+                           SaDataHob,
+                           &(PegPortTable[0]),
+                           ((sizeof (PegPortTable)) / (sizeof (PEG_PORT))),
+                           HwStrap);
+
+  ///
+  /// Read the presence detect bit for each PEG port - must be done before sampler calibration
+  ///
+  for (PegComplete = 0; PegComplete < ((sizeof (PegPortTable)) / (sizeof (PEG_PORT))); PegComplete++) {
+    PegBus  = PegPortTable[PegComplete].Bus;
+    PegDev  = PegPortTable[PegComplete].Device;
+    PegFunc = PegPortTable[PegComplete].Function;
+    if (( MmPci16 (0, PegBus, PegDev, PegFunc, PCI_VID                        ) != 0xFFFF) &&
+        ((MmPci16 (0, PegBus, PegDev, PegFunc, R_SA_PEG_SLOTSTS_OFFSET) & BIT6) !=      0)) {
+      PegPortTable[PegComplete].PresenceDetect = TRUE;
+
+      ///
+      /// Read the endpoint's Max Link Speed
+      ///
+      MmPci32AndThenOr (0, PegBus, PegDev, PegFunc, PCI_PBUS, 0xFF0000FF, 0x00010100);
+      MmPci16 (0, 1, 0, 0, PCI_VID) = 0;
+      CapOffset = PcieFindCapId (1, 0, 0, EFI_PCI_CAPABILITY_ID_PCIEXP);
+      if (CapOffset != 0) {
+        Data32 = MmPci32 (0, 1, 0, 0, CapOffset + 0xC);
+        PegPortTable[PegComplete].EndpointMaxLinkSpeed = Data32 & 0xF;
+        if (PegPortTable[PegComplete].EndpointMaxLinkSpeed >= 0x3) {
+          AnyGen3Endpoint = TRUE;
+        }
+      }
+      MmPci32And (0, PegBus, PegDev, PegFunc, PCI_PBUS, 0xFF0000FF);
+    }
+  }
+  DEBUG ((EFI_D_INFO, "Presence detect table...\n"));
+  for (PegComplete = 0; PegComplete < ((sizeof (PegPortTable)) / (sizeof (PEG_PORT))); PegComplete++) {
+    DEBUG ((EFI_D_INFO, " PEG%d%d PresenceDetect: %x. EndpointMaxLinkSpeed: %x.\n",
+            PegPortTable[PegComplete].Device,
+            PegPortTable[PegComplete].Function,
+            PegPortTable[PegComplete].PresenceDetect,
+            PegPortTable[PegComplete].EndpointMaxLinkSpeed));
+  }
+
+  ///
+  /// If any Gen3 device, setup equalization values and retrain link
+  ///
+  if (AnyGen3Endpoint &&
+      (((CpuFamilyId == EnumCpuHsw) && (CpuSteppingId >= EnumHswB0)) ||
+       ((CpuFamilyId == EnumCpuCrw) && (CpuSteppingId >= EnumCrwB0)))) {
+    ///
+    /// Program presets based upon endpoint fullswing value
+    ///
+    for (i = 0; i < SA_PEG_MAX_LANE; i++) {
+      switch (i) {
+        case  0:
+          GetLinkPartnerFullSwing (i, &FullSwing);
+          break;
+        case  8:
+          if (PegPortTable[1].PresenceDetect) {
+            GetLinkPartnerFullSwing (i, &FullSwing);
+          }
+          break;
+        case 12:
+          if (PegPortTable[2].PresenceDetect) {
+            GetLinkPartnerFullSwing (i, &FullSwing);
+          }
+          break;
+        default:
+          break;
+      }
+      GetCoefficientsFromPreset (SaPlatformPolicyPpi->PcieConfig->Gen3EndPointPreset[i], FullSwing, &PreCursor, &Cursor, &PostCursor);
+      SetPartnerTxCoefficients (i, &PreCursor, &Cursor, &PostCursor);
+    }
+
+    ///
+    /// Redo EQ
+    ///
+    for (PegComplete = 0; PegComplete < ((sizeof (PegPortTable)) / (sizeof (PEG_PORT))); PegComplete++) {
+      if (PegPortTable[PegComplete].PresenceDetect) {
+        PegBus  = PegPortTable[PegComplete].Bus;
+        PegDev  = PegPortTable[PegComplete].Device;
+        PegFunc = PegPortTable[PegComplete].Function;
+        MmPci32Or (0, PegBus, PegDev, PegFunc, R_SA_PEG_LCTL3_OFFSET, BIT0);  ///< DOEQ
+        MmPci16Or (0, PegBus, PegDev, PegFunc, R_SA_PEG_LCTL_OFFSET, BIT5);   ///< Retrain link
+      }
+    }
+    for (PegComplete = 0; PegComplete < ((sizeof (PegPortTable)) / (sizeof (PEG_PORT))); PegComplete++) {
+      if (PegPortTable[PegComplete].PresenceDetect) {
+        WaitForL0 (PeiServices, StallPpi, &(PegPortTable[PegComplete]), FALSE);
+      }
+    }
+  }
+
+  ///
+  /// Sampler Calibration
+  ///
+  if (SaPlatformPolicyPpi->PcieConfig->PegSamplerCalibrate == 1) {
+    DEBUG ((EFI_D_INFO, "PEG SamplerCalibration...\n"));
+    PegSamplerCalibration (PeiServices, SaPlatformPolicyPpi, StallPpi, CpuSteppingId, HwStrap);
+
+    ///
+    /// Restore the PEG speed
+    ///
+    McD1PciCfg16AndThenOr   (R_SA_PEG_LCTL2_OFFSET, 0xFFF0, Peg10Speed);
+    McD1F1PciCfg16AndThenOr (R_SA_PEG_LCTL2_OFFSET, 0xFFF0, Peg11Speed);
+    McD1F2PciCfg16AndThenOr (R_SA_PEG_LCTL2_OFFSET, 0xFFF0, Peg12Speed);
+
+    ///
+    /// Delay 100ms to let endpoint train properly
+    ///
+    StallPpi->Stall (PeiServices, StallPpi, 100 * STALL_ONE_MILLI_SECOND);
+  }
+  ///
+  /// Gen3 Preset Search: 0 = Disabled, 1 = Enabled (default)
+  ///
+  if (SaPlatformPolicyPpi->PcieConfig->PegGen3PresetSearch == 2) {
+    SaPlatformPolicyPpi->PcieConfig->PegGen3PresetSearch = 1;
+  }
+
+  if (SaPlatformPolicyPpi->PcieConfig->PegGen3PresetSearch == 1) {
+    PegGen3PresetSearch (PeiServices, SaPlatformPolicyPpi, StallPpi, SaDataHob);
+  }
+
+  ///
+  /// After last equalization, set PH3 bypass
+  ///
+  McD1PciCfg32Or (R_SA_PEG_EQCFG_OFFSET, BIT15 | BIT14);
+
+  ///
+  /// Scan PEG Ports for device population
+  ///
+  DEBUG ((EFI_D_INFO, "PEG Ports Scanning starts.\n"));
+  for (PegComplete = 0; PegComplete < ((sizeof (PegPortTable)) / (sizeof (PEG_PORT))); PegComplete++) {
+
+    PegBus    = PegPortTable[PegComplete].Bus;
+    PegDev    = PegPortTable[PegComplete].Device;
+    PegFunc   = PegPortTable[PegComplete].Function;
+    PegIndex  = PegPortTable[PegComplete].Index;
+
+    ///
+    /// Check for a card presence in the PEG slot, or if the PEG port exists.
+    ///
+    if ((MmPci16 (0, PegBus, PegDev, PegFunc, PCI_VID) == 0xFFFF) ||
+        (PegPortTable[PegComplete].PresenceDetect == FALSE)) {
+      if (SaPlatformPolicyPpi->PcieConfig->AlwaysEnablePeg == 0) {
+        goto PegDisable;
+      }
+    } else {
+      if (SaPlatformPolicyPpi->PcieConfig->AlwaysEnablePeg == 0) {
+        ///
+        /// Set PEG PortBus = 1 to Read Endpoint.
+        ///
+        MmPci32AndThenOr (0, PegBus, PegDev, PegFunc, PCI_PBUS, 0xFF0000FF, 0x00010100);
+
+        ///
+        /// A config write is required in order for the device to re-capture the Bus number,
+        /// according to PCI Express Base Specification, 2.2.6.2
+        /// Write to a read-only register VendorID to not cause any side effects.
+        ///
+        MmPci16 (0, 1, 0, 0, PCI_VID) = 0;
+
+        ///
+        /// Negotiation Done?
+        ///
+        if ((MmPci16 (0, PegBus, PegDev, PegFunc, R_SA_PEG_VC0RSTS_OFFSET) & BIT1) != 0) {
+          goto PegDisable;
+        }
+
+        ///
+        /// Restore bus numbers on the PEG bridge.
+        ///
+        MmPci32And (0, PegBus, PegDev, PegFunc, PCI_PBUS, 0xFF0000FF);
+      }
+
+      if (SaPlatformPolicyPpi->Revision >= SA_PLATFORM_POLICY_PPI_REVISION_8) {
+        PwrDnUnusedBundlesSetupData = SaPlatformPolicyPpi->PcieConfig->PowerDownUnusedBundles[PegIndex];
+      } else {
+        PwrDnUnusedBundlesSetupData = 0xFF; ///< Forced to AUTO mode for calculating unused bundles to powerdown
+      }
+
+      if (PwrDnUnusedBundlesSetupData == 0xff) { ///< AUTO mode for calculating unused bundles to powerdown
+        ///
+        /// Read the controller's Max Link Width
+        ///
+        CtrlMaxLinkWidth = (UINT8) ((MmPci32 (0, PegBus, PegDev, PegFunc, R_SA_PEG_LCAP_OFFSET) >> 4) & 0x3F);
+
+        ///
+        /// Read the endpoint's Max Link Width
+        ///
+
+        ///
+        /// Set PEG PortBus = 1 to Read Endpoint.
+        ///
+        MmPci32AndThenOr (0, PegBus, PegDev, PegFunc, PCI_PBUS, 0xFF0000FF, 0x00010100);
+
+        ///
+        /// A config write is required in order for the device to re-capture the Bus number,
+        /// according to PCI Express Base Specification, 2.2.6.2
+        /// Write to a read-only register VendorID to not cause any side effects.
+        ///
+        MmPci16 (0, 1, 0, 0, PCI_VID) = 0;
+
+        ///
+        /// Check if the device actually got mapped into config space,
+        /// if the device wasn't able to be mapped into config space then
+        /// it's possible that it's a test card or some other device that
+        /// does not support config space.  In that case our only option is
+        /// to assume that the link trains to its max width and use that to
+        /// determine which bundles to power down
+        ///
+        if (MmPci32 (0, 1, 0, 0, PCI_VID) == 0xFFFFFFFF) {
+          EpMaxLinkWidth = (UINT8) ((MmPci16 (0, PegBus, PegDev, PegFunc, R_SA_PEG_LSTS_OFFSET) & 0x3f0) >> 4);
+          DEBUG ((EFI_D_INFO,
+                  "PEG%d%d - Endpoint not responding to PCI config space access, assuming negotiated width (X%d) is max width\n",
+                  PegDev,
+                  PegFunc,
+                  EpMaxLinkWidth
+                ));
+        } else {
+          CapOffset = PcieFindCapId (1, 0, 0, EFI_PCI_CAPABILITY_ID_PCIEXP);
+          if (CapOffset != 0) {
+            EpMaxLinkWidth = (UINT8) ((MmPci32 (0, 1, 0, 0, CapOffset + 0xC) >> 4) & 0x3F);
+          }
+        }
+
+        ///
+        /// Restore bus numbers on the PEG bridge.
+        ///
+        MmPci32And (0, PegBus, PegDev, PegFunc, PCI_PBUS, 0xFF0000FF);
+
+        if (CtrlMaxLinkWidth > EpMaxLinkWidth) {
+          UnusedLanes = CtrlMaxLinkWidth - EpMaxLinkWidth;
+        } else {
+          UnusedLanes = 0;
+        }
+
+        BndlPwrdnCount  = (UnusedLanes / 2); 
+
+        DEBUG ((EFI_D_INFO, "CtrlMLW[%d]. EpMLW[%d]. UnusedLanes[%d]. BndlPwrdnCount[%d].\n", CtrlMaxLinkWidth, EpMaxLinkWidth, UnusedLanes, BndlPwrdnCount));
+        } else if (PwrDnUnusedBundlesSetupData != 0) { ///< User selection mode: 1...8 unused bundles
+          BndlPwrdnCount = PwrDnUnusedBundlesSetupData;
+          DEBUG ((EFI_D_INFO, "BndlPwrdnCount[%d].\n", BndlPwrdnCount));
+        }
+
+      ///
+      /// PowerOff unused lanes for PEGs
+      ///
+      if (((CpuFamilyId == EnumCpuHsw) && (CpuSteppingId >= EnumHswC0)) ||
+          ((CpuFamilyId == EnumCpuCrw) && (CpuSteppingId >= EnumCrwC0))) {
+        if (PwrDnUnusedBundlesSetupData != 0) {
+          MaxBndlPwrdnCount = GetMaxBundles(PeiServices, PegFunc, HwStrap);
+          if (BndlPwrdnCount > MaxBndlPwrdnCount) {
+            BndlPwrdnCount = MaxBndlPwrdnCount;
+            DEBUG ((EFI_D_INFO+EFI_D_ERROR, "BndlPwrdnCount violation! Overriding BndlPwrdnCount! BndlPwrdnCount[%d].\n", BndlPwrdnCount));
+          }
+          PowerDownUnusedBundles(PeiServices, PegFunc, HwStrap, BndlPwrdnCount);
+        }
+      }
+
+      ///
+      /// Additional Programming Steps for PEGs
+      ///
+      DEBUG ((EFI_D_INFO, "Run AdditionalPegProgramSteps on PEG%x%x!\n", PegDev, PegFunc));
+      AdditionalPegProgramSteps (SaPlatformPolicyPpi, PegBus, PegDev, PegFunc);
+    }
+
+    if ((HwStrap == SA_PEG_x16_x0_x0) && (PegIndex == 0)) {
+      DisableFun1 = TRUE;
+      DisableFun2 = TRUE;
+      break;
+    }
+    if ((HwStrap == SA_PEG_x8_x8_x0) && (PegIndex == 1)) {
+      DisableFun2 = TRUE;
+      break;
+    }
+    if ((HwStrap == SA_PEG_x8_x4_x4) && (PegIndex == 2)) {
+      break;
+    }
+
+    continue;
+
+PegDisable:
+    ///
+    /// SA_PEG_x16_x0_x0 Mode: in this mode, PEG11 and PEG12 need to be Disabled by BIOS in this driver.
+    /// Only PEG10 needs to be checked (whether has a VGA device on it) and disabled if not.
+    ///
+    /// SA_PEG_x8_x8_x0 Mode: in this mode, PEG12 needs to be disabled, PEG10 and PEG11
+    /// need to be checked and disabled if no device installed.
+    ///
+    ///
+    /// SA_PEG_x8_x4_x4 Mode: in this mode, all PEG10, PEG11 and PEG12 devices
+    /// need to be checked and disabled if no device installed.
+    ///
+    if (HwStrap == SA_PEG_x16_x0_x0) {
+      DisableFun0 = TRUE;
+      DisableFun1 = TRUE;
+      DisableFun2 = TRUE;
+      break;
+    } else if (HwStrap == SA_PEG_x8_x8_x0) {
+      DisableFun2 = TRUE;
+      if (PegIndex == 0) {
+        DisableFun0 = TRUE;
+      } else {
+        DisableFun1 = TRUE;
+        break;
+      }
+    } else if (HwStrap == SA_PEG_x8_x4_x4) {
+      if (PegIndex == 0) {
+        DisableFun0 = TRUE;
+      } else if (PegIndex == 1) {
+        DisableFun1 = TRUE;
+      } else {
+        DisableFun2 = TRUE;
+        break;
+      }
+    }
+  } ///< End of the for Loop
+
+  if (!DisableFun1 || !DisableFun2) {
+    ///
+    /// PEG10 must be enabled if PEG11 and/or PEG12 are enabled
+    ///
+    if (DisableFun0) {
+      DisableLinkFunc0 = TRUE;
+    }
+
+    DisableFun0 = FALSE;
+  }
+
+  if (MmPci16 (0, SA_PEG_BUS_NUM, SA_PEG10_DEV_NUM, SA_PEG10_FUN_NUM, R_SA_PEG_VID_OFFSET) != 0xFFFF) {
+    FunctionExists = TRUE;
+  } else {
+    FunctionExists = FALSE;
+    DEBUG ((EFI_D_WARN, "PEG10 Disabled.\n"));
+  }
+  if ((DisableFun0 || DisableLinkFunc0) && FunctionExists) {
+    ///
+    /// Set D1.F0.R 224h [8] = 1
+    ///
+    MmPci32Or (0, SA_PEG_BUS_NUM, SA_PEG10_DEV_NUM, SA_PEG10_FUN_NUM, R_SA_PEG_LTSSMC_OFFSET, BIT8);
+
+    ///
+    /// DisableLink. Set D1.F0.R 0B0h [4] (LD (Link Disable) bit in Link Control Register
+    /// Set D1.F0.R D10h [0].
+    ///
+    MmPci8Or (0, SA_PEG_BUS_NUM, SA_PEG10_DEV_NUM, SA_PEG10_FUN_NUM, R_SA_PEG_LCTL_OFFSET, BIT4);
+
+    ///
+    /// Poll until D1.F0.R 464h [5:0] = 2
+    ///
+    LoopCount = 0;
+    while(   ((MmPci32 (0, SA_PEG_BUS_NUM, SA_PEG10_DEV_NUM, SA_PEG10_FUN_NUM, R_SA_PEG_REUT_PH1_PIS_OFFSET) & 0x3F) != 2)
+          && (LoopCount < SA_PEG_LINK_DISABLE_MAXWAIT)) {
+      StallPpi->Stall (PeiServices, StallPpi, STALL_ONE_MICRO_SECOND*100); //100usec
+      LoopCount++;
+    }
+
+    ///
+    /// Program AFEOVR.RXSQDETOVR
+    /// PCIe link disable for Switchable GFx
+    /// Additional Power savings: Set 0:1:0 0xC20 BIT4 = 0 & BIT5 = 1
+    ///
+    MmPci8AndThenOr (0, SA_PEG_BUS_NUM, SA_PEG10_DEV_NUM, SA_PEG10_FUN_NUM, R_SA_PEG_AFEOVR_OFFSET, ~(BIT5 | BIT4), BIT5);
+
+    if (((CpuFamilyId == EnumCpuHsw) && (CpuSteppingId >= EnumHswC0)) ||
+        ((CpuFamilyId == EnumCpuCrw) && (CpuSteppingId >= EnumCrwC0))) {
+        MaxBndlPwrdnCount = GetMaxBundles(PeiServices, 0, HwStrap);
+        PowerDownUnusedBundles(PeiServices, 0, HwStrap, MaxBndlPwrdnCount);
+    }
+
+    if (DisableFun0) {
+      ///
+      /// Set D1.F0.R D20h [30] to power off PEG lanes when no device is attached (prvtexdetq=1).
+      /// Clear D0.F0.R 054h (DEVEN) enable bit.
+      ///
+      MmPci32Or (0, SA_PEG_BUS_NUM, SA_PEG10_DEV_NUM, SA_PEG10_FUN_NUM, R_SA_PEG_PEGCOMLCGCTRL_OFFSET, BIT30);
+      MmPci8And (0, SA_MC_BUS, 0, 0, R_SA_DEVEN, ~B_SA_DEVEN_D1F0EN_MASK);
+      DEBUG ((EFI_D_WARN, "PEG10 Disabled.\n"));
+    }
+  }
+
+  if (MmPci16 (0, SA_PEG_BUS_NUM, SA_PEG11_DEV_NUM, SA_PEG11_FUN_NUM, R_SA_PEG_VID_OFFSET) != 0xFFFF) {
+    FunctionExists = TRUE;
+  } else {
+    FunctionExists = FALSE;
+    DEBUG ((EFI_D_WARN, "PEG11 Disabled.\n"));
+  }
+  if (DisableFun1 && FunctionExists) {
+    ///
+    /// Set D1.F1.R 224h [8] = 1
+    ///
+    MmPci32Or (0, SA_PEG_BUS_NUM, SA_PEG11_DEV_NUM, SA_PEG11_FUN_NUM, R_SA_PEG_LTSSMC_OFFSET, BIT8);
+
+    ///
+    /// DisableLink. Set D1.F1.R 0B0h [4] (LD (Link Disable) bit in Link Control Register.
+    /// Set D1.F1.R D10h [0].
+    /// Set D1.F1.R D20h [30] to power off PEG lanes when no device is attached (prvtexdetq=1).
+    /// Clear B0,D0,F0 054h (DEVEN) enable bit.
+    ///
+    MmPci8Or (0, SA_PEG_BUS_NUM, SA_PEG11_DEV_NUM, SA_PEG11_FUN_NUM, R_SA_PEG_LCTL_OFFSET, BIT4);
+
+    ///
+    /// Poll until D1.F0.R 464h [13:8] = 2
+    ///
+    LoopCount = 0;
+    while(   (((MmPci32 (0, SA_PEG_BUS_NUM, SA_PEG10_DEV_NUM, SA_PEG10_FUN_NUM, R_SA_PEG_REUT_PH1_PIS_OFFSET) >> 8) & 0x3F) != 2)
+          && (LoopCount < SA_PEG_LINK_DISABLE_MAXWAIT)) {
+      StallPpi->Stall (PeiServices, StallPpi, STALL_ONE_MICRO_SECOND*100); //100usec
+      LoopCount++;
+    }
+
+    ///
+    /// Program AFEOVR.RXSQDETOVR
+    /// PCIe link disable for Switchable GFx
+    /// Additional Power savings: Set 0:1:1 0xC20 BIT4 = 0 & BIT5 = 1
+    ///
+    MmPci8AndThenOr (0, SA_PEG_BUS_NUM, SA_PEG11_DEV_NUM, SA_PEG11_FUN_NUM, R_SA_PEG_AFEOVR_OFFSET, ~(BIT5 | BIT4), BIT5);
+
+    if (((CpuFamilyId == EnumCpuHsw) && (CpuSteppingId >= EnumHswC0)) ||
+        ((CpuFamilyId == EnumCpuCrw) && (CpuSteppingId >= EnumCrwC0))) {
+        MaxBndlPwrdnCount = GetMaxBundles(PeiServices, 1, HwStrap);
+        PowerDownUnusedBundles(PeiServices, 1, HwStrap, MaxBndlPwrdnCount);
+    }
+
+    MmPci32Or (0, SA_PEG_BUS_NUM, SA_PEG11_DEV_NUM, SA_PEG11_FUN_NUM, R_SA_PEG_PEGCOMLCGCTRL_OFFSET, BIT30);
+    MmPci8And (0, SA_MC_BUS, 0, 0, R_SA_DEVEN, ~B_SA_DEVEN_D1F1EN_MASK);
+    DEBUG ((EFI_D_WARN, "PEG11 Disabled.\n"));
+  }
+
+  if (MmPci16 (0, SA_PEG_BUS_NUM, SA_PEG12_DEV_NUM, SA_PEG12_FUN_NUM, R_SA_PEG_VID_OFFSET) != 0xFFFF) {
+    FunctionExists = TRUE;
+  } else {
+    FunctionExists = FALSE;
+    DEBUG ((EFI_D_WARN, "PEG12 Disabled.\n"));
+  }
+  if (DisableFun2 && FunctionExists) {
+    ///
+    /// Set D1.F2.R 224h [8] = 1
+    ///
+    MmPci32Or (0, SA_PEG_BUS_NUM, SA_PEG12_DEV_NUM, SA_PEG12_FUN_NUM, R_SA_PEG_LTSSMC_OFFSET, BIT8);
+
+    ///
+    /// DisableLink. Set D1.F2.R 0B0h [4] (LD (Link Disable) bit in Link Control Register.
+    /// Set D1.F2.R D10h [0].
+    /// Set D1.F2.R D20h [30] to power off PEG lanes when no device is attached (prvtexdetq=1).
+    /// Clear B0,D0,F0 054h (DEVEN) enable bit.
+    ///
+    MmPci8Or (0, SA_PEG_BUS_NUM, SA_PEG12_DEV_NUM, SA_PEG12_FUN_NUM, R_SA_PEG_LCTL_OFFSET, BIT4);
+
+    ///
+    /// Poll until D1.F0.R 464h [21:16] = 2
+    ///
+    LoopCount = 0;
+    while(   (((MmPci32 (0, SA_PEG_BUS_NUM, SA_PEG10_DEV_NUM, SA_PEG10_FUN_NUM, R_SA_PEG_REUT_PH1_PIS_OFFSET) >> 16) & 0x3F) != 2)
+          && (LoopCount < SA_PEG_LINK_DISABLE_MAXWAIT)) {
+      StallPpi->Stall (PeiServices, StallPpi, STALL_ONE_MICRO_SECOND*100); //100usec
+      LoopCount++;
+    }
+
+    ///
+    /// Program AFEOVR.RXSQDETOVR
+    /// PCIe link disable for Switchable GFx
+    /// Additional Power savings: Set 0:1:2 0xC20 BIT4 = 0 & BIT5 = 1
+    ///
+    MmPci8AndThenOr (0, SA_PEG_BUS_NUM, SA_PEG12_DEV_NUM, SA_PEG12_FUN_NUM, R_SA_PEG_AFEOVR_OFFSET, ~(BIT5 | BIT4), BIT5);
+
+    if (((CpuFamilyId == EnumCpuHsw) && (CpuSteppingId >= EnumHswC0)) ||
+        ((CpuFamilyId == EnumCpuCrw) && (CpuSteppingId >= EnumCrwC0))) {
+        MaxBndlPwrdnCount = GetMaxBundles(PeiServices, 2, HwStrap);
+        PowerDownUnusedBundles(PeiServices, 2, HwStrap, MaxBndlPwrdnCount);
+    }
+
+    MmPci32Or (0, SA_PEG_BUS_NUM, SA_PEG12_DEV_NUM, SA_PEG12_FUN_NUM, R_SA_PEG_PEGCOMLCGCTRL_OFFSET, BIT30);
+    MmPci8And (0, SA_MC_BUS, 0, 0, R_SA_DEVEN, ~B_SA_DEVEN_D1F2EN_MASK);
+    DEBUG ((EFI_D_WARN, "PEG12 Disabled.\n"));
+  }
+
+  for (PegComplete = 0; PegComplete < ((sizeof (PegPortTable)) / (sizeof (PEG_PORT))); PegComplete++) {
+    PegBus  = PegPortTable[PegComplete].Bus;
+    PegDev  = PegPortTable[PegComplete].Device;
+    PegFunc = PegPortTable[PegComplete].Function;
+    WaitForVc0Negotiation(PeiServices, StallPpi, PegBus, PegDev, PegFunc);
+    ReportPcieLinkStatus(PegBus, PegDev, PegFunc);
+  }
+
+  ///
+  /// Re-check Link again and see if PegLinkFailMask in SaDataHob needed update
+  ///
+  if (SaDataHob != NULL) {
+    LinkStatusGood = 0;
+    if ((BIT1 & MmPci16(0, 0, SA_PEG10_DEV_NUM, SA_PEG10_FUN_NUM, R_SA_PEG_VC0RSTS_OFFSET)) != BIT1) {
+      LinkStatusGood |= BIT0;
+    }
+    if ((BIT1 & MmPci16(0, 0, SA_PEG10_DEV_NUM, SA_PEG11_FUN_NUM, R_SA_PEG_VC0RSTS_OFFSET)) != BIT1) {
+      LinkStatusGood |= BIT1;
+    }
+    if ((BIT1 & MmPci16(0, 0, SA_PEG10_DEV_NUM, SA_PEG12_FUN_NUM, R_SA_PEG_VC0RSTS_OFFSET)) != BIT1) {
+      LinkStatusGood |= BIT2;
+    }
+    if (SaDataHob->PegData.PegLinkFailMask != (UINT8) (~LinkStatusGood)) {
+      DEBUG ((EFI_D_INFO, "Original PegLinkFailMask=%X, Final PegLinkFailMask=%X\n", SaDataHob->PegData.PegLinkFailMask, (UINT8) (~LinkStatusGood)));
+      SaDataHob->PegData.PegLinkFailMask = (UINT8) (~LinkStatusGood);
+    }
+  }
+
+  if ((SaPlatformPolicyPpi->Revision >= SA_PLATFORM_POLICY_PPI_REVISION_11) &&
+      (SaPlatformPolicyPpi->PcieConfig->PegComplianceTestingMode == 1)) {
+    for (PegComplete = 0; PegComplete < ((sizeof (PegPortTable)) / (sizeof (PEG_PORT))); PegComplete++) {
+      PegBus  = PegPortTable[PegComplete].Bus;
+      PegDev  = PegPortTable[PegComplete].Device;
+      PegFunc = PegPortTable[PegComplete].Function;
+      MmPci32Or (0, PegBus, PegDev, PegFunc, R_SA_PEG_CFG5_OFFSET, BIT0);
+    }
+  }
+
+  ///
+  /// Maximize the dedicated credits for the PEG controllers
+  ///
+  MaximizeSharedCredits();
+  RebalancePegPerformanceCredits (DisableFun0, DisableFun1, DisableFun2);
+  return;
+}
+
+VOID
+ConfigurePegGenX (
+  IN EFI_PEI_SERVICES       **PeiServices,
+  IN PEI_STALL_PPI          *StallPpi,
+  IN SA_PLATFORM_POLICY_PPI *SaPlatformPolicyPpi,
+  IN PEG_PORT               *PegPortTable,
+  IN UINTN                  TableIndex,
+  IN UINT8                  CpuSteppingId,
+  IN UINT8                  Gen3Capable
+  )
+/**
+  Configure PEG GenX mode
+
+  @param[in] PeiServices         - Pointer to the PEI services table
+  @param[in] StallPpi            - Pointer to PEI_STALL_PPI
+  @param[in] SaPlatformPolicyPpi - Pointer to SA_PLATFORM_POLICY_PPI
+  @param[in] PegPortTable        - Pointer to PEG_PORT array
+  @param[in] TableIndex          - Index in PEG_PORT array
+  @param[in] CpuSteppingId       - CPU stepping
+  @param[in] Gen3Capable         - Selected PEG_PORT is Gen3 capable
+
+  @retval None
+**/
+{
+  UINT8   PegPortGenx;
+  UINT8   PegBus;
+  UINT8   PegDev;
+  UINT8   PegFunc;
+  UINT8   PegIndex;
+  UINT8   MaxLinkWidth;
+  UINT16  LinkSpeed;
+
+  PegBus        = PegPortTable[TableIndex].Bus;
+  PegDev        = PegPortTable[TableIndex].Device;
+  PegFunc       = PegPortTable[TableIndex].Function;
+  PegIndex      = PegPortTable[TableIndex].Index;
+  MaxLinkWidth  = PegPortTable[TableIndex].MaxLinkWidth;
+
+  ///
+  /// Check if this port exists
+  ///
+  if (MmPci16 (0, PegBus, PegDev, PegFunc, PCI_VID) == 0xFFFF) {
+    return;
+  }
+
+  ///
+  /// PegPortGenx: 0 = Auto, 1 = Gen1, 2 = Gen2, 3 = Gen3
+  ///
+  PegPortGenx = SaPlatformPolicyPpi->PcieConfig->PegGenx[PegIndex];
+
+  if (PegPortGenx == PEG_AUTO) {
+    DEBUG ((EFI_D_ERROR, "Auto\n"));
+    LinkSpeed = (UINT16)(MmPci32(0, PegBus, PegDev, PegFunc, R_SA_PEG_LCAP_OFFSET) & 0x0F);
+  } else {
+    LinkSpeed = SaPlatformPolicyPpi->PcieConfig->PegGenx[PegIndex];
+    DEBUG ((EFI_D_ERROR, "Speed From Setup %x\n", LinkSpeed));
+  }
+  ///
+  /// If Gen3 is fused off, limit is Gen2
+  ///
+  if (Gen3Capable == FALSE) {
+    if (LinkSpeed > 2) {
+      LinkSpeed = 2;
+    }
+  }
+  ///
+  /// Set the requested speed in Max Link Speed in LCAP[3:0] and Target Link Speed in LCTL2[3:0].
+  /// Update LCAP.MLW in the same write as it's a Write-Once field
+  ///
+  DEBUG ((EFI_D_INFO, "PEG%x%x (%x:%x:%x) - Max Link Speed = Gen%d\n", PegDev, PegFunc, PegBus, PegDev, PegFunc, LinkSpeed));
+  MmPci32AndThenOr (0, PegBus, PegDev, PegFunc, R_SA_PEG_LCAP_OFFSET, 0xFFFFFC00, ((UINT32) MaxLinkWidth << 4) | LinkSpeed);
+  MmPci16AndThenOr (0, PegBus, PegDev, PegFunc, R_SA_PEG_LCTL2_OFFSET, ~(0x0F), LinkSpeed);
+
+  return;
+}
+
+VOID
+AdditionalPegProgramSteps (
+  IN SA_PLATFORM_POLICY_PPI  *SaPlatformPolicyPpi,
+  IN  UINT8                  PegBus,
+  IN  UINT8                  PegDev,
+  IN  UINT8                  PegFunc
+  )
+/**
+  Additional PEG Programming Steps at PEI
+
+  @param[in] SaPlatformPolicyPpi - pointer to SA_PLATFORM_POLICY_PPI
+  @param[in] PegBus      - Pci Bus Number
+  @param[in] PegDev      - Pci Device Number
+  @param[in] PegFunc     - Pci Func Number
+
+  @retval None
+**/
+{
+  UINT32              Data32And;
+  UINT32              Data32Or;
+
+
+  ///
+  /// Set L0SLAT[15:0] to 0x2020
+  ///
+  Data32And = (UINT32) ~(0xFFFF);
+  Data32Or  = 0x00002020;
+  MmPci32AndThenOr (0, PegBus, PegDev, PegFunc, R_SA_PEG_L0SLAT_OFFSET, Data32And, Data32Or);
+
+  ///
+  /// Disable PEG Debug Align Message - set 258[29] = '1b'
+  ///
+  Data32And = (UINT32) ~BIT29;
+  Data32Or  = BIT29;
+  MmPci32AndThenOr (0, PegBus, PegDev, PegFunc, R_SA_PEG_CFG4_OFFSET, Data32And, Data32Or);
+
+  ///
+  /// Retrain the link only if VC0 negotiation is complete at this point.
+  /// This is to support CLB card together with "Aways Enable PEG" option
+  ///
+  if ((MmPci16 (0, PegBus, PegDev, PegFunc, R_SA_PEG_VC0RSTS_OFFSET) & BIT1) == 0) {
+    ///
+    /// Set LCTL.RL (0xb0 bit 5) to initiate link retrain
+    ///
+    MmPci8Or (0, PegBus, PegDev, PegFunc, R_SA_PEG_LCTL_OFFSET, BIT5);
+    ///
+    /// Wait for Link training complete
+    ///
+    while (MmPci16 (0, PegBus, PegDev, PegFunc, R_SA_PEG_LSTS_OFFSET) & BIT11) {
+    };
+  }
+
+  return;
+}
+
+VOID
+MaximizeSharedCredits (
+  )
+/**
+  Maximize the dedicated credits for the PEG controllers
+**/
+{
+
+  UINT64 MchBar;
+  UINT32 Crdtctl0;
+  UINT32 Crdtctl1;
+  UINT32 Crdtctl2;
+  UINT32 Crdtctl3;
+  UINT8  Data8;
+  UINT8  Iotrk;
+  UINT8  Rrtrk;
+  BOOL   CommitUpdates;
+  UINT8  i;
+
+  Iotrk = 40;
+  Rrtrk = 71;
+  CommitUpdates = FALSE;
+
+  MchBar = McD0PciCfg64 (R_SA_MCHBAR) & ~BIT0;
+  Crdtctl0 = Mmio32 (MchBar, R_SA_MCHBAR_CRDTCTL0_OFFSET);
+  Crdtctl1 = Mmio32 (MchBar, R_SA_MCHBAR_CRDTCTL1_OFFSET);
+  Crdtctl2 = Mmio32 (MchBar, R_SA_MCHBAR_CRDTCTL2_OFFSET);
+  Crdtctl3 = Mmio32 (MchBar, R_SA_MCHBAR_CRDTCTL3_OFFSET);
+
+  Data8 = 0;
+  for (i = 0; i < 24; i += 3) {
+    Data8 += (Crdtctl0 >> i) & 0x7;
+    Data8 += (Crdtctl1 >> i) & 0x7;
+  }
+  if (Data8 > Iotrk) {
+    DEBUG ((EFI_D_ERROR, "ERROR: Attempted to reserve > %d IOTRK (Attempt = %d)! Skipping programming.\n", Iotrk, Data8));
+    CommitUpdates = FALSE;
+  } else {
+    Iotrk -= Data8;
+    DEBUG ((EFI_D_INFO, "IOTRK: Reserved = %d. Shared = %d. Total = %d.\n", Data8, Iotrk, Data8 + Iotrk));
+  }
+
+  Data8 = 0;
+  for (i = 0; i < 24; i += 3) {
+    Data8 += (Crdtctl2 >> i) & 0x7;
+  }
+  Data8 += (Crdtctl2 >> 24) & 0x3F;
+  if (Data8 > Rrtrk) {
+    DEBUG ((EFI_D_ERROR, "ERROR: Attempted to reserve > %d RRTRK (Attempt = %d)! Skipping programming.\n", Rrtrk, Data8));
+    CommitUpdates = FALSE;
+  } else {
+    Rrtrk -= Data8;
+    DEBUG ((EFI_D_INFO, "RRTRK: Reserved = %d. Shared = %d. Total = %d.\n", Data8, Rrtrk, Data8 + Rrtrk));
+  }
+
+  if (CommitUpdates) {
+    Crdtctl3 = ((Rrtrk & 0x7F) << 6) | (Iotrk & 0x3F);
+    Mmio32AndThenOr (MchBar, R_SA_MCHBAR_CRDTCTL3_OFFSET, (UINT32) ~(0x00001FFF), Crdtctl3);
+  }
+
+  return;
+}
+
+VOID
+RebalancePegPerformanceCredits (
+  IN  BOOLEAN   DisablePeg10,
+  IN  BOOLEAN   DisablePeg11,
+  IN  BOOLEAN   DisablePeg12
+  )
+/**
+  Rebalance Credits when PEG controllers so that no starvation occurs
+
+  @param[in] DisablePeg10     - Peg10 disable/enable status
+  @param[in] DisablePeg11     - Peg11 disable/enable status
+  @param[in] DisablePeg12     - Peg12 disable/enable status
+
+  @retval None
+**/
+{
+  UINT64 MchBar;
+  UINT32 Crdtctl4;
+  UINT32 Crdtctl6;
+  UINT32 Crdtctl8;
+  UINT16 PegLinkWidth10;
+  UINT16 PegLinkWidth11;
+  UINT16 PegLinkWidth12;
+
+  MchBar = McD0PciCfg64 (R_SA_MCHBAR) & ~BIT0;
+  Crdtctl4 = Mmio32 (MchBar, R_SA_MCHBAR_CRDTCTL4_OFFSET);
+  Crdtctl6 = Mmio32 (MchBar, R_SA_MCHBAR_CRDTCTL6_OFFSET);
+  Crdtctl8 = Mmio32 (MchBar, R_SA_MCHBAR_CRDTCTL8_OFFSET);
+
+  DEBUG ((EFI_D_INFO, "Crdtctl4 Crdtctl6 Crdtctl8 Before = %x %x %x\n", Crdtctl4, Crdtctl6, Crdtctl8));
+
+  PegLinkWidth10 = 0;
+  PegLinkWidth11 = 0;
+  PegLinkWidth12 = 0;
+
+  if (!DisablePeg10) {
+    PegLinkWidth10 = (MmPci16 (0, SA_PEG_BUS_NUM, SA_PEG10_DEV_NUM, SA_PEG10_FUN_NUM, R_SA_PEG_LSTS_OFFSET) & 0x3F0) >> 4;
+  }
+  if (!DisablePeg11) {
+    PegLinkWidth11 = (MmPci16 (0, SA_PEG_BUS_NUM, SA_PEG11_DEV_NUM, SA_PEG11_FUN_NUM, R_SA_PEG_LSTS_OFFSET) & 0x3F0) >> 4;
+  }
+  if (!DisablePeg12) {
+    PegLinkWidth12 = (MmPci16 (0, SA_PEG_BUS_NUM, SA_PEG12_DEV_NUM, SA_PEG12_FUN_NUM, R_SA_PEG_LSTS_OFFSET) & 0x3F0) >> 4;
+  }
+
+  DEBUG ((EFI_D_INFO, "PEG10: LinkDisabled = %x. Width = %x\n", DisablePeg10, PegLinkWidth10));
+  DEBUG ((EFI_D_INFO, "PEG11: LinkDisabled = %x. Width = %x\n", DisablePeg11, PegLinkWidth11));
+  DEBUG ((EFI_D_INFO, "PEG12: LinkDisabled = %x. Width = %x\n", DisablePeg12, PegLinkWidth12));
+
+  ///
+  /// PEG10 = x8 and PEG11 = x8
+  ///
+  if (!DisablePeg10 && !DisablePeg11 && (PegLinkWidth10 == 8) && (PegLinkWidth11 == 8)) {
+    Crdtctl4 &= ~0x3E0;
+    Crdtctl4 |= (Crdtctl4 & 0x7C00) >> 5;
+    Crdtctl6 &= ~0x3E0;
+    Crdtctl6 |= (Crdtctl6 & 0x7C00) >> 5;
+    Crdtctl8 &= ~0xFC0;
+    Crdtctl8 |= (Crdtctl8 & 0x3F000) >> 6;
+  }
+
+  ///
+  /// PEG12 = x4
+  ///
+  if (!DisablePeg12 && (PegLinkWidth12 == 4)) {
+    ///
+    /// PEG10 = x4
+    ///
+    if (!DisablePeg10 && (PegLinkWidth10 == 4)) {
+      Crdtctl4 &= ~0x3E0;
+      Crdtctl4 |= (Crdtctl4 & 0xF8000) >> 10;
+      Crdtctl6 &= ~0x3E0;
+      Crdtctl6 |= (Crdtctl6 & 0xF8000) >> 10;
+      Crdtctl8 &= ~0xFC0;
+      Crdtctl8 |= (Crdtctl8 & 0xFC0000) >> 12;
+    }
+    ///
+    /// PEG11 = x4
+    ///
+    if (!DisablePeg11 && (PegLinkWidth11 == 4)) {
+      Crdtctl4 &= ~0x7C00;
+      Crdtctl4 |= (Crdtctl4 & 0xF8000) >> 5;
+      Crdtctl6 &= ~0x7C00;
+      Crdtctl6 |= (Crdtctl6 & 0xF8000) >> 5;
+      Crdtctl8 &= ~0x3F000;
+      Crdtctl8 |= (Crdtctl8 & 0xFC0000) >> 6;
+    }
+  }
+
+  DEBUG ((EFI_D_INFO, "Crdtctl4 Crdtctl6 Crdtctl8 After = %x %x %x\n", Crdtctl4, Crdtctl6, Crdtctl8));
+
+  Mmio32AndThenOr (MchBar, R_SA_MCHBAR_CRDTCTL4_OFFSET, (UINT32) ~0x01FFFFFF, Crdtctl4);
+  Mmio32AndThenOr (MchBar, R_SA_MCHBAR_CRDTCTL6_OFFSET, (UINT32) ~0x01FFFFFF, Crdtctl6);
+  Mmio32AndThenOr (MchBar, R_SA_MCHBAR_CRDTCTL8_OFFSET, (UINT32) ~0x3FFFFFFF, Crdtctl8);
+
+  return;
+}
+
+VOID
+PegPreDetectionSteps (
+  IN  UINT8                   PegBus,
+  IN  UINT8                   PegDev,
+  IN  UINT8                   PegFunc,
+  IN SA_PLATFORM_POLICY_PPI   *SaPlatformPolicyPpi
+  )
+/**
+  Additional PEG Programming Steps before PEG detection at PEI
+
+  @param[in] PegBus              - Pci Bus Number
+  @param[in] PegDev              - Pci Device Number
+  @param[in] PegFunc             - Pci Func Number
+  @param[in] SaPlatformPolicyPpi - Pointer to SA_PLATFORM_POLICY_PPI
+**/
+{
+  UINT32        Data32;
+  UINT32        Data32And;
+  UINT32        Data32Or;
+  UINT32        i;
+  CPU_STEPPING  CpuSteppingId;
+  CPU_FAMILY    CpuFamilyId;
+
+  CpuSteppingId = GetCpuStepping();
+  CpuFamilyId   = GetCpuFamily();
+
+
+  Data32Or = (UINT32) (BIT4 | BIT3 | BIT2 | BIT1 | BIT0);
+  Data32And = (UINT32) ~(BIT8);
+  MmPci32AndThenOr (0, PegBus, PegDev, PegFunc, R_SA_PEG_LTSSMC_OFFSET, Data32And, Data32Or);
+
+  ///
+  /// Set PPCIE_CR_REUT_OVR_CTL_0_1_0_MMR.GRCLKGTDIS [28] to 1 (for PCIE Margin Test, Default is kept 0)
+  ///
+  if ((PegDev == 1) && (PegFunc == 0)) {
+    Data32And = (UINT32) ~BIT28;
+    Data32Or  = 0;
+    MmPci32AndThenOr (0, PegBus, PegDev, PegFunc, R_SA_PEG_REUT_OVR_CTL_OFFSET, Data32And, Data32Or);
+  }
+
+  if ((PegDev == 1) && (PegFunc == 0)) {
+    ///
+    /// DCBLNC = 0
+    ///
+    Data32And = (UINT32) ~(BIT3 | BIT2);
+    Data32Or  = 0;
+    for (i = 0; i < SA_PEG_MAX_BUNDLE; i++) {
+      MmPci32AndThenOr (0, PegBus, PegDev, PegFunc, R_SA_PEG_G3CTL0_OFFSET + i * BUNDLE_STEP, Data32And, Data32Or);
+    }
+  }
+
+  ///
+  /// DEBUP3[4] = 1
+  ///
+  if ((CpuFamilyId == EnumCpuHsw) || (CpuFamilyId == EnumCpuCrw)) {
+    Data32And = (UINT32) ~(BIT4);
+    Data32Or  = BIT4;
+    MmPci32AndThenOr (0, PegBus, PegDev, PegFunc, R_SA_PEG_DEBUP3_OFFSET, Data32And, Data32Or);
+  }
+
+  ///
+  /// FCLKGTTLLL[2] = 1
+  ///
+  if (((CpuFamilyId == EnumCpuHsw) && (CpuSteppingId < EnumHswC0)) ||
+      ((CpuFamilyId == EnumCpuCrw) && (CpuSteppingId < EnumCrwC0))) {
+    Data32And = (UINT32) ~(BIT2);
+    Data32Or  = BIT2;
+    MmPci32AndThenOr (0, PegBus, PegDev, PegFunc, R_SA_PEG_FCLKGTTLLL_OFFSET, Data32And, Data32Or);
+  }
+
+  ///
+  /// Program Read-Only Write-Once Registers
+  ///   R 308h [31:0]
+  ///   R 314h [31:0]
+  ///   R 32Ch [31:0]
+  ///   R 330h [31:0]
+  ///
+  Data32 = MmPci32 (0, PegBus, PegDev, PegFunc, R_SA_PEG_VC0PRCA_OFFSET);
+  MmPci32          (0, PegBus, PegDev, PegFunc, R_SA_PEG_VC0PRCA_OFFSET)  = Data32;
+  Data32 = MmPci32 (0, PegBus, PegDev, PegFunc, R_SA_PEG_VC0NPRCA_OFFSET);
+  MmPci32          (0, PegBus, PegDev, PegFunc, R_SA_PEG_VC0NPRCA_OFFSET) = Data32;
+  Data32 = MmPci32 (0, PegBus, PegDev, PegFunc, R_SA_PEG_VC1PRCA_OFFSET);
+  MmPci32          (0, PegBus, PegDev, PegFunc, R_SA_PEG_VC1PRCA_OFFSET)  = Data32;
+  Data32 = MmPci32 (0, PegBus, PegDev, PegFunc, R_SA_PEG_VC1NPRCA_OFFSET);
+  MmPci32          (0, PegBus, PegDev, PegFunc, R_SA_PEG_VC1NPRCA_OFFSET) = Data32;
+
+  return;
+}
+#endif // PEG_FLAG
+
+#if defined(DMI_FLAG) || defined(PEG_FLAG)
+UINT32
+SendVcuApiSequence (
+  IN    UINT32  MchBar,
+  IN    UINT32  Address,
+  IN    UINT16  OpCode,
+  IN    UINT32  WriteData
+  )
+/**
+  Send one sequence to VCU MailBox
+
+  @param[in] MchBar              - MCHBAR value
+  @param[in] Address             - Target address
+  @param[in] OpCode              - OpCode number
+  @param[in] WriteData           - Data value (only used if OpCode is a write)
+**/
+{
+  BOOL              IsWrite;
+  BOOL              IsCsr;
+  UINT32            DataOpCode;
+  UINT32            SequenceId;
+  UINT32            VcuData;
+  CPU_FAMILY        CpuFamilyId;
+  CPU_STEPPING      CpuSteppingId;
+
+  CpuFamilyId   = GetCpuFamily();
+  CpuSteppingId = GetCpuStepping();
+
+  if ((CpuFamilyId == EnumCpuHsw) && (CpuSteppingId == EnumHswA0)) {
+    if ((OpCode == V_SA_VCU_OPCODE_WRITE_CSR_REV1) || (OpCode == V_SA_VCU_OPCODE_WRITE_MMIO_REV1)) {
+      IsWrite = TRUE;
+    } else {
+      IsWrite = FALSE;
+    }
+
+    if ((OpCode == V_SA_VCU_OPCODE_READ_CSR_REV1) || (OpCode == V_SA_VCU_OPCODE_WRITE_CSR_REV1)) {
+      IsCsr = TRUE;
+    } else {
+      IsCsr = FALSE;
+    }
+  } else {
+    if ((OpCode == V_SA_VCU_OPCODE_WRITE_CSR_REV2) || (OpCode == V_SA_VCU_OPCODE_WRITE_MMIO_REV2)) {
+      IsWrite = TRUE;
+    } else {
+      IsWrite = FALSE;
+    }
+
+    if ((OpCode == V_SA_VCU_OPCODE_READ_CSR_REV2) || (OpCode == V_SA_VCU_OPCODE_WRITE_CSR_REV2)) {
+      IsCsr = TRUE;
+    } else {
+      IsCsr = FALSE;
+    }
+  }
+
+  if ((CpuFamilyId == EnumCpuHsw) && (CpuSteppingId == EnumHswA0)) {
+    if (IsWrite) {
+      DataOpCode = V_SA_VCU_OPCODE_WRITE_DATA_REV1;
+      if (IsCsr) {
+        SequenceId = V_SA_VCU_SEQID_WRITE_CSR_REV1;
+      } else {
+        SequenceId = V_SA_VCU_SEQID_WRITE_MMIO_REV1;
+      }
+    } else {
+      DataOpCode = V_SA_VCU_OPCODE_READ_DATA_REV1;
+      if (IsCsr) {
+        SequenceId = V_SA_VCU_SEQID_READ_CSR_REV1;
+      } else {
+        SequenceId = V_SA_VCU_SEQID_READ_MMIO_REV1;
+      }
+    }
+  } else {
+    if (IsWrite) {
+      DataOpCode = V_SA_VCU_OPCODE_WRITE_DATA_REV2;
+      if (IsCsr) {
+        SequenceId = V_SA_VCU_SEQID_WRITE_CSR_REV2;
+      } else {
+        SequenceId = V_SA_VCU_SEQID_WRITE_MMIO_REV2;
+      }
+    } else {
+      DataOpCode = V_SA_VCU_OPCODE_READ_DATA_REV2;
+      if (IsCsr) {
+        SequenceId = V_SA_VCU_SEQID_READ_CSR_REV2;
+      } else {
+        SequenceId = V_SA_VCU_SEQID_READ_MMIO_REV2;
+      }
+    }
+  }
+  if ((CpuFamilyId == EnumCpuHsw) && (CpuSteppingId == EnumHswA0)) {
+    SendVcuApiCmd (MchBar, V_SA_VCU_OPCODE_OPEN_SEQ_REV1, SequenceId);
+  } else {
+    SendVcuApiCmd (MchBar, V_SA_VCU_OPCODE_OPEN_SEQ_REV2, SequenceId);
+  }
+  SendVcuApiCmd (MchBar, OpCode, Address);
+  SendVcuApiCmd (MchBar, DataOpCode, WriteData);
+  VcuData = Mmio32 (MchBar, R_SA_MCHBAR_VCU_MAILBOX_DATA_OFFSET);
+  if ((CpuFamilyId == EnumCpuHsw) && (CpuSteppingId == EnumHswA0)) {
+    SendVcuApiCmd (MchBar, V_SA_VCU_OPCODE_CLOSE_SEQ_REV1, SequenceId);
+  } else {
+    SendVcuApiCmd (MchBar, V_SA_VCU_OPCODE_CLOSE_SEQ_REV2, SequenceId);
+  }
+
+  return VcuData;
+}
+
+VOID
+SendVcuApiCmd (
+  IN    UINT32  MchBar,
+  IN    UINT32  Interface,
+  IN    UINT32  Data
+  )
+/**
+  Send one command to VCU MailBox
+
+  @param[in] MchBar              - MCHBAR value
+  @param[in] Interface           - Interface number
+  @param[in] Data                - Data value
+**/
+{
+  UINT32  ResponseCounter;
+  UINT16  ResponseCode;
+  UINT32  BusyCounter;
+  UINT32  RunBusy;
+  BOOL    BusyStatus;
+
+  ResponseCode = V_SA_VCU_RESPONSE_SUCCESS;
+  for (ResponseCounter = 0; ResponseCounter < V_SA_VCU_RESPONSE_RETRY_LIMIT; ResponseCounter++) {
+    Mmio32 (MchBar, R_SA_MCHBAR_VCU_MAILBOX_DATA_OFFSET) = Data;
+    Mmio32 (MchBar, R_SA_MCHBAR_VCU_MAILBOX_INTERFACE_OFFSET) = (Interface | B_SA_MCHBAR_VCU_STATUS_RUN_BUSY);
+    BusyStatus = FALSE;
+    for (BusyCounter = 0; BusyCounter < V_SA_VCU_STATUS_BUSY_LIMIT; BusyCounter++) {
+      RunBusy     = Mmio32 (MchBar, R_SA_MCHBAR_VCU_MAILBOX_INTERFACE_OFFSET);
+      BusyStatus  = (RunBusy & B_SA_MCHBAR_VCU_STATUS_RUN_BUSY) ? TRUE : FALSE;
+      if (BusyStatus == FALSE) {
+        break;
+      }
+    }
+
+    if (BusyStatus) {
+      DEBUG ((EFI_D_INFO, "VCU Busy Timeout after %d tries: MCHBAR=%8.8X. Interface=%8.8X. Data=%4.4X.\n", BusyCounter, MchBar, Interface, Data));
+    }
+    ResponseCode = Mmio16 (MchBar, R_SA_MCHBAR_VCU_MAILBOX_INTERFACE_OFFSET);
+    if (ResponseCode == V_SA_VCU_RESPONSE_SUCCESS) {
+      break;
+    }
+  }
+
+  if (ResponseCode != V_SA_VCU_RESPONSE_SUCCESS) {
+    DEBUG ((EFI_D_ERROR, "ERROR: VCU Response Error after %d tries: MCHBAR=%8.8X. Interface=%4.4X. Data=%8.8X. ResponseCode=%4.4X\n", ResponseCounter, MchBar, Interface, Data, ResponseCode));
+  }
+
+  return;
+}
+#endif // DMI_FLAG || PEG_FLAG
+
+#ifdef PEG_FLAG
+
+UINT8
+GetMaxBundles (
+  IN EFI_PEI_SERVICES          **PeiServices,
+  IN UINT8                     PegFunc,
+  IN UINT8                     HwStrap
+  )
+/**
+  GetMaxBundles: Get the maximum bundle numbers for the corresponding PEG
+
+  @param[in] PeiServices          - Pointer to the PEI services table
+  @param[in] PegFunc              - Points to PEG0/PEG1/PEG2/...
+  @param[in] HwStrap              - Points to PEG configuration information [x16_x0_x0/x8_x8_x0/x8_x4_x4/...]
+
+  @retval                         - MaxBndlPwrdnCount [Maximun number of bundles for this HW configuration]
+**/
+{
+  UINT8  MaxBndlPwrdnCount;
+
+  MaxBndlPwrdnCount  = 0;
+
+  DEBUG ((EFI_D_INFO, "In GetMaxBundles procedure\n"));
+
+  if (PegFunc == 0) { // PEG10
+    if (HwStrap == SA_PEG_x16_x0_x0) {
+      MaxBndlPwrdnCount = 8;
+    } else {
+      MaxBndlPwrdnCount = 4;
+    }
+  } else if (PegFunc == 1) { // PEG11
+    if (HwStrap == SA_PEG_x8_x8_x0) {
+      MaxBndlPwrdnCount = 4;
+    } else if (HwStrap == SA_PEG_x8_x4_x4) {
+      MaxBndlPwrdnCount = 2;
+    }
+  } else if (PegFunc == 2) { // PEG12
+    if (HwStrap == SA_PEG_x8_x4_x4) {
+      MaxBndlPwrdnCount = 2;
+    }
+  }
+
+  DEBUG ((EFI_D_INFO, "MaxBndlPwrdnCount = %d\n", MaxBndlPwrdnCount));
+  return MaxBndlPwrdnCount;
+}
+
+VOID
+PowerDownUnusedBundles (
+  IN EFI_PEI_SERVICES          **PeiServices,
+  IN UINT8                     PegFunc,
+  IN UINT8                     HwStrap,
+  IN UINT8                     BndlPwrdnCount
+  )
+/**
+  PowerDownUnusedBundles: Program the PEG BundleSpare registers for power on sequence [PowerOff unused bundles for PEGs]
+
+  @param[in] PeiServices          - Pointer to the PEI services table
+  @param[in] PegFunc              - Points to PEG0/PEG1/PEG2/...
+  @param[in] HwStrap              - Points to PEG configuration information [x16_x0_x0/x8_x8_x0/x8_x4_x4/...]
+  @param[in] BndlPwrdnCount       - Points to how many bundles are unused and should be powered down
+**/
+{
+  BOOLEAN  PegLaneReversal;
+  UINT8    BndlPwrdnFirst;
+
+  UINT8    i;
+  UINT8    j;
+
+  PegLaneReversal = FALSE;
+  BndlPwrdnFirst  = 0;
+
+  DEBUG ((EFI_D_INFO, "In PowerDownUnusedBundles sequence\n"));
+
+  if (BndlPwrdnCount == 0) {
+    ///
+    /// If all lanes are used. Do nothing
+    ///
+    DEBUG ((EFI_D_INFO, "All lanes are used. Do nothing.\n"));
+    return;
+  }
+
+  if ((MmPci32 (0, SA_PEG_BUS_NUM, SA_PEG10_DEV_NUM, SA_PEG10_FUN_NUM, R_SA_PEG_PEGTST_OFFSET) & BIT20) != 0) {
+    DEBUG ((EFI_D_INFO, "PegLaneReversal is true\n"));
+    PegLaneReversal = TRUE;
+  }
+
+  if (PegFunc == 0) { // PEG10
+    if (HwStrap == SA_PEG_x16_x0_x0) {
+      if (!PegLaneReversal) {
+        BndlPwrdnFirst = 8 - BndlPwrdnCount;
+      } else {
+        BndlPwrdnFirst = 0;
+      }
+    } else {
+      if (!PegLaneReversal) {
+        BndlPwrdnFirst = 4 - BndlPwrdnCount;
+      } else {
+        BndlPwrdnFirst = 4;
+      }
+    }
+  } else if (PegFunc == 1) { // PEG11
+    if (HwStrap == SA_PEG_x8_x8_x0) {
+      if (!PegLaneReversal) {
+        BndlPwrdnFirst = 8 - BndlPwrdnCount;
+      } else {
+        BndlPwrdnFirst = 0;
+      }
+    } else if (HwStrap == SA_PEG_x8_x4_x4) {
+      if (!PegLaneReversal) {
+        BndlPwrdnFirst = 6 - BndlPwrdnCount;
+      } else {
+        BndlPwrdnFirst = 2;
+      }
+    }
+  } else if (PegFunc == 2) { // PEG12
+    if (HwStrap == SA_PEG_x8_x4_x4) {
+      if (!PegLaneReversal) {
+        BndlPwrdnFirst = 8 - BndlPwrdnCount;
+      } else {
+        BndlPwrdnFirst = 0;
+      }
+    }
+  }
+
+  ///
+  /// Power down unused lanes per request
+  ///
+  DEBUG ((EFI_D_INFO, "BNDL_PWRDN PEG%d%d[%d:%d]\n", 0, PegFunc, BndlPwrdnFirst, (BndlPwrdnFirst+BndlPwrdnCount-1)));
+  for (i = BndlPwrdnFirst, j=1; j <= BndlPwrdnCount; i++, j++) {
+    MmPci32Or (0, SA_PEG_BUS_NUM, SA_PEG10_DEV_NUM, SA_PEG10_FUN_NUM, R_SA_PEG_BND0SPARE_OFFSET + (i * BUNDLE_STEP), BIT31);
+  }
+
+  return;
+}
+#endif // PEG_FLAG
diff --git a/ReferenceCode/Chipset/SystemAgent/SaInit/Pei/PciExpressInit.h b/ReferenceCode/Chipset/SystemAgent/SaInit/Pei/PciExpressInit.h
new file mode 100644
index 0000000..2ca1bbe
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/SaInit/Pei/PciExpressInit.h
@@ -0,0 +1,452 @@
+/** @file
+  PciExpressInit header file
+
+@copyright
+  Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement
+
+**/
+#ifndef _PCIEXPRESS_INIT_H_
+#define _PCIEXPRESS_INIT_H_
+
+#include "EdkIIGluePeim.h"
+#include "SaAccess.h"
+#include "PchAccess.h"
+#include "EdkIIGluePcdPciExpressLib.h"
+#include "EdkIIGlueConfig.h"
+#include "Pci30.h"
+#include "CpuRegs.h"
+#include "CpuPlatformLib.h"
+
+///
+/// Driver Consumed PPI Prototypes
+///
+#include EFI_PPI_DEPENDENCY (Stall)
+#include EFI_PPI_DEPENDENCY (SaPlatformPolicy)
+
+#define PEG_AUTO    0
+#define PEG_GEN1    1
+#define PEG_GEN2    2
+#define PEG_GEN3    3
+
+#define DMI_GEN1    1
+#define DMI_GEN2    2
+
+#define LANE_STEP   0x10
+#define BUNDLE_STEP 0x20
+
+typedef struct {
+  UINT8   Bus;
+  UINT8   Device;
+  UINT8   Function;
+  UINT8   Index;
+  BOOLEAN PresenceDetect;
+  UINT8   MaxLinkWidth;
+  UINT8   EndpointMaxLinkSpeed;
+} PEG_PORT;
+
+///
+/// Data structure used in Sampler Calibration
+///
+#pragma pack(1)
+typedef struct _SAMPLE {
+  UINT8   Data;
+  UINT16  Count;
+} DATA_SAMPLE;
+#pragma pack()
+
+#define MAX_CODES 10
+
+///
+/// Data structure used in Preset Search
+///
+typedef struct _PRESET_DATA {
+  UINT8 Preset;
+  UINTN TimingMargin[SA_PEG_MAX_BUNDLE];
+  UINTN VoltageUpMargin[SA_PEG_MAX_BUNDLE];
+  UINTN VoltageDownMargin[SA_PEG_MAX_BUNDLE];
+} PRESET_DATA;
+
+#define MAX_PRESETS 3
+
+#define SA_PEG_SAMPLER_ITERATIONS  500
+///
+/// Common register access macros - use either DMIBAR or PEG10
+///
+#define SaMmio32AndThenOr(BaseAddr, Device, Register, AndData, OrData) \
+  if (BaseAddr != 0) { \
+    Mmio32AndThenOr (BaseAddr, Register, AndData, OrData); \
+  } else { \
+    MmPci32AndThenOr (0, 0, Device, 0, Register, AndData, OrData); \
+  }
+
+#ifdef PEG_FLAG
+VOID
+BubbleSort (
+  IN OUT DATA_SAMPLE Array[]
+  )
+/**
+  Bubble sort from DATA_SAMPLE
+
+  @param[in, out] - Array[]: array of DATA_SAMPLE
+
+  @retval None
+**/
+;
+
+UINT32
+GetMiddleValue (
+  IN OUT DATA_SAMPLE Array[]
+  )
+/**
+  Get Middle Value from DATA_SAMPLE
+
+  @param[in, out] - Array[]: array of DATA_SAMPLE
+
+  @retval UINT32 : Middle Value of DATA_SAMPLE
+**/
+;
+
+VOID
+SetLoadBus (
+  IN UINT32 DmiBar,
+  IN UINTN  Dev,
+  IN UINTN  Lane,
+  IN UINT32 LoadSel,
+  IN UINT32 LoadData,
+  IN UINT8  CpuSteppingId
+  )
+/**
+  Set Load Bus
+
+  @param[in] DmiBar        - DMIBAR address
+  @param[in] Dev           - Device Number
+  @param[in] Lane          - Number of Lane
+  @param[in] LoadSel       - Load selection value
+  @param[in] LoadData      - Load Data
+  @param[in] CpuSteppingId - CPUID.1.EAX[3:0], CPU stepping ID
+
+  @retval None
+**/
+;
+
+UINT32
+GetMonBus (
+  IN UINT32 DmiBar,
+  IN UINTN  Dev,
+  IN UINTN  Lane,
+  IN UINT32 LoadSel,
+  IN UINT8  CpuSteppingId
+  )
+/**
+  Get monitor bus from the lane selected
+
+  @param[in] DmiBar        - DMIBAR address
+  @param[in] Dev           - Device number
+  @param[in] Lane          - Number of Lane
+  @param[in] LoadSel       - Load selection value
+  @param[in] LoadData      - Load selecttion data
+  @param[in] CpuSteppingId - CPUID.1.EAX[3:0], CPU stepping ID
+
+  @retval UINT32 - Load bus address
+**/
+;
+
+VOID
+DumpSamplerValues (
+  IN UINT32 DmiBar,
+  IN UINT8  CpuSteppingId,
+  IN UINTN  Dev,
+  IN UINTN  LanesCount
+  )
+/**
+  Dump Sampler Values
+
+  @param[in] DmiBar        - DMIBAR address
+  @param[in] CpuSteppingId - CPUID.1.EAX[3:0], CPU stepping ID
+  @param[in] Dev           - Device number
+  @param[in] LanesCount    - Value of Lanes
+
+  @retval None
+**/
+;
+#endif // PEG_FLAG
+
+#if defined(DMI_FLAG) || defined(PEG_FLAG)
+VOID
+PegDmiRecipe (
+  IN SA_PLATFORM_POLICY_PPI *SaPlatformPolicyPpi,
+  IN UINT32                 MchBar,
+  IN UINT32                 DmiBar,
+  IN UINTN                  Dev,
+  IN UINT8                  SwingControl
+  )
+/**
+  Perform PEG/DMI PCIe Recipe steps
+
+  @param[in] SaPlatformPolicyPpi - Pointer to SA_PLATFORM_POLICY_PPI
+  @param[in] MchBar              - MCHBAR or zero if called for PEG
+  @param[in] DmiBar              - DMIBAR or zero if called for PEG
+  @param[in] Dev                 - PEG device number: 1 for PEG10, 0 if called for DMI.
+  @param[in] SwingControl        - 1 = Half, 2 = Full
+
+  @retval None
+**/
+;
+#endif // DMI_FLAG || PEG_FLAG
+
+#ifdef PEG_FLAG
+VOID
+ConfigurePegGenX (
+  IN EFI_PEI_SERVICES       **PeiServices,
+  IN PEI_STALL_PPI          *StallPpi,
+  IN SA_PLATFORM_POLICY_PPI *SaPlatformPolicyPpi,
+  IN PEG_PORT               *PegPortTable,
+  IN UINTN                  TableIndex,
+  IN UINT8                  CpuSteppingId,
+  IN UINT8                  Gen3Capable
+  )
+/**
+  Configure PEG GenX mode
+
+  @param[in] PeiServices         - Pointer to the PEI services table
+  @param[in] StallPpi            - Pointer to PEI_STALL_PPI
+  @param[in] SaPlatformPolicyPpi - Pointer to SA_PLATFORM_POLICY_PPI
+  @param[in] PegPortTable        - Pointer to PEG_PORT array
+  @param[in] TableIndex          - Index in PEG_PORT array
+  @param[in] CpuSteppingId       - CPU stepping
+  @param[in] Gen3Capable         - Selected PEG_PORT is Gen3 capable
+
+  @retval None
+**/
+;
+
+VOID
+AdditionalPegProgramSteps (
+  IN SA_PLATFORM_POLICY_PPI  *SaPlatformPolicyPpi,
+  IN  UINT8                  PegBus,
+  IN  UINT8                  PegDev,
+  IN  UINT8                  PegFunc
+  )
+/**
+  Additional PEG Programming Steps at PEI
+
+  @param[in] SaPlatformPolicyPpi - SaPlatformPolicyPpi to access the GtConfig related information
+  @param[in] PegBus      - Pci Bus Number
+  @param[in] PegDev      - Pci Device Number
+  @param[in] PegFunc     - Pci Func Number
+**/
+;
+
+VOID
+MaximizeSharedCredits (
+  )
+/**
+  Maximize the dedicated credits for the PEG controllers
+**/
+;
+
+VOID
+RebalancePegPerformanceCredits (
+  IN  BOOLEAN   DisablePeg10,
+  IN  BOOLEAN   DisablePeg11,
+  IN  BOOLEAN   DisablePeg12
+  )
+/**
+  Rebalance Credits when PEG controllers so that no stavation occurs
+
+  @param[in] DisablePeg10     - Peg10 disable/enable status
+  @param[in] DisablePeg11     - Peg11 disable/enable status
+  @param[in] DisablePeg12     - Peg12 disable/enable status
+
+  @retval None
+**/
+;
+
+VOID
+PegPreDetectionSteps (
+  IN  UINT8                   PegBus,
+  IN  UINT8                   PegDev,
+  IN  UINT8                   PegFunc,
+  IN SA_PLATFORM_POLICY_PPI   *SaPlatformPolicyPpi
+  )
+/**
+  Additional PEG Programming Steps before PEG detection at PEI
+
+  @param[in] PegBus              - Pci Bus Number
+  @param[in] PegDev              - Pci Device Number
+  @param[in] PegFunc             - Pci Func Number
+  @param[in] SaPlatformPolicyPpi - Pointer to SA_PLATFORM_POLICY_PPI
+**/
+;
+#endif // PEG_FLAG
+
+#if defined(DMI_FLAG) || defined(PEG_FLAG)
+UINT32
+SendVcuApiSequence (
+  IN    UINT32  MchBar,
+  IN    UINT32  Address,
+  IN    UINT16  OpCode,
+  IN    UINT32  WriteData
+  )
+/**
+  Send one sequence to VCU MailBox
+
+  @param[in] MchBar              - MCHBAR value
+  @param[in] Address             - Target address
+  @param[in] OpCode              - OpCode number
+  @param[in] WriteData           - Data value (only used if OpCode is a write)
+**/
+;
+
+VOID
+SendVcuApiCmd (
+  IN    UINT32  MchBar,
+  IN    UINT32  Interface,
+  IN    UINT32  Data
+  )
+/**
+  Send one command to VCU MailBox
+
+  @param[in] MchBar              - MCHBAR value
+  @param[in] Interface           - Interface number
+  @param[in] Data                - Data value
+**/
+;
+
+VOID
+ReportPcieLinkStatus (
+  IN UINT8             PegBus,
+  IN UINT8             PegDev,
+  IN UINT8             PegFunc
+)
+/**
+  This function reports a PEG controller's link status
+
+  @param[in] PegBus       - Peg Bus
+  @param[in] PegDev       - Peg Device
+  @param[in] PegFunc      - Peg Function
+
+  @retval None
+**/
+;
+
+VOID
+WaitForVc0Negotiation (
+  IN EFI_PEI_SERVICES  **PeiServices,
+  IN PEI_STALL_PPI     *StallPpi,
+  IN UINT8             PegBus,
+  IN UINT8             PegDev,
+  IN UINT8             PegFunc
+)
+/**
+  This function prints the time required for VC0 Negotiation Pending to be cleared. Quits after 100 msec.
+
+  @param[in] PeiServices  - Pointer to the PEI services table
+  @param[in] StallPpi     - Pointer to PEI_STALL_PPI
+  @param[in] PegBus       - Peg Bus
+  @param[in] PegDev       - Peg Device
+  @param[in] PegFunc      - Peg Function
+
+  @retval None
+**/
+;
+
+UINT32
+PcieFindCapId (
+  IN UINT8   Bus,
+  IN UINT8   Device,
+  IN UINT8   PegFunc,
+  IN UINT8   CapId
+  )
+/**
+  Find the Offset to a given Capabilities ID
+  CAPID list:
+    0x01 = PCI Power Management Interface
+    0x04 = Slot Identification
+    0x05 = MSI Capability
+    0x10 = PCI Express Capability
+
+  @param[in] Bus       -   Pci Bus Number
+  @param[in] Device    -   Pci Device Number
+  @param[in] PegFunc   -   Pci Function Number
+  @param[in] CapId     -   CAPID to search for
+
+  @retval 0       - CAPID not found
+  @retval Other   - CAPID found, Offset of desired CAPID
+**/
+;
+
+VOID
+ProgramPreset (
+  IN UINT8  Direction,
+  IN UINT8  PresetValue,
+  IN UINT8  PegFunc,
+  IN UINT8  Lane
+  )
+/**
+  Program PEG Gen3 preset value
+
+  @param[in] Direction     - 0 = Root Port, 1 = End Point
+  @param[in] PresetValue   - Preset value to program
+  @param[in] PegFunc       - Peg function number to be configured
+  @param[in] Lane          - Lane to be configured
+
+  @retval None
+**/
+;
+
+#endif // DMI_FLAG || PEG_FLAG
+
+#ifdef PEG_FLAG
+UINT8
+GetMaxBundles (
+  IN EFI_PEI_SERVICES          **PeiServices,
+  IN UINT8                     PegFunc,
+  IN UINT8                     HwStrap
+  )
+/**
+  GetMaxBundles: Get the maximum bundle numbers for the corresponding PEG
+
+  @param[in] PeiServices          - Pointer to the PEI services table
+  @param[in] PegFunc              - Points to PEG0/PEG1/PEG2/...
+  @param[in] HwStrap              - Points to PEG configuration information [x16_x0_x0/x8_x8_x0/x8_x4_x4/...]
+
+  @retval                         - MaxBndlPwrdnCount [Maximun number of bundles for this HW configuration]
+**/
+;
+
+VOID
+PowerDownUnusedBundles (
+  IN EFI_PEI_SERVICES          **PeiServices,
+  IN UINT8                     PegFunc,
+  IN UINT8                     HwStrap,
+  IN UINT8                     BndlPwrdnCount
+  )
+/**
+  PowerDownUnusedBundles: Program the PEG BundleSpare registers for power on sequence [PowerOff unused bundles for PEGs]
+
+  @param[in] PeiServices          - Pointer to the PEI services table
+  @param[in] PegFunc              - Points to PEG0/PEG1/PEG2/...
+  @param[in] HwStrap              - Points to PEG configuration information [x16_x0_x0/x8_x8_x0/x8_x4_x4/...]
+  @param[in] BndlPwrdnCount       - Points to how many bundles are unused and should be powered down
+
+  @retval                         - None
+**/
+;
+#endif // PEG_FLAG
+
+#endif
diff --git a/ReferenceCode/Chipset/SystemAgent/SaInit/Pei/PcieTraining.c b/ReferenceCode/Chipset/SystemAgent/SaInit/Pei/PcieTraining.c
new file mode 100644
index 0000000..26f16be
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/SaInit/Pei/PcieTraining.c
@@ -0,0 +1,628 @@
+/** @file
+  This driver trains the PEG interface.
+
+@copyright
+  Copyright (c) 2012 - 2013 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement
+**/
+
+#include "PcieTraining.h"
+
+#ifdef PEG_FLAG
+
+UINT16
+GetErrorTarget (
+  IN  SA_PLATFORM_POLICY_PPI *SaPlatformPolicyPpi
+  )
+{
+  UINT16  ErrorTarget;
+
+  if ((SaPlatformPolicyPpi->Revision >= SA_PLATFORM_POLICY_PPI_REVISION_3) &&
+      (SaPlatformPolicyPpi->PcieConfig->PegGen3PresetSearchErrorTarget >= 1)) {
+    ErrorTarget = SaPlatformPolicyPpi->PcieConfig->PegGen3PresetSearchErrorTarget;
+  } else {
+    ErrorTarget = 4;
+  }
+
+  return ErrorTarget;
+}
+
+VOID
+GetPortInfo (
+  OUT PORT_INFO *PortInfoList,
+  OUT UINT8     *PortInfoListLength,
+  OUT BOOLEAN   *SkipBundle0
+  )
+{
+  UINT32            HwStrap;
+  UINT8             PegBus;
+  UINT8             PegDev;
+  UINT8             PcieController;
+  UINT8             Index;
+  UINT8             Lane;
+  UINT8             LaneIndex;
+  UINT8             FurcationSetup[SA_PEG_MAX_FUN];
+  UINT8             PcieControllerList[SA_PEG_MAX_FUN];
+  UINT8             NumberToCheck;
+  UINT8             StartLane;
+  UINT8             Width;
+  UINT32            Lcap;
+  UINT32            CapOffset;
+  CPU_FAMILY        CpuFamilyId;
+  CPU_STEPPING      CpuSteppingId;
+
+  PegBus        = SA_MC_BUS;
+  PegDev        = 1;
+  HwStrap       = (McD1PciCfg32(R_SA_PEG_FUSESCMN_OFFSET) >> 16) & 0x3;
+  CpuFamilyId   = GetCpuFamily();
+  CpuSteppingId = GetCpuStepping();
+
+  switch(HwStrap) {
+    case SA_PEG_x8_x4_x4:
+      FurcationSetup[0] = 8;
+      FurcationSetup[1] = 4;
+      FurcationSetup[2] = 4;
+      NumberToCheck     = 3;
+      break;
+    case SA_PEG_x8_x8_x0:
+      FurcationSetup[0] = 8;
+      FurcationSetup[1] = 8;
+      NumberToCheck     = 2;
+      break;
+    default:
+    case SA_PEG_x16_x0_x0:
+      FurcationSetup[0] = 16;
+      NumberToCheck     = 1;
+      break;
+  }
+
+  ///
+  /// Figure out which PcieControllers are enabled
+  ///
+  (*PortInfoListLength) = 0;
+  for (PcieController = 0; PcieController < NumberToCheck; PcieController++) {
+    ///
+    /// Sanity check to make sure width > 0
+    ///
+    if (FurcationSetup[PcieController] == 0) {
+      continue;
+    }
+
+    ///
+    /// Check to make sure the Root Port Exists
+    ///
+    if (MmPci16 (0, PegBus, PegDev, PcieController, PCI_VID) == 0xFFFF) {
+      continue;
+    }
+
+    ///
+    /// Add the PcieController to the list of enabled controllers
+    ///
+    PcieControllerList[(*PortInfoListLength)] = PcieController;
+    (*PortInfoListLength)++;
+  }
+
+  ///
+  /// If needed, skip Bundle 0's preset search and use Bundle 1's preset instead.
+  ///
+  (*SkipBundle0) = FALSE;
+  if (((CpuFamilyId == EnumCpuHsw) && (CpuSteppingId < EnumHswC0)) ||
+      ((CpuFamilyId == EnumCpuCrw) && (CpuSteppingId < EnumCrwC0))) {
+    (*SkipBundle0) = TRUE;
+  }
+  if ((*SkipBundle0)) {
+    DEBUG ((EFI_D_INFO, "Skipping each controller's Lane 0-1 preset searches; using their Lane 2 preset instead.\n"));
+  }
+
+  StartLane = 0;
+  for (Index = 0; Index < (*PortInfoListLength); Index++) {
+    PcieController = PcieControllerList[Index];
+
+    ///
+    /// Get information for the current port
+    ///
+    (PortInfoList[Index]).EnableMargin                 = TRUE;
+    (PortInfoList[Index]).FoundUsablePreset            = FALSE;
+    (PortInfoList[Index]).PegPort.Bus                  = PegBus;
+    (PortInfoList[Index]).PegPort.Device               = PegDev;
+    (PortInfoList[Index]).PegPort.Function             = PcieController;
+    (PortInfoList[Index]).PegPort.Index                = PcieController;
+    (PortInfoList[Index]).PegPort.EndpointMaxLinkSpeed = 0;
+    ReportPcieLinkStatus (PegBus, PegDev, PcieController);
+    Width                                              = GetNegotiatedWidth(&((PortInfoList[Index]).PegPort));
+    (PortInfoList[Index]).LaneListLength               = Width;
+    for (Lane = 0, LaneIndex = 0; Lane < Width; Lane++) {
+      if ((*SkipBundle0)) {
+        if ((Lane == 0) || (Lane == 1)) {
+          (PortInfoList[Index]).LaneListLength--;
+          continue;
+        }
+      }
+      if (LaneIndex < SA_PEG_MAX_LANE) {
+        (PortInfoList[Index]).LaneList[LaneIndex] = (Lane + StartLane);
+      }
+      LaneIndex++;
+    }
+
+    ///
+    /// Check that both root port and endpoint support Gen3
+    ///
+    Lcap = MmPci32 (0, PegBus, PegDev, PcieController, R_SA_PEG_LCAP_OFFSET);
+    if ((Lcap & 0x0F) != 3) {
+      DEBUG ((EFI_D_INFO, " PEG%x%x (%x:%x:%x) - Root Port is not Gen3-capable. Max Link Speed = %d.\n",
+        PegDev, PcieController, PegBus, PegDev, PcieController, Lcap & 0x0F));
+      (PortInfoList[Index]).LinkIsGen3Capable = FALSE;
+    } else {
+
+      DEBUG ((EFI_D_INFO, " PEG%x%x (%x:%x:%x) - Root Port is Gen3-capable.\n",
+        PegDev, PcieController, PegBus, PegDev, PcieController));
+
+      ///
+      /// Set PEG PortBus = 1 to Read Endpoint.
+      ///
+      MmPci32AndThenOr (0, PegBus, PegDev, PcieController, PCI_PBUS, 0xFF0000FF, 0x00010100);
+
+      ///
+      /// A config write is required in order for the device to re-capture the Bus number,
+      /// according to PCI Express Base Specification, 2.2.6.2
+      /// Write to a read-only register VendorID to not cause any side effects.
+      ///
+      MmPci16 (0, 1, 0, 0, PCI_VID) = 0;
+
+      ///
+      /// Save end point vendor id and device id
+      ///
+      (PortInfoList[Index]).EndPointVendorIdDeviceId = MmPci32 (0, 1, 0, 0, 0);
+
+      ///
+      /// Negotiation Done?
+      ///
+      if ((MmPci16 (0, PegBus, PegDev, PcieController, R_SA_PEG_VC0RSTS_OFFSET) & BIT1) != 0) {
+        (PortInfoList[Index]).LinkIsGen3Capable = FALSE;
+        DEBUG ((EFI_D_INFO, " PEG%x%x (%x:%x:%x) - VC0 negotiation is pending! Skipping endpoint.\n",
+          PegDev, PcieController, PegBus, PegDev, PcieController, Lcap & 0x0F));
+        ReportPcieLinkStatus (PegBus, PegDev, PcieController);
+      } else {
+        ///
+        /// Get the pointer to the Port PCI Express Capability Structure.
+        ///
+        CapOffset = PcieFindCapId (1, 0, 0, EFI_PCI_CAPABILITY_ID_PCIEXP);
+        if (CapOffset == 0) {
+          (PortInfoList[Index]).LinkIsGen3Capable = FALSE;
+          DEBUG ((EFI_D_INFO, " PEG%x%x (%x:%x:%x) - Endpoint is not Gen3-capable. No PCIe Capability found.\n",
+            PegDev, PcieController, PegBus, PegDev, PcieController, Lcap & 0x0F));
+        } else {
+          Lcap = MmPci32 (0, 1, 0, 0, CapOffset + 0x0C);
+          (PortInfoList[Index]).PegPort.EndpointMaxLinkSpeed = Lcap & 0x0F;
+          if ((Lcap & 0x0F) < 3) {
+            (PortInfoList[Index]).LinkIsGen3Capable = FALSE;
+            DEBUG ((EFI_D_INFO, " PEG%x%x (%x:%x:%x) - Endpoint is not Gen3-capable. Max Link Speed = %d.\n",
+              PegDev, PcieController, PegBus, PegDev, PcieController, Lcap & 0x0F));
+          } else {
+            (PortInfoList[Index]).LinkIsGen3Capable = TRUE;
+            DEBUG ((EFI_D_INFO, " PEG%x%x (%x:%x:%x) - Endpoint is Gen3-capable\n",
+              PegDev, PcieController, PegBus, PegDev, PcieController, Lcap & 0x0F));
+          }
+        }
+      }
+      ///
+      /// Restore bus numbers on the PEG bridge.
+      ///
+      MmPci32And (0, PegBus, PegDev, PcieController, PCI_PBUS, 0xFF0000FF);
+    }
+
+    StartLane += FurcationSetup[PcieController];
+  } ///< End of for each port
+
+  return;
+}
+
+EFI_STATUS
+RunMarginTest (
+  IN  EFI_PEI_SERVICES        **PeiServices,
+  IN  SA_PLATFORM_POLICY_PPI  *SaPlatformPolicyPpi,
+  IN  SA_DATA_HOB             *SaDataHob,
+  IN  PEI_STALL_PPI           *StallPpi,
+  IN  UINT32                  MonitorPort,
+  IN  PORT_INFO               *PortInfoList,
+  IN  UINT8                   PortInfoListLength,
+  IN  MARGIN_TEST_TYPE        MarginTest,
+  OUT INT32                   *Margins
+  )
+{
+  EFI_STATUS Status;
+  UINT8      *LaneList;
+  UINT8      Lane;
+  UINT8      PortListIndex;
+  UINT8      OriginalSpeed;
+  UINT8      OriginalWidth;
+  UINT8      LaneListLength;
+  PEG_PORT   *PegPort;
+
+  Status = EFI_SUCCESS;
+
+  ///
+  /// Initialize Margins to -1.  Since -1 is an invalid value, we know that lane wasn't tested if its margin == -1
+  ///
+  for (Lane = 0; Lane < SA_PEG_MAX_LANE; Lane++) {
+    Margins[Lane] = -1;
+  }
+
+  for (PortListIndex = 0; PortListIndex < PortInfoListLength; PortListIndex++) {
+    ///
+    /// Test all lanes associated with this the current port
+    ///
+    LaneList       = &((PortInfoList[PortListIndex]).LaneList[0]);
+    LaneListLength =   (PortInfoList[PortListIndex]).LaneListLength;
+    PegPort        = &((PortInfoList[PortListIndex]).PegPort);
+    if ((PortInfoList[PortListIndex]).EnableMargin == FALSE ||
+        (PortInfoList[PortListIndex]).SkipMargin   == TRUE) {
+      continue;
+    }
+
+    if ((PortInfoList[PortListIndex]).LinkIsGen3Capable) {
+      OriginalSpeed = 3;
+    } else {
+      OriginalSpeed = GetLinkSpeed (PegPort);
+    }
+    OriginalWidth = GetNegotiatedWidth (PegPort);
+
+    switch (MarginTest) {
+      case LaneLevelRxJitter:
+        Status = LaneLevelJitterTest (
+                 PeiServices,
+                 SaPlatformPolicyPpi,
+                 SaDataHob,
+                 StallPpi,
+                 MonitorPort,
+                 LaneList,
+                 LaneListLength,
+                 PegPort,
+                 OriginalSpeed,
+                 OriginalWidth,
+                 FALSE,
+                 Margins
+                 );
+        break;
+      default:
+        DEBUG ((EFI_D_WARN, "Invalid Margin Test Requested.\n"));
+        break;
+    }
+  }
+
+  return Status;
+}
+
+EFI_STATUS
+LaneLevelJitterTest (
+  IN  EFI_PEI_SERVICES       **PeiServices,
+  IN  SA_PLATFORM_POLICY_PPI *SaPlatformPolicyPpi,
+  IN  SA_DATA_HOB            *SaDataHob,
+  IN  PEI_STALL_PPI          *StallPpi,
+  IN  UINT32                 MonitorPort,
+  IN  UINT8                  *LaneList,
+  IN  UINT8                  LaneListLength,
+  IN  PEG_PORT               *PegPort,
+  IN  UINT8                  OriginalLinkSpeed,
+  IN  UINT8                  OriginalLinkWidth,
+  IN  BOOLEAN                TxJitterTest,
+  OUT INT32                  *Margins
+  )
+{
+  EFI_STATUS Status;
+  UINT8     LaneListIndex;
+  INT8      Jitter;
+  UINT32    Errors;
+  UINT32    PreviousErrors;
+  UINT8     Lane;
+  UINT32    RecoveryCount;
+  BOOLEAN   AbortMargin;
+  UINT16    ErrorTarget;
+  UINT8     ConvergenceCounter;
+  INT32     LastMargin;
+  INT32     MarginDifference;
+  INT32     StartJitter;
+  INT8      MarginDirection;
+  UINT8     RepeatCount;
+
+  ErrorTarget = GetErrorTarget (SaPlatformPolicyPpi);
+
+  for (LaneListIndex = 0; LaneListIndex < LaneListLength; LaneListIndex++) {
+    Lane            = LaneList[LaneListIndex];
+    Errors          = 0;
+    AbortMargin     = FALSE;
+    Margins[Lane]   = 0;
+    MarginDirection = 1;
+
+    if (TxJitterTest) {
+      ConfigureTxJitterMux (Lane, SaPlatformPolicyPpi->PlatformData->MchBar);
+      EnableTxJitterInjection (Lane, TRUE);
+    }
+
+    ///
+    /// Determine value to start at
+    ///
+    if (LaneListIndex == 0) {
+      StartJitter = 0;
+    } else {
+      StartJitter = (Margins[LaneList[LaneListIndex - 1]] / 100) - JITTER_MARGIN_INITIAL_OFFSET;
+      if (StartJitter < 0) {
+        StartJitter = 0;
+      }
+    }
+
+    ConvergenceCounter = 0;
+    LastMargin         = -1;
+    RepeatCount        = 0;
+    while (ConvergenceCounter < MARGIN_CONVERGANCE_MIN_MATCHES && RepeatCount < MARGIN_CONVERGANCE_MAX_REPEATS) {
+      RepeatCount++;
+      ///
+      /// Determine whether to go up or down from starting point
+      ///
+      AbortMargin   = FALSE;
+      RecoveryCount = SaPcieGetErrorCount (MonitorPort, PegPort->Function);
+      Status        = SetJitterTolerance (&Lane, 1, (UINT8) StartJitter);
+      ASSERT_EFI_ERROR (Status);
+
+      Errors = SaPciePointTest (PeiServices, SaPlatformPolicyPpi, StallPpi, MonitorPort, PegPort, RecoveryCount);
+      if (Errors >= ErrorTarget) {
+        if (StartJitter == 0) {
+          Margins[Lane] = 0;
+          AbortMargin   = TRUE;
+        } else {
+          MarginDirection = -1;
+        }
+      } else {
+        MarginDirection = 1;
+      }
+      for (Jitter =  (INT8) (StartJitter + MarginDirection);
+           Jitter <  JITTER_LENGTH &&
+           Jitter >= 0             &&
+           (!AbortMargin);
+           Jitter = (INT8) (Jitter + MarginDirection)) {
+        ///
+        /// Check for a link downgrade
+        ///
+        AbortMargin = LinkIsDowngraded (PegPort, OriginalLinkSpeed, OriginalLinkWidth);
+        if (AbortMargin) {
+          if (MarginDirection < 0) {
+            LastMargin         = -1;
+            ConvergenceCounter = 0;
+            StartJitter        = 0;
+            MarginDirection    = 1;
+          } else {
+            if (Jitter == 0) {
+              Margins[Lane] = 0;
+            } else {
+              Margins[Lane] = (Jitter - 1) * 100;
+            }
+          }
+          break;
+        }
+
+        ///
+        /// Get initial recovery count
+        ///
+        RecoveryCount = SaPcieGetErrorCount (MonitorPort, PegPort->Function);
+        Status        = SetJitterTolerance (&Lane, 1, Jitter);
+        ASSERT_EFI_ERROR (Status);
+
+        PreviousErrors = Errors;
+        Errors         = SaPciePointTest (PeiServices, SaPlatformPolicyPpi, StallPpi, MonitorPort, PegPort, RecoveryCount);
+        if (MarginDirection < 0) {
+          if (Errors < ErrorTarget) { ///< Downward direction has started passing
+            Margins[Lane] = InterpolateMargin (ErrorTarget, PreviousErrors, Errors, (INT32) Jitter);
+            break;
+          }
+        } else {
+          if (Errors >= ErrorTarget) { ///< Upward direction has started failing
+            Margins[Lane] = InterpolateMargin (ErrorTarget, Errors, PreviousErrors, (INT32) Jitter);
+            break;
+          }
+        }
+      } ///< End of for loop
+
+      ///
+      /// Check if we never reached the error target
+      ///
+      if (MarginDirection < 0) {
+        if ((Errors >= ErrorTarget) && (!AbortMargin)) {
+          Margins[Lane] = 0;
+        }
+      } else {
+        if ((Errors < ErrorTarget) && (!AbortMargin)) {
+          Margins[Lane] = JITTER_LENGTH * 100;
+        }
+      }
+
+      ///
+      /// Compute the next margin point to start at
+      ///
+      StartJitter = (Margins[Lane] / 100) - JITTER_MARGIN_INITIAL_OFFSET;
+      if (StartJitter < 0) {
+        StartJitter = 0;
+      }
+
+      ///
+      /// Check for convergance
+      ///
+      if (LastMargin == -1) {
+        LastMargin = Margins[Lane];
+      } else {
+        MarginDifference = CalculateMarginDifference (LastMargin, Margins[Lane]);
+        if (MarginDifference <= MARGIN_CONVERGANCE_ALLOWED_DELTA) {
+          ConvergenceCounter++;
+        } else {
+          ConvergenceCounter = 0;
+        }
+        LastMargin = Margins[Lane];
+      }
+
+      if (LinkIsDowngraded (PegPort, OriginalLinkSpeed, OriginalLinkWidth)) {
+        Status = SetJitterTolerance (&Lane, 1, 0);
+        ASSERT_EFI_ERROR (Status);
+      }
+
+      ///
+      /// If the link degraded in any way, bring it back to functional state
+      ///
+      Status = EnsureLinkIsHealthy (PeiServices, SaPlatformPolicyPpi, SaDataHob, StallPpi, PegPort, OriginalLinkSpeed, OriginalLinkWidth);
+      if (EFI_ERROR (Status)) {
+        return Status;
+      }
+    } ///< End of repeat while loop
+
+    ///
+    /// Remove Jitter in preparation for testing the next lane
+    ///
+    Status = SetJitterTolerance (&Lane, 1, 0);
+    ASSERT_EFI_ERROR (Status);
+    if (TxJitterTest) {
+      EnableTxJitterInjection (Lane, FALSE);
+    }
+  } ///< End of for each lane loop
+
+  return EFI_SUCCESS;
+}
+
+UINT32
+SaPciePointTest (
+  IN EFI_PEI_SERVICES       **PeiServices,
+  IN SA_PLATFORM_POLICY_PPI *SaPlatformPolicyPpi,
+  IN PEI_STALL_PPI          *StallPpi,
+  IN UINT32                 MonitorPort,
+  IN PEG_PORT               *PegPort,
+  IN UINT32                 InitialRecoveryCount
+  )
+{
+  UINT32  Data32;
+
+  StallPpi->Stall (PeiServices, StallPpi, SaPlatformPolicyPpi->PcieConfig->PegGen3PresetSearchDwellTime);
+  Data32 = SaPcieGetErrorCount (MonitorPort, PegPort->Function) - InitialRecoveryCount;
+
+  return Data32;
+}
+
+INT32
+CalculateMarginDifference (
+  IN INT32                   Margin1,
+  IN INT32                   Margin2
+  )
+{
+  if (Margin1 < Margin2) {
+    return Margin2 - Margin1;
+  } else {
+    return Margin1 - Margin2;
+  }
+}
+
+INT32
+InterpolateMargin (
+  IN UINT32 ErrorTarget,
+  IN UINT32 CurrentErrorCount,
+  IN UINT32 PreviousErrorCount,
+  IN INT32  FailingPoint
+  )
+{
+  UINT32 LnErrorTarget;
+  UINT32 LnCurrentErrorCount;
+  UINT32 LnPreviousErrorCount;
+  INT32  Margin;
+
+  if (ErrorTarget > 40000) {
+    ErrorTarget = 40000;
+  }
+  if (CurrentErrorCount > 40000) {
+    CurrentErrorCount = 40000;
+  }
+  if (PreviousErrorCount > 40000) {
+    PreviousErrorCount = 40000;
+  }
+
+  LnErrorTarget        = NaturalLog (ErrorTarget * 100);
+  LnCurrentErrorCount  = NaturalLog (CurrentErrorCount * 100);
+  LnPreviousErrorCount = NaturalLog (PreviousErrorCount * 100);
+
+  if (FailingPoint >= 0) {
+    if ((LnCurrentErrorCount - LnPreviousErrorCount) == 0) {
+      Margin = (FailingPoint - 1) * 100;
+    } else {
+      Margin = ((LnErrorTarget - LnPreviousErrorCount) * 100) /
+               (LnCurrentErrorCount - LnPreviousErrorCount)   +
+               ((FailingPoint - 1) * 100);
+    }
+    if (Margin < 0) {
+      Margin = 0;
+    }
+  } else {
+    if ((LnCurrentErrorCount - LnPreviousErrorCount) == 0) {
+      Margin = (FailingPoint + 1) * 100;
+    } else {
+      Margin = ((FailingPoint + 1) * 100)                     -
+               ((LnErrorTarget - LnPreviousErrorCount) * 100) /
+               (LnCurrentErrorCount - LnPreviousErrorCount);
+    }
+    if (Margin > 0) {
+      Margin = 0;
+    }
+  }
+
+  return Margin;
+}
+
+
+UINT32
+NaturalLog (
+  IN UINT32 Input
+  )
+  /*++
+
+  Routine Description:
+
+    This function calculates the Natural Log of the Input parameter using integers
+
+  Arguments:
+
+    Input           - 100 times a number to get the Natural log from.
+                    - Max Input Number is 40,000 (without 100x)
+
+  Returns:
+
+    Output          - 100 times the actual result. Accurate within +/- 2
+
+  --*/
+{
+  UINT32  Output;
+
+  ///
+  ///Special case - treat 0 recoveries as 1 recovery for interpolation purposes
+  ///
+  if (Input == 0) {
+    return 0;
+  }
+
+  Output = 0;
+  while (Input > 271) {
+    Input   = (Input * 1000) / 2718;
+    Output += 100;
+  }
+
+  Output += ((-16 * Input * Input + 11578 * Input - 978860) / 10000);
+
+  return Output;
+}
+
+#endif // PEG_FLAG
diff --git a/ReferenceCode/Chipset/SystemAgent/SaInit/Pei/PcieTraining.h b/ReferenceCode/Chipset/SystemAgent/SaInit/Pei/PcieTraining.h
new file mode 100644
index 0000000..5c7ee57
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/SaInit/Pei/PcieTraining.h
@@ -0,0 +1,425 @@
+/** @file
+  Header file for PcieTraining Initialization Driver.
+
+@copyright
+  Copyright (c) 2012 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement
+**/
+
+#ifndef _PCIETRAINING_H_
+#define _PCIETRAINING_H_
+
+#include "EdkIIGluePeim.h"
+#include "SaAccess.h"
+#include "PciExpressInit.h"
+
+#include EFI_PPI_DEPENDENCY (SaPlatformPolicy)
+#include EFI_GUID_DEFINITION (SaDataHob)
+
+///
+/// Data structures
+///
+
+typedef struct {
+  PEG_PORT PegPort;
+  UINT32   EndPointVendorIdDeviceId;
+  BOOLEAN  LinkIsGen3Capable;
+  UINT8    LaneList[SA_PEG_MAX_LANE];
+  UINT8    LaneListLength;
+  BOOLEAN  EnableMargin;
+  BOOLEAN  SkipMargin;
+  BOOLEAN  FoundUsablePreset;
+} PORT_INFO;
+
+typedef struct {
+  INT8  Depth;
+  UINT8 Step;
+  UINT8 ReportedMargin;
+  UINT8 DoubleMargin;
+} JITTER_SETTING;
+
+typedef struct {
+  UINT8  Lane;
+  UINT32 InitialDs0Dac;
+  UINT32 InitialDs0Value;
+  INT32  Ds0MarginOffset;
+  UINT32 InitialDs1Dac;
+  UINT32 InitialDs1Value;
+  INT32  Ds1MarginOffset;
+  INT32  MaxUpMargin;
+  INT32  MaxDownMargin;
+} VOC_STATE;
+
+typedef enum {
+  LaneLevelRxJitter,
+  VocUp,
+  VocDown
+} MARGIN_TEST_TYPE;
+
+#define JITTER_LENGTH                         25
+#define JITTER_MARGIN_INITIAL_OFFSET          1
+#define MARGIN_CONVERGANCE_ALLOWED_DELTA      100
+#define MARGIN_CONVERGANCE_MIN_MATCHES        2
+#define MARGIN_CONVERGANCE_MAX_REPEATS        30
+
+#define SA_PEI_MONITOR_OFFSET                 0xFED85000
+
+///
+/// Register Definitions
+///
+#define B_SA_PEG_LTSSMC_WIDTH_MASK            0xFFFFFFE0
+
+#define R_SA_PEG_REUT_PH_CTR_OFFSET           0x444
+#define B_SA_PEG_REUT_PH_CTR_PHYRESET_MASK    0x1
+#define B_SA_PEG_REUT_PH_CTR_RESETMOD_MASK    0x2
+#define B_SA_PEG_REUT_PH_CTR_AUTOCOMP_MASK    0x2000
+
+#define R_SA_PEG_REUT_PH1_PIS_OFFSET          0x464
+#define B_SA_PEG_REUT_PH1_PIS_ST_MASK         0x3F
+#define B_SA_PEG_REUT_PH1_PIS_ST_STEP         0x8
+
+#define B_SA_PEG_BCTRL_SRESET_MASK            BIT6
+
+#define V_SA_VCU_OPCODE_SET_TXJITTER_MUX      0x3002
+#define V_SA_VCU_SEQID_SET_TXJITTER_MUX       0x00030003
+
+#define R_SA_VCU_REUT_PH_CTR_ADDRESS_REV1     0x04448808
+#define R_SA_VCU_REUT_PH_CTR_ADDRESS_REV2     0x04448080
+
+#define R_SA_VCU_REUT_PH1_PIS_ADDRESS_REV1    0x04648808
+#define R_SA_VCU_REUT_PH1_PIS_ADDRESS_REV2    0x04648080
+
+///
+/// Function Prototypes
+///
+
+
+
+UINT16
+GetErrorTarget (
+  IN  SA_PLATFORM_POLICY_PPI *SaPlatformPolicyPpi
+  );
+
+VOID GetPortInfo (
+  OUT PORT_INFO *PortInfoList,
+  OUT UINT8     *PortInfoListLength,
+  OUT BOOLEAN   *SkipBundle0
+  );
+
+EFI_STATUS
+RunMarginTest (
+  IN  EFI_PEI_SERVICES        **PeiServices,
+  IN  SA_PLATFORM_POLICY_PPI  *SaPlatformPolicyPpi,
+  IN  SA_DATA_HOB             *SaDataHob,
+  IN  PEI_STALL_PPI           *StallPpi,
+  IN  UINT32                  MonitorPort,
+  IN  PORT_INFO               *PortInfoList,
+  IN  UINT8                   PortInfoListLength,
+  IN  MARGIN_TEST_TYPE        MarginTest,
+  OUT INT32                   *Margins
+  );
+
+EFI_STATUS
+LaneLevelJitterTest (
+  IN  EFI_PEI_SERVICES       **PeiServices,
+  IN  SA_PLATFORM_POLICY_PPI *SaPlatformPolicyPpi,
+  IN  SA_DATA_HOB            *SaDataHob,
+  IN  PEI_STALL_PPI          *StallPpi,
+  IN  UINT32                 MonitorPort,
+  IN  UINT8                  *LaneList,
+  IN  UINT8                  LaneListLength,
+  IN  PEG_PORT               *PegPort,
+  IN  UINT8                  OriginalLinkSpeed,
+  IN  UINT8                  OriginalLinkWidth,
+  IN  BOOLEAN                TxJitterTest,
+  OUT INT32                  *Margins
+  );
+
+UINT32
+SaPciePointTest (
+  IN EFI_PEI_SERVICES       **PeiServices,
+  IN SA_PLATFORM_POLICY_PPI *SaPlatformPolicyPpi,
+  IN PEI_STALL_PPI          *StallPpi,
+  IN UINT32                 MonitorPort,
+  IN PEG_PORT               *PegPort,
+  IN UINT32                 InitialRecoveryCount
+  );
+
+INT32
+CalculateMarginDifference (
+  IN INT32                   Margin1,
+  IN INT32                   Margin2
+  );
+
+INT32
+InterpolateMargin (
+  IN UINT32 ErrorTarget,
+  IN UINT32 CurrentErrorCount,
+  IN UINT32 PreviousErrorCount,
+  IN INT32  FailingPoint
+  );
+
+
+UINT32
+NaturalLog (
+  IN UINT32 Input
+  );
+
+
+VOID
+PegGen3PresetSearch (
+  IN EFI_PEI_SERVICES       **PeiServices,
+  IN SA_PLATFORM_POLICY_PPI *SaPlatformPolicyPpi,
+  IN PEI_STALL_PPI          *StallPpi,
+  SA_DATA_HOB               *SaDataHob
+  );
+
+BOOLEAN
+SaPolicyEnablesGen3 (
+  IN SA_PLATFORM_POLICY_PPI *SaPlatformPolicyPpi
+  );
+
+
+EFI_STATUS
+EnsureLinkIsHealthy (
+  IN EFI_PEI_SERVICES       **PeiServices,
+  IN SA_PLATFORM_POLICY_PPI *SaPlatformPolicyPpi,
+  IN SA_DATA_HOB            *SaDataHob,
+  IN PEI_STALL_PPI          *StallPpi,
+  IN PEG_PORT               *PegPort,
+  IN UINT8                  OriginalLinkSpeed,
+  IN UINT8                  OriginalLinkWidth
+  );
+
+EFI_STATUS
+WaitForL0 (
+  IN EFI_PEI_SERVICES **PeiServices,
+  IN PEI_STALL_PPI    *StallPpi,
+  IN PEG_PORT         *PegPort,
+  IN BOOLEAN          UseVcu
+  );
+
+EFI_STATUS
+TogglePegSlotReset (
+  IN EFI_PEI_SERVICES       **PeiServices,
+  IN PEI_STALL_PPI          *StallPpi,
+  IN SA_PLATFORM_POLICY_PPI *SaPlatformPolicyPpi
+  );
+
+EFI_STATUS
+AssertPegSlotReset (
+  IN SA_PLATFORM_POLICY_PPI *SaPlatformPolicyPpi
+  );
+
+EFI_STATUS
+DeassertPegSlotReset (
+  IN SA_PLATFORM_POLICY_PPI *SaPlatformPolicyPpi
+  );
+
+EFI_STATUS
+RecoverLinkFailure (
+  IN EFI_PEI_SERVICES       **PeiServices,
+  IN SA_PLATFORM_POLICY_PPI *SaPlatformPolicyPpi,
+  IN SA_DATA_HOB            *SaDataHob,
+  IN PEI_STALL_PPI          *StallPpi,
+  IN PEG_PORT               *PegPort,
+  IN UINT8                  OriginalLinkSpeed,
+  IN UINT8                  OriginalLinkWidth
+  );
+
+BOOLEAN
+LinkIsDowngraded (
+  IN PEG_PORT *PegPort,
+  IN UINT8    OriginalLinkSpeed,
+  IN UINT8    OriginalLinkWidth
+  );
+
+EFI_STATUS
+SecondaryBusReset (
+  IN EFI_PEI_SERVICES **PeiServices,
+  IN PEI_STALL_PPI    *StallPpi,
+  IN PEG_PORT         *PegPort
+  );
+
+EFI_STATUS
+ResetPhyLayer (
+  IN EFI_PEI_SERVICES **PeiServices,
+  IN PEI_STALL_PPI    *StallPpi,
+  IN PEG_PORT         *PegPort
+  );
+
+EFI_STATUS
+RetrainLink (
+  IN EFI_PEI_SERVICES **PeiServices,
+  IN PEI_STALL_PPI    *StallPpi,
+  IN PEG_PORT         *PegPort
+  );
+
+UINT8
+GetNegotiatedWidth (
+  IN PEG_PORT *PegPort
+  );
+
+EFI_STATUS
+RecoverLinkWidth (
+  IN EFI_PEI_SERVICES **PeiServices,
+  IN PEI_STALL_PPI    *StallPpi,
+  IN PEG_PORT         *PegPort,
+  IN UINT8            OriginalLinkWidth
+  );
+
+UINT8
+GetLinkSpeed (
+  IN PEG_PORT *PegPort
+  );
+
+EFI_STATUS
+RecoverLinkSpeed (
+  IN EFI_PEI_SERVICES **PeiServices,
+  IN PEI_STALL_PPI    *StallPpi,
+  IN PEG_PORT         *PegPort,
+  IN UINT8            OriginalLinkSpeed
+  );
+
+VOID
+PcieTrainingWarmReset (
+  IN EFI_PEI_SERVICES **PeiServices
+  );
+
+
+EFI_STATUS
+SetJitterTolerance (
+  IN UINT8   *LaneList,
+  IN UINT8   LaneListLength,
+  IN UINT8   ReportedMargin
+  );
+
+EFI_STATUS
+SetRawJitterTolerance (
+  IN UINT8   *LaneList,
+  IN UINT8   LaneListLength,
+  IN UINT8   Step,
+  IN UINT8   Depth,
+  IN UINT8   DoubleMargin,
+  IN BOOLEAN EnableJitter
+  );
+
+VOID
+EnableTxJitterInjection (
+  IN UINT8    Lane,
+  IN BOOLEAN  EnableTxJitter
+  );
+
+VOID
+ConfigureTxJitterMux (
+  IN UINT8    Lane,
+  IN UINT32   MchBar
+  );
+
+EFI_STATUS
+GetBundleList (
+  IN  UINT8 *LaneList,
+  IN  UINT8 LaneListLength,
+  OUT UINT8 *BundleList,
+  OUT UINT8 *BundleListLength
+  );
+
+
+UINT32
+OpenMonitor (
+  IN EFI_PEI_SERVICES       **PeiServices,
+  IN SA_PLATFORM_POLICY_PPI *SaPlatformPolicyPpi,
+  IN PEI_STALL_PPI          *StallPpi
+  );
+
+VOID
+CloseMonitor (
+  IN SA_PLATFORM_POLICY_PPI *SaPlatformPolicyPpi,
+  IN UINT32                  MonitorPort
+  );
+
+UINT32
+SaPcieGetErrorCount (
+  IN UINT32 MonitorPort,
+  IN UINT8  PcieController
+  );
+
+VOID
+SaPcieClearErrorCount (
+  IN UINT32           MonitorPort,
+  IN EFI_PEI_SERVICES **PeiServices,
+  IN PEI_STALL_PPI    *StallPpi
+  );
+
+VOID
+InitMonitor (
+  IN UINT32 MchBar,
+  IN UINT32 GdxcBar
+  );
+
+VOID
+TearDownMonitor (
+  IN UINT32 MchBar,
+  IN UINT32 GdxcBar
+  );
+
+UINT32
+EnableMonitor (
+  VOID
+  );
+
+VOID
+DisableMonitor (
+  VOID
+  );
+
+VOID
+FullMonitorReset (
+  IN UINT32 MonitorPort
+  );
+
+VOID
+ProgramMonitor (
+  IN UINT32           MonitorPort,
+  IN EFI_PEI_SERVICES **PeiServices,
+  IN PEI_STALL_PPI    *StallPpi
+  );
+
+
+VOID
+GetLinkPartnerFullSwing (
+  IN  UINT8 Lane,
+  OUT UINT8 *FullSwing
+  );
+
+VOID
+GetCoefficientsFromPreset (
+  IN  UINT8 Preset,
+  IN  UINT8 FullSwing,
+  OUT UINT8 *PreCursor,
+  OUT UINT8 *Cursor,
+  OUT UINT8 *PostCursor
+  );
+
+VOID
+SetPartnerTxCoefficients (
+  IN  UINT8 Lane,
+  IN  UINT8 *PreCursor,
+  IN  UINT8 *Cursor,
+  IN  UINT8 *PostCursor
+  );
+
+#endif
diff --git a/ReferenceCode/Chipset/SystemAgent/SaInit/Pei/PcieTrainingEqSettings.c b/ReferenceCode/Chipset/SystemAgent/SaInit/Pei/PcieTrainingEqSettings.c
new file mode 100644
index 0000000..dc4515e
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/SaInit/Pei/PcieTrainingEqSettings.c
@@ -0,0 +1,166 @@
+/*++ @file
+  This file adds equalization setting support.
+
+@copyright
+  Copyright (c) 2012 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement
+
+--*/
+
+#include "PcieTraining.h"
+#include "PciExpressInit.h"
+
+#ifdef PEG_FLAG
+
+VOID
+GetLinkPartnerFullSwing (
+  IN  UINT8 Lane,
+  OUT UINT8 *FullSwing
+  )
+{
+  UINT32  Data32;
+
+  Data32 = BIT25 | BIT23 | (Lane << 19) | BIT18;
+  McD1PciCfg32(R_SA_PEG_EQPH3_OFFSET) = Data32;
+  Data32 = McD1PciCfg32(R_SA_PEG_EQPH3_OFFSET);
+  McD1PciCfg32(R_SA_PEG_EQPH3_OFFSET) = 0;
+
+  *FullSwing = (Data32 >> 6) & 0x3F;
+
+  return;
+}
+
+VOID
+GetCoefficientsFromPreset (
+  IN  UINT8 Preset,
+  IN  UINT8 FullSwing,
+  OUT UINT8 *PreCursor,
+  OUT UINT8 *Cursor,
+  OUT UINT8 *PostCursor
+  )
+{
+  INT32   PreCursorMilli;
+  INT32   PostCursorMilli;
+
+  PreCursorMilli  = 0;
+  PostCursorMilli = 0;
+
+  ///
+  /// Get starting values from Table 4-16 of the PCIe Base Spec v3.0
+  ///
+  switch (Preset) {
+    case  0:
+      PreCursorMilli  =    0;
+      PostCursorMilli = -250;
+      break;
+
+    case  1:
+      PreCursorMilli  =    0;
+      PostCursorMilli = -167;
+      break;
+
+    case  2:
+      PreCursorMilli  =    0;
+      PostCursorMilli = -200;
+      break;
+
+    case  3:
+      PreCursorMilli  =    0;
+      PostCursorMilli = -125;
+      break;
+
+    case  4:
+      PreCursorMilli  =    0;
+      PostCursorMilli =    0;
+      break;
+
+    case  5:
+      PreCursorMilli  = -100;
+      PostCursorMilli =    0;
+      break;
+
+    case  6:
+      PreCursorMilli  = -125;
+      PostCursorMilli =    0;
+      break;
+
+    case  7:
+      PreCursorMilli  = -100;
+      PostCursorMilli = -200;
+      break;
+
+    case  8:
+      PreCursorMilli  = -125;
+      PostCursorMilli = -125;
+      break;
+
+    case  9:
+      PreCursorMilli  = -166;
+      PostCursorMilli =    0;
+      break;
+
+    case 10:  ///< P10 is unsupported
+    default:
+      PreCursorMilli  = -100;
+      PostCursorMilli = -200;
+      DEBUG ((EFI_D_WARN, "GetCoefficientsFromPreset(): Unsupported Preset Requested: P%d. Using P7.\n", Preset));
+      break;
+  }
+
+  ///
+  /// Convert to absolute values
+  ///
+  if (PreCursorMilli < 0) {
+    PreCursorMilli *= -1;
+  }
+  if (PostCursorMilli < 0) {
+    PostCursorMilli *= -1;
+  }
+
+  ///
+  /// Apply FullSwing
+  ///
+  PreCursorMilli  *= FullSwing;
+  PostCursorMilli *= FullSwing;
+
+  ///
+  /// Convert to integers
+  ///
+  *PreCursor  = (( PreCursorMilli % 1000) >= 500) ? (UINT8) (( PreCursorMilli / 1000) + 1) : (UINT8) ( PreCursorMilli / 1000);
+  *PostCursor = ((PostCursorMilli % 1000) >= 500) ? (UINT8) ((PostCursorMilli / 1000) + 1) : (UINT8) (PostCursorMilli / 1000);
+  *Cursor     = FullSwing - (*PreCursor) - (*PostCursor);
+
+  return;
+}
+
+VOID
+SetPartnerTxCoefficients (
+  IN  UINT8 Lane,
+  IN  UINT8 *PreCursor,
+  IN  UINT8 *Cursor,
+  IN  UINT8 *PostCursor
+  )
+{
+  UINT32  Data32;
+
+  Data32 = (Lane << 19) | BIT18 | (*Cursor << 12) | (*PreCursor << 6) | (*PostCursor);
+  McD1PciCfg32(R_SA_PEG_EQPH3_OFFSET) = Data32;
+  McD1PciCfg32(R_SA_PEG_EQPH3_OFFSET) = 0;
+
+  return;
+}
+
+#endif // PEG_FLAG
diff --git a/ReferenceCode/Chipset/SystemAgent/SaInit/Pei/PcieTrainingErrorCount.c b/ReferenceCode/Chipset/SystemAgent/SaInit/Pei/PcieTrainingErrorCount.c
new file mode 100644
index 0000000..d1fb107
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/SaInit/Pei/PcieTrainingErrorCount.c
@@ -0,0 +1,195 @@
+/** @file
+  Error Counting for PEG training.
+
+@copyright
+  Copyright (c) 2012 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement
+**/
+
+#include "PcieTraining.h"
+
+#ifdef PEG_FLAG
+
+UINT32
+OpenMonitor (
+  IN EFI_PEI_SERVICES       **PeiServices,
+  IN SA_PLATFORM_POLICY_PPI *SaPlatformPolicyPpi,
+  IN PEI_STALL_PPI          *StallPpi
+  )
+{
+  UINT32 MonitorPort;
+
+  InitMonitor (SaPlatformPolicyPpi->PlatformData->MchBar, SaPlatformPolicyPpi->PlatformData->GdxcBar);
+  MonitorPort = EnableMonitor ();
+  FullMonitorReset (MonitorPort);
+  ProgramMonitor (MonitorPort, PeiServices, StallPpi);
+
+  return MonitorPort;
+}
+
+VOID
+CloseMonitor (
+  IN SA_PLATFORM_POLICY_PPI *SaPlatformPolicyPpi,
+  IN UINT32                 MonitorPort
+  )
+{
+  FullMonitorReset (MonitorPort);
+  DisableMonitor ();
+  TearDownMonitor (SaPlatformPolicyPpi->PlatformData->MchBar, SaPlatformPolicyPpi->PlatformData->GdxcBar);
+
+  return;
+}
+
+UINT32
+SaPcieGetErrorCount (
+  IN UINT32 MonitorPort,
+  IN UINT8  PcieController
+  )
+{
+  UINT32 Data32;
+
+  Data32 = Mmio32 (MonitorPort, (0xC + (PcieController * 0x10)));
+
+  return Data32;
+}
+
+VOID
+SaPcieClearErrorCount (
+  IN UINT32           MonitorPort,
+  IN EFI_PEI_SERVICES **PeiServices,
+  IN PEI_STALL_PPI    *StallPpi
+  )
+{
+  FullMonitorReset (MonitorPort);
+  ProgramMonitor (MonitorPort, PeiServices, StallPpi);
+
+  return;
+}
+
+VOID
+InitMonitor (
+  IN UINT32 MchBar,
+  IN UINT32 GdxcBar
+  )
+{
+  Mmio32 (MchBar, 0x6430)  = 0x3;
+  Mmio32 (MchBar, 0x6434)  = 0x76543210;
+  McD1PciCfg32 (0x630)     = 0xB;
+  McD1PciCfg32 (0x600)     = 0x60B;
+  McD1PciCfg32 (0x604)     = 0x76543980;
+  McD1F1PciCfg32 (0x600)   = 0x60B;
+  McD1F1PciCfg32 (0x604)   = 0x76543280;
+  McD1F2PciCfg32 (0x600)   = 0xB;
+  McD1F2PciCfg32 (0x604)   = 0x76543210;
+  Mmio32 (MchBar, 0x6438)  = 0x680000;
+  Mmio32 (GdxcBar, 0xA04)  = 0xA;
+
+  return;
+}
+
+VOID
+TearDownMonitor (
+  IN UINT32 MchBar,
+  IN UINT32 GdxcBar
+  )
+{
+  Mmio32 (MchBar, 0x6430)  = 0x0;
+  Mmio32 (MchBar, 0x6434)  = 0x0;
+  McD1PciCfg32 (0x630)     = 0x0;
+  McD1PciCfg32 (0x600)     = 0x0;
+  McD1PciCfg32 (0x604)     = 0x0;
+  McD1F1PciCfg32 (0x600)   = 0x0;
+  McD1F1PciCfg32 (0x604)   = 0x0;
+  McD1F2PciCfg32 (0x600)   = 0x0;
+  McD1F2PciCfg32 (0x604)   = 0x0;
+  Mmio32 (MchBar, 0x6438)  = 0x0;
+  Mmio32 (GdxcBar, 0xA04)   = 0x0;
+
+  return;
+}
+
+UINT32
+EnableMonitor (
+  VOID
+  )
+{
+  UINT32 Data32;
+
+  Data32 = (McD0PciCfg32 (0140) & ~(07));
+  Mmio32Or (Data32, 0124, 040000);
+  Mmio64 (Data32, 0700020) = (UINT64) SA_PEI_MONITOR_OFFSET;
+  Mmio16Or (Data32, 0700004, 02);
+
+  return SA_PEI_MONITOR_OFFSET;
+}
+
+VOID
+DisableMonitor (
+  VOID
+  )
+{
+  UINT32 Data32;
+
+  Data32 = (McD0PciCfg32 (0140) & ~(07));
+  Mmio16And (Data32, 0700004, 0177775);
+  Mmio64And (Data32, 0700020, 07777);
+  Mmio32And (Data32, 0124, 037777737777);
+
+  return;
+}
+
+VOID
+FullMonitorReset (
+  IN UINT32 MonitorPort
+  )
+{
+  Mmio32 (MonitorPort, 0x0)  = 0x40000;
+  Mmio32 (MonitorPort, 0x4)  = 0x0;
+  Mmio32 (MonitorPort, 0x10) = 0x40000;
+  Mmio32 (MonitorPort, 0x14) = 0x0;
+  Mmio32 (MonitorPort, 0x20) = 0x40000;
+  Mmio32 (MonitorPort, 0x24) = 0x0;
+  Mmio32 (MonitorPort, 0x8)  = 0xFF000000;
+  Mmio32 (MonitorPort, 0x18) = 0xFF000000;
+  Mmio32 (MonitorPort, 0x28) = 0xFF000000;
+  Mmio32 (MonitorPort, 0xC)  = 0x0;
+  Mmio32 (MonitorPort, 0x1C) = 0x0;
+  Mmio32 (MonitorPort, 0x2C) = 0x0;
+
+  return;
+}
+
+VOID
+ProgramMonitor (
+  IN UINT32           MonitorPort,
+  IN EFI_PEI_SERVICES **PeiServices,
+  IN PEI_STALL_PPI    *StallPpi
+  )
+{
+  Mmio32 (MonitorPort, 0x4)  = 0xA100;
+  Mmio32 (MonitorPort, 0x14) = 0xA101;
+  Mmio32 (MonitorPort, 0x24) = 0xA102;
+  Mmio32 (MonitorPort, 0x0)  = 0x110000;
+  StallPpi->Stall (PeiServices, StallPpi, 1 * STALL_ONE_MILLI_SECOND);
+
+  Mmio32 (MonitorPort, 0x0)  = 0x22100;
+  Mmio32 (MonitorPort, 0x10) = 0x22101;
+  Mmio32 (MonitorPort, 0x20) = 0x22102;
+
+  return;
+}
+
+#endif // PEG_FLAG
diff --git a/ReferenceCode/Chipset/SystemAgent/SaInit/Pei/PcieTrainingLinkRecovery.c b/ReferenceCode/Chipset/SystemAgent/SaInit/Pei/PcieTrainingLinkRecovery.c
new file mode 100644
index 0000000..1480bc7
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/SaInit/Pei/PcieTrainingLinkRecovery.c
@@ -0,0 +1,721 @@
+/*++ @file
+  This driver recovers the PEG link.
+
+@copyright
+  Copyright (c) 2012 - 2014 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement
+
+--*/
+
+#include "PcieTraining.h"
+#include "PciExpressInit.h"
+#include EFI_PPI_CONSUMER (PchReset)
+
+#ifdef PEG_FLAG
+
+EFI_STATUS
+EnsureLinkIsHealthy (
+  IN EFI_PEI_SERVICES       **PeiServices,
+  IN SA_PLATFORM_POLICY_PPI *SaPlatformPolicyPpi,
+  IN SA_DATA_HOB            *SaDataHob,
+  IN PEI_STALL_PPI          *StallPpi,
+  IN PEG_PORT               *PegPort,
+  IN UINT8                  OriginalLinkSpeed,
+  IN UINT8                  OriginalLinkWidth
+  )
+{
+  EFI_STATUS Status;
+
+  Status = EFI_SUCCESS;
+
+  ///
+  /// Check Link Status and Recover the Link if needed
+  ///
+  Status = RecoverLinkWidth (PeiServices, StallPpi, PegPort, OriginalLinkWidth);
+  if (EFI_ERROR (Status)) {
+    Status = RecoverLinkFailure (PeiServices, SaPlatformPolicyPpi, SaDataHob, StallPpi, PegPort, OriginalLinkSpeed, OriginalLinkWidth);
+    if (EFI_ERROR (Status)) {
+      return Status;
+    }
+  }
+  Status = RecoverLinkSpeed (PeiServices, StallPpi, PegPort, OriginalLinkSpeed);
+  if (EFI_ERROR (Status)) {
+    Status = RecoverLinkFailure (PeiServices, SaPlatformPolicyPpi, SaDataHob, StallPpi, PegPort, OriginalLinkSpeed, OriginalLinkWidth);
+    if (EFI_ERROR (Status)) {
+      return Status;
+    }
+  }
+  Status = WaitForL0 (PeiServices, StallPpi, PegPort, FALSE);
+  if (EFI_ERROR (Status)) {
+    DEBUG ((EFI_D_INFO, "DOWNGRADE, Link is not in L0\n"));
+    Status = RetrainLink (PeiServices, StallPpi, PegPort);
+    if (EFI_ERROR (Status)) {
+      Status = RecoverLinkFailure (PeiServices, SaPlatformPolicyPpi, SaDataHob, StallPpi, PegPort, OriginalLinkSpeed, OriginalLinkWidth);
+      if (EFI_ERROR (Status)) {
+        return Status;
+      }
+    }
+  }
+
+  return Status;
+}
+
+/**
+  Wait until link is up.
+
+  @param[in] PeiServices  - Pointer to the PEI services table
+  @param[in] StallPpi     - Pointer to PEI_STALL_PPI
+  @param[in] PegPort      - Pointer PEG Port
+  @param[in] UseVcu       - If TRUE, use VCU to determine link state.  If FALSE, use MMIO CFG to determine link state.
+
+  @retval EFI_SUCCESS     - Completed successfully before timeout
+  @retval EFI_TIMEOUT     - Timed out
+**/
+EFI_STATUS
+WaitForL0 (
+  IN EFI_PEI_SERVICES **PeiServices,
+  IN PEI_STALL_PPI    *StallPpi,
+  IN PEG_PORT         *PegPort,
+  IN BOOLEAN          UseVcu
+  )
+{
+  UINT32        MchBar;
+  UINT32        i;
+  EFI_STATUS    Status;
+  UINT32        VcuAddress;
+  UINT8         VcuReadOp;
+  UINT8         VcuWriteOp;
+  CPU_FAMILY    CpuFamilyId;
+  CPU_STEPPING  CpuSteppingId;
+  BOOLEAN       CheckEq;
+  BOOLEAN       CompletedEq;
+  UINT32        EqStatus;
+  UINT32        LinkStatus;
+
+  Status         = EFI_TIMEOUT;
+  CheckEq        = (PegPort->EndpointMaxLinkSpeed >= 0x3) ? TRUE : FALSE;
+  CompletedEq    = FALSE;
+  i              = 0;
+  MchBar         = McD0PciCfg64 (R_SA_MCHBAR) & ~BIT0;
+  CpuFamilyId    = GetCpuFamily();
+  CpuSteppingId  = GetCpuStepping();
+
+#ifndef AMI_OVERRIDE_FOR_ULT_FASTBOOT
+  if (CpuFamilyId == EnumCpuHswUlt) return EFI_UNSUPPORTED;
+#endif // AMI_OVERRIDE_FOR_ULT_FASTBOOT
+
+  if ((CpuFamilyId == EnumCpuHsw) && (CpuSteppingId == EnumHswA0)) {
+    VcuAddress = R_SA_VCU_REUT_PH1_PIS_ADDRESS_REV1;
+    VcuReadOp  = V_SA_VCU_OPCODE_READ_CSR_REV1;
+    VcuWriteOp = V_SA_VCU_OPCODE_WRITE_CSR_REV1;
+  } else {
+    VcuAddress = R_SA_VCU_REUT_PH1_PIS_ADDRESS_REV2;
+    VcuReadOp  = V_SA_VCU_OPCODE_READ_CSR_REV2;
+    VcuWriteOp = V_SA_VCU_OPCODE_WRITE_CSR_REV2;
+  }
+
+  ///
+  /// If endpoint's LCAP.MLS (Spec section 7.8.6) indicated Gen3 capability, first wait for equalization to complete.
+  /// Check equalization status LSTS2.EC (Spec section 7.8.20) until Gen3 equalization successfully completed.
+  ///
+  if (CheckEq && !UseVcu) {
+    for (; i < 100; i++) {
+      EqStatus = MmPci16 (0, PegPort->Bus, PegPort->Device, PegPort->Function, R_SA_PEG_LSTS2_OFFSET);
+      EqStatus = (EqStatus >> 1) & 0x1;
+      if (EqStatus == 0x1) {
+        CompletedEq = TRUE;
+        break;
+      }
+      StallPpi->Stall (PeiServices, StallPpi, STALL_ONE_MILLI_SECOND);
+    }
+  }
+
+  ///
+  /// Check for L0 status.  If !UseVcu, check PEGSTS.
+  /// Continue up to 100 msec of combined delay.
+  /// Skip if equalization was needed but didn't successfully complete.
+  ///
+  if ((CheckEq && CompletedEq) || !CheckEq || UseVcu) {
+    for (; i < 100; i++) {
+      if (UseVcu) {
+        LinkStatus = SendVcuApiSequence (MchBar, VcuAddress, VcuReadOp, 0);
+        LinkStatus = (LinkStatus >> (PegPort->Function * B_SA_PEG_REUT_PH1_PIS_ST_STEP)) & B_SA_PEG_REUT_PH1_PIS_ST_MASK;
+        if (LinkStatus == 0x10) {
+          Status = EFI_SUCCESS;
+          break;
+        }
+      } else {
+        LinkStatus = MmPci32 (0, PegPort->Bus, PegPort->Device, PegPort->Function, R_SA_PEG_PEGSTS_OFFSET);
+        LinkStatus = (LinkStatus >> 16) & 0xF;
+        if (LinkStatus == 0x7) {
+          Status = EFI_SUCCESS;
+          break;
+        }
+      }
+      StallPpi->Stall (PeiServices, StallPpi, STALL_ONE_MILLI_SECOND);
+    }
+  }
+
+  return Status;
+}
+
+EFI_STATUS
+SetPchGpio (
+  IN UINT8    GpioNumber,
+  IN UINT8    Level
+  )
+/**
+  This function sets a GPIO to a particular level.
+
+  @param[in] GpioNumber          - PCH GPIO number
+  @param[in] Level               - 0 = Low, 1 = High
+
+  @retval EFI_SUCCESS            - Did toggle GPIO
+  @retval EFI_UNSUPPORTED        - Didn't toggle GPIO
+  @retval EFI_INVALID_PARAMETER  - Didn't toggle GPIO
+**/
+{
+  UINT32      Data32;
+  UINT16      LpcDeviceId;
+  UINT16      GpioBase;
+  UINT16      UseSelOffset;
+  UINT16      IoSelOffset;
+  UINT16      LvlOffset;
+  UINT8       GpioBit;
+  EFI_STATUS  Status;
+
+  Level       &= 0x1;
+  Status       = EFI_SUCCESS;
+  GpioBase     = 0;
+  UseSelOffset = 0;
+  IoSelOffset  = 0;
+  LvlOffset    = 0;
+  GpioBit      = 0;
+
+  LpcDeviceId = McDevFunPciCfg16 (
+                  DEFAULT_PCI_BUS_NUMBER_PCH,
+                  PCI_DEVICE_NUMBER_PCH_LPC,
+                  PCI_FUNCTION_NUMBER_PCH_LPC,
+                  R_PCH_LPC_DEVICE_ID
+                  );
+  if (!IS_PCH_LPT_LPC_DEVICE_ID (LpcDeviceId)) {
+    Status = EFI_UNSUPPORTED;
+    return Status;
+  }
+
+  GpioBase = McDevFunPciCfg16 (
+               DEFAULT_PCI_BUS_NUMBER_PCH,
+               PCI_DEVICE_NUMBER_PCH_LPC,
+               PCI_FUNCTION_NUMBER_PCH_LPC,
+               R_PCH_LPC_GPIO_BASE
+               ) & B_PCH_LPC_GPIO_BASE_BAR;
+  if (GpioBase == 0) {
+    Status = EFI_UNSUPPORTED;
+    return Status;
+  }
+
+  if (GpioNumber < 0x20) {
+    UseSelOffset = R_PCH_GPIO_USE_SEL;
+    IoSelOffset  = R_PCH_GPIO_IO_SEL;
+    LvlOffset    = R_PCH_GPIO_LVL;
+    GpioBit      = GpioNumber;
+  } else if (GpioNumber < 0x40) {
+    UseSelOffset = R_PCH_GPIO_USE_SEL2;
+    IoSelOffset  = R_PCH_GPIO_IO_SEL2;
+    LvlOffset    = R_PCH_GPIO_LVL2;
+    GpioBit      = GpioNumber - 0x20;
+  } else if (GpioNumber < 0x60) {
+    UseSelOffset = R_PCH_GPIO_USE_SEL3;
+    IoSelOffset  = R_PCH_GPIO_IO_SEL3;
+    LvlOffset    = R_PCH_GPIO_LVL3;
+    GpioBit      = GpioNumber - 0x40;
+  } else {
+    Status = EFI_INVALID_PARAMETER;
+    return Status;
+  }
+
+  if (!EFI_ERROR (Status)) {
+    DEBUG ((EFI_D_INFO, "Setting GPIO%d to %x\n", GpioNumber, Level));
+    IoOr32    ((UINTN) (GpioBase + UseSelOffset), (UINT32)  (1 << GpioBit));
+    IoAnd32   ((UINTN) (GpioBase + IoSelOffset),  (UINT32) ~(1 << GpioBit));
+    Data32   = IoRead32  ((UINTN) (GpioBase + LvlOffset));
+    Data32  &= (UINT32) ~(1     << GpioBit);
+    Data32  |= (UINT32)  (Level << GpioBit);
+    IoWrite32 ((UINTN) (GpioBase + LvlOffset), Data32);
+  }
+
+  return Status;
+}
+
+EFI_STATUS
+TogglePegSlotReset (
+  IN EFI_PEI_SERVICES       **PeiServices,
+  IN PEI_STALL_PPI          *StallPpi,
+  IN SA_PLATFORM_POLICY_PPI *SaPlatformPolicyPpi
+  )
+/**
+  This function asserts and deasserts a GPIO that controls PERST#.
+  The specific GPIO and its active level is provided by a policy.
+  The GPIO minimum assertion time, T_PERST (100 usec), is defined in the PCIe CEM Specification.
+
+  @param[in] PeiServices         - Pointer to the PEI services table
+  @param[in] StallPpi            - Pointer to PEI_STALL_PPI
+  @param[in] SaPlatformPolicyPpi - Pointer to SA_PLATFORM_POLICY_PPI
+
+  @retval EFI_SUCCESS            - Did toggle GPIO
+  @retval EFI_UNSUPPORTED        - Didn't toggle GPIO
+  @retval EFI_INVALID_PARAMETER  - Didn't toggle GPIO
+**/
+{
+  EFI_STATUS  Status;
+  UINT8       i;
+
+  DEBUG ((EFI_D_INFO, "Toggling PEG slot reset.\n"));
+  for (i = 0; i < SA_PEG_MAX_FUN; i++) {
+    MmPci16Or (0, SA_PEG_BUS_NUM, SA_PEG_DEV_NUM, i, R_SA_PEG_LCTL_OFFSET, BIT4);
+  }
+  Status = AssertPegSlotReset (SaPlatformPolicyPpi);
+  if (!EFI_ERROR (Status)) {
+    StallPpi->Stall (PeiServices, StallPpi, 100 * STALL_ONE_MICRO_SECOND);
+    for (i = 0; i < SA_PEG_MAX_FUN; i++) {
+      MmPci16And (0, SA_PEG_BUS_NUM, SA_PEG_DEV_NUM, i, R_SA_PEG_LCTL_OFFSET, (UINT16) ~(BIT4));
+    }
+    Status = DeassertPegSlotReset (SaPlatformPolicyPpi);
+  } else {
+    for (i = 0; i < SA_PEG_MAX_FUN; i++) {
+      MmPci16And (0, SA_PEG_BUS_NUM, SA_PEG_DEV_NUM, i, R_SA_PEG_LCTL_OFFSET, (UINT16) ~(BIT4));
+    }
+  }
+
+  return Status;
+}
+
+EFI_STATUS
+AssertPegSlotReset (
+  IN SA_PLATFORM_POLICY_PPI *SaPlatformPolicyPpi
+  )
+/**
+  This function asserts a GPIO that controls PERST#.
+  The specific GPIO and its active level is provided by a policy.
+  The GPIO minimum assertion time, T_PERST (100 usec), is defined in the PCIe CEM Specification.
+
+  @param[in] SaPlatformPolicyPpi - Pointer to SA_PLATFORM_POLICY_PPI
+
+  @retval EFI_SUCCESS            - Did assert GPIO
+  @retval EFI_UNSUPPORTED        - Didn't assert GPIO
+  @retval EFI_INVALID_PARAMETER  - Didn't assert GPIO
+**/
+{
+  EFI_STATUS  Status;
+  UINT8       GpioNumber;
+  UINT8       AssertLevel;
+
+  Status = EFI_SUCCESS;
+
+  DEBUG ((EFI_D_INFO, "Asserting PEG slot reset.\n"));
+
+  if (!((SaPlatformPolicyPpi->Revision >= SA_PLATFORM_POLICY_PPI_REVISION_3) &&
+        (SaPlatformPolicyPpi->PcieConfig->PegGpioData->GpioSupport == TRUE))) {
+    Status = EFI_UNSUPPORTED;
+  }
+
+  if (!EFI_ERROR (Status)) {
+    GpioNumber  = (UINT8) (SaPlatformPolicyPpi->PcieConfig->PegGpioData->SaPegReset->Value);
+    AssertLevel = (UINT8) (SaPlatformPolicyPpi->PcieConfig->PegGpioData->SaPegReset->Active & 0x1);
+    Status      = SetPchGpio (GpioNumber, AssertLevel);
+  }
+
+  return Status;
+}
+
+EFI_STATUS
+DeassertPegSlotReset (
+  IN SA_PLATFORM_POLICY_PPI *SaPlatformPolicyPpi
+  )
+/**
+  This function deasserts a GPIO that controls PERST#.
+  The specific GPIO and its active level is provided by a policy.
+  The GPIO minimum assertion time, T_PERST (100 usec), is defined in the PCIe CEM Specification.
+
+  @param[in] SaPlatformPolicyPpi - Pointer to SA_PLATFORM_POLICY_PPI
+
+  @retval EFI_SUCCESS            - Did deassert GPIO
+  @retval EFI_UNSUPPORTED        - Didn't deassert GPIO
+  @retval EFI_INVALID_PARAMETER  - Didn't deassert GPIO
+**/
+{
+  EFI_STATUS  Status;
+  UINT8       GpioNumber;
+  UINT8       DeassertLevel;
+
+  Status = EFI_SUCCESS;
+
+  DEBUG ((EFI_D_INFO, "Deasserting PEG slot reset.\n"));
+
+  if (!((SaPlatformPolicyPpi->Revision >= SA_PLATFORM_POLICY_PPI_REVISION_3) &&
+        (SaPlatformPolicyPpi->PcieConfig->PegGpioData->GpioSupport == TRUE))) {
+    Status = EFI_UNSUPPORTED;
+  }
+
+  if (!EFI_ERROR (Status)) {
+    GpioNumber    = (UINT8)  (SaPlatformPolicyPpi->PcieConfig->PegGpioData->SaPegReset->Value);
+    DeassertLevel = (UINT8) ((SaPlatformPolicyPpi->PcieConfig->PegGpioData->SaPegReset->Active & 0x1) ^ 0x1);
+    SetPchGpio (GpioNumber, DeassertLevel);
+  }
+
+  return Status;
+}
+
+EFI_STATUS
+RecoverLinkFailure (
+  IN EFI_PEI_SERVICES       **PeiServices,
+  IN SA_PLATFORM_POLICY_PPI *SaPlatformPolicyPpi,
+  IN SA_DATA_HOB            *SaDataHob,
+  IN PEI_STALL_PPI          *StallPpi,
+  IN PEG_PORT               *PegPort,
+  IN UINT8                  OriginalLinkSpeed,
+  IN UINT8                  OriginalLinkWidth
+  )
+{
+  EFI_STATUS Status;
+  UINT8      CurrentLinkWidth;
+  UINT8      CurrentLinkSpeed;
+  UINT8      PegBus;
+  UINT8      PegDev;
+  UINT8      PegFunc;
+
+  ///
+  /// A platform reset should be done after presets are saved in NVRAM
+  ///
+  if (SaDataHob != NULL) {
+    if ((SaPlatformPolicyPpi->Revision >= SA_PLATFORM_POLICY_PPI_REVISION_2) &&
+        (SaPlatformPolicyPpi->PcieConfig->PegGen3ForcePresetSearch == 0)) {
+      SaDataHob->PegPlatformResetRequired = TRUE;
+    } else if (SaPlatformPolicyPpi->Revision < SA_PLATFORM_POLICY_PPI_REVISION_2) {
+      SaDataHob->PegPlatformResetRequired = TRUE;
+    }
+  }
+
+  ///
+  /// Bypass phase2 and assert slot reset
+  ///
+  McD1PciCfg32Or (R_SA_PEG_EQCFG_OFFSET, BIT15);
+  Status = TogglePegSlotReset (PeiServices, StallPpi, SaPlatformPolicyPpi);
+  if (EFI_ERROR (Status)) {
+    DEBUG ((EFI_D_INFO, "Error 0x%x.\n", Status));
+  } else {
+    DEBUG ((EFI_D_INFO, "Success.\n"));
+  }
+  PegBus  = PegPort->Bus;
+  PegDev  = PegPort->Device;
+  PegFunc = PegPort->Function;
+  ///
+  /// Wait for Equalization Done
+  ///
+  while (((MmPci32 (0, PegBus, PegDev, PegFunc, R_SA_PEG_LSTS2_OFFSET) >> 1) & 0x1) != 0x1);
+  ///
+  /// Wait for flow control credits exchange
+  ///
+  WaitForVc0Negotiation (PeiServices, StallPpi, PegBus, PegDev, PegFunc);
+
+  CurrentLinkWidth = GetNegotiatedWidth (PegPort);
+  if (CurrentLinkWidth < OriginalLinkWidth) {
+    DEBUG ((EFI_D_ERROR, "Link Width DOWNGRADED!\n"));
+    Status = EFI_TIMEOUT;
+  }
+  CurrentLinkSpeed = GetLinkSpeed (PegPort);
+  if (CurrentLinkSpeed < OriginalLinkSpeed) {
+    DEBUG ((EFI_D_ERROR, "Link Speed DOWNGRADED!\n"));
+    Status = EFI_TIMEOUT;
+  }
+
+  return Status;
+}
+
+BOOLEAN
+LinkIsDowngraded (
+  IN PEG_PORT *PegPort,
+  IN UINT8    OriginalLinkSpeed,
+  IN UINT8    OriginalLinkWidth
+  )
+{
+  BOOLEAN   IsDowngraded;
+
+  IsDowngraded = FALSE;
+
+  if (OriginalLinkSpeed != GetLinkSpeed (PegPort)) {
+    DEBUG ((EFI_D_INFO, "Link speed downgrade detected\n"));
+    IsDowngraded = TRUE;
+  }
+  if (OriginalLinkWidth != GetNegotiatedWidth (PegPort)) {
+    DEBUG ((EFI_D_INFO, "Link width downgrade detected\n"));
+    IsDowngraded = TRUE;
+  }
+  return IsDowngraded;
+}
+
+EFI_STATUS
+SecondaryBusReset (
+  IN EFI_PEI_SERVICES **PeiServices,
+  IN PEI_STALL_PPI    *StallPpi,
+  IN PEG_PORT         *PegPort
+  )
+{
+  EFI_STATUS Status;
+
+  Status = EFI_SUCCESS;
+  DEBUG ((EFI_D_INFO, "SECONDARY BUS RESET!\n"));
+  MmPci16Or (0, PegPort->Bus, PegPort->Device, PegPort->Function, R_SA_PEG_BCTRL_OFFSET, B_SA_PEG_BCTRL_SRESET_MASK);
+  MmPci16And (0, PegPort->Bus, PegPort->Device, PegPort->Function, R_SA_PEG_BCTRL_OFFSET,~(B_SA_PEG_BCTRL_SRESET_MASK));
+  Status = WaitForL0 (PeiServices, StallPpi, PegPort, FALSE);
+  DEBUG ((EFI_D_INFO, "Reset Complete\n"));
+
+  return Status;
+}
+
+EFI_STATUS
+ResetPhyLayer (
+  IN EFI_PEI_SERVICES **PeiServices,
+  IN PEI_STALL_PPI    *StallPpi,
+  IN PEG_PORT         *PegPort
+  )
+{
+  EFI_STATUS        Status;
+  UINT32            MchBar;
+  UINT32            Data32;
+  UINT32            VcuAddress;
+  UINT8             VcuReadOp;
+  UINT8             VcuWriteOp;
+  BOOLEAN           UseVcu;
+  CPU_FAMILY        CpuFamilyId;
+  CPU_STEPPING      CpuSteppingId;
+
+  UseVcu        = TRUE;
+  Status        = EFI_SUCCESS;
+  MchBar        = McD0PciCfg64 (R_SA_MCHBAR) &~BIT0;
+  CpuFamilyId   = GetCpuFamily();
+  CpuSteppingId = GetCpuStepping();
+
+#ifndef AMI_OVERRIDE_FOR_ULT_FASTBOOT
+  if (CpuFamilyId == EnumCpuHswUlt) return EFI_UNSUPPORTED;
+#endif // AMI_OVERRIDE_FOR_ULT_FASTBOOT
+
+  if ((CpuFamilyId == EnumCpuHsw) && (CpuSteppingId == EnumHswA0)) {
+    VcuAddress = R_SA_VCU_REUT_PH_CTR_ADDRESS_REV1;
+    VcuReadOp  = V_SA_VCU_OPCODE_READ_CSR_REV1;
+    VcuWriteOp = V_SA_VCU_OPCODE_WRITE_CSR_REV1;
+  } else {
+    VcuAddress = R_SA_VCU_REUT_PH_CTR_ADDRESS_REV2;
+    VcuReadOp  = V_SA_VCU_OPCODE_READ_CSR_REV2;
+    VcuWriteOp = V_SA_VCU_OPCODE_WRITE_CSR_REV2;
+  }
+
+  DEBUG ((EFI_D_INFO, "PHY LAYER RESET!\n"));
+  if (UseVcu) {
+    Data32  = SendVcuApiSequence (MchBar, VcuAddress, VcuReadOp, 0);
+    Data32 &= (UINT32) ~(BIT1);
+    SendVcuApiSequence (MchBar, VcuAddress, VcuWriteOp, Data32);
+  } else {
+    McD1PciCfg32And (R_SA_PEG_REUT_PH_CTR_OFFSET, ~(B_SA_PEG_REUT_PH_CTR_RESETMOD_MASK));
+  }
+
+  if (UseVcu) {
+    Data32  = SendVcuApiSequence (MchBar, VcuAddress, VcuReadOp, 0);
+    Data32 |= (UINT32) BIT0;
+    SendVcuApiSequence (MchBar, VcuAddress, VcuWriteOp, Data32);
+  } else {
+    McD1PciCfg32Or (R_SA_PEG_REUT_PH_CTR_OFFSET, B_SA_PEG_REUT_PH_CTR_PHYRESET_MASK);
+  }
+
+  if (UseVcu) {
+    Data32  = SendVcuApiSequence (MchBar, VcuAddress, VcuReadOp, 0);
+    Data32 |= (UINT32) BIT13;
+    SendVcuApiSequence (MchBar, VcuAddress, VcuWriteOp, Data32);
+  } else {
+    McD1PciCfg32Or (R_SA_PEG_REUT_PH_CTR_OFFSET, B_SA_PEG_REUT_PH_CTR_AUTOCOMP_MASK);
+  }
+
+  if (UseVcu) {
+    Data32  = SendVcuApiSequence (MchBar, VcuAddress, VcuReadOp, 0);
+    Data32 &= (UINT32) ~(BIT0);
+    SendVcuApiSequence (MchBar, VcuAddress, VcuWriteOp, Data32);
+  } else {
+    McD1PciCfg32And (R_SA_PEG_REUT_PH_CTR_OFFSET, ~(B_SA_PEG_REUT_PH_CTR_PHYRESET_MASK));
+  }
+
+  Status = WaitForL0 (PeiServices, StallPpi, PegPort, TRUE);
+  DEBUG ((EFI_D_INFO, "Reset Complete\n"));
+
+  return Status;
+}
+
+EFI_STATUS
+RetrainLink (
+  IN EFI_PEI_SERVICES **PeiServices,
+  IN PEI_STALL_PPI    *StallPpi,
+  IN PEG_PORT         *PegPort
+  )
+{
+  EFI_STATUS Status;
+
+  ///
+  /// Initiate Link Retrain
+  ///
+  MmPci16Or (0, PegPort->Bus, PegPort->Device, PegPort->Function, R_SA_PEG_LCTL_OFFSET, 0x20);
+
+  Status = WaitForL0 (PeiServices, StallPpi, PegPort, FALSE);
+  if (EFI_ERROR (Status)) {
+    DEBUG ((EFI_D_INFO, "Link retrain FAILED!!!\n"));
+  }
+
+  return Status;
+}
+
+UINT8
+GetNegotiatedWidth (
+  IN PEG_PORT *PegPort
+  )
+{
+  UINT16 Lsts;
+
+  Lsts = MmPci16 (0, PegPort->Bus, PegPort->Device, PegPort->Function, R_SA_PEG_LSTS_OFFSET);
+
+  return (UINT8)((Lsts >> 4) & 0x3F);
+}
+
+EFI_STATUS
+RecoverLinkWidth (
+  IN EFI_PEI_SERVICES **PeiServices,
+  IN PEI_STALL_PPI    *StallPpi,
+  IN PEG_PORT         *PegPort,
+  IN UINT8            OriginalLinkWidth
+  )
+{
+  EFI_STATUS Status;
+  UINT8      CurrentLinkWidth;
+
+  Status = EFI_SUCCESS;
+
+  CurrentLinkWidth = GetNegotiatedWidth (PegPort);
+  if (CurrentLinkWidth < OriginalLinkWidth) {
+    DEBUG ((EFI_D_INFO, "DOWNGRADE from x%d to x%d detected\n", OriginalLinkWidth, CurrentLinkWidth));
+    MmPci32AndThenOr (
+      0,
+      PegPort->Bus,
+      PegPort->Device,
+      PegPort->Function,
+      R_SA_PEG_LTSSMC_OFFSET,
+      B_SA_PEG_LTSSMC_WIDTH_MASK,
+      OriginalLinkWidth
+    );
+    MmPci16Or (0, PegPort->Bus, PegPort->Device, PegPort->Function, R_SA_PEG_LCTL_OFFSET, 0x10);
+    StallPpi->Stall (PeiServices, StallPpi, STALL_ONE_MICRO_SECOND);
+    MmPci16And (0, PegPort->Bus, PegPort->Device, PegPort->Function, R_SA_PEG_LCTL_OFFSET, 0xFFEF);
+    Status = WaitForL0 (PeiServices, StallPpi, PegPort, FALSE);
+    MmPci32Or (
+      0,
+      PegPort->Bus,
+      PegPort->Device,
+      PegPort->Function,
+      R_SA_PEG_LTSSMC_OFFSET,
+      0x1F
+    );
+    if (EFI_ERROR (Status)) {
+      return Status;
+    }
+
+    CurrentLinkWidth = GetNegotiatedWidth (PegPort);
+    if (CurrentLinkWidth == OriginalLinkWidth) {
+      DEBUG ((EFI_D_INFO, "Width Recovery Successful\n"));
+      Status = EFI_SUCCESS;
+    } else {
+      DEBUG ((EFI_D_INFO, "Width Recovery FAILED!\n"));
+      Status = EFI_DEVICE_ERROR;
+    }
+  }
+
+  return Status;
+}
+
+UINT8
+GetLinkSpeed (
+  IN PEG_PORT *PegPort
+  )
+{
+  UINT16 Lsts;
+
+  Lsts = MmPci16 (0, PegPort->Bus, PegPort->Device, PegPort->Function, R_SA_PEG_LSTS_OFFSET);
+
+  return (UINT8)(Lsts & 0xF);
+}
+
+EFI_STATUS
+RecoverLinkSpeed (
+  IN EFI_PEI_SERVICES **PeiServices,
+  IN PEI_STALL_PPI    *StallPpi,
+  IN PEG_PORT         *PegPort,
+  IN UINT8            OriginalLinkSpeed
+  )
+{
+  EFI_STATUS Status;
+  UINT8      CurrentLinkSpeed;
+
+  Status = EFI_SUCCESS;
+
+  CurrentLinkSpeed = GetLinkSpeed (PegPort);
+  if (CurrentLinkSpeed < OriginalLinkSpeed) {
+    DEBUG ((EFI_D_INFO, "DOWNGRADE from Gen %d to Gen %d detected\n", OriginalLinkSpeed, CurrentLinkSpeed));
+
+    Status = RetrainLink (PeiServices, StallPpi, PegPort);
+    if (EFI_ERROR (Status)) {
+      DEBUG ((EFI_D_INFO, "Link Speed Recovery FAILED!\n"));
+      return Status;
+    }
+
+    CurrentLinkSpeed = GetLinkSpeed (PegPort);
+    if (CurrentLinkSpeed < OriginalLinkSpeed) {
+      DEBUG ((EFI_D_INFO, "Link Speed Recovery FAILED!\n"));
+      Status = EFI_DEVICE_ERROR;
+    } else {
+      DEBUG ((EFI_D_INFO, "Link Speed Recovery Successful\n"));
+    }
+  }
+
+  return Status;
+}
+
+VOID
+PcieTrainingWarmReset (
+  IN EFI_PEI_SERVICES **PeiServices
+  )
+{
+  EFI_STATUS      Status;
+  PCH_RESET_PPI   *PchResetPpi;
+
+  Status = (*PeiServices)->LocatePpi (
+                              PeiServices,
+                              &gPchResetPpiGuid,
+                              0,
+                              NULL,
+                              &PchResetPpi
+                              );
+  ASSERT_EFI_ERROR (Status);
+  PchResetPpi->Reset (PchResetPpi, WarmReset);
+
+  return;
+}
+
+#endif // PEG_FLAG
diff --git a/ReferenceCode/Chipset/SystemAgent/SaInit/Pei/PcieTrainingMargining.c b/ReferenceCode/Chipset/SystemAgent/SaInit/Pei/PcieTrainingMargining.c
new file mode 100644
index 0000000..7d2f63d
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/SaInit/Pei/PcieTrainingMargining.c
@@ -0,0 +1,223 @@
+/** @file
+  Margining for PEG Training
+
+@copyright
+  Copyright (c) 2012 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement
+**/
+
+#include "PcieTraining.h"
+
+#ifdef PEG_FLAG
+
+///
+/// Jitter Calculations
+///
+JITTER_SETTING Jitter_Gen3[/* 083.333 */] = {{1, 64, 1, 0}, {1, 33, 2, 0}, {3, 64, 3, 0}, {4, 80, 4, 0}, {5, 97, 5, 0}, {6, 128, 6, 0}, {7, 129, 7, 0}, {8, 161, 8, 0}, {9, 192, 9, 0}, {10, 193, 10, 0}, {11, 225, 11, 0}, {12, 128, 12, 1}, {13, 129, 13, 1}, {14, 145, 14, 1}, {15, 160, 15, 1}, {16, 161, 16, 1}, {17, 177, 17, 1}, {18, 192, 18, 1}, {19, 193, 19, 1}, {20, 209, 20, 1}, {21, 224, 21, 1}, {22, 225, 22, 1}, {23, 241, 23, 1}, {24, 246, 24, 1}};
+
+EFI_STATUS
+SetJitterTolerance (
+  IN UINT8 *LaneList,
+  IN UINT8 LaneListLength,
+  IN UINT8 ReportedMargin
+  )
+{
+  JITTER_SETTING Settings = {0, 0, 0, 0};
+  UINT8         i;
+  BOOLEAN       Found;
+
+  if (ReportedMargin > 0) {
+    Found = FALSE;
+    for (i = 0; i < (JITTER_LENGTH - 1); ++i) {
+      Settings = Jitter_Gen3[i];
+      if (Settings.ReportedMargin == ReportedMargin) {
+        Found = TRUE;
+        break;
+      }
+    }
+
+    if (Found) {
+      return SetRawJitterTolerance (
+                                      LaneList,
+                                      LaneListLength,
+                                      Settings.Step,
+                                      Settings.Depth,
+                                      Settings.DoubleMargin,
+                                      TRUE
+                                    );
+    } else {
+      return EFI_INVALID_PARAMETER;
+    }
+  } else {
+    return SetRawJitterTolerance (
+                                   LaneList,
+                                   LaneListLength,
+                                   Settings.Step,
+                                   Settings.Depth,
+                                   Settings.DoubleMargin,
+                                   FALSE
+                                 );
+  }
+}
+
+EFI_STATUS
+SetRawJitterTolerance (
+  IN UINT8   *LaneList,
+  IN UINT8   LaneListLength,
+  IN UINT8   Step,
+  IN UINT8   Depth,
+  IN UINT8   DoubleMargin,
+  IN BOOLEAN EnableJitter
+  )
+{
+  UINT8 BundleList[8];
+  UINT8 BundleListLength;
+  UINT8 i;
+  UINT8 Lane;
+  UINT8 Bundle;
+
+  BundleListLength = 0;
+
+  GetBundleList (LaneList, LaneListLength, &BundleList[0], &BundleListLength);
+
+  for (i = 0; i < LaneListLength; ++i) {
+    Lane = LaneList[i];
+
+    McD1PciCfg32And (R_SA_PEG_AFELN0CFG0_OFFSET + (Lane * LANE_STEP), 0xFFFFFBFF);
+  }
+
+  for (i = 0; i < BundleListLength; ++i) {
+    Bundle = BundleList[i];
+
+    McD1PciCfg32AndThenOr (
+      R_SA_PEG_AFEBND0CFG0_OFFSET + (Bundle * BUNDLE_STEP),
+      (UINT32) ~(BIT28 | BIT17 | BIT16 | BIT15 | BIT14 | BIT13 | BIT12 | BIT11 | BIT10),
+      (UINT32)  ((DoubleMargin << 28) | (Step << 10))
+    );
+
+    McD1PciCfg32AndThenOr (
+      R_SA_PEG_AFEBND0CFG3_OFFSET + (Bundle * BUNDLE_STEP),
+      (UINT32) ~(BIT16 | BIT15 | BIT14 | BIT13 | BIT12 | BIT11),
+      (UINT32)  (Depth << 11)
+    );
+  }
+
+  if (EnableJitter) {
+    for (i = 0; i < LaneListLength; ++i) {
+      Lane = LaneList[i];
+      McD1PciCfg32Or (R_SA_PEG_AFELN0CFG0_OFFSET + (Lane * LANE_STEP), BIT10);
+    }
+  }
+
+  return EFI_SUCCESS;
+}
+
+VOID
+EnableTxJitterInjection (
+  IN UINT8   Lane,
+  IN BOOLEAN EnableTxJitter
+  )
+{
+  UINT8 Bundle;
+
+  Bundle = Lane / 2;
+
+  if (EnableTxJitter) {
+    McD1PciCfg32AndThenOr (
+      R_SA_PEG_AFEBND0CFG0_OFFSET + (Bundle * BUNDLE_STEP),
+      ~(BIT1 | BIT2),
+      0x6
+    );
+  } else {
+    McD1PciCfg32And (
+      R_SA_PEG_AFEBND0CFG0_OFFSET + (Bundle * BUNDLE_STEP),
+      ~(BIT1 | BIT2)
+    );
+  }
+}
+
+
+VOID
+ConfigureTxJitterMux (
+  IN UINT8  Lane,
+  IN UINT32 MchBar
+  )
+{
+  CPU_FAMILY        CpuFamilyId;
+  CPU_STEPPING      CpuSteppingId;
+  UINT32            SequenceId;
+
+  CpuFamilyId   = GetCpuFamily ();
+  CpuSteppingId = GetCpuStepping ();
+  SequenceId    = V_SA_VCU_SEQID_SET_TXJITTER_MUX;
+
+#ifndef AMI_OVERRIDE_FOR_ULT_FASTBOOT
+  if (CpuFamilyId == EnumCpuHswUlt) return;
+#endif // AMI_OVERRIDE_FOR_ULT_FASTBOOT
+
+  if ((CpuFamilyId == EnumCpuHsw) && (CpuSteppingId == EnumHswA0)) {
+    SendVcuApiCmd (MchBar, V_SA_VCU_OPCODE_OPEN_SEQ_REV1, SequenceId);
+  } else {
+    SendVcuApiCmd (MchBar, V_SA_VCU_OPCODE_OPEN_SEQ_REV2, SequenceId);
+  }
+
+  SendVcuApiCmd (MchBar, V_SA_VCU_OPCODE_SET_TXJITTER_MUX, Lane);
+
+  if ((CpuFamilyId == EnumCpuHsw) && (CpuSteppingId == EnumHswA0)) {
+    SendVcuApiCmd (MchBar, V_SA_VCU_OPCODE_CLOSE_SEQ_REV1, 0);
+  } else {
+    SendVcuApiCmd (MchBar, V_SA_VCU_OPCODE_CLOSE_SEQ_REV2, 0);
+  }
+
+  return;
+}
+
+EFI_STATUS
+GetBundleList (
+  IN  UINT8 *LaneList,
+  IN  UINT8 LaneListLength,
+  OUT UINT8 *BundleList,
+  OUT UINT8 *BundleListLength
+  )
+{
+  UINT8   Bundle;
+  BOOLEAN HasBundle;
+  UINT8   i;
+  UINT8   j;
+
+  (*BundleListLength) = 0;
+
+  for (i = 0; i < LaneListLength; ++i) {
+    Bundle = LaneList[i] / 2;
+
+    HasBundle = FALSE;
+    for (j = 0; j < (*BundleListLength); ++j) {
+      if (BundleList[j] == Bundle) {
+          HasBundle = TRUE;
+          break;
+      }
+    }
+
+    if (!HasBundle) {
+      BundleList[*BundleListLength] = Bundle;
+      ++(*BundleListLength);
+    }
+  }
+
+  return EFI_SUCCESS;
+}
+
+#endif // PEG_FLAG
diff --git a/ReferenceCode/Chipset/SystemAgent/SaInit/Pei/PcieTrainingPhase3.c b/ReferenceCode/Chipset/SystemAgent/SaInit/Pei/PcieTrainingPhase3.c
new file mode 100644
index 0000000..6123968
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/SaInit/Pei/PcieTrainingPhase3.c
@@ -0,0 +1,657 @@
+/** @file
+  This driver trains the PEG interface.
+
+@copyright
+  Copyright (c) 2012 - 2014 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement
+**/
+
+#include "PcieTraining.h"
+
+#ifdef PEG_FLAG
+
+#include EFI_PPI_DEFINITION (PchMeUma)
+#include "PchMeUma.h"
+
+typedef struct _MARGIN_DATA {
+  UINT8 Preset;
+  INT32 TimingMargin[SA_PEG_MAX_LANE];
+} MARGIN_DATA;
+
+UINT8
+SelectBestPresetForLane (
+  IN  PORT_INFO               *PortInfo,
+  IN  UINT8                   Lane,
+  IN  SA_PLATFORM_POLICY_PPI  *SaPlatformPolicyPpi,
+  IN  SA_DATA_HOB             *SaDataHob,
+  IN  UINT8                   TrainingPreset
+  )
+{
+  UINT8   BestPreset;
+
+  ///
+  /// Init to EV default
+  ///
+  BestPreset = 7;
+
+  ///
+  /// EnableMargin    FoundUsablePreset    SaDataHob
+  ///            Y                    Y        !NULL  -> Use training results; update SaDataHob
+  ///            Y                    Y         NULL  -> Use training results
+  ///            Y                    N        !NULL  -> Use Policy value; update SaDataHob
+  ///            X                    N         NULL  -> Use Policy value
+  ///            N                    X        !NULL  -> Restore from SaDataHob
+  ///
+  if (Lane < SA_PEG_MAX_LANE) {
+    DEBUG ((EFI_D_INFO, "Preset for Lane %2d: ", Lane));
+    if ((PortInfo->EnableMargin) && (PortInfo->FoundUsablePreset)) {
+      ///
+      /// Use the best preset found during training
+      ///
+      BestPreset = TrainingPreset;
+      DEBUG ((EFI_D_INFO, "Search Result: P%d", BestPreset));
+      if (SaDataHob != NULL) {
+        DEBUG ((EFI_D_INFO, ". Saving value for next boot."));
+        SaDataHob->PegData.BestPreset[Lane] = BestPreset;
+      }
+    } else if ((PortInfo->EnableMargin) && (!PortInfo->FoundUsablePreset) && (SaDataHob != NULL)) {
+      ///
+      /// Use the policy value; update SaDataHob
+      ///
+      BestPreset = (UINT8) SaPlatformPolicyPpi->PcieConfig->Gen3EndPointPreset[Lane];
+      DEBUG ((EFI_D_INFO, "Applying Policy value: P%d. Saving value for next boot.", BestPreset));
+      SaDataHob->PegData.BestPreset[Lane] = BestPreset;
+    } else if ((!PortInfo->FoundUsablePreset) && (SaDataHob == NULL)) {
+      ///
+      /// Use the policy value
+      ///
+      BestPreset = (UINT8) SaPlatformPolicyPpi->PcieConfig->Gen3EndPointPreset[Lane];
+      DEBUG ((EFI_D_INFO, "Applying Policy value: P%d", BestPreset));
+    } else if ((!PortInfo->EnableMargin) && (SaDataHob != NULL)) {
+      ///
+      /// Use the preset found on a previous boot
+      ///
+      BestPreset = (UINT8) SaDataHob->PegData.BestPreset[Lane];
+      DEBUG ((EFI_D_INFO, "Restoring previous value: P%d", BestPreset));
+    }
+    DEBUG ((EFI_D_INFO, "\n"));
+  } else {
+    ///
+    /// Error: Non-existent lane
+    ///
+    DEBUG ((EFI_D_ERROR, "Illegal Lane: %d", Lane));
+  }
+
+  return BestPreset;
+}
+
+VOID
+PegGen3PresetSearch (
+  IN EFI_PEI_SERVICES       **PeiServices,
+  IN SA_PLATFORM_POLICY_PPI *SaPlatformPolicyPpi,
+  IN PEI_STALL_PPI          *StallPpi,
+  SA_DATA_HOB               *SaDataHob
+  )
+{
+  UINT8                 Index;
+  INT32                 MarginScore;
+  UINT8                 PegBus;
+  UINT8                 PegDev;
+  UINT8                 PegFunc;
+  UINT16                LinkStatus;
+  BOOLEAN               LoadedSavedPreset;
+  BOOLEAN               EndpointDeviceChanged;
+  UINT8                 TempIndex;
+  BOOLEAN               SkipBundle0;
+  CPU_FAMILY            CpuFamilyId;
+  CPU_STEPPING          CpuSteppingId;
+  MARGIN_DATA           MarginData[MAX_PRESETS];
+  PORT_INFO             PortInfoList[SA_PEG_MAX_FUN];
+  INT32                 LaneScores[SA_PEG_MAX_LANE];
+  INT32                 BestScores[SA_PEG_MAX_LANE];
+  UINT8                 BestPresets[SA_PEG_MAX_LANE];
+  EFI_STATUS            Status;
+  UINT32                MonitorPort;
+  UINT8                 PortInfoListLength;
+  UINT8                 PortIndex;
+  UINT8                 Lane;
+  BOOLEAN               AnyGen3CapableLinks;
+  BOOLEAN               AnyMarginingNeeded;
+  UINT8                 PreCursor;
+  UINT8                 Cursor;
+  UINT8                 PostCursor;
+  UINT8                 FullSwing;
+  UINT32                NominalRecoveryCount;
+  UINT8                 FirstSkippedLane;
+  UINT8                 LastSkippedLane;
+  UINT32                Data32;
+  BOOLEAN               SlotResetNeeded;
+  PCH_ME_UMA_PPI        *PchMeUmaPpi;
+  UINT8                 DetectedReplacedCpu;
+
+  AnyMarginingNeeded = FALSE;
+  CpuFamilyId        = GetCpuFamily();
+  CpuSteppingId      = GetCpuStepping();
+
+  ///
+  /// Setup default presets to search
+  ///
+  MarginData[0].Preset = 7;
+  MarginData[1].Preset = 3;
+  MarginData[2].Preset = 5;
+
+  ///
+  /// Initialize Arrays
+  ///
+  for (Lane = 0; Lane < SA_PEG_MAX_LANE; Lane++) {
+    LaneScores[Lane]  = -1;
+    BestScores[Lane]  = -1;
+    BestPresets[Lane] = MarginData[0].Preset;
+  }
+
+  DEBUG ((EFI_D_INFO, "PEG Gen3 Preset Search\n"));
+
+  if (!SaPolicyEnablesGen3 (SaPlatformPolicyPpi)) {
+    DEBUG ((EFI_D_INFO, " Gen3 is disabled by policy\n"));
+    return;
+  }
+  if ((CpuFamilyId == EnumCpuHsw) && (CpuSteppingId < EnumHswB0)) {
+    DEBUG ((EFI_D_WARN, " Gen3 preset search is not supported on this stepping\n"));
+    return;
+  }
+  Data32 = (McD1PciCfg32 (R_SA_PEG_PEGTST_OFFSET) & BIT20) >> 20;
+  if (Data32 != 0) {
+    DEBUG ((EFI_D_WARN, " Gen3 preset search does not support lane reversal\n"));
+    return;
+  }
+
+  ///
+  /// If ME is supported and the CPU has been replaced, redo the Preset Search.
+  /// Note that calling CpuReplacementCheck() can induce an ME-required warm reset.
+  ///
+  DetectedReplacedCpu = 0;
+  Status              = EFI_SUCCESS;
+
+  if ((SaDataHob != NULL) && (SaDataHob->PegDataValid)) {
+    Status = (*PeiServices)->LocatePpi (PeiServices, &gPchMeUmaPpiGuid, 0, NULL, &PchMeUmaPpi);
+    ASSERT_EFI_ERROR (Status);
+    DEBUG ((EFI_D_INFO, "Calling CpuReplacementCheck\n"));
+    Status = PchMeUmaPpi->CpuReplacementCheck (PeiServices, NULL, &DetectedReplacedCpu);
+    ASSERT_EFI_ERROR (Status);
+    DEBUG ((EFI_D_INFO, " ME reported CPU Replacement value: %x\n", DetectedReplacedCpu));
+  }
+
+  ///
+  /// Get the furcation setup and port information
+  ///
+  GetPortInfo (&(PortInfoList[0]), &PortInfoListLength, &SkipBundle0);
+
+  ///
+  /// Make sure we at Gen3 before starting, if not attempt reset and see if that helps
+  ///
+  SlotResetNeeded = FALSE;
+  for (PortIndex = 0; PortIndex < PortInfoListLength; PortIndex++) {
+    PegBus  = (PortInfoList[PortIndex]).PegPort.Bus;
+    PegDev  = (PortInfoList[PortIndex]).PegPort.Device;
+    PegFunc = (PortInfoList[PortIndex]).PegPort.Function;
+    LinkStatus = MmPci16 (0, PegBus, PegDev, PegFunc, R_SA_PEG_LSTS_OFFSET);
+    if (((LinkStatus & 0x0F) != 3) && ((PortInfoList[PortIndex]).LinkIsGen3Capable)) {
+      SlotResetNeeded = TRUE;
+      break;
+    }
+  }
+  if (SlotResetNeeded) {
+    ///
+    /// Bypass phase2 and assert slot reset
+    ///
+    McD1PciCfg32Or (R_SA_PEG_EQCFG_OFFSET, BIT15);
+    Status = TogglePegSlotReset (PeiServices, StallPpi, SaPlatformPolicyPpi);
+    if (!EFI_ERROR (Status)) {
+      for (PortIndex = 0; PortIndex < PortInfoListLength; PortIndex++) {
+        PegBus  = (PortInfoList[PortIndex]).PegPort.Bus;
+        PegDev  = (PortInfoList[PortIndex]).PegPort.Device;
+        PegFunc = (PortInfoList[PortIndex]).PegPort.Function;
+        ///
+        /// Wait for Equalization Done
+        ///
+        while (((MmPci32 (0, PegBus, PegDev, PegFunc, R_SA_PEG_LSTS2_OFFSET) >> 1) & 0x1) != 0x1);
+        ///
+        /// Wait for flow control credits exchange
+        ///
+        WaitForVc0Negotiation (PeiServices, StallPpi, PegBus, PegDev, PegFunc);
+      }
+    }
+  }
+
+  ///
+  /// Determine which PEG ports require testing
+  ///
+  AnyGen3CapableLinks = FALSE;
+  for (PortIndex = 0; PortIndex < PortInfoListLength; PortIndex++) {
+    PegBus  = (PortInfoList[PortIndex]).PegPort.Bus;
+    PegDev  = (PortInfoList[PortIndex]).PegPort.Device;
+    PegFunc = (PortInfoList[PortIndex]).PegPort.Function;
+
+    ///
+    /// If we already have Best Preset value from previous boot, use it and skip PresetSearch when end point device no change
+    ///
+    LoadedSavedPreset     = FALSE;
+    EndpointDeviceChanged = TRUE;
+    if (SaDataHob != NULL) {
+      if (SaDataHob->PegDataValid) {
+        LoadedSavedPreset = TRUE;
+        if (SaDataHob->PegData.EndPointVendorIdDeviceId[PegFunc] == (PortInfoList[PortIndex]).EndPointVendorIdDeviceId) {
+          EndpointDeviceChanged = FALSE;
+        }
+      }
+      if (EndpointDeviceChanged) {
+        ///
+        /// Save new device ID vendor ID
+        ///
+        SaDataHob->PegData.EndPointVendorIdDeviceId[PegFunc] = (PortInfoList[PortIndex]).EndPointVendorIdDeviceId;
+      }
+    }
+    DEBUG ((EFI_D_INFO, " PEG%x%x (%x:%x:%x) - LoadedSavedPreset = %d. EndpointDeviceChanged = %d.\n",
+      PegDev, PegFunc, PegBus, PegDev, PegFunc, LoadedSavedPreset, EndpointDeviceChanged));
+
+    ReportPcieLinkStatus (PegBus, PegDev, PegFunc);
+
+    if ( (!LoadedSavedPreset)         ||
+         (EndpointDeviceChanged)      ||
+         (DetectedReplacedCpu   != 0) ||
+         ((SaPlatformPolicyPpi->Revision >= SA_PLATFORM_POLICY_PPI_REVISION_2) &&
+          (SaPlatformPolicyPpi->PcieConfig->PegGen3ForcePresetSearch == 1    ))) {
+      (PortInfoList[PortIndex]).EnableMargin = TRUE;
+    } else {
+      (PortInfoList[PortIndex]).EnableMargin = FALSE;
+    }
+
+    if (!(PortInfoList[PortIndex]).LinkIsGen3Capable) {
+      (PortInfoList[PortIndex]).EnableMargin = FALSE;
+    } else {
+      AnyGen3CapableLinks = TRUE;
+    }
+  } ///< PegFunc Loop end
+
+  if (!AnyGen3CapableLinks) {
+    DEBUG ((EFI_D_INFO, "Skipping Preset Search - No Gen3 capable links\n"));
+    return;
+  }
+
+  ///
+  /// Determine if any ports need to be trained.
+  /// If any ports are trained, the corresponding endpoint should also be reset with PERST#.
+  ///
+  for (PortIndex = 0; PortIndex < PortInfoListLength; PortIndex++) {
+    if ((PortInfoList[PortIndex]).EnableMargin == TRUE) {
+      AnyMarginingNeeded = TRUE;
+      break;
+    }
+  }
+
+  if (AnyMarginingNeeded) {
+    MonitorPort = OpenMonitor (PeiServices, SaPlatformPolicyPpi, StallPpi);
+
+    McD1PciCfg32Or (R_SA_PEG_REUT_PH_CTR_OFFSET, B_SA_PEG_REUT_PH_CTR_AUTOCOMP_MASK);
+
+    ///
+    /// Presets Loop start
+    ///
+    for (Index = 0; Index < MAX_PRESETS; Index++) {
+      ///
+      /// Clear out old values
+      ///
+      for (TempIndex = 0; TempIndex < SA_PEG_MAX_LANE; TempIndex++) {
+        MarginData[Index].TimingMargin[TempIndex]      = 0;
+      } ///< End of for each Lane
+
+
+      for (PortIndex = 0; PortIndex < PortInfoListLength; PortIndex++) {
+        (PortInfoList[PortIndex]).SkipMargin = FALSE;
+        PegBus  = (PortInfoList[PortIndex]).PegPort.Bus;
+        PegDev  = (PortInfoList[PortIndex]).PegPort.Device;
+        PegFunc = (PortInfoList[PortIndex]).PegPort.Function;
+
+        if (!(PortInfoList[PortIndex]).LinkIsGen3Capable) {
+          DEBUG ((EFI_D_INFO, "Skipping PEG%d%d - Not Gen3 capable\n", PegDev, PegFunc));
+          continue;
+        }
+
+        ///
+        /// Find first lane of the port for coefficient programming
+        ///
+        switch (PegFunc) {
+          default:
+          case 0:
+            Lane             = 0;
+            FirstSkippedLane = 0;
+            LastSkippedLane  = 1;
+            break;
+          case 1:
+            Lane             = 8;
+            FirstSkippedLane = 8;
+            LastSkippedLane  = 9;
+            break;
+          case 2:
+            Lane             = 12;
+            FirstSkippedLane = 12;
+            LastSkippedLane  = 13;
+            break;
+        }
+
+        ///
+        /// Get FullSwing
+        ///
+        GetLinkPartnerFullSwing (Lane, &FullSwing);
+
+        ///
+        /// Get Coefficients
+        ///
+        GetCoefficientsFromPreset (MarginData[Index].Preset, FullSwing, &PreCursor, &Cursor, &PostCursor);
+
+        ///
+        /// Set Lane's Coefficients
+        ///
+        if (SkipBundle0) {
+          for (TempIndex = FirstSkippedLane; TempIndex <= LastSkippedLane; TempIndex++) {
+            SetPartnerTxCoefficients (TempIndex, &PreCursor, &Cursor, &PostCursor);
+            ProgramPreset (1, MarginData[Index].Preset, PegFunc, TempIndex);
+          }
+        }
+        for (TempIndex = 0; TempIndex < (PortInfoList[PortIndex]).LaneListLength; TempIndex++) {
+          SetPartnerTxCoefficients ((PortInfoList[PortIndex]).LaneList[TempIndex], &PreCursor, &Cursor, &PostCursor);
+          ProgramPreset (1, MarginData[Index].Preset, PegFunc, (PortInfoList[PortIndex]).LaneList[TempIndex]);
+        }
+
+        ///
+        /// Set DOEQ bit
+        ///
+        MmPci32Or (0, PegBus, PegDev, PegFunc, R_SA_PEG_LCTL3_OFFSET, BIT0);
+        RetrainLink (PeiServices, StallPpi, &((PortInfoList[PortIndex]).PegPort));
+
+        ///
+        /// Get the current link status
+        ///
+        LinkStatus = MmPci16 (0, PegBus, PegDev, PegFunc, R_SA_PEG_LSTS_OFFSET);
+        ///
+        /// No need to margin if couldn't get to Gen3 with this preset
+        ///
+        if ((LinkStatus & 0x0F) != 3) {
+          RecoverLinkFailure (PeiServices, SaPlatformPolicyPpi, SaDataHob, StallPpi,
+                              &((PortInfoList[PortIndex]).PegPort), 3,
+                              GetNegotiatedWidth (&((PortInfoList[PortIndex]).PegPort)));
+          LinkStatus = MmPci16 (0, PegBus, PegDev, PegFunc, R_SA_PEG_LSTS_OFFSET);
+          if ((LinkStatus & 0x0F) != 3) {
+            (PortInfoList[PortIndex]).SkipMargin = TRUE;
+            continue;
+          }
+        }
+
+        NominalRecoveryCount = SaPcieGetErrorCount (MonitorPort, PegFunc);
+        StallPpi->Stall (PeiServices, StallPpi, SaPlatformPolicyPpi->PcieConfig->PegGen3PresetSearchDwellTime * STALL_ONE_MICRO_SECOND);
+        NominalRecoveryCount = SaPcieGetErrorCount (MonitorPort, PegFunc) - NominalRecoveryCount;
+        if (NominalRecoveryCount > 0) {
+          (PortInfoList[PortIndex]).SkipMargin = TRUE;
+          continue;
+        }
+        (PortInfoList[PortIndex]).FoundUsablePreset = TRUE;
+      } ///< End of for each Port
+
+      Status = RunMarginTest (
+                 PeiServices,
+                 SaPlatformPolicyPpi,
+                 SaDataHob,
+                 StallPpi,
+                 MonitorPort,
+                 &(PortInfoList[0]),
+                 PortInfoListLength,
+                 LaneLevelRxJitter,
+                 MarginData[Index].TimingMargin
+                 );
+
+      if (EFI_ERROR (Status)) {
+        for (TempIndex = 0; TempIndex < SA_PEG_MAX_LANE; TempIndex++) {
+          MarginData[Index].TimingMargin[TempIndex] = 0;
+        }
+      }
+    } ///< Presets Loop end
+
+    McD1PciCfg32And (R_SA_PEG_REUT_PH_CTR_OFFSET, ~B_SA_PEG_REUT_PH_CTR_AUTOCOMP_MASK);
+    CloseMonitor (SaPlatformPolicyPpi, MonitorPort);
+
+    ///
+    /// Find the preset with the maximum margin (largest of all margin values)
+    ///
+    for (Index = 0; Index < sizeof (MarginData) / sizeof (MarginData[0]); Index++) {
+      for (Lane = 0; Lane < SA_PEG_MAX_LANE; Lane++) {
+        LaneScores[Lane] = -1;
+      }
+      for (Lane = 0; Lane < SA_PEG_MAX_LANE; Lane++) {
+        if (MarginData[Index].TimingMargin[Lane] != -1) {
+          MarginScore = MarginData[Index].TimingMargin[Lane];
+          LaneScores[Lane] = MarginScore;
+        }
+        if (LaneScores[Lane] > BestScores[Lane]) {
+          BestScores[Lane]  = LaneScores[Lane];
+          BestPresets[Lane] = MarginData[Index].Preset;
+        }
+      } ///< End of for each Lane
+    } ///< End of for each Preset
+
+    ///
+    /// If Lanes 0-1 were skipped, copy the values from Lane 2
+    ///
+    if (SkipBundle0) {
+      for (PortIndex = 0; PortIndex < PortInfoListLength; PortIndex++) {
+        PegFunc = (PortInfoList[PortIndex]).PegPort.Function;
+        switch (PegFunc) {
+          default:
+          case 0:
+            Lane             = 2;
+            FirstSkippedLane = 0;
+            LastSkippedLane  = 1;
+            break;
+          case 1:
+            Lane             = 10;
+            FirstSkippedLane = 8;
+            LastSkippedLane  = 9;
+            break;
+          case 2:
+            Lane             = 14;
+            FirstSkippedLane = 12;
+            LastSkippedLane  = 13;
+            break;
+        }
+        if (BestScores[Lane] != -1) {
+          DEBUG ((EFI_D_INFO, "Using Lane %2d's Best Preset for Lanes %2d-%2d.\n", Lane, FirstSkippedLane, LastSkippedLane));
+          for (TempIndex = FirstSkippedLane; TempIndex <= LastSkippedLane; TempIndex++) {
+            BestScores[TempIndex]  = BestScores[Lane];
+            BestPresets[TempIndex] = BestPresets[Lane];
+          }
+        }
+      } ///< End of for each port
+    } ///< End of SkipBundle0
+  } ///< End of AnyMarginingNeeded
+
+  for (PortIndex = 0; PortIndex < PortInfoListLength; PortIndex++) {
+    PegBus  = (PortInfoList[PortIndex]).PegPort.Bus;
+    PegDev  = (PortInfoList[PortIndex]).PegPort.Device;
+    PegFunc = (PortInfoList[PortIndex]).PegPort.Function;
+    if (!(PortInfoList[PortIndex]).LinkIsGen3Capable) {
+      continue;
+    }
+    if (SkipBundle0) {
+      switch (PegFunc) {
+        default:
+        case 0:
+          FirstSkippedLane = 0;
+          LastSkippedLane  = 1;
+          break;
+        case 1:
+          FirstSkippedLane = 8;
+          LastSkippedLane  = 9;
+          break;
+        case 2:
+          FirstSkippedLane = 12;
+          LastSkippedLane  = 13;
+          break;
+      }
+      for (TempIndex = FirstSkippedLane; TempIndex <= LastSkippedLane; TempIndex++) {
+        BestPresets[TempIndex] = SelectBestPresetForLane (
+                                   &(PortInfoList[PortIndex]),
+                                   TempIndex,
+                                   SaPlatformPolicyPpi,
+                                   SaDataHob,
+                                   BestPresets[TempIndex]
+                                   );
+      }
+    }
+    for (TempIndex = 0; TempIndex < (PortInfoList[PortIndex]).LaneListLength; TempIndex++) {
+      BestPresets[(PortInfoList[PortIndex]).LaneList[TempIndex]] = SelectBestPresetForLane (
+                                                                     &(PortInfoList[PortIndex]),
+                                                                     (PortInfoList[PortIndex]).LaneList[TempIndex],
+                                                                     SaPlatformPolicyPpi,
+                                                                     SaDataHob,
+                                                                     BestPresets[(PortInfoList[PortIndex]).LaneList[TempIndex]]
+                                                                     );
+    }
+  }
+
+  ///
+  /// Program the presets.  If any link was margined, also reset the
+  /// endpoints in order to return the endpoints to a known-good state.
+  ///
+  if (AnyMarginingNeeded) {
+    for (TempIndex = 0; TempIndex < SA_PEG_MAX_FUN; TempIndex++) {
+      MmPci16Or (0, SA_PEG_BUS_NUM, SA_PEG_DEV_NUM, TempIndex, R_SA_PEG_LCTL_OFFSET, BIT4);
+    }
+    AssertPegSlotReset (SaPlatformPolicyPpi);
+  }
+  for (PortIndex = 0; PortIndex < PortInfoListLength; PortIndex++) {
+    PegBus  = (PortInfoList[PortIndex]).PegPort.Bus;
+    PegDev  = (PortInfoList[PortIndex]).PegPort.Device;
+    PegFunc = (PortInfoList[PortIndex]).PegPort.Function;
+    if (!(PortInfoList[PortIndex]).LinkIsGen3Capable) {
+      DEBUG ((EFI_D_INFO, "PEG%d%d - Not Gen3 capable, skip coefficient programming.\n", PegDev, PegFunc));
+      continue;
+    }
+    ///
+    /// Find first lane of the port for coefficient programming
+    ///
+    switch (PegFunc) {
+      default:
+      case 0:
+        Lane             = 0;
+        FirstSkippedLane = 0;
+        LastSkippedLane  = 1;
+        break;
+      case 1:
+        Lane             = 8;
+        FirstSkippedLane = 8;
+        LastSkippedLane  = 9;
+        break;
+      case 2:
+        Lane             = 12;
+        FirstSkippedLane = 12;
+        LastSkippedLane  = 13;
+        break;
+    }
+    ///
+    /// Get FullSwing
+    ///
+    GetLinkPartnerFullSwing (Lane, &FullSwing);
+
+    if (SkipBundle0) {
+      for (TempIndex = FirstSkippedLane; TempIndex <= LastSkippedLane; TempIndex++) {
+        GetCoefficientsFromPreset (BestPresets[TempIndex], FullSwing, &PreCursor, &Cursor, &PostCursor);
+        SetPartnerTxCoefficients (TempIndex, &PreCursor, &Cursor, &PostCursor);
+        ProgramPreset (1, BestPresets[TempIndex], PegFunc, TempIndex);
+      }
+    }
+    for (TempIndex = 0; TempIndex < (PortInfoList[PortIndex]).LaneListLength; TempIndex++) {
+      ///
+      /// Get Coefficients
+      ///
+      GetCoefficientsFromPreset (BestPresets[((PortInfoList[PortIndex]).LaneList[TempIndex])], FullSwing, &PreCursor, &Cursor, &PostCursor);
+
+      ///
+      /// Set Lane's Coefficients
+      ///
+      SetPartnerTxCoefficients ((PortInfoList[PortIndex]).LaneList[TempIndex], &PreCursor, &Cursor, &PostCursor);
+
+      ///
+      /// Set Phase 1 Presets
+      ///
+      ProgramPreset (1, BestPresets[((PortInfoList[PortIndex]).LaneList[TempIndex])], PegFunc, (PortInfoList[PortIndex]).LaneList[TempIndex]);
+    }
+
+    MmPci32Or (0, PegBus, PegDev, PegFunc, R_SA_PEG_LCTL3_OFFSET, BIT0);   ///< DOEQ
+    MmPci16Or (0, PegBus, PegDev, PegFunc, R_SA_PEG_LCTL_OFFSET,  BIT5);   ///< Retrain link
+  }
+
+  if (AnyMarginingNeeded) {
+    StallPpi->Stall (PeiServices, StallPpi, 100 * STALL_ONE_MICRO_SECOND);
+    for (TempIndex = 0; TempIndex < SA_PEG_MAX_FUN; TempIndex++) {
+      MmPci16And (0, SA_PEG_BUS_NUM, SA_PEG_DEV_NUM, TempIndex, R_SA_PEG_LCTL_OFFSET, (UINT16) ~(BIT4));
+    }
+    DeassertPegSlotReset (SaPlatformPolicyPpi);
+  }
+
+  for (PortIndex = 0; PortIndex < PortInfoListLength; PortIndex++) {
+    PegBus  = (PortInfoList[PortIndex]).PegPort.Bus;
+    PegDev  = (PortInfoList[PortIndex]).PegPort.Device;
+    PegFunc = (PortInfoList[PortIndex]).PegPort.Function;
+    WaitForL0 (PeiServices, StallPpi, &(PortInfoList[PortIndex].PegPort), FALSE);
+    ReportPcieLinkStatus (PegBus, PegDev, PegFunc);
+  }
+
+  DEBUG ((EFI_D_INFO, "PEG Gen3 Preset Search done\n\n"));
+
+  return;
+}
+
+BOOLEAN
+SaPolicyEnablesGen3 (
+  IN SA_PLATFORM_POLICY_PPI *SaPlatformPolicyPpi
+  )
+{
+  UINTN   PegPortGenx;
+  BOOLEAN Gen3Enabled;
+  UINT8   Index;
+
+  Gen3Enabled = FALSE;
+
+  ///
+  /// Check if Gen3 is enabled on PEG10/11/12
+  ///
+  for (Index = 0; Index < SA_PEG_MAX_FUN; Index++) {
+    ///
+    /// PegPortGenx: 0 = Auto, 1 = Gen1, 2 = Gen2, 3 = Gen3
+    ///
+    PegPortGenx = SaPlatformPolicyPpi->PcieConfig->PegGenx[Index];
+
+    ///
+    /// Check if the root port is present and the speed is not limited to Gen1/Gen2
+    ///
+    if ((PegPortGenx == PEG_AUTO) || (PegPortGenx == PEG_GEN3)) {
+      Gen3Enabled = TRUE;
+      break;
+    }
+  }
+  return Gen3Enabled;
+}
+
+#endif // PEG_FLAG
diff --git a/ReferenceCode/Chipset/SystemAgent/SaInit/Pei/SaDmiPeim.c b/ReferenceCode/Chipset/SystemAgent/SaInit/Pei/SaDmiPeim.c
new file mode 100644
index 0000000..ea817d8
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/SaInit/Pei/SaDmiPeim.c
@@ -0,0 +1,450 @@
+/** @file
+  SA Dmi PEI Initialization library
+
+@copyright
+  Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement
+
+**/
+#include "SaDmiPeim.h"
+#include "PciExpressInit.h"
+
+///
+/// Functions
+///
+/**
+  Initialize DMI Tc/Vc mapping through SA-PCH.
+
+  @param[in] PeiServices          - General purpose services available to every PEIM.
+  @param[in] SaPlatformPolicyPpi  - Instance of SA_PLATFORM_POLICY_PPI
+
+  @retval EFI_SUCCESS
+**/
+EFI_STATUS
+SaDmiTcVcInit (
+  IN EFI_PEI_SERVICES          **PeiServices,
+  IN SA_PLATFORM_POLICY_PPI    *SaPlatformPolicyPpi
+  )
+{
+  EFI_STATUS        Status;
+  UINT64            MchBar;
+  UINT64            DmiBar;
+  PCH_INIT_PPI      *PchInitPpi;
+  PCH_DMI_TC_VC_PPI *PchDmiTcVcMapPpi;
+  CPU_FAMILY        CpuFamilyId;
+  UINT8             i;
+
+  MchBar  = McD0PciCfg64 (R_SA_MCHBAR) &~BIT0;
+  DmiBar  = McD0PciCfg64 (R_SA_DMIBAR) &~BIT0;
+  CpuFamilyId = GetCpuFamily();
+
+  ///
+  /// Locate PchInitPpi and PchDmiTcVcMapPpi
+  ///
+  Status = (*PeiServices)->LocatePpi (PeiServices, &gPchInitPpiGuid, 0, NULL, (VOID **) &PchInitPpi);
+  ASSERT_EFI_ERROR (Status);
+
+  Status = (*PeiServices)->LocatePpi (PeiServices, &gPchDmiTcVcMapPpiGuid, 0, NULL, (VOID **) &PchDmiTcVcMapPpi);
+  ASSERT_EFI_ERROR (Status);
+
+  ///
+  /// SA OPI Initialization
+  ///
+  if (CpuFamilyId == EnumCpuHswUlt) {
+    MmioOr8 ((UINTN) (DmiBar + 0xA78), BIT1);
+  }
+
+  ///
+  /// Update DmiTcVcMapping based on Policy
+  ///
+  PchDmiTcVcMapPpi->DmiVc[DmiVcTypeVc1].Enable  = (BOOLEAN) SaPlatformPolicyPpi->PcieConfig->DmiVc1;
+  PchDmiTcVcMapPpi->DmiVc[DmiVcTypeVcp].Enable  = (BOOLEAN) SaPlatformPolicyPpi->PcieConfig->DmiVcp;
+  PchDmiTcVcMapPpi->DmiVc[DmiVcTypeVcm].Enable  = (BOOLEAN) SaPlatformPolicyPpi->PcieConfig->DmiVcm;
+
+  for (i = 0; i < DmiTcTypeMax; i++) {
+    if (((PchDmiTcVcMapPpi->DmiTc[i].Vc == DmiVcTypeVc1) && (PchDmiTcVcMapPpi->DmiVc[DmiVcTypeVc1].Enable == FALSE)) ||
+        ((PchDmiTcVcMapPpi->DmiTc[i].Vc == DmiVcTypeVcp) && (PchDmiTcVcMapPpi->DmiVc[DmiVcTypeVcp].Enable == FALSE)) ||
+        ((PchDmiTcVcMapPpi->DmiTc[i].Vc == DmiVcTypeVcm) && (PchDmiTcVcMapPpi->DmiVc[DmiVcTypeVcm].Enable == FALSE))
+        ) {
+      PchDmiTcVcMapPpi->DmiTc[i].Vc = DmiVcTypeVc0;
+    }
+  }
+  ///
+  /// Program NB TC/VC mapping
+  ///
+  SaSetDmiTcVcMapping (PchDmiTcVcMapPpi, DmiBar);
+
+  ///
+  /// Call PchDmiTcVcProgPoll
+  ///
+  Status = PchInitPpi->DmiTcVcProgPoll (PeiServices);
+  ASSERT_EFI_ERROR (Status);
+
+  ///
+  /// Poll NB negotiation completion
+  ///
+  SaPollDmiVcStatus (PchDmiTcVcMapPpi, DmiBar);
+  ASSERT_EFI_ERROR (Status);
+
+  return EFI_SUCCESS;
+
+}
+
+/**
+  Map SA DMI TCs to VC
+
+  @param[in] PchDmiTcVcMapPpi     - Instance of PCH_DMI_TC_VC_PPI
+  @param[in] DmiBar               - DMIBAR address
+
+  @retval EFI_SUCCESS            -  Succeed.
+  @retval EFI_INVALID_PARAMETER  -  Wrong phase parameter passed in.
+**/
+EFI_STATUS
+SaSetDmiTcVcMapping (
+  IN    PCH_DMI_TC_VC_PPI   *PchDmiTcVcMapPpi,
+  IN    UINT64              DmiBar
+  )
+{
+  UINT32  Data32And;
+  UINT32  Data32Or;
+  UINT8   Data8And;
+  UINT8   Data8Or;
+  UINT8   Index;
+  UINT16  Register;
+  UINT8   VcId;
+  UINT8   VcMap[DmiVcTypeMax] = { 0 };
+
+  ///
+  /// Set the TC/VC mappings
+  ///
+  for (Index = 0; Index < DmiTcTypeMax; Index++) {
+    VcMap[PchDmiTcVcMapPpi->DmiTc[Index].Vc] |= (BIT0 << Index);
+  }
+  ///
+  /// System BIOS must perform the following steps for VC0 configuration.
+  ///   Program the TCs/VC0 map by setting DMIBAR offset 014h [7:1] = '0111 101b'.
+  ///
+  /// Private Virtual Channel Configuration
+  /// Step1. Assign Virtual Channel ID 2 to VCp:
+  ///    Programming the DMIVCPRCTL DMI Port Register DMIBAR Offset 02Ch[26:24] = '010b'.
+  ///
+  /// Step2. Set TC2 to VCp:
+  ///    Program the DMIVCPRCTL DMI Port Register DMIBAR offset 02Ch [7:1] = '0000 010b'.
+  ///
+  /// Step3. Enable VCp by programming the DMIVCPRCTL DMI Port Register DMIBAR Offset 02Ch[31] = '1b'.
+  ///
+  /// Virtual Channel for ME (VCm) Configuration
+  /// This is configured by ConfigMemMe
+  ///
+  /// Step1. Assign Virtual Channel ID 7 to VCm:
+  ///    Programming the DMIVCMRCTL DMI Port Register DMIBAR Offset 038h[26:24] = '111b'.
+  ///
+  /// Step2. Enable VCm:
+  ///    Programming the DMIVMPRCTL DMI Port Register DMIBAR Offset 038h[31] = '1b'.
+  ///
+  /// Step3. Enable VCm by programming the DMIVCMRCTL DMI Port Register DMIBAR Offset 038h[31] = '1b'.
+  ///
+  for (Index = 0; Index < DmiVcTypeMax; Index++) {
+    if (PchDmiTcVcMapPpi->DmiVc[Index].Enable == PCH_DEVICE_ENABLE) {
+      ///
+      /// Map TCs to VC, Set the VC ID, Enable VC
+      ///
+      VcId = PchDmiTcVcMapPpi->DmiVc[Index].VcId,
+
+      Data32And = (UINT32) (~(V_SA_DMIBAR_DMIVCCTL_ID | B_SA_DMIBAR_DMIVCCTL_TVM_MASK));
+      Data32Or = VcId << N_SA_DMIBAR_DMIVCCTL_ID;
+      Data32Or |= VcMap[Index];
+      Data32Or |= N_SA_DMIBAR_DMIVCCTL_EN;
+
+      switch (Index) {
+      case DmiVcTypeVc0:
+        Register = R_SA_DMIBAR_DMIVC0RCTL_OFFSET;
+        break;
+
+      case DmiVcTypeVc1:
+        Register = R_SA_DMIBAR_DMIVC1RCTL_OFFSET;
+        break;
+
+      case DmiVcTypeVcp:
+        Register = R_SA_DMIBAR_DMIVCPRCTL_OFFSET;
+        break;
+
+      case DmiVcTypeVcm:
+        Register = R_SA_DMIBAR_DMIVCMRCTL_OFFSET;
+        break;
+
+      default:
+        return EFI_INVALID_PARAMETER;
+      }
+
+      MmioAndThenOr32 ((UINTN) (DmiBar + Register), Data32And, Data32Or);
+    }
+  }
+  ///
+  /// System BIOS must program the extended VC Count:
+  ///    Set the DMI Port Register DMIBAR Offset 004h[2:0]=001b
+  ///
+  Data8And = (UINT8) (~0x07);
+  if (PchDmiTcVcMapPpi->DmiVc[DmiVcTypeVc1].Enable == TRUE) {
+    Data8Or = 1;
+  } else {
+    Data8Or = 0;
+  }
+
+  MmioAndThenOr8 ((UINTN) (DmiBar + R_SA_DMIBAR_DMIPVCCAP1_OFFSET), Data8And, Data8Or);
+
+  return EFI_SUCCESS;
+}
+
+/**
+  Poll SA DMI negotiation completion
+
+  @param[in] PchDmiTcVcMapPpi     - Instance of PCH_DMI_TC_VC_PPI
+  @param[in] DmiBar               - DMIBAR address
+
+  @retval EFI_SUCCESS            -  Succeed.
+  @retval EFI_INVALID_PARAMETER  -  Wrong phase parameter passed in.
+**/
+EFI_STATUS
+SaPollDmiVcStatus (
+  IN    PCH_DMI_TC_VC_PPI   *PchDmiTcVcMapPpi,
+  IN    UINT64              DmiBar
+  )
+{
+  UINT8   Index;
+  UINT16  Register;
+
+  ///
+  /// 6.2.3.2 - Step 4, Poll until VC1 has been negotiated
+  ///    Read the DMIVC1RSTS DMI Port Register Offset 026h until [1]==0
+  ///
+  /// 6.2.3.3 - Step4. Poll the VCp Negotiation Pending bit until it reads 0:
+  ///    Read the DMIVCPRSTS DMI Port Register Offset 032h until [1]==0
+  ///
+  /// 6.2.3.4 - Step4. Poll the VCm Negotiation Pending bit until it reads 0:
+  ///    Read the DMIVCMRSTS DMI Port Register Offset 03Eh until [1]==0
+  ///
+  for (Index = 0; Index < DmiVcTypeMax; Index++) {
+    if (PchDmiTcVcMapPpi->DmiVc[Index].Enable == PCH_DEVICE_ENABLE) {
+      switch (Index) {
+      case DmiVcTypeVc0:
+        Register = R_SA_DMIBAR_DMIVC0RSTS_OFFSET;
+        break;
+
+      case DmiVcTypeVc1:
+        Register = R_SA_DMIBAR_DMIVC1RSTS_OFFSET;
+        break;
+
+      case DmiVcTypeVcp:
+        Register = R_SA_DMIBAR_DMIVCPRSTS_OFFSET;
+        break;
+
+      case DmiVcTypeVcm:
+        Register = R_SA_DMIBAR_DMIVCMRSTS_OFFSET;
+        break;
+
+      default:
+        return EFI_INVALID_PARAMETER;
+      }
+      ///
+      /// Wait for negotiation to complete
+      ///
+      while ((MmioRead16 ((UINTN) (DmiBar + Register)) & B_SA_DMIBAR_DMISTS_NP) != 0);
+    }
+  }
+
+  return EFI_SUCCESS;
+}
+
+#ifdef DMI_FLAG
+/**
+  Initialize DMI.
+
+  @param[in] PeiServices          - General purpose services available to every PEIM.
+  @param[in] SaPlatformPolicyPpi  - Instance of SA_PLATFORM_POLICY_PPI
+
+  @retval EFI_SUCCESS
+**/
+EFI_STATUS
+DmiInit (
+  IN EFI_PEI_SERVICES          **PeiServices,
+  IN SA_PLATFORM_POLICY_PPI    *SaPlatformPolicyPpi
+  )
+{
+  EFI_STATUS              Status;
+  UINT64                  MchBar;
+  UINT64                  DmiBar;
+  PCH_INIT_PPI            *PchInitPpi;
+  PCH_PLATFORM_POLICY_PPI *PchPlatformPolicyPpi;
+  UINT8                   CpuSteppingId;
+  BOOLEAN                 DmiGen2Enable;
+  UINT16                  LinkStatus;
+  UINT32                  Data32Or;
+
+  ///
+  /// Read the CPU stepping
+  ///
+  CpuSteppingId = GetCpuStepping();
+
+  ///
+  /// BridgeId = (UINT8) (McD0PciCfg16 (R_MC_DEVICE_ID) & 0xF0);
+  /// BridgeSteppingId = BridgeId + CpuSteppingId;
+  ///
+  MchBar  = McD0PciCfg64 (R_SA_MCHBAR) &~BIT0;
+  DmiBar  = McD0PciCfg64 (R_SA_DMIBAR) &~BIT0;
+
+  ///
+  /// Get RCBA through the PchPlatformPolicy PPI
+  ///
+  Status = (**PeiServices).LocatePpi (
+                            PeiServices,
+                            &gPchPlatformPolicyPpiGuid,
+                            0,
+                            NULL,
+                            &PchPlatformPolicyPpi
+                            );
+  ASSERT_EFI_ERROR (Status);
+
+  if (EFI_ERROR (Status)) {
+    DEBUG ((EFI_D_ERROR, "Can't locate PchPlatformPolicy PPI - exiting.\n"));
+    return Status;
+  }
+  ///
+  /// Perform DMI Recipe steps
+  ///
+  DEBUG ((EFI_D_INFO, "DMI Recipe...\n"));
+  PegDmiRecipe (SaPlatformPolicyPpi, (UINT32) MchBar, (UINT32) DmiBar, 0, 0);
+
+  ///
+  /// Additional DMI steps. See SA BIOS Spec.
+  ///
+  DEBUG ((EFI_D_INFO, "Run AdditionalDmiProgramSteps!\n"));
+  AdditionalDmiProgramSteps (SaPlatformPolicyPpi, (UINT32) MchBar, (UINT32) DmiBar);
+
+  DmiGen2Enable = TRUE;
+  if ((SaPlatformPolicyPpi->PcieConfig->DmiGen2 == 0) ||
+      ((MmioRead8 ((UINTN) PchPlatformPolicyPpi->Rcba + R_PCH_RCRB_LCAP) & (BIT0 | BIT1 | BIT2 | BIT3)) == 0x1) ||
+      (McDevFunPciCfg32 (0, 0, 0, R_SA_MC_CAPID0_A_OFFSET) & BIT22)
+     ) {
+    DEBUG ((EFI_D_WARN, "DMI Gen2 is Disabled or not capable, staying at Gen1 !\n"));
+    DmiGen2Enable = FALSE;
+  }
+
+  if (DmiGen2Enable) {
+    ///
+    /// Locate PchInitPpi
+    ///
+    Status = (*PeiServices)->LocatePpi (PeiServices, &gPchInitPpiGuid, 0, NULL, &PchInitPpi);
+    ASSERT_EFI_ERROR (Status);
+
+    ///
+    /// Program PCH TLS to Gen 2
+    ///
+    PchInitPpi->DmiGen2Prog (PeiServices);
+
+    ///
+    /// Program CPU Max Link Speed to Gen 2
+    ///
+    MmioAndThenOr32 ((UINTN) (DmiBar + R_SA_DMIBAR_LCAP_OFFSET), (UINT32)~0xF, 2);
+  }
+  Data32Or = (MmioRead32 ((UINTN) (DmiBar + R_SA_DMIBAR_LCAP_OFFSET)) & (BIT3 | BIT2 | BIT1 | BIT0));
+  MmioAndThenOr32 ((UINTN) (DmiBar + R_SA_DMIBAR_LCTL2_OFFSET), (UINT32)~(BIT3 | BIT2 | BIT1 | BIT0), Data32Or);
+
+  ///
+  /// Retrain link
+  ///
+  DmiLinkTrain (DmiBar);
+
+  ///
+  /// Retrain link if it is GEN2 Capable and it is not yet set to GEN2
+  ///
+  if (DmiGen2Enable &&
+      ((((MmioRead16 ((UINTN) (DmiBar + R_SA_DMIBAR_LSTS_OFFSET))) & 0x0F) != DMI_GEN2) ||
+       (((MmioRead16 ((UINTN) PchPlatformPolicyPpi->Rcba + R_PCH_RCRB_LSTS)) & 0x0F) != DMI_GEN2))
+     ) {
+    DEBUG ((EFI_D_INFO, "DMI Link re-train to set GEN2\n"));
+    DmiLinkTrain (DmiBar);
+  }
+  ///
+  /// Get the current link status
+  ///
+  LinkStatus = MmioRead16 ((UINTN) (DmiBar + R_SA_DMIBAR_LSTS_OFFSET));
+  DEBUG ((EFI_D_INFO, "DMI trained to x%d at Gen%d\n", (LinkStatus >> 4) & 0x3F, LinkStatus & 0x0F));
+
+  return EFI_SUCCESS;
+}
+
+/**
+  DMI link training
+
+  @param[in] DmiBar - DMIBAR address
+**/
+VOID
+DmiLinkTrain (
+  IN  UINT64 DmiBar
+  )
+{
+  ///
+  /// Retrain link
+  ///
+  MmioOr8 ((UINTN) (DmiBar + R_SA_DMIBAR_LCTL_OFFSET), BIT5);
+
+  ///
+  /// Wait for link training complete
+  ///
+  while ((MmioRead16 ((UINTN) (DmiBar + R_SA_DMIBAR_LSTS_OFFSET)) & BIT11) != 0)
+    ;
+}
+
+/**
+  Additional DMI Programming Steps at PEI
+
+  @param[in] SaPlatformPolicyPpi - pointer to SA_PLATFORM_POLICY_PPI
+  @param[in] MchBar              - MCHBAR address
+  @param[in] DmiBar              - DMIBAR address
+**/
+VOID
+AdditionalDmiProgramSteps (
+  IN SA_PLATFORM_POLICY_PPI    *SaPlatformPolicyPpi,
+  IN UINT32                    MchBar,
+  IN UINT32                    DmiBar
+  )
+{
+  UINT32  Data32And;
+  UINT32  Data32Or;
+
+  ///
+  /// Disable DMI and PEG Debug Align Message - set 0x258[29] = '1b'
+  ///
+  Data32And = (UINT32) ~BIT29;
+  Data32Or  = BIT29;
+  Mmio32AndThenOr (DmiBar, R_SA_DMIBAR_CFG4_OFFSET, Data32And, Data32Or);
+
+  ///
+  /// Overwrite DMICC (DMIBAR offset 0x208) to 0x6B5
+  ///
+  Data32And = (UINT32)~(BIT10 | BIT9 | BIT8 | BIT7 | BIT6 | BIT5 | BIT4 | BIT3 | BIT2 | BIT1 | BIT0);
+  Data32Or  = 0x6B5;
+  Mmio32AndThenOr (DmiBar, R_SA_DMIBAR_DMICC_OFFSET, Data32And, Data32Or);
+
+  ///
+  /// Set L0SLAT[15:0] to 0x2020
+  ///
+  Data32And = (UINT32) ~(0xFFFF);
+  Data32Or  = 0x00002020;
+  Mmio32AndThenOr (DmiBar, R_SA_DMIBAR_L0SLAT_OFFSET, Data32And, Data32Or);
+}
+#endif // DMI_FLAG
diff --git a/ReferenceCode/Chipset/SystemAgent/SaInit/Pei/SaDmiPeim.h b/ReferenceCode/Chipset/SystemAgent/SaInit/Pei/SaDmiPeim.h
new file mode 100644
index 0000000..799eb13
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/SaInit/Pei/SaDmiPeim.h
@@ -0,0 +1,94 @@
+/** @file
+  Header file for the SA Dmi Init library.
+
+@copyright
+  Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement
+**/
+#ifndef _SA_DMI_PEIM_H_
+#define _SA_DMI_PEIM_H_
+
+#include "EdkIIGluePeim.h"
+#include "SaAccess.h"
+#include "CpuRegs.h"
+#include "CpuPlatformLib.h"
+
+///
+/// Driver Consumed PPI Prototypes
+///
+#include EFI_PPI_DEPENDENCY (SaPlatformPolicy)
+#include EFI_PPI_DEPENDENCY (PchPlatformPolicy)
+#include EFI_PPI_DEPENDENCY (PchInit)
+#include EFI_PPI_DEPENDENCY (PchDmiTcVcMap)
+
+/**
+  Map SA DMI TCs to VC
+
+  @param[in] PchDmiTcVcMapPpi     - Instance of PCH_DMI_TC_VC_PPI
+  @param[in] DmiBar               - DMIBAR address
+
+  @retval EFI_SUCCESS
+**/
+EFI_STATUS
+SaSetDmiTcVcMapping (
+  IN    PCH_DMI_TC_VC_PPI  *PchDmiTcVcMapPpi,
+  IN    UINT64             DmiBar
+  )
+;
+
+/**
+  Poll SA DMI negotiation completion
+
+  @param[in] PchDmiTcVcMapPpi     - Instance of PCH_DMI_TC_VC_PPI
+  @param[in] DmiBar               - DMIBAR address
+
+  @retval EFI_SUCCESS
+**/
+EFI_STATUS
+SaPollDmiVcStatus (
+  IN    PCH_DMI_TC_VC_PPI  *PchDmiTcVcMapPpi,
+  IN    UINT64             DmiBar
+  )
+;
+
+#ifdef DMI_FLAG
+/**
+  DMI link training
+
+  @param[in] DmiBar - DMIBAR address
+**/
+VOID
+DmiLinkTrain (
+  IN  UINT64 DmiBar
+  )
+;
+
+/**
+  Additional DMI Programming Steps at PEI
+
+  @param[in] SaPlatformPolicyPpi - pointer to SA_PLATFORM_POLICY_PPI
+  @param[in] MchBar              - MCHBAR address
+  @param[in] DmiBar              - DMIBAR address
+**/
+VOID
+AdditionalDmiProgramSteps (
+  IN SA_PLATFORM_POLICY_PPI    *SaPlatformPolicyPpi,
+  IN UINT32                    MchBar,
+  IN UINT32                    DmiBar
+  )
+;
+#endif // DMI_FLAG
+#endif
diff --git a/ReferenceCode/Chipset/SystemAgent/SaInit/Pei/SaInitPeim.c b/ReferenceCode/Chipset/SystemAgent/SaInit/Pei/SaInitPeim.c
new file mode 100644
index 0000000..28fc22e
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/SaInit/Pei/SaInitPeim.c
@@ -0,0 +1,689 @@
+/** @file
+  The PEIM implements the SA PEI Initialization.
+
+@copyright
+  Copyright (c) 1999 - 2013 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement
+
+**/
+#include "SaInitPeim.h"
+#ifdef RAPID_START_FLAG
+#include EFI_PPI_CONSUMER (RapidStart)
+#endif
+
+static EFI_PEI_PPI_DESCRIPTOR     mSaPeiInitPpi[] = {
+  (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
+  &gSaPeiInitPpiGuid,
+  NULL
+};
+
+STATIC EFI_PEI_NOTIFY_DESCRIPTOR  mSaResetCompleteNotifyDesc = {
+  (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
+  &gMemoryInitHobGuid,
+  SaResetComplete
+};
+
+EFI_GUID  gEfiPeiEndOfPeiPhasePpiGuid = EFI_PEI_END_OF_PEI_PHASE_PPI_GUID;
+STATIC EFI_PEI_NOTIFY_DESCRIPTOR  mSaS3ResumeNotifyDesc = {
+  (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
+  &gEfiPeiEndOfPeiPhasePpiGuid,
+  SaS3ResumeAtEndOfPei
+};
+
+#ifdef RAPID_START_FLAG
+STATIC EFI_PEI_NOTIFY_DESCRIPTOR  mSaOnRapidStartPpiNotifyDesc = {
+  (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
+  &gRapidStartPpiGuid,
+  SaCheckRapidStartMode
+};
+#endif
+
+///
+/// Functions
+///
+static
+EFI_STATUS
+SaS3ResumeAtEndOfPei (
+  IN      EFI_PEI_SERVICES          **PeiServices,
+  IN      EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDesc,
+  IN      VOID                      *Ppi
+  )
+/**
+  This function handles SA S3 resume task
+
+  @param[in] PeiServices   - Pointer to PEI Services Table.
+  @param[in] NotifyDesc    - Pointer to the descriptor for the Notification event that
+                             caused this function to execute.
+  @param[in] Ppi           - Pointer to the PPI data associated with this function.
+
+  @retval EFI_STATUS       - Always return EFI_SUCCESS
+**/
+{
+  SA_DATA_HOB                 *SaDataHob;
+  CPU_STEPPING                CpuSteppingId;
+  CPU_FAMILY                  CpuFamilyId;
+
+  CpuSteppingId = GetCpuStepping();
+  CpuFamilyId   = GetCpuFamily();
+  ///
+  /// Get SaPegDataHob HOB
+  ///
+  SaDataHob = NULL;
+  SaDataHob = (SA_DATA_HOB *)GetFirstGuidHob (&gSaDataHobGuid);
+  if (SaDataHob != NULL) {
+     ///
+     /// If there was no DXE mode supported, always enable SMM mode
+     ///
+#if SA_PCIE_ASPM_IN_DXE == 0
+    SaDataHob->InitPcieAspmAfterOprom = 1;
+#endif
+     ///
+     /// If there was no SMM mode supported, always enable DXE mode
+     ///
+#if SA_PCIE_ASPM_IN_SMM == 0
+    SaDataHob->InitPcieAspmAfterOprom = 0;
+#endif
+
+    if ((SaDataHob->SaIotrapSmiAddress != 0) && (SaDataHob->InitPcieAspmAfterOprom == 1)) {
+#if SA_PCIE_ASPM_IN_SMM == 1
+      ///
+      /// Always generate SA IO TRAP SMI when supported
+      /// The SMI handler will directly return if not PCIe ASPM init after Oprom was enabled
+      ///
+      DEBUG ((EFI_D_INFO, "Generate SA IOTRAP SMI port=%X\n", SaDataHob->SaIotrapSmiAddress));
+      IoWrite8 (SaDataHob->SaIotrapSmiAddress, 0);
+#endif
+    }
+  }
+#if SA_PCIE_ASPM_IN_DXE == 1
+  if ((SaDataHob == NULL) || (SaDataHob->InitPcieAspmAfterOprom == 0)) {
+    ///
+    /// When SaDataHob not preset/corrupted or InitPcieAspmAfterOprom set to 0,
+    /// try to do DXE mode S3 resume task.
+    ///
+    ///
+    /// Lock processor/chipset BAR registers
+    /// Other save/restore were done by S3 Save script table
+    ///
+    if (!(((CpuFamilyId == EnumCpuHsw)    && (CpuSteppingId <= EnumHswB0)   ) ||
+          ((CpuFamilyId == EnumCpuHswUlt) && (CpuSteppingId <= EnumHswUltB0)) ||
+          ((CpuFamilyId == EnumCpuCrw)    && (CpuSteppingId <= EnumCrwB0)   ) )) {
+      AsmMsrOr64 (0x2e7, 1);
+    }
+  }
+#endif
+  return EFI_SUCCESS;
+}
+
+#ifdef RAPID_START_FLAG
+static
+EFI_STATUS
+SaCheckRapidStartMode (
+  IN      EFI_PEI_SERVICES          **PeiServices,
+  IN      EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDesc,
+  IN      VOID                      *Ppi
+  )
+/**
+  This function will check Rapid Start mode and install SaS3Resume callback notify if it was Rapid Start Resume
+
+  @param[in] PeiServices   - Pointer to PEI Services Table.
+  @param[in] NotifyDesc    - Pointer to the descriptor for the Notification event that
+                             caused this function to execute.
+  @param[in] Ppi           - Pointer to the PPI data associated with this function.
+
+  @retval EFI_STATUS       - Always return EFI_SUCCESS
+**/
+{
+  RAPID_START_PPI     *RapidStartPpi;
+  EFI_STATUS          Status;
+
+  ///
+  /// When Rapid Start implemented and in the Rapid Start Resume transition, this SA S3 resume Notify should happen early than Rapid Start End-Of-Pei callback
+  /// This is because Rapid Start End-Of-Pei callback will generate ACPI_ENABLE SMI which should be after SA S3 resume completed.
+  ///
+  Status = PeiServicesLocatePpi (&gRapidStartPpiGuid, 0, NULL, &RapidStartPpi);
+  ASSERT_EFI_ERROR (Status);
+  if (RapidStartPpi->GetMode (RapidStartPpi) == RapidStartExit) {
+    DEBUG ((EFI_D_INFO, "[SA] Install Notify callback for Rapid Start Resume\n"));
+    Status = PeiServicesNotifyPpi (&mSaS3ResumeNotifyDesc);
+    ASSERT_EFI_ERROR (Status);
+  }
+  return EFI_SUCCESS;
+}
+#endif
+
+EFI_STATUS
+EFIAPI
+SaInitPeiEntryPoint (
+  IN EFI_FFS_FILE_HEADER       *FfsHeader,
+  IN EFI_PEI_SERVICES          **PeiServices
+  )
+/**
+  SA PEI Initialization.
+
+  @param[in] FfsHeader    - Pointer to Firmware File System file header.
+  @param[in] PeiServices  - General purpose services available to every PEIM.
+
+  @retval EFI_SUCCESS
+**/
+{
+  EFI_STATUS              Status;
+  SA_PLATFORM_POLICY_PPI  *SaPlatformPolicyPpi;
+  EFI_BOOT_MODE           BootMode;
+#ifdef RAPID_START_FLAG
+  RAPID_START_PPI         *RapidStartPpi;
+#endif
+#if defined(DMI_FLAG) || defined(PEG_FLAG)
+  CPU_FAMILY              CpuFamilyId;
+
+  CpuFamilyId = GetCpuFamily();
+#endif // DMI_FLAG || PEG_FLAG
+
+  ///
+  /// Get platform policy settings through the SaPlatformPolicy PPI
+  ///
+  Status = (**PeiServices).LocatePpi (
+                            PeiServices,
+                            &gSaPlatformPolicyPpiGuid,
+                            0,
+                            NULL,
+                            (VOID **) &SaPlatformPolicyPpi
+                            );
+  ASSERT_EFI_ERROR (Status);
+
+  ///
+  /// Dump SA Platform Policy
+  ///
+  SaPeiPolicyDump (SaPlatformPolicyPpi);
+
+  ///
+  /// Program SA Bar Registers
+  ///
+  DEBUG ((EFI_D_INFO, "Programming SA Bars\n"));
+  ProgramSaBars (SaPlatformPolicyPpi);
+
+  ///
+  /// Install SA HOBs
+  ///
+  InstallSaHob (PeiServices, SaPlatformPolicyPpi);
+
+  ///
+  /// Report SA PCIe code version
+  ///
+  DEBUG ((EFI_D_INFO, "Reporting SA PCIe code version\n"));
+  ReportPcieVersion (SaPlatformPolicyPpi);
+
+#ifdef DMI_FLAG
+  if ((CpuFamilyId == EnumCpuHsw) || (CpuFamilyId == EnumCpuCrw)) {
+    ///
+    /// Initialize DMI
+    ///
+    DEBUG ((EFI_D_INFO, "Initializing DMI\n"));
+    DmiInit (PeiServices, SaPlatformPolicyPpi);
+  }
+#endif // DMI_FLAG
+
+#ifdef SG_SUPPORT
+  ///
+  /// Initialize SwitchableGraphics
+  ///
+  DEBUG ((EFI_D_INFO, "Initializing SwitchableGraphics\n"));
+  SwitchableGraphicsInit (PeiServices, SaPlatformPolicyPpi);
+#endif
+
+#ifdef PEG_FLAG
+  if ((CpuFamilyId == EnumCpuHsw) || (CpuFamilyId == EnumCpuCrw)) {
+    ///
+    /// Initialize SA PCIe
+    ///
+    DEBUG ((EFI_D_INFO, "Initializing SA PCIe\n"));
+    PciExpressInit (PeiServices, SaPlatformPolicyPpi);
+  }
+#endif // PEG_FLAG
+
+  ///
+  /// Initialize Graphics (IGD/External)
+  ///
+  DEBUG ((EFI_D_INFO, "Initializing Graphics\n"));
+  GraphicsInit (PeiServices, SaPlatformPolicyPpi);
+
+  ///
+  /// Initialize Overclocking
+  ///
+  DEBUG ((EFI_D_INFO, "Initializing System Agent Overclocking\n"));
+  SaOcInit(PeiServices, SaPlatformPolicyPpi);
+
+  ///
+  /// Initialize DMI Tc/Vc mapping setting
+  ///
+  DEBUG ((EFI_D_INFO, "Initializing DMI Tc/Vc mapping\n"));
+  SaDmiTcVcInit (PeiServices, SaPlatformPolicyPpi);
+
+  ///
+  /// Early BIOS POST Programming
+  ///
+  DEBUG ((EFI_D_INFO, "Early BIOS POST Programming\n"));
+  EarlyBiosPostProgramming(SaPlatformPolicyPpi);
+
+  ///
+  /// Install Notify
+  ///
+  Status = PeiServicesNotifyPpi (&mSaResetCompleteNotifyDesc);
+  ASSERT_EFI_ERROR (Status);
+
+  ///
+  /// Install SA S3 resume Notify only when booting from S3 resume
+  ///
+  Status = PeiServicesGetBootMode (&BootMode);
+  DEBUG ((EFI_D_INFO, "[SA] BootMode = %X\n", BootMode));
+  if ((Status == EFI_SUCCESS) && (BootMode == BOOT_ON_S3_RESUME)) {
+    DEBUG ((EFI_D_INFO, "[SA] Install SA S3 Notify callback\n"));
+    Status = PeiServicesNotifyPpi (&mSaS3ResumeNotifyDesc);
+    ASSERT_EFI_ERROR (Status);
+  }
+#ifdef RAPID_START_FLAG
+  else {
+    ///
+    /// When Rapid Start implemented and in the Rapid Start Resume transition, this SA S3 resume Notify should happen early than Rapid Start End-Of-Pei callback
+    /// This is because Rapid Start End-Of-Pei callback will generate ACPI_ENABLE SMI which should be after SA S3 resume completed.
+    ///
+    Status = PeiServicesLocatePpi (&gRapidStartPpiGuid, 0, NULL, &RapidStartPpi);
+    if (Status == EFI_SUCCESS) {
+      DEBUG ((EFI_D_INFO, "[SA] Check Rapid Start transition mode\n"));
+      if (RapidStartPpi->GetMode (RapidStartPpi) == RapidStartExit) {
+        DEBUG ((EFI_D_INFO, "[SA] Install Notify callback for Rapid Start Resume\n"));
+        Status = PeiServicesNotifyPpi (&mSaS3ResumeNotifyDesc);
+        ASSERT_EFI_ERROR (Status);
+      }
+    } else {
+      DEBUG ((EFI_D_INFO, "[SA] Postpone Rapid Start mode checking after RapidStartPpi installed\n"));
+      Status = PeiServicesNotifyPpi (&mSaOnRapidStartPpiNotifyDesc);
+    }
+  }
+#endif
+
+  ///
+  /// Install Ppi with SaInitPeim complete
+  ///
+  Status = (**PeiServices).InstallPpi (PeiServices, mSaPeiInitPpi);
+  ASSERT_EFI_ERROR (Status);
+
+  return EFI_SUCCESS;
+}
+
+STATIC
+EFI_STATUS
+SaResetComplete (
+  IN      EFI_PEI_SERVICES          **PeiServices,
+  IN      EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDesc,
+  IN      VOID                      *Ppi
+  )
+/**
+  BIOS_RESET_CPL bit is set for processor to activate the power and thermal management
+  features on the platform.
+
+  @param[in] PeiServices   - Pointer to PEI Services Table.
+  @param[in] NotifyDesc    - Pointer to the descriptor for the Notification event that
+                  caused this function to execute.
+  @param[in] Ppi           - Pointer to the PPI data associated with this function.
+
+  @retval EFI_SUCCESS
+**/
+{
+  EFI_STATUS              Status;
+  UINT64                  MchBar;
+  UINT32                  Data32And;
+  UINT32                  Data32Or;
+  SA_PLATFORM_POLICY_PPI  *SaPlatformPolicyPpi;
+
+  MchBar = McD0PciCfg64 (R_SA_MCHBAR) &~BIT0;
+
+  ///
+  /// Get platform policy settings through the SaPlatformPolicy PPI
+  ///
+  Status = PeiServicesLocatePpi (&gSaPlatformPolicyPpiGuid, 0, NULL, (VOID **) &SaPlatformPolicyPpi);
+  ASSERT_EFI_ERROR (Status);
+
+  ///
+  /// Set MCHBAR Offset 5F00h [10:9] = 11b
+  ///
+  Data32And = (UINT32)~(BIT10 | BIT9);
+  Data32Or  = 0x3 << 9;
+  Mmio32AndThenOr (MchBar, R_SA_MCHBAR_SAPMCTL_OFFSET, Data32And, Data32Or);
+
+  ///
+  /// Set BIOS_RESET_CPL
+  ///
+  DEBUG ((EFI_D_INFO, "Set BIOS_RESET_CPL to indicate all configurations complete\n"));
+  Mmio8Or ((UINTN) MchBar, R_SA_MCHBAR_BIOS_RESET_CPL_OFFSET, BIT0 | BIT1);
+
+  return EFI_SUCCESS;
+}
+
+VOID
+ProgramSaBars (
+  IN    SA_PLATFORM_POLICY_PPI   *SaPlatformPolicyPpi
+  )
+/**
+  Programs SA Bars
+
+  @param[in] SaPlatformPolicyPpi - Instance of SA_PLATFORM_POLICY_PPI
+**/
+{
+  CPU_FAMILY  CpuFamilyId;
+
+  CpuFamilyId = GetCpuFamily();
+
+  ///
+  /// Program SA MchBar, DmiBar and EpBar
+  ///
+  McD0PciCfg64 (R_SA_MCHBAR)   = (UINT64) (SaPlatformPolicyPpi->PlatformData->MchBar        | BIT0);
+  McD0PciCfg64 (R_SA_DMIBAR)   = (UINT64) (SaPlatformPolicyPpi->PlatformData->DmiBar        | BIT0);
+  McD0PciCfg64 (R_SA_PXPEPBAR) = (UINT64) (SaPlatformPolicyPpi->PlatformData->EpBar         | BIT0);
+
+  ///
+  /// Program SA GdxcBar
+  ///
+  Mmio64 ((UINTN) (SaPlatformPolicyPpi->PlatformData->MchBar), R_SA_MCHBAR_GDXCBAR_OFFSET) = (UINT64)
+    (SaPlatformPolicyPpi->PlatformData->GdxcBar | BIT0);
+
+  if (CpuFamilyId == EnumCpuCrw) {
+    ///
+    /// Program SA EdramBar
+    ///
+    Mmio64 ((UINTN) (SaPlatformPolicyPpi->PlatformData->MchBar), R_SA_MCHBAR_EDRAMBAR_OFFSET) = (UINT64)
+      (SaPlatformPolicyPpi->PlatformData->EdramBar | BIT0);
+  }
+}
+
+VOID
+EarlyBiosPostProgramming (
+  IN    SA_PLATFORM_POLICY_PPI   *SaPlatformPolicyPpi
+  )
+/**
+  Do Early BIOS POST Programming
+
+  @param[in] SaPlatformPolicyPpi - Instance of SA_PLATFORM_POLICY_PPI
+**/
+{
+  /// SA BS 11.1 Early BIOS POST Programming
+  /// 1.  Enable System Agent Clock Gating by setting the MCHBAR offset 5F00h [0] = '1b'.
+  MmioOr32 ((UINTN) (SaPlatformPolicyPpi->PlatformData->MchBar + 0x5F00), BIT0);
+}
+
+EFI_STATUS
+InstallSaHob (
+  IN EFI_PEI_SERVICES          **PeiServices,
+  IN SA_PLATFORM_POLICY_PPI    *SaPlatformPolicyPpi
+  )
+/**
+  Init and Install SA Hob
+
+  @param[in] PeiServices  - General purpose services available to every PEIM.
+  @param[in] SaPlatformPolicyPpi  - SaPlatformPolicyPpi to access the GtConfig related information
+
+  @retval EFI_SUCCESS
+**/
+{
+  EFI_STATUS                  Status;
+  SA_DATA_HOB                 *SaDataHob;
+  PEI_CPU_PLATFORM_POLICY_PPI *CpuPlatformPolicy;
+
+  ///
+  /// Create HOB for SA Data
+  ///
+  Status = (**PeiServices).CreateHob (
+                             PeiServices,
+                             EFI_HOB_TYPE_GUID_EXTENSION,
+                             sizeof (SA_DATA_HOB),
+                             (VOID **) &SaDataHob
+                             );
+  ASSERT_EFI_ERROR (Status);
+
+  ///
+  /// Initialize default HOB data
+  ///
+  SaDataHob->EfiHobGuidType.Name = gSaDataHobGuid;
+  ZeroMem (&(SaDataHob->DprDirectory[EnumDprDirectoryTxt]), sizeof (DPR_DIRECTORY_ENTRY));
+  ZeroMem (&(SaDataHob->DprDirectory[EnumDprDirectoryPfat]), sizeof (DPR_DIRECTORY_ENTRY));
+  ZeroMem (&(SaDataHob->PegData), sizeof (SA_PEG_DATA));
+  SaDataHob->PegDataValid             = FALSE;
+  SaDataHob->PegPlatformResetRequired = FALSE;
+  if (SaPlatformPolicyPpi->Revision >= SA_PLATFORM_POLICY_PPI_REVISION_2) {
+    SaDataHob->SaIotrapSmiAddress = SaPlatformPolicyPpi->PcieConfig->SaIotrapSmiAddress;
+    SaDataHob->InitPcieAspmAfterOprom = SaPlatformPolicyPpi->PcieConfig->InitPcieAspmAfterOprom;
+  } else {
+    SaDataHob->SaIotrapSmiAddress = 0;
+    SaDataHob->InitPcieAspmAfterOprom = 0;
+  }
+
+  ///
+  /// Get platform policy settings through the SaPlatformPolicy PPI
+  ///
+  Status = (**PeiServices).LocatePpi (
+                            PeiServices,
+                            &gPeiCpuPlatformPolicyPpiGuid,
+                            0,
+                            NULL,
+                            (VOID **) &CpuPlatformPolicy
+                            );
+  ASSERT_EFI_ERROR (Status);
+
+  ///
+  /// TXT DPR Directory Entry
+  ///
+#if defined(TXT_SUPPORT_FLAG) && (TXT_SUPPORT_FLAG == 1)
+  SaDataHob->DprDirectory[EnumDprDirectoryTxt].Type = DPR_DIRECTORY_TYPE_TXT;
+  if (CpuPlatformPolicy->CpuConfig->Txt) {
+    SaDataHob->DprDirectory[EnumDprDirectoryTxt].Size = (UINT8) RShiftU64 (CpuPlatformPolicy->SecurityConfig->TxtConfig->TxtDprMemorySize, 20);
+  }
+#endif
+
+  ///
+  /// PFAT Directory Entry
+  ///
+  SaDataHob->DprDirectory[EnumDprDirectoryPfat].Type = DPR_DIRECTORY_TYPE_PFAT;
+  if (CpuPlatformPolicy->CpuConfig->Pfat) {
+    SaDataHob->DprDirectory[EnumDprDirectoryPfat].Size = CpuPlatformPolicy->SecurityConfig->PfatConfig->PfatMemSize;
+  }
+
+  DEBUG ((EFI_D_INFO, "SA Data HOB installed\n"));
+
+  return EFI_SUCCESS;
+}
+
+EFI_STATUS
+ReportPcieVersion (
+  IN    SA_PLATFORM_POLICY_PPI   *SaPlatformPolicyPpi
+  )
+/**
+  Report the SA PCIe initialization code version.
+
+  @param[in] SaPlatformPolicyPpi - Instance of SA_PLATFORM_POLICY_PPI
+
+  @retval EFI_SUCCESS
+**/
+{
+  UINT32            Version;
+  CPU_FAMILY        CpuFamilyId;
+  CPU_STEPPING      CpuSteppingId;
+  const CodeVersion SaPcieCodeVersion = {
+#include "SaPcieVersion.h"
+  };
+
+  DEBUG ((EFI_D_INFO, "***************** System Agent PCIe code version *****************\n"));
+  DEBUG ((EFI_D_INFO, "** Major version number is: %3d                                 **\n", SaPcieCodeVersion.Major));
+  DEBUG ((EFI_D_INFO, "** Minor version number is: %3d                                 **\n", SaPcieCodeVersion.Minor));
+  DEBUG ((EFI_D_INFO, "** Rev version number is:   %3d                                 **\n", SaPcieCodeVersion.Rev));
+  DEBUG ((EFI_D_INFO, "** Build number is:         %3d                                 **\n", SaPcieCodeVersion.Build));
+  DEBUG ((EFI_D_INFO, "******************************************************************\n"));
+
+  Version = (((UINT32) SaPcieCodeVersion.Major) << 24) | (((UINT32) SaPcieCodeVersion.Minor) << 16) | (((UINT32) SaPcieCodeVersion.Rev) << 8) | (((UINT32) SaPcieCodeVersion.Build));
+
+  CpuFamilyId   = GetCpuFamily();
+  CpuSteppingId = GetCpuStepping();
+
+  ///
+  /// Store SA Reference Code version and SA PCIe code version in scrachpad registers
+  ///
+  if ((CpuFamilyId == EnumCpuHsw) && (CpuSteppingId == EnumHswA0)) {
+    Mmio32 ((UINTN) (SaPlatformPolicyPpi->PlatformData->MchBar), R_SA_MCHBAR_PCIE_CODE_VERSION_OFFSET_HSW) = Version;
+  } else {
+    Mmio32 ((UINTN) (SaPlatformPolicyPpi->PlatformData->DmiBar), R_SA_DMIBAR_SCRATCHPAD0_OFFSET) = SaPlatformPolicyPpi->Revision;
+    Mmio32 ((UINTN) (SaPlatformPolicyPpi->PlatformData->DmiBar), R_SA_DMIBAR_SCRATCHPAD1_OFFSET) = Version;
+  }
+  return EFI_SUCCESS;
+}
+
+VOID
+SaPeiPolicyDump (
+  IN    SA_PLATFORM_POLICY_PPI   *SaPlatformPolicyPpi
+  )
+/**
+  This function prints the PEI phase platform policy.
+
+  @param[in] SaPlatformPolicyPpi - Instance of SA_PLATFORM_POLICY_PPI
+**/
+{
+#ifdef EFI_DEBUG
+  INTN   i;
+
+  DEBUG ((EFI_D_INFO, "\n------------------------ SA Platform Policy (PEI) dump BEGIN -----------------\n"));
+  DEBUG ((EFI_D_INFO, "Revision : %x\n", SaPlatformPolicyPpi->Revision));
+
+  DEBUG ((EFI_D_INFO, "------------------------ SA_PLATFORM_DATA -----------------\n"));
+
+  DEBUG ((EFI_D_INFO, " SpdAddressTable[%d] :", SA_MC_MAX_SOCKETS));
+  for (i = 0; i < SA_MC_MAX_SOCKETS; i++) {
+    DEBUG ((EFI_D_INFO, " %x", SaPlatformPolicyPpi->PlatformData->SpdAddressTable[i]));
+  }
+  DEBUG ((EFI_D_INFO, "\n"));
+
+  DEBUG ((EFI_D_INFO, " MchBar : %x\n", SaPlatformPolicyPpi->PlatformData->MchBar));
+  DEBUG ((EFI_D_INFO, " DmiBar : %x\n", SaPlatformPolicyPpi->PlatformData->DmiBar));
+  DEBUG ((EFI_D_INFO, " EpBar : %x\n", SaPlatformPolicyPpi->PlatformData->EpBar));
+  DEBUG ((EFI_D_INFO, " PciExpressBar : %x\n", SaPlatformPolicyPpi->PlatformData->PciExpressBar));
+  DEBUG ((EFI_D_INFO, " SmbusBar : %x\n", SaPlatformPolicyPpi->PlatformData->SmbusBar));
+  DEBUG ((EFI_D_INFO, " GdxcBar : %x\n", SaPlatformPolicyPpi->PlatformData->GdxcBar));
+  DEBUG ((EFI_D_INFO, " TsegSize : %x\n", SaPlatformPolicyPpi->PlatformData->TsegSize));
+  DEBUG ((EFI_D_INFO, " UserBd : %x\n", SaPlatformPolicyPpi->PlatformData->UserBd));
+  DEBUG ((EFI_D_INFO, " FastBoot : %x\n", SaPlatformPolicyPpi->PlatformData->FastBoot));
+  DEBUG ((EFI_D_INFO, " EdramBar : %x\n", SaPlatformPolicyPpi->PlatformData->EdramBar));
+
+  DEBUG ((EFI_D_INFO, "------------------------ GT_CONFIGURATION -----------------\n"));
+  DEBUG ((EFI_D_INFO, " MmioSize : %x MB\n", SaPlatformPolicyPpi->GtConfig->MmioSize));
+  DEBUG ((EFI_D_INFO, " GttSize : %x MB\n", SaPlatformPolicyPpi->GtConfig->GttSize));
+  DEBUG ((EFI_D_INFO, " IgdDvmt50PreAlloc : %x\n", SaPlatformPolicyPpi->GtConfig->IgdDvmt50PreAlloc));
+  DEBUG ((EFI_D_INFO, " InternalGraphics : %x\n", SaPlatformPolicyPpi->GtConfig->InternalGraphics));
+  DEBUG ((EFI_D_INFO, " PrimaryDisplay : %x\n", SaPlatformPolicyPpi->GtConfig->PrimaryDisplay));
+  DEBUG ((EFI_D_INFO, " ApertureSize : %x\n", SaPlatformPolicyPpi->GtConfig->ApertureSize));
+  DEBUG ((EFI_D_INFO, " GttMmAdr : %x\n", SaPlatformPolicyPpi->GtConfig->GttMmAdr));
+
+  DEBUG ((EFI_D_INFO, "------------------------ PCIE_CONFIGURATION -----------------\n"));
+  DEBUG ((EFI_D_INFO, " DmiVc1 : %x\n", SaPlatformPolicyPpi->PcieConfig->DmiVc1));
+  DEBUG ((EFI_D_INFO, " DmiVcp : %x\n", SaPlatformPolicyPpi->PcieConfig->DmiVcp));
+  DEBUG ((EFI_D_INFO, " DmiVcm : %x\n", SaPlatformPolicyPpi->PcieConfig->DmiVcm));
+  DEBUG ((EFI_D_INFO, " DmiGen2 : %x\n", SaPlatformPolicyPpi->PcieConfig->DmiGen2));
+  DEBUG ((EFI_D_INFO, " AlwaysEnablePeg : %x\n", SaPlatformPolicyPpi->PcieConfig->AlwaysEnablePeg));
+
+  DEBUG ((EFI_D_INFO, " PegGenx[%d] :", SA_PEG_MAX_FUN));
+  for (i = 0; i < SA_PEG_MAX_FUN; i++) {
+    DEBUG ((EFI_D_INFO, " %x", SaPlatformPolicyPpi->PcieConfig->PegGenx[i]));
+  }
+  DEBUG ((EFI_D_INFO, "\n"));
+
+  DEBUG ((EFI_D_INFO, " PegGen3Equalization : %x\n", SaPlatformPolicyPpi->PcieConfig->PegGen3Equalization));
+
+  DEBUG ((EFI_D_INFO, " Gen3RootPortPreset[%d] :", SA_PEG_MAX_LANE));
+  for (i = 0; i < SA_PEG_MAX_LANE; i++) {
+    DEBUG ((EFI_D_INFO, " %x", SaPlatformPolicyPpi->PcieConfig->Gen3RootPortPreset[i]));
+  }
+  DEBUG ((EFI_D_INFO, "\n"));
+
+  DEBUG ((EFI_D_INFO, " Gen3EndPointPreset[%d] :", SA_PEG_MAX_LANE));
+  for (i = 0; i < SA_PEG_MAX_LANE; i++) {
+    DEBUG ((EFI_D_INFO, " %x", SaPlatformPolicyPpi->PcieConfig->Gen3EndPointPreset[i]));
+  }
+  DEBUG ((EFI_D_INFO, "\n"));
+
+  DEBUG ((EFI_D_INFO, " Gen3EndPointHint[%d] :", SA_PEG_MAX_LANE));
+  for (i = 0; i < SA_PEG_MAX_LANE; i++) {
+    DEBUG ((EFI_D_INFO, " %x", SaPlatformPolicyPpi->PcieConfig->Gen3EndPointHint[i]));
+  }
+  DEBUG ((EFI_D_INFO, "\n"));
+
+  DEBUG ((EFI_D_INFO, " PegSamplerCalibrate : %x\n", SaPlatformPolicyPpi->PcieConfig->PegSamplerCalibrate));
+  DEBUG ((EFI_D_INFO, " PegGen3EqualizationPhase2 : %x\n", SaPlatformPolicyPpi->PcieConfig->PegGen3EqualizationPhase2));
+  DEBUG ((EFI_D_INFO, " PegGen3PresetSearch : %x\n", SaPlatformPolicyPpi->PcieConfig->PegGen3PresetSearch));
+  DEBUG ((EFI_D_INFO, " PegGen3PresetSearchDwellTime : %x\n", SaPlatformPolicyPpi->PcieConfig->PegGen3PresetSearchDwellTime));
+  DEBUG ((EFI_D_INFO, " PegGen3PresetSearchMarginSteps : %x\n", SaPlatformPolicyPpi->PcieConfig->PegGen3PresetSearchMarginSteps));
+  DEBUG ((EFI_D_INFO, " PegGen3PresetSearchStartMargin : %x\n", SaPlatformPolicyPpi->PcieConfig->PegGen3PresetSearchStartMargin));
+  DEBUG ((EFI_D_INFO, " PegSwingControl : %x\n", SaPlatformPolicyPpi->PcieConfig->PegSwingControl));
+  if (SaPlatformPolicyPpi->Revision >= SA_PLATFORM_POLICY_PPI_REVISION_2) {
+    DEBUG ((EFI_D_INFO, " PegGen3PresetSearchVoltageMarginSteps : %x\n", SaPlatformPolicyPpi->PcieConfig->PegGen3PresetSearchVoltageMarginSteps));
+    DEBUG ((EFI_D_INFO, " PegGen3PresetSearchVoltageStartMargin : %x\n", SaPlatformPolicyPpi->PcieConfig->PegGen3PresetSearchVoltageStartMargin));
+    DEBUG ((EFI_D_INFO, " PegGen3PresetSearchFavorTiming : %x\n", SaPlatformPolicyPpi->PcieConfig->PegGen3PresetSearchFavorTiming));
+    DEBUG ((EFI_D_INFO, " PegDataPtr : %p\n", SaPlatformPolicyPpi->PcieConfig->PegDataPtr));
+    DEBUG ((EFI_D_INFO, " PegGen3ForcePresetSearch : %x\n", SaPlatformPolicyPpi->PcieConfig->PegGen3ForcePresetSearch));
+    DEBUG ((EFI_D_INFO, " InitPcieAspmAfterOprom : %x\n", SaPlatformPolicyPpi->PcieConfig->InitPcieAspmAfterOprom));
+    DEBUG ((EFI_D_INFO, " SaIotrapSmiAddress : %x\n", SaPlatformPolicyPpi->PcieConfig->SaIotrapSmiAddress));
+  }
+  if (SaPlatformPolicyPpi->Revision >= SA_PLATFORM_POLICY_PPI_REVISION_3) {
+    DEBUG ((EFI_D_INFO, " PegGpioData : %p\n", SaPlatformPolicyPpi->PcieConfig->PegGpioData));
+    if (SaPlatformPolicyPpi->PcieConfig->PegGpioData != NULL) {
+      DEBUG ((EFI_D_INFO, " PegGpioData->GpioSupport : %x\n", SaPlatformPolicyPpi->PcieConfig->PegGpioData->GpioSupport));
+      if (SaPlatformPolicyPpi->PcieConfig->PegGpioData->SaPegReset != NULL) {
+        DEBUG ((EFI_D_INFO, " PegGpioData->SaPegReset->Value : %x\n", SaPlatformPolicyPpi->PcieConfig->PegGpioData->SaPegReset->Value));
+        DEBUG ((EFI_D_INFO, " PegGpioData->SaPegReset->Active : %x\n", SaPlatformPolicyPpi->PcieConfig->PegGpioData->SaPegReset->Active));
+      }
+    }
+    DEBUG ((EFI_D_INFO, " PegGen3PresetSearchErrorTarget : %x\n", SaPlatformPolicyPpi->PcieConfig->PegGen3PresetSearchErrorTarget));
+    DEBUG ((EFI_D_INFO, " RxCEMLoopback : %x\n", SaPlatformPolicyPpi->PcieConfig->RxCEMLoopback));
+    DEBUG ((EFI_D_INFO, " RxCEMLoopbackLane : %x\n", SaPlatformPolicyPpi->PcieConfig->RxCEMLoopbackLane));
+
+    DEBUG ((EFI_D_INFO, " Gen3RxCtleP[%d] :", SA_PEG_MAX_BUNDLE));
+    for (i = 0; i < SA_PEG_MAX_BUNDLE; i++) {
+      DEBUG ((EFI_D_INFO, " %x", SaPlatformPolicyPpi->PcieConfig->Gen3RxCtleP[i]));
+     }
+    DEBUG ((EFI_D_INFO, "\n"));
+  }
+
+  DEBUG ((EFI_D_INFO, "------------------------ OVERCLOCKING_CONFIGURATION -----------------\n"));
+  DEBUG ((EFI_D_INFO, " GtVoltageOffset : %x\n", SaPlatformPolicyPpi->OcConfig->GtVoltageOffset));
+  DEBUG ((EFI_D_INFO, " GtVoltageOverride : %x\n", SaPlatformPolicyPpi->OcConfig->GtVoltageOverride));
+  DEBUG ((EFI_D_INFO, " GtExtraTurboVoltage : %x\n", SaPlatformPolicyPpi->OcConfig->GtExtraTurboVoltage));
+  DEBUG ((EFI_D_INFO, " GtMaxOcTurboRatio : %x\n", SaPlatformPolicyPpi->OcConfig->GtMaxOcTurboRatio));
+  DEBUG ((EFI_D_INFO, " SaVoltageOffset : %x\n", SaPlatformPolicyPpi->OcConfig->SaVoltageOffset));
+  DEBUG ((EFI_D_INFO, " GtVoltageMode : %x\n", SaPlatformPolicyPpi->OcConfig->GtVoltageMode));
+  DEBUG ((EFI_D_INFO, " OcSupport : %x\n", SaPlatformPolicyPpi->OcConfig->OcSupport));
+  DEBUG ((EFI_D_INFO, " IoaVoltageOffset : %x\n", SaPlatformPolicyPpi->OcConfig->IoaVoltageOffset));
+  DEBUG ((EFI_D_INFO, " IodVoltageOffset : %x\n", SaPlatformPolicyPpi->OcConfig->IodVoltageOffset));
+
+  DEBUG ((EFI_D_INFO, "------------------------ Misc -----------------\n"));
+  DEBUG ((EFI_D_INFO, " S3DataPtr : %x\n", SaPlatformPolicyPpi->S3DataPtr));
+
+  if (SaPlatformPolicyPpi->Revision >= SA_PLATFORM_POLICY_PPI_REVISION_3) {
+    DEBUG ((EFI_D_INFO, "------------------------ SG_GPIO_DATA -----------------\n"));
+    DEBUG ((EFI_D_INFO, " SgGpioData : %x\n", SaPlatformPolicyPpi->SgGpioData));
+    if (SaPlatformPolicyPpi->SgGpioData != NULL) {
+      DEBUG ((EFI_D_INFO, " SgGpioData->GpioSupport : %x\n", SaPlatformPolicyPpi->SgGpioData->GpioSupport));
+    }
+  }
+
+  DEBUG ((EFI_D_INFO, "\n------------------------ SA Platform Policy (PEI) dump END -----------------\n"));
+#endif
+  return;
+}
diff --git a/ReferenceCode/Chipset/SystemAgent/SaInit/Pei/SaInitPeim.cif b/ReferenceCode/Chipset/SystemAgent/SaInit/Pei/SaInitPeim.cif
new file mode 100644
index 0000000..c60de34
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/SaInit/Pei/SaInitPeim.cif
@@ -0,0 +1,30 @@
+<component>
+	name = "SaInitPeim"
+	category = ModulePart
+	LocalRoot = "ReferenceCode\Chipset\SystemAgent\SaInit\Pei"
+	RefName = "SaInitPeim"
+[files]
+"SaInitPeim.sdl"	
+"SaInitPeim.mak"	
+"SaInitPeim.h"	
+"SaInitPeim.c"	
+"SaInitPeim.dxs"	
+"SaInitPeim.inf"	
+"GraphicsInit.h"	
+"GraphicsInit.c"	
+"SaDmiPeim.h"	
+"SaDmiPeim.c"	
+"PciExpressInit.h"	
+"PciExpressInit.c"	
+"PcieTraining.c"	
+"PcieTraining.h"	
+"PcieTrainingEqSettings.c"	
+"PcieTrainingErrorCount.c"	
+"PcieTrainingLinkRecovery.c"	
+"PcieTrainingMargining.c"	
+"PcieTrainingPhase3.c"	
+"SaOcInit.c"	
+"SaOcInit.h"	
+"SwitchableGraphicsInit.c"	
+"SwitchableGraphicsInit.h"	
+<endComponent>
diff --git a/ReferenceCode/Chipset/SystemAgent/SaInit/Pei/SaInitPeim.dxs b/ReferenceCode/Chipset/SystemAgent/SaInit/Pei/SaInitPeim.dxs
new file mode 100644
index 0000000..4eedf37
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/SaInit/Pei/SaInitPeim.dxs
@@ -0,0 +1,49 @@
+/** @file
+  Dependency expression source file.
+
+@copyright
+  Copyright (c)  2009 - 2013 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains a 'Sample Driver' and is licensed as such
+  under the terms of your license agreement with Intel or your
+  vendor.  This file may be modified by the user, subject to
+  the additional terms of the license agreement
+
+**/
+  
+
+//
+// Common for R8 and R9 codebase
+//
+#include "AutoGen.h"
+#include "PeimDepex.h"
+
+//
+// BUILD_WITH_GLUELIB and BUILD_WITH_EDKII_GLUE_LIB are both "defined" in R8 codebase;
+// BUILD_WITH_EDKII_GLUE_LIB is defined in Edk-Dev-Snapshot-20070228 and later version
+// BUILD_WITH_GLUELIB and BUILD_WITH_EDKII_GLUE_LIB are "not defined" in R9 codebase.
+//
+#if defined (BUILD_WITH_GLUELIB) || defined (BUILD_WITH_EDKII_GLUE_LIB)
+#include "EfiDepex.h"
+#endif
+
+#include EFI_PPI_DEPENDENCY (SaPlatformPolicy)
+#include EFI_PPI_DEPENDENCY (CpuPlatformPolicy)
+#include EFI_PPI_DEPENDENCY (PchInit)
+#include EFI_PPI_DEPENDENCY (Stall)
+#include EFI_PPI_DEPENDENCY (PchMeUma)
+
+DEPENDENCY_START
+  SA_PLATFORM_POLICY_PPI_GUID      AND
+  PCH_INIT_PPI_GUID                AND
+  PEI_STALL_PPI_GUID               AND
+  PEI_CPU_PLATFORM_POLICY_PPI_GUID
+  AND PCH_ME_UMA_PPI_GUID
+DEPENDENCY_END
diff --git a/ReferenceCode/Chipset/SystemAgent/SaInit/Pei/SaInitPeim.h b/ReferenceCode/Chipset/SystemAgent/SaInit/Pei/SaInitPeim.h
new file mode 100644
index 0000000..2f3263c
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/SaInit/Pei/SaInitPeim.h
@@ -0,0 +1,260 @@
+/** @file
+  Header file for the SA Init PEIM
+
+@copyright
+  Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement
+**/
+#ifndef _SA_INIT_PEIM_H_
+#define _SA_INIT_PEIM_H_
+
+///
+/// External include files do NOT need to be explicitly specified in real EDKII
+/// environment
+///
+#if !defined(EDK_RELEASE_VERSION) || (EDK_RELEASE_VERSION < 0x00020000)
+#include "EdkIIGluePeim.h"
+#include "SaAccess.h"
+#include "MemInfoHob.h"
+#include "CpuRegs.h"
+#include "CpuPlatformLib.h"
+#include "SaOcInit.h"
+
+#include EFI_PPI_DEPENDENCY  (SaPlatformPolicy)
+#include EFI_PPI_DEPENDENCY  (CpuPlatformPolicy)
+#include EFI_PPI_PRODUCER    (SaPeiInit)
+#include EFI_GUID_DEFINITION (SaDataHob)
+#endif
+///
+/// Data definitions & structures
+///
+
+EFI_GUID  gMemoryInitHobGuid = EFI_PEI_PERMANENT_MEMORY_INSTALLED_PPI_GUID;
+
+///
+/// Functions
+///
+EFI_STATUS
+EFIAPI
+SaInitPeiEntryPoint (
+  IN EFI_FFS_FILE_HEADER       *FfsHeader,
+  IN EFI_PEI_SERVICES          **PeiServices
+  )
+/**
+  SA PEI Initialization.
+
+  @param[in] FfsHeader    - Pointer to Firmware File System file header.
+  @param[in] PeiServices  - General purpose services available to every PEIM.
+
+  @retval EFI_SUCCESS
+**/
+;
+
+VOID
+ProgramSaBars (
+  IN    SA_PLATFORM_POLICY_PPI    *SaPlatformPolicyPpi
+  )
+/**
+  Programs Sa Bars
+
+  @param[in] SaPlatformPolicyPpi  - Instance of SA_PLATFORM_POLICY_PPI
+**/
+;
+
+VOID
+SwitchableGraphicsInit (
+  IN EFI_PEI_SERVICES             **PeiServices,
+  IN SA_PLATFORM_POLICY_PPI       *SaPlatformPolicyPpi
+  )
+/**
+  SwitchableGraphicsInit: Initialize the Switchable Graphics if enabled
+
+  @param[in] PeiServices          - Pointer to the PEI services table
+  @param[in] SaPlatformPolicyPpi  - SaPlatformPolicyPpi to access the SgConfig related information
+**/
+;
+
+VOID
+EarlyBiosPostProgramming (
+  IN    SA_PLATFORM_POLICY_PPI   *SaPlatformPolicyPpi
+  )
+/**
+  Do Early BIOS POST Programming
+
+  @param[in] SaPlatformPolicyPpi - Instance of SA_PLATFORM_POLICY_PPI
+**/
+;
+
+VOID
+GraphicsInit (
+  IN EFI_PEI_SERVICES             **PeiServices,
+  IN SA_PLATFORM_POLICY_PPI       *SaPlatformPolicyPpi
+  )
+/**
+  GraphicsInit: Initialize the IGD if no other external graphics is present
+
+  @param[in] PeiServices          - Pointer to the PEI services table
+  @param[in] SaPlatformPolicyPpi  - SaPlatformPolicyPpi to access the GtConfig related information
+**/
+;
+
+EFI_STATUS
+SaDmiTcVcInit (
+  IN EFI_PEI_SERVICES          **PeiServices,
+  IN SA_PLATFORM_POLICY_PPI    *SaPlatformPolicyPpi
+  )
+/**
+  Initialize DMI Tc/Vc mapping through SA-PCH.
+
+  @param[in] PeiServices          - General purpose services available to every PEIM.
+  @param[in] SaPlatformPolicyPpi  - SaPlatformPolicyPpi to access the GtConfig related information
+
+  @retval EFI_SUCCESS
+**/
+;
+
+#ifdef DMI_FLAG
+EFI_STATUS
+DmiInit (
+  IN EFI_PEI_SERVICES          **PeiServices,
+  IN SA_PLATFORM_POLICY_PPI    *SaPlatformPolicyPpi
+  )
+/**
+  Initialize DMI.
+
+  @param[in] PeiServices          - General purpose services available to every PEIM.
+  @param[in] SaPlatformPolicyPpi  - SaPlatformPolicyPpi to access the GtConfig related information
+
+  @retval EFI_SUCCESS
+**/
+;
+#endif // DMI_FLAG
+
+#ifdef PEG_FLAG
+VOID
+PciExpressInit (
+  IN EFI_PEI_SERVICES          **PeiServices,
+  IN SA_PLATFORM_POLICY_PPI    *SaPlatformPolicyPpi
+  )
+/**
+  GraphicsInit: Initialize the IGD if no other external graphics is present
+
+  @param[in] PeiServices          - Pointer to the PEI services table
+  @param[in] SaPlatformPolicyPpi  - SaPlatformPolicyPpi to access the GtConfig related information
+**/
+;
+#endif // PEG_FLAG
+
+EFI_STATUS
+InstallSaHob (
+  IN EFI_PEI_SERVICES          **PeiServices,
+  IN SA_PLATFORM_POLICY_PPI    *SaPlatformPolicyPpi
+  )
+/**
+  Init and Install SA Hob
+
+  @param[in] PeiServices  - General purpose services available to every PEIM.
+  @param[in] SaPlatformPolicyPpi  - SaPlatformPolicyPpi to access the GtConfig related information
+
+  @retval EFI_SUCCESS
+**/
+;
+
+EFI_STATUS
+ReportPcieVersion (
+  IN    SA_PLATFORM_POLICY_PPI   *SaPlatformPolicyPpi
+  )
+/**
+  Report the SA PCIe initialization code version.
+
+  @param[in] SaPlatformPolicyPpi - Instance of SA_PLATFORM_POLICY_PPI
+
+  @retval EFI_SUCCESS
+**/
+;
+
+STATIC
+EFI_STATUS
+SaResetComplete (
+  IN      EFI_PEI_SERVICES          **PeiServices,
+  IN      EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDesc,
+  IN      VOID                      *Ppi
+  )
+/**
+  BIOS_CPL_BIT is set for processor to activate the power and thermal management
+  features on the platform.
+
+  @param[in] PeiServices   - Pointer to PEI Services Table.
+  @param[in] NotifyDesc    - Pointer to the descriptor for the Notification event that
+                  caused this function to execute.
+  @param[in] Ppi           - Pointer to the PPI data associated with this function.
+
+  @retval EFI_SUCCESS
+**/
+;
+
+VOID
+SaPeiPolicyDump (
+  IN    SA_PLATFORM_POLICY_PPI   *SaPlatformPolicyPpi
+  )
+/**
+  This function prints the PEI phase platform policy.
+
+  @param[in] SaPlatformPolicyPpi - Instance of SA_PLATFORM_POLICY_PPI
+**/
+;
+
+static
+EFI_STATUS
+SaS3ResumeAtEndOfPei (
+  IN      EFI_PEI_SERVICES          **PeiServices,
+  IN      EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDesc,
+  IN      VOID                      *Ppi
+  )
+/**
+  This function handles SA S3 resume task
+
+  @param[in] PeiServices   - Pointer to PEI Services Table.
+  @param[in] NotifyDesc    - Pointer to the descriptor for the Notification event that
+                             caused this function to execute.
+  @param[in] Ppi           - Pointer to the PPI data associated with this function.
+
+  @retval EFI_STATUS       - Always return EFI_SUCCESS
+**/
+;
+
+#ifdef RAPID_START_FLAG
+static
+EFI_STATUS
+SaCheckRapidStartMode (
+  IN      EFI_PEI_SERVICES          **PeiServices,
+  IN      EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDesc,
+  IN      VOID                      *Ppi
+  )
+/**
+  This function will check Rapid Start mode and install SaS3Resume callback notify if it was Rapid Start Resume
+
+  @param[in] PeiServices   - Pointer to PEI Services Table.
+  @param[in] NotifyDesc    - Pointer to the descriptor for the Notification event that
+                             caused this function to execute.
+  @param[in] Ppi           - Pointer to the PPI data associated with this function.
+
+  @retval EFI_STATUS       - Always return EFI_SUCCESS
+**/
+;
+#endif // RAPID_START_FLAG
+
+#endif
diff --git a/ReferenceCode/Chipset/SystemAgent/SaInit/Pei/SaInitPeim.inf b/ReferenceCode/Chipset/SystemAgent/SaInit/Pei/SaInitPeim.inf
new file mode 100644
index 0000000..8ca75a4
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/SaInit/Pei/SaInitPeim.inf
@@ -0,0 +1,132 @@
+## @file
+#  Component description file for the SA Init PEIM.
+#
+#@copyright
+#  Copyright (c)  2010 - 2014 Intel Corporation. All rights reserved
+#  This software and associated documentation (if any) is furnished
+#  under a license and may only be used or copied in accordance
+#  with the terms of the license. Except as permitted by such
+#  license, no part of this software or documentation may be
+#  reproduced, stored in a retrieval system, or transmitted in any
+#  form or by any means without the express written consent of
+#  Intel Corporation.
+#
+#  This file contains a 'Sample Driver' and is licensed as such
+#  under the terms of your license agreement with Intel or your
+#  vendor.  This file may be modified by the user, subject to
+#  the additional terms of the license agreement
+#
+
+[defines]
+BASE_NAME            = SaInitPeim
+FILE_GUID            = FD236AE7-0791-48c4-B29E-29BDEEE1A811
+COMPONENT_TYPE       = PE32_PEIM
+
+[sources.common]
+  SaInitPeim.h
+  SaInitPeim.c
+  GraphicsInit.h
+  GraphicsInit.c
+  SaDmiPeim.h
+  SaDmiPeim.c
+  PciExpressInit.h
+  PciExpressInit.c
+  SwitchableGraphicsInit.c
+  SwitchableGraphicsInit.h
+  PcieTraining.h
+  PcieTraining.c
+  PcieTrainingEqSettings.c
+  PcieTrainingErrorCount.c
+  PcieTrainingMargining.c
+  PcieTrainingLinkRecovery.c
+  PcieTrainingPhase3.c
+  SaOcInit.h
+  SaOcInit.c
+#
+# Edk II Glue Driver Entry Point
+#
+  EdkIIGluePeimEntryPoint.c
+
+
+[includes.common]
+  .
+  ../Common
+  $(EDK_SOURCE)/Foundation/Efi
+  $(EDK_SOURCE)/Foundation/Include
+  $(EDK_SOURCE)/Foundation/Efi/Include
+  $(EDK_SOURCE)/Foundation/Framework/Include
+  $(EFI_SOURCE)/$(PROJECT_SA_ROOT)
+  $(EFI_SOURCE)/$(PROJECT_SA_ROOT)/Include
+  $(EFI_SOURCE)/$(PROJECT_RAPID_START_ROOT)
+  $(EFI_SOURCE)/$(PROJECT_CPU_ROOT)/Library
+  $(EFI_SOURCE)/$(PROJECT_CPU_ROOT)/Library/OverclockingLib
+
+#
+# EDK II Glue Library utilizes some standard headers from EDK
+#
+  $(EFI_SOURCE)
+  $(EFI_SOURCE)/$(PROJECT_PCH_ROOT)
+  $(EDK_SOURCE)/Foundation
+  $(EDK_SOURCE)/Foundation/Framework
+  $(EDK_SOURCE)/Foundation/Include/IndustryStandard
+  $(EDK_SOURCE)/Foundation/Core/Dxe
+  $(EDK_SOURCE)/Foundation/Include/Pei
+  $(EDK_SOURCE)/Foundation/Library/Pei/Include
+  $(EDK_SOURCE)/Foundation/Library/Dxe/Include
+  $(EDK_SOURCE)/Foundation/Library/EdkIIGlueLib/Include
+  $(EDK_SOURCE)/Foundation/Library/EdkIIGlueLib/Include/Library
+  $(EFI_SOURCE)/$(PROJECT_PCH_ROOT)/Include
+  $(EFI_SOURCE)/$(PROJECT_PCH_ROOT)/Include/Library
+  $(EDK_SOURCE)/Foundation/Library/EdkIIGlueLib/Include/Pcd
+  $(EDK_SOURCE)/Foundation/Cpu/Pentium/Include
+  $(EFI_SOURCE)/$(PROJECT_SA_ROOT)/$(PROJECT_SA_MRC)/Pei/Source/Api
+  $(EFI_SOURCE)/$(PROJECT_SA_ROOT)/$(PROJECT_SA_MRC)/Pei/Source/Include
+  $(EFI_SOURCE)/$(PROJECT_SA_ROOT)/$(PROJECT_SA_MRC)/Pei/Source/Include/MrcRegisters
+  $(EFI_SOURCE)/$(PROJECT_SA_ROOT)/$(PROJECT_SA_MRC)/Pei
+  $(EFI_SOURCE)/$(PROJECT_CPU_ROOT)
+  $(EFI_SOURCE)/$(PROJECT_CPU_ROOT)/Include
+  $(EFI_SOURCE)/$(PROJECT_CPU_ROOT)/Include/Library
+  $(EFI_SOURCE)/$(PROJECT_ME_ROOT)
+  $(EFI_SOURCE)/$(PROJECT_ME_ROOT)/PchMeUma
+
+[libraries.common]
+  $(PROJECT_PCH_FAMILY)PpiLib
+  EdkFrameworkPpiLib
+  EdkIIGlueBaseIoLibIntrinsic
+  EdkIIGlueBaseMemoryLib
+  EdkIIGluePeiDebugLibReportStatusCode
+  EdkIIGluePeiReportStatusCodeLib
+  EdkIIGluePeiServicesLib
+  EdkIIGluePeiMemoryAllocationLib
+  EdkIIGlueBasePciExpressLib
+  EdkIIGlueBasePostCodeLibPort80
+  PeiLib
+  $(PROJECT_SA_FAMILY)PpiLib
+  SAGuidLib
+  EdkPpiLib
+  CpuPpiLib
+  CpuPlatformLib
+  EdkIIGluePeiHobLib
+  PchPlatformLib
+  OverclockingLib
+  MeLibPpi
+#
+# Uncomment all the RapidStart include directories and library if RapidStart is supported
+#
+#  RapidStartPpiLib
+
+
+[nmake.common]
+  IMAGE_ENTRY_POINT = _ModuleEntryPoint
+  DPX_SOURCE        = SaInitPeim.dxs
+#
+# Module Entry Point
+#
+  C_FLAGS = $(C_FLAGS) -D __EDKII_GLUE_MODULE_ENTRY_POINT__=SaInitPeiEntryPoint
+  C_FLAGS = $(C_FLAGS) -D __EDKII_GLUE_BASE_IO_LIB_INTRINSIC__ \
+                       -D __EDKII_GLUE_BASE_MEMORY_LIB__ \
+                       -D __EDKII_GLUE_PEI_DEBUG_LIB_REPORT_STATUS_CODE__ \
+                       -D __EDKII_GLUE_PEI_REPORT_STATUS_CODE_LIB__ \
+                       -D __EDKII_GLUE_PEI_SERVICES_LIB__ \
+                       -D __EDKII_GLUE_PEI_MEMORY_ALLOCATION_LIB__ \
+                       -D __EDKII_GLUE_BASE_PCI_LIB_PCI_EXPRESS__
diff --git a/ReferenceCode/Chipset/SystemAgent/SaInit/Pei/SaInitPeim.mak b/ReferenceCode/Chipset/SystemAgent/SaInit/Pei/SaInitPeim.mak
new file mode 100644
index 0000000..935d761
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/SaInit/Pei/SaInitPeim.mak
@@ -0,0 +1,72 @@
+#---------------------------------------------------------------------------
+#   Create SaInitPeim module
+#---------------------------------------------------------------------------
+all : SaInitPeim
+SaInitPeim : $(BUILD_DIR)\SaInitPeim.mak SaInitPeimBin
+
+$(BUILD_DIR)\SaInitPeim.mak : $(SaInitPeim_DIR)\$(@B).cif $(SaInitPeim_DIR)\$(@B).mak $(BUILD_RULES)
+  $(CIF2MAK) $(SaInitPeim_DIR)\$(@B).cif $(CIF2MAK_DEFAULTS)
+
+SaInitPeim_INCLUDES=\
+            $(INTEL_MCH_INCLUDES)\
+            $(INTEL_PCH_INCLUDES)\
+            $(EdkIIGlueLib_INCLUDES)\
+            $(PROJECT_CPU_INCLUDES)\
+            $(RAPIDSTART_INCLUDES)\
+            $(PchMeUma_INCLUDES)\
+            /I$(PROJECT_CPU_ROOT)\Library\OverclockingLib \
+
+SaInitPeim_DEFINES = $(MY_DEFINES)\
+            /D"__EDKII_GLUE_MODULE_ENTRY_POINT__=SaInitPeiEntryPoint"\
+            /D __EDKII_GLUE_BASE_LIB__ \
+            /D __EDKII_GLUE_BASE_MEMORY_LIB__ \
+            /D __EDKII_GLUE_BASE_IO_LIB_INTRINSIC__ \
+            /D __EDKII_GLUE_PEI_DEBUG_LIB_REPORT_STATUS_CODE__ \
+            /D __EDKII_GLUE_PEI_REPORT_STATUS_CODE_LIB__ \
+            /D __EDKII_GLUE_PEI_SERVICES_LIB__ \
+            /D __EDKII_GLUE_PEI_MEMORY_ALLOCATION_LIB__ \
+            /D __EDKII_GLUE_BASE_PCI_LIB_PCI_EXPRESS__ \
+
+SaInitPeim_LIB_LINKS =\
+            $(INTEL_SA_PPI_LIB) \
+            $(IntelPchPpiLib_LIB)\
+            $(EDKFRAMEWORKPPILIB) \
+            $(EdkIIGlueBaseLib_LIB)\
+            $(EdkIIGlueBaseLibIA32_LIB)\
+            $(EdkIIGlueBaseIoLibIntrinsic_LIB) \
+            $(EdkIIGluePeiDebugLibReportStatusCode_LIB) \
+            $(EdkIIGluePeiReportStatusCodeLib_LIB) \
+            $(EdkIIGluePeiServicesLib_LIB) \
+            $(EdkIIGluePeiMemoryAllocationLib_LIB) \
+            $(EdkIIGlueBasePciLibPciExpress_LIB) \
+            $(EdkIIGlueBasePciExpressLib_LIB)\
+            $(PEILIB)\
+            $(SaGuidLib_LIB)\
+            $(EdkIIGlueBasePciExpressLib_LIB)\
+            $(EdkIIGlueBasePostCodeLibPort80_LIB)\
+            $(CPU_PPI_LIB)\
+            $(CpuPlatformLib_LIB)\
+            $(PchPlatformPeiLib_LIB)\
+            $(EdkIIGluePeiHobLib_LIB)\
+            $(OcPlatformLib_LIB)\
+#
+# Uncomment all the RapidStart include directories and library if RapidStart is supported
+#
+#  RapidStartPpiLib
+            $(RapidStartPpiLib_LIB)\
+            $(MeLibPpi_LIB)
+
+SaInitPeimBin: $(SaInitPeim_LIB_LINKS)  
+            $(MAKE) /$(MAKEFLAGS) $(EDKIIGLUE_DEFAULTS)\
+            /f $(BUILD_DIR)\SaInitPeim.mak all \
+            "MY_INCLUDES=$(SaInitPeim_INCLUDES)"\
+            "MY_DEFINES=$(SaInitPeim_DEFINES)"\
+            NAME=SaInitPeim\
+            MAKEFILE=$(BUILD_DIR)\SaInitPeim.mak \
+            GUID=FD236AE7-0791-48c4-B29E-29BDEEE1A811\
+            ENTRY_POINT=_ModuleEntryPoint \
+            TYPE=PEIM \
+            EDKIIModule=PEIM\
+            DEPEX1=$(SaInitPeim_DIR)\SaInitPeim.dxs\
+            DEPEX1_TYPE=EFI_SECTION_PEI_DEPEX\
+            COMPRESS=0
diff --git a/ReferenceCode/Chipset/SystemAgent/SaInit/Pei/SaInitPeim.sdl b/ReferenceCode/Chipset/SystemAgent/SaInit/Pei/SaInitPeim.sdl
new file mode 100644
index 0000000..38ceadb
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/SaInit/Pei/SaInitPeim.sdl
@@ -0,0 +1,39 @@
+TOKEN
+  Name  = "SaInitPeim_SUPPORT"
+  Value = "1"
+  Help  = "Main switch to enable SaInitPeim support in Project"
+  TokenType = Boolean
+  TargetEQU = Yes
+  TargetMAK = Yes
+  Master = Yes
+End
+
+TOKEN
+	Name  = "SA_DEBUG_INFO"
+	Value  = "1"
+	TokenType = Boolean
+	Range  = "0-1 "
+	TargetMAK = Yes
+End
+
+ELINK
+	Name  = "/D SA_DEBUG_FLAG"
+	Parent  = "INTEL_SA_RC_FLAGS"
+	Token = "SA_DEBUG_INFO" "=" "1"
+	InvokeOrder = AfterParent
+End
+
+PATH
+  Name  = "SaInitPeim_DIR"
+End
+
+MODULE
+  File  = "SaInitPeim.mak"
+  Help  = "Includes SaInitPeim.mak to Project"
+End
+
+ELINK
+  Name  = "$(BUILD_DIR)\SaInitPeim.ffs"
+  Parent  = "FV_BB"
+  InvokeOrder = AfterParent
+End
diff --git a/ReferenceCode/Chipset/SystemAgent/SaInit/Pei/SaOcInit.c b/ReferenceCode/Chipset/SystemAgent/SaInit/Pei/SaOcInit.c
new file mode 100644
index 0000000..80a1ffb
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/SaInit/Pei/SaOcInit.c
@@ -0,0 +1,189 @@
+/** @file
+  OC System Agent Early Post initializations.
+
+@copyright
+  Copyright (c) 2011 - 2012 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement
+**/
+
+///
+/// External include files do NOT need to be explicitly specified in real EDKII
+/// environment
+///
+#if !defined(EDK_RELEASE_VERSION) || (EDK_RELEASE_VERSION < 0x00020000)
+#include "EdkIIGluePeim.h"
+#include "SaOcInit.h"
+#endif
+
+EFI_STATUS
+SaOcInit (
+  IN EFI_PEI_SERVICES            **PeiServices,
+  IN SA_PLATFORM_POLICY_PPI      *SaPlatformPolicyPpi
+  )
+/**
+  Initializes Overclocking settings in the processor.
+
+  @param[in] PeiServices - General purpose services available to every PEIM.
+  @param[in] OverclockingtConfig      Pointer to Policy protocol instance
+
+  @retval EFI_SUCCESS
+**/
+{
+  EFI_STATUS    Status;
+  OC_CAPABILITIES_ITEM OcCaps;
+  VOLTAGE_FREQUENCY_ITEM CurrentVfItem;
+  VOLTAGE_FREQUENCY_ITEM RequestedVfItem;
+  UINT32      LibStatus;
+  UINT8       DomainId;
+  BOOLEAN     VfUpdateNeeded;
+  WDT_PPI     *gWdtPei;
+
+  LibStatus = 0;
+  VfUpdateNeeded = FALSE;
+
+  if (SaPlatformPolicyPpi->OcConfig->OcSupport == 0){
+    ///
+    /// Overclocking is disabled
+    ///
+    DEBUG ((EFI_D_ERROR, "(OC) Overclocking is disabled. Bypassing SA overclocking flow.\n"));
+    return EFI_SUCCESS;
+  }
+
+  Status = EFI_SUCCESS;
+  ZeroMem(&CurrentVfItem,sizeof(CurrentVfItem));
+  ZeroMem(&RequestedVfItem,sizeof(RequestedVfItem));
+
+  //
+  // Locate WDT_PPI (ICC WDT PPI)
+  //
+  Status = PeiServicesLocatePpi (
+             &gWdtPpiGuid,
+             0,
+             NULL,
+             (VOID **) &gWdtPei
+             );
+  ASSERT_EFI_ERROR (Status);
+
+  ///
+  /// We will loop on the CPU domains to manage the voltage/frequency settings
+  ///
+  for (DomainId = OC_LIB_DOMAIN_ID_GT; DomainId <= OC_LIB_DOMAIN_ID_IOD; DomainId++) {
+    ///
+    /// Only GT, Uncore, IOA, and IOD are valid for System Agent
+    ///
+    if ((DomainId == OC_LIB_DOMAIN_ID_GT) ||(DomainId == OC_LIB_DOMAIN_ID_UNCORE) ||
+        (DomainId == OC_LIB_DOMAIN_ID_IOA) || (DomainId == OC_LIB_DOMAIN_ID_IOD)){
+      ///
+      /// Get OC Capabilities of the domain
+      ///
+      ZeroMem(&OcCaps,sizeof(OcCaps));
+      OcCaps.DomainId = DomainId;
+      Status = GetOcCapabilities(&OcCaps,&LibStatus);
+
+      if (LibStatus == OC_LIB_COMPLETION_CODE_SUCCESS){
+        ///
+        /// If any OC is supported on this domain, then proceed
+        ///
+        if (OcCaps.RatioOcSupported || OcCaps.VoltageOverridesSupported || OcCaps.VoltageOffsetSupported){
+          ///
+          /// Need to populate the user requested settings from the platform policy
+          /// to determine if OC changes are desired.
+          ///
+          ZeroMem(&CurrentVfItem,sizeof(CurrentVfItem));
+          CurrentVfItem.DomainId = DomainId;
+
+          ///
+          /// Get a copy of the current domain VfSettings from the Mailbox Library
+          ///
+          Status = GetVoltageFrequencyItem(&CurrentVfItem,&LibStatus);
+          if ((Status != EFI_SUCCESS) || (LibStatus != OC_LIB_COMPLETION_CODE_SUCCESS)){
+            continue;
+          }
+
+          ///
+          /// Populate the user requested VfSettings struct
+          ///
+          ZeroMem(&RequestedVfItem,sizeof(RequestedVfItem));
+          RequestedVfItem.DomainId = DomainId;
+          if (DomainId == OC_LIB_DOMAIN_ID_GT){
+            RequestedVfItem.VfSettings.MaxOcRatio = (UINT8) SaPlatformPolicyPpi->OcConfig->GtMaxOcTurboRatio;
+
+            ///
+            /// VoltageTarget has 2 uses and we need to update the target based
+            /// on the voltagemode requested
+            ///
+            RequestedVfItem.VfSettings.VoltageTargetMode = SaPlatformPolicyPpi->OcConfig->GtVoltageMode;
+            if (RequestedVfItem.VfSettings.VoltageTargetMode == OC_LIB_OFFSET_ADAPTIVE){
+              RequestedVfItem.VfSettings.VoltageTarget = SaPlatformPolicyPpi->OcConfig->GtExtraTurboVoltage;
+            }
+            else {
+              RequestedVfItem.VfSettings.VoltageTarget = SaPlatformPolicyPpi->OcConfig->GtVoltageOverride;
+            }
+            RequestedVfItem.VfSettings.VoltageOffset = SaPlatformPolicyPpi->OcConfig->GtVoltageOffset;
+
+            VfUpdateNeeded = (BOOLEAN)CompareMem((VOID*)&RequestedVfItem,(VOID*)&CurrentVfItem,sizeof(VOLTAGE_FREQUENCY_ITEM));
+          }
+          else if ((DomainId == OC_LIB_DOMAIN_ID_UNCORE) || (DomainId == OC_LIB_DOMAIN_ID_IOA) || (DomainId == OC_LIB_DOMAIN_ID_IOD)){
+            ///
+            /// Uncore,IOA, and IOD domains only supports voltage offset, other settings are ignored
+            ///
+            switch (DomainId) {
+              case OC_LIB_DOMAIN_ID_UNCORE:
+                RequestedVfItem.VfSettings.VoltageOffset = SaPlatformPolicyPpi->OcConfig->SaVoltageOffset;
+              break;
+
+              case OC_LIB_DOMAIN_ID_IOA:
+                RequestedVfItem.VfSettings.VoltageOffset = SaPlatformPolicyPpi->OcConfig->IoaVoltageOffset;
+              break;
+
+              case OC_LIB_DOMAIN_ID_IOD:
+                RequestedVfItem.VfSettings.VoltageOffset = SaPlatformPolicyPpi->OcConfig->IodVoltageOffset;
+              break;
+            }
+
+            if (RequestedVfItem.VfSettings.VoltageOffset != CurrentVfItem.VfSettings.VoltageOffset)
+              VfUpdateNeeded = TRUE;
+          }
+
+          if (VfUpdateNeeded){
+            VfUpdateNeeded = FALSE;
+
+            ///
+            /// Arm watchdog timer for OC changes
+            ///
+            Status = gWdtPei->ReloadAndStart (WDT_TIMEOUT_BETWEEN_PEI_DXE);
+
+            ///
+            /// Need to update the requested voltage/frequency values
+            ///
+            Status = SetVoltageFrequencyItem(RequestedVfItem,&LibStatus);
+            if ((Status != EFI_SUCCESS) || (LibStatus != OC_LIB_COMPLETION_CODE_SUCCESS)){
+              DEBUG ((EFI_D_ERROR, "(OC) Set Voltage Frequency failed. EFI Status = %X, Library Status = %X\n", Status, LibStatus));
+            }
+          }
+        }
+        else {
+          DEBUG ((EFI_D_INFO, "(OC) No OC support for this Domain = %X\n", DomainId));
+        }
+      }
+      else {
+        DEBUG ((EFI_D_ERROR, "(OC) GetOcCapabilities message failed. Library Status = %X, Domain = %X\n", LibStatus, DomainId));
+      }
+    }
+  }
+
+  return Status;
+}
diff --git a/ReferenceCode/Chipset/SystemAgent/SaInit/Pei/SaOcInit.h b/ReferenceCode/Chipset/SystemAgent/SaInit/Pei/SaOcInit.h
new file mode 100644
index 0000000..0ebff94
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/SaInit/Pei/SaOcInit.h
@@ -0,0 +1,56 @@
+/** @file
+  Describes the functions visible to the rest of the OcInit.
+
+@copyright
+  Copyright (c) 2011 - 2012 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement
+**/
+#ifndef _SA_INIT_H_
+#define _SA_INIT_H_
+
+#include "OverclockingLibrary.h"
+#include EFI_PPI_DEPENDENCY (CpuPlatformPolicy)
+#include EFI_PPI_DEPENDENCY (SaPlatformPolicy)
+#include EFI_PPI_CONSUMER (Wdt)
+
+#ifdef USE_WDT_IN_DEBUG_BIOS
+//
+// MRC takes a lot of time to execute in debug mode
+//
+#define WDT_TIMEOUT_BETWEEN_PEI_DXE 120
+#else
+#define WDT_TIMEOUT_BETWEEN_PEI_DXE 60
+#endif
+
+///
+/// Function Prototypes
+///
+EFI_STATUS
+SaOcInit (
+  IN EFI_PEI_SERVICES            **PeiServices,
+  IN SA_PLATFORM_POLICY_PPI      *SaPlatformPolicyPpi
+  )
+/**
+  Initializes Overclocking settings in the processor.
+
+  @param[in] PeiServices - General purpose services available to every PEIM.
+  @param[in] OverclockingtConfig      Pointer to Policy protocol instance
+
+  @retval EFI_SUCCESS
+**/
+;
+
+#endif
diff --git a/ReferenceCode/Chipset/SystemAgent/SaInit/Pei/SwitchableGraphicsInit.c b/ReferenceCode/Chipset/SystemAgent/SaInit/Pei/SwitchableGraphicsInit.c
new file mode 100644
index 0000000..cbb8748
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/SaInit/Pei/SwitchableGraphicsInit.c
@@ -0,0 +1,288 @@
+/** @file
+  SwitchableGraphics Pei driver.
+  This Pei driver initialize GPIO programming
+  for the platform.
+
+@copyright
+  Copyright (c) 2010 - 2012 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement
+
+**/
+
+#include "SwitchableGraphicsInit.h"
+#include EFI_GUID_DEFINITION (SaDataHob)
+
+#ifdef SG_SUPPORT
+
+/**
+  Initialize the SwitchableGraphics support (PEI).
+
+  @param[in] PeiServices          - Pointer to the PEI services table
+  @param[in] SaPlatformPolicyPpi  - SaPlatformPolicyPpi to access the GtConfig related information
+**/
+VOID
+SwitchableGraphicsInit (
+  IN EFI_PEI_SERVICES             **PeiServices,
+  IN SA_PLATFORM_POLICY_PPI       *SaPlatformPolicyPpi
+  )
+{
+  EFI_STATUS              Status;
+  PEI_STALL_PPI           *StallPpi;
+  EFI_GUID                StallPpiGuid             = PEI_STALL_PPI_GUID;
+  UINT16                  GpioAddress;
+  SA_DATA_HOB             *SaDataHob;
+  BOOLEAN                 SgDgpuPrsntGpioIsValid   = TRUE;
+  CPU_FAMILY              CpuFamilyId;
+
+  CpuFamilyId = GetCpuFamily();
+
+  ///
+  /// Get SaDataHob HOB
+  ///
+  SaDataHob = NULL;
+  SaDataHob = (SA_DATA_HOB *) GetFirstGuidHob (&gSaDataHobGuid);
+
+  if (SaDataHob != NULL) {
+    SaDataHob->SgInfo.SgMode = SaPlatformPolicyPpi->PlatformData->SgMode;
+    SaDataHob->SgInfo.PXFixedDynamicMode = SaPlatformPolicyPpi->PlatformData->PXFixedDynamicMode; // AMI_OVERRIDE_FOR ATI 5.0 Fixed/Dynamic 
+
+    ///
+    /// GPIO Assigned from policy
+    ///
+    SaDataHob->SgInfo.SgGpioSupport  = SaPlatformPolicyPpi->SgGpioData->GpioSupport;
+
+    if (SaPlatformPolicyPpi->SgGpioData->GpioSupport == 1) {
+      ///
+      /// Get GPIO Base Address
+      ///
+      GpioAddress = MmPci16 (0, 0, PCI_DEVICE_NUMBER_PCH_LPC, 0, R_PCH_LPC_GPIO_BASE) &~BIT0;
+
+      SaDataHob->SgInfo.SgDgpuPwrOK     = SaPlatformPolicyPpi->SgGpioData->SgDgpuPwrOK->Value;
+      SaDataHob->SgInfo.SgDgpuHoldRst   = SaPlatformPolicyPpi->SgGpioData->SgDgpuHoldRst->Value;
+      SaDataHob->SgInfo.SgDgpuPwrEnable = SaPlatformPolicyPpi->SgGpioData->SgDgpuPwrEnable->Value;
+      SaDataHob->SgInfo.SgDgpuPrsnt     = SaPlatformPolicyPpi->SgGpioData->SgDgpuPrsnt->Value;
+
+      ///
+      /// Set Bit7 as indicator for GPIO Active Low/High
+      ///
+      SaDataHob->SgInfo.SgDgpuPwrOK     |= (SaPlatformPolicyPpi->SgGpioData->SgDgpuPwrOK->Active     << 7);
+      SaDataHob->SgInfo.SgDgpuHoldRst   |= (SaPlatformPolicyPpi->SgGpioData->SgDgpuHoldRst->Active   << 7);
+      SaDataHob->SgInfo.SgDgpuPwrEnable |= (SaPlatformPolicyPpi->SgGpioData->SgDgpuPwrEnable->Active << 7);
+      SaDataHob->SgInfo.SgDgpuPrsnt     |= (SaPlatformPolicyPpi->SgGpioData->SgDgpuPrsnt->Active     << 7);
+
+      if (CpuFamilyId == EnumCpuHswUlt) {
+        PEI_DEBUG ((PeiServices, EFI_D_INFO, "SgDgpuPrsntGpioIsValid = FALSE\n"));
+        SgDgpuPrsntGpioIsValid = FALSE;
+      }
+
+      ///
+      /// Locate PPI stall service
+      ///
+      Status = (**PeiServices).LocatePpi (
+                                PeiServices,
+                                &StallPpiGuid,
+                                0,
+                                NULL,
+                                &StallPpi
+                                );
+      if (!EFI_ERROR (Status)) {
+        ///
+        /// if DGPU PRSNT is Disabled, it means that MXM card was not detected, and
+        /// DGPU HOLD RST must be driven high to allow the board to support a normal PEG card
+        ///
+        if (    (SgDgpuPrsntGpioIsValid)
+             && (GpioRead (PeiServices, CpuFamilyId, GpioAddress, SaDataHob->SgInfo.SgDgpuPrsnt) == GP_DISABLE)) {
+          GpioWrite (PeiServices, CpuFamilyId, GpioAddress, SaDataHob->SgInfo.SgDgpuHoldRst, GP_DISABLE);
+            ///
+            /// Set SG mode as disabled
+            ///
+            SaDataHob->SgInfo.SgMode = SgModeDisabled;
+        } else {
+          ///
+          /// DGPU PRSNT Enabled. MXM is present.
+          ///      If PEG Mode or SG Muxless
+          ///              Power on MXM
+          ///              Configure GPIOs to drive MXM in PEG mode or SG Muxless
+          ///      else
+          ///              Do Nothing
+          ///
+          if ((SaPlatformPolicyPpi->PlatformData->SgMode == SgModeMuxless) ||
+              (SaPlatformPolicyPpi->PlatformData->SgMode == SgModeDgpu)) {
+            PEI_DEBUG ((PeiServices, EFI_D_INFO, "Configure GPIOs for driving the dGPU.\n"));
+            ///
+            ///  Drive DGPU HOLD RST Enable to make sure we hold reset
+            ///
+            GpioWrite (PeiServices, CpuFamilyId, GpioAddress, SaDataHob->SgInfo.SgDgpuHoldRst, GP_ENABLE);
+            ///
+            /// wait 100ms
+            ///
+            StallPpi->Stall (
+                        PeiServices,
+                        StallPpi,
+                        SG_DELAY_HOLD_RST
+                        );
+
+            ///
+            /// Drive DGPU PWR EN to Power On MXM
+            ///
+            GpioWrite (PeiServices, CpuFamilyId, GpioAddress, SaDataHob->SgInfo.SgDgpuPwrEnable, GP_ENABLE);
+
+            ///
+            /// wait 300ms
+            ///
+            StallPpi->Stall (
+                        PeiServices,
+                        StallPpi,
+                        SG_DELAY_PWR_ENABLE
+                        );
+
+            ///
+            /// Drive DGPU HOLD RST Disabled to remove reset
+            ///
+            GpioWrite (PeiServices, CpuFamilyId, GpioAddress, SaDataHob->SgInfo.SgDgpuHoldRst, GP_DISABLE);
+
+            ///
+            /// wait 100ms
+            ///
+            StallPpi->Stall (
+                      PeiServices,
+                      StallPpi,
+                      SG_DELAY_HOLD_RST
+                      );
+          }
+        }
+      }
+    }
+  }
+  ///
+  /// Program SubsystemID for IGFX
+  ///
+  PEI_DEBUG ((PeiServices, EFI_D_INFO, "Program SDID [Subsystem ID] for IGFX: 0x%x\n", SaPlatformPolicyPpi->PlatformData->SgSubSystemId));
+  McD2PciCfg16Or (PCI_SID, SaPlatformPolicyPpi->PlatformData->SgSubSystemId);
+
+}
+
+/**
+  SG GPIO Read
+
+  @param[in] PeiServices - General purpose services available to every PEIM
+  @param[in] CpuFamilyId - Specifies the CPU family
+  @param[in] GpioAddress - GPIO base address
+  @param[in] Value       - PCH GPIO number
+
+  @retval GPIO read value (0/1)
+**/
+BOOLEAN
+GpioRead (
+  EFI_PEI_SERVICES          **PeiServices,
+  CPU_FAMILY                CpuFamilyId,
+  IN UINT16                 GpioAddress,
+  IN UINT8                  Value
+  )
+{
+  BOOLEAN Active;
+  UINT16  BitOffset=0;
+  UINT32  Data;
+
+  Active = (BOOLEAN) (Value >> 7);
+  Value &= 0x7F;
+
+  ASSERT (GpioAddress != 0);
+
+  if (CpuFamilyId == EnumCpuHswUlt) {
+      GpioAddress += R_PCH_GP_N_CONFIG0 + (Value * 0x08);
+      BitOffset = 30; //GPI_LVL
+  } else {
+    if (Value < 0x20) {
+      GpioAddress += R_PCH_GPIO_LVL;
+      BitOffset = Value;
+    } else if (Value < 0x40) {
+      GpioAddress += R_PCH_GPIO_LVL2;
+      BitOffset = Value - 0x20;
+    } else {
+      GpioAddress += R_PCH_GPIO_LVL3;
+      BitOffset = Value - 0x40;
+    }
+  }
+
+  Data = IoRead32 (GpioAddress);
+  Data >>= BitOffset;
+
+  if (Active == 0) {
+    Data = ~Data;
+  }
+
+  return (BOOLEAN) (Data & 0x1);
+}
+
+/**
+  SG GPIO Write
+
+  @param[in] PeiServices - General purpose services available to every PEIM
+  @param[in] CpuFamilyId - Specifies the CPU family
+  @param[in] GpioAddress - GPIO base address
+  @param[in] Value       - PCH GPIO number
+  @param[in] Level       - Write SG GPIO value (0/1)
+
+  @retval none
+**/
+VOID
+GpioWrite (
+  EFI_PEI_SERVICES          **PeiServices,
+  CPU_FAMILY                CpuFamilyId,
+  IN UINT16                 GpioAddress,
+  IN UINT8                  Value,
+  IN BOOLEAN                Level
+  )
+{
+  BOOLEAN Active;
+  UINT32  Data;
+  UINT16  BitOffset=0;
+
+  Active = (BOOLEAN) (Value >> 7);
+  Value &= 0x7F;
+
+  if (Active == 0) {
+    Level = (~Level) & 0x1;
+  }
+
+  ASSERT (GpioAddress != 0);
+
+  if (CpuFamilyId == EnumCpuHswUlt) {
+      GpioAddress += R_PCH_GP_N_CONFIG0 + (Value * 0x08);
+      BitOffset = 31; //GPO_LVL
+  } else {
+    if (Value < 0x20) {
+      GpioAddress += R_PCH_GPIO_LVL;
+      BitOffset = Value;
+    } else if (Value < 0x40) {
+      GpioAddress += R_PCH_GPIO_LVL2;
+      BitOffset = Value - 0x20;
+    } else {
+      GpioAddress += R_PCH_GPIO_LVL3;
+      BitOffset = Value - 0x40;
+    }
+  }
+
+  Data = IoRead32 (GpioAddress);
+  Data &= ~(0x1 << BitOffset);
+  Data |= (Level << BitOffset);
+
+  IoWrite32 (GpioAddress, Data);
+  return ;
+}
+
+#endif //SG_SUPPORT
\ No newline at end of file
diff --git a/ReferenceCode/Chipset/SystemAgent/SaInit/Pei/SwitchableGraphicsInit.h b/ReferenceCode/Chipset/SystemAgent/SaInit/Pei/SwitchableGraphicsInit.h
new file mode 100644
index 0000000..7126b19
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/SaInit/Pei/SwitchableGraphicsInit.h
@@ -0,0 +1,93 @@
+/** @file
+  Header file for the SwitchableGraphics Pei driver.
+
+@copyright
+  Copyright (c) 2010 - 2012 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement
+**/
+
+#ifndef _SWITCHABLE_GRAPHICS_PEI_H_
+#define _SWITCHABLE_GRAPHICS_PEI_H_
+
+#if !defined(EDK_RELEASE_VERSION) || (EDK_RELEASE_VERSION < 0x00020000)
+#include "EdkIIGluePeim.h"
+#include "EdkIIGlueIoLib.h"
+#endif
+
+#include "CpuRegs.h"
+#include "CpuPlatformLib.h"
+
+#include "PchAccess.h"
+#include "SaAccess.h"
+
+#include EFI_PPI_DEPENDENCY (SaPlatformPolicy)
+#include EFI_PPI_DEPENDENCY (Stall)
+
+#ifndef FALSE
+#define FALSE 0
+#endif
+
+#ifndef HIGH
+#define HIGH  1
+#endif
+
+#ifndef LOW
+#define LOW 0
+#endif
+
+#define SG_DELAY_HOLD_RST    100 * STALL_ONE_MILLI_SECOND
+#define SG_DELAY_PWR_ENABLE  300 * STALL_ONE_MILLI_SECOND
+
+/**
+  SG GPIO Write
+
+  @param[in] PeiServices - General purpose services available to every PEIM
+  @param[in] CpuFamilyId - Specifies the CPU family
+  @param[in] GpioAddress - GPIO base address
+  @param[in] Value       - PCH GPIO number
+  @param[in] Level       - Write SG GPIO value (0/1)
+
+  @retval none
+**/
+VOID
+GpioWrite (
+  EFI_PEI_SERVICES          **PeiServices,
+  CPU_FAMILY                CpuFamilyId,
+  IN UINT16                 GpioAddress,
+  IN UINT8                  Value,
+  IN BOOLEAN                Level
+  )
+;
+
+/**
+  SG GPIO Read
+
+  @param[in] PeiServices - General purpose services available to every PEIM
+  @param[in] CpuFamilyId - Specifies the CPU family
+  @param[in] GpioAddress - GPIO base address
+  @param[in] Value       - PCH GPIO number
+
+  @retval GPIO read value (0/1)
+**/
+BOOLEAN
+GpioRead (
+  EFI_PEI_SERVICES          **PeiServices,
+  CPU_FAMILY                CpuFamilyId,
+  IN UINT16                 GpioAddress,
+  IN UINT8                  Value
+  )
+;
+#endif
diff --git a/ReferenceCode/Chipset/SystemAgent/SaInit/Smm/SaLateInitSmm.c b/ReferenceCode/Chipset/SystemAgent/SaInit/Smm/SaLateInitSmm.c
new file mode 100644
index 0000000..45ce0af
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/SaInit/Smm/SaLateInitSmm.c
@@ -0,0 +1,204 @@
+/** @file
+  This SMM driver will handle SA relevant late initialization
+
+@copyright
+  Copyright (c) 2012 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement
+**/
+
+///
+/// External include files do NOT need to be explicitly specified in real EDKII
+/// environment
+///
+#if !defined(EDK_RELEASE_VERSION) || (EDK_RELEASE_VERSION < 0x00020000)
+#include "SaBuildFlags.h"
+#include "EdkIIGlueDxe.h"
+#include "SaLateInitSmm.h"
+#include "SaRegs.h"
+#include "SaAccess.h"
+#include "PchAccess.h"
+#include "CpuIA32.h"
+#include "SaPcieLib.h"
+#include EFI_PROTOCOL_DEPENDENCY (SmmIoTrapDispatch)
+#include EFI_GUID_DEFINITION (SaDataHob)
+#endif
+
+typedef enum {
+  EnumSaSmiCallbackForMaxPayLoad,
+  EnumSaSmiCallbackForSecurityLock,
+  EnumSaSmiCallbackForLateInit,
+  EnumSaSmiCallbackForS3resume,
+  EnumSaSmiCallbackMax
+} SMI_OPERATION;
+
+UINT8                           mSaSmiCallbackPhase = EnumSaSmiCallbackForMaxPayLoad;
+
+/**
+  A SMI callback to do SA relevant late initialization
+
+  @param[in] DispatchHandle  - The handle of this callback, obtained when registering
+  @param[in] DispatchContext - Pointer to the EFI_SMM_IO_TRAP_DISPATCH_CALLBACK_CONTEXT
+
+  @retval None
+**/
+VOID
+EFIAPI
+SaIoTrapSmiCallback (
+  IN  EFI_HANDLE                                  DispatchHandle,
+  IN  EFI_SMM_IO_TRAP_DISPATCH_CALLBACK_CONTEXT   *CallbackContext
+  )
+{
+
+  if (mSaSmiCallbackPhase == EnumSaSmiCallbackMax) {
+    return;
+  }
+  if (mSaSmiCallbackPhase == EnumSaSmiCallbackForMaxPayLoad) {
+    SaPcieEnumCallback ();
+    ///
+    /// Switch to next phase
+    ///
+    mSaSmiCallbackPhase = EnumSaSmiCallbackForSecurityLock;
+  } else if (mSaSmiCallbackPhase == EnumSaSmiCallbackForSecurityLock) {
+    ///
+    /// Save platform registers including IGFX BAR & COMMAND registers and PAM
+    ///
+    SaSaveRestorePlatform (TRUE);
+    SaSecurityLock ();
+    ///
+    /// Switch to next phase
+    ///
+    mSaSmiCallbackPhase = EnumSaSmiCallbackForLateInit;
+  } else if (mSaSmiCallbackPhase == EnumSaSmiCallbackForLateInit) {
+    ///
+    /// Expected to execute in ReadyToBoot point (after OROM)
+    ///
+    SaPcieConfigAfterOpRom ();
+    ///
+    /// Switch to next phase
+    ///
+    mSaSmiCallbackPhase = EnumSaSmiCallbackForS3resume;
+  } else if (mSaSmiCallbackPhase == EnumSaSmiCallbackForS3resume) {
+    ///
+    /// Expected to execute in end of S3 resume flow
+    ///
+    SaS3ResumeCallback ();
+  }
+}
+
+/**
+  Initializes the SA SMM handler
+
+  @param[in] ImageHandle - The image handle of Wake On Lan driver
+  @param[in] SystemTable - The standard EFI system table
+
+  @retval EFI_SUCCESS    - SA SMM handler was installed or not necessary
+  @retval EFI_NOT_FOUND  - DxePlatformSaPolicy not found
+**/
+EFI_STATUS
+SaLateInitSmmEntryPoint (
+  IN EFI_HANDLE        ImageHandle,
+  IN EFI_SYSTEM_TABLE  *SystemTable
+  )
+{
+  EFI_STATUS                                Status;
+  EFI_SMM_IO_TRAP_DISPATCH_PROTOCOL         *PchIoTrap;
+  EFI_HANDLE                                PchIoTrapHandle;
+  EFI_SMM_IO_TRAP_DISPATCH_REGISTER_CONTEXT PchIoTrapContext;
+  SA_DATA_HOB                               *SaDataHob;
+  DXE_PLATFORM_SA_POLICY_PROTOCOL           *DxePlatformSaPolicy;
+  BOOLEAN                                   InitPcieAspmAfterOprom;
+  EFI_PHYSICAL_ADDRESS                      IotrapAddress;
+
+  DEBUG ((EFI_D_INFO, "SaLateInitSmmEntryPoint()\n"));
+
+  SaDataHob = NULL;
+  SaDataHob = (SA_DATA_HOB *)GetFirstGuidHob (&gSaDataHobGuid);
+  Status = EFI_NOT_FOUND;
+  if ((SaDataHob != NULL)) {
+    ///
+    /// Locate the PCH Trap dispatch protocol
+    ///
+    Status = gBS->LocateProtocol (&gEfiSmmIoTrapDispatchProtocolGuid, NULL, (VOID **) &PchIoTrap);
+    ASSERT_EFI_ERROR (Status);
+    if ((Status == EFI_SUCCESS) && (SaDataHob->SaIotrapSmiAddress != 0)) {
+      ///
+      /// Allocate 16 byte range from GCD for this IO trap address
+      ///
+      IotrapAddress = SaDataHob->SaIotrapSmiAddress;
+      DEBUG ((EFI_D_INFO, "Iotrap address=%X\n", SaDataHob->SaIotrapSmiAddress));
+      Status = gDS->AllocateIoSpace (
+                      EfiGcdAllocateAddress,
+                      EfiGcdIoTypeIo,
+                      0,
+                      0x10,
+                      &IotrapAddress,
+                      ImageHandle,
+                      NULL
+                      );
+      ASSERT_EFI_ERROR (Status);
+      if (Status == EFI_SUCCESS) {
+        PchIoTrapContext.Type     = ReadWriteTrap;
+        PchIoTrapContext.Length   = 4;
+        PchIoTrapContext.Address  = SaDataHob->SaIotrapSmiAddress;
+        PchIoTrapContext.Context  = NULL;
+        PchIoTrapContext.MergeDisable = FALSE;
+        Status = PchIoTrap->Register (
+                              PchIoTrap,
+                              SaIoTrapSmiCallback,
+                              &PchIoTrapContext,
+                              &PchIoTrapHandle
+                              );
+        ASSERT_EFI_ERROR (Status);
+        if (Status == EFI_SUCCESS) {
+          InitPcieAspmAfterOprom = SaDataHob->InitPcieAspmAfterOprom;
+#if SA_PCIE_ASPM_IN_DXE == 0
+          ///
+          /// There is no DXE ASPM code so always executes SMM code
+          ///
+          InitPcieAspmAfterOprom = 1;
+#endif
+          if (InitPcieAspmAfterOprom == 1) {
+            ///
+            /// Initialize module global variables - Stepping ID and Platform Policy for runtime SMI handler
+            /// Get the platform setup policy.
+            ///
+            Status = gBS->LocateProtocol (&gDxePlatformSaPolicyGuid, NULL, (VOID **) &DxePlatformSaPolicy);
+            ASSERT_EFI_ERROR (Status);
+            if (DxePlatformSaPolicy != NULL) {
+              SaPcieInitPolicy (DxePlatformSaPolicy);
+            }
+          } else {
+            ///
+            /// InitPcieAspmAfterOprom was not available or disabled, make this SMI handler directly return.
+            ///
+            mSaSmiCallbackPhase = EnumSaSmiCallbackMax;
+          }
+        }
+      }
+    }
+  }
+
+  ///
+  /// For security consideration, if this SMM driver was compiled/executed, the IOTRAP SMI handler must be registered successfully.
+  /// If not, hang system here
+  ///
+  if (Status != EFI_SUCCESS) {
+    DEBUG ((EFI_D_ERROR, "Failed to register SaIotrapSmiCallback! System halt!\n"));
+    EFI_DEADLOOP ();
+  }
+
+  return EFI_SUCCESS;
+}
diff --git a/ReferenceCode/Chipset/SystemAgent/SaInit/Smm/SaLateInitSmm.cif b/ReferenceCode/Chipset/SystemAgent/SaInit/Smm/SaLateInitSmm.cif
new file mode 100644
index 0000000..6fbd4ba
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/SaInit/Smm/SaLateInitSmm.cif
@@ -0,0 +1,13 @@
+<component>
+	name = "SaLateInitSmm"
+	category = ModulePart
+	LocalRoot = "ReferenceCode\Chipset\SystemAgent\SaInit\Smm\"
+	RefName = "SaLateInitSmm"
+[files]
+"SaLateInitSmm.sdl"	
+"SaLateInitSmm.mak"	
+"SaLateInitSmm.h"	
+"SaLateInitSmm.c"	
+"SaLateInitSmm.dxs"	
+"SaLateInitSmm.inf"	
+<endComponent>
diff --git a/ReferenceCode/Chipset/SystemAgent/SaInit/Smm/SaLateInitSmm.dxs b/ReferenceCode/Chipset/SystemAgent/SaInit/Smm/SaLateInitSmm.dxs
new file mode 100644
index 0000000..8890d7d
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/SaInit/Smm/SaLateInitSmm.dxs
@@ -0,0 +1,45 @@
+/** @file
+  Dependency expression source file.
+
+@copyright
+  Copyright (c)  2012 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains a 'Sample Driver' and is licensed as such
+  under the terms of your license agreement with Intel or your
+  vendor.  This file may be modified by the user, subject to
+  the additional terms of the license agreement
+
+**/
+ 
+
+//
+// Common for R8 and R9 codebase
+//
+#include "AutoGen.h"
+#include "DxeDepex.h"
+
+//
+// BUILD_WITH_GLUELIB and BUILD_WITH_EDKII_GLUE_LIB are both "defined" in R8 codebase;
+// BUILD_WITH_EDKII_GLUE_LIB is defined in Edk-Dev-Snapshot-20070228 and later version
+// BUILD_WITH_GLUELIB and BUILD_WITH_EDKII_GLUE_LIB are "not defined" in R9 codebase.
+//
+#if defined (BUILD_WITH_GLUELIB) || defined (BUILD_WITH_EDKII_GLUE_LIB)
+#include "EfiDepex.h"
+
+#include EFI_PROTOCOL_DEPENDENCY (SmmBase)
+#include EFI_PROTOCOL_DEPENDENCY (SmmIoTrapDispatch)
+#include EFI_PROTOCOL_DEPENDENCY (SaPlatformPolicy)
+#endif
+
+DEPENDENCY_START
+  EFI_SMM_BASE_PROTOCOL_GUID AND
+  EFI_SMM_IO_TRAP_DISPATCH_PROTOCOL_GUID AND
+  DXE_PLATFORM_SA_POLICY_GUID
+DEPENDENCY_END
diff --git a/ReferenceCode/Chipset/SystemAgent/SaInit/Smm/SaLateInitSmm.h b/ReferenceCode/Chipset/SystemAgent/SaInit/Smm/SaLateInitSmm.h
new file mode 100644
index 0000000..71ff7e4
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/SaInit/Smm/SaLateInitSmm.h
@@ -0,0 +1,39 @@
+/** @file
+  Header file for SA SMM Handler
+
+@copyright
+  Copyright (c) 2012 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement
+**/
+
+#ifndef _SaLateInitSmm_H_
+#define _SaLateInitSmm_H_
+
+///
+/// External include files do NOT need to be explicitly specified in real EDKII
+/// environment
+///
+#if !defined(EDK_RELEASE_VERSION) || (EDK_RELEASE_VERSION < 0x00020000)
+#include "EdkIIGlueDxe.h"
+///
+/// Driver Consumed Protocol Prototypes
+///
+#include EFI_PROTOCOL_DEPENDENCY (SmmBase)
+#include EFI_PROTOCOL_DEPENDENCY (SmmIchnDispatch)
+#include EFI_PROTOCOL_DEPENDENCY (SaPlatformPolicy)
+
+#endif
+#endif
diff --git a/ReferenceCode/Chipset/SystemAgent/SaInit/Smm/SaLateInitSmm.inf b/ReferenceCode/Chipset/SystemAgent/SaInit/Smm/SaLateInitSmm.inf
new file mode 100644
index 0000000..3fd8846
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/SaInit/Smm/SaLateInitSmm.inf
@@ -0,0 +1,97 @@
+## @file
+#  Component description file for the SA late initialization SMM module.
+#
+#@copyright
+#  Copyright (c)  2012 Intel Corporation. All rights reserved
+#  This software and associated documentation (if any) is furnished
+#  under a license and may only be used or copied in accordance
+#  with the terms of the license. Except as permitted by such
+#  license, no part of this software or documentation may be
+#  reproduced, stored in a retrieval system, or transmitted in any
+#  form or by any means without the express written consent of
+#  Intel Corporation.
+#
+#  This file contains a 'Sample Driver' and is licensed as such
+#  under the terms of your license agreement with Intel or your
+#  vendor.  This file may be modified by the user, subject to
+#  the additional terms of the license agreement
+#
+
+[defines]
+BASE_NAME            = SaLateInitSmm
+FILE_GUID            = 2D1E361C-7B3F-4d15-8B1F-66E551FABDC7
+COMPONENT_TYPE       = RT_DRIVER
+
+[sources.common]
+  SaLateInitSmm.c
+  SaLateInitSmm.h
+
+#
+# Edk II Glue Driver Entry Point
+#
+  EdkIIGlueSmmDriverEntryPoint.c
+
+[includes.common]
+  $(EDK_SOURCE)/Foundation
+  $(EDK_SOURCE)/Foundation/Efi
+  $(EDK_SOURCE)/Foundation/Framework
+  $(EDK_SOURCE)/Foundation/Include
+  $(EDK_SOURCE)/Foundation/Efi/Include
+  $(EDK_SOURCE)/Foundation/Framework/Include
+  $(EDK_SOURCE)/Foundation/Include/IndustryStandard
+  $(EDK_SOURCE)/Foundation/Core/Dxe
+  $(EDK_SOURCE)/Foundation/Core/Dxe/Include
+  $(EDK_SOURCE)/Foundation/Library/Dxe/Include
+  $(EDK_SOURCE)/Foundation/Library/EdkIIGlueLib/Include/Pcd
+  $(EDK_SOURCE)/Foundation/Library/EdkIIGlueLib/Include
+  $(EDK_SOURCE)/Foundation/Library/EdkIIGlueLib/Include/Library
+  $(EDK_SOURCE)/Foundation/Cpu/Pentium/Include
+  $(EFI_SOURCE)/$(PROJECT_SA_ROOT)/Include
+  $(EFI_SOURCE)/$(PROJECT_SA_ROOT)
+  $(EFI_SOURCE)/$(PROJECT_SA_ROOT)/Library/SaPcieLib/Common
+  $(EFI_SOURCE)/$(PROJECT_PCH_ROOT)/Include
+  $(EFI_SOURCE)/$(PROJECT_PCH_ROOT)
+
+
+[libraries.common]
+  EdkProtocolLib
+  ArchProtocolLib
+  EdkFrameworkProtocolLib
+  EdkIIGlueBaseLib
+  EdkIIGlueBaseIoLibIntrinsic
+  EdkIIGlueBaseMemoryLib
+  EdkIIGlueDxeMemoryAllocationLib
+  EdkIIGlueDxeDebugLibReportStatusCode
+  EdkIIGlueSmmRuntimeDxeReportStatusCodeLib
+  EdkIIGlueBasePciLibPciExpress
+  EdkIIGlueUefiLib
+  EdkIIGlueUefiBootServicesTableLib
+  EdkIIGlueDxeServicesTableLib
+  EdkIIGlueUefiRuntimeServicesTableLib
+  EdkIIGlueUefiDevicePathLib
+  EfiProtocolLib
+  $(PROJECT_SA_FAMILY)ProtocolLib
+  SaGuidLib
+  EdkIIGlueDxeHobLib
+  CpuPlatformLib
+  SaPcieSmmLib
+  $(PROJECT_PCH_FAMILY)ProtocolLib
+
+[nmake.common]
+  IMAGE_ENTRY_POINT=_ModuleEntryPoint
+  DPX_SOURCE=SaLateInitSmm.dxs
+
+  C_FLAGS = $(C_FLAGS) -D __EDKII_GLUE_MODULE_ENTRY_POINT__=SaLateInitSmmEntryPoint
+  C_FLAGS = $(C_FLAGS) -D __EDKII_GLUE_BASE_LIB__ \
+                       -D __EDKII_GLUE_BASE_IO_LIB_INTRINSIC__ \
+                       -D __EDKII_GLUE_BASE_MEMORY_LIB__ \
+                       -D __EDKII_GLUE_DXE_MEMORY_ALLOCATION_LIB__ \
+                       -D __EDKII_GLUE_DXE_DEBUG_LIB_REPORT_STATUS_CODE__ \
+                       -D __EDKII_GLUE_SMM_RUNTIME_DXE_REPORT_STATUS_CODE_LIB__ \
+                       -D __EDKII_GLUE_UEFI_LIB__\
+                       -D __EDKII_GLUE_DXE_SERVICES_TABLE_LIB__ \
+                       -D __EDKII_GLUE_UEFI_BOOT_SERVICES_TABLE_LIB__ \
+                       -D __EDKII_GLUE_UEFI_RUNTIME_SERVICES_TABLE_LIB__ \
+                       -D __EDKII_GLUE_UEFI_DEVICE_PATH_LIB__ \
+                       -D __EDKII_GLUE_BASE_PCI_LIB_PCI_EXPRESS__ \
+                       -D __EDKII_GLUE_DXE_HOB_LIB__
diff --git a/ReferenceCode/Chipset/SystemAgent/SaInit/Smm/SaLateInitSmm.mak b/ReferenceCode/Chipset/SystemAgent/SaInit/Smm/SaLateInitSmm.mak
new file mode 100644
index 0000000..dfa035d
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/SaInit/Smm/SaLateInitSmm.mak
@@ -0,0 +1,96 @@
+#*************************************************************************
+#*************************************************************************
+#**                                                                     **
+#**        (C)Copyright 1985-2011, American Megatrends, Inc.            **
+#**                                                                     **
+#**                       All Rights Reserved.                          **
+#**                                                                     **
+#**      5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093           **
+#**                                                                     **
+#**                       Phone: (770)-246-8600                         **
+#**                                                                     **
+#*************************************************************************
+#*************************************************************************
+
+#---------------------------------------------------------------------------
+#   Create SaLateInitSmm Driver
+#---------------------------------------------------------------------------
+EDK : SaLateInitSmm
+SaLateInitSmm : $(BUILD_DIR)\SaLateInitSmm.mak SaLateInitSmmBin
+
+
+$(BUILD_DIR)\SaLateInitSmm.mak : $(SaLateInitSmm_DIR)\$(@B).cif $(SaLateInitSmm_DIR)\$(@B).mak $(BUILD_RULES)
+  $(CIF2MAK) $(SaLateInitSmm_DIR)\$(@B).cif $(CIF2MAK_DEFAULTS)
+
+SaLateInitSmm_INCLUDES=\
+        $(EdkIIGlueLib_INCLUDES)\
+        $(INTEL_MCH_INCLUDES)\
+        $(INTEL_PCH_INCLUDES)\
+        /I$(INTEL_SYSTEM_AGENT_DIR)\Library\SaPcieLib\Common\
+
+SaLateInitSmm_DEFINES = $(MY_DEFINES)\
+      /D"__EDKII_GLUE_MODULE_ENTRY_POINT__=SaLateInitSmmEntryPoint"\
+      /D __EDKII_GLUE_BASE_LIB__ \
+      /D __EDKII_GLUE_BASE_IO_LIB_INTRINSIC__ \
+      /D __EDKII_GLUE_BASE_MEMORY_LIB__ \
+      /D __EDKII_GLUE_DXE_MEMORY_ALLOCATION_LIB__ \
+      /D __EDKII_GLUE_DXE_DEBUG_LIB_REPORT_STATUS_CODE__ \
+      /D __EDKII_GLUE_SMM_RUNTIME_DXE_REPORT_STATUS_CODE_LIB__ \
+      /D __EDKII_GLUE_UEFI_LIB__ \
+      /D __EDKII_GLUE_DXE_SERVICES_TABLE_LIB__ \
+      /D __EDKII_GLUE_UEFI_BOOT_SERVICES_TABLE_LIB__ \
+      /D __EDKII_GLUE_UEFI_RUNTIME_SERVICES_TABLE_LIB__ \
+      /D __EDKII_GLUE_UEFI_DEVICE_PATH_LIB__ \
+      /D __EDKII_GLUE_BASE_PCI_LIB_PCI_EXPRESS__ \
+      /D __EDKII_GLUE_DXE_HOB_LIB__ \
+
+SaLateInitSmm_LIB_LINKS =\
+            $(EDKPROTOCOLLIB)\
+            $(ArchProtocolLib)\
+            $(EDKFRAMEWORKPROTOCOLLIB)\
+            $(EdkIIGlueBaseLib_LIB)\
+            $(EdkIIGlueBaseIoLibIntrinsic_LIB)\
+            $(EdkIIGlueBaseMemoryLib_LIB)\
+            $(EdkIIGlueDxeMemoryAllocationLib_LIB)\
+            $(EdkIIGlueDxeDebugLibReportStatusCode_LIB)\
+            $(EdkIIGlueSmmRuntimeDxeReportStatusCodeLib_LIB)\
+            $(EdkIIGlueBasePciLibPciExpress_LIB)\
+            $(EdkIIGlueUefiLib_LIB)\
+            $(EdkIIGlueSmmFirmwarePerformanceLib_LIB)\
+            $(EdkIIGlueDxeServicesTableLib_LIB)\
+            $(EdkIIGlueUefiRuntimeServicesTableLib_LIB)\
+            $(EdkIIGlueUefiDevicePathLib_LIB)\
+            $(EFIPROTOCOLLIB)\
+            $(INTEL_SA_PROTOCOL_LIB)\
+            $(SaGuidLib_LIB)\
+            $(EdkIIGlueDxeHobLib_LIB)\
+            $(CpuPlatformLib_LIB)\
+            $(PchPlatformDxeLib_LIB)\
+            $(SaPcieSmmLib_LIB)\
+            $(INTEL_PCH_PROTOCOL_LIB)\
+
+SaLateInitSmmBin: $(COMPILERSTUB) $(SaLateInitSmm_LIB_LINKS)
+            $(MAKE) /$(MAKEFLAGS) $(EDKIIGLUE_DEFAULTS)\
+            /f  $(BUILD_DIR)\SaLateInitSmm.mak all \
+            "MY_INCLUDES=$(SaLateInitSmm_INCLUDES)" \
+            "MY_DEFINES=$(SaLateInitSmm_DEFINES)" \
+            GUID=2D1E361C-7B3F-4d15-8B1F-66E551FABDC7\
+            ENTRY_POINT=_ModuleEntryPoint \
+            TYPE=BS_DRIVER\
+            EDKIIModule=SMMDRIVER\
+            DEPEX1=$(SaLateInitSmm_DIR)\SaLateInitSmm.dxs\
+            DEPEX1_TYPE=EFI_SECTION_DXE_DEPEX  \
+            COMPRESS=1
+#*************************************************************************
+#*************************************************************************
+#**                                                                     **
+#**        (C)Copyright 1985-2011, American Megatrends, Inc.            **
+#**                                                                     **
+#**                       All Rights Reserved.                          **
+#**                                                                     **
+#**      5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093           **
+#**                                                                     **
+#**                       Phone: (770)-246-8600                         **
+#**                                                                     **
+#*************************************************************************
+#*************************************************************************
diff --git a/ReferenceCode/Chipset/SystemAgent/SaInit/Smm/SaLateInitSmm.sdl b/ReferenceCode/Chipset/SystemAgent/SaInit/Smm/SaLateInitSmm.sdl
new file mode 100644
index 0000000..285ea16
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/SaInit/Smm/SaLateInitSmm.sdl
@@ -0,0 +1,26 @@
+TOKEN
+	Name  = "SaLateInitSmm_SUPPORT"
+	Value  = "1"
+	Help  = "Main switch to enable SaLateInitSmm support in Project"
+	TokenType = Boolean
+	TargetEQU = Yes
+	TargetMAK = Yes
+	TargetH = Yes
+	Master = Yes
+End
+
+PATH
+	Name  = "SaLateInitSmm_DIR"
+	Help  = "SaLateInitSmm file source directory"
+End
+
+MODULE
+	Help  = "Includes SaLateInitSmm.mak to Project"
+	File  = "SaLateInitSmm.mak"
+End
+
+ELINK
+	Name  = "$(BUILD_DIR)\SaLateInitSmm.ffs"
+	Parent  = "FV_MAIN"
+	InvokeOrder = AfterParent
+End
\ No newline at end of file
diff --git a/ReferenceCode/Chipset/SystemAgent/SampleCode/Include/AcpiBuild.dsc b/ReferenceCode/Chipset/SystemAgent/SampleCode/Include/AcpiBuild.dsc
new file mode 100644
index 0000000..cc3fb3d
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/SampleCode/Include/AcpiBuild.dsc
@@ -0,0 +1,96 @@
+## @file
+#  Build description file for building ASL and ACT file types used in ACPI tables
+#  You should not put platform details, like how to build DSDT, SSDT, or how to
+#  package the ACPI tables into a data file in this build.  This should be platform 
+#  neutral code only.
+#
+#@copyright
+#  Copyright (c)  1999 - 2012 Intel Corporation. All rights reserved
+#  This software and associated documentation (if any) is furnished
+#  under a license and may only be used or copied in accordance
+#  with the terms of the license. Except as permitted by such
+#  license, no part of this software or documentation may be
+#  reproduced, stored in a retrieval system, or transmitted in any
+#  form or by any means without the express written consent of
+#  Intel Corporation.
+#
+#  This file contains a 'Sample Driver' and is licensed as such
+#  under the terms of your license agreement with Intel or your
+#  vendor.  This file may be modified by the user, subject to
+#  the additional terms of the license agreement
+#
+
+[=============================================================================]
+[Compile.Ia32.act,Compile.x64.act]
+#
+# Instructions to create ACPI table sections out of ACPI table C source files.
+#
+
+#/*++
+#
+# If it already exists, then include the dependency list file for this
+# source file. If it doesn't exist, then this is a clean build and the
+# dependency file will get created below and the source file will get
+# compiled. Don't do any of this if NO_MAKEDEPS is defined.
+#
+#--*/
+!IF ("$(NO_MAKEDEPS)" == "")
+
+!IF EXIST($(DEST_DIR)\$(FILE).dep)
+!INCLUDE $(DEST_DIR)\$(FILE).dep
+!ENDIF
+
+#
+# This is how to create the dependency file.
+#
+DEP_FILE = $(DEST_DIR)\$(FILE).dep
+
+$(DEP_FILE) : $(SOURCE_FILE_NAME)
+  $(MAKEDEPS) -ignorenotfound -f $(SOURCE_FILE_NAME) -q -target \
+    $(DEST_DIR)\$(FILE).obj \
+    -o $(DEP_FILE) $(INC)
+
+!ENDIF
+
+#
+# Compile the file
+#
+$(DEST_DIR)\$(FILE).obj : $(SOURCE_FILE_NAME) $(INC_DEPS) $(DEP_FILE)
+  $(CC) $(C_FLAGS) /TC $(SOURCE_FILE_NAME)
+
+#
+# Link it
+#
+$(DEST_DIR)\$(FILE).exe : $(DEST_DIR)\$(FILE).obj
+  $(LINK) $(LINK_FLAGS_EXE) $(DEST_DIR)\$(FILE).obj /OUT:$(DEST_DIR)\$(FILE).exe /ENTRY:main
+
+#
+# Strip out the ACPI table
+#
+$(DEST_DIR)\$(FILE).acpi : $(DEST_DIR)\$(FILE).exe
+  $(GENACPITABLE) $(DEST_DIR)\$(FILE).exe $(DEST_DIR)\$(FILE).acpi
+
+#
+# Create a section from the ACPI table
+#
+$(DEST_DIR)\$(FILE).sec : $(DEST_DIR)\$(FILE).acpi
+  $(GENSECTION) -I $(DEST_DIR)\$(FILE).acpi -O $(DEST_DIR)\$(FILE).sec -S EFI_SECTION_RAW
+
+#
+# Add it to the targets to build
+#
+SECTIONS = $(SECTIONS) $(DEST_DIR)\$(FILE).sec
+
+[=============================================================================]
+[Compile.Ia32.asl,Compile.x64.asl]
+#
+# We run the ASL through the C Preprocessor to resolve definitions.
+#
+$(DEST_DIR)\$(FILE).asl : $(SOURCE_FILE_NAME)
+  $(CC) $(ASL_CPP_FLAGS) /nologo /C /EP /TC $(INC) -oa $(SOURCE_FILE_NAME) > $(DEST_DIR)\$(FILE).asl
+
+#
+# Add it to the targets to build
+#
+ASL_FILES = $(ASL_FILES) $(DEST_DIR)\$(FILE).asl
+
diff --git a/ReferenceCode/Chipset/SystemAgent/SampleCode/Include/Cpu.h b/ReferenceCode/Chipset/SystemAgent/SampleCode/Include/Cpu.h
new file mode 100644
index 0000000..510f1b7
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/SampleCode/Include/Cpu.h
@@ -0,0 +1,66 @@
+/** @file
+  Various CPU-specific definitions.
+
+@copyright
+  Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains 'Framework Code' and is licensed as such
+  under the terms of your license agreement with Intel or your
+  vendor.  This file may not be modified, except as allowed by
+  additional terms of your license agreement.
+**/
+
+#ifndef _CPU_H_
+#define _CPU_H_
+
+#define B_FAMILY_MODEL_STEPPING       0x00000FFF
+
+#define EFI_MSR_CORE_THREAD_COUNT     0x35
+#define EFI_MSR_IA32_PERF_STS         0x198
+#define EFI_MSR_IA32_PERF_CTL         0x199
+#define EFI_MSR_IA32_CLOCK_MODULATION 0x19A
+#define EFI_MSR_IA32_THERM_STATUS     0x19C
+
+#define B_BS_VID                      0x0000003F
+#define N_BS_VID                      0
+#define B_BS_RATIO                    0x00001F00
+#define N_BS_RATIO                    8
+
+///
+/// UINT64 workaround
+///
+/// The MS compiler doesn't handle QWORDs very well.  I'm breaking
+/// them into DWORDs to circumvent the problems.  Converting back
+/// shouldn't be a big deal.
+///
+#pragma pack(1)
+typedef union _MSR_REGISTER {
+  UINT64  Qword;
+
+  struct _DWORDS {
+    UINT32  Low;
+    UINT32  High;
+  } Dwords;
+
+  struct _BYTES {
+    UINT8 FirstByte;
+    UINT8 SecondByte;
+    UINT8 ThirdByte;
+    UINT8 FouthByte;
+    UINT8 FifthByte;
+    UINT8 SixthByte;
+    UINT8 SeventhByte;
+    UINT8 EighthByte;
+  } Bytes;
+
+} MSR_REGISTER;
+#pragma pack()
+
+#endif
diff --git a/ReferenceCode/Chipset/SystemAgent/SampleCode/Ppi/Capsule/Capsule.c b/ReferenceCode/Chipset/SystemAgent/SampleCode/Ppi/Capsule/Capsule.c
new file mode 100644
index 0000000..4b1ea89
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/SampleCode/Ppi/Capsule/Capsule.c
@@ -0,0 +1,27 @@
+/** @file
+  Capsule PPI GUID declaration.
+
+@copyright
+  Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains 'Framework Code' and is licensed as such
+  under the terms of your license agreement with Intel or your
+  vendor.  This file may not be modified, except as allowed by
+  additional terms of your license agreement.
+**/
+
+#include "Tiano.h"
+#include "PeiBind.h"
+#include "PeiApi.h"
+#include EFI_PPI_DEFINITION (Capsule)
+
+EFI_GUID  gPeiCapsulePpiGuid = PEI_CAPSULE_PPI_GUID;
+
+EFI_GUID_STRING(&gPeiCapsulePpiGuid, "Capsule", "Capsule Update PPI");
diff --git a/ReferenceCode/Chipset/SystemAgent/SampleCode/Ppi/Capsule/Capsule.h b/ReferenceCode/Chipset/SystemAgent/SampleCode/Ppi/Capsule/Capsule.h
new file mode 100644
index 0000000..200e7f5
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/SampleCode/Ppi/Capsule/Capsule.h
@@ -0,0 +1,60 @@
+/** @file
+  Capsule PPI definitions.
+
+@copyright
+  Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains 'Framework Code' and is licensed as such
+  under the terms of your license agreement with Intel or your
+  vendor.  This file may not be modified, except as allowed by
+  additional terms of your license agreement.
+**/
+
+#ifndef _PEI_CAPSULE_PPI_H_
+#define _PEI_CAPSULE_PPI_H_
+
+#define PEI_CAPSULE_PPI_GUID \
+  { \
+    0x3acf33ee, 0xd892, 0x40f4, 0xa2, 0xfc, 0x38, 0x54, 0xd2, 0xe1, 0x32, 0x3d \
+  }
+
+EFI_FORWARD_DECLARATION (PEI_CAPSULE_PPI);
+
+typedef
+EFI_STATUS
+(EFIAPI *PEI_CAPSULE_COALESCE) (
+  IN EFI_PEI_SERVICES                **PeiServices,
+  IN OUT VOID                        **MemoryBase,
+  IN OUT UINTN                       *MemSize
+  );
+
+typedef
+EFI_STATUS
+(EFIAPI *PEI_CAPSULE_CREATE_STATE) (
+  IN EFI_PEI_SERVICES                                 **PeiServices,
+  IN VOID                                             *CapsuleBase, /// returned from coalesce
+  IN UINTN                              CapsuleSize                 /// returned from coalesce
+  );
+
+typedef
+EFI_STATUS
+(EFIAPI *PEI_CAPSULE_CHECK_CAPSULE_UPDATE) (
+  IN EFI_PEI_SERVICES           **PeiServices
+  );
+
+struct _PEI_CAPSULE_PPI {
+  PEI_CAPSULE_COALESCE              Coalesce;
+  PEI_CAPSULE_CHECK_CAPSULE_UPDATE  CheckCapsuleUpdate;
+  PEI_CAPSULE_CREATE_STATE          CreateState;
+};
+
+extern EFI_GUID gPeiCapsulePpiGuid;
+
+#endif /// #ifndef _PEI_CAPSULE_PPI_H_
diff --git a/ReferenceCode/Chipset/SystemAgent/SampleCode/Ppi/IntelSaSampleCodePpiLib.cif b/ReferenceCode/Chipset/SystemAgent/SampleCode/Ppi/IntelSaSampleCodePpiLib.cif
new file mode 100644
index 0000000..e8e28a4
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/SampleCode/Ppi/IntelSaSampleCodePpiLib.cif
@@ -0,0 +1,18 @@
+<component>
+	name = "IntelSaSampleCodePpiLib"
+	category = ModulePart
+	LocalRoot = "ReferenceCode\Chipset\SystemAgent\SampleCode\Ppi"
+	RefName = "IntelSaSampleCodePpiLib"
+[files]
+"IntelSaSampleCodePpiLib.sdl"	
+"IntelSaSampleCodePpiLib.mak"	
+"IntelSaSampleCodePpiLib.inf"	
+"PlatformMemoryRange\PlatformMemoryRange.c"	
+"PlatformMemoryRange\PlatformMemoryRange.h"	
+"PlatformMemorySize\PlatformMemorySize.c"	
+"PlatformMemorySize\PlatformMemorySize.h"	
+"Capsule\Capsule.c"	
+"Capsule\Capsule.h"	
+"SmmAccess\SmmAccess.c"	
+"SmmAccess\SmmAccess.h"	
+<endComponent>
diff --git a/ReferenceCode/Chipset/SystemAgent/SampleCode/Ppi/IntelSaSampleCodePpiLib.inf b/ReferenceCode/Chipset/SystemAgent/SampleCode/Ppi/IntelSaSampleCodePpiLib.inf
new file mode 100644
index 0000000..ce3a918
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/SampleCode/Ppi/IntelSaSampleCodePpiLib.inf
@@ -0,0 +1,51 @@
+## @file
+#  Component description file for the PEI protocol library
+#
+#@copyright
+#  Copyright (c)  1999 - 2012 Intel Corporation. All rights reserved
+#  This software and associated documentation (if any) is furnished
+#  under a license and may only be used or copied in accordance
+#  with the terms of the license. Except as permitted by such
+#  license, no part of this software or documentation may be
+#  reproduced, stored in a retrieval system, or transmitted in any
+#  form or by any means without the express written consent of
+#  Intel Corporation.
+#
+#  This file contains a 'Sample Driver' and is licensed as such
+#  under the terms of your license agreement with Intel or your
+#  vendor.  This file may be modified by the user, subject to
+#  the additional terms of the license agreement
+#
+
+
+[defines]
+BASE_NAME       = IntelSaSampleCodePpiLib
+COMPONENT_TYPE  = LIBRARY
+
+[sources.common]
+  Capsule/Capsule.h
+  Capsule/Capsule.c
+  PlatformMemorySize/PlatformMemorySize.h
+  PlatformMemorySize/PlatformMemorySize.c
+  PlatformMemoryRange/PlatformMemoryRange.h
+  PlatformMemoryRange/PlatformMemoryRange.c
+  SmmAccess/SmmAccess.c
+  SmmAccess/SmmAccess.h
+
+[includes.common]
+  $(EFI_SOURCE)
+  $(EDK_SOURCE)/Foundation
+  $(EDK_SOURCE)/Foundation/Efi
+  $(EDK_SOURCE)/Foundation/Efi/Include
+  $(EDK_SOURCE)/Foundation/Framework
+  $(EDK_SOURCE)/Foundation/Framework/Include
+  $(EDK_SOURCE)/Foundation/Include
+  $(EDK_SOURCE)/Foundation/Include/IndustryStandard
+  $(EDK_SOURCE)/Foundation/Include/Pei
+  $(EDK_SOURCE)/Foundation/Library/Pei/Include
+  $(EDK_SOURCE)/Foundation/Library/Dxe/Include
+  $(EFI_SOURCE)/$(PROJECT_SA_ROOT)
+  $(EFI_SOURCE)/$(PROJECT_SA_ROOT)/SampleCode
+
+[nmake.common]
+C_STD_INCLUDE=
diff --git a/ReferenceCode/Chipset/SystemAgent/SampleCode/Ppi/IntelSaSampleCodePpiLib.mak b/ReferenceCode/Chipset/SystemAgent/SampleCode/Ppi/IntelSaSampleCodePpiLib.mak
new file mode 100644
index 0000000..c94e324
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/SampleCode/Ppi/IntelSaSampleCodePpiLib.mak
@@ -0,0 +1,64 @@
+#*************************************************************************
+#*************************************************************************
+#**                                                                     **
+#**        (C)Copyright 1985-2011, American Megatrends, Inc.            **
+#**                                                                     **
+#**                       All Rights Reserved.                          **
+#**                                                                     **
+#**      5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093           **
+#**                                                                     **
+#**                       Phone: (770)-246-8600                         **
+#**                                                                     **
+#*************************************************************************
+#*************************************************************************
+
+#*************************************************************************
+# $Header: /Alaska/BIN/Chipset/Intel/NorthBridge/Haswell/Intel SystemAgent NB Refcode/SaSampleCode/IntelSaSampleCodePpiLib/IntelSaSampleCodePpiLib.mak 1     2/08/12 4:53a Yurenlai $
+#
+# $Revision: 1 $
+#
+# $Date: 2/08/12 4:53a $
+#*************************************************************************
+# Revision History
+# ----------------
+# $Log: /Alaska/BIN/Chipset/Intel/NorthBridge/Haswell/Intel SystemAgent NB Refcode/SaSampleCode/IntelSaSampleCodePpiLib/IntelSaSampleCodePpiLib.mak $
+# 
+# 1     2/08/12 4:53a Yurenlai
+# Intel Haswell/NB eChipset initially releases.
+#
+#*************************************************************************
+#<AMI_FHDR_START>
+#
+# Name:	IntelSaSampleCodePpiLib_LIB.mak
+#
+# Description:	
+#
+#<AMI_FHDR_END>
+#**********************************************************************
+all : IntelSaSampleCodePpiLib
+
+$(BUILD_DIR)\IntelSaSampleCodePpiLib.lib : IntelSaSampleCodePpiLib
+
+IntelSaSampleCodePpiLib : $(BUILD_DIR)\IntelSaSampleCodePpiLib.mak IntelSaSampleCodePpiLibBin
+
+$(BUILD_DIR)\IntelSaSampleCodePpiLib.mak : $(IntelSaSampleCodePpiLib_DIR)\$(@B).cif $(IntelSaSampleCodePpiLib_DIR)\$(@B).mak $(BUILD_RULES)
+	$(CIF2MAK) $(IntelSaSampleCodePpiLib_DIR)\$(@B).cif $(CIF2MAK_DEFAULTS)
+
+IntelSaSampleCodePpiLibBin : 
+	$(MAKE) /$(MAKEFLAGS) $(EDK_DEFAULTS)\
+		/f $(BUILD_DIR)\IntelSaSampleCodePpiLib.mak all\
+		"MY_INCLUDES=$(EDK_INCLUDES) $(INTEL_MCH_INCLUDES) /I$(INTEL_SYSTEM_AGENT_DIR)\SampleCode" \
+		TYPE=PEI_LIBRARY \
+#*************************************************************************
+#*************************************************************************
+#**                                                                     **
+#**        (C)Copyright 1985-2011, American Megatrends, Inc.            **
+#**                                                                     **
+#**                       All Rights Reserved.                          **
+#**                                                                     **
+#**      5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093           **
+#**                                                                     **
+#**                       Phone: (770)-246-8600                         **
+#**                                                                     **
+#*************************************************************************
+#*************************************************************************
\ No newline at end of file
diff --git a/ReferenceCode/Chipset/SystemAgent/SampleCode/Ppi/IntelSaSampleCodePpiLib.sdl b/ReferenceCode/Chipset/SystemAgent/SampleCode/Ppi/IntelSaSampleCodePpiLib.sdl
new file mode 100644
index 0000000..02bda23
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/SampleCode/Ppi/IntelSaSampleCodePpiLib.sdl
@@ -0,0 +1,28 @@
+TOKEN
+	Name  = "IntelSaSampleCodePpiLib_SUPPORT"
+	Value  = "1"
+	Help  = "Main switch to enable FrameworkPpiLib support in Project"
+	TokenType = Boolean
+	TargetMAK = Yes
+	Master = Yes
+End
+
+PATH
+	Name  = "IntelSaSampleCodePpiLib_DIR"
+End
+
+MODULE
+	Help  = "Includes IntelSaSampleCodePpiLib.mak to Project"
+	File  = "IntelSaSampleCodePpiLib.mak"
+End
+
+ELINK
+	Name  = "IntelSaSampleCodePpiLib_LIB"
+	InvokeOrder = ReplaceParent
+End
+
+ELINK
+	Name  = "$(BUILD_DIR)\IntelSaSampleCodePpiLib.lib"
+	Parent  = "IntelSaSampleCodePpiLib_LIB"
+	InvokeOrder = AfterParent
+End
diff --git a/ReferenceCode/Chipset/SystemAgent/SampleCode/Ppi/PlatformMemoryRange/PlatformMemoryRange.c b/ReferenceCode/Chipset/SystemAgent/SampleCode/Ppi/PlatformMemoryRange/PlatformMemoryRange.c
new file mode 100644
index 0000000..c3c1d75
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/SampleCode/Ppi/PlatformMemoryRange/PlatformMemoryRange.c
@@ -0,0 +1,25 @@
+/** @file
+  Platform Memory Range PPI GUID as defined in EFI 2.0
+
+@copyright
+  Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains 'Framework Code' and is licensed as such
+  under the terms of your license agreement with Intel or your
+  vendor.  This file may not be modified, except as allowed by
+  additional terms of your license agreement.
+**/
+#include "Tiano.h"
+#include "Pei.h"
+#include EFI_PPI_DEFINITION (PlatformMemoryRange)
+
+EFI_GUID  gPeiPlatformMemoryRangePpiGuid = PEI_PLATFORM_MEMORY_RANGE_PPI_GUID;
+
+EFI_GUID_STRING(&gPeiPlatformMemoryRangePpiGuid, "PlatformMemoryRange", "Platform Memory Range PPI");
diff --git a/ReferenceCode/Chipset/SystemAgent/SampleCode/Ppi/PlatformMemoryRange/PlatformMemoryRange.h b/ReferenceCode/Chipset/SystemAgent/SampleCode/Ppi/PlatformMemoryRange/PlatformMemoryRange.h
new file mode 100644
index 0000000..a9a2b3e
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/SampleCode/Ppi/PlatformMemoryRange/PlatformMemoryRange.h
@@ -0,0 +1,145 @@
+/** @file
+  Platform Memory Range PPI as defined in EFI 2.0
+  PPI for reserving special purpose memory ranges.
+
+@copyright
+  Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains 'Framework Code' and is licensed as such
+  under the terms of your license agreement with Intel or your
+  vendor.  This file may not be modified, except as allowed by
+  additional terms of your license agreement.
+**/
+#ifndef _PEI_PLATFORM_MEMORY_RANGE_H_
+#define _PEI_PLATFORM_MEMORY_RANGE_H_
+
+#define PEI_PLATFORM_MEMORY_RANGE_PPI_GUID \
+  { \
+    0x30eb2979, 0xb0f7, 0x4d60, 0xb2, 0xdc, 0x1a, 0x2c, 0x96, 0xce, 0xb1, 0xf4 \
+  }
+
+EFI_FORWARD_DECLARATION (PEI_PLATFORM_MEMORY_RANGE_PPI);
+
+#define PEI_MEMORY_RANGE_OPTION_ROM UINT32
+
+#define PEI_MR_OPTION_ROM_ALL       0xFFFFFFFF
+#define PEI_MR_OPTION_ROM_NONE      0x00000000
+#define PEI_MR_OPTION_ROM_C0000_16K 0x00000001
+#define PEI_MR_OPTION_ROM_C4000_16K 0x00000002
+#define PEI_MR_OPTION_ROM_C8000_16K 0x00000004
+#define PEI_MR_OPTION_ROM_CC000_16K 0x00000008
+#define PEI_MR_OPTION_ROM_D0000_16K 0x00000010
+#define PEI_MR_OPTION_ROM_D4000_16K 0x00000020
+#define PEI_MR_OPTION_ROM_D8000_16K 0x00000040
+#define PEI_MR_OPTION_ROM_DC000_16K 0x00000080
+#define PEI_MR_OPTION_ROM_E0000_16K 0x00000100
+#define PEI_MR_OPTION_ROM_E4000_16K 0x00000200
+#define PEI_MR_OPTION_ROM_E8000_16K 0x00000400
+#define PEI_MR_OPTION_ROM_EC000_16K 0x00000800
+#define PEI_MR_OPTION_ROM_F0000_16K 0x00001000
+#define PEI_MR_OPTION_ROM_F4000_16K 0x00002000
+#define PEI_MR_OPTION_ROM_F8000_16K 0x00004000
+#define PEI_MR_OPTION_ROM_FC000_16K 0x00008000
+
+///
+/// SMRAM Memory Range
+///
+#define PEI_MEMORY_RANGE_SMRAM      UINT32
+#define PEI_MR_SMRAM_ALL            0xFFFFFFFF
+#define PEI_MR_SMRAM_NONE           0x00000000
+#define PEI_MR_SMRAM_CACHEABLE_MASK 0x80000000
+#define PEI_MR_SMRAM_SEGTYPE_MASK   0x00FF0000
+#define PEI_MR_SMRAM_ABSEG_MASK     0x00010000
+#define PEI_MR_SMRAM_HSEG_MASK      0x00020000
+#define PEI_MR_SMRAM_TSEG_MASK      0x00040000
+///
+/// If adding additional entries, SMRAM Size
+/// is a multiple of 128KB.
+///
+#define PEI_MR_SMRAM_SIZE_MASK          0x0000FFFF
+#define PEI_MR_SMRAM_SIZE_128K_MASK     0x00000001
+#define PEI_MR_SMRAM_SIZE_256K_MASK     0x00000002
+#define PEI_MR_SMRAM_SIZE_512K_MASK     0x00000004
+#define PEI_MR_SMRAM_SIZE_1024K_MASK    0x00000008
+#define PEI_MR_SMRAM_SIZE_2048K_MASK    0x00000010
+#define PEI_MR_SMRAM_SIZE_4096K_MASK    0x00000020
+#define PEI_MR_SMRAM_SIZE_8192K_MASK    0x00000040
+#define PEI_MR_SMRAM_SIZE_16384K_MASK   0x00000080
+#define PEI_MR_SMRAM_SIZE_32768K_MASK   0x00000100
+#define PEI_MR_SMRAM_SIZE_65536K_MASK   0x00000200
+
+#define PEI_MR_SMRAM_ABSEG_128K_NOCACHE 0x00010001
+#define PEI_MR_SMRAM_HSEG_128K_CACHE    0x80020001
+#define PEI_MR_SMRAM_HSEG_128K_NOCACHE  0x00020001
+#define PEI_MR_SMRAM_TSEG_128K_CACHE    0x80040001
+#define PEI_MR_SMRAM_TSEG_128K_NOCACHE  0x00040001
+#define PEI_MR_SMRAM_TSEG_256K_CACHE    0x80040002
+#define PEI_MR_SMRAM_TSEG_256K_NOCACHE  0x00040002
+#define PEI_MR_SMRAM_TSEG_512K_CACHE    0x80040004
+#define PEI_MR_SMRAM_TSEG_512K_NOCACHE  0x00040004
+#define PEI_MR_SMRAM_TSEG_1024K_CACHE   0x80040008
+#define PEI_MR_SMRAM_TSEG_1024K_NOCACHE 0x00040008
+
+///
+/// Graphics Memory Range
+///
+#define PEI_MEMORY_RANGE_GRAPHICS_MEMORY  UINT32
+#define PEI_MR_GRAPHICS_MEMORY_ALL        0xFFFFFFFF
+#define PEI_MR_GRAPHICS_MEMORY_NONE       0x00000000
+#define PEI_MR_GRAPHICS_MEMORY_CACHEABLE  0x80000000
+///
+/// If adding additional entries, Graphics Memory Size
+/// is a multiple of 512KB.
+///
+#define PEI_MR_GRAPHICS_MEMORY_SIZE_MASK    0x0000FFFF
+#define PEI_MR_GRAPHICS_MEMORY_512K_NOCACHE 0x00000001
+#define PEI_MR_GRAPHICS_MEMORY_512K_CACHE   0x80000001
+#define PEI_MR_GRAPHICS_MEMORY_1M_NOCACHE   0x00000002
+#define PEI_MR_GRAPHICS_MEMORY_1M_CACHE     0x80000002
+#define PEI_MR_GRAPHICS_MEMORY_4M_NOCACHE   0x00000008
+#define PEI_MR_GRAPHICS_MEMORY_4M_CACHE     0x80000008
+#define PEI_MR_GRAPHICS_MEMORY_8M_NOCACHE   0x00000010
+#define PEI_MR_GRAPHICS_MEMORY_8M_CACHE     0x80000010
+#define PEI_MR_GRAPHICS_MEMORY_16M_NOCACHE  0x00000020
+#define PEI_MR_GRAPHICS_MEMORY_16M_CACHE    0x80000020
+#define PEI_MR_GRAPHICS_MEMORY_32M_NOCACHE  0x00000040
+#define PEI_MR_GRAPHICS_MEMORY_32M_CACHE    0x80000040
+#define PEI_MR_GRAPHICS_MEMORY_48M_NOCACHE  0x00000060
+#define PEI_MR_GRAPHICS_MEMORY_48M_CACHE    0x80000060
+#define PEI_MR_GRAPHICS_MEMORY_64M_NOCACHE  0x00000080
+#define PEI_MR_GRAPHICS_MEMORY_64M_CACHE    0x80000080
+#define PEI_MR_GRAPHICS_MEMORY_128M_NOCACHE 0x00000100
+#define PEI_MR_GRAPHICS_MEMORY_128M_CACHE   0x80000100
+#define PEI_MR_GRAPHICS_MEMORY_256M_NOCACHE 0x00000200
+#define PEI_MR_GRAPHICS_MEMORY_256M_CACHE   0x80000200
+///
+/// Pci Memory Hole
+///
+#define PEI_MEMORY_RANGE_PCI_MEMORY       UINT32
+#define PEI_MR_PCI_MEMORY_SIZE_512M_MASK  0x00000001
+
+typedef
+EFI_STATUS
+(EFIAPI *PEI_CHOOSE_RANGES) (
+  IN      EFI_PEI_SERVICES                      **PeiServices,
+  IN PEI_PLATFORM_MEMORY_RANGE_PPI              * This,
+  IN OUT  PEI_MEMORY_RANGE_OPTION_ROM           * OptionRomMask,
+  IN OUT  PEI_MEMORY_RANGE_SMRAM                * SmramMask,
+  IN OUT  PEI_MEMORY_RANGE_GRAPHICS_MEMORY      * GraphicsMemoryMask,
+  IN OUT  PEI_MEMORY_RANGE_PCI_MEMORY           * PciMemoryMask
+  );
+
+struct _PEI_PLATFORM_MEMORY_RANGE_PPI {
+  PEI_CHOOSE_RANGES ChooseRanges;
+};
+
+extern EFI_GUID gPeiPlatformMemoryRangePpiGuid;
+
+#endif
diff --git a/ReferenceCode/Chipset/SystemAgent/SampleCode/Ppi/PlatformMemorySize/PlatformMemorySize.c b/ReferenceCode/Chipset/SystemAgent/SampleCode/Ppi/PlatformMemorySize/PlatformMemorySize.c
new file mode 100644
index 0000000..4a6c6ea
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/SampleCode/Ppi/PlatformMemorySize/PlatformMemorySize.c
@@ -0,0 +1,25 @@
+/** @file
+  Platform Memory Size PPI GUID as defined in Tiano
+
+@copyright
+  Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains 'Framework Code' and is licensed as such
+  under the terms of your license agreement with Intel or your
+  vendor.  This file may not be modified, except as allowed by
+  additional terms of your license agreement.
+**/
+#include "Tiano.h"
+#include "Pei.h"
+#include EFI_PPI_DEFINITION (PlatformMemorySize)
+
+EFI_GUID  gPeiPlatformMemorySizePpiGuid = PEI_PLATFORM_MEMORY_SIZE_PPI_GUID;
+
+EFI_GUID_STRING(&gPeiPlatformMemorySizePpiGuid, "PlatformMemorySize", "Platform Memory Size PPI");
diff --git a/ReferenceCode/Chipset/SystemAgent/SampleCode/Ppi/PlatformMemorySize/PlatformMemorySize.h b/ReferenceCode/Chipset/SystemAgent/SampleCode/Ppi/PlatformMemorySize/PlatformMemorySize.h
new file mode 100644
index 0000000..0c11041
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/SampleCode/Ppi/PlatformMemorySize/PlatformMemorySize.h
@@ -0,0 +1,45 @@
+/** @file
+  Platform Memory Size PPI as defined in Tiano
+  PPI for describing the minimum platform memory size in order to successfully
+  pass control into DXE
+
+@copyright
+  Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains 'Framework Code' and is licensed as such
+  under the terms of your license agreement with Intel or your
+  vendor.  This file may not be modified, except as allowed by
+  additional terms of your license agreement.
+**/
+#ifndef _PEI_PLATFORM_MEMORY_SIZE_H_
+#define _PEI_PLATFORM_MEMORY_SIZE_H_
+
+#define PEI_PLATFORM_MEMORY_SIZE_PPI_GUID \
+  { \
+    0x9a7ef41e, 0xc140, 0x4bd1, 0xb8, 0x84, 0x1e, 0x11, 0x24, 0xb, 0x4c, 0xe6 \
+  }
+
+EFI_FORWARD_DECLARATION (PEI_PLATFORM_MEMORY_SIZE_PPI);
+
+typedef
+EFI_STATUS
+(EFIAPI *PEI_GET_MINIMUM_PLATFORM_MEMORY_SIZE) (
+  IN      EFI_PEI_SERVICES                       **PeiServices,
+  IN PEI_PLATFORM_MEMORY_SIZE_PPI                * This,
+  IN OUT  UINT64                                 *MemorySize
+  );
+
+struct _PEI_PLATFORM_MEMORY_SIZE_PPI {
+  PEI_GET_MINIMUM_PLATFORM_MEMORY_SIZE  GetPlatformMemorySize;
+};
+
+extern EFI_GUID gPeiPlatformMemorySizePpiGuid;
+
+#endif
diff --git a/ReferenceCode/Chipset/SystemAgent/SampleCode/Ppi/SmmAccess/SmmAccess.c b/ReferenceCode/Chipset/SystemAgent/SampleCode/Ppi/SmmAccess/SmmAccess.c
new file mode 100644
index 0000000..9dc4695
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/SampleCode/Ppi/SmmAccess/SmmAccess.c
@@ -0,0 +1,25 @@
+/** @file
+  SmmAccess PPI GUID
+
+@copyright
+  Copyright (c) 2009 - 2012 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains 'Framework Code' and is licensed as such
+  under the terms of your license agreement with Intel or your
+  vendor.  This file may not be modified, except as allowed by
+  additional terms of your license agreement.
+**/
+#include "Tiano.h"
+#include "Pei.h"
+#include EFI_PPI_DEFINITION (SmmAccess)
+
+EFI_GUID  gPeiSmmAccessPpiGuid = PEI_SMM_ACCESS_PPI_GUID;
+
+EFI_GUID_STRING(&gPeiSmmAccessPpiGuid, "SmmAccess", "SMM Access PPI");
diff --git a/ReferenceCode/Chipset/SystemAgent/SampleCode/Ppi/SmmAccess/SmmAccess.h b/ReferenceCode/Chipset/SystemAgent/SampleCode/Ppi/SmmAccess/SmmAccess.h
new file mode 100644
index 0000000..8ff077f
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/SampleCode/Ppi/SmmAccess/SmmAccess.h
@@ -0,0 +1,136 @@
+/** @file
+  This code abstracts the PEI core to provide SmmAccess services.
+
+@copyright
+  Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains 'Framework Code' and is licensed as such
+  under the terms of your license agreement with Intel or your
+  vendor.  This file may not be modified, except as allowed by
+  additional terms of your license agreement.
+**/
+#ifndef _PEI_SMM_ACCESS_PPI_H_
+#define _PEI_SMM_ACCESS_PPI_H_
+
+#include EFI_GUID_DEFINITION (SmramMemoryReserve)
+
+#define PEI_SMM_ACCESS_PPI_GUID \
+  { \
+    0x268f33a9, 0xcccd, 0x48be, 0x88, 0x17, 0x86, 0x5, 0x3a, 0xc3, 0x2e, 0xd6 \
+  }
+
+EFI_FORWARD_DECLARATION (PEI_SMM_ACCESS_PPI);
+
+typedef
+EFI_STATUS
+(EFIAPI *PEI_SMM_OPEN) (
+  IN EFI_PEI_SERVICES                **PeiServices,
+  IN PEI_SMM_ACCESS_PPI              * This,
+  IN UINTN                           DescriptorIndex
+  )
+/**
+  This routine accepts a request to "open" a region of SMRAM.  The
+  region could be legacy ABSEG, HSEG, or TSEG near top of physical memory.
+  The use of "open" means that the memory is visible from all PEIM
+  and SMM agents.
+
+  @param[in] This                  - Pointer to the SMM Access Interface.
+  @param[in] DescriptorIndex       - Region of SMRAM to Open.
+
+  @retval EFI_SUCCESS           - The region was successfully opened.
+  @retval EFI_DEVICE_ERROR      - The region could not be opened because locked by
+                          chipset.
+  @retval EFI_INVALID_PARAMETER - The descriptor index was out of bounds.
+**/
+;
+
+typedef
+EFI_STATUS
+(EFIAPI *PEI_SMM_CLOSE) (
+  IN EFI_PEI_SERVICES                **PeiServices,
+  IN PEI_SMM_ACCESS_PPI              * This,
+  IN UINTN                           DescriptorIndex
+  )
+/**
+  This routine accepts a request to "close" a region of SMRAM.  The
+  region could be legacy AB or TSEG near top of physical memory.
+  The use of "close" means that the memory is only visible from SMM agents,
+  not from PEIM.
+
+  @param[in] This                  - Pointer to the SMM Access Interface.
+  @param[in] DescriptorIndex       - Region of SMRAM to Close.
+
+  @retval EFI_SUCCESS           - The region was successfully closed.
+  @retval EFI_DEVICE_ERROR      - The region could not be closed because locked by
+                            chipset.
+  @retval EFI_INVALID_PARAMETER - The descriptor index was out of bounds.
+**/
+;
+
+typedef
+EFI_STATUS
+(EFIAPI *PEI_SMM_LOCK) (
+  IN EFI_PEI_SERVICES                **PeiServices,
+  IN PEI_SMM_ACCESS_PPI              * This,
+  IN UINTN                           DescriptorIndex
+  )
+/**
+  This routine accepts a request to "lock" SMRAM.  The
+  region could be legacy AB or TSEG near top of physical memory.
+  The use of "lock" means that the memory can no longer be opened
+  to PEIM.
+
+  @param[in] This                  - Pointer to the SMM Access Interface.
+  @param[in] DescriptorIndex       - Region of SMRAM to Lock.
+
+  @retval EFI_SUCCESS           - The region was successfully locked.
+  @retval EFI_DEVICE_ERROR      - The region could not be locked because at least
+                          one range is still open.
+  @retval EFI_INVALID_PARAMETER - The descriptor index was out of bounds.
+**/
+;
+
+typedef
+EFI_STATUS
+(EFIAPI *PEI_SMM_CAPABILITIES) (
+  IN EFI_PEI_SERVICES                **PeiServices,
+  IN PEI_SMM_ACCESS_PPI              * This,
+  IN OUT UINTN                       *SmramMapSize,
+  IN OUT EFI_SMRAM_DESCRIPTOR        * SmramMap
+  )
+/**
+  This routine services a user request to discover the SMRAM
+  capabilities of this platform.  This will report the possible
+  ranges that are possible for SMRAM access, based upon the
+  memory controller capabilities.
+
+  @param[in] This                  - Pointer to the SMRAM Access Interface.
+  @param[in] SmramMapSize          - Pointer to the variable containing size of the
+                            buffer to contain the description information.
+  @param[in] SmramMap              - Buffer containing the data describing the Smram
+                            region descriptors.
+
+  @retval EFI_BUFFER_TOO_SMALL  - The user did not provide a sufficient buffer.
+  @retval EFI_SUCCESS           - The user provided a sufficiently-sized buffer.
+**/
+;
+
+struct _PEI_SMM_ACCESS_PPI {
+  PEI_SMM_OPEN          Open;
+  PEI_SMM_CLOSE         Close;
+  PEI_SMM_LOCK          Lock;
+  PEI_SMM_CAPABILITIES  GetCapabilities;
+  BOOLEAN               LockState;
+  BOOLEAN               OpenState;
+};
+
+extern EFI_GUID gPeiSmmAccessPpiGuid;
+
+#endif
diff --git a/ReferenceCode/Chipset/SystemAgent/SampleCode/Protocol/IntelSaSampleCodeProtocolLib.inf b/ReferenceCode/Chipset/SystemAgent/SampleCode/Protocol/IntelSaSampleCodeProtocolLib.inf
new file mode 100644
index 0000000..32dd4d1
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/SampleCode/Protocol/IntelSaSampleCodeProtocolLib.inf
@@ -0,0 +1,42 @@
+## @file
+#  Component description file for SA SamepleCode protocol library
+#
+#@copyright
+#  Copyright (c)  1999 - 2012 Intel Corporation. All rights reserved
+#  This software and associated documentation (if any) is furnished
+#  under a license and may only be used or copied in accordance
+#  with the terms of the license. Except as permitted by such
+#  license, no part of this software or documentation may be
+#  reproduced, stored in a retrieval system, or transmitted in any
+#  form or by any means without the express written consent of
+#  Intel Corporation.
+#
+#  This file contains a 'Sample Driver' and is licensed as such
+#  under the terms of your license agreement with Intel or your
+#  vendor.  This file may be modified by the user, subject to
+#  the additional terms of the license agreement
+#
+
+[defines]
+BASE_NAME       =   IntelSaSampleCodeProtocolLib
+COMPONENT_TYPE  =   LIBRARY
+
+[sources.common]
+  PciEnumerationComplete.h
+
+[includes.common]
+  $(EDK_SOURCE)/Foundation
+  $(EDK_SOURCE)/Foundation/Efi
+  $(EDK_SOURCE)/Foundation/Efi/Include
+  $(EDK_SOURCE)/Foundation/Framework
+  $(EDK_SOURCE)/Foundation/Framework/Include
+  $(EDK_SOURCE)/Foundation/Include
+  $(EDK_SOURCE)/Foundation/Include/IndustryStandard
+  $(EFI_SOURCE)/$(PROJECT_SA_ROOT)/Include
+  $(EFI_SOURCE)/$(PROJECT_SA_ROOT)/SampleCode
+  $(EDK_SOURCE)/Foundation/Library/EdkIIGlueLib/Include
+  $(EDK_SOURCE)/Foundation/Core/Dxe
+  $(EDK_SOURCE)/Foundation/Library/Dxe/Include
+
+[nmake.common]
+C_STD_INCLUDE=
diff --git a/ReferenceCode/Chipset/SystemAgent/SampleCode/Protocol/PciEnumerationComplete.h b/ReferenceCode/Chipset/SystemAgent/SampleCode/Protocol/PciEnumerationComplete.h
new file mode 100644
index 0000000..405c2d5
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/SampleCode/Protocol/PciEnumerationComplete.h
@@ -0,0 +1,30 @@
+/** @file
+  PCI Enumeration Complete Protocol as defined in the PI 1.1 specification.
+  This protocol indicates that pci enumeration complete
+
+@copyright
+  Copyright (c) 2009 - 2012 Intel Corporation. All rights reserved.<BR>
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+@par Revision Reference:
+  This Protocol is defined in UEFI Platform Initialization Specification 1.2
+  Volume 5: Standards
+**/
+
+#ifndef _PCI_ENUMERATION_COMPLETE_H_
+#define _PCI_ENUMERATION_COMPLETE_H_
+
+#define EFI_PCI_ENUMERATION_COMPLETE_GUID \
+  {  \
+   0x30cfe3e7, 0x3de1, 0x4586, { 0xbe, 0x20, 0xde, 0xab, 0xa1, 0xb3, 0xb7, 0x93  } \
+  }
+
+extern EFI_GUID gEfiPciEnumerationCompleteProtocolGuid;
+
+#endif
diff --git a/ReferenceCode/Chipset/SystemAgent/SampleCode/SaPolicyInit/Dxe/SaDxePolicyInit.c b/ReferenceCode/Chipset/SystemAgent/SampleCode/SaPolicyInit/Dxe/SaDxePolicyInit.c
new file mode 100644
index 0000000..f907f4f
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/SampleCode/SaPolicyInit/Dxe/SaDxePolicyInit.c
@@ -0,0 +1,247 @@
+/** @file
+  This file is a wrapper for Intel SA Platform Policy driver.
+  Get Setup Value to initilize Intel SA DXE Platform Policy.
+
+@copyright
+  Copyright (c) 1999 - 2014 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains a 'Sample Driver' and is licensed as such
+  under the terms of your license agreement with Intel or your
+  vendor.  This file may be modified by the user, subject to
+  the additional terms of the license agreement
+
+**/
+#include "SaDxePolicyInit.h"
+
+DXE_PLATFORM_SA_POLICY_PROTOCOL mDxePlatformSaPolicy;
+
+PCIE_ASPM_DEV_INFO mPcieAspmDevsOverride[] = {
+  ///
+  /// Tekoa w/o iAMT
+  ///
+  {0x8086, 0x108b, 0xff, 2, 2},
+  ///
+  /// Tekoa A2
+  ///
+  {0x8086, 0x108c, 0x00, 0, 0},
+  ///
+  /// Tekoa others
+  ///
+  {0x8086, 0x108c, 0xff, 2, 2},
+  ///
+  /// Vidalia
+  ///
+  {0x8086, 0x109a, 0xff, 2, 2},
+  ///
+  /// 3945ABG
+  ///
+  {0x8086, 0x4222, 0xff, 2, 3},
+  ///
+  /// 3945ABG
+  ///
+  {0x8086, 0x4227, 0xff, 2, 3},
+  ///
+  /// 3945ABG
+  ///
+  {0x8086, 0x4228, 0xff, 2, 3},
+  ///
+  /// End of table
+  ///
+  {SA_PCIE_DEV_END_OF_TABLE, 0, 0, 0, 0}
+};
+
+PCIE_LTR_DEV_INFO mPcieLtrDevsOverride[] = {
+  ///
+  /// Place holder for PCIe devices with correct LTR requirements
+  ///
+  ///
+  /// End of table
+  ///
+  {SA_PCIE_DEV_END_OF_TABLE, 0, 0, 0, 0}
+};
+///
+/// Function implementations
+///
+/**
+  Initilize Intel SA DXE Platform Policy
+
+  @param[in] ImageHandle       Image handle of this driver.
+  @param[in] SystemTable       Global system service table.
+
+  @retval EFI_SUCCESS           Initialization complete.
+  @exception EFI_UNSUPPORTED       The chipset is unsupported by this driver.
+  @retval EFI_OUT_OF_RESOURCES  Do not have enough resources to initialize the driver.
+  @retval EFI_DEVICE_ERROR      Device error, driver exits abnormally.
+**/
+EFI_STATUS
+EFIAPI
+SaDxePolicyInitEntryPoint (
+  IN EFI_HANDLE       ImageHandle,
+  IN EFI_SYSTEM_TABLE *SystemTable
+  )
+{
+  EFI_STATUS  Status;
+  UINT8       pegFn;
+  UINT8       Index;
+
+  SetMem (&mDxePlatformSaPolicy, sizeof (DXE_PLATFORM_SA_POLICY_PROTOCOL), 0);
+  Status = (gBS->AllocatePool) (EfiBootServicesData, sizeof (SA_VTD_CONFIGURATION), &(mDxePlatformSaPolicy.Vtd));
+  ASSERT_EFI_ERROR (Status);
+  Status = (gBS->AllocatePool) (EfiBootServicesData, sizeof (SA_MEMORY_CONFIGURATION), &(mDxePlatformSaPolicy.MemoryConfig));
+  ASSERT_EFI_ERROR (Status);
+  Status = (gBS->AllocatePool) (EfiBootServicesData, sizeof (SA_PCIE_CONFIGURATION), &(mDxePlatformSaPolicy.PcieConfig));
+  ASSERT_EFI_ERROR (Status);
+  Status = (gBS->AllocatePool) (EfiBootServicesData, sizeof (SA_IGD_CONFIGURATION), &(mDxePlatformSaPolicy.IgdConfig));
+  ASSERT_EFI_ERROR (Status);
+  Status = (gBS->AllocatePool) (EfiBootServicesData, sizeof (SA_MISC_CONFIGURATION), &(mDxePlatformSaPolicy.MiscConfig));
+  ASSERT_EFI_ERROR (Status);
+#ifdef SG_SUPPORT
+  Status = (gBS->AllocatePool) (EfiBootServicesData, sizeof (SA_SG_VBIOS_CONFIGURATION), &(mDxePlatformSaPolicy.VbiosConfig));
+  ASSERT_EFI_ERROR (Status);
+#endif
+
+  ///
+  /// SA DXE Policy Init
+  ///
+  mDxePlatformSaPolicy.Revision = DXE_SA_PLATFORM_POLICY_PROTOCOL_REVISION_8;
+
+  ///
+  /// Initialize the VTD Configuration
+  ///
+  mDxePlatformSaPolicy.Vtd->VtdEnable       = 0;
+  mDxePlatformSaPolicy.Vtd->BaseAddress[0]  = 0xFED90000;
+  mDxePlatformSaPolicy.Vtd->BaseAddress[1]  = 0xFED91000;
+  ///
+  /// RMRR Base and Limit Address for USB
+  ///
+  Status = (gBS->AllocatePool) (EfiBootServicesData, (sizeof (EFI_PHYSICAL_ADDRESS) * 2), (VOID **) &mDxePlatformSaPolicy.Vtd->RmrrUsbBaseAddress);
+  ASSERT_EFI_ERROR (Status);
+  ///
+  /// BIOS must update USB RMRR base address
+  ///
+  mDxePlatformSaPolicy.Vtd->RmrrUsbBaseAddress[0] = 0x3E2E0000;
+  mDxePlatformSaPolicy.Vtd->RmrrUsbBaseAddress[1] = 0x3E2FFFFF;
+
+  ///
+  /// Initialize the PCIE Configuration
+  ///
+  mDxePlatformSaPolicy.PcieConfig->DmiAspm = PcieAspmL0sL1;
+  ///
+  /// PEG ASPM per port configuration. 3 PEG controllers i.e. 0,1,2
+  ///
+  for (pegFn = 0; pegFn < 3; pegFn++) {
+    mDxePlatformSaPolicy.PcieConfig->PegAspm[pegFn]       = PcieAspmAutoConfig;
+    mDxePlatformSaPolicy.PcieConfig->PegAspmL0s[pegFn]    = 0;
+    mDxePlatformSaPolicy.PcieConfig->PegDeEmphasis[pegFn] = 1;
+  }
+
+  mDxePlatformSaPolicy.PcieConfig->DmiExtSync     = 0;
+  mDxePlatformSaPolicy.PcieConfig->DmiDeEmphasis  = 0;
+  mDxePlatformSaPolicy.PcieConfig->DmiIot = 0;
+  mDxePlatformSaPolicy.PcieConfig->C7Allowed = 0;
+  for (Index = 0; Index < SA_PEG_MAX_FUN; Index++) {
+    mDxePlatformSaPolicy.PcieConfig->PegPwrOpt[Index].LtrEnable            = 1;
+    mDxePlatformSaPolicy.PcieConfig->PegPwrOpt[Index].LtrMaxSnoopLatency   = V_SA_LTR_MAX_SNOOP_LATENCY_VALUE;
+    mDxePlatformSaPolicy.PcieConfig->PegPwrOpt[Index].LtrMaxNoSnoopLatency = V_SA_LTR_MAX_NON_SNOOP_LATENCY_VALUE;
+    mDxePlatformSaPolicy.PcieConfig->PegPwrOpt[Index].ObffEnable           = 1;
+  }
+
+  mDxePlatformSaPolicy.PcieConfig->PcieAspmDevsOverride = mPcieAspmDevsOverride;
+  mDxePlatformSaPolicy.PcieConfig->PcieLtrDevsOverride  = mPcieLtrDevsOverride;
+
+  ///
+  /// Initialize the Memory Configuration
+  ///
+  ///
+  /// DIMM SMBus addresses info
+  /// Refer to the SpdAddressTable[] mapping rule in SaPlatformPolicy.h
+  ///
+  Status = (gBS->AllocatePool) (EfiBootServicesData, (sizeof (UINT8) * 4), (VOID **) &mDxePlatformSaPolicy.MemoryConfig->SpdAddressTable);
+  ASSERT_EFI_ERROR (Status);
+
+  mDxePlatformSaPolicy.MemoryConfig->SpdAddressTable[0] = DIMM_SMB_SPD_P0C0D0;
+  mDxePlatformSaPolicy.MemoryConfig->SpdAddressTable[1] = DIMM_SMB_SPD_P0C0D1;
+  mDxePlatformSaPolicy.MemoryConfig->SpdAddressTable[2] = DIMM_SMB_SPD_P0C1D0;
+  mDxePlatformSaPolicy.MemoryConfig->SpdAddressTable[3] = DIMM_SMB_SPD_P0C1D1;
+
+  mDxePlatformSaPolicy.MemoryConfig->ChannelASlotMap    = 0x01;
+  mDxePlatformSaPolicy.MemoryConfig->ChannelBSlotMap    = 0x01;
+  mDxePlatformSaPolicy.MemoryConfig->RmtBdatEnable      = 0x00;
+
+  ///
+  /// Initialize the Graphics configuration
+  ///
+  mDxePlatformSaPolicy.IgdConfig->RenderStandby     = 1;
+  mDxePlatformSaPolicy.IgdConfig->VbtAddress        = 0x00000000;
+  mDxePlatformSaPolicy.IgdConfig->Size              = 0;
+  mDxePlatformSaPolicy.IgdConfig->CdClk             = 0;
+  mDxePlatformSaPolicy.IgdConfig->PlatformConfig    = 1;
+
+  ///
+  /// SA internal devices and misc configuration
+  ///
+  mDxePlatformSaPolicy.MiscConfig->ChapDeviceEnable = FALSE;
+  mDxePlatformSaPolicy.MiscConfig->Device4Enable    = FALSE;
+  mDxePlatformSaPolicy.MiscConfig->CridEnable       = FALSE;
+  mDxePlatformSaPolicy.MiscConfig->AudioEnable      = TRUE;
+  mDxePlatformSaPolicy.MiscConfig->FviReport        = 1;
+  ///
+  /// Default Enable FVI SMBIOS Report
+  ///
+  mDxePlatformSaPolicy.MiscConfig->FviSmbiosType = 0xDD;
+  ///
+  /// Default SMBIOS Type 221
+  ///
+  Status = (gBS->AllocatePool) (EfiBootServicesData, sizeof (SA_DEFAULT_SVID_SID), (VOID **) &mDxePlatformSaPolicy.MiscConfig->DefaultSvidSid);
+  ASSERT_EFI_ERROR (Status);
+  mDxePlatformSaPolicy.MiscConfig->DefaultSvidSid->SubSystemVendorId = V_SA_MC_VID;
+  ///
+  /// 0x8086;
+  ///
+  mDxePlatformSaPolicy.MiscConfig->DefaultSvidSid->SubSystemId = 0x2010;
+
+
+#ifdef SG_SUPPORT
+  ///
+  /// Initialize the Switchable Graphics DXE Policies
+  ///
+
+  ///
+  /// 1 = Load secondary display device VBIOS
+  /// 0 = Do not load
+  ///
+  mDxePlatformSaPolicy.VbiosConfig->LoadVbios = 0;
+  ///
+  /// 1 = Execute the secondary display device VBIOS (only if LoadVbios == 1)
+  /// 0 = Do no execute
+  ///
+  mDxePlatformSaPolicy.VbiosConfig->ExecuteVbios = 0;
+  ///
+  /// 1 = secondary display device VBIOS Source is PCI Card
+  /// 0 = secondary display device VBIOS Source is FW Volume
+  ///
+  mDxePlatformSaPolicy.VbiosConfig->VbiosSource = 1;
+#endif
+
+  UpdateDxeSaPlatformPolicy (&mDxePlatformSaPolicy);
+
+  ///
+  /// Install protocol to to allow access to this Policy.
+  ///
+  Status = gBS->InstallMultipleProtocolInterfaces (
+                  &ImageHandle,
+                  &gDxePlatformSaPolicyGuid,
+                  &mDxePlatformSaPolicy,
+                  NULL
+                  );
+  ASSERT_EFI_ERROR (Status);
+
+  return Status;
+}
diff --git a/ReferenceCode/Chipset/SystemAgent/SampleCode/SaPolicyInit/Dxe/SaDxePolicyInit.dxs b/ReferenceCode/Chipset/SystemAgent/SampleCode/SaPolicyInit/Dxe/SaDxePolicyInit.dxs
new file mode 100644
index 0000000..21fcf4c
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/SampleCode/SaPolicyInit/Dxe/SaDxePolicyInit.dxs
@@ -0,0 +1,31 @@
+/** @file
+  Dependency expression source file.
+
+@copyright
+  Copyright (c)  1999 - 2012 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains a 'Sample Driver' and is licensed as such
+  under the terms of your license agreement with Intel or your
+  vendor.  This file may be modified by the user, subject to
+  the additional terms of the license agreement
+
+**/
+ 
+
+#include "EfiDepex.h"
+#include EFI_PROTOCOL_DEFINITION (PchPlatformPolicy)
+#include EFI_ARCH_PROTOCOL_DEFINITION (Variable)
+
+DEPENDENCY_START
+    DXE_PCH_PLATFORM_POLICY_PROTOCOL_GUID AND
+    EFI_VARIABLE_ARCH_PROTOCOL_GUID
+DEPENDENCY_END
+
+
diff --git a/ReferenceCode/Chipset/SystemAgent/SampleCode/SaPolicyInit/Dxe/SaDxePolicyInit.h b/ReferenceCode/Chipset/SystemAgent/SampleCode/SaPolicyInit/Dxe/SaDxePolicyInit.h
new file mode 100644
index 0000000..8f87761
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/SampleCode/SaPolicyInit/Dxe/SaDxePolicyInit.h
@@ -0,0 +1,59 @@
+/** @file
+  Header file for the SaDxePolicyInit Driver.
+
+@copyright
+  Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains a 'Sample Driver' and is licensed as such
+  under the terms of your license agreement with Intel or your
+  vendor.  This file may be modified by the user, subject to
+  the additional terms of the license agreement
+**/
+#ifndef _SA_DXE_PLATFORM_POLICY_H_
+#define _SA_DXE_PLATFORM_POLICY_H_
+
+#if !defined(EDK_RELEASE_VERSION) || (EDK_RELEASE_VERSION < 0x00020000)
+#include "EdkIIGlueDxe.h"
+#include "EfiScriptLib.h"
+#include EFI_PROTOCOL_PRODUCER (SaPlatformPolicy)
+#endif
+
+#include "SaAccess.h"
+#include "SaPlatformPolicyUpdateDxeLib.h"
+
+///
+/// DIMM SMBus addresses
+///
+#define DIMM_SMB_SPD_P0C0D0 0xA0
+#define DIMM_SMB_SPD_P0C0D1 0xA2
+#define DIMM_SMB_SPD_P0C1D0 0xA4
+#define DIMM_SMB_SPD_P0C1D1 0xA6
+#define DIMM_SMB_SPD_P0C0D2 0xA8
+#define DIMM_SMB_SPD_P0C1D2 0xAA
+
+/**
+  Initilize Intel SA DXE Platform Policy
+
+  @param[in] ImageHandle - Image handle of this driver.
+  @param[in] SystemTable - Global system service table.
+
+  @retval EFI_SUCCESS           Initialization complete.
+  @exception EFI_UNSUPPORTED       The chipset is unsupported by this driver.
+  @retval EFI_OUT_OF_RESOURCES  Do not have enough resources to initialize the driver.
+  @retval EFI_DEVICE_ERROR      Device error, driver exits abnormally.
+**/
+EFI_STATUS
+SaDxePolicyInitEntryPoint (
+  IN EFI_HANDLE           ImageHandle,
+  IN OUT EFI_SYSTEM_TABLE *SystemTable
+  )
+;
+
+#endif
diff --git a/ReferenceCode/Chipset/SystemAgent/SampleCode/SaPolicyInit/Dxe/SaDxePolicyInit.inf b/ReferenceCode/Chipset/SystemAgent/SampleCode/SaPolicyInit/Dxe/SaDxePolicyInit.inf
new file mode 100644
index 0000000..8ee2520
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/SampleCode/SaPolicyInit/Dxe/SaDxePolicyInit.inf
@@ -0,0 +1,84 @@
+## @file
+#  Component description file for the SaDxePolicyInit DXE driver.
+#
+#@copyright
+#  Copyright (c)  1999 - 2012 Intel Corporation. All rights reserved
+#  This software and associated documentation (if any) is furnished
+#  under a license and may only be used or copied in accordance
+#  with the terms of the license. Except as permitted by such
+#  license, no part of this software or documentation may be
+#  reproduced, stored in a retrieval system, or transmitted in any
+#  form or by any means without the express written consent of
+#  Intel Corporation.
+#
+#  This file contains a 'Sample Driver' and is licensed as such
+#  under the terms of your license agreement with Intel or your
+#  vendor.  This file may be modified by the user, subject to
+#  the additional terms of the license agreement
+#
+
+
+[defines]
+BASE_NAME            = SaDxePolicyInit
+FILE_GUID            = 67a54a24-3f4f-4048-8787-3e5aa2a0b7d2
+COMPONENT_TYPE       = BS_DRIVER
+
+[sources.common]
+  SaDxePolicyInit.c
+  SaDxePolicyInit.h
+#
+# Edk II Glue Driver Entry Point
+#
+  EdkIIGlueDxeDriverEntryPoint.c
+
+[includes.common]
+  .
+  $(EDK_SOURCE)/Foundation
+  $(EDK_SOURCE)/Foundation/Include
+  $(EDK_SOURCE)/Foundation/Efi
+  $(EDK_SOURCE)/Foundation/Efi/Include
+  $(EDK_SOURCE)/Foundation/Framework
+  $(EDK_SOURCE)/Foundation/Framework/Include
+  $(EDK_SOURCE)/Foundation/Library/EdkIIGlueLib/Include
+  $(EDK_SOURCE)/Foundation/Library/EdkIIGlueLib/Include/Pcd
+  $(EDK_SOURCE)/Foundation/Include/IndustryStandard
+  $(EDK_SOURCE)/Foundation/Library/Dxe/Include
+  $(EDK_SOURCE)/Foundation/Core/Dxe
+  $(EDK_SOURCE)/Foundation/Cpu/Pentium/Include
+  $(EFI_SOURCE)/$(PROJECT_SA_ROOT)
+  $(EFI_SOURCE)/$(PROJECT_SA_ROOT)/Include
+  $(PLATFORM_ECP_PACKAGE)/Include
+  $(EFI_SOURCE)/$(PROJECT_PCH_ROOT)
+  $(EFI_SOURCE)/$(PROJECT_PCH_ROOT)/Include
+
+[libraries.common]
+  EdkGuidLib
+  EdkFrameworkGuidLib
+  EdkFrameworkProtocolLib
+  EdkProtocolLib
+  EfiGuidLib
+  EfiCommonLib
+  $(PROJECT_SA_FAMILY)ProtocolLib
+  EdkIIGlueBaseLib
+  EdkIIGlueBaseIoLibIntrinsic
+  EdkIIGlueBasePciLibPciExpress
+  EdkIIGlueDxeReportStatusCodeLib
+  EdkIIGlueDxeDebugLibReportStatusCode
+  EdkIIGlueUefiBootServicesTableLib
+  EdkIIGlueUefiRuntimeServicesTableLib
+  EdkIIGlueDxeServicesTableLib
+  PlatformPolicyUpdateDxeLib
+
+[nmake.common]
+  IMAGE_ENTRY_POINT= _ModuleEntryPoint
+  DPX_SOURCE=SaDxePolicyInit.dxs
+  C_FLAGS = $(C_FLAGS)  -D"__EDKII_GLUE_MODULE_ENTRY_POINT__=SaDxePolicyInitEntryPoint" \
+                        -D __EDKII_GLUE_BASE_IO_LIB_INTRINSIC__ \
+                        -D __EDKII_GLUE_BASE_LIB__ \
+                        -D __EDKII_GLUE_BASE_MEMORY_LIB__ \
+                        -D __EDKII_GLUE_DXE_REPORT_STATUS_CODE_LIB__ \
+                        -D __EDKII_GLUE_DXE_SERVICES_TABLE_LIB__ \
+                        -D __EDKII_GLUE_DXE_DEBUG_LIB_REPORT_STATUS_CODE__ \
+                        -D __EDKII_GLUE_UEFI_BOOT_SERVICES_TABLE_LIB__\
+                        -D __EDKII_GLUE_UEFI_RUNTIME_SERVICES_TABLE_LIB__ \
+                        -D __EDKII_GLUE_UEFI_LIB__
diff --git a/ReferenceCode/Chipset/SystemAgent/SampleCode/SaPolicyInit/Pei/SaPeiPolicyInit.c b/ReferenceCode/Chipset/SystemAgent/SampleCode/SaPolicyInit/Pei/SaPeiPolicyInit.c
new file mode 100644
index 0000000..7317fb4
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/SampleCode/SaPolicyInit/Pei/SaPeiPolicyInit.c
@@ -0,0 +1,548 @@
+/** @file
+  This file is SampleCode for Intel SA PEI Platform Policy initialzation.
+
+@copyright
+  Copyright (c) 1999 - 2014 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains a 'Sample Driver' and is licensed as such
+  under the terms of your license agreement with Intel or your
+  vendor.  This file may be modified by the user, subject to
+  the additional terms of the license agreement
+
+**/
+#include "SaPeiPolicyInit.h"
+
+///
+/// This IO Trap address can be overridden by defining it
+/// in compiling environment variable
+/// It must not conflict with other IO address in platform
+///
+#ifndef SA_IOTRAP_SMI_ADDRESS
+#define SA_IOTRAP_SMI_ADDRESS 0x2000
+#endif
+
+EFI_STATUS
+SaPeiPolicyInitEntryPoint (
+  IN EFI_FFS_FILE_HEADER       *FfsHeader,
+  IN EFI_PEI_SERVICES          **PeiServices
+  )
+/**
+  This PEIM performs SA PEI Platform Policy initialzation.
+
+  @param[in] FfsHeader    - Pointer to Firmware File System file header.
+  @param[in] PeiServices  - General purpose services available to every PEIM.
+
+  @retval EFI_SUCCESS - The PPI is installed and initialized.
+  @retval EFI ERRORS  - The PPI is not successfully installed.
+**/
+{
+  EFI_STATUS                  Status;
+  EFI_PEI_PPI_DESCRIPTOR      *SaPlatformPolicyPpiDesc;
+  SA_PLATFORM_POLICY_PPI      *SaPlatformPolicyPpi;
+  SA_PLATFORM_DATA            *PlatformData;
+  GT_CONFIGURATION            *GtConfig;
+  MEMORY_CONFIGURATION        *MemConfig;
+  PCIE_CONFIGURATION          *PcieConfig;
+  OVERCLOCKING_CONFIGURATION  *OcConfig;
+  PEG_GPIO_DATA               *PegGpioData;
+  CPU_FAMILY                  CpuFamilyId;
+#ifdef SG_SUPPORT
+  SG_GPIO_DATA                *SgGpioData;
+#endif
+  UINT8                       Index;
+  ///
+  /// Allocate descriptor and PPI structures
+  ///
+  SaPlatformPolicyPpi = (SA_PLATFORM_POLICY_PPI *) AllocatePool (sizeof (SA_PLATFORM_POLICY_PPI));
+  ASSERT (SaPlatformPolicyPpi != NULL);
+  EfiCommonLibZeroMem (SaPlatformPolicyPpi, sizeof (SA_PLATFORM_POLICY_PPI));
+
+  SaPlatformPolicyPpiDesc = (EFI_PEI_PPI_DESCRIPTOR *) AllocatePool (sizeof (EFI_PEI_PPI_DESCRIPTOR));
+  ASSERT (SaPlatformPolicyPpiDesc != NULL);
+  EfiCommonLibZeroMem (SaPlatformPolicyPpiDesc, sizeof (EFI_PEI_PPI_DESCRIPTOR));
+
+  PlatformData = (SA_PLATFORM_DATA *) AllocatePool (sizeof (SA_PLATFORM_DATA));
+  ASSERT (PlatformData != NULL);
+  EfiCommonLibZeroMem (PlatformData, sizeof (SA_PLATFORM_DATA));
+
+  GtConfig = (GT_CONFIGURATION *) AllocatePool (sizeof (GT_CONFIGURATION));
+  ASSERT (GtConfig != NULL);
+  EfiCommonLibZeroMem (GtConfig, sizeof (GT_CONFIGURATION));
+
+  MemConfig = (MEMORY_CONFIGURATION *) AllocatePool (sizeof (MEMORY_CONFIGURATION));
+  ASSERT (MemConfig != NULL);
+  EfiCommonLibZeroMem (MemConfig, sizeof (MEMORY_CONFIGURATION));
+
+  PcieConfig = (PCIE_CONFIGURATION *) AllocatePool (sizeof (PCIE_CONFIGURATION));
+  ASSERT (PcieConfig != NULL);
+  EfiCommonLibZeroMem (PcieConfig, sizeof (PCIE_CONFIGURATION));
+
+  PegGpioData = (PEG_GPIO_DATA *) AllocatePool (sizeof (PEG_GPIO_DATA));
+  ASSERT (PegGpioData != NULL);
+  EfiCommonLibZeroMem (PegGpioData, sizeof (PEG_GPIO_DATA));
+
+  OcConfig = (OVERCLOCKING_CONFIGURATION *) AllocatePool (sizeof (OVERCLOCKING_CONFIGURATION));
+  ASSERT (OcConfig != NULL);
+  EfiCommonLibZeroMem (OcConfig, sizeof (OVERCLOCKING_CONFIGURATION));
+
+#ifdef SG_SUPPORT
+  SgGpioData = (SG_GPIO_DATA *) AllocatePool (sizeof (SG_GPIO_DATA));
+  ASSERT (SgGpioData != NULL);
+  EfiCommonLibZeroMem (SgGpioData, sizeof (SG_GPIO_DATA));
+#endif
+
+  SetMem ((VOID *) SaPlatformPolicyPpi, sizeof (SA_PLATFORM_POLICY_PPI), 0);
+
+  ///
+  /// Initialize the PPI
+  ///
+  SaPlatformPolicyPpiDesc->Flags  = EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST;
+  SaPlatformPolicyPpiDesc->Guid   = &gSaPlatformPolicyPpiGuid;
+  SaPlatformPolicyPpiDesc->Ppi    = SaPlatformPolicyPpi;
+
+  ///
+  /// Update the REVISION number
+  ///
+  SaPlatformPolicyPpi->Revision = SA_PLATFORM_POLICY_PPI_REVISION_15;
+
+  CpuFamilyId = GetCpuFamily();
+
+  ///
+  /// Initialize the Platform Configuration
+  ///
+  PlatformData->SpdAddressTable[0]  = 0xA0;
+  PlatformData->SpdAddressTable[1]  = 0xA2;
+  PlatformData->SpdAddressTable[2]  = 0xA4;
+  PlatformData->SpdAddressTable[3]  = 0xA6;
+  PlatformData->MchBar              = 0xfed10000;
+  PlatformData->DmiBar              = 0xfed18000;
+  PlatformData->EpBar               = 0xfed19000;
+  PlatformData->EdramBar            = 0xfed80000;
+  PlatformData->PciExpressBar       = (UINTN) PcdGet64 (PcdPciExpressBaseAddress);
+  PlatformData->SmbusBar            = 0xEFA0;
+  PlatformData->TsegSize            = 0x800000;
+  PlatformData->IedSize             = 0x400000;
+  PlatformData->FastBoot            = 0;
+  PlatformData->GdxcBar             = 0xFED84000;
+  PlatformData->BoardId             = 0;
+
+  SaPlatformPolicyPpi->PlatformData = PlatformData;
+  ///
+  /// Initialize the Graphics configuration
+  ///
+  GtConfig->GttSize             = 2;
+  GtConfig->IgdDvmt50PreAlloc   = 1;
+  GtConfig->InternalGraphics    = 2;
+  GtConfig->PrimaryDisplay      = 3;
+  GtConfig->ApertureSize        = 2;
+  GtConfig->PanelPowerEnable    = 0;
+  SaPlatformPolicyPpi->GtConfig = GtConfig;
+
+  ///
+  /// Initialize the Memory Configuration
+  ///
+  MemConfig->EccSupport             = 1;
+  MemConfig->DdrFreqLimit           = 0;
+  MemConfig->MaxTolud               = 0;
+  MemConfig->SpdProfileSelected     = 0;
+  MemConfig->NModeSupport           = 0;
+  MemConfig->ScramblerSupport       = 1;
+  MemConfig->PowerDownMode          = 0xFF;
+  MemConfig->PwdwnIdleCounter       = 0x80;
+  MemConfig->RankInterleave         = TRUE;
+  MemConfig->EnhancedInterleave     = TRUE;
+  MemConfig->WeaklockEn             = TRUE;
+  MemConfig->EnCmdRate              = 7;
+  MemConfig->CmdTriStateDis         = FALSE;
+  MemConfig->RefreshRate2x          = FALSE;
+  MemConfig->AutoSelfRefreshSupport = TRUE;
+  MemConfig->ExtTemperatureSupport  = TRUE;
+
+  ///
+  /// Thermal Management Configuration
+  ///
+  MemConfig->ThermalManagement  = 1;
+  MemConfig->PeciInjectedTemp   = 0;
+  MemConfig->ExttsViaTsOnBoard  = 0;
+  MemConfig->ExttsViaTsOnDimm   = 0;
+  MemConfig->VirtualTempSensor  = 0;
+  ///
+  /// Channel DIMM Disable
+  ///
+  MemConfig->DisableDimmChannel[0]  = 0;
+  MemConfig->DisableDimmChannel[1]  = 0;
+  ///
+  /// Channel Hash Configuration
+  ///
+  MemConfig->ChHashEnable         = TRUE;
+  MemConfig->ChHashMask           = 0x30CE;
+  MemConfig->ChHashInterleaveBit  = 1;
+  ///
+  /// Options for Thermal settings
+  ///
+  MemConfig->EnableExtts            = 0;
+  MemConfig->EnableCltm             = 0;
+  MemConfig->EnableOltm             = 0;
+  MemConfig->EnablePwrDn            = 1;
+  if (CpuFamilyId == EnumCpuHswUlt) {
+    MemConfig->EnablePwrDnLpddr = 0;
+  }
+  MemConfig->Refresh2X              = 0;
+  MemConfig->LpddrThermalSensor     = 1;
+  MemConfig->LockPTMregs            = 0;
+  MemConfig->UserPowerWeightsEn     = 0;
+
+  MemConfig->EnergyScaleFact        = 3;
+  MemConfig->RaplPwrFlCh1           = 0;
+  MemConfig->RaplPwrFlCh0           = 0;
+
+  MemConfig->RaplLim2Lock           = 0;
+  MemConfig->RaplLim2WindX          = 0;
+  MemConfig->RaplLim2WindY          = 0;
+  MemConfig->RaplLim2Ena            = 0;
+  MemConfig->RaplLim2Pwr            = 0;
+  MemConfig->RaplLim1WindX          = 0;
+  MemConfig->RaplLim1WindY          = 0;
+  MemConfig->RaplLim1Ena            = 0;
+  MemConfig->RaplLim1Pwr            = 0;
+
+  MemConfig->WarmThresholdCh0Dimm0  = 0xFF;
+  MemConfig->WarmThresholdCh0Dimm1  = 0xFF;
+  MemConfig->WarmThresholdCh1Dimm0  = 0xFF;
+  MemConfig->WarmThresholdCh1Dimm1  = 0xFF;
+  MemConfig->HotThresholdCh0Dimm0   = 0xFF;
+  MemConfig->HotThresholdCh0Dimm1   = 0xFF;
+  MemConfig->HotThresholdCh1Dimm0   = 0xFF;
+  MemConfig->HotThresholdCh1Dimm1   = 0xFF;
+  MemConfig->WarmBudgetCh0Dimm0     = 0xFF;
+  MemConfig->WarmBudgetCh0Dimm1     = 0xFF;
+  MemConfig->WarmBudgetCh1Dimm0     = 0xFF;
+  MemConfig->WarmBudgetCh1Dimm1     = 0xFF;
+  MemConfig->HotBudgetCh0Dimm0      = 0xFF;
+  MemConfig->HotBudgetCh0Dimm1      = 0xFF;
+  MemConfig->HotBudgetCh1Dimm0      = 0xFF;
+  MemConfig->HotBudgetCh1Dimm1      = 0xFF;
+
+  MemConfig->IdleEnergyCh0Dimm1     = 0;
+  MemConfig->IdleEnergyCh0Dimm0     = 0;
+  MemConfig->PdEnergyCh0Dimm1       = 0;
+  MemConfig->PdEnergyCh0Dimm0       = 0;
+  MemConfig->ActEnergyCh0Dimm1      = 0;
+  MemConfig->ActEnergyCh0Dimm0      = 0;
+  MemConfig->RdEnergyCh0Dimm1       = 0;
+  MemConfig->RdEnergyCh0Dimm0       = 0;
+  MemConfig->WrEnergyCh0Dimm1       = 0;
+  MemConfig->WrEnergyCh0Dimm0       = 0;
+
+  MemConfig->IdleEnergyCh1Dimm1     = 0;
+  MemConfig->IdleEnergyCh1Dimm0     = 0;
+  MemConfig->PdEnergyCh1Dimm1       = 0;
+  MemConfig->PdEnergyCh1Dimm0       = 0;
+  MemConfig->ActEnergyCh1Dimm1      = 0;
+  MemConfig->ActEnergyCh1Dimm0      = 0;
+  MemConfig->RdEnergyCh1Dimm1       = 0;
+  MemConfig->RdEnergyCh1Dimm0       = 0;
+  MemConfig->WrEnergyCh1Dimm1       = 0;
+  MemConfig->WrEnergyCh1Dimm0       = 0;
+
+  MemConfig->SrefCfgEna             = 1;
+  MemConfig->SrefCfgIdleTmr         = 0x200;
+  MemConfig->ThrtCkeMinDefeat       = 0;
+  MemConfig->ThrtCkeMinTmr          = 0x30;
+  if (CpuFamilyId == EnumCpuHswUlt) {
+    MemConfig->ThrtCkeMinDefeatLpddr = 1;
+    MemConfig->ThrtCkeMinTmrLpddr    = 0x40;
+  }
+
+
+  MemConfig->McLock               = TRUE;
+
+  MemConfig->GdxcEnable           = TRUE;
+  MemConfig->GdxcIotSize          = 4;
+  MemConfig->GdxcMotSize          = 12;
+  
+  MemConfig->MemoryTrace          = 0;
+
+  MemConfig->ECT                  = 0;
+  MemConfig->SOT                  = 1;
+  MemConfig->RDMPRT               = 1;
+  MemConfig->RCVET                = 1;
+  MemConfig->JWRL                 = 1;
+  MemConfig->FWRL                 = 0;
+  MemConfig->WRTC1D               = 1;
+  MemConfig->RDTC1D               = 1;
+  MemConfig->DIMMODTT             = 1;
+  MemConfig->WRDST                = 0;
+  MemConfig->WREQT                = 1;
+  MemConfig->RDODTT               = 1;
+  MemConfig->RDEQT                = 0;
+  MemConfig->RDAPT                = 1;
+  MemConfig->WRTC2D               = 1;
+  MemConfig->RDTC2D               = 1;
+  MemConfig->CMDVC                = 1;
+  MemConfig->WRVC2D               = 1;
+  MemConfig->RDVC2D               = 1;
+  MemConfig->LCT                  = 1;
+  MemConfig->RTL                  = 1;
+  MemConfig->TAT                  = 1;
+  MemConfig->RMT                  = 0;
+  MemConfig->MEMTST               = 0;
+  MemConfig->DIMMODTT1D           = 0;
+  MemConfig->WRSRT                = 0;
+  MemConfig->DIMMRONT             = 1;
+  MemConfig->ALIASCHK             = 1;
+  MemConfig->RCVENC1D             = 1;
+  MemConfig->RMC                  = 1;
+
+  MemConfig->RemapEnable          = TRUE;
+  MemConfig->RmtBdatEnable        = FALSE;
+  MemConfig->MrcTimeMeasure       = FALSE;
+  MemConfig->MrcFastBoot          = TRUE;
+  MemConfig->DDR3Voltage          = 0;
+  MemConfig->DDR3VoltageWaitTime  = 0;
+  MemConfig->RefClk               = 0;
+  MemConfig->Ratio                = 0;
+  MemConfig->BClkFrequency        = 100 * 1000 * 1000;
+  MemConfig->MaxRttWr             = 0;
+  ///
+  /// MrcUltPoSafeConfig
+  /// 1 to enable, 0 to disable
+  ///
+  MemConfig->MrcUltPoSafeConfig   = 0;
+
+  if (CpuFamilyId == EnumCpuHswUlt) {
+    ///
+    /// Interleaving mode of DQ/DQS pins - depends on board routing
+    ///
+    MemConfig->DqPinsInterleaved    = FALSE;
+  }
+
+  SaPlatformPolicyPpi->MemConfig  = MemConfig;
+
+  ///
+  /// Initialize the PciExpress Configuration
+  ///
+  PcieConfig->DmiVc1          = 0;
+  PcieConfig->DmiVcp          = 1;
+  PcieConfig->DmiVcm          = 1;
+  PcieConfig->DmiGen2         = 1;
+  PcieConfig->AlwaysEnablePeg = 0;
+  for (Index = 0; Index < SA_PEG_MAX_FUN; Index++) {
+    PcieConfig->PegGenx[Index] = 0;
+  }
+
+  for (Index = 0; Index < SA_PEG_MAX_FUN; Index++) {
+    PcieConfig->PowerDownUnusedBundles[Index] = 0xFF;
+  }
+
+  PcieConfig->PegGen3Equalization       = 1;
+  PcieConfig->PegSamplerCalibrate       = 0;
+  PcieConfig->PegSwingControl           = 2;
+  PcieConfig->PegComplianceTestingMode  = 0;
+
+  ///
+  /// PEG Gen3 Preset Search:                          0 = Disabled, 1 = Enabled (default)
+  /// PEG Gen3 Force Preset Search (always re-search): 0 = Disabled (default), 1 = Enabled
+  /// PEG Gen3 Preset Search Dwell Time:               400 usec
+  /// PEG Gen3 Preset Search Timing Margin Steps:      2
+  /// PEG Gen3 Preset Search Timing Start Margin:      15
+  /// PEG Gen3 Preset Search Voltage Margin Steps:     2
+  /// PEG Gen3 Preset Search Voltage Start Margin:     20
+  /// PEG Gen3 Preset Search Favor Timing:             0 = Timing + Voltage (default), 1 = Timing only
+  /// PEG Gen3 Preset Search Error Target:             4
+  ///
+  PcieConfig->PegGen3PresetSearch                   = 1;
+  PcieConfig->PegGen3ForcePresetSearch              = 0;
+  PcieConfig->PegGen3PresetSearchDwellTime          = STALL_ONE_MILLI_SECOND;
+  PcieConfig->PegGen3PresetSearchStartMargin        = 15;
+  PcieConfig->PegGen3PresetSearchVoltageStartMargin = 20;
+  PcieConfig->PegGen3PresetSearchErrorTarget        = 1;
+
+  for (Index = 0; Index < SA_PEG_MAX_LANE; Index++) {
+    PcieConfig->Gen3RootPortPreset[Index] = 8;
+    PcieConfig->Gen3EndPointPreset[Index] = 7;
+    PcieConfig->Gen3EndPointHint[Index]   = 2;
+  }
+
+  ///
+  /// Parameters for PCIe ASPM flow control
+  ///   InitPcieAspmAfterOprom:
+  ///     0 (default) - PCIe ASPM will be initialized Before Oprom
+  ///     1           - PCIe ASPM will be initialized After Oprom (required IOTRAP SMI handler)
+  ///   Note: This setting should match supported mode!
+  ///
+  ///   SaIotrapSmiAddress:
+  ///     IOTRAP SMI address for SA SMI callback handler. This should be given if platform supports InitPcieAspmAfterOprom = 1 scenario (SaLateInitSmm driver was compiled)
+  ///
+  PcieConfig->InitPcieAspmAfterOprom = FALSE;
+  PcieConfig->SaIotrapSmiAddress     = SA_IOTRAP_SMI_ADDRESS;
+
+  ///
+  /// Parameters for PCIe Gen3 device reset
+  /// Note: Refer to the Platform Design Guide (PDG) for additional information about this GPIO.
+  ///
+  PegGpioData->GpioSupport = TRUE;
+  if (PegGpioData->GpioSupport) {
+    PegGpioData->SaPegReset = (SA_GPIO_INFO *) AllocatePool (sizeof (SA_GPIO_INFO));
+    ASSERT (PegGpioData->SaPegReset != NULL);
+    if (PegGpioData->SaPegReset == NULL) {
+      return EFI_OUT_OF_RESOURCES;
+    }
+    ///
+    /// PEG Reset: GPIO 50, Active Low (Mobile PDG)
+    ///
+    PegGpioData->SaPegReset->Value  = 50;
+    PegGpioData->SaPegReset->Active = 0;
+    PcieConfig->PegGpioData         = PegGpioData;
+  }
+
+  ///
+  /// Enable/Disable RxCEM Loop back
+  /// 1=Enable, 0=Disable (default)
+  /// When enabled, Lane for loop back should be selected (0 ~ 15 and default is Lane 0)
+  ///
+  PcieConfig->RxCEMLoopback     = 0;
+  PcieConfig->RxCEMLoopbackLane = 0;
+
+  ///
+  /// Gen3 RxCTLE peaking default is 8
+  ///
+  for (Index = 0; Index < SA_PEG_MAX_BUNDLE; Index++) {
+    PcieConfig->Gen3RxCtleP[Index] = 8;
+  }
+
+  ///
+  /// Initialize the SA PEG Data pointer for saved preset search results
+  ///
+  PcieConfig->PegDataPtr = NULL;
+
+  SaPlatformPolicyPpi->PcieConfig = PcieConfig;
+
+  ///
+  /// Initialize the Overclocking Configuration
+  ///
+  OcConfig->GtVoltageOffset     = 0;
+  OcConfig->GtVoltageOverride   = 0;
+  OcConfig->GtExtraTurboVoltage = 0;
+  OcConfig->GtMaxOcTurboRatio   = 0;
+  OcConfig->SaVoltageOffset     = 0;
+  OcConfig->GtVoltageMode       = 0;
+  OcConfig->OcSupport           = 0;
+  OcConfig->IoaVoltageOffset    = 0;
+  OcConfig->IodVoltageOffset    = 0;
+
+  SaPlatformPolicyPpi->OcConfig = OcConfig;
+
+
+#ifdef SG_SUPPORT
+  ///
+  /// Initialize the Switchable Graphics Configuration
+  ///
+  ///
+  /// Switchable Graphics mode set as MUXLESS (By default)
+  ///
+  PlatformData->SgMode = SgModeMuxless;
+  PlatformData->SgSubSystemId = 0x2112;
+
+  SaPlatformPolicyPpi->PlatformData = PlatformData;
+
+  ///
+  /// Configure below based on the OEM platfrom design
+  /// Switchable Graphics GPIO support - 1=Supported, 0=Not Supported
+  ///
+  SgGpioData->GpioSupport = TRUE;
+
+  if (SgGpioData->GpioSupport) {
+    ///
+    /// Initialzie the GPIO Configuration
+    ///
+    ///
+    /// dGPU PWROK GPIO assigned
+    ///
+    SgGpioData->SgDgpuPwrOK = (SA_GPIO_INFO *) AllocatePool (sizeof (SA_GPIO_INFO));
+    ASSERT (SgGpioData->SgDgpuPwrOK != NULL);
+    if (SgGpioData->SgDgpuPwrOK == NULL) {
+      return EFI_OUT_OF_RESOURCES;
+    }
+    SgGpioData->SgDgpuPwrOK->Value = 17;
+    ///
+    /// dGPU PWROK Active High
+    ///
+    SgGpioData->SgDgpuPwrOK->Active = 1;
+
+    ///
+    /// dGPU HLD RST GPIO assigned
+    ///
+    SgGpioData->SgDgpuHoldRst = (SA_GPIO_INFO *) AllocatePool (sizeof (SA_GPIO_INFO));
+    ASSERT (SgGpioData->SgDgpuHoldRst != NULL);
+    if (SgGpioData->SgDgpuHoldRst == NULL) {
+      return EFI_OUT_OF_RESOURCES;
+    }
+    SgGpioData->SgDgpuHoldRst->Value = 50;
+    ///
+    /// dGPU HLD RST Active Low
+    ///
+    SgGpioData->SgDgpuHoldRst->Active = 0;
+
+    if (CpuFamilyId == EnumCpuHswUlt) {
+      SgGpioData->SgDgpuHoldRst->Value = 48;
+	}
+
+    ///
+    /// dGPU PWR Enable GPIO assigned
+    ///
+    SgGpioData->SgDgpuPwrEnable = (SA_GPIO_INFO *) AllocatePool (sizeof (SA_GPIO_INFO));
+    ASSERT (SgGpioData->SgDgpuPwrEnable != NULL);
+    if (SgGpioData->SgDgpuPwrEnable == NULL) {
+      return EFI_OUT_OF_RESOURCES;
+    }
+    SgGpioData->SgDgpuPwrEnable->Value = 54;
+    ///
+    /// dGPU PWR Enable Active Low
+    ///
+    SgGpioData->SgDgpuPwrEnable->Active = 0;
+
+    if (CpuFamilyId == EnumCpuHswUlt) {
+      SgGpioData->SgDgpuPwrEnable->Value = 84;
+	}
+
+    ///
+    /// dGPU_PRSNT# GPIO assigned
+    ///
+    SgGpioData->SgDgpuPrsnt = (SA_GPIO_INFO *) AllocatePool (sizeof (SA_GPIO_INFO));
+    ASSERT (SgGpioData->SgDgpuPrsnt != NULL);
+    if (SgGpioData->SgDgpuPrsnt == NULL) {
+      return EFI_OUT_OF_RESOURCES;
+    }
+    SgGpioData->SgDgpuPrsnt->Value = 67;
+    ///
+    /// dGPU_PRSNT# Active Low
+    ///
+    SgGpioData->SgDgpuPrsnt->Active = 0;
+
+    SaPlatformPolicyPpi->SgGpioData = SgGpioData;
+  }
+#endif
+
+  ///
+  /// Initialize the DataPtr for S3 resume
+  ///
+  SaPlatformPolicyPpi->S3DataPtr = NULL;
+
+  UpdatePeiSaPlatformPolicy (PeiServices, SaPlatformPolicyPpi);
+
+  ///
+  /// Install SA Platform Policy PPI
+  ///
+  Status = (**PeiServices).InstallPpi (PeiServices, SaPlatformPolicyPpiDesc);
+  ASSERT_EFI_ERROR (Status);
+
+  return Status;
+}
diff --git a/ReferenceCode/Chipset/SystemAgent/SampleCode/SaPolicyInit/Pei/SaPeiPolicyInit.dxs b/ReferenceCode/Chipset/SystemAgent/SampleCode/SaPolicyInit/Pei/SaPeiPolicyInit.dxs
new file mode 100644
index 0000000..b3b2c70
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/SampleCode/SaPolicyInit/Pei/SaPeiPolicyInit.dxs
@@ -0,0 +1,42 @@
+/** @file
+  Dependency expression source file.  
+
+@copyright
+  Copyright (c)  1999 - 2012 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains a 'Sample Driver' and is licensed as such
+  under the terms of your license agreement with Intel or your
+  vendor.  This file may be modified by the user, subject to
+  the additional terms of the license agreement
+
+**/
+  
+
+//
+// Common for R8 and R9 codebase
+//
+#include "AutoGen.h"
+#include "PeimDepex.h"
+
+//
+// BUILD_WITH_GLUELIB and BUILD_WITH_EDKII_GLUE_LIB are both "defined" in R8 codebase;
+// BUILD_WITH_EDKII_GLUE_LIB is defined in Edk-Dev-Snapshot-20070228 and later version
+// BUILD_WITH_GLUELIB and BUILD_WITH_EDKII_GLUE_LIB are "not defined" in R9 codebase.
+//
+#if defined (BUILD_WITH_GLUELIB) || defined (BUILD_WITH_EDKII_GLUE_LIB)
+#include "EfiDepex.h"
+#include EFI_PPI_DEPENDENCY (Variable)
+#endif
+
+
+DEPENDENCY_START
+
+  PEI_READ_ONLY_VARIABLE_ACCESS_PPI_GUID
+DEPENDENCY_END
diff --git a/ReferenceCode/Chipset/SystemAgent/SampleCode/SaPolicyInit/Pei/SaPeiPolicyInit.h b/ReferenceCode/Chipset/SystemAgent/SampleCode/SaPolicyInit/Pei/SaPeiPolicyInit.h
new file mode 100644
index 0000000..2cfb8e3
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/SampleCode/SaPolicyInit/Pei/SaPeiPolicyInit.h
@@ -0,0 +1,57 @@
+/** @file
+  Header file for the SaPeiPolicyInit PEIM.
+
+@copyright
+  Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains a 'Sample Driver' and is licensed as such
+  under the terms of your license agreement with Intel or your
+  vendor.  This file may be modified by the user, subject to
+  the additional terms of the license agreement
+**/
+#ifndef _SA_PEI_PLATFORM_POLICY_H_
+#define _SA_PEI_PLATFORM_POLICY_H_
+
+///
+/// External include files do NOT need to be explicitly specified in real EDKII
+/// environment
+///
+#if !defined(EDK_RELEASE_VERSION) || (EDK_RELEASE_VERSION < 0x00020000)
+#include "EdkIIGluePeim.h"
+#include "SaAccess.h"
+#include "MrcApi.h"
+#include "CpuRegs.h"
+#include "CpuPlatformLib.h"
+
+#include EFI_PPI_PRODUCER (SaPlatformPolicy)
+#include EFI_GUID_DEFINITION (SaDataHob)
+#endif
+
+#include "SaPlatformPolicyUpdatePeiLib.h"
+
+///
+/// Functions
+///
+/**
+  This PEIM performs SA PEI Platform Policy initialzation.
+
+  @param[in] FfsHeader    - Pointer to Firmware File System file header.
+  @param[in] PeiServices  - General purpose services available to every PEIM.
+
+  @retval EFI_SUCCESS - The PPI is installed and initialized.
+  @retval EFI ERRORS  - The PPI is not successfully installed.
+**/
+EFI_STATUS
+SaPeiPolicyInitEntryPoint (
+  IN EFI_FFS_FILE_HEADER       *FfsHeader,
+  IN EFI_PEI_SERVICES          **PeiServices
+  )
+;
+#endif
diff --git a/ReferenceCode/Chipset/SystemAgent/SampleCode/SaPolicyInit/Pei/SaPeiPolicyInit.inf b/ReferenceCode/Chipset/SystemAgent/SampleCode/SaPolicyInit/Pei/SaPeiPolicyInit.inf
new file mode 100644
index 0000000..175d1ba
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/SampleCode/SaPolicyInit/Pei/SaPeiPolicyInit.inf
@@ -0,0 +1,95 @@
+## @file
+#  Component description file for the SaPeiPolicyInit PEIM.
+#
+#@copyright
+#  Copyright (c)  1999 - 2012 Intel Corporation. All rights reserved
+#  This software and associated documentation (if any) is furnished
+#  under a license and may only be used or copied in accordance
+#  with the terms of the license. Except as permitted by such
+#  license, no part of this software or documentation may be
+#  reproduced, stored in a retrieval system, or transmitted in any
+#  form or by any means without the express written consent of
+#  Intel Corporation.
+#
+#  This file contains a 'Sample Driver' and is licensed as such
+#  under the terms of your license agreement with Intel or your
+#  vendor.  This file may be modified by the user, subject to
+#  the additional terms of the license agreement
+#
+
+[defines]
+BASE_NAME            = SaPeiPolicyInit
+FILE_GUID            = FD236AE7-0791-48c4-B29E-29BDEEE1A822
+COMPONENT_TYPE       = PE32_PEIM
+
+[sources.common]
+  SaPeiPolicyInit.h
+  SaPeiPolicyInit.c
+#
+# Edk II Glue Driver Entry Point
+#
+  EdkIIGluePeimEntryPoint.c
+
+
+[includes.common]
+  .
+  ../Common
+  $(EDK_SOURCE)/Foundation/Efi
+  $(EDK_SOURCE)/Foundation/Include
+  $(EDK_SOURCE)/Foundation/Efi/Include
+  $(EDK_SOURCE)/Foundation/Framework/Include
+  $(EFI_SOURCE)/$(PROJECT_SA_ROOT)
+  $(EFI_SOURCE)/$(PROJECT_SA_ROOT)/Include
+
+#
+# EDK II Glue Library utilizes some standard headers from EDK
+#
+  $(EFI_SOURCE)
+  $(EFI_SOURCE)/$(PROJECT_PCH_ROOT)
+  $(EDK_SOURCE)/Foundation
+  $(EDK_SOURCE)/Foundation/Framework
+  $(EDK_SOURCE)/Foundation/Include/IndustryStandard
+  $(EDK_SOURCE)/Foundation/Core/Dxe
+  $(EDK_SOURCE)/Foundation/Include/Pei
+  $(EDK_SOURCE)/Foundation/Library/Pei/Include
+  $(EDK_SOURCE)/Foundation/Library/Dxe/Include
+  $(EDK_SOURCE)/Foundation/Library/EdkIIGlueLib/Include
+  $(EFI_SOURCE)/$(PROJECT_PCH_ROOT)/Include
+  $(EDK_SOURCE)/Foundation/Library/EdkIIGlueLib/Include/Pcd
+  $(EFI_SOURCE)/$(PROJECT_SA_ROOT)/$(PROJECT_SA_MRC)/Pei/Source/Api
+  $(EFI_SOURCE)/$(PROJECT_SA_ROOT)/$(PROJECT_SA_MRC)/Pei/Source/Include
+  $(EFI_SOURCE)/$(PROJECT_SA_ROOT)/$(PROJECT_SA_MRC)/Pei/Source/Include/MrcRegisters
+  $(EFI_SOURCE)/$(PROJECT_CPU_ROOT)
+  $(EFI_SOURCE)/$(PROJECT_CPU_ROOT)/Include
+  $(EFI_SOURCE)/$(PROJECT_CPU_ROOT)/Include/Library
+  $(PLATFORM_ECP_PACKAGE)/Include
+
+[libraries.common]
+  $(PROJECT_PCH_FAMILY)PpiLib
+  EdkFrameworkPpiLib
+  EdkIIGlueBaseIoLibIntrinsic
+  EdkIIGlueBaseMemoryLib
+  EdkIIGluePeiDebugLibReportStatusCode
+  EdkIIGluePeiReportStatusCodeLib
+  EdkIIGluePeiServicesLib
+  EdkIIGluePeiMemoryAllocationLib
+  EdkIIGlueBasePciExpressLib
+  PeiLib
+  $(PROJECT_SA_FAMILY)PpiLib
+  PlatformPolicyUpdatePeiLib
+  CpuPlatformLib
+
+[nmake.common]
+  IMAGE_ENTRY_POINT = _ModuleEntryPoint
+  DPX_SOURCE        = SaPeiPolicyInit.dxs
+#
+# Module Entry Point
+#
+  C_FLAGS = $(C_FLAGS) -D __EDKII_GLUE_MODULE_ENTRY_POINT__=SaPeiPolicyInitEntryPoint
+  C_FLAGS = $(C_FLAGS) -D __EDKII_GLUE_BASE_IO_LIB_INTRINSIC__ \
+                       -D __EDKII_GLUE_BASE_MEMORY_LIB__ \
+                       -D __EDKII_GLUE_PEI_DEBUG_LIB_REPORT_STATUS_CODE__ \
+                       -D __EDKII_GLUE_PEI_REPORT_STATUS_CODE_LIB__ \
+                       -D __EDKII_GLUE_PEI_SERVICES_LIB__ \
+                       -D __EDKII_GLUE_PEI_MEMORY_ALLOCATION_LIB__ \
+                       -D __EDKII_GLUE_BASE_PCI_LIB_PCI_EXPRESS__
\ No newline at end of file
diff --git a/ReferenceCode/Chipset/SystemAgent/SampleCode/SaSampleCode.cif b/ReferenceCode/Chipset/SystemAgent/SampleCode/SaSampleCode.cif
new file mode 100644
index 0000000..ddaedbc
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/SampleCode/SaSampleCode.cif
@@ -0,0 +1,22 @@
+<component>
+	name = "SaSampleCode"
+	category = ModulePart
+	LocalRoot = "ReferenceCode\Chipset\SystemAgent\SampleCode"
+	RefName = "SaSampleCode"
+[files]
+"Include\AcpiBuild.dsc"	
+"Protocol\IntelSaSampleCodeProtocolLib.inf"	
+"Protocol\PciEnumerationComplete.h"	
+"Tools\GenAcpiTable.exe"	
+"Include\Cpu.h"	
+"SaPolicyInit\Dxe\SaDxePolicyInit.c"	
+"SaPolicyInit\Dxe\SaDxePolicyInit.h"	
+"SaPolicyInit\Pei\SaPeiPolicyInit.c"	
+"SaPolicyInit\Pei\SaPeiPolicyInit.h"	
+"SaPolicyInit\Dxe\SaDxePolicyInit.inf"	
+"SaPolicyInit\Dxe\SaDxePolicyInit.dxs"	
+"SaPolicyInit\Pei\SaPeiPolicyInit.dxs"	
+"SaPolicyInit\Pei\SaPeiPolicyInit.inf"	
+[parts]
+"IntelSaSampleCodePpiLib"
+<endComponent>
diff --git a/ReferenceCode/Chipset/SystemAgent/SampleCode/Tools/GenAcpiTable.exe b/ReferenceCode/Chipset/SystemAgent/SampleCode/Tools/GenAcpiTable.exe
new file mode 100644
index 0000000..5aad32c
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/SampleCode/Tools/GenAcpiTable.exe
diff --git a/ReferenceCode/Chipset/SystemAgent/SmbiosMemory/Dxe/SmBiosMemory.cif b/ReferenceCode/Chipset/SystemAgent/SmbiosMemory/Dxe/SmBiosMemory.cif
new file mode 100644
index 0000000..e3a1e70
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/SmbiosMemory/Dxe/SmBiosMemory.cif
@@ -0,0 +1,14 @@
+<component>
+	name = "SmBiosMemory"
+	category = ModulePart
+	LocalRoot = "ReferenceCode\Chipset\SystemAgent\SmbiosMemory\Dxe\"
+	RefName = "SmBiosMemory"
+[files]
+"SmBiosMemory.sdl"	
+"SmBiosMemory.mak"	
+"SmbiosMemory.c"	
+"SmbiosMemory.h"	
+"SmbiosMemory.dxs"	
+"SmbiosMemoryStrings.uni"
+"SmBiosMemory.inf"	
+<endComponent>
diff --git a/ReferenceCode/Chipset/SystemAgent/SmbiosMemory/Dxe/SmBiosMemory.inf b/ReferenceCode/Chipset/SystemAgent/SmbiosMemory/Dxe/SmBiosMemory.inf
new file mode 100644
index 0000000..3bacc7c
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/SmbiosMemory/Dxe/SmBiosMemory.inf
@@ -0,0 +1,98 @@
+## @file
+#  Component description file for SmbiosMemory Driver module
+#  {EDA39402-F375-4496-92D3-83B43CB8A76A}
+#
+#@copyright
+#  Copyright (c)  1999 - 2013 Intel Corporation. All rights reserved
+#  This software and associated documentation (if any) is furnished
+#  under a license and may only be used or copied in accordance
+#  with the terms of the license. Except as permitted by such
+#  license, no part of this software or documentation may be
+#  reproduced, stored in a retrieval system, or transmitted in any
+#  form or by any means without the express written consent of
+#  Intel Corporation.
+#
+#  This file contains a 'Sample Driver' and is licensed as such
+#  under the terms of your license agreement with Intel or your
+#  vendor.  This file may be modified by the user, subject to
+#  the additional terms of the license agreement
+#
+##
+
+[defines]
+BASE_NAME            = SmBiosMemory
+FILE_GUID            = EDA39402-F375-4496-92D3-83B43CB8A76A
+COMPONENT_TYPE       = BS_DRIVER
+
+[sources.common]
+  SmbiosMemory.h
+  SmbiosMemory.c
+  SmbiosMemoryStrings.uni
+#
+# Edk II Glue Driver Entry Point
+#
+  EdkIIGlueDxeDriverEntryPoint.c
+
+[includes.common]
+  .
+  $(DEST_DIR)
+  $(EFI_SOURCE)
+  $(EFI_SOURCE)/Include
+  $(EFI_SOURCE)/Include/IndustryStandard
+  $(EFI_SOURCE)/$(PROJECT_SA_ROOT)/Include
+  $(EFI_SOURCE)/$(PROJECT_SA_ROOT)
+  $(EDK_SOURCE)/Foundation/Framework
+  $(EDK_SOURCE)/Foundation/Framework/Include
+  $(EDK_SOURCE)/Foundation/Efi
+  $(EDK_SOURCE)/Foundation/Include
+  $(EDK_SOURCE)/Foundation/Include/IndustryStandard
+  $(EDK_SOURCE)/Foundation/Core/Dxe
+  $(EDK_SOURCE)/Foundation/Include/Pei
+  $(EDK_SOURCE)/Foundation/Framework/Include
+  $(EDK_SOURCE)/Foundation/Efi/Include
+  $(EDK_SOURCE)/Foundation
+  $(EDK_SOURCE)/Foundation/Library/Dxe/Include
+  $(EDK_SOURCE)/Foundation/Library/EdkIIGlueLib/Include
+  $(EDK_SOURCE)/Foundation/Library/Dxe/UefiEfiIfrSupportLib
+
+#
+# Typically the sample code referenced will be available in the code base already
+# So keep this include at the end to defer to the source base definition
+# and only use the sample code definition if source base does not include these files.
+#
+  $(EFI_SOURCE)/$(PROJECT_SA_ROOT)/SampleCode
+  $(EFI_SOURCE)/$(PROJECT_SA_ROOT)/SampleCode/Include
+
+[libraries.common]
+  EdkGuidLib
+  EfiCommonLib
+  EfiProtocolLib
+  UefiEfiIfrSupportLib
+  $(PROJECT_SA_FAMILY)ProtocolLib
+  EdkIIGlueBaseLib
+  EdkIIGlueBaseIoLibIntrinsic
+  EdkIIGlueDxeMemoryAllocationLib
+  EdkIIGlueDxeDebugLibReportStatusCode
+  EdkIIGlueDxeReportStatusCodeLib
+  EdkIIGlueUefiBootServicesTableLib
+  EdkIIGlueUefiRuntimeServicesTableLib
+  EdkIIGlueDxeServicesTableLib
+  EdkIIGlueHiiLib
+  EdkIIGlueBasePrintLib
+  EdkProtocolLib
+  EfiDriverLib
+
+[nmake.common]
+  IMAGE_ENTRY_POINT = _ModuleEntryPoint
+  DPX_SOURCE        = SmbiosMemory.dxs
+  C_FLAGS = $(C_FLAGS) -D __EDKII_GLUE_MODULE_ENTRY_POINT__=SmbiosMemoryEntryPoint\
+                       -D __EDKII_GLUE_BASE_LIB__ \
+                       -D __EDKII_GLUE_BASE_IO_LIB_INTRINSIC__ \
+                       -D __EDKII_GLUE_DXE_MEMORY_ALLOCATION_LIB__ \
+                       -D __EDKII_GLUE_DXE_REPORT_STATUS_CODE_LIB__ \
+                       -D __EDKII_GLUE_DXE_DEBUG_LIB_REPORT_STATUS_CODE__ \
+                       -D __EDKII_GLUE_UEFI_BOOT_SERVICES_TABLE_LIB__ \
+                       -D __EDKII_GLUE_UEFI_RUNTIME_SERVICES_TABLE_LIB__ \
+                       -D __EDKII_GLUE_DXE_SERVICES_TABLE_LIB__ \
+                       -D __EDKII_GLUE_HII_LIB__ \
+                       -D __EDKII_GLUE_BASE_PRINT_LIB__
diff --git a/ReferenceCode/Chipset/SystemAgent/SmbiosMemory/Dxe/SmBiosMemory.mak b/ReferenceCode/Chipset/SystemAgent/SmbiosMemory/Dxe/SmBiosMemory.mak
new file mode 100644
index 0000000..33553e3
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/SmbiosMemory/Dxe/SmBiosMemory.mak
@@ -0,0 +1,85 @@
+#---------------------------------------------------------------------------
+#		Create SmBiosMemory DXE driver
+#---------------------------------------------------------------------------
+EDK: SmBiosMemorySDB SmBiosMemory 
+
+SmBiosMemory: $(BUILD_DIR)\SmBiosMemory.mak SmBiosMemoryBin
+
+$(BUILD_DIR)\SmBiosMemory.mak : $(SmBiosMemory_DIR)\$(@B).cif $(SmBiosMemory_DIR)\$(@B).mak $(BUILD_RULES)
+    $(CIF2MAK) $(SmBiosMemory_DIR)\$(@B).cif $(CIF2MAK_DEFAULTS)
+
+SmBiosMemory_OBJECTS = \
+    $(BUILD_DIR)\$(SmBiosMemory_DIR)\SmBiosMemory.obj \
+    $(BUILD_DIR)\SmBiosMemoryStrings.obj \
+
+SmBiosMemory_INCLUDES=\
+    $(EdkIIGlueLib_INCLUDES)\
+    $(EDK_INCLUDES)\
+    $(INTEL_MCH_INCLUDES)\
+    $(NB_INCLUDES)\
+    /I$(UefiEfiIfrSupportLib_DIR)\
+
+SmBiosMemory_DEFINES = $(MY_DEFINES)\
+    /D"__EDKII_GLUE_MODULE_ENTRY_POINT__=SmbiosMemoryEntryPoint"\
+    /D __EDKII_GLUE_BASE_LIB__ \
+    /D __EDKII_GLUE_BASE_IO_LIB_INTRINSIC__ \
+    /D __EDKII_GLUE_DXE_MEMORY_ALLOCATION_LIB__ \
+    /D __EDKII_GLUE_DXE_REPORT_STATUS_CODE_LIB__ \
+    /D __EDKII_GLUE_DXE_DEBUG_LIB_REPORT_STATUS_CODE__ \
+    /D __EDKII_GLUE_UEFI_BOOT_SERVICES_TABLE_LIB__ \
+    /D __EDKII_GLUE_DXE_SERVICES_TABLE_LIB__ \
+    /D __EDKII_GLUE_HII_LIB__
+
+SmBiosMemory_LIBS=\
+    $(EDKGUIDLIB)\
+    $(EFICOMMONLIB)\
+    $(EFIPROTOCOLLIB)\
+!IF $(EFI_SPECIFICATION_VERSION) >= 0x0002000A
+    $(UEFIEFIIFRSUPPORTLIB)\
+!ENDIF
+    $(INTEL_SA_PROTOCOL_LIB)\
+    $(EdkIIGlueBaseLib_LIB)\
+!IF "$(x64_BUILD)"=="1"
+    $(EdkIIGlueBaseLibX64_LIB)\
+!ELSE
+    $(EdkIIGlueBaseLibIA32_LIB)\
+!ENDIF
+    $(EdkIIGlueBaseIoLibIntrinsic_LIB)\
+    $(EdkIIGlueDxeMemoryAllocationLib_LIB)\
+    $(EdkIIGlueDxeDebugLibReportStatusCode_LIB)\
+    $(EdkIIGlueDxeReportStatusCodeLib_LIB)\
+    $(EdkIIGlueUefiBootServicesTableLib_LIB)\
+    $(EdkIIGlueDxeServicesTableLib_LIB)\
+    $(EdkIIGlueHiiLib_LIB)\
+    $(EFIDRIVERLIB)\
+    $(EdkIIGlueUefiRuntimeServicesTableLib_LIB)\
+    $(EdkIIGlueBasePrintLib_LIB) \
+    $(EDKPROTOCOLLIB)\
+
+SmBiosMemoryBin : $(SmBiosMemory_LIBS)
+    $(MAKE) /$(MAKEFLAGS) $(EDKIIGLUE_DEFAULTS)\
+    /f $(BUILD_DIR)\SmBiosMemory.mak all\
+    GUID=EDA39402-F375-4496-92D3-83B43CB8A76A\
+    "MY_INCLUDES=$(SmBiosMemory_INCLUDES)" \
+    "MY_DEFINES=$(SmBiosMemory_DEFINES)"\
+    ENTRY_POINT=_ModuleEntryPoint\
+    TYPE=BS_DRIVER\
+    EDKIIModule=DXEDRIVER\
+    "OBJECTS=$(SmBiosMemory_OBJECTS)"\
+    DEPEX1=$(SmBiosMemory_DIR)\SmBiosMemory.dxs\
+    DEPEX1_TYPE=EFI_SECTION_DXE_DEPEX\
+    COMPRESS=1
+
+#---------------------------------------------------------------------------
+#    Create SmBiosMemory Setup Screens
+#---------------------------------------------------------------------------
+SmBiosMemorySDB : $(BUILD_DIR)\SmBiosMemory.mak 
+    $(MAKE) /$(MAKEFLAGS) $(BUILD_DEFAULTS)\
+    /f $(BUILD_DIR)\SmBiosMemory.mak all\
+    TYPE=SDB NAME=SmBiosMemory
+    $(STRGATHER) -dump -lang $(SUPPORTED_LANGUAGES: = -lang )\
+    -db $(BUILD_DIR)\SmBiosMemory.sdb\
+    -oh $(BUILD_DIR)\SmBiosMemoryStrDefs.h\
+    -bn SmBiosMemoryStrings\
+    -oc $(BUILD_DIR)\SmBiosMemoryStrings.c	
+    $(CC) $(CFLAGS) /Fo$(BUILD_DIR)\ $(BUILD_DIR)\SmBiosMemoryStrings.c
\ No newline at end of file
diff --git a/ReferenceCode/Chipset/SystemAgent/SmbiosMemory/Dxe/SmBiosMemory.sdl b/ReferenceCode/Chipset/SystemAgent/SmbiosMemory/Dxe/SmBiosMemory.sdl
new file mode 100644
index 0000000..945477c
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/SmbiosMemory/Dxe/SmBiosMemory.sdl
@@ -0,0 +1,32 @@
+TOKEN
+	Name  = "SMBIOS_MEMORY_SUPPORT"
+	Value  = "1"
+	Help  = "Main switch to enable SmBiosMemory support in Project"
+	TokenType = Boolean
+	TargetEQU = Yes
+	TargetMAK = Yes
+	TargetH = Yes
+	Master = Yes
+End
+
+PATH
+	Name  = "SmBiosMemory_DIR"
+End
+
+MODULE
+	Help  = "Includes SmBiosMemory.mak to Project"
+	File  = "SmBiosMemory.mak"
+End
+
+ELINK
+	Name  = "$(BUILD_DIR)\SmBiosMemory.ffs"
+	Parent  = "FV_MAIN"
+	Help  = "Add Intel SMBIOSMemory driver"
+	InvokeOrder = AfterParent
+End
+
+ELINK
+	Name  = "SmBiosMemory"
+	InvokeOrder = ReplaceParent
+End
+
diff --git a/ReferenceCode/Chipset/SystemAgent/SmbiosMemory/Dxe/SmbiosMemory.c b/ReferenceCode/Chipset/SystemAgent/SmbiosMemory/Dxe/SmbiosMemory.c
new file mode 100644
index 0000000..910c58a
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/SmbiosMemory/Dxe/SmbiosMemory.c
@@ -0,0 +1,745 @@
+/** @file
+  This driver will determine memory configuration information from the chipset
+  and memory and create SMBIOS memory structures appropriately.
+
+@copyright
+  Copyright (c) 1999 - 2013 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement
+
+**/
+#include "SmbiosMemory.h"
+EFI_DRIVER_ENTRY_POINT (SmbiosMemoryEntryPoint)
+
+extern UINT8                    SmBiosMemoryStrings[];
+MEMORY_MODULE_MANUFACTURE_LIST  MemoryModuleManufactureList[] = {
+  {
+    0,
+    0x2c,
+    L"Micron"
+  },
+  {
+    0,
+    0xad,
+    L"Hynix/Hyundai"
+  },
+  {
+    0,
+    0xce,
+    L"Samsung"
+  },
+  {
+    1,
+    0x4f,
+    L"Transcend"
+  },
+  {
+    1,
+    0x98,
+    L"Kingston"
+  },
+  {
+    2,
+    0xfe,
+    L"Elpida"
+  },
+  {
+    0xff,
+    0xff,
+    0
+  }
+};
+
+///
+/// Even SPD Addresses only as we read Words
+///
+const UINT8
+  SpdAddress[] = { 2, 8, 116, 118, 122, 124, 126, 128, 130, 132, 134, 136, 138, 140, 142, 144 };
+
+/**
+    This driver will determine memory configuration information from the chipset
+    and memory and report the memory configuration info to the DataHub.
+
+    @param[in] ImageHandle   - Handle for the image of this driver
+    @param[in] SystemTable   - Pointer to the EFI System Table
+
+    @retval EFI_SUCCESS          - if the data is successfully reported
+    @retval EFI_NOT_FOUND        - if the HOB list could not be located.
+    @retval EFI_OUT_OF_RESOURCES - if not able to get resouces.
+**/
+EFI_STATUS
+SmbiosMemoryEntryPoint (
+  IN EFI_HANDLE       ImageHandle,
+  IN EFI_SYSTEM_TABLE *SystemTable
+  )
+{
+  BOOLEAN                         Populated;
+  CHAR16                          StringBuffer2[64];
+  EFI_DATA_HUB_PROTOCOL           *DataHub;
+  DDR_ROW_CONFIG                  RowConfArray[SA_MC_MAX_SOCKETS];
+  EFI_MEMORY_SUBCLASS_DRIVER_DATA MemorySubClassData;
+  EFI_SMBUS_DEVICE_ADDRESS        SmbusSlaveAddress;
+  EFI_SMBUS_HC_PROTOCOL           *SmbusController;
+  EFI_STATUS                      Status;
+  EFI_STRING                      StringBuffer;
+  EFI_PHYSICAL_ADDRESS            BaseAddress;
+  UINT8                           Index;
+  UINT8                           *SmbusBuffer;
+  UINT16                          ArrayInstance;
+  UINT64                          DimmMemorySize;
+  UINT64                          TotalMemorySize;
+  UINT8                           Dimm;
+  UINTN                           SmbusBufferSize;
+  UINTN                           SmbusLength;
+  UINTN                           SmbusOffset;
+  UINTN                           StringBufferSize;
+  UINT8                           IndexCounter;
+  UINTN                           IdListIndex;
+  MEM_INFO_PROTOCOL               *MemInfoHob;
+  EFI_GUID                        MemInfoProtocolGuid = MEM_INFO_PROTOCOL_GUID;
+  UINT8                           ChannelASlotMap;
+  UINT8                           ChannelBSlotMap;
+  UINT8                           BitIndex;
+  UINT16                          MaxSockets;
+  UINT8                           WidthCount=0;  //AMI_OVERRIDE [EIP344598]
+  UINT8                           ChannelASlotNum;
+  UINT8                           ChannelBSlotNum;
+  BOOLEAN                         SlotPresent;
+  UINT16                          MemoryTotalWidth;
+  UINT16                          MemoryDataWidth;
+  UINT8                           i;
+
+#if (EFI_SPECIFICATION_VERSION >= 0x0002000A)
+  EFI_HANDLE                      DriverHandle;
+  EFI_HII_DATABASE_PROTOCOL       *HiiDatabase;
+  EFI_HII_PACKAGE_LIST_HEADER     *PackageList;
+  EFI_HII_HANDLE                  StringPackHandle;
+#else
+  EFI_HII_PROTOCOL                *Hii;
+  EFI_HII_HANDLE                  HiiHandle;
+  EFI_HII_PACKAGES                *PackageList;
+#endif
+  STRING_REF                      DimmToDevLocator[] = {
+    STRING_TOKEN (STR_MEMORY_SUBCLASS_DEVICE_LOCATOR_0),
+    STRING_TOKEN (STR_MEMORY_SUBCLASS_DEVICE_LOCATOR_1),
+    STRING_TOKEN (STR_MEMORY_SUBCLASS_DEVICE_LOCATOR_2),
+    STRING_TOKEN (STR_MEMORY_SUBCLASS_DEVICE_LOCATOR_3)
+  };
+
+  STRING_REF                      DimmToBankLocator[] = {
+    STRING_TOKEN (STR_MEMORY_SUBCLASS_BANK_LOCATOR_0),
+    STRING_TOKEN (STR_MEMORY_SUBCLASS_BANK_LOCATOR_1),
+    STRING_TOKEN (STR_MEMORY_SUBCLASS_BANK_LOCATOR_2),
+    STRING_TOKEN (STR_MEMORY_SUBCLASS_BANK_LOCATOR_3)
+  };
+
+  EFI_GUID                        gEfiMemorySubClassDriverGuid = EFI_MEMORY_SUBCLASS_DRIVER_GUID;
+  DXE_PLATFORM_SA_POLICY_PROTOCOL *DxePlatformSaPolicy;
+
+  DxePlatformSaPolicy           = NULL;
+
+  ///
+  /// Get the platform setup policy.
+  ///
+  Status = gBS->LocateProtocol (&gDxePlatformSaPolicyGuid, NULL, (VOID **) &DxePlatformSaPolicy);
+  ASSERT_EFI_ERROR (Status);
+
+  StringBufferSize  = (sizeof (CHAR16)) * 100;
+  StringBuffer      = AllocateZeroPool (StringBufferSize);
+  if (StringBuffer == NULL) {
+    return EFI_OUT_OF_RESOURCES;
+  }
+
+  SmbusBuffer     = NULL;
+  SmbusBufferSize = 0x100;
+  SmbusBuffer     = AllocatePool (SmbusBufferSize);
+  if (SmbusBuffer == NULL) {
+    (gBS->FreePool) (StringBuffer);
+    return EFI_OUT_OF_RESOURCES;
+  }
+
+  Status = gBS->LocateProtocol (&gEfiDataHubProtocolGuid, NULL, (VOID **) &DataHub);
+  ASSERT_EFI_ERROR (Status);
+
+  Status = gBS->LocateProtocol (&gEfiSmbusProtocolGuid, NULL, (VOID **) &SmbusController);
+  ASSERT_EFI_ERROR (Status);
+
+#if (EFI_SPECIFICATION_VERSION >= 0x0002000A)
+
+  Status = gBS->LocateProtocol (
+                  &gEfiHiiDatabaseProtocolGuid,
+                  NULL,
+                  (VOID **) &HiiDatabase
+                  );
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+  ///
+  /// Create driver handle used by HII database
+  ///
+  Status = CreateHiiDriverHandle (&DriverHandle);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+  ///
+  /// Publish our HII data
+  ///
+  PackageList = PreparePackageList (1, &gEfiMemorySubClassDriverGuid, SmBiosMemoryStrings);
+  if (PackageList == NULL) {
+    return EFI_OUT_OF_RESOURCES;
+  }
+
+  Status = HiiDatabase->NewPackageList (
+                          HiiDatabase,
+                          PackageList,
+                          DriverHandle,
+                          &StringPackHandle
+                          );
+  ASSERT_EFI_ERROR (Status);
+
+#else
+  ///
+  /// There should only be one HII protocol
+  ///
+  Status = gBS->LocateProtocol (&gEfiHiiProtocolGuid, NULL, (VOID **) &Hii);
+  ASSERT_EFI_ERROR (Status);
+
+  ///
+  /// Add our default strings to the HII database. They will be modified later.
+  ///
+  PackageList = PreparePackages (1, &gEfiMemorySubClassDriverGuid, SmBiosMemoryStrings);
+  Status      = Hii->NewPack (Hii, PackageList, &HiiHandle);
+
+#endif
+
+  (gBS->FreePool) (PackageList);
+
+  Status = gBS->LocateProtocol (&MemInfoProtocolGuid, NULL, (VOID **) &MemInfoHob);
+  ASSERT_EFI_ERROR (Status);
+  ///
+  /// Data for TYPE 16 SMBIOS Structure
+  ///
+  ///
+  /// Create physical array and associated data for all mainboard memory
+  ///
+  ArrayInstance                         = 1;
+  TotalMemorySize                       = 0;
+  MemorySubClassData.Header.Version     = EFI_MEMORY_SUBCLASS_VERSION;
+  MemorySubClassData.Header.HeaderSize  = sizeof (EFI_SUBCLASS_TYPE1_HEADER);
+  MemorySubClassData.Header.Instance    = ArrayInstance;
+  MemorySubClassData.Header.SubInstance = EFI_SUBCLASS_INSTANCE_NON_APPLICABLE;
+  MemorySubClassData.Header.RecordType  = EFI_MEMORY_ARRAY_LOCATION_RECORD_NUMBER;
+
+  MemorySubClassData.Record.ArrayLocationData.MemoryArrayLocation = EfiMemoryArrayLocationSystemBoard;
+  MemorySubClassData.Record.ArrayLocationData.MemoryArrayUse      = EfiMemoryArrayUseSystemMemory;
+
+  ///
+  /// Detect ECC
+  ///
+  if (MemInfoHob->MemInfoData.EccSupport) {
+    MemorySubClassData.Record.ArrayLocationData.MemoryErrorCorrection = EfiMemoryErrorCorrectionSingleBitEcc;
+  } else {
+    MemorySubClassData.Record.ArrayLocationData.MemoryErrorCorrection = EfiMemoryErrorCorrectionNone;
+  }
+  ///
+  /// Get the Memory DIMM info from platform policy protocols
+  ///
+  ChannelASlotMap = DxePlatformSaPolicy->MemoryConfig->ChannelASlotMap;
+  ChannelBSlotMap = DxePlatformSaPolicy->MemoryConfig->ChannelBSlotMap;
+  ChannelASlotNum = 0;
+  ChannelBSlotNum = 0;
+  for (BitIndex = 0; BitIndex < 8; BitIndex++) {
+    if ((ChannelASlotMap >> BitIndex) & BIT0) {
+      ChannelASlotNum++;
+    }
+
+    if ((ChannelBSlotMap >> BitIndex) & BIT0) {
+      ChannelBSlotNum++;
+    }
+  }
+
+  MaxSockets  = ChannelASlotNum + ChannelBSlotNum;
+  MemorySubClassData.Record.ArrayLocationData.MaximumMemoryCapacity = MAX_RANK_CAPACITY * SA_MC_MAX_SIDES * MaxSockets;
+  MemorySubClassData.Record.ArrayLocationData.NumberMemoryDevices   = (UINT16) (MaxSockets);
+
+  ///
+  /// Report top level physical array to datahub
+  /// This will translate into a Type 16 SMBIOS Record
+  ///
+  Status = DataHub->LogData (
+                      DataHub,
+                      &gEfiMemorySubClassGuid,
+                      &gEfiMemorySubClassDriverGuid,
+                      EFI_DATA_RECORD_CLASS_DATA,
+                      &MemorySubClassData,
+                      sizeof (EFI_SUBCLASS_TYPE1_HEADER) + sizeof (EFI_MEMORY_ARRAY_LOCATION_DATA)
+                      );
+  if (EFI_ERROR (Status)) {
+    goto CleanAndExit;
+  }
+  ///
+  /// Get Memory size parameters for each rank
+  ///
+  ///
+  /// We start from a base address of 0 for rank 0. We calculate the base address based on the DIMM size.
+  ///
+  BaseAddress = 0;
+
+  for (Dimm = 0; Dimm < SA_MC_MAX_SLOTS; Dimm++) {
+    ///
+    /// Channel 0
+    ///
+    RowConfArray[Dimm].BaseAddress  = BaseAddress;
+    RowConfArray[Dimm].RowLength    = LShiftU64 (MemInfoHob->MemInfoData.dimmSize[Dimm], 20);
+    BaseAddress += RowConfArray[Dimm].RowLength;
+    ///
+    /// Channel 1
+    ///
+    RowConfArray[Dimm + SA_MC_MAX_SLOTS].BaseAddress  = BaseAddress;
+    RowConfArray[Dimm + SA_MC_MAX_SLOTS].RowLength    = LShiftU64 (MemInfoHob->MemInfoData.dimmSize[Dimm + SA_MC_MAX_SLOTS], 20);
+    BaseAddress += RowConfArray[Dimm + SA_MC_MAX_SLOTS].RowLength;
+
+  }
+  ///
+  /// For each existed socket whether it is populated or not generate Type 17.
+  /// Type 20 is optional for existed and populated socket.
+  ///
+  /// The Desktop and mobile only support 2 channels * 2 slots per channel = 4 sockets totally
+  /// So there is rule here for Desktop and mobile that there are no more 4 DIMMS totally in a system:
+  ///  Channel A/ Slot 0 --> SpdAddressTable[0] --> DimmToDevLocator[0] --> MemInfoHobProtocol.MemInfoData.dimmSize[0]
+  ///  Channel A/ Slot 1 --> SpdAddressTable[1] --> DimmToDevLocator[1] --> MemInfoHobProtocol.MemInfoData.dimmSize[1]
+  ///  Channel B/ Slot 0 --> SpdAddressTable[2] --> DimmToDevLocator[2] --> MemInfoHobProtocol.MemInfoData.dimmSize[2]
+  ///  Channel B/ Slot 1 --> SpdAddressTable[3] --> DimmToDevLocator[3] --> MemInfoHobProtocol.MemInfoData.dimmSize[3]
+  ///
+  for (Dimm = 0; Dimm < SA_MC_MAX_SOCKETS; Dimm++) {
+    ///
+    /// Use channel slot map to check whether the Socket is supported in this SKU, some SKU only has 2 Sockets totally
+    ///
+    SlotPresent = FALSE;
+    if (Dimm < 2) {
+      if (ChannelASlotMap & (1 << Dimm)) {
+        SlotPresent = TRUE;
+      }
+    } else {
+      if (ChannelBSlotMap & (1 << (Dimm - 2))) {
+        SlotPresent = TRUE;
+      }
+    }
+    ///
+    /// Don't create Type 17 and Type 20 items for non-existing socket
+    ///
+    if (!SlotPresent) {
+      continue;
+    }
+    ///
+    /// Generate Memory Device info (Type 17)
+    ///
+    ZeroMem (SmbusBuffer, SmbusBufferSize);
+    ///
+    /// Only read the SPD data if the DIMM is populated in the slot.
+    ///
+    Populated = MemInfoHob->MemInfoData.DimmExist[Dimm];
+    if (Populated) {
+      WidthCount++;           //AMI_OVERRIDE [EIP344598]
+      ///
+      /// Read the SPD for this DIMM
+      ///
+      SmbusSlaveAddress.SmbusDeviceAddress = (DxePlatformSaPolicy->MemoryConfig->SpdAddressTable[Dimm]) >> 1;
+
+      ///
+      /// Read only needed values from SMBus or DimmsSpdData pointer to improve performance.
+      ///
+      for (i = 0; i < sizeof SpdAddress; i++) {
+        SmbusOffset = SpdAddress[i];
+        if (MemInfoHob->MemInfoData.DimmsSpdData[Dimm] == NULL) {
+          SmbusLength = 2;
+          Status = SmbusController->Execute (
+                                      SmbusController,
+                                      SmbusSlaveAddress,
+                                      SmbusOffset,
+                                      EfiSmbusReadWord,
+                                      FALSE,
+                                      &SmbusLength,
+                                      &SmbusBuffer[SmbusOffset]
+                                      );
+          if (EFI_ERROR (Status)) {
+            Populated = FALSE;
+            break;
+          }
+        } else {
+          *(UINT16 *) (SmbusBuffer + SmbusOffset) = *(UINT16 *) (MemInfoHob->MemInfoData.DimmsSpdData[Dimm] + SmbusOffset);
+        }
+      }
+    }
+
+    ZeroMem (&MemorySubClassData, sizeof (EFI_MEMORY_SUBCLASS_DRIVER_DATA));
+
+    ///
+    /// Use SPD data to generate Device Type info
+    ///
+    MemorySubClassData.Header.Version                       = EFI_MEMORY_SUBCLASS_VERSION;
+    MemorySubClassData.Header.HeaderSize                    = sizeof (EFI_SUBCLASS_TYPE1_HEADER);
+    MemorySubClassData.Header.Instance                      = ArrayInstance;
+    MemorySubClassData.Header.SubInstance                   = (UINT16) (Dimm + 1);
+    MemorySubClassData.Header.RecordType                    = EFI_MEMORY_ARRAY_LINK_RECORD_NUMBER;
+
+    MemorySubClassData.Record.ArrayLink.MemoryDeviceLocator = DimmToDevLocator[Dimm];
+    MemorySubClassData.Record.ArrayLink.MemoryBankLocator   = DimmToBankLocator[Dimm];
+
+#ifdef MEMORY_ASSET_TAG
+    StrCpy (StringBuffer, MEMORY_ASSET_TAG);
+    MemorySubClassData.Record.ArrayLink.MemoryAssetTag = (STRING_REF) 0;
+
+#if (EFI_SPECIFICATION_VERSION >= 0x0002000A)
+    Status = IfrLibNewString (StringPackHandle, &MemorySubClassData.Record.ArrayLink.MemoryAssetTag, StringBuffer);
+    ASSERT_EFI_ERROR (Status);
+#else
+    Status = Hii->NewString (
+                    Hii,
+                    NULL,
+                    HiiHandle,
+                    &MemorySubClassData.Record.ArrayLink.MemoryAssetTag,
+                    StringBuffer
+                    );
+    ASSERT_EFI_ERROR (Status);
+#endif
+
+#else
+    MemorySubClassData.Record.ArrayLink.MemoryAssetTag = STRING_TOKEN (STR_MEMORY_SUBCLASS_DEFAULT_ASSET_TAG);
+#endif
+
+    MemorySubClassData.Record.ArrayLink.MemoryArrayLink.ProducerName    = gEfiMemorySubClassDriverGuid;
+    MemorySubClassData.Record.ArrayLink.MemoryArrayLink.Instance        = ArrayInstance;
+    MemorySubClassData.Record.ArrayLink.MemoryArrayLink.SubInstance     = EFI_SUBCLASS_INSTANCE_NON_APPLICABLE;
+    MemorySubClassData.Record.ArrayLink.MemorySubArrayLink.ProducerName = gEfiMemorySubClassDriverGuid;
+    MemorySubClassData.Record.ArrayLink.MemorySubArrayLink.SubInstance  = EFI_SUBCLASS_INSTANCE_NON_APPLICABLE;
+    ///
+    /// Set MemoryType value to DDR3 (0x18)
+    ///
+    MemorySubClassData.Record.ArrayLink.MemoryType = EfiMemoryTypeDdr3;
+
+    ///
+    /// According to SMBIOS 2.6.1 Specification - Appendix A Conformance Guidelines
+    /// 4.8.7:  Form Factor is not 00h (Reserved) or 02h (Unknown).
+    ///
+    if (Populated) {
+      switch (SmbusBuffer[DDR_MTYPE_SPD_OFFSET] & DDR_MTYPE_SPD_MASK) {
+      case DDR_MTYPE_SODIMM:
+        MemorySubClassData.Record.ArrayLink.MemoryFormFactor = EfiMemoryFormFactorSodimm;
+        break;
+
+      case DDR_MTYPE_RDIMM:
+      case DDR_MTYPE_MINI_RDIMM:
+        MemorySubClassData.Record.ArrayLink.MemoryFormFactor = EfiMemoryFormFactorRimm;
+        break;
+
+      case DDR_MTYPE_UDIMM:
+      case DDR_MTYPE_MICRO_DIMM:
+      case DDR_MTYPE_MINI_UDIMM:
+      default:
+        MemorySubClassData.Record.ArrayLink.MemoryFormFactor = EfiMemoryFormFactorDimm;
+      }
+      ///
+      /// Show name for known manufacturer or ID for unknown manufacturer
+      ///
+      StrCpy (StringBuffer, L"");
+
+      ///
+      /// Calculate index counter
+      /// Clearing Bit7 as it is the Parity Bit for Byte 117
+      ///
+      IndexCounter = SmbusBuffer[117] & (~0x80);
+
+      ///
+      /// Converter memory manufacturer ID to string
+      ///
+      for (IdListIndex = 0; MemoryModuleManufactureList[IdListIndex].Index != 0xff; IdListIndex++) {
+        if (MemoryModuleManufactureList[IdListIndex].Index == IndexCounter &&
+            MemoryModuleManufactureList[IdListIndex].ManufactureId == SmbusBuffer[118]
+            ) {
+          StrCpy (StringBuffer, MemoryModuleManufactureList[IdListIndex].ManufactureName);
+          break;
+        }
+      }
+      ///
+      /// Use original data if no conversion information in conversion table
+      ///
+      if (!(*StringBuffer)) {
+        for (Index = 117; Index < 119; Index++) {
+          ///
+          /// --cr--         EfiValueToHexStr(StringBuffer2, SmbusBuffer[Index], PREFIX_ZERO, 2);
+          ///
+          UnicodeValueToString (StringBuffer2, PREFIX_ZERO, SmbusBuffer[Index], 2);
+          StrCat (StringBuffer, StringBuffer2);
+        }
+      }
+
+      MemorySubClassData.Record.ArrayLink.MemoryManufacturer = (STRING_REF) 0;
+#if (EFI_SPECIFICATION_VERSION >= 0x0002000A)
+      Status = IfrLibNewString (
+                StringPackHandle,
+                &MemorySubClassData.Record.ArrayLink.MemoryManufacturer,
+                StringBuffer
+                );
+      ASSERT_EFI_ERROR (Status);
+#else
+      Status = Hii->NewString (
+                      Hii,
+                      NULL,
+                      HiiHandle,
+                      &MemorySubClassData.Record.ArrayLink.MemoryManufacturer,
+                      StringBuffer
+                      );
+      ASSERT_EFI_ERROR (Status);
+#endif
+      StrCpy (StringBuffer, L"");
+      for (Index = 122; Index < 126; Index++) {
+        EfiValueToHexStr(StringBuffer2, SmbusBuffer[Index], PREFIX_ZERO, 2);
+        StrCat (StringBuffer, StringBuffer2);
+      }
+
+      MemorySubClassData.Record.ArrayLink.MemorySerialNumber = (STRING_REF) 0;
+#if (EFI_SPECIFICATION_VERSION >= 0x0002000A)
+      Status = IfrLibNewString (
+                StringPackHandle,
+                &MemorySubClassData.Record.ArrayLink.MemorySerialNumber,
+                StringBuffer
+                );
+      ASSERT_EFI_ERROR (Status);
+#else
+      Status = Hii->NewString (
+                      Hii,
+                      NULL,
+                      HiiHandle,
+                      &MemorySubClassData.Record.ArrayLink.MemorySerialNumber,
+                      StringBuffer
+                      );
+      ASSERT_EFI_ERROR (Status);
+#endif
+      StrCpy (StringBuffer, L"");
+      for (Index = 128; Index < 146; Index++) {
+        UnicodeSPrint (
+          StringBuffer2,
+          4,
+          L"%c",
+          SmbusBuffer[Index]
+          );
+        StrCat (StringBuffer, StringBuffer2);
+      }
+
+      MemorySubClassData.Record.ArrayLink.MemoryPartNumber = (STRING_REF) 0;
+#if (EFI_SPECIFICATION_VERSION >= 0x0002000A)
+      Status = IfrLibNewString (StringPackHandle, &MemorySubClassData.Record.ArrayLink.MemoryPartNumber, StringBuffer);
+      ASSERT_EFI_ERROR (Status);
+#else
+      Status = Hii->NewString (
+                      Hii,
+                      NULL,
+                      HiiHandle,
+                      &MemorySubClassData.Record.ArrayLink.MemoryPartNumber,
+                      StringBuffer
+                      );
+      ASSERT_EFI_ERROR (Status);
+#endif
+      ///
+      /// Get the Memory TotalWidth and DataWidth info for DDR3
+      /// refer to DDR3 SPD 1.0 spec, Byte 8: Module Memory Bus Width
+      /// SPD Offset 8 Bits [2:0] DataWidth aka Primary Bus Width
+      /// SPD Offset 8 Bits [4:3] Bus Width extension for ECC
+      ///
+      MemoryDataWidth   = 8 * (1 << (SmbusBuffer[8] & 0x07));
+      MemoryTotalWidth  = MemoryDataWidth + 8 * (SmbusBuffer[8] & 0x18);
+      MemorySubClassData.Record.ArrayLink.MemoryTotalWidth  = MemoryTotalWidth;
+      MemorySubClassData.Record.ArrayLink.MemoryDataWidth   = MemoryDataWidth;
+      DimmMemorySize = RowConfArray[Dimm].RowLength;
+
+      TotalMemorySize += DimmMemorySize;
+      MemorySubClassData.Record.ArrayLink.MemoryDeviceSize              = DimmMemorySize;
+      MemorySubClassData.Record.ArrayLink.MemoryTypeDetail.Synchronous  = 1;
+      if (MemorySubClassData.Record.ArrayLink.MemoryFormFactor == EfiMemoryFormFactorRimm) {
+        MemorySubClassData.Record.ArrayLink.MemoryTypeDetail.Rambus = 1;
+      }
+
+      MemorySubClassData.Record.ArrayLink.MemorySpeed       = MemInfoHob->MemInfoData.ddrFreq;
+      MemorySubClassData.Record.ArrayLink.MemoryAttributes  = MemInfoHob->MemInfoData.RankInDimm[Dimm] & 0x0F;
+    } else {
+      ///
+      /// Memory is not Populated in this slot.
+      ///
+      StrCpy (StringBuffer, L"");
+      MemorySubClassData.Record.ArrayLink.MemoryManufacturer = (STRING_REF) 0;
+#if (EFI_SPECIFICATION_VERSION >= 0x0002000A)
+      Status = IfrLibNewString (
+                StringPackHandle,
+                &MemorySubClassData.Record.ArrayLink.MemoryManufacturer,
+                StringBuffer
+                );
+      ASSERT_EFI_ERROR (Status);
+#else
+      Status = Hii->NewString (
+                      Hii,
+                      NULL,
+                      HiiHandle,
+                      &MemorySubClassData.Record.ArrayLink.MemoryManufacturer,
+                      StringBuffer
+                      );
+      ASSERT_EFI_ERROR (Status);
+#endif
+      MemorySubClassData.Record.ArrayLink.MemorySerialNumber = (STRING_REF) 0;
+#if (EFI_SPECIFICATION_VERSION >= 0x0002000A)
+      Status = IfrLibNewString (
+                StringPackHandle,
+                &MemorySubClassData.Record.ArrayLink.MemorySerialNumber,
+                StringBuffer
+                );
+      ASSERT_EFI_ERROR (Status);
+#else
+      Status = Hii->NewString (
+                      Hii,
+                      NULL,
+                      HiiHandle,
+                      &MemorySubClassData.Record.ArrayLink.MemorySerialNumber,
+                      StringBuffer
+                      );
+      ASSERT_EFI_ERROR (Status);
+#endif
+
+      MemorySubClassData.Record.ArrayLink.MemoryPartNumber = (STRING_REF) 0;
+#if (EFI_SPECIFICATION_VERSION >= 0x0002000A)
+      Status = IfrLibNewString (StringPackHandle, &MemorySubClassData.Record.ArrayLink.MemoryPartNumber, StringBuffer);
+      ASSERT_EFI_ERROR (Status);
+#else
+      Status = Hii->NewString (
+                      Hii,
+                      NULL,
+                      HiiHandle,
+                      &MemorySubClassData.Record.ArrayLink.MemoryPartNumber,
+                      StringBuffer
+                      );
+      ASSERT_EFI_ERROR (Status);
+#endif
+      DimmMemorySize  = 0;
+      MemorySubClassData.Record.ArrayLink.MemorySpeed       = 0;
+      MemorySubClassData.Record.ArrayLink.MemoryDeviceSize  = 0;
+      MemorySubClassData.Record.ArrayLink.MemoryType        = EfiMemoryTypeUnknown;
+      MemorySubClassData.Record.ArrayLink.MemoryFormFactor  = EfiMemoryFormFactorDimm;
+    }
+    ///
+    /// Generate Memory Device info (Type 17)
+    ///
+    Status = DataHub->LogData (
+                        DataHub,
+                        &gEfiMemorySubClassGuid,
+                        &gEfiMemorySubClassDriverGuid,
+                        EFI_DATA_RECORD_CLASS_DATA,
+                        &MemorySubClassData,
+                        sizeof (EFI_SUBCLASS_TYPE1_HEADER) + sizeof (EFI_MEMORY_ARRAY_LINK)
+                        );
+    if (EFI_ERROR (Status)) {
+      goto CleanAndExit;
+    }
+    ///
+    /// Memory Device Mapped Address (Type 20) is optional and it will not be generated by RC
+    ///
+// ...AMI_OVERRIDE... support Type 20
+    if ((Populated) && (DimmMemorySize != 0)) {
+      ///
+      /// Generate Memory Device Mapped Address info (Type 20)
+      ///
+      MemorySubClassData.Header.Instance    = ArrayInstance;
+      MemorySubClassData.Header.SubInstance = (UINT16) (Dimm + 1);
+      MemorySubClassData.Header.RecordType  = EFI_MEMORY_DEVICE_START_ADDRESS_RECORD_NUMBER;
+
+      MemorySubClassData.Record.DeviceStartAddress.MemoryDeviceStartAddress = RowConfArray[Dimm].BaseAddress;
+      MemorySubClassData.Record.DeviceStartAddress.MemoryDeviceEndAddress = MemorySubClassData.Record.
+          DeviceStartAddress.MemoryDeviceStartAddress +
+        DimmMemorySize -
+        1;
+      ///
+      /// 1 or 2 will be applicable for lock step mode
+      ///
+      MemorySubClassData.Record.DeviceStartAddress.MemoryDevicePartitionRowPosition       = 0xFF;
+
+      MemorySubClassData.Record.DeviceStartAddress.PhysicalMemoryDeviceLink.ProducerName  = gEfiMemorySubClassDriverGuid;
+      MemorySubClassData.Record.DeviceStartAddress.PhysicalMemoryDeviceLink.Instance      = ArrayInstance;
+      MemorySubClassData.Record.DeviceStartAddress.PhysicalMemoryDeviceLink.SubInstance   = (UINT16) (Dimm + 1);
+      MemorySubClassData.Record.DeviceStartAddress.PhysicalMemoryArrayLink.ProducerName   = gEfiMemorySubClassDriverGuid;
+      MemorySubClassData.Record.DeviceStartAddress.PhysicalMemoryArrayLink.Instance       = ArrayInstance;
+      MemorySubClassData.Record.DeviceStartAddress.PhysicalMemoryArrayLink.SubInstance = EFI_SUBCLASS_INSTANCE_NON_APPLICABLE;
+
+      ///
+      /// Set Interleave Data Depth and Position.
+      ///
+      if (((Dimm >= SA_MC_MAX_SLOTS) && (MemInfoHob->MemInfoData.DimmExist[Dimm - SA_MC_MAX_SLOTS])) ||
+          ((Dimm < SA_MC_MAX_SLOTS) && (MemInfoHob->MemInfoData.DimmExist[Dimm + SA_MC_MAX_SLOTS]))
+          ) {
+        ///
+        /// If DIMMs on both channels are populated then Interleaved Data Depth is 2 and Interleave Position is 1 or 2
+        ///
+        MemorySubClassData.Record.DeviceStartAddress.MemoryDeviceInterleaveDataDepth = (UINT8) (MaxSockets >> 1);
+        MemorySubClassData.Record.DeviceStartAddress.MemoryDeviceInterleavePosition = (UINT8) (1 << (Dimm >= (MaxSockets >> 1)));
+      } else {
+        ///
+        /// Interleaved Data Depth and Position is 1
+        ///
+        MemorySubClassData.Record.DeviceStartAddress.MemoryDeviceInterleaveDataDepth  = 1;
+        MemorySubClassData.Record.DeviceStartAddress.MemoryDeviceInterleavePosition   = 1;
+      }
+      ///
+      /// Generate Memory Device Mapped Address info (Type 20)
+      ///
+      Status = DataHub->LogData (
+                          DataHub,
+                          &gEfiMemorySubClassGuid,
+                          &gEfiMemorySubClassDriverGuid,
+                          EFI_DATA_RECORD_CLASS_DATA,
+                          &MemorySubClassData,
+                          sizeof (EFI_SUBCLASS_TYPE1_HEADER) + sizeof (EFI_MEMORY_DEVICE_START_ADDRESS)
+                          );
+      if (EFI_ERROR (Status)) {
+        goto CleanAndExit;
+      }
+    }
+// ...AMI_OVERRIDE... support Type 20 end
+  }
+  ///
+  /// Generate Memory Array Mapped Address info (TYPE 19)
+  ///
+  MemorySubClassData.Header.Instance    = ArrayInstance;
+  MemorySubClassData.Header.SubInstance = EFI_SUBCLASS_INSTANCE_NON_APPLICABLE;
+  MemorySubClassData.Header.RecordType  = EFI_MEMORY_ARRAY_START_ADDRESS_RECORD_NUMBER;
+
+  MemorySubClassData.Record.ArrayStartAddress.MemoryArrayStartAddress               = 0;
+  MemorySubClassData.Record.ArrayStartAddress.MemoryArrayEndAddress                 = TotalMemorySize - 1;
+  MemorySubClassData.Record.ArrayStartAddress.PhysicalMemoryArrayLink.ProducerName  = gEfiMemorySubClassDriverGuid;
+  MemorySubClassData.Record.ArrayStartAddress.PhysicalMemoryArrayLink.Instance      = ArrayInstance;
+  MemorySubClassData.Record.ArrayStartAddress.PhysicalMemoryArrayLink.SubInstance = EFI_SUBCLASS_INSTANCE_NON_APPLICABLE;
+  //MemorySubClassData.Record.ArrayStartAddress.MemoryArrayPartitionWidth = (UINT16) (MaxSockets);  //AMI_OVERRIDE [EIP344598]
+  MemorySubClassData.Record.ArrayStartAddress.MemoryArrayPartitionWidth = WidthCount;  //AMI_OVERRIDE [EIP344598]
+  ///
+  /// Generate Memory Array Mapped Address info (TYPE 19)
+  ///
+  Status = DataHub->LogData (
+                      DataHub,
+                      &gEfiMemorySubClassGuid,
+                      &gEfiMemorySubClassDriverGuid,
+                      EFI_DATA_RECORD_CLASS_DATA,
+                      &MemorySubClassData,
+                      sizeof (EFI_SUBCLASS_TYPE1_HEADER) + sizeof (EFI_MEMORY_ARRAY_START_ADDRESS)
+                      );
+CleanAndExit:
+  (gBS->FreePool) (SmbusBuffer);
+  (gBS->FreePool) (StringBuffer);
+  return Status;
+}
diff --git a/ReferenceCode/Chipset/SystemAgent/SmbiosMemory/Dxe/SmbiosMemory.dxs b/ReferenceCode/Chipset/SystemAgent/SmbiosMemory/Dxe/SmbiosMemory.dxs
new file mode 100644
index 0000000..5675c94
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/SmbiosMemory/Dxe/SmbiosMemory.dxs
@@ -0,0 +1,58 @@
+/** @file
+  Dependency expression file for the MemorySubClass Driver.
+
+@copyright
+  Copyright (c)  1999 - 2012 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains a 'Sample Driver' and is licensed as such
+  under the terms of your license agreement with Intel or your
+  vendor.  This file may be modified by the user, subject to
+  the additional terms of the license agreement
+
+**/
+
+//
+// Common for R8 and R9 codebase
+//
+#include "AutoGen.h"
+#include "DxeDepex.h"
+
+//
+// BUILD_WITH_GLUELIB and BUILD_WITH_EDKII_GLUE_LIB are both "defined" in R8 codebase;
+// BUILD_WITH_EDKII_GLUE_LIB is defined in Edk-Dev-Snapshot-20070228 and later version
+// BUILD_WITH_GLUELIB and BUILD_WITH_EDKII_GLUE_LIB are "not defined" in R9 codebase.
+//
+#if defined (BUILD_WITH_GLUELIB) || defined (BUILD_WITH_EDKII_GLUE_LIB)
+#include "EfiDepex.h"
+
+#include EFI_PROTOCOL_DEFINITION (DataHub)
+#if (EFI_SPECIFICATION_VERSION >= 0x0002000A)
+#include EFI_PROTOCOL_DEFINITION (HiiDatabase)
+#else
+#include EFI_PROTOCOL_DEFINITION (Hii)
+#endif
+#include EFI_PROTOCOL_DEFINITION (Smbus)
+#include EFI_PROTOCOL_DEFINITION (PciRootBridgeIo)
+#include EFI_PROTOCOL_DEPENDENCY (SaPlatformPolicy)
+#include EFI_PROTOCOL_DEPENDENCY (MemInfo)
+#endif
+
+DEPENDENCY_START
+  EFI_DATA_HUB_PROTOCOL_GUID            AND
+#if (EFI_SPECIFICATION_VERSION >= 0x0002000A)
+    EFI_HII_DATABASE_PROTOCOL_GUID AND
+#else
+    EFI_HII_PROTOCOL_GUID AND
+#endif
+  EFI_SMBUS_HC_PROTOCOL_GUID            AND
+  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_GUID  AND
+  DXE_PLATFORM_SA_POLICY_GUID           AND
+  MEM_INFO_PROTOCOL_GUID 
+DEPENDENCY_END
diff --git a/ReferenceCode/Chipset/SystemAgent/SmbiosMemory/Dxe/SmbiosMemory.h b/ReferenceCode/Chipset/SystemAgent/SmbiosMemory/Dxe/SmbiosMemory.h
new file mode 100644
index 0000000..9e0a641
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/SmbiosMemory/Dxe/SmbiosMemory.h
@@ -0,0 +1,127 @@
+/** @file
+  Header file for the SMBIOS Memory Driver.
+  This driver will determine memory configuration information from the chipset
+  and memory and create SMBIOS Memory structures appropriately.
+
+@copyright
+  Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement
+**/
+#ifndef _SMBIOS_MEMORY_H_
+#define _SMBIOS_MEMORY_H_
+
+#include "EdkIIGlueDxe.h"
+#if (EFI_SPECIFICATION_VERSION >= 0x0002000A)
+#include "UefiIfrLibrary.h"
+#include EFI_PROTOCOL_DEPENDENCY (HiiDatabase)
+#include EFI_PROTOCOL_DEPENDENCY (HiiString)
+#else
+#include EFI_PROTOCOL_DEPENDENCY (Hii)
+#endif
+#include "SaAccess.h"
+#include "CpuFuncs.h"
+#include "Cpu.h"
+
+///
+/// This is the generated header file which includes whatever needs to be exported (strings + IFR)
+///
+#include "SmbiosMemoryStrDefs.h"
+
+///
+/// Driver Consumed Protocol Prototypes
+///
+#include EFI_PROTOCOL_DEPENDENCY (DataHub)
+#include EFI_PROTOCOL_DEPENDENCY (Smbus)
+#include EFI_PROTOCOL_DEPENDENCY (MemInfo)
+#include EFI_PROTOCOL_DEPENDENCY (PciRootBridgeIo)
+#include EFI_PROTOCOL_DEPENDENCY (SaPlatformPolicy)
+
+///
+/// Driver private data
+///
+#include EFI_GUID_DEFINITION (DataHubRecords)
+
+#define EFI_MEMORY_SUBCLASS_DRIVER_GUID \
+  { \
+    0x1767CEED, 0xDB82, 0x47cd, 0xBF, 0x2B, 0x68, 0x45, 0x8A, 0x8C, 0xCF, 0xFF \
+  }
+
+///
+/// Memory
+///
+#define MEM_FRQCY_BIT_SHIFT 1
+
+#define MAD_DIMM_CH0        0x5004
+#define MAD_DIMM_CH1        0x5008
+
+///
+/// Memory module type definition in DDR3 SPD Data
+///
+#define DDR_MTYPE_SPD_OFFSET  3     ///< Module type, offset 3, bits (3:0)
+#define DDR_MTYPE_SPD_MASK    0x0F  ///< Module Type mask
+#define DDR_MTYPE_RDIMM       0x01  ///< Registered DIMM Memory
+#define DDR_MTYPE_UDIMM       0x02  ///< Unbuffered DIMM Memory
+#define DDR_MTYPE_SODIMM      0x03  ///< Small Outline DIMM Memory
+#define DDR_MTYPE_MICRO_DIMM  0x04  ///< Micro-DIMM Memory
+#define DDR_MTYPE_MINI_RDIMM  0x05  ///< Mini Registered DIMM Memory
+#define DDR_MTYPE_MINI_UDIMM  0x06  ///< Mini Unbuffered DIMM Memory
+///
+/// Maximum rank memory size supported by the memory controller
+/// 4 GB in terms of KB
+///
+#define MAX_RANK_CAPACITY (4 * 1024 * 1024)
+
+#ifndef MEMORY_ASSET_TAG
+#define MEMORY_ASSET_TAG  L"9876543210"
+#endif
+///
+/// Memory Module Manufacture ID List Structure
+///
+typedef struct {
+  UINT8   Index;
+  UINT8   ManufactureId;
+  CHAR16  *ManufactureName;
+} MEMORY_MODULE_MANUFACTURE_LIST;
+
+///
+/// Row configuration data structure
+///
+typedef struct {
+  EFI_PHYSICAL_ADDRESS  BaseAddress;
+  UINT64                RowLength;  ///< Size of Row in bytes
+} DDR_ROW_CONFIG;
+
+///
+/// Prototypes
+///
+/**
+    This driver will determine memory configuration information from the chipset
+    and memory and report the memory configuration info to the DataHub.
+
+    @param[in] ImageHandle   - Handle for the image of this driver
+    @param[in] SystemTable   - Pointer to the EFI System Table
+
+    @retval EFI_SUCCESS          - if the data is successfully reported
+    @retval EFI_NOT_FOUND        - if the HOB list could not be located.
+    @retval EFI_OUT_OF_RESOURCES - if not able to get resouces.
+**/
+EFI_STATUS
+SmbiosMemoryEntryPoint (
+  IN EFI_HANDLE         ImageHandle,
+  IN EFI_SYSTEM_TABLE   *SystemTable
+  )
+;
+
+#endif
diff --git a/ReferenceCode/Chipset/SystemAgent/SmbiosMemory/Dxe/SmbiosMemoryStrings.uni b/ReferenceCode/Chipset/SystemAgent/SmbiosMemory/Dxe/SmbiosMemoryStrings.uni
new file mode 100644
index 0000000..3b5be48
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/SmbiosMemory/Dxe/SmbiosMemoryStrings.uni
diff --git a/ReferenceCode/Chipset/SystemAgent/SmmAccess/Dxe/SmmAccess.cif b/ReferenceCode/Chipset/SystemAgent/SmmAccess/Dxe/SmmAccess.cif
new file mode 100644
index 0000000..b754f8b
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/SmmAccess/Dxe/SmmAccess.cif
@@ -0,0 +1,13 @@
+<component>
+	name = "SmmAccess"
+	category = ModulePart
+	LocalRoot = "ReferenceCode\Chipset\SystemAgent\SmmAccess\Dxe"
+	RefName = "SmmAccess"
+[files]
+"SmmAccess.sdl"	
+"SmmAccess.mak"	
+"SmmAccessDriver.c"	
+"SmmAccessDriver.h"	
+"SmmAccess.dxs"
+"SmmAccess.inf"	
+<endComponent>
diff --git a/ReferenceCode/Chipset/SystemAgent/SmmAccess/Dxe/SmmAccess.dxs b/ReferenceCode/Chipset/SystemAgent/SmmAccess/Dxe/SmmAccess.dxs
new file mode 100644
index 0000000..30e8eb6
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/SmmAccess/Dxe/SmmAccess.dxs
@@ -0,0 +1,40 @@
+/** @file
+  Dependency expression file for Smm Access Driver.
+
+@copyright
+  Copyright (c)  1999 - 2012 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains a 'Sample Driver' and is licensed as such
+  under the terms of your license agreement with Intel or your
+  vendor.  This file may be modified by the user, subject to
+  the additional terms of the license agreement
+
+**/
+
+
+//
+// Common for R8 and R9 codebase
+//
+#include "AutoGen.h"
+#include "DxeDepex.h"
+
+//
+// BUILD_WITH_GLUELIB and BUILD_WITH_EDKII_GLUE_LIB are both "defined" in R8 codebase;
+// BUILD_WITH_EDKII_GLUE_LIB is defined in Edk-Dev-Snapshot-20070228 and later version
+// BUILD_WITH_GLUELIB and BUILD_WITH_EDKII_GLUE_LIB are "not defined" in R9 codebase.
+//
+#if defined (BUILD_WITH_GLUELIB) || defined (BUILD_WITH_EDKII_GLUE_LIB)
+#include "EfiDepex.h"
+#include EFI_PROTOCOL_DEFINITION (PciRootBridgeIo)
+#endif
+
+DEPENDENCY_START
+   EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_GUID
+DEPENDENCY_END
diff --git a/ReferenceCode/Chipset/SystemAgent/SmmAccess/Dxe/SmmAccess.inf b/ReferenceCode/Chipset/SystemAgent/SmmAccess/Dxe/SmmAccess.inf
new file mode 100644
index 0000000..f19577b
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/SmmAccess/Dxe/SmmAccess.inf
@@ -0,0 +1,82 @@
+## @file
+#  Component description file for the SmmAccess module
+#  {1323C7F8-DAD5-4126-A54B-7A05FBF4151}
+#
+#@copyright
+#  Copyright (c)  1999 - 2012 Intel Corporation. All rights reserved
+#  This software and associated documentation (if any) is furnished
+#  under a license and may only be used or copied in accordance
+#  with the terms of the license. Except as permitted by such
+#  license, no part of this software or documentation may be
+#  reproduced, stored in a retrieval system, or transmitted in any
+#  form or by any means without the express written consent of
+#  Intel Corporation.
+#
+#  This file contains a 'Sample Driver' and is licensed as such
+#  under the terms of your license agreement with Intel or your
+#  vendor.  This file may be modified by the user, subject to
+#  the additional terms of the license agreement
+#
+
+[defines]
+BASE_NAME            = SmmAccess
+FILE_GUID            = 1323C7F8-DAD5-4126-A54B-7A05FBF41515
+COMPONENT_TYPE       = BS_DRIVER
+
+[sources.common]
+  SmmAccessDriver.h
+  SmmAccessDriver.c
+#
+# Edk II Glue Driver Entry Point
+#
+  EdkIIGlueDxeDriverEntryPoint.c
+
+[includes.common]
+  .
+  $(EFI_SOURCE)
+  $(EDK_SOURCE)/Foundation/Framework
+  $(EDK_SOURCE)/Foundation/Efi
+  $(EDK_SOURCE)/Foundation
+  $(EDK_SOURCE)/Foundation/Core/Dxe
+  $(EDK_SOURCE)/Foundation/Include
+  $(EDK_SOURCE)/Foundation/Efi/Include
+  $(EDK_SOURCE)/Foundation/Framework/Include
+  $(EDK_SOURCE)/Foundation/Include/IndustryStandard
+  $(EDK_SOURCE)/Foundation/Library/Dxe/Include
+  $(EFI_SOURCE)/$(PROJECT_SA_ROOT)/Include
+  $(EDK_SOURCE)/Foundation/Cpu/Pentium/Include
+  $(EDK_SOURCE)/Foundation/Library/EdkIIGlueLib/Include
+  $(EDK_SOURCE)/Foundation/Library/EdkIIGlueLib/Include/Library
+
+[libraries.common]
+  EdkFrameworkGuidLib
+  EdkFrameworkProtocolLib
+  EfiProtocolLib
+  EfiCommonLib
+  EfiScriptLib
+  EdkIIGlueBaseLib
+  EdkIIGlueBaseIoLibIntrinsic
+  EdkIIGlueBaseMemoryLib
+  EdkIIGlueDxeDebugLibReportStatusCode
+  EdkIIGlueDxeReportStatusCodeLib
+  EdkIIGlueUefiBootServicesTableLib
+  EdkIIGlueUefiRuntimeServicesTableLib
+  EdkIIGlueDxeServicesTableLib
+  EdkIIGlueDxeHobLib
+  EdkIIGlueDxeMemoryAllocationLib
+  EdkProtocolLib
+
+[nmake.common]
+  IMAGE_ENTRY_POINT = _ModuleEntryPoint
+  DPX_SOURCE        = SmmAccess.dxs
+  C_FLAGS = $(C_FLAGS) -D __EDKII_GLUE_MODULE_ENTRY_POINT__=SmmAccessDriverEntryPoint \
+                       -D __EDKII_GLUE_BASE_IO_LIB_INTRINSIC__ \
+                       -D __EDKII_GLUE_BASE_LIB__ \
+                       -D __EDKII_GLUE_BASE_MEMORY_LIB__ \
+                       -D __EDKII_GLUE_DXE_REPORT_STATUS_CODE_LIB__ \
+                       -D __EDKII_GLUE_DXE_DEBUG_LIB_REPORT_STATUS_CODE__ \
+                       -D __EDKII_GLUE_UEFI_BOOT_SERVICES_TABLE_LIB__ \
+                       -D __EDKII_GLUE_UEFI_RUNTIME_SERVICES_TABLE_LIB__ \
+                       -D __EDKII_GLUE_DXE_SERVICES_TABLE_LIB__ \
+                       -D __EDKII_GLUE_DXE_HOB_LIB__ \
+                       -D __EDKII_GLUE_DXE_MEMORY_ALLOCATION_LIB__
diff --git a/ReferenceCode/Chipset/SystemAgent/SmmAccess/Dxe/SmmAccess.mak b/ReferenceCode/Chipset/SystemAgent/SmmAccess/Dxe/SmmAccess.mak
new file mode 100644
index 0000000..59d1450
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/SmmAccess/Dxe/SmmAccess.mak
@@ -0,0 +1,63 @@
+#---------------------------------------------------------------------------
+#    Create SmmAccess Driver
+#---------------------------------------------------------------------------
+EDK : SmmAccess
+
+SmmAccess : $(BUILD_DIR)\SmmAccess.mak SmmAccessBin
+
+$(BUILD_DIR)\SmmAccess.mak : $(SmmAccess_DIR)\$(@B).cif $(SmmAccess_DIR)\$(@B).mak $(BUILD_RULES)
+  $(CIF2MAK) $(SmmAccess_DIR)\$(@B).cif $(CIF2MAK_DEFAULTS)
+
+SmmAccess_INCLUDES = \
+    $(EdkIIGlueLib_INCLUDES)\
+    $(EDK_INCLUDES)\
+    $(INTEL_MCH_INCLUDES)
+
+SmmAccess_DEFINES = $(MY_DEFINES)\
+  /D "__EDKII_GLUE_MODULE_ENTRY_POINT__=SmmAccessDriverEntryPoint" \
+  /D __EDKII_GLUE_BASE_IO_LIB_INTRINSIC__ \
+  /D __EDKII_GLUE_BASE_LIB__ \
+  /D __EDKII_GLUE_BASE_MEMORY_LIB__ \
+  /D __EDKII_GLUE_DXE_REPORT_STATUS_CODE_LIB__ \
+  /D __EDKII_GLUE_DXE_DEBUG_LIB_REPORT_STATUS_CODE__ \
+  /D __EDKII_GLUE_DXE_HOB_LIB__\
+  /D __EDKII_GLUE_UEFI_BOOT_SERVICES_TABLE_LIB__ \
+  /D __EDKII_GLUE_UEFI_RUNTIME_SERVICES_TABLE_LIB__ \
+  /D __EDKII_GLUE_DXE_SERVICES_TABLE_LIB__ \
+  /D __EDKII_GLUE_DXE_MEMORY_ALLOCATION_LIB__ \
+
+SmmAccess_LIB_LINKS =\
+  $(EDKFRAMEWORKGUIDLIB)\
+  $(EDKFRAMEWORKPROTOCOLLIB)\
+  $(EFIPROTOCOLLIB)\
+  $(EFICOMMONLIB)\
+  $(EFISCRIPTLIB)\
+  $(EdkIIGlueBaseLib_LIB)\
+!IF "$(x64_BUILD)"=="1"
+  $(EdkIIGlueBaseLibX64_LIB)\
+!ELSE
+  $(EdkIIGlueBaseLibIA32_LIB)\
+!ENDIF
+  $(EdkIIGlueBaseIoLibIntrinsic_LIB)\
+  $(EdkIIGlueBaseMemoryLib_LIB)\
+  $(EdkIIGlueDxeDebugLibReportStatusCode_LIB)\
+  $(EdkIIGlueDxeReportStatusCodeLib_LIB)\
+  $(EdkIIGlueDxeHobLib_LIB)\
+  $(EdkIIGlueUefiBootServicesTableLib_LIB)\
+  $(EdkIIGlueUefiRuntimeServicesTableLib_LIB)\
+  $(EdkIIGlueDxeServicesTableLib_LIB)\
+  $(EdkIIGlueDxeMemoryAllocationLib_LIB)\
+  $(EDKPROTOCOLLIB)\
+
+SmmAccessBin: $(SmmAccess_LIB_LINKS)
+  $(MAKE) /$(MAKEFLAGS) $(EDKIIGLUE_DEFAULTS)\
+    /f $(BUILD_DIR)\SmmAccess.mak all \
+    "MY_INCLUDES=$(SmmAccess_INCLUDES)" \
+    "MY_DEFINES=$(SmmAccess_DEFINES)"\
+    GUID=1323C7F8-DAD5-4126-A54B-7A05FBF41515\
+    ENTRY_POINT=_ModuleEntryPoint\
+    TYPE=BS_DRIVER \
+    EDKIIModule=DXEDRIVER\
+    DEPEX1=$(SmmAccess_DIR)\SmmAccess.dxs\
+    DEPEX1_TYPE=EFI_SECTION_DXE_DEPEX  \
+    COMPRESS=1
diff --git a/ReferenceCode/Chipset/SystemAgent/SmmAccess/Dxe/SmmAccess.sdl b/ReferenceCode/Chipset/SystemAgent/SmmAccess/Dxe/SmmAccess.sdl
new file mode 100644
index 0000000..89077d9
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/SmmAccess/Dxe/SmmAccess.sdl
@@ -0,0 +1,30 @@
+TOKEN
+	Name  = "SmmAccess_SUPPORT"
+	Value  = "1"
+	Help  = "Main switch to enable SmmAccess support in Project"
+	TokenType = Boolean
+	TargetMAK = Yes
+	Master = Yes
+	Token = "SMM_SUPPORT" "=" "1"
+End
+
+PATH
+	Name  = "SmmAccess_DIR"
+End
+
+MODULE
+	Help  = "Includes SmmAccess to Project"
+	File  = "SmmAccess.mak"
+End
+
+ELINK
+	Name  = "SmmAccess"
+	InvokeOrder = ReplaceParent
+End
+
+ELINK
+	Name  = "$(BUILD_DIR)\SmmAccess.ffs"
+	Parent  = "FV_MAIN"
+	InvokeOrder = AfterParent
+End
+
diff --git a/ReferenceCode/Chipset/SystemAgent/SmmAccess/Dxe/SmmAccessDriver.c b/ReferenceCode/Chipset/SystemAgent/SmmAccess/Dxe/SmmAccessDriver.c
new file mode 100644
index 0000000..f91c170
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/SmmAccess/Dxe/SmmAccessDriver.c
@@ -0,0 +1,457 @@
+/** @file
+  This is the driver that publishes the SMM Access Protocol
+  instance for System Agent.
+
+@copyright
+  Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement
+
+**/
+#include "SmmAccessDriver.h"
+
+static SMM_ACCESS_PRIVATE_DATA  mSmmAccess;
+
+EFI_DRIVER_ENTRY_POINT (SmmAccessDriverEntryPoint)
+
+/**
+    This is the standard EFI driver point that
+    installs an SMM Access Protocol
+
+    @param[in] ImageHandle     - Handle for the image of this driver
+    @param[in] SystemTable     - Pointer to the EFI System Table
+
+    @retval EFI_SUCCESS           - Protocol was installed successfully
+    @exception EFI_UNSUPPORTED    - Protocol was not installed
+    @retval EFI_NOT_FOUND         - Protocol can't be found.
+    @retval EFI_OUT_OF_RESOURCES  - Protocol does not have enough resources to initialize the driver.
+**/
+EFI_STATUS
+SmmAccessDriverEntryPoint (
+  IN EFI_HANDLE         ImageHandle,
+  IN EFI_SYSTEM_TABLE   *SystemTable
+  )
+{
+  EFI_STATUS                      Status;
+  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;
+  UINTN                           Index;
+  EFI_SMRAM_HOB_DESCRIPTOR_BLOCK  *DescriptorBlock;
+  EFI_PEI_HOB_POINTERS            *Hob;
+
+  ///
+  /// --cr-- INITIALIZE_SCRIPT (ImageHandle, SystemTable);
+  ///
+  /// Initialize Global variables
+  ///
+  ZeroMem (&mSmmAccess, sizeof (mSmmAccess));
+
+  Status = gBS->LocateProtocol (
+                  &gEfiPciRootBridgeIoProtocolGuid,
+                  NULL,
+                  (VOID **) &PciRootBridgeIo
+                  );
+
+  if (EFI_ERROR (Status)) {
+    DEBUG ((EFI_D_ERROR, "Could not locate PCI Root Bridge IO Protocol\n"));
+    return EFI_NOT_FOUND;
+  }
+
+  mSmmAccess.Signature        = SMM_ACCESS_PRIVATE_DATA_SIGNATURE;
+  mSmmAccess.Handle           = NULL;
+  mSmmAccess.PciRootBridgeIo  = PciRootBridgeIo;
+
+  ///
+  /// Get Hob list
+  ///
+  Hob = GetFirstGuidHob (&gEfiSmmPeiSmramMemoryReserve);
+  if (Hob == NULL) {
+    DEBUG ((EFI_D_ERROR, "SmramMemoryReserve HOB not found\n"));
+    return EFI_NOT_FOUND;
+  }
+
+  DescriptorBlock = (VOID *) ((UINT8 *) Hob + sizeof (EFI_HOB_GUID_TYPE));
+
+  ///
+  /// Alloc space for mSmmAccess.SmramDesc
+  ///
+  mSmmAccess.SmramDesc = AllocateZeroPool ((DescriptorBlock->NumberOfSmmReservedRegions) * sizeof (EFI_SMRAM_DESCRIPTOR));
+  if (mSmmAccess.SmramDesc == NULL) {
+    DEBUG ((EFI_D_ERROR, "Alloc mSmmAccess.SmramDesc fail.\n"));
+    return EFI_OUT_OF_RESOURCES;
+  }
+
+  DEBUG ((EFI_D_INFO, "Alloc mSmmAccess.SmramDesc success.\n"));
+
+  ///
+  /// Use the HOB to publish SMRAM capabilities
+  ///
+  for (Index = 0; Index < DescriptorBlock->NumberOfSmmReservedRegions; Index++) {
+    mSmmAccess.SmramDesc[Index].PhysicalStart = DescriptorBlock->Descriptor[Index].PhysicalStart;
+    mSmmAccess.SmramDesc[Index].CpuStart      = DescriptorBlock->Descriptor[Index].CpuStart;
+    mSmmAccess.SmramDesc[Index].PhysicalSize  = DescriptorBlock->Descriptor[Index].PhysicalSize;
+    mSmmAccess.SmramDesc[Index].RegionState   = DescriptorBlock->Descriptor[Index].RegionState;
+  }
+
+  mSmmAccess.NumberRegions              = Index;
+  mSmmAccess.SmmAccess.Open             = Open;
+  mSmmAccess.SmmAccess.Close            = Close;
+  mSmmAccess.SmmAccess.Lock             = Lock;
+  mSmmAccess.SmmAccess.GetCapabilities  = GetCapabilities;
+  mSmmAccess.SmmAccess.LockState        = FALSE;
+  mSmmAccess.SmmAccess.OpenState        = FALSE;
+
+  ///
+  /// Install our protocol interfaces on the device's handle
+  ///
+  Status = gBS->InstallMultipleProtocolInterfaces (
+                  &mSmmAccess.Handle,
+                  &gEfiSmmAccessProtocolGuid,
+                  &mSmmAccess.SmmAccess,
+                  NULL
+                  );
+
+  if (EFI_ERROR (Status)) {
+    DEBUG ((EFI_D_ERROR, "InstallMultipleProtocolInterfaces returned %r\n", Status));
+    return EFI_UNSUPPORTED;
+  }
+
+  return EFI_SUCCESS;
+}
+
+/**
+    This routine accepts a request to "open" a region of SMRAM.  The
+    region could be legacy ABSEG, HSEG, or TSEG near top of physical memory.
+    The use of "open" means that the memory is visible from all boot-service
+    and SMM agents.
+
+    @param[in] This                  - Pointer to the SMM Access Interface.
+    @param[in] DescriptorIndex       - Region of SMRAM to Open.
+
+    @retval EFI_SUCCESS           - The region was successfully opened.
+    @retval EFI_DEVICE_ERROR      - The region could not be opened because locked by
+                            chipset.
+    @retval EFI_INVALID_PARAMETER - The descriptor index was out of bounds.
+**/
+EFI_STATUS
+EFIAPI
+Open (
+  IN EFI_SMM_ACCESS_PROTOCOL  *This,
+  UINTN                       DescriptorIndex
+  )
+{
+  EFI_STATUS              Status;
+  SMM_ACCESS_PRIVATE_DATA *SmmAccess;
+  UINT64                  Address;
+  UINT8                   SmramControl;
+
+  SmmAccess = SMM_ACCESS_PRIVATE_DATA_FROM_THIS (This);
+
+  if (DescriptorIndex >= SmmAccess->NumberRegions) {
+    DEBUG ((EFI_D_WARN, "SMRAM region out of range\n"));
+    return EFI_INVALID_PARAMETER;
+  } else if (SmmAccess->SmramDesc[DescriptorIndex].RegionState & EFI_SMRAM_LOCKED) {
+    ///
+    /// Cannot open a "locked" region
+    ///
+    DEBUG ((EFI_D_WARN, "Cannot open a locked SMRAM region\n"));
+
+    return EFI_DEVICE_ERROR;
+  }
+  ///
+  /// BEGIN CHIPSET SPECIFIC CODE
+  ///
+  ///
+  /// SMRAM register is PCI 0:0:0:88, SMRAMC (8 bit)
+  ///
+  Address = EFI_PCI_ADDRESS (SA_MC_BUS, SA_MC_DEV, SA_MC_FUN, R_SA_SMRAMC);
+
+  Status = SmmAccess->PciRootBridgeIo->Pci.Read (
+                                            SmmAccess->PciRootBridgeIo,
+                                            EfiPciWidthUint8,
+                                            Address,
+                                            1,
+                                            &SmramControl
+                                            );
+
+  if (EFI_ERROR (Status)) {
+    DEBUG ((EFI_D_ERROR, "SmmAccess->PciRootBridgeIo->Pci.Read returned %r\n", Status));
+    return Status;
+  }
+  ///
+  ///  Is SMRAM locked?
+  ///
+  if ((SmramControl & B_SA_SMRAMC_D_LCK_MASK) != 0) {
+    ///
+    /// Cannot Open a locked region
+    ///
+    SmmAccess->SmramDesc[DescriptorIndex].RegionState |= EFI_SMRAM_LOCKED;
+    DEBUG ((EFI_D_WARN, "Cannot open a locked SMRAM region\n"));
+    return EFI_DEVICE_ERROR;
+  }
+  ///
+  /// Open SMRAM region
+  ///
+  SmramControl |= B_SA_SMRAMC_D_OPEN_MASK;
+  SmramControl &= ~(B_SA_SMRAMC_D_CLS_MASK);
+
+  Status = SmmAccess->PciRootBridgeIo->Pci.Write (
+                                            SmmAccess->PciRootBridgeIo,
+                                            EfiPciWidthUint8,
+                                            Address,
+                                            1,
+                                            &SmramControl
+                                            );
+  if (EFI_ERROR (Status)) {
+    DEBUG ((EFI_D_ERROR, "SmmAccess->PciRootBridgeIo->Pci.Write returned %r\n", Status));
+    return Status;
+  }
+  ///
+  /// END CHIPSET SPECIFIC CODE
+  ///
+  SmmAccess->SmramDesc[DescriptorIndex].RegionState &= ~(EFI_SMRAM_CLOSED | EFI_ALLOCATED);
+  SmmAccess->SmramDesc[DescriptorIndex].RegionState |= EFI_SMRAM_OPEN;
+  SmmAccess->SmmAccess.OpenState = TRUE;
+  return EFI_SUCCESS;
+}
+
+/**
+    This routine accepts a request to "close" a region of SMRAM.  The
+    region could be legacy AB or TSEG near top of physical memory.
+    The use of "close" means that the memory is only visible from SMM agents,
+    not from BS or RT code.
+
+    @param[in] This                  - Pointer to the SMM Access Interface.
+    @param[in] DescriptorIndex       - Region of SMRAM to Close.
+
+    @retval EFI_SUCCESS           - The region was successfully closed.
+    @retval EFI_DEVICE_ERROR      - The region could not be closed because locked by
+                              chipset.
+    @retval EFI_INVALID_PARAMETER - The descriptor index was out of bounds.
+**/
+EFI_STATUS
+EFIAPI
+Close (
+  IN EFI_SMM_ACCESS_PROTOCOL *This,
+  UINTN                      DescriptorIndex
+  )
+{
+  EFI_STATUS              Status;
+  SMM_ACCESS_PRIVATE_DATA *SmmAccess;
+  UINT64                  Address;
+  BOOLEAN                 OpenState;
+  UINT8                   Index;
+  UINT8                   SmramControl;
+
+  SmmAccess = SMM_ACCESS_PRIVATE_DATA_FROM_THIS (This);
+
+  if (DescriptorIndex >= SmmAccess->NumberRegions) {
+    DEBUG ((EFI_D_WARN, "SMRAM region out of range\n"));
+    return EFI_INVALID_PARAMETER;
+  } else if (SmmAccess->SmramDesc[DescriptorIndex].RegionState & EFI_SMRAM_LOCKED) {
+    ///
+    /// Cannot close a "locked" region
+    ///
+    DEBUG ((EFI_D_WARN, "Cannot close a locked SMRAM region\n"));
+    return EFI_DEVICE_ERROR;
+  }
+
+  if (SmmAccess->SmramDesc[DescriptorIndex].RegionState & EFI_SMRAM_CLOSED) {
+    return EFI_DEVICE_ERROR;
+  }
+  ///
+  /// SMRAM register is PCI 0:0:0:88, SMRAMC (8 bit)
+  ///
+  Address = EFI_PCI_ADDRESS (SA_MC_BUS, SA_MC_DEV, SA_MC_FUN, R_SA_SMRAMC);
+
+  Status = SmmAccess->PciRootBridgeIo->Pci.Read (
+                                            SmmAccess->PciRootBridgeIo,
+                                            EfiPciWidthUint8,
+                                            Address,
+                                            1,
+                                            &SmramControl
+                                            );
+  if (EFI_ERROR (Status)) {
+    DEBUG ((EFI_D_ERROR, "SmmAccess->PciRootBridgeIo->Pci.Read returned %r\n", Status));
+    return Status;
+  }
+  ///
+  ///  Is SMRAM locked?
+  ///
+  if ((SmramControl & B_SA_SMRAMC_D_LCK_MASK) != 0) {
+    ///
+    /// Cannot Close a locked region
+    ///
+    SmmAccess->SmramDesc[DescriptorIndex].RegionState |= EFI_SMRAM_LOCKED;
+    DEBUG ((EFI_D_WARN, "Cannot close a locked SMRAM region\n"));
+    return EFI_DEVICE_ERROR;
+  }
+  ///
+  /// Close SMRAM region
+  ///
+  SmramControl &= ~(B_SA_SMRAMC_D_OPEN_MASK);
+
+  Status = SmmAccess->PciRootBridgeIo->Pci.Write (
+                                            SmmAccess->PciRootBridgeIo,
+                                            EfiPciWidthUint8,
+                                            Address,
+                                            1,
+                                            &SmramControl
+                                            );
+
+  if (EFI_ERROR (Status)) {
+    DEBUG ((EFI_D_ERROR, "SmmAccess->PciRootBridgeIo->Pci.Write returned %r\n", Status));
+    return Status;
+  }
+  ///
+  /// END CHIPSET SPECIFIC CODE
+  ///
+  SmmAccess->SmramDesc[DescriptorIndex].RegionState &= ~EFI_SMRAM_OPEN;
+  SmmAccess->SmramDesc[DescriptorIndex].RegionState |= (EFI_SMRAM_CLOSED | EFI_ALLOCATED);
+
+  ///
+  /// Find out if any regions are still open
+  ///
+  OpenState = FALSE;
+  for (Index = 0; Index < mSmmAccess.NumberRegions; Index++) {
+    if ((SmmAccess->SmramDesc[Index].RegionState & EFI_SMRAM_OPEN) == EFI_SMRAM_OPEN) {
+      OpenState = TRUE;
+    }
+  }
+
+  SmmAccess->SmmAccess.OpenState = OpenState;
+  return EFI_SUCCESS;
+}
+
+/**
+    This routine accepts a request to "lock" SMRAM.  The
+    region could be legacy AB or TSEG near top of physical memory.
+    The use of "lock" means that the memory can no longer be opened
+    to BS state..
+
+    @param[in] This                  - Pointer to the SMM Access Interface.
+    @param[in] DescriptorIndex       - Region of SMRAM to Lock.
+
+    @retval EFI_SUCCESS           - The region was successfully locked.
+    @retval EFI_DEVICE_ERROR      - The region could not be locked because at least
+                            one range is still open.
+    @retval EFI_INVALID_PARAMETER - The descriptor index was out of bounds.
+**/
+EFI_STATUS
+EFIAPI
+Lock (
+  IN EFI_SMM_ACCESS_PROTOCOL *This,
+  UINTN                      DescriptorIndex
+  )
+{
+  EFI_STATUS              Status;
+  SMM_ACCESS_PRIVATE_DATA *SmmAccess;
+  UINT64                  Address;
+  UINT8                   SmramControl;
+
+  SmmAccess = SMM_ACCESS_PRIVATE_DATA_FROM_THIS (This);
+
+  if (DescriptorIndex >= SmmAccess->NumberRegions) {
+    DEBUG ((EFI_D_WARN, "SMRAM region out of range\n"));
+    return EFI_INVALID_PARAMETER;
+  } else if (SmmAccess->SmmAccess.OpenState) {
+    DEBUG ((EFI_D_WARN, "Cannot lock SMRAM when SMRAM regions are still open\n"));
+    return EFI_DEVICE_ERROR;
+  }
+
+  SmmAccess->SmramDesc[DescriptorIndex].RegionState |= EFI_SMRAM_LOCKED;
+  SmmAccess->SmmAccess.LockState = TRUE;
+
+  ///
+  /// SMRAM register is PCI 0:0:0:88, SMRAMC (8 bit)
+  ///
+  Address = EFI_PCI_ADDRESS (SA_MC_BUS, SA_MC_DEV, SA_MC_FUN, R_SA_SMRAMC);
+
+  Status = SmmAccess->PciRootBridgeIo->Pci.Read (
+                                            SmmAccess->PciRootBridgeIo,
+                                            EfiPciWidthUint8,
+                                            Address,
+                                            1,
+                                            &SmramControl
+                                            );
+
+  if (EFI_ERROR (Status)) {
+    DEBUG ((EFI_D_ERROR, "SmmAccess->PciRootBridgeIo->Pci.Read returned %r\n", Status));
+    return Status;
+  }
+  ///
+  /// Lock the SMRAM
+  ///
+  SmramControl |= B_SA_SMRAMC_D_LCK_MASK;
+
+  Status = SmmAccess->PciRootBridgeIo->Pci.Write (
+                                            SmmAccess->PciRootBridgeIo,
+                                            EfiPciWidthUint8,
+                                            Address,
+                                            1,
+                                            &SmramControl
+                                            );
+  if (EFI_ERROR (Status)) {
+    DEBUG ((EFI_D_ERROR, "SmmAccess->PciRootBridgeIo->Pci.Write returned %r\n", Status));
+    return Status;
+  }
+  ///
+  /// END CHIPSET SPECIFIC CODE
+  ///
+  return EFI_SUCCESS;
+}
+
+/**
+    This routine services a user request to discover the SMRAM
+    capabilities of this platform.  This will report the possible
+    ranges that are possible for SMRAM access, based upon the
+    memory controller capabilities.
+
+    @param[in] This                  - Pointer to the SMRAM Access Interface.
+    @param[in] SmramMapSize          - Pointer to the variable containing size of the
+                              buffer to contain the description information.
+    @param[in] SmramMap              - Buffer containing the data describing the Smram
+                              region descriptors.
+
+    @retval EFI_BUFFER_TOO_SMALL  - The user did not provide a sufficient buffer.
+    @retval EFI_SUCCESS           - The user provided a sufficiently-sized buffer.
+**/
+EFI_STATUS
+EFIAPI
+GetCapabilities (
+  IN EFI_SMM_ACCESS_PROTOCOL     *This,
+  IN OUT UINTN                   *SmramMapSize,
+  IN OUT EFI_SMRAM_DESCRIPTOR    *SmramMap
+  )
+{
+  EFI_STATUS              Status;
+  SMM_ACCESS_PRIVATE_DATA *SmmAccess;
+  UINTN                   NecessaryBufferSize;
+
+  SmmAccess           = SMM_ACCESS_PRIVATE_DATA_FROM_THIS (This);
+
+  NecessaryBufferSize = SmmAccess->NumberRegions * sizeof (EFI_SMRAM_DESCRIPTOR);
+
+  if (*SmramMapSize < NecessaryBufferSize) {
+    DEBUG ((EFI_D_WARN, "SMRAM Map Buffer too small\n"));
+    Status = EFI_BUFFER_TOO_SMALL;
+  } else {
+    CopyMem (SmramMap, SmmAccess->SmramDesc, NecessaryBufferSize);
+    Status = EFI_SUCCESS;
+  }
+
+  *SmramMapSize = NecessaryBufferSize;
+
+  return Status;
+}
diff --git a/ReferenceCode/Chipset/SystemAgent/SmmAccess/Dxe/SmmAccessDriver.h b/ReferenceCode/Chipset/SystemAgent/SmmAccess/Dxe/SmmAccessDriver.h
new file mode 100644
index 0000000..4d98f27
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/SmmAccess/Dxe/SmmAccessDriver.h
@@ -0,0 +1,178 @@
+/** @file
+  Header file for SMM Access Driver.
+
+@copyright
+  Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement
+**/
+#ifndef _SMM_ACCESS_DRIVER_H_
+#define _SMM_ACCESS_DRIVER_H_
+
+#include "EdkIIGlueDxe.h"
+#include "pci22.h"
+#include "EdkIIGlueHobLib.h"
+#include "EfiScriptLib.h"
+#include "SaAccess.h"
+
+///
+/// Driver Consumed Protocol Prototypes
+///
+#include EFI_PROTOCOL_CONSUMER (PciRootBridgeIo)
+
+///
+/// Driver private data
+///
+#include EFI_GUID_DEFINITION (SmramMemoryReserve)
+#include EFI_GUID_DEFINITION (Hob)
+#include EFI_PROTOCOL_DEFINITION (SmmAccess)
+
+#define SMM_ACCESS_PRIVATE_DATA_SIGNATURE EFI_SIGNATURE_32 ('4', '5', 's', 'a')
+
+///
+/// Private data
+///
+typedef struct {
+  UINTN                           Signature;
+  EFI_HANDLE                      Handle;
+  EFI_SMM_ACCESS_PROTOCOL         SmmAccess;
+  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;
+
+  ///
+  /// Local Data for SMM Access interface goes here
+  ///
+  UINTN                           NumberRegions;
+  EFI_SMRAM_DESCRIPTOR            *SmramDesc;
+} SMM_ACCESS_PRIVATE_DATA;
+
+#define SMM_ACCESS_PRIVATE_DATA_FROM_THIS(a) \
+  CR (a, \
+      SMM_ACCESS_PRIVATE_DATA, \
+      SmmAccess, \
+      SMM_ACCESS_PRIVATE_DATA_SIGNATURE \
+      )
+
+///
+/// Prototypes
+/// Driver model protocol interface
+///
+/**
+  This is the standard EFI driver point that
+  installs an SMM Access Protocol
+
+  @param[in] ImageHandle     - Handle for the image of this driver
+  @param[in] SystemTable     - Pointer to the EFI System Table
+
+  @retval EFI_SUCCESS     - Protocol was installed successfully
+  @exception EFI_UNSUPPORTED - Protocol was not installed
+**/
+EFI_STATUS
+SmmAccessDriverEntryPoint (
+  IN EFI_HANDLE         ImageHandle,
+  IN EFI_SYSTEM_TABLE   *SystemTable
+  )
+;
+
+/**
+  This routine accepts a request to "open" a region of SMRAM.  The
+  region could be legacy ABSEG, HSEG, or TSEG near top of physical memory.
+  The use of "open" means that the memory is visible from all boot-service
+  and SMM agents.
+
+  @param[in] This                  - Pointer to the SMM Access Interface.
+  @param[in] DescriptorIndex       - Region of SMRAM to Open.
+
+  @retval EFI_SUCCESS           - The region was successfully opened.
+  @retval EFI_DEVICE_ERROR      - The region could not be opened because locked by
+                          chipset.
+  @retval EFI_INVALID_PARAMETER - The descriptor index was out of bounds.
+**/
+EFI_STATUS
+EFIAPI
+Open (
+  IN EFI_SMM_ACCESS_PROTOCOL *This,
+  IN UINTN                   DescriptorIndex
+  )
+;
+
+/**
+  This routine accepts a request to "close" a region of SMRAM.  The
+  region could be legacy AB or TSEG near top of physical memory.
+  The use of "close" means that the memory is only visible from SMM agents,
+  not from BS or RT code.
+
+  @param[in] This                  - Pointer to the SMM Access Interface.
+  @param[in] DescriptorIndex       - Region of SMRAM to Close.
+
+  @retval EFI_SUCCESS           - The region was successfully closed.
+  @retval EFI_DEVICE_ERROR      - The region could not be closed because locked by
+                            chipset.
+  @retval EFI_INVALID_PARAMETER - The descriptor index was out of bounds.
+**/
+EFI_STATUS
+EFIAPI
+Close (
+  IN EFI_SMM_ACCESS_PROTOCOL *This,
+  IN UINTN                   DescriptorIndex
+  )
+;
+
+/**
+  This routine accepts a request to "lock" SMRAM.  The
+  region could be legacy AB or TSEG near top of physical memory.
+  The use of "lock" means that the memory can no longer be opened
+  to BS state..
+
+  @param[in] This                  - Pointer to the SMM Access Interface.
+  @param[in] DescriptorIndex       - Region of SMRAM to Lock.
+
+  @retval EFI_SUCCESS           - The region was successfully locked.
+  @retval EFI_DEVICE_ERROR      - The region could not be locked because at least
+                          one range is still open.
+  @retval EFI_INVALID_PARAMETER - The descriptor index was out of bounds.
+**/
+EFI_STATUS
+EFIAPI
+Lock (
+  IN EFI_SMM_ACCESS_PROTOCOL *This,
+  IN UINTN                   DescriptorIndex
+  )
+;
+
+/**
+  This routine services a user request to discover the SMRAM
+  capabilities of this platform.  This will report the possible
+  ranges that are possible for SMRAM access, based upon the
+  memory controller capabilities.
+
+  @param[in] This                  - Pointer to the SMRAM Access Interface.
+  @param[in] SmramMapSize          - Pointer to the variable containing size of the
+                            buffer to contain the description information.
+  @param[in] SmramMap              - Buffer containing the data describing the Smram
+                            region descriptors.
+
+  @retval EFI_BUFFER_TOO_SMALL  - The user did not provide a sufficient buffer.
+  @retval EFI_SUCCESS           - The user provided a sufficiently-sized buffer.
+**/
+EFI_STATUS
+EFIAPI
+GetCapabilities (
+  IN EFI_SMM_ACCESS_PROTOCOL     *This,
+  IN OUT UINTN                   *SmramMapSize,
+  IN OUT EFI_SMRAM_DESCRIPTOR    *SmramMap
+  )
+;
+
+#endif
diff --git a/ReferenceCode/Chipset/SystemAgent/SmmAccess/Pei/SmmAccess.inf b/ReferenceCode/Chipset/SystemAgent/SmmAccess/Pei/SmmAccess.inf
new file mode 100644
index 0000000..99b2a6d
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/SmmAccess/Pei/SmmAccess.inf
@@ -0,0 +1,91 @@
+## @file
+#  Component description file for the SmmAccess module
+#
+#@copyright
+#  Copyright (c)  1999 - 2013 Intel Corporation. All rights reserved
+#  This software and associated documentation (if any) is furnished
+#  under a license and may only be used or copied in accordance
+#  with the terms of the license. Except as permitted by such
+#  license, no part of this software or documentation may be
+#  reproduced, stored in a retrieval system, or transmitted in any
+#  form or by any means without the express written consent of
+#  Intel Corporation.
+#
+#  This file contains a 'Sample Driver' and is licensed as such
+#  under the terms of your license agreement with Intel or your
+#  vendor.  This file may be modified by the user, subject to
+#  the additional terms of the license agreement
+#
+##
+
+[defines]
+BASE_NAME            = SmmAccess
+FILE_GUID            = 6ECFCE51-5724-450c-A38A-58553E954422
+COMPONENT_TYPE       = PE32_PEIM
+
+[sources.common]
+  SmmAccessPeim.h
+  SmmAccessPeim.c
+
+#
+# Edk II Glue Driver Entry Point
+#
+ EdkIIGluePeimEntryPoint.c
+
+[includes.common]
+  $(EDK_SOURCE)/Foundation/Framework
+  $(EDK_SOURCE)/Foundation/Efi
+  $(EDK_SOURCE)/Foundation
+  $(EDK_SOURCE)/Foundation/Core/Dxe
+  $(EDK_SOURCE)/Foundation/Include
+  $(EDK_SOURCE)/Foundation/Efi/Include
+  $(EDK_SOURCE)/Foundation/Framework/Include
+  $(EDK_SOURCE)/Foundation/Include/IndustryStandard
+  $(EDK_SOURCE)/Foundation/Library/Dxe/Include
+  $(EDK_SOURCE)/Foundation/Include/Pei
+  $(EDK_SOURCE)/Foundation/Library/Pei/Include
+  $(EFI_SOURCE)/$(PROJECT_SA_ROOT)
+  $(EFI_SOURCE)/$(PROJECT_SA_ROOT)/Include
+  $(EDK_SOURCE)/Foundation/Cpu/Pentium/Include
+  $(CLIENT_COMMON_ECP_SOURCE)
+
+#
+# Edk II Glue Library, some hearder are included by R9 header so have to include
+#
+
+ $(EFI_SOURCE)
+ $(EFI_SOURCE)/Framework
+ $(EDK_SOURCE)/Foundation
+ $(EDK_SOURCE)/Foundation/Framework
+ $(EDK_SOURCE)/Foundation/Include/IndustryStandard
+ $(EDK_SOURCE)/Foundation/Core/Dxe
+ $(EDK_SOURCE)/Foundation/Include/Pei
+ $(EDK_SOURCE)/Foundation/Library/Dxe/Include
+ $(EDK_SOURCE)/Foundation/Library/EdkIIGlueLib/Include
+
+[libraries.common]
+  EdkIIGlueBaseLib
+  EdkIIGlueBaseMemoryLib
+  EdkIIGluePeiDebugLibReportStatusCode
+  EdkIIGluePeiReportStatusCodeLib
+  EdkIIGluePeiServicesLib
+  EdkIIGluePeiHobLib
+  EdkIIGlueBasePciLibPciExpress
+  EdkIIGluePeiMemoryAllocationLib
+  IntelSaSampleCodePpiLib
+
+[nmake.common]
+  IMAGE_ENTRY_POINT=_ModuleEntryPoint
+  DPX_SOURCE=SmmAccessPeim.dxs
+#
+# Module Entry Point
+#
+ C_FLAGS = $(C_FLAGS) -D __EDKII_GLUE_MODULE_ENTRY_POINT__=SmmAccessPeimEntryPoint
+ C_FLAGS = $(C_FLAGS) -D __EDKII_GLUE_BASE_LIB__ \
+                      -D __EDKII_GLUE_BASE_MEMORY_LIB__ \
+                      -D __EDKII_GLUE_PEI_DEBUG_LIB_REPORT_STATUS_CODE__ \
+                      -D __EDKII_GLUE_PEI_REPORT_STATUS_CODE_LIB__ \
+                      -D __EDKII_GLUE_PEI_HOB_LIB__ \
+                      -D __EDKII_GLUE_BASE_PCI_LIB_PCI_EXPRESS__ \
+                      -D __EDKII_GLUE_PEI_MEMORY_ALLOCATION_LIB__ \
+                      -D __EDKII_GLUE_PEI_SERVICES_LIB__
diff --git a/ReferenceCode/Chipset/SystemAgent/SmmAccess/Pei/SmmAccessPeim.c b/ReferenceCode/Chipset/SystemAgent/SmmAccess/Pei/SmmAccessPeim.c
new file mode 100644
index 0000000..fc2ab44
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/SmmAccess/Pei/SmmAccessPeim.c
@@ -0,0 +1,407 @@
+/** @file
+  This is the driver that publishes the SMM Access Ppi
+  instance.
+
+@copyright
+  Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement
+
+**/
+#if !defined(EDK_RELEASE_VERSION) || (EDK_RELEASE_VERSION < 0x00020000)
+#include "EdkIIGluePeim.h"
+#include "SmmAccessPeim.h"
+#include "CpuIA32.h"
+#endif
+
+/**
+    This is the standard PEIM entry point that
+    installs an SMM Access PPI
+
+    @param[in] FfsHeader       - FfsHeader.
+    @param[in] PeiServices     - General purpose services available to every PEIM.
+
+    @retval EFI_SUCCESS           - Protocol successfully started and installed.
+    @exception EFI_UNSUPPORTED    - Protocol can't be started.
+    @retval EFI_NOT_FOUND         - Protocol can't be found.
+    @retval EFI_OUT_OF_RESOURCES  - Protocol does not have enough resources to initialize the driver.
+**/
+EFI_STATUS
+EFIAPI
+SmmAccessPeimEntryPoint (
+  IN EFI_FFS_FILE_HEADER        *FfsHeader,
+  IN EFI_PEI_SERVICES           **PeiServices
+  )
+{
+  EFI_STATUS                      Status;
+  UINT32                          PciVidDid;
+  UINTN                           Index;
+  EFI_PEI_PPI_DESCRIPTOR          *PpiList;
+  EFI_SMRAM_HOB_DESCRIPTOR_BLOCK  *DescriptorBlock;
+  SMM_ACCESS_PRIVATE_DATA         *SmmAccessPrivate;
+  VOID                            *HobList;
+  EFI_BOOT_MODE                   BootMode;
+
+  Status = (*PeiServices)->GetBootMode (PeiServices, &BootMode);
+  if (EFI_ERROR (Status)) {
+    ///
+    /// If not in S3 boot path. do nothing
+    ///
+    return EFI_SUCCESS;
+  }
+
+  if (BootMode != BOOT_ON_S3_RESUME) {
+    return EFI_SUCCESS;
+  }
+  ///
+  /// Initialize private data
+  ///
+  SmmAccessPrivate  = AllocateZeroPool (sizeof (*SmmAccessPrivate));
+  PpiList           = AllocateZeroPool (sizeof (*PpiList));
+
+  ///
+  /// Check if the chipset is supported
+  /// by this driver.  Read the PCI Configuration Header for this device.
+  ///
+  PciVidDid                   = PciRead32 (PCI_LIB_ADDRESS (SA_MC_BUS, SA_MC_DEV, SA_MC_FUN, 0));
+
+  SmmAccessPrivate->Signature = SMM_ACCESS_PRIVATE_DATA_SIGNATURE;
+  SmmAccessPrivate->Handle    = NULL;
+
+  ///
+  /// Get Hob list
+  ///
+  HobList = GetFirstGuidHob (&gEfiSmmPeiSmramMemoryReserve);
+  if (HobList == NULL) {
+    DEBUG ((EFI_D_ERROR, "SmramMemoryReserve HOB not found\n"));
+    return EFI_NOT_FOUND;
+  }
+
+  DescriptorBlock = (EFI_SMRAM_HOB_DESCRIPTOR_BLOCK *) ((UINT8 *) HobList + sizeof (EFI_HOB_GUID_TYPE));
+
+  ///
+  /// Alloc space for SmmAccessPrivate->SmramDesc
+  ///
+  SmmAccessPrivate->SmramDesc = AllocateZeroPool ((DescriptorBlock->NumberOfSmmReservedRegions) * sizeof (EFI_SMRAM_DESCRIPTOR));
+  if (SmmAccessPrivate->SmramDesc == NULL) {
+    DEBUG ((EFI_D_ERROR, "Alloc SmmAccessPrivate->SmramDesc fail.\n"));
+    return EFI_OUT_OF_RESOURCES;
+  }
+
+  DEBUG ((EFI_D_INFO, "Alloc SmmAccessPrivate->SmramDesc success.\n"));
+
+  ///
+  /// use the hob to publish SMRAM capabilities
+  ///
+  for (Index = 0; Index < DescriptorBlock->NumberOfSmmReservedRegions; Index++) {
+    SmmAccessPrivate->SmramDesc[Index].PhysicalStart  = DescriptorBlock->Descriptor[Index].PhysicalStart;
+    SmmAccessPrivate->SmramDesc[Index].CpuStart       = DescriptorBlock->Descriptor[Index].CpuStart;
+    SmmAccessPrivate->SmramDesc[Index].PhysicalSize   = DescriptorBlock->Descriptor[Index].PhysicalSize;
+    SmmAccessPrivate->SmramDesc[Index].RegionState    = DescriptorBlock->Descriptor[Index].RegionState;
+  }
+
+  SmmAccessPrivate->NumberRegions             = Index;
+  SmmAccessPrivate->SmmAccess.Open            = Open;
+  SmmAccessPrivate->SmmAccess.Close           = Close;
+  SmmAccessPrivate->SmmAccess.Lock            = Lock;
+  SmmAccessPrivate->SmmAccess.GetCapabilities = GetCapabilities;
+  SmmAccessPrivate->SmmAccess.LockState       = FALSE;
+  SmmAccessPrivate->SmmAccess.OpenState       = FALSE;
+
+  ///
+  /// Install PPI
+  ///
+  PpiList->Flags  = (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST);
+  PpiList->Guid   = &gPeiSmmAccessPpiGuid;
+  PpiList->Ppi    = &SmmAccessPrivate->SmmAccess;
+
+  Status          = PeiServicesInstallPpi (PpiList);
+  ASSERT_EFI_ERROR (Status);
+
+  return EFI_SUCCESS;
+}
+
+/**
+  This routine accepts a request to "open" a region of SMRAM.  The
+  region could be legacy ABSEG, HSEG, or TSEG near top of physical memory.
+  The use of "open" means that the memory is visible from all PEIM
+  and SMM agents.
+
+  @param[in] This             -  Pointer to the SMM Access Interface.
+  @param[in] DescriptorIndex  -  Region of SMRAM to Open.
+  @param[in] PeiServices      -  General purpose services available to every PEIM.
+
+  @retval EFI_SUCCESS            -  The region was successfully opened.
+  @retval EFI_DEVICE_ERROR       -  The region could not be opened because locked by
+                            chipset.
+  @retval EFI_INVALID_PARAMETER  -  The descriptor index was out of bounds.
+**/
+EFI_STATUS
+EFIAPI
+Open (
+  IN EFI_PEI_SERVICES           **PeiServices,
+  IN PEI_SMM_ACCESS_PPI         *This,
+  IN UINTN                      DescriptorIndex
+  )
+{
+  SMM_ACCESS_PRIVATE_DATA *SmmAccess;
+  SMRAM                   Smram;
+
+  SmmAccess = SMM_ACCESS_PRIVATE_DATA_FROM_THIS (This);
+  if (DescriptorIndex >= SmmAccess->NumberRegions) {
+    DEBUG ((EFI_D_WARN, "SMRAM region out of range\n"));
+
+    return EFI_INVALID_PARAMETER;
+  } else if (SmmAccess->SmramDesc[DescriptorIndex].RegionState & EFI_SMRAM_LOCKED) {
+    ///
+    /// Cannot open a "locked" region
+    ///
+    DEBUG ((EFI_D_WARN, "Cannot open a locked SMRAM region\n"));
+
+    return EFI_DEVICE_ERROR;
+  }
+  ///
+  /// BEGIN CHIPSET SPECIFIC CODE
+  ///
+  ///
+  /// SMRAM register is PCI 0:0:0:88, SMRAMC (8 bit)
+  ///
+  Smram = PciRead32 (PCI_LIB_ADDRESS (SA_MC_BUS, SA_MC_DEV, SA_MC_FUN, R_SA_SMRAMC));
+
+  ///
+  ///  Is SMRAM locked?
+  ///
+  if (Smram & B_SA_SMRAMC_D_LCK_MASK) {
+    ///
+    /// Cannot Open a locked region
+    ///
+    SmmAccess->SmramDesc[DescriptorIndex].RegionState |= EFI_SMRAM_LOCKED;
+    DEBUG ((EFI_D_WARN, "Cannot open a locked SMRAM region\n"));
+
+    return EFI_DEVICE_ERROR;
+  }
+  ///
+  /// Open SMRAM region
+  ///
+  Smram |= B_SA_SMRAMC_D_OPEN_MASK;
+  Smram &= ~(B_SA_SMRAMC_D_CLS_MASK);
+
+  ///
+  /// Write the SMRAMC register
+  ///
+  PciWrite32 (PCI_LIB_ADDRESS (SA_MC_BUS, SA_MC_DEV, SA_MC_FUN, R_SA_SMRAMC), Smram);
+
+  ///
+  /// END CHIPSET SPECIFIC CODE
+  ///
+  SmmAccess->SmramDesc[DescriptorIndex].RegionState &= ~(EFI_SMRAM_CLOSED | EFI_ALLOCATED);
+  SmmAccess->SmramDesc[DescriptorIndex].RegionState |= EFI_SMRAM_OPEN;
+  SmmAccess->SmmAccess.OpenState = TRUE;
+  return EFI_SUCCESS;
+}
+
+/**
+  This routine accepts a request to "close" a region of SMRAM.  This is valid for
+  compatible SMRAM region.
+
+  @param[in] PeiServices      -  General purpose services available to every PEIM.
+  @param[in] This             -  Pointer to the SMM Access Interface.
+  @param[in] DescriptorIndex  -  Region of SMRAM to Close.
+
+  @retval EFI_SUCCESS            -  The region was successfully closed.
+  @retval EFI_DEVICE_ERROR       -  The region could not be closed because locked by
+                            chipset.
+  @retval EFI_INVALID_PARAMETER  -  The descriptor index was out of bounds.
+**/
+EFI_STATUS
+EFIAPI
+Close (
+  IN EFI_PEI_SERVICES        **PeiServices,
+  IN PEI_SMM_ACCESS_PPI      *This,
+  IN UINTN                   DescriptorIndex
+  )
+{
+  SMM_ACCESS_PRIVATE_DATA *SmmAccess;
+  BOOLEAN                 OpenState;
+  UINT8                   Index;
+  SMRAM                   Smram;
+
+  SmmAccess = SMM_ACCESS_PRIVATE_DATA_FROM_THIS (This);
+  if (DescriptorIndex >= SmmAccess->NumberRegions) {
+    DEBUG ((EFI_D_WARN, "SMRAM region out of range\n"));
+
+    return EFI_INVALID_PARAMETER;
+  } else if (SmmAccess->SmramDesc[DescriptorIndex].RegionState & EFI_SMRAM_LOCKED) {
+    ///
+    /// Cannot close a "locked" region
+    ///
+    DEBUG ((EFI_D_WARN, "Cannot close a locked SMRAM region\n"));
+
+    return EFI_DEVICE_ERROR;
+  }
+
+  if (SmmAccess->SmramDesc[DescriptorIndex].RegionState & EFI_SMRAM_CLOSED) {
+    return EFI_DEVICE_ERROR;
+  }
+  ///
+  /// SMRAM register is PCI 0:0:0:88, SMRAMC (8 bit)
+  ///
+  Smram = PciRead32 (PCI_LIB_ADDRESS (SA_MC_BUS, SA_MC_DEV, SA_MC_FUN, R_SA_SMRAMC));
+
+  ///
+  ///  Is SMRAM locked?
+  ///
+  if ((Smram & B_SA_SMRAMC_D_LCK_MASK) != 0) {
+    ///
+    /// Cannot Close a locked region
+    ///
+    SmmAccess->SmramDesc[DescriptorIndex].RegionState |= EFI_SMRAM_LOCKED;
+    DEBUG ((EFI_D_WARN, "Cannot close a locked SMRAM region\n"));
+    return EFI_DEVICE_ERROR;
+  }
+  ///
+  /// Close SMRAM region
+  ///
+  Smram &= ~(B_SA_SMRAMC_D_OPEN_MASK);
+
+  ///
+  /// Write the SAD_SMRAM register
+  ///
+  PciWrite32 (PCI_LIB_ADDRESS (SA_MC_BUS, SA_MC_DEV, SA_MC_FUN, R_SA_SMRAMC), Smram);
+
+  ///
+  /// END CHIPSET SPECIFIC CODE
+  ///
+  SmmAccess->SmramDesc[DescriptorIndex].RegionState &= ~EFI_SMRAM_OPEN;
+  SmmAccess->SmramDesc[DescriptorIndex].RegionState |= (EFI_SMRAM_CLOSED | EFI_ALLOCATED);
+
+  ///
+  /// Find out if any regions are still open
+  ///
+  OpenState = FALSE;
+  for (Index = 0; Index < SmmAccess->NumberRegions; Index++) {
+    if ((SmmAccess->SmramDesc[Index].RegionState & EFI_SMRAM_OPEN) == EFI_SMRAM_OPEN) {
+      OpenState = TRUE;
+    }
+  }
+
+  SmmAccess->SmmAccess.OpenState = OpenState;
+  return EFI_SUCCESS;
+}
+
+/**
+  This routine accepts a request to "lock" SMRAM.  The
+  region could be legacy AB or TSEG near top of physical memory.
+  The use of "lock" means that the memory can no longer be opened
+  to PEIM.
+
+  @param[in] PeiServices      - General purpose services available to every PEIM.
+  @param[in] This             -  Pointer to the SMM Access Interface.
+  @param[in] DescriptorIndex  -  Region of SMRAM to Lock.
+
+  @retval EFI_SUCCESS            -  The region was successfully locked.
+  @retval EFI_DEVICE_ERROR       -  The region could not be locked because at least
+                            one range is still open.
+  @retval EFI_INVALID_PARAMETER  -  The descriptor index was out of bounds.
+**/
+EFI_STATUS
+EFIAPI
+Lock (
+  IN EFI_PEI_SERVICES          **PeiServices,
+  IN PEI_SMM_ACCESS_PPI        *This,
+  IN UINTN                     DescriptorIndex
+  )
+{
+  SMM_ACCESS_PRIVATE_DATA *SmmAccess;
+  SMRAM                   Smram;
+
+  SmmAccess = SMM_ACCESS_PRIVATE_DATA_FROM_THIS (This);
+  if (DescriptorIndex >= SmmAccess->NumberRegions) {
+    DEBUG ((EFI_D_WARN, "SMRAM region out of range\n"));
+
+    return EFI_INVALID_PARAMETER;
+  } else if (SmmAccess->SmmAccess.OpenState) {
+    DEBUG ((EFI_D_WARN, "Cannot lock SMRAM when SMRAM regions are still open\n"));
+
+    return EFI_DEVICE_ERROR;
+  }
+
+  SmmAccess->SmramDesc[DescriptorIndex].RegionState |= EFI_SMRAM_LOCKED;
+  SmmAccess->SmmAccess.LockState = TRUE;
+
+  ///
+  /// Read the SAD_SMRAM register
+  ///
+  Smram = PciRead32 (PCI_LIB_ADDRESS (SA_MC_BUS, SA_MC_DEV, SA_MC_FUN, R_SA_SMRAMC));
+
+  ///
+  /// Lock the chipset
+  ///
+  Smram |= B_SA_SMRAMC_D_LCK_MASK;
+
+  ///
+  /// Write the SAD_SMRAM register
+  ///
+  PciWrite32 (PCI_LIB_ADDRESS (SA_MC_BUS, SA_MC_DEV, SA_MC_FUN, R_SA_SMRAMC), Smram);
+
+  ///
+  /// END CHIPSET SPECIFIC CODE
+  ///
+  return EFI_SUCCESS;
+}
+
+/**
+  This routine services a user request to discover the SMRAM
+  capabilities of this platform.  This will report the possible
+  ranges that are possible for SMRAM access, based upon the
+  memory controller capabilities.
+
+  @param[in] PeiServices   - General purpose services available to every PEIM.
+  @param[in] This          -  Pointer to the SMRAM Access Interface.
+  @param[in] SmramMapSize  -  Pointer to the variable containing size of the
+                   buffer to contain the description information.
+  @param[in] SmramMap      -  Buffer containing the data describing the Smram
+                   region descriptors.
+
+  @retval EFI_BUFFER_TOO_SMALL  -  The user did not provide a sufficient buffer.
+  @retval EFI_SUCCESS           -  The user provided a sufficiently-sized buffer.
+**/
+EFI_STATUS
+EFIAPI
+GetCapabilities (
+  IN EFI_PEI_SERVICES                **PeiServices,
+  IN PEI_SMM_ACCESS_PPI              *This,
+  IN OUT UINTN                       *SmramMapSize,
+  IN OUT EFI_SMRAM_DESCRIPTOR        *SmramMap
+  )
+{
+  EFI_STATUS              Status;
+  SMM_ACCESS_PRIVATE_DATA *SmmAccess;
+  UINTN                   NecessaryBufferSize;
+
+  SmmAccess           = SMM_ACCESS_PRIVATE_DATA_FROM_THIS (This);
+  NecessaryBufferSize = SmmAccess->NumberRegions * sizeof (EFI_SMRAM_DESCRIPTOR);
+  if (*SmramMapSize < NecessaryBufferSize) {
+    DEBUG ((EFI_D_WARN, "SMRAM Map Buffer too small\n"));
+
+    Status = EFI_BUFFER_TOO_SMALL;
+  } else {
+    CopyMem (SmramMap, SmmAccess->SmramDesc, NecessaryBufferSize);
+    Status = EFI_SUCCESS;
+  }
+
+  *SmramMapSize = NecessaryBufferSize;
+  return Status;
+}
diff --git a/ReferenceCode/Chipset/SystemAgent/SmmAccess/Pei/SmmAccessPeim.cif b/ReferenceCode/Chipset/SystemAgent/SmmAccess/Pei/SmmAccessPeim.cif
new file mode 100644
index 0000000..d7f3ab1
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/SmmAccess/Pei/SmmAccessPeim.cif
@@ -0,0 +1,13 @@
+<component>
+	name = "SmmAccessPeim"
+	category = ModulePart
+	LocalRoot = "ReferenceCode\Chipset\SystemAgent\SmmAccess\Pei"
+	RefName = "SmmAccessPeim"
+[files]
+"SmmAccessPeim.sdl"
+"SmmAccessPeim.mak"
+"SmmAccessPeim.c"
+"SmmAccessPeim.h"
+"SmmAccessPeim.dxs"
+"SmmAccess.inf"
+<endComponent>
diff --git a/ReferenceCode/Chipset/SystemAgent/SmmAccess/Pei/SmmAccessPeim.dxs b/ReferenceCode/Chipset/SystemAgent/SmmAccess/Pei/SmmAccessPeim.dxs
new file mode 100644
index 0000000..34e3dde
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/SmmAccess/Pei/SmmAccessPeim.dxs
@@ -0,0 +1,29 @@
+/** @file
+  Dependency expression file for Smm Access PEIM.
+
+@copyright
+  Copyright (c)  1999 - 2012 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains a 'Sample Driver' and is licensed as such
+  under the terms of your license agreement with Intel or your
+  vendor.  This file may be modified by the user, subject to
+  the additional terms of the license agreement
+
+**/
+
+
+#include "EfiDepex.h"
+#include EFI_PPI_CONSUMER (MemoryDiscovered)
+#include EFI_PPI_CONSUMER (BootMode)
+
+DEPENDENCY_START
+   PEI_PERMANENT_MEMORY_INSTALLED_PPI_GUID AND
+   PEI_MASTER_BOOT_MODE_PEIM_PPI
+DEPENDENCY_END
diff --git a/ReferenceCode/Chipset/SystemAgent/SmmAccess/Pei/SmmAccessPeim.h b/ReferenceCode/Chipset/SystemAgent/SmmAccess/Pei/SmmAccessPeim.h
new file mode 100644
index 0000000..c89cdaf
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/SmmAccess/Pei/SmmAccessPeim.h
@@ -0,0 +1,186 @@
+/** @file
+  Header file for SMM Access Driver.
+
+@copyright
+  Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement
+**/
+#ifndef _SMM_ACCESS_DRIVER_H_
+#define _SMM_ACCESS_DRIVER_H_
+
+#include "pci22.h"
+#include "SaAccess.h"
+
+///
+/// Driver Consumed Protocol Prototypes
+///
+///
+/// Driver Consumed GUID Prototypes
+///
+#include EFI_GUID_DEFINITION (SmramMemoryReserve)
+
+///
+/// Driver produced protocol
+///
+#include EFI_PPI_PRODUCER (SmmAccess)
+
+#define SMM_ACCESS_PRIVATE_DATA_SIGNATURE EFI_SIGNATURE_32 ('4', '5', 's', 'a')
+
+///
+/// SMM configuration register
+///
+typedef UINT32  SMRAM;  /// System Management RAM Control
+///
+/// Private data
+///
+typedef struct {
+  UINTN                 Signature;
+  EFI_HANDLE            Handle;
+  PEI_SMM_ACCESS_PPI    SmmAccess;
+  ///
+  /// Local Data for SMM Access interface goes here
+  ///
+  UINTN                 NumberRegions;
+  EFI_SMRAM_DESCRIPTOR  *SmramDesc;
+} SMM_ACCESS_PRIVATE_DATA;
+
+#define SMM_ACCESS_PRIVATE_DATA_FROM_THIS(a) \
+  PEI_CR (a, \
+          SMM_ACCESS_PRIVATE_DATA, \
+          SmmAccess, \
+          SMM_ACCESS_PRIVATE_DATA_SIGNATURE \
+      )
+
+///
+/// Prototypes
+/// Driver model protocol interface
+///
+/**
+    This is the standard PEIM entry point that
+    installs an SMM Access PPI
+
+  @param[in] FfsHeader   - Pointer to an alleged FFS file.
+  @param[in] PeiServices - General purpose services available to every PEIM.
+
+  @retval EFI_STATUS - Protocol successfully started and installed
+**/
+EFI_STATUS
+EFIAPI
+SmmAccessPeimEntryPoint (
+  IN EFI_FFS_FILE_HEADER       *FfsHeader,
+  IN EFI_PEI_SERVICES          **PeiServices
+  )
+;
+
+/**
+  This routine accepts a request to "open" a region of SMRAM.  The
+  region could be legacy ABSEG, HSEG, or TSEG near top of physical memory.
+  The use of "open" means that the memory is visible from all boot-service
+  and SMM agents.
+
+  @param[in] PeiServices      -  General purpose services available to every PEIM.
+  @param[in] This             -  Pointer to the SMM Access Interface.
+  @param[in] DescriptorIndex  -  Region of SMRAM to Open.
+
+  @retval EFI_SUCCESS            -  The region was successfully opened.
+  @retval EFI_DEVICE_ERROR       -  The region could not be opened because locked by
+                            chipset.
+  @retval EFI_INVALID_PARAMETER  -  The descriptor index was out of bounds.
+**/
+EFI_STATUS
+EFIAPI
+Open (
+  IN EFI_PEI_SERVICES        **PeiServices,
+  IN PEI_SMM_ACCESS_PPI      *This,
+  IN UINTN                   DescriptorIndex
+  )
+;
+
+/**
+  This routine accepts a request to "close" a region of SMRAM.  The
+  region could be legacy AB or TSEG near top of physical memory.
+  The use of "close" means that the memory is only visible from SMM agents,
+  not from BS or RT code.
+
+  @param[in] PeiServices           - General purpose services available to every PEIM.
+  @param[in] This                  - Pointer to the SMM Access Interface.
+  @param[in] DescriptorIndex       - Region of SMRAM to Close.
+
+  @retval EFI_SUCCESS           - The region was successfully closed.
+  @retval EFI_DEVICE_ERROR      - The region could not be closed because locked by
+                            chipset.
+  @retval EFI_INVALID_PARAMETER - The descriptor index was out of bounds.
+**/
+EFI_STATUS
+EFIAPI
+Close (
+  IN EFI_PEI_SERVICES        **PeiServices,
+  IN PEI_SMM_ACCESS_PPI      *This,
+  IN UINTN                   DescriptorIndex
+  )
+;
+
+/**
+  This routine accepts a request to "lock" SMRAM.  The
+  region could be legacy AB or TSEG near top of physical memory.
+  The use of "lock" means that the memory can no longer be opened
+  to BS state..
+
+  @param[in] PeiServices           - General purpose services available to every PEIM.
+  @param[in] This                  - Pointer to the SMM Access Interface.
+  @param[in] DescriptorIndex       - Region of SMRAM to Lock.
+
+  @retval EFI_SUCCESS           - The region was successfully locked.
+  @retval EFI_DEVICE_ERROR      - The region could not be locked because at least
+                          one range is still open.
+  @retval EFI_INVALID_PARAMETER - The descriptor index was out of bounds.
+**/
+EFI_STATUS
+EFIAPI
+Lock (
+  IN EFI_PEI_SERVICES        **PeiServices,
+  IN PEI_SMM_ACCESS_PPI      *This,
+  IN UINTN                   DescriptorIndex
+  )
+;
+
+/**
+  This routine services a user request to discover the SMRAM
+  capabilities of this platform.  This will report the possible
+  ranges that are possible for SMRAM access, based upon the
+  memory controller capabilities.
+
+  @param[in] PeiServices           - General purpose services available to every PEIM.
+  @param[in] This                  - Pointer to the SMRAM Access Interface.
+  @param[in] SmramMapSize          - Pointer to the variable containing size of the
+                            buffer to contain the description information.
+  @param[in] SmramMap              - Buffer containing the data describing the Smram
+                            region descriptors.
+
+  @retval EFI_BUFFER_TOO_SMALL  - The user did not provide a sufficient buffer.
+  @retval EFI_SUCCESS           - The user provided a sufficiently-sized buffer.
+**/
+EFI_STATUS
+EFIAPI
+GetCapabilities (
+  IN EFI_PEI_SERVICES            **PeiServices,
+  IN PEI_SMM_ACCESS_PPI          *This,
+  IN OUT UINTN                   *SmramMapSize,
+  IN OUT EFI_SMRAM_DESCRIPTOR    *SmramMap
+  )
+;
+
+#endif
diff --git a/ReferenceCode/Chipset/SystemAgent/SmmAccess/Pei/SmmAccessPeim.mak b/ReferenceCode/Chipset/SystemAgent/SmmAccess/Pei/SmmAccessPeim.mak
new file mode 100644
index 0000000..1cea8ff
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/SmmAccess/Pei/SmmAccessPeim.mak
@@ -0,0 +1,55 @@
+#---------------------------------------------------------------------------
+#   Create SmmAccessPeim Driver
+#---------------------------------------------------------------------------
+EDK : SmmAccessPeim
+SmmAccessPeim : $(BUILD_DIR)\SmmAccessPeim.mak SmmAccessPeimBin
+
+$(BUILD_DIR)\SmmAccessPeim.mak : $(SmmAccessPeim_DIR)\$(@B).cif $(SmmAccessPeim_DIR)\$(@B).mak $(BUILD_RULES)
+  $(CIF2MAK) $(SmmAccessPeim_DIR)\$(@B).cif $(CIF2MAK_DEFAULTS)
+
+SmmAccessPeim_INCLUDES=\
+  $(EDK_INCLUDES)\
+  $(EdkIIGlueLib_INCLUDES)\
+  $(INTEL_MCH_INCLUDES)\
+  $(INTEL_CPU_INCLUDES)\
+
+SmmAccessPeim_DEFINES = $(MY_DEFINES)\
+            /DMDE_CPU_IA32\
+            /D"__EDKII_GLUE_MODULE_ENTRY_POINT__=SmmAccessPeimEntryPoint"\
+            /D __EDKII_GLUE_BASE_IO_LIB_INTRINSIC__ \
+            /D __EDKII_GLUE_BASE_MEMORY_LIB__ \
+            /D __EDKII_GLUE_PEI_DEBUG_LIB_REPORT_STATUS_CODE__ \
+            /D __EDKII_GLUE_PEI_REPORT_STATUS_CODE_LIB__ \
+            /D __EDKII_GLUE_PEI_SERVICES_LIB__ \
+            /D __EDKII_GLUE_PEI_MEMORY_ALLOCATION_LIB__ \
+            /D __EDKII_GLUE_BASE_PCI_LIB_PCI_EXPRESS__ \
+            /D __EDKII_GLUE_PEI_HOB_LIB__\
+
+SmmAccessPeim_LIB_LINKS =\
+            $(EDKFRAMEWORKGUIDLIB)\
+            $(EDKPPILIB)\
+            $(EdkIIGlueBaseLibIA32_LIB)\
+            $(EdkIIGlueBaseIoLibIntrinsic_LIB)\
+            $(EdkIIGlueBaseMemoryLib_LIB)\
+            $(EdkIIGluePeiDebugLibReportStatusCode_LIB)\
+            $(EdkIIGluePeiReportStatusCodeLib_LIB)\
+            $(EdkIIGluePeiServicesLib_LIB)\
+            $(EdkIIGluePeiMemoryAllocationLib_LIB)\
+            $(EdkIIGlueBasePciLibPciExpress_LIB)\
+            $(EdkIIGlueBasePciExpressLib_LIB)\
+            $(EdkIIGluePeiHobLib_LIB)\
+            $(IntelSaSampleCodePpiLib_LIB)\
+
+SmmAccessPeimBin: $(SmmAccessPeim_LIB_LINKS) 
+            $(MAKE) /$(MAKEFLAGS) $(EDKIIGLUE_DEFAULTS)\
+            /f $(BUILD_DIR)\SmmAccessPeim.mak all\
+            NAME=SmmAccessPeim\
+            MAKEFILE=$(BUILD_DIR)\SmmAccessPeim.mak \
+            GUID=6ECFCE51-5724-450c-A38A-58553E954422\
+            "MY_INCLUDES=$(SmmAccessPeim_INCLUDES)"\
+            "MY_DEFINES=$(SmmAccessPeim_DEFINES)"\
+            ENTRY_POINT=_ModuleEntryPoint \
+            TYPE=PEIM \
+            EDKIIModule=PEIM\
+            DEPEX1=$(SmmAccessPeim_DIR)\SmmAccessPeim.dxs DEPEX1_TYPE=EFI_SECTION_PEI_DEPEX \
+            COMPRESS=0
diff --git a/ReferenceCode/Chipset/SystemAgent/SmmAccess/Pei/SmmAccessPeim.sdl b/ReferenceCode/Chipset/SystemAgent/SmmAccess/Pei/SmmAccessPeim.sdl
new file mode 100644
index 0000000..2217ebd
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/SmmAccess/Pei/SmmAccessPeim.sdl
@@ -0,0 +1,30 @@
+TOKEN
+	Name  = "SmmAccessPeim_SUPPORT"
+	Value  = "1"
+	Help  = "Main switch to enable SmmAccess support in Project"
+	TokenType = Boolean
+	TargetMAK = Yes
+	Master = Yes
+	Token = "SMM_SUPPORT" "=" "1"
+End
+
+PATH
+	Name  = "SmmAccessPeim_DIR"
+End
+
+MODULE
+	Help  = "Includes SmmAccess to Project"
+	File  = "SmmAccessPeim.mak"
+End
+
+ELINK
+	Name  = "SmmAccessPeim"
+	InvokeOrder = ReplaceParent
+End
+
+ELINK
+	Name  = "$(BUILD_DIR)\SmmAccessPeim.ffs"
+	Parent  = "FV_BB"
+	InvokeOrder = AfterParent
+End
+
diff --git a/ReferenceCode/Chipset/SystemAgent/SystemAgent.cif b/ReferenceCode/Chipset/SystemAgent/SystemAgent.cif
new file mode 100644
index 0000000..7ddc687
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/SystemAgent.cif
@@ -0,0 +1,27 @@
+<component>
+	name = "Intel SystemAgent NB Refcode"
+	category = ModulePart
+	LocalRoot = "ReferenceCode\Chipset\SystemAgent"
+	RefName = "Intel SystemAgent NB Refcode"
+[files]
+"SystemAgent.sdl"	
+[parts]
+"MemoryInit"
+"PciHostBridge"
+"SmBiosMemory"
+"SmmAccess"
+"SmmAccessPeim"
+"SaAcpiTables"
+"SaGuidLib"
+"SaInclude"
+"SaPcieLib"
+"SaPcieDxeLib"
+"SaPcieSmmLib"
+"SaPpiLib"
+"SaProtocolLib"
+"SaSampleCode"
+"SaInitDxe"
+"SaInitPeim"
+"SaLateInitSmm"
+"BdatAccessHandler"
+<endComponent>
diff --git a/ReferenceCode/Chipset/SystemAgent/SystemAgent.sdl b/ReferenceCode/Chipset/SystemAgent/SystemAgent.sdl
new file mode 100644
index 0000000..48c6a4f
--- /dev/null
+++ b/ReferenceCode/Chipset/SystemAgent/SystemAgent.sdl
@@ -0,0 +1,337 @@
+TOKEN
+	Name  = "SystemAgent_SUPPORT"
+	Value  = "1"
+	Help  = "Main switch to enable SystemAgent support in Project"
+	TokenType = Boolean
+	TargetEQU = Yes
+	TargetMAK = Yes
+	TargetH = Yes
+	Master = Yes
+End
+
+TOKEN
+	Name  = "PEG_SUPPORT"
+	Value  = "1"
+	TokenType = Boolean
+	TargetMAK = Yes
+End
+
+TOKEN
+	Name  = "DMI_SUPPORT"
+	Value  = "1"
+	TokenType = Boolean
+	TargetMAK = Yes
+End
+
+TOKEN
+	Name  = "SwitchableGraphics_SUPPORT"
+	Value  = "1"
+	TokenType = Boolean
+	TargetMAK = Yes
+	TargetH = Yes
+End
+
+TOKEN
+	Name  = "GPIO_dGPU_SELECT"
+	Value  = "52"
+	TokenType = Integer
+	TargetEQU = Yes
+	TargetH = Yes
+End
+
+TOKEN
+	Name  = "ACTIVE_dGPU_SELECT"
+	Value  = "0"
+	TokenType = Integer
+	TargetEQU = Yes
+	TargetH = Yes
+End
+
+TOKEN
+	Name  = "====== SharkBay MB/DT Two Chip platform GPIO setting======"
+	TokenType = Expression
+End
+
+TOKEN
+	Name  = "GPIO_dGPU_PRSNT"
+	Value  = "67"
+	Help  = "PCH GPIO bit offset on HuronRiver CRB-Emerald Lake\Unused GPIOs must return 0xFF"
+	TokenType = Integer
+	TargetEQU = Yes
+	TargetH = Yes
+End
+
+TOKEN
+	Name  = "ACTIVE_dGPU_PRSNT"
+	Value  = "0"
+	Help  = "PCH GPIO bit offset on HuronRiver CRB-Emerald Lake"
+	TokenType = Integer
+	TargetEQU = Yes
+	TargetH = Yes
+End
+
+TOKEN
+	Name  = "GPIO_dGPU_PWR_EN"
+	Value  = "54"
+	TokenType = Integer
+	TargetEQU = Yes
+	TargetH = Yes
+End
+
+TOKEN
+	Name  = "ACTIVE_dGPU_PWR_EN"
+	Value  = "0"
+	TokenType = Integer
+	TargetEQU = Yes
+	TargetH = Yes
+End
+
+TOKEN
+	Name  = "GPIO_dGPU_PWROK"
+	Value  = "17"
+	TokenType = Integer
+	TargetEQU = Yes
+	TargetH = Yes
+End
+
+TOKEN
+	Name  = "ACTIVE_dGPU_PWROK"
+	Value  = "1"
+	TokenType = Integer
+	TargetEQU = Yes
+	TargetH = Yes
+End
+
+TOKEN
+	Name  = "GPIO_dGPU_HOLD_RST"
+	Value  = "50"
+	TokenType = Integer
+	TargetEQU = Yes
+	TargetH = Yes
+End
+
+TOKEN
+	Name  = "ACTIVE_dGPU_HOLD_RST"
+	Value  = "0"
+	TokenType = Integer
+	TargetEQU = Yes
+	TargetH = Yes
+End
+
+TOKEN
+	Name  = "====== SharkBay ULT platform GPIO setting======"
+	TokenType = Expression
+End
+
+TOKEN
+	Name  = "GPIO_dGPU_PRSNT_ULT"
+	Value  = "67"
+	Help  = "PCH GPIO bit offset on HuronRiver CRB-Emerald Lake\Unused GPIOs must return 0xFF"
+	TokenType = Integer
+	TargetEQU = Yes
+	TargetH = Yes
+End
+
+TOKEN
+	Name  = "ACTIVE_dGPU_PRSNT_ULT"
+	Value  = "0"
+	Help  = "PCH GPIO bit offset on HuronRiver CRB-Emerald Lake"
+	TokenType = Integer
+	TargetEQU = Yes
+	TargetH = Yes
+End
+
+TOKEN
+	Name  = "GPIO_dGPU_PWR_EN_ULT"
+	Value  = "84"
+	TokenType = Integer
+	TargetEQU = Yes
+	TargetH = Yes
+End
+
+TOKEN
+	Name  = "ACTIVE_dGPU_PWR_EN_ULT"
+	Value  = "0"
+	TokenType = Integer
+	TargetEQU = Yes
+	TargetH = Yes
+End
+
+TOKEN
+	Name  = "GPIO_dGPU_PWROK_ULT"
+	Value  = "17"
+	TokenType = Integer
+	TargetEQU = Yes
+	TargetH = Yes
+End
+
+TOKEN
+	Name  = "ACTIVE_dGPU_PWROK_ULT"
+	Value  = "1"
+	TokenType = Integer
+	TargetEQU = Yes
+	TargetH = Yes
+End
+
+TOKEN
+	Name  = "GPIO_dGPU_HOLD_RST_ULT"
+	Value  = "48"
+	TokenType = Integer
+	TargetEQU = Yes
+	TargetH = Yes
+End
+
+TOKEN
+	Name  = "ACTIVE_dGPU_HOLD_RST_ULT"
+	Value  = "0"
+	TokenType = Integer
+	TargetEQU = Yes
+	TargetH = Yes
+End
+
+TOKEN
+	Name  = "====== SharkBay ULT platform port function setting======"
+	TokenType = Expression
+End
+
+TOKEN
+	Name  = "SG_ULT_PORT_FUNC"
+	Value  = "0x04"
+	Help  = "Port Function Number."
+	TokenType = Integer
+	TargetH = Yes
+End
+
+TOKEN
+	Name  = "MRC_BDAT_SUPPORT"
+	Value  = "1"
+	TokenType = Boolean
+	TargetEQU = Yes
+	TargetMAK = Yes
+	TargetH = Yes
+	Help  = "Main switch to enable BdatAccessHandler support in Project"
+End
+
+ELINK
+	Name  = "INTEL_SA_RC_FLAGS"
+	Help  = "System Agent Reference Code command line options of the compiler"
+	InvokeOrder = ReplaceParent
+End
+
+ELINK
+	Name  = "$(INTEL_SA_RC_FLAGS)"
+	Parent  = "GLOBAL_DEFINES"
+	InvokeOrder = AfterParent
+End
+
+ELINK
+	Name  = "$(INTEL_SA_RC_FLAGS)"
+	Parent  = "ASLPREPROCESS_FLAG"
+	InvokeOrder = AfterParent
+End
+
+ELINK
+	Name  = "/D PEG_FLAG"
+	Parent  = "INTEL_SA_RC_FLAGS"
+	Token = "PEG_SUPPORT" "=" "1"
+	InvokeOrder = AfterParent
+End
+
+ELINK
+	Name  = "/D DMI_FLAG"
+	Parent  = "INTEL_SA_RC_FLAGS"
+	Token = "DMI_SUPPORT" "=" "1"
+	InvokeOrder = AfterParent
+End
+
+ELINK
+	Name  = "/D SG_SUPPORT"
+	Parent  = "INTEL_SA_RC_FLAGS"
+	Token = "SwitchableGraphics_SUPPORT" "=" "1"
+	InvokeOrder = AfterParent
+End
+
+ELINK
+	Name  = "/D PciHotPlug_SUPPORT"
+	Parent  = "INTEL_SA_RC_FLAGS"
+	Token = "HOTPLUG_SUPPORT" "=" "1"
+	InvokeOrder = AfterParent
+End
+
+ELINK
+	Name  = "/D AMI_SgTpv_SUPPORT"
+	Parent  = "INTEL_SA_RC_FLAGS"
+	InvokeOrder = AfterParent
+	Token = "SgTpv_SUPPORT" "=" "1"
+	Token = "SwitchableGraphics_SUPPORT" "=" "1"
+End
+
+ELINK
+	Name  = "/D BDAT_SUPPORT"
+	Parent  = "INTEL_SA_RC_FLAGS"
+	InvokeOrder = AfterParent
+	Token = "MRC_BDAT_SUPPORT" "=" "1"
+End
+
+PATH
+	Name  = "INTEL_SYSTEM_AGENT_DIR"
+End
+
+ELINK
+	Name  = "INTEL_MCH_INCLUDES"
+	InvokeOrder = ReplaceParent
+End
+
+ELINK
+	Name  = "/I$(INTEL_SYSTEM_AGENT_DIR)"
+	Parent  = "INTEL_MCH_INCLUDES"
+	InvokeOrder = AfterParent
+End
+
+ELINK
+	Name  = "/I$(INTEL_SA_INCLUDE_DIR)"
+	Parent  = "INTEL_MCH_INCLUDES"
+	InvokeOrder = AfterParent
+End
+
+ELINK
+	Name  = "/I$(INTEL_SYSTEM_AGENT_DIR)\SampleCode"
+	Parent  = "INTEL_MCH_INCLUDES"
+	InvokeOrder = AfterParent
+End
+
+ELINK
+	Name  = "/I$(INTEL_SYSTEM_AGENT_DIR)\SampleCode\Include"
+	Parent  = "INTEL_MCH_INCLUDES"
+	InvokeOrder = AfterParent
+End
+
+ELINK
+	Name  = "/I$(INTEL_SYSTEM_AGENT_DIR)\MemoryInit\Pei\Source\Api"
+	Parent  = "INTEL_MCH_INCLUDES"
+	InvokeOrder = AfterParent
+End
+
+ELINK
+	Name  = "/I$(INTEL_SYSTEM_AGENT_DIR)\MemoryInit"
+	Parent  = "INTEL_MCH_INCLUDES"
+	InvokeOrder = AfterParent
+End
+
+ELINK
+	Name  = "/I$(INTEL_SYSTEM_AGENT_DIR)\MemoryInit\Pei"
+	Parent  = "INTEL_MCH_INCLUDES"
+	InvokeOrder = AfterParent
+End
+
+ELINK
+	Name  = "/I$(INTEL_SYSTEM_AGENT_DIR)\MemoryInit\Pei\Source\Include"
+	Parent  = "INTEL_MCH_INCLUDES"
+	InvokeOrder = AfterParent
+End
+
+ELINK
+	Name  = "/I$(INTEL_SYSTEM_AGENT_DIR)\MemoryInit\Pei\Source\Include\MrcRegisters"
+	Parent  = "INTEL_MCH_INCLUDES"
+	InvokeOrder = AfterParent
+End