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Diffstat (limited to 'ReferenceCode/Chipset/LynxPoint/SampleCode/PchPolicyInit')
10 files changed, 1569 insertions, 0 deletions
diff --git a/ReferenceCode/Chipset/LynxPoint/SampleCode/PchPolicyInit/Common/PchPolicyInitCommon.c b/ReferenceCode/Chipset/LynxPoint/SampleCode/PchPolicyInit/Common/PchPolicyInitCommon.c new file mode 100644 index 0000000..8845a6d --- /dev/null +++ b/ReferenceCode/Chipset/LynxPoint/SampleCode/PchPolicyInit/Common/PchPolicyInitCommon.c @@ -0,0 +1,427 @@ +/** @file + This file is SampleCode for Intel PCH Common Platform Policy initialzation. + +@copyright + Copyright (c) 2013 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement + +**/ +#if !defined(EDK_RELEASE_VERSION) || (EDK_RELEASE_VERSION < 0x00020000) +#include "EdkIIGlueDxe.h" +#include "EdkIIGlueBase.h" +#include "PchPlatformPolicy.h" +#include "PchPlatformLib.h" +#include "PchRegs.h" +#endif + +/** + Initilize Intel USB Common Platform Policy + + @param[in] PchUsbConfig Usb platform policy structure. + + @retval NONE +**/ +VOID +InitPchUsbConfig ( + IN PCH_USB_CONFIG *PchUsbConfig + ) +{ + UINTN PortIndex; + UINT16 LpcDeviceId; + PCH_SERIES PchSeries; + + if (PchUsbConfig == NULL) { + return; + } + + PchSeries = GetPchSeries(); + LpcDeviceId = MmioRead16 (MmPciAddress (0, 0, PCI_DEVICE_NUMBER_PCH_LPC, PCI_FUNCTION_NUMBER_PCH_LPC, 0) + R_PCH_LPC_DEVICE_ID); + + // + // EHCI Host Controller Enable/Disable + // + PchUsbConfig->Usb20Settings[0].Enable = PCH_DEVICE_ENABLE; + PchUsbConfig->Usb20Settings[1].Enable = PCH_DEVICE_ENABLE; + + // + // Automatically disable EHCI when XHCI Mode is Enabled to save power. + // + if (PchUsbConfig->Usb30Settings.Mode == PCH_XHCI_MODE_ON) { + PchUsbConfig->Usb20Settings[0].Enable = PCH_DEVICE_DISABLE; + if (PchSeries == PchH) { + PchUsbConfig->Usb20Settings[1].Enable = PCH_DEVICE_DISABLE; + } + } + // + // Set to Enable if BIOS has its own xHCI driver + // + PchUsbConfig->Usb30Settings.PreBootSupport = PCH_DEVICE_ENABLE; + /// + /// PCH BIOS Spec Rev 0.5.0 Section 13.1 xHCI controller options in Reference Code + /// Please refer to Table 13-1 in PCH BIOS Spec for USB Port Operation with no xHCI + /// pre-boot software. + /// Please refer to Table 13-2 in PCH BIOS Spec for USB Port Operation with xHCI + /// pre-boot software. + /// + /// The xHCI modes that available in BIOS are: + /// Disabled - forces only USB 2.0 to be supported in the OS. The xHCI controller is turned off + /// and hidden from the PCI space. + /// Enabled - allows USB 3.0 to be supported in the OS. The xHCI controller is turned on. The + /// shareable ports are routed to the xHCI controller. OS needs to provide drivers + /// to support USB 3.0. + /// Auto - This mode uses ACPI protocol to provide an option that enables the xHCI controller + /// and reroute USB ports via the _OSC ACPI method call. Note, this mode switch requires + /// special OS driver support for USB 3.0. + /// Smart Auto - This mode is similar to Auto, but it adds the capability to route the ports to xHCI + /// or EHCI according to setting used in previous boots (for non-G3 boot) in the pre-boot + /// environment. This allows the use of USB 3.0 devices prior to OS boot. Note, this mode + /// switch requires special OS driver support for USB 3.0 and USB 3.0 software available + /// in the pre-boot enviroment. + /// + /// Manual Mode - For validation and experimental purposes only. Do not create setup option for end-user BIOS. + /// + /// Recommendations: + /// - If BIOS supports xHCI pre-boot driver then use Smart Auto mode as default + /// - If BIOS does not support xHCI pre-boot driver then use AUTO mode as default + /// + if (PchUsbConfig->Usb30Settings.PreBootSupport == PCH_DEVICE_ENABLE) { + PchUsbConfig->Usb30Settings.Mode = PCH_XHCI_MODE_SMARTAUTO; + } else { + PchUsbConfig->Usb30Settings.Mode = PCH_XHCI_MODE_AUTO; + } + + // + // Manual Mode is for validation and experimental purposes only. + // Do not create setup option for end-user BIOS. + // + PchUsbConfig->Usb30Settings.ManualMode = PCH_DEVICE_DISABLE; + + // + // XhciIdleL1 can be set to disable for LPT-LP Ax stepping to workaround USB3 hot plug will fail after 1 hot plug removal. + // + PchUsbConfig->Usb30Settings.XhciIdleL1 = PCH_DEVICE_ENABLE; + + // + // Btcg is for enabling/disabling trunk clock gating. + // + PchUsbConfig->Usb30Settings.Btcg = PCH_DEVICE_ENABLE; + + for (PortIndex = 0; PortIndex < GetPchUsbMaxPhysicalPortNum (); PortIndex++) { + PchUsbConfig->Usb30Settings.ManualModeUsb20PerPinRoute[PortIndex] = 0; + } + + for (PortIndex = 0; PortIndex < GetPchXhciMaxUsb3PortNum (); PortIndex++) { + PchUsbConfig->Usb30Settings.ManualModeUsb30PerPinEnable[PortIndex] = PCH_DEVICE_DISABLE; + } + + // + // Use by AMT/MEBx to enable USB-R support. + // + PchUsbConfig->Ehci1Usbr = PCH_DEVICE_DISABLE; + PchUsbConfig->Ehci2Usbr = PCH_DEVICE_DISABLE; + + // + // UsbPrecondition = Enable , Force USB Init happen in PEI as part of 2Sec Fast Boot bios optimization + // UsbPrecondition = Disable, USB Init happen in DXE just like traditionally where it happen. + // + PchUsbConfig->UsbPrecondition = PCH_DEVICE_DISABLE; + + // + // USB Per-Port Control is use to Enable/Disable individual port. + // + PchUsbConfig->UsbPerPortCtl = PCH_DEVICE_DISABLE; + + PchUsbConfig->PortSettings[0].Enable = PCH_DEVICE_ENABLE; + PchUsbConfig->PortSettings[1].Enable = PCH_DEVICE_ENABLE; + PchUsbConfig->PortSettings[2].Enable = PCH_DEVICE_ENABLE; + PchUsbConfig->PortSettings[3].Enable = PCH_DEVICE_ENABLE; + PchUsbConfig->PortSettings[4].Enable = PCH_DEVICE_ENABLE; + PchUsbConfig->PortSettings[5].Enable = PCH_DEVICE_ENABLE; + PchUsbConfig->PortSettings[6].Enable = PCH_DEVICE_ENABLE; + PchUsbConfig->PortSettings[7].Enable = PCH_DEVICE_ENABLE; + PchUsbConfig->PortSettings[8].Enable = PCH_DEVICE_ENABLE; + PchUsbConfig->PortSettings[9].Enable = PCH_DEVICE_ENABLE; + PchUsbConfig->PortSettings[10].Enable = PCH_DEVICE_ENABLE; + PchUsbConfig->PortSettings[11].Enable = PCH_DEVICE_ENABLE; + PchUsbConfig->PortSettings[12].Enable = PCH_DEVICE_ENABLE; + PchUsbConfig->PortSettings[13].Enable = PCH_DEVICE_ENABLE; + + PchUsbConfig->Port30Settings[0].Enable = PCH_DEVICE_ENABLE; + PchUsbConfig->Port30Settings[1].Enable = PCH_DEVICE_ENABLE; + PchUsbConfig->Port30Settings[2].Enable = PCH_DEVICE_ENABLE; + PchUsbConfig->Port30Settings[3].Enable = PCH_DEVICE_ENABLE; + PchUsbConfig->Port30Settings[4].Enable = PCH_DEVICE_ENABLE; + PchUsbConfig->Port30Settings[5].Enable = PCH_DEVICE_ENABLE; + + // + // USB Port Over Current Pins mapping, please set as per board layout. + // + PchUsbConfig->Usb20OverCurrentPins[ 0] = PchUsbOverCurrentPin0; + PchUsbConfig->Usb20OverCurrentPins[ 1] = PchUsbOverCurrentPin0; + PchUsbConfig->Usb20OverCurrentPins[ 2] = PchUsbOverCurrentPin1; + PchUsbConfig->Usb20OverCurrentPins[ 3] = PchUsbOverCurrentPin1; + PchUsbConfig->Usb20OverCurrentPins[ 4] = PchUsbOverCurrentPin2; + PchUsbConfig->Usb20OverCurrentPins[ 5] = PchUsbOverCurrentPin2; + PchUsbConfig->Usb20OverCurrentPins[ 6] = PchUsbOverCurrentPin3; + PchUsbConfig->Usb20OverCurrentPins[ 7] = PchUsbOverCurrentPin3; + PchUsbConfig->Usb20OverCurrentPins[ 8] = PchUsbOverCurrentPin4; + PchUsbConfig->Usb20OverCurrentPins[ 9] = PchUsbOverCurrentPin4; + PchUsbConfig->Usb20OverCurrentPins[10] = PchUsbOverCurrentPin5; + PchUsbConfig->Usb20OverCurrentPins[11] = PchUsbOverCurrentPin5; + PchUsbConfig->Usb20OverCurrentPins[12] = PchUsbOverCurrentPin6; + PchUsbConfig->Usb20OverCurrentPins[13] = PchUsbOverCurrentPin6; + + PchUsbConfig->Usb30OverCurrentPins[0] = PchUsbOverCurrentPin0; + PchUsbConfig->Usb30OverCurrentPins[1] = PchUsbOverCurrentPin0; + PchUsbConfig->Usb30OverCurrentPins[2] = PchUsbOverCurrentPin1; + PchUsbConfig->Usb30OverCurrentPins[3] = PchUsbOverCurrentPin1; + PchUsbConfig->Usb30OverCurrentPins[4] = PchUsbOverCurrentPin2; + PchUsbConfig->Usb30OverCurrentPins[5] = PchUsbOverCurrentPin2; + + // + // USB 2.0 D+/D- trace length in inchs*10 or 1000mils/10 measurement eg. 12.3" = 0x123 + // Please set as per board layout. + // + PchUsbConfig->PortSettings[ 0].Usb20PortLength = 0x100; + PchUsbConfig->PortSettings[ 1].Usb20PortLength = 0x100; + PchUsbConfig->PortSettings[ 2].Usb20PortLength = 0x100; + PchUsbConfig->PortSettings[ 3].Usb20PortLength = 0x100; + PchUsbConfig->PortSettings[ 4].Usb20PortLength = 0x100; + PchUsbConfig->PortSettings[ 5].Usb20PortLength = 0x100; + PchUsbConfig->PortSettings[ 6].Usb20PortLength = 0x100; + PchUsbConfig->PortSettings[ 7].Usb20PortLength = 0x100; + PchUsbConfig->PortSettings[ 8].Usb20PortLength = 0x100; + PchUsbConfig->PortSettings[ 9].Usb20PortLength = 0x100; + PchUsbConfig->PortSettings[10].Usb20PortLength = 0x100; + PchUsbConfig->PortSettings[11].Usb20PortLength = 0x100; + PchUsbConfig->PortSettings[12].Usb20PortLength = 0x100; + PchUsbConfig->PortSettings[13].Usb20PortLength = 0x100; + + // + // Port Location + // + PchUsbConfig->PortSettings[ 0].Location = PchUsbPortLocationFrontPanel; + PchUsbConfig->PortSettings[ 1].Location = PchUsbPortLocationFrontPanel; + PchUsbConfig->PortSettings[ 2].Location = PchUsbPortLocationFrontPanel; + PchUsbConfig->PortSettings[ 3].Location = PchUsbPortLocationFrontPanel; + PchUsbConfig->PortSettings[ 4].Location = PchUsbPortLocationFrontPanel; + PchUsbConfig->PortSettings[ 5].Location = PchUsbPortLocationFrontPanel; + PchUsbConfig->PortSettings[ 6].Location = PchUsbPortLocationFrontPanel; + PchUsbConfig->PortSettings[ 7].Location = PchUsbPortLocationFrontPanel; + PchUsbConfig->PortSettings[ 8].Location = PchUsbPortLocationFrontPanel; + PchUsbConfig->PortSettings[ 9].Location = PchUsbPortLocationFrontPanel; + PchUsbConfig->PortSettings[10].Location = PchUsbPortLocationFrontPanel; + PchUsbConfig->PortSettings[11].Location = PchUsbPortLocationFrontPanel; + PchUsbConfig->PortSettings[12].Location = PchUsbPortLocationFrontPanel; + PchUsbConfig->PortSettings[13].Location = PchUsbPortLocationFrontPanel; + +/* + Guideline: + This algorithm is move from chipset level code to board level code to allow OEM more flexibility + to tune the value for individual board layout electrical characteristics to pass the USB 2.0 Eye Diagram Test. + + IF Board=LPT-H Desktop + For BIT[10:08] Usb20EyeDiagramTuningParam1 (PERPORTTXISET) + IF Back Panel + SET to 4 + ELSE + SET to 3 + ENDIF + + For BIT[13:11] Usb20EyeDiagramTuningParam2 (PERPORTPETXISET) + IF Back Panel + IF Trace Length < 8" + SET to 2 + ELSE IF Trace Length < 13" + SET to 3 + ELSE + SET to 4 + ENDIF + ELSE + SET to 2 + ENDIF + + For BIT[14] + Always SET to 0 + + END LPT-H Desktop + + IF Board=LPT-H Mobile + For BIT[10:08] Usb20EyeDiagramTuningParam1 (PERPORTTXISET) + IF Interal Topology + SET to 5 + ELSE IF Dock + SET to 4 + ELSE + IF Trace Length < 7" + SET to 5 + ELSE + SET to 6 + ENDIF + ENDIF + + For BIT[13:11] Usb20EyeDiagramTuningParam2 (PERPORTPETXISET) + IF Interal Topology + SET to 2 + ELSE IF Dock + IF Trace Length < 5" + SET to 1 + ELSE + SET to 2 + ENDIF + ELSE + IF Trace Length < 10" + SET to 2 + ELSE + SET to 3 + ENDIF + ENDIF + + For BIT[14] + Always SET to 0 + END LPT-H Mobile + + IF Board=LPT-LP + For BIT[10:08] Usb20EyeDiagramTuningParam1 (PERPORTTXISET) + IF Back Panel OR MiniPciE + IF Trace Length < 7" + SET to 5 + ELSE + SET to 6 + ENDIF + ELSE IF Dock + SET to 4 + ELSE + SET to 5 + ENDIF + + For BIT[13:11] Usb20EyeDiagramTuningParam2 (PERPORTPETXISET) + IF Back Panel OR MiniPciE + IF Trace Length < 10" + SET to 2 + ELSE + SET to 3 + ENDIF + ELSE IF Dock + IF Trace Length < 5" + SET to 1 + ELSE + SET to 2 + ENDIF + ELSE + SET to 2 + ENDIF + + For BIT[14] + Always SET to 0 + END LPT-LP +*/ + + // + // USB 2.0 trace length signal strength + // +/* + IF Board=LPT-H Mobile + + END LPT-H Mobile +*/ + + if (PchSeries == PchH) { + if (IS_PCH_LPT_LPC_DEVICE_ID_DESKTOP (LpcDeviceId)) { + for (PortIndex = 0; PortIndex < GetPchUsbMaxPhysicalPortNum (); PortIndex++) { + if (PchUsbConfig->PortSettings[PortIndex].Location == PchUsbPortLocationBackPanel) { + PchUsbConfig->PortSettings[PortIndex].Usb20EyeDiagramTuningParam1 = 4; //Back Panel + } else { + PchUsbConfig->PortSettings[PortIndex].Usb20EyeDiagramTuningParam1 = 3; //Front Panel + } + + if (PchUsbConfig->PortSettings[PortIndex].Location == PchUsbPortLocationBackPanel) { + if (PchUsbConfig->PortSettings[PortIndex].Usb20PortLength < 0x80) { + PchUsbConfig->PortSettings[PortIndex].Usb20EyeDiagramTuningParam2 = 2; //Back Panel, less than 7.9" + } else if (PchUsbConfig->PortSettings[PortIndex].Usb20PortLength < 0x130) { + PchUsbConfig->PortSettings[PortIndex].Usb20EyeDiagramTuningParam2 = 3; //Back Panel, 8"-12.9" + } else { + PchUsbConfig->PortSettings[PortIndex].Usb20EyeDiagramTuningParam2 = 4; //Back Panel, 13" onward + } + } else { + PchUsbConfig->PortSettings[PortIndex].Usb20EyeDiagramTuningParam2 = 2; //Front Panel + } + } + } else if (IS_PCH_LPT_LPC_DEVICE_ID_MOBILE (LpcDeviceId)) { + for (PortIndex = 0; PortIndex < GetPchUsbMaxPhysicalPortNum (); PortIndex++) { + if (PchUsbConfig->PortSettings[PortIndex].Location == PchUsbPortLocationInternalTopology) { + PchUsbConfig->PortSettings[PortIndex].Usb20EyeDiagramTuningParam1 = 5; // Internal Topology + } else if (PchUsbConfig->PortSettings[PortIndex].Location == PchUsbPortLocationDock) { + PchUsbConfig->PortSettings[PortIndex].Usb20EyeDiagramTuningParam1 = 4; // Dock + } else { + if (PchUsbConfig->PortSettings[PortIndex].Usb20PortLength < 0x70) { + PchUsbConfig->PortSettings[PortIndex].Usb20EyeDiagramTuningParam1 = 5; //Back Panel, less than 7" + } else { + PchUsbConfig->PortSettings[PortIndex].Usb20EyeDiagramTuningParam1 = 6; //Back Panel, 7" onward + } + } + + if (PchUsbConfig->PortSettings[PortIndex].Location == PchUsbPortLocationInternalTopology) { + PchUsbConfig->PortSettings[PortIndex].Usb20EyeDiagramTuningParam2 = 2; // Internal Topology + } else if (PchUsbConfig->PortSettings[PortIndex].Location == PchUsbPortLocationDock) { + if (PchUsbConfig->PortSettings[PortIndex].Usb20PortLength < 0x50) { + PchUsbConfig->PortSettings[PortIndex].Usb20EyeDiagramTuningParam2 = 1; //Dock, less than 5" + } else { + PchUsbConfig->PortSettings[PortIndex].Usb20EyeDiagramTuningParam2 = 2; //Dock, 5" onward + } + } else { + if (PchUsbConfig->PortSettings[PortIndex].Usb20PortLength < 0x100) { + PchUsbConfig->PortSettings[PortIndex].Usb20EyeDiagramTuningParam2 = 2; //Back Panel, less than 10" + } else { + PchUsbConfig->PortSettings[PortIndex].Usb20EyeDiagramTuningParam2 = 3; //Back Panel, 10" onward + } + } + } + } + } else if (PchSeries == PchLp) { + for (PortIndex = 0; PortIndex < GetPchUsbMaxPhysicalPortNum (); PortIndex++) { + if ((PchUsbConfig->PortSettings[PortIndex].Location == PchUsbPortLocationBackPanel) || + (PchUsbConfig->PortSettings[PortIndex].Location == PchUsbPortLocationMiniPciE)) { + if (PchUsbConfig->PortSettings[PortIndex].Usb20PortLength < 0x70) { + PchUsbConfig->PortSettings[PortIndex].Usb20EyeDiagramTuningParam1 = 5; //Back Panel, less than 7" + } else { + PchUsbConfig->PortSettings[PortIndex].Usb20EyeDiagramTuningParam1 = 6; //Back Panel, 7" onward + } + } else if (PchUsbConfig->PortSettings[PortIndex].Location == PchUsbPortLocationDock) { + PchUsbConfig->PortSettings[PortIndex].Usb20EyeDiagramTuningParam1 = 4; // Dock + } else { + PchUsbConfig->PortSettings[PortIndex].Usb20EyeDiagramTuningParam1 = 5; // Internal Topology + } + + if ((PchUsbConfig->PortSettings[PortIndex].Location == PchUsbPortLocationBackPanel) || + (PchUsbConfig->PortSettings[PortIndex].Location == PchUsbPortLocationMiniPciE)) { + if (PchUsbConfig->PortSettings[PortIndex].Usb20PortLength < 0x100) { + PchUsbConfig->PortSettings[PortIndex].Usb20EyeDiagramTuningParam2 = 2; //Back Panel, less than 10" + } else { + PchUsbConfig->PortSettings[PortIndex].Usb20EyeDiagramTuningParam2 = 3; //Back Panel, 10" onward + } + } else if (PchUsbConfig->PortSettings[PortIndex].Location == PchUsbPortLocationDock) { + if (PchUsbConfig->PortSettings[PortIndex].Usb20PortLength < 0x50) { + PchUsbConfig->PortSettings[PortIndex].Usb20EyeDiagramTuningParam2 = 1; //Dock, less than 5" + } else { + PchUsbConfig->PortSettings[PortIndex].Usb20EyeDiagramTuningParam2 = 2; //Dock, 5" onward + } + } else { + PchUsbConfig->PortSettings[PortIndex].Usb20EyeDiagramTuningParam2 = 2; // Internal Topology + } + } + } + + return; +} diff --git a/ReferenceCode/Chipset/LynxPoint/SampleCode/PchPolicyInit/Common/PchPolicyInitCommon.h b/ReferenceCode/Chipset/LynxPoint/SampleCode/PchPolicyInit/Common/PchPolicyInitCommon.h new file mode 100644 index 0000000..daf1750 --- /dev/null +++ b/ReferenceCode/Chipset/LynxPoint/SampleCode/PchPolicyInit/Common/PchPolicyInitCommon.h @@ -0,0 +1,33 @@ +/** @file + Header file for Common PchPolicyInit Library + +@copyright + Copyright (c) 2012 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement +**/ +#ifndef _PCH_POLICY_INIT_COMMON_H_ +#define _PCH_POLICY_INIT_COMMON_H_ + +/** + This function performs PCH USB Platform Policy initialzation + + @param[in] UsbConfig Pointer to PCH_USB_CONFIG data buffer. + + @retval NONE +**/ +VOID +InitPchUsbConfig ( + IN PCH_USB_CONFIG *UsbConfig + ); +#endif diff --git a/ReferenceCode/Chipset/LynxPoint/SampleCode/PchPolicyInit/Dxe/PchPolicyInitDxe.c b/ReferenceCode/Chipset/LynxPoint/SampleCode/PchPolicyInit/Dxe/PchPolicyInitDxe.c new file mode 100644 index 0000000..5deee40 --- /dev/null +++ b/ReferenceCode/Chipset/LynxPoint/SampleCode/PchPolicyInit/Dxe/PchPolicyInitDxe.c @@ -0,0 +1,490 @@ +/** @file + This file is SampleCode for Intel PCH DXE Platform Policy initialzation. + +@copyright + Copyright (c) 2009 - 2013 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement + +**/ +#include "PchPolicyInitDxe.h" +#include "..\Common\PchPolicyInitCommon.h" + +#define SW_SMI_BIOS_LOCK 0xA9 +#define PCI_CLASS_NETWORK 0x02 +#define PCI_CLASS_NETWORK_ETHERNET 0x00 +#define PCI_CLASS_NETWORK_OTHER 0x80 + +DXE_PCH_PLATFORM_POLICY_PROTOCOL mPchPolicyData = { 0 }; +PCH_DEVICE_ENABLING mPchDeviceEnabling = { 0 }; +PCH_USB_CONFIG mPchUsbConfig = { 0 }; +PCH_PCI_EXPRESS_CONFIG mPchPciExpressConfig = { 0 }; +PCH_SATA_CONFIG mPchSataConfig = { 0 }; +PCH_AZALIA_CONFIG mPchAzaliaConfig = { 0 }; +PCH_SMBUS_CONFIG mPchSmbusConfig = { 0 }; +PCH_MISC_PM_CONFIG mPchMiscPmConfig = { 0 }; +PCH_IO_APIC_CONFIG mPchIoApicConfig = { 0 }; +PCH_DEFAULT_SVID_SID mPchDefaultSvidSid = { 0 }; +PCH_LOCK_DOWN_CONFIG mPchLockDownConfig = { 0 }; +PCH_THERMAL_CONFIG mPchThermalConfig = { 0 }; +PCH_LPC_HPET_CONFIG mPchHpetConfig = { 0 }; +PCH_LPC_SIRQ_CONFIG mSerialIrqConfig = { 0 }; +PCH_DMI_CONFIG mPchDmiConfig = { 0 }; +PCH_PWR_OPT_CONFIG mPchPwrOptConfig = { 0 }; +PCH_MISC_CONFIG mPchMiscConfig = { 0 }; +PCH_AUDIO_DSP_CONFIG mAudioDspConfig = { 0 }; +PCH_SERIAL_IO_CONFIG mSerialIoConfig = { 0 }; + +UINT8 mSmbusRsvdAddresses[4] = { + 0xA0, + 0xA2, + 0xA4, + 0xA6 +}; + +PCH_PCIE_DEVICE_ASPM_OVERRIDE mDevAspmOverride[] = { + // + // Intel PRO/Wireless + // + {0x8086, 0x422b, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0xFFFF, 0xFFFFFFFF}, + {0x8086, 0x422c, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0xFFFF, 0xFFFFFFFF}, + {0x8086, 0x4238, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0xFFFF, 0xFFFFFFFF}, + {0x8086, 0x4239, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0xFFFF, 0xFFFFFFFF}, + // + // Intel WiMAX/WiFi Link + // + {0x8086, 0x0082, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0xFFFF, 0xFFFFFFFF}, + {0x8086, 0x0085, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0xFFFF, 0xFFFFFFFF}, + {0x8086, 0x0083, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0xFFFF, 0xFFFFFFFF}, + {0x8086, 0x0084, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0xFFFF, 0xFFFFFFFF}, + {0x8086, 0x0086, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0xFFFF, 0xFFFFFFFF}, + {0x8086, 0x0087, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0xFFFF, 0xFFFFFFFF}, + {0x8086, 0x0088, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0xFFFF, 0xFFFFFFFF}, + {0x8086, 0x0089, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0xFFFF, 0xFFFFFFFF}, + {0x8086, 0x008F, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0xFFFF, 0xFFFFFFFF}, + {0x8086, 0x0090, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0xFFFF, 0xFFFFFFFF}, + // + // Intel Crane Peak WLAN NIC + // + {0x8086, 0x08AE, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0xFFFF, 0xFFFFFFFF}, + {0x8086, 0x08AF, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0xFFFF, 0xFFFFFFFF}, + // + // Intel Crane Peak w/BT WLAN NIC + // + {0x8086, 0x0896, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0xFFFF, 0xFFFFFFFF}, + {0x8086, 0x0897, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0xFFFF, 0xFFFFFFFF}, + // + // Intel Kelsey Peak WiFi, WiMax + // + {0x8086, 0x0885, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0xFFFF, 0xFFFFFFFF}, + {0x8086, 0x0886, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0xFFFF, 0xFFFFFFFF}, + // + // Intel Centrino Wireless-N 105 + // + {0x8086, 0x0894, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0xFFFF, 0xFFFFFFFF}, + {0x8086, 0x0895, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0xFFFF, 0xFFFFFFFF}, + // + // Intel Centrino Wireless-N 135 + // + {0x8086, 0x0892, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0xFFFF, 0xFFFFFFFF}, + {0x8086, 0x0893, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0xFFFF, 0xFFFFFFFF}, + // + // Intel Centrino Wireless-N 2200 + // + {0x8086, 0x0890, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0xFFFF, 0xFFFFFFFF}, + {0x8086, 0x0891, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0xFFFF, 0xFFFFFFFF}, + // + // Intel Centrino Wireless-N 2230 + // + {0x8086, 0x0887, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0xFFFF, 0xFFFFFFFF}, + {0x8086, 0x0888, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0xFFFF, 0xFFFFFFFF}, + // + // Intel Centrino Wireless-N 6235 + // + {0x8086, 0x088E, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0xFFFF, 0xFFFFFFFF}, + {0x8086, 0x088F, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0xFFFF, 0xFFFFFFFF}, + // + // Intel CampPeak 2 Wifi + // + {0x8086, 0x08B5, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0xFFFF, 0xFFFFFFFF}, + {0x8086, 0x08B6, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0xFFFF, 0xFFFFFFFF}, + // + // Intel WilkinsPeak 1 Wifi + // + {0x8086, 0x08B3, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2AndL1SubstatesOverride, 0x0154, 0x00000003}, + {0x8086, 0x08B3, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1SubstatesOverride, 0x0158, 0x00000003}, + {0x8086, 0x08B4, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2AndL1SubstatesOverride, 0x0154, 0x00000003}, + {0x8086, 0x08B4, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1SubstatesOverride, 0x0158, 0x00000003}, + // + // Intel Wilkins Peak 2 Wifi + // + {0x8086, 0x08B1, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2AndL1SubstatesOverride, 0x0154, 0x00000003}, + {0x8086, 0x08B1, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1SubstatesOverride, 0x0158, 0x00000003}, + {0x8086, 0x08B2, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2AndL1SubstatesOverride, 0x0154, 0x00000003}, + {0x8086, 0x08B2, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1SubstatesOverride, 0x0158, 0x00000003}, + // + // Intel Wilkins Peak PF Wifi + // + {0x8086, 0x08B0, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0xFFFF, 0xFFFFFFFF} + +}; + +// +// Function implementations +// + +/** + Initilize Intel PCH DXE Platform Policy + + @param[in] ImageHandle Image handle of this driver. + @param[in] SystemTable Global system service table. + + @retval EFI_SUCCESS Initialization complete. + @exception EFI_UNSUPPORTED The chipset is unsupported by this driver. + @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver. + @retval EFI_DEVICE_ERROR Device error, driver exits abnormally. +**/ +EFI_STATUS +EFIAPI +PchPolicyInitDxeEntryPoint ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_HANDLE Handle; + EFI_STATUS Status; + UINT8 PortIndex; + UINTN Index; + PCH_SERIES PchSeries; + PchSeries = GetPchSeries(); + // + // General intialization + // + mPchPolicyData.Revision = DXE_PCH_PLATFORM_POLICY_PROTOCOL_REVISION_7; + mPchPolicyData.BusNumber = 0; + + mPchPolicyData.DeviceEnabling = &mPchDeviceEnabling; + mPchPolicyData.UsbConfig = &mPchUsbConfig; + mPchPolicyData.PciExpressConfig = &mPchPciExpressConfig; + mPchPolicyData.SataConfig = &mPchSataConfig; + mPchPolicyData.AzaliaConfig = &mPchAzaliaConfig; + mPchPolicyData.SmbusConfig = &mPchSmbusConfig; + mPchPolicyData.MiscPmConfig = &mPchMiscPmConfig; + mPchPolicyData.IoApicConfig = &mPchIoApicConfig; + mPchPolicyData.DefaultSvidSid = &mPchDefaultSvidSid; + mPchPolicyData.LockDownConfig = &mPchLockDownConfig; + mPchPolicyData.ThermalConfig = &mPchThermalConfig; + mPchPolicyData.HpetConfig = &mPchHpetConfig; + mPchPolicyData.SerialIrqConfig = &mSerialIrqConfig; + mPchPolicyData.DmiConfig = &mPchDmiConfig; + mPchPolicyData.PwrOptConfig = &mPchPwrOptConfig; + mPchPolicyData.MiscConfig = &mPchMiscConfig; + mPchPolicyData.AudioDspConfig = &mAudioDspConfig; + mPchPolicyData.SerialIoConfig = &mSerialIoConfig; + + /// + /// PCH BIOS Spec Rev 0.5.0 Section 3.6 Flash Security Recommendations, + /// Intel strongly recommends that BIOS sets the BIOS Interface Lock Down bit. Enabling this bit + /// will mitigate malicious software attempts to replace the system BIOS option ROM with its own code. + /// We always enable this as a platform policy. + /// + mPchLockDownConfig.BiosInterface = PCH_DEVICE_ENABLE; + mPchLockDownConfig.GlobalSmi = PCH_DEVICE_ENABLE; + mPchLockDownConfig.GpioLockDown = PCH_DEVICE_DISABLE; + mPchLockDownConfig.RtcLock = PCH_DEVICE_ENABLE; + /// + /// While BiosLock is enabled, BIOS can only be modified from SMM after ExitPmAuth. + /// + mPchLockDownConfig.BiosLock = PCH_DEVICE_DISABLE; + /// + /// If PchBiosLockIoTrapAddress is 0, BIOS will allocate available IO address with + /// 256 byte range from GCD and pass it to PchBiosLockIoTrapAddress. + /// + mPchLockDownConfig.PchBiosLockIoTrapAddress = 0; + /// + /// Initialize policy to default values when variable isn't found. + /// + mPchDeviceEnabling.Lan = PCH_DEVICE_ENABLE; + mPchDeviceEnabling.Azalia = 2; + mPchDeviceEnabling.Sata = PCH_DEVICE_ENABLE; + mPchDeviceEnabling.Smbus = PCH_DEVICE_ENABLE; + mPchDeviceEnabling.PciClockRun = PCH_DEVICE_ENABLE; + mPchDeviceEnabling.Display = 1; + mPchDeviceEnabling.Crid = PCH_DEVICE_DISABLE; + mPchDeviceEnabling.SerialIoDma = PCH_DEVICE_ENABLE; + mPchDeviceEnabling.SerialIoI2c0 = PCH_DEVICE_ENABLE; + mPchDeviceEnabling.SerialIoI2c1 = PCH_DEVICE_ENABLE; + mPchDeviceEnabling.SerialIoSpi0 = PCH_DEVICE_ENABLE; + mPchDeviceEnabling.SerialIoSpi1 = PCH_DEVICE_ENABLE; + mPchDeviceEnabling.SerialIoUart0 = PCH_DEVICE_ENABLE; + mPchDeviceEnabling.SerialIoUart1 = PCH_DEVICE_ENABLE; + mPchDeviceEnabling.SerialIoSdio = PCH_DEVICE_ENABLE; + mPchDeviceEnabling.AudioDsp = PCH_DEVICE_DISABLE; + + /// + /// Init USB related setting + /// + InitPchUsbConfig (&mPchUsbConfig); + + /// + /// PCI Express related settings from setup variable + /// + mPchPciExpressConfig.RootPortClockGating = PCH_DEVICE_ENABLE; + mPchPciExpressConfig.TempRootPortBusNumMin = 2; + mPchPciExpressConfig.TempRootPortBusNumMax = 4; + + for (PortIndex = 0; PortIndex < GetPchMaxPciePortNum (); PortIndex++) { + mPchPciExpressConfig.RootPort[PortIndex].Enable = PCH_DEVICE_ENABLE; + mPchPciExpressConfig.RootPort[PortIndex].FunctionNumber = PortIndex; + mPchPciExpressConfig.RootPort[PortIndex].PhysicalSlotNumber = PortIndex; + mPchPciExpressConfig.RootPort[PortIndex].Aspm = 4; + mPchPciExpressConfig.RootPort[PortIndex].SlotImplemented = 1; + mPchPciExpressConfig.RootPort[PortIndex].L1Substates = 3; + + } + mPchPciExpressConfig.RootPort[7].HotPlug = 1; + mPchPciExpressConfig.NumOfDevAspmOverride = sizeof (mDevAspmOverride) / sizeof (PCH_PCIE_DEVICE_ASPM_OVERRIDE); + mPchPciExpressConfig.DevAspmOverride = mDevAspmOverride; + mPchPciExpressConfig.EnableSubDecode = 0; + mPchPciExpressConfig.PchPcieSbdePort = 0; + mPchPciExpressConfig.RootPortFunctionSwapping = 1; + + for (PortIndex = 0; PortIndex < GetPchMaxSataPortNum (); PortIndex++) { + mPchSataConfig.PortSettings[PortIndex].Enable = PCH_DEVICE_ENABLE; + mPchSataConfig.PortSettings[PortIndex].HotPlug = PCH_DEVICE_DISABLE; + mPchSataConfig.PortSettings[PortIndex].InterlockSw = PCH_DEVICE_DISABLE; + mPchSataConfig.PortSettings[PortIndex].External = PCH_DEVICE_DISABLE; + mPchSataConfig.PortSettings[PortIndex].SpinUp = PCH_DEVICE_DISABLE; + mPchSataConfig.PortSettings[PortIndex].SolidStateDrive = PCH_DEVICE_DISABLE; + mPchSataConfig.PortSettings[PortIndex].DevSlp = PCH_DEVICE_DISABLE; + mPchSataConfig.PortSettings[PortIndex].EnableDitoConfig = PCH_DEVICE_DISABLE; + mPchSataConfig.PortSettings[PortIndex].DmVal = 15; + mPchSataConfig.PortSettings[PortIndex].DitoVal = 625; + } + + mPchSataConfig.RaidAlternateId = PCH_DEVICE_DISABLE; + mPchSataConfig.Raid0 = PCH_DEVICE_ENABLE; + mPchSataConfig.Raid1 = PCH_DEVICE_ENABLE; + mPchSataConfig.Raid10 = PCH_DEVICE_ENABLE; + mPchSataConfig.Raid5 = PCH_DEVICE_ENABLE; + mPchSataConfig.Irrt = PCH_DEVICE_ENABLE; + mPchSataConfig.OromUiBanner = PCH_DEVICE_ENABLE; + mPchSataConfig.HddUnlock = PCH_DEVICE_ENABLE; + mPchSataConfig.LedLocate = PCH_DEVICE_ENABLE; + mPchSataConfig.IrrtOnly = PCH_DEVICE_ENABLE; + mPchSataConfig.SmartStorage = PCH_DEVICE_ENABLE; + mPchSataConfig.OromUiDelay = PchSataOromDelay2sec; + mPchSataConfig.TestMode = PCH_DEVICE_DISABLE; + mPchSataConfig.SalpSupport = PCH_DEVICE_ENABLE; + mPchSataConfig.LegacyMode = PCH_DEVICE_DISABLE; + mPchSataConfig.SpeedSupport = PchSataSpeedSupportDefault; + + /// + /// AzaliaConfig + /// + mPchAzaliaConfig.Pme = PCH_DEVICE_DISABLE; + mPchAzaliaConfig.ResetWaitTimer = 300; + mPchAzaliaConfig.DS = 1; + mPchAzaliaConfig.DA = 0; + + /// + /// Reserved SMBus Address + /// + mPchSmbusConfig.NumRsvdSmbusAddresses = 4; + mPchSmbusConfig.RsvdSmbusAddressTable = mSmbusRsvdAddresses; + + /// + /// MiscPm Configuration + /// + mPchMiscPmConfig.PchDeepSxPol = PchDeepSxPolDisable; + mPchMiscPmConfig.WakeConfig.PmeB0S5Dis = PCH_DEVICE_DISABLE; + mPchMiscPmConfig.WakeConfig.WolEnableOverride = PCH_DEVICE_DISABLE; + mPchMiscPmConfig.WakeConfig.Gp27WakeFromDeepSx = PCH_DEVICE_ENABLE; + mPchMiscPmConfig.WakeConfig.PcieWakeFromDeepSx = PCH_DEVICE_DISABLE; + mPchMiscPmConfig.PowerResetStatusClear.MeWakeSts = PCH_DEVICE_ENABLE; + mPchMiscPmConfig.PowerResetStatusClear.MeHrstColdSts = PCH_DEVICE_ENABLE; + mPchMiscPmConfig.PowerResetStatusClear.MeHrstWarmSts = PCH_DEVICE_ENABLE; + + mPchMiscPmConfig.PchSlpS3MinAssert = PchSlpS350ms; + mPchMiscPmConfig.PchSlpS4MinAssert = PchSlpS44s; + mPchMiscPmConfig.PchSlpSusMinAssert = PchSlpSus4s; + mPchMiscPmConfig.PchSlpAMinAssert = PchSlpA2s; + mPchMiscPmConfig.PchPwrCycDur = 4; // 4-5 seconds (PCH default setting) + mPchMiscPmConfig.SlpStrchSusUp = PCH_DEVICE_DISABLE; + mPchMiscPmConfig.SlpLanLowDc = PCH_DEVICE_DISABLE; + + /// + /// Io Apic configuration + /// + mPchIoApicConfig.BdfValid = 1; + mPchIoApicConfig.BusNumber = 0xF0; + mPchIoApicConfig.DeviceNumber = 0x1F; + mPchIoApicConfig.FunctionNumber = 0x00; + mPchIoApicConfig.IoApicEntry24_39 = PCH_DEVICE_ENABLE; + + /// + /// Default Svid Sdid configuration + /// + mPchDefaultSvidSid.SubSystemVendorId = V_PCH_INTEL_VENDOR_ID; + mPchDefaultSvidSid.SubSystemId = V_PCH_DEFAULT_SID; + + /// + /// Thermal configuration - Initialize policy to default values when variable isn't found. + /// + mPchThermalConfig.ThermalAlertEnable.TselLock = PCH_DEVICE_ENABLE; + mPchThermalConfig.ThermalAlertEnable.TscLock = PCH_DEVICE_ENABLE; + mPchThermalConfig.ThermalAlertEnable.TsmicLock = PCH_DEVICE_ENABLE; + mPchThermalConfig.ThermalAlertEnable.PhlcLock = PCH_DEVICE_ENABLE; + mPchThermalConfig.ThermalThrottling.TTLevels.SuggestedSetting = PCH_DEVICE_ENABLE; + mPchThermalConfig.ThermalThrottling.TTLevels.PchCrossThrottling = PCH_DEVICE_ENABLE; + mPchThermalConfig.ThermalThrottling.DmiHaAWC.SuggestedSetting = PCH_DEVICE_ENABLE; + mPchThermalConfig.ThermalThrottling.SataTT.SuggestedSetting = PCH_DEVICE_ENABLE; + mPchThermalConfig.ThermalDeviceEnable = PCH_DEVICE_DISABLE; + /// + /// The value in this field is valid only if it is between 00h and 17Fh. + /// 0x17F is the hottest temperature and 0x000 is the lowest temperature + /// + mPchThermalConfig.PchHotLevel = 0x000; + + /// + /// HEPT Configuration + /// + mPchHpetConfig.BdfValid = 1; + for (Index = 0; Index < PCH_HPET_BDF_MAX; Index++) { + mPchHpetConfig.Hpet[Index].BusNumber = 0xF0; + mPchHpetConfig.Hpet[Index].DeviceNumber = 0x0F; + mPchHpetConfig.Hpet[Index].FunctionNumber = 0x00; + } + /// + /// Initialize Serial IRQ Config + /// + mSerialIrqConfig.SirqEnable = TRUE; + mSerialIrqConfig.StartFramePulse = PchSfpw4Clk; + mSerialIrqConfig.SirqMode = PchContinuousMode; + + /// + /// DMI related settings + /// + mPchDmiConfig.DmiAspm = PCH_DEVICE_ENABLE; + mPchDmiConfig.DmiExtSync = PCH_DEVICE_DISABLE; + mPchDmiConfig.DmiIot = PCH_DEVICE_DISABLE; + + /// + /// Power Optimizer related settings + /// + mPchPwrOptConfig.PchPwrOptDmi = PCH_DEVICE_ENABLE; + mPchPwrOptConfig.PchPwrOptGbe = PCH_DEVICE_ENABLE; + mPchPwrOptConfig.PchPwrOptXhci = PCH_DEVICE_DISABLE; + mPchPwrOptConfig.PchPwrOptEhci = PCH_DEVICE_DISABLE; + mPchPwrOptConfig.PchPwrOptSata = PCH_DEVICE_ENABLE; + mPchPwrOptConfig.MemCloseStateEn = PCH_DEVICE_ENABLE; + mPchPwrOptConfig.InternalObffEn = PCH_DEVICE_ENABLE; + mPchPwrOptConfig.ExternalObffEn = PCH_DEVICE_DISABLE; // De-feature OBFF from LPT-H/LPT-LP. + mPchPwrOptConfig.NumOfDevLtrOverride = 0; + mPchPwrOptConfig.DevLtrOverride = NULL; + for (PortIndex = 0; PortIndex < GetPchMaxPciePortNum (); PortIndex++) { + mPchPwrOptConfig.PchPwrOptPcie[PortIndex].LtrEnable = PCH_DEVICE_ENABLE; + // + // De-feature OBFF from LPT-H/LPT-LP. + // Doesn't enable Obff policy anymore. + // + mPchPwrOptConfig.PchPwrOptPcie[PortIndex].ObffEnable = PCH_DEVICE_DISABLE; + } + mPchPwrOptConfig.LegacyDmaDisable = PCH_DEVICE_DISABLE; + for (PortIndex = 0; PortIndex < GetPchMaxPciePortNum (); PortIndex++) { + if (PchSeries == PchLp) { + mPchPwrOptConfig.PchPwrOptPcie[PortIndex].LtrMaxSnoopLatency = 0x1003; + mPchPwrOptConfig.PchPwrOptPcie[PortIndex].LtrMaxNoSnoopLatency = 0x1003; + } + if (PchSeries == PchH) { + mPchPwrOptConfig.PchPwrOptPcie[PortIndex].LtrMaxSnoopLatency = 0x0846; + mPchPwrOptConfig.PchPwrOptPcie[PortIndex].LtrMaxNoSnoopLatency = 0x0846; + } + mPchPwrOptConfig.PchPwrOptPcie[PortIndex].LtrConfigLock = PCH_DEVICE_ENABLE; + mPchPwrOptConfig.PchPwrOptPcie[PortIndex].SnoopLatencyOverrideMode = 2; + mPchPwrOptConfig.PchPwrOptPcie[PortIndex].SnoopLatencyOverrideMultiplier = 2; + mPchPwrOptConfig.PchPwrOptPcie[PortIndex].SnoopLatencyOverrideValue = 60; + mPchPwrOptConfig.PchPwrOptPcie[PortIndex].NonSnoopLatencyOverrideMode = 2; + mPchPwrOptConfig.PchPwrOptPcie[PortIndex].NonSnoopLatencyOverrideMultiplier = 2; + mPchPwrOptConfig.PchPwrOptPcie[PortIndex].NonSnoopLatencyOverrideValue = 60; + } + + /// + /// Misc. Config + /// + /// FviSmbiosType is the SMBIOS OEM type (0x80 to 0xFF) defined in SMBIOS Type 14 - Group + /// Associations structure - item type. FVI structure uses it as SMBIOS OEM type to provide + /// version information. The default value is type 221. + /// + mPchMiscConfig.FviSmbiosType = 0xDD; + + /// + /// DCI (Direct Connect Interface) Configuration + /// + mPchMiscConfig.DciEn = PCH_DEVICE_DISABLE; + + /// + /// Audio Dsp Configuration + /// + mAudioDspConfig.AudioDspD3PowerGating = PCH_DEVICE_ENABLE; + mAudioDspConfig.AudioDspAcpiMode = 1; //1: ACPI mode, 0: PCI mode + mAudioDspConfig.AudioDspAcpiInterruptMode = 1; //1: ACPI mode, 0: PCI mode + mAudioDspConfig.AudioDspBluetoothSupport = PCH_DEVICE_DISABLE; // Bluetooth SCO disabled + + /// + /// Serial IO Configuration + /// + mSerialIoConfig.SerialIoMode = PchSerialIoIsAcpi; + switch(PchStepping()) { + default: + mSerialIoConfig.SerialIoInterruptMode = PchSerialIoIsAcpi; + break; + } + mSerialIoConfig.Ddr50Support = PCH_DEVICE_DISABLE; + + mSerialIoConfig.I2c0VoltageSelect = PchSerialIoIs18V; + mSerialIoConfig.I2c1VoltageSelect = PchSerialIoIs33V; + + + /// + /// Update policy by platform setting + /// + UpdateDxePchPlatformPolicy (&mPchPolicyData); + +#ifdef USB_PRECONDITION_ENABLE_FLAG + /// + /// Update Precondition option for S4 resume. + /// Skip Precondition for S4 resume in case this boot may not connect BIOS USB driver. + /// If BIOS USB driver will be connected always for S4, then disable below update. + /// To keep consistency during boot, must enabled or disabled below function in both PEI and DXE + /// PlatformPolicyInit driver. + /// + if (mPchUsbConfig.UsbPrecondition == TRUE) { + if (GetBootModeHob () == BOOT_ON_S4_RESUME) { + mPchUsbConfig.UsbPrecondition = FALSE; + DEBUG ((EFI_D_INFO, "BootMode is BOOT_ON_S4_RESUME, disable Precondition\n")); + } + } +#endif // USB_PRECONDITION_ENABLE_FLAG + Handle = NULL; + Status = gBS->InstallMultipleProtocolInterfaces ( + &Handle, + &gDxePchPlatformPolicyProtocolGuid, + &mPchPolicyData, + NULL + ); + ASSERT_EFI_ERROR (Status); + + return Status; + +} diff --git a/ReferenceCode/Chipset/LynxPoint/SampleCode/PchPolicyInit/Dxe/PchPolicyInitDxe.dxs b/ReferenceCode/Chipset/LynxPoint/SampleCode/PchPolicyInit/Dxe/PchPolicyInitDxe.dxs new file mode 100644 index 0000000..0140fb2 --- /dev/null +++ b/ReferenceCode/Chipset/LynxPoint/SampleCode/PchPolicyInit/Dxe/PchPolicyInitDxe.dxs @@ -0,0 +1,44 @@ +/** @file + Dependency expression source file. + +@copyright + Copyright (c) 2009 - 2012 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement + +**/ + + +// +// Common for R8 and R9 codebase +// +#include "AutoGen.h" +#include "PeimDepex.h" + +// +// BUILD_WITH_GLUELIB and BUILD_WITH_EDKII_GLUE_LIB are both "defined" in R8 codebase; +// BUILD_WITH_EDKII_GLUE_LIB is defined in Edk-Dev-Snapshot-20070228 and later version +// BUILD_WITH_GLUELIB and BUILD_WITH_EDKII_GLUE_LIB are "not defined" in R9 codebase. +// +#if defined (BUILD_WITH_GLUELIB) || defined (BUILD_WITH_EDKII_GLUE_LIB) +#include "EfiDepex.h" +#endif +#include EFI_ARCH_PROTOCOL_DEFINITION (Variable) +#include EFI_PROTOCOL_DEFINITION (PlatformInfo) +#include EFI_PROTOCOL_DEFINITION (CpuIo) + +DEPENDENCY_START + EFI_VARIABLE_ARCH_PROTOCOL_GUID AND + PLATFORM_INFO_PROTOCOL_GUID AND + EFI_CPU_IO_PROTOCOL_GUID +DEPENDENCY_END
\ No newline at end of file diff --git a/ReferenceCode/Chipset/LynxPoint/SampleCode/PchPolicyInit/Dxe/PchPolicyInitDxe.h b/ReferenceCode/Chipset/LynxPoint/SampleCode/PchPolicyInit/Dxe/PchPolicyInitDxe.h new file mode 100644 index 0000000..ae0cbae --- /dev/null +++ b/ReferenceCode/Chipset/LynxPoint/SampleCode/PchPolicyInit/Dxe/PchPolicyInitDxe.h @@ -0,0 +1,56 @@ +/** @file + Header file for the PchPolicyInitDxe Driver. + +@copyright + Copyright (c) 2009 - 2012 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement +**/ +#ifndef _PCH_PLATFORM_POLICY_DXE_H_ +#define _PCH_PLATFORM_POLICY_DXE_H_ + +// +// External include files do NOT need to be explicitly specified in real EDKII +// environment +// +#if !defined(EDK_RELEASE_VERSION) || (EDK_RELEASE_VERSION < 0x00020000) +#include "EdkIIGlueDxe.h" +#include EFI_PROTOCOL_PRODUCER (PchPlatformPolicy) +#include "PchAccess.h" +#include "PchPlatformPolicyUpdateDxeLib.h" +#include "PchPlatformLib.h" +#endif + +// +// Functions +// + +/** + Initilize Intel PCH DXE Platform Policy + + @param[in] ImageHandle Image handle of this driver. + @param[in, out] SystemTable Global system service table. + + @retval EFI_SUCCESS Initialization complete. + @exception EFI_UNSUPPORTED The chipset is unsupported by this driver. + @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver. + @retval EFI_DEVICE_ERROR Device error, driver exits abnormally. +**/ +EFI_STATUS +EFIAPI +PchPolicyInitDxeEntryPoint ( + IN EFI_HANDLE ImageHandle, + IN OUT EFI_SYSTEM_TABLE *SystemTable + ); + +#endif diff --git a/ReferenceCode/Chipset/LynxPoint/SampleCode/PchPolicyInit/Dxe/PchPolicyInitDxe.inf b/ReferenceCode/Chipset/LynxPoint/SampleCode/PchPolicyInit/Dxe/PchPolicyInitDxe.inf new file mode 100644 index 0000000..3b883ab --- /dev/null +++ b/ReferenceCode/Chipset/LynxPoint/SampleCode/PchPolicyInit/Dxe/PchPolicyInitDxe.inf @@ -0,0 +1,82 @@ +## @file +# Component description file for the PchPolicyInitDxe DXE driver. +# +#@copyright +# Copyright (c) 2009 - 2013 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# This file contains a 'Sample Driver' and is licensed as such +# under the terms of your license agreement with Intel or your +# vendor. This file may be modified by the user, subject to +# the additional terms of the license agreement +# + +[defines] +BASE_NAME = PchPolicyInitDxe +FILE_GUID = 3BC42C6D-ABEC-41ba-8CCB-D8E0EF1CEF85 +COMPONENT_TYPE = BS_DRIVER + +[sources.common] + PchPolicyInitDxe.h + PchPolicyInitDxe.c + ../Common/PchPolicyInitCommon.c + ../Common/PchPolicyInitCommon.h +# +# Edk II Glue Driver Entry Point +# + EdkIIGlueDxeDriverEntryPoint.c + +[includes.common] + . + $(EFI_SOURCE) + $(EDK_SOURCE)/Foundation + $(EDK_SOURCE)/Foundation/Include + $(EDK_SOURCE)/Foundation/Efi + $(EDK_SOURCE)/Foundation/Efi/Include + $(EDK_SOURCE)/Foundation/Framework + $(EDK_SOURCE)/Foundation/Framework/Include + $(EDK_SOURCE)/Foundation/Library/EdkIIGlueLib/Include + $(EDK_SOURCE)/Foundation/Library/EdkIIGlueLib/Include/Pcd + $(EDK_SOURCE)/Foundation/Library/EdkIIGlueLib/Include/Library + $(EDK_SOURCE)/Foundation/Include/IndustryStandard + $(EDK_SOURCE)/Foundation/Library/Dxe/Include + $(EDK_SOURCE)/Foundation/Core/Dxe + $(EDK_SOURCE)/Foundation/Cpu/Pentium/Include + $(EFI_SOURCE)/$(PROJECT_PCH_ROOT) + $(EFI_SOURCE)/$(PROJECT_PCH_ROOT)/Include + $(EFI_SOURCE)/$(PROJECT_PCH_ROOT)/Include/Library + $(EFI_SOURCE)/$(PROJECT_PCH_ROOT)/Protocol/PchPlatformPolicy + $(PLATFORM_ECP_PACKAGE)/Include + +[libraries.common] + EdkIIGlueDxeReportStatusCodeLib + EdkIIGlueDxeDebugLibReportStatusCode + EdkFrameworkProtocolLib + EdkIIGlueDxeHobLib + EdkProtocolLib + $(PROJECT_PCH_FAMILY)ProtocolLib + EdkIIGlueUefiBootServicesTableLib + EdkIIGlueUefiRuntimeServicesTableLib + PlatformPolicyUpdateDxeLib + EdkIIGlueDxeServicesTableLib + PchPlatformLib + +[nmake.common] + IMAGE_ENTRY_POINT = _ModuleEntryPoint + DPX_SOURCE = PchPolicyInitDxe.dxs +# +# Module Entry Point +# + C_FLAGS = $(C_FLAGS) -D __EDKII_GLUE_MODULE_ENTRY_POINT__=PchPolicyInitDxeEntryPoint + C_FLAGS = $(C_FLAGS) -D __EDKII_GLUE_DXE_REPORT_STATUS_CODE_LIB__ \ + -D __EDKII_GLUE_DXE_DEBUG_LIB_REPORT_STATUS_CODE__ \ + -D __EDKII_GLUE_UEFI_BOOT_SERVICES_TABLE_LIB__ \ + -D __EDKII_GLUE_UEFI_RUNTIME_SERVICES_TABLE_LIB__ \ + -D __EDKII_GLUE_DXE_SERVICES_TABLE_LIB__ \ + -D __EDKII_GLUE_DXE_HOB_LIB__ diff --git a/ReferenceCode/Chipset/LynxPoint/SampleCode/PchPolicyInit/Pei/PchPolicyInitPei.c b/ReferenceCode/Chipset/LynxPoint/SampleCode/PchPolicyInit/Pei/PchPolicyInitPei.c new file mode 100644 index 0000000..08e0cf7 --- /dev/null +++ b/ReferenceCode/Chipset/LynxPoint/SampleCode/PchPolicyInit/Pei/PchPolicyInitPei.c @@ -0,0 +1,250 @@ +/** @file + This file is SampleCode for Intel PCH PEI Platform Policy initialzation. + +@copyright + Copyright (c) 2009 - 2013 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement + +**/ +#include "PchPolicyInitPei.h" +#include "..\Common\PchPolicyInitCommon.h" +#ifdef RAPID_START_FLAG +#include "RapidStartCommonLib.h" +#endif + +/** + This PEIM performs PCH PEI Platform Policy initialzation. + + @param[in] FfsHeader Pointer to Firmware File System file header. + @param[in] PeiServices General purpose services available to every PEIM. + + @retval EFI_SUCCESS The PPI is installed and initialized. + @retval EFI ERRORS The PPI is not successfully installed. + @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver +**/ +EFI_STATUS +EFIAPI +PchPolicyInitPeiEntryPoint ( + IN EFI_FFS_FILE_HEADER *FfsHeader, + IN EFI_PEI_SERVICES **PeiServices + ) +{ + EFI_STATUS Status; + EFI_PEI_PPI_DESCRIPTOR *PchPlatformPolicyPpiDesc; + PCH_PLATFORM_POLICY_PPI *PchPlatformPolicyPpi; + PCH_GBE_CONFIG *GbeConfig; + PCH_THERMAL_MANAGEMENT *ThermalMgmt; + PCH_MEMORY_THROTTLING *MemoryThrottling; + PCH_HPET_CONFIG *HpetConfig; + PCH_SATA_CONTROL *SataConfig; + PCH_SATA_TRACE_CONFIG *SataTraceConfig; + PCH_PCIE_CONFIG *PcieConfig; + PCH_IOAPIC_CONFIG *IoApicConfig; + PCH_PLATFORM_DATA *PlatformData; + PCH_USB_CONFIG *UsbConfig; +#ifdef USB_PRECONDITION_ENABLE_FLAG + EFI_BOOT_MODE BootMode; +#endif // USB_PRECONDITION_ENABLE_FLAG + UINT8 PortIndex; + + PchPlatformPolicyPpiDesc = (EFI_PEI_PPI_DESCRIPTOR *) AllocateZeroPool (sizeof (EFI_PEI_PPI_DESCRIPTOR)); + ASSERT (PchPlatformPolicyPpiDesc != NULL); + if (PchPlatformPolicyPpiDesc == NULL) { + return EFI_OUT_OF_RESOURCES; + } + + PchPlatformPolicyPpi = (PCH_PLATFORM_POLICY_PPI *) AllocateZeroPool (sizeof (PCH_PLATFORM_POLICY_PPI)); + ASSERT (PchPlatformPolicyPpi != NULL); + if (PchPlatformPolicyPpi == NULL) { + return EFI_OUT_OF_RESOURCES; + } + + GbeConfig = (PCH_GBE_CONFIG *) AllocateZeroPool (sizeof (PCH_GBE_CONFIG)); + ASSERT (GbeConfig != NULL); + if (GbeConfig == NULL) { + return EFI_OUT_OF_RESOURCES; + } + + ThermalMgmt = (PCH_THERMAL_MANAGEMENT *) AllocateZeroPool (sizeof (PCH_THERMAL_MANAGEMENT)); + ASSERT (ThermalMgmt != NULL); + if (ThermalMgmt == NULL) { + return EFI_OUT_OF_RESOURCES; + } + + MemoryThrottling = (PCH_MEMORY_THROTTLING *) AllocateZeroPool (sizeof (PCH_MEMORY_THROTTLING)); + ASSERT (MemoryThrottling != NULL); + if (MemoryThrottling == NULL) { + return EFI_OUT_OF_RESOURCES; + } + + HpetConfig = (PCH_HPET_CONFIG *) AllocateZeroPool (sizeof (PCH_HPET_CONFIG)); + ASSERT (HpetConfig != NULL); + if (HpetConfig == NULL) { + return EFI_OUT_OF_RESOURCES; + } + + SataConfig = (PCH_SATA_CONTROL *) AllocateZeroPool (sizeof (PCH_SATA_CONTROL)); + ASSERT (SataConfig != NULL); + if (SataConfig == NULL) { + return EFI_OUT_OF_RESOURCES; + } + + SataTraceConfig = (PCH_SATA_TRACE_CONFIG *) AllocateZeroPool (sizeof (PCH_SATA_TRACE_CONFIG)); + ASSERT (SataTraceConfig != NULL); + if (SataTraceConfig == NULL) { + return EFI_OUT_OF_RESOURCES; + } + + PcieConfig = (PCH_PCIE_CONFIG *) AllocateZeroPool (sizeof (PCH_PCIE_CONFIG)); + ASSERT (PcieConfig != NULL); + if (PcieConfig == NULL) { + return EFI_OUT_OF_RESOURCES; + } + + IoApicConfig = (PCH_IOAPIC_CONFIG *) AllocateZeroPool (sizeof (PCH_IOAPIC_CONFIG)); + ASSERT (IoApicConfig != NULL); + if (IoApicConfig == NULL) { + return EFI_OUT_OF_RESOURCES; + } + + PlatformData = (PCH_PLATFORM_DATA *) AllocateZeroPool (sizeof (PCH_PLATFORM_DATA)); + ASSERT (PlatformData != NULL); + if (PlatformData == NULL) { + return EFI_OUT_OF_RESOURCES; + } + + UsbConfig = (PCH_USB_CONFIG *) AllocateZeroPool (sizeof (PCH_USB_CONFIG)); + ASSERT (UsbConfig != NULL); + if (UsbConfig == NULL) { + return EFI_OUT_OF_RESOURCES; + } + PchPlatformPolicyPpi->Revision = PCH_PLATFORM_POLICY_PPI_REVISION_4; + PchPlatformPolicyPpi->BusNumber = 0; + PchPlatformPolicyPpi->Rcba = PCH_LPC_RCBA_BASE_ADDRESS; + PchPlatformPolicyPpi->PmBase = PCH_LPC_ACPI_BASE_ADDRESS; + PchPlatformPolicyPpi->GpioBase = PCH_LPC_GPIO_BASE_ADDRESS; + PchPlatformPolicyPpi->Port80Route = 0; + + PchPlatformPolicyPpi->GbeConfig = GbeConfig; + PchPlatformPolicyPpi->ThermalMgmt = ThermalMgmt; + PchPlatformPolicyPpi->HpetConfig = HpetConfig; + PchPlatformPolicyPpi->SataConfig = SataConfig; + PchPlatformPolicyPpi->PcieConfig = PcieConfig; + PchPlatformPolicyPpi->IoApicConfig = IoApicConfig; + PchPlatformPolicyPpi->PlatformData = PlatformData; + PchPlatformPolicyPpi->UsbConfig = UsbConfig; + + GbeConfig->EnableGbe = 1; + ThermalMgmt->MemoryThrottling = MemoryThrottling; + MemoryThrottling->Enable = PCH_DEVICE_DISABLE; + MemoryThrottling->TsGpioPinSetting[TsGpioC].PmsyncEnable = PCH_DEVICE_ENABLE; + MemoryThrottling->TsGpioPinSetting[TsGpioD].PmsyncEnable = PCH_DEVICE_ENABLE; + MemoryThrottling->TsGpioPinSetting[TsGpioC].C0TransmitEnable = PCH_DEVICE_ENABLE; + MemoryThrottling->TsGpioPinSetting[TsGpioD].C0TransmitEnable = PCH_DEVICE_ENABLE; + MemoryThrottling->TsGpioPinSetting[TsGpioC].PinSelection = 1; + MemoryThrottling->TsGpioPinSetting[TsGpioD].PinSelection = 0; + + HpetConfig->Enable = 1; + HpetConfig->Base = PCH_HPET_BASE_ADDRESS; + + SataConfig->SataMode = PchSataModeAhci; + SataConfig->SataTraceConfig = SataTraceConfig; + + SataTraceConfig->TestMode = PCH_DEVICE_DISABLE; + for( PortIndex = 0; PortIndex < 6; PortIndex++ ) { + SataTraceConfig->PortRxEq[PortIndex].GenSpeed[0].Enable = PCH_DEVICE_DISABLE; + SataTraceConfig->PortRxEq[PortIndex].GenSpeed[1].Enable = PCH_DEVICE_DISABLE; + SataTraceConfig->PortRxEq[PortIndex].GenSpeed[2].Enable = PCH_DEVICE_DISABLE; + SataTraceConfig->PortRxEq[PortIndex].GenSpeed[0].RxEq = 0x0; + SataTraceConfig->PortRxEq[PortIndex].GenSpeed[1].RxEq = 0x0; + SataTraceConfig->PortRxEq[PortIndex].GenSpeed[2].RxEq = 0x0; + } + + PcieConfig->PcieSpeed[0] = PchPcieAuto; + PcieConfig->PcieSpeed[1] = PchPcieAuto; + PcieConfig->PcieSpeed[2] = PchPcieAuto; + PcieConfig->PcieSpeed[3] = PchPcieAuto; + PcieConfig->PcieSpeed[4] = PchPcieAuto; + PcieConfig->PcieSpeed[5] = PchPcieAuto; + PcieConfig->PcieSpeed[6] = PchPcieAuto; + PcieConfig->PcieSpeed[7] = PchPcieAuto; + + IoApicConfig->IoApicId = 0x02; + IoApicConfig->ApicRangeSelect = 0x00; + IoApicConfig->IoApicEntry24_39 = PCH_DEVICE_ENABLE; + + PlatformData->EcPresent = 0; + /// + /// PlatformData->SmmBwp value directly depends on the value of CpuConfig->Pfat + /// (found in CpuPolicyInitPei.c file) + /// If CpuConfig->Pfat is set to 1 (enabled) then + /// PlatformData->SmmBwp has to be set to 1 (enabled) + /// This is a PFAT Security requirement that needs to be addressed + /// If CpuConfig->Pfat is set to 0 (disabled) then + /// PlatformData->SmmBwp value don't care, it can be set to either + /// 1 (enabled) or 0 (disabled) based on customer implementation + /// + PlatformData->SmmBwp = 0; + + /// + /// Temporary Memory Base Address for PCI devices to be used to initialize MMIO registers. + /// Minimum size is 64KB bytes. + /// + PlatformData->TempMemBaseAddr = PCH_TEMP_MEM_BASE_ADDRESS; + + /// + /// Init USB related setting + /// + InitPchUsbConfig (UsbConfig); + + PchPlatformPolicyPpiDesc->Flags = EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST; + PchPlatformPolicyPpiDesc->Guid = &gPchPlatformPolicyPpiGuid; + + UpdatePeiPchPlatformPolicy (PeiServices, PchPlatformPolicyPpi); +#ifdef RAPID_START_FLAG + if (RapidStartResumeCheck () == TRUE) { + /// + /// This is RapidStart resume, skip the UsbPrecondition feature in PEI phase + /// + PchPlatformPolicyPpi->UsbConfig->UsbPrecondition = 0; + } +#endif + + + PchPlatformPolicyPpiDesc->Ppi = PchPlatformPolicyPpi; +#ifdef USB_PRECONDITION_ENABLE_FLAG + /// + /// Update Precondition option for S4 resume. + /// Skip Precondition for S4 resume in case this boot may not connect BIOS USB driver. + /// If BIOS USB driver will be connected always for S4, then disable below update. + /// To keep consistency during boot, must enabled or disabled below function in both PEI and DXE + /// PlatformPolicyInit driver. + /// + if (UsbConfig->UsbPrecondition == TRUE) { + (*PeiServices)->GetBootMode (PeiServices, &BootMode); + if (BootMode == BOOT_ON_S4_RESUME) { + UsbConfig->UsbPrecondition = FALSE; + DEBUG ((EFI_D_INFO, "BootMode is BOOT_ON_S4_RESUME, disable Precondition\n")); + } + } +#endif // USB_PRECONDITION_ENABLE_FLAG + + /// + /// Install PCH Platform Policy PPI + /// + Status = (**PeiServices).InstallPpi (PeiServices, PchPlatformPolicyPpiDesc); + ASSERT_EFI_ERROR (Status); + + return Status; +} diff --git a/ReferenceCode/Chipset/LynxPoint/SampleCode/PchPolicyInit/Pei/PchPolicyInitPei.dxs b/ReferenceCode/Chipset/LynxPoint/SampleCode/PchPolicyInit/Pei/PchPolicyInitPei.dxs new file mode 100644 index 0000000..806a8d6 --- /dev/null +++ b/ReferenceCode/Chipset/LynxPoint/SampleCode/PchPolicyInit/Pei/PchPolicyInitPei.dxs @@ -0,0 +1,40 @@ +/** @file + Dependency expression source file. + +@copyright + Copyright (c) 2010 - 2012 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement + +**/ + + +// +// Common for R8 and R9 codebase +// +#include "AutoGen.h" +#include "PeimDepex.h" + +// +// BUILD_WITH_GLUELIB and BUILD_WITH_EDKII_GLUE_LIB are both "defined" in R8 codebase; +// BUILD_WITH_EDKII_GLUE_LIB is defined in Edk-Dev-Snapshot-20070228 and later version +// BUILD_WITH_GLUELIB and BUILD_WITH_EDKII_GLUE_LIB are "not defined" in R9 codebase. +// +#if defined (BUILD_WITH_GLUELIB) || defined (BUILD_WITH_EDKII_GLUE_LIB) +#include "EfiDepex.h" +#include EFI_PPI_DEPENDENCY (Variable) +#endif + +DEPENDENCY_START + PEI_READ_ONLY_VARIABLE_ACCESS_PPI_GUID +DEPENDENCY_END diff --git a/ReferenceCode/Chipset/LynxPoint/SampleCode/PchPolicyInit/Pei/PchPolicyInitPei.h b/ReferenceCode/Chipset/LynxPoint/SampleCode/PchPolicyInit/Pei/PchPolicyInitPei.h new file mode 100644 index 0000000..3d155b3 --- /dev/null +++ b/ReferenceCode/Chipset/LynxPoint/SampleCode/PchPolicyInit/Pei/PchPolicyInitPei.h @@ -0,0 +1,60 @@ +/** @file + Header file for the PchPeiPolicy PEIM. + +@copyright + Copyright (c) 2009 - 2012 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement +**/ +#ifndef _PCH_POLICY_INIT_PEI_H_ +#define _PCH_POLICY_INIT_PEI_H_ + +// +// External include files do NOT need to be explicitly specified in real EDKII +// environment +// +#if !defined(EDK_RELEASE_VERSION) || (EDK_RELEASE_VERSION < 0x00020000) +#include "EdkIIGluePeim.h" +#include EFI_PPI_PRODUCER (PchPlatformPolicy) +#include "PchAccess.h" +#include "PchPlatformPolicyUpdatePeiLib.h" +#endif + +#define PCH_LPC_RCBA_BASE_ADDRESS 0xFED1C000 +#define PCH_LPC_ACPI_BASE_ADDRESS 0x1800 +#define PCH_LPC_GPIO_BASE_ADDRESS 0x800 + +#define PCH_TEMP_MEM_BASE_ADDRESS 0xDFFF0000 +#define PCH_HPET_BASE_ADDRESS 0xFED00000 + +// +// Functions +// + +/** + This PEIM performs PCH PEI Platform Policy initialzation. + + @param[in] FfsHeader Pointer to Firmware File System file header. + @param[in] PeiServices General purpose services available to every PEIM. + + @retval EFI_SUCCESS The PPI is installed and initialized. + @retval EFI ERRORS The PPI is not successfully installed. + @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver +**/ +EFI_STATUS +EFIAPI +PchPolicyInitPeiEntryPoint ( + IN EFI_FFS_FILE_HEADER *FfsHeader, + IN EFI_PEI_SERVICES **PeiServices + ); +#endif diff --git a/ReferenceCode/Chipset/LynxPoint/SampleCode/PchPolicyInit/Pei/PchPolicyInitPei.inf b/ReferenceCode/Chipset/LynxPoint/SampleCode/PchPolicyInit/Pei/PchPolicyInitPei.inf new file mode 100644 index 0000000..37ab29d --- /dev/null +++ b/ReferenceCode/Chipset/LynxPoint/SampleCode/PchPolicyInit/Pei/PchPolicyInitPei.inf @@ -0,0 +1,87 @@ +## @file +# Component description file for the PchPolicyInitPei PEIM. +# +#@copyright +# Copyright (c) 2009 - 2012 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# This file contains a 'Sample Driver' and is licensed as such +# under the terms of your license agreement with Intel or your +# vendor. This file may be modified by the user, subject to +# the additional terms of the license agreement +# + +[defines] +BASE_NAME = PchPolicyInitPei +FILE_GUID = 20596BCC-EF0D-4772-AB71-C5102620A013 +COMPONENT_TYPE = PE32_PEIM + +[sources.common] + PchPolicyInitPei.h + PchPolicyInitPei.c + ../Common/PchPolicyInitCommon.c + ../Common/PchPolicyInitCommon.h +# +# Edk II Glue Driver Entry Point +# + EdkIIGluePeimEntryPoint.c + +[includes.common] + . + $(EDK_SOURCE)/Foundation/Efi + $(EDK_SOURCE)/Foundation/Include + $(EDK_SOURCE)/Foundation/Efi/Include + $(EDK_SOURCE)/Foundation/Framework/Include + $(EFI_SOURCE)/$(PROJECT_PCH_ROOT) + $(EFI_SOURCE)/$(PROJECT_PCH_ROOT)/Include + $(EFI_SOURCE)/$(PROJECT_PCH_ROOT)/Include/Library + $(EFI_SOURCE)/$(PROJECT_PCH_ROOT)/Ppi/PchPlatformPolicy + $(EFI_SOURCE)/$(PROJECT_RAPID_START_ROOT) + $(EFI_SOURCE)/$(PROJECT_RAPID_START_ROOT)/Include + $(EFI_SOURCE)/$(PROJECT_RAPID_START_ROOT)/Samplecode/Library/RapidStartCommonLib +# +# EDK II Glue Library utilizes some standard headers from EDK +# + $(EFI_SOURCE) + $(EDK_SOURCE)/Foundation + $(EDK_SOURCE)/Foundation/Framework + $(EDK_SOURCE)/Foundation/Include/IndustryStandard + $(EDK_SOURCE)/Foundation/Core/Dxe + $(EDK_SOURCE)/Foundation/Include/Pei + $(EDK_SOURCE)/Foundation/Library/Pei/Include + $(EDK_SOURCE)/Foundation/Library/Dxe/Include + $(EDK_SOURCE)/Foundation/Library/EdkIIGlueLib/Include + $(PLATFORM_ECP_PACKAGE)/Include + +[libraries.common] + $(PROJECT_PCH_FAMILY)PpiLib + EdkFrameworkPpiLib + EdkIIGlueBaseIoLibIntrinsic + EdkIIGlueBaseMemoryLib + EdkIIGluePeiDebugLibReportStatusCode + EdkIIGluePeiReportStatusCodeLib + EdkIIGluePeiServicesLib + EdkIIGluePeiMemoryAllocationLib + EdkPpiLib + PlatformPolicyUpdatePeiLib + RapidStartCommonLib + +[nmake.common] + IMAGE_ENTRY_POINT = _ModuleEntryPoint + DPX_SOURCE = PchPolicyInitPei.dxs +# +# Module Entry Point +# + C_FLAGS = $(C_FLAGS) -D __EDKII_GLUE_MODULE_ENTRY_POINT__=PchPolicyInitPeiEntryPoint + C_FLAGS = $(C_FLAGS) -D __EDKII_GLUE_BASE_IO_LIB_INTRINSIC__ \ + -D __EDKII_GLUE_BASE_MEMORY_LIB__ \ + -D __EDKII_GLUE_PEI_DEBUG_LIB_REPORT_STATUS_CODE__ \ + -D __EDKII_GLUE_PEI_REPORT_STATUS_CODE_LIB__ \ + -D __EDKII_GLUE_PEI_SERVICES_LIB__ \ + -D __EDKII_GLUE_PEI_MEMORY_ALLOCATION_LIB__ |