diff options
Diffstat (limited to 'ReferenceCode/Chipset/SystemAgent/AcpiTables/SaSsdt')
13 files changed, 4243 insertions, 0 deletions
diff --git a/ReferenceCode/Chipset/SystemAgent/AcpiTables/SaSsdt/INTELGFX.ASL b/ReferenceCode/Chipset/SystemAgent/AcpiTables/SaSsdt/INTELGFX.ASL new file mode 100644 index 0000000..153afd5 --- /dev/null +++ b/ReferenceCode/Chipset/SystemAgent/AcpiTables/SaSsdt/INTELGFX.ASL @@ -0,0 +1,1731 @@ +/*++ + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +--*/ + +/*++ + +Copyright (c) 1999 - 2013 Intel Corporation. All rights reserved +This software and associated documentation (if any) is furnished +under a license and may only be used or copied in accordance +with the terms of the license. Except as permitted by such +license, no part of this software or documentation may be +reproduced, stored in a retrieval system, or transmitted in any +form or by any means without the express written consent of +Intel Corporation. + + +Module Name: + + INTELGFX.ASL + +Abstract: + + IGD OpRegion/Software ACPI Reference Code. + +--*/ + + + External(\_SB.PCI0.GFX0.IDAB, MethodObj) + External(\_SB.PCI0.GFX0.HWID, MethodObj) + External(\ECST, MethodObj) + External(HDOS, MethodObj) +#if !defined(ASL_Remove_SaSsdt_Data_To_Dsdt) || (ASL_Remove_SaSsdt_Data_To_Dsdt == 0) + External(\ECON, IntObj) + External(\PNHM, IntObj) +#endif // AMI_OVERRIDE + External(OSYS, IntObj) + External(SCIS) + External(\GUAM, MethodObj) + External(DSEN) + External(BID) + External(BHB) + External(BFS2) + External(BFS3) + External(BFS4) + + + External(S0ID) + External(\ADBG, MethodObj) + External(\_SB.PEPD, DeviceObj) + + Method(_DEP){ + ADBG("GFX0 DEP Call") + If(LEqual(S0ID, 1)){ + ADBG("GFX0 DEP") + Return(Package() {\_SB.PEPD}) + }Else{ + ADBG("GFX0 DEP NULL") + Return(Package(){}) + } + } + + // Enable/Disable Output Switching. In WIN2K/WINXP, _DOS = 0 will + // get called during initialization to prepare for an ACPI Display + // Switch Event. During an ACPI Display Switch, the OS will call + // _DOS = 2 immediately after a Notify=0x80 to temporarily disable + // all Display Switching. After ACPI Display Switching is complete, + // the OS will call _DOS = 0 to re-enable ACPI Display Switching. + + Method(_DOS,1) + { + // Store Display Switching and LCD brightness BIOS control bit + Store(And(Arg0,7),DSEN) + + If(LEqual(And(Arg0, 0x3), 0)) // If _DOS[1:0]=0 + { + If(CondRefOf(HDOS)) + { + HDOS() + } + } + } + + // Enumerate the Display Environment. This method will return + // valid addresses for all display device encoders present in the + // system. The Miniport Driver will reject the addresses for every + // encoder that does not have an attached display device. After + // enumeration is complete, the OS will call the _DGS methods + // during a display switch only for the addresses accepted by the + // Miniport Driver. For hot-insertion and removal of display + // devices, a re-enumeration notification will be required so the + // address of the newly present display device will be accepted by + // the Miniport Driver. + + Method(_DOD,0) + { + + If (CondRefOf(IDAB)) + { + IDAB() + } + Else + { + Store(0, NDID) + + If(LNotEqual(DIDL, Zero)) + { + Store(SDDL(DIDL),DID1) + } + If(LNotEqual(DDL2, Zero)) + { + Store(SDDL(DDL2),DID2) + } + If(LNotEqual(DDL3, Zero)) + { + Store(SDDL(DDL3),DID3) + } + If(LNotEqual(DDL4, Zero)) + { + Store(SDDL(DDL4),DID4) + } + If(LNotEqual(DDL5, Zero)) + { + Store(SDDL(DDL5),DID5) + } + If(LNotEqual(DDL6, Zero)) + { + Store(SDDL(DDL6),DID6) + } + If(LNotEqual(DDL7, Zero)) + { + Store(SDDL(DDL7),DID7) + } + If(LNotEqual(DDL8, Zero)) + { + Store(SDDL(DDL8),DID8) + } + If(LNotEqual(DDL9, Zero)) + { + Store(SDDL(DDL9),DID9) + } + If(LNotEqual(DD10, Zero)) + { + Store(SDDL(DD10),DIDA) + } + If(LNotEqual(DD11, Zero)) + { + Store(SDDL(DD11),DIDB) + } + If(LNotEqual(DD12, Zero)) + { + Store(SDDL(DD12),DIDC) + } + If(LNotEqual(DD13, Zero)) + { + Store(SDDL(DD13),DIDD) + } + If(LNotEqual(DD14, Zero)) + { + Store(SDDL(DD14),DIDE) + } + If(LNotEqual(DD15, Zero)) + { + Store(SDDL(DD15),DIDF) + } + } + + // @todo - This level of flexibility is not needed for a true + // OEM design. Simply determine the greatest number of + // encoders the platform will suppport then remove all + // return packages beyond that value. Note that for + // current silicon, the maximum number of encoders + // possible is 8. + + If(LEqual(NDID,1)) + { + Name(TMP1,Package() {0xFFFFFFFF}) + Store(Or(0x10000,DID1),Index(TMP1,0)) + Return(TMP1) + } + + If(LEqual(NDID,2)) + { + Name(TMP2,Package() {0xFFFFFFFF, + 0xFFFFFFFF}) + Store(Or(0x10000,DID1),Index(TMP2,0)) + Store(Or(0x10000,DID2),Index(TMP2,1)) + Return(TMP2) + } + + If(LEqual(NDID,3)) + { + Name(TMP3,Package() {0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF}) + Store(Or(0x10000,DID1),Index(TMP3,0)) + Store(Or(0x10000,DID2),Index(TMP3,1)) + Store(Or(0x10000,DID3),Index(TMP3,2)) + Return(TMP3) + } + + If(LEqual(NDID,4)) + { + Name(TMP4,Package() {0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF}) + Store(Or(0x10000,DID1),Index(TMP4,0)) + Store(Or(0x10000,DID2),Index(TMP4,1)) + Store(Or(0x10000,DID3),Index(TMP4,2)) + Store(Or(0x10000,DID4),Index(TMP4,3)) + Return(TMP4) + } + + If(LEqual(NDID,5)) + { + Name(TMP5,Package() {0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF}) + Store(Or(0x10000,DID1),Index(TMP5,0)) + Store(Or(0x10000,DID2),Index(TMP5,1)) + Store(Or(0x10000,DID3),Index(TMP5,2)) + Store(Or(0x10000,DID4),Index(TMP5,3)) + Store(Or(0x10000,DID5),Index(TMP5,4)) + Return(TMP5) + } + + If(LEqual(NDID,6)) + { + Name(TMP6,Package() {0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF}) + Store(Or(0x10000,DID1),Index(TMP6,0)) + Store(Or(0x10000,DID2),Index(TMP6,1)) + Store(Or(0x10000,DID3),Index(TMP6,2)) + Store(Or(0x10000,DID4),Index(TMP6,3)) + Store(Or(0x10000,DID5),Index(TMP6,4)) + Store(Or(0x10000,DID6),Index(TMP6,5)) + Return(TMP6) + } + + If(LEqual(NDID,7)) + { + Name(TMP7,Package() {0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF}) + Store(Or(0x10000,DID1),Index(TMP7,0)) + Store(Or(0x10000,DID2),Index(TMP7,1)) + Store(Or(0x10000,DID3),Index(TMP7,2)) + Store(Or(0x10000,DID4),Index(TMP7,3)) + Store(Or(0x10000,DID5),Index(TMP7,4)) + Store(Or(0x10000,DID6),Index(TMP7,5)) + Store(Or(0x10000,DID7),Index(TMP7,6)) + Return(TMP7) + } + + If(LEqual(NDID,8)) + { + Name(TMP8,Package() {0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF}) + Store(Or(0x10000,DID1),Index(TMP8,0)) + Store(Or(0x10000,DID2),Index(TMP8,1)) + Store(Or(0x10000,DID3),Index(TMP8,2)) + Store(Or(0x10000,DID4),Index(TMP8,3)) + Store(Or(0x10000,DID5),Index(TMP8,4)) + Store(Or(0x10000,DID6),Index(TMP8,5)) + Store(Or(0x10000,DID7),Index(TMP8,6)) + Store(Or(0x10000,DID8),Index(TMP8,7)) + Return(TMP8) + } + + If(LEqual(NDID,9)) + { + Name(TMP9,Package() {0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF}) + Store(Or(0x10000,DID1),Index(TMP9,0)) + Store(Or(0x10000,DID2),Index(TMP9,1)) + Store(Or(0x10000,DID3),Index(TMP9,2)) + Store(Or(0x10000,DID4),Index(TMP9,3)) + Store(Or(0x10000,DID5),Index(TMP9,4)) + Store(Or(0x10000,DID6),Index(TMP9,5)) + Store(Or(0x10000,DID7),Index(TMP9,6)) + Store(Or(0x10000,DID8),Index(TMP9,7)) + Store(Or(0x10000,DID9),Index(TMP9,8)) + Return(TMP9) + } + + If(LEqual(NDID,0x0A)) + { + Name(TMPA,Package() {0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF}) + Store(Or(0x10000,DID1),Index(TMPA,0)) + Store(Or(0x10000,DID2),Index(TMPA,1)) + Store(Or(0x10000,DID3),Index(TMPA,2)) + Store(Or(0x10000,DID4),Index(TMPA,3)) + Store(Or(0x10000,DID5),Index(TMPA,4)) + Store(Or(0x10000,DID6),Index(TMPA,5)) + Store(Or(0x10000,DID7),Index(TMPA,6)) + Store(Or(0x10000,DID8),Index(TMPA,7)) + Store(Or(0x10000,DID9),Index(TMPA,8)) + Store(Or(0x10000,DIDA),Index(TMPA,9)) + Return(TMPA) + } + + If(LEqual(NDID,0x0B)) + { + Name(TMPB,Package() {0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF}) + Store(Or(0x10000,DID1),Index(TMPB,0)) + Store(Or(0x10000,DID2),Index(TMPB,1)) + Store(Or(0x10000,DID3),Index(TMPB,2)) + Store(Or(0x10000,DID4),Index(TMPB,3)) + Store(Or(0x10000,DID5),Index(TMPB,4)) + Store(Or(0x10000,DID6),Index(TMPB,5)) + Store(Or(0x10000,DID7),Index(TMPB,6)) + Store(Or(0x10000,DID8),Index(TMPB,7)) + Store(Or(0x10000,DID9),Index(TMPB,8)) + Store(Or(0x10000,DIDA),Index(TMPB,9)) + Store(Or(0x10000,DIDB),Index(TMPB,10)) + Return(TMPB) + } + + If(LEqual(NDID,0x0C)) + { + Name(TMPC,Package() {0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF}) + Store(Or(0x10000,DID1),Index(TMPC,0)) + Store(Or(0x10000,DID2),Index(TMPC,1)) + Store(Or(0x10000,DID3),Index(TMPC,2)) + Store(Or(0x10000,DID4),Index(TMPC,3)) + Store(Or(0x10000,DID5),Index(TMPC,4)) + Store(Or(0x10000,DID6),Index(TMPC,5)) + Store(Or(0x10000,DID7),Index(TMPC,6)) + Store(Or(0x10000,DID8),Index(TMPC,7)) + Store(Or(0x10000,DID9),Index(TMPC,8)) + Store(Or(0x10000,DIDA),Index(TMPC,9)) + Store(Or(0x10000,DIDB),Index(TMPC,10)) + Store(Or(0x10000,DIDC),Index(TMPC,11)) + Return(TMPC) + } + + If(LEqual(NDID,0x0D)) + { + Name(TMPD,Package() {0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF}) + Store(Or(0x10000,DID1),Index(TMPD,0)) + Store(Or(0x10000,DID2),Index(TMPD,1)) + Store(Or(0x10000,DID3),Index(TMPD,2)) + Store(Or(0x10000,DID4),Index(TMPD,3)) + Store(Or(0x10000,DID5),Index(TMPD,4)) + Store(Or(0x10000,DID6),Index(TMPD,5)) + Store(Or(0x10000,DID7),Index(TMPD,6)) + Store(Or(0x10000,DID8),Index(TMPD,7)) + Store(Or(0x10000,DID9),Index(TMPD,8)) + Store(Or(0x10000,DIDA),Index(TMPD,9)) + Store(Or(0x10000,DIDB),Index(TMPD,10)) + Store(Or(0x10000,DIDC),Index(TMPD,11)) + Store(Or(0x10000,DIDD),Index(TMPD,12)) + Return(TMPD) + } + + If(LEqual(NDID,0x0E)) + { + Name(TMPE,Package() {0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF}) + Store(Or(0x10000,DID1),Index(TMPE,0)) + Store(Or(0x10000,DID2),Index(TMPE,1)) + Store(Or(0x10000,DID3),Index(TMPE,2)) + Store(Or(0x10000,DID4),Index(TMPE,3)) + Store(Or(0x10000,DID5),Index(TMPE,4)) + Store(Or(0x10000,DID6),Index(TMPE,5)) + Store(Or(0x10000,DID7),Index(TMPE,6)) + Store(Or(0x10000,DID8),Index(TMPE,7)) + Store(Or(0x10000,DID9),Index(TMPE,8)) + Store(Or(0x10000,DIDA),Index(TMPE,9)) + Store(Or(0x10000,DIDB),Index(TMPE,10)) + Store(Or(0x10000,DIDC),Index(TMPE,11)) + Store(Or(0x10000,DIDD),Index(TMPE,12)) + Store(Or(0x10000,DIDE),Index(TMPE,13)) + Return(TMPE) + } + + If(LEqual(NDID,0x0F)) + { + + Name(TMPF,Package() {0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF}) + Store(Or(0x10000,DID1),Index(TMPF,0)) + Store(Or(0x10000,DID2),Index(TMPF,1)) + Store(Or(0x10000,DID3),Index(TMPF,2)) + Store(Or(0x10000,DID4),Index(TMPF,3)) + Store(Or(0x10000,DID5),Index(TMPF,4)) + Store(Or(0x10000,DID6),Index(TMPF,5)) + Store(Or(0x10000,DID7),Index(TMPF,6)) + Store(Or(0x10000,DID8),Index(TMPF,7)) + Store(Or(0x10000,DID9),Index(TMPF,8)) + Store(Or(0x10000,DIDA),Index(TMPF,9)) + Store(Or(0x10000,DIDB),Index(TMPF,10)) + Store(Or(0x10000,DIDC),Index(TMPF,11)) + Store(Or(0x10000,DIDD),Index(TMPF,12)) + Store(Or(0x10000,DIDE),Index(TMPF,13)) + Store(Or(0x10000,DIDF),Index(TMPF,14)) + Return(TMPF) + } + + // If nothing else, return Unknown LFP. + // (Prevents compiler warning.) + + Return(Package() {0x00000400}) + } + + Device(DD01) + { + + // Return Unique ID. + + Method(_ADR,0,Serialized) + { + If(LEqual(And(0x0F00,DID1),0x400)) + { + Store(0x1, EDPV) + Store(NXD1, NXDX) + Store(DID1, DIDX) + Return(1) + } + If(LEqual(DID1,0)) + { + Return(1) + } + Else + { + Return(And(0xFFFF,DID1)) + } + } + + // Return the Current Status. + + Method(_DCS,0) + { + Return(CDDS(DID1)) + } + + // Query Graphics State (active or inactive). + + Method(_DGS,0) + { + If(LAnd(LEqual(And(SGMD,0x7F),0x01),CondRefOf(SNXD))) + { + Return (NXD1) + } + Return(NDDS(DID1)) + } + + // Device Set State. + + // _DSS Table: + // + // BIT31 BIT30 Execution + // 0 0 Don't implement. + // 0 1 Cache change. Nothing to Implement. + // 1 0 Don't Implement. + // 1 1 Display Switch Complete. Implement. + + Method(_DSS,1) + { + If(LEqual(And(Arg0,0xC0000000),0xC0000000)) + { + + // State change was performed by the + // Video Drivers. Simply update the + // New State. + + Store(NSTE,CSTE) + } + } + } + + Device(DD02) + { + + // Return Unique ID. + + Method(_ADR,0,Serialized) + { + If(LEqual(And(0x0F00,DID2),0x400)) + { + Store(0x2, EDPV) + Store(NXD2, NXDX) + Store(DID2, DIDX) + Return(2) + } + If(LEqual(DID2,0)) + { + Return(2) + } + Else + { + Return(And(0xFFFF,DID2)) + } + } + + // Return the Current Status. + + Method(_DCS,0) + { + If(LEqual(LIDS,0)) + { + Return(0x0) + } + + Return(CDDS(DID2)) + } + + // Query Graphics State (active or inactive). + + Method(_DGS,0) + { + // Return the Next State. + If(LAnd(LEqual(And(SGMD,0x7F),0x01),CondRefOf(SNXD))) + { + Return (NXD2) + } + Return(NDDS(DID2)) + } + + // Device Set State. (See table above.) + + Method(_DSS,1) + { + If(LEqual(And(Arg0,0xC0000000),0xC0000000)) + { + + // State change was performed by the + // Video Drivers. Simply update the + // New State. + + Store(NSTE,CSTE) + } + } + } + + Device(DD03) + { + + // Return Unique ID. + + Method(_ADR,0,Serialized) + { + If(LEqual(And(0x0F00,DID3),0x400)) + { + Store(0x3, EDPV) + Store(NXD3, NXDX) + Store(DID3, DIDX) + Return(3) + } + If(LEqual(DID3,0)) + { + Return(3) + } + Else + { + Return(And(0xFFFF,DID3)) + } + } + + // Return the Current Status. + + Method(_DCS,0) + { + If(LEqual(DID3,0)) + { + Return(0x0B) + } + Else + { + Return(CDDS(DID3)) + } + } + + // Query Graphics State (active or inactive). + + Method(_DGS,0) + { + If(LAnd(LEqual(And(SGMD,0x7F),0x01),CondRefOf(SNXD))) + { + Return (NXD3) + } + Return(NDDS(DID3)) + } + + // Device Set State. (See table above.) + + Method(_DSS,1) + { + If(LEqual(And(Arg0,0xC0000000),0xC0000000)) + { + // State change was performed by the + // Video Drivers. Simply update the + // New State. + + Store(NSTE,CSTE) + } + } + } + + Device(DD04) + { + + // Return Unique ID. + + Method(_ADR,0,Serialized) + { + If(LEqual(And(0x0F00,DID4),0x400)) + { + Store(0x4, EDPV) + Store(NXD4, NXDX) + Store(DID4, DIDX) + Return(4) + } + If(LEqual(DID4,0)) + { + Return(4) + } + Else + { + Return(And(0xFFFF,DID4)) + } + } + + // Return the Current Status. + + Method(_DCS,0) + { + If(LEqual(DID4,0)) + { + Return(0x0B) + } + Else + { + Return(CDDS(DID4)) + } + } + + // Query Graphics State (active or inactive). + + Method(_DGS,0) + { + If(LAnd(LEqual(And(SGMD,0x7F),0x01),CondRefOf(SNXD))) + { + Return (NXD4) + } + Return(NDDS(DID4)) + } + + // Device Set State. (See table above.) + + Method(_DSS,1) + { + If(LEqual(And(Arg0,0xC0000000),0xC0000000)) + { + + // State change was performed by the + // Video Drivers. Simply update the + // New State. + + Store(NSTE,CSTE) + } + } + } + + + Device(DD05) + { + + // Return Unique ID. + + Method(_ADR,0,Serialized) + { + If(LEqual(And(0x0F00,DID5),0x400)) + { + Store(0x5, EDPV) + Store(NXD5, NXDX) + Store(DID5, DIDX) + Return(5) + } + If(LEqual(DID5,0)) + { + Return(5) + } + Else + { + Return(And(0xFFFF,DID5)) + } + } + + // Return the Current Status. + + Method(_DCS,0) + { + If(LEqual(DID5,0)) + { + Return(0x0B) + } + Else + { + Return(CDDS(DID5)) + } + } + + // Query Graphics State (active or inactive). + + Method(_DGS,0) + { + If(LAnd(LEqual(And(SGMD,0x7F),0x01),CondRefOf(SNXD))) + { + Return (NXD5) + } + Return(NDDS(DID5)) + } + + // Device Set State. (See table above.) + + Method(_DSS,1) + { + If(LEqual(And(Arg0,0xC0000000),0xC0000000)) + { + // State change was performed by the + // Video Drivers. Simply update the + // New State. + + Store(NSTE,CSTE) + } + } + } + + + Device(DD06) + { + + // Return Unique ID. + + Method(_ADR,0,Serialized) + { + If(LEqual(And(0x0F00,DID6),0x400)) + { + Store(0x6, EDPV) + Store(NXD6, NXDX) + Store(DID6, DIDX) + Return(6) + } + If(LEqual(DID6,0)) + { + Return(6) + } + Else + { + Return(And(0xFFFF,DID6)) + } + } + + // Return the Current Status. + + Method(_DCS,0) + { + If(LEqual(DID6,0)) + { + Return(0x0B) + } + Else + { + Return(CDDS(DID6)) + } + } + + // Query Graphics State (active or inactive). + + Method(_DGS,0) + { + If(LAnd(LEqual(And(SGMD,0x7F),0x01),CondRefOf(SNXD))) + { + Return (NXD6) + } + Return(NDDS(DID6)) + } + + // Device Set State. (See table above.) + + Method(_DSS,1) + { + If(LEqual(And(Arg0,0xC0000000),0xC0000000)) + { + // State change was performed by the + // Video Drivers. Simply update the + // New State. + + Store(NSTE,CSTE) + } + } + } + + + Device(DD07) + { + + // Return Unique ID. + + Method(_ADR,0,Serialized) + { + If(LEqual(And(0x0F00,DID7),0x400)) + { + Store(0x7, EDPV) + Store(NXD7, NXDX) + Store(DID7, DIDX) + Return(7) + } + If(LEqual(DID7,0)) + { + Return(7) + } + Else + { + Return(And(0xFFFF,DID7)) + } + } + + // Return the Current Status. + + Method(_DCS,0) + { + If(LEqual(DID7,0)) + { + Return(0x0B) + } + Else + { + Return(CDDS(DID7)) + } + } + + // Query Graphics State (active or inactive). + + Method(_DGS,0) + { + If(LAnd(LEqual(And(SGMD,0x7F),0x01),CondRefOf(SNXD))) + { + Return (NXD7) + } + Return(NDDS(DID7)) + } + + // Device Set State. (See table above.) + + Method(_DSS,1) + { + If(LEqual(And(Arg0,0xC0000000),0xC0000000)) + { + // State change was performed by the + // Video Drivers. Simply update the + // New State. + + Store(NSTE,CSTE) + } + } + } + + + Device(DD08) + { + + // Return Unique ID. + + Method(_ADR,0,Serialized) + { + If(LEqual(And(0x0F00,DID8),0x400)) + { + Store(0x8, EDPV) + Store(NXD8, NXDX) + Store(DID8, DIDX) + Return(8) + } + If(LEqual(DID8,0)) + { + Return(8) + } + Else + { + Return(And(0xFFFF,DID8)) + } + } + + // Return the Current Status. + + Method(_DCS,0) + { + If(LEqual(DID8,0)) + { + Return(0x0B) + } + Else + { + Return(CDDS(DID8)) + } + } + + // Query Graphics State (active or inactive). + + Method(_DGS,0) + { + If(LAnd(LEqual(And(SGMD,0x7F),0x01),CondRefOf(SNXD))) + { + Return (NXD8) + } + Return(NDDS(DID8)) + } + + // Device Set State. (See table above.) + + Method(_DSS,1) + { + If(LEqual(And(Arg0,0xC0000000),0xC0000000)) + { + // State change was performed by the + // Video Drivers. Simply update the + // New State. + + Store(NSTE,CSTE) + } + } + } + + Device(DD09) + { + // Return Unique ID. + + Method(_ADR,0,Serialized) + { + If(LEqual(And(0x0F00,DID9),0x400)) + { + Store(0x9, EDPV) + Store(NXD8, NXDX) + Store(DID9, DIDX) + Return(9) + } + If(LEqual(DID9,0)) + { + Return(9) + } + Else + { + Return(And(0xFFFF,DID9)) + } + } + + // Return the Current Status. + + Method(_DCS,0) + { + If(LEqual(DID9,0)) + { + Return(0x0B) + } + Else + { + Return(CDDS(DID9)) + } + } + + // Query Graphics State (active or inactive). + + Method(_DGS,0) + { + If(LAnd(LEqual(And(SGMD,0x7F),0x01),CondRefOf(SNXD))) + { + Return (NXD8) + } + Return(NDDS(DID9)) + } + + // Device Set State. (See table above.) + + Method(_DSS,1) + { + If(LEqual(And(Arg0,0xC0000000),0xC0000000)) + { + // State change was performed by the + // Video Drivers. Simply update the + // New State. + Store(NSTE,CSTE) + } + } + } + + Device(DD0A) + { + // Return Unique ID. + + Method(_ADR,0,Serialized) + { + If(LEqual(And(0x0F00,DIDA),0x400)) + { + Store(0xA, EDPV) + Store(NXD8, NXDX) + Store(DIDA, DIDX) + Return(0x0A) + } + If(LEqual(DIDA,0)) + { + Return(0x0A) + } + Else + { + Return(And(0xFFFF,DIDA)) + } + } + + // Return the Current Status. + + Method(_DCS,0) + { + If(LEqual(DIDA,0)) + { + Return(0x0B) + } + Else + { + Return(CDDS(DIDA)) + } + } + + // Query Graphics State (active or inactive). + + Method(_DGS,0) + { + If(LAnd(LEqual(And(SGMD,0x7F),0x01),CondRefOf(SNXD))) + { + Return (NXD8) + } + Return(NDDS(DIDA)) + } + + // Device Set State. (See table above.) + + Method(_DSS,1) + { + If(LEqual(And(Arg0,0xC0000000),0xC0000000)) + { + // State change was performed by the + // Video Drivers. Simply update the + // New State. + Store(NSTE,CSTE) + } + } + } + + Device(DD0B) + { + // Return Unique ID. + + Method(_ADR,0,Serialized) + { + If(LEqual(And(0x0F00,DIDB),0x400)) + { + Store(0xB, EDPV) + Store(NXD8, NXDX) + Store(DIDB, DIDX) + Return(0X0B) + } + If(LEqual(DIDB,0)) + { + Return(0x0B) + } + Else + { + Return(And(0xFFFF,DIDB)) + } + } + + // Return the Current Status. + + Method(_DCS,0) + { + If(LEqual(DIDB,0)) + { + Return(0x0B) + } + Else + { + Return(CDDS(DIDB)) + } + } + + // Query Graphics State (active or inactive). + + Method(_DGS,0) + { + If(LAnd(LEqual(And(SGMD,0x7F),0x01),CondRefOf(SNXD))) + { + Return (NXD8) + } + Return(NDDS(DIDB)) + } + + // Device Set State. (See table above.) + + Method(_DSS,1) + { + If(LEqual(And(Arg0,0xC0000000),0xC0000000)) + { + // State change was performed by the + // Video Drivers. Simply update the + // New State. + Store(NSTE,CSTE) + } + } + } + + Device(DD0C) + { + // Return Unique ID. + + Method(_ADR,0,Serialized) + { + If(LEqual(And(0x0F00,DIDC),0x400)) + { + Store(0xC, EDPV) + Store(NXD8, NXDX) + Store(DIDC, DIDX) + Return(0X0C) + } + If(LEqual(DIDC,0)) + { + Return(0x0C) + } + Else + { + Return(And(0xFFFF,DIDC)) + } + } + + // Return the Current Status. + + Method(_DCS,0) + { + If(LEqual(DIDC,0)) + { + Return(0x0C) + } + Else + { + Return(CDDS(DIDC)) + } + } + + // Query Graphics State (active or inactive). + + Method(_DGS,0) + { + If(LAnd(LEqual(And(SGMD,0x7F),0x01),CondRefOf(SNXD))) + { + Return (NXD8) + } + Return(NDDS(DIDC)) + } + + // Device Set State. (See table above.) + + Method(_DSS,1) + { + If(LEqual(And(Arg0,0xC0000000),0xC0000000)) + { + // State change was performed by the + // Video Drivers. Simply update the + // New State. + Store(NSTE,CSTE) + } + } + } + + Device(DD0D) + { + // Return Unique ID. + + Method(_ADR,0,Serialized) + { + If(LEqual(And(0x0F00,DIDD),0x400)) + { + Store(0xD, EDPV) + Store(NXD8, NXDX) + Store(DIDD, DIDX) + Return(0X0D) + } + If(LEqual(DIDD,0)) + { + Return(0x0D) + } + Else + { + Return(And(0xFFFF,DIDD)) + } + } + + // Return the Current Status. + + Method(_DCS,0) + { + If(LEqual(DIDD,0)) + { + Return(0x0D) + } + Else + { + Return(CDDS(DIDD)) + } + } + + // Query Graphics State (active or inactive). + + Method(_DGS,0) + { + If(LAnd(LEqual(And(SGMD,0x7F),0x01),CondRefOf(SNXD))) + { + Return (NXD8) + } + Return(NDDS(DIDD)) + } + + // Device Set State. (See table above.) + + Method(_DSS,1) + { + If(LEqual(And(Arg0,0xC0000000),0xC0000000)) + { + // State change was performed by the + // Video Drivers. Simply update the + // New State. + Store(NSTE,CSTE) + } + } + } + + Device(DD0E) + { + // Return Unique ID. + + Method(_ADR,0,Serialized) + { + If(LEqual(And(0x0F00,DIDE),0x400)) + { + Store(0xE, EDPV) + Store(NXD8, NXDX) + Store(DIDE, DIDX) + Return(0X0E) + } + If(LEqual(DIDE,0)) + { + Return(0x0E) + } + Else + { + Return(And(0xFFFF,DIDE)) + } + } + + // Return the Current Status. + + Method(_DCS,0) + { + If(LEqual(DIDE,0)) + { + Return(0x0E) + } + Else + { + Return(CDDS(DIDE)) + } + } + + // Query Graphics State (active or inactive). + + Method(_DGS,0) + { + If(LAnd(LEqual(And(SGMD,0x7F),0x01),CondRefOf(SNXD))) + { + Return (NXD8) + } + Return(NDDS(DIDE)) + } + + // Device Set State. (See table above.) + + Method(_DSS,1) + { + If(LEqual(And(Arg0,0xC0000000),0xC0000000)) + { + // State change was performed by the + // Video Drivers. Simply update the + // New State. + Store(NSTE,CSTE) + } + } + } + + Device(DD0F) + { + // Return Unique ID. + + Method(_ADR,0,Serialized) + { + If(LEqual(And(0x0F00,DIDF),0x400)) + { + Store(0xF, EDPV) + Store(NXD8, NXDX) + Store(DIDF, DIDX) + Return(0X0F) + } + If(LEqual(DIDF,0)) + { + Return(0x0F) + } + Else + { + Return(And(0xFFFF,DIDF)) + } + } + + // Return the Current Status. + + Method(_DCS,0) + { + If(LEqual(DIDC,0)) + { + Return(0x0F) + } + Else + { + Return(CDDS(DIDF)) + } + } + + // Query Graphics State (active or inactive). + + Method(_DGS,0) + { + If(LAnd(LEqual(And(SGMD,0x7F),0x01),CondRefOf(SNXD))) + { + Return (NXD8) + } + Return(NDDS(DIDF)) + } + + // Device Set State. (See table above.) + + Method(_DSS,1) + { + If(LEqual(And(Arg0,0xC0000000),0xC0000000)) + { + // State change was performed by the + // Video Drivers. Simply update the + // New State. + Store(NSTE,CSTE) + } + } + } + +//device for eDP + Device(DD1F) + { + // Return Unique ID. + + Method(_ADR,0,Serialized) + { + If(LEqual(EDPV, 0x0)) + { + Return(0x1F) + } + Else + { + Return(And(0xFFFF,DIDX)) + } + } + + // Return the Current Status. + + Method(_DCS,0) + { + If(LEqual(EDPV, 0x0)) + { + Return(0x00) + } + Else + { + Return(CDDS(DIDX)) + } + } + + // Query Graphics State (active or inactive). + + Method(_DGS,0) + { + If(LAnd(LEqual(And(SGMD,0x7F),0x01),CondRefOf(SNXD))) + { + Return (NXDX) + } + Return(NDDS(DIDX)) + } + + // Device Set State. (See table above.) + + Method(_DSS,1) + { + If(LEqual(And(Arg0,0xC0000000),0xC0000000)) + { + // State change was performed by the + // Video Drivers. Simply update the + // New State. + Store(NSTE,CSTE) + } + } + // Query List of Brightness Control Levels Supported. + + Method(_BCL,0) + { + // List of supported brightness levels in the following sequence. + + // Level when machine has full power. + // Level when machine is on batteries. + // Other supported levels. + Return(Package(){80, 50, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100}) + } + + // Set the Brightness Level. + + Method (_BCM,1) + { + // Set the requested level if it is between 0 and 100%. + + If(LAnd(LGreaterEqual(Arg0,0),LLessEqual(Arg0,100))) + { + \_SB.PCI0.GFX0.AINT(1, Arg0) + Store(Arg0,BRTL) // Store Brightness Level. + } + } + + // Brightness Query Current level. + + Method (_BQC,0) + { + Return(BRTL) + } + } + + Method(SDDL,1) + { + Increment(NDID) + Store(And(Arg0,0xF0F),Local0) + Or(0x80000000,Local0, Local1) + If(LEqual(DIDL,Local0)) + { + Return(Local1) + } + If(LEqual(DDL2,Local0)) + { + Return(Local1) + } + If(LEqual(DDL3,Local0)) + { + Return(Local1) + } + If(LEqual(DDL4,Local0)) + { + Return(Local1) + } + If(LEqual(DDL5,Local0)) + { + Return(Local1) + } + If(LEqual(DDL6,Local0)) + { + Return(Local1) + } + If(LEqual(DDL7,Local0)) + { + Return(Local1) + } + If(LEqual(DDL8,Local0)) + { + Return(Local1) + } + If(LEqual(DDL9,Local0)) + { + Return(Local1) + } + If(LEqual(DD10,Local0)) + { + Return(Local1) + } + If(LEqual(DD11,Local0)) + { + Return(Local1) + } + If(LEqual(DD12,Local0)) + { + Return(Local1) + } + If(LEqual(DD13,Local0)) + { + Return(Local1) + } + If(LEqual(DD14,Local0)) + { + Return(Local1) + } + If(LEqual(DD15,Local0)) + { + Return(Local1) + } + Decrement(NDID) // AMI_OVERRIDE + Return(0) + } + + Method(CDDS,1) + { + Store(And(Arg0,0xF0F),Local0) + + If(LEqual(0, Local0)) + { + Return(0x1D) + } + If(LEqual(CADL, Local0)) + { + Return(0x1F) + } + If(LEqual(CAL2, Local0)) + { + Return(0x1F) + } + If(LEqual(CAL3, Local0)) + { + Return(0x1F) + } + If(LEqual(CAL4, Local0)) + { + Return(0x1F) + } + If(LEqual(CAL5, Local0)) + { + Return(0x1F) + } + If(LEqual(CAL6, Local0)) + { + Return(0x1F) + } + If(LEqual(CAL7, Local0)) + { + Return(0x1F) + } + If(LEqual(CAL8, Local0)) + { + Return(0x1F) + } + Return(0x1D) + } + + Method(NDDS,1) + { + Store(And(Arg0,0xF0F),Local0) + + If(LEqual(0, Local0)) + { + Return(0) + } + If(LEqual(NADL, Local0)) + { + Return(1) + } + If(LEqual(NDL2, Local0)) + { + Return(1) + } + If(LEqual(NDL3, Local0)) + { + Return(1) + } + If(LEqual(NDL4, Local0)) + { + Return(1) + } + If(LEqual(NDL5, Local0)) + { + Return(1) + } + If(LEqual(NDL6, Local0)) + { + Return(1) + } + If(LEqual(NDL7, Local0)) + { + Return(1) + } + If(LEqual(NDL8, Local0)) + { + Return(1) + } + Return(0) + } + + // Include IGD OpRegion/Software SCI interrupt handler which is use by + // the graphics drivers to request data from system BIOS. + + include ("IgdOpRn.ASL") +// +// iGfx WA for HSW. Exclude the memory range 20000000-201FFFFF (2MB) and 0x40004000-0x40004FFF (4KB +// +Device(\_SB.MEM2) +{ + Name(_HID, EISAID("PNP0C01")) // Hardware Device ID + Name(_UID, 2) + + Name(CRS2, ResourceTemplate() + { + Memory32Fixed (ReadWrite, 0x20000000, 0x00200000) + Memory32Fixed (ReadWrite, 0x40004000, 0x00001000) + }) + + Method(_STA,0) + { + If(IGDS) + { + If (LEqual(PNHM,0x000306C1)) + { + Return(0xF) // then enabled + } + } + Return(0) // then disabled + } + + Method (_CRS, 0) + { + Return(CRS2) + } + +} diff --git a/ReferenceCode/Chipset/SystemAgent/AcpiTables/SaSsdt/IgdOGBDA.ASL b/ReferenceCode/Chipset/SystemAgent/AcpiTables/SaSsdt/IgdOGBDA.ASL new file mode 100644 index 0000000..e28ce5c --- /dev/null +++ b/ReferenceCode/Chipset/SystemAgent/AcpiTables/SaSsdt/IgdOGBDA.ASL @@ -0,0 +1,164 @@ +/*++ + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +--*/ + +/*++ + +Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved +This software and associated documentation (if any) is furnished +under a license and may only be used or copied in accordance +with the terms of the license. Except as permitted by such +license, no part of this software or documentation may be +reproduced, stored in a retrieval system, or transmitted in any +form or by any means without the express written consent of +Intel Corporation. + + +Module Name: + + IgdOGBDA.ASL + +Abstract: + + IGD OpRegion/Software SCI Reference Code. + This file contains Get BIOS Data Area funciton support for + the Integrated Graphics Device (IGD) OpRegion/Software SCI mechanism. + +--*/ + + +Method (GBDA, 0, Serialized) +{ + + // Supported calls: Sub-function 0 + + If (LEqual(GESF, 0)) + { + //<TODO> Update implementation specific supported calls. Reference + // code is set to Intel's validated implementation. + + Store(0x0000659, PARM) + + Store(Zero, GESF) // Clear the exit parameter + Return(SUCC) // Success + } + + // Requested callbacks: Sub-function 1 + + If (LEqual(GESF, 1)) + { + + //<TODO> Update implementation specific system BIOS requested call + // back functions. Call back functions are where the driver calls the + // system BIOS at function indicated event. + + Store(0x300482, PARM) + If(LEqual(S0ID, One)){ + Or(PARM, 0x100, PARM) //Request Fn 8 callback in CS systems + } + Store(Zero, GESF) // Clear the exit parameter + Return(SUCC) // Success + } + + // Get Boot display Preferences: Sub-function 4 + + If (LEqual(GESF, 4)) + { + + //<TODO> Update the implementation specific Get Boot Display + // Preferences function. + + And(PARM, 0xEFFF0000, PARM) // PARM[30:16] = Boot device ports + And(PARM, ShiftLeft(DeRefOf(Index(DBTB, IBTT)), 16), PARM) + Or(IBTT, PARM, PARM) // PARM[7:0] = Boot device type + + Store(Zero, GESF) // Clear the exit parameter + Return(SUCC) // Success + } + + // Panel details: Sub-function 5 + + If (LEqual(GESF, 5)) + { + + //<TODO> Update the implementation specific Get Panel Details + // function. + + Store(IPSC, PARM) // Report the scaling setting + Or(PARM, ShiftLeft(IPAT, 8), PARM) + Add(PARM, 0x100, PARM) // Adjust panel type, 0 = VBT default + Or(PARM, ShiftLeft(LIDS, 16), PARM) // Report the lid state + Add(PARM, 0x10000, PARM) // Adjust the lid state, 0 = Unknown + Or(PARM, ShiftLeft(IBIA, 20), PARM) // Report the BIA setting + Store(Zero, GESF) + Return(SUCC) + } + + // Internal graphics: Sub-function 7 + + If (LEqual(GESF, 7)) + { + Store(GIVD, PARM) // PARM[0] - VGA mode(1=VGA) + Xor(PARM, 1, PARM) // Invert the VGA mode polarity + Or(PARM, ShiftLeft(GMFN, 1), PARM) // PARM[1] - # IGD PCI functions-1 + // PARM[3:2] - Reserved + // PARM[4] - IGD D3 support(0=cold) + // PARM[10:5] - Reserved + Or(PARM, ShiftLeft(3, 11), PARM) // PARM[12:11] - DVMT mode(11b = 5.0) + + // + // Report DVMT 5.0 Total Graphics memory size. + // + Or(PARM, ShiftLeft(IDMS, 17), PARM) // Bits 20:17 are for Gfx total memory size + + // If the "Set Internal Graphics" call is supported, the modified + // settings flag must be programmed per the specification. This means + // that the flag must be set to indicate that system BIOS requests + // these settings. Once "Set Internal Graphics" is called, the + // modified settings flag must be cleared on all subsequent calls to + // this function. + + // Report the graphics frequency based on B0:D2:F0:RF0h[12]. Must + // take into account the current VCO. + + Or(ShiftLeft(Derefof(Index(Derefof(Index(CDCT, HVCO)), CDVL)), 21),PARM, PARM) + + Store(1, GESF) // Set the modified settings flag + Return(SUCC) + } + + // Spread spectrum clocks: Sub-function 10 + + If (LEqual(GESF, 10)) + { + + Store(0, PARM) // Assume SSC is disabled + + If(ISSC) + { + Or(PARM, 3, PARM) // If SSC enabled, return SSC1+Enabled + } + + Store(0, GESF) // Set the modified settings flag + Return(SUCC) // Success + } + + + If (LEqual(GESF, 11)) + { + Store(KSV0, PARM) // First four bytes of AKSV + Store(KSV1, GESF) // Fifth byte of AKSV + + Return(SUCC) // Success + } + + // A call to a reserved "Get BIOS data" function was received. + + Store(Zero, GESF) // Clear the exit parameter + Return(CRIT) // Reserved, "Critical failure" +} diff --git a/ReferenceCode/Chipset/SystemAgent/AcpiTables/SaSsdt/IgdOMOBF.ASL b/ReferenceCode/Chipset/SystemAgent/AcpiTables/SaSsdt/IgdOMOBF.ASL new file mode 100644 index 0000000..07a716b --- /dev/null +++ b/ReferenceCode/Chipset/SystemAgent/AcpiTables/SaSsdt/IgdOMOBF.ASL @@ -0,0 +1,560 @@ +/*++ + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +--*/ + +/*++ + +Copyright (c) 1999 - 2013 Intel Corporation. All rights reserved +This software and associated documentation (if any) is furnished +under a license and may only be used or copied in accordance +with the terms of the license. Except as permitted by such +license, no part of this software or documentation may be +reproduced, stored in a retrieval system, or transmitted in any +form or by any means without the express written consent of +Intel Corporation. + + +Module Name: + + IgdOMOBF.ASL + +Abstract: + + IGD OpRegion/Software SCI Reference Code. + This file contains ASL code with the purpose of handling events + i.e. hotkeys and other system interrupts. + +--*/ + + +// Notes: +// 1. The following routines are to be called from the appropriate event +// handlers. +// 2. This code cannot comprehend the exact implementation in the OEM's BIOS. +// Therefore, an OEM must call these methods from the existing event +// handler infrastructure. Details on when/why to call each method is +// included in the method header under the "usage" section. + + +/************************************************************************; +;* ACPI Notification Methods +;************************************************************************/ + + +/************************************************************************; +;* +;* Name: PDRD +;* +;* Description: Check if the graphics driver is ready to process +;* notifications and video extensions. +;* +;* Usage: This method is to be called prior to performing any +;* notifications or handling video extensions. +;* Ex: If (PDRD()) {Return (FAIL)} +;* +;* Input: None +;* +;* Output: None +;* +;* References: DRDY (Driver ready status), ASLP (Driver recommended +;* sleep timeout value). +;* +;************************************************************************/ + +External(HNOT, MethodObj) + +Method(PDRD) +{ + + // Sleep for ASLP milliseconds if the driver is not ready. + + + // If DRDY is clear, the driver is not ready. If the return value is + // !=0, do not perform any notifications or video extension handling. + + Return(LNot(DRDY)) +} + + +/************************************************************************; +;* +;* Name: PSTS +;* +;* Description: Check if the graphics driver has completed the previous +;* "notify" command. +;* +;* Usage: This method is called before every "notify" command. A +;* "notify" should only be set if the driver has completed the +;* previous command. Else, ignore the event and exit the parent +;* method. +;* Ex: If (PSTS()) {Return (FAIL)} +;* +;* Input: None +;* +;* Output: None +;* +;* References: CSTS (Notification status), ASLP (Driver recommended sleep +;* timeout value). +;* +;************************************************************************/ + +Method(PSTS) +{ + If(LGreater(CSTS, 2)) + { + // Sleep for ASLP milliseconds if the status is not "success, + // failure, or pending" + // + Sleep(ASLP) + } + + Return(LEqual(CSTS, 3)) // Return True if still Dispatched +} + + +/************************************************************************; +;* +;* Name: GNOT +;* +;* Description: Call the appropriate methods to query the graphics driver +;* status. If all methods return success, do a notification of +;* the graphics device. +;* +;* Usage: This method is to be called when a graphics device +;* notification is required (display switch hotkey, etc). +;* +;* Input: Arg0 = Current event type: +;* 1 = display switch +;* 2 = lid +;* 3 = dock +;* Arg1 = Notification type: +;* 0 = Re-enumeration +;* 0x80 = Display switch +;* +;* Output: Returns 0 = success, 1 = failure +;* +;* References: PDRD and PSTS methods. OSYS (OS version) +;* +;************************************************************************/ + +Method(GNOT, 2) +{ + // Check for 1. Driver loaded, 2. Driver ready. + // If any of these cases is not met, skip this event and return failure. + // + If(PDRD()) + { + Return(0x1) // Return failure if driver not loaded. + } + + Store(Arg0, CEVT) // Set up the current event value + Store(3, CSTS) // CSTS=BIOS dispatched an event + + If(LAnd(LEqual(CHPD, 0), LEqual(Arg1, 0))) // Do not re-enum if driver supports hotplug + { + If(LOr(LGreater(OSYS, 2000), LLess(OSYS, 2006))) + { + // + // WINXP requires that the entire PCI Bridge be re-enumerated. + // + Notify(\_SB.PCI0, Arg1) + } + Else + { + // + // Re-enumerate the Graphics Device for non-XP operating systems. + // + Notify(\_SB.PCI0.GFX0, Arg1) + } + } + + If(CondRefOf(HNOT)) + { + HNOT(Arg0) //Notification handler for Switchable graphics + } + Else + { + Notify(\_SB.PCI0.GFX0,0x80) + } + + Return(0x0) // Return success +} + + +/************************************************************************; +;* +;* Name: GHDS +;* +;* Description: Handle a hotkey display switching event (performs a +;* Notify(GFX0, 0). +;* +;* Usage: This method must be called when a hotkey event occurs and the +;* purpose of that hotkey is to do a display switch. +;* +;* Input: Arg0 = Toggle table number. +;* +;* Output: Returns 0 = success, 1 = failure. +;* CEVT and TIDX are indirect outputs. +;* +;* References: TIDX, GNOT +;* +;************************************************************************/ + +Method(GHDS, 1) +{ + Store(Arg0, TIDX) // Store the table number + + // Call GNOT for CEVT = 1 = hotkey, notify value = 0 + + Return(GNOT(1, 0)) // Return stats from GNOT +} + + +/************************************************************************; +;* +;* Name: GLID +;* +;* Description: Handle a lid event (performs the Notify(GFX0, 0), but not the +;* lid notify). +;* +;* Usage: This method must be called when a lid event occurs. A +;* Notify(LID0, 0x80) must follow the call to this method. +;* +;* Input: Arg0 = Lid state: +;* 0 = All closed +;* 1 = internal LFP lid open +;* 2 = external lid open +;* 3 = both external and internal open +;* +;* Output: Returns 0=success, 1=failure. +;* CLID and CEVT are indirect outputs. +;* +;* References: CLID, GNOT +;* +;************************************************************************/ + +Method(GLID, 1) +{ + + If (LEqual(Arg0,1)) + { + Store(3,CLID) + } + Else + { + Store(Arg0, CLID) + } + + //Store(Arg0, CLID) // Store the current lid state + + // Call GNOT for CEVT=2=Lid, notify value = 0 + + if (GNOT(2, 0)) { + Or (CLID, 0x80000000, CLID) + Return (1) // Return Fail + } + + Return (0) // Return Pass +} + + +/************************************************************************; +;* +;* Name: GDCK +;* +;* Description: Handle a docking event by updating the current docking status +;* and doing a notification. +;* +;* Usage: This method must be called when a docking event occurs. +;* +;* Input: Arg0 = Docking state: +;* 0 = Undocked +;* 1 = Docked +;* +;* Output: Returns 0=success, 1=failure. +;* CDCK and CEVT are indirect outputs. +;* +;* References: CDCK, GNOT +;* +;************************************************************************/ + +Method(GDCK, 1) +{ + Store(Arg0, CDCK) // Store the current dock state + + // Call GNOT for CEVT=4=Dock, notify value = 0 + + Return(GNOT(4, 0)) // Return stats from GNOT +} + + +/************************************************************************; +;* ASLE Interrupt Methods +;************************************************************************/ + + +/************************************************************************; +;* +;* Name: PARD +;* +;* Description: Check if the driver is ready to handle ASLE interrupts +;* generate by the system BIOS. +;* +;* Usage: This method must be called before generating each ASLE +;* interrupt. +;* +;* Input: None +;* +;* Output: Returns 0 = success, 1 = failure. +;* +;* References: ARDY (Driver readiness), ASLP (Driver recommended sleep +;* timeout value) +;* +;************************************************************************/ + +Method(PARD) +{ + If(LNot(ARDY)) + { + + // Sleep for ASLP milliseconds if the driver is not ready. + + Sleep(ASLP) + } + + // If ARDY is clear, the driver is not ready. If the return value is + // !=0, do not generate the ASLE interrupt. + + Return(LNot(ARDY)) +} + +// +// Intel Ultrabook Event Handler. Arg0 represents the Ultrabook Event Bit # to pass +// to the Intel Graphics Driver. Note that this is a serialized method, meaning +// sumultaneous events are not allowed. +// + +Method(IUEH,1,Serialized) +{ + And(IUER,0xC0,IUER) // Clear all button events on entry. + XOr(IUER,Shiftleft(1,Arg0),IUER) // Toggle status. + + If(LLessEqual(Arg0,4)) // Button Event? + { + Return(AINT(5,0)) // Generate event and return status. + + } + Else // Indicator Event. + { + Return(AINT(Arg0,0)) // Generate event and return status. + } +} + +/************************************************************************; +;* +;* Name: AINT +;* +;* Description: Call the appropriate methods to generate an ASLE interrupt. +;* This process includes ensuring the graphics driver is ready +;* to process the interrupt, ensuring the driver supports the +;* interrupt of interest, and passing information about the event +;* to the graphics driver. +;* +;* Usage: This method must called to generate an ASLE interrupt. +;* +;* Input: Arg0 = ASLE command function code: +;* 0 = Set ALS illuminance +;* 1 = Set backlight brightness +;* 2 = Do Panel Fitting +;* 4 = Reserved +;* 5 = Button Indicator Event +;* 6 = Convertible Indicator Event +;* 7 = Docking Indicator Event +;* Arg1 = If Arg0 = 0, current ALS reading: +;* 0 = Reading below sensor range +;* 1-0xFFFE = Current sensor reading +;* 0xFFFF = Reading above sensor range +;* Arg1 = If Arg0 = 1, requested backlight percentage +;* +;* Output: Returns 0 = success, 1 = failure +;* +;* References: PARD method. +;* +;************************************************************************/ + +Method(AINT, 2) +{ + + // Return failure if the requested feature is not supported by the + // driver. + + If(LNot(And(TCHE, ShiftLeft(1, Arg0)))) + { + Return(0x1) + } + + // Return failure if the driver is not ready to handle an ASLE + // interrupt. + + If(PARD()) + { + Return(0x1) + } + + // Handle Intel Ultrabook Events. + + If(LAnd(LGreaterEqual(Arg0,5),LLessEqual(Arg0,7))) + { + Store(ShiftLeft(1,Arg0), ASLC) // Set Ultrbook Event [6:4]. + Store(0x01, ASLE) // Generate ASLE interrupt + + Store(0,Local2) // Use Local2 as a timeout counter. Intialize to zero. + + While(LAnd(LLess(Local2,250),LNotEqual(ASLC,0))) // Wait 1 second or until Driver ACKs a success. + { + Sleep(4) // Delay 4 ms. + Increment(Local2) // Increment Timeout. + } + + Return(0) // Return success + } + + // Evaluate the first argument (Panel fitting, backlight brightness, or ALS). + + If(LEqual(Arg0, 2)) // Arg0 = 2, so request a panel fitting mode change. + { + If(CPFM) // If current mode field is non-zero use it. + { + And(CPFM, 0x0F, Local0) // Create variables without reserved + And(EPFM, 0x0F, Local1) // or valid bits. + + If(LEqual(Local0, 1)) // If current mode is centered, + { + If(And(Local1, 6)) // and if stretched is enabled, + { + Store(6, PFIT) // request stretched. + } + Else // Otherwise, + { + If(And(Local1, 8)) // if aspect ratio is enabled, + { + Store(8, PFIT) // request aspect ratio. + } + Else // Only centered mode is enabled + { + Store(1, PFIT) // so request centered. (No change.) + } + } + } + If(LEqual(Local0, 6)) // If current mode is stretched, + { + If(And(Local1, 8)) // and if aspect ratio is enabled, + { + Store(8, PFIT) // request aspect ratio. + } + Else // Otherwise, + { + If(And(Local1, 1)) // if centered is enabled, + { + Store(1, PFIT) // request centered. + } + Else // Only stretched mode is enabled + { + Store(6, PFIT) // so request stretched. (No change.) + } + } + } + If(LEqual(Local0, 8)) // If current mode is aspect ratio, + { + If(And(Local1, 1)) // and if centered is enabled, + { + Store(1, PFIT) // request centered. + } + Else // Otherwise, + { + If(And(Local1, 6)) // if stretched is enabled, + { + Store(6, PFIT) // request stretched. + } + Else // Only aspect ratio mode is enabled + { + Store(8, PFIT) // so request aspect ratio. (No change.) + } + } + } + } + + // The following code for panel fitting (within the Else condition) is retained for backward compatiblity. + + Else // If CFPM field is zero use PFIT and toggle the + { + Xor(PFIT,7,PFIT) // mode setting between stretched and centered only. + } + + Or(PFIT,0x80000000,PFIT) // Set the valid bit for all cases. + + Store(4, ASLC) // Store "Panel fitting event" to ASLC[31:1] + } + Else + { + If(LEqual(Arg0, 1)) // Arg0=1, so set the backlight brightness. + { + Store(Divide(Multiply(Arg1, 255), 100), BCLP) // Convert from percent to 0-255. + + Or(BCLP, 0x80000000, BCLP) // Set the valid bit. + + Store(2, ASLC) // Store "Backlight control event" to ASLC[31:1] + } + Else + { + If(LEqual(Arg0, 0)) // Arg0=0, so set the ALS illuminace + { + Store(Arg1, ALSI) + + Store(1, ASLC) // Store "ALS event" to ASLC[31:1] + } + Else + { + Return(0x1) // Unsupported function + } + } + } + + Store(0x01, ASLE) // Generate ASLE interrupt + Return(0x0) // Return success +} + + +/************************************************************************; +;* +;* Name: SCIP +;* +;* Description: Checks the presence of the OpRegion and SCI +;* +;* Usage: This method is called before other OpRegion methods. The +;* former "GSMI True/False is not always valid. This method +;* checks if the OpRegion Version is non-zero and if non-zero, +;* (present and readable) then checks the GSMI flag. +;* +;* Input: None +;* +;* Output: Boolean True = SCI present. +;* +;* References: None +;* +;************************************************************************/ + +Method(SCIP) +{ + If(LNotEqual(OVER,0)) // If OpRegion Version not 0. + { + Return(LNot(GSMI)) // Return True if SCI. + } + + Return(0) // Else Return False. +} diff --git a/ReferenceCode/Chipset/SystemAgent/AcpiTables/SaSsdt/IgdOSBCB.ASL b/ReferenceCode/Chipset/SystemAgent/AcpiTables/SaSsdt/IgdOSBCB.ASL new file mode 100644 index 0000000..9cb0db6 --- /dev/null +++ b/ReferenceCode/Chipset/SystemAgent/AcpiTables/SaSsdt/IgdOSBCB.ASL @@ -0,0 +1,335 @@ +/*++ + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +--*/ + +/*++ + +Copyright (c) 1999 - 2013 Intel Corporation. All rights reserved +This software and associated documentation (if any) is furnished +under a license and may only be used or copied in accordance +with the terms of the license. Except as permitted by such +license, no part of this software or documentation may be +reproduced, stored in a retrieval system, or transmitted in any +form or by any means without the express written consent of +Intel Corporation. + + +Module Name: + + IgdOSBCB.ASL + +Abstract: + + This file contains the system BIOS call back functionality for the + OpRegion/Software SCI mechanism. + +--*/ + + +Method (SBCB, 0, Serialized) +{ + + // Supported Callbacks: Sub-function 0 + + If (LEqual(GESF, 0x0)) + { + + //<TODO> An OEM may support the driver->SBIOS status callbacks, but + // the supported callbacks value must be modified. The code that is + // executed upon reception of the callbacks must be also be updated + // to perform the desired functionality. + + Store(0x00000000, PARM) // No callbacks supported + //Store(0x000787FD, PARM) // Used for Intel test implementaion + + // <NOTSAMPLECODE> + + Store(0x000F87DD, PARM) + + // </NOTSAMPLECODE> + + Store(Zero, GESF) // Clear the exit parameter + Return(SUCC) // "Success" + } + + // BIOS POST Completion: Sub-function 1 + + If (LEqual(GESF, 1)) + { + Store(Zero, GESF) // Clear the exit parameter + Store(Zero, PARM) + Return(SUCC) // Not supported, but no failure + } + + // Pre-Hires Set Mode: Sub-function 3 + + If (LEqual(GESF, 3)) + { + Store(Zero, GESF) // Clear the exit parameter + Store(Zero, PARM) + Return(SUCC) // Not supported, but no failure + } + + // Post-Hires Set Mode: Sub-function 4 + + If (LEqual(GESF, 4)) + { + Store(Zero, GESF) // Clear the exit parameter + Store(Zero, PARM) + Return(SUCC) // Not supported, but no failure + } + + // Display Switch: Sub-function 5 + + If (LEqual(GESF, 5)) + { + Store(Zero, GESF) // Clear the exit parameter + Store(Zero, PARM) + Return(SUCC) // Not supported, but no failure + } + + // Adapter Power State: Sub-function 7 + + If (LEqual(GESF, 7)) + { + // + // Handle Low Power S0 Idle Capability if enabled + // + If(LEqual(S0ID, One)){ + // + // Call GUAM to trigger CS Entry + // If Adapter Power State Notification = D1 (PARM[7:0]=0x01) + // + If (LEqual (And(PARM,0xFF), 0x01)) { + // GUAM - Global User Absent Mode Notification Method + \GUAM(One) // 0x01 - Power State Standby (CS Entry) + } + } + + // Upon notification from driver that the Adapter Power State = D0, + // check if previous lid event failed. If it did, retry the lid + // event here. + If(LEqual(PARM, 0)) + { + Store(CLID, Local0) + If(And(0x80000000,Local0)) + { + And(CLID, 0x0000000F, CLID) + GLID(CLID) + } + } + Store(Zero, GESF) // Clear the exit parameter + Store(Zero, PARM) + Return(SUCC) // Not supported, but no failure + } + + // Display Power State: Sub-function 8 + + If (LEqual(GESF, 8)) + { + // + // Handle Low Power S0 Idle Capability if enabled + // + If(LEqual(S0ID, One)){ + // Bits [15:8] - Power State + // 00h = On + // 01h = Standby + // 02h = Suspend + // 04h = Off + // 08h = Reduced On + Store(And(ShiftRight(PARM, 8), 0xFF), Local0) + // + // Call GUAM + // If Display Turn ON Notification (PARM [15:8] == 0) for CS Exit + // + If (LEqual (Local0, 0)) { + // GUAM - Global User Absent Mode Notification Method + \GUAM(Zero) // 0x00 - Power State On (CS Exit) + } + } + Store(Zero, GESF) // Clear the exit parameter + Store(Zero, PARM) + Return(SUCC) // Not supported, but no failure + } + + // Set Boot Display: Sub-function 9 + + If (LEqual(GESF, 9)) + { + + //<TODO> An OEM may elect to implement this method. In that case, + // the input values must be saved into non-volatile storage for + // parsing during the next boot. The following Sample code is Intel + // validated implementation. + + And(PARM, 0xFF, IBTT) // Save the boot display to NVS + Store(Zero, GESF) // Clear the exit parameter + Store(Zero, PARM) + Return(SUCC) // Reserved, "Critical failure" + } + + // Set Panel Details: Sub-function 10 (0Ah) + + If (LEqual(GESF, 10)) + { + + //<TODO> An OEM may elect to implement this method. In that case, + // the input values must be saved into non-volatile storage for + // parsing during the next boot. The following Sample code is Intel + // validated implementation. + + // Set the panel-related NVRAM variables based the input from the driver. + + And(PARM, 0xFF, IPSC) + + // Change panel type if a change is requested by the driver (Change if + // panel type input is non-zero). Zero=No change requested. + + If(And(ShiftRight(PARM, 8), 0xFF)) + { + And(ShiftRight(PARM, 8), 0xFF, IPAT) + Decrement(IPAT) // 0 = no change, so fit to CMOS map + } + And(ShiftRight(PARM, 20), 0x7, IBIA) + Store(Zero, GESF) // Clear the exit parameter + Store(Zero, PARM) + Return(SUCC) // Success + } + + // Set Internal Graphics: Sub-function 11 (0Bh) + + If (LEqual(GESF, 11)) + { + + //<TODO> An OEM may elect to implement this method. In that case, + // the input values must be saved into non-volatile storage for + // parsing during the next boot. The following Sample code is Intel + // validated implementation. + + And(ShiftRight(PARM, 1), 1, IF1E) // Program the function 1 option + + If(And(PARM, ShiftLeft(0xF, 13))) // Use fixed memory if fixed size != 0 + { + + // Fixed memory + + And(ShiftRight(PARM, 13), 0xF, IDMS) // Program fixed memory size + } + Else + { + + // DVMT memory + + And(ShiftRight(PARM, 17), 0xF, IDMS) // Program fixed memory size + } + Store(Zero, GESF) // Clear the exit parameter + Store(Zero, PARM) + Return(SUCC) // Success + } + + // Post-Hires to DOS FS: Sub-function 16 (10h) + + If (LEqual(GESF, 16)) + { + Store(Zero, GESF) // Clear the exit parameter + Store(Zero, PARM) + Return(SUCC) // Not supported, but no failure + } + + // APM Complete: Sub-function 17 (11h) + + If (LEqual(GESF, 17)) + { + + Store(ShiftLeft(LIDS, 8), PARM) // Report the lid state + Add(PARM, 0x100, PARM) // Adjust the lid state, 0 = Unknown + + Store(Zero, GESF) // Clear the exit parameter + Return(SUCC) // Not supported, but no failure + } + + // Set Spread Spectrum Clocks: Sub-function 18 (12h) + + If (LEqual(GESF, 18)) + { + + //<TODO> An OEM may elect to implement this method. In that case, + // the input values must be saved into non-volatile storage for + // parsing during the next boot. The following Sample code is Intel + // validated implementation. + + If(And(PARM, 1)) + { + If(LEqual(ShiftRight(PARM, 1), 1)) + { + Store(1, ISSC) // Enable HW SSC, only for clock 1 + } + Else + { + Store(Zero, GESF) + Return(CRIT) // Failure, as the SSC clock must be 1 + } + } + Else + { + Store(0, ISSC) // Disable SSC + } + Store(Zero, GESF) // Clear the exit parameter + Store(Zero, PARM) + Return(SUCC) // Success + } + + // Post VBE/PM Callback: Sub-function 19 (13h) + + If (LEqual(GESF, 19)) + { + Store(Zero, GESF) // Clear the exit parameter + Store(Zero, PARM) + Return(SUCC) // Not supported, but no failure + } + + // Set PAVP Data: Sub-function 20 (14h) + + If (LEqual(GESF, 20)) + { + And(PARM, 0xF, PAVP) // Store PAVP info + Store(Zero, GESF) // Clear the exit parameter + Store(Zero, PARM) + Return(SUCC) // Success + } + + // Enable/Disable Audio: Sub-function 21 (15h) + + If (LEqual(GESF, 21)) + { + If(LEqual(PARM,1)) + { + OR (\_SB.PCI0.AUDE, 0x20,\_SB.PCI0.AUDE) + \_SB.PCI0.B0D3.ABWA (1) + \_SB.PCI0.B0D3.ARST () + \_SB.PCI0.B0D3.ASTR () + \_SB.PCI0.B0D3.AINI () + \_SB.PCI0.B0D3.CXDC () + \_SB.PCI0.B0D3.ABWA (0) + Notify(\_SB.PCI0,0) + } + If(LEqual(PARM,0)) + { + AND (\_SB.PCI0.AUDE, 0xDF,\_SB.PCI0.AUDE) + Notify(\_SB.PCI0,0) + } + Store(Zero, GESF) + Store(Zero, PARM) + Return(SUCC) + } + + // A call to a reserved "System BIOS callbacks" function was received + + Store(Zero, GESF) // Clear the exit parameter + Return(SUCC) // Reserved, "Critical failure" +} diff --git a/ReferenceCode/Chipset/SystemAgent/AcpiTables/SaSsdt/IgdOpRn.ASL b/ReferenceCode/Chipset/SystemAgent/AcpiTables/SaSsdt/IgdOpRn.ASL new file mode 100644 index 0000000..56d3f71 --- /dev/null +++ b/ReferenceCode/Chipset/SystemAgent/AcpiTables/SaSsdt/IgdOpRn.ASL @@ -0,0 +1,342 @@ +/*++ + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +--*/ + +/*++ + +Copyright (c) 1999 - 2013 Intel Corporation. All rights reserved +This software and associated documentation (if any) is furnished +under a license and may only be used or copied in accordance +with the terms of the license. Except as permitted by such +license, no part of this software or documentation may be +reproduced, stored in a retrieval system, or transmitted in any +form or by any means without the express written consent of +Intel Corporation. + + +Module Name: + + IgdOpRn.ASL + +Abstract: + + IGD OpRegion/Software SCI Reference Code. + This file contains the interrupt handler code for the Integrated + Graphics Device (IGD) OpRegion/Software SCI mechanism. + +--*/ + + +//NOTES: +// +// (1) The code contained in this file inherits the scope in which it +// was included. So BIOS developers must be sure to include this +// file in the scope associated with the graphics device +// (ex. \_SB.PCI0.GFX0). +// (2) Create a _L06 method under the GPE scope to handle the event +// generated by the graphics driver. The _L06 method must call +// the GSCI method in this file. +// (3) The MCHP operation region assumes that _ADR and _BBN names +// corresponding to bus 0, device0, function 0 have been declared +// under the PCI0 scope. +// (4) Before the first execution of the GSCI method, the base address +// of the GMCH SCI OpRegion must be programmed where the driver can +// access it. A 32bit scratch register at 0xFC in the IGD PCI +// configuration space (B0/D2/F0/R0FCh) is used for this purpose. + +// Define an OperationRegion to cover the GMCH PCI configuration space as +// described in the IGD OpRegion specificiation. + +Scope(\_SB.PCI0) +{ + OperationRegion(MCHP, PCI_Config, 0x40, 0xC0) + Field(MCHP, AnyAcc, NoLock, Preserve) + { + Offset(0x14), + AUDE, 8, + + Offset(0x60), // Top of Memory register + TASM, 10, // Total system memory (64MB gran) + , 6, + } +} + +// Define an OperationRegion to cover the IGD PCI configuration space as +// described in the IGD OpRegion specificiation. + +OperationRegion(IGDP, PCI_Config, 0x40, 0xC0) +Field(IGDP, AnyAcc, NoLock, Preserve) +{ + Offset(0x12), // Mirror of gfx control reg + , 1, + GIVD, 1, // IGD VGA disable bit + , 2, + GUMA, 3, // Stolen memory size + , 9, + Offset(0x14), + , 4, + GMFN, 1, // Gfx function 1 enable + , 27, + Offset(0xA4), + ASLE, 8, // Reg 0xE4, ASLE interrupt register + , 24, // Only use first byte of ASLE reg + Offset(0xA8), // Reg 0xE8, SWSCI control register + GSSE, 1, // Graphics SCI event (1=event pending) + GSSB, 14, // Graphics SCI scratchpad bits + GSES, 1, // Graphics event select (1=SCI) + Offset(0xB0), // Gfx Clk Frequency and Gating Control + , 12, + CDVL, 1, // Core display clock value + , 3, // Graphics Core Display Clock Select + Offset(0xB5), + LBPC, 8, // Legacy brightness control + Offset(0xBC), + ASLS, 32, // Reg 0xFC, Address of the IGD OpRegion +} + +// Define an OperationRegion to cover the IGD OpRegion layout. + +OperationRegion(IGDM, SystemMemory, ASLB, 0x2000) +Field(IGDM, AnyAcc, NoLock, Preserve) +{ + + // OpRegion Header + + SIGN, 128, // Signature-"IntelGraphicsMem" + SIZE, 32, // OpRegion Size + OVER, 32, // OpRegion Version + SVER, 256, // System BIOS Version + VVER, 128, // VBIOS Version + GVER, 128, // Driver version + MBOX, 32, // Mailboxes supported + DMOD, 32, // Driver Model + PCON, 32, // Platform Configuration + DVER, 64, // GOP Version + // OpRegion Mailbox 1 (Public ACPI Methods) + // Note: Mailbox 1 is normally reserved for desktop platforms. + + Offset(0x100), + DRDY, 32, // Driver readiness (ACPI notification) + CSTS, 32, // Notification status + CEVT, 32, // Current event + Offset(0x120), + DIDL, 32, // Supported display device ID list + DDL2, 32, // Allows for 8 devices + DDL3, 32, + DDL4, 32, + DDL5, 32, + DDL6, 32, + DDL7, 32, + DDL8, 32, + CPDL, 32, // Currently present display list + CPL2, 32, // Allows for 8 devices + CPL3, 32, + CPL4, 32, + CPL5, 32, + CPL6, 32, + CPL7, 32, + CPL8, 32, + CADL, 32, // Currently active display list + CAL2, 32, // Allows for 8 devices + CAL3, 32, + CAL4, 32, + CAL5, 32, + CAL6, 32, + CAL7, 32, + CAL8, 32, + NADL, 32, // Next active display list + NDL2, 32, // Allows for 8 devices + NDL3, 32, + NDL4, 32, + NDL5, 32, + NDL6, 32, + NDL7, 32, + NDL8, 32, + ASLP, 32, // ASL sleep timeout + TIDX, 32, // Toggle table index + CHPD, 32, // Current hot plug enable indicator + CLID, 32, // Current lid state indicator + CDCK, 32, // Current docking state indicator + SXSW, 32, // Display switch notify on resume + EVTS, 32, // Events supported by ASL (diag only) + CNOT, 32, // Current OS notifications (diag only) + NRDY, 32, + // Extended DIDL list + DDL9, 32, + DD10, 32, + DD11, 32, + DD12, 32, + DD13, 32, + DD14, 32, + DD15, 32, + //Extended Currently attached Display Device List CPD2 + CPL9, 32, + CP10, 32, + CP11, 32, + CP12, 32, + CP13, 32, + CP14, 32, + CP15, 32, + // OpRegion Mailbox 2 (Software SCI Interface) + + Offset(0x200), // SCIC + SCIE, 1, // SCI entry bit (1=call unserviced) + GEFC, 4, // Entry function code + GXFC, 3, // Exit result + GESF, 8, // Entry/exit sub-function/parameter + , 16, // SCIC[31:16] reserved + Offset(0x204), // PARM + PARM, 32, // PARM register (extra parameters) + DSLP, 32, // Driver sleep time out + + // OpRegion Mailbox 3 (BIOS to Driver Notification) + // Note: Mailbox 3 is normally reserved for desktop platforms. + + Offset(0x300), + ARDY, 32, // Driver readiness (power conservation) + ASLC, 32, // ASLE interrupt command/status + TCHE, 32, // Technology enabled indicator + ALSI, 32, // Current ALS illuminance reading + BCLP, 32, // Backlight brightness + PFIT, 32, // Panel fitting state or request + CBLV, 32, // Current brightness level + BCLM, 320, // Backlight brightness level duty cycle mapping table + CPFM, 32, // Current panel fitting mode + EPFM, 32, // Enabled panel fitting modes + PLUT, 592, // Optional. 74-byte Panel LUT Table + PFMB, 32, // Optional. PWM Frequency and Minimum Brightness + CCDV, 32, // Optional. Gamma, Brightness, Contrast values. + PCFT, 32, // Optional. Power Conservation Features + SROT, 32, // Supported rotation angle. + IUER, 32, // Optional. Intel Ultrabook Event Register. + FDSP, 64, // Optional. FFS Display Physical address + FDSS, 32, // Optional. FFS Display Size + STAT, 32, // State Indicator + + // OpRegion Mailbox 4 (VBT) + + Offset(0x400), + GVD1, 0xC000, // 6K bytes maximum VBT image + + // OpRegion Mailbox 5 (BIOS to Driver Notification Extension) + + Offset(0x1C00), + PHED, 32, // Panel Header + BDDC, 2048, // Panel EDID (Max 256 bytes) + +} + +// Define an OperationRegion to cover the ICH TCO I/O space region for use in +// clearing the MCH SCI status bit. + +/* Defined already by main ASL code, but shown below for reference. + +OperationRegion(TCOI,SystemIO,0x1060,0x8) +Field(TCOI,WordAcc, NoLock, Preserve) +{ + Offset(0x04), // TCO status register + , 9, + SCIS, 1, // TCO DMI SCI status + , 6, +}*/ + +// Convert boot display type into a port mask. + +Name (DBTB, Package() +{ + 0x0000, // Automatic + 0x0007, // Port-0 : Integrated CRT + 0x0038, // Port-1 : DVO-A, or Integrated LVDS + 0x01C0, // Port-2 : SDVO-B, or SDVO-B/C + 0x0E00, // Port-3 : SDVO-C + 0x003F, // [CRT + DVO-A / Integrated LVDS] + 0x01C7, // [CRT + SDVO-B] or [CRT + SDVO-B/C] + 0x0E07, // [CRT + SDVO-C] + 0x01F8, // [DVO-A / Integrated LVDS + SDVO-B] + 0x0E38, // [DVO-A / Integrated LVDS + SDVO-C] + 0x0FC0, // [SDVO-B + SDVO-C] + 0x0000, // Reserved + 0x0000, // Reserved + 0x0000, // Reserved + 0x0000, // Reserved + 0x0000, // Reserved + 0x7000, // Port-4: Integrated TV + 0x7007, // [Integrated TV + CRT] + 0x7038, // [Integrated TV + LVDS] + 0x71C0, // [Integrated TV + DVOB] + 0x7E00 // [Integrated TV + DVOC] +}) + +// Core display clock value table. + +Name (CDCT, Package() +{ + Package() {228, 320}, + Package() {222, 333}, + Package() {222, 333}, + Package() { 0, 0}, + Package() {222, 333}, +}) + +// Defined exit result values: + +Name (SUCC, 1) // Exit result: Success +Name (NVLD, 2) // Exit result: Invalid parameter +Name (CRIT, 4) // Exit result: Critical failure +Name (NCRT, 6) // Exit result: Non-critical failure + + +/************************************************************************; +;* +;* Name: GSCI +;* +;* Description: Handles an SCI generated by the graphics driver. The +;* PARM and SCIC input fields are parsed to determine the +;* functionality requested by the driver. GBDA or SBCB +;* is called based on the input data in SCIC. +;* +;* Usage: The method must be called in response to a GPE 06 event +;* which will be generated by the graphics driver. +;* Ex: Method(\_GPE._L06) {Return(\_SB.PCI0.GFX0.GSCI())} +;* +;* Input: PARM and SCIC are indirect inputs +;* +;* Output: PARM and SIC are indirect outputs +;* +;* References: GBDA (Get BIOS Data method), SBCB (System BIOS Callback +;* method) +;* +;************************************************************************/ + +Method (GSCI, 0, Serialized) +{ + Include("IgdOGbda.asl") // "Get BIOS Data" Functions + Include("IgdOSbcb.asl") // "System BIOS CallBacks" + + If (LEqual(GEFC, 4)) + { + Store(GBDA(), GXFC) // Process Get BIOS Data functions + } + + If (LEqual(GEFC, 6)) + { + Store(SBCB(), GXFC) // Process BIOS Callback functions + } + + Store(0, GEFC) // Wipe out the entry function code + Store(1, SCIS) // Clear the MCH SCI status bit in ICH TCO I/O space. + Store(0, GSSE) // Clear the SCI generation bit in PCI space. + Store(0, SCIE) // Clr SCI serviced bit to signal completion + + Return(Zero) +} + +// Include MOBLFEAT.ASL for mobile systems only. Remove for desktop. + +Include("IgdOMobF.asl") // IGD SCI mobile features + diff --git a/ReferenceCode/Chipset/SystemAgent/AcpiTables/SaSsdt/Sa.asl b/ReferenceCode/Chipset/SystemAgent/AcpiTables/SaSsdt/Sa.asl new file mode 100644 index 0000000..a8f4ee0 --- /dev/null +++ b/ReferenceCode/Chipset/SystemAgent/AcpiTables/SaSsdt/Sa.asl @@ -0,0 +1,495 @@ +/*++ + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +--*/ + +/*++ + +Copyright (c) 1999 - 2013 Intel Corporation. All rights reserved +This software and associated documentation (if any) is furnished +under a license and may only be used or copied in accordance +with the terms of the license. Except as permitted by such +license, no part of this software or documentation may be +reproduced, stored in a retrieval system, or transmitted in any +form or by any means without the express written consent of +Intel Corporation. + + +Module Name: + + Sa.ASL + +Abstract: + + Devices definition of SystemAgent ACPI reference code. + +--*/ +//AMI_OVERRIDE -->> +#if !defined(ASL_Remove_SaSsdt_Data_To_Dsdt) || (ASL_Remove_SaSsdt_Data_To_Dsdt == 0) +#if defined(ASL_RC_PEG_0) && (ASL_RC_PEG_0 == 1) +External(AR02) +External(PR02) +#endif +#if defined(ASL_RC_PEG_1) && (ASL_RC_PEG_1 == 1) +External(AR0A) +External(PR0A) +#endif +#if defined(ASL_RC_PEG_2) && (ASL_RC_PEG_2 == 1) +External(AR0B) +External(PR0B) +#endif +External(PICM) +External(\GPRW, MethodObj) +External(\_SB.PCI0, DeviceObj) +#endif +//AMI_OVERRIDE --<< + +Scope (\_SB.PCI0) { + Name(LTRS, 0) + Name(OBFS, 0) +//AMI_OVERRIDE -->> +#if defined(ASL_RC_PEG_0) && (ASL_RC_PEG_0 == 1) + Device(PEG0) { // P.E.G. Root Port D1F0 + Name(_ADR, 0x00010000) + OperationRegion(PEGR,PCI_Config,0xC0,0x30) + Field(PEGR,DWordAcc,NoLock,Preserve) + { + ,16, + PSTS, 1, // PME Status + offset (44), + GENG, 1, // General Message GPE Enable + ,1, // Reserved + PMEG, 1, // PME GPE Enable + } + Method(_PRW, 0) { Return(GPRW(0x09, 4)) } // can wakeup from S4 state + + Method(_PSW,1) + { + If(Arg0) + { + Store(1,GENG) + Store(1,PMEG) + } + Else + { + Store(0,GENG) + Store(0,PMEG) + } + } + Method(HPME,0,Serialized) + { + // + // Clear PME status bit + // + Store(1,PSTS) + } + Method(_PRT,0) { + If(PICM) { Return(AR02) }// APIC mode + Return (PR02) // PIC Mode + } // end _PRT + // + // Pass LTRx to LTRS so SaPcieDsm.asl can be reused for PEGs. + // + Method(_INI) + { + Store (LTRA, LTRS) + Store (OBFA, OBFS) + } + include("SaPcieDsm.ASL") + + Device(PEGP) { // P.E.G. Port Slot x16 + Name(_ADR, 0x00000000) + Method(_PRW, 0) { Return(GPRW(0x09, 4)) } // can wakeup from S4 state + } // end "P.E.G. Port Slot x16" + + } // end "P.E.G. Root Port D1F0" +#endif +#if defined(ASL_RC_PEG_1) && (ASL_RC_PEG_1 == 1) + Device(PEG1) { // P.E.G. Root Port D1F1 + Name(_ADR, 0x00010001) + OperationRegion(PEGR,PCI_Config,0xC0,0x30) + Field(PEGR,DWordAcc,NoLock,Preserve) + { + ,16, + PSTS, 1, // PME Status + offset (44), + GENG, 1, // General Message GPE Enable + ,1, // Reserved + PMEG, 1, // PME GPE Enable + } + Method(_PRW, 0) { Return(GPRW(0x09, 4)) } // can wakeup from S4 state + + Method(_PSW,1) + { + If(Arg0) + { + Store(1,GENG) + Store(1,PMEG) + } + Else + { + Store(0,GENG) + Store(0,PMEG) + } + } + Method(HPME,0,Serialized) + { + // + // Clear PME status bit + // + Store(1,PSTS) + } + Method(_PRT,0) { + If(PICM) { Return(AR0A) }// APIC mode + Return (PR0A) // PIC Mode + } // end _PRT + + Method(_INI) + { + Store (LTRB, LTRS) + Store (OBFB, OBFS) + } + include("SaPcieDsm.ASL") + } // end "P.E.G. Root Port D1F1" +#endif +#if defined(ASL_RC_PEG_2) && (ASL_RC_PEG_2 == 1) + Device(PEG2) { // P.E.G. Root Port D1F2 + Name(_ADR, 0x00010002) + OperationRegion(PEGR,PCI_Config,0xC0,0x30) + Field(PEGR,DWordAcc,NoLock,Preserve) + { + ,16, + PSTS, 1, // PME Status + offset (44), + GENG, 1, // General Message GPE Enable + ,1, // Reserved + PMEG, 1, // PME GPE Enable + } + Method(_PRW, 0) { Return(GPRW(0x09, 4)) } // can wakeup from S4 state + + Method(_PSW,1) + { + If(Arg0) + { + Store(1,GENG) + Store(1,PMEG) + } + Else + { + Store(0,GENG) + Store(0,PMEG) + } + } + Method(HPME,0,Serialized) + { + // + // Clear PME status bit + // + Store(1,PSTS) + } + Method(_PRT,0) { + If(PICM) { Return(AR0B) }// APIC mode + Return (PR0B) // PIC Mode + } // end _PRT + + Method(_INI) + { + Store (LTRC, LTRS) + Store (OBFC, OBFS) + } + include("SaPcieDsm.ASL") + } // end "P.E.G. Root Port D1F2" +#endif +//AMI_OVERRIDE --<< + Device(B0D3) { // SA Audio Device + Name(_ADR, 0x00030000) + Name (BARA, 0x80000000) + Name (TBAR, 0x0) + Name (TCMD, 0x0) + Name (MODB, 0x0) + Name (MODC, 0x0) + + Method(_STA,0) + { + If(LNotEqual(AUVD, 0xFFFF)) + { + Return(0xF) // then enabled + } + Return(0) // then disabled + } + + Method(_INI) { + // + // Save a valid Audio BAR for the ABWA W/A + // + If (LAnd (LNotEqual (And(ABAR, 0xFFFFC004), 0xFFFFC004), LNotEqual (And (ABAR, 0xFFFFC000), 0))) { + Store (ABAR, BARA) + } + } + + OperationRegion(RPCS,SystemMemory,\XBAS,0x18040) + Field(RPCS,AnyAcc,NoLock,Preserve) + { + Offset (0x18004), + ACMD, 8, + Offset (0x18010), + ABAR, 32, + } + + OperationRegion(RPCZ,PCI_Config,0x00,0x40) + Field(RPCZ,DWordAcc,Lock,Preserve) + { + AUVD, 16, + } + + /// + /// Restore Audio WAs + /// + Method (ASTR, 0, Serialized) { + + If (LAnd (LNotEqual (And(ABAR, 0xFFFFC004), 0xFFFFC004), LNotEqual (And (ABAR, 0xFFFFC000), 0))) { + And (ABAR, 0xFFFFFFF0, BBAR) + Add (BBAR, 0x1000, BBAR) + OperationRegion(RPCY,SystemMemory,BBAR, 0x25) + Field(RPCY,DWordAcc,NoLock,Preserve) + { + Offset(0xC), + EM4W, 32, + Offset(0x10), + EMWA, 32, + Offset(0x1C), + ADWA, 32, + } + + Store(AUDA, EMWA) + Store(AUDB, ADWA) + Store(AUDC, EM4W) + } + + } + + /// + /// Send the command to the codec via the Immediate Command + /// + Method (VSTR, 1, Serialized) { + + Name (CONT, 1000) + Name (ADDR, 0x80000000) + + Store (Arg0, ADDR) + OperationRegion(CCDC,SystemMemory,ADDR,4) + Field(CCDC,ByteAcc,NoLock,Preserve) + { + Offset(0x0), + CDEC, 32, + } + + If (LAnd (LNotEqual (And(ABAR, 0xFFFFC004), 0xFFFFC004), LNotEqual (And (ABAR, 0xFFFFC000), 0))) { + If (LNotEqual (CDEC, 0)) { + And (ABAR, 0xFFFFFFF0, BBAR) + + OperationRegion(IPCV,SystemMemory,BBAR,0x70) + Field(IPCV,DWordAcc,NoLock,Preserve) + { + Offset(0x60), + AVIC, 32, + Offset(0x68), + AIRS, 16, + } + + Store (1000, CONT) + While (LAnd (LEqual(And(AIRS, 0x1), 1), LNotEqual(CONT,0))) + { + Stall(1) + Decrement(CONT) + } + Or (AIRS, 2, AIRS) + Store (CDEC, AVIC) + Or (AIRS, 1, AIRS) + + Store (1000, CONT) + While (LAnd (LEqual(And(AIRS, 0x1), 1), LNotEqual(CONT,0))) + { + Stall(1) + Decrement(CONT) + } + } + } + } + + /// + /// Restore Verb Table + /// + Method (CXDC, 0, Serialized) + { + Name(IDDX, 0x80000000) +//AMI_OVERRIDE --- Change name from CADR to CCSA to fix that the system has BsOD issue. It is due to the name(CADR) is conflict with AMI Aptio definition name. >> + If (LAnd (LNotEqual (CCSA, 0), LNotEqual (CCNT, 0))) { + Store (CCSA, IDDX) + While (LLess (IDDX, Add (CCSA, Multiply (CCNT, 4)))) +// If (LAnd (LNotEqual (CADR, 0), LNotEqual (CCNT, 0))) { +// Store (CADR, IDDX) +// While (LLess (IDDX, Add (CADR, Multiply (CCNT, 4)))) +//AMI_OVERRIDE --- << + { + VSTR (IDDX) + Add (IDDX, 4, IDDX) + } + } + } + + /// + /// Reset Audio Controller + /// + Method (ARST, 0, Serialized) + { + If (LAnd (LNotEqual (And(ABAR, 0xFFFFC004), 0xFFFFC004), LNotEqual (And (ABAR, 0xFFFFC000), 0))) { + And (ABAR, 0xFFFFFFF0, BBAR) + OperationRegion(IPCV,SystemMemory,BBAR,0xBF) + Field(IPCV,AnyAcc,NoLock,Preserve) + { + Offset(0x08), + CRST, 32, + Offset(0x4C), + CORB, 32, + Offset(0x5C), + RIRB, 32, + Offset(0x80), + OSD1, 32, + Offset(0xA0), + OSD2, 32, + } + AND (CORB, 0xFFFFFFFD, CORB) + AND (RIRB, 0xFFFFFFFD, RIRB) + AND (OSD1, 0xFFFFFFFD, OSD1) + AND (OSD2, 0xFFFFFFFD, OSD2) + AND (CRST, 0xFFFFFFFE, CRST) + } + } + + /// + /// Codec Initialization Programming Sequence + /// + Method (AINI, 0, Serialized) + { + Name (CONT, 1000) + + If (LAnd (LNotEqual (And(ABAR, 0xFFFFC004), 0xFFFFC004), LNotEqual (And (ABAR, 0xFFFFC000), 0))) { + And (ABAR, 0xFFFFFFF0, BBAR) + + OperationRegion(IPCV,SystemMemory,BBAR,0x70) + Field(IPCV,DWordAcc,NoLock,Preserve) + { + Offset(0x0), + GCAP, 16, + Offset(0x08), + GCTL, 32, + Offset(0x0E), + SSTS, 8, + Offset(0x60), + AVIC, 32, + Offset(0x68), + AIRS, 16, + } + + /// + /// Step1/2:Reset Controller and wait for reset complete + /// + Or (GCTL, 1, GCTL) + Store (1000, CONT) + While (LAnd (LEqual (And (GCTL , 1), 0), LNotEqual (CONT, 0))) + { + Stall (1) + Decrement (CONT) + } + + /// + /// Step3: + /// Read GCAP and write the same value back to + /// the register once after Controller Reset# bit is set + /// + And (GCAP, 0xFFFF, GCAP) + + /// + /// Step4: + /// Clear the "State Change Status Register" STATESTS bits for + /// each of the "SDIN Stat Change Status Flag" + /// + Or (SSTS, 0xF, SSTS) + + /// + /// Step5: + /// Turn off the link and poll RESET# bit until it reads back + /// as 0 to get hardware reset report + /// + And (GCTL, 0xFFFFFFFE, GCTL) + + Store (1000, CONT) + While (LAnd (LEqual(And(GCTL,1), 1), LNotEqual(CONT,0))) + { + Stall (1) + Decrement (CONT) + } + + /// + /// Step6: + /// Turn on the link and poll RESET# bit until it reads back as 1 + /// + Or (GCTL, 1, GCTL) + Store (1000, CONT) + While (LAnd (LEqual(And(GCTL,1), 0), LNotEqual(CONT,0))) + { + Stall (1) + Decrement (CONT) + } + } + } + /// + /// W/A for Audio CdClk restore issue with HDMI hotplug after S3/S4 resume + /// Store ABAR temporarily and restore it at the end of Call Back SF 21h + /// + Method (ABWA, 1, Serialized) + { + If (Arg0) { + If (LOr (LEqual (And(ABAR, 0xFFFFC004), 0xFFFFC004), LEqual (And (ABAR, 0xFFFFC000), 0))) { + /// + /// if Audio BAR does not have a valid value + /// + If (LNotEqual (BARA, 0x80000000)) { // but a vaid value has been saved by the _INI or _WAK earlier + Store (ABAR, TBAR) // temporarily assign Audio Bar to restore mmio registers + Store (ACMD, TCMD) + Store (BARA, ABAR) + Store (0x06, ACMD) + Store (0x01, MODB) + } + } Else { // Audio BAR has a valid value + If (LNotEqual (And (ACMD, 0x06), 0x06)) { // but CMD register is not set to allow writes to mmio registers + Store (ACMD, TCMD) // temporarily set CMD register to allow mmio writes + Store (0x06, ACMD) + Store (0x01, MODC) + } + } + } Else { // Restore the original Audio Bar and Cmd Register + If (MODB) { + If(LEqual(ABAR, BARA)) { + Store (TBAR, ABAR) + Store (TCMD, ACMD) + } + } + If (MODC) { // Restore only the Cmd Register + Store (TCMD, ACMD) + } + } + } + } // end "SA Audio Device" + + Device(GFX0) { // I.G.D + Name(_ADR, 0x00020000) + include("IntelGfx.ASL") + } // end I.G.D + +} diff --git a/ReferenceCode/Chipset/SystemAgent/AcpiTables/SaSsdt/SaPcieDsm.asl b/ReferenceCode/Chipset/SystemAgent/AcpiTables/SaSsdt/SaPcieDsm.asl new file mode 100644 index 0000000..613138c --- /dev/null +++ b/ReferenceCode/Chipset/SystemAgent/AcpiTables/SaSsdt/SaPcieDsm.asl @@ -0,0 +1,119 @@ +/**************************************************************************; +;* *; +;* Intel Confidential *; +;* *; +;* Intel Corporation - ACPI Reference Code for the Haswell *; +;* Family of Customer Reference Boards. *; +;* *; +;* *; +;* Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved *; +;* This software and associated documentation (if any) is furnished *; +;* under a license and may only be used or copied in accordance *; +;* with the terms of the license. Except as permitted by such *; +;* license, no part of this software or documentation may be *; +;* reproduced, stored in a retrieval system, or transmitted in any *; +;* form or by any means without the express written consent of *; +;* Intel Corporation. *; +;* *; +;* *; +;**************************************************************************/ +/*++ + This file contains an 'Intel Peripheral Driver' and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +--*/ + + Name(LTRV, Package(){0,0,0,0}) + Name(OPTS, 0) // SA SETUP options for LTR and OBFF + + // + // _DSM Device Specific Method + // + // Arg0: UUID Unique function identifier + // Arg1: Integer Revision Level + // Arg2: Integer Function Index (0 = Return Supported Functions) + // Arg3: Package Parameters + Method(_DSM, 4, Serialized) { + // + // Switch based on which unique function identifier was passed in + // + Switch(ToInteger(Arg0)) { + // + // _DSM Definitions for Latency Tolerance Reporting + // + // Arguments: + // Arg0: UUID: E5C937D0-3553-4d7a-9117-EA4D19C3434D + // Arg1: Revision ID: 2 + // Arg2: Function Index: 6 + // Arg3: Empty Package + // + // Return: + // A Package of four integers corresponding with the LTR encoding defined + // in the PCI Express Base Specification, as follows: + // Integer 0: Maximum Snoop Latency Scale + // Integer 1: Maximum Snoop Latency Value + // Integer 2: Maximum No-Snoop Latency Scale + // Integer 3: Maximum No-Snoop Latency Value + // These values correspond directly to the LTR Extended Capability Structure + // fields described in the PCI Express Base Specification. + // + Case(ToUUID("E5C937D0-3553-4d7a-9117-EA4D19C3434D")) { + // + // Switch by function index + // + Switch(ToInteger(Arg2)) { + // + // Function Index:0 + // Standard query - A bitmask of functions supported + // + Case (0) + { + if (LEqual(Arg1, 2)){ // test Arg1 for Revision ID: 2 + Store(1, OPTS) // function 0 + if (LTRS){ + Or(OPTS,0x40,OPTS) // function 6 + } + if (OBFS){ + Or(OPTS,0x10,OPTS) // function 4 + } + Return (OPTS) // bitmask of supported functions: 6, 4, 0. + } else { + Return (0) + } + } + // + // Function Index: 4 + // + Case(4) { + if (LEqual(Arg1, 2)){ // test Arg1 for Revision ID: 2 + if (OBFS){ + Return (Buffer () {0,0,0,0,0,0,0,0,0,0,0,8,0,0,0,0}) // OBFF capable, offset 4[08h] + } else { + Return (Buffer () {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}) + } + } + } + // + // Function Index: 6 + // LTR Extended Capability Structure + // + Case(6) { + if (LEqual(Arg1, 2)){ // test Arg1 for Revision ID: 2 + if (LTRS){ + Store(And(ShiftRight(SMSL,10),7), Index(LTRV, 0)) + Store(And(SMSL,0x3FF), Index(LTRV, 1)) + Store(And(ShiftRight(SNSL,10),7), Index(LTRV, 2)) + Store(And(SNSL,0x3FF), Index(LTRV, 3)) + return (LTRV) + } else { + Return (0) + } + } + } + } // End of switch(Arg2) + } // End of case(ToUUID("E5C937D0-3553-4d7a-9117-EA4D19C3434D")) + } // End of switch(Arg0) + return (Buffer() {0x00}) + } // End of _DSM diff --git a/ReferenceCode/Chipset/SystemAgent/AcpiTables/SaSsdt/SaSsdt.asl b/ReferenceCode/Chipset/SystemAgent/AcpiTables/SaSsdt/SaSsdt.asl new file mode 100644 index 0000000..0650178 --- /dev/null +++ b/ReferenceCode/Chipset/SystemAgent/AcpiTables/SaSsdt/SaSsdt.asl @@ -0,0 +1,172 @@ +/*++ + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +--*/ + +/*++ + +Copyright (c) 2012 - 2013 Intel Corporation. All rights reserved +This software and associated documentation (if any) is furnished +under a license and may only be used or copied in accordance +with the terms of the license. Except as permitted by such +license, no part of this software or documentation may be +reproduced, stored in a retrieval system, or transmitted in any +form or by any means without the express written consent of +Intel Corporation. + +Module Name: + + SaSsdt.asl + +Abstract: + + SA SSDT Table ASL code + +--*/ + + +DefinitionBlock ( + "SaSsdt.aml", + "SSDT", + 0x01, + "SaSsdt", + "SaSsdt ", + 0x3000 + ) +{ + + OperationRegion(SANV,SystemMemory,0xFFFF0000,0xAA55) + Field(SANV,AnyAcc,Lock,Preserve) + { + SARV, 32, /// (000) SA RC Revision + ASLB, 32, /// (004) IGD OpRegion base address + IMON, 8, /// (008) IMON Current Value + IGDS, 8, /// (009) IGD State (Primary Display = 1) + CADL, 8, /// (010) Current Attached Device List + PADL, 8, /// (011) Previous Attached Device List + CSTE, 16, /// (012) Current Display State + NSTE, 16, /// (014) Next Display State + DID9, 32, /// (016) Device Id 9 + DIDA, 32, /// (020) Device Id 10 + DIDB, 32, /// (024) Device Id 11 + IBTT, 8, /// (028) IGD Boot Display Device + IPAT, 8, /// (029) IGD Panel Type CMOs option + IPSC, 8, /// (030) IGD Panel Scaling + IBLC, 8, /// (031) IGD BLC Configuration + IBIA, 8, /// (032) IGD BIA Configuration + ISSC, 8, /// (033) IGD SSC Configuration + IPCF, 8, /// (034) IGD Power Conservation Feature Flag + IDMS, 8, /// (035) IGD DVMT Memory Size + IF1E, 8, /// (036) IGD Function 1 Enable + HVCO, 8, /// (037) HPLL VCO + NXD1, 32, /// (038) Next state DID1 for _DGS + NXD2, 32, /// (042) Next state DID2 for _DGS + NXD3, 32, /// (046) Next state DID3 for _DGS + NXD4, 32, /// (050) Next state DID4 for _DGS + NXD5, 32, /// (054) Next state DID5 for _DGS + NXD6, 32, /// (058) Next state DID6 for _DGS + NXD7, 32, /// (062) Next state DID7 for _DGS + NXD8, 32, /// (066) Next state DID8 for _DGS + GSMI, 8, /// (070) GMCH SMI/SCI mode (0=SCI) + PAVP, 8, /// (071) IGD PAVP data + LIDS, 8, /// (072) Lid State (Lid Open = 1) + KSV0, 32, /// (073) First four bytes of AKSV (mannufacturing mode) + KSV1, 8, /// (077) Fifth byte of AKSV (mannufacturing mode) + BBAR, 32, /// (078) IGFX Audio (D3F0) MMIO BAR Address + BLCS, 8, /// (082) Backlight Control Support + BRTL, 8, /// (083) Brightness Level Percentage + ALSE, 8, /// (084) ALS Enable + ALAF, 8, /// (085) Ambient Light Adjusment Factor + LLOW, 8, /// (086) LUX Low Value + LHIH, 8, /// (087) LUX High Value + ALFP, 8, /// (088) Active LFP + AUDA, 32, /// (089) Audio MMIO WA 1 + AUDB, 32, /// (093) Audio MMIO WA 2 + AUDC, 32, /// (097) Audio MMIO WA 3 + DIDC, 32, /// (101) Device Id 12 + DIDD, 32, /// (105) Device Id 13 + DIDE, 32, /// (109) Device Id 14 + DIDF, 32, /// (113) Device Id 15 +//AMI_OVERRIDE --- Change name from CADR to CCSA to fix that the system has BsOD issue. It is due to the name(CADR) is conflict with AMI Aptio definition name. >> + CCSA, 32, /// (117) Codec Save Address + CCNT, 32, /// (121) Codec Save Count +//CADR, 32, /// (117) Codec Save Address +//CCNT, 8, /// (121) Codec Save Count +//AMI_OVERRIDE --- << + /// + /// Switchable Graphics Info + /// + Offset(200), + SGMD, 8, /// (200) SG Mode (0=Disabled, 1=SG Muxed, 2=SG Muxless, 3=DGPU Only) + SGFL, 8, /// (201) SG Feature List + PWOK, 8, /// (202) dGPU PWROK GPIO assigned + HLRS, 8, /// (203) dGPU HLD RST GPIO assigned + PWEN, 8, /// (204) dGPU PWR Enable GPIO assigned + PRST, 8, /// (205) dGPU Present Detect GPIO assigned + CPSP, 32, /// (206) PEG Endpoint Capability Structure Presence (Bit 0: Virtual Channel Capability) + EECP, 8, /// (210) PEG Endpoint PCIe Capability Structure Offset + EVCP, 16, /// (211) PEG Endpoint Virtual Channel Capability Structure Offset + XBAS, 32, /// (213) Any Device's PCIe Config Space Base Address + GBAS, 16, /// (217) GPIO Base Address + SGGP, 8, /// (219) SG GPIO Support + NVGA, 32, /// (220) NVIG opregion address + NVHA, 32, /// (224) NVHM opregion address + AMDA, 32, /// (228) AMDA opregion address + NDID, 8, /// (232) Number of Valid Device IDs + DID1, 32, /// (233) Device ID 1 + DID2, 32, /// (237) Device ID 2 + DID3, 32, /// (241) Device ID 3 + DID4, 32, /// (245) Device ID 4 + DID5, 32, /// (249) Device ID 5 + DID6, 32, /// (253) Device ID 6 + DID7, 32, /// (257) Device ID 7 + DID8, 32, /// (261) Device ID 8 + OBS1, 32, /// (265) Occupied Buses - from 0 to 31 + OBS2, 32, /// (269) Occupied Buses - from 32 to 63 + OBS3, 32, /// (273) Occupied Buses - from 64 to 95 + OBS4, 32, /// (277) Occupied Buses - from 96 to 127 + OBS5, 32, /// (281) Occupied Buses - from 128 to 159 + OBS6, 32, /// (285) Occupied Buses - from 160 to 191 + OBS7, 32, /// (289) Occupied Buses - from 192 to 223 + OBS8, 32, /// (293) Occupied Buses - from 224 to 255 + LTRA, 8, /// (297) Latency Tolerance Reporting Enable + OBFA, 8, /// (298) Optimized Buffer Flush and Fill + LTRB, 8, /// (299) Latency Tolerance Reporting Enable + OBFB, 8, /// (300) Optimized Buffer Flush and Fill + LTRC, 8, /// (301) Latency Tolerance Reporting Enable + OBFC, 8, /// (302) Optimized Buffer Flush and Fill + SMSL, 16, /// (303) SA Peg Latency Tolerance Reporting Max Snoop Latency + SNSL, 16, /// (305) SA Peg Latency Tolerance Reporting Max No Snoop Latency + P0UB, 8, /// (307) Peg0 Unused Bundle Control + P1UB, 8, /// (308) Peg1 Unused Bundle Control + P2UB, 8, /// (309) Peg2 Unused Bundle Control + EDPV, 8, /// (310) Check for eDP display device + NXDX, 32, /// (311) Next state DID for eDP + DIDX, 32, /// (315) Device ID for eDP device + PCSL, 8, /// (319) The lowest C-state for the package + SC7A, 8, /// (316) Run-time C7 Allowed feature (0=Disabled, 1=Enabled) +// AMI_OVERRIDE... + DSEL, 8, /// (319) dGPU Display Select GPIO assigned + ESEL, 8, /// (320) dGPU EDID Select GPIO assigned + PSEL, 8, /// (321) dGPU PWM Select GPIO assigned + MXD1, 32, /// (322) DID1 Mux Setting + MXD2, 32, /// (326) DID2 Mux Setting + MXD3, 32, /// (330) DID3 Mux Setting + MXD4, 32, /// (334) DID4 Mux Setting + MXD5, 32, /// (338) DID5 Mux Setting + MXD6, 32, /// (342) DID6 Mux Setting + MXD7, 32, /// (346) DID7 Mux Setting + MXD8, 32, /// (350) DID8 Mux Setting + PXFD, 8, /// (354) ATI 5.0 Fixed/Dynamic ATI 5.0 Fixed/Dynamic + EBAS, 32, /// (355) Endpoint PCIe Base Address + HYSS, 32, /// (359) dGPU SSID for MSHyBrid restore +// AMI_OVERRIDE...end. + } +#if !defined(ASL_Remove_SaSsdt_Data_To_Dsdt) || (ASL_Remove_SaSsdt_Data_To_Dsdt == 0) + include ("Sa.asl") +#endif // AMI_OVERRIDE +}
\ No newline at end of file diff --git a/ReferenceCode/Chipset/SystemAgent/AcpiTables/SaSsdt/SaSsdt.inf b/ReferenceCode/Chipset/SystemAgent/AcpiTables/SaSsdt/SaSsdt.inf new file mode 100644 index 0000000..e97e019 --- /dev/null +++ b/ReferenceCode/Chipset/SystemAgent/AcpiTables/SaSsdt/SaSsdt.inf @@ -0,0 +1,69 @@ +## @file +# Component description file for the ACPI tables +# +#@copyright +# Copyright (c) 2012 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# This file contains an 'Intel Peripheral Driver' and uniquely +# identified as "Intel Reference Module" and is +# licensed for Intel CPUs and chipsets under the terms of your +# license agreement with Intel or your vendor. This file may +# be modified by the user, subject to additional terms of the +# license agreement +# + + +[defines] +BASE_NAME = SaSsdt +FILE_GUID = AAA99A23-13B6-4C31-BB8B-299E8EC04FA4 +COMPONENT_TYPE = ACPITABLE +FFS_EXT = .ffs + +[sources.common] + SaSsdt.ASL + +[libraries.common] + +[includes.common] + . + $(EFI_SOURCE) + $(EFI_SOURCE)/Include + $(EFI_SOURCE)/$(PROJECT_SA_ROOT)/Include + $(EDK_SOURCE)/Foundation/Efi + $(EDK_SOURCE)/Foundation/Include + $(EDK_SOURCE)/Foundation/Efi/Include + $(EDK_SOURCE)/Foundation/Framework/Include + $(EFI_SOURCE)/Include/IndustryStandard + $(EDK_SOURCE)/Foundation/Include/IndustryStandard + $(EDK_SOURCE)/Foundation/Library/Dxe/Include + $(EDK_SOURCE)/Foundation + $(EDK_SOURCE)/Foundation/Framework +# +# Typically the sample code referenced will be available in the code base already +# So keep this include at the end to defer to the source base definition +# and only use the sample code definition if source base does not include these files. +# +# $(EFI_SOURCE)/$(PROJECT_SA_ROOT)/SampleCode/Include + +# +# Edk II Glue Library, some hearder are included by R9 header so have to include +# + + $(EFI_SOURCE) + $(EFI_SOURCE)/Framework + $(EDK_SOURCE)/Foundation + $(EDK_SOURCE)/Foundation/Framework + $(EDK_SOURCE)/Foundation/Include/IndustryStandard + $(EDK_SOURCE)/Foundation/Core/Dxe + $(EDK_SOURCE)/Foundation/Include/Pei + $(EDK_SOURCE)/Foundation/Library/Dxe/Include + $(EDK_SOURCE)/Foundation/Library/EdkIIGlueLib/Include + +[nmake.common] diff --git a/ReferenceCode/Chipset/SystemAgent/AcpiTables/SaSsdt/SaSsdtTables.cif b/ReferenceCode/Chipset/SystemAgent/AcpiTables/SaSsdt/SaSsdtTables.cif new file mode 100644 index 0000000..ef4ae0c --- /dev/null +++ b/ReferenceCode/Chipset/SystemAgent/AcpiTables/SaSsdt/SaSsdtTables.cif @@ -0,0 +1,19 @@ +<component> + name = "SaSsdtTables" + category = ModulePart + LocalRoot = "ReferenceCode\Chipset\SystemAgent\AcpiTables\SaSsdt\" + RefName = "SaSsdtTables" +[files] +"IgdOGBDA.ASL" +"IgdOMOBF.ASL" +"IgdOpRn.ASL" +"IgdOSBCB.ASL" +"INTELGFX.ASL" +"Sa.asl" +"SaPcieDsm.asl" +"SaSsdt.asl" +"SaSsdt.inf" +"SaSsdt_Edk.inf" +"SaSsdtTables.mak" +"SaSsdtTables.sdl" +<endComponent> diff --git a/ReferenceCode/Chipset/SystemAgent/AcpiTables/SaSsdt/SaSsdtTables.mak b/ReferenceCode/Chipset/SystemAgent/AcpiTables/SaSsdt/SaSsdtTables.mak new file mode 100644 index 0000000..e44f223 --- /dev/null +++ b/ReferenceCode/Chipset/SystemAgent/AcpiTables/SaSsdt/SaSsdtTables.mak @@ -0,0 +1,57 @@ +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2011, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* + +#************************************************************************* +#<AMI_FHDR_START> +# +# Name: SgAcpiTables.mak +# +# Description: MAK file for the ModulePart:SgAcpiTables +# +# +#<AMI_FHDR_END> +#************************************************************************* +all : BuildSaSsdt + +BuildSaSsdt : $(BUILD_DIR)\SaSsdt.ffs + +#----------------------------------------------------------------------- +# ASL compiler definition +#----------------------------------------------------------------------- +IASL = $(SILENT)iasl4.exe +#----------------------------------------------------------------------- +$(BUILD_DIR)\SaSsdt.aml : $(INTEL_SASSDT_ASL_FILE) + $(CP) /FI$(BUILD_DIR)\tokenasl.h $(INTEL_IgdOGBDA_ASL_FILE) > $(BUILD_DIR)\IgdOGBDA.asl + $(CP) /FI$(BUILD_DIR)\tokenasl.h $(INTEL_IgdOMOBF_ASL_FILE) > $(BUILD_DIR)\IgdOMOBF.asl + $(CP) /FI$(BUILD_DIR)\tokenasl.h $(INTEL_IgdOPRN_ASL_FILE) > $(BUILD_DIR)\IgdOPRN.asl + $(CP) /FI$(BUILD_DIR)\tokenasl.h $(INTEL_IgdOSBCB_ASL_FILE) > $(BUILD_DIR)\IgdOSBCB.asl + $(CP) /FI$(BUILD_DIR)\tokenasl.h $(INTEL_INTELGFX_ASL_FILE) > $(BUILD_DIR)\INTELGFX.asl + $(CP) /FI$(BUILD_DIR)\tokenasl.h $(INTEL_SA_ASL_FILE) > $(BUILD_DIR)\SA.asl + $(CP) /FI$(BUILD_DIR)\tokenasl.h $(INTEL_SAPCIEDSM_ASL_FILE) > $(BUILD_DIR)\SAPCIEDSM.asl + $(CP) /FI$(BUILD_DIR)\tokenasl.h $(INTEL_SASSDT_ASL_FILE) > $(BUILD_DIR)\SASSDT.asl + $(ASLEXPANDER) $(BUILD_DIR)\SASSDT.asl $(BUILD_DIR)\SASSDT_BUILD.asl $(BUILD_DIR) + $(IASL) -p $(BUILD_DIR)\SaSsdt.aml $(BUILD_DIR)\SASSDT_BUILD.asl + + +$(BUILD_DIR)\SaSsdt.sec: $(BUILD_DIR)\SaSsdt.aml + $(GENSECTION) -I $*.aml -O $@ -S EFI_SECTION_RAW + +$(BUILD_DIR)\SaSsdt.ffs: $(BUILD_DIR)\SaSsdt.sec $(SaSsdtTables_DIR)\SaSsdtTables.mak + $(MAKE) /f Core\FFS.mak \ + BUILD_DIR=$(BUILD_DIR) \ + GUID=AAA99A23-13B6-4C31-BB8B-299E8EC04FA4\ + TYPE=EFI_FV_FILETYPE_FREEFORM \ + FFS_CHECKSUM=1\ + RAWFILE=$(BUILD_DIR)\SaSsdt.sec FFSFILE=$(BUILD_DIR)\SaSsdt.ffs COMPRESS=0 NAME=SaSsdt + diff --git a/ReferenceCode/Chipset/SystemAgent/AcpiTables/SaSsdt/SaSsdtTables.sdl b/ReferenceCode/Chipset/SystemAgent/AcpiTables/SaSsdt/SaSsdtTables.sdl new file mode 100644 index 0000000..6e0c223 --- /dev/null +++ b/ReferenceCode/Chipset/SystemAgent/AcpiTables/SaSsdt/SaSsdtTables.sdl @@ -0,0 +1,104 @@ +TOKEN + Name = "SaSsdtTables_SUPPORT" + Value = "1" + TokenType = Boolean + TargetEQU = Yes + TargetMAK = Yes + Master = Yes + Help = "Main switch to enable SaSsdtTables support in Project" +End + +TOKEN + Name = "Remove_SaSsdt_Data_To_Dsdt" + Value = "0" + TokenType = Boolean + TargetEQU = Yes + TargetMAK = Yes + TargetH = Yes + Help = "Remove related SaSsdt acpi data to DSDT" +End + +ELINK + Name = "/D Remove_SaSsdt_Data_To_Dsdt" + Parent = "INTEL_SA_RC_FLAGS" + Token = "Remove_SaSsdt_Data_To_Dsdt" "=" "1" + InvokeOrder = AfterParent +End + +MODULE + Help = "Includes SgAcpiTables.mak to Project" + File = "SaSsdtTables.mak" +End + +PATH + Name = "SaSsdtTables_DIR" +End + +ELINK + Name = "$(SaSsdtTables_DIR)\Sa.asl" + Parent = "INTEL_GENERIC_ASL" + Token = "Remove_SaSsdt_Data_To_Dsdt" "=" "1" + InvokeOrder = AfterParent +End + +TOKEN + Name = "INTEL_IgdOGBDA_ASL_FILE" + Value = "$(SaSsdtTables_DIR)\IgdOGBDA.asl" + TokenType = Expression + TargetMAK = Yes +End + +TOKEN + Name = "INTEL_IgdOMOBF_ASL_FILE" + Value = "$(SaSsdtTables_DIR)\IgdOMOBF.asl" + TokenType = Expression + TargetMAK = Yes +End + +TOKEN + Name = "INTEL_IgdOPRN_ASL_FILE" + Value = "$(SaSsdtTables_DIR)\IgdOPRN.asl" + TokenType = Expression + TargetMAK = Yes +End + +TOKEN + Name = "INTEL_IgdOSBCB_ASL_FILE" + Value = "$(SaSsdtTables_DIR)\IgdOSBCB.asl" + TokenType = Expression + TargetMAK = Yes +End + +TOKEN + Name = "INTEL_INTELGFX_ASL_FILE" + Value = "$(SaSsdtTables_DIR)\INTELGFX.asl" + TokenType = Expression + TargetMAK = Yes +End + +TOKEN + Name = "INTEL_SA_ASL_FILE" + Value = "$(SaSsdtTables_DIR)\SA.asl" + TokenType = Expression + TargetMAK = Yes +End + +TOKEN + Name = "INTEL_SAPCIEDSM_ASL_FILE" + Value = "$(SaSsdtTables_DIR)\SAPCIEDSM.asl" + TokenType = Expression + TargetMAK = Yes +End + +TOKEN + Name = "INTEL_SASSDT_ASL_FILE" + Value = "$(SaSsdtTables_DIR)\SASSDT.asl" + TokenType = Expression + TargetMAK = Yes +End + +ELINK + Name = "$(BUILD_DIR)\SaSsdt.ffs" + Parent = "FV_MAIN" + InvokeOrder = AfterParent +End diff --git a/ReferenceCode/Chipset/SystemAgent/AcpiTables/SaSsdt/SaSsdt_Edk.inf b/ReferenceCode/Chipset/SystemAgent/AcpiTables/SaSsdt/SaSsdt_Edk.inf new file mode 100644 index 0000000..4ef6ff6 --- /dev/null +++ b/ReferenceCode/Chipset/SystemAgent/AcpiTables/SaSsdt/SaSsdt_Edk.inf @@ -0,0 +1,76 @@ +## @file +# Component description file for the ACPI tables (for EDK1117) +# +#@copyright +# Copyright (c) 2012 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# This file contains an 'Intel Peripheral Driver' and uniquely +# identified as "Intel Reference Module" and is +# licensed for Intel CPUs and chipsets under the terms of your +# license agreement with Intel or your vendor. This file may +# be modified by the user, subject to additional terms of the +# license agreement +# + + +[defines] +BASE_NAME = SaSsdt +FILE_GUID = AAA99A23-13B6-4C31-BB8B-299E8EC04FA4 +COMPONENT_TYPE = SA_SSDT_ACPITABLE +FFS_EXT = .ffs + +[sources.common] + SaSsdt.ASL + Sa.asl + IntelGfx.asl + IgdOpRn.asl + IgdOGBDA.asl + IgdOMOBF.asl + IgdOSBCB.asl + SaPcieDsm.asl + +[libraries.common] + +[includes.common] + . + $(EFI_SOURCE) + $(EFI_SOURCE)/Include + $(EFI_SOURCE)/$(PROJECT_SA_ROOT)/Include + $(EDK_SOURCE)/Foundation/Efi + $(EDK_SOURCE)/Foundation/Include + $(EDK_SOURCE)/Foundation/Efi/Include + $(EDK_SOURCE)/Foundation/Framework/Include + $(EFI_SOURCE)/Include/IndustryStandard + $(EDK_SOURCE)/Foundation/Include/IndustryStandard + $(EDK_SOURCE)/Foundation/Library/Dxe/Include + $(EDK_SOURCE)/Foundation + $(EDK_SOURCE)/Foundation/Framework +# +# Typically the sample code referenced will be available in the code base already +# So keep this include at the end to defer to the source base definition +# and only use the sample code definition if source base does not include these files. +# +# $(EFI_SOURCE)/$(PROJECT_SA_ROOT)/SampleCode/Include + +# +# Edk II Glue Library, some hearder are included by R9 header so have to include +# + + $(EFI_SOURCE) + $(EFI_SOURCE)/Framework + $(EDK_SOURCE)/Foundation + $(EDK_SOURCE)/Foundation/Framework + $(EDK_SOURCE)/Foundation/Include/IndustryStandard + $(EDK_SOURCE)/Foundation/Core/Dxe + $(EDK_SOURCE)/Foundation/Include/Pei + $(EDK_SOURCE)/Foundation/Library/Dxe/Include + $(EDK_SOURCE)/Foundation/Library/EdkIIGlueLib/Include + +[nmake.common] |