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Create a HII menu option to choose between device tree and ACPI platform
descriptions. Note that the option is only active if PCIe compatibility
mode is enabled.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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The ACPI/Linux code does not cope very well with I/O BAR windows that
involve type translation and address translation. In particular, the
secondary I/O window we implement on SynQuacer:
I/O 0x10000 ... 0x1ffff -> 0x77f00000
is misinterpreted by Linux, and results in the MMIO range starting at
0x77f10000 to be mapped for I/O port access to this range.
This can be mitigated by using the same bus range for I/O port access
on both RCs., i.e., [0x0 ... 0xffff]. This configuration can be represented
using both DT and ACPI, and will work as expected in Linux.
Now that the generic PCI host bridge driver has gained support for address
translation, we can actually support this configuration seamlessly in UEFI
as well, by applying an offset to the second I/O window to make it appear
adjacent to the first one in the CPU view of the I/O space.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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Fix the static B/D/F specifiers that refer to the pair of x1 PCIe slots
on the DeveloperBox PCB. The current configuration caused user-configurable
settings for slots 1/2 to apply to the incorrect one.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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Implement support for the SynQuacer eMMC controller. This involves an
implementation of the SD/MMC override protocol to handle a couple of
quirks that would otherwise prevent this IP from being driven by the
generic SDHCI driver.
Also, add a HII page to the PlatformDxe driver that allows eMMC support
to be enabled, and wire it up for both DeveloperBox and EVB.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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Even though the ARM ARM quite clearly states that the CNTFRQ field of
each MMIO timer frame should be a read-only alias of the CNTFRQ field
of the base frame, the SynQuacer SoC implements it as a register that
is programmable separately.
So let's program it from the hardware rather than overriding the
frequency using a DT property.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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Add menu options to the SynQuacer Platform menu screen to limit the
maximum PCIe link speed for each slot individually. This may be useful
to work around potential PCIe issues.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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As it turns out, it is surprisingly easy to configure both the NETSEC
and eMMC devices as cache coherent for DMA, given that they are both
behind the same SMMU which is already configured in passthrough mode
by the firmware running on the SCP.
So update the static SMMU configuration to make memory accesses performed
by these devices inner shareable inner/outer writeback cacheable, which
makes them cache coherent with the CPUs.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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Add the drivers, library resolutions and PCD settings to enable RTC
support on DeveloperBox. Also, update PlatformDxe to register the
non-discoverable device handles for both I2C controllers.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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Create a specialized PlatformPeiLib implementation that invokes the
platform specific firmware interface (currently, just a data structure
left in SRAM) to set the ARM standard PcdSystemMemoryBase|Size PCDs,
and expose the information via a newly added DramInfo PPI.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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Add a package .DEC description for SynQuacer with an [Includes]
section, and add header files containing descriptions of the
platform's memory map and PCIe configuration. No code yet.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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