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| author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2019-08-20 10:48:34 +0100 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2019-09-06 11:53:28 +0000 |
| commit | 2cac191491bbce22383d4fb81ea694e656b3c294 (patch) | |
| tree | 27e819a930c79dff6754de37062a0092ca9e798a /src/arch/arm/isa.cc | |
| parent | 1768c47bc4fc00e89601ad03c9091c9b949a6c97 (diff) | |
| download | gem5-2cac191491bbce22383d4fb81ea694e656b3c294.tar.xz | |
arch-arm: Fix read/setMiscReg for AArch32 GICv3 ICC regs
The readMiscReg/setMiscReg methods were not forwarding register
reads/writes to the cpu interface when in AArch32.
Change-Id: Ide983e793b8033a88d31fe6ea87eaeffe9b093f5
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20611
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/arch/arm/isa.cc')
| -rw-r--r-- | src/arch/arm/isa.cc | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc index 299698d3d..b95710506 100644 --- a/src/arch/arm/isa.cc +++ b/src/arch/arm/isa.cc @@ -737,6 +737,7 @@ ISA::readMiscReg(int misc_reg, ThreadContext *tc) case MISCREG_CNTVOFF_EL2 ... MISCREG_CNTPS_CVAL_EL1: return getGenericTimer(tc).readMiscReg(misc_reg); + case MISCREG_ICC_AP0R0 ... MISCREG_ICH_LRC15: case MISCREG_ICC_PMR_EL1 ... MISCREG_ICC_IGRPEN1_EL3: case MISCREG_ICH_AP0R0_EL2 ... MISCREG_ICH_LR15_EL2: return getGICv3CPUInterface(tc).readMiscReg(misc_reg); @@ -2069,6 +2070,7 @@ ISA::setMiscReg(int misc_reg, RegVal val, ThreadContext *tc) case MISCREG_CNTVOFF_EL2 ... MISCREG_CNTPS_CVAL_EL1: getGenericTimer(tc).setMiscReg(misc_reg, newVal); break; + case MISCREG_ICC_AP0R0 ... MISCREG_ICH_LRC15: case MISCREG_ICC_PMR_EL1 ... MISCREG_ICC_IGRPEN1_EL3: case MISCREG_ICH_AP0R0_EL2 ... MISCREG_ICH_LR15_EL2: getGICv3CPUInterface(tc).setMiscReg(misc_reg, newVal); |