summaryrefslogtreecommitdiff
path: root/src/cpu/base_dyn_inst.hh
diff options
context:
space:
mode:
authorIru Cai <mytbk920423@gmail.com>2019-04-03 10:29:37 +0800
committerIru Cai <mytbk920423@gmail.com>2019-04-03 10:55:39 +0800
commitf76b874533045543e56a69c1b5d75b34fbc8a888 (patch)
treec7f2948cf916ff938a713b6856cec789cb5f6982 /src/cpu/base_dyn_inst.hh
parentb28522528109f87d9420e59a31cef88a045ed0e6 (diff)
downloadgem5-f76b874533045543e56a69c1b5d75b34fbc8a888.tar.xz
check loads using tainted registers, set USL dst as tainted
Diffstat (limited to 'src/cpu/base_dyn_inst.hh')
-rw-r--r--src/cpu/base_dyn_inst.hh13
1 files changed, 12 insertions, 1 deletions
diff --git a/src/cpu/base_dyn_inst.hh b/src/cpu/base_dyn_inst.hh
index 4d8014445..756a5aa9f 100644
--- a/src/cpu/base_dyn_inst.hh
+++ b/src/cpu/base_dyn_inst.hh
@@ -480,11 +480,22 @@ class BaseDynInst : public ExecContext, public RefCounted
void taintDestRegs(void)
{
- for (auto dstreg: _destRegIdx) {
+ for (size_t i = 0; i < numDestRegs(); i++) {
+ auto dstreg = _destRegIdx[i];
cpu->setTaint(dstreg);
}
}
+ bool srcTainted(void)
+ {
+ bool result = false;
+ for (size_t i = 0; i < numSrcRegs(); i++) {
+ auto src = _srcRegIdx[i];
+ result |= cpu->regTainted(src);
+ }
+ return result;
+ }
+
/** Renames a source logical register to the physical register which
* has/will produce that logical register's result.
* @todo: add in whether or not the source register is ready.