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| author | Timothy M. Jones <tjones1@inf.ed.ac.uk> | 2010-07-22 18:52:02 +0100 |
|---|---|---|
| committer | Timothy M. Jones <tjones1@inf.ed.ac.uk> | 2010-07-22 18:52:02 +0100 |
| commit | e50a880297f13817200f4e74272ad1cf3194d401 (patch) | |
| tree | 5b3eebee5e2edc8fc3c3d221009b2b4a734977f7 /src/cpu/o3/lsq_unit.hh | |
| parent | 0d301ca4c401ced27443711c34f37de60533e20c (diff) | |
| download | gem5-e50a880297f13817200f4e74272ad1cf3194d401.tar.xz | |
O3CPU: Fix a bug where stores in the cpu where never marked as split.
Diffstat (limited to 'src/cpu/o3/lsq_unit.hh')
| -rw-r--r-- | src/cpu/o3/lsq_unit.hh | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/cpu/o3/lsq_unit.hh b/src/cpu/o3/lsq_unit.hh index cf51f8eab..7b8b1e2e3 100644 --- a/src/cpu/o3/lsq_unit.hh +++ b/src/cpu/o3/lsq_unit.hh @@ -822,6 +822,12 @@ LSQUnit<Impl>::write(Request *req, Request *sreqLow, Request *sreqHigh, storeQueue[store_idx].sreqLow = sreqLow; storeQueue[store_idx].sreqHigh = sreqHigh; storeQueue[store_idx].size = sizeof(T); + + // Split stores can only occur in ISAs with unaligned memory accesses. If + // a store request has been split, sreqLow and sreqHigh will be non-null. + if (TheISA::HasUnalignedMemAcc && sreqLow) { + storeQueue[store_idx].isSplit = true; + } assert(sizeof(T) <= sizeof(storeQueue[store_idx].data)); T gData = htog(data); |