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authorSteve Reinhardt <stever@eecs.umich.edu>2007-02-12 09:26:47 -0800
committerSteve Reinhardt <stever@eecs.umich.edu>2007-02-12 09:26:47 -0800
commitf78bc80bd75f6f4ebf080620b3aaeaee3b3e46cc (patch)
tree56134929157da94c31188651787a254e5b7b251b /src/cpu/simple/base.hh
parent6b37bb67101803f12b6ed2bef714af583d03f814 (diff)
downloadgem5-f78bc80bd75f6f4ebf080620b3aaeaee3b3e46cc.tar.xz
Move store conditional result checking from SimpleAtomicCpu write
function into Alpha ISA description. write now just generically returns a result value if the res pointer is non-null (which means we can only provide a res pointer if we expect a valid result value). --HG-- extra : convert_revision : fb1c315515787f5fbbf7d1af7e428bdbfe8148b8
Diffstat (limited to 'src/cpu/simple/base.hh')
-rw-r--r--src/cpu/simple/base.hh8
1 files changed, 8 insertions, 0 deletions
diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh
index c4853b916..a2b624139 100644
--- a/src/cpu/simple/base.hh
+++ b/src/cpu/simple/base.hh
@@ -329,6 +329,14 @@ class BaseSimpleCPU : public BaseCPU
return thread->setMiscRegWithEffect(reg_idx, val);
}
+ unsigned readStCondFailures() {
+ return thread->readStCondFailures();
+ }
+
+ void setStCondFailures(unsigned sc_failures) {
+ thread->setStCondFailures(sc_failures);
+ }
+
#if FULL_SYSTEM
Fault hwrei() { return thread->hwrei(); }
void ev5_trap(Fault fault) { fault->invoke(tc); }