diff options
| author | Gabe Black <gabeblack@google.com> | 2018-11-19 18:14:16 -0800 |
|---|---|---|
| committer | Gabe Black <gabeblack@google.com> | 2019-01-31 11:02:05 +0000 |
| commit | 5edfb67041ad1c246f4ceca147f06b9db3c0ecc3 (patch) | |
| tree | 22cc08624db8bfa11e4ea7c9817a864ebc2ea706 /src/cpu/simple | |
| parent | 25474167e5b247d1b91fbf802c5b396a63ae705e (diff) | |
| download | gem5-5edfb67041ad1c246f4ceca147f06b9db3c0ecc3.tar.xz | |
arch: cpu: Rename *FloatRegBits* to *FloatReg*.
Now that there's no plain FloatReg, there's no reason to distinguish
FloatRegBits with a special suffix since it's the only way to read or
write FP registers.
Change-Id: I3a60168c1d4302aed55223ea8e37b421f21efded
Reviewed-on: https://gem5-review.googlesource.com/c/14460
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Diffstat (limited to 'src/cpu/simple')
| -rw-r--r-- | src/cpu/simple/base.cc | 2 | ||||
| -rw-r--r-- | src/cpu/simple/exec_context.hh | 4 |
2 files changed, 3 insertions, 3 deletions
diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc index c597ac904..f71277d1c 100644 --- a/src/cpu/simple/base.cc +++ b/src/cpu/simple/base.cc @@ -493,7 +493,7 @@ BaseSimpleCPU::preExecute() // maintain $r0 semantics thread->setIntReg(ZeroReg, 0); #if THE_ISA == ALPHA_ISA - thread->setFloatRegBits(ZeroReg, 0); + thread->setFloatReg(ZeroReg, 0); #endif // ALPHA_ISA // check for instruction-count-based events diff --git a/src/cpu/simple/exec_context.hh b/src/cpu/simple/exec_context.hh index d2107b89a..3090f38a0 100644 --- a/src/cpu/simple/exec_context.hh +++ b/src/cpu/simple/exec_context.hh @@ -202,7 +202,7 @@ class SimpleExecContext : public ExecContext { numFpRegReads++; const RegId& reg = si->srcRegIdx(idx); assert(reg.isFloatReg()); - return thread->readFloatRegBits(reg.index()); + return thread->readFloatReg(reg.index()); } /** Sets the bits of a floating point register of single width @@ -213,7 +213,7 @@ class SimpleExecContext : public ExecContext { numFpRegWrites++; const RegId& reg = si->destRegIdx(idx); assert(reg.isFloatReg()); - thread->setFloatRegBits(reg.index(), val); + thread->setFloatReg(reg.index(), val); } /** Reads a vector register. */ |