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| author | Gabe Black <gabeblack@google.com> | 2018-11-21 16:20:57 -0800 |
|---|---|---|
| committer | Gabe Black <gabeblack@google.com> | 2019-02-01 01:22:19 +0000 |
| commit | a119a963240a35ab66a5baee3f77cfcd99c6bbbb (patch) | |
| tree | c883d37ed479e92c23d881a48b8f2abec469faf7 /src/cpu/simple | |
| parent | fbdf0b689eb31543292f52c71d14152d8ff1156a (diff) | |
| download | gem5-a119a963240a35ab66a5baee3f77cfcd99c6bbbb.tar.xz | |
cpu, arch: Replace the CCReg type with RegVal.
Most architectures weren't using the CCReg type, and in x86 and arm
it was already a uint64_t.
Change-Id: I0b3d5e690e6b31db6f2627f449c89bde0f6750a6
Reviewed-on: https://gem5-review.googlesource.com/c/14515
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Diffstat (limited to 'src/cpu/simple')
| -rw-r--r-- | src/cpu/simple/exec_context.hh | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/src/cpu/simple/exec_context.hh b/src/cpu/simple/exec_context.hh index 3090f38a0..0552dc0c6 100644 --- a/src/cpu/simple/exec_context.hh +++ b/src/cpu/simple/exec_context.hh @@ -60,7 +60,6 @@ class BaseSimpleCPU; class SimpleExecContext : public ExecContext { protected: - typedef TheISA::CCReg CCReg; using VecRegContainer = TheISA::VecRegContainer; using VecElem = TheISA::VecElem; @@ -365,7 +364,7 @@ class SimpleExecContext : public ExecContext { thread->setVecPredReg(reg, val); } - CCReg + RegVal readCCRegOperand(const StaticInst *si, int idx) override { numCCRegReads++; @@ -375,7 +374,7 @@ class SimpleExecContext : public ExecContext { } void - setCCRegOperand(const StaticInst *si, int idx, CCReg val) override + setCCRegOperand(const StaticInst *si, int idx, RegVal val) override { numCCRegWrites++; const RegId& reg = si->destRegIdx(idx); |