mem: Add a memory delay simulator

Add a memory system component that delays traffic. The base
functionality to delay packets is implemented in the abstract MemDelay
class. This class exposes three methods that control packet delays:

  * delayReq(pkt)
  * delayResp(pkt)
  * delaySnoopResp(pkt)

These methods should be specialized to implement delays for specific
packet types.

The class SimpleMemDelay uses the MemDelay base class to implement
constant delays for read/write requests and responses.

The intention is that these classes can be used for rapid prototyping
of components that add a small fixed delay and the same throughput as
the interconnect. I.e., any buffering done in the base class will be
small and proportional to the introduced delay.

Change-Id: I158cb85f20e32bfdbcbfed66a785b4b2dd47b628
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nicholas Lindsey <nicholas.lindsay@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/11521
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

1 files changed, 2 insertions, 0 deletions

diff --git a/src/mem/SConscript b/src/mem/SConscript
index 625eb0608..7c0d426d7 100644
--- a/src/mem/SConscript
+++ b/src/mem/SConscript
@@ -44,6 +44,7 @@ SimObject('SimpleMemory.py')
 SimObject('XBar.py')
 SimObject('HMCController.py')
 SimObject('SerialLink.py')
+SimObject('MemDelay.py')
 
 Source('abstract_mem.cc')
 Source('addr_mapper.cc')
@@ -68,6 +69,7 @@ Source('tport.cc')
 Source('xbar.cc')
 Source('hmc_controller.cc')
 Source('serial_link.cc')
+Source('mem_delay.cc')
 
 if env['TARGET_ISA'] != 'null':
     Source('fs_translating_port_proxy.cc')