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path: root/src/mem/SConscript
AgeCommit message (Expand)Author
2019-09-21mem: Delete the now unused Message*Port classes.Gabe Black
2019-09-10mem: Mark MemObject as deprecated.Gabe Black
2019-08-23mem: Put gem5 protocols in their own directory.Gabe Black
2019-08-23mem: Split the various protocols out of the gem5 master/slave ports.Gabe Black
2019-05-29arm, mem: Move the SecurePortProxy subclass into it's own file.Gabe Black
2018-09-07mem: Add a QoS-aware Memory Controller typeMatteo Andreozzi
2018-06-28mem: Add a memory delay simulatorAndreas Sandberg
2018-01-23x86, mem: Rewrite the multilevel page table class.Gabe Black
2015-11-03mem: hmc: serial link modelErfan Azarkhish
2015-11-03mem: hmc: adds controllerErfan Azarkhish
2015-08-04mem: Move trace functionality from the CommMonitor to a probeAndreas Sandberg
2015-08-04mem: Redesign the stack distance calculator as a probeAndreas Sandberg
2014-12-23mem: Add a stack distance calculatorKanishk Sugand
2014-12-23mem: Add MemChecker and MemCheckerMonitorMarco Elver
2014-10-16mem: Add ExternalMaster and ExternalSlave portsAndrew Bardsley
2014-07-29mem: Add DRAMPower wrapping classOmar Naji
2014-09-20mem: Rename Bus to XBar to better reflect its behaviourAndreas Hansson
2014-09-20mem: Simple Snoop FilterStephan Diestelhorst
2014-08-28mem: adding architectural page table support for SE modeAlexandru
2014-06-30mem: DRAMPower trace outputAndreas Hansson
2014-05-09mem: Add DRAM power states to the controllerAndreas Hansson
2014-03-23mem: Rename SimpleDRAM to a more suitable DRAMCtrlAndreas Hansson
2014-03-23ruby: Move Ruby debug flags to ruby dir and remove stale optionsAndreas Hansson
2014-03-23mem: Include the DRAMSim2 wrapper in NULL buildAndreas Hansson
2014-02-18mem: Add a wrapped DRAMSim2 memory controllerAndreas Hansson
2013-11-01mem: Use the same timing calculation for DRAM read and writeAni Udipi
2013-09-04arch: Resurrect the NOISA build target and rename it NULLAndreas Hansson
2013-01-07mem: Add tracing support in the communication monitorAndreas Hansson
2012-12-11ruby: add a prefetcherNilay Vaish
2012-09-25mem: Add a gasket that allows memory ranges to be re-mapped.Ali Saidi
2012-09-21DRAM: Introduce SimpleDRAM to capture a high-level controllerAndreas Hansson
2012-08-22Bridge: Remove NACKs in the bridge and unify with packet queueAndreas Hansson
2012-07-10ruby: banked cache array resource modelBrad Beckmann
2012-07-10ruby: tag and data cache access supportJoel Hestness
2012-05-31Bus: Split the bus into a non-coherent and coherent busAndreas Hansson
2012-05-09MEM: Add the communication monitorAndreas Hansson
2012-04-06MEM: Enable multiple distributed generalized memoriesAndreas Hansson
2012-03-30MEM: Remove legacy DRAM in preparation for memory updatesAndreas Hansson
2012-03-22MEM: Split SimpleTimingPort into PacketQueue and portsAndreas Hansson
2012-02-24MEM: Move all read/write blob functions from Port to PortProxyAndreas Hansson
2012-01-28Merge with the main repo.Gabe Black
2012-01-16Merge yet again with the main repository.Gabe Black
2012-01-17MEM: Add port proxies instead of non-structural portsAndreas Hansson
2012-01-11Ruby Debug Flags: Remove one, add anotherNilay Vaish
2012-01-11Ruby: Add infrastructure for recording cache contentsNilay Vaish
2012-01-07Merge with main repository.Gabe Black
2011-11-14Ruby: Process packet instead of RubyRequest in SequencerNilay Vaish
2011-10-16SE/FS: Turn on the page table class in FS.Gabe Black
2011-10-16SE/FS: Build in the tport in FS mode.Gabe Black
2011-10-16SE/FS: Build/expose vport in SE mode.Gabe Black