gem5 - gem5

Age	Commit message (Expand)	Author
2018-08-10	cpu: Removed unnecessary file reg_class_impl.hh	Bradley Wang
2017-07-05	cpu: Added interface for vector reg file	Rekai Gonzalez-Alberquilla
2017-07-05	cpu: Simplify the rename interface and use RegId	Rekai Gonzalez-Alberquilla
2017-07-05	cpu: Physical register structural + flat indexing	Nathanael Premillieu
2017-07-05	arch, cpu: Architectural Register structural indexing	Nathanael Premillieu
2016-11-09	style: [patch 1/22] use /r/3648/ to reorganize includes	Brandon Potter
2015-07-28	revert 5af8f40d8f2c	Nilay Vaish
2015-07-26	cpu: implements vector registers	Nilay Vaish
2015-07-04	o3: correct the number of cc registers in rename map	Nilay Vaish
2014-11-14	arm: Fixes based on UBSan and static analysis	Andreas Hansson
2013-10-15	cpu: add a condition-code register class	Yasuko Eckert
2013-10-15	cpu/o3: clean up rename map and free list	Steve Reinhardt
2013-01-22	o3 cpu: fix zero reg problem	Andrea Pellegrini
2011-06-10	o3: missing newlines on some dprintfs	Korey Sewell
2011-04-15	trace: reimplement the DTRACE function so it doesn't use a vector	Nathan Binkert
2007-04-22	Make the floating point zero register special handling only apply for ALPHA.	Gabe Black
2007-03-23	A couple of minor fixes.	Kevin Lim
2006-12-20	don't use (*activeThreads).begin(), use activeThreads->blah().	Nathan Binkert
2006-06-02	Merge ktlim@zizzer:/bk/newmem	Kevin Lim
2006-05-31	Updated Authors from bk prs info	Ali Saidi
2006-05-30	Merge ktlim@zizzer:/bk/m5	Kevin Lim
2006-05-22	New directory structure:	Steve Reinhardt