gem5 - gem5

Age	Commit message (Expand)	Author
2019-05-18	arch, base, cpu, dev, mem, sim: Remove #if 0-ed out code.	Gabe Black
2019-05-14	cpu: Revamp saturating counters	Daniel
2019-02-05	cpu: Made TAGE a SimObject that can be used by other predictors	Jairo Balart
2017-12-04	misc: Rename misc.(hh\|cc) to logging.(hh\|cc)	Gabe Black
2016-11-09	style: [patch 1/22] use /r/3648/ to reorganize includes	Brandon Potter
2016-12-21	cpu: disallow speculative update of branch predictor tables (o3)	Arthur Perais
2016-04-05	cpu: Implement per-thread GHRs	Mitch Hayenga
2016-04-06	Revert power patch sets with unexpected interactions	Andreas Sandberg
2016-04-05	cpu: Implement per-thread GHRs	Curtis Dunham
2015-04-13	cpu: re-organizes the branch predictor structure.	Dibakar Gope
2013-01-24	branch predictor: move out of o3 and inorder cpus	Nilay Vaish ext:(%2C%20Timothy%20Jones%20%3Ctimothy.jones%40cl.cam.ac.uk%3E)
2012-02-13	BP: Fix several Branch Predictor issues.	Mrinmoy Ghosh
2011-04-15	trace: reimplement the DTRACE function so it doesn't use a vector	Nathan Binkert
2009-06-04	types: clean up types, especially signed vs unsigned	Nathan Binkert
2009-06-04	move: put predictor includes and cc files into the same place	Nathan Binkert