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authorIru Cai <mytbk920423@gmail.com>2019-10-30 15:44:39 +0800
committerIru Cai <mytbk920423@gmail.com>2019-10-30 15:44:39 +0800
commit63cf543b3cc4d6e21d680bde234f697a5588c66e (patch)
tree6b1ea4cd9525e1ebeee8fb5ed427127197707022 /include/dt-bindings/clock/r8a7794-cpg-mssr.h
parenta899a6c0ed9a3066557fb170850f977b6bd7366f (diff)
downloaduext4-63cf543b3cc4d6e21d680bde234f697a5588c66e.tar.xz
rm include/dt-bindings
Diffstat (limited to 'include/dt-bindings/clock/r8a7794-cpg-mssr.h')
-rw-r--r--include/dt-bindings/clock/r8a7794-cpg-mssr.h43
1 files changed, 0 insertions, 43 deletions
diff --git a/include/dt-bindings/clock/r8a7794-cpg-mssr.h b/include/dt-bindings/clock/r8a7794-cpg-mssr.h
deleted file mode 100644
index 6314e23..0000000
--- a/include/dt-bindings/clock/r8a7794-cpg-mssr.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+
- *
- * Copyright (C) 2015 Renesas Electronics Corp.
- */
-
-#ifndef __DT_BINDINGS_CLOCK_R8A7794_CPG_MSSR_H__
-#define __DT_BINDINGS_CLOCK_R8A7794_CPG_MSSR_H__
-
-#include <dt-bindings/clock/renesas-cpg-mssr.h>
-
-/* r8a7794 CPG Core Clocks */
-#define R8A7794_CLK_Z2 0
-#define R8A7794_CLK_ZG 1
-#define R8A7794_CLK_ZTR 2
-#define R8A7794_CLK_ZTRD2 3
-#define R8A7794_CLK_ZT 4
-#define R8A7794_CLK_ZX 5
-#define R8A7794_CLK_ZS 6
-#define R8A7794_CLK_HP 7
-#define R8A7794_CLK_I 8
-#define R8A7794_CLK_B 9
-#define R8A7794_CLK_LB 10
-#define R8A7794_CLK_P 11
-#define R8A7794_CLK_CL 12
-#define R8A7794_CLK_CP 13
-#define R8A7794_CLK_M2 14
-#define R8A7794_CLK_ADSP 15
-#define R8A7794_CLK_ZB3 16
-#define R8A7794_CLK_ZB3D2 17
-#define R8A7794_CLK_DDR 18
-#define R8A7794_CLK_SDH 19
-#define R8A7794_CLK_SD0 20
-#define R8A7794_CLK_SD2 21
-#define R8A7794_CLK_SD3 22
-#define R8A7794_CLK_MMC0 23
-#define R8A7794_CLK_MP 24
-#define R8A7794_CLK_QSPI 25
-#define R8A7794_CLK_CPEX 26
-#define R8A7794_CLK_RCAN 27
-#define R8A7794_CLK_R 28
-#define R8A7794_CLK_OSC 29
-
-#endif /* __DT_BINDINGS_CLOCK_R8A7794_CPG_MSSR_H__ */