diff options
| author | Iru Cai <mytbk920423@gmail.com> | 2019-10-30 15:38:10 +0800 |
|---|---|---|
| committer | Iru Cai <mytbk920423@gmail.com> | 2019-10-30 15:41:07 +0800 |
| commit | 08dd4564b1f5c3258caf6bfc4bdc77ead1b042d6 (patch) | |
| tree | 8c22427201972800453e6da9b8175e2bf730dc40 /arch/arm/include/asm/cache.h | |
| parent | 1de6c9a59765f804ba40ac69fb12220e43734115 (diff) | |
| download | uext4-08dd4564b1f5c3258caf6bfc4bdc77ead1b042d6.tar.xz | |
fix ARCH_DMA_MINALIGN mess
Diffstat (limited to 'arch/arm/include/asm/cache.h')
| -rw-r--r-- | arch/arm/include/asm/cache.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/arm/include/asm/cache.h b/arch/arm/include/asm/cache.h index 950ec1e..57e2149 100644 --- a/arch/arm/include/asm/cache.h +++ b/arch/arm/include/asm/cache.h @@ -47,6 +47,10 @@ void dram_bank_mmu_setup(int bank); * value than found in the L1 cache but this is OK to use in terms of * alignment. */ +#ifdef CONFIG_SYS_CACHELINE_SIZE #define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE +#else +#define ARCH_DMA_MINALIGN 64 /* should be enough */ +#endif #endif /* _ASM_CACHE_H */ |